1982_RCA_CMOS_Microprocessors_Memories_and_Peripherals 1982 RCA CMOS Microprocessors Memories And Peripherals
User Manual: 1982_RCA_CMOS_Microprocessors_Memories_and_Peripherals
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Solid
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Microprocessors. Memories. Peripherals
RCA CMOS LSI
Microprocessors, Memories, Peripherals
This DATABOOK contains full information on CMOS
LSI products (microprocessors, memories, and
peripherals) currently available from RCA Solid
State Division. An Index to Products provides a
complete listing of types.
The Index to Products is followed by several pages
of general product information that includes photographs showing the package options available for
RCA CMOS LSI products, a Product Overview that
summarizes the basic features and complement of
each category of products, and a Product Classification Chart that groups integrated circuits and
systems according to product type and intended
function. Next, a Cross-Reference Guide lists popular
memory integrated circuits supplied by other manufacturers together with a recommended RCA replacement type. The DATABOOK then includes a
general discussion of Operating and Handling
Considerations for CMOS Integrated Circuits.
Five separate data sections provide definitive ratings,
electrical characteristics, and user information for
the (1) 1800 series of microprocessors and microcomputers, (2) 1800 series memories, (3) 1800 series
peripherals, (4) general-purpose memories, and (5)
6805 series LSI products.
Within each data section, the data pages for individual integrated circuits are grouped in alphanumerical sequence of type numbers.
The DATABOOK also contains selected application
note abstracts on RCA LSI products and dimensional
outlines of all packages in which RCA LSI products
are supplied.
Table of Contents
General Guide to
RCA LSI Products
1800-Serles Microprocessors
and Microcomputers
1800-Serles Memories
1800-Serl.. Peripheral.
General-Purpose Memorle.
8805-S_. LSI Product.
Supplementary Information
RCA Sales Offices,
Authorized Distributors and
Manufacturers' Representatives
nOli
Solid
State
I
1
Somerville, NJ • Brussels • Paris • London
Hamburg. Sao Paulo • Hong Kong
~
Ii
I
I
E
a
I
E
•
Information furnished by RCA is believed to be accurate and reliable.
However, no responsibility is assumed by RCA for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of RCA.
The device data shown for some types are i'ndicated as preliminary,
advance, or objective. Preliminary data are intended for guidance
purposes in evaluating devices for equipment design. Such data are
shown for types currently being designe~ for inclusion in our
standard line of commercially available products. Advance or
ObJective data are intended for engineering evaluation of types in the
initial stages of design. The type designations and data are subject to
change, u,nless otherwise arranged. No obligations are assumed for
notice of change or future manufacture of these devices. For current
information on the status of preliminary or objective programs, please
contact your local RCA sales office.
Copyright 1982 by RCA Corporation
(All rights reserved under Pan-American
Copyright Convention)
Trademark{s)eRegistered
Marca{s) Registrada{s)
Printed in USAl10-82
2
General Guide to RCA LSI Productsll
Page
Index to Products ................... , ... . .. . . .... .. .... . ..... . ... .. . .. . .
Packages and Ordering Information......................................
Product Overview ........................ '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Classification Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross-Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Handling Considerations. .................................
4
6
7
8
9
10
3
RCA CMOS LSI Products
Index to Products
Part
No.
4
Page
No.
Description
CD4036A
CD4039A
CD4061A
CD40061
CD40061A
3764 x8 RAM
3764 x8 RAM
383 256 x 1 RAM
391 256 x 1RAM,
391 256 x 1 RAM
CD40114B
CDM5332
CDM5333
CDM6116-1
CDM6116-2
396
401
401
407
407
CDP1802A
CDP1802AC
CDP1802BC
CDP1804AC
14
14
36
56
16x4 RAM
4096 x 8 ROM
4096 x 8 ROM
2048 x 8 RAM
2048 x 8 RAM
Part
No.
CDP1854C
CDP1855
CDP1855C
CDP1856
CDP1856C
Page
No.
214
232
232
245
245
UART
8-Bit Programmable MDU
8-Bit Programmable MDU
4-Bit Bus Buffer/Separator
4-Bit Bus Buffer/Separator
1193
1053
1053
1192
1192
1116
1366
1366
CDP1857
CDP1857C
CDP1858
CDP1859
245
245
250
250
250
4-Bit Bus Buffer/Separator
4-Bit Bus Buffer/Separator
4-Bit Latch/Decoder
4-Bit Latch/Decoder
4-Bit Latch/Decoder
1192
1192
1127
1127
1127
CDP1859C
CDP1861C
CDP1862C
CDP1863
250
258
2,66
271
4-Bit Latch/Decoder
Video Display Controller
Color Generator Controller
8-Bit Progr'ble Frequency
Generator
271 8-Bit Progr'ble Frequency
Generator
1127
1223
1181
137~CDP1858C
1372
CDP1805C
8-Bit Microprocessor
1305
8-Bit Microprocessor
1305
8-Bit Microprocessor
1342
8-Bit Microcomp/ROM/RAM/
Ctr/Tmr
1371
84 8-Bit Microproc/RAM/Ctr/Tmr 1349
CDP1805AC
CDP1806C
CDP1806AC
CDP1821
CDP1821C
103
84
103
128
128
CDP1822
CDP1822C
CDP1823
CDP1823C
CDP1824
134256 x 4 RAM
134256 x 4 RAM
141 128 x 8 RAM
141 128 x 8 RAM
14732 x 8 RAM
1074
1074
1198
1198
1103
CDP1824C
CDP1826C
CDP1831
CDP1831C
CDP1832
14732 x8 RAM
15364 x8 RAM
160512 x 8 ROM
160512 x 8 ROM
164512 x 8 ROM
1103
1311
1104
1104
1145
CDP1832C
CDP1833
CDP1833BC
CDP1833C
CDP1834
164512 x 8 ROM
168 Mask-Progr'ble,
168 Mask-Progr'ble,
168 Mask-Progr'ble,
174 Mask-Progr'ble,
CDP1834C
CDP1835C
CDP1837C
CDP1851
CDP1851C
CDP1852
CDP1852C
CDP1853
CDP1853C
CDP1854
8-Bit Microprocessor
8-Bit Microproc/Ctr/Tmr
8-Bit Microprocessor
1K x 1 RAM
1K x 1 RAM
FII_
No.
File
No.
,613
613
786
1188
1188
1370
1349
1370
1200
1200
1K x 8 ROM
1K x 8 ROM
1K x 8 ROM
1K x 8 ROM
1145
1135
1135
1135
1143
174
177
183
190
190
Mask-Progr'ble, 1K x 8 ROM
Mask-Progr'ble, 2K x 8 ROM
Mask-Progr'ble, 4K x 8 ROM
Programmable 110
Programmable 1/0
1143
1267
1381
1056
1056
203
203
210
210
214
Byte-Wide 1/0 Port
Byte-Wide 110 Port
N-Bit 1 of 8 Decoder
N-Bit 1 of 8 Decoder
UART
1166
1166
1189
1189
1193
CDP1863C
Description
1179
1179
CDP1864C
CDP1866
CDP1866C
CDP1867
CDP1867C
277
286
286
286
286
PAL Video Display Controller
4-Bit Latch/Decoder
4-Bit Latch/Decoder
4-Bit Latch/Decoder
4-Bit Latch/Decoder
1196
1112
1112
1112
1112
CDP1868
CDP1868C
CDP1869
CDP1869C
CDP1870
286
286
295
295
295
4-Bit Latch/Decoder
4-Bit Latch/Decoder
Video Interface System
Video I nterface System
Video Interface System
1112
1112
1197
1197
1197
CDP187qC
CDP1871A
CDP1871AC
CDP1872C
CDP1873C
295
312
312
320
325
Video Interface System
Keyboard Encoder
Keyboard Encoder
8-Bit Input Port
1 of 8 Binary Decoder
1197
1374
1374
1255
1248
CDP1874C
CDP1875C
CDP1876
CDP1876C
CDP1877
320
320
285
295
329
8-Bit Input Port
8-Bit Output Port
Video interface System
Video Interface System
Progr'ble Interrupt Controller
1255
1255
1197
1197
1319
CDP1877C
CDP1878
CDP1878C
CDP1879
CDP1879C
329
338
338
351
351
Progr'ble Interrupt Controller
Dual Counter-Timer
Dual Counter-Timer
Real-Time Clock
Real-Time Clock
1319
1341
1341
1360
1360
CDP1881
CDP1881C
CDP1882
CDP18.,2C
CDP6402
365
365
365
365
367
6-Bit Latch/Decoder
6-Bit Latch/Decoder
6-Bit Latch/Decoder
6-Bit Latch/Decoder
UART
1367
1367
1367 ,
1367
1328
General Guide to RCA LSI Products
Index to Products (Cont'd)
Part
No.
CDP6402C
CDP65516
CDP6805E2
CDP6805F2
CDP6805G2
Page
No.
Description
File
No.
Part
No.
1328 MWS5101DL3
UART
1376 MWS5101EL2
2K x8 ROM
8-Bit Micropro/RAM/Ctr/Tmr 1363 MWS5101EL3
8-Bit Microcomp/ROM/RAM/
MWS5101ADL2
Ctr/Tmr
1369 MWS5101ADL3
503 8-Bit Microcomp/ROM/RAM/
MWS5101AEL2
1364 MWS5101AEL3
Ctr/Tmr
367
434
442
477
529 Real-Time Clock/RAM
CDP6818
547 Paraliellnterface
CDP6823
MWS5101DL2 412256 x 4 RAM
1375 MWS5114-1
1377 MWS5114-2
1106 MWS5114-3
412
412
256 x 4 RAM
256 x4 RAM
File
No.
1106
1106
412
419
419
419
419
256 x4 RAM
256 x 4 RAM
256 x 4 RAM
256x4 RAM
256x4 RAM
1106
1207
1207
1207
1207
426
426
426
1K x4 RAM
1K x 4 RAM
1Kx4 RAM
1325
1325
1325
Page
No.
Description
5
I
RCA CMOS LSI Products
Package and Ordering Information
Packages
D Suffix
Dual-In-Llne Size-Brazed Ceramic Packages
16-,18-,22-,24-,28-, and 40-lead versions
E Suffix
Plastic Dual-In-Llne Packages
D Suffix
Dual-In-Llne Welded-Seal Ceramic Packages
16- and 24-lead versions
K Suffix
24-Lead Ceramic Flat Pack
16-, 18-, 22-, 24-, and 40-lead versions
H Suffix Chip
CD4036A and CD4039A only
L SUFFIX - LEAD LESSCHIP-CARRIER CERAMIC
PACKAGE
Ordering Information
RCA CMOS microprocessor and memory integrated
circuits are available in one or more of the following
package styles and are identified by the Suffix Letters
indicated: dual-in-line size-brazed ceramic, dual-in-line
welded-seal ceramic, dual-in-line plastic, flat-pack
ceramic, lead less chip-carrier ceramic and in chip form.
The available package styles for any specific type are
given in the technical data for that type.
When ordering CMOS devices, it is important that the
appropriate suffix letter be affixed to the type number of
the device required. Forexample a CDP1802A in adual-inline ceramic package will be identified as the CDP1802AD.
6
PACKAGE
Dual-In-Line Welded-Seal or
Side-Brazed Ceramic
Dual-In-Line Plastic
Chip
Ceramic Flat Pack
(CD4036A and CD4039A only)
Ceramic Leadless Chip-Carrier
SUFFIX
LETTERS
D
E
H
K
L
General Guide to RCA LSI Products
Product Overview
RCA offers an all CMOS line of microprocessor, memory
and peripheral integrated circuits for use in a broad range
of diverse industrial, consumer, and militaro/ applications.
These devices offer the user all the advantages unique to
CMOS technology, including:
• Low power drain-makes CMOS integrated circuits
a natural choice for battery-operated systems,
battery backed-up systems, and systems in which
heat dissipation is a prime consideration.
• High nolaelmmunlty and wide operating temperature
range (_55° C to +125° C)-allows CMOS integrated
circuits to be used in the most demanding industrial
environments.
• Wide operating voltage range-reduces the need for
expensive regulated power supplies and thereby
allows the design engineer greater freedom to
concentrate on other aspects of system design.
CDP1800 Series
The RCA CDP1800 series offers the most complete line of
CMOS microprocessor and associated memory and
peripheral devices in the industry. The heart of the series
is the CDP1802A central processing unit (CPU). This unit,
which features CMOS register-based architecture, offers
16 internal registers to facilitate data manipulation and to
reduce the need for additional devices. The need for
external devices is even further reduced by use of an
on-Chip clock, DMA, and single-phase operation.
The CDP1804A microcomputer, currently under development, incorporates all the features of the CDP1802
augmented by additional hardware and increased performance capabilities. The additional hardware includes 2
kilobytes of ROM, a 64-byte RAM array, an 8-bit presettable
down-counter, and 32 additional software instruction,
which add subroutine call and return capability, enhance
data transfer manipulation, control counter modes and
interrupt arbitration, and provide BCD arithmetic capability.
Also available, are four other 8-bit microprocessors that
are functional and performance enhancements of the
CDP1802. The CDP180S and CDP180SA feature an onboard RAM and Counter/Timer. The CDP1806 and
CDP1806A have all the features of the CDP180S and
CDP180SA, respectively, but contain no on-board RAM.
The microcomputer and microprocessor devices use the
CMOS technology, designed on a single chip to maintain
low power drain.
RCA's large and expanding CDP1800-series LSI product
line offers the system designer exceptional flexibility in
hardware/software tradeoffs. In addition to microprocessors and microcomputers, this product line includes a
hardware multiply/divide unit (MDU), a programmable
I/O, video and keyboard interface circuits, latches and
decoders, a universal asynchronous receiver-transmitter
(UART), buffers, separators, and a broad complement of
directly interfaceable random-access memories (RAM's)
and read-only memories (ROM's).
CDP6800 Series
RCA also offers the CDP6800 family, a new series of pinfor-pi n replacements for the Motorola MC14680S Series of
CMOS microprocessors and peripherals primarily intended
for single-chip system applications. This family of parts
includes the CDP680SE2 8-bit microprocessor; the CDP680SF2 8-bit microcomputer (1 K ROM); the CDP680SG2
8-bit microcomputer (2K ROM); the CDP6818 Real-Time
Clock piuS RAM; the CDP6823 Parallel Interface 1/0; and
the CDP6SS16 2Kx8 Mask Programmable ROM. Additional
types will be added as they become available.
General-Purpose Memories
In addition to the memories designed to interface directly
with CDP1800-series microprocessors, RCA also offers a
line of general-purpose memories. These memories
include small scratchpad types in the CD4000 series, and
types in the MWSSOOO and COM series.
Leadless Chip Carrier
RCA's broad CMOS LSI product line now includes 12
standard CDP1800 series chips in lead less chip-carrier
packages. This basic chip set will consist of 20, 28, and
44-lead packages on SO-mil lead centers.
I
Extra-Value Product
Most RCA CDP1800 series parts are offered with burn-in
(EVP - Extra-Value Program) and are designated by an
"X", "Y" or "a" suffix added to the part number, e.g.,
COM5332EX.
Microprocessor Development Systems and
Mlcroboard Computer Modules
For the designers of microprocessor-based equipment
and in support of the CDP1800-series microprocessors
and associated memory and peripheral circuits, RCA
provides a strong and extensive line of systems, system
support components, system support software, system
modules (including Microboard milliwatt computer systems), and other development aids. The support-system
line includes development systems ranging from a minimum tape-based system to a full development system
having floppy-disk mass memory storage and operating
system software. This line also includes two evaluation
systems that serve as convenient learning tools fordesign,
hardware interfacing, and programming of microcomputer
systems. These systems can also be used as the basis for
breadboarding and prototyping user-designed microcomputer systems.
The RCA Microboard milliwatt computer systems form an
extensive line of fully coordinated products based on a
standard, simple-to-use 4.S by 7.S inch module. These
modules feature the inherent CMOS advantages of low
power consumption, wide operating voltage range, and
excellent noise immunity. The microboard systems are all
designed with the microboard universal backplane anq
are compatible with RCA Development Systems. Userdeveloped systems, therefore, can be readily developed
and easily modified.
As a convenient starting pOint for the user, two microboard
prototyping systems are available. These systems include
an expandable S-card chassis, a microboard computersystem module, a microboard control-and-display module,
ROM-based utility software, and ample room for userdesigned expansion. These prototyping systems enable
the user to reduce his hardware concerns to a minimum
and to maximize his efforts in custom design and software
development to meet the specific requirements of his
application.
The RCA Microsystems DATA BOOK SSD-270 provides
detailed information on RCA Microprocessor-based development systems and Microboard computer modules
and in the product description booklets and user manuals
available on specific types. (A list of these publications are
included at the end of this DATABOOK).
7
RCA CMOS LSI Products
Product Classification Chart
Part Number Description
Page No.
COP1802A
CDP1802B
CDP1805C
CDP1805AC
CDP1806C
CDP1806AC
CDP6805E2
8-Bit
8-Bit
8-Bit with
8-Bit with
8-Bit with
8-Bit with
8-Bit with
Timer
RAM
RAM
Counter-Timer
Counter-Timer
RAM/I-O/Counter-
14
36
84
103
84
103
477
503
CDP1821
CDP1822
CDP1823
CDP1824
CDP1826
CDM6116
lK xl
256x4
128 x 8
32 x8
64 x8
2Kx8
128
134
141
147
153
407
MWS5101
MWS5101A
MWS5114
256x4
256x4
lK x4
412
419
426
CD4036A
CD4039A
CD4061A
CD4OO61A
CD40114B
4x8
4x8
256 xl
256 xl
16 x 4
376
376
383
391
396
ROMs
CDM5333
CDP1831
CDP1832
CDP1833
CDP1833B
8
Mask-programmable ROM
512 x 8
Mask-programmable ROM
512 x 8
Mask-programmable ROM
lK x 8
Mask-programmable ROM
lK x8
CDP1837
Mask-programmable
lK x 8
Mask-programmable
2Kx 8
Mask-programmable
4Kx 8
Mask-programmable
2K x8
ROM
174
ROM
177
ROM
183
ROM
434
Input/Output Circuits
56
RAMs
Mask-programmable ROM
512 x 8
Mask-programmable ROM
512 x 8
CDP1835
442
Microcomputers
8-Bit with RAM/ROM/CounterTimer
CDP6805F2 8-Bit with RAM/ROM/I-O/
Counter-Timer
CDP6805G2 8-Bit with RAM/ROM/I-O/
Counter-Timer
CDP1834
CDP65516
CDP1804A
CDM5332
Page No.
Part Number Description
ROMs (Cont'd)
Microprocessors
401
401
160
CDP1851
CDP1852
CDP1853
CDP1855
CDP1856
CDP1857
CDP1858
CDP1859
CDP1861
CDP1862
CDP1863
CDP1864
CDP1866
CDP1867
CDP1868
CDP1869
CDP1870
CDP1871A
CDP1872
CDP1873
CDP1874
CDP1875
CDP1876
CDP1877
CDP1878
CDP1879
CDP1881
CDP1882
CDP6818
CDP6823
Programmable I/O (PIO)
Byte 110 - 8-Bit I/O Port
Decoder - 1 of 8
Multiply/Divide Unit (MDU)
Buffer - 4-Bit
Buffer - 4-Bit
Latch/Decoder - 4-Bit
Latch/Decoder - 4-Bit
Video Display, Controller
(VDC)
Color Generator Circuit
Programmable Frequency
Generator
PAL Video Display Controller
(VDC)
Latch/Decoder - 4-Bit
Latch/Decoder - 4-Bit
Latch/Decoder - 4-Bit
Video Interface System (VIS)
Video Interface System (VIS)
Keyboard Encoder, ASCII/Hex
High-Speed Input Port - 8-Bit
High-Speed Decoder - 1 of 8
High-Speed Input Port - 8-Bit
High-Speed Output Port
Video Interface System (VIS)
Programmable Interrupt
Controller
Dual Cqunter-Timer
Real Time Clock
Latch/Decoder - 4-Bit
Latch/Decoder - 4-Bit
Real Time Clock with RAM
Parallel Interface
190
203
210
323
245
250
250
250
UART
Industry Standard UART
214
367
258
266
271
277
286
286
286
295
295
312
320
325
320
320
295
329
338
351
365
365
529
547
164
168
UARTs
168
CDP1854A
CDP6402
General Guide to RCA LSI Products
Cross-Reference Guide
Note: An RCA equivalent type may not be identical with other manufacturer's type in every detail.
Refer to published data for further information.
r-.
Manufacturer/Type
Description
AMI
S5614
S5101
1K x4 RAM
256 x 4 RAM
RCA Nearest Pln-for-Pln
Equlv. Type Compatible
86508
FUJITSU
MB8414E
HARRIS
6402
HM6551
lK x 1 RAM
MWS5114
CDP18221
MWS5101
CDP1821
lK x 4 RAM
MWS5114
Yes
UART
256 x RAM
Yes
Yes
HM6508
HM6514
HITACHI
HM435101
lK x 1 RAM
lK x4 RAM
CDP6402
CDP18221
MWS5101
CDP1821
MW85114
CDP18221
MWS5101
MWS5114
Yes
CDP1802
CDP18221
MWS5101
CDP1824
CDP1831
CDP1832
CDP1833
CDP1834
CDP1835
CDP1851
CDP1852
CDP1853
Yes
Yes
CDP1854
CDP1855
CDP18561
CDP18571
CDP1858/
Ves
Yes
Yes
HM4334
HUGHES
HCMP1802
HCMP1822
256 x4 RAM
lKx4 RAM
CPU
256 x4 RAM
HCMP1824 32 x8 RAM
HCMP1831 512 x8 ROM
HCMP1832 512 x8 ROM
HCMP1833 1K x8 ROM
HCMP1834 lK x8 ROM
HCMP1835 2K x8 ROM
HCMP1851 1/0 Interface
HCMP1852
I/O Port
HCMP1853
N-Bit
Decoder
HCMP1854
UART
HCMP1855
8-Bit MDU
HCMP18561 Bus Buffer
1857
HCMP18581
Latchl
Decoder
1859
HCMP1861
VDC
HCMP1871
Keyboard
Encoder
CDP1859
CDP1861
CDP1871
Ves
Ves
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Ves
Manufacturer/Type
Description
INTERSIL
IM6402
IM6551
UART
256 x 4 RAM
IM6514C
1K x 4 RAM
IM6316
2K x8 ROM
MITEL
~D74SC138A Decoder
I/O Port
~D74SC373A
MOTOROLA
MCM6508
1K x 1 RAM
MCM5101 256 x4 RAM
MCM65114
NATIONAL
MM74C920
MM74C929
NEC
PD5101
PD44/6514
OKI
MSM5114
SSS
SCM5101
SCM5114
1K x 4 RAM
256 x4 RAM
1K x 1 RAM
256x4 RAM
CDP6402
CDP18221
MWS5101
MWS5114
CDP1835
Yes
Ves
CDP1873C
CDP1872C/
CDP1874C
Yes
No
CDP1821
CDP18221
MWS5101
MWS5114
Yes
Yes
CDP18221
MWS5101
CDP1821
No
Yes
No
Yes
Yes
1kx 4 RAM
1Kx4 RAM
MWS5114
Yes
256x4 RAM
CDP18221
MWS5101
MWS5114
CDP1835
Yes
CDP1835
No
MW85114
CDP18221
MWS5101
CDP1821
MW85114
Yes
Ves
1Kx4 RAM
2K x8 ROM
Yes
1K x 1 RAM
lK x4 RAM
I
Yes
CDP18221
MWS5101
MWS5114
SUPERTEX
CM1600
'2Kx8ROM
TOSHIBA
TC5514P
1Kx4 RAM
TC5501P
256 x4 RAM
TC5508P
TC5507AP
RCA Nearest Pln-for-Pln
Equlv. Type Compatible
Yes
Yes
No
No
No
Yes
Yes
9
RCA CMOS LSI Products
Operating and Handling Considerations
RCA CMOS Integrated Circuits
This Note summarizes important operating recommendations and precautions which should be followed in
the interest of maintaining the high standards of
performance of solid state devices.
The ratings included in RCA Solid State Devices data
bulletins are based on the Absolute Maximum Rating
System, which is defined by the following Industry
Standard (JEDEC) statement:
Absolute-Maximum Ratings are limiting values of
operating and environmental conditions applicable to
any electron device of a specified type as defined by its
published data, and should not be exceeded under the
worst probable conditions.
The device manufacturer chooses these values to provide
acceptable serviceability of the device, taking no
responsibility for equipment variations, environmental
variations, and the effects of changes in operating
conditions due to variations in device characteristics.
The equipment manufacturer should design so that
initially and throughout life no absolute-maximum value
for the intended service is exceeded with any device under
the worst probable operating conditions with respect to
supply voltage variation, equipment component variation,
equipment control adjustment, load variation, signal
variation, environmental conditions, and variations in
device characteristics.
It is recommended that equipment manufacturers
consult RCA whenever device applications involve
unusual electrical, mechanical or environmental operating
conditions.
General Considerations
The design flexibility provided by these devices makes
possible their use in a broad range of applications and
under many different operating conditions. When
incorporating these devices in equipment, therefore,
designers should anticipate the rare possiblity of device
failure and make certain that no safety hazard would
result from such an occurence.
The small size of most solid state products provides
obvious advantages to the designers of electronic
equipment. However, it should be recognized that these
compact devices usually provide only relatively small
insulation area between adjacent leads and the metal
envelope. When these devices are used in moist or
contaminated atmospheres, therefore, supplemental
protection must be provided to prevent the development
of electrical conductive paths across the relatively small
insulating surfaces.
The metal shells of the TO-5 style package often used
for integrated circuits usually has the substrate or most
negative supply voltage connected to the case. Therefore,
consideration should be given to the possibility of shock
hazard if the shells are to operate at voltages appreciably
above or below ground potential. In general, in any
application in which devices are operated at voltages
which may be dangerous to personnel, suitable
10
precautionary measures should be taken to prevent direct
contact with these devices.
Devices should not be connected into or disconnected
from circuits with th~ power on because high transient
voltages may cause permanent damage to the devices.
TESTING PRECAUTIONS
In common with many electronic components, solidstate devices should be operated and tested in circuits
which have reasonable values of current limiting
resistance, or other forms of effective current overload
protection. Failure to observe these precautions ~n
cause excessive internal heating of the device resulting in
destruction and/ or possible shattering of the enclosure.
Mounting
Integrated circuits are normally supplied with lead-tin
plated leads to facilitate soldering into circuit boards. In
those relatively few applications requiring welding of the
device leads, rather than soldering, the devices may be
obtained with gold or nickel plated Kovarll leads. * It
should be recognized that this type of plating will not
provide complete protection against lead corrosion in the
presence of high humidity and mechanical stress.
-Trade Name: Westinghouse Corp.
*Mil-M-385IOA, paragraph 3.5.6.I(a), lead' material
The aluminum-foil-lined cardboard "sandwich pack"
employed for static protection of the flat-pack also
provides some additional protection against lead
corrosion, and it is recommended that the devices be
stored in this package until used.
When integrated circuits are welded onto printed
circuit boards or equipment, the presence of moisture
between the closely spaced ,terminals can result in
conductive paths that may impair device performance in
high-impedance applications. It is therefore recommended
that conformal coatings or potting be provided as an
added measure of protection against moisture penetration.
In any method of mounting integrated circuits which
involves bending or forming of the device leads, it is
extremely important that the lead be supported and
clamped between the bend and the package seal, and that
bending be done with care to avoid damage to lead
plating. In no case should the radius of the bend be less
than the diameter of the lead, or in the case of rectangular
leads, such as those used in RCA 14-lead and l6-lead
flat-packages, less than the lead thickness. It is also
extremely important that the ends of the bent leads be
straight to assure proper insertion through the holes in
the printed-circuit board.
Handling
All CMOS gate inputs have a resistor/diode gate
protection network. All transmission gate inputs and all
outputs have diode protection provided by inherent p-n
junction diodes. These diode networks at input and
General Guide to RCA LSI Products
Operating and Handling Considerations (Cont'd)
output interfaces protect CMOS devices from gate-oxide
failure in handling environments where static discharge is
not excessive. In low-temperature, low-humidity
environments, improper handling may result in device
damage. See ICAN-6525, "Handling and Operating
Considerations for MOS Integrated Circuits", for proper
handling procedures.
is directly driven, the device output characteristics given
in the published data should be consulted to determine
the requirements for a safe operation below 200 milliwatts.
For detailed CMOS IC operating and handling
considerations, refer to Application Note ICAN-6525
"Handling and Operating Considerations for MOS
Integrated circuits".
Operating
IC Chips
Unused Inputs
All unused input leads must be connected to either Vss
or VDD, whichevyr is appropriate for the logic circuit
involved. A floating input on a high-current type not only
can result in faulty logic operation, but can cause the
maximum power dissipation of 200 milliwatts to be
exceeded and may result in damage to the device. Inputs
to these types, which are mounted on printed-circuit
boards that may temporarily become unterminated,
should have a pull-up resistor to Vss or VDD. A useful
range of values for such resistors is from 10 kilohms to I
megohm.
Input Signals
Signals shall not be applied to the inputs while the
device power supply is off unless the input current is
limited to a steady state value ofless than 10 milliamperes.
Input currents ofless than 10 milliamperes prevent device
damage; however, proper operation may be impaired as a
result of current flow through structural diode junctions.
Output Short Circuits
Shorting of outputs to Vss or VDD can damage many of
the higher-output-current CMOS types. In general, these
types can all be safely shorted for supplies up to 5 volts,
but will be damaged (depending on type) at higher powersupply voltages. For cases in which a short-circuit load,
such as the base of a p-n-p or an n-p-n bipolar transistor,
Integrated-circuit chips, unlike packaged devices, are
non-hermetic devices, normally fragile and small in
physical size, and therefore, require special handling
considerations as follows:
1. Chips must be stored under proper conditions to
insure that they are not subjected to a moist and/ or
contaminated atmosphere that could alter their
electrical, physical, or mechanical characteristics.
After the shipping container is opened, the chip must
be stored under the following conditions:
A. Storage temperature, 40° C.
B. Relatively humidity, 50% max.
C. Clean, dust-free environment.
2. The user must exercise proper care when handling
chips to prevent even the slightest physical damage to
the chip.
3. During mounting and lead bopding of chips the user
must use proper assembly techniques to obtain
proper electrical, thermal, and mechanical
peformance.
4. After the chip has been mounted and bonded, any
necessary procedure must be followed by the user to
insure that these non-hermetic chips are not subjected
to moist or contaminated atmosphere which might
cause the development of electrical conductive paths
across the realtively small insulating surfaces, In
addition, proper consideration must be given to the
protection of these devices from other harmful
environments which could conceivably adversely
affect their proper performance.
11
I
RCA CMOS LSI Products
12
General Guide to RCA LSI Products
1800-Series
Microprocessors and Microcomputers ~
Technical Data Ii
13
RCA CMOS LSI Products
CDP1802A, CDP1802AC
--...........
~
lim
etm
sc,
•
~
....
~
TN
,
IUS J:
MOl
....
........,
lUI ..
lUI'
MOO
. .I I
IUS I
IUSO
V<'hl
m
o.0'
Vsa
In
In
En
TOP ViEW
Terminal A ••lgnment
CMOS 8-Blt Microprocessor
Fealurel:
• Minimum instruction fetch-execute time of 5 ps
or 7.5 ps at VOO=5 V: 2.5 ps or 3.75 ps at VOO=10 V
• Any combination of standard RAM and ROM up to 65,536 bytes
• Operates with slow memories, up to 1 ps access time at fCL =4 MHz
• 8-bIt parallel organization with bidirectional
data bus and multiplexed address bus
• 16 x 16 matrix of registers for use as
multiple program counters, data pointers, or data registers
• On-chip OMA, interrupt, and flag inputs
• Programmable single-bit output port
• 91 easy-ta-use instructions
The RCA-CDP1802A LSI CMOS 8-bit register-oriented
central-processing unit (CPU) is designed for use as a
general-purpose computing or control element in a wide
range of stored-program systems or products.
chronous interface to memories and external controllers
for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting
devices operating in polled, interrupt-driven, or direct
memory-access modes.
The CDP1802A and CDP1802AC are functionally identical.
They differ in that the CDP1802A has a recommended
operating voltage range of 4 to 10.5 volts, and the
CDP1802AC a recommended operating voltage range of 4
to 6.5 volts.
These types are supplied in 40-lead dual-in-line sidebrazed ceramic packages (D suffix); and 4D-lead dual-inline plastic packages (E suffix). The CDP1802AC is also
available in chip form (H suffix).
The CDP1802A includes all of the circuits required for
fetching, interpreting, and executing instructions which
have been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to
facilitate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a syn-
R
II
111.0-7
-"
---.:>
....
COPI852
INPUT PORT CS2
DATA
...
....
U
\j
\)
111.0-7
llAO-4
NO
CSt
~:
DATA
5
ffi
COPI852
CS2
OUTPUT PORT
CLOCK
Miro
iiiiD
COPI802
8-81T CPU
iiiiD
COPI8"
I K-ROM
MwiI
iiiiii
+- f-- NI
+- f-- TPB
CEO
TPA
TPA
DATA
DATA
II
COPI824
32 8YTE RAM
-
\/
Ci
DATA
II
'2CIl-34."RI
Fig. 1 - Typical CDP1802A small microprocessor system.
14
•
1800-Series Microprocessors and Microcomputers
CDP1802A, CDP1802AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDD):
(All voltages referenced to VSS terminal)
CDP1802A .......•.................•.•..•........•.........•..........•............•...•..•..•...••.••••.•.••.•••-0.5 to +11 V
CDP1802AC .........•................•.••...........•...•....••....•..••..............••........•.•.••••••.•..•••• -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ...••.......••..•...........•...•.•..•.•........•.•••.......•••...•••.• -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ...••........••...................••.••...........................•..........••••• ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA=-40 to +60'C (PACKAGE TYPE E) .....•.........••..•.•.....• : ••........................••••..•.•..•..•••••..• 500 mW
For T A=+60 to +85°C (PACKAGE TYPE E) .....•...•..•...•.•........•..••.•.........•.•. Derate Linearly at 12 mW/'C to 200 mW
For T A=-55 to +1 OO'C (PACKAGE TYPE D) ....•........•.....•..•.•.............................••..••..•.•..•..•••.•• 500 mW
For TA=+100 to +125'C (PACKAGE TYPE D) .............................•.•............• Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA=FULL PACKAGE-TEMPERATURE RANGE •..................•.•........•...•.........•...•..•••••.....•.••••.• 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ...........................••...... , ............•..•....•••..................•.......•.•••..•• -55 to +125'C
PACKAGE TYPE E .........•.............. '" ..........................•..•...............•.••.•...••.•...••••• :. -40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) •..••..•.....•......•......•....................•..••••...••.•..•.•.•..•. -85 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16±1/32 in. (1.59±0.79 mm) from case for 10 s max. . ..•...••.•......•...•..•.........•••..•.•.•.....••.... +285'C
I
OPERATING CONDITIONS at TA=-40'C to +8S'C
For maximum reliability operating conditions should be selected so that operation is always within the following ranges:
.
LIMITS
CONDITIONS
CHARACTERISTIC
VCC1
(V)
DC Operating Voltage
Range
Input Voltage Range
Maximum Clock Input Rise
or Fall Time. tr.tf
-
-
-
4 to 10.5
5
Minimum Instruction Time 2
5
10
5
Maximum DMA Transfer
5
Rate
10
Maximum Clock Input
5
5
Frequency. fCl. Load
10
Capacitance (CL)=50 pF
CDP1802AC
Max.
Min.
CDP1802A
Max.
Min.
VDD
(V)
4
10.5
4
6.5
VSS
VDD
VSS
VDD
1
-
UNITS
V
4 to 10.5
5
10
10
5
10
10
5
10
10
5
4
2.5
DC
DC
DC
-
1
-
5
400
500
800
3.2
4
6.4
-
-
400
DC
3.2
-
-
-
-
lIS
KBytes
per
second
MHz
1VCC must never exceed VDD.
2Equals 2 machine cycles-one Fetch and one Execute operation for all instructions except Long Branch and Long Skip. which require 3
machine cycles-one Fetch and two Execute operations.
LOAD CAPACITANCE (ell· 50pF
,!! 8
1."
7
~
u
'" 6
'"
!!
~I
~IO<
~
M
~
~
~
~
e
~
~
~
AMBIENT TEMPERATURE (TA)--C
92(S-33866
Fig. 2 - Typical maximum clock frequency
as a function of temperature.
~
25
~
15
too 12$ leo 17e
LOAD CAPACITANCE (CL)- pF
200
92(S-29596
Fig. 3 - Typical transition time vs. load
capacitance.
15
RCA CMOS LSI Products
CDP1802A, CDP1802AC
STATIC ELECTRICAL CHARACTERISTICS at T A=-40 to +850 C, except as noted.
CONDITIONS
CHARACTERISTIC
Quiescent Device Current 100
Output Low Drive (Sink)
Current
(Except XTAL)
IOL
XTAL
IOL
Output High Drive (Source)
Current
IOH
lExceot XTAL)
XTAL
IOH
Output Voltage
Low-Level
VOl
Output Voltage
High Level
VOH
Input Low Voltage
VIL
Input High Voltage
VIH
CLEAR Input Voltage
Schmitt Hysteresis
VH
VOUT
(V)
Y,N
(V)
-
-
5
10
-
0.1
1
50
200
-
1
200
-
-
0.4
0.5
0,5
0,10
5
10
1.1
2.2
2.2
4.4
1.1
2.2
-
-
0.4
5
5
170
350
-
170
350
-
4.6
9.5
0,5
010
5
10
-0.27
-0.55
-0.55
-1.1
-0.27
-0.55
-
-
4.6
0
5
-125
-250
-
-125
-250
-
0,5
0,10
5
10
-
0
0.1
-
0.1
0.1
5
10
4.9
9.9
4.9
5
-
5
5,10
10
1.5
1
3
-
5
5,10
10
3.5
4
7
-
-
-
-
-
-
0,5
0,10
0
0
5
10
-
-
-
3.5
4
-
-
-
5
5,10
10
0.4
0.3
1.5
0.5
0.4
2
±10-4
±10-4
±10-4
±10-4
-
0.4
0.5
-
-
-
-
-
-
±10-4
±10-4
±1
0.5,4.5
0.5,4.5
1,9
liN
3-State Output Leakage
Current
lOUT
Operating Current,
IOO1~
f=3.2 MHz
0.5,4.5
0.5,4.5
19
-
0,5
0,10
5
10
0,5
0,10
0,5
0,10
5
10
-
-
-
5
-
VOO=VOR
VOO-2.4 V
CIN
COUT
"Typical values are for TA=25°C and nominal VOO.
~
4
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
~
~
4
~
~
~
~
GATE-lO-SOURCE VOLTAGE
Min.
Any
Input
Minimum Data Retention
Voltage
VOR
Data Retention Current
lOR
Input Capacitance
Output CapaCitance
-
-
Input Leakage Current
LIMITS
VCC,
VDO
(V)
CDP1802A
Typ."
Max.
-
±1
±1
Min.
±1
±1
-
2
4
-
-
2
2.4
-
0.05
-
5
10
7.5
15
-
CDP1802AC
Typ."
Max.
UNITS
mA
pA
mA
pA
1.5
-
V
-
-
±1
-
2
4
pA
mA
2
2.4
V
0.5
-
pA
5
10
7.5
15
pF
Llldle "00" at M(OOOO), CL =50 pF.
~
"
{VGS)~-5V
GATE-lO-SOURCE VOLTAGE (VGS)=IOV
~
z
-10
AMBIENT TEMPERATURE.-40 TO +85°C
+
§
15
~
r
10
~
6
92CS-31863
Fig. 4 - Minimum output high (sourco) current characteristics.
16
5
pA
AMBIENT TEMPERATURE =-40 TO+85°C
5V
2
~
7
DRAIN-lO-SOURCE VOLTAGE (Vos)-Y
92CS-31864
10
Fig. 5 - Minimum output low (sink) current characteristics.
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
.
I ' i AMBIENT TEMPERATURE (TA'-2S·C
~
Ii
I
\O-~~
2
~IOO.
",,, I
~~-
Il ~ •
-.It
~f2
r""
in
,/ r1
o,)':ct'~
I
•
"'"
'"
~ "•
~ •
>- •
!a
••~o¥
2
_o:~
. / /n"1",,+' /
..~
~O.I
NOTES!
,.,-
."'1
_cc
:~
0.01
. . . .rYr'" I
-'111 1
• • •• 2
i~~~c'~O?:~~~,m..018107)
0.1
4
••
I
2
•••
10
6lOAD CAPACITANCE 14CL)- pF
CLOCK INPUT FREQUENCY IfCd-M::CS.29!149
I
/
NOTE: ANV OUTPUT
EXCEPT X'fAL
RCS-ISS"
CL a !50pF
Fig. 6 - Typical power dissipation as a function of clock
frequency for BRANCH instruction and IDLE instruction.
Fig. 7 - Typical change in propagation delay as a
function of a change In load capacitance.
1/0 REQUESTS
MEMORY ADDRESS LINES 1/0 FLAGS ~
,---"'---..." ~
lID
CONTROL
MAG MA4 MA2 MAO TIfT
1R1AT
m
I
rnif
CONTROL AND
TIM ING LOGIC
R(EI.I RlEl.O
R(F).I R FI.o
8-BIT BIDIRECTIONAL DATA
Fig. 8 - CDP1802A block diagram.
CLOCK
ADDRESS~~~H~I~8Y~T~E~~
______~L~OW~8Y~T~E________~~H~I~8Y~T~E~-L______~L~OW~IY~T~E________.A__
T~~~
__________________
____________________r_lL__
________________________~r-1~
TN __________________~r-l~
~A------------£:::::~~~.~L~ID~IN~pSU~TJD~A~TA~::::]~L______~~=AL=I=D~DU~TP~U~T~~~A~____.Jt__
Fig. 9 - Basic dc timing waveforms, one instruction cycle.
17
RCA CMOS LSI Products
CDP1802A, CDP1802AC
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bus):
TPA, TPB (2 Timing Pulses):
a-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and I/O devices.
Positive pulses that occur once in each machine cycle (TPB
follows TPA). They are used by I/O controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the
higher-order byte of the 16-blt memory address. TPA is
suppressed in IDLE when the CPU is in the load mode.
NO to N2 (1/0) Lines):
Activated by an I/O instruction to signal the I/O control logic
of a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device
selection codes to the I/O devices (independently or
combined with the memory byte on the data bus when an I/O
instruction is being executed). The N bits are low at all times
except when an I/O instruction is being executed. During
this time their state is the same as the corresponding
bits in the N register.
The direction of data flow is defined in the I/O instruction by
bit N3 (internally) and is indicated by the level of the MRD
~DI.=VCC: Data from I/O to CPU and Memory
MRLl=VSS: Data from Memory to I/O
EF1 to
m
MAO to MA7 (8 Memory Address Lines):
In each cycle, the higher-order byte of a 16-bit CPU memory
address appears on the memory address lines MAO-7 first.
Those bits required by the memory system can be strobed
into external address latches by timing pulse TPA. The loworder byte oflhe 16-bit address appears on the address lines
after the termination of TPA. Latching of all a higher-order
address bits would permit a memory system of 64K bytes.
MWR (Write Pulse):
A negative pulse appearing in a memory-write cycle, after the
address lines have stabilized.
MRD (Read Level):
(4 Flags):
These inputs enable the I/O controllers to transfer status
information to the processor. The levels can be tested by the
conditional branch instructions. They can be used in conjunction with the INTERRUPT request line to establish
interrupt priorities. These flags can also be used by I/O
devices to "call the attention" of the processor, in which case
the program must routinely test the status of these flag(s).
The flag(s) are sampled at the beginning of every S1 cycle.
A low level on MRD indicates a memory read cycle. It can be
used to control three-state outputs from the addres.sed
memory which may have a common data input and output
bus. If a memory does not have a three-state high-impedance
output, MRD is useful for driving memory/bus separator
gates. It is also used to indicate the direction of data transfer
during an I/O instruction. For additional information see
Table I.
INTERRUPT, DMA-IN, DMA-OUT (3 I/O Requests)
Q:
These inputs are sampled by the CDP1a02A during the
interval between the leading edge of TPB and the leading
edge of TPA.
Single bit output from the CPU which can be set or reset
under program control. During SE~ or REO instruction
execution, 0 is set or reset between the trailing edge of TPA
and the leading edge of TPB.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
set to 1; interrupt enable is reset to 0 (inhibit); and instruction
execution is resumed. The interrupt action requires one
machine cycle (S3).
DMA Action: Finish executing current instruction; R(O)
pOints to memory area fordata transfer; data is loaded into or
read out of memory; and increment R(O).
Note: In the event of concurrent DMA and Interrupt requests,
DMA-IN has priority followed by DMA-OUT and then
Interrupt.
SCO, SC1, (2 State Code Lines):
These outputs indicate that the CPU is: 1) fetching an
instruction, or2) executing an instruction, or3) processing a
DMA request, or 4) acknowledging an interrupt request. The
levels of state code are tabulated below. All states are valid at
TPA. H=VCC, L=VSS.
State Type
SO
S1
S2
83
18
(Fetch)
(Execute)
(DMA)
(Interrupt)
State Code Lines
SC1
SCO
L
L
L
H
H
L
H
H
CLOCK:
Input for externally generated single-phase clock. A typical
clock frequency is 6.4 MHz at VCC= VDD=10 volts. The
clock is counted down internally to a clock pulses per
machine cycle.
XTAL:
Connection to be used with clock input terminal, for an
external crystal, if the on-chip oscillator is utilized. The
crystal is connected between terminals 1 and 39 (CLOCK
and XTAL) in paraliel with a resistance (10 megohms typ.).
Frequency trimming capacitors may be required at terminals
1 and 39. For additional information, see ICAN-6565.
WAIT, CLEAR (2 Control Lines):
Provide four control modes as listed in the following truth
table:
CLEAR
WAIT
MODE
L
L
LOAD
H
RESET
L
L
PAUSE
H
H
RUN
H
VDD, VSS, VCC (Power Levels):
The internal voltage supply VDD is isolated from the
Input/Output voltage supply VCC so that the processor may
operate at maximum speed while interfacing with peripheral
devices operating at lower voltage. VCC must be less than or
equal to VDD. All outputs swing from VSS to VCC. The
recommended input voltage swing is VSS to VCC.
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
ARCHITECTURE
The CPU block diagram is shown in Fig. 8. The principal
feature of this system is a register array (R) consisting of
sixteen 16-bit scratchpad registers. Individual registers in
the array (R) are designated (selected) by a4-bit binary
code·from one of the 4-bit registers labeled N, P, and X. The
contents of any register can be directed to anyone of the
following three paths:
1. the external memory (multiplexed, higher-order byte
first, on to 8 memory address lines);
2. the D register (either of the two bytes can be gated to
D);
3. the increment/decrement circuit where it is increased
or decreased by one and stored back in the selected
16-bit register.
The three paths, depending on the nature of the instruction,
may operate independently or in various combinations in
the same machine cycle.
With two exceptions, CPU instructions consist of two 8clock-pulse machine cycles. The first cycle is the fetch
cycle, and the second-and third if necessary-are execute
cycles. During the fetch cycle the four bits in the P
designator select one of the 16 registers R(P) as the current
program counter. The selected register R(P) contains the
address of the memory location from which the instruction
is to be fetched. When the Instruction is read out from the
memory, the higher-order 4 bits of the instruction byte are
loaded into the I register and the lower-order 4 bits into the
N register. The content of the program counter is automatically incremented by one so that R(P) is now "pointing"
to the next byte in the memory.
The X designator selects one of the 16 registers R(X) to
"point" to the memory for an operand (or data) in certain
ALU or I/O operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. designate one of the 16 registers in R to be acted upon
during register operations;
2. indicate to the 1/0 devices a command code or deviceselection code for peripherals;
3. indicate the specific operation to be executed during
the AL.U instructions, types of tests to be performed
during the Branch instructions, or the specific operation
required in a class of miscellaneous instructions (70-73
and 78-7B);
4. indicate the value to be loaded into P to designate a new
register to be used as the program counter R(P);
5. indicate the valueto be loaded intoXtodesignateanew
register to be. used as data pOinter R(X).
The registers in R can be assigned by a programmer in three
different ways: as program counters, as data pointers, or as
scratchpad locations (data registers) to hold two bytes of
data.
Program Counter.
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other
registers in R can be used as subroutine program counters.
By a single instruction the contents of the P register can be
changed to effect a "call" to a subroutine. When interrupts
are being serviced, register R(1) is used as the program
counter for the user's interrupt servicing routine. After
reset, and during a DMA operation, R(O) is used as the
program counter. At all other times the register designated
as program counter is at the discretion of the user.
Data Pointer.
The registers In R may be used al data pointers to Indicate a
location in memory. The regllterdeslgnated by X (I.e., R(X»
points to memory for the following Instructions (aaa Tabla
I):
1. ALU operatlonl F1-F5, F7, 74, 7S, 77;
2. output Instructions 61 through 67;
3. input Instructions 69 through 6F;
4. certain miscellaneous Instructions -70-73, 78,60, FO.
The register deSignated by N (I.e., R(N» points to memory
for the "load 0 from memory" Instructions ON and 4N and
the "Store D" instruction SN. The register dellgnated by P
(i.e., the program counter) il used as the data pOinter for
ALU instructionl F8-FD, FF, 7C, 70, 7F. During these
instruction exec\.ltions, the operation is referred to al "data
immediate".
Another important use of R as a data pointer luPPOrts the
built-in Direct-Memory-Accels (DMA) function. When a
DMA-In or DMA-Out request is received, one machine
cycle is "stolen". This operation occurs at the end of the
execute machine cycle in the current instruction. Register
R(O) is always used as the data pOinter during the DMA
operation. The data is read from (DMA-Out) or written Into
(OMA-In) the memory location pointed to by the A(O)
register. At the end of the transfer, R(O) is incremented by
one so that the processor is ready to act upon the next OMA
byte transfer request. This feature In the 1.600-serles
architecture saves a substantial amount of logic when faIt
exchanges of blocks of data are required, such as with
magnetic discs or during CRT-display-refresh cycles.
Da.. Registers
When registers in R are used to store bytes of deta, four
instructions are provided which allow 0 to reCeive from or
write into either the hlgher-order- or lower-order-byte
portions of the register deSignated by N. By this mechanism
(together with loading by data immediate) program pointer
and data pOinter designations are initialized. Also, this
technique allows scratch pad registers in R to be used to hold
general data. By employing increment or decrement Instructions, such registers may be used as loop counters.
The Q Flip Flop
An internal flip flop, Q, can be set or reset by Instruction and
can be sensed by conditional branch instructions. The output
of Q is also available al a microprocessor output.
Interrupt ServIcing
Register R(1) is always used as the program counter whenever
interrupt servicing .Is initiated. When an Interrupt request
occurs and the Interrupt Is allowed by the program (again,
nothing takes place until the completion of the current
instruction), the contents of the X and P registers are stored
in the temporary registerT, and X and P are setto new values;
hex digit 2 in X and hex digit 1 in P. Interrupt Enable Is
automatically de-activated to inhibit further Interruptions.
The user's interrupt routine il now in control; the contents of
T may be saved by meanl of a lingle Inltruction (78) in the
memory location pointed to by R(X). Atthe conclusion ofthe
Interrupt, the User'1 routine may restore the pre-Interrupted
value of X and P with a lingle Instruction (70 or 71). The
Interrupt~Enable flip flop can be activated to parmlt further
interruptI or can be disabled to prevent them.
19
RCA CMO.S LSI Products
COP1802A, COP1802AC
CPU ......... 8umlllllry
8 Bits
Data R~ster (Accumulator)
1 Bit
Data I=lag (ALU Carry)
8elts
Au~illary Holding Register
18 Bits ... 1 ot18 Scratchpad RegisterS
4 Bits
D88lgnat88 which register is
P~am Counter
4.Bits
Designates which register is
Data Pointlr
D.
.DF
B
R
P
X
N
I
T
4 Bits
4 Bits
8 Bits
IE
Q
1 Bit
1 Bit
Holds Low-order Instr. Digit
.Holds High-Order Instr. Digit
Holds old X, P after Interrupt
(X Is high nibble)
Interrupt Enable
Output Flip Flop
CDP1802 Control Mod••
The WAiT and CLEAR lines provide f()ur control modes
lilted In the following truth table:
CiiAi
L
L
H·
H
~IT
as
MODE
LOAD
RESET
PAUSE
RUN
l
J!
L
H
The function of the modes are defined as follows:
L*
Holds the CPU in the IDLE execution state and allows an 110
device to load the memory without the need for a "bootstrap"
loader. It modifies the IDLE condition so that DMA-IN
operation does not foree execution of the next Instruction.
R....
Registers I, N, Q are reset,lE is set and O's (VSS) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU is placed in S1. The first machine cycle
after termination of reset is an initialization cycle which
requires 9 clock pulses. During this cycle the CPU remains in
$1 and registers X, P, and R(O) are reset. Interrupt and DMA
servicing are suppressed during the Initlalitation cycle. The
next cycle is an $0, S 1,or an 82 but never an S3. With the use
of. 71 InstrucfionfollOWed by 00 at memory loCati(m~ 0000
and 0001. thl, feature may be used to reset IE, so as to
preclude Interrupti until ready for them. Powerup reset can
be realized by connecting an RC network directly to the
CLEAR pin, since It has a Schmitt-triggered Input, see Fig. 10.
PaUH
Stops the internal CPU timing generator on the first negative
high-te-Iow transition of the Input clock. The oscillator
contln.U8s to operate, but subsequent clock transitions are
ignored.
Bun
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation on the first
negative hlgh-to-Iow transition of the input clock. When
initiated from the Reset operation, the first machine cycle
following Reset is always the initialization cycle. The initialization cycle is then followed by a DMA (S2) cycle or fetch
(SO) from location 0000 in memory.
RUN-MODE &TATE. TRANSITIONS
The CDP1802A CPU state transitions when in the RUN and
RESET modes are shown in Fig. 11. Each machine cycle
requires .the same period of time, 8 clock pulses, except the
initialization cycle. which requires 9 clock pulses. The
execution of an instruction requires either two or three
machine cycles, SO followed by a Single S1 cycle or two S1
cycles. S2is the response to a DMA request and 83 is the
interrupt response. Table II shows the conditions on Data
Bus and Memory-Address lines during all machine states.
CoPl802A
The RC time conatant
ahould be greater than
the osclllato! start-up time
(typically 20 mal.
PRIORITY, FORCE
so,s.
6iJ1IN
."OUT
92CS-33871
Fig. 10 - Rent diagram.
iNT
12C5-:j3I72
Fig. 11 - Stat. tranaitlon diagram.
20
..
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
INSTRUCTION SET
The CPU instruction summary is given in Table J. Hexadecimal
notation is used to refer to the 4-bit binary codes.
R(W).O: Lower-order byte of R(W)
R(W).l: Higher-order byte of R(W)
In all registers bits are numbered from the least significant bit
(LSB) to the most significant bit (MSB) starting with O.
Operation Notation
M(R(N)) - 0; R(N) + 1 - R(N)
R(W): Register designated by W, where
W=N orX, or P
This notation means: The memory byte pointed to by R(N) is
loaded into 0, and R(N) i8 incremented by 1.
TABLE I-INSTRUCTION SUMMARY (S.e Notes following bible. pp. 11 and 12)
INSTRUCTION
MEMORY REFERENCE
LOADVIAN
LOAD ADVANCE
LOAD VIA X
LOAD VIA X AND ADVANCE
LOAD IMMEDIATE
STORE VIA N
STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
DECREMENT REG N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HiGH REG N
LOGIC OPERATIONSf
OR
OR IMMEDIATE
OP
CODE
MNEMON,IC
LON
LOA
LOX
LDXA
LDI
STR
STXO
ON
4N
FO
72
Fa
5N
73
M(R(N))-O; FOR N NOT 0
M(A(N))-O; (AN)+l -A(N)
M(R(X))-O
M(R(X))-O; R(X)+l-A(X)
M(R(P))-O; A(P)+l-R(P)
D-M(R(N))
O-M(R(X)); R(X)-l-A(X)
INC
'DEC
IRX
GLO
PLO
GHI
PHI
1N
2N
R(N)+l-R(N)
R(N)-l-R(N)
R(X)+l-R(X)
R(N).O-O
O-R(N).O
R(N).1-0
D-R(N).l
so
aN
AN
9N
BN
OR
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
XOR
XRI
F3
FB
AND
AND IMMEDIATE
AND
ANI
F2
FA
SHIFT RIGHT
SHR
FS
SHIFT RiGHT WITH CARRY
OPERATION
SHRC!
RING SHIFT RIGHT
SHIFT LEFT
RSHR
SHL
SHIFT LEFT WITH CARRY
SHLC
RING SHIFT LEFT
RSHL
7S§
FE
!
7E§
M(R(X)) OR 0-0
!
M(R(P)) OR 0-0;
A(P)+l-R(P)
M(R(X)) XOR 0-0
M(R(P)) XOA 0-0;
R(P)+l-A(P)
M(R(X)) AND D-D
M(A(P)) AND D-D;
R(P)+l-R(P)
SHIFT D RIGHT, LSB(D)-DF,
O-MSB(D)
SHIFT D RIGHT, LSB(D)-OF,
DF-MSB(D)
SHIFT D LEFT, MSB(D)-OF,
O-LSB(D)
SHIFT D LEFT, MSB(O)....OF.
DF-LSB(D)
21
RCA CMOS LSI Products
CDP1802A, CDP1802AC
TABLE I - INSTRUCTION SUMMARY (Confd)
OP
CODE
INSTRUCTION
ARITHMETIC OPERATIONS'
ADD
,
ADD IMMEDIATE
ADD WITH CARRY
ADD WITH CARRY, IMMEDIATE
ADD
ADI
ADC
ADCI
F4
FC
74
7C
SUBTRACT 0
SUBTRACT 0 IMMEDIATE
SO
SOl
F5
FO
SUBTRACT 0 WITH BORROW
SUBTRACT 0 WITH
BORROW, IMMEDIATE
SUBTRACT MEMORY
SUBTRACT MEMORY IMMEDIATE
SOB
SDBI
75
70
SM
SMI
F7
FF
MNEMONIC
SUBTRACT MEMORY WITH BORROW
5MB
SUBTRACT MEMORY WITH
5MBI
BORROW, IMMEDIATE
BRANCH INSTRUCTIONS-SHORT BRANCH
SHORT BRANCH
BR
NO SHORT BRANCH (SEE SKP)
NBR
SHORT BRANCH IF 0=0
BZ
77
7F
30
3S§
32
SHORT BRANCH IF 0 NOT 0
BNZ
3A
SHORT BRANCH
SHORT BRANCH
SHORT BRANCH
GREATER
SHORT BRANCH
SHORT BRANCH
SHORT BRANCH
SHORT BRANCH
IF OF=l
IF POS OR ZERO
IF EOUAL OR
BOF
BPZ
BGE
33§
IF
IF
IF
IF
BNF
BM
BL
BO
OF=O
MINUS
LESS
O=F
!
!
M(R(P»-R(P).O
R(P)+l-R(P)
IF 0=0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF 0 NOT 0, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF OF=l, M(R(P»-R(P).O
ELSE R(P)+l-·R(P)
IF OF=O, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
31
IF 0=1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF 0=0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF1=1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF1=0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF2=1, M(R(P»'-R(P).O
ELSE R(P)+1-R(P)
IF EF2=0, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF3=1, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF3=O, M(R(P»-R(P).O
ELSE R(P)+1-R{P)
BNO
39
SHORT BRANCH IF EF1=1
B1
34
(ffi=vss)
SHORT BRANCH IF EF1=0
(ffi=vcc)
SHORT BRANCH IF EF2=1
BN1
3C
B2
35
(EF2=VSS)
'SHORT BRANCH IF EF2=0
BN2
3D
B3
36
BN3
3E
(EF3=VCC)
M(R(X»+D-DF, 0
M(R(P) )+D-DF,D; R(P)+1-R(P)
M(R(X»+D+OF-OF, 0
M(R(P»+D+OF-OF, 0
R(P)+1-R(P)
M(R(X»-D-OF, 0
M(R(P»-D-OF, 0;
R(P)+1-R(P)
M(R(X»-O-(NOT OF)-OF, 0
M(R(P»-O-(NOT OF)-OF, 0;
R(P)+1-R(P)
O-M(R(X»-OF, 0
D-M(R(P»-OF,O;
R(P)+1-R(P)
O-M(R(X»-(NOT OF)-OF, 0
O-M(R(P»-(NOT OF)-DF, 0
R(P)+l-R(P)
3B§
SHORT BRANCH IF 0=0
(m=VCC)
SHORT BRANCH IF EF3=1
(EF3=VSS)
SHORT BRANCH IF EF3=0
OPERATION
22
..
1800-Series Microprocessors and Microcomputers
CDP1802A, CDP1802AC
TABLE I - INSTRUCTION SUMMARY (Confd)
INSTRUCTION
OP
CODE
MNEMONIC
OPERAnON
BRANCH INSTRUCTIONS-SHORT BRANCH
SHORT BRANCH IF EF4=1
B4
37
(EF4=VSS)
SHORT BRANCH IF EF4=0
BN4
3F
BRANCH INSTRUCTIONS-LONG BRANCH
LONG BRANCH
LBR
CO
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF 0=0
NLBR
LBZ
C2
LONG BRANCH IF 0 NOT 0
LBNZ
CA
LONG BRANCH IF OF=1
LBDF
C3
LONG BRANCH IF DF=O
LBNF
CB
LONG BRANCH IF Q=1
LBQ
C1
LONG BRANCH IF Q=O
LBNQ
C9
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF D=O
SKP
LSKP
LSZ
38§
C8§
LONG SKIP IF D NOT 0
LSNZ
C6
LONG SKIP IF DF=1
LSDF
CF
LONG SKIP IF DF=O
LSNF
C7
LONG SKIP IF Q=1
LSQ
CD
LONG SKIP IF Q=O
LSNQ
C5
LONG SKIP IF IE=1
LSIE
CC
(EF4=VCC)
C8§
CE
IF EF4=1, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF4=O, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
R(P)+2-R(P)
IF 0=0, M(R(P))-R(P).1
M(R(P)+1)-R(P).O .
ELSE R(P)+2-R(P)
IF 0 NOT 0, M(R(P))-R(P).1
M(R(~)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF=1, M(R(P))-R(P).1
M(R(P)+1)-R(P).O
ELSE R(P)+2-R(P)
IF DF=O, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF Q=1, M(R(P))-R(P).1
M(R(P)+1 )-R(R).O
ELSE R(P)+2-R(P)
IF Q=O, M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
R(P)+1-R(P)
R(P)+2-R(P)
IF 0=0, R(P)+2-R(P)
ELSE CONTINUE
IF 0 NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF DF=1. R(P)+2-R(P)
ELSE CONTINUE
IF OF=O, R(P)+2-R(P)
ELSE CONTINUE
IF Q=1, R(P)+2-R(P)
ELSE CONTINUE
IF Q=O. R(P)+2-R(P)
ELSE CONTINUE
IF IE=1, R(P)+2-R(P)
ELSE CONTINUE
23
RCA CMOS LSI Products
CDP1802A, CDP1802AC
TABLE I - INSTRUCTION SUMMARY (Cont'd)
INSTRUCTION
OP
CODE
MNEMONIC
OPERATION
CONTROL INSTRUCTIONS
IDLE
IOl
QO#
NO OPERATION
SETP
SET X
SETa
RESET a
SAVE
PUSH X,P TO STACK
NOP
SEP
SEX
SEa
REa
SAV
MARK
C4
ON
EN
7B
7A
78
79
RETURN
RET
70
DISABLE
DIS
71
OUTPUT,"
OUTPUT 5
OUTPUT 6
,OUTPUT 7
OUT 1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
61
62
63
64
65
66
67
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
M(R(X))-BUS;R(X)+1-R(X);
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUTS
INPUT6
INPUT 7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
69
6A
6B
6C
60
6E
6F
BUS-M(R(X));
BUS-M(R(X));
BUS--M(R(X));
BUS-M(R(X));
BUS-M(R(X));
BUS-M(R(X));
BUS-M(R(X));
INPUT-OUTPUT BYTE TRANSFER
OUTPUT 1
OUTPUT 2
OUTPUT 3
WAIT FOR DMA OR INTERRUPT;
M(R(O»-BUS
CONTINUE
N-P
N-X
1-a
o-a
T-M(R(X))
(X,P)-T; (X,P)-M(R(2»
THEN P-X; R(2)-1-R(2)
M(R(X))-(X,P); R(X)+1-R(X)
1-IE
M(R(X))-(X,P); R(X)+1-R(X)
O-IE
BUS-O;
BUS-D;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-D;
N
N
N
N
N
N
N
N
N
N
N
N
N
N
LINES=1
LlNES=2
LlNES=3
LlNES=4
LlNES=5
LlNES=6
LlNES=7
LINES=1
LlNES=2
LlNES=3
LlNES=4
LlNES=5
LlNES=6
LINES=7
Notes
trHE ARITHMETIC OPERATIONS AND THE SHIFT INSTRUCTIONS ARE THE ONLY INSTRUCTIONS THAT CAN ALTER THE OF.
AN ADD INSTRUCTION:
DF=1 DENOTES A CARRY HAS OCCURRED
DF=O DENOTES A CARRY HAS NOT OCCURRED
AFTER A SUBTRACT INSTRUCTION:
DF=1 DENOTES NO BORROW. 0 IS A TRUE POSITIVE NUMBER
DF=O DENOTES A BORROW. 0 IS TWO'S COMPLEMENT
THE SYNTAX "-(NOT OF)" DENOTES THE SUBTRACTION OF THE BORROW
AFTER
§THIS INSTRUCTION IS ASSOCIATED WITH MORE THAN ONE MNEMONIC. EACH MNEMONIC IS INDIVIDUALLY LISTED.
'AN IDLE INSTRUCTION INITIATES A REPEATING S1 CYCLE. THE PROCESSOR WILL CONTINUE TO IDLE UNTIL AN 1/0 REQUEST
(INTERRUPT,
OR i5MA-0UT) IS ACTIVATED. WHEN THE REQUEST IS ACKNOWLEDGED, THE IDLE CYCLE IS TERMINATED
AND THE 1/0 REQUEST IS SERVICED, AND THEN NORMAL OPERATION IS RESUMED.
DMA-iN:
24
1800-Series Microprocessors and Microcomputers
CDP1802A, CDP1802AC
Not•• lor TABLE I
1. Long-Branch, Long-Skip and No Op instructions are
the only instructions that require three cycles to
complete (1 fetch +2 execute).
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
The long-branch instructions can:
a) Branch unconditionally
b) Test for 0=0 orD~O
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) effect an unconditional no branch
If the tested condition is met, then branching takes
place; the branching address bytes are loaded in the
high- and low-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
If the tested condition is not met, the branching
address bytes are skipped over, and the next instruction in sequence is fetched and executed. This
operation is taken for the case of unconditional no
branch (NLBR).
2. The short-branch instructions are two bytes long. The
first byte specifies the condition to be tested, and the
second specifies the branching address.
The short-branch instruction can:
a) Branch unconditionally
b) Test for 0=0 or O~O
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) Test the status (1 or 0) of the four EF flags
f) Effect an unconditional no branch
counter. This effects a branch within the current 256byte page of the memory, Le., the page which holds the
branching address. If the tested condition Is not met,
the branching address byte is skipped over, and the
next instruction in sequence is fetched and executed.
This same action is taken in the case of unconditional
no branch (NBR).
3. The skip instructions are one byte long. There is one
Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Skip instruction takes 2 cycles
to complete (1 fetch + 1 execute). Its action is to skip
over the byte following it. Then the next instruction in
sequence is fetched and executed. This SKP instruction
is identical to the unconditional no-branch instruction
(NBR) except that the skipped-over byte is not
considered part of the program.
The Long-Skip instructions take three cycles to
complete (1 fetch +2 execute).
They can:
a) Skip unconditionally
b) Test for 0=0 or O~O
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) Test for IE=1
If the tested condition is met, then Long Skip takes
place; the current program counter is incremented
twice. Thus two bytes are skipped over and the next
instruction in sequence is fetched and executed. If the
tested condition is not met, then no action is taken.
Execution is conti nued by fetching the next instruction
in sequence.
If the tested condition is met, then branching takes
place; the branching address byte is loaded into the
low-order byte position of the current program
25
RCA CMOS LSI Products
CDP1802A, CDP1802AC
00
1
I
TPA
I
MEMORY
ADDRESS
I
MRD
LtPLlil
I
t~LH'~PHl:l
~
~
:
~~~OC~~LE) '=:J
I'
MWR
(MEMORY
WRITE CYCLE)
rj
CPUTOBUS
I
r-----~--~~~4-~t_~--------~--------~~
TPB
OATA FROM
I
t---J
hi>HL\
~
1 tPLH
'pHL
tpLH
t ; 7 1
II
I
I
I
~1---_j.....11---(1'--+--.----:-1- - - - + - 1-+-r--.-L\-h
L:LJ
\
t~LH'trHs::p
STATE
CODES
Q
NO,NI,N2
~
(I/O
EXECUTION
CYCLE)
DATA FROM
BUS TO CPU
DMA
REQUEST
INTERRUPT
REQUEST
EF 1-4
I
1
INTERRUPT
.ISU
SAMPLED (51,52"
)""'-+--'''-'-'1 ~___
1FLAG LINES I
ISAMPLED (IN 51)
\.tsLTI'H 1
7
'- '
---1
1
~--+---:
l'ej
ANY NEGATIVE
TRANSITION
----------~~r-~---------------------------------------NOTES'
I. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE
2. ALL MEASUREMENTS ARE REFERENCED TO 50% POINT OF THE
WAVEFORMS
92CL-33869RI
3. SHADED AREAS INDICATE "OON'T CARE" OR UNDEFINED STATE;
MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD
Fig. 12 - Timing waveforms.
26
...
1800-Series Microprocessors and Microcomputers
CDP1802A, CDP1802AC
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, CL =50 pF, VDD±5%, except al noted•
CHARACTERISTIC
VCC
(V)
VDD
(V)
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
....wtrra
Typ.-
Max.
300
250
150
850
5
10
10
10
5
10
10
200
150
100
600
400
300
250
150
100
200
150
100
200
150
100
200
150
100
300
250
100
300
250
150
250
150
100
300
200
150
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
-20
0
-10
150
100
75
0
0
0
150
100
75
-75
-50
-25
25
50
40
200
125
100
30
20
10
250
200
125
0
0
0
UNITS
Propagation Delay Times:
Clock to TPA. TPB
tPLH. tpHL
Clock-to-Memory High~Address Byte
tpLH. tPHL
Clock-to-Memory Low-Address Byte Valid
tPLH. tPHL
Clock to MRD
tpHL
MRo
tpLH
Clock to MWR
tPLH. tPHL
Clock to (CPU DATA to BUS) Valid
tPLH. tpHL
Clock to
Clock to State Code
tpLH. tpHL
5
10
5
Clock toO
tPLH. tpHL
5
10
5
Clock to N (0-2)
tpLH. tpHL
5
600
400
350
250
150
300
250
150
350
290
175
300
250
150
450
350
200
450
350
250
400
250
150
550
350
250
ns
Minimum Setup and Hold Times:
Data Bus Input Setup
tsu
Data Bus Input Hold
tH-
DMA Setup
tsu
DMA Hold
tH-
Interrupt Setup
tsu
·TYPlcal values are for T A=25° C and nominal VDD.
-Maximum limits of minimum characteristics are the values above which all devices function.
27
RCA CMOS LSI Products
CDP1802A, CDP1802AC
DYNAMIC ELECTRICAL CHARACTERISTICS
(Conl'd)
CHARACTERISTIC
LIMITS
UNITS
Typ.M8X.
VCC
(V)
VDD
(V)
5
5
10
5
10
10
100
75
50
150
100
75
5
5
10
10
10
-10
50
15
25
5
10
10
-30
-20
-10
20
30
40
5
10
5
10
10
150
100
75
200
150
100
Minimum Setup and Hold Times:
Interrupt Hold
tH-
WAIT Setup
tsu
5
10
5
EFl-4 Setup
tsu
EFl-4 Hold
tH-
5
10
5
0
ns
Minimum Pulse Width Times:
Ct::EAR Pulse Width
tWL-
5
5
10
5
10
10
150
100
75
300
200
150
tWL
5
5
10
5
10
10
125
CLOCK Pulse Width
150
125
75
100
60
-Typical values are for T A=2S o C and nominal VOO.
-Maximum limits of minimum characteristics are the values above which all devices function.
TIMING SPECIFICATIONS a8 a uncII on 0 fT (T =l/f CLOCK;) at TA=-40 185°C
0+
VCC
CHARACTERISTIC
(V)
High-Order Memory-Address Byte
;r
Set Up to TPA
Time
LIMITS
TVD.Min.
5
5
5
10
2T-550 2T-400
2T-350 2T-250
10
10
2T-250 2T-200
5
10
10
T/2-25
T/2-35
T/2-10
T/2-15
T/2-25
T/2+0
High-Order Memory-Address Byte
Hold after TPA Time
tH
5
5
10
Low-Order Memory-Address Byte
Hold after WR Time
tH
5
5
10
5
10
10
T-30
T-20
T-l0
T+O
T+O
T+O
CPU Data 10 Bus Hold
after WR Time
IH
5
5
10
5
10
10
T-200
T-150
T-100
T-150
T-100
T-50
tACC
5
5
10
5
10
10
5T-375 5T-250
5T-250 5T-150
5T-190 5T-l00
Required Memory Access Time
Address to Data
-Typical values are for TA=2S o C and nominal VOO.
28
tsu
VDD
(V)
UNITS
ns
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
STATE
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STAT ES
DATA
MEMORY
N
MNEMONIC
. OPERATION
BUS
ADDRE..
iiRo Mwii
I
Sl
RESET
Sl
INITIALIZE
NOT PROGRAMMER
ACCESSIBLE
FETCH
SO
0
0
1
2
3
Sl
0
1-F
D-F
D-F
D-F
loL
LON
INC
DEC
SHORT
BRANCH
4
D-F
LOA
5
6
D-F
0
1
2
3
4
5
6
7
A
B
C
0
E
F
STR
IRX
OUTl
OUT 2
OUT3
OUT4
OUT5
OUT 6
OUT 7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
0
RET
1
6
7
N
LINES
NOTISG
O-I,N,Q,X,P;
1-IE
OOOO-R
00
XXXX
1
1
0
A
00
XXXX
1
1
Q
B
MRP-I,N;
RP+1-RP
IDLE
MRN-O
RN+1-RN
RN-1-RN
TAKEN;
MRP-RP.O
NOT TAKEN;
RP:+-1-RP
MRN-o;
RN+1-RN
O-MRN
RX+1-RX
MRP
RP
0
1
0
C
MRO
MRN
FLOAT
FLOAT
RO
RN
RN
RN
0
0
1
1
1
1
1
1
0
0
0
0
0.3
3
1
1
MRP
RP
0
1
0
MRN
RN
0
1
0
3
0
MRX
RN
RX
1
0
0
1
2
2
MRX
RX
0
1
0
0
1
2
3
4
5
6
7
1
MRX-BUS;
RX+l-RX
3
6
DATA
FROM
I/O
DEVICE
RX
1
0
MRX-(X,P);
RX+l-RX; l-IE
MRX
RX
0
1
0
3
DIS
MRX-(X,P);
RX+l-RX; D-IE
MRX
RX
0
1
0
3
2
LOXA
MRX-o;
RX+l-RX
MRX
RX
0
1
0
3
3
STXEl
o-MRX;
RX-l-RX
0
RX
1
0
0
2
4
AoC
MRX+D+
OF-OF 0
MRX
RX
0
1
0
3
9
BUS-MRX,O
2
3
4
5
6
7
5
29
RCA CMOS LSI Products
CDP1802A, CDP1802AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STATES (CONTD)
STATE
51
I
7
8
9
A
B
N
5
MNEMONIC
OPERATION
DATA
BUS
MEMORY
ADDRESS
MRD
SDB
MAX-D-
MAX
AX
0
FLOAT
AX
1
MAX
AX
T
T
6
SHAC
7
5MB
8
9
MAAK
A
B
C
SEO
ADCI
D
SDBI
E
5HLC
F
5MBI
O-F
O-F
O-F
D-F
SAY
AEO
GLO
GHI
PLO
PHI
51#1
#2
0-3,
8-B
51#1
#2
51#1
#2
51#1
#2
LONG
BAANCH
C
5
6
7
C
D
E
F
LONG
5KIP
51#1
4
#2
30
-
N
LINES
NOTESG
1
0
3
1
0
1
0
1
0
3
AX
A2
1
1
0
0
0
0
2
2
FLOAT
FLOAT
MAP
AP
AP
AP
1
1
Q
1
0
1
1
1
0
0
3
MAP
AP
0
1
0
3
AP+1
M5B(D)-DF;
DF-L5B(D)
FLOAT
AP
1
1
0
1
D-M~P-
MAP
AP
0
1
0
3
AN.O
AN.1
D
0
MAP
AN
AN
AN
AN
AP
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
4
M(AP+1)
AP+1
0
1
0
4
MAP
AP
0
1
0
4
M(AP+1)
AP+1
0
1
0
4
MAP
AP
0
1
0
4
TAKEN: AP+1-AP
M(AP+1)
AP+1
0
1
0
4
NOT TAKEN:
NO OPEAATION
NOT TAKEN:
MAP
AP
0
1
0
4
DFN-DF,D
LSB(D)-DF;
DF-M5B(D)
D-MAXDFN-DFD
T-MAX
(X,Pj-T, MA2;
P-X' A2-1-A2
0-0
1-Q
MAP+D+
DF-DF,D; AP+1
MAP-DDFN-DF,D;
DFN-DF,D;
AP+1
AN.O-D
AN.1-D
D-AN.O
D-AN.1
TAKEN: MAP-B;
AP+1-AP
TAKEN: B-AP.1;
MAP-AP.O
NOT TAKEN:
AP+1-AP
NOT TAKEN:
RP+1-AP
TAKEN: AP+l-AP
1
1
1
MAP
AP
0
1
0
4
NO OPEAATION
NO OPEAATION
MAP
AP
0
1
0
4
NO OPEAATION
MAP
AP
0
1
0
4
NOP
1800-Series Microprocessors and Microcomputers
CDP1802A, CDP1802AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORV ADDRESS LINES DURING
ALL MACHINE STATES (CONTD)
STATE
I
0
E
S1
F
S2
S3
N
O-F
O-F
0
1
2
3
4
5
-MRD MWR
--
DATA
MEMORY
MNEMONIC
OPERATION
BUS
ADDRESS
SEP
N-P
NN
RN
SEX
LOX
OR
AND
N-X
NN
MRX
RN
RX
0
MRX
RX
FLOAT
1
1
1
i
N
LINES
0
NOTESca
i
-~
i
1
--'l
--.a
0
1
0
3
RX
1
1
0
1
MRP
RP
0
1
0
3
RP+1-RP
MSB(O)-OF;
O-LSB(O)
FLOAT
RP
1
1
0
1
DMAIN
BUS-MRO;
RO+1-RO
DATA FROM
1/0 DEVICE
RO
1
0
0
F, 7
DMAOUT
MRO-BUS;
MRO
RO
0
1
0
F,e
INTERRUPT
RO+1-RO
X,P-T; O-IE
FLOAT
RN
1
1
0
9
M(RO-l)
RO-1
0
1
0
E,3
MRX-O
MRX OR 0-0
MRXANO 0-0
MRXXOR 0-0
7
XOR
ADD
SO
SM
6
SHR
LSB(O)-OF;
e
LOI
O-MSI!lCll.
MRP-O;
9
ORI
A
ANI
RP+1-RP
MRPOR 0-0;
RP+l-RP
MRPANO 0-0;
B
XRI
RP+1-RP
MRPXOR 0-0;
MRX+O-OF,O
MRX-O-OF,O
O-MRX-OF,O
C
AOI
0
SOl
RP+1-RP
MRP+O-OF,O;
RP+1-RP
MRP-D-OF,O;
F
SMI
RP+1-RP
O-MRP-OF,O;
E
SHL
1-P' 2-X
S1
LOAD
IDLE
(CLEAR, WAIT=O)
NOTES:
A. IE=l, TPA, TPB suppressed, state=Sl,
B, BUS=O for entire cycle,
C. Next state always S1.
D. Wait for DMA or INTERRUPT.
E. Suppress TPA, wait for DMA.
F. ,IN REQUEST has priority over OUT REQUEST.
G. Number refers to machine cycle. See Fig. 14 timing waveforms for machine cycles 1 through 9.
31
RCA CMOS LSI Products
CDP1802A, CDP1802AC
J
4
5
4
6
5
7
3
0
..
5
6
CLOCK
--'r'l..--
TPA ~'--_ _ _ _ _...JnL._ _ _ _ _--,nL._ _ _ _ _---,nL._ _ _ _ _
TPB ______________~r_1L.____________~r_1L.____________~r_1L.____________~r_1L.
_________
~:~~NE J[=======C~y~C~LIE~,,======~======~C~y~CILIE~',,~,~,C'====J[======C~y~CILIE~'o~.J'[I====:r======3C~Y£CL~EJ'~n~.~31====:JI:Jc~v~C~L.~iEn!+!.,c::
MA
HIGH ADD
I
LOW ADDRESS
!HIGH ADD
I
LOW ADDRESS
IHIGH ADol
F'GH
LOW ADDRESS
ADD}
LOW ADDRESS
F'GH ADol
LOW
General timing waveforms.
INSTRUCTION
===:!FIET!'.'C::!:H!:J:'S~O!I:'===:C===E~X~E~C~UI.iTE=:!'IS'~'==I==::::J'~E:!:TC£!":cJ'~SOIT'===:C==::IEX8J'~C:!:!U!!TEC'~STIll==JI=F~E[!T£C"!C~ISO!lilC:
f.---MEMORY READ CYCLE --...f---NON MEMORY CYCLE ---f---MEMORY READ CYCLE -
-tl...--NON,MEMOAY CYCLE-+--~~~gRV
....
I
MRD - - - , L_ _ _ _ _ ~
f CVCLE
MWR1HIGHI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LVALIDOUTPUT
No.1 Non-memory-cycle timing waveforms.
r
NSTRUCTlON
~
I
FETCH
~MtMORY
MRD
f XfCUH
(SOl
READ CYCLf
FETCH
($11
-+----MEMURY WRITf
(:YCLf~---+-- MEMORY
. JI
(SO)
I
~L_ _ _ _ _ _ _
I
L...J
MWR
~Sll
EXECUTE
REAO CYCLE--+-MEMORY WRITE
FETCH
ISOI
CYClE~~~~gRV
I CYClE
L...J
~~~~~TY ~1!I;/~$~~~~~///~«:~0j~.0~%atJ
. . . . . . . . .'2tj~;;~~~/.:~/'//~~~~~~~1~;:jPIll~~~••••~?0~/'v~/.:~ ~
:lLOWABlE~~LvAlIDUUTPUT
LVALIDOUTPUT
CPU OUTPUT
~~MORY
OFF
Vl'IlIll!)AIA
OFF
OF~
VALID DATA
No. ·2 Memory write-cycle timing waveforms.
INSTRUCTION
--,-I_ _--.:'.;.'_TC::.;"C-'' 'sO::.;'_ _ _..L.-_ _-'f-'-X.:.'::.;Ci;..JT.;.E____'S:...'_'_ _' -_ _ _F;:.ET:..;C;;.;"-'.'5:.:0",'_ _...J.____E_XE-'C'-'U_T_E....:.:;,s...;"_ _........;.F"""TC:;;."'--"::.;50;;.1__
~Mr-MORY
MRD
~L.
REAl) CYCLE---+- MEMOHY REAIl CYCU
--+---
+ol_o--- ~,~~gRY
MEMORY READ CYClE--T-MEMORY READ CYCLE-......
_ _ _ _ _~I1L._ _ _ _ _~I1L._______--'I1'___ _ _ _ _~n CYCLE
MWR (HIGH)
~C~~UR:
;:
~$&0
ALlOWABL"f MEMORY
fleet;:
w~~
L- VAllO ~ ------- L
~ff.0;//~;>2EU1W$$#4
0iVffi'd
O~TPUT
ar
VALID O~lPUT
-tVALIDOUTPUT
VALID
No.3 Memory read-cycle timing waveforms.
INSTRUCTION ..L_ _ _-"'.=.ET:.:C:.:.H:......:'~SO:.:.'_ _.....J'-_ _ _.=.EX::.:E:::Co:U.:.:TEc....:'O:S:.:."_---L._ _ _....:::EX.:.:E:::C.::U.:.:TE~'::.S':.:.,_...J._ _ _ _.:.:FE:.:T.::C;.;."...;.:150::;,'-_..... e",X:.::E.;:CU",T;.:Ec....:'::;S'c.1__
I--MRD
n
MEMORY READ CYCLE
-+-
MEMORY READ CYCLE
11
-+----
n
1:
MEMORY READ CYCLE .....t.-MEMORY READ CYCLE
.I~
111..._____--111
MWA (HIGH)
~C~~UR:;;
Zo/ff~~.
~#$$/;j
~~ ~~L1
L- VAUD OOTPUT
,. LVALID 00TPUT
• L
VALID olfTPUT
•
ALLOWAs:e MEMORY ACCES;
No.4 Long-branch or long-skip-cycle timing waveforms.
~
"Don't Care" or Ifllernal (!<'I
_
H,gh'ITlPI'(j,"lCl'\ld!i'
Fig. 13 - Machine-cycle timing waveforms (propagation delays not shown).
32
92CL-29600
:~:gRY
CYCLE
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
o
CLOCK
TPA
--IlL-.________...JrlL _ _ _ _ _ _ _ _ __
1L
TPB _ _ _ _ _ _ _ _ _---IIlL.._ _ _ _ _ _ _ _ _
MACHINECYClE __L_________~C~Y~C~L~E~n______________~________~C~Y~CL~E~I~n~+~I~'__________-L__...
INST RUCTION ....lL-.________F_E_T_CH--'-'SO-'-'_ _ _ _ _ _......._ _ _ _ _;;.EX~E;;.C;;;U~T;;.E~IS:.;,I:.;,I_ _ _ _ _ _...L.___
MRD
NO-N2 __--'-_ _ _ _ _ _ _ _ _ _ _- - - - - - 1
MWR
~~~~~TY
:J• •I2ZLZ:;]~§:_~%~Z~%~~~%~%~%~%~Z~Z~%~%~~~• • • • • • • • • • • • • •
L
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
DATA BUS
[
~
_.~.o-----
MEMORY _ _ _ _ _ _ _•.-11
WRITE CYCLE
..> - - - - - MEMORY - - - - - - -..
READ CYCLE
-
I
VALID DATA FROM INPUT DEVICE
'User-generated signal
92CS-29601
No.5 Input-cycle timing waveforms.
CLOCK
TPA
~
____________________________
TPB _ _ _ _ _ _ _ _ _ _ _ _ _ _~r--1L
MACHINE
CYCLE
~r-l~
_________________________________
____________...Jr__lL_______
CYCLE (n + 1)
CYCLE n
INSTRUCTION ....J_ _ _ _ _ _:.;FE:.;T;;;C:.;H~I;;.SO:;.'_ _ _ _ _......._ _ _ _ _ _...!E:.::X:.::Ec:::C::.UT.:..:E:....::IS:.:I~I_':....._ _.....L____
~
MRD
___________________...Jr__l~________________________~r---
NO-N2 ___________________________~/
N
~
1-7
ALLOWABLE MEMORY ACCESS
DATA BUS
~~IIII~~~~~~~~~~~~~IIII~~~·~~~~~~~~~
A~lOWABLE
~~~. . . .
MEMORY ACee:
VALID DATA FROM MEMORY
DATA STROBE' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~V~A~LI~O~O~U~T~PU~T:....._ _ _ _ _ _ _ _~
IMRD ' TPB, NJ
I
MEMORY
,---- - - - - - - - READ C Y C L E - - - - - - . I
I
1
• User-generated signal
~
"Don't Care" or Internal delays
92CS-29602
_
High'lmpedance state
No.6 Output-cycle timing waveforms.
Fig. 13 - Machine-cycle timing waveforms (propagation delays not shown). Continued.
33
RCA CMOS LSI Products
CDP1802A, CDP1802AC
•
CLOCK
TM~~
____________
~r_1~
______________
n
TPS
~r_1~
n-0
______________r_1L_____________
n
-11
MACHINE~~~~~~C!Y~C!Le~n~~~~~~~~~~C!V!C!L!E!n~+~1~~~~:!~~~~C~V~;!~~21~~~~~~~~l~~c!~~(~z~~~~~~
'CkLn +
Ln +
CYCLE
INSTRUCTION
FETCH ISOI
EXECUTE ISII
MRD - ,..._ _ _ _ _ _ _ _- '
FETCH ISO!
DMA 1121
DMA-iN' ~ffff/-0Wff«&//////M/&/A
&/////?/////////A
V/!./W/,/d/./!/!/IHU/!'A'
\ ... _ _ _ _ _ _ _ _ _ _ ../
\_--~
Ml'iR
MEMORY
OUTPUT
t. VALID OUTPUT
.
VALlDOUTPl!T
DATABUS'~""""""""""""~"""""""""""~JV~A~LTIID~A~A~~aIENP~UnT~D~E]V~IC~E::~. . . . . . . . . . . .Ii.........1
I
(
~~~
I
~ RE~EDMg;;lE-------."I.o--- READ. WRITE OR
I
I
I
I
OO~~V~=
1
MEMORV
REAOCYCLE
MEMORV
WRITE CYCLE
·1
92CS-29603
·User·generaledslgnal
No.7 DMA-IN-cyc/e timing waveforms.
CLOCK
TPA~
______________~r-1L
______________
~r-1L
______________
~r-L--
TPB~:::::::~~~~::::~r-1~_~~~:-:-:-:-:-:-~~=--:-:-:-~:-~~r-1
~~::::~~~~::~r-1~~:;-=--~~;-~:-~~
11
__
~:g~NE
CYCLE n
CYCLE In +
CYCLE In + 21
I CYCLE In , 31
INSTRUCTlONJ-______~F~E~T~C~H~IS~O~I________~______~E~X~E~C~U~TE~(S~I~I________L-________~O~M~A~15~2~1________~I~F~ET~C~H~IW~I__
MRO
,
,
---,
L -_ _ _ _ _ _ _ _ _ _ _ _~
'"- _ _ _ _ _ _ _ _ _ _ ..1
L ___ J
MWR
MEMORY
OUTPUT
V;WZZWZZWPPJ
t
DATA'
STROBE
IS2· TPBI
VALID OUTPUT
VALID DATA FROM MEMORY
I
I
r-1L....,.....________
I
---t. .I"'........
I
MEMORV
- - -......
~o--- READ, WRITE OR
READ CYCLE
:
NON MEMORY CYCLE
I.
...- - - - , MEMORY
I
/////W/?Z!7~t:J...~2Z<;Z<;ZZZz~
0VWWA/ZZ/LZ0
:
I
---;;-R.E'!EDMgvRC:E,...-----...+I.~MEMORY
:READ CYCLE
92CM - 29604RI
• User· generated slqnal
No.8 DMA-OUT-cycle timing waveforms.
CLOCK
TPA~~
~:g~~NE
INSTRUCTION
____________~r-1~
MWR
~rI~
______________
~r-1~
______________
~~~~~~:~~~~f~r-1~~~~~~~~~~~~~~r-1~. ~~~~~~~~~~~~r-1~~~~~~~~n--~~
CYCLE n
CYCLE (n + 1)
CYCLE In + 21
FETCH (SOl
EXECUTE (51)
INTERRUPT (531
MRO - - ,
TPB
______________
'.. _ _ _ _ _ _ _ _ _
CYCLE
'n + 31
FETCH (SOl
r
J
\___ 1
iNTeiiiiiJPT· W##/#$$###/##/#/#//##//#/#/#///,0Io..-__--'V//////$$$$/#/////$/#/$$////####/.Ih
IINTERNALIIE --------------------------------------------------------,_________________________________
~~~~: IIIIIE~~0~~~~~q:~~~~~~~~~~~~~~~?~~0~~~FlII~~~~~~/-2~~~~Z~Z~Z~2~Z~2~?~%~;:~2~·?~1I1I1I1I1I1I1I1I1I1I1I~%~~~~§~~~~§~~~~%~~~~~~§~~~~atJ"1I
lVALIDOUTPUT
•
VAlIDOU~j
"':·o----RE~~"gv"C:E
- - -..
OO+O:·.......---:O~E~gNR~E".i~~Y"t:~~CE-......• ..:·
.....--NON.MEMORYCYCLE
--t··:"'·. . . . ---RE~~Mc\'v':iE
I
·User.generated'ignal
~
"Don't Care" or IOternal delavs.
•
High-impedance state
No. 9 INTERRUPT-cycle timing waveforms.
Fig. 13 - Machine-cycle timing waveforms (propagation delays not shown). ContInued.
34
1
- - - - -...........
92CM-29605
1800-Serles Microprocessors and Microcomputers
CDP1802A, CDP1802AC
I
92CL-33410
Dimensions in perentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10- 3 inch).
The photographs and dimensions of each CMOS chip represent a
chip when it is part of the wafer. When the wafer is cut into chips,
the cleavage angles are 57° instead of 90° with respect to the face
of the chip. Therefore, the isolated chip is actually 7 mils (0. 17 mm)
larger in both dimensions.
Dimensions and pad layout for CDP1802ACH.
35
RCA CMOS LSI Products
CDP1802BC
CLOCK
40
••
WAIT
ErEn
Q
4
••
••
SCI
seo
ii1Ili
BUS
BUS
8US
8US
BUS
8US
BUS
7
6
5
4
3
2
I
auso
Vee
H2
NI
NO
Vs.
Preliminary Data
7
10
"
12
13
I.
"I.
17
18
I.
20
38
'7
••••
••
33
.2
31
.0
2.
2.
27
2.
2'
2.
2.
22
21
CMOS 8-Blt Microprocessor
Voo
1iT.U.
15iiAIii
F••tuIH:
1lIIiOilT
INT'ERRUPT
• Minimum Instruction fetch-execute time of 3.2 liS
(maximum clock frequency:=5 MHz) at VDD=5 V
• Any combinatIon of standard RAM and ROM up to 65,536 bytes
• Operates with slow memories, up to 775 ns access time at feL =5 MHz
• 8-blt parallel organization with bidirectional
data bus and multiplexed address bus
• 16 x 16 matrix of registers for use as
multiple program counters, data pointers, or data registers
• On-chip DMA, Interrupt, and flag Inputs
• Programmable single-bit output port
• 91 easy-to-use instructloM
IiW1I
TPA
TP.
MA7
MA.
MA'
MA.
MAl
MA2
MAl
MAO
m
m
EF'
EF'
TOP VIEW
t1CS-27467RI
Termlnel A••lgnmen.
The RCA-CDP1802BC LSI CMOS 8-bit register-oriented
central-processing unit (CPU) is designed for use as a
general-purpose computing or control element in a wide
range of stored-program systems or products.
The COP1802BC includes all of the circuits required for
fetching, interpreting, and executing instructions which
have been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to
facilitate system design.
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchronous interface to memories and external controllers
for I/O devices, and minimizes the cost of interface controllers. Further; the I/O interface is capable of supporting
devices operating in polled. interrupt-driven. or direct
memory-access modes.
The COP1802BC has a recommended operating voltage
range of 4 to 6.5 volts. These types are supplied in 40-lead
dual-in-line side-brazed ceramic packages (0 suffix). and
4o-Iead dual-in-line plastic packages (E suffix).
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
U
II
~
---v
CDPI852
INPUT PORT CS2
DATA
A_
""
MA0-4
NO
fTJ !
DATA
0
'V
MAO-7
MAO-7
CSl
Milo
C--
CDPI833
I K-ReM
CDPI824
32 BYTE RAM
IiWlI
iiWR
CSI
CDPI852
CS2 4OUTPUT PORT
CLOCK 4-
'Iiiib
MRD
CDPI802
8-81T CPU
NI
CEO
' - TPB
TPA
TPA
DATA
DATA
II
-
'\7
Ci
DATA
1/
'2ell- J4111RI
Fig. 1 - Typical CDP1802BC small microprocessor system.
36
...
1800-Series Microprocessors and Microcomputers
CDP1802BC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD):
(All voltages referenced to VSS terminal)
CDPl802BC ........................................................................................................ -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .........................................................•..•..•..•••.... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ·±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA=-40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA=+60 to +85°C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mWI"C to 200 mW
For TA=-55 to +100°C (PACKAGE TYPE D) ............................................................................. 500 mW
For TA=+I00 to +125°C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA=FULL PACKAGE-TEMPERATURE RANGE ....................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 .............................................................................................. -55 to +125°C
PACKAGE TYPE E .................................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) .......................................................................... -65 to +15O"C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16±1/32 in. (1.59±0.79 mm) from case for 10 s max. .. ............ , .......................................... +285°C
I
OPERATING CONDITIONS at TA=-40°C to +85°C
For maximum reliability. operating conditions should be selected so that operation is always within the following ranges:
CONDITIONS
CHARACTERISTIC
VCC1
(V)
DC Operating Voltage Range
Input Voltage Range
Maximum Clock Input Rise or Fall Time, tr,tf
Minimum Instruction Time 2
Maximum DMA Transfer Rate
Maximum Clock Input Frequency,
load Capacitance (CLl=50 pF
fCl
LIMITS
COP1802BC
VOO
(V)
UNITS
Max.
Min.
-
-
4.0
6.5
-
VSS
VDD
4 to 6.5
5
5
4 to 6.5
5
5
3.2
5
5
-
V
1
/.IS
-
667
KBytes/s
DC
5
MHz
lVCC must never exceed VDD.
2Equals 2 machine cycles-one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3
machine cycles-one Fetch and two Execute operations.
8 LOAD CAPACITANCE (Cl)a50pF
N
!
AMBIENT TEMPERATURECTA)
~
-Z'·C
350
7
~
5
~
g
U
.
~
;
2
~
I
1;; 0
25
3,
45
"
65
75
85
95
lOS
AMBIENT TEMPERATURE (TA I-·C
115
92CS-54662
Fig. 2 - Typical maximum clock frequency
as a function of temperature.
125
25
!SO
75
100 125
150
ITS
LOAD CAPACITANCE ICL)-pF
200
92CS-$4I1S
Fig. 3 - Typical transition time VB. load
capacitance.
37
RCA CMOS LSI Products
CDP1802BC
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85·C, except.a noted.
LIMITS
CONDITIONS
CHARACTERISTIC
Quiescent Device Current
Output Low Drive (Sink) Current
(Except XTAL)
VOUT
(V)
VIN
(V)
VCC,
VDD
(V)
-
-
5
-
1
200
pA
0.4
0,5
5
1.1
2.2
mA
0.4
5
5
170
350
-
4.6
0,5
5
-0.27
-0.55
-
mA
4.6
0
5
-125
-250
-
pA
-
0,5
5
-
0
0.1
IDD
IOL
XTAL
Output High Drive (Source) Current
(Except XTAL)
IOH
XTAL
Output Voltage Low-Level
VOL
Output Voltage High Level
VOH
Min.
CDP1802BC
Max.
Typ."
UNITS
pA
-
0,5
5
4.9
Input Low Voltage
VIL
0.5,4.5
-
5
VIH
0.5,4.5
-
5
5
-
1.5
Input High Voltage
3.5
-=-
5
0.4
0.5
-
Any
Input
0,5
5
±10-4
±1
0,5
0,5
±10-4
±1
-
-
5
5
-
15
30
mW
-
2
0.5
5
10
2.4
V
pA
CLEAR Input Voltage
VH
-
Schmitt Hysteresis
Input Leakage Current
3-State Output Leakage Current
liN
lOUT
Total Power Dissipation, f=5 MHza
Minimum Data Retention Voltage
Data Retention Current
Input Capacitance
Output Capacitance
VOR
lOR
CIN
COUT
VDD=VOR
VOO-2.4 V
-
V
-
7.5
15
pA
pF
"Typical values are for TA=25·C and nominal VDD.
ll.ldle "00" at M(OOOO), CL =50 pF.
..
DRAIN-TO-SOURCE VOLTAGE IVDS)-V
-3
-2
-t
-4
o
AM81 ENT TEMPERATURE =-40 TO
~
B5°C
c
•
1
,,§
.
z
~
GATE-TO-SOURCE VOLTAGE (VGS ).-5V
~
GATE-TO-SOURCE VOLTAGE (VOS):5V
92CS-34664
Fig. 4 • Minimum output high (source) current characteristics.
38
I
2
3
4
DRAIN-lO-SOURCE VOLTAGE IVoS}-V 92CS-34665
Fig. 5· Minimum output low (sink) current characteristics.
1800-Series Microprocessors and Microcomputers
CDP1802BC
5~ 75
z
o
!;i
50
~025
f
0.01
NOTES:
2
i~k~~:~3~1~!~O:(8107)
4
I
80 . 1
2
4
6 8 I
eloct< INPUT FREQUENCY (fCLI -
2
4
SPEC
VALUE
AT SOpF
II • 10
~:;S-346"
a
50
100
1&0
200
A LOAD CAPACITANCE IACL,-,F !'NOTE:::lErr'iit
.tes-!...,.
C L -50 pF
Fig. 6 - Typical power dissipation as a function of clock
frequency for BRANCH instruction and IDLE instruction.
Fig. 7 - Typical change in propagation delay all a
function of a change in load capacitance.
I
'----'-II--. XTAL
CONTROL AND
TIMING LOGIC
SCO\..STATE
SCI) CODES
Q LOGIC
~:afYSTEM
MW'R
F.ml
IMING
N O } :t/0
NI
OMMANDS
N2
R(El.I R(El.O
R( FI.I R(Fl:O
a-BIT BIDIRECTIONAL
BUS
BUS 5
Fig. 8 - CDP1802BC block diagram.
BUS6
BUS
9ZCM-34888RI
CLOCK
AO~SS
TPA
__~~H~I~BY~T~E~~________~L~OW~B~Y~TE~______~~~H~I~B~Y~T=E__-L______~L~OW~B~Y~T~E~_______L__
-rI'--________----lIlL_________
TPB __________________
...---, ______________________Ir---1L---
~I
I~
L-_..Jr~A------------_[::::::V~A~L~ID~I~N~PU~T~OA~T~A~::::J~L________~VA~L~I~O~O~U~TP~U~T~DA~~~A______~t__
Fig. 9 - Basic dc timing waveforms, one instruction cycle.
39
RCA CMOS LSI Products
CDP1802BC
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bus):
TPA, TPB (2 Timing Pulses):
8-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and 1/0 devices.
Positive pulses that occur once in each machine cycle (TPB
follows TPA). They are used by I/O controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the
higher-order byte of the 16-bit memory address. TPA is
suppressed in IDLE when the CPU is in the load mode.
NO to N2 (1/0) Lines):
Activated by an 110 instruction to signal the 1/0 control logic
of a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device
selection codes to the 1/0 devices (independently or
combined with the memory byte on the data bus when an 1/0
instruction is being executed). The N bits are low at all times
except when an 1/0 instruction is being executed. During this
time their state is the same as the corresponding
bits in the N register.
The direction of data flow is defined in the 1/0 instruction by
bit N3 (internally) and is indicated by the level of the MRD
Si~nal.
M..Q=VCC: Data from I/O to CPU and Memory
MRD=VSS: Data from Memory to 1/0
MAO to MA7 (8 Memory Address Lines):
In each cycle, the higher-order byte of a 16-bit CPU memory
address appears on the memory address lines MAO-7 first.
Those bits required by the memory system can be strobed
into external address latches by timing pulse TPA. The loworder byte of the 16-bit address appears on the address lines
after the termination of TPA. Latching of all 8 higher-order
address bits would permit a memory system of 64K bytes.
MWR (Write Pulse):
A negative pulse appearing in a memory-write cycle, after the
address lines have stabilized.
ffi to m (4 Flags):
Mii5 (Read Level):
These inputs enable the 1/0 controllers to transfer status
information to the processor. The levels can be tested by the
conditional branch instructions. They can be used in conjunction with the INTERRUPT request line to establish
interrupt priorities. These flags can also be used by 1/0
devices to "call the attention" of the processor, in which case
the program must routinely test the status of these flag(s).
The flag(s) are sampled at the beginning of every S1 cycle.
Mow level on MRD indicates a memory read cycle. It can be
used to control three-state outputs from the addressed
memory which may have a common data input and output
bus. If a memory does not have a three-state high-impedance
output, M'R'5 is useful for driving memorylbus separator
gates. It is also used to indicate the direction of data transfer
during an I/O instruction. For additional information see
Table I.
INTERRUPT, DMA-IN, DMA-OUT (3 1/0 Requests)
Q:
These inputs are sampled by the COP1802BC during the
interval between the leading edge of TPB and the leading
edge of TPA.
Single bit output from the CPU which can be set or reset
under program control. During SEQ or REQ instruction
execution, Q is set or reset between the trailing edge of TPA
and the leading edge of TPB.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X isset to 2; designator P is set
to 1; interrupt enable is reset to 0 (inhibit); and instruction
execution is resumed. The interrupt action requires one
machine cycle (S3).
DMA Action: Finish executing current instruction; R(O)
pOints to memory area for data transfer; data is loaded into or
read out of memory; and increment R(O).
Note: In the event of concurrent OMA and Interrupt requests,
DMA-IN has priority followed by DMA-OUT and then
Interrupt.
SCO, SC1, (2 State Code Lines):
These outputs indicate that the CPU is: 1) fetching an
instruction, or 2) executing an instruction, or 3) processing a
DMA request, or 4) acknowledging an interrupt request. The
levels of state code are tabulated below. All states are valid at
TPA. H=VCC, L=VSS.
State Type
SO
S1
S2
S3
(Fetch)
(Execute)
(DMA)
(Interrupt)
State Code Lines
SC1
SeD
L
L
L
H
H
L
H
H
CLOCK:
Input for externally generated single-phase clock. A typical
clock frequency is 5 MHz at VCC= VOO= 5 volts. The
clock is counted down internally to 8 clock pulses per
machine cycle.
XTAL:
Connection to be used with clock input terminal, for an
external crystal, if the on-chip oscillator is utilized. The
crystal is connected between terminals 1 and 39 (CLOCK and
XTAL) in parallel with a resistance (10 megohms typ.).
Frequency trimming capaCitors may be required at terminals
1 and 39. For additional information, see ICAN-6565.
WAiT, CLEAR (2 Control Lines):
Provide four control modes as listed in the following truth
table:
eLEAR
L
L
H
H
WAIT
L
H
L
H
MODE
LOAD
RESET
PAUSE
RUN
VDD, VSS, Vee (Power Levels):
The internal voltage supply VDD is isolated from the
I nput/Output voltage supply VCC so that the processor may
operate at maximum speed while interfacing with peripheral
devices operating at lower voltage. VCC must be less than or
equal to VOD. All outputs swing from VSS to VCC. The
recommended input voltage swing is VSS to Vcc.
40
..
1800-Serles Microprocessors and Microcomputers
CDP1802BC
ARCHITECTURE
The CPU block diagram is shown in Fig. 8. The principal
feature of this system is a register array (R) consisting of
sixteen 16-bit scratch pad registers. Individual registers in
the array (R) are designated (selected) by a 4-bit binar.y
code from one of the 4-bit registers labeled N. p. and X. The
contents of any register can be directed to anyone of the
following three paths:
1. the external memory (multiplexed. higher-order byte
first. on to 8 memory address lines);
2. the D register (either of the two bytes can be gated to
D);
3. the increment/llecrement circuit where it is increased
or decreased by one and stored back in the selected
16-blt register.
The three paths. depending on the nature of the instruction.
may operate independently or in various combinations in
the same machine cycle.
With two exceptions. CPU instructions consist of two 8clock-pulse machine cycles. The first cycle is the fetch
cycle. and the second-and third if necessary-are execute
cycles. During the fetch cycle the four bits in the P
designator select one ofthe 16 registers R(P) as the current
program counter. The selected register R(P) contains the
address of the memory location from which the instruction
is to be fetched. When the instruction is read out from the
memory. the higher-order 4 bits of the Instruction byte are
loaded into the I register and the lower-order 4 bits Into the
N register. The content of the program counter is automatically incremented by one so that R(P) is now "pointing"
to the next byte in the memory.
The X designator selects one of the 16 registers R(X) to
"point" to the memory for an operand (or data) in certain
ALU or I/O operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. designate one of the 16 registers in R to be acted upon
during register operations;
2. indicate to the I/O devices a com mand code or deviceselection code for peripherals;
3. indicate the specific operation to be executed during
the ALU instructions. types of tests to be performed
during the Branch instructions. orthe specific operation
required in a class of miscellaneous instructions (70-73
and 78-7B);
4. indicate the value to be loaded into P to designate a new
register to be used as the program counter R(P);
5. indicate the valueto be loaded into Xto designate a new
register to be used as data pOinter R(X).
The registers in R can be assigned by a programmer in three
different ways: as program counters. as data pointers. or as
scratch pad locations (data registers) to hold two bytes of
data.
Program Counter.
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other
registers in R can be used as subroutine program counters.
By a single Instruction the contents of the P register can be
changed to effect a "call" to a subroutine. When interrupts
are being serviced. register R(1) is used as the program
counter for the user's interrupt servicing routine. After
reset. and during a DMA operation. R(O) is used as the
program counter. At all other times the register designated
as program counter is at the discretion of the user.
Data Polnt.r.
The registers in R may be us.d as data polnt.rs to Indlcat. a
location In memory. The register d.slgnat.d by X (I ••.• R(X»
points to memory for the following Instructions (S88 Tabl.
I):
1. ALU operations F1-F5. F7. 74. 75. 77;
2. output Instructions 61 through 67;
3. input instructions 69 through 6F;
4. certain miscellaneous Instructions -70-73. 78. 60. FO.
The register designated by N (i.e .• R(N» points to memory
for the "load 0 from memory"lnstructions ON and 4N and
the "Store D" Instruction 5N. The register designated by P
(i.e .• the program counter) is used as the data pOinter for
ALU Instructions F8-FD. FF. 7C. 7D. 7F. During these
instruction executions. the operation Is referred to as "data
immediate".
Another Important use of R as a data pOinter supports the
built-in Dlrect-Memory-Access (OMA) function. When a
DMA-In or DMA-Out request Is received. one machine
cycle is "stolen". This operation occurs at the end of the
execute machine cycle In the current Instruction. Register
R(O) is always used as the data pOinter during the OMA
operation. The data is read from (DMA-Out) or written Into
(DMA-In) the memory location pOinted to by the R(O)
register. At the end of the transfer. R(O) Is Incremented by
one so that the processor Is ready to act upon the next DMA
byte transfer request. This feature In the 1800-serles
architecture saves a substantial amount of logic when fast.
exchanges of blocks of data are required. such as with
magnetic discs or during CRT-display-refresh cycles.
Data Regilt.,.
When registers in R are used to store bytes of data. four
instructions are provided which allow D to receive from or
write into either the higher-order- or lower-order-byte
portions of the register deSignated by N. By this mechanism
(together with loading by data Immediate) program pointer
and data pOinter designations are initialized. Also. this
technique allows scratch pad registers In R to be used to hold
general data. By employing increment or decrement Instructions. such registers may be used as loop counters.
The Q flip Flop
a.
can be set or reset by instruction and
An internal flip flop.
can be sensed by conditional branch instructions. The output
of a is also available as a microprocessor output.
Int.rrupt Servicing
Register R(1) Is always used as the program counter whenever
interrupt servicing is initiated. When an interrupt request
occurs and the interrupt Is allowed by the program (again.
nothing takes place until the completion of the current
instruction). the contents of the X and P registers are stored
in the temporary register T. and X and P are set to new values;
hex digit 2 in X and hex digit 1 in P. Interrupt Enable Is
automatically de-activated to Inhibit further Interruptions.
The user's Interrupt routine Is now in control; the contents of
T may be saved by means of a single Instruction (78) In the
memory location pOinted to by R(X). At the conclusion of the
Interrupt. the user's routine may restore the pre-Interrupted
value of X and P with a Single Instruction (70 or 71). The
Interrupt-Enable flip flop can be activated to permit further
interrupts or can be disabled to prevent them.
41
I
RCA CMOS LSI Products
CDP1802BC
cPU Regia'" Summary
0
p
8 Bits
1 Bit
8 Bits
16 Bits
4 Bits
X
4 Bits
OF
B
R
Data Register (Accumulator)
Data Flag (ALU Carry)
Auxiliary Holding Register
1 of 16 Scratch pad Registers
Designates which register is
Program Counter
Designates which register Is
Data Pointer
4 Bits
4 Bits
N
I
T
8 Bits
IE
Q
1 Bit
1 Bit
Holds Low-Order Instr. Digit
Holds High-Order Instr. Digit
Holds old X, P after Interrupt
(X is high nibble)
Interrupt Enable
Output Flip Flop
CDP1802 Control Mod.a
The WAiT and CLEAR lines provide four control modes as
listed in the following truth table:
CLEAii
L
L
H
H
WAIT
L
H
L
H
MODE
LOAD
RESET
PAUSE
RUN
The function of the mtldes are defined as follows:
Load
Holds the CPU in the IDLE execution state and allows an 1/0
device to load the memory without the need for a "bootstrap"
loader. It modifies the IDLE condition so that DMA-IN
operation does not force execution of the next instruction.
Reaet
Registers I, N, Q are reset, IE is set and O's (VSS) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU Is placed in 51. The first machine cycle
after termination of reset is an initialization cycle which
requires 9 clock pulses. During this cycle the CPU remains in
51 and registers X, P, and R(O) are reset. Interrupt and DMA
servicing are suppressed during the initialization cycle. The
next cycle is an SO, 51, or an 52 but never an 53. With the use
of a 71 instruction followed by 00 at memory locations 0000
and 0001, this feature may be used to reset IE, so as to
preclude interrupts until ready for them. Powerup reset can
be realized by connecting an RC network directly to the
CLEAR pin, since it has a Schmitt-triggered input, see Fig. 10.
Paule
Stops the internal CPU timing generator on the first negative
high-to-Iow transition of the Input clock. The oscillator
continues to operate, but subsequent clock transitions are
Ignored.
Bun
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation on the first
negative high-to-Iow transition of the input clock. When
initiated from the Reset operation, the first machine cycle
following Reset is always the initialization cycle. The Initialization cycle Is then followed by a DMA (82) cycle or fetch
(SO) from location 0000 in memory.
RUN-MODE STATE TRANSITIONS
The CDP1802BC CPU state transitions when in the RUN and
RESET modes are shown in Fig. 11. Each machine cycle
requires the same period of time, 8 clock pulses, except the
initialization cycle, which requires 9 clock pulses. The
execution of an instruction requires either two or three
machine cycles, SO followed by a single 51 cycle or two 51
cycles. 52 is the response to a DMA request and 53 Is the
interrupt response. Table II shows the conditions on Data
Bus and Memory-Address lines during all machine states.
(LONG BRANCH.
LONG SKIP, NOP, ETC)
Vee
CDPIB02BC
The RC time constant
should be greater than
the oscillator start-up time
(typically 20 ms).
DMA
PRIORITY:
~~~~: so, 81
DlfAOUT
92CS - 34669RI
Fig. 10 - Reset diagram.
42
iNT
12CS-33812
Fig. 11 - State transition diagram.
1800-Series Microprocessors and Microcomputers
CDP1802BC
INSTRUCTION SET
The CPU instruction summary is given in Table I. Hexadecimal
notation is used to refer to the 4-bit bi nary codes.
R(W).O: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
In all registers bits are numbered from the least significant bit
(LSB) to the most significant bit (MSB) starting with O.
Operation Notation
M(R(N» - 0; R(N) + 1 - R(N)
R(W): Register designated by W, where
W=N orX, orP
This notation means: The memory byte pOinted to by R(N) II
loaded into 0, and R(N) Is Incremented by 1.
TABLE I - INSTRUCTION SUMMARY (See Note. following table. pp. 11 end 12)
INSTRUCTION
MEMORY REFERENCE
LOADVIAN
LOAD ADVANCE
LOAD VIAX
LOAD VIA X AND ADVANCE
LOAD IMMEDIATE
STORE VIA N
STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
DECREMENT REG N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
LOGIC OPERATIONS'
OR
OR IMMEDIATE
OP
CODE
MNEMONIC
OPERATION
LON
LOA
LOX
LDXA
LDI
STR
STXD
ON
4N
FO
72
Fa
5N
73
M(R(N»-D; FOR N"NOT 0
M(R(N»-D; (RN)+1 '-R(N)
M(R(X»-D
M(R(X))-D; R(X)+1-R(X)
M(R(P»-D; R(P)+1-R(P)
D-M(R(N»
D-M(R(X»; R(X)-1-R(X)
INC
DEC
IRX
GLO
PLO
GHI
PHI
1N
2N
60
aN
AN
9N
BN
R(N)+1-R(N)
R(N)-1-R(N)
R(X)+1-R(X)
R(N).O-D
D-R(N).O
R(N).1-D
D-R(N).1
OR
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
XOR
XRI
F3
FB
AND
AND IMMEDIATE
AND
ANI
F2
FA
SHIFT RIGHT
SHR
F6
M(R(X)) OR 0-0
M(R(P» OR 0-0;
R(P)+1-R(P)
M(R(X)) XOR 0-0
M(R(P)) XOR 0-0;
R(P)+1-R(P)
M(R(X» AND 0-0
M(R(P» AND 0-0;
R(P)+1-R(P)
SHIFT 0 RIGHT, LSB(D)-DF,
O-MSB(D)
SHIFT 0 RIGHT, LSB(D)-DF,
DF-MSB(D)
SHIFT RIGHT WITH CARRY
SHRC
RING SHIFT RIGHT
SHIFT LEFT
RSHR
SHL
SHIFT LEFT WITH CARRY
SHLC
RING SHIFT LEFT
RSHL
I
76§
FE
I
7E§
•
SHIFT 0 LEFT. MSB(D)-DF,
o-LSS(D)
SHIFT 0 LEFT. MSS(D)-OF,
OF-LSS(D)
43
RCA CMOS LSI Products
CDP1802BC
TABLE I - INSTRUCTION SUMMARY (Confd)
44
OP
CODE
INSTRUCTION
ARITHMETIC OPERATIONS;
ADD
ADD IMMEDIATE
ADD WITH CARRY
ADD WITH CARRY, IMMEDIATE
ADD
ADI
ADC
ADCI
F4
FC
74.
7C
SUBTRACT 0
SUBTRACT 0 IMMEDIATE
SO
SOl
F5
FD
SUBTRACT 0 WITH BORROW
SUBTRACT 0 WITH
BORROW,IMMEDIATE
SUBTRACT MEMORY
SUBTRACT MEMORY IMMEDIATE
SOB
SDBI
75
70
SM
SMI
F7
FF
MNEMONIC
SUBTRACT MEMORY WITH BORROW
5MB
SUBTRACT MEMORY WITH
5MBI
BORROW, IMMEDIATE
BRANCH INSTRUCTIONS-SHORT BRANCH
SHORT BRANCH
BR
NBR
NO SHO~T BRANCH (SEE SKP)
SHORT BRANCH IF 0=0
BZ
30
38§
32
SHORT BRANCH IF 0 NOT 0
BNZ
3A
SHORT BRANCH IF DF=l
SHORT BRANCH IF POS OR ZERO
SHORT BRANCH IF EOUAL OR
GREATER
SHORT BRANCH IF DF=O
SHORT BRANCH IF MINUS
SHORT BRANCH IF LESS
SHORT BRANCH IF O=F
BDF
BPZ
BGE
SHORT BRANCH IF 0=0
BNO
39
SHORT BRANCH IF EF1=1
(EF1=VSS)
SHORT BRANCH IF EF1=0
(EF1=VCC)
SHORT BRANCH IF EF2=1
(EF2=VSS)
SHORT BRANCH IF EF2=0
(EF2=VCC)
SHORT BRANCH IF EF3=l
(EF3=VSS)
SHORT BRANCH IF EF3=O
(EF3=VCC)
B1
34
BN1
3C
B2
35
BN2
3D
B3
36
BN3
3E
BNF
BM
BL
BO
77
7F
I
I
33§
OPERATION
M(R(X»+D-DF, 0
M(R(P»+D-DF,D; R(P)+l-R(P)
M(R(X»+D+DF-DF, 0
M(R(P»+D+DF-DF, 0
R(P)+l-R(P)
M(R(X»-D-DF, 0
M(R(P»-D-DF, 0;
R(P)+l-R(P)
M(R(X»-D-(NOT DF)-DF, 0
M(R(P»-D-(NOT DF)-DF, 0;
R(P)+l-R(P)
D-M(R(X»-DF, 0
D-M(R(P»-DF, 0;
R(P)+l-R(P)
D-M(R(X»-(NOT DF)-DF, 0
D-M(R(P»-(NOT DF)-DF, 0
R(P)+l-R(P)
M(R(P»-R(P).O
R(P)+l-R(P)
IF 0=0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF 0 NOT 0, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF DF=l, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
3B§
IF DF=O, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
31
IF 0=1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF 0=0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF1=l, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF1=O, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF2=l, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF2=O, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF3=l, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF3=O, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
1800-Serles Microprocessors and Microcomputers
CDP1802BC
TABLE I-INSTRUCTION SUMMARY (Confd)
INSTRUCTION
OP
CODE
MNEMONIC
OPERATION
BRANCH INSTRUCTIONS-SHORT BRANCH
B4
37
BN4
3F
BRANCH INSTRUCTIONS-LONG BRANCH
LONG BRANCH
LBR
co
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF 0=0
NLBR
LBZ
C2
LONG BRANCH IF 0 NOT 0
LBNZ
CA
LONG BRANCH IF OF=1
LBOF
C3
LONG BRANCH IF OF=O
LBNF
CB
LONG BRANCH IF Q=1
LBQ
C1
LONG BRANCH IF Q=O
LBNQ
C9
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF 0=0
SKP
LSKP
LSZ
38§
C8§
LONG SKIP IF 0 NOT 0
LSNZ
C8
LONG SKIP IF OF=1
LSOF
CF
LONG SKIP IF OF=O
LSNF
C7
LONG SKIP IF Q=1
LSQ
CO
LONG SKIP IF Q=O
LSNQ
C5
LONG SKIP IF IE=1
LSIE
CC
SHORT BRANCH IF EF4=1
(EF4=VSS)
SHORT BRANCH IF EF4=0
(EF4=VCC)
C8§
CE
IF EF4=1. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF4=O. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
R(P)+2-R(P)
IF 0=0. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF 0 NOT O. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF=1. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF=O. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF Q=1. M(R(P))-R(P).1
M(R(P)+1)-R(R).0
ELSE R(P)+2-R(P)
IF Q=O. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
I
R(P)+1-R(P)
R(P)+2-R(P)
IF 0=0, R(Pl..+2-R(P)
ELSE CONTINUE
IF o NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF OF=1. R(P)+2-R(P)
ELSE CONTINUE
IF OF=O. R(P)+2-R(P)
ELSE CONTINUE
IF Q=1. R(P)+2-R(P)
ELSE CONTINUE
IF Q=O. R(P)+2-R(P)
ELSE CONTINUE
IF IE::1. R(P)+2-R(P)
ELSE CONTINUE
45
RCA CMOS LSI Products
CDP1802BC
TABLE I - INSTRUCTION SUMMARY (Confd)
INSTRUCTION
CONTROL INSTRUCTIONS
IDLE
OP
CODE
MNEMONIC
IDL
cot
NO OPERATION
SETP
SET X
SET 0
RESET 0
SAVE
PUSH X,P TO STACK
NOP
SEP
SEX
C4
REO
SAV
MARK
ON
EN
7B
7A
78
79
RETURN
RET
70
DISABLE
DIS
_71
INPUT-OUTPUT BYTE TRANSFER
OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT,",
OUTPUTS
OUTPUT 6
OUTPUT 7
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUTS
INPUT 6
INPUT 7
SE~
OUT 1
ouT!:!
OUT3
OUT4
OUTS
OUT 6
OUT7
INP 1
INP2
INP3
INP4
INPS
INP6
INP7
61
62
63
64
65
66
67
69
6A
6B
6C
60
6E
6F
OPERATION
WAIT FOR DMA OR INTERRUPT;
M(R(O»-BUS
CONTINUE
N-P
N-X
1-0
0-0
T-M(R(X»
(X,P)-T; (X,P)-M(R(2»
THEN P-X; R(2)-1-R(2)
M(R(X»-(X,P); R(X)+1-R(X)
1-IE
M(R(X»-(X,P); R(X)+1-R(X)
O-IE
M(R(X»-BUS;R(X)+1-R(X); N LINES=1
M(R(X»-BUS;R(X)+1-R(X); N LlNES=2
M(R(X»-BUS;R(X)+1-R(X); N LINES=3
M(R(X»-BUS;R(X)+1-R(X); N LINES=4
M(R(X»-BUS;R(X)+1-R(X); N LINES=S
M(R(X»-BUS;R(X)+1-R(X); N LlNES=6
M(R(X»-BUS;R(X)+1-R(X); N LlNES=7
BUS-M(R(X»; BUS-O; N LINES=1
BUS-M(R(X»; BUS-O; N LlNES=2
BUS-·M(R(X»; BUS-O; N LlNES=3
BUS-M(R(X»; BUS-O; N LlNES=4
BUS-M(R(X»; BUS-O; N LlNES=S
BUS-M(R(X»; BUS-O; N LINES=6
BUS-M(R(X»; BUS-O; N LlNES=7
hHE ARITHMETIC OPERATIONS AND THE SHIFT INSTRUCTIONS ARE THE ONLY INSTRUCTIONS·THAT CAN ALTER THE OF.
AN ADD INSTRUCTION:
DF=1 DENOTES A CARRY HAS OCCURRED
DF=O DENOTES A CARRY HAS NOT OCCURRED
AFTER A SUBTRACT INSTRUCTION:
DF=1 DENOTES NO BORROW. 0 IS A TRUE POSITIVE NUMBER
DF=O DENOTES A BORROW. 0 IS TWO'S COMPLEMENT
THE SYNTAX "-(NOT OF)" DENOTES THE SUBTRACTION OF THE BORROW
AFTER
§THIS INSTRUCTION IS ASSOCIATED WITH MORE THAN ONE MNEMONIC. EACH MNEMONIC IS INDIVIDUALLY LISTED.
#AN IDLE INSTRUCTION INITIATES A REPEATING S1 CYCLE. THE PROCESSOR WILL CONTINUE TO IDLE UNTIL AN 1/0 REQUEST
(INTERRUPT,
OR DMA-OUT) IS ACTIVATED. WHEN THE REQUEST IS ACKNOWLEDGED. THE IDLE CYCLE IS TERMINATED
AND THE 1/0 REQUEST IS SERVICED, AND THEN NORMAL OPERATION IS RESUMED.
0MA-iN.
Note. for TABLE I
1. Long-Branch, Long-Skip and No Op instructions are
the only instructions that require three cycles to
complete (1 fetch +2 execute).
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
The long-branch instructions can:
a) Branch unconditionally
b) Test for 0=0 or D~
'c) Tes! for OF=O or DF=1
d) Test for 0=0 or 0=1
46
e) effect an unconditional no branch
If the tested condition is met, then branching takes
place; the branching address bytes are loaded in the
high- and low-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
If the tested condition is not met, the branching
address bytes are skipped over, and the next instruction in sequence is fetched and executed. This
operation is taken for the case of unconditional no
branch (NLBR).
1800-Serles Microprocessors and Microcomputers
CDP1802BC
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85 0 C, CL=50 pF, VDD±5%, except al noted.
Propagation Delay Times:
Clock to TPA. TPB
Clock-to-Memory High-Address Byte
Clock-to-Memory Low-Address Byte Valid
Clock to MAD
Clock to MWA
Clock to (CPU DATA to BUS) Valid
Clock to State Code
Clock to 0
Clock to N (0-2)
Minimum Setup and Hold Times:
Data Bus Input Setup
Data Bus Input Hold
~Setup
DMA Hold
Interrupt Setup
Interrupt Hold
WATT Setup
EF1-4 Setup
EFl-4 Hold
Minimum Pulse Width Times:
Ci::'EAR Pulse Width
CLOCK Pulse Width
LIMITS
Typ.Max.
VCC
(V)
VDD
(V)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
200
475
175
175
175
250
250
200
275
' 275
225
375
400
300
350
tsu
tHtsu
tsu
tH-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-20
125
0
100
-75
75
20
-30
100
0
150
30
150
0
125
40
0
150
tWLtWL
5
5
5
5
100
90
150
100
CHARACTERISTIC
tPLH. tpHL
tpLH. tPHL
tpLH. tPHL
tpLH. tPHl
tPLH. tpHL
tPLH. tPHL
tPLH. tpHL
tPLH. tpHL
tPLH. tpHL
uNift".
300
525
250
ns
tsu
tHtsu
tH-
I
-TYPical values are for TA=25°C and nominal VDD.
-Maximum limits of minimum characteristics are the values above which all devices function.
Notes for TABLE I (Continued)
2. The short-branch instructions are two bytes long. The
first byte specifies the condition to be tested. and the
second specifies the branching address.
The short-branch instruction can:
a) Branch unconditionally
b) Test for 0=0 or 0#0
c) Test for DF=O or DF=l
d) Test for 0=0 or 0=1
e) Test the status (1 or 0) of the four EF flags
f) Effect an unconditional no branch
If the tested condition is met. then branching takes
place; the branching address byte is loaded into the
low-order byte position of the current program
counter. This effects a branch within the current 256byte page of the memory. i.e .• the page wh ich holds the
branching address. If the tested condition is not met.
the branching address byte is skipped over. and the
next instruction in sequence is fetched and executed.
This same action is taken in the case of unconditional
no branch (NBA).
3. The skip instructions are one byte long. There is one
Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Skip instruction takes 2 cycles
to complete (1 fetch + 1 execute). Its action Is to skip
over the byte following it. Then the next instruction In
sequence is fetched and executed. This SKP instruction
is identical to the unconditional no-branch Instruction
(NBA) except that the skipped-over byte Is not
considered part of the program.
The Long-Skip instructions take three cycles to
complete (1 fetch +2 execute).
They can:
a) Skip unconditionally
b) Test for 0=0 or D#O
c) Test for DF=O or DF=l
d) Test for 0=0 or 0=1
e) Test for IE=l
If the tested condition is met. then Long Skip takea
place; the current program counter is Incremented
twice. Thus two bytes are skipped over and the next
instruction in sequence is fetched and executed. If the
tested condition is not met. then no action is taken.
Execution is continued by fetching the next instruction
in sequence.
47
RCA CMOS LSI Products
CDP18028C
TPA
TPB
MEMORY
ADDRESS
(ME~~~ ~
~IIPHL~
____
~ ~
__
______
~
____________
---------~~~----!__+_-------_h"""'"
READ CYCLE)
MWii
':~tf~RJYCLE)
~-+__~~_I~-JH
i--'
I
I
DATA FROM
CPU TDBUS
STATE
CODES
Q
NO,NI,N2
(:1:/0
EXECUTION
CYCLE)
15MA
REQUEST
INTERRUPT
1
I
lSU
UM~~~~)
IH
1
IFLAG L I N
I
\.. -I- IH ~I
ESVSU
~
ISAMPLED
(IN SI)
I I
EFI-4
----
~'---+---:
_______-+1__..,
I
~
--------..,t:::r
ANY NEGATIVE
TRANSITION
NOTES'
I. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE
2. ALL MEASUREMENTS ARE REFERENCED TO !5O"Io POINT OF THE
WAVEFORMS
.
3. SHADED AREAS INDICATE "DON'T CARE" OR UNDEFINED STATE;
MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD
Fig. 12 - Timing waveforms.
48
92CL-33869RI
1800-Serles Microprocessors and Microcomputers
CDP1802BC
TPA
____~r__\L_____________________
TP8
LDW ORDER
ADDRESS BYTE
MEMORY
ADDRESS
1 4 - - - - 'AAD - - -__
MlfD
( MEMORYl
READ CYCLEl _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"'"
MWR
(MEMORY
WRITE CYCLEl
DATA FROM
CPU TO BUS
DATA FROM
BUS TO CPU
.c..::;c.c..::LL:LLLL..CLt.::LL'LL.LL.u..~'LL.L.LL.L.""'~~~""'''I''----.t''''.....~
I
92CM-34922
Fig. 13 - Clock frequency dependent relative timing waveforms.
-
-
TIMING SPECIFICATIONS a8 a function of T (T-1lfCLOCK) at TA--40 to +85°C
CHARACTERISTIC
High-Order Memory-Address Byte
Set Up to TPA
Time
"\.
tSAA
High-Order Memory-Address Byte
Hold after TPA Time
tHAA
Low-Order Memory-Address Byte
Hold after WR Time
tHAW
CPU Data to Bus Hold
after WR Time
tHDW
Low-Order Memory-Address Byte
Hold after TPB Time
tHAB
~ Hold after TPB Time
tHRB
Reqlli[ed Memory Access Time
Addl>ess to Data
tAAD
Vce
(V)
VDD
(V)
liMITS
Typ.Min.
5
5
2T-325 2T-275
5
5
T/2-25
T/2-15
5
5
T-30
T+O
5
5
T-175
T-125
5
5
T/2+O TI2+100
5
5
T/2-25
5
5
5T-225 51-175
UNITS
ns
T/2+O
-Typical 'values are for T A=25°C and nominal Vee.
49
RCA CMOS LSI Products
CDP1802BC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STAT ES
STATE
I
N
Sl
Sl
SO
RESET
INITIALIZE
NOT PROGRAMMER
ACCESSIBLE
FETCH
0
0
1
2
3
4
Sl
MNEMONIC
5
6
6
0
1-F
D-F
O-F
D-F
D-F
O-F
IDL
LON
INC
DEC
SHORT
BRANCH
LOA
3
4
5
6
7
9
A
B
C
0
E
F
STR
IRX
OUT1
OUT2
OUT3
OUT4
OUT5
OUT 6
OUT7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
0
RET
1
DIS
0
1
2
N
DATA
MEMORY
OPERATION
BUS
ADDRESS
MRD
MWR
LINES
NOTESG
O-I,N,Q,X,P;
1-IE
OOOO-R
00
XXXX
1
1
0
A
00
XXXX
1
1
0
B
MRP-I, N;
RP+1-RP
IDLE
MRN-D
RN+1-RN
RN-1-RN
TAKEN;
MRP-RP.O
NOT TAKEN;
RP+1-RP
MRN-D;
MRP
RP
0
1
0
C
MRO
MRN
FLOAT
FLOAT
RO
RN
RN
RN
0
0
1
1
1
1
1
1
0
0
0
0
03
3
1
1
MRP
RP
0
1
0
MRN
RN
0
1
0
3
0
MRX
RN
RX
1
0
1
0
0
1
2
2
0
MRX
RX
0
1
DATA
FROM
I/O
DEVICE
RX
1
0
RN+1-RN
D-MRN
RX+1-RX
MRX-BUS;
RX+1-RX
BUS-MRX,D
-
-
3
4
5
6
7
1
2
3
4
3
2
6
5
5
6
7
MRX-(X,P);
RX+1-RX; 1-IE
MRX
RX
0
1
0
3
MRX-(X,P);
MRX
RX
a
1
a
3
RX+1-RX; a-IE
7
2
LDXA
MRX-D;
RX+1-RX
MRX
RX
a
1
a
3
3
STXJ;)
D-MRX;
RX-1-RX
0
RX
1
a
0
2
4
ADC
MRX+D+
DF-DF,D
MRX
RX
0
1
a
3
50
...
1800-Series Microprocessors and Microcomputers
CDP1802BC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STATES (CONT'D)
STATE
51
I
7
8
9
A
B
N
5
MNEMONIC
5DB
6
5HRC
7
5MB
8
9
5AV
MARK
A
B
C
REO
5EO
ADCI
D
5DSI
E
5HLC
F
5MBI
o-F
o-F
o-F
o-F
GLO
GHI
PLO
PHI
51#1
#2
0-3,
51#1
#2
51#1
#2
51#1
#2
LONG
BRANCH
8-B
C
5
6
7
C
D
E
F
LONG
5KIP
51#1
4
#2
DATA
BUS
MRX
MEMORY
ADDRESS
RX
MRD
0
MWR
1
N
LINES
0
NOTESG
FLOAT
RX
1
1
0
1
MRX
RX
0
1
0
3
T
T
RX
R2
1
1
0
0
0
0
2
2
FLOAT
FLOAT
MRP
RP
RP
RP
1
1
0
1
0
1
1
1
0
0
3
MRP
RP
0
1
0
3
FLOAT
RP
1
1
0
1
MRP
RP
0
1
0
3
RN.O
RN.1
D
D
MRP
RN
RN
RN
RN
RP
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
4
M(RP+1)
RP+1
0
1
0
4
MRP
RP
0
1
0
4
M(RP+1)
RP+1
0
1
0
4
MRP
RP
0
1
0
4
TAKEN: RP+1-RP
M(RP+1)
RP+1
0
1
0
4
NOT TAKEN:
NO OPERATION
NOT TAKEN:
MRP
RP
0
1
0
4
OPERATION
MRX-DDFN-DF,D
L5B(D)-DF;
DF-M5BIDI
D-MRXDFN-DFD
T-MRX
(X,P)-T, MR2;
P-X· R2-1-R2
0-0
1-0
MRP+D+
DF-DF,D; RP+1
MRP-DDFN-DF,D;
RP+1
M5B(D)-DF;
DF-L5B(D)
D-MRPDFN-DF,D;
RP+1
RN.O-D
RN.1-D
D-RN.O
D-RN.1
TAKEN: MRP-B;
RP+1-RP
TAKEN: B-RP.1;
MRP-RP.O
NOT TAKEN:
RP+1-RP
NOT TAKEN:
RP+1-RP
TAKEN: RP+1-RP
-
3
1
MRP
RP
0
1
0
4
NO OPERATION
NO OPERATION
MRP
RP
0
1
0
4
NO OPERATION
MRP
RP
0
1
0
4
•
NOP
51
RCA CMOS LSI Products
CDP1802BC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STATES (CONrD)
STATE
I
N
MNEMONIC
0
o-F
SEP
E
o-F
SEX
LOX
OR
AND
0
1
2
3
4
5
7
6
Sl
F
S2
S3
B
XOR
ADD
SO
SM
SHR
DATA
MEMORY
OPERATION
N-P
BUS
ADDRESS
-MRD
NN
RN
1
N-X
MRX-D
MRXOR 0-0
NN
MRX
-.B/:Il
RX
-.1
0
MRX
RX
FLOAT
MRXANDD-D
MRXXOR 0-0
MRX+D-DF,D
MRX-D-DF,D
D-MRX-DFD
LSB(D)-DF;
O-MSB(D)
LDI
MRP-D;
9
ORI
RP+1-RP
MRPOR 0-0;
A
ANI
RP+1-RP
MRPANDD-D;
B
XRI
RP+1-RP
MRPXOR 0-0;
C
ADI
0
SOl
RP+1-RP
MRP+D-DF,D;
RP+1-RP
MRP-D-DF,D;
F
SMI
RP+1-RP
D-MRP-DF,D;
E
SHL
RP+1-RP
MSB(D)-DF;
O-LSB(D)
DMAIN
BUS-MRO;
DMAOUT
RO+1-RO
MRO-BUS;
INTERRUPT
RO+1-RO
X,P-T; O-IE
--
MWR
N
LIMES
NOTESQ
1
1
o .
0
1
1
0
3
0
1
0
3
RX
1
1
0
1
MRP
RP
0
1
0
3
FLOAT
RP
1
1
0
1
DATA FROM
1/0 DEVICE
RO
1
0
0
F, 7
MRO
RO
0
1
0
F,B
FLOAT
RN
1
1
0
9
M(RO-1)
RO-1
0
1
0
E,3
1
1-P' 2-X
Sl
LOAD
IDLE
(CLEAR, WAIT=O)
NOTES:
A. IE=l, TPA, TPB suppressed, state=Sl.
B. BUS=O for entire cycle.
C. Next state always Sl.
D. Wait for DMA or INTERRUPT.
E. Suppress TPA, wait for DMA.
F. IN REQUEST has priority over OUT REQUEST.
G. Number refers to machine cycle. See Fig. 14 timing waveforms for machine cycles 1 through 9.
52
1800-Serles Microprocessors and Microcomputers
° ,
CLOCK
TPA
3
4
5
2
6
3
4
5
7
CDP1802BC
°
-.Jl'---_ _ _ _ _..JnL_ _ _ _ _---'nL_ _ _ _ _---'rlL_ _ _ _ _.....JrL----'IlL_ _ _ _ _---'rlL-_______..JIlL_________
TPB _ _ _ _ _ _ _ _ _ _.....JIIL_ _ _ _ _
~¢g~NE -r-------C~Y~C~L~E-"------~------~C~Y~C~LE~I~,,7.~1I----~------~C~Y~CL~E~I~n7.~21-----;;------C~Y~C~LFE~I"~.~31;---;-~C~Y"C~l~E~I"~+~.~I-
MA
HIGH ADD.
I
IHIGH ADD.I
LOW ADDRESS
LOW ADDRESS
IHIGH ADDI
LOW ADDRESS
F'GH
ADD)
LOWAOQRESS
,..
FIGHAOOI
General timing waveforms.
INSTRUCTION
===~FKET~C~HQI5~Oi[1===:c==JE~X~E£CU~T~E::J15~'l:'==:c==~F~ET~C~H:J!ISO~1===:J===JE~X!:ECS!U!!TIE:J!15!I'Ic:=I:1!FE!lT]C~H::Jilso!!i!C:
~MEMORY READ CYCLE--oo.-t-I.~-NON MEMORY CYCLE ---+--MEMORY READ CYCLE
--".+I__--NON.MEMORV CYClE~~~~gRV
I
MRO -------,
l CYCLE
I
MWR(HIGHI ------------------------------------------------------------------------------------------
~C~~R/;:
~$~
ALLOWABLE MEMORY ACCESS
tVALID OUTPUT
LVAUDOUTPUT
No. 1 Non-memory-cycle timing waveforms.
I NSTRU CTION -Ir-----~FE-;T-;::C;:;-H-;-;15~O';-----.------E,-;X,.,E"'c77uT;;E;-';C5,"'"I--·-.,--------,F"'E""TC;:;H-;--I"'50""-----;;------:E""X"'E"CU""T"'E--::15'"":-'----rooF ETCH
~
MRD
!---MEMORY READ CYCLE ---..f.--MEMORYWRITE CYCLE---!--- MEMORY READCYCLE----f.-MEMOAYWRlTE
~
1
I
(SOl
CYClE~~~~gRY
1
1 CYCLE
MWR
~C~~R/
W.!'&,#ff#0
;
ALLOWABLE MEMORY ACCESS
•
LVALtD OUTPUT
,. LVALtD OUTPUT
~~UOUTPUT-r--------~O~F7F----------~----~V~A~L~ID~D~A~T~A---,------------O~F~F~-------,r---~V~A~L~,D~D~A~T7A----r--O~F~~~----
MEMORY
No.2 Memory write-cycle timing waveforms.
INSTRUCT ION
_1>-_____F_E_TC_H__I_50_'______-'-____....;;,_XE_C,-,U_T_E__15_"____-'-____--'F..:E-'.TC"'H-'--'.;.50:;;.'____.....J'--____...;E...X_EC'-U_T_E--'15...;1I____-'--'F.;:E.;.;TC:;;.H;.....;I.;.50;;;.1___
r---MEMOIW READ CYCLE---+-- MEMORY READ CYCLE-+-- MEMORY READ CYCLE-+-MEMORY READ CYCLE--........
I.>---~~~gRY
MRD
MWR
n
~
n
n
nCYClE
(HIGH~
~C~pDU;Y:;
~~
ALLOWAS:'E MEMORY Ace;;
~00.
L- VALID ~ - - - - . . L
0.fW0//ff$~$4
WWM
O"'0T'PUT
~ VALIDO~TPUT
*tVALtDOUTPUT
VAlIO
No.3 Memory read-cycle timing waveforms.
I:
INSTRUCTION -1.______.:.FE"'T"'C::.:H-.::'5"'0'-'____...J.______-'E:.:;''''E'''CU"T'''E-.::'5:.:''-'__-'-______.::E"XE:::C:::Uc:.T::.E..;.:15.:.;1I__.....J________.:.FE:.;T"'C"H-.:.:15.;.01'-__..... E"X",E",CU::.T;.::E:......:I:.;S'c..1_
MRD
f.--- MEMORY READ CYCLE -+- MEMORY READ CYCLE + - MEMORY READ CYCLE ~MEMORY READ CYCLE----+-- ~~~gRY
II
n
II
II
n CYCLE
MWR (HIGH)
~C~~URTY~#ff$~~/0·
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
~MWff~~&?i
LVAlID OUTPUT
L
VAllO OUTPUT
No.4 Long-branch or long-skip-cycle timing waveforms.
~
"Don't Care" or Internal delays
92CL-29600
Fig. 14 - Machine-cycle timing waveforms (propagation delays not shown).
53
RCA CMOS LSI Products
CDP1802BC
CLOCK
TPA~~________________~r_l~___________________
TPB _________________--'r_l~_ _ _ _ _ _ _ _ _ _
__'r__L
MACHINECYCLE __L -________~C~Y~C~L~E~n______________~__________~C~Y~C~L~E~(~n~+~11~__________~___
FETCH (SOl
INSTRUCTION
EXECUTE (511
MRD
NO-N2 ________________________
N -9
------~
F
MWR
~~~~~; : • •~7/-2A%::~~~~~/,:~/j~/j~%;~~~j0~/j~/j~~~/j~~~R• • • • • • • • • • • • •
-:;-
.. L
ALLOWABLE MEMORY ACCESS
OATABUS."
VALID OUTPUT
1I~1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I~::V~A~Lgl~D~D~A~T~A~F~R~O~M~I~N~P~U!T~D~E~vEIC~E::::::~1I1II
~I .~---------MEMORY ~------~~~14.~--------MEMORY ~
__
READ CYCLE
-
__________
WRITE CYCLE
~.I
·User-generated signal
92CS-29601
No.5 Input-cycle timing weveforms.
"6
TPA ~~
____________~r__l~_______________
TPB __________________________~r_lL__________________________~r_lL_______
MACHINE
"CYCLE n
CYCLE
CYCLE (n + 11
INSTRUCTION __L-__________....:...FE::.T:..:C::.H:....::(S::OI!..-__________.l-____________..::E;:;X~E~CU::.T:..:E:.....i:(S::.;1~1________..1-_____
MRD
~
____________
~r__r~
____________
NO-N2 ______________________________--J
~r----
L-
N·1-7
ALLOWABLE MEMORY ACCESS
4
DATA BUS
4
DATA STROBE'
~
VALID DATA FROM MEMORY
VALID OUTPUT
ALLOWABLE MEMORY ACCESS
~
~
r I..._______
(MRD "TPB" NI
MEMORY
aEAD CYCLE
-<""II~·I--------- R::~~~;LE------------I"I
I
I
4User·generated signal
~
"Don't Care" or Internal delays.
92CS-29602
_
High-impedance state
No.6 Output-cycle timing waveforms.
Fig. 14 - Machine-cycle timing waveforms (propagation delays not shown). Continued.
54
1800-Series Microprocessors and Microcomputers
CDP1802BC
CLOCK
TPA~L-
______________
______________
____________
______________
______________
_______________
____________
TpB ______________
~r_l~
~r_l~
_Jr_l~
~r_l~
_Jr_1~
_Jr_l~
~
~
MACHINEl~~~~llC~Y:C~LEl:"~~~~~~~~~~C~YlCiLE~I"l+~'~I~~:;~;;~~~CiYiCL~El'in!+~21~~~~~~~~l~~E~'~l'~~ll~~
CYCLE
-
INSTRUCTION
FETCH (SO)
EXECUTE (S1)
DMA-IN' ~AW'WA\
MRO -------,
CLn 1-
OMA (82)
FETCH (SO)
~#ffA
\ ... _ _ _ _ _ _ _ _ _ _
@0'/!/ff//l////l.//dA
-I'
\... _ _ ~i
MWR
?/W//Y&l!I7!j
MEMORY
OUTPUT
t
VALID OUTPUT
VALID OUTPUT
DATABUS4~i""""""""""""~"""""""""""~~V~ALgl£D]D~AITA~F~RO~M[TIIN~P~UTL£D~EV~12CE[:~""""""""""".
I
I
MEMORY
I---- REMAEDM~;;lE
NON-MEMORY CYCLE
I
I
MEMORY
READ CYCL,E
MEMORY
WAITE CYCLE
READ, WRITE OR
-I ..
I
92C5-29603
·User·generateod signa)
No, 7 DMA-IN-cycle timing waveforms.
CLOCK
TPA~
______________~r_1~______________~r_lL-____________~r-lL--
TPB ________________
~r_lL_
______________
~r_lL_
______________
_Jr_1~
________
~¢g~NE y---------~C~Y~CL~E~"----------,-------~C~YC~L~E-I~n-+~,~I--------y-------~cY~C~L~E~I~"~+~2~1--------TI~cY~C~L~E~I~n-'~3c-1
INsTRUCnONJ-______~F~E~TC~H~IS~O~I_________L______~EX~E~C~U~T~E~I~S~II________~________~O~M~A~(S~2~1________~I~F~E~TC~H~IS~O~I__
e?dd2Z
MRD
----,~
________________~
tL- _ _ _ _ _ _ _ _ _ _ ..Ii
L -___________
~
L ___ J
MWR
MEMORY
~J1
OUTPUT
l
DATA*
STROBE
~
I
(52. TPBI
1-----
10
.
1.
.1..
READ CYCLE
j
:
1
r_1L___________
I
MEMORY
1
MEMORY
?//lZZWflZ7~t:J• •E2ZZZZ~?~Z~
VALID DATA FROM ~EMORY
VALID OUTPUT
-I..:
1
READ, WRITE OR
NON MEMORY CYCLE
I
MEMORY
I
AEAD CYCLE
-:"MEMORY
IREAD CYCLE
92CM - 29604RI
'User-generated signal
NO.8 DMA-OUT-cycle timing waveforms.
CLOCK
TPA~~
____________~r_l~_______________JrlL______________~r_1L_______________
TPB ________________-Jr-l~________________~r_lL_______________Jr_1~________________~~
~¢g~NE -r------~C~Y~C~LE~"----------~--------~C~YC~L~E~I~n+~II------~~------~C~Y~C~LE~ln~+~2~1------,-------~C~Y~CL~E~(~n-+~3~J-------P-
IN~AUCTION::::::~~FE~T~C~H~15~O~I--------~::::;::::EX:E:C=U:T:E:1S:"::::::::~::::::':NT:E:R:R:U:PT:I:S:31::::::::::~----~FE~T~C~H~(S~O~I________::
MRO -------,
'L
INTERRUPT·
(INTERNAL) IE
~~~~u~Y
_
r
J
\___ .1
MWR
---------------------------------------------------------1..._______________________________________
• •E;;~~~.§/:0~/:0~~~~~~;0';~~/;~~~~§fJ~:::I.1'i;;2/:0~;2~Z:/:2:2~2~2:222?/2/"Z2Z/,2/,2/,Z
MEMORY
I
READ CYCLE
••
• • • • • • • • • • •~~2~~~~~~~~~~~~~%~2~2~y/~~~ap
l
VALtDOUTPUT
-----<•.,I~.-___, MEMORY READ,
I
•
WRITE
OR NON-MEMORY CYCLE
VALIDOUTP~T'
1........- - NON·MEMORY CYCLE - -..~I"".I----- REMAEOMCOyRCYLE -----_..0<11I
--10
...
I
I
J
·User-generated signal
~
"Don't Care" or internal delays
_
High-impedance state
No.9 INTERRUPT-cycle timing waveforms.
Fig. 14 - Machine-cycle timing waveforms (propagation delays not shown). Continued.
92CM-29605
55
RCA CMOS LSI Products
CDP1804AC
CLOCK
lim
mn
0
SCI
SCO
111m
••
8
7
BUS 7
8
BUS'
5
9
10
aus
BUS 4
IUS
:s
BUS 2
BUS I
auso
EifluMi
02
HI
NO
Yss
"
12
13
Objective Data
..•••
37
58
CMOS a-Bit Microcomputer
With On-Chip RAM, ROM, and
Timer/Counter
~
1ID1R
liIU""m
.
~
•• IIWII
•••• "T.'
32
31
30
29
2'
27
I.
28
15
II
25
t7
2"
t8
2.
22
19
20
21
TOP VIEW
M.7
M.,
MA.
....
Performance Features:
• Instfuction time of 3.2 /.IS, -40 to +8So C
• 123/nstructions-upwards software
compatible with CDP1802, CDP1805, and CDP1806
• BCD arithmetic Instructions
• Low~power IDLE mode
• Pin compatible with CDP1802, CDP1805, and CDP1806,
except for Vee terminal
• 64K-byte memory address, capability
...3
".2
""
"AO
m
m
En
m
t2CS-'4t80
TERMINAL ASSIGNMENT
The RCA-CDP1804AC is a. functional and performance
enhancement of the CDP1802, CDP180SC, and CDP1806C
LSI CMOS 8-blt register-oriented microprocessor series
and is designed for use in a wide variety of general-pu rpose
applications.
The CDP1804AC hardware enhancements include a 2Kbyte ROM array, a 64-byte RAM array, and a B-bit presettable
down counter. The timer/counter, which generates an
Internal Interrupt request, can be programmed for use in
time-base, event-counting, and pulse-durat!on measurement applications. The timer/counter underflow output can
also be directed to the Q output terminal.
The CDP180SAC and CDP1806AC which are identical to
the CDP1804AC, except forthe on-chip memory, should be
used for COP1804AC development purposes.
The CDP1804AC software enhancements include 22 more
Instructions than the CDP1802 and 10 more Instructions
than the COP180SAC and COP1806AC. The 32 new software
• 2 K bytes of on-chip ROM
• 64 bytes of on-chip RAM
• 16 x 16 matrix of on-board registers
• On-chip crystal or RC controlled oscillator
• 8-bit timer/counter
instructions add subroutine call and return capability,
enhanced data trans.fer manipulation, timer/counter control,
improved interrupt handling, Single-instruction loop
counting, and BCD arithmetic.
Upwards software lind hardware compatibility are maintained when substit\Jting a COP1804AC for other CDP180Dseries microprocesl'ors. Pinout is identical except for the
replacement of Vee with EMS/ME.
The COP1804AC has an operating voltage range of 4 V te.
6.S V and is supplied in a 4D-lead hermetic dual-In-line
ceramic package (0 suffix), and In a 4D-lead dual-In-line
plastic package (E suffix).
r------ -
-AOORESS BUS- - - - -
- -
-I
- - -
----j r--------,
~~
,- MA~MA7I
CONTROL
CDPI851
PIO
1
CDPI804AC
8- BIT CPU
WITH ROM,
MWR
~f~E:/N 0
TPA
COUNTER
J
---
---~TPA
I
I
1
MRD
I
1-
:
1
I
,
1
MWR
1
RAM
cs
I
1
I
I
I
L.!IUSO-BUS7 I
-II
-II:.:..:...J
~_________ ....J I
_________~
--=-...:::.;~:.:.::.==__
1
I
CEOI----~
I
1_
~---""'CS
--+cs
I BUS\l-BUS7
'--_ _ _ _ _ _
I
r----1
ROM
1
1
~,..,-
.J~
rM~MA71
f------..I
---~MRD
I
~
::
__________________ ...J 92CM-34981
'--OPTIONAL EXPANSION MEMORY--..i
Fig. 1 - Typical CDP1lKUAC m/croprocessQr system.
56
1800-Series Microprocessors and Microcomputers
CDP1804AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (Voo):
(Voltage referenced to V•• Terminal) ............................. '" ......................•.......•...•...•••••.•..••• -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS .....................................................•.••...•...•.. " ••.•• -0.5 to VOD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ........................................ '" .................•.................•..•. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ........................................................•.....•...•.••...•..... 500 mW
For T. = +60 +85·C (PACKAGE TYPE E) ................................................... Derate Linearly at 12 mW/·O to 200 mW
ForT. = -55 to +100·C (PACKAGE TYPE D) .............................................................................. 500 mW
For T. = +100 to +125·C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/·O to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForT. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 ............................................................................................... -55 to +125·0
PACKAGE TYPE E .................................................................................................-40 to +85·0
STORAGE TEMPERATURE RANGE (T••o) .... · ....................................................................... -65 to +150·0
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... +285·0
RECOMMENDED OPERATING CONDITIONS atTA = -40 to +85·C
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
CONDITION
LIMITS
CDP1804ACD
CDP1804ACE
CHARACTERISTIC
-
Voo
(V)
MIN.
-
4
6.5
Vss
Voo
Minimum Instruction Time' (fcL=5 MHz)
5
3.2
-
Maximum DMA Transfer Rate
5
-
0.625
5
DC
5
5
DC
2
DC Operating Voltage Range
Input Voltage Range
Maximum Clock Input Frequency,
load Capacitance (Cl) = 50 pF
MAX.
V
~
Mbytes/s
MHz
Maximum External Counter/Timer
Clock Input Frequency to --EF1, EF2
UNITS
tCLx
'Equals 2 machine cycles - one.Fetch and one Execute operation for all instructions except Long Branch,. Long Skip,
NOP, and "68" family instructions. which are more than two cycles.
57
RCA CMOS LSI Products
CDP1804AC
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85 0 C, Voo ± 5%, Except as noted
LIMITS
CONDITIONS
CDP1804ACD,
CDP1804ACE
CHARACTERISTIC
Quiescent Device Current
100
Output Low Drive (Sink) Current
IOL
(Exeeot XTALI
XTAL Output
Output High Drive (Source) Current
IOL
IOH
(Exceot XTALI
XTAL
UNITS
Vo
Y,N
VDD
(V)
(V)
(V)
Min.
Typ."
Max.
-
0,5
5
-
50
200
0.4
0,5
5
1.6
4
0.4
5
5
0.2
0.4
4.6
0,5
5
-1.6
-4
-
IOH
4.6
0
5
-0.1
-0.2
-
Output Voltage Low-Level
VOL
-
0,5
5
-
0
0.1
Output Voltage High Level
VO H
-
0,5
5
4.9
5
-
Input Low Voltage (BUS 0 - BUS 7, EMS/MEl
V,L
0.5,4.5
-
5
-
-
1.5
Input High Voltage (BUS 0 - BUS 7. !OMS/ME)
Schmitt Trigger Input Voltage
V,H
0.5,4.5
-
5
3.5
-
-
pA
mA
V
(Except BUS 0 - BUS 7, EMS/ME)
Positive Trigger Threshold
Vp
Negative Trigger Threshold
VN
Hysteresis
VH
Input Leakage Current
3-State Output Leakage Current
Input Capacitance
Output Capacitance
0.5,4.5
',N
lOUT
C'N
COUT
Total Power Dissipation (f=5 MHz)
Idle "00" at M(OOOO) CL = 50 of
Minimum Data Retention Voltage
Data Retention Current
-
5
2.2
2.9
3.6
0.9
1.9
2.8
0.3
0.9
1.6
-
0.5
5
-
±0.1
±5
0,5
0,5
5
-
±0.2
±5
pA
-
-
-
-
5
7.5
-
-
-
10
15
-
-
5
-
1.5
3
mW
V
pA
VOR
Voo = VOR
-
2
2.4
lOR
VOO = 2.4
-
25
100
pF
"Typical values are for T. = 25°C and nominal Voo.
OPERATING AND HANDLING CONSIDERATIONS
1.
2.
58
Handling
All inputs and outputs of RCA CMOS devices have a
network for elecltrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525 "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
OperatIng
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power s~pply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absol ute maximum
rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Vee nor less than
Vss.lnput currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Vee or Vss, whichever is appropriate.
Output Short Clrculls
Shorting of outputs to Voo, Vce, or Vss may damage
CMOS devices by exceeding the maximum device
dissipation.
1800-Series Microprocessors and Microcomputers
CDP1804AC
CONTROL
I
CONTROL AND
TIMING LOGIC
BUSO
I
BUS I
BUS
2
BUS 3
NO} 1/0
NI
COMMANDS
BUS 4
N2
BUS 5
BUS 6
BUS 7
92CM-34982
Fig. 2 - Block diagram for CDP1804AC.
Enhanced 1804AC Operation
ROM/RAM
The 2K-byte ROM is mask-programmable and mask-selectable in any 2K block of the available 64K address space in
the RUN (ROM/RAM) mode. (The procedure is detailed in
the Mask-Programming section at the end of the data
sheet.)
The 64-byte RAM is mask-selectable in any 64-byte block of
memory in the RUN (ROM/RAM) mode. It may also be
externally selected via the ME input in the RUN (RAM only)
mode.
The EMS/ME pin serves a dual function. In the RUN
(ROM/RAM) mode, EMS acts as an active low output to
indicate when the internal ROM or RAM is not selected. This
provides a convenient chip-select signal for any optional
expansion memory devices and a stable-address latch
signal. In the RUN (RAM only) mode, ME acts as an active
low input and is used to select the interrial RAM, which is
not mask-selected in this mode. Decoding is performed
externally and the RAM may reside in any 64-byte blOCk.
Timing
Timing for the CDP1804AC is the same as the CDP1802
microprocessor series, with the following exceptions:
• 4.5 clock cycles are provided for memory access
instead of 5.
• a changes 1/2 clock cycle earlier during the SEa and
REO instructions.
• Flag lines (EFi -m) are sampled at the end of the SO
cycle instead of at the beginning of the S1 cycle.
• Pause can only occur on the low-to-high transition of
either TPA or TPB, instead of any negative clock
transition.
Special Features
Schmitt triggers are provided on all control inputs, except
EMS/Mr:, for maximum immunity from noise and slow
signal transitions. A Schmitt trigger in the oscillator section
allows operation with an RC or crystal.
The CDP1802 series LOAD mode is not retained. This mode
(WAlT, CLEAR=O) is the RUN (ROMlRAM) mode on the
CDP1804AC.
A low power mode is provided, which is initiated via the
IDLE instruction. In this. mode all external signals, except
the oscillator, are stopped on the low-to-high transition of
TPB. All outputs remain in their previous states, MRD is set
to a logiC "1", and the data bus floats. The IDLE mode is
exited by a DMA or INT condition. The INT includes both
external interrupts and Interrupts generated by the timer
/counter. The only restrictions are that the Timer mode,
which uses the TPA + 32 clock source, and the underflow
condition at the Pulse Width Mellsurement modes are not
available to exit the IDLE mode.
59
RCA CMOS LSI Products
CDP1804AC
TIMING WAVEFORMS FOR POSSIBLE OPERATING MODES
l'NTERNAL RAM READ CYCLE ---t-'NTERNAL RAM WRITE CYCLE--j
00
CLOCK
~
~ ~
00
~
ro
~ ~
ro
~ ~
00
~
ro
I
ro
TPB:;~~~~::~~~~~~~~~::::~~:~~~.~
I
I
I
I
A~:EOS~Y
HIGH BYTE
I.OW BYTE
HIGH BYTE
LOW BYTE
MRD----,L____________~~
MWR------------------~,--------------,~
I
* ~NE ----------------'Lur------------,L--j
VALID OATA FROM
MEMORY~
"NOTE FOR RUN (RAM ONLY) MODE:
in HAS A MINIMUM SETUP AND HOLD' TIME WITH RESPECT TO THE
BEGINNING OF CLOCK 70 FOR A MEMORY READ OPERATION. RAM DATA
WILL APPEAR ON THE DATA BUS DURING TifE TIME 111! IS ACTIVE. THE TIME
SHOWN CAN BE LONGER, IF FOR INSTANCE, A DMA OUT OPERATION IS
PERFORMED ON INTERNAL RAM DATA. TO ALLOW DATA ENOUGH TIME TO
BE LATCHED INTO AN EXTERNAL DEVICE, THE INTERNAL RAM IS
AUTOMATICALLY DESELECTED AT THE END OF CLOCK 71,INDEPENDENT
OF ME.
NOTE FOR RUN (ROM/RAM) MODE:
INTERNAL MEMORY DATA WILL APPEAR ON THE DATA BUS AFTER CLOCK
PULSE 31.
92C5-349B3
Fig. 3 - Internal memory operation timing waveforms for CDP1804A C.
t
EXTERNAL MEMORY READ CYCLE +EXTERNAL MEMORY WRITE CYCLE
~ w w ~ w w ro ~ ~ w w ~ w w ro
00
1
CLOCK
01
TPA
TPB
~~~O:sYs
II
21
31
41
611
51
71
01
II
21
31
41
51
61
71
~'--__________~I>__----'nL----------------
n
~
:;;,;;;;;~::::;;,~;:~I-=~;;~;;~::~;;;;;:--~=
I HIGR BYTE I
LOW BYTE
I
I HIGH BYTE I
LOW BYTE
I
MRD~'--____________+I---'
I
MWR-----------------71--------------,~
---Ir
*EMS
L--_ _
OUT
DATA BUS -"~ca__=O::.:.A'::A...:L::.:.AT:.:C::HE=O...:IN:...C:...P.:..U__~_l==L___
VA_=L_='O_=O_AT_A_F_RO::M_C_PU
____...<.<;
"FOR RUN (ROM/RAM) MODE ONLY.
_
NOTE: FOR THE RUN (RAM ONLY) MODE ME MUST BE HIGH DURING
EXTERNAL MEMORY ACCESSES.
92CS- 34984
Fig. 4 -External memory operation timing waveforms for CDP1804AC.
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bus):
a-bit bidirectional OAT A BUS lines. These linesare used for
transferring data between the memory, the microprocessor,
and I/O devices.
NO to N2 (1/0) Lines:
Activated by an I/O instruction to Signal the I/O control
logic of a data transfer between memory and I/O interface.
These lines can be used to issue command codes or device
60
selection codes to the I/O devices. The N bits are low at all
times except when an I/O instruction is t,eing executed.
During this time their state is the same as the corresponding
bits in the N register. The direction of data flow is defined in
the I/O instruction by bit N3 (intetnally) and is indicated by
the level of the QJID signal:
MAD = VDO:
Data from I/O to CPU and Memory
MAD = Vss:
Data from Memory to I/O
1800-Serles Microprocessors and Microcomputers
CDP1804AC
SIGNAL DESCRIPTIONS (Cont'd)
m
to EF4(4 Flag.):
mor(Read Level):
These inputs enable the 110 controllers to transfer status
information to the processor. The levels can be tested by
the conditional branch instructions. They can be used in
conjunction with the INTERRUPT request line to establish
interrupt priorities. The flag(s) are sa.!!!2led at the end of
every SO cycle. One additional use for m and EF2 is event
counting and pulse-width measurement in conjunction
with the Timer/Counter.
INTERRUPT, DMA-IN, D.=cM""'A~-""'O""'U=T (31/0 Reque.t.)
These inputs are sampled by the CDP1804AC during TPB.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
set to 1; interrupt enable is reset to 0 (inhibit); and
instruction execution is resumed. The Interrupt action
requires one machine cycle (S3).
DMA Action: Finish executing current instruction; R(O)
points to memory area for data transfer; data is loaded into
or read out of memory; and increment R(O).
Note: In the event of concurrent DMA and INTERRUPT
requests. DMA-IN has priority followed by DMA-oUT and
then INTERRUPT.
SCO, SC1, (2 State Code Line.):
These outputs indicate that the CPU is: 1) fetching an"
instruction, or 2) executing an instruction, or 3) processing'
a DMA request, or 4) acknowledging an interrupt request.
The levels of state code are tabulated below. All states are
valid ~t TPA.
State Type
SO (Fetch)
Stete Code Line.
SC1
L
Sl (Execute)
S2 (DMA)
L
H
S3 (I nterrupt)
H
seo
L
H
L
H
H =VDD, L =Vss.
TPA, TPB (2 Timing Pulse.):
Positive pulses that occur once in each machine cycle (TPB
follows TPA). They are used by 1/0 controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the
high-order byte of the 16-bit memory address.
MAO to MA7 (8 Memory Addre•• Line.):
In each cycle, the higher-order byte of a .16-bit memory
address appears on the memory address lines MAO-7 first.
Those bits required by the memory system can be strobed
into external address latches by timing pulse TPA. The
low-order byte of the 16-bit address appears on the address
lines 1/2 clock after the termination of TPA.
iiWii (Write Pulse):
A negative pulse appearing in a memory-write cycle, after
the address lines have l\tabilized.
A low level on lmlj indicates a memory read cycle. It can be
used to control three-stete outputs from the addressed
memory and to indicate the direction of data transfer during
an 1/0 instruction.
Q:
Single bit output from the CPU which can be set or reset,
between the trailing edge of TPA and the leading edge of
TPB, under program control. The Enable Toggle Q command connects the Q-line flip-flop to the output of the
counter, such that each time the counter decrements from
01 to its next value, the Q line changes state. This command
Is cleared by a LOAD COUNTER (LDC) Instruction, a CPU
reset, or a BRANCH COUNTER INTERRUPT (BCI) instruction with the counter interrupt flip-flop set.
CLOCK:
Input for externally generated single-phase clock. The
maximum clock frequency isS MHz atVDD = SV. The clock is
counted down internally to 8 clock pulses per machine
cycle,
XTAL:
Connection to be used with clock Input terminal, for an
external crystal, If the on-Chip oscillator is utilized.
WAiT, CLEAR (2 Control Line.):
provide four control modes as listed in the following truth
table:
CLEAR
WAIT
L
L
H
L
H
H
L
H
MODE
RUN (ROM/RAM)
RESET
PAUSE
RUN (RAM ONLY)
iii (Memory Enabla) RUN (RAM ONLY) Mode
This active low Signal line is used to select or deselect the
internal RAM. It must be active prior to clock 70 for an
internal RAM aCCeSS to take place. Internal RAM data will
appear on the data bus during the time that ~ Is /\Ictlve
(after clock 31). Thus, If this data is to be latched Into an
external device (i.e., during an OUTPUT instruction arOMA
OUT cycle),'llE should be wide enough to provide finougt:l
time for valid data to be latched.
.
In the RUN (RAM ONLY) mode the Internal RAM i~ not
internally mask-decoded. Decoding of the starting ali(:lress
Is performed externally, and may reside In any 64~byte
block of memory.
EMs (External Memory Select) RUN (ROM/RAM) ~ode
This signal line Is used for external memory expansion. It Is
low when external memory Is being addressed and high at
all other times. It is initiated 1.S clock periods after TPA Cat
which time all addresses are.table) and terminates at the
end of the cycle. Use of EMS for memory selection ahows
3.5 clock cycles for data access.
VDD, VIS, (Power Level.):
Vss Is the most negative supply voltage terminal and Is
normally connected to ground. VDD Is the positive supply
voltage terminal. All outputs swing from VIS to VDD. The
recommended input voltage swing Is from VIS to VDD.
61
•
RCA CMOS LSI Products
CDP1804AC
ARCHITECTURE
Fig. 2 shows a block diagram of the CoP1804AC. The
principal feature of this system is a register array (R)
consisting ofsixteen 16-blt scratch pad registers. Individual
registers In the array (R) are designated (selected) by a 4-bit
binary code from one ofthe 4-bit registers labeled N, P, and
X. The contents of any register can be directed to anyone of
the following three paths:
1. the external memory (multiplexed, higher-order byte
first on to 8 memory address lines)
2. the 0 register (either ofthe two bytes can be gated to D)
3. the incremenVdecrement circuit where it is increalled
or decreased by one and stored back in the selected
16-bit register.
The three paths, depending on the nature of the instruction,
may operate Independently or in various combinations in
the same machine cycle.
Most instructions consist of two 8-clock-pulse machine
cycles. The first cycle is the fetch cycle, and the second
-and more if necessary - are execute cycles. During the
fetch cycle the four bits in the P designator select one of the
16 registers R(P) as the current program counter. The
selected register R(P) contains the address of the memory
location from which the instruction is to be fetched. When
the instruction is read out from the memory, the higherorder 4 bits of the instruction byte are loaded into the I
register and the lower-order 4 bits into the N register. The
content of the program counter is automatically incremented
by one so that R(P) is now "pointing" to the next byte in the
memory.
, The X deSignator selects one of the 16 registers R(X) to
"point" to the memory for an operand (or data) in certain
ALU or I/O operations.
The N deSignator can perform the following five functions
depending on the type of instruction fetched:
1. designate one of the 16 registers in R to be acted
upon during register operations
2. indicate to the I/O devices a command code or
device-selection code for peripherals
3. indicate the specific operation to be executed during
the ALU instructions, types of tests to be performed
durin!;! the Branch instructions, or the specific operation r$quired in a class of miscellaneous instructions
4. indicate the value to be loaded into P to designate a
new r~gister to be used as the program counter R(P)
5. Indicate the value to be loaded into X to deSignate a
new register to be used as data pOinter R(X).
The registers in R can be assigned by a programmer in three
different ways as prognam counters, as data pointers, or as
scratchpad locations (data registers) to hold two bytes of
data.
Progrlm Counter.
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other
registers In R can be used as subroutine program counters.
By a single instruction the contents of the P register can be
changed to effect a "call" to, subroutine. When interrupts
are being serviced, register R(l) is used as the program
62
counter for the user's interrupt servicing routine. After
reset, and during a oMA operation, R(O) Is used as the
program counter. At all other times the register designated
as p~ogram counter is at the discretion of the user.
Dltl Pointer.
The registers in R may be used as data pOinters to Indicate a
location in memory. The register designated by X (i.e., R(X»
pOints to memory for the following instructions (see Table
I):
1. ALU operations
2. output instructions
3. input instructions
4. register - - memory transfer
5. interrupt and subroutine handling.
The register deSignated by N (i.e., R(N» pOints to memory
for the "load 0 from memory" instructions ON and 4N and
tlla "Store 0" instruction 5N. The register designated by P
(i.e., the program counter) is used as the data pOinter for
ALU instructions F8-Fo, FF, 7C, 70, 7F, and the RLol
instruction 68CN. During these instruction executions, the
operation is referred to as "data immediate".
Another important use of R as a data pointer supports the
built-in oirect-Memory-Access (oMA) function. When a
oMA-ln or oMA-Out request is received, one machine
cycle is "stolen". This operation occurs at the end of the
execute machine cycle in the current instruction. Register
R(O) is always used as the data pOinter during the oMA
operation. The data is read from (oMA-Out) or written into
(oMA-ln) the memory .location pointed to by the R(P)
register. At the end of the transfer, R(O) is incremented by
one so that the processor is ready to act upon the next oMA
byte transfer request. This feature in the CoPl804AC
architecture saves a substantial amount of logic when fast
exchanges of blocks of data are required, such as with
magnetic discs or during CRT-display-refresh cycles.
Dati Regl.ter.
When registers in R are used to store bytes of data,
instructions are provided which allow 0 to receive from or
write into either the higher-order- or lower-order-byte
portions ofthe register deSignated by N. By this meChanism
(together with loading by data immediate) program pointer
and data pOinter designations are initialized. Alsl', this
technique allows scratch pad registers in R to be used to
hold general data. By employing increment or decrement
instructions, such registers may be used as loop c94nters.
The new RLol, RLXA, RSXo, and RNX instructions also
allow loading, storing, and exchanging the full 16-bit
contents of the R registers. The new oBNZ instruction
allows decrementing and branching-on-not-zeroof any 16bit R register without affecting the 0 register.
The Q Flip-Flop
An internal flip-flop, a, can be set or reset by instruction
and can be sensed by conditional branch instructions. It
can also be driven by the output of the timer/counter. The
output of a is also available as a microprocessor output.
1800-Series Microprocessors and Microcomputers
CDP1804AC
ARCHITECTURE (Cont'd)
Regllter Summary
0
8 Bits
Data Register (Accumulator)
OF
1 Bit
Data Flag (AlU Carry)
8
8 Bits
Auxiliary Holding Register
R
16 Bits
1 of 16 Scratch pad Registers
P
4 Bits
Designates which Register is
Program Counter
X
4 Bits
Designates which Register is
Data Pointer
N
4 Bits
Holds low-Order Instr. Digit
I
4 Bits
Holds High-Order Instr. bigit
T
8 Bits
Holds old X, P after Interrupt
(X is high nibble)
Q
1 Bit
Output Flip-Flop
CH
8 Bits
Holds Counter Jam Value
MIE
CIE
1 Bit
1 Bit
Master Interrupt Enable
Counter Interrupt Enable
XIE
1 Bit
External Interrupt Enable
Cil
1 Bit
Counter Interrupt latch
Interrupt Servicing
Register R(1) is always used as the program counter
whenever interrupt servicing is initialized. When an interrupt
request occurs and the interrupt is allowed by the program
(again, nothing takes place untif the completion of the
current instruction), the contents of the X and P registers
are stored in the temporary register T, and X and P are set to
new values; hex digit 2 in X and hex digit 1 in P. Master
Interrupt Enable is automatically deactivated to inhibit
further interrupts. The user's interrupt routine is now in
control; the contents of T may be saved by means of a single
SAV instruction (78) in the memory location pointed to by
R(X) or the contents of T, 0, and OF may be saved using a
single DSAV instruction (6876). At the conclusion of the
interrupt, the user's routine may restore the pre-interrupted
value of X and P with either a RET instruction (70) which
permits further interrupts, or a DIS instruction (71), which
disables further interrupts.
Interrupt Oenerallon and Arbitration
(See Fig. 5)
Interrupt requests can be generated from the following
sources:
1. Externally through the Interrupt Input (Requelt not
latched)
2. Internally due to timer/counter response (Request Is
latched)
a. On the transition from count (01)1. to Its next value
(counter underflow)
b. On the f
transition of min pulse measure. ment mode 1
_
c. On the f
transition of EF2 In pulse measurement mode 2
For an interrupt to be serviced by the CPU, the appropriate
Interrupt Enable flip-flops lTiust be set. Thus, the External
I nterrupt Enable flip-flop must be set to service an external
interrupt request, and the Counter Interrupt Enable flip-flop
must be set to service an internal timer/counter Interrupt
request. In addition, the Master Interrupt Enable flip-flop
(as used in the CDP1802) must be set to service either type
of request. All 3 flip-flops are initially enabled with the
application of a hardware reset, and, can be selectively
enabled or disabled with software: CIE, CID Instructions for
the CIE flip-flop; XIE, XID instructions for the XIE flip-flop;
RET, 01$ instructions for the MIE flip-flop.
Short branch instructions on Counter Interrupt (BCI) and
External Interrupt (BXI) can be placed in the user's Interrupt
service routine to provide a means of Identifying and
prioritizing the interrupt source. Note, however, that since
the External Interrupt request is not latched, it must remain
active untif the short branch is executed If this priority
arbitration scheme is used·.
I nterrupt requests can also be polled if automatic interrupt
service is not desired (MIE=O). With the Counter Interrupt
and External Interrupt short branch instructions, the branch
will be taken if an interrupt request is pending, regardless of
the state of any of the 3 Interrupt Enable flip-flops. The
latched counter interrupt request signal will be reset when
the branch is taken, when the CPU is reset, or with Ii tOC
instruction with the Counter stopped;
RET
RESET
S MASTER
MIE
QI-------.:::==------------,
INTERRUPT
ENABLE
FF
53
COUNTER
UNDERFLOW
' - - - - - - ' PULSE MODE EFi J
PULSE MODE EF2J.
BCI
RESET
LDC' COUNTER
CIE
STOPPED
S COUNTER
INTERRUPT
RESET
ENABLE
CIE
CID----j
FF
QI---------'=----'------L~
DIS
EXTERNAL
XIE
RESET
TNT
S EXTERNAL Q~-------------L~
EIE
XID----IR
INTERRUPT
EN~~LE
Fig. 5 - Interrupt logic-control diagram for CDP1804AC.
63
RCA CMOS LSI Products
CDP1804AC
ARCHITECTURE
TImer/Counter and Control. (... Fig. 8)
This logic consists of a presellable 8-bit down-counter
(Modulo N type), and a conditional dlvlde-by-32 prescaler.
After counting down to (01)11 the counter returns to its
Initial value althe next count and sets the Counter Interrupt
Latch. It will continue decrementing on subsequent counts.
If the counter Is preset to (OOhl a full 256 counts will occur.
During a Load Counter instruction (LDC) If the counter was
stopped with a STPC Instruction, the counter and its
holding register (CH) are loaded with the value In the 0
register and any previous counter Interrupt Is cleared. If the
LDC is executed when the counter Is running, the contents
of the 0 register are loaded into the holding register (CH)
only and any previous counter interrupt Is not cleared. After
counting down to (01 )11 the next count will load the new
Initial value Into the counter, set the Counter Interrupt
Latch, and operation will continue.
The timer/counter has the following five programmable
modes:
1. Event Counter 1: Input to counter is connected to the
terminal. The high-to-Iow transition decrements
the counter.
2. Event Counter 2: Input to counter is connected to the
En terminal. The high-to-Iow transition decrements
the counter.
3. Timer: Input to counter is from the divide-by-32 prascaler clocked by TPA. The prescaler is decremented
on the low-to-high transition of TPA. The dlvide-by-32
prescaler is reset when the counter is in a mode other
than the Timermode or stopped by a STPC.
4. Pulse Duration Measurement 1: Input to counter
connected to TPA. Each low-to-hlgh transition of TPA
m
(Co~rd)
decrements the counter If the input signal at EF'I
terminal (gate Input) Is low: On the transition ofm to
the positive state, the count Is stopped, the mode Is
cleared, and the Interrupt request latched. If the counter
underflows while the Input Is low, Interrupt will also be
set, but counting will continue.
5. Pulse Duration Measurement 2: Operation Is Identical
to Pulse Duration Measurement 1, except
Is used
as the gate Input.
m
The modes can be changed without affecting the stored
count.
and mtermlnals liS inputs do
Those modes wh!Ch use
not exclude testl~g these flags for branch instructions.
The Stop Counter (STPC) Instruction clears the cOllnter
mode and stops counting. The STPC instruction ShQuld be
executed prior to a GEC instruction, if ~he counter is In the
.
Event Counter Mode 1 or 2.
m
I n addition to the five programmable modes, the Decrement
eounter instruction (DTC) enables the user to count In
software. In order to avoid conflict with counting done In
the other modes, the instruction should be used only after
the mode has been cleared by a Stop Counter instruction.
The Enable Toggle a Instruction (ETa) connects the a-line
flip-flop to the output of the counter, such that each time the
counter decrements from 01 to its next value, the a output
Changes state. This action is independent of the counter
mode and the Interrupt Enable flip-flops. The Enable
Toggle a condition is cleared by an LDC with the
timer/counter stopped; system Reset, or a BCI with CI=1.
TO INTERRUPT LATCH
INH
COUNTER
OUT I-~UN;.;;D..
ER.;.;.F.;;.LO;:.;W;.............,~
Q OUTPUT
C
D
READ
92CM-547H
Fig. 6 - Timer/Counter diagram for CDP1804AC.
64
"U
1800-Serles Microprocessors and Microcomputers
CDP1804AC
ARCHITECTURE (Cont'd)
On-Board Clock ( ••• Fig. 7 and 8)
Clock circuits may use either an external crystal or an RC
network.
The crystal is connected between terminals 1 and 39
(CLOCK andXTAt) in parallel with a resistance (1 megohm
typ.).
Frequency trimming capacitors may be required at terminals
1 and 39. For additional information on crystal oscillators,
see ICAN-6565. Because of the Schmitt Trigger input, an
RC oscillator can be used as shown in Fig. 7. The frequency
is approximately 1/RC (see Fig. 8).
R
RESET
. Registers I, N, Q,counter prescaler, and Counter Interrupt
Latch are reset. XIE and CIE are set and O's (Vss) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU is placed in S1. The state of the
timer/counter is unaffected by the RESET operation.
The first machine cycle after termination of reset is an
initialization cycle which requires 9 clock pulses. During
this cycle the CPU remains In S1, X, P- T, and then registers
X, P, R(O) are reset, and MIE is set. Interrupt and DMA
servicing suppressed during the initialization cycle. The
next cycle isan SO oran S2 but never an S1 orS3. The use of
a 71 instruction followed by 00 at memory locations 0000
and 0001, may be used to reset MIE, so as to preclude
interrupts until ready for them. Power-up reset/run (ROM
/RAM) can be realized by connecting an RC network to
WAIT (See Fig. 9).
I
Voo
1
Cx
Fig. 7 - RC network for oscillator.
CDPI804AC
The RC time constant
should be greater
than the rsciilator
start·up time
(typically 20 mo).
RX
92CS-34979
Fig. 9 - Reset/Run (ROM/RAM) diagram.
PAUSE
Stops the internal CPU timing generator, freezing the state
of the processor. Pause can occur at two points in a
machine cycle, on the low-to-high transition of either TPA
orTPB.
The oscillator continues to run but sUbsequent clock
transitions are ignored. TPA and TPB remain at their
previous state (see Fig. 10).
2
468
10
2
468
100
468
IK
FREQUENCY
2 468
10K
2
468
2 .. 6
lOOK
(Hz)
92CS-3417Z
1M
If Pause is entered while in the event counter mode, the
appropriate Flag transitions will continue to decrement the
counter.
Fig. 8 - Nominal component values as a function
of frequency for the RC oscillator.
TPA PAUSE TIMING
CONTROL MODES
CLEAR
L
L
H
H
ENTER
PAUSE
WAIT
L
H
L
H
MODE
RUN (ROM/RAM)
RESET
PAUSE
RUN (RAM ONL V)
CLOCK
•
RESUME
RUN
•
TPA
The function of the modes are defined as follows:
65
RCA CMOS LSI Products
CDP1804AC
ARCHITECTURE (Conl'd)
CONTROL MODES (Confd)
TPB PAUSE TIMING
RUN
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the next
high-to-Iow clock transition, while if paused at TPB, it will
resume on the next low-ta-high clock transition(see Fig. 9).
When initiated from the Reset operation, the first machine
cycle following Reset Is always the initialization cycle. The
initialization cycle is then foflowed by Ii OMA (52) cycle or
fetch (SO) from location 0000 in memory.
ENTER'
PAUSE
!
CLOCK
TPB
I--tsu
SCHMITT TRIGGER INPUTS
92CM-31944
NOTE:
PAUSE (IN CLOCK WAVEFORM) WHILE REPRESENTED HERE AS ONE CLOCK
CYCLE IN DURATION. COULD BE INFINITELY LONG.
Fig. 10 - Pause mode timing waveforms.
All Inputs except BUS O-BUS 7 and ME contain a Schmitt
Trigger circuit, which is especially useful on the ~
input as a power-up RESET (see Fig. 9) and the CLOCK
input (see Fig. 7).
STATE TRANSITIONS
The COP1804AC state transitions are shown in Fig. 11.
Each machine cyole requires the same period of time, 8
PRIORITY:
clock pulses, except the initialization cycle (INIT) which
requires 9 clock pulses.
~~~~~ so, 51
~"'OUT
92CS-3"778
Fig. 11 - State transition diagram.
66
1800-Series Microprocessors and Microcomputers
CDP1804AC
INSTRUCTION SET
The CDP1804AC instruction summary is given in Table I.
Hexadecimal notation is used to refer to the 4-bit binary
codes.
In all registers bits are numbered from the least significant
bit (LSB)to the most significant bit (MSB) starting with O.
R(W): Register designated by W, where
W=N or X, or P
R(W).O: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
Operation Notation
M (R(N»-D; R(N) + 1-R(N)
This notation means: The memory byte pointed to by R(N)
is loaded into 0, and R(N) is incremented by 1.
TABLE I-INSTRUCTION SUMMARY (For Note., .ee al.o page 17)
INSTRUCTION
MEMORY REFERENCE
LOAD IMMEDIATE
REGISTER LOAD IMMEDIATE
LOAD VIA N
LOAD ADVANCE
LOAD VIAX
LOAD VIA X AND ADVANCE
REGISTER LOAD VIA X AND
ADVANCE
STORE VIA N
STORE VIA X AND DECREMENT
REGISTER STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
DECREMENT REG N
DECREMENT REG N AND LONG
BRANCH IF NOT EQUALO
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
5
LDI
RLDI
F8
68CN-
2
2
2
2
5
LON
LOA
LOX
LDXA
RLXA
ON
4N
FO
72
686N-
2
2
5
STR
STXD
RSXD
5N
73
68AN-
2
2
5
INC
DEC
DBNZ
1N
2N
682N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
REGISTER N TO REGISTER X COpy
LOGIC OPERATIONS (Note 5)
OR
OR IMMEDIATE
2
2
2
2
2
4
IRX
GLO
PLO
GHI
PHI
RNX
60
8N
AN
9N
BN
68BN-
2
2
OR
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
2
2
XOR
XRI
F3
FB
AND
AND IMMEDIATE
2
2
AND
ANI
F2
FA
SHIFT RIGHT
2
SHR
F6
SHIFT RIGHT WITH CARRY
RING SHIFT RIGHT
2
2
SHRC
RSHR
SHIFT LEFT
2
SHL
I
76·
OPERATION
M(R(P»-D; R(P)+1-R(P)
M(R(P»-R(N).1; M(R(P»+1R(N).O; R(P)+2-R(P)
M(R(N»-D; FOR N NOT 0
M(R(N»-D; R(N)+1-R(N)
M(R(X»-D
M(R(X»-D; R(X)+1-R(X)
M(R(X»-R(N).1; M(R(X)+1)R(N).O; R(X»+2-R(X)
D-M(RN»
D-M(R(X»; R(X)-1-R(X)
R(N).O-M(R(X»; R(N).1M(R(X)-1I: R(XI-2-R(XI
I
R(N)+1-R(N)
R(N)-1-R(N)
R(N)-1-R(N); IF R(N) NOT 0,
M(R(P» -R(P).1, M(R(P)+1)R(P).O, ELSE R(P)+2-R(P)
R(X)+1-R(X)
R(N).O-D
D-R(N).O
R(N).1-D
D-R(N).1
R(N}-R(X}
M(R(X» OR D-D
M(R(P» OR D-D;
R(P)+1-R(P)
M(RCX» XOR D-D
M(R(P» XOR D-D;
R(P)+1-R(P)
M(R(X» AND D-D
M(R(P» AND D-D;
R(P)+1-R(P)
SHIFT 0 RIGHT, LSB(D)-DF,
O-MSB(D)
SHIFT 0 RIGHT, LSB(D)-DF,
DF-MSB(D)
FE
SHIFT 0 LEFT, MSB(D)-DF,
O-LSB(D)
-Previous contents of T register are destroyed during instruction execution .
• This instruction is aSSOCiated with more than one mnemonic. Each mnemonic is individually listed.
67
RCA CMOS LSI Products
CDP1804AC
Table I - INSTRUCTION SUMMARY (Conl'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
2
2
SHLC
RSHL
ARITHMETIC OPERATIONS (Note 5)
ADD
DECIMAL ADD
2
4
ADD IMMEDIATE
DECIMAL ADD IMMEDIATE
INSTRUCTION
LOGIC OPERATIONS (Note 5) (Cont'd)
SHIFT LEFT WITH CARRY
RING SHIFT LEFT
OP
CODE
OPERATION
7E4
SHIFT 0 LEFT, MSB(D}-DF,
DF-LSB(O}
ADD
DADO
F4
68F4
2
4
AOI
OAOI
FC
68FC
ADD WITH CARRY
DECIMAL ADD WITH CARRY
2
4
ADC
DADC
74
6874
ADD WITH CARRY, IMMEDIATE
2
ADCI
7C
DECIMAL ADD WITH CARRY,
IMMEDIATE
4
DACI
687C
SUBTRACT D
SUBTRACT D IMMEDIATE
2
2
SD
SDI
F5
FD
SUBTRACT D WITH BORROW
SUBTRACT D WITH
BORROW, IMMEDIATE
SUBTRACT MEMORY
DECIMAL SUBTRACT MEMORY
2
2
SOB
SOBI
7D
2
4
SM
DSM
F7
68F7
SUBTRACT MEMORY IMMEDIATE
2
SMI
FF
DECIMAL SUBTRACT MEMORY,
IMMEDIATE
4
DSMI
68FF
SUBTRACT MEMORY WITH BORROW
DECIMAL SUBTRACT MEMORY
WITH BORROW
SUBTRACT MEMORY WITH
BORROW, IMMEDIATE
DECIMAL SUBTRACT MEMORY
WITH BORROW,IMMEDIATE
2
4
5MB
OSMB
77
6877
2
5MBI
7F
4
DSBI
687F
M(R(X»+O-Df, 0
M(R(X»+O-OF, 0
DECIMAL ADJUST-OF, 0
M(R(P»+O-OF, 0; R(P}+1-R(P}
M(R(P»+O-OF,O
R(P}+1-R(P}
DECIMAL ADJUST-OF, 0
M(R(X»+O+OF-'--OF, 0
M(R(X»+D+DF-OF,O
DECIMAL ADJUST-OF, 0
M(R(P»+D+DF-OF, 0
R(P}+1-R(P}
M(R(P»+D+OF-DF, D
R(P}+1-R(P}
DECIMAL ADJUST-OF, 0
M{R(X»-O-DF, 0
M(R(P})-D-DF, 0;
R/P}+1-R(P}
M(R(X})-D-(NOT OF}-OF, 0
M(R(P})-O-(NOT OF}-OF, 0;
R(P}+1-R(P)
O-M(R(X})-OF, 0
O-M(R(X})-OF, 0
DECIMAL ADJUST-OF, 0
O-M(R(P»-OF. 0;
R(P}+1-R(P}
O-M(R(P»-OF, D
R(P}+1-R(P}
DECIMAL ADJUST-OF, 0
D-M(R(X»-(NOT OF)-OF, 0
D-M(R(X»-(NOT OF}-OF, 0
DECIMAL ADJUST-OF, D
O-M(R(P})-(NOT OF}-OF, 0
R(P)+1-R(P}
O-M(R(P»-(NOT OF)-OF, 0
R(P)+1-R(P}
DECIMAL ADJUST-OF 0
BRANCH INSTRUCTIONS - SHORT BRANCH
SHORT BRANCH
2
NO SHORT BRANCH (SEE SKP)
2
SHORT BRANCH IF D =0
2
BA
NBR
BZ
30
38"
32
SHORT BRANCH IF D NOT 0
BNZ
3A
2
}
75
M(R(P»-R(P}.O
R(P}+1-R(P)
IF D =0, M(R(P»-R(P}.O
ELSE R(P}+1-R(P}
IF 0 NOT 0, M(R(P»-R(P}.O
ELSE R(P}+1-R(P)
"This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
68
..
1800-Serles Microprocessors and Microcomputers
CDP1804AC
Table I - INSTRUCTION SUMMARY (Conl'd)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNII;MONIC
BRANCH INSTRUCTIONS - SHORT BRANCH (Cont'd
SHORT BRANCH IF OF = 1
2
BOF
SHORT BRANCH IF POS OR ZERO
2
BPZ
SHORT BRANCH IF EOUAL OR
2
BGE
GREATER
SHORTBRANCHIFOF=O
BNF
2
SHORT BRANCH IF MINUS
2
BM
SHORT BRANCH IF LESS
2
BL
SHORT BRANCH IF 0 = 1
2
BO
1
1
OP
CODE
OPERATION
33"
IF OF = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
3B"
IF 0 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
31
SHORT BRANCH IF 0 = 0
2
BNO
39
SHORT BRANCH IF EF1 = 1
(EF1 = Vss)
SHORTBRANCHIFEF1=0
(EF1 = Voo)
SHORT BRANCH IF EF2 = 1
(EF2 = Vss)
SHORT BRANCH IF EF2 = 0
(EF2 = Vee)
SHORT BRANCH IF EF3 = 1
EF3 = Vss)
SHORT BRANCH IF EF3 = 0
EF3 = Veo)
SHORT BRANCH IF EF4 = 1
EF4 = Vss)
SHORT BRANCH IF EF4 = 0
(EF4 = Veo)
SHORT BRANCH ON
COUNTER INTERRUPT
SHORT BRANCH ON
EXTERNAL INTERRUPT
2
B1
34
2
BN1
3C
2
B2
35
2
BN2
3D
2
B3
36
2
BN3
3E
2
B4
37
2
BN4
3F
3
BCI
6S3Eo
3
BXI
6S3F
LONG BRANCH
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF 0 = 0
3
3
3
LBR
NLBR
LBZ
CO
CS"
C2
LONG BRANCH IF 0 NOT 0
3
LBNZ
CA
LONG BRANCH IF OF = 1
3
LBDF
C3
LONG BRANCH IF OF = 0
3
LBNF
CB
LONG BRANCH IF 0 = 1
3
LBO
C1
LONG BRANCH IF Q = 0
3
LBNQ
C9
IF 0 = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF 0 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EFl = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF1 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF2 = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF2 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF3 = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF3 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF4 =1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF4 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF CI =1, M(R(P»-R(P).O; O-CI
ELSE R(P)+l-R(P)
IF XI = 1, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
I
BRANCH INSTRUCTIONS - LONG BRANCH
M(R(P»-R(P).l, M(R(P)+l )-R(P).O
R(P)+2-R(P)
IF 0 = 0, M(R(P»-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF 0 NOT 0, M(R(P»-R(P}.l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF OF = 1, M(R(P»-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF OF 0, M(R(P»-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF 0 = 1, M(R(P»-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF 0 = 0, M(R(P»-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
=
T'
t
hIS onstn!ct,on IS aSSocIated wIth more than one mnemonIc. Each mnem 0 ni C is individual! V Ii sed
.
·ETQ cleared by LOC. reset of CPU. or BCI· (CI = 1).
CI = Counter Interrupt. XI = Externallnterrupl.
69
RCA CMOS LSI Products
CDP1804AC
,Teble 1- INSTRUCTION SUMMARY (Cont'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
3
3
SKP
LSKP
LSZ
3S·
CS·
CE
LONG SKIP IF 0 NOT 0
3
LSNZ
C6
LONG SKIP IF OF = 1
3
LSDF
CF
LONG SKIP IF OF = 0
3
LSNF
C7
LONG SKIP IF a = 1
3
Lsa
CD
LONG SKIP IF 0=0
3
LSNa
C5
LONG SKIP IF IE = 1
3
LSIE
CC
IDLE
2
IDL
00"
STOP ON TPB; WAIT FOR DMA OR
INTERRUPT; BUS FLOATS
NO OPERATION
:SETP
SETX
SETa
RESET a
PUSH X, P TO STACK
;3
2
2
2,
2
NOP
SEP
SEX
SEa
REO
MARK
C4
ON
EN
7B
7A
79
CONTINUE
N-P
N-X
1-0
0-0
(X, P)-T; (X, P)-M(R(2»
THEN P-X; R(2)-1-R(2)
l,OAD COUNTER
3
LDC
6S06·
GET COUNTER
STOP COUNTER
3
3
GEC
STPC
6S08
6800
PECREMENT TIMER/COUNTER
SET TIMER MODE AND START
SET COUNTER MODE 1 AND START
SET COUNTER MODE 2 AND START
SET PULSE WIDTH MODE 1
AND START
SET PULSE WIDTH MODE 2
AND START
ENABLE TOGGLE a
3
3
3
3
3
DTC
STM
SCMl
SCM2
SPMl
6801
6807
6805
6803
6804
3
SPM2
6802
3
ETa
6809·
!I
INSTRUCTION
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF 0 = 0
OPERATION
R(P)+l-R(P)
R(P)+-R(P)
IF 0 = O. R(P)+2-R(P)
ELSE CONTINUE
IF 0 NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF OF = 1, R(P)+2-R(P)
ELSE CONTINUE
IF OF = 0, R(P)+2-R(P)
ELSE CONTINUE
IF a = 1, R(P)+2-R(P)
ELSE CONTINUE
IF a = 0, R(P)+2-R(P)
ELSE CONTINUE
IF IE = 1, R(P)+2-R(P)
ELSE CONTINUE
CONTROL INSTRUCTIONS
2
TIMER/COUNTER INSTRUCTIONS
D-COUNTER; O-CI; (IF COUNTER
IS STOPPED)
COUNTER-D
STOP COUNTER CLOCK;
0-+32 PRES CALER
COUNTER-1-COUNTER
TPA+32-COUNTER CLOCK
EF1-COUNTER CLOCK
EF2-COUNTER CLOCK
~.EF1-COUNTER CLOCK;
EFl
-" STOPS COUNT
TPA.EF2-COUNTER CLOCK;
STOPS COUNT
IF COUNTER = 01 • NEXT
COUNTER CLOCK -" :0-0
m-"
.This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
/IAn IDLE instruction initiates an 81 cycle. All external signals, except'the oscillator. are stopped on the low-ta-high transition of TPB. All
outputs remain in their previous states, MfU) is set to a logic '1' and the data bus flpats. The processor will continue to IDLE until an 110 request
(INTERRUPT, DMA-IN, or DMA-OUT)is activated. When the request is acknowiedged, the IDLE cycle is terminated and the 110 request is
serviced, and then normal operation is resumed. (To respond to an INTERRUPT during an IDLE, MIE must be enabled.)
• ETa cleared by LDC, reset of CPU or BCI . (CI = 1).
CI = Counter Interrupt, XI = External Interrupt.
70
1800-Serles Microprocessors and Microcomputers
CDP1804AC
Table I - INSTRUCTION SUMMARY (Conl'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT DISABLE
COUNTER INTERRUPT ENABLE
COUNTER INTERRUPT DISABLE
RETURN
3
3
3
3
2
XIE
XID
CIE
CID
RET
680A
680B
680C
6800
70
DISABLE
2
DIS
71
SAVE
SAVET. D. OF
2
6
SAV
DSAV
78
687()t1
OUTPUT 1
2
OUT 1
61
OUTPUT 2
2
OUT2
62
OUTPUT 3
2
OUT3
63
OUTPUT 4
2
OUT4
64
OUTPUT 5
2
OUT5
65
OUTPUT 6
2
OUT6
66
OUTPUT 7
2
OUT7
67
INPUT 1
2
INP 1
69
INPUT 2
2
INP2
6A
INPUT 3
2
INP3
6B
INPUT 4
2
INP4
6C
INPUT 5
2
INP5
60
INPUT6
2
INP6
6E
INPUT 7
2
INP7
6F
STANDARD CALL
10
SCAL
688N-
ST ANDARD RETURN
8
SRET
689N-
INSTRUCTION
OPERATION
INTERRUPT CONTROL
1-XIE
O-XIE
1-CIE
O-CIE
M(R(X»-X, P;
R(X)+1-R(X); 1-MIE
M(R(X)-X. P;
R(X)+1-R(X); O-MIE
T-M(R(X»
R(X)-1-R(X). T-M(R(X».
R(X)-1-R(X). D-M (R(X».
R(X)-1-R(X). SHIFT 0
RIGHT WITH CARRY. D-MJRJXll
I
INPUT-OUTPUT BYTE TR.ANSFER
M(R(X»-BUS;
N LINES =1
M(R(X»-BUS;
N LINES =2
M(R(X»-BU'3;
N LINES =3
M(R(X»-BUS;
N LINES =4
M(R(X»-BUS;
N LINES =5
M(R(X»-BUS;
N LINES =6
M(R(X»-BUS;
N LINES =7
BUS-M(R(X»;
N LINES =1
BUS-M(R(X»;
N LINES =2
BUS-M(R(X»;
N LINES =3
BUS-M(R(X»;
N LINES =4
BUS-M(R(X»;
N LINES =5
BUS-M(R(X»;
N LINES = 6
BUS-M(R(X»;
N LINES = 7
R(X)+1-R(X);
R(X)+1-R(X);
R(X)+1-R(X);
R(X)+1-R(X);
R(X)+1-R(X);
R(X)+1-R(X);
R(X)+1-R(X);
BUS-D;
I3US-D;
BUS-D;
BUS-D;
BUS-D;
BUS-O;
BUS-D;
CALL AND RETURN
R(N}.O-M(R(X»;
R(N}.1-M(R(X)-1 };
R(X}-2-R(X); R(P)-R(N);
THEN M(R(N»-R(P).1;
M(R(N}+1 )-R(P).O;
R(N}+2-R(N)
R(N}-R(P); M(R(X)+1)-RtN).1;
M(R(X)+2)-R(N}.0;
R(X}+2-R(X}
·Previous contents of T register are destroyed during instruction execution.
71
RCA CMOS LSI Products
CDP1804AC
NOTES FOR TABLE I
1. Long-Branch, Long-Skip and No Op instructions
require three cycles to complete (1 fetch + 2 execute).
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
The long-branch instructions can:
a. Branch unconditionally
b. Test for 0=0 or O¢O
c. Test for OF=O or OF=l
d. Test for 0=0 or 0=1
e. Effect an unconditional no branch
If the tested condition is met, then branching takes
place; the branching addres$ bytes are loaded in the
high-and-Iow-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
If the tested condition is not met, the branching address
bytes are skipped over, and the next instruction in
sequence is fetched and executed. This operation is
taken for the case of unconditional no branch (NLBR).
2. The short-branch instructions are two or three bytes
long. The first byte specifies the condition to betested,
and the second specifies the branching address, except
for the branches on interrupt. For those, the first two
bytes specify the condition to be tested and the third
byte specifiesthe branching address.
The short branch instruction can:
a. Branch unconditionally
b. Test for 0=0 or 0#0
c. Test for OF=O or OF=1
d. Test for 0=0 or 0=1
Test the status (1 or 0) of the four EF flags
f. Effect an unconditional no branch
g. Test for counter or external interrupts (BCI, BXI)
e.
If the tested condition is met, then branching takes
place; the branching address byte is loaded into the
low-order byte position of the current program counter.
This effects a branch within the current 2S6-byte page
of the memory, i.e., the page which holds the branching
address. If the tested condition is not met, the branching
address byte is skipped over, and the next instruction in
sequence is fetched and executed. This same action is
taken in the case of unconditional no branch (NBR).
3. The skip instructions are one byte long. There is one
Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Skip instruction takes 2 cycles
to complete (1 fetch + 1 execute). Its action is to skip
over the byte following it. Then the next instruction in
sequence is fetched and executed. This SKP instruction
is identical to the unconditional no-branch instruction
(NBR) except that the skipped-over byte' is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
72
They can:
a. Skip unconditionally
b. Test for 0=0 or O¢O
c. Test for OF=O or OF=l
d. Test for 0=0 or 0=1
e. Test for MIE=l
If the tested condition is met, then Long Skip takes
place; the current program counter is incremented
twice. Thus two bytes are skipped over and the next
instruction in sequence is fetched and executed. If the
tested condition is not met, then no action is taken.
Execution is continued by fetching the next instruction
in sequence.
4. Instruction 6800 through 68FF take a minimum of 3
machine cycles and up to a maximum of 10 machine
cycles. In all cases, the first two cycles are fetches and
subsequent cycles are executes. The first byte (68) of
these two-byte op codes is used to generate the second
fetch, the second byte is then interpreted differently
than the same code without the 68 prefix. OMA and INT
requests are not serviced until tile end of the last
execute cycle.
5. Arithmetic Operations:
The arithmetic and shift operations are the only
instructions that can alter the content of OF. The syntax
'(NOT OF)' denotes the subtraction of the borrow.
Binary Operations:
After an ADD instruction OF=l denotes a carry has occurred. Result is
greater than FF,e.
OF=O denotes a carry has not occurred.
After a SUBTRACT instruction OF=l denotes no borrow. 0 is a true positive
number.
OF=O denotes a borrow. 0 is in two's complement
form.
Binary Coded Decimal Operations:
After a BCD ADD instruction OF=l denotes a carry has occurred. Result is
greater than 99,0.
OF=O denotes a carry has not occurred.
After a BCD SUBTRACT instruction OF=l denotes no borrow. 0 is a true positive
decimal number.
o
(Example)
99
-88
M(R(X))
IT
o
OF=l
OF=O denotes a borrow. 0 is in ten's complement
form.
(Example)
88
o
-99
M(R(X))
o
OF=O
89
89 is the ten's complement of 11, which is the
correct answer (with a minus value denoted by
OF=O).
1800-Series Microprocessors and Microcomputers
CDP1804AC
CLOCK
TPA--;---'PLH"PHL
TPB~;!~~~~~~~~~~~~;;~;;~j:========I:~~_~~
MEMORY
ADORES S ",,-,,:..L.~"-"..4 ' - - " ' -_ _
+--1""
MRo
( MEMORY
READ CYCLE)
MWR
(MEMORY
WRITE CYCL E I
*ME
'su'S ALLOWABLE
INTERNAL RAM
ACCESS TIME
(MEMORY
ENABLE)
.'EJ',1S
k::-_'~PH~L~_~_~_ _~~
--1
~~J~OF:u~M--~----111------~'----,ir-~r----------------;---r----~"'"
r
( EXTERNAL
MEMORY
SELECT)
~
I
,
I -.j , PLH
I
I
'PHL.----f-T------------r--+----~
i 'PLH
I
I - I 'PHL ,--------i-+---',
__~__~~--------4-~I--~
DATA FROM
INTERNAL
MEMORY
TO BUS
, PLH,
'PHL
PLH'
Q
,--, PLH ,I
rfi~"N2
EXECUTION
C.YCLE)
I
PHL
DATA LATCHED,
,
~~~CPU~/SU
~///
DATA FROM·
BUS TO CPU
r
OMA
,I
I
REQUEST
kNETQEuR:~fT
INTERRUPT
SAMPLED (SI,S2~
I
~
:
:
~ 'su I
WAiT
;
?J7777;
~
'H I
I
,
n~~LLJ~~SND OF SO
l~
I
iI
I,
m'EF4
.---=::'H
///
~SI:S2,S3):::-:-
'H
,.-------------~.t~s~U~'~t~H~r--------
'\O~--I·I..
"-7-1'
t
"I"
1
I
I
*
NOTES:
1, THtS T)MtNG DIAGRAM IS USED TD SHOW SIGNAL RELATIONSHIPS ONLY
AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLL
2, ALL MEASUREMENTS ARE REFERENCED TO SO'Io POINT OF THE WAVEFORMS.
3. SHADED ARE AS INDICATED "DON'T CARE" OR UNDEFINED STATE.
MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD.
92CL- 34986
'FOR THE RUN (RAM ONLY) MODE ONLY •
• FOR THE RUN (RAM/ROM) MODE ONLY.
Fig. 12 - Objective dynamic timing waveforms for CDP1804AC.
73
RCA CMOS LSI Products
CDP1804AC
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=-40 to +85°C, CL =50 pF, YDD =5 Y, ±5"1t.
LIMITS
CHARACTERISTIC
CDP1804AC
Typ."
UNITS
Max.
Propagation Delay Times:
Clock to TPA. TPB
tpLH. tpHL
150
275
Clock-to-Memory High-Address Byte
tPLH. tPHL
325
550
Clock-to-Memory Low-Address Byte
. tPLH. tPHL
275
450
tPLH. tPHL
200
325
tPLH. t~HL
150
275
Clock to lCPU DATA to BUS)
tPLH. tPHL
375
625
Clock to State Coda
tPLH. tpHL
225
400
Clock to Q
tPLH. tPHL
250
425
tPLH. tPHL
250
425
tPLH. tPHL
tPLH. tPHL
420
275
e50
450
tau
-100
0
tH
125
~25
Clock to MFii5
Clock to
MWFf
CloCk to N
Clock to Internal RAM Data to BUS
Clock to EMs
Minimum Set Up and Hold Times:Data Bus Input Set~Up
Data Bus Input Hold
DMASet-U~
-75
0
DMA Hold
tH
100
175
ME Set-Up
tau
-25
0
IH
90
150
ta
ME Hold
tau
-100
0
Interrupt Hold
tH
100
.175
WAIT Set-Up
tsu
20
50
EFl-4 Set-Up
tsu
-125
0
IH
175
300
100
175
Interrupt Set-Up
EFl-4 Hold
ns
ns
Minimum Pulse Width Times:CLEAR Pulse Width
tWL
CLOCK Pulse Width
tWL
125
. 75
ns
"Typical values are for T" = 25° C and nominal Vee.
-Maximum limits of minimum characteristics are the values above which all devices function.
TIMING SPECIFICATIONS al a function of T (T = 1/fCLOCK) at TA = -40 to +85° C, YDD = 5 Y, ±5%.
LIMITS
CDP1804AC
CHARACTERISTIC
High-Order Memory-Address Byte
Set-Up to TPA
"-
Time
Tsu
High-Order Memory-Address Byte
Hold after TPA Time
IH
Low-Order Memory-Address Byte
Hold after WR Time
IH
CPU Data to Bus Hold
after WR Time
IH
Required Memory Access Time
Address to Data
"Typical values are for T" = 25° C and nominal Vee.
74
tACC
Min.
Typ."
2T-275
2T-175
T/2-50
T/2-15
T+O
T+l00
T-200
T-l00
4.5T-400
4.5T-175
UNITS
ns
1800-Series Microprocessors and Microcomputers
CDP1804AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
STATE
I
N
MNEMONIC
RESET
Sl
SO
INITIALIZE
NOT PROGRAMMER
ACCESSIBLE
FETCH
IDL
0
0
0
1
2
3
1-F
O-F
O-F
O-F
4
5
6
O-F
O-F
0
1
2
3
4
5
6
7
9
A
B
C
D
E
F
0
LON
INC
DEC
SHORT
BRANCH
LDA
STR
lAX
OUT 1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
AET
1
DIS
2
3
4
5
LDXA
STXD
ADC
SOB
SHRC
5MB
SAV
MAAK
6
S1
6
7
8
9
A
B
7
8
9
A
B
C
0
E
F
O-F
O-F
O-F
O-F
AEO
SE~
ADCI
SDBI
SHLC
5MBI
GLO
GHI
PLO
PHI
DATA
BUS
MEMORY
ADDRESS
00
UNDEFINED
1
1
0
00·
UNDEFINED
1
1
0
MRP-1, N; RP+1-RP
STOP AT TPB
WAIT FOR DMA OR INT
MRN-D
RN+1-RN
RN-1-RN
TAKEN: MRP-AP.O
NOT TAKEN: RPt1...J.RP
MAN-D' AN+1-RN
D-MRN
RX+1-RX
MRP
FLOAT
RP
RO
0
1
1
1
0
0
MRN
FLOAT
FLOAT
MRP
RN
RN
RN
RP
0
1
1
0
1
1
1
1
0
0
0
0
MAN
D
.MRX
AN
RN
RX
0
1
1
1
0
1
MRX-BUS; RX+1-RX
MRX
RX
0
1
0
0
0
1
2
3
4
5
6
OPERATION
O-O.I.N, COUNTER
PRESCALER, CIL;
1-CIE. XIE
X, P-TTHEN
O-X, P; 1-MIE, OOOO-RO
Do MWii
N
LINES
•
7
BUS-MRX, D
RX
1
0
MRX
RX
0
1
1
2
3
4
5
6
7
0
MAX
AX
0
1
0
MRX
D
MRX
MAX
FLOAT
MAX
T
T
AX
RX
RX
RX
AX
AX
RX
A2
0
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
FLOAT
FLOAT
MAP
MRP
FLOAT
MRP
RN.O
AN.1
D
0
RP
RP
RP
RP
RP
RP
RN
RN
RN
RN
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
DATA
FROM
1/0
DEVICE
MAX-X,P; RX+1-AX
1-MIE
MRX-X,P; RX+1-AX
O-MIE
MAX--D; AX+1-RX
D-MRX' RX-1-RX
MAX+D+DF-DF, D
MRX-D-DFN-DF, D
LSB(D)-DF; DF-MSB(D)
D-MRX-DFN-DF, D
T-MRX
X,P-T, MA2; P-X
A2-1-R2
0-0
1-0
MRP+D+DF-DF, 0; AP+1
MAP-D-DFN-DF, D; AP+1
MSB(D)-DF; DF-LSB(D)
D-MRP-DFN-DF, D; RP+1
RN.O-D
RN.1-D
D-AN.O
D-AN.1
,
., .
0
0
1
0
1
1
1
1
0
0
0
0
0
0
• = Data bus floats for first 2-1/2 clocks of the 9 clock initialization cycle; all zeros for remainder of cycle.
75
RCA CMOS LSI Products
CDP1804AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Confd)
STATE
81#1
#2
81#1 .
#2
81#1
#2
I
C
MNEMONIC
0-3,
8-B
LONG
BRANCH
5
6
7
C
0
E
F
81#1
#2
81#1
#2
0
E
81
N
F
LONG
8KIP
4
NOP
O-F
O-F
0
1
2
3
4
8EP
8EX
LOX
OR
AND
XOA
ADD
SO
SM
8HR
LOI
ORI
ANI
XAI
AOI
SOl
8MI
SHL
5
7
6
8
9
A
B
C
0
F
E
OMA IN
82
S3
76
OMAOUT
INTERAUPT
OPERATION
TAKEN: MRP-B; RP+1-RP
TAKEN:B-RP,l'MRP-RP,O
NOT TAKEN RP+1-RP
NOT TAKEN: RP+1-RP
TAKEN: RP+l-RP
TAKEN: RP+1-RP
DATA
BUS
MRP
M(RP+1)
MRP
M(RP+1)
MRP
M(RP+1)
MRP
NOT TAKEN: NO
OPERATION
M(RP+1)
NOT TAKEN: NO
OPERATION
MRP
NO OPERATION
M(RP+l)
NO OPERATION
NN
N-P
NN
N-X
MRX
MAX-O
MAXOA 0-0
MRX AND 0-0
MAX
MRXXOR 0-0
MAX+O-OF,O
MRX-O-OF,O
O-MAX-OF' 0
FLOAT
LSB(O)-OF; 0-M8B(0)
MRP-O; AP+1-AP
MRP OR 0-0; AP+l-AP
MAP AND 0-0; RP+1-AP
MAP
MAP XOA 0-0; AP+1-AP
MAP+O-OF, 0; AP+1-AP
MRP-O-OF, 0; RP+1-AP
O-MAP-OF, 0; RP+1-AP
FLOAT
MSB(O)-OF; O-LSB(O)
DATA FROM
BUS-MAO; RO+1-RO
110 DEVICE
MRO-BUS; RO+1-RO
MRO
FLOAT
X,P-T; O-MIE
1-P; 2-X
0
0
0
0
0
0
MWR
1
1
1
1
1
1
N
LINES
0
0
0
0
0
0
RP
0
1
0
RP+1
0
1
0
RP
RP+1
RN
AN
RX
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
AX
0
1
0
AX
1
1
0
AP
0
1
0
RP
RO
1
1
1
0
IT
RO
AN
0
1
1
1
0
0
MEMORY
ADDRESS
RP
RP+1
RP
RP+1
RP
RP+1
iiiiD
0
1800-Serles Microprocessors and Microcomputers
CDP1804AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Confd)
STATE
I
N
MNEMONIC
OPERATION
DATA
BUS
MEMORY
ADDRESS
N
MRD
MWR
LINES
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS
"88" PRECEDES ALL THE OP CODES, SO THERE IS A DOUBLE FETCH
S1
S1#1
#2
#3
0
2
0
STPC
1
2
3
4
5
6
OTC
SPM2
SCM2
SPM1
SCM1
LOC
7
8
9
A
B
C
0
STM
GEC
ETQ
XIE
XIO
CIE
CIO
O-F
OBNZ
BCI
E
S1
3
F
S1#1
#2
#3
S1#1
#2
S1#1
#2
#3
#4
S1#1
#2
S1#1
6
7
7
O-F
4
6
BXI
RLXA
OAOC
OSAV
7
7
OSMB
7
C
OACI
#2
S1#1
7
#2
F
OSBI
STOP COUNTER CLOCK;
0-+32 PRESCALER
CNTR-1-CNTR
CNTR-1 ON EF2 AND TPA
CNTR-1 ON EF2 0 TO 1
CNTR-1 ON EF1 AND TPA
CNTR-1 ON EF1 0 TO 1
O-CNTR;O-CIL
(IF CNTR IS STOPPED)
CNTR-1 ON TPA+32
CNTR-O
IF CNTR THRU 0: Q-Q
1-XIE
O-XIE
1-CIE
O-CIE
RN-1-RN
MRP-B; RP+1-RP
TAKEN: B-RP.1; MRPRP.O NOT TAKEN:
RP+1-RP
TAKEN: MRP-RP.O;
O-CI
NOT TAKEN: RP+1-RP
TAKEN: MRP-RP.O
NOT TAKEN: RP+1-RP
MRX-B, RX+1-RX
B-T; MRX-B; RX+1-RX
B T-RN.O RN.1
MRX+O+OF-OF 0
DECIMAL ADJUST-OF 0
RX-1-RX
T-MRX; RX-1-RX
O-MRX; RX-1-RX
SHIFT 0 RIGHT WITH
CARRY
O-MRX
O-MRX-(NOT OF}-OF 0
DECIMAL ADJUST-OF, 0
MAP+O+OF-OF, 0;
RP+1-RP
DECIMAL ADJUST-OF, 0
O-MRP-(NOT OF)-OF, 0;
RP+1-RP
DECIMAL ADJUST-OF, 0
FLOAT
RO
1
1
0
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
0
R1
R2
R3
R4
R5
R6
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
FLOAT
CNTR
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
MRP
M(RP+1)
R7
R8
R9
RA
RB
RC
RO
RN
RP
RP+1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
MRP
RP
0
1
0
0
MRP
RP
0
1
MRX
M(RX+1)
FLOAT
MRX
FLOAT
FLOAT
T
0
RX
RX+1
RN
RX
RP
RX
RX-1
RX-2
0
0
1
1
1
1
1
0
MRX
FLOAT
RX-3
RX
RP
MRP
FLOAT
0
0
1
0
1
1
1
1
0
0
1
0
0
1
1
1
RP
0
1
0
RP+1
1
1
0
0
0
1
MAP
AP
0
1
FLOAT
RP+1
1
1
I
0
0
1
0
0
0
0
0
0
77
R.CA CMOS LSI Products
CDP1804AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Confd)
STATE
S1#1
#2
#3
#4
#5
#6
#7
#8
I
8
N
MNEMONIC
9
O-F
A
O-F
RSXIJ
B
O-F
RNX
C
O-F
RLDI
F
4
DADO
F
7
DSM
F
C
OADI
F
MEMORY.
ADDRESS
-- --
F
MRD
1
1
1
1
1
MWR
1
0
0
1
1
1
1
1
1
RN.O RN.1-T B
RX+1-RX
B, T-RP.1, RP.O
FLOAT
FLOAT
FLOAT
RN·
RX
RP
1
1
1
1
1
1
MRx-a; RX+1-RX
B-T; MRx-a
B, T -RN.O RN.1
RN.O, RN.1-T, a
T-MRX' RX-1-RX
a-MRX; RX-1-RX
RN.O, RN.1-T, B
B T-RX.1 RX.O
MRP-B' RP+1-RP
B-T' MRP-B' RP+1-RP
B, T-RN.O, RN.1;'RP+1-RP
MRX+D-DF 0
DECIMAL ADJUST-OF, 0
D-MRX-DF,D
DECIMAL ADJUST-OF, 0
MRP+D-DF, 0;
RP+1-RP
DECIMAL ADJUST-OF, 0
D-MRP~OF, 0
RP+1-RP
DECIMAL ADJUST-OF, 0
MIRX+1)
M(RX+1)
FLOAT
FLOAT
RN.O
RN.1
FLOAT
FLOAT
MRP
MIRP+11
FLOAT
RX+1
RX+2
RN
RN
RX
RX-1
RN
RX
RP
RP+1
RN
0
0
1
1
1
1
MRX
0
0
N
LINES
0
0
Jl
0
0
0
0
0
Jl
0
-'l
SRET
#2
S1#1
#2
DATA
BUS
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS
"88" PRECEDES ALL THE OP CODES, SO THERE ISA DOUBLE FETCH
RN.O, RN.1-T, a
RN
FLOAT
T-MRX; RX-1-RX
RN.O
RX
a-MRX RX-1-RX
RN.1
RX-1
O-F
SCAl
RP.O RP.1-T a
FLOAT
RP
a T-RN.1 RN.O
FLOAT
RN
MRN-a; RN+1-RN
MRP
RP
M(RP+1)
a-To MRN-B' RN+1-RN
RP+1
B, T-RP.O, RP.1
RP
FLOAT
81#1
#2
#3
#4
#5
#6
S1#1
#2
#3
S1#1
#2
S1#1
#2
#3
S1#1
#2
S1#1
#2
S1#1
OPERATION
DSMI
1
1
1
1
1
1
0
0
0
0
Jl
0
0
Jl
0
0
Jl
1
1
1
1
1
1
RX
0
1
0
FLOAT
MRX
FLOAT
RP
RX
RP
1
0
1
1
1
1
0
0
0
MRP
RP
0
1
0
FLOAT
RP+1
1
1
()
MRP
RP
0
1
0
FLOAT
RP+1
1
1
.0
0
0
-'l
0
78
..
1800-Serles Microprocessors and Microcomputers
CDP1804AC
In"ructlon Summary
N
0
o 1 1 1 2
lOLl
1 3
I
4
1
5
1 6
1
7 1
LON
1
BR I BO I BZ I BDF I B1
I
B2
LOA
STR
IRX 1
INP
OUT
1 • 1
RETl DISJLDXAlsTXDI ADC I SOB ISHRCI 5MB I SAV IMARKI REO I SEa IADCII SDBllsHLClsMBI
8
GLO
9
GHI
A
PLO
B
C
•
PHI
LBR 1LBO 1 LBZ 1LBDF 1 NOP 1LSNO 1LSNZ 1 LSNF 1 LSKP 1LBNO 1LBNZ 1LBNF 1 LSIE 1 LSQ 1 LSZ 1LSDF
SEP
0
E
F
F
DEC
I B3 I B4 I SKP I BNO I BNZ I BNF I BN1 I BN2 1 BN3 1 BN4
4
5
6
7
1 91AIBICIDIEl
INC
2
3
8
SEX
LOX lOR IANDI XOR I ADD I SO
I SHR I SM
I LDI I ORI I ANI I XRI I ADI I SOl I SHL I SMI
'68' LINKED OPCODES (DOUBLE FETCH)
0
STPCI DTC ISPM21SCM21 SPMl 1SCM1 1 LDC 1 STM 1 GEC 1 ETa 1 XIE 1 XID 1 CIE 1 CID 1 -
2
1 -
DBNZ
3
-1-1-1-1-1
-
1 -
1
-
I
-
I
-
1
-
1- 1
-
I BCI 1 BXI
6
7
- I -
-
RLXA
1DSAV 1DSMB 1
-
1
-
1
-
1
-
IDACII
-
1 -
1 DSBI
I -
I -
I DSMI
I -
1 -
IDADCI
1 -
8
SCAL
9
SRET
A
RSXD
B
RNX
C
RLDI
F
-
1 -
1 -
1-
IDADDI
-
I -
IDSM
I -
I -
I - I -
IDADI
• '68' IS USED AS A LINKING OPCODE FOR THE DOUBLE FETCH INSTRUCTIONS.
IMPORTANT NOTICE
Early versions of the CDP1804AC (with NLBJ5, NLBT5, or NR appearing in the bottom brand) fully execute all CDP1802
family, CDP1805C, and CDP1806C instructions, plus the additional eight BCD arithmetic instructions and the new DBNZ
instruction described in the CDP1804AC data sheet. They do not, however, execute the new DSAV instruction.
79
RCA CMOS LSI Products
CDP1804AC
CDP1804AC Mask-Programming
The ROM pattern for the CDP1804AC may be submitted on a
suitable media, such as a punched card deck, floppy diskette,
or EPROM as outlined below in the Programming Options.
In addition t6 specifying the 2K-byte ROM pattern, the
address space for the ROM and RAM must also be defined.
The locations of ROM and RAM in the CDP1804AC are
determined by AND-gate decoders which decode the upper
memory addresses and are programmable at the time of
ROM pattern masking during device fabrication. The logical
values of the decoder inputs are selectable as 1 or P
(positive), 0 orN (negative), or X (don't care). A5-bit decoder
is used for the ROM selection, so the ROM can be placed at
one or more of the 32 available 2K-byte blocks within the
65,536 locations of memory. Similarly, the RAM has a 10-bit
decoder and can be selected at one or mOre of the available
64-byte blocks. If the RAM is located within the ROM space,
the RAM will be enabled at the locations where both are
mapped. The RAM may also be selectively disabled.
Programming Options
2. Translate the upper ten hexadecimal starting addresses
of the RAM block into binary.
The logic levels of high-order address bits are mask
3. Circle the correspondi ng 1 or 0 in columns 28 through 43
programmable in the CDP1804AC. The high (1), low (0), or
on the ROM Information Sheet, Part B.
"don't ca.re" (X) logic status of the high-order address bits is
depend~,nt upon the desired starting address of the 2K-byte Multiple mapping can be achieved by choosing X (don't care)
ROM bh)<;:k and the 64-byte RAM block. The desired logiC for one or more of the high-order address lines; this choice
levels fpr the high-order address bits (A 15 through A6' can be will cause the ROM or RAM block to appear in more than one
selectr,d by use of the ROM information sheet, as follows:
location in the 64K memory space. The RAM may also be
1. Translate the upper five hexadecimal starti ng address of disabled completely by programming the RAM enable bit
(Col. 43) to a O.
the ROM block into binary.
Address Options
SPECIAL NOTE
I ndicate your RAM starting address on the ROM information
sheet, circling the address blocks under th'e RAM heading.
Data Programming Instructions
When a customer submits instructions for programming
RCA custom ROM's, the customer must also complete the
relevant parts of the ROM information sheet and submit this
sheet together with the programming instruction. Programming instructions may be submitted in anyone of three ways.
as follows:
3. Master device - a ROM, PROM, or EPROM that contains
the required programming information.
The requirements for each method are explained in detail in
the following paragraphs:
1. Computer card deck - use standard 80-column computer punch cards.
2. Floppy diskette - diskette information must be generated
on an RCA CDP1800-series microprocessor development
system.
Use standard 80-column computer cards. Each card deck
must contain, in order, a title card, an option card, a dataformat card, and data cards. Punch the cards as specified in
the following charts:
Computer Card Method
Title Card
Column No.
Data
1
2-5
6-30
31-34
35-54
55-58
59-63
64
65-71
72
73
74
75-78
79-80
Punch T
leave blank
"Customer Name (start at 6)
"leave blank
"Customer Address or Division (start at 35)
"'eave blank
"RCA custom selection number (5 digits) (Obtained from RCA Sales .office)
"leave blank
"RCA device type, without COP prefix (e.g., 1804ACE)
Punch an opening parenthesis (
Punch 8
Punch a closing parenthesis)
leave blank
Punch a 2-digit deCimal number to indicate the deck number;
the first deck should be numbered 01
• See ROM Information Sheet ,(Part A)
80
...
1800-Serles Microprocessors and Microcomputers
CDP1804AC
Data Programming Instructions (Cont'd)
Option Card
Use the ROM Information Sheet to select the polarity options, P, N. or X, for the desired ROM type.
Data
Punch the word OPTION
leave blank
Punch CDP1804A
leave blank
Punch 1. O. X. or leave blank per ROM Information Sheet (Part B)
leave blank
Punch the deck number (the 2-digit number in columns 79-80 of the title card)
Column No.
1-6
7
8-17
18-27
28-43
44-78
79-80
I
Data-Format Card
The data-format card specifies the form in which the data is to be entered into ROM.
Column No.
1-11
12
13-15
16
17-19
20-78
79-80
Data
Punch 'the words DATA FORMAT
leave blank
Punch the letters HEX
leave blank
Punch POS
leave blank
Punch the deck number (the 2-digit number in columns 79-80 of the title card)
Data Cards
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four hex digits.
Column No.
Data
Column No.
Data
1-4
Punch the starting address
in hexadecimal for the
following data:
Blank
2 hex digits of 1st WORD
2 hex digits of 2nd WORD
Blank
2 hex digits of 3rd WORD
2 hex digits of 4th WORD
Blank
2 hex digits or 5th WORD
2 hex digits of 6th WORD
Blank
2 hex digits of 7th WORD
2 hex digits of 8th WORD
Blank
26-27
29-29
30
31-32
33-34
35
36-37
38-39
40
41-42
43-44
45
2 hex digits of 9th WORD
2 hex digits of 1Oth,WORD
Blank
2 hex digits of 11th WORD
2 hex digits of 12th WORD
Blank
2 hex digits of 13th WORD
2 hex digits of 14th WORD
Blank
2 hex digits of 15th WORD
2 hex digits of 16th WORD
Semicolon, blank if last card
46-78
79-80
Blank
Punch 2 decimal digits
as in title card
5
6-7
8-9
10
11-12
13-14
15
16-17
18-19
20
21-22
23-24
25
'The address block must be contiguous starting at an even-numbered address. (See Sample Card-Deck Printout on page 28.)
Column 4 must be zero.
To minimize power consumption. all unused ROM locations should contain zeros.
81
RCA CMOS LSI Products
CDP1804AC
Data ProgrammIng InstructIons (Cont'd)
1 23 ... 17 •• ,01112111411,.,71.,120212121242121272.211031.3334113137 .. 8404'42434...54147414110111113541. . . .7115110.,1213 ....... 87 .... 7871 n7S747S7t7771'IW.
TITLE CARD I I I
OP ION CAR
DATA
IT
I
I
,
T
00
'01
H
Q
fOlO
3
0
to
~
F1
r
So
0
0.8
2'
VL.
S
Z J J I
'iI;l.3'
I
0
RC£(
J
t
Co
8
F
A
7
OE:.~
~
8.1
16
I>
t
01>30
~",
.1
0
1/
.
4-~FI£
0
FA40
~,
3+
4- 7
, "
9
;
oI
oI
, 7
"
"
I
,.
12F~
I" A 10;
A
o
o I
oI
o I
oS
X
,
'.ATCA
I? R
loo/OOOQOO()OooO/
3 I
f7:l
•
III
oI
j
DA A
CARDS
,
0
I
H
•
CF
C
02
11 r.p
.,
E:
.
£F~
~3
ob
+ o~
30
"
7
r
t
0
1"1"
FI!'
,
o
F
I
01
A
I
I
1 2 3 " 5 • 7 • • 1011121314'5'1171"120212223242$21272'21 301132 33 M 353137 3131404'414344"5.47414150 5152 5U45S 5151 II 1'10"12131485"17 .. ,170717213 74 71 71 7771 7t 10
92CL-35189
Sample Card-Deck PrIntout
82
Floppy-DIskette Method
Master-DevIce Method
The diskette contains the ROM address and data information. Title, option, and data-format information, which
would otherwise be punched on computer cards, must be
submitted on the ROM Information Sheet. In addition,
specify the RCA Development System used to generate the
diskette (CDP18S005, CDP18S007, or CDP18S008) and
supply a track number or file name, 11 possible, include a
printout of the program for verification purposes. The
format of the address and data information is essentially the
same as that shown on the Sample Card-Deck Printout with
the addition of a carriage-return character at the end of
each line and an end-of-file character (DC3) at the end of
the file.
Data may be submitted on a master ROM, PROM, or
EPROM device. Title, option, and data-format information,
which would otherwise be, punched on computer cards,
must be submitted on the ROM Information Sheet. In
addition, specifiy the master device type; RCA will select
Intel types 1702, 2332A, 2704, 2708, 2716, 2732, 2758,
Supertex CM3200, TI 4732, Motorola MCM68732, and
Motorola MCM68A332, or their equivalents as well as RCA
type CDP18U42. If more than one ROM pattern is stored in
the master device, the starting address and size of each
pattern must be stated on separate ROM Information
Sheets. If the master-device is smaller than 2K bytes, the
starting address of each master-device must be clearly
identified.
1800-Series Microprocessors and Microcomputers
CDP1804AC
ROM Information Sheet
How is ROM pattern being submitted to RCA?
check one
0
0
0
Computer Cards
Floppy Diskette
Master Device (PROM)
(Complete part$ B and C)
(Complete parts A, B, C, and E)
(Complete parts A, B, C, and D)
Customer Name (start at left)
6-30
«
....0::
«Q.
I' 1
II
1 1 1 1 1
35-54
1 1 1 1 1 1
59-63
I
65-71
II
1 1
1
1
IIII IIII
I 1 I Address or Division
IRCA Custom Number (obtained from RCA Sales Office)
1 1 1 1
1 1
I
II IIIII I
1 1 I I I I 1 I
I I I IROM type without CDP prefix (e.g., 1804ACE)
I
INTERNAL
MEMORY
ROM
RAM
RAM
INTERNAL
ADDRESS
A15
A14
A13
A12
A11
A15
A14
A13
A12
AU
A10
AI
AI
A7
AI
ENABLE
COL#
28
29
30
31
32
33
34
35
31
37
31
31
40
41
42
43
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
ID
....
0::
«Q.
OPTIONS
(circle one)
1 =actlve high
O=aetlv. low
X=don't care
()
t-
Starting address of CDP1804AC ROM and RAM blocks (in Hex)
«
Q.
ROM
o::
I I I II
RAM
If a diskette is submitted, check type of
RCA Development System used.
If a master device is submitted,
state type of ROM/PROM:
o
o
....0::
«Q.
Starting and last address
of data block in the
Master Device (in Hex).
1 I I 1 I
~
0::
«
Q.
CDP18S005
Specify: Track#[]]
o
o
CDP18S007
CDP18S008
Specify: File Name: _ _ __
Software program used:
(check one)
ROM SAVE
SAVE PROM
o
o
Software program used:
(check one)
MEMSAVE
SAVE PROM
o
o
83
RCA CMOS LSI Products
CDP1805C, CDP1806C
CLOCK
WAiT
Ci:EAR
Q
se I
seo
Mli1i
BUS
BUS
BUS
BUS
BUS
BUS
8US
BUS
7
6
5
4
3
2
I
0
*N2
NI
NO
VSS
I
2
3
4
5
6
7
40
39
38
37
36
35
34
33
B
9
32
31
10
II
30
12
29
13
28
14
27
26
15
16
25
17
24
23
18
19
22
21
zo
TOP VIEW
Voo
1!TAL
miiA"iR
0IilA0iJl
INTERRUPT
Preliminary Data
CMOS a-Bit Microprocessor With
On-Chip RAM· and Timer/Counter
MWR
TPA
TPB
MA7
MA6
MA5
MA4
MA3
MA2
MAl
MAO
Performance Features:
•
•
•
m
m
m
Instruction time of 4 JlS -40" to
+85"C
113 instructions - upwards software
compatible with COP1802
Pin compatible with COP1802
except for Vee terminal
ffi
16 x 16 matrix of registers for use
as memory pointers (program
counters, data pOinters, stack
pOinters) or as data storage
registers
• On-chip crystal or RC controlled
oscillator
• 64K memory address capability
•
92CS·.476'
TERMINAL ASSIGNMENT
•
* ME
FOR COPI805C
Vee FOR COPI806C
COP1805C only
Upwards software and hardware compatibility are
maintained when substituting a CDP180SC, CDP1806C for
other CDP1800-series microprocessors. Pinout is identifical
except for the replacement of Vcc with ME on the
CDP180SC and the replacement of Vce with VDD on the
CDP1806C.
Timing for the CDP180SC and CDP1806C is the same,
except that 4.S clock pulses are provided for memory
access, Q changes 1/2 cycle earlier during SEQ and REQ
instructions, and the FLAG LINES are sampled at the end of
the SO machine cycle. Schmitt Triggers are provided on all
control inputs, except ME. The only CDP1802 feature not
retained is the LOAD MODE (WAIT = CIE'AR = 0), which is
not allowed on the CDP180SC and CDP1806C.
The RCA-CDP180SC and CDP1806C are functional and
performance enhancements of the CDP1802 LSI CMOS
8-bit register-oriented microprocessor series and are
designed for use in a wide variety of general-purpose
applications.
The CDP180SC enhancements include a 64-byte RAM
array, an 8-bit presettable down-counter, and 22 additional
software instructions, that add subroutine call and return
capability, enhanced data transfer manipulation, and control
over the counter modes and intet'rupt arbitration.
The timer/counter generates an internal interrupt request
on underflow that can be directed to the Q output line can
be used in time-base, event-counting, and pulse duration
measurement applications.
The CDP180SC and CDP1806C have an operating voltage
range of 4 V to 6.S V, and is supplied in a 40-lead hermetic
dual-in-line ceramic package (D suffix) and in a 40-lead
dual-in-line plastic package (E suffix).
The CDP1806C enhancements are identical to thOSE; of the
CDP180SC, but the CDP1806C contains no on-chip RAM.
ADDRESS BUS
.-------....,
-
-
r---- -
-
-
-
-I
- - - --I
:
~ 7
MRO
COPleSI
PROGRAMMABLE
I/O
OUT
r-MA~MA4-,
I
I
I
:
MAO-MA7
MAO - MA7
CDPl805C
CDPI806C
8-BITCPU
COPI833
! I< BYTE ROM
---.JM"Ro
I
I
I
I
CQPI824
I
I 32 BYTE RAM I
I
I
___+(MWR
I
TPA
I
I
II
CDPIB06C
ONLY
--~cs
I
I
I
L-i-,- .-!
BUSO - eUS4
I
'--_____--'''''--_________ J
L _ _ _ _ _ _ _ _ _ _.::B_,.::B:.:.'T,.:D::A.:.:TA:.,:B:.,",:.S_ _ _ _ _ _ _ _
-- ___
I
!
-.1
92CM-~4168
Fig. 1 - Typical COP1BOSC, COP1806C small microprocessor system.
84
..
1800-Serles Microprocessors and Microcomputers
CDP1805C, CDP1806C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDO):
(Voltage referenced to VSS Terminal) ....................................................•.................•...... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....•........................................ ·· ..... ·············· ... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............•... , ............................................................. ± 10 mA
POWER DISSIPATION PER PACKAGE (PD):
For T A = -40 to +60° C (PACKAGE TYPE E) .........•................................................................. 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) ............................................ Derate Linearly at 12mWr C to 200 mW
For TA = -55 to +100° C (PACKAGE TYPE D) ...............................................•......................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE D) ............................•...•......... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...............................••.............. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D .•..........•..........................................................................•... -55 to +125°C
PACKAGE TYPE E ......... " ................•......•. '" ....................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ...•................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ................................................... +265°C
RECOMMENDED OPERATING CONDITIONS atTA
I
=-40 to +8S o C
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following
ranges:
LIMITS
CONDITION
CDP180SCD, CDP180SCE
CHARACTERISTIC
UNITS
CDP1806CD, CDP1808CE
VDD
(V)
MIN.
MAX.
DC Operating Voltage Range
-
4
6.5
Input Voltage Range
-
VSS
VOO
5
4
-
IJs
5
-
0.5
MBytes/s
5
DC
4
V
Minimum Instruction Time * (fCl
=4
MHz)
Maximum OMA Transfer Rate
Maximum Clock Input Frequency,
load Capacitance (Cl)
= 50
pF
MHz
Maximum External Counter/Timer
Clock Input Frequency to EF1, EF2
tClX
5
DC
2
• Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except long Branch, long Skip,
NOP, and "68" family instructions, which are more than two cycles.
85
RCA CMOS LSI Products
CDP180SC, CDP1806C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo = 5 V ± 5%, Except as noted
CONDITIONS
LIMITS
CDP1805CD, CDP1805CE
CDP1806CD, CDP1806CE
CHARACTERISTIC
Quiescent Device Current
Output Low Drive (Sink) Current
~~
~~~
~~p
'DD
IOL
0, 5
5
-
TYP.50
0.4
0, 5
5
1.6
4
-
IOL
0.4
5
5
0.2
0.4
-
IOH
4.6
0,5
5
-1.6
-4
-
IOH
4.6
0
5
-0.1
-0.2
-
VOL
-
0,5
5
-
0
0.1
-
MIN.
UNITS
MAX.
200
pA
(Exceptxm)
XTAL Output
Output High Drive (Source) Current
mA
(Except XTAL)
XTAL
Output Voltage Low-Level
VOH
-
0, 5
5
4.9
5
-
Input Low Voltage (BUS 0 -
BUS 7, ME)
V,L
0.5,4.5
-
5
-
1.5
Input High Voltage (BUS 0 -
BUS 7,
ME)
V,H
0.5,4.5
-
5
3.5
-
-
Output Voltage High Level
Schmitt Trigger Input Voltage
(Except BUS 0 -
V
BUS 7, ME)
Positive Trigger Threshold
Vp
Negative Trigger Threshold
VN
Hysteresis
Input Leakage Current
-
0.5,4.5
5
Input Capacitance
C'N
COUT
Output Capacitance
3.6
1.9
2.8
0.3
1.6
±5
-
0,5
5
-
0, 5
0, 5
5
-
±0.2
±5
liN
lOUT
2.9
0.9
±0.1
VH
3-State Output Leakage Current
2.2
0.9
pA
Total Power Dissipation (1=4 MHz)
Idle "00" at M(OOOO), CL = 50 pF
-
-
-
-
5
7.5
-
-
-
10
15
-
-
5
-
15
30
mW
Minimum Data Retention Voltage
VOR
VDD = VDR
-
2
2.4
V
Data Retention Current
'DR
VDD - 2.4
-
25
100
pA
-Typical values are lor TA = 25°C and nominal VDD.
MEMORY ADDRESS LINES 1/0 FLAG:' 1/0 REQUESTS
I
I
I
\
~
~
CONTROL
OUT
MA6 MA4 MA2 MAO
I
r----\.
ME
FOR COP I B05C
\1 00 FOR CDP IBa6e
I
I
I
CDPIB05C
r~NL'-.L___
,
I
J
t-I64-BnE '4
I ;_~~~y--
- - -- - ----
CONTROL AND
TIMING LOGIC
t----+--t---jTPA
INTERRUPT
LOGIC
BUSO
BUS I
BUS 2
BUS 3
NO} IIO
NI
COMMANDS
BUS 4
N2
BUS 5
BUS 6
BUS 7
92CM-34769
Fig. 2 - Block diagram for CDP1805C and CDP1806C.
86
pF
1800-5erles Microprocessors and Microcomputers
CDP1805C, CDP1806C
TIMING WAVEFORMS FOR POSSIBLE OPERATING MODES
r
INTERNAL RAM READ CYCLE -j--INTERNAL RAM WRITE CYCLE:l
~
00
CLOCK
01
TPA
00
~ ~ ~ ~
~ ~
ro
~ ~ ~ ~
00
ro
II
---.f""I'----_____-+-_-J
I
*
~NE
I
----------.4--1
VALID OATA FROM MEMORY~
92C$-33884RI
•
NOTE:
ME HAS A MINIMUM SETUP AND HOLD TIME WITH RESPECT TO THE BEGINNING
OF CLOCK 70. FOR A MEMORY READ OPERATION. RAM DATA WILL APPEAR ON
THE DATA BUS DURING THE TIME ME IS ACTIVE. THE TIME SHOWN CAN BE
LONGER. IF FOR INSTANCE. A DMA OUT OPERATION IS PERFORMED ON
INTERNAL RAM DATA. TO ALLOW DATA ENOUGH TIME TO BE LATCHED INTO
AN EXTERNAL DEVICE. THE LIMITATION ON MEPULSEWIDTH IS POSSIBLE BUS
CONTENTION. WHICH CAN OCCUR NO eARLIeR THAN CLOCK PULse 31 OF THe
NEXT MACHINE CYCLE.
* FOR CDPI805C ONLY
Fig. 3 -Internal memory operation timing waveforms for CDP1805C and
CDP1806C.
t
CLOCK
EXTERNAL MEMORY READ CYCLE +eXTERNAL MEMORY WRITE CYCLE
~
00
~ ~ ~ ~ ro ~ ~
611
11
01
~ ~ ~ ~ ro
00
II
21
31
41
51
61
1
71
'----__________~I--~r-1~--------------TPB
MEMORY
ADD
r+1
IL
~;;~;;~::::~;;;;~+I-=~;;;;~:::::;;;;;'~~:;:
I HIGH BYTE I
LOW BYTE
I HIGH BYTE I
LOW BYTE
MRD - - ,...._ _ _ _ _ _ _1---'
MWR----------+--------------~~
* (HIGH)
ME IN
i
-----------+1------------DATA BUS
* FOR
~
OATA LATCHEO IN CPU
!
VALID DATA FROM CPU
CDPI805C ONLY
92CS-3477,
Fig. 4 - External memory operation timing waveforms for CDP1805C and
CDP1806C.
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bus):
a-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor, and I/O devices.
NO to N2 (I/O) Lines:
Activated by an 1/0 instruction to Signal the 1/0 control
logic of a data transfer between memory and I/O interface.
These lines can be used to issue command codes or device
selection codes to the 1/0 devices. The N bits are low at all
times except when an 1/0 instruction is being executed.
During this time their state isthe same as the corresponding
bits in the N register. The direction of data flow is defined in
the I/O instruction by bit N3 (internally) and is indicated by
the level of the MAD signal:
MiID
= VDD:
MRD = VSS:
Data from I/O to CPU and Memory
Data from Memory to I/O
87
RCA CMOS LSI Products
CDP1805C, CDP1806C
SIGNAL DESCRIPTIONS (Cont'd)
m to EF4 (4 Flags):
f.iiiD (Read Level):
These inputs enabl.e the.I/O controllers to transfer status
information to the processor. The levels can be tested by
the conditional branch instructions. They can be used in
conjunction with the INTERRUPT request line to establish
interrupt priorities. The flag(s) are sa!!!.e!ed at the end of
every SO cycle. One additional use for EF1 and
is event
counting and pulse width measurement in conjunction with
the Timer/Counter.
A low level on MRO indicates a memory read cycle. It can be
used to control three-state outputs from the addressed
memory and to indicate the direction of data transfer during
an I/O instruction.
m
INTERRUPT, DMA-IN, DMA-OUT (3 I/O Requests)
These inputs are sampled by the COP1805C and COP1806C
during TPB.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
set to 1; interrupt enable is reset to 0 (inhibit); and
instruction execution is resumed. The interrupt action
requires one machine cycle (S3).
DMA Action: Fini.sh executing current instruction; R(O)
points to memory area for data transfer; data is loaded into
or read out of memory; and increment R(O).
Note: In the event of concurrent OMA and INTERRUPT
requests, OMA-IN has priority followed by OMA-OUT and
then INTERRUPT. .
Q:
Single bit output from the CPU which can be set or reset,
between the trailing edge of TPA and the leading edge of
TPB, under program control. The Enable Toggle a
command connects the a-line flip-flop to the output of the
counter, such that each time the counter decrements from
01 to its next value, the a line changes state. This command
is cleared by a LOAD COUNTER (LOC) instruction, a CPU
reset, or.a BRANCH COUNTER INTERRUPT (BCI)
instruction with the counter interrupt flip-flop set.
CLOCK:
Input for externally generated single-phase clock. The
maximum clock frequency is 4 MHz at VOO = 5 V. The clock
is counted down internally to 8 clock pulses per machine
cycle.
XTAL:
Connection to be used with clock input terminal, for an
external crystal, if the on-chip oscillator is utilized.
SCO, SC1, (2 State Code Lines):
WAiT, CLEAR (2 Control Lines):
These outputs indicate that the CPU is: 1) fetching an
instruction, or 2) executing an instruction, or 3) processing
a OMA request, or 4) acknowledging an interrupt request.
The levels of state code are tabulated below. All states are
valid at TPA.
Provide four control modes as listed in the following truth
table:
State Type
SO
S1
S2
S3
(Fetch)
(Execute)
(OMA)
(Interrupt)
State Code Lines
SC1
SCO
L
L
L
H
H
L
H
H
H = Voo, L = Vss.
TPA, TPB (2 Timing Pulses):
Positive pulses that occur once in each machine cycle (TPB
follows TPA). They are used by lIO controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the
high-order byte of the 16-bit memory address.
MAO to MA7 (8 Memory Address Lines):
In each cycle, the higher-order byte of a 16-bit memory
address appears on the memory address lines MAO-7 first.
Those b.its required by the memory system can be strobed
into external address latches by timing pulse TPA. The
low-order byte of the 16·bit address appears on the address
lines after the termination of TPA.
MWR (Write Pulse):
A negative pulse appearing in a memory-write cycle, after
the address lines have stabilized.
--CLEAR
L
L
H
H
-WAIT
L
H
L
H
MODE
NOT ALLOWED
RESET
PAUSE
RUN
ME (Memory Enable CDP180SC Only):
This active low signal line is used to select or deselect the
internal RAM. It must be active at the beginning of clock 70
for an internal RAM access to take place. I nternal RAM data
will appear on the data bus during the timethat ME is active
(after clock 31). Thus, if this data is to be latched into an
external devi~ie.; during an OUTPUT instruction or OMA
OUT cycle). ME shOUld be wide enough to provide enough
time for valid data to be latched.
The internal RAM is not internally mask-decoded. Decoding
of the starting address is performed externally, and may
reside in any 64 byte block of memory.
VDD (CDP1806C Only):
This input replaces the ME signal of the COP1805C and
must be connected to the positive power supply.
VOD, VSS, (Power Levels):
VSS is the most negative supply voltage terminal and is
normally connected to ground. VOO is the positive supply
voltage terminal. All outputs swing from VSS to VOO. The
recommended input voltage swing is from VSS to VOO.
88
...
1800-5erles Microprocessors and Microcomputers
CDP1805C, CDP1806C
ARCHITECTURE
Fig. 1 shows a block diagram of the CDP1805C and
CDP1806C. The principal feature of this system is a register
array (R) consisting of sixteen 16-bit scratchpad registers.
Individual registers in the array (R) are designated (selected)
bya 4-bit binary code from one of the 4-bit registers labeled
N, p, and X. The contents of any register can be directed to
anyone of the following three paths:
1.
2.
the external memory (multiplexed, higher-order byte
first on to 8 memory address lines)
the 0 register (either of the two bytes can be gated to
D)
3.
the increment/decrement circuit where it is increased
or decreased by one and stored back in the selected
16-bit register.
The three paths, depending on the nature of the instruction,
may operate independently or in various combinations in
the same machine cycle.
Most instructions consist of two a-clock-pulse machine
cycles. The first cycle is the fetch cycle, and the second
-and more if necessary - are execute cycles. During the
fetch cycle the four bits in the P designator select one of the
16 registers R(P) as the current program counter. The
selected register R(P) contains the address of the memory
location from which the instruction is to be fetched. When
the instruction is read out from the memory, the higherorder 4 bits of the instruction byte are loaded into the I
register and the lower-order 4 bits into the N register. The
content of the program counter is automatically
incremented by one so that R(P) is now "pointing" to the
next byte in the memory.
The X designator selects one of the 16 registers R(X) to
"point" to the memory for an operand (or data) in certain
ALU of I/O operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. designate one of the 16 registers in R to be acted
upon during register operations
2. indicate to the I/O devices a command code or
device-selection code for peripherals
3. indicate the specific operation to be executed during
the ALU instructions, types of tests to be performed
during the Branch instructions, or the specific
operation required in a class of miscellaneous
instructions
4. indicate the value' to be loaded into P to designate a
new register to be used as the program counter R(P)
5. indicate the value to be loaded into X to designate a
new register to be used as data pointer R(X).
Data Pointer.
The registers in R may be used as data painters to indicate a
location in memory. The register designated by X (i.e. R(X))
points to memory for the following Instructions (see Table
1 ):
1.
2.
3.
4.
5.
ALU operations
output instructions
input instructions
register - - memory transfer
interrupt and subroutine handling.
The register designated by N (i.e. R(N)) points to memory
for the "load 0 from memory" instructions ON and 4N and
the "Store 0" instruction 5N. The register designated by P
(i.e.; the program counter) is used as the data pointer for
ALU instructions F8-Fo, FF, 7C, 70, 7F, and the RLol
instruction 68CN. During these instruction executions, the
operation is referred to as "data immediate".
Data Regl.ter.
When registers in R are used to store bytes of data,
instructions are provided which allow 0 to receive from or
write into either the higher-order- or lower-order-byte
portions of the register designated by N. By this mechanism
(together with loading by data immediate) program painter
and data pointer designations are initialized. Also, this
technique allows scratch pad registers in R to be used to
hold general data. By employing increment or decrement
instructions, such registers may be used as loop counters.
Regllter Summary
0
DF
B
R
P
a Bits
1 Bit
8 Bits
16 Bits
4 Bits
Program Counters
X
4 Bits
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other
registers in R can be used as subroutine program counters.
By a Single instruction the contents of the P register can be
changed to effect a "call" to subroutine. When interrupts
are being serviced, register R(1) is used as the program
counter for the user's interrupt servicing routine. After
reset, and during a DMA operation, R(O) is used as the
program counter. At all other times the register designated
as program counter is at the discretion of the user.
N
I
T
4 Bits
4 Bits
8 Bits
MIE
1 Bit
1 Bit
8 Bits
The registers in R can be assigned by a programmer in
three different ways as program counters, as data painters,
or as scratch pad locations (data registers) to hold two
bytes of data.
•
Another important use of R as a data painter supports the
built-in oirect-Memory-Access (oMA) function. When a
DMA-In or oMA-Out request is received, one machine
cycle is "stolen". This operation occurs at the end of the
execute machine cycle in the current instruction. Register
R(O) is always used as the data poil1ter during the oMA
operation. The data is read from (oMA-Out) or written into
(DMA-In) the memory location painted to by the R(O)
register. At the end of the transfer, R(O) is incremented by
one so that the processor is ready to act upon the next oMA
byte transfer request. This feature in the CoP1805C and
CDP1a06C architecture saves asubstantial amount of logic
when fast exchanges of blocks of data are required, such as
with magnetic discs or during CRT-display-refresh cycles.
Q
CH
Data Register (Accumulator)
Data FIEl.Q.jALU Carm
Auxilia~ Holding Register
1 of 16 Scratch~ad Re.Bisters
Designates which register is
Program Counter
Designates which register is
Data P-.2inmr
Holds Low-Order Instr. Digit
Holds High-Order Instr. Digit
Holds old X, P after Interrupt
(X is high nibblel
Master Intern,lm Enable
Ou!put FIl£. FI~
Holds Counter Jam Value
89
RCA CMOS LSI Products
CDP1805C,CDP1806C
ARCHITECTURE (Conl'd)
On-Chip Clock (See Fig. 7 and 8)
Clock circuits may use either an external crystal or an
RC network.
The crystal is connected between terminals 1 and 39
(CLOCK and XTAL) in parallel<,vith a resistance (1 megohm
typ.) .
X, P, and R(O) are reset. Interrupt and DMA servIcing
suppressed during the initialization cycle. The next cycle is
an SO or an S2 but never an S1 orS3. The use of a 71
instruction followed by 00 at memory locations 0000 and
0001, may be used to reset MIE, so as to preclude interrupts
until ready for them. Power-up reset run can be realized by
connecting an RC network to CLEAR (See Fig. 9)
• Frequencylrimming capacitors may be required atterminals
1 and 39. For additional information on crystal oscillators,
see ICAN-6565. Because of the Schmitt Trigger input, an
RC oscillator can be used as shown in Fig. 7. The frequency
is approximately 1/RC (See Fig. 8).
The RC time constant
should be greater
than the oscillator
start-up time
(typically 20 ms)
CDPIB05C
COPIB06C
RS
92CS-3477ZRI
R
Fig. 9 - Reset diagram.
4 VOD '" 5V AT 25"C
PAUSE
Stops the internal CPU timing generator, freezing the state
of the processor. Pause can occur at two points in a
machine cycle, on the low-to-high transition of either TPA
or TPB.
The oscillator continues to run but subsequent clock
transitions are ignored. TPA and TPB remain at their
previous state (See Fig. 10).
B4
If Pause is entered wtli1e in the event counter mode, the
appropriate Flag transitions will continue to decrement the
counter.
Fig. 7 - RC network for oscillator.
TPA PAUSE TIMING
ENTER
PAUSE
RESUME
~
~
RUN
CLOCK
TPA
WAIT
10""~:----I---t-----P-----P'---t---,.,
TPB PAUSE TIMING
2-
ENTER
PAlSE
2
468
10
2
468
100
2
468
IK
FREQUENCY
2 468
10K
2
468
2
lOOK
(Hz)
92CS- 34172
Fig. 8 - Nominal component values as a function of frequency
for the RC oscillator.
I
t,~~~~I~~----I--tsu
92CM-31944
WAIT
L
H
L
H
MODE
NOT ALLOWED
RESET
PAUSE
RUN
The function of the modes are defined as follows:
RESET
Registers I, N, Q, counter prescaler, and counter interrupt
latch are reset. MIE, XIE, and CIE are set and a's (VSS) are
placed on the data bus. TPA and TPB are suppressed while
reset is held and the CPU is placed in S1. The state of the
counter/timer is unaffected by the RESET operation.
The first machine cycle after termination of reset is an
initialization cycle which requires 9 clock pulses. During
this cycle the CPU remains in S1. X, P,T, and then registers
90
I
TPS
~
CONTROL MODES
CLEAR
L
L
H
H
CLOCK
NOTE
PAUSE (IN CLOCK WAVEFORM) WHILE REPRESENTED HERE AS ONE CLOCK
CYCLE IN DURATION. COULD BE INFINITELY LONG.
Fig. 10 - Pause mode timing waveforms.
RUN
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the next
high-to-Iow clock transition, wt,ile if paused at TPB, it will
resume on the next low-to-high clock transition (See Fig.
9). When initiated from the Reset operation, the first
machine cycle following Reset is always the initialization
cycle. The initialization cycle is then followed by a DMA
(S2) cycle or fetch (SO) from location 0000 in memory.
SCHMITT TRIGGER INPUTS
All inputs except BUS a - BUS 7 and ME contain aSchmitt
Trigger circuit, which is especially usefull on the CLEAR
input as a power-up RESET (See Fig. 10) and the CLOCK
input (See Fig. 7).
1800-Series Microprocessors and Microcomputers
CDP180SC, CDP1806C
STATE TRANSITIONS
The CDP1805C and CDP1806C state transitions are shown
in Fig. 11. Each machine cycle requires the same period of
time, 8 clock pulses, except the initialization cycle (lNIT)
which requires 9 clock pulses.
(LONG BRANCH.
LONG SKIP, NOP, RSXD, ETC)
INT. DMi • FORCE 51
PRIORITY:
I
FORCE SO, 51
ffiiA IN
DiiAOUT
iNT
92C$-34778
Fig. 11 - State transition diagram.
Additional Timing Waveform Noles (See Fig. 12)
The CDP1805C and CDP1806C timing specification for
latching external data into the CPU requires some additional
clarification.
As specified data is latched at the beginning of clock pulse
70, with a data setup time required before that edge. While
this is generally true, there may be some extremely slow
applications where data will be required at an earlier time.
As shown in Fig. 12, valid data must be present during the
time that clock 61 • INTERNAL STROBE is valid.
INTERNAL STROBE provides a worst-case fixed width of
50 ps at 5 volts over the full temperature range, rather than a
width dependent on crystal-clock frequency. This width
overlaps Clock 61 for frequencies above 10 kHz (SOps il!.,1/2
clock pulse at 10 kHz), and data is latched on the high~to
low transition cf clock 61.lf the clock frequency used is less
than 10 kHz, the high-to-Iow transition of INTERNAL
STROBE becomes the Latch control and data must be
present during the time that INTERNAL STROBE is valid.
If the CDP1805C and CDP1806C are used in the pause
mode, clock timing will stop at the leading edge of TPB (or
TPA). Any data which changes after this time must be valid
within 50 ps of the beginning of clock 61 for proper latching
into the CPU.
CLOCK
I NTERNAl STROBE
TPB
VALID DATA
I LATCHED.
IN CPU
92CM-34049
Fig. 12 - Control-timing waveforms for CDPl805C and CDPl806C.
91
RCA CMOS LSI Products
CD·P1805C, CDP1806C
INSTRUCTION SET
The CDP1805C and CDP1806C instruction summary is
given in Table I.. Hexadecimal notation is used to refer to the
4-bit binary codes.
In all registers bits are numbered from the least significant
bit (LSB) to the most significant bit (MSB) starting with O.
R(W): Register designated by W. where
WoN or X. or P
R(W) 0: Lower-order byte of R(W)
R(W) 1: Higher-order byte of R(W)
Operation Notation
M (R(N))-D; R(N) + 1-R(N)
This notation means: The memory byte pointed to by R(N)
is loaded into D. and R(N) is incremented by 1.
TABLE I - INSTRUCTION SUMMARY (For Notes, see also page 15)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
5
LDI
RLDI
F8
68CN-
LOAD VIA N
LOAD ADVANCE
LOAD VIA X
LOAD VIA X AND ADVANCE
REGISTER LOAD VIA X AND
ADVANCE
STORE VIA N
STORE VIA X AND DECREMENT
REGISTER STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
D.cREMENT REG N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HtGH REG N
PUT HIGH REG N
REGISTER N TO REGISTER X COPY
LOGIC OPERATIONSt
OR
OR IMMEDIATE
2
2
2
2
5
LON
LOA
LOX
LDXA
RLXA
ON
4N
FO
72
686N-
2
2
5
STR
STXD
RSXD
5N
73
68AN_
2
2
2
2
2
2
2
4
INC
DEC
IRX
GLO
PLO
GHI
PHI
RNX
1N
2N
60
8N
AN
9N
BN
68BN-
2
2
01'1
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
2
2
XOR
XRI
F3
FB
AND
AND IMMEDIATE
2
2
AND
ANI
F2
FA
SHIFT RIGHT
2
SHR
F6
SHIFT RIGHT WITH CARRY
2
SHRC!
RING SHIFT RIGHT
SHIFT LEFT
2
2
RSHR
SHL
SHIFT LEFT WITH CARRY
2
SHLC
RING SHIFT LEFT
2
RSHL
INSTRUCTION
MEMORY REFERENCE
LOAD IMMEDIATE
REGISTER LOAD IMMEDIATE
1
76.
FE
7E.
OPERATION
M(R(P))-D; R(P)+1-R(P)
M(R(P))-R(N).1; M(R(P)+1R(N).O; R(P)+2-R(P)
M(R(N)-D: FOR N NOT 0
M(R(N)-D: R(N)+1-R(N)
M(R(X)-D
M(R(X))-D: R(X)+1-R(X)
M(R(X)) -R(N).1; M(R(X)+1)R(N).O; R(X))+2-R(X)
D-M(RN)
D-M(R(X)): R(X)-1-R(X)
R(N).O-M(R(X)); R(N).1M(R(X)-1); R(X)-2-R(X)
R(N)+l-R(N)
R(N)-1-R(N)
R(X)+1-R(X)
R(N).O-D
D-R(N).O
R(N).l-D
D-R(N).1
R(N)-R(X)
M(R(X)) OR 0-0
M(R(P)) OR 0-0;
R(P)+1-R(P)
M(R(X)) XOR 0-0
M(R(P)) XOR 0-9;
R(P)+1-R(P)
M(R(X)) AND 0-·0
M(R(P)) AND 0-0:
R(P)+l-R(P)
SHIFT 0 RIGHT. LSB(D)-DF.
O-MSB(D)
SHIFT 0 RIGHT. LSB(D)-DF.
DF-MSB(D)
SHIFT 0 LEFT. MSB(D)-DF.
O-LSB(D)
SHIFT D LEFT. MSB(D)-DF.
DF-LSB(D)
.. ~
-Previous contents of T register are destroyed during Instruction Execution.
tSee page 12 .
• This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
92
...
1800-Serles Microprocessors and Microcomputers
CDP180SC, CDP1806C
TABLE I - INSTRUCTION SUMMARY (Cont'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
ADD
ADI
AOC
ADCI
F4
FC
74
7C
SO
SOl
F5
FD
2
SOB
SDBI
75
70
2
2
SM
SMI
F7
FF
2
2
StiIIB
5MBI
77
7F
SHORT BRANCH
NO SHORT BRANCH (SEE SKP)
SHORT BRANCH IF 0 = 0
2
2
2
BR
NBR
BZ
30
38.&
32
SHORT BRANCH IF 0 NOT 0
2
BNZ
3A
SHORT BRANCH
SHORT BRANCH
SHORT BRANCH
GREATER
SHORT BRANCH
SHO,RT BRANCH
SHORT BRANCH
SHORT BRANCH
2
2
2
BOF
BPZ
BGE
2
2
2
2
BNF
BM
BL
Ba
2
BNa
39
=1
2
B1
34
=0
2
BN1
3C
=1
2
B2
35
INSTRUCTION
ARITHMETIC OPERATIONSt
ADD
ADD IMMEDIATE
ADD WITH CARRY
ADD WITH CARRY, IMMEDIATE
SUBTRACT 0
SUBTRACT 0 IMMEDIATE
SUBTRACT
SUBTRACT
BORROW,
SUBTRACT
SUBTRACT
0 WITH BORROW
0 WITH
IMMEDIATE
MEMORY
MEMORY IMMEDIATE,
SUBTRACT MEMORY WITH BORROW
SUBTRACT MEMORY WITH
BORROW, IMMEDIATE
2
2
2
:1
2
2
2
OPERATION
M(R(X))+D-DF, 0
M(R(P))+O-OF, 0; R(P)+l-R(P)
M(R(X))+O+OF-OF, 0
M(R(P))+D+DF-OF, 0
R(P)+l-R(P)
M(R(X))-O-DF, 0
M(R(P))-D-DF, 0;
R(P)+l-R(P)
M(R(X)-D-(NOT DF)-DF, 0
M(R(P)-D-(NOT OF)-OF, 0;
R(P)+l-R(P)
D-M(R(X))-OF, 0
O-M(R(P))-OF, 0;
R(P)+l-R(P)
O-M(R(X))-(NOT OF)-OF, 0
O-M(R(P))-(NOT DF)-OF, 0
R(P)+l-R(P)
I
BRANCH INSTRUCTIONS - SHORT BRANCH
IF OF = 1
IF POS OR ZERO
IF EaUAL OR
IF
IF
IF
IF
OF = 0
MINUS
LESS
a =1
SHORT BRANCH IF a
=0
SHORT BRANCH IF EF1
(EF1 = VSS)
SHORT BRANCH IF EF1
(EFT = VOO)
SHORT BRANCH IF EF2
(ill = VSS)
tTlie Arithmetic operations and the shift
instructions are the only instructions
that can alter the OF after an
ADD instruction:
OF = 1 denotes a carry has occurred
OF =0 denotes a carry has not occurred
After a SUBTRACT instruction:
OF = 1 denotes no borrow. 0 is a true
postivenumber
I
33.&
I
3B.&
31
M(R(P))-R(P).O
R(P)+l-R(P)
IF 0 = 0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF 0 NOT 0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF OF = 1, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF 0 = 0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF a = 1, M(R(P))-R(P).O
ELSE R(P)+1-:R(P)
IF a = 0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF1 = 1, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF EF1 = 0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF EF2 = 1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
OF = 0 denotes a borrow, D is two's complement
the syntax" -(NOT OF)" denotes the
subtraction of the borrow
.& This i,nstruction is associated with more than
one mnemonic, Each mnemonic is
individually listed.
93
RCA CMOS LSI Products
CDP1805C, CDP1806C
TABLE I - INSTRUCTION SUMMARY (Cont'd)
I
NO,OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
BN2
3D
2
B3
36
2
BN3
3E
2
B4
37
2
BN4
3F
3
BCI
6a3E-
3
BXI
6a3F
3
3
3
LBR
NLBR
LBZ
CO
ca.
C2
LONG BRANCH IF D NOT 0
3
LBNZ
CA
LONG BRANCH IF DF = 1
3
LBDF
C3
LONG BRANCH IF DF = 0
3
LBNF
CB
LONG BRANCH IF Q = 1
3
LBQ
C1
LONG BRANCH IF Q = 0
3
LB"JC:
C9
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF D = 0
2
3
3
SKP
LSKP
LSZ
3a ....
ca.
CE
LONG SKIP IF D NOT 0
3
LSNZ
C6
LONG SKIP IF DF = 1
3
LSDF
CF
LONG SKIP IF DF = 0
3
LSNF
C7
LONG SKIP IF Q = 1
3
LSQ
CD
LONG SKIP IF Q = 0
3
LSNQ
C5
LONG SKIP IF IE = 1
3
LSIE
CC
INSTRUCTION
OPERATION
BRANCH INSTRUCTIONS - SHORT BRANCH (Cont'd)
SHORT BRANCH IF EF2 = 0
(EF2 = VDD)
SHORT BRANCH IF EF3 = 1
= VSS)
SHORT BRANCH IF EF3 = 0
EF3= VDD)
SHORT BRANCH IF EF4 = 1
EF4'= VSS)
SHORT BRANCH IF EF4 = 0
(EF4 = VDD)
SHORT BRANCH ON
COUNTER INTERRUPT
SHORT BRANCH ON
EXTERNAL INTERRUPT
BRANCH INSTRUCTIONS - LONG BRANCH
LONG BRANCH
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF D = 0
m
IF EF2 = 0, M(R(P»-R(P).O
ELSE R(P)+l-R(P)
IF EF3 = 1, M(R(P»)-R(P).O
ELSE R(P)+l-R(P)
IF EF3 = 0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF EF4 =1, M(R(P»)-R(P).O
ELSE R(P)+l-R(P)
IF EF4 = 0, M(R(P))-R(P).O
ELSE R(P)+l-R(P)
IF CI =1, M(R(P))-R(P).O; O-CI
ELSE R(P)+l-R(P)
IF XI = 1, M(R(P»)-R(P).O
ELSE R(P)+l-R(P)
M(R(P»)-R(P).l M(R(P)+l)-R(P).C
R(P)+2-R(P)
IF D = 0, M(R(P))-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF D NOT 0, M(R(P»)-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF DF = 1, M(R(P))-R(P).l
M(R(P)+l)-R(P).O
ELSE R(P)+2-R(P)
IF DF = 0, M(R(P))-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF Q = 1, M(R(P»)-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
IF Q = 0, M(R(P))-R(P).l
M(R(P)+l )-R(P).O
ELSE R(P)+2-R(P)
R(P)+l-R(P)
R(P)+2-R(P)
IF D = 0, R(P)+2-R(P)
ELSE CONTINUE
IF D NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF DF = 1, R(P)+2-R(P)
ELSE CONTINUE
IF DF = 0, R(P)+2-R(P)
ELSE CONTINUE
IF Q = 1, R(P)+2-R(P)
ELSE CONTINUE
IF Q = 0, R(P)+2-R(P)
ELSE CONTINUE
IF IE = 1, R(P)+2-R(P)
ELSE CONTINUE
• This instruction is associated with more than one mnemonic, each mnemonic is individually listed.
CI = counter interrupt
:l<1 = external interrupt
-ETQ cleared by LDC, reset of CPU, or BCI - (CI = 1)
94
18QO-Serles Microprocessors and Microcomputers
CDP1805C, CDP1806C
TABLE I - INSTRUCTION SUMMARY (Cont'd)
INSTRUCTION
NO. OF
MACHINE
CYCLES
OP
MNEMONIC CODE
CONTROL INSTRUCTIONS
IDLE
2
IDL
00#
NO OPERATION
SET P
SET X
SET a
RESET a
PUSH X, P TO STACK
3
2
2
2
2
2
NOP
SEP
SEX
SEa
REO
MARK
C4
DN
EN
7B
7A
79
COUNTER INSTRUCTIONS
LOAD COUNTER
GET COUNTER
STOP COUNTER
3
3
3
LDC
GEC
STPC
3
3
3
3
3
DTC
STM
SCM1
SCM2
SPMl
3
SPM2
3
ETa
3
3
3
3
2
2
2
XIE
XID
CIE
CIO
RET
DIS
SAV
680A
680B
680C
6800
70
71
78
2
2
2
2
2
2
2
2
2
2
2
2
2
2
OUTl
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
INP 1
INP2
INP3
INP 4
INP5
INP6
INP 7
61
62
63
64
65
66
67
69
6A
68
6C
60
6E
6F
DECREMENT COUNTER
SET TIMER MODE AND START
SET COUNTER MODE 1 AND START
SET COUNTER MODE 2 AND START
SET PULSE WIDTH MODE 1
AND START
SET PULSE WIDTH MODE 2
AND START
ENABLE TOGGLE a
INTERRUPT CONTROL
EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT DISABLE
COUNTER INTERRUPT ENABLE
COUNTER INTERRUPT DISABLE
RETURN
DISABLE
SAVE
INPUT-OUTPUT BYTE TRANSFER
OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
OPERATION
WAIT FOR DMA OR INTERRUPT;
M(R(O))-BUS
CONTINUE
N-P
N-X
1-0
0-0
(X, P)-T; (X, P)-M(R(2))
THEN P-X' R(2l-1-R(2l
6806- D-COUNTER; O-CI;STOP COUNTER
6808 COUNTER-D
6800 STOP COUNTER CLOCK;
0-+32 PRESCALER
6801 COUNTER-l-COUNTER
6807 TPA+32-COUNTER CLOCK
6805 EFT-COUNTER CLOCK
6803 m-COUNTER CLOCK
6804 TPA.ffi-cOUNTER CLOCK;
I STOPS COUNT
6802 lli.EF2-COUNTER CLOCK;
EF2 f STOPS COUNT
6809- IF COUNTER = 01-NEXT COUNTER
CLOCK f : a-a
I
m
l-XIE
O-XIE
l-CIE
O-CIE
M(R(X))-X.P;R(X)+1-R(X);1-MIE
M(R(X)-X,P;R(X)+l-R(X);O-MIE
T-M(R(X))
M(R(X) )-BUS;R(X)+1-R(X);N LlNES=1
M(R(X))-BUS;R(X)+1-R(X);N LlNES=2
M(R(X))-BUS;R(X)+l-R(X);N LlNES=3
M(R(X»-BUS;R(X)+l-R(X);N LlNES=4
M(R(X»)-BUS;R(X)+l-R(X);N LlNES=5
M(R(X))-BUS;R(X)+l-R(X);N LlNES=6
M(R(X))-BUS;R(X)+1-R(X);N LlNES=7
BUS-M(R(X»;BUS-D;N LlNES=l
BUS-M(R(X);BUS-D;N LlNES=2
BUS-M(R(X»;BUS-O;N LlNES=3
BUS-M(R(X));8US-O;N LlNES=4
BUS-M(R(X));BUS-D;N LlNES=5
BUS-M(R(X»;BUS-O;N LlNES=6
BUS-M(R(X»);BUS-D;N LlNES=7
#An IDLE instruction initiates a repeating Sl cycle. The processor will continue to idle until an I/O request (INTERRUPT,
DMA-IN, or OMA-OUT) is activated. When the request is acknowledged, the IDLE cycle is terminated and the I/O request is
serviced, and then normal operation is resumed.
-ETa cleared by LOC, reset of CPU, or BCI-(CI = 1).
95
RCA CMOS LSI Products
CDP1805C, CDP1806C
TABLE I -INSTRUCTION SUMMARY (Cont'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
STANDARD CALL
10
SCAL
688N-
STANDARD RETURN
8
SRET
689N-
INSTRUCTION
OPERATION
CALL AND RETURN
R(N).O-M(R(X);
R(N).1-M(R(X)-1 );
R(X)-2-R(X); R(P)R(N); THEN M(R(N))R(P).1; M(R(N)+1 )-R(P).O;
R(N)+2-R(N)
R(N)-R(P); M(R(X)+1)
-R(N).1; M(R(X)+2)R(N).O; R(X)+2-R(X)
-Previous contents of T register are destroyed during Instruction Execution.
Notes for TABLE I
1.
Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch +2 execute).
Lon9-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the seond and
third byte, the branching address.
The long-branch instructions can:
d) Test for 0=0 or 0= 1
a) Branch unconditionally
e) Effect an unconditional no branch
b) Test for 0=0 or 0#0
c) Test for DF=O or DF=1
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-~nd
low-order bytes of the current program counter, respectively. This operation effects a branch to any memory location.
If the tested condition is not met, the branching address bytes are skipped over, and the·next instruction in sequence is
fetchM and executed. This operation is taken for the case of unconditional no branch (NLBR).
2. The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the
second specifies the branching address, except for the branches on interrupt. For those, the first two bytes specify the
condition to be tested and the third byte specifies the branching address.
The short bran~h instruction can:
e) Test tne status (lor 0) of the four EF flags
a) Branch unconditionally
f) Effect an unconditional no branch
b) Test for 0=0 or 0#0
g) Test for inter'upts
c) Test for DF=O or DF=1
d) Test for 0=0 or 0=1
If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte
position of the current program countp-r. This effects a branch within the current 256-byte page of the memory, i.e., the
page which holds the branching address. If the tested condition is not met, the branching address byte is skipped over,
and the next instruction in sequence is fetched and executed. This same action is taken in the case of unconditional no
branch (NBR).
3. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip overthe
byte following it. Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to
the unconditional no-branch instruction (NBR) except that the skipped-over byte is not considered part of the
program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
They can:
d) Test for 0=0 or 0=1
a) Skip unconditionally
e) Test for IE=1
b) Test for 0=0 or 0#0
c) Test for DF=O or DF=l
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus two
bytes are skipped over and the next instruction in sequence is fetched and executed. If the tested condition is not met,
then no action is taken. Execution is continued by fetching the next instruction in sequence.
4. Instructions 6800 through 6800, 683E, and 683F take 3 machine cycles; 68BN takes 4 machine cycles; 686N, 68AN,
and 68CN take 5 machine cycles; 688N takes 10 machine cycles; and 689N takes 8 machine cycles. In ali cases, the first
two cycles are fetches and subsequent cycles are executes. rhe first byte (68) of these two byte op codes is used to
generate the second fetch, the second byte is then interpreted differently than the same code without the 68 prefix.
DMA and INT requests are not serviced until the end of the last execute cycle, For the instructions noted in TABLE I
with ., previous contents of T register are destroyed during INSTRUCTION EXECUTION.
96
1800-Serles Microprocessors and Microcomputers
CDP180SC, CDP1806C
CLOCK
TPA--r--..,
'PLH"PHL I
TPB~~~;;.;j~~~.~~~~~~;;;;;;.;=t:::::::~::~_~~~
MEMORV
PLH PH
';g~E:~E
IGH ORDER
1
ADDRESS~~~~4~_OOR~~_B_V_T_E+--+JI\~_~__-~---~-~-~~-J~~~
MRO
(MEMORY
READ ~E)
4'
~"PLH
I
t.:r
'P
HL
I
(M~~~Ry---k,--~--rI-----4--'------~'PHL
I
WRITE CYCLE
--""""''"T-
~...."
I
*"M'E
(MEMORY
ENABLE)
I -..j' PLH
I 'Su IS ALLOWABLE
I INTERNAL RAM
1 ACCES.S TIME
'PHL r---+--i-:-----------+--+----'n
--~---+---"\--i__+',-----------r--,---~I
I
1 .
DATA "ROM
CPU TO
J
aus
*OATA FROM
R~~T~~~~~ __~---+--------+-~-~
(ME •
LOW)
• PLH.
'----------t------+-'
1
• PHL "' .
·STATECOOES
PLH'
PHL
INTERRUPT
SAMPLED (51,52)
INTERRUPT
REQUEST
I
I
I
. I
FLAG LINES
SAMPLED END OF SO
---L----+:--------------~-----_r---~
wm
1
1
~.~ts~u~I~~tH~rJ-------------~\~tS~u~l.t~H~lr-------1
\"..
7
I
\'
","
7
I
. NOTES:
1. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE.
2. ALL MEASUREMENTS ARE REFERENCED TO 50% POINT OF THE
WAVEFORMS.
3. SHADED AREAS INOICATED "DON'T CARE" DR UNOEFINED STATE;
MULTIPLE TRANSISTONS MAY OCCUR DURING THIS PERIOD.
*
FOR THE CDP1805C ONLY.
Fig. 13 - Objective (lynamic timing waveforms forCDPI805C and CDPI806C.
97
RCA CMOS LSI Products
CDP1805C, CDP1806C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=
-40 to +85°C. CL
=
50 pF. Voo
=
5 V ± 5%.
LIMITS
CDP1805C and CDP1806C UNITS
CHARACTERISTIC
Typ.-
Max.
Propagation Delay Times:
Clock to TPA. TPB
tpLH. tPHL
150
275
Clock-to-Memory High-Address Byte
tPLH. tPHL
200
325
Clock-to· Memory Low-Address Byte
tPLH. tPHL
150
250
Clock to MRD
tPLH. tPHL
200
325
Clock to MWR
tPLH. tPHL
150
275
Clock to (CPU DATA to BUS)
tPLH. tPHL
275
475
Clock to State Code
tPLH. tPHL
225
400
Clock to Q
tpLH. tPHL
200
350
Clock to N
tPLH. tPHL
250
425
Clock to Internal RAM Data to BUS
tpLH. tPHL
420
650
tsu
tH
-100
0
Data Bus Input Hold
125
225
DMA Set Up
ns
Minimum Set Up and Hold Times:Data Bus Input Set Up
tsu
-75
0
DMA Hold
tH
125
200
ME Set Up
tsu
-25
0
tH
90
150
ME Hold
tsu
-100
0
Interrupt Hold
tH
125
200
WAIT Set Up
tsu
20
50
tsu
-125
0
tH
125
225·
CLEAR Pulse Width
tWL
75
225
CLOCK Pulse Width
tWL
75
125
Interrupt Set Up
EF1-4 Set Up
EF1-4 Hold
ns
Minimum Pulse Width Times:-
--.-
ns
-Typical values are for T A = 25° C and nominal VDD.
-Maximum limits of minimum characteristics are the values above which all devices function.
TIMING SPECIFICATIONS as a function of T (T
=
1/fcLocK) at TA
=
-40 to +85°C. Voo
-Typical values are for TA = 25°C and nominal VOO.
98
5 V ± 5%.
LIMITS
CDP1805C and CDP1806C UNITS
Typ.Min.
CHARACTERISTIC
High-Order Memory-Address Byte
Set Up to TPA "'. Time
High-Order Memory-Address Byte
Hold after TPA Time
Low-Order Memory-Address Byte
Hold after WR Time
CPU Data to Bus Hold
after WR Time
Required Memory Access Time
Address to Data
=
TSU
tl-l
tH
tl-l
tACC
2T-150
2T-75
TI2-50
T/2-15
T+O
T+100
T-200
T-100
4.5T-250
4.5T-100
ns
1800-Serles Microprocessors and Microcomputers
CDP1805C, CDP1806C
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
STATE
I
N
MNEMONIC
HI:::)I
51
SO
INITIALIZE
NOT PROGRAMMER
ACCESSIBLE
FETCH
0
IDL
0
0
1
2
3
4
5
6
6
1~
LON
()"F
()"F
O-F
0
INC
DEC
SHORT
BRANCH
LOA
STR
IRX
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
RET
1
DIS
2
3
4
5
lDXA
STXD
ADC
SOB
SHRC
5MB
SAV
MARK
O-F
O-F
0
1
2
3
4
5
6
7
9
A
B
C
0
E
F
51
6
7
7
8
9
A
B
~
8
9
A
B
0
E
F
O-F
O-F
O-F
O-F
REO
SEO
ADC1
SDB1
SHlC
5MB1
GlO
GHI
PLO
PHI
OPERATION
0-1..1 •• N; 1-CIE XIE
X. P-TTHEN
O-X. P; 1-MIE. OOOO-RO
MRP-1. N; RP+1-RP
MRo-BUS
WAIT FOR DMA OR INT
--.M.BN-D
RN+1-RN
RN-1-RN
TAKEN: MRP-RP.O
NOT TAKEN: RP+1-RP
MRN-D' RN+1-RN
D-MRN
RX+1-RX
MRX-BUS; RX+1-RX
MRD
-MWR
1
1
1
1
Jt
RP
RO
0
0
1
1
'0
0
RN
RN
RN
RP
_0
1
1
0
~
~
MRN
0
MRX
RN
RN
RX
0
1
0
1
0
1
MRX
RX
0
1
DATA
BUS
00
OOA
MEMORY
ADDRESS
XXXX
XXXX
MRP
MRO
• MRN
FLOAT
FLOAT
MRP
1
1
1
N
LINES·
0
0
0
0
0
0
0
1
2
3
4
5
I
6
BUS-MRX.D
MRX-(X.P); RX+1-RX
1-MIE
MRX-(X.P); RX+1-RX
1-MIE
MRX-D; RX+1-RX
D-MRX; RX-1-RX
MRX+D+DF-DF 0
MRX-D-DFN-DF. 0
lSIHD~-DF' DF-MSBlDl
u-MRX-DFN-DF 0
T-MRX
(X.P)-T. MR2; P-X
R2-1-R2
0-0
1-0
MRP+D+DF-DF D' RP+1
MRP-D-DFN-DF 0; RP+"1
MSB~DL-DF;DF-lSB(D)
D-MRP-DFN-DF D' RP+1
RN.O-D
RN.1-D
O-RN.O
D-RN.1
RX
1
0
MRX
RX
0
1
7
1
2
3
4
5
6
7
0
MRX
RX
0
1
0
MRX
0
MRX
MRX
FLOAT
MRX
T
T
RX
RX
RX
RX
RX
RX
RX
R2
0
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
FLOAT
FLOAT
MRP
MRP
FLOAT
MRP
RN.O
RN.1
.0
0
RP
RP
RP
RP
RP
RP
RN
RN
RN
RN
1
1
0
1
1
1
1
1
1
1
1
1
1
DATA
FROM
1/0
DEVICE
0
1
0
1
1
1
1
--'l
0
--'l
0
0
0
0
0
0
0
0
0
0
0
0
0
A = Data Bus Floats for first 2-1/2 clocks of the 9 clock initialization cycle; all zeros for remainder of cycle.
99
RCA CMOS LSI Products
CDP1805C, CDP1806C
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Confd)
,
STATE
Sl#l
#2
,
N
I
0-3
8-B
51#1 , ..
#2
MNEMONIC
LONG
BRANCH
.
OPERATION
TAKEN: MRP-B; RP+1-RP
TAKEN:B-RP.1 ;MRP-RP.O
DATA
BUS
MRP
M(RP+1)
MEMORY
ADDRESS
RP
RP+1
NOT TAKEN RP+1-RP
NOT TAKEN: RP+1-RP
MRP
M(RP+1)
TAKEN: RP+1-RP
MAD DR
N
0
0
1
1
LINES
0
0
RP
RP+1
0
0
1
1
0
0
MRP
RP
0
1
0
TAKEN: RP+1-RP
M(RP+1)
RP+1
0
1
0
NOT TAKEN: NO
OPERATION
MRP
RP
0
1
0
NOT TAKEN: NO
OPERATION
NO OPERATION
MRP
RP
0
1
0
MRP
RP
0
1
0
RP
RN
RN
RX
0
0
0
1
1
1
1
RX
0
1
0
RX
1
1
0
RP
0
1
0
RP,
RO
1
1
1
0
0
0
RO
RN
0
1
1
0
0
C
,5
51#1
6
7
#2
C
D
E
F
51#1
I,.ONG
5KIP
#2
51#1
4
NOP
O-F
O-F
SEP
SEX
LDX
OR
AND
XOR
ADD
SD
SM
SHR
LDI
ORI
ANI
XRI
ADI
SDI
5MI
SHL
#2
D
E
0
51
F
1
2
3
4
5
7
6
8
9
A
B
C
D
F
E
DMA IN
S2
53
100
DMA OUT
INTERRUPT
NO OPERATION
MRP
N-P
NM
N-X
NN
MRX-D
MRX
MRXOR D-D
MRX AND D-D
MRX
MRX XOR D-D
MRX+D-DF. D
MRX-D-DF. D
D-MRX-DF' D
LSBIDI-DF' D-MSBIDI
FLOAT
MRP-D; RP+1--RP
MRP OR D-D; RP+1-RP
MRP AND D-D; RP+1-RP
MRP XOR D--D; RP+1-RP
MRP
MRP+D-DF. D; RP""-RP
MRP-D";DF. D: RP+1'-RP
D-MRP-DF D' RP+1-'RP
MSB(D)':DF: O-LSB(Oi
FLOAT
DATA FROM
BUS-MRO: RO+1-RO
110 DEVICE
MRO-BUS' RO+1-RO
MRO
X.P-T; O-MIE
FLOAT
1-P: 2-X
1
1
1
0
0
1800-Serles Microprocessors and Microcomputers
CDP1805C, CDP1806C
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Confd)
STATE
I
N
MNEMONIC
OPERATION'
DATA
BUS
MEMORY
ADDRESS
N
MRD
iiWA
LINES
RO
1
1
0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
1
1
1
1
1
1
1
1
1
1
1
1
1
RP
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS
"8S" PRECEDES ALL THE OP CODES. SO THERE IS A DOUBLE FETCH
0
Sl
3
Sl#l
#2
#3
Sl#l
#2
#3
#4
#5
#6
#7
#8
Sl#l
#2
#3
#2
Sl#l
#2
#3
STPC
1
2
3
4
5
6
7
8
9
'A
B
C
D
E
DTC
SPM2
SCM2
SPM1
SCM1
LDC
STM
GEC
ETQ
XIE
XID
CIE
CID
BCI
F
BXI
6
O-F
RLXA
8
O·F
SCAL
9
#4
#5
#6
Sl#l
#2
#3
51#1
0
O-F
O-F
RSXD
B
O-F
RNX
O-F
~
i
1
1
1
1
1
1
1
1
1
1
1
1
Jl
0
1
0
RP
0
1
0
RX
RX+1
RN
RN
RX
RX-1
RP
RN
RP
RP+1
RP
RN
RX
RP
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Jl
~
~
i
0
0
0
Jl
Jl
Q
Jl
I
0
0
0
0
1
1
1
Jl
_1
Jl
1
1
1
0
0
0
Q
0
SRET
A
C
STOP COUNTER CLOCK;
FLOAT
0- :-32 PRF~r.AI I=R
CNTR-1-CNTR
FLOAT
CNTR-1 ON EF2 AND TPA
FLOAT
CNTR-1 ON EF2 0 TO 1
FLOAT
CNTR-1 ON EF1 AND TPA
FLOAT
. CNTR-1 ON EF1 0 TO 1
FLOAT
D-CNTR;O-CI;STOP CNTR
D
CNTR-1 ON TPA+32
FLOAT
CNTR-D
CNTR
IF CNTR THRU 0: ~-Q
FLOAT
1-XIE
FLOAT
O-XIE
FLOAT
1-CIE
FLOAT
O-CIE
FLOAT
TAKEN: MRP-RP.O;O-CI
MRP
NOT TAKEN: RP+1-RP
TAKEN: MRP-RP.O
MRP
NOT TA~EN: RP+1-RP
MRX-B RX+1-RX
MRX
B-T; MRX-S; RX+1-RX
M(RX+1)
B T-RN.O .RN.1
FLOAT
RN.O RN.1-T B
FLOAT
T-MRX' RX-1-RX
RN.O
B-MRX RX-1-RX
RN.1
RP.O RP.1-T B
FLOAT
B T-RN.1 RN.O
FLOAT
MRN-B' RN+1-RN
MRP
B-T' MRN-B' RN+1-RN
MLRP+ll
B T -RP.O RP.1
FLOAT
RN.O RN.1-T B
FLOAT
R'X+1-RX
FLOAT
B, T-RP.1, RP.O
FLOAT
RLDI
MRX-B; RX+1-RX
B-T; MRX-B
B, T-RN.O, RN.1
RN.O RN.1-T B
T-MRX' RX-1-RX
B-MRX; RX-1-RX
RN.O, RN.1-T, B
M(RX+1)
M(RX+1)
FLOAT
FLOAT
RN.O
RN.1
FLOAT
RX+1
RX+2
RN
RN
RX
RX-1
RN
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
B. T-RX.1. RX.O
MRP-B; RP+1-RP
B-T; MRP-B; RP+1-RP
B, T-RN.O, RN.1; RP+1-RP
FLOAT
MRP
M(RP+1)
FLOAT
RX
RP
RP+1
RN
1
0
0
1
1
1
1
1
0
0
0
0
101
RCA CMOS LSI Products
CDP1805C, CDP1806C
Ins.ructlon Summary
N
0
0111213141
lOLl
5
1
BR I BO I BZ I BDF 1 B1
I B2
4·
5
6
7
6
I
7 I 8
LON
DEC
I B3 I B4 .1 SKP
I
A
I
B
I
C
I
0
I
ElF
J BNO
I BNZ I BNF I BN1 I BN2 I BN3 I BN4
STR
INP
IRX I
OUT
I * I
RET I DIS ILDXAISTXD I ADC I SOB ISHRC I 5MB I SAV IMARK I REO I SE~ I ADCI I SDBI ISHLC I 5MBI
GLO
9
GHI
A
PLO
B
PHI
LBR ILBO ILBZ ILBDFl NOP I LSNO ILSNZ ILSNFllSKP ILBNO ILBNZ ILBNF IlSIE ILSO I LSZ ILSDF
SEP
0
E
F
9
LOA
8
C
I
INC
2
3
I
SEX
LOX I OR lAND I XOR I ADD I SO
I SHR I SM
I
LDI
I
ORI
I ANI I
XRI
I
ADI
I
SOl
I SHl.1
SMI
'68' LINKED OPCODES (DOUBLE FETCH)
0 sTPcl DTC ISPM21sCM21sPM1 I SCM1 IlDC I STM I GEC I ETO I XIE I XID
3 • - I I I I I I I I I I I ·6
RLXA
8
SCAL
9
SRET
A
RSXD
B
RNX
C
RLDI
* '68' IS USED AS A LINKING OPCODE FOR THE DOUBLE FETCH INSTRUCTIONS.
102
I CIE I CID I - I I - I - I BCI I BXI
1800-Series Microprocessors and Microcomputers
Objective Data
CLOCK
40
39
YiiTt
ct'fiR
0
se I
seo
38
4
5
iiRo
BUS 1
BUS 6
BUS'
8US 4
10
BUS
BUS
BUS
BUS
12
13
14
15
3
2
I
0
*
N2
HI
NO
Vss
"
I.
17
18
19
20
37
3.
35
34
33
32
31
30
29
28
27
2.
25
24
23
22
21
TOP VIEW
FOA CDPI805AC
Voo FOR COPI806AC
Voo
1m
llIIAlII
15IIAl!UT
INTERRUPT
IIWI!
TPA
TPB
CDP1805AC, CDP1806AC
CMOS 8-Bit Microprocessor With
ON-CHIP RAM ~ and Timer/Counter
Performance Features:
MA7
MA.
MA5
MA4
MA3
MA2
MAl
MAO
m
m
m
EF3
*M'E:
92CS-3~OO4
TERMINAL ASSIGNMENT
• Instruction time of 3.2 p.s,
-40 to +85'C
• 123 instructions - upwards software
compatible with CDP1802,
CDP1805, CDP1806
• BCD arithmetic instructions
• Low-power IDLE mode
• Pin compatible with CDP1802,
CDP1805, CDP1806, except for
Vee terminal
The RCA-CDP180SAC and CDP1806AC are functional and
performance enhancements of the CDP1802, CDP180SC,
and CDP1806C LSI CMOS 8-bit register-oriented microprocessor series and are designed for use in generalpurpose applications.
The CDP180SAC hardware enhancements include a 64byte RAM array and a 8-bit presettable down counter. The
timer/counterwhich generates an internal interrupt request,
can be programmed for use in time-base, event-counting,
and pulse-duration measurement applications. The timer
Icounter underflow output can also be directed to the Q
output terminal. The CDP1806AC hardware enhancements
are identical to the CDP180SAC, except the CDP1806AC
contains no on-chip RAM.
The CDP180SAC and CDP1806AC are identical to the
CDP1804AC, except for the on-chip memory, and may be
used for CDP1804AC development purposes.
• 64K-byte memory address capability
• 64 bytes of on-chip RAMA
• 16 x 16 matrix of on-board registers
• On-chip crystal or RC
controlled oscillator
• 8-bit timerlcounter
.. CDP1805AC only
The CDP180SAC and CDP1806AC software enhancements
include 22 more instructions than the CDP1802 al'l1 10
more instructions than the CDP180SC and CDP1806C. The
32 new software instructions add subroutine call and return
capability, enhanced data transfer manipulation, timer
Icountercontrol, improved interrupt handling, Single-instruction loop counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP180SAC or CDP1806AC for other
COP1800-series microprocessors. Pinout is identical except
for the replacement of Vee with 'KifI: on the CDP180SAC and
the replacement of Vee with Voo on the CDP1806AC.
The COP180SAC and CDP1806AC have an operating voltage
range of 4 V to 6.S V and are supplied in a 40-lead hermetic
dual-in-line ceramic package (0 suffix) and in a 40-lead
dual-in-line plastic package (E suffix).
ADDRESS BUS
....-------.,
MAO - MA7
--
---I
,...---- - - - - - --
I
I
I
~ !;.
Y---,
r --MAOMA4
MAO - MA7
I
I
I
:
---.I MRO
MRO
I
1
COPI851
PIO
COP 1805Ae
COPI806 AC
8-BIT CPU
I
I
COPI833
COPI824
32 BYTE RAM
I
IK BYTE ROM
1
I
1-
I
I
---+t MWR
TPA
I
I
I
TPA
I
COPI806C
ONLY
---+jCs
I
I
I
L-l'-r--'~
BUSO - BUS7
BUSO - BUS4
I
I
' - - - - - - - - - - - ' ' ' ' ' ' ' - - - - - - - - - - - -J
'--_ _ _--:_ _-=--=-_:--_-:B_--:B:-'-:T-:D_A-:TA:-B_US_--:_ _ _ _ _ _ _ _ _ _ _ _
Fig. 1 - Typical CDP1805AC, CDP1806AC small microprocessor system.
I
I
I
-.J
92CM-34987
103
I
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOLTAGE RANGE. (Voo):
(Voltage referen(:ed to Vss Terminal) .................................................................................. -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................................................... ±10 rnA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60° C (PACKAGE TYPE E) ..................................•.•..........•..•...•..••. , ...........•...•.• 500 mW
ForT. = +60 +85°C (PACKAGE TYPE E) ................................................... Derate Linearly at 12 mWrC to 200 mW
For T. = -55 to +100° C (PACKAGE TYPE D) ............................................................................... 500 mW
For 1. = +100 to +125°C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForT. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 ....................................................•.............•......•.................•.•. -55 to +125°C
PACKAGE TYPE E ........ c ........................................................................................ -40 to +85°C
STORAGE TEMPERATURE RANGE (T... ) ............................................................................ -65 to +l50°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. .. ................................................... +265°C
RECOMMENDED OPERATING CONDITIONS at T A = ·40 to +85 0 C
For maximum reliability. nominal operating conditions should be selected so that operation is always within
.the following ranges:
CONDITION
LIMITS
CDP1805ACD, CDP1805ACE
CHARACTERISTIC
CDP1806ACD, CDP1806ACE
VO D
(V)
MIN.
UNITS
MAX.
Input Voltage Range
-
Vss
Minimum Instruction Time' (fcL=5 MHz)
5
3.2
-
ps
Maximum DMA Transfer Rate
5
-
0.625
Mbytes/s
5
DC
5
5
DC
2
DC Operating Voltage Range
Maximum Clock Input Frequency.
Load Capacitance (Cl) = 50 pF
m
6.5
VDo
V
MHz
Maximum External Counter/Timer
Clock Input Frequency to ffi.
4
tCLX
'Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch. Long Skip.
NOP. and "68" family instructions. which are more than two cycles.
104
.
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85 0 C, Voo ± 5%, Except as noted
LIMITS
CONDITIONS
CDP1805ACD, CDP1805ACE
CHARACTERISTIC
CDP1806ACD, CDP1806ACE
Quiescent Device Current
100
Output Low Drive (Sink) Current
IOL
IExceot XTALl
Vo
(V)
VIN
(V)
VDD
(V)
Min.
Typ."
Max.
-
O,S
S
-
50
200
0.4
O,S
S
1.6
4
-
0.4
S
S
0.2
0.4
4.6
O,S
S
-1.6
-4
IOH
4.6
0
S
-0.1
-0.2
-
Output Voltage Low-Level
VOL
-
O,S
5
-
0
0.1
Output Voltage High Level
VOH
V;L
-
0,5
5
4.9
S
0.S,4.S
-
5
VIH
0.5,4.5
-
-
5
3.5
-
XTAL Output
IOL
Output High Drive (Source) Current
IOH
(Exceot XTALI
XTAL
Input Low Voltage (SUS 0 -
SUS 7, ME)
Input High Voltage (BUS 0 - BUS 7, ME)
Schmitt Trigger Input Voltage
UNITS
pA
mA
I
1.S
V
(Except SUS 0 - BUS 7, ME)
Positive Trigger Threshold
Vp
Negative Trigger Threshold
VN
Hysteresis
VH
Input Leakage Current
3-State Output Leakage Current
Input Capacitance
Output Capacitance
0.5,4.5
2.2
2.9
3.6
0.9
1.9
2.8
0.3
0.9
1.6
0.5
S
-
±0.1
±5
lOUT
O,S
0,5
5
-
±0.2
±5
CIN
-
-
-
-
5
7.5
COUT
-
-
-
-
10
15
5
-
1.5
3
mW
V
pA
-
Idle "00" at M(OOOO} CL = 50 of
Minimum Data Retention Voltage
5
-
liN
Total Power Dissipation (f=5 MHz)
Data Retention Current
-
VOR
lOR
Voo = VOR
VOO = 2.4
-
2
2.4
-
25
100
pA
pF
"Typical values are for T. = 25° C and nominal Veo .
. OPERATING AND HANDLING CONSIDERATIONS
1.
2.
Handling
All inputs and outputs of RCA CMOS devices have a
networ-k for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6S2S "Guide to Setter Handling
and Operation of CMOS Integrated Circuits."
OperatIng
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absolute maximum
rating.
.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Vce nor less than
Vss. Input currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Vec or Vss, whichever is appropriate.
Output Short Circuits
Shorting. of outputs to Voo, Vee, or Vss may damage
CMOS devices by exceeding the maximum device
diSSipation.
105
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
':0
MEMORY ADORESS LINES 1/0 FLAGS
RfjQU~
,.-L---.
I
CONTROL
I
ME
FOR CDPI80SAC
VDD FOR CDPI806AC
I
COPI805AC
ONL~
I
I
;I-IS4-=-B-;TE"l• .J
II
'----'-i-X TAL
I_~~~.r--------
SCO}STATE
SCI
COOES
CONTROL AND
TIMING LOGIC
QLOGIC
~}SYSTEM
liWR
iiiiD
TIMING
BUSO
BUS I
BUS'2
NO} I/O
NI
COMMANDS
N2
BUS 3
BUS 4
BUSS
BUSS
BUS 7
92eN-34988
Fig. 2 - Block diagram for CDP1805AC and CDP1806AC.
TIMING WAVEFORMS FOR POSSIBLE OPERATING MODES
r
00
CLOCK
INTERNAL RAM ,READ CYCLE -r-'NTERNAL RAM WRITE CYCLE--j
~
ro
~ ~ ~ ~
TPB ________________
A:~~::
I HIGH 8YTE I
iiiiD----,~
ro
~ ~
~
~
ro
__________
I HIGH BYTE I
LOW BYTE
~ ~ ~ ~
ro
I
~rIL-
LOW BYTE
______~~
MWR
I
L..-r-
I
* ~NE --------'LLJr--------...,L-..j
\/ALiD DATA FROII I I E M O R Y A
92CM-34989
'NOTE
VE HAS A MINIMUM SETUP AND HOLD TIME WITH RESPECT TO THE
BEGINNING OF CLOCK 70 FOR A MEMORY READ OPERATION. RAM DATA
WILL APPEAR ON THE DATA BUS DURING THE TIME iii!'ISACTIVE. THE TIME
SHOWN CAN BE LONGER, IF FOR INSTANCE, A DMA OUT OPERATION IS
PERFORMED ON INTERNAL RAM DATA, TO ALLOW DATA ENOUGH TIME TO
BE LATCHED INTO AN EXTERNAL DEVICE. THE INTERNAL RAM IS
AUTOMATICALLY DESELECTED AT THE END OF CLOCK 71, INDEPENDENT
OF lIE.
* FOR COPIB05AC ONLY
Fig. 3 - Internal memory operation timing waveforms for CDP1805AC and CDP1806AC.
106
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
t
00
CLOCK
EXTERNAL MEMORY READ CYCLE -!-EXTERNAL MEMORY WRITE CYCLE
~
~ ~ ~ ~ ~ ro ~ ~
~ ~ ~ ~ ~ ro
1
TPB~;;;;;===;;;;~~;;;;~===;;;~~~~
I HIGH BYTE I
LOW BYTE
I HIGH BYTE I
LOW BYTE
A~DE:t~~
MRo----,~
____________
4_~
MWR------------------~I------------__,~
* (~~~------------------~:-----------------------I
~
DATA BUS
*
OATA LATCHED
I~ CPU
i
VALID DATA FROM CPU
FOR CDPI805AC ONLY
fa:
92CS-34990
Fig. 4 - External memory operation timing waveforms for CDPl805A C and CDPl806A C.
I
ENHANCED CDP180SAC and CDP1806AC OPERATION
1iifE, for maximum immunity from noise and slow signal
TIMING
Timing for the CDPl805AC and CDP1806AC is the same as
the CDPl802 microprocessor series, with the following
exceptions:
• 4.5 clock cycles are provided for memory access
instead of 5.
• a changes 1/2 clock cycle earlier during the SEa and
REa instructions. .
• Flag lines (Ul-EF4) are sampled at the end of the SO
cycle instead of at the beginning of the Sl cycle.
• Pause can only occur on the low-to-hgh transition of
either TPA or TPB, instead of any negative clock transition.
SPECIAL FEATURES
Schmitt triggers are provided on all control inputs, except
transitions. A Schmitttrigger in the oscillator section allows
operation with an RC or crystal.
The CDP1802-series LOAD mode is not retained. This
mode (WAIT, ~=O) is not allowed on the CDP1805AC
and CDP1806AC.
A low power mode is provided, which is initiated via the
IDLE instruction. In this mode all external signals, except
the oscillator, are stopped on the low-to-high transition of
TPB. All outputs remain in their previous states, fiiiRi5 is set
to a logic "1", and the data bus floats. The IDLE mode is
exited by a DMA or INT condition. The INT includes both
external interrupts and interrupts generated by the timer
Icounter. The only restrictions are that the Timer mode,
which uses the TPA + 32 clock source, and the underflow
condition at the Pulse Width Measurement modes are not
available to exit the IDLE mode.
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data BUI):
8-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microproces,sor,
and 1/0 devices.
NO 10 N2 (1/0) LInes:
Activated by an 110 instruction to signal the 1/0 control
logic of a data transfer between memory and 1/0 interfa~e.
These lines can be used to issue command codes or deVice
selection codes to the 1/0 devices. The N bits are low at all
times except when an 1/0 instruction is being executed.
During this time their state isthe same as the corresponding
bits in the N register. The direction of data flow is defined in
the 1/0 instruction by bit N3 (internally) and is indicated by
the level of the ~ signal:
MRD = VDD:
Data from 1/0 to CPU and Memory
MAD = Vss:
Data from Memory to 1/0
107
RCA CMOS LSI Product.
CDP1805AC, CDP1806AC
SIGNAL OESCRIPTIONS (CQnt'd)
EF1 to m(4 Flags):
fIJIIf (Read Level):
These inputs enable the 1/0 controllers to transfer status
information to the processor. The levels can be tested by
the conditional branch instructions. They can be used in
conjunction with the INTERRUPT request line to establish
interrupt priorities. The flag(s) are sa~ed at the end of
every SO cycle. One additional use for m and
is event
counting and pulse-width measurement in conjunction
with the Timer/Counter.
A low level on MR15 indicates a memory read cycle. It can be
used to control three-state outputs from the addressed
memory and to indicate the direction of data transfer during
an 110 instruction.
m
INTERRUPT, OMA-IN, O:'M:':'A':"--=O""U""'T (31/0 Requests)
These inputs are sampled by the CDP1805AC and CDP180SAC during TPB.
Interrupt Action: X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
set to 1; interrupt enable is reset to 0 (inhibit); and
instruction execution is resumed. The interrupt action
requires one machine cycle (S3).
OMA Action: Finish executing current instruction; R(O)
pOints to memory area for data transfer; data is loaded into
or read out of memory; and increment R(O).
Note: In the event of concurrent DMA and INTERRUPT
requests, DMA-IN has priority followed by DMA-OUT and
thEm INTERRUPT.
SCO, SC1, (2 State Code Line.):
Q:
Single bit output from the CPU which can be set or reset,
between the trailing edge of TPA and the leading edge ot
TPB, under program control. The Enable Toggle a command connects the a-line flip-flop to the output of the
counter, such that each time the counter decrements from
01 to its next value, the a Ilrie changes state. This command
is cleared by a LOAD COUNTER (LDC) instruction, a CPU
reset, ora BRANCH COUNTER INTERRUPT'(BCI) instruction with the counter interrupt flip-flop set.
CLOCK:
Input for externally generated single-phase clock. The
maximum clock frequencyis5 MHz at Voo= 5 V. The clock is
counted down internally to 8 clock pulses per machine
cycle.
ifiL:
Connection to be used with clock input terminal, for an
external crystal, if the on-chip olicillator is utilized.
WAiT, CLEAR (2 Control Lines):
These outputs indicate that the CPU is: 1) fetching an
instruction, or 2) executing an instruction, or 3) processing
a DMA request, or 4) acknowledging an interrupt request.
The lallels of state code are tabulated below. All states are
valid at TPA.
Provide four control modes as listed in the following truth
table:
CLEAR
State Type
State Code Lines
SC1
SO (Fetch)
S1 (Execute)
.S2 (DMA)
-S3 (I nterrupt)
H = Vee.
L
L
H
The AC time constant
should be greater
than the olcillator
stlrt~up
time
(typically 20 ms),
92C$·34991
I=ig. 9 - Aeset/run diagram.
Fig. 7 - RC network for oscillator.
PAUSE
Stops the internal CPU timing generator. freezing the state
of the processor, Pause can occur at two pOints in a·
machine cycle. onthe low-to-high transition of either TPA
or TPB.
The oscillator continues to run but subsequent clock
transitions are ignored. TPA and TPB remain at their
previous state (see Fig. 10).
If Pause is entered while in the event counter mode. the
appropriate Flag transitions will continue to decrement the
counter.
tvoo' sv AT 2S"C
TPA PAUSE TIMING
ENTER
PAUSE
RESUME
RUN
+
+
CLOCK
2
468
10
2
468
100
468
IK
FREOUENCY
2468
10K
2
468
2 468
lOOK
1M
TPA
(Hz)
92CS-34172
f--tsu
Fig. 8 - Nominal component values as 8 function
of frequency for the RC oscillator.
TPB PAUSE TIMING
CONTROL MODES
CLEAR
WAIT
MODE
L
L
H
L
H
L
NOT ALLOWED
RESET
PAUSE
H
H
RUN
The function of the modes are defined as follows:
RESET
. Registers I.N. a. counte·r prescaler. and Counter Interrupt
Latc;h are reset. XIEand CIE are set and O's (Vss) are placed
on the data bus. TPA and1:PB are suppressed while reset is
112
CLOCK
I
TPB
WAiT
I
I
I
\:-t
PHL
r--tsu
NOTE:
PAUSE (IN CLOCK WAVEFORM) WHILE REPRESENTED HERE AS ONE CLOCK
CYCLE IN OURATION, COULD BE INFINITELY LONG.
Fig. 10 - Pause mode timing waveforms.
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
ARCHITECTURE (Conl'd)
CONTROL MODES (Cont'd)
RUN
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the next
high-to-Iow clock transition, while if paused at TPB, it will
resume on the next low-to-high clock transition (see Fig. 9).
When initiated from the Reset operation, the first machine
cycle following Reset is always the initialization cycle. The
initialization cycle is then followed by a DMA (52) cycle or
fetch (SO) from location 0000 in memory.
SCHMITT TRIGGER INPUTS
All inputs except BUS O-BUS 7 and Me contain a Schmitt
Trigger circuit, which is especially useful on the
input as a power-up RESET (see Fig. 9) and the CLOCK
input (see Fig. 7).
crm
I
STATE TRANSITIONS
The CDP1805AC and CDP1806AC state transitions are
shown in Fig. 11. Each machine cycle requires the same
period of time, 8 clock pulses, except the initialization cycle
(INIT) which requires 9 clock pulses.
PIIiOFlITV: !m!CE so, S1
DMAIN
DifAout
iNT
Fig. 11 - State transition diagram.
113
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
INSTRUCTION SET
The CDP1805AC and CDP1806AC instruction summary is
given in Table I. Hexadecimal notation is used to refer to the
4-bit binary codes.
In all registers bits are numbered from the least significant
bit (LSB) to the most significant bit (MSB) starting with O.
R(W): Register designated by W, where
W=N or X, or P
R(W).O: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
Operation Notation
M (R(N»-D; R(N) + 1-R(N)
This notation means: The memory byte pOinted to by R(N)
is loaded into D, and R(N) is incremented by 1.
TABLE I - INSTRUCTION SUMMARY (For Notes, see also page 17)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
5
LDI
RLDI
F8
68CN-
2
2
2
2
5
LDN
LDA
LDX
LDXA
RLXA
ON
4N
FO
72
686~
2
2
5
STR
STXD
RSXD
5N
73
68AN-
2
2
5
INC
DEC
DBNZ
1N
2N
682N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
REGISTER N TO REGISTER X COPY
LOGIC OPERATIONS (Note 5)
OR
OR IMMEDIATE
2
2
2
2
2
4
IRX
GLO
PLO
GHI
PHI
RNX
60
8N
AN
9N
BN
68B~
2
2
OR
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
2
2
XOR
XRI
F3
FB
AND
AND IMMEDIATE
2
2
AND
ANI
F2
FA
SHIFT RIGHT
2
SHR
F6
SHIFT RIGHT WITH CARRY
RING SHIFT RIGHT
2
2
SHRC
RSHR
SHIFT LEFT
2
SHL
INSTRUCTION
MEMORY REFERENCE
LOAD IMMEDIATE
REGISTER LOAD IMMEDIATE
LOAD VIA N
LOAD ADVANCE
LOADVIAX
LOAD VIA X AND ADVANCE
REGISTER LOAD VIA X AND
ADVANCE
STORE VIA N
STORE VIA X AND DECREMENT
REGISTER STORE VIA X AND
DECREMENT
REGIStER OPERATIONS
INCREMENT REG N
DECREMENT REG N
DECREMENT REG N AND LONG
BRANCH IF NOT EQUAL 0
I
76 A
OPERATION
M(R(P»-D; R(P)+1-R(P)
M(R(P»-R(N).1; M(R(P»+1R(N).O; R(P)+2-R(P)
M(R(N»-D; FOR N NOT 0
M(R(N»-D; R(N)+l-R(N)
M(R(X»-D
M(R(X»-D; R(X)+1-R(X)
M(R(X) )-R(N).l; M(R(X)+l)R(N).O; R(X»+2-R(X)
D-M(RN»
D-M(R(X»; R(X)-1-R(X)
R(N).O-M(R(X»; R(N).lM(R(X}-1); R(Xl-2-RIX\
R(N)+1-R(N)
R(N)-l-R(N)
R(N)-1-R(N); IF R(N) NOT 0,
M(R(P»-R(P).1, M(R(P)+1)R(P).O, ELSE R(P)+2-R(P)
R(X)+l-R(X)
R(N).O-D
D-R(N).O
R(N).l-D
D-R(N).l
R(N)-R(X)
M(R(X» OR D-D
M(R(P» OR D-D;
R(P)+1-R(P)
M(R(X» XOR D-D
M(R(P» XOR D-D;
R(P)+l-R(P)
M(R(X» AND D-D
M(R(P» AND D-D;
R(P)+1-R(P)
SHIFT D RIGHT, LSB(D)-DF,
O-MSB(D)
SHIFT D RIGHT, LSB(D)-DF,
DF-MSB(D)
FE
-Previous contents of T register are destroyed during instruction execution.
AThis instruction is associated with more than one mnemonic. Each mnemonic is i'ndividually listed.
114
SHIFT D LEFT, MSB(D)-DF,
O-LSB(D)
1800-Series Microprocessors and Microcomputers
CDP180SAC, CDP1806AC
Table I - INSTRUCTION SUMMARY (Cont'd)
NO. OF
MACHINE
CYCLES
MNEMONIC
2
2
SHLC
RSHL
ARITHMETIC OPERATIONS (Note 5)
ADD
DECIMAL ADD
2
4
ADD IMMEDIATE
DECIMAL ADD IMMEDIATE
INSTRUCTION
LOGIC OPERATIONS (Note 5) (Cont'd)
SHIFT LEFT WITH CARRY
RING SHIFT LEFT
OP
CODE
OPERATION
7E·
SHIFT D LEFT, MSB(D)-DF,
DF-LSB(D)
ADD
DADD
F4
eilF4
2
4
ADI
DADI
FC
68FC
ADD WITH CARRY
DECIMAL ADD WITH CARRY
2
4
ADC
DADC
74
6874
ADD WITH CARRY, IMMEDIATE
2
ADCI
7C
DECIMAL ADD WITH CARRY,
IMMEDIATE
4
DACI
687C
SUBTRACT D
SUBTRACT 0 IMMEDIATE
2
2
SD
SOl
F5
FD
SUBTRACT D WITH BORROW
SUBTRACT D WITH
BORROW, IMMEDIATE
SUBTRACT MEMORY
DECIMAL SUBTRACT MEMORY
2
2
SDB
SDBI
75
70
2
4
SM
DSM
F7
68F7
SUBTRACT MEMORY IMMEDIATE
2
SMI
FF
DECIMAL SUBTRACT MEMORY,
IMMEDIATE
4
DSMI
68FF
2
4
5MB
DSMB
77
6877
2
5MBI
7F
4
DSBI
687F
M(R(X»+D-DF, D
M(R(X»+D-DF, D
DECIMAL ADJUST-DF, D
M(R(P»+D-DF, 0; R(P)+1-R(P)
M(R(P) )+D-DF,D
R(P)+1-R(P)
DECIMAL ADJUST-DF, D
M(R(X»+D+DF-DF, D
M(R(X»+D+DF-DF, D
DECIMAL ADJUST -DF, D
M(R(P»+D+DF-DF,D
R(P)+1-R(P)
M(R(P»+D+DF-DF, D
R(P)+1-R(P)
DECIMAL ADJUST -DF, D
M(R(X»-D-DF,D
M(R(P»-D-DF, D;
R(P)+1-R(P)
M(R(X»-D-(NOT DF)-DF, D
M(R(P»-D-(NOT DF)-DF, 0;
R(P)+1-R(P)
D-M(R(X»-DF, D
D-M(R(X»-DF,D
DECIMAL ADJUST-OF, D
D-M(R(P»-DF,D;
R(P)+1-R(P)
D-M(R(P»-DF,D
R(P)+1-R(P)
DECIMAL ADJUST-OF, 0
D-M(R(X»-(NOT DF)-DF, 0
D-M(R(X»-(NOT DF)-DF, 0
DECIMAL ADJUST-OF, 0
D-M(R(P»-(NOT DF)-DF, 0
R(P)+1-R(P)
D-M(R(P»-(NOT DF)-DF, 0
R(P)+1-R(P)
DECIMAL ADJUST-OF 0
BRANCH INSTRUCTIONS - SHORT BRANCH
SHORT BRANCH
2
NO SHORT BRANCH (SEE SKP)
2
SHORT BRANCH IF D = 0
2
BR
NBR
BZ
30
38·
32
SHORT BRANCH IF 0 NOT 0
BNZ
3A
SUBTRACT MEMORY WITH BORROW
DECIMAL SUBTRACT MEMORY
WITH BORROW
SUBTRACT MEMORY WITH
BORROW,IMMEDIATE
DECIMAL SUBTRACT MEMORY
WITH BORROW, IMMEDIATE
2
}
M(R(P»-R(P).O
R(P)+1-R(P)
IF Q= 0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF 0 NOT 0, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
·This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
115
I
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
Table I -
INSTRUCTION SUMMARY (Confd)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNEMONIC
SHORT BRANCH (Conl'd
BRANCH INSTRUCTIONS
SHORT BRANCH IF OF = 1
2
BOF
SHORT BRANCH IF pas OR ZERO
2
BPZ
SHORT BRAN"CH IF EaUAL OR
2
BGE
GREATER
SHORT BRANCH IF OF = 0
2
BNF
SHORT BRANCH IF MINUS
2
BM
SHORT"BRANCH IF LESS
2
BL
SHORT BRANCH IF a = 1
2
BO
1
1
OP
CODE
~
IF OF = 1. M(R(P))-I'I(P).O
ELSE R(P)+1-R(P)
3B6
IF 0 = o. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
31
SHORT BRANCH IF a = 0
2
BNa
39
SHORT BRANCH IF EF1 = 1
(EF1 = Vss)
SHORT BRANCH IF EF1 = 0
(EF1 = Voo)
SHORT BRANCH IF EF2 = 1
(EF2 = Vss)
2
B1
34
2
BN1
3C
2
B2
35
2
BN2
3D
2
B3
36
2
BN3
3E
2
B4
37
2
BN4
3F
3
BCI
683E-
3
BXI
683F
LONG BRANCH
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF 0 = 0
3
3
3
LBR
NLBR
LBZ
caa
LONG BRANCH IF 0 NOT 0
3
LBNZ
CA
LONG BRANCH IF OF = 1
3
LBOF
C3
LONG BRANCH IF OF = 0
3
LBNF
CB
LONG BRANCH IF a = 1
3
LBa
C1
LONG BRANCH IF a = 0
3
LBNa
C9
SHORr BRANCH IF EF2 = 0
(EF2 = Voo)
SHORT BRANCH IF EF3 = 1
EF3 = Vss)
SHORT BRANCH IF EF3 = 0
EF3 = Voo)
SHORT BRANCH IF EF4 = 1
EF4 = Vss)
SHORT BRANCH IF EF4 = 0
(EF4 = Voo)
SHORT BRANCH ON
COUNTER INTERRUPT
SHORT BRANCH ON
EXTERNAL INTERRUPT
BRANCH INSTRUCTIONS -
OPERATION
IF a = 1. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF a = o. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF1 = 1. M(R(PH-R(P).O
ELSE R(P)+1-R(P)
IF EF1 = O. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF2 = 1. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF2 = O. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF3 = 1. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF3 = O. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF4 =1. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF4 = O. M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF CI =1. M(R(P»-R(P).O; O-CI
ELSE R(P)+1-R(P)
IF XI = 1. M(R(P»-R(P).O
ELSE R(P)+1-RLP)
LONG BRANCH
CO
C2
M(R(P»-R(P).1. M(R(P)+1)-R(P).0
R(P)+2~R(P)
IF 0 = O. M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF 0 NOT O. M(R(P»-R(P).1
" M(R(P)+1)-R(P).0
ELSE R(P)+2-R(P)
IF OF = 1. M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF = O. M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF a = 1. M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF a = O. M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
6Thls Instruction Is associated with more than one mnemonic. "Each mnemonic Is Individually nsted.
"ETQ clssred by LOC. reset of CPU. or BCt"· (CI = 1).
el = Counter Interrupt. XI = External Interrupt.
116
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
Table I - INSTRUCTION SUMMARY (Cont'd)
NO. OF
INSTRUCTION
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF 0 =0
LONG SKIP IF 0 NOT 0
MACHINE
CYCLES
MNEMONIC
OP
CODE
2
3
3
SKP
LSKP
LSZ
38&
C8&
CE
3
LSNZ
C6
LONG SKIP IF OF
=1
3
LSDF
CF
LONG SKIP IF OF
=0
3
LSNF
C7
OPERATION
R(P)+l-R(P)
R(P)+--R(P)
IF 0 =0, R(P)+2-R(P)
ELSE CONTINUE
IF 0 NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF OF =1, R(P)+2-R(P)
ELSE CONTINUE
IF OF = 0, R(P)+2-R(P)
ELSE CONTINUE
IF a =1, R(P)+2-R(P)
ELSE CONTINUE
IF a =0, R(P)+2-R(P)
ELSE CONTINUE
IF IE =1, R(P)+2-R(P)
ELSE CONTINUE
LONG SKIP IF a
=1
3
LSO
CD
LONG SKIP IF a
=0
3
LSNO
C5
LONG SKIP IF IE
=1
3
LSIE
CC
IDLE
2
IDL
O()#
STOP ON TPB; WAIT FOR DMA OR
INTERRUPT; BUS FLOATS
NO OPERATION
iSETP
I
SETX
SETa
RESET a
PUSH X, P TO STACK
3
2
2
2
2
2
NOP
SEP
SEX
SEa
REO
MARK
C4
ON
EN
7B
7A
79
CONTINUE
N-P
N-X
1-0
0-0
(X, P)-T; (X, P)-M(R(2»
THEN P-X; R(2)-1-R(2)
LOAD COUNTER
3
LDC
6806"
GET COUNTER
STOP COUNTER
3
3
GEC
STPC
6808
6800
DECREMENT TIMER/COUNTER
SET TIMER MODE AND START
SET COUNTER MODE 1 AND START
SET COUNTER MODE 2 AND START
SET PULSE WIDTH MODE 1
AND START
SET PULSE. WIDTH MODE 2
AND START
ENABLE TOGGLE a
3
3
3
3
3
DTC
STM
SCMl
SCM2
SPMl
6801
6807
6805
6803
6804
3
SPM2
6802
3
ETa
6809"
I
CONTROL INSTRUCTIONS
TIMER/COUNTER INSTRUCTIONS
D-COUNTER; O-CI; (IF COUNTER
IS STOPPED)
COUNTER-D
STOP COUNTER CLOCK;
0--:-32 PRESCALER
COUNTER-l-COUNTER
TPA-:-32-COUNTER CLOCK
EF1-COUNTER CLOCK
EF2-COUNTER CLOCK
TPA.EF1-COUNTER CLOCK;
EF1 /
STOPS COUNT
TPA.EF2-COUNTER CLOCK;
EF2 /
STOPS COUNT
IF COUNTER =01 ' NEXT
:Q-O
COUNTER CLOCK /
&This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
#An IDLE instruction initiates an 51 cycle. All external signals, except the OSCillator, are stopped on the low-to-high transition of TPB. All
outputs remain in their previous states, MRD issetto a logic '1' and the data bus floats. The processor will continue to IDLE untilan I/O request
(INTERRUPT, DMA-IN, or DMA'()UT)is activated. When the request is acknowledged, the IDLE cycle is terminated and the 1/0 request is
serviced, and then normal operation is resumed. (To respond to an INTERRUPT during an IDLE, MIE must be enabled.)
"ETQ cleared by LDC, reset of CPU or BCI '(CI = 1).
CI = Counter Interrupt, XI = External Interrupt.
117
,RCA CMOS LSI Products
CDP180SAC, CDP1806AC
Table I - INSTRUCTION SUMMARY (Confd)
NO. OF
MACHINE
CYCLES
MNEMONIC
OP
CODE
EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT DISABLE
COUNTER INTERRUPT ENABLE
COUNTER INTERRUPT DISABLE
RETURN
3
3
3
3
2
XIE
XIO
CIE
CIO
RET
680A
680B
680C
6800
70
DISABLE
2
DIS
71
SAVE
SAVET, 0, OF
2
6
SAV
OSAV
78
687B-
OUTPUT 1
2
OUT 1
61
OUTPUT 2
2
OUT2
62
OUTPUT 3
2
OUT3
63
OUTPUT 4
2
OUT4
64
OUTPUT 5
2
OUT5
65
OUTPUT 6
2
OUT6
66
OUTPUT 7
2
OUT7
67
INPUT 1
2
INP 1
69
INPUT 2
2
INP2
6A
INPUT 3
2
INP3
6B
INPUT 4
2
INP4
6e
INPUT 5
2
INP5
60
2
INP6
6E
2
INP7
6F
STANDARD CAll
10
SCAl
688N1'
STANDARD RETURN
8
SRET
689N-
INSTRUCTION
OPERATION
INTERRUPT CONTROL
1-XIE
O-XIE
1-CIE
O-CIE
M(R(X»-X. P;
R(X)+l-R(X); 1-MIE
M(R(X)-X, P;
R(X)+l-R(X); O-MIE
T-M(R(X»
R(X)-l-R(X), T-M(R(X»,
R(X)-l-R(X), O-M (R(X»,
R(X)-l-R(X), SHIFT 0
RIGHT WITH CARRY, O-M(R(X»
INPUT-OUTPUT BYTE T~ANSFER
INPUT 6
INPUT 7
,
M(R(X»-BUS;
N LINES =1
M(R(Xj)-BUS;
N LINES =2
M(R(X»-BUS;
N LINES =3
M(R(X»-BUS;
N LINES =4
M(R(X»-BUS;
N LINES =5
M(R(X»-BUS;
N LINES =6
M(R(X»-BUS;
N LINES =7
BUS-M(R(X»;
N LINES =1
BUS-M(R(X»;
N LINES =2
BUS-M(R(X»;
N LINES =3
BUS-M(R(X»;
N LINES =4
BUS-M(R(X»;
N LINES =5
BUS-M(R(X»;
N LINES =6
BUS-M(R(X»;
N LINES =7
R(X)+l-R(X);
R(X)+l-R(X);
R(X)+l-R(X);
R(X)+l-R(X);
R(X)+l-R(X);
R(X)+l-R(X);
R(X)+l-R(X);
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
CAll AND RETURN
R(N).O-M(R(X»;
R(N).l-M(R(X)-l);
R(X)-2-R(X); R(P)-R(N);
THEN M(R(N»-R(P).l;
M(R(N)+l )-R(P).O;
R(N)+2-R(N)
R(N)-R(P); M(R(X)+l )-R(N).l;
M(R(X)+2)-R(N).0;
R(X)+2-R(X)
·Previous contents of T register are destroyed during instruction execution.,
118
..
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
NOTES FOR TABLE I
1. Long-Branch, Long-Skip and No Op instructions
require three cycles to complete (1 fetch + 2 execute).
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
The long-branch instructions can:
a. Branch unconditionally
b. Test for 0=0 or D¢O
c. Test for DF=O or DF=1
d. Test for 0=0 or 0=1
e. Effect an unconditiona'l no branch
If the tested condition is met, then branching takes
place; the branching address bytes are loaded in the
high-and-Iow-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
If the tested condition is not met, the branching address
bytes are skipped over, and the next instruction in
sequence is fetched and executed. This operation is
taken for the case of unconditional no branch (NLBR).
2. The short-branch instructions are two or three bytes
long. The first byte specifies the condition to be tested,
and the second specifies the branching address, except
for the branches on interrupt. For those, the first two
bytes specify the condition to be tested and the third
byte specifies the branching address.
The short branch instruction can:
• a. Branch unconditionally
. b. Test for 0=0 or D¢O
• c. Test for DF=O or DF=1
d. Test for 0=0 or 0=1
e. Test the status (1 or 0) of the four EF flags
f. Effec.t an unconditional no branch
g. Test for counter or external interrupts (BCI, BXI)
If the tested condition is met, then branching takes
place; the branching address byte is loaded into the
low-order byte position of the current program counter.
This effects a branch within the current 2S6-byte page
of the memory, i.e., the page which holds the branching
address. If the tested condition is not met, the branching
address byte is skipped over, and the next instruction in
sequence is fetched and executed. This same action is
taken in the case of unconditional no branch (NBR).
3. The skip instructions are one byte long. There is one
Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Skip instruction takes 2 cycles
to complete (1 fetch + 1 execute). Its action is to skip
over the byte following it. Then the next instruction in
sequence is fetched and executed. This SKP instruction
is identical to the unconditional no-branch instruction
(NBR) except that the skipped-over byte is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
They can:
a. Skip unconditionally
b. Test for 0=0 or D¢O
c. Test for DF=O or DF=1
d. Test for 0=0 or 0=1
e. Test for MIE=1
If the tested condition Is met, then Long Skip takes
place; the current program c6unter is incremented
twice. Thus two bytes are skipped over and the next
instruction in sequence is fetched and executed. If the
tested condition is not met, then no action is taken.
Execution is continued by fetching the next instruction
in sequence.
4. Instruction 6800 through 68FF take a minimum of 3
machine cycles and up to a maximum of 10 machine
cycles. I n all cases, the first two cycles are fetches and
subsequent cycles are executes. The first byte (68) of
these tWO-byte op codes is used to generate the second
fetch, the second byte is then interpreted differently
than the same code withoutthe68 prefix. DMA and INT
requests are not serviced until the end of the last
execute cycle.
5. Arithmetic Operations:
The arithmetic and shift operations are the only
instructions that can alter the content cf OF. The syntax
'(NOT OF), denotes the subtraction of the borrow.
Binary Operations:
After an ADD instruction DF=1 denotes a carry has occurred. Result is
greater than FF'6 .
DF=O denotes a carry has not occurred.
After a SUBTRACT instruction DF=1 denotes no borrow. 0 is a true positive
number.
DF=O denotes a borrow. 0 is in two's complement
form.
Binary Coded Decimal Operations:
After a BCD ADD instruction DF=1 denotes a carry has occurred. Result is
greater than 99,0.
DF=O denotes a carry has not occurred.
After a BCD SUBTRACT instruction DF=1 denotes no borrow. 0 is a true positive
decimal number.
99
0
(Example)
-88
M(R(X))
11
0
DF=1
DF=O denotes a borrow. 0 is in ten's complement
form.
(Example)
88
o
-99
M(R(X))
o
DF=O
89
89 is the ten's complement of 11, which is the
correct answer (with a minus value denoted by
DF=O).
119
I
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
CLOCK
TPA--:---TPB_-r_ _~~~~~~~~~~tp~L~H~.t~PH~L~I______~~~
~JD~~~~~~~~4~~~_ _~~J,~~'A~Lg~~~E~~~D~~~R~E~'-------~--L---~~J~~~
.~'tPLH
'~tPLH
MRii
( MEMORY
READ ~LE)
--.,---------r'-------I--r-'--4....;..,--'
' - - -......
(M~~~RY--'-'-----.---..,....--------I---.-------i\j tpHL
,
~I..
• .:.:.:;:....~...;.__..J
WRITE CYCLE)
*ME
(MEMORY
ENABLE)
, --l t PLH
I
ACCESS TI ME
tpHL'r---~--+I-----------------~~----_+~
,
DATA FROM
CPU TOBUS
I tsu lS ALLOWAB L E
I INTERNAL RAM
-..4-----r-----{
I
~-_r--~I~------------~r-_r--~~
I tpLH
1 - l tPHL
i---------i----1I--r-~
R~~T~~~U~-~----~-------4-~I---{
*DATA FROM
(ME • LOW)
~---------+-.....::...---..,.J
t PLH,
t PHL
STATE CODES
Q
,
,
PLH'
NO,NI,N2'
,
(:1:/0
/..-t PLH
EXECUTION
I
CYCLEI
...
~
PHL
.
DATA LATCHED,
IN
~"777J7J7/'J/77//
DATA FROM
BUS TO CPU
,
CPU~~tsu
/'/////////////////////////
_ _ tH
'~.S2.S3)
DMA
•
~
.
REQUEST
~ATJ:~~6iSI,S2)
:
I
I
INTERRUPT
REQUEST
,
nMU~
SAMPLED END OF SO
I
ffi-U4 --+,---4:--------------------+---~
,
I
~ tsul
WAiT
;
tH
Ir-----~------------~\~ts~u~'~t~H~/------
\I-~-oo""'to--<>/7
\
°1-
7
I
92CL- 34992
NOTES:
1. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE.
2. ALL MEASUREMENTS ARE REFERENCED TO 50% POINT OF THE
WAVEFORMS.
3. SHADED AREAS INDICATED "DON'T CARE" OR UNDEFINED STATE.
MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD.
*
FOR THE CDPI605AC ONLY
Fig. 12 - Obiective dynamic timing waveforms for CDP1805AC and CDPI806AC.
120
1800-S.rles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
DYNAMIC ELECTRICAL CHARACTERISTICS at y"
=-40 to +8S
O
C, CL
=50 pF, VDD =5 V, ±5%.
LIMITS
CHARACTERISTIC
CDP1805AC, CDP1806AC
Typ."
UNITS
Max.
Propagation Delay Times:
Clock to TPA. TPB
tPLH. tPHL
150
275
Clock-tO-:Memory High-Address Byte
tPLH. tPHL
325
550
Ciock-to-Memory Low-Address Byte
tPLH. tPHL
275
450
Clock to MRD
!PLH. tPHL
200
325
mvJ!f
tPLH. tPHL
150
275
Clock to (CPU DATA to BUS)
!PLH. tPHL
375
625
Clock to State Code
tPLH. tPHL
225
400
a
tPLH. tPHL
250
425
Clock to N
tPLH. tPHL
.250
425
Clock to Internal RAM Data to BUS
tPLH. tPHL
420
650
tsu
-100
0
tH
125
225
Clock to
Clock to
ns
I
Minimum Set Up and Hold Times:Data Bus Input Set-Up
Data Bus Input Hold
tsu
-75
0
DMAHold
tH
100
175
ME Set-Up
ME Hold
tsu
-25
0
lH
90
150
Interrupt Set~Up
tsu
-100
0
Interrupt Hold
tH
100
175
WAIT Set-Up
tsu
20
50
EFl-4 Set-Up
tsu
. -125
tH
175
300
~ Pulse Width'
tWL
100
175
CLOCK Pulse Width
tWL
75
125
DMASet-UD
"E"FT=4 Hold
ns
0
Minimum Pulse Width Times:ns
"Typical values are for TA = 25° C and nominal VDD.
-Maximum limits of minimum characteristics are the values above which all devices function.
TIMING SPECIFICATIONS a. a function of T (T = 1IfCLOCK) at T" = -40 to +85 0 C, VDD = 5 V, ±5%.
LIMITS
CDP1805AC, CDP1806AC
CHARACTERISTIC
'High-Order Memory-Address Byte
Set-Up to TPA
....
Time
Tsu
. High-Order Memory-Address Byte
Hold after TPA Time
tH
Low-Order Memory-Address Byte
Hold after WR Time
lH
CPU Data to Bus Hold
after WR Time
tH
Required Memory Access Time
Address to Data
lAce
Min.
Typ."
2T-275
2T-175
T/2-50
T/2-15
T+O
T+1.00
T-200
T-l00
4.5T-400
4.5T-175
UNITS
ns
"Typical values are for TA = 25° C and nominal VDD.
121
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
STATE
I
N
MNEMONIC
RESET
Sl
INITIALIZE
NOT PROGRAMMER
DATA
BUS
MEMORY
ADDRESS
00
UNDEFINED
1
1
0
00·
UNDEFINED
1
1
0
MRP-1, N; RP+1-RP
STOPATTPB
WAIT FOR DMA OR INT
MRN-D
RN+1-RN
RN-1-RN
TAKEN: MRP-RP.O
NOT TAKEN: RP+1-RP
MRN-D' RN+1-RN
D-MRN
RX+1-RX
MRP
FLOAT
RP
RO
0
1
1
1
0
0
MRN
FLOAT
FLOAT
MRP
RN
RN
RN
RP
0
1
1
0
1
1
1
1
0
0
MRN
0
MRX
RN
RN
RX
0
1
1
1
0
1
MRX-BUS; RX+1-RX
MRX
RX
0
1
OPERATION
o-a,I,N, COUNTER
PRESCALER, CIL;
1-CIE XIE
X, P-TTHEN
O-X, P; 1-MIE, OOOO-RO
MAD MWR
N
LINES
AC:C:E~~IBLE
SO
0
0
0
1
2
3
1-F
O-F
O-F
O-F
4
5
6
O-F
O-F
0
1
2
3
4
5
6
7
6
Sl
7
8
9
A
B
FETCH
IDL
A
B
C
0
E
F
0
LON
INC
DEC
SHORT
BRANCH
LOA
STR
IRX
OUT 1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
INP 1
INP2
INP3
INP4
INP5
INP6
INP 7
RET
1
DIS
2
3
4
5
6
7
8
9
LDXA
STXD
ADC
SOB
SHRC
5MB
SAV
MARK
A
B
C
0
E
F
O-F
O-F
O-F
O-F
REO
SEa
ADC1
SDB1
SHLC
5MB1
GLO
GHI
PLO
PHI
9
0
0
"~
0
1
2
3
4
5
6
~
BUS-MRX,D
MRX-X,P; RX+1-RX
1-MIE
MRX-X,P; RX+1-RX
O-MIE
MRX-D; RX+1-RX
D-MRX' RX-1-RX
MRX+D+DF-DF, 0
MRX-D-DFN-DF, 0
LSB(D)-DF; DF-MSBJDl
D-MRX-DFN-DF, 0
T-MRX
X,P-T, MR2; P-X
R2-1-R2
0-0
1-0
MRP+D+DF-DF, 0; RP+1
MRP-D-DFN-DF, 0; RP+1
MSB(D)-DF; DF-LSB(D)
D-MRP-DFN-DF, 0; RP+1
RN.O-D
RN.1-D
D-RN.O
D-RN.1
. .. .
RX
1
0
MRX
RX
0
1
1
2
3
4
5
6
7
0
MRX
RX
0
1
0
MRX
0
MRX
MRX
FLOAT
MRX
T
T
RX
RX
RX
RX
RX
RX
RX
R2
0
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
FLOAT
FLOAT
MRP
MRP
FLOAT
MRP
RN.O
RN.1
0
0
RP
RP
RP
RP
RP
RP
RN
RN
RN
RN
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
DATA
FROM
I/O
DEVICE
• = Data bus floats for first 2-1/2 clocks of the 9 clock Inillalization cycle; all zeros for remainder of cycle .
122
0
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Conl'd)
STATE
51#1
#2
51#1
#2
Sl#l
#2
I
C
N
MNEMONIC
0-3,
8-B
LONG
BRANCH
5
6
7
C
0
E
F
Sl#l
#2
Sl#l
#2
0
E
Sl
LONG
SKIP
F
4
NOP
O-F
O-F
0
1
2
3
4
SEP
SEX
LOX
OR
AND
XOR
ADD
SO
SM
SHR
LDI
ORI
ANI
XRI
AOI
SDI
SMI
SHL
5
7
6
8
9
A
B
C
D
F
E
OMAIN
52
53
DMAOUT
INTERRUPT
OPERATION
TAKEN: MRP-B; RP+1-RP
TAKEN:B-RP.1·MRP-RP.O
NOT TAKEN RP+1-RP
NOT TAKEN: RP+1-RP
TAKEN: RP+1-RP
TAKEN: RP+1-RP
DATA
BUS
MRP
MIRP+1)
MAP
MIRP+1)
MRP
M(RP+1)
MAP
NOT TAKEN: NO
OPERATION
·M(RP+1)
NOT TAKEN: NO
OPERATION
MRP
NO OPERATION
M(RP+1)
NO OPERATION
NN
N-P
N-X
NN
MRX
MRX-O
MRX OR 0-0
MRXANO 0-0
MAX
MRXXOR 0-0
MRX+O-OF,O
MRX-O-OF, D
D-MRX-DF' 0
FLOAT
LSB{O)-OF; O-MSB{D)
MRP-D; RP+1-RP
MRP OR O-D; RP+1-RP
MRP AND 0-0; RP+1-RP
MRP
MRP XOR 0-0; RP+1-RP
MRP+D-OF, D; RP+1-RP
MRP-D-DF, D; RP+1-RP
D-MRP-DF, D; RP+1-RP
FLOAT
MSB(O)-DF; O-LSB{D)
DATA FROM
BUS-MRO; RO+1-RO
1/0 DEVICE
MRO
MRO-BUS; RO+1-RO
FLOAT
X,P-T; O-MIE
1-P; 2-X
MEMORY
ADDRESS
AP
RP+1
RP
AP+1
RP
AP+1
N
MAD
LINES
0
0
0
0
0
0
MWA
1
1
1
1
1
1
RP
0
1
0
RP+1
0
1
0
AP
RP+1
RN
RN
RX
0
0
0
1
1
1
1
1
0
0
0
0
0
RX
0
1
0
RX
1
1
0
RP
0
1
0
RP
RO
1
1
1
0
0
RO
AN
0
1
1
1
0
0
1
1
0
0
0
0
0
0
I
0
123
RCA CMOS LSI Products
CDP180SAC, CDP18Q~A~ .
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Conl'd)
STATE
I
N
MNEMONIC
OPERATION
DATA
BUS
MEMORY
ADDRESS
N
MRD
iiWR
LINES
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS
"6S" PRECEDES ALL THE OP CODES, SO THERE IS A DOUBLE FETCH
S1
Sl#l
#2
#3
0
2
0
STPC
1
2
3
4
5
6
DTC
SPM2
SCM2
SPM1
SCM1
LDC
7
8
9
A
B
C
D
STM
GEC
ETa
XIE
XID
CIE
CID
O-F
DBNZ
BCI
E
Sl
Sl#1
#2
#3
Sl#1
#2
S1#1
#2
#3
#4
Sl#1
#2
Sl#l
3
6
7
7
F
BXI
O-F
RLXA
4
6
DADC
DSAV
7
7
DSMB
7
C
DACI
#2
Sl#l
7
#2
S1#1
#2
#3
#4
#5
#6
#7
#8
124
8
F
O-F
DSBI
SCAL
STOP COUNTER CLOCK;
0-+32 PRESCALER
CNTR-1..,..CNTR
CNTR-1 ON EF2 AND TPA
CNTR-1 ON EF2 0 TO 1
CNTR-1 ON EF1 AND TPA
CNTR-1 ON EF1 0 TO 1
D-CNTR;O-CIL
(IF CNTR IS STOPPED)
CNTR-1 ON TPA+32
CNTR-D
IF CNTR THRU 0: a-a
1-XIE
O-XIE
1-CIE
O-CIE
RN-1-RN
MRP-B; RP+1-RP
TAKEN: B-RP.1; MRPRP.O NOT TAKEN:
RP+1-RP
TAKEN: MRP-RP.O;
O-CI
NOT TAKEN: RP+1-RP
TAKEN: MRP-RP.O
!\JOT TAKEN: RP+1-RP
MRX-B, RX+1-RX
B-T; MRX-B; RX+1-RX
B T-RN.O RN.1
MRX+D+DF-DF D
DECIMAL ADJUST-DF D
RX-1-RX
T-MRX; RX-1-RX
D-MRX; RX-1-RX
SHIFT D RIGHT WITH
CARRY
D-MRX
D-MRX-INOT DF1-DF D
DECIMAL ADJUST -DF, D
MRP+D+DF-DF, D;
RP+1-RP
DECIMAL ADJUST-DF, D
D-MRP-(NOT DF)-DF, D;
RP+1-RP
DECIMAL ADJUST -DF, D
RN.O, RN.1-T, B
T-MRX; RX-1-RX
B-MRX RX-1-RX
RP.O RP.1-T B
B, T -RN.1, RN.O
MRN-B; RN+1-RN
B-T; MRN-B; RN+1-RN
B. T-RP.O, RP.1
FLOAT
RO
1
1
0
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
D
R1
R2
R3
R4
R5
R6
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
FLOAT
CNTR
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
MRP
M(RP+1)
R7
R8
R9
RA
RB
RC
RD
RN
RP
RP+1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
MRP
RP
0
1
0
MRP
RP
0
1
0
MRX
M(RX+1)
FLOAT
MRX
FLOAT
FLOAT
T
D
RX
RX+1
RN
RX
RP
RX
RX-1
RX-2
0
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
D
MRX
FLOAT
RX-3
RX
RP
1
0
1
0
1
1
JL
MRP
RP
0
1
0
FLOAT
RP+1
1
1
0
MRP
RP
0
1
0
FLOAT
FLOAT
RN.O
RN.1
FLOAT
FLOAT
MRP
fI.1(RP+11
FLOAT
RP+1
RN
RX
RX-1
RP
RN
RP
RP+1
RP
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1800-Serles Microprocessors and Microcomputers
CDP1805AC, CDP1806AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Conl'd)
STATE
I
N
MNEMONIC
OPERATION
DATA
BUS
MEMORY
ADDRESS
--MRD
MWR
N
LINES
THE FOLLOWiNG ARE ALL LINKED INSTRUCTIONS
"68" PRECEDES ALL THE OP CODES, SO THERE IS A DOUBLE FETCH
51#1
#2
#3
9
#4
#5
#6
S1#1
#2
#3
S1#1
#2
S1#1
#2
#3
S1#1
#2
S1#1
#2
51#1
O-F
O-F
RSXO
B
O-F
RNX
C
O-F
RLOI
F
4
DADO
F
7
OSM
C
OAOI
#2
S1#1
F
#2
F
FLOAT
FLOAT
FLOAT
RN
RX
RP
1
1
1
1
1
1
0
MRX-B; RX+1-RX
B-T; MRX-B
B, T-RN.O, RN.1
RN.O, RN.1-T, B
T-MRX' RX-1-RX
B-MRX; RX-1-RX
RN.O, RN.1-T, B
B, T -RX.1 RX.O
MRP-B' RP+1-RP
B-T' MRP-B' RP+1-RP
B, T-RN.O, RN.1; RP+1-RP
MRX+O-OF 0
DECIMAL ADJUST-OF, 0
O-MRX-OF,O
DECIMAL ADJUST -OF, 0
MRP+O-OF, 0;
B.P+1-RP
DECIMAL ADJUST-OF, 0
O-MRP-OF,O
RP+1-RP
DECIMAL A~JUST-OF. 0
M(RX+1)
M(RX+1)
FLOAT
FLOAT
RN.O
RN.1
FLOAT
FLOAT
MRP
MIRP+11
FLOAT
MRX
FLOAT
MRX
FLOAT
RX+1
RX+2
RN
RN
RX
RX-1
RN
RX
RP
RP+1
RN
_IlX
RP
RX
RP
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
_0
0
0
Jl.
0
0
0
1
0
1
1
1
1
1
0
0
0
MRP
RP
0
1
0
FLOAT
RP+1
1
1
0
MRP
RP
0
1
0
FLOAT
RP+1
1
1
0
0
0
SRET
A
F
RN.O RN.1-T B
RX+1-RX
B, T-RP.1, RP.O
OSMI
1
1
1
1
1
1
0
0
0
0
0
•
125
1800-Series Microprocessors and Microcomputers
RCA CMOS LSI Products
CDP1805AC, CDP1806AC
Instruction Summary
N
0
01
lOLl
1
I
2
I
3
I
4
I
5
I
6
I
7 I
LON
1
I
B2
I B3 I
B4
A
I
B ···1
C
I
DIE
I
F
I SKP I BNO I BNZ I BNF I BN1 I BN2 I BN3 I BN4
STR
OUT
IRX I
INP
I
* I
RET I DIS ILDXAlsTXDI ADC I SDB ISHRCI 5MB I SAY IMARKI REO I SE~ I ADCII SDBllsHLCI 5MBI
8
GLO
9
GHI
A
PLO
B
PHI
LBR ILBO ILBZ ILBDF I NOP I LSNO I LSNZ I LSNF I LSKP ILBNO ILBNZ ILBNF I LSIE I LSO I LSZ I LSDF
D
SEP
E
F
I
LOA
5
C
9
DEC
BR I BO I BZ I BDF I B1
4
6
7
I
INC
2
3
8
SEX
LOX I OR I AND LXOR I ADD I
SD
I SHR I SM
I LDI
I ORI I ANI
I
XRI
J
ADI I SOl I SHL
I
SMI
'68' LINKED OPCODES (DOUBLE FETCH)
0
STPCI DTC ISPM21SCM21 SPM1 I SCM1 I LDC I STM I GEC I ETO I XIE I XID I CIE I CID I - 1 -
2
DBNZ
3
-
6
7
- I -
I -
I":" I -
I
I
-
I
I -
IDADCI
-
RLXA
I DSAV I DSMB I
I -
-
-
8
-
I
-
I
-
I
-
I
-
-
I
-
I
-
1 -
-
I
-
1 - I -
I
-
I BCI I BXI
IDACII
-
I -
I
-
I DSBI
SCAL
9
SRET
A
RSXD
B
RNX
C
RLDI
F
*
I
-
I -I -
I -
IDADDI
-
I -
I DSM
1
I DADI
1 -
I - J DSMI
'68' IS USED AS A LINKING OPCODE FOR THE DOUBLE FETCH INSTRUCTIONS.
IMPORTANT NOTICE
Early versions of the CDP1805AC and CDP1806AC (with NLBJ5, NLBT5, or NR appearing in the bottom brand) fully
execute all CDP1802 family. CDP1805C. and CDP1806C instructions, plus the additional eight BCD arithmetic
instructions and the new DBNZ instruction described in the CDP1805AC. CDP1806AC data sheet. They do not, however,
execute the new DSAV instruction.
126
1800-Series Memories
Technical Data
II
127
RCA CMOS LSI Products
CDP1821, CDP1821C
1024-Word X 1-Bit Static
Random-Access Memory
~
"AO
"AI
"A2
"A3
"U
00
Vss
I·
2
3
4
I.
15
5
14
13
12
I
1
"
10
9
TOP VIEW
•
Features:
Voo
01
RO/WR
• No precharge or external clocks
required
• Separate data inputs and outputs
• Fast access time:
250 ns at Voo = 5 V
125 ns at Voo = 10 V
"At
"A8
"A1
"U
"A5
Terminal Assignment
The RCA-CDP1821 and CDP1821 Care
1024-word x 1-bit CMOS silicon-on-sapphire (SOS), fully static, random-access
memories for use in general-purpose microprocessor systems.
The output state of the CDP1821 and
CDP1821 C is a function of the input address
and chip-select states only. Valid data will
appear at the output in one access time
following the latest address change to a
selected chip. After valid data appears, the
address may then be changed immediately.
It is not necessary to clock the chip-select
input or any other input terminal for fully
static operation; therefore, the chip-select
input may be used as an additional address
input. When the device is in an unselected
state (CS,.1), the internal write circuitry and
output sense amplifier are disabled. This feature allows the three-state data outputs from
many arrays to be OR-tied to a common bus
for ease of memory expansion.
The CDP1821 and CDP1821C are functionally identical. They differ in that the CDP1821
has a recommended operating voltage range
of 4-10.5 volts, and the CDP1821C, a
recommended operating voltage range of
4-6.5 volts.
The CDP1821 and CDP1821C types are supplied in a 16-lead hermetic dual-in-line sidebrazed ceramic package (D Suffix) and in a
16-lead dual-in-line plastic package (E Suffix).
OPERATIONAL MODES
INPUTS
SE~CT
Standby
X
1
Write
0
0
High Impedance
Read
1
0
Contents of
Addressed Cell
MODE
X = DON'T CARE
128
CHIP-
OUTPUT
DATA
OUTPUT
DO
READI
WR!!.E
R/W
CS
High Impedance
LOGIC 1 s;< HIGH
LOGIC 0:2 LOW
1800-5erles Memories
CDP1821, CDP1821C
OPERA TlNG CONDITIONS at T A = Full Package Temperature Range
For maximum reliability, nominal operating conditions should be selected so that
operation is alwavs within the following ranges
LIMITS
CDP1821
CDP1821C
Min.
Max.
Max.
Min.
CHARACTER ISTIC
DC Operating Voltage Range
Input Voltage Range
4
10.5
4
6.5
VSS
VOO
VSS
VOO
UNITS
V
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (Vee):
(All voltage values referenced to V•• terminal)
CDP1821 ..................................................................... -0.5 to + 11 V
CDP1821C ..................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................... -0.5 to Veo +O.S V
DC INPUT CURRENT, ANY ONE INPUT ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................... SOO mW
For T. = +60 to +8SoC (PACKAGE TYPE E) ............ Derate Linearly at 12 mW/oC to 200 mW
For T. = -55 to + 100°C (PACKAGE TYPE D) ........................................... SOO mW
For T. = +100 to + 125°C (PACKAGE TYPE D) ......... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE ................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ............................................................. -55 to + 125°C
PACKAGE TYPE E .............................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (T".) ......................................... -65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.................... +265°C
I
STATIC ELECTRICAL CHARACTERISTICS at T. = -40 to + 85°C , Except as noted
TEST
CONDITIONS
LIMITS
CDP1821
CDP1821C
UNITS
CHARACTERISTICS
Vo Y,N Voo
(V) (V) (V) Min. Typ." Max. Min. Typ." Max.
Quiescent Device
0,5
5
50
500
50
500
/J. A
Current,
0,10 10
1000
100
Output Voltage:
0,5
5
0
0.1
0.1
0
Low-Level,
0,10 10
0
0.1
VOL
High-Level,
VOH
0,5
5
4.9
4.9
5
5
V
- 0,10 10 9.9 10
Input Low Voltage, V,l 0.5,4.5 5
1.5
1.5
0.5,9.5 10
3
Input High Voltage, V,H 0.5,4.5 5
3.5
3.5
0.5,9.5
10
7
Output Low (Sink)
0,5
0.4
5
4
4
2
2
Current,
0.5 0,10 10
rnA
4
8
10l
-1
-1
Output High (Source)
4.6
0,5
5
-2
-2
-4
Current,
9.5 0,10 10 -2
IOH
Input Current,
0,5
5
±5
±5
',N
±10 - 0,10 10 /J. A
3-State Output
0,5
0,5
5
±5
±5
±10
Leakage Current, lOUT 0,10 0,10 10
rnA
Operating Current,IOD.t
0,5
5
2
4
2
4
0,10 10
4
8
pF
Input Capacitance, C'N
7.5
7.5
5
5
Output Capacitance,
15
15
COUT
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tOutputs open circuited; cycle time = 1 ps.
'Typical values are for T. = 2SoC and nominal
Voe.
129
RCA CMOS LSI Products
CDP1821, CDP1821C
OYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +850 C, VOO ±5%
t r , tf= 20 ns, VIH = 0.7 VOO, VIL = 0.3 VOO, CL = 100 pF
LIMITS
CHARACTERISTIC
VOO
(V)
COP1821
Min. t
I
Typ. *
I
COP1821C
Max.
Min.t
I
Typ.*
I
UNITS
Max.
Read Cycle
Data Access
tAA
Read Cycle
tRC
Output Enable t DOA
Output Disable t DOH
ReadIWrite
Setup Time
Read/Write
Hold Time
tRWS
tRWH
125
250
250
-
75
-
125
125
-
-
250.
-
250
-
-
125
-
-
-
-
-
5
-
10
5
10
5
-
50
75
-
50
75
10
-
25
40
-
-
-
5
50
75
-
50
75
10
-
25
40
-
-
5
75
-
-
75
-
10
50
-
-
-
5
75
-
-
-
75
-
-
10
50
-
-
-
-
-
*Typical values are for T A = 25 0 C and nominal voltages.
tTime required by a limit device to allow for the indicated function.
AO-A9
R/W
(NOTE 3)
DATA OUT
----t------------( 1 " - - - - - . 1
(NOTE 5)
"READ-CYCLE
92CS· 51.71RI
Note 1 Chip-Select ICSI permitted
to changa from high to lOW
leval or remain lOW on 8
salected device.
Note 3 RaedIWrite (R/WI mUll ba
at a high laval during all
address tranlitionl.
Note 2 Chip-Select (eS) permitted
to change from low to high
leval or ramaln low.
Note 4 Don't cere.
Note 5 Oata-Out (001 II. hloh Impedance within tOIS nl after
the failing edge of RIW or
the rising edge of CS.
Fig. 1 - Read-cycle timing diagram.
130
ns
1800-Serles Memories
CDP1821, CDP1821C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85 0 C. VDD ±5%
t r .1t = 20 ns. VIH = 0.7 VDD. VIL = 0.3 VDD, CL = 100 pF
LIMITS
CHARACTERISTIC
CDP1821
CDP1821C
VDD
(V)
Min. t
5
10
275
175
-
-
275
-
-
-
-
5
10
75
-
-
75
50
-
-
-
I Typ. * I Max.
Min.t
I Typ.* I Max.
UNITS
Write Cycle
Write Cycle
twc
5
75
-
-
75
50
100
75
-
-
-
Input Data Setup
Time
tDS
10
5
10
-
-
100
-
-
-
Input Data Hold
Time
tDH
5
10
75
50
-
75
-
-
-
ReadlWrite Pulse
Width Low tWRW
5
10
125
75
-
-
125
-
Address Setup
Time
tAS
Write
Recovery
tWR
-
-
-
-
ns
-
-
I
*Typical values are for T A = 2S o C and nominal voltages.
tTime required by a limit device to ailow for the indicated function.
twc
AO-A9
R/W
(NOTE 3)
'AS
I'------.Jt--'AH
DI
WRITE -CYCLE
Nota 1 Chip-Select (6"51 permitted
to change from high to low
leval or remain low on a
selected device.
92CS-31972RI
Note 2 Chip-Select (CsI permitted
to change from low to high
level or remain low.
Note 3 Don't care.
Fig. 2 - Write cycle timing diagram
131
RCA CMOS LSI Products
CDP1821, CDP1821C
DATA RETENTION CHARACTERISTICS at TA = -40 to +85°C; see Fig. 3
TEST
CONDILIMITS
CHARACTERISTIC
TIONS
CDP1822
CDP1822C
UNITS
VOR Voo
(V)
(V) Min. Typ." Max. Min. Typ.- Max.
Min. Data Retention
1.5
1.5
V
2
2
Voltage,
VOR
pA
Data Retention Quiescent
2
100
30
100
30
Current,
100
Chip Deselect to Data
5
600
600
Retention Time,
10
ns
300
tCOR
Recovery to Normal
5
600
600
Operation Time,
10
300
tRC
ps
Voo to VOR Rise and
2
5
1
1
Fall Time
t"t,
-
-
-
-
-
-
-
-
-
-
-
'Typical values are for T. = 25° C and nominal Voo.
Fig. 3 - Low
VOD
data retention waveforms and timing diagram.
Fig. 4 - 4K byte RAM system using the COP 1859, COP1856, and COP1821.
132
1800-Series Memories
CDP1821, CDP1821C
R/Wo-----------------------------------------,
ROW
BUFFERS
Fig. 5 - Functional block diagram.
I
OPERATING AND HANDLING
CONSIDERATIONS
these conditions must not cause Voo-Vss
to exceed the absolute maximum rating.
1. Handling
All inputs and outputs of RCA CMOS
devices have a network for electrostatic
protection during handling. Recommended handling practices for CMOS
devices are described in ICAN-6525
"Guide to Better Handling and Operation of CMOS Integrated Circuits."
Input Signals
To prevent damage to the input protection circuit. input signals should never
be greater than Voo nor less than Vss.
Input currents must not exceed 10 mA
even when the power supply is off.
2. Operating
Operating Voltage
During operation near the maximum
supply voltage limit. care should be
taken to avoid or suppress power supply
turn-on and turn-off transients. power
supply ripple. or ground noise; any of
Unused Inputs
A connection must be provided at every
input terminal. All unused input terminals must be connected to either Voo or
Vss. whiChever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may
damage CMOS devices by exceeding
the maximum device dissipation.
133
RCA CMOS LSI Products
CDP1822, CDP1822C
A3
I
22
A2
AI
2
3
4
5
6
21
20
AO
A5
AS
A7
v'S
DI I
DDI
DI2
7
8
9
10
II
19
18
17
16
15
14
13
12
VDD
44
AlW
C1I"
0.0.
CS2
004
DI4
DOll
DIll
D02
TOP VIEW
9,2CS-29976AI
CDP1822, CDP1822C
TERMINAL ASSIGNMENTS
256-Word by 4-Bit LSI Static
Random-Access Memory
Feature.:
• Low operating current - 8 mA
at VDD = 5 V and cycle time = 1 IJs
• Industry standard pinout
• Two Chip-Select inputs - simple
memory expansion
• Memory retention for standby battery
voltage of 2 V min.
• Output-Disable for common I/O
systems
• 3-State data output for bus-oriented
systems
• Separate data inputs and outputs
The RCA-CDP1822 and CDP1822C are
25&-word by 4-bit static random-access
memories designed for use In memory systems where high speed, low operating current, and simplicity in use are desirable.
T~e CDP18~2 features high speed and a
wide operating vOI~age range. Both types
h~ve separate data Input~ and outputs and
utilize single power supplies of4 t06.5 volts
for the CDP1822C and 4 to 10.5voltsforthe
CDP1822.
operation independent of the Chip-Select
input condition. The output assumes a
high-impedance state when the Output
Disable is at h~evel or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS
technology is preserved in this design. For
TTL interfacing at 5-V operation, excellent
system noise margin is preserved by using
an external pull-up resistor at each input.
Two Chip-Select Inputs are provided to
simplify system expansion. An Output Disj!ble control provides Wire-OR capability
and is also useful in common InpuVOutput
systems. The Output Disable input allows
these RAMs to be used in common data
InpuVOutput systems by forci ng the output
into a high-Impedance state during a write
The CDP1822 and CDP1822C types are
supplied in 22-lead hermetic dual-in-line
side-brazed ceramic packages (0 suffix), in
22-lead dual-in-line plastic packages (E
suffix). The CDP1822C is also available in
chip form (suffix H).
OPERATIONAL MODES
MODE
Chip
Select 1
5.
Read
Write
Write
Standby
Standby
Output Disable
Logic 1 = High
134
0
0
0
1
X
X
Logic 0 = Low
INPUTS
Chip
Output
Select 2
Disable
CS2
00
1
0
1
0
1
1
X
X
0
X
X
1
x = Don't Care
Readl
Write
RIW
1
0
0
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
1800-5erle8 Memories
CDP1822, CDP1822C
RECOMMENDED OPERATING CONDITIONS at TA = Full Package Temperature Range
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
LIMITS
CDP1822
CDP1822C
Min.
Max.
Min.
Max.
10.5
4
6.5
4
Vss
Voo
Vss
Voo
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
UNITS
V
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss Terminal)
CDP1B22 ..................................................................... -0.5 to + 11 V
CDP1B22C ..................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ....................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to + 60° C (PACKAGE TYPE E) ................•...........•.•............ 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) ............ Derate Linearly at 12 mW/oC 10 200 mW
For T. = -55 to +100°C (PACKAGE TYPE D) .......................................... 500 mW
For T. = + 100 to + 125°C (PACKAGE TYPE D) ......... Derate Linearly at 12 mW/oC to 200 mW
DIOVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ............................................................. -55 to + 125°C
PACKAGE TYPE E .............................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (T...) ......................................... -65 to + 150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .................... +265°C
I
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to + 85°C Except as noted
TEST
CONDITIONS
LIMITS
CHARACTERISTICS
Y,N Voo
CDP1822
CDP1822C
UNITS
Vo
(V)
(V) (V) Min. Typ." Max. Min. Typ.* Max.
5
Quiescent Device
500
500
0.5
IIA
Current,
0,10 10
1000
100
Output Voltage:
0,5
0.1
5
0
0.1
0
Low-Level,
0
0.1
VOL
0.10 10
4.9
High-Level,
0,5
VOH
5
5
4.9
5
10
V
0.10 10 9.9
Input Low Voltage, V,L 0.5,4.5
1.5
5
1.5
0.5,9.5
10
3
Input High Voltage, V,H 0.5,4.5
5
3.5
3.5
0.5,9.5
10
7
Output Low (Sink)
0.4
0,5
4
4
5
2
2
Current,
0.5 0,10 10 4.5
9
mA
10L
-1
-1
-2
Output High (Source)
4.6
0,5
5
-2
Current,
9.5 0,10 10 -2.2 -4.4
10H
Input Current,
0,5
5
±5
±5
liN
0,10 10
±10
IIA
3-State Output
0,5
0,5
5
±5
±5
±10
Leakage Current, lOUT 0,10 0,10 10
0,5
4
4
mA
Operating Current,loo.t
5
8
8
0,10 10
8
16
7.5
pF
Input Capacitance, C'N
5
7.5
5
Output Capacitance,
10
15
10
15
COUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tOutputs open circuited; cycle time = lps.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
'TYPical values are for T. = 25°C and nominal VDO•
135
RCA CMOS LSI Products
CDP1822, CDP1822C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Vpp ±5%,
Input tf tf 20 ns, VIH 0 7 Voo VIL 03 Voo CL
100 pF
=
=
=
CHARACTERISTIC
Vop
(V)
=
CDP1822
CDP1822C
UNITS
Mln·t Typ,· Max. Mln·t Typ.· Max.
Read Cycle Times (Fig. 1)
Read Cycle
tRC
Access from
Address
Output Valid from
Chip-Select 1
Output Valid from
Chip-Select 2
Output Active from
Output Disable
Output Hold from
Chip-Select 1
Output Hold from
Chip-Select 2
Output Hold from
Output Disable
tM
tOPA1
t OPA2
tOPA3
tOOH1
tOOH2
tOOH3
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
450
250
20
20
20
20
20
20
250
150
250
150
250
150
-
450
250
450
250
450
250
200
110
-
-
-
-
-
450
20
20
20
-
-
-
250
450
-
-
250
450
-
-
250
450
-
200
-
tTime required by a limit device to allow for indicated function.
'Typical values are for T A = 25° C and nominal Vee.
AO - A7
CHIP SELECT I
CHIP SELECT 2
OUTPUT DISABLE
READ/WRiTE
DATA OUT
HIGH
IMPEDANCE
DATA OUT
VAll D
HIGH
IMPEDANCE
92CM- 30244R4
Fig. 1 - Read cycle timing waveforms.
136
ns
1800-Serles Memories
CDP1822, CDP1822C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ±5%,
Input t"t, = 20 ns, V,H = 0.7 Voo, V,L = 0.3 Voo. CL = 100 pF
CHARACTERISTIC
Voo
(V)
Write Cycle Times (Fig. 2)
Write Cycle
twc
Address Setup
tAs
Write Recovery
tWR
. Write Width
tCS2H
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
taos
5
10
tWRw
Input Data
Setup Time
tos
Data In Hold
tOH
Chip-Select 1
Setup
Chip-Select 2
Setup
l..Onlp-::;elect 1
Hold
Chip-Select 2
Hold
Output Disable
Setup
5
10
5
10
tCS1S
tCS2S
tCs1H
CDP1822
CDP1822C
UNITS
Mln·t Typ.· Max. Mln.t Typ.· Max.
500
300
200
110
50
40
250
150
250
150
50
40
200
110
200
110
0
0
0
0
200
110
-
-
500
-
-
-
-
-
-
-
200
-
-
-
-
-
-
-
50
-
250
-
-
-
-
250
-
-
-
-
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
-
-
200
-
-
-
-
-
-
0
0
0
0
200
-
-
-
-
-
-
-
-
ns
I
-
-
-
tTlme required by a limit device to allow for the Indicated function.
'Typical values are for T. = 25°C and nominal Voo.
t--------
'wc
AO-A7
CHIp-SELECT I
CHIP- SELECT 2
OUTPUT DISABLE
011- 014
'WRW
READ/WRiTE
~DON'TCARE
*
92CM- !t0804R04
'ODS IS REQUIRED FOR COMMON I/O
OPERATION ONLY; FOR SEPARATE I/O
OPERATIONS, OUTPUT DISABLE IS DON'T CARE.
Fig. 2 - Write cycle timing waveforms.
137
RCA CMOS LSI Products
CDP1822, CDP1822C
DATA RETENTION CHARACTERISTICS at TA - -40 to +85°C ; see F'Ig. 3
TEST
CONDILIMITS
CHARACTERISTIC
TIONS
CDP1822
CDP1822C
VOR VOO
(V)
(V) Min. Typ." Max. Min. Typ." Max.
Min. Data Retention
1.5
2
2
1.5
Voltage,
VOR
Data Retention Quiescent
100
100
2
30
30
Current,
100
Chip Deselect to Data
5
600
600
Retention Time,
10
300
teOR
Recovery to Normal
5
600
600
Operation Time,
10
300
tRC
Voo to VOR Rise and
2
5
1
1
Fall Time
t"t,
TYPical values are for TA - 25° C and nominal Vee.
-
-
-
UNITS
V
pA
-
ns
ps
.
92CS-3080~RI
Fig. 3 -
WRITE
AODRESS
DECODER
Low Vee data retention timing waveforms.
READ
ADDRESS
DECODER
Voo
92CS-27256R2
Fig. 4 - Memory cell configuration.
OPERATING & HANDLING
CONSIDERATIONS
1. Handling
All inputs and outputs of RCA COS/
MaS devices have a network for electrostatic protection' during handling.
Recommended handling practices for
COS/MaS devices are described in
ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated
Circuits."
2. Operating
Operating Voltage
During operation near the maximum
supply voltage limit, care should be
taken to avoid or suppress power supply
turn-on and turn-off transients, power
supply ripple, or ground noise; any of
138
these conditions must not cause Voo-Vss
to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input signals should never
be greater than VDO nor less than Vss.
Input currents must not exceed 10 rnA
even when the power supply is off.
Unused Inputs
A connection must be provided at every
input terminal. All unuSed input terminals must be connected to either Voo or
Vss, whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may
damage COS/MaS devices oy exceeding the maximum device dissipation.
1800-Serles Memories
CDP1822, CDP1822C
r;:----- --------- - - - --.- - - - - - - --,
(S)
(52)
I
~
I
•
-.!!oYoo
1
OECOO'
E~
I
I
I
(8K52)
(4)
I
STORAGE
013
014
I
I
I
I
I
I
I
ERS
I
I
I
*
R/Wcr~-----------4~
I
* 19 I
CSi
CS2
I
I
17
00* 18
I
-1!O"ss
I
_____ .-1
L ________________________ _
.+. f
INPUT PROTECTION
92CI..- Joot'5fll
OUTPUT
PROU:CTION
CIRCUIT
NETWORK
Fig. 5 - Functional block diagram for CDP1822 and CDP1822C.
r
19
-- - - -
-
-
- cONTROL
A -,
I
I }tHIP'SELECT
CS2
~-t------~
CONTROL
I
11
r=-::--':::"'::';-~ _ _ _ I
R/W
20
p---------tI }gH!!- SELECT a
-
---<
-- -- - CONTRoL--Cl
R/W CONTROL
l}gUTPUT
1
I
DISABLE L- _ _ _ _ _ _ _ _ _ _ _ _ _ - '
DISABLE
CONTROL
92CM-30oe4R3
Fig. 6 - Logic diagram of controls for CDP1822 and CDP1822C.
139
RCA CMOS LSI Products
CDP1822, CDP1822C
CPU
COPIB02
MAO-3
CLOCK
B
U
S
BUS 0-7
B
CS
CSIC--+--CS2
CS3
CEO
CEif------
CE2
en
Fig. 7 - 4K byte RAM system using the CDP1858 and CDP1822.
92CS-3156B
The photographs and dimensions of each CMOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57· instead of 90· with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both
dimensions.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10- 3
inch).
Dimensions and pad layout for CDP1822CH.
140
1800-Serles Memories
CDP1823, CDP1823C
BUS
BUS
BUS
BUS
BUS
BUS
8US
BUS
CSI
C52
C53
VSS
0
I
2
3
4
56
7
4
5
6
7
8
9
10
II
12
24
23
22
21
20
19
18
17
16
15
14
13
128-Word X 8-Bit Static
Random-Access Memory
Voo
M.O
M.,
M.2
M.3
MM
MA5
MAG
MWR
-MlfI'j
Features:
• Fast access time:
450 ns at Voo = 5 V;
250 ns at Voo = 10 V
• Common data inputs and outputs
• Multiple-chip select inputs to simplify
memory system expansion
c>5
CS4
TOP VIEW
92C5 - 28 703
TERMINAL ASSIGNMENT
The RCA-CDP1823 and CDP1823C are
128-word by 8-bit CMOS SOS static
random-access memories. These memories are compatible with general-purpose
microprocessors. The two memories are
functionally identical. They differ in that
the CDP1823 has a recommended operating voltage range of 4 to 10.5 volts, and the
CDP1823C has a recommended operating voltage range of 4 to 6.5 volts.
The CDP1823 memory has 8 common
data input and data output terminals for
direct connection to a bidirectional data
bus and is operated from a single voltage
supply. Five chip·select inputs are pro·
vided to simplify memory·system expan·
sion. In order to en~ the CDP18gg the
reo
chip·select inputs CS2, CS3, and
quire a low input signal, and the chip·
select inputs CS1 and CS4 require a high
input signal.
The MRO signal enables all 8 output
drivers when in the low state and should
be in a high state during a write cycle.
After valid data appear at the output, the
address inputs may be changed immediately. Output data will be valid until
either the MRD signal goes high, the
device is deselected, or tAA (access time)
after address changes.
I
The CDP1823 and CDP1823C are supplied
in hermetic 24-lead dual-in-line ceramic
packages (0 suffix), and in 24-lead dual-inline plastic packages (E suffix).
s
OPERATIONAL MODES
Function
MRD MWR
CS1
CS2
CS3
CS4
Cs5
READ
0
X
1
0
0
1
0
WRITE
STA"'O-BY
1
1
0
1
1
1
0
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
1
X
X
1
X
X
X
X
X
0
X
X
X
X
X
1
NOT
SELECTED
Logic 1 ~ High
Logic 0
~
Low
X
X
X
Bus Terminal State
Storage State of
Addressed Word
Input High-Impedance
High-Impedance
High-Impedance
X ~ Don't Care
141
RCA CMOS LSI Products
CDP1823, CDP1823C
at T A = FULL PACKAGE·TEMPERATURE RANGE
OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges:
LIMITS
CDP1823D
CDP1823CD
Min.
Max.
Min.
Max.
CHARACTERISTIC
Supply-Voltage Range
Recommended Input Voltage Range
UNITS
4
10.5
4
6.5
V
VSS
VOD
VSS
VOO
V
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD)
(All voltage values referenced to VSS terminal)
CDP1823 ............................................................. -0.5to + 11 V
CDP1823C ............................................................. -0.5to + 7 V
INPUT VOLTAGE RANGE, ALLINPUTS ................................... -0.5to VDD + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................. ;t 10 rnA
OPERATING·TEMPERATURE RANGE (TA):
CERAMIC PACKAGES (0 SUFFIX TYPES) ................................... - 55 to + 125·C
PLASTIC PACKAGES (E SUFFIX TYPES) ..................................... - 40 to +85·C
STORAGE TEMPERATURE RANGE (T stg)' .................................... - 65 to + 150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16;t 1/32 inch (1.59;t 0.79 mm) from case for 10 s max .................... + 265·C
STATIC ELECTRICAL CHARACTERISTICS at TA
= -40 to + 85°C
Except as noted
TEST
CONDITIONS
Va
(V)
Voo
(V) (V)
-
-
100
-
0,5
0,10
5
10
VOL
VOH
-
0,5
0,10
0,5
0,10
5
10
5
10
-
5
10
5
10
5
10
5
10
5
10
CHARACTERISTICS
Quiescent Device
Current,
Output Voltage:
Low-Level,
High-Level,
Input Low Voltage, V,L 0.5,4.5
Y,N
0.5,9.5
Input High Voltage, V,H 0.5,4.5
0.5,9.5
Output Low (Sink)
0.4
0,5
Current,
IOL
Output High (Source)
Current,
Input Current,
0.5
4.6
9.5
0,10
0,5
0,10
0,5
Any
Input 0,10
3-State Output
0,5
0,5
Leakage Current, lOUT 0,10 0,10
IOH
',N
Operating Current,loo,t
Input Capacitance, C'N
Output Capacitance,
COUT
5
10
LIMITS
CDP1823C
CDP1823
Min. Typ.· Max. Min. Typ.* Mali.
500
500
1000 0.1
0.1
0
0
0.1
0
4.9
5
4.9
5
9.9
10
1.5
1.5
-
-
-
-
-
-
-
-
-
-
-
-
3.5
7
-
-
3.5
-
-
2
4
-
2
4
4.5
-1
9
-
-
-
-2
-1
-2
-
-
-2.2 -4.4
-
-
-
0,5
0,10
5
10
-
-
-
-
-
-
-
tOutputs open CIrcuIted; cycle tIme = 1 JIS.
'Typical values are for T" = 25° C and nominal VDD.
142
-
3
-
-
±5
±10
4
8
5
8
16
7.5
-
10
15
-
±5
±10
-
-
UNITS
pA
V
-
-
rnA
±5
-
pAl
±5
-
4
8
-
-
5
7.5
10
15
rnA
pF
1800-Serles Memories
CDP1823, CDP1823C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
tr,t, 20 nl, CL 100 pF.
=
=
VDD
(V)
CHARACTERISTIC
Read Cycle (See Fig. 1)
Access Time From
Address Change, tAA
Access Time From
Chip Select, tDOA
MRD to Output
Actrve, tAM
Data Hold Time
After Read, tlDOH
.
=- 40 to + 85 ·C, VDD ± 5%,
LIMITS
UNITS
CDP1823
I CDP1823C
Min. tlTyp. * Max. Min. t Typ. * Max.
-
5
10
5
10
5
10
5
10
-
-
25
15
=
275
150
150
100
150
100
50
25
450
250
250
150
250
150
75
40
-
275
450
- - - 150 250
- 75
25
50
-
-
150
250
ns
Typical values are at TA 25'C and nominal voltage.
trlme required by a limit device to allow for the Indicated function.
I
tAA
ADDRESS
I---tAM - -
\
f - - - t OOA
CSI,CS4
DATA OUT
HIGH IMPEDANCE
1/
\\
VALID DATA
NOTE' ~ IS HIGH DURING READ OPERATION.
TIMING MEASUREMENT REFERENCE IS O.5V DD •
---
tOOH
I-gQ%
10%
92CM-31942RI
Fig. 1 • Read cycle liming diagram.
143
RCA CMOS LSI Products
CDP1823, CDP1823C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = - 40 to + 85 °C, VDD:t 5%,
tr,tf =20 ns, CL =100 pF.
VDD
(V)
CHARACTERISTIC
LIMITS
CDP1823
I CDP1823C
UNITS
Mln.t)Typ.* Max. Mln.tITyp.* Max.
Write Cycle (See Fig. 2)
5
10
5
10
5
10
5
10
5
10
5
10
Write Recovery, tWR
Write Cycle, twc
Write Pulse
Width, tWRW
Address
Setup Time, tAS
Data
Setup Time, tDS
Data Hold Time
From MWR, tOH
75
50
400
225
200
100
125
75
100
75
75
50
=
-
-
-
75
-
-
-
-
- 400 - - - - - 200 - - - - 125 - - - - - - - 100 - - - 75 - - - - -
ns
'Typical values are at TA 2SoC and nominal voltage.
frime required by a limit device to allow for the Indicated function.
1---------- 'wc----
----,
ADDRESS
I--
'AS---
r----'wrCSI.CS4
c"Q,m,rn
t-
- 'WRW-----ltos-+-JC:
WRITE OPERATION TiMING DIAGRAM
92CS-34740
Fig. 2 • Write cycle timing diagram.
150
os
os
ns
ns
ns
1800-Series Memories
CDP1824, CDP1824C
DATA RETENTION CHARACTERISTICS at TA = -40 to +85°C; See Fig. 3.
-
TEST CONDITIONS
CHARACTERISTIC
CDP1824
VDD
tv)
Data Retention Voltage,
2.5
-
2.5
-
V
= 2.5 V
-
-
10
-
40
I1A
= 2.5 V
5
10
600
300
600
ns
VDR=2.5V
5
10
600
300
-
VDR
Chi p Deselect to Data
Retention Time, tCDR
V DR
Recovery to Normal
Operation :rime, tRC
Min. Max.
-
VDR
Data Retention Quiescent
Current, IDD
Min. Max.
CDP1824C UNITS
-
600
-
- ElATA RETENTION -- MODE
09~
Voo
~
'cDR
cs
_
Voo
~tf*
0.95 Voo
VOR
t,
*
I
r---
_I ~
VIH
VIL
*t, .tPI~s
92CS-30629
Fig. 3 - Low Voo data retention waveforms and timing diagram.
"A4----,
MA3
MA2
MAl
MAO
BUS BUS 8US 8US BUS BUS 8US 8US
76543210
FUNCTIONAL DIAGRAM
Fig. 4 - Functional diagram.
151
RCA CMOS LSI Products
CDP1824, CDP1824C
CPUI ROM SYSTEM
£.U
COPIB02
ROM
COPIB33
I
RAM
SYSTEM
I
.M.M.
CDIB24
92CS-34141
Fig. 5 - CDP1824 (128 x 8) minimum system (128 x 8)
OPERATING AND HANDLING
CONSIDERATIONS
these conditions must not cause Voo-Vss
to exceed the absolute maximum rating.
1. Handling
Input Signals
To prevent damage to the input protection circuit. input signals should never
be greater than Voo nor less than Vss.
Input currents must not exceed 10 mA
even when the power supply is off.
.
All inputs and outputs of RCA CMOS
devices have a network for electrostatic
protection during handling. Recommended handling practices for CMOS
devices are described in ICAN-6525
"Guide to Better Handling and Operation of CMOS integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximClm
supply voltage limit. care should be
taken to avoid or suppress power supply
turn-on and turn-off transients. power
supply ripple. or ground noise; any of
152
Unused Inputs
A connection must be provided at every
input terminal. All unused input terminals must be connected to either Voo or
Vss. whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may
damage CMOS devices by exceeding
the maximum device diSSipation.
1800-Series Memories
Preliminary Data
BUS 0
BUS I
BUS 2
BUS 3
BUS4
BUS 5
BUS 6
BUS 7
CSI
~
Vss
3
4
5
6
7
8
9
10
"
22
21
20
19
18
17
16
15
14
13
12
CDP1826C
CMOS 64-Word X 8-Bit Static
Random-Access Memory
VDD
AO
CS/A5
AI
A2
A3
A4
TPA
MRD
Features:
• Compatible with CDP1800 and 4000-series devices
• Interfaces with CDP1800-series microprocessors
without additional address decoding
• Daisy chain feature to further reduce external
decoding needs
• Multiple chip-select inputs for versatility
• Single voltage supply
• No clock or precharge required
f;lWI{
CEO
TOP VIEW
92CS-34Q34
Terminal Assignment
The RCA CDP1826C is a general-purpose, fully static, 64word x 8-bit random-access memory, for use in CDP1800
series or other microprocessor systems where minimum
component count and/or price performance and simplicity
In use are desirable.
The CDP1826C has 8 common data input and data-output
terminals with tristate capability for direct connection to a
standard bi-directional data bus. Two chip-select inputsCS1 and CS2 - are provided to simplify memory-system
expansion. An additional select pin, CS/A5, is provided to
enable the CDP1826C to be selected directly from the
CDP1800 address bus without additional latching or decoding. In an 1800 system, the CS/A5 pin can be tied toany MA
ADOR BUS
--
--
address line from the CDP1800 processor. A TPA input is
provided to latch the high-order bit of this address line as a
chip-select for the CDP1826C. If this CSI A5 input is latched
high, and if CS1=1 and CS'2 =0 at the appropriate time in the
memory cycle, the CDP1826C will be enabled for writing or
reading. In a non-1800system, the TPA pin can betied high,
and the CS/A5 pin can be used as a normal address input.
The six input-address buffers are gated with the chip-select
function to reduce standby current when the device is deselected, as well as to provide for a simplified power down
mode by reducing address buffer sensitivity to long fall
times from address drivers which are being powered down.
1~
N -N2MRC
ADDR BUS
TPB
TPA
TPA
Q
DATA
ROM
MRD
---
MRli
SCO SCI
iN'i'EmiiWf
I/O
CONTROL
DMA -IN OMA-OL T
MWR
CEO
l
CPU
CDP/SOO
SERIES
RAM
COPIS26C
EFI-EI'4
II
S-SIT
II
BIDIRECTIONAL DATA BUS
I
92CM-34043
Fig. 1 - Typical CDP1802 microcprocessor system.
153
•
RCA CMOS LSI Products
CDP1826C
Two memory control signals, M1f!) and MWR, are provided
for reading from and writing to theCDP1826C. The logic is
designed so that MWR overrides MRD, allowing the chip to
be controlled from a single R/W line.
For such an interface, the MRD line can be tied to Vss, with
the MWR line connected to R/W
A CHIP ENABLE OUTPUT is provided for daisy-chaining to
additional memories. This output is high whenever the
chip-select function selects the CDP1826C, which deselects any other chip which has its CS input connected to the
CDP1826C CEO output. The connected chip is selected
when the CDP1826C is de-selected and the URn Input la
low. Thus, the CEO is only active fora read cycle and can be
set up so that a CEO of another device can feed the ~ of
the CDP1826C, which in turn selects a third chip Inthedalay
chain.
The CDP1826C has a recommended operating voltage of
4.5 to 6.5 V and is supplied in 22-lead hermetic dual-In-line
side-brazed ceramic packages (D suffix). in 22-lead dualin-line plastic packages (E suffix). The CDP1826C Is alao
available in chip form (H suffix).
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltages referenced to Vss Terminal) .............................................................................. -0.5 to'+7 V
INPUT VOLTAGE RANGE, ALL INPUTS .........................................................................-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................................................± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to + 100°C (PACKAGE TYPE D) ........................................................................... 500 mW
For TA = + 100 to + 125°C (PACKAGE TYPE D) .......................................... Derate Linearly at f2 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ................................................................................. , ............ -55 to + 12So C
PACKAGE TYPE E ............................................................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tot.) .......................................................................... ~6S to + lS0·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +26S"C
RECOMMENDED OPERATING CONDITIONS at TA = Full Package Temperature Range.
For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CDP1826C
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
Input Signal Rise or Fall Time
VeD = 5 V
154
t" tf
UNITS
MIN.
MAX.
4.5
Vss
' 6.5
Vee
V
-
10
ma
1800-Series Memories
CDP1826C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ± 5% except as noted
LIMITS
CONDITIONS
CHARACTERISTIC
V,N
CDP1826C
Vo
Voo
TYP.(V)
(II)
(V)
MIN.
Quiescent Device
100
0,5
5
5
Current
Output Low Drive
IOL
0.4
1
0,5
5
2
(Sink) Current
Output High Drive
IOH
-1
-1.5
4.6
0,5
5
(Source) Current
Output Voltage
VOL
0,5
5
0
Low Level
Output Voltage
VOH
0,5
4.9
5
5
High Level
Input Low Voltage
V,L
0.5,4.5
5
Input High Voltage
V,H
0.5.4.5
3.5
5
Any
Input Leakage Current
0,5
±0.1
5
ioN
Input
3-State Output
lOUT
0,5
±0.1
0.5
5
Leakage Current
Operating Device
IOPERt
5
0,5
5
Current
Input
C'N
5
Capacitance
Output
COUT
10
0,5
5
Capacitance
-
-
UNITS
MAX.
50
/J A
mA
0.1
-
-
1.5
V
±1
±1
/JA
-
mA
7.5
pF
I
15
-TYPical values are for TA - 25°C and nominal Vee.
tOutputs open circuited; cycle times = 1 /15.
BUS 0
AO
BUS I
AI
A2
A3
INPUT
ADDRESS
BUFFERS
XY
DECODE
IN PUT 10UTPUT
DATA
BUFFERS
AND
CONTROL
64,S
MATRIX
A4
BUS 2
BUS 3
BUS 4
BUS'
BUS 6
CS/A5
BUS 7
TPA
CSI--------------------~
en ------------------'
MWR--------------------------------------------~
~------------------------------------------~~
CEO
92.CM-34044
Fig. 2 - Functional diagram.
155
RCA CMOS LSI Products
CDP1826C
I
A5
TPA
MRD
CEO
BUS
g
I
I
~
I
~
:t::J--.i
RAM
CSI ..
r,
VALID
I
I
DATA
VALID
DATA
CYCLE
(RAM SELECTED)
ROM CYCLE
(RAM DESELECTED)
CS2= 0
92CM-34048
OPERATING MODES
MRD
iiWli
CSI·m
TPA
CS/A5#'
WRITE
X
0
I
.n
I
I
READ
0
I
I
...n.
I
I
DESELECT
I
I
I
DESELECT
I
X
0
DESELECT
0
X
0
DESELECT
I
X
X
..n..
0
I
DESELECT
0
X
x
.J!..
0
0
FUNCTION
....
0
0
::I!
0
0
.,
0:
""
.n
X
X
CEO
I
I
X
I
X
0
0
WRITE
X
0
I
I
X
I
CL:~
READ
DESELECT
0
I
I
I
I
X
I
I
I
I
I
DESELECT
I
X
0
I
X
I
DESELECT
0
X
0
I
X
0
~
~~
z
0
z
X
'" FOR CDPI900 MODE. REFERS TO HIGH ORDER MEMORV
~~~~;S~L:6~ LEVEL AT TIME WHEN TPA
TRANSITION
l.
Fig. 3 - Chip Enable Output timing waveforms for CDP1800-based systems.
156
I--
I
I
1800-8erle8 Memories
CDP1826C
DYNAMIC ELECTRICAL CHARACTERISTICS
Input t, tl = 10 ns; CL = 50 pF and 1 TTL Load
.
at TA
= -40 to +85°C.
Voo
LIMITS
CDP1826C
TYP.-
CHARACTERISTIC
MIN·t
Read - Cycle Time. (Fig. 4)
Address to TPA Setup
= 5 V ±5%.
I
UNITS
I
MAX.
100
-
-
100
-
-
-
500
1000
200
-
-
-
500
1000
-
500
1000
-
150
300
75
-
-
tASH
Address to TPA Hold
tAH
Access from
Address Change
TPA Pulse Width
tAA
tPAW
Output Valid from
MAo
tAM
Access from
Chip Select
CEO Delay from
lAc
TPA~dge
teA
MRD to CEO Delay
tMC
ns
I
tTime required by a limit device to allow for the indicated function.
eTypical values are for T A = 25° C and nominal VDD •·
ADORESS BYTE
AO-AS
TPA
VALID
CSI.CSl
CHIP
SELECT
CEO
BUS
------------;---~~~~~~------[
!-----IAII
----~
VALID DATA
ItCM"M047
Fig. 4 - Read-cycle timing waveforms.
157
RCA CMOS LSI Products
CDP1826C
DYNAMIC ELECTRrCAL CHARACTERISTICS at TA = -40 to +85°C, Voo = 5 V ±5%,
Input t, tf = 10 ns' CL = 50 pF and 1 TTL Load
LIMITS
CHARACTERISTIC
CDP1826C
TYP.MIN.t
Write-Cycle Times (Fig. 5)
Address to TPA Setup,
100
High Byte
tASH
Address to TPA Hold
100
tAH
Address Set.up
250
500
Low Byte
tASL
TPA Pulse Width
200
1
1
-
UNITS
MAX.
-
-
-
-
700
350
-
300
200
-
400'
200
-
100
50
-
tPAW
Chip Select Setup
tes
Write Pulse Width
tww
Data Setup
tos
Data Hold
tOH
tTime required by a limit device to allow for the indicated function.
oTypical values are forT. = 25°C and nominal VDD •
AO-A5
lOW ORDER ADDRESS BYTE
'AHI-----'A8L.------I
TPA _ _ _ _ _11-
MWR
------------------"j+-'ww
----~,...----
14----'C8'------<"'I
C81·m
VALID CHIP 8ELECT
14-------,
BU8
DS---------t---f4'DH
DATA IN STABLE
92CM -54048
Fig. 5 - Write-cycle timing waveforms.
158
ns
1800-Series Memories
CDP1826C
DATA RETENTION CHARACTERISTICS at TA = -40 to +85°C; see Fig. 6
TEST
CONDITIONS
CHARACTERISTIC
VOR
Voo
(V)
(V)
MIN.
Min. Data Retention
VoR
Voltage
Data Retention Quiescent
2.5
Current
100
Chip Deselect to Data
5
600
Retention Time
tCoR
Recovery to Normal
5
600
Operation Time
tRC
Voo to VoR Rise and
5
1
2.5
Fall Time
t"t,
-Typical values are for TA
= 25° C
and nominal Voo.
r
v~o~o____~
oATA RETENTION
MODE
O~:o
fCoR
VOR
f,
LIMITS
CDP1826C
UNITS
TYP,-
MAX.
2
2.5
V
5
25
/1 A
-
-
-
-
ns
-
-
/1S
=1
~______
O~O ~
CS2
I
fRC
}fViH
ViH\C
VIL~II-
.. _ _ _ _ _ _ _ _ _ _ _ _ _~f V,L
92CS-30e05RI
Fig. 6 - Low Voo data retention timing waveforms.
cOPle75
:tIO PORT
COPle02
CPU
COPI8U42
EPROM
COPle26C
RAM
Voo
CSI
vss
000·7
TPA
MWR
MRO
Voo
VSAT
VOO
~
VOO
CS2
CS3
CST
BUS 0-7
92CM- 34045
For the configuration shown, the RAM is mapped into locations 2000-3FFF with wrap-around at
6000-7FFF
AOOO-BFFF
EOOO-FFFF
Note: Any address from MAO-MAS can be connected to
CS/ A5 and still contiguously map 64 bytes of RAM - even
though the address labels of the RAM do not match those of
the CPU, the random access property of the RAM still results in proper operation.
The ROM is mapped into the first page of memory with
wrap-around at all pages where MA5.1 = O.
Fig. 7 - A compact microcomputer system without external decoding.
159
RCA CMOS LSI Products
CDP1831, CDP1831 C
MA7
MA6
MA5
MA4
MA3
MA2
MAl
MAO
BUSO
BUSI
BUS2
VSS
I
24
23
22
21
20
19
18
17
16
15
14
13
~
3
4
5
6
7
8
9
10
II
12
voo
TPA
Ne
CSI
CS2
MRO
CEO
BUS7
BUSS
BUS5
BUS4
BUS3
TOP VIEW
NC' NO CONNECTION
92CS-27584R2
512-Word X 8-Bit Static
Read-Only Memory
Features:
• Compatible with CDP1800 and CD4000-series devices
• On-chip address latch
• Interfaces with CDP1802 microprocessor without
additional components
• Optional programmable location within 64K
memory space
• Three-state outputs
Terminal Assignment
The RCA-COP 1831 and CDP1831 C types
are 4096-bit mask-programmable CMOS
read-only memories organized as 512
words x 8 bits and are completely static; no
clocks required. They will directly interface
with COP1800-series micro-processors
without additional components.
The COP1831 and COP1831C respond to
16-bit address multiplexed on 8 address
lines. Address latches are provided on-chip
to store the 8 most significant bits of the
16-bit address. By ma.sk option, this ROM
can be programmed to operate in any 512word block within 64K memory space. The
polarity of the high address strobe (TPA),
and CS1 and CS2 are user mask-programmable. (See RPP-610, "ROM Sales Policy
and Data Programming Instructions").
The Chip-Enable output signal (CEO) goes
"high" when the device is selected, and is
intended for use an an output disable control for RAM memory in a microprocessor
system.
The COP 1831C is functionally identical to
the CDP1831. The COP1831 has an operating voltage range of 4 to 10.5 volts, and the
COP1831 C has an operating voltage range
of 4 to 6.5 volts.
The COP1831 and CDP1831C types are
supplied in 24-lead hermetic dual-in-line,
side-brazed ceramic packages (0 suffix)
and in 24-lead dual-in-line plastic packages
(E suffix). The COP1831C is also available
in chip form (H suffix).
BUS4
BUS3
BUS2
BUSI
BUSO
f"'---"'--+CEO
VOO" 24
VSS " 12
Fig. 1 - Functional diagram.
160
'<2CS"Z758?R3
1800~Serles
Memories
CDP1831, CDP1831C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All voltage values referenced to Vs. terminal)
CDP1831 ..................................................................... -0.5 to +11 V
CDP1831.C .............................. " ...................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................... -0.5 to Voo H).5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60·C (PACKAGE TYPE E) ........................................... 500 mW
For T. = +60 to +85·C (PACKAGE TYPE E) ............ Derate Linearly at 12 mW/·C to 200 mW
For T. = -55 to + 100· C (PACKAGE TYPE D) .......................................... 500 mW
For T. = + 100 to + 125· C (PACKAGE TYPE D) ......... Derate Linearly at 12 mWfO C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T~ = FULL PACKAGE-TEMPERATURE RANGE ................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.)
PACKAGE TYPE 0 ............................................................. -55 to +125·C
PACKAGE TYPE E .............................................................. -40 to +85·C
STORAGE TEMPERATURE RANGE (T".) ......................................... -65 to + 150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .................... +265·C
OPERATING CONDITIONS at T. = Full Package-Temperature Range. For maximum reliability,
operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CDP1831
CDP1831C
Min.
Max.
Min.
Max.
4
10.5
4
6.5
VDD
Vss
Vss
VDD
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
UNITS
I
V
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C Except as noted
CONDITIONS
LIMITS
CHARACTERISTIC
Y,N VDD
CDP1831
CDP1831C
UNITS
Va
(V)
(V) (V)
Min.
Typ." Max. Min. Typ." Max.
Quiescent Device
5
5
0.01
50
- 0.Q2 200
/lA
10
10
1
Current, IDD
200 Output Low Drive
0.4
0,5
0.55
0.55
5
(Sink) Current, 10L 0.5 0,10 10
1.30
Output High Drive
(Source) Current,
4.6
0,5
-0.35
5
0.35 mA
9.5 0,10 10 -0.65
10H
Output Voltage
0,5
0.1
5
0
0.1
0
Low-Level, VOL
0,10 10
0.1
0
Output Voltage
0,5
5
4.9
5
4.9
5
10
High Level, VOH
V
9.9
- 0,10 10
Input Low Voltage, 0.5,4.5 5
1.5
1.5
V,L
1,9
10
3
Input High Voltage, 0.5,4.5 3.5
5
- 3.5 V,H
1,9
10
7
±10- ±1
Input Leakage
Any 0,5
5
±1
±10- ±2
Input 0,10 10
Current, I,N
mA
3-State Output
±10-4 ±1
Leakage Current,
0,5
0,5
±1
5
±10 4 ±2
0,10 0,10 10
lOUT
Input
7.5
pF
Capacitance, C in
7.5
5
5
Output
Capacitance, C out
10
15
15
10
-
-
-
-
-
-
-
-
Operating Current,
IDD1t
-
0,5
0,10
'TYPIcal values are for "one" T. = 25· C
and nominal Voo
-
-
5
10
-
5
10
10
20
-
5
-
10
mA
-
tOutputs open-cIrcUIted; cycle tIme = 2.5 /1S
161
RCA CMOS LSI Products
CDP1831, CDP1831C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input t" t, = 10 ns, CL = 50 pF, RL = 200kCl
TEST
CONDITIONS
CHARACTERISTIC
LIMITS
CDP1831
Vee
(V)
Access Time from
Address Change,
tAA
Access Time from
Chip Select,
tACS
Chip Select Delay,
tcs
Address Setup Time,
tAS
Address Hold Time,
tAH
Read Delay, tMRO
Chip Enable Output
Delay from Address,
tPAW
CDP1831C
UNITS
Mln.t Typ.· Max. Mln.t Typ.· Max.
850
350
1000
400
-
850
1000
-
-
700
250
600
200
800
300
-
700
800
-
-
-
600
-
-
-
-
-
300
100
-
5
10
-
5
10
5
10
5
10
5
10
5
10
-
-
-
200
70
-
50
150
-
500
150
-
-
300
500
-
-
-
500
200
200
100
-
600
250
350
150
-
500
600
-
-
200
-
-
-
-
50
25
150
75
5
10
5
10
5
10
tCA
Bus Contention Delay,
to
TPA Pulse Width,
= -40 to +85°C, Vee ±5%,
300
-
-
-
200
350
-
-
'tTl me reqUired by a limit device to allow for the indicated function.
'Time required by a typical device to allow for the indicated function. Typical values are for
T A = 25° C and nominal VDD.
MA
~
1\
HIGH ORDER '\
ADDRESS BYT E I
LOW ORDER
ADDRESS BYTE
~IAS~
'AA
'AH
F,PAW
TPA
.L
'MRij
~
"I
r----'AC~
K
CS
f4--'csBUS
CEO
I
HIGH IMPEDIINCE
OUTPUT
ACTIVE
r---'CA
--1:
'D-
--Jf
Fig. 2 - Timing waveforms.
162
VALID
I
92 M- 31 O!9R2
DATA
ns
1800-Serles Memories
CDP1831, CDP1831C
I
148-156
( 3.760-3.962)
92CM-3067!
Dimensions and pad layout for CDP1831CH chip.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10- 3
inch).
Note:
The dynamic characteristics and timing
diagrams indicate maximum performance
capability of the CDP183l. When used directly with a CDP1800-series microprocessor, timing will be determi.ned by the clock
frequency and internal delays of the
microprocessor.
The following general timing relationships
will hold when the CDP1831 is used with a
CDP1800-series microprocessor:
= 0.5 te
tPAW = 1 to
MAo occurs one clock period (tel earlier
than the address bits MAO-MA7.
1
where to =
CPU clock frequency
tAH
The photographs and dimensions represent a
chip when it is part of the wafer. When the wafer
is cut into chips, the cleavage angles are 57·
instead of 90· with respect to the face of the chip.
Therefore, the isolated chip is actually 7 mils
(O.17 mm) larger in both dimensions.
ORDERING INFORMATION
RCA Microprocessor device packages are
identified by letters indicated in the following chart When ordering a Microprocessor
device, it is important that the appropriate
suffix letter be affixed to the type number of
the device.
Package
Dual-In-Line Side-Brazed
Ceramic
Dual-In-Line Plastic
Chip
Suffix Letter
D
E
H
For example, a CDP183l in a dual-in-line
plastic package will be identified as the
CDP1831 E. A CDP1831 C chip will be identified as the CDP1831CH.
163
RCA CMOS LSI Products
CDP1832, CDP1832C
MA7
MA6
MA5
MA4
MA3
MA2
MAl
MAO
BUS 0
BUS I
BUS 2
VSS
24
VOO
AS
23
22
NC
4
21
NC
5
20
~
6
19
NC
7
18
NC
8
17
BUS7
9
16
BUSS
10
15
BUS 5
II
14
BUS 4
12
13
BUS 3
TOP VIEW
NC' NO CONNECTION
512-Word X 8-Blt Static
Read-Only Memory
Features:
• Compatible with CDP1800 and CD4000-series
devices
• Functional replacement for industry type
2704512 x 8 EPROM
• Three-state outputs
92CS-27579R2
TERMINAL ASSIGNMENT
The RCA CDP1832 and CDP1832C types
are 4096-bit mask-programmable CMOS
read-only memories organized as 512
words x 8 bits and designed for use in
CDP1800-series microprocessor systems.
(See PD30, "ROM Purchase Policy and
Data Programming Instructions.")
The CDP1832 ROM's are completely static;
no clocks are required.
A Chip-Select input (CS) is provided for
memory expansion. Outputs are enabled
when ~=O.
The CDP1832 is a pin-for-pin compatible
replacement for the industry types 2704
EPROM.
The CDP1832C is functionally identical to
the CDP1832. The CDP1832 has a
operating voltage range of 4 to 10.5 volts.
and the CDP1832C has a operating voltage
range of 4 to 6.5 volts.
The CDP1832 and CDP1832C are supplied
in 24-lead, hermetic, dual-in-line, sidebrazed, ceramic packages (0 suffix) and in
24-lead dual-in-line plastic packages (E
suffix). The CDP1832C is also available in
chip form (H suffix).
COU
COPI802
1/0
UCS-27580A3
Fig. 1 - Typical CDP1802 microprocessor system.
164
1800-Serles Memories
CDP1832, CDP1832C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS terminal)
CDP1832 ...................................................................... -0.5 to +11 V
CDP1832C ...................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA=-40 to +60°C (PACKAGE TYPE E) ............................................ 500 mW
For TA=+60 to +85°C (PACKAGE TYPE E) ............ Derate Linearly at 12 mV/oC to 200 mW
For TA=-55 to +100°C (PACKAGE TYPE D) · ......................................... 500 mW
For TA=+100 to 125°C (PACKAGE TYPE D) ........... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............... 100 mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPE D ............................................................ -55 to +125° C
PACKAGE TYPE E ............................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (T stg) ......................................... -65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 5 max.
. ............... +265°C
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum
reliability, operating conditions should be selected so that operation Is Illways within the
following ranges:
LIMITS
CDP1832
CDP1832C
Min.
Max.
Min.
Max.
4
10.5
4
6.5
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
VSS
VDD
VSS
I
UNITS
V·
VDD
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85 0 C, VDD ±5%, Except as noted
CONDITIONS
LIMITS
CDP1832
CHARACTERISTIC
Quiescent Device
Current, IDD
Output Low Drive
(Sink) Current, IOL
Output High Drive
(Source) Current, IOH
Output Voltage
Low-Level, VOL
Output Voltage
High Level, VOH
Input Low
Voltage, VIL
Input High
Vo
(V)
-
0.4
0.5
VIN VDD
(V) (V) Min.
5
5
10
10
0,5
5
0.55
0,10 10
1.30
-
0, 5
5
0,10 10
0, 5
5
0, 10 10
0, 5
5
- 0, 10 10
0.5,4.5 5
1,9
10
0.5,4.5 5
Voltage, VIH
1,9
10
Input Leakage
Any 0, 5
5
Current, liN
Input 0, 10 10
3-State Output Leakage
0, 5 0, 5
5
Current, lOUT
0, 10 0, 10 10
Input Capacitance,
CIN
Output Capacitance,
COUT
Operating Device
Current,
IDOl t
.
4.6
9.5
-
-0.35
-0.65
-
CDP1832C
UNITS
Typ.' Max. Min.
0.01
50
1
200
0.55
-
-
-
-
Typ.' Max
0.02 200
-
-
-
-
-
-
-
0
0.1
-
-
-
-0.35
-
0.1
0.1
-
-
4.9
5
-
-
-
-
1.5
3
3 ..5
-
1.5
-
-
-
0
0
5
10
-
3.5
7
-
-
-
±1
±2
±1
±2
-
-
±10 4
±10-4
±10-4
±10-4
-
5
7.5
-
5
7.5
15
4.9
9.9
-
-
-
-
-
-
-
10
15
-
10
-
0, 5
0, 10
5
10
-
5
10
10
20
-
-
,"5.
-
IJ.A
pF
-
TYPical values are for T A=25°C and nominal VDD.
V
-
±10-4 ±1
-
-
tOutputs open-circuited; cycle time=2.5
rnA
±10-4 ±1
-
-
IJ.A
-
5
10
-
rnA
165
RCA CMOS LSI Products
CDP1832, CDP1832C
MAO
MAl
MA2
MA3
MA4
MAe
MAS
1 - - -..... 8US7
I---I~S+BUSS
1-_ _",15+ auS5
512 X8
1----'1~4+BUS4
1---,:,:13+BUS3
1-_ _.:..:II+BUS2
~
+BUSI
I---":"+BUS 0
STORAGE
CELL
ARRAY
BUFFERS
AND
DECODERS
_ _l¥1
VDD - 24
Vss -12
FUNCTIONAL DIAGRAM
92CS- 27&81RI
Fig. 2 - Functional diagram.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VDD ±5%,
, Input t r ,t,=10 ns, CL=50 pF, RL =200 kQ
TEST
CONDITIONS
CHARACTERISTIC
LIMITS
CDP1832
CDP1832C
UNITS
VDD
(V)
Access Time From
Address Change. tAA
Access Time From Chip
Select. tACS
Min. Typ.· Max. Min. Typ.· Max.
850 1000
850 1000
400 500
400 550
400 550
200 250
200 250
200 250
100 130
-
5
10
5
10
5
10
Chip Select Delay. tcs
-
-
-
-
-
-
-
ns
• Time reqUired by a tYPical device to allow for the indicated function. Typical values are for
TA=25°C and nominal VOO.
MEMORY
ADDRESS
\I
J!~
"ES"
\
\,
BUS
HIGH
_lACS
;-+~gt~rE LOr
!-tCS
IMPEOA CE
I---'AA
V
VALID
DATA
92CS-31 05GR2
Fig. 3 - Timing waveforms.
OPERATING AND HANDLING
CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS
devices have a network for electrostatic
protection during handling. Recommended handling practices for CMOS
devices are described in ICAN-S5025
"Guide to Better Handling and Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum
supply voltage limit. care should be
taken to avoid or suppress power supply
turn-on and turn-off transients. power
supply ripple. or ground noise; any of
these conditions must not cause Vee-Vss
166
to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection Circuit. input signals should never
be greater than Vee nor less than Vss.
Input currents must not exceed 10 mA
even when the power supply is off.
Unused Inputs
A connection must be provided at every
input terminal. All unused input terminals must be connected to either Vee or
Vss. whichever is appropriate.
Output Short Circuits
Shorting of outputs to Vee or Vss may
damage CMOS devices by exceeding
the maximum device dissipation.
1800-Serles Memories
CDP1832, CDP1832C
I
148-156
( 3.760-3.9621
92CM-3067t
Dimensions and pad layout for CDP1832CH.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10- 3
inch).
The photographs and dimensions represent a
chip when it is part of the wafer. When the wafer
is cut into chips, the cleavage angles are 57·
instead of 90· with respect to the face of the chIp.
Therefore, the isolated chip is actually 7 mils
(0.17 mm) larger in both dimensions.
DIMENSIONAL OUTLINES
(D) SUFFIX
24-Lead Dual-In-!,.Ine Side-Brazed Ceramic Package
SYMBOL
A
C
D
F
G
·H
NOTES:
1. Loads within 0.006" (0.13 mm) radius of True Position
maximum material condition.
2. Centar to center of leads when formed parallel.
at
3. When this device is supplied solder dipped, the maximum
lead thickness (narrow portion) will not exceed 0.013"
(0.33mm).
J
K
L
M
P
N
INCHES
MIN:
MAX.
1.180
0.085
0.015
0.040
0.100
0.030
0.008
0.125
0.580
-
1.220
0.146
0.023
REF.
BSC
0.070
0.012
0.175
0.620
7·
0.025
0.050
24
NOTE
1
MILLIMETERS
MIN.
MAX.
29.98
30.98
2.16
3.68
0.39
0.68
1.02 REF.
2.54BSC
1.77
0.21
0.30
3.18
4.44
14.74
15.74
7·
0.64
1.27
24
o.n
3
2
92CS-30886R 1
167
RCA CMOS LSI Products
CDP1833, CDP1833C, CDP1833BC
I
24
2
23
22
21
MA7
MAS
MAS
MA4
MA3
MA2
3
4
5
S
MAl
7
MAO
BUSO
BUSI
BUS2
VSS
9
10
II
12
20
19
18
17
IS
15
14
13
8
VDD
TPA
CEl:
CMOS 1024-Word X 8-Blt Static
Read-Only Memory
CSI
CS2
mm
CEO
BUS7
BUSS
BUS5
BUS4
BUS3
TOP VIEW
92CS- 28889R2
Features:
• CDP1833BC Is compatible with the CDP1802BC 5 MHz microprocessor
• On-chip address latch
• Interfaces with CDP1800-series microprocessors without additional
components
• Optional programmable location within 64K memory space
• Three-state outputs
TERMINAL ASSIGNMENT
The RCA-CDP1833, CDP1833C, and CDP1833BC are static
8192-bit mask-programmable CMOS read-only memories
organized as 1024-words x8 bits and are completely static;
no clocks are required. They will directly interface with the
CDP1800-series microprocessors without additional
components.
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be
connected in a daisy chain to control selection of RAM
memory in a microprocessor system without additional
components.
The CDP1833C and CDP1833BC are functionally identical
to the CDP1833. The CDP1833 has a recommended
operating voltage range of 4 to 10.5 volts, and the CDP1833C
and CDP1833BC have a recommended operating voltage
range of 4 to 6.5 volts. The CDP1833BC is designed to
interface with the CDP1802BC microprocessor.
The CDP1833, CDP1833C, and CDP1833SC respond to a
16-bit address multiplexed on 8 address lines. Address
latches are provided on-chip to store the 8 most significant
bits of the 16-bit address. By mask option, this ROM can be
programmed to operate in any 1024-word block within 64K
memory space. Tile polarity of the high-address strobe
(TPA), CEI, CS1, and CS2 are user mask-programmable.
(See RPP-610, "Sales Policy and Data Programming
Instructions", for RCA Custom ROMs).
The CDP1833, CDP1833C, and CDP1833BC are supplied
in 24-lead hermetic dual-in-line side-brazed ceramic
package (D suffix) and 24-lead dual-in-line plastic package
(E suffix). The CDPf833C is also available in chip form (H
suffix).
CLEAR
WAIT
l~
NO-N2 MRD
ADDR BUS
TPB
TPA
Q
J>ATA
CPU
CDPISOO
SERIES
RAM
MRO
SCO SCI
~
I/O
CONTROl)
DMA-TN DMA:oui'
MWR
i'FI-m
HCIHIIIO.II
Fig. 1 - Typical CDP1800 Series microprocessor system.
168
)
1800-Serles Memories
CDP1833, CDP1833C, CDP1833BC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss terminal)
CDP1833 ....................................................................................................... -0.5 to +11 V
CDP1833C, CDP1833BC .........................................................•...•..........•..........•..... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ...................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............... " ........... " ..........................................•...... ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA =+60 to +85° C (PACKAGE TYPE E) ........................ , .................... Derate Linearly at 12 mV/o C to 200 mW
For TA = -55 to +1 OO°C (PACKAGE TYPE D) .......................................................................... 500 mW
For TA = +100 to 125°C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/oC to 200 mIN
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Packages) ..................................................... lor
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ..............................................................•............................ -55 to +120 _
PACKAGE TYPE E ..............................................................................................-40 to +85 0C
STORAGE TEMPERATURE RANGE (Tstg) ....•..........•............••.......•.................................. -65 to +1500C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max .................................................... +2650C
OPERATING CONDITIONS at TA = _40 0 to +85° C
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
CDP1833
CDP1833C, CDP1833BC
Min.
Max.
Min.
Max.
4
10.5
4
6.5
Vss
Voo
Vss
Voo
UNITS
V
BUS?
BUS6
BUS5
BUS4
BUS3
BUS2
BUSI
BUSO
92CS-28891R4
Fig. 2 - Functional diagram.
169
I
RCA CMOS LSI Products
CDP1833, CDP1833C, CDP1833BC
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ± 5%, Except as noted
CONDITIONS
LIMITS
CDP1833
CHABACTERISTIC
Quiescent Device Current
100
Input Capacitance
Output Capacitance
0.01
50
-
0.02
200
1
200
-
-
-
-
-
-
0
0.1
-
-
O.B
-
-
4.6
0, 5
5
-O.B
9.5
0, 10
10
-l.B
-
-
-
-
0, 5
5
-
0
0.1
VOL
-
0, 10
10
-
0
0.1
-
0, 5
5
4.9
5
VOH
-
0, 10
10
9.9
5
10
-
1.5
-
IOH
1,9
-
10
-
0.5,4.5
-
5
3.5
7
-
0.5,4.5
VIL
1,9
-
10
Any
0,5
5
Input
0,10
10
-
±10-4
. ±10-4
0, 5
0,5
5
0, 10
±10-4
±10-4
VIH
liN
-O.B
3
-
-
-
4.9
5
-
-
1.5
-
-
3.5
±1
±2
-
-
-
-
±10-4
±1
±10-4
±1
-
0, 10
10
-
±2
-
-
-
-
0,5
5
-
7
10
-
7
10
loo1t
-
0, 10
10
-
14
20
-
-
-
CIN
-
-
-
-
5
7.5
-
5
7.5
-
-
-
10
15
-
10
15
lOUT
Operating Device
Current
Max.
1.B
3-State Output
Current
Typ."
O.B
Input Leakage
Current
Min.
5
Input High
Voltage
-
-
Max.
10
Input Low
Voltage
5
10
Typ."
0,5
Output Voltage
High Level
5
10
Min.
CDP1833C, CDP1833BC UNITS
0,10
Output Voltage
Low-Level
-
Voo
(V)
0.5
IOL
Output High Drive
(Source) Current
Y,N
(V)
0.4
Output Low Drive
(Sink) Current
Vo
(V)
COUT
±1
pA
mA
V
pA
mA
pF
* Typical values are for TA = 25° C and nominal Voo.
t Outputs open-circuit; cycle time = 2.5ps.
8-81T 81 DIRECTIONAL DATA BUS
~J
~ ---ADM BUS
¥
-----
ADDR BUS
----
ROM
No.1
ROM
No.2
CDPI833
CDPlB33
~ -----
Mlil
CEO
ClFSfLECT
D
JJ
TPA
CS
ADM BUS
RAM
--CEI
~
CEO
iiRr>
C§
CS
SIGNAL
92C8~31973
Fig. 3 - Daisy chaining CDP1833's.
"Daisy Chaining" with CEI inputs and CEO outputs is used
to avoid memory conflicts between ROM and RAM in a user
system. In the above configuration, if ROM #1 was maskedprogrammed for memory locations 0000-03FF16 and ROM
170
#2 masked-programmed for memory locations 04001607FF16, for address from 0000-07FF16 the RAM would be
disabled and the ROM enabled. For locations above 07FF16
the ROM's would be disabled and the RAM enabled.
1800-Serles Memories
CDP1833, CDP1833C, CDP1833BC
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to =85 C, VDD
Input fr, tI = 10 ns, CL = 50 pF, RL = 200 kO
0
± 5%,
LIMITS
TEST
CHARACTERISTIC
CDP1833
CONDITIONS
tM
Access Time From
tAcs
tcs
Chip Select Delay
Address Setup Time
tAs
Address Hold Time
tAH
Read Delay
tMAO-
Chip Enable Output
Delay from Address
tCA
Bus Contention Delay
to
tPAW
TPA Pulse Width
Chip Enable In to
Chip Enable Out
Delay
tCEIO
775
-
650
775
425
-
-
500
625
500
625
10
275
310
5
-
250
320
10
-
125
180
-
5
75
50
-
75
-
-
-
100
75
10
5
Chip Select
650
350
-
5
Address Change
CDP1833BC
UNITS
Mln.# Typ •• Max. Mln.# Typ •• Max. Mln.# Typ •• Max.
VDD (V)
Access Time From
CDP1833C
-
-
250
320
-
-
575
-
-
-
250
320
-
75
50
-
-
10
40
25
5
100
75
10
50
30
-
-
-
-
5
400
500
-
400
500
10
-
200
275
-
-
5
-
120
170
120
170
10
-
70
100
-
-
5
-
220
270
220
270
10
-
130
150
-
-
-
200
-
-
175
50
-
475
600
-
-
75
50
-
700
-
400
-
500
-
-
120
170
-
-
220
270
-
5
200
10
70
-
-
-
5
-
200
250
-
-
200
250
-
200
250
10
-
100
150
-
-
-
-
-
-
-
ns
I
# Time required by a limit device to allow for the indicated function.
• Time required by a typical device to allow for the indicated function. Typical values are for
TA = 25 0 C and nominal voltages.
MA
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
~tAS~
F'PAW
----..
'AA
'AH
TPA
L
1\
~I
- 'MRli
I
'ACS
CS
--'CSBUS
CEO
I
HIGH IMPEDANCE
OUTPUT
ACTIVE
'0---1:
--~
VALID
DATA
I
r--'CA
92CM 31Q39R2
Fig. 4 - Timing waveforms.
171
RCA CMOS LSI Products
CDP1833, CDP1833C, CDP1833BC
92CL-31030
Dimensions and pad layout for CDP1833CH.
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3
inch).
The photographs and dimensions represent a
chip when it is part of the wafer. When the wafer
is cut into chips, the cleavage angles are 57"
instead of 90· with respect to the face of the chip.
Therefore, the isolated chip is actually 7 mils
(0.17 mm) larger in both dimensions.
Note:
The dynamic characteristics and timing diagrams indicate
maximum performance capability of the COP1833. When
used directly with a COP1800-series microprocessor, timing
will be determined by the clock frequency and internal
delays of the microprocessor.
The following general timing relationships will hold when
the COP1833 is used with a COP1800-series microprocessor.
tAH" 0.5 te
tPAW = 1 te
MRD occurs one clock period (te) earlier than the address
bits MAO-MA7.
where te = - - - - - - - CPU clock frequency
172
ORDERING INFORMATION
RCA Microprocessor device packages are identified by
letters indicated in the following chart. When ordering a
Microprocessor device, it is important that the appropriate
suffix letter be affixed to the type number of the device.
Package
Suffix Letter
Oual-in-Line Side Brazed Ceramic
0
E
Oual-in-Line Plastic
Chip
H
For example, a COP1833 in a dual-in-line plastic package
will be identified as the COP1833E. A COP1833C chip will
be identified as the COP1833CH.
1800-Serles Memories
CDP1834, CDP1834C
MAT
r:----....r--=. Voo
MAe
MAt
He:
CIII
MAe
MAli
MA4
IIIAIi
MA2
IIIAI
MAO
eS2
lUST
BUS 0
IUSI
IIUS4I
BUSS
1028-Word X 8-Blt Static
Read-Only Memory
He
BU112
BUS4
Vss
BUsa
TOP VIEW
F••tur••
• Industry pin compatible
• Three-state outputs
He • NO CONNECTION
IICI-UrlT
CDP1834, CDP1834C
TERMINAL ASSIGNMENT
The RCA-CDP1834 and CDP1834C are 8192-bit maskprogrammable CMOS read-only memories organized as
1024-words x 8-blts and designed for use In CDP1800series microprocessor systems. The CDP1834-series ROM's
are completely static; no clocks are required.
Two-Chip-Select Inputs (CS1, CS2) are provided for memory
expansion. The polarity of each Chip-Select is user maskprogrammable. (See PD30. "ROM Purchase Policy and
Data Programming Instructions"). The CDP1834-serles is
pin-compatible with industry type 2708 EPROM. The
CDP1834C is functionally Identical to the CDP1834. The
CDP1834 has a recommended operating voltage range of 4
to 10.5 volts and the CDP1834C has a recommended
operating voltage range of 4 to 6.5 volts. The CDP1834 and
the CDP1834C are supplied In 24-lead dual-in-line ceramic
packages (0 suffix) and in 24-lead dual-In-line plastic
packages (E suffix). The COP1834C Is also available in chip
form (H suffix).
ADDRESS
LATCH
RAM
1/0
92CM-32226
Fig. 1 - Typical CDP1802 microprocessor system.
173
I
RCA CMOS LSI Products
CDP1834, CDP1834C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD):
(All voltage values referenced to VSS terminal)
CDP1834 .......................................................................................... , ............ 0.5 to +11 V
CDP1834C ..................................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .................................................................. , ..... , -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................. ±10 rnA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +600 C (PACKAGE TYPE E) .............................................................................. 5Cio mW
ForTA = +60 to +85°C (PACKAGE TYPE E) ................................................. Derate Linearly at 12
to 200 mW
For TA = -55 to +1000C (PACKAGE TYPE D) ............................................................................ 500 mW
ForTA = 100 to +125°C (PACKAGE TYPE D) ................................................ Derate Linearly at 12
to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE ..................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 .............................................................................................. -55 to +125°C
PACKAGE TYPE E ............................................................................................... -40 to +85"C
STORAGE TEMPERATURE RANGE (Tstg) •.••••.••.••.•••..••.••.•.•...•••.••••••..•.••.•••••••••••••••••••••••••••• -65 to +15O"C
LEAD TEMPERATURE (DURING SOLDERING):
.
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max........................................................ +285°C
mwrc
mwrc
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD 5%, Except as noted
CHARACTERISTIC
Quiescent Device Current
Output Low. Drive
(Sink). Current
Output High Drive
(Source) Current
Output Voltage Low-Level
Output Voltage High Level
Input Low Voltage
Input High Voltage
Input Leakage Current
3-State Output
Leakage Current
Input Capacitance
Output Capacitance
Operating Device Current
CONDITIONS
Vo
VIN
VDD
(V)
(V)
(V)
5
5
100
10
10
0.4
0,5
5
0,10
10
0.5
IOL
0,5
4.6
5
9.5
0,10
10
IOH
0,5
5
VOL
0, 10
10
0,5
5
VOH
0, 10
10
0.5,4.5
5
VIL
1,9
10
5
VIH 0.5,4.5
1 9
10
Any
0,5
5
liN
Input
10
0, 10
0,5
5
5
0, 10
10
10
lOUT
CIN
COUT
0,5
5
IDD1t
0, 10
10
-
-
-
-
-
'Typical values are for T A = 25° C and nominal VDD.
tOutputs open-circuited; cycle time = 2.5 ps.
174
-
LIMITS
CDP1834
CDP1834C
Typ.·
Min.
Typ.·
Max.
Min.
Max.
0.01
50
0.02
200
1
200
0.8
0.8
1.8
-0.8
-0.8
-1.8
0.1
0
0.1
0
0
0.1
4.9
5
4.9
5
10
9.9
1.5
1.5
3
3.5
3.5
7
±1
±1
±2
±1
±1
±2
7.5
5
7.5
5
15
15
10
10
10
7
7
10
20
14
-
-
-
-
-
-
--
-
-
-
-
-
-
-
-
-
-
---
-
-
UNITS
pA
-
mA
-
-
-
V
-
-
-
pA
pF
mA
1800-Series Memories
CDP1834, CDP1834C
OPERATING CONDITIONS at T A = Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the foflowing ranges:
~AIIa
CHARACTERISTIC
CDP1834
Min.
4
VSS
DC Operating Voltage Range
Input Voltage Range
TEST
CONDITIONS
VOO
(V)
Access Time from Address Change,
tAA
Access Time from Chip Select,
tACS
Chip Select Delay,
tcs
UNITS
V
=-40 to + as·C. VDD ± 5%, Input Ir, tf =10 ns, CL =50 pF, RL =200 kn
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
CHARACTERISTIC
CDP1834C
Min.
Max.
4
6.5
VSS
VDD
Max.
10.5
VDD
5
10
5
10
5
10
LIMITS
CDP1834
CDP1834C
UNITS
Min.
-
-
-
Typ."
575
350
600
325
480
250
Max.
750
425
700
410
580
340
Min.
-
Typ."
575
Max.
750
-
-
600
700
-
-
-
480
580
-
-
-
ns
ns
I
ns
'Typical values are for T A = 25·C and nominal VDD.
OUTPUTS
ACTIVE
VALID DATA
92CS-Z8915RI
Fig. 2 - Timing waveforms.
MAO
MAl
MA2
MA3
MA4
MA5
MA6
1024 X 8
STORAGE
CELL
ARRAY
OUTPUT
BUFFERS
17
16
15
14
13
II
10
9
BUS7
BUS6
BUSS
BUS4
BUS3
BUS2
BUSI
BUS 0
E
Voo • 24
Vss ·12
92CS-28914R~
Fig. 3 - Functional diagram.
175
RCA CMOS LSI Products
CDP1834, CDP1834C
Dimensions and pad layout for CDP1834CH chip.
Dimensions in parentheses are In millimeters and
are derived from the basic inch dimensions as
indicated. Grid graduations are in mils (10-3 Inch).
The photographs and dimensions of each CMOS
chip represent a chip when It Is part of the wafer.
When the wafer is cut Into chips. the cleavage
angles are 67" Instead of 90° with respect to the face
of the chip. Therefore. the isolated chip lsactually 7
mils (0.17 mm) larger In both dimensions.
OPERATING. HANDLING CONSIDERATIONS
1. Handling
All Inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling pratlces for CMOS devices
are described In ICAN-6525 "Guide to Better Handling
and Operation of CMOS Integrated Circuits".
2. Operating
Operating Voltage
During operation near the maximum supply voltage
limit. care should be· taken to avoid or suppress power
supply turn-on and turn-off transients. power supply
ripple. or ground noise; any of these conditions must
not cause VOO - VSS to exceed the absolute maximum
176
rating.
Input Signall
To prevent damage to the Input protection circuit. Input
signals should never be greater than VOO nor less than
VSS. Input currents must not exceed 10 mA even when
the power supply Is off.
Unused Inpull
A connection must be provided at every Input terminal.
All unused input terminals must be connected to either
VOO or VSS. whichever is appropriate.
Output Short Clrcultl
Shorting of outputs to VOO orVss maydamageCMOS
devices by exceeding the maximum device dissipation.
1800-Serles Memories
Objective Data
MA7
MA6
MA5
MA4
MA3
MA2
MAl
MAO
BUSO
BUSI
BUS2
vss
I
2
3
4
5
6
7
8
zo
Voo
TPA
CEl:
CSI
CS2
19
18
17
16
15
14
13
CEO
BUS7
BUSS
BUS5
BUS4
BUS3
24
23
22
21
9
10
II
12
m
TOP VIEW
92CS-"I88
CDP1835C
CMOS 2048-Word X 8-Bit Static
Read-Only Memory
Features:
• Compatible with CDP1800- and CD4000-serles
devices
• On-chip address latch
• Interfaces with CDP1800-series microprocessors
(fCl :5 5 MHz) without additional components
• Optional programmable location within 64K
memory space
• 3-state outputs
Terminal AIIlgnmenl
The RCA CDP1835C is a 16384-bit mask-programmable
CMOS read-only memory organized as 2048 words x 8 bits
and is completely static; no clocks required. It will directly
interface with CDP1800-series microprocessors that have
clock frequencies up to 5 MHz without additional
components.
The CDP1835C responds to l6-bit address multiplexed on 8
address lines. Address latches are provided on-chip to store
the 8 most significant bits of the l6-bit address. By mask
option, this ROM can be programmed to operate in any
2048-word block of 64K memory space. The polarity of the
high address strobe (TPA), CEI, CSl and CS2 are user
mask-programmable.
RAM
(See Data Programming Instructions in this data sheet.)
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be connected in a daisy chain to control selection of RAM memory
in a microprocessor system without additional components.
The COP1835C has a recommended operating voltage
range of 4 to 6.5 volts.
The COP1835C is supplied in 24-lead hermetic dual-in-line
side-brazed ceramic packages (0 suffix) and 24-lead dualin-line plastic packages (E suffix).
CPU
CDPl800
ItO
SERIES
92CM-331'2RI
Fig. 1 '- Typical CDP1800 Series microprocessor system.
177
I
RCA CMOS LSI Products
CDP1835C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All voltage values referenced to V•• terminal)
CDP1835C ........................................................................................................ -0.5 to + 7 V
INPUT VOLTAGE RANGE, ALL INPUTS .........................................................................-0.5 to VOD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................................................± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to + 60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For T. = +60 to +85° C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mW/oC to 200 mW
For T. = -55 to + 100° C (PACKAGE TYPE D) .. , ........................................................................ 500 mW
For T. = + 100 to + 125°C (PACKAGE TYPE D) .......................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE ..................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 .... " .. , ..................................................................................... -55 to + 125° C
PACKAGE TYPE E ............................................................................................... -40 to + 85° C
STORAGE TEMPERATURE RANGE (Tot.) .......................................................................... -65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
OPERATING CONDITIONS at T. = Full Package Temperature
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CDP1835C
CHARACTERISTIC
MIN.
4
V••
DC Operating Voltage Range
Input Voltage Range
UNITS
MAX.
6.5
17
MA7
16
MA6
MA5
ADDRESS
MA4
CONTROL
CIRCUIT,
AND
DECODER
15
LATCH.
MA3
14
2048x8
STORAGt:
ARRAY
OUTPUT
BUFFERS
BUS 6
BUS 5
BUS 4
MA2
BUS 2
MAl
BUS 1
MAO
BUS 0
TPA
24
12
.vD D
~ VSS
92CM-35t10
Fig. 2 -
178
BUS 7
I~ BUS 3
MRD
0
0
V
Vee
Functional diagram.
1800-8erles Memories
CDP1835C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ± 5'010, except as noted
TEST
LIMITS
CONDITIONS
CHARACTERISTIC
CDP1835C
Vo
VIN
Voo
TYP."
(V)
(V)
(V)
MIN.
Quiescent Device Current
5
5
5
100
Output Low Drive (Sink) Current
0.4
0,5
0.8
1.6
5
10L
-1.6
4.6
Output High Drive (Source Current)loH
5
-0.8
0,5
Output Voltage Low-Level
0,5
0
5
VOL
Output Voltage High-Level
4.9
0,5
5
5
VOH
Input Low Voltage
0.5,4.5
5
VIL
Input High Voltag'e
3.5
0.5,4.5
5
VIH
Input Leakage Current (Any Input) lIN
0,5
5
3-State Output Leakage Current lOUT
0,5
0,5
5
Input Capacitance
5
CIN
Output Capacitance
COUT
10
Operating Device Current
0,5
5
5
lOPER-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
MAX.
50
0.1
1.5
±1
±2
7.5
15
10
pA
mA
V
V
pA
pF
mA
'Typical values are for T. = 25° C and nominal Voo .
• Outputs open circuited; cycle time = 1 ps.
I
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input t" tf = 10 ns, CL = 100 pF, 1 TTL Load
= -40 to +85° C,
TEST
CONDITIONS
Voo (V)
CHARACTERISTIC
Access Time from Address Change
Chip Select Delay
Address Setup Time
Address Hold Time
Output Active from f.i11rn
Output Valid from MRl5
Output Active from TJ5A
Output Valid from TPA
Chi,Q,Enable Output Delay from Address
Bus Contention Delay
TPA Pulse Width
Chip Enable In to Chip Enable Out Delay
Voo ±5%,
t.A
tC$
tAS
tAH
tMRO'
tMRD2
ITPA.
hpA2
teA
to
tPAW
IcEIO
5
5
5
5
5
5
5
5
5
5
5
5
MIN.t
LIMITS
CDP1835C
TYP."
-
-
50
70
125
-
UNITS
MAX.
-
550
200
-
-
-
100
600
100
60
100
200
ns
100
'Typical values are for T. = 25°C and nominal Voo.
tTime required by a limit device to allow for the indicated function.
179
RCA CMOS LSI Products
CDP1835C
LOW. ORDER
A OORESS BYTE
MA
TPA
CS
BUS ________~H~IG~H~I~M~P~EO~A~N~CE~_+------------~
VALID
OATA
CEO
CEl:
Fig. 3 -
Timing waveforms.
Note:
the CDP1835C is used with a CDP1800-series microprocessor.
tAH = 0.5 te
tPAW = 1.0 tc
MR15 occurs one clock period (te) earlier than the address bits MAO-MA7.
1
where te = CPU clock frequency
The dynamic characteristics and timing diagrams indicate
maximum performance capability of the CDP1835C. When
used directly with a CDP1800-series microprocessor, timing will be determined by the clock frequency and internal
delays of the microprocessor.
The following general timing relationships will hold when
II
8-BIT BIOOIRECTIONAL DATA BUS
lJ
~ --ADOR BUS
---
---
AOOR BUS
---
---
ROM
ROM
COPI83l1C
COPI83l1C
~ --:---
AOOR BUS
~
RAM
"'.2
"'.1
RIll)
CEI
CEO
OF SELECT
lJ
TAA
---CEO
II1II)
a
CS
CS
SIGNAL
!l2CS-33ItoRI
Fig. 4 -
Daisy chaining CDP1835C.
"Daisy Chaining" with CEI inputs and CEO outputs is used
to avoid memory conflicts between ROM and RAM in a user
system. In the above configuration, if ROM No. 1 was
masked-programmed for memory locations 0000-07FF,e
and ROM No.2 masked-programmed for memory locations
180
0800wOFFF,e, for addresses from OOOo-OFFF,., the RAM
would be disabled and the ROM enabled. For locations
above OFFF", the ROMS s would be disabled and the RAM
enabled.
1800-Serles Memories
CDP1835C
ROM ORDERING INFORMATION
All RCA mask-programmable ROM s are custom-ordered
devices. ROM program patterns can be submitted to RCA
by using master device (ROM, PROM or EPROM), a floppy
diskette generated on an RCA development system, or
computer punch cards.
check one
For detailed instructions, refer to the ROM Information
Sheet for the CDP1835C and publication "Sales Policy and
Data Programming Instructions," RPP-610. (Note polarity
options, columns 41 and 42, Part B, on the CDP1835C ROM
Information Sheet must be blank).
ROM INFORMATION SHEET
How is ROM pattern being submitted to RCA?
Computer Cards
0 (Complete part B, C, and D)
Floppy Diskette
0 (Complete parts A, B, C, D, and F)
Master Device (PROM)
0 (Complete parts A. B, C, D. and E)
Customer Name (start at left)
c(
I-
a:
6-30
35-54
Address or Division
c(
0.
59-63
65-71
ID
I-
a:
:
ROM Type (without COP prefix), e.g. 1835C
%
Pin
Functions
CDP1835C
Polarity Options
P
o
a:
:
=
=
CS2
PNX
PNX
N
X
PX
PN
PNX
PNX
PNX
PNX
PNX
28
29
30
31
32
34
36
37
38
39
40
C
I-
Positive or Negative Logic?
POS or NEG
W
I-
a:
:
Starting and last address
of data block in the
Master Device (in Hex).
0.
If a diskette is submitted, check type of
RCA Development System used:
o CDP18S005
II.
I-
a:
c(
0.
IIIII
III I I
42
I I I I I
c(
If a master device is submitted,
state type of ROM/PROM:
41
A9
Starting address of ROM pattern in Hex.
a:
I I I
I
=
CS1
Column #
I-
Circle one letter (P, N, or X)
In each column (Single Letter Indicates No Choice)
active when logic 1, N active when logic 0, X don't care
A11
A10
A12
TPA
A15
A14
A13
CEI
Specify: Track #
[TI
Software program used:
(Check one)
o ROM SAVE
o SAVE PROM
o
o
CDP18S007
CDP18S008
Specify: File Name:
(check one)
o MEM SAVE
o SAVE PROM
181
RCA CMOS LSI Products
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5
T
PI
01/ A -r
AT
1 00 12
1+'0
335C
100 I 0 0000000
)/ £ X f/ 0:'
Ff£f
3' D
ro
1
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TIO'"
0
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r r,4
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92Cl-35253
Sample Card-Deck Printout
Floppy-Diskette Method
Master-Device Method
The diskette contains the ROM address and data information. Title, option, and data-format information, which
would otherwise be punched on computer cards, must be
submitted on the ROM Information Sheet. In addition,
specify the RCA Development System used to generate the
diskette (CDP18S005, CDP18S007, or CDP18S008) and
supply a track number or file name, If possible, include a
printout of the program for verification purposes. The
format of the address and data information is essentially the
same as that shown on the Sample Card-Deck Printout with
the addition of a carriage-return character at the end of
each line and an end-of-file character (DC3) at the end of
the file.
Data may be submitted on a master ROM, PROM, or
EPROM device. Title, option, and data-format information,
which would otherwise be punched on computer' cards,
must be submitted on the ROM Information Sheet. In
addition, specifiy the master device type; RCA will select
I ntel types 1702, 2332A. 2704, 2708, 2716, 2732, 2758,
Supertex CM3200, TI 4732, Motorola MCM68732, and
Motorola MCM68A332, or their equivalents as well as RCA
type CDP18U42. If more than one ROM pattern is stored in
the master device, the starting address and size of each
pattern must be stated on separate ROM Information
Sheets. If the master-device is smaller than 2K bytes, the
starting address of each master-device must be clearly
identified.
182
1800-Serles Memories
CDP1837C
Objective Data
MA7
MA6
MA5
MM
MA3
MA2
MAl
MAO
BUS 0
BUSI
BUS2
VSS
I
2
3
4
5
6
7
24
23
22
21
VDD
20
TPA
CEL
CSI
CS2
19
18
17
16
15
14
13
CEO
BUS7
BUSS
BUS5
BUS4
BUS3
8
9
10
II
12
MAll
TOP VIEW
~2CS·
4096-Word X 8-Bit Static
Read-Only Memory
28889R2
Features:
• On-chip address latch
• Interfaces with CDP1800-series microprocessors
(fclock :5 5 MHz) without additional components
• Optional programmable location within 64K memory space
• Three-state outputs
TERMINAL ASSIGNMENT
The RCA-CDP1837C is a 32768-bit mask-programmable
CMOS read-only memory, organized as 4096 words x 8 bits
and is completely static: no clocks required. It will directly
interface with CDP1800-series microprocessors, having
clock frequencies up to 5 MHz, without additional
components.
The CDP1837C responds to a 16-bitaddress multiplexed on
8 address lines. Address latches are provided on chip for
storing the high byte address data. By mask option, this
ROM can be programmed to operate in any 4096-word
block of 64-K memory~ce. The polarity of the high
address strobe (TPA), MRD, CEI, CS1, and CS2 are user
mask-programmable.
RAM
(See RPP-610, "Sales Policy and Data Programming
Instructions", for RCA custom ROM's).
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be connected
in a daisy chain to control selection of RAM memory in a
microprocessor system without additional components.
The CDP1837C has a recommended operating voltage
range of 4 to 6.5 volts.
The CDP1837C is supplied in 24-lead heremetic dual-inline side-brazed ceramic packages (D suffix) and 24-lead
dual-in-line plastic packages (E suffix).
cPU
CDPl800
SERIES
I/O
92CM-3S120
Fig. 1 - Typical CDP1800 Series microprocessor system.
183
I
RCA CMOS LSI Products
CDP1837C
MAXIMUM RATING, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All voltages referenced to Vss terminal)
CDP1837C .......................................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................................................... -0.5 to voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ........ , ........................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60° C (PACKAGE TYPE E) ............................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE EJ ................................................. Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100°C (PACKAGE TYPE OJ .............................................................................. 500 mW
For TA = +100 to +125°C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForTA = FULL PACKAGE-TEMPERATURE RANGE ....................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ...................................... , ...... , ... , .. , ... , ................................•...•. -55 to +125'C
PACKAGE TYPE E .................................................................................................-40 to +85'C
STORAGE TEMPERATURE RANGE (Tstg) .............................................................•............. -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265'C
OPERATING CONDITIONS at TA = FULL PACKAGE-TEMPERATUREftANGE
For maximum reliability, nominal operating conditions should be selected so that operation is always within the
following ranges:
LIMITS
CDP1837C
CHARACTERISTIC
MIN.
Supply-Voltage Range
UNITS
MAX.
4
6.5
Vss
Voo
V
Recommended Input Voltage Range
MA7
I
MA6
2
MAS
ADDRESS
LATCH,
CONTROL
CIRCUIT
AND
DECODER
17
4096. e
MEMORY
ARRAY
OUTPUT
BUFFERS
BUSI
.5
BUS!
MA4
.4
BUS 4
MAO
.3
Bun
MA2
".0
BUS2
MAt
MAO
sus.
BUSO
23
19
TPA----.J
ii1f6-----....J
OE
g2eM-3512'
Fig. 2 - Functional block diagram.
184
BUS7
.6
1800-Serles Memories
CDP1837C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo ± 5%, except al noted
LIMITS
CONDITIONS
CHARACTERISTIC
CDP1837C
UNITS
Vo
(V)
VIN
(V)
Voo
(V)
Min.
Typ,*
Max.
-
5
50
/1A
mA
Quiescent Device Current.
100
-
0,5
5
Output Low Drive (Sink) Current
10l
0.4
0,5
5
0.8
1.6
-1.6
-
Output High Drive (Source) Current
10H
4.6
0,5
5
-0.8
Output Voltage Low-Level
VOL
-
0,5
5
-
0
0.1
Output Voltage High-Level
VOH
-
0,5
5
4.9
5
-
Input Low Voltage
Vil
0.5,4.5
5
-
VIH
0.5,4.5
5
3.5
-
1.5
Input High Voltage
-
Input Current
liN
-
0,5
5
lOUT
0,5
0,5
5
-
±1
3-State Output Leakage Current
-
±2
Operating Current, 1 MHz
1001-
-
0,5
5
-
5
10
CIN
-
-
-
-
5
7.5
COUT
-
-
-
-
10
15
Input Capacitance
Output Capacitance
V
/1A
•
mA
pF
"Typical values are for TA = 25°C and nominal VoD.
-Outputs open circuited; cycle time 1/1s.
8-BIT BIDIRECTIONAL DATA BUS
~
ADDR BUS
~J
--------ROM
No.1
CDPl837C
~ --CM>SELECT
SIGNAL
cs
CEO
~1
TPA
AODR BUS
-
1
----ROM
No.2
CDPI837C
CEI
---
CEO
CS
ADOR BUS
~
-
RAM
a
92CS-3~122
Fig. 3 - Daisy chaining CDP1837C's.
"Daisy Chaining" with CEI inputs and CEO outputs is used
to avoid memory conflicts between ROM and RAM ina user
system. In the above configuration, if ROM No. 1 was
masked-programmed for memory locations 0000-07FF16
and ROM No.2 masked-programmed for memory locations
0800,6-0FFF,6, for addresses from 0000-OFFF16, the RAM
would be disabled and the ROM, enabled. For locations
above OFFF16, the ROM's would be disabled and the RAM
enabled.
185
RCA CMOS LSI Products
CDP1837C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input tr, It = 10 ns, CL = 100 pF, and 1 TTL Load
=-40 to +85°C, VDD +5%,
LIMITS
CHARACTERISTIC
CDP1837C
CONDITIONS
VDD (V)
Mln.#
Max.
Access Time from Address Change
IAA
5
tcs
5
-
550
Chip Select Delay
Address Setup Time
lAs
5
50
Address Hold Time
tAH
5
70
-
Read Delay
tMRb
5
-
200
Chip Enable Output Delay from Address
tCA
5
-
100
Bus Contention Delay
to
5
-
200
TPA Pulse Width
tPAW
5
125
Chip Enable In to Chip Enable Out Delay
tCEIO
5
-
.
UNITS
200
ns
100
# Time required by a limit device to allow for the indicated function.
MA
LOW ORDER
ADDRESS BYTE
I - - - - I A A --------I~
TPA
AH
cs
BUS--------~~~~~~-+------------~
VALID DATA
CEO
CEI.
92CM-35123
Fig. 4 - Timing diagram.
Note:
The dynamic characteristics and timing diagrams indicate
maximum performance capability of the CDP1837C. When
used directly with a CDP1800-series microprocessor, timing
will be determined by the clock frequency and internal
delays of the microprocessor.
The following general timing relationships will hold when
the CDP1837C is used with a CDP1800-series
microprocessor.
tAH = 0.5 te
tPAW = 1.0 te
MRD occurs one clock period (te) earlier than the
address bits MAO-MA7.
1
where te =
CPU clock frequency
186
1800-Series Memories
CDP1837C
ORDERING INFORMATION
RCA Microprocessor device packages are identified by
letters indicated in the following chart. When ordering a
Microprocessor device, it is important that the appropriate
suffix letter be affixed to the type number of the device.
Package
Suffix Letter
D
Dual-in-Line Side Brazed Ceramic
Dual-in-Lirie Plastic
E
Forexample, a CDP1837AC in a dual-in-line plastic package
will be identified as the CDP1837ACE.
ROM Ordering In'ormatlon
All RCA mask-programmable ROM's are custom ordered
devices. ROM program patterns can be submitted to RCA
by using a master device (ROM, PROM, or EPROM), floppy
diskette generated on a RCA Development System, or
computer punch cards.
For detailed instructions refer to the ROM Information
Sheet for the CDP1837C and publication RPP-610 "Sales
Policy and Data Programming Instructions" for RCA custom
ROM's. (Ndte: Polarity options, columns 40,41, and 42 on
the CDP1837C ROM Information Sheet must be left blank).
ROM Information Sheet
How is ROM pattern being submitted to RCA?
check one Computer Cardl
[J (Complete parts B, C, and D)
Floppy Dllkette
[J (Complete parts A, B, C, D, and F)
Malter Device (PROM) [J (Complete parts A, 8, C, D, and E)
CUltomer Name (Itart at left)
c
I-
a::
C
Q.
III
I-
a::
C
Q.
6-30
I I I I I I I I I IJJJIlilJJI1JilJ
35-54
I I I I I I I I I I I I I I I I I I I I
59-63
I 1/ I I
65-71
1/ I I I "
%
l-
a::
c
ROM Type (without CDP prefix)
CSl
CS2
MRD
-
CEl
TPA
A15
A14
A13
A12
PNX
PNX
P,N
X
PX
PN
PNX
PNX
PNX
PNX
28
29
30
31
32
34
36
37
38
39
Column #
(J
RCA Custom Number
Circle one letter (P, N, or X) In each column.
(A single letter Indicates no choice)
P =active when logic 1, N =active when logic 0, X =don't care
Pin
Functions
CDP1837C
Polarity Options
Q
Positive or Negative Logic?
pas or NEG
a::
a::
C
Q.
Starting and last address
of data block in the
Master Device (in Hex).
II III
IIIII
A9
40
41
42
If a diskette is submitted, check typ~ of
RCA Development System used.
[J
1&1
I-
Al0
IIII I
C
Q.
If a master device is submitted,
state type or ROM/PROM:
All
Starting address of ROM pattern in Hex.
I-
OIl
II.
•
Addre.. or Division
Ii.
CDP18S005
rn
I-
C
Software program used:
(check one)
o ROM SAVE
[J SAVE PROM
a::
Q.
CDP18S007
CDP18S008
Specify: File Name:
Software program used:
(check one)
[J MEM SAVE
o SAVE PROM
[J
Specify: Track #
[J
---
187
RCA CMOS LSI Products
188
1800-Serles Memories
1800-Series Pheripherals
Technical Data
II
189
RCA CMOS LSI Products
CDP1851, CDP1851C
Yeo
CLOCK-
CS·
CMOS Programmable 1/0 Interface
Relit!
RAO
WR/Jif
RAI
BUSO
BUSI
BUS2
BUS!
TPB
A ROY
A STROBE
AO
AI
aUS4
BUSS
au..
A4
A.
eUS7
CC£lJi'
13
AIll1'
"
iiNT+- 15
8 ROY
AI
..
A1
B7
16
B.
B.
B'
B STROBE
BO
BI
Yss
B2
TOP VIEW
92CS-31926
TERMINAL ASSIGNMENT
Feature.:
• 20 Programmable I/O Lines
• Programmable for Operation In Four Modes:
Input
Output
Bidirectional
Bit-programmable
• Operates in Either I/O or Memory Space
The RCA CDP1851 and CDP1851C are CMOS programmable two-port II0s designed for use as general-purpose
1/0 devices. They are directly compatible with CDP1800
series microprocessors functioning at maximum clock
frequency. Each port can be programmed in either byte-1I0
or bit-programmable modes for interfacing with peripheral
devices such as printers and keyboards.
Both ports A and B can be separately programmed to be 8
bit input or output ports with handshaking control lines,
ROY and STROBE. Only port A can be programmed to be a
bidirectional port. This configuration provides a means for
communicating with a peripheral device or microprocessor
system on a single 8 bit bus for both transmitting and
receiving data. Handshaking signals are provided to
maintain proper bus access control. Port A handshaking
lines are used for input control and port B handshaking
lines are used for output; therefore port B must be in the
bit-programmable mode where handshaking is not used.
Ports A and B can be separately bit programmed so that
each individual line can be designated as an input or output
line. The handshaking lines may also be individually
programmed as input or output when port A is not in
bidirectional mode.
The CDP1851 has a supply-voltage range of 4 to 10.5 V, and
the CDP1851C has a range of 4 to 6.5 V. Both types are
supplied in 40-lead dual-in-line plastic (E suffix) or hermetic
ceramic (0 suffix) packages. The CDP1851 C is also available
in chip form (H suffix).
CDP1851 Programming Mod••
Mod.
Input
Output
Bidrectional
(Port A only)
BitProgrammable
190
(8)
PortA
Data Pin.
Accept input data
Output data
Transfer inpuV
output data
Programmed
individually as
inputs or outputs
(2)
(8)
PortA
Port B
Dala Pin.
Accept input data
Hand.haklng Pin.
READY, STROBE
READY, STROBE
Input handshaking
for Port A
Programmed
individually as
inputs or outputs
Output data
Must be
previously set to
bit-programmable mode
Programmed
individually as
inputs or outputs
(2)
Port B
Hand.haklng Pin.
READY, STROBE
READY, STROBE
Output handshaking
for Port A
Programmed
individually as
inputs or outputs
1800-Series Peripherals
CDP1851, CDP1851C
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS Terminal)
CDP1851 .......•......•.....••..•...•..•....•...••••....•••..•...••..•.•••..•.•.••••.••••••••••••.•.••••••••••• -0.5 to +11 V
CDP1851C ...•......•...••...••....•.......••...•..•.•••..•••••.•.••••.•.•.•••.....•.•.••..•••••.•••••••••••••••• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........•.••.•.•.....•••..••..•.•.•.•.....•.••••.••••••••••••..••.•.•• -0.5 to VOO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ :t10 mA
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ...•...........................•.....•.•.•... Derate Llneary at 12 mW/oC to 200 mW
For TA = -55 to 100°C (PACKAGE TYPE D) •.................................••......•....•..••..•.•..•••••••••••••••• 500 mW
ForTA = +100 to +125°C (PACKAGE TYPE D) ......•........•.•.......•.•.•.......•..... Derate Llneary at 12 mWI"C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Type) ••••...............••.••••••••.••••.••••••••••••• 40 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0, H ......................................................................................... -55 to +125°C
PACKAGE TYPE E ..............................................................................................-40 to +85°C
• STORAGE TEMPERATURE RANGE (T 5tg) ........................................................................ -85 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59:t 0.79 mm) from case for 10 s max................................................... +285°C
OPERATING CONDITIONS at T A = Full Package-Temperature Range. For maximum reliability. operating condltlonl Ihould
be lelected 10 that operation II alwaYI wIthIn the followIng rangel:
LIMITS
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
CDP1851
MIN.
MAX.
4
10.5
CDP1851C
MIN.
MAX.
4
6.5
VSS
VSS
VDD
VDD
UNITS
•
V
DATA
BUS
DATA
BUS
BUFFER
CLOCK
CS
R I
ADDRESS
DECODE
AND
READI
WRITE
TPB
LOGIC
RAO
RAI
Will D
A
TNT
B TNT
INTERRUPT
MASKING
AND
LOGIC
92CM-34326RI
Fig. 1 - Functional diagram for CDP1851 and CDP1851C.
191
RCA CMOS LSI Products
CDP1851, CDP1851C
STATIC ELECTRICAL CHARACTERISTICS at TA
=-40 to +8So C, VDD ± SOlo, Except al noted
CONDITIONS
CHARACTERISTIC
Quiescent Device Current
IDD
Output Low Drive
(Sink) Current
IOL
Output High Drive
(Source) Current
IOH
Output Voltage
Low-Level
VOL;
Output Voltage
High Level
Input Low Voltage
Input High Voltage
Input Leakage Current
VOH;
VIL
VIH
liN
3-State Output Leakage
Current
Operating Current
Input Capacitance
Output Capacitance
lOUT
IDD1l'·
CIN
COUT
LIMITS
CDP1851
CDP1851C
Typ.Max.
Vo
(V)
VIN
(V)
VDD
(V)
Min.
Typ.-
Max.
Min.
-
0,5
0, 10
5
10
-
0.Q1
50
200
-
0.02
200
-
1.6
3.2
1
0.4
0,5
5
1.6
3.2
0.5
0, 10
10
2.6
5.2
4.6
0,5
-1.15
-2.3
9.5
0,10
5
10
-2.6
-5.2
-
0,5
0
0.1
0, 10
5
10
-
-
0
0.1
0,5
5
4.9
5
0, 10
10
9.9
10
5
10
-
5
3.5
0.5,9.5
-
10
7
Any
0,5
Input
0, 10
5
10
0,5
0,5
5
0, 10
0, 10
10
-
0, 5
5
0, 10
10
-
-
-
-
-
0.5,4.5
0.5,9.5
0.5,4.5
1.5
3
-
-
-1.15
-2.3
-
-
-
0
0.1
-
-
4.9
5
-
-
-
-
3.5
±1
-
±2
±1
±1
1.5
3
6
12
5
7.5
10
15
-
1.5
UNITS
pA
mA
V
±1
±1
pA
-
1.5
3
-
-
5
7.5
10
15
mA
pF
-Typical values are for TA = 25° C and nominal VDD.
tlOL = IOH = 1 pA.
~Operating current is measured at 200 kHz for VDD = 5 V and 400 kHz for VDD = 10 V, with open outputs (worst-case
frequencies for CDP1802A system operating at maximum speed of 3.2 MHz).
FUNCTIONAL DESCRIPTION
The CDP1851 has four modes of operation: input, output,
bidirectional, and bit-programmable. Port A is programmable in all modes; port B is programmable in all but the
bidirectional mode. A control byte must be loaded into the
control register to program the ports. In the input and
output modes, each port has two handshaking signals,
STROBE and RDY. In the bidirectional mode, port A has
four handshaking signals: A RDY and A STROBE for input,
B RDY and B STROBE for output. If port A'is programmed in
the bidirectional mode, port B must be programmed in the
bit-programmable mode. Each terminal of port A or B may
be individually programmed for input or output in the bitprogrammable mode. Since handshaking is not used in this
mode, the RDY and STROBE lines may also be used for
bit-programming if port A is not in the bidirectional mode.
Input Mode
When a peripheral device has data to input, it sends a
192
STROBE pulse to the PIO. The leading edge of this pulse
clears the RDY line, inhibiting further transmission from the
peripheral. The trailing edge of the STROBE pulse latches
the data into the PIO buffer register and also a£lliates the
rnT lineto signal the CPU to read this data. The INT pin can
be wired to the im' pin of the CPU orthe~lines for polling.
The CPU then executes an input or a load instruction,
depending on the mapping technique used. In either case
the proper code must be asserted on the RAO, RA 1, and CS
lines to read the buffer register (see Table VI).
The iNT line is deactivated on the leading edgeofTPB. The
trailing edge of TPB sets the RDY line to signal the
peripheral that the port is ready to be loaded with new data.
If RDY is low when the input mode is entered (i.e. after a
reset), a "dummy" read must be done to set RDY high and
signal the peripheral device that the port is ready to be
loaded.
1800-Serles Peripherals
CDP1851, CDP1851C
FUNCTIONAL DESCRIPTION (Confd)
Output Mode
A peripheral STROBE pulse sent to the PIO generates an
interrupt to signal the CPU that the peripheral device is
ready for data. The CPU executes the proper output or store
instruction. Data are than read from memory and placed on
the bus. The data ar!! latched into the port buffer at the end
of the window when RE/\VE =0 and WR~ =1. The ROY
line is also set at this time, indicati~to the peripheral that
there is data in the port buffer. The ffilT line is deactivated at
the beginning of the window. After the peripheral reads
valid port data, it can send another STROBE pulse, clearing
the ROY line and activating the INT line as in the input
mode.
Bidirectional Mode
This mode programs port A to function as both an input and
output port. The bidirectional feature allows the peripheral
to control port direction by using both sets of handshake
signals. The port A handshaking pins are used to control
input data from peripheral to PIO, while the port B
handshaking pins are used to control output data from PIO
to peripheral. Data are transferred in the same manner as
the input and output modes. Since A1IiIT is used for both
input and output, the status retl~;r must be read to
determine what condition caused
to be activated (see
Table V).
Bit-Programmable Mode
This mode allows individual bits of port A or port B to be
programmed as Inputs or outputs. To output data to bits
programmed as outputs, the CPU loads adata byte Into the
8 bit port as in the output mode (no handshaking). Only bits
programmed for outputs latch this data. Data must be stable
when reading from bits programmed as inputs, since the
input bits do not latch. When the CDP1851 Inputs data to the
CPU the CPU also reads the output bits latched during the
last output cycle. The ROY .and STROBE lines may be used
for 1/0 by using the STROBE/ROY 1/0 control byte in table
II. An additional feature available in the bit-programmable
mode is the ability to generate interrupts based on
input/output byte combinations. These Interrupts can be
programmed to occur on logic condltio ... s (AND, OR,
NAND, and NOR) generated by the eight 1/0 lines of each
port (The STROBE and ROY lines cannot generate
interrupts).
A3
A4
A5
A6
~. A STROBE
B ROY
RD/WE
CLOCK
~
RAO
RAI
AI
A2
CDPI800
FAM ILY
fLP
f----+ A ROY
TPB
WR/RE
TPB
MRD
MWR
TPA
AO
PIO
NO.1
CDPI851
I-I-I--
A7
F=>.
F=>
I
B STROBE
PORT AO-A7
PORT BO-B7
CS
VDD
10 ko,
INT
r--
B INT
A INT
BUS 0-7
BUS 0-7
f
~
C>
v
~
-- TPe
7
BUS 0-7
L . - - - WR/RE
RD/WE
CLOCK
RAO
ADDRESS REGISTER
ADDRESS
SELECTS
8001
NO. I CONTROLI
STATUS REG
.8002
NO.1 PORT A
8003
NO.1 PORT B
8004
NO.2 CON TROll
STATUS REG
8008
NO.2 PORTA
6006
NO.2 PORTB
=>
RAI
CS
L
--:=--
AiN'T
BiNT
PIO
NO.2
CDPI651
~
A ROY
B ROY
A STROBE
B STROBE
PORT AO -A7
PORT BO-B7
92CM-31924
Fig. 2 - Memory space I/O. This configuration allows up to four CDP1851s to occupy
memory space 8XXX with no additional hardware (A4 - AS and AS - A7 are used as
RAO and RA 1 on the third and fourth PIO's).
193
RCA CMOS LSI Products
CDP1851, CDP1851C
PROGRAMMING
table II. Input data on the STROBE and ROY lines is
detected by reading the status register. When using the
STROBE or ROY lines for output, the control byte must
be loaded every time output data is to be changed. To
program logical conditions that will generate an
Interrupt, the interrupt control byte of table III must be
loaded. An Interrupt mask of the eight I/O lines may be
loaded next, if bit 04 (mask follows) of the interrupt
control byte
1. The 1/0 lines are masked if the
corresponding bit of the interrupt mask register is 1,
otherwise It Is monitored. Any combination of masked
bits arepermissable, except ali bits masked (mask =
1. InHI.IIz.tlon .nd Control.
The COP1851 PIO must be cleared by a low on the
CLEAR input during power-on to set itfor programming.
Once' programmed, modes can be changed without
clearing except wh~lng the bit-programmable
mode. A low on the CLEAR input sets both ports to the
Input modes, disables interrupts, unmasks all bltprogrammed interrupt bits, and resets the status
register, A ROY, and B ROY.
=
2. Modi SeHlng
The control register must be sequentially loaded with
. the appropriate mode set control bytes in order as
shown in table I (I.e. input mode then output mode,
etc.). PortA is set with the SET A bit = 1 and port Bisset
with the SET B bit = 1. If a port is set to the bitprogrammable mode, the bit-programming control byte
from table II must be loaded. A bit is programmed for
output with the 1/0 bit = 1 and for input with the 1/0 bit =
O. The STROBE and ROY lines may be programmed for
input or output with the STROBEIROY control byte of
FF) .
3. TN'i' En.ble/DIMblt
To enable or disable the iNT line in all modes, the
interrupt ENABLE/DISABLE byte must be loaded (see
Table IV). Interrupts can also be detected by reading
the status register see table V. All interrupts should be
disabled wl2!!:!.. programming or false Interrupts may
occur. The INT outputs are open drain NMOS devices
that allow wired ORlng (use 10K pull-up registers).
A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING
YES
PERFORM FOLLOWING
SEQUENCE BEFOR E
PROGRAMMING PORT A TO
BIDIRECTIONAL MODE
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
SET MASTER INTERUPT
ENABLE I DISABLE
USING TABLE III
RE PEAT FOR EACH
BIT- PROGRAMMABLE
PORT
NOTES
I· STROBE I READY IIO CONTROL BYTE (lQLE III
IS ALSO USED TO OUTPUT DATA TO STROBE AND
READY LINES WHEN BIT-PROGRAMMED.
2. STATUS REGISTER (TABLE III IS USED TO
INPUT DAllI FROM STROBE AND READY LINES
WHEN BIT-PROGRAMME.D.
3. INTERRUPT STATUS IS AlSO READ FROM
STATUS REGISTER.
9zeN-
194
~41108
1800-Serles Peripherals
CDP1851, CDP1851C
TABLE I
[RA1=O, RAO=1]
7
6
Input
MODE SET"
0
0
Output
0
1
Bit-Programmable
1
1
Bidirectional
1
0
5
X
X
X
X
4
3
2
1
Set B
Set A
X
1
1
Set B
Set A
X
1
1
Set B
Set A
X
1
1
Set B
Set A
X
1
1
0
• Modes should be set in order as shown in Table I
If either port is set for bit-programmable mode, the two following control bytes should immediately follow:
TABLE II
[RA1=O, RAO=1]
Bit-Programming
STROBEIRoy I/O Control~
7
6
5
4
3
2
1
0
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
07
06
05
04
03
02
01
DO
~Output = 1
~Input = 0
=Port A, 1 =Port B
(01)
0
(02)
0 = No change to ROY line function, 1 = Change per bit (06)
0
ROY line output data
(05)
STROBE line output data
(06)
I
=No change to STROBE line function, 1 =Change per bit (07)
(03)
(04)
ROY line used as:
Output = 1
Input = 0
(07)
STROBE line used as:
Output = 1
Input = 0
If interrupts will be used for either bit-programmed port, the following control bytes should be loaded:
TABLE III
[RA1=O, RAO=1]
INTERRUPT CONTROL
7
6
Logical Conditions and Mask
0
06
(03)
(04)
I
I
I
5
I
05
I
4
I
04
I
3
I
03
I
2
1
J
I
1
0
1
0
1
-'J
0 =Port A, 1 =Port B
0 = No change in mask, 1 = Mask follows (See TABLE Ilia)
(05) (06)
0,0 = NAND; 1, 0 = OR; 0,1 = NOR; 1, 1 = AND
TABLE ilia
[RA1=O, RAO=1]
INTERRUPT CONTROL
Mask Register
(It 04 = 1)
7
6
5
4
3
2
1
0
B7
Mask
B6
Mask
B5
Mask
B4
Mask
B3
Mask
B2
Mask
B1
Mask
BO
Mask
It Bn Mask = 1 then mask Bit (for n = 0 to 7)
195
RCA CMOS LSI Products
CDP1851, CDP1851C
[RA1=O, RAO=1]
TABLE IV
7
Interrupt
INT
Enable/Disable
Enable
6
5
4
3
2
1
0
X
X
X
AlB
0
0
1
INT Enable = 1, INT Enabled
AlB = 0, Port A
= 0, INT Disabled
= 1, Port B
[RA1=O, RAO=1]
TABLE V
Status Register
(DO)
(01)
BiNi" status (1 means set)
-A INT status (1 means set)
7
6
5
4
3
2
1
O.
07
06
05
04
03
02
01
DO
i
All Modes
1 Bidirectional Mode
(02)
1 = A INT was caused by B STROBE
(03)
1 = A INT was caused by A STROBE!
Only
(06)
A ROY input data
~
A STROBE input data
Bit-Programmable
B ROY input data
Mode
(07)
B STROBE input data
(04)
(05)
TABLE VI - CPU CONTROLS
CS·
RA1
RAO
RD/WE
WR/RE
0
X
X
X
X
X
X
0
0
X
X
X
X
No-op bus 3-stated
X
X
X
X
X
X
0
0
No-op bus 3-stated
1
1
No-op bus 3-stated
1
1
No-op bus 3-stated
Read • status register
Action
No-op bus 3-stated
1
0
1
1
0
1
0
1
0
1
Load control register
1
1
0
1
0
Read' port A
1
1
0
0
1
Load port A
1
1
1
1
0
Read' port B
1
1
1
0
1
Load port B
• Read = RO/WE = 1 and WR/RE = 0 is latched on trailing edge of CLOCK.
TABLE VII - MEMORY I/O USE
RDIWE Input
WR/RE Input
TPB InDut
I/O Space
MRO
TPB
TPB
Memory Space
MWR
MRO
TPB
1
1
PIO Terminals
CPU Terminals
FUNCTION PIN DEFINITION
CLOCK (Input):
Positive input pulse that latches RE~ and CS on its trailing
edge.
CS - CHIP SELECT (Input)
A high-level voltage at this input selects the COP1851 PIO.
RAO - REGISTER ADDRESS 0 (Input):
This input and RA1 are used to select either the ports orthe
control/status registers.
RA1 - REGISTER ADDRESS 1 (Input):
See RAO
BUSO- BUS 7:
Bidirectional CPU data bus.
Ci:EiR (Input)
A low-level voltage at this input resets both ports to the
input mode, and also resets the status register. A ROY, B
ROY, and interrupt enable (disabling interrupts).
AiN'T -
k'l
196
A INTERRUPT (Output):
A low-level voltage at this output indicates the presence of
one of the interrupt conditions listed in Table III. This
output is an open-drain NMOS device (to allow wired
ORing) and must be tied to a pull up resistor, normally 10
1800-Serles Peripherals
CDP1851, CDP1851C
FUNCTION PIN DEFINITION (Confd)
8 INT - B INTERRUPT (Oulpul):
AO-A7:
A low-level voltage at this output Indicates the presence of
one of the Interrupt conditions listed In Table III. This
output is also an open-draln NMOS device and must be tied
to a pullup resistor.
A STROBE (Inpul):
B RDY - B READY (Output):
Data Input or output lines for port A.
An Input handshaking line for port A in the Input, output,
and bidirectional modes. It can also be used as a data bit 1/0
line when port A Is In the bit-programmable mode.
This output is a handshaking or data bit 1/0 line In the
bit-programmable mode.
.
.
A RDY - A READY (OutpUI):
B STROBE (Inpul):
A output handshaking line or date bit 1/0 line.
TPB (Inpul):
An Input handshaking line for port 8 in the Input and output
modes, and for port A when it is in the bidirectional mode. It
can be used as a data bit 1/0 line In the bit-programmable
mode except when port A is not programmed as
bidirectional.
A positive input pulse used as a data load, set, or reset
strobe.
WR/RE - WRITE/READ ENABLE (Input):
A positive Input used to write data from the CDP1851 to the
CPU bus.
BO-B7:
RDIWI- READIWRITE ENABLE (Input):
Data input or output lines for port 8.
A positive input used to read data from the CDP1851 to the
CPU bus;
VSS:
Ground
VDD:
Positive supply voltage.
tlO
NI
N2
-MRii
A ROY
e ROY
~~
A STROBE
STROBE
TPA
CLOCK
TPB
WR/RE
COPIS02
?Voo
~
iiiT
ROIWe'
L
~
~I
PORT AO-A7
TPe
1'\7
=>
COPI851
10 kG
L
I
f==::
RAO
RAI
CS
PORT BO-B7
iIiNT
AiNT
BUS 0-7
BUS 0-7
II
• r,/
, ::-
BUS 0-7
'--- RAO
' - - - Rill
CS
CLOCK
RO/WE
L
WR/RE
TPB
cOPlesl
L
~.A ROY
~IBA ROY
STROBE
~ e-STROBE
~
~
PORT AO-A7
~'ORT
BO-B7
A INT
ii'iNT
9ZCM-319Z5
Fig. 3 - I/O spaceI/O.
197
RCA CMOS LSI Products
CDP1851, CDP1851C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85° C, YOO ± 5%,
t r, tf =20 ns, YIH = 0.7 YDD, YIL = 0.3 YDD, CL = 100 pF
LIMITS
CHARACTERISTIC
YDD
(Y)
COP1851
Typ.- Max.+
Min.
Min.
COP1851C
Typ.- Max.+
UNITS
Input Mode see Figs. 4 and 5
Minimum Setup Times:
Chip Select to CLOCK
RD/WE to CLOCK
-
WR/RE to CLOCK
Data in to STROBE
tCSCl
tRWCl
tWRCl
tDIST
Minimum Hold Times:
Chip Select After CLOCK
Address After TPB
Data In After STROBE
Data Bus Out After Address
Propagatio~
-
50
75
-
25
40
5
-
75
120
10
-
40
60
5
-
75
120
10
-
40
5
-
75
10
-
5
tHCSCl
TPB to RDY
STROBE to RDY
TPB
STROBE
120
-
-
75
120
60
-
-
-
120
-
75
120
40
60
-
120
-
-
75
75
120
-
-
40
60
-
-
5
-50
0
-50
0
-25
0
-
-
75
5
50
75
10
-
25
40
-
50
tHSTDI
-
-
5
50
325
500
50
325
500
tHADOH
10
25
165
250
-
-
5
-
200
300
200
300
tplNT
10
-
100
150
200
300
tSTINT
tTPRDY
tSTRDY
tWCL
tWTPB
tWST
tADA
40
60
-
75
120
-
40
60
-
-
-
100
150
-
100
150
50
75
-
-
-
325
500
-
325
500
250
-
-
-
10
-
100
150
5
250
375
10
-
125
200
5
-
260
400
10
-
130
200
5
75
120
5
-
10
-
5
-
10
-
5
-
10
-
165
10
-Typical values are for T A = 25°C and nominal voltages.
+Maximum limits of minimum characteristics are the values above which all devices function.
198
-
75
THATPB
Access Time, Address to Data
Bus Out
75
-
10
Minimum Pulse Widths:
CLOCK
-
50
10
5
STROBE to INT
-
-
Delay Times:
TPB to INT
5
10
-
-
200
300
-
-
250
375
-
-
260
400
-
-
75
120
-
-
75
120
ns
1800-Series Peripherals
CDP1851, CDP1851C
I kU
~50%
~
INPUT ~"V7.
SIGNAL
I
I
I
AINT~-+--~~-----{)A
IK
.J.
50PF
B INT I--+-._-------{) B
CDPIB51
1
I
i~·
A,B
I
I
i
:
~
i
tpINT!
r-tSTINT-i
I- IWINT
--1
50PF
92CS- 31927
Fig. 4 - Interrupt signal propagation delay time test circuit and waveforms.
RDY
-----I,
-"ll--,
i
~ tSTRDY
!
,
~tTPRDY
f--------',
I'
t WST·-!-:~~,-f- tSTINT
STROBE
~ t PINT
--j
~~,-------~i-~:------t--
t DIST ~
DATA-IN
I
tHSTDI
I
:
~~=----i-+-----
TPB
, '
:----r------------~Il~"
----~tWCL
CLOCKo(TPA)
_________~r__l~I--------~:---------
I
'
tWTPB
I
ICSCL--t--~·~:
CS
>-- IHCSCL
_____~--~i~iL___~_______
~twRcL
WR/REO(MRDJ
-.--Jr-----ii
:
MEMORY SPACE
RD/WEo(MWR)
RD/WEO(MRD}
t--1RWCL-----i
-.--JI-'-----------f[----I/O SPACE
WR/REo(TPB)
RAI/RAO
I
---------------'Il,..'______
-------...,Xi.
_ _ _ _ _ _ _ _...J.
--:
10 OR II
,
~IADA
DATA BUS
>---1 HATPB
VALID PORT ADDR)'(
------c==x
.1"'----I
I
.-----,-IHADOH
x==
92CM-3192e
Fig. 5 - Input mode timing waveforms.
199
RCA CMOS LSI Products
CDP1851, CDP1851C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85° C, VDD
trl If =20 ni, VIH =0.7 VDD, VIL =0.3 VDD, CL = 100 pF
± 5%,
LIMITS
CHARACTERISTIC
VDD
(V)
CDP1851
Typ.- Max.+
Min.
Min.
CDP1851C
UNITS
Typ.- Max.+
Oulput Mode lee Figi. 4 and 6
Minimum Setup Times:
Chip Select to CLOCK
5
tCSCL
10
5
-
RD/WE to CLOCK
tRWCL
10
5
WRiRE to CLOCK
Address to WRITE •
Data Bus to WRITE •
tWRCL
Chip Select After CLOCK
Data Bus After WRITE •
Propagation Delay Times:
WRITE • to Data Out
-
WRITE • to INT
STROBE to TriiT
STROBE to RDY
100
150
-
400
10
-
260
130
200
5
-
75
120
5
10
5
tSTRDY
CLOCK
tWCL
10
10
10
5
STROBE
tWST
10
5
WRITE·
tww
60
75
-
tHDW
5
10
Minimum Pulse Widths:
40
50
5
10
tSTINT
120
60
75
10
tHAW
twRDY
60
75
120
5
tHCSCL
5
10
10
....:.
40
60
75
50
tDW
-
-
40
40
5
WRITE • to RDY
120
-
5
10
tWINT
40
-
10
tWDO
75
25
75
5
5
Address After WRITE·
50
10
tAW
Minimum Hold Times:
-
25
40
80
120
75
-
-
75
120
-
-
75
120
-
-
50
75
-
-
80
120
-
-
75
120
-
-
50
75
-
-
50
75
25
40
-
50
25
75
-
40
-
-
-
225
350
225
350
125
200
300
450·
-
150
225
350
525
175
275
200
300
40
60
100
150
50
175
75
275
90
150
• WRITE is the overlap of RD/WE = 0 and WR/RE = 1..
-Typical values are for T A = 25°C and nominal voltages.
+Maximum limits of minimum characteristics are the values above which all devices function.
200
50
-
-
300
450
-
-
350
525
-
-
200
300
-
-
260
400
-
-
75
120
-
-
100
150
-
-
175
275
-
-
ns
1800-Serles Peripherals
CDP1851, CDP1851C
-!!
~
INT _ _ _ _ _ _
tWINT
i
r--
tSTINT ---:
RDY _ _ _ _ _ _ _~:-~
1
I
STROBE
I
---:
ISTRDY;"'::
~
-IWRDY
,'----;-IWTPB
:-----t--1WCL I
I
CLOCK' (TPAI
............
~
----i I
WST
l.-
I
I_ _ _ _ _ _ _ __
- - - lr I11..-_---"1..---;'
tHCSCL-i
i: :
I
1 ________
!-..L,_+'
cs --.Jr---T"1
1
--1
ICSCL : -
:
: ,.,-_ _ _ _ _ __
--1:,..--{X
. .'__
)
!l-
DATA - OUT _,..-,..-_-,-:_ _
:-- IWRCL
"_A_Ll_D_D_AT_A_O_U_T_ _
r---7IWDO
!
i
ME MORY SPACT
I:
WR/AE.(MRoI]J
RD/WE. (MWRI
--j
Ur---------
:
:
1
r---r--IWW*
n
Jn i l
WR/RE.(TPB
IIO SPACE:
- i 'RWCLI
i
1
RD/WE'(MWRl
I
1
r-1AW---i
RAI/RAO
--0
* WRITE IS THE OVERLAP OF
x,.------
----1 I HAW_
-----.)1( VALIDlg~TI~DDR
t--1DW
DATA BUS
I
1
:
' : ' 'I
VALID DATA
I HDW
)1(--'------
WR/RE" AND RD/WE· 0
I
92CM- 31920
Fig. 6 - Output mode timing waveforms.
OPERATING AND HANDLING CONSIDERATIONS
1, Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling,
Recommended handling practices for CMOS devices
are described in ICAN-6525 "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2, Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or supress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause VOO - VSS to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than VOO nor less than
VSS. Input currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused STROBE and OATA terminals must be
connected to either VOO or VSS, whichever is
appropriate.
Output Short Circuits
Shorting of outputs to VOO orVss may damage CMOS
devices by exceeding the maximum device dissipation.
201
RCA CMOS LSI Products
CDP1851, CDP1851C
o
40
80
120
200
226-234
5.740-5.944)
230- 238
14-----------:-::15.842-6.045)
92CL-3333B
Dimensions and pad layout for CDP1851CH.
Dimensions in parentheses are in millimeters and are derived from
the basic inch dimension as indicated. Grid graduations are in mils
(1cr 3 inch).
202
The photographs and dimensions of each CMOS chip represent a
chip when it is part of the wafer. When the wafer is cut into chips,
the cleavage angles are 57° instead of 90° with respect to the face
of the chip. Therefore, the isolated chip is actually 7 mils (0.17 mm)
larger in both dimensions.
1800-Serles Peripherals
CDP1852, CDP1852C
a-Bit Input/Output Port
Features:
• Static Silicon-Gate CMOS circuitry
• Compatible with COP1800-series
• Interfaces with COP1802 and COP1804
microprocessors without additiona I
components
• Single voltage supply
• F.ull military temperature range
(-55 0 C to +1250 C)
• Parallel 8-bit data register and buffer
• Flip-flop for service request
• Asynchronous register clear
• Low quiescent and operating power
csvCSi
I.
2
MODE
DID
3
000
011
001
012
002
013
003
CLOCK
9
10
24
23
22
21
20
19
18
17
16
15
I.
13
Vss
VDD
SR/SR
017
007
016
006
DIS
DDS
014
DO.
CLEAR
CS2
L!!12""T"'DP'"V-';;IE"'W'=
Terminal Assignment
The RCA-CDP1852 and CDP1852C are
parallel, 8-bit, mode-programmable COSIMOS
input/output ports designed for use in
CDP1800 series microprocessor systems.
These input/output ports are compatible and
will interface directly with the CDP1802 or
CDP1804 without additional components.
They are also useful as 8-bit address latches
in 1800-series microprocessor systems and as
I/O ports in general purpose applications.
If the CDP1852 is used as an output port
(mode=l). data is strobed into the port's
8-bit register when CST·CS2·CLOCK=1. The
three-state output drivers are enabled at all
times when the CDP1852 is configured as an
output port. The service request signal is
generated at the tbrmination of CS1'CS2=1
and will be present, 1 level, until the following negative, high-to-Iow transition of the
clock.
The mode control is used to program the
device as an input port (mode=O) or output
port (mode=l). If the CDP1852 is used as an
input port (mode=O). data is strobed into the
port's 8-bit register by a high (1) level on the
clock line. The negative, high-to-Iow transi·
tion of the clock sets the Service Request
output (SR=O) and latches the data in the
register. The SR output can be used to signal the microprocessor via a flag or interrupt
line. When CS1'CS2=1 the three-state output
drivers are enabled, the negative high-to-Iow
transition of CS1'CS2 resets the Service
Request output, SR=1.
A CLEAR control is provided for resetting
the port's register and service request flipflop.
ADOR BUS
AODR BUS
TPA
TPA
MRD
CEO
The CDP1852 and CDP1852C are supplied
on 24-lead, hermetic, dual-in-line ceramic
packages (D suffix). in 24-lead dual-in-line
plastic packages (E suffix).
NO-N2 MRO
TPB
CDU
CDPI802
RAM
ROM
MRD
I
The CDP1852 is functionally identical to
the CDP1852C. The CDP1852 has a recommended operating voltage range of 4 to
10.5 volts, and the CDP1852C has a recommended operating voltage range of 4 to 6.5
volts.
seQ
SCI
INTERRUPT
DMA-IN DMA"·QUT
MWR
ffi-EF4
Fig. 1- Tvpical COP 1802 microprocessor system.
203
RCA CMOS LSI Products
CDP1852, CDP1852C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOLTAGE RANGE, (V DO)
(Voltag" referenced to VSS Terminal)
CDP1852.
. . -0.5to+11V
CDP1852C .
-0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT
• • ±10mA
POWER DISSIPATION P.,ER PACKAGE (PO):
For T A = -40 to +600 C (PACKAGE TYPE E)
• . . . • . . . . • 500mW
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +85 ct. (PACKAGE TYPE E)
For TA = -55 to +100 ~ (PACKAGE TYPE D)
. . . . . . . . • . 500mW
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 C (PACKAGE TYPE D)
DEVICE DiSsiPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
· .100mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D, H
....
. -55 to +125 0 C
PACKAGE TYPE E .
°
: -6:!~~;:~og
~~~~A,-~~;~~~~~~~~~G~I~~GS~~D~~ING) :'
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.
·
. +265°C
SA/SR
--@)
SERVICE
REQUEST
LATCH
v;-J
d. :
DID
000
:J-+0
~i
= I
Vss I
1
L ________ _
O:tl
;-- -
-
-
-
-
-
_-.J
-
-
-
-
-
-
-
-
-
-
~
r-------
@-IL
r--J
____________
-
--- - ---[-- -
--------
--
-,
007
f-@
~
___ ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1
92CL-31293
Fig. 2 - CDP1852/ogic diagram.
204
001
t-@
L ____ - - - - ] ] - [ - -
on
-,
1800-Series Peripherals
CDP1852, CDP1852C
RECOMMENDED OPERATING CONDITIONS at TA = Full Package Temperature Range
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
LIMITS
CDP1852
CHARACTERISTIC
Min.
OC Operating-Voltage Range
Input Voltage Range
CDP1852C
Max.
Min.
UNITS
Max.
4
10.5
4
6.5
V
VSS
VOO
VSS
VOO
V
STATIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85°C. VDD ±5%
CONDITIONS
CHARACTERISTIC
Vo
(V)
Ouiescent Device
Current, 100
Output Low Drive
(Sink) Current, leL
Output High Drive
(Source) Current,
IOH
Output Voltage LowLevel VOL·
Output Voltage
HighLevel, VOH
Input Low Voltage,
VIL
Input High Voltage,
VIH
I nput Current,
liN
3-State Output
Leakage Current
lOUT
-
LIMITS
COP1852
VIN VDD
(V) (V)
Min.
Typ.*
-
5
-
0,10 . 10
-
0.4
0,5
5
1.6
3.2
0.5
'1,10
10
3
~
4.6
0,5
5
9.5
0,10
10
-
-
0,5.
Min.
100
-
500
-1.15 -2.3
-3
CDP1852C
Max.
-6
-
-1.15
-2.3
-
-
-
-
-
-
0
0.1
-
0
0.1
-
0,5
5
4.9
5
-
0,10
10
9.9
10
-
-
-
1.5
0.5,9.5
-
5
10
-
3
0.5,4.5
-
5
3.5
-
7
-
10
5
-
0,10
10
0,5
0,5
5
-
0,10
0,10
10
-
0
-
-
3.5
5
-
-
1.5
-
-
-
±1
~
-
±1
-
±2
-
-
-
-
-
±1
-
±2
-
-
0,5
5
-
130
200
-
-
0,10
10
-
400
600
-
'nput Capacitance
-
-
-
-
5
7.5
_.
-
-
±1
-
150
-
mA
I
rnA
V
-
-
-
p.A
0.1
-
-
4.9
Operating
Current, '001#
C'N
-
-
5
0.5
500
3.2
1.6
10
-
-
-
0,5
0.5,9.5
UNITS
Max.
-
0,10
0.5,4.5
Typ.*
200
V
/J A
p.A
p.A
5
7.5
pF
Output Capacitance,
COUT
-
-
5
7.5
-
-
-
* Typical values are for T A = 25°C and nominal VOO'
.. IOL = IOH = 1 p.A
# Operating current is measured at 2 MHz in an 1800 system with open outputs and a program of BN55. BNAA.
BN55. BNAA. ---- .
205
RCA CMOS LSI Products
CDP1852, CDP1852C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C. VDD = ±5%.
tr.tf = 20 ns. VIH = 0.7 VOO. Vil = 0.3 VOO. Cl = 100 pF. and 1 TTL load
LIMITS ATVOO= 10V APPLY TO THE COP1852 ONLY
CHARACTERISTIC
VOO
(VI
LIMITS
I
Min.
I
Typ.*
Max.
180
90
360
180
90
45
180
90
80
40
160
80
-10
-5
0
0
75
35
150
75
185
100
370
200
UNITS
MODE 0 - Input Port
-
Required Select Pulse Width, tsw
5
10
Required Write Pulse Width, tww
5
10
Required Clear Pulse Width, tClR
5
10
-
Required Data Setup Time, tSD
5
10
-
Required Data Hold Time, tDH
5
10
-
Data Out Hold Time, tDOH'"
5
10
30
15
SR Output Transition Time
5
10
-
30
15
60
30
Data Output Transition Time
5
10
-
30
15
60
30
Propagation Delay Times, tplH' tpH L:
Select to Data Out'"
5
10
30
15
185
100
370
200
Clear to SR
5
10
-
170
85
340
170
Clock to SR
~
10
-
110
55
220
110
120
60
240
120
130
65
260
130
130
65
260
130
60
30
120
60
-10
-5
0
0
75
35
150
75
-10
-5
0
0
30
15
60
30
30
15
60
30
Select to SR
-
-
-
-
5
-
lD
-
ns
MOOE 1 - Input Port
Required Clock Pulse Width, tCl
5
10
Required Write Pulse Width, tww .
5
10
Required Clear Pulse Width, tCLR
5
10
Required Data Setup Time, tDS
5
10
Required Data Hold Time, tDH
5
10
Required Clock-after-Select Hold Time
5
10
SR Output Transition Time
5
10
Data Output Transition Time
5
10
-
-
-
-
.. Minimum value is measured from CS2; maximum value is measured from CS1 .
.. Typical values are for TA = 2SoC and nominal VOO'
206
ns
1800-Serles Peripherals
CDP1852, CDP1852C
DYNAMIC ELECTRICAL CHARACTERISTICS (Cont'd)
CHARACTERISTIC
LIMITS
VDD
(V)
Min.
Max.
280
140
440
220
120
60
200
100
240
120
240
120
120
60
240
120
5
10
5
10
-
-
140
70
220
110
5
10
5
10
-
100
50
-
120
60
Clock to SR
5
10
-
Select to SR
5
10
Propagation Delay Times, tPLH, tPHL:
Clear to Data Out
Write to Data Out
Data In to Data Out
Clear to SR
-
UNITS
Typ.*
-
ns
• Typical values are for T A = 25°C and nominal VDD'
CSI.CS2
*::.....-----------------JI
CL.OCK------..JI
DATAIN--------~~--+--J'~--+_-----~-~--------
DATA
aus------------t-ti~DA.~----~--~-~--------
* CSI 'CS2
IS THE OVERL.AP OF eSI., ANO CS2- I
INPUTS
INPUTS
CLOCK CS1·CS2 t
X
X
0
0
1
I
0
0
1
1
1
OUTPUTS
CLEAR
0
1
0
1
X
DATA OUT
HIGHZ
HIGH Z
0
DATA LATCH
DATA IN
CLOCK
SR OUT
CSI'CS2 t
X
X
1
SA LATCH-
0
0
0
'-.r
-
X
1
0
0
OUTPUTS
CLEAR
SR LATCH-
0
X
1
1
1
1
0
NO CHANGE
-
t CSI'CS2 - 1 ~ CS1 -1 and CS2 -1.
• SR Latch is internal to the device (See Fig. 2).
92CM-31292
Fig. 3 - MODE 0 input port timing diagram and truth tables.
50%
CSI. CS2
-90'1
DATA OUT - - - - - (
t DOH
eSI
DATA
I K!l
OUT
PULSE
GENERATOR
CDPl852
92CM-31296
Fig. 4 - Data out hold time waveforms and test circuit.
207
,RCA CMOS LSI Products
'CDP1852, CDP1852C
ClOCK--------------~~
DATA IN
DATA OUT
__
+-~
__
~~---JI~~
SR
* CSI' CS2 IS THE OVERLAP OF
"
CSi .. 0 AND CS2 = I
WRITE IS THE OVERLAP OF CSI' CS2 AND CLOCK
"---,-N-P-UT-S-----,--:O"'U"'T;;;P;-,U""T--,
CLOCK
X
CSl 'CS2 t
CLEAR
SA LATCH e
X
X
NO CHANGE
t CSl ·CS2 '" 1 ' CSl "0 and CS2::: 1 .
DATA LATCH
.~R LATCH·
DATA LATCH
a
DATA IN
0
• SA Latch is Internal to the device (see Fig. 2).
92CM- 31295
Fig. 5 - MODE 1 input port timing diagram and truth rabies.
~~-------------------~/
~'--N I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -____________________
SELECT __~~~____6_D______
L//_______________6_5~._____________________~~__
INPUT
SR
PORT-~---->-----------~/
92CM-3t233
Fig. 6 - Execution of a "65" output instruction showing momentary
selection of input port ND",
Application Information
In a CDP1802- or CDP1804-based system
where MRD is used to distinguish between
INP and OUT instructions, and INP instruction is assumed to occur at the beginning of every I/O cycle because MRD
starts high. Therefore, at the start of an OUT
instruction, which uses the same 3-bit N
code as that used for selection of an input
port, the input device will be selected for a
short time (see Fig. 6). This condition forces
SR low and resets the SR latch (see Fig. 2).
In a small system with unique N codes for
inputs and outputs, this situation does not
arise. Using the CDP1853 N-bit decoder or
equivalent logic to decode the N lines
after TPA prevents dual selection in larger
systems.
4
NO 2
I OF 8
NI..L[>-
I~ 6~;!
N2 14
It OUT 5
10 OUT 6
9 OUT 7
DECODER
EN
TPA
OUT 0
5 our I
6 OUT 2
TP8
OUTPUT
'" UU I PUT ENABLED WHEN EN: HIGH
II\, "[RNAl SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIG. I)
92CS-i!9024
Fig. 7 CDP1853 timing diagram.
208
Fig. 8 - CDP1853 functional diagram.
1800-Serles Peripherals
CDP1852, CDP1852C
92CM- 31297
Dimensions and pad lavout for CDP1852H.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10- 3 inch).
The photpgraphs and dimensions of fJIlch chip
represent a chip when it is part of the wafer.
When the wafer is cut into chips, the clfJllvage
angles are 57° instfJlld of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actuallv 7 mils (0.17 mm) larger in both dimensions.
I
209
RCA CMOS LSI Products
CDP1853, CDP1853C
N-Bit 10f 8 Decoder
CLOCK A
NO
NI
OUT 0
our I
OUT 2
OUT 3
'ss
16
15
14
13
3
..
15
6
7
12
II
10
L..:8T=ap=-:-::""'EW.,.=9:...o
VOO
CLOCK 8
N2
C£
OUT4
OUT 5
OUT 6
Features:
• Provides direct control of up to 7 input and 7 output devices
• CHIP ENABLE (CEI allows easy expansion for multi-level
I/O systems
OUT 7
TERMINAL ASSIGNMENT
The RCA-CDP1853 and CDP1853C are 1 of
8 decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical, are
specifically designed for use as gated N-bit
decoders and interface directly with the
1800-series microprocessors without additional components. The CDP1853 has a
recommended operating voltage range of 4
to 10.5 volts, and the CDP1853C has a recommended operating voltage range of 4 to
6.5 volts.
When CHIP ENABLE (CE) is high, the selected output will be true (high) from the
trailing edge of CLOCK A (high-to-Iow
transition) to the trailing edge of CLOCK B
(high-to-Iow transition). All outputs will be
low when the device is not selected (CE =0)
and during conditions of CLOCK A and
CLOCK B as shown in Fig. 2. The CDP1853
inputs NO, Nl, N2, CLOCK A, and CLOCK B
are connected to an 1800 series microprocessor outputs NO, Nl, N2, TPA, and TPB
respectively, when used to decode I/O
NO 2
NI
3
I OF 8
DECODER
~ 6~~ ~
~ OUT 2
12 OUT 3
6~~:
N2 14
EN
II
10 OUT 6
9 OUT 7
commands as shown in Fig. 5. The CHIP
ENABLE (CE) input provides the capability
for multiple levels of decoding as shown in
Fig. 6.
The CDP1853 can also be used as a general
1 of 8 decoder for I/O and memory system
applications as shown in Fig. 4.
The CDP1853 and CDP1853C are supplied
in hermetic 16-lead dual-in-line ceramic (D
suffix) and plastic (E suffix) packages.
TRUTH TABLE
CLA
CL B
1
°
0
0
1
1
1
1
0
0
CE
1
N2
1
1
1
1
0
X
X
0
N1
NO
EN
0 1 2 3 4 5 6 7
1 0 0 0 0 0 0 0
0
0
0
1
0
0
1
1
0 1 0 0 0 0 0 0
0
0
1
0
1
0 0 1 0 0 0 0 0
0 0 0 1 0
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
1
1
1
0
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
X
X
X
0
1 = High level
Fig. 1 - CDP1853 functional diagram.
210
EN
On·1*
0
= Low level
X
0 0 0
0 0 0
1 0 0
0 1 0
0 0 1
0 0 0
= Don't care
*On-1 = Enable remains in previous state.
1800-Series Peripherals
CDP1853, CDP1853C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V oo )
(All voltage values referenced to V SS terminal
COP1853 ......•.........•..•......................................... -0.5 to + 11 V
COP1853C ...........•..........•.......................•............. -0.5 to + 7 V
INPUT VOLTAGE RANGE, ALL INPUTS. • • . . . . • . . . . . . • . . . . . . . . • . . . . . . . .. -0.5 to VOO + 0_5 V
DC INPUT CURRENT, ANY ONE INPUT .....••.....•....•..•...•.......•.........• ± 10 mA'
OPERATING-TEMPERATURE RANGE (TA):
CERAMIC PACKAGES (0 SUFFIX TYPES) ......•........................... -55 to + 125:C
PLASTIC PACKAGES (E SUFFIX TYPES) .....................•..•......... -40 to + 85 C
STORAGE TEMPERATURE RANGE (TJtIl~ ....•..............•..•............. ~5 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ±1132 inch (1.59±o.79 mm) from case for 10 s max•........••.•.•....... +265°C
STATIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85°C. Except as noted
CONDITIONS
LIMITS
CDP1853
CHARACTERISTIC
VO
IV)
Quiescent Device
Current,l L
Output Low Drive
ISink) Current,
IOL
Output High Drive
lSource Current)
IOH
Output Voltage
Low-Level ...
-
VIN VDD
IV) IV) Min_
-
-
-
5
10
0.4
0.5
0,5
0,10
5
10
1.6
2.6
4.6
9.5
0,5
0,10
5
10
-1.15
-2.6
-
-
VOL
-
0,5
0,10
5
10
-
Output Voltage
High Level
V OH
-
0,5
0,10
5
10
0.5,4.5
1,9
-
Input High Voltage
V IH
0.5,4.5
1,9
-
.
Operating Current
IDDl
Input Capacitance
CIN
Output Capacitance
COUT
Min. Typ.
-
t
UNITS
Max.
10
100
-
-
3.2
5.2
-
1.6
3.2
-
-
-
-
-
·2.3
-5.2
-
-1.15
0
0.1
0
0.1
4.9
9.9
5
10
-
5
10
-
5
10
3.5
7
-
5
10
-
-
-
-
±1
±1
5
10
.-
50
150
100
300
5
10
5
·2.3'
-
-
-
-
50
-
-
0
JJ.A
I
mA
mA
0.1
V
Input Low Voltage
V IL
Input Leakage
Current liN
t
Typ. Max.
1
10
-
CDP1853C
-
Any 0,5
Input 0,10
0,5
0,10
0,5
0,10
-
-
-
-
-
-
-
5
-
-
-
-
-
-
1.5
3
-
-
1.5
-
-
3.5
-
-
-
-
4.9
-
-
V
-
-
±1
50
100
-
7.5
-
15
-
-
JJ.A
-
JJ.A
5
7.5
pF
10
15
pF
t Typical values are for T A = 25°C and nominal voltage.
* Operating current measured in a CDP1802 system at 2MHz with outputs floating .
... IOL = IOH= lJJ.A
211
RCA CMOS LSI Products
CDP1853, CDP1853C
OPERATING CONDITIONS at T A = Full Package-Temperature Range. For maximum
reliability, operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
CDP1853
Min.
Supply-Voltage Range
Max. Min.
4
Recommended Input Voltage Range
CDP1853C
10.5
VSS
VOO
UNITS
Max.
4
VSS
.,
6.5
V
VOO
V
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85°C, V DD =± 5%,
V IH = 0.7 V DD , V i l = 0.3 V DD , tr,lt = 20 ns, Cl = 100pF
CHARACTER ISTIC
V OD
(V)
Propagation Oelay Time:
LIMITS
CDP1853
UNITS
CDP1853C
Typ.
Max.
Typ.
Max.
5
175
275
175
275
ns
CE to Output, tEOH' tEOl
10
5
90
225
150
350
225
350
ns
N to Outputs, tNOH' t NOl
10
5
10
120
200
100
200
300
150
-
-
200
-
300
5
10
175
90
275
150
175
-
275
5
10
50
25
75
50
50
75
-
-
5
10
50
25
75
50
50
75
-
-
Clock A to Output, tAO
Clock B to Output, t BO
Minimum Pulse Widths:
Clock A, tCACA
Clock B, t CBCB
ns
ns
-
ns
Note 1: Maximum limits of minimum characteristics are the values above which all devices
function.
Note 2: Typical values are for T A = 25°C and nominal voltages.
~~'1-
CLOCK A ' A O
CE~
OUTPUT
aJ
OUTPU:
tt
ouTPUT
EO
cl CLOCK A TO OUTPUT
~
ct
CLOCK B
NO
b) N LINES TO OUTPuT (0-7) DELAY TIME
(O~ 7)
DELAY TIME
:=§-=:1-
CE TO OUTPUT (0-7) DELAY TIME
'BO
OUTPUT
~
d) CLOCK B TO OUTPuT
(O~7)
DELAY TIME
Fig. 2 - Propagation delay time diagrams.
TPA
TPB
A
NO
B
C
CHIP ENABLE
N'
N2
Vee
EN'"
OUTPUT
# OUTPUT ENABlED WHEN EN· HtGH
INTERNAL SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIG. I)
Fig. 3 - Timing diagram.
212
Fig. 4 - N-bit decoder used as a 1 of 8
decoder.
1800-Serles Peripherals
CDP1853, CDP1853C
COP 1800 SERIES
LOAD VIA
611NSRUCTION
AVAILABLE
,
7 OUTPU'l PORTS
92C~· 2902~RI
7 INPUT PORTS
Fig. 5 - N·bit decoder in a one·level 110 system.
I
NOTE' SYSTEM SHOWN WILL SELECT
r------------,
COP leoOSERIES
UP TO 56 INPUT AND 48 OUTPUT
PORTS. WITH ADDITIONAL DECODING
THE TOTAL NUMBER OF INPUT
AND OUTPUT PORTS CAN 8E
FURTHER EXPANDED
INTERCONNECTED
,
AS IN FIGURE 4
ItO
NO, NI, NZ
7 INPUT,
6 OUTPUT
PORTS
.-.-+---j-----j-....jCLOCK A
.-.+--+~"'CLOCI(
CE
a
'-_"'N"'0."'N"".c.::N
::;2_+_t--t-___"""-1 ::~8::',
INST
PORTS
SECTIONS 3-7
L-t:t===:jCLOCK A
CLOCK B
'------ICE
L_.::NO:.:•.:.N:.:'•.:.N:::2________-". :~:~~5F~'
INST
110
7 INPUT,
6 OUTPUT
PORTS
Fig. 6 - Two-level 110 using CDP1853 and CDP1852.
213
RCA CMOS LSI Products
CDP1854, CDP1854C
Programmable
Universal Asynchronous
Receiver/Transmitter (UART)
CDP1854AE
CDP1854ACE
H-1892
Feltures:
• Baud rate-DC to 200 K bits/sec
• Two operating modes:
Mode O-functionally compatible with
@ VDD=5 V
DC to 400 K bits/sec
industry types such as the TR1602A
Mode 1-interfaces directly with
@ VDD=10 V
CDP1800-series microprocessors
• Fully programmable with externally selectable word length (5-8 bits), parity
without additional components
inhibit, even/odd parity, and 1, l'h, or
• Full- or half-duplex operation
2 stop bits
• Parity, framing, and overrun error
detection
• False start bit detection
The RCA CDP1854A and CDP1854AC are silicon-gate
CMOS Universal Asynchronous Receiver/Transmitter
(UART) circuits. They are designed to provide the necessary
formatting and control for interfacing between serial and
parallel data. For example, these UARTs can be used to
interface between a peripheral or terminal with serial I/O
ports and the 8-bit CDP1800-series microprocessor parallel
data bus system. The CDP1854A is capable of full duplex
operation, i.e., simultaneous conversion of serial input data
to parallel output data and parallel input data to serial
output data.
directly compatible with the CDP1800-series microprocessor system without additional interface circuitry.
When the mode input is low (MODE=O), the device is
functionally compatible with industry standard UART's
such as the TR1602A. It is also pin compatible with these
types, except that pin 2 is used for the mode control input
instead of a VGG=-12 V supply connection.
The CDP1854A UART can be programmed to operate in
one of two modes by using the mode control input. When
the mode input is high (MODE=1), the CDP1854A is
The CDP1854A and CDP1854AC are supplied in hermetic
40-lead dual-in-line ceramic packages (D suffix) and in
40-lead dual-in-line plastic packages (E suffix). The
CDP1854AC is also available in chip form (H suffix).
voo
MODE (YoDI
YSS
en
R
R
R
R
R
R
R
R
BUS
BUS
BUS
BUS
BUS
BUS
BUS
BUS
7
6
5
4
3
2
I
0
TNT
FE
PE/OE
RSEL
R CLOCK
TPB
DA
sor
I
40
39
3
38
4
37
36
5
6
35
34
7
33
B
32
9
10
31
II
30
12
29
13
2B
14
27
15
26
16
25
17
24
18
23
19
22
21
20
TOP YIEW
2
T CLOCK
m
ES
PSI
NC
CS3
RDM
TBUS7
TBUS6
T BUS5
TBUS4
TBUS3
TBUS2
TBUS I
TBUSO
YOO
*MOoE(Yssl
YSS
RRO
R BUS 7
R BUS 6
fiiRE
CLEAR
92CS-284'SRI
Mode 1
Termlnll Assignment
I
2
3
4
5
.6
R
R
R
R
R
R
40
39
38
37
36
35
34
7
33
8
BUS 4
32
9
8US 3
BUS 2
31
10
BUS I
II
30
BUS a - 1 2
29
13
28
PE
FE
14
27
15
26
OE
16
25
SFD
17
24
CLOCK
DAR
18
23
19
22
DA
21
20
sor
TOP YIEW
R BUS 5
500
RTS
CSI
NC-NO CONNECTION
214
The CDP1854A and the CDP1854AC are functionally
identical. The CDP1854A has a recommended operatingvoltage range of 4-10.5 volts, and the CDP1854AC has a
recommended operating-voltage range of 4-6.5 volts.
* PIN 2
NO CONNECTION
ON CDP6402
T CLOCK
EPE
WLS I
WLS 2
SBS
PI
CRL
T BUS 7
T BUS 6
T BUS 5
TBUS 4
T BUS 3
T BUS 2
TBUS I
TBUS 0
500
TSRE
'fHl'!L
THRE
MR
92C$- 28456RI
Mode 0
Termlnll Assignment
1800-Serles Peripherals
CDP1854, CDP1854C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DO)
(Voltage referenced to VSS Terminal)
COP1854A •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -0.5 to +11 V
COP1854AC ••••••••••••••••••••••••••••• " ••••••••••••••••••••••••••••••••••••••••••••••••••• -0.5 to +7 V
INPUT VOLTAGE RANGE. ALLINPUTS ......................................................... -0.5 to VOO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For T A=-40 to +60· C (PACKAGE TYPE E)
500mW
For TA=+60 to +85·C (PACKAGE TYPE E) ..................................... Derate Linearly at 12 mWI"C to 200 mW
For T A=-55 to 100·C (PACKAGE TYPE D) ••••.•••••••••••••••••••••••••••••••••••••••••••••••••••••••• 500 mW
ForTA=+100 to +125·C (PACKAGE TYPE D) ••••••••••••••••••••••••••••••••••• Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ....................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYP.E D ••••. " •.••••••••••••••..••••••••••.••••• " •. " •••••••••••••••••• '" " ••••• -55 to +125·C
PACKAGE TYPE E ••.•.••••..•••..•••••••••••••• , •••••••••••••••••••••• '" •• , ••••••••••••••••• -40 to +85·C
STORAGE TEMPERATURE RANGE (Tstg) •••••••••••.•••••••••••••••••••••••••••••••••••••••••••••• -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
••.•••••••••••••••••••••••••••••••••••••• +285·C
Mode Input High (Mode = 1)
TRANSMITTER SECTION
u
'"0
..J
I~ I~
U
t-
~ca
o
Q.
a:
L"- 34
t-
18
TRANSMITTER
TIMING a CONTROL
...en
..J
o:
I RECEIVER",
u
I
0
..J
U
I len I~
0:
)
IS
(
l
40
soo
25
COPl802
INTERFACE
I
I
I
I
SECTION
...
1.2' Voo
3·VSS
21·CLEAR
3S·NC
38
RECE IVER
aCONTROL
!'-+'+---4/ TIMING
I
_...1
I
I
TRANSMITTER
*
sus
II tl
I::: ~
u
U
I!
I
I
I 2
I Ill!%
I
t-
~ ;:J~ ro
Q.
RECEIVER SUS
*
(5-/21
LL..:- =--:.:-.. :- .:: =-:. .-:...:-.= .= .=;r= .= .=:::: .= .= ..::.:::: :::: .= -=-,::1_1
II
(2S-331
*USER INTERCONNECT
I I
.. C.-2 ••••••
Fig. 1 - Mode 1 block diagram (CDP1800-series microprocessor compatible).
215
RCA CMOS LSI Products
CDP1854, CDP1854C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, un Ie•• otherwlH noted.
CONDITIONS
LIMITS
CHARACTERISTIC
.CDP1854A
.-CI P~AC
UNITS
Vo
VIN VDD
(V)
(V) Min. Typ.· Max. Min. Typ.· Max.
(V)
5
0.01
50
0.02
0.5
200
Quiescent Device Current, 100
pA
0, 10
10
1
200
0,5
0.55
0.4
0.55
1.1
1.1
5
Output Low Drive (Sink) Current, IOL
mA
0.5 0, 10
10
1.3
2.6
Output High Drive (Source) Current, IOH
-0.55 -1.1
-0.55 -1.1
4.6
0,5
5
mA
(Except pins 24 and 25)
-1.3 -2.6
9.5
0,10
10
-
Output High Drive (Source) Current, IOH
Pins 24 and 25
4.6
9.5
Output VOltage Low-Level, YOLo
-
0,5
0,10
Output Voltage High-Level, VOH
0,5
0, 10
5
10
-1.6
-2.8
-3.5
-6.0
-
0,5
-
o 10
5
10
0
-
-
5
10
5
10
4.9
9.9
0
5
10
5
10
3.5
7
5
10
-
-
Input Low Voltage, V,L
0.5,4.5
0.5,9.5
Input High Voltage, V,H
0.5,4.5
0.5,9.5
Input Current, liN
3-State Output Leakage Current, lOUT
Operating Current, 1001#
Input Capacitance, C'N
Output Capacitance, COUT
-
0,5
0, 10
-
0,5
0, 10
0,5
0,10
0,5
0,10
5
10
-
-
5
10
-
-
-
-
-
0.1
0.1
-
-
1.5
3
±1
±2
±1
±10
1.5
6.0
5
10
3.0
12
7.5
15
-
-
-
-
-
-
-1.6
-3.5
-
-
-
0
0.1
-
4.9
5
-
-
-
±1
-
-
-
±1
1.5
3.0
-
-
5
10
7.5
15
3.5
-
mA
V
1.5
-
-
V
fJA
fJA
mA
pF
'Typical values are for TA=25°C.
*IOL =IOH=1 pA.
#Operating current is measured at 200 kHz for VOO=5 V and 400 kHz for VOO=10 V in a COP1800-series microprocessor system,
with open outputs.
RECOMMENDED OPERATING CONDITIONS at TA=Fu" Package Temperature Range
For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
CONDITIONS
LIMITS
CHARACTERISTIC
CDP1854A
CDP1854AC UNITS
VDD
V
Min.
Max.
Min.
Max.
DC Operating-Voltage Range
4
10.5
4
6.5
V
Input Voltage Range
V
VSS
VOO
VSS
VOO
5
200
K bits
200
Baud Rate (Receive or Transmit)
10
400
Isee
-
-
216
-
-
1800-Series Peripherals
CDP1854, CDP1854C
Functional Deflnlllon. for CDP1854A Terminal.
Mode 1
CDP1800-S.rle. Mlcroproce.sor Compatible
SIGNAL: FUNCTION
VOO:
Positive supply voltage
MODE SELECT (MODE):
A high-level voltage at this input selects CDP1800-series
microprocessor Mode operation.
VSS:
Ground
CHIP SELECT 2 (CS2):
A low-level voltage atthis input together with CS1 and CS3
selects the CDP1854A UART.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs (may be externally connected
to corresponding transmitter bus terminal.s).
INTERRUPT (INT):
A low-level voltage at this output indicates the presence of
one or more of the interrupt conditions listed in Table I.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the
received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level
voltage. This output is updated each time a character is
transferred to the Receiver Holding Register.
PARITY ERROR or OVERRUN ERROR (PElOE):
A high-level voltage at this output indicates that either the
PE orOE bit in the Status Register has been set (see Status
Register Bit Assignment, Table II.
REGISTER SELECT (RSEL):
This input is used to choose either the Control/Status
Registers (high input) or the transmitter/receiver data
registers (low input) according to the truth table in Table II I.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
TPB:
A positive input pulse used as a data load or reset strobe.
DATA AVAILABLE (DA):
A low-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SERIAL DATA IN (SOl):
Serial data received on this input line enters the Receiver
ShiftREigister at a point determined by the character
length. A high-level input voltage must be present when
data is not being received.
CLEAR (CLEAR):
A low-level voltage at this input resets the Interrupt FlipFlop, Receiver Holding Register, Control Register, and
Status Register, and sets SERIAL DATA OUT (SOO) high.
TRANSMITTER HOLDING REGISTER EMPTY (THRE):
A low-level voltage at this output indicates that the Transmitter Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character.
CHIP SELECT 1 (CS1):
A high-level voltage at this input together with CS2 and CS3
selects the UART.
REQUEST TO SEND (RTS):
This output signal tells the pe!!E.!!eral to get ready to
receive data. CLEAR TO SEND (eTS) is the response from
the perip~eral. FITS is set to a 10w~level voltage when data is
latched in the Transmitter Holding Register or TR is sel
high, and is reset high when both the Transmitter Holding
Register and Transmitter Shift Register are empty and TR is
low.
SERIAL DATA OUTPUT (SOO):
The contents of the Transmitter Shift Register (start bit,
data bits, parity bit, and stop bit(s) are serially shifted out on
this output. When no character is being transmitted, a high
level is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
TRANSMITTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data input. These may be externally
con~ted to corresponding Receiver bus terminals.
RO/WR:
A low-level voltage at this input gates data from the
transmitter bus to the Transmitter Holding Register or the
Control Register as chosen by register select. A high-level
voltage gates data from the Receiver Holding Register or
the Status Register, as chosen by register select, to the
receiver bus.
•
CHIP SELECT 3 (CS3):
With high-level voltage at this input together with CS1 and
CS2 selects the UART.
PERIPHERAL STATUS INTERRUPT (PSI):
A high-to-Iow transition on this input line sets a bit in the
Status Register and causes an INTERRUPT (INT=low).
EXTERNAL STATUS (ES):
A low-level voltage at this input sets a bit in the Status
Register.
CLEAR TO SEND (CTS):
When this input from peripheral is high, transfer of a
character to the Transmitter Shift Register and shifting of
serial data out is inhibited.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16times the desired transmitter
shift rate.
217
RCA CMOS LSI Products
CDP1854, CDP1854C
T abl e I
SET· (I NT - LOW)
Interrupt Set and Relet Condltlonl
RESET (INT = HIGH)
CONDITION
CAUSE
DA
Read of data
TIME
TPB leading edge
(Receipt of data)
THRE*
(Ability to reload)
Read of status or
write of character
TPB leading edge
THRE·TSRE
Read of status or
TPB leading edge
(Transmitter done)
write of character
~
Read of status
TPB trailing edge
(Neaative edael
eTS
Read of status
TPB leading edge
(Positive edge when THRE • TSRE)
"Interrupts will occur only after the IE bit in the Control Register (see Table IV) has been set.
*THRE will cause an interrupt only after the TR bit in the Control Register (see Table IV) has been set.
Table II - StatuI Regllter Bit Allignment
Bit
Signal
Allo Available at Terminal
7
6
3
2
1
0
TSRE
5
PSI
4
THRE
22-
ES
FE
PE
OE
-
-
-
14
15
15
DA
19-
-Polarity reversed at output terminal.
Bit Signal: Function
O-DATAAVAILABLE (DA):
When set high, this bit indicates that an entire character has
been received and transferred to the Receiver Holding
Register. This signal is also available atTerm. 19butwith its
polarity reversed.
1-0VERRUN ERROR (OE):
When set high, this bit indicates that the Data Available bit
was not reset before the next character was transferred to
the Receiver Holding Register. This signal OR'ed with PE is
output at Term. 15.
2-PARITY ERROR (PE):
When set high, this bit indicates that the received parity bit
does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This bit is updated each
time a character is transferred to the Receiver Holding
Register. This signal OR'ed with OE is output at Term. 15.
3-FRAMING ERROR (FE):
When set high, this bit indicates that the received character
has no valid stop bit, i.e., the bit following the parity bit (if
programmed) is not a high-level voltage. This bit is updated
each time a character is transferred to the Receiver Holding
Register. This signal is also available at Term. 14.
218
4-EXTERNAL STATUS (ES):
_
This bit is set high by a low-jevel input at Term. 38 (ES).
5-PERIPHERAL STATUS INTERRUPT (PSI):
This bit is set high by a high-to-Iow voltage transition of
Term. 37 (f§!). The INTERRUPT output (Term. 13) is also
asserted (INT=low) when this bit is set.
6-TRANSMITTER SHIFT REGISTER EMPTY (TSRE):
When set high, this bit indicates that the Transmitter Shift
Register has completed serial transmission of a full
character including stop bites). It remains set until the start
of transmission of the next character.
7-TRANSMITTER HOLDING REGISTER EMPTY (THRE):
When set high, this bit indicates that the Transmitter
Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character. Setting this bit also sets the THRE output (Term.
22) low and causes an INTERRUPT (INT=low), if TR is
high.
1800-Series Peripherals
CDP1854, CDP1854C
Description of Mode 1 Operation CDP1800-Serle. Mlcroproce..or Compatible (Mode Inpul=VDD)
1. Initialization and Controls
In the CDP1800-series microprocessor compatible mode.
the CDP1854A is configured to receive commands and
send status via the microprocessor data bus. The register
connected to the transmitter bus or the receiver bus is
determined by the RDIWR and RSEL inputs as follows:
Table III - Register Selection Summary
RSEL RD/WR
Function
Low
Low
Low
High Read Receiver Holding Register from
Receiver Bus
High
Low
High
High Read Status Register from Receiver Bus
Load Transmitter Holding Register from
Transmitter Bus
One transmitter clock period after the Transmitter Shift
Register is loaded from the Transmitter Holding Register.
the THRE signal will go low and an interrupt will occur (INT
goes law). The next character to be transmitted can then be
loaded into the Transmitter Holding Register for transmission with its start bit immediately following the last stop
bit of the previous character. This cycle can be repeated
until the last character is transmitted. at which time a final
THRE· TSRE interrupt will occur. This interrupt signals the
microprocessor that TR can be turned off. This is done by
reloading the original control byte in the Control Register
with the TR bit = O. thus terminating the REQUEST TO
SEND (RTS) signal.
SERIAL DATA OUT (SOO) can be held low by setting the
BREAK bit in the Control Register (see Table IV). SDO is
held low until the BREAK bit is reset.
Load Control Register from Transmitter
Bus
RSEL
NO
In this mode the CDP1854A is compatible with a bidirectional bus system. The receiver and transmitter buses are
connected to the bus. CDP1800-series microprocessor 1/0
control output signals can be connected directly to the
CDP1854A inputs as shown in Fig. 2. The CLEAR input is
pulsed. resetting the Control. Status. and Receiver Holding
Registers and setting SERIAL DATA OUT (SOO) high. The
Control Register is loaded from the Transmitter Bus in
order to determine the operating configuration for the
UART. Data is transferred from the Transmitter Bus inputs
to the Control ~sgister during TPB when the UART is
selected CS1·
2 • CS3=ll and the Control Register is
designated (RSEL=H. RD/WR=L). The CDP1854A also has
a Status Register which can be read onto the Receiver Bus
(R BUS 0 - R BUS 7) in order to determine the status of the
UART. Some of these status bits are also available at
separate terminals as indicated in Table II.
2. Transmitter Operation
Before beginning to transmit. the TRANSMIT REQUEST
(TR) bit in the Control Register (see bit assignment. Table
IV) is set. Loading the Control Register with TR=1 (bit
7=high) inhibits changing the other control bits. Therefore
two loads are required: one to format the UART. the second
to set TR. When TR has been set. a TRANSMITTER
HOLDING REGISTER EMPTY (THRE) interrupt will occur.
signalling the microprocessor that the Transmitter Holding
Register is empty and may be loaded. Setting TR also
causes assertion of a low-level on the REQUEST TO SEND
(RTS) output to the peripheral. It is not necessary to set TR
for proper operation for the UART. If desired. it can be used
to enable THRE interrupts and to generate the RTS signal.
The Transmitter Holding Register is loaded from the bus by
TPB during execution of an oU.!2!:!t instruction. The
COP1854A is selected by CS1 • CS2 . CS3=1. and the
Holding Register is selected ~b~gEL=L and RD/~=L.
When the CLEAR To SEND
) input. which can be
connected to a peripheral device output. goes low. the
Transmitter Shift Register will be loaded from the Transmitter Holding Register and data transmission will begin. If
CiS'is always low. the Transmitter Shift Register will be
loaded on the first high-to-Iow edge of the clock which
occurs at least 112 clock period after the trailing edge of
TPB and transmission of a start bit will occur 1/2 clock
period later (see Fig. 3). Parity (if programmed) and stop
bites) will be transmitted following the last data bit. If the
word length selected is less than 8 bits. the most significant
unused bits in the transmitter shift register will not be
transmitted.
CSI
NI
VSS
~CS2
N2
CS3
0
VDD
RO/WR
MRD
CPU
TPB
TPB
INT
EFx
ux
EFx
IT,
---0,
UART
CDPI854A
TNT
,
--<>'
-----
--
DA
/>---
FE
----- - -
I
THRE
--
PE/OE
SOO
BUS
R BUS
CLEAR
CLEAR
MODE
92CS-28460RI
Fig. 2 - Recommended CDP1800-series connection.
Mode 1 (non-interrupt driven system).
3. Receiver Operation
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SOl) input. After detection of the first
high-to-Iow transition on the SOl line. a valid start bit is
verified by checking for a low-level input 7-1/2 receiver
clock periods later. When a valid start bit has been verified.
the following data bits. parity bit (if programmed) and stop
bites) are shifted into the Receiver Shift Register by clock
pulse 7-1/2 in each bit time. The parity bit (if programmed)
is checked and receipt of a valid stop bit is verified. On
count 7-1/2 of the first stop bit. the received data is loaded
into the Receiver Holding Register.lfthe word length is less
than 8 bits. zeros (lOW output level) are loaded into the
unused most significant bits. If DATA AVAILABLE (DA)
has not been reset by the time the Receiver Holding
Register is loaded. the OVERRUN ERROR (OE) status bit is
set. One half clock period later. the PARITY ERROR (PE)
and FRAMING ERROR (FE) status bits become valid forthe
character in the Receiver Holding Register. At this time. the
Data Available status bit is also set and the DATA
AVAILABLE (OA) and INTERRUPT (INT) outputs go low.
signalling the microprocessor that a received character is
219
RCA CMOS LSI Products
CDP1854, CDP1854C
ready. The microprocessor responds by executing an input
instruction. The UART's 3-state bus drivers are enabled
whe!L!he UART is selected (CS1 • CS2 • CS3=1) and
RD/WR=high. Status can be read when RSEL=high. Data
is read when RSEL=low. When reading data. TPB latches
data in the microprocessor and resets DATA AVAILABLE
(DA) in the UART. The preceding sequence is repeated for
each serial character which is received from the peripheral.
4. Perlpherallnterfsce
In addition to serial data in and out. four signals are
provided for communication with a peripheral. The
REQUEST TO SEND (RTS) output signal alerts the
e!!!Pheral to get ready to receive data. The CLEAR TO
SEND (CTS) input Signal is the res onse. si nailing that
the peripheral is ready. The EXTERNAL TA U (ES"1
input latches a perifreral status level. and the PERIPHERAL
STATOS INTEAA PT (PSTj input senses a status edge
(high-to-Iow) and also generates an interrupt. For example.
the modem DATA CARRIER DETECT line could be
connected to the PSI input on the UART in order to signal
the microprocessor that transmission failed because of
loss of the carrier on the communications line. The PSI and
ES bits are stored in the Status Register (see Table II).
Table IV - Control Register Bit Assignment
I Bit
I Signal
I
TR
I BREAK I
Bit Signsl: Function
O-PARITYINHIBIT (PI):
When set high parity generation and verification are
inhibited and the PE Status bit is held low. If parity is
inhibited the stop bit(s) will immediately follow the last data
bit on transmission. and EPE is ignored.
1-EVEN PARITY ENABLE (EPE):
When set high. even parity is generated by the transmitter
and checked by the receiver. When low. odd parity is
selected. .
2-STOP BIT SELECT (SBS):
See table below.
3-WORD LENGTH SELECT 1 (WLS1):
See table below.
4-WORD LENGTH SELECT 2 (WLS2):
See table below.
IE
I WLS21 WLS1 I SBS I
I
o I
PI
I
5-INTERRUPT ENABLE (IE):
When set high THRE. DA. THRE • TSRE. CTS. and PSI
interrupts are enabled (see Interrupt Conditions. Table I).
6-TRANSMIT BREAK (BREAK):
Holds SDO low when set. Once the break bit in the control
register has been set high. SDO will stay low until the break
bit is reset low and one of the following occurs: CLEAR
goes low; CTS goes high; or a word is transmitted. (The
transmitted word will not be valid since there can be no start
bit if SDO is already low. SDO can be set high without
intermediate transitions by transmitting a word consisting
of all zeros).
7-TRANSMIT REQUEST (TR):
When set high. RTs is set low and data transfer through the
transmitter is initiated by the initial THRE interrupt. (When
loading the Control Register from the bus. this (TR) bit
inhibits changing of other control flip-flops).
Bit 4 Bit 3 BIt2
Function
WLS2 WLS1 SBS
0
0
0 5 data bits. 1 stop bit
0
5 data bits. 1.5 stop bits
0
0
0 6 data bits. 1 stop bit
1
1 6 data bits. 2 stop bits
0
0
0
, 7 data bits. 1 stop bit
1 7 data bits. 2 stop bits
0
0 8 data bits. 1 stop bit
8 data bits. 2 stop bits
220
EPE
1800-Serles Peripherals
CDP1854, CDP1854C
DYNAMIC ELECTRICAL CHARACTERISTICS II TA = -4010 +85°C, YDD ±5%, 1,,1,=20 n., YIH=0.7 YDD, YIL =0.3 YDD,
CL =100 pF, ••• Fla. 3.
LIMITS
CHARACTERISTIC
CDP1854A
CDP1854AC
YDD
(Y)
Typ.t
Mlx.*
~t
Mlx.*
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
250
125
100
75
100
75
100
50
175
90
300
150
200
100
200
100
310
155
125
100
125
100
150
75
225
150
450
225
300
150
300
150
250
310
-
-
100
125
-
-
100
125
-
-
100
150
-
-
175
225
-
-
300
450
-
-
200
300
-
-
200
300
-
-
UNITS
Trln.mltt.r nmlng - Mod. 1
Minimum Clock Period
tcc
Minimum Pulse Width:
Clock low level
tCl
Clock High level.
tCH
TPB
tTT
Minimum Setup Time:
TPB to Clock
Propagation Delay Time:
tT_C
Clock to Data Start Bit
tCD
--
TPBto THRE
tTTH
--
Clock to THRE
tCTH
,
ns
ns
ns
ns
ns
ns
ns
ns
I
tTypical values are for T A=25°C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
7~
T CLOCK
---.I--i
t TC
WRITE t
(TPBl
I
t
:.-
I
I
I I
--f i--'CD
I i :
I----~I-Ir---------------------~,,------------~:-----------
~
--l
tTTH :..: _ICTH
,..... I
I
I
I
~L--------------------.".------------rl----------I
--I r-tCD
I
----------~I~
)
SDO
I~I-----------L-I~S-T~D~~~A~B~IT~__
Ttffif
I
LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
* THE HOLDING REGISTER IS LOADED ON THE TRAILING EDGE OF TPB.
* * THE TRANSMITTER SHIFT REGISTER IS LOADED ON THE FIRST HIGH-TO-LOW TRANSITION OF THE
t
CLOCK WHICH OCCURS AT LEAST 1/2 CLOCK PERIOD + ITC AFTER THE TRAILING EDGE OF TPB, AND
TRANSMISSION OF A START BIT OCCURS 1/2 CLOCK PERIOD + ICD LATER.
WRITE IS THE OVERLAP OF TPB. CSI, AND CS3 • I AND CS3, RD I Wft • D.
,2eM - "878
Fig. 3 - Transmitter timing diagram - Mode 1.
221
RCA CMOS LSI Products
CDP1854, CDP1854C
PVNAftjllC ELECTRICAL CHARACTERISTICS el TA = -4010 +85°C, VDD ±50f0,I"lf=20 n., VIH=0.7 VDD, VIL=0.3 VDD,
CL "'100 pF, ... Fig. 4.
LIMITS
CHARACTERISTIC
CDP1854A
VDD
CDP1854AC
Typ.t
Mex.*
(~
~t
Mo.*
310
155
125
250
310
-
-
100
125
-
-
100
125
-
-
100
150
100
150
-
-
220
325
-
-
220
325
-
-
210
300
-
-
240
375
-
-
200
300
-
-
UNITS
Receive, Timing - Mod. 1
Minimum Clock Period
tcc
5
10
Minimum Pulse Width:
Clock low level
5
250
125
100
tCl
10
75
Clock High level
tCH
5
10
100
75
100
125
100
TPB
tTT
5
10
100
150
~
75
5
10
5
10
100
150
75
325
175
Minimum Setup Time:
Data Start Bit to Clock
Propagation Delay Time:
tDC
TPB to DATA AVAilABLE
tTDA
Clock to DATA AVAilABLE
tCDA
Clock to Overrun Error
tCOE
Clock to Parity Error
Clock to Framing Error
50
220
5
10
5
10
110
220
110
210
105
tCPE
5
10
240
120
325
175
300
150
375
175
tCFE
5
10
200
100
300
150
tTypical values are for TA=25°C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
CLOCK 7'/2
SAMPLE
R CLOCK
-i, !..-Ioc*
SOI
CLOCK 7 ~2 LOAD HOLOING REGISTER
'2
---,L,_____
.;..ST.;..A;..:.RT:....B='_
T _ _ _-.;,~biiiJ
STOP BIT I
,...ITOA.......
,,
I I
1-1
,..tCOA
-+i____4j~_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-_-_-_-_------------------------------~~i~l-\~-
DA ________
~/
REAO** ____ ____
~i~---------~\-------------------------~!_+!----
~~
L
......o!
TPB _ _ _ _ _
t
OE
~
I.
----------------------------....li
I,
I ....tCOE
------------------------------------------f.v:==:---ItcPE
"
i-"'1
:~
-------------------------------------------------r.lt~c~~-
h
__
FE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~:_4;_
lIe .. - 31880
II IF A START BIT OCCURS AT A TIME LESS THAN toc BEFORE A HIGH-TO-LOW TRANSITION OF THE CLOCK,
THE START BIT MAY NOT BE RECOGNIZED UNTIL THE NEXT HIGH -TO-LOW TRANSITION OF THE CLOCK.
THE START BIT MAY BE COMfLETELY ASYNCHRONOUS WITH THE CLOCK.
1111 READ IS THE OVERLAP OF CSI,CS3, RD/ViR" AND
IF A PENDING OA HAS NOT BEEN CLEARED BY A READ OF THE RECEIVER HOLDING REGISTER BY THE
TIME A NEW WORD IS LOADED INTO THE RECEIVER HOLDING REGISTER, THE DE SIGNAL WILL COME TRUE.
t DE AND PE SHARE TERMINAL 15 AND ARE ALSO AVAILABLE AS TWO SEPARATE BITS IN THE STATUS REGISTOR
en.o.
Fig. 4 - Mode 1 receiver timing diagram.
222
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1800-Series Peripherals
CDP1854, CDP1854C
DYNAMIC ELECTRICAL CHARACTERISTICS.t TA = -40 to +85°C, VDD ±5%, t r,t,=20 nl, VIWO.7 VDD, VIL=0.3 VDD,
CL =100 pF•••e Fig. 5.
LIMITS
CHARACTERISTIC
VDD
CPU Interface - WRITE Timing - Mode 1
Minimum Pulse Width:
CDP1854A
CDP1854AC
TIl). t
M.x.*
'Im,t
Max.*
5
100
150
100
150
tTT
10
50
75
-
-
5
50
75
50
75
tRSW
10
40
-
-
-75
tow
5
10
25
-100
-100
-75
-50
-35
-
-
5
50
75
50
75
RSEL after Write
tWRS
10
25
40
-
-
Data after Write
5
75
125
75
125
two
10
40
60
-
-
TPB
Minimum Setup Time:
RSEL to Write
Data to Write
Minimum Hold Time:
UNITS
(V)
ns
ns
ns
ns
ns
tTypical values are for TA=25°C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, tr,tf=20 nl, VIWO.7 VDD, VIL=0.3 VDD,
CL=100 pF, lee Fig. 6.
LIMITS
CHARACTERISTIC
CDP1854A
VDD
(V)
CDP1854AC
Min.
Typ.t
Max.*
UNITS
Min.
Typ.t
Max.*
CPU Interface - READ Timing - Mode 1
5
-
100
150
-
100
150
tTT
10
50
75
-
50
75
50
75
10
25
40
-
-
tRST
-
-
Minimum Hold Time:
5
-
RSEL after TPB
tTRS
10
5
Minimum
~ulse
Width:
TPB
Minimum Setup Time:
RSEL to TPB
Read to Data Access Time
5
tRDDA
Read to Data Valid Time
tRDV
RSEL to Data Valid Time
tRSDV
Hold Time:
Data after Read
tRDH
50
75
-
50
75
-
25
40
-
-
-
200
300
200
300
10
100
150
-
-
-
5
10
200
300
200
300
100
150
-
-
5
-
150
225
150
225
10
75
125
-
-
5
50
150
-
50
150
10
25
75
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tTyplcal values are for TA=25°C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
223
•
RCA CMOS LSI Products
CDP1854, CDP1854C
:---ITT--j
TPB* ____________________________________~II~-------
to-- IR5W -----i
:: I
X.. :
l-I WR5 -1
- - -_ _ _ _ _---,1
R5EL
" , . - -_ _
1
j--IDW--l
f:~~~-
'--I'
X::
I
X'-___
IWD~
-----------------------------~I,.----------~~~I-----------+------~,.--------
X~------
I
I
I
C53,C51*~
RD/WR,ffi*~
*
WRITE 15 THE OVERLAP OF TPB, CSI,C53'1 AND C52, RD/WR·o.
Fig. 5 - Mode 1 CPU interface (WRITE) timing diagram.
*---ITT_
TPB ____________________________
~I
_ _ IR5T----l
---------..*
,
R5EL
~,----------
:
1I.--I
R5DV __
~ :~;~-
!..-I TR5 -
:
1
====t!=)>.;-----------
~~:
CSI,CS3
I
II
---fIRDDA ~
I---IRDV_
RD/WR:'~
*,------
'I
I
---f RDH I+-
"~
1"_==========
I
I
u
*
READ IS THE OVERLAP OF C51, C53, RD/WR -I AND C52. O.
92CM-31881
Fig. 6 - Mode 1 CPU interface (READ) timing diagram.
Mode Input Low (Mode = 0)
1= VOO
2,3" VSS
21" MR
500
0
~
- >-
.. ..
'"~ '"~ ., '"'"ill
"
>- >- >- >- >-
23
THRL
TRANSMITTER
BUS
TRANSMITTER SECTION
ill'"
Q::
ct:
0:
0::
0::
a:.
RECEIVER
BUS
RECEIVER "SECTION
92CL-284:;SAI
Fig. 7 - Mode 0 block diagram (Industry standard compatible).
224
RRD
1800-Serles Peripherals
CDP1854, CDP1854C
Functional Definition. for CDP1854A Terminal.
Slandarel Mode 0
SIGNAL: FUNCTION
VDD:
Positive supply voltage.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
VSS:
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
A high-level voltage applied to this Input disconnects the
Receiver Holding Register from the Receiver Bus.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs.
PARITY ERROR (PE):
A high-level voltage at this output Indicates that the
received parity does not compare to that programmed by
the EVEN PARITY ENABLE (EPE) control. This output is
updated each time a character is transferred to the Receiver
Holding Register. PE lines from a number of arrays can be
bused together since an output disconnect capability is
provided by the STATUS FLAG DISCONNECT (SFD) line.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the
received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level
voltage. This output Is updated each time a character is
, transferred to the Receiver Holding Register. FE lines from
a number of arrays can be bused together since an output
disconnect capability Is provided by the STATUS FLAG
DISCONNECT (SFD) line.
OVERRUN ERROR (OE):
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next
character was transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bused together
since an output disconnect capability is provided by the
STATUS FLAG DISCONNECT (SFD) line.
TRANSMITTER HOLDING REGISTER EMPTY (THRE):
A high-level voltage at this output Indicates that the
Transmitter Holding Register has transferred its contents
to the Transmitter Shift Register and may be reloaded with
a new character.
TRANSMITTER HOLDING REGISTER LOAD (THRL):
A low-level voltage applied to this Input enters the character
on the bus Into the Transmitter Holding Register. Data Is
latched on the trailing edge of this signal.
TRANSMITTER SHIFT REGISTER EMPTY (TSRE):
A high-level voltage at this output indicates that the
Transmitter Shift Register has completed serial transmission
of a full character Including stop bites). It remains at this
level antll the start of transmission of the next character.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit,
data bits, parity bit, and stop (blt(s» are serially shifted out
on this output. When no character Is being transmitted, a
high-level Is maintained. Start of transmission Is defined as
the tranSition of the start bit from a high-level to a low-level
output voltage.
TRANSMITTER BUS ('I' BUS 0 - T BUS 7):
Transmitter parallel data inputs.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this Input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level Input voltage.
PARITY INHIBIT (PI):
A high-level voltage at this input Inhibits the parity generation and verification circuits and will clamp the PE output
low. If parity is inhibited the stop bites) will Immediately
follow the last data bit on transmission.
STOP BIT SELECT (SBS):
.
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a
low-level selects one stop bit. Selection of two stop bits
with five data bits programmed selects 1.5 stop bits.
STATUS FLAG DISCONNECT (SFD):
A high-level voltage applied to this Input disables the 3state output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this Input resets the DA
flip-flop.
DATA AVAILABLE (DA):
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SERIAL DATA IN (SOl):
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MASTER RESET (MR):
A high-level voltage at this Input resets the Receiver
Holding Register, Control Register, and Status Register,
and sets the serial data output high.
SBS
TPA I-o--r"""-
WLSI
SCI
L..........._ - '
RRD
WLS2
CPU TPB
CDPlaOD
'fiiRL UART
NO
CDPI854A
mt-----;TSRE
......... . . - - -........... T BUS
'--""""_-tR BUS
92CS-34Soe
Fig. 8 - Moda 0 connection diagram.
225
I
RCA CMOS LSI Products
CDP1854, CDP1854C
WORD LENGTH SELECT 2 (WLS2):
WORD LENGTH SELECT 1 (WLS1):
These two inputs select the character length (exclusive of
parity) as follows:
WLS2
WLS1
Word Length
Low
Low
5 Bits
Low
High
6 Bits
High
Low
7 Bits
High
High
8 Bits
EVEN PARITY ENABLE (EPE):
A high-level voltage at this input selects even parity to be
generated by the transmitter and checked by the receiver. A
low-level input selects odd parity.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16 ti mes the desi red transm itter
shift rate.
holding Register by apPIYin~ a low p-ulse to the fR'A'NSMITTER HOLDING REGISTE LOAD ('fR1i[finputcausing
THRE to go low. If the Transmitter Shift Register is empty
(TSRE is HIGH) and the clock is low, on the next high-tolow transition of the clock the character is loaded into the
Transmitter Shift Register preceded by a start bit. Serial
data transmission begins 1/2 clock period later with a start
bit and 5-8 data bits followed by the parity bit (if programmed) and stop bit(s). The THRE output signal goes
high 1/2 clock period later on the high-to-Iow transition of
the clock. When THRE goes high, another character can be
loaded into the Transmitter Holding Register for transmission beginning with a start bit immediately following the
last stop bit of the previous character. This process is
repeated until all characters have been transmitted. When
transmission is complete, THRE and Transmitter Shift
Register Empty (TSRE) will both be high. The format of
serial data is shown in Fig. 12. Duration of each serial
output data bit is determined by the transmitter clock
frequency (fCLOCK) and will be 16/f CLOCK.
3. Receiver Operation
Description of Standard Mode 0 Operation
(Mode Input=VsS)
1. Initialization and Controls
The MASTER RESET (MR) input is pulsed, resetting the
Control, Status. and Receiver Holding Registers and setting
the SERIAL DATA OUTPUT (SOO) signal high. Timing is
generated from the clock inputs, Transmitter Clock
(TCLOCK) and Receiver Clock (RCLOCK), at a frequency
equal to 16 times the serial data bit rate. When the receiver
data input rate and the transmitter data output rate are the
same, the TCLOCK and RCLOCK inputs may be connected
together. The CONTROL REGISTER LOAD (CRL) input is
pulsed to store the control inputs PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS),
and WORD LENGTH SELECTs (WLSl and WLS2). These
inputs may be hardwired to the proper voltage levels (VSS
or VOO) instead of being dynamically set and CRL may be
hardwired to VOO. The COP1854A is then ready for
transmitter and/or receiver operation.
2. Transmitter Operation
For the transmitter timing diagram refer to Fig. 10. At the
beginning of a typical transmitting sequence the Transmitter
Holding Register is empty (THRE is HIGH). A character is
transferred from the transmitter bus to the Transmitter
226
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SOl) Input. After the detection of a
high-to-Iow transition on the SOl line, a dlvide-by-16
counter is enabled and a valid start bit is verified by
checking for a low-level input 7-1/2 receiver clock periods
later. When a valid start bit has been verified, the following
data bits, parity bit (if programmed), and stop bit(s) are
shifted into the Receiver Shift Register at clock pulse 7-1/2
in each bit time .. 1f programmed, the parity bit is checked,
and receipt of a valid stop bit is verified. On count 7-1/2 of
the first stop bit, the received data is loaded into the
Receiver Holding Register. If the word length is less than 8
bits, zeros (low output voltage leval) are loaded into the
unused most significant bits. If DATA AVAILABLE (OA)
has not been reset by the time the Receiver Holding
Register is loaded, the OVERRUN ERROR (OE) signal is
raised. One-half clock period later, the PARITY ERROR
(PE) and FRAMING ERROR (FE) signals become valid for
the character in the Receiver Holding Register. The OA
signal is also raised at this time. The 3-state output drivers
for OA, OE, PE and FE are enabled when STATUS FLAG
DISCONNECT (SFD) is low. When RECEIVER REGISTER
DISCONNECT (RRD) goes low, the receiver bus 3-state
output drivers are enabled and data is available at the
RECEIVER BUS (R BUS 0 - R BUS 7) ouwuts. Appl~a
negative pulse to the DATA AVAILABL RESET (l)AA')
resets DA. The preceding sequence of operation is repeated
for each serial character received. A receiver timing diagram
is shown in Fig. 11.
1800-Series Peripherals
CDP1854, CDP1854C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = -40 10 +85°C. VDD ±5%. Ir.I,=20 n., V'WO.7 VDD. V,L =0.3 VDD.
CL =100 pF. He FIg •
..
LIMITS
CHARACTERISTIC
CDP1854A
VDD
(V)
~t
Max.*
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
50
40
300
150
20
0
40
20
200
100
75
40
200
100
80
40
150
100
400
200
50
40
60
30
300
150
120
60
300
150
150
70
CDP1854AC
Typ.t
Max.*
UNITS
Interfeee Timing - Mode 0
Minimum Pulse Width:
CRl
tCRl
Minimum Pulse Width:
MR
tMR
Minimum Setup Time:
Control Word to CRl
tcwc
Minimum Hold Time:
Control Word. after CRl
tccw
Propagation Delay Time:
SFD High to SOD
tSFDH
SFD low to SOD
tSFDl
RRD High to Receiver Register
High Impedance
tRRDH
RRD Low to Receiver Register Active
tRRDL
50
150
-
-
300
400
-
-
20
50
-
-
40
60
-
-
200
300
-
-
120
-
200
300
-
-
80
150
-
-
75
ns
ns
ns
ns
ns
ns
ns
ns
I
tTypical values are for TA=2So C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
CONTROL INPUT WORD TIMING
CONTROL WORD
INPUT
'!.
,-I
.....I
t cwc
I
(
CRL
II
~
---.l-tSFDH
I
I
I
I
SFO
\
tCRL
STATUS OUTPUT TIMING
STATUS
OUTPUTS
'!.
tccw---l
• I
:
~
--t
tSFOL
I
l.-
I
I
II
I
RECEIVER REGISTER DISCONNECT TIMING
::~~~------------J¥~----------------.:----------~f~------ltRRDH~
I-t RROL' :
1
RRD ________....
-i
L ____________
92CM-31875
Fig. 9 - Mode 0 interface timing diagram.
227
RCA CMOS LSI Products
CDP1854, CDP1854C
DYNAMIC ELECTRICAL CHARACTERISTICS •• TA = -40 to +85°C. YDD ±5"".Ir.'f=20 nt. YIH=o.7 YDD. YIL=0.3 YDo.
CL=100 pF. 1M Fig. 10.
LlIIITA
CHARACTERISTIC
YDD
(Y)
CDP1854A
'Typ.t
Ma.*
CDP1UdC
Typ.t
M•••*
250
310
-
-
100
125
UNITS
Tr.nlmlHer nmllrg - Mode 0
Minimum Clock Period
tcc
Minimum Pulse Width:
Clock low level
tCl
Clock High level
tCH
THRl
tTHTH
Minimum Setup Time:
fRRL to Clock
tTHC
Data toTHRL
tOT
Minimum Hold Time:
Data after "i'H'RL
tTD
Propagation Delay Time:
Clock to Data Start Bit
tCD
Clock to THRE
tCT
THRl to lJ"HRE
tTTHR
Clock to TSRE
tTTS
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
250
125
100
75
100
75
60
~
175
90
20
-
0
40
20
300
150
200
100
200
100
200
100
310
155
125
100
125
100
150
100
275
150
50
40
100
-
125
-
60
150
175
275
20
-
n8
40
60
-
-
300
450
-
-
200
300
-
200
300
-
-
200
300
-
** TRANSMITTER SHIFT
R GISTER LOADED
tcc
~
tCH.;.+4tCL
T CLOCK
I
tTHC
THRL - - - ,
I
I
I
I
W. : :
I I::
i
n
1--: ~tCD
-tTHTH --,
I!
I
, _tCD
~ ,
II
:I II 1ul:____________________~~----------'~i-~--~--.-Tn
SDO
tTTHR
--l r-I-
-I
_t"eT
Ir'------------------~n~------------------
THRE-------------tl,j!
I
!-e
"""t""';-:-'t
TSRE
-
t
TTS
n
'DT....l.-tTD .....,
----
TBUST
T BUS 0- ______~ DATA
_____________________-*___________________
X--------~:'~------_~
* THE HOLDING REGISTER IS LOADED ON THE TRAILING EDGE OF THRL.
* * THE TRANSMITTER SHIFT REGISTER,IF EMPTT,IS LOADED ON THE FIRST HIGH-lO-LOW TRANSITION OF THE
CLOCK WHICH OCCURS AT LEA~ 112 CLOCK PERIOD+'TlICAFTER THE TRAILING EDGE OF 'i'iiIit, AND TRANSMISSION OF A START BIT OCCURS 1/2 CLOCK PERIOD + 'CD LATER.
92CM-51anRI
Flg_ 10 - Mode 0 transmitter timing diagram.
228
ns
-
50
tTyplcal values are for TA=2S o C and nominal voltages.
*Maxlmum limits of minimum characteristics are the values above which all devices function.
*TRANSMITTER HOLDING
REGISTER LOADED
n8
ns
30
450
225
300
150
300
150
300
150
-
ns
-
60
-
ns
ns
ns
ns
ns
ns
1800-Series Peripherals
CDP1854, CDP1854C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, t"t,=20 n., VIH=0.7 VDD, VIL=0.3 VDD,
CL =100 pF, .ee Fig. 11.
LIMITS
CDP1854A
CHARACTERISTIC
CDP1854AC
UNITS
VDD
(V)
Typ.t
Max.*
T~p.t
Ma••*
Receive, Timing - Mode 0
Minimum Clock Period
tcc
Minimum Pulse Width:
Clock low level
tCl
Clock High level
tCH
DATA AVAilABLE RESET
too
Minimum Setup Time:
Data Start Bit to Clock
tDC
Proeagation Dela~ Time:
DATA AVAILABLE RESET to
Data Available
tDDA
Clock to Data Valid
tCDV
Clock to Data Available
tCDA
Clock to Overrun Error
ICOE
Clock to Parity Error
ICPE
Clock to Framing Error
tCFE
5
10
5
10
5
10
5
10
5
250
125
100
75
100
75
50
25
100
310
155
125
100
125
100
75
40
150
10
50
5
10
5
10
5
10
5
10
5
10
5
10
150
75
225
110
225
110
210
100
240
120
200
100
250
310
-
-
100
125
-
-
100
125
-
-
50
75
-
-
100
150
75
-
-
225
125
325
175
325
175
300
150
375
175
300
150
150
225
-
-
225
325
-
-
225
325
-
-
210
300
-
-
240
375
-
-
200
300
-
-
ns
ns
ns
ns
ns
ns
ns
ns
I
ns
ns
ns
tTypical values are for T A=25° C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
229
RCA CMOS LSI Products
CDP1854, CDP1854C
CLOCK 7 ~2
SAMPLE
R CLOCK
I
-t
2
I
!--tDC*
I
sDI----,~__________~S~~A~R~T~B~IT~________~P~tfr!iJ
I
I
I
I
I
I·
STOP BIT I
~tCDY
::~~~-------------------------------------------------------------------~!-+i-~
•
I
I
•
I
-+1-!I-tCDA
~tDDA
(1
I
:
\
:
• I
.
• I
L-tDD----l
OE**
I
,/------------------i-!j :r
DA
tCOE--r,
1';----
--------------------------------------------------~I~---
tCPE-l---:
PE _______________________________________________________~!--Lr===--I
tCFE~
___
FE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~:_~f====
*
*
*
IF A START BIT OCCURS AT A TIME LESS THAN tDC BEFORE A HIGH-TO-l.DW TRANSITION OF THE CLOCK,
THE START BIT MAY NOT BE RECOGNIZED UNTIL THE NEXT HIGH-TO-LOW TRANSITION OF THE CLOCK. THE START
BIT MAY BE COMP~ETE~Y ASYNCHRONOUS WITH THE CLOCK.
IF A PENDING DA HAS NOT BEEN CLEARED BY A READ OF THE RECEIVER HOLDING REGISTER BY THE TIME A NEW
WORD IS LOADED INTO THE RECEIVER HOLDING REGISTER, THE OE SIGNAL WILL COME TRUE.
92CM- 51877
Fig. 11 - Mode 0 receiver timing diagram.
j 1-
5-8 DATA BITS /
DATA
MSB
-
NEXT DATA WORD
j--STOP BITS
1,1 1/2 OR 2
~~~'TY
92CS-2B463
Fig. 12 - Serial data word format.
230
1800-Series Peripherals
CDP1854, CDP1854C
161-169
(4.089-4.293)
I
182 - 190 .,..,..._ _ _ _ _ _ _ _ _ ___
.826)
92CL-33340
Dimensions and pad layout for CDP1854ACH.
Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10- 3 inch).
The photographs and dimensions represent a chip when it is part
of the wafer. When the wafer is cut into chips, the c/eavageanglas
are 57° instead of 90° with respect to the face of the chip.
Therefore, the isolated chip is actually 7 mils (0.17 mm) larger in
both dimfmsions.
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525 "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
Ouring operation near the maximum supply voltage
limit. care should be taken to avoid or suppress power
supply turn-on and turn-off transients. power supply
ripple. or ground noise; any of these conditions must
not cause VOO-VSS to exceed the absolute maximum
rating.
Input Signall
To prevent damage to the input protection circuit.
input signals should never be greater than VOO nor
less than VSS. Input currents must not exceed 10 mA
even when the power supply is off.
Unuled Inputl
Aconnection must be provided at every inputterminal.
All unused inputterminals must be connected to either
VOO or VSS. whichever is appropriate.
Output Short Clrculta
Shorting of outputs to VOO or VSS may damage CMOS
devices by exceeding the maximum device dissipation.
231
RCA CMOS LSI Products
CDP1855, CDP1855C
8-Blt Programmable
MultiplyIDlvlde Unit
1
2
3
4
25
CI
YL
5
24
YR
ZL
6
7
8
23
22
CLK
ZR
BUS 7
8US 6
BUS 5
CE
CLEAR
CTL
~Jo:r.
mm
28
Veo
27
26
CN.
eN I
STB
9
21
20
ROIW£
10
II
19
18
12
13
17
16
RA2
RAI
RAil
Vss
....14
_ _ _15.....
aus
4
F•• tures:
SUS 3
BUS 2
IUS I
BUS II
•
•
•
•
•
TOP VIEW
92CS- 29985R2
TERMINAL ASSIGNMENTS
Cascadable up to 4 units for32-bit by 32-bit multiply or64 + .32 bit divide
8-bit by 8-bit multiply or 16 + 8 bit divide in 5.6 p.s at 5 Vor 2.8 p.s at 10 V
Direct interface to CDP1800 Series microprocessors
Easy Interface to other 8-bit microprocessors
Significantly Increases throughput of microprocessor used for arithmetic
calculations
The RCA-COP1855 and CDP1855C are CMOS 8-bit
multiply/divide units which can be used to greatly increase
the capabilities of 8-bit microprocessors. They perform
multiply and divide operations on unsigned, binary
operators. In general, microprocessors do not contain
multiple or divide instructions and even efficiently coded
multiply or divide subroutines require considerable memory
and execution time. These multiply/divide units directly
interface to the CDP1800 series microprocessors via the
N-lines and can easily be configured to fit in either the
memory or I/O space of other 8-bit microprocessors.
by add and shift right operations and dividing by subtract
and shift left operations. The device is structured to permit
cascading Identical units to handle operands up to 32 bits.
The CDP1855 and CDP1855C are functionally identical.
They differ in that the CDP1855 has a recommended
operating voltage range of 4 - 10.5 volts, and the
CDP1855C, a recommended operating voltage range of 4
- 6.5 volts.
The CDP1855 and CDP1855C types are supplied in a 28lead hermetic dual-in-line ceramic package (0 suffix) and
in a 28-lead dual-in-line plastic package (E suffix). The
COP1855C is also available in chip form (H suffix).
The multiple/divide unit is based on a method of multiplying
+v
1
t
~
CLEAR
CLEAR
XTAl
NO
NI
N2
TPB
MRii
CDPI802
IT
..
BUS
E
C
ClK
CE
RAO
CI
RAI
CNO
RA2
CNI
STB
RD/WE
Yl CDPI855
ZR
CTl
CO
YR
Zl
BUS
I
Fig. 1 - Circuit configuration for MDU addr&ssed as an 110 device.
232
92CM-34331
1800-Serles Peripherals
CDP1855, CDP1855C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to VSS Terminal)
COP1855 ........................................................................................................ -0.5 to +11 V
CDP1855C ......................................... : ............................................................. -o.5to+7V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................................ -0.5 to VDO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For T A = -40 to +60° C (PACKAGE TYPE E) .............................................................................. 500 mW
For TA = +60 tt).+85°C (PACKAGE TYPE E) ................................................ Derate Llneary at 12 mW/oC to 200 mW
ForTA = -55 to 100°C (PACKAGE TYPE D) .............................................................................. 500 mW
For TA = +100 t.o +125°C (PACKAGE TYPE D) ............................................. Derate Llneary at 12 mW/oC to 200 mW
DEVICE DISSIPATION P.ER OUTPUT TRANSISTOR
ForTA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................... -55 to +125°C
PACKAGE TYPE E .................................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) .•..•••.•..••..••..•.....•..•.•..••••.••••..••.•.••••.•••.••...•.••.•.•••. -85 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 10 s max...................................................... +265°C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +8SoC, VDD
'CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High Level
Input Low
Voltage
Input High
Voltage
Input Leakage
Current
3-State Output Leakage
Current
Operating Current
Input Capacitance
Output Capacitance
CONDITIONS
Vo
VIN
VDD
(V)
(V)
(V)
0,5
5
0, 10
10
100
0.4
0, 5
5
0.5
0, 10
10
1m
4.6
0,5
5
9.5
0, 10
10
IOH
0,5
5
0, 10
10
VOLt
0,5
5
0, 10
10
VOH±
0.5,4.5
5
0.5,9.5
10
V,l
5
0.5,4.5
10
0.5,9.5
V,H
0,5
5
0, 10
10
liN
0,5
0, 5
5
0, 10
0,10
10
lOUT
0
u,O
1001#
0, 10
10
-
-
-
C'N
COUT
-
-
-
-
± 10%, Except as noted
LIMITS
CDP18SSC
CDP18SS
Min.
Typ.Max.
Typ.Max.
Min.
0.02
0.01
200
50
1
200
1.6
3.2
1.6
3.2
5.2
2.6
1.15
2.3
1.15
2.3
2.6
5.2
0.1
0.1
0
0
0.1
0
4.9
5
5
4.9
10
9.9
1.5
1.5
3
3.5
3.5
7
±1
±1
±1
±1
±1
±10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
-
6
5
10
12
7.5
15
-
-
-
-
UNITS
I
pA
mA
V
-
-
-
pA
,
-
1.0
.,
-
-
5
10
7.5
10
mA
pF
-Typical values are for T A = 25° C and nominal VOO.
#Operating current is measured at 3.2 MHz with open outputs.
:j:IOL = IOH = 1 pA.
233
RCA CMOS LSI Products
CDP1855, CDP1855C
OPERATING CONDITIONS at TA = Full Package· Temperature Range. For maximum reliability, operating condltlonllhould
be selected so that operation Is always within the following ranges:
LIMITS
CONDITIONS
VDD
CHARACTERISTIC
CDP1855
j~
-
OC Operating Voltage Range
Input Voltage Range
Maximum Input Clock
Freauencv
Minimum 8 x 8 Multiply
(16 + 8 Divide) Time
5
10
5
10
..
CE
RA2
RAJ
Milt
4
VSS
3.2
6.4
Max.
10.5
Voo
-
5.6
2.8
-
RA0
CNI
26}--++-++-t~
CNe
2:1}-++-++-t~
STB
Fig. 2 - Block diagram of CDP1855 and CDP1855C.
234
CDP1855C
Min.
Max.
6.5
4
VOO
VSS
3.2
-
-
5.6
-
UNITS
V
MHz
/is
1800-Series Peripherals
CDP1855, CDP1855C
FUNCTIONAL DESCRIPTION
The CDP1855 Is a multlply-cllvide unit (MDU) designed to
be compatible with CDP1800 series microprocessor
systems. It can, in fact, be interfaced to most 8-blt
microprocessors (see Fig. 5). The CDP1855 performs binary
multiply or divide operations as directed by the microprocessor. It c~n do a 16N-bit by 8N-bit divide yielding an
eN-bit result plus and eN-bit remainder. The multiply is an
8N-bit by 8N-bit operation with a 16N-bit result. The "N"
represent the number of cascaded CDP1855's and can be 1,
2, 3 or 4. All operations require 8N + 1 shift pulses (See
"DELAY NEEDED WITH AND WITHOUT PRESCALER" Pg.
7).
When multiple MDU's are cascaded, the loading of each
register is done sequentially. For example. the first selection
of register X for loading loads the most significant CDP1855,
the second loads the next Significant, and so on. Registers
are also read out sequentially. This is accomplished by
internal counters on each MDU which are decremented by
STB during each register selection. When the counter
matches the chip number (CN1, CNO lines), the device Is
selected. These counters must be cleared with a clear on
pin 2 or with bit 6 in the control word (See "CONTROL
REGISTER BIT ASSIGNMENT TABLE") in order to start
each sequence of accesses with the most significant device.
The CDP1855 contains three registers, X, Y, and Z, which
are loaded with the operands prior to an operation and
contain the results at the completion. In addition, the
control register must be loaded to initiate a multiply or
divide. There is also a status register which contains an
overflow flag as shown in the "CONTROL REGISTER BIT
ASSIGNMENT TABLE". The register address lines (RAORA 1) are used to select the appropriate register for loading
or reading. The RDIWE and STB lines are used in
conjunction with the RA lines to determine the exact MDU
response (See "CONTROL TRUTH TABLE").
The CDP1855 has a built in clock prescaler which can be
selected via bit 7 in the control register. The prescaler may
be necessary in cascaded systems operating at high
frequencies or In systems where a suitable clock frequency
is not readily available. Without the prescaler select, the
shift frequency is equal to the clock Input frequency. With
the prescaler selected, the rate depends on the number of
MDU's as defined by bits 4 and 5 of the control word (See
"CONTROL REGISTER BIT ASSIGNMENT TABLE").
1. For one MDU, the clock frequency Is divided by 2.
2. For two MDU's the clock frequency Is divided by 4.
3. For 3 or 4 MDU's, the clock frequency is divided by 8.
OPERATION
1. Inltlallzallon and Conlroll
The CDP1855 must be cleared by a low on pin 2 during
power-on which prevents bus contention problems at the
YL, YR and ZL, ZR terminals and also resets the sequence
counters and the shift pulse generator.
Prior to loading any other registers the control register must
be loaded to specify the number of MDU's being used (See
"CONTROL REGISTER BIT ASSIGNMENT TABLE").
Once the number of devices has been specified and the
sequence counters cleared with a clear pulse or bit 6 of the
control word, the X, y, and Z registers can be loaded as
defined in the "CONTROL TRUTH TABLE". All bytes ofthe
X register can be loaded, then all bytes of the Y, and then all
bytes ofthe Z, or they can be loaded randomly. Succcessive
loads to a given register will always proceed sequentially
from the most significant byte to the least significant byte,
as previously described. Resetting the sequence counters
select the most significant MDU. In a four MDU system,
loading all MDU's results In the sequence counter pointing
to the first MDU again. In all other configurations (1, 2, or 3
MDU's), the sequence counter must be reset prior to each
series of register reads or writes.
2. Divide Operation
For the divide operation. the divisor is loaded in the X
register. The dividend is loaded In the Y and Z registers with
the more significant half in the Y register and the less
significant half in the Z register. These registers may be
loaded In any order, and after loading is completed, a
control word is loaded to specify a divide operation and the
number of MDU's and also to reset the sequence counters
and Y or Z register and select the clock option If desired.
Clearing the sequence counters with bit 6 will set the MDU's
up for reading the results.
The X register will be unaltered by the' operation. The
quotient will be in the Z register while the remainder will be
in the Y register. An overflow will be indicated by the
C.O.lO.F. of the most significant MDU and can also be
determined by reading the status byte.
The overflow indicator will be set at the start of a divide
operation if the resultant will exceed the size of the Z
register (8N bits).
The Z register can simply be reset using bit 2 of the control
word and another divide can be done in order to further
divide the remainder.
3. Muiliply Operation
For a multiply operation the two numbers to be multiplied
are loaded in the X and Z registers. The result is in the Yand
Z register with Y being the more significant half and Z the
less significant half. The X register will be unchanged after
the operation is completed.
The original contents of the Y register are added to the
product of X and Z. Bit 3 of the control word will reset
register Y to 0 If desired.
235
I
RCA CMOS LSI Products
CDP1855, CDP1855C
FUNCTIONAL DESCRIPTION OF CDP1855 TERMINALS
CE - CHIP ENABLE (Input):
CLK - CLOCK (Input):
A high on this pin enables the CDP1855 MDU to respond to
the select lines. All cascaded MDU's must be enabled
together. CE also controls the tristate d.O.lO.F., output of
the most significant MDU.
This pin should be grounded on all but the most significant
MDU. There is an optional reduction of clock frequency
available on this pin if so desired, controlled by bit 7 of the
control byte.
CLEAR (Input):
STB - STROBE (Input):
The CDP1855 MDU(s) must be cleared upon power-on with
a low-on this pin. The clear signal resets the sequence
counters, the shift pulse generator, and bits 0 and 1 of the
control register.
When RD/WE is low data is latched from bus lines on the
falling edge of this signal. It may be asynchronous to the
clock. Strobe also increments the selected register's
sequence counter during reads and writes. TPB would be
used in CDP1800 systems.
CTL - CONTROL (Input):
RD/WE - READ/WRITE ENABLE (Input):
This is an Input pin. All CTL pins must be wired together and
to the YL of the most significant CDP1855 MDU and to the
ZR of the least significant CDP1855 MDU. This signal is
used to indicate whether the registers are to be operated on
or only shifted.
C.O.lO.F. - C~A:-:R::-::R=-=-Y'"'O=-:U""T=-:/:':O":":V=ER=FL""O:-:W=(Output):
This signal defines whether the selected register is to be
read from or written to. In 1800 syst~ms use MRD if MDU's
are addressed as 110 devices, MW is used if MDU's are
addressed as memory devices.
This is a tristate output P!.!h It is the CDP18,55 ;t(Ca::":r:::ry":""O"""ut
signal and is connected to CI (CARRY-IN) of the next more
significant CDPl855 MDU, except for on the most significant
MDU. On that MDU it is an overflow indicator and is enabled
when chip enables is true. A low on this pin indicates that an
overflow has occured. The overflow signal is latched each
time the control register is loaded, but is only meaningful
after a divide command.
These input signals define which register is to be read from
or written to. It can be seen in the "CONTROL TRUTH
TABLE" that RA2 can be used as a chip enable. It is
identifical to the CE pin, except only CE controls the tristate
C.O./O.F. on the most significantMDU.ln 1800 systems use
N lines if MDU's are used as 110 devices, use address lines
or function of address lines if MDU's are used as memory
devices.
YL, YR - Y-LEFT, Y-RIGHT:
BUS 0 - BUS 7 - BUS LINES:
These are tristate bi-directional pins for data transfer
between the Y registers of cascaded CDP1855 MDU's. The
YR pin is an output and YL is an input during a multiply and
the reverse is true at all other times. The YL pin must be
connected to the YR pin of the next more significant MDU.
An exception is that the YL pin of the most significant
CDP1855 MDU must be connected to the ZR pin of the least
significant MDU and to the CTL pins of all MDU's. Also the
YR pin of the least significant MDU is tiexd to the ZL pin of
the most significant MDU.
Tristate bl-directional bus for direct interface with CDP1800
series and other 8-bit microprocessors.
ZL, ZR - Z-LEFT, Z-RIGHT:
RA2, RA1, RAO - REGISTER ADDRESS (Input):
ZR - Z-RIGHT:
See Pin 6.
YR - Y-RIGHT:
See Pin 5.
CI-
CARRY IN (Input):
This is an input for the carry from the next less significant
MDU. On the least significant MDU it must be high (VDD)
on all others it must be connected to the CO pin of the next
less significant MDU.
These are tristate bi-directional pins for data transfers
between the "Z" registers of cascaded MDU's. The ZR pin is
an output and ZL is an input during a multiply' and the
reverse is true at all other times. The ZL pin must be tied to
the YR pin of the next more significant MDU. An exception
is that the ZL pin of the most significant MDU must be
connected to the YR pin of the least significant MDU. Also,
the ZR pin ofthe least significant MDU is tied to the YL ofthe
most significant MDU.
These two input pins are wired high or low to indicate the
MDU pOSition in the cascaded chain. Both are high for the
most significant MDU regardless of how many CDP1855
MDU's are used. Then CN1 = high and CNO = low for the
next MDU and so forth.
SHIFT - SHIFT CLOCK:
VSS - GROUND:
This is a tristate bl-directlonal pin. It Is an output on the
most significant MDU. And an input on all other MDU's. It
provides the MDU system timing pulses. All SFfi'FF pins
must be connected together for cascaded operation. A
maximum of the 8N +1 shifts are required for an operation'
where "N" equals the number of MDU devices that are
cascaded.
Power supply line.
236
CN1, CNO - CHIP NUMBER (Input):
VDD-V+:
Power supply line.
1800-Series Peripherals
CDP1855, CDP1855C
CONTROL TRUTH TABLE
INPUTS·
RA1
RAO
(Nl)
(NOl
X
X
X
X
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
X
RA2
(N2)
CE
0
X
1
1
1
1
1
1
1
1
1
X
0
1
1
1
1
1
1
1
1
1
RD/WE
(MRD)
X
X
1
1
1
1
0
0
0
0
0
STB
(TPB)
X
RESPONSE
I
X
NO ACTION (BUS FLOATS)
NO ACTION (BUS FLOATS)
X
X
X
X
1
1
1
1
0
X TO BUS
INCREMENT SEQUENCE
Z TO BUS
COUNTER WHEN
Y TO BUS
STB AND RD = 1
STATUS TO BUS
INCREMENT
LOAD X FROM BUS
LOAD Z FROM BUS
SEQUENCE
LOAD Y FROM BUS
COUNTER
LOAD CONTROL REGISTER
NO ACTION (BUS FLOATS)
I
• ( ) =1800 system signals. 1 =High Level, 0 =Low Level, X =High or Low Level.
CONTROL REGISTER BIT ASSIGNMENT TABLE
I
BUS 7
I
BUS 6
I
BUS 5
1
BUS 4 1
BUS 3
I
BUS 2 1
BUS11
BUSO
,
,~
.~
~
REGISTER
RESET
--
~
~
I
OPERATION SELECT
B1
BO
0
0
NO OPERATION
0
1
MULTIPLY
1
0
DIVIDE
1
1
ILLEGAL STATE
B2 =1, RESET Z REGISTER
B3 =1, RESET Y REGISTER
B5
t
B6
B4
lot MDU'.
1
1
ONE MDU
1
0
TWOMDU'.
0
1
THREE MDU'.
0
0
FOUR MUD's
=1, RESET SEQUENCE COUNTER
B7 =1, SELECT SHIFT RATE OPTIONS:
B7 =0, SHIFT =CLOCK FREQUENCY RATE
# OF MDU's
...
SHIFT RATE
1
CLOCK + 2
2
CLOCK + 4
3
CLOCK + 6
4
CLOCK + 8
STATUS REGISTER
Bit
Output
Status Byte
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 O.F.
O.F. = 1 if overflow (only valid
after a divide has been done)
NOTE: Bits 1 - 7 are read as 0 always
237
RCA CMOS LSI Products
CDP1855, CDP1855C
DELAY NEEDED WITH AND WITHOUT PRESCALER
8N+1 Shifts/Operation at1 Clock Cycle/Shift
S =Shift Rate
N = Number of MDU'.
Number
of
MDU'.
1
2
3
4
No Pre.caler
Machine
Cycle.
Shift. = 8N+1
Needed
Needed·
9
2il NO~
17
2 (1 NOP)
25
3il NO~
33
4 (2 NOPs)
Shift. = S (8N+1)
Needed
18
68
200
264
With Presealer
Machine
Cycl..
Needed"
3 (1 NOP)
9 (3 NOPs)
25 (9 NOPs)
33 (11 NOPs)
Shift
Rate
2
4
8
8
'NOP instruction is shown for machine cycles needed (3/NOP). Other instructions may be used.
CDP1855 INTERFACING SCHEMES
CLEAR
X'fA[
CI:EAIi
MAO
MAl
CLOCK
RAO
RAI
MAX
RA2
!§.Qg
+voo
CI
CNO
CNI
DATA
BUS
l§.M!
TPA
MWR
MRO
TPB
~
REliVE
CE
STB
5!!
~+---------------A8
L---+-----------____ A9
~_+----~---------------~~M
92CS-33113RI
~~~------~----------~
~--~~------~~
1/4CD4011
~--------------------_(;LK(DUT
RESET OUT
1/4 CD4011
Fig. 3 - Required connection for memory
mapped addressing of the MDU.
238
92CS-31870
Fig. 4 -Interfacing the CDP1855 to an 8086
microprocessor as an I/O dellice.
..."'
on
o
1800-Serles Peripherals
CDP1855, CDP1855C
PROGRAMMING EXAMPLE
Fora 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply
201F7C16 by 723C0916:
MEMORY
LOCATION
0000
0002
0003
0005
0006
0008
(lOCl8
0008
0008
OOOA
OOOA
OP
CODE
F830;
A2;
F800;
Be,.
6758;
OOOC
OOOE
OOOE
0010
0010
647C;
6572;
0012
;
0012
0014
0014
001.6
0016
0016
0016
0016
0017
0019
0019
001B
001D
00lF
6509;
oooc
.~,
;
6420;
;
641F;
653C;
LINE
NO.
0001
0002
0003
0004
0005
0006
(1007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
O()19
0020
6759;
0021
ASSEMBLY
LANGUAGE
LDI 030H
PLO R2
LDI OOH
PHI R2
OUT 7; DC 058H
(JUT 4; DC 020H
OUT 4; DC 01FH
OUT 4; DC 07CH
OUT 5; DC 072H
OUT 5; DC
our
O~;CH
5; DC 09H
OUT .,, ., DC
O~)9H
0022
;
E2;
6E60;
6E60;
6E60;
6D60;
6D60;
6D;
0023:
0024
0025
0026
0027
0028
0029
0030
0031
0032
SEX R2
lNF' 6; IRX
INP
INF'
INP
INF'
INP
6', lRX
6; IRX
5; IRX
5', IRX
5
.• LOAD 30 INTO R2.0
• • LOAD 00 INTO R2.1 (R2=0030)
•• LOAD CONTROL REGISTERS
.• SPECIFYING THREE MDU'S,
.• RESET THE Y REGISTER AND
· . SEQUENCE COUNTER
•• LOAD Msa OF x REGISTER
• • WITH 20
•• LOAD NEXT MSB OF X REG
•• WITH IF
•• LOAD Lsa OF x REGISTER
• • WITH 7C
.. LOAD MSB OF Z REGISTER
• • WITH 72
•. LOAD NEXT Msa OF Z REG
• • WITH 3C
•. LOAD LSB OF Z REGISTER
•.• WITH 09
•. LOAD CONTROL. REGISTERS
.• RESETTING Y REGISTERS
•• AND SEQUENCE COUNTERS
· • AND STARTI NG MULTI PL Y
.• OPERATION
0022
00:34
.• COMPLETE LOADING RESULT
•• INTO MEMORY LOCATIONS
0022
0035
... 00:30 TO 0035
0022
0022
0024
0036
0037 STOP
0021
3022;
0033
0038
I
•• MSB OF RESULTS IS STORED
· . AT LOCATION 0030
.• RESULTS=OE558DBA2B5C
BR STOP
END
0000
The result of 201F7C16 x 723C0916 is OE558DBA2B5C =
1576061279727610. It will be stored in memory as follows:
LOC
0030
31
32
33
34
35
BYTE
OE
55
80
BA
2B
5C
BEFORE MULTIPLY
Register X
Register Y
Register Z
MDU1
20
00
72
MDU2
lF
MDU3
7C
QQ
QQ
3C
09
MDU2
1F
55
2B
MDU3
7C
80
5C
AFTER MULTIPLY
Register X
Register Y
Register Z
MDU1
20
OE
BA
239
RCA CMOS LSI Products
CDP1855, CDP1855C
t
V
8
OO BUS
C~OCK
e
~
CNI
Ii
CNIII
E
f----.
C~K
-
§Hi1!f
r-
1I
r--
RAI
RA 2 : - YR
1------+-1 Y~
ZR
Z~
n.
CE
R
RAil
RAI ' - RA2YR --- VOO
:.~.
n1
CT~
~
B
C~K
Y~
CT~
T
"'".. §Hil!i'
Z~
CE
S
CNIII E
RAil
~
1
v.~oo::
CE
If
CT~
1
L-____________
~--~--------------~--~~--------~Vg~
I/O
~EAST
MOST SIGNIFICANT
SE~ECT
SIGNIFICANT
92CM-31850
Fig. 5 - Cascading threa MDU's (CDP1855) In an 1800 system with MDU's being accessed as
I/O ports in programming example.
_iiCL.OCK
~I
l
v
BUS
B~ t
v
/ B R
~O
CNI ,
L
CNe
RAe
I---t CLK
RAIl-SHiFT RA21-r - Yl
YRI--Zl
OT
C.
llD
f--
!!!I:----
cOPless
CE CTl
E"I
BUS
iiiiii
~~~I
BUS B~
t
BUS ~
/ B R
Voo
CNI ,
CNI
CN0
RAil
L CNIII
ClK
RAIl-ClK
SHiPi' RA21-SHiFT
Yl
YRI----l-lYl
Zl
ZR
Zl
c.i.
c.o
cOPless
CE CTl
I I
T
TPB
~
N2
NI
Nil
J
¥t
I
BUS
ZB R
r
r
c:o
BTeS ~Rl
L
RAe
RAIr-RA2e-YRr--ZRr--c.i.r---
cOPless
CE CTl
CNI
CNIII
ClK
l
RAil
RAIl--
SHiFT RA2~
Yl
Zl
c:o
YRI-- 00
ZR
n.
cOPless
CE CTl
I I
I
L~=~~~~~~~~~~~g~~~~~~=±::;:=~92CS-34407
MOST SIGNIFICANT
lEAST SIGNIFICANT
Fig. 6 - Cascading four MDU's (CDP1855).
240
1800-Ser18S Peripherals
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = -4010 +85 C. YDD ±5% Ir. If = 20 nl. YIH = 0.7 YDD. Yll = 0.3 YDD.
Cl = 100 pF (S.. Fig. 7)
0
LIMITS
CHARACTERISTIC-
YDD
(Y)
CDP1855
Min.
1 Typ.*1
Mu.
CDP1855C
Min.
Typ.
Max.
1
UNITS
*1
Operation TIming
Maximum Clock Frequency+
Maximum Shift Frequency
(1 Device)l1
Minimum Clock Width
tCLKO
tClK1
Minimum Clock Period
tCLK
Clock to Shift Prop. Delay
tCSH
Minimum C.1. to Shift Setup
tsu
C.O. from Shift Prop. Delay
tPLH
tPHL
Minimum C.1. from Shift Hold
tH
Minimum Register Input Setup
tsu
Register after Shift Delay
tPLH
tPHL
Minimum Register after Shift Hold
tH
tPLH
tPHL
tPLH
tPHL
C.O. from C.1. Prop. Delay
Register from C.1. Prop. Delay
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
3.2
6.4
1.6
3.2
-
-
4
8
2
4
100
50
250
125
200
100
50
25
450
225
50
25
-20
-10
400
200
50
25
100
50
80
40
1fiO
75
312
156
300
150
67
33
600
300
7~
40
10
10
600
300
100
50
150
75
120
60
3.2
1.6
-
-
-
100
lfiO
250
312
4
-
2
-
-
-
200
300
MHz
50
67
450
600
-
-
-
5
-
-20
10
400
600
100
150
fiO
-
50
-
ns
I
-
100
-
-
-
80
120
-
-Maximum limits of minimum characteristics are the values above which ail devices function.
"Typical values are for T A = 25 0 C and nominal voltages.
+Clock frequency and pulse width are given for systems using the internal clock option of the CDP1855. Clock frequency
equals shift frequency for systems not using the internal clock option.
I1Shift period for cascading of devices is increased by an amount equal to the C.1. to C:O. Prop. Delay for each device added.
CLK
t eLK H - - - o f - - - t -
SI!TfT (PRESCALER
OFF)
Fig. 7 - Operation timing diagram.
241
RCA CMPS LSI Products
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = ·40 to +8S o C, YDD ±S% t r, tf = 20 nl, YIH = 0.7 YDD, YIL = 0.3 YDD,
CL =100 pF (S.. Fig. 8)
LIMITS
CHARACTERISTIC-
YDD
(Y)
CDP18SS
Min.
CDP18SSC
J *l
Typ.
Max.
50
25
150
75
-75
-40
50
25
50
25
50
25
75
40
225
115
0
0
75
40
75
40
75
40
Mln'l Typ.
*1
UNITS
Max.
Write Cycle
Minimum Clear Pulse Width
tClR
tww
Minimum Write Pulse Width
Minimum Data-In Setup
tosu
tOH
Minimum Oata-In-Hold
Minimum Address to Write Setup
tASU
tAH
Minimum Address after Write Hold
5
10
5
10
5
10
5
10
5
10
5
10
-
-
-
50
-
225
-
-
-75
0
-
-
50
50
75
-
-
75
-
-
1CLR
CLEAR' ~------------------------------------------------
,
CE
jj
~\\
RO/WE
\\
rl/
/1
~\
STB
'w://LX
'osu
RA0-2
//L X//////LL1L/ /
--
I'OH
-----..
--./~
'ASU---
.-
--
J
92CM-34841
i--'AH
Fig. 8 - Write timing diagram.
242
/ / / / / £L
* CE=I,ROtW£
WRITE IS OVERLAP OF
=0,ANO STB-I.
75
50
"Typical values are for T A = 25 0 C and nominal voltages.
t
-
150
-Maximum limits of minimum characteristics are the values above which all devices function.
j
~
ns
1800-Serles Peripherals
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS al T A = ·4010 +85 C. VDD ±5% Ir • I, = 20 nl. V,H = 0.7 VDD. V,L = 0.3 VDD.
CL 100 pF (S.. FIg. 9)
0
=
LIMITS
CHARACTERISTIC-
VDD
(V)
CDP18551~
CDP1855
MIn. \ TYP.·\ Max.
MIn. \ Typ.·
UNITS
MajJ,
Read Cycl.
CE to Data Out Active
tcoo
CE to Data Access
tCA
Address to Data Access
tAA
Data Out Hold after CE
tOOH
Data Out Hold after Read
tOOH
Read to Data Out Active
tROO
Read to Data Access
tRA
Strobe to Data Access
tSA
Minimum Strobe Width
tsw
-
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
200
100
300
150
300
150
150
75
150
75
200
100
200
100
200
100
150
75
-
50
25
50
25
-
50
25
-
-
300
150
450
225
450
225
225
115
225
115
300
150
300
150
300
150
200
-
300
450
300
150
225
-
-
450
50
150
225
-
50
-
-
-
-
200
300
200
50
-
-
200
300
150
225
-
-
-
-
-
115
-
-
~25
300
-
-
ns
300
-
I
-Maximum limits of minimum characteristics are the values above which all devices function.
'Typical values are for T A
= 25
0
C and nominal voltages.
CE------"
~/WE--------~--------------------~,
ADVANCE
STB _______
-;-_~......E,QS:ENCE CquNTER
I
RAlIl-2
DOUT
!
'CDO-:
I'
~
I
r
4
1
[
:
liSA rr-'AA-j
r-
________ Vr------~:-------
~
!.
I
1
~"---;-----'ir--,",~
I
\\--I
I
I
I
-jtDOHl--
I
'......;-'_---.1
~~--ii--F")-IN
I 0:
I
I
-\ tCA
IRDOi
I"
"lIDDH
I- :
.. :
'j-
I
IRA
92CM-31852
Fig. 9 - Read timing diagram.
243
RCA CMOS LSI Products
CDP1855, CDP1855C
o
20
40
60
80
100
120
140
160
ISO
224
200 220
203- 211
( 5.156 - 5.359)
221-229
t----------~(:-='5.613-5.817""),-------------~
92CL-33341
Dimensions and pad layout for CDP1855CH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mil (10- 3
inch).
The photographs and dimensions represent a
chip when it is part of the wafer. When the wafer
is cut into chips, the cleavage angles are 57·
instead of 90· with respect to the face of the chip.
Therefore. the isolated chip is actually 7 mils
(0.17 mm) larger in both dimensions.
OPERATING AND HANDLING CONSIDERATIONS
1.
2.
244
Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated Circuits".
Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause VDD - VSS to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protection circuit. input
signals should never be greater than V CC nor less than
Vss.lnput currents must not exceed 10 mAeven when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected 10 either
VCC or VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs 10 VDD. VCC. or VSS may damage
CMOS devices by exceeding the maximum device
dissi palion.
1800-Serles Peripherals
CDP1856, CDP1856C, CDP1857, CDP1857C
4-Bit Bus Buffers/Separators
DIa-
1
16r--VOD
011 -
2
15 f-cs
000-
3
14 f-oBO
001- 4
13 f-OBI
002-
5
003-
6
" f-OB3
0I2-
7
10
vss-
8
12 1--082
I-- MRO
Features:
• Provides easy connection of memory
and I/O devices to CDP1800-series
microprocessor data bus.
• Non-inverting fully buffered data
transfer
9f- 013
TOP VIEW
92CS- 2809'7
TERMINAL ASSIGNMENT
The RCA-CDP1856. CDP1856C. CDP1857. and CDP1857C
are 4-bit CMOS non-inverting bus separators designed for
use in CDP1800-series microprocessor systems. They can
be controlled directly by a 1800-series microprocessor
without the use of additional components.
The CDP 1856 is designed for use as a bus buffer or separator between the 1800-series microprocessor data bus and
memories. The CDP1857 is designed for use as a bus buffer
or separator between the 1800-series microprocessor data
bus and I/O devices. Both types provide a chip-select (CS)
input signal which. when high (1). enables the busseparator three-state output drivers. The direction of data
flow. when enabled. is controlled by the MRD input signal.
In the CDP1856. when the MRD signal == 0 (low). it enables
the three-state bus drivers (DBO - DB3) and outputs data
from the DATA-IN terminals to the data bus. When MRD == 1
(high). it disables the three-state bus drivers and enables
the three-state data output drivers (DOO-D03). thus
transferring data from the data bus to the DATA-OUT
terminals.
In the CDP1857. when MRD == 1. it enables the three state
bus drivers (DBO-DB3) and transfers data from the OAT AIN lines onto the data bus. When MRD == O. it disables the
three-state bus drivers (DBO-DB3) and enables the threestate data output drivers (DOO-D03). thus tranferring data
from the data bus to the DATA-OUT terminals.
The CDP1856 or CDP1857 can be used as a bi-directional
bus buffer by connecting the corresponding DI and DO
terminals (Fig. 2). The liiTli[j output signal from the H\OO
series microproc3ssor has the correct polarity to control
the CDP1856 when this device is used asa memory data bus
buffer/ separator. or the CDP1857 when it is used as I/O bus
buffer/separator. Therefore. the 1800 series microprocessor MRD signal can be connected directly to the l'Vfmjinput
of either device. See Function Tables I and II for use of the
CDP1856 as a memory data bus buffer/separator and
CDP1857 as an 110 bus buffer/separator.
The CDP1856 and CDP1857 are functionally identical to the
CDP1856C and CDP1857C. respectively. The CDP1856 and
COP1857 have a recommended operating-voltage range of
4 to 10.5 volts. and the CDP1856C and CDP1857C have a
recommended operating-voltage range of 4 to 6.5 volts. The
CDP1856. CDPI856C. COP1857 and COP1857C are supplied in 16-lead hermetic. dual-in-line ceramic packages (D
suffix). and in 16-lead plastiC packages (E suffix).
CDP18S6 FUNCTION TABLE ((
For Memory Data lius Separator Operation
CDP18S7 FUNCTION TABLE I
For I/O Bus Separator Operation
DATA BUS OUT
DBO - DB3
DATA OUT
000 - 003
CS
-MRD
DATA BUS OUT
DBO - DB3
DATA OUT
000 - 003
HIGH
IMPEDANCE
0
X
HIGH
IMPEDANCE
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
1
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
1
DATA IN
1
1
--
CS
MRD
0
X
1
1
OATA BUS
HIGH
IMPEDANCE
DATA IN
HIGH
IMPEDANCE
DATA BUS
245
I
RCA CMOS LSI Products
CDP1856, CDP1856C, CDP1857, CDP1857C
D!¢(}-'----;
000
0=---+--<
OIl
OIl
001
0'---+--<
001 ~--1---<
012
on
0020=---+--<
002
on
OIl
003
(Y----t---<
(Y----t---<:.
CDP1856
CDP1857
Fig. 1 - Functional diagrams for CDP1856 and COP1857.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(All voltage values referenced to Vss terminal)
CDP1856, CDP1857 ........ , .................•.•..........................................•........•...•.... -0.5 to +11 V
CDP1856C, CDP1857C .........................•..........•......•..........•.........•...................... -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS .........................................................................-0.5 to Voo + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ...... , ............................................................. , ........ , .... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) .......................... , ...................................... , ......... 500 mW
For TA = +60 to +85° C (PACKAGE TYPE E) ............................................ Derate Linearly at 12 mW/oC to 200 mW
For TA
= -55 to +100°C (PACKAGE TYPE D) .......................................................................... 500 mW
For TA +100 to +125°C (PACKAGE TYPE D) ........................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ......................... , ........... , ......... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D .....•..••..•..••..•.. , ...•.... , .....•....•..• , ..•....•.....•.....•...•..•...•.... , ........•. -55 to +125°C
PACKAGE TYPE E ...... , ........•...•..•.... , .....................••..• , .. , .............•..................•... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tot.) ................... , ............................. " ........................ ""il5 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
246
1800-Serles Peripherals
CDP1856, CDP1856C, CDP1857, CDP1857C
OPERATING CONDITIONS at TA = Full Package-Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
LIMITS
CDP1856
CDP1857
Min.
Max.
CDP1856C
CDP1857C
Min.
Max.
4
Vss
10.5
Voo
4
Vss
CHARACTERISTIC
Supply-Voltage Range
Recommended Input Voltage Range
STATIC ELECTRICAL CHARACTERISTICS at TA
= -40 to +85
0
6.5
Voo
V
V
C, Except as noted
CONDITIONS
LIMITS
CHARACTERISTIC
V,N
UNITS
CDP1856
CDP1857
UNITS
CDP1856C
CDP1857C
Vo
(V)
(V)
Voo
(V)
Min.
Typ."
Max.
Min.
Typ."
Max.
5
50
Quiescent Device
Current,
100
-
0,5
0,10
5
10
-
1
10
10
100
-
-
Output Low Drive
(Sink) Current,
0.4
0.5
0,5
0,10
5
10
1.6
2.6
3.2
5.2
-
1.6
3.2
10L
-
-
-
Output High Drive
(Source Current),
4.6
9.5
0,5
0,10
5
10
-1.15
-2.6
-2.3
-5.2
-
-1.15
-2.3
10H
-
Output Voltage
Low-Level.
0,5
0,10
5
10
0
0
0.1
0.1
0
0.1
-
-
0,5
0,10
5
10
4.9
9.9
5
10
-
4.9
5
VOH
-
-
VOL
-
-
-
5
10
-
1.5
V,H
5
10
3.5
7
-
1.5
3
0.5,9.5
0.5,9.5
-
-
V,L
0.5,4.5
0.5,9.5
-
-
0,5
0,10
5
10
-
-
-
±1
±1
±1
lIN
Any
Input
-
-
0,5
0,10
0,5
0,10
5
10
-
50
150
100
300
50
100
100'.
-
-
-
Output Voltage
High-Level.
Input Low
Voltage,
Input High
Voltage,
Input Leakage
Current,
Operating Current,
-
-
-
3.5
-
Input Capacitance,
C'N
5
7.5
Output Capacitance,
10
15
COUT
"TYPical values are for TA - 250 C and nom mal voltage .
• Operating current measured in a CDP1802 system at 3.2 MHz with outputs floating.
• 10L
10H
1 IJA.
=
-
-
IJA
I
mA
mA
V
V
IJA
-
-
IJA
5
10
'7.5
15
pF
pF
=
247
\
RCA CMOS LSI Products
CDP1856, CDP1856C, CDP1857, CDP1857C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C, Voo =± 5%,
V,H = 0.7 Voo. V,L = 0.3 Voo, tr , t, = 20 ns, Q = 100 pF
CHARACTERISTIC
Voo
(V)
Propagation Delay Time:
M'RD or CS to DO,
M'RD or CS to
5
10
5
10
5
10
5
10
te~
DB,
tea
01 to DB,
tla
·DB to DO
LIMITS
CDP1858
CDP1858C
CDP1857
CDP1857C
Typ.Typ.Max.
Max.
tao
150
75
150
75
100
50
100
50
225
125
225
125
150
75
150·
75
150
225
150
225
100
150
-
-
-
-
100
-
150
-
OJ:
~
CS
'L.......,
-
X
H'EB
DB
DB
r:'EB
90%
10%
DO
(al ENABLE TO DB TIME
H'ED
~
'EO
90%
I 10%
(bl ENABLE TO DO TIME
\-----.-~
-t. t;:]:
DI
DB
=:====~==,lf...VALID
DATA
.C'"
1--
PULARITIES ARE REVERSED FOR CDPI857
Fig. 2 -
248
~'D
DATA
~
(bl DB TO 00 TIME
(b I DI TO DB TIME
*
\'---
: - J,,,.r.::: j .~
CO
92CM-280nR2
Timing diagrams for CDP1856 or CDP1857 (see footnote).
ns
ns
-Typical values are for TA = 250 C and nominal voltages.
cs - - - J
,!-....,
UNITS
ns
ns
1800-Series Peripherals
CDP1856, CDP1856C, CDP1857, CDP1857C
TYPICAL APPLICATIONS
COPI856
OR
COPI857
000-003
MRii
CS
92CS-28096
Fig. 3 - COP1856, COP1857 bidirectional bus buffer operation.
1
MRo
CoPI800
SERIES
CPU
MWR
NO.NI.
OR N2
VOO
DATA
8US
1
cs
cs
COPIB57
CoPIB56
000-003
oB¢-083
(4)
010'-013
~
0013-003
~
~
(41
aJ
~
MRo
COP 1857
0013-003
MWR
/*--
MRo
"
coP 1856
or¢-OI3
OB¢-083
DO
~
'"::>
.
(4)
(81
14)
(41
MRo
;e
IIO
or
COPI821
RAMS
(41
08¢-OB3
0113-013
MRii
(4)
00¢-003
~
kf¢
"----
141
0I¢-0I3
CS
CS
j
~D
or
COPI821
RAMS
14)
oB¢-OB3
141
00
MWR +-
92CM·28098R 2
Fig. 4 - COP1856 and COP1857 bus separator operation.
249
RCA CMOS LSI Products
CDP1858, CDP1858C, CDP1859, CDP1859C
CLOCK
16
Voo
MAO
15
ENABLE
14
MA2
CSO
CSI
4
5
13
12
MA3
CS2
CS3
6
7
"10
Vss
8
MAl
~
CEI
ill
~
TOP VIEW
4-Bit Latch and Decoder
Memory Interfaces
Features:
• Provides easy connection of
memory devices to CDP1802
microprocessor
• Non-inverting fully buffered data
transfer
9CCS~31953
CDP1858
TERMINAL ASSIGNMENT
RCA-CDP1858, CDP1858C, CDP1859, and CDP1859C are
CMOS 4-bit latch decode circuits designed for use in
CDP1800 series microprocessor systems. These devices
have been specifically designed for use as memory-system
decoders and interface directly with the 1800-series microprocessor multiplexed address bus at maximum clock
frequency.
The CDP1858 and CDP1859 are functionally identical to the
CDP1858C and CDP1859C, respectively. The CDP1858 and
CDp'1859 have a recommended operating-voltage range of
4 to 10.5 volts, and the CDP1858C and CDP1859C have a
recommended operating-voltage range of 4 to 6.5 volts.
The CDP1858 interfaces the 1800-series microprocessor
address bus and upt032 CDP1822 256 x4 RAM's to provide
a 4K byte RAM system. No additional components are required. The CDP1858 generates the chip selects required
by the CDP1822 RAM. The chip select outputs are a function of the address bits connected to inputs MAO through
MA3.
The MAO-MA3 address bits are latched at the trailing e~
of TPA (generated by the CDP1802). When ENABLE=1 (Voo), the CS outputs=O (V ss), and the CE outputs=1. When ENABLE-O, the outputs are enabled and
correspond to the binary decode of the inputs. The ENABrrinput can be used for memory system expansion.
The CDP1858 is also compatible with non-multiplexed address bus microprocessors. By connecting the CLOCK
input to 1 (Voo), the latches are in the data following mode
and the decoded outputs can be used in general-purpose
memory-system applications.
The CDP1859 interfaces the 1800-series microprocessor
address bus and up to 32 CDP1821 1024 x 1 RAM's to
250
provide a 4K byte RAM system. The CDP1859 generates the
chip selects required by the CDP1821 RAM. Thechip select
outputs are a function of the address bits connected to
inputs MA2 and MA3. The address bits connected to inputs
MAO and MA 1 are latched by the trailing edge of TPA (generated by the 1800-series microprocessor) to provide the
two additional address lines required by the CDP1821 when
used in a CDP1800 series microprocessor-based system.
When 1:"NAB[E=1, the CE outputs are 1's; when NABLE=O, and CE outputs are enabled and correspond to
the binary decode of the MA2 and MA3inputs. ~
does not affect the latching or state of outputs A8, A8, A9, or
A9.
The CDP1858, CDP1858C, CDP1859, and CDP1859C are
supplied in 16-lead, hermetic, dual-in-line side-brazed ceramic packages (D suffix) and in 16-lead dual-in-line plastic
packages (E suffix).
16
CLOCK
voo
MAO
2
15
~
MAl
3
14
MA2
AS
4
13
MA3
A8
12
CEO
1<9
CEI
A9
7
"
VSS
8
9
10
m
m
TOP VIEW
92CS-31954
CDP1859
TERMINAL ASSIGNMENT
1800-Serles Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
Fig. 1 -
MAXI~UM
CDP1858 -
Functional diagram.
Fig. 2 -
CDP1859 - Functional diagram.
RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (Voo)
(Voltage referenced to Vss Terminal)
CDP1858. CDP1859 ......................................................................................... --{l.5 to +11 V
CDP1858C. CDP1859C ..................................................................•................•... --{l.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS .........................................................................--{l.5 to Voo + 0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................................................. ±100 j.lA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ........................................................................... 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ............................................ Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100°C (PACKAGE TYPE D) .......................................................................... 500 mW
For TA +100 to +125°C (PACKAGE TYPE D) ........................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D. H .•...............•..•..•.......•..•.........•...•.•...•...•...........•..........•.......-55 to +125°C
PACKAGE TYPE E ..............................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Toto) ...........................................................................-65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
251
•
RCA CMOS LSI Products
CDP1858, CDP1858C, CDP1~59, CDP1859C
OPERATING CONDITIONS at TA = Full Package-Temperature Range.
For maximum reliability. operating conditions should be selected so that operation is always
within the fol/owing ranges:
LIMITS
Min.
Max.
CDP1858C
CDP1859C
Min.
Max.
4
Vss
10.5
Voo
4
Vss
CDP1858
CDP1859
CHARACTERISTIC
Supply-Voltage Range
Recommended Input Voltage Range
STATIC ELECTRICAL CHARACTERISTICS at TA
= -40 to
CONDITIONS
CHARACTERISTIC
LIMITS
CDP1858C
CDP1858
CDP1859C
CDP1859
Max.
Max.
Min.
Typ."
Min.
Typ."
Vo
(V)
Y,N
(V)
Voo
(V)
-
0,5
0,10
5
10
-
0.1
1
-
5
50
-
-
-
-
1.6
3.2
-
-
-
-
-2.3
-5.2
-
·-1.15
-2.3
-
-
°
°
0.1
0.1
-
0
0.1
-
-
4.9
5
-
-
-
-
100
Output Low Drive
(Sink) Current,
IOL
0.4
0.5
0,5
0,10
5
10
1.6
2.6
3.2
5.2
Output High Drive
(Source Current),
IOH
4.6
9.5
0,5
0,10
5
10
-1.15
-2.6
-
0,5
0,10
0,5
0,10
5
10
5
10
-
-
V,H
0.5,4.5
0.5,9.5
0.5,4.5
0.5,9.5
-
5
10
5
10
3.5
7
liN
Any
Input
0,5
0,10
5
10
-
-
0,5
0,10
5
10
-
-
-
-
-
Input Low
Voltage,
Input High
Voltage,
Input Leakage
Current,
VOL
VO H
V,L
Operating Current,
10 01.
Input Capacitance,
C 'N
Output Capacitance,
COUT
-
10
100
UNITS
f.lA
mA
mA
V
4.9
9.9
5
10
-
-
-
1.5
-
-
1.5
3
-
-
-
-
3.5
-
-
-
10- 4
10-'
±1
±2
-
10-4
-
±1
50
150
100
300
-
50
100
-
-
-
-
f.lA
-
-
5
7.5
-
5
7.5
pF
-
-
10
15
-
-
-
pF
-
"Typical values are for T A = 25° C and nominal voltage.
e IOL = IOH = 1 f.lA .
• Measured in a CDP1802 or CDP1804 system at 3.2 MHz with open outputs.
252
V
V
6.5
Voo
+85°C. Except as noted
Quiescent Device
Current,
Output Voltage e
Low-Level
Output Voltage e
High-Level
UNITS
-
V
f.lA
l800-Series Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo
V1H = 0.7 Voo, V1l = 0.3 Voo, Cl = 100 pF, See Fig. 3.
Minimum Setup Time, Memory
Address to Clock, tMACl
Minimum Hold Time, Memory
Address After Clock, tClMA
Minimum Clock Pulse
Width, tClCl
Propagation Delay Times:
5
10
5
10
5
10
5
10
5
10
5
10
Clock to Outputs, tClO
Memory Address
to Outputs, tMAO
ENABLE to
Outputs, tEO
5%, t" tf
= 20 ns,
LIMITS
Voo
(V)
CHARACTERISTIC
±
UNITS
CDP1858C
CDP1858
Min.
Typ.
Max.
Min.
Typ.
Max.
-
40
25
25
10
75
40
-
25
40
-
-
0
25
-
-
-
25
10
0
0
50
25
-
50
75
-
-
-
-
150
75
-
150
225
125
225
125
-
150
-
-
-
-
75
125
65
200
100
-
150
125
-
-
ns
ns
225
225
-
ns
200
-
Typical values are for T A = 25° C and nominal voltages.
Maximum limits of minimum characteristics are the values above which all devices function.
I
ns
.-
I
---I
---I
CSo-CS3-------'-"I.r-------------'--\lr-----------t EO
tEO
~-~--------------~(~b~)E=N~AB~L~E~T~O~OU~T~PU~T~S~P~RO~P~O=E~LA~Y~T~IM~IN~G~I~-------------92CM-31956
Fig. 3 -
CDP1858 timing diagram.
253
RCA CMOS LSI Products
CDP1858, CDP1858C, CDP1859, CDP1859C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85 0 C, Voo
V'H = 0.7 Voo, V'l = 0.3 Voo, Cl = 100 pF, See Fig. 4.
LIMITS
CDP1859
CDP1859C
Min.
Typ.
Max.
Min.
Typ.
Max.
Voo
(V)
CHARACTERISTIC
-
5
10
5
10
5
10
Minimum Setup Time, Memory
Address to Clock, tMACl
Minimum Hold Time, Memory
Address After Clock, tClMA
Minimum Clock Pulse
Width, tClCl
Propagation Delay Times:
-
5
10
5
10
5
10
5
10
5
10
Clock to Address, tClA
Clock to
e5HIP ENABLE, hCE
Memory Address to
Address, tMAA
Memory Address to
CHIP ENABLE, tMACE
ENABLE to
CHIP ENABLE, tECE
± 5%, t" tf = 20 ns,
-
-
-
25
10
0
0
50
25
40
25
25
10
75
40
125
65
175
90
100
50
150
75
125
65
200
100
275
140
150
75
225
125
200
100
-
25
40
-
0
25
-
-
-
-
50
75
-
200
-
125
-
-
-
175
-
100
275
150
-
-
-
150
225
-
-
-
-
-
125
-
200
Typical values are for T A = 25 C and nominal voltages.
Maximum limits of minimum characteristics are the values abpve which all devices function.
0
--j
CLOCK
MAO- MA3
IClCL
r-
II
.r:-::
1- I CLA
A8,AiI,A9.~
---
II
lMACLrrCLMA
X
X
r-
I
~
---
ICLC~~
X
I
-
IMAA
-- 'MMA
-
'MACE ..-
'I
I MACE
( a ) MEMORY AODRESS TO OUTPUT T IMING
--+ECE~
(b) CHIP ENABLE TO CRTP El'lA!![£ PROP DELAY
Fig. 4 -
254
CDP1859 liming diagram.
-
l-
-
UNITS
ns
ns
ns
ns
1800-Serles Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
CDP1858 DECODE TRUTH TABLE
ENABLE
0
0
0
0
0
0
0
0
1
DATA INPUTS
MA1
MAO
0
0
1
1
MA3
0
0
1
0
1
0
1
MA2
0
1
0
1
1
X
X
CSO
CS1
CS2
CS3
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
NOT AFFECTED
BY MA3, MA2
0
0
0
0
CEO
CE1
CE2
CE3
NOT AFFECTED
BY MAl, MAO
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
0
1
x = MA3, MA2, MAl, MAO DON'T CARE
I
CDP1859 DECODE TRUTH TABLE
ENABLE
0
0
0
0
0
0
0
0
1
DATA INPUTS
MAO
MA1
0
0
1
1
MA3
0
0
1
1
0
1
0
1
MA2
0
1
0
1
X
X
A8
A9
AS
A9
0
0
1
1
0
1
0
1
1
1
0
0
1
0
1
0
NOT AFFECTED
BY MA3, MA2
NOT AFFECTED BY
-
CEO
-
CE1
-CE2
-CE3
NOT AFFECTED
BY MAl, MAO
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
rnABIT
x = MA3, MA2, MAl, MAO DON'T CARE
255
RCA CMOS LSI Products
CDP1858, CDP1858C, CDP1859, CDP1859C
f---r-
~
g
~
-g
r-
MAO-1
MWR
CPU
COPIB02
MRO
em
TPA
MAO-?
L-~4~_~41:~.;US~D~-~i:ti~tt~~4 ~BU~S;0~-3~~~~~~~
P
I
•
l-
2
2
C52
t- fljffi i
t-CSi 22
•
CS2i--
4
'~11~
lli
MWR
MWR c
~
MAO-?
C
D
L. MRD
~-,I csi
D
f
•~
CS2
L--
L. MRD
t-- ESi
I
f
•~
~
MAO-?
MWR C
D
'-MAO by setting SCO high
(VDDl, and SCl low (Vssl, permitting data transfer. Data
will be loaded on the subsequent 8 TPB input signals.
DMAO will be terminated on the ninth sync pulse, at which
time SCO should be set low (Vssl prior to the next TPB
command. Timing is illustrated in Figs. 3 and 5. The DMAO
output Signal may be connected to the DMA OUT Terminal
of the CDP1800-series microprocessor, which responds as
discussed above.
INT:
An active low (Vssl output signal two horizontal cycles
prior to the display, as shown in Figs. 3 and 5. This signal is
the output of the "open drain" of an n-channel transistor
and requires an external pull-up resistor to V~ The iiii'f
output signal is normally connected to the
ERRUPT
input terminal of the CDP1800-series microprocessor. In a
CDPl800-series microprocessor based system, 29 machine
cycles occur from initiation of an lJirt until theD'fiiiAO:
260
An active high timing pulse occurring once for every 8
clock pulses. The TPB Signal is used as a strobe for gating
the output of the counter and for loading data into the data
register. It is normally connected to the TPB terminal ofthe
CDP1800-series microprocessor.
COMPSYNC:
An active low output signal resulting from the exclusive
"OR" of the output of the horizontal and vertical counters.
COMP SYNC can be combined with the VIDEO output to
form a composite video Signal.
The COMP SYNcoutput frequency and pulse duration are
determined by the TPA and TPB input Signals. A horizontal
sync pulse is initiated by the trailing edge of the TPB Input
signal following the 13th or 14th TPA input, as determined
by the status of the SCO and SCl input signals, and is
terminated on the leading edge of the subsequent second
count of the TPA input.
Vertical timing is generated coincident with the 262nd
horizontal timing pulse and is present for six horizontal
clock cycles. Idealized timing is illustrated in Figs. 2 and 4.
VIDEO:
An active high output from the most significant bit of the
8-bit PIS data register. It is used to determine the luminance
level and may be combined externally with the COMP
SYNC output signal to form a composite video signal.
RESET:
An active low input signal which initializes the counters,
inhibits the display, and places all control outputs in the
high (VDDl state. Refer to Fig. 3.
1800-Serles Peripherals
CDP1861C
FUNCTIONAL DESCRIPTION OF CDP1861C TERMINALS (Conl'd)
RESET (Conl'dt
D1D - D17:
The RESET terminal is a Schmitt-trigger-type input which
permits the use of an external RC network to provide a
power-on reset.
Input signals to the data register. Data are loaded during
the high-to-Iow transition of the CIT< only when TPB, DISP
ON, and SCO are high (VDD), SC1 is low (VSS), and the
CDP1861C is enabled.
EFX:
An active low output signal which occurs for a period of
four horizontal cycles prior to the beginning and end of the
128-line display window, as illustrated in Figs. 2 and 4. The
signal can be used by the program software routines to
indicate the boundaries of the display area. It is.!!.2!1I)!!!l
connected to a CDP1800-series microprocessor EF1-EF4
FLAG input terminal.
DISP ON, DISP OFF:
Active high input signals that control the display. When
enabled by pulsing DISP ON high (VDD), data transfers,
DMA, and interrupt requests are permitted. These
operations are inhibited by the low-to-high transition ofthe
DISP OFF input signal if DISP ON is low (VSS). The RESET
signal also inhibits the display. When inhibited, the internal
counters remain operational. Sync and display status
signals are generated. Video output becomes low when the
register is emptied. Table I indicates the enable/disable
conditions.
The DISP ON and DISP OFF signals may be provided by the
I/O commands (N bits) of the CDP1800-series
microprocessor.
TABLE I
SIGNAL
STATE
RESET
INVALID
DISPLAY
ENABLE
DISPLAY
DISABLE
RESET
L
L
DISPON
L
H
DISPOFF
H
...rL
X
H
L
X
X
...r
The data input signals are normally connected to the 8-bit
microprocessor data bus.
SCD, SC1:
Input 'signals used to synchronize the operation of the
CDP1861 C witt its controller. They should be initiated prior
to the TPA input and terminate after the TPB input pulse.
These control signals are sampled at two different times: 1)
During the horizontal sync output when the TPA input is
present, the CDP1861 C expects to see SC1 = 1 (VDD) and
SCO = 0 (VSS). Any other combination will result in the
skipping of one of the normal 14 cycles per line. This
feature allows the CDP1800-series microprocessor to force
initial instruction fetch/execute sync with the CDP1861C,
and assures sync in case it is later lost for any reason. 2) In
the 6 cycles following the CDP1861C DMAO assertion, the
CDP1861 C expects to see SC1 = 0 and SCO = 1. Any other
combination will prevent the CDP1861 C from loading data
from the bus.
These signals may be connected to the STATE CODE
(SCO, SC1) outputs of the CDP1800-series microprocessor.
Ci:EAR:
The output of the Schmitt trigger (reset input circuitry)
provides high speed transitions that may be used to reset
other devices. It may be connected to the CLEAR terminal
of the CDP1800-series microprocessor.
VDD, VSS:
VDD is the positive supply voltage terminal, VSS is the
negative supply voltage terminal and is normally connected
to ground.
TPA ... L.IUUL... L.IUU1.JUUL... L.IL..IU1.JL.JUU1....lL.JUUL.lLJIUIUL.lL.IUU
TPB .IL.IUIUL... LJUI.JL..IUIUI....IL.lLJIUIUL... L.IU
TIft
,~
-II-------------------
________________________________________
DMAD -----------------------------------------------\\__________~,--~
SCI
sea
_______________________________________'r--------------
--J~L,
__________________________________________
-I----------~L.-
..Jr
....I....--.L..I,..--,L..I,.....""."~""1......·-Lrl.....I,....."".",....."".",.....",,.,,'L....~·-1.._ri_'r'1L.___________
92CM-29461RI
Fig. 2 .. Horizontal sync timing diagram.
261
I
RCA CMOS LSI Products
CDP1861C
Voo
Vss
Voo
92CS-29468RI
Fig. 3 - Reset transfer characteristics.
APPLICATION INFORMATION (CDP1861C DIRECTLY CONTROLLED BY THE CDP1800-SERIES MICROPROCESSOR)
Figure 5 shows a simple graphic display system using the
CDP1800-series microprocessor and the CDP1861C. The
CDP1861C uses both the INTERRUPT and direct memory
access (DMA) output channel of the microprocessor for
display refresh. The microprocessor specifies the area of
memory displayed via the interrupt routines, and the DMA
output channel is the mechanism which transfers the data
from memory to the CDP1861 C via the 8-bit data bus. The
data are then shifted out one bit at a time at the clock
frequency to generate the video (VIDEO) signal.
The composite sync (COMP SYNC) signal creates a 262line-per-field, 60-field-per-second non-interlace video
picture. The non-interlaced picture frame for this display
consists of two even fields of 262 horizontal lines each. This
format differs slightly from the National Television Standard
(NTSC) which has a 525-line interlaced picture frame of one
odd field and one even field. The vertical sync pulse
generated at COMP SYNC of the CDP1861C has no
equalizing pulses but is serrated to maintain horizontal
synchronization during the vertical blanking time. The
VIDEO and COMP SYNC pulses are resistively coupled to
create the composite video, which can be supplied directly
to a video monitor, a modified TV receiver, or a FCC
approved rf modulator.
A cloCk source of 3.58 MHz, the NTSC color frequency, if
divided by 2, may be used for some applications in place of
the 1.76-MHz crystal shown in Fig. 5. Deviations from the
NTSC frequencies are as follows:
The user should determine which choice of frequencies
provides an optimal cost/performance trade-off for his
application. Genera"y, video CRT's are more sensitive to
line frequency accuracy than to field frequency accuracy.
The display is a bit map of memory. Each bit in the display
memory corresponds to one spot on the video screen.
Logical 1 (VDD) bits in memory correspond to white or
lighted spots in the display. The highest resolution that may
be produced is 128 vertical by 64-horizontal segments. This
.resolution requires 1024 bytes of memory for the display.
The upper left-most spot that can be displayed on the video
screen is the most significant bit of the first byte in the
display refresh memory buffer. The starting location of the
display buffer is initialized in the INTERRUPT routine and
may be anywhere in addressable memory (ROM, RAM, or
both). The lower right-most spot that can be displayed is the
least significant bit of the last byte of the display bit map.
For each of the 128 horizontal display lines, 8 bytes of
memory are sequentially accessed and displayed from left
to right on the video screen. Adjacent illuminated spots
262
appear contiguous both In the horizontal and In the vertical
directions. A" display manipulations are accomplished by
changing the data within the display buffer or by changing
display buffers.
To control theCDP1861C as shown in Fig. 5, theCDP1800series microprocessor must be in synchronization with the
CDP1861 C during the display window. Exactly six machine
cycles must be executed beyond the eight DMA cycles
during each line, and an even number of cycles (282 x 14)
must be executed from the start of one display window to
the start of the next. These requirements insure that the
DMA burst wi" not be delayed one cycle waiting for an
instruction to finish - this delay would cause jitter on the
screen. These requirements can be accomplished In two
steps: 1) the main program must not execute any 3-cycle
instructions (i.e., SKIP, LONG BRANCHES, and NOP), and
2) the interrupt routine, including the Interrupt cycle itself,
must employ an even number of cycles, and must be
synchronized with the DMA bursts. There must be 29 cycles
between the INTERRUPT cycle (S3) and the first burst of
eight DMA cycles. This timing is accomplished by executing
an early 3-cycle instruction to compensate for the
INTERRUPT cycle. Furthermore, exactly three 2-cycle
instructions must be executed between eachsucesslve
burst. Occasionally these restrictions may be ignored atthe
expense of jitter on the screen.
For the 128 x 64 display, the CDP1800-series microprocessor
software requirement is straightforward. The DISP
STATUS/EF1 line is not required, and
may be used for
other purposes. A simple Interrupt routine merely resets the
DMA pointer, RO, to the beginning of the display buffer area
(see Fig. 8) - note the 3-cycle NOP Instruction' at the
beginning which compensates for the 1-cycle interrupt.
The first burst of eight DMA cycles occurs just as this
routine finishes, as indicated by the bracket following the
RETURN instruction (70). Exactly 29 cycles separate the
interrupt request cycle and the first DMA burst. The
Interrupt routine must last at least 28 cycles, because the
interrupt request line is held up that long by the CDP1861 C.
m
When less RAM is to be used (less resolution), a more
complicated interrupt routine is used. The interrupt routine
Is protracted for the full duration of the display window, and
the six free cycles in each line are used to execute three
instructions, which maintain control over the DMA pointer,
RO.1. In the simplest cases, each line of 8 bytes is repeated
n times to give 128/n vertical resolution. With n = 4, for
example, 64 x 32 resolution Is obtained. Such an Interrupt
routine is shown in Fig. 7. The use of three instructions per
1800-Serles Peripherals
CDP1861C
APPLICATION INFORMATION (CDP1881C DIRECTLY CONTROLLED BY THE CDP1800-SERIES MICROPROCESSOR)
(Conl'd)
line does not leave time to control a loop, so each of four
copies of the line corresponds to three Instructions.l!!Jhe
main loop, starting at EFX. The
signal, applied to EF1, Is
used to signal the last pass through the loop.
or even resol utlons which vary through the display window.
m
In general, additional functions may be implemented In the
routine before returning to the main program. For example,
a real-time clock can be maintained by incrementing a
counter once on each interrupt, i.e., once per 1/60 second.
Another example is vertical "scrolling" of the display,
wherein the starting address in a display file is incremented
or reincremented at regular intervals.
For other values of n, similar routines can be devised. For n
= 2, the 64 x 64 format, the last 4 lines need special treatment
(see Fig. 6). Other schemes are possible, resulting In other
resolutions which vary on command from the main pr9gram,
I
DISPLAY AREA
~-
~
~
I
~
IJ1..TPB
:
:
TPA
~""------------~LH SYNC
--..::.-.:.-.:.-==.:.-::.-::.-.:..=='''T.---...
____.J---------,L- a
SCI
om;
TPB BYTES
9zeM-29481ftl
Fig. 4 - Spatial diagram of one video display field (not to scale),
NTIC
1.78084
Line Freq.
Field Freq.
15750
60
15720
60
CLOCK FREQUENCIES (MHz)
3.579545/2
1.784000
15750
60.11
15980
60.99
263
RCA CMOS LSI Products
CDP1861C
liDO
R
RAM
ROM
92CM-29470RI
Fig. 5 - Typical CDP1802/CDP1861C video display system.
Asaembly
Language
Machine Code
72
70
C4
INTRET
INT
22
78
22
52
F8-SO
F8-AO
C4,C4
E2
SO]
DISP
E2
20
AO]
SEx2
E2
30-
SO]
E2
20 AO]
E2
3430-
: LDXA
RET
: NOP
DEC R2
SAV
DEC R2
STR R2
A.1 (DISMEM)-RO.1
A.O (DISMEM)-RO.O
NOP; NOP
SEX2
: GLO RO
SEX2
DEC RO
PLO RO
DISEF
BN1 DISP
: GLO RO
SEX2
DEC RO; PLO RO
SEX2
B1 DISEF
BR INTRET
Comments
·
·
·
·
·
.
.
.
.
.
RESTORE D
RETURN
3 CYC. INSTR. FOR PGM. SYNC
R2 IS STACK PTR
T-STACK
·
·
·
·
.
.
.
.
D-STACK
DISMEM IS START ADDR
OF DISPLAY MEMORY
NOPS FOR PGM SYNC
· .
..
· .
· .
..
· .
· .
..
NEW LINE
NOP
RESTORES RO.1 IF PASS PG
REPEATS SAME LINE
NOP
LOOP 60 TIMES
LAST 4 VIDEO LINES
NOP
.. NOP
· . END OF DISPLAY
Fig. 6 - Interrupt routine for 64 x 64 format (2 pgs mem).
264
1800-Series Peripherals
CDP1861C
Machine Code
72
INTRET
70
C4
INT
22
78
22
52
F8-BO
F8-AO
C4,C4
E2
SO]
E2
DISP
20
AO]
E2
20
AO]
E2
20
AO]
3G30-
: lDXA
RET
: NOP
DEC R2
SAV
DEC R2
STR R2
A1 (DISMEM)-RO.1
AO (DISMEM)-RO.O
NOP; NOP
: SEX2
GlO RO
SEX2
DEC RO
PlO RO
SEX2
DEC RO
PlO RO
SEX2
DEC RO
PlO RO
BN1 DISP
BR INTRET
·
·
·
·
·
·
.
.
.
.
.
.
RESTORE D
RETURN
3 CYC. INSTRU. USED
FOR PGM. SYNC
R2 IS STACK PTR
T-STACK
·
·
·
·
.
.
.
.
D-STACK
lOAD RO WITH
START ADDR. OF DISP. MEM
NOPS USED FOR SYNC
· .
..
· .
· .
..
· .
· .
· .
· .
· .
· .
· .
LINE START ADDR.-D
NOP
RESET RO.1 IF PASS PG
LINE START AOOR.-RO.O
NOP
RESET RO.1 IF PASS PG
LINE START ADDR.-RO.O
NOP
RESET RO.1 IF PASS PG
REPEATS SAME LINE
lOOPS 32 TIMES
END OF DIPLAY
I
Fig. 7 -Interrupt routine for 64 x 32 format (1 pg mem).
Assembly
Machine Code
72
INTRET
70]
C4
INT
22
78
22
52
E2,E2
F8-BO
F8-AO
30-
Language
Comments
: lDXA
RET
: NOP
DEC R2
SAV
DEC R2
STR R2
SEX R2; SEX R2
A1 (DISMEM)-RO.1
AO (DISMEM)-RO.O
BR INTRET
·
·
·
·
·
.
.
.
.
.
· .
..
· .
· .
· .
RESTORE D
RETURN
ENTRY POINT
R2 = STACK PTR
T-STACK
D-STACK
NOP
lOAD RO WITH
START ADDR OF DISP. MEM.
BRANCH TO INTERRUPT RETURN
Fig. 8 -Interrupt routine for 64 x 128 (4 pgs mem).
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
2.
not cause VDD - VSS to exceed the absolute maxi mum
rating.
Input Signall
.
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than
Vss.lnputcurrents must not exceed 10 mAevenwhen
the power supply is off.
Operating
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
VOD or VSS, whichever is appropriate.
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients. power supply
ripple. or ground noise; any of these conditions must
Unused Inputs
Output Short Clrculta
Shorting of outputs to VDD or VSS may damage CMOS
devices by exceeding the maximum device dissipation.
265
RCA CMOS LSI Products
CDP1862C
.Preliminary Data
r---------------~
RO
RESET
mR
B CHR
B LUI!
BKG
I
2
3
4
24
"23
22
21
20
19
5
6
~
7
TPB 8
CLK OUT 9
~ 10
LUI! IN
18
17
16
15
14
"
Vss 12
VOO
R LUI!
G LUI!
CMOS Color Generator
Controller
GO
BKG LUI!
G CHR
R CHR
8KG CHR
BO
BURST
xm
13 XTAL
TOP VIEW
Features:
• Interfaces directly with CDP1861C Video Display
Controller
• Programmable background color
• Programmable video (dot) color
". On-chip crystal controlled oscillator
• NTSC and RGB compatible
92CS-3166SRI
TERMINAL ASSIGNMENT
The RCA-CDP1862C is a color generator
controller designed for use in CDP1800series microprocessor systems. It is intended for use with the RCA-CDP1861C
video display controller and will interlace
directly with the CDP1802/CDP1861C as
shown in the system diagram below.
The CDP1862C utilizes many features of
the CDP1802 and CDP1861C to simplify
control and minimize the need for external
components. The CDP1862C is NTSC
color compatible. Red, green and blue
luminance signals are also available for
directly controlling the red, green and
blue amplifiers of a video monitor. A
7.15909-MHz on-chip crystal-controlled
oscillator or an external 7.15909-MHz
clock is used to generate multiple phases
of the 3.579545-MHz color burst frequency for NTSC-compatible color. The
color burst is further divided by 2 to provide system timing for the CDP1802 and
the CDP1861C. This frequency [1.789773
MHz] is available at ClK OUT. Two inputs
TPB and eoMP SYNC, are used to maintain system synchronization. The RES'E'f
input resets the CDP1862C and sets the
background color to blue and the dot
color to white.
RI360
seD
D
"
TPB
TPA
18
4
~;
20
·~K
ROM
mlift
COMP
RESISTANCE VALUES ARE IN OHMS:
SYNC
RD
CAPACITANCE VALUES ARE IN pF.
92CM- 31666RI
266
RII
~
Fig. 1- Typical CDP1802 microprocessor system using the CDP1862C.
i!o
I
!~
1800-Serles Peripherals
CDP1862C
Background color: Four background colors
are available. The colors are changed each
time TPB is pulsed when BKG = high. The
sequence is from blue to black to green to
red and return to blue [see Fig. 2].
rBB:8:Eh
92CS-31661
Fig. 2-Background C%r Sequencing.
Dot color: Color data [RO, BO, GO] is
latched internally on the high-to-Iow
transition of CO< when TPB = high. Eight
colors are available as shown in Table I.The
color is overlayed onto the LUM IN data
[video output from COP1861 C]. Each color
TABLE 1- Color Table
RD
BD
GO
COLOR
0
0
0
0
1
1
1
1
.0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Black
Green
Blue
Cyan
Red
Yellow
Purple
White
corresponds to eight horizontal bits of
video information. Only the selected
background color appears at the output if
LUM IN = low. When used with the
COP1861 C and set for the maximum
resolution of 64 x 128, 1024 color blocks [ 8
x 128] are possible, and would require a 1 K
x 3 random-access memory storage area.
This area would appear to be write-only
memory to the microprocessor because, in
the programmed state, this area occupies
an unique, unused 1 K block of memory
space. However, when it is read, this area
responds to the same address space
occupied by the COP1861'(~ refresh RAM.
This is accomplished with proper decoding
and requires the memory to have separate
I/O lines.
The CON input enables the RD, BO and GO
input latches. After a RESET condition, the
dot color is set to white and any color
change is inhibited until the CON input is
pulsed low, which normally occurs when
data is written into the color map. TheCC5N
input provides a means of inhibiting
erroneous color data until the color map is
.
properly loaded.
The color luminance [R LUM, BLUM, G
lUM], color chrominance [R CHR, B CHR,
G, CHR], background luminance [BKG
lUM], background chrominance [BKG
~HR), color burst [BURST], and ~
YNC are combined by an external RC
network to generate the composite video
[see Fig. 1].
The BURST signal is normally high and
oscillates at 'h the XT Al freguency from the
low-to-high transition of COMP SYNC until
TPB = high.
The COP1862C types are supplied in 24lead hermetic dual-in-line side-brazed
ceramic packages [0 suffix], and in 24-lead
dual-in-line plastic packages [E suffix].
I
RECOMMENDED OPERATING CONDITIONS at TA = 250 C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that operation is
always within the following ranges:
CHARACTERISTIC
VDD
(V)
LIMITS
Min.
Max.
Supply-Voltage Range (For T A = Full PackageTemperature Range)
-
4
6.5
Input Voltage Range
-
VSS
VOO
Input Signal Rise or Fall Time, t r , tf
5
-
5
Clock Input Frequency, fCl
5
UNITS
V
7.15009
Ils
MHz
267
RCA CMOS LSI Products
CDP1862C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDO)
-0.5 to +7 V
(Voltages referenced to VSS Terminal)
-0.5 to VDD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS. .
±10mA
DC INPUT CURRENT. ANY ONE INPUT . .
POWER DISSIPATION PER PACKAGE (PO):
..•..••. ,
500mW
For T A = -40 to +60o C (PACKAGE TYPE E)
Derate Linearly at 12 mW/oC to 200 mW
For T A = +60 to +850 C (PACKAGE TYPE E)
.
o
.
.
.
•
.
.
.
•
,
500mW
For T A = -55 to +100 C (PACKAGE TYPE D) •
Derate Linearly at 12 mW/oC to 200 mW
For TA = +100 to +125 0 C (PACKAGE TYPE D) •
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE (T A):
-55 to +125 0 C
PACKAGE TYPE D . : • . . . • • .
-40 to +85 0 C
PACKAGE TYPE E . . . • . . • • . • . . • . .
-65 to + 150°C
STORAGE TEMPERATURE RANGE (Tstg ) . • . . . . . .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ±0.79 mm) from case for 10 s max.
STATic ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C, except as noted.
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current. 'L
Output Low Drive (Sink)
Current. '0 L
LIMITS
CDP1862CD
CDP1862CE
Vo
(V)
VIN
(V)
VDD
(V)
Min.
-
0.5
5
-
0.4
O. 5
5
0.4
0.5
4.6
Typ.*
UNITS
Max.
50
250
J1A
2
2.4
-
rnA
5
150
200
-
J1A
O. 5
5
-1.6
-1.8
-
rnA
-150
-200
-
J1A
(Except XTAL)
XTAL Output. IOL
Output High Drive (Source)
Current. IOH
(Except XT A L
4.6
0, 5
5
Output Voltage
Low-Level. VOL
-
0,5
5
-
0
0.1
Output Voltage
High Level. VOH
-
O.
5
4.9
5
-
XT AL Output. IOH
5
Input Low Voltage. VIL
0.5,4.5
-
5
Input High Voltage. V,H
0.5,4.5
-
5
Input Leakage
Current, liN
Any
Input
O.
5
* Typical values are for TA = 25°C and nominal voltage.
268
V
..
5
3.5
-
-
1.5
-
-
±0.1
±1
J1A
1800-Series Peripherals
CDP1862C
RO
BO
GO
16
21
LATCH
r-----+-...,..-......-{8
TPB
LUM IN I \ } - - - t
OSCILLATOR AND COLOR
LOGIC
XTAL 11I1}---t
XT.AL ~~--~.--,r--r--r-.--,---r--r-,J
5
"..J
"
"'" '"'"
CD
III
92CM-31664RI
Fig. 3-Functional block diagram.
SIGNAL DESCRIPTIONS
FiEsEi'
A low level on this input initializes the
internal counters. sets the background
color to blue. and sets the dot color to
white.
BKG
A high level on this input enables the
background color to be changed when
TPB is pulsed high. This signal is normally
connected to an I/O line of the 1800Series microprocessor.
eLK
An input signal used to latch the color data
information. Color data [RD. BD. GO] is
latched on the high-to-Iow transition of
ClK when TPB " high. This signal is
normally connected to ClK OUT through
an inverter.
TPB
A high level on this input enables color
data latching and sequences background
color when BKG = high. This signal is normally connected to the TPB terminal of
the 1800-Series microprocessor.
ClK OUT
An output signal. equal to the XTAl frequency divided by four. that provides the
overall system synchronization. This signal is normally connected to the CLOCK
terminal of the 1800-Series microprocessor.
I
The inverse of this signal is normally
connected to the CLOCK terminal of the
CDP1861 C and the ClK terminal of the
CDP1862C.
COMP SYNC
An input signal used to provide horizontal
line
synchronization
between
the
CDP1861C and the CDP1862C color
signals. This signal is normally connected
to the COMP SYNC terminal of the
CDP1861C.
lUM IN
The luminance video input. to which the
color information is added. One color block
corresponds to eight serial bits of data from
this input. This input is normally connected
to the VIDEO terminal of the CDP1861 C.
VSS
Negative supply voltage; ground.
XTAl,XTAl
Terminal connections for an external
crystal. in parallel with a resistance [10
megohms typ.] if the on-Chip oscillator is
utilized. Frequency trimming capacitors
may be required at terminals 13 and 14.
XTAL is the input for an externally
generated single-phase clock.
BURST
The color reference output. which oscillates at the XT Al frequency divided by 2.
269
RCA CMOS LSI Products
CDP1862C
This signal provides approximately 11
cycles of 3.579545 MHz from the low-tohigh transition of COMP SYNC until TPB =
high. This signal is coupled throu~g a
external series RC circuit to the
M
SY"N"C output of the CDP1861C.
RD, BD, GO
The red, blue, and green color data inputs.
One of eight colors is latched on the highto-low transition of ClK when TPB = high,
forming a color block of eight horizontal
lUM IN data bits. Only the selected
background color appears at the output if
lUM IN = low. These inputs are normally
connected to the DATA OUT terminals of
the color map memory.
BKG lUM, R lUM, BLUM, GLUM
These output signals provide background
and color luminance information. TheY are
resistively added externally to the OMP
SYNC output of the CDP1861C.
p
OPERATING AND HANDLING
CONSIDERATIONS
these co'nditions must not cause Voo-Vss
to exceed the absolute maximum rating ..
1. Handling
All inputs and outputs of RCA CMOS
devices have a network for electrostatic
protection during handling. Recommended handling practices for CMOS
devices are described in ICAN-6525,
"Guide to Better Handling and Operation of CMOS Integrated Circuits."
Input Signals
To prevent damage to the input protection circuit, input signals should never
be greater than Voo nor less than Vss.
Input currents must not exceed 10 mA
even when the power supply is off.
2. Operating
Operating Voltage
During operation near the maximum
supply voltage limit, care should be
taken to avoid or suppress power supply
turn-on and turn-off transients, power
supply ripple, or ground noise; any of
270
BKG CHR, R CHR, B CHR, G CHR
These output signals provide background
and color chrominance Information. They
are coupled through an external series RC
circuit to the COMP SYNC output of the
CDP1861C. Each signal is phase-shifted
from the BURST reference signal by the
amount necessary for proper color operation.
CON
The color data input latch enable signal.
After a RESET condition, the internal RD,
BD, and GO input latches are held in a reset
state, providing a white color output. When
CON is pulsed low, the reset state is
removed and the latches are enabled, providing color output. This~WRt is normally
connected to the gated
signal from
the l80D-Series Microprocessor.
VDD
Positive supply voltage.
Unused Inputs
A connection must be provided at every
input terminal. All unused input terminals must be connected to either Voo or
Vss , whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may
damage CMOS devices by exceeding
the maximum device dissipation.
1800-Series Peripherals
Preliminary Data
mn'
16
CLK 2
15
Voo
OE
14
OUT
13
0:[7
12
DI6
CLK I
STR
4
DIO
OIl
0I.2
Vss
7
II
OI5
10
Dr4
Dr3
e
9
CDP1863, CDP1863C
CMOS 8-Bit Programmable
Frequency Generator
Features:
• Directly interfaces with CDPl800-series
microprocessors
• 256 possible programmable frequencies
• Two clock input predividers (-0- 4 and -0- 8)
• Gated square-wave output
• Single 4 to 10.5 V supply
TOP VIEW
92CS-31696
TERMINAL ASSIGNMENT
The RCA-COP1863 and COP1863C CMOS integrated circuits are programmable frequency generators designed to
produce 256 possible frequencies from a single-frequency
input clock. They will interface directly with the COP1800series microprocessor as shown in the system diagram (see
Fig. 1).
The COP1863 and COP1863C consist of a programmable
up-counter and an 8-bit latch (see Fig. 2). An input clock is
predivided by a fixed internal counter chain in addition to
the programmable counter. The final stage of the device
divides the output of the up-counter by two to provide a
square-wave output. The input clock may be applied to
either of two inputs; CLK1 provides a divide-by-four predivide, and CLK2 a divide-by-eight. The unused input must be
tied to Voo to avoid interference with the true clock. After the
programmable up-counter has reached its maximum count,
the next predivided clock pulse will cause it to go to zero.
At this time, the output flip-flop toggles and the load flipflop is turned on. The output of the load flip-flop is fed into
the NOR gates which allow the divide rate stored in the 8-bit
latch to preset the up-counter. Before the next predivided
clock pulse clocks this up-counter, the load flip-flop is reset
and the NOR gates are turned off. The counter then re-
sumes its up-count. The data at the eight data input': is
latched into the device by the high-to-Iow transition of
CLK1, when STR(STROBE) is high, or by the high-to-Iow
transition of STR, when CLK1 is high.
When using CLK2, CLK1 must be tied to Von to permit the
STR input to generate the internal latch clock. The 8-bit
data in the latch determines the divide rate of the programmable up-counter in the device. This rate may range from
divide-by-one to divide-by-256.
A low level on the RESET input resets the up-counter,
predividers, and flip-flops, and forces an initial state into the
8-bit data latch. This initial state provides a fixed divide rate
for the device prior to running the system. A high level on
the RESET input enables the up-counter, predividers, and
flip-flops and allows programming a new divide rate into the
device.
The COP1863 and COP1863C are functionally identical.
They differ in that the COP1863 has an operating voltage
range of 4 to 10.5 volts and the COP1863C hasan operating
voltage range of 4 to 6.5 volts. Both are supplied in 16-lead
hermetic dual-in-line ceramic packages (0 suffix) and in
16-lead dual-in-line plastic packages (E suffix).
Vce
AODR BuS
ADOR_ BUS
TPA
TPA
CPU
ROM
MRD
CEO
RAM
Mlll5
MWR
8-BIT BIDIRECTIONAL DATA
Fig. 1 -
CDPIB02
BU~_
TypicalCDPl800-series microprocessor system using the CDP1863 and CDPI863C.
271
I
RCA CMOS LSI Products
CDP1863, CDP1863C
MAXIMUM RATINGS; Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD):
(Voltage referenced to V•• Terminal)
CDP1863 .........................................................•..............•....•••..•..••..••..•••••.••.•• -0.5 to + 11 V
CDP1863C ..........................................................................•.... ; .••...••.••..••......• -0.5 to + 7 V
INPUT VOLTAGE RANGE, ALL INPUTS ................................................. , ....................... -0.5 to VO D fO.5 V
DC INPUT CURRENT, ANY ONE INPUT ........................................•....... \ ................. , ............... ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 12 mwrc to 200 mW
For T. = -55 to + 100°C (PACKAGE TYPE D) .........................................................••.•...••....•...• 500 mW
"or T. = + 109 to + 125°C (PACKAGE TYPE D) .......................................... Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 ............•...................................................................•...•....••.•. -55 to + 125·C
PACKAGE TYPE E ...........................................................................................••.. -40 to +85·C
STORAGE TEMPERATURE RANGE (T... ) .......................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265·C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85 0 C, except as noted
CHARACTERISTIC
Vo
(V)
-
'Quiescent Device
Current,
Output Low Drive
IL
(Sink) Current,
Output High Drive
10L
(Source) Current,
Output Voltage
Low-Level,
Output Voltage
High-Level,
Input Low Voltage,
-
50
250
-
1.6
2.2
-
-
-1
-1.6
-
-
-
pA
-
-
0
0.05
-
-
4.95
-
5
5
-
50
250
1.6
250
2.2
500
0,5
0.4
4.5
0,10
0,5
10
5
3
-1
3.6
-1.6
IOH
9.5
-
10
5
10
-3
-
-3.6
VOL
0,10
0,5
0,10
0
0
0.05
0.05
0,5
0,10
5
10
5
10
4.95
9.95
-
5
10
-
1.5
3
-
3.5
7
-
3.5
0,5
5
10
5
0,10
0,5
10
5
0,10
10
VOH
V,H
Input Leakage
0.5,4.5
0.5,9.5
0.5,4.5
0.5,9.5
Any
liN
Input
t
-
1001*
-
-
"Typical values are for T. = 25° C
tMeasured with CLK1=2 MHz, total divide rate of 8, CL = 50 pF.
:j:Measured with CLK1=4 MHz, total divide rate of 8, CL = 50 pF.
272
UNITS
0.4
V,L
Current
-
MIN.
LIMITS
CDP1863C
CDP1863
TYP."
TYP."
MAX.
MIN.
MAX.
10
5
Input High Voltage,
Current,
Operating
CONDITIONS
V,N
, Voo
(V)
(V)
-
-
-
±0.1
±1
±0.1
0.67
±1
1
3.5
4.5
-
-
mA
mA
V
1.5
-
±0.1
±1
-
-
0.67
1
-
-
V
pA
mA
1800-Series Peripherals
CDP1863, CDP1863C
OPERATING CONDITIONS at TA = 25°C Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so that operation is always within
the following ranges
LIMITS
CDP1863
MAX.
MIN.
CHARACTERISTIC
Supply-Voltage Range (At T A = Full
Package-Temperature Range)
Recommended Input Voltage Range
Input Signal Rise and Fall Time, t r , tf
CDP1863C
MAX.
MIN.
UNITS
4
10.5
4
6.5
V
Vss
VDD
·5
Vss
VDD
5
/-IS
-
-
V
I
Fig. 2 - Block diagram for the CDP1863 and CDP1863C.
SIGNAL DESCRIPTIONS
CLK1,CLK2
Input clock which is divided-down by the device to provide
an output frequency. The divide rate of the device is composed of a fixed predivide, the programmable divider, and a
divide-by-two output flip-flop which provides a squarewave output. ClK1 is pre-divided by four and ClK2 is predivided by eight. The unused CLOCK input must be tied to
Vee to avoid interference with the true CLOCK signal. ClK1
may also be used to latch the eight data inputs.
OUT
Square-wave output which is the result of the divided-down
input CLOCK. The OUTPUT toggles after the programmable up-counter reaches its maximum value and goes to
zero. OUT is held low when OE is low.
OE
A high on this input allows OUT to toggle freely. A low on
OE holds OUT low.
273
RCA CMOS LSI Products
CDP1863, CDP1863C
SIGNAL DESCRIPTIONS (Cont'd.)
010-017
Data inputs for programming the divide rate of the device.
The divide rates programmed into the device are inversely
proportional to the output frequencies generated. For example, programming the device with 00,6 causes the programmable up-counter to divide by one, providing the maximum output frequency for any given input clock.
Programming an FF '6 results in the maximum divide rate
and the minimum output frequency. To determine the frequency generated by a given programmed divide rate,
divide the input clock frequency by the decimal equivalent
of the programmed divide rate plus one, times the fixed
predivide which is 8 for CLK1 or 16 or CLK2:
Input Clock Frequency/[(Programmed Divide Rate + 1)10
(Fixed Predivide)]
STR
Positive pulse used to latch data at the eight inputs into the
device. This pulse is gated with CLK1 to form the internal
latch clock. When CLK1 is the input clock, the STR input
must be positive during the high-to-Iow transition of CLK1.
When CLK2 is the input clock, CLK1 must be tied to Voo so
that the STR input produces the latch clock.
RESET
A low on the RESET input resets all the stages of the predividers and the programmable up-counter and sets an initial
divide rate into the latch. This is to provide a standard initial
divide rate at the moment the system begins running. A high
on ~ enables the counter to run freely and allows
programming a new divide rate. The initial state of the
up-counter isa divide-by-54 resulting in a total divide rate of
432, after 1024 clock pulses when using CLK1, and 864,
after 2048 clock pulses when using CLK2.
VDD
Positive supply voltage.
Vss
Negative supply voltage; ground.
APPLICATION
The programmable frequency generator is directly compatAs an example of programming the frequency generator,
ible with the CDP1802 CMOS microprocessor. In Fig. 1 a
assume a 64 instruction is selected as the output code used
to program the device. Let machine register E point to the
simple CDP1802 system using this device is shown. TPB
may be used as the input clock. At typical CDP1802 system
data to be latched. N2 is the only N bit pulsed by a 64
clock frequencies, using TPB as an input to CLK1 results in
instruction and may be fed directly to the STR input if TPB is
nearly every possible output of the device being in the audio
fed to CLK1. An EE instruction makes RE the X register.
range. The Q output of the CDP1802 may be used as the
Following this with a 64 instruction puts the data pOinted to
OUTPUT ENABLE (OE) of the device. The eight data inputs
by RE onto the data bus and raises the N2 bit. TPB, which is
are connected to the bidirectional data bus which allows the
within the duration of the N2 pulse, causes the internal latch
clock to terminate before the data bus loses validity. The
system memory to provide divide rate data to the device. A
single N bit or some decoded output of all the N bits may be
latch in the device continually passes the data inputs
used as the STR input to latch data into the device. This
through to the outputs of the latch as long as CLK1 and STR
involves designating some output instruction of the
are high. Once CLK1 goes low, data is locked in. A 7B
CDP1802 for providing the STR. The output instruction
instruction then sets the Q line high which, if connected to
places the data pointed to by the X register on the bus, while
OE, allows the OUT to toggle at the desired rate.
simultaneously pulsing the appropriate N bits. By the interCode:
nal gating of TPB and STR, when TPB is fed into CLK1, the
EE RE is the X register
resulting latch clock terminates while the data is still valid
64 M(E)-BUS N2 pulsed high
on the 8-bit bus. If TPB is fed into CLK2, it is necessary to
7B Q turned on
provide an external AND gate for the appropriate N bits and
TPB, to preserve this timing feature. The same signal thai
feeds the CLEAR input of the CDP1802 may be used as the
RESET signal to this device.
274
1800-Serles Peripherals
CDP1863, CDP1863C
Lll-.
CLOCK I
~
CLOCK 2
REffi'
STR
INTERNAL
LATCH CLK
~
~
223
L.fJ
LATCH
I
DATA
INPUTS
~~VALIO~
92CM- 31676
Fig. 3 - General CLOCK 1 timing diagram.
CLOCK
1=:3
I
STR
INTERNAL
LATCH CLK
DATA
INPUTS
LATCH
VALID
92CM-31677
Fig. 4 - General CLOCK 2 timing diagram.
CLOCK I (TPB)
?"'/I
r - - lt~___
_~~~____~____~I
I
I
STR (NZ)
INTERNAL
LATCH CLK
4
I
I
I
LATCH
I
DATA INPUTS
( BUS)
L
VAll D
v:;~
92CM- 31678
Fig. 5 - General CDP1800-series microprocessor system timing diagram.
275
RCA CMOS LSI Products
CD·P1863, CDP1863C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=-40 to +85°C, VDD ± 5%, Cl = 50 pF
LIMITS
CHARACTERISTIC
Clock 1 Frequency
tclK'
Clock 2 Frequency
tclK2
Clock 1 Width
t,
Clock 2 Width
b
Clock 1 to Clockout
tCl'
Clock 2 to Clockout
tCl2
Reset to Clockout
-teLR
OE Delay to Clockout
toED
ReSet Pulse Width
-tRS
Data Setup to Clock 1
tDS
Data Hold to Clock 1
tDH
Data Setup to Strobe
tDSS
Data Hold to Strobe
tDHS
VDD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10 .
5
10
5
10
5
10
5
10
CDP1883
TYP.*
MIN.
-
250
100
125
70
-
-
-
.
-
-
-
-
1
0.3
0.9
0.3
260
130
110
40
120
60
0
0
75
50
0
0
50
40
MAX.
2
5
4
8
MIN.
-
250
1.7
0.5
1.2
0.5
375
170
150
70
160
90
20
10
100
80
30
30
100
60
-
125
-
-
-
-
CDP1883C
TYP.*
MAX.
2
-
1
0.9
-
Clk 1
------;1
1.2.
110
150
-
-
120
160
-
-
0
20
-
-
75
100
-
-
0
30
-
-
50
100
-
-
DATA
CLk 2
OUT _ _ _ _ _ _ _ _-J'I~~_JI'-------------~-J''-~
OE
92CM-35035
276
1.7
-
~------~....J
I,
!-_ __
Timing diagram for the CDP1863 and CDP1863C.
-
-
STR _ _ _ _ _ _- '
Fig. 6 -
-
260
,----oaJOlI
I
4
-
375
·TYpical values are for TA = 25°C and nominal voltages.
r--'ClK
-
UNITS
MHz
MHz
n8
n8
p8
118
n8
n8
n8
n8
n8
ns
n8
1800-Serles Peripherals
Preliminary Data
""
INLACE
en
mn
.
"
"
""
'""
AO'
SCI
seo
i.iii5
BUS 7
auso
BUn
ID
BU54
,."
eus!
BUS>
BUS I
""$0
.,
CON
"
""
17
Ef
I.
NO
"'"
'ss
"
""
TOJ> VIEW
CDP1864C
CMOS PAL Compatible
Color TV Interface
'00
'"
CDmi
6iiAO
INT
TPA
TP.
m
Features:
v SYNC
HSYNC
• Single chip contains circuitry for video, sync, RGB
color, and programmable frequency for tone
generation
• Programmable 1-of-8 dot colors plus 1-of-4 background colors
• Bit-mapped display with maximum resolution of 192
vertical x 64 horizontal
•. Interlaced or non-interlaced displays
• Schmitt trigger clear input and output for power-on
reset of CDPt800 system
• t.75-MHz crystal operation
CM>"'"
BLUE
GREEN
fiG
BURST
ALl
It DATA
8 DATA
"
92CS- 31899RI
TERMINAL ASSIGNMENT
The RCA-CDP1864C is an LSI CMOS color or black and
white PAL-compatible video controller designed for use in
CDP1800 microprocessor systems. It interfaces directly
with the 1800-series microprocessor as shown in Figs. 1 and
2. The DMA feature of these processors is used for direct
data transfers of luminance information for display refresh.
The INTERRUPT input and a flag line (EF1, EF2, EF3, or
EF4) are used for handshaking.
The CDP1864C generates vertical sync, horizontal sync,
and composite sync. These Signals, combined with the
RED, BLUE, GREEN, BURST, and BKG signals, ct:ln be
used to generate a composite video Signal, or they can be
used directly inside a TV set.
In addition to generating a bit-mapped video display the
CDP1864C contains a programmable frequency generator
designed to produce 256 tones that range from 107 Hz to
13672 Hz.
The CDP1864C is supplied in the 40-lead dual-in-line
ceramic (D suffix) and plastic (E suffix) packages.
voo
1.75 MHz
CEO
CLOCK, NO, N2, Q
COPI~22
RAM
CDPI833
ROM
TPB, SCO, SCI
CPU
CDPIB02
Fig. 1 -
TO COLOR
PHASE
CIRCUIT
}
OR
TO RGB
INPUTS
Typical color system.
277
RCA CMOS LSI Products
CDP1864C
MAXIMUM RATINGS, Absolute-Maximum. Values:
DC SUPPLY-VOLTAGE RANGE. (Voo)
(Voltage reference to Vss Terminal)
CDP1864C ......................................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................ , .................................................................± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................. 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 12 mW/oC to 200 mW
For T. = -55 to +100°C (PACKAGE TYPE D) " ........................................................................... 500 mW
For T. = +100 to +125°C (PACKAGE TYPE D) ........................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................. 100 mW
OPERATING-TEMPERATURE RANGE (T.):
.
PACKAGE TYPES. D. H .......................................................................................... -55 to+125°C
PACKAGE TYPE E ................................................................................................ -40 to+85°C
STORAGE TEMPERATURE RANGE (T".) .............................................................................£5 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
OPERATING CONDITIONS at T A = Full Package Temperature Range
For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
TYPICAL
VALUES
4. to 6.5
Vss to Voo
5
1.75
Voo
(V)
CHARACTERISTIC
-
DC Operating-Voltage Range
Input Voltage Range'
Maximum Input Pulse Rise or Fall Time, t"t,
Maximum Input Clock Frequency, fCl
5
5
STATIC ELECTRICAL CHARACTERISTICS at TA
LIMITS
CDP1864C
TEST CONDITIONS
Quiescent Device Current,
100
Output Voltage:"
Low-Level,
VOL
High-Level,
VOH
Input Low Voltage,
Vil
Input High Voltage,
VIH
Output Low (Sink) Current,
10l
Output High (Source) Current, 10H
Input Leakage (';urrent,
Ill,IIH
3-State Output Leakage
Current,
lOUT
"10 ~1 pA.
278
-
VIN
(V)
0,5
-
O,S
0,5
4.9
Any Input
-
0.5,4.5
0.5,4.5
0.4
4.5
0.5
V
V
ps
MHz
= 2SoC, Voo = 5 V ±5%
CHARACTERISTIC
Vo
(V)
UNITS
0,5
O,S
Any Input
0,5
Min.
3.5
2
-1.6
-
UNITS
Typ.
100
Max.
500
°
0.1
5
-
-
1.S
-
pA
V
-
2.4
-
-1.8
-
±0.1
±1
±0.2
±2
rnA
pA
1800-Serles Peripherals
CDP1864C
CDPI822
RAM
92CM- 3I900RI
Fig. 2 -
BUS7
Typical black and white system.
TPB
BUSS
BUS 5
BUS4
BUS 3
BUS2
BUS I
BUSO
PARALLEL LOAD/SERIAL OUT SHIFT REGISTER
PIS
CLK
G DATA
R DATA
TIMING
GENERATOR
~
1---.(3d CQMP SYNC
3~------~------~--~
HSYNC
V SYNC
NO
N2
MRo
TPB
TPA
SCO
SCI
INT OMAO VSS VOO
92CL-3190,RI
Fig. 3 -
CDP1864C block diagram.
279
RCA CMOS LSI Products
CDP1864C
*
'"
"z
z .. <1
~ ffi I....
> >
~
HORIZONTAL
LINE No·
<11
~
D
VERTICAL BLANKING
-
12
-
24
-
36
- 4B
-
72
-
84
I,:
-
~----------64------4---1/
'";'z
~
..J
132
144
-
168
180
192
o
N
iii
o
204
:I:
.
:I:
~~
96
-
;;;- 156
z
192
60
-
-
216
-
240
228
252
264
....
276
288
-
300
312
-,=1=sl,,-JILs_o-'.l_s_1-1-1_s2-,-1_s2-,-1s_2-'.I_s_2...I.1_s_2.LI_s2-,-1s_2-1I_s_2-L1_sO--,--I_s1-,-1s_o-::!I ~~~ TE
-1lIl
_________________________________________ HSYNC
~r-
---:--.
rr
I
•
I
I
SCO, SCI
SAMPLED BY TPA
*HBLANK AND VBLANK ARE INTERNAL SIGNALS
A iNT AND IT CHANGE ON LEADING EDGE OF H SYNC
Fig. 4 -
TPB
Display area diagram.
FUNCTIONAL DESCRIPTION OF
CDP1864C TERMINALS
INlACE - INTERLACE (Input):
A high level at this input results in the generation of a 625
line-per-frame interlaced display, and a low-level input results in the generation of a 312 line-per-frame noninterlaced display.
ClK - CLOCK INPUT (Input):
A 1.75 MHz clock input to the XTAL terminal of the 1800series microprocessor.
CLEAR - CLEAR OUT (Output):
This is a post-Schmitt trigger output of the signal on CLR
IN. It is connected to the CLEAR-N input of the CDP1800series microprocessor to provide it with a clean, clear
signal.
280
H BLANK* 92CM-31904
I
AOE - AUDIO OUTPUT ENABLE (Input):
A high level at this input allows the selected frequency to be
generated at the AUDIO-OUT terminal A low-level input
holds AUDIO OUT low. AOE may be connected to Q output
of the 1800-series microprocessor.
sca, SC1 - STATE CODES a AND 1 (Inputs):
These inputs are used to synchronize the CDP1864 to the
microprocessor machine states and are connected to the
SC1 and SCO outputs of the 1800-series microprocessor.
MRD - (Input):
This input selects the command issued to the CDP1864
conjunction with N2 and NO). It is connected to the MR
output of the 1800-series microprocessor.
(iD
1800-Serles Peripherals
CDP1864C
BUS 0 - BUS 7 (Inputs):
These inputs load the luminance information during the
display interval, and the frequency generator divide byte
when selected. They are connected to the DATA BUS.
CON - COLOR ON (Inpul):
A low level at this input enables the CDP1864 to begin
loading color information from the RDATA, GDATA, and
BDATA inputs. CON is connected to the gated MWR signal
of the color memory.
N2 (Input):
This input i~ used in conjunction with MAD and TPB to load
data into the tone generator latch (MRDeN2 eTPB) and disable the generation of INTERRUPT and DMA requests by
the CDP1864 (MRDeN2 eTPB). For example, a 64 instruction would result in data being loaded into the tone-divider
latch, while a 6C instruction would disable the INTERRUPT
and DMA requests. N2 is connected to the N2 output of the
1800-series microprocessor.
EF - EXTERNAL.FLAG OUT (Outpul):
I!:lliI old!J2Yt is connected to a 1800-series microprocessor
EF1 - EF4 inputs. It maintains software synchronization
with the display. Two pulses per field are generated on this
line, each of which is four horizontal lines wide. The first
pulse begins four horizontal lines before the display, and
the second pulse begins four horizontal lines prior to the
end of the display. The second pulse is used to indicate to
the microprocessor that the display is ending.
NO (Input):
This input is used in conjunction with MRD and TPB to step
the background color (MRDeNOeTPB) and to enable the
INTERRUPT and DMA requests (NOeTPB). For example, a
61 instruction would step the background color, and a 61 or
69 instruction would enable the INTERRUPT and DMA requests. NO is connected to the NO output of the 1800-series
microprocessor.
GREEN, BLUE, RED (Outputs):
These CMOS logic level outputs are used either directly in
the TV to generate the selected colors, or indirectly to
generate a composite video signal. These outputs are used
to indicate the selected color for an "on" spot or the background color for an "off" spot.
COMP SYNC - COMPOSITE SYNC (Output):
This output is the composite horizontal and serrated vertical sync signal.
Vss:
Negative supply voltage.
GDATA, BDATA, RDATA - RED, GREEN,
and BLUE DATA (Inputs):
These inputs carry color information from the color RAM.
The data on these lines are latched concurrent with the
latching of the luminance information from the data bus
during the display interval if the CON input has gone low
since reset.
AL T - ALTERNATE (Output):
This output toggles at each horizontal sync time and is used
to perform the phase alternation.
BURST (Output):
This output applies a 4.57 us pulse to each horizontal sync
back-porch (except for 24 lines during vertical sync when it
is blanked) which gates in the color burst signal.
BKG - BACKGROUND (Output):
This CMOS logic level output indicates that the color selected by the RGB outputs is due to background color
select rather than a one bit in a display luminance byte. BKG
may be used to lower the luminance of the background
color so that the same color may be used for display of data.
This output is blanked (held high) during horizontal and
vertical blanking.
DMAO -
HSYNC - HORIZONTAL SYNC (Output):
This output is a separate horizontal sync signal.
EVS - EXTERNAL VERTICAL SYNC (Input):
A high level at this input sets the line counters to the vertical
sync state.
TPB - TIMING PULSE B (Input):
This input is connected to the TPB output ofthe 1800-series
microprocessor. It is used forstrobing the MRD and N lines,
for horizontal line timing, and as the input to the tone
generator.
TPA - TIMING PULSE A (Input):
This input is connected to the TPA output of the 1800-series
microprocessor. It is used for horizontal line timing.
iNi' - INTERRUPT (Outpul):
This output is connected to the INT input of the 1800-series
microprocessor. One interrupt request is issued per field.
The request is issued two horizontal lines before the display
interval, and the signal remains active for two horizontal
lines.
DMA OUT REQUEST (Out'bUI):
This output is connected to the DMAO f input of the 1800series microprocessor. During the display interval the
CDP1864 issues this request for 6 machine cycles during
the center of each horizontal line (each line time is 14
machine cycles).
REm -
RESET IN
A low level at this input resets the CDP1864 and generates a
low on the CLROUT output. The requests and the loading of
color information are inhibited by reset. These remain inhibited until enabled by the appropriate signals. The line
counters and horizontal counters are also held reset while
RESET is low. The Schmitt trigger circuit at this input allows
the use of an RC circuit for power-on reset and reset
debounce.
AUD - AUDIO OUT:
This is the output of the programmable frequency
generator.
Voo:
Positive supply voltage.
281
RCA CMOS LSI Products
CDP1864C
CIRCUIT OPERATION
The CDP1864C consists of four major sections: a timing
generator that produces the necessary signals for video
interface, a parallel-in/serial out shift register for dot generation, a tone generator for one of 256 frequencies, and
control logic for software control of the first three sections
(see Fig. 3). In a typical CDP1800 system, control of the
CDP1864C is accomplished with I/O commands as shown
in Fig. 5.
The CDP1864C display is a bit-mapped, color or black and
white display with a maximum resolution of 192 lines vertically and 64 dots (eight 8-bit bytes) horizontally. This resolution, which requires 1.5 Kbytes of refresh RAM, is seldom
used because of the poor aspect ratio of the resultant picture element. An approximately square picture element is
obtained by repeating each horizontal line 6 times (this is
do~e in software by the CPU) for a-32-row by 64-dot display.
This lower resolution display requires 256 bytes of refresh
RAM.
The CDP1864C generates both composite and separate
horiz~1 and vertical sync, RED, BLUE, GREEN, BURST,
and BKG signals. These signals may be used directly (inside the TV), or they may be used to generate the composite
video signal. The sync signals generate either a 625 lineper-frame interlaced display or a 312 line-per-frame noninterlaced display. This is selectable by connecting the
INTERLACE input to either Vee or GND.
The video refresh is accomplished via the DMA channel of
~ '!!l9roprocessor, and s~chronization is provided by
INT, EF, SCO, and SC1. The EF signal goes low 4 horizontal
lines prior to the start of display and again 41ines priorto the
end of the display. This signal alone can be used by the CPU
to initialize R(O) for DMA refresh. Alternatively, the INT,
which goes low 2 lines prior to the start of the display, may
be used.!£.enter an interrupt routine that initializes R(O),
and the EF signal can be used to indicate the end of the
display. The combination of TNT and EF allows for an interrupt routine to oversee DMA refresh and repeat horizontal
lines for configurations with less than the maximum 192line re.solution. EF can be sampled to detect the end of the
display and cause a return to the main program from the
interrupt routine.
SC1 and SCO are used to provide CDP1864C-to-CPU synchronization for a jitter-free display. During every horizontal sync the CDP1864C samples SCO and SC1 for SCO == 1
and SC1 == 0 (CDP1800 execute state). Detection of a fetch
cycle causes the CDP1864C to skip cycles to attain synchronization. Once in lock the system will remain locked if:
(1) no 3-cycle instructions (e.g. NOP) are executed during
CONTROL LINE TRUTH TABLe
MRD
N2
NO
X
0
0
X
0
1
0
0
1
0
1
0
1
1
0
X
1
1
X
X
X
.
TPb
X
1
1
1
1
X
0
The OP COQE column IS given assummg that N1 - O. It
·connected to the-CDP1864C.
282
the display (three 2-cycle instructions are executed each
horizontal line); (2) an even number of cycles is performed
between frames (easiest to do by avoiding 3-cycle instructions); or (3) exactly 29 cycles, beginning with a fetch and
ending with an execute, are completed between the S3
intern!E!!esponse of the cpu and the first DMA in systems
usirg INT. The 29 cycles of interrupt should consist of an
early 3-cycle instruction and thirteen 2-cycle instructions
(or equivalent). Fig. 5 is an example of an interrupt routine
for a 64 by 32 picture element display (each horizontal.line
is repeated 6 times).
Reset disables the color, control, INT, and DMA requests. A
61 or 69 instruction enables the requests, and a 6C instruction disables them (see Fig. 5). Color is enabled by CON,
which is normally connected to the gated MWR signal of the
color RAM.
The background color is program-selected to be either
blue, black, green or red. The initial default is blue. The
color selected is changed by a 61 instruction (see Fig. 5).
This condition causes the color to step to the next color in
the order shown above. From red it steps to bl ue. The BKG
output may be used to lower the luminance of the color
when it is background. This would, for instance, enable a
blue spot to be used on a blue background and still be
visible. The BKG signal and RGB outputs are internally
blanked during the horizontal and vertical retrace.
The CDP1864C also contains a programmable tone generator designed to produce 256 frequencies. The frequency
input to this generator is the TPB input (TPB frequency ==
1.75 MHz -7- 8 == 218.75 kHz). This frequency is further
reduced by a divide-by-4 predivider, an 8-bit programmable
up-counter, and a divide-by-2 output stage. The programmable up-counter is reloaded automatically from the 8-bit
tone generator latch each time it reaches the terminal
count. The tone generator latch is loaded by the CPU from
the data bus during a64 output instruction (see Fig. 5).
An AUDIO OUTPUT ENABLE (AOE) terminal is also provided. When this terminal is high the output of the generator
(AUDIO OUT) is allowed to toggle freely. When this terminal is low the output is held low. AUDIO OUT may be
connected to the Q line of the 1800-series microprocessor.
A low on the reset sets the 8-bit latch to a default state of 35
hex and resets the programmable counter. When reset is
released a frequency output of 506 Hz will be generated
until a new value is loaded into the latch. The frequencies
generated from the input to the 8-bit tone generator latch
can be computed by:
27343.75
f ==
_
Hz.
(Hex Code + 1) 10
OP CODE'
61 or 69
61
64
6C
IS
OPERATION
NO ACTION
ENABLE REQUESTS
STEP BACKGROUND COLOR
LOAD TONE GENERATOR LATCH
DISABLE REQUESTS
ILLEGAL COMMAND
NO ACTION
actually a DON T CARE because N1 from the microprocessor
IS
not
1800-Series Peripherals
CDP1864C
Machine Code
72
70
C4
Assembly Language
INTRET: LDXA
RET
INT
:NOP
Comments
.. RESTORE D
.. RETURN
· .3 CYC. INSTR. USED
· . FOR PGM. SYNC
· . R21S STACK PTR
.. T - STACK
"
22
78
22
52
F8-BO
F8-AO
C4, C4
E2
80]
E2
20
AO]
E2
20
AO]
E2
20
AO]
E2
20
AO]
E2
20
AO
3C
30
DISP
DEC R2
SAY
DECR2
STR R2
A.1 (DISMEM) - RO.1
A.O (DISMEM) - RO.O
NOP; NOP
: SEX2
GLO RO
SEX2
DEC RO
PLO RO
SEX2
DEC RO
PLO RO
SEX2
DEC RO
PLO RO
SEX2
DEC RO
PLO RO
SEX2
DEC RO
PLO RO
BN1 DISP
BR INTRET
.. D - STACK
· . LOAD RO WITH
· . START.ADDR.OF DISP. MEM
· . NOPS USED FOR SYNC
· . LINE START ADDR. - D
.. NOP
· . RESET RO.1 IF PASS PG
· . LINE START AD DR. - RO.O
.. NOP
.. RESET RO.1 IF PASS PG
· . LINE START ADDR. - RO.O
.. NOP
· . RESET RO.1 IF PASS PG
· . LINE START AD DR. - RO.O
" NOP
· . RESET RO.1 IF PASS PG
.. LINE START ADDR. - RO.O
" NOP
· . RESET RO.1 IF PASS PG
· . REPEATS SAME LINE
· . LOOPS 32 TIMES
· . END OF DISPLAY
Fig. 5 - Interrupt routine for
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525 "Guide to Better Handling
and Operation of CMOS integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must not
cause Voo-Vss to exceed the absolute maximum rating.
a 64 x 32 display.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than VDO nor less than
Vss. Input currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Voo or Vss, whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may damage CMOS
devices by exceeding the maximum device dissipation.
283
RCA CMOS LSI Products
CDP1864C
HORIZONTAL
SYNC
l-----o~
____o.,.I..___~---
-------00--11
c j.---d
9-------I
I
J
.---.
I
I
\
CSo. Csi. ill. CS3
/
(0) CHIP ENABLE TO CHIP SELECT PROP. DELAY
MRD
+ MRW*
--------~/,
\----------
~
1
CSO.
lIMes
~
,
\
Csi. CS2. CS3
7
(b) MRD+MRW TO C:;;H;;:IP;;:;;S;;;EL::;E;C;T:P:':::RO:::P:-.D::-:E;-;-L-:A-::Y---------------J
MAO- MA3
==x~---~¥~----~::~------~~~--:
IMACL
~
CLOCK
CSo. Csi. CS2. CS3
:
tCLMA
f'"t"--
I
:
----I,I i,!-------------t!ll--------....,:
tCLCL-t:--' t CLCS
,IMACS
,
"'
~
:, L
' t MACS
*:
:-==-t
:
'C
-----+,---------''K.::
'-------! 1------------;,--'
,
I,. tCLA "I
: IMAA
' tMAA
~~
~
A8-AS
---"-----.x
: _r
- - - - ; - ( O....) ....M:':E"'M""OR:::Y7'A-:":O-d.ORESS SETUP
*
'
:
'C
~~Nc:O:-:·H':':O::-L-=-O-=T:':',M:':E-------J ' - - - 92CM-31868
SEE TRUTH TABLE FOR MRD a MRW
Fig. 8 - CDP1866 timing waveforms.
291
RCA CMOS LSI Products
CDP1866" CDP1866C, CDP1867, CDP1867C, CDP1868, CDP1868C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = --40 to +85°C, Vee
V'H = 0.7 Vee. V'L = 0.3 Veo, CL = 100 pF. See Fig. 9
LIMITS
Voo
(V)
CHARACTERISTIC
Minimum Setup Time,
Memory Address to CLOCK,
Minimum Hold Time,
Memory Address After CLOCK,
Minimum CLOCK Pulse Width
5
10
5
10
5
10
tMACL
tCLMA
tCLCL
Propagation Delay Times:
Chip Enable to
Chip Select,
MRD or MRWto
Chip Select,
CLOCK to Address,
5
10
5
10
5
10
5
10
tCECS
tMCS
teLA
Memory Address to
Address,
tMAA
± 5%, t r, tt = 20 ns,
CDP1867C
Typ.- Max.A
CDP1867
Min.
Typ.-
Max.A
Min.
-
50
25
50
25
50
25
75
40
75
40
75
40
-
50
-
-
-
50
75
-
-
-
100
50
80
40
125
65
75
40
150
75
125
60
200
100
125
60
-
100
150
-
-
-
-
75
-
-
50
75
-
-
80
125
-
-
125
200
-
-
-
-
75
125
-
-
-Typical values are for TA = 25°C and nominal Vee.
6Maximum limits of minimum characteristics are the values above which all devices function.
CE', CE2, - - - - - - , , . . - - - - - - - - - - - - - - - - - - - ,
CE3,CE4
~
r-------
~~----_ __
~ tCECSr-
I....-.t--tCECS
------~\
J~----
(0) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY TIME
MRD,MRW------\r----------------~(------
~
tMCS
I
I--
--jtMCSi--
\
'
)"---_
M"'O""RrvY'R~E;;:;AD;;-;;O:;RT.w;SR:;:;;IT;:;;E-;T:::O:-C;;;R;:,P;;:;;;SE;;L:;;E:;CT;-:PR::O:::P::AG::A::TI:::ON::-:DE:::L-:A::YTIM E
( b) iIM"'E
MAO-MA3
~
¥--~::~---~~------'
.-+,,----+---....,1
___'_~11
t
~------~l~l---~
L-I
I
...-tMACL-J-tCLMA-j
CLOCK
- - : CLCLrI
: - - tCLA----'
AS-All
=====~=~~=*~
,
:
____ ______
~:~:
(e) MEMORY ADDRESS SETUP AND HOLD TIME
Fig. 9 - CDP1867 timing waveforms.
292
I
- - : tMAA
I--
~~
I
I
l--tMAA--'
I
92CM-31867
UNITS
~
ns
1800-Series Peripherals
CDP1866, CDP1866C, CDP1867, CDP1867C, CDP1868, CDP1868C
DYNAMIC ELECTRICAL CHARACTERISTICS al T A = -40 10 +85 0 C, Voo
V,H = 0.7 Voo, V,l = 0.3 Voo, Cl = 100 pF. See Fig. 10
Minimum Selup Times:
Chip Enable 10
CLOCK,
Memory Address
10 CLOCK,
Minimum Hold Times:
Chip Enable After
CLOCK,
Memory Address Afler
CLOCK,
Minimum CLOCK Pulse Width,
IcecL
IMACl
IClce
ICLMA
tCLCL
Propagation Delay Times:
CLOCK 10
Chip Select,
Chip Enable 10
Chip Selecl,
Chip Enable 3 to
Chip Select,
MRD or MRW 10
Chip Select,
CLOCK to Address,
teLcs
leees
tC3CS
IMes
IClA
Memory Address to
Chip Select,
Memory Address 10
Address,
tMACS
IMAA
Ir, If
= 20
ns,
LIMITS
CDP1868
CDP1868C
Typ •• Max ..c.
Typ.• Max •.c.
Min.
Min.
Voo
(V)
CHARACTERISTIC
± 5%,
5
10
5
10
-
5
10
5
10
5
10
-
5
10
5
10
5
10
5
10
5
10
5
10
-
-
-
-
-
5
-
10
-
50
75
-
:>u
f:>
-
-
-
-
50
75
-
f:>
-
50
25
50
25
75
40
75
40
50
25
50
25
50
25
75
40
40
75
40
-
-
-
-
50
75
-
-
175
90
150
75
150
75
125
65
125
65
125
65
80
40
275
150
225
125
225
125
200
100
200
100
200
100
120
60
-
175
275
-
-
-
150
225
-
:>u
75
-
-
-
150
225
-
-
125
200
-
125
-
125
UNITS
ns
I
-
200
-
200
-
-
-
80
120
-
-
-
-
-Typical values are for TA = 25°C and nominal.
t.Maximum limits of minimum characteristics are the values above which all devices function.
1"'1 CEI,m TQCHIP SELf.CTPRO~ OHA'
}--,-.,..-,.----~------,
====:::::::::'j " j - - - - v~
0
-..,
'''''' ---L.-t,
·tescs
\
"",.'".~
esc-WI
...
L'M~
~=..;
---.L-.-t=
I
""-""=x====:x::::==:~
CLOCK
~:m
Ae-A9
~~~L~lClMA
: :
------r-l----~
--l-7C'5 ;:
~~l
~lMACS~~-±=
-
:--!~~
Fig. 10 - CDP1868 timing waveforms.
293
RCA CMOS LSI Products
CDPfs66, CDP1866C, CDP1867, CDP1867C, CDP1868, CDP1868C
92-100
.337-2.540)
92-100
(2.337-2.540)
92CM-33348
92CM-33347
Dimensions and pad layout for CDP1866CH.
Dimensions and pad layout for CDP1867CH.
92-100
(2.337-2.540)
92CM-33349
Dimensions and pad layout for CDP1868CH.
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10-' inch).
294
The photographs and dimensions of each CMOS chip represent a
chip when it is part of the wafer. When the wafer is cut into chips,
the cleavage angles are 57° instead of 90° with respect to the face
of the chip. Therefore, the isolated chip is actually 7 mifs (0. 17 mm)
larger in both dimensions.
1800-8erles Peripherals
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
".
""
'"
rn
'00
PNSEL
PiiiM
CMSEL*
(""WI!
COs/MOS
Video Interface System
M"119
"""1
MA2110
PPoIU
P"A~
"
.""""
*iiiiPLiY
hD::~!t
'"
..""
. """
to
PIIA6
PIII.7
PM ...
C.. "3/PI,lAIO
eMU
eMAI
C.. AO
Mil
Features:
•
•
•
*INTUICHIPCONN£CfIONS
CDP1889, CDP1889C
TERMINAL ASSIGNMENT.
•
•
CMOS technology (C2L)
DIrectly Interfaces wIth CDP1800
series microprocessors
DOT frequency = 5.67 MHz
(PAL = 5.626 MHz). Produces maxImum feasible resolution for RF
(antenna) input
CPU clock Independent ('12 DOT rate
provided)
CPU not Involved in screen refresh
The RCA-CDP1869 and CDP1870 video Interface system Is designed for use In
CDP1800-5erles Microprocessor systems.
It consists of the CDP1889C address and
sound generator and the CDP1870C color
video generator. These two LSI COs/MOS
circuits interface directly with the
CDP1802 or CDP1804 to simplify control
and minimize external components. (See
Fig. 1.)
The VIS offers a variety of formats for the
display and modification of data under
software control, with either NTSC or PAL
compatible output signals. The display
device can be a video monitor or a standard TV receiver with an RF modulator.
Composite sync, luminance, and
chromlnance are combined externally to
form a Single system~utput. (WIth the
RGB Bond-Out option (CDP1876), Red,
Green, and Blue outputs are provided to
drive the CRT color amplifiers directly.)
External sync inputs are also provided to
allow picture overlays In existing TV
chassis.
•
•
•
•
•
•
•
•
•
Produces extremely low chlp-count
systems for games and/or
"Intelligent" terminals
Graphics and motion through
character selection or bit map in
character memory
Up to 256 different characters
Character memory may be any combInation of ROM or RAM, allowing
modification of characters and
graphics
Programmable for 24 rows x 40
char/rowor 12 rows x 20 char/row
6 x 8 or 6 x 16 char. matrix (6 x 9
for PAL)
Character generation approach
minimizes memory
PAL and NTSC compatible
Page memory is accessed as extension of CPU memory during.nondisplay time
lCTU(DOTi
iTAilOOTl
.t:iiCi'i8*
"'"."
BUSE>
A sound output provides white noise and
eight octaves of programmable tones.
The output amplitude is variable in 16
steps from 0 Vto 0.78 VDD. This output Is
particularly useful In video game applications.
The CPU is clock Independent of the VIS
and Is not involved In screen refresh,
although a CPU clock output (Va DOT rate)
Is provided. At this clock rate 787 instructions (1080 for PAL) can be executed during non-dlsplay time. PREOisPLAY provides synchronization between the CPU
I
""
'""
CMSEL*
IWUT
H"S"friC*
EOMPi'm
BU$4
con
eU\l3
WMIRED\&
IUSO
IS
...
"'ss
20
cou
PALCHAOM (BLUII"
NUC CHAOM (611£11:""
ffir
ICHJJOM)
UAI.!CHRO',U
ffi
;w*
'FORTHERGI
acr,o·OI,ITOPTIOfII
COPI.'"
* INttllCHIPCONHECTIONS
IUS·3a_JIt
CDP1870, CDP1870C
CDP1878, CDP1878C
TERMINAL ASSIGNMENT
295
RCA CMOS LSI Products
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
Features: (cont'd)
•
•
•
•
•
Composite sync, composite
luminance, and composite
chroml6ance outputs
Programmable background color
Programmable color format control
allowing several modes for high
resolution color
Hardware scroll capability
Audio generator (576 selectable
tones covering 8 octaves) and white
noi~e generator.
and the VIS. The system configurations
for the CDP18691CDP1870 VIS are almost
unlimited due to:
PAGE MEMORY
• 20 Characters x 12 LinesRequires 240 Bytes of RAM
.40 Characters x 24 LinesRequires 960 Bytes of RAM
Character Memory-Can be RAM or
ROM
.32 Different (or any Combination
of) Characters-Requires 256
Bytes (NTSC)
• 64 Different Characters-Requires 512 Bytes (NTSC)
.128 Different Characters-Requires 1024 Bytes (NTSC)
• 256 Different Characters-Requires 2048 Bytes (NTSC)
Character memory requirements for PAL
are the same as NTSC in most
alphanumeric applications, but are 12.5%
higher for graphics applications due to
the larger character matrix (6x9) used for
PAL.
The CDP1869 and CDP1869C are functionally identical. They differ in that the
CDP1869 has an operating voltage range
of 4 to 10.5 volts and the CDP1869C has
an operating voltage range of 4 to 6.5
volts. The CDP1870 differs from the
•
•
•
•
Both tones and white noise can be
enveloped from 0 to 0.78 VDD In 16
steps
External horizontal and vertical sync
Inputs. allo w for Integration Into existing chassis for character-onpicture overlays
Teletext compatible format
RGB bond-out option available
(CDP1876)
CDP1870C in the same manner. All are
supplied in 40-lead hermetic dual-in-line
ceramic packages (0 suffix) and In
40-lead dual-ln-Iine plastic packages (E
suffix).
Color
Color information may be stored In the
two extra bits in each character byte
(characters are only six dots wide), providing a choice of one of four colors for
each character. With 128 different
characters, only seven bits are required In
the page memory and the eighth bit expands color to eight colors.
Graphics and Motion
Graphics and motion may be accomplished with two basic techniques.
The first is by character selection. In this
approach the desired graphics and
motion symbols are stored in ROM or
RAM. In a system where the character
memory is all ROM, all the possible required positions within a character space
are stored in the ROM. Graphics and motion are accomplished by selecting the
appropriate one for each screen position.
If the character memory is RAM then not
all combinations need be stored in the
character memory since they can be
modified as required during operation.
The second technique is used for more
sophisticated motion. In this technique a
block of characters in the RAM character
memory is treated as a continuous sur-
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Vollage referenced 10 VSS Terminal)
CDP1869, CDP1870, CDP1876 ............................................ -0.510 +11 V
CDP1869C, CDP1870C, CDP1876C ......................................... -0.510 + 7 V
INPUT VOLTAGE RANGE, ALL-INPUTS ..................................• -0.510 VDD +0.5V
DC INPUT CURRENT, ANY ONE INPUT ................................•........... , :t 10 mA
POWER DISSIPATION PER PACKAGE (PD):
For TA = -4010 + 60'C (PACKAGE TYPE E) ....................................... 500 mW
ForTA = +6010 + 85'C (PACKAGE TYPE E) ............ DeraleLinearlyal 12mW/'Cl0200mW
For T A = -5510 + 100'C (PACKAGE TYPE D) ...............................•...... 500 mW
ForTA = + 10010 125'C (PACKAGE TYPE D) ............. Derate Linearly al 12mW/'CIo 200mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) ........•....•.. 100 mW
OPERATING-TEMPERATURE RANGE (TAl:
PACKAGE TYPE D ....................................................... -5510 + 125'C
PACKAGE TYPE E ......................................................... -4010 + 85'C
STORAGE TEMPERATURE RANGE (T slg) ...................................•. -6510 + 15O'C
LEAD TEMPERATURE (DURING SOLDERING):
Aldislance1/16:t 1/32 Inch (1.59 :t 0.79mm)fromcasefor10smax .•..•.............. +285'C
296
l800-Series Peripherals
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
face. These characters are placed in adja·
cent locations on the screen to provide a
background. The object is moved through
this background using a bit map approach. As the object approaches the
"edge" of the characters as selected on
the screen, the background is moved. For
example, if the object approaches the
edge of the last background character on
the left, then the background characters
on the right are moved to the left side via
the page memory. Thus as the object
moves through these background
characters (as a continuous surface) it
moves across the screen.
RECOMMENDED CONDITIONS at TA = 25°C Unless Otherwise Specified
For maximum reliability, nominal operating conditions should be selected so
that operation is always within the following ranges:
CHARACTERISTIC
VDD
(V)
Supply-Voltage Range (At TA = Full PackageTemperature Range)
Input Voltage Range
STATIC CHARACTERISTICS at TA
CONDITIONS
Quiescent Device
Current, IL
Output Low Drive
(Sink) Current, IOl
(Except XT AL)
-XTAL Output,IO
Output High Drive
(Source) Current,
--
IOH
(Except XTAL)
XTAL Output,
4
-
VSS
10
5,10
Clock Input Frequency, tCl
CHARACTERISTIC
5
Input Signal Rise or Fall Time, t r , tt
LIMITS
CDP1869
CDP1869C
CDP1870
CDP1870C UNITS
Min. Max. Min. Max.
= -40 to
-
.
-
V
I-/S
MHz
I
.
-
0,5
0,10
0.4
0.5
05
0,10
5
10
2
4
2.4
4.8
0.4
0.5
5
10
5
10
75
150
150
300
4.6
0,5
5
-1.6 -1.8
9.5
4.6
9.5
0,10
0
0
0,5
0,10
0,5
0,10
10
5
10
5
10
5
10
5
10
5
10
5
10
-3.2 -3.6
-38 -75 -75 -150 0
0.05
0
0.05
4.95
5
9.95
10
1.5
3
3.5
7
- ±0.1 ±1
- ±0.1 ±1
5
10
-
V
LIMITS
CDP1869
CDP1869C
CDP1870C
CDP1870
UNITS
Min. Typ. Max. Min. Typ. Max.
100
500
- 100 500 I-/A
200 1000
-
VDD
(V)
5
10
-
6.5
+ 85°C, Except as noted
VIN
IOH
Output Voltage
Low-Level, VOL
Output Voltage
High Level, VOH
Input Low Voltage, 0.5,4.5 1,9
VIL
Input High Voltage, 0.5,4.5 1,9
VII-!
Input Leakage
Any
0,5
Input 0,10
Current, liN
3-State Output
0,5
0,5
Leakage Current,
0,10 0,10
lOUT
4
VDD VSS VDD
5
5
5
7. 15909(8.867236-PAL)
Vo
(V)
(V)
10.5
-
-
-
-
75
150
-
-
-
-
I-/A
-
mA
-
-
-
-
±0.2
±0.2
mA
2
-
-
-
-
+2
±0.2
2.4
-1.6 -1.8
-
-
-
-
-38
-75
-
-
-
0
0.05
-
-
4.95
5
-
-
-
3.5
-
-
±0.1
-
±0.2
-
-
I-/A
V
1.5
-
V
±1
±2
I-/A
I-/A
-
• Typical values are for TA = 25'C.
297
RCA CMOS LSI Products
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
lit Map Operation
.
The VIS may be used to display data In
a bit map format, offering a high resolu·
tlon display (up to 48,080 pixels) with up
to 7,880 (1olor blocks (8 colors). In this
mode; the character memory addresses
and the page memory addresses are used
to address the bit map memory. X·y coor·
dlnates are located by Implementing the
appropriate software.
ROB Boncl.()ut Option (CDP1878) - The
CDP1870 and CDP1870C may be ordered
with an alternate pln-out to provide direct
drive to the Internal TV chassis red, blue,
and green amplifiers. For the CDP1876,
the LUM, PAL CHROM, and NTSC
CHROM outputs become the RED, BLUE,
and GREEN outputs, respectively.
In the RGB mode of operation, the RF
and IF color demodulator circuits of the
TV chassis are bypassed and the com·
poslte sync, video, and color Information
are supplied directly to the appropriate
chassis sections. Since no color sub·
carrier is used, the CHROM crystal is not
needed, although the XTAL CHROM input
must be terminated (Fig. 1B). The
CDP1876, RGB Bond·Out option, offers
higher color resolution and Simpler Inter·
facing than the CDP1870, CDP1870C com·
poslte interface systems when used with
direct internal TV chassis systems.
OPERATION
CDP1888-Address and Sound O.n....lor
This circuit formats and controls sound,
page·memory addressing, and character'
memory addressing. This Is accom·
pllshed by software Instructions, data
from the CPU, and hardware Interaction
with the CDP1870 timing signals. Control
and multiplexing Is determined by Inter·
nal registers, which are loaded by four
CPU 110 Instructions. Data to the com·
mand registers are loaded from the 8
multiplexed address inputs (MA0/8MA7115). The high-order byte (MAS-MA15)
Is latched by the high to-low transition of
TPA, to provide up to 16 Internal data bils.
The 1/0 Instruction data are latched by the
high·to-low transition of TPB (Fig. 2).
OUT 4lnslrucllon - this Instruction uses
15 data blts(MAo-MA14) to control. the
tone output function. (Bit 15 Is unused.
but must be latched as a low). Bits MAOMA3 control the tone outpul amplitude
using an on-chlp binary Rl2R ladder net·
work to produce a varying output
amplitude In 16 steps. Bits MA4-MA6 con·
trol the tone output frequency range.
Eight octaves are available (TABLE 1).
Within each range the Input frequency Is
divided by the N + 1 value on bits MASMA14, producing up to 128 different fre·
quencles. The divided output Is a squarewave Signal gated on or off by bit MA7. A
high on MA7 turns the tone output off. If
both the tone and white noise are turned
off, the sound output Impedance Is equal
to 2.5R.
OUT 5 Instruction-This Instruction uses
13 data bits. (Bits MA1, MA2, and MA4 are
unused and need not be programmed).
The hlgher-order byte (MAS-MA15) Is used
to control the white noise output function.
Bits MAS-MA11 control the white noise
output amplitude using an on-chlp binary
Rl2R ladder network to provide a varying
output amplitude In 16 steps. Bits MA12MA14 control the white noise output fre·
quency range. Eight ranges are available
(TABLE 2). The white noise output Is
gated on or off by bit MA15. The result Is
Fig. 1A-System diagram using CDP1869 and CDP1870 (Composite Outputs).
See Fig. 1B using CDP1876 (RGB Bond-Out Option Outputs).
298
1800-Serles Peripherals
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
an explosion-type sound effect useful In
TV game systems. A high on MA15 turns
the white noise output off. If both the tone
and white noise are on, a combined
amplitude and frequency output results.
The lower-order byte (MAO-MA7) provides
screen format control. The CMEM ACCESS MODE Bit (MAO) Is used In conJunction with the OUT 6 Instruction to control
the character memory READIWRITE functions. A high on MAO enables the
character access mode.
The 9-L1NE bit (MA3) Is used to select
either 8-lIne or 9-lIne character matrix
operation. A low on MA3 selects 9-lIne
operation, which Is normally used with
PAL compatible signal timing (TABLE 7).
The 16-L1NE HI-RES bit (MA5) Is used to
define the vertical resolution of each
character by selective control of the
CMA3/PMA10 output. A low on MA5
defines each character as a 6x8 dot
matrix and PMA10 is available to extend
the page memory addressing. A high on
MA5 defines each character as a 6x16 dot
matrix by using CMA3 to extend the
character memory line addressing. Each
of the 16 character matrix lines may contain different data. The 16-L1NE HI-RES bit
(MA5) must be low If the DOUBLE-PAGE
bit (MA6) Is high. (During PAL operation,
where each character is normally a 6x9
dot matrix, the 16-L1NE HI-RES mode is
not available and MA5 should be programmed low).
CPUCLK
The DOUBLE-PAGE bit (MA6) is used to
select the function of the CMA3/PMA10
output. A low on MA6 selects the singlepage mode, in which the maximum page
memory size is limited to 960 bytes. The
VIS will normally do a roll screen operation when the end of the display page is
reached. In the single-page mode, the
CMA3IPMA10 output is available as
CMA3 to expand the character-memory if
the 16-line HI-RES bit is high. A high on
MA6 selects the double-page mode. In
this mode, the CMA3/PMA10 output functions as PMA10 to expand the pagememory addressing to 1920 bytes. At the
end of the first page a scroll automatically occurs. The next row entered is
displayed at the bottom of the screen,
with the previous page shifted up one
row. The old top row is no longer
displayed, but is still in memory.
In PAL systems, the double·page function
is normally useful only for alphanumeric
applications, since the CMA3 bit is not
available for addressing the charactermemory.
The FRES VERT bit (MA7) controls the full
screen vertical resolution of the display. A
low on MA7 sets the maximum resolution
to 12 rows of characters. A high on MA7
sets the maximum resolution of 24 rows
of characters.
I
All valid display format combinations are
shown in TABLE 8, along with the page
and character-memory requirements. Fig.
7 shows the relative character matrix
sizes.
OUT 6 Instruction-This instruction uses
11 data bits (MAO-MA 10) to load the pagememory address-register bits (PMAOPMA10). If the CMEM ACCESS MODE is
set (high), the page-memory address data
are latched to provide character selection
during a Character-memory READ/WRITE
operation. If the DOUBLE-PAGE bit is not
set (low), PMA10 is not used and does not
have to be programmed.
REDt-----~
BLUE/----+j
GREEN
TPB
DATA BUS
SOUND
92CS- 32699
Fig. lB-System diagram (same as that shown
in Fig. lA) using CDP1876 (RGB Bond·
Out Option).
If the CMEM ACESS MODE is not set
(low), the S multiplexed inputs (MAO/SMA7/15) are multiplexed to the pagememory address outputs (PMAO-PMA10)
and the page-memory functions as an extension of the CPU memory. When the
~a9wRemory is selected (F800-FFFF), the
outpu!..im9....ll!e PMSEL output are
M
enabled. The PMWR output is connected
to the WRITE input of the page-memory.
When using memories with a common
READ/WRITE input (RCA MWS5114), the
PMSEL output is connected to the select
input of the data-bus buffer/separator
(Fig. 1).
When the character-memory is selected
(F400-F7FF), the S multiplexed inputs
(MAO/S-MA7/15) are multiplexed to the
299
RCA CMOS LSI Produ'cts
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
OUT 6 Instruction (cont'd)
c;haracter-memory address outputs (CMAO-CMA3), and the CMWR and
CMSEL outputs are enabled. The CMWR
output is connected to the WRITE input of
the character-memory. The CMSEL output
is connected to the CMSEL input of the
CDP1870C to provide data bus multiplexing. If the DOUBLE-PAGE bit is set
(high), CMA3 is not used and bit MA3 does
not have to be programmed.
Out 7 Instruction-This instruction uses 9
data bits (MA2-MA10) to load the home
address register bits (HMA2-HMA10). The
home address determines which row of
characters, from the page-memory, is
displayed starting at the top left-hand corner of the screen. In the FULL RES HORZ
MODE (CDP1870), the home address must
be an even multiple of 40. In the HALF
RES HORZ MODE (CDP1870), the home
address must be an even multiple of 20.
Therefore, the HMAO and HMA1 bits are
not used and do not have to be programmed.
After the last row of characters has been
displayed, the home address is reloaded
into the page-memory address counter to
begin the next display frame. When final
page memory address count (maximum
page-memory size in TABLE 8) is reached
prior to the end of the display, zero is
loaded into the address counter. Changing the home address can be used to
scroll through the page-memory. In the
double-page mode, row zero will scroll on
to the screen after the final row, as
described above.
CDP1870-Color VIdeo Generator'
This circuit formats and controls the TV
sync, video, and color information. It also
provides synchronization timing to the
CDP1869 and the CPU. The charactermemory data 110 lines are multiplexed
through the CDP1870 to the CPU 8-bit
bidirectional data bus. This Is accomplished by software instructions,
data from the CPU, and hardware interaction with the CDP1869 timing Signals.
Control and multiplexing is determined by
a Single Internal command reglster,-which
is loaded by a CPU I/O instruction. Data to
the command register are loaded from the
8-bit bidirectional data bus, which is
latched by the..J.!!il!1-to-low transition of
TPB when the MRD and the 'Ff;3 inputs
are at a logic 0 (Fig. 3).
OUT 3 Instruction-This instruction uses
8 data bits to control the Internal format
and timing functions. The BKG GREEN,
BKG BLUE, BKG RED bits (BUSQ-BUS2)
provide a binary selection of eight screen
background colors, as shown in TABLE 5.
The CFC bit (BUS 3) selects the color format control function (TABLE 4). When the
CFC bit Is low, the background luminance
300
and chromlnance are selected by the BKG
GREEN, BKG BLUE, and BKG RED control
bits. The dot chromlnance and luminance
are selected by the CCBO, CCBI, and PCB
Inputs. Operation Is the same when the
CFC bit Is high, except that the dot
chromlnance Is now selected by the BKG
GREEN, BKG BLUE, and BKG RED control
bits to provide a tone-on-tone color
display. The DISP OFF bit (BUS 4) Is used
to turn the screen display off. When the
DISP-OFF bit Is high, the PAL CHROM,
NTSC CHROM, and LUM outputs are held
at the bac'l'0und color and the AOOSTB,
PREDISP[ Y, and DISPLAY outputs are
held atJ!.l!.!.!l!!..level. However, the ~
S'fNO, HSYJiJC, and CPUCLK outputs continue to supply synchronization timing.
This display-off condition allows the CPU
to access the VIS, page memory, and
character memory asynchronously. Any
change In this bit Is only recognized at the
end of the frame. The COLBO and COLB1
bits (BUS 5, BUS 6) provide a binary selection of 3 character-color control modes,
as shown In TABLE 3_ These 3 modes. control which color bit Inputs (CCBO, CCB1,
PCB) select a particular character color
(TABLE 5). The FRES HORZ bit (BUS 7)
controls the full screen horizontal resolution of the display. A low of BUS 7 sets the
maximum resolution to 20 characters per
row. A high on BUS 7 sets the maximum
resolution to 40 characters per row_ All
valid display format combinations are
shown In TABLE 8.
The CDP1870 uses two separate input frequencies. On-chip oscillators are provided, requiring only external crystal circuits. One oscillator circuit provides the
dot clock frequency, from which SYNC
and ADDSTB timing is derived. The DOT
frequency, divided by two, provides a CPU
CLK output. The other oscillator circuit
provides the color reference and
chrominance frequencies. The NTSC
CHROM, PALCHROM, and LUM outputs
include on-chip summing resistors to
reduce the external components reg~re~.
The outputs are connected to the C M SYNC output to provide a Single video
Signal, which may be used to drive a video
monitor directly or a standard TV receiver
through an RF modulator circuit.
(WIth the RGB Bond-Out option, CDP1876,
the color crystal Is not used and the LUM,
NTSC CHROM, and PAL CHROM become
the RED, BLUE, and GREEN outputs,
respectively.)
The EVS and EHS Inputs may be used to
sync the VIS from an existing TV chassis
to provide picture overlay and teletext
operations. The PAUNTSC Input Is used
to select either European or U.S. Operation (TABLE 6 and 7).
The VIS does not provide for an external
system reset. All command and format Instructions must be executed before proper operation In Initiated.
1800-Series Peripherals
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
1--_(25)CMA3/PMAIO
Fig. 2-CDP1869 and CDP1869C block diagram.
DOT
XTAL
I
PREDISPLAY
2
DiSPUi.Y
I
CDBO-CDB5
ADDSTB
CPUCLK
BURST
COMPSYNC
LUM (RED)"
MRD
NTSC CHROM (GREEN)"
TPB
PAL CHROM (BLUE)"
No 3
"RGB BONO- OUT OPTION
COPI876
92CM-31911RI
XTAL XTAL
CHROM
Fig. 3-CDPI870, CDPI870C, CDP1876, and CDP1876C block diagram.
301
RCA. CMOS LSI Products
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
FUNCTIONAL DESCRIPTION OF
CDP1889 TERMINALS
TPA (Input):
An active high pulse from the CPU that
occurs once In each machine cycle. The
trailing edge of TPA Is used to latch the
hlgher-order byte of the 16-blt memoryad·
dress. TPA Is also one of the frequency
generator Input clocks,
TPB (Input):
An active high pulse from the CPU that
occurs once In each machine cycle,
following TPA. It Is used to latch the
various Internal command registers. TPB
Is also one of the frequency generator Input clocks.
MRD (Input):
An active low pulse from the CPU, Indicating a memory read cycle. It Is used to
provide various latch and control functions.
MWR (Input):
An active low pulse from the CPU, appearIng In a memory write cycle after the address lines have stabllzed. It Is used to
gate various latch and control functions.
MA0I8-MA7/15 (Inputs):
The 8 memory address lines. The higher·
order byte of. a 16-blt CDP1802 or
CDP1804 memory address appears on the
memory address lines MA()'MA7 first, and
Is latched by the hlgh-to.Jow transition of
TPA. These 8-lInes serve a dual purpose.
They can be used to provide direct address Information to the page or
character memories or they can be used
to provide data to the command registers.
NO to N2 (Inputs):
These lines are used to issue command
codes during an 1/0 instruction from the
CPU. Their state is the same as the cor·
responding bits in the CPU N register. The
three N bits are internally decoded with
MRD to provide various latch and control
functions.
HSYNC (Input):
Active low horizontal sync signal from the
CDP1870. This signal provides synchronization between the CDP1869 and
the CDP1870 timing signals.
DISPLAY (Input):
Active low signal from the CDP1870 that
indicates that a screen refresh Is In pro·
gress. This signal provides synchronlza·
tlon between the CDP1869 and the
CDP1870 timing signals.
ADDSTB (Input):
Active low pulses from a CDP1870 that
provide page and character-memory ad·
dress clock timing. ADDSTB
DOT
clock + 6 (40 character display). ADDSTB
= DOT clock + 12 (20 character display).
Only 40 or 20 pulses are generated per
horizontal line, and no pulses occur durIng non-dlsplay time.
=
302
SOUND (Output):
This output provides two types of frequency Signals that can be selected
either Individually or In combination. The
first type provides Single frequency· tones
In 8 selectable ranges, with 128 different
tones in each range (TABLE 1). The second type provides a white-noise output
in 8 selectable ranges, with the white
noise consisting of all 128 tones of each
range (TABLE 2). Both tone and whitenoise outputs are programmable from 0
volts to 0.78 VDD In 16 steps.
VSS:
Ground
N=i (Output):
Active low output from the internally
decoded N bits that is normally connected to the CDP1870. It Is used to select
the CDP1870 command register.
CMAO·CMA2-CHARACTER·MEMORY
ADDRESS (Outputs):
The character memory address outputs.
These three outputs function as
character-line selects. During a screen
refresh the address data are provided by
an internal counter, which is controlled by
~, to provide character information
in one of eight formats (Fig. 7). During
non·refresh periods the address data are
provided by the MAO-MA2 Inputs as an extension of the CPU memory.
CMA3IPMA10 (Output):
This output signal serves a dual purpose.
In the 16-LlNE HI-RES character mode
(command bit 5 = 1) this output represents CMA3 and Its function is Identical
to the CMA()'CMA2 outputs. In the 9·LlNE
mode (command bit 3 = 0), this signal
represents CMA3 In both the low-and
high-resolution modes (command bit
5 =0 or 1), and Is used to select the ninth
line of the character matrix. In the doublepage mode (command bi~ 6 = 1) this output represents PMA10 and Its function Is
Identical to the PMA()'PMA9 outputs.
PMAO·PMA9-PAGE·MEMORY
ADDRESS (Outputs):
These ten page-memory address outputs
access the page·memory data (PMDO-6),
7 bits of which are used to address the
character memory. The spare bit (PCB)
may be used to expand the color Information. During a screen refresh the address
data are provided by an internal counter,
which is controlled by ADDSTBto provide
page·memory information in one of four
formats (TABLE 8). During non·refresh
periods the address data are provided by
the MA0/8-MA9/15 Inputs as an extension
of the CPU memory.
'Ci.iWR-CHARACTER·MEMORY WRITE
cgMt;t,:s an active low output signal that
Is connected to the WRITE Input of the
1800-Serles Peripherals
CDP1869, CDP1869C, CDP1870'~"CDPf870C, CDP1876, CDP1876C
characteL.!IWJ1ory. This output provides a
delayed MWR pulse during non-display
periods, when the character memory is
selected by the MA10-MA15 inputs
(F400-F7FF).
CMSEL- CHARACTER-MEMORY
SELECT (Output):
CMSEL is an active high output signal
that is connected to the CDP1870 CMSEL
input. This output provides a delayed
positive pulse during non-display periods,
when the character memory is selected
by the MA10-MA15 inputs (F400-F7FF)
and tlJ!m or MWR is low.
PMWR-PAGE-MEMORY
WRITE (Output):
~ is an active low output signal that
Is connected to the WRITE input of the
page memory. This output provides a
delayed MWR pulse during non-display
periods, when the page memory is
selected by the MA11-MA15 inputs
(F800-FFFF).
PMSEL-PAGE-MEMORY
SELECT (Output):
PMSEL is an active high output signal
that is connected to an external bus
separator. This output provides a delayed
positive chip-enable pulse during nondisplay periods, when the page memory is
selected by the MA11-MA15 inputs
(F800-FFFF) and"MRO or l\W9Ff'is low.
VDD
Positive supply voltage.
FUNCTIONAL DESCRIPTION OF
CDP1870 TERMINALS
""PR::':E=>D=:-:I""'Sp::':L..-JA
CMEM
ACCESS
X
MODE
PMAl
PMAO
REG
REG
X"
X"
•• = ALWAYS LATCHED LOW INTERNALLY
••• MUST BE LATCHED LOW DURING 9-LlNE OPERATION
309
RCA CMOS LSI Products
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
-
012345
I I II I
COLUMUN
01234567891011
I I I I I II I I I I
NUMBER_
012345
01234567891011
rGB~zt___
==~~[~\~~~F
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-----
-
-
;br-H=
r ;,.
-
'.'.
'-
:
"
. --
'--
~.",...",-"
r---I
24-
liJ
If'-r---.I
30.":':':',,:
l i : i ...
29-111~:=::LJ.h+22J
2128-
31
SIZE NUMBER
CHART 8)
"
20-
~~
. '
~CHAR,
(SEE
I •
.....
10-
i .
.
==
567-
6
I
7
92CL-31908RI
8
Fig. 7-Character display matrix size.
TABLE 10
CDP1870 COMMAND REGISTER CODE
CPU 110
INSTRUCTION
OUT 3
310
BUS 7
FRES
HORZ
BUS6
COLB1
BUS 5
COLBO
BUS4
DISP
OFF
BUS 3
CFC
BUS2
BKG
RED
BUS 1
BKG
BLUE
BUSO
BKG
GREEN
1800-Serles Peripherals
CDP1869, CDP1869C, CDP1870, CDP1870C, CDP1876, CDP1876C
1
COL,
01234~
0
Nr
"'z
~'"
EACH CHARACTER IS
A 6X8 DOT MATRIX (NTSCl
OR A 6,9 DOT MATRIX (PALl
"'-PAL ONLY
."'"
~
'"
0
0
"'"
iii
r
~
"
I
I
<
~I
~
(;
!1l
z
"
*
I
I
I
: / ' AilDSTB COUNT
o
.
...'"
,.r
:
:
0
56
60
.Jr---i:----------~H~O=-R~,Z~O~N:TA;L:S;Y~N=-C:*~--------~:----1~
~
60
I 4
I
~~______________B~U~R~ST~__________________~r
* HORIZONTAL AND VERTICAL SYNC ARE COMBINED TO FORM COMPSYNC
92CM - 31909Rl
Fig, 8-40 x 24 character display,
OPERATING AND HANDLING
CONSIDERATIONS
1. Handling
All inputs and outputs of RCA COS/MaS
devices have a network for electrostatic
protection during handling,
Recom·
mended handling practices for COS/MaS
devices are described in ICAN·6525.
"Guide to Better Handling and Operation
of CMOS I ntegrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum
supply voltage limit. care should be
taken to avoid or suppress power supply
turn·on and turn·off transients. power
supply ripple. or ground noise; any of
these conditions must not cause VDD-
VSS to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protec·
tion circuit. input signals should never be
greater than VD D nor less than VSS.
Input currents must not exceed 10 mA
even when the power supply is off.
Unused Inputs
A connection must be provided at every
input terminal. All unused input termi·
nals must be connected to either VDO or
VSS. whichever is appropriate.
Output Short Circu its
Shorting of outputs to VDD or VSS may
damage COS/MOS devices by exceeding
the maximum device dissipation.
311
RCA CMOS LSI Products
CDP1871A, CDP1871AC
Preliminary Data
CMOS Keyboard Encoder
:: ~ :: ;~~:,eL
1;~-= i
09-
B
e,
,
01
10
"52
"
..,
32
BUS 7
Features:
O£BOUNCE
":n,.~ ITArea
• Directly interfaces with CDP1800-series
microprocessors
• Low power dissipation
• 3-State outputs
• Scans and generates code for 53 key ASCII
keyboard plus 32 HEX keys (SPST mechanical
contact switches)
• Shift, control, and alpha lock inputs
• RC-control/ed debounce circuitry
• Single 4 to 10.5 V supply (CDP1871A); 4 to 6.5 V
(CDP1871AC)
• N-key lockout
~I :~::
29C
"
BUS 4
aus 2
26
BUS I
"
56
CS.
'"
'"
'"
'"
Terminal Assignment
vents unwanted key codes if two or more keys are pressed
s i m u Ita neously.
The RCA-CDP1871A is a keyboard encoder designed to
directly interface between a CDP1800-series microprocessor and a mechanical keyboard array, providing up to 53
ASCII coded keys and 32 HEX coded keys, as shown in the
system diagram (Fig. 1).
.
The CDP1871A and CDP1871AC are functionally identical.
They differ in that the CDP1871 A has a recommended operating voltage range of 4 to 10.5 volts, and the CDP1871AC
has a recommended operating voltage range of 4 to 6.5
volts. These types are supplied in 40-lead dual-in-line
ceramic packages (D suffix), and 40-lead dual-in-line plastic packages (E suffix).
The keyboard may consist of simple single-pole singlethrow (SPST) mechanical switcr.es. Inputs are provided for
alpha-lock, control, and shift functions, allowing 160
unique codes. An external R-C input is available for userselectable debounce times. The N-key lock-out feature pre-
21
DEBOUNCE
gk
NO - N 2 f--'C""O"'NT=R:C-OL--'\.I
f----.,2"3-v'1 CS3
MRli f -_ _ _""24'-+jCS4
TPS _ _ _ _ _~3~4'-+jTPB
CDPI871A
COP1BOQ- SERIES
CPu
Voo
SHIFT
f-----+-t>(2e) BUS 0
>--Ho@~BUS' 7
VDD-®
vss-@l
313
RCA CMOS LSI Products
CDP1871A, CDP1871AC
STATIC ELECTRICAL CHARACTERISTIC at TA
= -40 to +85'C,
CONDITIONS
CHARACTERISTIC
Va
(V)
Quiescent Device
Current
Output Low Drive (sink) Current
(except debounce and 01-011)
Oebounce
01-011
Output High Drive (Source) Current
100
IOL
IOL
IOL
IOH
Input Low Voltage
(except Oebounce)
Input High Voltage
(except Oebounce)
Oebounce Schmitt Trigger
Input Voltage
Positive Trigger Voltage
Negative Trigger Voltage
Hysteresis
Output Voltage Low Level
V,L
V,H
Vo
VN
VH
VOL
VOH
0.4
0.5
0.4
0.5
0.4
0.5
I,N
Rpo
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
-
0.5
0,10
-
-
0.5,4.5
0,5
0,10
-
(V)
LIMITS
CDP1871AD
CDP1871ACD
UNITS
CDP1871AE
CDP1871ACE
MIN, TYP.' MAX. MIN. TYP.' MAX.
1
0.1
50
200
/1 A
1
200
1
0.5
1
0.5
2
1
1.5
0.75
1.5
0.75
1
2
mA
.05
0.1
0.1
.05
0.1
0.2
0.6
0.3
0.6
0.3
1.5
0.75
1.5
1.5
3
3.5
3.5
-
-
7
2.0
4.0
0.8
1.9
0.3
0.7
-
-
-
-
-
4.0
8.0
3.0
6.0
2.6
4.7
.05
.05
2.0
3.3
4.0
-
-
-
0.8
1.8
3.0
-
-
-
0.3
1.6
2.6
-
-
-
-
0
.05
5
10
5
10
5
10
5
10
5
10
4.95
9.95
5
10
5
10
-
3.3
6.3
1.8
4.0
1.6
2.3
0
0
5
10
.01
.01
.01
.02
-
7
14
5
10
-
-
0.6
2.7
-
V
-
-
-
4.95
5
--
-
-
-
-
.01
1
-
-
-
-
.02
2
-
-
24
7
14
24
kn
-
-
0.6
-
-
rnA
-
1
1
1
2
/1 A
loper
1.9
'Typical values are for TA = +25' C. and nominal Voo.
314
Voo
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
lOUT
Pull-Down Resistor Value
(Sl-S8. Shift, Control)
Ope rati ng Cu rrent
(All-outputs fcL = 0.4 MHz
unloaded)
fcL = 0.8 MHz
0.4
0.5
0.4
0.5
0.4
0.5
4.6
9.5
0.5,4.5
1,9
0.5,4.5
1,9
-
Output Voltage High Level
Input Leakage Current
(except Sl-S8. Shift. Control)
3-State Output Leakage Current
-
VIN
(V)
except as noted
1800-Serles Peripherals
CDP1871 A, CDP1871 AC
FUNCTIONAL DESCRIPTION OF CDP1871A TERMINALS
D1 - 011 (Outputs):
Drive lines for the 11 x 8 keyboard switch matrix. These
outputs are connected through the external switch matrix
to the sense lines (S1 - S8).
S1 -
S8 (Inputs):
Sense lines for the 11 x 8 keyboard maxtrix. These inputs
have internal pull-down resistors and are driven high by
appropriate drive line when a keyboard switch is closed.
CSt, CS2, CS3, CS4 (Inputs):
Chip select inputs, which are used to enable the tri-state
data bus outputs (BUS 0 - BUS 7) and to enable the
resetting of the status flag (OA). which occurs on the lowto-high transition of TPB. These four inpRts are normally
connected to the N-lines (NO-N2) and M 0 output of the
COP1800-series microprocessor. (Table 2)
BUS 0 - BUS 7 (Outputs):
Tri-state data bus outputs which provide the ASII and
HEX codes of the detected keys. The outputs are normally
connected to the BUS 0 - BUS 7 terminals of the COP1800series microprocessor.
DA (Output):
The data available output flag which is set low when a valid
key closure is detected. It is reset high by the low-to-high
transition of TPB when data is read from the COP1871A.
This output is normally connected to a flag input (EF1-EF4)
of the COP1800-series microprocessor.
TPB (Input):
The input clock used to drive the scan generator and reset
the status flag (l5A). This input is normally connected to the
TPB output of the COP1800-series microprocessor.
APT (Output):
The repeat output flag which is used to indicate that a key is
still closed after data has been read from the COP1871A
(OA = high). It remains low as long as the key is closed and
is used for an autorepeat function, under CPU control. This
outpuUs normally connected to a flag input (EF1-EF4) of
the COP1800-series microprocessor.
DEBOUNCE(lnput):
This input is connected to the junction of an external resistor to.Voo and capacitor to Vss. It provides a debounce time
delay (t "" RC) after the release of a key. If a debounce is not
desired, the external pull-up resistor is still required.
ALPHA, SHIFT, CONTROL (Inputs):
A high on the SHIFT or CONTROL inputs will be internally
latched (after the debounce time) and the drive and sense
line decoding will be modified as shown in Table 3. They are
normally connected to the keyboard, but produce no code
by themselves. The SHIFT and CONTROL inputs have internal pull-down resistors to simplify use with momentary
contact switches. The ALPHA input is not latched and is
designed for a standard SPOT switch to provide an alphalock function. When ALPHA = 1 the drive and sense line
decoding will be modified as shown in Table 3.
Voo, Vss:
Voo is the positive supply voltage input. Vss is the most
negative supply voltage terminal and is normal connected
to ground. All outputs swing from Vss to Voo. The recommended input voltage swing is from Vss to Voo.
TABLE 1 - SWITCH INPUT FUNCTIONS
CONTROL
0
1
0
0
x=
SHIFT
0
X
1
0
KEY FUNCTION
NORMAL
CONTROL
SHIFT
ALPHA
ALPHA
0
X
X
1
DON'T CARE
TABLE 2 CPU
CS4
COP1800SERIES
SIGNAL
MRO
MRO
MRO
VALID N-LINE CONNECTIONS
CDP1871A SIGNAL
CS3
CS2
N2
NO
N2
NO
N1
N1
CS1
CPU INPUT
INSTRUCTION
N1
N2
NO
INP5
INP3
INP6
315
I
RCA CMOS LSI Products
CDP1871A, CDP1871AC
TABLE 3 -
DRIVE AND SENSE LINE KEYBOARD CONNECTIONSt
52
89,.
91,.
99,.
53
8A,.
92,.
9A'6
S.
88,6
93,.
98,6
55
8C,.
94,6
9C,.
56
80,6
95,6
90,6
57
8E,.
96,6
9E,.
S.
8F,.
97,.
9F,.
lUI =
'CONTROL overrides SHIFT and ALPHA
NO RESPONSE
tShowing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL.
tDrive lines 8, 9, 10, and 11 generate non-ASCII hex values which can be used for special codes.
TABLE 4 -
HEXIDECIMAL VALUES OF ASCII CHARACTERS
MSD
b7- 0
b60
bS..
0
BITS
o
o
1
o
b1
0
o
r
o
o
0
o
0
NUL
OLE
o
o
o
0
1
1
SOH
1
o
1
1
1
1
1
0
0
1
o
2
3
4
STX
' ETX
EOT
1
5
ENQ
OCl
OC2
OC3
OC4
NAK
%
o
&
1
1
ACK
BEL
SYN
1
o
6
7
8
9
A
8
C
0
E
1
F
1
1
1
1
1
o
1
o
o
Ht:.X
b2
o
o
o
o
o
1
o
1
b3
o
o
o
o
316
o
b4
o
LSD
o
0
o
0
1
1
o
1
1
0
0
1
1
o
1
3
4
o
@
S
p
\
A
Q
a
B
C
R
b
#
2
3
4
S
T
c
5
6
E
U
e
u
F
G
H
v
w
x
9
v
w
x
$
ETB
BS
CAN
HT
EM
LF
SUB
VT
ESC
7
)
8
9
o
h
z
z
<
K
L
M
RS
>
N
n
US
?
o
o
FF
FS
CR
GS
SO
SI
s
d
Y
J
+
6
7
p
q
2
SP
k
\
m
DEL
1800-Serles Peripherals
CDP1871A, CDP1871AC
OPERATION
The CDP1871A is made up of two marar sections: the
is removed, allowing the scancounters to advance on the
following high-to-Iow transitions of TPB. This provides an
counter/scan-selection logic and the control logic (Fig. 2).
The counter and scan-selection logic scans the keyboard
N-key lockout feature, which prevents the entry of erroneous codes when two or more keys are pressed simultaarray using the drive lines (D1-D11) and the sense lines
(S1-S8). The outputs of the internal 5-stage scancounter
neously. The first key pressed in the scanning order is
are conditionally encoded by the ALPHA, SHIFT, and CONrecognized, while all other keys pressed are ignored until
TROL inputs (Table 1, Table 3) and are used to drive the
the first key is released and read by the CPU, at which time
D1-D11 output lines highoneata time. Each D1-D11 output
the next key pressed in the scanning order is detected. If the
may drive up to eight keys, which are samp'led by the sense
fir!lt key re.!!!.ains closed after the CPU reads the data and
line inputs (S1-S8). The S1-S8 inputs are enabled by the
resets the DA output on the low-to-high transition of TPB,
internal 3-stage scancounter.
an auxiliary signal (RPT) is generated and is available to the
CPU to indicate an auto-repeat condition. The APi' output
The control logic interfaces with the CDP1800-series I/O
is reset high at the end of the debounce delay after the
and timing signals to establish timing and status conditions
depressed key is released.
for the CDP1871A.
The TPB input clocks the scanc.Q!!!lters and is also used to
reset the Data Available output (DA). When a valid keydown
condition is detected on a sense line, the control logic
inhibits the clock to the scancounters on the next low-tohigh transition of TPB and the 5A output is set low. The
scancounter outputs (C1-C8) represent the ASCII and HEX
key codes and are used to drive the BUS 0 - BUS 7 outputs,
which interface directly to the CDP1800-Series data bus.
The BUS 0 - BUS 7 outputs, which are normally tri-stated,
are enabled by decoding the CS inputs during a CPU input
instruction (Table 2). The low-to-high t!:l!!!sition of TPB
during thEllnput instruction resets the DA output high.
Once the DA output has been reset, it cannot go low again
until the present key is released and a new keydown condition is detected. (This prevents unwanted repeated keycode
outputs which may be caused by fast software routines).
After the depressed key is released and the debouncedelay
(determined by RX, CX) has occurred, the scan clock inhibit
The DEBOUNCE input provides a terminal connection for
an external user-selected RC circuit to eliminate false detection of a keydown condition caused by keyboard noise.
The operation of the DEBOUNCE circuit is shown in Fig. 2
(Pin 36). When a valid keydown is detected, the on-Chip
.active-resistor device (RN) is enabled and the external capacitor (Cx) is' discharged, providing a key closure debounce time"" RNCX • This discharge is se~d by the
Schmitt-tiggeLJnverter, which clocks the DA flip-flop
(latch!!:!g the DA output low and inhibiting the scan cloCk).
(The DA F/F is reset by the low-to-high transition of TPB
when the CS inputs are enabled). When a valid key-release
is detected RN is disabled and Cx begins to charge through
the external resistor (Rx), providing a key-release debounce
time"" RxCx. This charge time is again sensed by the
Schmitt-trigger inverter, enabling the scan clock to continue on the next high-to-Iow transitions of TPB, after the
current keycode data is read by the CPU.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA -40 to +8SoC Vee ±S%
CHARACTERISTIC
Voo
Clock Cycle Time
tcc
Clock Pulse Width High
tCWH
Data Available Valid
Delay
Data Available Invalid
Delay
Scan Count Delay
(Non-Repeat)
Data Out Valid Delay
tOAl
tOAH
tCD1
tcov
Data Out Hold Time
tCOH
Repeat Valid Delay
tAPl
Repeat Invalid Delay
tAPM
..1~
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
LIMITS
CDP1871ACD
CDP1871AD
CDP1871ACE
CDP1871AE
TYP.TYP.·
MIN.
MAX.
MIN.
MAX.
-
-
100
50
40
-
20
260
130
70
35
850
425
120
60
100
50
150
75
350
170
500
250
150
75
1900
950
250
125
200.
100
400
200
700
350
-
-
-
100
40
-
-
260
500
-
-
70
150
-
-
850
1900
120
250
-
-
100
200
-
-
150
400
-
-
350
700
-
-
-
-
-
UNITS
NOTE
1
ns
ns
ns
ns
ns
ns
ns
ns
'TYPical Values are for TA = + 25° C and nom mal Voo
Note 1: tcc = tewH + tewL
tewl = teDl + KC
k = 0.9 X 10-9 n
c = keyboard capacitance (pF)
317
I
RCA CMOS LSI Products
CDP1871A, CDP1871AC
I
I
I
I
r-RXCx-1~_ _ _ _-IIf--_ _
~--~---I~
DEBOUNCE
I
:t-__"1:___________ t-- , 'COl
DI-DII _ _ _;';';';=~"";';;;;;';';""_ _
~NT
+-____
CS* _ _ _ _ _ _
BUSO-BUS7
~--------~--------~u------~u-------~1
-I
tCDV\-
f
~ tCDH I-
--------~~------~~-----;U~----~&--------_<<:~_1VA~L~ID~~»>-----
* CS- -CSloCS2oCS3.CS4
ffi.
CS2. CS3 • i:l>u N-LINES
CS4 (MliIi'IIS HIGH FOR CPU INPUT INSTRUCTION
Fig. 3 - CDP1871A dynamic timing diagram (non-repeat).
n
TPB
Ii
I
KEV
DEPRESSED
I
-J
I
1lA
I
OPEN
r-'DAH
II
I
I
1/
~tRP~
~tRPL
---I
I
1Wf
U
CLOSED
II
:
u~~------------------
I--RxCX:..j
~--------------~-----~------------------Ii
DEBDUNCE
.
:
PRESENT
Dt-DII _ _ _ _
_ _ _ _COUNT
_ _ _ _ _ _~~------~
---1
CS*
~'CDV
BUSO-BUS7
*
f-
--<:
I
~tCDHrVALID
II
II
;»-~U-------*Il----------------
rn
CS 0 CS2 'CS3oCS4
CS- EST. CS2 .CS3 - (CPU N-LiNESI
CS4 (MRD) IS HIGH FOR CPU INPUT INSTRUCTION
Fig. 4 - CDP1871A dynamic timing diagram (repeat).
318
NEXT COUNT
92CM-3&007
1800-Series Peripherals
------------------------------------------------------~~~.
CDP1871A, CDP1871AC
OPERATING AND HANDLING CONSIDERATIONS
1, Handling
All inputs and outputs of RCA Microprocessor devices
have a network for electrostatic protection during handling. Recommended handling practices for Microprocessor devices are described in ICAN-6525, "Guide to
Better Handling and Operation of CMOS Integrated
Circuits."
2, Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must not
cause Voo-Vss to exceed the absolute maximum rating.
Input Signall
To prevent damage to the input protection circuit. input
signals should never be greater than Voo nor less than
Vss.lnputcurrents must not exceed 10 mAeven when the
power supply is off.
Unuled Inputl
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Voo or Vss, whichever is appropriate.
Output Short Clrcultl
Shorting of outputs to Voo or Vss may damage Microprocessor devices by exceeding the maximum device
dissipation.
•
92CM - 32 '30RI
Fig. 5 - Typical system software flowchart
for CDP1871A, CDP1871AC.
ORDERING INFORMATION
RCA Microprocessor device packages are identified by letter indicated in the following chart. When ordering a Microprocessor device. it is important that the appropriate
suffix letter be affixed to the type number of the device.
Package
Suffix Letter
Dual-In-Line Side-Brazed Ceramic
D
Dual-In-Line Plastic
E
For example. a CDP1871AC in a dual-in-line plastic package will be identified as the CDP1871ACE.
319
RCA CMOS LSI Products
CDP1872C, CDP1874C, CDP1875C
IT!
DID
000
01 I
001
012
002
013
003
CLOCK ._-
Vss -
22
21
20
19
18
17
16
15
14
13
12
I
2·
4
5
6
10
"
High-Speed
8-Blt Input and Output Ports
Voo
017
007
016
006
015
005
014
004
- CLR
Feature8:
• Parallel 8-bit input/output register with buffered outputs
• High-speed data-in to data-out:
85 ns (max.) at V00=5 V
• Flexible applications in microprocessor systems as
buffers and latches
• High order address-latch capability in COP1800 series
microprocessor systems
• Output sink current=5 mA (min.) at VOO=5 V
• 3-state output-COP1872C and COP1874C
CS2
g2<'~-
:nOt2
CDP1872C Input Port
TERMiNAl. ASSIGNMENT
The RCA-CDP1872C, CDP1874C and CDP1875C devices
are high-speed 8-bit parallel input and output ports
designed for use in the CDP1800 microprocessor system
and for general use in other microprocessor systems. The
CDP1872C and CDP1874C are 8-bit input ports; the
CDP1875C is an 8-bit output port.
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects. The CDP1872C has one active
low and one active high select; the CDP1874C has two
C51
I
DID
2
3
4
000
011
001
012
002
013
003
CLOCK
7
8
9
10
Vss
II
22
21
20
19
18
17
16
15
14
13
12
5
6
Voo
017
007
016
006
015
005
014
004
CLR
C52
TOP VIEW
92CS-33011
CDP1874c Input Port
TERMINAL ASSIGNMENT
320
Preliminary Data
active high device selects. These devices also feature 3state outputs when deselected. Data is strobed into the
register on the leading edge of the CLOCK and latched on
the trailing edge of the CLOCK.
The COP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
Thesa devices are supplied in 22-lead hermetic, dual-in-line
side-brazed ceramic packages (0 suffix) and in 22-lead
dual-in-line plastic packages (E suffix).
IT!
010
000
011
001
012
002 013
003
C53
V55
22
21
20
19
18
17
16
15
14
13
12
4
5
6
7
8
10
"
Voo
017
007
016
006
015
005
014
004
CLR
C52
TOP VIEW
92CS-33010
CDP1875C Output Port
TERMINAL ASSIGNMENT
1800-Serles Peripherals
CDP1872C, CDP1874C, CDP1875C
91-..------...
RECOMMENDED OPERATING CONDITIONS at
TA=-40o'C to +8S°C. For maxImum reliability, operating
CS2
DI - - - - - - - i D
conditIon••hould be .e/ected .0 that operation I. alway.
within the following range.:
CHARACTERISTIC
DC Operating-Voltage Range
Input Voltage Range
}--------,
C~OCK
-'t------i
DO
LIMITS
UNITS
ALL TYPES
4 to 6.5
VSS to VDD
CIJI ---
17
AIO
MA2
I.
All
MAl
15
ese
MAD
I.
CSt
MRD
13
eS2
• Performs memory address latch and
decoder functions multiplexed or
non-multiplexed
• Interfaces directly with the CDP1800series microprocessors
• Can replace existing CDP1866 and
CDP1867 (upward speed and function
capability)
• Allows decoding for systems larger
than 16K
MWR
Vss
VOD
m
12
10
TI
"
TOP VIEW
92CS~
34998
CDP1881
Term'na' A"'gnmenl
The RCA-CDP1881 and CDP1882 are CMOS 6-bit memory
latch and decoder circuits intended for use in CDP1800
series microprocessor systems. They can interface directly
with the multiplexed address bus of this system at maximum
clock frequency, and up to four 4K x 8-bit random-access
memories to provide a 16K-byte RAM system. With four 2K
x 8-bit RAMs, an 8K-byte RAM system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock
input to VDD, the latches are in the data-following mode
and the decoded outputs can be used in general-purpose
memory-system applications.
CLOCK
I.
VDO
MA5
17
A.
16
A9
MA4
4
MA.
15
"'0
MA2
14
MAl
13
A"
eso
.. AO
12
CsT
"
es.
CE
10
Vss
m
TOP VIEW
92C~-3"999
CDP1882
T,rm'na' A"'gnmenl
The CDP1881 and CDP1882 are intended for use with 2K or
4K-byte RAMs and are identical except that in the CDP1882
MWR and MRD are excluded.
The CDP1881 and CDP1882 are functionally identical to
the CDP1881C and the CDP1882C. They differ in that the
CDP1881 and CDP1882 have a recommended operating
voltage range of 4 to 10.5 volts and their C versions have a
recommended operating voltage range of 4 to 6.5 volts.
The CDP1881 and CDP1882 are supplied in 20-lead and
18-lead packages, respectively. Both the CDP1881 and
CDP1882 are available in hermetic, dual-in-line side-brazed
ceramic (D suffix) and plastic (E suffix) packages.
I
vOO"@
vss' ®
92CS- 35001
Fig. 1 - Functional diagram lor the CDP1881.
Fig. 2 - Functional diagram for the CDP1882.
365
RCA CMOS LSI Products
CDP1881, CDP1881C, CDP1882, CDP1882C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS terminal)
CDP1881 and CDP1882 ....................•......•.........•...••...........................•..•..•••..••......•.-0.5 to +11 V
CDP1881 C and CDP1882C ...............................•......•.....................•................•..••.•..•.. -0.5 10 +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ............................................................•........•• -0.510 VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ...................•..........................................•..•................ ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A=-40 to +60· C (PACKAGE TYPE E) ........................•..........•...........••.................•....••.••. 500 mW
For T A=+60 to +85·C (PACKAGE TYPE E) ............................................... Derate Linearly at 12 mW/·C to 200 mW
ForTA=-55 to +100·C (PACKAGE TYPE D) .........................................•.............................•.••. 500 mW
For TA=+100to 125·C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T A=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ...................•...................•...•....•.. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ................•.........................................................•..............•..•. -55 to +125·C
PACKAGE TYPE E .........................................................................................•..•.. -40 to +85·C
STORAGE-TEMPERATURE RANGE (T stg) .............................................................. , ...•...... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. . .................................................•.. +265·C
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum reliability,
operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
CDP1881, CDP1882
Min.
DC Operating Voltage Range
Input Voltage Range
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described ~o ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noiSe; any of these conditions must
366
Max.
CDP1881C, CDP1882C
Min.
UNITS
Max.
4
10.5
4
6.5
VSS
VDD
VSS
VDD
V
not cause Voo-Vss to exceed the absolute maximum
rating.
Input Signal 1
To prevent damage to the input protection circuit,
input Signals should never be greater than Vcc nor less
than Vss. Input currents must not exceed 10 mA even
when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused inpullerminals must be connected to either
Vce or Vss, whichever is appropriate.
Output Short Circuit.
Shorting of outputs to Voo, Vee, or Vss may damage
CMOS devices by exceeding the maximum device
dissipation.
1800-Serles Peripherals
Preliminary Data
VDD
NC.
GND
RRD
RBRe
RBR7
RBR6
TRC
EPE
CLSI
CLS2
SBS
P1:
CRL
RBR~
TBR8
RBR4
RBR3
RBR2
RBRI
PE
FE
OE
SFD
RRC
DQ
DR
RRJ:
TBR7
TBR6
CMOS Universal Asynchronous
Receiver/Transmitter (UART)
Features:
•
Low-power CMOS circuitry 7.5 mW typo at 3.2 MHz
(max. freq.) at VDD = 5 V
Baud rate - DC to 200K bits/sec (max.)
at VDD = 5 V
TBRS
TBR4
TBR3
TBR2
TBRI
TRO
TRE
'mil
TBRE
MR
CDP6402, CDP6402C
•
DC to 400K bits/sec (max.)
at VDD = 10 V
• 4 V to 10.5 operation
• Automatic data formatting and
status generation
• Fully programmable with externally
selectable word length (5-8 bits),
parity inhibit, even/odd parity, and
" 1.5,or 2 stop bits
• Operating-temperature range:
(CDP6402D, CD) -55 to +125·
(CDP6402E, CE) -40 to +85· C
• Replaces industry types IM6402
andHD6402
TERMINAL ASSIGNMENT
The RCA CDP6402 and CDP6402C are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART)
circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to
provide the necessary formatting and control for interfacing
between serial and parallel data channels. The receiver
T8f!~CMSB)
converts serial start, data, parity, and stop bits to parallel
data verifying proper code transmission, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start parity and stop bits.
The data word can be 5. 6. 7 or 8 bits in length. Parity may be
odd, even or inhibited. Stop bits can be 1, 1.5. or 2 (when
transmitting 5-bit code).
TBRI (lSB)
-------
TRE _ _- - - - - - ,
I
I
'TIJlIl
TRe
--t-+
I
MULIPLEXER
I
I
I
L--------------...,Ir-..TRO
I
CLSI--1--+-----~-----+r--%--~-------------------------_+_SBS
iJ>~11~~~
ClS2
EPE
CRL.--r--t------r----~L-_,-_~---------------------------------------------_t-EPI
MRI--cr---4
~-------------------------------~~+_~--RRI
j-----~-RRO
SFD-r---l..
DR'
DE
TBRE
FE
PE
RBR8 (MSB)
RBRl(lSB)
92CL-34~~3
Fig. 1 - Functional block diagram.
367
RCA CMOS LSI Products
CDP6402, CDP6402C
operating voltage range of 4 to 1.6.5-volts, and the C0P6402C
has a recommended operating voltage range of 4 to 8.5
volts. Both types are supplied in 4D-lead dual-in-line ceramic
packages (0 suffix), and 40-lead dual-in-line plastic
packages (E suffix).
The COP6402 and COP6402C can be used in a wide range
of applications including modems, printers, peripherals,
video terminals, remote data acquisition systems, and serial
data links for distributed processing systems.
The COP6402 and COP6402C are functionally identical.
They differ in that the CDP6402 has a recommended
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOD)
(Voltage referenced to VSS Terminal)
CDP6402 ...............................................•..••.•......•......•..•..•......••.••.• -o.5to+l1 V
CDP6402C ............................................•....................•.•.•.........••.•...• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ................ , ........•........•.....•.•............. -0.5 to VOO +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ......•...........•...................•..•....•.........••..... , . ± 100 /lA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60· C (PACKAGETYPE E ...................•.............................•........•..• 500 mW
For TA = +60 to +85 0 C (PACKAGE TYPE E) ............................... Derate Lineary at 12 mW/o C to 200 mW
For TA = -55 to 100 0 C (PACKAGE TYPE D) ............................................................. 500 mW
For TA = + 100 to +125°C (PACKAGE TYPE D) ............................ Derate Lineary at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ..•..............••...........•.. 100 mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPE D .............................................................................. -55 to +125" C
PACKAGE TYPE E ..............................•.................•............•.•.•............•. -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) .......................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................... +265°C
OPERATING CONDITIONS at TA = Full Package-Temperature Range. For maximum reliability. operallng condItIon•
• hould be .elected.o that operatIon I. alway. wIthIn the followIng rang..:
LIMITS
CHARACTERISTIC
CDP8402
DC Operating Voltage Ranoe
Input Voltage Range
CDP8402C
Min.
Max.
4
6.5
vOO
VSS
Max.
10.5
VOO
Min.
4
VSS
UNITS
V
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VDD ±10%, Except a. noted
CONDITIONS
r~
CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
output vOltage
High Level
Input Low
Voltage
Input Hlgn
Voltaoe
Input Leakage
Current
3-State Output Leakage
Current
100
U.4
Inl
IOH
VOL*
VOHt
V,l
VIH
111\1
Operating Current,
lOUT
1001*
Input Capacitance
Output Capacitance
C'N
COUT
0.5
4.6
9.5
-
0.5,4.5
0.5,9.5
U.O, 4.0
0.5 9.5
Any
Input
0,5
0, 10
-
~t~
0,5
0, 10
0,5
o 10
0,5
0, 10
0,5
0, 10
0,5
0, 10
~~r
0,5
o 10
0,5
0, 10
5
10
5
10
5
10
5
10
5
10
5
'10
5
10
5
10
5
10
0~'100
5
10
-
-
-
LIMITS
r.DP8402
CDPM02C
Typ ••
Typ ••
Max.
Min.
Max.
Min.
0.02
0.01
50
20U
1
200
1.2
i 2.4
2.4
1.2
2.5
5
-1.1
-0.55
-1.1
-0.55
-1.3
-2.6
0.1
0.1
0
0
0.1
0
:)
l)
4.9
4.9
9.9
10
-:'
U.IS
P:~
p. 2VOO
VOO-2.0
~00-2.C
7
±10-"
±1
±1
±lo-4
±2
±1
±1
±lo-"
±lO-"
±lo-4
±10
1.0
1.5
10
7.5
5
7.5
5
10
15
15
10
-
-
-
--
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
/lA
mA
-
-
V
/lA
mA
pF
.Typical values are for TA=25°C and nominal VOO.
:tIOL=IOH=l /lA.
#Operating current is measured at 200 I kHz or VOO = 5 V and 400'.kHz for VOO = 10 V, with open outputs (worSt-caS.
frequencies for COP1802A system operating at maximum speed of 3.2 MHz).
368
1800-Ser/es Peripherals
CDP6402, CDP6402C
Receiver Operation
DESCRIPTION OF OPERATION
Initialization and Controls
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets
the serial output (TRO) High. Timing is generated from the
clock inputs RRC and TRC at a frequency equal to 16times
the serial data bit rate. The RRC and TRC inputs may be
driven by a common clock, or may be driven independently
by two different clocks. The CONTROL REGISTER LOAD
(CRL) input is strobed to load control bits for PARITY
INHIBIT (PI), EVEN PARITY ENABLE (EPE), STOP BIT
SELECTS (SBS), and CHARACTER LENGTH SELECTS
(CLS1 and CLS2). These inputs may be hand wired to VSS
or VDD with CRL to VDD. When the initialization is
completed, the UART is ready for receiver and/ortransmitter
operations.
Data is received in serial form at the RRI input. When no
data is being received, RRI input must remain high. The
data is clocked through the RRC. The clock rate is 16 times
the data rate. Receiver timing is shown in Fig. 4.
BEGINNING OF FIRST STOP BIT
I
RRI
DATA
~~
FE
The transmitter section accepts parallel data, formats it,
and transmits it in serial form (Fig. 2) on the TRO terminal.
5-8 DATA BITS
1\
ILSB I
IMSBI
*'LLLL
*IF ENABLED
PARITY
92.C$-
345~4
Fig. 2 - Serial data format.
Transmittertiming is shown in Fig. 3. (A) Data is loaded into
the transmitter buffer register from the inputs TBR1 through
TBRS by a logic low on the"fBR[ input. Valid data must be
present at least tOT prior to, and ITO following, the rising
edge of "I'lrn"C. If words less than 8 bits are used, only the
least significant bits are used. The character is right
justified into the least significant bit, TBR1. (B) The rising
edge o('i'sRL clears TBRE. Zero to 1 clock cyles later data
is transferred to the transmitter register and TRE is cleared
and transmission starts. TBREmpty is reset to a logic high.
Output data is clocked by TRC. The clock rate is 16 times
the data rate. (C) A second pulse on f'BR[ loads data into
the transmitter buffer register. Data transfer to the
transmitter register is delayed until transmission of the
current character is complete. (D) Data is automatically
transferred to the transmitter register and transmission of
that character begins.
-
~1/2CLOC K
CYCLE
92CS-34559
Fig. 4 - Receiver timing waveforms.
1,I-I/ZOR2STOPBITS
~
1/2 CLOCK
CYCLES
1
DR
A
'-1-----....11------.1
f-- 7
I I
RBRI-B ,OE,PE
Transmitter Operation
START BIT",\
~
(A) A low level on 5FiR clears the DR line. (B) During the
first stop bit data is transferred from the receiver register to
the RBRegister. If the word is less than 8 bits. the unused
most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
logic high on OE indicates overruns. An overrun occurs
when DR has not been cleared before the present character
was transferred to the RBA. A logic high on PE indicates a
parity error. (C) 1/2 clock cycle later DR is set to a logic
high and FE is evaluated. A logic high on FE indicates an
invalid stop bit was received.
Start Bit Detection
The receiver uses a 16X clock for timing (Fig. 5). The start
bit could have occurred as much as one clock cycle before it
was detected. as indicated by the shaded portion. The
center of the start bit is defined as clock count 71/2. If the
receiver clock is a symmetrical square wave. the center of
the start bit will be located within ±1 /2 clock cycle. ±1 /32 bit
or ±3.125%. The receiver begins searching for the nextstart
bit at 9 clocks into the first stop bit.
COUNT 71/2
DEFINED CENTER
OF START BIT
CLOCK
::::~ I ~
92C$- 34558
DATA
Fig. 5 - Start bit timing waveforms.
A
B
C
D
~~~~F
STDP BIT
92C9-34557
Fig. 3 - Transmitter timing waveforms.
369
I
.ACA CMOS LSI Products
CDP6402, CDP6402C
Table I - Control Word Function
.WOlln
CLS2
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
CLS1
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
DI
~D~
!!lBS
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
X
X
L
L
H
H
X
X
L
L
H
H
X
X
L
L
H
H
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
ftAT.BIT8
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
DAltITY.IT
STOP.IT'S'
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
X = Don't Care
Table II - Function Pin Definition
2
3
4
SYMBOL
VDD
N/C
GND
RRD
5
RBR8
6
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
PIN
1
7
8
9
10
11
12
13
14
370
FE
DESCRIPTION
Positive Power Supply
No Connection
Ground (VSS)
A high level on RECEIVER REGISTER
DISABLE forces the receiver holding
register ouputs RBR1-RBR8 to a high
impedance state.
The contents of the RECEIVER BUFFER
REGISTER appear on these three-state
outputs. Word formats less than 8
r=:~ ~;:h:::;fi'd RBRl
to
A high level on PARITY ERROR
indicates that the received parity does
not match parity programmed by control
bits. The output is active until parity
matches on a succeeding character.
When parity is inhibited, this output
is low.
A high level on FRAMING ERROR
indicates the 'first stop bit was invalid.
FE will stay active until the next valid
character's stop bit is received.
PIN
SYMBOL
15
OE
16
SFD
17
RRC
18
DDR
19
DR
20
RRI
21
MR
22
TBRE
DESCRIPTION
A high level on OVERRUN ERROR
indicates the data received flag was not
cleared before the last character was
transferred to the receiver buf.fer
register. The Error is reset at the next
character's stop bit if ORR has been
performed (i.e., ORR; active low).
A high level on STATUS FLAGS
DISABLE forces the outputs PE, FE, OE,
DR, TBRE to a high impedance state.
The RECEIVER REGISTER CLOCK is
16X . the receiver data rate.
A low level on DATA RECEIVED RESET.
clears the data received output (DR), to ,
a low level.
A high level on DATA RECEIVED
indicates a character has been received
and transferred to the receiver buffer
register.
Serial data on RECEIVER REGISTER
INPUT is clocked into the receiver
register.
A high level on MASTER RESET (MR)
clears PE, FE, OE, DR, TRE and sets
TBRE, TRO high. Less than 1'8 clocks
after MR goes low, TRE returns high.
MR does not clear the receiver buffer
register, and is required after power-up.
A high level on TRANSMITTER BUFFER
REGISTER EMPTY indicates the
transmitter buffer register has
transferred its data to the transmitter
register and is ready for new data.
1800-5erles Peripherals
CDP6402, CDP6402C
Table II • Function Pin Definition (Confd)
PIN
23
24
25
26
27
28
29
30
31
32
33
SYMBOL
DESCRIPTION
TBRL A low htvel on TRANSMITTER BUFFER
REGISTER LOAD transfers data from
inputs TBR1-TBR8 into the transmitter
buffer register. A low to high transition
on TBRL requests data transfer to the
transmitter register. If the transmitter
register is busy, transfer is automatically
delayed so that the two characters are
transmitted end to end.
TRE
A high level on TRANSMITTER
REGISTER EMPTY indicates completed
transmission of a character including
stop bits.
TRO
Character data, start data and stop bits
appear serially at the TRANSMITTER
REGISTER OUTPUT.
TBR1
Character data is loaded into the
TRANSMITTER BUFFER REGISTER via
inputs TBR1-TBR8. For character
formats less than 8-bits, the TBR8, 7,
and 6 Inputs are ignored corresponding
to the programmed word length.
TBR2
TBR3
TBR4
TBR5
See Pin 26 - TBR1
TBR6
TBR7
TBR8
PIN
34
35
36
37
38
39
40
SYMBOL
DESCRIPTlOti
CRL
A high level on CONTROL REGISTER
LOAD loads the control register.
PI'
A high level on PARITY INHIBIT inhibits
parity generation, parity checking and
forces PE output low.
SBS'
A high level on STOP BIT SELECT
selects 1.5 stop bits for a 5 character
format and 2 stop bits for other lengths.
CLS2' These inputs program the CHARACTER
LENGTH SELECTED. (CLS1 low CLS2
low 5-bits) (CLS1 high CLS210w 6-bits)
(CLS1Iow CLS2 high 7-bits) (CLS1 high
CLS2 high 8-bits).
CLS1' See Pin 37 - CLS2
EPE'
When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parity. A low level selects odd
parity.
TRC
The TRANSMITTER REGISTER
CLOCK is 16X the transmit data rate.
'See Table I (Control Word Function)
}
I
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525. "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Opel'lltlng
Operating Voltage
During operation near the maximum supply voltage
limit. care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple. or ground noise; any of these conditions must
not cause VDD - VSS to excead the absolute maximum
rating.
Input Slgna's
To prevent damage to the input protection circuit, input
signals should never be greater than VCC nor less than
VSS. Input currents must not exceed 100 p.A even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
VCC or VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to VDD. VCC or VSS may damage
CMOS devices by exceeding the maximum device
dissipation.
371
RCA CMOS LSI Products
CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA '" ....0 to +85°C, VDD ± 51fo,
VIH
=0.7 VDD, VIL "
t"
tf '" 20 nl,
0.3 VDD, CL " 100 p'
LIMITS
CDP6402C
CDP8402
CHARACTERISTIC
VDD
(V)
Typ.·1
Ma•. A
Typ.·1
Ma•• A
50
150
20
50
UNITS
SYltem nmlng (See Fig 8)
Minimum Pulse Width:
CRl
tCRl
5
10
50
40
150
100
Minimum Setup Time
Control Word to CRl
tcwc
5
10
20
0
50
40
Minimum Hold Time
Control Word after CRl
5
10
40
20
60
30
40
60
tccw
200
100
300
150
200
300
tSFDH
5
10
5
10
75
40
120
60
75
120
Propagation Delay Time
SFD High to SOD
-
'-
-
-
-
-
-
-
SFD low to SOD
tSFDl
RRD High to Recej.)ler Register
High Impedance
5
10
80
40
150
70
80
150
tRRDH
RRD low to Receiver Register
Active
5
10
80
40
150
70
80
150
tRRDl
-
-
-
-
-Typical values for TA = 25° C and nominal VDD~
AMaximum limits of minimum characteristics are the values above which all devices function.
CONTROL INPUT WORD TIMING
~~JTROlWORD----~¥r--------=CO~N~TR~O~L~W~O~RD~8Y~T~E------------~~~________
i....- - - - - - - - - - t c w c - - - -.....I,.-Iccw----l
CRl
,
----~-~(I.
-.l.--------
\'1
t C R l - - - -....
STATUS OUTPUT TIMING
STATUS
OUTPUTS
------------.X,.--------:------------..,---)f.~--I
--t ISFDli-
-..L-tSFDH
I
,
I
I
--1/
SFD _ _ _ _ _ _ _
,
•
,
1..._ _ _ __
RECEIVER REGISTER DISCONNECT TIMING
RBUSo----------~r---------------!----------~r-----
X
R BUS 7
~'-_______
I
,-
--1tRRDHl-RRD _ _ _ _....II
I-tRRDl...l
•
Li_ _ _ _ _ __
92CM-3187$RI
Fig. 6 - System timing waveforms.
372
ns
1800-Series Peripherals
CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85° C, VDD
VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF
± 5%, tr , tf = 20 ns,
LIMITS
CDP6402
CHARACTERISTIC
Transmitter Tlmln 9 (Se, FIg7)
Minimum Clock Period (TRC)
tcc
Minimum Pulse Width:
Clock Low Level
tCL
CDP6402C
I
~~p
Tn.-
5
10
250
125
310
155
250
310
5
10
100
75
125
100
100
125
I
Max. A
I
Typ.-
1
Max. A
-
-
-
-
Clock High Level
tCH
5
10
100
75
125
100
100
-
125
'i'BRL
tTHTH
5
10
60
40
150
100
60
150
5
10
175
90
275
150
175
275
5
10
20
0
50
40
20
50
Mi!l!!!!..!!.m Setup Time:
TBRL to Clock
Data to T8R['
JI
r
tTHC
tOT
UNITS
-
-
-
-
-
-
Minimum Hold Time:
Data after f'Birr ] I
5
10
40
20
60
30
40
60
tTO
Propagation Delay Time:
Clock to Data Start Bit
5
10
300
150
450
225
300
-
450
tco
-
ns
-
-
Clock to TBRE
tCT
5
10
200
100
300
150
200
300
TeAt to TBRE
tTTHR
5
10
200
100
300
150
200
-
300
Clock to TRE
tTTS
5
10
200
100
300
150
200
300
-
I
-
-
-
-Typical values for TA = 25°C and nominal VOO.
AMaximum limits of minimum characteristics are the values above which all devices function.
* TRANSMITTER
BUFFER
REGISTER LOADED
TRC
** TRANSMITTER
SHIFT
REG ISTER LOADED
I
I I I I
II-l--II
I
I
I
TBRE
Fig. 7 - Transmitter timing waveforms.
373
1800-Serles Peripherals
RCA CMOS LSI Products
CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS It T A = -40 to +85 0 C, VDD
± 5%, tr, tf = 20 nl,
VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF
LlIIITR
CDP8402
CHARACTERISTIC
~~p
CDP8402C
TVD.·
M.lr.~
TvD.·
II... ~
5
1n
5
10
250
~!~
250
310
100
75
125
100
100
125
1~
~~~
~~
100
125
5
10
5
10
~'!?
~~
50
75
100
50
150
75
100
150
tDDA
5
10
150
75
225
125
150
225
tCDV
5
10
225
110
325
17!i
225
325
tCOA
5
10
5
10
5
10
5
10
225
110
210
100
240
120
200
100
325
175
300
150
375
175
300
150
225
325
210
300
240
375
200
300
UNITS
"&cliver Timing (5ee Fig. 8)
Minimum Clock Period (RRC)
tcc
Minimum Pulse Width:
Clock Low Level
Clock High Level
tCL
tCH
DATA RECEIVED RESET
too
I MinimUm setup Time:
Data Start Bit to Clock
Ime:
DATA RECEIVED RESET to
Data Received
tnr.
I propagation ue a~
Clock to Data Valid
Clock to DR
Clock to Overrun Error
tCOE
Clock to Parity Error
tCPE
Clock to Framing Error
tCFE
-Typical values for TA
1~o;
-
-
-
-
-
-
=25° C and nominal VDD.
~Maximum limits of minimum characteristics are the values above which all devices function.
j,.t
ICC
CLOCK71/2
SAMPLE
ICH H-t-ICL
\.
CLOCK 71/2 LOAD
HOLDING REGISTER
RRC~·
-J j.a-IOC*
RRI
START BIT
PARITY
R BUSO-------------------------------------------------4-~~~
R BUS 7
OR--------------~--------------------------------~~-----
--j ~loOA
ORR----------~~----------~----------------------4_~-----
I-- loo----l
OE**------------------------~------------------------¥-----PE--------------------------------------------------+-~---
FE----______________________________________________
*
IF A START BIT OCCURS AT A TIM! LIBI THAN IDC BEFORE A HIGH-TO.LOW TRANSITION
OF THt: CLOCK. THE START BIT MAY NOT 8E RECOGNIZED UNTIL THE NEXT HIGH-TO·
LOW TRANSITION OFTHECLOCK. THI! STAR'SIT IIAY BE COMPLETELY ASYNCHRONOUS
WITH THE CLOCK.
**
IF A PENDING DA HAS NOT BEEN CLEARED 8V A READ OF THE RECEIVER HOLDING
REGISTER BY THE TIME A NEW WORD 18 LOADED INTO THE RECEIVER HOLDING
REGISTER, THE oe SIGNAL WILL COME TRUE.
Fig. 8 - Recflivflr timing wavflforma.
374
~_L
92CM-54eee
___
ns
General-Purpose Memories
Technical Data
375
RCA CMOS LSI Products
CD4036A, CD4039A
COS/MOS 4-Word by a-Bit
Random-Access NORO
Memory
Binary Addressing CD4036AD, CD4036AK
Direct Word-Line
CD4039AD, CD4039AK
Addressing
Special Features:
• COs/MOS logic compatibility at a/l
Input and output terminals
• Memory bit expansion
• Memory word expansion via Wire-OR
capability at the 8 INPUT-BIT and 8
OUTPUT-BIT lines
RCA type CD4036A is a single monolithic
integrated circuit containing a 4-word x
a-bit Random Access NDRO Memory_ Inputs include a INPUT-BIT lines, CHIP INHIBIT, WRITE, READ INHIBIT, MEMORY
BYPASS, and 2 ADDRESS inputs_ a
OUTPUT-BIT lines are provided_
All input and output lines utilize standard
COSIMOS inverter configurations and
hence can be directly interfaced with
COs/MOS logic devices.
.
CHIP INHIBIT allows memory word expansion by WIRE-ORing of multiple
CD4036A packages at either the a-bit input andlor output lines (see Fig. 19). With
CHIP INHIBIT "high", both READ and
WRITE operations are inhibited on the
CD4036A. With CHIP INHIBIT "low", information can be written into andlor read
continuously from one of the four words
selected by the binary code on the two address Hnes. With CHIP INHIBIT "low", a
"high" WRITE signal and a "low" READ
INHIBIT signal activate WRITE and READ
operations, respectjvely, at the addressed
word location (see Fig. 4).
The MEMORY BYPASS signal, when
"high", allows shunting of information
from the a INPUT-BIT lines directly to the
a OUTPUT-BIT lines without disturbing
the state of the 4 words. During the
bypass operation input information may
also be written into a selected word location, provided the CHIP INHIBIT Is "low"
and the WRITE Is "high". The READ
operation is deactivated during the
BYPASS operation because information
is fed directly from the a INPUT-BIT lines
to the a OUTPUT-BIT lines.
376
• Memory bypass capability for all bits
• Buffering on all outputs
• CD4036A-on-chip binary address
decoding, separate READ INHIBIT and
WRITE controls
• CD4039A-Direct word-line addressing
• Access Time-200 ns (typ.)
atVDD=10V
.
Applications:
Digital equipment where low power dissipation and/or high noise Immunity are
primary design requirements.
• Channel Preset Memory in digital
frequency-synthesizer circuits
• General-purpose and scratchpad
memory in COS/MOS and other lowpower systems.
RCA type CD4039A is identical to the
CD4036A with the exception that individual address-line inputs have been
provided for each memory word in place
of the binary ADDRESS, CHIP INHIBIT,
and READ INHIBIT inputs. When WlreORing multiple CD4039A packages for
memory word expansion, an individual
CD4039A is selected by addressing one of
its word locations. The READ operation is
activated whenever a word location is addressed (via a "high" signal':"'see Fig. 5).
These devices will be supplied in two different 24-lead ceramic packages; the
CD4036AK and CD4039AK in the flatpack, and the CD4036AD and CD4039AD
in the dual-in-line package.
General-Purposes Memories
CD4036A, CD4039A
MAXIMUM RATINGS,
Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE .......................................... -6510 + 150·C
OPERATING·TEMPERATURE RANGE ........................................ -5510 + 125·C
DC SUPPLY VOLTAGE RANGE (VDD-VSS) .................................... -0.510 +15V
DEVICE DISSIPATION (Per Package) ................................................ 200 mW
ALL INPUTS .............................................................. VSS" VI" VDD
RECOMMENDED DC SUPPLY VOLTAGE (VDD- VSS) ................................. 310 15V
LEAD TEMPERATURE (During Soldering)
AI distance 1/16 ± 1/32 inch (1.59±0.79mm) from case for 10 seconds max ............... 265·C
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
Quiescent Device
Current,IL
Quiescent Device
Dissipation/Pack·
age, Po
Output Voltage:
Low·Level, VOL
TEST
CONDITIONS
Vo
VDD
Volts Volts
5
10
5
10
5
10
5
10
High·Levei, VOH
Threshold Voltage:
N·Channel, VTHN
10= 2O IJ.A
P·Channel, VTHP
10= -20/1A
Noise Immunity,
5
VNL
(All inputs except
10
bit inputs when
in memory by·
5
10
pass mode.) VNH
Output Drive Current:
Nor0.5
5
N-Channel, ION
mal
0.5
10
Read 4.5
5
P-Channel, lOP
Modes 9.5
10
Output Drive Cur· Memrent:
ory
0.5
5
ByN-Channel, ION
0.5
10
pass
4.5
5
P-Channel, lOP
Mode 9.5
10
+
Input Current, II
-
LIMITS
CD4036AD, CD4036AK
UNITS
CD4039AD CD4039AK
2SoC
-SsoC
12S·C
Min. Max. Min. Max. Min. Max.
-
5
10
25
100
-
-
5
10
25
100
-
0.01
0.01
-
0.01
0.01
4.99
9.99
-
1.7 typo
-1.7typ.
4.99
9.99
-
1.5 typo
-1.5typ.
-
4.95
9.95
300
600
1500
6000
O.OS
0.05
-
1.3 typo
-1.3 typo
1.5
3
-
1.5
3
-
1.4
2.9
-
1.4
2.9
-
1.5
3
-
1.5
3
-
0.12
0.30
-0.12
-0.30
-
-
-
0.10
0.25
-0.10
-0.25
--
0.07
0.17
-0.07
-0.17
-
-
0.04
0.09
-0.04
-0.09
-
0.03
0.075
-0.03
-0.075
-
0.02
0.05
-0.02
-0.05
-
-
-
-
-
10 typo
-
-
IJ.A
IJ.W
V
•
V
V
V
V
mA
mA
mA
mA
pA
+ Bit inputs driven from low·impedance driver.
377
RCA CMOS LSI Products
CD4036A, CD4039A
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25·C and CL = 15 pF
Typical Temperature Coefficient for all values of VDD =O.3%I·C
CHARACTERISTIC
TEST CONDITIONS
VDO
Volts
Aead Delay Time, trd:
(Access time)
Aead Inhibit (AI)
Chip Inhibit (CI)
Memory Bypass (MB)
Output tied
through 100 kQ
to VSS for data
output "high"
and to VDD for
data output "low"
Address 1 (ADD)
Write Set-up Time 2, tws
Write Aemoval Time 3, tWA
Write Pulse Duration, tw
Data Set-up Time 5, tDS
Data Overlap Time 6, too
Output Transition
tTHL
Time,
tTLH
Input Capacitance, CI
Any Input
..
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
C04036AD, CD4036AK
C04039AO, CD4039AK UNITS
Min.
Typ.
Max.
-
375
150
500
200
375
150
500
200
125
50
0
0
75
30
0
0
50
20
200
100
5
750
ns
300 Note 4
1000
ns
400 Note 4
75C
ns
300
1000
ns
400
-
-
250
100
0
0
150
60
-
-
100·
40·
-
-
O·
O'
-
i's
ns
ns
ns
ns
400
200
ns
-
pF
1. For C04036A only, remove 100·kQ test condItIon and write all 1's In word one, and all O's In word
two, or vice versa.
2. Delay from change of ADDRESS or CHIP-INHIBIT signals to application of WRITE pulse.
3. Delay from removal of WRITE pulse to change of ADDRESS or CHIP·INHIBIT signals.
4. Values for C04036AD and C04036AK only.
5. The time that DATA signal must be present before the WRITE pulse removal.
• Max. indicates satisfactory operation if tos equals or exceeds this value.
6. The time that DATA signal must remain present after the WHITE pulse removal.
• Min. indicates satisfactory operation if too equals or exceeds this value.
378
HANDLIN.G CONSIDERATIONS
OPERATING CONSIDERATIONS
Although protection against electr.ostatic
effects is provided by built-in circuitry, the
following handling precautions should be
taken:
1. Soldering iron tips and test equipment
should be grounded.
2. Devices should not be inserted in non·
conductive containers such as
conventional plastic snow or trays.
1. Low impedance pulse generators or
power supplies connected to the inputs of these devices must be disconnected before the dc power supply is
turned off.
2. All unused input leads should be connected to either VSS or VDD, whichever is appropriate for the logic circuit
involved.
General-Purposes Memories
CD4036A, CD4039A
\1-------8;
BIT OUTPUTS
92CS-19935
92C5-19934
Fig. 1-CD4036A-logic block diagram.
A[
24
23
22
2[
WRITE
4
20
5
6 CD4036A 19
(TOP) [8
7
ViEW
[7
8
[6
9
[5
[0
[[
[4
[3
12
""t
[N
5
6
7
8
MEMORY
BYPASS
GND
Fig. 2-CD4039A-logic block diagram.
WORD [
VDD
Ao
WR[TE
CHIP [NH[B[T
READ [NH[BIT
~l
~ ~BITS
5
""t
IN
5
6
7
8
MEMORY
BYPASS
GND
OUT
D
24
23
22
21
20
5
6 CD4039A 19
[
2
3
4
7
8
9
[0
(TOP)
VIEW
[[
18
17
[6
15
[4
[2
13
92C$-19937
VDD
WORD 3
WORD 4
WORD 2
}"
5
6
OUT
7
.• 8
•
92CS -19936
Fig. 3a)-CD4036AD and CD4036AK terminal
assignments.
b)-CD4039AD and CD4039AK terminal
assignments.
,
A,
0------------,
WORD I
0---,:-.-,~
'M)RD2
WRITE
CHIP
0===::::'
INHI8ITO _ _ _ _
READ
INHIBIT
WOfl03
~=~::;--I-----
WRITE I
KIilORY
o-----=:crl::=.:.t--t---'I
DATA
'"
DATA
OOT
-J,t '"r1ljJI
,
0- -
II
1\
'--
o~~~1
,
eVF'A$S
...,.".'
o
-
-
-
-
-
r
(RI)
(ADO)
(MBI
Fig. 4-CD4036A timing diagram.
MEMORY
BYPASS
DATA
----1-'w -L
I
a
OA1A
, r
OUT
0----
'"
I
o
'"
(ADO)
I-~~
'"
Ir
,I
,- __
(MB)
..J
Fig. 5-CD4039A timing diagram.
379
RCA CMOS LSI Products
CD4036A, CD4039A
Fig. 7- Typical p-channel drain
characteristics .
Fig. 6- Typical n-channel drain
characteristics.
.
i= 750
~
~
o 500
.
o
Il:;
250
10
LOAD CAPACITANCE (Cl)-pF
Fig. 9- Typical transition time vs. CL.
Fig. 8-Typical read delay time vs. CL.
IDa
I
LOAD CAPACITANCE (Cll: 15pF
- - DATA FREQUENCY AT BIT INPUTS
~
(CONSTANr ADDRESS)
----ADDRESS "REQUENCY
(CONSTANT DATAl
AMBIENT TEMPERATURE (TA)-25°C
rREQUENCYm~KHz
Fig. 10- Typical power dissipation vs.
frequency.
380
General-Purposes Memories
CD4036A, CD4039A
TEST CIRCUITS
'OV
g "20
•
,
!°
4
to
,.
,.
"
II
17
'1
T
o
,."
"
FIg. 12-QulesCflnt current (CD4039A).
Fig. 11-Quiescent current (CD4036A).
,OV
c
o
.:
4
7
g
C
0
• •,
10
0
·
" •
12
CONNECTIONS TO ALL TERMINALS IElI:CEPT 12 • 241
ARE MAOE THROUGH 41 KO RESISTOItS
Fig. 13-Noise immunity.
lal n-CHANNEL
Voo
I
IS
•
FIg. 15-BI.sed life.
Fig. 14-0peratlng life.
Voo
(5V OR 10 Vl
I.
17
I•
.v
i5VORIOV)
{bl p-CHANNEL
Fig. 16-Drive current.
FIg. 17- Threshold voltage.
381
RCA CMOS LSI Products
CD4036A, CD4039A
Switch ••
sho ... "
GRAYHILL
2-pole ,wit,*,"
are
5OCY23133.CEfli
TRALAII 1'''160,
Or equ ... lent can
.lIobeuNd.
Switch" (leI! 10
right! read 5':1·2
~!'" :~"'.,~~~t:~
thes40 ,witch po
,iuon. (from the
Table belowl "
H·O",N~13
+ ThlCDC036ACANBE UTILIZED IN A SIMILAR fASHION
SEE APP. NOTE ICAN-&498 - "DESIGN OF FIXED AND PROGRAMMABLE COUNTERS USING THE RCA CD4018ACOSIMOS PRESETTABLE OIVIDE-BV-'N'COUNTER" -9.ND
ICAN-6718, "lOW POWER DIGITAL FREQUENCY SYNTHESIZERS UTILIZING COS/MOS Ie's"
Fig. 18- Three·decade programmable.;. N counter with 4·channel preset memory settings for
frequency synthesizers.
The divide-by-N counter system shown in
Fig. 18 is programmable from 2 to 999.
Four counter-preset words, selected by
means of the rotary switches, can be
stored in the CD4039A devices and can be
read into each CD4018A by simply addressing the proper word. Note that the
CD4029A (see Bulletin File No. 503)
Presettable Up/Down Counter with BCD
decade counting can also be used to perform the basic counting function.
,--________________
MEMO RY BYPASS
READ INMIBIT
E
~"~'~\"~'"~'~S
______________,
I
I
,
~
.
,
,
r+-t-+; I
,
s
s
..
,,
~
,
~l
,
,,
.,
S
,
,,
"
C04036" •
"
C04036A·
2O
2O
2O
2O
"
"
"
""
"
"
"
"
"
"
"
""
""
""
"
""
"
"
6
6
C04036A ..
TT+
'0
""
+
"
"
"
-T-T-T-
TIT
I
,
'0
C04036A ..
m
~_345678
01- THE C04039A
CAN BE UTILIZED IN A SIMILAR FASHION
i
BIT OUTPUTS
Fig. 19-General·purpose memory storage-8 words x 16 bits (RAM or ROM).
382
General-Purposes Memories
CD4061A
COS/MOS
256-Word by 1-Bit
Static Random-Access
Memory
Features:
•
•
•
•
•
•
•
•
•
•
•
Low standby power: 10 nW/bit (typ-l @ VOO = 10 V
Access time: 380 ns (max-l @ VOO = 10 V
Single 3-to-15 V power supply
COS/MOS input/output logic compatibility
TTL output drive capability
Three-state data outputs for bus-oriented systems
1101-type pin designations*
Separate data output and data input lines
Noise immunity: 45% of VOO (typ-l
Fully decoded addressing
Single write/read control line
16
•
AD
15
A,
READ/WRITE
,4
-DATA OUT
A2
vss*
4
*
5
vDD
C04061A
13
12
A3
A.
NC
CHIP
SELECT
DATA OUT
DATA IN
A7
10
A6
A5
92CS~21~26RI
The RCA-CD4061A is a single monolithic
integrated circuit containing a 256-word by
I-bit fully static, random-access, NDRO
memory. The memory is fully decoded and
requires 8 address input lines (AO-A7) to
select one of 256 storage locations. Additional connections are provided for a READ/
WRITE command CHIP SELECT DATA IN,
and DATA OUT and DATA OUT lines.
signal may be used to permit the selection
of individual packages.
Output-voltage levels appear on the outputs
only when the CHIP SELECT and READ/
WRITE signals are both low. Separate data
inputs and outputs are provided; they may
be tied together, or, to eliminate interaction
between READ and WR ITE functions, may
be used separately. The circuit arrangement
permits the outputs from many arrays to be
tied to a common bus.
To perform READ and WR ITE operations
the CHIP-SELECT signal must be low. When
the CHIP-SELECT signal is high, read and
write operations are inhibited and the output is a high impedance. To change addresses,
the CHIP-SELECT signal must be returned
to a high level, regardless of the logic level
of the READ/WR ITE input. In a mUltiple
package application, the CHIP-SELECT
The CD4061A is available in a hermetically
sealed 16-lead dual-in-line ceramic package
(CD40r>lAD) or in chip form (CD4061AH).
MAXIMUM RATINGS,
DEVICE DISSIPATION (PER PACKAGE)
Absolute-Maximum Values:
. . . . . . . . . . . . . . . . . . . . . . 200mW
STORAGE-TEMPERATURE RANGE
..................
-65to+150'C
OPERATING-TEMPERATURE RANGE
. . . . . . . . . . . . . . . . ..
•
All input and output lines are buffered. The
CD4061 A output buffers are capable of
direct interfacing with TTL devices.
-55 to +125'C
DC SUPPLY-VOLTAGE RANGE:
VDD" . . . . . . . . . . . . . . . -0.5 to +15 V
ALL INPUTS
. . • . . . . . . . . VSSE;;VIE;;VDD
RECOMMENDED DC SUPPLY VOLTAGE
(VDD-VSS)
.............
3 to 15 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm)
from case for lOs max. . . . . . . ..
+265' C
*The pin designations are compatible with other static 256-bit memories and are, therefore, not
compatible with standard COS/MOS CD4000A-series devices; i.e., V DD is pin 5 and VSS is pin 4.
383
RCA CMOS LSI Products
CD4061A
-,
AO
CE
l
AI
I
I
2
A2
'}-I>-------j
VOO
o-+-'Wlr-...-GATE
Vss
I
A3
6
I
VDD
------0
VSS--(£J
Fig. 1 - CD4061A logic diagram.
CD4061A OPERATIONAL MODES
OPERATION
Write "0"
Write "1"
Read
*Read Modify
Write
Address Change
ADDRESS
LINES
---
CHIPSELECT
READ/
WRITE
DATA
IN
Stable
Stable
Stable
Stable
0
0
0
0
1
1
0
0/1
0
1
X
X
Changing
1
X
X
DATA OUTPUTS
High-I mpedance
High-Impedance
Valid 1 or 0
Valid 1 or O/HighImpedance
High-Impedance
X = Don't Care
*For a READ MODIFY WR ITE operation, CHIP SELECT may be held to logic 0 for
the whole operation.
384
General-Purposes Memories
CD4061A
STATIC ELECTRICAL CHARACTERISTICS
(AI/inputs ... V~V~VDD)
(Recommended DC Supply Voltage (VDD-VSS)' .. 3 to 15 V)
TEST
CHARAC·
TERISTIC
LIMITS
~ONDITIONS
Vo
(vI
Quiescent De·
vice Current,
-55°C
Voo
Output Volt·
age
Low·Level,
UNIT
125°C
(VI
MIN.
MAX.
MIN.
TYP.
MAX.
MIN.
5
-
5
-
0.12
5
10
-
10
-
0.25
10
-
300
5
-
-
25
-
-
-
0.6
10
2.5
100
-
3000
5
-
0.01
10
-
om
'L
See Fig. 14
Quiescent De·
vice Dissipation/Package,
PD
25°C
-
0
0.01
0
om
MAX.
150
Il A
750
-
IlW
0.05
0.05
VOL
High·Level,
VOH
Noise Immuni·
ty, (Allinputsl
See Fig. 17
VNL
VNH
0.8
5
4.99
-
4.99
5
-
4.95
10
9.99
-
9.99
10
-
9.95
1.5
-
5
1
10
4.2
5
1.4
10
2.9
9
3
1.5
2.25
3
4.5
1.5
2.25
3
4.5
-
-
2.9
-
1.5
-
3
-
1.1
-
:2.4
-
-0.65
-
1.4
V
V
Output Drive
Current:
(Data Out,
I
~Out)
1.6
2.5
4.3
-
3.5
5
5
-1.1
-
-0.9
-1.8
4.6
5
-0.5
10
-1.1
-
-0.4
9.5
-0.9
N·Channel
(Sink), IDN
See Figs. 3,
4,12
0.4
0.5
10
P·Channel
(Source), IDP
See Figs. 5,
2.5
6,13
Output Off
Resistance
(High·lmped·
anee State),
Ro (Offl
4.5
2
5
10
10
10
10
10
-
-0.8
-
-0.3
-1.8
-
-0.65
-
-
-
10
-
10
rnA
-
M!1
385
RCA CMOS LSI Products
CD4061A
DYNAMIC ElECTRICAL CHARACTERISTICS
atTA--25°C VSS=OV CL=50pF andt"t,=20ns
TEST
CONDITIONS
LIMITS
UNITS
CHARACTERISTIC
r
VDD
(v)
MIN.*
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
15
1200
550
40
0
700
350
460
200
5
10
5
10
5
10
5
10
5
10
5
10
5
I
Typ.1 MAX.*
READ CYCLE TIME
Read Cycle
tRC
Address Setup
tADS
Chip Select
tcs
Address Hold
tADH
Read Access
tRA
Data Out Hold
tOOH
Data Out Active
tDOA
tTLH
Output Transition
tTHL
Ch ip·Select
Input Rise and
Fall Time,
trCE
tfCE
-
110
130
80
40
-
1000
450
0
-
ns
-
-
ns
500
250
-
ns
450
250
170
160
120
70
60
50
35
25
-
ns
750
380
230
190
160
100
100
75
60
40
15
5
1
-
-
-
-
1200
550
40
0
700
350
460
200
150
100
150
100
140
80
25
20
1000
450
0
-
ns
ns
ns
ns
)1S
WRITE CYCLE TIME
Write Cycle
twc
Address Setup
tAOS
Chip Select
tcs
Address Hold
tADH
Write Hold
tWRH
Write
tWRW
Data·1 n Setup
tOIS
Oata·ln Hold
* See Symbols Definitions.
386
tDIH
10
5
10
-
-
500
250
-
-
-
100
70
100
70
80
35
10
10
-
ns
General-Purposes Memories
CD4061A
aJ REAO-CYCLE WAVEFORMS
~~~ECT
--'
~
ADDRESS
DATA IN =oo",'r CARE
WIR= lOGIC "0"
f
~'Os
-
~---
'ADS
____
~r-------"""20",
.
tRC
____
________ J
J-I-
-aj
DATA OUT
\~
~-I 'ADH
t DDA
HIGH IMPEDANCE
1
---I 'DOH fo--r----;,;"I""":-;LE~V;::EL""' I
---.::"2-0':.;'L~E~VE;1L.-Jr;:HiiGIG:;;-H"'M;;;'''ED'''A",NC,"'
1----4-__
"0" LEVEL
I.~
__~"',"~LE,-,V",EL~ 1 HIGH IMPEDANCE
----I 'DOH
fo---
b) WRITE-CYCLE WAVEFORMS
\~--
CHIP
SELECT
---'k
~r---------~,- _ _ _ _ _ _ ~W~ _ _ _ _ _ _ .J
_______
--1 'ADS I-"
t==::
READ/WRITE
DATA IN
'WRW
====\I
--I'AaH
If':--- f~'------------_
f--
lOtS
-=+t--~f_D'_H
_ _ _ _ _ _ _ __
NOTE; CHIP SELECT MUST BE HIGH DURING AN ADDRESS CHANGE
Fig. 2 - Typical write-read waveforms.
SYMBOL DEFINITIONS
tRC
- Read Cycle Time - Time required
between address changes during a
read cycle. Minimum read cycle
time is equal to tADS(min) + tcs
(min) + tAOH(min).
tAOS - Address Setup Time - Time required before the Chip-Select voltage level can be lowered after the
slowest address transition.
tAOH - Address Hold Time - Time required before the earliest address
transition can take place after ChipSelect voltage level has been in·
creased. tAOH(min) + tAOS(mir.)
is the minimum time required to
discharge internal nodes and allow
setting of address decoders during
an address transition. Chip-Select
level must be high during each
address change, even if only read or
write cycles are successively performed. However, if address is not
changed, the Chip-select may remain in its active (low) state during
successive read and write cycles.
tcs
- Chip select Time - Time required
for the Chi p Select to be active for
a valid memory cycle.
tRA
- Read Access Time - Measured
from Chip Select negative going
transition to the valid output data.
tDOA - Data-Out Active - Time required
before the high-impedance state of
Data Output is changed to a low·
voltage state and Data output is
changed to a high-voltage state. (If
the read out data from a selected
storage location is logic "1", then
Data Output will rise and Data
Output will fall. If the read out
data is logic "0", both Data Output
and Data Output will maintain their
original states.
I
tDOH - Data-Out Hold - Time required for
the Data Output and Data Output
to change from an active to a highimpedance state.
twc
- Write Cycle Time - Time required
between address changes during a
write cycle. This time sets the
maximum operating speed for the
memory, with a minimum cycle
time equal to tAOS(min) + tcs
(min) + tAOH(min).
tWRH - Write Hold Time - Time required
before the negative transition of
R/W pulse with respect to the negative transition of the Chip·Select
signal.
tOIS - Data-In Setup Time - Time required for the data input to be valid
~fore the negative transition of the
R/W pulse.
387
RCA CMOS LSI Products
CD4061A' .
tOIH - Data-In Hold Time - Time required
for the data input to be valid after
R/W pulse is returned to a low
level. The minimum data-in width is
equal to tOlS(min) + tOIH(min).
twRW-Write Width - Time required for
the RIW pulse to be high. Note that
the positive transition of this signal
can be made after the Chip-Select
signal is high. In addition, the high
state of the rilW signal shall be
within the Chip-Select active state
by at least a twRH period.
AlBENT TEMPE"ATUfilE (TA)-U·C
TYPICAL TE .......TUM COEFFICIENT IS -O.• "'·C
AT ALL VALUES 01 Yes
~~kJ=1+
I
~
50
PKG. DISSIPATION (200 ",WI
GATE-TO-SOtHtCE VOLTAGE
C »-IOV
40
I
30
w
5
10
15
20
Ii
10~
I
I
I
.."j
Ii
5V-
III
:1
IEtf
10
92CS-231541t1
15
'U:CS-23855
DRAIN-lO-SOURCE VOLTAGE (V05)-V
Fig. 4 - Minimum n-channel drain characteristics.
Fig. 3 - Typical n-channel drain characteristics.
DRAIN-lO-SOURCE VOL.TAGE {Vesl-V
-10
!Il·
10V'
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
-15
VOLTAGE
~
•
OV
Inmw
!
i
~
10V
IIttt+tttttt
~1tGATE-TO-SOURCE
{VGS1=ISV
~
z
l1tln
AMBIENT TEMPERATURE (TA}z2S-C
:
TYPICAL TEMPERATURE COEFFICIENT IS -Q.3%'-C
AT ALL. VALUES OF VGS
1
DRAIN-lO-SQURCE VOLTAGE (VDSI-V
-5
-15
-10
-5
[AMBIENT TEMPERATURE (TAl' 25-C
f ~,(PICAL TEMPERATURE COEFFICIENT
'"
IS -O.3%I-C,AT ALL VALUES ~lr1.S H-t++H+OVtH+bMti-2.5
:::
:: +
t,"~!tn
'.f -; ..j:.
t
-.:t.
!pI !..,
~
,:
t!
IE
l?tVt·.
1&1
f~
~
-60
-Ht
-5
:t.'\:I:.f
:+'!
MAXIMUM AVERAGE
PKG. DISSIPATION (200 mWI
f
+\
-7.5
~
. -10
!
:li
. -12.5
~
-15
!
~
1..
92CS-238S6
Fig. 5 - Typical p-channel drain characteristics.
Fig. 6 - Minimum p-channel drain characteristics.
AMIlfENT T£MP~RATURE ITA)-2S-C
300 ..
f
%
g
!
~
~
~
~
.
- tH
ttl.
AMBIENT TEMPERATURE (TA1=25-C
ittl:t\:.~
200
,~6
JJ.~
,~
~~ff
200
10
f
+
~u
,
t
j:
11
100
ooli
II'
0
I
Iii
50
100
Iii
100
+
200
25o
300
~
..
".
II III
~
!
~
;::
;;;
~
~
,1'111
,11n
1m
1;'1 HI
I
200
' -:'1;+
~~~-.J .t I·:
r+
~"Q~
, 1P.G€.
1 ~ff
.~~~"1 ""'O\.
+~o~ :
100
:t:
100
.•0
.,
r il+..•.
.\~'>J.-r I t
00
350
LOt.!> CAPACITANCE CCL)-pF
50
100
150
200
250
Fig. 7 - Typicallow·to-high transition time
388
CL.
,
ifH11l1r l"l-n
300
350
LOAD CAPACITANCE (CLI -pF
VI.
.-
t'
nCS-2381)8
(tTLH)
H1
Fig. 8 - Typical high-to-Iow transition time
(tTHL)
vs. CL.
General-Purposes Memories
CD4061A
600
.00
400
I
'j
10V
'00
15Y.
200
': 'I~d\J!
; ~ ::
-1-15'"
fin
'00
~
200
+
100
100
eo
100
ISO
200
250
300
'P.!
350
Ii
H·
t~
I"
f+1-l
-50
LOAD CAPACITANCE (CL1-pF
92C$-231160
i;!
zs
-25
!So
15
100
125
AMBIENT TEMPERATURE (TA1- °C
Fig. 9 - Typical read access time (tRA)
CL.
l<16
MEMORY
ARRAY
-{!)
Ne
!)2CS-27184
Fig. 1 - Functional block diagram for CD40061 and CD40061A.
STATIC ELECTRICAL CHARACTERISTICS
Values shoVlin for VOO = 5 V apply to all types, values shown for VDD = 10 V apply to the
CD40061AD and CD40061AE only.
CHARACTERISTIC
TEST CONDITIONS
VoIV)
TYPICAL
VALUES
at 25°C
UNITS
10
20
0.5
1
J.l.A
-
0.05
0.05
0
0
V
Quiescent Device
Current, 100
5
10
Output Voltage, Low
Level, VOL
5
10
Output Voltage, High
Level, VOH
5
10
4.95
9.95
-
5
10
V
-
-
Output Current, Low
Level,IOL
0.4
0.5
5
10
0.85
2.1
-
1.1
2.8
rnA
Output Current, High
Level,IOH
4.5
9
5
10
-0.3
-0.6
-
-0.4
-0.9
mA
Noise Immunity, All
Inputs Low, VNL
0.8
1
5
10
1
2
1.5
3
V
Noise Immunity, All
Inputs High, VNH
4.2
9
5
·10
1
2
-
1.5
3
V
Output Resistance, Off
State, Roloff)
392
VDDIV)
LIMITS
Full Temp. Range
Min. Max.
5
5
10
5
-
10
10
Mn
General-Purposes Memories
CD40061, CD40061 A
DYNAMIC ELECTRICAL CHARACTERISTICS at VDD ± 5%, Input t r ,
tf =20 ns, and CI =50 pF,see Note 2.
Values shown for VDO = 5 V apply to all types; values shown for VDO
the CD40061AD and CD40061AE only.
READ CYCLE TIMES (For waveforms, see Figs. 2, 3, and 4)
TEST
CONDITIONS
CHARACTERISTIC
VDD(V)
LIMITS·
Full Temp. Range
Min. Max.
tRDS
5
10
5
10
5
10
5
10
1380
380
40
20
0
0
0
0
Read Hold,
0
0
-
tRDH
5
10
Data Out Hold,
5
10
5
10
5
10
5
10
--
tDOH
-
65
40
50
35
880
380
-
Chip-Select, (Note 1)
tcs
Address Setup, (N ote 2) tADS
Address Hold,
Read Setup,
tADH
Data Out Active,
tDOA
Read Cycle, (Note 3)
tRC
Access,
tACC
-
-
-
-
-
-
-
850
345
= 10 Vapply
TYPICAL
VALUES
at 25°C
720
290
20
10
-5
-5
-5
-5
-5
-5
40
20
35
25
720
290
700
265
to
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
WRITE CYCLE TIMES (For waveforms, see Figs. 2,3, and 4)
TEST
CONDITIONS
VDD(V)
CHARACTERISTIC
LIMITS·
Full Temp. Range
Min. Max.
420
200
Address Setup, (Note 2) tADS
5
10
5
10
Address Hold,
tADH
5
10
0
0
Write Setup,
tWRS
5
10
330
190
5
10
5
10
5
10
5
10
330
190
Chip-Select,
tcs
Write Width,
tWRW
Data In Setup,
tOIS
Data In Hold,
tDIH
Write Cycle, (Note 3)
twc
40
20
0
0
40
20
480
240
-
-
-
TYPICAL
VALUES
at 25°C
350
150
20
10
-5
-5
270
140
270
140
-5
-5
20
10
400
180
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
For footnotes, see page 4.
393
RCA CMOS LSI Products
CD40061, CD40061A
DYNAMIC ELECTRICAL CHARACTERISTICS (Cont'd)
READ/MODIFY/WRITE TIMES (For waveforms, see Figs. 2, 3, and 4)
TEST
CONDITIONS
CHARACTERISTIC
Chip-Select, (Note 1)
tcs
Address Setup, (Note 2) tAOS
Address Hold,
tADH
Read Setup,
tRDl:)
Data Out Active,
tDOA
Previous Data Hold,
tPDH
Access,
tACC
Read Width Effective,
tRDW
Write Setup,
tWRS
Write Width,
tWRW
Data I n Setup,
tDIS
Data In Hold,
tDIH
Read/Modify/Write
Cycle, (Note 3)
tRWC
VDD(V)
Min.
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
1190
545
40
20
0
860
355
330
190
330
190
0
0
40
20
-
5
10
1230
570
-
-
980
410
20
10
-5
-5
-5
-5
35
25
50
25
700
265
710
270
270
140
270
140
-5
-5
20
10
-
-
0
-
0
-
0
-
-
50
35
65
40
850
345
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
430
-
Note 2 - Address rise and fall times must be equal
to or less than 1 !J,S under all conditions
and for all modes.
Note 3 - Cycle time defines the shortest time in
which this memory will correctly perform its desired function.
=0, f =1 MHz)
Min.
Typ.
Max_
Address Input, CA
-
9
-
pF
Chip-Select, CCS
-
9
-
pF
Read/Write Input, CWE
-
5
pF
Data Input, CDI
-
5
-
Data Output, CDO
ns
Note 1 - The chip-select times specified provide an
active output data time of 50 ns minimum.
put or required at the input. The maximum limit
indicates the longest time generated at the output or required at the input. The tYpical values
are for 250 C and nominal voltage.
Timing
measurements for the transition period are taken
at either the 0.8 VDD or 0.2 VDD point.
CHARACTERISTICS
UNITS
at 25°C
-
-
dynamic characteristics un,der worst operating
conditions are based on the time durations expressed in Fig,. 2, 3, and 4. The minimum limit
indicates the shortest time generated at the out-
394
TYPICAL
VALUES
Max.
-
• The maximum and minimum .Iimit values of the
CAPACITANCES (VI
LIMITSFull Temp. Range
10
UNITS
pF
pF
General-Purpo.e. Memorle.
CD40061, CD40061A
CHIP-SELECT
READI
WRITE
DATA
OUT
DATA
OUT
DON'T CARE
1';/11////Ii
92CS-27185RI
Fig.2 - RBad cycle waveforms for CD40061, CD40061A.
ADDRESS
'WRS
'WRW ----~-!
READI
WRITE
DATA IN
DON'T CARE
0"1;1P$$
I
92CS-21186RI
Fig.3 - lIl7ite cycle waveforms for CD40061, CD40061A.
ADDRESS
~~t~~
____________
~
______
~~~~~
REiD/WRITE
DATA
OUT
DA'i'A
OUT
HIGH
IMp:.:,;E'='D.,.,AN""'C""'E'\._ _ _ _
+-....:..._-+.-r
##$/l/J!gliXl'-----l
DATA IN . .
DON'T CARE
W/lJPfff&
92CS-27187RI
Fig.4 - RBad/modify/write cycle waveforms for CD40061, CD40061A.
395
RCA CMOS LSI Products
CD40114B
Preliminary Data
COS/MOS 64-Bit Random
Access Memory
High-Voltage Types (20-Volt Rating)
Features:
."
• Input address latch
• 3-state outputs
• Low-power TTL compatible
• ~ivalent to and pil1-COfT1llltible with National 74C89
• Pin -compatible with 74S189
• Buffered inputs and outputs
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard
No. 13A, "Standard Specifications for description of
"B" Series CMOS Devices"
INPUT 4
INPUT 3
llO2
vss
4
~
0*
014
I51l4
"
6
10
9
7
•
c"
013
~
TOP VIEW
92CS-30960
ttADORESS INPUTS
Terminal Assignment
• Main frame
memories
• Memory storage
WRT'i'E
DATA
011
60i
012
VDD
."
I~
14
13
12
Applications:
The RCA-CD40114B is a 16-word x 4-bit
random access memory (RAM) with four
~n~s, four data inputs, a
ENABLE (WE) input,a MEMORY ENABLE
(ME) input, and four 3-state data outputs.
The four address inputs are decoded internally to select one of the 16 possible
word locations. The address information is
latched on the negative edge of the ME input
by an internal address register. The selected
output assumes a high-impedance condition
when the device is writing or disabled. The
ME input and the 3-state outputs allow
memory expansion.
DATA
16
ME:
WE
ME
WE
L
L
H
H
L
H
H
L
• Scratch-pad
memories
• Games
CONDITION OF
OPERATION OUTPUTS
3-STATE
Write
Complement of
Read
Selected Word
3-STATE
Inhibit,
Storage
3-STATE
Inhibit,
Storage
DATA
DATA
wr
ME
'r
I ADORESS
LATCH!
DECODER
AOORESS
INPUTS
C
14
0'
nOD
I
I
I
I
IMEMORYIARRAY
I
I
I
I
I
I
I
Vooo,.
I
vssoa
I
I
92CS' 29202R2
Fig. 1 - Functional Block Diagram
396
ALL'NM
PROTECTED BY
COS/MDS PROTECTION
NETWORK
Vss
General-Purposes Memories
CD40114B
Address Operation
The high-to-Iow transition of ME enables the
memory. Address inputs must be stable
(either high or low) prior to and during this
transition, but it is not necessary to hold
them stable beyond it.
Write Operation
When WE and ME are low, information
present at the data inputs is written into
the memory at the selected address.
Read Operation
When ME is low and WE is high the complement of the memory contents at the selected
address location are non-destructively read
out at the four data outputs.
The CD40114B is supplied in 16-lead
hermetic dual-in-line ceramic packages (0
and F suffixes), 16-lead plastic packages (E
suffix), and in chip form (H suffix).
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the fol/owing ranges:
CHARACTERISTIC
Supply·Voltage Range (For T A = Full Package
Temperature Range)
LIMITS
MIN_
MAX.
3
18
UNITS
V
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE. (V DO)
-0.5 to +20 V
(Voltages refer~nced to VSS TermInal)
-0.5 to V DD +0.5 V
INPUT VOLTAGE RANGE. ALL INPUTS
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PoER PACKAGE (PO)
........ '
500mW
For T A = -40 to +600 C (PACKAGE TYPE E)
Derate LInearly at 12 mW/C to 200 mW
For T A = +60 to +85 ~ (PACKAGE TYPE E). .
. . . . . . . ..
500mW
For T A = -55 to +100 ~ (PACKAGE TYPES 0, FI
Derate LInearly at 12 '!'W/ C to 200 mW
For TA = +100 to +125 C (PACKAGE TYPES D, F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR T A = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE ITA):
-55 to + 125°C
PACKAGE TYPES D. F. H
-40 to +85°C
PACKAGE TYPE E
-65 to +150oC
STORAGE TEMPERATURE RANGE (T,,)
. .
LEAD TEMPERATURE (DURING SOLD~RING):
At distance 1/16±1/32 inch 11.59 ±0.79 mm) from case for 10 s max.
I
Voo
~
ou~:~~I-~-.-tIOkn
ou~:~~ 1----...
r
rOPF
10 kQ
5PF
MEMORY Voo
~
OV
_
Voo
DATA
OUTPUT
J
O.
-.~~~~-
0
10.
_ _ Veo -----~--VOD
~
TLZ
MEMORY
'E"N'Aii:E
OV
Vo•
....
'THZ
VDO
~oo
~
OV _ _ _ _- - - ' . - ,
92CS-30962
0,[ Voo
92CS-30961
Fig. 2 - Output low to high-impedance
Fig. 3 - Output high to high-impedance
transition time test circuit
transition time test circuit
and waveforms.
and waveforms.
397
RCA CMOS LSI Products
CD40114B
READ CYCLE
i.iE"MoiiY
Voo - - - t r - -.......I
ENAiiLE
0
ADDRESS VOO
INPUT
0
-----.J/-t-"l/----------'1"-
92C5-30963
Fig. 4 - Read cycle waveforms.
WRITE CYCLE
M'E'MoRY
ENABLE
VOO
0
ADDRESS VDO
INPUT
WRffi
0
VOO
ENABLE
0
Voo
OATA
INPUT
0
'32CS-30964
Fig. 5 - Write cycle waveforms
READ MODIFY CYCLE
tM.
MEMORY VDO
ENABi:E
0
--17--___ 1
1"---------
DATA
IN
92CS-3096S
Fig. 6 - Read·modify·write cycle waveforms.
398
General-Purposes Memories
CD401148
STATIC ELECTRICAL CHARACTERISTICS
LIMITS AT INDICATED TEMPERATURES {OCI
Values at -55, +25, +125 Apply to D,\F ,H Packages
Values at -40, +25, +85 Apply to E Package
CONDITIONS
CHARACTERISTIC
+25
Vo
(V)
VIN
(V)
VDD
(V)
-55
-40
+85
+125
Min_
Typ_
Max_
Quiescen t Device
Current,
100 Max.
-
0,5
5
5
5
150
150
-
10
15
10
300
.600
20
20
100
10
20
100
300
600
3000
0.04
0.04
-
0,10
0,15
0,20
-
0.04
0.08
5
10
20
100
Output Low
(Sink) Current
IOL Min.
0.4
0,5
5
0.64
0.61
0.42
0.51
1
-
0.5
1.5
4.6
0,10
1.6
2.5
9.5
13.5
0,5
0,10
0,15
1.3
34
-0.51
-1.6
-1.3
-3.4
2.6
0,15
0,5
10
15
5
5
10
15
6.8
-1
-3.2
-2.6
-6.8
-
-
0
0.05
0
0.05
0.05
Output High
(Source)
Current,
I'OH Min.
3000
1.5
4
4.2
-0.64 -0.61
-2
-1.8
-1.6 -1.5
-4
-4.2
1.1
2.8
-0.42
-1.3
-1.1
-2.8
0.36
0.9
2.4
-0.36
'-1.15
-0.9
-2.4
Output Voltage:
Low-Level,
VOL Max.
-
0,5
5
0.05
-
0,10
-
Output Voltage:
High-Level,
VOHMin.
-
0,15
0,5
0,10
-
0,15
10
15
5
10
15
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
Input Low
Voltage,
VIL Max.
Input High
Voltage,
VIH Min.
I nput Current
liN Max.
3·State Output
Leakage Current
lOUT Max.
-
0
5
10
15
-
-
5
1.5
-
-
1.5
-
3
4
3.5
-
-
1.5,13.5
0.5,4.5
1,9
10
15
5
3
4
-
10
15
7
1.5,13.5
11
0,18
18
±0.1
±0.1
±1
±1
-
0,18
18
±OA
±OA
±12
±12
-
0,18
-
-
7
-
-
-
11
±10- 5
V
-
-
-
mA
-
1,9
3.5
IJ.A
-
0.5,4.5
.-
UNITS
V
I
±0.1
IJ.A
±10-4 ±0.4
IJ.A
399
RCA CMOS LSI Products
CD40114B
ELECTRICAL CHARACTERISTICS at TA = 250 C, CL
=50 pF, RL = 200 kn, t r , tf =20 ns
Unless Otherwise Specified
CHARACTERISTIC
TEST
CONDITIONS
UNITS
Typ. Max
Access Time From Address Change, tAA
5
10
15
325 650
140 280
120 240
Min. Address Setup Time, tAS
5
10
15
75
30
25
150
60
50
ns
Min. Address Hold Time, tAH
5
10
15
30
20
15
60
40
30
ns
Min. Memory Enable Pulse Width, tME, tME
Min. Write Enable Setup Time For a Read, tSR
Min. Write Enable Setup Time for a Write, tws
5
200
400
10
15
75
60
150
120
5
10
15
5
10
-
tME
tME
15
-
tME
Min. Write Enable Pulse Width, tWE
5
10
15
Min. Data Input Hold Time, tH
10
5
15
5
10
15
Min. Data Input Setup Time, ts
ns
ns
0
0
ns
0
150 300
50 100
40
80
ns
ns
25
12
10
50
25
20
ns
25
12
50
25
20
ns
10
Propagation Delay Time from Output-high
or Output-low \0 High-Impedance State
from Memory Enable
RL = 10 kn
CL =5pF
5
10
15
150 300
60 120
50 100
ns
Propagation Delay Time from Output-high
or Output-low to High-Impedance State
from Write Enable
RL=10kn
CL = 5 pF
5
10
15
150 300
60 120
50 100
ns
5
10
15
250
100
80
500
200
160
ns
Propagation Delay Time From Memory
Enable, tpd
400
LIMITS
VDD
(VI
Input CapaCitance, CIN
Any Input
5
7.5
pF
Output Capacitance, COUT
Any Output
6.5
13
pF
General-Purposes Memories
Preliminary Data
A7
24
A6
23
VOO
AS
22
A9
A5
3
A4
4
A3
21
All
CSI/OE
A2
6
19
AIO
7
18
CS2
AD
8
17
07
00
9
16
06
01
10
15
05
02
II
14
04
VSS
12
13
TOP VIEW
CMOS 4096-Word X 8-Bit Static
Read-Only Memory
20
AI
CDM5332, CDM5333
Features:
03
92 CS- 34993
CDM5332
TERMINAL ASSIGNMENT
• Low power replacement for NMOS ROMS
• Choice of two industry standard pin outs:
CDM5332 is pin compatible with INTEL 2732 and 2332A
CDM5333 is pin compatible with Supertex CM3200, TI TMS 4732,
Motorola MCM 68732 and MCM 68A332
• Fast access time: 450 ns at 5 V
• TTL input and output compatible
• Three state outputs
• Two programmable chip selects
The RCA CDM5332 and CDM5333 are 32,768-blt maskprogrammable CMOS Read Only Memories organized as
4096-word x 8-bits and are designed for use in general
purpose microprocessor systems, such as the CDP1800series system. Two chip-select inputs (CS1, CS2) are
provided for memory expansion. Chip selects CS1 and CS2
directly gate the output buffers. Chip select CS2 gates the
address decoder for the standby mode. The polarity for
each chip select is user mask-programmable. (See Data
Programming Instructions in this data sheet).
The CDM5332 and CDM5333 differ only in terminal
assignments and are pin compatible with standard industry
types. CDM5332 is pin compatible with Intel 2732 and
2332A. COM5333 is pin compatible with Supertex CM3200,
T.!. TMS4732, and Motorola MCM68732 and MCM68A332.
The COM5332 and COM5333 are supplied in 24-lead dualin-line ceramic packages (0 suffix) and 24-lead dual-in-line
plastic packages (E suffix).
TO OTHER
{
MEMORY
CHIP SELECTS
~------";MAII
A7
24
Voo
A6
23
A8
A5
22
A9
21
CS2
20
CSI/OE
A4
, - - - - - - - - - 1 MA 10
, - - - - - - - - 1 MA 9
A3
A2
MAS
A1
ADDRESS BUS
ROM
COM5332
OR
COM5333
7
AO
=--=- =--::. .
RAM
4
CPU
COPI800
SERIES
19
AIO
18
All
17
07
DO
9
16
06
01
10
15
05
02
II
14
04
VSS
12
13
03
I
TOP VIEW
92CS- 34 995
8-BIT BIDIRECTIONAL DATA BUS
CDM5333
TERMINAL ASSIGNMENT
Fig. 1 - Typical CDP1800 series microprocessor system.
401
RCA CMOS LSI Products
CDM5332, CDM5333
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to Vss terminal) ................................................................................. -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ...........................................•....•..••...•........•.•.•. -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ ±10 mA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60·C (PACKAGE TYPE E) .................. '" ....................................................... 500 mW
For TA =+60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 12 mW/'C to 200 mW
For TA = -55 to +100'C (PACKAGE TYPE D) ........................................................................... 500 mW
For TA = +100 to 125·C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................ 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ...................................... , .......................................•............. -55 to +125'C
PACKAGE TYPE E ..............................................................................................-40 to +85'C
STORAGE-TEMPERATURE RANGE (Tstg) ........................................................................ -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265'C
RECOMMENDED OPERATING CONDITIONS at TA =-40 to +85°C
For maximum reliability, nominal operating conditions should be selected so that operation Is always within the 'ollowlng
ranges:
LIMITS
UNITS
CHARACTERISTIC
Min.
DC Operating Voltage Range
Input Voltage Range
STATIC ELECTRICAL CHARACTERISTICS at TA
=·40 to +85°C, VDD =5 V ±
Max.
4
6.5
Vss
Voo
V
10%, Except as noted
LIMITS
CONDITIONS
ALL TYPES
CHARACTERISTIC
Vo
(V)
Min.
Typ.-
Max.
-
0, Voo
-
50
p.A
-
rnA
(V)
100 6
UNITS
VIN
Output Low Drive (Sink) Current
IOL
0.4
0, Voo
1.8
2
3.6
Outout Hiah Drive JSourcel Current
IOH
Voo -0.4
0, Voo
-0.4
-0.8
Output Voltage Low-Level
VOL
-
0, Voo
Voo -0.1
°
0.1
VOH
-
0, Voo
Output Voltage High-Level
Voo
-
Input Low Voltage
VIL
0.5, Voo -0.5
-
-
0.8
Input High Voltage
'VIH
0.5, Voo -0.5
-
2.4
-
-
-
±1
5
7.5
10
15
0.8V,2.4V
-
0.25
0.5
O.8V,2.4V
-
7.5
15
Quiescent Device Current
Input Leakage Current (Any Input)
3-State Output Leakage Current
liN
lOUT
0, Voo
0, Voo
CIN
-
COUT
-
-
Input Capacitance
Output Capacitance
Standby Device Current
Is By 6
Operating Device Current
loPERLI.
-Typical values are for TA
402
-
0, Voo
=25° C and nominal Voo.
±1
V
p.A
pF,.
rnA
General-Purposes Memories
CDM5332, CDM5333
STATIC CHARACTERISTIC Device Current Telt Condltlonl:
CHIP SELECT
STATUS
CHARACTERISTIC
ADDRESS
INPUT TO TOGGLE
FREQUENCY
OUTPUT
LOADING
0
Open Circuit
100 Quiescent
Device Current
Any Chip
Select Disabled
Standby
Device Current
CS2 Disabled
at TTL Level
1 MHz
Open Circuit
CS2 Active
CS1 Don't Care
1 MHz
Open Circuit
tSBY -
Operating
Device Current
IOPER -
DYNAMIC ELECTRICAL CHARACTERISTICS lit TA = -40 to +85°C, VDD = 5 V ± 10%,
Input tr, " = 10 nl, C. = 100 pi, 1 TTL Load
LIMITS
CHARACTERISTIC
UNITS
fAA
tOH
Address Access Time
Data Hold from Address or CS2
CS1/0E Enable to Bus Active
tcx
toF
Data Fioat from CS1/0E Disabled
Output Hold from CSlIOE Disabled
tOH
Mln.+
Typ.-
-
-
50
0
0
Max.
450
150
120
ns
-
+Time required by a limit device to allow for the indicated function.
-Typical values are for TA = 25° C and nominal VOO.
ADDRESS OR CS2
*'
I
r
------------, ~------'A-A===~~_~-I-------------' ~-'-DH--------------------CSI/OE
'ex
, OH
OUTPUT BUS - - - - - - - - - - - - - - - - - - - - - ( '
1 4 - - - - - ' D F - - - - I...
92GII-34998
Fig. 2 - Timing waveforms.
403
RCA CMOS LSI Products
CDM5332, CDM5333
DO 01
All
AID
A9
A8
A7
A6
A5
A4
A3
A2
Al
02 03 04 05 06 07
......X1
...
:>
II)
....
:>
G-
!!:
.,
'"
(I)
II:
0
0
<[
.....
11:-
32768-BIT
CELL
MATRIX
ON
~~
CSIIOE
CHIP
SELECT
BUFFERS
AND
PROGRAM
0::
x
AD
CS2
92CM-34997
Fig. 3 - Functional block diagram.
ROM ORDERING INFORMATION
All RCA mask-programmable ROM's are custom-ordered
diskette generated on an RCA development system, or
devices. ROM program patterns can be submitted to RCA
'computer punch cards.
by using a master device (ROM, PROM or EPROM), a floppy
DATA PROGRAMMING INSTRUCTIONS
W'hen a customer submits instructions for programming
3. Master Devlce- a ROM, PROM, or EPROM that contains
RCA custom ROM's, the customer must also complete the
the required programming information.
relevant parts of the ROM information sheet and submit this
The requirements for each method are explained in detail in
sheet together with the programming instructions.
the following paragraphs:
Programming instructions may be submitted in anyone of
three ways, as follows:
Computer-Card Method
1. Computer-Card Deck - use standard 80-column
computer punch cards.
Use standard 80-column computer cards. Each card deck
must contain, in order, a title card, an option card, a data2. Floppy Diskelle - diskette information must be
format card, and data cards. Punch the cards as specified in
generated on an RCA CDP1800-series microprocessor
the following charts:
development system.
TITLE CARD
Column No.
Data
1
Punch T
2-5
leave blank
6-30
Customer Name (start at 6)
31-34
leave blank
35-54
Customer Address or Division (start at 35)
55-58
leave blank
59-63
RCA custom selection number (5 digits) (Obtained from RCA Sales Office)
64
leave blank
65-71
RCA device type, without COM prefix, e.g. 5332E
72
Punch an opening parenthesis (
73
Punch 8
74
Punch an closing parenthesis)
75-78
leave blank
79-80
Punch a 2-digit decimal number to indicate the deck number;
the first deck should be numbered 01
404
General-Purposes Memories
CDM5332, CDM5333
DATA PROGRAMMING INSTRUCTIONS (Conl'd)
OPTION CARD
Use the ROM Information Sheet to select the polarity options, P, N, orX, for the desired ROM type.
Column No.
1-6
Dala
Punch the word OPTION
7
leave blank
8-17
RCA device type, including CPM prefix, e.g. CDM5332E
leave blank
18-27
28-29
Punch P or N per ROM Information Sheet
30-39
40-78
79-80
Punch X or leave blank per ROM Information Sheet
leave blank
Punch the deck number (the 2-digit number in
columns 79-80 of the title card)
DATA-FORMAT CARD
The data-format card specifies the form in which the data is to be entered into ROM.
Column No.
Dala
1-11
Punch the words DATA FORMAT
12
leave blank
13-15
Punch the letters HEX
16
leave blank
17-19
Punch POS
20-78
leave blank
79-80
Punch the deck number (the 2-digit number in
columns 79-80 of the title card
I
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Data
Column No.
Dala
1-4
Punch the starting address
26-27
2 hex digits of 9th WORD
in hexadecimal for the
28-29
2 hex digits of 10th WORD
following data.'
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
6-7
2 hex digits of 1st WORD
33-34
2 hex digits of 12th WORD
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
2 hex digits of 4th WORD
40
Blank
15
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43-44
2 hex digits of 16th WORD
18-19
2 hex digits of 6th WORD
45
20
Blank
Blank if last card, semicolon
follow
21-22
2 hex digits of 7th WORD
46-78
Blank
23-24
2 hex digits of 8th WORD
79-80
Punch 2 decimal digits
25
Blank
as in title card
'The address block must be contiguous starting at an even-numbered address.
Column 4 must be zero.
405
RCA CMOS LSI Products
CDM5332, CDM5333
which would otherwise be punched on computer cards.
must be submitted on the ROM Information Sheet. In
addition. specify the master device type; RCA will accept
Intel types 1702, 2704. 2708. 2716. 2732. 2332A. 2758.
Supertex CM3200. T.I. TMS4732. Motorola type: MCM68732
and MCM68A332 or their equivalents as well as RCA type
CDP18U42. If the ROM to be manufactured is smaller in
memory size than the master device. or if more than one
ROM pattern is stored in the master device. the starting
address and size of each pattern must be stated on separate
ROM Information Sheets.
To minimize power consumption. all unused ROM locations
should contain zeros.
Floppy-Diskette Method
The diskette contains the ROM address and data
information. Title. option. and data-format information.
which would otherwise be punched on computer cards.
must be submitted on the ROM Information Sheet. In
addition. specify the RCA Development System used to
generate the diskette (CDP18S005. CDP18S007. or
CDP18S008) and supply a track number or file name. If
possible. include a printout of the program for verification
purposes. The format of the address and data information is
essentially the same as that described for Computer-Card
method with the addition of a carriage-return character at
the end of each line and an end-of-file character (DC3) at
the end of the file.
If the Master-Device is smaller than 4 kilobytes. the starting
address of each Master-Device must be clearly identified.
For additional information refer to the following RCA
publications:
"Sales Policy and Programming Instructions for f\CA Custom
ROMs". RPP-610.
Master-Device Method
Data may be submitted on a master ROM, PROM. or
EPROM device. Title, option. and data-format information.
"Programming 2732 PROMs with the CDP18S480 PROM
Programmer", RCA Application Note ICAN-6847.
ROM INFORMATION SHEET
How is ROM pattern being submitted to RCA?
0 (Complete part B)
Computer Cards
Floppy Diskette
0 (Complete parts A. B, and D)
Master Device (PROM) 0 (Complete parts A B. and C)
check one
Customer Name (stsrt at left)
"'a:
"'
I11-
I I 11 1 I I I I I ITT I I I I
35-54
I
59-63
I I I I I RCA Custom Number (Obtained from RCA Sales Office)
65-71
I I I I
I
I I
~
I
I I
I
111
I
I
one
CD
I-
Pin
Functions
a: CDM5332
: Polarity Options
CDM5333
Polarity Options
Column #
Circle the ROM type desired, then circle one letter (P, N, or X)
In each column for that ROM.
P =active when logiC 1, N
=acllve when logic 0, X = don't care
CSl
CS2
PN
PN
X
X
X
X
X
X
X
X
PN
PN
X
X
X
X
X
X
X
X
28
29
30
31
32
34
36
37
38
39
If a diskette is submitted. check type of
If a master device is submitted,
RCA Development System used:
state type of ROM/PROM:·
c
Starting and last address
Ii:
of data block in the
:
Master Device (in Hex).
IIII I
Address or Division
I I I I I I I II
I
ROM Type (without CDM prellx), e.g. 5332E
Circle
406
11111 I I I
6-30
II
o
CDP18S005
Specify: Track #
rn
Software program used:
(check one)
o ROM SAVE
o SAVE PROM
o
CDP18S007
o
CDP18S008
Specify: File Name:
(check one)
o
MEM SAVE
o
SAVE PROM
General-Purposes Memories
Preliminary Data
A7
2.
Voo
A6
23
A8
A'
22
A9
21
WI:
.3
5
20
OE
'2
6
A'
CMOS 2048-Word by 8-Bit
LSI Static RAM
19
AIO
AI
18
;:s
AO
17
Iloa
I/O I
16
I/07
I/o2
10
1/03
vss
12
CDM6116-1, CDM6116-2
Features:
15
LID6
I.
1/05
13
I/04
•
•
•
•
•
•
•
•
TOP VI EW
92CS-35043
TERMINAL ASSIGNMENT
•
•
Fully static operation
Single power supply - 4.5 V to 5.5 V
All inputs and outputs directly TTL compatible
3-state outputs
Industry standard 24 pin configuration
Input address buffers gated off with chip deselect
Fast access time
Low standby and operating power - IDDSl = 1 pA typical, IOPER
maximum
Data retention voltage - 2 V min.
Operating temperature range (Max. Rating) - D· to 7D·C
The RCA-COM6116 is a 2048-word by 8-bit static randomaccess memory. It is designed for use in memory systems
where high-speed, low power and simplicity in use are
desirable. This type has common data input and data output
and utilizes a single power supply of 4.5 V to 5.5 V.
=35 mA
The input address buffers are gated off with chip deselect
for minimum standby power with inputs toggling.
The COM6116 is supplied in 24-lead, hermetic, dual-in-line
side-brazed ceramic (0 suffix) and in 24-lead dual-in-line
plastic packages (E suffix).
AIO
A9
1/08
1/07
A8
INPUT
ADDRESS
BUFFERS
A7
A6
XY
DECODE
,28,,28
MEMORY
MATRIX
I NPUTI
OUTPUT
DATA
8UFFERS
A5
1/06
I/05
I104
A4
1/03
A3
I/02
A2
IIOl
•
Al
AO
WE
CONTROL
LOGIC
- - . 0 VDO
OE
Fig. 1 - Functional block diagram.
4 - 0 VSS
92CM~
3!5044
TRUTH TABLE
--
L
CS
OE
-WE
AOTOAIO
MODE
DATA 1/0
H
X
X
X
STANDBY
HIGHZ
L
L
H
STABLE
READ
DATA OUT
L
H
L
STABLE
WRITE
DATA IN
L
L
L
STABLE
WRITE
DATA IN
= LOW
H = HIGH
X = DON'T CARE
407
RCA CMOS LSI Products
f'
CDM6116-1, CDM6116-2
MAXIMUM RATING, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO):
(All voltage values referenced to Vss terminal) ...•.•.••••••. , .•..•...•....•..•....•..•••••••••.•••..•...••••.••.••••••• -0.3 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ................................................................................ -0.3 to +7V
POWER DISSIPATION PER PACKAGE (Po):
ForTA =O· to +60·C (PACKAGE TYPE E) ................................................. , .............................. 500 mW
For TA = +60 to +70·C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mWI"C to 380 mW
For TA = O· to +70·C (PACKAGE TYPE D) ............................................................................... 500 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE ....................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 .................................................................................................. 0 to +70·C
PACKAGE TYPE E .................................................................................................. 0 to +70· C
STORAGE TEMPERATURE RANGE (Talg) ...•....••.........•.••...•...•..•.••...•......•••••.••••••.••..••.•••••••• -55 to +125°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case lor 10 s max........................................................ +265·C
OPERATING CONDITIONS atTA = O· to, +70·C
For maximum reliability, operating conditions should be selected so that operation Is always within the foHowlng rangee:
LIMITS
CHARACTERISTIC
ALL TYPES
MIN.
DC Opera.ting Voltage Range
Input Voltage Range
UNITS
MAX.
4.5
5.5
VIH
2.2
Voo + 0.3
VIL
-0.3
0.8
V
STATIC ELECTRICAL CHARACTERISTICS at TA = 0 to +70· C, YDD = 5 Y ± 10"10, Except as noted
LIMITS
CHARACTERISTIC
Standby Device
Current
Low-Level
MAX.
MIN.
TYP.-
MAX.
0.6
2
1
mA
1
100
1
30
pA
-
0.4
-
0.4
0.1
IOH = -1 rnA
2.4
Voo-o.1
-
-
0.8
IOL = 11lA
-
±0.1
±2
IOOSl
CS = Voo -0.2 V
IOL = 2.1 rnA
Output Voltage
±O.1
::1:2
±2
-
±0.5
±2
20
35
-
20
35
Input Leakage
Current
liN Max.
Voo = 5.5 V
VIN=OVtoVoo
-
lOUT
CS orOe = VIH
VIIO = 0 V to Voo
-
±0.5
VIN = VIL, VIH
-
2.4
V
V
IlA
Input
Capacitance
CIN
VIN = 0 V,
f= 1 MHz, TA=25·C
-
4
6
-
4
6
Output
Capacitance
CliO
VIIO = 0 V,
f = 1 MHz, TA = 25·C
-
6
8
-
6
8
eTypical values are for TA = 25· C and nominal Voo.
#Outputs open circuited; cycle time = Min. toyole, duty = 100"10
408
Voo-o.1
IOH = -11lA
IOPER#
-
-
-
VOH Min.
Operating Device
Current
0.1
-
High Level
3-State Output
Leakage Current
UNITS
TYP.e
CS = VIH
VOL Max.
CDMI11H
MIN.
loos
Output Voltage
CDM6116-1
CONDITIONS
rnA
pF
General-Purposes Memories
CDM6116-1, CDM6116-2
DYNAMIC I;LECTFlICAL CHARACTERISTICS at TA = 0 to +70· C, VDD = 5 V ± 10%,
Input., It =10 n.; CI. =100 pF and 1 TTL Load, Input Pul.e Levell! 0.8 V to 2.4 V
Read Cycle Time. See Fig. 2
LIMITS
CHARACTERISTIC
CDM8118-1
MIN.t
CDM8118-2
MAX.
MIN.t
UNITS
MAX.
Read Cycle Time
tRC
250
-
200
-
Address Acce!!s Time
tAA
250
tAcs
250
-
200
Chip Select Access Time
-
Chip Select to Output Active
tcx
15
-
15
-
200
Output Enable to Output Valid
tOEV
-
150
-
120
Output Enable to Output Active
tOEX
15
-
15
-
Chip Deselect to Output High Z
tCHZ
0
80
0
60
Output Disable to Output High Z
10HZ
0
80
0
60
Output Hold from Address Change
tOH
15
-
15
-
ns
tTime required by a limit device to allow for the indicate!:! function.
•
ADDRESS
DATA OUT
NOTE:
WE
IS HIGH DURING READ CYCLE.
TIMING MEASUREMENT REFERENCE
LEVEL IS 1.5 V
92CS ~
3~042
Fig. 2 - Read-cycle timing waveforms.
409
General·Purposes Memories
CDM6116-1, CDM6116-2
DYNAMIC ELECTRICAL CHARACTERISTICS It TA = 0 to +70· C, VDD = 5 V ± 10%,
Input fr, II = 10 n.; CL = 100 pF Ind 1 TTL Load, Input Pul.. LevelS: 0.8 V to 2.4 V
Write Cycle Time. See Fig. 3
LIMITS
CDM8118·1
CHARACTERISTIC
MIN.t
MAX.
MIN.t
MAX.
200
160
160
10
-
Address Setup Time
lAs
0
Write Pulse Width
twp
Write Recovery Time
tWA
200
10
-
Write Cycle Time
twc
Chip Select to End of Write
tcw
250
200
Address Valid to End of Write
tAW
200
160
0
Output Disable to Output High Z
tOHZ
0
80
0
60
Write to Output High Z
twHZ
80
0
60
Input Data Setup Time
tDW
0
100
80
Input Data Hold Time
tDH
10
Output Active from End of Write
tow
10
-
-
tTime required by a limit device to allow for the indicated function.
WRITE CYCLE (1):
t----twc---a.t
ADDRESS
DATA OUT
DATA IN
92cs-3e04e
WRITE CYCLE (2): OE = LOW
~--twc
---a.t
"I'_--:'__--:=~~:-;:::::---
ADDRESS _ _ _
tWR
DATA OUT
DATA
IN
NOTE: TIMING MEASUREMENTS
REFERENCE LEVEL·I.5V
92C$-35046
Fig. 3 - Write cycle timing waveforms.
410
CDM8118-2
10
10
UNITS
ns
General-Purposes Memories
CDM6116-1, CDM6116-2
DATA RETENTION CHARACTERISTICS at TA = 0 to 70°C; See Fig. 4.
LIMITS
CHARACTERISTIC
TEST CONDITIONS
ALL TYPES
MIN.
MAX.
CS ? Voo -0.2 V
2
-
CDM6116-1
Voo = 3 V, CS ? 2.8 V
-
50
CDM6116-2
VDO = 3 V,CS? 2.8 V
-
15
tCOR
See Fig. 4
0
tR
See Fig. 4
'tRC
-
Minimum Data Retention Voltage
VOR
Data Retention Quiescent Current
looDR
Chip Deselect to Data Retention Time
Recovery to Normal Operation Time
UNITS
V
JlA
ns
DATA RETENTION _
MODE
'tRC = Read Cycle Time
VOD
-4.5 V
1\
'COR-
I--
/
VOR?! 2 V
r-"*
SJh
*"--j
I, ,If ~ I!,s
'R
0
Cs>-V DR -02V
cs
*
4.5 V
~
1
92C5-35047
Fig, 4 - Low VOD data retention timing waveforms.
OPERATING AND HANDLING CONSIDERATIONS
Handling
All inputs and outputs of RCA CMOS devices have a
network tor electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Voo nor less than
Vss.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Voo or Vss, whichever is appropriate.
Output Short Circuits
Shorting of outputs to VOD, or Vss may damage CMOS
devices by exceeding the maximum device dissipation.
ORDERING INFORMATION
The RCA-CDM6116 family packages, and electrical options
are identified by suffix leiters indicated in the following
chart. When ordering a Memory/Microprocessor device, it
is important that the appropriate suffix letter be affixed to
the type number of the device.
Suffix Letter·
Package/Option
o
Dual-in-Line Side Brazed Ceramic
Dual-in-Line Plastic
E
Chip (When applicable)
H
Package/Option
Suffix Letter·
EVP Screening (Extra Value Program)
i.e. Burn-In - optional for 0, E
package types
X
Electrical Option (0 0 to 70 0 C
Temperature Range)
1 or 2
For example, a CDM6116 with electrical option 1, and in a
dual-in-line plastic package will be identified as the
CDM6116E1. A CDM6116E1 with EVP screening option will
be identified as the CDM6116E1X.
1.
2.
• Nomenclature Guide
J
Product
DeSignator
CDM
6116
I
Family
Code
E
T
Package
1
T
Electrical
Option
X
L
EVP (Optional)
411
•
RCA CMOS LSI Products
MWS5101DL2, MWS5101DL3, MWS5101E,-2, MWS5101EL3
A3
I
22
21
voo
A2
2
AI
AO
A5
3
4
5
AS
A7
6
7
Vss
OIl
8
9
14
13
003
OI3
002
001
OI2
10
"
20
1.9
A4
Rl'W
m
18
17
0.0.
16
004
15
OI4
12
CS2
TOP VIEW
92C$-29976RI
TERMINAL ASSIGNMENT
256· Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard pinout
• Very low operating current - 8 mA
at VDD = 5 V and cycle time = 1 /ls
• Two Chip-Select inputs - simple memory
expansion
• Memory retention for standby battery
voltage of 2 V min.
• Output-Disable for common I/O systems
• 3-State data output for bus-oriented
systems
• Separate data inputs and outputs
state when the Output Disable is at ~
level or when the chip is deselected by CS1
and/or CS2.
The RCA-MWS5101 is a 256-word by 4-bit
static random-access memory designed for
use in memory systems where high speed,
very low operating current, and simplicity in
use are desirable. It has separate data inputs
and outputs and utilizes a single power supply
of 4 to 6.5 volts.
The high noise immunity of the CMOS technology is preserved in this design. For TTL
interfacing at 5- V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input.
Two Chip-Select inputs are provided to simplify system expansion. An Output Disable
control provides Wire-OR capability and is
also useful in common Input/Output systems.
The Output Disable input allows t.hese RAMs
to be used in common data Input/Output systems by forcing the output into a highimpedance state during a write operation
independent of the Chip-Select input condition. The output assumes a high-impedance
For applications requiring wider temperature
and operating voltage ranges, the mechanically and functionally equivalent static RAM,
RCA-CDP1822, may be used.
The MWS5101 types are supplied in 22-lead
hermetic dual-in-line side-brazed ceramic
packages (0 suffix), in 22-lead dual-in-line
plastic packages (E suffix), and in chip form
(H suffix).
OPERATIONAL MODES
-INPUTS
MODE
READ
WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
Chip
Chip
Select 1 Select 2
CS,
CS2
0
0
1
0
1
0
0
1
X
X
X
0
1
X
X
X
1
LogiC 0
412
1
Output Read/
-Disable Write
00
R/W
c
Low
1
0
0
X
X
X
X
'C
OUTPUT
Read
Data
High
High
High
In
Impedance
Impedance
Impedance
Hlghlm~~
Don't Care
General-Purposes Memories
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE (Voo)
(All voltage referenced to Vss terminal) .......................................... ~.5 to -7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................... ~.5 to VDD + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A = -40 to +60· C (PACKAGE TYPE E) ......................................... 500
For T A = +60 to +85· C (PACKAGE TYPE E) .......... Derate Linearly at 12 mW/o C to 200
For T. = -55 to +100·C (PACKAGE TYPE D) ........................................ 500
For TA = +100 to +125·C (PACKAGE TYPE D) ....... Derate Linearly at 12 mWI"C to 200
mW
mW
mW
mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............. 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ...........................................................-55 to +125°C
PACKAGE TYPE E ............................................................ -40 to +85°C
STORAGE TEMPERATURE RANGE (T,•• ) .........................................-55 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ................... +265° C
OPERATING CONDITIONS at T A = Full Package-Temperature Range
For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
LIMITS
ALL TYPES
Min.
Max.
CHARACTERISTIC
DC Operating· Voltage Range
6.5
4
Input Voltage Range
UNITS
VSS
V
VOO
'---
STATIC ELECTRICAL CHARACTERISTICS at T A" 0 to 700 C, VDD = 5 V ± 5%.
TEST CONDITIONS
LIMITS
MWS5101D
UNITS
CHARACTERISTIC
MWS5101E
Vo
VIN
(V)
(V)
Min. TYD.- Max.
Quiescent Device
Current. 100
Output Voltage:
Low-Level,
L2 Types
L3 Types
VOL
High-Level,
VOH
Input Low Voltage,
VIL
Input High Voltage,
VIH
Output Low (Sink)
Current,
IOL
Output High (Source)
Current,
IOH
Input Current, •
liN
3·State Output
Leakage Current, * L2 Types
L3 Types
'OUT
Operating Current,
IOD1#
Input Capacitance,
CIN
Output Capacitance,
COUT
-
0,5
0,5
-
100
25
50
200
-
0,5
-
0
0.1
-
0,5
4.9
5
-
-
1.5
3.5
--
-
0.4
0,5
2
4
-
4.6
0,5
-1
-2
-
-
0,5
-
±5
05
0,5
05
0,5
-
-
+5
±5
IJ.A
-
0,5
4
5
10
8
mA
7.5
-
-
-
-
-
•
IJ.A
V
-
15
mA
pF
• TVPical values are for T A = 25"C and nominal VOO'
• All inputs in parallel.
*All outputs in parallel.
#
Outputs open-circuited; cycle time=l J.IS.
413
RCA CMOS LSI Products
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 0 to 70oC, VDD = 5 V
tr,tf = 20 ns, VIH = 0.7 VDD, VIL = 0.3 VDD. CL = 100 pF
LIMITS
MWS5101D. MWS5101E
CHARACTERISTIC
L2 Types
Min.t Typ.- Max.
Read Cycle Times (Fig. 1)
Read Cycle
250
tRC
Access from
Address
tAA
Output Valid from
Chip·Select 1
tDOAl
Output Valid from
Chip·Select 2
tDOA2
Output Active from
Output Disable
tDOA3
Output Hold from
20
Chip·Select 1
tDOHl
Output Hold from
20
tDOH2
Chip· Select 2
Output Hold from
20
Output [)isable
tDOH3
U
N
I
L3 Types
T
Min.t Typ~ Max. S
-
-
350
-
-
150
250
-
200
350
150
250
-
200
350
150
250
-
200
350
-
110
-
-
-
-
20
-
-
-
-
20
-
-
-
-
20
-
-
150 ns
t Time required by a limit device to allow for the indicated function.
- Typical values are for T A = 25 0 C and nominal VOO.
1 4 - - - - - - "RC------~
AO - A7
CHIP SELECT I
CHIP SELECT 2
OUTPUT DISA8LE
REAO/WRi'TE
1+-----tAA--~
OATA OUT
DATA OUT
HIGH
IMPEDANCE
,----"VA""L,,-,I0,--_-,
IM:~~~NCE
92CM- 30244R4
Fig. 1 - Read cycle timing waveforms.
414
± 5%,
General-Purposes Memories
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 0 to 70 0 C, VDD
tr,tf = 20 ns, VI H = 0.7 VDD, VI L = 0.3 VDD, CL = 100 pF
=5 V
± 5%,
LIMITS
MWS5101D, MWS5101E
CHA RACTE R ISTIC
L2 Types
Min.t Typ.- Max.
Write Cycle Times
Write Cycle
Address Setup
Write Recovery
Write Width
Input Data
Setup Time
Data In Hold
Chip·Select 1
Setup
Chip·Select 2
Setup
t
U
N
I
L3 Types
T
Min.t Typ.- Max. S
(Fig. 2)
twc
tAS
tWR
tWRW
lOS
tDH
tCs1S
tCS2S
-
-
200
-
-
-
50
-
-
-
150
-
-
-
-
150
-
-
110
40
150
-
-
400
150
50
200
150
-
-
40
-
110
110
300
-
-
ns
0
Chip·Select 1 Hold
tCS1H
0
Chip·Select 2 Hold
tCS2H
0
-
-
0
-
-
Output Disable
Setup
110
-
-
150
-
-
tODS
Time required by a limit device to allow for the indicated function.
= 25 0 C and nominal VOO.
- Typical values are for T A
1 " - - - - - - - 'WC
•
--------i~
AO-A7
'fS'H
CHIp-SELECT I
CHIP, SELECT 2
OUTPUT DISABLE
'os
011- 014
READI WRITE
DATA IN STABLE
---t------"',f---, WRW
~DON'TCARE
*
92CM- 30B04R4
'ODS IS REQUIRED FOR COMMON 110
OPERATION ONLY; FOR SEPARATE 110
OPERATIONS, OUTPUT DISABLE IS DON'T CARE
Fig. 2 - Write cycle timing waveforms.
415
RCA CMOS LSI Products
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
DATA RETENTION CHARACTERISTICS at TA = 0 to 70·C; See Fig. 3
-
TEST CONDITIONS
VDD
VDR
(V)
(Vi
CHARACTERISTIC
Minimum Data
Retention Voltage, VDR
Data Retention
L2 Types
Quiescent
L3
Types
Current, 100
Chip Deselect to Data
Retention Time,
Recovery to Normal
Operation Time,
UNITS
Max.
-
1.5
2
V
2
-
-
2
5
10
50
IlA
-
5
600
-
-
-
5
600
-
-
2
5
1
-
-
ns
tRC
VOO to VOR Rise and
Fall Time
tr,tf
• Typical values are for T A
Min.
-
-
tCOR
LIMITS
All Types
TVD.·
= 250 C and nominal
IlS
VOO'
92CS-30805RI
Fig. 3 - Low Voo data retention timing waveforms .
....:::>
i
!
I
I
WRITE
ADDRESS
DECODER
0
.
~
0
READ
ADDRESS
DECODER
V OD
92CS-27256R2
Fig. 4 - Memory ce/l configuration.
OPERATING AND HANDLING
CONSIDERATIONS
1. Handling
All inputs and outputs of RCA COS/MOS
devices haVe a network for electrostatic
Recom·
protection during handling.
mended handling practices for COS/MOS
devices are described in ICAN-6525,
"Guide to Better Handling and Operation
of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum
supply voltage. limit, care should be
taken to avoid or suppress power supply
turn-on and turn-off transients, power
supply ripple, or ground noise; any of
these conditions must not cause VOO-
416
VSS to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the inl'lut protec·
tion circuit, input signals should never be
greater than VDD nor less than VSS.
Input currents must not exceed 10 mA
even when the power supply is off.
Unused Inputs
A connection must be provided at every
input terminal. All unused input terminals must be connected to either VDD or
VSS, whichever is appropriate.
Output Short Circuits
Shorting of outputs to VOD or VSS may
damage COS/MOS devices by exceeding
the maximum device dissipation.
General-Purposes MemorIes
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
r ; : - - - - - - - - - - - - - - - - - - - - - - - - - - --1
I~
I
m21
AI
ROW
A2
DECODERS
I •
~v
I DO
I
A4
I
18.321
18.321
STORAGE
STORAGE
14)
1
I
Dr4
I
I
I
I
I
I
A5
I
1
*
R/W
CS~
CS2
1
I '--_ _...J
1
20
19
I
~Vss
I
I
I
I
17
OD~~18~1~.__________________________~
L ________________________ _
-----.-!
.+. f.
92CL- 3006!RI
OUTI~UT
INPUT PROTECTION
NETWORK
I
PROTf:CTION
CIRCUIT
Fig. 5 - Functional block diagram for MWS5101.
,.- - - -- - - - cONiRoL A l
c~~
~ 19T~
}
I
I
p-+----""
I
I
CS2
o
17L___
_
__
tHIP-SELECT
CONTROL
I
r-----'
,--- -
R~~O
--CONTRoLSI
: '
I=-=L
~
[=- =::: ::: :::----:~
~.JDI~[../
OUTPUT
I
I
}s
CHIP-SELECT
Lv-+
-r>rl}gUTPUT
DISASLE
CONTROL
L- _ _ _ _ _ _ _ _ _ _ ....J
III
a
R/Vi CONTROL
I
92CM-30064R2
Fig. 6 - Logic diagram of controls for MWS5101.
417
RCA CMOS LSI Products
MWS5101DL2, MWS5101DL3, MWS5101EL2, MWS5101EL3
:~
CO'ff,W02
e
~ BUSO-7
5
TFA
f"a-
MAO-7
.----
..-
MAO-?
MW.
•w
s,
S
MRD
~
•
,-----
MWR
l"-
MAO
,
0
CSi
ESi
C52
.
moMAO-?
M
~MRO
~~CSi
MAO-7
w
5
S
,
,
0
•,
--I
~
-"
l"-
iiiii
,
CSi
CS2
MRb
5
S
s
MAO-7
It-':,
jiiIIIl~,
•,
,
I"-
0
0
CSi
C~21--
C52
•
BUS 0-3
~
~
r-
MAO-7
W
0
MWR
~
BUS 0-3
~
MWR
,
L.MliO
t---'ESi ,
·-~CSi
CS2
,,
,
0
CS2
'---
MAO-?
MWR'!
w
S
BUS 4-7
•
~-1M
0
C52
~-
s
~
~
MWR
-
w
S
•,
r- CSi ,
L-t
MRo
0
CS2
'-----
~j(tcso
C
0
P
~
C5I
C52
C53
emEN '•
s
•
ffi
U2
I
m
92CL-34701
Fig. 7 - 4K byte Ram system using the CDP1858 and MWS5101.
92CS- 31568
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10- 3 inch).
The photographs and dimensions of each CMOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are S7" instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both
dimensions.
Dimensions and pad layout- for MSWS101.
418
General-Purposes Memories
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2, MWS5101AEL3
A2
2
22
21
AI
AO
A5
3
20
4
19
5
Ie
D.O.
6
7
B
9
10
II
17
16
15
14
13
12
004
OI4
003
0:I3
002
A3
AI;
A7
VSS
OI I
001
012
I
VOO
A4
Riw
m
CS2
TOP VIEW
92C$-29916RI
TERMINAL ASSIGNMENT
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard pinout
• Low operating current - 8 mA
at VDD=5 V and cycle time = 1,..s
• Two Chip-Select inputs - simple
memory expansion
• Memory retention for standby battery
voltage of 2 V min.
• TTL compatible
• Output-Disable for common /10
systems
• 3-state data output for bus-oriented
systems
• Separate data inputs and outputs
The RCA-MWS5101A is a 256-word by
4·bit static random-access memory
designed for use In memory systems
where high speed, very low operating current, and simplicity in use are desirable. It
has separate data Inputs and outputs and
utilizes a single power supply of 4 to 6.5
volts_
Two Chip-Select Inputs are provided to
simplify system expansion. An Output
Disable control provides Wire-OR
capability and Is also useful in common
Input/Output systems. The Output
Disable input allows 'hese RAM's to be
used In common data Input/Output
systems by forCing the output into a high-
impedance state during a write operation
independent of the Chip-Select input condition. The output assumes a highimpedance state when the Output Disable
is at high level .or when the chip is
deselected by CS1 and/or CS2.
For applications requiring CMOS compatibility over wider operating voltage and
temperature ranges, the mechanical and
functional equivalent RCA-CDP1822
statiC RAM may be used.
The MWS5101A types are supplied in
22-lead hermetic dual-in-line side-brazed
ceramic packages (0 suffix), in 22-lead
dual-in-line plastiC packages (E suffix),
and in chip form (H suffix).
I
OPERATIONAL MODES
MODE
READ
I WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
Logic 1
= High
~IP
Select 1
C§1
0
0
0
1
X
X
INPUTS
Output
Chip
Select 2 Disable
CS2
00
1
0
1
0
1
1
X
0
X
Logic 0
X
X
1
Low
Read/
Write
RIW
1
0
0
X
X
X
OUTPUT
Read
Data In
High Impedance
High_ Impedance
H~ Impedance
High Impedance
X
Don't Care
419
RCA CMOS LSI Products
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2,MWS5101AEL3
=
OPERATING CONDITIONS at TA Full Package·Temperature Range
For maximum reliability, operating conditions should be selected so that
operation is always within the following ranges'
LIMITS
UNITS
CHARACTERISTIC
ALL TYPES
Min.
Max.
4
6.5
DC Operating' Voltage Range
v
Input Voltage Range
Vee
Vss
MAXIMUM RATINGS, Absolute·Maximum Values:
DC SUPPLY-VOLTAGE RANGE (Voo)
(All voltage referenced to Vss terminal) ........................................... ~.5 to -7 V
INPUT VOLTAGE RANGE. ALL INPUTS ........................................ ~.5 to Voo + 0.5 V
DC INPUT CURRENT. ANY ONE INPUT ....••..•..••.•..•.....•.....••.••..•..........• ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ...•......•••••••.•...•..•.••.•.•••.••.••. 500 mW
For T. = +60 to +85·C (PACKAGE TYPE E) ........... Derate Linearly at 12 mW/·C to 200 mW
For T. = -55 to +100·C (PACKAGE TYPE D) ......................................... 500 mW
For T. = +100 to +125·C (PACKAGE TYPE D) ........ Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T.,= FULL PACKAGE-TEMPERATURE RANGE (All Package Types) •..•.•.•....•. 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE Type.p ............................................................-55 to +125·C
PACKAGE TYPE E ............................................................. -40 to +85·C
STORAGE TEMPERATURE RANGE (T... ) ..........................................'-65 to +150·0
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max.................... +265·0
STATIC ELECTRICAL CHARACTERISTICS at TA =0 to 70·C, VDP = 5 V
IMITS
TEST
UNITS
MWS5101AD
CONDITIONS
CHARACTERISTIC
MWS5101AE
Vo
VIN
(V)
(V)
Min. Typ.- Max.
25
5
50
Quiescent Device
L2Tvoes
jAA
200
0,5
L3Types
Current, 100
100
Output Voltage:
0.1
0, 5
0
Low-Level
VOl
V
,0,5
4.9
5
High-Level,
VOH
0.65
Input Low Voltage,
VIL
2.2
Input High Voltage,
VIH
butput Low (Sink)
2
4
0.4
0, 5
Current, .
IOL
rnA
Output High (Source)
4.6
0,5
-1
-2
Current,
IOH
0, 5
±5
Input Current,liN
3·State Output Leakage
jAA
±5
L2Tyoes
5
0,5
Current:
0,
5
L3Types 0, 5
±5
lOUT
rnA
8
0, 5
4
Operating Current,
1001#
7.5
5
Input Capacitance,
CIN
pF
15
10
Output Capacitance,
COUT
o
-
-
~
-
o
-
-Typical values are for TA = 25°C and nominal VDD.
4Allinputs in parallel.
"All outputs in parallel.
'Outputs open-clrcuited; cycle time = 1 '"'s.
420
General-Purposes Memories
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2, MWS5101AEL3
=
=
DYNAMIC ELECTRICAL CHARACTERISTICS at T A 0 to 70 ·C, VDD 5 V ± 5%,
tr,t, 20 na, CL == 50 pF and 1 TTL Load
LIMITS
MWS5101AD, MWS5101AE
CHARACTERISTIC
UNITS
L2 TVD.a
L3 TVD.a
I
Mln.t Typ.- Max. Mint Typ.- Max.
=
Read Cycle Times (Fig. 1)
Read Cycle
Access from Address
Output Valid from
Chip-Select 1
Output Valid from
Chip-Select 2
Output Active from
Output Oisable
Output Hold from
Chip-Select 1
Output HOld from
Chip-Select 2
Output Hold from
Output Oisable
tRC
tAA
tOOA1
tOOA2
tOOA3
tOOH1
tOOH2
tOOH3
-
-
200
350
200
350
200
350
-
150
20
-
-
-
20
-
-
-
20
-
-
-
-
-
150
250
150
250
-
150
250
-
-
110
20
-
-
20
-
20
-
250
350
-
ns
tTlme required by a limit device to allow for the Indlcatad function.
-Typical values are .for TA =25·C and nominal Vee.
-----'RC
AO -AT
I
CHIP SELECT I
CHIP SELECT,
OUTPUT DISABLE
READ/WRITE
DATA OUT
OATA OUT
HIGH
IMPEDANCE
,--.-:.;;;VA:::.;LI.:..D_--,
IM:~O~NCE
92CM- 30244R4
Fig. f - Read cycle timing waveforms.
421
RCA CMOS LSI.Products
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2, MWS5101AEL3
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 0 to 70 ·C, VDD = 5 V ± 5%,
tr,tf 20 ns, CL 50 pF and 1 TTL Load
LIMITS
MWS5101AD, MWS5101AE
CHARACTERISTIC
UNITS
L2 Types
L3 Types
Min.t Typ.- Max. I Mint Typ.- Max.
Write Cycle Times (Fig. 2)
Write Cycle
400
twc 300
Address Setup
150
tAS 110
Write Recovery
40
50
tWR
Write Width
200
tWRW 150
Input Data
150
200
ns
Setup Time
tDS
Data In Hold
40
50
tDH
{';nip-:select 1 Setup tCS1S 110
150
150
Chip-Select 2 Setup tCS2S 110
Chip-select 1 Hold tCS1H
0
0
Chip-Select 2 Hold tCS2H
0
0
Output Disable
110
150
Setup
tODS
=
=
-
-
-
hime required by a limit device to allow for the indicated function.
·Typical values are for TA 25·C and nominal VOO.
=
f o o t - - - - - - - ' W C -----~~
AO-A7
CHIp-SELECT I
CHIP- SELECT 2
OUTPUT 01 SABLE
011- 014
READIWRITE
~DON'TCARE
*
92CM-30B04R4
'ODS IS REQUIRED FOR COMMON 110
OPERATION ONLY; FOR SEPARATE I/O
OPERATIONS, OUTPUT DISABLE IS DON'T CARE·
Fig. 2 - Write cycle timing waveforms.
422
General-Purposes Memories
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2, MWS5101AEL3
DATA RETENTION CHARACTERISTICS at TA = 0 to 700 C· See Fig 3
TEST
CONDITIONS
VDR
VDD
CHARACTERISTIC
(V)
(V)
-
-
-
1.5
2
V
2
-
-
2
5
10
50
,.,.A
-
5
600
-
600
-
ns
5
-
2
5
1
-
-
,.,.s
Minimum Data
Retention Voltage,
VOR
Data Retention
L2Types
Quiescent
L3Types
Current, IDD
Chip Deselect to Data
Retention Time,
tCDR
Recovery to Normal
Operation Time,
tRC
VDD to VDR Rise and
Fall Time
tr,tf
"Typical values are for TA =25 ·C.
VDD
r
oATA
RETENTION~
MODE
-""---~095Voo
r'f
'CoR
CSz
""Viii\;
LIMITS
All Types
UNITS
Min. Typ'- Max.
11
095Voo 1 , - - - -
VDR
I
I,
---1
'RC
I fViH
¥
VIL\l.
V1L
9ZCS·30a05RI
Fig. 3 - Low Vee data retention timing waveforms.
I
>::>
i
I
WRITE
ADDRESS
DECODER
0
-
---+___1-CS2
0---'-'--+---
1--RI'ij
20
CONTROL
I
I
-
-
-
CONTRoL B I
I
I
-
-
-
»-----_-+:. }gH~-SELECT6
-
-
-
R/W CONTROL
I}COUTPUT
I
.-
DISABLE
CONTROL
-'
92CM-30064R2
Fig. 6 - Logic diagram of controls for MWS5101A.
424
General-Purposes Memories
MWS5101ADL2, MWS5101ADL3, MWS5101AEL2, MWS5101AEL3
------------------------------nCL-34702.
Fig. 7 - 4K byte RAM system using the CDP1858 and MWS5101A.
I
135
3.429)
92CS-31568
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimen·
sions as Indicated. Grid graduations are in
mils (10 - 3 Inch).
The photographs and dimensions of each
CMOS chip represent a chip when it is part of
the wafer. When the wafer is cut into chips,
the cleavage angles are 57° instead of 90°
with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0. 17mm)
larger in both dimensions.
Dimensions and pad layout for MWS5101AH.
425
RCA CMOS LSI Products
MWS5114-1, MWS5114-2, MWSS114-3
CMOS
A6
I
AO
5
Ie
Voo
16
Ae
15
A9
14
1/01
AI
6
13
1/02
A2
7
12
1/03
cs
e
II
Vss
9
10
'-----'
I/~
WE
92CS- 3D982Rt
TERMINAL
ASSIGNMENT
1024-Word by 4-Bit
LSI Static RAM
Fealures:
• Fully static operation
• Industry standard 1024 x 4 pinout (same as pinouts for 6514, 2114,
9114, and 4045 types)
• Common data input and output
• Memory retention for stand-by battery voltage as low as 2 V min.
• All inputs and outputs directly TTL compatible
• 3-state outputs
• Low standby and operating power
The RCA-MWS5114 is a 1024-word by 4-bit static randomaccess memory that uses the RCA ion-implanted silicon
gate complementary MOS (CMOS) technology. It is designed for use in memory systems where low power and
simplicity in use are desirable. This type has common data
input and data output and utilizes a single power supply of
4.5 V to 6.5 V.
The MWS5114 is supplied in 18-lead, hermetic, dual-in-line
side-brazed ceramic packages (0 suffix) and in 18-lead
dual-in-line plastic packages (E suffix).
A4-------{~~--1
A5 ------j"::L:::J
A6
A7
Ae
MEMORY ARRAY
64 ROWS
64 COLUMNS
----IIX::::I
----IIX::::I
----IIX::::I
A9------{l=t-__~
OPERATIONAL MODES
1/01==~~:=~~~~~m
FUNCTION
1/0, -_+++-II>--l
CS
WE
DATA PINS
Read
0
1
Output:
Dependent
on data
Write
0
0
Input
X
HighImpedance
1/02 ---.++-II>--l
I/~ --rl-t++-II>--l
Not
Selected
ENABLE
92CS-30980RI
Fig. 1 - Functional block diagram for MWS5114
426
1
General-Purposes Memories
MWS5114-1, MWS5114-2, MWS5114-3
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE RANGE, (Voo)
(Voltages referenced to Vss Terminal ........................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................................................ ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60° C (PACKAGE TYPE E) ....................................................................... 500 mW
For·TA = +60 to +85°C (PACKAGE TYPE E) ...................................... Derate Linearly at 12 mW/o C to 200mW
ForTA = -55 to +100°C (PACKAGE TYPE D) ...................................................................... 500 mW
For TA =+100 to +125° C (PACKAGE TYPE D) ................................... Derate Linearly at 12 mW/" C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ....................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA ):
PACKAGE TYPE D .......................................................................................... -55 to +125° C
PACKAGE TYPE E ........................................................................................... -40 to +85° C
STORAGE TEMPERATURE RANGE (Tstg ) •.••••••••••••..••..••••.•••.•..•..••.•...•..••••.•••.••••.•.•••.••. -65 to +150° C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for lOs max ............................................. +265° C
OPERATING CONDITIONS at TA = -40 0 C to +85 0 C
For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CHARACTERISTIC
DC Operating-Voltage Range
Input Voltage Range
UNITS
Max.
6.5
VDD
Min.
4.5
Vss
V
STATIC ELECTRICAL CHARACTERISTICS at TA = 0 to +70· C, Voo ±5%, Except as noted
LIMITS
CONDITIONS
CHARACTERISTIC
MWS 5114-3
MWS 5114-2
MWS 5114-1
UNITS
Vo
VIN
Voo
(V)
(V)
(V)
Quiescent Device
Current
'100 Max.
-
0,5
5
Output Voltage
Low Level VOL Max.
-
0,5
High Level VOH Min.
-
0,5
Input Voltage
Low Level VIL Max.
0.5,4.5
-
5
-
1.2
0.8
-
1.2
0.8
-
1.2
0.8
High Level VIH Min.
0.5,4.5
-
5
2.4
-
-
2.4
-
-
2.4
-
-
0.4
0,5
5
2
4
-
2
4
-
2
4
-
4.6
0,5
5
-0.4
-1
-
-0.4
-1
-
-0.4
-1
-
-
0,5
5
-
±0.1
±5
-
±0.1
±5
-
±0.1
±5
3-State Output Leakage
Current
lOUT
0,5
0,5
5
-
±0.5
±5
-
±0.5
±5
-
±0.5
±5
Operating Device
Current
100'#
-
0,5
5
-
4
8
-
4
8
-
4
8
-
-
-
-
5
7.5
-
5
7.5
-
5
7.5
-
-
-
-
10
15
-
10
15
-
10
15
Output Current
(Sink)
IOL Min.
(Source)
IOH Max.
Input Current
liN Max."
.
Input CapaCitance
CIN
MIN.
TYP.'
MAX.
-
75
100
5
-
a
5
4.9
5
MIN.
TYP.'
MAX.
-
75
100
0.1
-
0
-
4.9
5
MIN.
TYP.'
MAX.
-
75
250
0.1
-
a
0.1
-
4.9
5
-
/-LA
•
V
mA
/-LA
mA
pF
Output Capacitance
CaUT
"Typical values are for TA = 25° C and nominal Vee.
AAII inputs in parallel.
#Outputs open circuited; cycle time = 1 /-Ls.
• All outputs in parallel.
427
RCA CMOS LSI Products
MWS5114-1, MWS5114-2: MWS5114-3
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =0 to ~70o C,
Voo = 5 V ±5%,
Input Ut = 10 ns; CL = 50 pF and 1 TTL Load
LIMITS
MWS5114·2
UNITS
I MW$ 5114·1
MIN.tITYP:IMAX.1 MIN.tITYP:1 MAX.IMIN.tITYP:1 MAX.
MWS 5114-3
CHARACTERISTIC
I
Read Cycle times See Fig. 2
Read Cycle
fRc
200
160
-
250
200
-
300
250
-
Access
fAA
-
160
200
-
200
250
-
250
300
Chip Selection to Output Valid
teo
-
110
150
-
150
200
-
200
250
Chip Selection to Output Active
tex
20
100
-
20
100
-
20
100
-
Output 3-state from Deselection
toTO
-
75
125
-
75
125
-
75
125
Output Hold from Address Change
toHA
50
100
-
50
100
-
50
100
-
ns
t
Time required by a limit device to allow for the Indicated function.
·Typlcal values are for TA = 25° C and nominal VDD.
~
'RC
'AA
-I -,
ADORESS::i
es
Dour
t
i
I
- ( tOTO
'ex
92CS-'III5RI
NOTE'
Wl IS HIGH DURING THE READ CYCLE.
TIMING MEASUREMENT REF. LEVEL IS 1.5 V
Fig. 2 - Read cycle waveforms.
428
General-Purposes Memories
MWSS114-1, MWSS114-2, MWSS114-3
OYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input t"t, =10 n8; CL =50 pF and 1 TTL Load
=0 to +70· C,
Voo
=5V ±5%,
LIMITS
CHARACTERISTIC
MWS 5114-3
I
I
1
1
MWS 5114-2
MWS 5114-1
I
I
UNITS
I
MIN.t TYP: MAX.' MIN·t LTYP:J MAX. MIN.t TYP: MAX.
Wnte Cycle TImes See FIg. 3
Write Cycle
twe
200
160
-
250
200
-
300
220
-
tw
125
100
-
150
120
-
200
140
-
tWA
50
40
-
50
40
-
50
40
-
0
0
-
0
0
-
0
0
-
25
20
-
50
40
-
50
40
-
75
50
-
75
50
-
75
50
-
30
10
-
30
10
-
30
10
-
Write
Write Release
Address To Chip Select
Set-Up Time
tACS
Address To Write
Set-up Time
tAW
Data to Write
Set-up Time
tosu
Data Hold From Write
t
tOH
ns
Time required by a limit device to allow for the indicated function.
"Typical values are for TA = 25° C and nominal Voo.
I
4='--------------=1'
~.~. Lt
ADDRESS
X,.---
-V
r--'
WR
_
""1---'w
-----'
'/WI
92CM-34394
NOTE: WE IS LOW DURING THE WRITE CYCLE
TIMING MEASUREMENT REF. LEVEL IS 1.5 V
Fig. 3 - Write cycle waveforms.
429
RCA CMOS LSI Products
MWSS114-1, MWSS114-2, MWSS114-3
DATA RETENTION CHARACTERISTICS atTA = 0 to 700 C; See Fig. 4.
CHARACTERISTIC
TEST
LIMitS
CONDITIONS
ALL TYPES
(V)
VDR
Minimum Data
Retention Voltage
VOR
Data Retention Quiescent
Current, 100
VDD
teOR
TYP,·
MAX,
-
-
25
50
-
2
2
-
-
25
50
60
125
5
300
-
-
MWS5114-1
Chip Deselect to Data
Retention Time,
UNITS
MIN.
-
MWS 5114-3
MWS 5114-2
(V)
-
V
#J.A
ns
Recovery to Normal
Operation Time,
lAc
Voo to VOR Rise and
Fall Time
t,., tf
• Typical values are for l'A
-
5
300
-
-
2
5
1
-
-
; 25° C and nominal Voo.
DATA RETENTION
MODE
VCR
92CS- 31114RI
Fig. 4 - Low Voo data retention timing waveforms.
430
ps
General-Purposes Memories
MWS5114-1, MWS5114-2, MWS5114-3
I
CPU/ROM SYSTEM
...£!JL
CDPI802
-'!!!!!.
COPI833
RAM I NTERFACE
I
I
LATCH AND DECODE I,
CDPI866
RAM SYSTEM
I
~
MWS5114(2)
92CM-34700
Fig. 5 - MWS5114 (IK" 4) minimum system (IK" 8).
OP£RATING AND HANDLING
CONSIDERATIONS
1. Handling
All. inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525, "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to.avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, orground noise; any of these conditions must not
cause Voo-Vss to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Voo nor less than
Vss. Input currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Voo or Vss , whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may damage CMOS
devices by exceeding the maximum device dissipation.
431
I
General-Purposes Memories
R'CA CMOS LSI Products
MWS5114-1, MWS5114-2, MWS5114-3
142
175-183
(4.445-4.648)
Dimensions end pad layout for MWS5114H
Dimensions in parentheses are in millimeters and are derived from
the basio inoh dimensions as indioated. Grid graduations are in
mils (10- 3 inoh).
ORDERING INFORMATION
RCA Memorydevice packages are identified by letters indicated in
the following chart. When ordering a Memorydevice, it is important
that the appropriate suffix leiter be affixed to the type number of the
device.
Package
Suffix Letter
Dual-in-Line Side-Brazed Ceramic
0
Dual-in-Line Plastic
E
H
Chip
For example, a MWS5114-3 in a dual-in-line plastiC package will be
identified as the MWS5114E-3.
432
The photographs and dimensions represent a ohip when it is part
of the wafer. When the wafer is out into chips. the cleavage angles
are 57° instead of 90° with respect to the face of the chip.
Therefore. the isolated chip is actually 7 mils (0.17 mm) larger in
both dimensions.
680S-Series LSI Products
Technical Data
433
RCA CMOS LSI Products
CDP65516
Objective Data
AQO
18
Vee
AQ.
17
G
AQ2
IS
CMOS 2048-Word X 8-Bit Static
Read-Only Memory
Features
AQ'
AQ4
4
15
M
5
14
5
AQ5
6
13
E
AIO
AQ6
12
AQ7
II
A9
VSS
10
A8
• Pins 13. 14. 16. and 17 are mask programmable
• 2K x 8 CMOS ROM
• 3 to 6 volt supply
• MOTEL mask option also insures direct
compatibility with many NMOS
• Access time
430 ns (5 V) CDP65516-43
microprocessors
550 ns (5 V) CDP65516-55
• Standard 18-pin package
• Low power dissipation
15 mA maximum(active)
30llA maximum (standby)
• Directly compatible with muxed bus
CMOS microprocessors
TOP VIEW
12e8-55111
TERMINAL ASSIGNMENT
The CDP65516 is a complementary MOS mask programmable byte organized read-only memory (ROM). The
CDP65516Is organized as 2048 bytes of 8 bits. designed for
use in multiplex bus systems. It is fabricated using silicon
gate CMOS technology. which offers low-power operation
from a single 5-volt supply.
The memory is compatible with CMOS microprocessors
that share address and data lines. Compatibility is enhanced
by pins 13. 14. 16. and 17 which give the user the versatility
of selecting the active levels of each. Pin 17 allows the user
to choose active high. active low or a third option of
programming which is termed the "MOTEL" mode. If this
mode is selected by the user. it provides direct compatibility
with the CDP6805E2 type microprocessor series. In the
MOTEL operation the ROM can accept either polarity
signal on the data strobe input as long as the signal toggles
during the cycle. This'unique operational feature makes the
ROM an extremely versatile part.
AOO-AQ7
PIN NAMES
AOO-A07 ............. Address/Data Output
A8-A10 ................................. Address
M .................. Multiplex Address Strobe
E..................................... Chip Enable
S ......................... : ........... Chip Select
G ............... Data Strobe (Output Enable)
M---------------.
S Disables
Output Buffers
E. E Limit
Power Dissipation
ROM Array
!128x 128)
Fig. 1 - Block diagram.
434
6805-Serles LSI Products
CDP65516
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Supply Voltage
Vlllue
Unit
VCC
-0.3 to +7
Input Voltage
Vin
-0.3 to +7
V
V
Operating Temperature Range
TA
Oto+70
·C
Storage Temperature Range
-66 to + 150
·C
Tst!!
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restncted to
RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS ANO CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted.!
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Supply Voltage
(VCC must be applied at least 100,.5 before proper device operation is achieved)
Parameter
VCC
4.5
Input High Voltage
VIH
VCC-2
Input low Voltage
Vil
-0.3
RECOMMENDED OPERATING CHARACTERISTICS
CDP85516-48
Characteriltic
Symbol
CDpt5511-55
Nom
MIIx
.Unit
5.5
V
5
-
-
5.5
V
0.8
V
Teet COndition
Unit
'Min
Max
Min
Max
VOH
VCC-O.4 V
-
VCC-0.4 V
-
V
VOL
-
0.4
-
0.4
V
Supply Current (Operating)
ICCl
-
15
-
15
mA
Supply Current (DC Active)
ICC2
100
,.A
IISB
-
Viil=VCC to ~NO
Standby Current
30
-
CL = 130 pF, Vin = VIH to VIL
!eyc= 1 p.S
50
p.A
Vin=VCC to GNO
Input Leakage
lin
-Hi
;1"10
-10
+10
,.A
Output leakage
IOl
-10
+10
-10
+10
,.A
Output High Voltage
Source Current - 1.6 mA
Output low Voltage
Sink Current + 1.6 mA
100
CAPACITANCE (f= 1 MHz, TA=25"C periodically sampled rather than 100% tested.)
Characteristic ..
Symbol
MIX
Unit
Cin
5
pF
Cout
12.5
pF
Input Capacitance
Output Capacitance
I
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted ..
READ CYCLE
CL= 130 pF
Parameter
Symbol
CDPl5516-43
MIn
Max
-
Address Strobe Access Time
tMLOV
Read Cycle Time
tMHMH
Multiplex Address Strobe High to Multiplex Address Strobe Low (Pulse Width)
tMHML
150
Data Strobe Low to Multiplex Address Strobe Low
tGLML
50
Multiplex Address Strobe Low to Data Strobe High
tMLGH
100
Address Valid to Multiplex Address Strobe Low
tAVML
50
Chip Select Low to Multiplex Address Strobe Low
tSLML
50.
Multiplex Address Strobe Low to Chip Select High
tMLSH
tELML
tEHML
50
50
50
Multiplex Address Strobe Low to Address Don't Care
tMLAX
50
Data Strobe High to Data Valid
tGHOV
175
Data Strobe Low to High-Z
tGLDZ
Chip Enable Low/High to Multiplex Address Strobe Low
. 430
CDpt551W1 Unit
Min
-
j 750'
-
-
-
--
160
Max
550
1000
175
50
160
50
50
00
50
50
00
200
-
-
--
ns
ns
ns
ns
ns
ns
ns
os
ns
-
ns
160
ns
-
ns
435
RCA CMOS LSI Products
CDP65516
1+--------- tMHMH (Read Cycle T i m e l - - - - - . . . . . : - - - - - . t
VIH
M
o.S V
Vil
VIH
Vil
VIH
E and
Select Mode
Deselect Mode
E
Vil
VIH
Vil
AS to AIO
High Z -VOH
AOO to A07
-Val
~-+-----lMlDV----------~
Fig. 2 - Read cycle timing waveforms.
Functional Description
The 2K x 8 bit CMOS ROM (COP65516) shares address and
data lines and. therefore. is compatible with the majority of
CMOS microprocessors in the industry. The package size is
reduced from 24 pins for standard NMOS ROMs to 18 pins
because of the multiplexed bus approach. The savings in
package size and external bus lines adds up to tighter board
packing density which is handy for battery-powered handcarried CMOS Systems. This ROM is designed with the
intention of having very low active as well as standby
. currents. Theactive power dissipation of75 mW (atVcc=5 V.
freq.=1 MHz) and standby power of 150pW (atVcc=5 V) add
up to low power for battery operation. The typical access
time of the ROM is 280 ns making it acceptable for operation
with today's existing CMOS microprocessors.
An example of this operation is shown in Fig. 3. Shown is a
typical connection with the C0P6805E2 CMPS microprocessor. The main difference between this system and
competitive process is that the data strobe (OS) on the
C0P6805E2 and the read bar (Ao) on the competitive
process both control the output of data from the ROM but
. are of opposite polarity. The 2K x 8 ROM can accept either
polarity signal on the data strobe input as long as the signal
toggles during the cycle. This is termed the MOTEL mode of
operation. This unique operational feature makes the ROM
an extremely versatile part. Further operational features are
explained in the following section.
Operational F..turet .
In order to operate in a multiplexed bus system the ROM
latches. for one cycle. the address and chip-select input
information on the traili ng edge of address strobe (M) so the
address signals can be taken off the bus.
Since they are latched. the address and chip-select signals
have a setup and hold time referenced to the negative edge
of address strobe. Address strobe has a minimum pulse
436
width requirement since the circuit is internaily precharged
during this time and is set up for the next cycle on the
trailing edge of address strobe. Access time is measured
from the negative edge of address strobe.
The part is equipped with a data strobe input (G) which
controls the output of data onto the bus lines after the
addresses are off the bus. The data strobe has three
potential modes of operation which are programmable with
the ROM array. The first mode is termed the MOTEL mode
of operation. In this mode. the circuit can work with either
the 6805 or 8085 type microprocessor series. The difference
between the two series for a ROM peripheral is only the
polarity of the data-strobe signal. Therefore. in the MOTEL
mode the ROM recognizes the state of the data-strobe
Signal at the trailing edge of address strobe (requires a
setup and hold time). latches the state into the circuit after
address strobe. and turns on the data outputs when an
oppOSite polarity signal appears on the data-strobe input. In
this manner the data-strobe input can work with either
polarity signal but that signal must toggle during a cycle to
output data on the bus lines. If the data strobe remains at a
dc level the outputs will remain off. The data-strobe input
has two other programmable modes of operation and those
are the standard static select modes (high or low) where a
dc input not synchronous with the address strobe will turn
the output on or off.
The chip-enable and chip-select inputs are all programmable
with the ROM array to either a high or low select. The chip
select acts as an additional address and is latched on the
address-strobe trailing edge. On deselect the chip select
merely turns off the output drivers acting as an output
disable. It does not power down the chip. The chip-enable
inputs. however. do put the chip in a power down standby
mode but they are not latched with address strobe and must
be maintained in a dc state for a full cycle.
680S-Serles LSI Products
CDP65516
rna Microprocessor
LI
CDP6805E2
High Order Address Bus (5)
Bus Control Signals (3)
Fig. 3 - Typical minimum system.
Introduction
and display time. using an optional CDP6818 Real-Time
Clock (RTC). and routines to punch and load an optional
cassette interface. Fig. 2 shows a minimum system which
only requires the MPU. ROM. keypad inputs and display
output interfaces. Port A of the CDP6805E2 MPU is required
for the I/O; however. Port B and all other CDP6S05E2 MPU
features remain available to the user. A possible expanded
system is shown in Fig. 3.
CBUG05 is a debug monitor program written for the
CDP6805E2 Microprocessor Unit and contained in the
CDP65516 2K x 8 CMOS ROM. CBUG05 allows for rapid
development and evaluation of hardware and 6805 Family
type software. using memory and register examine/change
commands as well as breakpoint and single instruction
trace commands. CBUG05 also includes software to set
COP65516
CDP6805E?
L
BO-87
8
5
A8 - AI2
L'
AS,DS,R/W
ADO-A07
AB-AI2
M, DE, CE
6 ••
KEYPAD
CDP1873
PA4-PA6
,
A,B,C
/6
06
•
PAO- PA3
PA6-PA7
3
QI
TO
,
2
DATA
B.
CLOCk
FP
/
I
.
ROWS
COLUMNS
SP
, /12
LCD
FP
t2CM- a5118
Fig. 4 - Minimum CBUG05 system.
437
I
RCA CMOS LSI Products
CDP65516
~~PRO-PI~FOR
....---,....
USER
TIM
CASSETTE
READ
I-"-'RON CASSETTE
RECORDER
INTERFACE
I
IRQ
FOR USER
RESET
~FRON
USER HARDWARE
A8- AI2, AS,DS,R/W
V
\1
CDPS818
REAL-TIME
CLOCK
CDPS5516
ROM
CDP6805E2
MPU
k:
~
ADDRESS
DECODE
CDM5332
CDMSIIS
ADDmONAL
MEMORY
~
it
COP 1873
H08
DECODER
~
S.4
KEYPAD
ROWS
COLUMNS
I
~.
PAO-PA3
i'--r
PA7
I--
8O-B7
~
PAS
~
V
.....
DATA
CLOCK
BPI-BP4
.>
:>
:::FPI-FPI2
...
,-
LCD
CASSETTE
WRITE
INTERFACE
t----
10 CASSETTE
RECORDER
\
92CL-35117
Fig. 5 - Expanded CBUG05 system.
438
ADDITIONAL
PERIPHERALS
680S-Serles LSI Products
CDP65516
DATA PROGRAMMING INSTRUCTIONS
3. Master Deylce - a ROM, PROM, or EPROM that
When a customer submits instructions for programming
contains the required programming information.
RCA custom ROM s, the customer must also complete the
relevant parts of the ROM information sheet and submit this
The requirements for each method are explained In detail in
sheet together with the programming instructions. Programming
the following paragraphs:
instructions may be submitted in anyone of three ways, as
COMPUTER-CARD METHOD
follows:
1. Computer-Card Deck-use standard aO-column comUse standard aO-column computer cards. Each card deck
puter punch cards.
must contain, in order, a title card, an option card, a data2. Floppy Diskette-diskette information must be genformat card, and data cards. Punch the cards as specified in
erated on an RCA CDPlaOO-series microprocessor
the following charts:
development system.
TITLE CARD
Column No.
Data
1
Punch T
2-5
leave blank
6-30
Customer Name (start at 6)
31-34
leave blank
35-54
Customer Address or Division (start at 35)
55-58
leave blank
59-63
RCA custom selection number (5 digits) (Obtained from RCA Sales Office)
64
leave blank
65-71
RCA device type, without COPS prefix, e.g., 5516
72
Punch an opening parenthesis (
73
Punch 8
74
Punch a closing parenthesis)
75-78
leave blank
79-80
Punch a 2-digit decimal number to indicate the deck number;
the first deck should be numbered 01
OPTION CARD
Use the ROM Information Sheet to select the polari!y options, P, N, or X, for the desired ROM type.
Column No.
Data
1-6
Punch the word OPTION
7
leave blank
8-17
RCA device type, including COPS prefix, e.g., CDPS5516
18-27
leave blank
28-31
Punch P or N per ROM Information Sheet
32-78
leave blank
79-80
Punch the deck number (the 2-digit number in
I
columns 79-80 of the title card)
DATA-FORMAT CARD
'The data-format card specifies the form in which the data is to be entered into ROM.
Column No.
Data
1-11
Punch the words DATA FORMAT
12
leave blank
13-15
Punch the letters HEX
16
leave blank
17-19
Punch POS
20-78
leave blank
79-80
Punch the deck number (the 2-digit number in
columns 79-80 of the title card)
439
RCA CMOS LSI Products
CDP65516
DATA PROGRAMMING INSTRUCTIONS (Cont'd)
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Data
Column No.
Data
1-4
Punch the starting address
26-27
2 hex digits of 9th WORD
2 hex digits of 10th WORD
in hexadecimal for the
28-29
following data:
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
6-7
2 hex digits of 1st WORD
33-34
2 hex digits of 12th WORD
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
2 hex digits of 4th WORD
40
Blank
15
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43~44
2 hex digits of 16th WORD
18-19
2 hex digits of 6th WORD
45
Semicolon, blank if last card
20
Blank
21-22
2 hex digits of 7th WORD
46-78
Blank
23-24
2 hex digits of 8th WORD
79-80
Punch 2 decimal digits
25
Blank
as in title card
·The address block must be contiguous starting at an even-numbered address.
Column 4 must be zero.
OPTION DATA CARD
12341'1"'0111213141S1"7U1'~21HHNHaVHHU31UUUU~»HH~41UU~UQUQQ"51UU~""UH"""U"MeH~"n~nnn~nnnnn~
OP
Rr
,~U
I'
0
£ x MP L £
COP"'I.
10
PO
11II
9
,113
A r
HiX
.. ,.
IRCA
55
i'/VL
!'f'!lX
PaS
.<2:22
3333
44H 5'55
AAA
B88B
ecce
~5.7
f9AS
c
OEIF
00
¢ Il"
1111
e fii';
t:E
F
(1yJO;
+5.1
F9A 8
C DE";
£
999 9 r 5'
/
"
(?J
P
I
Ii
I
I
¢ I
OBTAIN FROM
RCA SALES
t1 I
~ I
;:>
OECKNUMBER
(OPTIONAL)
1134"""011'11SU111"71.,.e21aU"UU~nHH~UHMnH~HH~~aU"".~QOH"U"M"n.7HnM~U"M"H~hn~nn"N"""nN"
440
680S-Serles LSI Products
CDP65516
ROM INFORMATION SHEET
OPTION LIST
Select the options for your ROM from the following list. A manufacturing mask will be generated from this
information. Select one in each section ..
PROGRAMMABLE PIN OPTIONS
13 (8)
Pin Number
14 (M)
16 (E)
17 (G)
Active High (1 or P)
0
0
0
0
Active Low (1 or P)
0
0
0
0
0
MOTEL (X)
28
29
30
31
Column Number
( On Option Card)
CUSTOMER INFORMATION
Customer Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ _ _ _ _ _State'_ _ _ _ _ _ _ _ _ _ _ _ _Phone (
Zlp_ _ _-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ __
Contact Ms.lMr. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CustomerPartNo. ______________________________________
PATTERN MEDIA
o
o
o
EPROM
Card Deck
Other·
·Other media require factory approval.
Signature _____________________________________________
Title ______________________________________________
OPERATING AND HANDLING CONSIDERATIONS
Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525 "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absolute maximum
rating.
1.
Input Signal.
To prevent damage to the input protection circuit, input
signals should never be greater than Vcc nor less than
Vss. Input currents must not exceed 10 mA even when
the power supply is off.
Unu.ed Input.
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Vce or Vss, whichever is appropriate.
Output Short Clrcultl
Shorting of outputs to Voo, Vec, or Vss may damage
CMOS devices by exceeding the maximum device
dissipation.
441
RCA CMOS LSI Products
CDP6805E2
Objective Data
CMOS 8-Bit Microprocessor
I
Voo
OSCI
os
2
3
4
TIMER
R'W
AS
5
6
PA7
PA6
7
8
PBO
PBI
PB2
PB3
LZ
P"
PA.
PA'
PA2
PAl
PAD
AI2
All
AID
9
10
P8'
12
31
30
29
13
28
"
Hardware Features
a Typical full speed operating power of 35 mW @ 5 V
a Typical WAIT mode power of 5 mW
a Typical STOP mode power of 25 pW
OSC2
27
"15
26
25
A9
A8
16
17
18
19
Vss
20
2.
23
22
21
PB5
PB.
PB7
80
BI
B2
B3
B.
B.
B.
B7
TOP VIEW
92'C$-1511&
TERMINAL ASSIGNMENT
a 112 bytes of on-chip RAM
a 16 bidirectional I/O lines
a InternalB-bit timer with software programmable 7-bit
prescaler
a External timer input
a Full external and timer interrupts
a Multiplexed address/data bus
a Master reset and power-on reset
a Capeble of addressing up to BK bytes of external memory
a Single 3- to 6-volt supply
a On-Chip oscillator
a 40-pin dual-in-line package
The CDP6805E2 Microprocessor Unit (MPU) belongs to the
CDP6805 Family of Microcomputers. This 8-bit fully static and
expandable microprocessor contains a CPU, on-chip RAM, I/O,
and TIMER. It is a low-power, low-cost processor designed for
low-end to mid-range applications in the consumer, automotive,
industrial, and communications markets where very low power
consumption constitutes an important factor. The following are
the major features of the CDP6805E2 MPU.
Software Features
a Similar to the MC6BOO
a Efficient use of program space
a Versatile interrupt handling
a True bit manipulation
a Addressing modes with indexed addressing for tables
a Efficient instruction set
a Memory mapped I/O
a Two power saving standby modes
LI
TIMER
PAO
PAl
PA2
Port
A
PA3
Port
A
Reg
Data
8
a"
CPU
Control
Index
Register
Reg
Bl
Mux
Bus
Drive
B2
X
B3
/ CondItion
Code
5 Register CC
B4
8
110
Lanes
BO
Accumulator
A
Data
Bus
B5
CPU
B6
Stack
6
MultIplexed
Address!
POinter SP
B7
rogram
PBO
PBl
Port
B
110
Lines
PB2
PB3
Port
B
Reg
Data
air
Counter
High PCH
Program
Counter
Low PCL
19
ALU
Address
Dnve
18
17
16
Reg
15
PB4
A8
A9
Al0
Address
Bus
All
A12
PB5
PB6
PB7
112 x B
RAM
Fig, 1 - Block diagram.
442
Bus
Control
AS
Address Strobe
as
Data Strobe (4;12)
R/W
Read/Wnte
6aOS-Serles LSI Products
CDP6805E2
MAXIMUM RATINGS (voltages referenced to VSS)
Ratings
Supply Voltage
All Input Voltages Except OSC1
Current Orain Per Pin Excluding VOD and VSS
Symbol
Value
Unit
VOO
-0.3 to +8.0
V
Yin
VSS-0.5 to VOO+0.5
V
I
10
mA
h
Operating Temperature Range
COP6805E2
COP6B05E2C
toTH
o to 70
TA
·C
-40 to 85
Storage 'Temperature Range
-55 to +150
Tst9
·C
DC ELECTRICAL CHARACTERISTICS 3.0 V 1VOO=3 0 Vdc, VSS =0, TA= A· to 70°C, unless otherwise noted)
Symbol
Min
Max
VOL
VOH
-
0.1
VOO-O.l
-
-
1.3
mA
iJ:llL
200
I'A
100
-
100
I'A
(iLOAO=O.25 mAl A8-A12,BO-B7
VOH
2.7
-
V
IiLOAO=Ol mAl PAQ-PA7, PBO-PB7
VOH
2.7
IiLOAO=0.25 mAl OS, AS, R/W
'{QH
2.7
-
V
0LOAO=0.25 mAl A8-A12, BO-B7
VOL
V
VOL
-
0.3
IILOAO=0.25 mAl PAO-PAl, PBO-PB7
0.3
V
VOL
-
0.3
V
Characteristics
Output Voltage ILOAO,,10.0 p.A
Unit
V
Total Supply Current ICL=50 pF - no OC loads) tcyc=5l's
Run IVIL=0.2 V, VIH=VOO-0.2 VI
Walt lTest Conditions - See Note Belowl
Stop IT est Conditions - See Note Belowl
100
Output High Voltage
V
Output Low Voltage
(ILOAO=0.25 mAl OS, AS, R/W
Input High Voltage
PAD-PA7, PBO-PB7, BO-B7
VIH
2.1
-
V
TIMER, IRQ, RESET
VIH
25
-
V
OSCl
VIH
21
-
V
VIL
-
0.5
V
Crystal
fOSC
0.032
1.0
MHz
External Clock
10SC
OC
1.0
MHz
lin
-
±1
I'A
ITSL
-
±10
I'A
Gin
-
B.O
pF
Cout
-
12.0
pF
Input Low Voltage IAII inputsl
I
Frequency of Operation
Input Current
RESET, IRQ, Timer, OSCl
Three-State Output Leakage
PAO-OAl, PBO-PB7, BO-B7
Capacitance
RESET, IRQ, Timer
Capacitance
OS, AS, R/W, AB-A 12, PAO-PA7, PBD-PB7, BO-B7
NOTE: Test conditions lor QUiescent Current Values are:
Port A and B programmed as inputs.
VIL=02 V for PAD-PA7, PBD-PBl, and BO-B7.
VIH=VOO - 0.2 V for iiESEi,
and Timer.
OSCl Input IS a squarewave from VSS + D.2 V to VOO - 0.2 V.
OSC2 output load (including tester) is 35 pF maximum.
Wait mode 100 IS affected linearly by thiS capacitance.
mo,
443
RCA CMOS LSI Products
CDP6805E2
DC ELECTRICAL CHARACTERISTICS 5.0 V IVOD = 50 Vdc ± 10% VSS = 0 T A = 0° to 70 0 unless otherwise noted)
Characteristics
Symbol
Min
Max
Output Voltage ILOADs 10.0 /loA
Total Supply Current ICL - 130 pF - On Bus, CL - 50 pF - On Ports,
No OC Loads, tcyc = 1.0 /los
Unit
VOL
-
0.1
V
VOH
VDO-O.l
-
V
100
-
10
rnA
Run IVIL = 0.2 V, VIH = VOO - 0.2 V)
Wait ITest Conditions - See Note Below)
100
rnA
100
-
1.5
Stop !Test Conditions - See Note Below)
200
/loA
VOH
4.1
-
V
VOH
VOH
4.1
4.1
-
V
V
IILOAO= 1.6 mAl AB-A 12, BO-B7
VOl
V
VOL
0.4
V
VOL
-
04
"LOAO= 1.6 mAl PAO-PA7, PBO-PB7
0.4
V
Output High Voltage
II LOAD -1.6 mAl AB-A 12, BO-B7
IILOAO=D36 mAl PAC-PA7, PBO-PB7
IILOAD= 1.6 mAl OS, AS, R/Vii
Output Low Voltage
"LOAo=1.6mA) OS, AS, R/W
Input High Voltage
PAO-PAl, PBO-PB7
VIH
VDO-2.0
-
V
TIMER, iRQ, RESET
VIH
VOO-O.B
-
V
OSCl
VIH
VOO-l.5
-
V
VIL
-
0.8
V
Crystal
10SC
0.032
5.0
MHz
External Clock
lose
DC
5.0
MHz
lin
-
±1
/loA
ITSI
-
±10
/loA
Cin
-
8.0
pF
Cout
-
12.0
pF
Input Low Voltage IAII Inputs)
Frequency 01 Operation
Input CurrAnt
.RESET, IRQ, Timer OSCl
Three-State Output Leakage
PAO-PAl, PBO-PB7, BD-B7
Capacitance
RESET, IRQ, Timer
Capacitance
OS, AS, R/W, AS-A 12, PAD-PA7, PBD-PB7, BO-B7
NOTE: Test conditions lor QUiescent Current Values are:
Port A and B programmed as inputs.
VIL = 0.2 V for PAC-PA7, PBO-PB7, and BO-B7.
VIH = VOO - 0.2 V for RESET, IRQ, and Timer.
OSCl input IS a sQuarewave from VSS + 0.2 V to VOO - 0.2 V
OSC2 output load Iincluding tester) is 35 pF rTlaximum.
Wait mode 11001 is affected linearly by this capacitance.
444
680S-Series LSI Products
CDP680SE2
DC ELECTRICAL CHARACTERISTICS 50 V (Voo = 50 Vde ± 10% VSS = 0 T A =0° to 70° unless otherwise noted)
Characteristics
Output Voltage ILOAOs 10.0 J!A
Total Supply Current ICL -130 pF - On Bus, CL - 50 pF ~ On Ports,
No OC Loads, teye = 1.0 J!s
Symbol
Min
Max
Unit
VOL
-
0.1
V
VOH
VOO-D.l
-
V
100
-
10
mA
Run IVIL =0.2 V, VIH = VOO - 0.2 V)
Wait I Test Conditions - See Note Below)
100
mA
IOD
-
1.5
Stop (Test Conditions - See Note Below)
200
/loA
ilLOAO-1.6 mAl AB-A12, BO-B7
VOH
4.1
-
V
ilLOAO=O.36 mAl PAQ-PA7, PBO-PB7
IILOAO= 1.6 mAl OS, AS, R/W
VOH
4.1
4.1
-
VOH
V
V
IlLOAO= 1.6 mAl AS-A12, BO-B7
VOL
-
0.4
V
ilLOAO = 1.6 mAl PAQ-PA7, PBO-PB7
VOL
-
0.4
V
VOL
-
0.4
V
Output High Voltage
Output Low Voltage
IlLOAO=1.6 mAl OS, AS, R/W
Input High Voltage
PAQ-PA7, PBO-PB7
VIH
Vnn-2.0
-
V
TIMER, iRQ, RESET
VIH
VOO-O.S
V
OSCl
VIH
VOO-l.5
-
VIL
-
O.S
V
Crystal
fose:
0.032
5.0
MHz
External Clock
fOSC
OC
5.0
MHz
lin
-
±1
p.A
ITSI
-
±10
p.A
Cin
-
B.O
pF
Cout
-
12.0
pF
Input Low Voltage IAII Inputs)
V
Frequency of Operation
Input Cumlnt
RESET,
iRa
Timer OSCl
Three-State Output Leakage
PAQ-PA7, PBO-PB7, BO-B7
Capacitance
RESET, IRQ, Timer
Capacitance
OS, AS, R/W, AS-A12, PAQ-PA7, PBO-PB7, BO-B7
NOTE: Test conditions for Quiescent Current Values are:
Port A and B programmed as inputs.
VIL =0.2 V for PAQ-PA7, PBO-PB7, and BO-B7.
VIH = VOO - 0.2 V for RESET, iRQ, and Timer.
OSCl input is a squarewave from VSS+0.2 V to VOO - 0.2 V.
OSC2 output load lincluding tester) IS 35 pF maximum.
Wait mode "00) is affected linearly by this capacitance.
445
RCA CMOS LSI Products
CDP6805E2
TABLE 1 - CONTROL TIMING (VSS=O, TA=Oo to 70°C)
VOO=5V ± 10%
fOSC=5' MHz
VOO=3~V
fOSC=l MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
I/O Port Timing - Input Setup Time (Figure 3)
Characteristics
tpVASL
500
-
250
tASLPX
100
100
-
Output Delay Time 1Figure 3)
tASLPV
-
-
0
0
ns
Interrupt Setup Time (Figure 6)
tlLASL
2
-
0.4
-
-
tOXOV
30
300
-
~
Crystal Oscillator Startup Time (Figure 5)
-
-
-
-
ns
Input Hold Time IFigure 3)
-
15
100
ms
Wait Recovery Startup Time I Figure 7)
WASH
-
-
10
-
-
2
15
100
..As
ms
-
1.0
~s
Stop Recovery Startup Time 1Crystal OscillatorllFigure 81 tlLASH
-
30
300
Required Interrupt Release (Figure 61
tOSUH
-
-
5
-
Timer Pulse Width (Figure 7)
tTH, tTL
0.5
-
-
0.5
Reset Pulse Width (Figure 5)
tRL
5.2
Timer Period (Figure 71
tTLTL
1.0
Interrupt Pulse Width Low 1Figure 16)
lfUH
1.0
Interrupt Pulse Period IFigure 16)
tlLlL
'IF
tOLOL
tOH
1000
-
OSCl Pulse Width High
350
-
OSCl Pulse Width Low
tOL
350
-
Oscillator Cycle Period 11/5 of t cyc )
-
-
1.05
-
-
1.0
1,0
-
-
'IF
75
75
tcyc
I'S
tf'iC
tcyc
tf'iC
ms
200
-
ns
ns
-
-
ns
*The minimum period tlLlL should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 20 Icye
cycles.
VOO=4.5V
TTL Equivalent
R2
Test
POint
c~
CMOS Equivalent
Test POUlt
,....
~
'P
'P
Rl
"::-
-::-
Pin
R,
R2
C
PAQ-PA7, PBD-PB7
11.3 k
2.1 k
50 pF
BO-B7, A8·A12,
R/W OS AS
2.5 k
2 k
130 pF
C=50 pF, PAD·PAl, PBD·PB7
= 130 pF, A8-A12, BO-B7, OS, AS, R/IN
with VOO= 5 V ± 10%
Fig, 2 - Equivalent tellt-Ioad circuitll,
446
6aOS-Serles LSI Products
CDP6805E2
(VLOW=0.8 v, VHIGH= VDD-2 I V,IvDD=5 '± 1096
Temp=Oo \0 10°C, CL on Port=50 pF, fOSC=5 MHzI
Address
Strobe
Port
Input----{
-~---tpVASL-----t""'t---tASLPX--"'"
Port
Output
*The address strobe of the first cycle of the next instructIOn as shown
In
Table 11.
Fig, 3 - 110 port timing waveforms.
TABLE 2 - BUS TIMING ITA = 0° to 10°C. VSS = 0 VI See Figure 4
Num
1
2
3
4
8
9
11
16
11
18
19
21
23
24
25
26
27
2B
Characteristics
Cycle Time
Pulse Width, os Low
Pulse Width, OS High or AD, WR, Low
Clock Transition
R/W Hold
Non-Muxed Address Hold
R/W Delay from OS Fall
Non-Muxed Address Delay from AS Rise
MPU Read Data Setup
Read Data Hold
MPU Data Delay, Write
Write Data Hold
Muxed Address Delay from AS Rise
Muxed Address Valid to AS Fall
M uxed Address Hold
Delay OS Fall to AS Rise
Pulse Width AS High
Delay, AS Fall to OS Rise
Symbol
tcye
PWEL
PWEH
t , tf
tRWH
tAH
tAD
tADH
tOSR
tm-lR
tDDW
tOHW
tBHO
tASL
tAHL
tASD
PWASH
tASED
fOSC=l MHz,
Voo=31V
60 pF load
Min
5000
2800
1800
Max
DC
-
fOSC=6 MHz
Voo=6IV± 10"'.
1 TTL
and 130 pF load
Min
1000
5flO
375
Max
100
-
30
10
800
-
10
100
-
-
500
-
300
0
200
0
100
200
-
115
-
0
1000
0
160
120
-
-
DC
-
-
0
-
800
-
55
-
0
260
0
120
-
56
60
160
175
160
800
250
800
850
800
750
-
-
180
-
-
-
I
Unh
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
n5
ns
ns
ns
ns
ns
ns
•
447
.".
Cl:D
.j:>.
.j:>.
00
mO
Q)
Vl--@~VHIGH*
AS
C»~
5:0
men
V LOW
0-+11+-
0)
---H---------..
DS
~---___l-
CD
f---
0~l@-
Nr-
en
"0
C;
a.
c
Q) ---~
R/W
@
®
~
AS-A11
~@
~@
Valid
Write
BO-B7
MPU Write
~®
~
~@/~~@~
Valid
I I
Addr
BO-B7
MPU Read
*VHIGH~2 V, VLOW~O 5 V for VOO~3 V
VHIGH VOO
2 V, VLOW~ 0 8 V for VOO ~ 5 V ± 10%
Fig. 4
~
Bus timing waveforms.
II
@
Data
®
Valid Read Data
o
/'------+----
~
•
o':C~1=f=~J77Jfl{//1!/JIl!JT
t=',C;
ITIII//Jll/fil77lTfl/Tfl//////////fl/IlW7!IIIlIlVzmzlt
,wI'
J i!1Jl07//lJ7////l~
RESET
tOXOV _I
1920 tcyc
-1
AS _ _ _---'
DS _ _ _ _ _---'
Unmux
Ad~~~!1~us 1IlT!I!!/a. 1F
Mux BO-B7
Address/Data
Bus
R/VV
~=-x
FE
XNew PCH X
1F
FF
x=x::::::ICX
X
1F
X
X
1F
First Instruction
x:::::::JL:::::X New PCH x:::=:
1F
New PCH
New PCl,
..L.t...'-U.I....L.£...U.J\...-J'<:..LLLL.l.JA.-f'LL.i.~{'-~_-:::-::J'-~-:-+::-:1'-..../I _ _.../\...../I_ _.../\..-JL-_..../I.-JL-_--.A::-:!'.l....L.l....Wog~=-:!'\L.L.LL.l.CV\=-:!'L-_..../I-:!L-_~o-'~t-~........."-
FE
FE
New PCH
New PCl
FE
OI/llT//II
Oscillator Waveform
i:
Crystal Oscillator ConnectIOns
CDP6805E2
tOl---b:=:}-OH
OSCl Pin
J
10 Mil
38~39
OSC2L----lnw OSCl
-tOlOl
ICOSC2
I
FE
FE
FF
First Instruction
x=J
\
Crystal Parameters Representative Frequencies
RS max
CO
Cl
0
CaSCl
COSC2
5 MHz
500
8 pF
0.02 pF
50k
15-30 pF
15-25 pF
4 MHz
750
7 pF
0.012 pF
40k
15-30 pF
15-25 pF
1 MHz
4000
5 pF
0.008 pF
30k
15-40 pF
15-30 pF
COSCl
l
Crystal Circuit
Cl
RS
oC~
0~C2
Fig. 5 - Powef-on feset and iiiit timing waveforms.
"""
--"---.
en
TABLE 4 -
.j:>.
REGISTER/MEMORY INSTRUCTIONS
Addressing Modes
Immediate
Direct
Op
Code
A6
AE
-
#
Bytes
#
CycleS
Op
Code
2
2
2
-
2
-
-
-
-
B6
BE
B7
BF
#
,
Bytes
Cycles
2
2
2
2
3
3
4
4
Op
Code
C6
"U
Indexed
(No Offsetl
Extended
,
,
Bytes
CycleS
3
3
4
4
FB
1
1
1
1
1
Op
Code
F6
FE
F7
FF
,
,
Bytes
Cycles
2
2
4
4
3
EF
EB
2
2
2
5
5
4
DE
D7
DF
DB
Op
Code
E6
EE
E7
ADD
AB
2
2
BB
2
3
CB
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract Memory
SUB
AD
2
2
BO
2
3
CO
3
4
FO
1
3
EO
2
4
DO
3
5
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND Memory to A
AND
A4
OR Memory with A
Exclusive OR Memory
with A
ORA
AA
2
2
2
2
B4
SA
2
2
3
3
C4
CA
3
3
4
4
F4
FA
1
1
3
3
E4
EA
2
2
4
4
D4
DA
3
3
5
5
EOR
A8
2
2
88
2
3
C8
3
4
F8
1
3
E8
2
4
DB
3
5
CMP
Al
2
2
Bl
2
3
Cl
3
4
Fl
1
3
El
2
4
Dl
3
5
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
D3
3
5
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
D5
3
5
DC
3
4
DD
3
7
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A (Logical Compare~
STA
STX
Jump to Subroutine
4
5
5
4
3
3
3
3
3
6
5
-
I
-
-
-
-
BC
BD
2
5
2
2
CC
CD
3
3
3
FC
FD
6
1
2
EC
1
5
ED
2
2
3
6
TABLE 5 - READ/MODIFY/WRITE INSTRUCTIONS
Addressing Modes
Inherent (XI
Inherent (AI
Function
Mnemonic
Increment
INC
Decrement
Clear
DEC
CLR
COM
Complement
Negate
(2's Complement)
NEG
Op
Code
4C
4A
4F
#
Bytes
1
1
#
Cycles
43
1
1
3
3
3
3
40
1
3
Indexed
(No Offsetl
Direct
#
Cycles
Op
Code
#
Bytes
#
Cycles
3C
3A
3F
53
1
1
3
3
3
3
33
2
2
2
2
5
5
5
5
Op
Code
7C
7A
7F
73
50
1
3
30
2
5
70
Op
Code
5C
5A
5F
#
Bytes
1
1
Indexed
(8-Bit Offsetl
,
#
Bytes
Cycles
1
1
1
1
5
5
1
5
Op
Code
6C
6A
6F
63
#
Bytes
2
2
2
2
5
60
2
5
#
Cycles
6
6
6
6
6
ROL
49
1
3
59
1
3
39
2
5
79
1
5
69
2
6
ROR
46
1
3
56
1
3
36
2
5
76
1
5
66
2
6
Logical Shift Left
LSL
48
2
5
78
6
34
2
5
64
2
5
5
67
2
2
6
37
74
77
5
5
2
1
1
1
1
1
68
54
3
3
3
38
44
3
3
3
1
LSR
ASR
1
1
1
58
Logical Shift RIght
Arithmetic Shift Right
6
2
4
70
1
4
60
2
5
Rotate Left Thru Carry
Rotate Right Thru
Carry
Test for Negatiye
or 7P.fO
m
Nrth
5
5
6
"U
~
0
Q,
c
n
-
C8
:
i
i
JMP
JSR
Jump Unconditional
CE
C7
CF
D6
TST
47
4D
1
3
57
50
1
3
30
-
-
I
»
0
CO 31:
0
en 0th
,
Add Memory to A
Add Memory and
Carry to A
Load X from Memory
Store A In Memory
Store X in Memory
Mnemonic
LDA
LOX
(J)
Indexed
I1&-Bit Offsetl
Op
#
Code Bytes Cycles
#
Bytes
3
3
3
3
3
Function
Load A from Memory
#
Cycles
4
Indexed
(8-Bit Offsetl
!
6805-Serles LSI Products
CDP6805E2
TABLE 6 -
BRANCH INSTRUCTIONS
Relative Add~
Op
Code
,
Mode
Mnemonic
Byt..
Cyelet
Branch Always
BRA
20
2
Branch Never
Branch IFF Higher
BRN
BHI
21
2
22
2
Branch IFF Lower or Same
BLS
23
2
BCC
(BHS)
24
2
24
2
BCS
(BlO)
25
2
25
2
Branch IFF Not Equal
BNE
26
2
Branch IFF Equal
BEQ
27
2
Branch IFF Half Carry Clear
BHCC
28
2
Branch IFF Half Carry Set
BHCS
29
2
BPl
2A
2
Branch IFF Minus
BMI
2B
2
Branch IFF Interrupt Mask Bit is Clear
BMC
2C
2
Branch IFF Interrupt Mask Bit is Set
BMS
2D
2
Bil
2E
2
Function
-'1
,
Branch IFF Interrupt Line is High
BIH
2F
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Branch to Subroutine
BSR
AD
2
6
Branch IFF Carry Clear
(Branch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF lower)
Branch IFF Plus
Branch IFF Interrupt Line is low
TABLE 7 -
BIT MANIPULATION INSTRUCTIONS
Addressing Model
Bit Setl Clear
Function
Mnemonic
Branch IFF Bit n is Set
BRSET n (n=O .. 7)
Branch IFF Bit n is Clear
BRClR n (n=O .. 71
Set Bit n
BSET n (n=O .. 71
Clear Bit n
BClR n (n=O .. 71
Bit T..t and Branch
I
I
Byt..
Cycles
-
Op
Code
20n
3
01 +20n
3
5
5
5
5
-
-
Op
Code
#
#
Bytes
Cycles
-
-
10+ 20 n
11 +2 on
2
2
-
I
TABLE 8 -
CONTROL INSTRUCTIONS
Inherent
Function
Mnemonic
Op
Code
#
I
Bytes
Cyel..
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
2
CLC
99
98
1
Clear Carry Bit
1
2
Set Interrupt Mask Bit
SEI
9B
2
Clear Interrupt Mask Bit
CLI
9A
1
1
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
6
Return from Interrupt
ATI
80
1
9
9C
1
2
9D
Reset Stack Pointer
RSP
No-Operation
NOP
Stop
STOP-
Wait
WAIT
2
1--8E
1
2
1
2
SF
1
2
465
RCA CMOS LSI Products
·CDP6805E2
TABLE 9 - INSTRUCTION SET
Addreuing Model
Mnemonic
ADC
AD[
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Inh8l'8f1t
Immediate
Direct
x
X
X
X
X
X
X
X
X
X
Extended
x
X
X
X
X
X
X
X
BI
A
A
X
X
X
X
X
X
X
X
H I N Z C
X
X
---
--_._- -_._-
.
X
X
X
__ ._- ------- --.--_.
.X
X
x
X
X
X
X
X
---x-- - - - - -
-
X
X
X
X
X
-
X
X
- -X
X
X
----
--
X
. - - - -..
-_..__..
---.--
x
X
x- ----X
f----
x
-----.---
-----
X'
-~f-----
X
--X
X
X
X
X
X
X
X
X
X
--._-----._-
X
X
-- _xX
X
X
X
X
X
X
Half Carry IFrom Bit 31
Interrupt Mask
Negative ISlgn Bltl
Zero
Carry/Borrow
-~ ----
·0,1
A A A
A A 1
A A A
A A
A A
A A
•••
•• •• •
••
---
X
X
X
X
x
A
A
A
0
---~- -~- f-'-~- --
-----
A
A
A
A
A
A
A
••••
•• • •• •
• •• • ••
•• • • ••
••• •• •• •• .
•••
A
A
A
A
A
A
A
A
A
A
X
X
0
X
X
X
X
X
X
X
X
0
A
Test and Set .f True. Cleared OtherWise.
•
I
Not Affected
load CC Register From Stack
Cleared
Set
o
A
1
1
1
X
A
A
•
••••
•
f---- --.
A
A •
A A
A A
A A
•••••
•
•
•
X
-
A
A
0
X
X
----
•
••
••
0
X
Condition Code Symbols
H
I
N
Z
C
x
x--
X
X
X
X
X
X
X·-
A
A
A
A
X
X
A
X
X
------
--+- --f--
------_.
A
. -----
X
X
X
X
X
X
A
A
A
A
A
__o_
~--- f-'--}- -- . - X
1-
X
X
X
X
X
X
X
X
X
X
X
X
X
--
X
X
X
._-- "."-
._-_.- -- ---- --- ----- .._-
"
X
X
X
. .•.__
X
- ..-. -- - - - --_._-_._-
--.----
X
X
X
X
X
X
X
X
X
X
X . --X
X
- .- -- .. - _ .. ----.
A
A
fA
A
••
••
•• •••
•• •
••• •••
••
X
X
X
X
X
X
X
X
X
OAA
AOl
AOR
RSP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
466
Bit
Teet &
Branch
X
._--_ ..--- --
~-BlS
-~NOP
Condition Codes
Bit
Indexed Indexed
(8 Bits) (16 Bits) Setl
Clear
X
I---~Il
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BASET
BSH
BSA
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lDA
lDX
lSl
lSA
Ralative
Indexed
(No Offset)
A
·
TABLE 10 - CDP6805E21NSTRUCTION SET OPCODE MAP
Branch
BItM. 'lipulation
~i
In
~,
cJ,o
_Ilie
lUll
c:..
ODin
5
BRSEJ~.
. 7
5
BRCLRO
3
BTB
5
3SRSEJ~B
5
.
.,
,
BSE1~c
,
2 aCL~~c
2 BSE~lc
5
~,
3BRCL~iB
4
0100
BRSET2
BTB
3
O~,
[3BRCL~tB
2 BCL~~c
5
5
~,
O~O
BRSEJ~B
O,~,
BRCL:rB
5
,BRSEJ:.
5
1~
9
1001
5
3BRCL~¢s
5
It,O
,~,
2 BCL~~c
BRSEJ~B
5
• 3BRCL:~B
~o
.
5
5
2
BSEl~c
,
,
3
BLS
AOC
3
BCCA"
3
2 BCSAR
..
3BRSEJ~B
,Pn,
,BRCL:~
.'
'
, BCL~~c
5
5
J
,
11~0
3BRSEJIB
2
F
BRCLR7'
BTB
3
BCLR7'
2
BSC
BSE~~c
5
NEGDI •
-~.
ReadfModify/Write
]X
X
I
_Qi1.~
3
, NEG~H
,
3
BRNBEL
3
2 SHIAR
2
BM~EL
NEGX
'NH
5
2 COMDI •
,
, 5
LSRWA
3
1
COMA
INH
3
1 LSRANH
3
, COMXINH
2
BIL AEL
3
BtH
AEL
IX'
NEG
1
I~O
1~'
9
RT!
IX
1
6
, COM,x ,
1
INH
5
COM
1
6
2 LSR
LSR
IX'
1
IX
5
,
10
SWI
INH
12
5
RO'\,'A
5
ASR
OIA
5
LSLOIA
5
ROLOIA
5
DECOlA
3
RORA
1
INH
3
ASR~H
3
RORX
1
lNH
3
3
ASRX
INH
3
LSLX
3
ROLA
INH
1
3
DECA
1
INH
3
ROLX
INH
3
DECX
1
INH
1
2 ROR
1
, LSLANH ,
iNH
,
IXI
ROR
1
6
ASR
2
IXI
~SLIXI
6
2
DEC
IX
5
2
LSL
1
TAX
INH
2
2
CLC
12 EOR
INH
IMM
2
2
SEC
AOC
INH 2
IMM
1
2
ORA L
CLI
INH 2
1
IMM
,
IXI
1
IX
5
ROL
IX
5
DEC
IX
SEI
5
INC OIA
4
2 T5TOIA
3
INCA
INH
3
TSTA
1
INH
,
3
INCX
INH
3
TSTX
1
INH
,
5
CLR
OIA
2
3
CLRA
INH
1
3
CLRX
1
INH
L
ADD
L
IMM
INH 17
2
RSP
INH
1
2
6
NOP
BSR
1
INH 2
AEl
2
LOX
12_
IMM
2
TXA
INH
1
1
5
6
INC
2
INC
IXI
5
4
TST
IXI
2
6
CLR
2
IX
1
TST
IXI
IX
1
,
5
CLR
IX
1
STOP L
INH
WAIT L
1
INH
3
SUBDI •
,
3
CMP
DIR
2
3
2 sac
01.
3
CPX
OIA
2
3
AND
OIA
2
3
2
BIT OIA
3
LOA
OIA
2
STA
OIA
3
2 EOROIA
;
ADC
OIA
2
2
2
ADD"
OIA
2
JMP
OIA
2
2
J5R
2
2
INH
BSe
BTB
IX
IXl
IX2
~
LOX "
OIA
1~
4
SU~XT
4
CMP
EXT
3
,
.
SUB ,x ,
SBC
EXT
IX
,~,
4
SUB ,x ,
5
CMP
3
IX2
3
SBC •
Ix2
4
3
,
1
11~0
4
4
CPX
3
lXT
4
AND
EXT
3
4
BI\XT
4
LOA
EXT
3
STA •
3
EXT
4
3 EOR
EXT
4
ADC
EXT
3
4
ORA
EXT
3
ADD·
EXT
3
JMP "
EXT
3
J5R 6
EXT
3
3
LOX
EXT
STX
3
J~
CPX '
3
IX2
5
AND
3
1X2
5
3
B!T IX2
5
2 CPX
3
ORA 5
IX2
ADD 0
IX2
3
4
JMP
IX2
3
JSR
3
IX2
LOX '
1X2
6
STX
IX2
3__
3
IXI
4
I
2
BIT
IXI
4
LOA
2
IX'
5
2 STA
IX
3
In
1
0001
, SBC IX
00'0
,
CPX
2
3
IX
3
0011
IX
3
BIT IX
0:'00
AND
IXI
4
2
CMP
IX
AND
LOA
IX2
3
- STA 0
3
IX2
6
5
EOR
IX2
3
5
ADC
3
IX2
,
4
CMP
IXI
2
4
sac
IXI
2
H~
3
SUB
1
,
3
, LOA IX
o~,
6
0110
4
7
STA
IXI
1
IX
0111
1
EOR "
IX
1(XX)
1001
4
EOR
2
IXI
4
8
2
IX'
,
ADC J
IX
2
ORA 4
IXI
1
ORA '
IX
101C
2
ADD
IX'
1
ADD'
IX
!01t
JMP "
IXI
2
,
ADC
JSR 6
IXI
2
4
2
LOX
STX
2
IXI
0
IXI
1
,
JMP
L
A
B
C
1 ~oo
"
JSR
9
•
IX
LOX 3
0
1101
E
IX
Inc
STX •
1
IX
ll11
F
LEGEND
F ...
Inherent
Immediate
Direct
Extended
Relative
M~=
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed. 1 Byte IB-Bitl Offset
Indexed. 2 Byte It6-BitI Offset
~
r
I of Cvcles - - - - - - - - '
CMOS Veniona Only
0>
....,
5
OIA
STX •
OIA
2
AbbnMa1iona for AcIcha Modw
IMM
DIR
EXT
REl
ORA "
OIA
~
Jioo
4
1
IX
6
2
[2 LOA
IMM
5
IX'
ROL
2
ASR
1
6
2
BI~MM
5
6
l~'
2
AND L
IMM
2
2
IX
~
PJR
SU?MM
2
CMP
IMM
2
2
SBC
IMM
2
CPX
IMM
2
'NH
6
3
LSRX
3
2
NEG
1~
5
0
,
INti
01
0:'0
3
Register/Memory
Control
I~
RTS
INH
1
3
2 BSE~~c [, BNEAEl 2
.5
3
BEOAFl .
2 BCL~~c
2
3
2 BSE11c , BHC~FI
,
5
3
2 BCL~~c 2 BHC~R 2
5
3
BPLAEl
2 B5E~~c
2
5
3
2 BCL~~c 2 BM~El
3
,0
, BSE~~c , BM~FL 2_
lfoo
1111
c:.,
00'\0
3
BRA...
A
-
:> Opcode in Hexadac:im8I
Zx~ am;j
"
Opcode in Binary
Io
en
I
.
oCD
CD
Adcfr-. Mode
•
"0;
Or00
0) ..
(1&)0
OA.
c.nC
m9.
1\) •
RCA CMOS LSI Products
CDP6805E2
is within the span of the branch.
EA = PC + 2 + (PC + 11; PC- EA if branch taken;
otherwise PC-PC+2
Indexed. 8-bit Offset - Here the EA is obtained by aaaing
the contents of the byte following the opcode to that of the
index register. The operand is therefore located anywhere
within the lowest 511 memory locations. For example, this
mode of addressing is useful for selectinq the moth element in
an 1'1 element table. All instructions are two bytes. The contents of the index register (X) is not changed. The contents
of (PC+ 1) is an unsigned a-bit integer. One byte offset indexing permits look-up tables to be easily accessed in either
RAM or ROM.
EA=X+(PC+1); PC-PC+2
Address Bus High-K; Address Bus Low-X + (PC+ 1)
Where: K = The carry from the addition of X + (PC + 11
Bit Set/Clear - Direct addressing and bit addressing are
combined in instructions which set and clear individual
memory and I/O bits. In the bit set and clear instructions, the
byte is specified as a direct address in the location following
the opcode. The first 256 addressable locations are thus accessed. The bit to be modified within that byte is specified
with three bits of the opcode. The bit set and clear instructions occupy two bytes, one for the opcode (including the bit
number! and the second to address the byte which contains
the bit of interest.
EA= (PC + 11; PC-PC+2
Address Bus High-O; Address Bus Low-(PC+ 1)
Indexed. 16-Bit Offset - In the indexed, 16-bit offset addressing mode the effective address is the sum of the contents of the unsigned 8-bit index register and the two unSigned bytes following the opcode. This addressing mode
can be used in a manner similar to indexed 8-bit offset. except that this three byte instruction allows tables to be
anywhere in memory (e.g., jump tables in ROM). As with
direct and extended, the I assembler determines the most
jefficient form of indexed offset - 8 or 16 bit. The content of
the index register is not changed.
EA=X+[(PCt1):(PC+2)]; PC-PC+3
Address Bus High-(PC+11+K;
Address Bus Low- X + (PC + 2)
Where: K= The carry from the addition of X + (PC + 2)
Bit Test and Branch - Bit test and branch is a combination of direct addressing, bit addressing and relative addressing. The bit address and condition (set or clear! to be tested
is part of the opcode. The address of the byte to be tested is
in the single byte immediately following the opcode byte
(EA 1). The signed relativeS-bit offset is in the third byte (EA2) and
is added to the PC if the specified bit is set or clear in the
specified memory location. This Single three byte instruction
allows the program to branch based on the condition of any
bit in the first 256 locations of memory.
EA1=(PC+l)
Address Bus High-O; Address Bus Low-(PC+ 1)
EA2= PC+3+ (PC+2); PC-EA2 if branch taken;
otherwise PC - PC + 3
Relative - Relative addressing is only used in branch instructions. In relative addressing the contents of the a-bit
Signed byte following the opcode (the offset! is added to the
PC if and only if the branch condition is true. Otherwise,
control proceeds to the next instruction. The span of relative
addressing is limited to the range of - 126 to + 129 bytes
from the branch instruction opcode location. The Motorola
assembler calculates the proper offset and checks to see if It
SYSTEM CONFIGURATION
Figures 20 through 25 show in general terms how the
CDP6805E2 bus structure may be utilized. Specified interface details vary with the various peripheral and memory
devices employed.
Chip
Enable
AS·A12
TYPical CMOS
Peripheral
CDP6805E2
CMOS
Microprocessor
BO·B7
AS
OS
RIW
IRO
ascI
RESET
Addressl Data Bus
Address Strobe
Data Strobe
ReadlWnte
Interrupt
4.19 MHz
-
-r -
ADO-AD7
AS
OS
RIVii
IRO
CKOUT
RESET
Fig. 20 - Connection to CMOS peripherals.
468
680S-Serles LSI Products
CDP6805E2
Chip
Enable
CMOS
Multiplexed
Memory
COP65516
CDP6805E2
A8-A12
1---------.
Address/ Data 8us
AOOO-ADQ7
AS~____~A~d~dr~e~ss~S~tr~ob~e~__~M
OS
Data Strobe
G
R/IN
Read/Write
IN
Fig. 21 - Connection to CMOS multiplexed memories.
CDP6805E2
Peripherals
AS
I
DS~____~O~at~a~S~t~ro~b~e____~E
R/IN
Read/Write
R/IN
IRO
Interrupt
IRO
RESET
RESET
NOTE: In some cases, pullup resistors or other level
shlftl"g techniques may be reqUired on signals
going from NMOS to CMOS parts
Fig. 22 - Connection to peripherals.
469
RCA CMOS LSI Products
CDP6805E2
Address/Data Bus
BO-B7K:
Data
A~
CDP6805E2
A8-A12
R/W
oS
AS
)
Address
Read/
Write
Read
Data Strobe
J
U
J
Address
Decode
Output
Enable
I
I
Chip
Enable
Address
Strobe
00-07
CMOS
Non-Muxed
AO-A7 ROM or
EPROM
A8
S
E
Fig_ 23 - Connection to latch non-multiplexed CMOS ROM or EPROM.
CDP6805E2
CMOS
CMOS
Static
RAMs
MIcroprocessor
00-07
Strobe
AS...---....
A8
A9
A8-A12
Chip
Enable
I-----IE
•
DS~~------r-~
Read/
R/W Write
Fig. 24 - Connection to static CMOS RAMs.
470
6aOS-Serles LSI Products
CDP6805E2
Address/ Data Sus
Data
00-07
AO-A7
CDP6805E2
CMOS
Non-Mu.ed
RAM
AS-A12
Address
AS
1-----__.
Data
Strobe
DS I--~-e_l...
Output
Enable
Read/
Write
R/W~-----I
Address
AS
~
Write
Strobe
Chip
Enable
E
Fig. 25 - Connection to latched non-multiplexed CMOS RAM.
I
471
RCA CMOS LSI Products
CDP6805E2
pected results during debug of both software and hardware
as the control program is executed. The information is
categorized in groups according to addressing mode and
number of cycles per instruction.
Table 11 provides a detailed description of the information
present on the Bus, the Read/Write (R/W) pin and the Load
Instruction IU) pin during each cycle for each instruction.
This information is useful in comparing actual with exTABLE 11 Addreu Mode
Instructions
Inherent
LSR LSL
ASR NEG
CLR ROL
COM ROR
DEC INC TST
TAX CLC SEC
STOP CLI SEI
RSP WAIT NOP TXA
RTS
I
Cycles
Cycle #
3
1
2
2
6
3
Op Code
Op Code Next Instruction
Op Code Next Instruction
1
2
Op Code Address
Op Code Address
+1
1
1
1
0
Op Code
Op Code Next Instruction
1
2
Op Code Add ress
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
New Op Code Address
1
0
0
0
0
0
1
0
6
7
8
9
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Vector Address 1FFC (Hex)
Vector Address 1FFD (Hex)
Interrupt Routine Starting Address
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
New Op Code Address
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code
Op Code
Op Code Next Instruction
Return Address (LO Bytel
Return Address (HI By tel
Contents of Index Register
Contents of Accumulator
Contents of CC Register
Address of Int. Routine (HI Byte)
Address of Int. Routine (LO Byte)
Interrupt Routine First Opcode
Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code
1
2
Op Code Address
Op Code Address
+1
1
1
1
0
Op Code
Operand Data
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand
1
1
1
1
0
1
0
0
0
0
Op Code
Address of Operand
Operand Data
Operand Data
Manipulated Data
Op Code Add ress
Op Code Address + 1
Address of Operand
Op Code Address + 2
Op Code Add ress + 2
1
1
1
1
1
1
0
0
0
0
Op Code
Address of Operand
Operand Data
Branch Offset
Branch Offset
Op Code Add ress
Op Code Address
Op Code Address
1
1
1
1
0
0
Op Code
Branch Offset
Branch Offset
1
1
1
1
0
0
1
0
0
0
0
0
Op Code
Branch Offset
Branch Offset
First Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)
3
4
3
5
6
7
8
9
10
1
2
3
4
Immediate
ADC EOR CPX
ADD LOA LOX
AND ORA BIT
SBC CMB SUB
2
Data Bus
1
0
0
4
9
Pin
1
1
1
1
2
RTI
LI
R/W
Pin
+1
+1
6
10
Address Bus
Op Code Add ress
Op Code Address
Op Code Address
5
SWI
SUMMARY OF CYCLE BY CYCLE OPERATION
5
0
0
0
0
0
0
0
Bit Set/Clear
BSET n
BCLR n
5
'5
Bit Test and Branch
BRSET n
BRCLR n
1
2
5
3
4
5
Relative
BCC BHI BNE BEQ
BCS BPL BHCC BLS
BIL BMC BRN BHCS
BIH BMI BMS BRA
BSR
1
3
6
2
3
1
2
3
4
5
6
472
+1
+1
Op Code Address
Op Code Address + 1
Op Code Address + 1
Subroutine Starting, Address
Stack Pointer
Stack Pointer -1
680S-Serles LSI Products
CDP6805E2
TABLE 11 - SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUED)
Addr_ Mode
Instructions
I
LI
R/W
Pin
PIn
+1
1
1
0
Op Code Add ress
Op Code Address + 1
Address of Operand
1
1
1
0
0
Op Code Address
Op Code Address + 1
Address of Operand
Op Code Add ress + 2
1
1
1
1
1
1
1
Addr_ BUB
Cycles
Cycles'
JMP
2
1
2
Op Code Address
Op Code Add ress
ADC EOR CPX
ADD LOA LOX
AND ORA BIT
SBC CMP SUB
3
1
2
I
DetlIIil
Direc1
3
TST
4
STA
STX
4
LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR
1
2
3
4
1
2
3
4
1
2
5
3
4
5
1
2
JSR
5
Op Code Address
Op Code Adrress + 1
Op Code Address + 1
Address of Operand
Op Code Address
Op Code Address
Operand Address
Operand Address
Operand Address
+1
0
1
1
1
1
0
op Code Address
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
Op Code
Jump Address
Op Code
Address of Operand
Operand Data
Op Code
Address of Operand
Operand Data
Op Code Next Instruction
Op Code
Address of Operand
Address of Operand
Operand Data
Op. Code
Address of Operand
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Subroutine Address (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Bvte)
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
0
0
0
0
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Address of Operand
1
1
1
1
1
1
1
1
0
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
2
Op Code Address
Op Code Address + 1
1
1
0
Op Code
Op Code Next Instruction
1
2
Op Code Address
Op Code Address + 1
Index Register
1
1
1
1
0
0
Op Code
Op Code Next Instruction
Operand Data
Op Code Address
Op Code Address
Index Register
Op Code Address
Op Code Address
Op Code Address
Op Code Address
Index Register
1
1
1
1
1
1
1
)
Op Code
Op Code Next Instruction
Operand Data
Op Code Next Instruction
3
4
5
Extended
JMP
3
1
2
3
ADC BIT ORA
ADD CMP LOX
AND EaR SBC
CPX LOA SUB
4
1
2
3
4
1
STA
STX
5
2
3
4
5
1
JSR
6
2
3
4
1
1
0
0
0
Op Code
Jump Address (H I Byte)
Jump Address (LO Byte)
Op Code
Address Operand (HI Byte)
Address Operand (LO Byte)
Operand Data
Op Code
Address of Operand (HI Byte)
Address of Operand (LO Byte)
Address of Operand (LO Byte)
Operand Data
Op Code
Address of Subroutine (HI Byte)
Address of Subroutine (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)
Indexed, No-Offset
JMP
ADC
ADD
AND
SBC
2
EOR CPX
LOA LOX
ORA BIT
CMP SUB
TST
STA
STX
LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR
JSR
3
3
4
4
5
5
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
5
+1
+1
+1
+1
Op Code Address
Op Code Address + 1
Index Register
Index Register
Index Register
Op Code Address
Op Code Address + 1
Index Register
Stack POinter
Stack POinter - 1
0
-- - 1
1
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
0
----1
0
0
0
0
1
0
0
0
0
Op Code
Op Code Next Instruction
Op Code Next Instruction
Operand Data
Op Code
Op Code Next Instruction
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Op Code Next Instruction
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)
473
I
RCA CMOS LSI Products
CDP6805E2
TABLE 11 - SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUED)
Addr_Mode
Instruction.
Indexed 8-Bit
I
Cycles
R/~T
Pin
LI
Pin
Data Bus
Offset
3
JMP
1
2
3
ADC
ADD
AND
SUB
Add~Bus
Cvcles ,
EOR CPX
LOA LOX
ORA CMP
BIT SBC
STA
STX
4
1
2
3
4
1
2
5
3
4
5
1
2
TST
5
3
4
5
LSL LSR
ASR NEG
I CLR ROL
: COM ROR
DEC INC
1
2
6
3
4
5
6
1
2
JSR
6
3
4
5
6
1
1
1
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
1
1
1
1
0
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Op Code Address + 2
1
1
1
1
Op Code Address
Op Code Address
Op Code Address
+1
+1
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Index Register + Offset
Index Register + Offset
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset
1
1
1
1
1
0
0
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Op Code Address + 2
Index Register + Offset
1
1
1
1
1
Op Code
Offset
Offset
Op Code
Offset
Offset
Operand Data
Op Code
Offset
Offset
Offset
Operand Data
Op Code
Offset
Offset
Operand Data
Op Code Next Instruction
Op Code
Offset
Offset
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Offset
Offset
1st Subroutine Op Code
Return Address LO Byte
Return Address HI Byte
Indexed, 16-Bit ~
JMP
4
1
2
3
4
ADC CMP SUB
ADD EOR SBC
AND ORA
CPX LOA
BIT LOX
1
5
2
3
4
5
1
2
STA
STX
6
3
4
5
6
1
2
3
JSR
7
4
5
6
7
474
Op
Op
Op
Op
Code
Code
Code
Code
Address
Address
Address
Address
+1
+2
+2
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset
Stack Pointer
Stack Pointer - 1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
Op Code
Offset (HI Bytel
Offset (LO Bytel
Offset (LO Bytel
Op Code
Offset (HI By tel
Offset (LO Bytel
Offset (LO Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
Offset (LO Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HO Byte)
680S-Series LSI Products
CDP6805E2
TABLE 11 - SUMMARY OF CYCLE BY CYCLE OPERATION (CONTINUEDI
._-------
Instructions
Cycles
Cycles #
Address Bus
RESE'I'
RIW
LI
Pin
PIft
PIn
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
1
1
1
0
0
1
1
1
1
1
iJm
R/iR
Pin
Pin
LI
Pin
0
X
0
X
0
X
X
1
1
0
0
0
0
Irrelevant Data
Irrelevant Data
Return Address (LO Byte)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
Return Address IHI Byte)
Contents Index Reg
Contents Accumulator
Contents CC Register
Vector High
Vector Low
In! Routine First
om8ua
Other Functions
Hardware RESET
5
$lFFE
$lFFE
$lFFE
1
2
3
4
$lFFE
$lFFE
$lFFE
Reset Vector
$IFFE
5
1
Power on Reset
1922
•
•
•
•
•
•
$IFFE
$IFFE
$lFFF
Reset Vector
1919
1920
1921
1922
Instruction
Cycles
Cycles #
I
I
IRO Interrupt
(Timer Vector $lFF8, $lFF91
10
1
2
3
4
5
6
7
8
9
10
Address Bus
Last Cycle of Previous
Instruction
Next Op Code Address
Next Op Code Address
SP
SP-1
SP-2
SP-3
SP-4
$lFFA
$lFF8
IRQ Vector
0
1
1
1
0
0
0
0
0
0
0
0
0
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Vector High
Vector Low
Op Code
Irrelevant Data
•
•
•
Irrelevant Data
Vector High
Vector Low
Op Code
Data Bus
APPENDIX
CDP6805E2INTERRUPT CLARIFICATION
Under certain circumstances, the CDP6805E2 '(BP4xxx
& AW9xxxx) 8-bit Microprocessor Unit i"i"m interrupt does
not conform to the operation described in this Advanced Information Sheet (ADI-850Rll.
1. The level sensitive IRQ mode, which is by far the most
frequently used, is FULLY OPERATIONAL; thUS, most
CDP6805E2 applications are unaffected. However,
the edge-triggered i'RCi interrupt mode MIGHT NOT BE
SERVICED under certain programming circumstances;
therefore, it is recommended that the edge- triggered
mode not be used.
2 . An interrupt-vector address CAN BE improperly
generated in some circumstances. There is a possibility
that when an external interrupt (lRQI and timer interrupt occur during the Wait mode (following a Wait instruction), address locations $1 FF2 and $1 FF3 are
selected instead of vector locations $1 FF6 and $1 FF7.
There are three specific examples listed below; two of
these require no action and the third has a recommended solution.
a. Those not using the Wait mode need not take any
action.
b .If the Wait mode is used without external interrupt
(iRQ pin held highl, no precautions are required,
c . When IRQ can be active (low) during the Wait
mode, the vector in locations $1 FF6 and $1 FF7 (the
Wait mode Timer Interrupt Vector) should be
,duplicated in $1 FF2 and $1 FF3. In this way the circumstances that caused selection of the second
vector do not disturb normal program -execution,
On future CDP6805E2 parts, no special actions will be
necessary. If you have questions, contact your Motorola
distributor or Motorola sales office, or contact Motorola
Microprocessor Applications Engineering in Austin, Texas.
475
RCA CMOS LSI Products
CDP6805E2
CDP6805 FAMILY
~PIIOIP2
ICO..-ea
CMOS
CMOS
CMOS
40
28
40
112
64
112
CDPeIOII2 I
TechnolQ9Y
Number of Pins
On-Chip RAM 18ytesl
On-Chip User ROM I Bytesl
External Bus
Bidirectional I/O Lines
None
1K
2K
Yes
None
None
16
16
32
Unidirectional I/O Lines
None
4 Inputs
None
Other I/O Features
Timer
Timer
Timer
1
1
1
EPROM Version
None
None
None
STOP and WAIT
Yes
Yes
Yes
External Interrupt Inputs.
OPERATING AND HANDLING
CONSIDERATIONS
1. Handling
InputSIIMIi
All inputs and outputs of RCA CMOS devices- have a
network for electrostatic protection during handling. Recommended handling. practices for CMOS devices are described in ICAN-6525, "Guide to Better Handling and
Operation of CMOS Integrated Circuits."
2. Operating
Operating Voltage
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and tum-off transients, power supply ripple, or
ground noise; any of these conditions must not cause
VDD-VSS to exceed the absolute maximum rating.
To prevent damage to the input protection Circuit, Input
Signals should never be greater than VOO nor leas than
VSS. I nput currents must not exceed 10 mA even when the
power supply Is off.
UnUMdlnpute
A connection must be provided at every Input terminal. All
unused input terminals must be connected to either VOO or
VSS, whichever is appropriate.
Output Short Clrculta
Shorting of outputs to VOO or VSS may damage CMOS
devices by exceeding the maximum device dissipation.
Ordering InformaUon
RCA Microprocessor device packages are identified by letters
indicated in the following chart. When ordering a Microprocesor
device, it is important that the appropriate suffix letter be affixed
to the type number of the device.
Package
Dual-In-Line Side-Brazed Ceramic
Dual-In-line Plastic
Suffix Letter
D
E
For example, a CDP6805E2 in a dual-in-line plastic package will
be identified as the CDP6805E2E.
476
6805-Serles LSI Products
Objective Data
RESET
-,
IlIa"
28
27
NUM
26
PCO
4
25
PCI
OSC2
5
24
PC2
PAO
6
7
23
22
PC3
PA2
PA3
8
21
9
20
PBI
PB2
PA4
10
19
PB3
PA5
II
18'
PB4
12
17
PBS
13
14
16
15
PB6
PB7
PAl
PA6
PA7
VSS
CMOS High-Performance Silicon-Gate
a-Bit Microcomputer
VOD
TIMER
OSCI
CDP6805F2
Feature.:
• Typical full speed operating power
of10mWat5 V
• Typical WAIT mode power of 3 mW
• Typical STOP mode power of 25 J}W
• Fully static operation
• 64 bytes of on-chip RAM
• 1089 bytes of on-chip ROM
• 16 bidirectional I/O lines
• 4 input-only lines
• Internal 8-bit timer with software
programmable 7-bit prescaler
• External timer input
• External and timer interrupts
• Self-check mode
• Master reset and power-on reset
PBO
TOP VIEW
92CS~3&031
TERMINAL ASSIGNMENT
The CDP6805F2 Microcomputer Unit (MCU) belongs to the
CDP6805 Family of Microcomputers. This a-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer. The fully static design allows operation at frequencies
down to DC, further reducing its already low-power
•
•
•
•
Single 3 to 6 volt supply
On-chip oscillator
1 ps cycle time
28-pin dual-in-line package
Software Feature.:
•
•
•
•
•
•
•
•
•
Similar to the MC6800
Efficient use of program space
Versatile interrupt handling
True bit manipulation
Addressing modes with indexed
addressing for tables
Efficient instruction set
Memory-mapped I/O
User-callable self-check routines
Two power-saving standby modes
consumption. It is a low-power processor designed for lowend to mid-range applications in the consumer, automotive,
industrial, and communications markets where vf?Jry low
power consumption constitutes an important factor.
RESET
OSCl
NUM
3
2
8
Accumulator
8
A
CPU
Control
Index
Register
PAO
Port PAl
A PA2
PA3
110 PA4
lines PA5
PA6
PA7
8
Port
Data
A
Direction
Register Register
5
X
Condition
Code
Register
CC
Data
Port
Direction
B
Register Register
PBO
PBl
PB2 Port
PB3 B
PB4 110
PB5 lines
PB6
PB7
CPU
Stack
Pointer
5
S
Program
Counter
3
High
8
Program
Counter
Low
PCH
ALU
Self-Check
ROM
Fig. 1 - CDP6805F2 CMOS microcomputer block diagram.
477
RCA CMOS LSI Products
CDP6805F2
MAXIMUM RATINGS. (Voltages Referenced to VSS)
Ratings
Symbol
Value
Unit
Supply Voltage
VOO
All Input Voltages Except OSCl
Yin
VSS-0.5 to VOO+0.5
V
I
10·
mA
TA
TL to TH
to 70
-40 to +85
°C
Tstg
-55 to + 150
°C
Current Drain per Pin EXGluding VOO and VSS
Operating Temperature Range
yOP6805F2
COP6805F2C
Storage Temperature Range
-0.3 to +8
o
V
VOO=4.5V
-
ILoad
Test Point
50 pF
4.27 k
20.5 k
Fig. 2 - Equivalent test load.
«
E 2.5
I
0
,g
6V
IZ
w
a:
a:
5V
:::l
Q
C!l
z
i=
«
a:
w
0..
0
...J
«
Q
a::>I-
INTERNAL FREQUENCY (l/t."c)...,.MHz
Fig. 3 - Typical operating current vs. internal frequency.
478
6805-Serles LSI Products
CDP6805F2
Vdc ± 10%. VSs=O Vdc. TA= TL to TH. unless otherwise noted I ISee Note 11
Characteristics
Symbol
Min
Max Unit
Output Voltage. ILoadS 10.0 p.A
0.1
VOL
V
VDD-O.l
VOH
Output HighVoltage IILoad- 200 p.AI PAO-PA7. PBD-PB7
4.1
V
VOH
Output Low Voltage. ilLoad = BOO p.AI PAO-PA7. PBD-PB7
0.4
V
VOL
Input High Voltage
Ports PAO-PA7. PBO-PB7. PCO-PC3
VOO-2
VOO
V
VIH
TIMER. TIm. i'fESEi
VOD-0.8 VDD
OSCl
~-1.5
VOO
Input Low Voltage. All Inputs
V
0.8
VSS
VIL
Total ~upply Current ICL = 50 pF on Ports. No dc Loads. tcyc= 1 p.sl
RUN IMeasured During Self-Check. VIL=0.2 V. VIH=VDD-0.2 VI
mA
5
IDD
WAiT ISee Note 21
mA
2
STOP (See Note 21
200 LA
1/0 borts Input Leakage - PAO-PA7. PBO-PB7
IlL
± 10 LA
Input Current TIm. TIMER. OSCI. PCO-PC3
p.A
±1
lin
Output Capacitance - Ports A and B
12
pF
Cuill_
Input Capacitance - RESET. IRQ. TIMER. OSC1. PCO-PC3
8
pF
Cin
DC ELECTRICAL CHARACTERISTICS IVDD=5
mrr.
NOTES:
1. Electrical Characteristics for VDD = 3 V available soon.
2. Test Conditions for IDD are as follows:
All ports programmed as inputs
VIL =0.2 V !PAO-PA7. PBO-PB7. PCO-PC31
VIH = VDO - 0.2 V for RESET. iRQ. TIMER
OSCl input is " square wave from 0.2 V to VDD - 0.2 V
OSC2 output load = 20 pF (WAIT 100 is affected linearly by the OSC2 capacitancel
TABLE 1 - CONTROL TIMING CHARACTERISTICS (VDO= 5
Crystal Oscillator Startup Time
Stop Recovery Startup Time Timer Pulse Width I See Figure
Characteristics
(See Figure 51
Crystal Oscillator (See Figure 61
41
51
Reset Pulse Width (See Figure
Timer Period I See Figure 41
Interrupt Pulse Width (See Figure 151
Vdc ± 10%. VSS=O, T A = TL to TH, fosc=4 MHz. tcyc= 1 p.sl
Symbol
tOXDV
tlLCH
tTH. tTL
Min
-
Max
Unit
-
100
100
ms
ms
0.5
-
tcyc
tcye
tcyc
-
tcyc
tcyc
ns
ns
4
4
MHz
tRL
tTLTL
1.5
1
tlLlH
tlLlL
tOH. tOL
*
100
Cycle Time
tcyc
1000
Frequency of Operation
Crystal
External Clock
losc
Interrupt Pulse Period ISee Figure 151
OSC1 Pulse Width (See Figure 71
1
dc
*The minimum period. tILlL, should not be less than the number of tcyc cycles it takes to execute the interrupt service routines plus 20 tcyc
cycles.
479
~
Q)
O::a
o
".
CO
--l
External
Clock
tTH
I--
-+I
tTl
\.-
Timer)
( Pin
27
0»0
<»1:
~O
'TI0
Nr-
!!
'V
a
Fig. 4 - Timer relationships.
Q.
c
,
n
;-
I~-
VDD
%
I
I
ru-v=l\\\\\\\\\\\\\~\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
l~~I~~~~TITI~~~~~~~~~~-
OSC1
-r
I
I
I
I
I
,0(1920 teye.,I
I
I
~toxOV
iI
teye
IJ
~2*
Internal
Address
Bus*
Internal
Data
Bus*
RESET
*
-./'
~
-\
t RL
Internal timing signal not available externally.
Fig. 5 - Power-on RESET and RESET.
t
---,
680S-Serles LSI Products
CDP6805F2
OSC2**
IRQ
or
RESET
----......,~
---r-J
~ 11111111111
V'
; III
------_.0401. .
M"~f-_____
------i.~1
~~---------------------------------------0~----'ILCH
--1920 tCYC
¢2* ___________________________________________--J
* Internal timing Signals not avatlable externally
** Represents the Internal gating of the OSC1 Input pin
Fig. 6 - Stop recovery.
FUNCTIONAL PIN DESCRIPTION
Voo and VSS
Power is supplied to the MCU using these two pins. VOO
is power and VSS is ground.
IRQ (MASKABLE INTERRUPT REQUEST)
IRO is photomask option selectable with the choice of interrupt sensitivity being both level and negative edge or
negative edge only. The MCU completes the current instruction before it responds to the request. If TROis low and the
interrupt mask bit (I bit) in the condition code register is
clear, the MCU begins an interrupt sequence at the end of
the current instruction.
If the photomask OPtion is selected to include level sensitivity, then the IRO input requires an external resistor to
VDD for "wire-OR" operation. See the Interrupt section for
more detail.
RESET
The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly software start-up procedure. Refer to the Resets section
for a detailed description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to the Timer section for a detailed
description.
NUM (NON-USER MODE)
This pin is intended for use in self-check only. User applications should leave this pin connected to ground through
a 10 kilohm resistor.
OSC1, OSC2
The CDP6805F2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived from either a divide-by-two or divideby-four of the external frequency (fosc). Both of these options are photomask selectable.
RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b/.
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(al is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for f osc in
the electical characteristics table. Using an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VOD. Refer to Table 1,
Control Timing Characteristics, for limits.
EXTERNAL CLOCK - An external clock should be applied to the 05Cl input with the 05C2 input not connected,
as shown in Figure 7(c). An external clock may be used with
either the RC or crystal oscillator mask option. toxOV or
tlLCH do not apply when using an external clock input.
PAO-PA7
These eight I/O lines comprise Port A. The state of any pin
is software programmable. Refer to the Input/Output Programming section for a detailed description.
481
I
RCA CMOS LSI Products
CDP6805F2
Crystal Parameters
Oscillator Waveform
Units
1 MHz
4 MHz
400
75
0
7
pF
Cl
5
0.008
0.012
/,F
COSCl
15-40
15-30
pF
COSC2
Rp
15-30
1525
pF
10
10
MO
30k
40 k
RSMAX
Co
0
lal Crystal Oscillator Connections and Equivalent Crystal Circuit
CDP6805F2
OSCl
4
.OSC2
Rp
5
o
-5'--------110
4
1-1_ _ _
COSCl
Ibl
RC Oscillator Connection
lei External Clock Source Connections
CDP6805F2
OSCl
CDP6805F2
OSC2
R
OSC1
OSC2
4
!5
Unconnected
External Clock
Fig. 7 - Oscillator connections.
482
6805-Serles LSI Products
CDP680SF2
PBO-PB7
These eight lines comprise Port B. The state of any pin is
software programmable. Refer to the Input/Output Programming section for a detailed description.
PeG-PC3
These four lines comprise Port C, a fixed input port. When
Port C is rea(j, the four most-significant bits on the data bus
are "'s" . There is no data dir.ection register associated with
Port C.
TBD
INPUT/OUTPUT PROGRAMMING
Any Port A or B pin may be software programmed as an
input or output by the state of the corresponding bit in the
port data direction register IDDRl. A pin is configured as an
output if its corresponding DDR bit is set to a logic "'''. A
pin is configured as an input if its corresponding DDR bit is
cleared to a logic "0". At reset, all DDRs are cleared, which
configures all port pins as inputs. A port pin configured as an
output will output the data in the corresponding bit of its
port data latch. Refer to Figure 9 and Table 2.
RlkOl
Fig. 8 - Frequency vs. resistance for
RC oscillator option only.
la)
Internal
CDP6805F2
Connections
Ibl
I
Typical Port
Data Direction '
Register
Typical Port
Register
Pin
P-7
P-6
P-5
P-4
P-3
P-2
P-l
p-o
Fig. 9 - Typical I/O port circuitry.
TABLE 2 -
R/W
OOR
0
0
0
1
I
0
1
1
1/0 PIN. FUNCTIONS
110 Pin Function
The 1/0 pin is in input mode. Data is written into the output data latch.
Data 15 written IOta the output data latch and output to the 1/0 plO.
The state of the 1/0 pIn 15 read.
The 1/0 pIn IS 10 an output mode. The output data latch IS read
483
RCA CMOS LSI Products
CDP680SF2
The RAM test must be called with the stack pointer at $7F
and the accumulator zeroed. When run. the test checks
every RAM cell eKeept for $7F and $7E which are assumed to
contain the retum address.
A and X are modified. All RAM locations eKeept the top 2
are modified. (Enter at location $78B.l
SELF-CHECK
The CDP6805F2 self-check is performed using the circuit
in Figure 10. Self-check is initiated by tying NUM and TIMER
pins to a logic "1" then executing a reset. After reset. the
following five tests are executed automatically:
1/0 - Functionally Exercise Ports A. B. C
RAM - Walking Bit Test
ROM - Exclusive OR with ODD "ls" Parity Result
Timer - Functionally Exercise Timer
Interrupts - Functionally Exercise External and Timer Interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not reQuire any external hardware.
ROM CHECKSUM SUBROUTINE
Returns with Z bit cleared if any error wes found; otherwise Z = 1. X =0 on return. and A is zero it the test passed.
RAM locations $40-$43 are overwritten. (Enter at location
$7A4.1
TIMER TEST SUBROUTINE
Return with Z bit cleared if any error was found; otherwise
TABLE 3 - SELF-CHECK RESULTS
Z=1.
PB3
1
PB2
PBO
0
PBI
1
1
1
1
0
0
1
0
Bad Timer
Bad RAM
1
1
1
1
0
Bad ROM
Bad Interrupt or Request Flag
This routine runs a Simple test on the timer. In order to
work correctly as a user subroutine. the internal clock must
be the clocking source and interrupts must be disabled.
Also. on eKit. the clock will be running and the interrupt
mask will not be set. so the caller must protect himself from
interrupts if necessary.
A and X register contents are lost; this routine counts how
many times the clock counts in 128 cycles. The number of
counts· should be a power of two since the prescaler is a
power of two. If not. the timer probably is not counting correctly. The routine also detects if the timer is running at all.
(Enter at location $7BE.1
.
Remarks
1
All Cycling
Good Part
Bad Part
All Others
RAM SELF-CHECK SUBROUl:INE
Returns with the Z bit clear if any error is detected; otherwise. the Z bit is set.
+5V+5V
10 k
+5 V +5 V
> ~ 10 k
•
••
1
;6 :-:1:
0
--
:~10 k
.>
.
2
.....2.
VOO
RESET
IRQ
TIMER
PCl
XTALJ OSC2
PC2
7
8
9
~
1...-!2
12
13
GNO.l1
PAO
PAl
PC3
COP6805F2
PBO
PA2
PBl
PA3
PB2
PA4
PB3
PA5
PB4
PA6
PB5
PA7
PB6
VSS
27
pco ~
NUM
XTAL...! OSCI
~
~
PB7
~ to24
23
tBtE- to20
19
18
17
16
15
Fig. 10 - Self-check pinout configuration.
484
6aOS-SerlesLSI Products
CDP680SF2
MEMORY
The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to $7F
and it is decremented as data is pushed on the stack. When
data is removed from the stack, the Slack pointer is incremented. A maximum of 32 bytes of RAM are available for
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and I or subroutine
stacking purposes, the unused bytes are available for program data storage.
The CDP6805F2 has a total address space of 2048 bytes
of memory and 1/0 registers. The address space is shown in
Figure ".
The first 128 bytes of memory (first half of page zero) is
comprised of the 1/0 port locations, timer locations, and 64
bytes of RAM. The next 1079 bytes comprise the user ROM.
The 10 highest address bytes contain the reset and interrupt
vectors.
$0000
Access
[
Via
Page 0
Direct
Addressing
liD Ports
Timer
RAM
0
0
255
1079 Bytes
User ROM
I
$0002
4
Port A Data Direction Register
$0004
5
Port B Data Direction Register
2
3
$OOFF
$0100
256
$0000
$0001
Port C
$007F
$0080
,
127
128
Port A Data Register
Port B Data Register
1 1 1 1
6
1279
1280
Timer Data Register
$0008
9
Timer Control Register
$0009
$oooA
54 Bytes
Unused*
$04FF
$0500
63
$003F
64
$0040
640 Bytes
Unused*
1919
1920
2037
2038
User
Defined
Interrupt
Vectors
[
118 Bytes
Self-Check ROM
RAM
(64 Bytes)
$077F
$0780
1------------Timer Interrupt From Wait State Only
1 - - -Timer
- -Interrupt
-----1---External Interrupt
1-----
r---2047
* Reads of unused locatIOns undefined
95
96
$07F5
$OO5F
I--
/ / $0060
/
$07F6 $07F7
I
$07F8 $07F9
/
RESET
$07FA$07FB
.".
I
./ ./ Stack (32 Bytes Max)
$07FC $07FD
$07FE $07FF
./
127
..-
..-
/
/
I
SWI
$0007
Unused *
8
10
$04B6
$0487
73 Bytes
Self-Check ROM
$0005
$0006
Unused *
7
1206
1207
$0003
Unused *
./
./
+
$007F
Fig. 11 - Address map.
485
RCA CMOS LSI Products
CDP680SF2
PROGRAM COUNTER (PC)
The program counter is an ll-bit register that contains the
address of the next instruction to be executed by the processor.
REGISTERS
The CDP6805F2 contains five registers as shown in the
programming model (Figure 12). The interrupt stacking order
is shown in Figure 13.
STACK POINTER (SP)
The stack pointer is an ll-bit register containing the address of the next free location on the stack. When accessing
memory, the six most-significant bits are appended to the
five least-significant register bits to produce an address
within the range of $7F to $60. The stack area of RAM is
used to store the return address on subroutine calis and the
machine state during interrupts. During external or power-on
reset, and during a "reset stack pointer" instruction. the
stack pointer is set to its upper limit ($7F)' Nested interrupts
and/ or subroutines may use up to 32 (decimal) locations
beyond which the stack pointer "wraps around" and points
to its upper limit thereby losing the previously stored information. A subroutine cali occupies two RAM bytes on the
stack, while an interrupt uses five bytes.
ACCUMULATOR (A)
This accumulator is an B-bit general purpose register used
to hold operands and results of the arithmetic calculations
and data manipulations.
INDEX REGISTER (X)
The X register is an B-bit register which is used during the
indexed modes of addressing. It provides the B-bit operand
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addressing operations.
0
1 Accumulator
0
7
I
A
7
I
10
X
I ndex Register
I
Program Counter
0
I
PC
5
10
1
I
0 1010101 11
I
0
1 Stack POinter
4
SP
Condition Code Register
Carry/ Borrow
Zero
' - - - - - Negative
' - - - - - - Interrupt Mask
' - - - - - - - - Half Carry
Fig. 12 - Programming model.
o
7
1I 1I 1 I
Condition Code Register
Accumulator
Increasing Memory
Addresses
n
Decreasing Memory
Addresses
Index Register
11 0101010101
Stack
PCH
PCl
Unstack
T
NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling frQm the stack IS in
the reverse order.
Fig. 13 - Stacking order.
486
6805-Serles LSI Products
CDP6805F2
CONDITION CODE REGISTER (CC)
The condition code" register is a 5-bit register which indicates the results of the instruction just executed. These
bits can be indiVidually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.
HALF CARRY BIT (H) - The H bit is set to a "1" when a
carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and is
processed when the I bit is next cleared.
NEGATIVE (N) - Indicates that the result of the last
arithmetic, logical, or data manipulation is negative (bit 7 in
the result is a logical" 1" I.
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external RESET pin is low at the end of the 1920
time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:
• Timer control register interrupt request bit (TCR7) is
cleared to a "0".
• Timer control register interrupt mask bit (TCR6) is set
to a "1".
• All data direction register bits are cleared to a "0". All
ports are defined as inputs.
• Stack pointer is set to $7F.
• The internal address bus is forced to the reset vector
($7FE, $7FFl
• Condition code register interrupt mask bit (I) is set to a
"1" .
• STOP and WAIT latches are reset.
• External interrupt latch is reset.
All other functions, such as other registers (including output ports), the timer, etc., are not cleared by the reset conditions.
ZERO (Z) - Indicates that the f()sult of the last arithmetic,
logical, or data manipulation is zero.
CARRY /BORROW (C) - Indicates that a carry or borrow
out of the arithmetic logic unit (ALUI occurred during the
last arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.
RESETS
The CDP6805F2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 5.
RESET
The RESET input pin is used to reset the MCU to provide
an orderly software start-up procedure. When using the external reset mode, the RESET pin must stay low for a
minimum of one tRL. The RESET pin is provided with a
Schmitt Trigger input to improve its noise immunity.
POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
INTERRUPTS
Systems often require that normal processing be interrupted so that some external event may be serviced. The
CDP6805F2 may be interrupted by one of three different
methods, either one of two maskable interrupts (external input or timer) or a non-maskable software interrupt (SWI).
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask set to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and return to normal processing.
The stacking order is shown in Figure 13.
Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered
pending until the current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. Refer to Figure 14 for the interrupt and instruction
processing sequence.
487
I
RCA CMOS LSI Products
CDP680SF2
TIMER INTERRUPT
Each time the timer decrementR to zero (transitions from
$01 to $00), the timer interrupt request bit (TCR7) is set. The
processor is interrupted only if the timer mask bit (TCR6) and
interrupt mask bit (I bit! are both cleared. When the interrupt
is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code
register is set. This mask prevents further interrupts until the
present one is serviced. The processor now vectors to the
1-1 Bit lin CCR)
07F-SP
O-DDRs
CLR IRQ Logic
FF-Timer
7F-Prescaler
7F-TCR
timer interrupt service routine. The address for this service
routine is specified by the contents of $7F8 and $7F9 unless
the processor is in a WAIT mode, in which case the contents
of $7F6 and $7F7 specify the timer service routine IIddress.
Software must be used to clear the timer interrupt request
bit (TCR71. At the end of the timer interrupt service routine,
the software normally executes an RTI instruction which
restores the machine state and starts executing the interrupted program.
lear
IRQ
Request
Latch
Stack
PC.X.A.CC
Timer
Put 7FE on
Address Bus
Load PC From:
SW): 7FCI7FDIRQ: 7FA17FB
TIMER: 7F817F9
Timer Wait: 7F617E7
Fetch
Instruction
PC-PC+ 1 I-S;;..;W..;.;I-iO'
Load PC
from
7FE17FF
Execute All
Instruction
Cycles
Fig. 14 -
488
iiEffi" and INTERRUPT proceas/ng flowchart.
8805-Serle. LSI Product.
CDP6805F2
EXTERNAL INTERRUPT
...,
I
struction; refer to Figure 15. The second configuration
shows many interrupt lines "wire ORed" to form the interrupts at the processor. Thus, if after servicing an interrupt
the iRO remains low, then the next interrupt is recognized.
Either level- and edge-sensitive or edge-sensitive onl'y inputs are available as mask options. If the interrupt mask bit
of the condition code register is cleared and the external interrupt pin (lml) is "low" or a negative edge has set the internal interrupt flip-flop, then the external interrupt occurs .
The action of the external interrupt is identical to the timer
except that the service routine address is specified by the
contents of $7FA and $7FB. Figure 15 shows both a functional diagram and timing for the interrupt line. The timing
diagram shows two different treatments of the interrupt line
flRC) to the processor. The first method is single pulses on
the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of
the interrupt service routine. Once a pulse occurs, the next
pulse should not occur until the MPU software has exited the
routine Ian RTI occursl. This time·(tILlL) is obtained byadding 20 instruction cycles Itcycl to the total number of cycles
it takes to complete the service routine including the RTI in-
SOFlWARE INTERRUPT ISWII
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $7FC and $7FD.
The following three functibns are not strictly interrupts,
however, they are tied very closely to the interrupts. These
functions are RESET, STOP, and WAIT.
RESET - The RESET input pin and the internal power-on
reset function each cause the program to vector to an initialization program. This vector is specified by the contents
lal Intenupt Functional Diagram
Level Sensitive
Mask Option
VDD ,....--.,
External
Interrupt
Request
Q~----I
D
Interrupt Pin - - - -....--~CIIIC
Q
I Bit ICeR)
R
Power-On Reset
External Reset
External Interrupt
Being Serviced
Ibl Interrupt Mode Diagram
11)
IRQ~tILlH
~
121
U
tILlL~1
Edge Condition
I
The minimum pulse width ItILlH) is one
tcye. The period tlLlL should not be less
than the number of teyc cycles it takes to
execute the interrupt service routine plus
20 tCYC cycles.
iRa IMPUI---,L-_ _ _ _ _ _ _ _ _ _ _ _ _ _~
Mask Optional Level Sensitive
If after servicing an interrupt the I RQ remains low. then the next interrupt is
recognized .
•
•
iROn
Fig. 15 - External interrupt.
489
RCA CMOS LSI Products
CDP6805F2
of memory locations $7FE and $7FF. The interrupt mask of
the condition code register is also set. See preceding section
on Reset for details.
STOP - The STOP instruction places the CDP6805F2 in
its lowest power consumption mode. In the STOP function,
the internal oscillator is turned off causing all internal processing and the timer to be halted; refer to Figure 16.
During the STOP mode, timer control register (TCRI bits 6
and 7 are altered to remove an." pending timer interrupt requests and to disable any further timing interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All 1/0 lines
remain unchanged. The processor can only be brought out
of the STOP mode by an external IRQ or RESET.
Stop
Stop Oscillator
And All Clocks
TCR Bit 7-0
Bit 6-1
Clear I Mask
Yes
T urn on Oscillator
Fig. 16 - Stop function flowchart.
490
WAIT - The WAIT instruction places thelCDP6805F2in
a low-power consumption mode, but the WAIT mode consumes somewhat more power than the STOP mode. In the
WAIT mode, the internal clock is disabled from all internal
circuitry except the timer circuit; refer to Figure 17. Thus, all
internal processing is halted, however, the timer cOntinues
to count normally.
During the WAIT 'mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers.
memory. and 1/0 lines remain in their last state. The timer
may be enabled by software prior to entering the WAIT
mode to allow a periodic exit from the WAIT mode. If an external and a timer interrupt occur at the same time. the external interrupt is serviced first; then. if the timer interrupt request is not cleared in the external interrupt routine. the normal timer interrupt (not the timer WAIT interrupti is serviced
since the MCU is no longer in the WAIT mode.
TIMER
The MCU timer contains an 8-bit software programmable
counter with a 7-bit software selectable prescaler. Figure 18
contains a block diagram of the timer. The counter may be
preset under program control and decrements towards zero.
When the counter decrements to zero, the timer interrupt request bit (i.e., bit 7 of the timer control register (TCRII is set.
Then, if the timer interrupt is not masked (i.e., bit 6 of the
TCR and the I bit in the condition code register are both
cleared I the processor receives an interrupt. After completion of the current instruction, the processor proceeds to
store the appropriate registers on the stack and then fetches
the timer vector address from locations $7F8 and $7F9 (or
$7F6 and $7F7 if in the WAIT model in order to begin servicing.
The counter continues to count after it reaches zero allowing the software to determine the number of internal or external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The contents of the counter
become stable. prior to the read portion of a cycle. and do
not change during the read. The timer interrupt request bit
remains set until cleared by the software. TCR7 may also be
used as a scanned status bit in a non-interrupt mode of
operation (TCR6= 11.
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output within the range of + 1 to + 128 which is uSed as the
counter input. The processor cannot write into or read from
the prescaler, however, its contents are cleared to all "Os" by
the write operation into TCR when bit 3 of the written data
equals one. This allows for truncation-free counting.
The timer input can be configured for three different
operating modes plus a disable mode depending on the value
written to the TCR4 and TCR5 control bits. Refer to the
Timer Control Register section.
TIMER INPUT MODE 1
If TCR5 and TCR4 are both programmed to a "0", the input to the timer is from an internal clock and the TIMER input pin is disabled. The internal clock mode can be used for
6805-Serles LSI Products
CDP6805F2
1
Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop
No
No
Fetch External
Interrupt, Reset,
or Timer Interrupt
Vector Hrom Wait
Mode only)
I
Fig. 17 - WAIT function flowchart.
periodic interrupt generation as well as a reference in frequency and event measurement. The internal clock is the instruction cycle clock. During a WAIT instruction, the internal
clock to the timer continues to run at its normal rate.
TIMER INPUT MODE 3
If TCRS= 1 and TCR4==O, all inputs to the timer are disabled.
TIMER INPUT MODE 4
TIMER INPUT MODE 2
With TCRS=O and TCR4== 1, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the
count in this mode is ± one internal clock and therefore, accuracy improves with longer input pulse widths.
If TeRS== 1 and TCR4== 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The timer can, in this mode, be used to count
external events as well as external frequencies for generating
periodic interrupts. The counter is clocked on the falling
edge of the external signal.
Figure 18 shows a block diagram of the timer subsystem.
Power-on reset and the STOP instruction invalidate the contents of the counter.
491
RCA CMOS LSI Product.
CDPS,05F2
Software Selectable
Input and Prescaler Options
External
Input
r-~--_A~__~==~
Internal
Clock
Clear
~,
Write
__________
• T,mer: 8-Bit Read/Write Counter
7-Bit Software Selectable Prescaler
Inpui Pin
Timer Interrupt
Read
~",
Interrupt
__________-J'
Software Functions
Fig. 18 - Progr.mmable tImer/counter block dIagram.
TIMER CONTROL REGISTER ITCR)
7
S
543210
ITCR71TCRSITCR51TCR41TCR31TCR21 TCR11TCROI
All bits in this register except bit 3 are read/write bits.
TCR7 - Timer interrupt request bit: bit I,lsed to indicate
the timer interrupt when it is logic "1".
1 - Set whenever the counter decrements to zero or
under program control.
o - Cleared on external
power-on reset. STOP
instruction. or program control.
mrr.
TCR6 - Timer interrupt mask bit: when this bit is a logic
"1". it inhibits the timer interrupt to the processor.
1 - Set on external Atm. power-on reset. STOP instruction. or program control.
Cleared under program control.
o-
TCR5 - External or internal bit: selects the input clock
source to be either the external timer pin or the internal
clock. (Unaffected by
1 - Select external Clock source.
~ Select internal clock source.
mrr.1
o
TCR4 - External enable bit: control bit us$(! to .enable the
external TIMER pin. (Unaffected by
1 - Enable external TIMER pin.
o - Disable external TIMER pin.
mrr.)
TCR5 TCR4
0
0 Internal Clock to Timer
0
1 AND of Internal Clock and TIMER
Pin to Timer
1
0 Inputs to Timer Disabled
1
1 TIMER Pin to Timer
492
TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always iodicates "0". (Unaffected by
mrr.)
TCR2, TCR1, TCRO - Pre,scaler select bits: decoded to
select ,one of eight outputs on the prescaler. (Unaffected by
"RtS"Ei.)
Prescaler
TCR2
0
0
0
0
TCRl
0
0
TCRO
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
1
1
1
Result
+1
+2
+4
+8
+16
+32
+64
+128
INSTRUCTION SET
The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory. readmodify-write. branch. bit manipulation. and control. The
following paragraphs briefly explain each type. AU the instructions within a given type are presented in individual
'
tables.
REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumuilitor or the index register. The
other operand is obtained from memory using one of the addressing modes. The operand for the jump unconditional
(JMP) and jump to subroutine (JSR) instructions is the program counter. Refer to Table 4.
6805-Serles LSI Products
CDP6805F2
READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back. to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modifywrite sequence since it does not modify the value. Refer to
Table 5.
BRANCH INSTRUCTIONS
Most branch instructions test the state of the condition
code register and, if certain criteria arE! met, a branch is executed. This adds an offset between -127 and + 128 to the
current program counter. Refer to Table 6.
BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 128 bytes of the memory space where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within the first 256
locations. The bit set, bit clear, and bit test and branch functions are implemented with a single instruction. For the test
and branch instructions, the value of the bit tested is also
placed in the carry bit of the condition code register. Refer to
Table 7.
CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8.
OPCODE MAP
Table 9 is an opcode map for the instructions used on the
MCU.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 10.
ADDRESSING MODES
The MCU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single-byte instructions while the longest instructions (three bytes) permit tables throughout memory.
Short and long absolute addressing is also included. Twobyte direct addressing instructions access all data bytes in
most applications. Extended addressing permits jump instructions to reach all memory. Table 10 shows the addressing modes for each instruction with the effects each instruction has on the condition code register. An opcode map is
shown in Table 9.
The term "Effective Address" (EA) is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of," an arrow indicates "is replaced by," and a
'colon indicates" concatenation of two bytes."
INHERENT
In inherent instructions, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index registers or accumulator and
no other arguments are included in this mode.
IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter!.
EA=PC+1; PC-PC+2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a Single two-byte instruction. This includes all on-chip RAM and 1/0 registers
and 128 bytes of on-chip ROM. Direct addressing is efficient
in both memory and time.
EA= (PC+ 1); PC+ PC+2
Address Bus High-O; Address Bus Low-(PC+1)
EXTENDED
In the extended addressing mode, the ef·fective address of
the argument is contained in the two bytes following the op,code. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three-byte instruction. When using the CDP6805
assembler, the user need not specify whether an instruction
uses direct or extended addressing. The assembler
automatically selects the most efficient addressing mode.
EA= (PC+ 1);(PC+2); PC-PC+3
Address Bus High-(PC+1); Address Bus Low-(PC+2)
INDEXED, NO-OFFSET
In the indexed, no-offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or 1/0 location.
EA=X; PC-PC+1
Address Bus High-O; Address Bus Low-X
INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register, therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the mth element in an n element table. All
instructions are two bytes. The content of the index register
493
I
RCA CMOS LSI Products
CDP6805F2
(X) is not changed. The content of (PC+ 1) is an unsigned
8-bit integer. One-byte offset indexing permits look-up tables
to be easily access.ed in either RAM or ROM.
EA=X+(PC+1); PC-PC+2
Address Bus High-K; Address Bus Low-X+(PC+1)
where K = The carry from the addition of X + (PC + 1)
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three-byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the assembler
determines the most efficient form of indexed offset - 8
or 16 bit. The content of the index register is not
changed.
EA=X+[(PC+1);(PC+2)J; PC-PC+3
Address Bus High - (PC + 1) + K;
Address Bus Low-X+(PC+2)
where K = The carry from the addition of X + (PC + 2)
RELATIVE
Relative addressing is only used in branch instructions. In
relative addressing, the contents of the 8-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
is limited to the range of - 126 to + 129 bytes from th~
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
494
EA= PC+2+ (PC+ 11; PC- EA if branch taken;
otherwise, PC-PC+2
BIT SETICLEAR
Direct addressing and bit addressing are combined in instructions which' set and clear individual memory and 1/0
bits. In the bit set and clear instructions, the byte is sPE\Cified
as a direct address in the location following the opcode. The
first 128 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the
opcode. The bit set and clear instructions occupy two bytes:
one for the opcode (including the bit number) and the second for addressing the byte which contains the bit of interest.
EA=(PC+1I; PC-PC+2
Address Bus High-O; Address Bus Low-(PC+ l)
BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit addressing, and relative addressing. The bit address and
condition (set or ciear) to be tested is part of the opcode.
The address of the byte to be tested is in the Single byte immediately following the opcode byte (EAl). The Signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or cleared in the specified
memory location. This Single three-byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1=(PC+l)
Address Bus High-O; Address Bus Low-(PC+ l)
EA2= PC+3+ (PC+2); PC-EA2 if branch taken;
otherwise, PC- PC+ 3
_I
TABLE 4 -
REGISTER/MEMORY INSTRUCTIONS
Addressing Modes
Immediate
Mnemonic
Op
Code
Direct
,
,
Bytes
Cycles
Op
Code
Indexed
INo Offset)
Extended
,
,
Bytes
Cycles
,
Op
Code
Bytes
I
Cycles
Load A from Memory
LOA
A6
2
2
B6
2
3
C6
3
4
Op
Code
F6
Load X from Memory
LOX
AE
2
2
BE
2
3
CE
3
4
FE
Function
Indexed
IS-Bit Offset)
I
Bytes
I
Cycles
Indexed
I1t-Bit Offset)
I
I
Op
I
Bytes
Cycles
Code
ByteS
3
Op
Code
E6
2
3
5
EE
2
4
4
D6
3
E7
2
5
6
4
EF
2
OF
3
EB
2
5
4
3
3
3
5
4
DE
07
DB
3
5
I
Store A In Memory
STA
B7
2
4
C7
3
STX
BF
2
4
CF
3
5
°5
F7
Store X In Memory
Add Memory to A
Add Memory and
Carry to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
1
1
1
1
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract Memory
SUB
AO
2
2
BO
2
3
CO
3
4
FO
1
3
EO
2
4
DO
3
5
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
02
3
5
AND Memory to A
AND
A4
2
B4
C4
3
E4
04
3
BA
3
CA
3
FA
3
EA
2
2
4
2
1
1
3
AA
4
4
F4
ORA
2
2
3
OR Memory with A
2
2
4
OA
3
5
5
Exclusive OR Memory
With A
EOR
AB
2
2
BB
2
3
CB
3
4
FB
1
3
E8
2
4
08
3
5
CMP
Al
2
2
Bl
2
3
Cl
3
4
Fl
1
3
El
2
4
01
3
-5
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
03
3
5
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
05
3
5
JMP
-
-
-
BC
CC
3
3
FC
EC
2
3
OC
3
4
5
CD
3
6
FD
1
1
2
BD
2
2
2
-
5
ED
2
6
00
3
7
ArlthmeliC Compare A
With Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A (Logical Compare)
Jump Unconditional
Jum-,,-~~b-,-ou~n~ __
-
JSR
-
TABLE 5 -
FF
I
Cycles ;
6
READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes
Inherent (AI
Function
.,..
~
Mnemonic
Inherent IXI
Indexed
INo Offset)
Direct
Op
Code
I
Bytes
#
Cycles
Op
Code
#
Bytes
Cycles
1
3
3
#
Op
Code
7C
I
I
Bytes
Cycles
1
5
6
5
2
6
5
1
1
6C
6A
2
7A
7F
5
6F
2
6
5
73
1
5
63
2
6
#
#
Bytes
Cycles
3C
3A
2
5
2
5
3
3F
3
33
2
2
Op
Code
Indexed
It-Bit Offset)
Op
Code
#
#
Bytes
Cycles
Increment
INC
4C
1
3
Decrement
4A
5C
5A
3
5~
Complement
COM
43
1
1
1
3
Clear
OEC
CLR
3
53
1
1
1
Negate
(2's Complement)
NEG
40
1
3
50
1
3
30
2
5
70
i
5
60
2
6
Rotate Left Thru Carry
ROL
49
1
3
59
1
3
39
2
5
79
1
5
69
2
6
4F
G)
CD
,
I
o
en
I
o
.
CD
CD
Or0 0
CIt
Rotate Right Thru
Carry
ROR
46
1
3
56
1
3
36
2
5
76
1
5
66
2
6
Logical Shift Left
LSL
48
1
3
1
3
3B
2
5
7B
1
5
6
LSR
1
3
1
3
34
2
5
74
1
5
2
6
ArithmetiC Shift Right
ASR
44
47
68
64
2
Logical Shift Right
58
54
1
3
57
1
3
37
2
5
17
1
5
67
2
6
Test for Negative
or Zero
TST
40
1
3
50
1
3
3D
2
4
7D
1
4
60
2
5
'V:;
:a
oc:a.
(lie
"a
NCIt
RCA CMOS LSI Product.
CDP8805F2
TABLE 8 - BRANCH INSTRUCTIONS
Rellltive AddlUlinlJ Modi
Function
Mnemonic
Op
Code
BRA
20
Branch Never
Branch IFF Higher
Branch IFF lower or Same
Branch IFF Carry Clear
(Branch IFF Higher or Samel
Branch IFF Carry Set
(Branch IFF lowerl
BRN
BHI
BlS
BCC
(BHSI
21
Branch IFF Not Equal
Branch IFF Equal
Branch IFF Half Carry Clear
BNE
BEQ
BHCC
26
27
Branch IFF Half Carry Set
Branch IFF Plus
Branch IFF Minus
Branch IFF Interrupt Mask Bit is Clear
Branch IFF Interrupt Mask Bit is Set
Branch IFF Interrupt Line is low
Branch IFF Interrupt Line is High
B'ranch to Subroutine
BHCS
BPl
BMI
29
Branch Always
TABLE 7 -
I
I
Bvtei
2
2
Cyclet
2
3
3
3
22
23
24
25
28
2A
2B
2C
20
2E
2F
AD
BMC
BMS
Bil
BIH
BSR
3
2
2
2
2
2
24
25
BCS
(BlOI
'J
3
3
3
2
2
2
3
3
3
2
2
2
2
2
2
2
3
2
6
3
3
3
3
3
3
BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Setl Clear
Function
Branch IFF Bit n is Set
Branch IFF Bit n is Clear
Set Bit n
Clear Bit n
#
#
Bytes
Cycles
-
-'
-
-
10+ 2-n
2
11 + 2-n
2
5
5
Mnemonic
Op
Code
BRSET n In'" 0... 71
BRClR n In'" 0 ... 71
BSET n (n=O .. 71
-
BClR n In=0 ... 71
Bit Test and Branch
Op
#
I
Bytes
Cycles
Code
2-n
3
5
01 + 2-n
3
5
-
-
TABLE 8 - CONTROL INSTRUCTIONS
Inherent
Function
Transfer A to X
Transfer X to A
Set Carry Bit
Clear Carry Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
Software Interrupt
Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
Stop
Wait
496
Mnemonic
Op
I
Code
Bvtei
1
TAX
97
TXA
SEC
ClC
SEI
9F
Cli
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
99
98
9B
9A
1
1
1
1
81
1
1
1
80
9C
1
1
90
8E
8F
1
1
1
83
,
Cyclee
2
2
2
2
2
2
10
8
9
2
2
2
2
-
--1 __
TABLE 9- INSTRUCTION SET OPCODE MAP
B_
Bil
~
.2.,
,
0lI01
2
00'0
~,
oit.,
ol1"
c:u
~
-'
I,BRClRO' 12 BCl~~C
BTB
BRCl!\':
5
BRSEJ1.
,.'
BRClrlR
5
1lT.,
~,
BRSEJts.
9
BRCl::.
1011
,~
,Po,
11\'
F
1111
•
,
o,~,
NEG '
1
oT.,
01~0
Q~
NEG 3
'NH
INH
0
, NEG
IXl
NEG
1
BHI 3
AF'
5
3
I, BCl~~r I, BlSA.. "
5
3
!, BSE1~r I, BCCRF , ,
5
3
, BCL~~r I, BC~REL
5
3
,BSE~e 12 BNE,.EL 2
3
2 BCl~~e i 2 BEO"EL ,
,3
2 BSE1~c i 2 BHC~EL 2
3
5
2 BCL':c ! 2 BHC~EL 2
5
3
2 BSE1~c i, BPlAH 2
RTI
'X
1
5
.'
5
BRSE;::;;:
r'
BRCl:;.
..
..
,'
BCl~~r
5
COMD'A
1 COM~H
5
3
lS~TA
5
ASRD'A
5
lSlD'A
5
ROlOiA
5
DECOlA
,
,.
.'
LSRA
'NH
1
1
ROR~H
COM~H 2 COM,. 1
6,
LSR
3
1
'Xl
3
,
3
, INCAINH
1
TST~NH
3
1
ClRA
INH
3
INCX
INH
TSTX 3
,
NH
1
2
2
3
, CLRXINH
-
1
1
6
ROR~H 2 ROR",
3
6
ASRX
, ASR
1
INH 1
'NH
'Xl
6
lSlX 3 2 lSL
1 lSl~NH 1
INH
'Xl
3
3
6
ROlA
ROLX
ROl
IXl
1
INH '}
'NH 1
3
3
6
DECA
DECX
DEC
INH 2
IXI
'NH 1
ASRA
5
6
3
1 lSR;<"H ,
3
5
RORO'A
BMI •
,
I,
RFt
,
3
5
I ]BRSEJ~. , BSE1~r I, BM ()pcoda in
~IX~
7
"
~
Hexadecimal
Opcode in Binary
(Dl) .....--
Address Mode
I0»
i
n, r-
0-
'11:;;
G ..
-
Z:a.
en' c
,.: 0
N,tr
RCA CMOS LSI Products
CDP6805F2
TABLE 10 -
INSTRUCTION SET
Addressing Modes
Mnemonic
Inherent
ADC
ADD
AND
ASl
ASA
BCC
BClR
BCS
BEQ
BHCC
BHCS'
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BAA
BAN
BAClR
BASET
BSEl
BSA
ClC
CLI
ClA
CMP
COM
CPX
DEC
EOA
INC
JMP
JSA
LDA
lOX
lSl
lSA
NEG
NOP
OAA
AOl
AOA
ASP
ATI
ATS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
Immediate
Direct
Extended
x
X
x
X
X
"X
"X
Relative
X
X
X
X
Indexed
(8 Bits)
Indexed
(16 Bits)
X
X
X
X
X
X
X
X
"X
Setl
Clear
Bit
Test &
Branch
X
H
A
I
N Z C
•
A A A
•
•
•• •• ••
,•• • •
•• ••• •••
• • ••
• A• ••
A
• • ••
•• •• •
•• •• •
•
I.•• •• ••
•• •• •
A
••• •• ••
0
••0 ••1 •
•
A A
X
X
X
X
X
X
X
X
X
X
X
X
X
·1·
X
X
X
X
X
-•• •• - -
X
X
X
X
X
I-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
"
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
..• ••
l·
•
•0
•
I·
X
X
•
H Half Carry (From BI1 31
r Interrupt Mask
N Negative (Sign Bltl
A
Test and Set If True. Cleared OtherWIse.
•
Not Affected
Z
Zero
o
C
Carry/Borrow
Load CC Register From Stack
Cleared
Set
'
.
A
A A 1
• A
A
A
•
•• •AA A •
•• • A•• ••
•
• A
•• •• 0A AA AA
•••
•• •• A• A• A•
•••••
•• •1 • •• •1
• •A A
•• •0 A• •A •••
•• • A A
• • A I- •
•• •• •A •A ••
o •
•
A
• A
A _
-- --·--A
A
A
A
A
A
A
A
A
A
A
• _A ~-
- -- - -I-
X
A IA
A
A
A
A A A
A A A
·1-
X
X
ConditIon Code Symbols
498
Bit
X
X
coo.
Condition
Indexed
(No Offset)
I-
680S-Serles LSI Products
CDP6805F2
To minimize power consumption, all unused ROM locations
should contain zeros.
(OOOO-007F) bytes of the EPROM correspond to the
CDP6805F2 internal RAM and 1/0 ports and will be ignored
when generating ROM masks. The 831 unused and selfcheck bytes (0487-07F5) will also be ignored when generating ROM masks. The EPROM should be placed in a
conductive IC carrier and securely packed. Do not use
styrofoam.
MASTER-DEVICE METHOD
EPROM-A 2716 EPROM, programmed with the customer
program (positive logic sense for address and data), may be
submitted for pattern generation. Fill out Customer Information of ROM Information Sheet. Note that the first 128
xxx
2716
XXX~Customer
0000
ID
Fig. 1a - EPROM marking.
ROM INFORMATION SHEET
OPTION LIST
Select the options for your MCU from the following list. A manufacturing mask will be generated from this information.
Select one in each section.
I nternal Oscillator Input
CJ Crystal
CJ Resistor
Column 28 of Option Card
OorN
lor P
InternalDivide
CJ + 4
CJ + 2
Column 29 of Option Card
o orN
1 or P
Interrupt
Column 30 of Option Card
OorN
1 or P
CJ Edge-Sensitive
CJ Level- and Edge-Sensitive
VECTOR LIST
Timer Interrupt from Wait State Only _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Timer Interrupt _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
External Interrupt
SWI _______________________________________________________
RESET ___________________________________________________
CUSTOMER INFORMATION
CustomerName _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,State_ _ _ _ _ _ _ _ _ _ _ _ _ _ Zip,_ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ __
Phone (
Contact Ms.lMr. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Cu~omerPartNo,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
PATTERN MEDIA
CJ
6805F2
o EPROM
CJ Card Deck
CJ Other'
'Other media require factory approval.
Signature'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Title' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
499
RCA CMOS LSI Products
CDP6805F2
DATA PROGRAMMING INSTRUCTIONS
When a customer submits instructions for programming
RCAcustom ROM s, the customer must also complete the
relevant parts ofthe ROM information sheet and submit this
sheet together with the programming instructions. Programming
instructions may be submitted in anyone of three ways, as
follows:
1. Computer-Card Deck-use standard 80-column computer punch cards.
2.' Floppy Diskette-diskette information must be generated on an RCA CDP1800-series microprocessor
development system.
TITLE
Column No.
Data
1
Punch T
3. Master Devlce-a ROM, PROM, EPROM, orC0P6805F2
that contains the requirecl programming information.
The requirements for each method are explained in detail in
the following paragraphs:
COMPUTER-CARD METHOD
Use standard 80-column computer cards. Each card deck
must contain, in order, a title card, an option card, a dataformat card, and data cards. Punch the cards as specified In
the following charts:
CARD
2-5
leave blank
6-30
Customer Name (start at 6)
31-34
35-54
leave blank
Customer Address or Division (start at 35).
55-58
59-63
leave blank
RCA custom selection number (5 digits) (Obtained from RCA Sales Office)
64
65-71
RCA device type, without COP68 prefix, e.g. 05F2
72
Punch an opening parenthesis (
73
Punch 8
74
Punch a closing parenthesis )
leave blank
75-78
leave blank
79-80
Punch a 2-digit decimal number to indicate the deck number;
the first deck should be numbered 01
OPTION CARD
Use the ROM Information Sheet to select the polarity options, P, N, or X, for the desired ROM type.
Column No.
1-6
Data
Punch the word OPTION
7
leave blank
8-17
RCA device type, including CDPS8 prefix, e.g. CDP6805F2
1.8-27
28-30
leave blank
Punch P or N per ROM Information Sheet
31-78
leave blank
79-80
Punch the deck number (the 2-digit number in
columns 79-80 of the title card)
DATA-FORMAT CARD
The data-format card specifies the form in which the data is to be entered into ROM.
Column No.
1-11
Data
Punch the words DATA FORMAT
12
13-15
leave blank
Punch the letters HEX
16
17-19
Punch POS
leave blank
20-78
leave blank
79-80
Punch tl)e deck number (the 2-digit number in
columns 79-80 of the title card)
500
6805-Serl•• LSI Product.
CDP680SF2
DATA PROGRAMMING INSTRUCTIONS (Conrd)
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Data
Column No.
Data
1-4
Punch the starting address
26-27
2 hex digits of 9th WORD
2 hex digits of 10th WORD
in hexadecimal for the
28-29
following data.'
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
2 hex digits of 12th WORD
6-7
2 hex digits of 1st WORD
33-34
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
2 hex digits of 4th WORD
40
Blank
15
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43-44
2 hex digits of 16th WORD
18-19
2 hex digits of 6th WORD
45
Semicolon, blank if last card
20
Blank
21-22
2 hex digits of 7th WORD
46-78
Blank
23-24
2 hex digits of 8th WORD
79-80
Punch 2 decimal digits
25
Blank
as in title card
'The address block must start at 0080 and run through 0466. Column 4 must be zero. One additional card starting at 07FO is required to
specify vectors. Note that as the sample program card shows, both the 0460 and 07FO card must contain 16 data words. Zeros are used to fill
unused locations 0467-04BF and 07FO-07FS.
OPTION DATA CARD
1234561 8 91011121314 1S 16171819 20 21 22 23 24 25 26 27 28 2930 31 32333435 363738394041424344 45 464748 49 50 5152535455565758596061626364658667686970717273747578 77 78 79 180
T
,
0.
0
N
FO
T
8
"
f
•
I
•
AM PLE
~CA
CDP6S0 SF
A
"
"
HEi" POS
21'- 3" 44 55
6' T 7
BSq.,
5678
E F F £
DC B
2£33
"'""
• S "
SMu1...
qqqqq
(//!5 F ..
..... CD
44 SIS
0. (11111
( 8)
,
1
01
HPH
01
66 ....
'70C
TIMER INTERRUPT FROM
WAIT STATE ONLY
(/ fII."
e7_~
1\
AaS
SS
.,6
CCDO
• £ F F ;
43'"
00A
0. 0 '
fII.,,1l
'17
1/!J7
6"
TIMER INTERRUPT
Ei'>
, ,,,
(/j
4"
EXTERNAL SWI
INTERRUPT
.
"',
;
Ql
RESET
(// 1
OBTAIN FROM
RCA SALES
(/j
1
01
(21 1
I
DECK NUMBER
(OPTI ONAl
123456 1 8 91011121314151617 18 192021 222324 2S 26 27 28 2930 31 32 33 3435363738394041424344454647484950 51 52 S3 54 5556 57 58 59 60 6162636465666768697071727374757677 78 79 80
92Cl-35134
501
RCA CMOS LSI Products
CDP6805F2
CDP6805 FAMILY
CDP6805E2 Available Now CDP8805G2
Technology
CMOS
CMOS
Number of Pins
40
40
On-Chip RAM (Bytes)
112
112
On-Chip User ROM (Bytes)
External Bus
Bidirectional 1/0 Lines
None
2K
Yes
None
16
32
Unidirectional 110 Lines
None
None
Other 1/0 Features
Timer
Timer
EPROM Version
None
None
STOP and WAIT
Yes
Yes
CDP6805F2
Technology
CMOS
Number of Pins
28
On-Chip RAM (Bytes)
64
On-Chip User ROM (Bytes)
1K
External Bus
None
Bidirectional 1/0 Lines
20
Unidirectional 1/0 Lines
None
Other I/O Lines
Timer
EPROM Version
None
STOP and WAIT
Yes
OPERATING AND HANDLING CONSIDERATIONS
1.
2.
Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525. "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
Operating
Operating Voltage
During operation near, the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absolute maximum
rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than Vee nor less than
Vss. Input currents must not exceed 10 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Vee or Vss, whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo, Vee, or Vss may damage
CMOS devices by exceeding the maximum device
dissipation.
ORDERING INFORMATION
RCA Microprocessor device packages are identified by
letters indicated in the following chart. When ordering a
Microprocessor device, it is important that the appropriate suffix letter be affixed to the type number of the
device.
Package
Dual-in-Line Side Brazed Ceramic
Dual-in-Line Plastic
Suffix Letter
D
E
For example, a CDP6805F2 in a dual-In-line plastic
package will be identified as the CDP6805F2E.
502
6805-Serlel LSI Productl
CDP-S805G2
Objective Data
,.
I!lm
.0
m
CMOS High-Performance Silicon-Gate
a-Bit Microcomputer
VOO
OSCI
.,. ·•• ,.""",. .0.
"
.., ""· ",.
'B
NU.
P',
PA.
PAS
7
B
PA3,
'"
10
'AI
..P.,,
PAD
'0
'.0
"
""
P., "
Vss
I•
PB'
PBS
17
P ••
I.
'0
28
27
26
2'
24
23
22
21
osc,
TIMER
Features:
P07
PO,
-
PO'
PO,
PO,
POI
POD
Typical full speed operating power
of 15 m W at 5 V
Typical WAIT modepowerof4mW
Typical STOP mode power of 25 pA
Fully static operation
112 bytes of on-chip RAM
2106 bytes of on-chip ROM
32 bidirectional I/O lines
High current drive
Internal 8-bit timer with software
programmable 7-bit presca/er
External timer input
External and timer interrupts
Self-check mode
Master reset and power-on reset
-
peo
PCt
pe2
PC3
PC4
PCS
pes
PC7
TOP VIEW
TERMINAL ASSIGNMENTS
-
The CDP6805G2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers. This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer. The fully static design allows operation at
frequencies down to DC, further reducing its already low-
- Single 3 to 6 volt supply
- On-chip oscillator with RC or crystal
mask options
- 40-pin dual-in-line package
- Similar to the MC6800
- Efficient use of program space
- Versatile interrupt handling
- True bit manipulation
- Addressing modes with indexed
addressing for tables
_ Efficient instruction set
- Memory mapped I/O
- Most self-check routines user
callable
- Two power saving standby modes
power consumption. It is a low-power processor designed
for low-end to mid-range applications in the conSume."
automotive, industrial, and communications markets where
very low power consumption constitutes an important
factor.
IRQ
2
TIMER
Port
A
110
lines
Port
B
110
Lines
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
PAD
PAl
PA2
PA3
PA4
PA5
PA6
PA7
peo
Accumulator
8
Port
A
Reg
Data
Oir
Reg
8
A
Index
Register
X
Condition
Code
5 Register CC
6
Port
B
Reg
Data
Oir
Reg
5
8
Stack
Pointer
CPU
Control
Data
Oir
Reg
Port
C
Reg
CPU
S
Program
Counter
High PCH
Program
Counter
low PCl
AlU
Data
Dir
Reg
Port
D
Reg
PCl
PC2
PC3
PC4
PC5
PC6
PC7
POD
PDl
P02
P03
P04
P05
P06
P07
Port
C
110
Lines
Port
0
110
Lines
I
198x8
Self-Check
ROM
Fig. 1 - CDP6805G2 CMOS microcomputer block diagram.
503
RCA CMOS LSI Products
CDP6805G2
MAXIMUM RATINGS (Voltages Referenced to VSS)
Ratinas
Symbol
Supply Voltage
All Input Voltages Except DSCl
Current Drain Per Pin Excluding VDD and VSS
Operating Temperature Range
VDD
Value
-0.3 to +8.0
Yin
VSS-0.5to VDD+0.5
V
I
10
mA
o to
TA
Unit
V
+ 70
°C
Storage Temperature Range
Tstg
-55 to + 150
°C
Current Drain Total (P04-P07 only)
IOH
40
mA
THERMAL CHARACTERISTICS
Characteristics
Symbol
Thermal Resistance
Plastic
\ Ceramic
8JA
Value
Unit
100
50
°C/W
-
This device contains circuitry to protect the
inputs against damage due to high static
voltages of electric fields; however, it is advised that normal precautions be taken to
avoid application ohny voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range Vsss (Vin or
Vout)sVOO. Reliability of operation is
enhanced if unused inputs except OSC2 and
NUM are tied to an appropriate logic voltage
level (e.g., either VSS or VOO).
VOO=4.5V
Port
B andC
Rl
R2
A, PDO-PD3
24.3 kll
1.21 kll
4.32 kll
3.1 kll
PD4-P07
30011
1.64 kll
-
ILoad
Test Point
R2
50 pF
(mA)
5.0
Fig. 2 - Equivalent test load.
4.0
Q
.9
1:
~
:;
u
VOO=6V
3.0
Cl
c:
.~
VOO=5V
~
0
"iii
'~
f-
2.0
1.0
0.2
0.3
0.4
0.6
0.7
Internal Frequency 11/tcyc)
Fig. 3 - Typical operating current VB. Internal frequency.
504
1.0
(MHz)
6aOS-Serles LSI Products
CDP6805G2
DC ELECTRICAL CHARACTERISTICS ISee Note 21 IVOO=5.0 Vdc ± 10%, VSS=O Vdc, TA=oo to 700C unless otherwise notedl
Svrnbol
Characteristics
Min
-
l
Unit
0.1
V
V
VOO-O.l
-
II Load = -100 "AI PBO-PB7, PCO-PC7
VOH
2.4
V
II Load = -2 mAl PAO-PA7, POO-P03
VOH
2.4
-
IILoad= -S mAl PD4-P07
VOH
2.4
-
V
VOL
-
0.4
V
VIH
VIH
VIH
VOO-2.0
VOO-0.8
VOO-0.8
VIL
VSS
VOO
VOO
VOO
O.S
V
V
V
V
-
6
3
-
250
mA
mA
/loA
IlL
-
±10
/loA
lin
-
±1
"A
Cout
Cin
-
12
S
pF
pF
Min
Max
Unit
100
100
-
-
ms
ms
teye
teye
teye
teyc
teyc
ns
ns
4
4
MHz
MHz
Output High Voltage
I
Max
VOL
VOH
Output Voltage ILoad:S 10.0 "A
Output Low Voltage
II Load = 800 "AI All Ports
PAO-PA7, PBO-PB7, PCO-PC7, POD-P07
Input High Voltage
Ports PAO-PA7, PBD-PB7, PCO-PC7, POO-P07
TIMER, IRO, RESET
OSCl
Input Low Voltage All Inputs
Total Supply Current ICL - 50 pF
on Ports, no dc Loads, tcyc = 1 "sl
RUN Imeasured during selt-check,
VIL=0.2 V, VIH=VOO-0.2 VI
WAIT ISee Note 11
STOP ISee Note 11
1/0 Ports Input Leakage
PAO-PA7, PBO- PB7, PCO-PC7, POO-P07
Input Current
RESET, IRO, TIMER, OSCl
Capacitance
Ports
RESET, IRO, TIMER, OSCl
100
IUD
100
V
NOTES: 1. Test conditions for 100 are as follows:
All ports programmed as inputs
VIL = 0.2 V IPAO-PA7, PBO-PB7, PCO-PC7, POO-P071
VIH = VOO-0.2 V for RESET, IRO, TIMER
OSCl input is a squarewave from 0.2 V to VOO-0.2 V
OSC2 output load = 20 pF Iwait 100 is affected linearly by the OSC2 capacitance).
2. Electrical Characteristics for VOO = 3 V available soon.
TABLE 1 - CONTROL TIMING
1VOO=5 Vdc ± 10%, VSS=O, TA=Oo to 70°C, fosc=4 MHzl
Characteristics
Crystal Oscillator Startup Time I Figure 51
Stop Recovery Startup Time ICrystal Oscillatorl IFigure 61
Timer Pulse Width IFigure 4)
Reset Pulse Width I Figure 5)
Timer Period IFigure 4)
Interrupt Pulse Width Low IFigure 15)
Interrupt Pulse Period (Figure 15)
OSCl Pulse Width
Cycle Time
Frequency of Operation
Crystal
External Clock
Symbol
toxOV
tlLCH
tTH, tTL
tRL
tTLTL
tlUH
tlUL
tOH, tOL
teyc'
-
0.5
1.5
1
1
*
100
1000
lose
-
'osc
OC
-
-
I
'The minimum period tlUL should not be less than the number of tCYc cycles it takes to execute the interrupt service routines plus 20 teye cycles.
505
C1I
O::D
o
0>
-+I
External
Clock
( Timer)
Pin 37
tTL
~
CO
"U:.-
c:n0
C»i:
5:0
C)0
fl,)r-
!!!
'U
Fig. 4 - Timer relationships.
;;
Do
C
n
c:
I
I
VDD
.r
1
i
OSC1
1
I
I
ItOXOV 1 1920 tcye
I..
I
I
-t"
I
I
.1
iI
teye
-1
",2*
Internal
Address
Bus*
Internal
Data
Bus*
I+- -i
1- . --- J!
tRL
RESET
• Internal timing signal not available externally.
Fig. S - Power-on RESET and RESET.
680S-Serles LSI Products
CDP6805G2
OSC2**-~11111771177 ~ III
iRa
..
--------l.~1
or
Ami'
c___-1920 leye
-~
* Internal tirning signals not available externally.
**Represents the Internal gating of the OSCI input pin.
Fig. 6 - Stop recovery and power-on RESET.
FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power is supplied to the MCU using these two pins. VOO
is power and VSS is ground.
iRa (MASKABLE INTERRUPT REQUEST)
OSC1, OSC2
The CDP6805G2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived by either a divide-by-two or divideby-four of the external frequency (fOSC). Both of these
options are mask selectable.
rna
is mask option selectable with the choice of interrupt
sensitivity being beth level- and negative-edge or negativeedge only.The MCU completes the current instruction
is low and the interbefore it responds to the request. If
rupt mask bit (I bit) in the conqition code register is clear, the
MCU begins an interrupt sequence at the end of the current
instruction.
If the mask option is selected to include level sensitivity,
then the IRQ input requires an external resistor to VOO for
"wire-OR" operation. See the Interrupt section for more
detail.
rna
RESET
The I'iESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to Timer section for a detailed description.
NUM - NON-USER MODE
This pin is intended for use in self-check only. User applications should connect this pin to ground through a 10 kO
resistor.
RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b)'
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(a) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT -cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electrical characteristics table. USing an external CMOS
oscillator is suggested when crystals outSide the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VOO. Refer to Control
Timing Characteristics for limits. See Table 1.
EXTERNAL CLOCK - An external clock should be applied to the OSCl input with the OSC2 input not connected,
as shown in Figure 7(c). An external clock may be used with
either the RC or crystal oscillator mask option. tOXOV or
tlLCH do not apply when using an external clock input.
507
RCA CMOS LSI Products
CDP6805G2
1 MHz
RSMAX
Co
Cl
COSCl
COSC2
Rp
Q
4 MHz
75
400
7
0.012
5
0.008
15-40
15-30
15-25
15-30
10
30
10
40
Units
0
pF
I'F
pF
pF
MO
-
Crystal Parameters
CDP6805G2
39
~~r~'
OSC2
OSCl
38
Rp
o
----110 1-1___
~ COSC2
COSCl
_3_8
Crystal Oscillator Connections
3_9
Equivalent Crystal Circuit
(a)
CDP6805G2
CDP6805G2
OSCl
OSC2
OSCl
OSC2
!38
39
Unconnected
R
'----«
(b)
RC Oscillator Connection
(c) External Clock Source Connections
Fig. 7 - Oscillator connections.
TBD
R(kOl
Fig. 8 - Frequency vs. resistance for RC oscillator option only.
508
External Clock
6aOS-Serle. LSI Product.
CDP6805G2
PAO-PA7
PDO-P07
These eight I/O .Iines comprise Port A. The state of any
pin is software programmable. Refer to Input/Output Programming section for a detailed description.
These eight lines comprise Port D. PD4-PD7 also are
capable of driving LED's directly. The state of any pin is software programmable. Refer to the Input/Output Programing
section for a detailed description.
PBO-PB7
INPUT/OUTPUT PROGRAMMING
Any port pin may be software programmed as an input or
output by the state of the corresponding bit in the port Dina
Direction Register !DDR). A pin is configured as an output if
its corresponding DDR bit is set to a logic '1.' A pin is configured as an input if its corresponding DDR bit is cleared to
a logic '0.' At reset, all DDRs are cleared, which configures
all port pins as inputs. A port pin configured as an output
will output the data in the corresponding bit of its port data
latch. Refer to Figure 9 and Table 2.
These eight lines comprise Port 8. The state of any pin is
software programmable. Refer to Input/Output Programming section for a detailed description.
peO-PC7
These eight lines comprise Port C. The state of any pin is
software programmable. Refer to the Input/Output Programming section for a detailed description.
Internal
CDP6805G2
Connections
lal
Typical Port
Data Direction
Register
7
6
5
4
P-7
P-6
P-5
P-4
2
0
Typical Port
Register
Pin
P-3
P-2
P-l
p-o
I
lbl
TABLE 2 - I/O PIN FUNCTIONS
R/W
0
0
DDR
0
1
1
0
1
1
I/O Pin Function
The I/O pin is in input rnode. Data is written into the output data latch.
Data is written into the output data latch and output to the I/O pin.
The state of the 1/0 pin is read.
The 1/0 pin is in an output mode. The output data latch IS read.
Fig. 9 - Typical port I/O circuitry.
509
RCA CMOS LSI Products
CDP6805G2
SELF-CHECK
The CDP6805G2 self-check is performed using the circuit
in Figure 10. Self-check is i(litiated by tying NUM and
TIMER pins to a logic 1 then executing a reset. After reset.
five subroutines are called that execute the following tests:
I/O-Functionally exercise port A. B. C. D
RAM - Walking bit test
ROM-Exclusive OR with odd 1's parity result
Timer - Functionally exercise timer
Interrupts- Functionally exercise external and timer interrupts
Self-check results are shown in Table 3. The following
subroutines are available to user programs and do not require' any external hardware.
RAM SELF-CHECK SUBROUTINE
Returns with the l-bit clear if any error is detected; otherwise the l-bit is set.
The RAM test must be called with the stack pointer at
$07F. When run. the test checks every RAM cell except for
$07F and $07E which are assumed to contain the return address.
A and X are modified. All RAM locations except the top 2
are modified. (Enter at location $1 FB7.)
ROM CHECKSUM SUBROUTINE
Returns with l-bit cleared if any was found. otherwise
l = 1. X = 0 on return. and A is zero if the test passed. RAM
locations $040-$043 are overwritten. (Enter at location
1FA 1.)
TIMER TEST SUBROUTINE
Return with l-bit cleared if any error was found; otherwise
l= 1.
This routine runs a simple test on the timer. In order to
work correctly as a user subroutine. the internal clock must
be the clocking source and interrupts must be disabled.
Also. on exit. the clock will be running and the interrupt
mask not set so the caller must protect himself from interrupts if necessary
A and X register contents are lost; this routine counts how
many times the clock counts in 128 cycles. The number of
counts should be a power of two since the prescaler is a
power of two. If not. the timer probably is not counting correctly. The routine also detects if the timer is running at all.
(Enter at location $1FBB')
MEMORY
The CDP6805G2 has a total address space of 8192 bytes
of memory and 1/0 registers. The address space is shown in
Figure 11.
r----'-
__ 1
RESET
40
VDD
TIMER 37
NUM
OSCl
3
10 kG
10 kG
~
6
PA7
PA6
~
PD6
~ ;--
PD5
PD4
PD3
PA2
PDl
PAO
PDO
-
PCO
PBO
PCl
PBl
PC2
14 PB2
PC3
15 PB3
....!.2.
T
4M Hz
I
33
32
E. 26
25
~
F22
PC7
19 PB7
29
1§.
PC5
PC6
18 PB6
30
PC4
PB4
~ PB5
21
Vss
1
0
Fig. 10 - Self-check circuit.
510
c!s
34
PD2 31
10 PAl
..E.
.J1
38
PD7
PA5
~ PA3
11
12!
IRQ 2
7 PA4
---1
5v
J
10 MG
OSC2
10 kG
39
CDP6805G2
- r2
1
Y
5t Status
In dication
680S-Serles LSI Products
CDP6805G2
TABLE 3 - SELF-CHECK RESULTS
PD3
P02
POl
POO
Remarks
1
0
1
0
Bad I/O
1
0
1
1
Bad Timer
1
1
0
0
Bad RAM
1
1
0
1
Bad ROM
1
1
1
0
Bad Interrupt or Request Flag
All Cycling
Good Part
Bad Part
All Others
0
SOOOO
I/O Ports
Access
Via
Page 0
Direct
Addressing
0
Port A Data
$0000
1
Port B Oata
$0001
S0080
I
2
Port C Data
$0002
3
Port D Data
SOO03
SOOFF
4
Pon A Data Direction
$0004
5
Port B Data Direction
$0005
6
Port C Data Direction
$0006
$0007
Timer
RAM
fm
$OOlF
128
255
256
2096 Bytes
User ROM
SOl00
\
2223
2224
2303
S08AF
$08BO
80 Bytes
Self-Check ROM
$08FF
$0900
2304
7
Port D Data Direction
8
Timer Data
$0008
9
Timer Control
$0009
10
$OOOA
5 Bytes
5750 Bytes
Unused*
Unused'
15
16
$oooF
$0010
t-RAM
(112 Bytes)
8063
$lF7F
8064
8181
8182
User
Defined
Interrupt
Vectors
I
63
SlF80
118 Bytes
64
Self-Check ROM
r-----------Timer Interrupt From Walt State Only
r----------"'-Timer Interrupt
r----
$lFFA-$lFFB
$lFFE$lFFF
L
127
/
;'
./
./
. / ./ Stack 154 Bytes Maxi
I
RESET
$003F
$0040
;'
$lFF8S1FF9
$lFFC$lFFD
,;;;;
;'
$lFF5- $lFF7
SWI
8191
..,
$lFF5
External Interrupt
r---r--- - -
t-
./
./
+
$G07F
*Reads of unused locations undefined.
Fig. 11 - Address map.
511
RCA CMOS L.SI Products
CDP6895G2
ACCUMULATOR (AI
The first 128 bytes of memory (first half of page zero) is
comprised of the I/O port locations, timer locations, and 112
bytes of RAM. The next 2096 bytes comprise the user ROM.
The 10 highest address bytes contain the reset and interrupt
vectors.
The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and subroutine calls. At power-up, the stack pointer is set to $OO7F
and it is decremented as data is pushed on the stack. When
data is removed from the stack, the stack pointer is incremented. A maximum of 64 bytes of RAM is available for
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and/ or
subroutine stacking purposes, the unused bytes are usable
for program data storage.
This accumulator is an a-bit general purpose register used
for arithmetic calculations and data manipulations.
INDEX REGISTER (XI
The X register is an a-bit register which is used during the
indexed modes of addressing. It provides an 8-bit operand
which is used to create an effective address. The index
register is also used for data manipulations with the
read/modify/write type of instructions and as a temporary
storage register when not performing addressing operations.
PROGRAM COUNTER (PCI
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the processor.
STACK POINTER (SPI
The stack pointer is a 13-bit register containing the
address of the next free location on the stack. When accessing memory, the seven most-significant bits are permanently
set to 0000001. These seven bits are appended to the six
least-significant register bits to produce an address within
the range of $OO7F to $0040. The stack area of RAM is used
to store the return address on subroutine calls and the
REGISTERS
The CDP6805G2 contains five registers as shown in the
programming model in Figure 12. The Interrupt stacking
order is shown in Figure 13.
7
0
I
0
I
A
7
x
Accumulator
Index Register
0
12
I
PC
12
6
0
5
I 0 I 0 I 0 I0 I 0 I 0 I d
Program Counter
SP
I
Stack Pointer
Condition Code Register
Carry/Borrow
L-_ _ _
Zero
Negative
......- - - - Interrupt Mask
Half Carry
L.._ _ _ _ _ _
Fig. 12 - Programming Model.
o
7
1
I1I1I
Condition Code Register
Accumulator
I ncreasing Memory
Addresses
Index Register
11
PCH
010 101
PCl
Unstack
Stack
!1
Decreasing Memory
Addresses
T
NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is in
the reverse order.
Fig. 13 - Stacking order.
512
680S-Serles LSI Products
CDP6805G2
machine state during interrupts. During external or poweron reset, and during a "reset stack pointer" instruction, the
stack pointer is set to its upper limit ($OO7FI. Nested interrupts and/or subroutines may use up to 64 (decimal) locations, beyond which the stack pointer "wraps around" and
points to its upper limit thereby losing the previously stored
information. A subroutine call occupies two RAM bytes on
the stack, while an interrupt uses five bytes.
CONDITION CODE REGISTER (CCI
The condition code register is a 5-bit register which indicates the results of the instruction just executed. These
bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.
HALF CARRY BITS (HI - The H-bit is set to a one when
a carry occurs between bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H-bit is useful in binary coded
decimal subroutines.
Either of the two types .of reset conditions causes the
following to occur:
- Timer control register interrupt request bit TCR7 is
cleared to a "0."
- Timer centrel register interrupt mask bit TCR6 is set te a
"1."
- All data direction register bits are cleared te a "0." All
ports are defined as inputs.
- Stack pointer is set to $OO7F.
- The internal address bus is forced to the reset vector
($1 FFE, $1 FFFL
- Condition code register interrupt mask bit (I) is set to a
"1."
- STOP and WAIT latches are reset.
- External interrupt latch is reset.
All other functions, such as other registers (including .output ports), the timer, etc., are not cleared by the reset conditions.
INTERRUPTS
INTERRUPT MASK BIT (I) - When the I-bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I-bit is set, the interrupt is latched and is
processed when the I-bit is next cleared.
NEGATIVE (NI -. Indicates that the result of the last
arithmetic, logical, or data manipulation is negative (bit 7 in
the result is a logical onel.
ZERO IZI - Indicates that the result of the last arithmetic,
logical, or data manipulation is zero.
CARRY /BORROW (C) - Indicates that a carry or borrow
out of the arithmetic logic unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.
RESETS
The CDP680SG2 has two reset modes: an active low
external reset pin (RESET) and a power-on reset function·
refer to Figure S.
•
RESET
The RESET input pin is used 10 reset the MCU to provide
an orderly software start-up procedure. When using the external reset mode, the RESET pin must stay low tor a minimum of one tcyc. The RESET pin is provided with a Schmitt
Trigger input to improve its noise immunity.
POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any dreps in the pewer supply voltage. There is ne provisien
for a power-down reset. The power-en circuitry prevides fer
a 1920 tcyc delay frem the time of the first .oscillator eperatien. If the external RESET pin is low at the end of the 1920
tcyc time .out, the processor remains in the reset conditien.
The CDP680SG2 is capable of operation with three
different interrupts, two hardware (timer interrupt and
external interrupt), and one software (SWI). When any of
these interrupts occur, normal processing is suspended at
the end of the current instruction execution. All of the
program registers (the machine state) are pushed onto the
stack; refer to Figure 13 for stacking order. The appropriate
vector pointing to the starting address of the interrupt
service routine is then fetched; refer to Figure 14 for the
interrupt sequence.
The prierity of the various interrupts from highest to
lowest is as follows:
RESET -*-Externallnterrupt- Timer Interrupt
TIMER INTERRUPT
If the timer mask bit (TCR6) is cleared, then each time the
timer decrements tez9fCJ(transitiens from $01 to $00) an
interrupt requestis·generated. The actual processer interrupt
is generated only if the interrupt mask bit .of the condition
code register is alse cleared. When the interrupt is recegnized, the current state of the machine is pushed .onto the stack
and the interrupt mask bit in the cenditien code register is
set. This masks further interrupts until the present one is serviced. The processer new vectors to the timer interrupt service routine. The address for this service routine is specified
by the contents of $1 FF8 and $1 FF9 unless the processor is
in a WAIT mode in which case the contents of $1FF6 and
$1 FF7 specify the timer service routine address. Software
must be used to clear the timer interrupt request bit ITCR7).
At the end of the timer interrupt service routine, the software
nermally executes an RTI instruction which restores the
machine state and starts executing the interrupted program.
I
EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register is
cleared and the external interrupt pin is "low," then the external interrupt occurs. The action of the external interrupt is
* Any current instruction including SWI.
513
RCA CMOS LSI Products
CDP680SG2
Force Interrupt
Execution, Set
Interrupt Mask,
Fetch Timer
Vector *Note .
Force Interrupt
Execution, Set
Interrupt Mask,
Fetch Ext Int
Vector, Reset
Interrupt Latch
* NOTE: The clear of TCR bit 7 must be accomplished with software.
Fig. 14 - Interrupt and instruction processing flowchart.
514
680S-Serles LSI Products
C[)P6805G2
SOFlWARE INTERRUPT (SWII
The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the in'
terrupt mask in the condition code register. The service
routin address is specified by the contents of memory locations $1 FFC and $1 FFD. See Figure 14 for interrupt and instruction processing flowchart.
The following three functions are not strictly interrupts;
however, they are tied very closely to the interrupts. These
functions are RESEi", STOP, WAIT.
identical to the timer interrupt with the exception that the
service routine address is specified by the contents of $1 FFA
and $1FFB. Either a level- and edge-sensitive (or edge-sensitive only) are available as mask options. Figure 15 shows
both a functional diagram and timing for the interrupt line.
The timing diagram shows two different treatments of the
interrupt line (IRO) to the processor. The first method is
single pulses on the interrupt line spaced far enough apart to
be serviced. The minimum time between pulses is a function
of the length of the interrupt service routine. Once a pulse
occurs, the next pulse should not occur until the MPU software has exited the routine (an RTI occurs!. This time (tIULI
is obtained by adding 20 instruction cycles (tCycl to the total
number of cycles it takes to complete the service routine including the RTI instruction; refer to Figure 15. The second
configuration shows many inter(upt lines "wire ORed" to
form the interrupts at the processor. Thus, if after servicing
an interrupt the IRO remains low, then the next interrupt is
recognized.
RESET
The RESEi" input pin and the internal power-on reset
function each cause the program to vector to an initialization
program. This vector is specified by the contents of memory
locations $1 FFE and $1 FFF. The interrupt mask of the condition code register is also set. Refer to Resets section for
details.
(a) Interrupt Functional Diagram
Level Sensitive
Mask Option
Voo ,.....--.,
o
External
Interrupt
Request
Q~----I
Interrupt Pin ----~__--_QC
Q
I Bit ICCR)
R
Power-On Reset
External Reset
External Interrupt
Being Serviced
(b)
11)
12)
U
IRQ~tILIH
~
Interrupt Mode Diagram
tILlL~-i
Edge Condition
IThe minimum pulse width ItlllH is one
tcyc· The period till L should not be
less than the number of tcyc cycles it
takes to execute the interrupt service routine plus 20 tcyc cycles.)
I
)RQ I M P U ) I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
L
Mask Optional Level Sensitive
II! after servicing an interrupt the IRQ remains low, then the next interrupt is recognized)
IR.Ql~ tUHI---tl~..,j
•
•
IRl)n
Fig. 15 - External interrupt.
515
RCA CMOS LSI Products
CDP6805G2
STOP
The STOP instruction places the CDP6805G2 in its
lowest power consumption mode. In the STOP function the
internal oscillator is turned off, causing all internal processing and the timer to be halted; refer to Figure 16.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. The timer
prescaler is cleared. External interrupts are enabled in the
condition code register. All other registers and memory remain unaltered. All 1/0 lines remain unchanged.
except the timer circuit; refer to Figure 17. Thus, all internal
proceSSing is halted; however, the timer continues to count
normally.
During the Wait mode, the I-bit in the' condition code
register is cleared to enable interrupts. All other registers,
memory, and I/O lines remain in their last state. The timer
may be enabled to allow a periodic exit from the Wait mode.
If an external and a timer interrupt occur at the same time,
the external interrupt is serviced first; then, if the timer interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer Wait interrupt) is serviced since the MCU is no longer in the WAIT
mode.
TIMER
Stop Oscillator
And All Clocks
TCR Bit 7-0
Bit 6-1
Clear I Mask
Yes
Fig. 16 - Stop function flowchart.
WAIT
The WAIT instruction places the CDP6805G2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode. In the WAIT
mode, the internal clock Is dlabled from all internal circuitry
516
The MCU timer contains a 8-bit software programmable
counter with7-bit software selectable prescaler. The counter
may be present under program control and decrements
towards zero. When the counter decrements to zero, the
timer interrupt request bit, i.e., bit 7 of the timer control
register (TRC), is set. Then, if the timer interrupt is not
masked, i.e., bit 6 of the TCR and the I-bit in the condition
code register are both cleared, the processor receives an interrupt. After completion of the current instruction, the processor proceeds to store the appropriate registers on the
stack, and then fetches the timer vector address from locations $lFF8 and $lFF9 (or $lFF6 and $lFF7 if in the WAIT
mode) in order to beging servicing.
The counter continues to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer in,errupt request bit
was set. The counter may be read at any time by the processor without disturbing the count. The contents of the
counter becomes stable prior to the read portion of a cycle
and does not change during the read. The timer interrupt request bit remains set until cleared by the software. If a read
occurs before the timer interrupt is serviced, the interrupt is
lost. TCR7 may also be used as a scanned status bit in a noninterrupt mode of operation (TCR6= 1).
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however, its
contents are clearedto all "O's" by the write operation into
TCR when bit 3 of the written data equals 1. This allows for
truncation-free counting.
The timer input can be configured for three different
operating modes, plus a disable mode depending on the
value written to the TCR4, TCR5 control bits. Refer to the
Timer Control Register section.
TIMER INPUT MODE 1
If TCR4 and TCR5 are both programmed to a "0," the input to the timer is from an internal clock and the TIMER input pin is disabled. The internal clock mode can be used for
periodic interrupt generation, as well as a reference in frequency and event measurement. The internal clock is the instruction cycle clock. During a WAIT instruction, the internal clock to the timer continues to run at its normal rate.
680S-Serles LSI Products
CDP680SG2
Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop
No
No
Fetch External
Interrupt Reset,
or Timer Interrupt
Vector Ifrom Wait
Mode only)
I
Fig, 17 - Wait function flowchart.
TIMER INPUT MODE 2
With TCR4= 1 and TCR5= 0, the internal clock and the
TIMER input pin are ANDed together to form the timer input
signal. This mode can be used to measure external pulse
widths. The external pulse simply turns on the internal clock
for the duration of the pulse. The resolution of the count in
this mode is ± 1 clock and, therefore, accuracy improves
with longer input pulse widths.
TIMER INPUT MODE 3
If TCR4=0 and TCR5= 1, then all inputs to the Timer are
disabled.
TIMER INPUT MODE 4
If TCR4= 1 and TCR5= 1, the internal clock input to the
Timer is disabled and the TIMER input pin becomes the input to the Timer. The timer can, in this mode, be used to
count external events as well as external frequencies for
generating periodic interrupts. The counter is clocked on the
falling edge of the external signal.
Figure 18 shows a block diagram of the Timer subsystem.
Power-on Reset and the STOP instruction cause the counter
to be set to $FO.
517
RCA CMOS LSI Products
CDP6805G2
External
Input
Counter
8 Bits
Prescaler
7 Bits
Disabled
(No clock)
Write
Cleared by
TCR3
Read
Interrupt
'~------------~"'------------~/
Software Functions
NOTES:
1. Prescaler and B-bit counter are clocked on the falling edge of the internal clock or external input.
2. Counter counts down continuously.
Fig. 18 - Timer block diagram.
Timer Control Register (TCR)
76543210
ITCR71TCR6lTCR51TCR41TCR31TCR21TCR11TCROI
All bits in this register except bit 3 are Read/Write bits.
TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic" 1".
1 - Set whenever the counter decrements to zero, or under prograrn control.
o - Cleared on external reset, power-on reset, STOP instruction, or program control.
TCR6 - Timer interrupt mask bit: when this bit is a logic
"1" it inhibits the timer interrupt to the processor.
1 - Set on external reset, power-on reset, STOP instruction, or program control.
o - Cleared under program control.
TCR5 - External or internal bit: selects the input clock
source to be either the external timer pin or the internal
clock. (Unaffected by RESET.)
1 - Select external clock source.
Select internal clock source (AS),
o-
TCR4 - External enable bit: control bit used to enable the
external timer pin. (Unaffected by RESET,)
1 - Enable external timer pin.
Disable external timer pin.
o-
518
TCR5 TCR4
o
~
o
1
1
1
0
1
Internal clock to Timer
AND of internal clock and TIMER
pin to Timer
Inputs to Timer disabled
TIMER pin to Timer
Refer to Figure 18 for Logic Representation.
TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always indicates a "0". (Unaffected by RESET.)
TCR2, TCR1, TCRO - Prescaler select bits: decoded to
select one of eight taps on the prescaler. (U naffected by
RESET.)
TCR2
Prescaler
TCRl
TCRO
0
0
0
0
0
0
1c
1
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
1
Result
+1
+2
+4
+8
+16
+32
+64
+128
680S-Serles LSI Products
CDP6805G2
INSTRUCTION SET
The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory,
read/modify/write, branch, bit manipulation, and control.
The following paragraphs briefly explain each type. All the
instructions within a given type are presented in individual
tables.
REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addressing modes. The operand for the jump unconditional
IJMP) and jump to subroutine IJSR) instructions are the
program counter. Refer to Table 4.
READ/MODIFY /WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero ITST) instruction is an exception to the
read/modify/write sequence since it does not modify the
value. Refer to Table 5.
BRANCH INSTRUCTIONS
Most branch instructions test the state of the Condition
Code Register and if certain criteria are met, a branch is executed. This adds an offset between + 128 and -127 to the
current program counter. Refer to Table 6.
BIT MANIPULATION INSTRUCTIONS
The M PU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where all
port registers, port DDR's, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 256 locations. The bit set, bit clear and bit test and branch functions
are all implemented with a single instruction. For the test
and branch instructions the value of the bit tested is also
placed in the carry bit of the Condition Code Register. Refer
to Table 7 for instruction cycle timing.
CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8 for instruction cycle timing.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 10.
OPCODE MAP
Table 9 is an opcode map for the instructions used on the
MCU.
ADDRESSING MODES
The MCU uses ten different addressing modes to give the
programmer an opportunity to optimize the code to all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scalling
tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions Ithree bytes I permit tables throughout memory. Short
and long absolute addressing is also included. One and. two
byte direct addressing instructions access all data bytes inmost applications. Extended addressing permits jump instructions to reach all memory. Table 10 shows the addressing modes for each instruction, with the effects each instruction has on the Condition Code Register. An opcode
map is shown in Table 9.
The term "Effective Address" lEA) is used in describing
the various addressing modes, which is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of," an arrow indicates "is replaced by" and a colon indicates concatenation of two bytes. For additional
details and graphical illustrations, refer to the M6805 Family
User Manual.
INHERENT
In inherent instructions all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and
no other arguments, are included in this mode.
IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution le.g., a constant used to initialize a loop
counter).
EA=PC+1; PC-PC+2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a signle byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a Single two byte instruction. This includes all on-chip RAM and I/O registers
and 128 bytes of on-chip ROM. Direct addressing is efficient
in both memory and time.
EA=IPC+1); PC-PC+2
Address Bus High-O; Address Bus Low-IPC + 1)
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. I nstructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single thre byte instruction. When using the CDP6805
assembler, the user need not specify vyhether an instruction
uses direct or extended addressing. The assembler
automatically selects the most efficient addressing mode.
I
EA=IPC+1):IPC+2); PC-PC+3
Address Bus High-IPC+ 1); Address Bus Low-IPC+2)
INDEXED, NO-OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte long
and therefore are more efficient. This mode is used to move
a pointer through a table or to address a frequency referenced RAM or I/O location.
EA=X; PC-PC+1
Address 8us High-O; Address Bus Low-X
519
RCA CMOS LSI Products
CDP680SG2
INDEXED, 8-BIT OFFSET
Here the EA is obtained by adding the contents of the byte
follo'IVing the opcode to that of the index register. The
operad is therefore located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the moth element in an n element table.
All instructions are two bytes. The contents of the index
register (X) is not changed. The contents of (PC+ 1) is an
unsigned B-bit integer. One byte offset indexing permits
look-up tables to be easily actessed in either RAM or ROM.
EA= + (PC+ 1); PC-PC+2
Address Bus High-K; Address Bus Low-X+(PC+1)
Where: K = The carry from the addition of X + (PC + 1)
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode the effective
address is the sum of the content~ of the unsigned 8-bit
index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar
to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM), As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset - B or
16 bit. The content of the index register is not changed.
EA= X+ [(PC+ 1):(PC+2)]; PC-PC+3
Address Bus High-(PC+l)+K;
Address Bus Low-X+ (PC+2)
Where: K = The carry from the addition of X + (PC + 2)
RELATIVE
Relative addressing is only used in branch instructions. In
relative addressing the contents of the B-bit signed byte
following the opcode (the offset) is added to the PC if and
only if the branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing
520
is limited to the range of -126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to. see if it is within
the span of the branch.
EA= PC+2+ (PC+ 1); PC-EA if branch taken;
otherwise PC-PC+2
BIT SET/CLEAR
Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the
opcode. The bit set and clear instructions occupy two bytes,
one for the opcode (including the bit number) and the
second to address the byte which contains the bit of interest.
EA= (PC+ 1); PC-PC+2
Address Bus High-O; Address Bus Low-(PC+l)
BIT TEST AND BRANCH
Bit test and branch is a combination of direct addressing,
bit addressing and relative addressing. The bit address and
condition (set or clear) to be tested is part of the opcode.
The address of the byte to be tested is in the single byte immediately following the opcode byte (EA 1). The signed
relative B-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or clear in the specified
memory location. This single three byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EAl = (PC+ 1)
Address Bus High-O; Address Bus Low-(PC+ 1)
EA2 = PC + 3 + (PC + 2); PC - EA2 if branch taken;
otherwise PC-PC+3
___ L
TABLE 4 -
REGISTER/MEMORY INSTRUCTIONS
Addressing Modes
Immediate
Function
Mnemonic
#
#
Bytes
Cycles
Op
Code
#
#
Bytes
Cycles
CE
Op
Code
Indexed
(S-Bit Offset)
Indexed
(No Offset)
Extended
#
#
Bytes
Cycles
4
4
5
5
4
__ Op
Code
Indexed
(l6-Bit Offset)
Op
Code
I
I
,
Cycles
Op
Code
,
Bytes
Bytes
Cycles I
3
E6
2
3
5
EE
DE
3
5
E7
5
07
3
EF
2
5
OF
3
6
6
1
4
4
3
2
2
4
4
06
3
EB
2
4
DB
3
5
5
#
I
Bytes
Cycles
F6
1
FE
1
F7
1
FF
1
FB
2
B6
2
BE
2
-
2
-
B7
2
3
3
4
-
-
BF
2
4
CF
AB
2
2
BB
2
3
CB
3
3
3
3
3
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
AO
2
2
BO
2
3
CO
3
4
FO
1
3
EO
2
4
DO
3
5
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
02
3
5
Load A from Memory
LOA
A6
Load X from Memory
LOX
AE
2
2
Store A
In
Memory
STA
-
Store X
In
Memory
STX
-
Add Memory to A
Add Memory and
Carry to A
ADD
ADC
Subtract Memory
SUB
Subtract Memory from
A with Borrow
SBC
C6
C7
AND Memory to A
AND
A4
2
2
B4
2
3
C4
F4
1
3
E4
2
4
D4
3
ORA
AA
2
2
BA
2
3
CA
3
3
4
OR Memory with A
4
FA
1
3
EA
2
4
DA
3
5
5
Exclusive OR Memory
With A
EaR
A8
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
08
3
5
CMP
Al
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
01
3
5
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
03
3
5
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
05
3
5
JMP
-
-
BC
2
2
CC
3
3
FC
1
2
EC
2
3
DC
3
4
Jump to~llbrout,"e_ _ _ J_S~
-
BD
2
5
CD
3
6
FD
1
5
ED
2
6
DO
3
7
Anthmetlc Compare A
With Memory
Arithmetic Compare X
with Memory'
I
Op
Code
Direct
Bit Test Memory with
A 1Logical Compare)
bump Unconditional
-
I
-
-
TABLE 5 -
,
READ/MODIFY/WRITE INSTRUCTIONS
Addressing Modes
Inherent (XI
Inherent (AI
Function
01
I\)
.....
Op
Code
#
#
Mnemonic
Bytes
Cycles
Indexed
(No Offset)
Direct
Op
Code
#
#
Bytes
Cycles
Indexed
(S-Bit Offset)
Op
Code
#
I
I
Cycles
Op
Code
I
Bytes
Bytes
Cycles
Op
Code
I
I
Bytes
Cycles
6
6
Increment
INC
.4C
1
3
5C
1
3
3C
2
5
7C
1
5
6C
Decrement
DEC
4A
1
3
5A
1
3
3A
2
5
7A
1
5
6A
Clear
CLR
4F
1
3
5F
1
3
3F
2
5
7F
1
5
6F
Complement
COM
43
1
3
53
1
3
33
2
5
73
1
5
63
2
2
2
2
Negate
12's Complement!
NEG
40
1
3
50
1
3
30
2
5
70
1
5
60
2
ROL
49
1
3
59
1
3
39
2
5
79
1
5
69
2
6
Rotate Right Thru
Carry
ROR
46
1
3
56
1
3
36
2
5
76
1
5
66
2
6
Logical Shift Left
LSL
48
1
3
58
1
38
2
5
78
1
5
6
LSR
44
1
5
74
1
5
-
1
1
3
2
5
77
1
5
67
2
2
6
47
34
37
2
ASR
54
57
1
ATithmetic Shift Right
3
3
68
64
2
Logical Shift Right
3
3
TST
40
1
3
50
1
3
3D
2
4
7D
1
4
60
2
5
---
CII
6
Rotate Left Thru Carry
Test for Negative
or Zero
5
6
6
6
0»
!t
:
n,-
c.
"CJ;;
..
0)
,
C»o
00.
u.~
el-
I!\)-
RCA CMOS LSI Products
CDP6805G2
TABLE 6 -
BRANCH INSTRUCTIONS
Relative Addressing Mode
Op
#
#
Code
Bytes
Cycles
20
2
3
21
2
3
Mnemonic
Function
BRA
Branch Always
Branch Never
BRN
BHI
BlS
Branch I FF Higher
Branch IFF lower or Same
Branch I FF Carry Clear
IBranch IFF Higher or Samel
BCC
22
23
24
IBHSI
24
2
Branch IFF Carry Set
IBranch IFF lower)
BCS
IBlO)
Branch IFF Not Equal
Branch I FF Equal
BNE
BEQ
25
25
26
27
2
2
2
2
Branch IFF Half Carry Clear
BHCC
28
2
3
Branch I FF Hall Carry Set
BHCS
29
2
2A
2
3
3
Branch IFF Minus
BPl
BMI
Branch I FF Interrupt Mask Bit is Clear
Branch IFF Interrupt Mask Bit is Set
BMC
BMS
2B
2C
2
2
3
3
2D
2
3
2
2
3
2
Branch IFF Plus
Branch IFF Interrupt Line is low
Bil
Branch IFF Interrupt Line is High
BIH
2E
2F
Branch to Subroutine
BSR
AD
2
2
2
3
3
3
3
3
3
3
3
3
6
TABLE 7 - BIT MANIPULATION INSTRUCTIONS
Addressing Modes
,
Bit Setl Clear
Function
Branch IFF Bit n is Set
Branch IFF Bit n is Clear
Set Bit n
Clear Bit n
Mnemonic
BRSET n In=O .. 7)
BRClR n In = O. .7)
BSET n In=O . .7)
BClRnln=O .. 7)
Op
Code
#
#
Bytes
-
-
Cycles
-
-
-
-
10+ 2.n
2
5
11 +2.n
2
5
Bit Test and Branch
Op
#
Cycles
Code
Bytes
2·n
01 + 2.n
3
3
-
-
TABLE 8 - CONTROL INSTRUCTIONS
,
,
Bytes
Cycles
1
1
2
2
2
Transfer A to X
Transfer X to A
TAX
TXA
9F
Set Carry Bit
Clear Carry Bit
SEC
ClC
99
9B
1
1
Set Interrupt Mask Bit
SEI
98
1
Clear Interrupt Mask Bit
CLI
SWI
9A
1
2
83
10
RTS
81
1
1
RTI
RSP
NOP
BO
9C
9D
STOP
WAIT
8E
8F
Function
Software Interrupt
Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
Stop
Wait
522
Inherent
Op
Code
97
Mnemonic
1
1
2
2
6
9
2
1
1
2
2
1
2
5
5
-
_L_
-
lit
~
00lIO
o
!1m
BRSETO
..:.. I
U
"I
ATA
,
BSETO 51
A~r.
BRCLRO,n-;~~!i -I
I
...Jm!
BTah'
2
-OJ
BRSET!
3
BRClRI"I
110'.
00'
2
BRA
,
31
7
0"
8
'OlIO
BCC
~
1011
C
"00
o
1101
E
1110
F
1111
OTR
ROR '6
RR2
RORA
DIA
.
I~
BTB
BRCLR55
2
I
BSiC
2
BHCS 3 [
2
BCLR5 51
BTB2
esc 2
1 BRSETlT-~;~T;51
~
:I
a.:'al2
51
8SC
AFt
51
3
BTB
2
BSC
2
')
COM
I'lll
LSRX 3']- L;R -6
JNH
I2
IXl
r-
1
COM
I'll'
e-
31- ;OR-X 31 - ROR
1
INH
LSLA 31
lNH
ROLA 31
DECA
1
1
INH,
INH'
ASRX 31
INH
LSLX 31
INH
ROLX 31
31--- _.-
INH
3
INC 51
0lRI1
BMS 31
TST 4
I,
INCA
INH.
I
TSTA
OIA
RR2
'NM
SBC
2
CPX 21
2
IMM
LSR .,
1
:r--'Y---
IMM
10
'NM
AND
IMM
pc
I
2
2
2
LSL
ROL
31- -
INH
DECX
2
ASR
INH
2
2
DEC
1
1
INCX
I
3,
TSTX
INH
INH
2
INC
TST
2
2
CLR 51
OIR
1
CLRA 31
INH
ROR
IXl
IXl I 1
IXl
I ,
IXl I 1
ASR
LSL
ROL
6
IXl
I
1
DEC
LOA 21
,
IMM
TAX
INH
IX
T
IXl
'6
IXl
I1
I
CLC 21
,
IX
INH
IX
INH
~ CLR
CLRX
IXt I
1
INH I 2
1
IX
2
IMM
lMM
ORA 21
INH 12
T
IMM
2
2
2
2
ADD
IMM l2
INH
X
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2
U1
~
DIA
CIR
AND
NOP
INH 12
T
lNH 11
3
31
CIA
3
2
f'
41
BSR
REll 2
LOX
IMM
TXA 21
I
I
INH
2
2
-- -s-I
SBC ~
EXT
3
CPX 41
EXT
AND
3
SBC
__
3
1111
S,UB":l,,
SUB IX3
_ ___ L
- -'[---3
CMP
CMP
IXl
IXl
2
IX2
2
__
~xJ
1
IX
SBC
IXI
1
IXI
1
CPX
AND
00'0
IX
(1m
CIA
STA 41
DIR
EOR 31
DIA
ADC 31
DIR
3
3
3
3
EXT
3
1X22 __ -.lXL1
3
STA 51
EXT
3
EOR 41
EXT
3
ADC 41
eXT
3
1X2
STA "I
1X2
ADC 51
lX2
ADD 31
ADD 41
.DIA
3
EXT
OIR
lOX 31
OIR
STX 41
OlR
3
3
3
EXT
JSR 61
EXT
LOX 41
EXT
STX "I
EXT
IX2
2
2
ADD "I
3
JMP 31
3
JSR 51
3
EXT
2
IX22
-'1
ORA 4 1ORA
I3
2
EOR 51
ORA 31
CIA
IX
0'00
IX
0101
lX2
3
3
3
IX2
JSR 71
IX2
LOX "I
IX2
STX 61
IX2
lXl
1
2
IXI
EOR 4]
2
2
2
EOR
X'-:r
_ .JX'
ADC
JX
1_
lXl
1
1
ORA 41
IXl
1
IXl
1
IXl
IXl
LOX 41
IXl
STX " '
4
5
6
0110
7
0111
8
'000
IX
'001
IX
A
1010
9
B
IX
1011
IX
"00
IX
1101
IX
1110
JMP
1
JSR 61
IX'
ADC
ORA
3
IX
ADD --.-
JMP 31
2
IX
-.
STA " [ STA
ADD 41
JMP 41
3
BIT
:r
LOA,41~---4~-3
lOA
LOA
LOA
EXT
BI,T:::r
\
0lI01
11(
4,-- -
CPX 41
o
Opcode in Hexadecimal
i1x~
I
(XXX)
"
:-:t
Opcode in Binary
CJ)
!UI
o..
CD
Address Mode
CD
o·
c~
"Ucn'V
-
CD"
o&.
CI'Ic
C)!l
N.
RCA CMOS LSI Products
CDP6805G2
TABLE 10 - INSTRUCTION SET
Mnemonic
Inhflrent
Iml'l18diate
ADC
x
AUU
"x
AND
ASL
ASR
BCC
BCLR
BCS
x
lildexed
Relitive INo 0ffMt1
Direct
x
x
x
x
x
x
x
)(
)(
)(
x
NEG
x
x
x
)(
)(
x
rAJ
TST
TXA
WAIT
x
X
)(
X
X
X
x
x
x
)(
x
x
x
x
X
X
X
X
x
X
x
X
x
X
X
X
X
x
x
x
)(
x
x
)(
x
x
)(
x
x
)(
x
x
x
x
•
AlA.
•••••
x
X
X
x
X
x
)(
)(
"
x
x
x
x
1\
1\
1\
X
X
)(
X
1\
x
)(
x
•
U
AlA
• :. A_A.!.
•••••
X
X
•••••
•
"-x
x
• .:A. A
x
x
)(
I.
~_~I_O
x
X
X
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
X
X
x
Condition Code SymbOls
H Half Carry (From Bit 31
I Interrupt Mask
N Negative (Sign Bill
Z Zero
C Carry/Borrow
524
)(
X
STX
SUB
SWI
x
x
X
•••••
•• •• •• •• ••
•••••
•••••
•• •• •• •• ••
•• •• •• •• ••
•••••
•• •• •• •• ••
• • • • 0
X.
x
x
x
)(
x
H I N Z C
·... '.
x
x
x
x
x
BIt
T_..
•
x
x
SEC
STOP
x
x
)(
x
SEI
"
)(
x
NOP
ORA
fie L
ROR
RSP
R'I
RTS
SBC
STA
x
x
L X
LSL
LSR
x
x
x
)(
x
BNE
EOR
INC
JMP
JSR
LOA
)(
x
x
Bit
Setl
C'" Branch
x
BEQ
DEC
x
x
x
x
x
BHCC
BHCS
BHI
BHS
IIIH
BIL
BIT
BLD
BLS
BMC
BMI
BMS
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
COM
;PX
)(
Indexed Indexed
18 Bltal (18 Bltal
A Test and Set if True. Cleared OtherwIse.
• Not Affected
? Load CC Register From Stack
o Cleared
1 Set
••••
X
X
X
• •••••
6805-Serles LSI Products
CDP6805G2
To minimize power consumption. all unused ROM locations
should contain zeros.
address mapping. Note that the first 128 (OOOO-007F) bytes of
EPROM 1 correspond to the CDP6805G2 internal RAM and 1/0
ports and will be ignored when generating ROM masks. Only
the first 176 (OOOO-OOAF) bytes of EPROM 2 represent user
ROM in the CDP6805G2 and all other locations are ignored.
EPROM 3 may be replaced by filling out vector list on ROM
Information Sheet since there are only 10 bytes. After the
EPROMs are marked they should be placed in conductive IC
carriers and securely packed. Do not use styrofoam.
Master-Device Method
EPROMs - 2716 EPROMs. programmed with the customer
program (positive logic sense for address and data). may be
submitted for pattern generation. Fill out Customer Information
of ROM Information Sheet. The EPAOMs must be clearly
marked to indicate which EPROM corresponds to which
~ ~ ~
1
2
3
0000
.0800
1800
xxx =Customer 10
Fig. A-1 - EPROM marking.
ROM INFORMATION SHEET
OPTION LIST
Select the options for your MCU from the following liSt. A manufacturing mask will be generated from this information.
Select one in each section.
Internal Oscillator Input
Crystal
Resistor
a
a
Column 28 of Option Card
Oar N
1 or P
Internal Divide
0+4
0+2
Column 29 of Option Card
o or N
1 or P
Interrupt
Column 30 of Option Card
o orN
lor P
a
o
Edge-Sensitive
Level- and Edge-Sensitive
VECTOR LIST
Timer Interrupt from Walt State Only
Timer Interrupt
External Interrupt
sWI
RESET
CUSTOMER INFORMATION
Customer Name
Address
City
Zip
State
Phone (
)
I
Extension
Contact Ms.lMr.
Customer Part No.
PATTERN MEDIA
o
o
o
o
6805G2
EPROM
Card Deck
Other·
·Other media require factory approval.
Signature
Title
525
RCA CMOS LSI Products
CDP6805G2
DATA PROGRAMMING INSTRUCTIONS
When a customer submits instructions for programming
RCA custom ROM's, the customer must also complete the
relevant parts of the ROM information sheet and submit this
sheet together with the programming instructions. Programming
instructions may be submitted in anyone of three ways, as
follows:
1. Computer-Card Deck-use standard 80-column computer punch cards.
2. Floppy Disketle-diskette information must be generated on an RCA CDP1800-series microprocessor
development system.
3. Master Devlce-a ROM, PROM"EPROM or CDP6805G2
that contains the required programming information.
The requirements for each method are explained In detail in
the following paragraphs:
Computer-Card Method
Use standard 80-column computer cards. Each card deck
must contain, in order, a title card, an option card, iI dataformat card, and data cards. Punch the cards as specified In
the following charts:
TITLE CARD
Column No.
Data
1
2-5
6-30
31-34
35-54
55-58
59-63
64
65-71
72
Punch T
RCA device type, without CDP68 prefix, e.g. 05G2
Punch an opening par'enthesis (
7~
Punch 8
74
Punch a closing parenthesis )
leave blank
Customer Name (start at 6)
leave blank
Customer Address or Division (start at 35)
leave blank
RCA custom selection number (5 digits) (Obtained from RCA Sales Office)
leave blank
75-78
leave blank
79-80
Punch a 2-digit decimal number to indicate the deck number;
the first deck should be numbered 01
OPTION CARD
Use the ROM Information Sheet to select the polarity options, P, N, or X, for the desired ROM type.
Column No.
1-6
Data
Punch the word OPTION
7
leave blank
8-17
RCA device type, including CDP68 prefix, e.g. CDP6805G2
18-27
leave blank
28-30
Punch P or N per ROM Information Sheet
31-78
leave blank
Punch the deck number (the 2-digit number in
79-80
columns 79-80 of the title card)
DATA-FORMAT CARD
The data-format card specifies the form in which the data is to be entered into ROM.
--
Column No.
1-11
12
13-15
Data
Punch the words DATA FORMAT
leave blank
16
Punch the letters HEX
leave blank
17-19
Punch POS
20-78
leave blank
79-80
Punch the deck number (the 2-digit number in
columns 79-80 of the title card)
_.
----
526
S80S-Serles LSI Products
CDP6805G2
DATA PROGRAMMING INSTRUCTIONS (Cont'd)
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus. sixteen words of data in clusters of four Hex Bytes.
...,,
!
Column No,
Data
Punch the starting address
Column No.
26-27
Data
1-4
in hexadecimal for the
28-29
2 hex digits of 10th WORD
following data. *
30
Blank
Blank
31-32
2 hex digits of 11th WORD
2 hex digits of 12th WORD
2 hex digits of 9th WORD
5
6-7
2 hex digits of 1st WORD
33-34
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
40
Blank
15
2 hex digits of 4th WORD
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43-44
18-19
2 hex digits of 6th WORD
45
2 hex digits of 16th WORD
Semicolon, blank if last card
20
Blank
21-22
23-24
.2 hex digits of 7th WORD
2 hex digits of 8th WORD
25
Blank
46-78
Blank
79-80
Punch 2 decimal digits
as in title card
'The address block must start at 0080 and run through 08AF. Column 4 must be zero. One additional card starting at 1FFO is required to
specify vectors. Note that as the sample program card shows, the 1FFO card must contain 16 data words. Zeros are used to fill unused
locations 1FFO - 1FFS.
OPTION DATA CARD
.
1 2 3 4 5 I 7,8 "01111213141516171.,920 2122 23 24 25 2627 28 2930 3132 3334 35 383t 3. 31 40 414243 44 45 4147484950 51525354 5556 575159 60 61626364 65818788" 70117273 74 757177 71" II
CA
p
C
'0
0
6'7
"
5
HE ..
AT
,
, FF
~"805
2..2 !I 3
SA
q 8
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P
2
S&D
'1'1'1'1
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tJ
PoS
841"
'I 5
Hj6
e
"'lll"
oe."
17"77
FEOC
88Q.,
&A"8
7"6"1
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CCD.D
6EF
F;
7654
3:2. ,
;
e
":2.11l
FlSoC
BA q
(II 8 DC
081OG!'
1/1 B £4
TIMER INTER UPTFROM
WAIT STATE ONLY
TIME
os
ISS
INTERRUPT
f (J
Ilb_"
j
EXTERNAL
INTERRUPT
OBTAIN FROM
RCA SALES
(8 )
0,
II'
01
01
01
III
IZ
SWI
RESET
DECK NUMBER
(OPTIONAL)
I
t 2 34 5 • 7 • 910 "'21314151617 '8 19 20 2122 23 24 25 28 27 282930 31323334 35 3837 3139 404142 4344 45 414748 49 50 51525354555157585960 6182 6384 8&6& 8188 8170 7172 73 n 757177 78 71 10
nCL..J&135
527
"CA CMOS LSI Products
CDP6805G2
CDP68011 FAMILY
Avallabl. Now
Technology
Number of Pins
On-Chip RAM (Bytes)
On-Chip User ROM (Bytes)
External Bus
Bidirectional 1/0 Lines
Undirectional 1/0 Lines
CMOS
40
112
None
Yes
16
None
Timer
None
Yes
Other 1/0 Features
EPROM Version
STOP and WAIT
2
CMOS
40
112
2K
None
32
None
Timer
None
Yes
CDP8805F2
CMOS
28
Technology
Number of Pins
On-Chip RAM (Bytes)
64
1K
None
20
None
On-Chip User ROM (Bytes)
External Bus
Bidirectional 1/0 Lines
Undirectional 1/0 Lines
Other 1/0 Lines
Timer
None
Yes
EPROM Version
STOP and WAIT
OPERATING AND HANDLING CONSIDERATIONS
1. Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described In ICAN-6525. "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
2. Operallng
Op.ratlng Voltag.
During operation near the maximum supply voltage
limit. care should be taken to avoid or suppress power
supply turn-on and turn-off transients. power supply
ripple. or ground noise; any of these conditions must
not cause VDD - VSS to exceed the absolute maximum
rating.
Input Signaia
To prevent damage to the Input protection Circuit. input
signals should never be greater than VCC nor less than
VSS. Input currents'must not exceed 10 mA even when
the power supply is off.
Unuaed Inputa
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
VCC or VSS. whichever Is appropriate.
Output Short Clrculta
Shorting of outputs to VDD. VCC. or VSS may damage
CMOS devices by exceeding the maximum device
dissipation.
ORDERING INFORMATION
RCA Microprocessor device packages are identified by
letters indicated in the following chart. When ordering a
Microprocessor device. it is important that the appropriate
suffix letter be affixed to the type l1umber of the device.
Pacug.
Suffix Letter
Dual-in-Llne Side Brazed Ceramic
D
Dual-In-Llne Plastic
E
Forexample. a CDP6805G2In a dual-in-line plastic package
will be identified as the CDP6805G2E.
528
6805·Serlel LSI Productl
Objective Data
,.
..
Ne
ose,
CMOS Real-Time Clock with RAM
Features:
VDD
sow
Low·Power, High·Speed. High·Density CMOS
Internal Time Base and Oscillator
AD.
CIynchronous bus structures.
The MOTEL circuit is built into peripheral and memory ICs to
permit direct connection to either type of bus. An industry
standard bus structure is now available. The MOTEL concept
is shown logically in Figure 9.
6800
Family Type
MPU Signals
Competitor Type
IvlPU Signals
ALE
AS
CDP6818
Pin Signals
AS
MOTEL selects one of two interpretations of two pins. In the
6805 case, OS and R/W are gated together to produce the
internal read enable. The internal write enable is a similar
gating of the inverse of R/W. With competitor buses, the inversion of tID and WR create functionally identical internal read
and write enable signals.
The COP6818 automatically selects the...m:0cessor type by
uSing ASI ALE to latch the state of the OS/fID pin. Since OS is
always low and Fill is always high during AS and ALE, the latch
automatically indicates which processor type is connected ..
o
U---+--tC
Competative Bus
Q
Internal
Signals
6805
Family'
Bus
OS, E, or <1>2
OS
Read Enable
R/W
R/W
Write Enable
Fig. 9 -
Functional diagram of MOTEL circuit.
SIGNAL DESCRIPTIONS
The block diagTam in Figure 1, shows the pin connection
with the major in1:farnal functions of the COP6818 Real-Time
Clock plus RAM. The following paragraphs describe the function of each pin.
Voo, VSS
DC power is prclvided to the part on these two pins, VDO
being the most positive voltage. The minimum and maximum voltages are listed in the Electrical Characteristics
tables.
OSCl, OSC2 - liME BASE, INPUTS
The time base for the time functions may be an external
signal or the cr'{stal oscillator. External square waves at
4.194304 MHz, 1.048576 MHz, or 32.768 kHz may be connected to OSCI as shown in Figure 10. The time-base frequency to be us ed is chosen in Register A.
The on-chip oscillator is designed for a parallel resonant
AT cut crystal at 4.194304 MHz or 1.048576 MHz frequencies. The crystal connections are shown in Figure 11 and the
crystal characteristics in Figure 12.
CKOUT - CLOCK OUT, OUTPUT
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. A major use for CKOUT is as the input
clock to the microprocessor; thereby saving the cost of a second crystal. The frequency of CKOUT depends upon the
time-base frequency and the state of the CKFS pin as shown
in Table 2.
.
CKFS - CLOCK OUT FREQUENCY SELECT, INPUT
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. CKFS tied to VOO causes CKOUT to be
the same frequency as the time base at the OSCI pin. When
CKFS is at VSS, CKOUT is the OSCI time-base frequency
divided by four. Table 2 summarizes the effect of CKFS.
535
I
RCA CMOS LSI Products
CDP6818
l
~
4.194304 MHz
or
1.048576 MHz
or
32.768 kHz
VO:ptional
1VOO-1.0 VI
I
I
2
•
•
OSC1
3
(Openi
-......;--t
OSC2
CDP6818
Fig. 10 - External Time-base connection .
. . . - - - - - - -....- - -....--40SC1
4.194304 MHz
or
1048576 MHz
10 M
3
....---t---t
OSC2
CDP6818
Cout'T
Fig. 11 - Crystal oscillator connection.
Crystal Equivalent Circuit
c; :Jt--L1
C1
RS
2
----1'
_3
-------tID~1
fosc
Rs max
CO max
__
4.194304 MHz
750
7 pF
1.048676 MHz
4000
5 pF
C1
0.012 pF
Cin/Cout
15-30 pF
0.008 of
15-40 pF
Q
50k
35k
Fig. 12 - Crystal parameters.
536
2
680S-Serles LSI Products
CDP6818
TABU,2 - CLOCK OUTPUT FREQUENCIES
Time BaSt B
(OSC1)
FrequenC'j
4.194304 MH , z
4.194304 MH 2'
1.048576 MH z
1.048576 MH z
32.768 kHz
32.768 kHz
SQW -
SQUARE
~
Clock Frequency
Select Pin
(CKFS)
High
Low
High
Low
High
Low
-
Clock Frequency
Output Pin
(CKOUT)
4.194304 MHz
1.048576 MHz
1.048576 MHz
262.144 kHz
32.768 kHz
8.192 kHz
VAVE, OUTPUT
The SQW pin can output a signal aile of 15 of the 22
internal-divider stagel ). The frequency aLld output enable of
the SQW may be altered by programming f~'9gister A, as shown
in Table 5. The SQW sil Jnal may be turned on arid off uSing a bit
in Register B.
ADO-AD7 - MUL TIPL .EXED BIDIRECTI·()NAL
ADDRESS/DATA BUS:
Multiplexed bus proct ,ssors save pins by presenting the
address during the first portion of the bus cycl e and uSing the
same pins during the sec lond portion for data. Address-thendata multiplexing does I ~ot slow the acces s time of the
CDP6818 since the bus n ,versal from address to data IS occurring during the internal RAM access time.
The address must be va, lid just prior to the fall ()f AS! ALE at
which time the CDP6818 latches the address I'rom ADO to
AD5. Valid write data must b, 9 Rresented and held s table during
the latter portion of the OS ( lr W1i pulses. In a rea, oj cycle, the
CDP6818 outputs 8 bits of data during the latter pc lrtlon of the
DS or RD pulses, then cea S'3S driving the bus (returns the
output drivers to three-state) when OS falls in th,'s case of
MOTEL or RD rises in the ott 1,er case.
AS -
MULTIPLEXED ADDF lESS STROBE, INPUT
A positive going multiplexed, ;!ddress strobe pulse se rves to
demultiplex the bus. The falling Isdge of AS or ALE cau~les the
address to be latched within tl 'le CDP6818. The autc )matlc
MOTEL circuitry in the CDP681 i g also latches the state of the
DS pin with the falling edge of j is or ALE.
OS -
DATA STROBE OR RE,lID,'INPUT
The DS pin has two interpretati ons via the MOTEL circl)it.
When emanating from a 6800 type processor. OS is a positil Ie
pulse during the latter portion of the" bus cycle. and is various.ly
called DS (data strobe). E (enable). and 1/J2 (1/J2 clock). Durinl1
read cycles, DS signifies the time tl ~at the RTC is to drive thE.'
bidirectional bus. In write cycles. the trailing edge of DS
causes the Real-Time Clock plus RAM to latch the written
data.
_
The second MOTEL interpretatit on of DS is that of RD,
liifE"M1"i, or'i7O"R ema .. dting from a C( lmpetitor type processor.
In this case. DS identifies the time period when the real-time
clock plus RAM drives the bus with re ,'ad data. This interpretation of OS is also the same as an OL .Itput-enable signal on a
typical memory.
The MOTEL circuit. within the CDPE :818, latches the state of
the DS pin on the falling edge of AS/ AL E. When the 6800 mode
of MOTEL is desired OS must be low d, uring AS/ ALE. which is
the case with the CDP6805 family of multiplexed bLl's processors. To insure the competitor mode of MOTEL, the OS pin
must remain high during the time AS/ ALE is high.
R/W -
READ/WRITE, INPUT
The MOTEL circuit treats the R/ill pin in one of two ways.
When a 6805 type processor is connected, R/ill is a level
which indicates whether the current cycle is a read or write. A
read cycle is indicated with a high level on R/ill while DS is
high, whereas a write cycle is a lo~on R/W durin9, DS. .
The second interpretation of R/W IS as a negative wrrte
pulse, 'Wrl, MEMW, and rrrJiiil from competitor type processors. The MOTEL circuit in this mode gives R/iI! pin the same
meaning as the write (W,) pulse on many generic RAMs.
CE -
CHIP ENABLE, INPUT
The chip-enable (CE) signal must be asserted (Iow)for a
bus cycle in which the CDP6818 is to be accessed. CE IS not
latched and must be stable during DS and AS (in the 6805
mode of MOTEL) and during iii5 and WR (in the competitor
mode). Bus cycles which take place without asserting IT
cause no actions to take place within the CDP6818. When CE
is high, the multiplexed bus output is in a high-impedance
state.
_
When CE is high, all address, data, DS, and R/W inputs from
the processor are disconnected within the CDP6818. This
permits the CDP6818 to be isolated from a powered-down
processor. When CE is held high, an unpowered device cannot
receive power through the input pins from the real-time clock
power source. Battery power consumption can thus be reduced by using a pullup resistor or active clamp on CE when
the main power is off.
i1'iQ - INTERRUPT REQUEST, OUTPUT
The IRQ pin is an active low output of the CDP68UU,hat may
be used as an interrupt input to a processor. The IRQ output
remains low as long as the status bit causing the interrupt is
present and the corresponding interrupt-enable bit is set. To
clear the IRQ pin, the processor prog'ram normally reads Register C. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the ii"il:i level is in
the high-impedance state. Multiple interrupting devices may
thus be connected to an ii'lQ bus with one pullup at the
processor.
RESET -
I
RESET, INPUT
The RESET pin does not affect the clock, calendar, or RAM
functions. On the powerup, the RESET pin must be held low for
the specified time, tALH, in order to allow the power supply to
stabilize. Figure 13 shows a typical representation of the
RESET pin circuit.
When ~ is low the following occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared to zero,
b) Alarm Interrupt Enable (AlE) bit is cleared to zero,
c) Update ended Interrupt Enable (UIE) bit is cleared to
zero,
d) Update ended Interrupt Flag (UF) bit is cleared to zero,
e) Interrupt Request status Flag (IRQF) bit is cleared to
zero,
f) Periodic Interrupt Flag (PF) bit is cleared to zero,
537
RCA CMOS LSI Products
CDP6818
g) Alarm Interrupt Flag (AF) bit is cleared to zero,
h) iRa pin is in high-impedance state, and
j) Square Wave output Enable (SOWE) bit is cleared to
zero.
01
02
System
Battery
Backup
VOO
PS - POWER SENSE, INPU"!'
The power-sense pin is u~;ed in the control 'of the valid
RAM and time (VRn bit in Hegister C. When Une PS pin is
low the VRT bit is cleared to zero.
During powerup, the PS pin must be exterrll311y held low
for the specified time, tpL. As power is applie,:J the VTR bit
remains low indicating that th'3 contents of t~1 e RAM, time
registers, and calendar are not guaranteed. INhen normal
operation commences ps. 8hould be permittf;l,d to go high.
Figure 14 shows a typical circuit connection f lor the powersense pin.
VOO
03
COP6818
POWER-DOWN CONSIDERAT!IONS
R'ESff
Io.oo51'F
D1
~ 02~ 03~
Vss
lN4148 or Equivalent
Note: If the RTC is isolated from the MPU or MCU power by a
diode drop, care must be taken to meet Yin requirements.
Fig. 13 -
Typical power-up delay circuit for ~
01
02
System
Battery
Backup
VOO
VOO
PS 1 - - -.....
COP6818
Vss
01
Fig. 14 -
In most systems, the CDP6818 must co ntinue to keep time
when system power 'is removed. In such· systems, a conversion from system povvmtoan alternate po \ IIer supply, usually a
battery, must be marJe. During the trans;i Ition from system to
battery power, the dlfJsigner of a battery Ie lacked-up RTC system must protect da.ta integrity, minimiz€1 power consumption,
and ensure hardwa,re reliability.
The chip enable ( eE) pin controls all b I JS inputs (R/W, OS,
AS, ADO-AD7). ct, when negated, dis! lliows any unintended modification of the RTC data by the '1 bus. eE also reduces
power consumpti,on by reducing the r- lumber of transitions
seen internally.
Power consun,lption may be further reduced by removing
resistive and CB pacitive loads from th ,e clock out (CKOUT)
pin and the sqt.:larewave (SOW) pin.
During and after the power sourc e conversion, the VIN
maximum specification must neve'( t Je exceeded. Failure to
meet the VIN, maximum specificclti on can cause a virtual
SCR to apperar which may result in excessive current drain
and destructi,on of the part.
~ 02~
I
lN4148 or Equivalent
ADDRESS MAP
Figure 15 shows the address; map of the CDP6818. The
memory consists of 50 generall~ Jurpose RAM bytes, 10 RAM
bytes which normally contain II' Ie time, calendar, and alarm
data, an d four control and status bytes. All 64 bytes are directly
readabl,e and writable by the proc ;essor program excePt Registers C and 0 which are read or Ily. Bit 7 of Register A and the
secorl ds byte are also read only. Bit 7, of the second byte,
alwav s reads "0". The conteM, s of the four control and status
regis,j,ers are described in the Register section.
TP",nE, CALENDAR, AND Al.ARM LOCATIONS
. The processor program obtains time and calendar inforn.l.ation by reading the appr'c Jpriate locations. The program
IT,lay initialize the time, calf3 ndar, and alarm by writing to
Lhese RAM locations. The c c mtents of the 10 time, calendar,
and alarm byte may be eithHI r binary or binary-coded decimal
(BCD),
Typical power-up delay circuit for POWER SENSE.
538
.
6805-Serles LSI Products
CDP6818
-,
Before initializing the internal registers, the SET bit in
Register B should be set to a "1" to prevent time/calendar
updates from occurring. The program initializes the 10 locations in the selected format (binary or BCD), then indicates
the format in the data mode (OM) bit of Register B. All 10
time, calendar, and alarm bytes must use the same data
mode, either binary or BCD. The SET bit may now be cleared
to allow updates. Once initialized the real-time clock makes
all updates in the selected data mode. The data mode cannot
be changed without reinitializing the 10 data bytes.
Table 3 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24/12 bit in Register B
establishes whether the hour locations represent 1-to-12 or
o
00
14
Bytes
13
00
14
OE
50
Bytes
User
RAM
63
3F
O-to-23. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected
the high-order bit of the hours byte represents PM when it is
a "1".
The time, calendar, and alarm bytes are not always accessable by the processor program. 'Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248,.s at the 4.194304 MHz and
1.048567 Mj-lz time bases and 1948 ,.s for the 32.768 kHz
time base. The Update Cycle section shows how to accommodate the update cycle in the processor program.
0
Seconds
1
Sec Alarm
01
2
Minutes
02
3
Min Alarm
00
03
4
Hours
04
5
Hr Alarm
05
6
Day of Wk
06
7
Date of Mo
07
8
Month
9
Year
Binary
or BCD
Contents
08
09,;
10
Register A
11
Register B
OB
12
Register C
DC
13
Register 0
00
OA
Fig. 15 - Address map.
-
TABLE 3 - TIME, CALENDAR, AND ALARM DATA MODES
Address
Location
Decimal
Range
0
Seconds
0-59
$00-$3B
$00-$59
15
1
Seconds Alarm
0-59
$00-$36
$00-$59
15
21
2
Minutes
0-59
$00-$36
$00-$59
3A
58
3
Minutes Alarm
0-59
$00-$36
$00-$59
3A
58
Hours
(12 Hour Mode)
1-12
$01-10C lAM} and
$81-$8C (PM)
$01-$12 (AM) and
$81-$92 (PM)
05
05
Hours
124 Hour Mode}
0-23
$00-$17
$00-$23
05
05
Hours Alarm
112 Hour Mode}
1-12
$OI-$OC lAM} and
$81-$8C (PM)
$01-$12 lAM} and
$81-$92 (PM)
05
05
Hours Alarm
124 Hour Mode}
0-23
$00-$17
$00-23
05
05
6
Day of the Week
Sunday = 1
1-7
$01-$07
$01-$07
05
05
7
Day of the Mo,lth
1-31
$OI-$IF
$01-$31
OF
15
8
Month
1-12
$Ol-$OC
$01-$12
02
02
9
Year
0-99
$00-$63
$00-$99
4F
79
4
5
Range
Binary Data Mode BCD Data Mode
Example"
Binary
BCD
Data Mode Data Mode
Function
21
I
• Example: 5:58:21 Thursday February 1979
539
RCA CMOS LSI Products
CDP6818
The three alarm bytes may be used in two ways. When the
program inserts an alarm time in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is
initiated at the specified time each day if the alarm enable bit
is high. The alternate usage is to insert a "don't care" state in
one or more of three alarm bytes. The "don't care" code is
any hexadecimal byte from CO to FF. That is, the two mostsignificant bits of each byte, when set to "1", create a "don't
care" situation. An alarm interrupt each hour is created with
a "don't care" code in the hours alarm location. Similarly, an
alarm is generated every minute with "don't care" codes in
the hours and minutes alarm bytes. The "don't care" codes
in all three alarm bytes create an interrupt every second.
STATIC CMOS RAM
The 50 general purpose RAM bytes are not dedicated within
the CDP6818. They can be used by the processor program,
and are fully available during the update cycle.
When time and calendar information must use battery
back-up, very frequently there IS other non-volatile data that
must be retained when main power is removed. The 50 user
RAM bytes serve the need for low-power CMOS batterybacked storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional
CDP6818s may be included in the system. The timet calendar functions may be disabled by holding the dividers, in
Register A, in the reset state by setting the SET bit in CR2 or
by removing the oscillator, Holding the dividers in reset
prevents interrupts or SQW output from operating while setting the SET bit allows these functions to occur. With the
dividers clear, the available user RAM is extended to 59
bytes. Bit 7 of Register A, Registers C and D, and the
high-order 8it of the seconds byte cannot effectively be used
as general purpose RAM.
INTERRUPTS
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for
rates from half-a-second to 30.517 p.s. The update-ended
interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt
conditions are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register B enable the three
interrupts. Writing a "1" to a interrupt-enable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the interrupt-enable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt
becomes enabled, the IRQ pin is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before first
enabling new interrupts.
540
When an interrupt event occurs a flag bit is set to a "1" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The "interrupt" flag bit becomes a
status bit, which the software interrogates, when it wishes.
When the software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the
bit was last read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching isincluded with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
all utilized flag bits every time Register C is read to insure
that no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable bit is also set, the IRQ pin is
asserted low. IRQ is asserted as long as at least one of'the
three interrupt sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the IRQ pin is
being driven low.
The processor program can determine that the RTC
initiated the interrupt by reading Register C. A "1" in bit 7
IIRQF bit} indicates that one or more interrupts have been
initiated by the part. The act of reading Register C clears all
the then-active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual
flag bits in the same byte which have the corresponding
interrupt-mask bits set and service each interrupt which is
set. Again, more than one interrupt-flag bit may be set.
DIVIDER STAGES
~.:"t1t
The CDP6818 has 22 binary-divider stages following the
time base as shown in Figure 1. The output of the dividers is a 1
Hz signal to the update-cycle logic. The dividers are controlled
by three divider bits (DV2, DVI. and DVO) in Register A.
DIVIDER CONTROL
The divider-control bits have three uses, as shown in Table
4. Three usable operating time bases may be selected
14.194304 MHz. 1.048576 MHz, or 32.768 kHz}. The 2
'0
>0
2'
28
27
2.
"
12
"••
,.
,.,.
IS
,.
17
2'
2
2
2'
20
peS/CAe!'
PC6/CB
PC7lC82
PBO
PB'
PB2
PB'
PB.
PB.
P8.
PB7
IRQ
Features:
• 24 Individual Programmed I/O Pins
• MOTEL Circuit for Bus Compatibility with Many Microprocessors
• Multiplexed Bus Compatible with: CDP6805E2 and Competitive Microprocessors
•
•
Data Direction Registers for Ports A, B, and C
Port C may also be Control Lines for:
Four Interrupt Inputs
Input Byte Latch
Output Pulse
•
•
16 Registers Addressed as Memory Locations
Handshake Control Logic for Input and Output Peripheral Operation
•
•
Interrupt Output Pin
Reset Input to Clear Interrupts and InitializelnterQilI Registers
R/W
AS
TOP VIEW
92C5·
CMOS Parallel Interface
REm
os
cr
3~1I4
TERMINAL ASSIGNMENT
CDP6823
• 40-Pin Package
The CMOS CDP6823 Parallel Interface (PI) provides a universal means of interfacing external signals with the CDP6805E2
CMOS microprocessor, and other multiplexed bus microprocessors. The unique MOTEL circuit on-chip allows direct interfacing to most industry CMOS microprocessors, as well as
many NMOS MPUs.
The CDP6823 PI includes three bidirectional8-bit ports, or 24
I/O pins. Each I/O line may be separately established as an
input or an output under program control via data direction
registers associated with each port. Using the bit change and
test instructions of the CDP6805E2, each ihdividuall / 0 pin can
be separately accessed. All port registers are read/write bytes
to accommodate read / modify /write instructions
CMOS
Microprocessor
Bus
16 Addressable
Bytes
Interrupt
20·to·24
Bid,rectional
I/O
Mux
Bus
Interrupt
Control
40
Fig. 1 -
O·loA
Port Control
and/ or
Interrupts
I
PinS
Functional diagram.
547
RCA CMOS LSI Products
6805-Serles LSI Products
CDP6823
CDP681a
Real-Time Clock
Plus RAM
3
Clock
~
l
3
1
8
I
l
CDP65516I
16K ROM I
CDP65516I
16K ROMJ
CDP65516I
16K RDMJ
a
3
5
3
5
8
5
Mux Add~JData
High Addr
5
Interrupt
Reset
1
Chip
EnablesL----il......
+--+-+--+--------..-.,f-+-i-+-----
, 1 V,
5
8
a
74HCI38
Decoder
a
11
3
1 '8
CDP6a23
Parallel Interface
fa
fa
8 '3
CDP6a23
Parallel Interface
i
An 8-Chip CMOS Microprocessor System Includes;
Powerful.8-Bit Processor
6 K Bytes of ROM
162 Bytes of RAM
64 Parallel 1/0 Pins
1 '1
f fa
8
fa
Up to 12 System Interrupts,
Timer Interrupt
Periodic Interrupt
Alarm Time Interrupt
Update Cycle (1 Secondt Interrupt
Up to External Event Interrupts
Time-Of-Day and Calendar
8-Bit Programmable Counter with 7-Bit Prescaler
a
Fig, 2 - A typical CMOS microprocessor system,
Four of the 24 I/O pins have multiple functions, The mode of these
four lines is selected by programming the Port C Pin Function Select
Register. Any of the four control pins may be configured to initiate
interrupts to the microprocessor via the iRG pin. All four interrupts
have separate programmable enables, status bits, methods of clearing
the interrupt, and over-run detection.
The interrupts are enabled and the port handshaking controls are
established via the content of Control Registers associated with Ports A
The interrupt conditions are indicated in a Status Register and
and
the IRQ pin is asserted. The interrupts are normally cleared by reading
or writing the associated port data. Ports A and B each have three
addresses for reading/writing data. Two addresses access the data and
clear an interrupt while the third accesses the data without modifying
the interrupt status.
.!L.
548
CDP6823 Registers
o
Port A Data, Clear CAl Interrupt
1
Port A Data, Clear CA2 Interrupt
Port A Data
2
3
4
5
6
7
8
9
A
Port B Data
Port C Data
Not Used
Data Direction Register
Data Direction Register
Data Direction Register
Control Register for
Control Register for
for Port A
for Port B
for Port C
Port A
Port B
8
C
Pin Function Select Register for Port C
Port B Data, Clear CBl Interrupt
D
E
F
Port B Data, Clear CB2. Interrupt
Interrupt Status Register
Interrupt Over-Run Warning Register
Supplementary Information
549
RCA CMOS LSI Products
RCA High-Reliability IC Capability
RCA Solid State is a leading supplier of high-reliability
integrated circuits to the military and aerospace community. Years of commitment, dedication, experience, and
know-how make possible shipment of hundreds of thousands of quality high-reliability microcircuits annually.
RCA specialists fully understand the needs of component
and systems engineers in the design of high-reliability
equipment, are thoroughly familiar with the objective €\nd
requirements of MIL-STO-883 and MIL-M-38510, and work
closely with governmental agencies in the establishment of
detailed specifications for high-reliability microcircuits.
Moreover, RCA provides complete facilities for processing
and testing integrated circuits to these specifications. RCA
is justly proud of its many significant accomplishments with
respect to the development, production and shipment of
high-reliability integrated circuits, including:
• First supplier of MIL-M-38510 to attain QPL Class S Part
One Radiation-Hardness Listing
• First supplier of MIL-M-38510 CMOS integrated circuits
• Leader in the production of radiation-resistant CMOS
microcircuits [to 1 x 10· rad (Si))
• Initiator of scanning-electron-micrbscope (SEM) inspections in the production of high-reliability microcircuits - in use at RCA since 1972
• Initiator of MIL-STO-883, Condition A inspections - in
use at RCA since 1972
• A leading supplier of dielectrically isolated circuits
Standard-Product High-Reliability IC's
RCA offers high-reliability versions of virtually its entire line
of standard-product integrated circuits from the C04000
series of CMOS digital logic types, the COP1800 series of
microprocessor and associated memory and input/output
(1/0) types, and the CA3000 series of bipolar linear types.
These integrated circuits are processed and screened to
MIL-STO-883 Class B requirements. Extensive inventories
are maintained for rapid, off-the-shelf delivery.
RCA also offers high-reliability versions of standardprod uct types that are processed and screened to special
customized specifications, especially for the aerospace
user and others wh 0 procure types to Class S speCifications.
RCA maintains an extensive computer file of customer
specifications and has the methodology required to translate these customized specifications into internal RCA
standards and factory operating procedures. In addition to
the detailed device specifications, the computer file lists the
customer specification number, any revision number, and
the RCA custom number assigned to a specific device type.
radiation dosage of 105 rads(Si) for Z-suffix types or 10"
rads(Si) for J-suffix types. Selected COP1800-series CMOS
integrated circuits are available to various levels of raiflation hardness. In addition. RCA offers a spectrum of
radiation-hardened bipolar integrated circuits that employ
dielectric isolation and diode-photocurrent compensation,
High-Reliability Custom IC',
RCA has complete custom-circuit capabilities for various
CMOS and bipolar integrated-circuit technologies. Custom
circuits are offered whenever this approach to integratedcircuit design is determined to be economically feasible.
RCA high-reliability custom integrated circuits can be processed and screened to MIL-STO-883 Class S and Class B
specifications. These custom circuits, which are described
in detail in later sections of this OATABOOK. include:
• Gate universal arrays
• EPIC 8-bit slice microcomputer family and associated
memory (RAM) complement
• Radiation-hardened linear IC's
• Radiation-hardened high-speed bipolar IC's.
f1rC\~~~'~
.1.01'
Radiation-Hardened High-Reliability IC's
RCA also offers radiation-hardened versions of highreliability (Class S and Class S format) C04000-series
CMOS integrated circuits. Radiation-hardened types,
which are identified by additon of a "z" or "J" suffix to the
device type number, are electrically and mechanically identical to their prototype with the exception that they are
processed and screened to withatand a total gamma-
Sample pages of RCA', computer file on standard-product highreliability IC's processed to special custom specification•• The file
can be accessed by device specification number, by customer or
by the RCA custom number assigned to the device.
RCA also provides a broad line of high-reliability discrete solid-state power devices
(power transistors, triacs, and silicon controlled rectifiers). These devices include types
qualified as JAN or JANTX devices in accordance with MIL-STO-19500 General
Specifications and MIL-STO-750 Test Methods, types that are not yet covered by
military specifications but that are processed and screened to specifications patterned
after the military standards, and types that are specially designed and processed to
withstand high radiation enviroments.
550
.
Supplementary Information
Dimensional Outlines
Dual-In-Llne Pla,tlc Package,
ESUFFIX
18-Lead (E • F)
(JEDEC MO-o01-AC)
!sYMBOL
A
AI
.........
......
........
B
~
Bl
C
0
E
El
·1
eA
L
L2
a
N
Nl
°1
5
INCHES
MIN. MAX.
0.155 0.200
0.020 0.050
0.014
0.035
0.020
0.085
0.008
0.745
0.300
0.240
0.012
0.785
0.325
0.260
18-Lead
NOTE
I
O.looTP
2
O.300TP
2,3
0.125
0.000
15°
16
0
0.356
0.89
0.508
1.85
0.204
18.93
7.62
6.10
0.304
19.93
8.25
6.80
4
5
6
SYMBOL
B
a,
C
0
.,
E,
·A
L
a
N
N,
S
7.62TP
3.81
0.76
li'l
INCHES
NOTE
MIN. MAX.
0.156 0.200
0.020 0.060
0.014 0.020
0.035 0.085
0.008 0.012
0.B45 0.885
0.240 0.280
0.100 TP
0.3OOTP
0.12510.150
O· 1 15·
18
A
AI
2.54TP
3.18
0.000
0.150
0.030
Ii'
MILLIMETERS
MAX.
MIN.
5.08
3.94
1.27
0.51
1
2
2,3
4
5
"
6
0.015 10.060
15°
MILLIMETERS
MIN.
MAX.
3.94
5.08
0.508
1.27
0.356
0.508
0.89
1.65
0.204
0.304
21.47
22.47
8.10
8.80
2.54 TP
7.62TP
3.18
3.81
O·
15·
18
0
0.39 I 1.52
92CS-30630
16
0
0.040
0.075
1.02
1.90
0.015
0.060
0.39
1.52
92CM-le967R4
20-Lead
INCHES
SYMaO
A
AI
A2
a
al
C
D
D2
E
El
Bl
eA
ea
L
N
8
NOTES:
1. Reier 10 JEDEC Publlcallon No. 85 JEDEC R....•
tared and Standard OuUlnn lor Solid Stata Producla,
lor rul. and generallnlormallon concemlng retl.·
tared and I .. ndlrd oualnal.
2. Prolrullona (n_h) on the blH plana IUrlace Ihall
not 8 .._
.25 mm (.010 In.).
3. The dlmenllon Ihown II lor luilleadi. "Hili- leadl
N N
a,. opllonalalilld pOllllonll, N, 2' 2 +1.
4. Olmen.lon 0 doe. nol Include mold " .. h or
prolru.lon.. Mold llalh or prolrtllloni Ihall not
exceed .25 mm (.010 In.).
5. Thll dlma",1on II conirolllnll when I particular
comblnaUon 01 body lenlllh, leld width. and Illd
Ipaclng ellmanllonl would allow lead mlterlal 10
overhanllthe endl 01 lhe plckallB.
e. E I. the dlmenolon 10 Ihe oullidl 01 Ihellad. Ind I.
mlliured wllh the ..adl plrpendlcular 10 the blH
plane (zero lead Ipread).
7. Dlmanllon El doe. nol Include mold "alh or
prolrullonl.
MILLIMETERS
NOTE
MIN.
MAX.
0.210
0.010
-
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.125
1.040
0.005
0.300
0.325
0.240
0.280
0.110
0.010
0.3GOTP
-
0.115
-
\ 0.410
0.150
20
I
-
MIN.
10
10
3
4
5
8
7,8
9
10
11
10
12
13
MAX.
5.33
0.254
-
2••3
4.85
0.358
0.558
1.15
1.77
0.204
0.381
23.41
28.42
0.13
7.82
8.25
8.10
7.11
2.79
2.21
7.82TP
-
-
2.13
-
\10.41
3.81
20
I
T
I
-
'2CM·3513.
8. Peckllgabody and IeedlIheII burmmellfc8laround
cenler Une Ih_n In end view within .25 mm (.Gl0
In.).
•• Lead lpaclng el ahaJl be non-cumula\IYe and abel!
be meaaured aJthe lead lip. Th"meuurantenlahall
be madl belore lnaertlon Into gaugH, boardl or
lockllll;
10. Thll II a bellc Inlllellad ell_Ion. u..uremanl
Ihlll be made with the device lnatalled In the _Ung
plane gauge (JEOEC OuUlne No. OW, , ..ling
plane gaUlle). L..dlabell be In true pollUon within
.25 mm (.Gl0 In.) dlam_ lor dlmenllon eA.
11. ea .. Ihe dlmenllon 10 Ihe outllde ollhele. . and II
mealured II the lead 1Ip1 belO,. the davlce ..
Inlllellad. Nqallvetead Ipread I. not permitted.
12. N .. the maximum number ot llad poIIIIonl.
13. Olmanalon S al Ihe Iell end 01 the pickage mu.1
equII dlmenllon S althe rlllhi end 01 the pac......
wllhln.71 mm (.G30 In.).
551
RCA CMOS LSI Products
Dimensional Outlines (Cont'd)
Dual-In-Llne Plastic Packages
E SUFFIX
22-Lead
..........
INC
MIN .
0.155
0.020
0.015
0.035
0.008
IES
MAX.
0.200
0.050
0.020
0.085
0.012
1120
0.390 0.420
0.345 0.355
0.100TP
0.4OOTP
0.125 0.150
0
0.030
2"
150
22
0
0.055 0.085
0.015 0.060
SYMBOL
A
••TlMGPLMI.
A_~
B
B1
C
0
E
E
81
8A
L
L2
'"
N
N,
0,
S
NOTE
1
2
2.3
4
5
6
MI IMETER"
MIN.
MAX.
3.94
5.08
1.27
0.508
0.381
0.508
1.65
0.89
0.204
I,~'~
9.91
10.66
8.77
9.01
2.54 TP
10.16TP
3.81
3.18
0
0.762
2"
150
22
0
1.40
2.15
0.381
1.27
24-Lead
(JEDEC MO-G15-AA)
SYMBOL
A
AI
B
Bl
C
0
E
e,
81
tA
L
L2
a
N
Nl
0,
S
28·Lead
SYMBOL
.0.120 0.250
0.020 0.070
3.10
0.51
6.30
1.77
8,
B
0.016 0.020
0.028 0.070
0.407
0.72
0.508
1.77
C
0.008 0.012
1.400 1.490
0.515 0.580
1
0
E,
0.204
35.56
13.09
0.304
37.85
14.73
81
eA
0.100 TP
0.600 TP
2
2.3
L
L2
0.100 0.200
0.000 0.030
N
N,
0,
S
INCHES
MILLIMETERS
NOTE
MIN. MAX.
MIN. MAX.
0.120 0.250
3.10 6.30
0.020 0.070
0.61
1.77
I~:g~: I~:~;~
0.009 0.012
1.20 .1.29
0.600 0.626
0.516 0.580
0.100 TP
0.600 TP
0.100 0.200
0.000 0.030
150
00
24
0
0.040 0.075
0.040 0.100
U.4UI
1
2
2.3
4
5
6
~:~~
0.72 I
0.204 0.304
30.48 32.76
16.24 15.87
13.09 14.73
2.54 TP
15.24 TP
2.54 5.00
0.00 0.76
00
150
24
0
1.02 1.90
1.02 2.54
92CS26938R3
INCHES
NOTE MILLIMETERS.
MIN.
MAX.
MIN. MAX.
A
AI
a
92C8-30830
00
I 150
28
0
0.045 0.080
0.040 0.100
2.54 TP
15.24 TP
2.54
0.00
4
5.00
0.76
150
00
5
28
0
6
1.14
1.02
40-Lead
SYMBOL
A
Al
B
B,
C
D
El
.,
°A
L
L2
"N
Nl
ul
S
I MILLIMETERS
INC:HES .
NOTE
MIN. MAX.
MAX.
MIN.
8.30
0.120 0.250
3.10
1.77
0.020 0.070
0.51
0.018 0.020
0.407
0.508
0.72
1.77
O.02B 0.070
0.304
1
0.008 0.012
0.204
6a09
2.000 2.090
50.80
14.73
0.616 0.680
13.09
0.1110 TP
2.1>· TP
2
16.24
TP
O.600TP
2.3
,g:~lg:=
1l)V
II"
40
0
I
: 0.0Ii0 0.l1li11
0.040 0.100
15u
00
5
40
0
6
1.66
1.02
2.41
2.54
92CS-3OB5B
2.03
2.54
92CS·31862
NOTES:
Ref.r to Rules for Dimensioning (JEDEC Publication
No. 96) for Axial Load prOduct Outlines.
1. When this device is supplied solder dipped. the
maximum lead thickness (nerrow portion) will not
exceed 0.013" (0.33 mm).
g::
~::
4
2. Loads within O.OOS" (0.12 mm) radius of Tru.
Position (TP) at gauge plane with maximum
material condition and unit installed.
3. oA applies in zone L2 when unit installad.
4. a applies to sproad laads prior to installalion.
5. N is the maximum quantity of load poSitions.
6. N1 is the quantity of allowable missing loads.
552
..
Supplementary Information
Dimensional Outlines (Cont'd)
Dual-In-Llne Side-Brazed Ceramic Package.
o SUFFIX
18-Lead
SYMBOL
18-Lead
MILLIMETERS
INCHES
NOTE
MIN. MAX.
MIN. MAX.
A
-
0.830
C
-
0.200
0
0.Q15 0.021
F
0.045 0.010
1
G
O.IOC 8SC
1
H
0.015 0.090
J
0.008 0.012
K
0.125 0.150
L
0.290 0.310
3
2
-
21.08
A
5.08
C
0.381
0.533
1.143
1.178
2.~
2.286
0.203
0.304
3.115
3.810
1.386
1.874
M
0"
Is"
rI'
P
0.020
-
0.508
N
16
0
F
G
H
J
K
L
M
P
N
8SC
0.381
INCHES
NOTE MILLIMETERS
MIN. MAX.
MIN.
MAX.
SYMBOL
15"
0.890 0.915
- 0.200
0.Q15 0.021
0.054 REF.
0.100 BSC
0.035 0.065
0.008 0.012
0.125 0.150
0.290 0.310
00
150
0.025 0.045
18
22.606
23.241
5.080
0.381
0.533
1.371 REF.
2.54 BSC
0.889
1.651
0.203
0.304
3.175
3.810
7.366
7.874
00
15 0
0.635
1.143
18
-
1
1
3
2
-
92CS·27231 R1
16
92CS·31130
20-Lead
INCHES
SYMBO
MILLIMETERS
NOTE
eA
L
MIN.
MAX.
0.105
0.175
0.025
0.055
0.015
0.021
0.038
0.060
0.008
0.015
0.970
1.020
0.290
0.325
0.280
0.310
0.090
0.110
0.3OOTP
0.175
0.125
L2
0.000
0.030
-
a
O·
15·
3
A
Al
B
1,
C
0
E
E,
e,
H
0,
S
20
0.005
0.030
6
6
5
1
1,2
6
MIN.
MAX.
4.445
2.667
1.397
0.835
0.381
0.533
0.985
1.524
0.203
0.381
24.638 25.908
7.366
8.255
7.112 7.874
2.794
2.288
7.620 TP
3.175
4.445
o·
-
-
15·
20
4
0.085
0.762
0.000
0.127
0.762
I
-
I 1.651
92CM-35139
NOTES:
1. Leado within 0.005" (0.13 mm) radluo of True Poeillon
(T .P.) M gauge plane wHh maximum mlllrlal concllUon
and unit lnotalled. Lead ,pRing " ohall lie noncumulatlv. and ohal. O. maa,ured Ilth,leld tip. Thlt
me..uramenl .hall be made Oefora In..rllon Inlo
gauge" boardo, or .ockel..
2. eA appill. In zone LZ whan unit .. In.talled.
3. a Ippll•• 10 .pread 1.ldl prior 10 Inlllnlllon.
4. N.o the number of lermlnal _Dlonl.
5. El dos. nollnclude plrllel•• of ploklge INllarllll.
8. Thll ellmanalon .hln be mauurad wHh the device
•••Ied In Ihe Hilling pllne glug. JEOEC Outline No.
GS-3.
553
RCA CMOS LSI Products
Dimensional Outlines (Cont'd)
Dual-In-Llne Side-Brazed Ceramic Packages
DSUFFIX
22-Lead
SYMBOL
A
e
0
F
G
H
J
K
L
M
P
N
INeliES
MIN.
MAX.
1.065 1.085
0.090 0.150
0.017 0.023
0.040 REF.
0.100 Bse
0.030 0.045
0.008 0.012
0.125 0.145
0.390 0.420
7°
0.025 0.050
22
NOTE
1
3
2
MIL !ETERS
MIN.
MAX.
27.06
27.55
2.29
3.81
0.44
0.68
1.02 REF.
2.54BSC
1.14
0.77
0.21
0.30
3.68
3.18
9.91
10.68
70
0.64
1.27
22
92CS·25186R3
24-Lead
SYMBOL
A
C
0
F
·G
'H
J
K
L
M
P
N
INCHES
MIN.
NOTE
MAX.
1.180
1.220
0.086
0.146
0.015
0.023
0.040 REF.
O.l00BSC
0.070
0.030
0.008
0.012
0.175
0.125
0.580
0.620
0.025
7"
0.050
24
MILLIMETERS
MIN.
1
3
2
MAX.
29.98
30.98
2.18
3 ••
0.38
0.68
1.02 REF.
2.54BSC
1.77
0.77
0.21
0.30
3.18
4.44
14.74
15.74
7"
0.64
1.27
24
92CS·30988R 1
4G-Leed
28-Lead
SYMBOL
A
C
0
F
G
H
J
K
L
M
P
N
INCHES
MIN. MAX.
1.380 1.420
0.085 0.145
0.017 0.023
0.050 REF.
0.100 sse
0.030 0.070
0.008 0.012
0.125 0.175
0.580 0.620
JO
0.025 0.050
28
NOTE
1
1
3
2
MILLIMETERS
MIN. I MAX.
35.06
36.06
3.68
2.16
0.56
0.43
1.27 REF.
2.54 BSC
0.76
1.78
0.20
0.30
3.18
4.45
14.74
15.74
70
0.64
1.27
28
-
Q2CM-26419R 1
SYMBOL
NOTE MILLIMETERS
INCHES
MIN.
MIN.
A
MAX.
1.980 2.020
C
0
0.095 0.155
0.017 0.023
60.30
2.43
0.43
F
0.050 REF.
O.l00BSC
H
0.030 0.070
J
0.008 0.012
K
0.125 0.175
L
0.580 0.620
-
3.93
0.58
1.27 REF.
G
M
MAX.
51.30
1
3
.r---
70
P
0.025 0.050
N
40
2
2.54BSC
0.78
1.78
0.20
0.30
3.18
14.74
4.46
15.74
-'
70
0.64
1.27
40
92CM~7029R2
NOTES:
1. Loads within 0.005" (0.13 mm) radius of Truo
Position at maximum material condition.
2. Conter to center of loads when formaci perallel.
3. When this device is supplied solder dipped, tho
maximum lead thickness (narrow portion) will not
oxcoad 0.013" (0.33 mm).
554
Supplementary Information
Dimensional Outlines (Cont'd)
Dual-In-Lln. C....mlc Packeg.
D SUFFIX
18-L.ad
~YMBOL
A
Al
INCHES
MlI.X.
MIN.
0.120
0.160
0.065
0.020
B,
0.014
0.035
0.020
0.065
C
0
E
E,
0.008
0.746
0.300
0.240
0.012
0.785
0.325
0.260
B
'I
'A
L
NOTES:
R_ to JEDEC Publicotion No. 96 for Ru" for
~in. A.ioI LIod Product o..tll.....
1. _this ....i.. I. IUpplled '--dlppod,"'"
_imum ..... thiclc_ (nonow portlonl will not
••GIId 0.013" (0.33 mml.
2. L _ within 0.006 .. (0.127 mml ,lCIiu. of TNI
_
(TPlII ..... pi.... with moximum
_ i l l condition.
3. " ..... 0A oppIy in . _ L2 _
unit is instilled.
4. AppllII to .........
prior to iM1ollllion.
S. N i."", muimum qu..tIty of I.... pooitiOftL
8. Nl I."", _litv of III......... milli",I_.
24-L••d
(JEDEC MO-015-AG)
L2
4
NOTE
1
O.l00TP
2
O.300TP
2,3
0.125
0.000
15°
16
N
a
Nl
01
0.050
0.085
S
0.015
0.060
1_
4.06
1.65
0.356
0.89
0.508
1.66
0.204
18.93
7.62
6.10
0.304
19.93
8.25
6.60
2.54 TP
7.62 TP
4
5
6
3.81
0.76
rfJ
15°
16
0
INCHES
MILLIMETERS'
NOTE
MIN. MAX.
MIN.
MAX.
SYMBOL
A
3.05
0.51
3.18
0.000
0.150
0.030
001
MILLIMETERS
MAX.
MIN.
Al
B
Bl
C
0
E
El
81
8A
L
L2
a
N
Nl
0,
S
0.090 0.200
0.020 0.070
0.015 0.020
0.046 0.055
0.008 0.012
1.15
1.22
0.600 0.625
0.480 0.520
O.I00TP
0.600TP
0.100 0.180
0.000 0.030
00
150
24
0
0.020 0.080
0.020 0.080
1
2
2,3
4
5
6
2.29
5.08
0.51
1.78
0.381
0.508
1.143
1.397
0.204
0.304
29.21
30.98
15.24
15.87
12.20
13.20
2.54TP
15.24 TP
2.54
4.57
0.00
0.76
00
150
24
0
0.51
2.03
1.62
0.51
92CS-19948R4
1.27
2.15
0.39
1.52
92SS-428SR5
Ceramic Flat Pack
K SUFFIX·
TERMINAL "114"
I
I
I
..
•-
I
I
I
I
I
...
r-
I
.... ~
- -
I
1
f-.
-~
.~
I
H
I
I
m~x
- -
I
I
1
I I LlL~
I
I
,-
-
I
, ,
-B-.
-
- • f-.
I
l-
J~~~
SEATING
PLANE
92CS-19949R2
SYMBOL
A
B
C
,
E
H
L
N
a
S
Z
Z,
INCHES
NOTE
MIN.
MAX
0.075 0.120
0.018 0.022
0.004 0.007
O.05OTP
0.600 0.700
1.150 1.350
0.225 0.325
24
0.035 0.070
0.060 0.110
0.700
0.750
1
1
2
3
1
4
4
MILLIMETERS
MIN.
MAX.
3.04
1.91
0.458
0.558
0.102
0.177
1.27 TP __
15.24
17.78
29.21
34.29
8.25
5.72
24
1.77
0.89
2.79
1.53
17.78
19.05
I
NOTES:
1. Refer to JEDEC Publication No. 95 for Rules for
Dimensioning Peripheraf Lead Outlines,
2. Leads within 0.005" (0.12 mm) radius of True
Position (TPI at maximum material condition.
3. N is the maximum quantity of lead positions.
4. Z and Z, determine a lone within which all body
and lead irregularities lie.
'This package is used for CD4036K and CD4039AK types only.
555
RCA CMOS LSI Products
Application Notes - Abstracts
ICAN-8315
COS/MOS Int.rf.clng Simplified. • . • . . • . • .. • . .. .. .. .. .. • ... 8
Example of practical circuits for a wide variety of interfacing
situations are given in this Note; design constraints are
included In each case.
ICAN-8418
An Introduction to MlcroproceHO... and the
RCA COSMAC COs/MOS Mlcroproce..or •••.•......•..••. 8
This Note is an introduction to the fundamentals of microprocessors and to' the specific capabilities of the RCA
COS MAC microprocessor.
ICAN-8525
Guld. to B.tler Und....tandlng and Ope...tlon of
COS/MOS Integ...t.d Clrculta ............................. 6
This Note recommends specific handling and operating
practices that minimize the probability of damage to CMOS
integrated circuits In the manufacturing operation and the
field environment.
ICAN-8538
Us. of CMOS ROMI CDP1S31 and CDP1S32 with the
RCA Mlcroproc.Hor Ev.luatlon Kit CDP1SS020· •.••..•.... 4
This application note describes the operation and design of
CDP1 131- and COP1 S32-based read-only memory systems in
the COP18S020 Evaluation Kit.
ICAN-8537
U.. of CMOS RAM CDP1S24 with the
RCA Mlcroproc.Hor Evaluation Kit CDP1SS020· ••••..••.•. 4
This Note describes the COP1824, its application in the
COP18S020 Evaluation Kit, and presents examples of how the
CDP1824 can be combined with the COP1831 ROM to form
efficient ROM-RAM systems.
ICAN-853S
Use of the CDP1 852 8-Blt 110 Port with the
RCA Mlcroproc•••or Evaluation KIt CDP1SS020· •....•..••. 4
This Note describes several applications of the CDP1 852 I/O
port and especially explains its use in the COP18S020
Evaluation Kit.
ICAN-8539
u.. of CMOS-SOS RAM CDP1S22 with the
RCA Mlcroproce••or Evaluation Kit CDP1SS020· ....•.••.•• 4
This application note describes the CDP1822, its operation,
and its application in the COP18S020 Evaluation Kit.
ICAN-85S2
R.gl.tar-B..ed Output Function lor
RCA COSMAC MlcroproceHo... . .. • • . • .. • . .. . • .. . • . . • .. . .. 2
This Note describes a circuit for use with RCA COS MAC
Microprocessors; the circuit provides the capability to output
information from any of the 16 general-purpose scratchpad
registers contained within the CPU.
ICAN-8585
Delllgn of Clock Generato... for use with the
RCA COSMAC MlcroproceHorCDP1802 .•..•.••.•.•.•.••.• 4
This Note describes ciock generator designs suitable for
various applications.
ICAN-8581
Po_r-On Re..t/Run Clrcul.. for the
RCA CDP1802 COSMAC Mlcroproce..or •.•••.•..••..•..••. 2
This Note describes severai Circuits which enabie a power-on
reset/run capability for COSMAC microprocessor systems.
ICAN-8595
Interfacing Analog and Digital DIsplays with
CMOS Integrated Circuit••..•....••.••••.•...•••...•..... 12
This Note describes some of the COS/MOS integrated circuits
most suitable for interfacing the electronic circuit display.
ICAN-8802
Interfacing COS/MOS with
Other Logic Families .••.....••.•••.•••.••.•.•.•...••..•.. 12
This Note describes the conditions governing the interface of
COS/MOS logiC circuits with other logic families.
ICAN-8811
Keyboard Scan Routln. for U.e with ths
RCA COSMAC Mlcrotermlnal CDP1SS021 •..•..•••.• ; ..•.•• 4
This Note contains the code for such a keyboard reading
routine which can be added as a subroutine to the user
program, thereby making the Mlcrotermlnal useful as a
general-purpose Input as well as output device.
ICAN-8832
U.e of the CDP1854 UART with RCA Mlcroproce••or
Evaluation Kit CDP18S020 or EKIAI..mbler-Edltor
Dellgn Kit CDP18S024· ........... . . . .. . . . . • . .. . .. . • .. • • •• 6
This application note describes several methods of InterfaCing
the COP1854 with the CDP1602 microprocessor and specifically explains the use of the COP1854 in the COP18S020and
CDP18S024 kits.
ICAN-8835
Use of CMOS ROMs CDP1S33 and CDP1834 with the
RCA MlcroproceHor Evaluation Kit CDP1SS020
and the EKlAHembler-Edltor De.lgn Kit CDP18S024· •••.•.. 4
The CDP18S020 Evaluation Kit and the COP18S024 EK/Assembler-Editor Design Kit are designed to accept the CDP1833
and CDP1834 as described in this application note.
ICAN-8857
U.. of the CDP1858 and CDP1857 Bulfer/Seperetor In
CDP1802 Microprocessor System. . • . .. . .. . . . . • .. • .. • .. • ... 4
This Note describes the uses of the CDP1856 and COP1857
and, more specifically, how they may be utilized in the RCA
Evaluation Kit, CDP18S020, and the EKlAssembler-Editor
Design Kit, CDP18S024.
ICAN-8893
CDP1802-Ba.ed Design. Using the 8253 Programmable
Countertnmer. . .. .. • • .. • • . • . . . • .. • .. .. • . • .. . .. .. • .. .. . • .. 4
The 8253 programmable interval timer, manufactured by Intel
Corp., is an integrated circuit containing three independent
111-bit counters, each prog rammable in any of six modes. This
Note describes methods by which it can be Incorporated In
RCA COSMAC-based microprocessor systems.
ICAN-8704
Optimizing Hardware/Soltwa,. Trade-oils In
RCA CDP1802 MlcroproceHor Applications .••..•.••...••. 12
This Note will develop some examples of processor interfaces
that not only minimize external hardware but, through Judicious
programming techniques, also minimize speed requirements
on the CPU.
ICAN-8834
MlcroproceHor Control for Color-TV Receive... . . • . . • • • • • .. 12
This Note describes a microprocessor control for a color-TV
receiver, a control that supports a large number of features
a nd options.
ICAN-8842
18-Blt Operation. In the CDP1802 MlcroproceHor ..•..•••.. 6
This paper describes various software routines and a few
interface cirCUits that can be used to manipulate full 111-bit
values in the CDP1602.
ICAN-8847
Programming 2732 PROMs with the CDP18S480
PROM Programmer ....................................... 4
This Note describes the techniques utilizing the PROM
Programmer to program Intel 2732 PROMs.
ICAN-88S3
Simplified De.lgn of Altable RC Osclllato... Using the
CD4080B or Two CMOS Inverte... . . . . . • . . .. • . .. . . .. . • . .. ... 2
Application notes are available that deal with theoretical
approaches to oscillator design; this Note stresses practical
aspects of design and provides easy-to-use algebraic equations that permit values of Rand C for a given oscillator
frequency to be quickly determined.
'Note: The information in this Application Note Is useful here; the
Evaluation Kit, however, is no longer available.
556
...
Supplementary Information
Application Notes - Abstracts (Cont'd)
ICAN-8889
Using Slower Memorle. with Ihe VIS DI.play System .. . . . . .. 4
The scheme described in this Note, while requiring a few more
parts, very nearly doubles the memory access-time requirement of the system and permits the use of memories
approximately half as fast as those normally required with the
VIS system.
ICAN-8901
CDP1802 Mlcroproces.or-Ba.ed Setback Thermostat ...... , 8
This Note describes an inexpensive, programmable, setback
thermostat circuit, based on the RCA CDP1802 microprocessor
that can be used to control both heating and air-conditioning
systems.
ICAN-8918
A Methodology for Programming COSMAC 1802
Applications Ullng Higher-Level Language•.•.............. 4
This Note defines a method of optimizing the time-critical
portions of programs written in higher-level languages for
COSMAC 1802 applications by recording those portions in
assembly language.
ICAN-8925
Understanding and Using the CDP18U42 EPROM .......... , 8
This Note describes the design and programming characteristics of the RCA CDP18U42 nonvolatile ultraviolet-erasable
/programmable read-only memory.
ICAN-8928
Inlerfaclng PLM Code to COOS System Function. .......... 6
This application note defines a method for interfacing PLM
programs 10 COOS system functions without the need for
as,sembly language; the interface is an array of PLM procedures
(which can be included in a PLM library) and supportive
macro definitions, all of which are described In detail and used
in a sample program.
ICAN-8934
Cas.."e Tapa I/O for COS MAC Mlcroproce..or System •... 12
This Note describes a circuit and the software needed to add a
low-cost cassette-tape input and output to the COSMAC
Evaluation Kit (CDPI88020, CDPI88024, and CDP188025),
the COS MAC Developmental System (CDP18S005 and CDP188007), or the Microboard Prototyping Kit (CDP188691).
ICAN-8943
De.lgnlng Minimum/Nonvolatile Memory Systema with
CMOS Slatlc RAMs ...................................... 28
This Note details the system considerations and circuit
requirements for CDP1800-series RAM operation and data
retention in CDP1802-based systems.
ICAN-8948
Parallel Clocking of Sequential CMOS Devices ............•. 2
This Note shows the equations for modeling the maximum
permitted clock input rise time, tRCL for sequential devices.
ICAN-6953
An Introduction to the Video Interface System (VIS)
Devlcea-CDP1889 and CDP1870 ...... '" ................ 12
This Note describes a circuit and the software required to
mate the RCA-CDP1869 and CDP1870 VIS (Video Interface
System) chip set to the Evaluation Kit, CDP18S020.
ICAN-69SS
Using !he COSMAC Mlcroboard Baltery-Backup RAM,
CDP18S822 ...................................... '" ..•... 6
This Note discusses the application olthe board as a standard
power backup medium, a nonvolatile transport medium, and
as an efficient means of aiding the testing of new or prototype
boards.
ICAN-8957
CDP1804 and CDP1805 Proce.lorslmprove Syslem
Performance and Lower Chip Count ........................ 6
This Note describes the CDPl804 and CDP1805 enhancement
to the capability of the CDPl802 microprocessor, both in
higher performance and additional system functions, while
maintaining upward software and hardware capability.
ICAN-6988
New CMOS CDP1800-Serle. ProCillOrs Reduce
Chip Count.. . . . . . . . . • .. .. . . .. . .. • . • .. • .. . . . .. • . • • .. .. . . •. 4
This Note describes the CDP1804 and CDP1805 devices
having combined CPU, memory, and peripheral functions on
a single chip, and provide a compact system design with the
additional portability offered by battery-operation.
ICAN-6970
Understanding and U.lng the CDP1855
Multiply/Divide Unit ••• '" .••... " ...•......•.•.••.....•.. 12
This Note describes the CDP1855 MDU as an efficient hardware
replacement for the software-only implementation of arithmetic and Signal-processing algorithms.
ICAN-6971
New CMOS CDP1800-Serle. Proce..ors Enhance
System Performance ... . . .. .. . . . .. . . . . . .. . .. . . .. .. . . . . . ... 6
This Note is devoted .to a discussion of the attributes 01 the
CDP1804 and CDP1805, both 01 which are hardware and
software upward-compatible with the CDP1802.
ICAN-8991
A Slave CDP1802 Serial Printer Buffer System ••....•....•.• 8
This Note describes a CDP1802-based stand-alone line printer
buffer that links a master processor syatem to a serial printer
through an RS232C Interface.
ICAN-7009
New CDP1805 Mlcroproce••or Upgrade.
CDP18OD-Based Sy.tem•.......•..•..•......•.•..•.•....•• 8
This Note describes specific CDP1805 features and explains
how they are optimally al?plied in microcomputer systems.
ICAN-7020
Multlmlcroproce••or-baHd Tranal.tor Teat Equipment. . . • .. 8
This Note discusses a modern test system that meets these
demands through its ability to perform multiple-temperature
testing of traditional and custom parameters In one Insertion.
ICAN-7023
CDP1800-Serle. Peripheral. - Building Blocke of a
Complete Proce••or Family ............................... , 8
This Note discusses the host of peripheral chips available
from RCA that meke available to the system designer the
functions, flexibility, and performance levels that once were
only achieved with NMOS.
ICAN-7028
Mlcrob08rd Equipment Control .......................... " 6
This Note discusses the project to build a piece of equipment
to demonstrate the use of RCA Mlcroboards in specialized
manufacturing-test equipment. The specific example selected
was the testing of some active parameters of power transistors.
ICAN-7029
Low-Power Technique. for U.e with
CMOS CDP1800-Based Sy.tem•...••...•..••.......•.••.•• 6
This Note describes various techniques for reducing the
power requirements of microcomputer systems since battery
life is so Important In most portable applications and In
systems having RAM battery-back-up provision.
ICAN-7032
CDP1800-Based Video Terminal Using the
RCA Video Interface Sy.tem, ViS ......................... 36
This Note discusses the RCA Video Interface System, VIS.
chip set CDP1869, CDP1870, and CDP1876 for use in video
terminals, industrial displays, and broadcast-TV text overlays.
ICAN-7038
A CDP1800-Based CRT Controller ......................... 8
This Note discusses the addition of the Video Interface
System, VIS, to the peripheral support line for the CDP1800series microprocessors.
ICAN.;"/lIft
Understanding the CDP1851 ProgrammableI/O ............• 6
This Note discusses the general-purpose programmable I/O
port, CDP1851, having 20 I/O pins which may be used In
several different modes of operation.
ICAN-7067
VIS - A Commercially Compatltlve CRT Controller
ChlpSel. ................................................. 4
This Note discusses the VIS as an economical solution to a
variety of CRT display applications.
557
I
RCA CMOS LSI Products
Supplementary Information
Related Technical Publications
Mlcrosystem ,.nd Mlcroboard Product Description.
M8-801
M8-802
M8-803
M8-8048
M8-820
M8-821
M8-822
M8-823
M8-823A
M8-824
M8-825
M8-821
M8-827
M8-829
M8-840
M8-840V1
M8-841
M8-842
M8-843
M8-844
M8-847
M8-848
M8-859
M8-81O
M8-811
M8-8118
M8-870
M8-875
M8-891
M8-892
MPM-9208
POI
P07
P08
P010
P012
P013
P014
P011C
PD178
P018C
P019
P020
PI)228
P024
P030
P031
P034
P037A
P039
P040
P044
Mlcroboard Computer. COP18S601
Microboard Computer. COP18S602
Microboard Computer. COP18S603
Microboard Computer. COP18S804B
Microboard 4-Kllobyte RAM. COP18S820
Mlcroboard 18-Kilobyte RAM. COP18S621
Mlcroboard 8-Kilobyte Battery-Backup RAM. COP18S822
Microlloard 8-Kilobyte RAM. COP18S823
Microboard 8-Kilobyte RAM CDP18S623A
Mlcroboard 4-Kilobyte Battery-Backup RAM. COP18S824
Mlcroboard 8/18/32-Kllobyte ROM/PROM. COP18S825
Microboard 32/84-Kilobyte EPROM/ROM/RAM
Mlcroboard 4-Kllobyte CMOS EPROM COP189827
Mlcroboard 32-Kilobyte RAM
Mlcroboard Control and Display Module. COP18S840
Microboard Control and Display Module. COP18S84OV1
Microboard UART Interlace. COP18S841
Microboard O/A Converter. COP18S842
Microboard A/O Converter. COP18S843
Mlcroboard AID and O/A Converters. COP189844 and COP18S8S4
Mlcroboard O/A Converters. COP18S847 and COP18S857
Mlcroboard A/O Converters. COP18S848 and COP18S858
Microboard Breadboard. COP18S859
Mlcroboard Combination Memory and I/O Module. COP18S860
Mlcroboard Vldeo-Audlo-Keyboard Interlace. COP18S881V1 and COP18S881V3
Mlcroboard Video/Audio/Keyboard Interlace COP18S881B
Mlcroboard 22-Card Chassis with Integral Power Supply COP18S870
Mlcroboad S-Card Chassis. COP18S875 and COP18S878 (with case)
Mlcroboard Prototyplng System. COP18S891 and COP188881V3
Mlcroboard Prototyplng System. COP18S892
CDP1802 Microprocessor Instruction Summary
Fixed-Point Arithmetic Subroutine
Floating-Point Arithmetic Subroutine
COSMAC Development System IV CDP18S008
COS MAC Dictionary
COSMAC Mlcrotermlnal
Mlcroboard Computer Development Systems (MCOS) COP188883 and COP18S894
Color Mlcroboard Computer Development System COP18S885
COSMAC Development Systems
COS MAC Floppy Disk System II
COSMAC Mlcromonltor
COS MAC UART Interlace Module
COS MAC Byte 1/0 Module
PROM Programmer
EK/Assembler-Editor
ROM Purchase Policy and Programming InstructiOns
Mlcromonltor Operating System (MOPS)
BASIC1 Complier/Interpreter (COP18S834)
Disk Operating System Upgrade Package (COP18S837)
PLM 1800 High-Level-language Compiler (COP18S839)
BASIC2 High-Level-Language Interpreter COP18S84()
Micro Concurrent PASCAL Cross-Complier COP18S844 and
Interpreter/Kernel COP18S852 and COP18S853
Product Guide.
CM8-2508
MPG-1100
MPL-200
COSMAC Microboard Computer Systems
COSMAC Microprocessor Product Guide
Mlcrosystems Product Guide and Price List
DATABOOKS
SSO-270
SSO-21O
SSO-23OA
558
Microsystems
LSI Products - Applications
High-Reliability IC Products
RCA Sales Offices,
Authorized Distributors and
Manufacturers' Representatives
559
RCA CMOS LSI Products
RCA Sales Offices
Argentina
Belgium
Brazil
Canada
France
Ramiro E. Podetti Reps.
P.O. Box 4622
Buenos Aires 1000
Tel: 393·4029
RCAS.A.
Mercure Centre, Rue de Ia
Fusee 100, 1130 Bruxelles
Tel: 02/720.89.80
RCA Solid State Limitada
Av. Brig Faria Lima 1476
7th Floor, Sao Paulo 01452
Tel: 210-4033
RCA Inc.
6303 30th Street, SE
Calgary, Alberta T2C I R4
Tel: (403) 279·3384
RCA Inc.
21001 No. Service Road,
Trans Canada Highway,
S!. Anne·d.,.Bellevue,
Quebec H9X 3L3
Tel: (514) 457·2185
RCA Inc.
I Vulcan Street, Rexdak,
Ontario M9W I L3
Tel: (416) 247·5491
RCAS.A.
24 Avenue de L'Europe
78140 Velizy
U.S.
Tel: (3) 946.56.56
Hong Kong
Italy
Mexico
Singapore
Sweden
Taiwan
U.K.
RCA International Ltd.
P.O. Box 112, Hong Kong
Tel: 852·5·234·181
RCA SpA
Piazza San Marco I
20121 Milano
Tel: (02) 65.97.048·051
RCA S.A. de C.V.I
Solid State Div., Avenida
Cuitlahuac 2519. Apartado
Postal 17·570, Mexico 16, D.F.
Tel: (905) 399·7228
RCA Corporation
Solid State Division, 2315 Inter·
national Plaza, 10 Anson Road.
Singapore 0207
Tel: 2224156/2224157
RCA International LTD
Box 304~, Hagalundsgatan 8
171 03 So Ina 3
Tel: 08/83 42 25
RCA Corporation
Solid State Division,
7th Floor, 97
Nanking East Road, Section 2
Taipei
Tel: (02) 5~1.1971
RCA LTD
Lincoln Way, Windmill Road
Sunbury·on·Thames
Middlesex TWI6 7HW
Tel: 093 27 85511 .
Alabama
RCA
Suite 133
303 Williams Avenue,
Huntsville, AL 3580 I
Tel: (205) 533·5200
Arizona
RCA
6900 E. Camelback Road, Suite
460, Scottsdale, AZ 85251
Tel: (602) 947·7235
California
RCA
4546 EI Camino Real,
Los Altos, CA 94022
Tel: (415) 948-8996
RCA
4827 No. Sepulveda Blvd., Suite
420, S'herman Oaks, CA 91403
Tel: (213) 468·4200
RCA
17731 Irvine Blvd., Suite 104
Magnolia Plaza Bldg., Tustin, CA
92680
Tel: (714) 832·5302
Colorado
RCA Corp.
6767 So. Spruce Street
Englewood, CO 80112
Tel: (303) 740·8441
Florida
RCA
P.O. Box 12247, Lake Park, FL
33403
Tel: (305) 626·6350
Illinois
RCA
2700 River Road, Des Plaines
IL 60018
Tel: (312) 391·4380
Indiana
RCA
4410 Executive Blvd., Suite 13A
Fort Wayne, IN 46808
Tel: (219) 436·4383
RCA
9240 N. Meridian Street, Suite
102, Indianapolis, IN 46260
Tel: (317) 267·6375
Kansas
West Germany
RCA
8900 Indian Creek Parkway,
Suite 410.
Overland Park, KS 66210
Tel: (913) 642·7656
Massachusetts
RCA
20 William Street, Wellesley,
MA02181
Tel: (617) 237·7970
.Michigan
RCA
30400 Telegraph Road, Suite
440, Birmingham, MI 48010
Tel: (313) 644-1151
Minnesota
RCA
6750 France Avenue, So., Suite
122, Minneapolis, MN 55435
Tel: (612) 929-0676
New Jersey
RCA
1998 Springdale Road,
Cherry Hill, NJ 08003
Tel: (609) 338·5042
RCA
67 Walnut Avenue, Clark, NJ
07066
Tel: (201) 574·3550
New York
RCA
160 Perinton Hill Office Parle
Fairport, NY 14450
Tel: (716) 223·5240
Ohio
RCA
6600 Busch Blvd.,Suite 110,
Columbus, OH 43229
Tel: (614) 436·0036
Tennessee
RCA
1111 Northshore Drive,
Suite 405, Northshore Center 2,
Knoxville, TN 37919
Tel: (615) 588·2467
Texas
RCA Center
4230 LBJ at Midway Road
Town No. Plaza, Suite 121
Dalias, TX 75234
Tel: (214) 661·3515
Virginia
RCA
1901 N. Moore Street
Arlington, VA 22209
,Tel: (703) 558·4161
RCA GmbH
Pfingstrosenstrasse 29,
8000 Munchen 70
Tel: 089/7143047·49
RCA GmbH
Justus-von-Liebig-Ring lO
2085 Quickborn
Tel: 04106/613·0
RCA GmbH
Zeppelinstrasse 35,
7302 Ostfildern 4 (Kemnat)
Tel: 0711/454001·04
'560
.
RCA Sales Offlces/Olstributors/Mfrs. Reps.
RCA Authorized Distributors
Argentina
Australia
Austria
Bahamas
Belgium
Bermuda
Brazil
Canada
Eneka S.A.I.C.F.I.
Tucuman 299.
1049 Buenos Aires
Tel: 31-3363
Radlocom S.A:.
Conesa 1003.
1426 Buenos Aires
Tel: 551-2780
Tecnos S.R.L.
Independencia 1861
1225 Buenos Aires
Tel: 37-0239
Galli Hnos, S.A.C.I. e Inm.
Entre Rios 628
Buenos Aires
L.A.D.E., S.R.L.
Sequrola 1879
Buenos Aires 1407
A W A Microelectronics
348 Victoria Road
Rydalmere N.S. W. 2116
Amtron Tyree
176 Botany Street, Waterloo,
N.S.W.2017
Bacher Elektronlsche Gerate
GmbH
Rotenmuhlgasse 26,
A-1120 Vienna
Tel: 0222/8356460
Home Furniture
Company Ltda.
P.O. Box 331, Nassau
Inelco Belgium S.A.
Avenue des Croix de Guerre 94
1120 Bruxelles
Tel: 02/216.01.60
DeFontes TV Centre
Steed Building
Parliament Street
Hamilton
Tel: (809) 2-0050
Commercial Bezerra Ltda.
Rua Costa Azevedo, 139,
CEP-69.000 Manaus/ AM
Tel: (092) 232-5363
Organizacao Distribuldora E
Representacoes Ltda.
Chile
Rua Vigario Tenorio,
10S-Conj. 102/402,
CEP-50.000 Recife! PE
Tel: (081) 224-2229
Panamericana Comercial
Importadora Ltda.
Rua Aurora, 263,
01209, Sao Paulo, SP
Tel: (011) 222-3211
Saturno Brasileiro
Importacao Exportacao
Ltda.
Rua Sacadura Cabral, 120,
Sala 509, CEP-20.081
Colombia
Rio de Janeiro! RJ
Tel: (021) 243-4744·
Cesco Electronics, Ltd.
4050 Jean Talon Street, West
Montreal, Quebec H4P IWI
Tel: (514) 735-5511
Cesco Electronics, Ltd.
909 Blvd., Charest Quest
Quebec City,
Quebec GIK 6W8
Tel: (418) 524-4641
Electro Sonic, Inc.
1100 Gordon Baker Road
Willowdale, Ontario M2H 3B3
Tel: (416) 494-1666
Hamilton Avnet (Canada) Ltd.
210 Colonnade Street
Nepean, Ontario K2E 7L5
Tel: (613) 226-1700
Hamilton Avnet Elec.
2816 21st St. N.E., Calgary
Alberta, T2E 6Z2
Tel: (403) 230-3586
Hamilton Avnet (Canada) Ltd.
6845 Rexwood Drive
Units 3,4,5
Mississauga. Ontario L4V I M5
Tel: (416) 677-7432
Hamilton Avnet (Canada) Ltd.
2670 Sabourin Street, St.
Laurent, Quebec H4S 1M2
Tel: (514) 331-6443
L. A. Varah, Ltd.
1832 King Edward Street
Winnipeg, Manitoba R2R ONI
Tel: (104) 633-6190
L. A. Varah, Ltd.
2077 Alberta Street,
Vancouver, B.C. V5Y IC4
Tel: (604) 873-3211
L. A. Varah, Ltd.
4742 14th Street, NE Calgary,
Alberta T2E 6L7
Tel: (403) 276-8818
L. A. Varah, Ltd.
505 Kenara Avenue, Hamilton,
Ontario L8E 3 P2
Tel: (416) 561-9311
R.A.E. Industrial Electronics,
Ltd.
3455 Gardner Court, Burnaby,
B.C. V5G 417
Tel: (604) 291-8866
Rayle:< Ltd ••
Av Providenci. 1244
Depto.D, 3er, Piso
Casilla 13373, Santiago
Tel: 749835
Amplitel Ltd •.
Pedro Leon Ugalde 1464
Santiago
Tel: (2) 568074
Industria de Radio y
Television S.A. (IRT)
Vic. MacKenna 3333
Casilla I 70-0, Sa n!iago
Tel: 561667
Miguel Antonio Pen. Pena
Y Cia. S. En C.
Carrera 12 #1906
Bogota
Costa Rica
Denmark
Dominican
Republic
Ecuador
Egypt
EI Salvador
Finland
France
Electronlca Moderna
Carrera 9A, NRO 19-52
Apartado Aereo 5361
Bogota,D.E.1
Jose E Marulanda Montoya
Carrera 10, NRO 15-39 Of. 701
Apartado Aereo 3697
Bogota, D.E.
Electro-Impex, S.A.
Avenida 10, Calles 10 Y 12
San Jose
Tel: 11-59-54
Gamto Tecnieo, S.A.
Av.2 Calles 4 Y 6
Apartado 10069, San Jose
Tel: 21-31-31
J. G. Valldeperas, S.A.
Calle I, Avenidas 1-3,
Apartado Postal 3923
San Jose
Tel: 31-36-14
Tage Olsen A/S
P.O. Box 225
DK - 2750 Ballerup
Tel: 01/658111
H"mberto Garcia, C. por A.
EI Conde 366
Apartado de Correos 771
Santo Domingo
Tel: 682-3645
Elecom, S.A.
Padre Solano 202-0F. 8, P.O.
Box 9611, Guayaquil
Sakrco Enterprises
P.O. Box 1133.
37 Kasr EI Nil Street, Apt. 5
Cairo
Tel: 744440
Radio Electrica, S.A.
4A Avenida Sur Nb. 228
San Salvad'or
Tel: 21-5609
Radio Parts, S.A.
2A C. O. No. 319 Postalla
Dalia, P.O. Box 1262
San Salvador
Tel: 21-3019
Telerca.OY
P.O. Box 33
SF - 04201 Kerava
Tel: 0/248.055
Almex S.A.
48, rue de I'Aubepine.
F - 92160 - Antony
Tel: (01) 666 21 1l
Radio Equipments
Antares S.A.
9, rue Ernest Cognacq,
F - 92301 - Levallois Perret
Tel: (01) 758 11 11
Tekelec Alrtronic S.A.
Cite des Bruyeres,
Rue Carle Vernet.
F - 92310 - Sevres
Tel: (01) 534.75.35
561
I
RCA CMOS LSI Products
RCA Authorized Distributors
Greece
Guatemala
Haiti
Holland
Honduras
Hong Kong
Hungary
Iceland
India
Indonesia
lsrael
Semicon Co.
Italy
104 AeoLou Str.
TT.131 Athens
Tel: 325:3626
Electronics Guatemalteca
13 Calle 5-59, Zona I
P.O. Box 514
Guatemala City
Tel: 25-649
Tele-Equipos, S.A.
lOA Calle 5-40. Zona I
Apartado Postal 1798
Guatemala City
Tel: 29-805
Societe Haitienne
D'Automobile., S.A.
P.O. Box 428.
Port-Au-Prince
Tel: 2-2347
Inelco Nederland BV
Turfstekerstraat 63,
Japan
N - 1431 GD Aalsmeer
Tel: (02977) 2 88 55
Vekano BV
Korea
Postbus 6115.
N - 5600 HC Eindhoven
Tel: (40) 81 0975
Francisco J. Yones
3A Avenida$.O. 5
San Pedro Sula,
Honduras, Central America
Tel: 52-00-10
Gibb Livingston & Co., Ltd.
Mexico
77 Leighton Road
Leighton Centre
P.O. Box 55
Chinam Associates
Suite 602-3 Ritz Building
625 Nathan Road
Kowloon
Hong Kong Electronic
Components Co.
Flat A Yun Kai Bldg. 1/ FI
466-472 Nathan Road
Kowloon
Hungagent
P.O. Box 542
H-1374 Budapest
Tel: 01/669-385
Georg Amundason
P.O. Box 69B,Reykjavik
Tel: 81180
Photophone (Comel)
179-5 Second Cross Road
Lower Palace Orchards
Bangalore 3
NVPD Soedarpo Corp.
Samudera Indonesia Building
JL Letten S. Parman KAV.
35/Slipi
Jakarta Barat
Aviv Electronics
Kehilat Venezia Street 12
69010 Tel-Aviv
Nepal
Tel: 03-494450
DEDO Elettronica SpA
Strada Statale 16 Km 403-550
64019 Tortoreto Lido (Te)
Tel: 861/78.134
Eledra 3S SpA
Via Ie Elvezia 18.
I - 20154. Milano
Tel: (02) 349751
IDAC Elettronlca SpA
Via Verona 8
1- 35010 Busa di Vigonza
Tel: (049) 72.56.99
LASI Elettronics SpA
Viale Lombardia 6,
I - 20092 Cinisello
Balsamo (MI)
Tel: (02) 61.20.441-5
Silversta. Ltd.
Via dei Gracchi 20,
1- 20146 Milano
Tel: (02) 49.96
Okura & Company Ltd_
3-6 Ginza Nichome, Chuo-Ku
Tokyo 104
Panwest Company, Ltd.
Room 312, Sam Duk Building
131, Da-Dong, Chung-Ku
Seoul, Republic of South Korea
c.P.O. Box 3358
Tong Jin Trading Co.
Room 1003, Bock-Chang Bldg.
Sokong-Dong, Chung-Ku
Seoul, Republic of Sou.a Korea
Electronic. Remberg, S.A.
deC.V.
Republica del Salvador No.
30-102, Mexico City I, D.F.
Tel: 510-47-49
Manlenimlento E Instalaclone. Internacionales, S.A.
Calle 15 No. 79, Col. San Pedro
de Los Pinos, Mexico I B, O.l'.
Tel: 516-10-74
Moxicana de Bulbos, S.A.
Michoacan No. 30
Mexico II, D.F.
Tel: 564-92-33
Sprint S.A.
San Juan de Letran #55
Pasaje Lopez
Mexico I, D.F.
Tel: 511-4292
Partes Electronicas, S.A.
Republica Del Salvador 30-501
Mexico City
Tel: (90S) 585-3640
Enrique Devesa Ramos
San Juan de Letran #55
Local E, Mexico, D.F.
Tel: 510-2536
Raylel, S.A.
Sullivan 47 Y 49
Mexico 4, D.F.
Tel: 566-67-86
Continental Commercial
Distributors
Durbar Marg
Kathmandu
Netherland
Antilles
New Zealand
Nicaragua
Norway
Panama
Paraguay
Peru
PhlUppines
Portugal
Puerto Rico
Singapore
Soutb Africa
Spain
EI Louvre, S.A.
P.O. Box 138, Curacao
Tel: 54004
AWANZLtd.
36-44 Adelaide Road
P.O. Box 830
Wellington 2
Comereial F. A. Mendieta, S.A.
Apartado Postal No. 1956
C.S.T. 5c AI Sur 2c 1/2 Abajo
Managua
National Elektro A/S
Ulvenveien 75, P.O. Box 53
Okern, Oslo 5
Tel: (472) 64 49 70
Tropeleo, S.A.
Via Espana 20-18, Panama 7
Rep. de Panama
Compania Comerda! Del
Paraguay, S.A.
Casilla de Correa 344
Chile 877, Asuncion
Arven S.A.
PSJ Adan Mejia 103, OF. 33
Lima II
Tel: 716229
DeUron S.A.
Apartado Postal 1574
Lima
PhlUpplne Electronic
Industries, Inc.
3rd Floor, Rose
Industrial Bldg., II Pioneer St.
Pasig, Metro Manila
Semltronlcs
216 Ortego Street
San Juan, Metro Manila 3134
P.O. Box 445
Telectra Sari
Rua Rodrigo da Fonseca, 103
Lisbon' I
Tel: 68.60.71-75
Kelvln.tor Sales of Puerto
Rico, Inc.
P.O. Box BG, Rio Piedras,
Puerto Rico 0092B
Edware Eu & Co., Ltd.
I Orchard Road
Singapore
Allied Electronic
Componenls (PTY) Ltd.
P.O. Box 6387
Dunswart I SOB
Tel: (011) 528-661
Kontron S.A.
Salvatierra 4,
Madrid 34
Tel: 1/729.11.55
Novolemlc
Valencia 109-111,
Barcelona II
Tel: (03) 253.20.07
562
..
RCA Sales Offices/Dlstrlbutors/Mfrs. Reps.
RCA Authorized Distributors
Sri Lanka
Surinam
Sweden
Switzerland
Taiwan
Thailand
Trinidad
Turkey
U.K.
Uruguay
Ceylon SVC & Sup. Co.
c/o P.A. Silva
P.O. Box 89
Colombo
Kirpalani's Ltd.
17-27 Maagden.treet,
U.S.
P.O. Box 251, Paramaribo
Tel: 71-400
Surinam Electronics
Keizer.treet 206
P.O. Box 412
Paramaribo
Tel: 76-555
Ferner Electronics AB
Snormakarvagen 35,
P.O. Box 125,
S-161 26 Bromma Stockholm
Tel: 08/802540
Baerlocher A G
Forrlibuckstrasse 110
8005 Zurich
Tel: (01) 42.99.00
Haw Sheng Electric Co., Ltd.
5th Floor Pong Lai Building
245 Min Chuan East Road
Taipei
Delta Engineering Ltd.
No. 42 Hsu Chang Street
8th Floor, Taipei
Anglo Thai Engineering Ltd.
2160 Klongton-Bangkapi Hwy.
Hua Mark, Bangkok
Kirpalani's Limited
Kirpalani's Komplex
Churchill Roosevelt Highway
San Juan, Port-of-Spain
Tel: 638-2224/9
Teknim Company Ltd.
Riza Sah Pehlevi Caddesi 7
Kavaklidere Ankara
Tel: 27.58.00
ACCESS Electronic Components Ltd.
Austin House, Bridge Street
Hitchin, Hertfordshire SG5 2DE
Tel: Hitchin (0462) 31 221
Crellon Electronics Ltd.
380 Bath Road, Slough,
Berks. SLI 6JE
Tel: Burnham (06286) 4434
I.T.T. Electronic Services
Edinburgh Way. Harlow
Essex. CM20 2DE
Tel: Harlow (0279) 26777
Jermyn Distribution
Vestry Industrial Estate
Sevenoaks, Kent
Tel: Sevenoaks (0732) 450144
Macro Marketing Ltd.
Burnham Lane.
Slough, Berkshire SLI 6LN
Tel: Burnham (06286) 4422
VSI Electronics (U .K.) Ltd.
Roydonbury Industrial Park
HOTsecroft Road, Harlow
Essex CMI9 5 BY
Tel: Harlow (0279) 29666
American Products S.A.
(APSA)
Av. Italia 4230
Montevideo
Tel: 594210
ALABAMA
Hamilton Avnet Electronics
4692 Commercial Drive, NW
Huntsville, AI. 35805
Tel: (205) 837-7210
ARIZONA
Hamilton A vnet Electronies
505 South Madison Drive
Tempe, AZ 85281
Tel: (602) 231-5100
Kierulff Electronics, Inc.
4134 East Wood Street
Phoenix, AZ 85040
Tel: (602) 243-4101
Kierulff Electronics, Inc.
1806 West Grant Road. Suite 102,
Tucson, AZ 85705
Tel: (602) 624-9986
Sterling Electronics, Inc.
200 I East University Drive.
Phoenix, AZ 85034
Tel: (602) 258-4531
Wyle Distribution Group
8155 North 24th Avenue
Phoenix. AZ 85021
Tel: (602) 249-2232
CALIFORNIA
Arrow Electronics, Inc.
9511 /!.idge Haven Court
San Diego. CA 92123
Tel: (7J4) 565-6928
Arrow Electronics, Inc.
52 [ Weddell Drive
Sunnyvale, CA 94086
Tel: (408) 745-6600
Arrow Electronics, Inc.
19748 Dearborn Street
North Ridge Business Center
Chatsworth, CA 91311
Tel: (213) 701-7500
A .net Electronics
350 McCormick Avenue
Costa Mesa, CA 92626
Tel: (714) 754-6051
Hamilton A.net Electronics
3170 Pullman Street
Costa Mesa. CA 92626
Tel: (714) 641-4107
Hamilton Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, CA 94086
Tel: (408) 743-3300
Hamilton Avuet Electronics
4545 Viewridge Avenue
San Diego. CA 92123
Tel: (714) 571-7510
Hamilton Electro Sale.
10912 W. Washington Blvd.
Culver City, CA 90230
Tel: (213) 558-2020
Hamilton Avnet Electronics
4103 Northgate Boulevard,
Sacramento, CA 95834
Tel: (916) 920-3150
Kierulff Electronics, Ine.
2585 Commerce Way
Los Angeles. CA 90040
Tel: (213) 725-0325
Kierulff Eleelronics, Inc.
3969 E. Bayshore Road
Palo Alto, CA 94303
,.11
(~961j.6l92
Kierulff Electronics, Inc.
8797 Balboa Avenue
San Diego, CA 92123
Tel: (714) 278-2112
Kierulff Electronics, Inc.
14101 Franklin Avenue
Tustin. CA 92680
Tel: (714) 731-5711
Schweber Electronics Corp.
178 II Gillette Avenue
Irvine, CA 92714
Tel: (714) 556-3880
Schweber Electronics Corp.
3110 Patrick Henry Drive
Santa Clara, CA 95050
Tel: (408) 748-4700
Wyle Distribution Group
124 Marvland Avenue
EI Segu';do, CA 90245
Tel: (213) 322-8100
Wyle Distribution Group
9525 Chesapeake Drive
San Diego, CA 92123
Tel: (714) 565-9171
Wyle Distribution Group
3000 Bowers Avenue
Santa Clara. CA 95052
Tel: (408) 727-2500
Wyle Distribution Group
J 7872 Cowan A venue
Irvine, CA 92714
Tel: (714) 641-1600
COLORADO
Arrow Electronics Inc.
2121 S. Hudson
Denver. CO 80222
Tel: (303) 758-2100
Kierulff Electronics, Inc.
10890 East 47th Avenue
Denver. CO 80239
Tel: (303) 371-6500
Hamilton A.net Electronics
8765 E. Orchard Road. Suite
708, Englewood, CO 80 III
Tel: (303) 740-1000
Wyle Distribution Group
451 East 124th Avenue
Thornton. CO 80241
Tel: (303) 457-9953
CONNECTICUT
Arrow Electronics, Inc.
12 Beaumont Road
Wallingford, CT 06492
Tel: (203) 265-7741
563
RCA CMOS LSI Products
RCA Authorized Distributors
U.S.
564
Hamilton Avnet Electroalcs
Commerce Drive, Commerce
Industrial Park,
Danbury, CT 06810
Tel: (203) 797·1100
Klerulff Electronics, Inc.
169 North Plains Industrial Road
Wallingford, CT 06492
Tel: (203) 165-1115
Scbweber Electronics Corp.
Finance Drive,
Commerce Industrial Park,
Danbury, CT 06810
Tel: {203) 791·3_
FLORIDA
Arrow Electronics, Inc.
1001 NW 62nd Street, Suite
108, FI. Lauderdale, FL 33309
Tel: (305) 776-7791
Arrow Electronics, Inc.
50 Woodlake Dr .• West·Bldg. B
Palm Bay, FL 32905
Tel: (305) 725-1410
Hamilton Avnet Electronics
6801 NW 15tb Way
Ft. Lauderdale, FL 33068
Tel: (305) 971·2900
Hamilton Avnet Electronics
3197 Tech Drive, No.
St. Petersburg, FL 33702
Tel: (813) 576·3930
·Klerulff Electronics, Inc.
3247 Tech Drive
St. Petersburg, FL 33702
Tel: (813) 576-1966
MlI...y E1eetronles, lnc.
1850 Lee World Center
Suite 104
Winter Park, FL 32789
Tel: (385) 647·5747
Sehweber Electronic. Corp.
2830 North 28th Terrace
Hollywood, FL 33020
Tel: (305) 917-8511
GEORGIA
Arrow Electronics, Inc.
2979 Pacific Drive
Norcross, GA 30071
Tel: (4CI4) 449-8251
Hamilton Avnet Electronics
582SD Peach Tree Comers
Norcross, GA 30071
Tel: (404) 447·7503
Sebweber Electronics Corp.
303 Research Drive
Suite 210
Norcross, GA 30092
Tel: (4CI4) 449-9170
ILLINOIS
Arrow Electronics, Inc.
2000 Algonquin Road
Schaumburg, IL 60193
Tel: (312) 893-941.
Hamilton Avnet Electronics
1130 Thorndale Avenue
Bensenvilie, IL 60166
Tel: (312) 860-77.
Klerulff Electronles, Inc.
1536 Landmeier Road
Elk Grove Village, IL 60007
Tel: (31l) 640-0100
Newark Eleetronlcs
500 North Pulaski Road
Chicago, IL 60624
Tel: (31l) 638-4411
Sebwe!Jer Eleetronles Corp.
904 Cambridge Drive
Elk Grove Village, IL 60007
Tel: (31l) 364-3751
INDIANA
Arrow Electronics, Inc.
2718 Rand Road
Indianapolis, IN 46241
Tel: (317) 243-9353
Grabam Electronics Supply, Inc.
133 S. Pennsylvania Street
Indianapolis, IN 46204
Tel: (317) 63....8202
Hamilton Avnet Electronics, Inc.
485 Gradle Drive
Carmel, IN 46032
Tel: (317) 84....9333
KANSAS
Hamilton Avnet Eleetronles
921 ~ Quivira Road
Overland Park. KS 66215
Tel: (913) 888-8900
LOUISIANA
Sterling Electronics, Inc.
3005 Harvard St., Suite 101
Metairie, LA 70002
Tel: (504) 887·7610
MARYLAND
Arrow Electronics, Inc.
480 I Benson Avenue
Baltimore, MD 21227
Tel: (301) 247·5200
Hamilton A vnet Electronics
6822 Oakhall Lane
Columbia, MD 21045
Tel: (301) 995-3500
Pyttronlc Industries, Inc.
Baltimore/Washington Ind.Pk.
8220 Wellmoor Court
Savage, MD 20863
Tel: (301) 791·0711
Sebweber Electronics Corp.
9218 Gaithers Road
Gaithersburg, MD 20877
Tel: (301) 840-5900
Zebra Electronics, Inc.
2400 York Road
Timonium, MD 21093
Tel: (301) 251-6576
MASSACHUSETTS
Anow E1eetronlcs, Inc.
Arrow Drive
Woburn, MA 01801
Tel: (617) 933-8130
Hamilton Avnet Electronics
50 Tower Office Park
Woburn, MA 01801
Tel: (617) 935·9780
Klerulff Electronla, Inc.
13 Fortune Drive
Billerica, MA 01821
Tel: (617) 667-8331
A. W. Mayer Co.
34 Linnell Circle
Billerica, MA 01821
Tel: (617) 129-2155
Scbweber Electronics Corp.
25 Wiggins Avenue
Bedford, MA 01730
. Tel: (617) 175-5100
SterUna Electronics, Inc.
411 Waverly Oaks Road
Waltbam, MA 02154
Tel: (617) 194-62.
MICHIGAN
Arrow Electronics, Inc.
3810 Varsity Drive
Ann Arbor, M148104
Tel: (313) 971·8220
Hamilton Avnet Electronics
2215 29th Strect
Grand Rapids, MI 49503
Tel: (616) 243·8805
Hamilton Avnet Electronia
32487 Schoolcraft Road
Livonia, MI48150
Tel: (313) 511-4700
Scbweber Electronics Corp.
12060 Hubbard Avenue
Livonia, MI481SO
Tel: (313) 515-1100
MINNESOTA
Arrow Electronics, Inc.
5230 West 73rd Street
Edina, MN 55435
Tel: (612) Ill-I_
Hamilton Avnet Electronics
10300 Bren Road, East
Minnetonka, MN 55343
Tel: (612) 931-0600
Klerulff Electronics, Inc.
7667 Cahill Road
Edina, MN 55435
Tel: (612) 941·7_
Sehw.ber Electronics Corp.
7422 Washington Avenue, So.
Eden Prairie, MN 55344
Tel: (611) 941·5210
MISSOURI
Arrow E1eetronlcs, Inc.
2380 Schuetz Road
St. Louis, MO 63141
Tel: (314) 567·6188
Hamilton A vnet Elcetroala
13743 Shoreline Court East
Earth City, MO 63045
Tel: (314) 344-1_
Klerulff Electronics, IDe.
2608 Metro Park Boulevard
Maryland Heights, MO 63043
Tel: (314) 739-0855
RCA Sales Offices/Distributors/Mfrs. Reps.
RCA Authorized Distributors
U.S.
NEW HAMPSHIRE
Arrow Electronics, Inc.
One Perimeter Drive
Manchester, NH 03103
Tel: (603) 668-6968
NEW JERSEY
Arrow Electronics, Inc.
Pleasant Valley Avenue
Moorestown, NJ 08057
Tel: (609) 235-1900
Arrow Electronics, Inc.
Two Industrial Road
Fairfield, NJ 07006
Tel: (201) 575-5300
Hamilton A vnet Electronics
Ten Industrial Road
Fairfield, NJ 07006
Tel: (201) 575-3390
Hamilton Avnel Electronics
One Keystone Avenue
Cherry Hill, NJ 08003
Tel: (609) 424-0110
Kierulff Electronics, Inc.
37 Kulick Road
Fairfield, NJ 07006
Tel: (201) 575-6750
Schweber Electronic. Corp.
18 Madison Road
Fairfield, NJ 07006
Tel: (201) 227-7880
NEW MEXICO
Arrow Electronics, Inc.
2460 Alamo, SE
Albuquerque, NM 87106
Tel: (50S) 243-4566
Hamilton Avnet Electronics
2524 Baylor S.E.
Albuquerque, NM 87106
Tel: (505) 765-1500
Sterling Electronics, Inc.
3540 Pan American
Freeway, N.E.
Albuquerque, NM 87107
Tel: (505) 884-1900
NEW YORK
Arrow Eleclronics, Inc.
900 Broad Hollow Road
Route 110, Farmingdale, LI,
NY 11735
Tel: (516) 694-6800
Arrow Eleclronics, Inc.
7705 Maltlage Drive
Liverpool, NY 13088
Tel: (315)652-1000
Arrow Electronics, Inc.
3000 South Winton Road
Rochester, NY 14623
Tel: (716) 275-0300
Hamilton A vnel Electronics
Five Hub Drive
Melville, NY 11746
Tel: (516) 454-6000
Hamilton Avnel Electronics
333 Metro Park
Rochester, NY 14623
Tel: (716) 475-9130
Hamilton Avnel Electronics
16 Corporate Circle
East Syracuse, NY 13057
Tel: (315) 437-2641
Milgray Electronics, Inc.
191 Hanse Avenue
Freeport, LI, NY 11520
Tel: (516) 546-6000
Schweber Electronics Corp.
Three Townline Circle
Rochester, NY 14623
Tel: (716) 424-2222
Schweber Electronics Corp.
Jericho Turnpike
Westbury, LI, NY 11590
Tel: (516) 334-7474
Summit Distributors, Inc.
916 Main Street
Buffalo, NY 14202
Tel: (716) 884-3450
NORTH CAROLINA
Arrow Electronies, Inc.
938 Burke Street,
Winston-Salem, NC 27!OI
Tel: (919) 725-8711
Hamilton Avnel Eleclronics
2803 Industrial Park
Raleigh, N C 27609
Tel: (919) 829-8030
Kierulff Electronics Inc.
1800 #E Fairfax Road
Greensboro, NC 27407
Tel: (919) 852-9440
OHIO
Arrow Eleclronics, Inc.
7620 McEwen Road
Centerville, OH 45459
Tel: (513) 435-5563
Arrow Electronics, Inc.
6238 Cochran Road
Solon, OH 44139
Tel: (216) 248-3990
Hamilton Avnet Electronics, Inc.
4588 Emery Industrial Parkway
Cleveland, 0 H 44128
Tel: (216) 831-3500
Hamilton Avnel Electronics
954 Senate Drive
Dayton, OH 45459
Tel: (513) 433-0610
Hughes-Peters, Inc.
481 East 11th Avenue
Columbus, OH 43211
Tel: (614) 294-5351
Kierulff Electronics, Inc.
23060 Miles Road
Cleveland, 0 H 44128
Tel: (216)587-6558
Schweber Electronics Corp.
23880 Commerce Park Road
Beachwood. OH 44122
Tel: (216) 464-2970
OKLAHOMA
Kierulfr Electronics, Inc.
Metro Park 12318 East 60th
Tulsa, OK 74145
Tel: (918) 252-7537
OREGON
Hamilton Avnet Electronics
6024 S.W. Jean Road,
Bldg. B-Suite J,
Lake Oswego. OR 97034
Tel: (503) 635-8157
Wyle Distribution Group
5289 N.E. Ezam Young Parkway
Hillsboro, OR 97123
Tel: (503) 640-6000
PENNSYLV ANIA
Arrow Electronics, Inc.
650 Seco Road
Monroeville, PA 15146
Tel: (412) 856-7000
Herbach & Rademan, Inc.
401 East Erie Avenue
Philadelphia, PA 19134
Tel: (215) 426-1700
Schweber ElectronIcs Corp.
231 Gibralter Road
Horsham, PA 19044
Tel: (215) 441-0600
TEXAS
Arrow Electronics, Inc.
13715 Gamma Road
Dallas, TX 75240
Tel: (214) 386-7500
Arrow Electronics, Inc.
10700 Corporate Drive 11100
Stafford, TX 77477
Tel: (713) 491-4100
Hamilton Avnet Electronics
2401 Rutland Drive
Austin, TX 78758
Tel: (512) 837-8911
Hamilton A vnel Electronics
2111 West Walnut Hill Lane
Irving, TX 75060
Tel: (214) 659-4111
Hamilton Avn~t Electronics
8750 Westpar k
Houston, TX 77063
Tel: (713) 975-3515
Kierulff Electronics, Inc.
3007 Longhorn Blvd., Suite !O5
Austin, TX 78758
Tel: (512) 835-2090
Kierulf! Eleclronics, Inc.
9610 Skillman Avenue
Dallas, TX 75243
Tel: (214) 343-2400
Kierulff Electronics, Inc.
10415 Landsbury Drive, Suite 210
Houston, TX 77099
Tel: (713) 530-7030
Schweber Electronics Corp.
4202 Beltway,
Dallas, TX 75234
Tel: (214) 661-5010
Schweber Electronics Corp.
10625 Richmond Ste. 100
Houston, TX 77042
Tel: (713) 784-3600
Sterling ElectronIcs, Inc.
2335A Kramer Lane, Suite A
Austin, TX 78758
Tel: (512) 836-1341
Sterling Electronics, Inc.
11090 Stemmons Freeway
Stemmons at Southwell
Dallas, TX 75229
Tel: (214) 243-1600
Sieriing Eleclronics, Inc.
4201 Southwest Freeway
Houston, TX 77027
Tel: (713) 627-9800
565
RCA Sales Offlces/Dlstrlbutors/Mfrs. Reps.
RCA CMOS LSI Products
RCA Authorized Distributors
u.s.
West Indies
WISCONSIN
Arrow Electronic., Inc.
430 West Rawson Avenue
Oak Creek, WI 53154
Tel: (414) 764-6600
Hamilton Avnet Electronic.
West Germany
2975 South Moorland Road
New Bertin. WI 53151
Tel: (414) 784-4510
Kierulff Electronic., Inc.
2212 East Moreland Blvd.
Waukesha, WI 53186
Tel: (414) 784-8160
Taylor Electric Company
1000 W. Donges Bay Road
Mequon, WI 53092
Tel: (414) 241-4321
Dinaradio, C.A.
Conjunto Industrial EI
Cedralito No.6
KM3, Carretera
PetarewGuarenas, Caracas
MAIL ADDRESS: Apartado Postal 60429
Chacao
Tel.-Cuba, S.A,
Av. Este 0, No. 164, Ferrenquin
a la Cruz, La Candelaria.
Caracas
Tel: 55-62-71
P. Benavides, P., S.R.L.
Residencies Camarat, Local 7
La Candelaria, Caracas
MAIL ADDRESS: Apartado Postal 20.249 Yugoslavia
San Martin, Caracas
UTAH
Hamilton A vnet Electronics
1585 West 2100 South
Salt Lake City. UT 84119
Tel: (801) 972-18"
Klerulff Eleetronlcs, Inc.
2121 S. 3600 West Street
Salt Lake City. UT 84119
Tel: (80t) 973-6913
Wyle Distribution Group
1959 South 4130 West Unit B
Salt Lake City, UT 84104
Tel: (801) 974-9953
WASHINGTON
Arrow Eleclronics, Inc.
14320 N.E. 21st Street
Bellevue, W A 98005
Tel: (206) 643-4800
Venezuela
Hamilton A vnet Electronics
14212 N.E. 21st Street
Bellevue, W A 98005
Tel: (206) 453-5874
Kierulfr Electronies, Inc.
1005 Andover Park E.
Tukwila, WA98188
Tel: (206) 575-4420
Robert E. Priebe Company
2211 5th Avenue
Seattle, W A 98121
Tel: (206) 682-8242
Wyle Distribution Group
1750 132nd Avenue, N.E.
Bellevue, W A 98005
Tel: (206) 453-8300
Da Costa and Muason Ltda.
Carlisle House
Hincks Street
P.O. Box 103
Bridgetown. Barbados
Tel: 601-50
Alfred Neye Enatechnlk GmbH
Schillerstrasse 14,
2og5 Quickborn
Tel: 04106/6121
ECS HOm.. Frehsdorf GmbH
ElectronIc Components Service
Carl-Zeiss Strasse 3
2085 Quickborn
Tel: 04106/71058-59
Beck GmbH I< Co.
Elektrolllk Bauelemente KG
Eltersdorfer Strasse 7,
8500 Nurnberg 15
Tel: 0911/34961-66
Elkose GmbH
Bahnhofstrasse 44,
7141 Moglingen
Tel: 87141/4171
SaseoGmbH
Hermann-Oberth-Strasse 16
8011 Putzbrunn bei Munchen
Tel: 089/"111
Spoerl. Electronic KG
Max-Planck Strasse 1-3,
6072 Dreieich bei Frankfurt
Tel: 06103/3041
Avtotehna
P.O. Box 593, Celovska 175
Ljubljana 61000
Tel: 552341
RCA Manufacturers' Representatives
U.S.
Arizona
California
Florida
566
Thom Luke Sales, Inc.
2940 North 67th Place
Suite H
Scottsdale, AZ 85251
Tel: (602) 941-1901
ell. K Assocs.
8333 Clairemont Mesa Blvd.
Suite 105
San Diego. CA 92111
Tel: (714) 279-0420
Bohman Assocs., Inc.
130 North Park Avenue
Apopka, FL 32703
Tel: (305) 886-1882
Massachusetts
New York
Ohio
New England Tecbnlcal Sales
Corp.
135 Cambridge Street
Burlington, MA 01803
Tel: (617) 272-0434
Astrorep, Inc.
300 Sunrise Highway
Suite 2B
West Babylon, NY 11704
Tel: (516) 422-2500
Lyons Corp.
4812 Frederick Road
Suite 101
Dayton. OH 45414
Tel: (513) 278-0714
Soulb CaroHna eSR Electronics
III Greenhouse Court
Columbia, SC 29210
Tel: (404) 396-3720
Southern States Marketlnc, Ine.
Tex.s
16910 Dallas Parkway
Suite 222
Dallas, TX 75248
Tel: (214) 387-1489
Wa.hlngton
Western Technical Sales, Inc.
P.O. Box 3923
Bellevue, W A 98009
Tel: (206) 641-3900
· . State
Solid
RGII
DATABOOK Series-SSD-260A
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