1982_SGS_Linear_Integrated_Circuits_3ed 1982 SGS Linear Integrated Circuits 3ed
User Manual: 1982_SGS_Linear_Integrated_Circuits_3ed
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criterion
(40B) 9BB-6300
manufacturers representatives
3350 Scott Blvd .. Bldg. 44. Santa Clara . CA 95051
ISSUED JUNE 1982
INTRODUCTION
This databook contains data sheets on the SGS-ATES range of linear integrated circuits for professional,
industrial and consumer applications.
Selection guides are provided in the following pages to facilitate rapid identification of the most suitable
device for the intended use.
The information on each product has been specially presented in order that the performance of the
product can be readily evaluated within any required equipment design.
SGS·ATES GROUP OF COMPANIES
INTERNATIONAL HEADQUARTERS
SGS-ATES Componenti Elettronici SpA
Via C. Olivetti 2 - 20041 Agrate Brianza - Italy
Tel.: 039 - 65551
Telex: 330131-330141
BENELUX
SGS-ATES Componenti Elettronici SpA
Benelux Sales Office
8- 1180 Bruxelles
Winston Churchill Avenue, 122
ITALY
SGS-ATES Componenti Elettronici SpA
Direzione Commerdale Italia
20149 Milano
Via Correggio, 1/3
Tel.: 02 - 4695651
Sales Office:
00199 Roma
Piazza Gondar, 11
Tel.: 06 - 8392848/8312777
Tel.: 02 - 3432439
Telex: 24149 B
DENMARK
SGS-ATES Scandinavia AB
Sales Office
2730 Herlev
Herlex Torv, 4
SINGAPORE
SGS-ATES Singapore (Pte) Ltd.
Singapore 1231
Lorang 4 & 6 - T oa Payoh
Tel.: 2531411
Telex: ESGIES RS 21412
Tel.: 02 - 948533
Telex: 35411
EASTERN EUROPE
SGS-ATES Componenti Elettronici SpA
Export Sales Office
.
20041 Agrate Brianza - Italy
Via C. Olivetti, 2
Tel.: 039 - 6555287/6555207
Telex: 330131-330141
FINLAND
SGS-ATES Scandinavia AB
Sales Office
02210 Esbo 21
Kaantopiiri,2
Tel.: 90 - 881395/6
Telex: 123643
FRANCE
SGS-ATES France S.A.
15643 Paris Cedex 13
Residence "Le Palatino"
17, Avenue de Choisy
Tel.: 01 - 5842730
Telex: 042 - 250938
WEST GERMANY
SGS-ATES Deutschland Halbleiter
Bauelemente GmbH
8018 Grafing bei Miinchen
Haidling, 17
Tel.: 08092··691
Telex: 0527378
SWEDEN
SGS-ATES Scandinavia AB
19501 Miirsta
Box 144
Tel.: 0760 - 40120
Telex: 042 - 10932
SWITZERLAND
SGS-ATES Componenti Elettronici SpA
Swiss Sales Offices
6340 Baar
Oberneuhofstrasse, 2
Tel.: 042 - 315955
Telex: 864915
1218 Grand-Saconnex (Geneve)
~~le~~;f~a~~~~6~/;mann 22
Telex: 28895
UNITED KINGDOM
SGS-ATES (United Kindgom) Ltd.
Aylesbury, Bucks
Planar House, Walton Street
Tel.: 0296 - 5977
Telex: 041 - 83245
Sales Offices:
3012 langenhagen
Hubertusstrasse, 7
Tel.: 0511 -772075/7
Telex: 0923195
8000 Munchen 90
Tegernseer LandstL, 146
Tel.: 089 - 6925100
Telex: 05215784
8500 Niirnberg 30
Ostendstr.,204
Tel.,0911-572977/78/79
Telex: 0626243
7000 Stuttgart 80
Kalifenweg,45
Tel.: 0711 - 713091/2
Telex: 07 255545
HONG KONG
SGS-ATES Singapore (Pte) Ltd.
9th Floor, Block N,
Kaiser Estate, Phase 1: t,
11 Hok Yuen St.,
Hung Hom, Kowloon
Tel.: 3-644251/5
Telex: 63906 ESGIE HX
U.S.A.
SGS-ATES Seminconductor Corporation
Scottsdale, AZ 85251
7117, East 3rd Avenue
Tel.: (602) 990-9553
Telex: SGS ATES SCOT 165808
Waltham, MA 02154
240, Bear Hill Road
Tel.: (617) 890-6688
Telex: 923495 WHA
Des Plaines, I L 60018
2340, Des Plaines Ave Suite 309
Tel.: (312) 296-4035
Telex: 282547
Santa Clara, CA 95051
2700, Augustine Drive
Tel.: (408) 727-3404
Telex: 346402
Woodland Hills, CA 91367
6355, Topange Canyon Boulevard
Suite 220
Tel.: (213) 716-6600
Telex: 182863
2
TABLE OF CONTENTS
I~
I,
'I'
"
ALPHANUMERICAL INDEX
Page
APPLICATION GUIDE
4
9
HANDLING OF POWER ICs
15
RELIABILITY (SURE III)
19
DATA SHEETS
33
3
ALPHANUMERICAL INDEX
Type
L120A
L 121A
L123
L146
L149
L165
L194-5
L194-12
L194-15
L200
L201
L202
L203
L204
L290
L291
L292
L293
L293E
L294
L487
L601
L602
L603
L604
L702
L2605
L2685
L2610
L3654
L7805
L7806
L7808
L7812
L7815
L7818
L7820
L7824
L78M05
L78M06
L78M08
L78M12
L78M15
L78M18
L78M20
L78M24
Function
Page
TRIAC/SCR phase control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
34
TRIAC/SCRburstcontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
High precision voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
49
High precision, high voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
57
68
High gain power output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3A-Power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
5V-Positive voltage regulator with rectifying bridge . . . . . . . . . . . . . . . . . . .
79
12V-Positive voltage regulator with rectifying bridge. . . . . . . . . . . . . . . . . ..
79
15V-Positive voltage regulator with rectifying bridge. . . . . . . . . . . . . . . . . ..
79
Adjustable voltage and current regulator . . . . . . . . . . . . . . . . . . . . . . . . . ..
83
High voltage, high current 7 darlington arrays. . . . . . . . . . . . . . . . . . . . . . ..
93
High voltage, high current 7 darlington arrays . . . . . . . . . . . . . . . . . . . . . . .
93
High voltage, high current 7 darlington arrays . . . . . . . . . . . . . . . . . . . . . . .
93
High voltage, high current 7 darlington arrays . . . . . . . . . . . . . . . . . . . . . . .
93
Tachometer converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
98
5 bit D/A converter and position amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 104
Switch-mode driver for DC motors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Push-pull four channel driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 122
Push-pull four channel driver .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 122
Switch-mode solenoid driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Low dropout 5V ,egulator with reset . . . . . • . . . . . . . . . . . . . . . . . . . . . .. 136
High voltage, high current 8 darlington arrays . . . . . . . . . . . . . . . . . . . . . . . 139
High voltage, high current 8 darlington arrays . . . . . . . . . . . . . . . . . . . . . . . 139
High voltage, high current 8 darlington arrays . . . . . . . . . . . . . . . . . . . . . . . 139
High voltage, high current 8 darlington arrays . . . . . . . . . . . . . . . . . . . . . . . 139
Quad darlington switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 142
5V-Positive voltage regulator for automotive. . . . . . . . . . . . . . . . . . . . . . .. 146
8.5V-Positive voltage regulator for automotive. . . . . . . . . . . . . . . . . . . . . .. 146
10V-Positive voltage regulator for automotive. . . . . . . . . . . . . . . . . . . . . .. 146
Printer solenoid driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 148
Positive voltage regulator (lA-5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (lA-6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (lA-8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (lA-12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (1 A-15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (1 A-18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (1 A-20V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (lA-24V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 153
Positive voltage regulator (0.5A-5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Positive voltage regulator (0.5A-6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Positive voltage regulator (0.5A-8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Positive voltage regulator (0.5A-12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 165
Positive voltage regulator (0.5A-15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Positive voltage regulator (0.5A-18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 165
Positive voltage regulator (0.5A-20V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 165
Positive voltage regulator (0.5A-24V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 165
4
11
IlIiI
14
~
I~
ALPHANUME.RICAL INDEX (continued)
I',!
Type
L78S05
L78S75
L78S09
L78S10
L78S12
L78S15
L78S18
L78S24
L7905
L7952
L7908
L7912
L7915
L7918
L7920
L7924
LMl17
LM217
LM317
LM324
LM324A
LM339
LM339A
LM2902
LS025
LS045
LS10l
LS107
LS141
LS141A
LS141C
LS148
LS148A
LS148C
LS150
LS156
LS159
LS201
LS204
LS204A
LS204C
LS207
LS285
LS285A
LS288
LS301
Function
Positive voltage regulator (1.5A-5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-7.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-9V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-l OV) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive voltage regulator (1.5A-24V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-5.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (1 A-15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-20V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative voltage regulator (lA-24V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2V to 37V adjustable regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2V to 37V adjustable regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2V to 37V adjustable regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low power quad operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low power quad operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad voltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad voltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low power quad operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balanced modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High performance operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . .
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . .
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . .
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . .
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High performance 80 dB compandor . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High reliability transistor array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High performance operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
High performance dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . .
High performance dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . .
High performance dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . .
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . .
Telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .
High performance operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Page
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.
.
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.
.
.
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.
175
175
175
175
175
175
175
175
187
187
187
187
187
187
187
187
192
192
192
198
198
205
205
198
211
218
222
231
236
236
236
243
243
243
251
259
271
222
276
276
276
231
284
284
292
222
i
'.
ALPHANUMERICAL INDEX (continued)
Type
LS307
LS342
LS356
LS404
LS404C
LS656
LS709
LS709A
LS709C
LS776
LS776C
LS4558N
MC1458
MC1458C
TAA550
TAA611A
TAA611B
TAA611C
TBA231A
TBA331
TBA800
TBA810CB
TBA810P
TBA810S
TBA820
TBA820M
TCA830S
TCA900
TCA910
TCA940N
TCA 3089
TCA 3189
TDA 4405
TDA1054M
TDA1151
TDA1170
TDA1170D
TDA1170N
TDA1170S
TDA 1180P
TDA1190Z
TDA1200
TDA1220A
TDA1220B
TDA1220L
TDA1410A
Function
Page
Frequency compensated operational amplifier . . . . . . . . . . . . . . . . . . . . . "
Multifrequency to telephone line interface circuit. . . . . . . . . . . . . . . . . . . ..
Telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High performance quad operational amplifier . . . . . . . . . . . . . . . . . . . . . . "
High performance quad operational amplifier. . . . . . . . . . . . . . . . . . . . . . ..
Telephone speech circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmable operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
Dual high performance operational amplifier . . . . . . . . . . . . . . . . . . . . . . "
Dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TV voltage stabilizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
1.8W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
2.1W audio amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3W audio amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual audio preamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General purpose transistor array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7W audio amplifier for CB radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7W audio amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
2W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Minidip 1.2W audio amplifier . . . . . . . . . . . . . ;...... . . . . . . . . . . . . ..
3.4W audio amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Motor speed regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Motor speed regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOW audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FM-I F radio system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FM-IF high quality radio system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
TV vision I F system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preamplifier with ALC for cassette recorders . . . . . . . . . . . . . . . . . . . . . . ..
Motor speed regulator . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
TV vertical deflection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Low-noise TV vertical deflection system . . . . . . . . . . . . . . . . . . . . . . . . . "
Low-noise TV vertical deflection system. . . . . . . . . . . . . . . . . . . . . . . . . ..
TV vertical deflection system .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TV horizontal processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Complete TV sound channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FM-IF radio system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM-FM radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM-FM quality radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low voltage AM-FM radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
Quasi-complementary dual darlington . . . . . . . . . . . . . . . . . . . . . . . . . . . .
231
303
307
320
320
329
342
342
342
347
347
357
364
364
14
14
14
14
367
371
377
382
389
396
14
402
14
409
409
413
420
427
433
442
453
459
469
475
481
493
506
14
514
530
535
14
6
ALPHANUMERICAL INDEX (continued)
Type
TDA1420A
TDA1420L
TDA1470
TDA1670
TDAl770
TDA1904
TDA1905
TDA1908
TDA1910
TDA2002
TDA2003
TDA2004
TDA2005
TDA2006
TDA2008
TDA2009
TDA2010
TDA2020
TDA2020D
TDA2030
TDA2030A
TDA2040
TDA2054M
TDA2140
TDA2151
TDA2161
TDA2170
TDA2190
TDA2310
TDA2320
TDA2320A
TDA3190
TDA3310
TDA3410
TDA3420
TDA4092
TDA4420
TDA4431
TDA4433
TDA7270S
TDA7770
Function
Page
Quasi-complementary dual darlington . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quasi-complementary dual darlington . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vertical deflection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vertical deflection circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Vertical deflection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
4W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5W audio amplifier with muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOW audio amplifier with muting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8W car radio audio amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOW car radio audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 + lOW stereo amplifier for car radio . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
20W bridge amplifier for car radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOW audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12W audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10 + lOW Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12W Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
20W Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
40w audio driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14W Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " .,
18W Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
22W Hi-Fi amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Preampl ifier with A LC for cassette recorders . . . . . . . . . . . . . . . . . . . . . . ..
PAL Subcarrier Reference Oscillator for Colour TV . . . . . . . . . . . . . . . . . . .
Luminance and Chrominance Amplifier for Colour TV . . . . . . . . . . . . . . . . .
Synchronous Demodulator and RGB Matrix for Colour TV . . . . . . . . . . .
TV vertical deflection output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete TV sound channel with VCR and CCC . . . . . . . . . . . . . . . . . . . . .
Hi-Fi dual preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Preamplifier for infrared remote control systems . . . . . . . . . . . . . . . . . . . . .
Minidip stereo preamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Complete TV sound channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Low noise N PN transistor array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual low noise tape preamplifier with autoreverse . . . . . . . . . . . . . . . . . . . ..
Dual low noise tape preamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5 bit binary to 7 segment decoder driver. . . . . . . . . . . . . . . . . . . . . . . . . ..
Vision I F system with AFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TV signal identif. and AFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TV signal identif. and AFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multifunction system for tape players. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Multifunction system for tape recorders . . . . . . . . . . . . . . . . . . . . . . . . . ..
14
14
540
551
563
575
579
592
603
616
623
632
642
656
666
672
683
691
700
711
721
735
742
14
14
14
749
756
775
784
790
800
14
809
817
824
830
837
837
845
14
7
APPLICATION GUIDE: CONSUMER CIRCUITS
Audio Power Amplifiers
TV
~.'~
« .• <».....;,."
""~:',' ":'«.'.\,;"
r"
Horizontal
TDA 1180P
Vertical
TDA1170
TDA1170D
TDA1170N
TDA 1170S
TDA1470
TDA1670
TDA1770
TDA2170
<:
0
.;::;
u
;;:::
'"
0'"
e
.I:.
u
TDA2140
TDA2151
TDA2161
Oscillator
Lumin. & Chromin.
Demodulator
Car radio
Portable radio
TAA611A
TAA611B
TAA611C
TBA820
TBA820M
TDA1904
TDA1905
TV receiver
TBA800
TCA940N
TDA1904
TDA1905
TDA1908
TDA2006
TDA2008
TDA2009
Hi-Fi and Hi-Fi TV
TDA1910
TDA2009
TDA2010
TDA2020
TDA2030
TDA2030A
TDA2040
Driver
TDA2020D
TDA2030A
f-
TV signal identification
TDM431
TDM433
Varicap supply
TAA550A
TAA550B
TAA550C
TV channels display driver
TDM092
Preamplifiers
General purpose
TBA231A
Tape
TDA1054M
TDA2054M
TDA3410
TDA3420
Hi-Fi
TDA2310
Infrared receiver
TDA2320
Stereo preamplifier
TDA2320A
. . . ; . .•.•. •. . 1,···,··!t,$V,e>S ...•••.• • . .•.,.,. . . <'
TBA810P
TBA810S
TBA810CB
TDA2002
T::lA2OO3
TDA2OO4
TDA2005
TDM40S
TDM420
Video I F system
'"
I~pp~i~~.'~,".,····. ·.,.;
TDAl190Z
TDA2190
TDA3190
Complete sound channel
E
i ;;;.:..
..... "'."~~'7.
:.•'.••.'; .. ,•...•....
Radio
IF/FM radio system
TCA3089
TCA3189
TDA1200
AM/FM radio
TDA1220A
TDA1220B
TDA1220L
Tape Recorders
Transistor Array
NPN array
lultifunction
TDA7270S
9
LS159
TBA331
APPLICATION GUIDE: PROFESSIONAL CIRCUITS
Operational Amplifiers
Single general purpose
Positive Voltage Regulators
LS107/207/307
LS141/A/C
LS148/A/C
LS709/A/C
Single high performance
LS1 01/201 /301
Programmable
LS776/C
Dual general purpose
MC1458/C
Dual high performance
LS204/A/C
LS4558N
Quad general purpose
LM324/A
LM2902
Quad high performance
Industrial Circuits
LS404/C
Telecommunications Circuits
Balanced modulator
LS025
Channel amplifier
LS045
Compandor
LS150
Telephone speech circuit
LS156
LS285/A
LS288
LS356
LS656
Multifrequency interface
LS342
Op-amps for active filter
LS204
LS404
10
Power operational amplifier
L165
DC motor positioning
system
L290
L291
L292
DC and stepping
motor driver
L293
L293E
Switch-mode solenoid driver
L294
Printer solenoid driver
L3654
Quad comparator
LM339
Darlington array
L201/2/3/4
L601/2/3/4
L702
Current boosters
L149
TDA1410A
TDA1420A
TDA1420L
Triac/SCR control
L120A
L121A
AUDIO POWER AMPLIFIERS
Selection table (test conditions; d = 10%,
SUpply
(VI
f = 1 kHz)
output Power
IWI
Device
RL=40
RI..""20
RI..=80
4
TBAS20M
0.35
TAA611A
TBAS10S
TBAS20M
TDA1904
0.5
1
0.75
O.S
0.35
6
1.S
1.S
2.5
1.6
1.6
2.2
2.5
1.15
1.15
9
TAA611A
TAA611B
TBAS10P
TBAS20
TBAS20M
TDA1904
TDA1905
12
TAA611B
TAA611C
TBAS20
14.4
TBAS10CB
TBAS10P
TDA1904
TDA1905
TDA190S
TDA2002
TDA2003
TDA2004
TDA2005
18
22
3.4
3
7
7
6
6
4.5
5.4
5.S
5.2
6
2x6.5
2x6.5 (0)
S
10
2xl0
2xl0
1.2
1.2
1.3
2.1
2.1
2
3
3
12 }
2xll RL =1.60
2xll
9
TDA2008
12
S
2xl0
(0)
4.5
5
5.5
5
23
TDA2009
24
TBASOO
TDA1905
TDA1908
TDA2006
12
S
28
TDA2010*
TDA2030*
12
14
9
9
32
TDA2030A*
TDA2040*
lS
22
12
12
36
TDA2020*
20
-
(0) 20W in Bridge
, ....
0.45
TBASOO
TCA940N
TDA1905
TDA190S
9
RL =
!.3} RL =160
(*) d
= 0,5%. f = 1 KHz.
11
OPERATIONAL AMPLIFIERS
LS10n
LS101AT
LS107T
LS14n
LS141AT
LS141CT
LS148T
LS148AT
LS148CT
LS20n
LS201AT
LS207T
LS301AT
LS307T
LS709T
LS709AT
LS709CT
LS776T
LS776CT
LS204T*
LS204AT*
LS204CT*
LS141CM.
LS148CB
LS201B
LS301AB
LS307B
LS776CB
LS204CB*
LS4558NB*
MC1458Pl*
MC1458CP1*
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
o to 70
-55 to 125
-55 to 125
o to 70
o to 70
-25 to 85
-25 to 85
o to 70
o to 70
-55 to 125
-55 to 125
o to 70
-55 to 125
o to 70
-25 to 85
-55 to 125
o to 70
o
o
o
o
o
o
o
o
o
o
to
to
to
to
to
to
to
to
to
to
70
70
70
70
70
70
70
70
70
70
LS141CM
LS148CM
LS201M
LS301AM
LS307M
LS776CM
LS204M*
LS204CM*
LS4558NM*
MC1458M*
MC1458CM*
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
-25 to 85
o to 70
o to 70
o to 70
o to 70
LM324N**
LM324AN**
LM2902N**
LS709CB
LS404CB**
-25 to 85
-55 to 125
o to 70
o to 70
o to 70
LM324CM**
LM2902CM**
LS404M**
LS404CM**
-25 to 85
o to 70
-25 to 85
o to 70
, Dual
* * Quad.
••
••
•
•
••
••
•
•
•••
••
•
•
••
••
••
•
••
•
•
•
•••
90
96
96
90
95
90
90
95
90
90
96
96
90
90
90
110
90
120
30
30
80
30
80
80
20
80
250
30
30
70
70
200
100
300
10
10
0.7
0.5
0.7
0.5
5.5
5.5
5.5
10
10
0.7
10
0.5
0.25
0.25
0.25
22
22
22
22
22
18
22
22
22
22
22
22
18
18
18
18
18
TO-99
~
90
i5
0.35
i8
90
100
100
95
15
50
50
80
0.8
1.5
1.5
1
18
18
18
18
90
90
90
90
90
90
95
90
90
90
80
80
250
70
70
15
80
50
80
80
0.5
5.5
10
10
0.5
0.8
1
1.5
0.5
0.5
±18
± 22
± 22
±18
± 18
± 18
±18
±18
±18
± 18
WN
90
90
90
90
90
90
100
95
90
90
90
80
80
250
70
70
15
50
80
50
80
80
0.5
5.5
10
10
0.5
0.8
1.5
1
1.5
0.5
0.5
± 18
50-8
± 22
± 22
± 18
±18
± 18
± 18
± 18
± 18
±18
± 18
§fij9
70
85
70
90
90
45
45
45
300
100
70
70
94
90
45
45
50
100
12
0.25
1
32
32
32
± 18
± 18
32
32
± 18
± 18
Minidip
DIP
~Niif
SO-14
~
POSITIVE VOLTAGE REGULATORS
R"gulated .000t\>Ut vo\t!'IJ~ .tV)
I" max
(A)
2
1.5
IH~
L200CH/CV
L200CT/T
L78S00CV
L78S00CT/T
2.9 ..
2.9.-
LMl17K
LM217K
LM317K
LM317T
1.21.2.·
1.21.2 ..
•
•
L7800CV
L7800CT/T
0.5
0.15
L2600V
L78MOOCV
L 194-5V*
L 194-12V*
L194-15V*
L487
.
'•.
9101Z
15
ADJUSTABLE
ADJUSTABLE
• •
• •
Versawatt
TO-3
ADJUSTABLE
ADJUSTA.BLE
ADJUSTABLE
ADJUSTABLE
TO-3
TO-3
TO-3
Versawatt
Versawatt
TO-3
•
••
Versawatt
Versawatt
Pentawatt®
Pentawatt®
Pentawatt~
Pentawatt
POO1-A
TO-1OO
POO1-L
TO-1OO
L 123CB
L123CT/T
L146CB
L 146CT/T
* With integrated rectifying bridge.
NEGATIVE VOLTAGE REGULATORS
13
NOT FOR NEW DESIGN
TO-18
TAA550
TV VOLTAGE STABILIZER
TAA 611A
TAA 611B
TAA 611C
1.8W AUDIO AMPLIFIER
2.1W AUDIO AMPLIFIER
3.3W AUDIO AMPLIFIER
14-DIP/TO-100
14-DIP
14-DIP
TBA 820
TCA 830S
2W AUDIO AMPLIFIER
3AW AUDIO AMPLIFIER
14-DIP
FIN-DIP
12
15
22
16
20
TDA 1200
FM-IF RADIO SYSTEM
16-DIP
16
PENTAWATT@
PENTAWATT@
PENTAWATT@
36
44
40
KIT CHROMA
16-DIP
16-DIP
16-DIP
15
15
15
LOW-NOISE NPN TRANSISTORS
14-DIP
FIN-DIP
V z = 30V to 36V, IZ(max)= 20 mA
Po = 1.8W (9V - 4n). Po = 1.15W (9V - 8n)
Po = 2.1W (12V - 8n). Po = 1.15W (9V - 8n)
Po = 3.3W (15V -8n), Po = 1.7W (12V - 8n)
Po = 1.2W (9V - 8n)
Po = 2W (12V - 8n).
Po = 3AW (12V -4n). Po = 2.3W (12V -8n)
I See TCA 3089
.I:>
TDA 1410A
TDA 1420A
TDA 1420L
TDA 2140
TDA 2151
TDA 2161
TDA 3310
QUASI COMPLEMENTARY
DUAL DARLINGTON
hFE
hFE
hFE
> 800@ 2A
> 500@ 3A
> 800@ 2A
20
hFE
> 300 @ 100/lA,
20
Motor speed regulator, Bias Oscillator, DC record
play switching, Automatic stop.
NF = 0.5 dB
ARRAY
TDA 7770
I MULTIFUNCTION SYSTEM FOR
TAPE RECORDERS
PRECAUTIONS FOR PHYSICAL HANDLING OF POWER LINEAR ICs
When mounting power ICs certain precautions must be taken in operations such as bending of leads,
mounting of heatsink, soldering and removal of flux residue. If these operations are not carried out
correctly, the device can be damaged or reliability compromised.
1.
Bending and cutting leads
The bending or cutting of the leads requires the following precautions:
1.1 When bending the leads they must be clamped tightly between the package and the bending point
to avoid strain on the package (in particular in the area where the leads enter the resin) (fig. 1). This
also applies to cutting the leads (fig. 2).
1.2. The leads must be bent at a minimum distance of 3 mm from the package (fig. 3a).
1.3. The leads should not be bent at an angle of more than 90° and they must be bent only once
(fig.3b).
1.4. The leads must never be bent laterally (fig. 3c).
1.5. Check that the tool used to cut or form the leads does not damage them or ruin their surface.
Fig. 1 - Bending the leads
Fig. 2 - Lead forming or cutting mechanism
w
Plastic
packag~1 t
rn
j
I
\::~h1~1~~ng
Spaced? W
"'-0039
Clamp mechanism
Fig. 3 - Angles for lead wire bending
3.0min
a
c
b
15
or cutting
2.
Mounting on printed circuit
During mounting operations be careful not to apply stress to the integrated circuit.
2.1. Adhere strictly to the pin spacing of the IC to avoid forcing the leads.
2.2. Leave a suitable space between printed circuit and integrated circuit, if necessary use a spacer.
2.3. When fixing the device tp the printed circuit do not put mechanical stress on the IC. For this
purpose the device should be soldered to the printed circuit board after the IC has been fixed to the
heatsink and the heatsink to the printed circuit board.
3.
Soldering
In general an Ie should never be exposed to high temperatures for any length of time. It is therefore
preferable to use soldering methods where the IC is exposed to the lowest possible temperatures for
a short time.
3.1. Tolerable conditions are 260°C for 10 sec or 350°C for 3 sec. The graphs in fig. 4 give an idea of the
excess junction temperature during the soldering process for a TO-220 (Versawatt). It is also important to use suitable fluxes for the tin baths to avoid deterioration of the leads or of the package
resin.
3.2. An excess of residual flux between the pins of the integrated circuit or in contact with the resin can
reduce the long-term reliability of the device. The solvent for removing excess flux must be chosen
with care.
The use of solvents derived from trichloroethylene is not recommended on plastic packages because
the residue can cause corrosion.
.
Fig. 4 - Junction temperatures during soldering
TJ
260·( soldering bath
Tj
Exposed to air
('0 )
('C)
h :
150
100
---l
350·C soldering bath
Exposed to air
150
100
;
1.5mm :
50
260.C
20
40 60 80 100
50
I
Solder
I
1,"0
180
110
50
Time {sec)
16
60
Time(secl
I.
,.,
~
"
I.,
4.
Mounting of heatsink
To exploit best the performance of power ICs a heatsink with
will dissipate must be used.
Rth
suitable for the power that the IC
4.1. The plastic packages used by SGS for its linear ICs (Pentawatt, Multiwatt, Versawatt) provide for
the use of a single screw to fix the package to the heatsink. A compression spring (clip) can be
sufficient as an alternative (fig. 5).
Fig. 5 - MULTIWATT® mounting examples
The screw should be properly tightered to ensure good
contact between the back of the package and the heatsink
but should not be too tight to avoid deformation of the
copper part (tab) of the package causing breaking of the
die or separation of the resin from the tab (fig. 6).
Fig. 6 - Contact thermal resistance
vs. tightening torque
,.
l--L
("C/W )
MULTIWATT
0.8
'\
""- ........
06
I'
"
W"ho",
]!
'''''00" "m.
siuL.I""tj:
r-- -
4.2. The suggested tightening torques with a 3 MA screw are:
Versawatt 6 Kg/cm
Pentawatt 6 Kg/cm
Multiwatt 8 Kg/cm
--
c----
Torque (Kglcm)
If different screws are used the force transmitted to the tab must not exceed that encountered in
the above conditions.
When fixing the device avoid bumping or stressing the resin and pins with the tools used for this
operation (pneumatic screw drivers, tweezers etc.).
17
r.
i
4.3. The contact Rth between device and heatsink can be improved by inserting a thin layer of silicone grease with
fluidity sufficient to guarantee perfectly uniform distribution on the surface of the tab. The thermal resistance
with and without silicone grease is given in fig. 7. An
excessively thick layer or an excessive viscosity of the
si Iicone grease can be damaging for the Rth and for any
tab deformations.
5.
Fig.7 - Contact thermal resistance
insulator thickness
VS.
Heatsink problems
The most important aspect from the point of view of
reliability of a power IC is that the heatsink should be
dimensioned to keep the Tj of the device as low as
possible. From the mechanical point of view, however, the
heatsink must be realized so that it does not damage the
integrated circuit.
0.05
5.1. The planarity of the contact surface between device and heatsink must be
and Versawatt and < 20 Jlm for Multiwatt.
0.10
0.15
Th(mm)
< 10 Jlm for Pentawatt
5.2. If self threading screws are used there must be an outlet for the material that is deformed during
formation of the thread. The diameter if> 1 (fig. 8) must be large enough to avoid distortion of the
Fig. 8 - Device mounting
WRONG
RIGHT
tab during tightening. For this purpose it may be useful to insert a washer or use screws of the type
shown in fig. 9 where the pressure on the tab is distributed on a much larger surface. Sometimes
when the hole in the heatsink is formed with a punch, around the hole
Fig. 9 - Suggested screw
or hollow there may be a ring which is lower than the heatsink surface.
This is dangerous because it may lead to distortion of the tab as mentioned before.
T
5.3. A very serious problem is that of the rigidity between heatsink,device
and printed circuit board. When mounting the heatsink, device (which
may be fixed to frame of apparatus) and printed circuit board are
;''"''
bound together by the leads of the device. A solution of this type is extremely dangerous,especially
if the equipment is subjected to vibrations.
18
SEMICONDUCTOR USERS RELIABILITY EVALUATION
SGS SURE III programme is an important improvement of SURE II programme obtained with tightened
quality levels. Moreover there are many level's options to satisfy various customer's requests.
SGS SURE III programme aims to inform customers of basic production operations and internal quality
and reliability assurance procedures, paying particular attention to the tests and guarantees on the
finished product.
This programme covers the set of 100% operations, controls and testing operations undergone by the
devices produced to standard specification, i.e. without any special customer requirements.
In other words, unless special co-produced specifications are used, the majority of SGS customers in the
professional, consumer and industrial markets buy products tested according to the SURE III programme.
The programme thus fully meets the requirements of almost all applications.
Moreover, since the programme offers more options, the customer can request the product with certain
supplementary screenings, while the entire production process, apart from the optional operations
indicated in the programme, remains identical to that of the standard product.
General Information
This information is valid for all products ordered from SGS or which are ordered to one of the SURE
Programme options.
Marking
Each device will be marked in a contrasting ink with the following standard information (if sufficient
space is available);
1 - SGS logo
2 - Device type as shown in the detail specification
3 - Manufacturing plant number
4 - Lot code (Production lot)
Packing
Device will be packed in the SGS standard package.
The following information will be marked on the primary package.
1 - SGS logo
2 - Device type as shown on the order confirmation
3 - Quantity in the package
4 - SGS order confirmation
5 - Warning label on Mos products
Testing and finishing
1 - Screenings according to MIL or CECC or however to this programme
2 - 100% electrical testing according to SGS data sheet
3 - Temperature acceptance
When an extended temperature range is guaranteed SGS Outgoing QC may carry out the test at temperatures other than those shown on the data sheet on the basis of temperature correlation of the
parameters.
SGS, guarantees the applicability of the AQL levels at the temperature limits and will accepts any lot
rejected as a consequence.
19
External visual and Mechanical Inspection Criteria (group A Acceptance)
Inoperative mechanical defects (critical):
e.g. wrong pin indication, wrong marking or splitting, broken or weakened leads, short circuits between leads, missing or partially detached cap, mixed package, cap and frame not aligned at the same
side, catastrophic bent leads.
Major defects (significant mechanical defects, but not functional defects):
e.g. open packages, deformed leads, unmarked packages or with illegible marking, deep cracks on
packages, incomplete tinning or with bubbles - roughness - blackenings, lead straightness and
position not in accordance with relevant drawing.
-
Minor defects:
Reference specification
a) Basic Sampling Procedures and tables for inspection by attributes: MI L-STD-105D, IEC 410.
In general the single sampling plan will be used but it is acceptable for the customer to use double or
multiple sampling (with, naturally, the same AOLs and inspection levels).
Similarly O.C. managers can also use double or multiple sampling.
b) The Sure III Programme has been prepared considering the following specs: IEC 68-2, MI L-STD883B, CECC 50000, MIL-STD-38510 D and IEC 147-5.
It should be noted that conformance with these specs should be assumed only where specifically
stated in th is programme.
Precedence of documents
For the purpose of contractual interpretation in case of conflict, documents shall take the following
order of precedence:
1
Purchase order or contract. The text of the order or contract prevails over any other specification.
2
Detail specification. The detail specification agreed between customer and vendor prevails over this
present specification and any other reference specification.
3
Generic specification. The generic specification (including this programme) prevails over all reference specifications.
4 -
Relevant specification. All reference documents apply only to the extent defined here in.
Essential terms and definitions
For the purpose of interpretation of this general specification the following terms and definitions are
applied:
Detail/relevant/blank specification
A specification which covers a particular component or range of components, and which describes that
component including rated and/or limiting values and characteristics. The detail specification will also
give the inspection requirements or appropriate reference to this general specification.
Inspection lot
A quantity of components presented together for inspection from which a sample is to be drawn and
inspected to determine conformance with the acceptance criteria of the specification.
20
Production lot
Consists of one lot of devices sealed within a period not exceeding six weeks.
Delivery lot
A quantity of components del ivered to an order at one time. One del ivery lot may consist of one or
more inspection lots or parts thereof.
Structurally similar devices
-----------Structurally similar devices are those devices produced concurrently through final seal by the same
fabrication techniques, using the same type of machines and apparatus and having the same basic design
rules and the same packaging.
Details of structural similarity for various components will be defined, when required, by the SGS
Quality Assurance Mgr(s).
Certificate of Conformance
A document issued with a delivery lot stating that the components have been taken from one or more
inspection lots accepted under the requirements of the particular specification.
21
Standard production process flow chart
KEY:
OPERATION/SCREENING
IN-PROCESS CONTROL (MONITOR)
GATE INSPECTION (SAMPLE ACCEPTANCE)
HERMETIC PACKAGE
PROCESS
MOLDED PACKAGE
PROCESS
MATERIAL INSPECTION
Starting materials are inspected following written specification and
records are maintained for traceability.
2
WAFER FABRICATION
Masking, etching, diffusion and metallization processes produce
finished dice in wafer form.
3
IN-PROCESS CONTROL
Wafers and process environment are inspected at main process steps.
4
ELECTRICAL WAFER SORT
Each die is electrically tested and identified when doesn't meet
electrical requirements.
5
FINISHED WAFER INSPECTION
Active surface and back finish are inspected on each diffusion lot
before release for die fab and assembly.
6
DIE-FABRICATION
Wafers are separated into individual dice and electrical rejects are
removed.
7
VISUAL SCREENING
Dice are inspected and selected at high magnification.
8
QUALITY INSPECTION
Each dice lot is accepted before assembly (visual inspection of active
surface)
9
DIE ATTACH
10
QUALITY CONTROL (Table I)
Daily visual and mechanical (die shear strangth) control.
11
WIRE BOND
22
Standard production process flow chart (continued)
HERMETIC PACKAGE
PROCESS
MOLDED PACKAGE
PROCESS
12
QUALITY CONTROL (Table I)
Daily visual and mechanical (bond strength) control.
13
PRECAP VISUAL
Assembled but unsealed units are individually inspected at low and
high power magnifications.
14
QUALITY INSPECTION (Table I)
Each lot is accepted before sealing to verify compliance to precap
inspection specifications.
15
FINAL SEAL
16
MOLDING AND CURING
17
SEALING ATMOSPHERE CONTROL (Table I)
18
SEAL AND LID TORQUE CONTROL (Table I)
19
TEMPERATURE CYCLING (Table I)
20
CROPPING
21
CROPPING CONTROL
22
LEAD FINISH
23
LEAD FINISH INSPECTION (SOLDERABILITY - Table I)
24
FINAL CROPPING
25
INTERNAL WATER-VAPOR CONTENT CONTROL (Table I)
26
HIGH IMPACT SHOCK (Table I)
27
RAW LINE INSPECTION (Table I)
28
GROUPS B, C, AND D TESTS
QUALITY CLASSES
OPTIONS
QUALITY CLASSES
OPTIONS
23
Production quality tests description and screenings
TABLE I
10
DIE-ATTACH CONTROL
MIL STD 883B Mth 2010 condo B (internal visual) and Mth 2019
(die shear strength).
12
BONDING CONTROL
MIL STD 883B Mth 2010 condo B (internal visual) and Mth 2011
condo C (bond strength).
14
PRECAP INSPECTION
MIL STD 883B Mth 2010 condo B (internal visual)
17
SEALING ATMOSPHERE
CONTROL
18
SEAL CONTROL
Moisture content:
for Ceramic packages
for Metal Can packages
< 50 ppm
< 120 ppm
Fine Leak:
Metal can packages
IEC 68-2-17 test QK (CECC 50000 para 4.4.10)
Helium leak detector after pressurization in He for 16 hrs at 5
atm.
Limiti 5 • 10- 7 ccls
Ceramic packages
MIL STD 883B Mth 1014 condo Al
Helium leak detector after pressurization in He for 2 hrs at
4 atm.
Limit: 5· 10-' ccls for I.C. V .• < 0.4 cc
5 • 10- 7 ccls for I.C.V. ;. 0.4 cc
* (I.e.v. = internal
cavity volume).
Gross Leak:
Metal Can packages
I EC 68-2-17 test Qc Mth 2 (CECC 50000 para 4.4.10).
Bubble test in mineral oil at T amb = 125°C after pressurization in He for 16 hrs at 5 atm.
Ceramic packages
MIL STD 883B Mth 1014 condo C.
LI D TORQUE TEST
(CONTROL)
19
TEMPERATURE
CYCLING
Ceramic Packages only - MI L STD 883B Mth 2024.
-
From -25°C to +1500C; 30 min at extreme temperatures;
5 minutes transfer time; n° 5 cycles
CROPPING
Not for Metal Can packages.
23
SOLDERABI LlTY
INSPECTION
-
25
INTERNAL WATER VAPOR
CONTENT CONTROL
Dew Point method MIL STD 883B Mth 1018 procedure 3 - 5000
ppm max. (dew point temperature less than -15°C).
26
HIGH IMPACT SHOCK
Metal Can packages only except TO-3 and TO-66.
20000 G min.; T = 25 ),lsec min; Yl axis only.
27
RAW LINE INSPECTION
20-21-24
IEC 68-2-20 Test TA (bath method) - CECC 50000 para
4.4.7 - 230 ± 5°C with preconditioning for 16 hrs at 155°C.
External Visual
- MIL STD 883B Mth 2009.
Lid torque test: as per step 18.
Centrifuge (ceramic packages only)
MIL STD 883B Mth 2001
High I mpact Shock: as per step 26
Seal control: as per step 18
24
Available class options (*)
HERMETIC
MOLDED
r----- ----,
_ _ _ _ _ _specs:
_ _ -.J
L -ESA/SCCG
MIL class 8
MIL class C
Class B1
(81 160hrs)
Class 82
Class 83
(Automotive)
Class 84
Class 84
Class STD
Class STD
(*) SGS-A TES will also supply devices to CECC specifications when these are issued.
Quality & reliability tests
A
Each lot
Each lot
B
Each lot
See group C
C
3 months
3 months
o
6 months
6 months
25
Quality class options
B1
B2
B3, B4, STD
(Hermetic packages only)
(Hermetic packages only)
(Hermetic and molded packages)
100% electrical test
Reduced electrical test
100% electrical test
Marking
Marking
Marking
Burn-in 160 H
Burn-in 48 H
Group A acceptance (STD)
100% electrical test
100% electrical test
Group A acceptance (B 1)
Group A acceptance (B2)
Group A acceptance (B3 or B4
or STD)
Pack
Pack
Pack
Pack and documentation acc.
Pack and documentation acc.
Pack and documentation acc.
Ship
Ship
Ship
Group A acceptance (.)
Al
A2
A3
A4
Visual and mechanical insp.
Major
Minor
0.25
1
Inoperative failure
(electrical and mechanical)
over guaranteed tempe·
rature range
Tmax
25°C
T min
II
DC parameters and main
AC parameters over
gu aranteed temperatu re
range
Tmax
25°C
Tinin
II
Other AC parameters
25°C
S4
}0.15
0.25 0.25
1
1
} 0.15
0.15
0.65
0.25
1
0.25
1
0.065 } 0.1
I
0.25
0.65
26
} 0.1
10 .25 10 .4
0.65
Parameters are guaranteed within the teDlperature range by 250 C correlation measurements.
* Automotive devices only.
(.)For MIL class B/C and ESA/SCCG products see relevant SGS-ATES documents.
0.25
1
0.65
0.25 0.25
1
1
} 0.1
0.1
-
} 0.4
0.4
0.65 0.65
j
I
TABLE III - Group C tests - every 3 months on raw line material (+)
"'.~;}:
V :>:' ~'~';"'"
.•.'.•'::\;;:i:;;[~~~,'
.",.' ~,\t "".>>;'\.
;:, ,'; <;}~,
.",:::};.:
~); "'~
"
'Mft;4T1ii~~; "',
"",,::;'2 ,.:.:" ';< :';
"
" " \ " ' > , " " ' . ".",/;-;""";""< '"
",~:,\:;:;;,;,;;:,,:;,;,.. '
:,.
~~:':
Subgroup 1
Physical dimensions
-
Resistance to solvent
2015
Subgroup 3 11)
Solderability (2)
2003
Subgroup 4
Steady state and operating life
test or
I ntermittent Iife test
End-point electrical
parameters
2 devices (no failure)
2016
Subgroup 2 11)
1005
-
Ceramic packages
Molded packages: solvent solution 2.1A only
Metal can packages
4 devices (no failure)
Soldering temperature of 260 + 1 O"C or I EC
method 68-2-20 test T A (230 ± 5°C)
1000 hrs; according to device spec. type
15
2
5
2
15
2
-
5000 cycles
Key parameters (Table V); measurements at 0, 168,
500 and 1000 hrs,
Subgroup 5
(Hermetic packages only)
Temperature cycling
Constant acceleration
Seal (41
a) fine
b) gross
1010
2001
1014
F.,,-l-+-+-.J----i-+-+-.J----i-++.J----i-+-I---l
'm'l
'.
(V)
::::~~~:E
"
G:rEE:~~:: H+f1l-+I++-HflI
.
'"
"-
,!'.
1111
/8
220"" 15
10
t
'-~~~-I,-j~~~~~-4~
I
"
'"
"
-"
10 Rs(KA)
61.
H-
"
"'--
0.6
"
II
j
-'0
17
0.'
-10
10
30
SO
70
90
-
TambCoCJ
Fig. 6 - Ramp width vs. ex·
ternal time constant RI6 'C I
""1131-
os
_30
f..-
"
C 11_15 C"FI
Fig. 7 - Alternative system for reduction of power dissipation
.7Kn
3Vi
"
"
'0'
G-113ZIZ
".
ems)
20
-20
'0
T.. mb("cl
Fig. 5 - Gate pulse width
vs. C ll - 15
Fig. 4 - Gate current variation vs. ambient temperature
(mAl
"
30
IN4001
I
0j:7,.., 300 n
~
9
'0
LI21A
8
I
IN'OOI
!"
I
46
(250'1-) 1IZW
r
S~"Of'n
%20'
I ,',I:
i)
.~
I+i'
~
I
:.\
APPLICATION INFORMATION
Fig. 8 - Application circuit for temperature control (proportional type)
r-~~--------~~---~~------------------~O
rv 22()...21.0V
50-60Hz
Fig.9 - Application circuit for temperature control (ON-OFF type)
l~~F
':iiF20~F
II
I
1
16
15
14
I
12
13
"
10
9
6
7
8
6.8Kll 11 W "-'220 v-I
r
L' 2' A
1
I
2
J
~
5
4
I
ii
r
220,I.JF
l'so"lt
NTC
m!!.
''"ni
.el
390
RL
n)
,
I
II
~1.
10Kll.
,!
1··.
5 - LOS4/2
11
i
I;1
\
47
Fig. 10 - Application circuit for low AC supply voltage (by using pin 14)
5."
O.oIIJF
loon
rv
220-240V
SO-60Hz
lOOk
1.
L 121A
10)JF
10V
RL
10
kO
180.ll.
5-351912
Fig. 11 - Cimate control for car.
120.ll.
r----------------------------.---{==~~~OVS=12V
100
10
K.ll.
K.ll.
15
14
47
L 121 A
2 .
IN 4148
IOnF
KJl
4
100KJl
,
270 KJl
1
220IJF
Q.11J F
.i-T *12VI1W
5-3967/1
* Protection against overvoltages.
Pi : system hysteresis setting
P2 : temperature setting
NOTE - For a more detailed descriDtion of the L 120A and its applications refer to SGSDESIGN NOTE - DN 382.
48
'SLiNEAR INTEGRATED CIRCUIT
HIGH PRECISION VOLTAGE REGULATOR
INPUT VOLTAGE UP TO 40V
OUTPUT VOLTAGE ADJUSTABLE FROM 2 T037V
POSITIVE OR NEGATIVE SUPPLY OPERATION
SERIES, SHUNT, SWITCHING OR FLOATING OPERATION
OUTPUT CURRENT TO 150 rnA WITHOUT EXTERNAL PASS TRANSISTOR
ADJUSTABLE CURRENT LIMITING
•
•
•
•
•
•
The L123 is a monolithic integrated prQgrammable voltage regulator, assembled in 14-lead dual in-line
plastic package and 10-lead Metal Can (TO-100 type). The circuit provides internal current limiting.
When the output current excedes 150 rnA an external NPN or PNP pass element may be used. Provisions
are made for adjustable current limiting and remote shut-down.
ABSOLUTE MAXIMUM RATINGS
Vi
lN i _O
10
I ref
Ptot
Input voltage
Dropout voltage
Output current
Current from V ref
Power dissipation (at T amb = 70°C) Plastic DIP
TO-100
Operating junction temperature
Storage temperature
MECHANICAL DATA
L123
L123C
40V
40V
40V
40V
150mA
15 rnA
150mA
25mA
1W
520mW
to 70°C
-65 to 150°C
520mW
-25 to 150°C
-65 to 150 °C
o
Dimensions in mm
49
6/82
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top views)
NC
CURRENT
NC
CURRENT
LIMIT
13
liMIT
CURRENT
SENSE
INVERTING
INPUT
"
INVERT.
NON-
3
INVERT
'0
INPUT
PIN 5
COMP.
·v,
Vc
INPUT
NONINVERTING
INPUT
FREQUENCY
v,
Vref
Vz
-v,
NC
V
connected Iotas€' - S
Type
TO-l00
Plastic DIP
L123
L123T
-
L123C
L123CT
L 123CB
TEST CIRCUIT
BLOCK DIAGRAM
(Pin configuration relative to the Plastic package)
INVERT.
INPUT
FREQUENCY
CQMPENS
Ve
I
I
SERIES PASS I
TRANSISTOR
NON-INVERT.
CURRENT
CURRENT
INPUT
LIMIT
SENSE
Vj'" 12V
Vo '" 5V
10'" 1 mA
~
A 1IJR 2 .;;;; 10 Kn
THERMAL DATA
Rth j-amb
TO-100
max
Thermal resistance junction-ambient
50
Plastic DIP
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C unless otherwise
specified)
L123C
Unit
Min.
t:,vo
~
/',V o
-Vo
Line regulation
Vi~12t015V
V· ~ 12 to 40V
Vi - 12 to 15V;
T min";; T amb ~ T max
Load regu lation
~
10
Typ.
Max.
0.01
0.1
0.1
0.5
1 to 50 mA
0.03
Reference voltage
Iref~
SVR
Ripple rejection
f
~
6.8
160!LA
Input voltage range
Vo
Output voltage range
Quiescent drain
current
0.01
0.02
0.1
0.2
%
%
0.3
%
0.15
%
0.6
%
7.35
V
0.03
7.5
6.95
7.15
74
86
150
Rsc~
10n
Vo~
0
Vi-YO
Id
7.15
Output voltage drift
Vi
0.2
74
86
0
Cref~ 5 !L F
Short circuit current
limiting
Max.
100 Hz to 10KHz
Cref~
Ise
Typ.
0.6
10~1t010mA
V ref
Min.
0.3
T min ~ T amb ~ T max
/',V o
~
L123
Test conditions
Parameter
10
Vi
~
~
dB
dB
150
65
65
ppm
---ac
mA
9.5
40
9.5
40
V
2
37
2
37
V
3
38
3
38
V
5
mA
0
30V
2.3
Long term stability
4
0.1
2.3
0.1
%-1000
hrs
eN
Vz
Output noise voltage
Output zener vOltage
BW~
Iz
~
100 Hz to 10 KHz
Cref~ 0
Cref~ 5 !LF
1 mA
6.9
(for plastic package
only)
Note:
20
2.5
T min ~ O°C iL123C); -25°C (l123).
T max~ 70°C (l123C); 150°C il123).
51
20
2.5
7.7
!LV
!LV
V
Ij
Ii
I;
Fig. 1 - Maximum output
current vs. voltage drop
Fig. 2 - Current limiting
characteristics
G·4J4011
,
Fig. 3 - Current limiting
characteristics vs. junction
temperature
0.7
vi: 12 II
r-
Rse : Ion
0.6
.
u
g
N
!
I
:
,
I
!
I
10
Fig. 4 - Load regulation
characteristics without current limiting
I-- f---t-~. r-- r-t--
arnb~
O'c
~.?SoC
a~
--
CUR~ENT
"'"
,
-0.1
va
-10
10
-0.2
40
r .~
;::::-
"'::::-
('/.)
0.1
-"
100
60
TJ (OC)
G- 4 344
,
Vo ",5 II
I
r~~
~
:::f-.C
iit~6 ~'2S
·cr--
:5V
.
I
I-- -
--..
-.....
-
Vi =1211
R5e =10ll.
"""'I~
-
I
-0.1
~~
I
-f---
T
\-
J~
i\TA :25~C
~
r-
TA =l25'C
I \
-0.4
10
t--
A:~5'C
\ '\
I
"
r- r-
I
,,\~
-0.3
60
Fig. 7 - Line regulation vs.
voltage drop
61J0 /Vo
,
~
Fig. 6 - Load regulation
characteristics with current
limiting
'il
-0. 1
,10
:::--r-.-
r::-.;;~.'04
1
-0.0
~
I
-~~~~:1~
10
~
;-- r--
-60
Fig. 5 - Load regulation
characteristics with current
limiting
--..
-0.3
,60
10)
Fig.8 - Unity gain configuration
·,s
O.llJf
:I:
lN4001
10Kn
IN4001
.2
76
11KHz)
Fig.9 - Motor current control circuit with external power transistors (lmotor
> 3.5A)
+ Vs max36V
IOKJl
36Ko.
~
3.3Kfl2%
R2*
R7
Q,22},JF
~l
8D535
10Kfl
3.3KD
35Kll
... Vi
=0
'BV~~~C=J-~~~~~~~~~~~~~-c=r~~+-~~~~~~~-~~~~~
R3*
Note: The input voltage level is compatible with L291 (5-BIT D/A converter)
Fig. 10 - High current tracking regulator
Fig. 11 - Bidirectional speed control of
DC motor
... 15V
"'o-----r'
"pF
-- -------------0 • Vo
Lr,-...".....
-r-~:J..
OK"
1OKD.
~.~~~--CJ-
O,l,uF+-_~-c5-~~.,
..,..,O.2Z,.oF
i
fl'
.>=-----+----l~.'o
-Vi (}-~~~--'-~~~~-'
A:for±18';;;V i ';;;±32
Note -
V z must be chosen in order to verify
2 VI - V z ';; 36V
B: for V I ';;;± 18V
77
Fig. 12 - Split power supply
Fig. 13 - Power squarewave oscillator with independent adjustments for frequency and duty-cycle.
R1
2.2Kll
R2
2.2K !l.
>4--.--D"out
Pl : duty-cycle adjust
P2 : frequency adjust (f = 700 Hz with
Cl= 10 nF, P2= 100 Kn, f=25 Hz
with Cl= 10 nF, P2= 0)
..rLn.
'fi
5-5361
Fig. 14 - Bidirectional DC motor control with TTL!C-MOS/j.lP compatible inputs
V Sl = logic supply voltage
Must be V S2
;;:'
V S1
El, E2 = logic inputs
NOTE - For a more detailed description of the L 165 and its applications, refer to SGSTECHNICAL NOTE TN. 150.
78
LINEAR INTEGRATED CIRCUITS
POSITIVE VOLTAGE REGULATORS WITH RECTIFYING BRIDGE
•
•
•
•
•
OUTPUT VOLTAGE: 5V, 12V AND 15V
OUTPUT CURRENT UP TO 500 mA
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
OVERVOLTAGE PROTECTION (60V - 10 ms)
The L 194-5, L 194-12 and L 194-15 are fixed voltage regulators assembled in Pentawatt ®
They incorporate a rectifying diode bridge with 7A surge current capability.
package.
ABSOLUTE MAXIMUM RATINGS
Vi
Vi
Vi
VR
ID
I DS
10
Ptot
T st9
Tj
Peak input voltage (10ms)
DC input voltage (at pin 2)
AC input voltage (rms)
Peak reverse voltage across each diode
Input diode repetitive current
Input diode surge current (10 ms)
Output current
Power dissipation
Storage temperature
Operating junction temperature
60
40
28
80
2
7
Internally limited
Internally limited
-65 to + 150
-25 to + 150
V
V
V
V
A
A
°C
°C
ORDERING NUMBERS: L 194-5V
(Vo= 5V)
L194-12V (Vo= 12V)
L194-15V (Vo= 15V)
MECHANICAL DATA
Dimensions in mm
79
6/82
CONNECTION DIAGRAM
(top view)
'I!
:&4: ~~:
~II
~'''"'
,
.
(tab connected to pin 3)
AC INPUT
5-4034
BLOCK DIAGRAM
4 OUTPUT
AC
INPUT
DC
INPUT
5- 4035
GND
THERMAL DATA
Rth j-case
Rthj-arnb
Thermal resistance junction-case
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (Tj
Quiescent drain
current
Vo
Output voltage
/;V o
10 = 0
Vi (pin 2) = 28V
10= 100 rnA
VI = 15V (L194-5)
VI = 22V (L194-12)
Vi = 25V (L194-15)
10 = 100mA
Vi= 8 to 18V (L194-5)
Vi = 15 to 25V (L194-12)
VI = 18 to 28V (L194-15)
Line Regu lation
4
50
°C/W
°C/W
= 25°C)
Test conditions
Parameter
Id
max
max
80
Min.
4.75
11.4
14.25
TVp.
Max.
Unit
5
14
rnA
5
12
15
5.25
12.6
15.75
V
5
10
15
mV
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
t,vo
Load Regulation
10=10to
250 mA
Vo
V i- O
Dropout voltage
(pin 2-4)
t,vo
Output voltage drift
Min.
Vi = 15V (L194-5)
VI = 22V (L194-12)
Vi = 25V (L194-15)
lo=100mA
I:5.V
o
--v;;
10
Output current
Ise
Short-circuit current
~ 1%
2
Vi = 15V (L194-5)
Vi = 22V (L194-12)
Vi = 25V (L194-15)
L 194-5/12
L194-15 (*)
Max.
1
1
1
10 = 300 mA
LIT
Typ.
%
3
0.3
0.6
0.8
V
mV/oC
500
300
Vi = 15V (L194-5)
Vi = 22V (L194-12)
Vi = 25V (L194-15)
Unit
mA
700
500
400
0.7
mA
1.4
A
Ip
Peak output current
SVR
Supply voltage
Rejection
f=100Hz
10=200mA
LlV i =10V
L 194-5/12
L194-15
46
40
dB
Ro
Output Resistance
f = 1 kHz
10=100mA
80
mn
Vd
Diode Forward
Voltage
If = lA
If = 5A
1.6
4.5
V
(*) See diagram of fig. 1.
APPLICATION CIRCUIT
In the design of power supplies using
the L194, it must be always verified
that:
_ V2R V s
Ipeak -
<7A
5
where Rs is the sum of the transformer
resistance, the equivalent diode resistance and external resistors.
81
APPLICATION INFORMATION
The Absolute Maximum Ratings guarantee a max of 40V at pin 2 with max peak current of 7 A in the
rectifying diodes.
To avoid to damage the device, a suitable transformer secondary must be used so that even when there
are network variations the limits set are always respected during operation.
For example, with a nominal voltage of 24 V rms the maximum variations due to the transformer tolerance are ± 20% .
In order to limit (to the maximum value allowed) the current peak, which occurs in diodes during
switch-on, an external resistance RE,in series with the secondary of the transformer, must be introduced.
Supposing that the capacitor of the filter is discharged at switch-on, the following equivalent circuit can
be drawn:
Secondary voltage.
Secondary resistances of transformer.
Resistance produced by the diode pair involved in
conduction.
If values RT and RD are known RE is calculated in such a way that the peak current at switch-on does
not exceed 7 A.
Vs
peak
-7 (R T + R D )
7
For the 5V, with the nominal voltage of the 1 OV A transformer at 12V and with a total voltage variation
of ±15%, the transformer secondary is connected directly to pins 1 and 5.
For correct use of the device at 15V the graph in fig. 1 gives the max output current.
Fig. 1 - Guaranteed output
current vs. secondary voltage
I,
ImA )
RS"''''SJ-,
lp.,SA
Rs ,,4,fl.
.....r
1p=-7A
RsdA
60 0
IpaSA
500
Note:
40 0
JOO
2()0
~i:i=J:Ll"'''rr
'""V. t-: ~rf
K
I"
"0
1S
9
20
52
I
"
20.9
18,8
22
( 20 I.)
~~.'5V
l
23
(-15"1.)
Vs nom = 24.6 V rms for 220V ± 15%.
Vs nom'= 23.55 V rms for 220V ± 20%.
"
s (Vrms )
24.6
23.55
82
LINEAR INTEGRATED CIRCUIT
ADJUSTABLE VOLTAGE AND CURRENT REGULATOR
•
•
•
•
•
•
•
•
ADJUSTABLE OUTPUT CURRENT UP TO 2A (GUARANTEED UP TO T j = 150°C)
ADJUSTABLE OUTPUT VOLTAGE DOWN TO 2.85V
INPUT OVERVOL TAGE PROTECTION (UP TO 60V, 10 ms)
SHORT CIRCUIT PROTECTION
OUTPUT TRANSISTOR S.OA PROTECTION
THERMAL OVERLOAD PROTECTIOI\I
LOW BIAS CURRENT ON REGULATION PIN
LOW STANDBY CURRENT DRAIN
The L200 is a monolithic integrated circuit for voltage and current programmable regulation. It is
available in Pentawatt ® package or 4-lead TO-3 metal case. Current limiting, power limitinq, thermal
shutdown and input overvoltage protection (up to 60V) make the L200 virtually blowout proof. The
L200 can be used to replace fixed voltage regulators when hiqh output voltage precision is required and
eliminates the need to stock a range of fixed voltage regulators.
ABSOLUTE MAXIMUM RATINGS
Vi
Vi
t-,V i _o
10
P tot
Tstg
Top
DC input voltage
Peak input voltage (10 ms)
Dropout voltage
Output current
Power dissipation
Storage temperature
Operating junction temperature for L200C
for L200
MECHANICAL DATA
40
V
60
V
32
V
internally limited
internally limited
-55 to 150°C
-25 to 150
°C
-55 to 150°C
Dimensions in mm
83
6/82
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
5-2387! 2
Type
Pentawatt®
TO-3
L 200 T
L 200
L 200 C
L 200 CT
L 200 CH
L 200 CV
BLOCK DIAGRAM
------
~5
1
0>----+--
OUTPUT
INPUT
\CURRENT
/LiMITING
2
GROUND
5·3928
84
SCHEMATIC DIAGRAM
I
R8
Z2
Z3
RI5
R9
R26
R21
0/ 08
03
021~
0/015
026
O~
014
RI4
RIO
~
01
C~
02
RII
,~[IJ"' ~5
o
~
03
411
R13
,~[ ~
ZI
U.
18
'""0' 22
-,
j
R
19
R
20
F
R
22
02~~
r
R
17
0/027
Q29
R
23
0-
020
017
R29
>--t::1023t-- K028
f-----
019
R28
030
l
~~ I
03~ ~J3
27
2
R24
5
{I!
~'
RI
R2
HI~" :A
010
R4
R6
025
1
~
RI2
R7
R
16
18
R25
THERMAL DATA
Rth j-case
Rth j-arnb
TO-3
Thermal resistance junction-case
Thermal resistance junction-ambient
Gl
5-2385
max
max
4°C/W
35°C/W
Pentawatt®
3°C/W
50°C!W
ELECTRICAL CHARACTERISTICS (T arnb = 25°C, unless otherwise specified)
Parameter
Test conditions
VOLTAGE REGULATION LOOP
Id
Quiescent drain current (pin 3)
Vi = 20V
eN
Output noise voltage
Vo= V ref
4.2
9.2
rnA
10= 10mA
B = 1 MHz
80
Vo
10=10mA
loVo
Voltage load regulation
(note 1)
lolo= 2A
lol o=1.5A
Line regulation
Vo= 5V
Vi = 8 to 18V
48
60
dB
Vo= 5V
10= 500mA
loVi= 10 Vpp
f = 100 Hz (note 2)
48
60
dB
Vo
loV i
-loVo
SVR
Supply voltage rejection
2.85
/LV
Output voltage range
0.15
0.1
85
36
V
1
0.9
%
%
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
Min.
1:1 V i- o
Droupout voltage between
pins 1 and 5
10 = 1.5A
I:1 V o
V ref
Reference voltage (pin 4)
Vi = 20V
10=10mA
1:1 V ref
Average temperature
coefficient of reference voltage
Vi = 20V
~
2%
2.64
10 = 10mA
for T j = -25 to 125°C
forTj= 125to 150°C
Typ.
Max.
Unit
2
2.5
V
2.77
2.86
V
-0.25
-1.5
mV/"C
mY/DC
10
14
Bias current at pin 4
3
1:114
I:1T·1 4
Average temperature
coefficient (pin 4)
-0.5
%/oC
Zo
Output impedance
1.5
mn
Vi = 10V
10= 0.5A
Vo= V ref
f = 100 Hz
Vi = 10V
Vo = V ref
IlA
CURRENT REGULATION LOOP
Vsc
Current limit senSe voltage
between pins 5 and 2
I:1 V se
1:1 T • V sc
Average temperatu re
coefficient of V sc
1:110
Current load regulation
-10
Ise
Peak short circuit current
0.38
15= 100 mA
V j =10V
10 = 0.5A
10 = 1A
10= 1.5A
0.45
0.52
V
0.03
%/"C
1.4
1
0.9
%
%
%
I:1Vo= 3V
Vi- V o=14V
(pins 2 and 5 short circuited)
3.6
A
Note 1):
A load step of 2A can be applied provided that input-output differential voltage is lower than 20V (see
fig. 1).
Note 2):
The same performance can be maintained at higher output levels if a bypassing capacitor is provided between pins 2 and 4.
86
Fig. 1 - Typical safe oper·
ating area protection
Fig. 3 - Quiescent current
vs. junction temperature
Fi!l. 2 - Quiescent current
vs. supply voltage
'd
(',1846
'H-t
H- +++v, .,,:
(rnA
"'h.
++-
4,Omammmw
3.8
I
""I.
,
,
!
•.
:~
Fig. 5 - Output noise voltage
vs. output voltage
r-
r-....
I
-
!
~
-~
-,......
T
\
I
I
I
I
.<0
20
Fig. 4 - Quiescent current
vs. output current
!
_. :.......
,
I
:
T~t~
~+ .. j l--~t'
3.6
I'
L_
.
' i i -'-+:
I vo~vr"
i
80
40
Fig. 6 - Output noise voltage
vs. frequency
G-:l831
'0
,
'N
(PVRMS
(rnA)
1.6
200
1.4
II I!I
ii, :
H•
1.2
i~:
! ,
: '
r~
I
!
'SO
0.8
0.6
B "lMHz
100
0.4
f-t
I
2
1.6
12
,
10
15
I-
6-1848
,
I
I
'1::' .20V-~
I
"
I' I
,
t--
2180
~--+--
-- i""'-
2160
5VR
(de)
I
I
111I11I11
Vi ;15VOC.2VRM5
10 "lOrnA
I
80
7S
65
60
2120
55
50
-"0
40
87
60
120
Tj (OC)
I
I
,
i
I
I
II
!
2100
III
Vo ,,'I ref
16
70
00
I
65
!\
-40
,
I
I
12
I
f (Hl'.:l
I
,,
2140
i
I
('-1849!2
0'0
~
~
f1I . I
I I
Fig. 9 - Supply voltage rejection vs. frequency
(mV)
J, II---t-1TA
i P=~
Vo"Vref
I
10'
'10 (v)
Fig. 8 - Voltage load regulation vs. junction temperature
Fig. 7 - Reference voltage
vs. junction temperature
,
I
I
0
lo(A)
,I
T'=75°C
r""2S'c
1--' .
50
0.8
,
Tj"I50°
0.2
04
I
"1
I
i
I
T
B:l00H:;o:
Vo=:Vref
I
i
'"
i I"
i
!I
II
'"10'
1
""
~
1468
10'
1
".a
f {Hz}
Fi~. 12 - Output impedance
vs. output current
Fig. 11 - Output impedance
vs. frequency
Fig. 10 - Dropout voltage
vs. junction temperature
C.-2845
I
Vo =Vrl'f
5.5
~
45
.
i--'T
i
3.5
V
.....
2.
2.5
.-
~=2"1.
v.
,
"-
LS'
1.5
!.
n!.
0.5
40
80
120
I
H=f
f---
It
j.
!
-20
-40
.. 0
o
h-l
o
(,-1861/1
+
~t-H
I
,
-HJ_i-
t
F~f
=O;-I-C2--4-~O
2
I
10:= lOrnA to lA
'
+0
+ ~
3
Vi=10V
-
-
~.
1
L=mf
Jfh=!t' 1:
.,
Vo =5.5V • Vj-=lOV
--,.-
(
.'
h- rt
[0 (Al
Fig. 14 -- Load transient response
Fig. 13 - Voltage transient
response
)
1.5
0.5
Tj ("C)
4
5
6
7
8
9
5-2386/1
t (,us)
Fig. 16 - Current limit sense
voltage. vs. junction temperature
Fig. 15 - Load transient response
Vi :.lOV
10 " lOrnA to lA
U"'O-t-t---co" '/-IF
5- 2388/1
88
i
APPLICATION CIRCUITS
Fig. 17 - Programmable voltage regulator
>
Fig. 18 - P.C. board and components layout offig. 17
(1 : 1 scale)
I
J _.1
CAD
Fig. 19 - Programmable voltage regulator with
current limiting
Cl
Fig. 20 - Programmable current regulator
Io(max)= V:;2
vo=vr€"
(1.~ )
0.22
Y,
"F
Fig. 22 - Digitally selected regulator with
inhibit
Fig. 21 - High current voltage regulator with
short circuit protection
lkn
s-
253912
89
APPLICATION CIRCUITS
Fig.24 - High current regulator with NPN
pass transistor
Fig. 23 - Tracking voltage regulator
BOWSl
!
Roo
Y\,
I
I,
1011
,
v
>---'-
L 200
2
3] 820 n]4
~lkn
BC~
10k'll
'r
=:o.,,"Fl
0.47"F
==
A: Vi(max)"; ± 34V ; 3 < Vo < 30.
B: Vi(max)"; ±22V ;3-
9
1
TTL OUTPUT
CMOS OUTPUT
Fig. 11 - Peak collector current as a function fo duty
cycle and number of outputs
Fig. 10 - Collector current
vs. collector emitter saturation voltage
Fig. 9 - DC current gain. vs.
collector current (for L 201)
G-1162
'e
\\
\'
(mA )
"0
,
I
/
I
10'
',,,
VCE~~
!
-
300
300
roo
-
~
,
"-' .........
'\.
"-,.
~6
"-
7~
f' ........
"'""
'00
~
''';:::
Tamo ,,70'C
100
100
i
10'
10
j'
II
'0'
0.5
Ie (rnA)
Fig. 12 - Input current vs.
input voltage (for L 202
and L 204)
1.5
VCE(~)M
;
-++
3.'
,
>.6
,
'.4
IC"~
'20'
L6
L2"Y
I
OA
I
0 ('/.)
(,-2165
"
(mA )
I
I
80
Fig. 14 - Power rating chart
Fig. 13 - Input current vs.
input voltage (L 203)
(',_2164/1
I
"
(rnA )
60
0.8
..-:: ~
t5
h V
~
~ Ie =350o:nA
0.6
0.'
•
•
0.3
I
"
16
20
30
24 Vi (v)
97
60
90
120
150
lamb ("C)
LINEAR INTEGRATED CIRCUIT
TACHOMETER CONVERTER
The L290, a monolithic LSI circuit in a 16-lead dual in-line plastic package, is intended for use with the
L291 and L292 which together form a complete 3-chip DC motor positioning system for applications
such as carriage/daisy-wheel position control in typewriters.
The L290/1/2 system can be directly controlled by a microprocessor. The L290 integrates the following
functions:
- tacho voltage generator (FIV converter)
reference voltage generator
- position pulse generator.
ABSOLUTE MAXIMUM RATINGS
vs
± 15
±7
1
-40 to +150
Supply voltage
VI (FTA, FTB, FTF) Input signals
Ptot
Tstg' TJ
Total power dissipation Tamb = 70°C
Storage and junction temperature
V
V
W
°C
ORDERING NUMBER: L290 B
Dimensions in mm
MECHANICAL DATA
6182
98
CONNECTION DIAGRAM
(top view)
FTB
16 FTA
VAB
15 VAA
Vre-t
14 STA
TACHO 4
13
'V s
12 FTF
Vbias.
srB
11 GND
6
VMB
10 STF
VMA
9
-Vs
5 - lo 159
BLOCK DIAGRAM
11
Vbias
GNO i
"VS:
, 6 FTA
TACHO
~
FTS
11.. STA
13
FTF
STF
STS
VrE'f
VAA
15
VAS
VMS
VMA
7 8
99
5- 41L.
312
4
12
10
TEST CIRCUIT
- Vs
FTA
,V s
TACHO
.5V
I
3x2.5K!t
'6
FTB
L 290
,4
STA
, 3
STB
FTF
STF
VMB
OVMA
2x820 n
+'.8V
-'.8V
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
80
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, S in (A), Vs = ± 12V,Tamb = 25°C
unless otherwise specified)
Parameters
Vs
Supply vol tage
Id
Quiescent drain current
Test conditions
Min.
Typ.
±10
13
Vs=±15V
Max.
Unit
±15
V
20
mA
±0.6
Vp
± 55
mV
INPUT AMPLIFIERS (AI and A 2 )
FTA, FTB
I nput signal from encoder
(pin 1, 16)
f max = 20 KHz
Vos
Output offset voltage
(pin 2,15)
FTA = FTB = OV
Ib
I nput bias current (pin 1, 16)
Gv
Voltage gain
f = 10 KHz FT A=FTB=±0.6V p
Vo
Output voltage swing
(pin 2, 15)
FTA= FTB= ± 1 Vp
±0.4
0.15
100
22
±9.5
23
IJA
24
dB
V
i
I"
~
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameters
I,
COMPARATORS WITH HYSTERESIS (C I , C2 and C3 )
VTHP(O)
VTHN(oo)
VL
Ileak
Positive Threshold voltage
(pin 2. 12. 15)
Negative Threshold voltage
(pin 2. 12, 15)
C I and C 2
550
850
rnV
C3
700
900
rnV
C I and C2
55
175
rnV
C3
570
830
rnV
0.4
V
1
/J.A
5.5
V
1.4
rnA
± 80
rnV
Output voltage (low levell
(pin 10.13,14)
10 = 2 rnA
0.2
(pins 10, 13, 14)
FT A= FTB= 0.5V
FTF= 1V
V CE= 5V
FT A= FTB= FTF= OV
REFERENCE GENERATOR
FTA= FTB= ± 0.5V p (*)
I ref = 1 rnA
V ref
DC reference voltage
(pin 3)
Iref
Output current (pin 3)
4.5
5
"TACHO" AMPLIFIER (A 3 )
Vos
Vo
Output offset voltage (pin 4)
FTA= ± 15 rnV FTB= 0.5V
DC output voltage (pin 4)
!',V o
Vo
FTA= FTB= ±0.5Vp
(**)
Vol
V MA= V MB = ±1.25V p
(*")
V 02
I
S in (B)
V MA
V MB
Multiplier input voltage
(pin 7,8)
V bias
Bias voltage (pin 6)
(0 )
FT A = FTB = FTF = 0
Note : Phase relationship
* FT A : 00
FTA : 00
*** FTA: 00
f
I
6
6.6
-5.4
-6
-6.6
V
-150
Vol + V 02
Output voltage swing (pin 4)
5.4
FTA= FTB= 0.5V
9
FTA= FTB= -0.5V
-9
+150
V
± 1.25
FT A and FTB floating
IV
(00)
FTA=FTB=FTF=
between the signals:
FTB : 900
FTB: _90 0
FTB: 900
101
rnV
-6.5
± 1.7
Vp
-8
V
i
WAVE FORMS (Neglecting threshold voltage level of the comparators)
ANTICLOCKWISE
DIRECTION
CLOCKWISE
DIRECTION
Wi;
t'
I
i
VAA
~VAA
h~VAB
VAB
CS1
CS1
CS2
, CS2
VMA
! VMA
~~'-'-'-VM:..::...B_
Yr:
~
CSB
~C5B
CSA
~CSA
i VMB
~
I
~TACHO
TACHO
~
SYSTEM DESCRIPTION: refer to the L292 data sheet
102
5-4156/1
Fig. 1 - Complete application circuit
FAOt04
ENCOOER
Speed
"OK.
L291
1 SO
10,",0j)
FRO'"'
,uPROCESSOR
'"
ISlI.n
16
", ~ -',
hC10 e'l
I Ol~
Strobli!'
1511.0.
0.1",
~
",
12
·12
-'.
103
ON(Hl
OFF(Ll
LINEAR INTEGRATED CIRCUIT
5 BIT - D/A CONVERTER AND POSITION AMPLIFIER
The L291, a monolithic LSI circuit in a 16-lead dual in-line plastic package, is intended for use with the
L290 and L292 to form a complete 3 chip DC motor positioning system for applications such as carriage/
daisy-wheel position control in typewriters.
The L290/1/2 system can be directly controlled by a microprocessor.
The L291 integrates the following functions:
5 bit 0/ A converter
error amp Iifier
position amplifier
(~
LSB max linearity error)
ABSOLUTE MAXIMUM RATINGS
±15
1
-40 to 150
Supply voltage
Total power dissipation T amb = 70°C
Storage and junction temperature
v
w
°C
ORDERING NUMBER: L291 B
Dimensions in mm
MECHANICAL DATA
6/82
104
CONNECTION DIAGRAM
(top view)
ERRV
1
16 POS lOUT
SC ,
15
POSIIN
SC 2
14
.V s
SC J
13
GND
SC 4
12
DACIOUT
SC 5
11
N.C
SIGN.
10
Strobe 8
-Vs
DAC liN
5-4160
BLOCK DIAGRAM
,J
14
SC'
SC2
-".
SCJ
SCI.
SC5
DIA
CONY,
~D--+--~ '6
POSIOUT
SIGN
Strobe
OAC/IN
DACfOUT
ERRV
12
POS/IN
1
105
15
S-t,157/1
TEST CIRCUIT
5c,00 8 2
5C2
5C)
L291
5C4
5C5
StrobeQ-50n
5'
s- 41 581l
:L ~
52
al ~.t
b
Otl00mV
2,l. V
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
80
°C/W
± 12V,
ELECTRICAL CHARACTERISTICS (Refer to the circuit, Sl and S2 in (a). Vs
Tamb = 25°C, unless otherwise specified)
Parameters
Vs
Supply voltage
Id
Quiescent drain current
Test conditions
Min.
Typ.
± 10
Vs = ± 15V
6.5
Max.
Unit
± 15
V
10
mA
POSITION AMPLIFIER
V strobe Enable voltage level
V L (S in (a)) •
0
0.8
V
V H (S in (b)) •
2.4
+Vs
V
± 50
mV
0.3
IJA
Vos
Output offset voltage (pin 16)
V strobe= V L; G v = 20 dB
Ib
Input bias current (pin 15)
Vstrobe= V L
Vo
Output voltage swing (pin 16)
Vstrobe=VL; S2 in(b); Vs=±10.8V
VR
Residual output voltage (pin 16)
Vstrobe= V H
• See block diagram and the note for Position Amplifier.
106
V
±9
± 20
mV
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
D/A CONVERTER
I ref
Current reference input range
(pin 91
Vas
Current reference offset voltage
(pin 91
10
Output current range (pin 121
10
Output current (pin 121
LIla
0.3
Iref= 0.3 to 1.2 mA
All inputs high
I ref = 0.722 mA
SC1 to SC5 = L
1.2
mA
± 20
mV
1.4
mA
SIGN = L (1011
-1.358
-1.4
-1.442
SIGN = H (1021
-1-1.358
+1.4
+1.442
mA
-21
101 + 102
+21
!J.A
%FS
Linearity error
I ref = 0.722 mA
1.61
los
Pin 12 output offset current
(including Error Amplifier bias
currentl
All inputs high
± 0.4
!J.A
VL
Low voltage level (digital inputsl
0
0.8
V
VH
High voltage level (digital inputsl
2.4
+VS'
V
IL
Digital inputs current (low statel
V L = O.4V
-50
!J.A
IH
Digital inputs current (high statel
V H = +Vs
1
!J.A
± 200
mV
± 5
mA
± 8.4
Vp
SC1 = LSB
SC5 = MSB
ERROR AMPLIFIER
Vas
Output offset voltage (pin 11
I ref = 0.5 mA; All inputs high
G v = 40 dB
10
Output current (pin 11
Va
Output voltage swing (pin 11
All inputs high
S1 in (bl; R L =10Kn
107
±7.4
D/A Converter
The L291 contains a 5-bit D/A converter accepting a binary code and generating a bipolar output
current, the polarity of which depends on the SIGN input. The amplitude of the output current is a
multiple of a reference current Iref .
The maximum output current is
I FS = +
-
31
I
~ ref
The following table shows the value of 10 for different input codes. Note that the input bits are active
low.
DIGITAL INPUT WORD
Output Current
SIGN
SC5
SC4
Se3
Se2
Se1
L
L
L
L
L
L
10
-~
16
1
I ref
L
H
H
H
H
L
-"""""i"6 I ref
X
H
H
H
H
H
0
H
H
H
H
H
L
+ _1- lref
H
L
L
L
L
L
+
16
31
"""""16 I ref
X = indifferent
L = low
H = high
This D/A converter has a maximum linearity error equal to ± 1/2 LSB (or ± 1.61% Full Scale); that gua:
rantees its monotonicity.
Error Amplifier
In order to have a good stability, the Error Amplifier must work with a closed loop gain greater or equal
than 20 dB.
Position Amplifier
It is inserted by means of the strobe signal, TTL and microprocessor compatible. Its output is connected
to pin 16 when Vstrobe= Low; pin 16 is grounded for Vstrobe= High.
SYSTEM DESCRIPTION: refer to the L292 data sheet.
108
Fig. 1 - Complete application circuit
109
LINEAR INTEGRATED CIRCUIT
SWITCH-MODE DRIVER FOR DC MOTORS
The L292 is a monolithic LSI circuit in 15-lead MUL TIWATT® package. It is intended for use, together
with L290 and L291, as a complete 3-chip DC motor positioning system for applications such as carriage/daisy-wheel position control in typewriters.
The L290/1/2 system can be directly controlled by a-microprocessor. The outstanding characteristics
of the L292 are:
Singie power supply (18 to 36V).
Input signal symmetric to ground.
Thermal protection.
Driving capability: 2A, 36V, 30 KHz.
2 Logic chip enable.
- External loop gain adjustment.
-
ABSOLUTE MAXIMUM RATINGS
Vs
VI
V inhibit
Ptot
T 519
36
-15 to +Vs
o to Vs
25
-40 to +150
Power supply
Input voltage
Inhibit voltage
Total power dissipation (Tcase= 75°C)
Storage and junction temperature
V
V
V
W
°C
ORDERING NUMBER: L292
Dimensions in mm
MECHANICAL DATA
6/82
110
CONNECTION DIAGRAM
(top view)
MOTOR
Rs2
INHIBITCCEll
INHIBIT(m)
OSCILL.(R)
OSCILL.(C)
OUTPUT(ERR.AMPU
GNO
INPUT(ERR.AMPL.)
15
"
13
12
11
10
9
INPUT
OUTPUT C.S.A.
COMP. INPUT
'\'0
Rsl
MOTOR
5-3673
BLOCK DIAGRAM
'Vs
slon
.5,
c
r - - - - - - - - - - - - - - -- - - - - - - - - -
!---------- ~-.
L292
,,
VI : 6
03
RI
.,
lnF
,
04
I
!L. ________________________________ _
5_4168
High speed diodes (BYW 72 or equivalent)
111
THERMAL DATA
Rth j-case'
Thermal resistance junction-case
max
3
°C/W
ELECTRICAL CHARACTERISTICS (T amb = 25°C, fosc= 20 KHz unless otherwise specified)
Parameter
Test conditions
Vs
Supply voltage
Id
Quiescent drain current
V s = 20V (offset null)
Vos
Input offset voltage (pin 6)
Vs = 36V
V inh .
Inhibit low level (pin 12,13)
Typ.
18
30
10 = 0
Inhibit high level (pin 12, 13)
Max.
Unit
36
V
50
mA
±350
mV
2
V
3.2
Low voltage condition
V inh . (L)= O.4V
High voltage conditions
V inh . (H)= 3.2V
Ii
Input current (pin (6)
VI = -8.8V
VI = +8.8V
Vi
Input voltage (pin 6)
linh.
Min.
V
-100
Il A
10
Il A
-1.8
0.5
mA
mA
10= 2A
9.1
V
10= -2A
-9.1
V
Rsl = R s2 =0.25]
10
Output current
V D·
Total drop out voltage
VI = ±9.8V
RSI = R s2 = 0.25]
(inluding
±2
A
10= 2A
5
V
resistors)
10= lA
3,5
V
Sensing resistor voltage drop
T j = 150°C
10= 2A
0.44
V
Transconductance
Rsl = R s2 = 0.2n
235
mA/V
sensing
V RS
i
10
-Vi
205
120
Rsl = R s2 = O.4n
Frequency range (pin 10)
fosc
1
TRUTH TABLE
Vinhibit
Pin 12
Pin 13
L
L
H
H
L
H
L
H
Output stage
condition
Disabled
Normal operation
Disabled
Disabled
112
220
mAN
30
KHz
I
SYSTEM DESCRIPTION
I
I
The L290, L291 and L292 are intended to be used as a 3-chip microprocessor controlled positioning
system. These devices may be used separately - particularly the L292 motor driver - but since they will
usually be used together, a description of a typical L290/1/2 system follows.
Fig. 1 - System block diagram
The system operates in two modes to achieve high-speed, high-accuracy positioning.
Speed commands for the system originate in the microprocessor. It is continuously updated on the
motor position by means of pulses from the L290 tachometer chip, which in turn gets its information
from the optical encoder. From this basic input, the microprocessor computes a 5-bit control word
that sets the system speed dependent on the distance to travel.
When the motor is stopped and the microprocessor orders it to a new position, the system operates
initially in an open-loop configuration as there is no feedback from the tachometer generator. Therefore
maximum current is fed to the motor. As maximum speed is reached, the tachometer chip output backs
off the processor signal thus reducing accelerating torque.
The motor continues to run at top speed but under closed-loop control.
As the target position is approached, the microprocessor lowers the value of the speed-demand word;
this reduces the voltage at the main summing point, in effect braking the motor. The braking is applied
progressively until the motor is running at minimum speed.
At that time, the microprocessor orders a switch to the position mode, (strobe signal at pin 8 of L291)
and within 3 to 4 ms the L292 drives the motor to a null position, where it is held by electronic
"detenting" .
113
SYSTEM DESCRIPTION (continued)
The mechanical/electrical interface consists of an optical encoder which generates two sinusoidal signals
90° out of phase (leading or lagging according to the motor direction) and proportional in frequency to
the speed of rotation. The optical encoder also provides an output at one position on the disk which is
used to set the initial position.
The opto encoder signals, FT A and FTB are filtered by the networks R2 C2 and R3 C3 (referring to
Fig. 4) and are supplied to the FT A/FTB inputs on the L290.
The main function of the L290 is to implement the following expression:
Output signal (TACHO) =
d~AA
FTA
IFTAI
FTB
IFTBI
•
Thus the mean value of TACHO is proportional to the rotation speed and its polarity indicates the
direction of rotation.
The above function is performed by amplifying the input signals in Al and A2 to obtain VAA and
VAB (typ. 7 Vp ). From VAA and VAB the external differentiator RC networks Rs Cs and R4 C4 give
the signals V MA and V MB which are fed to the multipliers.
.
The second input to each multiplier consists of the sign of the first input of the other multiplier before
differentiation, these are obtained using the comparators CSI and CS2 ' The multiplier outputs, CSA and
eSB, are summed by A3 to give the final output signal TACHO. The peak-to-peak ripple signal ofthe
T ACHO can be found from the following expression:
V ripple
P-i>
=
-%-(..[2 - 1)
• V thace
DC
The max value of TACHO is:
Vtache max = :
V2'
Vthaco
DC
Using the comparators C 1 and C2 another two signals from VAA and VAB are derived - the logic signals
STA and STB.
These signals are used by the microprocessor to determine the position by counting the pulses.
The L290 internal reference voltage is also derived from V AA and VAB:
V ref == I VAA I
+
I VAB I
This reference is used by the 0/ A converter in the L291 to compensate for variations in input levels,
temperature changes and ageing.
The "one pulse per rotation" opto encoder output is connected to pin 12 of the L290 (FTF) where it is
squared to give the STF logic output for the microprocessor.
The T ACHO signal and V ref are sent to the L291 via filter networks Rs Cs Rg and Rs C7 R7 respectively.
Pin 12 of this chip is the main summing point of the system where T ACHO and the 0/ A converter out·
put are compared.
The input to the O/A converter consists of 5 bit word plus a sign bit supplied by the microprocessor.
The sign bit represents the direction of motor rotation. The (analogue) output of the 0/ A converter OAC/OUT - is compared with the TACHO signal and the resulting error signal is amplified by the error
amplifier, and subsequently appears on pin 1.
114
SYSTEM DESCRIPTION (continued)
The E RRV signal (from pin 1, L291) is fed to pin 6 of the final chip, the L292 H-bridge motor-driver.
This input signal is bidirectional so it must be converted to a positive signal because the L292 uses a
single supply voltage. This is accomplished by the first stage - the level shifter, which uses an internally
generated BV reference.
This same reference voltage supplies the triangle wave oscillator whose frequency is fixed by the external
RC network (R 20 , C ll - pins 11 and 10) where:
fo,c
=
1
2RC
(with R > B.2 K.II.)
The oscillator determines the switching frequency of the output stage and should be in the range 1 t030
KHz.
Motor current is regulated by an internal loop in the L292 which is performed by the resistors RIB' RIg
and the differential current sense amplifier, the output of which is filtered by an external RC network
and fed back to the error amplifier.
The choice of the external components in these RC network (pins 5, 7,9) is determined by the motor
type and the bandwidth requirements. The values shown in the diagram are for a 5.11., 5 mH motor.
(See L292 Transfer Function Calculation in Application Information).
The error signal obtained by the addition of the input and the current feedback signals (pin 7) is used
to pulse width modulate the oscillator signal by means of the comparator. The pulse width modulated
signal controls the duty cycle of the H-bridge to give an output current corresponding to the L292
input signal.
The interval between one side of the bridge switching off and the other switching on, T , is programmed
by C ll in conjunction with an internal resistor Rr .
This can be found from:
T =
Rr ' Cpin
(C ll in the diagram)
10'
Since Rr is approximately 1.5 K.II. and the recommended T to avoid simultaneous conduction is 2.5 I1S
Cpin 10 should be around 1.5 nF.
The current sense resistors RIB and RIg should be high precision types (maximum tolerance ± 2%) and
the recommended value is given by:
Rmax • 10 max';; 0.44V
It is possible to synchronize two L292's, if desired, using the network shown in fig. 2.
Fig. 2
,--1" L292
L-l
11
tf
.R
1.
" - 1.1lt.
Finally, two enable inputs are provided on the L292 (pins 12 and 13-active low and high respectively).
115
SYSTEM DESCRIPTION (continued)
Thus the output stage may be inhibited by taking pin 12 high or by taking pin 13 low. The output will
also be inhibited if the supply voltage falls below 18V.
The enable inputs were implemented in this way because they are intended to be driven directly by a
microprocessor. Currently available microprocessors may generates spikes as high as 1.5V during powerup. These inputs may be used for a variety of applications such as motor inhibit during reset of the
logical system and power-on reset (see fig. 3).
Fig. 3
I
Fig. 4 - Application circuit
FROM
C,
15nF
R le
0.220.
RI9
t-0._22_n~~~~~~~L::.:2::.:9:..:2::,
I
D,
f
'I
,D3
1~,}~n5n
C1S
I
lnF
0'1' 0,
FROM
.uPROCESSOR
4xlN4001
~---wt=5j---;PF'---tc=='--
R"
ISKJl
+ Ys
GNO
~Vs
116
ON(H)
QFF(L)
1
M 5mH
APPLICATION INFORMATION
This section has been added in order to help the designer for the best choise of the values of external
components.
.Vs
Fig. 5 - L292 block diagram
47nF
C
7
9
3
-------------
D3
InF
D'
5-4168
The schematic diagram used for the Laplace analysis of the system is shown in fig. 6.
Fig. 6
Vi
,I....._ _.J
I CURRENT
I
I FILTER
I
L _ _ _ _ _ _ _l
5- 1,17611
I SENSING
I'- AMPLIFIER
_______1
RSI = RS2 = Rs (sensing resistors)
_1_ = 0.005 n -1 (current sensing amplifier transconductance)
R4
LM = Motor inductance
RM = Motor resistance
1M = Motor current
Gm- o -1M
--VTH
I
S =
0
(DC transfer function from the input of the comparator (V TH) to the· motor cur·
rent (1M)).
117
APPLICATION INFORMATION (continued)
Neglecting the V CEsat of the bridge transistors and the V BE of the diodes:
where:
Vs = supply voltage
V R = 8V (reference voltage)
(1 )
DC transfer function
In order to be sure that the current loop is stable the following condition is imposed:
1 + sRC = 1 + S LM
RM
from which RC =
(pole cancellation)
~
(2)
(Note that in practice R must be greater than 5.6 Kn)
RM
The transfer function is then,
~ (s) =
VI
R2 R4
RIR3
G mo
1 + sRFC F
GmoRs+sR4C+s2RFCFR4C
(3)
In DC condition, this is reduced to
-.!.M...
(0) =
VI
0.044
R2 R4
RI R3
Rs
[..A..l
VJ
(4)
Open-loop gain and stability criterion
For RC
= LM/R M, the open loop gain is:
A
{3
=
1
SRFC
•
G
Rs
mo ~
(5)
In order to achieve"good"stability, the phase margin must be greater than 45° when IA J3I = 1.
That means that, at fF = 2 7r ~FCF ,must be IA {31
< 1 (see fig. 7), that is
Gmo Rs
R4 C
Fig. 7 - Open-loop frequency response
IAJ31
OdB,+_ _ _ _ _~;:--.;..
118
RFC F
~
<1
(6)
APPLICATION INFORMATION (continued)
Closed-loop system step response
a) Small-signals analysis.
Fig. 8 - Small signal step
response (normalized amplitude vs. t/RFC F )
The transfer function (3) can be written as follows:
1+ 2~
I
0.044
~(s)= - - -
VI
s
G-4J';l
Wo
1 + 1!~ +
Rs
Wo
where:
=
Wo
j
(7)
4-
'S=1I..fT
Wo
0.9
/
~----
Rs
R4 C RFC F
Gmo
is the cutoff frequency
,/ II
0.6
0.3
I.
5"'
I
I
/
II
I
"
By choosing the ~ value, it is possible to determine the system
response to an input step signal. Examples:
Fig. 9 - Motor current and pin 7 voltage
waveforms (application of fig. 5). Small
signal response
1)~=1
from which
OV
___
t_
1M
(t)
=
0.044 [1 - e 2R FC F (1 + 4 RtFC F ) 1• Vi
Rs
(where Vi is the amplitude of the input step).
2) ~ =
1
'1'2
1M
(t) =
from which
t
0.044 (1 - cos
t
e
Rs
2R FCF
2R F CF )V;
OA
V 7 = 200mV/div.
1M = 100mA/div.
t
= 100/ls/div.
with VI = 1.5 Vp.
From fig. 9, it is possible to verify that the L292 works in "closed-loop" conditions during the entire
motor current rise-time: the voltage at pin 7 (inverting input of the error amplifier) is locked to the
reference voltage V R, present at the non-inverting input of the same amplifier.
The previous linear analysis is correct for this example.
Decreasing the ~ value, the rise-time of the current decreases. But for a good stability, from relationship
(6), the minimum value of ~ is:
1:.=_1_
min
2
(phase margin = 45°)
W
119
APPLICATION INFORMATION (continued)
b) Large signal response
The large step signal response is limited by slew-rate and inductive load.
In this case, during the rise-time of the motor current, the L292 works in open-loop condition, as
can be seen from the photograph of fig. 10.
Fig. 10 - Motor current and pin 7 voltage waveforms
(application of fig. 5) Large signal response.
OV
V7
1M
t
1V/div.
0.5A/div.
500"s/div.
OA
The voltage at pin 7 (inverting input of the error amplifier) departs from the reference voltage V R
present at the non-inverting input and the feedback loop is open.
The fed back loop is on when the motor current reaches its steady-state value (2A).
Closed loop system bandwidth
A good choice for ~ is the value 1/V2.ln this case:
~ (s)
VI
= 0.044
Rs
1 + s RFC F
1 + 2s RFC F + 2s 2 R F 2C F 2
(8)
The module of the transfer function is:
0.044
Rs
2
.J 1 + w
2
V [ (1 + 2 w R F C F )2 + 1 ]
RF2 C F 2
• [(1 - 2
The cutoff frequency is derived by the expression (9) by putting
Wr =
0.9
RFC F
120
w R F C F )2
(9)
+ 1]
I ~~ 1= 0.707 (-3 dB). from which:
APPLICATION INFORMATION (continued)
Example:
a) Data
b) Calculation
-
Motor characteristics:
-
Voltage and current characteristics:
V 5 = 20V
1M = 2A
-
Closed loop bandwidth: 6 KHz.
-
From relationship (4):
LM = 5 mH
RM =50
LM/RM = 1 msec
and from (1):
G
'rno-
RC = 1 msec
Assuming
2Vs
RMV R
,.
[from expression (2) ].
~ = 1/...(2; from (7) follows:
p = 1.-. =
2
c) Summarising
1~-1
-
The cutoff frequency is:
-
RC = 1 • 10-3 sec
500 C = 1
RFCF
RFC F ~ 24 "sec
}
200 C
4 RFC F • 0.2
C = 47 nF
R = 22 Ko
For RF = 5100 -+ CF = 47 nF.
NOTE - "For a more detailed description of the L290-L291-L292 and its applications
refer to SGS - TECHNICAL NOTES TN 149 and TN150.
121
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
PUSH-PULL FOUR CHANNEL DRIVERS
The L293 and the L293E are monolithic integrated high voltage, high current four channel drivers in
dual in-line plastic package with 16 leads and 20 leads respectively. They are designed to accept standard
DTL or TTL input logic levels and drive inductive loads (such as relays, solenoids, DC and stepping
motors) and switching power transistors.
Both are provided of complementary push-pull output stage, two inhibit inputs (which disable two
channels each), and an additional supply inputs so that the logic circuitry may run at a lower voltage to
reduce power dissipation.
In the L293E the emitters of the lower transistors of each push-pull stage are not internally grounded
and the corresponding pins can be used for the connection of an external sensing resistor, making very
easy switch-mode current control.
.
The main features of the L293 and of the L293E are:
1A output current capability per channel
2A peak output current (non-repetitive) per channel
Inhibit facility
Overtemperature protection
Logical "0" input voltage up to 1.5V (high noise immunity).
The devices are assembled in new packages which have the four central pins connected together and used
for heatsinking and grounding.
ABSOLUTE MAXIMUM RATINGS
Vs
Vss
Vi
V inh
lout
Ptot
Tstg , Tj
Supply voltage
Logic supply voltage
Input voltage
Inhibit voltage
Peak output current (non-repetitive)
Total power dissipation at TgrOUnd-Pins= 800C
Storage and junction temperature
ORDERING NUMBERS:
V
V
V
V
A
5
W
-40 to 150
°C
L293B (16 leads)
L293E (20 leads)
MECHANICAL DATA
6/82
36
36
7
7
2
Dimensions in mm
122
CONNECTION AND BLOCK DIAGRAM (L293)
(top view)
CHIP ENABLE 1
16
INPUT 1
15
INPUT 4
OUTPUT 1
14
OUTPUT 4
V55
GNO
13
GN 0
GNO
12
GNO
OUTPUT 2
11
OUTPUT 3
INPUT
10
2
9
Vs
I NPU T 3
CHIP ENABLE 2
's
5 - 1,'69
CONNECTION AND BLOCK DIAGRAM (L293E)
(top view)
CHIP ENABLE 1
1
INPUT 1
V"
INPUT 4
OUTPUT 1
OUTPUT 4
SENSE 1
SENSE 4
GNO
GNO
GND
GND
SENSE 'I.
SENSE 3
OUTPUT 2
OUTPUT
INPUT 2
Vs
3
INPUT 3
10
+Vs
123
v
(2)
(0)
o
~
(12)
In the L293 these points are not externally available. They are internally connected to the ground (substrate).
Pins of L293
( ) Pins of L293E
5 - 51St,
I
Ii
~
I
THERMAL DATA
Rth j-case
Rth j-amb
max
max
Thermal resistance junction-case
Thermal resistance junction-ambient
14
80
°C/W
°C/W
ELECTRICAL CHARACTERISTICS (For each channel, Vs= 24V, Vss= 5V, Tamb = 25°C,
unless otherwise specified)
Parameter
Vs
Supply voltage
Vss
Logic supply voltage
Is
Total quiescent supply
current
Iss
Total quiescent logic
supply current
V iL
I nput low voltage
V iH
Input high voltage
Test conditions
Vi
Vi
Vi
Vi
=L
=H
=L
=H
10
=0
=0
36
V
36
V
V 1nh = H
2
6
V inh = H
V inh - L
16
24
V inh = H
44
60
V inh = H
16
22
V inh = L
16
24
1.5
Vss
> 7V
2.3
7
Low voltage input current
Vi - L
Vi - H
I nhibit low voltage
V inhH
I nhibit high voltage
mA
4
2.3
High voltage input current
mA
V
V
-10
p,A
100
/loA
-0.3
1.5
V
Vss ..; 7V
2.3
> 7V
2.3
Vss
7
V
-100
p,A
± 10
p,A
. Vss
High voltage inhibit
current
10
=0
=0
Unit
-0.3
liH
V inhL
linhH
10
10
Max.
Vss"; 7V
liL'
Low voltage inhibit current
Typ.
4.5
V ss
linhL
Min.
30
-30
VCEsatH Source output saturation
voltage
10
= lA
1.4
1.8
V
VCEsatL Sink output saturation
voltage
10
= -lA
1.2
1.8
V
2
V
VSENS
Sensing Voltage
(pins 4, 7,14,17) (**)
tr
Rise time
0.1 to 0.9 Va (*)
250
ns
tf
Fall time
0.9 to 0.1 Va (0)
250
ns
ton
Turn-on delay
0.5 Vi to 0.5 Va (")
450
ns
toff
Turn-off delay
0.5 Vi to 0.5 Va (")
200
ns
(*) See fig. 1.
(**) Referred to L293E.
125
TRUTH TABLE
Fig. 1 - Switching times
Vi (each channen
Vo
V inh . (00)
H
L
H
L
H
L
X (0)
X (0)
H
H
L
L
(0) High output impedance.
(00) Relative to the considerate channel.
Fig. 2 - Saturation voltage
vs. output current
Fig. 3 - Source saturation
voltage vs. ambient temperature
G- 4J4 5
veEs ...I
VCEsatH
(V)
I
(V)
Vs= 24'0'
;:::::; p-
sat H
G-4)47
veE sat L
~~·~V,-.~14~v~--L-+-~-4~
(V)
--
+ __+-----1
3 f---~in"h"";b,,,!I',V~""T5_V-t__
Vinhibit~V5S=5V
VeE
Fig. 4 - Sink saturation voltage vs. ambient temperature
i
----vl. ",I
Vinhibit" V55 " 5V
--
f-
/
-
......-:: ~ ~£satl
I
-t--1
1 0 " tSA
I
10 _1A
-
10 " O.SA
10 ",0.1 A
I
0.5
- 50
Fig. 5 - Quiescent logic
supply current vs. logic
supply voltage
(;-4398
'"
{rnA )
V,
I
-~4V
Fig. 6 - Output voltage vs.
input voltage
-" ,
f---
V
VOr--'~V'~'~'~4V~'--'--'---_~~~~
j----------j---t--+--+---
'II
V V
46
Fig. 7 - Output voltage vs.
inhibit voltage
VS-JCE sa;H
V1nh"HIGH
"
50
"55" Vi ,,5'0'
Vs '" 24'0'
Vss"Vinhibit ,,5V
-
Vi :LOW
50
-50
50
It-
1/
V
"'s-VeE sat H
/.f-Tamb:25 'c
_Tamb" 25'C
-125'C
-40'C
f--t--+--tH'-I+---12S• c
--40'C
I
42
iL
/
VeE sat l
I
I
to
20
30
..ss(V)
1..5
'.5
126
veE sat l
1.5
r--
APPLICATION INFORMATION
Fig, 8 - DC motor controls (with connection
to ground and to the supply voltage)
Fig, 9 - Bidirectional DC motor control
.v.
L_.....:==::;:;:;::;::;:~=:::tL--{)
vinh
5 - 5155
V inh
A
H
H
H
L
L= Low
Ml
Fast motor
stop
M2
B
H
Run
L
Fast motor
stop
X
Free running
motor stop
X
Free running
motor stop
H = High
C = H;
D=L
Turn right
V inh = H
C = L;
D=H
Turn left
V inh = L
C = X;
Run
L
Fast motor stop
C=D
X = Don't care
Fig, 10 - Bipolar stepping motor control
FUNCTION
INPUTS
L= Low
H = High
D=X
X = Don't care
• v,
O.22.IJF
06
05
ch
iLljlL2dOOmA
02
I"
0'
D1 - D8
127
Free running
motor stop
= 1N4001
APPLICATION INFORMATION
(continued)
Fig. 11 - Stepping motor driver with phase current control and short circuit protection
r--------------------------------------------------r-------r~--~~O.v.
I-----------------_t_~--t_----------O. 5 v·
V,o-~~----------------_f~,
V2o-~~~----------r_~F_~
L-~I-----~------------_t_--t__t_--~--~OV3
1
09
2xlN4148
012
Hi
KJl
+5Vo-----~~----~
R14
5-5166
D1 + D8: O.5A fast diodes (1N4001 or equivalent).
NOTE - For a more detailed description of the L293/L293E and its applications, refer to
SGS-TECHNICAL NOTE TN. 150.
128
MOUNTING INSTRUCTIONS
The Rthj-amb of the L293 and the L293E can be reduced by soldering the GND pins to a suitable copper
area of the printed circuit board or to an external heatsink.
The diagram of fig. 13 shows the maximum dissipable power Ptot and the Rthj-amb as a function of the
side "Q" of two equal square copper areas having a thickness of 351J. (see fig. 12). In addition, it is possible to use an external heatsink (see fig. 14).
During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
Fig. 12 - Example of P.C. board copper area
which is used as heatsink
Fig. 13 - Max. dissipable
power and junction to ambient thermal resistance vs.
size "Q"
COPPER AREA 35,u THtCKNESS
,
RIh
PtO!
,W)
·CIW)
r\
60
~hj- .. mb
'"""'.,-
r--.
.-~
6
--
- r--,
Ptot (lamb" 70·C)
10
20
2
40
30
I (mm)
P.C. BOARD
Fig. 14 - External heatsink
example (R th = 30 °C!W)
mounting
Fig. 15 - Maximum allowable power dissipation vs.
ambient temperature
(,_4350
,w
Pt. 1
)
ic
.y~"'I'''
'"%
~
's/1t.ot
~
If-/rJy
~1"c:'s:"'1T~t
o
·50
129
50
~
~
c''''
A./
~
t-T-%.
""
"~
....,... :f\
)0...
LINEAR INTEGRATED CIRCUIT
SWITCH MODE SOLENOID DRIVER
The L294 is a monolithic integrated circuit in an 11-1ead MUL TIWATT® package. It is particularly
suited for solenoid driving,such as hammers and needles in printers and comp
hard-copy peripherals.
ith high working
The switch-mode control of the output current allows electromechanic
speed to be driven (switch ON/switch OFF time is very short) and to
r dissipation compared to standard solutions.
Furthermore, the L294 incorporates a diagnostic circuit with lat
function (for instance electromagnet coil in short circuit). ,
The L294 main features are:
high voltage operation (up to 50V)
high output current capability (up to 4A)
low saturation voltage
/J-P compatible input
Vs
Vss
VEN
Vi
Ip
Ptot
Tstg , Tj
Input
age
Peak output current (repetitive)
Total power dissipation (at T case = 75°C)
Storage and junction temperature
50
v
7
7
7
V
4.5
A
W
°C
25
-40 to 150
V
V
ORDERING NUMBER: L294
Dimensions in mm
MECHANICAL DATA
6/82
130
CONNECTION DIAGRAM
(top view)
SINK OUTPUT
"
CURRENT SENSING
B
TIMING
~ '~
ENABLE
INPUT VOLTAGE
GNO
DIAGNOSTIC OUTPUT
LOGIC SUPPLY VOLTAGE
ON
TIME
LIMITER
SOURC E OUTPUT
POWER SUPPLY VOLTAGE
Tab connected to pin 6
5
~
5312/1
BLOCK DIAGRAM
02
ZOUT
11
SINK
STAGE
OUT
L r9
01
5-501411
131
THERMAL DATA
Rth
j-case
Thermal resistance junction-case
max
3
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs =40V, Vss= 5V, T amb =25°C,
unless otherwise specified).
Parameter
Test conditions
Min.
Typ.
Vs
Power supply voltage (pin 1)
Operative condition
Id
Quiescent drain current (pin 1)
VENABLE- H
20
Vi;;' 0.6V;
70
Vss
Logic supply voltage (pin 4)
Iss
Quiescent logic supply current
12
VENABLE= L
DIAG output at high
impedance
Vi
I nput voltage (pin 7)
Operating output
I nput current (pin 7)
VENABLE Enable input voltage (pin 9)
IENABLE
Iload/Vi
Enable input current (pin 9)
Transconductance
46
V
30
7
V
mA
10
100
J.lA
0.6
0.45
Vi;;' 0.6V
-1
Vi" 0.45V
-3
Low level
-0.3
High level
2.4
V
J.lA
0.8
VENABLE= L
-100
VENABLE- H
100
Rs= 0.2.11
mA
8
Non-operative output
Ii
Unit
5
4.5
V 01AG - L
Max.
Vi = lV
0.95
1
1.05
Vi= 4V
0.97
1
1.03
V
J.lA
AN
V sat H
Source output saturation
voltage
Ip= 4A
1.7
V
V sat L
Sink output saturation
voltage
Ip=4A
2
V
V sat H+V sat L Total saturation voltage
4.5
Ip-4A
1
V
mA
Ileakage
K
Output leakage current
Rs- 0.2.11;
On time I imiter constant (0)
VENABLE- L
V 01AG
Diagnostic output voltage
(pin 5)
IOIAG- 10mA
0.4
V
IOIAG
Diagnostic leakage current
(pin 5)
V o1AG =40V
10
J.lA
V pin 8
OP AMP and OT A DC voltage
gain (00)
V pin 10- 100 to 800 mV
0.9
V
V pin 10
V SENS
Vi " 0.45V
Sensing voltage (pin 10) (000)
()
After a time interval t max = KC 2 , the output stages are disabled.
(00) See the block diagram.
(000) Allowed range of V SENS without the intervention of the short circuit protection.
132
K.I1
120
5
CIRCUIT OPERATION
The L294 works as a transconductance amplifier: it can supply an output current directly proportional
to an input voltage level (Vi). Furthermore, it allows complete switching control of the output current
waveform (see fig. 1).
The following explanation refers to the Block Diagram, to fig. 1 and to the typical application circuit of
fig.3.
The ton time is fixed by the width of the Enable input signal (TTL compatible): it is active low and
enables the output stages "source" and "sink". At the end of ton, the load current Iload recirculates
through D1 and D2, allowing fast current turn-off.
The rise time t, depends on the load characteristics, on Vi and on the supply voltage value (V s, pin 1).
During the ton time, Iload is converter into a voltage signal by means of the external sensing resistance
Rs connected to pin 10. This signal, amplified by the op amp and converted by the transconductance
amplifier OTA, charges the external RC network at pin 8 (R1, Cn. The voltage at this pin is sensed by
the inverting input of a comparator. The voltage on the non-inverting input of this one is fixed by the
external voltage Vi (pin 7).
After t" the comparator switches and the output stage "source" is switched off. The comparator output
is confirmed by the voltage on the non-inverting input, which decreases of a constant fraction of Vi
(1/10), allowing hysteresis operation. The current in the load now flows through D1.
Two cases are possible: the time constant of the recirculation phase is higher than R 1. C1; the time
constant is lower than R1.C1. In the first case, the voltage sensed on the non-inverting input of the
comparator is just the value proportional to Iload. In the second case, when the current decreases too
quickly, the comparator senses the voltage signal stored in the R1 C1 network.
In the first case t1 depends on the load characteristics, while in the second case it depends only on the
value of R 1.C1 .
In other words, R1.C1 fixes the minimum value of t1 (t 1 ;;;;'1/10 R1.C1. Note that C1 should be chosen
in the range 2.7 to 10 nF for stability reasons of the OTA).
After t 1 , the comparator switches again: the output is confirmed by the voltage on the non-inverting
input, which reaches Vi again (hysteresis).
Now the cycle starts again: t 2 , t4 and t6 have the same characteristics as t" while t3 and t5 are similar to
t 1 . The peak current Ip depends on Vi as shown in the typical transfer function of fig. 2.
It can be seen that for Vi lower than 450 mV the device is not operating.
For Vi greater than 600 mV, the L294 has a transconductance of 1A/V with Rs= 0.2n.. For Vi included
between 450 and 600 mV, the operation is not guaranteed.
The other parts of the device have protection and diagnostic functions. At pin 3 is connected an external
capacitor C2, charged at constant current when the Enable is low.
After a time interval equal to K . C2 (K is defined in the table of Electrical Characteristics and has the
dimensions of ohms) the output stages are switched off independently by the Input signal.
This avoids the load being driven in conduction for an excessive period of time (overdriving protection).
The action of this protection is shown in fig. 1 b. Note that the voltage ramp at pin 3 starts whenever
the Enable signal becomes active (low state), regardless of the Input signal. To reset pin 3 and to restore
the normal conditions, pin 9 must return high.
This protection can be disabled by grounding pin 3.
The thermal protection included in the L294 has a hysteresis.
It switches off the output stages whenever the junction temperature increases too much. After a fall of
about 20°C, the circuit starts again.
Finally, the device is protected against any type of short circuit at the outputs: to ground, to supply and
across the load.
When the source stage current is higher than 5A and/or when the pin 10 voltage is higher then 1 V (i.e.
for a sink current greater than 1 V/Rs) the output stages are switched off and the device is inhibited.
This condition is indicated at the open-collector output DIAG (pin 5); the internal flip-flop F/F changes
and forces the output transistor into saturation. The F/F must be supplied independently through Vss
(pin 4). The DI.AG signal is reset and the output stages are still operative by switching off the supply
133
CIRCUIT OPERATION (continued)
voltage at pin 1 and then by switching the device on again. After that, two cases are possible: the reason
for the "bad operation" is stili present and the protection acts again; the reason has been removed and
the device starts to work properly.
Fig. 1 - Output current waveforms
Fig. 2 - Peak output current
vs. input voltage
(;-66961'
'p
(A )
RS =0.2 it
V'l--f---"-"-'''I--VENABLE
/
a)
'/
V
V
V
V
V
b)
Fig. 3 - Test and typical application circuit
+
sv
Fig. 4 - Output saturation
voltages vs. peak output
current
H
+ Vs
.
v"
(V'
Vi
L
2mH
ENABLE
"'"L..r
RL
2fi
_.
I
I
Vsat
I
./
V
1.,
I
/v
./
01: 3A fast diode
02: 1 A fast diode
./
./
./
V
V
VSatH
V
0.'
5 - 531111
4 JplAI
Fig. 6 - Turn-off phase
Fig. 5 - Safe operating areas
-1,701
V
CE
ve,
)
(V)
I
100 se
40
JOO}Jsec
I
/
\
30
,\C
\
i
/
/
\
.-J
100
134
200
I. . . . . r-.
300
tensed
CALCULATION OF THE SWITCHING TIMES
Referring to the block diagram and to the waveforms of fig. 1, it is possible to calculate the switching
times by means of the following relationships.
t
,= -
L
RL
In (1 -
=-
L
RL
In
tf
RL
V1
. Ip)
V2
V2 + RL . 10
where:
V1 = Vs - VsatL - VsatH - V R sens
where:
V2
IK ";; 10
";;
= Vs + VOl + V 02
Ip
10 is the value of the load current at the end
of ton.
a) _
L
RL
0.9 Ip . RL + V3
Ip RL + V3
In
b) - R1 C1 In 0.9
~
RL
Note that the time interval tl
switching frequency is always:
==
-k-
where
V3 = VsatL + V Rsens + VOl
R1 C1
In ( V1 - Ip RL )
V1 - IK RL
= t3 = t5 = .... takes the longer value between case a) and case b). The
fswitching
=
In the case a) the main regulation loop is always closed and it forces:
IK = (0.9 ± S) Ip
where: S= 3%
S = 1.5%
@
@
Vi = 1V
Vi = 4V
In the case b), the same loop is open in the recirculation phase and IK,which is always lower than 0.9I p ,
is obtained by means of the following relationship.
V3
RL
- - (l-e
With the typical application circuit, in the conditions Vs
result:
= 40V,
t, = 255/Js
a) 70/Js
b) 16/Js
f = 10.2 KHz
135
Ip
= 4A, the following switching times
LINEAR INTEGRATED CIRCUIT
VERY LOW DROP 5V VOLTAGE REGULATOR
• PRECISE OUTPUT VOLTAGE (5V ± 2.5%)
• VERY LOW DROPOUT VOLTAGE
• OUTPUT CURRENT IN EXCESS OF 500 mA
• POWER-ON, POWER-OFF INFORMATION (RESET FUNCTION)
• +1 00/-1 OOV LOAD DUMP PROTECTION
:;t{:!':35V
5-5B33
Fig. 5 - P.C. board and component layout of the circuit of fig. 4 (1: 1 scale)
C5-0175
3/83
SELECTION OF COMPONENT VALUES
Component
Recommended
Value
R1
R2
100 kl1
Reset
sensing
threshold
R3
4.7 kl1
fa setting
R4
1 kl1
R5
15 kl1
Purpose
Allowed Range
Min.
Max.
-
1 kl1
220 kl1
NOTE
R1/R2 =
Vi min.
V T (pin 12)
100 kl1
R4 rnin =
Frequency
Va
50 rnA
See application note
"Designing with the L296
Power Switching Regulator".
10 kl1
compensation
R6
R7
51 kl1
Voltage
divider
-
C1
10 J.lF
Stability
1 J.lF
C2
2.2 J.lF
Reset delay
1 J.lF
4.7 J.lF
C3
2.2 nF
fa setting
1 nF
3.3 nF
C4
2.2 J.lF
Soft start
1 J.lF
4.7 J.lF
C5
33 nF
51 kl1.
R6/R7 =
Vo - V ref
V ref
Frequency
compensation
C6
100 J.lF
C7
100 J.lF
L1
300 J.lH
See application note
"Designing with the L296
Power Switching Regulator".
Output filter
3/83
Fig. 6 - Efficiency vs; out·
put current
Fig. 7 - Dissipated Power vs.
output current (L296 only)
-
Vo "S.1V
f ,,100KH~
Po
-
,W)
6-4!1I6
0,,5.1 V ~~.
f ,,100KHz
diode VSKS40
(Schottky)
eo
70
/
I--
diodeVSK54
(Schottky)
f-
Fig. 9 - Efficiency vs. output voltage
-
,/""
..;;V ,./
,/
V
/ V
,/
'"
,.,
r--r--r--+--+-~V;~'''3'~V--L--4
50
f---+c--l- r--
'o·JA
0
I"
Vo(V)
I
I
/-
I
'-I /
Fig. 11 - Power dissipation
derating curve
6-4117
"7".
I"\t-,
IIII
10
RJ(Ko.)
• VSK
540
-'-----+-------------~~~
f
GNO----~------------~-4----~--~~~
3/83
j-..;.
II
·,S
~~
,. "''''~4''',"'."'. ~ ~
~
Fig. 12 - Voltage sensing for remote load
10
-.
-....
('' KHj
~V
2D
C3~\Snf
IIII
>0
24
K..
OKH~
(wi
CJa2.Znr:)r...
dlodeVSK 540(Sc:hottky)
- - diode VHE 1402
25KHJ
p ....
I
60
,....
Vj .15V
r--r--r--r--r--+--r.to~.~~~K~H'~
80
~
diodeVSKS40{Schottkyl
(KH~ )
I
.
I
50
04)
90
..
Fig. 10 - Operating frequency vs. R3 and C3 0"4111
t
"
6-4'15
Vj",J5V
Vo .5.W
"
90
60
Fig. 8 - Efficiency vs. output current
5.
\
........,:-
~~
~~
~
"",
>0'
rOC)
Fig. 13 - Typical application
RESET OUT
BOVA
':J
BY251
20V
20V
BY251
VSK
540
5-5&32
Va= 5.1to15V
10 = 4A max. (min. load current = 100 mAl
ripple ~ 20 mV
loadregulation(lAt04A}= 10mV(V o = 5.1V}
line regulation (220V ± 15% and to 10 = 3A) = 15 mV (Va = 5.1V)
Fig. 14 - Preregulator for distributed supplies
I---.----{)sv /400mA
lO-4DY
L296
PREREGULATOR
5.Bv
f-.......---35V
';CURRENT LIMIT SETTING
A resistor connected to pin 4 sets the current
limit threshold. If this resistor is omitted, and pin 4
left open circuit, the limit threshold is 5A. The
threshold can be varied from 0.5 to 4A. For a
threshold of 2.5A the resistor is about 33 kil.
When the switching frequency is at least ten times
greater than the frequency at which the open loop
gain is unity, the system can be approximated to a
linear system. The PWM block can then be characterised as a linear block with gain independent of
frequency.
Compensating the system with a series RC network
on the output of the error amplifier (pin 9). we
obtain:
THE LC FILTER
Z
The LC filter converts the pulse output of the
L296's power stage into a continuous output
voltage with a superimposed ripple, I::, V. The inductor determines the voltage ripple on the capacitor.
The ripple 1::,1 L is generally chosen to be twice the
minimum load current to avoid periods when the
transistor and diode are both non-conducting.
The formulae used to calculate LC as a function
of 1::,1 L and I::, V are:
L=
Vo(Vi-V o )
=
1+ sRC
sC
Placing the zero introduced by the error amplifier
at the resonjlnce frequency of the LC output filter
(w o = 1/ Y LC) we obtain the Bode plot shown in
figure 2.
The slope when it crosses the frequency axis at 0
dB is roughly 40 dB/decade. In practice the LC
filter contains parasitic elements which give a lower
slope.
/'
The series resistance of the capacitor (ESR) 1,,- /
troduces a zero at high frequencies, guaranteeing'
stability of the system.
Vi f I::,IL
Fig. 2 - Bode plot of regulation loop.
C=
Va (Vi - Vol
8U' I::,V
dB
For example, for the test circuit (figure 5) the LC
filter was calculated from the following data:
Vi = 35V
I::,IL = 150 mA
I::,V = 3 mV
Therefore
Vo= 5V
f = 100 kHz
5 --'.(3:=;5=---...:::5..:.)_ _ _ 300 /LH
L = _ _ _:c
35x 1OOOOOx 150x 10·'
Wo
and
I
I.
I
Hz
S_~97S
fswilch
C = _ _ _ _--".5--'-(3::.:5;:..-_5::.;)'--_ _ _ - 220 /-LF
8x300x 10·' x (1 OOx 10' ) • x30x 1 0·'
10
DIODE
In practice the ripple depends on the quality of the
filter capacitor. With standard components the
ripple will be roughly twice the value implied by
this calculation. In this example the actual ripple
is about 5 mV.
The diode should be a fast type to avoid high
current peaks in the output transistor. The choice
is therefore between Schottky diodes and fast'
diodes with a Trr of less than 35 ns.
A multiple capacitor - two or more connected in
parallel with a total capacity of C - is recommended. Smaller electrolytics have a lower inductance - important at high frequencies - and handle
higher peak currents.
These diodes cost roughly the same. The only significant difference is the lower forward voltage of
Schottky diodes. At low output voltages - around
5V - a Schottky diode therefore improves the efficiency of the system.
COMPENSATION AND STABILITY
SWITCHING FREQUENCY
The system is non linear because the output stage
operates in switchmode. However, in certain conditions the system can be represented as linear
blocks. Delays are introduced by the output stage
which can contribute to instability of the system.
The choice of switching frequency depends on the
inductor chosen (a smaller inductor can be used at
higher frequencies), the power dissipation and
desired efficiency. It should not exceed 200 kHz
or efficiency will be reduced; the lower limit is set
2
only by the maximum acceptable dimensions of
the output filter.
The chosen frequency is set by the RC network
connected to pins 7 and 11 (OSC and SYNC).
Suitable values can be found from the nomogram,
figure 3. The capacitor must be in the range 1 nF 3.3 nF and the resistor in the range 1 kil to
100 kil.
Fig. 3 - Nomogram to find the values of the
oscillator components.
,
Fig. 4 - In multiple supplies several L296s can be
synchronised as shown here to reduce
interference on the ground plane.
L296
osc
G - 4912
Rose
2
100
'"'0
,,,
'\
I
C3=t5nF
leos
L-~
osc
I
SYNC
osc
SYNC
_.+-1_~______~_J
e
I n view of the high currents (5A peak) and fast
risetimes involved, care is necessary in the printed
circuit layout to avoid problems. In particular, the
tracks connecting the L296 output, recirculation
diode and LC filter must be short to reduce voltage
drop and avoid stray coupling.
C3=Un~"
1":,
",~
r-.
6
10
--
I
L296
LAYOUT
~~
10
SYNC
1
(KHz l
c ........
L296
,
R3(Klll
SYNCHRONISATION
When several L296s are used in a multiple supply
the switching frequencies should be synchronised
to avoid interference propagated on the ground
plane.
This is done by connecting the SYNC pins together
and omitting the oscillator components on all but
the first device. The OSC pins of the subsequent
devices are left open, as shown in figure 4.
It is also important to connect the input filter
capacitor, the recirculation diode and output capacitor to the same ground point. A separate ground
should be used for the signal processing circuit
grounds, connected to the power ground at the
negative output terminal.
Figure 5 shows a su itable layout for the test and
evaluation circuit of figure 1.
To guarantee good load regulation the two sensing
terminals, pin 8 and 10, should be connected
directly to the load as shown in figure 6. The two
ten ohm resistors shown in this circuit are necessary
to ensure that feedback will still be supplied to the
L296 even when the sensing wires are disconnectedc
Fig. 5 - PC board layout for the test and evaluation circuit of figure 1.
(
C5-0175
3
Fig. 6 - When the load is some distance away this
four wire connection should be used to
ensure good regulation.
divitler, to the unregulated input (figure 8).
The internal threshold of the reset circu it is V ref - 100 mV (roughly 5V). Therefore the divider for
the second case is found from:
A
VSK
10
Vi min
V ref -100 mV
R1
R2
10.0.
540
8
R2 should not exceed 200 kn.
The reset output is open collector and the maximum allowed collector current is 50 mAo
--+---------'i-~
c
lOll.
GND----~--------------~----OD--------~
5 - 58 2 11
Fig. 8 - The reset circuit's sense input can be
connected to the feedback point (a) or to
the input via a divider (b).
35V
Taking away all the optional components gives the
even simpler configuration of figure 3. This circuit
provides 4A at 5.1 V, soft start, thermal shutdown
and current limiting with the default 5A threshold.
The L296 is also ideal for use as a preregulator in
distributed supply systems. Combined with low
drop series regulators such as the L4800 series, an
L296 gives extremely high efficiency plus very
good regulation (figure 4).
I,
It
"
i
'f
~'
"I
I
Fig. 3 - Many components can be omitted as shown here. This is a 4A/5.1 V supply.
LIMIT
THRESHOLD
10_SOI/
INPUT
RESET
THRESHOLD
RESET RESET CROWBAR CROWBAR
OUT
DELAY
SENSE
DRIVE
300,uH
0 - - INPUT
OUT
1-~r--
___-"'"yy'---.--*-~--05.IV
200,uF
L296 POWER
SWITCHING REGULATOR
GNal-~~--------4----*----O
FEEDBACK
INHIBIT
"'_5980
2.211
I
Fig. 4 - The L296 is ideal for use as a preregulator in distributed supply systems. Efficiency is very high
and regulation is excellent.
I---.---QSY /400mA
10-40Y
L 296
5.BY
PREREGULA TOR
-05Y/400mA
')-S'lDl
LOOKING INSIDE
Looking at the simplified block diagram, figure 5,
the main regulation loop can be identified quite
easily; it consists of a 5.1 V reference, loop error
amplifier, PWM modulator (sawtooth oscillator
IS comparator), power stage and an external LC
(.
er.
Voltage feedback from the output is compared
with the 5.1 V reference in the error ampl ifier. The
output of this amplifier sets the threshold of the
PWM comparator and thus controls the duty cycle
of the switching pulses. These pulses drive the output stage, producing the desired output voltage
with the help of the LC filter. If the output is con-
nected to the feedback point directly the regulated
output voltage is 5.1V; a divider is added to the
feedback loop to produce higher Voltages. The loop
gain characteristics can be adjusted by the external
RC network, RgCg, to give the required stability,
ripple rejection at twice the mains frequency and
immunity against supply and load variations.
The output of the oscillator is not connected internally to the PWM comparator. This is done
del iberately so that several L296s can be synchronised, avoiding interference and switching noise on
the ground plane in multiple supplies. The SYNC
pins of all the devices to be synchronised are connected together and only one is equ ipped with the
oscillator components, as shown in figure 6.
3
Fig. 5 - Simplified block diagram of the L296.
CROWBAR
INPUT
SUPPLY
VOLTAGE
CROWBAR
DRIVE
OSC.
S
Q
INHIBIT
FLIP
FLOP
~--------~R
Q
r-------~~'2~~R~E~SET INPUT
THERMAL
SHUTDOWN
I
1-':.:4'l-_R..,ES:)E T 0 U TP UT
RESET
1--------
'3
RESET
:CDELAY
5-5834/l
I
INHIBIT
INPUT
ess
SWITCHING vs LINEAR
How much do you gain?
It's a well known fact that switching regulators are
more efficient than linear types so the transformer
and heatsink can be smaller and cheaper. But how
mlj,ch can you gain? We can estimate the savings
by comparing equivalent linear and switching regulators. For example, suppose that we want a
4A/5V supply.
Therefore Vi min ~ 10.6V
,t
V1(min)
---~~~~
l-
vr' PP't>
--~-~tS-~g96
Linear
For a good linear regulator the minimum dropout
will be at least 4V at 4A. The minimum input
vo/tage.is given by:
4
Since operation must be guaranteed even when the
mains voltage falls 20%, the nominal voltage on
load at the terminals of the regulator must be:
V nom =
VI min
0.8
=
10.6
0.8
= 13.25V
VI min = Va + V OROP + Y2 VrlPPle
/0 T1
4x8x10-3
= 3.2V
where VrlPPle ~----1Ox10- 3
C
To allow even a small margin we have to cho!Js~/
(a good approximation is 8 ms for tl (at mains
frequency of 50 Hz) and 1000 fJ.F for C, the filter
capacitor after the bridge).
The power that the series element must dissipate
is therefore:
V nom
=
14V
P d = (Vnom - Va) 10 = 36W
Fig. 6 - Several L296s can be synchronised easily to avoid switching noise and save components.
L296
OSC
50
SYNC
I
~ ±Co~
-
OSC
SYNC
I
I
SOFT START AND CURRENT LIMITING
The soft start is produced by the diode, D, an external capacitor, Cs s , and a constant current
source.
("
L296
L296
'/hen power is applied, after an inhibit, or after a
OSC
SYNC
I
S-!!976
current limit, the voltage across Css is zero,
clamping the error amplifier output to zero via the
diode D. The capacitor is charged by the constant
current generator, thereby allowing the error amplifier output - and hence the output voltage - to
rise (figure 7).
Fig. 7 - Waveforms showing the soft start.
CLAMPED ERROR
AMP OUTPUT
NOMINAL
ERROR AMP
OUTPUT
OUTPUT
CURRENT
5- 56 35
and the transformer must supply a power of:
P diss = 14x4 = 56W
It follows that the transformer must be roughly
30 VA and the heatsink thermal resistance about
11 ° C/W.
It must therefore be dimensioned for:
Po=
56
0.9
=
62 VA
Transformer
and a heatsink will be necessary with a thermal
resistance of:
Rth heats. = 0.8° C/W
(
Switching (L296)
Assuming the same nominal voltage (14V), the
L296 data sheet indicates that the power dissipated
in this case is only 7W. And this power is dissipated
in two elements; the L296 itself and the recirculation diode.
Heatsink
Linear
Switching
62 VA
30 VA
0.8°C/W
11°C/W
This comparison shows that the L296 switching
regulator allows a saving of roughly 50% on the
cost of the transformer and an impressive 80-90%
on the cost of the heatsink. Considering also the
extra functions integrated by the L296 the total
cost of active & pas&ive components is roughly the
same for both types.
If for some reason it is necessary to use higher
supply voltages the switching technique, and hence
the L296, becomes even more advantageous.
5
Current limiting is more complex and involves two
comparators, a flip flop, an AND gate, an OR gate
and the transistor Or. A comparator compares the
output current,sensed by an on-chip metal resistor,
with the limit threshold preset by an external
resistor.
advanced bipolar process which allows the combination of fast-switching "high power devices and
dense control circuitry on the same chip. One of
the key features of this process is the use of a
two-step ion-implantation technique to form the
isolation wells.
As soon as the current tops the threshold,this comparator switches, setting the flip flop which disables the output stage and shorts the soft start
capacitor via Or.
Normally this isolation is created by diffusing
p-type impurities from above. The result is a
bowl-like cross section which wastes silicon area
(figure 9). Moreover, since prolonged high temperature processing is needed to perform this diffusion,
the n+ buried layer spreads, reducing the breakdown voltage.
A second comparator resets the fl ip flop when the
voltage across C ss has fallen below OAV, re-enabling the output stage. With the usual slow ramp,
the output current rises again and if the cause of
the excess current is still present the whole process
is repeated.
This cycle continues until the fault condition is
removed (figure 8). Thanks to the dead time and
the soft start ramp the average current in this condition is not high enough to damage the device.
Fig. 8 - Waveforms illustrating the action of the
current limiter.
ION-IMPLANTED ISOLATION
The L296 is one of the first products to exploit an
I n the new process a heavy p+ implant is made
before the n- epitaxi(ll collector growth, followed
by a further implant from above. When the wafer
is heated both implants diffuse, jOining in the
middle to create a narrow but deep isolation well
(figure 10). Since high temperature processing is
much reduced the n+ buried layer spreads verv
little and the resulting NPN transistor has a brea:
down voltage in excess of 50V.
The narrower isolation resu Its in an increased
density, with minimal geometry transistors reduced
to a compact 18 mil 2 • Speed is correspondingly
increased.
Teamed with the Multiwatt plastic package, this
process allows the integration of complex devices
handling in excess of 200W. Other devices already
introduced include the L295 dual solenoid driver
(220W), the L294 switchmode driver (180 W) and
the L298 dual bridge driver (200 W).
Fig. 9 - Diffusing the isolation from above gives the familiar bowl-shaped cross section which wastes
spaces.
P t ISOLATION
DIFFUSION
n+
EMITTER
n- EPITAXIAL
P substrate
5-6001
Fig. 10 - The above/below two-step implanted isolation is more compact and results in an increased nthickness between base and buried laver. raising the breakdown voltage.
p+-ISOLAT10N
DIFFUSION
~
n+
EMITTER
p
n-EPITAXIAL
BASE COLLECTOR
n+
---vTTTTTh1~.o...r----+. ~J._
p
n+
BURIE~~AYER
_ _ _ _)
K
subsleal.
15-60oa
6
Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for the consequences of its use nor for
infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise un,.
any patent or patent rights of SGS·ATES. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and substitutes all information previously supplied.
SGS·ATES GROUP OF COMPANIES
Italy· France· Germany· Malta· Malaysia· Singapore· Sweden· Switzerland· United Kingdom· U.S.A.
© SGS-ATES Componenti Elettronici SpA, 1983 - Printed in Italy
CONNECTION DIAGRAM (top view)
@7i,
(tab ctr',nected to pin 3)
5- 5307
BLOCK DIAGRAM
INPUT
lo---~--------~------------------------------------~~'
4
DELAY
CAPACITOR
5 - 5 202
TEST CIRCUIT
OUTPUT
VOLTAGE
IN
I,oonF
4
,..,
,,J
L 487
I
I
+ 5V
""rn
..J.!.O fJF 10'00 fJF
RESET
OUTPUT
5-5308
THERMAL DATA
Rth j-case
max
Thermal resistance junction-case
137
3
°C/W
= 14.4V, Tamb = 25°C, unless
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vi
otherwise specified)
Test conditions
Parameter
Vo
Output voltage
Vi
Operating input voltage
!OVo
Line regulation
10=5mA to 500mA
Vi = 6to 26V
Min.
TVp·
Max.
Unit
4.80
5
5.20
V
28
V
10 =5mA
5
mV
mV
!oVo
Load regulation
10 = 5 to 500 mA
15
Vi-V o
Dropout voltage
10 = 500mA
0.6
V
Id
Qu iescent current
5
20
100
mA
0.5
mV/oC
60
dB
0.8
A
!OVo
~
SVR
Ise
10 = 0 mA
io=150mA
10 = 500mA
Temperatu re output
voltage drift
SupplV voltage rejection
f = 120 Hz
Vi=12V±5Vpp
10 = 350 mA
Co = 10IlF
Output short circuit
current
VR
Reset output voltage
IR= 16mA
IR
Reset output leakage
current
Vo in regulation
td
Delav time for reset
output
Cd=100nF
V RT
Reset threshold
VRTH
Threshold hysteresis
Vo';; 4.75V
4.75
Fig. 1 - Timing diagram for reset function
~o) 1------486
4 e~
______
-
_ ___ _ _ __ _ _____ _
- -- - - - - - - - - - - - - - - - - - - I
J~omv
'
I/ :
.
138
i
• I
0.8
V
50
IlA
30
ms
Vo-0.15
V
10
mV
LINEAR INTEGRATED CIRCUITS
HIGH-VOLTAGE, HIGH-CURRENT 8 DARLINGTON ARRAYS
These high-voltage, high-current Darlington transistor arrays comprise eight NPN Darlington on a
common monolithic substrate. All units feature open collector outputs and integral suppression diodes
for inductive loads. Peak currents of 500 mA can be withstood. They are pinned with inputs opposite
outputs to facilitate circuit board layout.
The L601 is a general-purpose array wich may be used with DTL, TTL, PMOS, CMOS, etc.
The L602 is specifically designed for use with 14 to 25V PMOS devices. Each input has a Zener
diode and resistor in series in order to limit the input current to a safe value.
The L603 has a series base resistor to each Darlington pair, and thus allows operation directly with
TTL or CMOS operating at a supply voltage of 5V.
The L604 has a series base resistor to each Darlington pair, and thus allows operation directly with
PMOS or CMOS utilizing supply voltage of 6 to 15V.
In all cases, the individual Darlington collector current rating is 400 mAo However, outputs may be paralleled for higher load current capability. The devices are supplied in a 18-lead dual in-line plastic package
with copper frame.
ABSOLUTE MAXIMUM RATINGS
V CEX
Ic
Ic
VI
Ii
Ptot
Top
Tstg
Collector emitter voltage (input open)
Collector current
Collector peak current
Input voltage (for L602, L603 and L604)
Input current (for L601 only)
Total power dissipation a T amb = 25°C
Operating junction temperature
Storage temperature
90
0.4
0.5
30
25
1.8
-25 to 150
-55 to 150
V
A
A
V
mA
W
°C
°C
ORDERING NUMBERS: L601B, L602B, L603B, L604B
MECHANICAL DATA
Dimensions in mm
139
6/82
CONNECTION DIAGRAM
(top view)
IN
>---,----1118
OUT
1
IN
2
:>-;--+-1117
OUT
2
IN
3
;>-;--+-11'6
OUT
3
IN 4
>---,--+--11'5
OUT 4
IN 5
>-~-+-1114
OUT
5
IN 6
;>-;--+-1113
OUT
6
IN 7
:>-;--+-1112
OUT
7
IN 8
>-.....-+-1111
OUT
8
10 COMMON FREE
WHEELING DIODES
GND
5-34901\
SCHEMATIC DIAGRAMS
L601
L602
COM
COM
__- - - - + - - . - - o O U T
10.5kfi
INo-T--T~~_~
I
L_~
I
I
________ _
EACH DRIVER
L_~
__________ J
EACH DRIVER
5- 3499
L603
5-1984
L604
COM
COM
2.7kn
INo--r--=-
~----+--.--oOUT
10.5k(1
~----+--.--oOUT
I N o-·T--C=r-I--t"'---.~
__y
3kfi
-~-------
EACH DRIVER
140
_J
5-2574
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
70
°C/W
ELECTRICAL CHARACTERISTICS (T amb = 25°C, unless otherwise specified)
Parameter
I CEX
Output leakage current
V CE(sat) Collector emitter saturation
voltage
Test conditions
Ic= 300 mA
Ic= 200 mA
Ic= 100 mA
18= 500 !LA
18= 350 !LA
18= 250 !LA
DC forward current gain
(L601 only I
V CE = 3V
Ic= 300 mA
Vi
Minimum input voltage
(ON condition I
V CE = 3V
for L602
for L603
for L604
Ic= 300 mA
Maximum input voltage
VCE= 90V
for L601
for L602
for L603
for L604
Ic= 25 !LA
(OFF conditionl
Typ.
V CE= 90V
hFE
Vi
Min.
Max.
Unit
10
!LA
2
1.7
1.2
V
V
V
-
1000
11.5
2.5
2.5
V
V
V
V
V
V
V
0.55
7
0.75
1
50
!LA
2.4
V
IR
Clamp diode nwerse current
V R= 90V
VF
Clamp diode forward voltage
IF= 300 mA
ton
Turn-on delay
0.5 Vi to 0.5 Vo
0.4
!LS
toft
Turn-off de Iay
0.5 Vi to 0.5 Va
0.4
!LS
2
i.i
Iii:1
I.:
I.'
i:
11
141
LINEAR INTEGRATED CIRCUIT
QUAD DARLINGTON SWITCH
•
SUSTAINING VOLTAGE: MIN. 70V
•
•
2A OUTPUT
HIGH CURRENT GAIN
The L 702 is a monolithic integrated circuit for high current and high voltage switching applications.
It comprises four darlington transistors with common emitter and open collector, suitable for current
sinking applications, mounted on the new Powerdip and Multiwatt packages.
This circuit reduces components, sizes and costs; it can provide direct interface between low level logic
and a variety of high current applications.
ABSOLUTE MAXIMUM RATINGS
V eEX
Vi
Ie
Ie
Ptot
Collector-emitter voltage (input open)
Input vo Itage
Collector current
Collector peak current (repetitive)
Total power dissipation at T pin 9 to 16 .;;; 90DC}
Total power dissipation at Tamb .;;; 70DC
Total power dissipation at Tease';;; 90DC
Sto rage temperatu re
Operating junction temperature
ORDERING NUMBER:
Multiwatt
V
V
4
W
W
W
1.1
20
-55 to 150
-25 to 150
A
A
DC
DC
L 7028 - Powerdip
L 702N - Multiwatt
MECHANICAL DATA
6/82
Powerdip
90
30
2
3
Dimensions in mm
142
CONNECTION DIAGRAMS (top view)
S-J480
81
1
16
81
1
15
Cl
3
14
Cl
C2
,
13
C2
GND
C3
5
"
C'
6
1.1
83
7
10
84
8
~
11
Bl
10
B2
nc
GND
4
~
3
THE TAB 15 CONNECTED TO PIN 6
Powerdip
C3
C4
B3
B4
5-3749
Multiwatt
SCHEMATIC DIAGRAM (each Darlington)
c
B
- ......- -......---.--~--_oV
Fig. 6 - Input current vs.
input voltage
--
+--11-
\
rtt
Fig. 7 - Safe operating areas
Fig. 8 - Safe operating areas
(L702B)
(L702N)
'e
'~~!!!~II~III
,-
• r---SlNGLE PULSE
f-l-oc+H-f*I---+f\
-..
Fig. 9 - DC current gain vs.
collector current (*)
G-3105
_FE,
(A).
YJCYI
20
10
,,<.oJ
. 500 ~ ,~.
501,;~-
,
Ii--
I
,0>
I
\
.!
I:,
10"'
I
:I·!
i
III
['ilil
I
10""
'0
~
I
•
10·'
It")
(*J Pulse width = 300 IlS, duty cycle 1.5%.
Fig. 10 - Stepping motor buffer
145
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
POSITIVE VOLTAGE REGULATORS FOR AUTOMOTIVE
•
•
•
•
•
•
•
•
•
OUTPUT VOLTAGE OF 5,8.5 AND 10V
OUTPUT CURRENT UP TO 500 mA
NO EXTERNAL COMPONENTS
LOW DROP-OUT VOLTAGE
LOAD DUMP VOLTAGE SURGE PROTECTION
REVERSE VOLTAGE PROTECTION
SHORT CIRCUIT PROTECTION
CURRENT LIMITING
THERMAL SHUTDOWN
The L2600 series of three therminal positive regulators is specially designed to stabilize power supplies
for car instrumentation in vehicles with 12V battery. They can supply an output current up to 500 mA.
ABSOLUTE MAXIMUM RATINGS
DC input voltage
DC input reverse voltage
Positive transient peak voltage (t = 40 ms, duty cycle = 1 %)
Negative transient peak voltage (t = 30 ms, duty cycle = 1%)
Operating temperature
Storage temperature
Power dissipation
ORDERING NUMBERS: L2605V
L2685V
L2610V
(Vo= 5V)
(Vo= 8.5V)
(Vo= 10V)
Dimensions in mm
MECHANICAL DATA
4.amu
I
25
I~
~
6/82
35
V
-28
V
120
V
-90
V
-40to 150
DC
-65 to 150
DC
I nternally limited
146
CONNECTION AND BLOCK DIAGRAMS
(top view)
s-
156811
THERMAL DATA
Rthj-case
max.
Thermal resistance junction-case
ELECTRICAL CHARACTERISTICS (T amb
Parameter
25°)
Test conditions
Output voltage
Vo
=
10=500mA
4 °C/W
Vi = 12 to 16V (L26051
Vi = 12 to 16V (L2685)
Vi = 12 to 16V (L2610)
Vi
Operating input voltage
see note (0)
/',V o
Line regulation
10 = 50mA
Vi = 12 to 16V
/',V o
Load regulation
Vi = 14V
10 = 50 to 500 mA
/',V i _o
Dropout voltage
10=500mA
/',V o
Output voltage
drift
10 = 50mA
Vi = 14V
Tamb = -12 to 80°C
Isc
Output short
circuit current
Vi = 14V
SVR
Supply voltage
rejection
Vi = 16V
f= 100Hz
Output resistance
10 = 500mA
Min.
Typ.
Max.
Unit
4.8
8.15
9.55
5
8.5
10
5.2
8.85
10.45
V
28
V
2
mV
0.3
%
Vo
/',T
Ro
eN
(0)
Output noise voltage
Note: For a DC input voltage 28V
1.8
/',V i = 2V
10 = 500mA
BW = 100Hz to 10KHi
< Vi < 35V
the device is not operating
147
V
-1
mV/oC
900
mA
60
dB
0.05
n
20
I'V
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
PRINTER SOLENOID DRIVER
The L3654 is a printer solenoid driver containing ten open-collector driver outputs and a ten-bit serialin, parallel-out shift register.
Data is clocked into the shift register serially and transferred to the open-collector outputs by an enable
input. Serial input data is loaded by the rising edge of the clock. A serial output from the tenth bit is
provided which changes at the falling edge of the clock. This output is not controlled by the enable
input and remains active at all time.
Output stages are inhibited when the logic supply voltage falls below 6V.
Each output is rated at 250 mA (sink) and is clamped to ground internally at 50V to dissipate stored
energy in inductive loads.
The L3654 is supplied in a 16 lead dual in-line plastic package, and its main fields of application comprise thermal printers, cash registers and printing pocket calculators.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
VE
10
Ig
Ptot
Tstg'. TJ
Supply voltage
Input voltage
External supply voltage
Output current (single output)
Ground current
Total power dissipati~n (Tamb = 70°C)
Storage and junction temperature
9.5
9.5
45
0.4
4.0
1
-65 to 150
V
V
V
A
A
W
°C
ORDERING NUMBER: L3654 B
Dimensions in mm
MECHANICAL DATA
6/82
148
CONNECTION DIAGRAM
(top view)
OUTPUT ENABLE 1
16
Vs
OUTPUT 6
15
OUTPUT 5
OUTPUT 7
14
OUTPUT 4
OUTPUT 8
13
OUTPUT 3
OUTPUT 9
12
OUTPUT 2
OUTPUT 1
OUTPUT 10
6[
11
DATA OUTPUT
7[
10 DATA INPUT
GND
a[
CLOCK
S
5012
LOGIC DIAGRAM
OUTPU,5
V
OUTPUT 1
EN ENABLE
S - 5013
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
80
°C/W
I:
I,j
149
ELECTRICAL CHARACTERISTICS
(Vs= 8.5V, vss= 30V,
T amb = 0° to 70 0 e, unless otherwise
specified)
Test conditions
Parameter
Vs
Supply voltage
Is
Supply current
Min.
Typ.
7.5
Max.
Unit
9.5
V
T amb = 25°C
V EN = OV; Voo= OV
27
40
mA
Vs = 9.5V
V EN = 2.6V
10 = 250 mA (each bit)
55
70
mA
40
V
1
mA
65
V
1.6
V
VE
External operating supply
voltage
Ileak
Output leakage current
(each output)
Vss= 40V
VEN=OV
Vz
I nternal clamp voltage
I z = 0.3A
V EN = OV
VCE sat
Output satu ration voltage
lo=250mA
V EN = 2.6V
VOl
V CLK
V EN
I nput logic levels
(pins 1,9,10)
Low State (L)
101
Data input current
45
50
0.8
V
High state (H)
2.6
T amb = 70°C
V OI = 2.6V
0.3
0.57
mA
oOe
0.57
V OI = 1V
T amb = 70°C
220
V CLK = 2.6V
T amb= 70De
T amb =
ICLK
lEN
Clock input current
0.2
0.75
J.LA
0.33
mA
Enable input current
T amb = oOe
0.33
VCLK=1V
T amb = 70°C
125
V EN = 2.6V
T amb = 70°C
0.2
0.5
J.LA
0.33
mA
RIN
Voo
T amb = oOe
0.33
V EN = 1V
T amb = 70°C
125
Input pu II-down resistance
Clock input
T amb = 25°C
V CLK
Enable input
T amb = 25°C
V EN
Data input
T amb = 25°C
VOl
< Vs
4.5
Low state (L)
V OI = OV
loo(pin 7)= 0
0.01
Output logic levels
(pin 7)
< Vs
Roo
Output pull-down
resistance (pin 7)
V OI = OV
Voo=1V
150
J.LA
8
< Vs
High state (H)
V OI = 2.6V
100 (pin 7) = -0.75 rnA
0.5
K.I1
8
2.6
0.5
V
3.4
V
14
K.I1
Fig. 1 - Timing diagram
1L-_______----\lS
r
ItENclK
,"
I
Ult~~~~N
tClK tClK
~.
I
~n
I
~----4_----------~------
VClK
II'
4
~
VOO
-_l
~
-I
POH
,-1-
~tpoEll
OUTPUT- -
-
-
-
-
-
-
-
-
-
-
-
t PDEH
-
ELECTRICAL CHARACTERISTICS (see fig. 1 and the section "definition of terms")
Test conditions
Parameter
Min.
Typ.
Max.
Unit
Clock, data and enable input
tCLK
4
tCLK
5.5
tSET-UP
1
tHoLO
3
,"S
Clock to enable delay
tCLK EN
2 tSIT
tEN CLK
tSIT
Enable to clock delay
Data output delay
tpoH, tpoL
R L= 5Kfl.,
C L ";; 10 pF
0.8
2.5
,"s
Output delay
tpOEL
3
tpoEH
3.5
,"S
Output rise time
R L = 100 n, C L <100pF
Output fall time
R L = 100 n, C L <100pF
1.2
,"s
1.2
,"s
V OO rise time
0.4
,"s
V OO fall time
0.4
,"S
151
DEFINITION OF TERMS
v 55
VOl. V
:
CLK '
External power supply voltage. The return for open-collector relay driver outputs.
V EN :
The voltages at the data. clock and enable inputs respectively.
VOO
: The voltage at data output.
tSIT
: Period of the incoming clock.
tCLK
: The portion of tSIT when V CLK ;;;. 2.6V.
tCLK
: The portion of tSIT when VCLK ';;; O.BV.
t HOLO
: The time following the start of tCLK required to transfer data within the shift register.
tSET-UP
: The time prior to the end of tCLK required to insure valid data at the shift register input
for subsequent clock transitions.
152
LINEAR INTEGRATED CIRCUITS
3-TERMINAL POSITIVE VOLTAGE REGULATORS
•
•
•
•
•
OUTPUT CURRENT UP TO 1.5A
OUTPUT VOLTAGES OF 5; 6; 8; 12; 15; 18; 20; 24V
THERMAL OVERLOAD PROTECTION
SHORT CIRCUIT PROTECTION
OUTPUT TRANSISTOR SOA PROTECTION
The L7800 series of three-terminal positive regulators is available in TO-220 and TO-3 packages and
with several fixed output voltages, making it useful in a wide range of applications. These regulators can
provide local on-card regulation, eliminating the distribution problems associated with single point
regulation. Each type employs internal current limiting, thermal shut-down and safe area protection,
making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.
ABSOLUTE MAXIMUM RATINGS
Vi
DC input voltage (for Va = 5 to 18V)
(for Va = 20, 24V)
Output current
Power dissipation
Operating junction temperature (for L7800)
(for L7800C)
Storage temperature
35
V
40
V
internally limited
internally limited
-55 to +150
°C
Oto+150
°C
-65 to + 150°C
Dimensions in mm
MECHANICAL DATA
8.,....,1.7
(.-00$3It
TO-3
TO-220
153
6/82
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
~
o
C).
OUTPUT
~")3
,0
GND
INPUT
5--25&912
!)-lSti8/'
Type
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
7805
7805C
7806
7806C
7808
7808C
7812
7812C
7815
7815C
7818
7818C
7820
7820C
7824
7824C
TO-220
TO-3
-
L 7805T
L 7805 CT
L 7806T
L 7806CT
L 7808T
L 7808CT
L 7812T
L 7812CT
L 7815T
L 7815CT
L 7818T
L 7818CT
L 7820T
L 7820CT
L 7824T
L 7824CT
L 7805CV
L 7806 CV
L 7808 CV
L 7812CV
L 7815CV
L 7818CV
L 7820CV
L 7824CV
BLOCK DIAGRAM
INPut
'O---~--------~-------------~-1
154
Output voltage
5V
5V
6V
6V
8V
8V
12V
12V
15V
15V
18V
18V
20V
20V
24V
24V
SCHEMATIC DIAGRAM
Q17
R12
Rll
R5
OUT
R6
R20
R15
Qll
D1
R7
R,
R2
07
R19
TEST CIRCUITS
Fi!l. 1 - DC parameters
Fig. 2 - Load regulation
Fi!l. 3 - Ripple rejection I
THERMAL DATA
Rth H:ase
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
max
max
155
TO-220
TO-3
3°C/W
50°C/W
4°C/W
35°C/W
ELECTRICAL CHARACTERISTICS L 7800 (Refer to the test circuits, TJ= -55 to 150"C,
10
= 500 rnA, Ci = 0.33 iJ.F, Co = 0.1 iJ.F unless otherwise specified)
OUTPUT VOLTAGE
5
6
8
12
INPUT VOLTAGE
(Unless otherwise specified)
10
11
14
19
Parameter
Vo
Output
Min.
Typ.
Tj: 25°C
4.8
5
lo""5mAto1A
5
5.15 5.65
8
12
4.65
6
6.35 7.6
8.4 11.4
12.6
(V,: 8 to 20V)
(V,: 9 to 21V)
(V,: 11.5 to 23V)
(V,: 15.5t027V)
Test conditions
Max. Min.
5.2 5.75
Typ.
Max. Min.
Typ.
6
6.25 7.7
8
Unit
Max. Min.
8.3 11.5
Typ.
Max.
12
12.5
voltage
Po ,,15W
tNo
60
80
(V,: 10.5 to 25V)
120
(V,: 14.5t030V)
30
40
(V,: 11 to 17V)
60
(V,: l&to 22V)
100
100
100
120
25
30
40
60
6
6
6
6
0.5
0.5
0.5
0.5
0.8
(Vi: 8 to 25V)
0.8
(V,: 9 to 25V)
0.8
(V,: 11.5 to 25V)
0.8
(V,: 15 to 30V)
50
Line
regulation
(V,: 7 to 25V)
(V,: 8 to 25V)
Tj: 25°C
mV
25
(V,: 8 to 12V)
t1Vo
Load
regulation
V
Tj: 25°C
10:5mAtol.5A
(V,: 9 to 13V)
mV
Tj: 25°C
10= 250 to 750 rnA
'd
Quiescent
T j : 25°C
mA
current
t1'd
Quiescent
lo=5rnAto 1A
current
change
t1Vo
TT
Output
voltage
0.6
10= 5 rnA
1
0.7
mA
mV/oC
1.5
drift
eN
output
noise
B: 10Hz to 100KHz
Tj: 25°C
40
40
40
40
",V
-Vo-
voltage
SVR
Supply
f : 120Hz
voltage
68
65
(V,: 8 to 18V)
(V,: 9 to 19V)
2
2
62
61
(V,: 15 to 25V)
(V,: 11.5 to 21.5V)
dB
rejection
2.5
2.5
Dropout
10= 1A
voltage
T): 25°C
Ro
Output
resistance
f : 1 KHz
17
'se
Short
Vi: 35V
T): 25°C
0.75
1.2
0.75
1.2
2.2
3.3 1.3
2.2
3.3 1.3
Vd
circuit
current
Iscp
Short
Tj: 25°C
1.3
19
eire. peak
cuP'"ent
156
2
2.5
16
0.75
2.2
2
2.5
18
V
mil
1.2
0.75
1.2
A
3.3 1.3
2.2
3.3
A
ELECTRICAL CHARACTERISTICS L 7800
OUTPUT VOLTAGE
INPUT VOLTAGE
(Unless otherwise specified)
Parameter
Va
Output
Test conditions
(continued)
15
18
20
24
23
26
28
33
Unit
Min.
Typ.
Max. Min.
Typ.
Max. Min.
Typ.
T J= 25'C
14.4
15
15.6 17.3
18
18.7 19.2
20
'0""
14.25
15
15.75 17.1
18
18.9 19
20
21 22.8
24
25.2
IV;= 18.5 to 30VI
IV;= 22 to 33VI
IV;= 24 to 35VI
IV;= 28 to 38VI
Max. Min.
Typ.
24
20.8 23
Max.
25
voltage
5 mA to 1 A
Po';;;; l5W
:o.Va
Line
regulation
T J = 25'C
150
IV;= 17.5 to 30VI
180
IV;= 21 to 33VI
200
IV;= 22.5 to 35VI
240
IV;= 27 to 38VI
75
IVj= 20 to 26VI
90
IV;= 24 to 30VI
100
IV;= 26 to 32VI
120
IV;= 30 to 36VI
150
180
200
240
75
90
100
120
6
6
6
6
0.5
0.5
0.5
0.5
0.8
IV;= 18.5to30VI
0.8
IV;= 22 to 33VI
0.8
IV;= 24 to 35VI
0.8
IV;= 28 to 38VI
V
rnV
6.V a
Load
regulation
T J = 25'C
10= 5 mA to 1.5A
rnV
T j = 25°C
'0=
Id
Quiescent
250 to 750 mA
T j = 25'C
rnA
current
6. l d
Quiescent
'o==5mAtolA
current
change
6.V a
Output
c;:T
voltage
drift
eN
output
nOIse
10= 5 mA
1.8
2.3
2.5
3
B= 10Hz to 100KHz
T j = 25°C
40
40
40
40
rnA
rnV/oC
~V
-Va
voltage
SVR
Supply
f = 120 Hz
voltage
rejection
Vd
Ra
60
IV;=18.5 to 28.5VI
2
Dropout
10= lA
voltage
Tj'= 2SoC
Output
f = 1 KHz
19
V;= 35V
T j = 25°C
0.75
59
58
IV;= 22 to 32VI
2.5
2
56
dB
IV;= 24 to 35VI
IV;= 28 to 38VI
2
2
2.5
2.5
28
24
22
2.5
V
rnD
resistance
I"
Shart
circuit
1.2
0.75
1.2
0.75
1.2
0.75
1.2
A
2.2
3.3
A
current
tscp
Short
.T j = 25°C
1.3
2.2
3.3 1.3
eire. peak
current
157
2.2
3.3 1.3
2.2
3.3 1.3
o to
ELECTRICAL CHARACTERISTICS L 7800C (Refer to the test circuits, Tj
10 = 500 mA, Cj = 0.33 JlF, Co = 0.1 JlF unless otherwise specified)
OUTPUT VOLTAGE
INPUT VOLTAGE
(Unless otherwise specified)
Parameter
Vo
Output
Test conditions
Min.
5
6
8
12
10
11
14
19
Typ.
5
Max. Min.
5.2 5.75
Typ.
Max. Min.
Typ.
6
6.25 7.7
S
Max. Min.
S.3 11.5
125°C,
Unit
Typ.
Max.
12
12.5
T J = 25'C
4.S
lo""5mAtolA
4.75
5.25 5.7
12
12.6
6
6.3 7.6
5
S
S.4 11.4
(V i = 14.5 to 27VI
(V i = 7 to 20VI
(V j "" 8 to 21 V)
(V i = 10.5 to 25VI
voltage
Po";; 15W
:c,V o
Line
regulation
100
3
(V i = 7 to 25VI
120
(V i = S to 25VI
160
(V i =10.5t025VI
240
(V i = 14.5to30VI
1
50
(V i = S to 12VI
60
SO
(V i = 11 to 17VI
120
16 to 22VI
T J= 25'C
~Vo
Load
T j = 25'C
regulation
10= 5 mA to 1.5A
V
mV
(V i = 9 to 13VI
(V i =
100
120
160
240
50
60
SO
120
S
8
8
S
0.5
0.5
0.5
0.5
mV
T j = 25'C
10= 250 to 750 mA
Id
Quiescent
T j = 25'C
rnA
current
L.ld
Quiescent
lo=5mAtolA
current
change
-~
6T
eN
Output
10= 5 rnA
Output
Supply
B'" 10Hz to 100KHz
TJc 25'C
f=120Hz
voltage
rejection
Vd
1
1
rnA
(Vj= 8 to 25V)
(V i = 10.5 to 25VI
(V i = 14.5to30VI
-1.1
-O.S
-O.S
-1
mV/'C
40
45
52
75
MV
(V i = S to lSVI
(V i = 9 to 19VI
56
(V i = 11.5 to 21.5V)
2
2
2
2
V
voltage
drift
noise
voltage
SVR
1.3
1.3
(Vi= 7 to 25Vj
Dropout
10= lA
62
59
dB
55
(V i = 15 to 25VI
voltage
Ro
Output
resistance
f = 1 KHz
17
19
16
18
mil
I,c
Short
Vi= 35V
T j = 25'C
750
550
450
350
rnA
T j = 25'C
2.2
2.2
2.2
2.2
A
circuit
current
Iscp
Short
eire. peak
current
158
ELECTRICAL CHARACTERISTICS L 7800C
OUTPUT VOLTAGE
15
18
20
24
INPUT VOLTAGE
(Unless otherwise specified)
23
26
28
33
Output
Max. Min.
Typ.
Unit
Max.
Min.
Typ.
Max. Min.
Typ.
Max. Min.
Typ.
T j " 25°C
14.4
15
15.6 17.3
18
18.7 19.2
20
lo""5mAto lA
21
14.25
15
15.75 17.1
18
18.9 19
20
IV;" 23 to 35VI
IV;" 17.5 to 30VI
IV;" 21 to 33VI
22.8
24
25.2
IV;" 27 to 38VI
400
480
IV;" 27 to 38VI
Test conditions
Parameter
Va
(continued)
20.8 23
24
25
voltage
Po';;;; 15W
"Va
Line
regulation
300
IV;" 17.5 to 30VI
360
IV;" 22.5 to 35VI
IV;" 21 to 33VI
TJ" 25°C
"Va
Load
regulation
V
rnV
240
IV;" 30 to 36VI
200
150
IV;" 20 to 26VI
180
IV;" 24 to 30VI
TJ" 25°C
r a '" 5 rnA to 1 .5A
300
360
400
480
T j " 25°C
150
180
200
240
8
8
8
8
0.5
0.5
0.5
0.5
IV;" 26 to 32VI
rnV
10
Id
Quiescent
::'
250 to 750 rnA
T j " 25°C
rnA
current
"Id
Quiescent
lo=5mAto lA
current
change
~
"T
Output
1
1
1
1
rnA
IV;" 17.5t030VI
IV;" 21 to 33VI
IV;" 23 to 35VI
IV;" 27 to 38VI
10= 5 rnA
-1
-1
-1
-1.5
rnV/oC
90
110
150
170
~V
voltage
drift
eN
Output
noise
voltage
B= 10Hz to 100KHz
T j " 25c C
SVR
Supply
f"120Hz
54
53
dB
50
52
voltage
rejection
Vd
Dropout
2
V
24
28
rnn
200
180
150
rnA
2.1
2.1
2.1
A
10= 1A
2
2
2
f = 1 KHz
19
22
Vi'" 35V
T j "25°C
230
2.1
voltage
Ro
Output
i
resistance
Iso
Short
circuit
current
Isep
Short
Tj
~
25°C
eire. peak
current
159
Fig. 4 - Dropout voltage vs.
junction temperature
Fig. 5 - Peak output current
vs. input/output differential
voltage
i""r--i""-... -...: :::-..
'.5
t-f-
t--
2.5
~
rr--t.ljjjjH-r++I+8---i-m,+1I-+Htflill
'1111
I
,II
!.
I
r-::: ::-- ~
DROPOUT CONDITIONS
AVo:OSo,. of Vo
05
(A,
- J",.
---t--
::rTTlmTi,~~'TImII~TITI!m-Tlrll'~i1i~
eo • i
II'! III +t+l,++i'#--'--"80-"-5+ti+llI
till II F '
(0
L 78XX
IV'
Fig. 6 - Supplv voltage
rejection vs. frequency
60
l
1.5
20~
40
~
20
--4 '. ..~ ~.
:Jltiil ~t:""",_t.idI8..v-Hlt-t+tttt1lt--+++ti+llI
111
. 1,IIil ~;"'C"
0.5
Hili
-75 -50 -25
0
25
50
75
100
125,
Tj
re)
Fig. 7 - Output voltage vs.
junction temperature
'lfll'!l
(rnA)
f-
10
4.2
H;;;):
I
I-- - .
50
75
100
125
Fig. 10 - Load transient
response
''Ie
(V)
G 2971
I
r- rlv
%= v
(0
I
(AI
I
r-
i
.v
Fig. 11
response
I,
, I
.1-.
,
i
-+t=
~
,
V
I
,
!
r- -H~
10
G-291211
,
INPUT VOlTAGE
I
I
!
•
-50 -25
I
I
0
2S
i
L780S
50
75
I I
100
125
Tj (Oe)
Fig. 12 - Quiescent current
vs. input voltage
v,
(
v,
L7805
15
i
I
20
..i
(Q
I
I
10
I
~~mTo~TAGEI
I"-
,
I
~1O
I
Io-SOOmA
I
I
I
'SV
I
20
-15
Line transient
0
I
OUTPUT VOLTAGE
DEVIATON
10'
(m' I
L 7805
LOAD CURREN
10'
10'
Tj (oe)
-+-
-+tt-t
l
,
25
I I I :.
mtt'
+~++ H
%1
/
3.6
0
I
/ i I
4.0
3.8
+-
G-297"
'd
(11) ~
-75 -50 -25
f (Hz)
)()'
Fig. 9 - Quiescent current
vs. junction temperature
Fig. 8 - Output impedance
vs. freauency
20
1I11
10'
10
~
~20
50 t (us)
o
I
i
10
160
t{JJs)
10
20
25
30
Vi (V)
APPLICATION INFORMATION (continued)
Fig. 13 -
Fig. 14 -
Fixed output regulator
Costant current regulator
V;
Notes:
(1) To specify an output voltage, substitute voltage
value for "XX".
(2) Although no output capacitor is needed for stability, it does improve transient response.
(3) Required if regulator is located an appreciable
distance from power supply filter.
Fig. 15 - Circuit for increasing output voltage
vxx!
IFig. 16 -Adjustable output regulator (7 to 30V)
R1
R2
Fi~.
17 - 0.5 to 10V regulator
Fig. 18 - HiQh current voltage regulator
VBEQ1
161
APPLICATION INFORMATION (continued)
Fig. 19 - High output current with short
circuit protection
Fig. 20 - Tracking voltage regulator
'\10
COMMON
~
-Vo
Fig. 22 - Negative output voltage circuit
Fig. 21 - Split power supply (±15V - 1A)
+20VC)--'---'-I
F--~>---'-O
- 20Vo--""'--"l
r--4-......-o·15V·
+ 15 V
JI
• Against potential latch-up problems
Fig. 24 - High input voltage circuit
Fig. 23 - Switching regulator
162
APPLICATION INFORMATION (continued)
Fig. 25 - High input voltage circuit
Fig. 26 - High output voltage regu lator
Fig. 27 - High input and output voltage
Fig. 28 -
Reducing power dissipation with
dropping resistor
R = ~mjn)
-
Vxx -
lo(max)
Fig. 29 - Remote shuntdown
163
+
VOROP(max)
Id(max)
APPLICATION INFORMATION (continued)
Fig. 31 - Adjustable output voltage with temperature compensation
Fig. 30 - Power AM modulator (unity voltage
gain, 10 ';;; 1A)
.v;o-!j
L 7BXX
Ir'---t----<
13
!
Q1
~~3 C&-r--t---'
5-4117"
Note:
Note: The circuit performs well up to 100 KHz.
02 is connected as a diode in order to
compensate the variation of the 01
VBE with the temperature. C allows a
slow rise-time of the V0
R2
Vo= Vxx (1 + - - I +VBE
R1
Fig. 32 - Light controllers (V o
min=
Vxx + V BE )
(b)
(a)
V;
v
0
falls when the Ii!lht !loes up
Vo
rises when the light goes up
Fig. 33 - Protection against input short-circuit with high capacitance loads
Applications with high capacitance loads and an
output voltage greater than 6 volts need an external
diode (see fig. 33) to protect the device against
input short circuit. In this case the input voltage
falls rapidly while the output voltage decreases
showly. The capacitance discharges by means of the
Base-Emitter junction of the series pass transistor
in the regulator. If the energy is sufficiently high,
the transistor may be destroyed. The external diode
by-passes the current from the Ie to !lround.
164
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
3- TERMINAL POSITIVE VOLTAGE REGULATORS
• OUTPUT CURRENT UP TO 0.5A
• OUTPUT VOLTAGES OF 5; 6; 8; 12; 15; 18; 20; 24V
• THERMAL OVERLOAD PROTECTION
• SHORT CIRCUIT PROTECTION
• OUTPUT TRANSISTOR SOA PROTECTION
The L78MOO series of three-terminal positive regulators is available in TO-220 package and with several
fixed output voltages, making it useful in a wide range of applications. These regulators can provide local
on-card regulation, eliminating the distribution problems associated with single point regulation. Each
type employs internal current limiting, thermal shut-down and safe area protection, making it essentially
indestructible. If adequate heat sinking is provided, they can deliver over 0.5A output current. Although
designed primarily as fixed voltage regulators, these devices can be used with external components to
obtain adjustable voltages and currents.
ABSOLUTE MAXIMUM RATINGS
DC input voltage (for V 0 = 5 to 18V)
(for Vo = 20, 24V)
Output current
Power dissipation
Storage tem peratu re
Operating junction temperature
MECHANICAL DATA
35
V
40
V
Internally limited
Internally limited
-65 to +150
°C
Oto+150
°C
Dimensions in mm
165
6/82
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
s- 1'j66fl
Ordering Numbers
Output Voltage
L78M05CV
L78M06CV
L78M08CV
L78M12CV
L78M15CV
L78M18CV
L78M20CV
L78M24CV
5V
6V
8V
12V
15V
18V
20V
24V
BLOCK DIAGRAM
166
SCHEMATIC DIAGRAM
r-~~----------~--------~----~--~------~----OIN
R9
R4
RI3
02
R5
~~-----+--4-------~----~~---oOUT
R6
D1
TEST CIRCUITS
Fiq. 1 - DCparameters
Fiq. 3 - Ripple rejection
Fig. 2 - Load regulation
JL
30~s
Vo
ov
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
max
max
167
3
50
ELECTRICAL CHARACTERISTICS L78MOOC(Refer to the test circuits,Tj =25°C, 10= 350mA
unless otherwise specified, Ci = 0.33 J.1F, Co = 0.1 J.1F)
OUTPUT VOLTAGE
INPUT VOLTAGE
(Unless otherwise specified)
Parameter
Vo
Test conditions
Output
Min.
4.8
5
6
8
12
10
11
14
19
Typ.
5
Max.
Min.
5.2
5.75
Typ. Max.
6
6.25
Min.
7.7
Typ.
8
Unit
Max.
Min.
Typ.
Max.
8.3
11.5
12
12.5
voltage
10= 5 to 350 mA
6V o
Line
regulation
10= 200 mA
4.75
5
5.25
(V;= 7 to 20VI
5.7
6.3
6
(V;= 8 to 21VI
7.6
8
8.4
(V;= 10.5 to 23VI
11.4
12
12.6
(V;= 14.5 to 27V1
100
(V;= 7 to 25VI
100
IV;= 8 to 25VI
100
IV;= 10.5 to 25VI
100
IV;= 14.5 to 30VI
50
IV;= 8 to 25VI
50
IV;= 9 to 25VI
50
IV;= 11 to 25VI
50
IV;= 16 to 30VI
100
120
160
240
50
60
80
120
6
6
6
6
0.5
0.5
0.5
0.5
0.8
IV;= 8 to 25VI
0.8
(V;= 9 to 25VI
0.8
(V;= 10.5 to 251
0.8
IV;= 14.5 to 30VI
V
mV
6V o
Load
10= 5 mA to 0.5A
regulation
mV
10= 5 mA to 200 mA
Id
Quiescent
current
61 d'
Quiescent
10= 5 mA to 350 mA
current
change
6V o . Output
6T
Voltage
10= 200 mA
10= 5 rnA
T j = 0 to 125°C
mA
mA
-0.5
-0.5
-0.5
-1.0
mVtc
40
45
52
75
!-IV
56
IV;=11.5 to 21.5VI
55
(V;= 15 to 25VI
dB
drift
eN
Output
noise
B= 10Hz to 100KHz
voltage
SVR
Supply
voltage
rejection
Vd
Dropout
voltage
Ise
Short
circuit
f= 120Hz
10= 300 mA
V;= 35V
62
IV;= 8 to 18VI
59
IV;= 9 to 19VI
2
2
2
2
V
300
270
250
240
mA
700
700
700
700
mA
current
Isep
Short eire.
peak
current
168
ELECTRICAL CHARACTERISTICS L78MOOC (continued)
OUTPUT VOLTAGE
INPUT VOLTAGE
(Unless otherwise specified)
Parameter
Vo
Test conditions
Output
Min.
14.4
15
18
20
24
23
26
29
33
Typ.
Max.
Min.
Typ.
Max.
15
15.6
17.3
18
18.7
Min. Typ.
Max.
Min.
19.2
20.8
23
20
Typ.
24
Unit
Max.
25
Voltage
/oVO
line
10= 5 to 350 mA
14.25 15 15.75
(V;= 17.5 to 30V)
17.1
18
18.9
(V;= 20.5 to 33V)
19
20
21
(V;= 23 to 35V)
22.8
24
25.2
IV;= 27 to 38VI
10= 200 mA
100
IV;= 17.5 to 30V)
100
IV;= 21 to 33V)
100
IV;= 23 to 35V)
100
IV;= 27 to 38VI
50
IV;= 20 to 30VI
50
IV;= 24 to 33VI
50
IV;= 24 to 35V)
50
IV;= 28 to 38VI
10= 5 mA to 0.5A
300
360
400
480
10= 5 mA to 200 mA
150
180
200
240
6
6
6
6
0.5
0.5
0.5
0.5
0.8
IV;= 17.5 to 30V)
0.8
IV;= 21 to 33V)
0.8
IV;= 23 to 35V)
0.8
IV;= 27 to 38V)
regulation
V
mV
/OVo
Load
regulation
Id
mV
Quiescent
current
/Old
Quiescent
10= 5 mA to 350 mA
current
/oVo
/OT
eN
SVR
change
10= 200 mA
Output
voltage
drift
T amb =
Output
noise
voltage
B= 10Hz to 100KHz
Supply
voltage
mA
mA
100;: 5 mA
a to 125°C
f=120Hz
10= 300 mA
-1
-1.1
-1.1
-1.2
mVtc
90
100
110
170
!'V
54
IV;= 18.5 to 28.5V)
53
IV;= 22 to 32V)
53
IV i = 24 to 34V)
50
IV;= 28 to 38V)
dB
2
2
2
2
V
240
240
240
240
mA
700
700
700
700
mA
rejection
Vd
Dropout
Voltage
Ise
Iscp
Short
circuit
current
Vi= 35V
Short eire.
peak
current
169
Fig. 4 - Dropout voltage vs.
junction temperature
Fig. 5 - Dropout charac·
teristics
G-46\9
-416
"I-Vo
"
L78MXX
(V)
1.5
--
'"'-
tovo"S'" of Vo
--
our =100mA
i
OmA
16UT"OV
j
I
20~
L76MOS
!
~itt
200rnA
t--i---
DROPOUT CONDITIONS
i
IV 1
r--I- ~A
r--r-::: :.- r- I--r--: :-- ~
'"'-
t/"i
-25
0
25
50
75
100
Tj
'i
~
i
<::::
i I'" I:::-,
i
Fig. 9 - Quiescent current
vs. junction temperature
Fig. 8
Supply voltage
rejection vs. frequency
S,R r-r-TTTTn-"""11T~"rmn-ni'iWr\,
L78M12
G-H2:;:
0
I
!
ImA I
(dB)
L78M05
jVIN .1OV
I·····;:...t'
'-..J
0
'"
I
1
I
r
I
!
60
45
"-
1
11.92
lOUT =200mA
I
I
ill
11.8 4
H~OUT:5V
.- - - r--
I
12.0
~;~~ 1"-': ~"
0'0
0.2
10
G-4520
.
-...;::~
04
('e)
Fig. 7 - Output voltage vs.
junction temperature
I
~
b-
ti
125
~
Y
06
11 ilL
!
I
1
--.
I
/1/
~
--...
0.8
y/ I
))1
-50
Fig. 6 - Peak output current
vs. input-output differential
voltage
I,
I
(A I
...... r---...
r--
I-
i
"
f-
"
I
1'-.'
I
-15
-50 -25
0
Fig. 10
25
SO
75
100
10
125 TJ rOC)
Load transient
10'
Fig. 11
10'
D'
f (Hz)
-75 -50 -25
'0
IAl
25
50
75
100
125
TJ(OCl
Fig. 12 - Quiescent current
vs. input voltage
Line transient
I,
0
ImA
,
G--1,1>25
I I
+
I
78M05
I~ou,:·
--iI;5'(
I I
/1
I
1
I
I
I
I
I I
I
j
I
I
I I
170
10
1+-I e--+-L
I
I
,
I
I i ,-
I I
t {JJs)
I
I
I
I I
10
I
15
20
APPLICATION INFORMATION (continued)
Fig. 13 -
Fig. 14 - Costant current regulator
Fixed output regulator
Vi
Notes:
(1) To specify an output voltage, substitute voltage
value for "XX".
(2) Although no output capacitor is needed for stabil ity, it does improve transient response.
(3) Required if regulator is located an appreciable
distance from power supply filter.
Fig. 1.5 - Circuit for increasing output voltage
vxxl
5-4962
Fig. 16 -Adjustablf:' output regulator (7 to 30V)
R1
R2
Fi!1. 17 - 0.5 to 10V regulator
Fig. 18·- Hiqh current voltage regulator
1-'--+--0 v,
'c;l--,."...---.J
-..;
O.1,uF
171
APPLICATION INFORMATION (continued)
Fig. 19 - High output current with short
circuit protection
Fig. 20 - Tracking voltage regulator
,\10
COMMON
Vo
~
a1 =80534
02 2N6124
=
4.7kO
5-1,966
-Vo
Fig. 21 - Positive and negative regu lator
Fig. 22 - Negative output voltage circuit
JI
(*) D1 and D2 are necessary if the load is connected
between + V0 and - V 0
Fig. 23 - High input voltage circuit
Fig. 24- High input voltage circuit
Vo
Vo
172
APPLICATION INFORMATION (continued)
Fig. 25 - High output voltage regulator
Fig. 26 - High input and output voltage
Vo
5-497)
Fig. 27 -
Fig. 28 - Remote shuntdown
Reducing power dissipation with
dropping resistor
oj
Vi
0---r--V'-v-ri
R,
R=
Vi(min) -
Vxx -
lo(max)
+
1--",--'
VDROP(max)
Id(max)
Fig. 29 - Power AM modulator (unity voltage
gain, 10 < 0.5)
Fig. 30 - Adjustable output voltage with tern·
perature compensation
Note:
Note: The circuit performs well up to 100 KHz.
Q 2 is connected as a diode in order to
compensate the variation of the QJ
V BE with the temperature. C allows a
slow rise-time of the V 0
R2
Vo= Vxx (1 + - - ) + V BE
R1
173
APPLICATION INFORMATION
Fig. 31 - Light controllers (V 0
min =
(continued)
V XX + V BE)
(a)
(b)
v,
Vi
v0
Vo falls when the li!lht ooes up
rises when the light goes up
Fig. 32 - Protection against input short-circuit with high capacitance loads
Vi
Applications with high capacitance loads and an output
voltage greater than 6 volts need an external diode (see fig.
32) to protect the device against input short circuit. In this
case the input voltage falls rapidly while the output voltage
decreases showly. The capacitance discharges by means of
the Base-Emitter junction of the series pass transistor in the
regulator. If the energy is sufficiently high, the transistor may
be destroyed. The external diode by-passes the current from
the Ie to ground.
174
LINEAR INTEGRATED CIRCUITS
3- TERMINAL POSITIVE VOLTAGE REGULATORS
•
•
•
•
•
OUTPUT CURRENT UP TO 2A
OUTPUT VOLTAGES OF 5; 7.5; 9; 10; 12; 15; 18; 24V
THERMAL OVERLOAD PROTECTION
SHORT CIRCUIT PROTECTION
OUTPUT TRANSISTOR SOA PROTECTION
The L78S00 series of three-terminal positive regulators is available in TO-220 and TO-3 packages and
with several fixed output voltages, making it useful in a wide range of applications. These regulators can
provide local on-card regulation, eliminating the distribution problems associated with single point
regulation. Each type employs internal current limiting, thermal shut-down and safe area protection,
making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 2A output
current. Although designed primarily as fixed voltage regulators, these devices can be used with external
components to obtain adjustable voltages and currents.
ABSOLUTE MAXIMUM RATINGS
10
P tot
Tstg
Top
DC input voltage (for Va = 5 to 18V)
(for Va = 24V)
Output current
Power dissipation
Storage temperature
Operating junction temperature (for L78S00)
(for L78S00C)
V
35
40
V
internally limited
Internally limited
-65 to + 150
°C
-55 to +150
°C
o to + 150°C
Dimensions in mm
MECHANICAL DATA
TO-3
175
6/82
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
s,- 1568/1
Type
TO-220
TO-3
Output voltage
L 78S05
L 78S05C
L 78S75
L 78S75C
L 78S09
L 78S09C
L 78S10
L 78S10C
L 78S12
L 78S12C
L 78S15
L 78S15C
L 78S18
L 78S18C
L 78S24
L 78S24C
L 78S05CV
L 78S05T
L 78S05CT
L 78S75T
L 78S75CT
L 78S09T
L 78S09CT
L 78S10T
L 78S10CT
L 78S12T
L 78S12CT
L 78S15T
L 78S15CT
L 78S18T
L 78S18CT
L 78S24T
L 78S24CT
5V
5V
7.5V
7.5V
9V
9V
10V
10V
12V
12V
15V
15V
18V
18V
24V
24V
-
L 78S75CV
L 78S09CV
L 78S10CT
L 78S12CV
L 78S15CV
L 78S18CV
L 78S24CV
BLOCK DIAGRAM
I~.~PU~T_ _~______________________~~
176
SCHEMATIC DIAGRAM
TEST CIRCUITS
Fiq. 1 - DC parameters
Fig. 2 - Load regulation
Fiq. 3 - Ripple rejection
THERMAL DATA
Rth j-case
Rth j-amb
max
max
Thermal resistance iunction-case
Thermal resistance junction-ambient
177
TO-220
TO-3
3°C/W
50°C/W
4°C/W
35°C/W
•
..
,
ELECTRICAL CHARACTERISTICS L78S00 (Refer to the test circuits, Tj = 25°C, 10= 500 mA
unless otherwise specified)
5
7.5
9
10
10
12.5
14
15
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
7.15
8.65
9.35
9.5
9
9.4
(Vi~ llV)
9.4
OUTPUT VOLTAGE
INPUT VOLTAGE
(Unless otherwise specified)
Test conditions
Parameter
Ou'tput
Vo
4.8
5
5.2
4.75
5
5.25
7.5
7.9
9
10
Unit
10.5
V
voltage
lo~
lA
(V;~
{No
Line
regulation
7.1
7V)
(Vi~
100
7 to 25V)
(Vi~
50
8 to 12V)
7.5
7.95
(Vi~ 9.5V)
(Vi~
120
9.5 to 25V)
8.6
(Vi~
130
11 to 25V)
(Vi~
65
11 to 20V)
10
10.6
(Vi~ 12.5V)
(Vi~
200
12.5 to 30V)
rnV
rw
0
Load
lo~
20 rnA to 2A
(Vi~
60
10.5 to 20V)
(Vi~
100
14 to 22V)
100
120
130
150
rnV
8
8
8
8
rnA
0.5
0.5
0.5
0.5
regulation
Id
Quiescent
current
llid
Ouiescent
lo~
20 rnA to lA
lo~
20 rnA
current
change
rnA
(V;~
llVo
llT
Output
voltage
lo~
Ti~
5 rnA
-55 to 150"C
1.3
7 to 25V)
(Vi~
1.3
9.5 to 25V)
(Vi~
1.3
11 to 25V)
(V;~
1
12.5 to 30V)
-1.1
-0.8
-1
-1
rnV/"C
40
52
60
65
p.V
drift
eN
Output
noise
B~
10Hz to 100KHz
voltage
SVR
Supply
f
~
120 Hz
60
54
53
53
dB
8
10.5
12
13
V
voltage
rejection
Vi
Operating
input
voltage
10
Ro
Output
resistance
f
Ise
Short
circuit
~
';;
1.5A
1 KHz
17
16
17
17
500
500
500
500
rnH
rnA
Vi
~
27V
current
Iscp
Short eire.
peak
3.5
3.5
current
178
3.5
3.5
A
ELECTRICAL CHARACTERISTICS L78S00 (continued)
I
!
'----
OUTPUT VOLTAGE
12
INPUT VOLTAGE
(Unless otherwise specified)
19
Test conditions
Parameter
Va
Output
r
Min.
Typ.
Max.
Min.
11.5
12
12.5
14.4
15
18
24
23
26
33
Typ. Max.
15
15.6
Min.
17.1
Typ. Max.
18
18.9
Min.
23
Typ.
24
Unit
Max.
25
vol tage
10
. Vo
-
1A
14.25 15 15.75
(Vi= 17.5VI
17
18
19
(Vi= 20.5VI
24
25.2
22?
(Vi= 27VI
240
IVi" 14.5 to 30VI
300
(Vi" 17.5 to 30VI
360
(V,= 20.5 to 30VI
480
(Vi= 27 to 38VI
120
(Vi= 16 to 22VI
150
IV,= 20 to 26VI
180
(V," 22 to 28VI
240
(V;= 30 to 36VI
160
180
200
250
mV
8
8
8
8
mA
0.5
0.5
0.5
0.5
1
(V;" 14.5 to 30VI
(V;" 17.5 to 30VI
(V,= 22 to 33VI
(Vi= 28 to 38V)
-1
-1
-1
-1.5
mVI"C
75
90
110
170
~V
Line
regulation
mV
I
~VO
Load
V
11.4
12
12.6
(V,= 14.5VI
10= 20 "IA to 2A
regulation
Id
Qu ie5cent
current
61d
Quiescent
current
lo=20mAtolA
change
10= 20mA
l6;1-
Output
10= 5mA
voltage
T amb'" 0
II eN
Output
nOise
to
7CYC
1
1
1
mA
drift
B= 10Hz to 100KHz
vol tage
SVR
Supply
f=120Hz
53
52
49
48
dB
10'C 1.5A
15
18
21
27
V
vol tage
reJectton
V,
Operating
Input
voltage
Ro
Output
f
=
1 KHz
18
19
22
23
mD.
500
500
500
500
mA
resistance
Isc
Short
circuit
Vi" 27V
current
Iscp
Short eire.
peak
3.5
3.5
current
179
3.5
3.5
A
ELECTRICAL CHARACTERISTICS L78S00C(Refer to the test circuits, Tj = 25°C, 10= 500mA
unless otherwise specified)
OUTPUT VOLTAGE
5
7.5
9
10
INPUT VOLTAGE
(Unless otherwise specified)
10
12.5
14
15
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
7.15
8.65
9.5
Parameter
Va
Output
voltage
Test conditions
I
4.8
I
I
5.2
7.5
7.9
9
9.35
10
10.5
V
10= lA
i
{No
5
Unit
4.75
5.25
5
IV;= 7V)
7.95
7.5
7.1
IV;= 9.5V)
IVi= 7 to 25V)
regulation
9
IVi= llVI
120
100
Line
8.6
(Vi= 9.5 to 25VI
9.4
10
10.6
9.4
IVi= 12.5VI
130
200
(Vi= 12.5 to 30V)
(Vi= 11 to 25VI
rnV
50
(Vi= 8 to 12V)
6V o
Load
10= 20 rnA to 2A
60
(Vi= 10.5 to 20VI
65
IVi= 11 to 20VI
100
(Vi= 14 to 22VI
100
140
170
240
rnV
8
8
8
8
rnA
0.5
0.5
0.5
0.5
regulation
Id
Quiescent
current
61d
Quiescent
current
change
6V a
6T
Output
voltage
10= 20 rnA to lA
1.3
I l o=20rnA
1.3
1.3
1.0
rnA
(Vi= 7 to 25VI
(V; = 9.5 to 25VI
IV; = 11 to 25VI
(Vi= 12.5 to 30VI
-1.1
-0.8
-1
-1
mV/"C
40
52
60
65
MV
10= 5 rnA
T amb= 0 to 7rJ'C
drift
eN
Output
B= 10Hz to 100KHz
noise
voltage
SVR
Supply
voltage
f = 120 Hz
54
48
47
47
dB
10 ';; 1.5A
8
10.5
12
13
V
rejection
Vi
Operating
input
voltage
Ro
Ise
Output
resistance
f = 1 KHz
17
16
17
17
Vi = 27V
500
500
500
500
mil
mA
Short
circuit
current
Is""
Short eire.
peak
3.5
3.5
current
180
3.5
3.5
A
ELECTRICAL CHARACTERISTICS L78S00C (continued)
OUTPUT VOLTAGE
12
15
18
24
INPUT VOLTAGE
(Unless otherwise specified)
19
23
26
33
Test conditions
Parameter
Vo
Output
Typ. Max.
Min.
11.5
12
12.5
11.4
12
12.6
14.5V)
Min.
14.4
Typ. Max.
15
15.6
Min.
Typ. Max.
17.1
18
18.9
Min.
23
Unit
Typ. Max.
24
25
voltage
lo~
lA
(Vi~
6V o
Line
240
14.5 to 30V)
(Vi~
regulation
14.25 15 15.75
(Vi~ 17.5V)
(Vi~
300
17.5 to 30V)
17
(Vi~
(Vi~
18
19
20.5V)
360
20.5 to 30V)
22.8
24
25.2
27V)
V
(Vi~
(Vi~
480
27 to 38V)
rnV
120
(Vi~
6V o
Load
lo~
16 to 22VI
20 rnA to 2A
150
(V i~ 20 to 26V)
180
(V i~ 22 to 28V)
240
(V,~
30 to 36V)
240
300
360
480
rnV
8
8
8
8
rnA
0.5
0.5
0.5
0.5
regulation
Id
Quiescent
current
61d
Quiescent
current
change
'o=20mAto1A
lo~
20 rnA
(V,
6V o
Output
10= 5mA
6T
voltage
drift
Tamb~
Output
B~
eN
~
1.0
14.5 to 30V)
(V,
~
1.0
17.5 to 30V
1.0
(V,
~
20.5 to 30V)
(V,
~
1.0
27 to 38V)
rnA
-1
-1
-1
-1.5
rnV/oC
75
90
110
170
"V
0 to 70°C
10Hz to 100KHz
noise
voltage
SVR
Supply
f~120Hz
47
46
43
42
dB
10
15
18
21
27
V
voltage
rejection
Vi
Operating
';;
1.5A
input
voltage
Ro
Output
f
~
1 KHz
18
19
22
28
rn!l
500
500
500
500
rnA
resistance
Ise
Short
circuit
current
Iscp
Short eire.
peak
Vi
~
27V
3.5
3.5
curren~
181
3.5
3.5
A
F iq. 4 - Dropout voltage vs.
junction temperature
------ ----
G-4386
......... ,....
J
-.......; t--
CON::~
DROPOUT'
oj "0
I
i
i
-50
[Jl
III
2~
lIVo~5·1.
-75
I
-25
0
25
50
75
100
---
"
~"
~:::--
r'--...
f--I~~
L 76505
"R:c_
O'c
<~
,,~
~'c
i0
ISo.('
f-
i
L 16SXX
i
I
11----
2.5
~
.........
-
(A)
r- ~
r- §O!t.
..::::: I:::-- ......
k'- I"
":""
~
"
I
125
Fig. 6 - Supply voltaqe
rejection vs. frequency
<3438511
10
I
r- t-2= F!-
.........
1.5
Fig. 5 - Peak output current
vs. input/output differential
voltage
rc)
Tj
25 V,-Vo(V)
Fig. 7 - Output voltage vs.
j unction temperature
Fig. 9 - Quiescent current
vs. junction temperature
fig. 8 - Output impedance
vs. frequency
0-4389
V.
20
'd
(V)
(nl
(mA)
Vi~19V
l78S12
vidvl
I-- -
Yo=sv
I
I-- -- lo:500mAI
f--+-...,--j-+--j~:~~"mA 1-+---t----1
'"
,
I
/
IO'UMB• •
11.9
'"
-50 -25
0
25
50
75
m
125
Fig. 11
response
Fig. 10 - Load transient
response
G-q92
","0'1
I
I
I
_ Vo=5V
,
- r l-f-
.....
-
rf--
10
L
(A)
.vo
---
r-- - -
lO
--
t- r---
0
-
-_
..
OUTPUT vOLTAGE
Vt
I-r--- ~I--J
1
10
20
30
2S
50
75
-10
+t-
l18S05
f-
Vo = 5'"
~ lo:20tnA
Tj :25 C
------
~
.-
--
.
OUTPUT VOLTAG
DEVIATION
-
r-
-.-
-
1o:5~OIA
I
-20
5
4.0
182
.. -
,..-7
-.
-/-
':"-1-:-
:..-:-- k-
I
--f--
::::pi-"
!
l
L78S05\
I
I
I
3.0
I (;..Is)
TJ('Cl
. .....
!
,/
-
10
(~s)
125
I
10
-~=r
f- f-r-50 t
100
i
G-QSO
'd
(rnA)
r-- --
I
i
-~
20
I
:~E~i~-
0
I
Fig. 12 - Qu iescent current
vs. input voltage
(V)
INPUT VOLTAGE
-50 -25
L 78505
I
1.5
J
_ _o.~IATON
i
-75
Vi
I
1
,
3.6
t (Hz)
10'
I
Line transient
(mV)
L 78505
LOAD CURREN
I
10'
10'
10'
10
Tj (<5V
10= 10 mA to
1.5A
T j = 25°C
bl ADJ
Adjustment pin
current
Vi-Vo= 2.5 to 40V
10= 10 mA to 1.5A
V REF
Reference voltage
(between pin 3 and
pin 1)
Vi-Vo= 3 to 40V
10= 10 mA to 1.5A
Minimum load
current
10 max
Maximum load
current
1.2
Output noise
(percentage of V 0)
SVR
Supply voltage
rejection (*)
Max.
0.01
0.02
0.01
0.04
0.02
0.05
0.02
0.07
5
15
5
25
20
50
20
70
0.1
0.3
0.1
0.5
0.3
1
0.3
1.5
50
100
50
100
}.LA
0.2
5
0.2
5
}.LA
1.25
1.3
1.25
1.3
V
1.2
1
3.5
V i -V o ":;15V
1.5
2.2
1
5
3.5
1.5
%
10
mA
2.2
A
Vi-Vo= 40V
eN
Typ.
Min.
%
Output voltage
temperatu re stab i Iity
10 min
Max.
mV
Adjustment pin
current
Vo
Typ.
%IV
IADJ
bV o
LM 317
Test conditions
0.4
0.4
Ti= 25°C. 10Hz to 10KHz
0.003
0.003
Tj= 25°C CADJ= 0
f= 120Hz
CADJ=10}.LF
65
65
%
dB
66
80
66
80
(*) C ADJ is connected between pin 1 and ground.
Note -
Unless otherwise specified the above specs, apply over the following conditions: LM 117 T j = -55 to 150°C;
LM217 T j =-25to150°C;LM317 T j =Oto125°C.
194
Fig. 1 - Output current vs.
input- output
differential
voltage
Fig. 2 - Dropout voltage vs.
junction temperature
.J _
(-+_.'-i--
-
==: ::-....
;1
Tj ~15~'C
,
,,~
,'f--- - - - - ~,
:
'"
llV o =100mV
I
1.25 0
,
r--
'
--
-
/
Io :l.5A
r-- r-.
-... t--- r-.
r-- r-.t--
Y'_-"jC---
-- ""' ,
~
,
"DRO P
I
) _25'C
!
G" 4631/,
G'A63{)
[,-4629
)
Fig.3 - Reference voltage vs.
junction temperature
5
V
1/
, A
~mA
'"
r"\
\
\
0
I--b
f-
-...~
'2~ f +100
\
1.23 5
Tj(e')
i
-50
+50
-I- 100
'\
T, (C')
APPLICATION INFORMATION
The LM 117/LM 217/LM 317 provides an internal reference voltage of 1.25V between the output and
adjustment terminals. This is used to set a constant current flow across an external resistor divider (see
fig. 4), giving an output voltage Va of:
Fig. 4 - Basic adjustable regulator
Va
=
V REF (1 +
£L)
Rl
+ IADJ R2
The device was designed to minimize the term IADJ (100 J.lA max) and to maintain it very constant with
line and load changes. Usually, the error term IADJ • R2 can be neglected. To obtain the previous
requirement, all the regulator quiescent current is returned to the output terminal, imposing a minimum
load current condition. If the load is insufficient, the output voltage will rise.
Since the LM 117/LM 217/LM 317 is a floating regulator and "sees" only the input-to-output differential voltage, supplies of very high voltage with respect to ground can be regulated as long as the maximum input-to-output differential is not exceeded. Furthermore, programmable regulator are easily obtainable and, by connecting a fixed resistor between the adjustment and output, the device can be used
as a precision current regulator.
In order to optimise the load regulation, the current set resistor Rl (see fig. 4) should be tied as close as
possible to the regulator, while the ground terminal of R2 should be near the ground of the load to
provide remote ground sensing.
No external capacitors are required, but performance may be improved with added capacitance as
follows:
An input bypass capacitor of 0.1 J.lF.
An adjustment terminal to ground 10 J.lF capacitor to improve the ripple rejection of about 15 dB
(C ADJ )·
An 1 J.lF tantalum capacitor on the output to improve transient response.
195
APPLICATION INFORMATION (continued)
In additional to external capacitors, it is good practice to add protection diodes, as shown in fig. 5.
Fig. 5 - Voltage regulator with protection diodes.
lN4001
D1
D1 protects the device against input short circuit, while D2 protects against output short circuit for
capacitors discharging.
Fig. 7 - Current regulator
Fig. 6 - Slow turn-on 15V regulator
~
Rl
Vi
V ref
10= ~+
I
_
1.25V
ADJ = -R-l--
0 0 = 10mAtol.5AI
Fig. 8 - 5V electronic shut-down regulator
Fig. 9 - Digitally selected outputs
.
DIGITAL INPUTS
(R2 sets maximum Vol
196
5-5055/1
APPLICATION INFORMATION (continued)
Fig. 10 - Battery charger (12V).
Fig. 11 - Current limited 6V charger.
Vi
• Rs sets output impedance of charger
R2
Zo ~ Rs (1 + R j )
* R3 sets peak current (O.6A for 1 n).
Use of Rs allows low charging rates with fully
charged battery.
* * C 1 recommended to filter out input transients.
197
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
LOW POWER QUAD OPERATIONAL AMPLIFIERS
•
•
•
•
SINGLE OR SPLIT POWER SUPPLY
VERY LOW POWER CONSUMPTION
INPUT COMMON-MODE RANGE INCLUDING GROUND
LARGE DC VOLTAGE GAIN (100 dB)
The LM 324 consists of four indipendent, high gain, internally frequency compensated opamps specifically designed to operate from a single power supply over a wide range of voltages. Botn in split and in
single supply the current drain is independent of the magnitude of the power supply voltage.
In the linear mode the input common-mode voltage range includes ground and the output voltage can
also swing to ground, even though operating from only a single power supply voltage.
The LM 324 is available in a standard 14-lead dual in-line plastic package and in a 14-lead micropackage
version for thick or thin film hybrid circuits.
ABSOLUTE MAXIMUM RATINGS
VS
Vi
Vi
Ptot
Top
Supply voltage
Input voltage (single supply)
Differential input voltage
Total power dissipation
Operating temperature for: LM 2902
LM324
LM 324A
T stg
Storage temperature
MECHANICAL DATA
6/82
32
-0.3 to 26
32
400
to 70
-25 to 85
-55 to 125
-65 to 150
o
V
V
V
mW
°C
°C
°C
°C
Dimensions in mm
198
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
OUTPUT A
OUTPUT D
INV.INP. A
'3
INV.INP. 0
NON INY. INP. A
12
NONINV,INRD
Type
-Vs
DIP-14
LM 324
LM 324N
80-14
LM 324CM
NON JNV.INRC
LM 324A
LM 324AN
-
INV.INP. B
INV.INP. C
LM 2902
LM 2902N
LM 2902CM
OUTPUT B
OUTPUT C
NON I NV.INP. B
10
:.-
SCHEMATIC DIAGRAM
(one section)
r---------------~--~--~--~--~--u+Vs
RSC
NON-INVERTING
INPUT
Q8
Q9
THERMAL DATA
Rth j-amb
DIP 14
Thermal resistance junction-ambient
max
• Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mm).
199
200°C/W
SO 14
200 0 C/W*
ELECTRICAL CHARACTERISTICS (v. = +5V, Tamb = -55 to 125°C for the LM 324A,
T amb = -25 to 85°C for the LM 324 and T amb = 0 to 700C for the LM 2902, unless otherwise specified)
LM324
Parameter
Supply current
Input bias current
Ib
R L= 00
Vs = 30V
Typ.
Max.
Min.
Typ.
I nput offset voltage
R g= 0
los
Input offset current
Tamb - 25°C
3
1.5
3
1.5
3
0.7
1.2
0.7
1.2
250
45
100
45
±2
200
±7
±2
±9
±5
± 50
Gv
60
nA
±7
± 10
7
30
7
± 5
±30
±5
rnV
Ilv/"e
± 50
nA
±200
10
300
10
40
60
40
"AI"e
60
rnA
to ground current
Large signal open
loop voltage gain
Vs= 15V
RL;> 2 KS1
Tamb = 25°C
88
100
88
83
Vo
±2
±3
±75
10
40
Tamb= 25"e (.)
250
500
±5
7
~ Inp'ut offset current
LIT
drift
Output short circuit
Max.
1.2
±150
Ise
Typ.
1.5
45
Rg= 0
T amb = 25"e
Vs = 5Vt03OV
InRut offset voltage
Min.
rnA
Tamb = 25°C
t:,vos
~drlft
Max.
0.7
500
Vos
LM 2902
Unit
Min.
IS
LM324A
Test conditions
I nput common-mode
voltage range
Vs = 30V
Output voltage swing
T amb = 25"e
T amb = 25"e
100
100
83
0
V s-1.5
0
Vs-1.5
0
V s-1.5
0
Vs-2
0
Vs-2
0
Vs-2
R L = 2 KS1
V s-1.5
V s-1.5
Va sat Output saturation
V
V
R L ;>10KS1
Vs = 30V
dB
83
V s-1.5
R L = 2 KS1
26
R L ;>10KS1
27
22
26
28
RL'; 10 KS1
5
27
20
V
28
5
23
24
5
20
100
rnV
voltage to ground
eMR
Common mode
rejection
T amb = 25°C
65
70
65
85
50
70
dB
SVR
Supply voltage
rejection
T amb = 25"e
65
70
65
100
50
70
dB
es
Channel separation
f = 1 KHz to 20 KHz
T amb = 25"e
(I "put referred)
120
dB
1o '
Output source
current
10
-
Output sink current
Vs = 15V
Vi'= 1V
V i - = OV
VI' = OV
Vi-= 1V
V o= 200 rnV
V I -= 1V
Vi' = OV
Vs= 15V
(*)
T amb = 25"e
120
120
20
40
20
40
20
40
10
20
10
20
10
20
T amb = 25"e
12
50
12
50
Tamb= 25"e
10
20
10
20
10
20
5
8
5
8
5
8
rnA
IlA
rnA
Short circuits from the output to positive supply voltage can cause excessive heating and eventual destruction. The maximum output current is 40 rnA typo independent of the magnitude of Vs. Destructive dissipation can result from simultaneous shorts on all
amplifiers.
200
(, -
~6
"
~6J3
";
I
I,
Fig. 3 - Output short circuit
current vs. ambient temperature
G·
5
Fig. 2 - Input voltage range
vs. supply voltage
Fig. 1 - Supply current vs.
supply voltage
tv
ImA )
J
)
Tamb =2S'C
RL=m
16
I
1.5
,
,
I
0.9
!16
--1
1
;-j '-- ~
V
20
25
"30
1,0
;-jV
03
15
~
~
06
10
Vj
Negative
!12
50
V
30
,
10
~12
"'s(lI)
:!.16
-50
':Vs(V)
50
0
"'5=15V
100
60
1""-
60
100
f-- f--
I
Vo
ImV )
IICl"SOpF
V,.30V
I-------r-'
G~:40dB
16
RL=2K!l.
40 a
" r-
-.C
I""-
"-
10K
OUTPUT
f\v
300
'-..
""-
f(Hz)
1-
'
./
1\
"'\
I
II
350
\
1""-
-tnt-
I
10
'""-
1
Tamb=25'C~- - -
INPUT
12
""-
20
10
V5 =1511
Tamb:2SOC
"- ~
lamb('C)
G-4632
G-HJ6
J
)
100
Fig. 6 - Voltage follower
pulse response (small signal)
Fig. 5 - Large signal frequency response
Fig. 4-0pen loop frequency
response
"-
I
20
!~
'"
25
a
V
1
I
I
10'
APPLICATION INFORMATION
The LM 324 can operate with a single power supply voltage, has true-differential inputs and remains in
the linear mode with an input common-mode voltage of OV. The four included op amps work over a
wide range "Of power supply voltage with little change in performance characteristics. At 2SoC operation
is possible down to a minimum supply voltage of 2.3V.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by
more than 0.3V. The upper end of the common-mode voltage range is Vs -1.5V, but either or both
inputs can go to +32V without damage.
If the voltage at any of the input leads is driven negative (V in < -0.3Vl, the collector-base junction of
the input PNP transitor becomes forward biased and thereby acts as an input diode clamps (max
current: 50 rnA). In addition to this diode action, there is also lateral NPN parasitic transistor action on
the Ie chip. This can cause the output voltage to go to the positive supply voltage level (or to ground for
a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage again returns positive (V in >-0.3V).
The output stage design allows the amplifiers to both source and sink large output currents.
Therefore both NPN and PNP external current boost transistors can be used to extend the power capa201
APPLICATION INFORMATION (continued)
bility of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above
ground to bias the on-chip vertical PNP transistor for output current sinking applications.
Output short circuits either to ground or to the positive power supply should be of short time duration.
Units can be destroyed, not as a result of the short circuit current causing metal fusing, but rather due
to the large increase in IC chip dissipation which will cause eventual failure due to excessive junction
temperature. Putting direct short-circuits on more than one amplifier at a time, the total Ie power dissipation will increase to destructive levels, if not properly protected with external dissipation limiting
resistors in series with the output leads of the amplifiers. The larger value of output source current which
is available at 25°C provides a larger output current capability at elevated temperatures (see typical
performance characteristics) than a standard IC op amp.
The circuits presented in the following section emphasize operation on a single power supply voltage.
If split supplies are used, all the standard op amps configuration can be realised.
TYPICAL SINGLE SUPPLY APPLICATION CIRCUITS (V s = 5V)
Fig. 8 - Power amplifier
Fig. 7 - DC summing amplifier
R1
+Vi n o--1t--I
where: Vo=VI+V2-V3-V4
(VI + V 2 )';;' (V 3 + V4 ) to keep Vo
Fig. 9 - LED driver
> OV
Fig. 10 - Lamp driver
Fig. 11 - Fixed current sources
V'
R2
202
TYPICAL SINGLE SUPPLY APPLICATION CIRCUITS (continued)
Fig. 13 - Ground referencing a differential input signal
Fig. 12 - Comparator with Hysteresis
Hysteresis
I~I
R1
V
rT°
H
VOL~"
VinL
VREF
VinH
R4
5 - 5069
S~5068
R1
VinL= R1+R2
(VOL-VREFI+VREF
R1
VinH = R1+R2
(VOH-VREFI+VREF
Hysteresis=
R1
R 1 + R2
(V OH - V OLI
Fig. 15 - Squarewave oscillator
Fig. 14 - Driving TTL
R1
S - 5071
Fig. 17 - Wien bridge oscillator
Fig. 16 - High input Z, DC differential amplifier
R2
50Kil
+~~._
2
For
R1
R2
Vo= 1+
R4
R3
R4
R3
r-,"
(CMRR depends on this resistor
ratio match)
(V2-V1)
fo
203
=
2
1
RC
7T
I
TYPICAL SINGLE SUPPLY APPLICATION CIRCUITS (continued)
Fig. 18 - Function generator
TRIANGLE WAVE
OUTPUT
SQUARE
>--H:.JWAVE
OUTPUT
f=
Rl + RC , R3=
4CR f Rl
R2 Rl
R2+Rl
Fig. 19 - Bi-Quad filter
1
Rl
fo= 211 RC ; Rl= QR; R2= G BP ;
1
V ref =2" Vs; R3=G N R2; Cl=10C
Example:
fo = 1 KHz
Q= 10
R = 160 K!l
C = 1 nF
Rl= 1.6 M!l
R2= 1.6M!l
R3= 1.6 M!l
Where: G BP= Center Frequency Gain
G N = Passband Notch Gain
R2
204
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
QUAD VOLTAGE COMPARATOR
The lM 339 and the lM 339A are monolithic integrated circuits in a 14-lead dual in-line plastic package
and in a 14-lead micropackage. They consists of four independent precision voltage comparators and are
specially designed to offer a versatility as high as possible; application areas include limit comparators,
AID converters, waveforms generators, high voltage logic gates and so on. Furthermore, the open collec·
tor output stage provides easy interfacing with all types of logic circuitry.
The lM 339/lM 339A main features are:
- Wide supply range (2 to 36V)
Single or split supply operation
Very low current consumption (0.8 rnA, regardless of supply voltage)
Ground input compatibility
Output voltage compatible with TTL, DTl, ECl, MOS and CMOS logic systems
- Output short circuit to ground continuous
ABSOLUTE MAXIMUM RATINGS
Vs
VI
Vi
Ii
Ptot
Top
T stg •
Supply voltage
Input voltage range
Differential input voltage
Input current (V in < -0.3 VdC)
Total power dissipation at Tamb = 25°C
Operating temperature
Storage and junction temperature
±180r+36
-0.3 to 36
36
50
600
a to 70
-65 to 150
V
V
V
rnA
mW
°C
°C
Dimensions in mm
MECHANICAL DATA
205
6/82
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
OUT2
14
OUT 3
OUT 1
13
OUl4
+Vs
12
GNO
11
IN4(+)
DIP14
Type
IN1(-)
4
IN1("')
5
IN4(-)
IN2(-)
6
IN 3(+)
lN2('" )
7
IN3(-)
LM 339
LM 339N
LM 339A
LM 339AN
SO-14
LM 339CM
-
5- 5169
SCHEMATIC DIAGRAM
(each section)
INPUT
(+)
OUT
17:'Y To------+----+--------'
5- 5170
THERMAL DATA
Rth j-amb
DIP-14
max
Thermal resistance junction-ambient
• Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mml.
206
200°C/W
SO-14
200°C/W*
ELECTRICAL CHARACTERISTICS (V s = +5V for the LM 339; Vs
= +15V
for the LM 339A;
T. mb = 25°C, unless otherwise specified)
LM 339A
Parameter
Unit
Typ.
Max.
Input offset voltage At out.switch point
Vo"l.4V;Rg~ 0
Tamb~ 0 to 70"e
VREF~ 1.4 V dc
± 1
±2
I nput bias current
Output in linear
25
(1)
range
Min.
Vas
Ib
los
±5
Tamb~ 0 to 70'e
Input CommanTamb~ 0 to 70'e
(2)
Supply current
RL ~
Voltage gain
R L ;;' 15 Krl
Large signal
± 2
Max.
±5
±9
250
25
250
±50
±5
±50
±150
0
V s-l.5
0
Vs-l.5
0
Vs-2
0
Vs-2
0.8
nA
2
0,8
2
nA
V
mA
106
106
dB
response time
V IN - TTL logic swing;
VREF~ +l.4V; RL ~ 5.1 Krl
V RL ~ 5V
300
300
nsec
RL ~ 5.1 Krl
1.3
1.3
}jsec
Response time (3)
VRL~5V;
10
Output sink current
V IN (-);;' lV;
Va';;; 1.5V
V sat
Output saturation
voltage
V1N(-);;' lV
VIN(+I~ OV
I sink < 4 rnA
10 leak Output leakage
current
Differential input
voltage
V1N(+);;' lV
V 1N (-) ~ OV
94
mV
400
±150
=
Is
Gv
Typ.
400
I npu t offset
Mode voltage range
Min.
±4
Tamb~ 0 to 700 e
cu rrent
Notes:
L339
Test conditions
V 1N (+)- OV;
6
16
250
Tamb~ 0 to 700 e
Va
~
5V
6
500
700
0.1
T amb - 0 to 700
Vo~ 30V
e
All V 1N ;;' OV (or -Vs if split
supply is used);
Tamb~ 0 to 70c e
16
250
mA
500
700
0.1
mV
nA
1
1
I1A
36
36
V
(1)
The direction of the current is out of the Ie due to the PNP input stage. This current is essentially constant, independent of the state of the output, so no loading change exists on the reference or input lines.
(2)
If either input of any comparators goes more negative than 0.3V below ground, a parasitic transistor turns
on causing high input current and possible faulty outputs. This condition is not destructive providing the
input current is limited to less than 50 mAo
(3)
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals
300 nsec can be obtained.
207
APPLICATION INFORMATION
The LM 339 includes four high gain, wide bandwidth devices which, like most comparators, can easily
oscillate if tht! output is inadvertently allowed to capacitively couple to the inputs via stray capacitance.
That occurs during the output voltage transitions, when the comparator changes stat~.
To minimize this problem, PC board layout should be designed to reduce stray input-output coupling;
reducing the input resistors to less than 10 Kn reduces the feedback signal levels and finally, adding even
a small amount (1 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible.
It is good design practice to ground all unused pins.
The differential input voltage may be larger than positive supply without damaging the device. Note that
voltages more negative than -0.3V should not be used: an input clamping diode can be used as
protection.
The output of the LM 339 is the uncommitted collector of a NPN transistor with grounded emitter. This
allows the device to be used like any open-collector gate providing the OR-wide facility.
The output sink current capability is approximately 16 rnA; if this limit is exceeded, the output transistor will come out of saturation and the output voltage will rise very rapidly.
Under this limit, the output saturation voltage is limited by the approximatively 60n rsat of the output
transistor.
Fig_ 1 - Basic comparator
Fig. 3 - Inverting comparator
with Hysteresis
Fig. 2 - Non-inverting comparator with Hysteresis
+V
+V
3KJl
+VREFo----i~
+VINo----I
3K !l
>-+--OVO
5-5118
Fig.4 - Driving C/MOS
Fig. 5 - Driving TTL
+5V
+5V
5-5173
208
APPLICATION INFORMATION (continued)
Fig.6 - AND gate
Fig.7 - OR gate
3 K!l
A "---"-'---A v-'--_~----'
B o--L_}--+----..--l
C ,",---"-L
J
:VST
~VST
"0"
A+ B+C
B~~_r_-~~~
"0"
"1"
Cv-----,_-'--
"1"
5 - 5175
5- 51 7i.
Fig.9 - Squarewave oscillator
Fig. 8 - Large fan-in AND gate
+Vs
4.3 K IL
lOOK IL
Vo + v s T U
o
1=100KHz
5-5177
Fig. 10 - Time delay generator
Fig. 11 - ORing the outputs
... 15 V
10Kll
15KIl.
200Kll
10 K
n
51 Kj)
10K11
+lS;TL..
to
Ve ,
V,N
J!nF
INPUT GATING SIGNAL
'l2[
V3
------
V2
----
v, _
I
~
I
I
to
+15V
oT
to
V,
12
51 Kll
.15V
o
10KIl
e'
14
:
'
t, t,
I
13 '4
lQKJl
+15V
oT
to t,
v,
51 Kll
I
s- 5333
209
APPLICATION INFORMATION
(continued)
Fig. 12 - Peak audio level display
560.n
IN
Fig. 13 - PC Board and component layout of
the circuit of fig. 12
... ,2V
1 K1L
R1
RS
S.8K 11
>-,'4"--_"3-:'d80,("1.4"-V')-----!
R"
68011
13
-1008(0.6V)
5-5160
Fig. 15 - Zero crossing detector (split supplies)
Fig. 14 - Zero crossing detector (single supply)
+lSV
V I Nmin "" O.4V peak for 1% phase distortion (ll ())
D1 prevents input from going negative by more
than O.6V:
R1 + R2 = R3
R3';;
~~
for smaller error in zero crossing
210
LINEAR INTEGRATED CIRCUIT
BALANCED MODULATOR
• SINGLE OR DUAL SUPPLY OPERATION
• LOW POWER CONSUMPTION
• LOW CARRIER LEAKAGE
• LOW DISTORTION
• LOW NOISE
The LS025 is a low noise linear integrated circuit, intended for use as a channel modulator and demodulator in FDM telephone equipments and as analogue AC and DC multiplier in industrial and professional
applications. It features low quiescent power consumption, low distortion and intermodulation. It shows
a typical carrier leakage better than 85 dB throughtout the audio bandwidth. The LS025 is available in
TO-l00 metal case, while the hermetic gold chip (8000 series) is available in SO-14 (14-lead plastic
micropackage). This last version is particularly suitable for professional and telecom applications wherever very high MTBF are required.
ABSOLUTE MAXIMUM RATINGS
TO-100
Supply voltage
Differential input voltage
Operating temperature
Power dissipation at T. mb = 70°C
Storage temperature
J-Lpackage
30V
±5V
-25 to 85°C
520 mW
400 mW
-65 to 150°C
-55 to 150 °C
MECHANICAL DATA
Dimensions in mm
]:lr
211
6/82
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
CARRIER
INPUTS
~,
OUTPUT
MULTIPLIER
14~LTIPLIER
INPUT
[2
INPUT
CARRIER
INPUTS
,
iSIGNAL OR
MULTIPLIER
7
INPUTS
MULTIPLIER
INPUTS
(X AXIS)
INPUT
BIAS
I
SIGNAL OR
9
MULTIPLIER
INPUTS
Type
TO-100
SO-14
LS025
LS 025T
LS025M
LS 8025M
LS 8025
SCHEMATIC DIAGRAM (The pin numbers refer to the ",package version, while the numbers in
brackets refer to the TO-100 version)
6(6)
,----+--c
O.5kfi
L ____+-I---___k
(10)21(7)
_ _ _+_~_~J
~L_o5(5)
9(8)
THERMAL DATA
Rth j-amb
__
I
Thermal resistance junction ambient
TO-100
max
155°C/W
• The thermal resistance is measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mm).
212
SO-14
200* °C/W
ELECTRICAL CHARACTERISTICS (Referred to the circuit of fig.
otherwise specified. The pins correspond to the /Lpackage version)
Parameter
Test conditions
Min.
1; T amb =
Typ.
25°C
unless
Max.
Unit
-30
V
2
2.5
rnA
2
2
4
/LA
/LA
/LA
Vs
Supply voltage range
-12
Is
Supply current
Ib
I nput bias cu rrent
Pins 14-1
Pins 14-2
Pins 8-9
0.7
0.7
1.4
AI
Input offset current
Pins 14-1
Pins 14-2
Pins 8-9
50
70
100
nA
nA
nA
4.5
V
-8
V
Positive input common mode
voltage
Negative input common mode
voltage
Vo
DC output voltage (pin 12)
AVo
Differential output voltage
(pins 11-12)
V ref
I nput biasing reference voltage
(pin 6)
Ri
I nput resistance
Ro
Output resistance
Vo
Output voltage swing
CMR
Common mode rejection
SVR
-3.2
Pins 14-1
Pins 14-2
Pins 8-9
f = 1 kHz
-3.8
-4.6
V
25
100
mV
-7.5
V
30
300
150
k!1
k!1
k!1
3
10
!1
1.3
Vpp
98
dB
CM signal (pins 14-2)
V = 700 mVrms fl= 10 kHz
Diff. signal (pins 8-9)
V = 350 mVrms f2= 40 kHz
86
dB
CM signal (pins 8-9)
V = 350 mVrms fl= 10 kHz
Diff. signal (pins 14-1)
V = 175 mVrms f2= 40 kHz
80
dB
33
dB
80
dB
1
eM signal (pins 14-1)
V = 700 mVrms fl= 10 kHz
Diff. signal (pins 8-9)
V = 350 mVrms f2= 40 kHz
Positive supply voltage
rejection
f = 1 kHz
SVR
Negative supply voltage
rejection
213
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
Typ.
Max.
Scale factor
Gc
Conversion gain
t.G c
Conversion gain change
T amb = 10 to 50"C
Carrier leakage
V m=
4.5
a
Modulating signal leakage
5
Unit
V-I
3.2
K
Vfm
Min.
5.5
dB
± 0.1
dB
-35
-50
dBv
-35
-50
dBmo
-75
dBmo
V (fc±fml
V(2 f m l
V (fc±fml
V (fc±2fml
2nd harmonic modulating
signal leakage
2nd harmonic distortion
--60
-75
dBmo
2nd harmonic d,stortion
-55
-80
dBmo
3rd harmonic distortion
-60
-79
dBmo
-115
-125
dBv
-127
dBv
V (fc±fml
V 2 (fc ±f m l
V (fc±fml
V(fc±3 f m l
V (fc±fml
Low frequ ency thermal noise
High frequency thermal noise
Vm=O
B = 100 Hz
f = 1 kHz
Vm=O
B = 100 Hz
f=30kHz
Fig. 1 - Test and application circuit of modulator with single supply voltage
Working conditions
Vs= -20V
fc=130kHz
fm =25 kHz
Vo= -15 dBv (fc
Vc= -13 dBv
R L = 600 n
214
± fm)
Fig. 2 - Carrier leakage vs.
modulation signal input
offset
Fig. 3 - Conversion gain vs.
frequency
Fig. 4 - Distortion vs. output level
G,r-rr~~TTTmrn-"nITmIIIr-TTITTIm
(dB) f-t+H-+1IIII--++-tffii/tl;;-,,:-'.:-'_""""dB~,It-++ttttll
V• • tIOIl
-100
f-+-+-f-+--+---j:cL ::~z
f-t+H-+1IIII--++-tffiIllVm"·l6dB
-eo
-
12 f-t+H-+1IIII--++-tffiIll~m ::O~H~ -
r---
IIc_·IJdBv
f-+-+-+-f-+-+-+--+-+-I
_2
H-t.+'f-IA-t-++-I!~:I;~:~:
10..-
V
i'""'-'" f--+-+-9--+--j-f--f"-4_dH
H-+'-rTlH-++-HIIc=-IJdBv
H-+++-H-++H~:~~~
L+
10
10
110ft (mV)
Fig. 5 - Carrier leakage adjustment circuit for
system with two supply voltages
12
-votdBv)
Fig. 6 - Carrier leakage vs.
frequency
,dllY' ,..--rTTTTTnr-,--rrrrmr-,-ri'l'mn
.10V
600n
-90 f-++++A'III~.--c"'iithJ...d"'i",,:..'"m_H14
"0 1==
~~r::::::+=I=+=tim
.... 15'1
;-~t-=
I)'
Fig. 9 - Voltage follower
pulse response
Fig. 8 - Large signal frequency respo~s~"
\
100
10'
10'
(V)
:t 15'1
10
10
10
12
1~""
70
~~.~.~.~,~.~.~.-+~~~~~
10
t 10 (mA)
G 4163
0.' t-H-Iftffltt-+t+ttIfllo,.t-Httttff--t-t+1ttttl
"
SIN L
Guaranteed performance characteristics (LS 107/LS 207)
Fig. 10- Input voltage range
vs. supply voltage
arnb"
to
Fig. 12 - Voltage gain vs. supply voltage
Fig. 11 - Output voltage
swing vs. supply
voltage
__ 5 tol15
toll
*_
(V)
"
,0
'"
"
"
.un
80
4
I;
B
10
12
14
6
16!\Is (l/)
8
10
12
14
16 til, (1/)
Guaranteed performance characteristics (LS 307)
Fig. 13 - Input voltage range
vs. supply voltage
Fig. 14 - Output voltage
swing vs. supply
voltage
Fig.15- Voltagegainvs.supply voltage
,,)
"om~stmm
am •
to
(dB)
•
G,
90
ffi~§f~~ff!J~ff~~fl
.01010"(.
POSITIVE
"
'0
t€GATlvE
80
15
6
7
8
9
10
"
12
Il
!I!.(V)
5
6
1
8
9
to
11
12
13 tV,(II)
8
9
10
11
12
lJ !V. (II)
TYPICAL APPLICATIONS
Fig. 16 - Inverting amplifier
R2::
'i~R'
2 _
6
J •
, •• .ill.
0-
~.
R1
Fig. 17 - Non-inverting AC
amplifier
Fig. 18 - Non-inverting amplifier
Rl
RI
RZ
~~,o
,
,0
Vo •
I
]&20
R~,R2
Ri .RJ
RJ • RlIR2
5-2621
235
Vi
v'~'
R)
:'·2622
,
LINEAR INTEGRATED CIRCUITS
FREQUENCY COMPENSATED OPERATIONAL AMPLIFIERS
• NO FREQUENCY COMPENSATION REQUIRED
• SHORT CI RCUIT PROTECTION
• OFFSET VOLTAGE NULL CAPABILITY
• LARGE COMMON MODE AND DIFFERENTIAL VOLTAGE RANGE
• NO LATCH-UP
The LS 141 series consists of general purpose operational amplifiers, intended for a wide range of analog
appl ications. High common mode voltage range and absence of "latch-up" tendencies make the LS 141
series.ideal for use as a voltage foliower.The high gain and wide range of operating voltage provide superior
performance in integrators, summing ampl ifiers, and general feedback applications. The LS 141 series is
available with hermetic gold chip (8000 series). This is particularly suitable for professional and telecom
applications, wherever very high MTBF are required.
ABSOLUTE MAXIMUM RATINGS
TO-99
Vs
Supply voltage
V j (1)
tNj
Top
Input voltage
Differential input voltage
Operating temperature for LS 141/LS 141A
for lS 141C
Output short circuit duration(2)
Power dissipation at T amb = 70°C
Storage temperatu re
Lead soldering temperature
Ptot
T stg
for LS 141/lS 141A
for lS 141C
I
Minidip
I
J.lpackage
±22V
±18V
±15V
± 30V
-55 to 125°C
o to 70°C
indefinite
520mW
400mW
665mW
-65 to 150°C -55 to 150°C -55 to 150°C
300°C (lOs) 260°C (12s)
260°C (5s)
235°C (11s)
1) For supply voltage less than ± 15V, input voltage is equal to the supply voltage
2) The short circuit duration is limited by thermal dissipation
MECHANICAL DATA
6/82
Dimensions in mm
236
CONNECTION DIAGRAMS AND ORDERING NUMBERS
I':
i
I,
""SE'M'LCO'
INVER tNPUf_
Type
2
7
NON INVER
INPUT.
3
6
OUTPUT
-vs
4
5
OFFSET NJLl
TO-99
.Vs
"'FSE''"' O'
IN'o£R INPUT-
2
7
NON INVER
3
6
OUTPUT
-vs
to
5
OFFSET NJLl
INPUT-
+VS
80-8
Minidip
LS 141
LS 141T
-
-
LS 141A
LS 141 AT
-
-
LS 141C
LS 141 CT
LS 141 CB
LS 141 CM
LS 8141
-
-
LS 8141M
LS 8141A
-
-
LS8141 AM
LS8141C
-
-
LS 8141 CM
SCHEMATIC DIAGRAM
R1
R3
lkfl
SOtin
R2
1kfl
5-2059
THERMAL DATA
Rth j-amb
TO-99
Thermal resistance junction ambient
max
155°C/W
* Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mm)
237
Minidip
80-8
120°C/W 200* °C/W
I
ELECTRICAL CHARACTERISTICS (see note)
Parameter
Test conditions
!~141
__
LS141~k
__
LS 141C
Unit
Typ. Max.
Input offset
voltage
T amb = 25°C
R g <;;10kn
Rg <;; 50 n
2
T amb= T min to T max
R g <;;10kn
Rg <;; 50 n
r-------.-.-----
f---[:, Vos
~
In pu t offset
voltage adjust.
range
Vs= ± 20V
Vs= ± 15V T amb = 25°C
-----
~--------r--"
.----....
Average input
offset voltage
Ri
i
20
85
current
Input resistance
T amb = 25°C
3
200
500
30
20
70
I
2
1
30
6
to T max
Large signal
voltage gain
±13
±12
94
nA
80
0.21
80
0.3
2
500
0.8
nA
IJ-A
Mn
Mn
±13
±12
±13
V
86
106
dB
dB
84
±12
±10
±14
±13
V
25
mA
mA
-
238
nA
nA
OC
0.5
±12
200
300
i
I
0.3
T amb= T min to T max
15
0.5
I
T amb = 25°C
T amb= T min to T max
Input voltage
range
±15
-L-L
T amb= T min to T max
~ T amb= T min
Vi
mV
mV
I I I
±_1d_j±10
I
Average input
offset current
drift
Input bias
+-'
'
f---_ _d_rif_t_ - - 1_ _ _ _ _ _ _
Input offset
T amb = 25°C
current
mV
mV
+ 'J J ~-' I-+-i__ _7_.5+-~_~-i
i
_il
6
...•.
V
--'-
90
dB
96
d8
dB
ELECTRICAL CHARACTERISTICS (continued)
LS 141
Parameter
LS 141A
LS 141C
Test conditions
Unit
Min. Typ. Max. Min. Typ. Max.
Min. Typ. Max.
Transient respon. T amb = 25°e
(unity gain)
Rise time
Overshoot
0.3
5
0.25
6
B
Bandwidth
T amb = 25°e
SR
Slew rate
T amb = 25°e
0.5
Is
Supply current
T amb = 25°e
1.7
2.8
Power
T amb = 25°e
Vs= ±20V
Vs= ±15V
50
85
Plot
consumption
0.437
1.5
0.3
0.7
80
Vs= ±20V
T amb = T min
T amb= Tmax
0.8
20
0.3
5
",s
%
MHz
V/",s
0.5
1.7
2.8 mA
50
85
150
165
135
Vs=±15V
T amb= T min
T amb= T max
mW
mW
100
75
60
45
mW
mW
mW
mW
Note: These specifications, unless otherwise specified, apply for V s= ±15V and T amb = -55 to 125°e for LS 141 and
LS 141A. For the LS 141e these specifications apply for Tamb= 0 to 700 e
Fig. 1 - Open loop voltage
gain vs. supply voltage
Fig. 2 - Output voltage
swing vs. supply
voltage
('·Zlll/l
G,
V
(dB)
511,1
lS lloolA.
V
it-
211n
."
32
80
L
LS141A
28
1IJO
V
"
LSI41C
"
'0
LS 141e
20
1/
16
/
90
as
(mW)
R
.05
Fig. 3 - Power consumption
vs. supply voltage
12
20
V
Tamb =2S"C
I
80
11
15
"
239
:t
Vs (v)
.0
15
!Vs (v)
Fig.4 - Open loop voltage
gain vs. frequency
.
Fig. 5 - Open loop phase
response vs. fre·
quency
G-UlO
(f)
(dB )
'0
Fig.6 - Input offset cu rrent
vs. supply voltage
(for LS 141 and
LS 141C)
(nA)
f-- f--..
0
'0
1'\
Vs=:tlSV
"'-
60
-30
"'-
0
20
~
:t15V
T mb :f5
30
1\
-60
"-
v
'\.
20
-90
"-
"'-
l'
t-- r-
-120
'0
-180
1\
.
•. +
·,so
---.!~ -+
2
Fig. 7 - Input resistance and
capacitance vs. fre·
quency(for LS 141
and LS 141C)
Fig. 8 - Output resistance
vs. frequency.
c,
"
S
B
10
Lt·
b;:~;T~
-:;-
I--- I--
12
14
16
tVs{V)
Fig. 9 - Output voltage
swing vs. load resistance
Yo
(pC)
(Vpo)
f-----I-I+++1+1t~--:;,.f--4+++H-tl
24
f--+-+-++++.m--+--+-+++H+l
20
f-----I-I+++1+1t-+++++H_tl
'0
II
Vs-:15V
....
200
•
H-H-Il+ttI-+++ttttll--+t-tt1Itt1f---t1I-H1HH
Tamb""ZS-C
16
"
to' l.....!~.'!J.L!'.L.....!...1..!lfl!lL-+.l.!.LI!.lI!'.L...!-U.llllIlO·'
to'
tol
10"
105
I (Hz)
Fig. 10 - Output voltage
swing vs. frequency
10. 1
10'
Fig. 11 - Input noise voltage
vs. frequency
Fig. 12 - Input noise current
vs. frequency
(~)'I.~I
It;.
Vs:!:.15V
lamb= 25"C
'" H-+++llllI-+f+++llll\l\-+l+l!l!l--+++1JllII
20
I--+l-Itl+ll>-I--++Ijillll-\-+\I+IlliIll----l-l-l+lillll
10. . . . .
16
t2
.,.
101
I
10'
•••
I
10"
105
f(Hz)
w l.....!~.~.~,-+~~-+~~-+~~
10'
f (Hz)
to
to'
'0'
240
t-t--
Fig. 13 - Transient response
Fig. 14 - Common mode reo
jection ratio vs. fre·
quency
G·222?
20
0-2217
eM"
I
I h.
VJ
Vo
6~
Tamb " zs "c
__
10':11_
"L 02kn -
NO ov RSHOOT
(CLSlOOpF)
'~S=OOT
':
10·'
2OOH-++I!!!II-++lj1llll--++++!HII-+~\lII
-.;:::::,
LJL.l...l....L..L..!.-LL.JU...l....L..L.LJ
o
10
20
JO
40
50
60
Gy(dB)
10. . . . . .
10'
10'
10'
10'
249
10'
10'
10'
! (Hz)
(;-221512
RELATIVE
Fig. 32 - Transient response
test circuit
Fig. 31 - Voltage follower
transient response
(unity gain)
Fig. 30 - Frequency characteristics vs. supply
voltage
(;-221311
Vo
I
(mV )
Tam b,,2S"c
10
1.4
90"1.
__ RANSIENT
SLEW RAT
f-:: ~
0.8
16
RESPONSE
"'t-t--l-
"""b::::
r--
V,,=115V
CcdOpF
I
LOSED lOOP BANDWIDTH
R L : 2kO
CL ."OOpF
I
-'-
0.6
I- -r--
-r--
Vi
Tam1b"ZS'C
11~'"
C,
lOpF
- f - RISIE T\t~E
0.4
,5
0.5
10
2
t(us)
Fig. 35 - Large signal feed
forward transient
response
G-lOJ1
Fig. 34 - Feed forward compensation
Fig. 33 - Voltage follower
large-signal pulse
response
(;-221412
v.
Vo
7
I
..L~o-2
OUT
PRECISION
THERMALLY
COMPENSATED
BIAS NETWORK
'" o--.-'4--~-----'
1',.0.
13
252
I"
",c:r+
I '
I
:L-----7~
I
\
I
I
I
I
I
I
I
:L--------C'I~~-_r
I
I
I
I
I
I
I
I
I
I
I
I
~
~
I
I
~!~O~I+-~------~~Jl------~------t_~~
253
THERMAL DATA
Rth i-amb
Plastic
120°C!W
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (Refer
Ceramic
to the test circuit of fig. 1, -Vs= -12V;T amb =25°C
unless otherwise specified)
Parameter
Is
Supply current
R7
Input dynamic biasing resistance
(pin 7)
Gv
Gain
t.G v
Gain variation
B
Bandwith (-3 dB)
Ro
Output resistance
RI·
Input resistance (pin 5)
d
Distortion
d3
Two-tone th ird order
intermodulation
eN
Output noise in psophometric
band
t.IGI
Expansion accuracy after
balancing
10ff
Inhibit current consumption
(pin 2)
G
Amplifier gain
Test conditions
Min.
LI = -14 dBv f = 800 Hz
External time constant
2 Rl • Cl = 20 ms
-1
Tamb= 5 to 55°C
t.V s=±2%
Typ.
Max.
Unit
5
8
mA
60
90
n
0
+1
dB
±0.2
±0.03
dB
dB
500
KHz
25
LI = -14 dBv
f = 800 Hz
f 2 =1020Hz
f1 = 900 Hz
V 1 = V 2 = 88 mV
L i =-40to-l0dBv, f=800Hz
T amb = 5 to 55°C , f = 800 Hz
I nhibit ON (pin 2 grounded)
.·f = 800 Hz
254
-1.5
60
n
100
Kn
0.7
%
0.5
%
-100
dBm
0.1
0.2
0.2
0.3
dB
dB
0.3
1
mA
0
+1.5
dB
TEST AND APPLICATION CIRCUITS
Fig. 1 - Expandor circuit
Fig. 2 - Compressor circuit
4.7kl'l
4.7kn
-12Vo--+---......-"""'4
4.'T5kfi 2.2fJF
100,uF
4.75kl1
OUT
(.) S closed: unity gain amplifier.
S open : expandor.
Fig. 3 - Compandor Characteristics
Fig. 4 - Comparison between LS150 performance (curve A) and limits from CCITT
recommendation (curve B) - Green Book Geneva 1972 - G162.
AG
dB
tll---~
.. 0.75
1
I
1
1
+0.2
-0.2
- - - - -~~26 - - - ~;o --- A- 0 ~4- dS;O_____ ~----- _ _ _ _ _ _ ...J _ _ _ _li
'I
I
I
I
I
I, ",.
255
Fig. 5 - Expandor gain vs. temperature
Y:t-
6G
(d8)
I
tittHu
-I"
+
'
,r
0.3
0.2
G 2305
j Ii,
.--j-
'-+
-~---l---
: ,++r
R+
1[- ttt t~
+~
i-..
0.'
I
"'j-.."
--
Fig. 6 - Transient response
II~'
t
+-
ta .. 3m.
T;
tr '" 15.5ms
+-
-Jlt--.r--
--
•
T:~ r
I-
~o.'
-60
-- ---
I
-0.3
-40
-20
1
20
ill
60
TcawrO
APPLICATION INFORMATION
The fig. 7 shows the basic configuration (with relative signal levels) of a compandorized system.
It is clear the action against the line noise: the system using a compressor in sending and an expandor in
receiving can improve very much the signal-to-noise ratio, especially with very high noise lines_
By using the LS150 it is possible to built both the compressor and the expandor blocks.
Fig. 7 - Compandorized system.
NOl5E
.8dB
OdB --=========::::::::::============::::::::============~8dB
OdB=-'4dBv
-3odB-----~
NOl5E
-GOdB - - - - " / . ''".'
256
~------30dB
~=. .
=.:::::""":::::_ -GOdB
APPLICATION INFORMATION (continued)
The basic block diagram of an expandor is shown in fig. 8. The product of the input voltage Vi and its
mean value Vi (obtained from the rectifier with time constant r) is supplied at the output of an "ideal"
multiplier.
Multiplier
Fig. 8 - Basic expandor circuit.
X
Rectifier
~
~
r-
Vi
5-[,187
The output voltage Va is proportional to the product of V i and V I :
Va= KVixV i
where K is a factor that defines a level for unity gain.
For a constant input level,
Va = KV i X ~= KV;2
Expressing all levels in decibels relative to a reference level:
Va (dB) = 20 IOg10 V? = 2 Vi (dB).
Signals with an input level equal to the reference level are unaffected by the expandor while higher levels
are raised and lower levels attenuated. It is recommended by CCITT, and practically advantageous, that
the unaffected level be - 14 dBv, a voltage corresponding to -14 dBm across 600n. A time constant for
the average rectifier of 20 ms is also recommended, giving "syllabic" operation of the compandor.
Fig. 9 - Basic compressor circuit. Vi _ _ _-\.
r----------
-,
,
I
'I
5-4'88
I
______________ 1
A compressor can easily be implemented with an expandor in the feedback path of an operational amplifier (Fig. 9). Assuming infinite gain for the amplifier:
Vi = KVa x Va
and for a constant input level
Va =
~
K
In decibels, with respect to the unaffected level,
Va (dB) = 20 10glo (VI) y,
257
~
Vi (dB).
i:
APPLICATION INFORMATION (continued)
Design Constraints
There are several constraints on the design of a compandor to be used in telecommunication equipment.
Level: The reference (or unity gain) level is -14 dBv, i.e. 155 mV rms. For application in high-quality
multiplexer transmission systems between exchanges, and expansion accuracy better than 0.2 dB in the
same range (+40 to -25 dBmo) considered by CCITT for all operating conditions is required. These parameters had to be compatible with mass production manufacturing techniques. Particularly when
taking into account the low signal levels, this requirement is very demanding. It was the main target in
designing the device and had a strong influence on the fabrication process, circuit configurations, and
layout.
Power Supply: The circuit has to operate with a single 12V negative supply, unregulated, and with
relatively high noise.
Input Impedance: This has to be precisely defined by an external resistor, which is the passive termination
of an LC filter before the expandor. Thus the input impedance of the IC must be very high. A differential input stage is preferable to reduce ground loop noise.
Gain: The expandor (or compressor) shall not modify the level diagram of existing channel modems,
already optimized for crosstalk and noise. This means that the gain at the unaffected level shall be 0 dB,
with small spread.
Inhibition: It must be possible to inhibit the operation of the compandor for testing and maintenance
purpose, and to allow the transmission of telegraph channels.
Definition of units
dBmo
power level (10 log :: ) is expressed in dBm when P1 is 1 mW, therefore 0 dBm = 1 mW.
dBm
the power is expressed in dBmo when referred to an established power level in the circuit,
generally the output signal level.
e.g.: if the output level is -15 dBm and this level is chosen as reference, then 0 dBmo = -15
dBm; if another signal, i.e. the distortion measured at the same point of the circuit, is
-90 dBm, then the distortion is -75 dBmo.
dBv
20 log V ~ when V 1 = 775 mVrms.
V
258
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
TELEPHONE SPEECH CIRCUIT WITH MUL TIFREOUENCY TONE GENERATOR
INTERFACE
The LS156 is a monolithic integrated circuit in 16-lead dual in-line plastic package to replace the hybrid
circuit in telephone set. It works with the same type of transducers for both transmitter and receiver
(typically piezoceramic capsules, but the device can work also with dynamic ones). Many of its electrical
characteristics can be controlled by means of external components to meet different specifications.
In addition to the speech operation, the LS156 acts as an interface for the MF tone signal (particularly
for M761 C/MOS frequency synthesizer).
The LS156 basic functions are the following:
It presents the proper DC path for the line current.
It handles the voice signal, performing the 2/4 wires interface and changing the gain on both sending
and receiving amplifiers to compensate for line attenuation by sensing the line length through the line
current.
It acts as linear interface for MF, supplying a stabilized voltage to the digital chip and delivering to
the Iine the MF tones generated by the M761.
ABSOLUTE MAXIMUM RATINGS
VL
IL
IL
Ptot
Top
T stg '
Tj
Line voltage (3ms pulse duration)
Forward Iine current
Reverse line current
Total power dissipation at Tamb = 70 D C
Operating temperature
Storage and junction temperature
22
150
-150
1
-45 to 70
-65 to 150
V
mA
mA
W
DC
DC
ORDERING NUMBER: LS 1568
Dimensions in mm
MECHANICAL DATA
259
6/82
CONNECTION DIAGRAM
(top view)
MIC.INPUT
MlC.INPUT
16
• LINE
15
VDO
MUTING
14
MFINPUT
BIAS ADJ.
13
RECEIVER OUTPUT
SHUNT REG.
BYPASS
12
~
RECEIVER OUTPUT
h
10h
11
O.C.REGUlATOR
LINE CURRENT
SENSING
INPUT.(REC.AMP)
INPUT-(REC.AMP.)
2BAl SWITCH
9
~
-LINE
5·3838 11
BLOCK DIAGRAM
r-----------------------,--{:=}-~~------------------------~----------Q~
tvl
J.
R2
bia!oo
resistor
r--------------{141r---------~~----~
t
MF
signal
5-4313
260
TEST CIRCUITS
G
-+______-,
~~+OA~-.__________________~_6,8~nr-~~33~0~n~~+-__
52
10
LS156
nF
13
KD.
-8
F
5-1, 3 68(1
Fig.2
Fig. 1
~
~
G
A
G
r---+_---¢A
TEST
CIRCUIT
TEST
CIRCUIT
R=6.8Kfi
R =6.SKfi
L---+.------68
L---+-----
,--
SVA
L-
10 5
100
100
Fig. 6 - Supply voltage rejection vs. frequency
80
~
10
Gv
(dB )
Gv
20
o
~.
so
-so
so
~
95
'"
40
40
90
-50
1et f (Hz)
Fig. 7 - Large signal frequency response
50
100
Tamb( C)
20
10
Fig. 8 - Output voltage
swing vs. load resistance
10'
10'
10'
10 5
f(Hz)
Fig. 9 - Total input noise
vs. freq uency
G-!713
24
r--t-t-t-rttffl 'Is =.15V
)
_Lll
~-+-++-H-.f+H Gy =20dS
20 ~-+-++-i1ft+H f = 1kHz
~-+-t+1f-t++H d = 3'"
Rg.IOKIl
.
10 ~
12 ~-+-1f+-H-f+H--+-+-H-f++H
4~~~**--~+#~~~~~
-+-M+**--~-+-H#ffi-~++~
/
OL-+-~~L-~~~~-LLll~
10 2
10 3
10'
f(Hz)
10'
r
"s_.,5V
IKIl
5OJl[
;i
.
10'
279
I
. ..
10'
. ..
.II ..
f(Hz)
APPLICATION INFORMATION
Fig. 10 -Amplitude response
Active low-pass filter:
0_36oWi
'.
BUTTERWORTH
(dB )
The Butterworth is a "maximally flat" amplitude response filter.
Butterworth filters are used for filtering signals in data acquisition
systems to prevent aliasing errors in sampled-data applications and
for general purpose low-pass filtering.
The cutoff frequency, fe, is the frequency at which the amplitude
response is down 3 dB. The attenuation rate beyond the cutoff frequency is -n6 dB per octave of frequency where n is the order(number
of poles) of the filter.
Other characteristics:
• Flattest possible amplitude response.
• Excellent gain accuracy at low frequency end of passband
~
\\
-20
~
\'
-40
ber of poles) of the filter. The cutoff frequency, fe, is defined as the
frequency at which the phase shift is one half of this value. For accurate delay, the cutoff frequency shOUld be twice the maximum signal
frequency. The following table can be used to obtain the -3 dB frequency of the filter.
2 pole
4 pole
6 pole
8 pole
-so
0.77 fc
0.67 fc
0.57 fc
0.50 fc
I
III
as
fife
Fig. 11 -Amplitude response
G_361o~
'.
(dB
)
;:.....
~'\.
-20
I"-
1\\
\
--
n =2
ir·
n.B \ l\n.S
I\(
-4 0
-60
-3 dB frequency
~
n.B ,\ t'.4
\ n.s1-j
0.1
BESSEL
The Bessel is a type of "linear phase" filter. Because of their linear
phase characteristics, these filters approximate a constant time delay
over a limited frequency range. Bessel filters pass transient waveforms
with a minimum of distortion. They are also used to provide time
delays for low pass filtering of modulated waveforms and as a "running
average" type filter.
The maximum phase shift is -~1T radians where n is the order (num-
'"
4
as
0.1
Other characteristics:
• Selectivity not as great as Chebyschev or Butterworth.
• Very little overshoot response to step inputs
• Fast rise time.
Fig. 12 -Amplitude response
(± 1 dB ripple)
CHEBYSCHEV
A.
Chebyschev filters have greater selectivity than either Bessel or Butterworth at the expense of ripple in the passband.
Chebyschev filters are normally designed with peak-to-peak ripple
values from ± 0.2 dB to ± 2 dB.
Increased ripple in the passband allows increased attenuation above
the cutoff frequency.
The cutoff frequency is defined as the frequency at which the amplitude response passes through the specified maximum ripple band and
enters the stop band.
Other characteristics:
• Greater selectivity
• Very nonlinear phase response
• High overshoot response to step inputs
280
I
I
(dB )
G-3I41
I
I
~
i
t., "1\\ ..... n.2
I
-20
!
\\
I
-40
\\
i
-60
.4
iI
I
0.1
\
.BY n.s\l
f--I
o.s
fife
APPLICATION INFORMATION (continued)
The table below shows the typical overshoot and settling, time response of the low pass filters to a step
input.
NUMBER
OF POLES
PEAK
OVERSHOOT
SETTLING TIME (% of final value)
±1%
% Overshoot
BUTTERWORTH
BESSEL
CHEBYSCHEV
(RIPPLE ± 0.25 dB)
CHEBYSCHEV
(RIPPLE ± 1 dB)
4
11
2
4
± 0.1%
1.1/fc sec.
1.7/fc
1.7lfc sec.
2.8/fc
3.9/fc
5.1 fc
6
14
2.4/fc
8
16
3.1/fc
2
4
0.4
0.8/fc
1.0/fc
± 0.01%
1.9/fc sec.
3.8lf c
5.0lf c
7.1/fc
1.7/f c
2.4/fc
2.7/f c
6
0.8
0.6
8
0.3
1.6/fc
1 .4/f c
1.81f c
2.1/fc
2.3/fc
2
4
11
18
21
1.1/fc
3.0/fc
5.9/fc
8.4/fc
1.6/fc
5.4/fc
10.4/fc
16.4/fc
-
1.6/fc
4.8/fc
2.7/f c
8.4/fc
-
8.2/fc
11.6/fc
16.3lf c
24.8/fc
6
8
23
2
4
6
21
28
32
34
8
1.3/fc
Design of 2 nd order active low pass filter
(Sallen and Key configuration unity gain op-amp)
Fig. 13 - Filter configuration
where:
with fc= cutoff frequency
We
271' fe
~
damping factor.
281
3.2/f c
-
-
APPLICATION . INFORMATION (continued)
Tab_I
Three parameters are needed to characterise the
frequency and phase response of a 2 nd order active filter: the gain (G y l. the damping factor (~)
or the O-factor (0= (2 ~)-l).and the cutoff frequency (fel.
The higher order responses are obtained with a
series of 2 nd order sections. A simple RC section
is i"trcduced when an odd filter is required.
The choice of .~. (or O-factor) determines the
filter response (see table).
Filter response
~
0
Bessel
:Yr
2
V3
Butterworth
E2
V2
Chebyschev
<-:5..
2
1
1
>_1_
V2
Cutoff frequency
fc
Frequency at which
phase shift is _900
Frequency at which
Gv = -3 dB
Frequency at which
the amplitude
response passes
through specified
max. ripple band
and enters the stop
band
Fig. 14 - Filter response vs. damping factor
(dB)r--r-rTTTTl"lr-r-ro-rrm
-4 f-- 1j=~~07FR''I""'~,--
75
•
n
536n
~
~;"F
R2
6.8Kfi
2
4
13
-11
R7
1
14
100n
,B.L,
10011
12
-.r-
LINE
LS285
16'
R4
2.05K n
:g2nF
R 6'
9
5
3
6
10
C7
~F
Q"
Fi
2501l
,.!li.
C6
250Il.
>-R3
16.2Kll
~
'-----
289
f"'"
R50
9.09 K
n
j
5-5007
C4
:~2nF
F
APPLICATION INFORMATION
The following table shows the recommended values for the typical application circuit of fig. 6. Different
values can be used and notes are added in order to help designer.
Component
Recommended
Value
R1
75 n
R2
536n
R3
Purpose
Note
Bridge resistors
The ratio R2/R1 fixes the amount of the
signal delivered to the line. (see fig. 7)
16.2 Kn
Bias resistor
Changing R3 value it is possible to shift the
gain characteristics.
The value can be chosen from 15 Kn to 20
Kn. The recommended value assures the
maximum swing (see fig. 9).
R4
2.05 Kn
Balance network
R5
9.09 Kn
In order to optimize the sidetone it is possible
to change R4 and R5 values. I n any case;
R2
ZB
- - = R1 where ZB= R4 + R5/1C4.
ZL
R6 and R6'
250n
Microphone impedance
matching
R6 and R6' must be equal; 250n is a typical
value for dynamic capsules.
Furthermore, they determ ine a sending gain
variation according to;
AG s = 20 log
Rx
850n
where Rx = R6 + R6' + R mike . The trend of
AG s as a fu nction of Rx value is shown in fig. 8.
R7 and R7'
lOOn
Receiver impedance
matching
R7 and R7' must be equal; lOOn is a typical
value for dynamic capsules
C1
1Ol'F
AC loop opening
Ensures a high regulator impedance for AC
signals ('" 20 Knl.
This capacitor should not be higher than 10
I'F in order to have a short response time of
the system.
C2
22 nF
Matching to a capacitive
line
C2 changes with the characteristics of the
transmission line.
C3
82 nF
High frequency roll-off
C3 determines the high frequency response
of the circuit.
It also acts as RF bypass.
C4
22 nF
Balance network
See note for R4 and R5.
C5
1 I'F
C6 and C7
1000 pF
DC decoupl ing for
receiving input
RF bypass
290
APPLICATION INFORMATION (continued)
.,
•
.,
Fig. 7
Receiving gain
variation vs. R 1 value (with
fixed Rl/R2 ratio)
G-4626
OG
OG R
OG 5
~ \
(dB
(dO )
l"lKHz
r-
IL~10to80
lL~'O 10 80mA
·'1
Rl IR 2: 7 5
V
• 2
-
OdBfa)7Sn
-
7
....v
V
-2
,.,lKHz
(dB )
1.1KHz
mA
.,
Fig. 9 - Sending and receiving gain variation vs. line
current
,.,
Fig. 8 - Sending gain variation vs. Rx value (see note
for R6 and R6')
G-4 21
'8
'6
.\r\
\
R .20K1'l.
./"
-2
\
.2
"-
-2
-, /
OdS (ci)850n
"r--.....
-4
-6
.......
-
~~:K~~ -
\
1\
f---
-6
\
\ I\.
"'"
-........
-8
'0
60
80
200
600
20
291
40
f---
LINEAR INTEGRATED CIRCUIT
PROGRAMMABLE TELEPHONE SPEECH CIRCUIT
The LS288 is a monolithic integrated circuit in 16 lead dual in-line plastic
signed as a rep lacement for the hybrid circuit in telephone sets it performs all the func
carried out by
this circuit.
With the LS288 it is possible to select the operating mode (fixed or
both piezoceramic and dynamic transducers and therefore its
sending and receiving paths,
can be preset by means of two external resistors. This fe
obtained in AGC operating
mode, when the device automatically adjusts the Rx/Tx gai
nsate for the line attenuation by
sensing the line current.
The LS288 can supply the decoupling FET when
g with an electret microphone. Output impe·
dance can be matched to the line independent
impedance.
VL
IL
IL
22
150
-150
1
-45 to 70
-65 to 150
Ptot
Top
Tstg' Tj
V·
rnA
rnA
W
°C
°C
ORDERING NUMBER: LS288 B
Dimensions in mm
MECHANICAL DATA
6/82
292
CONNECTION DIAGRAM
(top view)
AGC CUTOFF
MICROPHONE INPUT]
16
A C LOOP OPENING
15
AC AND DC
IMPED.MATCHING
2
14
SENDING AMP OUT
SENDING GAIN
PROGRAM.
13
LINE ""
RECEIVING
PROGRAM.
12
B IA S RESISTOR
11
ELECTRET MIKE
SUPPLY
GAIN
BAL. NETWORK
REC. INPUT
LINE - (GND)
$- 4468"
BLOCK DIAGRAM
r----------{==~--------~--==J_~~--~------------------------,~
R2
R1
C2
14
I
- - -(~'o--"
I
BIAS
RESISTOR
5-4934
293
TEST CIRCUITS
Fig. 1 - Test Circuit
IL• A
39.2
n
392
n
cr~--~--------------~-i~R:1:1}W~~~~:R:2J-~------------,~---,
12
7 14
13
LS288
5
ISM
+--
13
Kn
J'R6
3~~J
1W
-Q-1"6
2
3
9
10
[
1'" ""
R5
6Kn
iii~C1
B
5-4935/1
Fig.2
Fig. 3
,----~-_oA
.--_-.0 A
Fig.4
TEST
CIRCUIT
TEST
CIRCUIT
TEST
CIRCUIT
'---+---oB
'--~>-----¢B
C
D
E
F
D
5-49/,0
5-4938
CMRR
V RO
Vso
V MI
V MI
Side tone = - - ; Gs = -----
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
294
80
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Tamb = -25 to +50°C, f
to 3400 Hz, IL = 12 to 120 mA, unless otherwise specified)
Parameter
=
200
Test conditions
AGe off (pin 1 floating)
VL
Line voltage
T amb = 25°C
IL= 15 mA
IL= 22 mA
IL= 60mA
IL= 120 mA
CMRR
Common mode rejection
f = 1 KHz
Gs
Sending gain (*)
IL= 15 mA
T amb = 25°C
f = 1 KHz
Rs=17Kn
V M1 = 3 mV
R7 = 8 Kn
R7 = 29 Kn
R7 =47 Kn
V M1 = 3 mV
f ref = 1 KHz
I Lref= 60 mA
.6G S
Sending gain flatness (vs. freq.)
.6G s
Sending gain flatness (vs. current)
dS
Sending distortion
IL= 15 mA
T amb = 25°C
f = 1 KHz
R7 = 29 Kn
V R1 = 0.3V
Rs = 8 Kn
Rs = 17 Kn
Rs = 23 Kn
V R1 = 0.3V
f ref = 1 KHz
I Lref= 60 mA
ZML
V SM
40
26
41
51
42
dB
3
± 0.5
dB
± 0.5
dB
V M1 = 0
Receiving gain (*)
R9-10
2
2
GR
Receiving distortion
dB
5
V M1 = 3 mV
dR
1
VSO= 775 mV
G s = 42 dB
Receiving gain flatness (vs. freq.)
V
VSO= 450 mV
Sending noise
. Receiving gain flatness (vs. current)
4.9
5.4
10
14
f = 1 KHz
G s = 42 dB
Microphone input impedance
pin 2-3
.6G R
4.5
50
R2_3
.6G R
4.1
f = 1 KHz
G R= -3 dB
%
3
dBmp
3
Kn
3
6
dB
4
± 0.5
dB
4
± 0.5
dB
-72
11
15
4
-6
5
14
3
V R1 = 570 mV
2
V R1 = 1.2V
5
%
4
250
ltV
4
Receiving noise
GR=OdB
VRI= 0
Receiver output impedance
(pin 9 and 10)
V RO =50mV
20
n
4
Sidetone
f = 1 KHz
G s = 42 dB
GR= -3 dB
15
dB
3
n
4
Vp
4
V
1
Line matching impedance
V R1 = 0.3V
Max receiving output (click
suppressor)
V R1 = 2V
GR=OdB
Microphone supply voltage
(pin 11)
ISM= 0.8 mA
f = 1 KHz
650
750
850
2.3
1.9
2.1
(*) The sending and receiving gains are not completely independent but the variation in sending gain over the whole
range of receiving gain (and vice-versa) is less than 0.5 dB.
295
ELECTRICAL CHARACTERISTICS (continued)
Test condition
Parameter
AGe on (pin 1 grounded)
fiGS and
flG R
T amb =25°C
Sending and receiving gain
variation (**)
f = 1 KHz
IL = 25 mA
IL = 50mA
IL = 110mA
-1
+1
-6
-7
-4
dB
3-4
-5
(00) Referred to any value fixed by means of R7 and R 8 .
CIRCUIT DESCRIPTION
1. DC Characteristic
In accordance with CCITT recommendations, any device connected to a telephone line must exhibit a
proper DC characteristic V L, IL'
The DC characteristics ofthe LS288 is determined by the shunt regulator (block 2) together with two
series resistors Rl and R3 (see the block diagram). The equivalent circuit is shown in fig. 5.
Fig. 5 - Equivalent DC load to the line
14
R1
13
R3
15
5-4936
A fixed amount, 10 , of the total available current, IL' is drained to allow the circuit to operate correctly.
The value of 10 can be programmed externally by changing the value of the bias resistor connected to
pin 12.
296
CIRCUIT DESCRIPTION (continued)
The recommended minimum value of 10 is 7.5 mA with R pin 12 = 13 Kn.
The voltage Va "" 3.8V of the shunt regulator is independent of the line current.
The shunt regulator (block 2) is controlled by a temperature compensated voltage reference (block 1).
Fig.6 shows a more detailed circuit configuration of the shunt regulator.
Fig.6 - Circuit configuration of the shunt regulator
R2
RI
14
15
16
L-R3~ ~~~_I
__
The difference IL - 10 flows through the shunt regulator since Ib is negligible.
I. is an internal constant current generator; hence Va = VB + I•. R. = 3.8V.
The V L, IL characteristic of the device is therefore similar to a pure resistance in series with a battery.
It is important to note that the DC voltage at pin 16 is proportional to the line current V 16 = V 15 + VB =
(IL - 10 ) R3 + VB·
2. Two to four wires conversion
The LS288 performs the two wire (line) to four wire (microphone, earphone) conversion by means of a
Wheatstone bridge configuration thus obtaining the proper decoupling between sending and receiving
signals (see fig. 7).
For a perfect balancing of the bridge
:~
=
~~
The AC signal from the microphone is sent to one diagonal of the bridge (pin 8 and 14). A small percentage of the signal power is lost on ZB (since ZB ~ ZL); the main part is sent to the line via R 1 .
In receiving mode, the AC signal coming from the line is sensed across the second diagonal of the bridge
(pin 6 and 7). After amplification it is applied to the receiving capsule.
The impedance ZM is simulated by the shunt regulator which also acts as a transconductance amplifier
for the transmission signal.
The impedance ZM is defined as
1;V(14-8)
...:;::,~-~.!!L_
1;1 (14-8)
297
CIRCUIT DESCRIPTION (continued)
Fig. 7 - Two to four wires conversion
14
,
[J
ZL
LINE
~ -----------J___ _
8
5-4937
From fig. 6, considering C l as a short circuit to the AC signal, any variation in /:"V 14 generates a variation as follows:
The corresponding current change is:
/:,.1
therefore
/:"V
Ra
R3 (1 + - - I
/:"1
Rb
The total impedance across the line connections (pin 13 and 8) is given by
ZM
= - -14- =
R
ZML ~ ZM = R3 (1 + _a_)
Rb
The amplitude of the signal received across pins 6 and 7 can be changed using different values of R 1.
(Of course the relationship
~~
=
:~
must always be valid).
298
The received signal is related to the value of R 1 according to the approximated relationship:
Rl
Rl + ZM
Note that if the value of R 1 is changed the transmission signal current is not changed, since the microphone amplifier is a transconductance amplifier.
=
VR
V R1 2
3. Input and output amplifiers
The microphone amplifier (4) has a differential input stage with high impedance (min 11 Kn) so allowing a good matching to the microphone by means of an external resistor without affecting the sending
gain.
The receiving output stage (8) is intended to drive both piezoceramic and dynamic capsules. It has low
output impedance, a maximum voltage swing greater than 2 Vp and a peak current of 2 mAo
With very low impedance transducers, DC decoupling by an external. capacitor must be provided to
prevent a large DC current flow across the transducer itself due to the receiving output stage offset.
4. Gain Control
It is possible to set the LS288 gain characteristics by means of one pin (pin 1).
When the pin 1 is floating, the gains of the sending and receiving ampl ifiers do not depend on the line
current (AGC off). When the pin 1 is grounded the LS288 automatically changes the gain to compensate
for line attenuation (AGC on).
4.1. AGe OFF
In this conditions, as already mentioned, both the sending and the receiving gain are fixed. Their values
are determined, independently for the two paths, by the two external resistors R7 (for T x, between pin
4 and ground) and Rs (for Rx , between pin 5 and ground). R7 values ranging from 8 Kn up to 50 Kn
giving sending gains from 26 dB to 51 dB. Rs values range from 8 Kn to 23 Kn giving receiving gains
from -6 dB to + 14 dB (see fig. 9 and 10).
This allows the LS288 to be used with a variety of different transducers.
Fig. 9 - Sending gain vs.
R7 value (AGC off)
Fig. 10 - Receiving gain vs.
Rs value (AGC off)
G-HI5
Os
"8',I
56
AGe off
/'
'/
AGe 011
/
I
V
I
./
,/
:
./
./
./
32
28
V
I
./
I
~V
-8
i
I
-16
:
i
20
20
JO
20
299
Ra(Kfi)
DESCRIPTION CIRCUIT (continued)
4.2. AGCON
Starting from any couple of gain values, fixed by the appropriate values of R7 and Rs , the LS288 can
automatically change the sending and receiving gains depending on the line current.
The line current is sensed across R3 (see fig. 7) and transferred to pin 16 by the regulator.
V16 =
Va + V 15 =
Va + (I L - 10
) •
R3
Following comparison with an internal reference V REFG (see the block diagram) the voltage at pin 16
is used to modify the gain of the amplifiers (5) and (7) on both the sending and receiving paths.
The starting point of the automatic level control is obtained at IL = 25 rnA when the drain current
10 = 7.5 rnA.
The external resistors R7 and Rs fix the maximum value for the gains.
Minimum gain is reached for a line current of about 110 rnA when the same drain current 10 of 7.5 rnA
is used.
When 10 is increased by means of the external resistor connected to pin 12 the two above mentioned
line current values for the starting point and for the minimum gain increase accordingly.
5. DC Shunt Regulator
The LS288 has built into the chip a DC shunt regulator intended to supply the coupling FET when an
electret microphone is used. It delivers 1 mAp current with a voltage of 2 Volts (typ) regardless of the
line current.
Fig. 11 - Typical application circuit (piezoceramic transducers)
•
~
rv
C5
I-'+t.--.--...--.----+--C::J"'----~-_C:;::J_-___;
C2 1,uF
13
10 I---C:::J--+---'
LS288
LINE
18V
Rl0
15
12
8
16
R3
33.2Jl
lW
b-----'-i
R5
10nF
101111 C3
s- '942fl
300
CIRCUIT DESCRIPTION (continued)
Fig. 12 - Application circuit with electret microphone
+
C2 l,..uF
13
LS288
LINE
18v
15
12
8
16
R3
33.Z!l
lW
13K
s- 494311
The following table can be helpful to the designer when choosing different values for the external
components; it refers to the typical application circuit of fig. 11.
Component
Value
Note
Function
RI
39.2 n
Bridge
'. R2
392n
Resistors
Line current sensing
R I controls the receiving gain.
The ratio R2/RI fixes the amount of
signal delivered to the line. RI helps in
fixing the DC characteristic (see R3
note)
The relationships involving R3 are:
- ZML= (25 R3I!ZB) + RI
ZLI! ZML
R3
-VL=(lL-lol. (R3+ R ,)+V o
[Vo = 3.8V]
- Gs = K·
R3
33.2 n
Fixing DC
characteristic
Values of ZML ranging from 650 up to
850n are easily obtainable.
R4
Rs
2.2 Kn
10Kn
Balance
Network
I n order to optimize the sidetone it is
possible to change R4 and Rs values; in
any case the following relationship
applies:
ZB
ZC=
301
R2
R1
where
ZB= R4+RSI!XC3
APPLICATION INFORMATION
Component
R6
Value
13 Kn
(continued)
Function
Bias Resistor
Note
The suggested value assures the minimum operating current.
It is possible to increase the supply
current by decreasing R6 (they are
inversely proportional) , in order to
achieve the shifting of the AGC starting
point
R7
8 to 50 Kn
Sending gain
programming Resistor
Rs
8 to 23 Kn
Receiving gain
programming Resistor
1.8 Kn
Receiver impedance
matching
R9 and R9' must be equal; the suggested
value is good for matching to piezoceramic capsule; there is no problem in increasing and decreasing (down to On)
th is value, but when low resistance levels
are used DC decoupling must be inserted
to stop the current due to the receiver
output offset voltage (max 400 mY).
RIO
4Kn
Microphone
impedance matching
The suggested value is typical for a piezoceramic microphone, but it is possible
to choose RIO from a wide range of
values: R Mike ~ RIO//Rpin 2-3'
CI
1OI'F
Regulator AC
bypass
A value greater than 10 I'F gives a
system start time too high for low line
current. A lower value gives an alteration
of the AC line impedance at low
frequency.
C2
1 I'F
R9, R9'
DC decoupl ing for
receiving input
C3
10 nF
Balance network
See note for R4 and R s.
C4
47 nF
Matching to a
capacitive line
C4 must be chosen according to the
characteristics of the transmission line.
Cs
82 nF
Receiving gain
flattness
Cs depends on balancing and line impedance versus frequency.
C6 , C 7
1000 pF
RF bypass
302
LINEAR INTEGRATED CIRCUIT
MULTIFREQUENCY TO TELEPHONE LINE INTERFACE CIRCUIT
The LS342 is a monolithic integrated circuit in dual in-line minidip plastic package. It interfaces the
multifrequency tone diallers M751 and M761/761A to the line in telephone sets, performing the follow·
ing functions:
Adjustment of the DC current/voltage characteristic and AC input line impedance by means of an
external resistor (Rd.
Sending to the line of the multifrequency signal.
Adjustment of the signal level by means of an external resistor (R T ).
Stabilized supply voltage to the tone dialler.
ABSOLUTE MAXIMUM RATINGS
VL
IL
IL
Ptot
Top
T stg , Tj
Maximum line voltage (pulse duration';;; 10 ms)
Maximum forward current
Maximum reverse current
Total power dissipation at T amb = 70°C
Operating temperature
Storage and junction temperature
22
'155
-150
800
-40 to 70
-55 to 150
V
mA
mA
mW
°C
°C
ORDERING NUMBER: LS342D
Dimensions in mm
MECHANICAL DATA
~~;
.5
....
.
.
7
303
6/82
CONNECTION DIAGRAM
(top view)
MULTIFREQUENCY INPUT
1
REGULATOR AC BYPASS
2
3
8
~
SIGNAL LEVEL
ADJUSTMENT
7
~
BIAS
6
~
+ VLAND MF OUTPUT
5~ ACIDC CHARACT.ADJUSt
4
5- 40731 2
BLOCK DIAGRAM
DESCRIPTION
The L5342 interface the M751 and M761/761A tone diallers with the telephone line. Power is only
applied to the system when the handset is lifted and a key pressed. At this time 51 is also switched (see
fig. 2) disconnecting the speech circuit from the line and connecting the dialling circuit.
In the dialling condition the L5342 performs 3 functions:
1) D.C. and A.C. line termination
2) Tone dialler power supply
3) Amplification and transmission of tone pairs.
In the initial stage of switch-on the supply voltage V DD is regulated at ~ 4 volt. This overdrives the
M751/761/761A internal oscillator causing a rapid start-up and therefore rapid generation of output
tones.
When the system reaches its normal operating point the supply voltage VDD is stabilized at 2.5V ± 4%.
THERMAL DATA
Rthi-amb
max
Thermal resistance junction-ambient
304
100 °C/W
ELECTR.ICAL CHARACTERISTICS
(lL=10tol00
rnA; Tamb = -25
to +60°C; f = 1
KHz;S in
(b), unless otherwise specified).
Parameter
VL
Line voltage
Gs
Sending gain
fiGs
Sending gain spread over
temperature
THD*
Distortion
Test conditions
Min.
Typ.
Max.
Unit
4.2
4.6
6.3
9.8
4.5
5
6.8
11.5
V
14
dB
± 0.2
dB
I L = lOrnA
IL= 17mA
IL= 60mA
IL= 150mA
Ej = 0
T amb = 25°C Ej = 50 mV
f = 500 Hz to 2 KHz
12.4
S in (a)
Ej = 120 mV **
2
S in (c)
Ej= 95 mV **
2
%
ZREF= 6000
f ;"" 300 Hz to 3.4 KHz
14
AR
Return loss
ZOUT
Output impedance (pins 6, 4)
CE=2.2/L F
Voo
Supply voltage for digital device
T amb = 25°C
2.4
Voo= 2.4V
1.8
100
Supply current for digital device
t s***
Start-up time
ZIN
I nput impedance (pin 1)
dB
750
R E= 390
2.5
0
2.6
V
5
msec
mA
4
MO
* The distortion of the device is not affected by a signal coming from the line with the following levels: -13 dBm
if IL= 10 mA, -8 dBm if IL= 20 mAo
The different AC and DC levels are intended to simulate the limit working operation of the digital devices M751,
M761, M761A.
The time necessary because the AC signal is varying within ± 1 dB of its steady-state value.
Fig. 1 - Test circuit
LS342
6°~lOIlF
.nr
5- 5005/1
305
IVo
APPLICATION INFORMATION
The table shows the recommended values for the circuit of fig. 2.
Component
Recomm.
value
RE
390.
Note
Purpose
DC characteristic The relationships involving RE are:
• VL=(lL-IO)RE+Vo
where 10 '" 6 mA and Vo '" 4V
• Zo = 22 RE (f = 1 KHz)
The following relationship must be always verified
AC impedance
adjustment
Vp' ZL
RE ;;.
(lL-l o )ZL-22Vp
where Vp is the maximum peak value of the MF signal in the line and
ZL is the line impedance.
5.6 Kn
Rp
R~
Bias resistor
(
71.50.
RT
can be reduced in order to increase the output current from pin 3
DDI. In this case, the total current consumption is increased.
The MF gain is:
Signal level
adjustment
G MF = 0.97
ZL
II
Zo
RT
The recommended value for RT is good to set the Europe I standard
(-9 dBm, -11 dBml. If the Europe II or the American Standard is
required, RT must be decreased. I n the mean time, the minimum
operation current will increase because the pin 8 voltage is fixed by an
internal reference (190 mV typ.l.
CE
2.2/.1F
Cf
0.33/.1F
CL
30 nF
Regu lator AC
bypass
A value greater than 2.2 /.IF gives a system start time too high when line
current is between 10 mA and 17 mAo A value less than 2.2 /.IF gives an
alteration of the AC line impedance because its reactance is not negligible at low frequencies.
DC filtering
The Cf range is from 0.33 /.IF to 0.47 /.IF. The lowest values is ripple
limited, the higher values is starting up time limited.
Match ing to a
capacitive line
This is needed with a capacitive line because the output impedance of
the LS342 is essentially resistive. The range of C L is between 30 and 60nF.
Fig. 2 - Application circuit with M751/M761A.
"
1209
C2
1336
OJ
1477
C4
1633
'DO
H,
'11 697 Hz
13
1'12770 Hz
12
1'13852 Hz
M751
tl
--+4-
10
ll~
~a
~
M761 A
R4 941 Hz;
HOOK
TO THE SPEECH
"
,
3
R,
--',.-+......_ _+-_
SINGLE PUSH BUTTON
306
SINGLE
PUSH BUTTON
LINE
LINEAR INTEGRATEO CIRCUIT
TELEPHONE SPEECH CIRCUIT WITH MULTIFREQUENCY TONE GENERATOR
INTERFACE
The LS356 is a monolithic integrated circuit in 16-lead dual in-line PI,'\ ;'j~,\{:::
~'1N~S
VL
Lin
IL
IL
Fo
Rev
Total
Opera g temperatu re
Storage and junction temperature
Ptot
Top
T stg , T j
22
150
-150
1
-45 to 70
-65 to 150
V
mA
mA
W
°C
°C
ORDERING NUMBER: LS356B
MECHANICAL DATA
Dimensions in mm
307
6/82
CONNECTION DIAGRAM
(top view)
'-'
16
MlC. INPUT
~
MlC.INPUT
+LINE
15
VDD
MUTING
14
MF INPUT
BIAS ADJ.
13
RECEIVER OUTPUT
BYPASS
12
RECEIVE.R OUTPUT
D.C.REGULATOR
11
INPUT.(RECAMP)
LINE CURRENT
SENSING
10
INPUT -(REC.AMP)
SHUNT REG.
GAIN CONTROL
-LINE
5-4919
BLOCK DIAGRAM
.-----------------------~--{:~--~--------------------------~----------~~
tVL
.1.
t
MF .
signal
R3
S'-4930/1
308
TEST CIRCUITS
-
G
Rl
.A
IL
39.2
n
392.11
52
~
33
nF
:!2V
10
Vz=18V
VL
LS356
13
K.Q
33
n
VG
R3
R
_B
5-4920/2
Fig.2
Fig. 1
'L=IZto~
'L=12to~
G
,----+---QA
G
A
TEST
CIRCUIT
R =6.8Kfl.
TEST
CIRCUIT
R=6.8Kfl.
l.....-+-~B
B
C
0
E
F
C
0
E
5-4921
CMRR
Side tone
Fig.3
= V RO
~
Fig.4
G
A
r--~--QA
TEST
CIRCUIT
R =S.8K fl.
lO,uF
TES T
CIRCUIT
R=lKfl.
~-""--QB
B
C
0
E
C
F
309
0
E
F
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS
80 mA, S1 and S2 in (a), T amb
(Refer to the test circuits, VG =
80
°C/W
1 to 2V, IL
12 to
= -25 to +50°C, f = 200 to 3400 Hz, unless otherwise specified)
Parameter
Test conditions
SPEECH OPERATION
VL
Line voltage
CMRR
Common mode rejection
f = 1 KHz
50
Gs
Sending gain
T amb = 25°C f= 1KHz VG= 2V
V M1 = 3 mV
VG= 1V
44
Sending gain flatness
(vs. frequency)
V M1 = 3 mV
Tamb= 25°C
IL= 12 mA
IL= 20mA
IL= 80 rnA
4.7
5.5
12.2
3.9
-
dB
1
46
50
dB
2
± 1
dB
2
± 0.5
dB
2
%
2
48
f ref = 1 KHz
* Sending gain flatness
V
(vs. current)
GR
Sending distortion
f = 1 KHz
V so - lV
Vso= 1.3V
Sending noise
V M1 = OV
VG=lV
Microphone input impedance
(pin 1-16)
V M1 = 3 mV
Sending gain in MF operation
V M1 = 3 mV
S2 in (b)
Receiving gain
V R1 = 0.3V
f = 1 KHz
T amb = 25°C
VG= 2V
VG=lV
Receiving gain flatness
(vs. frequency)
V R1 = 0.3V
f ref = 1 KHz
2
10
-70
dBmp
2
40
Kn
-
-30
dB
2
-5
1
dB
3
± 1
dB
3
± 0.5
dB
3
%
3
-3
-1
-4
0
* Receiving gain flatness
(vs. current)
Receiving distortion
f - 1 KHz
Receiving noise
V R1 = OV
Receiver output impedance
(pin 12-13)
V Ro =50mV
Sidetone
f = 1 KHz
Sl in (bi
T amb = 25°C
ZML
Line match ing impedance
V R1 = 0.3V
f = 1 KHz
18
Input current for gain control
(pin 8)
* Fixed gain mode.
2
V RO - 400mV
VRo= 480 mV
10
I'V
3
100
n
-
36
dB
2
100
310
500
600
700
n
3
-10
I'A
-
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
MUL TlFREQUENCY SYNTHESIZER INTERFACE
S2 in (b)
2.4
S2 in (b)
0.5
2
MF amplifier gain
fMF in= 1 KHz
V MF in= 80 mV
15
DC input voltage level
(pin 14)
V MF In= 80 mV
RI
Input impedance (pin 14)
VMF 1n= 80 mV
d
Distortion
V MF in= 110 mV
Voo
M F supply voltage (Standby
and operation)
100
M F supply current
VI
Standby
Operation
M F operation
Muting operating current (pin 3)
S2 in (b)
311
V
-
mA
-
dB
4
V
-
K!l
-
2
%
4
5
ms
-
1
V
-
60
Speech operation
Muting standby current (pin 3)
17
.0.3
Voo
Starting delay time
Muting threshold voltage
(pin 3)
2.5
V
-
-10
IJ.A
-
+10
IJ.A
-
1.6
CIRCUIT DESCRIPTION
1. DC characteristic
The fig. 5 shows the DC equivalent circuit of the LS356.
Fig. 5 - Equivalent DC load to the line
PIN 6
R,
PIN2
lro
VL
PIN9
PIN7
~
LINE
5 .. 4365
A fixed amount 10 of the total available current IL is drained for the proper operation of the circuit.
The value of 10 can be programmed externally by changing the value of the bias resistor connected to
pin 4 (see block diagram).
The minimum value of 10 is 7.5 mAo
The voltage Vo = 3.8V of the shunt regulator is independent of the line current.
The shunt regulator (2) is controlled by a temperature compensated voltage reference (1) (see the block
diagram).
Fig. 6 shows a more detailed circuit configuration of the shunt regulator.
Fig. 6 - Circuit configuration of the shunt regulator
R2
R'
I. . ._
c
L -_ _ _ _ _ _ _ _ _
_'--S-CI.925----·
b
The difference IL -10 flows through the shunt regulator being Ib negligible.
I. is an internal constant current generator; hence V 0 = VB + I•• R. = 3.8V.
The V L. IL characteristic of the device is therefore similar to a pure resistance in series to a battery.
It is important to note that the DC voltage at pin 5 is proportional to the line current (V 5 = V7 + VB =
(I L-10) R3 + VB).
312
I
CIRCUIT DESCRIPTION (continued)
I.:
I',
2. Two to four wires conversion
The LS356 performs the two wires (line) to four wires (microphone, earphone) conversion by means of
a Wheatstone bridge configuration so obtaining the proper decoupling between sending and receiving
signals (see fig. 7).
'
Fig. 7 - Two to four wires conversion
6
11
-----...-
---
:,
r1
l}ZL
,
LINE
.,
9
-----------~---s· 4367(1
R1
R2
ZL.
For a perfect balancing of the bridge - ZB
The AC signal from the microphone is sent to one diagonal of the bridge (pin 6 and 9). A small percentage of the signal power is lost on ZB (being ZB > ZL.); the main part is sent to the line via R1.
In receiving mode, the AC signal coming from the line is sensed across the second diagonal of the bridge
(pin 11 and 10). After amplification it is applied to the receiving capsule.
The impedance ZM is simulated by the shunt regulator that is also intended to work as a transconductance amplifier for the transmission signal.
The impedance ZM is defined as
/:"V 6 - 9
•
/:,.1 6 - 9
From fig. 6 considering C1 as a short circuit for AC signal, any variation /:"V 6 generates a variation:
tN7
=
/:"V A
=
/:"V 6
The corresponding current change is
61
Therefore
313
•
, Rb
Ra + Rb
I~
CIRCUIT DESCRIPTION (continued)
The total impedance across the line connections (pin 11 and 9) is given by
ZML = R1 + ZM II (R2 + Zs)
By choosing ZM
> R1 and ZB > ZM
The received signal amplitude across pin 11 and 10 can be changed using different values of R1 (of
course the relationship ZL/Z B = R1/R2 must be always valid).
The received signal is related to R1 value according to the approximated relationship:
1'l1
Note that by changing the value of R 1, the 'transmission signal current is not changed, being the microphone amplifier a transconductance amplifier_
3.Automatic gain control
The LS356 automatically adjusts the gain of the sending and receiving amplifiers to compensate for line
attenuation.
This function is performed by the circuit of fig_ BFig_ 8
5-4696
The differential stage is progressively unbalanced by changing VG in the range 1 to 2V (V REFG is an
internal reference voltage, temperature compensated).
It changes the current IG' and this current is used as a control quantity for the variable gain stages "(amplifier (4) and (5) in the block diagram). The voltage V G can be taken:
a) from the LS356 itself (both in variable and in fixed mode) and
b) from a resistive divider, directly at the end of the line.
al In the first case, connecting VG (pin
8) to the regulator bypass (pin 5) it is possible to obtain a gain
characteristic depending on the current.
In fact (see fig. 6):
V5 = VB + V7 ~ Vs + (I L - 10 ) R3
The sta,rting point of the automatic level control is obtained at IL = 25 rnA when the drain current
10 = 7.5 rnA.
314
CIRCUIT DESCRIPTION (continued)
Minimum gain is reached for a line current of about 52 mA for the same drain current 10 = 7.5 mAo
When 10 is increased by means of the external resistor connected to pin 4, the two above mentioned
values of the line current for the starting point and for the minimum gain increase accordingly.
It is also possible to change the starting point without changing 10 by connecting pin 8 to the centre
of a resistive divider placed between pin 5 and ground (the total resistance seen by pin 5 must be at
least 100 Kn). In this case, the AGC range increases too; for example using a division 1: 1 (50K/50K)
the AGC starting point shifts to about IL = 40 mA, and the minimum gain is obtained at IL = 95 mAo
In addition to this operation mode, the VG voltage can be maintained constant thus fixing the gain
values (Rx, Tx) independently of the line conditions.
For this purpose the VDD voltage, available for supplying the MF generator, can be used.
b) When gains have to be related to the voltage at the line terminals of the telephone set, it is necessary
to obtain VG from a resistive divider directly connected to the end of the line.
This type of operation meets for istance the requirements of the French standard. (See the application circuit of fig. 12).
4. Transducers interfacing
The microphone amplifier (3) has a differential input stage with high impedance (~ 40 Kn) so allowing
a good matching to the microphone by means of external resistor without affecting the sending gain.
The receiving output stage (6) is particularly intended to drive dynamic capsules. (Low output impedance, 100 n max; high current capability, 3 mAp).
When a piezoceramic capsule is used, it is useful to increase the receiving gain by increasing R 1 value (see
the relationship for V R)'
With very low impedance transducer, DC decoupling by an external capacitor must be provided to prevent a large DC current flow across the transducer itself due to the receiving output stage offset.
5. Multifrequency interfacing
The LS356 acts as a linear interface for the Multifrequency synthesizer M761 according to a logical
signal (mute function) present on pin 3.
When no key of the keyboard is pressed the mute state is low and the LS356 feeds the M761 through
pin 15 with low voltage and low current (standby operation of the M761). The oscillator of the M761
is not operating.
When one key is pressed, the M761 sends a "high state" mute condition to the LS 356. A voltage comparator (8) of LS356 drives internal electronic switches: the voltage and the current delivered by the
voltage supply (9) are increased to allow the operation of the oscillator.
This extra current is diverted by the receiving and sending section of the LS356 and during this operation the receiving output stage is partially inhibited and the input stages of sending and receiving amplifiers are switched OFF.
A controlled amount of the signalling is allowed to reach the earphone to give a feedback to the subscriber; the MF amplifier (10) delivers the dial tones to the sending paths.
The application circuit shown in fig. 9 fulfils the EUROPE II standard (-6, -8 dBm). If the EUROPE I
levels are required (-9, -11 dBm) an external divider must be used (fig. 10).
The'mute function can be used also when a temporary inhibition of the output signal is requested.
315
APPLICATION INFORMATION
Fig.9 - Application circuit with multifrequency (EUROPE II STD)
C3
II
~~
r---
ct
+
Voo
f
18
LINE
""*
, 8V
1
2
3
,
S
6
7
8
9
* ° '"
A
D~-
l'
I~:,
3
MF
INPUT
16
8~
M761
39.2n
Rl
2
~oJ
~
~
9
6
11
~20PF
IS
13
3
10
~~F
clld
I~S
2.2Kll
LS356
"
8
C5
R80200£
,
R3
3311
lW
~ 13~it l
9
5
? FOi
C7"
1
171----
I
lOon
R7'
100n
R7
~~3IJF
:~OPF
n
12
7
2
14:,
:cZinf
R2
82Kfi
1
392
lW
MUTE
IS
I--- "
B I--- 12
C I--- 13
82nFil
16
~f·
11
34.8
Kit
18
*
VDO
15
MUTE
15
4.87K
16
n
*
M761
LS 356
MF IN~UT
14
30 n
* TOLLERANCE
=t2%
316
......
C6
I-OnF
R6
:~C
10Kfi
5'492611
Fig. 10 - Application circuit with multifrequency (EUROPE I)
F
II
~OPF
I
I
:1
1
j
I
APPLICATION INFORMATION (continued)
Fig. 11 - Sending and
receiving gain vs. line cur·
rent (application circuit of
fig. 13)
G-
Fig. 12 - Application circuit without multifrequency
..
C3
~..--
J9.21t 1w
~5'3
(,.
"If,
G,
(dB)
)
392.n
I ~C2 lIT
J:47nF
C'L
2
50
S
"
:\
-2
'3
"
-4
INE
----
-,
"
'0
20
so
~
'6V
.s
,
4
.3
lW
1l:~
~
'---
s
,s
C~~,uF
..
Fig. 13 - Application circuit with gain controlled by line voltage (French standard)
CURRENT
LIMITING
82nF
39.2fi
a
392fi
lW
:::I:47nF
"
12
,5
13
LS 356
18Y
14
8
7
33fi
1W
317
10
07 ..
RsD200n
~
CIRCU--+_OVOUI
with fe = cutoff frequency
= damping factor.
325
-
APPLICATION INFORMATION (continued)
TAB 1
Three parameters are needed to characterize
the frequency and phase response of a 2 nd
order active filter: the gain (G v ), the damping
factor (~) or the O-factor (0= (2 ~)-1 ), and
the cutoff frequency (fel.
The higher order responses are obtained with a
series of 2nd order sections. A simple RC section
is introduced when an odd filter is required.
The choice of '~' (or O-factor) determines the
filter response (see table).
Filter response
Bessel
Butterworth
Chebyschev
~
Q
.J3
1
2
.J3
.)2
1
2
ft
.j2
1
< - >.)2
2
Cutoff frequency
fc
Frequency at wh ich
phase sh itt is _90
0
Frequency at which
Gv = -3 dB
Frequency at which
the amplitude
response passes
through specified
max. ripple band
and enters the stop
band
Fig. 14 - Filter response vs. damping factor
(dB)r--,-,-.-r-rrnr-'---TT--rrrrn
f---++t+J-Yt,Htt'~""5 =0.177
f---++t+mtm'='JI== 0.25
rt-:~~.!~~=OJ5
=0.5
-4 -
Fixed R= Rl = R2 , we have (see fig. 13)
~=U707FR'IiF\'I""+--H:-H+tH
=2
Cl=~
R we
1
-'2f----+++-+-t+ftt--\'l--t+-t+J+jj
-'6 f---+-+++-++m--~\~-'+-+++H-I1
0.2
0.5
.'
C2 =
1
R ~Wc
The diagram of fig. 14 shows the amplitude response for different
values of damping factor ~ in 2 nd order filters.
5 (fifO)
EXAMPLE:
Fig. 15 - 5 th order low pass filter (Butterworth) with unity gain configuration.
Ri
326
APPLICATION INFORMATION (continued)
In the circuit of fig. 15, for fc = 3.4 KHz and
R j = R 1= R 2 = R3= R4= 10 Kn, we obtain:
Cj = 1.354
1
0
Ff
1
0
21T f
Tab. II
Damping factor for low-pass Butterworth filters
6.33 nF
Order
c
1.97 nF
C2 =1753
.
C3 = 0.309
C4 =3.325
0 _
1
R
1
0
0
Ffo
-1- =
21T fc
1
21T f
1
c
1
Off ° 21Tf
c
=
8.20 nF
1.45 nF
Cj
Cl
C2
2
0.707 1.41
3
1.392 0.202 3.54
4
0.92
5
1.354 0.421
1.08
C3
C4
0.38
2.61
C5
Cs
0.966 1.035 0.707 1.414 0.259 3.86
7
1.336 0.488 1.53 0.623 1.604 0.222 4.49
0.98
Ca
1.75 0.309 3.235
6
8
C7
1.02·
0.83
1.20 0.556 1.80 0.195 5.125
= 15.14nF
The attenuation of the filter is 30 dB at 6.8 KHz
and better than 60 dB at 15 KHz.
The same method, referring to Tab. II and fig.
16, is used to design high-pass filter. In this
case the damping factor is found by taking the
reciprocal of the numbers in Tab. II. For fc
= 5KHz and C j = C1 = C 2 = C3 = C4 = 1 nF
we obtain:
1
R1 = 0.421
1
1
°c
21Tfc =
75.6 Kn
18.2 Kn
1
R3 = 0.309
1
1
°c'
21Tfc =
103 Kn
9.6 Kn
Fig. 16 - 5 th order high-pass filter (Butterworth) with unity gain configuration.
R2
Cj
R4
c,
o--i~
I
1st order
327
5-4122
APPLICATION INFORMATION (continued)
Fig. 17 - Multiple feedback 8-pole bandpass filter.
C3
C6
R,
CI
IN
C9
ell
••
C2
RI
.,
O-;'I--=K--IH'"'-P.....
o'l,uF
.1<
O.l,uF
.,.o--~-+-----1
R2
22KO
R3
22KJ'l
1--0
220"1
e13 O.221JF
I
C7
fc = 1.180Hz;A= 1; C2 = C3 = Cs = C6 =Cs =C9 =C IO = C11 = 3.300 pF;
RI = R6
R9 = Rl2 = 160 Kn; Rs = Rs = R11 = Rl4 = 330Kn; R4 = R7 =
=:
Fig. 18 - Frequency response
of band-pass filter
I
(dB)
~,
!
ONE-,
-20
,
, ,
,
,
-<0
TWO""
, ,-
-60
,
\
\
-3
-,
\ ,
-.
\
\
-.
-.
_7
FOUR..
11
-80
-9
AI
0.1
OJ
" .' I
ONE/
,
f{KHz)
,,-.r!
fO"IKHz
_2
I \' ' ,
=
Rll
= 5.3Kn
Fig. 19 - Bandwidth of band·
pass filter
(dB)
1
RIO
TWO/
i
I
fOu
.'11
I
II
328
" ,
'.
1\ ...
\
\
\
II I
7
1\
rr
_150 _120 -90 -60
". ."
""" 1\\"
\
-JO
0 .30 ·60 .90
(Hz)
OUT
LINEAR INTEGRATED CIRCUIT
TELEPHONE SPEECH CIRCUIT WITH MULTI FREQUENCY TONE GENERATOR
INTERFACE
The LS656 is a monolithic integrated circuit in 16-lead plastic package ••torepl~~eih~ hybrid circuit in
telephone set. It works with the same type of transducers for both transm.i~teral"ld receiver (typically
dynamic capsules). Many of its electrical characteristics can be ccii'ltrolled'hy. means of external components to meet different s p e c i f i c a t i o n s . . " ..•.....••......••...•.•..•
In addition to the speech operation, the LS656 acts as an i#t~i'facef~r the MF tone signal (particularly
for M761 CiMOS frequency synthesizer).
The LS656 basic functions are the following:
.
'
.
- It presents the proper DC path for the line curfli1nf, particular care being paid to have low voltage
drop.
. .. '. "... '
.
-
perfOrmi~g~i'f~:~f4,:",I~e~interfaCe
It handles the voice signal,
and changing the gain on both sending
and receiving amplifiers to compensa~~.4pt;·.tjri~·.attenuation by sensing either the line current or the
line Voltage. In addition, the L$~l:i~ calr~I~'';Work in fixed gain mode.
<~,:",'!, ' . ' '\<,:
It acts as linear interface f6B••MF;,•.• SIif't:)iYirig a stabilized voltage to the digital chip and delivering to
the line the MF tones gel'ffl(~~ b\I:.the M761.
i,'"',,
VL
IL
IL
Ptot
Top
Tstg , Tj
'!";;}
., pulse duration)
rent
Reverse I'e current
Total power dissipation at Tamb.= 70DC
Operating temperature
Storage and junction temperature
22
V
150
-150
1
-45 to 70
-65 to 150
mA
mA
W
DC
DC
ORDERING NUMBER: LS656B
Dimensions in mm
MECHANICAL DATA
329
6/82
CONNECTION DIAGRAM
(top view)
......
MIC.INPUT
16
MIC.INPUT
_LINE
15
VOO
MUTING
14
MFINPUT
BIAS ADJ.
13
RECEIVER OUTPUT
SHUNT REG.
BYPASS
12
RECEIV~R
D.C.REGULATOR
11
INPUT_(REC.AMP)
liNE CURRENT
SENSING
10
INPUT ~(REC.AMP.)
GAIN CONTROL
OUTPUT
-LINE
s -1,919
BLOCK DIAGRAM
,-----------------------~--c=~--~--------------------------.---------~~
tvL
.1.
I
~
,I
---
bia5
resistor
)----------{14:.--------{
t
MF .
signal
R3
YuTE
5-493011
330
TEST CIRCUITS
G
_I L
A
~r--r
________________r-t:j-~~33=0=11~~~__~_____
3011
33
nF
B
Fig. 1
Fig.2
IL·'i'o~
IL=12'o~~
G
G
A
A
TE5T
CIRCUIT
R=6.8Ka.
TEST
CIRCUIT
R =6.8Ka.
'----+------flB
B
C
E
F
50-4921
Side tone =
CMRR
V =O.lV
VRO
Gs=
V MI
VSO
V MI
Fig.4
Fig. 3
IL·1210~
G
lo.85v
A
A
TEST
CIRCUIT
R =6.8K a.
lO,uF
TEST
CIRCUIT
R =lKn
B
B
C
0
F
E
$-
5-'923
GR=
V RO
G MF =
V RI
331
V MO
V MF
492411
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
80
(Refer to the test circuits, VG = 1 to2V,I L = 12to80mA,
= 25 to +50°C, f = 200 to 3400 Hz, unless otherwise specified).
ELECTRICAL CHARACTERISTICS
51,52 and 53 in (a), T amb
Parameter
Test conditions
SPEECH OPERATION
VL
Line voltage
CMRR
Common mode rejection
f = 1 KHz
Gs
Sending gain
T amb = 25°C
V M1 = 3 mV
GR
Sending gain flatness
(vs. freq.)
VMI= 3 mV
Sending gain flatness*
(vs. current)
V M1 = 3 mV
S3 in (b)
Sending distortion
f = 1 KHz
IL= 15 mA
4
5
6.9
IL= 12 mA
IL= 30mA
IL= 60 mA
Tamb= 25°C
50
f= 1 KHz
IL25mA
IL= 50 mA
48
44
1
dB
2
± 1
dB
2
± 0.5
dB
2
2
10
%
%
2
46
Vso= 700 mV
Vso= 800 mV
-
dB
50
f ref = 1 KHz
V
Sending noise
V M1 - OV;
dBmp
2
Microphone input
impedance (pin-16)
VMI- 3 mV
40
Kn
-
Sending gain in MF
operation
VMI= 3mV
S2 in (b)
-30
dB
2
Receiving gain
VRI= 0.3V
f = 1 KHz
T amb = 25°C
IL= 25 mA
IL= 50 mA
dB
3
V R1 - 0.3V
f ref - 1 KHz
± 1
dB
3
±0.5
dB
3
3
Receiving gain flatness
(vs. freq.)
-70
VG=1V
-4
-2
-8
-6
Receiving gain flatness*
(vs. current)
Receiving distortion
f = 1 KHz
I L =15mA
Receiving noise
VRI=OV; VG=1V
150
%
%
IJV
Receiver output
impedance (pin 12-13)
V Ro =50mV
30
n
-
Sidetone
f = 1 KHz
T fmb = 25°C
S in (b)
36
dB
2
700
n
3
-10
IJA
-
ZML
Line matching
impedance
18
Input current for gain
control (pin 8)
V R1 = 0.3V
2
10
VRO=440mV
V Ro=480mV
f = 1 KHz
* F .xed ga on mode.
332
500
600
3
I.11
I
i
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
MULTIFREQUENCY SYNTHESIZER INTERFACE
Voo
M F supply voltage
Stand by and Operation
S2 in (b)
100
MF supply current
Stand by
Operation
S2 in (b)
MF amplifier gain
fMF in= 1 KHz
V MF in= 80 mV
VI
DC input voltage level
(pin 14)
V MF in= 80 mV
RI
I nput impedance
(pin 14)
V MF in= 80 mV
d
Distortion
V MF in= 150 mVp
IL> 15mA
2.4
15
mA
mA
-
dB
4
V
-
K!1
-
2
%
4
5
ms
-
1
V
-
V
-
-10
iJ.A
-
+10
iJ.A
-
17
0.3 Voo
60
Speech operation
M F operation
1.6
Muting stand by current
(pin 3)
Muting operating
current (pin 3)
-
0.5
2
Starti ng delay time
Muting threshold voltage
(pin 3)
V
2.5
S2 in (b)
333
-
CIRCUIT DESCRIPTION
1. DC characteristic
The fig. 5 shows the DC equivalent circuit of the LS656.
Fig. 5 - Equivalent DC load to the line
PIN 6
RI
PIN2
110
VL LINE
PIN9
PIN7
~
5 .. 4365
A fixed amount 10 of the total available current IL is drained for the proper operation of the circuit. The
value of 10 can be programmed externally by changing the value of the bias resistor connected to pin 4
(see block diagram).
The minimum value of 10 is 7,5 mA.
The voltage Vo= 37V of the shunt regulator is independent of the line current.
The shunt regulator (2) is controlled by a temperature compensated voltage reference (1) (see the block
diagram).
Fig. 6 shows a more detailed circuit configuration of the shunt regulator.
Fig. 6 - Circuit configuration of the shunt regulator
R2
RI
6
R3
S-492S
The difference IL -10 flows through the shunt regulator being Ib negligible. la is an internal constant
current generator; hence Vo= Va + la • Ra= 3.7V.
The V L • IL characteristic of the device is therefore similar to a pure resistance in series to a battery.
334
It is important to note that the DC voltage at pin 5 is proportional
to the line current (V 5 = V7 + V B= (lL -10) R3 + VB)'
The DC characteristic of the LS656 is shown in fig. 7.
Fig. 7 - DC characteristic
G-4707
VL
(V,
R,:30 n
R3:30 11
I
/'
/V"
'/
V
/'
,
10
40
60
80
'l(mA)
2. Two to four wires conversion
The LS656 performs the two wires (line) to four wires (microphone, earphone) conversion by means of
a Wheatstone bridge configuration so obtaining the proper decoupling between sending and receiving
signals (see fig. 8).
Fig. 8 - Two to four wires conversion
11
.
- - - -
------ -
--
LINE
___________
----4; _ _ _ _
5- 4367/1
ZR1
For a perfect balancing of the bridge __
L_ - - ZB
R2
The AC signal from the microphone is sent to one diagonal of the bridge (pin 6 and 9). A small percentage of the signal power is lost on ZB (being ZB > ZLI; the main part is sent to the line via R 1.
In receiving mode, the AC signal coming from the line is sensed across the second diagonal of the bridge
(pin 11 and 10). After amplification it is applied to the receiving capsule.
The impedance ZM is simulated by the shunt regulator that is also intended to work as a transconductance amplifier for the transmission signal.
335
APPLICATION INFORMATION
The impedance ZM is defined as
(continued)
/::"V 6 - 9
/::,.1 6 - 9
From fig. 6 considering C1 as a short circuit for AC signal, any variation /::"V 6 generates a variation:
Rb
The corresponding current change is
/::"1=
Therefore
/::"V 7
R3
/::"V 6
Ra
ZM = - - = R3 (1 + - )
/::"1
Rb
The total impedance across the line connections (pin 11 and 9) is given by
ZML = R1 + ZM//(R2 + ZB)
By choosing ZM :l!> R1 and Z,B:l!> ZM
ZML "" ZM = R3 (1 +
~)
Rb
The received signal amplitude across pin 11 and 10 can be changed using different values of R 1 (of
course the relationship ZL/ZB = R1/R2 must be always valid).
The received signal is related to Rl value according to the approximated relationship:
R1
R1 + ZM
Note that by changing the value of R1, the transmission signal current is not changed, being the microphone amplifier a transconductance amplifier.
3. Automatic gain control
The LS656 automatically adjusts the gain of the sending and receiving amplifiers to compensate for line
attenuation.
This function is performed by the circuit of fig. 9.
Fig.9
5-4696
336
I.
l~·.~
'1
II
I:
The differential stage is progressively unbalanced by changing V G in the range 1 to 2V (V REFG is an
internal reference voltage, temperature compensated).
It changes the current IG' and this current is used as a control quantity for the variable gain stages
(amplifier (4) and (5) in the block diagram). The voltage VG can be taken:
a) from the LS656 itself (both in variable and in fixed mode) and.
b) from a resistive divider, directly at the end of the line.
a) In the first case, connecting VG (pin 8) to the regulator bypass (pin 5) it is possible to obtain a gain
characteristic depending on the current.
In fact (see fig. 6)
The starting point of the automatic level control is obtained at IL = 25 mA when the drain current
10 = 7.5 mAo
Minimum gain is reached for a line current of about 50 mA for the same drain current 10 = 7.5 mAo
When 10 is increased by means of the external resistor connected to pin 4, the two above mentioned
values of the line current for the starting point and for the minimum gain increase accordingly.
It is also possible to change the starting point without changing 10 by connecting pin 8 to the centre
of a resistive divider placed between pin 5 and ground (the total resistance seen by pin 5 must be at
least 100 Kn). In this case, the AGe range increases too; for example using a division 1: 1 (50K/50K)
the AGe starting point shifts to about IL = 40 mA, and the minimum gain is obtained at I L = 95 mA.
In addition to this operation mode, the VG voltage can be maintained constant thus fixing the gain
values (Rx, Tx) independently of the line conditions.
For this purpose the V DD voltage, available for supplying the MF generator, can be used.
b) When gains have to be related to the voltage at the line terminals of the telephone set, it is necessary
to obtain V G from a resistive divider directly connected to the end of the line.
This type of operation meets the requirements of the French standard. (See the application circuit
of fig. 13).
4. Transducer interfacing
The microphone amplifier (3) has a differential input stage with high impedance (==' 40 Kn) so allowing
a good matching to the microphone by means of external resistor without affecting the sending gain.
The receiving output stage (6) is particularly intended to drive dynamic capsules. (Low output impedance (lOOn max); high current capability 3 mAp).
When a piezoceramic capsule is used, it is useful to increase the receiving gain by increasing R 1 value
(see the relationship for V R).
Whit very low impedance transducer, De decoupling by an external capacitor must be provided to
prevent a large De current flow across the transducer itself due to the receiving output stage offset.
5. Multifrequency interfacing
The LS656 acts as a linear interface for the Multifrequency synthesizer M761 according to a logical
signal (mute function) present on pin 3.
When no key of the keyboard is pressed the mute state is low and the LS656 feeds the M761 through
pin 15 with low voltage and low current (standby operation of the M761). The osci IIator of the M761
is not operating.
337
When one key is pressed, the M761 sends a "high state" mute condition to the LS656. A voltage comparator (8) of LS656 drives internal electronic switches; the voltage and the current delivered by the
voltage supply (9) are increased to allow the operation of the oscillator.
This extra current is diverted by the receiving and sending section of the LS656 and during this operation the receiving output stage is partially inhibited and the input stages of sending and receiving ampi ifiers are switched 0 F F.
A controlled amount of the signalling is allowed to reach the earphone to give a feedback to the subscriber; the MF amplifier (10) delivers the dial tones to the sending paths.
The mute function can be used also when a temporary inhibition of the output signal is requested.
The application circuit shown in fig. 10 fulfils the EU ROPE II standard (-6, -8 dBm). If the EUROPE I
levels are required (-9, -11 dBm) an external divider must be used (see fig. 11).
APPLICATION INFORMATION
Fig. 10 - Application circuit with multifrequency (EU ROPE II STD)
C3
82nFI
330.n.
t-'----t---t------ - - - - - - - -------,----+---4:=:J;""'.,--c=}----;
R1
I1l--o=:r-+lh
11
Voo
18
R 7'
15
13 I--o=:r--I--'
R7
MUTE
1S
10
MF
LS656
INPUT
14
LINE
16H-~--t-~,
y. R6
J!.50F
"'!':'"
6.BKfi ICt,
b _ _ _ _ _ _ ':V
L~
Fig. 11 - Application circuit with multifrequency (EU ROPE I STD)
18
1Sf------+--t-=-=--.j
16f---rl=H--F"-"-'='>j
M761
17
120pF
* TOLLERANCE ,,±2%
338
I
I
J
I
APPLICATION INFORMATION (continued)
Fig. 12 - Sending and receiving gain vs. line current
(application circuit of fig.1 0)
)
i
--
,
(
50
l
i
46
I
\\
- - -#o-~-'-- +
(
-
--
.\
INE
I
R2
r
e
1
,
so
'"
' OOft
R7
t
,
,
9
1'3~~
'---
Fig. 14 - Application circuit with gain controlled by line voltage (French standard)
CURRENT
82 nF
330n
12
13
10
of
20Kfi
339
C7
Rs0200n
,~
47
22Kfi
8
"of
CJ
--*
P5
lS656
J
~ 11.
30 fl
LINE
1I'0pF
IlO
13
7
CIRCUli
R7'
'Or----
IL(mA)
lIMlllNG
lOOll
"
'00<"
:C2
330n
R'
£'5
1\
50
82nFn
30!l,w
"
(
I
ii
cst
R~=13Kn\ '\R4=6.SKO
i
I
i+-
I
i
Fig. 13 - Application circuit without multifrequency
5
'5
'f
,
¢1
(6
r--R6
:~5
.SKfL
5
'"
APPLICATION INFORMATION
Fig. 15 - Application circuit
with fixed gain operation
(continued)
Fig. 16 - External mute function
15
5 - 5251
b) without mu Itifrequency
a) with multifrequency
Main gain condition
Main gain condition
In addition to the above mentioned applications, different values for the external components can be
used in order to satisfy different requirements.
The following table (refer to the application circuit of fig. 10) can help the designers.
Component
Value
Rl
30 n
R2
330n
R3
30n
R4
13 Kn
Purpose
Note
Bridge Resistors
Line current sensing.
Fixing DC
characteristic.
Rl controls the receiving gain. When high current values are allowed, Rl must be able to
dissipate up to lW.
The ratio R2/Rl fixes the amount of signal
delivered to the line. Rl helps in fixing the DC
characteristics (see R3 note).
The relationships involving R3 are:
-
ZIIIIL = (20 R311Z s ) + Rl
ZL//ZML
R3
-
Gs = K·
-
V L = (I L - 10 ) (R3 + R1) + Va; Vo= 3.7V.
Without any problem it is possible to have a
ZML ranging from 600 up to 900n. As far
as the power dissipation is concerned, see
Rl note.
The suggested value assures the minimum operating current. It is possible to increase the
supply current by decreasing R4 (they are
inversely proportional), in order to achieve the
shifting of the AGC starting point. (See fig. 16).
After R4 changement, some variations could be
found also in other parameters, i.e. line voltage.
Bias Resistor
340
I,
Ii
Component
Value
R5
2,2 Kn
R6
6,8 Kn
Purpose
8alance Network
Nota
It's possible to change R5 and R6 values in
order to improve the matching to different
lines; in any case:
R2
Rl
Zs
=
R5 + R6/1X C4
R7-R7'
100n
Receiver impedance
matching
R7 and R7: must be equal; the suggested value
is good for matching to dynamic capsule; there
is no problem in increasing and decreasing
(down to On) this value, A DC decoupling must
be inserted when low resistance levels are used
to stop the current due to the receiver output
offset voltage (max 200 mVl,
R8
200n
Microphone
impedance matching
The suggested value is typical for a dynamic
microphone, but it is possible to choose R8 in a
wide range.
Regulator
AC bypass
A value greater than 10 I'F gives a system start
time too high for low current line during MF
operation; a lower value gives an alteration of
the AC line impedance at low frequency.
Cl
C2
47 nF
Matching to a
capacitive line
C2 changes with the characteristics of the
transmission line.
C3
82nF
Receiving gain
flatness
C3 depends on balancing and line impedance
versus frequency.
C4
15 nF
8alance network
See note for R5, R6.
DC filtering
The C5 range is from 0.1 I'F to 0.47 IIF. The
lowest value is ripple limited, the higher value
is starting up time limited.
C5
C6-C7
1000pF
RF bypass
C8
Receiving output
DC decoupling
C9
Receiving input
DC decoupling
341
See note for R7, R7.
LINEAR INTEGRATED CIRCUITS
OPERATIONAL AMPLIFIERS
The LS 709 series features low offset, high input impedance, large input common mode range, high
output voltage swing. The amplifier is intended for use in D.C. servosystems, high impedance analog
computer,low level instrumentation applications, and for the_,generation of special linear and non linear
transfer functions.
ABSOLUTE MAXIMUM RATINGS
TO-99
Supply voltage
Input voltage
Differential input voltage
Operating temperature for LS 709/LS 709A
for LS 709C
Power dissipation at T amb = 70°C
Storage temperature
DIP
± 18 V
± 10 V
±5V
-55 to 125°C
o to 70 ~C
520 mW
400 mW
-65 to 150°C -55 to 150 °C
1) For supply voltages less than ± 10V maximum input voltage is equal to the supply voltage.
MECHANICAL DATA
6/82
Dimensions in mm
342
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
.'.
9
Type
TO-99
DIP
LS 709
LS 709T
-
LS 709A
LS 709 AT
-
LS 709C
LS 709 CT
LS 709 CB
SCHEMATIC DIAGRAM (pin numbers are referred to the TO-99 version)
?8
r-----~~~--------~~----~--------~--~--O·~
R1
2Skll
R2
2Skll
'--~t-t::.a4
as
R1S
30kll
a13
4
'---------'>----------------"---:5--:-2"'74-'"'--{)-vs
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
343
OUTPUT FltEO.CONP,
ELECTRICAL CHARACTERISTICS (see note)
LS 709A
Ib
1
6
5
2
10
7.5
mV
mV
I nput bias
Tamb~ T min
Tamb~ 25c C
0.3
100
0.6
200
0.5
200
1.5
500
0.36
300
2
1500
/lA
nA
Tamb~ T max
Tamb~ T min
Tamb~ 25c e
3.5
40
10
50
250
50
20
100
50
200
500
200
75
125
100
400
750
500
nA
nA
nA
I nput offset
Ro
Output resistance Tamb~ 25 c e
Is
Supply current
Vs~±15V
Transient response R isetime
Overshoot
Tamb~
25 c C
Slew rate
Tamb~
25 c e
Gv
Tamb~
Tamb~
170
700
40
150
150
T amb~25ce
2.5
100
400
50
50
150
250
250
kn
kn
150
n
3.6
2.6
5.5
2.6
6.6
mA
1.5
30
0.3
10
1
30
0.3
10
1
30
jJ.s
%
Vi~20mveL<;;100pF
Average tempera- Rg~ 50n
ture coefficient
T amb~ 25c C to
of input offset
Tamb~ 25 c C to
voltage
Rg~ 10 kn
Tamb~ 25c C to
Tamb~ 25 c c to
Large signal
voltage gain
85
350
T min
25 c e
Vs~±15V
0.25
T max
T min
1.8
1.8
10
10
T max
T min
2
4.8
15
25
88
93
97
±12
±10
±14
±13
0.25
0.25
V/jJ.s
3
6
6
12
",vre
",Vrc
",v/ce
",v/ce
RL# 2 kn
Vo~±10V
Output voltage
Vs~±15V
RL~
swing
Vs~
±15V
RL~
Vi
Input voltage
range
Vs~±15V
±8
eMR
Common mode
Rg<;; 10 kn
80
Rg<;; 10 kn
80
Va
Max.
3
2
Input resistance
I'Nos
Typ.
0.6
Ri
---.6T
Typ. Max. Min.
Rg<;; 10 kn
Rg<;; 10 kn T amb~25cC
current
SR
Typ. Max. Min.
I nput offset
voltage
current
los
LS 70ge
Unit
Min.
Vas
LS 709
Test conditions
Parameter
10 kn
2 kn
97
88
93·
83
93
dB
±12
±10
±14
±13
±12
±10
±14
±13
V
V
±8
±10
±8
±10
V
110
70
90
65
90
dB
88
76
92
74
92
dB
rejection
SVR
Supply voltage
rejection
Note: These specifications, unless otherwise specified, apply for Tamb= -55 to 125c e for LS 709/LS 709A and
T amb = 0 to 70c e for LS 70ge with the following conditions: Vs= ± 9V to ± 15V, el= 5000 pF, Rl= 1.5 kn,
C2= 200 pF and R2= 51 n. (See fig. 8 and fig. 17).
344
II,
I.•. ,
I~
~
I
Fig. 1 - Voltage gain vs. supply voltage (for 709A)
(,-,970
G,
V
Tam b"-5S'toll5
f--
60k
RL ~2kn
....... f-"""
V
./
",
./
30k
~,~~.~~ro~l
....-
lamb" -5S'C to12S'C
....... ~
....... ~\"'~P""t'l.
15
I
...-
.-'~.-
.-'-
~.-
V
~,
i--
~ I--
Wk
w
w
"
10
Fig. 5 -Output voltage swing
vs. load resistance(for 709A)
Fig. 4 - Power consumption
vs. supply voltage (for 709A)
Fig. 6 - Input bias current
vs. ambient temperatu re (for
709A)
(,-2986
I
P to!
(m' )
II
)
Tamb= 2Soc;
Tam b'2S'C
./
/'
./
80
V
V
30
./
....... f-"""
", .......
v
400
300
./
..-
70
;-l987
'b
(nA)
v :!ISV
"0
50
!--
W
V
.....-
20k
(,-2919
G-297&
'0
20
./
Fig. 3 - Input common
mode voltage range vs. supply voltage (for 709A)
(Vpp )
25
V
V-'./
40k
Fig. 2 - Output voltage swing
vs. supply voltage (for 709A)
.....-
18
"\
200
'\.
~
/
I
"'""' '---. r-
/
10
10-'
Fig. 7 - Input offset current vs. ambient temperature
(for 709A)
-60
Fig. 8 - Transient response
test circuit
0
20
60
Fig. 9 - Transient response
(for 709A)
REL,6,TlVE,---,--r--,-,--,-,---f"""-,
I
40
-20
OOTPUT
1\
Vs ,'15V
Tam b'2S'C
1.2
\
30
r--..
o.s
\
20
0.6
'\
'"
10
I
-60
-20
0
20
I
0.4
--.
RISE TIME
02
05
60
345
'5
t
(,us)
Fig. 10 - Slew rate vs. closed
loop gain using recommended compensation networks
(for 709A)
SR'~~~~II~~~~~~!!~I
Fig.11- Voltage gain vs. suplply voltage (for 709)
(,296'
(1//1-'5)'
'I--- .mHS·
V5~'15V
•
60>
r
./
--
/
>!o-
f--
-'r--
--
~+ ~+
H-
I
r--
-t
_~c...\:'I.
1-- L"
~10--
.......
V
......"""~
"'rJ!'
-
1---
'"
10
~
-
..-i<:::' V'-'
I
~
I-
lamb" O'C to 70'C (LS709C)
20
I
i
..
f--
r--
I - f--
V
lamb- -55'C to 125'C (LS709)
./
I
~
I
V
Rl ;:>:2kfl
'"
G-l98<
1/
~tt~b-S5'''R 12;"
1--+-tt-+--- -
1-
10
-~---
--
G.
10'
10
Fig. 12-0utputvoltageswing
vs. supply voltage (for 709
and 70ge)
14
Fig.13 - Voltage gain vs. supply voltage (for 70ge)
Fig. 14 - Input bias current
vs. ambient temperature (for
70ge)
(;-2963
Fig. 15 - Input offset current vs. ambient temperature
(for 70ge)
13-1992
I
G.
lamb-O'C to 70"C
r--- RL :.'!2kn
Vs·!15V
Vs~!15V
/'
!Vs (V)
0,8
160
0,6
120
/'
10k
~V
V
V
......
"'-
/'
"
0,2
80
~
r--...
~
I-- r10
12
14 !Vs (V)
-60
60
100 lamb('C)
60
20
0
20
........
60
r-100 Tamb("C)
Frequency compensation for all types
Fig. 16 - Open loop frequency response for various
values of compensation
Fig. 17 - Frequency compensation circuit
G-J~
IIIII~
111m
G.
(dB)
G. "~I~Ir-nTmw-rITrnm-TPv.IT'~'~l5vTr~
(dB) H+iffll-+H-tttHt-Httttllt---tlTamb :25'C
1/$"t'51/
T amb'"2S'C
IlIl'e,." 11111111.
100
80
IllIIn
11111111
Fig. 18 - Frequency response for various closed loop
gains
._""
:--
60
~'- "
c~.~,.~
'bo
.'$" '('~.. )!~
.0,...-9/~ ~$
'0
4-4. C'<,,,,<,; Jo.o,c-
.f~c..
0.o,c-
S-21~l
"U$~R:2.son
... 1\fiI t~.mplif, ... ,$
opeoratfod .... ,th eap,o.e,hv. lo~,"9
20
..~
20
_20 L..l.lllllllL...J..J.lllllll-LllUU'---LUUJJlI.....1..J..J1Jill
-20
10'
10'
10'
10'
346
10'
10' f (Hz)
LINEAR INTEGRATED CIRCUITS
PROGRAMMABLE OPERATIONAL AMPLIFIER
• MICROPOWER CONSUMPTION
• INTERNALLY FREQUENCY COMPENSATION
• OFFSET NULL CAPABI LlTY
• SHORT CI RCUIT PROTECTION
• LOW INPUT BIAS CURRENTS
• LOW NOISE
The LS 776 is a programmable operational amplifier available in three different packages (TO-99,
Minidip and SO-8 imicropackage). High input impedance, low supply currents and low input noise over
a wide range of operating supply voltages coupled with programmable electrical characteristics, make it
an extremely versatile amplifier for use in high accuracy, low power consumption analog applications.
Input noise voltage and current, power consumption and input current can be optimized by a single
resistor t..f current source that sets the quiescent current for nanowatt power consumption or for characteristics similar to the LS 141. Internal frequency compensation, absence of "latch-up", high slew rate
and short circuit current protection assure ease of use in long interval integrators, active filters and
sample and hold circuits. The LS 776 is available with hermetic gold chip (8000 Series).
ABSOLUTE MAXIMUM RATINGS
Vs
VI (1)
tNI
YSET
ISET
Top
Supply voltage
I nput voltage
Differential input voltage
Maximum voltage to ground at ISET
Maximum current at ISET
Operating temperature for LS 776
for LS 776 C
Output short circuit duration (2)
Power dissipation at T amb = 70°C
Storage and junction temperature
TO-99
Minidip
Jlpackage
520 mW
-65 to 150°C.
±18V
± 15V
±30V
Vs -2V to Vs
500 JlA
-55 to 125°C
o to 70°C
indefinite
665mW
-55 to 150°C
400mW
-55 to 150°C
1) For supply voltage less than ± 15V, input voltage is equal to the supply voltage
2) The short circuit duration is limited by thermal dissipation
Dimensions in mm
MECHANICAL DATA
347
6/82
I
[
CONNECTION DIAGRAMS AND ORDERING NUMBERS
(top views)
OFFSET
NULL
'D1SET
INVERTING
INPUT-
2
1
""
3
''"''eT
INVERTING
INPUT.
I
L~~~~6_
I
I
I--
l
I
TO-99
INVERTING
INPUT",N
INVERTING
INPUT.
OF~3c~
4
Type
.V s
:0:'::
3
6 OUTPU1
4
S
Minidip
OF~3c~
80-8
LS 776T
I
LS 776C
LS8776
1
Lssn-6:
I
LS 776CT
LS 776 CB
I
--------
1
l ______
SCHEMATIC DIAGRAM
'SET
7
.---------------~------~._---~--~--~----~----------~-___o.vs
INVERTING
INPUT 2
R4
500
R5
lOOn
R6
R7
6
OUTPUT
lOon
lOon
t------lt_09
OFFSET
NULL
~'0c~ET
R1
10kO
5- 2107/1
019 _::I--+.-fb-'°'""c"'-8----1--l:. 020
R2
10kQ
4
' - - - - - - -. . .- - - - - - - - '__________- - - -. . .---+-------~>_--------_+----__{)-vs
I
THERMAL DATA
Rth j-amb
TO-99
Minidip
80-8
Thermal resistance junction-ambient
* The thermal resistance is measured with device mounted on a ceramic substrate (25 x 16 x 0.6 mm)
348
ELECTRICAL CHARACTERISTICS for LS 776
I
(V s= ± 15V. T amb = 25°C unless otherwise specified)
J.:
ISET= 1.5"A
Parameter
ISET= 15"A
Test conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Vas
I nput offset voltage
R g 0(10kn
2
5
2
5
mV
los
Input offset current
R g 0(10kn
0.7
3
2
15
nA
Ib
I nput bias current
2
7.5
15
50
Ri
I nput resistance
50
5
nA
Mn
Ci
I nput capacitance
2
2
pF
l;V os
I nput offset voltage
adjustment range
9
18
mV
Gv
Large signal voltage gain
Ro
Isc
RL> 75 kn
Vo=±1,OV
RL> 5 kn
Vo= ± 10V
106
dB
112
100
112
dB
Output resistance
5
1
kn
Output short-circuit
3
12
mA
current
Is
Supply current
Ps
Power consumption
Transient response
(unity gain)
20
VI = 20 m V
CL = 100pF
Rise time tr
Slew rate
Vo
Output voltage swing
180
"A
5.4
mW
RL> 5 kn
Overshoot l; Vo
SR
160
25
0.75
RL> 5 kn
± 12
RL> 75 kn
1.6
0.35
0
10
%
0.1
0.8
V I"s
± 13
V
"s.
± 14
V
± 10
RL> 5 kn
The following specifications apply for T amb = -55 to 125°C
vas
Input offset voltage
Rg 0(10kn
6
6
mV
los
Input offset current
Tamb= 125°C
5
15
nA
Tamb= -55°C
10
40
nA
T amb = 125°C
7.5
50
nA
T amb = -55°C
20
120
nA
Ib
Input bias current
Vi
Input voltage range
CMR
Common mode rejection
Rg 0( 10 kn
70
90
70
90
dB
SVR
Supply voltage rejection
Rg 0( 10 kn
76
92
76
92
dB
Gv
Large signal voltage gain
RL> 75 kn
Vo
Output voltage swing
Is
Supply current
Ps
Power consumption
± 10
Vo= ± 10V
RL> 75 kn
± 10
100
98
± 10
±10
30
0.9
349
V
dB
V
200
"A
6
mW
ELECTRICAL CHARACTERISTICS for LS 776
IV.= ± 3V, Tamb = 25°C unless otherwise specified)
ISET= 1.5/LA
Parameter
ISET= 15/LA
Test conditions
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
VOS
Input offset voltage
2
5
2
5
mV
los
Input offset current
0.7
3
2
15
nA
Ib
I nput bias current
2
7.5
15
50
Ri
Input resistance
50
Rg " 10 kn
5
nA
Mn
Ci
In pu t capaci tance
2
2
pF
tNos
Input offset voltage
adjustment range
9
18
mV
Gv
Large signal voltage gain
RL:> 75 kn
Vo= ± 1 V
R L :> 5 kn
Vo= ± lV
94
106
dB
94
106
dB
Ro
Output resistance
5
1
kn
Isc
Output short-circuit
current
3
5
mA
I.
Supply current
13
20
130
160
/LA
Ps
Power consumption
78
120
780
960
/LW
Transient response
(unity gain)
SR
Vi = 20mV
C L .. l00pF
RL:> 5 kn
Rise time tr
3
0.6
/LS
Overshoot I!. Vo
0
5
%
0.03
0.35
V//Ls
Slew rate
RL:> 5 kn
The following specifications apply for Tamb
= -55 to 125°C
"'os
Input offset voltage
Rg" 10 kn
6
6
mV
los
I n put offset current
Tamb= 125°C
5
15
nA
Tamb= -55°C
10
40
nA
Tamb= 125°C
7.5
50
nA
20
120
nA
Ib
Input bias current
Tamb= -55°C
V,
Input voltage range
CMR
Common mode rejection
Rg.. 10 kn
70
86
70
86
dB
SVR
Supply voltage rejection
Rg" 10 kn
76
92
76
92
dB
Gv
Large signal voltage gain
RL:> 75 kn
Vo= ± lV
R L :> 5 kn
Vo= ± lV
Vo
Output voltage swing
± 1
V
dB
B8
·88
±2
RL:> 75 kn
± 1
dB
± 2.4
V
± 1.9 ± 2.1
R L :> 5kn
V
I.
Supply current
25
180
Ps
Power consumption
150
1080 /LW
350
/LA
I
j
'i
ji
I
ELECTRICAL CHARACTERISTICS for LS 776C
(Vs= ± 15V, T amb = 25°C unless otherwise specified)
ISET= 1.5J.!A
Parameter,
Unit
Min.
VOS
Input offset voltage
los
I n put offset cu rrent
Ib
Input bias current
Ri
Input resistance
ISET= 15J.!A
Test conditions
Rg<10k.l1
Typ.
Max.
Min.
Typ.
Max.
2
6
2
6
mV
0.7
6
2
25
nA
2
10
15
50
5
50
nA
M.I1
Ci
Input capacitance
2
2
pF
/eNos
Input offset voltage
adjustment range
9
18
mV
Gv
Large signal voltage gain
112
dB
RL> 75 k.l1
Vo= ± 10V
5 k.l1
Vo= ± 10V
RL>
94
' 112
dB
,94
Ro
Output r,esistance
5
1
k.l1
Isc
Output short-circuit
3
12
mA
Is
Supply current
Ps
Power consumption
current
Transient response
(unity gain)
20
30
160
0.9
Vi = 20 mV
CL<100pF
SR
Slew rate
RL> 5 k.l1
Vo
Output voltage swing
RL> 75 k.l1
RL>
190
J.!A
5.7
mW
RL> 5 k.l1
Rise time tr
Overshoot 11 V 0
± 12
1.6
0.35
0
10
%
0.1
0.8
V/J.!s
± 13
V
J.!s
± 14
V
± 10
5k.l1
The following specifications apply for T amb = 0 to 70°C
Vos
Input offset voltage
R g< 10 k.l1
7.5
7.5
mV
los
Input offset current
Tamb= 70°C
6
25
nA
T amb = O°C
10
40
nA
T amb = 70c C
10
50
nA
T amb = O°C
20
100
nA
Ib
I nput bias current
± 10
± 10
V
Vi
I nput voltage range
CMR
Common mode rejection
Rg < 10 k.l1
70
90
70
90
dB
SVR
Supply voltage rejection
Rg< 10k.l1
74
92
74
92
dB
Gv
Large signal voltage gain
RL> 75 k.l1
Vo
Output voltage swing
RL> 75 k.l1
Is
Supply current
Ps
Power consumption
Vo= ± 10V
351
94
94
± 10
± 10
I
/,
dB
V
35
200
J.!A
1.05
6
mW
!
ELECTRICAL CHARACTERISTICS for LS 776C
± 3V, Tamb = 25°C unless otherwise specified)
(Vs=
ISET= 1.5MA
Unit
Min.
Vas
Input offset voltage
lOS
Input offset current
Ib
I nput bias current
ISET= 15MA
Test conditions
Parameter
R g< 10 kn
Typ.
Max.
Min.
Typ.
Max.
2
6
2
6
mV
0.7
6
2
25
nA
2
10
15
50
nA
50
5
Mn
Ri
I nput resistance
Ci
Input capacitance
2
2
pF
!Nos
I nput offset voltage
adjustment range
9
18
mV
Gv
Large signal voltage gain
RL> 75 kn
Vo= ± lV
RL> 5 kn
V o - ± lV
88
106
dB
88
106
dB
Ro
Output resistance
5
1
kn
Isc
Output short-circu it
current
3
5
mA
Is
Supply current
13
20
130
170
MA
Ps
Power consumption
78
120
780
1020
MW
Transient response
(unity gain)
Vi = 20 m V RL> 5 kn
C L < 100 pF
Rise time tr
Overshoot
SR
to Vo
Slew rate
RL> 5 kn
3
0.6
0
5
%
0.03
0.35
VII's
MS
The following specifications apply for Tamb = 0 to 70°C
vAS
Input offset voltage
Rg <10kn
7.5
7.5
mV
los
I nput offset current
T amb = 70°C
6
25
nA
T amb = O°C
10
40
nA
T amb = 70°C
10
50
nA
Tamb= O°C
20
100
nA
Ib
I nput bias current
± 1
±1
V
Vi
Input voltage range
CMR
Common mode rejection
R g< 10 kn
70
86
70
86
dB
SVR
Supply voltage rejection
Rg< 10 kn
74
92
74
92
dB
Gv
Large signal voltage gain
RL> 75 kn
Vo= ± 1V
5 kn
Vo= ± lV
RL>
Vo
Output voltage swing
dB
88
±2
RL> 75 kn
RL>
88
dB
V
± 2.4
5kn
±2
V
± 2.1
Is
Supply current
25
180
MA
Ps
Power consumption
150
1080
MW
352
Fig. 1 - Input bias current
vs. set current
Fig. 2 - Input bias current
vs. ambient temperature
10
Fig. 3 - Input offset current
vs. ambient temperature
1,1
1o,
II
i~
30
1/
10
~,
"dllloH II
"
"
/
12
1.5
·60
Fig. 4 - Change in input offset voltage vs. set
current
dVos
()Jvl
300
~~JJTIIT
,j.~
i"l' lill1 -;'
t---.+.
1
115=1310tI8\1
_100
>-1 ~~
I,
---'--,-T
i
t
'1
~500
20
60
Fig. 6 - Input noise voltage
vs. set current
'N'rnmg;m
= lSpA
300
200
t--- I
I
r
ii
100
10
i--..
I
-1; ; , I
_300
0
400
jI l
f'j.
-20
(~):SU
Vs=.!.15V
ISET
.60
100 Tilmb{OC)
Fig. 5 - Change in input offset voltage vs. ambient temperature
(unnulled)
,.,",,"
500
I
100
60
A
T
-zoo
1
-300
10
10. 1
-60
ISEy(jJA)
Fig. 7 - Input noise voltage
and cu rrent vs. frequency
-20
0
20
60
100 Tamb<"C)
Fig. 8 - Input noise current
vs. set cu rrent
10-'
'°.
1
10 'SET (,uA)
Fig.9 - Optimum source resistance for minimum noise vs. set
current.
11111
.
I
1 0 , _
lamb =25*C
,
F
Vs :!;310.!.18V
f .. lkHz
llf" 1Hz
L+--U.~..!l-------!--l-!l-!l111TI1illl--------!--nr1TLjljnml!ll--!--4J-!ljIIlO"
10
10'
10'
10'
f (Hz)
10'
10-!
... ...
353
TIm
Trmm
, ..
10
..
ISET (jJA)
10' c...,f---Lj.-4.lf,tL-f-1-!ljljlL.,l-4ljljlL
10·'
10
ISET (jJA)
Fig. 10- Output voltage
swing vs. load reo
sistance
Fig. 11 - Output voltage
swing vs. supply
voltage
Fig. 12 - Gain bandwidth
product vs. set
current
~"-''-,,~-r'-,,,,-r~~''
", H".Lmb-',>ZS"·,,+-+-H-+++-H-++-i
•.
28~~~t~~+=t~::,+.,=~L,~" ~IO~"~"~A+~H
"H-+++-H-+R~l'r",>_n,,~~~7~?~~
"
lamb
~
25"C
1111
1111
~1.S
15ET
V
lo15)JA
:!Jv
1111
",
".
"
Fig. 13- Open loop voltage
gain vs. ambient
temperatu re
Fig. 14 - Open loop voltage
gai n vs. ambient
temperature
II
V, :1
SET·
,(Xl>
Fig. 15 - Open loop voltage
gain vs. set current
:t1SV
L~
/.I
1.4"-4
800>" ""'-"
ET'
1.2M
1. /.IA:
10'. _ _
JJA.:
'Is :
1. /-IA.: 15k
~
3'1
soo>
400k
"Xl>
amb: 2S·C
L=7Skfl
200t
'--LLllll.llL.-'-.LLl.llIllL-III...L.LLLll!-"
10'
.60
_20
0
20
-60
Fig. 16 - Common mode rejection
vs.
set
current
CMR
I III
,
(dB
(,_2891
-20
0
20
"
60
Fig. 17 - Supply voltage' rejection
vs.
set
current
(~,,::, ~=:=I=II;'II;III=:::~~;=:=::~
Fig. 18 - Supply current vs.
ambient temperature
'.
-++
(jJA)
lilmb :25'(:
lamb =lS
V :13to!18v
9J
I
'15 :~15V
~t15/JA
v
dlSV
v,
=il
,/
./
I
69
"
os
20
./
I ..
80
,0
IO
lis: !JV
..
f-++++ttItl--++fttHlto--,-++fIFIlII
ET =T. }lA
V :1;15'1
ro
..
ISET (",Al
354
'Is =!3Y
-60
-ro
0 20
60
100 Tamb('C)
I,
1
Fig. 19 - Standby supply
current VS. set
Fig. 20 - Slew rate
current
VS.
Fig. 21 - Voltage follower
transient response
(unity gain)
set
" e-J--i-+-H--P+-I-+++-f-+++-1
10-' '-LllJl!jj'-LlllilJJ'-Llil
10-'
Ml'
10
as
I5£T(,I.I"')
"
2S
t (/-IS)
TYPICAL APPLICATIONS
Fig. 22 - High accuracy sample and hold
Fig. 23 - Nanowatt amplifier
.sv
5-258611
S~~~JlLE
Fig. 24 - High input impedance
amplifier
CONTROL
-sv
HOLD
*HOLD CAPACITOR
5-258511
e;
355
TYPICAL APPLICATIONS (continued)
Fig. 25 - Multiplexing and signal conditioning
-15V
2.7Mfi
+---C:J-O.15V
270kn
5- 2588
Fig. 26 - Multiple feedback bandpass filter
Fig. 27 - Gated amplifier
lMfi
'>''---~---r; 0 UTPU T
VEE
5-3936
5- 3935
356
I ii
LINEAR INTEGRATED CIRCUIT
~,
1,',:"
PRELIMINARY DATA
DUAL HIGH PERFORMANCE OPERATIONAL AMPLIFIER
•
•
•
•
•
•
•
!
j:;
1,'
SINGLE OR SPLIT SUPPLY OPERATION
LOW POWER CONSUMPTION
HIGH UNITY GAIN BANDWIDTH
NO CROSSOVER DISTORTION
NO POP NOISE
SHORT CIRCUIT PROTECTION
HIGH CHANNEL SEPARATION
,~
~
!.I
The LS 4558N is a high performance dual operational amplifier with frequency and phase compensation
built into the chip. The internal phase compensation allows stable operation as voltage follower in spite
of its high gain-bandwidth products. The circuit presents very stable electrical characteristics over the
entire supply voltage range and the specially designed input stage allow the LS 4558N to be used in low
noise audio signal processing application. The optimized class AB output stage completely eliminates
crossover distortion, under any load conditions, has large source and sink capacity and is short circuit
protected.
,
J";,,
,',',
ABSOLUTE MAXIMUM RATINGS
V5
VI
Vi
Ptot
Supply voltage
Input voltage
Differential input voltage
Power dissipation at T amb = 70°C
Top
Tj
T stg
Operating temperature
Junction temperature
Storage temperature
Minidip
Micropackage
± 18
±Vs
±(Vs -1)
665
400
o to 70
150
-55 to 150
V
V
mW
mW
°C
°C
°C
ORDERING NUMBER: LS 4558 NB (Minidip)
LS 4558 NM (Micropackage)
MECHANICAL DATA
Dimensions in mm
]
1:,
i
357
6/82
CONNECTION DIAGRAM
(top view)
OUTPI,IT
A
~OU~UT
INIlINP.
A
7
NONINI!
INP. A
6 ~ INI!~NP.
h NON INV.
5 ~
INP. B
5-3590
SCHEMATIC DIAGRAM
(one section)
INVERTING
INPUT
NON INVERTING
INPUT
8
~_ _- 1_ _ _ _ _ _~_ _ _ _ _ _~_ _ _ _~_ _~_ _ _ _~~_ _ _ _ _ _~_ _ _ _ _ _--o~s
R7
OUTPUT
RS
Q16·
5-5155
THERMAL DATA
Rth
j-amb
Minidip
Thermal resistance junction-ambient
(*) Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mml.
358
120 °e/W
80-8
200*
°e/W
ELECTRICAL CHARACTERISTICS (V s = ± 15V, Tamb = 25°C, unless otherwise specified)
Parameter
Test cond itions
Min.
Typ.
Max.
Unit
Is
Supply current (.)
1
2
mA
Ib
I nput bias current
50
500
nA
Ri
I nput resistance
T min < Top
f = 1 KHz
Vos
I nput offset voltage
Rg .. 10 Kn
Rg <;; 10 Kn
T min < Top
los
Gain-bandwidth product
f = 20 KHz
Total inpu t noise voltage
f - 1 KHz
eN
Popcorn no ise
d
Distortion
Vo
Output voltage swing
RL- 2 Kn
Vo
Large signal voltage swing
RL-l0 Kn
f = 10 KHz
Transient response
Slew rate
unity gain
R L = 2 Kn
CMR
Common mode rejection
V i -l0V
T min < Top
VI lV
T min < Top
f - 10 KHz
Supply voltage rejection
Channel separation
200
nA
500
nA
86
100
d8
2
3
8
10
18
0.03
R L - 2 Kn
< T max
f
< T max
100 Hz
R g- l Kn
(.) Both amplifiers.
359
MHz
15
nV
VRZ
10
RL= 2 Kn
f = 1 KHz
Vi - 20mV
C L = 100 pF
SR
mV
mA
Rg- 50n
R = 1 Kn
R~= 10 Kn
Gv= 20 dB
Vo=2 Vpp
Rise time
5
7.5
23
B-1 Hz to 1 KHz
Rg= 10 Kn
t =·10 sec
Overshoot
CS
< T max
current
B
nA
Mn
mV
J
I
Output short circuit
eN
SVR
0.5
20
RL= 2 Kn
800
1
< Top < T max
Large signal open loop
voltage gain
Gv
0.3
I nput offset current
T min
Ise
< T max
1
/JV
peak
%
± 13
V
28
Vpp
0.13
/JS
5
%
0.8
1.5
V//Js
70
90
dB
80
100
dB
105
dB
l
Fig. 1 -Open loop frequency
and phase response
Fig. 2 - Open loop gain vs.
ambient temperature
IJ
Gv
(dB )
Vs o,,5"- RLo2Kn_ -
200
f-"'.+-',-"+--,--+--..,...--] 160
10 5
120
10 0
Fig.3 - Supply voltage rejection vs. frequency
I
I
i
I
,
.
80
-t+t-
95
1
I
'ii
0
i
50
-50
r+-
.
W~--L
10
Fig. 5 - Output voltage
swing vs. load resistance
Fig. 4 - Large signal frequency response
t
'.'-j
40
I
__
10'
~_-L_~~_~
10' 1(Hz)
10'
10'
Fig. 6 - Total input noise vs.
frequency
G_3713
G-369SIt
Illllll
Vo
(Vpp )
24
Vo
(Vpp )
I
20 -
16 f12
Vs= ~15V
RL=2KIl.
Gv =20dB
' d =. 3°/0
,
Gv =20dB
f =1kHz
d
3 0 1ft
20
16
!,
/
.
,
10'
10'
HHz)
G'
I'
'G
10'
.
,
10'
RL(a)
Fig. 8 - Transient response
..
1
10'
!
~~
i! I
..
"II
10'
G- 4661
"s='±15V
-
"
I
..
I
,I 1\
, \
,
/
-
WK
II
L
_ .L
I
-+
"
f (Hz)
6
V.5,,:t15V
10
"I
II illill
..
!
Fig. 9 - Voltage follower
large-signal pulse response
.. -+t
'--I·
'00
I
I:
~
80
I: I
10'
'10
'00
"~.
I
Fig. 7 - Channel separation
'40
1Kn I I
,
I
I
t
10'
Rg=10Kfi,'
i
I
I
i
,
~
I
jl
12
~fw ~.
ee-
I
•
,
~.
160
r-....
10
LI'll
,.,'
I
=
L
I ill
e--r
~O:'5-7E1
"r"
}I-
.Vs=.!.lSV
24
Ililll
f(Hz)
0.25
0.5
360
0.75
1
t(,us}
10
- ----
30
APPLICATION INFORMATION
], :1;
'.
Fig. 10 - Mike/Line preamplifier for audio mixers (0 dB to 60 dB continuously variable gain)
lK.IL
i.
J
56
'."
150 Il.
KIl.
1.8 nF
OUT
l
5 - 5 2 73
Note -
The particular characteristics of the circuit of fig. 10 is that using a linear potentiometer, the gain is continuously variable in a logarithmic mode from 0 dB to 60 dB in the audio band.
Fig. 11 - Microphones nomograph
Very Low-Noise mike
Fig. 12
preamplifier (G v = 40 dB)
SOUND
PRESSURE LEVEL
dB
3.3 K 11
130
OUT
120
MICROPHONE
OUTPUT VOLT AGE
110
100
dB
NOISV FACTORY
IV
600
'00
200
100mv
lPascal(Pa) =lnewfon/m 2
90
SUBWAY
"-
TRAIN
5-PIECE ORCHESTRA
AT 10 FEET
eo
AVERAGE
NOl5Y
OFFICE
MICRO PHON E
SENSITIVITY
dB
(1 Vfpa) (lV/,ubar)
10 mv
40
-60
- 50
-70
- 60
-80
- 70
-90
- 80
-100
~
STREET
,
l,ubar=1dynE"/cm
70
60
'0
20
1m,
600
'00
200
"-
Rl
100 }Jv
60
NORMAL SPEECH
AT 3 FEET
60
'0
20
10 )-Iv
6
,
50
PRIVATE
OFFICE
1 ~,
'0
AVERAGE
RESIDENCE
Fig. 13 - Balanced input audio preamplifier
361
R2
f
APPLICATION INFORMATION (continued)
Fig. 15 - Frequency response
of the High-pass filter offig.14
Fig. 14 - 20 Hz to 200 Hz variable High-pass
filter (G v = 3 dB)
(dB),-,,---nTIl1l-,,---nmTT-ri--rrmn
O.15~F
INo--Jb-_-II-~-"-l
OUT
1.,1
5- 5274
·30
f-hf+ttHtf-+-It-t+t+tII-H++ft+1j
10
Fig. 16 - DC coupled low-pass
active filter (f = 1KHz, Gv = 6 dB)
30
100
300 I (Hz)
Fig. 17 - Switch able HP-LP audio filter
C1
1S0n
Fig. 18 - Subsonic or rumble filter (G v = 0 dB)
10KIl
C
Vin 0-11-<>-411-....-"-1
Vout
s- 5279
fc (Hz)
C (IlF)
15
22
30
55
100
0.68
0.47
0.33
0.22
0.1
Fig. 19 - High-cut filter (G v = 0 dB)
>'+--OVout
362
fc (KHz)
C1 (nF)
C2 (nF)
3
5
10
15
3.9
2.2
1.2
0.68
6.8
4.7
2.2
1.5
APPLICATION INFORMATION
(continued)
Fig. 20 - Fifth order 3.4 KHz low-pass Butterworth filter
,st order
For fc = 3.4 KHz and R; = R1 = R2 = R3 = R4 = 10 Kn, we obtain:
C1
1 •
= 1.354 • -R
1
21r fc
C1 = 0421 ._1_.
1
21r fc
.
R
C2
1 •
= 1.753 • -R
1
21r fc
6.33 nF
C3
= 0309 •
_1_. _ 1 _
R
21r fc
1.45 nF
1.97 nF
C4
= 3.325.
_1_. _1_
R
2,1r fc
15.14 nF
S.20 nF
The attenuation of the filter is 30 dB at 6.S KHz
and better than 60 dB at 15 KHz.
.
Fig. 21 - Six-pole 355 Hz low-pass filter (Chebychev type)
I
16o ;"F
2 20 rf
S -5218
This is a 6- pole Chebychev type with ± 0.25 dB ripple in the passband. A decoupling stage is used to
avoid the influence of the input impedance on the filter's characteristics. The attenuation is about 55 dB
at 710Hz and reaches SO dB at 1065 Hz. The in band attenuation is limited in practice to the ± 0.25 dB
ripple and does not exceed 0.5 dB at 0.9 fc.
363
LINEAR INTEGRATED CIRCUITS
PRELIMINARY DATA
DUAL OPERATIONAL AMPLIFIERS
• INTERNALLY COMPENSATED
• SHORT-CIRCUIT PROTECTED
• LOW POWER CONSUMPTION
• WIDE COMMON-MODE AND DIFFERENTIAL VOLTAGE RANGES
• NO LATCH-UP
The MC 1458 is a dual operational amplifier with frequency and phase compensation built into the chip,
available in 8-lead minidip package and in 8-lead micropackage. It is intended for a wide range of
applications where space and cost saving are the main goals. In spite of that, the MC 1458 offers good
performance and absence of latch-up makes the device ideal for use as voltage follower, integrator,
summing amplifier and general feedback applications.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage (*)
Differential input voltage
Power dissipation at T amb = 70°C
Minidip
Micropackage
Operating temperature
Storage temperature
± 18
± 15
±30
665
400
o to 70
-55 to 150
V
V
V
mW
mW
(*) For Vs lower than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
MECHANICAL DATA
6/82
Dimensions in mm
364
Ii:
I
!
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
OUTPUT
A
6
INY.INP.
A
Type
OUTPUT
Minidip
SO-8
B
NON INY.
INP. A
-lis
Ns
~
6
INY.INP.
B
5
NON INV.
INP. B
MC 1458
MC 1458 P1
MC 1458 M
MC 1458C
MC 1458 CP1
MC 1458 CM
5-3590
SCHEMATIC DIAGRAM (one section)
~_----_-- -,.._ _ _ _ _ _--._ _ _ _--._-o+Vs
08 :I---.-----J::09
NON
INVERTING
INPUT
01
02
R6
R9
INVERTING
INPUT
u----+---+---+----'
OUTPUT
R10
THERMAL DATA
Rth j-amb
Minidip
max·
Thermal resistance junction-ambient
* Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mm.).
365
120°C/W
SO-8
200* °C!W
ELECTRICAL CHARACTERISTICS
±
(Vs=
15V, T amb =
25°C, unless otherwise specified)
MC 1458C
MC 1458
Parameter
Unit
Test conditions
Min.
l
Is
Supply current
(both amplifiers)
Ib
Input bias current
Typ.
Input offset voltage
Rg'; 10 Kn
2
bVos
bT
Input offset voltage
drift
los
Input offset current
Ise
Rg =10Kn
O°C0 'f,.c;.
15K
~~
~v,,\.'·:.:..
10K
d; V
4
10
Rt=l-
--
--
---;:;
....-;:; ~
-
~RL
--RL
1---- -
-
f = 1 KHz
f./'"
~~
o
GSD150
G,
'5Dl03
Vo
Fig, 3 - Open loop voltage
gain vs. supply voltage
Fig, 2 - Quiescent drain current vs, supply voltage
I---R L
RL - SDK ;,
10~ II
12
14
-c-::
V~ (V)
10
.t
369
---
--
5K
12
14
II
i;
II~
I,
---
SK, C
3KCl_
I
~II
Fig. 4 - Open loop frequency
response using recommeded
compensation networks
l
Fig. 5 - Output voltage
swing vs. frequency for vari·
ous compensation networks
Fig. 6 - Input noise voltage
vs. frequency
e,
G.
~~~i~±ttlt~~
80 f:
Cd!3)
HI--
Vs=
+
15V
",.14,• •
Hr 15
r-.
10- 16
EEf~fE!limj5!~
10- 17
·20
U.J.ll...l.....ulL.LI.J..LLl....l..UL.LllU
100
1K
10K
lOOK
'0"8 L-L.LlL..L.LJ..lL-L-LllJ.-l.....J...LJ.L..J
f (HZ)
10
Fig. 7 - Input noise current
vs. frequency
Fig. 8 - Closed loop gain vs.
frequency
100
1K
10 K
Fig. 9 - Open loop voltage
gain vs. temperature
,"~~~~~~~~~~~.,i4~
(~:
I
_
Vs = ± 15V
VS -±15V
f = 1KHz
30K
...... j----.,: t---\.;: ,
Rt ~~
10K
a
10
Fig. 10 - TV remote control receiver
~
lK.n.
t..7nF 4.7nF
C1330RJ
lOOK
C2 330 .--!--!--.,,J,,........,I,.--,I,--*_~-::.-~--~----O Va
C8
:I: 4,'"F
~~_~=R=5~____~__________________D'Vs
lQOKfi
370
5-39~O
--
"-
R~ - 107D
APPLICATION INFORMATION
1
'"
f--
..........
20K
10. 26 L-L.LlL..L.LJ..lL-L-LllJ.-l.-l...LJ.L.J
10K
f (Hz)
10
100
1K
f (Hz)
(15~lB)
20
30
40
50
T {"CI
LINEAR INTEGRATED CIRCUIT
GENERAL PURPOSE TRANSISTOR ARRAY
The TBA 331 is an array of 5 monolithic NPN transistors in a 14-lead dual in-line plastic package. Two
transistors are internally connected to form a differential amplifier.
The transistors of the TBA 331 are well suited to low noise general purpose and to a wide variety of
applications in low power systems in the DC through VHF range. They may be used as discrete components in conventional circuits; in addition, they provide the very significant inherent integrated circuit
advantages of close electrical and thermal matching.
Ic
P tot
T stg' T j
Top
Collector-base voltage (I E = 0)
Collector-emitter voltage (I B = 0)
Collector-substrate voltage
Emitter-base voltage (lc = 0)
Collector current
Total power dissipation at Tomb ~ 55°C
Storage and junction temperature
Operating temperature
Each
transistor
20
15
20
5
50
300
-40 to
o to
Total
package
V
V
V
V
mA
750 mW
150
°C
85
°C
* The collector of each transistor of the TBA 331 is isolated from the substrate by an integrated diode.
The substrate (pin 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
ORDERING NUMBER:
TBA 331
Dimensions in mm
MECHANICAL DATA
2.5: . ;j
~~
D~.s.
I
I
j
ABSOLUTE MAXIMUM RATINGS
V CBO
. V CEO
V css *
V EBO
j
15.24
I
371
6/82
i
!
SCHEMATIC DIAGRAM
2
5
8
4
3
7
6
11
9
10
14
12
13
substrate
5-3763
THERMAL DATA
Rth j-amb
Total
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS
I CEO
126°C/W
(T amb = 25°C unless otherwise specified)
Parameter
ICBO
max
Test conditions
Co lIector cutoff
current (I E = 0)
V CB
=
10 V
Collector cutoff
current (lB = 0)
VCE
=
10 V
Min.
Typ.
Max.
Unit
Fig.
0.002
40
nA
1
see
0.5
/.LA
2
2
/.LA
7
curve
IIB1-1B21
Input offset
current
Ic
VCE
=
=
1 mA
3 V
372
0.3
i;!
'II
11
i~
~
ELECTRICAL CHARACTERISTICS
(continued)
Test conditions
Parameter
VCSO
V CEO
Vcss
VCE (sat)
Collector-base
voltage (I E ~ 0)
Ic
~
Collector-emitter
voltage (Is ~ 0)
Ic
~
collector-substrate
voltage (I css ~ 0)
Ic
~
Is
Ic
~
IE
~
IE
VCE
IE
VCE
~
Ic
VCE
~
Ic
VCE
~
Ic
VCE
~
Ic
VCE
~
Base-em itter
voltage
temperature
coefficient
Ic
VCE
~
I nput offset
voltage
temperature
coefficient
Ic
VCE
~
Emitter-base
voltage (I C ~ 0)
Base-emitter
voltage
VSE
I V SEr V sE21
IVSE3- V SE41
IV SE4- V SE51
Input offset
voltage
I nput offset
voltage
I nput offset
voltage
IV SE5- V SE4 1 I nput offset
voltage
L1V SE
LIT
IVSErVSE21
LIT
Typ.
Unit
Fig.
10"A
20
60
V
-
1 mA
15
24
V
-
10"A
20
60
V
-
0.23
V
-
7
V
-
0.715
V
4
0.8
V
4
Max.
Collector-emitter
saturation voltage
V EBO
Min.
~
~
~
~
~
~
~
~
~
~
1 mA
10mA
10 "A
1 mA
3V
10 mA
3V
5
1 mA
3V
0.4?
5
mV
4-6
1 mA
3V
0.45
5
mV
4-6
1 mA
3V
0.45
5
mV
4-6
1 mA
3V
0.45
5
mV
4-6
1,
1 mA
3V
-1.9
mV/oC
5
1 mA
3V
1.1
"V/oC
6
373
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
hFE
fT
NF
Hie
hfe
.,
hre
hoe
Yie
yfe
Yre
DC current gain
Transition
frequency
Noise figure
I nput impedance
Forward current
transfer ratio
Reverse voltage
transfer ratio
Output
admittance
Input
admittance
Forward
transadmittance
Reverse
transadmittance
Ie
VeE
Ie
veE
Ie
V eE
= lOrnA
= 3V
1 mA
= 3V
10JJA
= 3V
Min.
Typ.
Max.
Unit.
Fig.
100
-
3
100
-
3
54
-
3
550
MHz
14
3.25
dB
8
Ie = 1 rnA
VeE = 3V
= 1 kHz
f
3.5
k!1
9
Ie = 1 rnA
V eE = 3V
= 1 kHz
f
110
-
9
Ie = lmA
V eE = 3V
= 1 kHz
f
1.8xl0"
-
9
Ie = 1 rnA
VeE = 3V
= 1 kHz
f
15.6
JJS
9
Ie = 1 rnA
V eE = 3V
= 1 MHz
f
o.3+jQ.04
mS
11
Ie = 1 rnA
VCE= 3V
= 1 MHz
f
I I
31-jl.5
mS
10
Ie = 1 rnA
veE = 3V
= 1 MHz
f
see curve
mS
13
Ie = 3mA
V eE = 3V
Ie
V eE
f
Rg
=
=
=
=
40
300
100JJA
3V
1 KHz
1 k!1
374
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
Output
admittance
y""
C EBO
Collector-base
capacitance
CCBO
Collector-sustrate
capacitance
Cess
Fig. 1 - Collector cutoff
current vs ambient temperature
'CEO
(nA)
10
~~~~~~~~~~~'I-'~"~'"
Unit.
Fig.
0.001+jO.03
mS
12
Max.
f
=
=
=
1mA
3V
1 MHz
Ic
V EB
=
=
0
3V
0.6
pF
-
IE
VCB
=
=
0
3V
0.58
pF
-
Ic =
Vcss=
0
3V
2.8
pF
-
IC
V CE
Emitter-base
capacitance
Typ.
Min.
Fig. 2 - DC current gain vs.
emitter current.
,-
Fig. 3 - Input voltage and
input offset voltage vs. emitter current
, .,
E
V.
120
=3V
(mV)
1.1
h
0.7
100
IhFEl
H"FE21
hFE2
~E.l
80
0.6
A.'
o.a
60
os
ilVSE
0.'
·20
20
100
60
80
10. 2
10- 1
100 Tamtrcl
Fig. 4 - Input characteristic
for each transistor
'BE
I ,,10m
froY)
1'·,",,1'
(PA):
as
IE (mAl
Fig. 6 - Input offset current
for matched transistor pair
Fig. 5 - Input offset voltage
vs. ambient temperature
G-046113
10·'
~~~~IE~~~~~~'~'~"I'"
f-~ _
f-f---H-++tHtt-..L ..l.
+
• -
.
VCEdV
.7
VE"'W
"mA
.5
0'
lmA
oeo
Ie'" 3mA
lmA
o.lmA
10-"~_
020
-60
-30
30
60
90
Tamb("'C)
·tlO
-20
0
20
375
OJ
100
TafT'bl"C1
Ie (mA)
Fig. 7 - Noise figure vs collector current
N'
(dB)
IYJ
veE ~ 3V
= 1kfl.
I--R
1= 0.1 kHz
--'T
~-~
'+'-
"
Fig.9 - Input admittance
Fig.8 - Forward admittance
-o'''n
~:i,
II
"
~-
20
f-
gie
~~~~-
(mS1
gf,
_>en
0
~"~
0,+
b"
'CE
1 _
r--t
r-
VeE ·3V
IC
~
lmA
'111-:+
g,
I,
,
+-T
°~
"
-20
10kHz
-4O
10·'
10-'
10-
Ie (rnA)
10
Fig. 11 - Reverse admittance
Fig. 10 - Output admittance
bee
gee
(mS)
,-,-rn-rrnr7-rrrrTTTrr--rrrTiTiTI
f-+++t+tfH--++HtHtt--H-ttttffi
f-+++t+tfH--++HtHtt--H-ttttffi
go.
10'
f (MHz)
376
>0'
"
10'
I (MHz)
Fig. 12 - Transition frequency
LINEAR INTEGRATED CIRCUIT
j:
5W AUDIO AMPLIFIER
i
The TBA 800 is a monolithic integrated power amplifier in a 12-lead quad in-line plastic package. The
external cooling tabs enable 2.5W output power to be achieved without external heatsink and 5W
output power using a small area of the P.C. board copper as a heatsink.
It is intended for use as a low frequency Class B amplifier.
r:
I
I
I
ABSOLUTE MAXIMUM RATINGS
Vs
10
10
Ptot
T stg , Tj
30
2
1.5
1
5
-40 to 150
Supply voltage
Peak output current (non repetitive)
Peak output current (repetitive)
Power dissipation at Tamb = 80°C
at T tab = 90°C
Storage and junction temperature
V
A
A
W
W
°C
ORDERING NUMBER: TBA 800
Dimensions in mm
MECHANICAL DATA
I
l.!.i,
,·
I'j
iM
I
:i
i,~
~
377
6/82
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
SUPPLY VOLTAGE
12
N C
11
OUTPUT
N C
SUPPLY VOLTAGE
10
GROUND
GROUND
GROUND
GROuND
BOOTSTRAP
(SUBSTRATE)
COMPENSATION
8
INPUT
FEEDBACK
7
RIPPLE REJECTION
5-0329
Substrate
TEST CIRCUIT
+Vs=24V
C9
01
.~
C6
'Tr _T 100~F
25V
C8
100,uF
Vi
15V
R2
100kQ
C2
500I'F
15 V
C1
100!,F
6V
Rj
560.
*
C3, C7 see fig. 5.
378
THERMAL DATA
Rth J-tab
Rth j-amb
Thermal resistance junction-tab
Thermal resistance junction-ambient
max
max
12
70*
°C/W
°C/W
- Obtained with tabs soldered to printed circuit with minimized copper area.
ELECTRICAL CHARACTERISTICS(Refer to the test circuit, T amb = 25°C, Vs= 24V, RL = 16n,
unJess otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
11
12
13
V
Vo
Quiescent output voltage
(pin 12)
Id
Quiescent drain current
9
20
mA
Ib
Input bias current (pin 8)
1
5
!J.A
Po
Output power
Vi(rms)
Input saturation voltage
V·I
I nput sensitivity
Po: 5W
Ri
Input resistance (pin 8)
f : 1 KHz
B
Frequency response (-3 dB)
C3: 330 pF
d
Distortion
d: 10%
f : 1 kHz
f : 1 kHz
W
mV
80
mV
5
MD
40 to 20,000
Hz
Po: 50 mW to 2.5W
f : 1 kHz
0.5
%
80
dB
Voltage gain (open loop)
f : 1 kHz
Gv
Voltage gain (closed loop)
f : 1 kHz
eN
Input noise voltage
39
B : 22 Hz to 22 KHz
-
iN
I nput noise current
1)
Efficiency
Po: 5W
SVR
Supply voltage rejection
f ripple: 100 Hz
C5 : 25!J.F
C5:100!J. F
Drain current
5
220
Gv
Id
4.4
f = 1 kHz
Po: 5W
• See fig. 6.
379
42
45
dB
5
!J. V
0.2
nA
75
%
35
38
dB
dB
280
mA
Fig. 2 - Maximum power
dissipation vs. supply voltage
Fig. 1 - Output power vs.
supply voltage
r
Fig. 3 - DislOrtion vs. output power
60805/1
I~i:
Ptot
_._-
- 1--- --
(W)
-
-
,
Rl=8Q
/
f-++-+++
V
i
1++++- +
~
10
20
~~
~
Fig. 4 - Distortion vs. frequency
1•·
20
~t
+
I
R -lGn
111\lL-_
1=
, ~ :' I I I
f-
---i
tVs!:Lv
"""I
I:I~"
I
I
tll I",,", 1 't'll
,/
-. -11
t5
10
Vs (V)
I
A",o16U
/v
rrrn ' ij If!i III j
I
r-- -=
I
V
d
('/,)
t·
T
I
r
LL._.~L
'
1!
I
-
I
,
I
t
Ij
V: '
'
, f
' '
'..L'
4
25 Vs (V)
-
I'
f"o(W)
Fig. 6 - Voltage gain (closed
loop) and input voltage vs.
Fig. 5 - Value of C3 vs. Rf
for various values of B
Rf
d
C3,
(%)
111111
so24V,,-=lsn
",=5SU
(pF)e
7"'5xC
,-
-5kHz
Po =50mW
e--
/ ' 10kHz
t-
10',
r--
2
r-'
, ==--
o=2.5W
I
1\
--_..- ./
to'
10
to'
to'
to'
20kHz
f (Hz)
10
Fig. 7 - Power dissipation
and efficiency vs. output
power
-I
,
6
8
I
II
1;
~t(O)
102
50
100
Rt (n)
Fig. 9 - Supply voltage
rejection vs. Rf •
Fig. 8 - Quiescent output
voltage (pin 12) vs. supply
voltage
G-0633Jl
Ptot
(W)
P,
'1
Va
('/,)
(V)
70
SO
1.5
101-+++-1-++H-+-if-H-+-H
50
1/
-10
H-++-H-+-+-I-+--+--+-1I-+-H
-20
f-f--.
40
Vs=24V
30
RL=16n
f -lkH
10
4
fb
(W)
-+-~
to
-so
20
380
~~-I-++I-++I-++H
: : Rf!t:f:h~'5"'1~OlF~i~5.~5"tt~
20
0.5
.-1-1-+++-1-+++-11-+++-1
50
100
APPLICATION INFORMATION
Fig. 10 -- Circuit with the load connected to the supply voltage
5-0102/3
* C3, C7 see fig. 5.
Compared with the other circuits, this configuration entails a lower number of external components
and can be used at low supply voltages.
Fig. 11 - Circu it with load connected to ground without bootstrap.
~:t500~F
~i1
'5V
1
*C3, C7 see fig. 5.
This circuit is only for use at high voltages. The pin 3 is left open circuit, this automatically inserts
diodes 02-03 (see schematic diagram) and this enables a symmetrical wave to be obtained at the output.
381
LINEAR INTEGRATED CIRCUIT
FULLY-PROTECTED 7W AUDIO AMPLIFIER FOR CB RADIO
•
•
•
•
•
•
HIGH OUTPUT POWER (7W AT 16V/4n; 14.4V/2n)
HIGH OUTPUT CURRENT (3A REPETITIVE)
LOAD DUMP PROTECTION UP TO 40V
LOAD SHORT CIRCUIT PROTECTION UP TO Vs = 15V
POLARITY INVERSION PROTECTION
THERMAL PROTECTION
The TBA 810CB is a monolithic integrated circuit in a 12-lead quad in-line plastic package, expressly
designed for use as a power audio amplifier in CB radios.
The TBA 810 ACB has the same electrical characteristics as the TBA 81 OCB but its cooling tabs are flat
and pierced so that an external heatsink can be easily attached.
ABSOLUTE MAXIMUM RATINGS
Peak supply voltage (50 ms)
DC supply voltage
Operating supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Power dissipation at Tamb
80°C (for TBA 810CB)
T tab .;; 100°C (for TBA 810ACB)
Storage and junction temperature
V s(peak)
Vs
Vs
10
10
Ptot
40
28
20
4
3
1
5
<
-40 to 150
V
V
V
A
A
W
W
°C
ORDERING NUMBER: TBA 810CB
TBA 810ACB
MECHANICAL DATA
Dimensions in mm
.~.'95""'
.
.
"
,
,
T13A 810CB
6/82
TBA 810AC13
382
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
'3UPPLY
VOLTAGE
12
N.
C.
OUTPUT
N, C
N.C.
10
6
0----
GROUND
,
GROUND
GRCUND
(}-------
GROUND
BOOTSTRAP
(SUBSTRATE)
COMPENSATION
INPUT
RIPPLE
REJECTION
FEEDBACK
5-0289
TEST AND APPLICATION CIRCUIT
R3
loon
CB
v,
100~F
15V
Y''--<>---+--------,
R2
I
IOOkO
~2
T:~eO"F
I
WR,
5-220311
*C3,C7 SEE FIG.6
THERMAL DATA
Rth' j-tab
Rth j-amb
TBA 810CB
Thermal resistance junction-tab
Thermal resistance junction-ambient
max
max
• Obtained with tabs soldered to printed circuit with minimized copper area,
383
TBA 810ACB
12°C/W
10°C/W
70* °C/W
80°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit;
Vs = 14.4V,
T amb = 25°C unless
otherwise specified)
Test conditions
Parameter
Min.
Typ.
Max.
Unit
20
V
7.2
8
V
20
mA
Vs
Supply voltage (pin 1)
Vo
Quiescent output voltage
(pin 12)
Id
Quiescent drain current
12
Ib
Input bias current (pin 8)
0.4
f.lA
Po
Output power
6
7
W
W
Vi(rms)
I nput saturation voltage
Vi
I nput sensitivity
/
4
6.4
d ~ 10%
RL ~ 4.11
RL ~ 2.11
f
~
1 kHz
5.5
5.5
f ~ 1 kHz
Po ~6W
R f ~ 56.11
R f ~ 22.11
Po~ 7W
R f ~ 56.11
R f ~ 22.11
RL
RL
Ri
Input resistance (pin 8)
B
Frequency response
(-3 dB)
RL ~ 4.11/2.11
C 3 ~ 820pF
C 3 ~ 1500 pF
Distortion
P0 ~ 50 mW to 2.5W
RL ~ 4.11/2.11
f ~ 1 kHz
d
Gv
Voltage gain (open loop)
RL
Gv
Voltage gain (closed loop)
RL ~ 4.11/2.11
eN.
I nput noise voltage
iN
Input noise current
1]
Efficiency
Supply voltage rejection
~
4.11
~
~
4.11
B (-3 dB)
~
f
~
1 kHz
f
~
1 kHz
34
40 to 15000 Hz
Po~
~
RL
RL
6W
1 kHz
~
4.11
mV
mV
55
20
mV
mV
5
Mn
40 to 20 000
40 to 10000
Hz
Hz
0.3
%
80
dB
37
40
dB
2
f.lV
80
pA
75
%
48
dB
4.11
V ripple~ 1 V rms
friPPle~ 100 Hz
384
~
75
30
2.11
Vs~16V
f
SVR
mV
220
40
I,
Fig. 1 - Output power vs.
supply voltage
I","
Fig. 3 - Distortion vs. frequency (R L = 417.)
Fig. 2 - Maximum power
dissipation vs. supply voltage
(sine wave operation)
P,
d
(wi
(0/.)
!i
11
j",
i,;
16
Vs(v)
16
Fig. 4 - Distortion vs. frequency (R L = 217.)
Vs(V)
Fig. 5 - Distortion vs. output
power
d
d
(.10)
(°1.)
Fig. 6 - Value of C3 vs. feed·
back resistance for various
values of B
, '
,il
10'
10
10-'
10'
Fig. 7 - Relative voltage gain
(closed loop) and input voltage vs. feedback resistance
Po(W)
I
w'
Fig. 8 - Relative voltage gain
(closed loop) and input voltage vs. feedback resistance
Fig. 9 - Power dissipation
and efficiency vs. output
power
Ptot
'l.
(W)
(°1.)
80
60
20
80
100
120
RI (0)
20
<.0
60
80
385
100
Rf (n)
Fig. 10 - Quiescent output
voltage (pin 12) vs. supply
voltage
Fig. 11 - Quiescent drain
current vs. supply voltage
Fig. 12 - Supply voltage
rejection vs. feedback resistance
(~~ ~~-.-.~~-~~~~
(dB)
8
~"
I.
:;
I-L~~:~~+:
, r +t
t
;
;:
20
i
- t
2
~lf
h-
~i
1- ++-
vJ"Lllt-f
RL"4.n
_ C5=,100,uF
tr f",",f'f-"r'--
I
t-J ,
40
50
60
16
~m
~LI
tl ..
j i
i i
·lil-
ffi{ +1..:
,
f
Vs(V)
100
BUI LT -IN PROTECTION SYSTEMS
Load dump protection
The load dump case occurs in a car when the engine is running and the battery is disconnected: voltage
spikes on the power line are supplied by the alternator since there is no clamping effect due to battery
capacitance.
The TBA 810CB was designed to withstand a pulse train on pin 1, of the type shown in Fig. 13. Providing
an LC filter is included, as shown in Fig. 14, a much higher pulse train amplitude (up to 100 V peak ) is
allowed on the supply line with no damage to the device.
Fig.13
Fig.14
From
L=2mH
Topin1of
supply ~TBA8'OCB
line
~O~q,uF
'6V
I
5-2207
5-2206
Short-circu it protection
The TBA 810CB can withstand a permanent short circuit across the load for a supply voltage up to 15V.
Polarity inversion protection
High current (up to 5A) can be handled by the device with no damage for a longer period than the
blow-out time of a quick lA fuse (normally connected in series with the supply).
This feature is added to avoid destruction if, during fitting to the car, a mistake on the connection of the
supply is made.
386
BUI LT -IN PROTECTION SYSTEMS(continued)
Open ground protection
When the radio is in the ON condition and the ground is accidentally opened, a standard audio amplifier
will be damaged. On the TBA 810CB, protection diodes are included to avoid any damage.
I nductive load protection
A protection diode is provided between pin 12 and pin 1 (see the internal schematic diagram) to allow
use of the TBA 810CB with inductive loads.
In particu lar, the TBA 81 OCB can drive the coupl ing transformer for aud io modulation in CB transmitters.
DC voltage protection
The maximum operating DC voltage on the TBA 810CB is 20V.
However the device can withstand a DC voltage up to 28V with no damage. This could occur during
winter if two batteries were series connected to crank
This means that a variation in current absorbed by the motor, due to a variation in torque applied,causes
a proportional variation in regulator output voltage. In fig. 6 is shown the minimum allowable Eo vs. RT .
The TCA 900 and TCA 910 give a reference constant voltage V,ef (between pins 2 and 3) independent
of variations of V5' 12 and ambient temperature.
They also give:
13 = Id3 + 12/k
13 = total current at pin 3
Id3 = quiescent current at pin 3 (12 = 0)
12 = current at pin 2
k
constant
The output voltage V m, applied to the motor has the following value:
Where:
V m = V,ef +R T [ V,ef (1 +.!...) + Id3 ]
R5
k
+~
k
RT
-------
Term 2
Term 1
Term 1 equals Eo and fixes the motor speed by means of the variable resistor R5 ;
-If-.
Term 2
RT equals the term Rm. 1m and, therefore, compensates variations of torque applied.
Complete compensation is achieved when:
RT = k Rm
If RT max > k Rm min instability may occur.
412
LINEAR INTEGRATED CIRCUIT
lOW AUDIO POWER AMPLIFIER
The TCA 940N is a monolithic integrated circuit in a 12-lead quad in-line plastic package, intended for
use as a low frequency class B amplifier. The TCA 940N provides lOW output power@ 20V/4n, 7W@
16V /4n and 6.5W @ 20V /8n. It gives high output current (up to 3A), very low harmonic and cross-over
distortion. Besides the thermal shut-down, the device contains a current limiting circuit which restricts
the operation within the safe operating area of the power transistors. The TCA 940N is pin to pin
equivalent to the TBA 810 AS.
I
j"
ABSOLUTE MAXIMUM RATINGS
v
5
10
10
P tot
T stg , T j
Supply voltage
Output peak current (non-repetitive)
Output peak current (repetitive)
Power dissipation: at T amb = 50D C
at T tab = 70D C
Storage and junction temperature
28
3.5
V
A
3
A
W
W
1.25
8
-40 to 150
DC
ORDERING NUMBER: TCA 940N
MECHANICAL DATA
Dimensions in mm
I!
II
,
.,
:~
I:I,·
"
i
\i
I,:
I~
Ii:~
:j
1<
,.
I~
[!
413
6/82
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
t"'"
I
SUPPLY
VOLTAGE
I
I
12
())
OUTPUT
N.C.
N. C.
N C.
GROUND
GROUND
CB) I
BOOTSTRAP
[ifli
GROUND
(SUBSTRATE)
COMPENSATION
INPUT
FEEDBACK
RIPPLE
REJECTION
J
lt
[
GI
®
5-0289
TEST AND APPLICATION CIRCUIT
V
C9
O.lfJF
R3
C6
lOon
IOO}JF
CB
lOOfJF
R2
100kO
*=C3 ,C7 SEE FIG. 7
414
THERMAL DATA
Rth J-tab
Rth J-amb
max
max
Thermal resistance junction-tab
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS
Parameter
10
80
°CIW
°CIW
(Refer to the test circuit, T amb = 25°C)
Test conditions
Min.
-
Typ.
Max.
Unit
28
V
9.8
V
Vs
Supply voltage (pin 1)
Vo
Quiescent output voltage (pin 12)
Vs=18V
Id
Quiescent drain current
Vs=12V
Vs = 24V
13
20
mA
rnA
Ib
I nput bias current (pin 8)
Vs=18V
0.5
/JA
Po
Output power
d= 10%
Vs = 20V
Vs=18V
Vs=16V
Vs = 20V
Vs=18V
10
9
7
6.5
5
W
W
W
W
W
6
8.2
f = 1 kHz
R L =40
R L =40
R L =40
R L =80
R L =80
Vl(rms) Voltage for input saturation
Vi
Input sensitivity
Vs=18V
f = 1 kHz
90
RL=40
40 Hz to 20 KHz
Vs=18V
C3 = 1000 pF
d
Distortion
Po = 50 mW to 5W
R L =40
Vs=18V
f = 1 kHz
Gy
Voltage gain (open loop)
Gv
Voltage gain (closed loop)
mV
Po =9W
R L =40
Frequency response (-3 dB)
Input resistance (pin 8)
7
250
B
Ri
9
Vs=18V
f = 1 kHz
R L =40
Vs=18V
f = 1 kHz
R L =40
Rg=O
eN
I nput noise voltage
Vs=18V
iN
Input noise current
Vs=18V
415
34
mV
0.3
%
5
MO
75
dB
37
40
dB
3
/JV
0.15
nA
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
1)
Efficiency
Po
~
Min.
Typ.
Max.
Unit
Vs~18V
9W
RL~4n
1 ~ 1 kHz
SVR
Id
Tsd
Supply voltage rejection
Drain current
Vs ~ 24V
f ripple ~ 100 Hz
RL~4n
Po ~ 9W
RL ~ 4n
Vs~18V
Ptot
Thermal shut-..down (.)
Case temperature
~
4.8W
65
%
45
dB
770
mA
110
°C
(.) Seelig. 15.
Fig. 1 - Output power vs.
supply voltage.
Fig. 2 - Maximum power
dissipation vs. supply volt·
age (sine wave operation)
~otrT-T'-rT-''-''-''-''~'T-'~'''c,''
(w)
H++-H++ +c:+--ri--+-+-t--+-I
f--t--+--H--+-+--t-'I= \~Hi'--t++-H+-i
-I-+-I,---t-,;f---t--+~\-I/I'¥I----j
L=lIn
416
Fig. 3 - Distortion vs. output
power.
Fig. 4 - Voltage gain and
input sensitivity vs. feed·
back resistance (R f )
Fig. 5 - Distortion vs. frequency (R L = 4n)
Fig. 6 - Distortion vs. frequency (R L = 8n)
Fig. 7 - Value of C3 vs. R f
for different bandwidths
Fig. 8
Supply voltage
rejection vs. feedback resi stance (R tl~~.-,-,-"'-T'ro
Fig. 9 - Power dissipation
and efficiency vs. output
power (R L = 4n)
C3~~~C-"TT~--~~-rI7TrD
(PF)3
-
• • • • "...
~:)
--+"
r--:-- 1
-'0
-20
Vs~24 V
RL= 40
-30
C5:100 .... f
f"PIM=100H z .
-40
-so
-60
100
"
°
Fig. 10 - Power dissipation
and efficiency vs. output
power (R L = 8n)
Fig. 11 - Qu iescent output
voltage (pin 12) vs. supply
voltage
p\:;, EEEEEEEfa=HS=-t~Ft4EfIr=,.+
~F<~~~:l-(~"
t++-EEi§i§!§'E~'
i:+'+' '
->,t--
-1-- .....
8
Fig. 12 - Quiescent current
vs. supply voltage
" rr-,--n--'--'-T1,-",-",-n--::n
("
60
fI!.--:':
, 'f-t-+--t-
I
l'tot
1-+
+-~--.::..-t=
40
".18'-+-t--l-:::-=sn
; _
Rl ..
~_~_ ~
>-_~
-+tJ- ~1~~ :: ~-~
5
20
!
~d(oulput 'tran~is~or~):
_
+)' "
20
"
417
""s(vl
Po(W)
"~1
:
SHORT CIRCUIT PROTECTION
The most important innovation in the TCA 940N is an original circuit which limits the current of the
output transistors. Fig. 13 shows that the maximum output current is a function of the colle~tor-emitter
voltage; hence the circuit works within the safe operating area of the output power transistors. This can
therefore be considered as being power limiting rather than simple current limiting. The TCA 940N is
thus protected against temporary overloads or short circuit by the above circuit. Should the short circuit
exists for a longer time, the thermal shut-down comes into action and keeps the. junction temperature
within safe limits.
.
Fig. 14 - Test circuit for the limiting characteristiCs
Fig. 13 - Maximum output
current vs. voltage (V CE)
across each output transistor
,A, rrr-r"",-,-,-rrr---,,':-":':':::'
lOMAX
n9J
..JW
f;50Hz
THERMAL SHUT-DOWN
Fig. 15 - Output Aower and
drain current vs. case tem·
The presence of a thermal limiting circuit offers the following
advantages:
1) an overload on the output (even if it is permanent), or an
above-limit ambient temperature can be easily supported.
2) the heatsink can have a smaller factor of safety compared
with that of a conventional circuit. There is no device
damage in the case of too high a junction temperature: all
that happens is that Po (and therefore P tot) and Idare
reduced (fig. 15).
10
++-t-t-+-t +-t ++++-it-H 0.2
418
MOUNTING INSTRUCTION
The power dissipated in the circuit may be removed by connecting the tabs to an external heatsink according to fig. 16. The desired thermal resistance may be obtained by fixing the TCA 940N to a suitably
dimensioned plate as shown in fig. 17. This plate can also act as a support for the whole printed circuit
board; the mechanical stresses do not damage the integrated circuit. During soldering the tabs temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds.
Fig. 16 - Maximum allowable power dissipation vs.
ambient temperature
Fig. 17 - Mounting example
ALUMINIUM
3.5rrm THICKNESS
Fig. 18 - P.C. board and components layout of the test and application circuit (1:1 Scale).
CS-003311
419
LINEAR INTEGRATED CIRCUIT
FM-I F RADIO SYSTEM
•
•
•
•
•
•
HIGH LIMITING SENSITIVITY
HIGH AMR
HIGH RECOVERED AUDIO
GOOD CAPTURE RATIO
LOW DISTORTION
MUTING CAPABILITY
The TCA 3089 is a monolithic integrated circuit in a 16-lead dual in-line plastic package. It provides a
complete subsystem for amplification of FM signals.
The functions incorporated are:
FM amplification and detection
Interchannel controlled muting
- AFC and delayed AGC for FM tuner
- Switching of stereo decoder
- Driver of a field strength meter
The TCA 3089 can be used for FM-IF amplifier application in Hi-Fi, car-radios and communication
receivers.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current (from pin 15)
Total power dissipation at T amb
Storage temperature
Operating temperature
16
V
mA
800
mW
-55 to 150°C
-25 to 70°C
2
';;
70°C
ORDERING NUMBER: TCA 3089
Dimensions in mm
MECHANICAL DATA
6182
420
CONNECTION DIAGRAM
J:I
(top view)
"
IF INPUT
N.C.
BYPASS
AGC OUTPUT
BYPASS
GROUND
FIEL D STRENGTH
METER
GROUND
MUTE INPUT
MUTE OUTPUT
AUDIO OUTPUT
SUPPLY VOLTAGE
AFC OUTPUT
REF.
QUAQ OUTPUT
QUAD. INPUT
5-0398/1
BLOCK DIAGRAM
TO Ir-.. H R'.AL
f-lE"C,ULA 7CH',
o
IF
INPUT
i~~~~f·~
:~
I
2
DELAYED
AGe FOR
RF AMPL
421
BIAS
!i
:i!:
± 40 KHz
5.6
V
430
TEST CIRCUITS
Single tuned detector coil
Double tuned detector coil
r-"";oo~;1
!
VS,;ll';
1tL~~~-t---::---~,----!;;---';-.., :~~O
001,uF
II •
~
I
6
~AUDIO
C'.;i. ~*
0
51
OCl2.t-
OUTPUT
)1
AUDIO
TeA 3189
..:..
I"F-OO~
"1"','
OUTPUT
1
"'
J..
W
II •
,L~~::
PIN 13
1
Fig.1 - P.C. board and component layout of the single tuned circuit (1:1 scale)
10.7MHz
INPUT
431
Fig. 2 - Limiting and noise
characteristics
(kHz)r--,-r-rrTTlTr-..,..,.,iTi'i'n
(dB) _ _
r---'~'/l"3-'-[-~"Alffll;'~~ITT~l1jlt-1
o f==
-10
Fig. 4 - Recovered audio
and muting action vs. input
level
Fig. 3 - Deviation mute
threshold vs. R 7-10
I
_20~~'~~"~~:~~~~1
-~
M~1~k~
dB =500mV
-40
-1Om_
-50 ----
lis ~ '2'1
AUDI
f---f-H+++++t~m: ~~~~HZ
"0 f---,"\rl-+++f++f---jl-H-+i-H--H
"0 f---HH-+++++t--+-++m+H
'00 1--t---i\\-H-ttI-tt--t-H-++-1tH
-20
f--+-II-f-+-+-17",-::.",,,",,-'--t-1
f--+-+_.f-+-+-1 ~~ ~o;~~~z
llh ±75KHz
OdB=500mX
8°f---f-~.r++++t--4--++m+H
~~,
-60
0 TPUT
(
-60
1--+-t+/-+-+-I--+--~+--+--1
-80
-90
10
10'
10'
10
Fig. 5 - AFC characteristics
)
"
'IS" 12 V
t .. 10.7MH:/:
f,,'0.7MHz
1/
/
"00
'50
-50
-15 0
'Isz12V
/
0
-10
Fig. 7 - Field strength and
tuning meter output vs.
input level
"3
)
.200
'"
10'
10
Fig.6 - AGC voltage for FM
tuner vs. input level
1
'.A
R7-lO{kn)
V
V
V"
V
V
Vs= 12V
j
f" IO.7MHz
"
, I-~
"
V
V
/
/
-\00
-50
50
100 l!f(KHz)
10
10'
FEATURES
I
!
I
I
Low Limiting Sensitivity (25 p.V max.)
Low Distortion « 1%)
Single-coil Tuning Capability
Programmable Audio Level
SIN Mute
Deviation Mute
AFC and delayed AGC
Programmable AGC Threshold and Voltage
Typical S + NIN > 70 dB
Typical S + NIN > 60 dB
Meter Drive Voltage Depressed at Very-Low Signal Levels
On-Channel Step Control Voltage
432
10
TCA 3189
TCA 3089
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
No
Yes
No
No
LINEAR INTEGRATED CIRCUIT
TV VISION I F SYSTEM
The TDA 440S is a monolithic integrated circuit in a 16-lead dual in-line plastic package. The functions
incorporated are:
- Gain controlled vision I F amplifier
- Synchronous detector
- AGC detector with gating facility
- AGC amplifier for PNP tuner drive with variable delay
- Video preamplifier with positive and negative outputs.
It is intended for use in black and white and colour TV receivers.
ABSOLUTE MAXIMUM RATINGS
Vs
V5
Supply voltage (pin 13)
Voltage at pin 5
VlO
Voltage at pin 10
V ll
Voltage at pin 11 (with load connected to V s)
Output current
Total power dissipation at Tamb .;; 70°C
Storage temperature
Operating temperature
Ill,112
Ptot
T stg
Top
ORDERING NUMBER:
15
15
-1
3
8
f
1
5
V
V
V
V
V
mA
800
mW
-55 to 150°C
o to 7 0 ° C
TDA 440S
Dimensions in mm
MECHANICAL DATA
433
6/82
_ _ _1_ _ _ _ _
_
CONNECTION DIAGRAM (top view)
[ 1
16
INPUT
OECOUPLING
[ 2
15
BIAS
DECOUPLING
GROUND
[ 3
14
INPUT
BIAS
AGe TIME
CONSTANT
TUNERAGC
OUTPU T
N,C.
su PPL Y
13
[ 4
l5
VOLTAGE
12
POSIT IvE
V I OEO
OUTPUT
11
NEGATIVE
VIDEO
10
VOLTAGE
TUNER AGe
DELAY
OUTPUT
FLYBACK
PULSE INPUT
OUTPUT
REGULATION
CARRIER
TUNING
CARRIER
TUNING
'-, (19-8' 1
BLOCK DIAGRAM
~
+-11-··1
~
',,8}
C3
+
1.9"'
'3
I
1
434
V'S
.~.
•
THERMAL DATA
Rthi·amb
max
Thermal resistance junction-ambient
100
°C/W
~,
ELECTRICAL CHARACTERISTICS (Refer to fig. 1 test circuit, T amb = 25°C)
Parameter
Test conditions
DC CHARACTERISTICS
Vs
Supply voltage range
(pin 13)
Is
Supply current (pin 13)
Vs=12V
-Ill (1)
Output current
Vs=15V
V l l = 8V
V ll
Output voltage
Vs=12V
Rs =
(2)
10
12
15
V
50
rnA
la
1.6
rnA
lb
~
4.5
V
Rs = 0
V 12
(2)
LlV l l
---;;v;-
Output voltage
Vs = 12V
Output voltage drift
V s =11to14V
7
V l l = 5.5V
1a
5.6
V
1a
3.5
%
lb
9.5
rnA
3c
-5
V
-
220
IlV
AC CHARACTERISTICS (Refer to fig. 2 test circuit, Vs = 12V, T amb = 25°C)
IS (3)
V7
V.
I
(4)
LlV I
Vo
Tuner AGe current
V7 = 0
fo = 38.9 MHz
R4
= 2.5 K.fl
6
AGe gating pulse input
peak voltage
f = 15.6 kHz
-1.5
I nput sensitivity
V7 = 0
fo = 38.9 MHz
V 11 = 3.3V peak to peak
100
150
V 7 =0
LlVo = 1 d8
fo = 38.9 MHz
V 11 = 3.3V peak to peak
50
60
V 7 =0
V l l = 5.5V
fo = 38.9 MHz
V I = see note (5)
3.3
3.5
AGe range
Peak to peak output
voltage at pin 11
430
dB
3.7
V
3c
ELECTRICAL CHARACTERISTICS
(continued)
Test conditions
Parameter
Video output varia-
f\,V o
tion over the AGC
range (0 to 5.5 MHz)
V
n . V 12
Sound I F at video
outputs (5.5 MHz)
Differential error of
the output voltage
(B&W)
Vn
. V 12
V7
Vn
~
fa
fm
~
~
~
Min.
0
LWi~50dB
3.3V peak to peak
38.9 MHz
0 to 5.5 MHz
V7 ~ 0
V i ~ see note (5)
fa (vision) ~ 38.9 MHz
fa (sound) ~ 33.4 MHz
Max.
Unit
Fig.
1
2
dB
3b
mV
3d
%
-
30
0
fa ~ 38.9 MHz
3.3V peak to peak
V7
Vn
~
V7
Vi
fa
~O
~
Typ.
15
Video carrier and
video carrier 2 nd har-
monic leakage at
video outputs
V
n . V 12
Video carrier leakage
at video outputs
~
~
see note (5)
38.9 MHz
mV
5
mV
10
MHz
3d
dB
3a
3c
Frequency response
B
8
(-3 dB)
I ntermodulation
dim
products at video
outputs
V7 ~ 0
Vi ~ see note (5)
fa (vision) ~ 38.9 MHz
fa (sound) ~ 33.4 MHz
fa (chroma) ~ 34.5 MHz
-50
V7
1.4
krl
-
2
pF
-
-40
I nput resistance
Ri
(between pins 1
and 16)
I nput capacitance
(between pins 1
and 16)
Ci
NOTES:
15
~O
Vi ~ see note (5)
fa : 38.9 MHz
(1)
(2)
Current flowing out from pin 11 with the load connected to V == av.
V 11 and V 12 are adjustable simultaneously by means of the resistance, or by a variable voltage
(3)
connected between pin 10 and ground.
Measured with an input voltage 10 dB higher than the Vi at which the tuner AGe current starts.
(4)
RMS values of the unmodulated video carrier (modulation down).
(5)
The input voltage Vi can have any value within the AGe range.
436
< O.6V.
Fig. la - Test circuit for measurement
of is. V ll • V 12
Fig. lb - Test circuit for measurement
of-ill and 6.V ll/6.Vs
J;
IDA 4405
lDA 4405
10
11
3V •
Rl
2.5
kil
TO 8 FOR -Ill TEST
Fig.2 - AC test circuit
VIDEO
.(v5O'_ _ _-.-_ _-.-_ _ _ _ (~g~j~~E)
VIDEO
(~~~~¥I~E)
2.5kfl
R5
13
12
10
T,l
TDA.4405
IF
'NPU
1
G
AGe OUTPUT
(TO TUNER)
Note: T 1
Vi
= 50/200n Balun transformer.
= Input voltage between pins 1 and
16.
437
5-097213
Fig. 3a - Set-up for measurement of dim
SELECTIVE
VOLTMETER
S-0973
Fig. 3b - Set-up for measurement of l:;,.Va
AC VOLTMETER
UP TO 5.5 MHz
5-0974
Fig. 3c - Set-up for measurement of
'5.
Vi' l:;,.V i • Va. V 11 and V 12
.V5
o
• AC
VOL TMETER
.SELECTIVE VOLTMETER
FOR LEAKAGE TEST
438
Fig. 3d - Set-up for measurement of B, V 11 and V 12
V
AC VOLTMETER
o (UP TO 1SMHz)
VIDEO CARRIER INPUT LEVEL a dB
SIDE BAND INPUT LEVEL
-3QdB
SOUND CARRIER INPUT LEVEL.-30dB
S1 TO
A
FOR FREQUENCY RESPONSE TEST
51 TO B FOR SOUND r F OUTPUT TEST
Fig. 5 - Tuner AGC output
current vs. I F gain variation
Fig. 4 - AGC voltage vs.
input voltage variation
G
"
I
'" Hc--I~fdce'~9"~H'--+-+-+-+-IH-t-l
__
4
I
- - c---
VS~!2V
--:~:~SOJ.JV(OdB)
110=3.3 vpp ,,-t-t-t--t--+-1
--
VS .,,12 V
117=0
"
L
20
Hall
f:389MHz
f-- - " OdS =Gma~ f--
-10
~
Fig. 6 - Output black level
vs. supply voltage
30
/R6;O
II
I
I
R6;O_5Kfi
I
I
I J
-30
R6.>Kfi /
"nt.:t
II (In
I I1I1
.A 11 ~
-40
.o.G(d8)
APPLICATION INFORMATION
The TDA 440S enables very compact I F amplifiers to be designed and provides the performance demanded by high quality receivers.
The input tuning-trapping circuitry and the detector network can be aligned independently with respect
to each other.
The value of Q for the parallel tuned circuit between pin 8 and 9 is not critical, although the higher it
is, the better is the chroma-sound beat rejection, but the tuning is more critical. Values of Q from 30 to
50 give good rejection with non-critical tuning.
The LC circuit between pins 8 and 9 is tuned to the vision carrier thus appreciably attenuating the sidebands. Hence a small amount of signal can be removed whose amplitude is almost constant over the
whole working range of the AGC and it can be used to drive an AFC circuit.
The black level at the output is very stable against variations of Vs and of temperature: this enables
the contrast control to be kept simple. The AGC is of the gated type and can take the top of the
synchronism or the black level (back porch) as its reference: when the latter is used, the output black
level is particularly stable.
439
Fig. 8 - Typical application circuit.
VIDEO
OUTPUT
(NEGATIVE)
VIDEO
OUTPUT
(POSITIVE)
R7
14
13
12
11
2.5k(l
10
TDA 4405
C19
II
:: O.42,uH- Q o= 110 -
lZ, L3,L7=0.3,uH- Q O= 110
L4
=
R6 t..7t.1,uF
MANUAL GAIN
RJ
CONTROL o--l_l--+----1--t-~
kfl
:: O.22,uH- QO=110-4.5turns,0=O.22mn(close wound}
L5,l6::
L8
6turns0::0.22rrm (clos€' wound)
5.5turnskhO.22rrm{close wound)
KEY INPUT
51
kfl
1 )-lH-Q O=1l0- IOturns0=O.22rnn{close wound)
1.2jJH-Q O"nC- IOturns.0=O.2Zmn(c\osewoundJ
AGe TUNER
L1 tol7:coil former BR 27IP,coreGW4>O.5'13Fl00 Neosld,
screening can BR JOIST
5-097711
Typical performance of the Fig. 8 circuit
Fig. 9 - Overall frequency
response of the fig. 8 circuit
Frequency response (fo vision = 38.9 MHz, fo sound = 33.4 MHz)
standard eel R
Sound carrier attenuation
28
dB
;;;'60
dB
31.9 MHz trap attenuation
;;;. 56
40.4 MHz trap attenuation
dB
;;;. 44
41 .4 MHz trap attenuation
dB
AGe range
55
dB
Overall gain including I F filter and trap
circuits (note 1)
dB
86
Intermodulation products over the whole
- 55
AGe range (note 2)
dB
dB
13~MHZ
(1)
(2)
The gain is measured at video output 3.3V peak to peak
and is defined as peak to peak output voltage to RMS
input voltage (modulation down).
Measured at 1.07 MHz, vision carrier level = 0 dB, chroma
carrier level = -6 dB, sound carrier level = -6 dB.
440
40.4MHz
I 41j4MHZ
j\
·10
I
.40
.60
NOTES:
6.9MHz
1.9MHz
,
I
I
rTj
32
-
.
Jb
1,4
f (MHz)
I
II
I
I"
I',
j~
Fig. 10 - Circuit options for tuner AGC driving
!'\
!I
Ii
Ii
j\
i.ii
'I
.1
I;
i.
lOA 4405
2.2
r----------
kfi
I
I
:
PIN DIODE TUNER
I
I
I
'-----------
5-098111
TDA 440 5
I
I
I
I
I
I
IL __________ .:..._
5-0982f1
441
LINEAR INTEGRATED CIRCUIT
PREAMPLIFIER WITH ALC FOR CASSETTE RECORDERS
• EXCELLENT VERSATILITY in USE (V s from 4 to 20V)
• HIGH OPEN LOOP GAIN
• LOW DISTORTION
• LOW NOISE
• LARGE AUTOMATIC LEVEL CONTROL RANGE
• GOOD SUPPLY RIPPLE REJECTION
• STEREO MATCHING BETTER THAN 3 dB
The TDA 1054M is a monolithic integrated circuit in a 16-lead dual in-line plastic package. The functiens incorporated are:
-- Low noise preamplifier
- Automatic level control system (ALC)
- High gain equalization amplifier
- Supply voltage rejection facility (SVRF).
It is intended as preamplifier in cassette tape recorders and players, dictaphones, compressor and ex·
pander in industrial equipments, Hi-Fi preamplifiers and in wire diffusion receivers; for stereo applications the ALC matching is better than 3 dB.
ABSOLUTE MAXIMUM RATINGS
Vs
P tot
Tstg,"J;j
Supply voltage
Total power dissipation at Tamb .;;; 50°C
Storage and junction temperature
ORDERING NUMBERS:
TDA 1054M mono applications
2 TDA 1054M stereo applications
MECHANICAL DATA
6/82
20
V
500
mW
-40 to 150°C
Dimensions in mm
442
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
16 ALe REC~~~
Ale OUTPUT
~~~~iO SUPPLY 2
1..1:
COLLECTOR
ALe INPUT
J
SUPPLY
Q2 BASE
"
VOLTAGE
Ql BASE
\3
OUTPUT
01 EMITTER
12 ccJ~~c;~ET~~
11 NON INV~:r~~
02 EMITTER
Q2 COLLECTOR
07
7
10
o.
INVERTING
INPUT
GROUNO
12
01
Q2
SVRF
\3
EQUALIZATION AMPLIFIER
16
A LC
TEST CIRCUIT
~-------------------------------{)+Vs
~
1
150pF
0.47t.JF
4.7 k!l 0.47
B~
Bo
A
52
2.2I'F
6V
47}JF
6V
443
THERMAL DATA
Rth
j-amb
Thermal resistance junction-ambient
max
200
°C/W
Max_
Unit
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, Tamb
=
25°C)
Parameter
Min_
Test conditions
Vs
Supply voltage
Id
Quiescent drain current
RL~ =
Vs ~ 9V
S1 ~S2~S3~ B
hFE
DC current gain
Ic~0.1mA
eN
Input noise voltage (Q1)
4
Ic
f
iN
Input noise current (Q11
NF
Noise figure (Q11
~
~
VCE ~ 5V
V CE
0.1 mA
1 kHz
~
300
20
rnA
500
-
2
JHz
nV
5V
V CE ~ 5 V
Ic~0.1mA
Rg ~ 4.7 k!"l
B (-3 dBI ~ 20 to 10,000 Hz
Open loop voltage gain
(for equalization
amplifier!
Vs
~
9V
Va
Output voltage with
A.L.C.
Vs
f
~
9V
1 kHz S1
~
f
~
~
1 kHz
Vi ~ 100mV
S2 ~ S3 ~ A
(for SVR F systeml
V
6
..E6...
0.5
Gv
R1
Typ_
0.5
y'Hz
4
dB
60
dB
1.1
V
7.5
k!"l
120
!"l
1.3
MV
0.8
V
see schematic diagram
R2
(for SVR F systeml
eN
Input noise voltage
(for equalization amplifier
pin 111
Vs
~
9V
40 dB
V OR
Drop-out (between pins
14 and 21
Vs
~
9V
Rg ~ 4.7 k!"l
S1 ~ B
Gv~
B (-3 dBI~ 22 Hz to 22 KHz
444
Id
~
6 mA
II
Fig. 2 - Equivalent input
noise current vs. frequency
(input transistor 0 1 )
Fig. 1 - Equivalent input
spot voltage and noise current vs. bias current (input
transistor 0,)
'N
0
'N
If*)
10H
(i):
10'
Fig. 3 - Equivalent input
noise voltage vs. frequency
(input transistor 0 1 )
tt
10
0
10'
10
10kHz
k-
10
I
10
lun'
I-":
..
100HZJri
1kHz 10kHz
00
10
10'
1~'
..
-.
•
10'
50 A
50.IJA
10- 1
10'
1.
IC{J.lA)
0
..
f(Hz)
10'
10
10'
..
,
10'
o •
f(Hz}
Fig. 6 - Current gain vs. collector current (input transistor 0 1 )
Fig. 5 - Optimum source
resistance and minimum NF
vs. bias current (input transistor 0 1 )
Fig. 4 - Noise figure vs. bias
current (input transistor 0 1 )
..
lmA
'g •
•g •
(kn)
B(-3dB),,20Hzto lOkH%
G
(k11.):
.~,
10
'\ ilL
,~
'dB
2
10
j
i'..~
I i
500
10
100Hz
f--+
I
1'.."
10'
I"
"
..
<00
>1-
1kHz
10kHz
II
10'
10
10'
Fig. 8 - Open loop phase response vs. frequency (equalization amplifier)
Fig. 7 - Open loop gain vs.
frequency (equalization amplifier)
G'rTnm~~rnrTm~~~ill~III~~
(dS)
Htttlttl--titttllf--t+tttIII-++tlfflll-!
IIIII--H-ttfflfl
60r+~~~~~~~~·I~IIIIUli~
-60
-120
-180
-240
-300
10'
10'
10'
10'
10'
I (Hz)
10'
445
10'
10'
10'
lev..I.A)
APPLICATION INFORMATION
Fig.9 - Application circuit for battery/mains cassette player and recorder
"
~~~~
L-l
6V
* TANTALUM
1.8,uF
R21
2.2
"'
CAPACITORS
Fig. 10 - P.C. board and component layout for the circuit fig. 9 (1:1 scale)
446
'"270n
Typical performance of circuit in fig. 9
(T amb
= 25°C, Vs = 9V)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
PLAYBACK
Gy
Voltage gain
(open loop)
f
= 20 to 20,000 Hz
110
dB
Gy
Voltage gain
(closed loop)
f
= 1 kHz
57
dB
IZjl
Input impedance
f
f
f
= 100 Hz
= 1 kHz
= 10 kHz
10
41
43
kn
kn
kn
IZol
Output impedance
f
= 1 kHz
12
B
Frequency response
d
Distortion
S+N
-N-
Output weighted
background noise
n
see fig. 12
Vo= lV
f
= 1 kHz
Output background noise
***
35
Z9 = 300 n + 120 mH
(DIN 45405)
0.1
%
1.3
mV
1.3
mV
Signal to noise ratio
Vo= 1.3V
Z9 = 300 n + 120 mH
60
dB
SVR
Supply voltage ripple
rejection at the output
frjPPle = 100 Hz
30
dB
ton **
Switch-on time
Vo= lV
500
ms
Gy
Voltage gain
(open loop)
f
= 20 to 20,000 Hz
110
dB
Gy
Voltage gain
(closed loop)
f
= 1 kHz
70
dB
B
Frequency response
d*
Distortion without ALC
Va= 1.1V
f
=.1 kHz
0.3
%
d
Distortion with ALe
Vo= 1.1V
f
= 10 kHz
0.4
%
ALe
Automatic level control
range (for 3 dB of output
voltage variation)
Vj "40mV
f
= 10 kHz
54
dB
Vo
Output voltage before
clipping without ALe
f
2.3
V
Vo
Output voltage with ALe
Vj =30mV
1.1
V
RECORDING
see fig. 14
= 1 kHz
447
f
= 10 kHz
Typical performance of circuit in fig. 9 (continued)
Parameter
t[ **
tset
tree
Test conditions'
Min.
Limiting time Isee fig. 11)
LV;~+40dB
---
f
~
ton **
S + N ****
-N-
~
LV;
Switch-on time
Vo~
1.1V
Signal to noise ratio with
ALe
Vo~
1.1V
-40 dB
f
~
Max.
Unit
75
ms
300
ms
150
s
500
ms
64
dB
1 kHz
Level setting time
Isee fig. 11)
Recovery time
Isee fig. 11)
Typ.
1 kHz
Rg~470n
* Measured with selective voltmeter
This value depends on external network
When the DIN 45511 norm for frequency response is not mandatory the equalization peak at 10 kHz can be
avoided - so halving the output noise
Weighted noise measu"ement lOIN 45405)
Fig. 11 - Limiting, level setting, recovery time
Vi
'0
-.-
'0
tset
~ ~_\-
~
VO~
tl
=lIMITING
trec=RECOVERY TIME
TIME
tset:: LEVEL SETTING TIME
5_11-12
Fig. 12 - Relative frequency
response for the circuit in
fig.9 (playback)
Fig. 13 - Distortion vs. fre·
quency for the circuit in fig.
9 (playback)
Fig. 14 - Relative frequency
response for the circuit in
fig.9 (recording)
G,r;~TImr>-nTIlmrllll-'~mr-'nnm
611
(;-2178
Yr • t
(V)
(VI
Tamb
'II."
,
= 25"C
\/slY)
IS
Fig. 6 - Reflection coefficient vs. supply voltag~.""
Tamb =2Soc
1M ", loomA
V... 6'11
23
6'11
l1V
18'11 -
1.30
I.
1.2
\ls('II)
22
I", ,,4OOmA
1.4
1.25
I.
21
t3
1.20
•
""""'
2.
1.2
19
1.15
1.1
16
1.10
"
100
200
300
'M(mA)
-2.
40
2.
to Tambrtl
"
Fig. 8 - Reflection coefficient vs. ambient temperature
Fig. 7 - Reflection coefficient vs. motor current
12
16 VsIV)
Fig. 9 - Typical minimum
supply voltage vs. motor
current
.·21nll
VH'.O
'Is ,,6'11
Tamb " 25"C
23
23
22
22
V• .,..,
21
21
2.
2.
8'
"
19
16
18
'V)
1M'" 25mA
" " SOmA
" = 100m A
" =200mA
" =400mA
.. T~mb·Z5-C
!!w.-s
Yr ..,
.
2.8
14
~~.
17
I.
"
f+ll I
100
200
300
'MirnA)
-20
20
Wi4.
456
U
I.'
60 Tamb,OC)
100
200
300
.,.
...
-
APPLICATION INFORMATION
1M
RM
Eg
Motor current at rated speed
Motor resistance
Back electromotive force
V ref • RT
RSmin= Eg-(Vref-Id
RT )
RT
K· RM
RT
K typ • RM typ
If RT max> KRM min instability may occur
5-1996
Application circuit
+9V
14.2n
280n
1 kn
2.9V
150 mA
RM • 1M + Eg = 5.03V
5-1995
Note: A ceramic capacitor of 10 nF between pins. 1 and 2 improves stability in some applications.
Fig. 10 - Speed variation vs.
supply voltage
.
n
.
(rpm)
T~mb.,2S'C
ro
A..
••
Fig. 12 - Speed variation vs.
ambient temperature
Fig. 11 - Speed variation vs.
motor current
~~~~dfj:::
~
(rpm)
,. , IT~'·m~'.']'.c1111
G"l17ill
(rpm)
Vs " 9V
_
IM:a lSOmA.
1080
('/.)
Vs: + 9V
I "l50mA
1200
1-1--1-1--+-1--1-+-1--1-1-·+-'--1-1-+--1-1--1-1-12100
1100
-.
1000
-'0
,"00
1900
12
16
Vs (V)
-,
2000
_11,"00
so
100
140
457
220
[M(mA)
'9EO
1920
-10
10
'"'
APPLICATION INFORMATION (continued)
Low cost application circuit
+12V
14.7n
290n
1 kn
2.65V
110 mA
Vs
RM
RT
Rs
Eg
1M
M
10nF
5-2000
Fig. 14 - Speed variation vs.
motor current
Fig. 13 - Speed variation vs.
supply voltage
..!co..
(rpm)
("I.)
T~mb
..An.
"
,"/.)
=25'
Fig. 15 - Speed variation vs.
ambient temperature
(rpm)
Vs ='ZV
~
(rpm)
("/.)
lamb= 25"C
lis
1M'" 1l0mA
,.1210'
'",,='10mA
10
2200
10
2200
2200
ID
2100
2100
2100
2000
2000
2000
-,
1900
-,
1900
-,
1900
-ID
1800
-10
1800
·10
1800
12
,0
100
458
20
60
LINEAR INTEGRATED CIRCUIT
TV VERTICAL DEFLECTION SYSTEM
The TDA 1170 is a monolithic integrated circuit in a 12-lead quad in-line plastic package. It is designed
mainly for use in large and small screen black and white TV receivers.
.
The functions incorporated are:
oscillator
voltage ramp generator
high power gain amplifier
flyback generator
ABSOLUTE MAXIMUM RATINGS
Vs
V 4 -V 5
Va
Supply voltage (pin 2)
Flyback peak voltage
Sync. input voltage
VlO
Power amplifier input voltage
10
Output peak current (non-repetitive) @ t = 2 ms
@ f = 50 Hz, t ~ 10 J1s
Output peak current @ f = 50 Hz, t> 10 J1s
10
Ptot
27
58
± 12
10
1. -0.5
2
2.5
1.5
5
1
-40 to 150
J
Power dissipation: at T tab = 90°C
at Tamb = 80°C (free air)
Storage and junction temperature
V
V
V
V
V
A
A
A
W
W
°C
ORDERING NUMBER: TDA 1170
Dimensions in mm
MECHANICAL DATA
459
CONNECTION AND BLOCK DIAGRAM
(top view)
RAMP OUTPUT
RAMP
GENERATOR
SUPPLY VOLTAGE
GROUND
REGULATED
VOLTAGE
C6
+-_--'~_--'~
________________+ _ _ + - '
SCHEMATIC DIAGRAM
_
1
~to,
-r-@
~~
I
a~
I
1
R~~
I I
~"2 Vu35i.
05
«.<\"~:"! ';:..
+-+r
ni $
!
i.
i
4
I
032
TABS
460
5-0611/2
THERMAL DATA
Rth j-tab
Rth j-amb
max
max
Thermal resistance junction-tab
Thermal resistance junction-ambient
12 °C/W
70* °C/W
* Obtained with tabs soldered to printed circuit with minimized area.
I'
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Vs = 25V, T amb = 25°C unless
otherwise specified)
Test conditions
Parameter
DC CHARACTERISTICS
-19
Oscillator bias current
Vg
-1 10
Amplifier input bias
current
VI0~
-112
1V
~
1V
Ramp generator bias
0.2
1
J.lA
1a
0.15
1
J.lA
1b
0.05
0.5
J.lA
1a
current
Vs
Supply voltage
V4
Quiescent output voltage
10
R2 ~ 10 kD
Vs ~ 25V
Vs~10V
V 6, V 7
R1
R1
~
~
30 kD
10 kD
Regulated voltage
/'-,V 6 /'-,V 7
- - Line regulation
/'-,V s /'-,V s
V
-
1a
8
4
8.8
4.4
9.6
4.8
V
V
6
6.5
7
V
I.
1b
V5
~
10 to 27V
mV/V
1.5
Supply current
Iv
Peak to peak yoke current
(pin 4)
V4
Flyback voltage
Va
Peak sync. input voltage
(positive or negative)
Iv
II
~
1A
140
mA
1.6
A
2
Iv
'I:
Ii
AC CHARACTERISTICS (f = 50 Hz)
Is
i
~
1A
51
1
461
V
V
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
Vg
Peak to peak oscillator
sawtooth voltage
Ra
Sync. input resistance
Va
~
tfly
Flyback time
Iy
~
of
Pull-in range
(below 50 Hz)
3.5
kr!
1A
0.6
of
/:,T tab
Oscillator frequency drift
with tab temperature
Ttab~
10 to 27V
40 to 120°C
Fig.
ms
0.8
7
Hz
0.01
Hz
V
0.015
Hz-
2
°C
Fig. 1b - DC test circuit for measurement of
-110' V 6, V 7,6V 6/6Vs and 6V 7/tN 5
Fig. 1a - DC test circuit for measurement of
-19, -112 and V4
TDA1170
Unit
1V
Vs
9
Max.
V
Oscillator frequency drift
with supply voltage
--
Typ.
2.4
of
/:,V s
~
Min.
9
4
5V
462
TDA 1170
10
Fig.2 - AC test circuit
, -________~~------~~----~----------------------~.V5=25V
DI
::'1
IN4001
C3
lOOfJF 25V
TABS
2
4
R9
10 kll
II
1000 ",F/16 v
C7
SYNC INPUT 8
TDA 1170
10
I
YOKE
Ion
12
20mH
R7
5.6kll
C4
O.lfJF
R3
270
C5
kll
O.1fJF
RIO
III
Fig. 3 - Relative qu iescent
voltage variation vs. supply
voltage
5-111813
Fig. 5 - Regulated voltage
vs. supply voltage
Fig. 4 - Relative quiescent
voltage variation vs. tab
temperature
-:bti: ~
~t -ttii~~
,
R:- +~-+6.52
I
--<--
6.50
6.4
,
-f-+-I-
6,46
··+fa.;;'b=25'C
-[ t-
H-
I
10
20
25
Vs (v)
10
463
IS
20
25
Vs (v)
Fig. 6 - Regu lated voltage
vs. tab temperature
Fig. 8 - Frequency variation
of unsynchronized oscillator
vs. tab temperature
Fig. 7 - Frequency variation
of unsynchronized oscillator
vs. supply voltage
to
25
20
"
Vs
lv}
APPLICATION INFORMATION
The thermistor in series to the yoke is not required because the current feedback enables the yoke
current to be independent of yoke resistance variations due to thermal effects. The oscillator is directly
synchonized by the sync. pulses (positive or negative). therefore its free frequency must be lower than
the sync. frequency. The flyback generator applies a voltage, about twice the supply voltage, to the yoke.
This produces short flyback time together with a high useful power to dissipated power ratio.
The flyback time is:
2
Lv Iv
3'
Vs
where:
Lv
Vs
Iv
Yoke inductance
Supply voltage
Peak to peak yoke current
The supply current is:
Iv
+ 0.02 (A)'
8
It does not depend on the value of V s but only on yoke characteristics. The minimum value of V s
necessary for the required output current permits the maximum efficiency.
The quiescent output voltage (pin 4) is fixed by the voltage feedback network R7, R8 and R9 (refer to
fig. 2) according to:
R7
+
R8
R7
+
R9
Pin 10 is the inverting input of the amplifier and its voltage is V 10:::= 2V.
464
Fig. 9 - Typical application circuit for B & W 24" 110° TV sets
=fj
Hold 150kil
*
5-061312
Tolerance 5%
Typical performance (V s = 22V; Iv = 1A; Rv= 10n; Lv= 20 mH)
Supply current
Flyback time
Maximum scanning current (peak to peak)
Operating supply voltage
TDA 1170 power dissipation
140
0.75
1.2
20 to 24
2.2
mA
ms
A
V
W
For safe working up to T amb = 50°C a heatsink of Rth = 40 °C/W is requ ired and each tab of TDA 1170
must be soldered to 1 cm 2 copper area of the printed circuit board.
465
Fig. 10 - Typical application circuit for B & W small screen TV sets
.------..----+---...------------o.Vs=1Stab.
O.BV
llr------<>----------'
~VNC
INPUT 8
C7
TDA 1170
2000 ).JF/IOV
10 I--~-.--___.--["-H
1
YOKE
12
P3
47kil
linearity
P2
Height
.R2
220kJl
*C.4
*R6
0.1}J·E39kJl
R3 •
470
kJl
R7
68kJl
CS*
O.1}JF
RIO
* Tolerance 5·'.
S-1I20n
Typical performance (V. = 10.8V; Iy= 1A; Ry = 4n; Ly = 7.5 mH)
Supply current
Flyback time
Maximum scanning current (peak to peak)
Operating supply voltage
TDA 1170 power dissipation
150
0.7
1.15
10.8
1.3
rnA
ms
A
V
W
For safe working up to T amb = 50°C a heatsink of Rth = 30 °C/W is required and each tab of the
TDA 1170 must be sol de reb to 1 cm 2 copper area of the printed circuit board.
466
Fig. 11 - P.C. board and component layout for the circuit of fig. 9 and fig. 10 (1: 1 scale)
+Vs
GND
YOKE
YOKE
SYNC.
GND
C9 is not mounted on the P.C. board.
MOUNTING INSTRUCTIONS
The junction to ambient thermal resistance of the TDA 1170 can be reduced hy soldering the tabs to a
suitable copper area of the printed circuit board (fig. 12) or to an external heatsink (fig. 13).
The diagram of fig. 16 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the
side "s" of two equal square copper areas having a thickness of 35!l (1.4 mil).
During soldering the tab temperature must not exceed 260 DC and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
467
Fig. 13- Example of TDA 1170 with external heatsink
Fig. 12 - Example of P.C. board copper area
used as heatsink
R AREA
35}.J THICKNESS
H£ATSINK
R'h ~ 30°CjW
C. BOARD
Fig. 14 - Maximum power
dissipation and junction-ambient thermal resistance vs.
"s"
R
"
20
Fig. 15 - Maximum allowable
power dissipation vs. ambient temperature
jamb
30
40 s (mm)
468
LINEAR INTEGRATED CIRCUIT
LOW-NOISE TV VERTICAL DEFLECTION SYSTEM
The TDA 11700 is a monolithic integrated circuit in a 16-lead dual in-line plastic package. It is intended for use in black and white and colour TV receivers. Low-noise meakes this device particularly
suitable for use in monitors. The functions incorporated are:
I
synchronization circuit
oscillator and ramp generator
high power gain amplifier
flyback generator
voltage regulator
ABSOLUTE MAXIMUM
V,
V6, V7
V14
I
I'
Supply voltage at pin 2
Flyback peak voltage
Power amplifier input voltage
Output peak current (non repetitive) at t = 2 msec
Output pe'lk current at f = 50 Hz t ~ 10 psec
Output prakcurrentat f = 50 Hz t > 10 psec
Pin 3 DC ctlrrentat V6 < V2
Pin 3 peak to peak flyback current for f = 50 Hz, tfly
Pin 10 current
Power dissipation: at T tab = 90°C
at Tamb = 70 0 e (free air)
Storage and junction temperature
~
1.5 msec
35
60
{ + 10
- 0.5
2
2.5
1.5
100
1.8
± 20
4.3
1
-40 to 150
V
V
V
V
A
A
A
mA
A
mA
W
W
°C
ORDERING NUMBER: TDA 11700
MECHANICAL DATA
. Dimensions in mm
PQ:)l-V
469
6/82
CONNECTION DIAGRAM
RAMP
RAMP OUTPUT
16
SUPPLY VOLTAGE
15
COMPENSATION
FLYBACK
14
AMP. INPUT
11
GROUND
12
AMP. OUTPUT
GENERATOR
I
GROUND
OSCILLATOR
AMP VOLTAGE
REGULATED
VOLTAGE
10
SINe. [NPUT
9
HEGHT ADJUST
5_531411
-----''------------,-------o·V.
BLOCK DIAGRAM
...
i
THERMAL DATA
Rth j-tab
Rth j-amb
Thermal resistance junction-pins
Thermal resistance junction-ambient
max
max
1°) Obtained with pins 4, 5, 12,13 soldered to printed circuit with minimized copper area.
470
14 °C/W
80 °C/W (0)
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,
Vs
J
othwwise specified)
Test conditions
Parameter
DC CHARACTERISTICS
12
Pin 2 quiescent current
13
~
0
17
Pin 7 quiescent current
14
~
0
-III
Oscillator bias current
Vll~
1V
Amplifier input bias
V12~
lV
0
-112
7
14
mA
lb
8
15
mA
lb
0.1
1
)J.A
la
1
7
)J.A
lb
0.02
0.3
)J.A
la
20
24
)J.A
lb
0.2
1
%
lb
35
V
-
1
1.4
V
-
1.7
2.6
V
la
4.17
4.4
4.63
V
la
8.35
8.8
9.25
V
1a
O.lA
0.9
1.2
V
lc
-16= 0.8A
1.9
2.3
V
lc
16= O.lA
1.4
2.1
V
ld
current
-116
Ramp generator bias
current
V16~
-1 16
Ramp generator current
17
LlI16
Ramp generator
non-linearity
LI V 16= 0 to 1 2V
19 = 20)J.A
116
Vs
Vl
20)J.A
~
19
V16= 0
Supply voltage range
Pin 1 saturation voltage to
10
11
~
1 mA
ground
V3
Pin 3 saturation voltage to
13~10mA
ground
V6
Quiescent output voltage
Vs~
R2
lOV
10 Kll
Rl=10Kll
35V
Rl = 30 Kll
~
Vs~
r-
R2~10Kn
V6L
Output saturation voltage
-16~
to ground
V6H
Output saturation voltage
to supply
2.8
3.2
V
ld
6.1
6.5
6.9
V
lb
6.2
6.6
7
V
lb
mVN
lb
V
--
Mll
1a
16= 0.8A
V8
Regulated voltage at pin 6
V9
Regulated voltage at pin 7
LI V8; LI V9 Regulated voltage drift
LI V s LI V s with supply voltage
V14
Amplifier input reference
voltage
Rl0
Pin 10 input resistance
19= 20)J.A
LlV s =10t035V
1
2.07
1
V10';; O.4V
471
22
2.3
Fig. 1 - DC test circuit
10
11
11
D.U.T.
14
I
--1.-
Fig.lb
Fig. la
1I
11
D.U.T.
11
14
I
I
--L
4v
"------~---
1
D.U.T.
14
V6L
IV
5-5317
Fig. ld
Fig. lc
472
-114
5-5316
ELECTRICAL CHARACTERISTICS (Refer to the AC test circuit,
25V; f = 50 Hz;
Vs
T amb = 25°C, unless otherwise specified)
Test conditions
Parameter
AC CHARACTERISTICS
~
Iy
1 App
Is
Supply current
140
mA
11 0
Sync. input current
(positive or negative)
V6
Flyback voltage
Iy
~
1 App
51
V
tll y
Flyback time
Iy
~
1 App
0.7
ms
VON
Peak to peak output
Bw~
500
J.lA
20 -0- 20.000 Hz
50
rnV
noise
fo
Llf
LIt
LlVs
Llf
LIT pins
Free running frequency
(P1 + R1) ~ 260 K!1
C2 ~ 0.1 J.lF
52.4
Hz
(P1 + R1) ~ 300 Kn
C2;100nF
43.7
Hz
~
Synchronization range
18
Frequency drift with
supply voltage
Vs
Frequency drift vs. pins
4,5,12 and 13 temp.
Ttab~ 40 to 120°C
~
0.5 rnA
14
Hz
10 to 35V
0.005
Hz/V
0.01
Hzf'C
Fig. 2 - AC test circuit
D 1 fIN 4001
r---i
C36
Cl
O.1~F
.L
Cl0
,
100~;r5Vr-o-l..J..-!-.l...J...J--,
L 37
R9
10
151--~1--
~n
_ _ _-'
C7
SYNC INPUT
10
TDA 11700
1000 ....F/16 V
R8
141----1---------~c:J-i
R5
L.7k!1
, I--~I---.,
L...;i-__.:;-__..:,'6::...J
4;: ~, "'
PI
C4
J:."ea~!~
O.1,up,47kD.
YOKE
Ion
20mH
R7
5.6kn
R3
270
kll
C5
O.1,uF
RIO
'n
473
5-5359
Fig.3 - P.C. board and components layout of the AC test circuit.
474
LINEAR INTEGRATED CIRCUIT
LOW-NOISE TV VERTICAL DEFLECTION SYSTEM
The TDA 1170N is a monolithic integrated circuit in a 12-lead quad in-line plastic package. It is intended for use in black and white and colour TV receivers. Low-noise meakes this device particularly
suitable for use in monitors. The functions incorporated are:
synch ron ization ci rcu it
oscillator and ramp generator
high power gain amplifier
flyback generator
vo Itage regu lator
ABSOLUTE MAXIMUM
Vs
V4,V5
Vl0
Supply voltage at pin 2
Flyback peak voltage
Power amplifier input voltaij.e
r
Output peak currEl~t (tJo()nr~petrtive) at t = 2 msec
Output peakqljl~r~ntl;\1;~= 50 Hz t .;;; 10 /lsec
Output peal5;~urre~t atf= 50 Hz t > 10 flSec
Pin 3 g'EcurrElPt~tV4 < V2
Pin 3 ~I;\k.:~()peak flyback current for f = 50 Hz, t jly
Pin S CUl'r:E!nt
Power di~~ipation: at T tab = 90 0 e
at T amb = sove (free air)
Storage and junction temperature
.;;;
1.5 msec
35
60
10
- 0.5
2
2.5
1.5
100
1.S
± 20
5
1
-40 to 150
V
V
V
V
A
A
A
mA
A
mA
W
W
°e
Dimensions in mm
MECHANICAL DATA
475
6/82
CONNECTION AND BLOCK DIAGRAMS
RAMP
GENERATOR'
RAMP OUTPUT
COMPENSATION
SUPPLY VOLTAGE
FLVSACK
AMP. INPUT
GROUND
GROUND
OSCILLATOR
AMP. OUTPUT
SYNC.
AMP. VOLTAGE
REGULATED
VOLTAGE
INPUT
HEIGHT ADJUST.
5-1'1511
THERMAL DATA
Rth j-tab
Rth j-amb
Thermal resistance junction-tab
Thermal resistance junction-ambient
max
max
(0) Obtained with tabs soldered to printed circuit with minimized copper area.
476
12
70
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Vs
=
35V, T amb = 25°C, unless
otherwise specified)
Parameter
Test conditions
DC CHARACTERISTICS
12
Pin 2 quiescent current
7
13 = 0
15
Pin 5 quiescent current
14 = 0
-19
Oscillator bias current
V9 = 1V
-110
Amplifier input bias
Vl0= lV
14
mA
lb
1b
8
15
mA
0.1
1
}J.A
la
1
7
}J.A
lb
0.02
0.3
}J.A
la
20
24
}J.A
lb
0.2
1
%
lb
35
V
~
~
current
-112
Ramp generator bias
V12= 0
current
-112
L'l112
112
V12= 0
Ramp generator current
17 = 20}J.A
Ramp generator
L'I V 1 2= 0 to 12V
non-linearity
17 = 20}J.A
19
Vs
Supply voltage range
Vl
Pin 1 saturation voltage to
ground
11=1 mA
1
1.4
V
V3
Pin 3 saturation voltage to
ground
13 = 10 mA
1.7
2.6
V
la
V4
Quiescent output voltage
Vs= lOV
R2 = 10 K!1
Rl= 10 K!1
4.17
4.4
4.63
V
la
Vs= 35V
R2=10K!1
Rl= 30 K!1
8.35
8.8
9.25
V
la
0.9
1.2
V
lc
lc
V4L
Output satu ration voltage
to ground
V4H
Output saturation voltage
to supply
V6
Regu lated voltage at pin 6
V7
Regulated voltage at pin 7
10
-14= O.lA
-14= O.8A
1.9
2.3
V
14 = O.lA
1.4
2.1
V
ld
2.8
3.2
V
ld
6.1
6.5
6.9
V
lb
6.2
6.6
7
V
lb
mVN
lb
14 = O.8A
L'I V6 ; L'I V7 Regulated voltage drift
L'I V s L'I Vs with supply voltage
Vl0
Amplifier input reference
voltage
R8
Pin 8 input resistance
17 = 20}J.A
1
L'lVs= 10 to 35V
2.07
V8,;;; O.4V
1
477
22
2.3
V
M!1
~
la
Fig. 1 - DC test circuits
TDA 1170 N
lOA 1170 N
10
Rl
10
TABS
V4
R2
--LSV
BV
5 - 5300
Fig.lb
Fig.la
.Vs
~----2-S
2-S
V4H
lOA 1170 N
lOA 1170 N
10
10
TABS
TABS
--L 4V
T
~IY
I
'----_ _ _----*-____
±
Fig. ld
Fig.lc
478
--+____
!
.J..
...J
5-5303
ELECTRICAL CHARACTERISTICS (Refer to the AC test circuit, Vs
25V; f = 50 Hz;
Tamb = 25°C, unless otherwise specified)
Parameter
Test conditions
AC CHARACTERISTICS
Is
Supply current
Is
Sync. input current
(positive or negative)
Iy = 1 App
140
mA
500
JJ-A
V4
Flyback voltage
Iy= 1 App
51
V
tfly
Flyback time
Iy
0.7
ms
VON
Peak to peak output
Bw = 20 .;. 20.000 Hz
fo
Free running frequency
[If
ld
to V s
I~I
to T tab
=
1 App
50
mV
noise
(P1 + R1) = 300 Kn
C2=0.1JJ-F
52.4
Hz
(P1 + R1) = 360 Kn
C2 = 100 nF
43.7
Hz
14
Synchronization range
Is = 0.5 mA
Frequency drift with
supply voltage
Vs = 10 to 35V
Frequency drift with tab
temperatu re
T tab = 40 to 120°C
Hz
0.005
Hz/V
0.01
Hz/"C
Fig. 2 - AC test circuit
----~------~----~~------------------~O·Vs·25V
lN4001
Dl
R7
5.6kQ
479
Fig. 3 - PC board and component layout of the AC test circuit (1:1 scale)
480
LINEAR INTEGRATED CIRCUIT
TV VERTICAL DEFLECTION SYSTEM
The TDA 11705 is a monolithic integrated circuit in a 12-lead quad in-line plastic package. It is intended for use in black and white and colour TV receivers.
The functions incorporated are:
• synchronization circuit
• oscillator and ramp generator
• high power gain amplifier
• flyback generator
• voltage regu lator
ABSOLUTE MAXIMUM RATINGS
Supply voltage at pin 2
F Iyback peak voltage
Power amplifier input voltage
T stg , T j
Output peak current (non repetitive) at t = 2 msec
Output peak current at f = 50 Hz t < 10 !-,sec
Output peak current at f = 50 Hz t> 10 !-,sec
Pin 3 DC current at V4 < V 2
Pin 3 peak to peak flyback current for f = 50 Hz, t fly
Pin 8 current
Power dissipation: at T tab :: 90:C} TDA 11705
at T amb - 80 C
Storage and junction temperature
< 1.5 msec
35
60
+ 10
- 0.5
2
2.5
1.5
100
1.8
± 20
5
1
-40 to 150
V
V
V
V
A
A
A
mA
A
mA
W
W
°C
ORDERING NUMBERS: TDA 1170 S
TDA 1170 SH
MECHANICAL DATA
· ·. ·. ~· ·.~ ·. · ·.
·e
"
'.
Dimensions in mm
'
TDA 1170SH
TDA.1170 S
481
6/82
CONNECTION AND BLOCK DIAGRAMS
REGULATED
VOLTAGE
SCHEMATIC DIAGRAM
02
als
aID
alS
all
ZI
.3
I
~I
I
02
,
032
.,
!
I
TABS
482
THERMAL DATA
Rth j-tab
Rth j-amb
TDA 1170S
TDA 1170SH
max 1Q°C/W
max 80°C/W
max 12°C/W
max 70°C/W(0)
Thermal resistance junction-tab
Thermal resistance junction-ambient
(0) Obtained with tabs soldered to printed circuit with minimIzed copper area.
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Vs= 35V, T amb = 25°C, unless
otherwise specified)
Test conditions
Parameter
DC CHARACTERISTICS
12
Pin 2 quiescent current
13
~
Is
Pin 5 quiescent current
14
~
-19
Oscillator bias current
Vg
-110
Amplifier input bias current
VlO~
1V
-112
Ramp generator bias current
V12~
0
0
0
1V
~
-112
Ramp generator current
17~20JlA
1';(12
-112
Ramp generator non-linearity
10 V 12~ 0 to 1 2V
17 ~ 20 JlA
Vs
Supply voltage range
VI
Pin 1 saturation voltage to
V12~
19
0
7
14
mA
1b
8
15
mA
1b
0.1
1
JlA
1a
0.1
1
JlA
1b
0.02
0.3
JlA
1a
20
24
JlA
1b
0.2
1
%
1b
36
V
-
1
1.4
V
-
1.7
2.6
V
1a
10
11
1 mA
~
ground
V3
Pin 3 saturation voltage to
ground
13~10mA
V4
Quiescent output voltage
Vs~ 10V
R2~10 Kl1
Rl~10
Kl1
4.17
4.4
4.63
V
1a
Vs~
Rl~30Kl1
8.35
8.8
9.25
V
1a
R2~
V 4L
V 4H
Output saturation voltage to
ground
Output saturation voltage to
supply
35V
10 Kl1
-14
~
0.1A
0.9
1.2
V
1c
-14
~
0.8A
1.9
2.3
V
1c
14
~
0.1A
1.4
2.1
V
1d
14
~
0.8A
2.8
3.2
V
1d
6.1
6.5
6.9
V
1b
~
20 JlA
6.2
6.6
7
V
1b
mV!V
1b
V
-
Ml1
1a
V6
Regulated voltage at pin 6
V7
Regulated voltage at pin 7
17
Regulated voltage drift with
supply voltage
IoVs~
IoV 6 IoV 7
-- -IoV s ' IoV s
VlO
Amplifier input reference
voltage
Rs
Pin 8 input resistance
10 to 35V
1
2.07
V s <;;O.4V
483
1
2.2
2.3
Fig. 1 - DC test circuits
TOA 11705
10
lOA 11705
9
R1
10
TABS
V4
R2
5-329411
Fig.1a
Fig.1b
~
~
2-5
-9
2-5
4r---
lOA 11705
TOA 11705
10
TABS
TABS
t"
,
S - 329&
J
Fig.1c
Fig.1d
484
1
~
-.J
S 3297
14
AC CHARACTERISTICS
(Refer to the test circuit, Vs= 25V; f = 50 Hz; T arnb = 25°C, unless
otherwise specified)
Test conditions
Parameter
Is
Supply current
Is
Sync. input current
(positive or negative)
V4
F Iyback voltage
Vg
Peak to peak oscillator
sawtooth voltage
tfly
Flyback time
fo
Free running frequency
Iy
~
Min.
1 App
Typ.
140
500
Iy
Iy
~
~
(P 1
1 App
1 App
+ R 1)
~ 300 Kr!
C2~100nF
iP 1
+ R 1)
~ 260 Kr!
C2~100nF
~
LIt
Synchronization range
18
LIt
---6V s
Frequency drift with supply
voltage
Vs~10t035V
0.5 mA
I6TLIt tab Il
Frequency drift with tab
temperature
Ttab~40to
C1
mA
2
MA
2
V
2
V
2
0.7
ms
2
44
Hz
2
52
Hz
2
Hz
2
0.005
Hz/V
2
0.01
Hz/oC
2
C3
1.
SYNC INPUT 8
TDA 11705
P1
100kfl
5-1i18/1
485
Fig.
51
Fig. 2 - AC test circuit
O.11'~
Unit
2.4
14
120"C
Max.
Fig.3 - Typical application circuit for small screen B/W TV set (R y = 2.9n, Ly= 6 mH; Iy= 1.1 App)
......- - - - - - - - - - _ o . V s = 1 0 . 8 V
----_~---+--
c,l
"'I
Dl
C9
IN4001
CIO
C3
11 t - - + - - - - - - '
SYNC. o---It:~>---;
INPUT
Cll
C7
2000 .uF/16 V
TDA 11705
10 1---1~
It--_----,
YOKE
12
2.9.fi
6mH
PI,
R1**
56kn
CS
O.1I'F
5-332711
* Toleorance- 5-'.
**.. .
2'1.
Typical performance
Vs
Is
t fly
Ptot
Iy
Operating supply voltage
Supply current
F Iyback time
TDA 11705 power dissipation
Maximum scanning current (peak to peak)
For safe working up to T amb = 60°C a heatsink of Rth = 30°C/W is required.
486
10.8
155
0.5
1.35
1.30
V
mA
ms
W
A
Fig.4 - Typical application circuit for small screen 90° PIL TVC set (R y= 12.5.11; Ly= 31 mH; Iy= 0.8
App)
n
. -________~--------~----~~--------------------~.Vs~22v
Dl
lN4001
C9cb470l-'F
25V
C3
Cl
Rll
3,30
O.II-'F
5 VNC. "--..i
lNPUT'-'
,I-C::-:'-:-'.----t
4.7
R13
k1l.
11
~--~--------_
TDA 1170 S
.
12
PI
l00kIl
I
Rl
~
150kO
Hold
~
lookO'
R2,
220kfly
I
P3
r"[
"-,
.L"'N"'I ;.,
:-r-
O.lj.JF~
nR3*
330
kO
~
47kil}1
C4 ..... 39kl11
R6i
P2
Hegnt
C2
clO
O.l~F
_
I
R7
**
J 561<.1<
C5
T°.1~F
1
**
,,2",
Typical performance
Vs
Is
t f1y
Ptot
Iy
Operating supply voltage
Supply current
Flyback time
TDA 1170S power dissipation
Maximum scanning current (peak to peak)
For safe working up to T amb = 60°C a heatsink of Rth = 18°C/W is required.
487
22
120
0.8
1.95
1.0
V
rnA
ms
W
A
Fig. 5 - Typical application circuit for large screen 8/W TV set (R y = 1012;
Ly=
20 mH; I y = 1 App)
1
----------.-------~~----~---------------------4J·VS=2ZV
Cl
C3
O.II';r
1
11
~
__
~
________
~
O.1IJF
SYNC. "--~
INPUT ,-,----.I-C
=':-'..---i
;:;kfl
i
l.
L
R1
:
150kO
,
'"iiz
:
.J..
I' FI16V
I
12
HOI~.r ~
!
RS ..
-r,~rtlc6
~:
.
1,
TDA 11705
~ ~----~
P.2 I lOOkfl
t, ..
YOKE
10 It
Is.6kO
H •• gnt
R2~
C2
l""'
180kfl
Rl0·
111
5-3329/1
* Tolerancp 5·'.
**..
2'/,
Typical performance
V.
I.
t lly
Ptot
Iy
Operating supply voltage
Supply current
Flyback time
TDA 1170S power dissipation
Maximum scanning current (peak to peak)
For safe working up to T amb = 60°C a heatsink of Rth = 14°C/W is required.
488
22
145
0.7
2.3
1.2
V
mA
ms
W
A
Fig. 6 - Typical application circuit for large screen 110° PI L TVC set (R y = 10n; Ly= 25 mH; Iy= 1.25
App)
,-------~~·---T--_,.------------_o.
470,.,F
35V
'5
iSv
R"[n C'O
3.3 ()
O.1)JF
R9'*1
19H1
TDA 1170SH
e12
J: 6.8nF
C7_
1000
~F/25V
10 t---~-----"-L_
YOKE
12
10 Jl
2SmH
P2
lookO
C4
R2
270kD
*
Tole-rancE'
• • ..
5-'_
2'/,
Typical performance
Vs
Is
tfly
Ptot
Iy
Operating supply voltage
Supply current
F Iyback time
TDA 1170SH power dissipation
Maximum scanning current (peak to peak)
For safe working up to T amb = 60°C a heatsink of Rth = 8.5°C/W is required.
489
25
175
1
3.25
1.4
V
mA
ms
W
A
Fig.7 - P.C. board and component layout of the circuit of fig. 6 (1 : 1 scale)
Note: For the heatsink (1170 Sand 1170 SH) see mounting instructions
MOUNTING INSTRUCTIONS
During soldering the tab temperature must not exceed 260°C and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
TDA 1170S
The junction to ambient thermal resistance of the TDA 11705 can be reduced by soldering the tabs to a
suitable copper area of the printed circuit board (fig. 8) or to an external heatsink (fig. 9).
The diagram of fig. 10 shows the maximum dissipable power Ptot and the Rth i-amb as a function of the
side "sn of two equal square copper areas having a thickness of 35 jJ. (1.4 mil).
490
MOUNTING INSTRUCTIONS (continued)
Fig. 8 - Example of P .C. board copper area used as
heatsink.
Fig. 9 - Example of TDA 1170 S with external
heatsink.
AREA 35)J THICKNESS
HEATSINK
'Rth ~ 30°C/W
P. C. BOARD
Fig. 10 - Maximum Power
dissipation and junctionalambient thermal resistance
vs. "S"
Ptot
Fig. 11 - Maxim. allowable
power dissipation vs. ambient temp. (TDA 1170S)
,!~.,4+tttt
("C/WI
(WI
Fig. 12 - Maxim. allowable
power dissipation vs_ ambient temp_ (TDA 1170SH)
WITH INFINITE HEAT SINK
80
60
R
WITH H AT SINK HAVIN
lamb
40
H-
P tot (lamb =55·C
WITH U HEAT SINK
(T
",70'C)
H-+-H' fjllt
40"
(mm)
-so
50
1
-50
TDA 1170SH
The power dissipated In the circuit may be removed by connecting the tabs to an external heatsink accordrng to fig. 12. The desired thermal resistance may be obtained by fixing the TDA1170SH to a
suitable dimensioned plate as shown in fig. 13.
I
491
I
MOUNTING INSTRUCTIONS
(continued)
Fig, 13 - Mounting example,
492
LINEAR INTEGRATED CIRCUIT
TV HORIZONTAL PROCESSOR
J
The TDA 1180P is a horizontal processor circuit for b.w. and colour television receiver. It is a monolithic integrated circuit encapsulated in 16-lead dual in-line plastic package. The TDA 1180P combines
the following functions:
Noise gated horizontal sync separator.
Noise gated vertical sync separator.
Horizontal oscillator with frequency range limiter.
Phase comparator between sync pulses and oscillator pulses (PLL).
Phase comparator between flyback pulses and oscillator pulses (PLL).
Loop gain and time cons.tant switching (VCR).
Composite blanking and key pulse generator.
Protection circuits.
Output stages with high current capability.
I
ABSOLUTE MAXIMUM RATINGS
Supply voltage (pin 1)
Voltage at pin 2
Voltage at pin 4
15
18
Vs
{ Vs
-6
6
- 6
Vs
1
0.5
30
20
30
1
-40 to 150
Voltage at pin 8
{+
Vg
Voltage at pin 9
Vl l
Voltage at pin 11
Pin 2 peak current
Pin 3 peak current
Pin 6 current
Pin 7 current
Pin 10 current
Total power dissipation at Tamb .;;; 70°C
Storage and junction temperature
12
13
16
17
110
Ptot
T stg, Tj
ORDERING NUMBER:
V
V
V
V
A
A
mA
mA
mA
W
°C
TDA 1180P
Dimensions in mm
MECHANICAL DATA
.•~
.==:sr.
"""".""""""'."'l
l27~\
i~~·········
493
H.·
.•.4.m•.' .•.•.....•.......•...
. ~.
1<' 'f' .
~,
6/82
I
j
i
1
j
I
CONNECTION DIAGRAM
(top view)
16
GNO
OUTPUT -
15
OSc. CONTROL
CURRENT
OUTPUT ...
14
OSCILLATOR
PROTECTION
CIRCUIT INPUT
13
CONT. CURRENT
PHASE SHIFTER
FILTER
12
FLYBACK
11
SUPPLY VOLTAGE
1
INPUT
KEY AND BLANK
PUlSE OUTPUT
T~.i?EPARATOR
7
10
9
R
OUTPUT
TIME CONSTANT
SWITCH
COINCIDENCE
DETECTOR
VERTICAL
SYNC OUTPUT
VERTICAL SYNC
SEPARATOR
IN
s- 3426
BLOCK DIAGRAM
Il
A
Jl
",
.~
",
~
l
II
,l.J
",
~I~~LO
r
I
'L
l'
~I -.
!
(
VCR
rI
_J
."
"
T
494
,':~
.!.
1
1
I
j.'.'
,
I"1,,1
2:
«cc
(!)
«
o
c.J
I-
«
:E
w
:::r::
c.J
rJ)
495
TEST CIRCUIT
SANDCA$TLE
OUTPUT
A Jl
VERT SYNC
OUTPUT
FlYBACK
INPUT (lQOV)
+ Vs
470nF
(I
~~.~Mn
R6
47
kll
,.-....J- ._---'-_ _- ' -_ _~_---L_ __'___,_,
,O
~_ 9
RI
2.2kfl
TDA 1180P
JIDEQ SIGNAL
INPUT
OUTPUT
PULSE
16
•'s o--C=:}-C:J--===:;;'
5>-3427J1
THERMAL DATA
Rth i-amb
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS
80
°e/W
(Refer to the test circuit, Vs= 12V, T amb = 25°e unless
otherwise specified)
Parameter
Vs
Supply voltage
Is
Suppty current
Vs
Supply voltage at which the output
pulses (at pin 2and31are switched off
Test conditions
Min.
10
13~
0
Typ.
Max.
12
13.2
V
40
52
mA
4
V
6
V
Unit
HORIZONTAL SYNC. SEPARATOR AND NOISE GATE
Vi
Peak to peak input signal
Va
Input switching voltage
Is
80.uA
1
1.5
V
Is
Input switching current
Va~1.4V
10
.u A
la
Input blocking current for noise
suppression
0.9
mA
Va
Input switching voltage for noise
suppression
2.1
V
Is
Leakage current
~
Va
~
-5V
496
3
1
.uA
ELECTRICAL CHARACTERISTICS (continuedl
Parameter
Test conditions
Min.
Typ.
Max.
3
6
Unit
VERTICAL SYNC. SEPARATOR
VI
Peak to peak input signal
Vg
Input switching voltage
1
~
Ig
80 IlA
1.5
V
V
Ig
Input switching current
Vg~1AV
Ig
Leakage current
Vg
VIO
Vertical sync. pulse output voltage
No load at pin 10
RlO
Output resistance
10
Kn
tLv
Delay between leading edge of input
and output signals
17
IlS
tTV
Delay between trailing edr,e
of input and output signa s
50
IlS
tv
Vertical sync pulse duration
190
. IlS
~
5
-5V
IlA
1
11
IlA
V
-
PROTECTION CIRCUIT
V4
Input voltage for switching off the
output pu Ises
R4
Input resistance
14
Input current
Output pulses OFF
Output pulses ON
0.5
1
200
V
Kn
5
IlA
fL YBACK PULSE
V6
., Input threshold
voltage of blanking
V6
Input threshold voltage of phase
comparator
16
Input switching current
V
1.5
generator
V6~1.7V
7.6
V
0.23
mA
OUTPUT PULSE
~
V3
Peak to peak output voltage
13
13
Output current
V3
R3
Output resistance
at leading edge of output pulse
3
at trailing edge of output pulse
20
tp
150 mApp
~
5V
Output pulse duration
20
10
V
500
mA
22
n
26
IlS
4.8
V
COMPOSITE BLANKING AND KEY PULSE
V 7K
V 78
Key pulse output peak voltage
. Blanking pulse output voltage
9
11
4.2
4.5
V
R7
Output res ista nce
100
n
t5K
Phase relation between trailing
edge of key pulse and middle of
sync input pulse
2.7
IlS
tK
Key pulse duration
tfb
Delay between flyback pulse and
blanking pulse
3.5
V6~1.7V
497
3.8
IJ.S
0.2
IJ.S
I
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
INTERNAL GATING PULSE
tg
Gating pulse duration
t
Phase relation between middle of
sync pulse and trailing and leading
edge of gating pulse
7.5
flS
3.75
flS
COINCIDENCE DETECTOR
V ll
Output voltage
6.S
with coincidence
4
without coincidence
III
Peak output current
0.5
V
mA
VCR SWITCH
o to 4 or 8.5 to
Vll
Input voltage
-Ill
Output cu rrent
35
1
III
Output current
0.4
1
12
I
V
flA
I.
mA
TIME CONSTANT SWITCH
V 12
Output voltage
R12
Output resistance
4.5V
V ll
< V ll < SV
> S.5V or V ll < 4V
3
V
100
n
Kn
40
OSCILLATOR
V 14
Low level threshold voltage
5.4
V
V 14
High level threshold voltage
Charge current
S.2
0.6
V
mA
0.3
mA
114
114
Discharge current
V 15
Current source supply voltage
3
V
115
Current source supply current
0.3
mA
15625
Hz
± 10
%
fo
Mo
-fo
fd o
Free running frequency
Adjustment range
Frequency control sensitivity
Mo
Hz
52
tJl5
Frequency change when V s drops
t04V
-,;A
± 10
498
%
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
OSCILLATOR-FL YBACK PULSE PHASE COMPARATOR
V5
Control voltage range
15
Peak control current
15
I nput current (blocked phase
detector)
td
Permissible delay between output
pulse leading edge and fly back pulse
lead ing edge
6t
6td
9.4 to 8.2
V
± 0.5
mA
5
IlA
tp - tf
Static control error
IlS
0.2
%
SYNC PULSE-OSCILLATOR PHASE COMPARATOR
V13
Control voltage range
4.6 to 1.4
V
113
Control peak current
±2
mA
M6t
Phase lock loop gain
2
KHz
-IlS
± 700
Hz
Phase relation between middle of
flyback pulse and middle of sync
pulse
2.6
IlS
Adjustment sensitivity
65
mV
-IlS
Adjustment sensitivity
10
~
f
Catching and holding range
OVERALL PHASE RELATIONSHIP
to
6V 5
--6to
61 5
-6to
499
IlS
Fig. 1 - Vertical sync. output pulse
I
f
tv
Fig. 2 - Relationship of main waveform phases
I
\
FLVBACK
INPUT PULS
~
"
1
lo-
,J
VIDEO IN PUT
SIGNAL
\..
PHASE COM PARATOR
r
I
DRIVING PU lSE
SEPARATED
SYNC. PU lSE
I
\
'9
GATE PUlS
I
I
---"'---
SANDCASTL E
OUTPUT PU lSE
I
.--
I
I
I
I
'SK
'K
v"
\ [v's
'p
OuTPUT PULSE
PIN
J
S-3~3"l
500
Fig. 3 - Free running fre·
quency vs. supply voltage
(k~~) H-+-H--t--r--t+-t-i-f'+-1-++-1
+-++-+-++++--+-++-H
,
,
--t
H--f-f'-+1-t-[--j--l-+-+-+-+-+-+-+-I
-i---
+-+-+-+-++-1-+ T
+-'
,
I
5
15.5
Fig. 5 - Loop gain
Fig. 4 - Overall phase relation vs. supply voltage
J
,
(,-)597
(,-)';96
I
I
rLSYNC
t:I::
~t
•
. : l'
If
+
~~+
-+
PULSE
~LVBA.CK
-
PULSE
-tFF
,
~
,
--
,
f
I
H=-0.8
-0.0
-04
I
-0.2
APPLICATION INFORMATION
Pin 1 - Positive supply
The operating supply voltage of the device ranges from 10V to 13.2V.
Pin 2 and 3 - Output
The outputs of TDA 1180P are suitable for driving transistor output stages, they deliver positive pulse at
pin 3 and negative pulse at pin 2.
The negative pulse is used for direct driving of the output stage, while positive pulse is useful when a
driver stage is required.
The rise and fall times of the output pulses are about 150 ns so that interference due to radiation are
avoided.
Furthermore the output stages are internally protected against short circuit.
Pin 4 - Protection circuit input
By connecting pin 4 of the Ie to earth the output pulses at pin 2 and 3 are shut off; this function has
been introduced to protect the final stages from overloads.
The same pulses are also shut off when the supply voltage falls below 4V.
Pin 5 - Phase shifter filter
To compensate for the delay introduced by the line final stages, the flyback pulses to pin 6 and the oscillator waveform are compared in the oscillator-flyback pulse phase comparator.
The result of the comparison is a control current which, after it has been filtered by the external capacitor connected to pin 5, is sent to a phase shifter which adequately regulates the phase of the output
pulses.
The maximum phase shift allowed is:
where tl is the flyback pulse duration.
Pin 5 has high input and output resistance (current generator).
501
APPLICATION INFORMATION (continued)
Pin 6 - Flyback input
The fly back pulse drives the high impedance input through a resistor in order to limit the input current
to suitable maximum values.
The flyback input pulses are processed by a double threshold circuit; this generates the blanking pulses
by sensing low level flyback voltage and the pulses to drive the phase comparator by sensing high level
flyback voltage, therefore phase jitter caused by ringing normally associated with the flyback pulse, is
avoided.
Pin 7 - Key and blanking pulse output
The key pulse for taking out the burst from the chrominance signal is generated from the oscillator
ramp and has therefore a fixed phase position with respect to the sync.
The key pulse is then added internally to the blanking pulse obtained by correctly forming the flyback
pulse present at pin 6.
The sum of the two signals (sandcastle pulse) is available on low impedance at output pin 7.
Pin 8 and 9 - Sync separators inputs
The video signal is applied by means of two distinct biasing networks to pins 8 and 9 of the Ie and
therefore to the respective vertical and horizontal sync separators.
The latter take the sync pulses out of the video signal and make them available to the rest of the circuit
for further processing.
An amplitude detector also connected to pin 8, blocks operation of the sync separators when interference or noise peaks exceed a certain preset value.
Pin 10 - Vertical sync output
The vertical sync pulse, obtained by internal integration of the synchronizing signal, is available at this
pin.
The output impedance is typically 10Kn and the lowest amplitude without load is 11 V.
Pin 11 - Coincidence detector
From the oscillator waveform a gate pulse 7 p,s wide is taken whose phase position is centered on the
horizontal syncronism.
The gate pulse not only controls a logic block which permits the sync to reach the oscillator-sync phase
comparator only for as long as its duration, but also allows the latching and de-latching conditions of
the oscillator to be established.
This function is obtained by a coincidence detector which compares the phase of the gate pulses with
that of the sync.
When the two signals are not accurately aligned in time It means that the oscillator is not synchronized.
In this case the detector acts on the logic block to eliminate its filtering effect and on the time constant
switching block to establish a high impedance on pin 12 (small time constant of low-pass filter).
Th is latter block also acts on the oscillator-sync phase detector to increase its sensitivity and with it the
loop gain of the synchronizing system.
In this conditions the phase lock has low noise immunity (wide equivalent noise bandwidth) and rapid
pull-in time which allows fairly short synchronization times.
502
APPLICATION INFORMATION (continued)
Once locking has taken place the coincidence detector enables the logic block, causes a low impedance
on pin 12 and reduces the sensitivity of the phase comparator.
In these conditions the phase lock has high noise immunity (narrow equivalent noise bandwidth) due to
the complete elimination of interference which occurs during the scanning period and the greater inertia
with which the oscillator can change its frequency.
To optimize the behaviour of the Ie if a video recorder is used, the state of the detector can be forced
by connecting pin 11 to earth or to +Vs. The characteristics of the phase lock thus correspond to the
lack of synchronization.
Pin 12 -:- Time constant switch, (see pin 11)
Pin 13 - Control current output
The oscillator is synchronized by comparing the phase of its waveform with that of the sync pulses in
the oscillator-sync phase comparator and sending its output current 113 (proportional to the phase difference between the two signals) to pin 15 of the oscillator after it has been filtered properly with an
external low-pass circu it.
The time constant of the filter can be switched between two values according to. the impedance presented by pin 12.
The voltage limiter at the output of the phase comparator limits the voltage excursion on pin 13 and
therefore the frequency range in which the oscillator remains held-in.
The output resistance of pin 13 is :
low when V 13 > 4.3V or V 13 < 1.6V
high when 1.6V < V 13 < 4.3V
Tb prevent the vertical sync from reaching the oscillator-sync phase comparator along with the horizontal sync, a signal which inhibits the phase detector during the vertical interval is taken from the
vertical output stage; inhibition remains even if the video signal is not present.
The free running frequency of the oscillator is determined by the values of the capacitor and of the
resistor connected to pins 14 and 15 respectively.
To generate the line frequency output pulses, two thresholds are fixed along the fall ramp of the triangular waveform of the oscillator.
Pin 14 - Oscillator (see pin 13)
Pin 15 - Oscillator control current input (see pin 13)
Pin 16 - Ground
503
Fig.6 - Application circuit for large screen b.w. and colour TV
SANDCASTLE
OUTPUT
A
.v,
ll
FlYBACK
INPUT (IOOV)
PHASE
Fig. 7 - p.e. board and component layout for the circuit in fig. 6 (1: 1 scale)
FLYBACK
INPUT(lOOV)
Vs
OUTPUT
PULSE
504
Fig.8 - Application circuit for small screen b.w. TV.
.10.1\'
SANDCA51lE
OUTPUT
]l
A
I
1511
FLYBACK
INPUT(100V)
.V s
470nF
C1
R1
R8
47
n'1fi
kfl
r--:':,0:----:---~----:---.......- - -...--,
f---"'---'
9
2.2kfl
TDA 1180P
VIDEO SIGNAL
INPUT
16
C9
5nF
5-31.33/1
Fig.9 :.' Application circuit for Darlington output stage
SANOCASTlE
OUTPUT
]l
A
FLYBACK
I NPUTi 100v)
R8
47
IOO"F
J:
kfl
r-~----~--~~--~----~----~-'
10
fl
TDA 1180P
VIDEO SIGNAL
INPUT
16
C9
5nF
5-31,34/1
505
Bue060r
BUB07
82
LINEAR INTEGRATED CIRCUIT
COMPLETE TV SOUND CHANNEL
The TDA 1190Z is a monolithic integrated circuit in a 12-lead quad in-line plastic package. It performs
all the functions needed for the TV sound channel:
I F limiter-amplifier
- Active low-pass filter
- FM detector
- DC volume control
- AF preamplifier
- AF output stage
The TDA 1190Z can give an output power of 4.2W (d = 10%) into a 160 load at Vs = 24V, or 1.5W
(d = 10%) into an 80 load at Vs = 12V. This performance, together with the FM-IF section characteristics of high sensitivity, high AM rejection and low distortion, enables the device to be used in
almost every type of television receivers.
The device has no irradiation problems, hence no external screening is needed.
ABSOLUTE MAXIMUM RATINGS
Supply voltage (pin 10)
Input signal voltage (pin 1)
Output peak current (non-repetitive)
Output peak current (repetitive)
Power dissipation: at T tab = 90°C
at T amb = 80° (free air)
Storage and junction temperature
ORDERING NUMBER:
V
1
V
A
A
2
1.5
5
1
-40 to 150
W
W
°C
TDA 1190Z
Dimensions in mm
MECHANICAL DATA
6/82
28
506
CONNECTION AND BLOCK DIAGRAM
(top view)
I;
"
~-
SCHEMATIC DIAGRAM
TABS
507
TEST CIRCUIT
L1
L= 10,.,H
Q o =60
10=4.5 MHz
9pF
C7
C6
0
I
~
120pF
INPUT
lOOnrJ:
C12
C10
J----0..C~
.' . .
,.,'.,,<: .•. ~
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~
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u...
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(S
tl
S
:..'. .......
. •. F:~ ............
, Rl3
..Q
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....0
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~
:::l
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'':;
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co
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...
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CS-0117
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u...
524
FM
APPLICATION INFORMATION
(continued)
Low cost receiver performance (V s = 9V)
I!
Test conditions
Parameter
Value
I
I.
Wavebands
Sensitivity
Distortion f m : 1 KHz
~
fm:1KHz
·N
FM
87.5 -;. 108 MHz
AM
510-;. 1620 KHz
FM : 75.11 (S + N/N) : 26 dB
(S + N/N) : 6 dB
m: 0.3
1 jJV
AM
(S + N/N) : 26 dB
m: 0.3
10 jJV
FM
Vi:
100jJV
M: 22.5 KHz
p: 0.5W
.;; 0.25 %
FM
Vi:
100jJV
M: 75 KHz
p: 0.5W
.;; 1 %
AM
Vi:
100jJV
m: 0.3
p: 0.5W
.;; 0.6 %
AM
Vi:
100jJV
m: 0.8
p: 0.5W
.;; 1 %
FM
Vi:
100jJV
M: 22.5 KHz
p: 0.5W
;. 70dB
AM
Vi: 1000jJV
m: 0.3
p: 0.5W
FM
-3 dB point
AMR
FM
Vi: 100jJV
Quiescent current
Supply voltage range
.;; 2 jJV
AM
Input limiting voltage
IF
I1f: 22.5 KHz
;. 55 dB
.;; 1.5jJV
M: 22.5 KHz
m: 0.3
;. 45 dB
FM
10.7 MHz
AM
460 KHz
FM
23mA
AM
15 mA
FM
3-;.12V
AM
3-;.12 V
525
J; "'
·H~
• ~\>
:
,
~~
I
0
l
,
I
,I
,
,
I
j~
I
"~
13::J
C
.;::;
C
0
.::.
.2
Q
"0
«
:2E
:;§;
I-
a:
0
~
I
u.
Z
S
en
Z
S
!;;:
S
-l
LL
0
:;§;
(J
I
...I
N
N
Q.,
Q.,
«
~
I
~
~
!. i
I
z
I
.",
u.
526
0
APPLICATION INFORMATION (continued)
Fig. 23 - PC board and component layout of the four band radio (fig. 22)
C11
I'.)
-..J
~
I
mm205
i
~I
I
----...
----.-.......-..-
APPLICATION INFORMATION (continued)
FOUR BAND RADIO PERFORMANCE
Parameter
AM SECTION
Values
Test. conditions
H
I~I
N
BW
Distortion
Vi = 10"V
V i - l mV
-3 dB
V I = 20 "V
Vi -100"V
VI 1 mV
Vi 20"V
Vi 1 mV
m =0.3
m - 0.3
Vi- 30"V
V i -l00"V
V i - 10"V
V i - 1OO ILV
V i - l mV
V I - 10ILV
V i -l00"V
Vi
10"V
V i -l00"V
Vi -1 mV
M = 22.5
b.f - 22.5
M - 22.5
b.f - 22.5
b.f - 22.5
M-75
M-75
M - 22.5
M - 22.5
b.f - 22.5
26 dB
55 dB
10 KHz
0.5 %
0.5 %
0.5 %
0.9 %
1%
m = 0.3
m - 0.3
m 0.3
m 0.8
m 0.8
FM SECTION
AMR
Distortion
I~I
N
Input limiting
voltage
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
m - 0.3
m -0.3
f m = 1 KHz
f m - 1 KHz
-3 dB
45 dB
47 dB
0.3 %
0.2 %
0.2 %
1%
1%
60dB
70dB
70dB
l"V
(.j The performance remains substantiallv the same over LW, MW and SW bands.
100 KHz/div.
5 KHz/div.
Fig. 24 - FM-SECTION
S cu rve response
Fig. 25 - AM-SECTION
Band pass IF filter response at AGC
starting point.
528
..
APPLICATION INFORMATION (continued)
Fig. 26 - Low cost 27 MHz receiver
·9V
I,
TDA 1220 A
111----'-.......-+-----,
16
Sensitivity: 1O!J. V for ( S ~ N )
= 26 dB
Fig. 27 - PC board and component layout of
the low cost 27 MHz receiver (1: 1 scale)
AUDIO
OUT
Fig. 28 - L2 Oscillator Coil
I
00
+9V
«XX>
0000
0000
I r--II
I:
I
I
I
IL __ _
!
5-3419
Coil support: Taka 10K.
Primary winding: 10 Turns of enamelled copper wire 0.16 mm diameter (pins 3-1).
Secondary winding: 4 Turns copper wire
0.16 mm diameter (pins 6-4).
I:
Fig. 29 - L 1 Antenna Coil
j---
00)
«XX>
0000
I:I
I
I:
I
NOTE - For a more detailed description of the TDA 1220A and
its applications refer to SGSTECHNICAL NOTE TN. 14B.
-~~3~18
Coil support: Taka 10K.
Primary winding: as L2 (pins 3-1)
Secondary winding: 2 Turns copper wire
0.16 mm diameter (pins 6-4).
529
Ji
LINEAR INTEGRATED CIRCUIT
AM-FM QUALITY RADIO
The TDA 1220B is a monolithic integrated circuit in a 16-lead dual in-line plastic package designed as
an improved version of the TDA 1220A.
It is intended for quality receivers produced in large quantities.
The functions incorporated are:
AM SECTION
Preamplifier and double balanced mixer (1)
One pin local oscillator
I F amplifier with internal AGC
Detector and audio preamplifier
The TDA 1220B is suitable up to 30 MHz
and features:
ds (including 450 KHz narrow band)
Very constant characteristics (3V to 16V)
High sensitivity and low noise
Very low tweet
Very high signal handling (1 V)
Sensitivity regulation facility,,(
recovered audio signal (100 mY) suited'
stereo decoders and radio recorders
simple DC switching of AM-FM
Low current drain
''':1)f;'
e
or,
by mean of a resistor (5 to 12 Krl) between pin 4 and ground.
ABSOLUTE
Vs
Ptot
Top
Tstg , Tj •
Supply~ltage
Total po~er dissipation at Tamb
110°C
Operating temperature
Storage and junction temperature
<
16
V
400
mW
-30 to 8 5 ° C
-55 to 150°C
ORDERING NUMBER: TDA 1220B
Dimensions in mm
MECHANICAL DATA
6/82
530
CONNECTION DIAGRAM
LOCAL
OSCILLATOR
16
AM
15
IF FM
'4
IF FM BYPASS
AMPLIFIED
AGG (BYPASS)
i3
FM
DETECTOR
AM IF INPUT
12
FM
DETECTOR
INPUT
MIXER
A~
OUT
DETECTOR
IF FM INPUT
6
GROUND
BYPASS
AM DETECTOR
AGe (BYPASS)
BYPASS
.v 5
10
8
AF
OUTPUT
BLOCK DIAGRAM
- ',
~,--------,. ~-------'---r'6--l-~O.V'
:
:~~-u-~
: -- _
~--- -' ~ I.l : :
I
,
L -
,
-
-
t-.l
,--\
'#
~:
.l.
..,..
I~_"
.....
OUT
---------------"
S-S16611
531
THERMAL DATA
max
Thermal resistance junction-ambient
Rth j-amb
100
ELECTRICAL CHARACTERISTICS (T amb = 25°C, Vs= 9V unless otherwise specified, refer to
test circu it!
Test conditions
Parameter
Vs
Supply voltage
Id
Drain current
AM SECTION(f o
Vi
=
Min.
Typ.
3
Max.
16
10
Unit
V
mA
1 MHz; f m = 1 KHz!
I nput sensitivity
SIN
SIN = 26 dB
m = 0.3
12
Vi = 10mV
m = 0.3
52
dB
100
d8
120
mV
0.4
%
1
V
Vi
AGC eange
llV out = 10dB
m = 0.8
Vo
Recovered audio signal
(pin 9)
Vi = 1 mV
m = 0.3
d< 10%
65
25
IJV
d
Distortion
VH
Max input signal handling
capability
m = 0.8
Rj
I nput resistance between
pins 2 and 4
m=O
7.5
KO
Ci
I nput capacitance between
pins 2 and 4
m-O
18
pF
Ro
Output resistance (pin 9)
Tweet 2 IF
--
Tweet 3 IF
FM SECTION (fo
=
10.7 MHz; f m
m = 0.3
=
Vi = 1 mV
7
KO
38
d8
55
dB
1 KHz!
Vi
Input limiting voltage
-3 dB li""iting point
AMR
Amplitude modulation
rejection
M = ± 22.5 KHz
m = 0.3
22
IJV
52
dB
Vi = 3 mV
SIN
Ultimate quieting
M = + :'2.5 KHz
Vi = 1 mV
64
dB
d
Distortion
M = ± 75 KHz
Vi= 1 mV
0.7
%
d
Distortion
d
Distortion (double tuned)
Vo
0.25
%
0.1
%
100
mV
M = ± 22.5
Vi= 1 mV
Recovered audio signal
(pin 9)
M = ± 22.5 KHz
Vi = 1 mV
Ri
I nput resistance between
pin 16 and ground
M=O
6.5
KO
Ci
I nput capacitance between
pin 16 and ground
M-O
14
pF
Ro
Output resistance (pin 9)
7
KO
532
65
Fig. 1 - Test circuit
I,.
Fig.2 - PC board and component layout (1: 1 scale) of the test circuit.
533
Fig. 3 - Suggestion for 7 x 7 mm "Le" conventional filter use.
TDA 1220 B
13
___
10
AM
FM
.-J
KAC5 K586 HM
Fig.4 - Suggestion for "coil block" use.
SUMIDA FSN 1067
r--~-
'.1
100jJF
L_ - -
'6
--------'"1
2
9
t
/ t
TOKO RWO
6A6574A
'
50h
~)
r-
:
:
6 '
-~- ~3{-.o:---~
~~I---+---~~--c:::}--t
Vs=3 to 12V
I
-.
100 n F
1>----+-----"
-:L.
~
1
~---------: lOll s
Pin 2 D.C. current at V 16 < V 3
Pin 2 peak to peak flyback current for f = 50 Hz, t fly
Pin 11 current
Maximum power dissipation at Tease ~ 75°C
Storage and junction temperature
~
1.5 ms
35
60
+10
-0.5
3
3.5
2
100
3
20
25
-40 to 150
V
V
V
V
A
A
A
mA
A
mA
W
°C
ORDERING NUMBER: TDA 1470
MECHANICAL DATA
6/82
Dimensions in mm
540
CONNECTION AND BLOCK DIAGRAMS
(top view)
POWER GROUND
16
AMP.
FLYBACK
15
NC
OUT
SUPPLY VOLTAGE
14
AMP. SUPPLY
RAMP
OUT
13
REG
RAMP
GENERATOR
VOLTAGE
12
HEIGHT AOJUS T
COMPENSATION
11
SYNC. INPUT
AMP. INPUT
(+)
10
OSCILLATOR
AMP. INPUT
(-)
9
GROUND
The copper slug is electrically
connected to pin 9 (substrate)
SCHEMATIC DIAGRAM
aiD
all
R3
D2
.1
.2
10
01
.6
I,
13
541
THERMAL DATA
Rth j-case
Thermal resistance junction-case
max
3
°C/W
DC ELECTRICAL CHARACTERISTICS (Refer to the DC test circuits, Vs= 35V, T amb = 25°C,
unless otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Fig.
13
Pin 3 quiescent current
12 = 0
7
mA
lb
114
Pin 14 quiescent current
116 = 0
10
mA
1b
-1 10
Oscillator bias current
V 10=1V
0.1
!LA
la
-IS
Amplifier input bias
current
Vs=lV
1
!LA
lb
Ramp generator bias
V5 = OV
0.02
!LA
1a
20
!LA
1b
1
%
1b
35
V
-
1.4
V
-
V
la
-15
current
-15
Ramp generator current
V5= OV
"'15
15
Ramp generator linearity
"'V5= 0 to 12V
112 = 20 !LA
Vs
Supply voltage range(pin3)
V4
Pin 4 saturation voltage
to ground
14= 1 mA
1
V2
Pin 2 saturation voltage
to ground
12= 10 mA
0.5
V 16
Quiescent output voltage
Vs= 10V
R 2 =10 K!1
R I = 10K!1
Vs= 35V
R 2 = 10 K!1
R I = 30 K!1
V I6L
Output saturation voltage
to ground
112= 20 !LA
0.2
10
4.15
4.45
4.73
V
la
8.3
8.9
9.45
V
la
-116= O.8A
1.3
V
lc
-116= 1.5A
1.7
V
lc
542
D.C. ELECTRICAL CHARACTERISTICS
Test conditions
Parameter
Output saturation voltage
to supply
V 16H
V 13
Regu lated voltage at
pin 13
V 12
Regulated voltage at
pin 12
loV 13
nV s
Min.
Typ.
Max.
Unit
Fig.
116 = O.SA
1.9
V
1d
116 = 1.5A
2.3
V
1d
112 = 2O IlA
n V 12 Regulated voltages
lo V s drift
V7
(continued)
6.1
6.5
6.9
V
1b
6.2
6.5
7
V
1b
mV/V
1b
1
nVs= 10 to 35V
Amplifier input reference
voltage
2.07
2.2
2.3
V
Fig. 1 - DC test circuits
(b)
(a)
14
'2
-----111
D.U.T.
1- 9
16
10
~R1
D.U.T.
.....
5-376611
543
S -3 76 7/1
(c)
(d)
.V s
Q
t---- -----14
14
10
10
16
D.U.T.
16
D.UJ.
1-9
i
TABS
I
l__ I_V-±-_
---'-
1V
S -3769/1
S-J 7 6 611
AC ELECTRICAL CHARACTERISTICS (Refer to the AC test circuit f
= 50 Hz, Vs = 24V,
unless otherwise specified)
Parameter
Test cond itions
Min.
Typ.
Max.
Unit
Vs
Operating supply voltage
Iy max= 2.2 App
24
V
Is
Supply current
Iy = 2 App
270
rnA
III
Sync. input current
V I6
Flyback voltage
V IO
Peak to peak oscillator
sawtooth voltage
tflY
Flyback time
Free running frequency
500
Iy = 2 App
IlA
49
V
2.4
V
Iy = 2 App
0.6
ms
Rl +P 1 = 300 Kn
C2 = 100 nF
44
Hz
Rl +P 1 = 260 Kn
C2 =100nF
52
Hz
~.
fo
lit
Synchronization range
I l l = 500 IlA
-litf:,V s
Frequency drift vs. supply
voltage
Vs= 10 to 35V
-lit
--
Frequency drift vs. tab
temperatu re
T amb = 40 to 120°C
f:,T tab
544
14
Hz
0.005
Hz/V
0.01
Hz/oC
Fig. 2 - AC Test circuit
,---------~--------~----~----------------------O·%=24V
YOKE
5.9fl.
lOmH
1
lOOkfi
4
12
5
Linearit
Rl
(2
R6
(4
Hold 220kfl
47kfi
Height
R2
100kil
R3
470
kil
(5
O.1~F
5·3770/1
Fig. 3 - Relative output
voltage drift vs. supply
voltage
_
",('/.J6
,0.
99/1
Fig. 4 - Relative output voltage drift vs. case temperatu re
AV,6 --,---,--,--,--,-,--,-,--,--,""'r~
("!o)--P---_ _....-I
OUTPUT
YOKE
lOA 1470
41-~~0---,
12
5
1000,uF/,6
R3*
680
kfi
* Tolerance 5-/.
** " ,"
S-37731'
2'1,
Typical performance
Vs
Is
tfly
Pd
Iy
23
185
1
2.8
1.4
Operating supply voltage
Supply current
Flyback time
TDA 1470 power dissipation
Maximum scanning current
For safe operation up to T amb = 60°C a heatsink of Rth = 10 °C/W is required.
548
V
mA
ms
W
App
Fig. 9 - P.C. board and component layout (Application circuits of fig. 6, 7 and 8)
SYNC.
INPUT
FLVBACK
OUTPU T
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink as shown in fig. 10.
The system for attaching the heatsink is very simple; it uses a plastic spacer which is supplied with the
device on request (TDA 1470 F2).
Thermal contact between the copper slug (of the package) and the heatsink is guaranteed by the pressure
which the screws exert via the printed circuit board; this is due to the particular shape of the spacer.
Note: The most negative supply voltage is connected to the copper slug, hence to the heatsink (because it is in contact
with the slug).
549
Fig. 10 - Mounting system example (TDA 1470)
HEATSINK
- - - - - - - ; o . r - - R t h " 2\oS'CIW
~/ - + - - - - - S P A C E R
~--",_---P.
550
c.
BOARD
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
VERTICAL DEFLECTION CIRCUIT
The TDA 1670 is a monolithic integrated circuit in 15-lead Multiwatt® package. It is a full performance
and very efficient vertical deflection circuit intended for direct drive of the yoke of 110° colour TV
picture tubes. It offers a wide range of applications also in portable CTVs, BW TVs, monitors and
displays. The functions incorporated are.
Synchronization circuit
Precision osci lIator and ramp generator
Power output amplifier with high current capability
Flyback generator
Voltage regulator
Precision blanking pulse generator
Thermal shut down protection
CRT screen protection circuit which blanks the beam current in the event of loss of vertical deflection current.
I
I
!..
ABSOLUTE MAXIMUM RATINGS
V5
Supply voltage at pin 14
Flyback peak voltage
Sync. input voltage
Vll ,VI2
Power amplifier input voltage
V 13
Voltage at pin 13
Output current (non repetitive) at t = 2 msec
Output peak current at f = 50 Hz t
10 Jisec
Output peak current at f = 50 Hz t';;; 10 Jisec
Pin 15 peak to peak flyback current at f = 50 Hz, t f1y
Pin 15 DC current at VI
V 14
Maximum power dissipation at T case';;; 60°C
Storage and junction temperature
Vs
VI, V 2
10
10
10
'15
'15
Ptot
Tst9' Tj
>
<
.;;;
1.5 msec
35
60
V
V
20
V
{ Vs
-10
Vs
V
3
A
2
A
3.5
A
A
3
100
mA
.30
-40 to 150
°C
W
ORDERING NUMBER: TDA 1670
Dimensions in mm
MECHANICAL DATA
I,
I
551
6/82
CONNECTION DIAGRAM
(top view)
~~
Ay
FLYBACK
SUPPLY
BLANKING OUTPUT
AMPLIFIER INPUT (-)
AMPLIFI ER INPUT (+)
RAMP OUTPUT
RAMP GENERATOR
GROUND
HEIGHT ADJUSTMENT
OSCILLATOR
SYNC. INPUT
OSCILLATOR
OSCILLATOR
AMPLIFIER SUPPLY
AMPLIFIER OUTPUT
131
121
11
10
9
8
7i
'I5,
BLOCK DIAGRAM
,-------~-~--~----~--------~O+vs
BLANKING
OUT
O-----~
14
I
I
Cf
15
JL
SYNC.
Ra
cr'j-----j
5 - S264
552
THERMAL DATA
Rth j-case
Rth j-amb
max
max
Thermal resistance junction-case
Thermal resistance junction-ambient
3
40
ELECTRICAL CHARACTERISTICS (Vs= 35V, T amb = 25°C, unless otherwise specified)
Test conditions
Parameter
DC CHARACTERISTICS
12
Pin 2 quiescent current
11 = 0
18
30
mA
lb
-19
Ramp generator bias
current
V9= 0
0.02
1
p.A
lb
-19
Ramp generator current
V9 =0;
20
21.5
p.A
lb
Ramp generator non
linearity
!lV 9 =Oto15V
-17= 20 p.A
0.2
1
%
lb
25
50
mA
lb
16.8
17.8
18.6
V
7
7.5
8
V
I~I
19
114
Pin 14 quiescent current
VI
Quiescent output voltage
-17= 20 p.A
Vs= 35V;
Rb= 1 Kn
Ra= 2.2 Kn
Vs= 15V;
Ra= 390n
Rb= 1 Kn
18.5
la
V 1L
Output saturation voltage
to ground
11 = 1.2A
1
1.4
V
lc
V 1H
Output saturation voltage
to supply
-11= 1.2A
1.6
2.2
V
ld
V4
Oscillator virtual ground
V
lb
V7
Regulated voltage at pin 7
-17= 20p.A
V
lb
!lVs
Regulated voltage drift
with supply voltage
!lVs= 15 to 35V
Vu
Amplifier input (+)
reference voltage
V 13
Blanking output saturation
voltage
113= 10 mA
0.35
V 15
Pin 15 saturation voltage
to ground
'15= 20mA
1
!lV7
0.45
6.3
7.1
mV
1
4.2
553
6.6
4.4
4.6
1.3
----v-
lb
V
lb
V
la
V
1a
Fig. 1 - DC test circuit
Fig. 1a
Fig. 1b
4
5-5258
Fig. 1d
Fig.1c
554
ELECTRICAL CHARACTERISTICS(Refer to the A.C. test circuit of fig. 2, T amb = 25°C,
Vs= 24V, f = 50 Hz, unless otherwise specified)
Test conditions
Parameter
AC CHARACTERISTICS
Is
Supply current
15
Sync input current
required to sync.
2 App
Iy~
295
mA
100
!LA
vI
Flyback voltage
Iy~
2 App
50
v3
Peak to peak oscillator
sawtooth voltage
15 -
a
3.6
V
15= 100 !LA
V 10th L
Start scan level of the input
ramp
2 App
V
3.4
V
1.85
V
tfly
Flyback time
Iy~
Blanking pulse duration
fo- 50 Hz
T j - 75°C
0.6
1.4
ms
tblank
fo= 60 Hz
T j = 75°C
1.17
ms
Ro- 7.5 K.I1
Co = 330 nF
Tj = 75°C
43.5
Hz
Ro= 6.2 K.I1
Co = 330 nF
Tj
75°C
52.5
Hz
15 - 100 !LA
T j - 75°C
Free running frequency
fo
lit
Synchronization range
Tj
Junction temperature for
thermal shut-down
~
ms
16
Hz
145
°C
Fig.2 - AC test circuit
t blank
II
Jl
J11![
BLANKING
OUT
SYNC. IN
YOKE
lLt sync .
5.9
II
A
t blank
- ---i- 4'7:n.(FREa~0~:
~
__
__
I
10mH :
TDA 1670
_
lito
3 i 7180
_
v3
~~
SERVICEl
SWITCH
S2
5-5260
~'
220
K Jl
2200
O.l}JF9
KJl
56KJl
560
KII
r-,--~~L-r
J~>F
HEIGHT
555
L -_____
--~~~J~tly
:~
Fig. 3 - Application circuit for small screen 90° Tve set (Ry= 15,n; Ly= 30 mH, Iy= 0.82 App)
+vs
1N4001
R3
10K Jl
BLANKING
OUT
~G~~E
IN
01~F
13
Oc,1
S
14
"
TDA 1670
19~~\
15
Q ~F
R9
2.2
C7
::I:
n.
0.22
2.4KJl
:
Rl1
I
330Jl :
1
I
I
I!
1
1
L _ _ _ .J
Co
R2
1SKJl
SERVICE
SWITCHJS1
~
RT1
HEIGHT
S - 5261
* The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Vs
Is
t fly
t blkg
fo
Ptot
Rth heatsink
Minimum supply voltage
Supply current
Flyback time
Blanking time
Free running frequency
Power dissipation
Thermal resistance of the heatsink
for T amb = 600 e and T j max= 1100 e
for T amb = 600 e and T j max= 1200 e
556
25
140
0.7
1.4
43.5
V
mA
msec
msec
Hz
2.4
W
13
16
°e/w
°e/W
Fig. 4 - Application circuit for 110° TVC set (Ry= 9.6n; Ly= 27 mH; Iy= 1.17 App)
BLANKING
OUT
,J
"
YOKE
14
r - --,
5
I
I
Ii
TDA 1670
Co
s-
•
5262
The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Vs
Is
t f1y
t b1kg
fO
Ptot
Rth heatsink
Minimum supply voltage
Supply current
Flyback time
Blanking time
Free running frequency
Power dissipation
Thermal resistance for the heatsink
for T amb = 60°C and T j max= 110°C
for Tamb = 60°C and T j max= 120°C
557
22.5
185
1
1.4
43.5
V
mA
msec
msec
2.7
Hz
W
11.5
14.5
°C/W
°C/W
Fig. 5 - Application circuit for 110° TVC set (Ry= 5.90; Ly= 10 mH; Iy= 1.95 App)
1N4001
+Vs
R3
10KA
BLANKING
OUT
~0~~E
IN
01!-1F
0y,J
13
5
14
"
YOKE
15
r - --.,
:
~-~------~~~~
TDA1670
1\
5 - 5263
*
The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Vs
Is
tfly
t b1kg
fo
Ptot
Rth heatlnk
Minimum supply voltage
Supply current
Flyback time
Blanking time
Free running frequency
Power dissipation
Thermal resistance of the heatsink
for T amb = 600C and TJ max= 1100C
;or T amb = 600C and Tj max= 1200C
558
24
285
0.6
1.4
43.5
4.3
V
rnA
msec
msec
Hz
W
6.5
8.5
°CIW
°CIW
Fig. 6 - PC board and components layout for the application circuits of fig. 3, 4 and 5 (1 : 1 scale)
GND
SYNC. Iy
I N TEST
APPLICATION INFORMATION (Refer to the block diagram)
Oscillator and Sync gate (Clock generation)
The oscillator is obtained by means of an integrator driven by a two threshold circuit that switches Ro
high or low so allowing the charge or the discharge of Co under constant current conditions.
The Sync input pulse at the Sync gate lowers the level of the upper threshold and than it controls the
period duration. A clock pulse is generated.
Pin 4
Pin 6
Pin 3
Pin 5
is
is
is
is
the
the
the
the
inverting input of the amplifier used as integrator.
output of the switch driven by the internal clock pulse generated by the threshold circuits.
output of the amplifier.
input for sync pulses (positive)
559
Ramp generator and buffer stage
A current mirror, the current intensity of which can be externally adjusted, charges one capacitor producing a linear voltage ramp.
The internal clock pulse stops the ramp increasirg by a very fast discharge of the capacitor; a new
voltage ramp is immediately allowed.
The required value of the capacitance is obtained by means of the series of two capacitors, Ca and Cb,
which allow the linearity control by applying a feedback between the output of the buffer and the
tapping from Ca and Cb.
Pin 7
Pin 9
Pin 10
The resistance between pin 7 and ground defines the current mirror current and than the height
of the scanning.
is the output of the current mirror that charges the series of Ca and Cb. This pin is also the
input of the buffer stage.
is the output of the buffer stage and it is internally coupled to the inverting input of the power
amplifier through R 1.
Power amplifier
This amplifier is a voltage-to-current power converter, the transconductance of which is externally
defined by means of a negative current feedback.
The output stage of the power amplifier is supplied by the main supply during the trace period, and by
the flyback generator circuit during the most of the duration of the flyback time. The internal clock
turns off the lower power output stage to start the flyback.
The power output stage is thermally protected by sensing the junction temperature and then by putting
off the current sources of the power stage.
Pin 12
Pin 11
Pin 1
Pin 2
is the inverting input of the amplifier. An external network, Ra and Rb, defines the DC level
across Cy so allowing a correct centering of the output voltage. The series network Rc and Cc,
in conjunction with Ra and Rb, applies at the feedback input pin 12 a small part of the parabola, available across Cy, and the AC feedback Voltage, taken across Rf. The external components Rc, Ra and Rd, produce the linearity correction on the output scanning current Iy and
their values must be optimized for each type of CRT.
is the non-inverting input and it is not used. At this pin the non-inverting input reference
voltage supplied by the voltage regulator can be measured.
This pin is only used on a quasi-bridge configuration.
is the output of the power amplifier and it drives the yoke by a negative slope current ramply.
Re and the Boucherot cell are used to stabilize the power amplifier.
The supply voltage of the power output stage is forced at this pin. During the trace time the
supply voltage is obtained from the main supply voltage Vs by a diode, while during the retrace
time this pin is supplied from the flyback generator.
Flyback generator
This circuit supplies both the power amplifier output stage and the yoke during the most of the duration
of the flyback time (retrace).
The internal clock opens the loop of the amplifier and lets pin 1 floating so allowing the rising of the
flyback. Crossing the main supply voltage at pin 14, the flyback pulse front end drives the flyback
560
generator in such a way allowing its output to reach and overcome the main supply voltage, starting
from a low condition forced during the trace period.
An integrated diode stops the rising of this output incrl:ase and the voltage jump is transferred by means
of capacitor Cf at the supply voltage pin of the power stage (pin 2).
When the current across the yoke changes its direction, the output of the flyback generator falls down to
the main supply voltage and it is stopped by means of the saturated output darlington at a high level.
At this time the flyback generator starts to supply the power amplifier output stage by a diode inside
the device. The flyback generator supplies the yoke too.
Later, the increasing flyback current reaches the peak value and then the flyback time is completed:
the trace period restarts. The output of the power amplifier (pin 1) falls under the main supply voltage
and the output of the flyback generator is driven for a low state so allowing the flyback capacitor Cf
to restore the energy lost during the retrace.
Pin 15
is the output of the flyback generator that, when driven, jumps from low to high condition. An
external capacitor Cf transfers the jump to pin 2 (see pin 2).
Blanking generator and CRT protection
This circuit is a pulse shaper and its output goes high during the blanking period or for CRT protection.
The input is internally driven by the clock pulse that defines the width of the blanking time when a
flyback pulse has been generated. If the flyback pulse is absent (short circuit or open circuit of the yoke),
the blanking output remains high so allowing the CRT protection.
Pin 13
is an open collector output where the blanking pulse is available.
Voltage regulator
The main supply voltage Vs is lowered and regulated internally to allow the required reference voltages
for all the above described blocks.
Pin 14
Pin 8
is the main supply voltage input Vs (positive).
is the GND pin or the negative input of Vs.
Fig. 7 - Output saturation
voltage to ground vs. peak
output cu rrent
Fig. 8 - Output saturation
voltage to supply vs. output
peak current
Fig. 9 - Maximum allowable
power dissipation vs. am·
bient temperature
Pto
t
{WI
32
28
"20
I.
7'1-
O"BlO
~
'l(1~n
'%
~,,~c;..-I$.
"<.
I?,!~~
tJ,'8t'~
'\<-v,
-
'I'~
12
o
1.5
iyCAp)
'5
1.5
561
ly(Ap)
-so
'0
100 Tamb(-cJ
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the MUL TIWATT® package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon
grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces.
Fig. 10- Mounting example
562
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
VERTICAL DEFLECTION CIRCUIT
The TDA 1770 is a monolithic integrated circuit in 20-lead plastic package. It is a full performance and
very efficient vertical deflection circuit intended for direct drive of the yoke.
It offers a wide range of applications in portable CTVs, BW TVs, monitors and displays. The functions
incorporated are:
synchronization circuit.
precision oscillator and ramp generator
power output amplifier
fly back generator
voltage regulator
precision blanking pulse generator
thermal shut down protection
CRT screen protection circuit which blanks the beam current in the event of loss of vertical deflection current.
The TDA 1770 is assembled in a new 20-lead plastic package which has 4 centre pins connected together
and used for heatsinking.
ABSOLUTE MAXIMUM RATINGS
Vs
V7 , Va
V ll
V 19 , V 20
35
Supply voltage at pin 2
Flyback peak voltage
Sync. input voltage
Power amplifier input voltage
60
Voltage at pin 1
Output current (non repetitive) at t = 2 msec
Output peak current at f = 50 Hz t
10 J,1sec
Output peak current at f = 50 Hz t .;;; 10 J,1sec
Pin 3 peak to peak flyback current at f = 50 Hz, t f1y
Pin 3 DC current at V 7
V2
Maximum power dissipation: at T Pins';;; 90°C
at Tamb = 70°C
Storage and junction temperature
20
{ Vs
-10
Vs
2
>
<
2
50
rnA
2.2
1.5 msec
V
A
A
A
A
1.2
.;;;
V
V
V
4.3
W
1
-40 to 150
W
°C
ORDERING NUMBER: TDA 1770
MECHANICAL DATA
Dimensions in mm
563
6/82
CONNECTION DIAGRAM
(top view)
BLANKING OUTPUT
AMPliFIER INPUT(-)
SUPPLY (+)
AMPLIFIER INPUT(+)
RAMP
FLVBACK
RAMP GENERATOR
N.C
GROUND
GROUND
GROUND
GROUND
AMPLIFIER OUTPUT
7
AMPLIFIER SUPLLY
8
HEIGHT
ADJUST.
N.C.
OSCILLATOR
OSCILLATOR
OSCILLATOR
OUTPUT
11
10
SYNC. INPUT
s- 5265
BLOCK DIAGRAM
c-------------~r---1r----~------~--------------O.vs
:r
BLANKING
OUT
LCJ-t-!=:J--l---+-I'Ol-fI- ~
,.j",
"
5- 5280
564
THERMAL DATA
Rth
j-pins
Rth j-amb
max
max
Thermal resistance junction-pins
Thermal resistance junction-ambient
14
80
°C/W
°C/W
ELECTRICAL CHARACTERISTICS (Vs= 35V, Tamb = 25°C, unless otherwise specified)
Parameter
Test conditions
DC CHARACTERISTICS
12
Pin 2 quiescent current
Is
Pin 8 quiescent current
-117
Ramp generator bias
. current
50
mA
lb
18
30
mA
lb
0.02
1
JJ.A
la
20
21.5
JJ.A
lb
0.2
1
%
lb
V
lb
la
30
17= 0
V 17= 0
Ramp generator current
V 17 = 0;
Ramp generator non
linearity
LW17= 0 to 15V
-114= 20 JJ.A
VI
Blanking output saturation
voltage
11= 10 mA
0.35
V3
Pin 3 saturation voltage
to ground
13= 20 mA
1
1.3
V
V7
Quiescent output voltage
Vs= 35V;
Rb= 1 Kn
Ra= 2.2 Kn
16.8
17.8
18.6
V
Vs= 15V;
Ra= 390n
Rb= 1 Kn
7.1
7.5
8
V
-117
I t.l17 I
117
-114= 20JJ.A
18.5
la
V 7L
Output saturation voltage
to ground
17= 0.7A
0.7
1
V
lc
V7H
Output saturation voltage
to supply
-17= 0.7A
1.3
1.8
V
ld
V IO
Oscillator virtual ground
V
la
V14
Regulated voltage at pin 14
-114= 20 JJ.A
V
lb
Regulated voltage drift
with supply voltage
L1Vs= 15 to 35V
L1VI4
L1Vs
VI 9
0.45
6.3
Amplifier input (+)
reference voltage
7.1
mV
1
4.2
565
6.6
4.4
4.6
V--
lb
V
lb
Fig. 1 - DC test circuit
71-_.-----,
:) - 5281
Fig. lb
Fig.la
+Vs
+Vs
1+ 17
lV-.c-
I
7
10
lV
20
8V....L
I
S - 5283
f"
I
10
S -- 528.
Fig.ld
Fig.lc
566
ELECTRICAL CHARACTERISTICS (Refer to the A.C. test circuit of fig. 2, Vs= 20V, f= 50 Hz,
T amb = 25°C, unless otherwise specified)
Test conditions
Parameter
AC CHARACTERISTICS
Iy~
1 App
Is
Supply current
III
S·Ync. input current
V7
F Iyback voltage
Iy~
Vg
Peak to peak oscillator
sawtooth voltage
III ~
1 App
V
3.6
V
III ~ 100 /LA
3.4
V
tfly
Flyback time
Iy~
1 App
tblank
Blanking pulse duration
fo~
fo~
1.85
V
0.75
msec
50 Hz
1.4
ms
60 Hz
1.17
ms
7.5 K!1
330 nF
43.5
Hz
6.2 K!1
330 nF
52.5
Hz
Ro~
Free running frequency
Co~
Ro~
Co~
Ill~
lit
Synchronization range
Tj
Junction temperature for
thermal shut-down
/LA
a
Start scan level of the
input ramp
-
mA
42
V 18th L
fo
160
100
100/LA
16
Hz
145
DC
Fig. 2 - AC test circuit
+Y's
tblank
...,-y-
Jl
~12 2O,uF
1N4001
O}'-~~~~~~---'O~-+--r-r---'+--'1Jrl25 V
25~70
2.2 KIL
:cpr:c
BLANKING
O~._~~~~~
-D?ir o
...J2 1,fJ F
,i
,
'I'
'I'
"
,'I
SVNC.IN
11
YOKE
20mH
~~-o~~~--j12
sync
5-5285
7.5 Kil
TDA 1770
l.
HEIGHT
567
I
I
Fig. 3 - Typical application circuit for small screen 90° TVC set (Ry= 155); Ly= 30 mH; Iy= 0.82 App)
19
I!
TDA1770
14
17
~J~!5'I'R4~'* ~r- -~.ik l~F
Co
*
lNi
SERVICE
SWITCH }Sl
~
•
RT1
220
Kfl
HEIGH1.
RS }56Kfl
390
Kfl
*(6 R6
:E'~F
S
5286
The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Vs
Is
t fly
t blkg
fo
Ptot
Rth heatsink
**
Minimum supply voltage
Supply current
Flyback time
Blanking time
Free running frequency
Total dissipation
Thermal resistance of the heatsink
for T amb = 60°C and T j max= 130°C
See "Thermal considerations" .
568
25
140
0.7
1.4
43.5
2.4
V
mA
msec
msec
Hz
W
8
°C/W
Fig.4 - Typical application circuit for B/W TV set (Ry= 100; Ly= 20 mH; Iy= 1 App)
01
RJ
BLANKING
10Kfl
OUT
:....-------1
3
19
7
R9
TDA 1770
SERVICE
SWITCH
6
15
2.2!l
1
.J...
* The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Vs
Is
t f1y
t b1kg
fa
Ptot
Rth heatsink
**
Minimum supply voltage
Supply current
Flyback time
Blanking time
Free running frequency
Power dissipation
Thermal resistance of the heatsink
for T amb = 60°C and Tj max= 1300C
See "Thermal considerations".
569
20
160
0.75
1.4
43.5
2.1
V
mA
msec
msec
Hz
W
11
°C/W
Fig. 5 - Typical application circuit for small screen (Ry= 2.9n; Ly= 6 mH; Iy= 1.1 App)
1 N40Ql
R3
BLANKING
lOKil
OUT
::)----------~
Co
•
The value depends on the characteristics of the CRT. The value shown is indicative only.
Typical performance
Minimum supply voltage
Supply current
Flyback time
tfly
t b1kg
Blanking time
Free running frequency
fo
Ptot
Power dissipation
Rth heatsink * * Thermal resistance of the heatsink
for T amb = 60°C and T j max= 130°C
Vs
Is
See "Thermal considerations".
570
10.5
170
0.45
1.4
43.5
1.25
mA
msec
msec
Hz
28
°C/W
V
W
Fig. 6 - PC board and components layout for the application circuits of fig. 3, 4 and 5 ( 1: 1 scale)
GND
BLKG
or
vs
YOKE
Iy TEST
s·a:C.IN
GND
APPLICATION INFORMATION (Refer to the block diagram)
Oscillator and Sync gate (Clock generation)
The oscillator is obtained by means of an integrator driven by a two threshold circuit that switches Ro
high or low so allowing the charge or the discharge of Co under constant current conditions.
The Sync input pulse at the Sync gate lowers the level of the upper threshold and than it controls the
period duration. A clock pulse is generated.
Pin 10
Pin 12
Pin 9
Pin 11
is
is
is
is
the
the
the
the
inverting input of the amplifier used as integrator.
output of the switch driven by the internal clock pulse generated by the threshold circuits.
output of the amplifier.
input for sync pulses (positive).
Ramp generator and buffer stage
A current mirror, the current intensity of which can be externally adjusted, charges one capacitor producing a linear voltage ramp.
The internal clock pulse stops the ramp increasing by a very fast discharge of the capacitor; a new
voltage ramp is immediately allowed.
The required value of the capacitance is obtained by means of the series of two capacitors, Ca and Cb,
which allow the linearity control by applying a feedback between the output of the buffer and the
tapping from Ca and Cb.
Pin 14
Pin 17
Pin 18
The resistance between pin 7 and ground defines the current mirror current and than the height
of the scanning.
is the output of the current mirror that charges the series of Ca and Cb. This pin is also the
input of the buffer stage.
is the output of the buffer stage and it is internally coupled to the inverting input of the power
amplifier through R 1.
571
APPLICATION INFORMATION (continued)
Power amplifier
This amplifier is a voltage-to-current power converter, the transconductance of which is externally
defined by means of a negative current feedback.
The output stage of the power amplifier is supplied by the main supply during the trace period, and by
the flyback generator circuit during the most of the duration of the flyback time. The internal clock
turns off the lower power output stage to start the flyback.
The power output stage is thermally protected by sensing the junction temperature and then by putting
off the current sources of the power stage.
Pin 20
Pin 19
Pin 7
Pin 8
is the inverting input of the amplifier. An external network, Ra and Rb, defines the DC level
across Cy so allowing a correct centering of the output voltage. The series network Rc and Cc,
in conjunction with Ra and Rb, applies at the feedback input pin 20 a small part of the parabola, available across Cy, and the AC feedback voltage, taken across Rf. The external components Rc, Ra and Rd, produce the linearity correction on the output scanning current Iy and
their values must be optimized for each type of CRT.
is the non-inverting input. At this pin the non-inverting input reference voltage supplied by the
voltage regulator can be measured.
This pin is used on a quasi-bridge configuration or on portable TVS.
is the output of the power amplifier and it drives the yoke by a negative slope current ramp Iy.
Re and the Boucherot cell are used to stabilize the power amplifier.
the supply voltage of the power output stage is forced at this pin. During the trace time the
supply voltage is obtained from the main supply voltage Vs by a diode, while during the retrace
time this pin is supplied from the flyback generator.
Flyback generator
This circuit supplies both the power amplifier output stage and the yoke during the most of the duration
of the flyback time (retrace).
The internal clock opens the loop of the amplifier and lets pin 1 floating so allowing the rising of the
flyback. Crossing the main supply voltage at pin 2, the flyback pulse front end drives the flyback generator in such a way allowing its output to reach and overcome the main supply Voltage, starting from a
low condition forced during the trace period.
An integrated diode stops the rising of this output increase and voltage jump is transferred by means
of capacitor Cf at the supply voltage pin of the power stage (pin 8).
When the current across the yoke changes its direction, the output of the flyback generation falls down
to the main supply voltage and it is stopped by means of the saturated output darlington at a high level.
At this time the flyback generator starts to supply the power amplifier output stage by a diode inside the
device. The flyback generator supplies the yoke too.
Later, the increasing flyback current reaches the peak value and then the flyback time is completed:
the trace period restarts. The output of the power amplifier (pin 7) falls under the main supply voltage
and the output of the flyback generator is driven for a low state so allowing the flyback capacitor Cf to
restore the energy lost during the retrace.
Pin 3
is the output of the flyback generator that, when driven, jumps from low to high condition.
An external capacitor Cf transfers the jump to pin 8 (see pin 8).
Blanking generator and CRT protection
This circuit is a pulse shaper and its output goes high during the blanking period or for CRT protection.
572
APPLICATION INFORMATION (continued)
The input is internally driven by the clock pulse that defines the width of the blanking time when a
flyback pulse has been generated. If the flyback pulse is absent (short circuit or open circuit of the yoke),
the blanking output remains high so allowing the CRT protection.
Pin 1
is an open collector output where the blanking pulse is available.
Voltage regulator
The main supply voltage Vs is lowered and regulated internally to allow the required reference voltages
for all the above described blocks.
Pin 2
is the main supply voltage input Vs (positive).
Pin 5,6,15,16 are the GND pins or the negative input of Vs.
THERMAL CONSIDERATIONS (a note referred to Fig. 3, 4 and
5)
The shown value of case to ambient thermal resistance is the equivalent to three thermal resistances
that are:
R1 - Thermal resistance junction to ambient of the device.
R2 - Thermal resistance of the p.c. copper side.
R3 - Thermal resistance of the auxiliary heatsink.
The circuit that contains these thermal resistances is shown on fig. 7 where R3 is the thermal resistance
junction to pins of the device and Pd is the maximum dissipated power.
Fig. 7 - Semiconductor heatsink thermal circuit.
~-5289
Since the thermal resistance R3 of the heatsink is defined from its physical and mechanical charac·
teristics, it is necessary to define the required copper side on the p.C. board for the necessary R2 value.
For instance, let's consider the application for the 900 yoke.
It is known:
It can be calculated:
130 - 60
T j max - Tamb max
Rth c-amb
+
Rth j-Plns-:
8 + 14
3.18W
Using an auxiliary heatsink of a thermal resistance R3= 20°C/W (including some losses), it can be easily
calculated (see fig. 7): R2 = 94°C/W.
From fig. 9, it can be found: Q;;;' 21 mm.
573
MOUNTING INSTRUCTIONS
The Rth j-amb of the TDA 1770 can be reduced by soldering the GND pins to a suitable copper area of
the printed circuit board (Fig. 8) or to an external heatsink.
The diagram of figure 9 shows the Rth as a function of the side "Q" of two equal square copper areas
having a thickness of 35" (1.4 mils).
During soldering the pins temperature must not exceed 260"C and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
Fig. 8 - Example of P.C. board copper area which is used as heatsink.
COPPER AREA 35" THICKNESS
P.C. BOARD
Fig. 10- Maximum allowable
power dissipation vs. ambient temperature
Fig. 9 - Thermal resistance
of the P .C. copper side vs.
side "Q"
,-,
Rt h
f'tot
("C/W }
100
150
\
\t:
"'>",
~>
1\
\
'\.
10 0
,
"-
.......
50
10
\
~
"'",
10
30
'-
*
"
t:::
1-
40
.e
(mm)
-50
574
50
..
~"
~<;.
l:.
~.
\C,
/,
~~
'1'-
--;...
100
TambC-C)
LINEAR INTEGRATED CIRCUIT
4W AUDIO AMPLIFIER
The TDA 1904 is a monolithic integrated circuit in POWERDIP package intended f6r.useas low-frequency power amplifier in a wide range of applications in portable radio and
sets.
Its main features are:
rv
High output current capability (up to 2A)
Protection against chip overtemperature
Low noise
High supply voltage rejection
Supply voltage range: 4V to 20V
ABSOLUTE MAXIMUM
Vs
10
10
Ptot
Tstg , Tj
Supply voltage'
Peak output current(rontepetitive)
Peak outpy,~curl%ll~t (fepetitive)
Total pow(tr~i~si~ti(im at Tamb = 80°C
c,cCCc,>c c
Tease = 60°C
Storage ancf'tunction temperature
20
2.5
2
1
6
-40 to 150
V
A
A
W
W
°C
ORDERING NUMBER: TDA 1904
Dimensions in mm
MECHANICAL DATA
575
6/82
CONNECTION DIAGRAM
(top view)
'-'
OUTPUT
16
GNO
15
GND
BOOTSTRAP
3
14
GND
N.C
4
13
GND
12
~GND
11
~GND
15
I
N.t
INVERT. IN
6
10~GND
SVR
9
~GND
5-5291
SCHEMATIC DIAGRAM
22ea1 R1I
e
R3 )26'11
Q1
~~
0
~
./012
~
013
1OO.n
'"ii5
kC12
-
R7
100'11
R6
......04
os,/"
r2llnA
RI
iml.
*C1
AI
D1
to
: !::50pF'
R4
6'11
"'07
"
~03
K~
D2
7
05
•
AI
D6
0;""
OS
~
Q1Q
........014
......
--<09
06>-
R2
03
~
RIO
,
S_S293
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-pins
Thermal resistance junction-ambient
max
max
576
15
70
, I oil
TEST CIRCUIT
(*) R4 is necessary only for V s < 6V.
ELECTRICAL CHARACTERISTICS (refer to the test circuit, Gv= 40 dB, RL = 4n, Tamb = 25°C
unless otherwise specified)
Parameter
Test conditions
Vs
Supply voltage
Id
Quiescent drain current
V=
s 9V
Vs= 14V
Po
Output power
d = 10%
Vs= 9V
Vs= 12V
Vs= 6V
d
Ri
Distortion
B
Frequency response
Voltage gain (open loop)
Gv
Voltage gain (closed loop)
eN
Total input noise voltage
Typ.
4
Max.
20
Unit
V
16
19
mA
mA
2
3.5
0.8
W
W
W
0.1
%
f = 1 KHz
f = 1 KHz
Vs=9V
Po= 50 mW to 1.2W
Vs= 14V
Po= 50 mW to 2W
I nput resistance (pin 8)
Gv
Min.
0.1
%
150
Kn
40 to 40 000
Hz
80
dB
40
dB
Rg= 10 Kn;
B= 22Hz to 22KHz
3
Rg= 10 Kn;
B = curve A
2
J.lV
11
Efficiency
V=
9V
s
Vs= 12V
Po= 2W
Po= 3.5W
SVR
Supply voltage rejection
Vs= 12V
fripple= 100 Hz
Rg= 10 Kn
577
4
70
65
%
50
dB
Fig. 1 - Application circuit
>-'-+_____~C-17
100 !l
R2
Fig. 2 - P.C. board and components layout of fig. 1 (1:1 scale)
C5-0163
578
1000I-lF
LINEAR INTEGRATED CIRCUIT
5W AUDIO AMPLIFIER WITH MUTING
The TDA 1905 is a monolithic integrated circuit in POWERDIP package, intended for use as low frequency power amplifier in a wide range of applications in radio and TV sets.
Its main features are:
muting facility
protection against chip over temperature
very low noise
high supply voltage rejection
low "switch-on" noise
voltage range 4 V to 30V
The TDA 1905 is assembled in a new plastic package, the POWERDIP, that offers the same assembly
ease, space and cost saving of a normal dual in-line package but with a power dissipation of up to 6W
and a thermal resistance of 15 D C/W (junction to pins).
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Input voltage
Differential input voltage
Muting thresold voltage
Power dissipation at Tamb = 80 D C
Tcase = 60D C
Storage and junction temperature
ORDERING NUMBER:
30
3
2.5
o to + Vs
±7
Vs
1
6
-40 to 150
V
A
A
V
V
V
W
W
DC
TDA 1905
MECHANICAL DATA
Dimensions in mm
579
6/82
CONNECTION DIAGRAM
(Top view)
--.::.J
OUTPUT
16
GND
Vs
15
GND
BOOTSTRAP
14
GND
13
000
MUTING
12
GND
INVERT. IN
11
GND
SVR
10
GND
THRESHOLD
4
NON INVERT'I 8
INPUT
GND
5-2913
SCHEMATIC DIAGRAM
I
L~~
k
MUTING
~~
R3
~
Rll
§
0./012
013
l00kil
02
Rl
01
9
~
~
26kfi
300nl
R6
R5
R4
~~
lQOkfl
R7
R,
---{)
200KA
10Kfi+
03
~OB
Cl
"'07
6kn
~"
06>-
R2
6
Kn
02
RB
OS
06
;{;
~ ;~,""
T
RIO
5-361;712
4
( 7
5
• to 16
6
" 6
THERMAL DATA
RthJ-case
RthJ-amb
max
max
Thermal resistance junction-pins
Thermal resistance junction-amb
580
15 °C/W
70 °C/W
TEST CIRCUIT
• c_
_
.....
-
.
. -4055/2_
MUTING CIRCUIT
Vi
1
'Vr
(Muting)
581
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tamb
25°C, Rth (heatsink)
20°C/W, unless otherwise specified)
Vs
Vo
Qu iescent output vol tage
Min.
Test conditions
Parameter
Supply voltage
~ 4V
Vs~14V
~ 30V
Vs
1.6
6.7
14.4
Vs
Id
V CE sat
Po
Quiescent drain current
Output stage saturation
voltage
Output power
Vs ~ 4V
V s ~ 14V
Vs ~ 30V
Harmonic distortion
Max.
Unit
30
V
2.1
7.2
15.5
2.5
7.8
16.8
V
15
17
21
35
Ic
~
lA
0.5
Ic
~
2A
1
mA
V
d ~ 10%
Vs ~ 9V
Vs~14V
f ~ 1 KHz
RL ~ 4[1 (-)
RL ~ 4[1
Vs~18V
RL~8[1
Vs
d
Typ.
4
~
24V
f ~ 1 KHz
Vs ~ 9V
P0
RL
~
2.2
5
5
4.5
16[1
2.5
5.5
5.5
5.3
W
RL~4[1
~
50 mW to 1 .5W
RL ~ 4[1
P0 ~ 50 mW to 3W
0.1
Vs~14V
Vs~18V
Vs
Vi
I nput sensitivity
~
f ~ 1 KHz
Vs ~ 9V
Vs ~ 14V
Vs~18V
Vs ~ 24V
V
~
RL
~
4[1
Po
Po
Po
16[1 Po
RL~4[1
RL~8[1
RL
~
0.1
~
~
~
~
2.5W
5.5W
5.5W
5.3W
9V
37
49
100
Vs
~
24V
I nput resistance (pin 8)
f
1 KHz
60
Id
Drain current
f ~ 1 KHz
Vs ~9V
Vs~18V
Vs~14V
RL
RL
Vs~18V
RL~8[1
~
~
~
RL
~
Po
Po
Po
16[1 Po
RL
RL
RL
RL
~
4[1
4[1
Vs
1]
Efficiency
~
24V
f ~ 1 KHz
Vs ~ 9V
Vs~14V
Vs~18V
~ 24V
Vs
~
~
4[1
4[1
Po
Po
~8[1
Po
~ 16[1 Po
~
(-) With an external resistor of 100[1 between pin 3 and +V s'
582
mV
73
Ri
V:~14V
~
%
0.1
0.8
1.3
1.8
2.4
Vi
Input saturation
voltage (rms)
0.1
RL~8[1
P0 ~ 50 mW to 3W
24V RL ~ 16[1
P0 ~ 50 mW to 3W
V
100
~
2.5W
5.5W
5.5W
5.3W
380
550
410
295
~
~
~
~
2.5W
5.5W
5.5W
5.3W
73
71
74
75
K[1
mA
%
ELECTRICAL CHARACTERISTICS
(continued)
Test conditions
Parameter
BW
Small signal
bandwidth (-3dB)
Vs = 14V
Gv
Voitage gain (open loop)
Vs=14V
f = 1 KHz
Gv
Voltage gain (closed loop)
Vs=14V
f = 1 KHz
eN
Total input noise
SIN
Supply voltage rejection
Thermal shut-down
Tsd
case temperatu re
MUTING FUNCTION
Min.
Po = 1W
RL = 4n
Po = 1W
39.5
Rg = 50n
Rg = 1 Kn
R g =10Kn
(0 )
Rg = 50n
Rg = 1 Kn
R g =10Kn
(00 )
Vs=14V R g =10Kn
Po = 5.5W Rg = 0
R L = 4n
Rg = 10Kn
Rg = 0
Signal to noise ratio
SVR
RL = 4n
Vs=18V RL = 8n
f ripple = 100 Hz
V ripple = 0.5Vrms
Max.
Hz
75
dB
40
40.5
1.2
1.3
1.5
4.0
2.0
2.0
2.2
6.0
dB
p.V
p.V
90
92
dB
(00 )
87
87
dB
50
dB
115
°C
R g =10KH
40
(Refer to Muting circuit)
V TOFF
Muting-off threshold
voltage (pin 4)
1.9
4.7
V TON
Muting-on threshold
voltage (pin 4)
0
1.3
6.2
Vs
R5
I nput resistance (pin 5)
R4
I nput resistance (pin 4)
AT
Muting attenuation
Muting off
80
Rg+ Rl = 10Kn
10
to
22 KHz.
583
50
Kn
200
30
n
Kn
150
Note:
Weighting filter = curve A.
Filter with noise bandwidth: 22 Hz
See fig. 30 and fig. 31
V
V
Muting on
(0)
(00)
(*)
Unit
(0 )
Ptot = 2.5W
(*)
Typ.
40 to 40,000
60
dB
Fig. 1 - Quiescent output
voltage vs. supply voltage
Fig. 2 - Quiescent drain current vs. supply voltage
Vo
Fig. 3 - Output power vs.
supply voltage
P"r-r-'-,,-,,-,-,--,-.,-r-r-,-,,
(V)
(WI
hIKH:;t
f-t-
'.10'. H-++++-H--++-H
n
H-+++.f-,H+-+
20
u"'
_.
...
=t~
" H-+++-,· J++-H-+++f.-H
II'
I
12
16
20
24
12
Fig. 4 - Distortion vs. output power (R L = 16n)
•
(-"':I==l==
16
20
16
Fig. 5 - Distortion vs. output power (R L = an)
20
24
Fig. 6 - Distortion vs. output power (R L = 4n)
("2,: :-- .. -E
V s .. 9'1
·r------nrL=~n
2 I----
J
(J.'
I)
OJ
f .. IKH
J
0.'
11
RL~I6n.
f slKHz
0.0'
..
.'
OD'
,
d
("t.J
\Is ~24V
r-...
(J.,
R L;16Jl.
··
,
,W
/
·
_50mW
Q,
,
0.0,
'0
...10' , ... '0' . ...'0'
, ,
0.0
t(Hz)
.Pc,IWI
0'
Fig. a - Distortion vs. frequency (R L = an)
Fig. 7 - Distortion vs. frequency (R L = 16n)
..
0.0'
(J.,
%(wI
Fig. 9 - Distortion vs. frequency (R L = 4Q)
IIIIIII
V5 ;18Y
......
RI:S.a.
l7'w
I$r
50mW
Q',-SOmW
...'0' , ...10' . ...'0'
5a4
z • ••
f(HzI
oo,L-~~1¥L~4.~.~.L-~,~.~
••~+y.~.~.
10
102
tO J
104
11Hz}
Fig. 10 - Open loop frequency response
G,
Fig. 11 - Output power
vs. input voltage
Fig. 12 - Value of capacitor ex vs. bandwidth (BW)
and gain (Gv)
c,
r--'~~~~TC~~~~~~
(nF)
(dBl
"BW~5KHz
'0
1".."
1$
"0<,yo>
-try ~
"",-
"'"- ~ "' "\.
20
f---Tttitllr--H+H1+
\
lO~
10'
I(Hz)
Vi (mV)
Fig. 14 - Supply voltage rejection vs: source resistance
Fig. 13 - Supply voltage rejection vs. voltage gain (ref.
to the Muting circuit)
"R
5"
,~-,---,--r--~--~-'---,
(dB)
eo
(dB)
r--- -+--,~~--
60
1---
'10\
I!!
I
,-
I
,
r--
20
t--~
II
lilt
50
G v (d8)
10
Fig. 16 - Power dissipation
and efficiency vs. output
power
Plot
(W )
("I.)
f elKHz
~ot
,w,
Gv,"'OdE
60
1.5
"n
--h
-
'0
I
05
ii
~H- f-"I
rr(8nJ
~~~!:~l H7f'''''='''-'i''-t.-l''+-H-++-1
I
16
Rg (Knl
20
24
'Is
(v)
Fig. 18 - Power dissipation
and efficiency vs. output
power
1
('/.)
'tot
,W,
7<)
,.,.,
~
"S·24V
f
~IKHz
y
70
Gv~
Gv,l,OdB
40d
R L ;16ll.
60
3,0
60
2.5
H-I-+-.....~::-t+++-H-I-+-H
so
,.
50
2.0
Hf-f--Y-H
'0
2.0
'5
I-lilL~~-.L+-t--+-L..L+-H-+++-H
30
'.5
30
fH!i'++-P'H~tot {'6°Hrl-+++-H
'.0 IIH-+++-H~-,++-H-++-H 20
'.0
20
0.5
05
10
20
to
8
i
. -r
H-,-,-¥-H7r'+++-H-I-+-H
30
0.5 J-~~~ --'~---I---'~
t
en
3.0
70
30
_
I
2.0
Fig. 17 - Power dissipation
and efficiency vs. output
power
'----,---,--r-_---,_"
Vs~'~V
-
.
i
I
2.5
I
I
20
~-~~
RL~"n
I
I
H-~'~f+i~ +_-+------+--
i
:-
I-
,WI
II
Gv(dB)
Fig. 15 - Max power dissipation vs. supply voltage
(sine wave operation)
r-ti~ ~:~:~:'IOO~!
60
50
20
Po(W)
585
so
"
Plot
to
~ (W)
60
Po (W)
APPLICATION INFORMATION
Fig. 19 - Application circuit without muting
Fig. 20 - PC board and components lay-out
of the circuit of fig. 19 (1:1 scale)
1000,!.JF
°16v
R3
lD
lOon
(-I
R2
R4 is necessary only
for Vs < 10V.
Po = 5.5W (d = 10%)
Vs=14V
Id = 0.55A
Gv = 40 dB
C5-0129'1
Fig. 21 - Application circuit with muting
Fig. 22 - Delayed muting circuit
586
APPLICATION INFORMATION (continued)
Fig. 24 - Output power vs.
supply voltage (circuit of
fig. 23)
Fig. 23 - Low-cost application circuit without bootstrap.
"s
'0
IW)
I0
1uF
"
Fig. 25 - Two position DC tone control using change of pin 5
resistance (muting function)
I'll
lOOka
Fig. 26 - Frequency response
of the circuit of fig. 25
"
"
flIIJ~~~i~~f~~
'0
b
IdB)
50
,"
~
.....
',~-
G,
10
kfi
1£1.
R7
012j.JF
ca
Fig. 27 - Bass Bomb tone control using change of pin 5 resistance
(muting function)
---~--I-r--------{)·vs
C'I0
20 Vs(V)
~!!lIl.ll!lIl~l!II'FL~rlllll
Fig. 28 - Frequency response
of the circuit of fig. 27
Gv
(dB)
1/JF
50
48
l000,uF
BOOST
46
ca
1'14
RG
10Hl
lJl
"
FLAT
40
loon
38
"
'0
587
'0'
'0'
)0'
t(Hz)
MUTING FUNCTION
The output signal can be inhibited applying'a DC voltage VT to pin 4, as shown in fig. 29
Fig. 29
VOUT
Vs/2
The input resistance at pin 5 depends on the threshold voltage V T at pin 4 and is typically:
Rs =200 Ku
@
1.9V < VT < 4.7V
muting-off
Rs = lOu
@
OV-
R2
12
~
./
07
~03
'Y
@
012
==Cl
Rl
@
"",014
10
RIO
5- 4044
7
8
6
593
9
TEST CIRCUIT
• See fig. 12.
THERMAL DATA
Rth j-tab
Rth j-amb
TDA 1908
TDA 1980A
25°C,
Rth (heatsink)=
max
max
Thermal resistance junction-tab·
Thermal resistance junction-amb
(0) Obtained with tabs soldered to printed circuit board with min copper area.
ELECTRICAL CHARACTERISTICS
8 °C/W,
(Refer to the test circuit, T amb =
unless otherwise specified)
Max.
Unit
30
V
2.1
9.2
15.5
2.5
10.2
16.8
V
Vs =4V
Vs=18V
Vs = 30V
15
17.5
21
35
Ic= lA
0.5
Ic= 2.5A
1.3
Test condition
Parameter
Vs
Supply voltage
Va
Quiescent output voltage
Id
Quiescent drain current
V CEsat
Po
Output stage saturation voltage
(each output transistor)
Output power
Min.
Typ.
4
1.6
8.2
14.4
Vs =4V
Vs=18V
Vs = 30V
mA
V
f = 1 KHz
d = 10%
R L = 40Vs= 9V
R L = 40Vs=14V
R L = 40.
Vs=18V
R L = 80.
Vs = 22V
R L = 160.
Vs = 24V
594
2.5
5.5
7
9
6.5
4.5
8
5.3
W
ELECTRICAL CHARACTERISTICS
(continued)
Test condition
Parameter
f ~ 1 KHz
Vs ~ 9V
P0
Harmonic distortion
d
Min.
RL~ 4S"!
50 mW to 1.5W
RL~ 4S"!
P0 ~ 50 mW to 4W
24V
RL~ 16S"!
Po~ 50 mW to 3W
~
•
Typ.
Max
Unit
0.1
Vs~1SV
V5
V
I nput sensitivity
Vi
9V
RL~
4S"!
Po~
Po~
Vs=1SV
Vs ~ 22V
V 5 ~ 24V
RL~
4S"!
SS"!
Po~
RL~16S"!
Po~
~
V:~14V R L = 4S"!
RL~
0.1
2.5W
5.5W
9W
37
52
64
90
110
Po~SW
5.3W
~
24V
Ri
I nput resistance (pin S)
f
~
1 KHz
Is
Drain current
f
~
1 KHz
Efficiency
1)
mA
1 KHz
Po~ 9W
72
%
Po~
40 to 40 000
Hz
75
dB
Po~
~
f
Vs~18V
BW
Small signal bandwidth (-3 dB)
Vs=1SV
Gv
Voltage gain (open loop)
f
Gv
Voltage gain (closed loop)
Vs~18V
f
Total input noise
570
730
500
310
Po~
RL~ 411
RL~ 4S"!
22V RL ~ SS"!
24V RL~ 16S"!
RL~
eN
KS"!
Vs~1SV
~
~
~
~
4S"!
Po~
Po~
4S"!
RL~
5.5W
9W
8W
5.3W
1W
1 KHz
1 KHz
(0 )
(00 )
RL~
Po~
Rg
Rg
Rg
~
Rg
Rg
~
4S"!
1W
~
~
~
39.5
40
40.5
50S"!
1 KS"!
10 KS"!
1.2
1.3
1.5
4.0
50S"!
1KS"!
2.0
2.0
2.2
6.0
Rg~10Ks"!
SIN
Signal to noise ratio
Vs~18V
Rg~
P0 ~ 9W
RL ~ 4S"!
Rg~
Rg~
SVR
Supply voltage rejection
Vs~1SV
Tsd
Thermal shut-down case
temperature
(0)
(0 )
10KS"!
1° 0
0
RL~
4S"!
Rg~
Ptot~
(* )
)
40
10KS"!
4W
-
Note:
(00)
(*)
10KS"!
0
Rg~
f ripple~ 100 Hz
Weighting filter ~ curve A.
Filter with noise bandwidth· 22 Hz to 22 KHz.
See fig. 24 and fig. 25.
595
V
100
60
Vs~14V
V5
V5
mV
0.8
1.3
1.S
2.4
Vs~18V
Vs
%
0.1
V 5 ~ 9V
V 5 ~ 14V
Input saturation voltage (rms)
Vi
~
dB
J1.V
J1.V
92
94
dB
S8
90
dB
50
dB
110
°C
Fig. 1 - Quiescent output
voltage vs. supply voltage
G-4216
v,
(V)
Fig. 2 - Quiescent dra'in current vs. supply voltage
G_1,277
I.
+-
(rnA)
,
10
"t-
"
"I"
U
h-
16
-
F
r
24
16
20
Fig. 4 - Distortion vs. output power (R L = 16n)
•
(O,.J:
I"
P, r--'--~r--,---,---~-P~,
(W)
9
J....l
20
-+17
Fig. 3 - Output power vs.
supply voltage
,;'6
'''S9V
-
20
'is (V)
24
6
Fig. 5 - Distortion vs. output power (R L = 8n)
9
12
15
18
21
24
,"s(V)
Fig. 6 - Distortion vs. output power (R L = 4n)
G-HSO
(~
fi-"
1
11
'
IIi
0.1
.
il
22V
I
' C--"
.
0.1
, ,
0.01
~(W)
01
>BV
Vs:9V
!
f ,,1KHz
0.1
R L ~\6.n
f .IKHz
0"'
'~~Jl
'I
0.1
Fig. 7 - Distortion vs. frequency (R L = 16n)
.
i
0.1
Po (W)
Fig. 9 - Distortion vs. frequency (R L = 4n)
Fig. 8 - Distortion vs. frequency (R L = 8n)
..
tJ
.11
0.01
Po(W)
)
,;:
(OM
'I'l1
3W.
-
'0'5. 24 '0'
,-
.
'J-tt
L,I6V
R
I
:f=fl
(l()1
'W
10
t
,"
1:1--1
10'
II
'7
ii.
01
I
I
1
~
50mW
fir ,lW·
10 4
I(Hz)
,
I
no,
,0
."
10'
iT
p-
""S·IBV
RL,a.Q
3W
50mW
""5. 14 ""
3W
R L,4
50mW
0'
'" 10'
596
,"
no,
10'
I(Hz)
'0
,0'
'"
,
~,
...
10'
f(Hz)
G,
Fig. 12 - Values of capacitor
versus gain and Bw
Fig. 11 - Output power vs.
input voltage
Fig. 10 - Open loop frequency response
ex
C,
,,-cmr~~r-~~~~m-~~
(nfJ
(dB)
-t,y
,"
~BW'5t(Hz
'0
/s
<'01"Z..y~ -?'
.,
60
10
,,'
la'
la'
)0'
20
!(Hz)
Fig. 13 - Supply voltage
rejection vs. voltage gain
Fig. 14 - Supply voltage rejection vs. source resistance
i
I I! II
I ('---I!
I
II ~S,:':~ !~t;
I
I ! I!
f r iPplEhl00Hz \
I!
i
I i II
I'
Fig. 16 - Power dissipation
and efficiency vs. output
power (Vs= 14V)
j
I
Fig. 15 - Max power dissipation vs. supply voltage
Plot
'WI
~
I
1'1 11
~ I I
0.5
"
Rg (KIU
Fig. 17 - Power dissipation
and efficiency vs. output
power (Vs= 18V)
(WI
80
"
21
"
vs(V)
HY"f:~;,~'":Y",t+f-_t~+_+f-71-"J..-rl'-+ ++-1
::::~-f--Hft+++-f-t++H
35
~~)
60
so
30
60
2.5
50
25
"
1.5
30
IS
Fig. 18 - Power dissipation
and efficiency vs. output
power (Vs= 24V)
~~~
Plot
40
30
I
'j
10
j\.
I
I I
I
•
2.0
1'-
'\ ~
60 H++~··++ffiljir--c-l'"~-+l+'IIII--++;ljj!j
40
30
20
1.0
20
05
"
•
0.5
~ (W)
597
APPLICATION INFORMATION
Fig. 19 - Application circuit with bootstrap
• R4 is necessary when V s is less than 1 OV.
Fig. 20 - P.C. board and component lay-out of the circuit of fig. 19 (1: 1 scale)
Vs
GND
G
GND
CS-0128'1
598
APPLICATION INFORMATION
(continued)
Fig. 22 - Output power vs.
supply voltage (circuit of
fig. 21)
Fig. 21 - Application circuit without bootstrap
,;,1
~--~--~~--
I /"
I
1KHz
"'-""l'
RL="n
I
d,'O·'.
I~ ~~
[-~T
24
Fig. 23 - Position control for car headlights
,
~O.lAJF
I.....
-------c::J----100 11
~lu
~
1 M-ll~~~--+'
MANUAL
SETTING
,-------c:J---i
I
I
!
I-T--~---L
l8'4
-------~
~-~-
599
lsJ
Vs(V)
APPLICATION SUGGESTION
The recommended values of the external components are those shown on the application circuit of
fig. 19.
When the supply voltage V5 is less than 10V, a 100n resistor must be connected between pin 1 and pin 4
in order to obtain the maximum output power.
Different values can be used. The following table can help the designer.
Component
Raccom.
value
Purpose
Larger than
raccomanded value
Smaller than
raccomanded value
Allowed range
Min.
Max.
RI
10Kn
Close loop gain
setting.
Increase of gain.
Decrease of gain.
Increase qu iescent
current.
R2
lOon
Close loop gain
setting.
Decrease of gain.
Increase of gain.
R3
1n
Frequency stability
Danger of oscillation
at high frequencies
with inductive loads.
R4
100n
Increasing of output
swing with low V s'
CI
2.21'F
Input DC
decoupling.
C2
O.lI'F
Supply voltage
bypass.
C3
2.21'F
Inverting input DC
decoupling.
Increase of the
switch-on noise
Higher low frequency cutoff.
O.lI'F
C4
10l'F
Ripple Rejection.
Increase of SVR.
Increase of the
switch-on time.
Degradation of
SVR.
2.21'F
100 l'F
Cs
471'F
Bootstrap
Increase of the
distortion at low
frequency
10l'F
100l'F
C6
0.221'F
Frequency stability.
Danger of oscillation.
C7
1000l'F
Output DC
decoupling.
Higher low frequency cutoff.
9 R2
R l /9
47n
Lower noise
Higher low frequency cutoff.
Higher no ise.
330n
O.lI'F
Danger of
oscillations.
600
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent). or an above limit ambient temperature can be
easily supported since the Tj cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
If, for any reason" the junction temperature increases up to 150°C, the thermal shut-down simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance); fig. 26 shows this dissipable power as a function of ambient temperature for different
thermal resistance.
Fig. 24 - Output power and
drain current vs. case tem·
perature
Fig. 25 - Output power and
drain current vs. case temperature
Fig. 26 - Maximum power
dissipation vs. ambient tem·
perature
MOUNTING INSTRUCTIONS
The thermal power dissipated in the circuit
may be removed by connecting the tabs to
an external heatsink (TDA 1908A see fig.
27), or by soldering them to a copper area
on the PC board (TDA 1908 see fig. 28).
During soldering, tab temperature must not
exceed 260°C and the soldering time must
not be longer than 12 seconds.
Fig. 27
ALUMINIUM
J5rrm THICKNES-?
601
MOUNTING INSTRUCTIONS (continued)
Fig. 28 -- Mounting example (TDA 1908)
Fig. 29 -- Maximum power
dissipation and thermal resistance vs. side "Q"
(TDA 1908)
_+
0952
G
COPPER
AREA 35}.l
THICKNESS
h-
'I.
L_~_.
Rlh
__ .~
Rt J-am
N..
40
I
+
Ptot(Tamb~ 55 'C)
r=
..H-p\Q\ (Tarnb " 70'C l
20
P.
C BOARD
602
30
40
10
l(mm)
LINEAR INTEGRATED CIRCUIT
lOW AUDIO AMPLIFIER WITH MUTING
The TDA 1910 is a monolithic integrated circuit in MULTIWATT@package,intendedforusein Hi-Fi
audio power applications, as high quality TV sets.
The TDA 1910 meets the DIN 45500 (d = 0.5%) guaranteed output power of 10W when used at 24V/
4n. At 24V/8n the output power is 7W min. Features:
muting facility
protection against chip over temperature
very low noise
high supply voltage rejection
low "switch-on" noise.
The TDA 1910 is assembled in MU LTIWA TT@ package that offers:
easy assembly
simple heatsink
space and cost saving
high reliability.
ABSOLUTE MAXIMUM RATINGS
Vs
10
10
Vi
Vi
Vl l
Ptot
T stg , T j
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Input voltage
Differential input voltage
Muting thresold voltage
Power dissipation at T case = 900 e
Storage and junction temperature
o to
30
3.5
3.0
+ Vs
±7
Vs
20
-AO to 150
V
A
A
V
V
V
W
°e
ORDERING NUMBER: TDA 1910
MECHANICAL DATA
Dimensions in mm
603
6/82
CONNECTION DIAGRAM (Top view)
r====::o
r====::o
THRESHOLD
BOOTSTRAP
-V5
OUTPUT
GNu
I~~~~GNO
INPUT-
Ne
o
SVR
INPUTMUTING
5-3655
tab connected to pin 6
SCHEMATIC DIAGRAM
10
300nj RI1
~"
k
MUTING
-,....-
D1
~
R3
~
(J 26kfi
f~
9
f~
0
::: 012
a2
.,
IOOkil
l00kfi
R5
R6
~
"",a4
a13
a/o
.7
R9
2~Jl
1o'K1L
:::/CI ~
R4
6kfi
>--f( a3
~"
Q6)-6
R2
KJl
02
R8
8
03
H' .
os
D6
a,0
a8
~
Va'4
7
J.w
5-3647/1
11
I
3
5
2
604
6
TEST CIRCUIT
.Vs
I
3.3 R r1820
k.tl
xl I n
," ("J
~:f:~Cx
L -_ _ _.,......, _ - - -.... - - - - 1
C4
100n
R2
(*) See fig. 13.
5-364811
MUTING CIRCUIT
.Vs
1
C5
.VT
(Muting)
605
RL
THERMAL DATA
Rlh
Thermal resistance junction-case
max
3
j-c
.~----------------------------------------~-----------------
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Rlh (heatsink)
4°C/W, unless otherwise specified)
Test condition
Parameter
r-'
Vs
Supp Iy vo Ilage
Va
Quiescent output voltage
Id
Quiescent drain current
Min.
8
Vs
Vs
~
~
18V
24V
8.3
11.5
Vs~18V
Vs
~
Ic~
VCE sal Output stage saturation voltage
24V
2A
Output power
d
= 0.5%
d
~
~
~
f
~
24V
24V
10%
Vs~18V
V s = 24V
Vs ~ 24V
d
d
Vi
I nput sensitivity
RL~4n
RL~4n
I
I
9.2
12.4
10
13.4
19
21
32
35
V
mA
V
RL~
8n
f = 1 KHz
R L =4n
RL~ 4n
RL~ 8n
7
12
7.5
W
8.5
15
9.5
17
10
W
9
1 KHz
18V RL~4n Po~ 7W
Vs ~ 24V R L = 4n p 0 ~ 12W
Vs = 24V RL~ 8n Po~ 7.5W
f
V
6.5
10
7
Vs = 24V R L =4n Po= 10W
f2= 8 KHz
fl = 250 Hz
(DIN 45500)
Intermodulation distortion
30
40 to 15,000Hz
f = 40 to 15.000 Hz
RL~4n
Vs=18V
P0= 50 mW to 6.5W
RL~4n
Vs= 24V
Po~ 50 mW to 10W
Vs ~ 24V
RL~ 8n
Po= 50 mW to 7W
Harmonic distortion
Unit
1.6
Vs~18V
Vs
Vs
Max.
1
Ic= 3A
Po
Typ.
0.2
0.5
0.2
0.5
0.2
0.5
%
0.2
%
170
220
245
mV
~
Vs~
Vi
Input saturation voltage (rms)
Vs=18V
Vs ~ 24V
1.8
2.4
Ri
Input resistance (pin 5)
f = 1 KHz
60
Id
Drain current
Vs
~
f = 1 KHz
24V
p 0 ~ 12W
R L =4n
R L = 8n
Po= 7.5W
606
V
100
820
475
Kn
I
I
mA
ELECTRICAL CHARACTERISTICS (continued)
Test condition
Parameter
Efficiency
1)
R L =4n
BW
Small signal bandwidth
Vs = 24V
BW
Power bandwidth
Vs=24V
Po = 12W
Gv
Voltage gain (open loop)
f = 1 KHz
Gv
Voltage gain (closed loop)
Vs = 24V
f = 1 KHz
eN
Total input noise
SIN
Signal to noise ratio
SVR
Supply voltage rejection
Tsd
Thermal shut-down case
temperature
Min.
f = 1 KHz
Vs = 24V
R L =4n
Po= 12W
R L =8n
Po= 7.5W
Vs = 24V
Po = 12W
R L =4n
Po= 1W
R L =4n
d" 0.5%
R L =4n
Po= 1W
Max.
Unit
62
65
%
10 to 120,000
Hz
40 to 15,000
Hz
75
dB
30
30.5
dB
Rg = 50n
Rg = 1Kn (0)
Rg = 10Kn
1.2
1.3
1.5
3.0
3.2
4.0
/lV
Rg = 50n
Rg = 1Kn (00)
Rg = 10Kn
2.0
2.0
2.2
5.0
5.2
6.0
/lV
Rg = 10Kn
(0)
Rg = 0
97
103
105
dB
R g =10Kn
(00)
Rg = 0
93
100
100
dB
50
60
dB
110
125
°C
R L =4n
Vs = 24V
Rg= 10Kn
friPPle= 100 Hz
Ptot = 8W
(*)
29.5
Typ.
MUTING FUNCTION (Refer to Muting circuit)
VT
Muting-off threshold voltage
(pin 11)
1.9
4.7
VT
Muting-on threshold voltage
(pin 111
0
1.3
6
Vs
Rl
V
I nput resistance (pin 1)
Muting off
80
Muting on
Rll
Input resistance (pin 11)
AT
Muting attenuation
(*)
200
10
150
R g +R 1 =10Kn
Nota:
(0)
(00)
V
Weighting filter = l'urve A.
Filter with noise bandwidth: 22 Hz to 22 KHz.
See fig. 29 and fig. 30.
607
50
Kn
30
n
Kn
60
dB
Yo
G_3682
P"
(V)
14~~~-t-+~4-+-i-+~+-~~
Fig. 3 -Open loop frequency
response
Fig. 2 - Quiescent drain
current vs. supply volta g:_""
Fig. 1 - Quiescent output
voltage vs. supply voltage
(m~H-+-j-H-+++-~~+-~-
--+-------l----__+v",s_;,_,_v-t-_-i
_--I---+
(d'!:)
+-- --100 I==::j-80. L______ ---'-- - ''60
12~+H+
40.
'0.-cL-_~
12
16
20
24
12
Vs (V)
G_J6a3
Po
20
24
lis (II)
Fig. 5 - Output power vs .
supply voltage
. Fig. 4 - Output power vs.
supply voltage
(W )1---- 1= 40Hz
16
10
10.'
_
_ L _ _L__~_~
10.'
10'
Fig. 6
Distortion
output power
vs.
G_36a4
"0
to 15KHz
(W )
d=O.5°'.
4r--
16
f=lKHz
d,,10%
--
RL=4n
RL=4n./
12
8
/
V
./'"
/'
",-
~
0.
8
.-
V
/'
RL :8n
/
,
V
./
16
20.
/
---- ----
/'
",.- Rl ,,8n
",.-
f:::=: I--
0.
12
/
24
Fig. 7
Distortion
output power
8
Vs (V)
vs.
V
12
./
./
16
24
20.
Vs (V)
Fig. 8 - Output power vs.
frequency
G 3701
Ii>
(W )
s·'·V
R L=4n
10.
fl,(W)
Fig. 9 - Output power vs.
frequency
'm!eE~m!e~'~S~"~4!V~
($) ~
RL =8n
d=0,2·J.
10.
_m·,.
I IT'
d=O.10J0
d.Q.,·,.
d=Q2'/.
,
10.-
I' 254063
~2S4063
I I I'
16254063
1625410163
10 3
608
10~
f (Hz)
Fig. 10 - Output power vs.
input voltage
Fig. 11 - Output power vs.
input voltage
Fig. 12 - Total input noise
vs. source resistance
G 3699
'" :~
(W)
10
Vs=24V
Gv = 30dB
.
:
/
RL=4J1
RL,-sn
R L_'6f
'/
!
r-t
10-
.
ex
I
I [
10
10'
10
Fig. 13 - Values of capacitor ex vs. bandwidth (BW)
and gain (G v )
6_3696
30
50
100 Vi (mY)
Fig. 15 - Supply voltage rejection vs. source resitance
Fig. 14 - Supply voltage rejection vs. voltage gain
G 3696
(dB)
,
.t'-..
10
z
--
".,
Vs:24V
80
R
~
........
60
."":\
I,
0-
Bw =5KHz
10KHz
=
Vs=24V
Rl =4J1
80
LL
i
-
frippl€, =l00Hz
60
~~
2~FI
I"'-- ~ R
I"'--
-c---
r--- r---
f r ipple:100Hz
RL=4n
Rg =()KJ1
63697
,
SVR
(dB )
SVR
(nF )
10.u F C3
r---
40
5~F
2~F
20
20
15KHz
30KHz
,
20
30
40
o
50 Gv(dB)
Fig. 16 - Power dissipation
and efficiency vs. output
power
'1
( "I.)
/'1
60
IV
1/
----
--
40
4
I
~
. / r-rt
1/
/
6_3675
80
6
I
./
)
10
V
I/R Lo4n
40
/
'lot
20
"
2
I
20
o
12
Rg (0)
Fig. 18 - Max power dissipation vs. supply voltage
(
,/
6
10'
,
Vs=24V
(W) - t=lKHz
80
/
A"'-
~o t
Rl=4Il
Rl =SJ1
10'
50 Gv(dB)
Fig. 17 - Power dissipation
and efficiency vs. output
power
,-
G_3731
Vs=24V
~ot
(W )1--- t=IKHz
40
30
I
i
o
20
10
16 Fb(W)
12
609
16
Fb (W)
o
L
V
i:::::: V
V RL° 8n
./
16
24
APPLICATION INFORMATION
Fig. 19 - Application circuit without muting
Fig. 20 - PC board and component lay-out of the
circuit of fig. 19 (1: 1 scale)
.
nOO,uF
C7
16v
R3
ID
O.22,uF
lOOil
R2
C6
Fig. 21 - Application circuit with muting
Performance (circuits of fig. 19 and 21)
Po =
Vs
Id =
Gv =
12W (40 to 15000 Hz, d ";;;0.5%)
= 24V
Rg
R2
.v,
Muting
610
0.82A
30 dB
APPLICATION INFORMATION (continued)
Fig. 22 - Two position DC tone control (10 dB boost 50 Hz and
20 KHz) using change of pin 1 resistance (muting function)
Fig. 23 - Frequency response of the circuit of
fig. 22
G.3679
r-----~p---.,....--------oVs::.+2"V
R,
lQOkIl
01,uF
Flat
R2
I
~.
C5
12karOOS'
I!!
i
-t
2
--I
-~
B
r-----~p---.,....-------_ovs=
Rl
l00kll
Flat
C4
't,
1
'I
to'
10
Fig. 24 - 10 dB 50 Hz boost tone control using change of pin
resistance (muting function)
BOOST
I
I Ii
I'
,
j II
:\-
",
0
i
J
Bh
I
! il,!
I
r- 11'"
6
34
ii
ii i
2
',~
' I ~I,
-f FLAT
i III
1I1I
10'
10'
f(Hz)
Fig. 25 - Frequency response of the circuit of
fig. 24
·24V
G~l"6
IO.1,uF
I
)
,
I
42
,
40
38
36
2200,uF
C8
C2
34
16V
l\a005
I
'/
,
32 <-
R6
30
la
R3
2B -
RL=411
10
O.22,uF
C7
Fig. 26 - Squelch function in TV applications
,
~
If
, FLAT
i
,
I
10'
I
10'
1()'
Fig. 27 - Delayed muting circuit
r---~----------OV5='24V
Rl
l00kfl.
2200,uF
'6'
611
t(Hz)
MUTING FUNCTION
The output signal can be inhibited applying a DC voltage V T to pin 11, as shown in fig. 28
Fig. 28
"OUT
Vs/2
The input resistance at pin 1 depends on the threshold voltage VT at pin 11 and is typically.
Rl = 200 Kn
@
@
1.9V ~ V T
OV
~
~
4.7V
muting-off
V T ~ 1.3V
Vs
muting-on
6V~VT ~
Referring to the following input stage, the possible attenuation of the input signal and therefore of the
output signal can be found using the following expression.
where Rs "" 100 Kn
Considering Rg = 10 Kn the attenuation in the muting-on condition is typically AT= 60 dB. In the
muting-off condition, the attenuation is very low, typically 1.2 dB.
A very low current is necessary to drive the threshold voltage V T because the input resistance at pin 11
is greater than 150 Kn. The muting function car1 be used in many cases, when a temporary inhibition
of the output signal is requested, for example:
in switch-on condition, to avoid preamplifier power-on transients (see fig. 27)
- during commutations at the input stages.
- during the receiver tuning.
The variable impedance capability at pin 1 can be useful in many applications and we have shown 2
examples in fig. 22 and 24, where it has been used to change the feedback network, obtaining 2 different
frequency responses.
612
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 21. Different
values can be used.
The following table can help the designer.
Component
Rg
+ Rl
R2
Recomm.
value
10Kn
3.3Kn
Larger than
recommended value
Smaller than
recommended value
Input signal imped.
for muting operation
Increase of the attenuation in muting-on
condition.Decrease of
the input sensitivity.
nuation in muting
on condition.
Close loop gain
setting.
Increase of gain.
Purpose
Allowed range
Min.
Max.
Decrease of the atte-
Decrease of gain.
Increase quiescent
9 R3
current.
Close loop gain
setting.
Decrease of gain.
Frequency stability
Danger of oscillation
at high frequencies
with inductive loads.
Volume potentiometer.
Increase of the
switch-on noise.
R3
lOOn
R4
In
Pl
20Kn
Cl
C2
C3
11lF
1 }LF
0.22 }LF
Input DC
decoupling.
C4
2.2}LF
Inverting input DC
decoupling.
Cs
O.lIlF
Supply voltage
bypass.
C6
10llF
Ripple Rejection.
C7
471lF
Cs
0,22}LF
C9
2200 }LF
(R L =4n)
l0001lF
(RL=Bnl
R 2 /9
Increase of gain.
Decrease of the input
impedance and the
input level.
10K!1
100Kn
Higher low frequency cutoff.
Increase of the
switch-on noise.
I:i igher low frequency cutoff.
0.1 ,,;,F
Danger of
oscillations.
Degradation of
SVR.
2.2 }LF
100llF
Bootstrap.
Increase of the distortion at low frequency.
10llF
100llF
Frequency stability.
Danger of oscillation.
Output DC
decoupling.
Higher low frequency cutoff.
Increase of SV R .
Increase of the
switch-on time.
613
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent), or an above limit ambient temperature can' be
easily supported since the T j cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
If for any reason, the junction temperature increases up to 150°C, the thermal shut-down simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance); fig. 31 shows this dissipable power as a function of ambient temperature for different
thermal resistance.
Fig. 29 - Output power and
drain current vs. case tel"
perature
,
.
!
,
)
I
IIs:<2411
f :::lKHz
Rl =41\
i
I
fbi
12
10
Id
j.
i-1-
I
'l
I
20 40
I
60 80 100 120 140
i
-. :fu ~~
.
16
-9
I
08
12
10
__ ,_+-
06
II-\
~01
(W I
I
12
I
i
d
Al
V5 =24V,
L=lf",Hz 1----RL:::81\!
14
1
\
_-t-_ . LJ+:
I
-
\
I
---t
1d
1Al
I
1\
t-
"
Fig. 31 - Maximum allowable power dissipation vs.
ambient temperature
6·)578
Fig. 30 - Output power and
drain current vs. case temperature
!
10
Po ,._
Id
I--
"
--
04
I
I
0
Tease( C} (1
20 40
,
0.8
I
I
1 ____
;I
60 80 100 120 140 Tcase{oC)
614
f.;;
-9
S"~
~r
~c
50
100 Tamb(OC)
~
.~~
;'~'6' /""
.,-
0.6
~t_
+-
~
~
'c'/Jr
0.4
0.2
o
-50
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the Multiwatt ® package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon
grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces._
Fig. 34 - Mounting examples
o
....
o .. .
.. ..
.•
.
5-3712
S-3713
615
LINEAR INTEGRATED CIRCUIT
8W CAR RADIO AUDIO AMPLIFIER
The TDA 2002 is a class B audio power amplifier in Pentawatt® package designed for driving low impedance loads (down to 1.60.). The device provides a high output current capability (up to 3.5A), very
low harmonic and cross-over distortion. In addition, the device offers the following features:
-
very low number of external comoonents
assembly ease, due to Pentawatt® power package with no electrical insulation requirement
space and cost saving
high reliability
flexibility in use
complete safety during operation due to protection against:
a) short circuit; b) thermal over range; c) fortuitous open ground; d) polarity inversion (V s max= 12V);
e) load dump voltage surge.
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10
10
Ptot
T stg, T j
Peak supply voltage (50 ms)
DC supply voltage
Operating supply voltage
Output peak current (repetitive)
Output peak current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature
40
28
18
3.5
4.5
15
-40 to 150
V
V
V
A
A
W
°C
ORDERING NUMBERS: TDA 2002 H
TDA 2002 V
Dimensions in mm
MECHANICAL DATA
6/82
616
CONNECTION DIAGRAM
(top view)
5-1894'1
SCHEMATIC DIAGRAM
L ~'bi
~4
O~
T
~5
OJ
R6
~'JI
01
as
R.
07
08
06
09
R9
4
~1-'
=f"
R7
02
R14
020
RS
R4
09
RIO
150kn
R2
022
~a23
if
RJ
021
~Q13
os
,-----
01
OJ
04
1
·F+
l~~
If
07
-
YS =14.4V
'-1kHz
R L=4.n
'00
VS "'4.4V
'-1kHz
RL"2.n
200
14.IoV
200
P. .. S.2W
100
100
"'
..-P. -O.SW
p'::aQ.5W
8Y
12
,
16
20
24
RL (1)
Fig. 7 - Distortion vs. out·
put power
G-20n/l
,
-
I
I
f= 1kHz
SY"
1111
(dS)
I
III ~
o
j
I·
V•• 144V
J
r
___ ~::~~~~Hz
R2 "Z.2n
·20 f-+-+-+-+-+++-+-+-+-+-I
Gv,, 40
40
"l
II
I
---Vs=14.4V-
.lD
I"
I
R =4n
Fig. 9 -Supply voltage rejec'
tion vs. voltage gain
G_2099/1
r
Vs ·I4.4V
Gv ·40dB
,..
200
100
'00
Fig. 8 - Distortion vs. fre·
quency
("10 l
(",. l
200
'00
2n
·40 1--l.L-l-+---I--+-++-+-+-+-+-I
Po :2.5W
l/
50mW
10
_50 L.L.L.L..L..L..J....J......LJJ...J.--.J
10'
10'
619
10'
f (Hz)
o
100
200
300
400
Fig. 10 - Supply voltage
rejection vs. frequency
Fig. 11 - Power dissipation
and efficiency vs. output
power (R L = 4n)
Fig. 12 - Power dissipation
and efficiency vs. output
power (R L = 2n)
;;"110211
SVR
I
R = 4n
V$ "'14,4V
"
-20
P tot
V
-eo~1DI
E:Etmm
10
... .
lOJ
,
60
I
50
EHfEEEIS=Ef.g~fa"
vs _1Io4V1=
(W)
Plot
~t~
6'
10 3
104
f (Hz)
Fig. 13 - Maximum power
dissipation vs. supply voltage
(sine wave operation)
•
Ptotlll
P tot
+t+
"--I-
+ Kh-t M-t-
,,--,--,--,,--,--,--,.,--r,--,.,-'-T'T'-'o
50
13
5
6
7
·
, ",
.......
··
B .. 10KHz
r--..
0
t"-
20KHz
,
,
JO'CtW
40
60
80
100
120
TaOilb(OC)
'Po (W)
c,
10
R "2
8
, (nF )
' .......
lO"CIW
"
Fig. 15 - Values of capacitor
(C x ) for different values of
frequency response (BI '"''
,
10
20
10
12
20
60
10
14
Vs (V)
70
30
to
15
R,,2tt
H~
(W) H7.,.:OF;:"."'IT'<-.-J,H"'EA::',t;S,.d--rH++-H i
15
Pt t
t:::lkHz
40
Fig. 14 - Maximim allowable
power dissipation vs. ambient temperature
(W)
(0/.)
+
+
~G'·'mOdB
J-'-'-
R2 .. Z.2n
-80
..-
-
Rg
c::::J
(*) In
TDA 2003
C1
c=:J
--cJRl
c:::)
c=J
C5
C6
the device can
support a short circuit between every
side of the loudspeaker and ground.
Fig. 22 - P.C. board and component layout for the low-cost bridge amplifier of fig. 20, in stereo version
(1:1 scale}
C5-0103/3
1m'
C3
C3
C5
--c:::::>-
(
<==::)
)
C1
IN
m m m
TDA 2003
lOA 2003
T{)AZ003
TDA 2003
U4
C2
C7
C2
<==::)
-c:=r
R1
C6
--c:=JR1
C6
c==:>
D4
·~C5
~
<==::)
C1
RL
BUILT-IN PROTECTION SYSTEMS
Load dump voltage surge
The TDA 2003 has a circuit which enables it to withstand a voltage pulse train, on pin 5, of the type
shown in fig. 23.
If the supply voltage peaks to more than 40V, then an LC filter must be inserted between the supply
and pin 5, in order to assure that the pulses at pin 5 will be held within the limits shown in fig. 23.
A suggested LC network is shown in fig. 24. With this network, a train of pulses with amplitude up to
120V and width of 2 ms can be applied at point A. This type of protection is ON when the supply
voltage (pulsed or DC) exceeds 18V. For this reason the maximum operating supply voltage is 18V.
629
Fig. 23
Fig. 24
FROM
A
L=2mH
SUPPLY ~TO PIN 5
j£."""
3000JJF
LINE
5
~
I
1901
16V
Short-circuit (AC and DC conditions)
The TDA 2003 can withstand a permanent short-circuit on the output for a supply voltage up to l6V.
Polarity inversion
High current (up to 5A) can be handled by the device with no damage for a longer period than the
blow-out time of a quick 1A fuse (normally connected in series with the supply).
This feature is added to avoid destruction if, during fitting to the car, a mistake on the connection of
the supply is made.
Open ground
When the radio is in the ON condition and the ground is accidentally opened, a standard audio amplifier
will be damaged. On the TDA 2003 protection diodes are included to avoid any damage.
Inductive load
A protection diode is provided between pin 4 and 5 (see the internal schematic diagram) to allow use of
the TDA 2003 with inductive loads.
In particular, the TDA 2003 can drive a coupling transformer for audio modulation.
DC voltage
The maximum operating DC voltage on the TDA 2003 is l8V.
However the device can withstand a DC voltage up to 28V with no damage. This could occur during
winter if two batteries were series connected to crank the engine.
Thermal shut-down
The presence of a thermal limiting circuit offers the following advantages:
1) an overload on the output (even if it is permanent), or an excessive ambient temperature can be easily
withstood.
2) the heat-sink can have a smaller factor of safety compared with that of a conventional circuit. There
is no device damage in the case of excessive junction temperature: all that happens is that Po (and
therefore Ptot ) and Id are reduced (figs. 25 and 26).
Fig. 25 - Output power and
drain current vs. case tem·
perature (RL = 4.0:)
.0
.0 r-r--'--r-r'~~rTl--'---"---''''::'';::-:r--",
v-;;14A -
(W)
RL
d
f-++-f-++-l-+-+-l
~ 10"(. f-++-f-++-t-+-+-l
3
4
f-++-Ic++-l
rr--.---"--.---"-,,,-,,-,-'TT--I,,
(WI
(A)
(A)
n.
f-t+"H-t-H--t-+-1-+-+-1-+-+-t
12
'0
Fig. 26 - Output power and
drain current vs. case tem·
perature (RL = 20)
H--t-H-t-H--j os
f-+...f.!!"+-++H++-+++-+-+-H 0.6
f-+-lP:J!O+-++H++-+++-+,,*-H 0.'
+-+-+-+-H->HH-j 0.6
f-++-H'\\-I-i 0.'
f--t+H+H++-+++-+--t'ltH o.2
1-++-H++-+--+-+-l-+-+-l~M--i 0.2
50
1.2
H-+-H-+-I-++-+
50
'00
630
100
PRATICAL CONSIDERATIONS
Printed circu it board
The layout shown in fig. 17 is recommended. If different layouts are used, the ground points of input 1
and input 2 must be well decoupled from the ground of the output through which a rather high current
flows.
Assembly suggestion
No electrical insulation is required between the package and the heat·sink. Pin length should be as short
as possible. The soldering temperature must not exceed 260°C for 12 seconds.
Application suggestions
The recommended component values are those shown in the application circuits of fig. 16. Different
values can be used. The following table is intended to aid the car-radio designer.
Component
Recommended
value
Cl
2.2 jLF
C2
C3
C4
C5
Cx
Purpose
Larger than
recommended value
Input DC
decoupling
Noise at switch-on,
switch-off
470 jLF
Ripple rejection
Degradation of SVR
0.1 jLF
Supply bypassing
Danger of oscillation
1000 jLF
Output coupling to
load
Higher low frequency
cutoff
0.1 jLF
Frequency stability
Danger of oscillation at
high frequencies with
inductive loads
1
~
2" B Rl
Upper frequency
cutoff
Lower bandwidth
Rl
(G v -1) • R2
R2
2.212
Setting of gain and
SVR
Degradation of SVR
R3
1 12
Frequency stability
Danger of oscillation at
high frequencies with
inductive loads
20 R2
Upper frequency
cutoff
Rx
Smaller than
recommended value
~
Setting of gain
631
Larger bandwidth
I ncrease of drain current
Poor high frequency
attenuation
Danger of oscillation
LINEAR INTEGRATED CIRCUIT
10 + 10W STEREO AMPLIFIER FOR CAR RADIO
The TDA 2004 is a class B dual audio power amplifier in MU LTIWATT ® package specifically designed
for car radio applications: stereo amplifiers are easily designed using this device that provides a high
current capability (up to 3.5A) and that can drive very low impedance loads (down to 1.6n).
Its main features are:
Low distortion.
Low noise.
High reliability of the chip and of the package with additional complete safety during operation thanks
to protections against:
output AC short circu it to grou nd
very inductive loads
overrating chip temperature
load dump voltage surge
fortuitous open ground
polarity inversion
Space and cost saving: very low number of external components, very simple mounting system with no
electrical isolation between the package and the heatsink (one screw only).
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10 (*)
10 (*)
Ptot
Tj,Tstg
(.)
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50 ms)
Output peak current (non repetitive t = 0.1 ms)
Output peak current (repetitive f ;;;, 10Hz)
Power dissipation at Tease = 60°C
Storage and junction temperature
18
28
40
4.5
3.5
30
-40 to 150
v
V
V
A
A
W
°C
The max. output current is internally limited.
ORDERING NUMBER: TDA 2004
Dimensions in mm
MECHANICAL DATA
6/82
632
I~
Ii
I'
CONNECTION DIAGRAM
(top view)
!I===
$/
Tab connected
BOOTSTRAP 1
OUTPUT 1
+VS
OUTPUT 2
BOOTSTRAP 2
GNO
INPUT+(2)
lNPUT-(2)
SVRR
lNPUT·(1)
INPUTt(l)
to pin 6
SCHEMATIC DIAGRAM
THERMAL DATA
Rth j-case
max
Thermal resistance junction-case
633
3
°C/W
Fig. 1 - Test and application circuit
INPUT(R)
2.2.u F
!~1~1~
C2
C7
lJn
Fig.2 - PC board and components layout (scale 1: 1)
GND
IN
(ll
GND
IN
.Vs
(R)
634
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Gv = 50 dB,
Rth (heatsink) =
4°C/W, unless otherwise specified)
Test conditions
Parameter
Vs
Supply voltage
Vo
Quiescent output voltage
Total quiescent drain current
Typ.
Max.
Unit
18
V
7.2
6.6
7.8
7.2
V
V
65
62
120
120
mA
mA
8
Vs~14.4V
6.6
5.0
Vs~13.2V
Id
Min.
Vs~14.4V
Vs~13.2V
IS8
Stand-by current
Pin 3 grounded
Po
Output power (each channel)
f
~
1 KHz
mA
5
d~
10%
Vs~14.4V
RL ~ 4D.
RL~3.2D.
RL ~ 2D.
RL ~ 1.6D.
,
Vs
~
6
7
9
10
6.5
8
10(*)
11
W
W
W
W
6.5
10
W
W
12
W
13.2V
RL ~ 3.2D.
RL ~ 1.6D.
6
9
Vs~16V
RL ~ 2 D.
d
Distortion (each channel)
f
~
1 KHz
Vs~14.4V
Po~ 50 mW
Vs ~ 14.4V
Po~ 50 mW
Vs ~ 13.2V
Po~ 50 mW
Vs ~ 13.2V
Po~ 50 mW
CT
Vi
Cross talk
I nput sensitivity
Vs
RL ~ 4D.
to 4W
RL ~ 2D.
to 6W
0.2
1
%
0.3
1
%
0.2
1
%
0.3
1
%
RL~3.2D.
to 3W
RL ~ 1.6D.
to 6W
~
14.4V
Vo~ 4 V rms
f ~ 1 KHz
f ~ 10KHz
RL ~ 4D.
50
40
f ~ 1 KHz
Po ~ 1W
RL ~ 4D.
RL~ 3.2D.
60
45
dB
dB
6
5.5
mV
mV
mV
300
Vi
Input saturation voltage
Ri
I nput resistance (non inverting
input)
f
~
1 KHz
Ri
Input resistance (inverting input)
f
~
1 KHz
fL
Low frequency roll off (-3 dB)
RL~
4D.
RL ~ 2D.
RL~ 3.2D.
RL ~ 1.6.11
fH
High frequency roll off (-3 dB)
RL ~ 4D.
RL ~ 2D.
RL~ 3.2D.
RL ~ 1.6D.
I
635
70
KD.
200
Kn
10
35
50
40
55
15
15
15
15
Hz
Hz
Hz
Hz
KHz
KHz
KHz
KHz
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameters
Gy
Gy
Voltage gain (open loop)
f = 1 KHz
Voltage gain (closed loop)
f = 1 KHz
Min.
Typ.
50
48
eN
Total input noise voltage
Rg= 10 Kn(O)
SVR
Supply voltage rejection
f'iPPle= 100 Hz Rg- 10 Kn
C3 = 10jJ.F V'iPPle=0.5V,ms
Efficiency
Vs =
R L=
R L=
Vs =
RL=
RL=
Thermal shut down case
temperature
TSd'
Unit
dB
51
dB
dB
0.5
Closed loop gain matching
1)
Max.
90
1.5
35
f = 1 KHz
Po= 6.5W
Po= lOW
f = 1 KHz
Po= 6.5W
Po= lOW
14.4V
4n
2n
13.2V
3.2n
1.6n
jJ.V
5
45
dB
70
60
%
%
70
60
%
%
R L =4n
Vs=14.4V
f = 1 KHz
Ptot = 5.5W
125
135
°C
(*) 9.3W Without Llootstrap.
(0) Bandwidth filter: 22 Hz to 22 KHz.
Fig. 4 - Quiescent drain
current vs. supply voltage
Fig.:3 - Quiescent output
voltage vs. supply voltage
Fig. 5 - Distortion vs. output power
G"'299f1
G4297
I.
Vo
(V)
/
/
/
V
/
V
/
/
/
t.1KHl
80
60
"
,
-
VS"12V Rl,12fi
--Vs·ltJ.VR l ,4n
-- ----
II
'11111
VSd12V R L,16,fl
VS"4.4V RLdn
'0
20
12
16
14
VslVl
Fig. 6 - Output power vs.
supply voltage
...""
Po
n
11111
Gy .50dB
100
/
10
IW
II
{mAl
10
ds1O~
I
12
".24/
V
V
/
"
12
V
./
V
V
VR L 12n
o
V
......
12
636
1.2
p~~
~~~iE33~~~~~~"~~'~2~n~
"'t~~~~~~~~~7~'R~~'nT'~n~
Po,2.5W
V
10
":"1=-i ll
~,
I
I
12
V
./
./
f"'"
,/
V
V
Vs=14.4\f
Gv=SOdB
Rl °1.6.n/
d.IO"r.
1/1'
0.'
Fig. 8 - Distortion vs. frequency
-
~ ~':~;~B
/RLsion
10
0.01
(W
hlKHz
G.,.5OdB
1/
i---"
"
12
Fig. 7 - Output power vs.
supply voltage
Po
I
I
I
16
Vs(V)
10
10'
10 4
1(Hz)
Fig.9 - Distortion vs. frequency
Fig. 11 - Supply voltage
rejection vs. frequency
Fig. 10 - Supply voltage
rejection vs. C3
G.4J0411
sv. r---,r-TO-rrncn---''''"T"TTTTTI
lOB)
f----j---jH+++1*C"""7,-lc-L+++t+tl
"'S.14./"V
~
f----jf-H+++1+1 'rlppl•• 100HZL
f----jf-H+++1+1 Vrippie.O.5 V
f----jf-H+++1+1 Gv.50dB
f----jf-H+++1+1 Rg.IOl(n
I
'0
20
30
40
~~~ _
Vs·14.4V
1tI---+-+t+I-t1lI-H+l-Hlll
-
Gy:SOdB
CJilOJ.lF
Ht---++ttf-tftt-H-H+IllI
...........
f----jf-.......
-f''''''''<+l+++--f-+-I+++1ftj
'0 f-++++ttItl---+-+t+I+Hf-H-HfIIH
6Of---+-+-H++Ht--+--+++++tH
10
'0
Fig. 12 - Supply voltage
rejection vs. values of capacitors C2 and C3
!Fig.13 - Supply voltage
rejection vs. values of capacitors C2 and C3
f (HlI:I
Fig. 14 - Gain vs. input
sensitivity
G-4l0&
sv.)
sv.
III
III
VS~1".4V
(dB
RL~4fl
Rg,1)KQ
Gv· J 90/1n
{dBI
40
/'
./
'0
"
"
200
'00
38
/
'0
L
20
/
~
"
V
50
P: =0.5
30
2.
22
10
20
'0
..
."
G,
(dB)
'0
20
Fig. 16 - Total power dissipation and efficiency vs.
output powp.r
Fig.15 - Gain vs. input
sensitivity
'0
'00
300
. ..
"
I"",
Yj(mV)
12
60
IWI ~-+++-H-+'+-+-H-++~HI~J
P,ot
500
••
,.
4Z
·.,w
..
100
so
"o.sw
30
fI/
22
'00
300
...
Vi (mY)
Ptot
'0
17'
"-
-/.
"'S·144Y
40
RLs 2n
hll---+c---.---~___il
C'I '.',oF
1
2200lllF
Cll
5 -t.06 51 2
647
R3 (n)
ELECTRICAL CHARACTERISTICS (Refer to the stereo application circuit, Tamb = 25°C,
Gy= 50 dB, Rth(heatsink)= 4°CIW, unless otherwise specified).
Parameters
Test conditions
Vs
Supply voltage
Vo
Quiescent output voltage
Vs = 14.4V
Vs = 13.2V
Id
Total quiescent drain current
Vs = 14.4V
Vs = 13.2V
Po
Output power (each channel)
f = 1 KHz
Vs = 14.4V
Vs=16V
Distortion (each channell
CT
Cross talk (0)
Vi
Input saturation voltage
Vi
Input sensitivity
6.6
6
d = 10%
R L =4n
R L =3.2n
R L =2n
R L = 1.6n
R L = 3.2n
R L = 1.6n
R L = 2n
6
7
9
10
6
9
f = 1 KHz
R L =4n
Vs = 14.4V
Po = 50 mW to 4W
R L =2n
Vs = 14.4V
Po = 50 mW to 6W
R L = 3.2n
Vs = 13.2V
Po= 50 mW to 3W
R L = 1.6n
Vs = 13.2V
Po = 40 mW to 6W
Vs= 14.4V
R L =4n
Vo = 4V,ms
Rg= 10 Kn
f = 1 KHz
f = 1 KHz
fL
Low frequency roll off (-3 dB)
R L = 2n
fH
High frequency roll off (-3 dB)
R L = 2n
Gv
Voltage gain (open loop)
f = 1 KHz
f = 1 KHz
70
inverting input
Voltage gain (closed loop)
eN
Total input noise voltage
18
V
7.2
6.6
7.8
7.2
V
V
65
62
120
120
mA
mA
6.5
8
10
11
6.5
10
12
W
W
W
W
W
W
W
0.2
1
%
0.3
1
%
0.2
1
%
0.3
1
%
dB
dB
45
Po= 1W
R L =4n
R ...= 3.2n
f = 1 KHz non inverting input
Closed loop gain matching
Unit
mV
300
I nput resistance
Gy
Max.
60
f = 10 KHz
Ri
AG y
Typ.
8
Vs = 13.2V
d
Min.
6
5.5
mV
200
Kn
Kn
10
50
KHz
15
dB
90
48
50
51
(0)
For TDA 2005S only.
(00) Bandwidth filter: 22 Hz to 22 KHz.
648
1.5
dB
dB
0.5
Rg= 10 Kn (00)
Hz
5
p.V
I
I
I,,-
ELECTRICAL CHARACTERISTICS (continued)
I'
I'
Parameters
Test conditions
SVR
Supply voltage rejection
Rg= 10 K11 fripple= 100 Hz
C 3= 10 /LF V riPPle= 0.5V
1/
Efficiency
Vs = 14.4V
R L =411
R L = 211
Vs = 13.2V
R L = 3.211
R L = 1.611
f = 1 KHz
Po= 6.5W
Po= 10W
f = 1 KHz
Po= 6.5W
Po= 10W
Vs = 14.4V
Ptot = 6.6W
R L = 211
Thermal shut-down case
temperature
TSd
Fig. 8 - Quiescent output
voltage vs. supply voltage
Min.
Typ.
35
45
Max.
Unit
dB
i'
120
Fig. 9 - Quiescent drain current vs. supply voltage
70
60
%
%
70
60
%
%
130
°C
Fig. 10- Distortion vs. output power
Vo
tv)
(mAl
/
1/
V
IV
100
/
80
/
IIIII
f-f-f-~-1-,----j'---'~--+--+--+--I
II
/
V
/
V
10
12
16
VSIVI
10
Fig. 11 - Output power vs.
supply voltage
Po
tW
"
,
1
G vs50dB
I
I
d ~ '10-"
i
f~ll(Hz
-
1
i
12
I
I
,/
,/
1/
v
%l
I
I
10
12
d
RL~
~10·J.
1.6.n
V
12
/
V
/
V
,/
/RL~J.2n
1.2
o.s
/'
'"
Fig. 13 - Distortion vs.
frequency
hlKHz
Gv~SOdB
~L:4Il
I
I.A"
V
r-
1/
0.1
I
tW)
I Rl~2n/
I
I
Fig. 12 - Output power vs.
supply voltage
Po
I
I
0.01
12
./
V
".,
"'
V
10
12
649
'I,
16
VS(VI
11
10
10'
1)4
11Hz)
I
I
"
Fig. 14 frequency
Distorsion vs.
Fig. 15 - Supply voltage rejection
VS.
C3
Fig. 16 - Supply voltage
rejection vs. frequency
G-4306/1
,-
'iSd4."V
Gv=50dB
C3'\O/JF
-
Iii
I',
Rg_ 0
i--J'
,
! '
I ,~9·lOKJl
I
30
I
20
'I
I
II
III
I
!
10
10'
10~
10'
Fig. 17 - Supply voltage
rejection vs. values of capacitors C 2 and C 3
5'"
Vs:14.I,V
Rl·4,Q
Rg,1OKn
G y .l000110D
t r l pp l.,100Hz
G,
"ffi
'Is =14.4'0'
1 : 1kHz
RL = 411
54
C2'22iJ~
,500
50
/vr
200
46
~2,5j..JF
/
I (Hz)
G,
U-
/ C Z,220j.JF
50
10'
Fig. 19 - Gain vs. input
sensitivity
Fig. 18 - Supply voltage rejection vs. values of capacitors C 2 and C3
(dBI
10'
10
10
f{Hzl
Po -6W
42
100
/
30
20~
I
I,
i
I
/
, I' ill
~
"
V
20
!
. 10
Fig. 20 - Gain vs. input
sensitivity
+++
:
!
I
20
26
I
,
22
10
20
Fig. 21 - Total power dissipation and efficiency vs.
output power (bridge)
0,
50
P , 0,5
30
30
100
300
"
Vi (mV)
Fig. 22 - Total power dissipation and efficiency vs.
output power
Ptot
,WI
I Vs·14.4
: If :lkH
RL-2Il.
500
I
60
200
46
42
3S
40
" =--.:.'"
30
,,--+
22
Po' lOW
~-t-.
R
100
+
.Q,SW
Ii
11+
--
20
,
100
300
"
"',(I'T'V)
20
650
24
Po(W)
10
Po(W)
APPLICATION INFORMATION
Fig. 23 - 10 + 10W stereo amplifier with ton(' balance and
loudness control
Fig. 24
Tone control
response (circuit of fig. 23)
H-c:::J-~~1
.---blOiJ F
.,
I
INPUHLJ
1--=---'----'--'
.,
.,
.,
JNPUT(RJ
J:~'=.6JKn--~--~--'
Fig. 25 - 20W Bus amplifier
VS •• 14.4V
18Ka
22
IJ
F
r
10/(a.
lOKn
lOKn
2Z001JF
..,~ol:,_":____,.o_K_~K_n _:_:_~ ~,-",+
__....
__.....
__________-'-I
OJ!.
on
on
an
$-4350/1
651
Fig. 26 - Simple 20W two way amplifier (fc = 2 KHz)
2200,uF
8
lKn~'
~~
R3..L
..,.. C7
0: O.1,uF
,,100 /-IF
-----f'-c-i
R7
WOOFER
In
C,~n QR'
.
I
INPUT
..J.. ..L C10 .J...
>-_+'~O_ -t-- -1"--1l~
lKf) rlR5
l00~F
100.uF'~
2
nL . J
-U,
=
lil
(8
Q)'
R8
CO
lon
2.2.u F
I
3
e1 !
..J.
.J...
...
Fig. 27 - Bridge amplifier circuit suited for low-gain applications (G v = 34 dB)
R1
INPUT!A
1
2.2,.uF
","F
~
R7
111
5- 541,7/1
652
TWE.ETER
APPLICATION SUGGESTION
The recommended values of the components are those shown on Bridge application circuit of fig. 1.
Different values can be used, the following table can help the designer.
Component
Recommended
Value
Kn
RJ
120
R2
1
Kn
R3
2
Kn
R4 and Rs
12
R6 and R7
1
Larger than
Purpose
Optimization of the
output symmetry
Smaller Po max
Smaller than
Smaller Po max
Closed loop gain
setting (see BRIDGE
AMPLIFIER
DESIGN)
n
n
Frequency stabil ity
C1
2.2/-lF
Input DC
decoupling
C2
2.21'F
Optimization of
turn on pop and
tu rn on delay.
C3
O.lI'F
Supply by pass
C4
10l'F
R ipp Ie Rejection
Danger of oscillation
at high frequency
with inductive loads
High turn on delay
Higher turn on pop.
Higher low frequency
cutoff.
Increase of noise.
Danger of oscillation.
I ncrease of SV R.
Increase of the
Degradation of SVR.
switch-on time.
Cs and C 7
100 I'F
Bootstrapping
Increase of distortion
at low frequency.
C 6 and C 8
220 I'F
Feedback input
DC decoupling, low
frequency cutoff.
Higher low frequency
cutoff.
C 9 and C IO
O.lI'F
Frequency stability.
Danger of oscillation.
653
BUILT-IN PROTECTION SYSTEMS
Load dump voltage surge
The TDA 2005 has a circuit which enables it to withstand a voltage pulse train, on pin 9, of the type
shown in fig. 29.
If the supply voltage peaks to more than 40V, then an LC filter must be inserted between the supply
and pin 9, in order to assure that the pulses at pin 9 will be held within the limits shown.
A suggested LC network is shown in fig. 28. With this network, a train of pulses with amplitude up to
l20V and width of 2 ms can be applied at point A. This type of protection is ON when the supply
voltage (pulse or DC) exceeds l8V. For th is reason the maximum operating supply voltage is l8V.
Fig. 29
Fig.28
FROM
A
L,,2mH
SUPPLY ~TO PIN 9
LINE
IJ.£ "''''''
16V
3000f.JF
5_1901
14.4
t1'
-~
I
I
---~~
Short circuit (AC and DC conditions)
The TDA 2005 can withstand a permanent short-circuit on the output for a supply voltage up to 16V.
Polarity inversion
High current (up to lOA) can be handled by the device with no damage for a longer period than the
blow-out time of a quick 2A fuse (normally connected in series with the supply). This feature is added
to avoid destruction, if during fitting to the car, a mistake on the connection of the supply is made.
Open ground
When the radio is in the ON condition and the ground is accidentally opened, a standard audio amplifier
will be damaged. On the TDA 2005 protection diodes are included to avoid any damage.
I nductive load
A protection diode is provided to allow use of the TDA 2005 with inductive loads.
DC voltage
The maximum operating DC voltage for the TDA 2005 is 18V.
However the device can withstand a DC voltage up to 28V with no damage. This could occur during
winter if two batteries are series connected to crank the engine.
Thermal shut-down
The presence of a thermal limiting circuit offers the following advantages:
1) an overload on the output (even if it is permanent), or an excessive ambient temperature can be easily
withstood.
2) the heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no device damage in the case of excessive junction temperature: all that happens is that Po (and
therefore Ptot ) and Id are reduced.
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance); fig. 30 shows this dissipable power as a function of ambient temperature for different
therma I resistance.
654
Fig. 30 - Maximum allow·
able power dissipation vs.
ambient temperature
Fig. 31 - Output power and
drain current vs. case temperature
)~i-+-t
r--"
i
I.
_.
1
1'5'''.''
I:,L,~"~
.J ld
Fig. 32 - Output power and
drain current vs. case temperature
"
''I
~
~
\
'0
1
'\
,
'.
I
I
t-
03
1
eo
Tease
(OCJ
160 Tcase-(OC)
Loudspeaker protection
The circuit offers loudspeaker protection during short circuit for one wire to ground.
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the MUL TIWATT® package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon
grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces.
Fig. 33 - Mounting examples
o
,,
,,
655
--
LINEAR INTEGRATED CIRCUIT
lOW AUDIO AMPLIFIER
The TDA 2006 is a monolithic integrated circuit in Pentawatt® package, intended for use as a low
frequency class" AB" amplifier. At ± 12V, d = 10% typically it provides 12W output power on a 4n
load and BW on a Bn. The TDA 2006 provides high output current and has very low harmonic and
cross-over distortion. Further the device incorporates an original (and patented) short circuit protection
system comprising an arrangement for automatically limiting the dissipated power so as to keep the
working point of the output transistors within their safe operating area. A conventional thermal
shutdown system is also included. The TDA 2006 is pin to pin equivalent to the TDA 2030.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
Vi
10
Ptot
T stg , T j
Supply voltage
Input voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at T case = 90°C
Storage and junction temperature
± 15
Vs
± 12
3
20
-40 to 150
V
V
A
W
°C
ORDERING NUMBERS: TDA 2006H; TDA 2006V
MECHANICAL DATA
6/B2
Dimensions in mm
656
CONNECTION DIAGRAM
C)
~iiii:'VS
OUTPUT
-Vs
INVERTING INPUT
NON INVERTING INPUT
5-2628/1
tab connected to pin 3
SCHEMATIC DIAGRAM
657
TEST AND APPLICATION CIRCUIT
C5
0.22 pF
5-3916
THERMAL DATA
Rth _i
case
Thermal resistance junction-case
max
3
°CIW
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs= ±12V, T amb = 25°C unless
otherwise specified)
Parameters
Vs
Supply voltage
Id
Quiescent drain current
Ib
Input bias current
Test conditions
Min.
Typ.
Max.
Unit
± 15
V
40
SO
mA
0.2
3
IlA
±6
Vs=±15V
Vos
Input offset voltage
los
Input offset current
±
Vos
Output offset voltage
± 10
Po
Output power
±S
d = 10%
f = 1 KHz
R L=4n
RL=Sn
658
6
mV
SO
12
S
nA
± 100
mV
W
W
ELECTRICAL CHARACTERISTICS
(continued)
Parameter
d
Distortion
Test conditions
Min.
Typ.
Max.
Units
Po~O.l
to8W
RL ~ 4!1
f ~ 1 KHz
0.2
%
Po~
0.1 to 4W
RL ~ 8!1
1 ~ 1 KHz
Vi
Input sensitivity
Po~
P0
B
~
lOW
6W
Rj
I nput resistance (pin 1)
Gv
Voltage gain (open loop)
Gv
Voltage gain (closed loop)
eN
I nput noise voltage
iN
InpOt noise current
SVR
Supply voltage rejection
RL ~ 4!1
0.5
f
~
29.5
B (-3 dB) ~ 22Hz to 22kHz
RL~4!1
RL~
4n
22 Kn
1ripPle~ 100 Hz
Drain current
Po~12W
P0 :
Tj
1
%
200
220
mV
mV
1 0 to 140,000
Hz
5
M!1
75
dB
1 KHz
Rg~
Id
1 ~ 1 KHz
RL ~ 4!1
R L ~ 8!1
Frequency response (-3 dB)
Po~8W
I
0.1
8W
Thermal shut down junction
temperatu re
(*) Relerring to lig. 15, single supply.
659
40
30
30.5
dB
3
10
IN
80
200
pA
50
dB
850
500
mA
mA
145
°C
(*)
RL~ 4!!
R L : B!1
Fig. 1 - Output power vs.
supply voltage
I
I
0)
IW
d ~,o 'I.
f :1KHz
16
Fig.2 - Distortion vs. output
power
("10
Fig. 3 - Distortion vs. frequency
)I--+--t--t+tf!f---j
RL=t.n/
V
VI
V RL"7
/
VI
,
/
./
/' V
!
I
I
Fig. 4 - Distortion vs. frequency
Fig.5 -Sensitivity vs. output
power
')f--- _..1.._L.' ..
'
R L,,4n
I
ImV
0
IT
++
_l
G v = 30dB
18 0
f (Hz)
Fig. 6 - Sensitivity vs. output
power
-r-~
vI",-l~r
iL
?'
60
=+
A"'"
0.3
G v =_40d!L-
~i
I--:-
--f
-t
! ~
J !
10'
Fig.7 - Frequency response
with different values of the
rolloff capacitor Cs (see
fig. 13)
G,r----r---,----,-----~~
(dB)
Fig. 8 - Value of C s vs.
voltage gain for different
bandwidths (see fig. 13) ,
C,
(;-4173
IpF )
Vs= ± 12 v
RS;' 3R2
80
B-20KHz
10'
" 1\
~
B=50KHz
1\
20
1\
10
10
10 4
- !
's';"H-+- f+
, =lKHz
0.2
w'
G-<;1
d"~~-'TP~-'TITmr~~~
(0/0)
10
10'
10
"
10'
1\
G v (dB)50
30
660
Fig. 9 - Qu iescent current
vs. supply voltage
Fig. 10 - Supply voltage
rejection vs. voltage gain
Fig. 11 - Power dissipation
and efficiency vs. output
power
Fig. 12 - Maximum power
dissipation vs. supply voltage (sine wave operation)
o~ " ,
,
I
)
i
I
, ,lK<, I
:
I
R L< ~
n
y
I
V
./
--
,./
Po (W)
Fig. 13 - Application circuit with
split power supply
V
v
RL:Sfi
V
Fig. 14 - P.C. board and component
layout for the circuit of fig. 13
661
Fig. 15 - Application circuit with single
power supply
Fig. 16 - P.C. board and component
layout for the circuit of fig. 15
Fig. 17 - Bridge amplifier configuration with split power supply (Po
lN40Ql
-;\0.22 >IF
1!l
s- '316
662
= 24W, Vs = ± 12V)
PRACTICAL CONSIDERATION
Printed circuit board
The layout shown in fig. 14 should be adopted by the designers. If different layout are used, the ground
points of input 1 and input 2 must be well decoupled from ground of the output on which a rather high
current flows.
Assembly suggestion
No electrical isolation is needed between the package and the heat-sink with single supply voltage
configuration.
Application suggestion
The recommended values of the components are the ones shown on application circuits of fig. 13.
Different values can be used. The following table can help the designers.
Larger than
recommended value
Smaller than
recommended value
Increase of gain
Decrease of gain
Closed loop gain
setting
Decrease of ga i n
Increase pf ga in
22 K!1
Non inverting input
biasing
Increase of input
impedance
Decrease of input
impedance
R4
1!1
Frequency stability
Danger of oscillation at
high frequencies with
inductive loads
R5
3 R2
Upper frequency
cutoff
Poor high frequencies
attenuation
C1
2.21'F
Input DC decoupling
I ncrease of low
freqencies cut off
C2
221'F
Inverting input DC,
decoupling
I ncrease of low
frequencies cutoff
C 3C 4
0.1 I'F
Supply voltage by pass
Danger of oscillation
C 5C6
100l'F
Supply voltage by pass
Danger of oscillation
C7
0.221'F
Frequency stability
Danger of oscillation
Ca
1
21TBR J
Upper frequency
cutoff
DID2
lN4001
To protect the device against output voltage spikes.
Component
Recommended
value
Rl
22 K!1
R2
680!1
R3
Purpose
Closed loop gain
setting
Lower bandwidth
663
Danger of oscillation
Larger bandwidth
SHORT CIRCUIT PROTECTION
The TDA 2006 has an original circuit which limits the current of the output transistors. Fig. 18 shows
that the maximum output current is a function of the collector emitter voltage; hence the output
transistors work within their safe operating area (fig. 19).
This function can therefore be considered as being peak power limiting rather than simple current
limiting. The TDA 2006 is thus protected against temporary overloads or short circuit. Should the short
circuit exist for a longer time, the thermal shutdown protection keeps the junction temperature within
safe limits.
Fig. 18 - Maximum output
current vs. voltage V Ce(sat)
across each output transistor
Fig. 19 - Safe operating area and
collector characteristics of the pro·
tected power transistor
\
\....,--P tat ::k
\
Ie
max,
\
\
5-0764/1
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent), or air above limit ambient temperature can be
easily supported since the T j cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
If for any reason, the junction temperature increases up to 150°C, the thermal shutdown simply
reduces the power dissipation and the current consumption.
664
Fig. 20 - Output power and
drain current VS. case temperature (R L = 40.)
Po
Fig. 21 - Output power and
drain current VS. case temperature (R L = Bn)
•.
I":1
f---·
!':-
,..-..-.~
(W)~
~....,
-r-
---
~---T
T--_
r--- ---'"P -
: :j
o - .- - - - - .-
.- . . _..j
..
-- - .-- ~
- ---- 1
iillll
- ~--~~-t r--.,.-t~.-~~ ................. ~
1
: :Joe
. . .---- -~--~- +-+
::,:~lO.6
.=r~-==:.
.•... _ -
0.4
0.2
so
-+-~+--t-
O6
0.4
•
0.2
so
100
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its
thermal resistance); fig. 22 shows this dissipable power as a function of ambient temperature for different thermal resistances.
Fig. 22 - Maximum allowable power dissipation VS.
ambient temperature
20
Fig. 23 - Example of heatsink
I
f - - -....."'T"-__
16
I
12
-so
so
100
150 TambC"Cl
Dimension suggestion
The following table shows the lenght of the heatsink
in fig. 23 for several values of Ptot and Rth .
P tot (WI
12
8
6
Lenght of
heatsink (mml
60
40
30
Rth of heats ink
4.2
6.2
8.3
(oeMiI
665
L1N,EAR INTEGRATED CIRCUIT
12W AUDIO AMPLIFIER (V s
=
22V, RL = 4[2)
The TDA 2008 is a monolithic class B audio power amplifier in Pentawatt® package designed for driving
low impedance loads (down to 3.2n). The device provides a high output current capability (up to 3A),
very low harmonic and crossover distortion.
In addition, the device offers the following features:
very low number of external components
assembly ease, due to PentawattQ3) power package with no electrical insulation requirement
space and cost saving
high reliability
flexibility in use
thermal protection
ABSOLUTE MAXIMUM RATINGS
Vs
io
10
Ptot
T stg ' T j
DC supply voltage
Output peak current (repetitive)
Output peak current (non repetitive)
Power dissipation at T case= 90°C
Storage and junction temperatu re
ORDERING NUMBERS:
28
3
4
20
W
-40 to 150
°C
TDA 2008V
MECHANICAL DATA
6/82
V
A
A
Dimensions in mm
666
CONNECTION DIAGRAM
(top view)
IC) ;IIr
r-
I
r*
"om'
2
1
-
INPUT
INPUT
c
5-1b94!l
tab connected to pin 3
SCHEMATIC DIAGRAM
667
:ii::;
INVERTING
NON INVERTING
DC TEST CIRCUIT
,-----------~--------~J+vs
:!100nF
470}JF
R2
nl
.------.
-------;U~
5- 4009
--
AC TEST CIRCUIT
C4
1000 ).IF
4
Rl
470 ).IF
668
J..
THERMAL DATA
Rth
j-case
max
Thermal resistance junction-case
3
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,V s = 22V, T amb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Vo
Quiescent output voltage
(pin 4)
Id
Quiescent drain current
(pin 5)
Po
Output power
Test conditions
I nput sensitivity
65
d: 10%
R L : 8St
f : 1 KHz
R L : 4St
d
Distortion
f : 1 KHz
Po = 0.05 to 4W R L = 8St
Po = 0.05 to 6W R L = 4St
Voltage gain (open loop)
f : 1 KHz
f = 1 KHz
Gv
Voltage gain (closed loop)
eN
I nput noise voltage
10
R L : 8St
R L : 8St
R L : 4St
R L: 4St
Po: 1W
R L : 4St
Gv
Unit
28
V
V
115
70
mA
8
W
12
W
mV
300
f : 1 KHz
Po: 0.5W
Po: 8W
Po: 0.5W
Po: 12W
Frequency response
(-3 dB)
I nput resistance (pin 1)
Max.
10.5
B
Ri
Typ.
10
Vi (RMS) I nput saturation voltage
Vi
Min.
20
80
14
70
mV
mV
mV
mV
40 to 15000
Hz
0.15
0.15
%
%
150
KSt
80
dB
RL = 8St
39.5
40
40.5
dB
1
5
}lV
60
200
pA
BW= 22Hz to 22 KHz
iN
I nput noise cu rrent
SVR
Supply voltage rejection
V ripple= 0.5V
R g : 10KSt
R L =4St
669
f=100Hz
f= 15 KHz
30
36
dB
36
dB
6/81
APPLICATION INFORMATION
Fig. 1 - Typical application circuit
,-----c-iI..----,O
Fig. 2 - P.C. board and component layout for
the circuit of fig. 1 (1: 1 scale)
Co,-0126
Vs
..,.~~
v
.....
1
c!
'o--~~. . t
5
Fig. 3 - 25W bridge configuration application
circuit (0)
Fig. 4 - P.C. board and component layout for
the circuit of fig. 3 (1: 1 scale)
I
'----_--".:c3~11__---+_C:::J------~~
15 )JF
10pF
S - GO, 2
(0 I The value of the capacitors C3 and C4 are different to optimize the SVR (Typ. = 40 dB!
670
Fig. 5 - Vertical deflection for count-down circuits
2200,u F
lN4001
lN4001
y :'.4.!l,3mH ,3.5App
5 - 4007
671
LINEAR INTEGRATED CIRCUIT
10 + 10W HIGH QUALITY STEREO AMPLIFIER
The TDA 2009 is class AS dual Hi-Fi Audio power amplifier
cially designed for high quality stereo applications as Hi-Fi TV and
High output power (10 + lOW min.@ d = 0.5%)
High current capability (up to 3.5A)
Thermal overload protection
Space and cost saving: very low number of
Multiwatt@ package.
"'''''"hn'r....onto
Vs
10
10
Ptot
T519' Tj
(repetitive f ;;;. 20 Hz)
(fN:e·~t (non repetitive, t = 100 /-ls)
Power
ipation at Tcase= 90°C
Storage lind junction temperature
and simple mounting thanks to the
28
3.5
4.5
20
-40 to 150
V
A
A
W
°C
ORDERING NUMBER: TDA 2009
MECHANICAL DATA
6/82
Dimensions in mm
672
CONNECTION DIAGRAM
(top view)
N.C.
OUTPUT (1)
+Vs
OUTPUT (2)
N.C.
GNO
NON INV.INPUT(2)
INV. INPUT (2)
SVRR
-$2
INV. INPUT (1)
NON INV.INPUT(1)
s- 5203
SCHEMATIC DIAGRAM
THERMAL DATA
Rth j-case
Thermal resistance junction-case
max
673
3
Fig. 1 - Test circuit (G v
= 36 dB)
+Vs
2Z,uF
I
Ie3
2.2IJF
~11---4------F"'"
(Ll
Cl
IN
2.21JF
(Rl
C2
~II---'+---l
5_5188
Fig. 2 - P.C. board and components layout of the circuit of fig. 1 (1
674
1 scale)
ELECTRICAL CHARACTERISTICS (Refer to the stereo application circuit, Tamb = 25°C,
Gv
= 36 dB, unless otherwise specified)
Test conditions
Parameters
Min.
Typ.
Vs
Supply voltage
Vo
Qu iescent output voltage
Vs
~
23V
11
Id
Total quiescent drain current
Vs
~
23V
80
Po
Output power leach channell
8
RL~
4 n
n
RL=4 n
RL~ 8 n
10
12
5.5
7
7
RL~8
Vs~18V
CT
Distortion leach channel)
Rg
Vi
Input saturation voltage Irmsl
R;
Input resistance
f
120
mA
~
W
W
W
W
%
0.05
00
f
~
1 KHz
60
dB
10 Kn
f
~
10 KHz
50
dB
~
1 KHz non inverting input
70
Low frequency roll off 1-3 dB)
~
mV
200
Kn
10
Kn
15
Hz
80
KHz
85
dB
4n
fH
High frequency roll off 1-3 dB)
Gv
Voltage gain lopen loop)
f
~
1 KHz
Gv
Voltage gain Iclosed loop)
f
~
1 KHz
6G v
Closed loop gain matching
eN
Total input noise voltage
Supply voltage rejection
leach channell
V
300
RL
SVR
V
0.1
inverting input
fL
28
4
f ~ 1 KHz
Vs ~ 23V
RL~ 4 n
Po~ 100 mW to 8W
Vs ~ 23V
RL~ 8 n
Po~ 100 mW to 3W
RL ~
Cross talk 1°° o I
Unit
f~40Hzt016KHz
d ~ 0.5%
Vs ~ 23V
d
Max.
35.5
36
36.5
dB
0.5
dB
Rg = 10 Kn 1°)
1.5
IN
Rg ~ 10 Kn 1°°1
2
MV
55
dB
145
°c
Rg = 10 Kn
fripPle~ 100 Hz
V ripple= 0.5V
TJ
Thermal shut-down junction
temperature
1°) Curve A.
1°°) 22 Hz to 22 KHz.
(000
675
I
Optimized test box.
Fig. 3 - Output power vs.
supply voltage
Fig. 5 - Distortion vs. output power
Fig. 4 - Output power vs.
supply voltage
6-466211
,...
d
I
I IIIIII
"1Z
0.'
I
0.5
H--"-r-+--l--
11
,
0.4
0.3
16KHz
E" n
16KHz
=-~ii'
0.1
0.1
10
12
14
16
18
riy. u -
20
22
21.
Lii:'luriiull
26
'1 s (V)
V!).
11t:-
10
·f
d
I
I
I IIIIW
I
LH:s~23V
~,,36dB
I
I
I Po'" loW
t II1
0.3
d
0.1
01
..
,
f-
~
4ni
T
.3
I
10
,
50
I
I
V
"
/'
''/
10K
50
10
f (Hz)
"
10
,--+++- ~-
70
11
10
/1
~J
1--'10+10W
I STEREO
ft'
i~
,/
10
f (Hz)
.!L.
'!-
--;-
j
~
II-T-
30
10
CJ (pFl
Fig. 11 - Total power dissipation and efficiency vs.
output power
,
.....- ...,....;
V
1----+-!+HttH-
'Is (V)
,
Pto
60
16
11
18
Fig. 10 - Total power dissipation an efficiency vs. output power
(;-4566
1---+-++t+i11t--+-t-!-t+tH!--
100
1---J,Lh--Pi"h,f-~+-+++++++i
V
SVRr-'-TTnnm---'--rTTTmr~PC'i'i'nrn
10
Ii
,",Ullvili.
./'
Fig. 9
Supply voltage
rejection vs. frequency
30
i
,I
,
~
70
-
--t
~
II
dB1
,
/
100
(
0.1
Vs(V)
I
I,
en
lKlt;
I
,
Ii
II
60
I
I
30
- -
I
: I
05
26
"
I I I
.6
22
ri~. 7 - GLiia5Ci;;j-,'t
vs. supply voltage
quency
".
18
i
,
I,
,.
I
I !~~:;!~
I.
'.1
60
I·-+~I---
~ot~!l~!llsill-fl~~lc!!i"!l
,WI
P tot
4
+-
~r-+Ts~23V
Rl:" !l
f
12
2
'" 1KHz
16
676
20
24
Po(W)
'1$=23'1
Rl"B il.
f ",1KHz
10
12
14
16
Po (W)
APPLICATION INFORMATION
Fig. 12 - Typical application circuit
2200,uF
1.2Kfl
RI
.t:a
To'~F
I
•
C6
~~
220,uF
R2
IBn
IN
QR5
In
1
2.2,uF
o.----tC2If---'+--l·
(Ri
'·°"'1
r'
RL
RL
R6
1
_'I!
5_5189
Fig. 13 - 10 + 10W stereo amplifier with tone balance and
loudness control
Fig. 14 - Tone control response (circuit of fig. 13)
INPUHl)
T
~1
22d
~4JKO
.6
I
P1
100""
Kn
.1,
INPUT(RJ
1
O.22/-lF
1/1
TDA1009
5-5190
677
APPLICATION INFORMATION (continued)
Fig. 15 - 10 + lOW high quality cassette player
'-~~~~~~~~~~~~
__-'~~~~f-~~~~~~~~~~~~~~~~~-o."
I TONE
'8K~
.O~F~---;-----=---.
r-;l,- - 82KJl.
_
~~
~
...
___
'"~
5,6 Kil
:;i3nFU681l.
,
,
'l_~'6KJl.'
i
h21~'F'~F
{R).L 4.7/OO~F
IN
2.2~F
o----------iil-C-,-'-1'-.r.-..
r
2.2}.JF
C25
5_519411
Fig. 19 - P.C. board and components layout of the circuit of fig. 18 (1
C5-0153
Vi
GND
680
OUT B OUT A
1 scale)
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 12. Different
values can be used; the following table can help the designer.
Component
R1 and R3
Recomm.
value
1.2
Larger than
Purpose
Kn
Smaller than
I ncrease of gain
Decrease of gain
Decrease of gain
I ncrease of gain
Close loop gain setting
R2 and R4
18
R5 and R6
1
n
n
Frequency stability
Danger of oscillation at
high frequency with
inductive load
C1 and C2
2.21'F
Input DC decoupling
High turn-on delay
High turn-on pop
Higher low frequency
cutoff. I ncrease of noise
C3
221'F
Ripple rejection
Better SVR.
I ncrease of the
switch-on time
Degradation of SVR.
C6 and C7
220l'F
Feedback I nput DC
decoupling.
C8 and C9
0.11'F
Frequency stabil ity.
Danger of oscillation.
C10andC11
1000 I'F to
2200l'F
Output DC decoupling.
Higher low-frequency
cut-off.
681
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the MULTIWATT® package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon
grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces.
Fig. 20 - Mounting examples
/
.
......
682
LINEAR INTEGRATED CIRCUIT
12W Hi-Fi AUDIO AMPLIFIER
The TDA 2010 is a monolithic integrated operational amplifier in a 14-lead quad in-line plastic package, inteded for use as a low frequency class B power amplifier. Typically it provides 12W output
power (d = 1% ) at ± 14V /4n; at V s = ± 14V the guaranteed output power is 10W on a 4n load and
8W on a 8n load (DIN norm 45500). The TDA 2010 provides high output current (up to 3.5 A) and
has very low harmonic and cross-over distortion. Further, the device incorporates an original (and
patented) short circuit protection system, comprising an arrangement for automatically limiting the
dissipated power so as to keep to working point of the output transistors within their safe operating
area. A conventional thermal shut-down system is also included. The TDA 2010 is pin to pin equivalent
to TDA 2020.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
Vi
10
Ptot
T stg , T j
Supply voltage
I nput voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at T case < 95°C
Storage and junction temperature
ORDERING NUMERS:
TDA
TDA
TDA
TDA
2010
2010
2010
2010
882
B92
BC2
BD2
± 18
Vs
± 15
3.5
18
-40 to 150
V
V
A
W
°C
dual in-line plastic package
quad in-line plastic package
dual in-line plastic package with spacer
quad in-line plastic package with spacer
MECHANICAL DATA
Dimensions in mm
683
6/82
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
~~----t,--i;----+_
I
rtJ
12
POWER lINtYlNG
10
CO ...PEttSATlON
9
8
~-J+----*----+-~ ~-+-+--I:::'
I
I,
II
i I
I
•
I
COIolPENSATlON
INVERTING
INPUT
The copper slug is electrically
connected to pin 5 (substrate)
I
I
l_L
l-.~_J----~------,_-,,~---o
,6
TEST CIRCUIT
*
02
*IN 4001
5-113912
OR EQUIVALENT
THERMAL DATA
max
Thermal resistance junction-case
684
I
i;1
l'I
.
Ii
i
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, V s = ± 14V, T amb = 25°C unless otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Ib
I nput bias current
Vos
I nput offset voltage
Test conditions
I nput offset current
Vos
Output offset voltage
Po
Output power
Typ.
Max.
Unit
± 18
V
± 5
Vs
Vs
los
Min.
~
± 18V
~ ±
45
mA
0.15
)J.A
5
mV
0.05
)J.A
17V
10
d
100
mV
=1%
T case " 7ft' C
f ~ 40 to 15 000 Hz
RL~4 n
RL ~ 8 n
10
8
d ~ 10%
T case" 7Cf'C
f
~
f ~ 1 kHz
RL ~ 4 n
RL ~8 n
I nput sensitivity
P~ ~ lOW
P0
~
8W
C4
~
B
Frequency response (-3dB)
RL ~ 4 n
d
Distortion
Po ~ 100mWto lOW
RL ~ 4 n
T case" 7Cf'C
f
f
~
~
W
W
15
12
W
W
1 kHz
RL ~4n
RL ~8 n
Vj
12
9
68 pF
1 kHz
40 to 1 5 000 Hz
220
250
mV
mV
10 to 160000
Hz
0.1
0.3
1
%
%
0.1
0.2
1
%
%
P0 ~ 100 mW to 8 W
RL ~8 n
T case" 7ft'C
f
f
Rj
Input resistance (pin 7)
Gv
Voltage gain (open loop)
~
~
1 kHz
40 to 15 000 Hz
Mn
5
dB
100
RL ~ 4 n
Gv
Voltage gain (closed loop)
eN
Input noise voltage
RL ~4 n
iN
I nput noise current
B (-3 dB)
f
~
1 kHz
29.5
~
22 Hz to 22 KHz
685
30
30.5
dB
4
)J.V
0.1
nA
ELECTRICAL CHARACTERISTICS (continued)
Parameter
SVR
Test conditions
fripple
Drain current
Tsd
Thermal shut-down
Typ.
Max.
Unit
R,_ = 4
Supply voltage rejection
Id
n
= 100
Min.
Po
Pa
50
dB
0.8
0.5
A
A
145
DC
120
DC
Hz
n
n
RL = 4
RL = 8
= 12 W
= 9W
junction temperature
(*l Thermal shut·down case
Tsd
P tat
temperature
= 10.5 W
(*l See fig. 14.
Fig. 1 - Output power vs.
supply voltage
Fig.2 - Output power vs.
supply voltage
(>·16'7/1
(W
I
16
d ,,10".
16
- I--
12
\>oy't.
~~1-
/
/
V
V
~~~
.//
4nV V
/
RL 40
t.oVli
~
~
,/
,/
1/
'II',
/
I '. !
-
/'
d
oa
II
:
~::~l~V
~ Vs
, ,; Fi
['j--cTrrm----,-,-oT'Tin
'11"
I
!
I
i
,,
40H,'
I
lkH~
1
II
~
,
.
10
~~ : ~~4dVB
j!,I]
II
i iI
Ij
,
.
10-1
10
686
I I
'I,
, "
,
I
I,
I
I
I.!' "
I II
. III
"
~Tjl 1-1+ I :,,'.1'·1
I
il
],
=8ft Po - 8W
!
02
!
RL .. 4Cl Po "lOW
-~-RL
II
0.2
I
I
II
II
IIIIII!II
II
I
15KHz
,
, II
0.2
I
I{~
08
,
I
G165312
d
I
I
04
II
,I
Fig. 6 - Distortion vs. frequency
Gv "30dS
0.6
':
(V)
("I.)
I
II!
aD!
+ +':HiIt--+_C' HttIJI+-;-I
i
Fig. 5 - Distortion vs. output
power (R L =8 n)
II
__
,
15
G-1649
+I'.
/
i
Fig.4 - Distortion vs. output
power (R L = 4 n)
I' '+III'H-i-+-Htt.JJI
v, .""
,/
;/ f/
.•~:,.::::.v
1-++
"I ~v ~~~~zB+-,I-tlitt
Ht
Itttt-Il-t-+THtffi
/'
f ,,1kHz
GV"30dB
~
('1.I
('/.) I--h-i-Dillilllllll_+-+1+1I!~+t.lt-HC-t-t-H+I'.JJI
(WI
d ~ ",.
(\,"30dB
Fig. 3 - Distortion vs. output
power
G_I64611
, "'
10"
'V
, "
lO4
""
I (Hz)
Fig. 7 - Output power vs.
frequency
L,+,~
~l'ct
RL~4
II
a,~,
!
I:Vs=!14V
. w'
Gv =30dBIIll-+l+HltiI-++HltiI
d=l"'.
-1v,J;-;h
RL .4[l
f=lkHl'!
I
-± ~rli I~i+~
i- .
240
A'
200
,.,V
"
r;p r--7
v,
(mV)
350
....r
I
RL=sn
G". =JOd
250
200
I
-I
H-+'V,.1,M,,\'-V+ t-+-H--t-+
300
""V' -r",'Od8!
/
[,L-
120
"
Fig. 9 - Sensitivity vs. output
power (R L =8 n)
G_!65
v,
(mV)
"0
it
'ltiI'~+ttt+tll--H111lti1
t
I
Fig.8 - Sensitivity vS.output
power (R L = 4 n)
150
:~~
'lR~~TT
G,,"
I (Hz)
10
Po(W)
>C
Fig. 11 - Value of C4 vs.
voltage gain for different
bandwidths
Po(W)
Fig. 12 - Quiescent current
vs. supply voltage
I,
"
.0
"
lei (OUTPUT TRANSISTORS
20
>C.
>c'
>C'
10~
>C'
~
(H:rl
>C.
>C
"
G,
0-1"58
G_165812
SVR
Ptot
,W)
(dBl
I
VS=!14V
60
I
lTiPPle=l00Hzl-
80
"
I.
.n
~
(0'.)
---8.0.
20
........
eo
30
,W)
"
V
12
I-("
,/
"
-1::: p.,.
...
50
20
Vs=!"14V
f"lkH:i" ,
Gv =30dB
12
G",(dB)
687
-
V
101
I
20
Plot
Plot
.0
........
Vs (V)
Fig. 15 - Maximum power
dissipation vs. supply voltage
(sine wave operation)
Fig. 14 - Power dissipation
and efficiency vs. output
power
Fig. 13 - Supply voltage
rejection vs. voltage gain
17
15
16
Po(Wl
,/
V
..-an
~
13
15
tV. IV)
APPLICATION INFORMATION
Fig. 16 - Application circuit with split power supply
.
01
13
O.l~!
R,
10
~C5
....
IOO~FT'
.
RL
02
C8
OJ~F
J..
"N,OO' OR EQUIVALENT
O-Vo
5-1141/2
Fig. 17 - P.C. board and component layout for the circuit of fig. 16 (1:1 scale)
CS-0074
688
SHORT CIRCUIT PROTECTION
The most important innovation in the TDA 2010 is an original circuit which limits the current of the
output transistors. Fig.18 shows that the maximum output current is a function of the collectoremitter voltage; hence the output transistors work within their safe operating area (fig. 19). This function
can therefore be considered as being peak power limiting rather than simple current limiting. The TDA
2010 is thus protected against temporary overloads or short circuit. Should the short circuit exists for
a longer time, the thermal shut-down comes into action and keeps the junction temperature within
safe limits.
Fig. 18 - Maximum output
Fig. 19 - Safe operating "rea and
current vs. voltave (V CE)
collector characteristics of the proacross each output transistor
tected power transistor.
!
\
I c,I
Ie
max.
\....-P1ot =k
\
\
\
ar.a\
Second breakdowl'\
a2
-,
-+
L -____________________~
30 VCEQ1 (vl
0
20
-20
VCr::
-10
5-076411
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) an overload on the output (even if it is permanent). or an above-limit ambient temperature can be
easily supported since the Tj cannot be higher than 150°C
2) the heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
If, for any reason, the junction temperature increases up to 150°C, the thermal shut-down simply reduces the power dissipation and the current consumption.
Fig. 20 - Output power and
drain current vs. case temperature (R L =8 n)
Fig. 21 - Output power and
drain current vs. case temperature (R L = 4 n)
~l rr-',,-'r-r-',,~-.r=.!.T'''~-'\iV-r'±T"",61 (:~
f-++-t-++-t-++-t-1R l "811.
'0 f-++-t-++-H
10 f-++-H-+-toPot-+-t
H-H-++.::r'd-++'-+H. \
, ,. +
_.fWtU~++-t++\t-I-~
... ri '
50
'00
! . •
50
689
'
• .
100
Tease (·C)
08
06
::
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed
by adding an external heatsink as shown in figs. 22
and 23.
The system for attaching the heatsink is very simple:
it uses a plastic spacer wh ich is suppl ied with the
device.
Thermal contact between the copper slug (of the
package) and the heatsink is guaranteed by the pres·
sure which the screws exert via the spacer and the
printed circuit board; this is due to the particular
shape of the spacer.
Note: The most negative supply voltage is connected to the
copper slug, hence to the heatsink (because it is in
contact with the slug).
Fig. 22 - Mounting system of TDA 2010
HEATSINK
----. R 1h :. 2toS·C/W
~
--
---CONTACT
(SILICONE GREASE)
R1h=q
rfcjw
~.-----s1'AC'"
~.Fig. 23 - Cross-section of mounting system
.
Q
-
--_'_'._0
Q
Fig. 24 - Maximum allowable power dissipation vs.
ambient temperature
The maximum allowable power dissipation depends
upon the size of the external heatsink (i.e. its thermal
resistance); fig. 24 shows this dissipable power as a
function of ambient temperature for different thermal
resistance.
690
LINEAR INTEGRATED CIRCUIT
20W Hi-Fi AUDIO AMPLIFIER
The TDA 2020 is a monolithic integrated operational amplifier in a 14-lead quad in-line plastic package, intended for use as a low frequency class B power amplifier. Typically it provides 20W output
power (d = 1%) at ± 18V/4n; the guaranteed output power at ± 17V/4n. is 15W (DIN norm 45500).
The TDA 2020 provides high output current (up to 3.5 A) and has very low harmonic and cross-over
distortion. Further, the device incorporates an original (and patented) short circuit protection system,
comprising an arrangement for automatically limiting the dissipated power ~o as to keep to working
point of the output transistors within their safe operating area. A conventional thermal shut-down
system is also included.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
Vi
10
Ptot
T stg , T j
Supply voltage
I nput voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at Tease ,,;;; 75°C
Storage and junction temperature
± 22
V
Vs
± 15
3.5
25
-40 to 150
V
A
W
°C
ORDERING NUMBERS: TDA 2020 A82
dual in-line plastic package
TDA 2020 A92 quad in-line plastic package
TDA 2020 AC2 dual in-line plastic package with spacer
TDA 2020 AD2 quad in-line plastic package with spacer
MECHANICAL DATA
Dimensions in mm
691
6/82
CONNECTION AND SCHEMATIC DIAGRAMS
(top view)
-SUPPLY VOLTAGE I
OUTPUT
Nt
"
Nt
-SUPPLY VOLTAGE 3
12
POWER LIMITING
10
COMPE NSATION
Nt
Nt
-SUPPLy' VOLTAGES
o[
Nt
NON INVERTING
• INPUT
COMPENSATION
7 [
8
INVERTING
INPUT
The copper slug is electrically
connected to pin 5 (substrate)
TEST CIRCUIT
~
Dl
IOfJF
Vi
o9Jlr--.---.------4+
Vo
14
4.7fJF
0.1 ~F 100fJF
R3
100
kn
Rl
33
kn
C7
5"/.
C8
*
02
R2
100kn
5'/.
5-1143/3
*IN4001
OR EQUIVALENT
THERMAL DATA
Rthl-case
max
Thermal resistance junction-case
692
3
°C/W
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, V, = ± 17V,
Tamb =
25°C unless otherwise specified)
V,
Supply voltage
Id
Quiescent drain current
Ib
Input bias current
Vos
Typ.
Min.
Test conditions
Parameter
±5
V,
~
Max.
± 22
± 22 V
Unit
V
60
mA
0.15
f.LA
I nput offset voltage
5
mV
10 ,
I nput offset current
0.05
Vas
Output offset voltage
Po
Output power
10
d
~
T case
f
~
Vs
Vs
V
~
,
d
~
~
~
Vi
I nput sensitivity
,
,
d
~
Gv
~
P0
~
Vs
V
~
,
B
~
~
Frequency response (-3 dBI
RL~
Distortion
Pa
G v ~ 30 dB
1%
7DoC
40 to 15000 Hz
± 17V
± 1SV
± 1SV
RL ~ 4 n
RL ~ 4n
RL ~ S n
10%
Gv
f
~
,
V
Gv
f
f
Gv
Voltage gain (open loop)
RL ~ 4n
RL ~ Sn
30dB
15W
f
± 17V
±1SV
RL~ 4n
RL ~ sn
4n
C4
~
~
W
W
W
24
20
W
W
30 dB
1 kHz
± 17V
±1SV
1 kHz
260
3S0
mV
mV
10 to 160000
Hz
.
6S pF
~
~
~
~
~
1 kHz
40 to 15 000 Hz
0.2
0.3
1
%
%
150 mW to 15W
±1SV
RL ~ 8 n
30dB
T case .; 700 C
%
%
0.1
0.25
1 kHz
40 to 15 000 Hz
5
Mn
dB
100
RL ~ 4 n
Gv
~
1S.5
20
16.5
~
~
P0
Input resistance (pin 7)
~
15
150 mW to 15W
G v ~ 30 dB
RL ~ 4n
T case .; 700 C
f
f
Ri
mV
~
T case .; 70' C
V
V
f.LA
100
Voltage gain (e lased loop)
f
~
1 kHz
29.5
693
30
30.5
dB
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test cond itions
Min.
eN
I nput noise voltage
RL~
iN
I nput noise current
B(-3 dB) ~ 10 to 20,000 Hz
SVR
SupplV voltage rejection
Gv
RL~ 4D.
f ripple ~ 100 Hz
Id
Drain current
Tsd
Tsd
4D.
~
~
18.5W
RL ~ 4D.
P0
~
16.5W
8D.
V5
~
Thermal shut-down case
Fig. 1 - Output power vs.
supply voltage
!'101
~
'1
a::.
Unit
4
I'V
0.1
nA
50
dB
1
A
0.7
A
140
°C
,"0;
0('
±18V
Thermal.hut-down
junction temperature
+ .............. "' ........ + .........
Max.
30dB
P0
RL~
TVp.
[:;\1\1
Fig. 2 - Output power vs.
supply voltage
Fig. 3 - Distortion vs. output
power
d
('10)
f
8
-
~
1kHz
G v '" JOd
slf--++++tfflt---Ittttttttl
-- II
,
16
694
18 £'t's (v)
10-'
'0
.,
Po(W}
Fig. 4 - Distortion vs. output
power (R L =4.11)
Fig.5 - Distortion vs. output
power (R L =8.11)
Fig. 6 - Distortion vs. frequency
d
(•., 1--+-1f-t+tt+tto--::c';;;t+
1tt-Htf--+-+--H+I+lI
Vs "118V
Rl"aJl
Gv"30.n.
0.81----- -
0.'
1--+-t+HtlIIf--++1f-1tHtt-----1-+++Ht1I
0.4
f-+++++ttll---++Ht-H#---H-H+Il1I
!
!
0.1,
f- -
0.'
H--ti-H~jf-H++H~+-f-Hj-Hlf--+++I-HlH
./'5 kHz
lkHJ
40Hz
10'
Fig. 7 - Output power vs.
frequency
Fig. 8 - Sensitivity vs. output
power (R L =4n)
10'
104
f (Hz)
Fig. 9 - Sensitivity vs. output
power (R L =8.11)
(W)
RL =81l.
f
20
200
16
I--
Vs=.t18V
RL=8
H-++-¥-f'G.:"'..:.30:,,dc:H
:lkHz
B
JOO
H-+II--+-H-+++-H-+-++-H
120 H++-++-j--l+++-H-+-++-H
BOf-If-+++-H-,j......"F+-H++-H
160
Gy "30d
d
,
10
10'
..
=1°1.
10'
10'
f (Hz)
Fig. 10 - Open loop frequency response with different
values of the rolloff capacitor C4
.,~nT~-rrmm-----.--~
THERMAL DATA
Rth j-case
max
Thermal resistance junction-case
701
3
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs= ±20V, T amb = 25°C unless
otherwise specified)
Test conditions
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Ib
Input bias current
Vos
Min.
Typ.
±5
40
V s = ±25V
Max.
Unit
± 25
V
80
mA
0.15
}.tA
I nput offset vo Itage
5
mV
los
Input offset current
0.05
}.tA
Vos
Output offset voltage
VeE(sat)
Output saturation voltage
I:!
t-requency response (-3 dB)
d
Distortion
I ntermodu lation
Rj
I nput resistance (pin 7)
Gv
Voltage gain (open loop)
10
100
mV
10 = 0.5A
± 1.7
±2
V
10 = 0.5A
10 to 160000
G v= 30 dB
10 = 0.5A
f = 1 kHz
f = 40 to 15000 Hz
._DIN 45500
f
Gv
Voltage gain (closed loop)
eN
Input noise voltage
0.05
0.2
=
Hz
0.3
%
%
0.2
%
5
MD.
100
dB
1 kHz
29.5
30
30.5
dB
4
}.tV
0.1
nA
50
dB
160
100
mA
mA
145
°C
135
°C
B (-3 dB) = 10 to 20 000 Hz
iN
Input noise current
SVR
Supply voltage rejection
f ripple= 100 Hz G v = 30 dB
Id
Drain current
Po = 4.5W
Po = 2W
Tsd
Thermal shut-down junction
temperatu re
Tsd
Thermal shut-down case
temperature
Ptot = 5W
702
R L = 36D.
R L = 36D.
35
!
0.,_
Fig. 1 - Qu iescent current vs.
supply voltage
Fig. 2 - Output current vs.
Fig. 3 - Power dissipation
vs. supply voltage
V CE (sat)
40
G-/B61
f- I+-r- +
Ptol
IWI
HI
R:3
1
"~
10
0.2
23
1.6
!Vs(V)
Fig. 4 - Open loop frequency. response with different values of the rolloff
capacitor
Fig. 6 - Supply voltage
rejection vs. voltage gain
C-l'"
c
j~
19
(pFl
Vs"!20V
'KK
120
I
'i-
10'
~o
17
1.8
Fig. 5 - Value of rolloff
capacitor vs. voltage gain
for different bandwidths
(,-15511
100
EffiWffiiHEiE
I
li',
"
WI
B~40 ~Hz
'0
1--+-+-+----j-+---jtrlpp le =100Hz -
20
1--+--+-+-+--+---+-+----1-"-+:-......-""4
1
('°4),
~~s
'0
100pF
220pF
15pF
II
III
~
6~
~
i'--.ffililli
~l--,
IIIII
IIIII
IIIII
'"
160kHz
I
IIIh
7pF--'
20
I
~~i
60
II
1"i,10
1
106
~T*
I
~
I
1.
•
,
G,
l(Hz)
..
',
[0
.;~;+o·t-h
'AI
20
Vs:22011
- r--
RL =3sn
R L = 36n
Gv" 30dB
II
10
U
0.4
I
0.'
-10
+-
01
rt=- rt=
20
t(ps)
703
1J
~,
0.2
f--'
I
I
0.5
-
H-
0,6
1/
-20
'0
Fig. 8 - Output current vs.
case temperatu re
Fig. 7 - Transient response
,.,"
20
40
1 ,
::t~,-
60
80
H H100
120T case (OC)
40
APPLICATION INFORMATION
Fig.9 - Applic~tion circuit for P0= 30 to 50W
.Y,
Note:
Resistors R9, aJ,P, Rll and R12 are
optional. Their pu~pose is to change the
allowable operating area of the output
transistors (see fig. 23).
The designer can choose different values
according to working conditions (V s,
R L) and to the SOA of the external
transistors. When these resistors are not
used the application circuit is modified
as follows:
.2
lJkO
a) R7, R8 are changed to 25 mn.
b) R 10, R12 are substituted by a short
.,
circuit .
L-_-+____ ~-
Fig. 10 - P.C. board and component layout for the circuit of fig. 9 (1:1 scale)
Po
R L=4.(1
30W
40W
± Vs
18V
20V
R9/Rll
-
2.2 kn
Rl0/R12
4.7n
4.7n
01
BD707
or
BOW21A
BD907
or
BOW21A
02
B0708
or
BOW22A
B0908
or
BOW22A
Note:
If resistors R9, R1D, Rll and R12 are not
used, R7 and R8 must be 25 mil. The following table shows what length of wire
(copper and constantan) is required to obtain
a resistor of 25 mn for different values of -"U-
100
kfl
~~#T
10
kO
n
~
I
,56n!I:;
•
I
.L
=1 kO
BOO24A
l/ZW
!
+
r,-.'2v
For this application the maximum value of Vs in no-load condition is ± 45V.
707
Application suggestions for circuit in fig. 20
Using the two circuits shown in fig. 21 and fig. 22 it is possible
to use a transformer with a large spread of output voltage
between load and no-load condition.
The voltage on pins 1 and 5 follows Vo according to the
equations:
V 1= V 0 + (V s - Vol •
-':::R71-,-,~=;2R:::-;2--
Fig. 21
- 2 V BE
R2
V5= Vo - (Vs + Vol • ---;R""1:;-'-'-+"'R~2;- + 2 VBE
R2
while the voltage between pins 1 and 5 is a constant. In fact:
~--'----+---JVo~
~
-V 1-V 5- V'
V 1-5s
2 R2
R1+R2
- 4 V BE
TO OUTPUT
POWER
TRANSISTORS
V 1-5 must not exceed 50V and then the maximum value of Vs
in no-load condition will be:
Vs max= (50 + 4 VBEI •
R1 + R2
2 R2
R1
:'-255211
The minimum value of Vs depends on the output power
requested and will be:
VS(min)= V L + VCE(sat) with VL=
.J 2 Po
RL
Resistance R2 must be greater than R 1 to guarantee a positive
voltage on pin 1 and a negative voltage on pin 5 for correct
working of TDA 2020D.
Note 1 - Between pins 1 and 5 a ceramic capacitor must be inserted
to guarantee good stability.
Note 2 - It is possible to insert an electrolytic capacitor (10 ).LF)
between pin 1 and GND and between pin 5 and GND, but
in this case the maximum output voltage must be V peak=23V.
With the circuit in fig. 22 the voltage at pins 1 and 5 is kept
constant by two zener diodes. In load conditions a current
equal to 10= 1/{3 flows in R; the value of R is then given by
(VCE-VBEI
R =
I
{3. In no-load condition, if !:N is the in-
Fig. 22
rfY:T'V
I :"F .
VO TO OUTPUT
POWER
TRANSfS TORS
crease in the supply voltage, the zener diodes dissipate a
power depending on !:N and {3 according to the equation:
5-1553
708
SHORT CIRCUIT PROTECTION
The most important innovation in the TOA 20200 is an original circuit which limits the current of the
output transistors. Fig. 23 shows that the maximum output current is a function of the collector-emitter
voltage; hence the output transistors work within their safe operating area (fig. 24). This function can
therefore be considered as being peak power limiting rather than simple current limiting.
By choosing the appropriate values for R9, R 10, R11, R12, (fig. 9) the maximum output current can be
established as a function of the SOA of the output parameters being used.
Fig. 23 - Maximum output
current vs. vo Itage [V C~(sat)]
across one output transistor,
for different values of R 10
(typical application circuit)
Fig. 24 - Safe operating area and collector
characteristics of the protected power
transistor
\
\"'--P tot =k
\
Ie max
\
\
1O:Rlh4.7; = 11" kn
RIO" RIZ"I,,7n; R9"RII,,_
Rl0",R12:0 . R9:RlI:_
6
12
18
24
]0
36
42
48
Vc.E(Vl
os 076411
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent) or an above-limit ambient temperature can be
easily withstood since the T j cannot be higher than 150°C.
2) The heatsink can have a smaller safety factor than a conventional circuit. There is no possibility of
device damage due to high junction temperature.
If, for any reason, the junction temperature increases up to 150°C, the thermal shut-"~~~--ill-----,
,.--'-1
~"1
,n
Rio
I
22KJ1
22KQ
717
'00,",}
0' F
iJ
an
Tweeter (SW)
PRACTICAL CONSIDERATIONS
Printed circuit board
The layout shown in fig. 16 should be adopted by the designers. If different layouts are used, the ground
points of input 1 and input 2 must be well decoupled from the ground return of the output in which a
high current flows.
Assembly suggestion
No electrical isolation is needed between the package and the heatsink with single supply voltage configuration.
Application suggestions
The recommended values of the components are those shown on application circuit of fig. 13. Different
values can be used. The following table can help the designer.
Recomm.
value
Component
Larger than
recommended value
Purpose
Smaller than
recommended value
Rl
22 kn
Closed loop gain
setting
Increase of gain
Decrease of ga in
R2
680 n
Closed loop gain
setting
Decrease of ga in
Increase of ga in
R3
22 kn
Non inverting input
biasing
Increase of input
impedance
Decrease of input
impedance
R4
1n
Frequency stability
Danger of osci Ilat. at
high frequencies
with induct. loads
R5
'= 3 R2
Upper frequency
cutoff
Poor high frequencies attenuation
Cl
1 "F
C2
Danger of
oscillation
Inpu.t DC
decoupling
Increase of low frequencies cutoff
22" F
Inverting DC
decoupling
Increase of low frequencies cutoff
C3,C4
0.1 "F
Supply voltage
bypass
Danger of oscillation
C5,C6
100 "F
Supply voltage
bypass
Danger of oscillation
C7
0.22"F
Frequency stability
Danger of oscillat.
C8
D1,D2
-
1
21T B R1
1 N4001
Upper frequency
cutoff
Smaller bandwidth
Larger bandwidth
To protect the device against output voltage spikes
718
SHORT CIRCUIT PROTECTION
The TDA 2030 has an original circuit which limits the current of the output transistors. Fig. 20 shows
that the maximum output current is a function of the collector emitter voltage; hence the output
transistors work within their safe operating area (fig. 21). This function can therefore be considered
as being peak power limiting rather than simple current limiting. The TDA 2030 is thus protected
against temporary overloads or short circuit. Should the short circuit exist for a longer time, the thermal
shut-down protection keeps the junction temperature within safe limits.
Fig. 21 - Safe operating area and'
collector characteristics of the pro·
tected power transistor
Fig. 20 - Maximum output
current vs. voltage [V CEsat]
across each output transitor
Q,
aroa\
Second
breakdown
0,
-,
10
.... CEQ2 (v) -30
10
-10
S-075t,11
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent), or an above limit ambient temperature can be
easily supported since the T j cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature. If for any reason, the junction
temperature increases up to 150°C, the thermal shut-down simply reduces the power dissipation and
the current consumption.
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance); fig. 24 shows this dissipable power as a function of ambient temperature for different
thermal resistance.
719
Fig. 23 - Output power and
drain current vs. case temperature (R L = 8n)
Fig. 22 - Output power and
drain current vs. case temperature (R L = 4n )
Fig. 24 - Maximum allowable power dissipation vs.
ambient temperature
ld
(A)
16
12
12
10
50
0.6
0.6
0.4
0.4
01
0.2
100
50
100
150
50
Tcase(OC)
Dimension: suggestion.
Fig. 25 - Example of heat-sink
The following table shows the length
that the heatsink in fig. 25 must have for
several values of Ptot and Rth .
Ptot(W)
Length of heatsink
(mm)
Rth of heatsink
(OC/W)
..... _~ _____.~5~O_ _ _ _ _+l
720
12
8
6
60
40
30
4.2
6.2
8.3
~i,
;
:\
LINEAR INTEGRATED CIRCUIT
I-I
I
PRELIMINARY DATA
law Hi-Fi AMPLIFIER AND 30W DRIVER
The TDA 2030A is a monolithic IC in Pentawatt@package intended for use as low frequency class AB
amplifier.
With Vs max= 44V it is particularly suited for more reliable applications without regulated supply and
for 30W driver circuits using low-cost complementary pairs.
The TDA 2030A provides high output current and has very low harmonic and cross-over distortion.
Further the device incorporates a short circuit protection system comprising an arrangement for automatically limiting the dissipated power so as to keep the working point of the output transistors within
their safe operating area. A conventional thermal shut-down system is also included.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
Vi
10
Ptot
Tstg • TJ
Supply voltage
Input voltage
Differential input voltage
Peak output current
Total power dissipation at Tcase= 90°C
Storage and junction temperature
± 22
Vs
±15
3.5
20
-40 to 150
V
V
A
W
°C
ORDERING NUMBER: TDA 2030AV
MECHANICAL DATA
Dimensions in mm
721
6/82
CONNECTION DIAGRAM
(top view)
'~<.D•.
jj
.
_
l,r::!::,,"~
~
NON INVERTING INPUT
$-2128/1
TEST CIRCUIT
THERMAL DATA
Rth j-case
Thermal resistance junction-case
max
722
3
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs= ±16V, Tamb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Ib
Input bias current
Test conditions
Min.
Typ.
Max.
Unit
± 22
V
50
80
mA
0.2
2
/lA
±6
Vs=±22V
Vos
I nput offset voltage
±2
± 20
mV
los
I nput offset current
± 20
± 200
nA
Po
Output power
BW
Power bandwidth
SR
Slew Rate
Gv
Open loop voltage gain
Gv
Closed loop voltage gain
d
Total harmonic distortion
d = 0.5%
G v = 26 dB
f = 40 to 15000 Hz
RL= 4 n
RL= 8 n
15
10
18
12
Vs = ± 19V
R L =8n
13
16
Po= 15W
RL = 4 n
W
100
KHz
8
V//lsec
80
dB
1 = 1 KHz
25.5
26
26.5
dB
Po=0.1t014W
RL=4 n
1 = 40 to 15000 Hz
1 = 1 KHz
0.08
0.03
%
0.05
%
0.03
%
0.08
%
Po =0.1t09W
R L =8 n
1 = 40 to 15000 Hz
d2
Second order CC I F
intermodulation distortion
Po=4W
R L = 4n
Irl1 = 1 KHz
d3·
Third order CCIF
i ntermodu lation distortion
11 = 14 KHz
12 = 15 KHz
21 1 -1 2 = 13KHz
I nput noise voltage
B = curve A
2
B = 22 Hz to 22 KHz
3
eN
/lV
iN
I nput noise current
B = curve A
50
B = 22 Hz to 22 KHz
80
R L = 4n
Rg= 10 Kn
B = curve A
Po = 15W
106
Po = 1W
94
10
pA
SIN
Signal to noise ratio
200
dB
723
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
RI
I nput resistance (pin 1)
(open loop)
f = 1 KHz
SVR
Supply voltage rejection
R L =4n
Rg= 22 Kn
Gv = 26dB
f = 100 Hz
I=in
1 _ -C::innl.a
ell""!..1
";:'"
" ' ; : J ' - --1""1""',
.
..
0.5
5
Mn
54
dB
145
°C
i"'-....
60
GA'N
.0
,/
•0
I
I
Fig. 3 - Output power vs.
supply voltage
G-10601
l"
/ ',J'..
10
..
::-.....
Unit
~rnnli.f:iR"
PHASE
,00
.0
Max.
_ ••• ,... ........ .
Fig. 2 - Open loop-frequency response
G-'""
I
)
-.0
Typ.
Thermal shut-down junction
temperatu re
Tj
,-,
Min.
"'. ~
.- f -
•
'w",
Fig. 4 - Total harmonic
distortion vs. output power(*)
.....-,----,-,--r_---,--,--"':!.!i''''---,
,
~v=~l~·ZS
fa40Hz to 15KHz
2'
./
.0
. /K."
"
" V
./
k;;-
V
......... V
......
115;3811 :,lIs =3211
0.3 1-+_I-+_;:"L=,=6"-~!I=rURL='~='=I-----i
V
I
·.0
·60
'0
"
"
"
*) Test using noise filters.
724
3.
0.1
0.3
10
30
Po(W)
I
Fig. 5 - Two tone CCIF
intermodulation distortion
(;-'607
(.,d
.)
.. I" . II.
I
J1V
Po: 4W
- - R L :4fi
IG v :26dB
I
-r.-~
I
-...+-
i-t-!
I
I
f--f--Il---i-- -
~~
f--
'0 r-r"TTTTmr--"-jTTTTTnr--T~\-m,
2.
"
~"50.n.
r-
=4,n.
20
0.1
J
0.0 3
ri DRciR J, )
(t 2
,
i\
"
ORDER (2f,-f21
i,
./
I
30
100
300
11(
311.
10K
t (Hz)
10
I (KHz)
-50
50
100
Fig. 8 - Split-supply high power amplifier (TOA 2030A + B0907/B0908)
Fig. 9 - Single supply high power amplifier (TOA 2030A + B0907/B0908)
Rl
56K.ll.
!
~1~~H4~~~~~--~+H~
"s:IISV
.
I
0.3
Fig. 7 - Maximum allowable
power dissipation vs. ambient temperature
Fig. 6 - Large signal frequency response
C3
R6
Io.22JJF
1.5ll.
4ll.
725
Fig. 10 - P.C. board and component layout for the circuit of fig. 9 (1:1 scale)
GND IN
RL
GND +Vs
Typical performance of the circuit of fig. 9
Parameter
Test conditions
Min.
Typ.
Max.
Unit
36
44
V
Vs
Supply voltage
Id
Quiescent drain current
Vs = 36V
Po
Output power
d = 0.5%
RL=4n
f = 40Hz to 15KHz
Vs= 39V
35
Vs= 36V
28
d = 10%; f = 1 KHz
Vs= 39V
44
R L =4n
Vs= 36V
35
50
mA
W
W
Gv
Voltage gain
SR
Slew Rate
d
Total harmonic distortion
f = 1 KHz
19.5
20
8
f = 1 KHz
0.02
f=40Hzt015KHz
0.05
20.5
dB
V I!-,sec
%
Po= 20W
Vi
I nput sensitivity
Gv = 20 dB
Po= 20W
f = 1 KHz
RL=4n
890
SIN
Signal to noise ratio
RL= 4.11
Rg= 10 Kn
B = curve A
Po= 25W
108
Po=4W
100
mV
dB
726
35
30
t--
Pp,-------,-,-~~~~
d
('10)
TOA 20JOA
B0907-60908
Po
(w)
Fig. 13 - Output power vs.
input level
Fig. 12 - Total harmonic
distortion vs. output p?~~,:
Fig. 11 - Output power vs.
supply voltage
(WI
18
G v " 20 dB
~ d"
~;:~~<:1015KHzf--+-+-f--7'"-1
0.5 I.
/
/'
15
20
f----
'5
-
//,
,,/
0'
V
I
24
03
/'
26
r---t-+-L---f
I
36
28
30
Fig. 14 - Power dissipation
vs. output power
,
125
Vs=36V
Rl ,,1,11.
I I
10
-
I--
Cm-1~LET~
V
/
I
Y;
/
t ,,1KHz
-
AJPLlFiER
I r
I I
r-
I'
809b7 - sl0908
t
TDj 2030
1 I
I I
"
175
250
350
500
700
Vi (mV)
Fig. 15 - Typical amplifier whit split power supply
G-4701
I
!
)
'0
Po(W)
I
I
Fig. 16 - P.C. board and component layout for the circuit of fig. 15 (1
727
1 scale)
Fig. 17 - Bridge amplifier whit split power supply (Po= 34W, Vs= ±16V)
811
22Kll
R7
C5
~22JJF
R 6.:t680
11
5-5218
Fig. 18 - P.C. board and component layout for the circuit in fig. 17 (1:1 scale)
728
Multiway speaker systems and active boxes
Multiway loudspeaker systems provide the best possible acoustic performance since each loudspeaker is
specially designed and optimized to handle a limited range of frequencies. Commonly, these loudspeaker
systems divide the audio spectrum into two or three bands.
To maintain a flat frequency response over the Hi-Fi audio range the bands covered by each louds·
peaker must overlap slightly. Imbalance between the loudspeakers produces unacceptable results there·
fore it is important to ensure that each unit generates the correct amount of acoustic energy for its seg·
ment of the audio spectrum. In this respect it is also important to know the energy distribution of the
music spectrum to determine the cutoff frequencies of the crossover filters (see fig. 19). As an example,
a lOOW three-way system with crossover frequencies of 400 Hz and 3 KHz would require 50W for the
woofer, 35W for the midrange unit and 15W for the tweeter.
Both active and passive filters can be used for crossovers but today active filters cost significantly less
than a good passive filter using air-cored inductors and non-electrolytic capacitors. In addition, active
filters do not suffer from the typical defects of passive filters:
power loss
increased impedance seen by the loudspeaker (lower damping)
difficulty of precise design due to variable loudspeaker impedance.
Fig. 19 - Power distribution
vs. frequency
Fig. 20 - Active power filter
~ HH++~~~++~4+h+~H+++~
00
,.
o. H+++i-t"rm"l-fII-r7'l++-h-
5.
H+++H+-h-~~~++~++h+++rH
'0
H+t+H+ffl+-f+-t+-h-P-h-f-l+"rH
HH+h,*ffi-t+4-t+++·f7-HHHJ·+-f-h
10
Obviously, active crossovers can only be used if a power amplifier is provided for each drive unit.
This makes it particularly interesting and economically sound to use monolithic power amplifiers.
In some applications, complex filters are not really necessary and simple RC low-pass and high-pass
networks (6 dB/octave) can be recommended.
The results obtained are excellent because this is the best type of audio filter and the only one free from
phase and transient distortion.
The rather poor out of band attenuation of single RC filters means that the loudspeaker must operate
linearly well beyond the crossover freqllency to avoid distortion.
A more effective solution, named "Active Power Filter" by SGS is shown in fig. 20.
The proposed circuit can realize combined power amplifiers and 12 dB/octave or 18 dB/octave high-pass
or low-pass filters.
In practice, at the input pins of the amplifier two equal and in-phase voltages are available, as required
for the active filter operation.
The impedance at the pin (-) is of the order of lOOn, while that of the pin (+) is very high, which is
also what was wanted.
729
The component values calculated for fc = 900 Hz using a Bessel 3rd order Sallen and Key structure are:
Cl
= C2 = C3
22 nF
Rl
R2
R3
8.2 KO
5.6 KO
33 KO
Using this type of crossover filter, a complete 3-way 60W active loudspeaker system is shown in fig. 21.
It employs 2nd order Buttherworth filters with the crossover frequencies equal to 300 Hz and 3 KHz.
The midrange section consists of two filters, a high pass circuit followed by a low pass network.
With Vs = 36V the output power delivered to the woofer is 25W at d = 0.06% (30W at d = 0.5%).
The power delivered to the midrange and the tweeter can be optimized in the design phase taking in
account the louspeaker efficiency and impedance (R L = 40 or 80).
It is quite common that midrange and tweeter speakers have an efficiency 3 dB higher than woofers.
Fig. 21 - 3 way 60W active loudspeaker system (V s = 36V)
~r,,-0-ou-F~~~0.-,,-uF--~O-.5-A---'N-40-0~~~_~1~O+36V
............
LOW-PA~S
WOOFER
+36V
BAND - PA55
300 Hz to
3~Hz
l1i14001
1
'O,..F
'A
8A
}22I'F
MIDRANGE
1N4001
HIGH-PAS!)
3K.Hz
'!L'OO)"'F
+v.
81l.
l,22,..F
22K.1l.
I
TWEETER
22KJl
5 - LeU
730
Musical instruments amplifiers
Another important field of application for active systems is music.
In this area the use of several medium power amplifiers is more convenient than a single high power
amplifier, and it is also more reliable.
A typical example (see fig. 22) consist of four amplifiers each driving a low-cost, 4n, 12 inch loudspeaker. Th is appl ication can supply 80 to 160W rms.
Similar output power can be obtained by a single amplifier using the "superbridge" circuit of fig.24.As
shown in the diagram of fig. 16 this circuit can supply output power of 120W and more.
Fig. 22 - High power active box for musical instrument
Fig. 23 - Output power vs.
supply voltage (application
circuit of fig. 24)
G"
l
P,
(W )
!
0
IN
/'
0
1/,'/
80
50
d_""/
]7V
~
59&
V /
A
~'I.
~-
I
I
I
I
I
V
20
:!:12
Fig. 24 - 120W "superbridge" power ampl ifier
731
!11,
±1S
!18
\Is (V)
Transient intermodulation distortion (TIM)
Transient intermodulation distortion is an unfortunate ph en omen associated with negative-feedback
amplifiers. When a feedback amplifier receives an input signal which rises very steeply, i.e. it contains
high-frequency components, the feedback can arrive too late so that the amplifiers overloads and a burst
of intermodulation distortion will be produced as in fig. 25. Since transients occur frequently in music
this is obviously a problem for the designer of audio amplifiers. Unfortunately, heavy negative feedback
is frequently used to reduce the total harmonic distortion of an amplifier, which tends to aggravate the
transient intermodulation (TIM) situation. The best known method for the measurement of TIM consists
of feeding sine waves superimposed onto square waves, into the amplifier under test. The output spectrum is then examined using a spectrum analyser and compared to the input. This method suffers from
serious disadvantages: the accuracy is limited, the measurement is a rather delicate operation and an
expensive spectrum analyser is essential. A new approach (see Technical Note 143) applied by SGS to
monolithic amplifiers measurement is fast cheap-it requires nothing more sophisticated than an oscilloscope - and sensitive - and it can be used down to the values as low as 0.002% in high power amplifiers.
The "inverting-sawtooth" method of measurement is based on the response of an amplifier to a 20 KHz
sawtooth waveform. The amplifier has no difficulty following the slow ramp but it cannot follow the
fast edge. The output will follow the upper line in fig. 26 cutting of the shaded area and thus increasing
the mean level. If this output signal is filtered to remove the sawtooth, a direct voltage remains which
i"Ji<;dL'" Li,,, dll'VUIIL VI Tiivi Ji,ivriiun, aithuugh it is ciiiiicui1lO measure because i1 is indis1inguisnabie
from the d.c. offset of the amplifier. This problem is neatly avoided in the IS-TIM method by periodically inverting the sawtooth waveform at a low audio frequency as shown in fig. 27. In the case of the
sawtooth in fig. 26 the mean level was increased by the TIM distortion, for a sawtooth in the other
direction the opposite is true.
Fig. 26 - 20 KHz sawtooth waveform
Fig. 25 - Overshoot phenomenon in feedback amplifiers
v,
- --,.....,
I
V3
II
---
I-- ~
Fig. 27 - Inverting sawtooth waveform
f--
r--
mTmD
OUTPUT
SIGNAL_ _ _..J
(I)
The result is an a.c. signal at the output whose peak-to-peak value is the TIM voltage, which can be
measured easily with an oscilloscope.
If the peak-to-peak value of the signal and the peak-to-peak of the inverting sawtooth are measured,
the TIM can be found very simply from:
TI M = ---,-..,.V..=o-,,-u-,-t_ _ • 100
Vsawtooth
732
'I,
,
,.,
j
i/
11
ii
In fig. 28 the experimental results are shown for the 30W amplifier using the TDA2030A as a driver and
a low-cost complementary pair.
The measured performances are perfectly suitable for Hi-Fi systems.
A simple RC filter on the input of the amplifier to limit the maximum signal slope (SS) is an effective
way to reduce TIM.
The diagram of fig. 29 originated by SGS can be used to find the Slew-Rate (SR) required for a given
output power or voltage and a TI M design target.
For example if an anti-TIM filter with a cutoff at 30 KHz is used and the max. peak-to-peak output
voltage is 20V then, referring to the diagram, a Slew-Rate of 6V /J1S is necessary for 0,1% TIM.
As shown Slew-Rates of above 10V/IlS do not contribute to a further reduction in TIM.
Slew-Rates of 100V/IlS are not only useless but also a disadvantage in Hi-Fi audio amplifiers because
they tend to turn the amplifier into a radio receiver.
Fig. 28 - TIM distortion vs.
output power
Fig. 29 - TIM design diagram (fc= 30 KHz)
0"'l1li_
v
om '-.L.l.LLl,.il,1L-...L..L,Ll.J.J,
0,1 LL.L.l.JLWll--.JLl..LllWL...l...Ll-1..W.lJ
L-.L..L.L,.w,.LUJ,
.IJJ,
0.1
1
10
Po(W)
0.1
10
Vo(Vpp)
Power supply
Using monolithic audio amplifier with non-regulated supply voltage it is important to design the power
supply correctly. In any working case it must provide a supply voltage less than the maximum value
fixed by the IC breakdown voltage.
It is essential to take into account all the working conditions, in particular mains fluctuations and supply
voltage variations with and without load.
The TDA 2030A (V. max= 44V) is particularly suitable for substitution of the standard Ie power amplifiers (with V. max= 36V) for more reliable applications.
An example, using a simple full-wave rectifier followed by a capacitor filter, is shown in the table and in
the diagram of fig. 30.
A regulated supply is not usually used for the power output stages because of its dimensioning must be
done taking into account the power to supply in the signal peaks. They are only a small percentage of
the total music signal, with consequently large overdimensioning of the circuit.
Even if with a regulated supply higher output power can be obtained (V. is constant in all working conditions), the additional cost and power dissipation do not usually justify its use. Using non-regulated
supplies, there are fewer design restriction. In fact, when signal peaks are present, the capacitor filter acts
as a flywheel supplying the required energy.
In average conditions, the continuous power supplied is lower. The music power/continuous power ratio
is greater in this case than for the case of regulated supplied, with space saving and cost reduction.
733
.,I:
Mains
(220V)
+20%
+15%
+10%
-10%
-15%
-20%
Secondary
voltage
28.8V
27.6V
26.4V
24V
21.6V
20.4V
19.2V
Fig. 30 - DC characteristics
of 50W non-regulated supply
DC output voltage (V 0)
10= 0
43.2V
41.4V
39.6V
36.2V
32.4V
30.6V
28.8V
10= O.1A
10= 1A
42V
40.3V
38.5V
35V
31.5V
29.8V
28V
37.5V
35.8V
34.2V
31V
27.8V
26V
24.3V
"0
'v
eVppl
G8C-tH-l744-JO
3.
34
R IPPLE
I
)
t)'"
220 V
\
l"-
31
I
""'-
RIPPLE
f-
30
50VA
.......
"''"
L
'0
f-
--......... "OUT(DC)
~
""'j--....,
28
0.8
15
20
Io(A)
SHORT CIRCUIT PROTECTION
The TDA 2030A has an original circuit which limits the current of the output transistors. This function
can be considered as being peak power limiting rather than simple current limiting. The TDA 2030A is
thus protected against temporary overloads or short circuit. Should the short circuit exist for a longer
time, the thermal shut-down protection keeps the junction temperature within safe limits.
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent), or an above limit ambient temperature can be
easily supported since the T j cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature. If for any reason, the junction
temperature increases up to 150°C, the thermal shut-down simply reduces the power dissipation and
the current consumption.
734
LINEAR INTEGRATED CIRCUIT
22W Hi-Fi AUDIO POWER AMPLI FIER
The TDA 2040 is a monolithic integrated circuit in Pentawatt ® package, intended for use as an audio
class AB amplifier. Typically it provides 22W output power (d = 0.5%) at Vs = 32V/4n. The TDA 2040
provides high output current and has very low harmonic and cross-over distortion. Further the device
incorporates a patented short circuit protection system comprising an arrangement for automatically
limiting the dissipated power so as to keep the working point of the output transistors within their safe
operating area. A thermal shut-down system is also included.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
Vi
10 .
Ptot
Tstg , Tj
Supply voltage
I nput voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at Tease = 75° C
Storage and junction temperature
ORDERING NUMBER:
± 20
V
Vs
± 15
V
4
25
-40 to 150
A
W
°C
TDA 2040V
MECHANICAL DATA
Dimensions in mm
l5.8""'~
735
6/82
CONNECTION DIAGRAM
(top view)
~I!
l1ri:,?~::",,~
~
~
""
NON INVERTING INPUT
5-262B/1
TEST CI RCUIT
5 - 5383
THERMAL DATA
Rth j-case
max
Thermal resistance junction-case
736
3
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs
= ±16V,
Tamb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Test conditions
Min.
Typ.
Max.
± 2.5
Unit
V
Vs= ± 4.5V
45
30
mA
100
mA
Ib
Input bias current
0.3
1
p.A
Vos
Input offset voltage
±2
± 20
mV
±200
nA
los
Input offset current
Po
Output power
BW
Power bandwidth
Gv
Open loop voltage gain
Gv
Closed loop voltage gain
d
Total harmonic distortion
eN
iN
I nput noise voltage
20
22
12
W
f = 15 KHz
RL= 4n
15
1S
W
Po= 1W
R L =4n
100
KHz
SO
dB
29.5
Po= 0.1 to 10W
R L =4n
f = 40 to 15000Hz
f = 1 KHz
30
O.OS
0.03
B = curve A
2
B '= 22 Hz to 22 KHz
3
30.5
dB
%
p.V
I nput noise current
B = curve A
50
B = 22 Hz to 22 KHz
SO
pA
I nput resistance (pin 1)
SVR
Supply voltage rejection
Tj
T case= 60°C
R L =4n
RL=Sn
f = 1 KHz
Rj
1"/
d = 0.5%
f = 1 KHz
Efficiency
Gv = 30 dB
R L = 4n
f=100Hz
Rg= 22 Kn
Vrjpple= 0.5 V rms
f = 1 KHz
Po= 12W
Po= 22W
R L = sn
R L =4n
Thermal shut-down junction
temperatu re
737
0.5
5
Mn
40
4S
dB
66
63
%
145
°C
APPLICATION INFORMATION
Fig. 1 - Amplifier with split power
supply (*)
Fig. 2 - P.C. board and components layout of the
circuit of fig. 1.
----~----.n-vs
22 ~ ~ :I:100~~:I:
5-5137
Vs = ± 16V
RL=4D
PO;;;' 15W (d
= 0.5%)
Fig. 3 - Amplifier with single supply (*)
Fig. 4 - P.C. board and components layout of the
circuit of fig. 3.
5-482612
* In the case of highly inductive loads protection
diodes may be necessary.
738
APPLICATION INFORMATION (continued)
Fig. 5 - 30W Bridge amplifier with split power supply
IN
C1
5-j] l-..----f---'-l
2.2 )-IF
22K ..'l
eD
Vs = ± 16V
RL = 8n
Po;;' 30W (d
= 0.5%)
Fig.6 - P.C. board and components layout for the circuit of fig. 5.
739
APPLICATION INFORMATION (continued)
Multiway speaker systems and active boxes
Multiway loudspeaker systems provide the best possible acoustic performance since each lodspeaker is
specially designed and optimized to handle a limited range of frequencies. Commonly, these loudspeaker
systems divide the audio spectrum into two, three or four bands.
To maintain a flat frequency response over the HiFi audio range the bands covered by each loudspeaker
must overlap sl ightly. Imbalance between the loudspeakers produces unacceptable results therefore it is
important to ensure that each unit generates the correct amount of acoustic energy for its segment of
the audio spectrum. In this respect it is also important to know the enenlV distribution of the music
spectrum to determine the cutoff frequencies of the crossover filters (see fig. 7). As an example, a
100 W three-way system with crossover frequencies of 400 Hz and 3KHz would require 50W for the
woofer, 35W for the midrange unit and 15W for the tweeter.
Both active and passive filters can be used for crossovers but today active filters cost significantly less
than a good passive filter using air-cored inductors and non-electrolytic capacitors. In addition, active
filters do not suffer from the typical defects of passive filters:
power loss
increased impedance seen by the loudspeaker (lower damping)
difficulty of precise design due to variable loudspeaker impedance
,.,
Fig. 7 - Power distribution
vs. frequency
G-'66'
.)
-
90
~
~
V
lEe -DIN
FOR
SPEAKER
TESTING
80
I
i
70
60
MODERN
MUSIC
II
'1/
!
40
'/:
30
10
Fig. 8 - Active power filter
I
V
./
,
i
I
0.02 0.04 O,OB 0.16 0.31 0.63 1.25 2.5
5
10
20
f (KHz)
Obviously, active crossovers can only be used if a power amplifier is provided for !lach drive unit.
This makes it particularly interesting and economically sound to use monolithic power amplifiers.
In some applications, complex filters are not really necessary and simple RC low-pass and high-pass
networks (6 dB/octave) can be recommended.
The results obtained are excellent because this is the best type of audio filter and the only one free from
phase and transient distortion.
The rather poor out of band attenuation of single RC filters means that the loudspeaker must operate
linearly well beyond the crossover frequency to avoid distortion.
A more effective solution, named "Active Power Filter" by SGS is shown in fig. 8.
The proposed circuit can realize combined power amplifiers and 12 dB/octave or 18 dB/octave highpass or low-pass filters.
In practice, at the input pins of the amplifier two equal and in-phase voltages are available, as required
for the active filter operation.
The impedance at the pin (-) is of the order of 100.11, while that of the pin (+) is very high, which is
also what was wanted.
740
The component values calculated for fc
= 900 Hz using a Bessel 3rd order Sallen and
C1 = C2= C3
R1
R2
R3
22 nF
8.2 Kn
5.6 Kn
33 Kn
Key structure are:
In the block diagram of fig. 9 is represented an active loudspeaker system completely realized using
power integrated circuits, rather than the traditional discrete transistors or hybrids, very high quality is
obtained by driving the audio spectrum into three bands using active crossovers (TDA 2320A) and a
separate amplifier and loudspeaker for each band.
A modern subwoofer/midrange/tweeter solutionis used.
Fig. 9 - High power active loudspeaker system using TDA 2030A and TDA 2040
r- -I
8il
: TWEETER
I
811.
I SUBWOOFER
8il
: MIDRANGE
5-5139
741
LINEAR INTEGRATED CIRCUIT
PREAMPLIFIER
•
•
•
•
•
•
WITH
ALC
FOR
Cr 0 2
CASSETTE RECORDERS
EXCELLENT VERSATILITY IN USE (V s from 4 to 20V)
HIGH OPEN LOOP GAIN
LOW DISTORTION
LOW NOISE
LARGE AUTOMATIC LEVEL CONTROL RANGE
STEREO MATCHING BETTER THAN 3 dB (matched pair)
The TDA 2054M is a monolithic integrated circuit in a 16-lead dual in-line plastic package.
The functions incorporated are:
-
low noise preamplifier
automatic level control system (ALC)
high gain equalization amplifier
It is intended as preamplifier in tape and cassette recorders and players (C,02), dictaphones, compressor
and expander in telephonic equipments, Hi-Fi preamplifiers and in wire diffusion receivers; for stereo
applications the ALC matching is better than 3 dB.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation at T amb = 50°C
Storage and junction temperature
ORDERING NUMBERS:
20
500
-40 to 150
TDA 2054M mono applications
2 TDA 2054M stereo applications
MECHANICAL DATA
Dimensions in mm
~
~.~~ ~
•••.
.....•
0.4 ....
· 1 8 . . ' .. . \ .
",' ',',
,,',
e
6/82
V
mW
°C
742
'
......
a3BI
, ".. ,,' ',',' *'OC!I-C
CONNECTION DIAGRAM
ALC OUTPUT
16
ALC RECOVERY
TIME
03 BASE
15
ALC INPUT
01 COLLECTOR
Q2 BASE
01
SUPPLY
VOLTAGE
BASE
OUTPUT
01
EMITTER
12
FREOUENCY
COMPENSATION
02
EMITTER
11
NON INVERTING
INPUT
INVERTING
INPUT
02
03
GROUND
5-3341
SCHEMATIC DIAGRAM
4
11
10
08
02
09
01
I~
010
D5
tI
I
I
@
01
Q2
03
i-~
l
OJ'
EQUALIZATION AMPLIFIER
15
A LC
S-Jt.04
743
TEST CIRCUIT
,---..----------------o.v.
2.2Mfi
150pF
4'7~
IVo
5-3405
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
200
°C!W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C)
Parameter
Test conditions
Vs
Supply voltage
Id
Quiescent drain current
Vs=9V
S1 = S2 = S3 = at B
hFE
DC current gain (Q1, Q2, Q3)
Ie = 0.1 mA
V eE = 5V
eN
Input noise voltage (Q1, Q2, Q3)
le=0,1 mA
f = 1 KHz
V eE = 5V
iN
Input noise current (Q1, Q2, Q3)
NF
Noise figure (Q1, Q2, Q3)
Min.
Typ·.
4
Max.
20
10
'300
Unit
V
rnA
500
nV
2
../Hz
pA
0,5
../Hz
V eE = 5V
le=0.1 rnA
Rg = 4,7 K1'2
B (-3 dB)= 20 to 10000 Hz
Gv
Open loop voltage gain(for
equalization amplifier)
V s - 9V
Vo
Output voltage with A.L,C.
Vs = 9V
f = 1 KHz
eN
Equivalent input noise voltage
(for equalization amplifier pin 11)
V s - 9V
G v = 40 dB
S1 at B
B (-3 dB)= 20 to 20000 Hz
Rl
Q3 emitter resistance
0.5
4
dB
f = 1 KHz
60
Vi= 100mV
S1= S2= S3 at A
0,6
V
1.3
}J.V
105
744
150
dB
195
1'2
Fig. 1 - Equivalent input
spot voltage and noise cur·
rent vs. bias current (tran·
sistors 01,02,03)
Fig. 2 - Equivalent input
noise current vs. frequency
(transistors 01, 02, 03)
(~):~~aI~~~~IO~H~~I~~)\
-Kalil
(;,;;.)
(ve)
w':~. ~-t
e-. " ':J.i
,• e"""~-
~p!'
.~;., 10H, ~.~
1,
''"''
11;'OkHZ
10'
10
10-'
10'
I
A
tr+:150 "A:-=
,-
-1-T~! !I'III
10'
10'
I
-1
i~
d±
I
I
50 A
,!II
...
ImA
10'
10'
«Hz)
Fig. 6 - Current gain vs.
collector current (transistors
01,02,03)
NF
(dB)
(kO)
"'.
soo
i'..
"
:,,11
it:
10
f(Hz)
Fig. 5 - Optimum source
resistance and minimum N F
vs. bias current (transistors
01 02 03)
,
R,
.==:.
il'
'I
~
10
Fig. 4 - Noise figure vs.
bias current (transistors 01,
02,03)
,~t
10
rT
-
~.
t
:
,e-H
~TTp-..+-=:::T~100Hl
f
ImA
k
lo'~b;: -li- '"~' ~-y~"j,~~1
,
10'
10
r ",,+",+HlII"0""'''l"'41-ffi4li
I"
J-+
!
i
I
G-I!!084
'N
1--+-l-W-I.lll1--T . .
I
Fig. 3 - Equivalent input
noise voltage vs. frequency
(transistors 01, 02, 03)
I
10
400
1
:~'"
'f--
..,,'
I
10
,,'
...
I
",
Ie
(~A)
10
Fig. 7 - Open loop gain vs.
frequency (equalization amplifier!
, !~~~, "I
"'~~
+1-
*lkH, I R,
'00
"TT
11OOH,
.,.
..
1
I
10"'
200
Ie (,uAl
G,
G-3592
RI- 9
In )
60
10
o~
I
, "":t,+
,
40
COMPENSATION
330~i!
e 12.13 :680pF
30
!'\;
"
"'..r..,
I
~
,
-60
\.
1\
(f: 1kHz)
\.
10
\
-120
,"01-
,
-180
\.
'C~A)
10'
Fig. 9 - Dinamic resistance
R I - 9 vs. ALC voltage V I6
Cd.)
50
",
10
Fig. 8 - Open loop phase
response vs. frequency(equaIization ampl ifier)
(0-158&
I-
,
I
-
I
20
-240
I
"
10
~,
"W
_'00 .
.
.
,
\
\
.
I.
10
10'
'0'
10'
10'
10'
10'
745
22
V16(V)
APPLICATION INFORMATION
Fig. 9 - Application circuit for Cr 0 2 cassette player and recorder
""
330n
~-------~~
C9
I
SO/.lF
--
~
i,,,n33on
U...,F
2.2kfi
:
L-____________~}~ __------~
Fig. 10 - P.C. board and component layout for the circuit of Fig. 9 (1: 1 scale)
746
I
TYPICAL PERFORMANCE OF CIRCUIT IN FIG. 9 (T amb = 25°C, Vs = 9V)
Test conditions
Parameter
Min.
Typ.
Max.
Unit
PLAYBACK
Gv
Voltage gain (open loop)
1 ~ 20 to 20000 Hz
Gv
Voltage gain (closed loop)
1 ~ 1 KHz
60
dB
Zi
I nput impedance
1 ~ 100 Hz
1 ~ 1 KHz
1 ~ 10 KHz
10
41
43
Kn
Kn
Kn
1 ~ 1 KHz
Zo
Output impedance
B
Frequency response
d
Distortion
Vo~1V
Output background noise
Zg
'"
ton
,
12
dB
35
n
see lig. 11
f
~
1 KHz
0.2
%
300n + 120 mH
(DIN 45405)
1.5
mV
1
mV
Signal to noise ratio
Vo ~ 1.5V
Zg ~ 300n + 120 mH
60
dB
Switch-on time
Vo
500
ms
134
dB
72
dB
~
Output weighted background noise
S+N
-N
134
~
1V
RECORDING
Gv
Voltage gain (open loop)
f
~
20 to 20000 Hz
Gv
Voltage gain (closed loop)
I
~
1 KHz
B
Frequency response
see fig. 13
~
I~
10 KHz
0.5
%
f~
10 KHz
54
dB
3
,V
1.1
V
75
ms
d
Distortion with ALe
Vo
ALC
Automatic level control range(for
V i <40mV
Va
Output voltage belore clipping
without ALC
f
Va
Output voltage with ALC
Vi~30mV
I
~
1 KHz
tl'
limiting time (see lig. 17)
"'Vi~+40dB
I
~
1 KHz
1V
3 dB of output voltage variation)
,
,
tree
,
tset
ton
S+N
- -***
N
~
1 KHz
Level setting time (see fig. 17)
Recovery time (see lig. 17)
"'Vi~
Switch-an-time
Va
Signal to noise ratio with ALC
Vo~1V
~
-40 dB
I
~
1 KHz
1V
Rg
~
470n
300
ms
150
sec.
500
ms
64
dB
* This value depends on external network.
When the DIN 45511 norm for Irequency response is not mandatory the equalization peak at 15 KHz can be
avoided - so halving the output noise.
Weighted noise measurement (DIN 45405).
747
Fig. 11 - Frequency response
for the circuit in fig. 9 (playback)
Fig. 12 - Distortion vs. frequency for the circuit in
fig.9 (playback)
G-Mn
G,,,,,nm,,,,nm,,,,nmr-rrrrnm
d
"B'H-+t-Hl!tH-+ttlitiH-+t+t+ttf-f-+tttHII
" f---H-1f+W'
12
II
'"fo)
f\-f-\i':ef::;-:i-:i!::;!~efrlJll
-c--t";~ I
1.
H-H++WH~t+.'~;: 50dBat f ~ lkHz--
I'
,. -U~
OA
.2
10'
10 4
t(Hz)
'0
~j(ffijImI
I
i
I
I
l-
,
I;
!'
II
i
Ii
t
1
Ii
l'i
i'
I
Iii
"
"
Fig. 14 - Output voltage
variation
and
distortion
with ALC vs. input voltage
for the circuit in fig. 9
(record ing)
(dB)~
I I
I
I
I
iH
f-f-!-tttlft-f-H-ftHit-f-H-t+liIt-l--HttHII
I
r
i
'1,
I"
G,'-rn~r-rnTmr-rn~r-rn~
(dB)
"o= 1V i:
I
1
'I
-
10
',Ii : I
!
Fig. 13-Frequency response
for the circuit in fig. 9 (recording)
Fig. 16 - Limiting and level
setting time vs. input signal
variation
Fig. 15 - Distortion vs. frequency with ALC for the
circuit in fig. 9 (recording)
Cd51'S
('J.)
f+-
('/.) H-+titttlHr-tiitttlt-t-H-tttttt--t-H+ttffi
,.
54dB
2.'
..,
-8
f-
lIoatOdB=UV
,6
1,:.10kHz
08
Vo
'* 1V
200
100
0.5
I
I
00
10'
00'
10'
00'
Vi C,..v)
~
W'
00'
I (Hz)
Fig. 17 - Limiting, level setting, recovery time
v,
t\
tset
tn'e=RECOYERY TIME
=LlMITING TIME
=LEVEL
SETTING TIME
5-1112
748
10
-+
+
2.
,
LINEAR INTEGRATED CIRCUIT
TV VERTICAL DEFLECTION OUTPUT CIRCUIT
The TDA 2170 is a monolithic integrated circuit in 11-lead Multiwatt@ package. It is a high efficiency
power booster for direct driving of vertical windings of TV yokes. It is intendl!d fOt LJ~.jn Colour and
B & W television receivers as well as in monitors and displays. The functionsincorpora1;ed ani:
power amplifier
- flyback generator
- reference voltage
- thermal protection
Vs
V 7 , Va
V5
V2 ,V 3
Supply voltage (pin 4)
Flyback peak voltage>}
Voltage at pin 5., .. '."
Ampl ifier.i,fJPut.'l!Rtta~;
10
OutP/4,!1.
10
10
15
15
~~(~ur~t i~on repetitive,_ t = 2 msec)
OutP~ .·I!~I4~nt at f = 50 or 60 Hz, t';;; 10 /J.sec
OutPUt;~ealtcurrent at f = 50 or 60 Hz, t
Pin 5 Decurrent at V 7 < V4
Pin 5 peak to peak flyback current
at f = 50 or 60 Hz, t fly ';;; 1.5 msec
Total power dissipation at Tcase = 60"C
Storage and junction temperature
> 10 /J.sec
V
V
35
60
+ Vs
+ Vs
, -0.5
2.5
3
2
100
t
V
A
A
A
mA
3
30
-40 to 150
A
W
°C
ORDERING NUMBER: TDA 2170
Dimensions in mm
MECHANICAL DATA
749
6/82
CONNECTION DIAGRAM
(top view)
-·-~11
o
o
NC
GND
REFERENCE VOLTAGE
OUTPUT STAGE SUPPLY
OUTPUT
GND
FLYBACK GENERATOR
SUPPLY VOLTAGE
NON INVERTING INPUT
INVERTING INPUT
NC
10
9
6
5
o
~
5_ 5325
BLOCK DIAGRAM
- - - - - - < 0 · v5
5_5324
750
Fig. 1 - DC test circuits
Fig. la - Measurement of 12 ; 13 ; 14; la; V g ;
f-,Vg/I'N s ; R9
Fig. 1 b - Measurement of V7 H
......- - - - - - 0 · V 5
, - - - - - ......- - - -......--O.V5
r~
1,or3v
ao
5,
6-10
53
5-5323
Sl : (a) 12 ; (b)
S2 : (a) 14 and
S3 : (a) 12 , 13 ,
13 , 14 and la.
la; (b) 13 ; (c) 12 ,
14 , la, 19 and V 9 ; (b) R9.
Fig. lc - Measurement of VSL ; V 7L
Fig. 1d - Measurement of V 7
12 K Il
5- 5320
50 - S J 2'
751
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
max
max
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,
Vs
=
3
40
°C/W
°C/W
35V, T amb = 25°C unless
otherwise specified)
!
Test conditions
Parameter
Min.
TVD.
Max.
Unit
Fia.
14
Pin 4 quiescent current
15 = 0;
17 = 0;
V3= 3V
8
mA
1a
Is
Pin 8 quiescent current
15 = 0;
17 = 0;
V3=3V
18
mA
1a
Amplifier input bias
V3= 1V
-0.1
-1
JiA
1a
V 2= 1V
-0.1
-1
JiA
1a
13
current
12
Amplifier input bias
current
Reference voltage
19 = 0
2.2
V
1a
!:1Vs
Reference voltage drift
vs. supply voltage
Vs = 15 to 30V
0.5
mV/V
1a
V5L
Pin 5 saturation voltage
to GND
15 =20mA
0.5
V
1c
V7
Quiescent output voltage
Vs = 35V;
Ra = 39 K.r2
18
V
1d
Vs = 15V;
Ra = 13 K.r2
7.5
V
1d
17=1.2A
1
V
1c
17 = 0.7A
0.6
V
1c
-17 = 1.2A
1.6
V
1b
-17 = 0.7A
1.2
V
1b
V9
tN9
V 7L
V,H
Output saturation
voltage to GND
Output saturation voltage
to supply
R9
Reference voltage output
resistance
2.1
K.r2
Tj
Junction temperature for
thermal shut down
140
°c
752
Fig.2 - AC test circuit
TDA2170
0.22
C4Q~F
R7
1.5.fl!
Ry
611.
5 - 5305
Fig.3 - PC board and component layout (1: 1 scale)
GND
YOKE
YOKE (V o )
IN
NOt\I~:V.IN
REF. VOLTAGE
GND
753
Components list for typical applications
110 TVC
110 TVC
90° TVC
5.9n/10 mH
9.6n/27 mH
15n/30 mH
1.95 App
1.17 App
0.82 App
0
0
Component
Unit
Rl
24
18
12
Kn
R2
10
6.8
5.6
Kn
R3
R4
39
5.6
22
5.6
22
Kn
5.6
Kn
R5
0.82
1.2
2.2
n
R6
270
330
330
n
R7
1.5
1.5
1.5
n
D1
1 N 4001
IN 4001
IN 4001
-
Cl
0.1
IlF
1000/25V
0.1
470/25V
0.1
C2 el.
470/25V
IlF
C3 el.
C4
C5 el.
220/25V
220/25V
220/25V
IlF
0.22
2200/25V
0.22
1500/25V
0.22
1000/16V
IlF
IlF
C6 el.
10/16V
10/16V
10/16V
IlF
Typical performances
Parameter
V5
15 -
-
Supply voltage
Current
tfly - Flyback time
Ptot - Power dissip.
Rth c-a - Heatsink
110° TVC
110° TVC
90° TVC
5.9n/10 mH
9.6n/27 mH
15n/30 mH
24
22.5
25
V
280
175
125
mA
Unit
0.6
1
0.7
ms
4.2
7
2.5
2.05
13
16
60
W
°C/W
°c
60
110
110
60
110
To
20
20
20
Vi
4
4
4
ms
Vpp
v7
50
47
52
Vp
Tamb
Tj
max
754
°c
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the MU LTIWATT® package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon
grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces.
Fig. 4 - Mounting examples
o
,
, -', , "
5-37'12
Fig. 5 - Maximum allowable power dissipation vs. ambient temperature
Plot
IW)
"
"
~~
"
'""
20
-t
"
·so
50
755
-.~
100 Tamb("C)
LINEAR INTEGRATED CIRCUIT
COMPLETE TV SOUND CHANNEL WITH V.C.R. AND C.C.C.
The TDA 2190 is a monolithic integrated circuit in 16-lead dual in-line power dip. It performs the
following functions:
IF limiter-amplifier and low-pass filter.
FM detector.
DC volume control.
AF preamplifier and AF power amplifier with thermal shut-down protection and choice of class B or
C.C.C. operation mode
VCR facility with common pin for input and output (playback and recording).
VCR input and FM Detector DC switching for recording and playback.
The main features of TDA 2190 are:
Suitable for all TV standards with FM modulation.
Class B or constant current consumption (C.C.C.) operation mode.
Video cassette recorder (VCR) facility according to DIN norms.
DC or AC volume control.
Physiological volume and tone controls (AC volume control mode).
LC or ceramic filters can be used for input and detector networks.
High output power (lOW) easily achieved by very simple external stage.
n .... _¥. ______ _
n _ L _-'
~dlt:ay
1II;IIIVI11'QII\.oo'll
Very low spread of DC volume control.
DC volume control thermally compensated.
Very low current ripple in C.C.C. operation mode.
4W output power.
No radiation problem
Thermal protection of AF output stage.
Short-circuit protection of VCR
input-output pin.
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
V3
10
10
Ptot
T stg • T j
Supply voltage (pins 14 and 15)
Input peak voltage (pin 10)
Voltage at pin 3
Output peak current (non repetitive)
Output peak current (repetitive)
Power dissipation at T case= 75°C
Storage and junction temperature
28
1
Vs
2
1.5
15
-40 to 150
V
V
V
A
A
W
°c
ORDERING NUMBERS: TDA 2190
TDA 2190 F2
MECHANICAL DATA
6/82
Dimensions in mm
756
CONNECTION DIAGRAM
AF OUTPUT
GROUND
"
RIPPLE REJECTION
SUPPLY VOLTAGE
VCR SWITCH
. I,
C.c.c. SUPPLY VOLTAGE
"
INPUT
12
DC VOLUME CONTROL
AF AMPLIf INVERTING
VCR INPUT/OUTPUT
DE - EMPHASIS
DC VOLUME CONTROL
DETECTOR
REFERENCE VOLT
DETECTOR
IF INPUT
IF BY- PASS
GROUND
BLOCK DIAGRAM
VCR
VCR
INPUT/OUTPUT
SWITCH
R3
ell
R-C,C.C
R2
C7
I
VOLUME
P1
THERMAL DATA
Rth j-case
max.
Thermal resistance junction-case
757
5
758
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, V 5= 24V. fo= 5.5MHz, f m = 1 KHz,
class B, T amb = 25°C, unless otherwise specified)
Test conditions
Parameter
DC CHARACTERISTICS
Vs
Supply voltage (pi ns 14 and 151
Vo
Quiescent output voltage (pi n 11
28
11
Vs = 24V
PI = 0
Vs~12V
PI
11
12
13
5.1
6
6.9
V
V
~
0
V4
Pin 4 DC voltage
Playback and recording
5
6
7
V
V ll
DC volume control reference
P1 =Ot05Kll
4
4.7
5.5
V
0.9
1.1
1.3
V
voltage
V 14~15
C.C.C. reference voltage (between
pins 14 and 151
Id
Quiescent drain current
Vs = 24V
PI = 0
25
45
65
Vs=12V
PI = 0
20
35
50
PI
=
0
L\f =
40
100
J.lV
Vi
PI
~
1 mV
0
L\f=±25KHz
400
480
mV
=
Vi
m
1 mV
0.3
L\f
=
mA
IF AMPLIFIER AND DETECTOR
Vi (threshold) Input limiting voltage at
25 KHz
t
pin 10
V5
AMR
Recovered audio voltage
Amplitude modulation rejection
= +
240
50 KHz
62
dB
Ri
Input resistance (pin 10)
Vi
=
1 mV
10
Kll
Ci
Input capacitance (pin 101
Vi
=
1 mV
5
pF
Volume attenuation
(resistance control)
PI
PI
PI
=
=
Vc
Control voltage
A ~ 90 dB
A = 30 dB
A= o dB
6A
6T tab
Volume attenuation thermal drift
(resistance control)
T tab 251085°C
PI = 2.3 Kll
DC VOLUME CONTROL
A
--~
on
80
22
2.3 Kll
5 Kll
90
30
0
0
1.5
3
=0.05
38
3
dB
dB
dB
V
V
V
dB
DC
AUDIO FREQUENCY AMPLIFIER
Po
Ou tput power in class B mode
d
10%
Vs 24V
12V
Vs
d = 2%
Vs - 24V
Vs 12V
.~-----
16l!
SSI,
R L.
RL
RL
R,
=
1612
8S1
-- - - - - - - - - - - - - - - - - - -
759
4.1
1.5
I
3
1.2
W
W
-L£J
ELECTRICAL CHARACTERISTICS (coQtinued)
Test conditions
Parameter
AUDIO FREQUENCY AMPLIFIER (continued)
Po
Output power in C.C.C. mode
d : 10%
Vs: 24V
Vs:12V
R L : 16n
R L : 8n
3.5
1.2
W
W
R L : 16n
507
10000
Hz
50
dB
B
Frequency response of audio
amplifier (-3 dB)
Po: 1W
SVR
Supply vortage rejection ratio
PI: 0
R L : 16n
Llf : 0
Vi: 1 mV
friPPle: 100 Hz
V.C.R.
2
V3
Input switching voltage for
recordinq
V3
Input switching voltage for
playback
R3
Input resistance
V3: 1 to lOV
V 4i
Input voltage (playback)
V3 ~ 8.5V
Pout: 1W
PI: 5 Kn
V 40ut
Output voltage (recording)
V3 <;;2V
PI: 0
Vi: 1 mV
Llf: ± 25 KHz
I
V
8.5
R4i
Input resistance (playback)
V 3 ;;' 8.5V
R 4put
Output resistance (recording)
V3 <;;2V
d
Total harmonic distortion of pin 4
output signal
PI: 0
Llf: ± 25 KHz
SVR
Supply voltage rejection at output
pin 4
V i ;;'1 mV
PI: 0
V3 <;;2V
Llf: 0 friPPle: 100 Hz
S+N
-N-
Signal and noise to noise ratio
(pin 4)
V3 <;; 2V
Llf: ± 50 KHz
Vi;;' 1 mV
V
Kn
50
100
45
90
180
mV
240
400
480
mV
13
Kn
140
n
0.5
%
50
dB
50
67
dB
50
67
dB
0.5
0.5
%
%
10
Vi: 1 mV
V3 <;; 2V
OVERALL CIRCUIT
-1\1
S+N
Signal and noise to noise ratio
Vi~ 1 mV
Llf: ± 50 KHz
Vo :4V
d
Distortion
Po: 50 mW
Vs: 24V
Vs: 12V
Llf: ± 25 KHz
R L : 16n
R L : 8n
760
TEST CIRCUIT
4
TDA 2190
IF
INPUT
14
'~f
ll~0 _;rvc
W,'i
t~
Fig. 1 - Relative audio output and signal to noise ratio
vs. input signal
''(
A:ClassB
B: c.c.e.
O. Ys
Ys
12
RL
8
24 'y
R7 180
C8 3.9
16
!l
100
n
1.8 nF
S-3185
Fig, 2 - AM rejection vs,
input signal
Fig. 3 - fl.AM rejection vs.
tun ing frequency change
5·N
I
"\
10'
V,(I-.N)
-30
761
-20
-10
0
Xl
20
JO
If(kHz)
Fig. 5 - Distortion of the
detected signal (pin 5) vs.
unloaded O-factor of the
detector coil
Fig. 4 - Detected audio voltage (pin 5) vs. unloaded 0factor of the detector co iI
Fig. 6 - Output voltage attenuation vs. DC volume
control resistance (P 1) and
vs. DC volume control volt
age (V e )
••
'·~·)E~.
:""4V
~
RL'''''
v, :lOmV
_:'0 =5.SMHz
nfm=lkHl
Vs = 24V
:~ : ;:.1=1=fO=5~MIm =lkHz
AI =!25kHz
'00
f-
nbf = ~50kHz
,.'
300
.Y
lot
r;--
X
o.,~
90
60
1020304050607080
o
8
P1(k.fi)
o
Fig. 8 - Distortion vs. tuning frequency change
Fig. 7 - Distortion vs. frequency deviation
d
(0/.)
i
H~S=24
Rl = 16
ti
II
~r~:
Fig. 9 - Switch-off attenuation of the VCR at pin 4
vs. switch-off voltage at pin3
" ,-,-,-,---r,,-,-,---r,,-,-,--PFl
(dB)H-+++-H-++-+O'--d-'-.-"o'--,-",++-H
-10
00=80
~;~
=S.5MHz
i----':~7: ~k2~:HZ
'Jet¥)
H-'-++-1'ri-'-+-I,oc,"",,,',,,-'--H-t---i
H---t--++-H--i--l-jRl = 00
-20
Vi =lmV
H-+++-H-\+--H'O = 5.5 MHz
H-+---t--t-H-tr--H~~ = ~e~Ztor ~4 =0.4'1
1--
,
-c-
: ~"-I""~
0
Fig. 10 - Overall frequency
response
f+H+'
-"
_" H-+-++-H--+++-rW,'_'hri",--'TO_'H
-50
-20
H-t-++--H-+H-+--H-+-++--H
-70
~LL-L-'---'--'-"--LL-'---'--L.L-L-'---'--'
(; f(kHz)
20
H-+++-H-+H--+-+--+++-H
-60
o
Fig. 11 - Audio amplifier
frequency response
10
Fig. 12 - Distortion vs. output power (Vs= 24V and
RL = 16.11)
d
CO!.lf--
v.'
C.C.,
~ ~iO~=';d
,I" !-----------lm =lktb:
4V
Rl 'l6.n ,
I---- 6f
Vi :lmV
-,
'0 =S.SMHz
/.I.1=!2Sk
QUTPU pin1
VCR OUTPUT
-'0
-.
-10
Tf>lJT( In1)
-11
10
L:~6~t
16
::~
-,Ri
-8
VJ(V)
10'
• l 25kHz
12
10
;::::t::
~
10
10'
10'
762
10'
f(Hz)
%(W)
Fig. 15 - Maximum power
dissipation vs. supply voltage
(sine wave operation; class B
mode)
Fig. 14 - Output power vs.
supply voltage (class B
mode)
Fig. 13 - Distortion vs. output power (V s= 12V and
RL = 8n)
Fb
IW,
IW'
Vi -lmY
j;
d=lO"I.
0.5.5 Hz
'm'_t- lI1Hz
'O:5.SMHz
fn,=lkHz
Af=&25kHz
25kHz
R =1
R ;8n.
I:.c.c..
Ctass
10
to
Fig. 16 - Power dissipation
and efficiency vs. output
power (class B mode)
"
I....
IW'
P,
30
Vsey)
Fig. 18 - Power dissipation
and efficiency vs. output
power (C.C.C. mode)
rj ~l ~f1!;lIl .fl lf'r-~l ·
(~otmmmrm·;J-.,
W)
~l::~
.ton
Vi
j=
.~;;J---l-
ao
'O.S.5MH2:
R =8.0
.
10<
25
20
Fig. 17 - Output power vs.
supply voltage (C.C.C. mode)
R
Iw,
t5
PIG!
~7:~~~z
.
m
fO:~:~tt
'm_
40
lkHz
llf .~25kHz
Rl=16.tl.
Vj ;lmY
to ~ UN
'", .. 1kHz
.
At :t15kHz
f\(W)
Fig. 20 - Current ripple vs.
signal frequency (C.C.C.
mode only)
Fig. 19 - Current ripple vs.
R-CCC value (C.C.C. mode
only)
Irippll'
(mARMS)
1
'h): .
~ __
120
100
I. .
"
10
o
,.
o
FbIWl
I---Wj____
imr;i!~1rTT"n"mr-r~
. ~~,..:.~tO"'+'-HIf-l-l+1.JllII
Fig. 21 - Quiescent drain
current vs. supply voltage
(C.C.C. mode only).
G 3.l1l;I11
,
I,
ImA
'50
: ~~+~_-f~cc~"J.Jn
I,.
Po ,,0
R-CCC=3.Jfi
I
tOO
.,.
60
.•0
"0
60
320
40
300
-
I--
q-=
Rif
!
20
4 R-<:CC(n.)
1)4
to
763
'(Hz)
-~--
,.
I
+,
Fig. 22 - Quiescent output
voltage (pin 1) vs. supply
voltage
Fig. 23 - Supply voltage
ripple rejection vs. volume
control attenuation
Fig. 24 - Supply voltage ripple rejection at the AF and
VCR outputs vs. ripple
frequency
v.
(vl
RL=w
IIi: 0
10
CLA5SB
C.c.C
IIU
10
30
'Is(V)
1020]Q40S060
(dB)
10
APPLICATION INFORMATION (Refer to the block diagram)
I F amplifier and limiter
The IF sound signal is amlJlified and limited by a chain of 6 differential stages. To avoid the possibility
of radiation problems an active low pass filter has been integrated to eliminate the high frequency
harmonics from the signal sent to the detector.
Pin 10 is the non inverting input of the amplifier-limiter and it is used as input of the I F sound signal
coming from the input network which can employ either LC or ceramic filters.
The typical input impedance of pin lOis 10 Kn, 5 pF at f 0 = 5.5 MHz.
Pin 8 is the inverting input, of the amplifier-limiter. The DC negative feedback of the amplifier is applied internally to this pin which must therefore be decoupled by means of a by pass capacitor toward
ground.
FM detector
Signal detection is obtained by means of a peak differential detector which enables radiation problems
to be minimized.
Pin 7 is the first input of the peak differential detector and it is the output of the low pass filter. The
typical output impedanca is 2.7 Kn.
Pin 6 is the second input of the peak differential detector. This pin must be supplied with the same DC
voltage as the other input (pin 7) and this is done by coil L1.
External components L 1 C3 and C5 transform the frequency variations into ampl itude variations useful
to drive the detector. Network L 1 C3 C5 has two resonance frequencies:
f 1 series resonance for
Xu· XC3
XC5 = --==-.,...'="'XC3 + Xu
f2 parallel resonance for Xu = XC3
764
APPLICATION INFORMATION (continued)
Coil L 1 must be tuned at frequency fo = IF sound, equidistant from frequencies fl and f2 to which the
peaks of the "S" response of the detector correspond. The separation between the peaks is defined by
the ratio ff2:
=
1 +
1
~.
C3
Network L 1 C3 C5 can obviously be substituted by a ceramic filter.
Pin 5 is the output of the FM detector. Its output impedance of 20 Kn, in combination with capacitor
C4 connected between pin 5 and ground, defines the time constant of the deemphasis. The detector "S"
curve is visible at pin 5. Improved AM R performance can be obtained by connecting a 10 Kn 10 J.1F RC
series network between pin 5 and ground.
VCR
This function, required by receivers capable of recording complete TV signals, is made in accordance
with D IN Norms. A single pin (pin 4) acts both as output of the signal to be recorded and as input of
the signal to be played back. The function of this pin is changed by means of a control, applied to pin 3,
consisting of two different levels of DC voltage. The operating conditions of pins 3 and 4 are:
Mode
Recording
Playback
VCR Switch
pin 3
Function of
pin 4
V3 <2V
Output
R4
Input
R4
V3
~
8.5V
Signal at
pin 4
Impedance of
pin 4
=
=
140n
V4
=
400 mV
13 Kn
V4
=
90 mV
In the recording state the output signal at pin 4 is independent of the volume control, while during playback the signal applied at pin 4 is regulated by the volume control before being sent to the audio amplifier.
Pin 3, input of the VCR switch, has an impedance greater than 50Kn for any value of input voltage.
Control pulses at pin 3 with very sharp edges cause temporary unbalancing of the circuit and produce
audible signals. This effect is eliminated by means of R3 C8 which slows down the control edges. In the
playback state the I F sound signal coming from the detector is automatically blocked by the VCR
switch.
Pin 4, input-output of the audio signal,has a DC typical voltage of 6V. C6 must therefore be used to
decouple it from the VCR.
The output signal of pin 4 can be used to perform the AC volume control (fig. 31). The potentiometer
must be connected between pin 4 and ground and the slider must be connected to pin 13 after DC
decoupling.
DC volume control
The audio signal coming from the FM detector or from the VCR is adjusted in amplitude by means of a
DC controlled active attenuator. The attenuation can be changed either by means of a potentiometer or
by means of a DC voltage.
Pin 11 supplies the reference voltage for the volume control.
This voltage is between 4V and 5.5V and has a thermal coeff. of +O.25%;oC. The maximum current
which can be suppliedby pin 11 is 10 mAo
765
APPLICATION INFORMATION (continued)
Pin 12 is the input of the DC volume control. To minimize the attenuation spreads, the volume control
network R 1, R2, Pl is supplied by the reference voltage of pin 11. The attenuation of the signal is inversely proportional to the voltage applied at pin 12; therefore maximum attenuation is for V 12 =0 or for
Pl = 0 . Capacitor C7, connected in parallel to the volume potentiometer, eliminates any signals or
spikes picked up by the connection wires of the potentiometer. The volume control characteristic
depends on the configuration and on the values of the components of the network connected to pins 11
and 12. The suggested values are: R 1= 1 Kn R2= 3.9 Kn and Pl = 5 Kn with linear variation; with this
network a linear variation of the output power is obtained. Different slopes of the volume control and
relative networks are shown in figs. 25 and 26.
Fig. 26
Fig.25
12
R1
3.9kfi
20
40
60
80
lCX)
120
R2
Pl(°/o)
The volume can also be controlled by means of a DC voltage applied between resistor R2 and ground
instead of potentiometer Pl. Using this configuration, volume variation can be obtained by means of
remote control as shown in fig. 36.
AF amplifier
The AF amplifier consists of an operational amplifier with thermally protected (thermal shut down)
output stage. By using a simple external variant the power stage can be made to operate in class B or in
costant current consumption.
Pin 1 is the output of the power amplifier. The network which defines the gain and the band of the
audio amplifier is connected between pins 1,2 and 13.
The input voltage of the amplifier is I • R4, where I is the signal output current of the DC volume control block. The closed loop gain of the amplifier is given by G v = R5/R6;
Therefore the output voltage is given by
V o =I·R4-
R5
R6
Changing the values of these resistors, different output voltage (i.e. different closed loop gain) can be
obtained.
When impedances, rather than pure resistors, are used, the closed loop gain is changed with frequency.
In particular at high frequencies the gain is reduced by capacitor Cll and at low frequencies it is reduced
by capacitor C13.
The Boucherot cell R7 C14 guarantees the stability of the circuit in all the operating conditions.
Pin 2, the non inverting input of the audio amplifier, is connected to an integrated voltage divider which
fixes its DC voltage at V 5/2.
766
APPLICATION INFORMATION (continued)
Since the voltage of pin 2 is the reference of the input differential stage of the audio amplifier, both the
voltage of pin 13 and the voltage of pin 1 are equal to Vs/2. Capacitor C12, connected between pin 2
and ground, has the dual function of eliminating the audio signals from pin 2 and providing the s:.Jpply
voltage ripple rejection.
Pin 13 is the inverting input of the audio preamplifier; the outoput of the DC volume control is also
connected to this pin.
Supply
The device can operate either in class B or in C.C.C. mode. In class B the supply current is highly variable
and depends on the power supplied to the load. The supply must therefore be well filtered to prevent
modulation effects on the supply itself which may influence other circuits in the TV. In C.C.C. mode
supply current is constant and the supply system can therefore be simplified; for example the sound
channel can be supplied directly by the line transformer without problems of modulation of the picture
size.
is the ma in supply of the device; when it is connected directly to the power supply and pin 14 is
left open, the circuit operates in class B.
Pi n 15
Pin 14 is the supply point for C.C.C. The reference system, connected between pin 14 and pin 15,
determines a constant voltage of 1.1 V between the two pins. To make the device operate in C.C.C. mode,
pin 14 must be connected to the supply and a resistor R-CCC must be connected between pin 14 and
pin 15; the value of this resistor d8fines the quiescent current Iccc= 1.1 V/R-CCC.
Pin 9
is the main ground of the circuit.
Pin 16 is the ground of the power output stage only.
767
APPLICATION INFORMATION (continued)
Fig. 27 - Typical application circuit (class B mode)
Cl~210~F
TDA 2190
C3
CF1
'F~r:F~:S~~BC2'OnF L-~--!f---4---T---1'-...J
INPUT
R9
560n
I
=
10
Rla
R6
10kll
R7
3.3!l.
C14
1·
22 ,uF
560n
L_~
+ _____
___
5-3187
.V s
24V
Fig. 28- P.C. board and component layout of the circuit shown in fig. 27 (1:1 scale)
768
R
L
lGll
APPLICATION INFORMATION (continued)
Fig. 29 - Application using a ceramic discriminator and an LC network at the IF input (C.C.C. mode)
R5
C3
L2
I(f'
L___
~I IC~-;" ~c
INPUT 33 PF
~
IF
'-:C"l
10
3lt539XX
(Taka)
Fig. 30 - P.C. board and component layout of the circuit shown in fig. 29. (1: 1 scale)
769
APPLICATION INFORMATION (continued)
Fig. 31 - Application circuit with AC volume control
Volume
47kfi
Log.
10
11
12
Fig. 32 - Application circuit with tone controls
+
"
770
100kfi
APPLICATION INFORMATION (continued)
Fig. 33 - Application circuit with physiological volume control
,
P,
(dB)
0
,}:vt .
[-:zf'.
15
Vs'24V
RL =16V
1-~',
-+-:
'
.12V
'
~47d6(o) 10 '"
20
d~10'
"
O_5W
30
'0
-
"
'0
~
-I
~+
10'
f-.-d
10'
10'
lo(Hz)
Fig. 34 - Application circuit with fixed bass and treble boost
VCR
VCR
IN/OUT
SWITCH
..,
(dB)
~~:~:m,
--l --:-,
=12V,
'oblum~
,
+t
Volume
H
TDA 2190
rl~5.';~~B100F
~~T
5600
I
=-
-,
-t~
-4
12
13
560n
, ,
---r-:-
-6
16
10
~+
"
100
."
10
771
10'
10'
50
mW
APPLICATION INFORMATION (continued)
Fig. 35 - Application circuit for lOW of output power when Vs= 22V and RL = 4f!
VCR
SW'TCH
TDA2190
~~F~:S~Bf'onF
r
'F
INPUT
S60n
-==:-
560n
..i..
tO~
5-319»1
+
Vs
Fig. 36 - Remote volume control. The output of the sound channel increases when the duty-cycle at pin
2 of the I.C. M1025 decreases
t8kn
47!1
---D---n~
I
Output from
pin20f the
I.C. M'025
(Outy- cycle
variabl. from
1/31 to 30/31)
I
,I 'f 112".5 (31131)
':J
~I.
27/31
.
.1
>80dB
,
--, r-------, r--I
Max Vo'ume
~.
_I
Min. Volume
5-3194
NOTE:
RTI must be set for the normalization of the output power (P o = 100 mW).
Procedure:
- IF input at pin 10 of the TDA 2190
Vs= 24V; R L = 16f!; V j = 1 mV;f o = 5.5 MHz; !If = ± 25 KHz; fm = 1 KHz.
Whith the normalizated output of the
RL = 16f!.
I.e.
Ml025 (duty cycle of 10/31), set RTI for 1.26 V RMS across the load
772
I!
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink as shown in figs. 37
and 38.
The system for attaching the heatsink is very simple: it uses a plastic spacer which is supplied with the
device on request (TDA 2190 F2).
Thermal contact between the copper slug (of the package) and the heatsink is guaranteed by the pressure
which the screws exert via the spacer and the printed circuit board; this is due to the particular shape of
the spacer.
Note:
The most negative supply voltage is connected to the copper slug,hence to the heatsink(because
it is in contact with the slug).
Fig.37 - Mounting system
.------CONTACT
(SILICONE GREASE)
Rth=O.S'c/w
~; ~+_----SPACER
~__',---P.
773
C. BOARD
MOUNTING INSTRUCTIONS (continued)
Fig. 38 - Cross-section of mounting system
HII!';!I!stnk
PC board
/
Chip
The maximum allowable power dissipation' depends upon the size of the external heatsink (i.e. its
thermal resistance): fig. 39 shows this dissipable power as a function of ambient temperature for an
heatsink having 5°C/W.
Fig. 39 - Maximum allowable
power dissipation vs. am·
bient temperature
.....
"
.
,
..
•
.
100
774
Tamb{"C)
LINEAR INTEGRATED CIRCUIT
Hi-Fi DUAL PREAMPLI FI ER
The TDA2310 is a dual high quality class A preamplifier intended for extremely low distortion application in Hi-Fi systems.
The TDA2310 is a monolithic integrated circuit in a 14-lead dual-in-line plastic package and its main
features are:
Very high dynamic range
Very low distortion
High open loop bandwidth
Very low noise
No pop-noise
High slew-rate: 14V/lls (G v = 30 dB) - 50V/lls (G v = 50 dB)
Large output voltage swing
Single or split supply operation
Output short circuit protection
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vem
Vi
Ptot
T j , T stg
± 22
± 20
± 15
±5
500
-40 to 150
DC supply voltage
Operating supply voltage
Common mode input voltage
Differential input voltage
Total power dissipation at Tamb <"60°C
Junction and storage temperature
ORDERING NUMBER:
V
V
V
V
mW
°C
TDA2310
MECHANICAL DATA
Dimensions in mm
. . . . . . ~.t-~
~
,
U1
_d
o~
I
,
...
15.24
I···
_
Lri
~
·2...54
~
t
~::::::r
775
6/82
CONNECTION DIAGRAM
(top view)
OUTPUT (AI
14
P051TIVE 5UPPLV(.Vs I
DRIVER (AIDUTPUT
13
OUTPUT(BI
COMPEN5ATlON (A
DRIVER(BIOUTPUT
11
"
NON INVERTlN6
INPUT (A I
10
INVERTING INPUHAI
6
NEGATIVE SUPPLY (-Vs>
7
I
COMPENSATION (BI
NON INVERTING
INPUT (BI
8
~
INVERTING INPUT(BI
~
BLOCK DIAGRAM
(one section)
OUTPUT
NON
INVERTING
INPUT
:~~5~TlN G ."..-----1------'
-Vs
*-________~________~~________-"
t7~____
776
THERMAL DATA
Rthj-amb
max.
Thermal resistance junction-ambient
180
°C/W
Fig. 1 - Gain and distortion test
f
',uF
20
KJl.
OUT
RL
30 KJl.
5 - 4 06611
Fig. 2 - Noise test
OUT
ELECTRICAL CHARACTERISTICS (Refer to the Test circuit offig. 1, Tamb = 25°C, Vs = ± 15V,
G v = 30dB, RL = 20K.Q unless otherwise specified)
Parameter
Vs
Supply voltage
Test conditions
Min.
Typ.
± 5
Max.
±
20
Unit
V
Is
Supply current
10
15
mA
Ib
Input bias current
0.2
1
f.lA
los
I nput offset current
50
300
nA
Vos
I nput offset voltage
1
3
mV
777
ELECTRICAL CHARACTERISTICS
(continued)
Gv
Voltage gain
(open loop)
Min.
Test conditions
Parameter
1 - 1 KHz
Typ.
Max.
Unitl
85
dB
No compensation
85
dB
1 ~ 1 KHz
±0.2
dB
1 ~ 100KHz
±0.5
dB
5
M>1
1 ~ 20KHz
l>G v
Voltage gain spread
(closed loop)
Ri
I nput resistance
Ro
Output resistance
Vpp
Output voltage swing
(peak to peak)
d~l%
Va
Output voltage (rms)
Rx~
RIM
Pn'-'l.I~r ~~~tj'..JI.!!d":~
\'u
=
20
Gv
~
30dB
SR
Slew rate
Gv
~
50dB (C 3
Rs
~
3V
1 ~ 1 KHz
0.035
%
1 ~ 20 KHz
0.035
%
1 ~ 1 KHz
1 ~ 1 KHz
1 ~ 100KHz
Total harmonic
distortion
d
d2
Second order CCI F
intermodulation
distortion
d3
Third order CC IF
intermodulation
distortion
8.2K>1
\/~~
,
1 ~ 1 KHz
6
1 ~ 20KHz
6
R
. ·X
=
Q'"
.....
~
vn
10
>1
24
V
22
V
8
V
8
V
1Dn
,....-1 ,_
,~~¥
14
V/jls
~
Va
VOl~lV
V o2
11
12
~
~
Rg
Rg
~
~
330pF
470>1)
12 - 11
~
50
1 KHz
0.01
0.1
%
0.03
0.1
%
0.6
1.0
0.8
1V
14KHz
15KHz
~
~
21rl2 ~ 13 KHz
600>1
3.3K>1 (0)
jlV
* Total input noise
eN
Rg ~ 600>1
Rg ~ 3.3K>1 (0)
* Signal to noise ratio
SIN
Cs
Channel separation
Vo
~
20KHz
~ 600>1
~
~
Rg
Rg
Rg
~
~
~
jlV
3.3K
600
0
(0 )
74
78
80
dB
3.3K
600
0
(00)
72
76
78
dB
100
dB
500mV
Rg
f
Rg
Rg
Rg
0.75
1.2
~
~
CMR
Common mode rejection
Rg
~
600>1
95
dB
SVR
Supply voltage rejection
Rg
~
600>1
85
dB
15
rnA
ISh
Output short
circuit current
(*)
(0)
Test CirCUit 01 I,g. 2 (G v ~ 40 dB)
BW ~ curve A
(00)
BW
~
22Hz to 22KHz
778
Fig. 4 - Harmonic distortion
vs. frequency.
Fig.3 - Harmonic distortion
vs. output leve I.
Fig. 5 - Output voltage
swing vs. frequency.
'or-,-TTTITm--,,-nTnT--~~TIm
(VPP}r--t-Htitttt---t+H-tt-ttt---H-ttttttl
RX_S.2Kll
~
r--t-Htitttt-R'_:OO
t--
t---- -
" I-- - -t-ttttttt---H-Htti1t--t-Httt-fH
r--t-Httt-ItI~~: :~~ ~
f-_-t-Httt-ttr-d~.'i"" -
f (Hz)
lOOK
Fig. 6 - Output voltage
swing vs. load resistance.
I\
\
f (KHz)
'00
Fig. 7 - Total input noise
vs. source resistance.
Fig. 8 - Noise density vs.
frequency.
'or--'--"-'rITTr--'--'~~Tn
(Vpp)
1--,",.c-1,"'''++-t+1-tH----t--H-H+H1
~ ~ i ~,~ z H+H-ttt----t-+:bI+t-H
/
/
v
v
'1 '
v
10K
Fig. 9 - Open loop frequency response.
I
5-.323
1 : 1
NO COMPENSATION
NETWORK I
,,-on
i'.. 330>
1\
"- !,\L
3.36~~
'\
V$-'15V
1
60
I
i
"-1,,\1 \
"-
r-1
I
--p-
,
i
1M
f(Hz}
1
1
I
I
C 3 ,,3JOpF R S ,,470 Jli
I
50
\
1
!
i
},.
r-
1
Vs " ~15 V
I
I
\.
Fig. 11 - Two tone CCI F
intermod. distortion.
Fig. 10 - Closed loop gain
vs. frequency.
G-'32211
B
f (Hzf
I
I
c ,,3.3 nF R .68 It
,
I
I
1
~ -,
I
I
,
!
I
-tti
,
I'
-+
-w F::j:2Il:!:..i'0!:RO,!!E~R..!.(tC!.1:.:-t"'1)'../11-----t
1
I
779
1M
f(Hz)
0.25
0.5
0.3
r-"}
---+moRDe:~(2f1-fZ)
I
,"
I
-.. f--+--+--~+---'--t-+6---+---+..------4-----4---------+..-----I--<)-VS
S-5155
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
max
785
200
ELECTRICAL CHARACTERISTICS (Vs= 5V, Tarnb = 25°C, single amplifier, unless otherwise
specified)
Parameter
Vs
Supply voltage
Is
Total supply current
Ib
I nput bias current
Vos
I nput offset voltage
los
I nput offset cu rrent
Gv
Open loop voltage gain
Test conditions
Min.
Typ.
Max.
Unit
20
V
0.8
2
rnA
100
500
nA
4
Vs = 20V
Rg
< 10 Kn
f = 1 KHz
64
f=100KHz
0.5
mV
15
nA
70
dB
30
dB
3
MHz
B
Gain bandwidth product
f = 40 KHz
SR
Slew rate
R L = 2 Kn
1.5
V/J.LS
eN
Total input noise voltage
f = 40 KHz
Rg= 10Kn
20
nVr/Hz
2.5
Vpp
80
dB
Vo·
DC output voltage swing
SVR
Supply voltage rejection (.)
f = 100 Hz
1.5
(.) Circuit of fig. 1.
APPLICATION INFORMATION
Fig. 1 - Application circuit with carrier
Fig. 2 - Alternative input
stage
5 -5108
786
,I
APPLICATION INFORMATION (continued)
The preamplifier shown in fig. 1 must be used with carrier mode transmission. It is particularly suitable
for use with microprocessor decoding system (for instance with the M206 + M3870 or M3872 TV PLL
frequency synthesizer).
The "with carrier" signal is sent as a burst (fcarr= 38 KHz) to reduce power consumption at the transmitter (duty cycle = 1 %) and to allow the receiver to have some bandwidth limiting in the preamplifier to
improve noise immunity (50/100 Hz pulses from incandescent lighting).
The fig. 2 shows an alternative configuration for the input stage: this new circuit allows the correct
operation of the preamplifier even when an incandescent lamp is very close to the I R diode.
Using this configuration, the circuit has only a slight degradation in the useful range.
Fig. 3 - Tuned amplifier application (with carrier)
1 K 11
Fig. 4 - Application circuit without carrier
787
APPLICATION INFORMATION (continued)
The circuit shown in fig. 4 works in transmission mode without carrier. The transmitted signal is sent as
a series of single pulses (rather than bursts, as with the carrier solution).
The DC bias network formed by the 82/2.2 Ko divider and 1 N4148 diode fixes the DC output voltage
near the supply voltage (just under the saturation level). In this way it is possible to optimize the noise
immunity of the receiver. The 2.2 Ko output resistance avoids turn-off problems in the final stage.
Performance
4.5V min; 5.5V max
6mA
Supply voltage
Quiescent drain current
Supply voltage rejection (f = 100 Hz)
Useful range (using the transmitter of fig. 7)
greater than 50 dB
14 mt
With a incandescent IiQht (75WI as a noise source located at 1 mt from the receiver the useful ranQe
decreases to 10 mt.
Fig. 5 - Optimized preamplifier ("no carrier" mode)
Fig. 6 - P.C. and components layout of the circuit of fig. 5 (1 : 1 scale)
788
APPLICATION INFORMATION (continued)
Fig. 7 - I R transmitter using M709 or M710
Fig. 8 - MMC II - PLL TV Frequency synthesizer
•
ONIOFF
Fig.9 - I R Preamplifier and Remote Control receiver for 32 channels voltage synthesizer (EPM - M293)
., ,
h',,"
l:
d(fjll',l
I
210F
5 ...
t1
S _
4
BC17B
'
'°11 tt
3
:-+
47K D.
82Kfi
Kn
12K.n
3.3K Jl
14
by
05C
'B500
17
5:'OOPF
1,6
1"
2
INFRARED
Stand
RI1lay
l
4. 7
£o"n'
H
,
22Kfl
~_
i
I
~~ZA 2320
J3Kll
I
1[
D 475- 525
--r-l--- 1
47nF
I
I
1(ll)K!l
PREAMPLIFIER
PA 26
PB 25
"1293
Pc 24
5 A
Po 23
P E 22
5 B
7 C
,
0
Ml04
27
Strobe
10
RE's.l
9
Res.2
27Kfl.
16
II II II II
.....
p
fl
rl !I r rl
®
-:¢:~
19
11 ?I II JI
-
()
1
.... 0
27Kn
~'5
21
120
I
~
~
s-
~1
Vol.
I"oonF
~
l1J--_-uOUT
Rg
792
150
= 20 dB
for Rx
= 1350n
THERMAL DATA
Rth
j-amb
max
Thermal resistance junction-ambient
200
°G/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Vs = 15V, T amb = 25°G, unless
otherwise specified)
Parameter
Vs
Supply voltage (*)
Is
Supply current (*)
Ib
Input bias current
Vos
I nput offset voltage
los
Gv
Open loop voltage gain
Test conditions
Rg
< 10 Kn
Input offset current
Output voltage swing (*)
Typ.
Max.
Unit
36
V
0.8
2
mA
150
500
nA
0.5
5
mV
10
50
nA
3
Vs=15V
Vo
Min.
f = 333 Hz
80
f = 1 KHz
70
f = 10 KHz
50
70
Vs = 4.5V
f = 1 KHz
f = 1 KHz
Vs= 15V
13
RL = 600n
Vs= 4.5V
2.5
dB
Vpp
B
Gain-bandwidth product
f = 20 KHz
1.5
2.5
MHz
BW
Power bandwidth (*)
Vo= 5 Vpp
d = 1%
40
70
KHz
1.6
V/,.,S
SR
Slew rate (*)
d
Distortion (*)
Vo= 2V
f = 1 KHz
0.03
G v= 20 dB
f = 10 KHz
0.08
eN
Total input noise
voltage ('0)
Curve A
R9 =
1
B - 22 Hz to
22 KHz
50n
Rg= 600n
1.1
Rg- 5 Kn
1.5
50n
1.3
Rg- 600n
1.5
Rg- 5 Kn
2
Rg=
%
1
1.4
,.,V
,.,V
Rc= 600n
9
nV/,fiiZ'
Cs
Channel separation (**)
f = 1 KHz
100
dB
SVR
Supply voltage (**)
rejection
f=100Hz
80
dB
f - 1 KHz
(*) Test circuit of fig. 1.
(*0) Test circuit of fig. 2.
793
•
••
Fig. 3 - Supply current vs.
supply voltage
'.
Fig. 5 - Output voltage swi ng
vs. load resistance
Fig. 4 - Supply current vs.
ambient temperature
G-~554
'.
'mA )
'mA )
Vs=15V
0.9
f--f--HH--I7f-fttG y "20dS
20 f--f--Hf-hlf+ftt f =1kHz
1.0
-
V
16
V
l-
0.8
0.'
,./1-'"
1/
0.6
0.7
f--+-+-++t++tt -- T
..
u-
Fiy.
-50
14
"
n _" _____
ruvvcl
50
1__ "__ 1••• !_I..o.I_
I
rly.
.
10'
......
UallUVYIULl1
L
4
0.4
I
•
I ULi:l1
•
;:ig.
lIi:11 JlIUIIIl,,;
distortion vs. output voltage
10'
a - IUlili in(Jui nui5tl V5.
sou rce resistance
G-45S1
-"'n-"''''~~
B:22Hzto22K~
,f--
0.3
+
4lli
curveA
~C..;...-+--~
i .. '.
!
. I
i
0.'
0,3
10
0.1
30 f(KHl:)
)
v,,"'5V
.
10'
1
30
,
20
-
318/-15
"20KHz
(500Hz) I
o
I
..
I
1
10'
.,
c----'
Wili
......
r-
20
,
,
10'
11!11l
II'
40
30
I
Ilj
Vs ,,4.5V
60
10
i
Rg (11)
50
-
son
.
--rr
i ill' ,.ill
i(1120
"I H,
SUBSONIC,
FILTER
40
lKn
10 t'--
I:
---
EO.=120....s
f75,IJ5
:
I
-, _.
r
Rg -lOKfi
.----1-
,I;',.
j'I!11
' 10'
70
I
)
,
,
Fig. 11 - Tape preamplifier
frequency response (circuit
of fig. 14)
dB
,.
iii
0.3
Fig. 10- RIAA preamplifier
response (circuit of fig. 12)
Fig. 9 - Noise density vs.
frequency
!
'52 S
f (Hz)
10
~~
63
16 25
10 2
~o
6J
16 25
10 J
794
~o
63
15 2S 40 53
10 4
I (Hz)
10
.0
.0'
'"
10'
"Hz)
APPLICATION INFORMATION
18K
.n
Fig. 12 - Stereo RIAA preamplifier
R6
C>~~11111~~'~5______o_ugR)
5- 467012
Fig. 13 - P.C. board and components layout of the circuit of fig. 12
OUT(R)
OUT(L) + Vs
795
APPLICATION INFORMATION (continued)
Fig. 14 - Stereo preamplifier for Walkman cassette players
18K Jl
+4.5V
82KJl
0'3~V
4.71JF
TAPE
HEAD
'~.
100
KJl
20
K
Fig. 15 - Second order 2 KHz Butterworth crossover
filter for Hi-Fi active boxes
Fig. 16 - Frequency response
(circuit of fig. 15)
+ 15 V
r
o
LOW-PASS
./
HIGH-PA S
0.47 flF
10K1l
7
~
~ 5Kll
fe
\
5.6K Jl
= 2KHz
IN
TO
WOOFER
AMPLIFIER
1
O"}JrF~
5KJl
TO
TWEETER
AMPLIFIER
5.6 KJl
5- 466211
796
"f--I-+I-+++-++I+--+-+-1H-I+I.fj
10-1
fife
APPLICATION INFORMATION (continued)
Fig. 18 - Frequency response
(circuit of fig. 17)
Fig. 17 - Third order 2.8 KHz Bessel crossover filter for Hi-Fi
active boxes
.15V
-rii;2320
7
5.+ 4
t
L
-
AS
O.47,uF .
5K.fl.
pi
5.6K!\
R'
~F
'c
8
-"~
+-f-III+H---'I-+---++++++H
=2,8KHz
TWEETER
:--~>----.--.--IIL
11
I
C8
10
C7.,..
.J..
Cl
IN
o-JJ---<~-o---I
*PIN5 4-5-12-13 ARE
CONNECTED TO GROUND
J-Lth
C4
801
C6...i-
I
~~-------------4
0
z
::§!
::>
«
a:
C!'
«
0
a:
'"~
0
i!!u
'"zz
C
0
u
'"a:..
~
I-
,
~
«
::§!
+
.
w
01)
::I:
z
Ii:
(.J
en
*
802
TEST CIRCUIT
L1
L.l0;JH
0 0 .60
l~~F r----l0-,-0-n""F-----..--C-14-nvS
I--+-_ _---,Cll ."T'
..
to=4.S MHz
14
"T'
...100;JF/35V
470;JF/16V
e12
111--'--*~-1If=-'
TDA 3190
.*
16
O.lume
R2
~
Pl
22kIl
4.7 n
ltn.
(5
75
nF
,
...
*
RC·75)Js
"PINS 4-5 -12-1) ARE
CONNECTED TO GROUND
C9
50;JF/16V
IP (FM DISCRIMINATOR)
THERMAL DATA
Rth j-pins
Rth j-amb
max
max
Thermal resistance junction-pins
Thermal resistance junction-ambient
14
80*
°C/W
°C/W
* Obtained with the GND pins soldered to printed circuit with minimized copper area.
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs= 24V, T amb = 25°C unless
otherwise specified)
Parameter
Test conditions
Min.
Typ.
Unit
28
V
Vs
Supply voltage (pin 14)
Vo
Quiescent output voltage (pin 11)
Vs= 24V
Vs= 12V
11
5.1
12
6
13
6.9
V
V
Id
Quiescent drain current
PI = 22Kn
Vs = 24V
Vs=12V
11
22
19
45
40
mA
mA
Po
Output power
9
Max.
d = 10%
fo= 4.5 MHz
Vs = 24V
Vs= 12V
f m = 400 Hz
f., f = ± 25 KHz
R L = 16.11
R L = 8.11
4.2
1.5
W
W
d = 2%
fo = 4.5 MHz
Vs = 24V
Vs=12V
f m = 400 Hz
M= ± 25 KHz
R L = 16.11
R L = 8.11
3.5
1.4
W
W
803
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
Vi
d
B
Vo
Input limiting voltage (-3 dB)
at pin 1
Distortion
Frequency response of audio
amplifier (-3 dB)
Recovered audio voltage (pin 16)
fo = 4.5 MHz
f m = 400 Hz
P1 = 0
M = ± 7.5 KHz
Po = 50 mW
fo = 4.5 MHz
Vs = 24V
Vs = 12V
f m = 400 Hz
M = ± 7.5 KHz
R L = 16n
R L = 8n
RL = 16n
C 7= 470 pF
Rf = 82n
Rf = 47n
C s = 120 pF
P 1= 22 Kn
Vi> 1 mV
f m = 400 Hz
fo
Fl
AMR
S+N
---r;J
Ampliture modulation rejection
Signal to noise ratio
R3
External feedback resistance
(between pins 9 and 11)
Ri
Input resistance (pin 1)
Ci
Input capacitance (pin 1)
SVR
Supply voltage rejection
Av
DC volume control attenuation
=
Min.
Max.
Unit
40
100
IlV
0.75
1
%
%
70 to 12000
70 to 7000
Hz
Hz
.20
III'V'
55
dB
65
dB
= 4.5 MHz
M = ± 7.5 KHz
0
Vi> 1 mV
f m = 400 Hz
m = 0.3
Typ.
fo = 4.5 MHz
M = ± 25 KHz
Vo =4V
Vi> 1 mV
fo = 4.5 MHz f m = 400 Hz
M = ± 25 KHz
50
25
Kn
30
Kn
5
pF
RL = 16n
f rlpple= 120 Hz
P1 = 22 Kn
46
dB
P 1 =12Kn
90
dB
Vi = 1 mV
fo = 4.5 MHz
804
Fig. 2 - Output voltage attenuation vs. DC volume
control resistance.
Fig. 1 - Relative audio output voltage and output noise
vs. input signal.
Fig. 3 - Amplitude modulation rejection vs. input
signal
'0
'dB)
o.
50
-,
~30
~'O
~.
~"
~'O
~11
-60
-70
10'
"
",
10'
\Ij(,uV)
Fig. 4 - LlAMR vs. tuning
frequency change.
>0'
'0'
",
>0
Fig. 5 - Recovered audio
voltage vs. unloaded Q factor
of the detector coil
Fig. 6
Distortion
output power
,
"/,)
\ I:J
-
I,
-
~
r-
' ,
;-1
f-+i-+~~·t-·-+--H-++-H-+-+-H
f-++
i '
-10
10
20
30 6fo(KHz)
Fig. 7 - Distortion vs. frequency deviation
G,'"
)tt\!.,;~ I
-t
1
102030405060
00
d,,~-r-r'-~,,-'-r-r'-~~
\lj=lm\l
fo=i,.5MHz
,
~~~;~~~:z
I !
!
ii'
00= 60
II
I:
!II
Ii
i
!
1J.;.,.n
I!!
\Is=24VI
Rl'''O ,
t
II,
I'
II
!
I I
,
W'
1-
'~
!
i
"I
10·'
Fig, 9 - Audio amplifier
frequency response
Fig. 8 - Distortion vs. tuni ng frequency change
(OWH-+-++++-H--+-+-+++-H
G"H%
\15 =12'1
T Rl · · "
!
-20
vs.
't
"
-1 'Ij1~":~ l~
,
!
-30
\Ii (~IJ)
10'
~r-r;-~W-"Trrmr-rnT~-'Tn~
,dB)
-+- f -- R =47il.
t ,;
"'MH,
tm=400Hz
I
I -:'
-, f-t-tt-HttIll'-+t-tt+IW;.
Po "Z50mW-
0 0 =60
ilifll
i
i : i:
!
10
j- t
!20
-6
f-t-+HttHt--t
-8
II
A
r'
f
!30
Af(lCHz)
-30
-20
20
-10
805
30 6fo( kHz)
to
to'
to'
f(Hz)
Fig. 10 - Supply voltage
ripple rejection vs. ripple
frequency
SVR
(dB)
so
r-1-rrmll"'IIITTTTTllrrr-rrrmnr-rnmm
H--'+Itttlt-+++tttttt--+t++IHtf--+1-+t+1tII
r-~"
r- r
h8f-+
r IP ,+
50
Fig. 11 - Supply voltage
ripple rejection vs. volume
control attenuation
SVR
r-r--ro-r-T-''-,,--'-.-,,-'T''1
(dB)
H++--H-++--H-+-+-H-+-I
Fig. 12 - Output power vs.
supply voltage
~ rT-''-,,-''-,,-'-''-rT''1
(w)
H-++--H-+-+-+-I-+-+-+--H-I
'fttlIt-1-tHt14f----'-t+t1"'lli
ffit- ~f_tttlffi_+ttt1t1ll
+t'
'ft.
.....
"
RL-I!IA
f+
RL =laA
+
lIV-,
' -+-
y
-Xl
Fig. 13 - Maximum power
dissipation vs. supply voltage (sine wave operation)
Plot
(w)
1-1-T-r+
-I-+-+-+--H++-~-f-+-J
2
:i ::;.;.
fo =4.5MHz
-Ifm =400 Hz
.IAf "'t25kHz
RL = ell
)
-r-r
(5
/
t-i
-60
(dB)
I
/
os
V
2S
30
Vs
'"
----
I
I
(',-1305
)n-
80
r-~'
!
-,
10
I
f-;-
+0/'
/:
~
A
40
~jlIj t+
iV":::'
10
Vs (v)
(v)
Vo
15
,
j--,-+I
i
i
20
m
Fig. 15 - Quiescent output
voltage (pin 11) vs. supply
voltage
(V
J
15
25
20
15
10
,/
A
f-+-t-+-+><+--l-","i-,t+-t-H-l-,H
-so
l-
Qo~60
1.5
-I.(J
('·'470
Ptot
/
RL =16.n.
+--h'-,-!Ft-'--,,+-1
f--,
-30
Fig. 14 - Power dissipation
and efficiency vs. output
power
, -~'H=i±_+I-tt~~+-!--+,-t-H
2.5
-20
::7_
20
25
30
Ys{V)
APPLICATION INFORMATION
The electrical characteristics of the TDA 3190 remain almost constant over the frequency range 4.5 to
6 MHz, therefore it can be used in all television standards (FM mod.). The TDA 3190 has a high input
impedance, so it can function with a ceramic filter or with a tuned circuit that provide the necessary
input selectivity.
The value of the resistors connected to pin 9, determine the AC gain of the audio frequency amplifier.
This enables the desired gain to be selected in relation to the frequency deviation at which the output
stage of the AF amplifier, must enter into clipping.
Capacitor C8, connected between pins 10 and 11, determines the upper cutoff frequency of the audio
bandwidth. To increase the bandwidth the values of C8 and C7 must be reduced, keeping the ratio
C7/C8 as shown in the table of fig. 16.
The capacitor connected between pin 16 and ground, together with the internal resistor of 10 Kn forms
the de-emphasis network. The Boucherot cell eliminates the high frequency oscillations caused by the
inductive load and the wires connecting the loudspeaker.
806
APPLICATION INFORMATION (continued)
Fig. 16 - Typical application circuit
L1
,-----~l00~nF~----~--~OVS
C14
C
L= 10"H
Qo =60
to~4.S MHz
•
"--...---1If-t-------,
10
11
I
I
"'lXl/JF{2sv
250/JF/16V
14
C12
111---"-*_-1IF='
IDA 3190
16
C5
.*
7.5nF
•• PINS 4-5-12-13 ARE
.Cpram1c filter
CONNECTEO TO GROUND
S-3483
Fig. 17 - P.C. board and component layout of the circuit shown in Fig. 16 (1: 1 scale)
73mm
·1
1°
25mm
C5-0097/1
807
MOUNTING INSTRUCTIONS
The Rth j-amb of the TDA 3190 can be reduced by soldering the GND pins to a suitable copper area of
the printed circuit board (Fig. 18) or to an external heatsink (Fig. 19).
The diagram of figure 20 shows the maximum dissipable power Ptot and the Rth j-amb as a function of
the side "JI." of two equal square copper areas having a thickness of 351' (1.4 mils).
During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.
Fig. 18 - Example of P.C.board copper area which is
used as heatsink.
COPPER
AREA 3ot'
Fig. 19 - External heatsink
mounting example
THICKNESS
I
/
S-J181
P. C. BOARD
Fig. 20 - Maximum dissipable power and junction to
ambient thermal resistance
vs. side "JI."
G-nS8
Fig. 21 - Maximum allowable
power dissipation vs. ambient temperature
Ptot
Rth
(W)
( "CIW)
eo
r\
r-
,
~j- ... mb
i'-
--
I'-- r-f-- ,........ ~
Ptot (T amb = ?OOCli
20
T
I
10
20
30
100
-50
I (mm)
808
so
100
T...mb("C)
LINEAR INTEGRATED CIRCUIT
DUAL LOW NOISE TAPE PREAMPLIFIER WITH AUTOREVERSE
The TDA 3410 is a dual preamplifier with tape autoreverse facility for the amplification of low level
si!lnals in applications requirin!l very low noise performance, as stereo cassette players. Each channel
consists of two independent amplifiers. The first has a fixed gain of 30 dB while the second one is an
operational amplifier optimized for high quality audio application.
The TDA 3410 is a monolithic integrated circuit in a 16-lead dual in-line plastic package and its main
features are:
Very low noise
High gain
Low distortion
Sin!lle supply operation
Wide supply range
- SVR = 120dB
- Large output voltage swing
- Tape autoreverse facility
- Short circuit protection
ABSOLUTE MAXIMUM RATINGS
36
600
-40 to 150
Supply voltage
Total power dissipation at T amb = 60°C
Storage and junction temperature
V
mW
°C
ORDERING NUMBER: TDA 3410
Dimensions in mm
MECHANICAL DATA
809
6/82
CONNECTION DIAGRAM (top view)
OUTPUT A
16
NON INVERT.
INPUT A
15
OUTPUT B
14
NON INVERT.
B
INPUT
13
INVERT.
INPUT B
INVERT.
INPUT A
VOLTAGE
REF.
• Vs
THRESHOLO
12
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
ui-tu
~O
;
~
ii,jrv"i
5-32G1
BLOCK DIAGRAM
j
r---
'Vs
~----
___
53
6'
1
I
'--
- 12
"
AUTO REVERSE
'11
~OUTPUT
~Ch.A
s- 4051/·'
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
810
150
°C/W
SCHEMATIC DIAGRAM
DJ·iQQ~
iH
2
-----~
I
~~
~
0,
~32
~
~
~
IQ~
02
~
.,~
03
R2.
...
r
Q36
fQ~
R'7
1
D3't~t ~
Q23C
!:
VOLTAGE
QtQ~
D45~
R33
00
'-------
6
lQgo lag,
+087
R36
I~
I@
Q62
01.
Ql1
l092
Q96J
Q~
t fO~8'
f---------i(Q80
072
~6
013
014
15
R'8
it'
IRSS
017
'-2
•
'0
11
14
R60
R5.
13
rD.'j
TEST CIRCUIT (Flat Gain - Gv= 60 dB)
4
0-------------- v ref
11
L
R 5 "R6"4 7K.!l(Vs " '4.4 V)
R5"R6"'5K!l(V s "30V)
_____ _
I
I
1
Aut.orel/ersE' I
SWitch
:
,
Shielded Test -Box
5-4053fl
* Mylar or polycarbonate capacitors.
ELECTRICAL CHARACTERISTICS (T amb = 25°C, Vs= 14.4V, G v= 60 dB, refer to the test
circuit, unless otherwise specified)
Parameter
Test conditions
Is
Supply current
Vs~
10
Output current (pins 1-15)
Source
Min.
8V to 30V
Vs~
Gv
Closed loop gain
f
~
20 Hz to 20 KHz
Rj
I nput resistance
f
~
1 KHz
Ro
Output resistance (pins 1-15)
f
~
1 KHz
THD
Total harmonic distortion
Vo~300mV
50
~
f~
812
Max.
Unit
10
mA
10
mA
1
mA
60
dB
80
Kn
50
n
8V to 30V
Sink
f
Typ.
1 KHz
10 KHz
0.05
0.05
%
%
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Vo
Output voltage swing (pins 1-15)
Vo
Output voltage (pins 1-15)
Total input noise (0)
en
Signal to noise ratio (0)
SIN
Test conditions
Min.
Typ.
Max.
Unit
Peak to Peak
V 5= 14.4V
Vs= 30V
12
28
.V
V
d = 0.5%
f = 1 KHz
Vs= 14.4V
Vs= 30V
4
8
Vrms
Rg= 50.11
Rg= 600.11
Rg= 5Kn
0.25
0.4
1.3
V rms
0.6
ltV
ltV
ltV
Vin= 0.3 mV
Rg= 600.11
57
dB
Vin= 1 mV
Rg= 0
73
dB
CS
Channel separation
f = 1 KHz
60
dB
CT(OOO )
Cross-talk (differential input)
f = 1 KHz
80
dB
SVR
Supply voltage rejection (00)
f = 1 KHz
120
dB
SVR (00)
Of reference voltage (Pin 4)
100
dB
55
mV
100
.11
Rg= 600.11
f = 1 KHz
Rg= 600.11
V ref
Reference voltage (pin 4)
R ref
Ref. voltage output resistance
(pin 4)
l'N ref
~
(0)
(00)
(000)
Voltage temperature
coefficient
10
The weighting filter used for the noise measurement has a curve A frequency response.
Referred to the input.
Between a disabled input and an input ON.
813
ItV/oC
ELECTRICAL CHARACTERISTICS (Refer test circuit, Vs= 30V!
AMPLIFIER N° 1
Test conditions
Parameter
Gv
Gain (pins 6 to 5)
d
Distortion
Vo= 300mV
en
Total input noise (0)
Zo
Output impedance (pin 5)
10
Output current (pin 5)
Vs
DC output voltage (pin 5)
Min.
Typ.
Max.
Unit
29
30
30.5
dB
f = 1 KHz
f = 10 KHz
0.05
0.05
%
R g=600n
0.4
IN
f = 1 KHz
100
n
1
mA
1.3
Vs=10V
2
2.7
V
AMPLIFIER N° 2
Gv
Open loop voltage gain (pins2tol)
100
dB
Is
I nput bias current
0.2
IJA
Vos
I nput offset voltage
2
mV
los
I nput offset cu rrent
0.05
IJA
BW
Small signal bandwidth
G v= 30 dB
150
KHz
en
Total input noise (0)
Rg= 600n
2
IJV
Rj
I nput impedance
f = 1 KHz (open loop)
500
Kn
150
AUTOREVERSE
Pjn
(0)
V 12
< 2V
V 12
> 4.5V
6 -10
OFF
ON
7- 9
ON
OFF
The weighting filter used for the noise measurement has a curve A frequency response.
Fig. 2 - Total input noise
vs. source resistance (BW=
22 Hz to 22 KHz)
Fig. 1 - Total input noise vs.
source resistance (curve A)
I-t--t+lttltl-t )
.k'
1
0..
1
0.'. _ _
I-t~-++~--~rn '+-0.01
0,01
10
Rg(i'I.l
10'
I Ii
Fig. 3 - Total harmonic
distortion vs. output voltage
I!! I
II'
I'
,
I'
'--~~~:'---:--'-~~---:--:-'c~
10 3
Rg (11.)
10'
'0
I
"
Fig. 6 - Very low noise stereo preamplifier for car cassette players
(with Gap Loss Correction and autoreverse function)
'0
Fig. 5 - Frequency response
G 0961\
(dB I
1111
iTTr
'!
I
,l-
60
I
I
,
c- ,.~
l
,
r-
22nF
30
r-+
tt-
,
"
Rll.
O2°'1,·"'OF
RL,,20KA
t--f~I~~~~2~2~OKJn~
L{==~~~~,~;1~22~n~F
It..4V Rl
lMll
R2
1
C9
50Kn
2AJf
1
Autoreverse
*
Myla.r or
polycarbonat~
5-
~
04 912
815
capacitors
"
,
,
"
,
10
I
rt+~
t (Hz)
Fig. 6 - P.C. board and component lay-out (1:1 scale) for the circuit of fig. 4
OUTPUT
LEFT .Vs
--.-
OUTPUT
RIGHT
'-..-
INPUT
INPUT
(LEFT CHAN.) (RIGHT CHAN.)
AUTOREVERSE
. Fig. 7 - Stereo preamplifier for car cassette players, with low value
capacitors (Autoreverse function)
Fig. 8 - Frequency response
(dB)
lOOn.
IIIIII
---,"--c:"-_:--·-o.llo.4V
I
*'OO,.uF
......
O.3mV
IIIIII
80
70
60
50
lOOKA
S.Stc:A
e13 *
1SnF
40
30
a.3mV
20
0'::~RL'20Kn
15
Rn
I
C14.
15nF
'4.4V Rt
lM ..'l.
lAut.
5-1,050/2
* MylAr
or polycarbonat. capacitors
816
10
10'
t(Hz)
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
DUAL VERY LOW NOISE PREAMPLIFIER
The TDA 3420 is a dual preamplifier for applications requiring very low noise performance, as stereo
cassette players and quality audio systems. Each channel consists of two independent amplifiers.
The first one has a fixed gain while the second one is an operational amplifier for audio application.
The TDA 3420 is available in two packages: 16-lead daul in-line plastic and 16 lead micropackage.
Its main features are:
Very low noise
High gain
Low distortion
- Single supply operation
- Large output voltage swing
- Short circuit protection
ABSOLUTE MAXIMUM RATINGS
Vs
Ptot
Tj , T stg.
Supply voltage
Total power dissipation at T amb = 70°C Dip
50-16
Storage and junction temperature
20
V
530
mW
400
mW
-40 to 150°C
ORDERING NUMBERS: TDA 3420 (DIP)
L 343M (50-16)
Dimensions in mm
MECHANICAL DATA
817
6/82
CONNECTION DIAGRAMS
'-"
OUTPUT A
16
• VS
NON INVERT.
;NPUT A
15
OUTPUT B
GND
14
NON INVERT.
INPUT
B
INVERT.
LNPUT B
INVERT.
INPUT A
13
GND
N.C.
OUTPUT
12
INVERT.
INPUT B
16
• VS
15
OUTPUT B
14
NON INVERT.
INPUT
B
N.C.
13
OUTPUT
12
INPUT
"
OUTPUT A
NON INVERT.
INPUT A
INVERT.
INPUT A
10
INPUT
GND
INPUT
"
OUTPUT
INPUT
INPUT
10
INPUT
INPUT
GND
OUTPUT
INPUT
5-523'
5-5233
50-16
DIP
BLOCK DIAGRAM(Pin numbers refer to the DIP)
r - - - - -
I
':C~)-:()- 5
6
-
-
- -
-.
I
I
OUTPUT(L)
I
I
I
8~ND
I
I
OUTPUT(R)
DIP
THERMAL DATA
Rth j-amb
•
max
Thermal resistance junction-ambient
The thermal resistance is measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mml.
818
80-16
Fig. 1 - Test circuit
INPU~~
(Ll
y
10
INPUrC2 10JoJF
(Rl
Note: Pin numbers refer to DIP.
Fig. 2 - P.C. board and components layout of the circuit of fig. 1 (1: 1 scale)
819
Fig. 3 - Test circuit without input capacitors
INPUT ( Ll
INPUT(R)
C5
10p F
T
R2n R4nR
3Kfil. t2Kfi
--- .. ,vvnu
Note: Pin numbers refer to the DIP.
5- 5 237/1
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, Vs= 14.4V, Gv= 60 dB refer to the test
circuit of fig. 1, unless otherwise specified)
Parameter
Test conditions
Is
Supply current
Vs= 8V to 20V
10
Output current
Source
Min.
Typ.
Max.
Unit
8
mA
10
mA
1
mA
60
dB
100
Kn
50
n
f = 1 KHz
0.05
%
f = 10 KHz
0.05
%
Vs= 8V to 20V
Sink
Gv
Gain
Ri
.Input resistance
Ro
Output resistance
THD
Total harmonic distortion
without noise
f = 1 KHz
Vo= 300mV
50
820
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
Va
Peak to peak output
voltage
I = 40 Hz to 15 KHz
en
Total input noise (0)
Rs= 50 n
Rs= 600 n
Rs= 5 Kn
SiN
(0 )
Signal to noise ratio
(00)
CS
Channel separation
SVR
Supply voltage
rejection
Min.
Typ.
Max.
12
0.25
0.4
1.3
Unit
V
0.7
!LV
!LV
!LV
Vin= 0.3 mV
Vin= 1 mV
Rs= 600 n
Rs= 0
57
73
dB
Vin= 0.3 mV
Vin= 1 mV
Rs= 600 n
Rs= 0
55
71
dB
60
dB
110
dB
1= 1 KHz
1= 1 KHz
Rs= 600 n
(000 )
(0)
Weighting lilter: curve A.
(00) Weighting lilter: Dolby CCIRiARM.
(000) Relerred to the input.
ELECTRICAL CHARACTERISTICS (Refer to the test circuit of fig. 1, Vs= 14.4V)
AMPLIFIER N° 1
Parameter
Test conditions
Gv
Gain (pin 6 to pin 5)
d
Distortion
Va= 300 mV
en
Total input noise (0)
Zo
Output impedance (pin 5)
10
Output current (pin 5)
V5
DC output voltage (pin 5)
Min.
Typ.
Max.
Unit
27.5
28.5
29
dB
1= 1 KHz
f = 10 KHz
0.05
0.05
%
Rs= 600n
0.4
!LV
f = 1 KHz
100
n
1
mA
Test circuit fig. 3
2.8
V
Test circuit fig. 1
(0) Weighting lilter: curve A.
821
1.0
1.5
ELECTRICAL CHARACTERISTICS (continued)
AMPLIFIER N° 2
Test conditions
Parameter
Typ.
Min.
Max.
Unit
Gv
Open loop voltage gain
100
dB
18
I nput bias current
0.2
I'A
Vos
I nput offset voltage
2
mV
los
I nput offset current
50
nA
en
Total input noise (0)
Rs= 600n
2
I'V
Rj
I nput impedance
f = 1 KHz (open loop)
500
Kn
150
(0) Weighting filter: curve A.
Fig.4 - Total input noise vs.
source resistance (curve A)
Fig. 5 - Total input noise vs.
source resistance(BW= 22 Hz
to 22 KHz)
G_3!411
_.
.1
i,1
i !
4 r--=jV s =14.4V I
,
!Ii.em
.- [.Iff-
0.1
0.'
=F=B
:~
'-1- illII' ,
I
,
0.01
Rg (n)
Rg(n)
Fig. 8 - Distortion vs. input
level (test circuit of fig, ,,~)
Fig. 7 - Output voltage vs.
frequency
400
300
11111\11
i
i
'I:
I
!
v":4i4~~~:"j
d"opS%
!,
i'
I'
"
'f--.
,[--
li'!1
I
I
0.'
-
I
I
i
I
I
II
- f
~++tllI ,I
1'1
I
I i iI
Fig. 9 - Frequency response
,
I
0.'
I
II'il!li
G-3620
II
11
,
i
Illdll
I '+EQ.:120,uS
'T-I
'!-,.
so
Ii
822
!
60
'--
I
03
ll
I
'''t-
,
I
0.0 1
-'1·
70
-
!
I IIII! II
I
I III
-
I
1 I
I
circuit of fig. 10
,of the
111,'11
I !II Ii
f ,,300Hz
I'! '
hi
'i _J ;~ it,
r-i ~i~ ~ ~T
-t-~
0.'
eo
,
[--
11 -~ iii
(dB
d
('J.
RL=ZOKl'l
[I' H
I
II
t100
II
it
I
200
IlIlili
G·3610/1
II
:=tl:~:::f+
-..:- ,
I
,[--
I
I:
I
:1
,
I
Tt.
.,
11:1
I
>--- --:-t- .'
1'----'-'
,-1- 7~j
I
,
"
I!V i'-6~EI~~~L ~~~~~OR I,
0.1
,
I
I I
f-+t
-
Vo
,
1:t'C
,--
(mV
G·I,
o~I~~~~~~!J.
I~-----r-r+tt
-~
0.01
.,
d
('/
BW" curve
~
Fig. 6 - Total harmonic distortion vs. output voltage
-t
"
-
"
..-
,
30
-
20
'0
10'
.<>,
'0'
f(Hz)
Fig. 10 - Very low noise stereo preamplifier for cassette players
C5
.r-ll--r"44V
01,uF
1
'6
onf-JF
>,---.--11-
-0
CIO
0.22 .uf
>"--~--IJ------o
Cll
S-SZJe,lf
Fig. 11 - Complete 20 + 20W stereo tape playback system
823
LINEAR INTEGRATED CIRCUIT
PRELIMINARY DATA
5 BIT BINARY TO 7-SEGMENT DECODER DRIVER
•
•
ROM MASK OPTION
STANDARD CONFIGURATION FOR 2 DIGIT 7-SEGMENT LED TO PRESENT THE NUMBERS
1 TO 32
• CONSTANT CURRENT OUTPUT STAGES FOR DIRECT DRIVING OF COMMON ANODE LEDs
• OUTPUT PROVIDED TO DISPLAY THE STAND-BY MODE
• AV OUTPUT ACTIVATED WHENEVER PROGRAM 32 IS SELECTED
• TTL COMPATIBLE INPUTS
• 5V SUPPLY VOLTAGE
The TDA 4092 is a monolithic integrated circuit designed to display the program number (1 to 32) in
TV or Radio sets in conjunction with voltage or frequency synthesizers. The inputs accept a 5 bit binary
code with TTL levels and have internal pull-up.
The outputs can directly drive LED display elements with common anode.
One of these outputs is intended to display the stand-by mode of the set.
No p.xtp.rn::ll
rf~~ic;;tnrc:; ~rp
!"p'=!'_t!r,=,d
jf
the LED5
~~e 5!..!p~Eed ~t
5V.
The LEDs can also be supplied with higher voltage (up to 18V) but in this case a single resistor in series
with the LED elements must be used in order to limit the power dissipation of the IC; moreover, a suitable Rext must be chosen.
The circuit is produced in 12 L technology and is available in a 24 pin dual in-line plastic package.
ABSOLUTE MAXIMUM RATINGS
Vs
VI
Vo (off)
IOL
Ptot
T stg , Tj
Top
10
10
20
22
0.8
-25 to 150
Oto 70
Supply voltage
Input voltage
Off state output voltage
Output current
Total power dissipation at T amb = 55°C
Storage and junction temperature
Operating temperature
V
V
V
mA
W
°C
°C
ORDERING NUMBER: TDA 4092
MECHANICAL DATA
6/82
Dimensions in mm
824
CONNECTION DIAGRAM (top view)
GND
BRIGHTNESS
CONTROL
S TAND- BY INPUT
PA
PB
BINARY
INPUTS
DECIMAL
POINT OUTPUT
A"l OUTPUT
PEN - COLLECTOR)
PC
PD
PE
C
OUTPUTS(TD
THE MOST
6:gl~ljICANT
C
d
OUTPUTS
(TO THE LEAST
SIGNIFICANT
DIGIT)
BLOCK DIAGRAM
PA
I----------->---t ~~I~THRT~tSS
PB
BINARY
INPUTS
,------------t T~~~~- BY
PC
PD
DECIMAL POINT
OUTPUT
PE
AV(OPEN COLLECTOR
>--------i OUTPUT)
ROM
32 x 14
TO DISPLAY
DIGITS
GNO
825
5-
522~
APPLICATION CIRCUIT
BRIGHTNESS
CONTROL
5- 5227
(*) R is necessary only with Vc greater than 5.5V.
THERMAL DATA
Rth j-amb
Thermal resistance junction ambient
max
120
°G/W
ELECTRICAL CHARACTERISTICS (Vs= 5V, Tamb = 25°G unless otherwise specified)
Test conditions
Parameter
Min.
Typ.
4.5
Vs
Supply voltage
Is
Quiescent supply current
Vs= 5.5V
V IH
High level input voltage
T amb =
a to
V IL
Low level input voltage
T amb =
a to 70 e
IIH.
High level input current
T amb = a to 700
Vs = 5.5V
IlL
Low level input current
20
700
e
5.5
V
28
rnA
V
V IH = 2V
V IL=0.8V
826
Unit
2
0
e
Max.
-50
0.8
V
100
nA
-200
/1A
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
V out
Output voltage
10= 15 rnA
V AV '
AV output voltage (pin 20)
(All the binary inputs high)
IAV=1.6mA
Pin 23 input current
(Brightness control)
18
Output current (*)
10
Min.
Typ.
Max.
Unit
V
2
50
Rext= 3.3 Kn
-375
R ext = 5.6 Kn
-225
260
mV
!LA
Rext= 3.3 K
13.5
15
16.5
R ext = 5.6 K
8
9
10
mA
Output cu rrent for
decimal point (pin 21)(**)
lop
Lllo
-I~
o
III V s
Segment cu rrent
stability
10=15mA
V s= 4.5 to 5.5V
(*) 10 = 40· 18
(**) lop is fixed and independent of R ext value.
827
12.5
mA
0.2
%
FUNCTION TABLE
INPUTS
A B C D E
Standby
a
H L
L
L
1
2
3
4
5
6
H H L
L
L
7
H H H L
L
L
L
L
L
H L
L
L
L
L
H L
L
L
L •
H H L
L
L
L
L H L
L
L
L
L
L
H L
L
L
8
9
10
11
12
13
14
15
16
L
L
L
H
L
17
H L
L
L
L
L
H L
L
H L
L
L
H L
L
H L
H L
L
H H L
L
H L
L
L
H H L
L
H L
L
H H L
L
H H H L
L
H H H H L
L
L
H H H
L
H H H H
L
H H H H H
L
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X X X X X
H
none
L
L
H
L
L H L
L
H
L
H H L
L
H
L
H L H
L
L
L
H L
H
L
L H H L H
H L
L
H H H L
H
L
L
L H H
L
H L
L H H
L
H L H H
L
L
L
H H L H H
L
H H H
H L
L
L
H
OUTPUTS
Number
displayed
L
L
= High
L = Low
Av: open collector output.
on
on
on
on
on
on
on
on
on
on
on
on
on
ten's digit (MSD)
b
c
d
e
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
g
b
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
a
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
unit's digit (LSD)
c
d
e
f
g
DP
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
X = Don't care
AV output is "on" whenever the input bits are all high, regardless of the standby input.
828
Av'
..
APPLICATION INFORMATION
Fig. 1 - Remote controlled voltage synthesizer (up to 32 stations) for TV and radio
When operating with a supply voltage higher than 5.5V for LED elements, it is necessary to limit the IC
power dissipation by means of one external resistance connected in series with the common point of the
digits (R in fig. 2).
Unused outputs must be connected to Vs taking into account the additional power dissipation.
The ~alue of. ~ must be chosen taking into account the worst
Fig. 2 _ Schematic diagram
working conditions.
for LED driving.
The maximum number of ON segments is 12 (number 28 dis·
played), so,
Vc - Vo - Vout min
R=
12· 10
10 , depending on Rext (see Table of Electrical characteristics), can
be fixed to the most suitable value to minimize the power dissipation in the IC. Since the worst condition for the device is with
seven outputs active, it follows that:
Pd out = 7· 10 (V c - Vo -7R • 10 )
Pd = Vs· Is max
Power dissipation in the output
stage
Power drained from the supply
I-TD_A_4_09_2--1f---1f-...J } . ' "
Total power dissipation
Ptot must not exceed the Absolute Maximum Ratings of 800 mW, at Tamb = 55°C.
Otherwise the maximum operating ambient temperature can be fixed by:
Tamb max= Tj max - Rth j-amb Ptot
Example:
Vc = 18V;
10 = 10 mA (fixed by means of Rext= 5.6 Kn);
Tj max= 150°C; Vo = 2V; Vs = 5.5V.
Applying the previous formulae, it follows that: R ~ 120n;
Ptot = 0.686W; Tamb max~ 68°C.
829
Vout min= 2V;
Is max= 28 mA;
Pd out= 0.532W;
Pd = 0.154W;
LINEAR INTEGRATED CIRCUIT
VISlor\l I F SYSTEM WITH AFC
•
•
•
•
•
•
•
•
HIGH GAIN-HIGH STABILITY
VERY LOW INTERMODULATION PRODUCTS
MINIMUM DIFFERENTIAL ERROR
CONSTANT INPUT IMPEDANCE INDEPENDENT OF AGC
FAST AGC GATING-ACTION, LARGELY INDEPENDENT OF PULSE SHAPE AND AMPLITUDE
ADJUSTABLE WHITE LEVEL
LARGE AFC OUTPUT CURRENT SWING (PUSH-PULL OUTPUT)
SWITCHABLE AFC
The TDA4420 is a monolithic integrated circuit in 18 lead dual in-line plastic package. The functions in·
corporated are:
gain controlled vision I F amplifier
video demodulator controlled by picture carrier
AGC detector with gating facility
AGC amplifier for tuner drive with variable delay
phase comparator for AFC current generation
electronic AFC switch, controlled by a DC threshold detector
thermally compensated push-pull AFC output stage.
ABSOLUTE MAXIMUM RATINGS
Vs
V5
113 , 114
Ptot
T stg , T j
Supply voltage (pin 15)
Voltage at pin 5
Video DC output current
Total power dissipation at Tamb ,;;; 70°C
Storage and junction temperature
15
15
V
V
5
mA
1
W
-40 to 150°C
ORDERING NUMBER: TDA 4420
MECHANICAL DATA
Dimensions in mm
6/82
830
CONNECTION DIAGRAM
(top view)
,.
INPUT
DECOUPLING
17
BIAS
DECOUPLING
GROUND
16
A Fe OUT
INPUT
BIAS
AGe TIME
15
,.
CONSTANT
TUNER AGe
OUTPUT
SUPPLY
VOLTAGE
POSITIVE
VIDEO
OUTPUT
NEGATIVE
TUNER AGe
13
DELAY
VIDEO
OUTPUT
FlVBACK
12 WHITE LEVEL
PULSE INPUT
CARRIER
TUNING
"
AFC
TUNING
lOP
CARRIER
TUNING
AFC
TUNING
$-1,026
BLOCK DIAGRAM
_J'
ci
>...,
M
>
5-4033
836
LINEAR INTEGRATED CIRCUITS
TV SIGNAL IDENTIFICATION CIRCUIT AND AFC INTERFACE
The TDA4431 and the TDA4433 are monolithic integrated circuits in a 14 lead dual-in-line plastic
package. They integrate the following functions:
-
TV signal identificator-Sync.separator - Threshold detector - Digital Interface - Voltage regulator
They are intended for use in Electronic Program Memory tuning systems. the TDA4431 in conjunction
with M193B1, while the TDA4433 with M293B1. The circuits features are:
Identification of true TV stations only.
Low impedance output of the identification signal.
Digital control signal for automatic search and AFC operation.
Thermal compensation of the voltage regulator.
ABSOLUTE MAXIMUM RATINGS
Vs
V3
V13
12
16 ; 12
110
III
112
Ptot
Tstg' Tj
16
16
-5 to +6
±1
1
2
2
±2
800
-40 to 150
Supply voltage (pin 1)
Voltage at pin 3
Voltage at pin 13
Pin 2 current (TDA4431 )
Pin 6 and pin 2 current (TDA4433)
Pin 10 current
Pin 11 current
Pin 12 current
Total power dissipation at Tamb ,,;; 70°C
Storage and junction temperature
V
V
V
mA
mA
mA
mA
mA
mW
°C
ORDERING NUMBERS: TDA 4431
TDA 4433
MECHANICAL DATA
Dimensions in mm
I
~
~::::::l
837
6/82
CONNECTION AND BLOCK DIAGRAM (TDA4431)
(Top view)
REGULATED VOLTAGE
OUTPUT
r------------------------------{4,)-----------~
OND
V,
'13
OUTPUT
Afe "5"
CURVE INPUT
3
"
STABILIZED
IDENTIFICATION
H
~~~\~~~TAfl
FLYBACK
INPUT
VIDEO
SENS!TIVITY
VOLTAGE OUT
TIME CONSTANT
VIDEO SIGNAL
INPUT
SIGNAL
CONTROL
W
IDENTIFICATION
SIGNAL OUTPUT
N,C
N.C.
N,C
N.C
SENSITIVITY
CONTROL
14
IDENTIFICATION
SIGNAL OUTPUT
CONNECTION AND BLOCK DIAGRAM (TDA4433)
(Top view)
REGULATED VOLTAGE
OUTPUT
V,
14
OND
OUTPUT A
13
VIDEO SIGN"AL
AFe "S"
CURVE INPUT
"
STABILIZED
~~~I~~:TA:fl
SENSITIVITY
CONTROL
VOLTAGE OUT
IDENTifiCATION
TIME CONSTANT
INPUT
H FLVBACK
INPUT
10
IDENTIFICATION
SIGNAL OUTPUT
OUTPUT B
N.C.
N C,
N.C
SENSITIVITY
CONTROL
I
~
BUFFER
STAGE
L-________________________
-----l-
~1D)}---------------------~
LOENT1FICATION
SIGNAL OUTPUT
*
Open collector outputs
838
.....
5-4046/1
TEST CIRCUIT
dl-
)
O----A~b
.------'-----',,---'--.;;,
Hor'8_,b_a_'k_'"_ _6,,-,9
r
~L-.4--o
D,gltal AFC
lout A
:
L
r"
'o,,3B.9MHz
out TDA 44311:
(no ident.) :
O~---,
i--o-----oldentlf. out
t:::..;~---T---':';'----T-...J
HL
I
(ld;nU
PI Digital AFC perfect tuning
P2 Sensitivity control
S2 A : DC or pulses width
B : Functional tests
SI A: Static tests
B : Functional tests
L---+J 0\
outTOA4433
TDA4431133
o or3V(DC)
: r:-u7 B
HL
Digital AFC
'N F
_ '-_-+--i_O+VS"'12 V
Oor3V(OC1
Jl
(*'r
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (refer to the test circuit; Vs
12V,
Tamb
100 °C/W
= 25°C, unless
otherwise specified)
Test conditions
Parameter
Vs
Supply voltage range (pin 1 )
Is
Supply current (pin 1)
V s =14.5V
V2
Output voltage: low
ftuning
medium
high (TDA4431)
V2
Output voltage
(TDA4433)
Min.
10.8
< fo
Typ.
Max.
Unit
14.5
V
30
mA
0.8
V
8.5
V
ftunin£ = fo
Vs = 10.8 to 14.5
5.5
ftuning
>
Vs-0.5
V
ftuning
< fo
Vs-0.5
V
fo
12 = lmA
ftuning == fo
0.8
V
> fo
0.8
V
ftuning
839
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
V6
Output voltage
(TDA4433)
Min.
Typ.
Max.
Unit
ftuning
< fo
16 = lmA
0.8
V
ftuning
= fo
16= lmA
0.8
V
ftuning
> fo
V
Vs-0.5
12
Output cu rrent
(TDA4431)
V3
I nput voltage range
V 3U
Upper threshold voltage
(see fig. 2)
V 4 -25
V 3L
Lower threshold voltage
(see fig. 2)
V 4 -425
R3
I nput resistance
V3 = V 4
V4
Regulated voltage
14 = lmA
14
Output current
R4
Output differential resistance
f:..V 4
-f:..Ts
Regulated voltage thermal drift
± 25
IJ-A
8
V
V4
V 4 +25
mV
V 4 -400
V 4 -375
mV
4
Mn
1.4
V
6.6
1
n
60
±2
mVrc'
VlO
Identification
output
voltage
RIO
Output resistance
V 12
Switch off threshold voltage
112
Input flyback current
R12
Input resistance
lfly
Flyback pulse duration
10
17
}.lsec.
t
Time delay between leading
edges of flyback pulse and
sync. pulse
0
3.5
J.l sec.
Vl3
Video input signal
(peak to peak)
2.5
4.5
V
no identification
110 = lmA
mA
V
Vs-l.3
identification
Vl3
Sync. pulse amplitude
(above black level)
Rl3
I nput resistance
20
0.5
V 12 = 3V
1
V
1.5
mA
Kn
10
0.52
V
1.5
840
mV
n
100
Kn
Fig. 2 - Digital AFC threshold voltage vs. frequency.
Fig. 1 - Medium output Voltage Vs. Supply voltage.
('_31,7
"
MEDIUM
",
V
-
/'
V""
/'
;-
.....-v
,/
V-
/'
M~ / '
/'
.....- V
• 25m'"
"t.-O.4V.Z5mv
/'
14
'Is (v)
TDA4431
I nput Voltage
(V3)
V3> V 4
V 4 -0.4V
V3
< V3 < V 4
< V 4 -O·4V
TDA4433
Output voltage
(V 2 )
Output voltage
(V 2 )
Output voltage
(V 6 )
Low level
High level
Low level
Medium level
Low level
Low level
High level
Low level
High level
APPLICATION INFORMATION (refer to the block diagram)
TV signal identification circuit:
The circuit recognizes only TV signals by checking 'Iogically during one line the coincidence between
the horizontal flyback pulse and the pulse detected by a sync. separator.
The signal identification is carried out by charging the capacitor connected to pin 5; when the capacitor
voltage overcomes a fixed threshold voltage, a Schmitt trigger switches and enables the AFC control. If
a TV signal is recognized, the capacitor is slightly charged every line and its voltage reaches the threshold
after a number of line which is defined by the value of the capacitor itself. The sensitivity of the identification circuit, hence the number of lines required to charge the capacitor, can be adjusted by means
of the resistor connected between pin 11 and ground.
When the identification has been made, a signal (level L) is available at pin 10.
841
Threshold circuit:
The circuit detects 3 ranges of AFC voltage and in combination with the TV signal identification circuit
drives the electronic switches.
With a correct TV signal, the output levels corresponding to the 3 ranges are:
TDA4433
TDA4431
(V 2 )
fa - Ii f
L
(V 2 )
(V 6 )
H
L
fa
M
L
L
fa + Ii f
H
L
H
L
M
H
~
~
~
Low level
Medium level
High level
Note that the output levels are different for the two devices.
The TOA4431 provides three output levels: low (L), medium (M) and high (H). The output at pin 2
remains at medium level if no video signal is applied at the input or if a video signal is applied but is not
identified as a true TV signal.
The TOA 4433 has two separate outputs which can have only two states, high (H) or low (L). The outputs at pin 2 and at pin 6 remain at a low level with no video signal input or with a video signal not
identified as a true TV signal. Both pin 2 and pin 6 are open collector outputs and must be pulled.,up
to the positive supply voltage by external resistors.
Voltage Regulator
The circuit can deliver 1 mA and it can be used as. Of A converter reference to supply fine tuning voltage.
Fig. 3 - Application circuit
LS HS
~----c ldentif. out
Digital AFC out
(TDA 4433 only)
Digital AFC out
(TDA4 431 and
TOA 4433)
Pos. video out
Po,
Ily. in
842
5-403211
The passive components should be chosen as follows:
R 1 and R2
: these define the AFC response slope. For R 1 = R 2 = 5.1 KQ, the typical slope is 750/11
KHz/V (with AFC output unloaded).
Sl
: switches between low slope (LS) and high slope (HS). The high slope is typically 88/11
KHz/V.
R3 and R4
: the ratio (R3 + R4 )/R 3 defines the digital AFC width (of) calculated from the linear
AFC width (26f). With V 5 = 12V, the relation is:
Df = 0.036 (26f)
RT 1
:
by means of this trimmer it is possible to align the linear tuning with the digital one,
at the same frequency. The typical relation is:
with R3 = 3.3KQ, Ra can be a fixed resistor of 11 OKQ.
RT2
: by means of this trimmer it is possible to choose the better sensitivity. It is possible to
put a fixed resistor at pin 11 in the range of 68 Kn to 100 Kn.
To make a better sensitivity adjustment of trimmer R T2 , it is necessary to use only a weak signal at the
antenna. The video information must be a black picture or a field of small white points on a black field.
Furthermore, the action of the syncs separator must be as quick as possible.
In receivers with automatic program search, Sl should be in the HS position and then the components
Sl, R 1 and R2 can be omitted completely.
Fig. 4 - Linear and digital AFC
2" f
Vout pin 16
TOA 4420(AFCou!)
Low Slope
VOUI pin 2
TOA 4431
A
MH,
ca.rrier)
5-4033
843
EPM SYSTEM CONFIGURATIONS
1) For 16 channels
M 193
1 ___M__19_3_A__~
__T_D_A
__
4_43_1__~--------------~~,_
M 193 C
'2) For 32 channels
'--__
T_D_A_4_4_33__
~~-----------~--~~
____M_2_9_3____
3; With microprocessor
TDA 4433
11
844
P
~
LINEAR INTEGRATED CIRCUIT
MULTIFUNCTION SYSTEM FOR TAPE PLAYERS
The TDA 7270S is a multifunction monolithic integrated circuit in a 16-lead dual in-line plastic package
specially designed for use in car radios cassette players, but suitable for all applications requiring tape
playback.
It has the following functions:
Motor speed regulator
Automatic stop
Manual stop
Pause
Cassette ejection
Radio - Playback automatic switching.
The circuit incorporates also:
Thermal protection
- Short circuit protection to ground (all the pins)
ABSOLUTE MAXIMUM RATINGS
Vs
11
15
Ptot
Tstg ;Tj
Supply voltage
Sink peak current at pin 1
Sink peak current at pin 5
Power dissipation at T amb ';;; 80°C
Storage and junction temperature
20
2
V
A
2
A
1
W
-40 to 150
°C
ORDERING NUMBER: TDA 7270 S
Dimensions in mm
MECHANICAL DATA
845
6/82
CONNECTION DIAGRAM
(top view)
16
MOTOR
S~EED
15
REG.
14
CASS, SWITCH 4
13
RELAY
12
GND
DRIVER
AUT. STOP
11
EJECTION
10
Vs
5- 321"
BLOCK DIAGRAM
~~----------------~
M
+V5 9
LSJ:
C~~Sl
RELAY
( 1A MAX)
,
RELAV
(150mA MAX)
9 to16
ROTARY
SWITCH
5 - 3 S67/1
846
c.
~~
"
~
~"
,
~= ~
'
~:" 7::~;
~ ~").
,
'"
847
~c_cc
',
~""'" ;lit
y "'" ~
c
~~
_ _ _ c__
©
_c _ _ _ _ _ _ _
TEST CIRCUIT
tV5~
15 Jl
lOKfi
A'08
s,
J.~
THERMAL DATA
Rth j-amb
Rth Hoase
max
max
Thermal resistance junction-ambient
Thermal resistance junction-pins
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; T amb = 25°C;
15
°C/W
°C/W
Vs = 14V;
57 at
70
B, unless otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Is
Test conditions
Max.
Unit
18
V
Automatic stoP-S3 at B
S4 at B
5
10
Pause - S3 at A; S4 at A
9
15
Maximum output current
Thermal shut-down case
temperature
Typ.
6
mA
mA
150
for relay driving
Tsd
Min.
Ptot
~
1W
105
( I'N ref ~ -5%)
V ref
848
125
°C
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
MOTOR SPEED CONTROL
I MS
Starting current {pin 1)
V ref
Reference voltage (pin 2-3)
1
IM= 100 mA
1.15
A
1.25
1.35
V
0.4
%/V
0.03
%/mA
/l,V ref //1, V
V ref
S
IM= 100 mA
V 5 = 8 to 18V
0.1
/l,Vr~//I,IM
IM= 50 to 400 mA
0.01
IM= 100 mA
T amb = -20 to 700C
0.01
V ref
/l,V ref //1, T
V ref
V2
Operating voltage
K
~//I,V
K
Reflection coeff.{K= 1M/IT
see fig. 12)
IM= 100mA
/I, V ref = -5%
V ref
IM= 100mA
V
2.4
18
IM= 100mA
V 5= 8V to 18V
5
%/oC
-
20
22
0.3
1
%/V
0.02
%/mA
~//I,IM
I M= 50 to 400 mA
0.005
~//I,T
IM= 100mA
T amb= -20 to 700 C
0.01
K
K
%/"C
PAUSE
13
Current consumption
V S- 1
S4 at A
1.4
mA
S4 at A
0.2
V
EJECTION
17
20
S2 in A
Vs-s
Saturation voltage
I s =100mA
Vs
Satu ration voltage
Is-s= 1.5A
V4
(Pause condition)
Sl at A
V4
(Radio)
Sl at A
V4
(Tape)
Sl at A
Ro
Output impedance at pin 4
S3 at B
S3 at A
S4 at A
6
S3 at B
S4 at B
6
S3 at A
S4 at B
fJ.A
2.1
3
V
2.2
3
V
V
V
9
16
1.7
V
22
Kn
1
fJ.A
1
fJ.A
19.5
fJ.A
AUTOMATIC STOP
V S- 1
Saturation voltage
Sl at B
16
Minimum current to avoid
stop
Sl at C
17_S
Load current for delay circu it
16= 0
S2 at B
S7 at A
849
S3 at B
S2 at B
10.5
15
Fig. 1 - Reference voltage
vs. supply voltage.
G-~UGI1
f
I
)
IM~'OOmA
.,
,
Fig. 3 - Reference voltage
vs. ambient temperature.
Fig. 2 - Reference voltage
vs. motor current.
(3-'14711
Vref
,~ f
"f
./.)
"
I
)
I
(
Vs " 1"V
1.3 5
,
5
I
i
/
f.2 6
.......
"
1.25~-+I--=!--+--+-I--+-+-+-k-+
(
5
I--
4
5
1---,
i
i
,
1.1Sf---+-+----l--+-+-+--f---+-+---l
:
>'6
I
1
I
I
1
I
T
I
100
15
I-Ig. 4 - Saturation voilage
(pins 5-8) vs. pin 5 current.
-20 -10
4001M(mA)
0
+10 +20 +30
+40 +50 1amb('C)
!=:g. e - Ref!e~tk~~ c0~f
ficient vs. motor current.
riy. 5 - nt:fit:Cliui~, Cu~f
ficient vs. supply voltage.
r-'--r-.--'--r-'--r--r~~~
~+--+-I--+--+-+--+-~-+~,{~)
22
f---+-+---l--++--l--+-+--l---!'5
~+-~-+--~4--+~~+-~~'5
,/
,/
~+-~-+--t-4--+~1---+--r~-5
,/
"
150
fOO
200
IS (mAl
200
fOO
Fig. 7
Reflection coefficient vs. ambient temperature.
Fig. 8 - Pin 1 saturation
voltage vs. motor current.
G-~153
)
~
oM
)
1---+'-,,-.-\c14c;,,_L-+--~+--+~--+--1«
1 =100 rnA
f-4--+---I--+--+-+--+-+--+---+'5
1/
V
f-4--+---I--+-~-+--t-4---+---+'5
"
f-4--+---I--+-+-+~+-+--+---+
./
:,...-
./
V
-20
-10
0
+10
0.3
+20 +30 +40 +50Tamb{'C)
850
0.6
09
/
300
400 lM(rnA)
APPLICATION INFORMATION
The TDA 7270S incorporates four different functional blocks:
1) Motor speed contro I.
2) Autostop circuit.
3) Radio/Playback switching
4) Relay driver.
The motor speed control is a conventional circuit providing correction for the internal losses of the
motor. Fig. 9 shows the external circuit.
The values of RT , Rs and RK determine the regulation characteristics and motor speed.
RT
=
K· RM
where K = the IC regulator reflection coefficient and RM = motor internal resistance.
The following condition must be always satisfied
Rs
<
4 RT
Fig.9
S-4358
The voltage applied across the motor is given by
VS -
1 =
RT
1)
+ _RK 1
V ref [1 + ~ ( 1 + -K
Rs
and this is proportional to RK which therefore adjusts the speed.
The voltage between pin 2 and the supply must not fall below 0.3V and so
[V ref
RT
min
(~s ) + 1M
RT
min
(---.-)
1>
0.3V
Kmax
<
<
The "pause" condition corresponds to V 3
50 mV; in this condition the motor will stop (V 1-8
0.2V),
the capacitor C2 on the autostop circuit (see below) will no longer be charged and the pin 4 (cassette/
radio switch output) will be pulled high.
851
APPLICATION INFORMATION (continued)
The autostop circuit is shown in fig. 10.
In normal operation the capacitor C2 (22 }.IF) is slowly charged by a constant current drawn by pin 7 of
15 }.lA, and each time the pulser (a switch on the cassette take-up speed shaft) closes, C2 is discharged.
If the cassette stops, and the pulse stops, the voltage on pin 7 falls.
This switches the power amplifier state and pin 5 goes low. Pin 5 can be used for one of two purposes:
1} to drive a stop warning light connected from pin 5 supply Vs.
2} to actuate a solenoid wired eitherto ground (to release the cassette) or to supply (to eject the cassette).
The pause and/or cassette/radio switching shown in fig. 11 has an input/output on pin 4.
If pin 4 is not used it should be grounded.
This pin has the following logic.
Fig. 11
Fig. 12 - Application circuit
Function
Cass IN
Pause
Pin 4
Open
Open
>6V
motor off/radio on
Open
Close
>6V
motor off/radio on
Close
Open
< 1.7V
Close
Close
>6V
motor on/casso on
pause/radio on
+vso--~----~-----~~,..-'
C2
Ego
.--1--1-:---+-----:::~~}_---
R2
R1
RM
il]R5
T
'l
'I
CASS
SWITCH
£TTE
5-390311
EJECTION
852
DESCRIPTION OF OPERATION (Refer to fig. 12)
When the cassette is introduced the switch T 2 closes, the motor start to turn and the rotary switch
generates the pulses which keep the levels of pin 5 and pin 7 high. A relay between pin 5 and ground
holds the cassette. If there are no pulses at pin 6 (because tape stopped) or if the ejection switch T I is
closed, the voltages at pin 5 and pin 7 drop; the relay is thus de-energized and the cassette ejected; as
soon as the cassette is ejected, the switch T 2 opens and the motor stops. The capacitor at pin 7 dis·
charges allowing the system to start again when another cassette is inserted. In other types of mechanical
systems the cassette is ejected by energizing a relay; in this case the relay must be connected between
pin 5 and the supply; the sequence of operations is then the same as described above. If the pause switch
T 3 is closed, the motor stops even though there are no pulses at pin 6, the voltage levels at pins 7 and
5 remain high so the cassette is not ejected and the motor is ready to start again as soon as the pause key
is released. A voltage for driving the radio-tape switching is available at pin 4. This voltage level is high
(> 6V) with stopped motor and is low « 1.7V) with running motor.
APPLICATION SUGGESTION (See figure 12)
Component
RI
Recommended
value
10Kn
Purpose
Limits current
from pin 7
R2
560 Kn
By rotary switch
it produces pulses
which disable the
automatic stop
R3
10Kn
Limits the motor
current during
pause (T 3 closed)
R4
2.2 Kn
Rs
560Kn
R6
1 Mn
Larger than
recommended
value
Smaller than
recommended
value
Allowed range
Min.
Max.
0
100Kn
Delayed ejection.
Possibility that
ejection does not
work
High driving
current at pin 7
Undesired
operation of
automatic switch
Possibility of
audio interference
spikes
100Kn
2Mn
Reference voltage
Higher motor
current during
pause (T 3 closed)
with delayed stop
of motor
1Kn
47Kn
Voltage at pin 4
decreases. RadioPlayback switching
could not work
1.5Kn
2.7Kn
variation
Fixes voltage of
pin 4 du ring pause
and playback
Voltage at pin 4
Compensates for
cu rrent loss
between pin 6
and ground
Limited
compensation
Necessity to
increase C I and
decrease R2
100Kn
00
Limited
Possibility that
automatic stop
will not work
560Kn
00
Compensates for
current loss
between pin 7 and
grou nd. Also
reduces recovery
increases
compensation
time
RT
K-R M
(typical values)
Compensates for
voltage drops at
motor terminals
vs.l'> 1M
Danger of
oscillations
853
Poor speed
regu lation versus
l'>IM
See note
on next page
APPLICATION SUGGESTION (continued)
Component
Larger than
recommen",ded
value
Smaller than
recommended
value
Fixes the current
value in RT and
and RK for IM= 0
Danger of
saturation of non
inverting input of
regulator (pin 2).
Considerable speed
variation for small
variation cif R K
I mpossibil ity to
obtain a low motor
speed
Fixes the
requested V 8 - 1
Wide speed
variation versus
Recommended
value
Purpose
Rs
SeeNote(*)
RK
See Note (*)
C1
0.1 J-LF
DC isolati on
Allowed range
Min.
Max.
4 RT
Limited speed
variation versus
'" RK
'" RK
Electrolytic
Undesired
automatic stop
capacitors cannot
0.047
J-LF
be used
I
C2
22 J-LF
C3
10J-LF
Rotary
switch
frequency
20 Hz
Low recovery time.
Undesired
automatic stop
I ntegrates the
pulses of the rotary
switch
High recovery time
By pass
Wow and flutter
problems
I nstability at low
temperature
Keeps automatic
Possibility of audio
interference spikes
Necessity to increase
stop off
3.3 J-LF
22 J-LF
5J-LF
C 1 and C 2
NOTE (*):
RT
1
RK
V 8-1 = V ref [1 + - - (1 + -K) + - R - j from wh ich it can be seen that V 8-1 varies Iinearly with R K .
Rs
5
The voltage between pin 2 and the supply must not fall below 0.5V, so the following expression must be verified
RT
RT
[Vrefmin (R-)+IMmin (-K--)j > 0.3V
5
max
During the pause, the voltage between pin 3 and ground must be lower than 1.3V.
n
VS.
~
(rpm)
n
2100
'5
2000
1900
co,.)
Vs ,,14V
(rpm)
("t.)
Vs =14V
I M ,,100mA
+5
2100
f.....-
2000
r-
7
On
--;;-
(rpm)
(O,.)
~:100mA
Fig. 15 - Speed variation
vs. ambient temperature
Fig. 14 - Speed variation
motor current
Fig. 13 - Speed variation
vs. supply voltage
+5
2100
2000
I-5
1900
1900
-5
i
14
16
16
20
o
20
40
60
60
lOa
120 140
854
160 IM(mA)
-40 -20
0
20
40
60
SO
lambC'C)
;,."
~
,*
"'\
j
.'
, ' , : .:
~
IT'
~
,~"""
\
~
'
,
,
"
,
''''Hi
APPLICATION SUGGESTION (continued)
Fig. 16 - Delay time of the relay driver
Fig. 17 - Low cost application circuit
(C 2 = 2.2I'F)
VOLTAGE
AT PIN 5
5-3898,1
V51
0.5
U,
.
I
1.5
.
t (sec)
The circuit shown in fig. 17 offers the following functions:
1)
2)
3)
4)
motor speed regulation
automatic stop
autostop warning light
pause.
The circuit incorporates an additional resistor/diode from pin 3 to pin 5. When the cassette stops, and
the pulser no longer generates pulses, pin 5 falls to a low level and the stop indicator is on.
Pin 3 is pulled low through the 1 Kn resistor and the diode, however pin 3 must not be pulled lower
than 1.3V since this would cause pin 5 to go high again. The current of about 1 mA out of pin 3 causes
V3-5 to be about 1.5V.
In this way the motor remains stopped and pin 5 remains low.
MOUNTING INSTRUCTIONS
Fig. 18 - Example of heatsink using PC board
copper
Fig. 19 - Example of external heatsink
30mm.
cs- 0'00
~--------65mm-------~
Figures 18 and 19 show two ways to make the device dissipate.
In both cases, Rth = 35°C/W.
855
I
Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for the consequences of its use nor for
any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of SGS-ATES. Specifications mentioned in this publication are subject to change without notice. This
publication supersedes and substitutes all information previously supplied.
SGS-ATES GROUP OF COMPANIES
Italy - France - Germany - Malta - Malaysia - Singapore - Sweden - United Kingdom - U.S.A.
© SGS-ATES Componenti Elettronici SpA, 1982 - Printed in Italy
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