1982 Signetics MOS Microprocessor Data Manual

1982_Signetics_MOS_Microprocessor_Data_Manual 1982_Signetics_MOS_Microprocessor_Data_Manual

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~ro!lt, chip enable (CE), byte
select (BYTE), and readlwrite 1i'i1W) inputs
before each data bus transfer operation.

=0

~.E=1~~~~__;
(PROCESSOR SHOULD
LOAD TxDB)

During a read operation (R/W = 0>, the
leading edge of DB EN will initiate an MPCC
read cycle. The addressed register will
place Its contents on the data bus. If BYTE =
1, the 8-bit byte is placed on DB15-08 or
DB07-00 depending on the H/L status olthe
register addressed. Unused bits In ROSRL
are zero. If BYTE = 0, all 16 bits (DB15-00>
contain MPCC Information. The trailing
edge of OBEN will reset RxOA andlor RxSA
If RDSRL or ROSRH is addressed respectively.

TxBE: 1
(pROCESSOR SHOULD

CLEAR TEOM AND
DROPTxI!)

TxA = 0 - - - - - - - -

DB EN acts as the enable and strobe so that
the MPCC will not begin its internal read
cycle until OBEN is asserted.

i
Figure 7

and retransmit the message to recover This
is not compatible with IBM's BISYNC, so
that the user must not underrun when supporting that protocol.
CRC-16, if specified by PCSARs-,o, IS generated on each character transmitted from
TDSRL when TSOM = O. The processor
must set TEOM = 1 after the last data character has been sent to TxSR (TxBE = 1). The
MPCC will finish transmitting the last data
character and the CRC-16 field before sending SYNC characters which are transmitted
as long as TEOM = 1. If SYNCs are not
desired after CRC-16 transmission, the processor should clear TEOM and lower TxE
when the TxBE corresponding to the start of
CRC-16 transmission is asserted. When
TEOM = 0, the line is marked and a new
message may be iniated by setting TSOM
and raising TxE.
If VRC IS specified, It IS generated on each
data character and the data' character
length must not exceed 7 bits For software

LRC or CRC, TEOM should be set only If
SYNC's are required at the end of the
message block.

During a write operation (~IW = 1), data
must be stable on DB,5-08 andlor DB07-00
prior to the leading edge of DBEN. The
stable data is strobed into the addressed
register by DBEN. TxBE will be cleared if the
addressed register was TDSRH or TDSRL.

Special Case
The capability to transmit 16 spaces IS provided for line turnaround in half duplex
mode or for a control recovery situation.
This is achieved by setting TSOM and
TEOM, clearing TEOM when TxBE = 1, and
proceeding as required.

PROGRAMMING
Prior to initiating data transmission or reception, PCSAR and PCR must be loaded
with control information from the processor. The contents Of these registers (see
Register Format section) will configure the
MPCC forthe user's specific data communication environment. These registers should
be loaded during power-on initialization
and after a reset operation. They can be
changed at any time that the respective
transmitter or receiver is disabled.

Signetics

1·23

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

A2
BYTE = 0

a
a

=

1
1

BYTE = 1

AO

REGISTER

1

a

x
x
x

1

X

RDSR
TDSR
PCSAR
PCR'

Al

16-BIT DATA BUS

DB15 - DBOO

a

8-BIT DATA BUS

a
a
a
a

= DB7_0 or DB 15-8"

a
a

a

1
1

a

1
1

a

1

a
a

1
1
1
1

RDSRl
RDSRH
TDSRl
TDSRH
PCSARl
PCSARH
PCRl'
PCRH

1

a
1

1

NOTES
~ peR lower byte does not eXist It will be all "O"s when read
.. Corresponding high and low order pms must be tied together

Table 4 MPCC REGISTER ADDRESSING

BIT

NAME

00-07

Not Defined

08-10

RxCL

BOP/BCP

Receiver Character Length is loaded by the processor when RxCLE = o. The
character length is valid after transmission of single byte address and control fields
have been received.
10
9
Char. length (bits)
8
a
a
a
8
a
a
1
1
a
1
a
2
a
1
1
3
1
a
a
4
1
a
1
5
1
1
a
6
1
1
1
7

RxCLE

BOP/BCP

Receiver Character Length Enable should be zero when the processor loads RxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.

11

MODE

FUNCTION

12

TxCLE

BOP/BCP

Transmitter Character Length Enable should be zero when the processor loads TxCL.
The remaining bits of PCR are not affected during loading. Always 0 when read.

13-15

TxCL

BOP/BCP

Transmitter Character Length is loaded by the processor when TxCLE = O. Character
bit length specification format IS identical to RxCL It IS valid after transmission of
single byte address and control fields

Table 5 PARAMETER CONTROL REGISTER (PCR)-(R/W)

1-24

Signefics

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

BIT

NAME

MODE

FUNCTION

00-07

S/AR

BOP

SYNC/ADDRESS Register. Contains the secondary station address if the MPCC is a
secondary station. The contents of this register is compared with the first received nonFLAG character to determine if the message is meant for this station.
SYNC character is loaded into this register by the processor It is used for receive and
transmit bit synchronization with bit length specified by RxCL and TxCL

BCP
08-10

11

ECM

BOP/BCP

IDLE
BOP
BCP

12

SAM

13

SS/GA

BOP

BOP

BCP

14

PROTO
BOP
BCP

15

APA

BOP

10

1-8
0
0
BOP
0
BCP
0
1
8
0
0
1
0
--BCP
8
0
1
1
5-7
1
0
BCP
0
5-7
1
0
1
BCP
1
1
0
--5-8
1
1
1
BCP/BOP
processor dUring Initialization or when both data paths

9

8

Suggested Mode

Char. length

Error Control Mode
CRC-CCITT preset to 1's
CRC-CCITT preset to O's
Not used
CRC-16 preset to O's
VRC odd
VRC even
Not used
No error control
ECM should be loaded by the
are idle.

Determines line fill character to be used if transmitter underrun occurs (TxU asserted
and TERR set) and transmission of special characters for BOP/BCP.
IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1
IDLE = 1, transmit FLAG characters dUring underrun and when TABORT = 1
IDLE = 0 transmit initial SYNC characters and underrun line fill characters from the
S/AR
IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO dUring underrun.
Secondary Address Mode = 1 If the MPCC IS a secondary station ThiS facIlitates
automatic recognition of the received secondary station address When transmitting,
the processor must load the secondary address Into TxDB
SAM = 0 inhibits the received secondary address comparison which serves to activate
the receiver after the first non-FLAG character has been received
Strip SYNC/Go Ahead Operation depends on mode.
SS/GA =1 IS used for loop mode only and enables GA detection. When a GA is detected
as a closing character, REaM and RAB/GA will be set and the processor should
terminate the repeater function SS/GA =0 is the normal mode which enables ABORT
detection. It causes the receiver to terminate the frame upon detection of an ABORT or
FLAG
SS/GA = 1, causes the receiver to striP SYNC's Immediately following the first two
SYNC's detected SYNC's 10 the middle of a message will not be stripped SS/GA = 0,
presents any SYNC's after the mltlal two SYNC's to the processor
Determmes MPCC Protocol mode
PROTO = 0
PROTO = 1
All Parties Address. If thiS bit IS set, the receiver data path IS enabled by an address field
of '11111111' as well as the normal secondary station address

Table 6 PARAMETER CONTROL SYNC/ADDRESS REGISTER (PCSAR)-(R/W)
BIT

NAME

MODE

FUNCTION

00-07

TxDB

BOP/BCP

08

TSOM

Transmit Data Buffer. Contains processor loaded characters to be serialized 10 TxSR
and transmitted on TxSO.
Transmitter Start of Message. Set by the processor.to mitiate message transmission
prOVided TxE = 1.
TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS
generation (if specified) begins. FCS, as specified by PCSAR._ 1o , should be CRCCCITT preset to 1'so
TSOM = 1 generates SYNCs from PCSARL or transmits from TxDB for IDLE = 0 or 1
respectively When TSOM = 0 transmission IS from TxDB and CRC generation (,f
specified) begins

BOP

BCP

Table 7 TRANSMIT DATA/STATUS REGISTER (TDSR) (R/W except TDSR 15)

Signetics

1-25

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

BIT
09

NAME
TEOM

MODE

FUNCTION
Transmit End of Message. Used to terminate a transmitted message.

BOP

TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the
transmission of the data character in TxSR. FLAGs are transmitted until TEOM = O.
ABORT or GA are transmitted if TABORT or TGA are set when TEOM = 1.

BCP

TEOM = 1 causes CRC-16 to be transmitted (if selected) followed by SYNCs from
PCSARL or TxDB IIDLE = 0 or 1). Clearing TEOM prior to the end of CRC-16
transmission (when TxBE = 1) causes TxSO to be marked following theCRC-16. TxE
must be dropped before a new message can be initiated. If CRC is not selected, TEOM
should not be set.

10

TABORT

BOP

Transmitter Abort = 1 will cause ABORT or FLAG to be sent IIDLE = 0 or 1) after the
current character is transmitted. (ABORT = 11111111)

11

TGA

BOP

Transmit Go Ahead (GA) instead of FLAG when TEOM
termination In loop mode. (GA = 01111111)

12-14

Not Defined

15

TERR

Read
only
BOP
BCP

= 1. This facilitates repeater

Transmitter Error = 1 indicates the TxDB has not been loaded in time (one character
time -1/2 TxC period after TxBE IS asserted) to maintain continuous transmission. TxU
will be asserted to Inform the processor of this condition. TERR is cleared by
setting TSOM. See timing diagram.
ABORT's or FLAG's are sent as fill characters IIDLE = 0 or 1)
SYNC's or MARK's are sent as fill characters IIDLE = 0 or 1), For IDLE = 1 the last
character before underrun is not valid.

Table 7 TRANSMIT DATA/STATUS REGISTER (TDSR) (R/W except TDSR 15) (Cont'd)
BIT

NAME

MODE

FUNCTION

00-07

RxDB

BOP/BCP

Receiver Data Buffer. Contains assembled characters from the RxSR If VRC is
specified, the parity bit is stripped.

08

RSOM

BOP

Receiver Start of Message = 1 when a FLAG followed by a non-FLAG has been
received and the latter character matches the secondary station address if SAM = 1 .
RxA will be asserted when RSOM = 1. RSOM resets itself after one character time and
has no effect on RxSA.

09

REOM

BOP

Receiver End of Message = 1 when the cloSing FLAG is detected and the last data
character is loaded into RxDB or when an ABORT/GA character is received. REOM is
cleared on reading RDSRH, reset operation, or dropping of RxE.

10

RAB/GA

BOP

Received ABORT or GA character = 1 when the receiver senses an ABORT character If
SS/GA = 0 or a GA character If SS/GA = 1 RAB/GA IS cleared on reading RDSRH, reset
operation, or drOPPing of RxE. A received ABORT does not set RxDA.

11

ROR

BOP/BCP

Receiver Overrun = 1 indicates the processor has not read last character in the RxDB
within one character time +1/2 RxC period after RxDA is asserted. Subsequent characters will be 10st.RORisclearedon readingRDSRH,resetoperation,or droppingof RxE.

12-14

ABC

BOP

15

RERR

BOP/BCP

Assembled Bit Count. Specifies the numberof bits in the last received data character of
a message and should be exam ined by the processor when REOM = 1 (RxDA and RxSA
asserted), ABC = 0 indicates the message was terminated (by a FLAG or GA) on a
character boundary as specified by PCRS-10. Otherwise, ABC = number of bits in the
last data character. ABC is cleared when RDSRH is read, reset operation, or dropping
RxE. The resiaual cnaracter is rignt justified In RDSRL.
Receiver Error indicator should be examined by the processor when REOM 1 in BOP,
or when the processor determines the last data character of the message in BCP with
CRC or when RxSA is set in BCP with VRC.
CRC-CCITT preset to 1's/0's as specified by PCSARs-10:
RERR = 1 indicates FCS error (CRC ¥ FOB81 ¥ 01
RERR = a indicates FCS received correctly (CRC = FOB /=01
CRC-16 preset to a's on 8-bit data characters specified by PSCARs-10:
RERR = 1 mdicates CRC-16 received correctly (CRC = 01.
RERR = a indicates CRC-16 error (CRC ¥ 01
VRC specified by PCSARs-1o:
RERR = 1 indicates VRC error
RERR = a indicates VRC is correct

Table 8 RECEIVER DATA/STATUS REGISTER (RDSR)-(Read Only)

1·26

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

ABSOLUTE MAXIMUM RATINGSI
PARAMETER
TA
TSTG

Vcc

Operating ambient temperature2
Storage temperature
Input or output voltages
with respect to GND3
With respect to GND

RATING

UNIT

o to +70
-65 to +150

·C
·C

-0.3 to +15
-0.3 to+7

V
V

DC ELECTRICAL CHARACTERISTICS TA; O·C to +70·C, Vcc; +5V ±5%4,5
PARAMETER

LIMITS

TEST CONDITIONS
Min

VIL
VIH

Input voltage
Low
High

VOL
VOH

Output voltage
Low
High

Icc

Power supply current

ilL
IOL

Leakage current
Input
Output

CIN
COUT

Capacitance
Input
Output

Typ

UNIT
Max
V
0.8

2.0
V
IOL; 1.6mA
IOH; -100"A
Vcc; 5.25V, TA - O·C

0.4
2.4
150

VIN ; 0 to 5.25V
VOUT; 0 to 5.25V

10
10

VIN; OV, f ; lMHz
VOUT; OV, I ; lMHz

20
20

mA
"A

pF

AC ELECTRICAL CHARACTERISTICS TA; O·C to 70·C, Vcc ; 5V ± 5%4,5.6
2652-1

2652

PARAMETER
Min

UNIT
Typ

Max

Min

Typ

Max

tACS
tACH
tos
tOH
tRxS
tRxH

Setup and hold time
Address/control setup
Address/control hold
Data bus setup (write)
Data bus hold (write)
Receiver serial data setup
Receive serial data hold

50
0
50
0
150
150

50
0
50
0
150
150

tRES
tOBEN

Pulse width
RESET
DBEN

250
250

250
200

too
ITxo
tOBENO

Delay time
Data bus (read)
Transmit serial data
DB EN to DBEN delay

tOF

Data bus Iloat time (read)

150

150

ns

f

Clock (RxC, TxC) frequency

1.0

2.0

MHz

tCLKl
tCLKl
tCLKO

Clock high (MM - 0)
Clock high (MM; 1)
Clock low

ns

ns
m'

m'
ns
170
250

200
325
200

200

340
490
490

165
240
240

Signetics

ns

1·27

, MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)
NOTES
1 Stresses above those listed under "Absolute MaXimum Ratings" may cause
permanent damage to the deVice. This IS a stress ratmg only and functional operation
of the deVice at these or at any other condition above those indicated In the operation
sections of this specification IS not Implied
2 For operating al elevated temperatures the deVice must be derated based on +150°C
maximum JunctIOn temperature and thermal resistance of 60 0 elW Junctton to ambient
(lQ ceramiC package)
3 This product Includes circuitry specifically deSigned for the protectron of Its Internal
deVices from the damaging effects of excessive static charge Nonetheless, It IS
suggested that conventional precautions be taken to aVOid applYing any voltages
larger than the rated maxima

SC2652

Parameters are valid over operating temperature range unless otherwise speCified
All voltage measurements are referenced to ground All time measurements are at 0 BV
or 2.0V. Input voltage levels for testing are O.4V and 2.4V.
8 Output load CL .. 100pF.
7 m = TxC low and applies to writing to TDSRH only

TIMING DIAGRAMS
RESET

READ AND WRITE DATA BUS
DBEN':.._ _ _ _

tDBEN_
~===::==~-------

RESET-1='RES=f-Dor

D -===+V-==-....-:::=t-V--::==:-15

("EAD)'_===+"":~~'1'"....;.;=t-"'I':-:'-=DF:,FL;;O;;;AT.:..;';.;;NG=-_

---V+------t-V-----(WRITE)_..,-_++
______t-II'--,._____

DocrD15

'D"

CLOCK

Vi
A

TxSO

----~~I~----------+------------I-TXD_I
I

i

I

R'O,I

I

l-tcLKO
I
I

O,SI

1
/
-:-tCLK1- . . .____

I

l~tRxs-l_tRXH-I

~!

I

1-28

...J

,

I

I

X~----:
I

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

TIMING DIAGRAMS ICont'dl

T
=

TRANSMIT-START OF MESSAGE

1.S0

TxBE

DBEN

T>. _ _...J

T,A _ _ _ _ _ _..1

NOTES

3

SYNC may be 5 to 8 bits and will contam panty bit as specIfied
TxA goes high relative to TxC nSlng edge after TSOM has been set and TxE has been
raised
TxBE goes low relatIVe to DBEN fallIng edge on the fIrst write transfer Into TDSA. It IS
reasserted 1 TxC time before the 'Irst bit of the transmitted SYNC/FLAG TxBE then
goes low relatIVe to DBEN failing edge when writing mto TDSRH and/or TDSRL It IS
reasserted on the rasing edge of the TxC that corresponds to the transmlsston afthe
last bit of each character, except In BOP mode when the CRC IS to be sent as the
next character (see Transmit Timing-End of Message)

TRANSMIT-END OF BOP MESSAGE

TxSO

NEXT TO LAST CHAR

LAST CHAR

CRC

-----~---~----~--~

RESET TEOM

DB EN

r-j-----r----

TxE 5

\I

"A~6------------------------------------------------------~,·--------NOTES

4

5
6

TxBE goes low relative to the failing edge of OBEN corresponding to loading
TOSAH/l It goes high one TxC before character transmiSSion beginS and also when
TxA has been dropped
TxE can be dropped before resetting TEOM If TxBE (correspondIng to the closing
FLAG) IS high Alternatively TxE can remain high and a new message Initiated
TxA goes low after TxE has been dropped and 1 1/2 TxC's after the last bit of the
closing FLAG has been transmitted.

Signetics

1·29

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

TIMING DIAGRAMS (Cont'dl
TRANSMIT TIMING-END OF BCP MESSAGE

T)[50

NEXT TO LAST CHAR

LAST CHAR

MARK

T~BE~
LOAD LAST CHAR

DBEN

SET TEOM

RESET TEOM

J""--__. . .nl...._ _ _--InI...._ _ _ _ _ _ _ __
1------------------------

T,E

TxA

r---------

NOTES
7

When 2652 generated CRG IS not reqUired, TeOM should only be set If SYNCs are to
follow the message block In that case, TxE should be dropped In response to TxBE
(which corresponds to the start of transmiSSion of the fast character' When CRG IS
required, TxE must be dropped before CRC transmiSSion IS complete Otherwise, the
contents 01 TxDB will be shifted out on TxSO This faCilitates transmiSSion of contiguous messages

TRANSMIT UNDERRUN
T,C

T.U~

DBEN

_ _____________~SETTSOM

11--

NOTES
8

9

1-30

TxU goes active relative to TxC failing edge If TxBE has not been serviced after n-1/2
TxC times (where n = transmit character length) TxU IS reset on the TxC failing edge
follOwtng assertion of the TSOM command
An underrun will occur at the next character boundary If TEOM IS reset and the
transmitter remains enabled, unless the TSOM command IS asserted or a character IS
loaded tnto the TxDB

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

TIMING DIAGRAMS

~

I

~

(Cont'dl

RECEIVE-START OF MESSAGE

I

R,A

-r+----....,

-r---....,

1ST CHAR READY
TO BE READ

2NO CHAR READY
TO BE READ

OBEN

SIF"

R.E

~......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

J

NOTES

RxA goes high relative to failing edge of Rxe when RxE IS high and
a A data character following two SYNC's IS In RxDB (BCP model
b Character following FLAG IS In RxDB (BOP primary station mode)
c Character following FLAG IS In AxDB and character matches the secondary
station address or All Parties Address (BOP secondary station model
10 RxDA goes high on Rxe failing edge when a character In RxDB IS ready to be read It
comes up before RxSA and goes low on the failing edge of DB EN when RxDB IS read
11 S/F goes high relative to riSing edge of Rxe anytime a SYNC (BCPl or FLAG (BOP) IS
detected
9

RECEIVE END OF MESSAGE

~-------------------------1-------------------------------_·
RI(A 14

1------------,

NOTES
12 At the end of a BOP message, RxSA goes high when FLAG detection (S/F = 1) forces
REaM to be set Processor should read the last data character (ROSRL) and status
(ROSRH) which resets RxDA and RxSA respectively For BCP end of message, RxSA
may not be set and SI F = a The processor should read the last data character and
status
13 RxE must be dropped for BCP with non-contiguous messages It may be left on at the
end of a BOP message (see BOP Receive Operation)
14 RxA IS reset relative to the failing edge of Rxe after the closing FLAG of a BOP
message (REOM = 1 and RxSA actIve,) or when AxE IS dropped

Signetics

1·31

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

TYPICAL APPLICATIONS
2652 MPCC MICROPROCESSOR INTERFACE

BbB.-

r

DATA BUS

PO"

RESET

I~

T5 BUFFER

T,C

'"'1..::.1
"'C

080.7

8 BIT

-G-

MPCC

uP

SYNCHRONOUS

2652
ADDRESS

CONTROL

MODEM

A2-G, AIW DBEN CE

lxSO

0-me-

RxSI

R..

-B--G-

T,E

RTS, CTS,
DTR, OS A,

OCD
MODEM
CONTROL

'----

DCD

CTS

LOGIC

NOTES

1

2

3
4

5

Possible ~p mterrupt requests are
RxDA, RxSA, TxBE, TxU
Other 2652 status signals and possible uses are
S/F hne Idle indicator, frame delimiter
RxA handshake on RxE, Ime turn around control
TxA handshake on TxE, hne turn around control
Line Drivers/Receivers (LD/LR) convert EIA to TTL voltages and vice-versa
ATS should be dropped after the CAe (Bep) or FLAG (BOP) has been transmitted
ThiS forces CTS low and TxE low
Corresponding hIgh and low order bits of DB must be OR tied

DMA/PROCESSOR INTERFACE
DATA BUS

~~

. / 8 OR 16 BITS

~}
RDREQ

WORD COUNT

R/W CONTROL

1

DATA BUS

A""

ADDRESS PTR

I

~~

DATA BUS

DB U .. OO
RaDA

I

A,E

TO PAofESSOA

RaSA
WRREQ
TaBE

OMA

T,A

....

CONTROLLER

T,E

PROCESSOR (P)

T,U

SUPPORT
LOGIC

S/F

1 INITIALIZES 2652
2 SETS/RESETS TSOM,
TEOM
3 RESPONDS TO
RISA

AND

A2·AO

2652
ADDRESS AND
CONTROL

BYTE
RESET

l!IW

-A,OA
-T,BE

AIW
MEMORY

MM

CE
DBEN

.

ADDRESS, RIW CONTROLS

~

A,C

noc

RxSl T.sO

ADDRESS, RM, CONTROL

t J~oAL 1
System Address and Control Bus

For non-DMA operation, TxBE and RxDA are sent to the processor which then loads or
reads data characters as required

1·32

Signetics

ADDRESS, CEo RM

,

MICROPROCESSOR DIVISION

JANUARY 1982

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER (MPCC)

SC2652

TYPICAL APPLICATIONS (Cont'd)
CHANNEL INTERFACE

COMPUTER

OR
TERMINAL

MPCC

MPCC

2652

2652

G--G---

TxSO

COMPUTER

OR
TERMINAL

RxSI

No Modem-DC Baseband Transmission

2652/2653 INTERFACE
TYPICAL PROTOCOLS: BISYNC, DDCMP, SDLC, HOLC
TxBE TxU RxDA RxSA

INTERRUPTS

U

II
087 - DBO

2652
MPCC

r---

hO

~R.D

A2
A1

I - TxC
f-+- Rxe

AD

R/W
DBEN
CPU

PBOBO

CE

4

CEO

A1

2653
PGC

Fi/w
AO
CE1

f

t

iNf
(OPEN DRAIN)

I

5V

Signetics

1·33

MICROPROCESSOR DIVISION

JANUARY 1982

POLYNOMIAL GENERATOR CHECKER (PGC)
DESCRIPTION
The Signetics 2653 Polynomial Generator
Checker (PGC) is a polynomial generator
checker I character comparator circuit that
complements a receiver Itransmitter (R/T or
USART I USRT I UART) in the support of
character oriented data link controls. Table
1 defines many of the more commonly used
PGC terms and abbreviations.
Parallel data characters transferred between the CPU and R/T are monitored by
the PGC which performs block check character (BCC) and parity (VRC) generation I checking, single character detection,
and two character sequence detection.
Since the PGC operates on parallel characters, the data transmission format may be
serial (synchronous or asynchronous) or
parallel.
There are four modes of BCC accumulation
and each mode can select one of three polynomials to compute the BCC. In the BISYNC
normal and transparent modes, the PGC determines which characters are to be accumulated and which characters are to be excluded 'rom the accumulation. The block
terminating characters and the initiation and
termination of BISYNC transparent text can
be detected and an interrupt generated. The
single interrupt output represents the inclu~
sive OR of four maskable status conditions.
In the automatic accumulation mode, all
characters are accumulated while the single
accumulate mode requires a specific accu~
mulation command for each character to be
accumulated.
Character accumulation control and character comparisons are facilitated by a character class array which places each of 128
characters into one of four character
classes. The four classes are normal,
SYN I BISYNC not included, block terminating character (BTC) I search character (SC),
and secondary search character (SSC).
Additional PGC applications include off-line
R IT operation where the BCC is generated
on data not sent to the R/T, BCC multiplexing by sharing the PGC among several R/Ts
and reading I writing the partial BCC accumulation on a character by cnaracter basis,
VRC generation I checking on characters
appearing on a bidirectional data bus, and
programmable character comparisons or
searches.
PGC operation is half duplex (either receive
or transmit, one way or two way alternate).
Full duplex (two way simultaneous) is
achieved by using two PGCs. The device is
directly compatible with the Signetics 2651
Programmable Communications Interface
(PCI) and 2661 Enhanced Programmable

1-34

SC2653

Communications Interface (EPCI). When
used in BISYNC modes with the 2661, software requirements are minimized by the
2653-2661 control character comparisons,
character sequence comparisons, and automatic OLE insertion I detection.

PIN CONFIGURATION
Vee

Other bus oriented R/Ts can be interfaced
to the PGC with a minimum of external circuitry. See figure 1 for a typical system configuration.
This NMOS LSI circuit is TIL compatible,
operates from a single + 5V supply and is
contained in a 16 pin dual in line package.

TOP VIEW

FEATURES
• Parallel Block Check Character
accumulation/checking: CRC-16,
CRC-12, LRC-8
• BISYNC normal and transparent modes
• Automatic or single character accumulation modes
• Character detection - up to 128 characters
• Two character sequence detection; examples: DLE-STX, ACK 0, ACK 1,
WACK, RVI, DISC, WBT
• 6, 7, or 8-bit characters
• VRC generation / checking on data bus
• Four maskable Interrupt conditions
• Four classes of characters
• Internal power-on reset
• Maximum character accumulation rate
of 500 kHz (4 Mbps)
• Directly compatible with Signetics
2651, 2652 and 2661
• No system clock required
• TTL compatible Inputs and outputs
• Single 5V supply
• la-pin dual In line package

APPLICATIONS
• Character oriented data link control:
-dedicated to one USART /USRT
-multiplexed
among
several
USART/USRTs
• Automated BISYNC with 2661 (minimal
software Intervention)
• acc and VRC generation / detection on
a block of memory or peripheral data
• Programmable character array comparator

BLOCK DIAGRAM
The PGC consists 01 six major sections.
These are the operation control, character
class array, OLE ROM, character register,
BCC and parity generators, and BCC registers. These sections communicate with
each other via an internal data bus and an
internal control bus. The internal data bus
interfaces to the CPU data bus via a data
bus buffer.

ORDERING CODE
PACKAGES

COMMERCIAL RANGES
VCC = 5V ± 5%, TA = O"C to 70"C

Ceramic DIP

SC2653CSI16

Plastic DIP

SC2653CSN16

MICROPROCESSOR DIVISION

JANUARY 1982

POLYNOMIAL GENERATOR CHECKER (PGC)

SC2653

BLOCK DIAGRAM

.1

00-07

DATA BUS

BUFFER

.1

K

DATA BUS

+

r--

Dl.E

~
DETECT

OPERATION CONTROL

'---

~i

0

,

MOOE REGISTER

,

COMMAND REGISTER

I

STATUS REGISTER

w

~

0

CHARACTER REGISTER

I

ace AND VRC
GENERATION UNIT

~'"I

I

J.

~
~

_.t

BCCUPPER

§

BI"I
CHARACTER CLASS
ARRAY

II

i~
~

"

l'·

8

\.

I

II

acc LOWER

B"

I

U

PIN DESIGNATION
MNEMONIC
VCC
GND

NAME AND FUNCTION

PIN NO.

TYPE

16

I

+5V: Power supply
Ground

a

I

11,12

I

Address LInes: Used to select internal PGC registers or character class array

Fi/w

13

I

Read/Write: Read command when low, write command when high

CEO

15

I

Chip Enable: Connected to chip enable input of a receiver Itransmitter (R IT) circuit. It is used
to strobe data being transferred between the CPU and the Fi IT into the PGC character
register.

CE1

14

I

ChIp Enable: Used in conjunction with the Fi I W signal to enable the transfer of data between
the PGC and the CPU or DMA controller and to initialize the PGC registers.

9,7-1

1/0

Data BU8: a-bit three-state bidirectional bus used to transfer data to or from the PGC via CEO
or CE 1. All data, mode words, command words, and status information are transferred on this
bus. DO is the least significant bit; 07 is the most significant bit.

10

0

Interrupt: Open drain active low interrupt output that signals the CPU that one or more
maskable conditions are true: acc error, VRC error, BTC I SC detect, SSC detect. The true
conditions can be determined by reading the status register which in turn deactivates INT. A
power on, clear BCC, or master reset command causes INT to be inactive (high).

Al-AO

07-00

iNi'

Signetics

1·35

I

I

~

MICROPROCESSOR DIVISION

JANUARY 1982

POLYNOMIAL GENERATOR CHECKER (PGC)
Table 1. GLOSSARY

SC2653
Operation Control Unit

TERM/ABBREVIATION

DEFINITION

BCC

Block check character

BTC

Block terminating character
Search character

SC

Second search character (preceded by OLE)

SSC

+ X 15 + X2 + 1 divisor, dividend pre-cleared
+ X3 + X2 + X + 1 divisor, dividend

CRC-1S

X 16

CRC-12

X12 + X"
pre-cleared

This functional block stores configuration
and operation instructions from the CPU and
generates appropriate signals to control the
device operation. It also contains read and
write circuits to permit communications between the CPU and the PGC registers via
the data bus. The mode, command, and status registers are in this logic block.

Character Register

VRC

Vertical redundancy check (character parity)

R/T

Receiver/transmitter circuit. Also known as
USART / USRT / UART / PCI/ MPCC

BISYNC

IBM binary synchronous communications (BSC),
ANSI X3.28, ISO 1745

Characters to be considered for BCC generation, parity generation and checking, or
character comparisons are loaded into this
register by either CEO or CE 1. This register
serves as an input to the BCC and VRC generator, where the accumulation and parity
generation takes place. The character register also sarves as the input for character
class array and OLE comparisons.

MSB

Most significant bit

Character Class Array

LSB

Least significant bit

This 128 x 2 array holds the character class
associated with each of 128 possible 7-bit
characters. The array is zero after a master
reset. When the character class array is
loaded (see PGC Addressing), the character on the data bus is placed in the class
specified by the contents of command register bits CR2 and CR3. The PGC uses these
two command bits to represent four different
character classes. These are:

Horizontal parity on least significant 7 bits; vertical
parity on most significant bit

LRC-8

Rx

Receive

Tx

Transmit

TYPICAL SYSTEM CONFIGURATION
nc

~

~

1. Normal class (included in the accumulation)
USART

2. SYN character/BISYNC not included
class

OR
USRT

00-07

•

4
CEO

.

R"/W

CPU

.0

I--

JF
lk

4. Second search character class (preceded by OLE)
These encoded character classes are used
by the PGC:
2653
PGC

ill

3. Block terminating character / search
class

INT

1. To control the BCC accumulation of associated characters in BISYNC modes
only. BCC accumulation in automatic or
single accumulation modes is carried out
independent of the character classes.
2. To detect characters and two character

NOTES
1 Open drain iNf may be OR tied with 2651 PCI. 266 t EPCI. or other open dram Interrupt
OUtPU1S

sequences in all rnodes of accumulation

and to set the control character detect
bits in the status register.

2 No external CirCUitry necessary If 2651 or 2661 18 the USAAT

Figure 1

It should be noted that any number of characters (up to 128 for CRC-16 or LRC-8; up to
64 for CRC-12) can be put into anyone
class.

I! VRC is specified along with CRC-16 then
the least significant 7 bits of the character
are used for character array comparison. I!
VRC is not enabled, but CRC-16 is, the MSB
of the character then determines whether a

1·36

Signe1ics

MICROPROCESSOR DIVISION

JANUARY 1982

POLYNOMIAL GENERATOR CHECKER (PGC)
character comparison is to take place. If the
MSB is 0, the comparison takes place; if the
MSB is I, the comparison does not take
place and the character is processed as
though it were in the normal class. This enables the PGC to detect all communication
control characters and OLE-SSC sequences.

SC2653

CHARACTER CLASS ARRAY COMPARISON OPERATION

1

=--=

CRC - 16

.)

Only the first 64 locations of the array are
accessed if CRC-12 is selected. The user
should right justify each six bit character
(00-05) to be written into the character
class array. Bit 6 must be zero.
If VRC is enabled, the generated parity becomes the most significant bit of the character to be compared. VRC is not allowed in
BISYNC transparent mode.
The method in which the character register
contents is compared against the character
class array depends on the BCC polynomial
chosen. Figure 2 illustrates the comparison
process.

ENABLE COMPARISON
ON LOWER 7 BITS
(06 - DO)
MSB IS IGNORED

.)

I

CRC-12

!

OLE Read Only Memory
The OLE characters are stored internally
and are selected by the error polynomial as
follows:

ENABLE COMPARISON
ON LOWER 6 BITS
(D5 - DO)

USB IS IGNORED

CRC-12: 01 1111
LCR-8 or CRC-16:
No VRC or odd VRC: 0001 0000
Even VRC 1001 0000

BIT 6 MUST BE ZERO

BCC and Parity Generator
This functional block performs all the necessary computation to generate and update
the BCC accumulation on a character by
character basis. It contains the three generator polynomials (CRC-16, CRC-12, and
LRC-a) that can be selected to compute the
BCC. This block also checks and generates
odd or even parity for 7 ·bit (ASCII) characters.

BCC Registers
This block consists of two 8-bit registers
(BCC upper and BCC lower) which contain
the high and low order bytes of the BCC
accumulation. The result of the accumulation from the BCC and parity generator is
stored in these registers. A recirculating
register address pointer is initialized by a
power on, master reset, or clear Bee com~
mand. The pointer alternately selects BCC
upper and lower on successive BCC register
accesses for CRC-16 or CRC-12. For LRC8, BCC upper is always selected.
BCC upper and lower are cleared by a clear
BCC or master reset command. The highest
term of the BCC polynomial is always represented by bit 0 of BCC upper; the lowest
term is always represented by bit 7 of BCC
lower (see figure 3, Orientation of BCC Polynomials.)

oJ

LRC-B

!
ENABlE COMPARtSQN
ON LOWER 7 BITS
(06 - DO)
MSB IS IGNORED

NOTE

Transparent mode always disables the

sse companson
Figure 2

The length of the block check character depends on the error checking polynomial that
is selected. If LRC-8 is chosen, the BCC
result is stored entirely in BCC upper. The
BCC lower remains unchanged from previous setting. Both BCC registers are used
when CRC-16 is specified. When CRC-12 is
selected, the block check character is 12
bits long. The six least significant bits of the
BCC are stored in the least significant bits
of the BCC lower. The remaining upper six
bits of the BCC are stored in least significant bits of BCC upper. The two most significant bits in each BCC register are filled with

The BCC register(s) are read by the CPU
after the last data character is transmitted.
They can then be sent to the R IT to complete a transmitted block of data. These registers are read and loaded when one PGC is
time-shared by several R ITs. Refer to Applications Information - Multiplexed PGC.

PGC Addressing
All internal registers and the character class
array are selected by the unique address
codes shown in table 2.

zero.

Signetics

1·37

JANUARV1982

MICROPROCESSOR DIVISION

5C2653

POLYNOMIAL GENERATOR CHECKER (PGe)

ORIENTATION OF

a-=

Q IX)

+-Hf-.

WHERE R IX)

=AnI" + An -

ace POLYNOMIALS
,Xn - 1-- + AoXD

II (X) • BINARY POLYNOMIAL (DATA STREAM)
G (X) FIXED DIVISOR TO GENERATE ace

ace
ace

Q (X) • QUOTIENT AFTER
O!NERATION
R (X) REMAINDER AFTER
QEfERATION

acc LOWER

accUPPER
(BBITS)

(8 BITS)

I

07 - - - - - - - - - - DO

I

I
CRC-18" X18+ x15+ X2

D7 DB

os - - - - - - -

Holtl

I

+,

D7 DB

00

os - - - - - -

1010ltl

It I

AoX0 - - - - -

D7 - - - - - - - - - - DO

"aXI - - - - - - - A1sX 1S

AoX0 - - - - - - - - A7X7

DO

)<1

AeXI - - - - AUX11

AsKS

CRC-12

= X12 +X11

+X3+X2+X+ 1

D7

D7 - - - - - - - - - - DO

Ix ----------- x I

DB - - - - - - - - DO

1·I-LRc-1

(DON'T CARE)

PARITY

+ (7~T LAC)

LAC - 8 ., HORIZONTAL PARITY ON 7 LSB

VERTICAL PARITY ON USB

RECEIVED. OR TRANSMm'ED CHARACTER BITS (TO BE INCLUDED II ace ACCUMULATION)

3

4

5

8

7

8

•

~

11 12 13 M 15

FEEDBACK DATA

OPERATION OF ICC RECJlSTER FOR CRC - 1. ace

ace

OPERATION OF
REGISTER FOR LAC
ACCUMlLATION (SIMPLIFIED)

ACCUMULATION (SN'LFEDI

Figure 3

1·38

ace

MICROPROCESSOR DIVISION

JANUARY 1982

SC2653

POLYNOMIAL GENERATOR CHECKER (PGC)
Table 2.

ADDRESS CODES

CEO

CE1

A1

AO

R/W

0
0

0
1

x

x

X

Operation not guaranteed

0

0

0

If MR2 = 0 load data bus into character register
If MR2 = 1 PGC not selected'

0

1

0

0

1

0

1

1

X

0

1

0
1

If MR2 = 1 load data bus into charactar register
If MR2 = 0 PGC not selected'
PGC not selected'

0

X

PGC not selected'

0

1

1

1

X

1
1

0

0

0

0

PGC not selected'
Read character register

0

0

0

1

Load data bus into character register if MR 1,0
002 ; write character class array using CR3,
CR2 class code if MR 1,0 = 003 .•

1

0
0

0

1
1

1

0

0
1

0
1

Read Status register

1

0

Read mode register

1

into the character register when in receive
mode (MR2 = 0 and R IW = 0) while
CPU I DMA characters are loaded into the
character register when in transmit mode
1 and R/W
1). The time between
(MR2
consecutive chip enables is given by tCEC
or tCED.

FUNCTION

=

The open drain active low interrupt signal
(lNT) goes active whenever one or more of
four maskabla status conditions (SRO-SR3)
are true (= 1). A status read deactivates
INT.
The same techniques used in interfacing the
2651 PCI to 8-bit microprocessors can be
used to interface the 2653 PGC (consult Application Note M22). Note that when addressing the R IT's holding registers, the
PGC pins must have A I,AO = 00 and that the
address and R I W signals must be stable
(set up) prior to the active low chip enable.
When using the 2651 or 2661 as the R/T,
the PGC's A I, AO, R/W, and CEO are directly connected to comparable 2651 or 2661
signals. Schematics of a 2653 monitoring
data transfers to I from the Signetics
285112661 and 2652 are shown in figures 4
and 5.

*

Write command register

1

0

1

0
0

1
1

0
0

1
1

1
1

0
1

Write mode register
Read sec upper I lowers
Write BCC upper I lowers

1

1

X

X

X

PGC not selected'

NOTES
1
2
3.
4

Data bus 18 a-state
Character wUI not be accumulated unless MR3 ... 1
Character will not be accumulated aven If MR3
1
The mode bits MRl and MAO are cleared to 00 by power-on-reset, master reset, or by
loading the mode register bits MRl and MRO

=

An alternate interfacing techniqua is to traat
the PGC as an independent peripheral device. This necessitates a write character
registar instruction aftar the CPU reads or
writes a character to or from the R/T.

5 Recirculating IOlemal pOinter selects BCe Upper on first access, BCe towaro" next
access for all BCCs except for LRC-8; in case of LRC·B, the pointer only selects BCe
upper.

INTERFACE SIGNALS AND TIMING
PGC data transfers ara controlled by A I, AO,
and R/W which must be stable prior to the
active low going chip enable pulse. CEO is
used for PGC monitoring of data transfars
between a CPU/DMA controller and a R/T;
is used for direct CPU-to-PGC transfers. MR3 must be set prior to loading the
character register in order to accumulate or
compare characters via CE 1. The active low
(leading) edge of chip enable initiates a
PGC read/write cycle; the rising (trailing)
edge ends the cycle and also serves as a
write strobe.

2651 OR 2661/2653 INTERFACE

D~nM~TS

-en

R

+5V
'fiJiI)Y,

RxJii5V, 'f'infI'!D§CHG

------

087 - DBO

fi!w,

~
A1, AO

-

~

2651/61
PC'

R,D

---

~
r==--

CPU

When loading the character, mode, or command register, the data bus is strobed into
the selected register on the trailing (rising)
edge of the appropriate CEo When writing
into the character class array, the data on
the bus (the special character) Is placed in
the class specified by command register
bits CR3 and CR2.
Characters are transferred into the character register when CEO is active (low) depending on the state of MR2 and the R/W
input. Characters from the R/T are loaded

=

~
2853

m

PGC

ffi

t

1

lilT

R

+5V

Figure 4

Signetics

1·39

1

JANUARY 1982

MICROPROCESSOR DIVISION

SC2653

POLYNOMIAL GENERATOR CHECKER (PGC)

register for BCC accumulation, VRC
generation/checking, BTC/SC and OLESSC comparisons, See table 3 for a summary of BCC accumulation modes.

2652/2653 INTERFACE
TYPICAL PROTOCOLS: BISYNC, DDCMP, SDLC, HDLC
TxBE TxU RxDA RxSA

INTERRUPTS

D

BCC accumulation depends on the mode selected.

II

087 - DBD

2652

- - . . TxD

MPCC

_R,O

A2
A1
AD

_TxC

R/W
~RxC

DBEN

080.BO

CE
CPU

4

CEO

A1

2653
PGC

R/W
AO
CE1

i

iN'f

Figure 5

PGC PROGRAMMING
The PGC operational mode must be initially
programmed by the CPU (see figure 6). The
mode register, command register and character class array should be written into,
alter a power-on-reset or a master reset
command. The character class array should
be programmed only for the classes pertinent to the application. After a master reset,
the character class array is zero which

1

(OPEN DRAIN}

I

+sv

places all characters in the normal class
(included in the BCC accumulation).

OPERATION
The PGC should be initially configured by
the CPU (via CE I) prior to systems operation. This is done by loading the mode register, command register and character class
array (see PGC PROGRAMMING). Characters may then be loaded into the character

BISYNC Normal
In BISYNC normal mode, all characters loaded into the character register are accumulated except those in the SYN / BISYNC not
included class. During receive (MR2 = 0), a
BTC / SC match will cause the BCC accumulation to stop alter the next one (LRC-8) or
two (CRC-12 or CRC-16) characters have
been accumulated. At that time, if the BCC
accumulation does not equal zero, the BCC
error bit (SRO) will be sel and INT will go
active ilthe corresponding mask bit (CR4) IS
enabled (= I). In transmit (MR2 = I), the
BCC accumulation is automatically stopped
once the BTC / SC character has been accumulated. The CPU must read the BCC upper
and BCC lower (CRC-12 or CRC-16) registeres) and transmit them to the R / T.
Note that the received BCCs are not subject
to VRC if CRC-16 is selected. If LRC-8 is
selected, the received BCC is subject to
VRC. An incorrect result will set the VRC
error bit (SR I). After its accumulation, the
least significant 7 bits of BCC upper are
checked and a non-zero result will set the
BCC error bit (SRO). BCCs are not checked
against the character class array nor are
they compared to the OLE ROM.
Second search character (SSC) detection
is enabled so that a OLE-STX or two character communication control sequence can be
detected.

Table 3_ SUMMARY OF BCC ACCUMULATION MODES
ACCUMULATION
MODES
BISYNC normal and
BISYNC transparent

START
ACCUMULATION

STOP
ACCUMULATION

CHARACTERS EXCLUDED
FROM ACCUMULATION

Clear BCC registers command

After BTC has been detected
and received BCC is
accumulated

SYN/BISYNC not included
class in normal mode

Mode register is loaded with
BISYNC or automatic mode

OLE-SYN / not Included class
and first OLE of a OLE non SYN
pair in transparent mode
These characters are not excluded If preceded by an odd
number of OLEs

Start accumulation command

After transmitted BTC has been
accumulated

Load BCC registers

Single mode is selected

Automatic

Same as above

Single mode selected

None

Single

Start accumulation command

After each character has been
accumulated

Up to user who must generate
start accumulation command
for each character to be included

1·40

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SC2653

POLYNOMIAL GENERATOR CHECKER (PGC)

are accumulated (depending on LRC-B or

PGC PROGRAMMING

CRC-12/16, respectively) and the PGC will

automatically stop further accumulation.
However, the PGC can continue the
accumulation if a start accumulate command is issued or either BISYNC mode is
loaded into the mode register. The start accumulate command should be given to the
PGC before loading the character that follows the detected BTC I SC. This procedure
enables a special search character to be
detected (the BTC I SC detect bit (SR2) will
be set and an interrupt generated if CR6 =
1) with the BCC accumulation continuing
(see figures 7 and B).

Automatic Accumulate
All characters loaded into the character
register are accumulated, BTCI SC and SSC
detection is enabled. The BCC accumulation
is not automatically terminated. (The CPU
must use single accumulate mode to stop
the accumulation). When in receive mode,
the BCC error bit (SRO) is sell reset after
accumulating each character so that the
CPU must examine this bit after the last
character is accumulated. SRO = 0 if the
accumulated remainder in the BCC register(s) is zero; otherwise SRO = 1. Examples
of use of automatic accumulate mode usage
include an R/T (265112661) in transparent
OLE/SYN strip mode and asynchronous I synchronous I parallel ODCMP.

Single Accumulate

(

All characters for which a start accumulate
command (CR I, CRO = 01) is given are accumulated and compared against the character class array. If not given, the BCC accumulation is not updated and BTC I SC and
SSC detection is disabled. Operation in this
mode is otherwise identical to automatic accumulate.

OPERATE)

Figure 6

BISYNC Transparent
BISYNC transparent mode should be used
for data blocks beginning with OLE-STX if
the OLEs are transferred between CPU and
R IT (CEO) or CPU and PGC (CE I), i.e., OLEs
are not stripped. VRC should be disabled in
this mode. Characters excluded from the
BCC accumulation are the first OLE of a
OLE-non SYN sequence pair and the OLESYN sequence if not preceded by an odd
number of OLEs. For example, consider the
following transparent mode character string:

OLE

exclude

OLE SYN

T

include
both

OLE OLE

/

exclude

\

include

In receive and transmit modes, the termination of BCC accumulation works exactly as
in BISYNC normal, except that the BTC I SC
must be immediately preceded by an odd
number of OLEs to be identified as a
BTC/SC.
Second search character detection is not
enabled in BISYNC transparent.
After a BTCI SC class character is detected
by the PGC when receiving in either BISYNC
mode, the following one or two characters

--t
OLE SYN

OLE

ETX

exclude
both

exclude

include

Signe1ics

Single accumulate mode can be used to selectively accumulate characters under CPU
control or to accumulate characters that
were unintentionally excluded in one of the
other modes.

Polynomial Selection and OLE
Comparison

The sec polynomial may be CRC-16, CRC12 or LRC-B. The cyclic redundancy check
(CRC) is generated by dividing the binary
value of a character in the character register by the selected polynomial. The quotient
is discarded and the remainder is used as
the BCC (two 6-bit characters for CRC-12,
two B-bit characters for CRC-16). CRC-,16
uses all B bits of each BCC register. CRC-12
uses the least significant 6 bitS of the BCC
registers. The two most significant bits of
the BCC registers are cleared to zero whenever CRC-12 is selected (see figure 3).

1·41

=
--i-=

JANUARY 1982

MICROPROCESSOR DIVISION

SC2653

POLYNOMIAL GENERATOR CHECKER (PGC)
acc ACCUMULATION

EXAMPLES - BISYNC TEXT MESSAGE
SHADED AREAS ACCUMULATED
Ax '" RECEIVE MODE

CHARACTER CLASS ARRAY
SYN/BISYNC NOT INCLUDED 5YH, SOH
BTC/SC ETX, ETB, ITB, ENQ

NO OLE/SYN STAFPING

sse

STX

CRC-16ORCRC-12

syo

SYN

SOH

I "' __

STXI _ _ _ "'!!"ETX!

laccJaccl I
PAD

+
ace ERROR (Rx) IF
ACCI.IUU1.ATlON *" 0
ACCUMlA.A1lON STOPPED

BTC

DETECT

acc

AFTER 2ND
NO
PARITY CtEeK ON aces
LRC-8

SVO

SYN

svo

ISTxi "'-~::e

CPU RESETS

SVO

E11!

l

l,apcl.1
+

+

ace

ace ERROR (Ax) IF 7 LS BITS

aTC
DETECT

REGISTERS AFTER
SOFTWARE DETECT

PAD

OF BCCu

*" 0

VAC ERROR IF

MS 1fT IS INCORRECT PARITY
ACClMJLATION STOPPED AFTER
1

OF STX 11IS

ace

EFFECTIVELY
EXCLUDES 8TX

BLOCK 1

----srx.t----ITBJ
OPTIONAL

BTC

DETECT

sse

arc

DETECT

DETECT

PDSSIBLE

ace ERROR

SETBlSVNC
TR........NT

POSSIILE ace ERROR

(F so RESET ace
REGISTERS)
RESET
REGISTERS OR
"SET BISYNC NORMAL

ace

sse

arc

DETECT
SET BISYNC
TRANSPARENT
MOOE

DETECT

POSSIBLE

ace ERROR

~1.~-------------------------BL~1--------------------------.'~I.~-----BL~K2~

sse

BTC
DETECT

DETECT
lEY BISYNC
TRANSPARENT AND
RESET

RESET

ace REGISTERS

NOTES
1.
.rror on/yfor receIVe mode In transmit moda, CPU must respond to BTC detect by
reading the BCC regl8ter(s) and sending them to the R IT The accumulatIOn IS stopped
after the BTC 18 accumulated
2. ENQ (OLE-ENQ) In a text measage should be treated as an abort
3. Opening SYNa may be stripped by the R IT
4 The alngle accumulate mode and command can be used to accumulate a character that
Inadvertently wa. excluded (For example, the OLE of a OLE-STX If the PGe was 1ft
transparent mode and there was not a hne turnaround pnor to the OLE) The Single
accumulation should be done uSing CET after the BCC----+

~

(16)

TRANSMIT DATA
HOLDING REGISTER

rBAUD RATE
GENERATOR
AND
CLOCK CONTROL

(22)

(17)

DTR

•

(9)

Tie/SYNC

(15)

TRANSMITTER

MODEM
CONTROL

(24)

~

RECEIVE
SHIFT REGISTER

(18)

DSCHG

I
I

-(3)

R,D

...£!L-

Vcc

~

OND

NOTE

*Open drain output pin
BLOCK DIAGRAM
The EPCI consists of six major sections.
These are the transmitter, receiver, timing,
operation control, modem control and
SYN I DLE control. These sections communicate with each other via an internal data bus
and an internal control bus. The internal data
bus interfaces to the microprocessor data
bus via a data bus buffer.

Operation Control
This functional block stores configuration
and operation commands from the CPU and
generates appropriate signals to various internal sections to control the overall device
operation. It contains read and write circuits
to permit communications with the
microprocessor via the data bus and contains mode registers 1 and 2, the command
register, and the status register. Details of
register addressing and protocol are presented in the EPCI programming section of
this data sheet.

Table 1 BAUD RATE GENERATOR CHARACTERISTICS
SC2661A (BRCLK = 4.9152MHz)

MR23-20

BAUD
RATE

ACTUAL
FREQUENCY
16XCLOCK

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200

0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2

Signefics

PERCENT
ERROR

-0.Q1

0.196

-0.19
-0.26

-

-

DIVISOR
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16

1-53

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
Timing
The EPCI contains a baud rate generator
(BRG) which is programmable to accept external transmit or receive clocks or to divide
an external clock to perform data communications. The unit can generate 16 commonly
used baud rates, anyone of which can be
selected for fuli duplex operation. See
table 1.

Receiver
The receiver accepts serial data on the RxO
pin, converts this serial input to parallel format, checks for bits or characters that are
unique to the communication technique and
sends an "assembled" character to the
CPU.

Transmitter
The transmitter accepts parallel data from
the CPU, converts it to a serial bit stream,
inserts the appropriate characters or bits
(based on the communication technique)
and outputs a composite serial stream of
data on the TxO output pin.

Table 1 BAUD RATE GENERATOR CHRACTERISTICS
SC2661 B (BRCLK = 4.9152MHz)

MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

SYN/DLE Control
This section contains control circuitry and
three 8-bit registers storing the SYN I,
SYN2, and OLE characters provided by the
CPU. These registers are used in the synchronous mode of operation to provide the
characters required for synchronization, idle
fill and data transparency.

ACTUAL
FREQUENCY
16XCLOCK

45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400

0.7279kHz
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4

PERCENT
ERROR
0.005

DIVISOR

-

6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8

PERCENT
ERROR

DIVISOR

-0.01

-

-

-0.19
-0.26

-

-

MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

BAUD
RATE

ACTUAL
FREQUENCY
16XCLOCK

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

0.8kHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8

-

-

0.016

-

-

0.253

3.125

NOTE
l6X clock 18 used In asynchronous mode In synchronous mode, clock multIplier IS 1X and
BRG can be used only for TxC

1·54

(Cont'd)

SC2661C (BRCLK = 5.0688MHz)

Modem Control
The modem control section provides interfacing for three input signals and three output signals used for "handshaking" and status indication between the CPU and a
modem.

BAUD
RATE

SC2661

Signe1ics

6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
Table 2

CPU-RELATED SIGNALS

OPERATION

PIN NO.

INPUTI
OUTPUT

VCC

26

I

+5V supply input

GND
RESET

4
21

I
I

Ground
A high on this input performs a master
reset on the 2661. This signal asynchro·
nously terminates any device activity and
clears the mode, command and status reg·
isters. The device assumes the idle state
and remains there until initializad with the
appropriate control words.
Address lines usad to select internal EPCI
regIsters.
Read command when low, write command
when high.

PIN NAME

10,12

I

R/W

13

I

CE

11

I

Al- AO

Dr Do

8,7,6,5,
2,1,28,17

1/0

TxRDY

15

0

RxRDY

14

0

TxEMTI
DSCHG

18

0

SC2661

FUNCTION

Chip enable command. When low, indicates that control and data lines to the
EPCI are valid and that the operation
specilied by the R/W, AI and AO inputs
should be performed. When high, places
tha DO-D7 lines in the three-state condition.
8-bit, three-state data bus used to transler
commands, data and status between EPCI
and the CPU. DO is the least signilicant bit;
D7 the most signilicant bit.
This output is the complement 01 status
register bit SRO. When low, it indicates
that the trensmit data holding register
(THR) is ready to accept a data character
Irom the CPU. It goes high when the data
character is loaded. This output is valid
only when the transmitter is enabled. It is
an open drain output which can be used 8S
an Interrupt to the CPU.
This output is the complement 01 status
register bit SR 1. When low, it indicates
that the receive data holding register
(RHR) has a character ready lor input to
the CPU. It goes high when the RHR is read
by the CPU. and also when the receiver is
disabled. It is an open drain output which
can be used as an interrupt to the CPU.
This output is the complement 01 status
register bit SR2. When low, it indicates
that the transmitter has completed serialization 01 the last character loaded by the
CPU, or that a change of state 01 the DSR
or DCD inputs has occurred. This output
goes high when the status register is read
by the CPU, il the TxEMT condition does
not exist. Otherwise, the THR must be
loaded by the CPU lor this line to go high. It
is an open drain output which can be used
as an interrupt to the CPU.

The lunctional operation 01 the 2661 is pro·
grammed by a set 01 control words supplied
by the CPU. These control words specify
items such as synchronous or asynchronous
mode, baud rste, number 01 bits per character, etc. The programming procedure is de·
scribed in the EPCI programming section 01
the data sheet.
Alter programming, the EPCI is ready to perlorm the desired communications lunctions.
The receiver performs serial to parallel conversion 01 data received Irom a modem or
equivalent device. The transmitter converts
parallel data received from the CPU to a
serial bit stream. These actions are accomplishad within the Iramework specilied by
the control words.

Receiver
The 2661 is conditioned to receive data
when the DCD Input Is low and the RxEN bit
in tha command register is true. In the asynchronous mode, the receiver looks lor a high
to low (mark to space) transition 01 the start
bit on the RxD Input line. II a transition is
detected, the state 01 the RxD line Is sam·
pled again after a delay 01 one-hall of a bit
time. If RxD is now high, the aearch lor a
valid atart bit is begun again. II RxD Is still
low, a valid start bit Is assumed and the
receiver continues to ssmple the input line
at one bit time Intervals until the proper num·
ber 01 data bits, the parity bit, and one stop
bit have been assembled. The data are then
translerred to the receive data holding reg·
ister, the RxRDY bit in the status register is
set, and the RxRDY output is asserted. If the
character length is less than 8 bita, the high
order unused bits In the holding regiater are
set to zero. The parity error, Iramlng error,
and overrun error status bits are strobed
Into the atatus register on the positive going
edge 01 RiC correaponding to the received
character boundary. II the stop bit is
present, the receiver will immediately begin
its search lor the next atart bit. If the stop bit
is absent (Iraming error), the receiver will
interpret a space aa a atart bit il it peralsta
Into the next bit time Interval. II a break condition ia detected (RxD is low for the entire
character as well aa the atop bit), only one
character conaisting 01 all zeros (with the
FE status bit SR5 set) will be transferred to
the holding register. The RxD Input must return to a high condition before a search lor
the next start bit begins.
Pin 25 can be programmed to be a break
detect output by appropriate setting 01
MR27-MR24. II so, a detected break will
cauae that pin to go high. When RxD returns
to mark lor one RxC time, pin 25 will go low.
ReIer to the break detection timing diagram.

1·55

-------_.-

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
Table 3

DEVICE-RELATED SIGNALS
INPUT/

PIN NAME

PIN NO.

OUTPUT

FUNCTION

BRCLK

20

I

Clock input to the internal baud rate generator (see teble 1). Not required if external
receiver and transmiller clocks are used.

'RxC/BKDET

25

I/O

Receiver clock. If external receiver clock
is programmed, this Input controls the rate
at which the character is to be received.
Its frequency is IX, 16X or 64X the baud
rate, as programmed by mode register 1.
Data are sampled on the rising edge of the
clock. If internal receiver clock is programmed, this pin can be a lX/16X clock
or a break detect output pin.

'TxC/XSYNC

9

I/O

Transmiller clock. If external transmiller
clock is programmed, this input controls
the rate at which the character is transmitted. Its frequency is IX, 16X or 64X the
baud rate, as programmed by mode register 1. The transmilled data changes on the
falling edge of the clock. If internal transmiller clock is programmed, this pin can
be a lX/16X clock output or an external
jam synchronization input.

RxD

3

I

Serial data input to the receiver. "Mark" IS
high, "space n is low.

TxD

19

0

Serial data output from the transmiller.
"Mark" is high, "space" is low. Held in
mark condition when the transmiller is disabled.

DSR

22

I

General purpose input which can be used
for data set ready or ring indicator condition. Its complement appears as status
register bit SR7. Causes a low output on
TxEMT/DSCHG when its state changes if
CR2 or CRO = 1.

DCD

16

I

Data carrier detect input. Must be low In
order for the receiver to operate. Its complement appears as status register bit
SR6. Causes a low output on
TxEMT /DSCHG when its state changes if
CR2 or CRO = 1. If DCD goes high while
receiving, the RxC is internally Inhibited.

CTS

17

I

Clear to send input. Must be low in order
for the transmiller to operate. If it goes
high during transmission, the character in
the transmit shift register will be transmitted before termination.
General purpose output which is the complement of command register bit CR 1. Normally used to indicate data terminal ready.

DTR

24

0

"R'rn

23

0

General purpose output which is the complement of command register bit CR5. Normally used to indicate request to send. If
the transmit shift register is not empty
when CR5 is reset (1 to 0), then RTS will
go high one TxC time after the last serial
bit is transmilled.

NOTE

•J!!iiC and ~ outputa have &hort circuli protection max. CL - 100pF Outputs become
open olreutted upon detection of • zero pulled hlgh or a one pulled low.

1·56

Signetics

SC2661

When the EPCI is initialized into the synchronous mode, the receiver first enters the hunt
mode on a 0 to 1 tranSition of RxEN(CR2). In
this mode, as data are shifted into the receiver shift register a bit at a time, the contents of the register are compared to the
contents of the SYN 1 register If the two are
not equal, the next bit is shifted in and the
comparison IS repeated. When the two regIsters match, the hunt mode IS terminated
and character assembly mode begins If Single SYN operation is programmed, the SYN
DETECT status bit is set. If double SYN operation is programmed, the first character
assembled after SYN 1 must be SYN2 in order for the SYN DETECT bit to be set. Otherwise, the EPCI returns to the hunt mode.
(Note that the sequence SYN I-SYN I-SYN2
will not achieve synchronization.) When synchronization has been achieved, the EPCI
continues to assemble characters and
transfer them to the holding register, setting
the RxRDY status bit and asserting the
RxRDY output each time a character is
transferred. The PE and OE status bits are
set as appropriate. Further receipt of the
appropriate SYN sequence sets the SYN
DETECT status bit. If the SYN stripping
mode is commanded, SYN characters are
not transferred to the holding register. Note
that the SYN characters used to establish
initial synchronization are not transferred to
the holding register In any case.
External jam synchronization can be
achieved via pin 9 by appropriate seiling of
MR27-MR24. When pin 9 is an XSYNC Input,
the internal SYN I, SYN I-SYN2, and DLESYN 1 detection is disabled Each positive
going signal on XSYNC will cause the receiver to establish synchronization on the
rising edge of the next RxC pulse. Character
assembly will start with the RxD input at thiS
edge. XSYNC may be lowered on the next
rising edge of RxC. This external synchronization will cause the SYN DETECT status bit
to be set until the status register is read.
Refer to XSYNC timing diagram.

Transmitter
The EPCI is conditioned to transmit data
when the CTS input is low and the TxEN
command register bit is set. The 2661 indicates to the CPU that it can accept a character for transmission by seiling the TxRDY
status bit and asserting the TxRDY output
When the CPU writes a character into the
transmit data holding register, these conditions are negated. Data are transferred from
the holding register to the transmit shift register when it is idle or has completed transmission of the previous character. The
TxRDY conditions are then asserted again
Thus, one full character time of buffering is
provided .

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

In the asynchronous mode, the transmitter
automatically sends a start bit followed by
the programmed number of data bits, the
least significant bit being sent first. It then
appends an optional odd or even parity bit
and the programmed number of stop bits. If,
following transmission of the data bits, a
new character is not available in the transmit holding register, the TxO output remains
in the marking (high) condition and the
TxEMT I OSCHG output and its corresponding status bit are asserted. Transmission
resumes when the CPU loads a new character into the holding register. The transmitter
can be forced to output a continuous low
(BREAK) condition by setting the send
break command bit (CR3) high.

Table 4
CE
1
0
0
0
0
0
0
0
0

SC2661

2661 REGISTER ADDRESSING
A1
X

X

X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1

FUNCTION

R/W

AO

Three-state data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN 1I SYN2 IDLE registers
Read mode registers %
Write mode registers %
Read command register
Write command register

NOTE
See AC characteristIcs section for tlmmg reqUirements

2661 INITIALIZATION FLOW CHART
INITIAL RESET

In the synchronous mode, when the 2661 is
initially conditioned to transmit, the TxO output remains high and the TxROY condition is
asserted until the first character to be transmitted (usually a SYN character) is loaded
by the CPU. Subsequent to this, a continuo
ous stream of characters is transmitted. No
extra bits (other than parity, if commanded)
are generated by the EPCI unless the CPU
fails to send a new character to the EPCI by
the time the transmitter has completed
sending the previous character. Since synchronous communication does not allow
gaps between characters, the EPCI asserts
TxEMT and automatically "fills" the gap by
transmitting SYN 1s, SYN I-SYN2 doublets,
or OLE-SYN 1 doublets, depending on the
state of MR 16 and MR 17. Normal transmission of the message resumes when a new
character is available in the transmit data
holding register. If the SEND OLE bit in the
command register is true, the OLE character
IS automatically transmitted prior to transmission of the message character in the
THR.

NOTE
Mode register 1 must be wntten

before 2 can be wntten Mode register 2
need not be programmed If external
clocks are used

NOTE
SYNI regIster must be wntten

EPCI PROGRAMMING
Prior to initiating data communications, the
2661 operational mode must be programmed by performing write operations to
the mode and command registers. In addition, if synchronous operation is programmed, the appropriate SYN IDLE registers must be loaded. The EPCI can be
reconfigured at any time during program execution. A flowchart of the intialization process appears in figure 1.
The internal registers of the EPCI are
accessed by applying specific signals to the
CE, R/W, AI and AO inputs. The conditions
necessary to address each register are
shown in table 4.
The SYN1, SYN2, and OLE registers are
accessed by performing write operations
with the conditions AI = 0, AO = 1, and

Figure 1

Signe1ics

1·57

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
R/W = 1. The first operation loads the
SYN 1 register. The next loads the SYN2
register, and the third loads the OLE regis·
ter. Reading or loading the mode registers is
done in a similar manner. The first write (or
read) operation addresses mode register 1,
and a subsequent operation addresses
mode register 2. If more than the required
number of accesses are made, the internal
sequencer recycles to point at the first reg·
ister. The pOinters are reset to SYN 1 regis'
ter and mode register 1 by a RESET input or
by performing a read command register op·
eration, but are unaffected by any other read
or write operation.
The 2661 register formats are summarized
in tables 5, 6, 7 and 8. Mode registers 1 and
2 define the general operational character·
istics of the EPCI, while the command regis·
ter controls the operation within this basic
framework. The EPCI indicates its status in
the status register. These registers are
cleared when a RESET input is applied.

Mode Register 1 (MR1)
Table 5 illustrates Mode Register 1. Bits
MR 11 and MR 10 select the communication
format and baud rate multiplier. 00 specifies
synchronous mode and IX multiplier. IX,
16X, and 64X multipliers are programmable
for asynchronous format. However, the mul·
tiplier in asynchronous format applies only if
the external clock input option is selected
by MR24 or MR25.
MR 13 and MR 12 select a character length
of 5, 6, 7 or 8 bits. The character length
does not include the parity bit, if pro·
grammed, and does not include the start and

stop bits in asynchronous mode.
MR 14 controls parity generation. If enabled,
a parity bit is added to the transmitted char·

Table 5

acter and the receiver performs a parity
check on incoming data. MR 15 selects odd
or even parity when parity is enabled by
MRI4.

To effect assembly / disassembly of the next
received Itransmitted character, MR 12·15
must be changed within n bit times of the
active gOing state of RxROY /TxROY. Trans·
parent and non·transparent mode changes
(MR 16) must occur within n·l bitlimes of the
character to be affected when the receiver
or transmitter is active. (n = smaller of the
new and old character lengths.)

In asynchronous mode, MR17 and MR16 se·
lect character framing of 1, 1.5, or 2 stop
bits. (If IX baud rate is programmed, 1.5
stop bits defaults to 1 stop bits on transmit.)
In synchronous mode, MR 17 controls the
number of SYN characters used to establish
synchronization and for character fill when
the transmitter is idle. SYN 1 alone is used if
MR 17 = 1, and SYN I·SYN2 is used when
MR 17 = O. If the transparent mode is speci·
fied by MR 16, OLE·SYN 1 is used for charac·
ter fill and SYN detect, but the normal syn·
chronization sequence is used to establish
character sync. When transmitting, a OLE
character in the transmit holding register will
cause a second OLE character to be trans·
mitted. This OLE stuffing eliminates the soft·
ware OLE compare and stuff on each trans·
parent mode data character. If the send OLE
command (CR3) is active when a OLE is
loaded into THR, only one additional OLE will
be transmitted. Also, OLE stripping and OLE
detect (with MR 14 = 0) are enabled.

Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23,
MR22, MR21 and MR20 control the frequen·
cy of the internal baud rate generator (BRG).
Sixteen rates are selectable for each EPCI
version (-1, -2, -3). Version 1 and 2 speci·
fy a 4.9152 MHz TTL input at BRCLK (pin
20); version 3 specifies a 5.0688 MHz input
which is identical to the Signetics 2651.
MR23·20 are don't cares if external clocks
are selected (MR25·MR24 = 0). The individ·
ual rates are given in table 1.
MR24·MR27 select the receive and transmit
clock source (either the BRG or an external
input) and the function at pins 9 and 25. Re·
fer to table 6.

Command Register (CR)

The bits in the mode register affecting char·
acter assembly and disassembly (MR 12·
MRI6) can be changed dynamically (during
active receive/transmit operation). The
character mode register affects both the
transmitter and receiver; therefore in syn
chronous mode, changes should be made
only in half duplex mode (RxEN = 1 or
TxEN = 1, but not both simultaneously = 1).
In asynchronous mode, character changes
should be made when RxEN and TxEN=O or
when TxEN = 1 and the transmitter is mark·
ing in half duplex mode (RxEN = 0).

Table 7 illustrates the command register.
Bits CRO (TxEN) and CR2 (RxEN) enable or
disable the transmitter and receiver respec·
tively. A 0 to 1 transition of CR2 forces start
bit search (aaync mode) or hunt mode (sync
mode) on the second RxC rising edge. Dis·
abling the receiver causes RxROY to go
high (inactive). If the transmitter is disabled,
it will complete the transmission of the char·
acter in the transmit shift register (if any)
prior to terminating operation. The TxO out·
put will then remain in the marking state

w

MODE REGISTER 1 (MR 1)

MR17

MR16

Sync/Async
Async: Stop Bit Length
00 = Invalid
01 = 1 stop bit
10 = 1% stop bits
11 = 2 stop bits
Sync:
Number of
SYN char
0= Double
SYN
1 = Single
SYN

MR14

MR15
Parity Type
0= Odd
1 = Even

Parity Control
0= Disabled
1 = Enabled

Sync:
Transparency
Control
0= Normal
1 = Transparent

NOTE
Baud rate factor.n asynchronous applies only If external clock IS selected Factor IS l6X If
Internal clock 18 selected Mode must be selected (MRll, MR10) 10 any case

1·58

SC2661

Signetics

MR13

MR12

MRll

Character
Length
00
01
10
11

=
=
=
=

5
6
7
8

bits
bits
bits
bits

MR10

Mode and Baud
Rate Factor
00
01
10
11

=
=
=
=

Synchronous 1X rate
Asynchronous 1X rate
Asynchronous 16X rate
Asynchronous 64X rate

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

j'

SC2661

!

I
Table 6

MODE REGISTER 2 (MR2)
MR27-MR24

0000
0001
0010
0011
0100
0101
0110
0111

TxC

RxC

Pin 9

Pin 25

E
E
I
I
E
E
I
I

E
I
E
I
E
I
E
I

TxC
TxC
IX
IX
TxC
TxC

RxC
IX
RxC
IX
RxC
16X
RxC
16X

lex
lex

MR23-MR20

TxC

RxC

Pin 9

Pin 25

Mode

E
E
I
I
E
E
I
I

E
I
E
I
E
I
E
I

XSYNC'
TxC
XSYNC'
IX
XSYNC'
TxC
XSYNC'

RxC/TxC
BKOET
RxC
BKOET
RxC/TxC
BKOET
RxC
BKOET

sync
async
sync
async
sync
asyne
sync
async

1000
1001
1010
1011
1100
1101
1110
1111

lex

Baud Rate Selection

See baud rates in table 1

NOTES
1 When pin 9 i8 programmed 88 XSVNC Input. SYN 1, SVN 1 SYN2, and DLE-SYN 1 detection i8 disabled.
E .. External clock
I
Internal clock (BRG)
1X and l6X are clock outputs
4

=

Table 7

COMMAND REGISTER (CR)

CR7

CR6

Operating Mode
00 - Normal operation
01 = Async:
Automatic
echo mode
Sync: SYN and t or
OLE stripping mode
10 = Local loop baok
11 = Remote loop baok

CR5

CR4

Request
To Send

R••et Error

0- Force RTS
oulput high
one clock time
after TxSR
serialization
1 =- Force RTS
ou,put low

0= Normal
1 = Reset
error flags
in status register
(FE. OE. PEtOLE
detect)

CR3

CR2

Sync/Async

Receive
Control
(RxEN)

Aaync:
Force break
0= Normal
1 = Force break

0= Disable
1 = Enable

CRI

CRO

Data Terminal
Ready

Transmit
Control
ITxEN)

0= Force OTR
output high
1 = Force OTR
output low

0= Disable
1

= Enable

Sync:
Send OLE
0= Normal
1 = Send OLE

Table 8

STATUS REGISTER (SR)

SR7

SR6

Data Set
Ready

Data Carrier
Detect

0= oSR input
is high
1 = 'i5S'R Input
IS low

0= oCD input
IS high
1 = OCO ,"put
IS low

SR5
FE/SYN Detect

Async:
0= Normal
1 = Framing
Error

Sync:
0= Normal
1 = SYN
detected

(high) while TxROY and TxEMT will go high
(inactive). If the receiver is disabled. it will
terminate operation immediately. Any character being assembled will be neglected. A
o to 1 transition of CR2 will initiate start bit
search (async) or hunt mode (sync).
Bits CR 1 (OTR) and CR5 (RTS) control the
OTR and RfS outputs. Data at the outputs
are the logical complement of the register
data.

SR3

SR2

SR1

SRO

PE IDLE Detect

TxEMT IDSCHG

RxROY

TxRDY

0= Normal
1 = Change In
DSR, or DCO,or
transmit shift
register is
empty

0= Receive
holding
register empty
1 = Receive
holdmg register
has data

0= Transmit
holding
register busy
1 = Transmit
holding register
empty

SR4
Overrun
0= Normal
1 = Overrun
Error

Async:
0= Normal
1 = Parity error

Sync:
0= Normal
1 = Panty error or
OLE received

In asynchronous mode, selling CR3 will
force and hold the TxO output low (spacing
condition) at the end of the current transmitted character. Normal operation resumes
when CR3 is cleared. The TxO line will go
high for at least one bit time before begin·
ning transmission of the next character in
the transmit data Ilolding register. In syn·
chronous mode, setting CR3 causes the
transmission of the OLE register contents
prior to sending the character in the transmit

Signetics

data holding register. Since this is a one
time command. CR3 does not have to be
reset by software. CR3 should be set when
entering and exiting transparent mode and
for all OLE-non-OLE character sequences.

Setting CR4 causes the error flags in the
status register (SR3, SR4. and SR5) to be
Cleared. This is a one time command. There
is no internal latch for this bit.

1·59

T

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
Table 9

SC2661 EPCI vs SC2651 PCI

FEATURE

SR3 0 for OLE-OLE,
OLE-SYNC 1

1 for OLE-OLE,
SR3
OLE-SYNC 1

3. Reset of SR3, OLE
detect

Second character after
OLE, or receiver disable,
orCR4
1
One time command

Receiver disable, or CR4

Automatic OLE stuffing when
OLE is loaded except if
CR3
1
All SYNCI

None

First SYNC 1 of pair

7. Baud rate
versions

Three

One

8. Terminate ASYNC
transmission
(drop RTS)

Reset CR5 in response to
TxROY changing from 1 to 0

5. OLE stuffing .n
transparent mode
6. SYNC 1 stripping
in double sync
non-transparent
mode

Note that automatic stripping mode does not
affect the setting of the OLE detect and SYN
detect status bits (SR3 and SR5).

Not used

Control pin 9, 25

4. Send OLE-CR3

only the first OLE of a OLE-OLE pair is
stripped.

PCI

EPCI

1. MR2 Bit 6, 7
2. OLE detect-SR3

=

=

=1

=

Reset via CR3 on next TxROY

=

Pin 25'

Reset CRO when TxEMT
goes from 1 to O. Then reset
CR5 when TxEMT goes from
o to 1
FE and null character

to. Stop bit searched
11. External jam sync

Dna
Pin g2

No

12. Data bus timing

Improved over 2651

-

13. Data bus drivers

Sink 2.2mA

Sink 1.6mA

Source 4001LA

Source 100ltA

9. Break detect

Two

NOTES
1. Internal BRG used for Rxe.
2. Internal BRG used for TxC

When CR5 (RTS) is set, the RTS pin is
forced low and the transmit serial logic is
enabled. A 1 to 0 transition of CR5 will cause
RTS to go high (inactive) one TxC time after
the last serial bit has been transmitted (if
the transmit shift register was not empty).
The EPCI can operate in one of four submodes within each major mode (synchronous or asynchronous). The operational
sub-mode is determined by CR7 and CR6.
CR7-CR6 = 00 Is the normal mode, with the
transmitter and receiver operating independently in accordance with the mode and status register instructions.
In asynchronous mode, CR7-CR6 = 01
places the EPCI In the automat!c echo
mode. Clocked, regenerated received data
are automatically directed to the TxO line
while normal receiver operation continues.
The receiver must be enabled (CR2 I), but
the transmitter need not be enabled. CPU to
receiver communications continues normally, but the CPU to transmitter link is disabled. Only the first character of a break
condition is echoed. The TxO output will go
high until the next valid start is detected.
The following conditions are true while in
automatic echo mode:

=

1·60

1. Data assembled by the receiver are
automatically placed in the transmit holding register and retransmitted by the
transmitter on the TxO output.
2. The transmitter is clocked by the receive
clock.
3. TxROY output = 1.
4. The TxEMT/OSCHG pin will reflect only
the data set change condition.
5. The TxEN command (CRO) is ignored.
In synchronous mode, CR7-CR6 = 01 places
the EPCI in the automatic SYN IDLE stripping mode. The exact action taken depends
on the setting of bits MR 17 and MR 16:
1. In the non-transparent, Single SYN mode
(MR17-MRI6 = 10), characters in the
data streem matching SYN 1 are not
transferred to the receive data holding
register (RHR).
2. In the non-transperent, double SYN mode
(MR17-MRI6 = 00), characters in the
data stream matching SYN I, or SYN2 if
immediately preceded by SYN I, are not
transferred to the RHR.
3. In transparent mode (MRI6 = I), charac·
ters in the data stream matching OLE, or
SYN 1 if immediately preceded by OLE,
are not transferred to the RHR. However,

Signetics

SC2661

Two diagnostic sub-modes can also be
configured. In local loop back mode (CR7CR6 = 10), the following loops are connected internally:
1. The transmitter output is connected to
the receiver input.
2. OTR is connected to OCO and RTS is connected to CTS.
3. The receiver is clocked by the transmit
clock.
4. The OTR, RTS and TxO outputs are held
high.
5. The CTS, OCO, OSR and RxO inputs are
ignored.
Additional requirements to operate in the local loop back mode are that CRO (TxEN),
CR 1 (OTR), and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the EPCI.
The second diagnostic mode is the remote
loop back mode (CR7-CR6 = 11). In this
mode:
1. Data assembled by the receiver are
automatically placed in the transmit holding register and retransmitted by the
transmitter on the TxO output.
2. The transmitter is clocked by the receive
clock.
3. No data are sent to the local CPU, but the
error status conditions (PE, DE, FE) are
set.
4. The RxROY, TxROY, 'and TxEMT 10SCHG
outputs are held high.
5. CRI (TxEN) is ignored.
6. All other signals operate normally.

Status Register
The data contained in the status register (as
shown in table 8) indicate receiver and
transmitter conditions and modem I data set
status.
SRO is the transmitter ready (TxROY) status
bit. It, and its corresponding output, are valid
only when the transmitter is enabled. If equal
to 0, it indicates that the transmit data holding register has been loaded by the CPU and
the data has not been transferred to the
transmit shift register. If set equal to 1, it
indicates that the holding register is ready
to accept data from the CPU. This bit is
initially set when the transmitter is enabled
by CRO, unless a character has previously
been loaded into the holding register. It is
not set when the automatic echo or remote
loopback modes are programmed. When
this bit is set, the TxROY output pin is low. In

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
the automatic echo and remote loop back
modes, the output is held high.
SR I, the receiver ready (RxRDY) status bit,
indicates the condition of the receive data
holding register. If set, it indicates that a
character has been loaded into the holding
register from the receive shift register and is
ready to be read by the CPU. If equal to
zero, there is no new character in the hold·
ing register. This bit is cleared when the
CPU reads the receive data holding register
or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT I DSCHG bit, SR2, when set, indio
cates either a change of state of the DSR or
DCD inputs (when CR2 or CRO = 1) or that
the transmit shift register has completed
transmission of a character and no new
character has been loaded into the transmit
data holding register. Note that in synchro·
nous mode this bit will be set even though
the appropriate "fiU" character is transmitted. TxEMT will not go active until at least
one character has been transmitted. It is

cleared by loading the transmit data holding
register. The DSCHG condition is enabled
when TxEN = 1 or RxEN = 1. It is cleared
when the status register is read by the
CPU. If the status register is read twice and
SR2 = 1 while SR6 and SR7 remain un·
changed, then a TxEMT condition exists.
When SR2 is set, the TxEMT I DSCHG output
is low.
SR3, when set, indicates a received parity
error when parity is enabled by MR 14. In
synchronous transparent mode (MRI6 = I),
with parity disabled, it indicates that a character matching OLE regisler was received
and Ihe present character is neither SYN 1
nor OLE. This bit is cleared when the next
character following the above sequence is
loaded into RHR, when the receiver is dis·
abled, or by a reset error command, CR4.
The overrun error status bit, SR4, indicates
that the previous character loaded into the
receive holding register was not read by the
CPU at the time a new received character
was transferred into it. This bit is cleared

SC2661

when the receiver is disabled or by the reset
error command, CR4.
In asynchronous mode, bit SRS signifies that
the received character was not framed by a
stop bit, Le., only the first stop bit is
checked. If RHR 0 when SRS I, a break
condition is present. In synchronous nontransparent mode (MRI6 = 0), it indicates
receipt olthe SYN 1 character in single SYN
mode or the SYN I-SYN2 pair in double SYN
mode. In synchronous transparent mode
(MRI6 = I), this bit is set upon detection of
the initial synchronizing characters (SYN 1
or SYN I-SYN2) and, after synchronization
has been achieved, when a DLE·SYN 1 pair
is received. The bit is reset when the receiv·
er is disabled, when the reset error com·
mand is given in asynchronous mode, or
when the status register is read by the CPU
in the synchronous mode.

=

=

SR6 and SR7 reflect the conditions of the
DCD and DSR inputs respectively. A low in·
put sets its corresponding status bit, and a
high input clears it.

ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
Operating ambient temperalure 2
Siorage temperature
All voltages wilh respecllo ground 3

DC ELECTRICAL CHARACTERISTICS

TA

RATING

UNIT

o to +70
-6Slo +IS0
-O.Slo +6.0

°c
°c
V

= O°C 10 HO°C, VCC = S.OV

± S%

4.5 ••

LIMITS
PARAMETER

VIL
VIH

Input voltage
Low
High

VOL
VOH 7

Outpul voltage
Low
High

IlL

Input leakage currenl

ILH

3-slale outpul leakage current
Data bus high

ILL

Dala bus low

ICC

Power supply current

CAPACITANCE

TA

TEST CONDITIONS

Min

Typ

Max

UNIT
V

O.B
2.0
V
IOL = 2.2mA
IOH = -400/LA
VIN

0.4
2.4

= 010 S.S V

10

/LA
/LA

Vo = 4.0V
Vo = 0.4SV

10
10
ISO

mA

= 2SoC, VCC = OV
LIMITS

PARAMETER

CIN
COUT
CliO

Capacitance
Input
Output
In pull Outpul

TEST CONDITIONS

Min

Typ

Max

UNIT
pF

fc = lMHz
Unmeasured pins tied 10 ground

20
20
20

Notes on follOWing page

Signe1ics

1·61

1

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
AC ELECTRICAL CHARACTERISTICS
PARAMETER

TA = O·C to HO·C, vcc = 5.0V ± 5%
TEST CONDITIONS

4.5.6

Min

Pulse width
Reset
Chip enable

1000
250

tAS
tAH
tcs
tCH
tos
tOH
tRXS
tRXH

Setup and hold time
Address setup
Address hold
AI W control setup
AI W control hold
Data setup for write
Data hold for write
Rx data setup
Rx data hold

10
10
10
10
150
0
300
350

too
tOF
tCEO

Data delay time for read
Data bus floating time for read
CE to CE delay

UNIT

ns

200
100

Cl = 150pF
Cl = 150pF

ns

600
MHz

fRIT'o
tBRH"
tBRH"
tBRl S
tBRl S
tR/TH
tRITl'o

Clock width
Baud rate high (2661A,B)
Baud rate high (2661C)
Baud rate low (2661A,B)
Baud rate low (2661C)
TxC or RxC high
TxC or RxC low

tTXD

TxD delay from falling
edgeof~

Cl = 150pF

tTCS

Skew between TxD changing and
falling edge of TxC output 8

CL = 150pF

1.0

4.9152

4.9202

1.0
dc

5.0688

5.0738
1.0
ns

75
70
75
70
480
480

1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This IS a stress rating only and functional operation of
the device at these or at any other condition above those indicated In the operation section of this specIfication is not Implied
2 For operating at elevated temperatures, the device must be derated based on
+ 150°C maximum ,unction temperature and thermal resistance of 60°C/W Junction to ambient (10 ceramic package)
3 This product Includes cIrcUitry speClflcally designed for the protection of Its internal devices from the damaging effects of excessive statiC charge Nonetheless, It
IS suggested that conventional precautions be taken to avoid applYing any voltages larger than the rated maxima
4 Parameters are valid over operating temperature range unless otherwise specIfied.
5. All voltage measurements are referenced to ground All time measurements are at
the 50% level for Inputs (except IBAH and tSAL) and at 0 BV and 2 OV for outputs
Input levels sWing between 04V and 2.4V, with a transition time of 20 ns maxImum
6 TYPical values are at + 20°C, tYPical supply voltages and tYPical processing
parameters
7 TxADY, 'RX'Ff5Y and"TxEMT/B'SCHG outputs are open drain
8. Parameter apphes when Internal transmItter clock IS used
9 Under test conditions of 5.0688 MHzfBRG (2661 C) and 4 9152 MHz fSRG (2661A,B),
leRH and teRL measured at VIH and VIL respectively
10 In asynchronous localloopback mode, uSing 1X clock, the follOWing parameters
apply'
fAIT=OB3 MHz max
tRITL = 700 ns min

1·62

Max

ns

Input clock frequency
Baud rate generator
(2661A,B)
Baud rate generator
(2661C)
TxC or RxC

fBRG

Typ

...

tRES
tCE

fBRG

SC2661

Signetics

650
0

ns

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

SC2661

TIMING DIAGRAMS
RESET

CLOCK

RESET-1_'"ES_r~--

BACLK,

TiC, RiC
-'/lBRG-

- - - lJ1RIT

TRANSMIT

---1

RECEIVE

1 BIT TIME
(1 16 OR 64 CLOCK PERIODS)

fie
(INPUT)

T.D

TiC
(OUTPUT)

READ AND WRITE

CE---...

Do-D7
(WRITE)

00-0 7
(READ)

---+---....;.;==+,'-..;.;;:;;;;...,I'-___~-'

Signelics

1·63

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

SC2661

TIMING DIAGRAMS (Cont'd)
TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode] )

DATA 1

-

D

DATA 4

I I'
A

I

2 I

3 I •

I '

I"

C

I

A

I'

I 2

~A;A ~ •

I '

1" CI A,1_
I

TxEN

0

~

~

TxRDY

Ii
~

~

TxEMT

~

I
I
I

2 ! 3 ! 4 : 5,"
DATA 3

:

I
I
I

•

C_D_A

I
I
I

S

DATA 4

t
----+------+---_--\----~'_______'c
~~:
)

CEFOR~
WRITE
OFTHR
DATA 1

t5

)

NOTES
A = Start bIt
B=Stopbitl
C=Stopbit2
o = TxD marking conditIOn
TxEMT goes low at the beglnnmg of the last data bit, or, If panty IS enabled, at the beglnnmg of the panty bit

1·64

!

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

SC2661

TIMING DIAGRAMS (Conl'd)
EXTERNAL SYNCHRONIZATION WITH XSYNC

1XRxC

Ie.

XSYNC

1--

-1

I

II

---j

t8S = XSYNC SETUP TIME = 300n.
IH = XSYNC HOLD TIME = ONE Rxe

I
I

I.

I

R'D

v

CHARACTER ASSEMBLY

BREAK DETECTION TIMING
Rx CHARACTER = 5 BITS, NO PARITY

AxC-16or64

I

LOOK FOR START BIT = LOW (IF RxO IS HIGH, LOOK FOR HIGH TO LOW TRANSITION)

R,D

I

i

FALSE START BIT CHECK MADE (RxD LOW)

I
MlsstNG STOP BIT DETECTED, SET FE BIT
O-RHR. ACTIVATE RxRIW SET BKDET PIN
RxD INPUT- RxSR UNTIL A MARK TO SPACE TRANSITION OCCURS

NOTE

* If the stop bit 18 present, the start bit search
will commence ImmedIately

Signetics

1·65

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

SC2661

TIMING DIAGRAMS (Cont'd)
RxRDY (Shown for 5·b,t characters, no parity, 2 stops bits [in asynchronous mode] )

UJ
t
-~~--'----~._------'-----~~
~ ~ ~-r-------

i:;~~
I

RiADY

=

~

IGNORED

I

-

----, I

~

~------~,

U

READ

READ

READ

READ

READ

STATUS

STATUS

AHA
(DATA 1)

AHA
(DATA 2)

AHA
(DATA 3)

AHA
(DATA 3)

c

IU

~

~,--------

READ

I -, 0 , -

A

l'

I _

I 2 I 3 I 4 I 5
DATA 3

U

II

B I C

.

I

A, 1 I 2 I 3 I

I _

DATA 4

RxEN

L-o----'

IL ___________________

~--~------~,

OVERRUN
STATUS BIT

------------------~~~----------------------~

CE FOA
READ

READ
RHR

READ
RHR

(DATAt)

(DATA3)

NOTES

A=Startbit
B Stop bit 1
C=Stopblt2
o = TxD marking condition

=

Only one stop bit IS detected

1·66

SigneIics

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)

SC2661

TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL

ADDRESS IUS

CONTROL BUS

DATA BUS

r------,
R,O

...,

T,O

1··0----11

ElATa TTL

kIv
I

1 ....r----JF1n----.==---.-~

1-----i~~r_----Co-:-~-;rr-----J-__,

'-....___-1

L..._ _ _ _ _._R_CL.....
K ,~'"

BAlI) RATE CLOCK

CRT
TERMINAL

L -_ _O_._C'_LLA_T_OR_ _.....

ASYNCHRONOUS INTERFACE TO TELEPHONE LINES

DATA BUS

ASYNC
MODEM

BRCLK

PHONE
LINE
INTERFACE

BAUD RATE CLOCK
OSCILLATOR

T!lEPHONE
LINE

1·67

MICROPROCESSOR DIVISION

JANUARY 1982

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE (EPCI)
TYPICAL APPLICATIONS (Cont'd)
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE

\

\

ADDRESS BUS

I

\

CONTROL BUS

\

I

I

\

DATA BUS

JD~

R.D
T.D

RiC

'66'

SYNCHRONOUS
TERMINAL
OR PERIPHERAL

DEVICE

TiC

SYNCHRONOUS INTERFACE TO TELEPHONE LINES

PHONE
LINE
INTERFACE
SYNC
MODEM

r

TELEPHONE
LINE

1·68

Signettcs

'SC2661

JANUARY 1982

MICROPROCESSOR DIVISION

SC2681 SERIES

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

'4'Mi4Y'
PIN CONFIGURATION

DESCRIPTION

FEATURES

TheSIgnetlcsSC2681 Dual Universal Asynchronous ReceiverlTransmitter (DUART) Is
a single chip MOS-LSI communications
device that provides two Independent fullduplex asynchronous receiver/transmitter
channels in a single package. It interfaces
directly with microprocessors and may be
used in s polled or interrupt driven system.

• Dual full-duplax asynchronous racelver/
transmlter
• Quadruple buffered receiver data registers
• Programmable data format
-5 to 8 data bits plus parity
-Odd. even, no parity or force parity
-1,1.5 or 2 stop bits programmable In
1/16 bit Increments
• Programmable baud rate for each recelvar and transmlter selectable from:
-18 fixed rates: 50 to 38.4K baud
-One user defined rate derived from
programmable timer/counter
- External 1x or 16x clock
• Parity. framing. and overrun error detec·
tlon
• False start bit detection
• LIne break detection and generation
• Programmable channel mode
-Normal (full duplex)
-Automatic echo
-Localloopback
-Remote loopback
• Multl·functlon programmable 16-blt
counter/timer
• Multl·functlon 7·blt Input port
-Can serve as clock or control Inputs
-Change of state detection on four
Inputs
• Multl·functlon 6-blt output port
-Individual bit set/raset capability
-Outputs can be programmed to be
status/Interrupt signals
• Versatile Interrupt system
-Single Interrupt output with eight
maskable Interrupting conditions
-Output port can be configured to provide a total of up to six separate wire·
OR'able Interrupt outputs
• Maximum data transfer: 1X - 1MB/sec,
16X - 125KB/sec
• Automatic wake-up mode for multidrop
applications
• Start·end break Interrupt/status
• Detects break which originates In the
middle of a character
• On·chlp crystal oscillator
• TTL compatible
• Single + 5V power supply

The operating mode and data format of
each channel can be programmed independently. Additionally, each receiver and
transmitter can select its operating speed
as one of eighteen fixed baud rates, a 16x
clock derived from a programmable
counter/timer, or an external 1x or 16x
clock. The baud rate generator and
counter/timer can operate directly from a
crystal or from external clock inputs. The
ability to independently program the
operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications
such as clustered terminal systems.
Each receiver is quadruply buffered to
minimize the potential of receiver overrun
or to reduce interrupt overhead In Interrupt driven systems. In addition, a flow
control capability Is provided to disable a
remote DUART transmitter when the buffer of the receiving device Is full.
Also provided on the SC2681 are a multipurpose 7-blt input port and a multipurpose 8-blt output port. These can be used
as general purpose I/O ports or can be
assigned specific functions (such as clock
Inputs or status/Interrupt outputs) under
program contro\.
The SC2681 is available In three package
versions to satisfy various system requirements: 4O-pln and 28-pin, both 0.6" wide
DIPs, and a compact 24-pln, 0.4" wide,
DIP.

,p,
,p>
,po

'.2
CSN
RESET
X1lelK

X2

RXDA

RXDS

OPl
OP'
OPS
OP7

OP~

Dl

DO

D'

D2

DS

D'

D7

DO

GND

Vee

'P2
CSN
RESET

XlICLK
X2

RXDA

OPO
Dl

DO

DS

D'

D2

D7

DO

GND

INTRN

AD

Vee

CSN
RESET
X1/CLK
RXDA

TXDA

ORDERING CODE
PACKAGES
Ceramic DIP
Plastic DIP

1
Vee

DO

Vcc=5V :t5%, TA=O·C to 70·C
24 Pin'

28 Pln 2

40 Pln 2

SC2681CSI24
SC2681CSN24

SC2681CSI28
SC2681CSN28

SC2681CSI40
SC2681CSN40

1400 mil wide DIP
2eoo mil Wide DIP

02
OS

0'
DO

INTRN

OND

TOP VIEWS

Signetics

1·69

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'Q'¥'Weii
BLOCK DIAGRAM

r8
DO-D7 (

.1)I

I
J.;::::

BUS BUFFER

CHANNEL A

"

I

r--

TRANSMIT
HOLDING REG

TxDA

TRANSMIT
SHIFT REGISTER
RON
WRN

OPERATION

•

CEN
AO-A3
RESET

~ I'--

CONTROL

..
4/

•
•

I

ADDRESS
DECODE

I

RIW CONTROL

RECEIVE
HOLDING REG
(3)

I r--

-

I

RECEIVE
SHIFT REG

..

RxDA

~
CRA

SRA

INTERRUPT
CONTROL

j.-

BE:)

INTRN

f--

,,1z

TIMING

XlICLK
X2

•

..

BAUD RATE
GENERATOR

I

I

CLOCK
SELECTORS

I

I

COUNTERI
TIMER

iii

;::

.""'

.....~

INPUT PORT
CHANGE OF
STATE
DETECTORS (4)

7/

IPO-IPS

z

0:

w

....

f-- t-- !

~
ACR

OUTPUT PORT

I

XTALOSC

J

I

'--

FUNCTION
SELECT
LOGIC

V-

r-csRA
:

CSRB
ACR

:

CTUR

~

1·70

RxDB

f-- ~

ISR

I

TxDB

CHANNELB
(AS ABOVE)

Signetics

8

OPO-OP7

~
OPR

..

Vee

..

·GND

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'i't""

PIN DESIGNATION
APPLICABLE

TYPE

NAME AND FUNCTION

X

I/O

Data BUB: Bidlrectlonal3-state data bus used to transfer commands, data and status between
the OUART and the CPU. DO Is the least significant bit.

X

X

I

Chip Enable: Active low Input signal. When low, data transfers between the CPU and the
OUART are enabled on 00-D7 as controlled by the WRN, RON and AO-A3Inputs. When high,
places the DO-07 lines In the 3-state condition.

X

X

X

I

Write Strobe: When low and CEN Is also low, the contents of the data bus Is loaded Into the
addressed register. The transfer occurs on the rising edge of the signal.

RDN

X

X

X

I

Read Strobe: When low and CEN is also low, causes the contents of the addressed register to
be presented on the data bus. The read cycle begins on the falling edge of RDN.

MNEMONIC

40

28

24

00-07

X

X

CEN

X

WRN

AO-A3

X

X

X

I

Address Inputs: Select the OUART internal registers and ports for read/write operations.

RESET

X

X

X

I

Re..t: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO-OP7
in the high state, stops the counter/timer, and puts channels A and B In the inactive state,
with the TxDA and TxDB outputs In the mark (high) state.

INTRN

X

X

X

0

Interrupt Request: Active low, open drain, output which signals the CPU that one or more of
the eight maskable Interrupting conditions are true.

X1/CLK

X

X

X

I

Crystal 1: Crystal or external clock Input. A crystal or clock of the specified limits must be
supplied at all times.

X2

X

X

I

Crystal 2: Connection for other side of the crystal. Should be open if crystal is not used.

RxOA

X

X

X

I

Channel A Receiver Serial Data Input: The least significant bit is received first. 'Mark' Is high,
'space' is low.

RxOB

X

X

X

I

Channel B Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high,
'space' Is low.

TxOA

X

X

X

0

Channel A Transmitter Serial Data Output: The least significant bit Is transmitted first. This
output is held In the 'mark' condition when the transmitter is disabled, Idle, or when operat·
ing in local loopback mode. 'Mark' Is high, 'space' Is low.

TxOB

X

X

X

0

Channel B Trensmltter Serial Data Output: The least significant bit Is transmitted first. This
output is held In the 'mark' condition when the transmitter is disabled, idle, or when operat·
ing in local loopback mode. 'Mark' is high, 'space' is low.

OPO

X

X

0

Output 0: General purpose output, or channel A request to send (RTSAN, active low). Can be
deactivated on receive or transmit.

OP1

X

X

0

Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be
deactivated on receive or transmit.

OP2

X

X

0

Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or chan·
nel A receiver 1X clock output.

OP3

X

0

Output 3: General purpose output, or open drain, active low counter/timer output, or channel
B transmitter 1X clock output, or channel B receiver 1X clock output.

OP4

X

0

Output 4: General purpose output, or channel A open drain, active low, RxROYAlFFULLA out·
put.

OP5

X

0

OutputS: General purpose output, or channel B open drain, active low, RxROYB/FFULLB out·
put.
OutputS: General purpose output, or channel A open drain, active low, TxROYA output.

OPS

X

0

OP7

X

0

Output 7: General purpose output, or channel B open drain, active low, TxROYB output.

IPO

X

I

Input 0: General purpose Input, or channel A clear to send active low input (CTSAN).

I

Input 1: General purpose Input, or channel B clear to send active low input (CTSBN).

I

Input 2: General purpose Input, or counter/timer external clock input.

I

Input 3: General purpose Input, or channel A transmitter external clock input (TxCA). When
the external clock Is used by the transmitter, the transmitted data Is clocked on the failing
edge of the clock.

IP1

X

IP2

X

1P3

X

X

Signetics

1-71

JANUARY 1982

MICROPROCESSOR DIVISION

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART)

SC2681 SERIES

'Rit)i;;'
PIN DESIGNATION (Continued)
MNEMONIC

APPLICABLE
40

28

24

TYPE
I

NAME AND FUNCTION

IP4

X

Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.

IP5

X

I

Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When
the external clock Is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.

IP6

X

I

Input 6: General purpose input or channel B receiver external clock input (RxCA). When the
external clock Is used by the receiver, the received data is sampled on the rising edge of the
clock.

Vcc
GND

X

X

X

I

Power Supply: + 5V supply Input

X

X

X

I

Ground

BLOCK DIAGRAM

Timing Circuits

The 2681 DUART consists of the following
eight major sections: data bus buffer,
operation control, interrupt control, timing, communications channels A and B, input port and output port. Refer to the
block diagram.

The timing block consists of a crystal
oscillator, a baud rate generator, a pro·
grammable 16-blt counterltlmer, and four
clock selectors. The crystal oscillator
operates directly from a 3.6864MHz crys·
tal connected across the Xl/ClK and X2
inputs. If an external clock of the appropri·
ate frequency is available, it may be con·
nected to Xl/ClK. The clock serves as the
basic timing reference for the baud rate
generator (BRG), the counterltim'er, and
other internal circuits. A clock Signal
within the limits specified in the specifica·
tions section of this data sheet must
always be supplied to the DUART.

Data Bus Buffer
The data bus buffer provides the interface
between the external and internal data
busses. It is controlled by the operation
control block to allow read and write
operations to take place between the controlling CPU and the DUART.

Operation Control
The operation control logic receives
operation commands from the CPU and
generates appropriate signals to internal
sections to control device operation. It
contains address decoding and read and
write circuits to permit communications
with the microprocessor via the data bus
buffer.

Interrupt Control
A Single active low interrupt output
(INTRN) is provided which Is activated
upon the occurence of any of eight inter·
nal events. Associated with the interrupt
system are the Interrupt mask register
(IMR) and the interrupt status register
(ISR). The IMR may be programmed to
select only certain conditions to cause
INTRN to be asserted. The ISR can be read
by the CPU to determine all currently ac·
tive interrupting conditions.
Outputs OP3-0P7 can be programmed to
provide discrete Interrupt outputs for the
transmitters, receivers, and counter/timer.

1-72

Communications Channels
A and B
Each communications channel of the 2681
comprises a full duplex asynchronous receiverltransmitter (UART). The operating
frequency for each receiver and transmitter can be selected independently from
the baud rate generator, the counter timer,
or from an external input.
The transmitter accepts parallel data from
the CPU, converts it to a serial bit stream,
inserts the appropriate start, stop, and op·
tional parity bits and outputs a composite
serial stream of data on the TxD output
pin. The receiver accepts serial data on
the RxD pin, converts this serial input to
parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition
and sends an assembled character to the
CPU.

The baud rate generator operates from the
oscillator or external clock Input and is
capable of generating 18 commonly used
data communications baud rates ranging
from 50 to 38.4K baud. The clock outputs
from the BRG are at 16X the actual baud
rate. The counterltimer can be used as a
timer to produce a 16X clock for any other
baud rate by counting down the crystal
clock or an external clock. The four clock
selectors allow the independent selection,
for each receiver and transmitter, of any of
these baud rates or an external timing signal.

The Inputs to this unlatched 7·blt port can
be read by the CPU by performing a read
operation at address D16. A high input reo
suits in a logic 1 while a low Input results
In a logic O. The pins of this port can also
serve as auxiliary inputs to certain por·
tions of the DUART logic.

The counterltimer (CIT) can be program·
med to use one of several timing sources
as its input. The output of the CIT is avail·
able to the clock selectors and can also be
programmed to be output at OP3. In the
counter mode, the contents of the CIT can
be read by the CPU and It can be stopped
and started under program control. In the
timer mode, the CIT acts as a program·
mabie divider.

Four change·of·state detectors are provided which are assoCiated with inputs
IP3, IP2, IP1, and IPO. A high-to-Iow or lowto-high transition of these inputs lasting
longer than 25-50"s will set the corresponding bit in the input port change register. The bits are cleared when the register is read by the CPU. Any change of state
can also be programmed to generate an interrupt to the CPU.

Signetics

Input Port

JANUARY 1982

MICROPROCESSOR DIVISION

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

IQ i49 i£i,
Output Port
The 8·bit multi·purpose output port can be
used as a general purpose output port, in
which case the outputs are the comple·
ments of the output port register (OPR).
OPR[nj= 1 results in OP[nj= low and vice·
versa. Bits of the OPR can be individually
set and reset. A bit is set by performing a
write operation at address E'6 with the ac·
companying data specifying the bits to be
set (1 = set, 0 = no change). Likewise, a bit
is reset by a write at address F '6 with the
accompanying data specifying the bits to
be reset (1 = reset, 0 = no change).
Outputs can be also individually assigned
specific functions by appropriate pro·
gramming of the channel A mode registers
(MR1A, MR2A), the channel B mode regis·
ters (MR1B, MR2B), and the output port
configuration register (OPCR).

OPERATION
Transmitter
The 2681 is conditioned to transmit data
when the transmitter is enabled through
the command register. The 2681 indicates
to the CPU that it is ready to accept a
character by setting the TxRDY bit in the
status register. This condition can be pro·
grammed to generate an interrupt request
at OP6 or OP7 and INTRN. When a charac·
ter is loaded into the transmit holding reg·
ister (THR), the above conditions are
negated. Data is transferred from the hold·
ing register to the transmit shift register
when it is idle or has completed transmis·
sion of the previous character. The TxRDY
conditions are then asserted again which
means one full character time of buffering
is provided. Characters cannot be loaded
into the THR while the transmitter is dis·
abled.
The transmitter converts the parallel data
from the CPU to a serial bit stream on the
TxD output pin. It automatically sends a
start bit followed by the programmed
number of data bits, an optional parity bit,
and the programmed number of stop bits.
The least significant bit is sent first. Fol·
lowing the transmission of the stop bits, if
a new character is not available in the
THR, the TxD output remains high and the
TxEMT bit in the status register (SR) will
be set to 1. Transmission resumes and the
TxEMT bit is cleared when the CPU loads a
new character into the THR. If the trans·
mitter is disabled, it continues operating
until the character currently being trans·
mitted is completely sent out. The trans·
mitter can be forced to send a continuous

low condition by issuing a send break
command.
The transmitter can be reset through a
software command. If it is reset, operation
ceases immediately and the transmitter
must be enabled through the command
register before resuming operation. If CTS
operation is enabled, the CTSN input must
be low in order for the character to be
transmitted. if it goes high in the middle of
a transmission, the character in the shift
register is transmitted and TxDA then reo
mains in the marking state until CTSN
goes low. The transmitter can also control
the deactivation of the RTSN output. If
programmed, the RTSN output will be reo
set one bit time after the character in the
transmit shift register and transmit hold·
ing register (if any) are completely trans·
mitted, if the transmitter has been dis·
abled.

Receiver
The 2681 is conditioned to receive data
when enabled through the command reg·
ister. The receiver looks for a high to low
(mark to space) transition of the start bit
on the RxD input pin. If a transition is de·
tected, the state of the RxD pin is sampled
each 16X clock for 7·1/2 clocks (16X clock
mode) or at the next rising edge of the bit
time clock (1X clock mode). If RxD is
sampled high, the start bit is invalid and
the search for a valid start bit begins
again. If RxD is still low, a valid start bit is
assumed and the receiver continues to
sample the input at one bit time intervals
at the theoretical center of the bit, until
the proper number of data bits and the
parity bit (if any) have been assembled,
and one stop bit has been detected. The
least sigificant bit is received first. The
data is then transferred to the receive
holding register (RHR) and the RxRDY bit
in the SR is set to a 1. This condition can
be programmed to generate an interrupt at
OP4 or OP5 and INTRN. If the character
length is less than eight bits, the most
significant unused bits in the RHR are set
to zero.
After the stop bit is detected, the receiver
will immediately look for the next start bit.
However, if a non·zero character was reo
ceived without a stop bit (framing error)
and RxD remains low for one half of the bit
period after the stop bit was sampled,
then the receiver operates as if a new start
bit transition had been detected at that
point (one·half bit time after the stop bit
was sampled).
The parity error, framing error, overrun er·
ror and received break state (if any) are

Signetics

strobed into the SR at the received charac·
ter boundary, before the RxRDY status bit
is set. If a break condition is detected
(RxD is low for the entire character in·
cluding the stop bit), a character con·
sisting of all zeros will be loaded into the
RHR and the received break bit in the SR
is set to 1 The RxD Input must return to a
high condition for at least one·half bit time
before a search for the next start bit
begins.
The RHR consists of a first·in·first·out
(FIFO) stack with a capacity of three char·
acters. Data is loaded from the receive
shift register into the topmost empty posi·
tion of the FIFO. The RxRDY bit in the
status register is set whenever one or
more characters are available to be read,
and a FFULL status bit is set if all three
stack positions are filled with data. Either
of these bits can be selected to cause an
interrupt. A read of the RHR outputs the
data at the top of the FIFO. After the read
cycle, the data FIFO and its associated
status bits (see below) are 'popped' thus
emptying a FIFO position for new data.
In addition to the data word, three status
bits (parity error, framing error, and reo
ceived break) are also appended to each
data character in the FI FO (overrun is not).
Status can be provided in two ways, as
programmed by the error mode control bit
in the mode register. In the 'character'
mode, status is provided on a character·
by'character basis: the status applies only
to the character at the top of the FIFO. In
the 'block' mode, the status provided in
the SR for these three bits is the logical
OR of the status for all characters coming
to the top of the FIFO since the last 'reset
error' command was issued. In either
mode reading the SR does not affect the
FIFO. The FIFO is 'popped' only when the
RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO is full when a new character is
received, that character is held in the reo
ceive shift register until a FIFO position is
available. If a~ additional character is reo
ceived while this state exits, the contents
of the FI FO are not affected: the character
previously in the shift register IS lost and
the overrun error status bit (SR[4]) will be
set upon receipt of the start bit of the new
(overruning) character.
The receiver can control the deactivation
of RTS. If programmed to operate in this
mode, the RTSN output will be negated
when a valid start bit was received and the
FIFO is full. When a FIFO position be·
comes available, the RTSN output will be
re·asserted automatically. This feature
can be used to prevent an overrun, in the

1-73

1

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
receiver, by connecting the RTSN output
to the CTSN Input of the transmitting
device.

ate normally whether or not the receiver is
enabled.

If the receiver is disabled, the FIFO char·
acters can be read. However, no additional
characters can be received until the reo
celver Is enabled again. If the receiver Is
reset, the FIFO and all of the receiver
status, and the corresponding output
ports and Interrupt are reset. No additional characters can be received until the
receiver is enabled again.

PROGRAMMING

Multidrop Mode
The DUART Is equipped with a wake up
mode used for multidrop applications.
This mode Is selected by programming
bits MR1A[4:3) or MR1B[4:3) to 'II' for
channels A and B respectively. In this
mode of operation, a 'master' station
transmits an address character followed
by data characters for the addressed
'slave' station. The slave stations, with
receivers that are normally disabled, ex·
amine the received data stream and 'wake·
up' the CPU (by setting RxRDy) only upon
receipt of an address character. The CPU
compares the received address to Its sta·
tion address and enables the receiver if it
wishes to receive the subsequent data
characters. Upon receipt of another address character, the CPU may disable the
receiver to Initiate the process again.
A transmitted character consists of a start
bit, the programmed number of data bits,
an address/data (AID) bit, and the programmed number of stop bits. The polarity
of the transmitted AID bit is selected by
the CPU by programming bit MR1A[2)1
MRI B[2). MR1A[2)/MRl B[2) = 0 transmits a
zero in the AID bit pOSition, which Identifies the corresponding data bits as data,
while MR1A[2)/MRlB[2)= 1 transmits a
one in the AID bit position, which identifies the corresponding data bits as an address. The CPU should program the mode
register prior to loading the corresponding
data bits Into the THR.
In this mode, the receiver continuously
looks at the received data stream, whether
It Is enabled or disabled. If disabled, it
sets the RxRDY status bit and loads the
character Into the RHR FIFO if the received AID bit is a one (address tag), but
discards the received character If the
received AID bit Is a zero (data tag). If
enabled, all received characters are transfe,rred to the CPU via the RHR. In either
case, the data bits are loaded into the data
FIFO while the AID bit is loaded into the
status FIFO pOSition normally used for
parity error (SRA[5) or SRB[5)). Framing
error, overrun error, and break detect oper·

1·74

The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback
Is provided via status registers which can
be read by the CPU. The addressing of the
registers Is described In table 1.
The contents of certain control registers
are Initialized to zero on RESET. Care
should be exercised if the contents of a
register are changed during operation,
since certain changes may cause operational problems. For example, changing
the number of bits per character while the
transmitter Is active may cause the transmission of an incorrect character. In gen·
eral, the contents of the MR, the CSR; and
the OPCR should only be changed while
the receiver(s) and transmltter(s) are not
enabled, and certain changes to the ACR
should only be made while the CIT Is
stopped.
Mode registers 1 and 2 of each channel are
accessed via Independent auxiliary point·
ers. The pointer Is set to MRlx by RESET
or by Issuing a 'reset pOinter' command
via the corresponding command register.
Any read or write of the mode register
while the pointer is at MRlx switches the
pointer to MR2x. The pointer then remains
at MR2x, so that subsequent accesses are
always to MR2x unless the pointer is reset
to MRlx as described above.
Mode, command, clock select, and status
registers are duplicated for each channel
to provide total independent operation
and control. Refer to table 2 for register bit
descriptions.
Table 1.
A3 A2 AI AO

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

SC2681 SERIES

MR1A - Channel A Mode
Register 1
MRIA is accessed when the channel A MR
pOinter points to MRI. The pointer is set
to MRI by RESET or by a 'set pOinter' com·
mand applied via CRA. After reading or
writing MR1A, the pointer will pOint to
MR2A.
MR1AI7J - Channel A Receiver Request·
to-Send Control - This bit controls the
deactivation of the RTSAN output (OPO) by
the receiver. This output is normally
asserted by setting OPR[O) and negated by
resetting OPR[O). MR1A[7) = 1 causes
RTSAN to be negated upon receipt of a
valid start bit If the channel A FI FO is full.
However, OPR[O) is not reset and RTSAN
will be asserted again when an empty
FIFO position is available. This feature
can be used for flow control to prevent
overrun in the receiver by using the
RTSAN output Signal to control the CTSN
input of the transmitting device.
MR1A18) - Channel A Receiver Interrupt
Select - This bit selects either the channel A receiver ready status (RXRDY) or the
channel A FIFO full status (FFUll) to be
used for CPU interrupts. It also causes the
selected bit to be output on OP4 if it is
programmed as an Interrupt output via the
OPCR.
MR1A[5) - Channel A Error Mode Select
- This bit selects the operating mode of
the three FIFOed status bits (FE, PE, received break) for channel A. In the 'charac·
ter' mode, status is provided on a character-by-character basis: the status applies
only to the character at the top of the
FIFO. In the 'block' mode, the status provided in the SR for these bits is the ac-

2681 REGISTER ADDRESSING

READ (RON =0)

WRITE (WRN = 0)

Mode Register A (MR1A, MR2A)
Status Register A (SRA)
"Reserved"
RX Holding Register A (RHRA)
Input Port Change Reg. (IPCR)
Interrupt Status Reg. (ISR)
CounteriTImer Upper (CTU)
CounteriTImer lower (CTl)
Mode Register B (MRI B, MR2B)
Status Register B (SRB)
"Reserved"
RX Holding Register B (RHRB)
"Reserved"
Input Port
Start Counter Command
Stop Counter Command

Mode Register A (MR1A, MR2A)
Clock Select Reg. A (CSRA)
Command Register A (CRA)
TX Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Reg. (IMR)
CIT Upper Register (CTUR)
CIT lower Register (CTlR)
Mode Register B (MR1B, MR2B)
Clock Select Reg. B (CSRB)
Command Register B (CRB)
TX Holding Register B (THRB)
"Reserved"
Output Port Conf. Reg. (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'4'00'#4
Table 2. REGISTER BIT FORMATS

MR1A
MR1B

BIT7

BIT6

BITS

RX RTS
CONTROL

RXINT
SELECT

ERROR
MODE

O=no
1 =yes

0= RXRDY
1 = FFULL

0= char
1 = block

BIT7

BIT6

CHANNEL MODE
MR2A
MR2B

BIT7
CSRA
CSRB
BIT7
CRA
CRB

SRA
SRB

not usedmust be 0

If

channel

BIT4
CTS
ENABLE Tx

O=no
1 =yes

0= no
1 =yes

IS

BIT2

BIT1

PARITY
TYPE

BIT3

00=5
01 =6
10=7
11 = 8

BIT2

BIT1

BITO

STOP BIT LENGTH*
0= 0.563
1 =0.625
2=0.688
3= 0.7S0

4=0.813
5=0.875
6=0.938
7= 1.000

8= 1.S63
9= 1.625
A= 1.688
B= 1.7S0

C= 1.813
D= 1.875
E= 1.938
F= 2.000

BIT2

BIT1

BITO

programmed for 5 bits/char

BIT4

BITS

BIT3

RECEIVER CLOCK SELECT

TRANSMITTER CLOCK SELECT

See text

See text

BIT6

1

BITO

BITS PER CHAR.

0= even
1 =odd

00 = with parity
01 = force parity
10= no parity
11 = special mode

BITS

BIT6

BIT3

PARITY MODE

Tx RTS
CONTROL

00= Normal
01 = Auto echo
10= Local loop
11 = Remote loop
• Add 0.5 to values shown for 0-7

BIT4

BIT3

BIT2

BIT1

BITO

MISCELLANEOUS COMMANDS

BITS

BIT4

DISABLE Tx

ENABLE Tx

DISABLE Rx

ENABLE Rx

See text

O=no
1 =yes

0= no
1 =yes

O=no
1 = yes

O=no
1 =yes

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

RECEIVED
BREAK

FRAMING
ERROR

PARITY
ERROR

OVERRUN
ERROR

TxEMT

TxRDY

FFULL

RxRDY

O=no
1 =yes

O=no
1 =yes

0= no
1 =yes

O=no
1 =yes

0= no
1 =yes

0= no
1 =yes

0= no
1 = yes

0= no
1 =yes

*These status bits are appended to the corresponding data character In the receIVe FIFO A read of the status register prOVides these bits (7 5) from the top of the FIFO
together with bits 40 These bits are cleared by a 'reset error status' command In character mode they are discarded when the corresponding data character IS read
from the FIFO

OPCR

ACR

IPCR

BIT2

BIT3

BIT1

BITO

BIT7

BIT6

BITS

BIT4

OP7

OP6

OP5

OP4

OP3

OP2

0= OPR[7]
1 = TxRDYB

0=OPR[6]
1 = TxRDYA

O=OPR[S]
1 = RxRDYI
FFULLB

0=OPR[4]
1 = RxRDYI
FFULLA

00= OPR[3]
01 = CIT OUTPUT
10= TxCB (1X)
11 = RxCB (1X)

00= OPR[2]
01 = TxCA (16X)
10 = TxCA (1X)
11 = RxCA (1X)

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

BRG SET
SELECT

COUNTERITIMER
MODE AND SOURCE

DELTA
IP31NT

DELTA
IP21NT

DELTA
IP11NT

DELTA
IPO INT

0= set1
1 = set2

See table 4

0=011
1 =on

0=011
1 =on

0=011
1 =on

0=011
1 =on

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

DELTA
IP3

DELTA
IP2

DELTA
IP1

DELTA
IPO

IP3

IP2

IP1

IPO

O=no
1 = yes

0= no
1 =yes

0= no
1 =yes

O=no
1 =yes

O=low
1 = high

O=low
1 = high

O=low
1 = high

O=low
1 = high

Signetics

1·75

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

'4'ii'.'
ISR

IMR

SC2681 SERIES

Table 2. REGISTER BIT FORMATS (continued)
BIT7

BIT8

BITS

BIT4

BIT3

BIT2

BIT1

BITO

INPUT
PORT
CHANGE

DELTA
BREAK B

RxRDYI
FFULLB

TxRDYB

COUNTER
READY

DELTA
BREAK A

RxRDYI
FFULLA

TxRDYA

O=no
1=yes

O=no
1=yes

O=no
1 = yes

O=no
1 = yes

O=no
1=yes

O=no
1 = yes

O=no
1=yes

O=no
1 = yes

BIT7

BIT8

BITS

BIT4

BIT3

BIT2

BIT1

BITO

IN. PORT
CHANGE
INT

DELTA
BREAK B
INT

RxRDYI
FFULLB
INT

TxRDYB
INT

COUNTER
READY
INT

DELTA
BREAK A
INT

RxRDYI
FFULLA
INT

TxRDYA
INT

0=011
1=on

O=off
1=on

O=off
1 =on

O=off
1=on

0=011
1=on

O=off
1=on

O=off
1=on

0=011
1 =on

CTUR

CTLR

cumulation (logical OR) of the status for
all characters coming to the top of the
FIFO since the last 'reset error' command
for channel A was issued.
MR1A[4:3) - Channel A Parity Mode
Select - If 'with parity' or 'force parity' is
selected, a parity bit Is added to the transmitted character and the receiver per·
forms a parity check on Incoming data.
MR1A[4:3]= 11 selects channel A to operate In the special multidrop mode described In the Operation section.
MR1A12J - Channel A Parity Type Select
- This bit selects the parity type (odd or
even) if the 'with parity' mode Is programmed by MR1A[4:3], and the polarity of the
forced parity bit if the 'force parity' mode
Is programmed. It has no effect if the 'no
parity' mode Is programmed. In the special
multidrop mode It selects the polarity of
the AID bit.
MR1A[1:0)- Channel A Bits per Character
Select - This field selects the number of
data bits per character to be transmitted
and received. The character length does
not Include the start, parity, and stop bits.

1·76

MR2A - Channel A Mode
Register 2
MR2A Is accessed when the channel A MR
pointer points to MR2, which occurs after
any access to MR1A. Accesses to MR2A
do not change the pointer.
MR2A[7:8) - Channel A Mode Select Each channel of the DUART can operate In
one of four modes. MR2A[7:6]= 00 is the
normal mode, with the transmitter and receiver operating Independently. MR2A[7:6]
= 01 places the channel in the automatic
echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo
mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock Is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The channel A TxRDY and TxEMT
status bits are Inactive.
5. The received parity Is checked, but Is
not regenerated for transmission, i.e.,
transmitted parity bit Is as received.

Signetics

6. Character framing is checked, but the
stop bits are retransmitted as received.
7. A received break Is echoed as received
until the next valid start bit Is detected.
8. CPU to receiver communication continues normally, but the CPU to transmitter link Is disabled.
Two diagnostic modes can also be configured. MR2A[7:6]= 10 selects local loopback mode. In this mode:
1. The transmitter output Is Internally
connected to the receiver input.
2. The transmit clock Is used for the receiver.
3. The TxDA output Is held high.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but
the receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode Is the remote
loopback mode, selected by MR2A[7:6]=
11. In this mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.

JANUARY 1982

MICROPROCESSOR DIVISION

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

IQi4\tMi
3. Received data is not sent to the local
CPU, and the error status conditions
are i nact ive.
4. The received parity is not checked and
is not regenerated for transmission,
i.e., transmitted parity bit is as received.
S. The receiver must be enabled.
6. Character framing is not checked, and
the stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
The user must exercise care when switching into and out of the various modes. The
selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected, the device will switch out of the
mode immediately. An exception to this is
switching out of autoecho or remote loopback modes: if the de-selection occurs
just after the receiver has sampled the
stop bit (indicated in autoecho by assertion of RxRDY), and the transmitter is
enabled, the transmitter will remain in
autoecho mode until the entire stop bit
has been retransmitted.
MR2A15] - Channel A Transmitter Request-to-Send Control - This bit controls
the deactivation of the RTSAN output
(0 PO) by the transmitter. This output is
normally asserted by setting OPR[O] and
negated by resetting OPR[O]. MR2A[S)= 1
causes OPR[O) to be reset automatically
one bit time after the characters in the
channel A transmit shift register and in
the THR, if any, are completely transmit·
ted, including the programmed number of
stop bits, if the transmitter is not enabled.
This feature can be used to automatically
terminate the transmission of a message
as follows:
1.
2.
3.
4.
S.

Program auto-reset mode: MR2A[S) = 1.
Enable transmitter.
Assert RTSAN: OPR[O)= 1.
Send message.
Disable transmitter after the last character is loaded into the channel A THR.
6. The last character will be transmitted
and OPR[O) will be reset one bit time
after the last stop bit, causing RTSAN
to be negated.
MR2A[4] - Channel A Clear·to·Send Con·
trol - If this bit is 0, CTSAN has no effect
on the transmitter. If this bit is a 1, the
transmitter checks the state of CTSAN

(I PO) each time it is ready to send a charac·
ter. If IPO is asserted (low), the character is
transmitted. If it is negated (high), the
TxDA output remains in the marking state
and the transmission is delayed until
CTSAN goes low. Changes in CTSAN
while a character is being transmitted do
not affect the transmission of that charac·
ter.
MR2A[3:0] - Channel A Stop Bit Length
Select - This field programs the length of
the stop bit appended to the transmitted
character. Stop bit lengths of 9/16 to 1 and
1-9/16 to 2 bits, in increments of 1/16 bit,
can be programmed for character lengths
of 6,7, and 8 bits. For a character length of
S bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. The receiver only checks for a 'mark' condition
at the center of the first stop bit position
(one bit time after the last data bit, or after
the parity bit if parity is enabled) in all
cases.
If an external 1X clock Is used for the
transmitter, MR2A[3) = 0 selects one stop
bit and M R2A[3) = 1 selects two stop bits
to be transmitted.

MR1 B - Channel B Mode
Register 1

CSRA[7:4]

a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1

a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1 1 1

a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 0
1 1 1

Baud Rate
ACR[7J=O
ACRI7] = 1

so
110
134.S
200
300
600
1,200
1,OSO
2,400
4,800
7,200
9,600
38.4K
Timer
IP4-16X
IP4-1X

7S
110
134.S
1S0
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
IP4-16X
IP4-1X

The receiver clock is always a 16X clock
except for CSRA[7:4]= 1111.
CSRAI3:0] - Channel A Transmitter Clock
Select - This field selects the baud rate
clock for the channel A transmitter. The
field definition is as per CSRA[7:4) except
as follows:
CSRA[3:0]

Baud Rate
ACR[7] = 0
ACR[7] = 1

1 1 1 a
1 1 1 1

IP3-16X
IP3-1X

IP3-16X
IP3-1X

MR1 B Is accessed when the channel B MR
pointer points to MR1. The painter is set
to MR1 by RESET or by a 'set pointer' command applied via CRB. After reading or
writing MR1 B, the pointer will point to
MR2B.

The transmitter clock is always a 16X
clock except for CSRA[3:0) = 1111.

The bit definitions for this register are
identical to the bit definitions for MR1A,
except that all control actions apply to the
channel B receiver and transmitter and the
corresponding inputs and outputs.

CSRBI7:4] - Channel B Receiver Clock
Select - This field selects the baud rate
clock for the channel B receiver. The field
definition is as per CSRA[7:4) except as
follows:

MR2B - Channel B Mode
Register 2
M R2B is accessed when the channel B M R
pointer paints to MR2, which occurs after
any access to MR1 B. Accesses to MR2B
do not change the pointer.
The bit definitions for this register are
identical to the bit definitions for MR2A,
except that all control actions apply to the
channel B receiver and transmitter and the
corresponding Inputs and outputs.

CSRA - Channel A Clock Select
Register
CSRA[7:4] - Channel A Receiver Clock
Select - This field selects the baud rate
clock for the channel A receiver as follows:

Signetics

CSRB - Channel B Clock Select
Register - Access Type: Write
Only

CSRB[7:4]

Baud Rate
ACRI7] = 0
ACRI7] = 1

1 1 1 a
1 1 1 1

IP6-16X
IP6-1X

IP6-16X
IP6-1X

The receiver clock is always a 16X clock
except for CSRB[7:4) = 1111.
CSRBI3:0] - Channel B Transmitter Clock
Select - This field selects the baud rate
clock for the channel B transmitter. The
field definition Is as per CSRA[7:4) except
as follows:
CSRB[3:0]

Baud Rate
ACR[7] = 0
ACR[7] = 1

1 1 1 a
1 1 1 1

IPS-16X
IPS-1X

IPS-16X
IPS-1X

The transmitter clock is always a 16X
clock except for CSRB[3:0) = 1111.

1·77

1

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'p"nA'",
CRA - Channel A Command
Register
CRA is a register used to supply commands to channel A. Multiple commands
can be specified in a single write to CRA
as long as the commands are non-conflicting, e.g., the 'enable transmitter' and
'reset transmitter' commands cannot be
specified in a single command word.
CRA[6:4) - Channel A Miscellaneous
Commands - The encoded value of this
field may be used to specify a single command as follows:
CRA[6:41

o0
o0
o1

o1

0
1

0

1

1 0 0

1 0 1

1 1 0

1 1 1

1-78

COMMAND
No command.
Reset MR pointer. Causes the
channel A MR pointer to pOint to
MR1.
Reset receiver. Resets the channel A receiver as if a hardware
reset had been applied. The receiver is disabled and the FIFO
is flushed.
Reset transmitter. Resets the
channel A transmitter as if a
hardware reset had been applied.
Reset error status. Clears the
channel A Received Break, Parity Error, Framing Error, and
Overrun Error bits in the status
register (SRA[7:4]). Used in character mode to clear OE status
(although RB, PE, and FE bits
will also be cleared) and in block
mode to clear all error status
after a block of data has been
received.
Reset channel A break change
interrupt. Causes the channel A
break detect change bit in the interrupt status register (ISR[2]) to
be cleared to zero.
Start break. Forces the TXDA
output low (spacing). If the
transmitter is empty the start of
the break condition will be delayed up to two bit times. If the
transmitter IS active the break
begins when transmission of the
character is completed. If a character is in the TH R, the start of
the break will be delayed until
that character, or any others
loaded subsequently are transmitted. The transmitter must be
enabled for this command to be
accepted.
Stop Break. The TXDA line will
go high (marking) within two bit

times. TXDA will remain high for
one bit time before the next
character, if any, is transmitted.
CRA[3) - Disable Channel A Transmitter
- This command terminates transmitter
operation and resets the TxRDY and
TxEMT status bits. However, if a character
is being transmitted or if a character is in
the THR when the transmitter is disabled,
the transmission of the character(s) is
completed before assuming the inactive
state..
CRA[2) - Enable Channel A Transmitter
- Enables operation of the channel A
transmitter. The TxRDY status bit will be
asserted.
CRA[1) - Disable Channel A Receiver This command terminates operation of
the receiver immediately - a character
being received will be lost. The command
has no effect on the receiver status bits or
any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is disabled. See
Operation section.
CRA[O) - Enable Channel A Receiver Enables operation of the channel A receiver. If not in the special wakeup mode,
this also forces the receiver into the
search for start-bit state.

CRB - Channel B Command
Register
CRB is a register used to supply commands to channel B. Multiple commands
can be specified in a single write to CRB
as long as the commands are non-conflicting, e.g., the 'enable transmitter' and
'reset transmitter' commands cannot be
specified in a single command word.
The bit definitions for this register are
identical to the bit definitions for CRA, except that all control actions apply to the
channel B receiver and transmitter and the
corresponding inputs and outputs.

SRA ~ Channel A Status
Register
SRA[7) - Channel A Received Break This bit indicates that an all zero character
of the programmed length has been received without a stop bit. Only a Single
FIFO position is occupied when a break is
received: further entries to the FIFO are inhibited until the RxDA line returns to the
marking state for at least one-half a bit
time (two successive edges of the internal
or external 1x clock).

Signetics

When this bit is set, the channel A 'change
in break' bit in the ISR (ISR[2]) is set. ISR[2]
is also set when the end of the break condition, as defined above, is detected.
The break detect circuitry can detect
breaks that originate in the middle of a
received character. However, if a break
begins in the middle of a character, it must
persist until at least the end of the next
character time in order for it to be detected.
SRA[6) - Channel A Framing Error - This
bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The
stop bit check is made in the middle of the
first stop bit position.
SRA[5) - Channel A Parity Error - This
bit is set when the 'with parity' or 'force
parity' mode is programmed and the corresponding character in the FIFO was received with incorrect parity.
In the special multidrop mode the parity
error bit stores the received AID bit.
SRA[4) - Channel A Overrun Error - This
bit, when set, indicates that one or more
characters in the received data stream
have been lost. It is set upon receipt of a
new character when the FIFO is full and a
character is already in the receive shift
register waiting for an empty FIFO position. When this occurs, the character in
the receive shift register (and its break
detect, parity error and framing error
status, if any) is lost.
This bit is cleared by a 'reset error status'
command.
SRA[3) - Channel A Transmitter Empty
(TxEMTA) - This bit will be set when the
channel A transmitter underruns, i.e., both
the transmit holding register (THR) and
the transmit shift register are empty. It is
set after transmission of the last stop bit
of a character if no character is in the THR
awaiting transmission. It is reset when the
THR is loaded by the CPU or when the
transmitter is disabled.
SRA[2) - Channel A Transmitter Ready
(TxRDYA) - This bit, when set, indicates
that the THR is empty and ready to be
loaded with a character. This bit is cleared
when the THR is loaded by the CPU and is
set when the character is transferred to
the transmit shift register. TxRDY is reset
when the transmitter is disabled and IS set
when the transmitter is first enabled, viz.,
characters loaded into the THR while the
transmitter is disabled will not be transmitted.

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

'4'41'"

SRA[1[ - Channel A FIFO Full (FFULLA)
- This bit IS set when a character is trans·
ferred from the receive shift register to the
receive FIFO and the transfer causes the
FIFO to become full, Le., all three FIFO
positions are occupied. It is reset when
the CPU reads the RHR. If a character is
waiting in the receive shift register be·
cause the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[O! - Channel A Receiver Ready
(RxRDYA) - This bit indicates that a char·
acter has been received and is waiting in
the FIFO to be read by the CPU. It is set
when the character is transferred from the
receive shift register to the FIFO and reset
when the CPU reads the RHR, if after this
read there are no more characters still in
the FIFO.

SRB - Channel B Status Register
The bit definitions for this register are
identical to the bit definitions for SRA, ex·
cept that all status applies to the channel
B receiver and transmitter and the carre·
sponding inputs and outputs.

OPCR - Output Port Configuration Register
OPCR[7! - OP7 Output Select - This bit
programs the OP7 output to provide one of
the following:
- The complement of OPR[7]
- The channel B transmitter interrupt
output, which is the complement of
TxRDYB. When in this mode OP7 acts
as an open collector output. Note that
this output is not masked by the can·
tents of the IMR.
OPCR[6! - OP6 Output Select - This bit
programs the OP6 output to provide one of
the followng:
- The complement of OPR[6]
- The channel A transmitter interrupt
output, which is the complement of
TxRDYA. When in this mode OP6 acts
as an open collector output. Note that
this output is not masked by the can·
tents of the IMR.
OPCR[S! - OPS Output Select - This bit
programs the OP5 output to provide one of
the following:
- The complement of OPR[5]
- The channel B receiver interrupt out·
put, which is the complement of ISR[5].
When in this mode OP5 acts as an open
collector output. Note that this output
is not masked by the contents of the
IMR.

SC2681 SERIES

OPCR[4! - OP4 Output Select - This bit
programs the OP4 output to provide one of
the following:

OPCR[1:0! - OP2 Output Select - This
field programs the OP2 output to provide
one of the following:

- The complement of OPR[4]
- The channel A receiver interrupt out·
put, which is the complement of ISR[1].
When in this mode OP4 acts as an open
collector output. Note that this output
is not masked by the contents of the
IMR.

- The complement of OPR[2]
- The 16X clock for the channel A trans·
mitter. This is the clock selected by
CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111.
- The 1X clock for the channel A trans·
mitter, which is the clock that shifts the
transmitted data. If data is not being
transmitted, a free running 1X clock is
output.
- The 1X clock for the channel A receiver,
which is the clock that samples the
received data. If data is not being received, a free running 1X clock is out·
put.

OPCR[3:2! - OP3 Output Select - This
field programs the OP3 output to provide
one of the following:
- The complement of OPR[3]
- The counterltimer output, in which
case OP3 acts as an open collector out·
put. In the timer mode, this output is a
square wave at the programmed fre·
quency. In the counter mode, the out·
put remains high until terminal count is
reached, at which time it goes low. The
output returns to the high state when
the counter is stopped by a stop
counter command. Note that this out·
put is not masked by the contents of
the IMR.
- The 1X clock for the channel B trans·
mitter, which is the clock that shifts the
transmitted data. If data is not being
transmitted, a free running 1X clock is
output.
- The 1X clock for the channel B receiver,
which is the clock that samples the
received data. If data is not being reo
ceived, a free running 1X clock is out·
put.

ACR - Auxiliary Control Register
ACR[7)- Baud Rate Generator Set Select
- This bit selects one of two sets of baud
rates to be generated by the BRG:
Set 1: 50, 110, 134.5, 200, 300, 600, 1.05K,
1.2K, 2.4K, 4.8K, 7.2K, 9.6K, and
38.4K baud.
Set 2: 75, 110, 134.5, 150, 300, 600, 1.2K,
1.8K, 2.0K, 2.4K, 4.8K, 9.6K, and
19.2K baud.
The selected set of rates is available for
use by the channel A and B receivers and
transmitters as described in CSRA and
CSRB. Baud rate generator characteristics
are given in table 3.

Table 3. BAUD RATE GENERATOR CHARACTERISTICS
CRYSTAL OR CLOCK = 3.6864MHz
NOMINAL RATE (BAUD)

ACTUAL 16X CLOCK (KHz)

ERROR (PERCENT)

50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
7200
9600
19.2K
38.4K

0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
307.2
614.4

0
0
-0.069
0.059
0
0
0
0
-0.260
0
0
0.175
0
0
0
0
0
0

NOTE
Duty cycle of 16X clock IS 50% :t: 1%

Signetics

1-79

1

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

14'4i"41"
ACR[6:4)-CounterITlmer Mode and Clock
Source Select - This field selects the
operating mode of the counterltimer and
its clock source as shown in table 4.
ACR[3:0) - IP3, IP2, IP1, IPO Change of
State Interrupt Enable - This field selects
which bits of the Input Port Change regis·
ter (IPCR) cause the input change bit In
the Interrupt status register (ISR[7)) to be
set. If a bit is In the 'on' state, the setting
of the corresponding bit In the IPCR will
also result in the setting of ISR[7], which
results in the generation of an Interrupt
output if IMR[7] = 1. If a bit Is in the 'off'
state, the setting of that bit in the IPCR
has no effect on ISR[7].

)PCR - Input Port Change
Register
IPCR[7:4) - IP3, IP2, IP1, IPO Change of
State - These bits are set when a change
of state, as defined in the Input Port sec·
tion of this data sheet, occurs at the respective input pins. They are cleared when
the IPCR Is read by the CPU. A read of the
IPCR also clears ISR[7], the input change
bit in the interrupt status register.
The setting of these bits can be programmed to generate an interrupt to the CPU.
IPCR[3:0) -IP3,IP2,IP1,IPO Current State
- These bits provide the current state of
the respective inputs. The (Information Is
unlatched and reflects the state of the input pins at the time the I PCR is read.

ISR -

Interrupt Status Register

This register provides the status of all
potential interrupt sources. The contents
of this register are masked by the interrupt
mask register (IMR). If a bit in the ISR is a
'1' and the corresponding bit in the IMR is
also a '1', the INTRN output will be asserted. If the corresponding bit in the IMR
is a zero, the state of the bit in the ISR has
no effect on the INTRN output. Note that
the IMR does not mask the reading of the
ISR - the true status will be provided
regardless of the contents of the IMA. The
contents of this register are initialized to
00'6 when the DUART is reset.
ISR[7) - Input Port Change Status - This
bit is a '1' when a change of state has
occurred at the IPO, IP1, IP2, or IP31nputs
and that event has been selected to cause
an interrupt by the programming of
ACR[3:0]. The bit is cleared when the CPU
reads the I PCR.

1·80

Table 4. ACR [6:4) FIELD DEFINITION
ACR[6:4)

MODE

CLOCK SOURCE

00 0
00 1
01 0
o11
1 00
1 0 1
1 1 0
111

Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer

External (IP2)
TXCA - 1X clock of channel A transmitter
TXCB - 1X clock of channel B transmitter
Crystal or external clock (X1fCLK) divided by 16
External (I P2)
External (IP2) divided by 16
Crystal or external clock (X1fCLK)
Crystal or external clock (X1fCLK) divided by 16

ISR[&) - Channel B Change In Break This bit, when set, Indicates that the channel B receiver has detected the beginning
or the end of a received break. It Is reset
when the CPU Issues a channel B 'reset
break change interrupt' command.

ISR[2] - Channel A Change in Break This bit, when set, Indicates that the channel A receiver has detected the beginning
or the end of a received break. It is reset
when the CPU Issues a channel A 'reset
break change Interrupt' command.

ISR[S) - Channel B Receiver Ready or
FIFO Full - The function of this bit is programmed by MR2B[5]. If programmed as
receiver ready, it indicates that a character
has been received In channel B and is
waiting in the FIFO to be read by the CPU.
It is set when the character Is transferred
from the receive shift register to the FI FO
and reset when the CPU reads the RHA. If
after this read there are more characters
still in the FIFO the bit will be set again
after the FI FO is 'popped'. If programmed
as FIFO full, it is set when a character is
transferred from the receive holding register to the receive FIFO and the transfer
causes the channel B FIFO to become full,
i.e., all three FIFO positions are occupied.
It is reset when the CPU reads the RHR. If
a character is waiting in the receive shift
register because the FIFO is full, the bit
will be set again when the waiting character Is loaded into the FIFO.

ISR[1) - Channel A Recelvar Ready or
FIFO Full - The function of this bit is programmed by MR2A[5]. If programmed as
receiver ready, it indicates that a character
has been received in channel A and is
waiting in the FIFO to be read by the CPU.
It is set when the character is transferred
from the receive shift register to the FIFO
and reset when the CPU reads the RHA. If
after this read there are more characters
still in the FIFO the bit will be set again
after the FI FO is 'popped'. If programmed
as FIFO full, It is set when a character Is
transferred from the receive holding register to the receive FIFO and the transfer
causes the channel A FIFO to become full,
I.e., all three FIFO pOSitions are occupied.
It is reset when the CPU reads the RHA. If
a character is waiting in the receive shift
register because the FIFO Is full, the bit
will be set again when the waiting character is loaded into the FIFO.

ISR[4) - Channel B Transmitter Ready This bit is a duplicate of TxRDYB (SRB[2]).
ISR[3) - Counter Ready - In the counter
mode, this bit is set when the counter
reaches terminal count and is reset when
the counter is stopped by a stop counter
command.
In the timer mode, this bit is set once each
cycle of the generated square wave (every
other time that the counterltlmer reaches
zero count). The bit is reset by a stop
counter command. The command, however, does not stop the counterftimer.

Signetics

ISR[O) - Channel A Transmitter Ready This bit is a duplicate of TxRDYA (SRA[2]).

IMR - Interrupt Mask Register
The programming of this register selects
which bits in the ISR cause an Interrupt
output. If a bit in the ISR is a '1' and the
corresponding bit in the IMR Is also a '1',
the INTRN output will be asserted. If the
corresponding bit in the IMR Is a zero, the
state of the bit in the ISR has no effect on
the INTRN output. Note that the IMR does
not mask the programmable interrupt outputs OP3-0P7 or the reading of the ISA.

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'A'iitA';'
CTUR and CTLR - Counter/Timer
Registers
The CTUR and CTlR hold the eight MSB's
and eight lSB's respectively of the value
to be used by the counterltimer in either
the counter or timer modes of operation.
In the timer (programmable divider) mode,
the CIT generates a square wave with a
period of twice the value (in clock periods)
of the CTUR and CTlA. If the value in
CTUR or CTlR is changed, the current
half·period will not be affected, but subse·
quent half periods will be. In this mode the
CIT runs continuously. Receipt of a start
counter command (read with A3-AO =
1111) causes the counter to terminate the
current timing cycle and to begin a new
cycle using the values in CTUR and CTlR.
The counter ready status bit (ISR[3]) is set

once each cycle of the square wave. The
bit IS reset by a stop counter command
(read with A3-AO= 1110). The command,
however, does not stop the CIT. The gen·
erated square wave is output on OP3 if it is
programmed to be the CIT output.
In the counter mode, the CIT counts down
the number of pulses loaded into CTUR
and CTlR by the CPU. Counting begins
upon receipt of a start counter command.
Upon reaching terminal count (0000 16), the
counter ready interrupt bit (ISR[3]) is set.
The counter continues counting past the
terminal count until stopped by the CPU. If
OP3 is programmed to be the output of the
CIT, the output remains high until terminal
count is reached, at which time it goes
low. The output returns to the high state
and ISR[3] is cleared when the counter is
stopped by a stop counter command. The

CPU may change the values of CTUR and
CTlR at any time, but the new count be·
comes effective only on the next start
counter command. If new values have not
been loaded, the previous count values
are preserved and used for the next count
cycle.
In the counter mode, the current value of
the upper and lower 8 bits of the counter
may be read by the CPU. It is recom·
mended that the counter be stopped when
reading to prevent potential problems
which may occur if a carry from the lower
8·bits to the upper 8·bits occurs between
the times that both halves of the counter
are read. However, note that a subsequent
start counter command will cause the
counter to begin a new count cycle using
the values in CTUR and CTlR.

ABSOLUTE MAXIMUM RATINGS 1
PARAMETER

RATING

UNIT

Operating ambient temperature2
Storage temperature
All voltages with respect to ground 3

o to + 70
-65 to + 150
-0.5 to +6.0

'C
'C
V

NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device ThiS 15
a stress rating only and functional operation of the device at these or at any other condition above those indicated
In the operation section of thiS specification IS not Implied
2 For operating at elevated temperatures, the device must be derated based on + 150°C maximum Junction
temperature and thermal resistance of 60"C/W Junction to ambient for ceramic package (116"CIW for plastiC
package)
3 ThiS product Includes circuitry specifically designed for the protection of ItS mternal devices from damaging effects of excessive static charge Nonetheless, It IS suggested that conventional precautions be taken to aVOId applymg any voltages larger than the rated maxima

DC ELECTRICAL CHARACTERISTICS TA = O'c to + 70'C, Vee= 5.0V
PARAMETER
V,L
V,H
V,H
VOL
V OH
I'L
ILL
loe
lee

Input low voltage
Input high voltage (except X1/ClK)
Input high voltage (X1/ClK)
Output low voltage
Output high voltage (except o.c. outputs)
Input leakage current
Data bus 3·state leakage current
Open collector output leakage current
Power supply current

TEST CON DITIONS

± 5%4,5.6

liMITS
Min

Typ

Max
0.8

2.0
3.0
10L = 2.4mA
10H= - 400~A
V ,N = 0 to Vcc
Vo= 0 to Vee
Vo=OtoV ee

0.4
2.4
-10
-10
-10

10
10
10
150

UNIT
V
V
V
V
V
~A
~A
~A

mA

NOTES
4 Parameters are valid over specified temperature range
5 All voltage measurements are referenced to ground (GNO) Fortestlng, all Input signals sWing between 0 4V and 2 4V with a tranSition tlmeof 20ns maximum All time measurements are referenced at Input voltages of 0 BV and 20V and output voltages of 0 BV and 2 OV as appropnate
6 TYPical values are at + 25°C, tYPical supply voltages, and tYPical processing parameters

Signetics

1·81

1

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'P't"#4
AC ELECTRICAL CHARACTERISTICS TA=O·C to + 70 ·C, Vcc =5.0V ± 5~ 4,5,6,7
TENTATIVE LIMITS

PARAMETER

Min

Reset Timing (figure 1)
t RES RESET pulse width
Bus Timing (figure 2)6
t AS
AO-A3 setup time to RON, WRN low
AO-A3 hold time from RON, WRN high
tAH
CEN setup, time to RON, WRN low
tcs
CEN hold time from RON, WRN high
tCH
tRW WRN, RON pulse width
Data valid after RON low
too
Data bus floating after RON high
tOF
Data
setup time before WRN high
tos
Data hold time after WRN high
tOH
Time between READs and/or WRITEs
tcc

10
10
0
0
225

n8
n8
n8
n8
ns
ns
ns
n8
ns
ns

150
100

0
0

400

Timing (figure 5)
X1ICLK high or low time
X1/CLK frequency
CTCLK (IP2) high or low time
CTCLK (IP2) frequency
RxC high or low time
RxC frequency (16X)
(1X)
TxC high or low time
TxC frequency (16X)
(1X)

,

300

-75

Receiver Timing (figure 7)
t RXS RxD data setup time to RXC high
tRXH RxD data hold time from RXC high
NOTES

300
300
300
300
200

100
2.0
200
0
220
0
0
220
0
0

Transmitter Timing (figure 6)
t Txo TxD output delay from TxC low
t TCS TxC output skew from TxD output data

UNIT

/LS

100
0
600

Interrupt Timing (figure 4)
INTRN (or OP3-0P7 when used as interrupts) high from:
tlR
Read RHR (RXRDY/FFULL Interrupt)
Write THR (TXRDY Interrupt)
Reset command (delta break Interrupt)
Stop CIT command (counter Interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)

tTX
f TX

Max

1.0

Port Timing (figure 3)8
t ps
Port input setup time before RON low
Port input hold time after RON high
t pH
Port output valid after WRN high
t po

Clock
tCLK
fCLK
t CTC
f CTC
tRX
f RX

Typ

200
200

3.6864

ns
ns
ns
ns
ns
ns

2.0
1.0

ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz

350
75

ns
ns

4.0
2.0
2.0
1.0

0

ns
ns
ns

ns
ns

4 Parameters are valid over specified temperature range
5 All voltage measurements are referenced to ground (GND) Fortestlng, alilOput signals sWing between 0 4Vand 2 4V wltl1a transition time of 20n8 maximum All time measure·
ments are referenced at Input voltages of 0 BV and 20V and output voltages of 0 BV and 2 OV as approprtate
TYPical values are at + 25 D C, tYPical supply voltages, and tYPical proceSSing parameters
Test condition for outputs CL = 150pF

8 Timing IS Illustrated and referenced to the WRN and RON Inputs The deVice may also be operated with CEN as the 'strobing' input. In this case, all timing specifications apply
referenced to the failing and rlsmg edges of CEN

1·82

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'A'WU;;'

1
RESET

r
--'

RESET TIMING

~_

l-IRES~

,

FIGURE 1

BUS TIMING

M_M~
lAS

CEN

leH

1 - - - - tRW-------'
RON

00-07

FLOAT

(READ)

WRN

FIGURE 2

Signefics

1·83

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

'4itlt4i,ii
PORT TIMING

"'~_4"~)L...-_-_-_-_~-_-_-_-_~-_~.

,~~ j{"-

WRN\'----_i~jX.

OPO·OP7

OLD DATA

NEW DATA

FIGURE 3

INTERRUPT TIMING

J£\'-----i,";-_
INTRN

OR
OP3·0P7

FIGURE 4

X1/CLK

CTCLK
RxC
TxC

--/

---

CLOCK TIMING
tcLK
tCTC

tA,
t"

----

FIGURE 5

1·84

Signetics

/
teLK
tCTC

tA,
t"

---

r-

SC2681 SERIES

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'i'Ai';4

1

TRANSMIT
(1

TxC

O~~~6~~~Ks)--=t

- }

(INPUn

-

TxD

t

ITXD

~r---:{.---"\x

TxC
(IX OUTPUn

-

/

FIGURE 6

RECEIVE
RxC
(IX INPUT)

\ r \"'---_

RXD--f···~ ~~]--FIGURE 7

TRANSMITTER TIMING

TRANSMITTER
ENABLED

TIlRDY
(SR2)

WRN

D'

03

START
BREAK

CTSN1
(IPO) _ _ _- - '

RTSN 2

(OPO)

A

D4

STOP

D5W1L.L

BREAK

NOT BE
TRANSMITTED

D.

i"1-----------------------~----OPR(O)= 1

NOTES
1. TIMING SHOWN FOR MR2(4)=1
2 TIMING SHOWN FOR MR2(5) 1

=

FIGURE 8

Signetics

1·85

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC2681 SERIES

'P'4it:i'
RECEIVER TIMING
RxO

RECEIVER
ENABLED

RxRDY

(8RO) _ _ _ _ _ _.......

+-__________-'

FFULL
(8R1) _ _ _ _ _ _ _ _ _ _ _

RxRDYf--------,
FFUlL
(OP5)2

RON

+ __..;;;;=..I

OVERRUN
(8R4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

RESET BY COMMAND

RTS1
(OPO)

NOTES
1. TIMING SHOWN FOR MR1(7)=1.
2. SHOWN FOR OPCR(4) 1 AND MR1(8)=O.

=

FIGURE 9
WAKEUP MODE
MASTER STATION

BIT9

TxO

!AOO_",

--------1','8

BIT9

I

DO

!oI

11-',

I

I

B,T9

_
IAoo"!'1
---------1,\----'---'---'-'

i

~I-I

L.CI---I---

I

TRANSM'TTER~'
ENA,BLED
I
II

(wSR ~

I

TxRDY

I
"

1 - - ' ,_

_

;)---1'~~----'I\

_

_ _ _ _ _ _ _ _--\'

,.

\

i

MR1(4·3)=11

ADO#1 MR1(2)=ODO

,'--_ _ _ _ _ _ _ _ _ _ _ __
)-

MR1(2)=1

ADD#2

MR1(2)=1

PERIPHERAL STATION

BIT 9
RXD---'

!oI

BIT9

BIT9

I

RECEIVER

!,'~

Of

I

I

R;~~~ ________.....J~ ~I-:
MR2(4.3):::11

-VADO#1

~

______----I~~
~

S~S~TA

STATUS DATA

DO

ADD#2

FIGURE 10

1·86

.-.....,B;:.:'T...
9-,;1-

-----------------+,----"L--

,--;-,

ENABLED _ _ _ _ _ _ _ _ _ _ _ _...:'_ _---I

RDN/WRNLJ

BIT 9

IADD., H 1i ............
I -DO .......
ioI::1 '""""II-,
\: ----------1, ~ IAoo*", I 1:1L.....L_..;.;I0;..l1 II'II-

Signetics

Section 2
Video Display

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
DESCRIPTION
The Signetics Display Character and
Graphics Generator (DCGG) is a maskprogrammable 11,648-bit line select character generator. It contains 128 10X9 characters placed in a 10X16 matrix, and has
the capability of shifting certain characters,
such as j, y, g, p and q, that normally extend
below the baseline. Character shilling, preViously requiring additional external circuitry, is now accomplished internally by the
DCGG; effectively, the 9 active lines are
lowered within the matrix to compensate for
the character's position.
Seven bits of an 8-bit address code are
used to select 1 of the 128 available characters. The eighth bit functions as a chip enable signal. Each character is defined by a
pattern of logic Is and Os stored in a 10X9
matrix. When a specific 4-bit binary line address code is applied, a word of 10 parallel
bits appears at the output. The lines can be
sequentially selected, providing a 9-word
sequence of 10 parallel bits per word for
each character selected by the address inputs. As the line address inputs are sequentially addressed, the device will automatically place the 1OX9 character in 1 of 2 preprogrammed positions on the 16-line matrix
with the positions defined by the 4-line address inputs. One or more of the 10 parallel
outputs can be used as control signals to
selectively enable functions such as halfdot shift, color selection, etc.
The 2670 DCGG includes latches to store
the character address and line address
data. A control input to inhibit character
data output for certain groups of characters
is also provided. The 2670 also includes a
graphics capability, wherein the 8-bit character code is translated directly into 256
possible user programmable graphic patterns. Thus, the DCGG can generate data for
384 distinct patterns, of which 128 are defined by the mask programmable ROM. See
figure 1 for a typical applications display.

FEATURES
•
•
•
•
•
•
•
•
•
•

SC2670

PIN CONFIGURATION

128 10X9 matrix characters
256 graphic characters
Optional thin graphics for forms
Character and line address latches
Internal descend logic
300nsec character select access
maximum
Control character output inhibit logic
Static operation-no clocks required
Single 5V power supply
TTL compatible inputs and outputs

TOP VIEW

ORDERING CODE
PACKAGES

COMMERCIAL RANGES
5%, TA = O'C to 70'C

vcc = sv ±

Ceramic DIP

SC2670'CS128

Plastic DIP

SC2670'CSN28

NOTE
Substitute letter corresponding to standard font for '*' In part number for standard parts See back of data sheet Contact sales office for custom ROM patterns

BLOCK DIAGRAM

=>

2-2

Signetics

DO-DO

JANUARY 1982

MICROPROCESSOR DIVISION

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

'ilA'"'''''-'''

PIN DESIGNATION
MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

CAO·CA7

3·6.6·11

I

Character Address: Eight bit code specifies the character or graphic pattern for whIch matrix
data is to be supplied. In character mode (GM=O), CAO thru CA6 select one of the 128 ROM·
defined characters and CA7 is a chip enable. The outputs are active when CA7= 1 and are trio
stated when CA7=0. In graphics mode (GM= I), the outputs are active and CAO thru CA7
select one of 256 possible graphic patterns to be output.

CSTROBE

7

I

Character Strobe: Used to store the character address (CAO thru CA7) and graphics mode
(GM) Inputs into the character latch Data is latched on the negative gOing edge of CSTROBE

GM

12

I

Graphics Mode: GM=O (low) selects character mode, GM=1 (hIgh) selects graphIcs mode

1,25'27

I

Line Address: In character mode, selects one of the 16 lines of matrix data for the selected
character to appear at the 10 outputs. LAO is the LSB and LA3 is the MSB. The input codes
which cause each of the nine lines of character data to be output are specified as part of the
programming data for both non·shifted and shifted fonts. Cycling through the nine specIfied
counts at the LAO thru LA3 inputs cause successive lines of data to be output on DO thru 09
The 7 non· specified codes for both non·shifted and shIfted characters cause blanks (logIc
zeros) to be output. In graphics mode, the line address gates the latched graphics data
directly to the outputs

LSTROBE

2

I

Line Strobe: Used to store the line address data (LAO thru LA3) in the line address latch
Data is latched on the negative going edge of LSTROBE

SCD

13

I

Selected Character Disable: In character mode, a hIgh level at this input causes all outputs
(regardless of line address) to be blanks (zeros) for characters for whIch CA6 and CA5 are
both O. A low level input selects normal operation. Inoperative in the graphIcs mode.

15·24

0

Data Outputs: Provide the data for the speCIfIed character and line.

28

I

+5V power supply

14

I

Ground.

LAO·LA3

09·00
VCC
GND

2

TYPICAL APPLICATION

Part No. Quant. Price TDt.3.1 i
r-Pi/?4
°JI

_'J.

:X9009

A~jW-2AI

?C
i...~

15.00 375.901
.-r
100 J"t,~b 3486.001
50 0.95 47.501
J

1"1. .....

L
E

s

!

Figure 1

Slgnatics

76

.,.,

,f ..l

78

80 81
2·3

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

Imti"lI,t.!lj
FUNCTIONAL DESCRIPTION
The OCGG consists of nine major sections.
Line and character codes are strobed into
the line and character latches. The character latch outputs are presented to the three
sources of data; the ROM through an address decoder, the graphics logic, and the
output inhibit control. The output inhibit control (together with the SCO input) suppresses the ROM data for selected character codes. The outputs from the line latch
drive the line address translation ROM
which maps the character ROM data onto 9
of 1S line positions. Finally, the line select
multiplexers route the ROM or graphics data
to the output drivers on DO through 09.

Character Latch
The character latch is a 9-bit edge triggered
latch used to store the character address
(CAO thru CA7) and graphics mode (GM)
inputs. The data is stored on the falling edge
of CSTROBE. Seven latched addresses
(CAO thru CAS) are inputs to the ROM character address decoder. In character mode
(GM=O), CA7 operates as a chip enable.
The output drivers are enabled when CA7= 1
and are tri-stated when CA7=0. In graphics
mode (GM= 1), the output drivers are always
enabled and the CAO thru CA7 outputs of the
latch are used to generate graphic symbols.

Character Address Decoder
This circuit decodes the 7 -bit character address from the character latch to select one

of the 128 character fonts stored in the ROM
section of the OCGG.

graphics symbols and an example where
(CA7 thru CAO) = H'S5'. The outputs from
the graphics logic go to the line select
multiplexers. The multiplexers route the
graphic symbol data to the outputs when
GM = 1.

Read Only Memory
The 11 ,S48-bit ROM stores the fonts for the
128 matrix-defined characters. The data for
each character consists of 91 bits. Ninety
bits represent the 10X9 matrix and one bit
specifies whether the character data is output at the normal (unshilled) lines or at the
descended (shilled) lines. The 90 data bit
outputs are supplied to the line select
multiplexers. The descend control bit is an
input to the line address translation ROM.

Thin Graphics Option
As a customer specified option, 1S of the
possible graphic codes (H'80' to H'8F') may
be used to generate the special graphic
characters illustrated in figure 3. For each of
these characters, the vertical component
appears on the 04 output. The horizontal
component occurs on LH which is specified
by the customer. The vertical components
specified by CAO and CA2 are output for line
addresses zero thru LH and LH thru filleen,
respectively.

Graphics Logic
When the GM input is zero (low), the OCGG
operates in the character mode. When it is
one (high), it operates in the graphics mode.
In graphics mode, output data is generated
by the graphics logic instead of the ROM.
The graphics logic maps the latched character address (CAO thru CA7) to the outputs
(DO thru 09) as a function of line address
(LAO thru LA3). For any particular line address value, two of the CA bits are output:
CAO, CA2, CA4 or CAS is output on DO thru
04 and CA 1, CA3, CA5 or CA7 is output on
05 thru 09. The outputs are paired: When
CAO is output on DO thru 04, CA 1 is output
on 05 thru 09 and likewise for CA2-CA3,
CA4-CA5 and CAS-CA7.

Line Select Multiplexers
The ten line select multiplexers select ROM
data as specified by the line address translation ROM when GM=O, or graphics data
when GM= 1. The inputs to each multiplexer
are the nine line outputs from the ROM, an
output from the graphics logic and a logic
zero (ground).

Output Drivers
Ten output drivers with 3-state capability
serve as buffers between the line select
multiplexers and external logic. The 3-state
control input to these drivers is supplied
from the CA7 latch when GM=O. When
GM= 1, the outputs are always active.

A ROM within the graphics logic allows the
specific line numbers for which each pair of
bits is output to be specified by the customer. Figure 2 illustrates the general format for

GRAPHICS SYMBOLS-GENERAL FORMAT
UNEADDRE5S

LF=O-

,,-

CAO

CA'

CA'

CA3

}-~,

3-

4-

,,3-

}

GMWP'

4-

G~UP3

S-

5-

56-

,-

~
0-

CA.

CAS

}

6-

,6-

9-

'0-

CAS

CA'

}

OROUP 4

I......-DO -04'---'I-+-----D5 - 09----"'1

'0I

GROUP LINE AOOAESSES ARE SPECIFIED BY THE CUSTOMER

I

I

I

8QSS!l!l8~

I

1

1

I

I

~

3

EXAMPLE' CA7 - CAO = HiSS'
GROUP 1 SPECIFIED FOR LINES 0, 1, 2
GROUP 2 SPECIFIED FOR LINES 3, 4, 5
GROUP 3 SPECIFIED FOR LINES 6, 7, 8
GROUP 4 SPECIFIED FOR LINES 9, 10, 11
SPACE SPECIFIED FOR LINES 12, 13, 14, 15

Figure 2

2·4

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
Output Inhibit Control
The output inhibit control logic operates only
if GM=O. It causes the output of the line
select multiplexers to be logic zero if the
SCD input is high and CA6 and CAS of the
latched character address are 00. If the
SCD input is low, normal operation occurs.
(This feature is useful in ASCII coded applications to selectively disable character
generation for non-displayable characters
such as line feed, carriage return, etc.)

SC2670

SPECIAL GRAPHIC CHARACTERS
GENERAL FORMAT
10 X 18 CHARACTER BLOCK
LO

Line Address Latch
The line address latch is a 4-bit latch used
to store the line address (LAO-LA3). The
data is stored on the negative edge of the
LSTROBE input.

Line Address Translation ROM
This 32X 10 ROM translates the S-bit code
consisting of the 4 outputs from the line address latch and the descend control bit from
the ROM into a l-of-l0 code for the line
select multiplexers. Programming information provided by the customer specifies the
address which selects each line of ROM
data for both shifted and non-shifted characters. Thus, there are nine line addresses
which select ROM data for unshifted characters and nine addresses for shifted characters. These combinations are usually
specified by the customer in either ascending or descending order. For the remaining
14 codes (7 each for un shifted and shifted
characters), the translation ROM forces zeros at the outputs of the line select
multiplexers.

"5
THIN GRAPHIC FONTS FOR

This circuitry only operates if GM=O. When
GM= I, the line select multiplexers are
forced to select the outputs from the graphics logic.
Figure 4 shows an example of data outputs
where the customer has specified line 14 as
the first line for unshifted characters, line 11
as the first line for shifted characters and
line address combinations in descending
order.

CUSTOM PATTERN
PROGRAMMING INSTRUCTIONS
A computer-aided technique utilizing
punched computer cards is employed to
specify a custom version of the 2670. This
technique requires that the customer supply
Signetics with a deck of standard BO-column
computer cards describing the data to be
stored in the ROM array, the programmable
line address translation ROM, thin graphics
option, and the graphics line font translation
ROM.

DO

D4

DO

CA7 - CAO '" HEX 80 - HEX SF

80

.,

.2

.3

UJDJcarn
..
84

.

.7

.5

.9

88

SA

5JBJ@tE
.e

8D

BE

8F

Figure 3

Signetics

2·5

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

CUSTOMER SPECIFIED EXAMPLE
Y!!i

~
(')

~~

,.
,.

!II ><

"

r-

"'"

?'<

13

,~

r---

7'"

I

11

10

1

L-_____________________

(

()

(J

X

~mER~QAm

____________________

~

Figure 4

On receipt of a card deck, Signetics will
translate the card deck to a truth table using
the Signetics Computer Aided Design (CAD)
facility. The truth table and font diagrams
will then be sent to the customer for final
approval. On receipt of final approval,
Signetics will produce masks and proceed
with manufacturing.
Programming information can also be input
on TTY 7-level tape as card images. Each
card Image must be terminated with a carriage return-line feed. An EOT character
must signify the end of the data set.
Customer identification cards are always
labeled with a C in column 1. For customer
identification, four cards are required. Any
number of additional customer identification
cards are permitted. The following data
should be included:

CUSTOMER 10 CARD #2
COLUMN
1
2
3-70

71-80

DATA
C
blank
Customer contact
person name I
phone number
blank

CUSTOMER 10 CARD #3
COLUMN
1
2
3-70
71-80

DATA
C
blank
Customer address
blank

CUSTOMER 10 CARD # 1
COLUMN
1
2
3-g
10-14
15-70
71-60

2·6

DATA
C
blank
2670/CP
blank
Company name I
company part number
blank

CUSTOMER 10 CARD #4
COLUMN
1
2
3-70
71-80

DATA
C
blank
Customer cily, state,
zip code
blank

Signatlcs

CUSTOMER 10 CARD #5 THRU N
COLUMN
1
2
3-70
71-80

DATA
C
blank
Any information desired
blank

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

The following masking information cards must be included:

Mask Information Card # 1:
Shift and Nonshlft Character Translation Data
DATA

COLUMN

1-9
10
11
12
13
14
15
16
17

18
19
20
21
22
23
24
25
26
27-29
30-35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53-59
60'
61-64
65'
66-80

MASK INFORMATION CARD #2:
Graphics Translation Data
COLUMN

NONSHIFT=
Line address in hex which outputs the first font
word for nonshifted ROM fonts

1-14
15-17

Line address in hex which outputs the second
font word for nonshifted ROM fonts

18-19
20-23
24

,

third

,

25-29
30-45

fourth

,

fifth

,

sixth

,

seventh

,

46-80

eighth

DATA
THIN GRAPHICS=
YES or NOI6, where ~ = blank. Specifies whether graphics address hex 80 thru hex 8F will
select the special thin graphics font.
blank
HOR=
The line address in hex for the horizontal segments of line graphics fonts. Leave blank if columns 15 thru 17 are NO
blank
Graphics group number 1 or 2 or 3 or 4 or blank.
Columns 30 thru 45 correspond to line address
hex 0 thru hex F respectively. The group number specified in each column will cause the
graphics data generated by that group to be
output at the corresponding line address. A
blank specifies no data for that address.
blank

,

ninth
blank
SHIFT=
Line address in hex which outputs the first font
word for shifted ROM fonts
second

,

third

,

fourth

,

fifth

,

sixth

,

seventh

,

eighth

,
ninth
blank
o or 1
blank
o or 1
blank

NOTES
1 Column 60 specifies the font truth table hOrizontal for-

mal 0 specifies left to right prmting of DO thru 09 1
specifies 09 thru DO

MASK INFORMATION CARD #3 THRU #130:
ROM Font Data
COLUMN

1-2
3
4
5
6-8
9
10-12
13
14-16
17
18-20
21
22-24
25
26-28
29
30-32
33
34-36
37
38-40
41-80

DATA
Character address in hex (CA6 thru CAO)'
blank
S for shifted; N for nonshifted.
blank
Data for first ROM font word in hex (09 thru ~O).
blank
second
blank
1hird
blank
fourth
blank
fifth
blank
sixth
blank
seventh
blank
eighth
blank
ninth
blank

NOTe
• A separate card IS required for each character address
hex 00 thru hex 7F

2 Column 65 speclfles the font truth table vertical printout
formal 0 specIfies top to bottom printing of Ime address
hex 0 thru F 1 specifies hex F thru 0

Signetics

2·7

JANUARY 1982

MICROPROCESSOR DIVISION

SC2670

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
Imii"lI.i.i(i
Printouts

SAMPLE CARD DECK INPUT

Signetics will translate the card deck to the
following printouts to be submitted to the
customer for approval:

THIN GRAPHICS=YES

SlGN[TICS C

2670/CPIOOOPA

NONSHIFr=l, 2 • .5 ...

• A rapeat of all customer information.
• A separate font drawing for each of the
128 ROM characters and 256 graphics
fonts. The font drawings are positioned on
a 10 X 16 matrix as specified by the cus·
tomer's translation data.

HOR=7

2670 TE:ST RUN

t". 6.7. S.9

::'HIFT=3. 11.5. EO. 7.8.9. A. B

00 N 022 026 02A n32 OAA oe8 088 088 070

1+0 N 078 08,+ 082 nCA 08A 072 002 08'+ 078

01 N Ole 002 DOC 1'110 OBE 086 OF'8 088 088

'+1 NOlO 028 Ottl+ nS2 082 OFE

02 N Ole 002 DOC 010 DBE 050 020 050 088

1f2 N 03E 01+1+ 08'+ 0'+11- 03e Olt'+ 0811- 01+1+ 03£.

03 N DIE 002 ODE 002 09E 050 020 050 088

'+3 N 07S 08'+ 002 002 002 002 002 081+ 078

all- N DIE 002 ODE n02 DIE OF'8 020 020 U20

'+1+ N 03£ 0'+1+ 08'+ n8'+ 08'+ 084 081f Olfl+ 03E

05 N DIE 002 ODE 002 OGE 090

O~O

000 OED

0~2

082 OB2

11-5 N OFE 002 002 n02 03E 002 002 002 OFE

06 N DOc 012 DIE n12 092 050 030 050 090

11-6 N OF[ 002 002 n02 03( 002 002 002 002

07 NODE 012 ODE 012 ODE 010 010 010 OFD

1+7 N 018

OS~

002 002 002 OE2 082 Oe'+ 088

08 NODE 012 ODE 012 DEE 010 060 oeD 070

48 NOS.:! 082 082 n82 Of( 082 082 082 082

09 N 012 012 DIE 012 012 OF'8 020 OZG 020

'+9 N 07C 010 010 010 010 010 010 010 07C

OA N 002 002 002 olE OFO 010 070 010 010

itA N OED 040 0'+0 oltO 01+0 0'+0 042 042 03C

DB N 022 022 022 011+ 008 OF8 ()20 020 020

48 N 082 042 022 n12 aDA 016 0'2 0,+2 082

on

DC N DIE 002 00£ 002 OF2 010 070 010 010

4C N 002 002 002 n02 002 002 002 002

00 N OlC 002 002 002 07C 090 PO 050 0'90

'+0 N 082 oe6 OAA n'92 0'92 082 082 082 082

DE N OlC 002 DOC 010 06E 09() 0'30 0'90 0&0

'+E N 082 082 086 n8A 092 OA2 oe2 082 082

OF N OlC 002 DOC 010 DEE

O~O

01+0 01+0 OED

10 NODE 012 012 012 DOE 010 010 010 OFO
11 NODE 012 012 012 0'+( 060 01+0 01+0 oro

12 NODE 012 012 '112 06E 090

O~O

II-F N 038 0'+'+ 082 n82 082 08o! 082 01+'+ 038
50 N 01[ 082 082 n82 07E 002 002 002 002
51 N 0313 01+'+ 082 n82 082 092 !lA2 01+'+ 088

020 OFO

52 N 07E 082 082 082 07£. 012 022 042 08.:!

13 NODE 012 012 n12 ObE 080 060 oeD 070

53 N 078 084 002 n04 038 040 080 042 03e

III- NODE 012 012 n12 OI+E 060 050 OF8 040

51+ N OFE 010 010 nlO 010 010 ulO el0 CIO

15 N 012 016 OlA 012 092 050 030 050 0'30

55 N 082 082 082 n82 082 082 0132

16 N Olc 002 oDe 310 08E 050 U20 020 020

56 N 082 082 082 n!flt 044 028 0'8 010 010

17 N DIE 002 ODE 002 07[ 090 C70 neJo 070

57 !II 08;1: 082 082 n82 082 092 ,)q::,> OAII 04'+

18 N Ole 002 002 002 Ole 090 l'PO liDO

58 N 082 082 0'+4 n28 010 028 0'+1+ 082 082

n

N OlE 002 ODE 002 OlE 088 008 OAIl Ollll

59 N 082 082 01+'+ 028 010 010 010 010 010

lA N OlC 002 DOC 1110 07E 090 070 0'90 070

SA N OF( 080 01+0 020 010 008 00,+ 002 OF[

''"

IB N DIE 002 OO( n02 Ol( 0(0 010 010 OED

58 N 07C 001+ 00'+ 00,+ 001+ 00'+ 001+ DOli- 07C

lC N Ol( 002 OO( 002 O(l 010 Of-O 080 070

!5C N 000 002 00,+ nOa 010 020 0,+0 080 000

10 N Ole 002 OlA 012 DEC 010 060 080 070

50 N 07e 0,.0 0"0 n"o 0'+0 0'+0 040 0'+0 07C

IE N OO( O1l ODE 1I0A OFl 010 060 080 070

5E NOlO 038 051+ 010 010 010 010 010 010

IF N 012 012 012 012 DEC 010 060 080 070

SF N 000 000 008 00" OFE 00,. 008 000 000

20 N 000 000 000 000 000 000 000 000 000

60 N 018 018 010 020 000 000 000 000 000

21 N 010 010 010 010 010 000 000 010 010

61 N 000 000 000 03C 01+0 01C 011-2 0"2 OBC

22 N 028 028 028 028 000 000 000 000 000

62 N 002 002 002 03A 0'+6 0'+2 0'+2 011-6 03tt

23 N 028 028 OF( 028 02B 028 OF( 02a 028

63 N 000 000 000 03C C,+2 002 002 0,+2 03e

2 .. N 028 OFe 02A 02A 07C OAS 01\8 07E 028

6" N 01+0 O~O 0'+0 oSC 062 01+2 0'+2 062 OSC

25 N 001+ 08A 01+11- 020 010 008 Oil-II- OA2 0'+0

65 N 000 000 000 03C 0'+2 07E 002 002 03e

26 N DOC 012 012 DOC OOC 012 OAl 0,+2 OBC

66 N 030 01+8 008 008 03E 008 008 008 008

27 N 018 018 008

2·8

0 .. /16179

111122223333'+l+ljll

nO~

000 000 000 000 000

67 S 000 OSC 062 n,+2 062 OSC 01+0 011-2 03e

28 N 020 010 008 n08 008 008 ceo 010 020

68 N 002 002 002 03A 046 0'+2 042 0'+2 0'+2

29 N OOa OlD 020 020 020 020 020 010 OOa

6'iI N 000 010 000 018 010 010 010 010 038

2A N 000 010 05'!- n38 OF( 038 O!SI+ 010 000

&A S 000 060 01+0 n'!-O 011-0 01t0 01+0 01+1+ 038

28 N 000 010 010 010 OF( 010 010 010 000

68 N 002 002 002 n22 012 OOA 016 022 042

2C S 000 000 000 000 000 018 018 008 001+

6C N 018 010 010 010 010 010 010 010 038

20 N 000 000 000 000 OFE 000 000 000 000

60 N 000 000 000 06A 0'96

2£ N 000 000 000 000 000 000 000 018 {l18

6( N 000 000 000 03A 0'+6 011-2 01+2 011-2 Olt2

0~2

0~2

0~2

0~2

0'2

2F N 000 080 01t0 n20 010 008 OOtt 002 000

6F N 000 000 000 03C 042

30 N 038 01+1t OC2 oA2 092 08A 086 04'+ 038

70 S 000 03A 01+6 Olt2 011-6 03A 002 002 002

31 N 010 018 Oh 010 010 010 010 010 07C

71 S 000 OSC 062 011-2 062 OSC 0'+0 0 .. 0 0'+0

0'+2 01+2 03e

32 N 07C 082 080 0'+0 038 00'+ 002 002 OF(

72 N 000 000 000 03A

0~6

002 002 002 002

33 N 07C 082 080 080 070 080 080 082 01C

73 N 000 000 000 o3C

O~2

OOC 030 0'+2 03C

3tt N Otto 060 OSO nlf8 Oillf OFE 01f0 0'+0 0110

7'1- N gOO 008 008 {lIe 008 008 008 01+8 030

35 N OFt 002 002 n02 07E oeD 080 082 01C

7S N 000 000 000 nll-2 0'+2 0,+2 042 062 OSC

36 N 078 081f 002 002 07A 086 0132 082 07C

76 N 000 000 000 nlt'!- 011-1+

31 N OFF:: 080 080 01+0 020 010 008 DOli- 002

77 N 000 000 000 082 082 092 092 0'92 06C

38 N 07c 082 082 0'+'1 038 0'+11- 082 082 07C

78 N 000 000 000 0'+2 02'+ 018 018 021+

39 N 07C 082 082 OC2 OBC 080 060 0'12 03C

79 S 000 01+2 011-2 nll-2 062 05C 0"0 01+2 03C

0~4

0'+1+ 028 010
0~2

3A N 000 000 000 018 018 000 000 018 018

7A N 000 000 000 n7E 020 010 008 00,+ 07E

38 SODa 018 018 nOD 000 016 018 008 00'+

78 N 030 008 008 008 001+ 008 008 008 030

3C N 020 010 008 00'1 002 00'1 008 010 020

7C NOlO 010 010 000 000 000 010 010 010

30 N 000 000 000 nFE 000 000 QFE 000 000

70 N 018 020 020 020 0'+0 020 020 020 016

3E N 008 010 020 0'10 080 01f0 020 010 008

7E: N 000 000 000 noc 092 060 000 000 000

3F N 07C 082 082 n80 060 010 010 000 010

7F N OU 05,+ OAA

Signetics

05~

OAA 05'+ OAA 05,. OAA

JANUARY 1982

MICROPROCESSOR DIVISION

SC2670

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

l:tQii"ii,t·'¢1
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Supply vollage
Operaling ambienllemperalure2
Siorage lemperalure
All vollages wilh respecllo ground 3

RATING

UNIT

6.0
010 +70
-6510 +150
-0.310 +6.0

V
°c
°c
V

NOTES
1 Stresses above those hsted under Absolute MaXimum Ratings may cause permanent
damage to the deVice This 18 a stress rating only and functional operation of the deVice
at these or any other condition above those mdlcated In the operation section of thiS
specification 18 not Implied
2 For operating at elevated temperatures. the deVice muat be derated based on + 150"C
maximum Junction temperature and thermal retustsnce of 60"C/W Junction to ambient
(ceramic package)
3 This product Includes circuitry specifICally deSigned for the protection of Its Internal
deVices from the damagmg effects of excessive static charge Nonetheless It IS
suggested that conventional precautions be taken to aVOid applymg any voltages
larger than the maxima

DC ELECTRICAL CHARACTERISTICS TA = O°C 10 70'C, VCC = 5.0V ± 5%

1.2.3

LIMITS
PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

VIL

Inpul low vollage

0

0.8

V

VIH

Inpul high vollage

2.0

VCC

V

VOL

Oulp"1 low vollage

0

0.45

V

VOH

Oulpul high vollage

2.4

VCC

V

IlL

Inpul leakage currenl

10

p.A

10L

Oulpul leakage currenl

ICC

Supply currenl

CIN

Inpul capacilance

COUT

Oulpul capacilance

AC CHARACTERISTICS TA

= 1.6mA
10 = -1001tA
10

VIN = 0 10 4.25V
Vo = 0.410 4V
VCC

= 5.25V

50

All olher pins grounded

= O°C 10 +70'C, VCC = 5V ±

5%

±10

p.A

100

mA

10

pF

15

pF

1.2.3

TENTATIVE LIMITS
PARAMETER

Min

Max

UNIT

IWS

Sirobe pulse widlh

100

ns

lAS

Address selup

50

ns

IAH

Address hold

25

ICA

Characler seleci access

300

ns

ILA

Line select access

500

ns

ISEL

Chip selecl delay'

250

ns

IDES

Chip deseleci delay'

200

ns

ISC

Special characler blank I unblank lime

1

p's

ns

NOTES
Parameters are valid over operatmg temperature range unless otherwise specified
All voltage measurements are referenced to ground All time measurements are at 50%
level for mputs and at the 0 BV or 2 OV level for outputs Input levels are 0 45V and

2.V
3 TYPical values are at +25°C. typical supply voltages and typical proceSSing
parameters
4 Test conditions CL = 100pF and 1 TTL load

Signetics

2·9

JANUARY 1982

MICROPROCESSOR DIVISION

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

'mu", ..t.",
TIMING DIAGRAMS

C

_ ' _ '_'LA_

CAS,CAO

NOTE
1 WHEN GM= 1, SCD INPUT IS INACTIVE

CSTROBE

CAO-CA7,OM

___c

CSTROBE

---I~

00-00 _ _-::;OlJ11!UTB:;;,,;,;;:,;TIII-II=t:;,;:'TE=-_ _

NOTE
1 CA7 OPERATES AS OUTPUT ENABLE ONLY IN CHARACTER MODE (GM=O)

2·10

Signetics

-

.... -1

0lJ11!UTB...... } - -

SC2670

JANUARY 1982

MICROPROCESSOR DIVISION

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

l:mil"JI,t.!lj

=

Signetics

2·11

2

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
l81ii"jj,(.I'I

2·12

Signetics

SC2670

MICROPROCESSOR DIVISION

JANUARY 1982

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

SC2670

1#1 11 "",1.1,,

=

Signetics

2·13

2

MICROPROCESSOR DIVISION

JANUARY 1962

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)

'm""n,[.I"

2·14

Signetics

SC2670

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC)
DESCRIPTION

FEATURES

The Signetics 2671 Programmable Keyboard and Communications Controller
(PKCC) is an MOS LSI device which provides a versatile keyboard encoder and an
independent full duplex asynchronous communications controller. It is intended for use
in microprocessor based systems and provides en eight bit deta bus interface.

• Keyboard Interface
Contact or capacitive kayboard
Up to 128 key. on .n 8 X 16 matrix
Encoded or unencoded operation
Four code level. per key
Latched key optlon- ••p.rat.
d.press .nd r.I•••• code.
Programmabl. acan rata .nd debounc.
tim.
Progr.mm.bl. rollov.r mod••
Progr.mm.ble .uto-r.p.at for
••I.cted k.ys
Ton. output-two fr.qu.ncl.s
• Asynchronous communication
Int.rfac.
Int.rn.1 baud rat. g.ner.tor-16 rates
Full dupl.x op.r.tlon
D.t.ctlon of stert .nd .nd of br•• k
Programm.bl. br••k g.neratlon
Progr.mmable ch.r.ct.r p.r.m.t.rs
Auto-acho .nd m.lnt.nsnce loopb.ck
modes
• PolI.d or Int.rrupt op.r.tlon
• Int.rrupt priority controll.r .nd vector
g.n.rator
• Operat.s dlr.ctly from cryst.1 or
.xt.rn.1 clocks
• TTL compatlbl.
• Slngl. +5 volt pow.r .upply
• 40 pin dual In-line packag.

The keyboard encoder handles the scsnning, debounce, and encoding of a keyboard
matrix with a maximum of 128 keys. It provides four levels of key encoding corresponding to the separate SHIFT and CONTROL input combinations. Four keyboard
rollover modes can be programmed includIng provisions for up to 16 latched keys.
Control outputs are provided for interfacing
with contact or capacitive keyboards. An
eight bit keyboard status register provides
status information to the CPU.
The receiver section of the communications
controller accepts serial data from the RxD
pin and converts it to parallel data characters. Simultaneously, the transmitter section
accepts parallel data from the data bus end
outputs serialized data onto the TxD pin. Received data is checked for parity and framing errors, and break conditions are flagged.
Character lengths can be programmed as 5,
6, 7, or 8 bits not Including parity, start or
stop bits. An internal baud rate generator
(BRG) with 16 divider ratios can be used to
derive the receive and I or transmit clocks.
The BRG can accept an external clock or
operate directly from a crystal. An eight bit
communications status register provides
status Information to the CPU.
The PKCC has an interrupt mask register to
selectively enable certain keyboard and
communications status bits to generate in·
terrupts. Priority encoded interrupt
vectoring is available. Upon receipt of an
interrupt acknowledge, an interrupt vector
will be output on 00-07 reflecting the source
of the interrupt. The interrupt source can
also be read from an interrupt status register.

PIN CONFIGURATION

Vee
AxO

.,0
XTAL2/BRClK
XTAL1

Axe
TXe

.,••
xAO

M

REPEAT

~

!lRIrT

liii

el5IITIIl![

WIi

TONE

lIlfA

xAET

07

DO

DO

01

os

D.
d.

IIITII

Vss

O'

mTII

APPLICATIONS
•
•
•
•
•

CRT t.rmlnal.
Hard copy t.rmlnals
Word proc.sslng syst.ma
Data .ntry t.rmlnals
Small busln.ss comput.rs

FUNCTIONAL DESCRIPTION
The PKCC consists of six major sections
(see block diagram). These are the transmitter, receiver, timing, operation control,
keyboard encoder, and a priority encoded
int.rrupt control unit. These sections communicate with each other via an Internal
data bus and an internal control bus. Th.
internal data bus interfaces to the
microprocessor data bus via a bidir.ctional
data bus buff.r.

ORDERING CODE
PACKAGES

SC2671

COMMERCIAL RANGES
VCC= 5V ±5%, TA= O"C to 7O"C

Ceramic DIP

SC2671 ACSI40

Plastic DIP

SC2671 ACSN40

Signetlcs

Operation Control
This functional block stores configuration
and operation commands from the CPU and
generates appropriate signals to various internal sections to control the overall device
op.ration. It contains read and write circuits
to permit communications with the
microprocessor via the data bus and contains mode registers KMR and CMR, the
command d.coder, and status registers
KSR and CSR. Details of operating mod.s
and status information are pr.s.nted In the
Operation section of this data sheet. The
regist.r addressing is sp.cified in table 1.

Timing
The PKCC contains a baud rate generator
(BRG) which is programmable to accept .xternal transmit or receive clocks or to divide
an external clock to perform data communications. The unit can g.nerat. 16 baud
rates, any of which can be s.l.ct.d for full
duplex operation. Th. external clock to the
baud rate generator can be appli.d directly
to the XTAL2 input (see figure 21) or can be
generated internally by connecting a crystal
across the XTAL 1, XTAL2 Input pins. The
clock input is also utilized by the keyboard
encoder section. Thus, a clock must b. provided even if external transmitter and receiver clocks are used.

2·15

2
====

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE KEYBOARD Ik COMM CONTROLLER (PKCC)

SC2671

'PI""II,I.",
PIN DESIGNATION
PIN NO.

TYPE

NAME AND FUNCTION

00-07

MNEMONIC

16·19,
23·26

1/0

Data Bus: 8-bitthree-atate bidirectional data bus. All data, command and atatustransfers are
msde using this bua. DO is the least aignificant bit; 07 ia the moat significant bit.

AO·A2

31·33

I

RD

29

I

Read Strobe: When low, gates the selected PKCC register onto the data bus if CE ia alao low.

WJ!i

28

I

Write Strobe: When low, gates the contenta of the data bus into the selected PKCC register if
CE is also low.

CE

30

I

Chip Enable: When high, places the 00-07 output drivers in a three-state condition. If CE is
low, data transfers are enabled in conjuction with the RD and WR inputs.

INTR

22

0

Interrupt Reque.t: Several conditions may be programmed to requeat an interrupt to the
CPU. It ia an active low open-drain output. Thia pin will be inactive aiter power on reaet or a
maater reaet command.

INTA

27

I

Interrupt Acknowledge: Used to indicate that an interrupt request has been accepted by the
CPU. When INTA goes low, the PKCC outputs an 8-bit address vector on 00-07 corresponding
to the highest priority interrupt currently active.

XINTR

21

I

External Interrupt: An active low external interrupt input to the PKCC interrupt priority
resolver.

TxC

34

1/0

Transmitter Clock: The function of this pin depends on bit 7 of the baud rate control register
(BRR7). If external transmitter clock is aelected (BRR7 0), it is an input for the transmiller
clock. If internal transmitter clock is aelected (BRR7
1), this pin is an output which ia a
multiple of the actual baud rate (1 X, 16X) as selected by BRR5. The data is transmitted on the
falling edge of TxC. It is an input after power on and aiter master reset or communications
reaet commands.

RxC

35

1/0

Receiver Clock: The function of this pin depends on BRR6. If external receiver clock is
selected (BRR6 0), it is an input for the receiver clock. If internal receiver clock is selected
(BRR6
I), this pin is an output which is a multiple of the actual baud rate (IX, 16X) as
selected by BRR4. The received dsta is aampled on the rising edge of RxC. It ia an input aiter
power on and after master reset or communications reset commands.

Address Unes: Used to select internal PKCC registers or commands.

=
=

=

=

TxD

38

0

Transmitter Data: This output is the transmitted aerial data; the least significant bit is
transmitted first. This pin is high after power on reset or a reset command that affecta the
tranamitter.

RxO

39

I

Receiver Data: This input is the serial data input to the receiver. The least significant bit ia
received first.

36,37

I

Connections for Crystal: Provides an on-chip clock generator for the internal baud rate
generator and the keyboard interface logic. If an external clock is provided, use XTAL2 as the
clock input. See figures 20 and 21.

XTALI
XTAL2/BRCLK

All timing parametera such as keyboard scan time, tone frequency, and baud rate assume a
clock input at the specified BRG input frequency. If this frequency is different, the timing
parameters will vary proportionately.
KRO-KR2

10-8

0

Keyboard Row Scan: Decoded externally; selects one of eight rows.

KCO-KC3

7-4

0

Keyboard Column Scan: Decoded externally; selects one of 16 columns.

KRET

15

I

Key Return: An active high level indicates that the key being scanned is closed.

SHIFT

12

I

SHIFT Key: Active low input from the SHIFT key. The combination of SHIFT and CONTROL
inputs select one of four possible codes from the internal key encoding ROM.

CONTROL

13

I

CONTROL Key: Active low input from the CONTROL key. The combination of SHIFT and
CONTROL inputs select one of four possible codes from the internal key encoding ROM.

2-16

Signetlcs

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC)

SC2671

'w""n"·"t
PIN DESIGNATION (Cont.)
REPEAT

11

I

REPEAT Key: Active low input from the REPEAT key. Causes the key depression currently
active to be repeated at a rate of approximately 15 times per second.

KCLK

3

0

Keyboard Clock: High frequency (approximately 400 kHz) output used to scan capacitive
keyboards.

KDRES

2

0

Key Detect Reset: Resets the analog detector before scanning a key. Used for capacitive
keyboards.

HYS

1

0

Hysteresis Output: Sent to the analog detector for capacitive keyboard applications. A low
indicates the key currently being scanned has been recognized on previous scan cycles.

TONE

14

0

Square Wave Output: Used for tone generation.

VCC

40

I

+5V power supply.

VSS

20

I

Ground.

Receiver
The receiver accepts serial data on the RxD
pin, converts this serial input to parallel format, checks for break conditions, framing
and parity errors, and loads an "assembled"
character in the receive holding register for
access by the CPU.

Transmitter
The transmitter accepts parallel data loaded by the CPU into the transmit holding register and converts It to a serial bit stream
framed by the start bit, calculated parity bit
(if specified), and stop bites). The composite serial stream of data is transmitted on
the TxD output pin.

Keyboard Encoder
The keyboard encoder provides ancoded

CE

A2

AI

AO

RD/WR

1
0
0
0

X
0
0
0

X
0
0
0

X
0
0
1

X
WR
AD
AD,WR

0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
1

1
1
1
1
0
0
1
1
1

0
0
1
1
0
1
0
1
1

WR
AD
WR
AD
AD,WR
RD,WR
AD
RD

Wi!i

scanning signals for a matrix keyboard. Key
depressions are detected on the KRET input. The debounced and verified key codes
(or matrix addresses) are loaded into the
key holding register for access by the CPU.
Figures 1 and 2 illustrate the PKCC interface
to contact and capacitive keyboards, respectively.

Interrupt Control
The interrupt controller unit contains a soliware programmable interrupt mask register
which selactively enables status conditions
from the keyboard encoder and communication controller to generate interrupts. The
intarrupts are priority encoded and individually generate an eight bit vector which is
output on the data bus in response to a CPU
interrupt acknowledge on the INTA input pin.

FUNCTION
Three-state data bus
Reset command (see table 6)
Read interrupt status register (lSR)
Read/write communications mode register
(CMR)
Write transmit holding register (TxHR)
Read receiver holding register (RxHR)
Write baud rate mode register (BRR)
Read communications status register (CSR)
Read/write interrupt mask register (IMR)
Read/write keyboard mode register (KMR)
Read keyboard holding register (KHR)
Read keyboard status register (KSR)
Miscellaneous commands (see description)

NOTE
x - don't care.

Table 1.

2671 REGISTER ADDRESSING

Signetics

OPERATION
Keyboard Encoder
The keyboard is continuously scanned by
KCO-KC3 and KRO-KR2 which are decoded
externally to handle 128 possible keys (see
figures 1 and 2). KCO-KC3 select one of 16
columns and KRO-KR2 multiplex the eight
row return lines into the KRET pin.
Debouncing is accomplished by remembering a 1 state at the KRET pin when a key is
being addressed and verifying it one scan
later. Once the key is verified, a key code is
loaded into the keyboard data register
(KDR). " the keyboard holding register
(KHR) is empty, the contents of the KDR will
be transferred to the KHR immediately; if the
KHR IS full (i.e., the CPU has not read the
previous key code), the transfer will be held
off until the KHR is read. The data transfer to
the KHR causes keyboard data ready
(KRDY) to be set in the keyboard status
register.
For capacitive keyboards, the high frequency output KCLK can be used to gate the
column scan to the keyboard (see figure 2).
The key detector reset (KDRES) output
resets the analog detector prior to scanning
each key location. The output from the analog multiplexer is sensed and then latched in
the analog detector. The HYS output controls the sense level. A 0 will lower the
sense level causing hysteresis, and a 1 will
raise the sense level with no hysteresis.
The REPEAT input enables the keyboard
logic to recognize any key repeatedly, 15
times per second. Additionally, certain keys
can be programmed to repeat automatically
if depressed for more than one-half second.
A square wave is output on the TONE pin
when the CPU issues a ring tone command
to the PKCC.

2·17

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC)

SC2671

'am",,"·i-"i
BLOCK DIAGRAM

.1)I

080-7

DATA

K

BUS BUFFER

KEYBOARD ENCODER
KCLK

t

CONTROL

1

OPERATION CONTROL.

t------<

Ali
eMR

VIR

2 }

-

XINTR

I.

KMR

a;;

I

KEYBOARD
SCANNER &

KSR

ENCODER/DECODER

I

KDRES

KCO-3

CSR

COMMAND DECODER

KRET

KRO-2

,-

r------i
I
I
I
I

~

4X128X8
READ-ONLY

MEMORY

!------i

INTERRUPT CONTROL

•

VECTOR GENERATOR

[:J

urn;

I

MODE & TIMING

KEYBOARD
DATA
REGISTER

~

I
I

Vec_
GND_

TIMING

T,C

R,C

I
I

I
I

BAUD RATE
GENERATOR

BAUD RATE
CONTROL

REGISTER

-

TRANSMITIER

-"

XTAL2

>--

f

TONE

GENERATOR

--y

XTAL1! BRCLK

KEY HOL.DING
REGISTER

TRANSMIT
HOLDING REGISTER
TRANSMIT
SHIFT REGISTER

r
RECEIVER

INTE';;uP';

RECEIVE
HOLDING REGISTER

TIMING

RECEIVE
CONTROLS

2·18

Signetics

SHIFT REGISTER

1
I

TONE

MICROPROCESSOR DIVISION

JANUARY 1982

SC2671

PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC)

'm"..lIel·'N
the code in the KDR is transferred to the
KHR and the KRDY status bit is set
(KSRO).

CONTACT KEYBOARD INTERFACE

N-Key Rollover With Latched Keys: This
mode is the same as regular N-key
rollover, except that the keys which are
assigned to row a of the keyboard matrix
(KR2-KRO = 000) produce a code both
when depressed and when released. The
codes are independent of the states of
the inputs at SHIFT and CONTROL. If one
or more of the latched keys are depressed when the keyboard is enabled
(after a keyboard reset), the corresponding codes will be sent out as the
keys are scanned and debounced. Note
that simultaneous latched keys will not
set KERR (KSR 1) and that latched keys
will not be auto-repeat and will not be
affected by the REPEAT input.

KRET

)I

KR2-0

DIGITAL MULTIPLEXER

8 ROWS

I

PKCC

r---KC3-0

1 OF 16

16

DECODE

COLUMNS

~

'-CONTACT
KEYBOARD
MATRIX

Figure 1

Two-Key Rollover: The first key code is
loaded into the KDR immediately and the
second code is loaded only after the first
key is released. Simultaneous keys will
set KERR (KSR1). If three or more keys
remain closed at any given time, the
KERR bit will also be set. All keys must
then be released before the next KRET
will be processed.

CAPACITIVE KEYBOARD INTERFACE
ANALOG
DETECTOR
KRET

HV!
KDRES

J'f
)I

KR2-0

ANALOG MULTIPLEXER

I

BROWS

PKCC

;---KeLK

1 OF 16

16 COLUMNS

DECODE
KC3-0

~

~
CAPACITIVE

KEYBOARD

MATRIX

Two-Key Inhibit: All keys must be released between keystrokes; otherwise,
KERR (KSR1) will be set.
Bit KMR4 specifies the key encoding mode.
Each key is assigned four S-bit codes, corresponding to the states of the SHIFT and
CONTROL inputs. If the encoded mode is
programmed, the row/column address of
the detected key is used to load one of the
four key codes into the KDR. See table 2 for
key code assignments. If the non-encoded
mode is programmed, the row / column address is loaded directly into the KDR with
the following format:

Figure 2
KDR

Keyboard Mode Register
Operating modes are selected by programming the keyboard mode register (KMR),
whose format is illustrated in figure 3.
Bit KMR7 is used for testing the device. For
normal operation, this bit should always be
written to a O.

Bits KMR6-KMR5 select the rollover modes
for keyboard processing:
N-key Rollover: In this mode, the code
corresponding to each key depression is
loaded into the KDR as soon as that key
is debounced, independent of the release of other keys. Two or more closures occurring within one scan cycle
are considered to be simultaneous,
which will set keyboard error in the keyboard status register (KSR1). As soon as
the keyboard holding register is empty,

Signetics

[TLL

KC3, KC2. KC 1. KCD

"0" for momentary keys

"1" for latched keys release
"0" for latched keys depress

2·19

2

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE KEYBOARD &COMM CONTROLLER (PKCC)

SC2671

'Wn"ii,l.iu
ROW (KR2-KRO)
COLUMN
(KC3-KCO)

a

1

2

3

4

S

6

7

8

9

A

8

C

0

E

F

2

1

0

3
09
09
09
09

I

11
11

DCl
DCl

51
71

0

17

ET8
ET8

CO
DO
CO
DO

lB
lB
lB
lB

El
Fl
El
Fl

Cl
01
Cl
01

21
31
21
31

E2
F2
E2
F2

C2
02
C2
02

22
32
22
32

E3
F3
E3
F3

C3
03
C3
03

23
33
23
33

E4
F4
E4
F4

e4
04
C4
04

24
34
24
34

$

1

I
1

"

2

"2
#
3

#
3
4

$
4

ES
FS
E5
F5

CS
OS
C5
05

25
35
25
35

%

E6
F6
E6
F6

C6
06
C6
06

26
36
26
36

&

E7
F7
E7
F7

C7
07
C7
07

27
37
27
37

E8
F8
E8
F8

C8
08
C8
08

28
38
28
38

(

E9
F9
E9
F9

C9
09
C9
09

29
39
29
39

)

EA
FA
EA
FA

CA
DA
CA
DA

37
37
37
37

E8
F8
E8
F8

C8
DB
CB
08

EC
FC
EC
FC

5

%
5
6

&
6
7
7
8

(
8

7

6

a

=
•=

2A
3A
2A
3A

.

IF
IF
7F
5F

US
US
DEL

lA
lA
5A
7A

01
01
41
61

SOH
SOH
A

18
18
58
78

,

3D
20
3D
20

13
13
53
73

DC3
DC3
S

s

03
03
43
63

ETX
ETX
C
c

IE
IE
7E
5E

ENO
ENO
E

04
04
44
64

EDT
EDT
0
d

16
16
56
76

SVN
SVN
V

FS
FS

v

lC
lC
7C
5C

DC2
DC2
R
r

06
06
46
66

ACK
ACK
F
f

02
02
42
62

STX
STX
8
b

06
08
08
08

BS
BS

14
14
54
74

DC4
DC4
T
t

07
07
47
67

8EL
8EL
G
9

DE
DE
4E
6E

SO
SO
N
n

10
10
50
70

19
19
59
79

EM
EM
V
y

08
08
48
68

8S
8S
H
h

00
00
40
60

eR
eR
M

15
15
55
75

NAK
NAK
U

OA
OA
4A
6A

LF
LF

J

3C
2C
3C
2C

08
08
48
68

VT
VT
K
k

05
05
45
65
12
12
52
72

09
09
49
69

q

W
w

.

"HT

,

HT

,

a

,Z
CAN
CAN
X

30
30
30
30

+
;
+;

US
US
US
US

• HT
• HT

SUB
SUB

2B
3B
2B
38

IF
IF
IF
IF

17
57
77

HT
HT

0
0
0

·-

RS
RS
~

I

18
18
78
58

:

\

8S
8S
8S
• 8S

00
00
60
40

NUL
NUL

@

09
09
09
09

• HT
• HT

<
<

7F
7F
7F
7F

DEL
DEL
DEL
DEL

20
20
20
20

• SP
• SP

3E
2E
3E
2E

>
>

OA
OA
OA
OA

LF
LF
LF
LF

08
08
08
08

• VT
• VT

FF
FF
L

?
/

00
00
00
00

CR
CR
eR
CR

OA
OA
OA
OA

0
0
0
0

AD
BO
AD
80

A6
86
AS
86

J

m

9

0

,

7
7
7
7

34
34
34
34

4
4
4
4

31
31
31
31

1
1
1
1

30
30
30
30

38
38
38
38

8
8
8
8

35
35
35
35

5
5
5
5

32
32
32
32

2
2
2
2

2E
2E
2E
2E

AI
81
AI
81

A7
87
A7
87

CC
DC
CC
DC

39
39
39
39

9
9
9
9

36
36
36
36

6
6
6
6

33
33
33
33

3
3
3
3

8F
AF
9F
8F

A2
82
A2
B2

A8
88
A8
88

ED
FD
ED
FD

CD
DO
CD
DO

90
90
90
90

93
93
93
93

82
82
82
62

95
95
95
95

A3
83
A3
83

A9
89
A9
B9

EE
FE
EE

91
91
91

FE

CE
DE
CE
DE

91

80
80
80
80

84
84
84
84

61
81
81
81

A4
B4
A4
B4

EF
FF
EF
FF

CF
OF
CF
OF

92
92
92
92

94
94
94
94

83
83
83
83

96
96
96
96

T

Th,. row contaon. the 'atched
keys when that mode 18 selected

(KMRe. KMR5

I

CONTROL,
(Pin 13 0)

=

""1:

XX
XX

XX
XX

= 00)
Key code. on he,

TABLE 2.

------.J

.

..

Vyy
yyy
yyy
YVY

tV

/

?

,

·

SP
SP

VT
VT

LF
LF
• LF
• LF

·

AA
AA

------

BA
AB
88
A8
88

·

ml'f (Pon
~

~

HT
HT

8A

A5
85
A5
B5

I

I

1

12

·

··

= 0)

Latched key code fa r release

Latched key code for depres

ASCII equivalent 
t ..

I¢==I~~~~;~~~~~::I: : :t-='~ =' '_ TROSE~
j

LJ
""'. .
L_____~_"__" __~r---IL___________~_ooo_'_:_~~____________~
rux,"

2-36

CH...

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

SC2672

':tA"..",I_"j
ORDERING CODE
COMMERCIAL RANGES
VCC = SV ±S%, TA = O'C to 70'C

PACKAGES
Ceramic DIP

SC2672C4140

Plastic DIP

SC2672C4N40

2

PIN DESIGNATION
PIN NO.

TYPE

NAME AND FUNCTION

AO-A2

MNEMONIC

37-39

I

Address Lines: Used to select PVTC internal registers for read / write operations and for

DO-D7

8-15

1/0

8-Blt Bidirectional Three-State Data Bus. Bit 0 is the lSB and bit 7 IS the MSB. All data,
command, and status transfers between the CPU and the PVTC takeplace over this bus.
The direction of the transfer is controlled by the RD and WR Inputs when the CE input IS
low. When the CE input is high, the data bus is in the three-state condition.

RD

1

I

Read Strobe: Active low Input. A low on this pin while CE is low causes the contents of the
register selected by AO-A2 to be placed on the data bus. The read cycle begins on the
leading (falling) edge of RD.

WR

3

I

Write Strobe: Active low input. A low on this pin while CE is also low causes the contents
of the data bus to be transferred to the register selected by AO-A2. The transfer occurs on
the trailing (rising) edge of WR.

CE

2

I

CClK

16

I

Chip Enable: Active low input. When low, data transfers between the CPU and the PVTC
are enabled on DO-D7 as controlled by the WR, RD, and AO-A2 inputs. When CE is high,
the PVTC is effectively isolated from the data bus and DO-D7 are placed in the
three-state condition.
Character Clock: Timing signal derived from the video dot clock which is used to synchronize the PVTC's timing functions.

HSYNC

19

0

Horizontal Sync: Active high output which provides video horizontal sync pulses. The
timing parameters are programmable.

VSYNC/CSYNC

18

0

Vertical Sync/Composite Sync: A control bit selects either vertical or composite sync
pulses on this active high output. When CSYNC is selected, equalization pulses are
included. The timing parameters are programmable.

BLANK

17

0

Blank: This active high output defines the horizontal and vertical borders of the display.
Display control signals which are output on DADD3 thru DADD 13 are valid on the trailing
edge of BLANK.

CURSOR

7

0

Cursor Gate: This active high output becomes active for a specified number of scan lines
when the address contained In the cursor registers match the address output on DADDO
thru DADDI3. The first and last lines of the cursor and a blink option are programmable.

35

0

Interrupt Request: Open drain output which supplies an active low interrupt request from

commands.

INTR

any of five maskable sources. This pin is inactive after power on reset or a master reset

command.
lPS

36

I

Light Pen Strobe: Positive edge triggered input indicating a light pen hit. Causes the
current value of the display address to be strobed into the light pen register.

CTRll

4

1/0

Handshake Control 1: In independent mode, provides an active low write data buffer
(WDB) output which strobes data from the interface latch Into the display memory. In
transparent and shared modes, this is an active low processor bus request (PBREa) input
which indicates that the CPU desires to access the display memory. This control output
has no meaning in row buffer mode

CTRl2

5

0

Handshake Control 2: In independent mode, provides an active low read data buffer
(RDB) output which strobes data from the display memory into the interface latch. In
transparent and shared modes, this is an active low bus external enable (BEXT) output
which indicates that the PVTC has relinquished control of the display memory
(DADDO-DADDI3 are in the three-state condition) in response to a CPU bus request.
BEXT also goes low in response to a 'display off and float DADD' command. In row buffer
mode, it is an active low bus request (BREO) output which halts the CPU during a line DMA.

Signetics

2·37

MICROPROCESSOR DIVISION

JANUARY 1982

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'w""""_,,,
PIN DESIGNATION
MNEMONIC
CTRL3

DADDO-DADD 13

(cont.)

PIN NO.

TYPE

NAME AND FUNCTION

6

0

34-21

0

Handshake Control 3: In independent mode, provides the active low buffer chip enable
(BCE) signal to the display memory. In transparent and shared modes, provides an active
low bus acknowledge (BACK) output which serves as a ready signal to the CPU in
response to a processor bus request. In row buffer mode, this is an active high memory bus
control (MBC) output which configures the system for the DMA transfer of one row of
character codes from system memory to the row display buffer.
Display Address: Used by the PVTC to address up to 16K of display memory. These
outputs are floated at various times depending on the buffer mode. Various control signals
are multiplexed on DADD3 thru DADO 13 and are valid at the trailing edge of BLANK. These
control signals are:
DADD3/L1
Line Interlace: Replaces DADD4/ LAO as the least significant line address for interlaced
sync and video applications. A low indicates an even row of an even field or an odd row of

an odd field.
DADD4-DADD7/LAO-LA3
Line Address: Provides the number of the current scan line within each character row.
DADD8/LNZ
Line Zero: Asserted before the first scan line in each character row.
DADD9/LPL
Li9ht Pen Line: Asserted before the scan line which matches the programmed light pen
line position (line 3, 5, 7, or 9).
DADD10/UL
Underline: Asserted before the scan line which matches the programmed underline position (line 0 thru 15).
DADD11/BLINK
Blink frequency: Provides an output divided down from the vertical sync rate.
DADD12/0DD
Odd Field: Active high signal which is asserted before each scan line of the odd field when
interlace is specified.
DADD13/LL
Last Line: Asserted before the last scan line of each character row.
VCC
GND

40

I

Power Supply: +5 volts ± 5% power input.

20

I

Ground: Signal and power ground input.

FUNCTIONAL DESCRIPTION
As shown on the block diagram, the PVTC
contains the following major blocks:
• Data bus buffer
• Interface Logic
• Operation Control
• Timing
• Display Control
• Buffer Control

Data Bus Buffer
The data bus buffer provides the interface
between the external and internal data busses. It is controlled by the operation control
block to allow read and write operations to
take place between the controlling CPU and
the PVTC.

Table 1

PVTC ADDRESSING

A2 A1 AO
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

READ (RD=O)
Interrupt register
Status register
Screen start address lower register
Screen start address upper register
Cursor address lower register
Cursor address upper register
Light pen address lower register
Light pen address upper register

2·38

Command register
Screen start address lower reg.
Screen start address upper reg.
Cursor address lower register
Cursor address upper register
Display pointer address lower reg.
Display pOinter address upper reg

NOTE
1 There are 11 Inltlahzatlon registers which are accessed sequentlaUy via a smgle address The pvre mamtams an
Internal pOinter to these registers which IS Incremented after each wrtte at thIS address until the last register (lR10,
the split screen register) IS accessed. The pomter then continues to pOint to the split screen register Upon
power-up or a master reset command, the internal pOinter IS reset to pOint to the first register (lRO) of the
Initialization register group The Internal pOinter can also be preset to any register of the group via the 'load IR
address pOinter' command

Interface Logic
The interface logic contains address decoding and read and write circuits to permit
communications with the microprocessor

WRITE (WR=O)
Initialization registers 1

via the data bus buffer. The functions performed by the CPU read and write oper·
ations are as shown in table 1.

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

SC2672

'am""'..!··,,
Operation Control

Buffer Control

The operation control section decodes configuration and operation commands from the
CPU and generates appropriate signals to
other internal sections to control the overall
device operation. It contains the timing and
display registers which configure the display format and operating mode, the inter·
rupt logic, and the status register which provides operational feedback to the CPU.

The buffer control section generates three
signals which control the transfer of data
between the CPU and the display buffer
memory. Four system configurations requiring four different 'handshaking' schemes
are supported. These are described below.

SYSTEM CONFIGURATIONS

Display Control

Figure 1 illustrates the block diagram of a
typical display terminal using the Signetics
2670, 2671, 2672, and 2673 CRT terminal
devices. In this system, the CPU examines
inputs from the data communications line
and the keyboard and places the data to be
displayed in the display buffer memory. This
buffer is typically a RAM which holds the
data for a single or multiple screenload
(page) or for a single character row.

The display control section generates linear
addressing for up to 16K bytes of display
memory. Internal comparators limit the portion of the memory which is displayed to
programmed values. Additional functions
performed in this section include cursor positioning, storage of light pen 'hit' location,
and address comparisons required for generation of timing signals and the split screen
interrupt.

The PVTC supports four common system
configurations of display buffer memory,
designated the independent, transparent,
shared, and row buffer modes. The first
three modes utilize a single or multiple page
RAM and differ primarily in the means used
to transfer display data between the RAM
and the CPU. The row buffer mode makes
use of a single row buffer (which can be a

Timing
The timing section contains the counters
and decoding logic necessary to generate
the monitor timing outputs and to control the
display format. These timing parameters are
selected by programming of the initialization
registers.

shift register or a small RAM) that is updated in real time to contain the appropriate
display data.
The user programs bits 0 and 1 of IRO to
select the mode best suited for the system
environment. The CNTRL 1-3 outputs perform different functions for each mode and
are named accordingly in the deScription of
each mode.

Independent Mode
The CPU to RAM interface configuration for
thIS mode is illustrated in figure 2. Transfer
of data between the CPU and display memory is accomplished via a bidirectional
latched port and is controlled by the signals
read data buffer (ROB), write data buffer
(WDB), and buffer chip enable (BCE). This
mode provides a non-contention type of operation that does not require address
multiplexers. The CPU does not address the
memory directly-the read or write oper·
ation is performed at the address contained
in the cursor address register or the pointer

address register as specified by the CPU.
The PVTC enacts the data transfers during
blanking intervals in order to prevent visual
disturbances of the displayed data.

CRT TERMINAL BLOCK DIAGRAM

CP\J

Figure 1

Signetics

2·39

2

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'm"""'!·"t
The CPU manages the data transfers by
supplying commands to the PVTC. The com-

INDEPENDENT BUFFER MODE CONFIGURATION

mands used are:
REFRESH

2672
PYle

1. Read / Write at pOinter address.
2. Read/Write at cursor address (with optional increment of address)
3. Write from cursor address to pOinter address.

RAM

OAOD

-

ADR

DISPLAY ADDRESS

;;a;

CTRL3
CTRL1

The operational sequence for a write operation is:

CTRl2

-

"""

1. CPU checks RDFLG status bit to assure
that any previous operation has been
completed.
2. CPU loads data to be written to display
memory into the Interface latch.
3. CPU writes address Into cursor or pOInter

co

w.
DATA 1/0

TO

VIDEO

DISPLAY DATA BUS

LOGIC

;,

registers.

y~

4. CPU issues 'write at cursor with/without

74LS364

I

(jE

cp

74LS364

increment' or 'write at pointer' command.

5. PVTC generates control signals and out·
puts specified address to perform requested operation. Data is copied from
the Interface latch into the memory.
6. PVTC sets RDFLG status to indicate that
the write is completed

ViR

RD

{

FROM CPU

FROM CPU

SYSTEM DATA BUS

I

Figure 2

Similarly, a read operation proceeds as follows:

1. Steps 1 and 3 as above.
2. CPU Issues 'read at cursor with /without
increment' or 'read at pointer' command.

3. PVTC generates control signals and outputs specified address to perform requested operatIon. Data is copied from
memory to the interface latch and PVTC
sets RDFLG status to indicate that the
read is completed.
4 CPU checks RDFLG status to see if operation is completed.
5. CPU reads data from interface latch.
LoadIng the same data into a block of dIs·
play memory is accomplished via the 'write
from cursor to pOinter' command:
CPU checks RDFLG status bIt to assure
that any previous operation has been
completed.
2. CPU loads data to be written to display
memory Into the Interface latch.

2·40

3. CPU writes beginning address of memory
block into cursor address regIster and
ending address of block Into pOinter address register.
4. CPU Issues 'write from cursor to painter'
command.
5. PVTC generates control signals and outputs block addresses to copy data from
the Interface latch into the specified
block of memory.
6. PVTC sets RDFLG status to indicate that
the block write is completed.

play window (defined as first scan line of the
first character row to the last scan line of
the last character row), the operation takes
place during the next horizontal blanking in·
terval, as Illustrated in figure 3. If the command is gIven during the vertical blanking
interval, or while the display has been com·
manded blanked, the operation takes place
Immediately. In the latter case, the execution tIme for the command IS approxImately
one mIcrosecond plus six (6) character
clocks (see figure 4).

Similar sequences can be implemented on
an interrupt driven basis using the READY
interrupt output to advise the CPU that a
previously requested command has been
completed.

TimIng for the 'write from cursor to pointer'
operation is shown In figure 5. The BLANK
output is asserted automatically and remains asserted until the vertical retrace in·
lerval following completion of the command.
The memory is filled at a rate of one location
per two character times, plus a small
amount of overhead.

Two timing sequences are possible for the
'read /write at cursor / pointer' commands. If
the command is given during the active dis-

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'pmllnllel·"t
READ/WRITE AT CURSOR/POINTER COMMAND TIMING
(Command received during active display window)

~

;U

~

~

~

1/

LANK

~

~?:-

OA

oo

_;n.

YLAST Y CURSOR OR
ADDRESS

POINTER ADDRESS

Y

"X

---~
I

22

\

HORIZONTAL BLANKING
INTERVAL

I

----------------~~

2

'~

~,

I

I'f'---'
'--I

I

\

NOTE
Wnte waveforms shown In dotted hnes

X

XPVTC CONTROLSIGNAlSI 1ST CHAR
TO VAC AND DCG
ADDRESS

Y

r-

I_REFRESH AOORESSES_

I

I
I

~~--------------------------------

22

1,--,
! \
Figure 3

READ/WRITE AT CURSOR/POINTER COMMAND TIMING
(Command received while display Is blanked)

BUNK

OADO

PYle READ COMMAND
ADDRESS

~_.-------------RE-FR-E-SH-A-O-D~-S-S-ES-~--------~~.~l----------------________~--~------------------__

Figure 4

Signetics

2·41

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'W""IIe1·"1
WRITE FROM CURSOR TO POINTER COMMAND TIMING

BLANK

BLANK IS SET UNTIL FIRST VBLNK AFTER LAST WRITE

"""----------------j

Figure 5

Shared and Transparent Buffer
Modes
In these modes the display buffer RAM IS a
part of the CPU memory domain and is addressed dlreclly by the CPU. Both modes
use the same hardware configuration with
the CPU accessing Ihe display buffer via
three-state drivers (see figure 6). The processor bus request (PBREO) control signal
Informs the PVTC thallhe CPU is requesting
access to Ihe display buffer. In response to
Ihls request, the PVTC raises bus acknowledge (BACK) unlll its bus external (BEXT)
outpul has freed the display address and
data busses for CPU access. BACK, which
can be used as a 'hold' input 10 the CPU, is
then lowered 10 indicate that the CPU can
access the buffer

PVTC SHARED OR TRANSPARENT BUFFER MODES

2672

pVle

PBR>Q
CPu {

=

ID'f

In transparent mode, the PVTC delays the
granting of the buffer to Ihe CPU until a verticalor horizonlal blanking interval, Ihereby
causing minimum disturbance of the display.
In shared mode, Ihe PVTC will blank Ihe display and grant Immediale access 10 the
CPU. Timing for these modes is illuslrated in
figures 7, 8, and 9

2·42

REFRESH

t-~====~~~~~======~
DISPLAY ADDRESS
ADR
RAM

SYSTEM DATA BUS

Figure 6

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'm""""·"j
TRANSPARENT BUFFER MODE TIMING

~~(1)

,------

~;-------------~~----------------.

~~----~--~------~~-- ______ I

\'----~2~~~_--AI ____ J------------~?------------------

221
w

;

W

BLANK
I/r-------H-O.-lz-O-NT-.-L-.LA...;~INl~...IN-G-,N-TE-.-V.-L------""\'------------i2------\
------~2~
.
\----------SYSTEM ADDRESSES

CADDX;>..I=

NOTES
1 PBREO must be asserted prior to the rlsmg edge of BLANK
begm dunng that blanking penod

In

order for sequence to

2 If PBREQ IS negated after the next to last CCLK of the hOrizontal blanking mterval, the
next scan hne will also be blanked

Figure 7

SHARED BUFFER MODE TIMING

'--____I-__-+____

~ {c;---------~~--------------

+-~~

--- ___ __ J

2~

~

____

r----

r--------~~-------------

~,~-------J

(1)

\--------~~ - ---\._--------

~~
BLANK

-------'

CADD

NOTE

1 If PBRea IS negated after the next to last CCLK of the honzontal blanking Interval, the
next scan hne Wilt also be blanked

Figure 8

Signetics

2·43

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'amn..""••"
,.j

SHARED AND TRANSPARENT MODE TIMING

'"
PBREQ

----------------~~----------------.
12

VBLANK OR DBLANK

BL.ANK

B----cI:

DAD~

--1
SYSTEM PROCESSOR HAS lJONTINUOUS BUS CONTROL.
}OAoo\'-_ _ _ _ _ _~il~~---------J

~

_REFRESH ADDRESSES-

ADDRESSES

a) During Vertical Blank or after 'display off' command

b) After 'display off and 3-slate' command

Figure 9

Row Buffer Mode

ROW BUFFER MODE CONFIGURATION

Figures 10 and 11 show the timing and a
typical hardware implementation for the
row buffer mode. During the first scan line
(line 0) of each character row, the PVTC
halts the CPU and DMA's the next row of
character data from the system memory to
the row buffer memory. The PVTC then reo
leases the CPU and displays the row buffer
data for the programmed number of scan
lines. The bus request control (BREQ) sig·
nal informs the CPU that character ad·
dresses and the memory bus control (MBC)
signal will start at the next falling edge of
BLANK. The CPU must release the address
and data busses before this time to prevent
bus contention. After the row of character
data is transferred to the CPU, BREQ reo
turns high to grant memory control back to
the CPU.

2X2111
ROW
REFRESH

BREQ
TO CPU

Figure 10

ROW BUFFER MODE TIMING

J\JV~f\J\J\J\J\.I'-I1JLF

:----rc~
=<

I

I

MBC _ _ _ _

I

~"-"::

~I~

12

Figure 11

2·44

Signetics

Ir-.:,....I_ __

1

~r---

\...._ _ __

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'tam""n,I_'"
groups, the PVTC is ready to control the
monitor screen. Prior to executing the PVTC
commands whIch turn on the dIsplay and
cursor, the user should load the dIsplay
memory with the first data to be displayed.
Durmg operation, the PVTC will sequentially
address the display memory within the limits
programmed into its registers. The memory
outputs character codes to the system
character and graphICS generation logic,
where they are converted to the seroal video
stream necessary to display the data on the
CRT. The user effects changes to the display by modifying the contents of the display
memory, the PVTC display control and command registers, and the initialization registers, if reqUired. Interrupts and status condItIons generated by the PVTC supply the
'handshaking' information necessary for the
CPU to effect the display changes in the
proper time frame.

OPERATION
After power is applled,the PVTC will be In an
inactive state. Two consecutive 'master
reset' commands are necessary to release
this circuitry and ready the PVTC for oper·
ation. Two register groups exist within the
PVTC: the initialization registers and the display control registers. The initialization regIsters select the system configuration, monitor timing, cursor shape, display memory
domain, and screen format. These are loaded first and normally require no modification
except for certain special visual effects.
The display control registers specify the
memory address of the base character (upper lell corner of screen), the cursor positoon, and the pointer address for independent memory access mode. These usually
require modIfication during operation.
Alter initial loading of the two register

INITIALIZATION REGISTERS

There are 11 inItIalizatIon regIsters
(lRO-IR 10) whIch are accessed sequentially via a single address. The PVTC maintains
an internal pointer to these registers which - - - is incremented after each write at this address until the last register (lR 10, the split
screen register) is accessed. The pOinter
then continues to point to the split screen
register. Upon power-up or a master reset
command, the internal pointer is reset to
pomt to the first register (lRO) of the
initIalizatIon register group. The internal
pointer can also be preset to any regIster of
the group via the 'load IR address pOinter'
command These registers are write only
and are used to specify parameters such as
the system configuration, dIsplay format.
cursor shape, and monitor timing. RegIster
formats are shown In figure 12

2

INITIALIZATION REGISTER FORMATS
am

...

NOT
USED

0000"" 1l_
0G01- 2LMS
0010 = 3UN1S

0001
0010

1110= 15UNES
1111"'"18L1N1S

1110= 31 LINES
1111 = UNDEFIED

=SLIES
=7 LIES

~I -

o '" VSYNC

00

1

01

=CSYNe

=INDEPEMJENT
=TRANSPARENT
=

BIT7

... :.,Wam

·....!!!!-·....!!!!.·AC~IV::...:,T:
00000010

[

.
.- -.- -.- -.- -.- -.- -.

.:C

11111110 =-255 CHARACTERS

1",1111 "" 256 CHARACTERS

10"" SHARED
11
ROW

L.----'_ _ '._---'-_ _ _ _-'------'_ _

..,..orr,
.......
lA,

~~;·-~~~~I

"IT
'

B1T7

[

....

000' .. SCAN LINE 1

'-_.....L_ _• _ _ • _ _ • _ _• _ _ • _ _ •

WI2

BlT7

= II CQJ(

001

NOT.
USED . / .
1110=30CCLJ(
1111 =32ca.K

•
•
110 = 2I!iCCLK
111 =2SlCCLK

--

~::..r:"'I";·
BIT.. ~~:;~BIT'

..

00000 "" 4 SCAN LINES

001

00001 "'" 6 SCAN UtES

IR3

110 = 28 SCAN LINES
111 = 32 SCAN LINES

----1-.

am
CHAIIM:mo
BUNK

... ~
VSYNC
1/32
VSYNC

1

..

000 - 4 SCM LINES

=

.JIIT. [

00000oo
0000001

BIT3.8IT2_BlT1.

.

=1 ROW
=2 ROWS

BlT4

CHAR

01=SCANUM:5
10='SCANUfiE7
11 "'SCANLINE8

O=NO
1=YES

-O=NO
1=YES

81T7

r!~Y:U~!~';ADD'"!'ESS~S8~1T2 -~-J.rro

---..!!!!.--

8IT3

. . .

1110 = SCAN UNE 14
1111 '" SCAN LIE 15

If000'= 0

H'001'= 1
-

H'FF£' = 4,094

NOTE MY'S ARE ..
1RII(30)

H'FFF' "" 4,085

-- --- --- --- --- --- --

11110 = 84 SCAN LINES

ACTIVE CHARACTER ROWS IleA ICfEEN

~~~~~~.Jarro

BITS

--

IR8

1--,-: :. :.:. .:. -I : : . :. : :.:.: :. :. .:

11111=HSCANUNES
-_
_ •_ _•_ _ •

1I11I.IfTS.1IIT4.

IIT6

I-~-==

.-

-- -.- --

=8 SCAN LINES

It7

•

1111=-SCANLlNE15

=SCAN UNE 3

00

CQJ(

0001 '" 4 CCLK

.
.-.
--

111:=SCAN LlNE14

1110.:SCAN LINE 14
1111 = SCAN LINE 15

',11110_127CCLK

.LA~7...~~~.JBrro

0000 = SCAN LINED

0001 .. SCAN LINE 1

.- -.- -.

IMl

~AL.sy.:,rr':";:C81T3
~~.J"':
0000 =2
000 = 1 CCLK

Brr, lIT,

·ARS~ ~~:..

0000 .. SCAN LINE 0

1111111 .. 128 CCLK

BITO

.~.JBIT.

= 3 CHARACTERS

00000011 "" • CHARACTaIS

BrrG

(NOTE]!

0000 - 1,023
0001'" 2,047

-:

.__.__.
1110= 15,3119
1111"" 18,383

1111110= 127 ROWS
1111111
128 ROWS

=

BIT7

L _ _L - _ · _ _ • _ _ • _ _ • _ _ • _ _ •
NOTE

CURSOR

1 In Interlace mode with odd total character rows per screen the last cha!Jcter
row will be the programmed scan lines per character row minus one

BUNK

~
IR10

0"" 1/16

1

VSYNC
1132
VSYNC

=

I

-~

.__.__.

.J"".
__.__.__.__.__.

BITe ...... :rr~~= . BIT,

'---'---'.

=·ROW

1111110
126
1111111 '" ROW 127

Figure 12

Signetics

2-45

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

SC2672

'm",,",I-,'j
IR0[6:3]-Scan Lines per
Character Row
Both interlaced and non-interlaced scanning are supported by the PVTC. For interlaced mode, two dIfferent formats can be
implemented, depending on the
interconnectIon between the PVTC and the
character generator (see IR1(7)). ThIs field
defines the number of scan lines used to
compose a character row for each technique. As scanning occurs, the scan line
count is output on the LAO-LA3 and LI pins.

IR1[6:0]-Equallzlng Constant
ThIs fIeld indirectly defines the horizontal
front porch and is used internally to generate the equalizing pulses for the RS 170
compatIble CSYNC. The value for this field
is the total number of character clocks
(CCLK) during a horizontal line period divided by two, minus two times the number of
character clocks in the horizontal sync
pulse'
HACT + HFP + HSYNe + Hap
EC =
-2(HSYNC)
The definition of the individual parameters is
Illustrated in figure 14.

IR0[2]-VS/CS Enable
This bit selects either vertical sync pulses
or composite sync pulses on the
VSYNC/CSYNC output (pIn 18). The composite sync waveform conforms to EIA
RS 170 standards, with the vertical interval
composed of six equalizing pulses, six vertical sync pulses, and six more equalizing
pulses.

Note that when using the 2673 VAC, it will
delay the blank pulse three CCLKs relative
to the HSYNC pulse.

IR2[6:3]-Horizontal Sync Pulse
Width
This field specifies the width of the HSYNC
pulse in CCLK periods.

IR0[1:0]-Buffer Mode Select

IR2[2:0]-Horlzontal Back Porch

Four buffer memory modes may be selectively enabled to accommodate the desired
system configuration. See System Configuration.

This field defines the number of CCLKs between the trailing edge of HSYNC and the
trailing edge of BLANK.

SpecIfies interlaced or noninterlaced timing
operation. Two modes of interlaced operation are available, depending on whether
LO-L3 or LI, LO-L2 are used as the line
address for the character generator The resulting displays are shown in figure 13.
For 'interlaced sync' operatIon, the same
information is displayed in both odd and
even fields, resulting in enhanced
readability. The PVTC outputs successive
line numbers in ascending order on the
LAO-LA3 lines, one per scan line for each
field.
The 'onterlaced sync and video' format doubles the character density on the screen
The PVTC outputs successIve line numbers
in ascending order on the LI, LAO-LA2 lines,
one per scan line for each field, but alternates beginning the count with even and odd
line numbers. This displays the odd fIeld
with even scan lines in even character rows
and odd scan lines in odd character rows,
and the even field with odd scan lines in
even character rows and even scan lines on
odd character rows. This provides balanced
beam currents in the odd and even fields,
thus minimizing character variations due to
different loading of the CRT anode supply
between fields.

2·46

ThIs field determines the number of characters to be displayed on each row of the CRT
screen. The sum of thIS value, the horizontal
front porch, the horizontal sync width, and
the horizontal back porch is the horizontal
scan period in CCLKs.

IR6[7:4]. IR6[3:0]-First and Last
Scan Line of Cursor
These two fields specify the height and poSItion of the cursor on the character block.
The 'first' line IS the topmost line when scanning from the top to the bottom of the
screen.

IR7[7:6]-Light Pen Line Position
This field defines which of four scan lines of
the character row will be used for the light
pen strike-thru attribute by the 2673 VAC.
The tIming signal is multiplexed onto the
DADD91 LPL output during the falling edge
of BLANK.

IR7[5]-Cursor Blink Enable
IR3[7:5]-Vertlcal Front Porch

IR1[7]-lnterlace Enable

IR5[7:0]-Actlve Characters Per
Row

Programs the number of scan line periods
between the rising edges of BLANK and
VSYNC during a vertical retrace interval.
The width of the VSYNC pulse is fixed at
three scan lines.

IR3[4:0]-Vertical Back Porch
This fIeld determines the number of scan line
peroods between the falhng edges of the
VSYNC and BLANK outputs.

IR4[7]-Character Blink Rate
Specifies the frequency for the character
blink attribute timing. The blink rate can be
specified as 1/16 or 1/32 of the vertical
fIeld rate. The timing signal has a duty cycle
of 75% and is multiplexed onto the
DADD 111 BLINK output at the falhng edge of
each BLANK.

ThIS bit controls whether or not the cursor
output pin will be blinked at the selected
rate (lR 10(7)). The blink duty cycle for the
cursor IS 50%.

IR7[4]-Double Height Character
Row Enable
If enabled, the number of each scan line will
be repeated twice in succession, causing
the height of the character row to double.
This bit can be changed at any time but will
only become effective at the begInning of
the character row following the tIme it is
ehanged. This allows selected character
rows to be of double height. The split screen
onterrupt can be used to notify the CPU when
to effectuate changes to this bit. For each
double height row which replaces a normal
row, one row count should be subtracted
from the 'character rows per screen' field
(lR4) to maintain the same total number of
scan lines per field.

IR4[6:0]-Character Rows Per
Screen
This field defines the number of character
rows to be displayed This value multiplied
by the scan lines per character row, plus the
vertical front and back porch values, and the
vertical sync pulse width (three scan lines)
IS the vertical scan period in scan lines.

5ignetics

IR7[3:0]-Underllne Position
This field defines which scan line of the
character row will be used for the underline
attribute by the 2673 VAC. The timing signal
is multiplexed onto the DADD10/UL output
during the falling edge of BLANK.

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

INTERLACED DISPLAY MODES

2
LINE ADDRESS
TO CHAR GEN

LINE ADDRESS
TO CHARGEN

LINE ADDRESS
TO CHAR GEN

8~

......

1

--e-e-e-e-e----

2

--.--------------

3

--.---------------

o SCAN
/

1

- - . -. -. ----------

ROW

--.~~~~~~~~
2-0

UNES/

3

--.

2
4

-

3-0

•••

4-0

ROW

0-0

5

--.---------------

5-0
5--.'~~

8

--.---------------

8 --.

7

-e-e-e-e-e----

7

{--.

:-.:::======
1-00000----

1 -0-0-0-0-0---

17 SCAN
4

0---------------e-e-e-e-e---

3-0

o SCAN
UNO.I
ROW

4

5-0

8

~~.~=====

7-00000----

8

6-0

o

1

-

-e-e-e-e-e----

3

-.

•••••- - - -

7 -0-0-0-0-0---

5

--. --------

2-0=======
4-000---------

8- 0 - - - - - - - - - - - - -

1

-e-e-e-e-e----

2

--. -------------

3

- - . ---------------

1

--. -. -.----------

5

-- .---------------

8

--.---------------

7

-e-e-e-e-e----

-

2-0-------------

2

- . -------------

3-0

4

-- •••

8

-.

1

-

3

-.

-e-e-e-e-e---

•••••- - - -

1-00000-------

2-.======
--.::;:::-;=====
6-0======
3

4

7

1 -0-0-0-0-0---

4-0

0

4

5-0
--.:~.~.~:::::::::

5

--.

6

-.

7

3-0~~~~~~~
5-0

0

7-00000----

o

7 -0-0-0-0-0---

-e-e-e-e-e----

•••••- - - -

6-02-0~~~~~~~
4-000

5 --.
7

NONINTERlACED
IRO=1000, TOTAL LINESlROW=9

-

•••••- - - -

INTERLACED SYNC & VIDEO
IRO
0011; TOTALUNES/ROW

INTERLACED SYNC
IRO = 0111; TOTALUNES/ROW = 17

=

=9

Figure 13

IR9(3:0], IR8[7:0]-Display Buffer
First Address
IR9[7:4]-Display Buffer Last Ad·
dress
These two fields define the area within the
buffer memory where the display data will
reside When the data at the 'display buffer
last address' is displayed, the PVTC will
wrap-around and obtain the data to be displayed at the next screen position from the
'display buffer first address'. If 'last address' is the end of a character row and a
new screen start address has been loaded
into the screen start register, or if 'last address' is the last character position of the

screen, the next data is obtained from the
address contained in the screen start
register.
Note that there IS no restriction in displaying
data from other areas of the addressable
memory. Normally, the area between these
two bounds IS used for data which can be
overwritten (e.g., as a result of scrolling),
while data that is not to be overwritten would
be contained outside these bounds and
accessed by means of the split screen interrupt feature of the PVTC.

IR10[7] - Cursor Blink Rate
The cursor blink rate can be specified at
1/16 or 1/32 of the vertical scan frequency.

Signe1ics

Blink

IS

effective only if blink is enabled by

IR7[5].

IR10[6:0]-Split Screen Interrupt
The split screen interrupt can be used to
proVide special screen effects such as a
row of double height characters or to
change the normal addressing sequence of
the display memory. The contents of this
field IS compared, In real time, to the current
character row number. Upon a match, the
PVTC sets the split screen status bit, and
Issues an interrupt request If so programmed The status change/interrupt request IS made at the beginning of scan line
zero of the split screen character row.

2-47

MICROPROCESSOR DIVISION

JANUARY 1982

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'am""""·'fJ
HORIZONTAL AND VERTICAL TIMING

r-----___

HBLANK~

----j

HSYNC

I--

CH~:::5~OW - - - - - - 1

L-

BACK PORCH {IR21

FRONT PORCH (IR1)

______________--,n,--___
r~AR

---1I~

--t
~r------;I

HSYNC (lA2)

VBLANK

--I I-

--I I--

ROWS/SCREEN (1R4)------I

I

I-- SCAN LINES PER ROW (lRO)

Ii----'L
--I
I-

FRONT PORCH (lR3)

BACK PORCH (IR3)

--.lnL...-___

VSYNC---IlL...-_ _ _ _ _ _ _ _ _ _ _ _ _

r-

----1

VSVNC (FIXED AT 3)

EQUALIZING
CONSTANT

LINES/ROW

I
100

I

IL-LI-II-----'-.I-11--,-1-'--'--'
I

102

101

HBACK
PORCH

HSYNC

WIDTH
,

IL...LI-'--'-.LI-,IL-L-'--I
YFRONT

VBACK

POACH
,

PORCH
,

I

I

1I I I I I I I
CHAR ROWS/SCREEN

CHARACTERS PER ROW

,

104

,

I I I I

105

I 1I I 1

Figure 14

Timing Considerations
Normally, the contents of the initialization
registers are not changed dUring operation.
However, thiS may be necessary to imple·
ment special display features such as multiple cursors, smooth scrolling, horizontal
scrolling, and double height character rows.
Table 2 describes timing details for these
registers which should be conSidered when
Implementing these features.

Table 2

TIMING CONSIDERATIONS
PARAMETER

TIMING CONSIDERATIONS

First line of cursor
Last line of cursor
Light pen line
Underline

These parameters must be established at a minimum of two character
times prior to their occurenC8.

Double height characters

Sell reset during the character row
prior to the row which IS to be I not to
be double height

Cursor blink
Cursor blink rate
Character blink rate

New values become effective within
one field after values are changed

Split screen interrupt row

Change anytime prior to line zero of
desired row

Character rows per screen

Change onlY aUrlng verhcal Dlanklng
period

Vertical front porch

Change prior to first line of VFP

Vertical back porch

Change prior to fourth line after
VSYNC

Screen start register

2·48

Signetics

Change prior to the horizontal
blanking interval of the last line of
character row before row where new
value is to be used

JANUARY 1982

MICROPROCESSOR DIVISION

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
DISPLAY CONTROL REGISTERS
There are nine registers in this group, each
with an individual address. Their formats are
illustrated in figure 15. The command register is used to invoke one of 16 possible
PVTC commands as described in the COM·
MANOS section of this data sheet. The remaining registers in the group store address
values which specify the cursor and buffer
pointer locations, the location of the first
character to be displayed on the screen,
and the location of a light pen 'hit'. With the
exception of the light pen register, the user
initializes these registers after powering on
the system and changes their values to control the data which is displayed.

Screen Start Registers
The screen start registers contain the address of the first character of the first row
(upper left corner of the active display). At
the beginning of the first scan line of the first
row, this address is transferred to the row
start register (RSR) and into the memory
address counter (MAC). The counter is then
advanced sequentially at the character rate
the number of times programmed into the
active characters per row register (IRS),
thus reaching the address of the last character of the row plus one. At the beginning of
each subsequent scan line of the first row,
thE> MAC is reloaded from the RSR and the
above sequence is repeated. At the end of
the last scan line of the first row, the contents of the MAC is loaded into the RSR to
serve as the starting memory address for
the second character row. This process is
repeated for the programmed number of
rows per screen. Thus, the data 10 the diS'
play memory is displayed sequentially starting from the address contained in the screen
start register. After the ensuing vertical retrace interval, the entire process repeats
again.

The sequential operation described above
will be modified upon the occurence of either of two events. First, if during the incrementing of the memory address counter the
'display buffer last address' (IR9[7:4]) is
reached, the MAC will be loaded from the
'display buffer first address' register
(IR9[3:0], IR8[7:0]) at the next character
clock. Sequential operation will then resume
starting from this address. This wraparound
operation allows portions of the display buffer to be used for purposes other than storage of displayable data and is completely
automatic without any CPU intervention (see
figure 16a).
The sequential row to row addressing can
also be modified under CPU control. If the
contents of the screen start register (upper,
lower, or both) are changed during any character row (say row 'n'), the starting address
of the next character row (row 'n + 1') will
be the new value of the screen start register
and addressing will continue sequentially
from there. ThiS allows features such as
split screen operation, partial scroll, or status line display to be implemented. The split
screen interrupt feature of the PVTC is useful in controlling this type of operation. Note
that in order to obtain the correct screen
display, the screen start register must be
reloaded with the original value prior to the
end of the vertical retrace. See figure 16b.
During vertical blanking the address counter
operation is modified by stopping the automatic load of the contents of the RSR into
the counter, thereby allowing the address
outputs to free-run. This allows dynamic
memory refresh to occur durmg the vertical

retrace mterval. The refresh addressing
starts at the last address displayed on the
screen and increments by one for each char·

acter clock during the retrace interval. If the
display buffer last address IS encountered,

SC2672

refreshing continues from the display buffer
first address.

Cursor Address Registers
The contents of these registers defines the
buffer memory address of the cursor. If en·
abled, the cursor output will be asserted
when the memory address counter matches
the value of the cursor address registers.
The cursor address registers may be read
or written by the CPU or incremented via the
'increment cursor address' command. In in-

dependent buffer mode, these registers define a buffer memory address for PVTC controlled access in response to 'read /write at
cursor with /wlthout increment' commands,
or the first address to be used in executing
the 'write from cursor to pointer' command.

Display Pointer Address Registers
These registers define a buffer memory ad·
dress for PVTC controlled accesses in response to 'read/write at pomter' commands They also define the last buffer
memory address to be written for the 'wnte
from cursor to pOinter' command.

Light Pen Address Registers
If the light pen input is enabled, these registers are used to store the current character
address upon receipt of a light pen strobe
input. Several sources of delay between the
display of a character upon the screen and
the receipt of a light pen hit can be expected
to eXist in a system environment. These delays include address pipelining in the char·
acter generation cirCUits, delays in the Video
generation circuits, and delays in the light
detection circuitry Itself These delays
cause the value stored in the light pen register to differ from the actual address of the
character at which the light pen hit actually
was detected. Software must be used to
correct this condition.

DISPLAY CONTROL REGISTER FORMATS

~7 .~.~a~~~~~~_~B::.'~'JBITO
[

._---_.__.__.__.__.
COMMAND REGISTER (Write only)

F-~~ '1-"'--0 -~~.- O--"'-0J"ITO

~..--~.--.--.--.--.--.

B1T7 •....!!!!..... "1T5LO;E''':,';.~'S;'' ~':""'~'
H'OOOO'
H'OOO1'

[

0

=1

2!!!.. . JBITO

Not., MSB', Ire In
Upper Regl.ter {5:0]

.- -.- -.- -.- -.- -.- -.
H'3FFE'
H'3FFF'

SCREEN START REGISTERS
CURSOR ADDRESS REGISTERS
POINTER ADDRESS REGISTER
UGHT PEN ADDRESS REGISTER

= 16,382

= 16,383

(READ AND WRITE)
(READ AND WRITE)
(WRITE ONLY)
(READ ONLY)

Figure 15

Signetics

2·49

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'RI""II,I-"i
INTERRUPTISTATUS REGISTERS
The interrupt and status registers provide
information to the CPU to allow it to interact
wIth the PVTC to effect desired changes to
implement various display operations. The
interrupt register provides information on
five possible interrupting conditions, as
shown in figure 17. These conditions may be
selectiyely enabled or disabled (masked)
from causing Interrupts by certain PVTC
commands. An interrupt condition which is
enabled (mask bit equal to one) will cause
the INTR output to be asserted and will
cause the corresponding bit in the interrupt
register to be set upon occurrence of the
interrupting condition. An interrupt condition
whIch is disabled (mask bit equal to zero)
has no effect on either the INTR output or
the interrupt register.

DISPLAY ADDRESSING OPERATION

f - - - - - - - - l ...
BOnOU OF SCREEN ...

DISPLAY BUFFER START

f--------l

MONITOR
DI.....Y

16. ' -_ _ _ _ _----'
MEMOFlY

The status register provides six bits of status information: the five possible interrupting
conditions plus the NOT BUSY bit. For this
register, however, the contents are not
effected by the state 01 the mask bits.

la)

DISPLAY MEMORY WRAPAROUND

f - - - - - - - - I ...

DISPLAY BUFFER START

Descriptions of each interrupt I status register bit follow. Unless otherwise indicated, a
bit, once set, will remain set until reset by
the CPU by issuing a 'reset interrupti status
bits' command. The bits are also reset by a
'master reset' command and upon
power-up.

SR[5] - RDFLG
This bit is present in the status register only.
A zero indicates that the PVTC is currently
executing the prevIously issued command. A
one indicates that the PVTC is ready to ac-

MONITOR
DISPLAY

cept a new command.
16. ' -_ _ _ _ _----'

I/SR[4] - VBLANK

MEMORY

Indicates the beginning of a vertical blanking
interval. Is set to a one at the beginning of
the first scan line of the vertical front porch.

(b)

DISPLAY MEMORY SPliT SCREEN WITH WRAPAROUND

Figure 16

I/SR[3] - Line Zero
Is set to a one at the beginning 01 the f,rst
scan line (line 0) of each active character

row.

INTERRUPT AND STATUS REGISTER FORMAT
BIT7

I/SR[2] - Spilt Screen
This bit is set when a match occurs between
the current character row number and the
value contained in the split screen interrupt
register, IR 10[6:0). The equality condition is
only checked at the beginning 01 line zero of
each character row. This bit is reset when
either 01 the screen start registers is loaded
by the CPU.

I/SR[1] - Ready
Certain PVTC commands affect the display
and may require the PVTC to wait for a
blanking interval before enacting the command. This bit is set to one when execution
01 the command has been completed. No

2-50

BITS

BIT6

I

RDFLG

Not used
always read as 0

BIT4

BIT3

BIT2

VBLANK

LINE
ZERO

SPLIT
SCREEN

0= Busy 0= No
1 = Ready 1 = Yes

0= No
1 = Yes

BIT1

BITO

READY

LIGHT
PEN

0= No 0= Busy 0= No
1 = Yes 1 = Ready 1 = Yes

I
NOTE

·Status reglater only Always 0 when readlRg Interrupt register

Figure 17
command should be invoked until the prior
command IS completed.

I/SR[O] - Light Pen
A one indicates that a light pen hit has occurred and that the contents of the light pen

Signetics

regIster have been updated. This bit will be
reset when either of the light pen registers is
read.

MICROPROCESSOR DIVISION

JANUARY 1982

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'am"") ..i.',,
COMMANDS

The PVTC commands are divided into two
classes the instantaneous commands,
which are executed Immediately after they
are invoked, and the delayed commands
which may need to wait for a blanking interval prior to their execution. Command formats are shown In table 3. The commands
are asserted by performing a write operation to the command register with the appropriate bit pattern as the data byte.

Table 3_

Instantaneous Commands

This command initializes the PVTC and may
be invoked at any time to return the PVTC to
ItS ,"itial state. Upon power-up, two
successive master reset commands must
be applied to release the PVTC's internal
power on CirCUitS. In transparent and shared
buffer modes, the CNTRll input must be
high when the command is issued. The command causes the following'

This command IS used to preset the
initialization register pOinter With the value
'V' defined by 03-00. Allowable values are
o to 10.

Enable Light Pen
After invoking this command, receipt of a
light pen strobe input will cause the light pen
register to be loaded with the current buffer
memory address and the corresponding interrupt and status flag to be set Once loaded, further loads are inhibited until either
one of the light pen registers are read or a
reset function IS performed.

Disable Light Pen
Light pen hits will not be recognized.

Display Off
Asserts the BLANK output The DADDO thru
DADO 13 display address bus outputs may

0
0
0
0
0
0

0
0
0
0
0
0

0
0
1
1
1
1

0
1
d
d
d
d

0
V
d
d
1
1

0
V
d
d
N
N

0
V
1
1
d
d

0
V
0'
12
0'
12

0
0
0
1
0

0
0
1
0
1

1
1
0
0
1

1
1
N
N
N
V
B

d
d
N
N
N

d
d
N
N
N

0'
12

l
Z

S
S

d
d
N
N
N
R
0

1
1
1
1
1
1

0
0
0
0
0
0

1
1
1
1
1
1

0
0
0
0
0
0

0
0
1
1
1
1

1
0
0
1
0
1

1
1

0

1

0

1

0

1

1

1

Master reset
load IR pOinter with value V (V = 0 to 10)
Disable light pen
Enable light pen
Display off. Float DADO bus If N = 1
Display on Next field (N = 1) or scan line
(N =0)
Cursor off
Cursor on
Reset interrupt! status Bit reset where N = 1
Disable interrupt· Disable where N = 1
Enable interrupt" Enables interupts and resets
the corresponding interrupt / status bits where
N=l

N
N
N

L

P

Delayed Commands:

Master Reset

Load IR Address

COMMAND

Instantaneous Commands:

The Instantaneous commands are executed
Immediately after the trailing edge of the WR
pulse during which the command IS Issued.
These commands do not affect the state of
the RDFlG or READY Interrupt! status bits.
However, a command should not be invoked
if the RDFlG bit IS low

1. VSYNC and HSYNC are driven low for the
duration of RESET and BLANK goes high.
BLANK remains high until a 'display on'
command is received.
2. The interrupt and status bits and masks
are set to zero, except for the RDFlG flag
which is set to a one.
3. The transparent mode, cursoroff, display
off, and light pen disable states are set.
4. The initialization register pointer is set to
address IRO.

PVTC Command Formats

D7 D6 05 04 03 02 01 DO

Hex
A4
A2
A9
AC
AA
AD

0
1
0
0
1
0

0
0
1
0
0
1

0

1

1

AB

0

1

1

BB

Read at pointer address
Write at pOinter address
Increment cursor address
Read at cursor address
Write at cursor address
Read at cursor address and Increment
address
Write at cursor address and increment
address
Write from cursor address to pOinter address

,

NOTES
Any combmatlon of these three commands IS valid
2 Any combmatlon of these three commands IS valid
3 d = don't care

be optionally placed in the three-state condition by setting bit 2 to a '1' when invoking
the command.

Display On
Restores normal blanking operation either
at the beginning of the next field (bit 2 = 1)
or at the beginning of the next scan line (bit
2 = 0). Also returns the DADDO-DADD13
drivers to their active state

Cursor Off
Disables cursor operation. Cursor output is
placed in the low state.

Cursor On
Enables normal cursor operation.

Reset Interrupt/Status Bits
This command resets the deSignated bits in
the interrupt and status registers. The bit
positions correspond to the bit positions in
the registers:
Bit
Bit
Bit
Bit
Bit

0
1
2
3
4

-

Light pen
Ready
Split screen
Line zero
Vertical blank

Signefics

Disable Interrupts
Sets the Interrupt mask to zeros for the designated conditions, thus disabling these
conditions from asserting the INTR output.
Bit position correspondence is as above.

Enable Interrupts
Resets the selected interrupt and status
register bits and writes the associated interrupt mask bits to a one. This enables the
corresponding conditions to assert the INTR
output Bit position correspondence is as
above

Delayed Commands
This group of commands IS utilized for the
independent buffer mode of operation, although the' Increment cursor' command can
also be used in other modes. With the exception of the 'write from cursor to pointer'
and 'increment cursor' commands, all the
commands of this type Will be executed immediately or will be delayed depending on
when the command IS Invoked. If invoked
during the active screen time, the command
IS executed at the next horizontal blanking
mterval. If invoked during a vertical retrace
Inlerval or a 'display off' state, the command
IS executed immediately.

2·51

MICROPROCESSOR DIVISION

JANUARY 1982

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'am""II,I_"t
The 'increment cursor' and 'write from
cursor to pointer' commands are executed
ImmedIately after they are issued. 'Increment cursor' requires approximately three
CCLK periods for completion. 'Write from
cursor to pointer' asserts the BLANK output
during its execution. BLANK will not be released until the beginning of the vertical
blanking interval following the last write operation. A second 'write from cursor to pOinter' command should not be issued until this
time.
In all cases, the PVTC will assert the
READY / RDFLG status to signify completion
of the command. No other commands should
be given until the current command is completed. Therefore, the READY Interrupt or

RDFLG status flag should be used for
handshaking control between the PVTC and
CPU when using these commands.

Read/Write

at Pointer

Transfers data betwaen the display buffer
and the bus interface latch using the address contained In the pointer register.

Read/Write

Read/Write
Increment

at Cursor and

Transfers data between the display buffer
and the bus interface latch using the address contained in the cursor register and
then adds one (modulo 16K) to the cursor
address register.<

Write from Cursor to Pointer

at Cursor

Transfers data between the display buffar
and the bus Interface latch using the address contained in the cursor register.

Increment Cursor
Adds one (modulo 16K) to the cursor address regIster.

Writes the data contained in the bus interface latch into the block of display memory
designated by the the cursor address and
pOinter address registers, inclusive. After
completion of the command, the pointer address will be unchanged, but the cursor register contents will be equal to the pOinter
address.

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature2
Storage temperature
All voltages with respect to ground'

RATING

UNIT

o to +70

·C
·C
V

-65 to +150
-0.5 to +6.0

DC ELECTRICAL CHARACTERISTICS TA=O·Cto + 70·C, Vcc =5.0V ±50/0 4 •5.6
LIMITS
PARAMETER

TEST CONDtTIONS
J

VIL
VIH
VOL
VOH
IlL
ILL
100
ICC

Input low voltage
Input high voltage
Output low voltage
Output high voltage
(except INTR output)
Input leakage current
Data bus 3-state laakage current
INTR open drain output leakage current
Power supply current

Typ

Max
0.6

10L = 1 SmA
10H
VIN
Vo
Vo

= -100 uA
= Oto VCC
= Oto VCC
= Oto VCC

See next page

Signetics

2.4
-10
-10
)

UNIT

0.4

V
V
V

10
10
10
160

V
fAA
fAA
fAA
mA

2.0

NOTES

2·52

Min

MICROPROCESSOR DIVISION

JANUARY 1982

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'm""""·"A
AC ELECTRICAL CHARACTERISTICS

TA =O'C 10 + 70'C, Vee =5.0V ± 5% 4,5,6,7,8
TENTATIVE LIMITS
TEST CONDITIONS

PARAMETER
Bus Timing (Fig. 18)9
AO-A2 setup time to WR, RD low
lAS
AO-A2 hold time from WR, RD high
tAH
CE setup time to WR, RD low
tcs
CE hold time from WR, RD high
tCH
WR, RD pulse width
tRW
Data valid after RD low
tDD
Data bus floating after RD high
tDF
Data
setup time to WR high
tDS
Data hold time from WR high
tDH
Time between READs and/or WRITEs'o
tcc

Min

Typ

30
0
0
0
250
200
100
150
0
600

CCLK Timing (Fig. 19)
CCLK period
tccp
CCLK high time
tCCH
CCLK low time
tCCL
Output delay from CCLK edge
tCCD

250
100
100

Other Timings (Fig. 20)
READY IRDFLG low from WR high 9
tRDL
tBAK
tBXT
tLPS
tLPH
tlRL
tlRH

BACK high from PBREO low
BEXT high from PBREO high
Light pen strobe setup time to
CCLK low
Light pen strobe hold time from
CCLK low
INTR low from CCLK low
INTR high from WR, RD high 9

600

ns

150
150

ns
ns
ns

150
600

3 ThiS product Includes CirCUitry specIfically deSigned for the protection of Its Internal
deVices from damaging effects of excessIve static charge Nonetheless, It IS suggested that conventional precautions be taken to avoid applYing any voltages larger than
the rated maxima

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

150

-10

2 For operating at elevated temperatures, the deVice must be derated based on + 150°C
maximum Junction temperature and thermal resistance of 55°C/W Junction to ambient
(IWA ceramiC package)

UNIT

ns
ns
ns
ns

120

Notes:
1 Stresses above those hsted under Absolute MaXimum Ratmgs may cause permanent
damage to the deVice This IS 8 stress ratmg only and functional operation of the deVIce
at these or at any other condition above those In the operation section of this specliIcation 18 not Implied

4 Parameters are valid over specified temperature range

Max

ns
ns
ns

5 All voltage measurements are referenced to ground (GND)
6 TYPical values are at +25°C, tYPical supply voltages, and typical processmg parameters
7 For testing, all Input signals sWing between 0 4V and 2 4V with a transition time of 20ns
maximum All time measurements are referenced at Input voltages of 0 8V and 2 OVand
output voltages of 0 8V and 2 OV as appropriate
8 Test condition for outputs CL

= 150pF

9 Timing IS Illustrated and specified referenced to WR end AD Inputs DeVice may also be
operated with CE as the 'strobing' Input In this case, all timing speCifications apply
referenced to falhng and rising edges of CE
10 1 microsecond minimum after 'master reset' command

Signetics

2·53

MICROPROCESSOR DIVISION

JANUARY 1982

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

SC2672

'Wnull.I·'tA
BUS TIMING

A~A2 ~-------:---_

00-D7

(READ)

FLOAT

FLOAT

riDS
00-07 _ _ _ _ _ _ _ _ _
(WRITE)

~\A
~

VALID

Figure 18

CCLK TIMING

NOTES
OUTPUTS
(NOTE 1)

-----...1

1 DADDO·DAOD13, BLANK. HSVNC, CSYNCIVSVNC, CURSOR, BEXT. BREQ, BCE,
MBC. BACK
2 BCE changes state on both CC'["R edges-(see FIgures 3 and 4)

OUTPUTS

WIiIi,_,1ft

Figure 19

2·54

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

SC2672

'm""II.i_"t
OTHER TIMINGS

BLANK

_---Ir

2
=

VERTICAL
BUNKING
INTERVAL

F1RSTHSYNC
OFYIILANK

HSYNC

VOlANI<
STATUS BIT

BLANK

DADD3-

DADD13

UNEZERO AND
SPUT SCREEN
STAruS BITS

IITII

----------l~

______

LPS

UGHT ....
STATUS Bff

DADDODADD13

CHARACTER
ADDRESS n

Figure 20

Signetics

2·55

JANUARY 1982

MICROPROCESSOR DIVISION

SC2672

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)

'RI"..II.'-III
OTHER TIMINGS (Continued)
WliFORA
DELAYED
COMMAND

READY OR
RDFLG
STATUS BITS

WlfORlW
WHICH RESETS

INTERRUPT

~r
\1:....-_-

~
___---.J/
Figure 20

COMPOSITE SYNC TIMING

. +-

VERTICAL SYNC PULSE

VERTICAL BACK PORCH

---1

FIRST DtSPlAYED SCAN
OF/EVEN FIELD
HORIZONTAL SYNC

~ULSES

- Un L -

_ _________
I~_I
' - - - - - - - - - - - - - - - - YERTICALBlANKING INTERVAL

ODD FIELD

LAST DISPLAYED SCAN
Of EVEN FE\,

r-

VERTJCAL FRONT PORCH-l-iI H

CSYNC~JW

+

VERTICAL SYNC PULSE

---t-

FIRST DISPLAYED SCAN
OF 000 FIELD

I

---------------I--Lf-I1II

I~

r--'2

.1

HPERIOD

HORIZONTAL BLANKING INTERVAL

NOTES
1 In non-mterlaced operation the even 'Ield 18 repeated continuously, and the odd 'Ield
IS not

2·56

--I ~ H I--

*H

~

B l A N K . J U . . -_
- I -_
- _ _ _ _ _ _ _ _ _ _ _ _ VERTICAL BtANKING INTERVAl

2 In Interlaced operation the even 'Ield alternates with the odd field

~
VERTICAL BACK POACH _

Figure 21

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

':tQii"ii,j.'"
PIN CONFIGURATION

DESCRIPTION

FEATURES

The Signetics 2673A and 26738 Video Attrl·
butes Controllers (VAC) are bipolar LSI de·
vices designed for CRT terminals and display
systems that employ raster scan techniques.
Each contains a high speed video shift regis·
ter, field and character attributes lagle, attri·
bute latch, cursor format logic and half dot
shift control.

• 25MHz video dot rate
• Three level current driven (75 ohms)
video output
• Three level encoded TTL video outputs
• Character Ifleld attribute logiC
Reverse video
Character blank
Character blink
Underline
Highlight
Light pen strlke-thru or graphics
control
• Field attributes extend from row to row
• Light or dark field
• Cursor reverse video logic
• Up to 10 dot. per character
• CompOSite blanking for light field
retrace
• Optional field graphics control output
• High .peed bipolar de.lgn
• 40 pin dual In-line package
• TTL compatible
• Compatible with Signetics 2672 PVTC
and 2670 DCGG

The VAC provides control of visual attributes
on a field or character by character. Internal
logic preserves field attribute data from char·
acter row to character row so that an attribute
byte Is not required at the beginning of each
row. The 26738 provides for reverse video,
blank (non·displaY), blink, underline and high·
light attributes and a graphic smode attribute
to work in conjunction with the Signetics
2670 Display Character and Graphics Gener·
ator (bCGG). The 2673A substitutes a light
pen (strike·thru) attribute for the graphics
attribute.
The horizontal dot frequency is the basic
timing input to the VAC. Internally, this clock
is divided down to provide a character clock
output for system synchronization. Up to ten
bits of video dot data are parallel loaded
into the video shift register on each character boundary. The video data is shifted out
on three outputs at the dot frequency. On
the VIDEO output, the data is presented as a
three level signal representing low, medium
and high intensities. The three intensities
are also encoded on two TIL compatible
video outputs. Light or dark screen back·
ground can be selected.

Vee
02
01

=

=
ceo
ee1
ee2
OCLK

CBLANK

TTLVID1
TTLVID2
VIDEO
HOOT
ABLANK
ABUNK

AU'
AHILT

APPLICATIONS

ARVID

• CRT terminal.
• Word proce.slng sy.tems
• Small business computer.

AlTPEN/AGM

TOP VIEW

ORDERING CODE
PACKAGES

Ceramic DIP
Plastic DIP

VCC

COMMERCIAL RANGES
± 5%, VBB = 1.5V ± 10%, TA

= 5V

GRAPHICS ATTRIBUTE
SC2673BC5140
SC2673BC5N40

= O'C to 70"C

LIGHT PEN ATIRIBUTE
SC2673AC5140
SC2673AC5N40

I

BLOCK DIAGRAM
VIDEO ATTRIBUTES CONTROLLER
ceo
ee1
ee2

CHAAACTER

CLOCK COUNTER

DCLK

~~
I

10

vtDeOSHIFT

00-09

'1

t
DOT
DATA

REGISTER
-12BITS-

HOOT
CURSOR
ARVID
ABLANK

AND

..c=-

~
~
DRIVER

VIDEO
ATTRIBUTE
HIERARCHY
LOGIC

DRIVERS

ALTPEN/AGM

AFLG

TTLVID2

BKGND

ABLINK

AHILT
AJJ'

VIDEO
TTLVID1

CBI..ANK

ATTRtBUTE AND
CURSOR CONTROL
LOGIC AND
PIPELINE

AUODE

t

.

--

ACD
BLINK

UL
LL

lPL/GMD

Signetics

BI..ANK

RESET

Vee
VBB

GND

2-57

2

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

l:W il "",,.,?_
PIN DESIGNATION
PIN NO.

TYPE

DCLK

32

I

Dot Clock: Dot frequency input. Video output shift rate.

CCLK

36

0

Character Clock: A submultiple of DCLK. The frequency ranges from one sixth to one twellth
of DCLK, as determined by the state of the CCO-CC2 inputs.

33-35

I

Character Clock Control: The logic state on these three static inputs determine the internal
divide factor for the CCLK output rate. Character clock rates of 6 thru 12 dots per character
may be specified.

DO-D9

37-39,2-8

I

Dot Data Input: These are parallel inputs corresponding to the character I graphic symbol dot
data for a given scan line. These inputs are strobed into the video shift register on the falling
edge of each character clock.

HDOT

27

I

Half Dot Shift: When this input is high, the serial video output is delayed by one half dot time.
This input is latched on the falling edge of each character clock.

CURSOR

14

I

Cursor Timing: This input provides the timing for the cursor video. When high, effectively
reverses the intenSIties of the video and attributes. Cursor position, shape, and blink rate are
controlled by this input.

BKGND

10

I

Background IntenSity: Specifies light or dark video during BLANK and character fields.
Affects the intensities of all attributes.

BLANK

15

I

Screen Blank: When high, this input forces the video outputs to the level specified by the
BKGND input (either high or low intensity). Not effective when CBLANK is high.

CBLANK

31

I

CompOSite Blank: Used with the TTL video outputs only. When high, this input forces the
video outputs to a low intensity state for retrace blanking. When BKGND input is low, or when
using video outputs, this input may be tied low.

ARVID

22

I

Reverse Video Attribute: The intensity of the associated character or field video is reversed.
All other attributes are effectively reversed.

AHILT

23

I

Highlight Attribute: All dot video (including underline) of the associated character or field is
highlighted with respect to the BKGND input and the reverse video attribute.

ABLANK

26

I

Blank Attribute: Generates a blank space in the associated character or field. The blank
space intenSity is determined by the BKGND input, the reverse video attribute, and the
CURSOR input.

ABLiNK

25

I

Blink Attribute: The associated character or field video is driven to the intensity determined
by BKGND and the reverse video attribute when the BLINK input is high.

AUL

24

I

Underline Attribute: Specifies a line to be displayed on the character or field. The line is
specified by the UL input. All other attributes apply to the underline video.

ALTPEN/AGM

21

I

Light Pen Attribute (2673A): SpeCifies a highlighted line to be displayed on the character or
field. The line IS specified by the LPL input.

I

Attribute Graphics Mode (2673): This input is latched and synchronized to provide a field
GMD output for the 2670 DCGG.

MNEMONIC

CC2-CCO

NAME AND FUNCTION

= 0) or field (AMODE = 1) attributes mode.

AMODE

12

I

Attribute Mode: Specifies character (AM ODE

AFLG

13

I

Attributes Flag: The VAC samples and latches the attributes inputs when this input is high. II
field attributes are specified (AMODE = I), the attributes are double buffered on a row basis.
Thus, each scan line of every character row will start with the attributes that were valid at the
end of the previous row.

ACD

11

I

Attribute Control Display: In field attributes mode (AMODE = I), if ACD = 0, the first
character in each new attribute field (the attribute control character) will be suppressed and
only the attributes will be displayed. II ACD = I, the first character and the attributes are
displayed. This input has no effect in character mode (AMODE = 0).

2·58

$ignetics

MICROPROCESSOR DIVISION

JANUARY 1982

SC2673

VIDEO ATTRIBUTES CONTROLLER (VAC)

'm""jj,t·'ti
PIN DESIGNATION (continued)
PIN NO.

TYPE

NAME AND FUNCTION

BLINK

17

I

Blink: ThiS input IS sampled on the failing edge of BLANK to provide the blink rate for the
character blink attribute It should be a submultiple of the frame rate

UL

16

I

Underline: Indicates the scan Ilne(s) for the underline attribute. Latched on the failing edge of
BLANK.

LPLlGMD

19

I

Light Pen Line (2673A): Indicates the scan Ilne(s) for the light pen stnke·thru attribute.
Latched on the falling edge of BLANK.

0

Graphics Mode (2673): This output provides a synchronIZed, latched, field graphics mode
corresponding to the AGM Input This output can be used to control the GM Input on the 2670
DCGG.

MNEMONIC

LL

18

I

Last Line: Indicates the last scan line of each character row Used Internally to extend field
attributes across row boundanes Latched on the failing edge of BLANK. ThiS Input has no
effect in character mode (AM ODE = 0).

VIDEO

28

0

Video: A three level serial Video output which corresponds to the composite dot pattern of
characters, attributes and cursor.

TTLVIDl

30

0

TTL Video 1: ThiS output corresponds to the senal, non·hlghllghted Video dot pattern

TTLVID2

29

0

TTL Video 2: ThiS output corresponds to the highlighted senal Video dot pattern Should be
used with TTLVID 1 to decode a composite Video of three intensities

RESET

9

I

Manual Reset: ThiS active high input initializes the Internal logiC and resets the attnbute
latches. Normally used for testing.

VCC

40

I

Power Supply: +5 Volts

VBB

1

I

Bias Supply: +1.5 Volts

GND

20

I

Ground: OV reference

± 5%
± 10%

FUNCTIONAL DESCRIPTION
The VAC consists of four major sections
(see block diagram). The high speed dot
clock input is divided internally to provide a
character clock for system timing. The par·
allel dot data is loaded into the video shift
register on each character boundary and
shifted into the video logic block at the dot
rate. The six attribute inputs are latched in·
ternally and combined with the serial dot
data to prOVide a three level video source
for the monitor.
A separate BLANK input defines the active
screen area. When BLANK = 0, the video
levels are derived internally by the combina·
tions of dot data, attributes, cursor, and the
state of the BKGND input. Either black or
white background can be selected. Symbols
(dot data) are normally gray and can be
highlighted to white or black as shown in
figure 1. Note that the VIDEO output is in·
verted as referenced to the TTL video outputs.
DUring the inactive screen area (BLANK =
1), the video level produced by the TTL out·
puts is either white (BKGND = 1) or black
(BKGND = 0). A separate composite blank
(CBLANK) input is provided to suppress ras·
ter retrace video when white background is
specified. During the inactive screen area
(BLANK = 1), the video level produced by
the VIDEO output is either black (BKGND =
1) or white (BKGND = 0). For the latter

CCLK
CC2

CC1

CCO

DOTS/CHARACTER

DUTY CYCLE

a
a
a
a

a
a

0
1

6
6
7
8
9
10
11
12

3/3
3/3
4/3
4/4
5/4
5/5
6/5
6/6

1
1
1
1

1
1

a

a
a

a

1
1

1
1

a
1

case, raster retrace Video suppression is
accomphshed by raising the BKGND Input
dUring hOrizontal and vertical retrace inter·
vals For black background, tie BKGND high.
Tie CBLANK Input low for both cases.

Character Clock Counter
The character clock counter divides the fre·
quency on the OCLK input to generate the
character clock (CCLK). The divide factor is
specified by the clock control inputs (CCOCC2) as follows:

Video Shift Register
On each character boundary, the parallel
data (00-09) is loaded into the video shift
register. The data is shifted out least signifi·
cant bit first (DO) by the OCLK. If 11 or 12
dots/character are specified (CC2-CCO =
110 or 111), a a (blank dot) is always shifted

Signetics

out before DO. For 12 dots/ character, a a is
also shifted out after 09. The serial dot data
is shifted into the video logic where it is
combined with the cursor and attributes to
encode three levels of video.

Attribute and Cursor Control
The VAC visual attributes capabilities in·
elude: reverse video, character blank, blink,
underline, highlight, and light pen strike·thru.
The six attributes and the three attribute
control inputs (AMOOE, AFLG, and ACO) are
clocked into the VAC on the falling edge of
CCLK. If AFLG is high, the attributes are
latched internally and are effective for either
one character time (AMOOE = 0) or until
another set of attributes is latched (AMOOE
= 1). The attributes set is double buffered
on a row by row basis internally. Using this
technique, field attributes can extend
across character row boundaries thereby

2·59

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

l;mil"jj,t.ilj
ENCODED VIDEO OUTPUTS

DClK

VIDE01

.~

I

LflJt:

~
I

I
TTLVID1

TTLVID2

HIGHLIGHTED
WHITE ON BLACK

NORMAL
GRAY ON BLACK

REVERSE
GRAY ON WHITE

REVERSE,
HIGHLIGHTED

BLACK ON WHITE

NOTE

1 W:::Whlte
G '" Gray

B "" Black

Figure 1

eliminating the necessity of starting each
row with an attribute set.
When field attribute mode is selected,
(AMODE = 1), the VAG will accommodate
two attribute storage configurations. In one
configuration, the attribute control data is
stored in the refresh RAM, taking the place
of the first character code in the field to be
affected. For this mode, the AGO input is
tied low and blank characters will be dis·
played in the screen positions occupied by
the attribute data (see figure 10). In the sec·
ond configuration, (AGO = 1), the character
codes and attribute data are presented to
the VAG in parallel. In this mode, dot data is
displayed at each character position (see
figure 11).
The CURSOR and the attribute input signals
are pipelined internally to allow for system
propagations (one GGLK for refresh RAM,
one CGLK for dot generator). The attribute
timing signals BLINK, UL, LPL and LL are
clocked into the VAG at the beginning of
each scan line by the falling edge of the
BLANK input. Thus, these signals must be in
their ~roper state at the falling edge of
BLANK preceding the scan line at which
they are to be active (see figure 4).

Video Logic
The serial dot data and the pipelined cursor
and attributes are combined to generate the

2-60

TTLVID2

TTLVIDI

0
0
1
1

0
1
0
1

INTENSITY
Black (or CBLANK)
Gray (on black surround)
Gray (on white surround)
White

NOTE

The TTLVID1 output can be used independently to generate a two level non-highlighted video

three level current source on the VIDEO out·
put. The three levels (white, gray, and black)
are also encoded on the two TTL compatible
outputs TTLVIDI and TTLVID2. The three
levels are encoded as shown.
The video is normally shifted out on the leading edge of the DCLK. When the HOOT input
is asserted, the corresponding dot data is
delayed by one-half DCLK. This half dot
s~ifting, when used on selected lines of
character video, can be used to effect eyepleasing character rounding as shown in
figure 2.

Attribute Hierarchy
The video of each character block consists
of four components as shown in figure 3.
Symbol video is generated from the dot data
inputs 00-09.
Underline video is enabled by the AUL
attribute and is generated when the UL tim-

Signetics

ing input is active. Underline and symbol video are always the same intensity.
Strike-thru video is enabled by the ALTPEN
attribute and is generated when the LPL timing input is active. This video is always
highlighted and takes precedence over the
symbol and underline video. This feature applies to the 2673A only.
Surround video is the absence of symbol,
underline and strike-tnru video or the presence of the non-display attributes (ABLANK
or ABLINK • BLINK).
The relative intensities of the four video
components are determined by the remaining attributes (AHILT, ABLANK, ABLlNK,
ARVID) and the BKGND and CURSOR inputs
as illustrated in table 1.

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

Imli"jj,i.ilj
"AT" SYMBOL WITH AND WITHOUT HALF DOT SHIFTING

I I I I I I

o
o
o

1/ I I I I

0000

0000
000
000
000

0
00
0

0

~0'1--- SURROUND

VIDEO

o 0
0
o 000
o

000
000000

o

VIDEO COMPONENTS OF CHARACTER BLOCK

000

0000

H "'" LINeS SHIFTED

Figure 3

Figure 2

ATTRIBUTES AND CONTROL INPUTS
d = don't care

BKGND5
0
0
0
0
0
0
1
1
1
1
1
1

RELATIVE VIDEO INTENSITIES
W = White, B = Black, G = Gray

REVERSE'

NONDISPLAY'

0
0

0
0

0

1

d
0

,.
1
1
1

0
0

0
0
0

0
0

1
1
1

0
0

1

1

1

AHILT

STRIKE
THRU
VIDE03

SYMBOL OR
UNDERLINE
VIDE03,'

SURROUND
VIDE03

W
W
B
B

G
W
B
G
B
W
G
B
W
G
W
B

B
B
B
W
W
W
W
W
W
B
B
B

1

1

B

d
0

W
B

1

B

d
0

W
W
W
B

1

d

NOTES
1 Reverse::: ARVID. CURSOR
ARVID. CURSOR
2 Non-display:: ABLANK + ABLINK • BLINK
3 See figure 3
Symbol and underline video are always the same mtenslty

+

Reverse sense for VIDEO output

Table 1. ATTRIBUTES HIERARCHY

ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature'
Storage temperature
All voltages with respect to ground

RATING

UNIT

o to +70

·C
·C

-65 to +150
-0.5 to +6.0

V

NOTES

1 StresS8S above those listed under Absolute Maximum Ratings may cause permanent
damage to the device nus is 8tre88 rating only and functional operation of the device
at these or at any other condition above those indicated In the operation section of this
specification is not Implied.
2 For operatmg at elevated temperaturea, the device muat be derated baaed on +l50°C
maximum Junctton temperature and thermal realstance of 60 0 C/W junction to ambient
(ceramic package)

Signetics

2·61

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

'M""n,[.I.
DC ELECTRICAL CHARACTERISTICS

TA" 0'0 to +70'0, VoO" 5V ±5%, Vaa = +1.5V ± 10%3.4·6
LIMITS

PARAMETER
VIL
VIH

Input low voltage
Input high voltage

VOL

Output low voltage
(except VIDEO)
Output high voltage
(except VIDEO)

VOH
VB
VG
Vw

VIDEO black level
VIDEO gray level
VIDEO white level

IlL

Input low current

TEST CONDITIONS

Min

Typ

Max
0.8

V
V

0.4

V

2.0
IOL = 1.6mA
IOH = -100,.A

2.4

RL .. 750 to GNO
RL .. 750 to GNO
RL = 750 to GNO

\

UNIT

V
0
0.225
0.50

V
V
V

-4001

VIN" 0.4V

/LA

-800 10
IIH

Input high current

100
IBB

V00 supply current
VBB aupply current

AC ELECTRICAL CHARACTERISTICS

VIN" 2.4V

20/40 10

/LA

VIN = OV, VOO = max
VBB" max

50
100

mA
mA

TA" 0'0 to +70'0, VOC" 5V ±5%, vBB = +1.5V ± 10%3.4·6
TENTATIVE LIMITS
TEST CONDITIONS

PARAMETER·
Dot clock8
fO
tOH
tOL

Min

Typ

Max
25

frequency
high
low

Setup tlmea to CCIJ(7
BLANK
tBS
BLINK, UL, LPL, LL (ref to BLANK)
tso
Attributea
tSA
Dot deta 00·09
tso
OURSOR
tSK
AFLG
tFS
HOOT
tSH
Hold limes from CC[j(7
BLINK, UL, LPL, LL (ref to BLANK)
tHO
Attributes
tHA
Dot data 00·09
tHO
CURSOR
tHK
AFLG
tFH
HOOT
tHH

UNIT

15
15

MHz
na
na

35
20
35
70
35
50
35

na
na
na
na
na
ns
ns

20
35
0
35
50

35

ns
ns
ns
na
na
n8

Setup timea to 00LK8
BKGNO
tSG
OBLANK
tSB

15
15

na
na

Hold limes from 00LK8
BKGNO
tHG
OBLANK
tHB

15
15

na
na

Oelaytlmes9
GMO from OOLK
tOGM
OOLK from OOLK
too
VIDEO, TTLVI01, and TTLVI02
tov
from OCLK

0L" 150pF

NOTES

3 Parameters are valid over operating temperature range unleas otherwise specified.
4. All voltage measurements are referenced to ground (VSs). All Input signals sWing
between 0 4V and 2 4V All time measurements are referenced at mput voltages of
O.8V, 2.0V and at output voltages of 0 BV, 2.0V 8S appropriate.
5 TYPical values are at + 2S-C, typical supply voltages and typical processing
parameters

2·62

6. See figure 7. Half dot shift feature 18MHz max

7. See figures 4, 5, 6, and 9
8. see figure 8
9 See figures 6 and 7.
10 For DCLK mput

~Ics

\IIW'I .....

60
60

ns
na

75

na

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

IPmli"ii.t.'fj
VAC PIPELINE nMING

..------=~T'---~-_+__-+__ -

... 1--1
-

--

J

~~------------------------

BUNIC,lL
LPi.,LL

ATTRIBUTES'

..

DOTDATAi
"..

BKGND4

,..

2nd

- - - - - ....,~UST=--~,..,.-'~LAST=--r-BK-.....
--

....;""""=_....._c.;;....
::;:;,.....,j"-_ _

_ _ _ _....._.;;""",;;.;;......L.....;""""=_...... _ _ _ _ _ _ .....
NOTES
1. Attnbut•• include: ABLiNK. ABLANK, ARVID. AUL. AHILT, and ALTPEN.
2. One ~ delay lor dot data (obtained from delay through oh....ct... generator).
3 S•• figure 7 for detail timing of VIDEO, mVID1. TTLVID2.
4. Non-active scan time. VIDEO reverts to polarity Hlected by the BKGND Input.

Flgur.4

CURSOR PIPELINE TIMING

Flgur.5

Signatlcs

2·63

MICROPROCESSOR DIVISION

JANUARY 1982

SC2673

VIDEO ATTRIBUTES CONTROLLER (VAC)

'$",,11,[.,,1
CHARACTER (AMODE

= 0),

~~

jS-.-A;__

IA-=~.l--.....JI

1), AND GMD ATTRIBUTE TIMING

I

r~~

'AI\

'FLO

=

FIELD (AMODE

~

-J

-= "____. . __

1

I

?Si"ijI
1---..

I

VIlEO

---,----,--

Gml

_ _ _ _ _ _ _ _ _ _ _~rl------------------------'

......1_ _ __

I

(AlKIDE

==1

L-_ _.;...._ _ _ _ _ _ _ __

) .

NOTE
1 GMD output In 2873 version only See figure 7 for detail timing

Figure 6

VIDEO AND GMD PIPELINE TIMING

DCLK

~ ~~-~------------------VIDEO

TTLVID1,2

~

I

CHARACTER N -

1

CHARACTER N

I
-Jr'''''''
(A":~~ 1)
NOTE
1 GMD output In 2673 version only

2·64

. - - - - - - - - - - ( ___________ _

Figure 7

Signatics

JANUARY 1982

MICROPROCESSOR DIVISION

SC2673

VIDEO ATTRIBUTES CONTROLLER (VAC)
Imil .. lI.i·!,i
BKGND AND CBLANK TIMING DURING INACTIVE SCAN TIME (BLANK

= 1)

2
=
---

DCLK

"OND

---.:::l r~I:r:HG _ _ _ _ _~21_2_ _
\J'- __---Jf
VOl.

~

VIDED ----WHl-"'-- \

BLACK

df.-I-~2~

,r-----W-H'--TE--=D,._

I

Figure 8

HALF DOT SHIFT TIMING

DCLK

:::11:..._ _ _ _ _ _ _
tSH

1----1---1

-= =:: 1 ....._ __

tHH

HOOT~

FIRST PIXEL

CHARN+1

Figure 9

Signetics

2·65

MICROPROCESSOR DIVISION

JANUARY 1982

SC2673

VIDEO ATTRIBUTES CONTROLLER (VAC)
Imfi .. jj,t.lkl
SYSTEM BLOCK DIAGRAM OF THE 2673 IN FIELD ATTRIBUTE MODE
USING THE NARROW RAM (8 WIDE) CONFIGURATION

o CRT CONTROLLER

61~

rpAGEN-i

!

I

~

I

RAM

8

7

I

2KX8

c~o

I

2673

0.0

0.0

Og

Og

7

I~

I
RAM BYTE FORMAT

7

°I

VIDEO

GMO

GMO

J

10 1

LL

'0

--f---,) cA6

f-t-

PAGE 1

0

DCLK

UL

2670

I

REFRESH

eeLK~T
BLANK
BLINK

AGM
ARVID

Vee

AHILT

AUL
ABLINK

ABLANK
AFLG

AMODE

U'Kn

.....--.&--CAUSES
ATTRIBUTE BYTE
AeolI

CHARACTER BYTE

CHAR CODE

TO BE DISPLAYED
AS A BLANK CHARACTER

+

jltlll~IEltIL':::BVTE
~~
~

NOT USED

~

ABLINK

ARVID

AHllT

ABLANK

AUL

,--

;
I

Figure 10

SYSTEM BLOCK DIAGRAM OF THE 2673 IN FIELD OR CHARACTER ATTRIBUTE MODE
USING THE WIDE RAM CONFIGURATION

~,~~-=-~ l~ (

' - ' -_ _ _ _ _- - - '

ceo<

BYTE

.- PAGEN-l

RE:=~SH

TO CRT CONTROLLER

DCLK

BLANK
BUNK

UL

:

LL

2670

2673

I
00
2KXB

PAGE 1

VIDEO

09
j

GMO~-----~ GMO

Vee

lkn
ACO

'PAGEN--l
ATTRIBUTE
RAt.II

2KX8

FIELD ATTRIBUTES

,~

I
I

I
.... foIODE

I
I

~ ~ACTER

I

ATTRIBUTES

PAGE 1

7

...J

u
0

. ,1_IL......JIL......JIL......J!-ll-l-ll-JI ~~~~BUTE

NOTUS::L~~U
t
ABLINK

~

ASLANt<

2·66

t L~R:':·

L

AUL

NOTE

1 For operation

AHILT

Figure 11

Signetics

In

character attnbute mode, tie AFLG high

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEO ATTRIBUTES CONTROLLER (VAC)

SC2673

VIDEO OUTPUT STAGES OF THE 2673

PARTOFH73

Vee

Vee
76n

76n

m.

m.

OlIVER

DRIVER

760

Figure 12

2·67

JANUARY 1982

MICROPROCESSOR DIVISION

VIDEOTEXT TIMING CHAIN (VTC)

SAA5020/SAA5025

PRODUCT BRIEF, contact your Signetlcs sales offices for complete Information.

DESCRIPTION

FEATURES

The Signetics SAA5020/SAA5025 Videotext Timing Chains (VTIC) are MOS
N-channel Integrated circuits which perform the timing functions necessary for
\ the display of viewdata and teletext Information on an Interlaced or non-interlaced
CRT monitor.
The SAA5020/SAA5025 are compatible
with the British videotext standards, currently implemented in systems such as
Prestel, Ceefax, and Oracle. The SAA5020
Is Intended for use with PAL (625 line) television standards, while the SAA5025 is intended for use with systems employing
the NTSC (525 line) television standard.

• Compatible with British videotext
stenderds
• 625 line (PAl) and 525 line (NTSC)
versions
• 40 characters per row, 20 or 24 rows per
screen
• Sync Inputs allow synchronlzallon with
other video sources
• Composite sync output
• Display addressing outputs
• Double height character capability
• Character rounding output to SAA5050
• Single 5·volt power supply

The basic Input to the VTIC Is a 6MHz
clock signal. This is subdivided internally
to produce various synchronized timing
outputs Including the character and dot
rate clocks for the character generator, a
composite sync output for the monitor,
and row address outputs and a column
address clock for the display memory.

TYPE

LINES ROWS LINES/ROW
625
525
525
525

24
20
24
24

10
10
10
8

The VTIC operates from a single 5-volt
power supply and Is packaged in a 24-pin
dual-In-line package.

2·68

RACK
A4
A3

A2
Al
AO

'fIB

I!CS
HIE

m

FS
CRS

DEW

Vee

LOSE
TOP VIEW

Several versions of the VTIC are available
to meet the requirements of various applications. Basic characteristics of the variants are:

SAA5020
SAA5025A
SAA5025B
SAA5025C

PIN CONFIGURATION

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEOTEXT TIMING CHAIN (VTC)

SAA5020/SAA5025

PIN DESIGNATION
MNEMONIC

PIN

TYPE

F6

2

I

6MHz Input. Master clock signal used to derive the basic timing for the display.

FUNCTION

TR6

3

0

6MHz output. Buffered 6MHz dot rate clock output to the SAA5050 character generator.

Fl

4

0

1MHz output. Character clock rate output signal, synchronous with TR6, to the character generator
and other external circuits.

AHS

5

0

Alter hours sync. Active low composite sync output to the display.

FLR

6

I

Fast line reset. Input used to reset the internal line rate counter.

GIR

7

0

General line reset. Line frequency active low signal used for reset and clock functions in the charac·
ter generator and other external circuits.

PL

8

0

Phase lock. Line frequency active low output to the teletext video processor used to phase lock the
6MHz display clock to the incoming television video signal.

CBii

9

0

Color burst blanking. Active low output to the teletext video processor.

FS

10

I

Field sync. Input signal used to reset the field rate counter to maintain correct field sync with incom·
ing video.

CRS

11

0

Character rounding select. Output used by the character generator for character rounding.

LOSE

13

0

Load output shllt register enable. Output signal to the SAA5050 character generator used to reset in·
ternal control flip·flops prior to the start of each line and to define the character display period.

DEW

14

0

Data entry window. Output required by the teletext acquisition circuit and character generator which
defines the period during which data may be extracted from the incoming TV signal and written into
page memory.

TLC

15

I

Transmitted large character. Input from the character generator used to enable the correct display of
large characters under attribute control.

HIE

16

I

High impedance enable. A high input switches the AO-A4 and RACK outputs to their high Impedance
state.

BCS

17

I

Big character select. When low causes all characters to be displayed at double height. Used in con·
junction with TIB input.

TIB

18

I

Top or bottom select. When BCS is low this input controls the row address outputs to cause the top
half to be displayed when low and the bottom half to be displayed when high.

AO-A4

19-23

0

Display memory row address. Provides a binary count sequence during the display period which is in·
cremented every 10 (8 for SAA5025C) lines in normal character mode and every 20 (16 for SAA5025C)
lines in large character mode. If any row contains attributed large characters the address is Incre·
mented by two after 20 (16) lines.

RACK

24

0

Column address clock. lMHz clock used to clock the RAM column address counter. It occurs only
during the active display period of each scan line.

Vee

12

I

+ 5 volts power input.

Vss

1

I

Signal and power ground.

Signetics

2·69

MICROPROCESSOR DIVISION

JANUARY 1982

SAA5020/SAA5025

VIDEOTEXT TIMING CHAIN (VTC)
SAA5020 BLOCK DIAGRAM

TR6

F1

FLR

FS

Voo

Vss

F6

DEW
LOSE
CRS

CBB
PI
GiJI

TIB

AHS

SAA5025 BLOCK DIAGRAM

TR6

F1

FLR

FS

Voo

Vss

F6

DEW
LOSE
CRS
CBB

TIB

PI
GLR
AHS

·SAA5025A
··SAA5025C

2·70

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SAASOSO SERIES

VIDEOTEXT CHARACTER GENERATOR (VCG)
PRODUCT BRIEF, contact your Signetics sales offices for complete information.

PIN CONFIGURATION

DESCRIPTION
The Signetlcs SAA5050 Series Videotext
Character Generators (VCG) are MOS
N·channel integrated circuits which per·
form the attribute decoding and character
generation functions necessary for the
display of viewdata and teletext informa·
tlon on a color or black and white CRT
monitor. They are compatible with the
British vledotext standards, currently 1m·
plemented in systems such as Prestel,
Ceefax, and Oracle.
The VCG incorporates a character gener·
ator read only memory (ROM), decoding
for the 32 videotext control and attribute
characters, video shift registers, and
decoding for some of the remote control
functions generated by compatible reo
mote control circuits. The circuit gener·
ates 96 alphanumeric and 64 graphic
characters.
The basic input to the VCG Is character
data from the display page memory. Each
character code defines a dot matrix pat·
tern. Each character block Is six dots wide
and ten TV lines high, with dot rate of
6MHz and character period of one micro·
second. Alphanumeric characters are gen·
erated on a 5 x 9 matrix, allowing space for
lower case descenders, with one dot be·
tween characters and one TV line between
character rows. The alphanumeric char·
acters are rounded, I.e. a half dot Is In·
serted before or after a whole dot during
the interlace frame of the TV picture In the
presence of a diagonal In the character
matrix.
Each of the 64 graphic characters is decoded to form a 2 x 3 block arrangement
which occupies the complete 6x 10
matrix. Graphic characters may be either
contiguous or separated.

The SAA5050 series devices are func·
tlonally Identical except for the character
font stored In the character generator
ROM. The part types currently available
are:

DE

T

PO
lOSE

TYPE

CHARACTER SET

SAA5050
SAA5051
SAA5052
SAA5055

English
German
Swedish
American

The VCG operates from a single Sovolt
power supply and Is packaged in a 28·pin
dual·in·line package.

FEATURES

=

BLANK

F1

D7

TAe

DUM

vee

GOi

NC

DEW

TlC

TOP VIEW

• Compatible with British videotext
st.nd.rds
• 40 ch.racters par row, 10 or 20 SClin
line, par row
• 98 alphanumeric characters with
rounding
• 84 graphic ch.r.ctera, contiguous or
separ.ted
• Double height and blinking character
Cllpability
• Decoding of control and attribute
ch.ract....
• Decoding of remote control commands
• RGB and monochrome output,
• Overlay and In..rted box Cllpability
• Single S·volt power supply

The character video signals comprise a
monochrome signal and RGB signals for a
color monitor. The monochrome data slg·
nal can be used to Inlay characters Into TV
video. A blanking output is provided to
blank out the TV picture signal for In·
serted box applications.

Sig1e11cs

2·71

JANUARY 1982

MICROPROCESSOR DIVISION

VIDEOTEXT CHARACTER GENERATOR (VCG)

SAA5050 SERIES

PIN DESIGNATION
MNEMONIC

PIN

TYPE

FUNCTION

2

110

Superimpose. As an open drain output, it is low when the superimpose mode is selected to allow
contrast reduction of the TV picture if required. As an input, if held low, the internal 'TV mode' flip·
flop is held in the 'text' state. This is for VDU applications when remote control is not used.

DATA

3

I

Remote control data. This input accepts a 7·bit serial data stream from the remote control decoder.

D1-D7

4-10

I

Character code. 7·bit parallel code from the page memory which specifies alphanumeric, graphic, or
control characters.

DUM

11

I

Remote control clock. Clock used to sample the input at the DATA pin. The positive edge of every
second clock pulse is at the nominal center of the data bit.

GLA

12

I

General line reset. Active low input from the SAA5020lSAA5025 VTIC used for internal synchroniza·
tion of remote control data signals.

DEW

13

I

Data entry window. Input from the SAA5020lSAA5025 VTIC used to reset the AOM row address
counter prior to the display period. Also used to derive the character blink period.

CAS

14

I

Character rounding select. Input from the SAA5020lSAA5025 VTIC used to effect rounding of charac·
ters.

BCS

15

I

Big character select. When low causes all characters to be displayed at double height.

TLC

16

0

Transmitted large character. Output to the VTIC used to enable the correct display of large charac·
ters under attribute control.

TA6

19

I

Dot rate clock. 6MHz clock from the VTIC.

F1

20

I

Character rate clock. 1MHz clock from the VTIC used to latch the incoming character data and to syn·
chronize internal circuits.

Y

21

0

Monochrome output. Open drain serial video output which is in the high state whenever an alpha·
numeric or graphic character is required on the display.

22-24

0

Blue, green, and red outputs. Open drain serial video outputs to the monitor drive circuits. They are
high whenever the corresponding color gun is to be active. The video is a composite of background
and foreground (character) information.

BLANK

25

0

Blanking. Open drain output which provides TV picture blanking. It is active for a duration of a box
when the PO and DE inputs are on. It is also activated permanently when no TV picture is required
(PO low).

LOSE

26

I

Load output shift register enable. Input signal from the VTIC used to reset internal control flip·flops
prior to the start of each line and to define the character display period.

PO

27

I

Picture on. Input used to control the character video and blanking outputs. When high, only text in
boxes is displayed unless in superimpose mode. The input is high for TV picture video on, low for pic·
ture off.
Display enable. Input used to control the videotext display. High for display on, low for display off.

SUP

B,G,A

DE

28

I

Vcc

18

I

+ 5 volts power Input.

Vss

1

I

Signal and power ground.

2·72

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEOTEXT CHARACTER GENERATOR (VCG)

SAA5050 SERIES

SAA5050 BLOCK DIAGRAM

Voo

Vss

NC

18
01

~:".L-r--.

02

03
04

CRS

05
06

07

BCS

~£~~;Md==:!:=~F1

TR6

LOSE
DEW

B

G

BLAN~gjtE~~~~~~~~~~~=:i==:i=~~~~~~~~~~~LJ
DE

PO

Signetics

2·73

MICROPROCESSOR DIVISION

JANUARY 1982

VIDEOTEXT CHARACTER GENERATOR (VCG)

SAA5050 SERIES

SAA5050 CHARACTER SET

~.
b4:b3:b2:b1!,~OL
b6

BITS

II

b5

0

I

I

I

IROW

0

0
0

II

0

0

1

NUL'

OLE'

o

0

1

1

0
2

: 2.

: 3.

o

0

0

o

0

o

1

1

ALPHA"
RED

GRAPHICS
RED

[!]I~ 8~

o

0 1 0

2

ALPHA"
GREEN

GRAPHICS
GREEN

tJl[j 0~

o

0 1

1

3

ALPHA"
YELLOW

GRAPHICS
YELLOW

0:~

0~

o

1

o

0

4

ALPHA"
BLUE

GRAPHICS
BLUE

01~

0iJ

GRAPHICS
MAGENTA

81~

01J

0:0
I

I

o

1

o

1

5

ALPHA"
MAGENTA

o

1 1

0

6

ALPHA"
CYAN

GRAPHICS
CYAN

G:~

o

1 1

1

7

ALPHAn ..

GRAPHICS
WHITE

DI~

1

0

o

0

8

FLASH

CONCEAL
DISPLAY

1

0

o

1

9

STEADY'"

CONTIGUOUS"
GRAPHICS

WHITE

1 0

1 0

10

END BOX"

SEPARATED
GRAPHICS

1 0

1 1

11

START FOX

ESC·

1 1

o

12

NORMAL*"
HEIGHT

BLACK"
BACKGROUND

DOUBLE

NEW
BACKGROUND

1

o

0

1

13

HEIGHT

1

1 1 0

14

SO'

HOLD
GRAPHICS

1

1

15

S1'

RELEASE"
GRAPHICS

1 1

0

1

0

4

0
5

1
1

1

1
0

6 : 6.

1

1

7 : 7.

0 B:Q G~
0 G 01~
GCJ
I
0 0 GI~ ~~
@] 0 G:~ 0=

0~ ~

0

0~

~ ~ 01~ ~1iJ

I
G GI~ G~
0 G 0:~ Gil

~

@]
I 011
01[3 0~ 8
0:~ 0~ 0
GI~ D~ 0
I
ElI~ DI~ 0
D:~ B:~ ~

El 01~
I B-=
0 GICi 0~
0 0:~ G:~
GI~
0 [!]I[)
I
I
EJ 01~ EJICI
EJ 0:~

G:.

1
BI~ Glii
I
I 8 I13 El B I
DI~ GI~ 0 [IJ Gilt Bli
0:~ G:I! @] G
BI~

Control characters shown In columns a and 1 are normally displayed as spaces.
The SAA5050 character set IS shown as an example
*These control cnaracters are reserved for compatlblilty with O1her codes
• *These control characters are presumed before each row beings
Character rectangle

Black represents display color
White represents background

2·74

1
1

o

1

o

3

1

Signetics

0:" I:.

JANUARY 1982

MICROPROCESSOR DIVISION

VIEWDATA INPUT/OUTPUT PERIPHERAL (VIOP)

SAA5070

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

FEATURES

The Signetics SAA5070 Viewdata Input!
Output Peripheral (VIOP) is a complex
microprocessor peripheral integrated cir·
cuit intended for use in wired communications systems, notably viewdata systems
such as Prestel in the UK and Antiope in
France. It is implemented in N-channel
MOS technology and packaged in a 40-pin
dual-in-line package.

• Multiplexed addressldata bus
compatible with scao and SCa4 Series
microcomputers

The VIOP provides several peripheral functions required in viewdata terminals. It
contains an autodialing circuit, a 1200
baud demodulator and asynchronous receiver, and a 75 baud modulator and asynchronous transmitter. The 75 baud modulator and asynchronous transmitter can be
programmed to operate at 1200 baud for
use on private telecommunications systems.

PIN CONFIGURATION

DON

• Modem
- 1200 baud demodulator
- 75/1200 baud modulator
• Line asynchronous receiver and
transmitter
Autodlaling circuit
• Tape recorder 1300 baud modem
(modified KC standard)
• Tape recorder asynchronous receiver
and transmitter
• Remote control receiver and
transmitter
• 1_5 and 60 second timers
Two general purpose 1/0 ports

The input to the VIOP's demodulator is a
filtered and squared FSK signal from the
phone line. This signal is internally processed to produce a pseudo-analog output signal which, after external filtering
and squaring, serves as the input to the
line receiver. The modulator generates a
pseudo-analog output from a serial shift
register which is loaded with patterns
from an internal ROM. Each sine wave
cycle is comprised of a 92-bit pattern
which provides a suitable FSK signal output with minimal external filtering. The
sine wave frequency is determined by the
selected baud rate and the value of the
transmitted data.

CARDET
FSKIN
DOCDI

iiii
07
06

TOP VIEW

The device also includes a tape interface
circuit suitable for the recording and retrieval of character codes of pages of text
from an audio cassette recorder. This is
performed at 1300 baud using a modified
'Kansas City' standard.
Other on-chip facilities include 1.5 and 60
second timers and two general purpose
quasi-bidirectional input/output ports.
One port could, for example, be used as an
interface to a nonvolatile RAM that stores
telephone numbers for autodialing and
user passwords, while the second port
could be used for display control functions.
The SAA5070 has been partitioned for flexibility of use. For example, an external
modem can be used in conjunction with
the internal receiver and transmitter, or
the internal modem can be used independently of the internal receiver and transmitter.

Signetics

2·75

2

MICROPROCESSOR DIVISION

JANUARY 1982

VIEWDATA INPUT/OUTPUT PERIPHERAL (VIOP)

SAA5070

PIN DESIGNATION
MNEMONIC

FUNCTIONS

PIN

TYPE

1

I

IMP

2

0

Dialing pulse output

TFSKIN

3

I

FSK input from tape player

TFSKOUT

4

0

FSK output to tape recorder

FSKOUT

5

0

Line modulator output

TXDATA

6

1/0

Line transmitter output or modulator input

RXDATA

7

I

Line data input

F1

8

I

1MHz clock input

Vss

Signal and power ground

DUMB

9

1/0

Remote control receiver B clock input or transmitter B clock output

DATAB

10

1/0

Remote control receiver B data input or transmitter B data output

DLENB

11

1/0

Remote control receiver B bus enable input or transmitter B bus enable output

DATAA

12

I

DUMA/DLENA

13

I

IBCLCK

14

I/O

62.5kHz clock input or output

PA4-PAO

15-19

1/0

General purpose 1/0 port A

20

I

24-21

1/0

Vcc
PB3-PBO
ALE
DO-D7

25

I

26-33

1/0

Remote control receiver A data input
Remote control receiver A clock or bus enable input

+ 5·volt power input
General purpose 1/0 port B
Address latch enable input from microprocessor
8·bit bidirectional addressldata bus

RD

34

I

Read strobe

WR

35

I

Write strobe

CS

36

I

Chip select

DOCDI

37

1/0

FSKIN

38

I

Filtered and squared line FSK "input

CARDET

39

I

Unfiltered line FSK input

DON

40

0

Dialing in progress output

2·76

Line demodulator output or external carrier detect input

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

SAA5070

VIEWDATA INPUT/OUTPUT PERIPHERAL (VIOP)
BLOCK DIAGRAM OF TYPICAL VIEWDATA RECEIVER

2

r------...,TIMINGr------,
R
SAA5020

VTIC

SAA50S0
VCG

B

G

ROW ADDRESS BUS
MICROPROCESSOR

8049

TER~II~!TING
UNIT (SAFETY AND
ISOLATION
COMPONENTS
DIALING RELAYS
FILTERING)

RECEIVE FSK ,....._ _ _--l"-...,
RETURN FSK

SAA5070
VIIOP

t

TELEPHONE LINE

FROM
COMMAND KEYPAD

Signefics

2·77

~

SIMPLIFIED BLOCK DIAGRAM

<
iii
=e
C

00

IBUSA

RXDATA

DOCDI

DATA A DliM AlOLEN A IBCLCK

r r

7

f37
38
FSKIN

CARDET

14

DATA B DLiM B OLEN B

rr

11

20

LINE
DEMODULATOR
AND CARRIER
DETECT

38

IBUSB

1-....

IBUSA
RECEIVER

LINE RECEIVER

,

IBUSB
RECEIVERI
TRANSMITIER

0

el
"U

;v

0
0

)I'

~

!ll0

Z
"'V

0

c::

-I

VDD

;;:

;v
CJ

<:

en
Z

0c::

-I

"'V
FSKOUT

LINE
MODULATOR

r-

~

TXDATA

!..- ...

l1

fc

5

11

I REGISTERS
STATUS .11

MODE
REGISTER

II

J

COMMAND
REGISTER

36
35

R

I~

34

~
lV

IV
TFSKIN

3

TAPE
DEMODULATOR
AND
CARRIER
DETECT

r-

TAPE
RECEIVER

4

TAPE
MODULATOR

~

TAPE
TRANSMITIER

jjjj

~~

22
"'V
:::z:
m

;IU

»

-<
~

0

07-00

I.:!!

tv

p..
r-v'
V-

TFSKOUT

cs
Viii

33
MICROPROCESSOR
INTERFACE

c::

-I

m

r [1

--"-"

Vss

"'V

Vi
LINE
TRANSMITIER

~
~

"

V-

II

V<-

IV--

PORTA

I

1918 171615

SR1;
TO
SRO

V-

PORTB

Jl

2423 2221

I

DIALING
CIRCUIT

2

40

IMP

DON

--

PAO

PA2

PAl

PA4

PA3

PBO

PB2

PBl

PB3

<:

~

ADDRESS
LATCH AND
REGISTER
ADDRESS
DECODER

q

TIMING

25

I·

8

ALE

,

FI

en

~

UI
0

.....

0

~

'"

CO

'"

Section 3
Single Chip
Microcomputers

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SINGLE CHIP 8-BIT MICROCOMPUTERS

SC80SERIES

PRODUCT BRIEF, contact your Signetics sales offices for complete Information.

PIN CONFIGURATION

DESCRIPTION

FEATURES

The Signetics SCBO Series microcomputers are self-contained, 8-bit processors
which contain the system timing, control
logic, RAM data memory, ROM program
memory (8048149/50 only), and 1/0 lines
necessary to implement dedicated control
functions. All seeo Series devices are pin
and program compatible, differing only in
the size of the on-board program ROM and
data RAM, as follows:

• 8-bit CPU, ROM, RAM, 1/0 in a 4O·pln
package
• 24 quasi bidirectional 1/0 lines
• Two test inputs
• Internal counterltlmer
• Single·level vectored Interrupts: exter·
nal, counterltlmer
• Over 90 Instructions, 70% single byte
• 1.36J'S or 2.5J'S instruction cycle, all In·
structlons one or two cycles
• Expandable memory and 1/0
• Low voltage standby
• TTL compatible inputs and outputs
• Single + 5V power supply

TYPE

RAM SIZE

ROM SIZE

8048
8049
B050
B035
8039
B040

64x8
128x8
258xB
64x8
128xB
258 x 8

1KxB
2KxB
4KxB

-

Program memory can be expanded externally up to a maximum total of 4K bytes
without paging_ Data memory can also be
expanded externally. 110 capabilities can
be expanded using standard devices or
the 8243 1/0 expander.
The SCBO Series processors are designed
to be efficient control processors as well
as arithmetic processors. They provide an
instruction set which allows the user to
directly set and reset individual lines withIn Its 1/0 ports as well as test individual
bits within the accumulator. A large variety of branch and table look-up instructions make these processors very efficient
In Implementing standard logic functions.
Also, special attention has been given to
code efficiency. Over 70% of the instructions are a single byte long and all others
are only 2 bytes long.
An on-chip 8-blt counter is provided which
can count, under program control, either
Internal clock pulses (with a divide by 32
prescaler) or external events. The counter
can be programmed to cause an Interrupt
on terminal count.

vee
T1
P27
P26
P25
P24
P17
P18
P15

\iii

P14

ALE

P13

FUNCTIONAL DESCRIPTION

DBO

P12

The following is a general functional
description of the seeo Series microcomputers. Refer to the block diagram.

DB1

P11

PROGRAM MEMORY
Resident program memory consists of up
to 4K bytes of ROM. The program memory
is divided Into pages of 258 bytes each. As
shown In the memory map, figure 1, program memory Is also divided Into two
2048-byte banks, MBO and MB1. 4096
bytes can be addressed directly. If more
memory Is required, an 1/0 port can be
used to address locations over 4095.

DB2

P10

DB3

V••

DB4

PROG

DB5

P23

DB8

P22

DB7

P21

vss

P20
TOP VIEW

There are three locations in program memo
ory of special importance. These locations
contain the first instruction to be ex·
ecuted upon the occurrence of one of
three events.
LOCATION

EVENT

0

Activation then deactivation of the ~ line.
Activation of the jjij'f line
when the external Interrupt is enabled.
An overflow of the tlmerl
counter if the TIC interrupt
is enabled.

3

7

)

3·2

Signe1ics

MICROPROCESSOR DIVISION

JANUARY 1982

SC80SERIES

SINGLE CHIP 8-BIT MICROCOMPUTERS
PIN DESIGNATION
MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

DBO-DB7

12-19

I/O

Bus. Bidirectional 110 port can be read from or written into using the RD orWR strobes. This port can
also be statically latched.
Contains the 8 lower address bits during an access of external memory and receives the addressed
instruction under control of PSEN. PSEN, ALE, RD, and ijijf! determine whether the access is an in·
struction fetch or a RAM read/write.

Pl0-P17

27-34

I/O

Port 1. 8·bit quasi·bidirectionalliO port.'

P20-P27

21-24,
35-38

I/O

Port 2. 8·bit quasi·bidirectionall/O port.' P20-P23 contain the 4 higher order address bits during an
access of external program memory and also serve as a 4·bit I/O expander bus for the 8243.

25

I/O

Output strobe (active low) for the 8243 I/O expander.

TO

1

110

Input pin sensed using the JTO and JNTO instructions.
Clock output pin when designated as such by the ENTO ClK instruction.

T1

39

I

Input pin sensed using the JTl and J NTl instructions. Can be designated as the timer/counter input
by the STRT CNT instruction.

INT

6

I

Interrupt Input pin. When low causes interrupt if interrupt is enabled. Can also be used as an input
which is testable with the JNI instruction. Interrupt is disabled during and aiter a RESET.

RESET

4

I

Reset Input pin is that used to initialize the microcomputer. Active low. Internal pullup -75kIl 2 .
During program verification the address is latched by a "0" to "1" transition on RESET and the data
at the addressed location is output on BUS.

ALE

11

0

Address latch enable. Occurs each clock cycle and is useful for clocking and sampling.
During external program or data memory access, ALE is used to strobe the address information
multiplexed on the DBO-DB7 outputs.

RD

8

0

Read strobe. Active low strobe used to gate data onto BUS lines when reading from an external
source.

WR

10

0

Write strobe. Active low strobe used to write data from BUS lines to an external destination.

EA

7

I

External access Input. When high forces instruction fetches from external memory. Internal pullup
-10MIl.

PSEN

9

0

Program store enable. Active low strobe that occurs only during a fetch from external program
memory.

SS

5

I

Single step. Active low input which is used with ALE to cause the microcomputer to execute a single
instruction. Internal pullup -300kll.

XTAll

2

I

One side of crystal (or l) input for internal oscillator. Can also be used as an input for an external
timing source2 .

PROG

XTAl2

3

I

Other side of crystal.

Vss

20

I

Circuit ground.

Vcc

40

I

Power Input, + 5VDC.

• Voo

26

I

RAM power input; low power standby pin.

NOTES
1 Each pm on these ports can be aSSigned, under program control, to be an Input or
an output A pin Is designated as an Input by writing a logic "1" to the pm RESET
sets all PinS to the Input mode Each pin has an Internal pullup of approximately

50kn
2 Non-standard TTL VIH

Signetics

3·3

3

MICROPROCESSOR DIVISION

JANUARY 1982

SC80SERIES

SINGLE CHIP 8·BIT MICROCOMPUTERS
BLOCK DIAGRAM

P20

OBO

P27

DB7

RESIDENT

ROM

(8048149/50 ONLy)

PORT 1
BUS

.-________~------~------~--------~----~~----------~~--v1B~:~R
LATCH

REGISTER 2
REGISTER 3
REGISTER 4

B
DD

----. RAM SUPPLY

POWER
SUPPLY

REGISTER 5

VS£. + 5V MAIN SUPPLY

REGISTER 6

V~GND

REGISTER 7

8 LEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK

DATA STORE

RESIDENT
RAM ARRAY
TIMING
OUTPUT

INTERRUPT

INITIALIZE

EXPANDER
STROBE

CPU
OSCILLATOR
PROGRAM SINGLE READIWRITE
STEP
STROBES
MEMORY
XTAL
MEMORY
SEPARATE
ENABLE
ADDRESS
LATCH

ENABLE

3·4

Signefics

PlO

JANUARY 1982

MICROPROCESSOR DIVISION

SC80 SERIES

SINGLE CHIP 8·BIT MICROCOMPUTERS
DATA MEMORY
Resident data memory, as shown in figure
2, consists of up to 256 bytes of RAM. All
locations are indirectly addressable by
either of two RAM pOinter registers at
locations 0 and 1. The first eight locations
of RAM (0-7) are designated as working
registers and are directly addressable by
several instructions.

By selecting register bank 1, RAM locations 24-31 become the working registers,
replacing those in register bank 0 (0-7).
RAM locations 8-23 are designated as the
stack. Two locations (bytes) are used per
CALL, allowing nesting of up to eight sub·
routines.
If additional RAM is required, up to 256
bytes may be added and addressed direct·
Iy using the MOVX instructions. If more
RAM is required an I/O port can be used to
select one (256-byte) bank of external
memory at a time.

PROGRAM COUNTER AND
STACK
The Program Counter (PC) is a 12-bit
counter/register that points to the location from which the next instruction is to
be fetched. The 8048 and 8049 will automatically address exernal memory when
the boundary of their internal memory is
exceeded. All processors access external
memory if EA is high.
An interrupt or CALL to a subroutine
causes the contents of the program
counter to be stored in one of the 8 register pairs of the program counter stack. The
pair to be used is determined by a 3-bit
stack pointer which is part of the Program
Status Word (PSW). Data RAM locations 8
through 23 are available as stack registers
and are used to store the program counter
and 4 bits of PSW. The stack pOinter, when
initialized to 000, pOints to RAM locations
8 and 9. The first subroutine jump or inter-

rupt results in the program counter contents being transferred to locations 8 and
9 of the RAM array. The stack pointer is
then incremented by one to point to locations 10 and 11 in anticipation of another
CALL. Nesting of subroutines within subroutines can continue up to eight times
without overflowing the stack. If overflow
does occur the deepest address stored
(location 8 and 9) will be overwritten and
lost since the stack pOinter overflows
from 111 to 000. It also underflows from
000 to 111.
The end of a subroutine, which is signalled by a return instruction (RET or
RETR), causes the stack pointer to be
decremented and the contents of the resulting register pair to be transferred to
the program counter.

DATA MEMORY MAP
PROGRAM MEMORY MAP

255

8040/8050
USER RAM

~'D

128
127

64
63

-BI~'."

-,

-

2047

.mB

~

32
31

SEL MBO

24
23

1023

;:

Y
z

0

lOCATION7-TIMER

I--------

4
3
2
1

'-'-

-

8
7
6
5

~O

-

-

INTERRUPT VECTORS
PROGRAM HERE

8
7

0

ADDRESS

32x 8
BANK 1
WORKING

~
DIRECTLY

REGISTERS

ADDRESSABLE

8x8

WHEN BANK 1

---'R1"------'RO,----

BANKO
WORKING
REGISTERS
8x8

LOCATION 3-EXTERNAl
INTERRUPT VECTORS
PROGRAM HERE

RESET VECTORS
716151413121'10 ----- PROGRAM HERE

64x 8
803518048
USER RAM

IS SELECTED

-.-J
ADDRESSED
INDIRECTLY
THROUGH
R1 OR RO
(RO' OR R1 ')

8 LEVEL STACK
OR
USER RAM
16)( 8

~

i.

128 x8
803918049
USER RAM

----------~----

~
DIRECTLY
ADDRESSABLE
WHEN BANK 0
ISSELErED

IN ADDITION, RD OR R1 (RO' OR R1 ') MAY
BE USED TO ADDRESS 256 WORDS OF
EXTERNAL RAM

Figure 2

Figure 1

Signetics

3·5

3

MICROPROCESSOR DIVISION

JANUARY 1982

SC84 SERIES

SINGLE CHIP 8-BIT MICROCOMPUTERS
PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

FEATURES

The Signetics SC84 Series microcomputers are self-contained 8-bit processors
which contain the system timing, control
logic, RAM data memory, ROM program
memory, and serial and parallel 1/0 lines
necessary to implement dedicated control
functions. All SC84 Series devices are pin
and program compatible, differing only in
the size of the on-board program ROM and
data RAM, as follows:

• 8·bit CPU, ROM, RAM, I/O In a 28·pln
package
• 20 quasi bidirectional I/O lines
• Two test Inputs, one with zero voltage
crossover detection

TYPE

RAM SIZE

ROM SIZE

8400
8405
8410
8420
8440

128x8
32x8
64x8
64x8
128x8

512x8
1Kx8
1Kx8
4Kx8

-

PIN CONFIGURATION

• Serial I/O hardware
• Internal counter/timer
• Single· level vectored interrupts: external, counterltimer, serial I/O
• Over 90 instructions, 70% single byte
• 6.77"s Instruction cycle, all instructions
one or two cycles
• High current drive on four outputs
• TTL compatible Inputs and outputs
• Single + 5V power supply

The 8400 is a ROM-less piggyback version
which can be used with standard EPROMs
for emulating any of the other devices of
the family.
The SC84 Series processors are designed
to be efficient control processors as well
as arithmetic processors. They provide an
instruction set which allows the user to
directly set and reset individual lines within its I/O ports as well as test individual
bits within the accumulator. A large variety of branch and table look-up instructions make these processors very efficient
in implementing standard logic functions.
Also, special attention has been given to
code efficiency. Over 70% of the instructions are a single byte long and all others
are only 2 bytes long. The instruction set
is based on that of the SCBO Series.
A special feature of the SC84 Series is the
serial I/O interface. This eliminates the
heavy processing load imposed upon a
normal microcomputer performing serial
data transfer, and facilitates the design of
multi-microcomputer systems using serial
communications.
An on-Chip 8-bit counter is provided which
can count, under program control, either
internal clock pulses (with an optional
divide by 32 prescaler) or external events.
The counter can be programmed to cause
an interrupt on terminal count.

3·6

vee
P21
P20
P17
P16
P15
P14
P13
P12
P06

P11
P10

P07
INT/TO

RESET

T1

XTAl2

vss

XTAl1
TOP VIEW

PIN DESIGNATION
MNEMONIC

PIN

FUNCTION

POO-P07
P10-P17
P20-P23

4-11
18-25
26,27,1,2

8-bit quasi bidirectional I/O port (Port 0)
8-bit quasi bidirectional I/O port (Port 1)
4-bit quasi bidirectional 1/0 port (Port 2); P23 is the serial
data input/output in serial I/O mode
Bidirectional clock for serial I/O
External interrupt input (active iow); testable using the JTO,
JNTO instructions.
Input pin testable using the JT1, JNT1 instructions. Can be
designated the event counter input, using the STRT CNT instruction. Also allows zero crossover sensing of slowly
moving AC inputs.
Input. Used to initialize the processor (active high).
Connection to timing component (usually a crystal) which
determines the frequency of the internal oscillator. Aiso the
input for an external clock source.
Connection to other side of timing component.
Ground
+ 5V power supply

SCLK
INTITO

3
12

T1

13

RESET
XTAL1

17
15

XTAL2

16
14
28

Vss
Vee

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SINGLE CHIP 8-BIT MICROCOMPUTERS

SC84 SERIES

BLOCK DIAGRAM

SERIAL OATA/P23
(PIN 2)

P07-POQ

P17-P10

SCLK
(PIN 3)

RESIDENT ROM
8405
8410·
8420
8440

O,5K
1 K
2 K
4 K

=

BYTES
BYTES
BYTES
BYTES

CLOCK

REGISTER 2
REGISTER 3

INSTRUCTION
REGISTER
AND

REGISTER 4
REGISTER 5

DECODER

o

POWER {

REGISTER 7

E

8 LEVEL STACK
(VARIABLE LENGTH)

o
o

-

TEST 0

Vee

SUPPLY

REGISTER 6

E
C

OPTIONAL SECOND
REGISTER BANK

Vss
---+- GND

CONDITIONAL
BRANCH
LOGIC

DATA STORE
ACC

CONTROL AND TIMING

iNTlTO

RESET

t

t

INTERRUPT

INITIALIZE

ACe BIT
TEST

XTAL1

RESIDENT RAM ARRAY

t

8400· 128 BYTES
8405: 32
8410 64
8420· 64
8440 128

OSCILLATOR

XTAL

Signetics

BYTES
BYTES
BYTES
BYTES

3·7

3

JANUARY 1982

MICROPROCESSOR DIVISION

SINGLE CHIP 8-BIT MICROCOMPUTERS

SC84 SERIES

Serial 1/0
The 8400 serial I/O interface has been
designed to eliminate the heavy processing load imposed upon a normal microcomputer performing serial data transfer.
Whereas a normal microcomputer must
regularly monitor the serial dat bus for the
presence of data, the 8400 serial I/O interface detects, receives and converts the
serial data stream into parallel format
without interrupting the execution of the
current program. An interrupt is sent to
the microcomputer only when a complete
byte Is received. Then, the microcomputer
reads the data byte In one instruction.
Likewise, for transmission, the serial I/O
interface performs parallel-to-serial conversion and subsequent serial output of
the data and the microcomputer is only interrupted in the execution of its programmed tasks when a complete byte has been
transmitted.
The design of the 8400 serial I/O system
allows any number of 8400 devices to be

3·8

Interconnected by the two-line serial bus.
The ability of any two devices to communicate, without interrupting the operation of
any other devices on the bus, is an out·
standing attribute of the system. This is
achieved by allocating a specific l·bit address to each device and providing a system whereby a device reacts only to messages prefixed with its own address or the
'general call' address. Address recognition is performed by the interface hardware so that operation of the microcom·
puter need only be interrupted when a
valid address has been received. This
saves significant processing time and
memory space compared with a conven·
tional microcomputer employing a software serial interface. When the address·
ing facility is not required, for instance in
a system with only two microcomputers,
direct data transfer without addressing
can be performed.
In multimaster systems, an automatically

Signetics

invoked arbitration procedure prevents
two or more devices from continuing
simultaneous transmission.

Serial 1/0 Interface
Figure 1 shows the serial I/O interface.
The clock line of the serial bus has exclusive use of pin 3 (SCLK), while the data line
shares pin 2 (serial data) with the I/O line
P23 of Port 2. When the serial I/O is enabled, P23 is disabled as a parallel port
line.
The microcomputer and interface com·
municate via the Internal microcomputer
bus and the serial interrupt request line.
Data and information controlling the
operation of the interface are stored in
four registers:
-

Data shift register SO
Serial I/O interface status word SI
Serial clock control word S2
Address register.

1/0 LOGIC DIAGRAM

en

Z

8400 SERIES SERIAL 110 LOGIC

G>
rm

0

=v

INTREQ

II1I I

~

DATA

CONTROL

.6nnDr:\C:~

~
nATA

,

.

·1

I":nUD.6D.6TnD

,

.

~
."

.,

R

m

~

0
::z: .,0

INTERRUPT
LOGIC
SERIAL DATA
(PIN 2)

s::

()

C»
•
W

<:
en

(5
Z

=i

LENSI
DISS1

3:

0;U

,

0
0
0
3:

~WRSOI

.

SHIFT REGISTER

-

RDSO

"V

1

AL I

I I

I LRB I

IAAS~ADOI

I PIN

....

c:

I

m

;U

en

oen

INTERNAL MICROCOMPUTER BUS

BIT 0
SCLK
(PIN 3)

ESO

WRSI

AL

RDSI

PIN
CLOCK
SYNC
LOGIC
AND
CONTROL

en

0
INTERNAL CLOCK

~

C»
~

en
m
!!
m
en

Figure 1

CD

1111wll~

'-

»z
»c

~

:0
00
I\)

I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Section 4
SC68000 16-Bit Family

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

16-811 MICROPROCESSOR

SC68000

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

FEATURES

Advances in semiconductor technology
have provided the capability to place on a
single chip a microprocessor at least an
order of magnitude higher in performance
and circuit complexity than has been previously available. The SCS8000 is the first
of a family of such VLSI microprocessors
from Signetics. It combines state-of-theart technology and advanced circuit design techniques with computer sciences
to achieve an architecturally advanced
lS-bit microproceSSing unit. The SCS8000
offers seventeen 32-bit registers in addition to the 32-bit program counter and a
lS-bit status register (see the programming model in figure 1). The first eight
registers (00-07) are used as data registers for byte (B-bit), word (1S-bit), and long
word (32-bit) data operations. The second
set of seven registers (AO-AS) and the system stack pointer can be used as software
stack pointers and base address registers.
In addition, these registers can be used
for word and long word address operations. All 17 registers can be used as index
registers.

•
•
•
•
•
•

PIN CONFIGURATION

32-bit data and address registers
16-megabyte direct addressing range
56 powerful instruction types
Operations on five main data types
Memory mapped 1/0
14 addressing modes

05
06
07
D8
09
Dl0
D11
012
D13

=

Dl.

BGACK

GND

BG

D1S

BR

A23

Vee

A22

ClK

A21

GND

Vee

HALT

A20

RESET

A19

VMA

A18

PROGRAMMING MODEL
31

16 15

A17
VPA

A16

DO

BERR

A1S

Dl

IPl2

Al'

D2

IPLl

A13

8 7

D3

IPlO

A12

FC2

A11

DS

FCl

Al0

06

FCO

A9

07

Al

A8

A2

A7

A3

A6

D.

31

lIl-

ff-

I-

EIGHT
DATA
REGISTERS

16 15

I

AO

-

I
I

-

I

-

I

I
I
I
I
I

Al
A2
A3
A.

SEVEN
ADDRESS
REGISTERS

AS

-

A6

USER STACK POINTER
~--------------------l

TWO STACK
POINTERS

PROGRAM
COUNTER

15

I

8 7

SYSTEM BYTE:

0
USER BYTE

I

STATUS
REGISTER

Figure 1

4·2

AS

A'

Signetics

TOP VIEW

MICROPROCESSOR DIVISION

JANUARY 1982

16·BIT MICROPROCESSOR
A 23-bit address bus provides a memory
addressing range of greater than 16 megabytes. This large range of addressing
capability, coupled with a memory management unit, allows large, modular programs to be developed and operated without resorting to cumbersome and time
consuming software bookkeeping and
paging techniques.

Table 1.

Bits
BCD digits (4 bits)
Bytes (8 bits)
Word (16 bits)
Long words (32 bits)

In addition, operations on other data
types, such as memory addresses, status
word data, etc., are provided for in the instruction set. The 14 addressing modes
(see table 1) include six basic types:
•
•
•
•
•
•

Register direct
Register indirect
Absolute
Immediate
Program counter relative
Implied

Included in the register indirect addressing modes is the capability to do postIncrementing, predecrementing, offsetting, and indexing. Program counter relative mode can also be modified via indexing and offsetting.

DATA ADDRESSING MODES

MODE

Five basic data types are supported:
•
•
•
•
•

SC68000

GENERATION

Register Direct Addressing
Data Register Direct
Address Register Direct

EA=Dn
EA=An

Absolute Data Addressing
Absolute Short
Absolute Long

EA = (Next Word)
EA = (Next Two Words)

Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset

EA=(PC)+d '6
EA = (PC) + (Xn) + d s

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

EA=(An)
EA = (An), An_An + N
An .... An-N, EA=(An)
EA=(An)+d ,6
EA = (An) + (Xn) + d s

Immediate Data Addressing
Immediate
Quick Immediate

DATA = Next Word(s)
Inherent Data

Implied Addressing
Implied Register

EA = SR, USP, SP, PC

NOTES
EA = Effective Address
An = Address Register
Dn = Data Register
Xn = Address or Data Register used as Index Register
SR = Status Register
PC = Program Counter

( )= Contents of
dB = B·btt Offset (displacement)
d16 = 16·blt Offset (displacement)
N = 1 for Byte, 2 for Words and 4 for Long Words
~-=

Replaces

Signetics

4·3

MICROPROCESSOR DIVISION

JANUARY 1982

16-811 MICROPROCESSOR
The SC68000 instruction set is shown in
table 2. Some additional instructions are
variations, or subsets, of these and appear
in table 3. Special emphasis has been
given to the instruction set's support of
structured high·level languages to facilitate ease of programming. Each instruction, with a few exceptions, operates on
bytes, words, and long words, and most instructions can use any of the 14 addressing modes. Combining instruction types,
data types, and addressing modes, over
1000 useful instructions are provided.
These instructions include signed and unsigned multiply and divide, 'quick' arith·
metic operations, BCD arithmetic and expanded operations (through traps).

SC68000
Table 2.
MNEMONIC

I

DESCRIPTION

ABCD
ADD
AND
ASL
ASR

Add Decimal with Extend
Add
Logical AND
Arithmetic Shift Left
Arithmetic Shift Right

Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register against Bounds
Clear Operand
Compare

DBcc
DIVS
DIVU

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EXG
EXT

Exclusive OR
Exchange Registers
Sign Extend

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSL
LSR

Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

MOVE
MOVEM
MOVEP
MULS
MULU

Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

OR

Logical OR

PEA

Push Effective Address

RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

4·4

INSTRUCTION SET

"

Reset External Devices
Rotate Left without Extend
' Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Retu rn and Restore
Return from Subroutine

SBCD
Scc
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

UNLK

Unlink

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SC68000

16·811 MICROPROCESSOR
Table 3.
INSTRUCTION TYPE

VARIATIONS OF INSTRUCTION TYPES
DESCRIPTION

VARIATION
ADD
ADDA
ADDQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND

AND
ANDI

Logical AND
AND Immediate

CMP

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR

EOR
EORI

Exclusive OR
Exclusive OR Immediate

MOVE

MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move
Move
Move
Move
Move
Move

NEG

NEG
NEGX

Negate
Negate with Extend

OR

OR
ORI

Logical OR
OR Immediate

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Subtract
Subtract
Subtract
Subtract
Subtract

ADD

Signetics

Address
Quick
Immediate
with Extend

Address
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer

Address
Immediate
Quick
with Extend

4·5

JANUARY 1982

MICROPROCESSOR DIVISION

SC68120

INTELLIGENT PERIPHERAL CONTROLLER
PRODUCT BRIEF, contact your Signetlcs sales offices for complete information.

PIN CONFIGURATION

DESCRIPTION

FEATURES

The SC68120 Intelligent Peripheral Con·
troller (IPC) is a general·purpose, user·
programmable peripheral controller. It
contains a system interface, an 8·bit CPU,
a serial communications interface, 21
parallel 110 lines, a 16·bit timer, 2048 bytes
of ROM, and eight operating modes. In ad·
dition, the SC68120 features 128 bytes of
dual·ported RAM and six semaphore
registers that are accessible to both the
internal CPU and an external processor or
device through the system interface. The
SC68120 provides all the control signals
necessary to interface with the asyn·
chronous bus of the SC68000.

• Bus compatible with the 16·blt SC6BOOO
and with B·blt microprocessors
• Bus compatible with B·bit peripherals
• TTL compatible 110
• B·blt CPU
• 2K bytes ROM
• 12B bytes dual·ported RAM
• Six shared semaphore registers
• 16·blt timer
• 21 parallel 110 and two handshake lines
• Serial communications Interface
• Interrupt capability
• Operates In slngle·chlp mode or ex·
pandable to 64K·byte addressing range
• DMA capability
• B)( B·blt multiply

PROGRAMMING MODEL

K----~ -__ ~U~ -- -..!---- 3
15

1'5

8·BITACCUMULATORSAAND B
D O O R la-BIT DOUBLE ACCUMULATOR D

I

o INDEX REGISTER (X)

'1IT!
I

1'5

SP

1'5

PC

o

7

0

o STACK POINTER (SP)

I

PROGRAM COUNTER (PC)

H 1 N Z V C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
INTERRUPT
HALF CARRY (FROM BIT 3)

4·6

Signetics

RESEi'
P24
P23
P22
P21
P20
SC2
SCI
P30
S.AS

P31

S.A4

P32

Vee

P33

S.A3

P34

S.A2

P35

S.Al

P36

S.AO

P37

S.DO

P40

S.Dl

P41

S.D2

P42

S.D3

P43

5.04

P44

S.DS

P4S

5.06

P46
P47

S.D7
TOP VIEW

JANUARY 1982

MICROPROCESSOR DIVISION

SC68120

INTELLIGENT PERIPHERAL CONTROLLER
BLOCK DIAGRAM

CS

8._
DTACK
S.DO
5.Dl

S.D2
S.D3
5.D4
5.D5

S.De
5.D7

.,::>
Ii:

2

..

lI!

w

E

4

5.AO
SAl
5.A2
S.A3
S.M
5.AS
S.AI
S.A7
DATA

ADDRESS

SINGLE CHIP
EXPANDED NON·MULTIPLEXED

EXPANDED MULTIPLEXED

I

gggggggg

gggggggg9~

I !;UUSUU
I !;!8iHISESa ..

In

:c~:a:l~:O!C:il};
~~5~~~~:I

i

ii:UUiU ..

~UU~Uii!C

iUnU!!U
SUMMARY OF OPERATING
MODES
Common to all modes:
System bus Interface
Reserved register area
Six semaphore registers
I/O port 2
16·bit programmable timer
Serial communications interface
128 bytes of dual·ported RAM
Single chip mode - Mode 7
2048 bytes of ROM (Internal)
Port 3 is a parallel I/O port with two
control lines
Port 4 is a parallel I/O port
SC1 Is input strobe 3 (IS3)
SC2 Is output strobe 3 (OS3)

Expanded non·multiplexed mode Mode 5
2048 bytes of ROM (internal)
256 bytes of external memory space
Port 3 is an a·bit data bus
Port 4 Is an address bus
SC1 is Input/output select (lOS)
SC2 Is read/write (R/W)
Expanded multiplexed modes - Modes 1,
2,3,6
Four memory space options (64K ad·
dress space);
(1) MOOS compatible
(2) No ROM
(3) External vector space
(4) ROM with partial address bus

External memory space accessed
through:
Port 3 as a multiplexed address/data
bus
Port 4 as an address bus (high)
SC1 Is address strobe (AS) Input
SC2 is read/write (RIW)
Test modes - Modes 0, 4
Expanded multiplexed test mode - may
be used to test RAM and ROM
Single chip and non·multlplexed test
mode - may be used to test ports 3
and 4 as I/O ports

Sigletics

-----.-~

--

--

4·7

-.--.

..

- . - - - - ---.

MICROPROCESSOR DIVISION

JANUARY 1982

SC68230

PARALLEL INTERFACE/TIMER
PRODUCT BRIEF, contact your Signetics sales offices for complete Information.

DESCRIPTION

FEATURES

The SC68230 ParaliellnterfacelTlmer (PIIT)
is a general·purpose, programmable parallel interface device which meets most
system parallel 1/0 and timing needs. The
parallel interfaces of the PI/T may be used
to connect a wide variety of peripheral
devices to the SC68000 bus. The PI/T can
be programmed to generate interrupt requests to the SC68000, or DMA requests
to the SC68450 Direct Memory Access
Controller, on demand of the peripheral.
No external logic Is needed to connect the
PI/T to the DMAC or to the SC68000. The
PI/T also provides complete port and timer
status information.

24 programmable I/O lines
o Port modes include:
Bit mode
Unidirectional B·blt mode
Unidirectional 16·blt mode
Bidirectional B-blt mode
Bidirectional 16·bit mode
o Selectable handshaking modes
o 24·blt programmable timer
o Several timer modes
o Contains interrupt prioritization logic
o Unique interrupt vectors for each source
o Supports Interrupt and DMA service
requests
o Contains port and timer status registers
o SC680DO bus compatible

The SC68230 contains two multi-mode,
double-buffered 1/0 ports (Port A and Port
B), a third &bit 1/0 port, and a 24-blt programmable timer. The PI/T also contains
flexible prioritization logic for generating
unique interrupt vectors. Autovectored interrupts are also supported. Port C pins
provide either another port pin or special
functions consisting of Interrupt, timer, or
direct memory access control lines.

4·8

FUNCTIONAL DIAGRAM

o

PAD-PA7

PBO-P87

PORT c/DMAREQ
PORT c/INTR
PORTC/IACK
PORTC/TIMER
PORT C/TIMER
PORTC/TIMER
PORTC
PORTC

CA1
CA2
C81
C82

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

SC68450

DMA CONTROLLER
PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

FEATURES

The SC68450 Direct Memory Access Con·
troller (DMAC) offers the system designer
unparalleled performance where both
speed and flexibility In data transfer are
required. Sophisticated chaining tech·
niques, memory-to-memory block transfers, and variable bus bandwidth utilization result in optimum data transfers. Internal 32-bit address registers provide
upward software compatibility with future
SC68000 family processors

• Compatible with both SC68000 family
and B-blt peripherals
• Four fully-Independent channels
• Single or dual address transfers
• Byte, word, or long word transfers
• Memory-to-memory block transfers
• Supports both chained and unchained
operations
• Transfer rates up to 4 megabytes per
second
• Supports vectored Interrupts
• Supports array or linked array chaining
• 16-blt data bus
• Programmable priorities

FUNCTIONAL DIAGRAM

A8-A23/
00-D15
A1-A7

REOD
ACKO
PCLD

RiW
Cli
All
UDS
LDS
DTACK

lIEQi

£K1
PCL1

Iml2
~

PCL2

lffil3
ACK3
PCL3

OWN

iiU
HIBYTE

IiiiEIiI
DliIII

Signetics

ClK

FCD

Vee

FC1

GND

FC2

4-9

4

JANUARY 1982

MICROPROCESSOR DIVISION

SC68450

DMA CONTROLLER

INTERNAL ORGANIZATION

CHANNEL
STATUS REGISTER

CHANNEL

STATUS RECJISTER

CHANNEL
ERROR REGISTER

CHANNEL

ERROR REGISTER
DEVICE
CONTROL REGISTER

DEVICE
CONTROL REGISTER

OPERATION
CONTROL REGISTER

OPERATION
CONTROL REGISTER

SEQUENCE
CONTROL REGISTER

SEQUENCE
CONTROL REGISTER
CHANNEL
CONTROL REGISTER

CHANNEL

CONTROL REGISTER
NORMAL

NORMAL
INTERRUPT VECTOR

CHANNEL 0

INTERRUPT VECTOR

PRIORITY REGISTER

ERROR
INTERRUPT VECTOR
CHANNEL
PRIORITY REGISTER

MEMORY
FUNCTION CODES

MEMORY
FUNCTION CODES

DEVICE

DEVICE
FUNCTION CODES

ERROR
INTERRUPT VECTOR
CHANNEL

FUNCTION CODES
BASE
FUNCTION CODES

BASE
FUNCTION CODES

15

MEMORY TRANSFER COUNTER

I

I

BASE TRANSFER COUNTER

MEMORY ADDRESS REGISTER

MEMORY TRANSFER COUNTER
BASE TRANSFER COUNTER

"

"

I
I

31

MEMORY ADDRESS REGISTER

DEVICE ADDRESS REQISTER

DEVICE ADDRESS REGIST!R

BASE ADDRESS REGISTER

SASE ADDRESS REGISTER

CHANNEL
STATUS REGISTER

CHANNEL

STATUS REGISTER

CHANNEL
ERROR REGISTER

CHANNEL

ERROR REGISTER

DEVICE
CONTROL REGISTER

DeVICE
CONTROL REGISTER

OPERATION
CONTROL REGISTER

OPERATION
CONTROL REGISTER

SEQUENCE

SEQUENCE
CONTROL REGISTER

CONTROL REGISTER
CHANNEL

CHANNEL
CONTROL REGISTER

CONTROL REGISTER
NORMAL
INTERRUPT VECTOR

NORMAL
INTERRUPT VECTOR

CHANNEL 2

ERROR
INTERRUPT VECTOR

CHANNEL3

ERROR
INTERRUPT VECTOR
CHANNEL
PRIORITY REGISTER

CHANNEL

PRIORITY REGISTER

MEMORY
FUNCTION CODES

MEMORY
FUNCTION CODES

DEVICE
FUNCTION CODES

DEVICE
FUNCTION CODES

BASE
FUNCTION CODES
MeMORY TRANSFER COUNTER
BASE TRANSFER COUNTER

4-10

CHANNEL 1

BASE

"

I
I

16

FUNCTION CODES
MEMORY TRANSFER COUNTER
31

BASE TRANSFER COUNT!R

I
I

MEMORY ADDRESS REGISTER

MEMORY ADDRESS REGISTER

DEVICE ADDRESS REGISTER

DEY1CE ADDREIS REGISTER

BASE ADDRESS REGISTER

BASE ADDRESS REGISTER

Signetics

31

MICROPROCESSOR DIVISION

JANUARY 1982

MEMORY MANAGEMENT UNIT

SC68451

PRODUCT BRIEF, contact your Signetics sales offices for complete Information.

DESCRIPTION

FEATURES

The SC68451 Memory Management Unit
(MMU) provides address translation and
protection of the 16·megabyte addressing
space of the SC68000. The MMU can be
accessed by any potential bus master,
such as Instruction set processors, or
DMA controllers. Each bus master (or pro·
cessor) In the SC68000 family provides a
function code and an address during each
bus cycle. The function code specifies an
address space while the address specifies
a location within that address space. The
function codes are provided by the
SC68000 to distinguish between program
and data spaces as well as supervisor and
user spaces. This separation of address
spaces provides the basis of protection in
an operating system. By simplifying the
programming model of the address space,
the MMU also Increases the reliability of a
complex multiprocess system.

• Separates address spaces of system
and user resources
• Provides write protection
• Increases system reliability
• Provides efficient memory allocation
• Allows interprocess communication
through shared resource.
• Simplifies programming model of ad·
dress space
• Minimizes operating system overhead
with quick context switches
• 32 segments with variable segment
sizes
• Multiple MMU system capability
• Supports both paging and segmentation
• DMA compatible
• Provides virtual memory support
• SC88000 bus compatible

FUNCTIONAL DIAGRAM

I

MEMORY
MANAGEMENT
UNIT CONTROL

I

MULTIPLEXER
CONTROL

SC88451

GLOBAL
} HANDSHAKE
LINES
BERR

IiESE'f
FCO

MAPPING LOGICAL SEGMENTS TO PHYSICAL MEMORY

CLK

FC1

Vee

-FC2

GND

-FC3

READ
ONLY

READ
ONLY
A
READI
WRITE

SHARED
DATA
UNDEFINED

READ
ONLY

A

B

READ
ONLY

READI
WRITE

B

UNDEFINED

B

READI
WRITE

PHYSICAL
MEMORY

LOGICAL ADDRESS SPACE

Signetics

4·11

4

JANUARV1982

MICROPROCESSOR DIVISION

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUARij

SC68681

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

FEATURES

The Signetics SC68681 Dual Universal
Asynchronous Receiver/Transmitter
(DUARl) Is a single chip MOS-LSI com·
munications device that provides two in·
dependent, full·duplex, asynchronous
receiver/transmitter channels in a 40'pin
package. It interfaces directly with the
SC68000 16·bit CPU and other micropro'
cessors and may be used In a polled or
interrupt driven system.

• SC68000 compatible bus interface
• Dual, full·duplex, asynchronous
receiver/transmitter
• Quadruple buffered receiver data
registers
• Programmable data format
- 5 to 8 data bits plus parity
- Odd, even, no parity or forca parity
- 1, 1.5 or 2 stop bits programmable In
l/1a·blt Increments
• Progremmable baud rate for each receiver and transmitter selectable from
- 18 fixed rates: 50 to 38.4K baud
- One user-deflned rate derived from
programmeble timer/counter
- ExternallX or laX clock
• Parity, framing, and overrun error detec·
tlon
• False start bit detection
• Line brake detection and generation
• Programmable channel mode
- Normal (full duplex)
- Automatic echo
- Localloopback
- Remote loopback
• Multl·function programmable la·blt
counter/timer
• Multi·functlon II-blt Input port
- Can serve as clock or control inputs
- Change of state detection on four in·
puts
• Multl·f,unctlon II-blt output port
- Individual bit setlreset capability
- Outputs can ba programmed to be
status/lnterrupt Blgnals
• Versatile Interrupt systam
.... Single Interrupt output with alght
maskabla Interrupting conditions
- Interrupt vector output on interrupt
acknowladge
- Output port can be configured to provide a total of up to six saparata wlr&OR'able Interrupt outputs
• Maximum data transfer: lX - 1MB/sec,
laX - 125KB/sec
• Automatic wake·up mode for multidrop
applications
• Start·end break Interruptlstatus
• Detacts break which originates In the
middle of a character
• On·chlp crystal oscillator
• TTL compatlbla
• Single + 5V power supply

The operating mode and data format of
each channel can be programmed independently. Additionally, each receiver and
transmitter can select Its operating speed
as one of 18 fixed baud rates, a 16x clock
derived from a programmable counter/
timer, or an external 1 x or 16 x clock. The
baud rate generator and counter/timer can
operate directly from a crystal or from ex·
ternal clock Inputs. The ability to Inde·
pendently program the operating speed of
the receiver and transmitter make the
DUART particularly attractive for dual·
speed channel applications such as clus·
tered terminal systems.
Each receiver is quadruply buffered to
minimize the potential of receiver overrun
or to reduce interrupt overhead In inter·
rupt driven systems. In addition, a hand·
shaking capability Is provided to disable a
remote DUART transmitter when the buf·
fer of the receiving device Is full.
Also provided on the SC68681 are a multi·
purpose 6-blt input port and a multipur·
pose B-bit output port. These can be used
as general·purpose I/O ports or_can be
assigned specific functions (such as clock
Inputs or status/Interrupt outputs) under
program control.
The SC68681 is similar to the Signetics
SC2681, differing primarily in that the
SC68681 bus interface Is compatible with
the SC68000 16·bit microprocessor. Refer
to the SC2681 data sheet for operational
details.

4-12

PIN CONFIGURATION

Signetics

vee
IP4
IP5

1P2
IACKN
CSN
RESETN
Xl/ClK
X2

DTACKN
RXDS

RXDA

TXDB

TXDA

OPI

OPO

OP3

OP2

OP5

OP4

OP7

OPS

Dl

DO

D3

D2

D5

D4

D7

De
INTRN

OND
TOP VIEW

JANUARY 1982

MICROPROCESSOR DIVISION

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC68681

BLOCK DIAGRAM

rDO-D7

<

8/

~

k

BUS BUFFER

CHANNEL A

14-

I

I

r-

I

TRANSMIT
HOLDING REG

TxDA

TRANSMIT
SHIFT REGISTER

OPERATION
CONTROL

R/WN
DTACKN

•

CEN
AO-A3

4/

I

ADDRESS
DECODE

I

RIW CONTROL

RESETN

I--

-

4

RECEIVE
HOLDING REG

I r-

(3)

I

AxDA

RECEIVE
SHIFT REG

>--

~
CRA

SRA

INTERRUPT
CONTROL

IACKN

I-

r""'j'M'jj""

INTRN

---

~
~

•

TIMING

I

BAUD RATE
GENERATOR

I

CLOCK
SELECTORS

I
X1/ClK

X2

I

COUNTER!
TIMER

XTAlOSC

>--

I

I
I

I

.
~

-

;:

TxOB

CHANNELB
lAS ABOVE)

!!!ID
:!

...c~

RxDB

INPUT PORT
CHANGE OF
STATE
DETECTORS (4)

6/

IPO-IPS

z

--- -

II:

i

-

~
ACR

OUTPUT PORT
FUNCTION
SELECT
lOGIC

L...-

"'"'CsRA

~
~
CTUR

~

signetics

8

OPO-OP7

~
OPR

•

Vee

•

GND

4·13

MICROPROCESSOR DIVISION

JANUARY 1982

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)

SC68681

BLOCK DIAGRAM
The SC68681 DUART consists of the following eight major sections: data bus buffer, operation control, Interrupt control,
timing, communications channels A and
B, Input port and output port. Refer to the
block diagram.

Data Bus Buffer
The data bus buffer provides the interface
between the external and Internal data
busses. It is controlled by the operation
control block to allow read and write
operations to take place between the controlling CPU and the DUART.

Operation Control
The operation control logiC receives
operation commands from the CPU and
generates appropriate signals to internal
sections to control device operation. It
contains address decoding and read and
write circuits to permit communications
with the microprocessor via the data bus
buffer.

Interrupt Control
A single active-low interrupt output
(INTRN) is provided which Is activated
upon the occurrence of any of eight Internal events. Upon receiving an interrupt
acknowledge from the CPU, the SC68681
responds by placing a programmable 8-bit
Interrupt vector on the data bus.
Associated with the Interrupt system are
the interrupt mask register (lMR) and the
interrupt status register (ISR). The IMR
may be programmed to select only certain
conditions to cause INTRN to be asserted.
The ISR can be read by tbe CPU to determine all currently active Interrupting conditions.
Outputs OP3-0P7 can be programmed to
provide discrete interrupt outputs for the
transmitters, receivers, and counter/timer.

Timing Circuits
The timing block consists of a crystal
OSCillator, a baud rate generator, a programmable 16-blt counter/timer, and four

4·14

clock selectors. The crystal oscillator operates directly from a 3.6864MHz crystal
connected across the Xl/ClK and X2 inputs. If an external clock of the appropriate frequency Is available, It may be connected to Xl/ClK. The clock serves as the
basic timing reference for the baud rate
generator (BRG), the timer/counter, and
other Internal circuits. A clock signal must
always be supplied to the OUART.

pin. The receiver accepts serial data on
the RxD pin, converts this serial input to
parallel format, checks for start bit, stop
bit, parity bit (If any), or break condition
and sends an assembled character to the
CPU.

The baud rate generator operates from the
oscillator or external clock Input and Is
capable of generating 18 commonly used
data communications baud rates ranging
from 50 to 38.4K baud. The clock outputs
from the BRG are at 16X, the actual baud
rate. The counter/timer can be used as a
timer to produce a 16X clock for any other
baud rate by counting down the crystal
clock or an external clock. The four clock
selectors allow the Independent selection,
for each receiver and transmitter, of any of
these baud rates or an external timing
signal.

The inputs to this unlatched port can be
read by the CPU by performing a read operation at address 0 16 , A high input
results In a logic 1 while a low input results In a logic O. The pins of this port can
also serve as auxiliary inputs to certain
portions of the OUART logic.

The counter/timer (CIT) can be programmed to use one of several timing sources
as Its input. The output of the CIT is available to the clock selectors and can also be
programmed to be output at OP3. In the
cou nter mode, the contents of the CIT can
be read by the CPU and it can be stopped
and started under program control. In the
timer mode, the CIT acts as a programmable divider.

Communications Channels
A and B
Each communications channel of the
SC68681 comprises a full-duplex, asynchronous receiver/transmitter (UART). The
operating frequency for each receiver and
transmitter can be selected Independently
from the baud rate generator, the counter
timer, or from an external Input.

Input Port

Four change-of-state ,detectors are provided which are associated with inputs
IP3, IP2, IP1, and IPO. A high-ta-Iow or lowto-high transition of these inputs lasting
longer than 25-50l's Will set the corresponding bit In the input port change
register. The bits are cleared when the register Is read by the CPU. Any change of
state can also be programmed to generate
an interrupt to the CPU.

Output Port
The 8-blt multi-purpose output port can be
used as a general-purpose output port, In
which case the outputs are the complements of the output port register (OPR).
OPR[n] = 1 results In OPn = low and viceversa. Bits of the OPR can be individually
set and reset. A bit Is set by performing a
write operation at address E16 with the accompanying data specifying the bits to be
set (1 = set, 0 = no change). Likewise, a bit
is reset by a write at address F16 with the
accompanying data specifying the bits to
be reset (1 reset, 0 no change).

=

=

Outputs can also be individually assigned
The transmitter accepts parallel data from specific functions by appropriate prothe CPU, converts it to a serial bit stream, gramming of the channel A mode registers
Inserts the appropriate start, stop, and op- ' (MR1A, MR2A), the channel B mode registional parity bits and outputs a compOSite ters (MRl B, MR2B), and the output port
serial stream of data on the TxO output configuration register (OPCR).

5ignetics

Section 5
Video Game

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

UNIVERSAL SYNC GENERATORS (USG)

SC2621 (PAl), SC2622(NTSC)

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION
The Signeties.2621 Universal Sync Generator (USG) provides the timing and control
signals necessary for generating and displaying TV video information in the PAL format.

The Signetics 2622 Universal Sync Generator (USG) provides the timing and control
signals necessary for generating and displaying TV video information in the NTSC
format.

The USG accepts a single 3.55MHz input
clock and generates various timing outputs
including vertical, horizont,el and composite
blanking, composite sync and color burst
flag. Several auxiliary clock outputs are also
provided.

The USG accepts a single 3.5795MHz input
clock and generates various timing outputs
including vertical, horizontal, and compOSite
blanking, composite sync and coior burst
flag. Several auxiliary clock outputs are also
provided. The USG is primarily intended for
use in microprocessor-controlled video
games. A typical game configuration consists
of a 2622 USG, a 2650A microprocessor, a
2636 Programmable Video Interface, a 2616
16K ROM, and video summer circuitry. The
2622 is constructed using Signetics silicon
gate N-channel depletion load technology and
operates from a single + 5 volt power supply.

The USG is primarily intended for use in
microprocessor-controlled video games. A
typical game configuration consists of a
2621 USG, a 2650A microprocessor, a 2636
Programmable Video Interface, a 2616 16K
ROM, and digital video summer circuitry.
The 2621 is constructed using Signetics silicon gate N·channel depletion load techno·
logy and oparates from a single +5 volt power supply.

PIN CONFIGURATION

TOP VIEW

BLOCK DIAGRAM

1----,--- VRST

CBLANK

RESET

VSR

--------+--=======4----1

CLOCK

r--""";:':"'---l-:±=-++-1 - - - -.....

HRST

L ________=-.J=~ 0'

-C8'

PCK

Q-CK'
&CK4

5·2

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

SC2636

PROGRAMMABLE VIDEO INTERFACE (PVI)
PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION

PIN CONFIGURATION

FEATURES

The Signetics 2636 Programmable Video Interface (PVI) is intended for use In
microprocessor-controlled game systems,
and provides all of the common game circuits on a single chip. Circuits are provided
for player inputs, background, moving objects, scoring, and audio signals.
A typical system configuration consists of
five LSI circuits: a PVI, a 2616 16K ROM, an
NE549 Digital Video Summer (DVS) a Universal Sync Generator (USG), and a 2650A
microprocessor.
Additional PVls as well as random logic can
easily be interfaced to enhance game compleXity. Since the system is microprocessor
based, the actual game itself need not be
"hardwired" into the system. Game definition is completely contained in the ROM. To
change games, one simply replaces one
ROM with another. Each ROM can contain
several games, depending on game complexity and similarity between games.
The 2636 PVI is constructed uSing
Signetics' silicon gate N-Channel depletion
load technology and operates from a Single
+5 volt power supply.

• Four general-purpose, RAM-resident
object modules
• Object duplication permitting
generation of up to 80 object Images
on the screen
• 280ns object resoluUon
• Object size and pOSition under
program control
• Programmable score
Programmable sound
• Programmable background
• Eight programmable colors with
multiple brightness levels
• 37-byte scratch pad memory
• Chip Enable outputs for system ROMs
and PROMs
• 1/0 facilities for switch scanning and
potentiometer Inputs
• WIre-OR expansion capability to
multiple PVls
• Forty-pin dual-in-line package

APPLICATIONS
•
•
•
•
•

Consumer programmable video games
Arcade games
Simulators
Special purpose graphic displays
Home computer center

GND
INTREQ
R/W

VAST

HR8T

Cl

C2
Ci
QBJ/SCR

A,

INTACK

Ae

Do

vee

D,

A.

D:!

A,O

D.

A11

D.

CE,

DS

OI'ACK

Do

OPREQ

D7

ffi

5

--==--

SOUND

POT>

POT'

TOP VIEW

PVI BLOCK DIAGRAM

-'---~

CE'

POT'

POT.

Signetics

SOUNC

5-3

MICROPROCESSOR DIVISION

JANUARY 1982

UNIVERSAL VIDEO INTERFACE (UVI)

SC2637

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION
The Signetics 2637 Universal Video Interface (UVI), using a new design approach,
enables a microprocessor based system to
be interfaced more efficiently with a color or
black and white television receiver or monitor. For the first time, the 2637 UVI combines an object oriented approach with
character generation (alphanumencs or other displayable forms) plus RAM-mapped
color graphics.
The UVl's primary use is in microprocessor
controlled home computers or game systems, however, it may also be used in other
applications where the display of alphanumeric and graphics data is desired. In particular, the UVI has been designed to require
a minimum of support components thereby
allowing a system configuration that is optimized for the user's needs.
The UVI reads data and operational commands from a memory and produces video
signals that result in the generation of alphanumeric or graphics color TV displays. Many
of the common display circuits have been
incorporated in a single chip, including:
• Analog to digital converters which accept
potentiometer inputs
• Alphanumeric and special character
generators
• Moving object circuits
• Audio signal generators
With the 2637, a typical system configuration consists of a UVI, a 2616/2632 ROM, a
2622 (NTSC) or 2621 (PAL) Universal Sync
Generator (USG), a 2650 senes microprocessor, four 2112 RAMs, and video summing circuitry. Additional UVls, Programmable Video Interfaces (PVls), as well
as random logic can be interfaced to enhance game or system complexity.

UVI FUNCTIONAL DESCRIPTION
The 2637 UVI is a bus oriented device with
address and data busses contrOlling the
flow of data between the user's system and
the UVI (see block diagram). Both the address and data busses are bidirectional.
The basic clock frequency and the horizontal and vertical resel signals to the UVI drive
vertical and horizontal counters. The two
counters provide the UVI with a Cartesian
coordinate representation of the television
screen, i.e., each counter pair describes a
unique point on the screen. Typically these
clock and reset signals are provided by a
universal sync generator circuit.

5-4

PIN CONFIGURATION

FEATURES
• Four general purpose, RAM-resident
objects
• 280nsec object resolution
• Object size and pOSition under program
control
• Programmable multi-level sound and
noise generators
• 16 characters per display row
• 13 or 26 character rows per screen
• 40 alphanumeric characters
• 16 background characters
• 8 program definable characters
• 64 graphics characters
• 8 programmable color codes
• Chip enable outputs for I I 0 logic
• 1/0 facilities for switch scanning and
potentiometer (RCI inputs
• Operates with both U_S_ and European
standards
• Single +5 volt power supply
• Forty-pin package

D2

.,

DO

A.

A1

••
A3

••

AS

POT1

Cli

A7

CI
~

a

C!

CI!

SOUND

APPLICATIONS
•
•
•
•
•
•

.
.

POT2

Video games
Home computers
Communications terminals
Educational systemB
Process control displays
Medical electronics

R/W

R/W

aPJilR

YRST

cs

HAST

PC_
TOP VIEW

AID Block

Internal Status Block

The AID Block converts the analog potentiometer position information into binary data
which can be read by the system's CPU.
Only two of the four potentiometers are active at any given time.

The internal status block accumulates status information which can be read by the
CPU; for example, collisions

Address Block
The address block provides chip enable outputs for external RAMs and 1/ 0 buffers.

Color Mux System
The color multiplexer generates the color
codes for characters, objects, and screen.

Sound Block

ROM Character Generator

The sound block is a multi-level square wave
generator sending out pulses at a user
programmable audio frequency. Random
noise is also generated and can be mixed
with the audio frequency for simulating
crowd noise, explosions, etc.

The 64 bytes of RAM stores eight programmable character I object fonts

Signe1ics

The ROM character generator stores the
character lonts.

RAM

MICROPROCESSOR DIVISION

JANUARY 1982

SC2637

UNIVERSAL VIDEO INTERFACE (UVI)
BLOCK DIAGRAM
8-8IT DATA BUS DO - D7

--

HCIIIZOHTAi.

COUNtER, VERTl-

CAL COUNTER,

~----------------~l~

DIM. ADDRESS BUS

_NG
RIW[E]
_COUIfmI

_
RIW

PROCE88OR

iIII!II

LOGIC

STAlUSOf'
COW8ION

lII'm!
CBJECT

MODULE
1

RCE

~

DI!CODER

Cl!1

CO

.-------,L..-..-IO Cl

.......

OPRED

l:!
L-~-~~ t!fi(OBJECT vtDEO)

.....,.---._---,.._-..1

ADDRESS MJS AO - AS

+ 5 VOLTS

o

QND

0

Signetics

5·5

JANUARY 1982

MICROPROCESSOR DIVISION

MICROPROCESSOR

SC2650A

PRODUCT BRIEF, contact your Signetics sales offices for complete Information.

DESCRIPTION

FEATURES

The Signetics 2650A series are B-blt general
purpose microprocessors constructed using
Signetics n-channel silicon gate MOS tectlnology. The 2650 series executes a fixed Instruction set, with each Instruction being one
to three bytes In length.

• Stetlc 8 bit parallel NMOS microprocessor
• Single power supply of +6 volts
• TTL level single phase clock
• Tll compatible Input. and outputa
• Vsrlabl. length Instructions of I, 2 or 3
bytes
• ,,32K byte addressing rang.
• Coding efficiency with multiple addressing modes
• Synchronous or a.ynchronous memory
and 1/0 Int.rfac.
• Interface. directly with Indu.try standard memorl••
• Single bit aerial 110 path
• Seven 8 bit addr....ble g.nersl purpose r.glst.rs
• Vectored Int.rrupt
• Subroutln. return address stack

The 2650 InstNctlon set consists of many
powerful InstNctlons which are all ...IIy
understood and are typical of larger cornputers. There are one-, two-, and three-byte Instructions as a result of the multiplicity of
addressing modes.
Addressing range of these processors Is
32K bytes of memory snd 268 1/ 0 devices.
A single level hardware vectored Interrupt
capability is provided.

PIN CONFIGURATION

TOP VIEW

MICROPROCESSOR BLOCK DIAGRAM

8UBROUTINE

.ETURN
ADDR."
STACK

ADDRESS8US

I/O

CONTROL
LINES

.....

WRITE,
INTIRRUPT
_ITOP

DECODING

AND

CDNTROL

LOGIC
TIMING

LOGIC

Figure 1

5-6

SigneIics

CLOCK

MICROPROCESSOR DIVISION

JANUARY 1982

MICROPROCESSOR

SC2650A

PIN DESIGNATION
MNEMONIC

NUMBER

NAME

TYPE

FUNCTION

ADRO-ADR12

14-2

Address lines

0

ADRl3-E/NE

19

Address 13Extended I Non extended

0

ADR14-D/~

18

Address 14Data I Control

0

AmmiI

15

Address enable

I

DBUSo-DBUS7

33-28

Data bus

1/0

~

25

Data bus enable

I

Low order memory address lines for Instruction or operand fetch.
ADRO Is the least significant bit and ADR 12 is the most significant
bit. ADRO through ADR7 are also used as the 110 device address for
extended 110 Instructions.
Low order memory page sddress line during memory reference
instructions. For 1/0 inatructions this line discriminates between
extended and non-extended 110 inatructions.
High order memory page address line during memory reference
instructions. It also serves as the 1/0 device address for non-extended 110 Instructions.
Active low Input allowing 3-state control of the address bus ADROADR12.
These lines provide communicetion between the CPU, Memory, and
110 devices for Instruction and data transfers.
this active low input allows tri-state control of the data bus.

OPREQ

24

Operation request

0

Indicates to external devices that all address, data and control
information is valid.

~

38

Operation acknowledge

I

M/iO
WRP

20
23
22

Memory I input-output
Read/Wrlte
Write pulse

0
0
0

SENSE

1

Sense

I

FLAG

40

Flag

0

IIiiTRm

17

Interrupt request

I

INTACK

34

Interrupt acknowledge

0

~

37

Pause

I

RUN/WAiT

35

Run/Wait

0

RESET

18

Reset

I

CLOCK

38

Clock

I

VCC
GND

39
21

+5V supply
Ground

I
I

Active low input indicating completion of an external operation. This
allows asynchronous functioning of external devices.
Indicates whether the current operation references memory or 1/0.
Indicates a read or a write operation.
This is a timing signal from the 2850 that provides a positive-going
pulse during each requested write operation (memory or 1/0) and a
high level during read operations.
The senss bit in the PSU reflects the logic state of the sense Input to
the processor at pin # 1.
The flag bit In the PSU Is tied to a latch that drives the flag output at
pin #40.
This active low input line indicates to the processor that an external
device Is requesting service. The processor will recognize this signal at the end of the current instruction If the interrupt inhibit status
bit Is zero.
this line indicates that the 2850 is ready to receive the interrupt
vector (relative address byte) from the interrupting device.
This active low input is used to suspend processor operation at the
end of the currant Instruction.
This output is a processor status indicator. During normal operation
this line is high. If the processor Is halted either by executing a halt
instruction or by a low input on the pauae line, the run I walt line will
go low.
Resets the Instruction address register to zero. Clesrs interrupt
inhibit.
A positive going pulse train that determines the instruction execution
time.
+5Vpower
Ground

R/W

Signetics

5·7

=

5

MICROPROCESSOR DIVISION

JANUARY 1982

MICROPROCESSOR
FUNCTIONAL DESCRIPTION
The 2650 series processors are general
purpose, single chip, fixed instruction set,
parallel 8-bit binary processors. A general
purpose processor can perform any data
manipulations through execution of a stored
sequence of machine instructions. The processor has been designed to closely resemble conventional binary computers, but executes variable length instructions of one to

three bytes in length.
The 2650 series contains a total of seven
general purpose registers, each eight bits
long. They may be used as source or destination for arithmetic operations, as index
registers, and for I/O transfers.
The processor can address up to 32,768
bytes of memory in four pages of 8,192
bytes each. The processor instructions are
one, two, or three bytes long, depending on
the instruction. Variable length instructions
tend to conserve memory space since a
one-or-two byte instruction may often be
used rather than a three byte instruction.
The first byte of each instruction always
specifies the operation to be performed and
the addressing mode to be used. Most
instructions use six of the first eight bits for
this purpose, with the remaining two bits
forming the register field. Some instructions
use the full eIght bIts as an operation code.
The data bus and address signals are tristate to provide convenience in system design. Memory and I/O interface signals are
asynchronous so that direct memory access
(DMA) and multiprocessor operations are
easy to implement.
The block diagram for the 2650 series (figure 1) shows the major internal components
and the data paths that interconnect them.
In order for the processor to execute an instruction, it performs the following general
steps:
1. The instruction address register provides

an address for memory.
2. The first byte of an instruction is fetched
from memory and stored in the instruction
register.
3. The instruction register (IR) is decoded
to determine the type of instruction and
the addressing mode.
4. If an operand from memory is required,
the operand address ;s resolved and
loaded into the operand address register.
5. The operand is fetched from memory and
the operation is executed.
6. The first byte of the next instruction is
fetched.
The instruction register holds the first byte
of each instruction and directs the subsequent operations required to execute each

5·8

SC2650A
instruction. The IR contents are decoded
and used in conjunction with the timing information to control the activation and
sequencing of all the other elements on the
Chip. The holding register is used in some
multiple-byte instructions to contain further
instruction information and partial absolute
addresses.
The arithmetic logic unit (ALU) is used to
perform all of the data manIpulatIon operations, including load, store, add, subtract,
AND, inclusive OR, exclusive OR, compare,
rotate, increment and decrement. It contains
and controls the carry bit, the overflow bit,
the interdigit carry and the condition code
register.
The register stack contains six registers
that are organized into two banks of three
registers each. The register select bit picks
one of the two banks to be accessed by
instructions. In order to accommodate the
register-to register instructions, register
zero (RO) is outside the array. Thus, register
zero is always available along with one set
of three registers.
The address adder is used to increment the
instruction address and to calculate relative
and indexed addresses.
The instruction address register holds the
address of the next instruction byte to be

accessed. The operand address register
stores operand addresses and sometimes
contains intermediate results during effective address calculations.
The return address stack (RAS) is a last in,
first out (LIFO) storage which receives the
return address whenever a branch-to-subroutine instruction is executed. When a return instruction is executed, the RAS provides the last return address for the
processor's IAR. The stack contains eight
levels of storage so that subroutines may be
nested up to eight levels deep. The stack
pOinter is a three bit wraparound counter
that indicates the next available level in the
stack. It always points to the current address.

PROGRAM STATUS WORD
The program status word (PSW) is a major
feature of the 2650 which greatly increases
its flexibility and processing power. The
PSW is a special purpose register within the
processor that contains status and control
bits.
It is divided into two bytes called the program status upper (PSU) and program status lower (PSL). The PSW bits may be tested, loaded, stored, preset, or cleared using
the instructions which affect the PSW. The
bits are utilized as shown in table 1.

Table 1 PROGRAM STATUS WORD
PSUO,l,2 SP
PSU3,4
PSU5
II
PSU6
F
PSU7
S
PSLO
C
PSLI
COM
PSL2
PSL3

OVF
WC

PSL4
PSL5
PSL6,7

RS
IDC
CC

Pointer for the return address stack.
Not used. These bits are always zero.
Used to inhibit recognition of additional Interrupts.
Flag is a latch directly driving the flag output.
Sense equals the state of the sense input.
Carry stores any carry from the high-order bit of ALU.
Compare determines if a logical or arithmetic comparison is to be
made.
Overflow is set if a two's complement overflow occurs.
With carry determines if the carry is used in arithmetic and rotate
instructions.
Register select identifies which bank of 3 GP registers is being used.
Inter digit carry stores the bit-3 to bit-4 carry in arithmetic operations.
Condition code is allected by compare, test and arithmetic instructions.

PSU

I ~ I : I ~ I~ I~ Is~21 S~l IS~O I
S
F
II
SP2
SP 1
SPO

Sense
Flag
Interrupt inhibit
Stack pointer two
Stack pointer one
Stack pOinter zero

Signetics

CC 1
CCO
IDC
RS
WC
OVF
COM
C

Condition code one
Condition code zero
Interdigit carry
Register bank select
With/without carry
Overflow
Logical arithmetic compare
Carry / borrow

MICROPROCESSOR DIVISION

JANUARY 1982

MICROPROCESSOR
INPUT/OUTPUTINTERFACE
The 2650 series microprocessor has a set
of versatile I/O instructions and can perlorm
I/O operations in a variety of ways. One-and
two byte 1/ 0 instructions are provided, as
well as a special single-bit I/O facility. The
1/ 0 modes provided by the 2650 are designated as data, control, and extended 1/ O.
Data or controlI/O instructions, also called
non-extended 1/ 0 Instructions, are one byte
long. Any general purpose register can be
used as the source or destination. A special
control line indicates if either a data or control instruction is being executed.
Extended 1/ 0 is a two-byte read or write
instruction. Execution of an extended 1/ 0
instruction will cause an 6-bit address, taken from the second byte of the instruction, to
be placed on the low order eight address
lines. The data, which can originate or terminate with any general purpose register, is
placed on the data bus. This type of 1/ 0 can
be used to simultaneously select a device
and send data to it.
Memory reference instructions that address
data outside of physical memory may also

SC2650A
be used for 1/ 0 operations. When an instruction is executed, the address may be decoded by the 1/ 0 device rather than memory.

MEMORY INTERFACE
The memory interlace consists of the address bus, the 6-bit data bus and several
signals that operate in an interlocked or
handshaking mode.
The write pulse signal is designed to be
used as a memory strobe signal for any
memory type. It has been particularly optimized to be used as the chip enable or
read/write signal.

INTERRUPT HANDLING
CAPABILITY
The 2650 series has a single level hardware
vectored interrupt capability. When an interrupt occurs, the processor finishes the current instruction and sets the interrupt inhibit
bit in the PSW. The processor then executes
a branch to subroutine relative to location
zero (ZBSRl Instruction and sends out interrupt acknowledge and operation request
signals. On receipt of the INTACK signal, the
interrupting device inputs an 6-bit address,

Signetics

the interrupt vector, on the data bus. The
relative and relative indirect addressing
modes combined with this 8-bit address allow interrupt service routines to begin at any
addressable memory location.

INSTRUCTION SET
The 2650 instruction set consists of many
powerful instructions which are all easily
understood and are typical of larger com·
puters. There are one-, two-, and three-byte
instructions as a result of the multiplicity of
addressing modes.
Automatic incrementing or decrementing of
an index register is available in the
arithmetic indexed instructions. All of the
branch instructions except indexed branching can be conditional.
Register-to-register instructions are one
byte; register-to-storage instructions are
two or three bytes long. The two-byte register-to-memory instructions are either immediate or relative addressing types.

5-9

5

Section 6
Application
Notes

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

INTERFACE TECHNIQUES FOR THE 2651 PCI
INTRODUCTION

App Note M22

READ WRITE TlMfNG DIAGRAM

The Signetlcs2651 Programmable Communications Interface (PCI) is a universal synchronouslasynchronous data communications controller chip designed for
microcomputer systems. The 2651 accepts
programmed instructions from a microprocessor and supports many senal data
communication disciplines, synchronous
and asynchronous, in the full or half-duplex
mode.

I------Ico - - - - - . J

Although designed pnmarily to Interface to
a 2650 microprocessor, the 2651 can be
easily integrated Into systems emploYing
other CPUs. This application note descnbes
methods to interface the PCI to 8080A,
SC/MP, Z80, 8085, and 6800-based microcomputer systems

0 0-0 7
(WRITE'

INTERFACE SIGNALS

Do-Dr

The PCI interface signals can be grouped
Into two types' the CPU-related signals,
which interface the 2651 to the microprocessor system, and the device-related signals, which are used to Interface to the
communications device or system. The
functions of the CPU-related signals of
interest in this application note are detailed
in Table 1 Timing signals for the CPU-PC I
Interface are Illustrated in Figure 1, with

(READ)

_________ J

I'-1-

BUS
FLOATING

IOS--

DATA VAllO

BUS FLOATING

Figure 1

relevant specificatIOns summanzed in Table

2
PIN NAME

PIN NO.

INPUTIOUTPUT

FUNCTION

A1-Ao
'R/W
CE

10,12
13
11

I
I
I

07-00

8,7,6,5,
2,1,28,27

1/0

Address lines used to select internal PCI registers
Read command when low, wnte command when high.
Chip enable command When low, Indicates that control and data linesto the PCI are
valid and that the operation specified by the R/W, A1 and Ao inputs should be
performed. When high, places the 00-07 lines in the tri-state condition.
8-bit, three-state data bus used to transfer commands, data and status between PCI
and the CPU. Do is the least significant bit, 07 the most significant bit
Table 1

CPU-RELATED INTERFACE SIGNALS
LIMITS

PARAMETER
tCE

Chip enable pulse Width

tAS
tAH
tcs
tCH
tDS
tDH

Setup and hold time
Address setup
Address hold
R/W control setup
R/W control hold
Data setup for write
Data hold for write

tDD
tDF

Data delay time for read
Data bus floating time for read

TEST CONDITIONS1

Min
300

ns
ns

20
20
20
20
225
0

I
CL - 100pF
CL = 100pF

Table 2 AC ELECTRICAL CHARACTERISTICS FOR CPU INTERFACE SIGNALS

NOTES
1 TA=OQCto + 70°C, VCC=5V ±5%
2 ParametriC values listed are from 2651 data sheet Consult latest data sheet for
possible changes to specifications

6·2

UNIT
Max

Signetics

250
150

ns
ns

JANUARY 19S2

MICROPROCESSOR DIVISION

AppNoteM22

INTERFACE TECHNIQUES FOR THE 2651 PCI
2650 INTERFACE

2650-2651 INTERFACE

The 2651 IS designed to interface directly to
the 2650 microprocessor bus The PCI may
be addressed via the 2650 extended I/O
Instructions or It may be memory mapped,
In which case it IS addressed using the 2650
memory reference instructions. As shown In
Figure 2, the 2651 chip enable (CE) Input IS
generated by "NAN Ding" OPREQ with the
appropriate control signals (depending on
the addressing mode used) and the higher
order address lines required to select the
PCI.

."

ADRO
ADR1

IIIW

ii/w

....

DBUSODBUS7

"

V
r;NOTE1
/ :;.::-

M/iO

8080A INTERFACE
With regard to interfacing to the 2651, the
major difference between a 2650 CPU and
an 80S0A system consisting of an SOSOA
CPU, S224 Clock Generator, and 822S/38
System Controller (Figure 3) is the absence
of a combined read/write signal sUitable for
the 2651 RIW input. Instead, the 8080A system provides separate lOR and lOW (or
MEMR and MEMW) outputs which specify
both the direction of data flow and the data
transfer timing
The simplest way to accomplish the interface IS to utilize an address line from the
S080A for the R/W Input and to 'OR' the lOR
and lOW (or MEMR and MEMW) signals for
ultimate use as the 2651 chip enable signal,
as illustrated in Figure 4 The only impact on
system design IS that the software must
specify a different address to read the PCI
mode or command registers than to write
the same registers The selection of these
addresses must result In a '0' at the R/W
input for read operations and a '1' for write
operations The resulting register addressing and function are summarized In Table3
An analYSIS of the timing characteristics for
the recommended configuration shows that
adequate margins eXist to satisfy both the
2651 and the SOSOA specifications at the
minimum 8OS0A clock period of 480ns The
timing waveforms and calculations for the
read and write cycles are shown In Figures 5
and 6.

g-:NOTE3

2851

NOTE 2

,"//

E/NE

DBD-'

y

/

OPREQ

"""P-

CE

74LS
NAND GATE

j:1

~

HIGH ORDER ADDRESS
LINES FOR CHIP SELECT,
AS REQUIRED

NOTES

3

Inverter reqUired only If 2651 addreSSing IS by extended 110 instructions (Wnte, Read)
ThiS Input required only If 2651 addreSSing IS by extended 1/0 instructIOns and nonextended addreSSing IS also used In the system
These Inputs not reqUired If aU I/O addreSSing IS memory mapped

Figure 2

OPERATION

A2 (R/W)

A1

AO

REGISTER

READ

0
0
0
0

0
0
1
1

0
1
0
1

Receive Holding Register
Status Register
Mode Registers 1/2
Command Register

WRITE

1
1
1
1

0
0
1
1

0
1
0
1

Transmit Holding Register
SYN1/SYN2/DLE Registers
Mode Registers 1/2
Command Register

Table 3 PCI REGISTER ADDRESSING FOR 8080A INTERFACE

Signetics

6·3

JANUARY 1982

MICROPROCESSOR DIVISION

INTERFACE TECHNIQUES FOR THE 2651 PCI

AppNoteM22

8080A SYSTEM

2

2S

GNO---_

A.

20
+5V_

A,

11
-5V---_

A,

28
+12V---_

A,
A,

8080A

..

CPU

A,

A.
26

A,

27

A,

29

A,

3.

A,

31

A,

A,

SYSTEM OMA REO

-

A,
13

HOLD

A,

32

A,

33

A,

34

ADDRESS BUS

A,

35

A,

1
A"
A"

A"

37

14

Au

Au

INT

SYSTEM tNT REO

A"

••
38

A"
16
INTE

INT ENABLE

A"
39

A"

A"
36

A"

A"
18

WR

17
OBIN

t,;m~r
TANK
OSC
2 of T3 to AQ, Al, Fi/w changmg
Delay from 4>2 of T3 to CE changmg
Delay from $2 of T1 to B080A data bus valid
Time from $2 of T1 to BOaOA data required

200n8 MaX} tAS, les for 2651
310n5 Mm
are satisfied
4BOns
200n8
690n5
810ns

Mm }
Max
Max}
Max

tAH, tCH for 2651

are satisfIed
tOS1, 1052 for
BOBOA are satisfIed

Figure 5

Signetics

6·5

MICROPROCESSOR DIVISION

JANUARY 1982

App Note M22

INTERFACE TECHNIQUES FOR THE 2651 PCI

8080A-2651 WRITE TIMING

,...

I

T1

)

.,J\

I'

12

n

.. --'

\

TO

n

I

~

---~II--- n - -

______~r-\~____
I

\

\

- 1-;5.'N

~=x-

4i1iiii

-

:::x-H-

_t--- ii'iiii
OMIN
\

f0-

_MIN

X
DATA

j-

I

C

!-'52.,N_

FRO._

I-!
- t--

I-

DATA' ROM • •

HMIN

~

VALID

.1!!!1!..

.. MAX

..-

VALID

~

2SSID AUINSPEe

~ 100,¥_MIN
MIN
NOTES
All times In nanoseconds.

4. Data available

Time pnor to WR Ao. A" RIw val,d
Time after WR

683ns Min} tAS. tcs for 2651
508 Min
are UllSfl8d

CE valid

3 Time after iNA Ao. A,.
Delay from WR to CE

Rtw valid

to 2651

pnor to

ee, therefore tos for 2651 18 satisfied

5. Time after WR data...!,v81lable at 2651
Delay from WR to CE

125n8 Min} toH for 2651
7508 Max
IS satisfied

12008 Min} Wi. tCH for 2651
75nl Min
are satisfied

Figure 8

zaG INTERFACE

Z80-2851 INTERFACE

.....

..

.
i

I
~

0"

A,

IIiW

<

De..
2SS'

.......
- ....

_ORRmI
IWIiI OR in

"'GHOR".
ADDAE88
LiNea
FOR CHIP IILlCT.

I

AlRI!QUIRI!D

4
. yI

74 OR 74LS SIRlES

NOTE'

MRm. RFSH used for memory mapped 1/0
10RO, hIi usad lor standard 110

Figure 7

6-6

ill

The zeo CPU provides separate RD and WR
signals to indicate read and write operations
respectively. In addition, an MREO signal
(for memory operations) or an 10RO signal
(for 1/0 operations) are also provided. Although the RD signal could logically be
used as the RIW input for the ~, with
either MREO or 10RO used as the CE Input,
as appropriate, the Z80 timing specifications are such that the control hold time
specification (tCH) for the265f could"llOiDe
guaranteed .

-

To overcome this problem, a technique
utilizing an address line for the RIW Input is
recommended, as previously discussed for
the 8080A interface.
Interfaces for memory mapped and 1/0
map!!!,d operations are shown in Figure 7.
The M1 signal inhibits 2651 operation durIng interrupt acknowledge cycles, Similarly,
RFSH inhibits operation of the 2651 during
memory refresh cycles. A detailed timing
analysis shows that all pertinent 2651 and
Z80 timing specifications are satisfied with
the techniques illustrated,

JANUARY 1982

MICROPROCESSOR DIVISION

AppNoteM22

INTERFACE TECHNIQUES FOR THE 2651 PCI
SC/MP II INTERFACE

SC/MP 11-2651 INTERFACE

The bus interface signals for the SC/MP II
are similar to those previously described for
the 8080A and Z80, except that only memory reference operations are available. Again,
a technique using an address line for the
2651 R/W input is recommended, as shown
in Figure 8. All timing requirements for the
2651 and SC/MP II are easily satisfied.

6800 INTERFACE

.

A,

RIW

A,

<

D8 0 ?

The 6800 microprocessor provides a R/W
signal which, when inverted, is suitable for
use by the 2651. The remainder of the interface logic required consists of gating of the
appropriate bus signals to generate the CE
signal for the 2651, as shown in Figure 9.
The only timing parameter which is not
easily satisfied is the write data hold time
for the 2651 (t OH )' which is specified at Ons
minimum. The 6800 specifications guarantee only a minimum of 10ns data hold time
with respect to the DBE processor input,
which is normally the 2 clock. To guarantee worst-case operation, the DBE signal
should be skewed with respect to 2 to
guarantee the minimum data hold time at
the 2651. Consult the M6800 System Design Data Manual for detailed information.

.

A,

DO"

265'
PC.

RDS
WDS

H.

GH ORDER
ADD AESS LINES
FOR CHIP SELECT,
REQUIRED

I

A.

~

co

I

74 OR 74LS NAND
GATES

Figure 8

6

,--------------------------------------------,
6800-2651 INTERFACE

8085 INTERFACE
The bus signals of an 8085 microcomputer
system are similar to those ofthe 8080A system shown in Figure 3. The major d.fferences are the multiplexing of the eight least
significant bits of address on the data bus
and the use of an 101M control line to
distingUIsh between memory and 1/0 referenees.

Since a single RIW control line is not available, the same addressing technique forthe
2651 registers as described for the 8080A
interface .s recommended. Thus, the interface will be similar to the one shown in
Figure 4

~

m

DBof

~

I

The 8085 timing specifications are such that
all 2651 requirements are easily satisfied.
Similarly, the 2651 timing satisfies the 8085
requirements.

A,

.....

R/W

RIW

Y

-"

<

••

YMA

H.

OH ORDER
ADD AESS LINES
FOR CHIP SELECT,
REQUIRED

.

I

:

A.

If I/O addressing .s used, AO-A2 in Figure 4
can be replaced by the non-multiplexed
higher order address lines A8-A 10, since the
8085 provides the 1/0 address on both AOA7 and A8-A15 during an INPUT and OUTPUT instruction. In addition, the inverted
101M signal must be used as an input to the
final NAND gate.
If memory addressing is used for the 2651,
AO-A2 must be obtained by demultiplexing
from the addressldata bus through an externallatch clocked by the ALE timing signal. If
10 addressing is also used in the system, the
MIlO signal must be used in the final NAND
gate.

..

..
A,

p,-

DBa·,

...,
PC'

i:I

74 OR 7iQ.S SEAlES

Figure 9

REFERENCES
1. Signetics 2651 PCI Specificalton
2. Signetics MP8080A Microprocessor
Specification
3. Signetics SC/MP II 
2653
CEO

Use of PCI Transparent
Mode Features
• Send OLE (CR3) Command
To ensure that there IS no transmitter
underrun between a OLE and the control
character or OLE character to follow, the

PGC

.,.,
f

I

iN'f

R

+5v

Figure 1

Signetics

6·9

6

MICROPROCESSOR DIVISION

JANUARY 1982

APPLICATIONS TECHNIQUES FOR THE 2651 PCI
INTRODUCTION
The Signetics 2651 Programmable CommunicatIOns Interface (PCI) IS a universal
synchronous! asynchronous data communications controller chip designed for use with
microcomputers and minicomputers The
2651 accepts programmed instructions from
a CPU and supports many senal data commUnications disciplines, both synchronous
and asynchronous, In full or half-duplex, including IBM's Binary Synchronous Communications Protocol (BISYNC) The reader IS
referred to the 2651 Data Sheet for general
specifications and to applicatIOns memo
M22 for Interface techniques with such
microprocessors as 8080A, SC/MP, Z80,
8085, and 6800 Techniques for uSing the
2651 PCI to support BISYNC are detailed in
application memo M24. The purpose of this
applications memo IS to assist the designer
by demonstrating vanous interface and
operational procedures which have been
successful With the 2651 While we have
tried to cover several possibilities m each
procedure, the techniques shown should not

be construed to be constraining and the designer IS encouraged to develop whatever
Interface techniques best fit his application.

PROCEDURES FOR TERMINATING
TRANSMISSION
FULL DUPLEX (RTS always true)
Load last character into THR in response
to TxRDY going active low
2. Disable TxEN (0- CRO) in response to the
next TxRDY. This will cause TxRDY and TxEMT to remain in the high state after the
last character (in TxSR) is serialized.
HALF DUPLEX (RTS true when transmitting; false otherwise)
Synchronous-use a closing PAD
1 Load an all 1's PAD character Into THR In
response to TxRDY At this time the preVIOUS (last) data character is in TxSR being serialized
2. Disable TxEN as above In this case, the
last data character has been transmitted
when TxRDY goes active.
3. Drop RTS (0 - CR5). One or more bits of

PCI INTERRUPT REQUESTS iR1 AND IR2
WHEN TxEMT/DSCHG MUST BE SEPARATED FROM TxRDY
+5V

fiRI5Y
iifj

RxRDV

+sv

2651

ENBL

}~

LOGIC

iR2

TxEMT
DSCHG

App Note M26
the PAD character will be transmitted on
TxD before the RTS pin (23) goes high
Asynchronous-wait for TxEMT
1 Load last character Into THR in response
to TxRDY
2 Mask out the TxRDY interrupt condition
by externally disabling It This can be
done through a gate, interrupt controller
ChiP, or CPU mask flip-flop. Note that
TxRDY and TxEMT cannot be tied together (see Figure 1)
3 Drop RTS In response to the next TxEMT.
TxEMT gOing active Indicates that the
last character has been transmitted The
TxD state will be marked hold one bit
time after TxEMT goes active

DISTINGUISHING BETWEEN
TxEMT AND DSCHG
CONDITIONS
The DSCHG condilion goes active on a state
change of either the DCD or DSR Pln(s) provided either RxEN or TxEN = 1 but not In
local loopback mode The DCD and DSR
status bits (SR6, SR?) reflect the pin status
at the time the status register IS read, i e.,
they are not latched. A Status Read will
clear the DSCHG condilion.
The TxEMT condition goes active dunng
transmitter underrun. The condition is Immediately reset when a character IS loaded into
THR It IS reset after the linefill is sent once
the transmitter IS disabled (TxEN = 0)
Smce both of these conditions share a pin
(18) and a status register bit (SR2), it IS
necessary to determine which or both conditions are present when the pin I status bit IS
active (Figure 2)

Figure 1

, - - - - - . . . . FLOWCHART TO DISTINGUISH BETWEEN TxEMT & DSCHG

Figure 2

6-10

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

APPLICATIONS TECHNIQUES FOR THE 2651 PCI
GENERATING CORRECT
INITIALIZATION STATE
OFTxD

App Note M26

LOGIC TO GUARANTEE TxD

=

1 ON POWER UP OR RESET
GATeD

19r------i~~----------_f--,

After a power-on or RESET all Mode register
bits will be zero Specifically, MR25 will select external TxC The TxD pin requires at
least one high to low transition on TxC for
TxD to go high. Without a TxC Input, a break
(all zeros) may be transmitted This
presents a problem In asynchronous mode
when using the Internal BRG (MR25 = 1) To
circumvent the problem, the user may take
one of the following actions:
a) Generate one high to low transition on
TxC dunng a power on or RESET
b) Input a system clock or the BRCLK into

2651

Vee

RESET

TxC through a 1K resistor.

c) Inclusive OR RTS and TxD to produce
the Tx serial data to the modem
d) Use external logic (Figure 3) to insure
TxD comes up in the" 1" state.

ACTIVE
LOW

Figure 3

USING THE PCI BEYOND THE
SPECIFIED SERIAL DATA RATE

-----------

1Mbps DC BASEBAND LINK

If local loopback is not required, the PCI
will operate correctly if the RxC high and
low times are equal to or greater than 500
ns. A 1 Mbps DC baseband link between
two PCI's is therefore quite acceptable.
The only requirement is a synchronizing
flip flop at the transmitter to compensate
for the uncertainty in t TXD• the TxD delay
from the falling edge of TxC. That time can
be anywhere from 150 ns to 650 ns (Fig. 4).

6

j

2651

Figure 4

ANALYSIS OF PULL UP RESISTOR
VALUES FOR 2651 PCI WIRE-OR
OF OPEN DRAIN OUTPUTS
This

diSCUSSion IS

Intended to

assist

the

1. Rx mm Wish to mamtaln acceptable "0"

V output
AxmlO =

Vee max - VOL max

-""'--------'=---'OL max

user in determlnmg pull up resistor values for
open drain output TxRDY, RxRDY,
TxEMT IDSCHG shown In Figure 1 (Rx, Ry)

(5 25 -

+ IlL ,uP

45) volts

(16+ 01)mA

48

kl!

161

only one output sonklng (low) = 3kf!
2 Rx max Wish to mamtam acceptable" 1"
V output
Rxmax

Vee max - VOH min

= -""'--------'''-'-3 x 'OH - IlL J1P

(475 - 24)V
(3x 01 -

01)mA

=1175kll

all outputs sourcing (high)

Signe1ics

6·11

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
INTRODUCTION

per second. The PGC Is a device that
monitors parallel data transferred between a CPU or memory and a serial
receiverltransmitter (RIT, UART, USRT,
etc.) or other bus oriented device. Operation is two-way alternate (half-duplex) in
that the PGC Is selected to receive
characters either from the R/T or from the
CPU. Full duplex operation Is achieved by
using two PGCs. A unique feature of the
2653 is its 'character class array', a 12Sx2
RAM which is used to classify received
characters Into one of four types - normal,
sync/not included, block terminating
character,
and
secondary
search
character. The received characters may
be block checked and/or compared to the
special characters pre loaded into the
character class array. In addition to the
block check character (BCC) generation,
the PGC is capable of single character
detection, two character sequence detection and parity generation and checking.
All operating modes are software
programmable and can be changed for
each application. Figure I illustrates the
block diagram of the PGC, while figure 2
describes the formats of the registers
used to program its operation. 1

When transferring data via a data communications link using any protocol, the only
way to ensure a correct transfer Is to perform error checking on the messages
being exchanged. Error checking can be
accomplished through vertical, longitudinal and cyclic redundancy checks,
special
character
recognition
and
transparent operating modes. " the error
checking is perjOrmed correctly, the
result is an accurate transfer of data from
station to station. The checking technique
can be performed by software only, but
this may result in a reduction of the maximum channel speed, may reduce the
number of channels which can be handled
by the CPU, or may limit the supplementary tasks which can be performed by the
CPU. The most efficient way to accomplish error checking is to use a combination of hardware and software.
The Signetics 2653 Polynomial Generator
and Checker (PGC) is designed to provide
the above error checking capability while
operating with asynchronous, synchronous or parallel receivers or transmitters at a speed of up to 500K characters

AppNote400

The block check character (BCC), which
the 2653 computes from monitoring the 8bit data bus, takes the form of a cyclic
redundancy check (CRC) on specified
characters. The CRC Is a reliable method
of detecting errors In received serial data
streams and Is employed In almost all synchronous data communications protocols.
The PGC can compute the BCC In four
{!lodes:
BISYNC
normal,
BISYNC
transparent, automatic accumulate, and
single accumulate. In each of these
modes, one of three error polynomials
(CRC-16, CRC-12, and LRC-S) can be
selected. In either of the BISYNC modes,
the 'Intelligence' provided by the
character comparison capability within
the chip enables it to know which characters to include and which to exclude from
the BCC accumulation. Additionally, block
terminating characters can be detected as
well as the Initiation and termination of
BISYNC transparent mode. As a result, It
can handle character oriented processing
for IBM BISYNC, ANSI 3.2S, ISO 1745,
DEC DDCMP, and other disciplines.
1See the 2653 data sheet for full operational description.

BLOCK DIAGRAM
00-07

~

<
DATA BUS

'I

DATA BUS

I.

>I

BUFFER

+

r-

OLE
R

AO
1
E1
w

.

r-

OPERATION CONTROL

~

-I

MODE REGISTER
COMMAND REGISTER

n

~

STATUS REGISTER

I!

EO

~

CHARACTER REGISTER

~

I8

ARRAY

~

8
~

act ANDVRC
GENERATION UNIT

~'.1

i§
i

ace UPPeR

§

-8

II
Figure I

6·12

Signettcs

t, 18

{.Jo

Bn
CHARACTER CLASS

I

I

U

II

B
ace LOWER

B8

I

JANUARY 1982

MICROPROCESSOR DIVISION

App Note 400

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

PGC REGISTER BIT FORMATS

ACCUMULATION MODES

~

00 SINGLE
01 AUTOMATIC

10 BISYNC NORMAL
11 BISYNC TRANSPARENT

' - - - - - - - RECEIVE/TRANSMIT

ODD/EVEN PARITY - - - - - - - - - '

o RECEIVE

0000
1 eVEN

1 TRANSMIT

VRCENABLE _ _ _ _ _ _ _ _ _ _ _ _ _-1
('" 1)

' - - - - - - - - - ENABLE ACCUMULATION
WITH ffi
(= 1)

MODE REGISTER

6

=
----

SECOND SEARCH
CHARACTER DETECT
INTERRUPT
ENABLE = 1

BTC/SC DETECT _ _ _ _ _ _J
INTERRUPT
ENABLE'" 1

VRC ERROR
INTERRUPT

ENABLE = 1

Bee ERROR
INTERRUPT
ENABLE = 1

COMMAND REGISTER

BCe ERROR

CR'

(= 1)

L _____

CR6------I

VRC ERROR
(= 1)

L-_ _ _ _ _ _ _ _ BTC/SC DETECT

CRS - - - - - - - - - '

(oo 1)

CR4------------'

L ___________

sse DETECT
(= 1)

STATUS REGISTER

Figure 2

Signetics

6·13

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote400

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
A companion chip, the Signetics 2661
Enhanced Programmable Communications Interface (EPCi), directly combines
with the 2653 to effect a synchronous/
asynchronous character oriented communications link. If a complete multi-protocol
interface is desired, it can be obtained
using the PGC in conjunction with the Signetics 2652 Multi-Protocol Communications Controller (MPCC).

BISYNC TEXT MESSAGE FORMAT
Text

SYN SYN SOH Header STX

ETX

BCC
LRC-B, CRC-12, or
CRC-16, depending
on character
code (ASCII,
transcode, EBCDIC)

Figure 3

PROTOCOLS
Protocols provide the necessary ground
rules to assure the orderly and accurate
transfer of data between digital equipments. Data communications protocols
are becoming increasingly important as
the terminal population increases, distributed processing becomes widespread,
and new communications technologies,
such as packet switching and satellite
links, become commonplace.
The protocols associated with the data
communications have been classified into
several major levels, or layers, that define
various functions and operations. Each
level is designed to be functionally independent of the others, but each depends
on the correct operation of the previous
level to operate. The protocols embodied
in these levels range from those that
define the physical and electrical links,
e.g. RS232C and CCITT V.35, to those
which are responsible for functions such
as message buffering, code conversion,
recognizing and reporting faulty conditions in terminals or lines, communication
with the host mainframe, and management
of the communication network. These protocols are implemented by software
packages such as IBM's Systems Network
Architecture (SNA), CCITT's X.25, and
DEC's DECnet.
In the remainder of this application note,
we shall concern ourselves with data link
control protocols (DLC's), which are the
sets of rules necessary for effective communications between terminals and computers over conventional communications
cnannels. DLe's are concernea wltn nandling the communications link itself and
moving information across it efficiently
and accurately.
The basic functions of a DLC are to:
I. Establish and terminate a connection
between two stations.
2. Assure message integrity through error
detection, requests for retransmission,
and positive or negative acknowledgments.

6-14

3. Identify sender and receiver through
polling or selection.
4. Handle special control functions such
as requests for status, station reset,
reset acknowledge, start, start acknowledge, and disconnect.
Data link controls can be classified into
character oriented protocols (COPs) and
bit oriented protocols (BOPs). COPs can
be further subdivided into byte control
protocols (BCPs) and character count protocols (CCPs).

BYTE CONTROL PROTOCOLS
In BCPs, a defined set of commUnication
control characters effects the orderly
operation of the data link. IBM BISYNC,
ANSI 3.2B and ISO 1745 are all byte controlled. Control characters and two
character sequences configure and
manage the data link between sender and
receiver. Control messages or acknowledgements consist of one or two characters while data messages usually contain
less than 1,000 characters. For text
messages, shown in figure 3, an optional
header may precede each text (information) block. The entire message block is
error checked based on the information
code set used (ASCII, EBCDIC, SBT) and
the operational status of a transparent text
mode. The transparent text mode is a

Table 1

means of identifying pure data characters
from the characters of the information
code set. For example, packed BCD, floating point numbers or memory image data
would be sent in the transparent mode
such that the receiver would not interpret
that data as code set characters.
Transparent mode is initiated by the sequence DLE-STX and terminated by a OLE
followed by a block terminating character
(ETX, ETB, ITB, or ENO).
Byte controlled protocols utilize a stop and
wait automatic repeat request (ARO)
which limits operation to two way alternate
(half duplex). Each transmitted message
block must be acknowledged before the
next message may be sent. A negative acknowledgement is achieved by sending a
NAK, a positive acknowledgement is sent
as an ACKO or ACKI for even and odd
blocks respectively. The acknowledgement is sent after one or more Block
Check Characters (BCCs) have been
received and checked (one character for
LRC-B, two characters for CRC-12 or
CRC-16). Table I presents error checking
requirements for byte controlled protocols.
For
control
and
acknowledgement
messages the receiving processor must
detect various single and two character
sequences. These are defined in tables 2
and 3.

ERROR CHECKING REQUIREMENTS FOR
BISYNCI ANSI 3.28

Information
Code

No
Transparency

Transparency
Operating

Transparency
Not Operating

EBCDIC
ASCII
SBT

CRC-16
VRC-LRC
CRC-12

CRC-16
CRC-16
CRC-12

CRC-16
VRC-CRC-16
CRC-12

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
Table 2

COMMUNICATION CONTROL CHARACTERS FOR BISYNC

Mnemonic

Name

SOH
STX
ETX
ETB
EOT

Start of heading
Start of text
End of text
End of transmittal block
End of transmission

NAK

Negative acknowledgement

ENQ

Enquiry

ITB

Intermediate block

DLE
ACK
SYN

Data link escape
Acknowledgement
Synchronization character

Table 3

AppNote400

Function

Start of message which is used as heading.
Start of any message. Information code characters follow.
Signals the end of a text. BCC(s) follow.
Signals the end of a transmittal block. BCC(s) follow.
If used by the master, it signals the end of a transmission. As a slave
response, it indicates an abnormal termination of the transmission
(abort). In multipoint systems, it is' used by the control station to activate address decoding functions within the tributary stations.
Signals back to the master station that the last data block was not accepted. It may also represent a negative response to an initialize sequence, I.e. not ready.
Request to send back status, or abort a block of transmitted data.
Also used by the master station to end a polling sequence.
Blocks of the received message are released to the program via intermediate interrupts for faster processing. BCC(s) follow the ITB.
Used as leader in control sequences (see table 3).
Used as OLE trailers in control sequences (see table 3).
SYN-SYN establishes character synchronization. Inserted automatically into the data stream by the transmitter. Does not enter
main storage of the receiver.

BISYNC CONTROL CHARACTER SEQUENCES

Mnemonic

Function

OLE-RVI

Indicates to the transmitting statton that the receiving station wants to transmit data. Implies acknowledgement of last received block.
Indicates to the transmitter that the last message was received free of errors, but the receiver cannot
continue.
Enters transparent text mode. Allows all 256 characters to be used as data.
~isconnect sequence on a switched network.
End-of-text signal in transparent mode. BCCs follow.
End-of-transmitlal-block Signal in transparent mode. BCCs follow.
Intermediate-block-checking signal in transparent text mode. BCCs follow.
Used as positive reply to even/odd blocks respectively.
Aborts block of transparent data. BCCs do not follow.
Establishes character synchronization. Automatically inserted into the data stream during underrun in
normal text mode. Used to maintain synchronization, and to recognize line interruptions. Does not enter
main storage of receiver.
Automatically inserted into the data stream during underrun in transparent text mode. Used to maintain
synchronization, and to recognize line interruptions. Does not enter main storage of receiver.
Signals to the transmitting station that the last block was received correctly, but the receiver cannot
continue immediately because other operations have to be performed first.
Temporary text delay. Abort sequence used by the master station to announce an abnormal termination of the transmission.

OLE-SAK
OLE-STX
OLE-EOT
OLE-ETX
OLE-ETB
OLE-ITB
OLE-O/l
OLE-ENQ
SYN-SYN

OLE-SYN
OLE-WBT
STX-ENQ

Signetics

6015

6

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
Character Count Protocols

Bit Oriented Protocols

Digital Equipment Corporation's DDCMP
and its associated versions used by Bell
Labs are character count protocols. A
character count specifies the number of
data characters in the information field of
a message: positional significance is used
to identify control information in the
header of the block which is verified by a
separate cyclic redundancy check. There
are three control charac;ters in DDCMP
(SOH, ENQ, DLE) - each identifies the start
of a different type of message. Figure 4
depicts the DDCMP text message format.

2653 FUNCTIONS AND
APPLICATIONS

BOPs make use of only two or three specific control characters for operation of
the data link. These characters are used to
delimit the beginning (FLAG) and end
(FLAG, ABORT, GA) of a message frame.
Upon receipt of the opening FLAG, POSItional signficance is used to delineate the
bIt sequence that follows into prescnbed
fields, as shown in figure 5. These fields
area address, control, information, and
frame check sequence. The address, control, and frame check field are fixed length;
the information field is variable and may be
zero. Examples of BOPs are IBM's Synchronous Data Link Control (SDLC),
ANSI's Advanced Data Communication
Control Procedures (ADCCP), ISO's HighLevel Data Link Control (HDLC), Burroughs' Data Link Control (BDLC), and
various other protocols developed by computer mainframe manufacturers. All of the
above mentioned protocols are sImIlar and
can be treated as subsets of ADCCP.
BOPs also utilize a "go back N" type of
error control.

A "go bac;k N blocks" type of error control
is used in this protocol. Up to 255 blocks
may remain outstanding before an acknowledgement is required. This is
achieved by separate 8-bit send and
receive block counts. When an acknowledgement is sent the received block count
indicates the number of message blocks
correctly received. This is compared with
the send block count. The difference, if
any, is the number of blocks that must be
retransmitted.

AppNote400

BCC Accumulation
The primary function of the PGC is the accumulation of the BCC for character
oriented protocol
(BCP and CCP)
messages. As described previously, there
are four modes of BCC accumulation and
each mode can select one of three
generating polynomials to compute the
BCC(s). The polynomials are X'6 +
X'5 +x 2 +1 (CRC-16), X'2 +x 3 +X 2 +X+1
(CRC-12), and x 8 + I (LRC-8). The four accumulation modes are BISYNC normal,
BISYNC transparent, automatic accumulate and single accumulate.
In BISYNC normal mode, all characters
loaded Into the PGC's character register
are accumulated except those in the SYNI
Not Included class. During receive operations, a detected block terminating
character (BTC) will cause the BCC accumulation to stop after the next one
(LRC-8) or two (CRC-12 or CRC-16)

DDCMP MESSAGE FORMAT

SYN SYN SOH

Count
(14 bits)

Flags
(2 bits)

Response Sequence
(8 bits)
(8 bits)

Address
(8 bits)

CRC-16
(16 bits)

Information
(any number
of 8 bit
characters)

CRC-16
(16 bits)

Figure 4

BIT ORIENTED PROTOCOL (BOP) MESSAGE FORMAT

I

Header
Flag
(8 bits)

Address

I

Control

I

I
I

Information
(any number
of bits)

Zero irertlon/deletion, CRC accumulation

Figure 5

6·16

Signetics

FCS
(16 bits,
CRC-CCITT,
Inverted
remainder)

Flag
(8 bits)

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
characters have been accumulated. At
that time, If the BCC accumulation does
not equal zero there has been a block
check error. The BCC error bit will be set
and an interrupt generated If the corresponding mask bit was enabled. In
transmit mode, the BCC accumulation is
automatically stopped once the BTC
character has been accumulated. The
CPU must read the BCC upper and BCC
lower (for CRC-12 or CRC-16 only)
register(s) and transmit them to the R/T or
parallel peripheral. Since the accumulation has been stopped, the transfer of the
first BCC to the R/T will not effect BCC
lower. This assures that the second BCC
will be correct when it is reed by the CPU.
Note that BCCs are not checked against
the character class array nor are they
compared to the OLE ROM. This prevents
false character detections when transmitting or receiving BCCs.
Second search character (SSC) detection
is enabled in BISYNC normal allowing a
two character communication control sequence such as OLE-STX to be detected.
In BISYNC transparent mode characters
excluded from the BCC accumulation are
the first OLE of a OLE-OLE pair, the OLE of
a OLE-BTC pair, or OLE-SYN sequences
(the SYN is also excluded).
In receive and transmit modes, the termination of BCC accumuiatlon works
exactly as in BISYNC normai, except that
the BTC must be immediately preceded by
an odd number of OLEs to be properly
identified.
Second search character detection is not
enabled in BISYNC transparent since
OLE-SSC sequences are only valid in
BISYNC normal mode.
In Automatic accumulate mode all characters loaded into the character register are
accumulated; BTC and SSC detection Is
enabled and the BCC accumUlation is not
automatically terminated. The CPU must
use single accumulate mode to stop the
accumulation. When in receive mode, the
BCC error bit Is sel/reset after accumulating each character so that the CPU must
examine this bit after the last character Is
accumulated.
Examples of use of the automatic accumulate mode are a system where the RfT
(265112661) operates with OLE/SYN
stripping or in support of character count
protocols such as OOCMP.

In Single accumulate mode all characters
are accumulated, but only after an accumulate command Is given by the CPU. If
not given, the BCC accumulation is stopped. Operation in this mode is otherwise
identical to automatic accumulate. Single
accumulate mode can be used to selectively accumulate characters under CPU
control or to accumulate characters that
were unintentionally excluded In one of
the other modes.

Figures 6 and 7 illustrate the operation of
the 2653 on various types of text and control messages.

Some Other Applications
The PGC can be employed in a variety of
applications other than a dedicated BCC
generator for a single channel. For example, it can be multiplexed among several
data channels, used as a programmable
character comparator or It can be used to
check parity on a system address or data
bus. A brief description of each of these
applications is given below.
a. MULTIPLEXED POC
One PGC may be time-shared among a
few RlT's if the CPU saves and restores
the mode register and partial BCC result in
the BCC registers. These registers are accessed via CE1. There must be separate
save area for each RIT (serial channel)
and a channel pointer Indicating the last
RfT that transferred or received a data
character (see figure 8).
The loading of the BCC registers will clear
SRO-SR3 and all previously detected special characters, i.e., OLE, BTC/SC, BCC
(BISYNC modes). The BCC accumulation
will start again when the next character IS
loaded into the character register In all accumulation modes except Single. That
mode requires a start accumUlation command.
b. CHARACTER COMPARATOR
The PGC can be used as a programmable
data bus character comparator which
monitors data bus character transfers
(CPU to peripheral, CPU to CPU, CPU to
memory, memory to Rerlpheral via OMA).
The user selectively loads the character
class array with BTC/SC and SSC characters to be compared. Status bits will be set
and an interrupt can be generated upon
SC and OLE-SSC detection. A match on
one to 128 different characters or OLESSC sequences can be programmed.

SIgnetics

AppNote400

Figure g depicts an arrangement where
the OMA controller or slave CPU handles
data bus transfers, the PGC interrogates
the data bus, and the host CPU responds
to PGC interrupts.
c. BUS PARITY CHECKER
The PGC can be used to check the panty
of transactions on a system's data bus.
The processor first writes control information into the PGC via the CEl pin. All other
bus operations are then checked for parity
with external address decoding used to
generate an active low CEO. Bus parity
checking is useful in data transfers between CPU and peripherals or memory
and CPU. Some computers check panty
on both halves of a 16-bit word during all
system bus transfers.

MULTI-PROTOCOL
SYNCHRONOUS CHIP SET
The Signetics 2652 Multi-Protocol Communications Controller (2652), originally
targeted for bit oriented protocols and
OOCMP, can send and receive EBCDIC,
ASCII, and SBT data. However, the 2652
doesn't support many of the functions of
byte controlled protocols. In particular, the
2652 has no way of knowing which
characters to include or exclude in the
BCC accumulation. ThiS makes the on
board CRC-16 generator/checker useless
for BISYNC. Furthermore, there are no
provisions In the 2652 for transparent
mode OLE handling, special character
detection or two character sequence
detection. But the PGC encompases all of
these missing functionsl Thus, the 2652 2653 combination can totally support
character controlled protocols as well as
bit oriented and character count disciplines. The PGC can be used for single
character compares in SOLC/HOLC or
OOCMP applications to reduce software
overhead.
As shown in figure 10, only a single
Inverter is required to interface the 2652
and 2653 such that 2652 data bus
transfers are monitored.

A BISYNC!ASYNC CHIP SET
Although the 2653 complements any RIT
in the support of character controlled protocols it is optimized for use with the Signetics 2661 Enhanced Programmable
Communications Interface (EPCI). That
device is a USART with on chip baud rate
generator that has special features for
BISYNC. There are two loadable SYN

6·17

6
~~~~~

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

EXAMPLES - BISYNC TEXT MESSAGE BCC ACCUMULATION
SHADED AREAS ACCUMULATED
Rx "" RECEIVE MODE
NO DLE/$YN STRIPPING

CHARACTER CLASS ARRAY
SYN/BISYNC NOT INCLUDED 5VN, SOH

BTc/se ETX, ETB, ITB, ENC

sse

STX

CRe - 16 DR CRe - 12

SYN

$YN

SOH

1-.. . . . . -

STXII+tT---ETXI

iscclaccl I
PAD

+

BTC

acc ERROR (Rx) IF

DETECT

ACCUMULATION

"* 0

ACCUMULATION STOPPED
AFTER 2ND
NO
PARITY CHECK ON BCC5

ace

LRC - 8

SYN

SYN

I ,I

SVN

STX

SVN

ace

ETO)

OTe

CPU RESETS
REGISTERS AFTER
SOFTWARE DETECT

DETECT

I

BCe~
ace

PAD

ERROR (Rx) IF 7 LS BITS
OF BCC u
0 VRC ERROR IF
MS BIT IS INCORRECT PARITY

'*

OF STX THIS

ACCUMULATION STOPPED AFTER

EFFECTIVELY
EXCLUDES STX

1 BCe

BLOCK 1

_ _ _ _ STXI--"--ITSJ

OTe
DETECT

OPTIONAL

sse
DETECT

Brc
OETECT

POSSIBLE
ace ERROR

SET BISYNC
TRANSPARENT

POSSIBLE BCC ERROR
(IF SO RESET BCC
REGISTERS)
RESET acc REGISTERS OR
SET BISYNC NORMAL

sse

BTC
DETECT

DETECT
SET BISYNC
TRANSPARENT
MODE

I-I_o--------------BLOCK 1

sse
SET BISYNC
TRANSPARENT AND
RESET BeC REGISTERS

POSSIBLE
acc ERROR

RESET

NOTES

1 BGe error only for receive mode In transmit mode, GPU must respond to BTG detect by
reading the BGG reglster(s) and sending them to the R IT The accumulation IS stopped
after the BTG IS accumulated
2 ENO (OLE-ENO) In a text message should be treated as an abort
3 Opemng SYNs may be stripped by the RfT
4 The Single accumulate mode and command can be used to accumulate a character that
madvertently was excluded (For example, the OLE of a OLE-STX If the PGG was In
transparent mode and there was not a hne turnaround prior to the OLE) The Single
accumulation should be done uSing GE 1 after the BGC(s) have been accumulated

Figure 6

6·18

.\_

BTC
DETECT

DETECT

Signetics

POSSIBLE
acc ERROR

sec

REGISTERS
(IF BCC ERROR)
AND SET BISYNC
NORMAL

BLOCK 2

-----..t

OTe
DETECT

POSSIBLE

ace ERROR

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

EXAMPLES - BISYNC CONTROL MESSAGES
BTC/SC EDT, NAK

sse

ACKO, ACK1, WACK, RVI
SINGLE ACCUMUlATION MODE
STOPS sec ACCUMULATION
8YH

I I I

8TN

PAD

EaT

8VH 5TH

ENO

CONTROL STATION POLL
OR SELECTION OF A
TRIBUTARY STATION

8TC/SC
DETECT

BTC/SC
DETeCT

ex

a- -

REPRESENTS A UNIQUE POLLING OR SELECTION ADDRESS

8YN

TRIBUTARY STATION PREPAR£D TO
RECEIVE OR POSITIVE ACKNOWLEDGMENT
OF EVEN NUMBERED TEXT BLOCK

8TN

sse
DETECT

5YN

8TH

I I I
NAK

TRIBUTARY STATION NOT READY TO
RECEIVE OR NEGATIVE ACKNOWLEDGMENT

PAD

OF TeXT BLOCK

~
STC/se
DETECT

5YH

5YN

TRIBUTARY STATION TEMPORARILY
NOT READY TO RECEIVE

WACK

6

sse
DETECT

SYN

8YN

REVERSE INTERRUPT FROM REceiVING
STATION TO REQUEST TERMINATION
OF THE CURRENT TRANSMISSION
BECAUSE THE RECEIVER WANTS TO
TRANSMIT

RVI

sse
DETECT

NOTES

1 BCC accumulation should be Ignored for control messages thiS can be effected by
81ngle accumulate mode Without smgle accumulate commands
2 Characters programmed as S8Cs should be the binary eqUivalent of the second
character of the OLE-SSe sequence

Figure 7

registers and a loadable OLE Register in
the EPCI. Figure 11 IS a schematic showIng the 2653 and 2661 Interfaced to an 8bit CPU.
A transparent operating mode causes the
EPCI to automatically change the detected
synchronization sequence and underrun
linefill from SYN-SYN to DLE-SYN. This is
necessary to prevent an unrecoverable
problem at the receiver. If a USART sent or
received the normal mode SYN-SYN sequence it would be interpreted as
transparent data rather than actual synchronization Information.
Another transparent mode function is
detecting and stripping received DLE's.
Normally a software job, this task is completely and properly handled by the 2661.
The DLE Detect status bit is even automatically reset at the proper time.

A Send OLE command in the 2661 's
transmitter can be used to prevent a possible underrun between the DLE and a
subsequent control character. Such an
underrun would cause an Incorrect control
sequence to be transmitted. For example,
consider an underrun between a DLESTX, the sequence used to enter
transparent mode. The transmitted sequence becomes DLE-SYN-SYN-STX. But
a DLE-SYN IS illegal unless transparent
mode has been entered. Furthermore, the
STX would set normal text mode not
transparent mode.

FLOW CHARTS FOR BISYNC
OPERATION
Figures 12 through 15 Illustrate functional
flow charts for the operation of the 2653 2661 pair in BISYNC. The intent of these
flow charts is to illustrate the procedures

Signetics

required when receiving and transmitting
BISYNC text messages in both normal and
transparent modes of operation It IS not
implied that the actual software program to
handle these tasks necessarily follow the
flow charts step by step. In an actual
application, an interrupt driven structure
would be more appropriate. Assumptions
are half-duplex operation (normal for the
BISYNC protocol) and use of the EBCDIC
code.
The receive flow, figure 12, starts With inttlallzatlon of the PGC and EPCI for the normal mode Modem handshaking IS then
performed. Upon detection of carner, indicated by assertion of the 2661 's DCD status bit, the receiver IS enabled, the PGC IS
setup for receive, and miscellaneous flags
are reset. Data is then read from the 2661
receive holding register and acted upon
according to the BISYNC protocol The

6-19

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

PGC SERVICES MULTIPLE RECEIVERSITRANSMITTERS
I

ADDRESS

I

DATA

:

R/W

CEO
READ/WRITE

MEMORY

,D
ADDReSS, DATA, R/W,

m

~TAD

eEO

CI'U

u;-

eEl

I

ONE PGC IS TIMe-SHARED BY THREE RiTa
THE CPU ReADS AND RESTORES THE PARTIAL
REMAINDeR FOR EACH SERIAL CHANNEL

PGC

I

iiiT

I-

ace

Figure 8
PGC DATA BUS MONITORING WITH DMA TRANSFERS
lIlT

APPLICATIONS IrICWDE CHARACTER ARRAY

COIIPAFUIONS, YRC AND/OR ICC CHECKS
ON THE DATA BUS.

NOTE
·CPU Inltlahzes DMA controller for each block transfer of
data,

Figure 9

6·20

Signetics

AppNote400

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

2652/2653 INTERFACE
TYPICAL PROTOCOLS: BISYNC, OOCMP, SOLC, HOLC
INTERRUPTS

U

Tl(BE, TxU, RxDA, AxSA

II

087 - DBO

t----

2852
MPCC

TxD

I - RxD

A2
A1

I - TxC
f - Axe

AO

R/w
DOEN

4

CPU

DB{}DBO
~

2653
A1

PGC

fi/w
AO

m

f
I

R

t

I

iiiT

6

(OPEN DRA..,

+SV

Figure 10

2651 OR 2661/2653 INTERFACE

ll~~S

R
+5V
TiRIri',IGlm'i',TiEJiIT~

-

---

087 - DBO

r--'"

A/w, Al, AO

2651/61
PCI

TKO
RxD

-----

I >

r-t-- ~
CPU

~
2653

~

PGC

CEi

f

I

iNf (OPEN DRAIN)

R

+SV

Figure 11

Signe1ics

6·21

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
PGC status flags are utilized to determine
If and when the transmission switches to
transparent mode, and to determine the
receipt of a block terminating character
(BTC). The two characters following the
BTC are the Block Check Character. After
these are received, the PGC status
register is examined to determine if a BCC
error has occured.
The data stored In the buffer will be stripped of all sync characters. OLEs are not
stripped. Although the 2661 Includes a
OLE stripping capability, this feature is not
employed because the OLEs must be
'seen' by the PGC In order for it to accumulate the BCC correctly. The CPU

8·22

must remove the extranecus OLEs which
may be imbedded In a transparent block of
text.
The transmit flow chart, figure 13, operates on a block of data placed in a buffer
area by the contrOlling CPU. This data
must include the SYNs to be sent at the
Initiation of transmission and the OLEs
that form part of a two character control
sequence. OLEs in a transparent block of
text need not be doubled up -the EPCI will
automallcally add a OLE if one is loaded
Into its THR while operating In transparent
mode. A character counter assists the
software to determine when a OLE Is really
part of a BTC (in transparent mode).

AppNote400

After Initialization of the PGC and EPCI
and establishment of the modem connection, the data is pulled from the buffer and
transmitted. If a OLE is detected in the
data stream, and that character is part of a
two character control sequence, the 'send
OLE' feature of the PCI is used to avoid
underrun between the two characters.
Since the OLE Is not transferred to the
EPCI via the data bus, this requires that an
extra OLE be accumulated In the PGC.
This is done by use of the PGC's capability
to accumulate characters loaded via CEI.
When a BTC is detected by the PGC, the
two BCC characters are read from the
BCC registers and transferred to the EPCI
for transmission.

JANUARY 1962

MICROPROCESSOR DIVISION

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

BISYNC RECEIVE FLOW CHART

WRtTEPCI

.R>

DATA - 4C
WRITEPGC

MR

SWITCH
POCAND

""TO
TRANSPARENT
MODe,SET
TRANSPARENT

MOOEFLAG

DATA-Ol

INCREMENT
POINTER AND
STORE
CHARACTER

IN BUFFER

BISYNC NORMAL

RECEIVE
CRO 18

Figure 12

6·23

------ - -----

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

BISYNC RECEIVE FLOW CHART CONTINUED

BISYNC RECEIVE FLOW CHART NOTES

eo,
'"

FFLAG

=

WRITEPCI

M"

WRIT€PGC

C,
DATA

~

02

INITIALIZE
FLAGS FOR
NEXT BLOCK.
RESET BCC.
SWITCH TO
BISYNC NORMAL
MODE

character has

been

TFLAG

=

operating

=

BCe or PAD error

81 FLAG

= Received block terminating character (BTC)
Awaiting BCe

82FlAG

=

RESET

DATA~OC

non~sync

EFLAG

TEST

TFLAG,B,FlAG

the first
received

In

transparent mode

Received first
second BCe

BCe character

Awaiting

2

sse detect IS disabled by PGC while In transparent mode

3

Pomter IS decremented to overwrite prevIOusly stored
'OLE' which was part of a 'DLE~SYN' Ime flll

4

Test for closing PAD of at least four ones at end of
message

5

If first non·sync character IS a 'OLE', the message will start
with 'OLE-STX' (transparent mode) FFLAG IS not set In this
case since both these characters are excluded from the
accumulation

6

First non·sync character of a new message, or first two If
message starts In transparent mode, are excluded from the
BCC accumulation

WRITEPGC

"'

TEST
RXRDY

(NOTE 4)

R€ADPCI

'"'

LOGICAL 'OR
CHARACTER
WITH'FO'

NEGATEOTR
OISABLERX

Figure 12 continued

6·24

Signetics

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

BISYNC TRANSMIT FLOW CHART

'"

CHARACTER

FAOM8UFFER

'"

INCREMENT
POINTER AND
DECREMENT
COUNTER

'SENDDlE'

=

--0

NORMALLY

00"

0'

'"
WRITETQ

'GC
RESET

CHARACTER
REGISTER

'"

USINGCFi
DATA-l0

(NOTE 3)

ACCUMULATE
'OLE

iNTOTHEBCC

RESET

'CC
(NOTE 3)

,co
(NOTEZI

ENABLETX

ASSERTRTS
(NOTE 11

WRITEPCI

""

DATA~4C

SISYNCNORMAL
ACCUM WITHCEl
TRANSMIT

WRITEPGC

"'

CRC'6

SWITCHPGC
AND PCI TO
TRANSPARENT

MODE,SET
TRANSPARENT

MODE FLAG

INITIALIZE
BUFFER POINTER
AND CHARACTER
COUNTER
RESET

FFLAG,TFLAG

Figure 13

Signetics

6·25

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

AppNote400

BISYNC TRANSMIT FLOW CHART CONTINUED

RESET
TRANSPARENT

~~~T~;:' :ci-~GS.
ANOpetTO
NORMAL MODE

RESETBCC
ACCUMULATION

READPGC

'"

REGISTER

TRANSMIT

'"

UPPER
(NOTESI

TEST

TXRDY

BISYNC TRANSMIT FLOW CHART NOTES

1
2

'"

REGISTER

WRITETOPCI

'""

TRANSMIT

'"

3
4
5
6

Transmitter Will not operate until Clear to Send leTS) Input IS asserted
A DLE al thiS pOint In the transmit sequence can only be followed by an STX, which Will place the system In
transparent mode The 'Send OLE' capability of the pel IS used In order to prevent underrun between the DLE and
STX characters, and possible miSinterpretation of the sequence by the receiving stabon
First non-sync character of a new message, or first two If message starts In transparent mode, are excluded from
the BCC accumulation
DFLAG IS used to mdlcate that a DLE must precede the next transmItted character
In transparent mode, the 2661 Will automatically send an extra DLE when a DLE IS loaded Into the THR
Underrun of PCI IS not permitted at pOints shown OtherWise, received data may be misinterpreted

Figure 13 continued

6·26

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote400

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER

2653 INITIALIZATION

2661 INITIALIZATION

RESET
REGISTER

MASTER RESET

PUT INTO START -UP MODE

POINTER

SYNC FORMAT,
BITS, NO PARITY,
DOUBLE SYNC,
NON-TRANSPARENT MODE

SET UP FOR
SYNfNI CLASS

EXTERNAL CLOCKS

SYN/NI CLASS

a

6

SYN

EBCDIC'SYN'

SET UP FOR

BTc/se CLASS

WRITE TO
CHARACTER REG
DATA = 03

EBCDIC 'SYN'

DATA

=

IF

DATA = 26
DATA = 20

BTC/se CLASS
ETX
ITB
ETB
ENO

EBCDIC 'OLE'

SET UP FOR

sse CLASS

sse CLASS
STX

Figure 14

Figure 15

Signetics

6·27

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
INTRODUCTION
Microprocessors and LSI have had a
dramatic impact on the implementation
and capabilities of alphanumeric CRT terminals. The first generation of CRT terminals were little more than 'glass
teletypes'. Current designs, implemented
with microprocessors, are characterized
by an abundance of sophisticated
features that were previously not
economically feasible: a universal hardware design that can adapt to different
user requirements Simply by changing
software or firmware; programmability to
provide end users with the flexibility to
execute specialized routines; and local
intelligence and storage which off-loads
the host CPU by permitting data manipulation and verification at the terminal site.
Just as the impact of microcomputers has
been felt in the functional capabilities of
terminals, advances in semiconductor
technology have revolutionized the hardware implementation. Designs that previously consisted of 100 to 200 ICs can
now be realized with a few dozen MSI and
LSI devices. The majority of the LSI
manufacturers' effort with respect to CRT

terminals has been concentrated in the
'CRT controller' area. These circuits provide the character timing, display
addressing, and sync generation functions required by all terminals. However,
these controllers need to be supported by
many other external circuits to implement
a complete terminal.
The purpose of this application note is to
provide information on the use of four new
Signetics CRT terminal products which,
when combined with standard CPUs,
memories, and TTL, allow the implementation of a wide spectrum of CRT terminal
capabilities in as few as 15 total
packages. These devices are:
• 2670
Display Character and
Graphics Generator (DCGG)
• 2671 Programmable Keyboard and
Communications Controller (PKCC)
• 2672 Programmable Video Timing
Controller (PVTC)
• 2673 Video and Attributes Controller (VAC)

MAJOR ELEMENTS OF A CRT
TERMINAL
Figure I shows the major elements of a
typical low-end microcomputer-based

CRT TERMINAL BLOCK DIAGRAM

CPU

Figure 1

6-28

Signetics

AppNote401
CRT terminal. In this system, the CPU
examines Inputs from the data communications line and the keyboard and
places the data to be displayed in a display buffer memory, which is typically a
RAM which holds the data for a single or
multiple screenload (page) or for a single
character row. High-end ('smart' and
'intelligent') terminals start with the same
base, but append additional CirCUItS to
provide more features and capabilities.
The following sections describe the functions of each of the major blocks.

Character Timing and Sync
Generation
The major function of this block is to
generate the horizontal and vertical timing
signals required to produce the TV raster
on the CRT monitor. Other functions
include the generation of display memory
addresses in synchronism with the monitor scan and in accordance with a defined
screen format (characters per row, scan
lines per row and rows per screen),
generation of a cursor signal at the
appropriate scan position, and generation
of video blanking signals during retrace
intervals.

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
1/0 Interface
In its simplest form, this block provides an
interface to a keyboard to identify the key
depressed and a serial communications
link, normally operating in an asynchronous format, between the terminal and the
host computer. Although these functions
could be performed programmatically by
the terminal CPU system, removing these
functions to intelligent controllers unburden the system CPU and allow it to
be used more effectively to provide additional features with a relatively small
cost impact.

Character and Graphics
Generation
These circuits convert the data stored in
the display memory to the line by line dot
patterns required to display the data on
the CRT monitor.

Video Timing and Visual
Attributes
This section contains the high speed (dot
rate) circuits necessary to convert the

parallel data from the character and
graphics generation circuits to the serial
video stream required by the CRT. Also
included are circuits to sum visual display
attributes such as blinking, highllow
intenSity, reverse video, and underlining
into the video stream.

SIGNETICS' CRT CHIP SET
As mentioned previously, the Signetics
CRT 'set' consists of four circuits. The
functions of these circuits correspond
closely to the four major CRT terminal
blocks described above. The circuits have
been partitioned so as to allow each to be
used independent of the others, allow
several alternative methods of implementing the display memory interface so that
the hardware can be tailored to the system
requirements, provide a full complement of
programmable capabilities, and minimize
the number of support circuits required.
The following sections give a brief
description of each of the circuits. The
reader is referred to the individual data
sheets for full operational details.

2672 Programmable Video
Timing Controller (PVTC)
The 2672 PVTC, figure 2, is a programmable device designed for use in CRT terminals and display systems that employ
raster scan techniques. The PVTC generates the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT
monitor. Also, the 2672 provides consecutive addressing to a user specified display
buffer memory domain and controls the
CPU-display buffer interface for various
buffer configuration modes. A variety of
operating modes, display formats, and timing profiles can be implemented by
programming the control registers in the
PVTC.
The CPU initializes the 2672 control and
timing registers for the desired timing
profiles and memory configuration. The
PVTC provides the handshake control for
CPU access to the display buffer. One of
four memory access modes may be
programmed: independent mode, trans-

2672 PROGRAMMABLE VIDEO TIMING CONTROLLER

'"

I' ' ' ' ' '"' ' I

...,,'
"""''''''

,,.,

READ/

DISPlAV

REGISTERS

"''''''

~==:>I
ADDRESS
DECODER

...."'"
DISf'LAY

~

-

HANDSHAKE
COQ>C

L..-_ _- '

I ~= I¢::
L...-_--'

11

·~i71
".,m,

Figure 2

Signe1ics

6·29

6

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
parent mode, shared mode, and row mode.
These modes are described in the System
Configurations section of this application
note.
I n all modes, the PVTC provides
addresses for the display buffer which
outputs the character codes to the 2670
Display Character and Graphics Generator (DCGG) and visual attribute codes to
the 2673 Video Attributes Controller
(VAC). The DCGG and PVTC supply the
dot data and sync timing to the VAC which
generates the serialized video.
Programmable features of the PVTC
include screen format (characters/row,
rows/screen, scan lines/row), horizontal
and vertical timing parameters, cursor
type (block or underline) and blink rate,
character blink rate, interlaced or noninterlaced operation, and single or double
height characters.
The PVTC is capable of producing interrupts based upon several internal conditions. By using these interrupts (or by polling the equivalent status register) display
features such as non-consecutive buffer
addressing for split screen operation,
multiple cursors, horizontal and vertical
scrolling, and smooth vertical scroll can be
implemented.

2671 Programmable Keyboard
and Communications Controller
(PKCC)
The 2671, figure 3, is an MaS LSI device
which provides a versatile keyboard interface and also functions as an asynchronous communications controller. It is
intended for use in microprocessor based
systems and provides an eight bit data bus
interface.
The keyboard controller handles the scanning, debounce, and encoding of mechanicalor capacitive keyboards with a maximum of 128 keys utilizing any of four
programmable rollover modes. A mask
programmable ROM provides four levels of
key encoding, corresponding to the separate shift and control input combinations.
An eight bit keyboard status register
transmits status infoiiiiaticii to the CPU.
Programmable features include rollover
mode, scan rate and debounce time,
coded or uncoded operation, and
automaltc repeat operation.
The communications section of the PKCC
is a universal asynchronous receiver and

6·30

transmitter (UART). The receiver accepts
serial input data and converts it to parallel
data characters. Simultaneously, the
transmitter accepts parallel data from the
CPU data bus and outputs it in serialized
form. Received data is Checked for parity
and framing errors, and break conditions
are flagged. Character lengths can be
programmed as 5, 6, 7, or 8 bits not including parity, start or stop bits. An internal
baud rate generator (BRG) operating from
an external clock or directly from a crystal
can be used to derive one of sixteen
receive and/or transmit clocks. An eight
bit communications status register provides status information to the CPU.
The PKCC has an interrupt mask register
to selectively enable keyboard and communications status bits to generate interrupts. Priority encoded interrupt vectoring
is available. Upon receipt of an interrupt
acknowledge, a mask programmable interrupt vector will be output on the data bus
reflecting the source of the interrupt. The
mask enabled interrupt sources can also
be read directly.

2670 Display Character and
Graphics Generator (DCGG)
The DCGG, figure 4, is a mask-programmable 11,648-bit line select character
generator. It contains 1281 Ox9 characters
placed in a 10x16 matrix, and has the
capability of shifting certain characters,
such as j, y, g, p and q, that normally
extend below the baseline; effectively, the
9 active lines are lowered within the matrix
to compensate for the character's position.
Seven bits of an 8-bit address code are
used to select 1 of the 128 available
characters. The eighth bit functions as a
chip enable signal. Each character is
defined by a pattern of logiC 1s and Os
stored in a 1Ox9 matrix. When a specific 4bit binary line address code is applied, a
word of 10 parallel bits appears to the output. The lines can be sequentially
selected, providing a 9-word sequence of
10 parallel bits per word for each
character selected by the address inputs.
As the line address inputs are sequentially
addressed, the device will automatically
place the 10x9 character in 1 of 2
preprogrammed positions on the 16-line
matrix with the pOSitions defined by the 4line address inputs. One or more of the 10
parallel outputs can be used as control
signals to selectively enable functions
such as half-dot shift, color selection, etc.

Signetics

AppNote401
The 2670 DCGG includes latches to store
the character address and line address
data. A control input to inhibit character
data output for certain groups of characters is also provided. The 2670 also
includes a graphics capability, wherein
the 8-bit character code is translated
directly into 256 possible user programmable graphic patterns. Thus, the DCGG
can generate data for 384 distinct patterns, of which 128 are defined by the
mask programmable ROM.

2673 Video and Attributes
Controller (VAC)
The 2673, figure 5, is a bipolar LSI device
designed for CRT terminals and display
systems that employ raster scan techniques. It contains a high speed video shift
register, field and character attributes
logiC, attribute latch, cursor format logic
and half dot shift control, and can be
programmed for a light or dark screen
background.
The VAC visual attribute capabilities are
reverse video, character blank, blink,
underline, highlight, and light pen strikethru or, optionally, graphics. Each attribute
has a separate control input which is
latched internally when the AFLAG input is
asserted. If the AMODE input is low, the
attributes are valid for one character time.
If AMODE is high, the attributes remain
valid until the field is terminated by strobing in a new attributes set. The attributes
are double buffered on a row by row basis
internally so that field attributes can
extend across character row boundaries
thereby eliminating the necessity of starting each row with an attribute set
The horizontal dot frequency is the basic
timing input element to the VAC; internally,
this clock is divided down to provide a
character clock output for system synchronization. Ten bits of dot data are
parallel loaded into the video shift register
on each character boundary. The video
data is shifted out on three outputs at the
dot frequency. On the video output, the
video is presented as a three level signal
representing low, medium and high iniensities, and the three intensities are also
encoded on the two TTL compatible Video
outputs.

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET

2671 PROGRAMMABLE KEYBOARD AND COMMUNICATIONS CONTROLLER

.1

DATA

)I

080-7 {

REPEAT

K

BUS BUFFER

KEYBOARD ENCODER

I

KCL.K

f

CONTAOL

OPERATION CONTROL

Ii1l
CMR

WII
"MR
~

liV!

-- I .

1
KCO-3

CSR

KEYBOARD
SCANNER &
ENCODER/DECODER

"SR
AO- 2

I

XiNTJi

COMMAND DECODER

I

r------i
I
I
I
I

•

VECTOR GENERATOR

DATA

!

I
I

TIMING

I

BAUD RATe
CONTROL
RfGISTER

6

REGISTER

GND~

BAUD RATE
GENERATOR

~

KEYBOARD

VCC~

R,C

MEMORY

c:J

I

l!HiI'f

4X128X8
READ-ONLY

l------i

INTERRUPT CONTROL

IIITA

T,C

KAET

KRO-2

-

I--

iNi'li

KDRES

MODE & TIMING

KEY HOLDING
REGISTER

TONE

GENERATOR

I

TONE

I I

f--

TRANSMITIER

TRANSMIT
HOLDING REGISTER

XTAL11 BRCLK

XTAI.2

f

~

TRANSMIT
SHIFT REGISTER

1
RECEIVER
INTERRuPTS

RECEIVE
HOLDING REGISTER

TIMING

RECEIVE
CONTROLS

SHIFT REGISTER

Figure 3

Signetics

6·31

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET

2870 DISPLAY CHARACTER AND GRAPHICS GENERATOR

_Vee

-

8CD
OIl
CAD-CA7

....

DO-DO

.... -.....
...- -----'
Figure 4

2873 VIDEO AND ATTRIBUTES CONTROLLER

CCO
CCl
CC2

I

DCLK

L r--

10

.1

,

DO-DI

CHARA'''. .
CLOCK COUNTER

'I

V:=

-12111TS-

I
I

DOT

•

DATA
VIDEO

AND

,--

HOOT

ATTIIIIIITE
HIERARCHY

CURSOR

LOGIC

ARVID
A8LANK

AUL

An.UTEAND
CURSOR COH11IOL

......-

.

:I

I
FigureS

6·32

DRIVERS

t=:

BKGND
CBUNK

t

LOGIC...,

AFLO
AMaDE

LL

:::::I

VIDEO

TTLVID1
TTLVID2

-y

ALTPEN/AGM

LPl/GMD

--

.~

.....

. . .IIK
AHILT

AOD
BLINK
UL

~

Signetics

...

BLAH•

iI!IH

Vee
VB!!
GNO

MICROPROCESSOR DIVISION

JANUARY 1982

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
SYSTEM CONFIGURATIONS

vals in order to prevent visual disturbances of the displayed data.

The PVTC supports four common system
configurations of display buffer memory
interface, designated the independent,
transparent, shared, and row buffer
modes. The first three modes utilize a
single or multiple page RAM and differ primarily in the means used to transfer display data between the RAM and the CPU.
The row buffer mode makes use of a single
row buffer (which can be a shift register or
a small RAM) that is updated in real time to
contain the appropriate display data.

The CPU manages the data transfers by
supplying commands to the PVTC. The
commands used are:
1. Read/Write at pointer address.
2. Read/Write at cursor address (with
optional increment of address).
3. Write from cursor address to pOinter
address.
The operational sequence for a write to
memory operation is:
1. The CPU loads data to be written into
the display memory into the interface
latch.
2. The CPU writes the destination
address into the PVTC's cursor or
pOinter registers.
3. The CPU checks the PVTC 'RDFLG'
status bit to assure that any previous
operation has been completed.
4. The CPU issues a 'write at cursor with/

Independent Mode
The CPU to RAM interface configuration
for this mode is illustrated In figure 6.
Transfer of data between the CPU and display memory is accomplished via a
bidirectional latched port and is controlled
by the PVTC Signals read data buffer
(R'D'B), write data buffer (WDB), and buffer
chip enable (BCE). This mode provides a
non-contention type of operation that does
not require address multiplexers. The CPU
does not address the memory directly - the
read or write operation is performed at the
address contained in the cursor address
register or the pOinter address register as
specified by the CPU. The PVTC enacts
the data transfers during blanking inter-

without increment' or a 'write at pointer'

command to the PVTC.
5. The PVTC negates 'RDFLG', outputs
the specified address, and generates
control signals to perform requested
operation. Data is copied from the
interface latch into the memory.
6. The PVTC sets its 'RDFLG' status to
indicate that the write operation is completed.

Similarly, a read operation proceeds as
follows:
1. Steps 2 and 3 as above.
2. The CPU issues a 'read at cursor with/
without increment' or 'read at pOinter'
command.
3. The PVTC negates 'RDFLG', outputs
the specified address. and generates
control signals to perform the read
operation. Data is copied from the
memory to the interface latch and the
PVTC sets its 'RDFLG' status to indicate that the operation is completed.
4. The CPU checks the 'RDFLG' status to
see if the read is completed.
5. The CPU reads the data from the interface latch.
Loading the same data into a block of display memory is accomplished via the 'write
from cursor to pOinter' command:
1. The CPU loads the data to be written
into the display memory into the interface latch.
2. The CPU writes the beginning address
of the memory block into the PVTC's
cursor address register and the ending
address of the block into the pointer
address register.
3. The CPU checks the 'RDFLG' status bit
to assure that any previous operation
has been completed.
4. The CPU issues a 'write from cursor to
pOinter' command to the PVTC.

INDEPENDENT BUFFER MODE CONFIGURATION

REFRESH

2672

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74lS3B4

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SYSTEM DATA BUS

/

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Figure 6

Signetics

6·33

6

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
5. The PVTC negates 'RDFLG' and outputs block addresses and control signals to copy the data from the interface
latch into the specified block of memory.
6. The PVTC sets its 'RDFLG' status to
indicate that the block write is completed.
Similar sequences can be implemented on
an interrupt driven basis using the READY
interrupt output from the PVTC to inform
the CPU that a previously requested command has been completed.
Two timing sequences are possible for the
'read/write at cursor/pointer' commands.
If the command is given during the active
display window (defined as first scan line
of the first character row to the last scan
line of the last character rowl. the operation takes place during the next horizontal
blanking interval. If the command is given
during the vertical blanking interval, or
while the display has been commanded
blanked, the operation takes place
immediately.

For the 'write from cursor to pointer'
operation, the PVTC's BLANK output is
asserted automatically and remains
asserted until the vertical retrace interval
following completion of the command. The
memory is filled at a rate of one location
per two character times, plus a small
amount of overhead.

AppNote401
lowered to indicate that the CPU can
access the buffer.
In transparent mode, the PVTC delays the
granting of the buffer to the CPU until a
vertical or horizontal blanking interval,
thereby causing minimum disturbance of
the display. In shared mode, the PVTC will
blank the display and grant immediate
access to the CPU.

Shared and Transparent
Buffer Modes

Row Buffer Mode

In these modes the display buffer RAM is a
part of the CPU memory domain and is
addressed directly by the CPU. Both
modes use the same hardware configuration with the CPU accessing the display
buffer via three-state drivers (see figure
7). The processor bus request (PBREQ)
control signal informs the PVTC that the
CPU is requesting access to the display
buffer. In response to this request, the
PVTC raises bus acknowledge (BACK)
until its bus external (BEXT) output has
freed the display address and data busses
for CPU access. BACK, which can be used
as a 'hold' input to the CPU, is then

Figure 8 shows the hardware implementation for the row buffer mode. During the
first scan line (line 0) of each character
row, the PVTC halts the CPU and DMA's
the next row of character data from the
system memory to the row buffer memory.
The PVTC then releases the CPU and displays the row buffer data for the programmed number of scan lines. The bus
request (BREQ) control signal informs the
CPU that character addresses and the
memory bus control (MBC) signal will start
at the next falling edge of BLANK. The
CPU must release the address and data
busses before this time to prevent bus

PVTe SHARED OR TRANSPARENT BUFFER MODES

Figure 7

6-34

Signe1ics

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET

AppNote401

ROW BUFFER MODE CONFIGURATION

2X2111

jjjjEll
TO CPU

Figure 8

contention. After the row of character data
is transferred to the CPU, BREQ returns
high to grant memory control back to the
CPU.

A MINIMUM CHIP COUNT
TERMINAL IMPLEMENTATION
Figure 9 is the schematic of a minimum
chip count CRT terminal using the four
CRT set devices. Only 15 IC packages are
required for the complete Implementation,
including all keyboard encoding and RS232 level conversion for the serial interface. Despite this low chip count the terminal Is capable of providing an
impressive array of features including:
Display Format·
• 24 or 25 character rows
• 80 characters per row
Character Format.
• 7x9 dot matnx character In a
9x12 character block
• 96 ASCII alphanumeric characters
• 32 special symbols
• Block graphics
• Line drawing character set
Cursor'
• Underline or block cursor
• Optional blinking
Keyboard:
• 128 keys maximum
• Non-encoded

• Cursor control keys
• Numeric keypad
Serial Interface'
• Full or half duplex
• RS-232 compatible
• 16 baud rates with Internal baud
rate generator
• Character or block transmiSSion
Operating Modes:
• Normal
• TransParent (displays graphic
and control characters)
• Page or scroll With optional
smooth scroll
Visual Attributes.
• Blink
• Reverse Video
• Highlight
• Underline
• Non-display
The system utilizes the independent buffer
mode to minimize hardware requirements.
The dual port interface to the 2Kx8 display
buffer is via a Signetics 8X31 bidirectional
latch ThiS may be replaced by a unidirectionallatch such as the 74LS37 4 if reading
of the RAM's contents by the CPU is not
required.
The operating program for the terminal is
contained in the internal ROM of the 8049
microcomputer, which also provides the

Signetics

RAM required by the system program.
Since the majority of the terminal's
features are tailored by firmware, the ROM
size can be increased, either Internally or
externally, to support additional functions. 1

BASIC TERMINAL SOFTWARE
The software for a microcomputer based
terminal is closely tied to the system hardware configuration and its charactenstlcs.
If an Interrupt driven mode of operation IS
desired, the system hardware/software
design must be capable of prioritizing the
interrupts so that the system will correctly
service interrupts from different sources.
In a typical system, there are three interrupt sources' the keyboard, the communications Interface, and the Video timIng controller. The latter must usually be
assigned the highest priority since failure
to service an interrupt from the video timing controller on a timely basis may result
in visual perturbations on the display The
keyboard and datacomm interrupts can, in
most cases, absorb some time delay
before they are serviced since they
include one or more levels of data buffers.
lA pre-programmed 8049 microcomputer
containing the operating firmware for this
terminal will be available from Signetlcs.

6·35

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'"

MICROPROCESSOR DIVISION

JANUARY 1982

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
Often, a multi-level interrupt structure will
be required sc that a high priority Interrupt
requiring Immediate service can be serviced even while the system Is in the process of servicing a lower priority Interrupt.

BASIC TERMINAL SOFTWARE FLOWCHART

A simplified flowchart for the software for
an interrupt driven terminal Is shown In
figure 10. After application of power, the
microprocessor first performs a system
initialization routine which consists of five
parts:
1. Clear the microcomputer's scratchpad RAM.
2. Initialize the 2672 PVTC for the
desired screen format, monitor timIng parameters, cursor parameters,
and display start address.
3. Clear the CRT display by loading a
non display-code (usually an ASCII
'space', 20 hex) Into the buffer
memory.
4. Initialize the 2671 PKCC for the
desired keyboard and serial Interface modes.
5. Read any mode switches (e.g., full
or half duplex, baud rate, cursor
type, etc.) and set system parameters as required.
The processor can now enable its interrupts and walt In a loop until an interrupt is
received. When this happens, the processor first determines the source of the
Interrupt and then performs the required
system operation.
An interrupt from the CRT timing controller
usually Indicates that some Information Is
required for proper screen refresh operation. For example, the PVTC may issue a
'split screen' Interrupt to indicate that a
new address must be loaded Into Its
screen start registers In order for the next
character row to be displayed from other
than the next sequential address in memory. The CPU must service this Interrupt
within a finite time In order for the display
to operate correctly.
An Interrupt from the keyboard interface
may be either a displayable character or a
control function. Displayable characters
are usually transmitted to the host computer and also placed Into the buffer
memory for display on the terminal. Certain control characters, such as cursor
control keys or keyboard error codes, may
cause only local actions, whiie others will
also require transmission to the host.
An interrupt from the data communications
Interface may also be a displayable
character or a system control character. In

&·38

Figure 10

A DESIGN EXAMPLE

could have been included by selecting
another of the numerous microprocessor
devices on the market with greater
program memory capacity. Major features
of the terminal are summarized in table I.'

A fully operational emulation of an IBM
3101 terminal was designed and constructed using the Signetlcs CRT chip set.
The terminal Incorporates the majority of
the 3101 's functions. Selected functions
were not incorporated due to program
memory limitations. For example, the tabbing functions were developed and tested
but were left out In deference to the block
transmission functions. More features

'A data package for the design, Including
details of operation, schematic, and
program listing, is available upon request
by writing to:
Signetics Corporation
Microprocessor Applications Dept.
Mail Station 12-76
P.O. Box 409
Sunnyvale, CA 94088

either case the microprocessor must
determine the type of character and perform the necessary system operation.

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MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
Table 1 - TERMINAL FEATURES
Display Screen Format
Erase functions: erase EOl, erase
2000 character screen capacity (25
EOS, clear screen
rows x 80 columns)
Operator information area (25th Visual Attributes
Highlighted field
line)
Blinking field
Block-shaped cursor with optional
Non-displayed field
blinking
Underlined field
Displayable Graphic Set
Modes of Operation
95 ASCII characters for nonTransmission modes: character or
block (page or line)
transparent mode
128 characters for transparent
Normal or transparent
mode
7x9 character matrix In 9x12 field
Line Protocol
Asynchronous
7-bit ASCII with programmable
Keyboard
63-key main keyboard
parity
12-key control key cluster
One or two stop bits
12-key numeric keypad
Full or half duplex
Keyboard locklunlock under softOnline or local
ware control
Programmable
line
turnaround
Keyboard clicker
character for block mode (EOT I
Typamatic operation
ETX/CR/XOFF)
EIA RS232 interface
Communication line speed: 50 to
Edit Functions
9,600 baud
Cursor controls: up, down, left, right,
Screen Refresh Rate
home
- 60Hz
Cursor address read and write

Terminal Hardware
The block diagram of the 8035 based terminal is illustrated in figure 11. It is an
expanded version of the logic shown in
figure 9, the major difference being a
larger display RAM, to provide up to two
pages of screen data, and the addition of
several input ports to handle the large
number of option and set-up switches. The
terminal's software is contained in 4K of
program storage external to the 8035
The 2672 PVTC is programmed to operate
in the independent buffer mode with the
CPU isolated from the display RAM by two
74lS364 eight-bit latches, which provide
the path for data transfers between the
CPU and RAM. The PVTC, responding to
commands from the CPU, completely controls the data transfer To avoid display
interference, the PVTC is instructed to
complete the access during a blanking
interval. For massive display updates
(clear screen, load form, etc.) the PVTC is
instructed to blank the display and service
the data transfer immediately and continuously. Additional memory contention
cirCUitry is not necessary since the PVTC
provides all of the timing and addreSSing
(via cursor and pointer) necessary to complete the transfer. An Interrupt from the

6·40

PVTC informs the CPU when an operation
is completed.
The PVTC addresses the display buffer
memory, which contains both character
and attribute data. An attribute byte is
identified by the software by setting bit 7
of the byte to a logic 1. The RAM data outputs are applied to the 2670 DCGG, which
provides the character dot data information, and to the 2673 VAC.
The VAC is hardwired to operate in the
field attributes mode for this application.
An attribute character occupies a screen
pOSition but is not displayed unless the
ACD input to the VAC is asserted. Bit 7 of
the character byte identifies a character
as an attribute character if it is a 1. When
bit 7 on the RAM data bus is ai, the
attribute byte is latched into the VAC to
begin a new attributes field. Since the
attributes are double buffered in the VAC,
only one byte (at any character position) is
required to specify a field.
The bipolar VAC circuit serializes the dot
data from the DCGG Into a 17.5 MHz data
stream for the monitor. Two TTL-level
video outputs provide three levels of video:
blaCK, white, and gray.
The PKCC provides the asynchronous
data communications link at one of sixteen

5ignetics

AppNote401
selectable baud rates. The PKCC
addresses two 74lS145s which act as a
4-to-16 decoder to drive a 16x8 matrix
keyboard. Key depressions are detected
on the KRET input from a 74lS151 8-to-l
multiplexer. Each key depression is
debounced, encoded according to the
states of the SHIFT and CONTROL inputs,
and presented to the CPU. Repeat and
'typomatic' (auto-repeat) functions are
processed automatically by the PKCC.

Timing Calculations
One of the tasks required in the design
phase of the terminal is the selection of a
suitable monitor and calculation of the
PVTC register values to provide suitable
drive signals for the selected monitor.
The selection process begins with
calculation of the required horizontal scan
frequency. Each character will be contained in a 9 dot by 12 line field. Since
there are 25 display rows, the total number
of active scan lines will be 12 x 25, or 300.
To this we must add some number of scan
lines for the vertical retrace, which IS
typically 5 to 10 percent of the active scan
lines. For a screen refresh rate of 60 Hz,
this yields
H frequency ~ (60)(300)( 1.1) ~
18,900 Hz.
A Motorola monitor was selected for the
application. The major timing specifications for the mon itor are:
Horizontal frequency: 18.72 KHz ±
500 Hz
HOrizontal retrace: 8 us max
Horizontal sync width: 4 us min
Vertical frequency: 50/60 Hz
Vertical retrace: 750 us max
Vertical sync width: 50 us min
Monitor timing definitions are shown in
figure 12. The worksheet illustrated in
table 2 can be used to compute the
required timing and associated PVTC
register values. Some rough guesses are
required initially and several iterations
through the worksheet will usually be
required to arrive at final values. For
example, the character clock period must
be known to select the horizontal front
porch (HFP), sync width (HSYNC), and
back porch (HBP) values. An estimate of
the character period can be made initially
as follows:
Horizontal period ~ 1118,900 ~
52.9 us
Horizontal active = total - blank =
52.9 - 10 ~ 42.9 us
Character period ~ 42.9/80 ~ 0.53 us
approximately

JANUARY 1982

MICROPROCESSOR DIVISION

AppNote401

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET

HORIZONTAL AND VERTICAL TIMING
1------CH~:;5~W---------I
~----~

HOlAN"

HSYNC

~----~

L-

--1

'-I I--

FRONT PORCH (IR1)

--I I-

- I I_______________--'Il...____

r--

VBlANK

BACK PORCH (lR2)

HSYNC (1A2)

CHAR ROWS/SCREEN ( I A 4 ) - - - I

~LlNESPERROW(IRO)
--.Jr--------il

--I r--

I
rl

------~L

--l
r---Inl...-___

BACK PORCH (IR3)

FRONT PORCH (IR3)

VSYNC---I"ll..-_ _ _ _ _ _ _ _ _ _ _ _

r-

----1

VSYNC (FIXED AT 3)

eOUALIZING

.
I I I I I

CONSTANT

LINES/ROW

lAO

HSYNC
WIDTH

HBACK
PORCH

0

IA'

I

I

IIIIII

IA3

VFRONT
PORCH

VBACK
PORCH

o

o

LI-.LI.....L--,-IL-.LI-,-..L-l

6

CHARACTERS PER ROW
o

CHAR ROWS/SCREEN
o

IR4

I I

IA1

IIIIII

IA5

III

Figure 12
In calculating horizontal timing, an approximate ratio for the HFP, HSYNC, and HBP
of 1:2:2 respectively is recommended.
Table 2 contains the final values selected
for the application.

Memory Allocation
The 4K bytes of available buffer memory
were allocated as follows (all addresses
are in hex):
0000 to 004F: display data for row
25, status line
0050 to 0075: not used
0076 to 007F: CPU scratch pad
0080 to 07FF: display data for rows
1 to 24
0800 to OFFF: not used, available for
second page of display data
The PVTC's 'display buffer first address'
and 'display buffer last address' registers
are loaded with the values 0080 and 07FF
respectively so as to cause this portion of
the RAM to act as a circular buffer. Initially
the display data is organized in the RAM
as follows:
0080 to OOCF: row 1 data
0000 to 011 F: row 2 data

07BO to 07FF: row 24 data

When a scroll operation is reqUired, the
CPU changes the value in the PVTC's
'screen start' register from 0080 to 0000.
This effectively shifts the displayed data
up one row. Upon reaching the speCified
last buffer address (which is now the last
character in row 23), the PVTC automatically changes the addressing sequence to resume starting at 0080 for the
24th row. The display data IS now
organized:
- 0000 to 011 F' row 1 data
- 01 20 to 016F: row 2 data

tialized so as to cause an interrupt to be
issued at the beginning of row 24 The
CPU responds to this interrupt by changing the value in the screen start register to
0000. The PVTC then uses this value as
the starting address of the next (25th) row.
causing the status line to be displayed In
that position. The CPU must re-Ioad the
screen start register before the end of the
vertical blanking interval with the correct
value for the first character to be displayed on the screen.

Terminal Software
-

07BO to 07FF: row 23 data
0080 to OOCF: row 24 data

The CPU can clear the previous data in
0080 to OOCF so that a blank row appears
in the 24th position.
The status line (row 25) data is kept in a
separate section of RAM to eliminate the
necessity of moving the data whenever the
scrolling operation described above
occurs. Thus, the PVTC must be
instructed to change its addressing sequence at the beginning of the 25th row.
This is accomplished by use of the split
screen row interrupt capability. IR10, the
'split screen interrupt row' register, is in i-

Signetics

Because the 8035 microcomputer used in
the terminal provides only a single interrupt level, a totally interrupt driven software design could not be used. The interrupt was assigned to the PVTC to service
the split screen interrupt described above
and the operations reqUired to implement
the smooth scroll feature The keyboard
and datacomm functions are serviced by
polling the PKCC status register. Both the
keyboard interface and UART receiver are
double buffered in the PKCC, preventing
overrun even if they are not serviced immediately.
The program generally follows the typical
program flow described previously. At
system reset the 8035 Interrupts are dis-

6-41

MICROPROCESSOR DIVISION

JANUARY 1982

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
Table 2 - CRT TIMING WORKSHEET
1.

HORIZONTAL CHARACTER BLOCK (no of dots)

2.

VERTICAL CHARACTER BLOCK (no. of scan lines)

12

3.

VERTICAL REFRESH RATE. Hz ...... .

60

9
(lRO)

4.

CHARACTERS PER ROW .

80

(lR5)

5.

CHARACTER ROWS PER SCREEN ..... .

25

(lR4)

6

TOTAL ACTIVE VIDEO SCAN LINES (step 2 x step 5)

7.

VERTICAL FRONT PORCH (no of scan lines)

8.

VERTICAL BACK PORCH (no. of scan lines) ..

9.

VERTICAL RETRACE INTERVAL (step 8

300

+ 3)

4

(lR3)

12

(lR3)

15

10

TOTAL SCAN LINES PER FRAME (add steps 6, 7, and 9) ..

319

11

HORIZONTAL LINE RATE, KHz (step 3 x step 10)

12.

HORIZONTAL FRONT PORCH (character time units)

5

13.

HORIZONTAL SYNC WIDTH (character time units) ..

8

(lR2)

14.

HORIZONTAL BACK PORCH (character time Units)

9

(lR2)

15.

HORIZONTAL RETRACE INTERVAL (step 13

16.

TOTAL CHARACTER TIME UNITS IN ONE HORIZONTAL

19.14

+ step

14)

SCAN LINE (add steps 4, 12, 13, and 14) ...
17.

17

102

EQUALIZING CONSTANT ([step 16 I 2J - [2 x step 13])

(lR1)

35

18.

CHARACTER CLOCK RATE, MHz (step 16 x step 11) ..... .

1.95228

19.

CHARACTER PERIOD, us (1 I step 18)

0512

20

SCAN LINE PERIOD, us (step 19 x step 16) ..

53.27

21.

DOT CLOCK RATE, MHz (step 18 x step 1) .

1757052

PARAMETER
A.

HORIZONTAL RATE, KHz

SPEC

ACTUAL

18.72 ± 0.5

1914

B. HORIZONTAL RETRACE TIME, us

8

8.7

C. HORIZONTAL SYNC WIDTH

4

4.1

50 - 60

60

750

784

50

157

D

VERTICAL RATE, Hz

E

VERTICAL RETRACE TIME, us

F

VERTICAL SYNC WIDTH, us

abled, data memory and display memory
are cleared to zeroes, and both the PVTC
and PKCC are master reset through software commands The system option
switches are then read and stored and the
PVTC and PKCC internal registers are initilized for the selected operation Finally,
the initial data for the status line is loaded,
the PVTC, UART, and keyboard are
enabled, and the CPU Interrupt is enabled.

6·42

The program then enters a loop where the
PKCC is checked for keyboard or UART
entries. If an entry has occurred, the
character is fetched and stored in a software controlled FIFO (first-in-first-out)
memory which IS eight bytes deep for both
receiviiig or transmitting characters (the
need for the FIFO is described below). If
either FIFO has an entry, the program proceeds to a character recognition routine

Signetics

AppNote401
which checks for the type of character
(displayable or control) and the appropriate handling subroutine (ESC sequence,
control
sequence,
cursor
control,
character display, etc.) is called. If the
FIFO's are empty, the polling routine
checks the option switches for any
changes since reset entry and if so reconfigures the system as necessary.
The need from the FIFOs results from the
method used to effect the clear row function required when a scroll IS performed
Although the PVTC includes a 'clear from
cursor to pOinter' command that can be
used to clear a block of memory rapidly,
the display is temporarily blanked during
this operation. This would cause undesirable flashes on the display. Instead, the
program does the function by a repetitive
loop using the 'write at cursor and increment' command. Since the write occurs
only once per scan line during the active
display window, a worst case total of approximately 80 scan line times IS reqUired
to execute the routine. This would limit the
maximum received character rate to approximately one per 80 scan lines or about
240 characters per second (2400 baud).
To overcome this limitation, the PKCC is
also polled each time through the clear
line subroutine loop, and any entries from
the receiver or keyboard are stored in the
appropriate FIFO. Since the FIFO IS eight
deep, this allows eight characters to be
received in the same time, increaSing the
maximum baud rate to 19,200. (Other
program limitations actually reduce the
maximum baud rate to 9600 baud)
However, thiS does not increase the rate at
which characters which cause a scroll
function to occur, such as a line feed, can
be received. Each character of this type
must be followed by 'fill' characters in
order for data rates higher than 2400 baud
to be used
An interrupt from the PVTC will occur
when the display scan reaches the row
count programmed in its split screen
address register, row address 24 (for the
24th row). In response to the interrupt, the
CPU loads the screen start registers with
the address of the status line (0000) and
enables the PVTC's line zero Interrupt.
This causes another interrupt at the beginning of display of the status line. At this
time the CPU reloads the screen start
register With the proper address to begin
the next display frame and disables the
line zero interrupt.

If scrolling is reqUIred the screen start
register value is incremented by 80 (popping off the top row) and the effective bottom row cleared to nulls. If soft scrolling is

JANUARY 1982

MICROPROCESSOR DIVISION

USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
selected, additional functions are performed during the Interrupt routines. To
begin the operation, the line zero interrupt
routine adds ten lines to the vertical back
porch. This causes the next active screen
display to begin ten scan lines later than
normal and gives the effect of the display
moving up two scan lines (12 lines per
character row - 10) instead of jumping up

12 lines. If nothing else were changed,
however, the bottom of the display would
move down ten lines. Thus, during the row
24 interrupt the number of scan lines per
character row is changed to two (12-10),
causing only the first two scan lines of that
row to be shown. The next line zero interrupt (at row 25) restores the lines per row
count back to 12 to keep the whole status

AppNote401
line showing, and now changes the vertical back porch to 8. The display moves up
two more scan lines and at the next row 24
interrupt four scan lines are shown The
process continues in this manner, providing the effect of the entire display, except
for the status line, smoothly scrolling up
over a selected interval of six frames, or
one tenth of a second

=

Signetics

6·43

6

MICROPROCESSOR DIVISION

JANUARY 1982

2661 OPERATING MODE SWITCHING PROCEDURES
INTRODUCTION
This application note describes procedures for switching the operating mode
of the Signetics' 2661 Enhanced Programmable Communications Interface (EPCil
from echoplex or remote loopback mode
to normal operation and vice-versa.

ECHOPLEX (AUTOMATIC
ECHO) MODETONORMAL
OPERATION
The echoplex operation is initiated by setting command register bits CR7:CR6 =
01, and CR2 (receiver enable bit) = 1.
Echoplex operation is terminated by
resetting CR2 to zero. To ensure the
proper transmission of the last received
character, no change of operating mode
should be made until the end of that
character. However, If mode switching is
necessary in certain applications, the
following procedure is recommended to
ensure no garbling on the last transmitted
character. Two potential problems may
arise: the calculated parity Instead of the
received parity may be transmitted, and
data rate may be shortened or lengthened.
The procedure provides the necessary
handshaking to avoid these potential
problems by making use of the TXEMTI
DSCHG pin or of the status register bit 2,

SR2, to indicate the end of the parity bit or
the first stop bit, depending on whether
one or two stop bits are selected
(MR17:MR16 = 01 or 11). The procedure
causes TXEMT/OSCHG to be driven to Its
active state only at the completion of the
last cheracter, as shown in figure 1.
The recommended sequence of operation
is as follows:
1. Wait for RXRDY (either RXRDY interrupt or status read). This Is necessary
for the assembly of the last character
to be completed and to ensure the
transfer of this character to the
transmitter.
2. Enable the transmitter by setting CRO
to one.
3. Disable the receiver by setting CR2 to
zero.
4. Walt for TXEMT (either TXEMTI
OSCHG interrupt or status read). At
this pOint, the parity bit or the first stop
bit (if two stop bits are selected) has
been sent out.
5. Change mode from echoplex to normal.
6. Load new character Into the transmit
holding register, THR. Further communication between the 2661 chip and
the CPU will resume as normal - that is,
TXRDY Is driven active to indicate that
the THR is available for new data and

TXEMTIDSCHG OPERATION FOR ECHOPLEX MODE SWITCHING

•

~L~~~':"-1L?~2~2~2~2~2~2~2~/2~2~2~2~/2~2~2~4ac2P~"~~~tl~~~w~t----------------I
I

I
I

I
I

-1
-----+.,----------

;";;:EM:::';;'DS:::C:;::'O:---------------------------ii - ORlvENACnvEH:::'' :.:''c.:ON=:':.::s,:.::oP'--__ !-,
BIT IS SELECTED-

_

I

I
I

I

I

I

~~A~:~~c~~~E._,,_mo_s_'o_p_~I~_ _
,:

Figure 1
SWITCHING FROM NORMAL TO ECHOPLEX OR REMOTE LOOPBACK

vz?//'lZ2V'L/~

I

I

·--_. Ie I\'U~-"'"'0'

~~:i~,,",, ~!
CHANGE TO ECHOPLEX OR REMOTE

Figure 2

6·44

.'0""

I

---.I

AppNote402
TXEMT is driven active upon underrun
condition.
Note that the TXEMT pin Is not driven
active In echoplex mode. It Is optionally
driven active when the above steps are
followed, particularly the transmitter being
enabled as Indicated in step 2. Because
the transmitter relies on CRO = 1 and CR2
= 0 to drive TXEMT active, It is necessary
to set CRO to zero In echoplex mode If it is
desired not to drive TXEMT active. CRO,
transmitter enable, Is Ignored for data
transmission in echoplex mode. It Is,
however, used to determine whether
TXEMT should be driven active.
If frequent mode switching is anticipated
and it is desired to drive TXEMT active,
step 2 of the above procedure could be
skipped, provided that the echoplex
operation Is Initiated by enabling both the
receiver and the transmitter - that is,
CR2:CRO = 11.
The TXEMT timing shown above is only
applicable when switching modes. Note
that in normal operation, TXEMT is driven
active at the beginning of the last data bit
or parity bit upon underrun condition.

REMOTE LOOP BACK MODE TO
NORMAL OPERATION
The procedure is similar to the procedure
for echoplex to normal, with the following
exceptions:
1. No handshaking with RXRDY is
required.
2. During step 3 of the previous procedure, CR2 goes to zero, and
CR7:CR6 should be simultaneously
changed from 11 to 01 (remote to echoplex). This Is necessary because the
logic Implemented to drive TXEMT
active relies on echoplex information.
However, this requirement does not
need additional service from the controller because remote-to-echoplex
switching Is done at the same time as
disabling the receiver.

NORMAL OPERATION TO
ECHOPLEX OR REMOTE
To avoid garbling the last transmitted
data, a mode switch from normal operation
to echoplex or remote operation should be
performed as follows:
1. Walt for TXEMT (either TXEMTI
DSCHG Interrupt or status read) to be
asserted.
2. Disable the transmitter by, setting CRO
to zero.
3. Walt for TXEMT to be negated.
4. Change the mode from normal operation to echoplex or remote.
The timing Is illustrated In figure 2.

SigneHcs

Section 7
Appendices

Signetics

JANUARY 1982

MICROPROCESSOR DIVISION

PACKAGE OUTLINES
INTRODUCTION
The following Information applies to all
packages unless otherwise specified on
Individual package outline drawings.

General
1. Dimensions shown are metric units
(millimeters), except those In par·
entheses which are English units
(Inches).
2. Lead spacing shall be measured with·
in this zone.
a. Shoulder and lead tip dimensions
are to center·line of leads.
3. Tolerances non·cumulatlve.
4. Thermal resistance values are deter·
mined by utilizing the linear temper·
ature dependence of the forward volt·
age drop across the substrate diode in
a digital device to monitor the Junc-,
tlon temperature rise during known
power application across Vee and
ground. The values are based upon
120 mils square die for plastic pack·
ages and a go mils square die In the
smallest available cavity for hermetic
packages. All units were solder
mounted to P.C. boards, with standard
stand·off, for measurement.

7·2

Plastic Only
5. Lead material: Alloy 42 (Nickel/Iron
Alloy) Olin 194 (Copper Alloy) or
equivalents, solder dipped.
6. Body material: Plastic (Epoxy)
7. Round hole In top corner denotes lead
No.1.
8. Body dimensions do not Include
molding flash.

Hermetic Only
9. Lead material
a. ASTM alloy F·15 (KOVAR) or equiv·
alent-gold plated, tin plated, or
solder dipped.
b. ASTM alloy F·30 (Alloy 42) or equiv·
alent-tin plated, gold plated, or
solder dipped.
c. ASTM alloy F·15 (KOVAR) or equlv·
alent-gold plated.
10. Body Material
a. Eyelet, ASTM alloy F·15 or equlv·
alent-gold or tin plated, glass
body.
b. Ceramic with glass seal at leads.
c. BeO ceramic with glass seal at
leads.
d. Ceramic with ASTM alloy F·30 or
equivalent.

SIgletics

11. Lid Material
a. Nickel or tin plated nickel, weld
seal.
b. Ceramic, glass seal.
c. ASTM alloy F·15 or equivalent, gold
plated, alloy seal.
d. BeO ceramic with glass seal.
12. Signetics symbol, angle cut, or lead
tab denotes Lead No.1.
13. Recommended minimum offset bafore lead bend.
14. Maximum glass climb 0.010 inches.
15. Maximum glass climb or lid skew is
0.010 inches.
16. Typical four piaces.
17. Dimension also applies to seating
plane.

MICROPROCESSOR DIVISION

JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC
(16·PIN)

7

I PACKAGE - HERMETIC
(16·PIN)

I ~[~~]~fj
=-=-=--I
,•

OZOl

165(.065)
o S1 (

1

2070 calS)
19.93 (785)
12.95(.510)
12.45 (.490)

_I

~
0.63 f.025J

8.13(.3201
7.37(2901

,3, 005"I.N~.~~~~~~~ryOJ;!~~l~~~~~~~~~i::i
_-+__

031 (012)

~ 0.20(008)

, .8.741.3441
7.11 (.280)

.1

2.79 (110)
2.29 (.090)
NON·
CUMULATIVE

Signetics

7·3

MI~ROPROCESSOR DIVISION

JANUARY 1982

PACKAGE OUTLINES

N PACKAGE -

PLASTIC SLIM LINE
(24-PIN)

LEAD NO 1

r--

0381.015)

D.25To1Oi
053 (021)

0381015)

2.791110)
2291.090)
NON·
CUMULATIVE

I PACKAGE -

HERMETIC SLIM LINE
(24·PIN)

CONTACT YOUR SIGNETICS SALES OFFICE

7·4

Signefics

JANUARY 1982

MICROPROCESSOR DIVISION

PACKAGE OUTLINES

N PACKAGE - PLASTIC
(28·PIN)

LEAONQ 1

01

o

1410(555)

hn~TTrM~TrrnTTrn~TTrn~::L·~O'

IV V V V V

"'36.86/1.465/

VVVV

:.::

I~~~

r--~----'~"
I--~~~
.94 .,00,1,...'4.99(.0.0'""'\1.1:.(060'

~

mT.'14si

1.32 (.052)

1.l2T044i
~

0.38 (0151

~

2.79(.110)
fi9T.'09ijj'

'-~0.3!::.~(.:::O'~0'~
0.25 (010)

:!:!! I-- 17 65 ( 6951--..1
(~1~1 I 15.2iT.6OOi
I

(.12ijj

165 (.0651

NON·
CUMULATIVE

7

I PACKAGE - HERMETIC
(2S·PIN)

!

,.,.................................---.

LEAD NO 1

D

NON·
CUMULATIVE

Signetics

7·5

MICROPROCESSOR DIVISION

JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC
(40·PIN)

LEAD NO.1

17.651.6951
15.241.6001

0.51.0201
NON·

0.4 (.016)

CUMULATIVE

I PACKAGE - HERMETIC
(40·PIN)

[~~~~~~[::::]~~~~~~1~

~::~.~~~:~
~15.741.620I-l
~
",.,."
~~,~~
''''=, •• ,=, t:~t~1
T
I~!====If=;::J
~
J ~
~
l
3.05t201

-L

~ ;~ ~ g~~:

1-

I
I-

~....
038 (015)

7·6

~

1295(.510)--'

12.95(.510

0.76(,030)

i - 16.36 1.6441 --J

I-

:.~: ~ g:~:

14731.5801--'

4.451.1751

NON

CUMULATIVE

Signetics

3'i'iT.i'2si

0.20 (.OOSI

JANUARY 1982

MICROPROCESSOR DIVISION

SALES OFFICES
Melville
Phone (516) 752-0130

SIGNETICS
HEADQUARTERS

In~ewood

hone (213) 670-1101

Irvine

NEVADA

~~~~e TI~~~)o~o5~-9986

CANADA
SIGNETICS CANADA, LTD,
Etoblcoke, OntarIo
Phone (416) 626-6675
StGNETICS CANADA, LTD.!lTEE,
POlnte-Cla"e, &uebeC
Phone (514) 6 7-3385

COLORADO
Aurora
Phone (303) 7515011
CONNECTtCUT
Danbury
Phone (203) 744-6066

NEWMEXtCO

AlbpUo~:~~~~erprlses
Phone (505) 298-1918

REPRESENTATIVES

DELAWARE
Call Micro-Camp, Baltimore
Phone (301) 247-0400
FLORID
Lighthouse pOint~
hone (~05)7828225
GEORGIA-----.,..
Atlanta
:JO~(,
Phone (404) 953-{1067 ~
ILLINOIS

813)7'''<\t. )

ALABAMA
Huntsville
ElectronIC Sales, Inc
Phone (205) 533-1735
CALIFORNIA
Los Gatos

~'~~r;e T(1~~)\On-9986

San Diego

~~~~eE(m)efin/8021

CONNECTICUT
Danbury
Kanan ASSOCiates
Phone (203)265-2404
FLORIDA

MARYLAND
Glen Burnie

Phone (301)787-0220

MASSACHUSETTS
Woburn
Phone (617)938-1000

Elk Grove Village
Mlcro-Tex, Inc
Phone (312)640-9633

MICHIGAN
Farmington Hills
Phone (313)476-1610

FO[:~f~~e s, Inc

NEW YORK
Liverpool
Phone (315)451-5470

MISSOURI
SI. LoUIS
B C Electromc Sales
Phone (314) 731-1255

UTAH
Bountilul
Phone (801) 298-2624

Phone (7l~ 833-8980
(213) 588-3 81
San Diego
Phone (714) 560-0242

NEW JERSEY
Cherry Hill
Phone (609) 665-5071
Piscataway
Phone (201)981-0126

MINNESOTA
Edina
Mel Foster Techmcal Sales
Phone (612) 941-9790

TEXAS
Austin
Phone (512) 458-2591
Dallas
Phone (214) 661-1296

cu~~r~~~o (408) 725-8100

MINNESOTA
Edina
Phone (612)835-7455

MICHIGAN
Bloomlield Hills
Enco Marketing
Phone (313) 642-0203

TENNESSEE
Greeneville
Phone (615) 639-0251

CALIFORNIA
Canoga Park
Phone, (213) 340-1431

KANSAS
Overland Park
Phone (913) e41-8181

MASSACHUSETTS
Reading
Kanan Associates
Phone' (617) 944-8484

OHIO
Worthington
Phone (614) 888-7143

ARIZONA
Phoenix
Phone (602) 2654444

INDIANA
Kokomo
Phone (317) 453-6462

wa~~~nn~erfgftll~974074
NORTH CAROLINA
Raleigh
Phone (919) 851-2013

811 East Arques Avenue
PO Box 409
Sunnyvale, Cahlorma 94086
Phone (408) 739-7700

sC~~~~~U[Jl2) 843-7805

MARYLAND
Baltimore
MlCro-Comp, Inc
Phone (301) 247-0400

INDIANA
Phone &19)482-1596
Indianapolis
Insul-Re~s, Inc
Phone (317)842-5203
IOWA
Cedar Rapids
Comstrand Inc
Phone (319)377-1575
KANSAS
Shawnee Mission
B C Electromc Sales
Phone (913) 888-6680

NEW YORK
Ithaca
Bob Dean, Inc
Phone (607) 272-2187
OHIO
Cleveland
Norm Case ASSOCiates
Phone (216) 333-4120

Da~~r~ Case ASSOCiates

Phone (800)362-6631

OKLAHOMA
Tulsa
Cunmngham Co
Phone (918)492-0390
OREGON
Hillsboro
Western Techmcal Sales
Phone (503) 640-4621
TEXAS
Ausltn
Cunningham Co
Phone (512)459-8947
Dallas
Cunmngham Co
Phone (214)233-4303
Houston
Cunningham Co
Phone (713)461-4197
VIRGINIA

LY~~~~~mp, Inc

Phone (804)237-6221

WASHINGTON
Bellevue
Western TechnICal Sales
Phone (206)641-3900
Spokane
Western Techmcal Sales
Phone' (509)9227600
WASHINGTON, D,C,

~~lbn~'I%tof4M:ri~more

Signetics

WISCONSIN
Waukesha
Mlcro-Tex, Inc
Phone (414) 542-5352

DISTRIBUTORS
ALABAMA
Huntsville
Hall-Mark Electromcs
Phone (205) 837-8700
HamlltonlAvnet Electromcs
Phone (205) 837-7210
Pioneer Electromcs
Phone (205) 837-9300
ARIZONA
Phoenix
Ham"ton/Avnet ElectroniCS
Phone (602) 894-9600

~~b~~'M~~I~~~~~~'¥'
CALIFORNIA
Costa Mesa
Avnet Electromcs
Phone (714) 754-611l
Hamilton Electro Sales
Phone (714) 6414100
Culver City
HamlltonlAvnet Electromcs
Phone (213) 558-2121
HamlltonlAvnet Electromcs

Ph~ri~ta[!13) 558-2901
EI Segundo
Wyle DlSt"bulion Group
Phone (213)322-8100
Irvine
Schweber Electromcs
Phone (714)556-3880
Wyle DlSt"bulion Group
Phone (714)979-2125
San Diego
Anthem Electromcs
Phone (714)279-5200
HamlltonlAvnet Electromcs
Phone (714) 571-7510
Wyle DlSt"butlon Group
Phone (714)565-9171
San Jose
Anthem Electromcs Inc
Phone (408) 946-8000
Santa Clara
Schweber Electromcs
Phone (408)496-0200

7

~Kben~'il~~I~~~%~W'
Sunnyvale
A"ow Electromcs
Phone (408)745-6600
HamlllonlAvnet Electromcs
Phone (408)743-3366
CANADA

Calr,~ill~I~/~J~et Electromcs

Phone (403)230-3586
Downsvlew, Ontario
Cesco Electromcs
Phone (416)661-0220
Mississauga, Ontario
HamlltonlAvnet ElectroniCs
Phone (416)677-7432
Zentromcs
Phone (416)451-9600

7·7

JANUARY 1982

MICROPROCESSOR DIVISION

SALES OFFICES
Montreal, Quebec
Cesco Electronics
Phone (514) 735-5511
Zentromcs
Phone (514) 735-5361
Ottawa, Ontario
Ceseo Electronics
Phone (613) 719-5118
HamlltonlAvnet Elecrromes
Phone (613) 116-1700
Zentromcs
Phone (613) 138-6411
Quebec City
Ceseo Eleetromcs
Phone (418) 514-4641
Ville 51. Laurent, Quebec
HamlltonlAvnet Electromes
Phone (514) 331-6443
COLORADO
Denver
Arrow Electromes
Phone (303) 758-1100
Wyle DlStnbution Group
Phone (303) 457-9953
Englewood
HamlltonlAvnet Eleetromcs
Phone (303) 740-1000
CONNECTICUT
Danbury
HamlltonlAvnet Eleetromes
Phone (203) 797-2800
Schweber Eleetromes
Phone (203) 792-3500
Wallingtord
Arrow ElectroniCS

Phone (203) 265-7741
FLORIDA
FI. Lauderdale
Arrow ElectroniCS
Phone (305) 176-7790
HamlltonlAvnet Electromcs
Phone (305) 971-2900
Hollywood
Schweber Electromes
Phone (305) 927-0511
Palm Bay
Arrow Electromes
Phone (305) 725-1480
51. Petersburg
HamlltonlAvnet Electromes
Phone (813) 576-3930
GEORGIA
Atlanta
Sehweber Eleetromcs
Phone (404) 449-9170
Norcross
Arrow Eleetromcs
Phone (404) 449-8252
HamlltonlAvne! Eleeiromes
Phone (404) 447-7500
ILLINOIS
Chicago
Bellindust"es
Phone (312) 982-9210

7·8

Elk Grove
Schweber Electronics
Phone (311) 364-3750
Schaumburg
Arrow Electromcs
Phone (311) 893-9410
Bensenville
HamlltonlAvnet Electromcs
Phone (311) 8607700
INDIANA
Indianapolis
Pioneer Electronics
Phone (317) 849-7300
Arrow Eleerromcs
Phone (317) 143-9353
HamlltonlAvnet Electronics
Phone (317) 844-9333
KANSAS
Overland Park
HamlltonlAvnet Electronics
Phone (913) 888-8900
MARYLAND
Baltimore
Arrow Electronics
Phone (301) 147-5100
Columbia
HamlitonlAvnet Eleetromcs
Phone (301) 995-3500
GaitherSbUW
Pioneer ashlnYion Electronics
Phone (301) 94 -0710
Sehweber Eleetromes
Phone' (301) 840-5900
MASSACHUSETIS
Bedford
Sehweber Eleetromes
Phone (617) 275-5100
Burlington

~'~~n': ~3[Y) 272-9400

Woburn

Arrow Eleetromes
Phone (617) 9338130
HamlltonlAvnet Eleetromes
Phone (617) 173-7500
MICHIGAN
Ann Arbor
Arrow Eleerromes
Phone (313) 971-8220
Grand RapIds
HamlltonlAvnet Eleetromes
Phone (616) 243-8805
Livonia
HamlltonlAvnet Eleetromes
Phone' (313) 522-4700
Pioneer Electromes
Phone (313) 525-1800
Sehweber Electromes
Phone (313) 525-8100
MINNESOTA
Eden Prairie
Sehweber Eleetromes
Phone (612) 941-5280
Minneapohs
Arrow Electromes
Phone (612) 830-1800
HamlltonlAvnet Eleetromes
Phone (612) 932-0600
MISSOURI
Earth City
Hamllton/Avnet Electromes
Phone (314) 344-1200
51. Louis
Arrow Electromes
Phone (314) 567-6888

NEW HAMPSHIRE
Manchester
Arrow Electronics
Phone' (603) 668-6968
NEW JERSEY
Cherry Hill
HamlltonlAvnet Eleerromes
Phone (609) 414-0100
Fairfield
HamlltonlAvnet Electronics
Phone (101) 575-3390
Schweber E~clromes
Phone (101) 117-7880
Moorestown
Arrow Eleetromcs
Phone' (609) 135-1900
Saddlebrook
Arrow Eleetromcs
Phone (101) 797-5800
NEW MEXICO
Albuquerque
HamlltonlAvnet Electronics
Phone (505) 765-1500
NEW YORK
BuHalo
Summit DlStnbutors
Phone' (716) 887-2800
East Syracuse
Arrow Electromes
Phone (315) 652-1000
HamlltonlAvnet Electromcs
Phone' (315) 437-2642
Farmingdale, L.I.
Arrow Electronics
Phone' (516) 694-6800
Liverpool
Arrow Eleetromes
Phone (315) 651-1000
Melville
HamlltonlAvnet Electronics
Phone (516) 454-6012
Rochester
Arrow Electromes
Phone (716) 175-0300
HamlitonlAvnet Electromcs
Phone (716) 475-9130
Sehweber Eleetromcs
Phone (716) 424-2222
Westbury, LI.
Sehweber Electromcs
Phone' (516) 334-7474
NORTH CAROLINA
Greensboro
Pioneer Electromcs
Phone (919) 273-4441
Raleigh

~~~~~o(~~~r~~§lio~~mes

Winston-Saillm
Arrow Elee~omcs
Phone (91 ) 725-8711
OHIO
Beeetrwood
Sehweber Eleetromes
Phone (216) 464-1970
Cleveland
HamlltonlAvnet Eleetromes
Phone' (216) 831-3500
Pioneer Eleetromes
Phone (216) 587-3600
Centerville
Arrow Electronics
Phone. (513) 435-5563

Signetics

D"ri~o~ilton/Avnet Electromcs

Phone- (513) 433-0610
Pioneer Standard Elecrromcs
Phone' (513) 136-9900
Solon
Arrow Electromcs
Phone: (116) 148-3990
OKLAHOMA
Tulsa
~uahty Components
hone: (918) 664-8811
OREGON
Lake Oswego
HamiltonlAvnet Electromes
Phone (503) 635-8831
PENNSLYVANfA
Horsham
Sehweber Eleetromes
Phone (115) 441-0600
Pittsburgh
Arrow Electromes
Phone, (412) 856-7000

~ho~n':.r;~lmb7~~~300
TEXAS
Austin
HamlltonlAvnet Electromcs
Phone (512) 837-8911
~uahty Components
hone' (512) 835-0220
Dallas
Hall-Mark Electromcs
Phone' (214) 341-1147
HamlltonlAvnet Electromcs
Phone' (214) 659-4111
~uaity Components
:, ilione, (214) 387-4949
'- 'Sehweber,!:leetromcs
, J'fi'one"(2r4) 661-5010
Houst..
~a~'lton/Avnet Eleetromes
Ph ne: (713) 780-1771
~uahty Components
hone. (713) 771-7100
Schweber Electromes
Phone. (713) 784-3600

.

,

UTAH
Salt Lake Ci%
Hamlltonl vnet Electromes
Phone (801) 972-4300
WASHINGTON
Bellevue
Arrow Eleetromcs
Phone (206) 643-4800
HamlltonlAvnet Eleetromes
Phone (206) 453-5844
Wyle DIStribution Group
Phone' (206) 453-8300
WISCONSIN
Oak Creek
Arrow Electromcs
Phone (414) 764·6600
New Berlin
Hamiiton/Avne! Eleetromes
Phone, (414) 784-4510

Iii nOliC
bf U.S. Philips Corporation
Signetics Corporation

en East Arques Avenue

Po. Box 40.9
94086
Telephone 408/ 739-770.0.

Sunnyvo~ California

800000

Copyrig ht 1981 Signe ti cs Co rporat ion
Pr inted in U.S.A
15M0182



---

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