1982_Siliconix_Analog_Switch_and_IC_Product_Data_Book 1982 Siliconix Analog Switch And IC Product Data Book
User Manual: 1982_Siliconix_Analog_Switch_and_IC_Product_Data_Book
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analog switch
& Ie product
data book
H
Siliconix
incorporated
Siliconix Analog Switch
& Ie Product Data Book
January 1982
Siliconix incorporated reserves the right to make changes in the
circuitry or specifications at any time without notice and assumes no
responsibility for the use of any circuits described herein and makes
no representations that they are free from patent infringement.
© 1982 Siliconix incorporated
Printed in U.S.A.
0·3
Numeric-Alpha Index
TYPE I
TYPE I
PAGE
LD 110 .............................. 7-15
LD 111A ............................ 7-15
G 115.............................. 5-1
G 116... ........ .... ............... 5-3
G 117 ..............................
5-5
G 118 .............................. 5-6
G 119 .............................. 5-9
LD 120 .............................. 7-41
LD 121A............................ 7-41
G 122 .............................. 5-11
LD
121 .............................. 7-66
D 123............... ...... .........
1-8
DG 123............... ............... 3-3
G 123.............................. 5-13
D 125.............................. 1-10
DG 125.............................. 3-6
DG 126.............................. 3-9
D 129.............................. 1-12
DG 129 .............................. 3-12
DG 133 .............................. 3-12
DG 134.............................. 3-9
D 139.............................. 1-14
DG 139.............................. 3-15
DG 140.............................. 3-18
DG 141 .............................. 3-18
DG 142 .............................. 3-21
DG 143 .............................. 3-21
DG 144.............................. 3-15
L 144.............................. 6-1
DG 145 .............................. 3-24
DG 146 .............................. 3-24
DG 151 .............................. 3-27
DG 152 .............................. 3-30
DG 153 .............................. 3-27
DG 154 .............................. 3-30
DG 161 .............................. 3-33
L 161.............................. 6-11
DG 162 .............................. 3-36
DG 163 .............................. 3-33
DG 164 .............................. 3-36
D 169 .............................. 1-20
DG 172 .............................. 3-39
DG 180 .............................. 3-42
DG 181 .............................. 3-42
DG 182 .............................. 3-42
DG 183 .............................. 3-42
DG 184 .............................. 3-42
DG 185 .............................. 3-42
DG 186 .............................. 3-42
DG 187 .............................. 3-42
DG 188 .............................. 3-42
DG 189 .............................. 3-42
DG 190 .............................. 3-42
DG 191 .............................. 3-42
DG 200 .............................. 3-48
DG 2OOA............................ 3-52
DG 201 .............................. 3-55
DG 201A............................ 3-58
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
PAGE
202 ..............................
211 ..............................
212 ..............................
243 ..............................
281 ..............................
284 ..............................
287 ..............................
290 ..............................
300 ..............................
300A .............................
301 ..............................
302 ..............................
303 ..............................
304 ..............................
305 ..............................
306 ..............................
307 ..............................
307A............................
308 ..............................
3-61
3-63
3-69
3-71
3-75
3-75
3-75
3-75
3-79
3-86
3-79
3-79
3-79
3-79
3-79
3-79
3-79
3-86
3-90
l1li
-.....
309 .............................. 3-94
DF 320..............................
2-1
DF 320A............................. 2-1
DF 322..............................
2-1
DF 328 .............................. 2-12
DG
DG
DG
DG
DG
DG
DF
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o
Q.
c:
381 .............................. 3-81
381A ............................. 3-86
384 .............................. 3-81
387 .............................. 3-81
390 .............................. 3-81
390A ............................. 3-86
412......... .......... ........... 1-1
501.............................. 4-1
503.............................. 4-5
506.............................. 4-9
507.............................. 4-9
508 .............................. 4-17
508A ............................. 4-25
509 .............................. 4-17
509A ............................. 4-25
515.............................. 8-1
516.............................. 8-1
528 .............................. 4-29
529 .............................. 4-29
1525B ............................ 6-22
1527B ............................ 6-22
2525B ............................. 6-22
2527B ............................. 6-22
3002 ............................. 3-101
3525B ............................. 6-22
3527B ............................. 6-22
3705............................. 4-37
"o..._.
:::s
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
DG
Si
Si
Si
Si
Si
Si
Si
Si
DG 5040............................. 3-96
DG 5041............................. 3-96
DG 5042 ........................... " 3-96
DG 5043............................. 3-96
DG 5044 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-96
DG 5045............................. 3-96
Siliconix
0·5
About This Edition of the
Siliconix Integrated Circuit Catalog
This Data Manual combines three previous publications: The Analog Switch, LSI
and Telecommunications Data Books.
For Integrated Circuit Cross Referencing and Substitution, see the current issues of
the Siliconix Short Form or OEM Pricing Guides.
NEW PRODUCT DATA SHEETS APPEARING FOR THE FIRST TIME
0169
DF328
DG200A
DG201A
DG202
DG2l2
DG243
DG300A-DG307A
DG381 A-DG390A
DG309
DG5040-DG5045
DG506AI DG507A
DG508A/DG509A
DG528/DG529
Sil525/27B, Si2525/27B, Si3525/27B
Dual Level Shifter Driver
Loop Disconnect Dialer, Push Button Activated
PLUS-40 CMOS Dual SPST Analog Switch
PLUS-40 CMOS Quad SPST Analog Switch
PLUS-40 CMOS Quad SPST Analog Switch
PLUS-40 CMOS Quad SPST Analog Switch
PLUS-40 CMOS Dual SPOT Analog Switch
PLUS-40 CMOS Family of Analog Switches
PLUS-40 CMOS Family of Analog Switches
PLUS-40 CMOS Quad SPST Analog Switch
PLUS-40 CMOS Family of Analog Switches
PLUS-40 CMOS l6-Channel Analog Multiplexer
PLUS-40 CMOS a-Channel Analog Multiplexer
PLUS-40 CMOS a-Channel Latchable Analog Multiplexer
Regulating Pulse Width Modulators
--..
...
~
o
A.
C
"o-....
~
DATA SHEETS NO LONGER INCLUDED
DGMlll
DGMl22
DF331A/DF332A/DF334A
DF341/DF342
LD111/LDl14
LD130
SM310
Dual PMOS SPST Switch-Note 1
Dual PMOS DPST Switch- Note 1
,.-Law Companding CODEC - Note 1
A-Law Companding CODEC-Note 1
3J1.z-Digit Serial Output AID Converter Set- Note 2
3-Digit Integrating AID Converter - Note 2
SMOKE Detector Battery Operated, Piezo Horn Drive - Note 1
Notes: 1. Contact factory on availability.
2. Obsolete product.
Siliconix
0-7
r"-CD
Device Ordering Information
DG
DG
DG
187
303
506
-r-
-r-
A
B
C
P
P
o
a.
/883
J
1
T
::I
CD
Process Option
Package
t
' - - - - - - - - - - - - Operating Temperature Range
::I
...
o
--o...
a
' - - - - - - - - - - - - - - - - Device Number
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
..-..:I
CD
-4
Device Family
::I
DEVICE FAMILY
11, 2 or 3 Letters)
D
DF
DG
DGM
G
-
L
LD
- Linear
- Linear Digital Combinations
PACKAGE
Letter)
11
-....
a..
A- Metal Can
J - Dual In-Line Package-Plastic
K - Dual In-Line Package- CERDIP
Drivers for FET Switches
Digital Function
Analog Switches
Analog Switches
Multi-Channel FETs
::I
L - Flat Package
P - Dual In-Line Package-Side Braze
R - Dual In-Line Package-Side Braze
o
c
"o..._.
Si
- Siliconix Second Source Part
SJM - QPL Listed Part
::I
DEVICE NUMBER
(3 or 4 Digit Numbers)
OPERATING TEMPERATURE RANGE
Letter)
PROCESS OPTION
11
1883 MIL-STD-883, Class B
A - -55 to 125°C
B-
-4 160 Hour Burn-In
BS9000 Series
-20 to 85°C
C - 0 to 70°C
D - -40 to 85°C (Applies to Telecom Products only)
B temperature range parts receive industrial processing unless
a process option dash number is added to the part number.
C and D temperature range parts are given commercial
processing.
All possible combinations of device types, temperature
ranges, package types and MIL-883 process options are not
necessarily available. Consult individual data book pages for
complete information, or sales office.
Siliconix
0·9
.....
II
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~
Process Option Flow Chart
--...oD-
The Process Option Flow Chart shows the standard screening options
provided by Siliconix for Integrated Circuits!
O
I
A.
Column 1:
Denotes the screening process for MIL-883, Class B. To order a part screened to this option, add a "/883"
following the package suffix letter. If Group B or C Quality Conformance is also required, call out as a
separate line item. Parts in this classification are carried in inventory.
Column 2:
Is the screening procedure for military grade standard products ("A" temperature suffix).
Column 3:
Is the normal screening procedure for industrial and commercial grade products (B and C temperature suffixes). An industrial and commercial grade product (B and C temperature range) may be given a 160 hour
burn-in at 125°C by adding a Dash 4 (-4) following the package suffix letter.
0-10
Siliconix
.
"a
o
Process Option Flow Chart
, - -/883 -
--,
I
I
I
I
I
I
MIL·STD·883B
METHOD 5004
Class B
,
STANDARDPRODUCT-'
I
I
I
I
I
I
I
(A Temperature Suffix)
I
I
I
I
I
I
rINDUSTRIALICOMMERCIA~
I
(S-C Temperature Suffix) and
-4 (Burned-In)
I Preseallnspectlon
Method 1010, Condo C
-6SoC to +1S0°C
I
I
I
I
I
I
I
I
I
I
I
[Eie~al-;:;;;-
I,,25°e
Per Data Sheet
L._
-
-IB I
I
I
__.J
fEle~iT;;;t
Da.ta Sheet
I Per
100% at 25 e
-,
G
L=~f:"= 125°e _ _
J
IHI
I
I
I
I
I
I
I
I
fFlI~'e:;'-ca' Te51--1 I
I
IHI
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I
Siliconll( Industrial
Specifications
I
I
I
Temperature Cycle
o
I
Ir-------, II
II
IH
I L _ _ _ ...1 I
I
I
Temperature Cycle
Method 1010, Condo C
-6SoC 10 +150°C
10 Cycles
'"
m
CII
::s
-
"II
I
o
I
I
I
I
I
I
I
I
I
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a
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I
I
.
I
Hermetlclty (Gross leakl
(Non·Plastic Only)
Method 1014. Condo C
o
A.
I
I
I
C
"o--...
::s
I
I
I
100% Per Data Sheet
L-J-_~
i
I
I
~
I
IH II
r;;::--1
Quality Conformance
3
I
I
.-------''------, I
I
I
: I
I
___ J
8
L-.--r----'
I
Electrical Test
Per Data Sheet
~~L
-------'~J
__
.J
3
-Group Band C tests done to customer order on 1883 parts
·"Physlcal DimenSions Excluded
The latest revision of MI L-STD·883 is applicable
Siliconix
0-11
II
--..."
~
eI
m
-
o
JAN 38510 Analog Switches
"Several Siliconix Analog Switches are available fully certified on the QPL (Qualified Parts List) published monthly by
Defense Electronics Supply Center (DESC). The QPL numbers follOW this format J M38510/XXXXX. Refer to the current
Siliconix Price List for available part types and order numbers."
JAN Part Numbering System
II
C
C
...
rl---"-JA-N-'-'c-e-r-ti-fic-a-t-,o-n-M-a-rk--J
o
!I!!.~!!1!97
BEe
lit
10
Lead Finish
A-Solder dip
B- Bright tin plate
C-Gold plate
Military Designator
~
Z
.,C
Detail Specification (Slash Sheet)
1111-DG181 Series
1116-DG300 Series
1123- DG200 Series
Device Type
1111
01-DG181
02-DG182
03-DG184
04-DG185
05-DG187
06-DG188
07-DG190
08-DG191
1116
01-DG300
02-DG301
03-DG302
04-DG303
05-D<>304
06-DG305
07-DG306
08-DG307
1123
03-DG200
04-DG201
Device Class
S-Class S
B-Class B
C-Class C
Order Part Number
Generic Part Number
JM38510111101BCC
SJM181BCC
DG181APIB83
JM38510111101BIC
SJM181BIC
DG181AAl883
JM38510111102BCC
SJM182BCC
DG182API883
Part Number
0-12
-
Case Outline
C-14 Lead side braze
E-16 Lead side braze
1-10 Lead can
JM38510111102BIC
SJM182BIC
DG182AAI883
JM38510111103BEC
SJM184BEC
DG184API883
JM38510111104BEC
SJM185BEC
DG185API883
JM38510111105BCC
SJM187BCC
DG187API883
JM38510111105BIC
SJM187BIC
DG187 AAI883
JM38510111106BCC
SJM18BBCC
DG188APIB83
JM38510111106BIC
SJM1BBBIC
DG188AAI883
JM3B510111107BEC
SJM190BEC
DG190API883
JM38510111108BEC
SJM191BEC
DG191API883
JM38510111601BCC
SJM300BCC
DG300API883
JM38510111601BIC
SJM300BIC
DG300AAl883
JM38510111602BCC
SJM301BCC
DG301API883
JM38510111602BIC
SJM301BIC
DG301AAI883
JM38510111603BCC
SJM302BCC
DG302API883
JM38510111604BCC
SJM303BCC
DG303API883
JM38510111605BCC
SJM304BCC
DG304API883
JM38510111605BIC
SJM304BIC
DG304AAI883
JM38510111606BCC
SJM305BCC
DG305API883
JM38510111606BIC
SJM305BIC
DG305AAI883
JM38510111607BCC
SJM306BCC
DG306API883
JM38510111608BCC
SJM307BCC
DG307API883
JM38510112303BCC
SJM200BCC
DG200API883
JM38510112303BIC
SJM200BIC
DG200AAI883
JM38510112304BEC
SJM201BEC
DG201API883
Siliconix
0'-a... w
3:
_. CD
o:::s VI
....
JM38510/883 Process Option
Flow Chart
Class S
Class B
Visual Inspection
Method 2010
Condition A
Visual Inspection
Method 2010
Condition B
Visual Inspection
Method 2010
Condition B
Stabilization Bake
Stabilization Bake
Method 1008
24 Hours
Method 1008
24 Hours
Stabilization Bake
Method 1008
24 Hours
Temperature Cycle
Method 1010
Temperature Cycle
Method 1010
Constant Acceleration
Method 2001
Condition E
Constant Acceleration
Method 2001
Condition E
Hermeticity Fine
Method 1014
Condition A or B
Hermeticity Fine
Method 1014
Condition A or B
Hermeticity Gross
Method 1014
Condition C
Hermeticity Gross
Method 1014
Condition C
..
_
o
... .......
0
Class C
~
...
.
IA
...
Constant Acceleration
Method 2001
Condition E
...
Hermeticity Fine
.
Method 1014
Condition A or B
Hermeticily Gross
..
Method 1014
Condition C
P.I.N.D
...
...
...
III
-...::s
"'I
o
D.
Method 2020
C
Condition A or B
Electrical Test
Data Sheet
...
Burn In
Method 1015
240 Hours. 125°C
...
Electrical Test
Data Sheet
"o-....
Electrical Test
Data Sheet
::s
...
Burn In
Method 1015
160 Hours, 125°C
Hermeticity Fine
Method 1014
Condition A or B
...
Hermeticily Gross
Method 1014
Condition C
Electrical Test
Data Sheet
Electrical Test
Data Sheet
...
Radiographic
Method 2012
Two Views
..
Quality Conformance
Group A. B, C, and 0
t:
n"
g:::1"'''
0
'"
... m
I
Temperature Cycle
Method 1010
CD
Quality Conformance
Group A, B, C, and 0
Siliconix
Quality Conformance
Group A, B, C, and 0
0·13
BS9000 Approved Analog Switches
Siliconix is the first company to receive BS9000 approval for Analog Switch Devices. The advantages of such approval are:
• A controlled inspection is known to the customer, so reduces the customer's needs
for Goods Inwards Inspection
• A more consistent quality of product
• Easier interchangeability of suppliers
• A product of known quality levels with, in general, a minimal increase in costs
It is the policy of the UK government to encourage the growth of the BS9OO0 scheme for the benefit of both government and
industry. All the Siliconix BS9000-Approved parts are included in the British Ministry of Defence Preferred Range defined in
DEF-STAN 56/36 and as such are first choice components for use in UK defense equipment. Under STANAG 4093 they carry
approved status with other NATO member nations.
Interpretation of Ordering Information
DGXXX
X
-,-
X
T
BS
X
TL.....-_T
__
~
III
-.:...:I
screening Level
BS9000 Approval
Package
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
o
a.
cft
Temperature Range
..._.
' - - - - - - - - - - - - - - - - - - - - - - D e v i c e Number
o
::I
Key
Temperature Range
A
- 55'C to 125'C
B
- 20'C to 85'C
Package
A
L
P, R
Metal Can
Flatpack
Dual·ln·Line
Screening Level
Full Assessment
(Blank)
.S1
Screening Level S1
S2
Screening Level S2
S3
Screening Level S3
S4
Screening Level S4
Siliconix
0-15
....,.
Bs9000 Approved Analog Switches
:.
1
a.
a.
C
i
(Contrd)
DEVICE
PART NUMBER
BS DETAIL SPECIFICATION
DG126
9491-F-0814 to 9491-F-0831
DG129
9491-F-0832 to 9491-F-0849
DG133
9491-F-0850 to 9491-F-0867
DG134
9491-F-0868 to 9491-F-0885
DG139
9491-F-0886 to 9491-F-0903
DG140
9491-F-1030 to 9491-F-1038
DG141
9491-F-1039 to 9491-F-1056
DG142
9491-F-0904 to 9491-F-0921
DG143
9491-F-0922 to 9491-F-0939
DG144
9491-F-0940 to 9491-F-0957
DG145
9491-F-1084 to 9491-F-1092
DG146
9491-F-1093 to 9491-F-1110
DG151
9491-F-1057 to 9491-F-1074
DG152
9491-F-0958 to 9491-F-0975
DG153
9491-F-1075 to 9491-F-1083
DG154
9491-F-0976 to 9491-F-0993
DG161
9491-F-1111 to 9491-F-1128
DG162
9491-F-0994 to 9491-F-1011
DG163
9491-F-1129 to 9491-F-1137
DG164
9491-F-1012 to 9491-F-1029
DG180
9491-F-0688 to 9491-F-0714
DG181
9491-F-0508 to 9491-F-0534
DG182
9491-F-0535 to 9491-F-0561
DG183
9491-F-0733 to 9491-F-0750
DG184
9491-F-0562 to 9491-F-0579
DG185
9491-F-0580 to 949l-F-0597
DG186
949l-F-0751 to 9491-F-0777
DG187
949l-F-0598 to 949l-F-0624
DG188
949l-F-0625 to 949l-F-0651
DG189
949l-F-0715 to 949l-F-0732
DG190
949l-F-0652 to 949l-F-0669
DG191
949l-F-0670 to 949l-F-0687
DG200
9491-F-0778 to 949l-F-0804
DG201
949l-F-0805 to 949l-F-08l3
DG501
949l-F-1138 to 949l-F-1146
DG503
949l-F-1147 to 949l-F-1155
DG506
949l-F-1165 to 949l-F-1l73
DG507
949l-F-1174 to 9491-F-1182
DG508
949l-F-1183 to 949l-F-1l9l
DG509
949l-F-1192 to 9491-F-1200
813705
9491-F-1156 to 9491-F-1l64
Awaiting Approval*
Generic Part No_
DG281 I
IBS
IBS
IBS
IBS
DG3001 IBS
DG3011 IBS
DG3021 IBS
DG3031 IBS
DG3041 IBS
DG3051 IBS
DG3061 IBS
DG3071 IBS
DG381 I IBS
DG3841 IBS
DG3871 IBS
DG3901 IBS
DG2841
DG2871
DG2901
'Contact one of the
Siliconix Sales Offices
for latest information.
Specifications are being raised for additional parts to B89000, which will be qualified during the currency of this
catalogue. For approval status and cORies of the detail specifications for the products approved (or in course of qualification approval) please contact Siliconix Ltd., Morriston, Swansea SA6 6NE. Telephone (0792) 74681, Telex: 48197.
0-16
Siliconix
il
-·0
859000 Series Process Option
Flow Chart
0 0
:s
:!!tr
o ..
~
Cir
::rea
a ..
nUl
.. 0
~i
•-.
:s
~
o
A.
C
_.
ft
~
o
:s
INSPECTION REQUIREMENTS: All tests to be conducted at T8mb = 250C unless othelWlS8 specified. Samples submitted to tests marked '0' shall not be accepted for release under BS9000 lsee 2.6.5 of
BS9000 Part 11.
Flow chart for 100% screening test procedureslsee also Inspection Requirements). Production batches containing greeter than 10% defective units subsequent to Bum-in will not be Issued for relea88.
The following acceptance/rejection criteria apply to the electrical tests after Burn-in for screening levels A, Band D.
lal lots exhibiting greater than 20% defectives shall be rejected.
(bl lots exhibiting less than 10% defectives shall be accepted.
(e) Lots exhibiting between 10% and 20% defectives (inclusive) shall have the defectives removed and the remainder of the lot subjected to an identical Burn-in. If such a lot then exhibits greater than 5%
defectives is shall b. rejected.
Radiographic tasts. Each device shall be examined. for extraneous matter and assembly defects. in the X and V directions.
Siliconix
0-17
H
Silicanix
Interface
III
Index
INTERFACE
DECODERS/DISPLAY DRIVERS
Page
Title
DF412
Decodes Four Digit Multiplexed BCD to LCD Display DriverlDecodes up to 4 digits of multiplexed BCD information and derives the AC signals needed to drive a 4 digit LCD display.
Any digit can be blanked as required.
1-1
LEVEL SHIFTERS
Channels
Input Load
Output Drive
tON/tOFF
0123
6
1 mA/l,..A
1.0 V/O.4 V
ON - 5 rnA Sink. OFF - Block 30 V
500/1500 ns
1-8
0125
6
-0.7 mAl + 1 ,..A
ON - 5 rnA Sink. OFF - Block 30 V
5OO/15OOns
1-10
0129
4
- 0.2 mAl + .25,..A
OV/5V
ON -10 rnA Sink. OFF - Block 50 V
3001 1500ns
1-12
0139
2
-500 ,..AI + 10,..A
30 V p-p @ 10 rnA
170/200 ns
1-14
33 V p-p @ 40 rnA
70-110 ns
1-20
o V/4.6 V
OV/+5V
0169
2
-loo,..AI +5,..A
OV/+3V
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) to devices without resulting in
permanent damage. This is a stress rating only and not subject to production testing. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.
Four Digit LCD Decoder Driver
designed for . . .
H
Siliconix
BENEFITS
• Driving Liquid Crystal Displays
Directly
•
•
Reduces Complexity of Driving LCD Displays
Blanking of any Digit with Input Code of
1111
• Only 1 Package Required to Drive Up to a
4 Digit Display
• Minimal Power Consumption
o Typically 1.5 mW
o Operates over 3.5 to 6.0 V supply
• Interfaces Readily with Most Logic Families
•
•
•
•
DESCRIPTION
No External Oscillator Required
No Display Buffering Required
Easy Multiple Driver Interfacing
Eliminates DC Bias Levels That Degrade
Display Lifetime
The DF412 Four Digit LCD Decoder Driver is a CMOS Monolithic device employing multiplexed BCD to LCD Decoding.
A single DF412 contains all of the circuitry needed to decode up to 4 digits of multiplexed BCD information and derive the
AC signals needed to directly drive a 4 digit LCD display. Included is the decoding of BCD input 1111 to blank a digit.
An internal oscillator, its frequency being controlled by an external capacitor, develops a backplane (BP) signal that
is a square wave swinging between ground (VSS) and the positive supply (VDD). Segment drivers supply square waves of
the same frequency as the backplane but either in phase for an OFF segment or out of phase for an ON segment. In this
manner of LCD digit driving the net DC potential applied between segment and backplane is zero, a necessary requirement
for long display life. Digital input levels are defined as input voltages> 4 V being a logic "1" and input voltages < 0.8 V
being a logic "0" with VDD = 5 V.
BCD input data is decoded into 7 segment form using an on board ROM. The 7 segment data is then latched into the
appropriate static latches via the digit strobe inputs and control logic.
The pinout of the DF412 allows easy PC board interfaces to Dual·ln-Line LCDs as well as edge connecting types of displays.
l1li
-..
::::I
CD
.f
ft
CD
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Dual-In-Line Package
B3
B2
B,
BO
(MSB)
BCDT07
SEGMENT ROM
(LSB)
Voo COMMON TO SUBSTRATE
RESET
FCLK
L-~O:OC~Jr____-1~~'L._~~5:'2~~------~-f>----oBP
Siliconix
I
ORDER NUMBER DF412CJ
SEE PACKAGE 22
I:
1-1
ABSOLUTE MAXIMUM RATINGS
-0.3 V to 8 V
VDD -vss ....................
Voltage on Any Pin . . . . . . .
VSS-0.3V toV DD +0.3V
Current at Any Pin ..... . . . ....... . . . . . . 10mA
Operating Temperature . . . . . . . . . . . . . . . . . . . 0 to 70°C
.
.
.
.
Storage Temperature . . . . . . . . . . . . . . . . . • . -65 to 125°C
Power Dissipation (Package)" . • . • . . . . . . . . . . . . . 450 mW
"Device mounted with all leads welded or soldered to PC board .
Derate 6.3 mW/oC above 25°C .
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample tested for AC parameters to assure conformance with specifications.
Limits
Characteristic
Unit
Min
1
.2
,3
---'4
,-
I
N
p
U
T
S
~
6
--+
8
9
---:ro
- 11
12
- 13
liN (Digits)
Digital Inputs
Leakage Currents
liN (FCLK)
Oscillator Input
Current
VINL
Digital Inputs
Logic Low Voltage
VINH
Digital Inputs
Logic High Voltage
VOL (Segments)
Segment Output
Voltage in "0" State
U
T
S
14
15
0.01
Max
1
j.tA
0
U
T
p
Typ1
350
-350
BCD and DS Inputs
Clock Input
4.0
4.5
BCD and DS Inputs
Clock Input
0.3
0.03
VOH (Segments)
Segment Output
Voltage in "1" State
VOL (Backplane)
Backplane Output
Voltage in "0" State
VOH (Backplane)
Backplane Output
Voltage in "1" State
tr (Segments)
Segment Output
Rise Time
1.0
tf (Segments)
Segment Output
Fall Time
1.0
tr (Backplane)
Backplane Output
Rise Time
0.8
tf (Backplane)
Backplane Output
Fall Time
0.8
Min
LCD
30
0.7
V
4.7
4.97
0.3
0.03
4.3
0.7
InL = 5 mA
IOL - 0.5 mA
4.7
4.97
IOH =-5 mA
IOH --0.5 mA
CLOAD = 200 pF
16
17
18
1-
D
V
N
A
M
I
C
19
FBP1
120
FBP2
21
IDD (Digital Inputs Static)
I- S
22
U
Backplane
Frequency
j.ts
CLOAD = 3900 pF
COSC = 3800 pF
Hz
Max
LCD
100
Supply Current
140
COSC = 1000 pF
400
See Figure 2
j.tA
IDD (Digital Inputs Dynamic)
Supply Current
VDD Range
Operating Supply
Voltage Note 2
1- P
23
IOL = 250j.tA
IOL = 25j.tA
IOH =-250j.tA
IOH - 25j.tA
~
-
VIN = 5 V
VIN - 0 V
0.8
0.5
4.3
Test Conditions
VOO = 5 V. TA = 25°C
Vss = 0 V. COSC = 200 pF
155
3.5
5
See Figure 3
6
V
NOTES:
1.
Typical values are for Design Aid Only. and are not guaranteed nor subject to production testing.
Operation over the supply voltage range is functionally tested. DC and AC parametric testing is performed only at specified test
2.
conditions.
1-2
Siliconix
TRUTH TABLE
83 82 81
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
1
1
1
1
1
1
1
a a a
a a 1
a 1 a
a 1 1
1 a a
1
1
1
1
1
0
1
1
DIGIT
DISPLAY CHARACTER
80
a
a
a
a
a
a
a
a
TIMING WAVEFORMS AND DEFINITIONS
STROBE INPUT
II
L1
I
I
BCO
,?
DATA INPUT
~~~-
~ 3.50
.,z
w_
220
aG
210
~S
3D
"'<
.,-
10
" 3.25
~a:
o
>
".,
9o
~ 2.75
.
2.50
~
2.25
l:
I-
;l
~
.!;
I
I
2: 200
~
~.~
V~D 6'V
=
CL (SEGMENTS) '" 200 pF
CL (BACKPLANE) '" 3900 pF
., 1\
I---+--+-+-+---+.
w
100
~~
Supply Current Vs.
Temperature
Input Threshold Vs.
Positive Supply Voltage
190
~ 180
"en
" i'--
170
........ ~
E 160
l:
t
",
..........
150
10
Voo POSITIVE SUPPLY VOLlAGE (VOLlSI
Cose OSCILLATOR CAPACITOR (pF)
20
30
40
50
T TEMPERATURE
60
70
t C)
(rOGROUND)
Figure 4
Figure 5
Figure 6
TYPICAL WAVEFORMS
I
512
I
512
I
-M.fUlJl.f4~JUlllfU1JlJUl
OSCIL~~~~~
V
BACKPLANE
II
D O - r 256 CLOCK ,
,/ '"
\I
..... /'
I _ _ _ _ __
;..'
I.
256 CLOCK }
I.
~ CYCLES , - - CYCLES =:j
VSS~-~~~-~~~====~~----~~~~~~~-------
J
VDO- , - - - - - - - ,
OFF
SEGMENT VSS,,!.--------.!======"--------'"======L----ON VDDl
SEGMENT V~ b:=====L-_ _ _ _ _~=====~_ _ _ _ _~=====~
Figure 7
DIGIT STROBE INPUT STAGE
OSC
(PIN 36)
1ST
2ND
NEG CLOCK
eDGE
NEG CLOCK
EOGe
CLOCK
--tcp
Q
SINGLE
PULSE
ONE
SHOT
DIGIT
STROBE _ _ _ _ _ _..J
CLOCK
DATA LOAD
~ROBE~2
__________
~1
DATA
LOAD
TURNS ON DECODING
ROM AND ENABLES
LOADING OF SEGMENT
LATCHES
Digit Strobe and Clock Timing
Relationships to Data Loading
Figure 8b
Digit Strobe Input Circuit
Figure 8a
1-4
Siliconix
TURNS OFF
DECODING ROM
ANO LATCHES
DATA AT SEGMENT
OUTPUT LATCH
PIN DESCRIPTIONS
Oscillator - A capacitor connected between the oscillator
pin and ground completes the integral clock generator. The
frequency of the clock generator (fOSC) is determined by
the capacitance value and the VOO voltage, as seen in
Figure 4. For driving LCOs with a 30 Hz to 100 Hz back·
plane frequency range, the typical oscillator capacitor is
1000 pF to 3800 pF (for VOO = 5 V). The oscillator pin
can also be driven with an external clock whose output
swings within 10% of VOO and VSS. This is useful when syn·
chronization of more than one 0 F412 is necessary, such as
when driving displays of more than 4 digits on a single
backplane.
Backplane - The backplane of the liquid crystal display is
driven by this pin whose output is a squarewave swinging
between VOO and VSS. The frequency of the backplane
signal is fOSC/512. Most LCOs require backplane fre·
quencies of between 30 Hz and 100 Hz. See Figure 4 for a
graph of oscillator capacitance vs backplane frequency.
edge, the segment outputs are latched, storing the 7-segment
information for this digit. This input structure is the basis
for the timing requirements of the OF412, shown in
Figure 1.
The digit strobe input structure can actually load more than
one digit at a time from the same BCD input. The loading
of multiple digits can save time for microprocessor applications, such as for zeros, or blanks. However, all four digits
cannot be simultaneously loaded due to a special decode of
01 • 02 . 03 • 04 which causes a reset of the backplane
divider and inhibits loading of the BCD data. Unused ~igit
Strobes should be tied to ground, to avoid them floating to
a logic 1 condition which could cause an inadvertent reset
condition. The reset condition stops the backplane square
wave, putting the OF412 drive in a steady voltage state
which would degrade the LCD for long term application.
Digit Strobes 0,-04 and BCD Inputs B3, B2' B, and BOMultiplexed BCD information is entered into the OF412 by
presenting the appropriate BCD code to the inputs B3, B2,
Bl and BO and by pulsing the appropriate digit strobe input
01, 02, 03 or 04 with positive true logic (i.e., VINH;;;'
[0.8 x Vool for logic 1, VINL ~ 0.8 V for logic 0). The
minimum pulse width of a digit strobe should be not less
than one period of the oscillator frequency. Information
presented at the BCD inputs (B3, B2, Bl, BO) must be valid
during the digit strobe pUlse. See the timing requirements
in Figure 1.
When ganging more than one OF412 together, it is necessary
to synchronize the individual backplane signals to insure
proper segment-backplane signal phase relationships. This is
easily accomplished by initially pulling all digit strobe
inputs high and by then driving the ganged OF412s with a
common oscillator. By comparing the individual backplane
signals of two OF412s with an exclusive or gate (see Figure
10) a continual checking of the backplane phase relationships can be accomplished. Should, for some reason, the
individual backplane signals become out of phase an automatic reset will occur and proper phase once again will be
establ ished.
The digit strobe inputs are shaped by the input logic shown
in Figure Ba. This logic causes a strobe signal which is a
single clock period wide. The active time of this data load
strobe (shown in Figure Bb) enables the BCD to 7-segment
decoding ROM, which brings the new 7-segment data to the
output latches. Delay time for data to get from BCD input
to the segment outputs is typically 2 tls-3 tiS. The end of
the data load strobe is triggered by the second negative
clock edge following the digit strobe going high. At this
Segment Outputs - Segments are driven with the 0 F412
segment outputs which generate square waves whic;:h are
either in phase with the backplane for an OFF segment
or out of phase with the backplane for an ON segment.
Output swings of the drivers are between VOO and VSS.
Segment peak to peak voltages are then 2X (VOO-VSS).
The CMOS output drivers provide matched resistance to
both VOO and ground, eliminating any net DC voltage
component on the LCD to give maximized display life.
Siliconix
1-5
III
-..
:I
CD
t
ft
CD
APPLICATIONS
8 DIGIT DISPLAYS- HAMLIN 3918 LXD 65DXX9
I-I
CI
08
I-I
1=1
B
B
B
B
B
:fJ
0,
Os
03
06
D2Ll
----J
DATA
BITS
r
B3
B,
B2
B,
BO
BO
82
l
I rr=-
13-g3
84-94
,.--B2
_B,
H
DF412
r-
8,-111
H
DF412
Bo
02 0, BP
OSC04 Da
°2°, BP
pi5-
y~
~~Pf~
08
~I
74C32
R,
20Kfl
R2
100Kfl
,
82-92
83-93
B3
VDD
THR EE INVERTER OSCILLATOR
~
--=;l
8,-91
esc 04 03
D
l...-
82-92
14-94
(MSBI
I-I
CI
(MSD)
0.,
=ql~t~~
R~
06
Os
DIGIT
STROBES
0,
03
02
0,
Ganged DF412's Drive 8 Digit LCD
Figure 9
881T
DATA
rJ!!!!.
I-I--
I-I-I-I-I--
8·BIT ~-PROC
-- }~D
'. --
}'"~ {PORT
82 92
INPUTS
'4-04
B81T
PORT
INPUTS
BACKPLANE
H
I I I
BP
OF412
8255
PROGRAMMABLE
PERIPHERAL
INTERfACE
A,
LCD DISPLAY
STROBE
8080 FAMILY
cs An
U
} DIGIT
I-I
1=1
83-93
I
SC
?N
Cose
~
BEI B
if
8,-91
"The DF412 Allows Simple Interface to the LCD Display
from an 8080 Microprocessor. Data Transfer is Made with
an 8 Bit Dump, Bringing Both the BCD Input and the Digit
Strobes to the Chip in Parallel
Figure 10
1-6
i
Siliconix
CONTINUE
APPLICATIONS (Cont'd)
BACKPLANE
LXO 450XX03
HAMLIN 3909
SEGMENTS
FOR DIGIT 5
+5V
H
Vee
BP
OF412
Vss
OSC
BO(LSBJ
SIGN/OR/UR
+5V
!-__.......--\eLK
H
GND
L0121A
VOD
-=
-12V
+12V
INPUT +
o------! V,N
VOLTAGE
.. .,.
HI QGNO
::>
:t0:
N
::>
!!!
v+
H
LD120
t=
~
'"
CR130
VREF
-'
0
~
11:
~
N
N
e-
+12V
~V-
-12V
'" '" '"
6.7 V
~eSTRG
Figure 11
r- l'.alT
rrr-r--
INPUT
PORT
4·a1T {
OUTPUT
PORT
SELECT
8·BIT /A·PROC
8048 FAMILY
4·BIT {
OUTPUT
PORT
OR
-
--
--
a2-92
}aeo
INPUTS
U
14--94
LCD OISPLAV
} DIGIT
STROBE
INPUTS
BACKPLANE
ap
H
(4-BIT p·PROC)
OF412
I-I I-I CI I-I
1=1 1=1 I_I 1=1
8243
I/O EXPANDER
a3-93
l o sINe
J
O--T--OOUT,
IN10
INs
13
3
OUT2
IN2
IN6
Vl
TOP VIEW
IN3
ORDER NUMBER:
D125AL
SEE PACKAGE 5
12
•
OUT3
11
5
OUT4
IN.
10
6
OUTS
INS
7
OUTS
IN6
1
V-
V-
D125AP OR D125BP
SEE PACKAGE 11
TYPICAL CHARACTERISTICS
Supply Current vs
Temperature
Propagation vs
Temperature
800
600
'00
V+: lOV
V-=-20V
10= 2.5mA
CO'" 35pF
tOFF,VL-5~
VL=5V
-- ++8 V
l--r J..I
I
V-=-20V
2.0
ONE DRIVER.fN
Il_
1.5
~
1.0
tON,VL =5V
200
I
0.5
I
tON,vL = 2.8 V
o
o
-25
25
50
75
-55 -35 ·15
100
TEMPERATURE 1°C)
1-10
5
25 45
65
85 105 125
TEMPERATURE fOCI
Siliconix
ABSOLUTE MAXIMUM RATINGS
Vo to V-. . . . . . . . . ................ .. . 36 V
VL to V- ..... ... . ...................
30V
VIN to V- . . . . . . . . . . . . . . . . . . . . . . .....
30V
VIN to VL . . . . . . . . . . . . . . . . . . . . . . .....
±6 V
Current (Any Terminal) ............. .... . 30mA
Storage Temperature ............... -65 to 150°C
Operating Temperature (A Suffix) . . . . . . . -55 to 125°C
(8 Suffix) . . . . . . . . -20 to 85°C
Power Dissipation *
Flat Package** . .....................
14 Pin DIP***
750mW
825mW
* All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mWfC above 75°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
Output Voltage,
10 VOL
I-u
2T 10H
Low
-Ssoc
012SA
2Soc
12SoC
_20°C
012S8
2Soc
8SoC
-19.6
-19.6
-19.S
-19.6
-19.6
-19.S
0.1
0.1
10
0.1
0.1
10
Output Current,
High
Input Current,
Input Voltage High
3
"NH
I-I
4N "NL
Input Current.
Input Voltage Low
ST
I - I ton
6M toff
±1
±10
±10
±10
±20
-0.7
-0.7
-0.7
-1
-1
-1
O.S
1.2
Turn-ON Time
E
-2.S
2.5
-2
1
Negative Supply Current
Logic Supply Current
Negative SuppiV Current
11o~ 'L
Logic Supply Current
-2.S
2.S
-2
1
V
TEST CONDITIONS. UNLESS NOTED:
V- = -20 V, VL = S V
10 = S rnA. VL = 4.S V. V,N = 0.5 V
Vo = 10 V. V,N = 4.6 V
"A
±1
Turn-OFF Time
7 S 1I-u
8 P IL
19 P 1-
UNIT
0.5
I.S
-2.S
2.5
-200
100
-2.S
2.S
-2
2
-2.S
2.5
-2
2
-2.S
2.5
-100
100
V'N=4.6V
III
rnA
V,N =0
"'
See Switching Time Test Circuit
mA
10= 0
"A
Vo = 10 V All V,N =4.6V
-...
::a
..f
CD
V,Nl =0,
All Other V,N = 4.6 V
'"CD
IBAF·B
SWITCHING TIME TEST CIRCUIT
V'N
t r < 100ns
tf <10ons
J
o
~
.
J'24V
VOUT
1'-(90%1
7V
-2DV-
~..
VL
J
5V
l-10V
Jc
tOFF
VL
2.4V
lOUT
2 rnA
VOUT
W'-
±",:-
-tON
Siliconix
leouT
-20V
v-
1
35
.'
-=-
1·11
4-Channel MOS FEY Switch
Driver with Decode
designed for . • •
.H
Siliconix
BENEFITS
• Interfacing Low Level Signals to
FET Switches such as G 115 and
G 123 Series Multi-Channel FET
Switches
•
Reduces System Component Requirements
o Four Interface Circuits in One Chip
•
Easily Interfaced
o Inputs Compatible with Low Power TTL
and DTL IF = 200tLA Max
o Output Current Sinking Capability' 0 mA
DESCRIPTION
The D129 is a four·channel driver designed to provide the DC level·shifting and amplification functions needed to interface
low-level logic outputs (0.7 to 2.2 V) and field·effect transistor switch inputs (up to 50 V peak·to·peak). With an input logic
supply of 5 V, the output transistor emitter, V-, may be set at any voltage between -5 and -30 V. In the ON state, the
output collector wiJI sink up to '0 mA of current, and in the OFF state will hold off voltages up to 50 V above V-. Each of
the four drivers has a 3·input logic gate, with each of the inputs either open or at positive logic ",", the driver will be ON.
With any of the inputs either grounded or at positive logic "0", the driver will be OFF. Some of the logic inputs to the
four gates are internally connected to facilitate decoding from a binary counter; however, one input to each gate provides
a means for independent operation of each driver, if desired.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAM
Flat Package
,.
IN,
vl
IN2
OUT,
IN3
OUT2
IN.
OUT 3
INS
OUT 4
IN.
V-"
IN7c:~~~:r-"'C=~=~
7
8
TOPVIEW
INPUTS
ORDER NUMBER: D129AL
SEE PACKAGE 5
·Common to Substrate and Base of Package
L--_-ov_
Dual·ln·Line Package
ORDER NUMBERS: Dl29AP OR D129BP
SEE PACKAGE 11
1-12
Siliconix
ABSOLUTE MAXIMUM RATINGS
Vo
Vo
VR
VR
to
to
to
to
VVVV-
(A Suffix)
(B Suffix)
(A Suffix)
(A Suffix)
Operating Temperature (A Suffix)
( B Suffix)
Power D issi pation *
Flat Package**
14 Pin DIP***
50V
36V
33V
24 V
8V
±6V
6V
30mA
-65 to 150°C
VL to VR
VIN to VR .
VIN to VIN (Any Other VIN Terminals)
Current (Any Terminal)
Storage Temperature
. -55 to 125°C
-20 to 85°C
750mW
825mW
* All leads soldered or welded to PC board.
**Derate 10 mWfC above 75°C
***Derate 11 mWfC above 75°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
D129A
_55°C
3
8SoC
125°C
_20°C
25°C
-19.25
-19.25
-19
VOL
Output Voltage, Low
-19.3
-19.3
-19
2U VOL
T 10H
Output Voltage, Low
-19.8
-19.8
-19.75
Output Current, High
0.1
0.1
20
0.2
0.2
10
0.25
0.25
5
1
1.0
5
~o
Input Current,
Input Voltage High
4
"NH*
-I
5 N "NL*
10=10mA
V
-250
Input Voltage Low
-200
-250
-160
-225
VO' 10 V, V,N = 0.7 V
VIN - 5 V Input Under Test,
VIN ;; 0 All Other Inputs
-200
V,N = 0, VL = 5.5 V
Turn·ON Time
0.3
0.3
Turn·OFF Time
1.5
1.5
8 S 1gU
'L
1-
Negative Supply Current
-2
-2.25
1o~
3
3.3
Negative Supply Current
-10
-25
~A
l i L IL
y
Logic Supply Current
0.75
1
mA
7
Logic Supply Current
See Switching Time Test Circuit
#s
V-=-20V,
VL = 5.5 V
~
0:
0:
"...
~
~
I
80 ......... 1
2~
ffi
40
20
:
2
"'"\ \
-~ \
CD
0
;.
I-:-
I-LJ
2
3
V 1N -INPUT VOLTAGE (VOLTS)
I
'400
0
~
1000
~
800
.."
;::
....... ...
-
i-- -
m
-
I---
l1200
;::
T":- -
10
-60-40 -20
=5l
r--. ....... ~nl
-
"CD
Propagation
vs Temperature
V-=-30V _
V R =0
..... .......
,
'I
\
I , \ \. \
0
v~
V L =5V
V-=-20V
V R =0
-5~~
'00
60
3
I
."-J
<.>
::s
All Channels "OFF"
Current
vs Temperature
liN vs VIN
-"
.-
All V,N = 0,
IBAD·A
TYPICAL CHARACTERISTICS
"...
l1li
One Channel "ON"
mA
·Per gate input
'20
V,N =2.2 V, VL =4.5 V
10= 1 mA
~A
~A
Input Current,
T
6 I ton
M tof1
E
TEST CONDITIONS, UNLESS NOTED:
V- = -20 V. VR = O. VL = 5 V
UNIT
01298
25°C
-
'off
1--" ......
i"'"
600
is
if
-
r- r- -
~,.....
400
200
0
-60 -40 -20 0
20 40 60 80 100 120 140
20 40 60 80 100 120 140
T - TEMPERATURE (OCI
T - TEMPERATURE (OCI
SWITCHING TIME AND TEST CIRCUIT
+10V
Wf:5V
-~
If < lOOns
tf
IN
- :::::I
iV
....to..
b
V-=-20V
R
r
< lOOns
1 ~s
f= lOOK Hz
tpw =
3K
IN
.,::={
l'off
to~
OUT
+10V
OUT
-2:
Siliconix
~
\.
17
vJl.
90%
+7 V
90%
1-13
Monolithic 2-Channel FEY
Switch Driver
designed for. • •
H
Siliconix
BENEFITS
•
• Interfacing Low Level Signals to
FET Switches
Easily Interfaced
o TTL, DTL and RTL Compatible
• Minimizes Switching Time
o 150 ns Typical Propagation Time
• Interfacing TTL to CMOS
• Interface from TTL to Other Logic
Levels, i.e. PROM Program Levels
• Versatile
o Complementary Outputs
o Up to 30 V Output Swing
DESCRIPTION
The D139 is a dual low level to high level voltage translator with complementary outputs. Uses include bipolar to MOS logic
interface and bipolar logic to F ET analog switch control.
The following characteristics of the input circuit provide an ideal interface to the common logic forms TTL, CMOS, and
DTL: light loading ("" 1/3 TTL load) to "0" inputs, a 1.2 V trip point, and high input impedance with high breakdown to
"1" inputs.
The output can drive up to 30 V peak-to-peak into pure capacitive loads or moderate resistive loads. Current source coupling
between the input and output and split power supplies allow wide flexibility in the actual output voltage levels. Complementary outputs permit maximum application versatility, allowing functions such as double-throw analog switch control.
A positive logic "1" at the input provides a "1" at OUT and a "0" at OUT.
SCHEMATIC DIAGRAM (Typical Channel)
PIN CONFIGURATIONS
Metal Can Package
v+
Rl
OUT2
D1
06
D2
R2
TOP VIEW
·COMMON TO SUBSTRATE AND CASE
D3
'--.....----+--0 OUT
D4
ORDER NUMBERS
D139AA or D139BA
SEE PACKAGE 2
Dual-In-Line Package
R6
'---+-oOiiT
Logic
OUT
OUT
0
vv+
v+
v-
1
1·14
Siliconix
ORDER NUMBERS D139AP
OR D139BP
SEE PACKAGE 11
ORDER NUMBER D139CJ
SEE PACKAGE 7
...w
a
ABSOLUTE MAXIMUM RATINGS
V+to VV+ to VR
V+ to Vo
Storage Temperature
(A & 8 Suffix)
(C Suffix)
Power Dissipation (L Package)'
(P Package)'
(J Package)'
Thermal Resistance (0 JA, J Package)
36 V
36V
36V
8V
8V
36 V
36 V
36 V
8V
12 rnA
100mA
VL to VR
VIN to VR .
VR to VVL to VVo to VVL to VIN
Current (Any Terminal) DC
Peak (Any Terminal)
(200 J.LS pulse width, 100 pps)
Operating Temperature
(A Suffix)
(8 Suffix)
(C Suffix)
-65 to 150°C
-65 to 125°C
750mW
825mW
470mW
0.16°C/mW
•
• All leads soldered or welded to PC board.
Derate L package 10 mWfC above 75°C
Derate P package 11 mWfC above 75°C
Derate J package 6.5 mWfC above 25°C
. -55 to 125°C
-20 to 85°C
o to 70°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
0139BA/BP (0139CJI
0139AA/AP
CHARACTERISTIC
(MINI/MAX LIMITS
_55°C
-
1
VOHIVOH
2
25°C
125°C
(MINI/MAX LIMITS
_20°C
85°C
25°C
10°CI
170°CI
TEST CONDITIONS,
UNLESS NOTED:
V+ = 10 V, VL = 5 v,
V- = -20 V, VR = 0
UNIT
Output Voltage, High
1.1
0.9
0.7
1.1
0.9
0.7
lOUT = -10 #A
(V+ 10 VOl
1.5
1.5
1.5
1.5
1.5
1.5
lOUT
VIH=2Vfor
=--2 mA
V
-
3
VOLIVOL
4
5
Output Voltage, Low
1.3
1.1
0.9
1.3
1.1
0.9
IOUT=10#A
IVOloV-1
1.5
1.5
1.5
1.5
1.5
1.5
lOUT = 2 mA
10
20
10
20
VIN
=5 V
VIN
=0
Input Current, Input
IINH
Voltage High
VOHIV61,
VIL = O.BV for
VOHIVOL
6
IINL
7
1(+1
Voltage Low
Switching Time, Low to
High, Delay Plus Rise Time
(-6001
(-5001
(-5001
1-6001
170
(-5001
1-5001
B
1(-1
Low, Delay Plus Fall Time
200
CD
1+
Positive Supply Current
0.1
0.1
10
IL
Logic Supply Current
4.0
4.0
11
1-
Negative Supply Current
See Switching Time Test Circuit
(CL = 35 pFI
200
9
Input Voltage High
or
Input Voltage Law
-3.0
-3.0
H.61
(-1.61
VIN1 =VIN2=5V
(-1.11
(-1.11
VINI
mA
Reference Supply Current
12
IRH
13
IRL
Input Voltage High
Reference Supply Current,
Input Voltage Low
= VIN2 =OV
CMOA
Siliconix
CD
ir
170
ns
Switching Time, High to
:I
ft
#A
Input Current. Input
-..-
1-15
...
0-
f'»
TYPICAL CHARACTERISTICS
Q
Logic Input Current vs
Logic Input Voltage
Output "Low" Characteristic
-100
V L =5V
VR=OV- .
!
as
-80
a''"" -60
I-
~
Z
U -40
§
~-20
-"" '\
-5SOC
J+=lov l v-= tOr-
2.4
'0
~7
2.2
;.. ~
2.0
~~:~v
::>1-
5£ 1.8
r--..... 25°C \
1\
o
-
~
I
I
1.6
_,I ~
>:& 1.4
~F
~~
1.2
G~
1.0
ZSoC
f-'"" ....-: I- H
f-'""
~ 0.8
g
0.6
r- t--
r- I-.....
~
J
-IH- AND -IL-
·1 I I
~0
10
f::o-
-15
25
45
65
85 105 125
-30
-20
Switching Time, High to
Low, vs Load Capacitance
see
,/
,/
lDO
!
'"i=:E
V"
./
V"
";:
Z
~ 200
~,
k"
100
V
~
,/
~,
,/
o
r- ANDTEST
CONDITIONS
DEFINITIONS
-2
I
V
200
V
V
........
300
400
500
100
CL - lOAD CAPACITANCE IpF)
V
'" "
-f-
r-
V
200
300
-8
w
"
""
;:
""..
J!
200
~
~,
1.
'100
"
'd-
400
500
C L - LOAO CAPACITANCE (pFl
-55 -35 -15
5
25
45
65
Switching Time Test Circuit
LOGIC INPUT
t r < 20 ns
tf< 20 ns
'---+-+.....-0 VOUT
lOGIC
INPUT
Siliconix
85 105 125
T - TEMPERATURE ( CI
TEST CONDITIONS AND DEFINITIONS
1-16
-10
SEE TEST CONDITIO'NS
ANO DEFINITIONS
]
;::
""..
I--'"
-6
-4
CL = 35 pF
V'-
300
~
::H'"
0.6
Switching Time vs Temperature
./
100
200
~
0.8
>""
300
400
l1
'd+
100
1.0
~EE
TEST CONDITIONS
AND DEFINITIONS
f-::::
~
-~ :::::+::::
.", 12SoC
25"C ___
-10
Switching Time, Low to
High, vs Load Capa ci ta nce
500
o
V
v- (VOLTS)
400
o
/
-20
5
/
T - TEMPERATURE (OC)
500
'"
V
-10
o
REGION
V
-
...55°C
1.2
The output swings between V+ and
V- (VOH ~ V+ and VOL ~ V-).
Select V+ and V-, within the operating region of curve at left, to provide the desired output swing. Note
that V- can be -2.0 V to -30 V
and V+ - V- must be at least 10 V.
i..{PERATING
/
-5
-'RL
!
'"i=
1/
,.
?!
'r+A~D -I'L+ .........
-55 -35 -15
1.6
I.'
Selecting V+ and V-
V
15
I
I
IOH - OUTPUT "HIGH" CURRENT ImAI
/
20
r-
'RH
v~cJv
ZS
r-:- ::::
0
>
i
1.8
Selecting V+ and V-
V+-l0V,VL=5V
VR=O,V-=-20V
VL-5V
V --20V-
2.0
'OL - OUTPUT "LOW" CURRENT (mA)
30
I
?=~
+ "
I
VR=O
,,+
1-1::>11-",
~"
''''
''''
~~
125°C
v~clo)-
2.4
0
10
Supply Current vs Temperature
r-
~
2.6
~2: 2.2
s~
o
V 1N - LOGIC INPUT VOLTAGE (VOL lSI
Output "H igh" Characteristic
"ij!:
~i
-55"C
0",
1"\
ll\c
T
~
2.6
...a
DRIVING PMOS ANALOG SWITCHES
•w
DPDT PMOS
Sl
13
S2
12
S3
11
S4
10
01
14
OUT 1
OUT 1
ANALOG IN/COUT)
0139
12
OUr2
11
OUT2
vA"'" FROM CONTROL CONNECTS 52 TO 01 AND S3 TO 02.
VAN RANGE" +10 V TO -lOV
9 }
ANALOG OUT/IIN)
02
G123
PMOS Interface Circuit
Figure 1
Driving PMOS Analog Switches. The D139 output swing is dictated by the analog signal range. VOH is the PMOS "OFF"
level and must equal the most positive analog voltage. VOL is the PMOS "ON" level and must be 10 V more negative than
the most negative analog v.oltage. Therefore for VAN = ±10 V -+ V+ = +10 V and V- = -20 V. PMOS control is make· beforebreak.
l1li
-.
::I
CD
....
~
aft
PMOS LOGIC INTERFACE
CD
-20V
Figure 2
Siliconix
1-17
=
..
DRIVING NJFET ANALOG SWITCHES
ell
Fast Dual SPST, NJFET, for
Low Frequency Signals (1)
Dual SPST, NJFET for High
Frequency Signals (1)
CONTROL
CONTROL
50K
OUT 1
lN961
OUT 1
o
0139
12
OUT2
11
lN961
OUT 2
50K
THE 2N4393WILL BE "ON" FOR A "'" FROM CONTROL.
VAN RANGE'" +10 V TO -10 V.
THE 2N4393 WILL BE "ON" FOR A "'" FROM CONTROL.
VAN RANGE = +10 V TO -10 V.
Figure 3'
Driving NJFET Analog Switches. VOH is the "ON" NJFET level and must be isolated from the gate by a series diode as shown
above to prevent forward gate current. VOL is the "OFF" NJFET level and must be more negative than the most negative
analog signal voltage by (iVGS(off)i +2 V). NJFET control is break·before·make.
(1) See Siliconix Application Note "Driver Circuits for the J·FET Analog Switch" AN73·5, August 1973.
APPLICATIONS
IN914
+5V
IN914
+15V
IN914
IN914
V+
+--......-0--1 v+
3621
-s.OV
(INTEL)
+15V
O,I-~+++..J
02~-4-~~--J
1.2K
03~--~~--~+a~~o---I-~
04~---""
+15V
"'c, IS USED TO SLOW THE RISE TIME TO -400 ns
0139 Used in Programming the Intel 3621 PROM
Figure 4
1-18
Siliconix
+5V
APPLICATIONS (Cont'd)
+5V
+1SV
0139 Used in Programming the Intel 3601 PROM
Figure 5
+12V
'5V
l1li
-...
'5 V
::I
.
CD
'---i-............---._--1PROGRAM cs/WEI-t----i---'
~
ft
CD
(lNTELI
2708
-5V
-5V
O.SV
TTL
ADDRESS
LOGIC
O.5V
DATA BUS
DATA BUS
+5V+12V-5V OV
TTL
DATA
LOGIC
*C, USED IN OBTAINING THE PROPER RISE AND FALL TIMES
··Rl USED IN LIMITING CURRENT INTO 0139
0139 Used in Programming the Intel 270B PROM
Figure 6
0139 2·Channel Interface. The D139 may be used to interface 0.5 V TTL to CMOS Logic by setting VL. VR. V+ and
V- to the proper levels. If 0 to 5 V TTL levels are to be used to control the switch. VL should be set to 5 V and VR
grounded.
V+ and V- may be set to whatever levels are needed. The operating region of the D139 is determined by the graph of V+ vs
V-.
Note. V- must be at least 2 V below VA in order for the D139 to operate. See the V+ vs V- graph for selecting the supply voltages within
the operating region.
Siliconix
1·19
0.0
~
ca
Dual Driver
Ie
H
Silicanix
designed lor . . .
•
•
•
•
•
•
Analog Multiplexing
BENEFITS
Interfacing from Low-Level Logic to
MOS Power FETs
Logic Level Translation
• Complementary Outputs
• Wide Output Swing:
33Vat ± 40 rnA
o
• Fast Switching:
70 ns Delay Time
o
Driver for PIN Diodes and FET
Switches
• Variable Input Threshold
Timing Circuits (Oscillators, Pulse
Generators, and Timers)
• Low Power Drain
Differential-Output Line Driver
DESCRIPTION
The 0169 is a versatile high-voltage dual driver with complementary outputs. Low-level logic inputs can be translated up to ± 33 V
output levels. A differential input stage with adjustable threshold provides high input impedance and easy interfacing to low-level
logic or analog inputs. Current-source coupling to the output stage allows wide flexibility in output voltage levels. The complementary emitter-follower outputs can source and sink currents of-up to±40 rnA with an output swing of up to 33 V. This output
stage is excellent for driving capacitive loads; such as power MOSFETs, long cables, or timing capacitors. The output stage can
be operated from single or split supplies. Each channel of the dual 0169 has two separate outputs that are complementary (OUT
and OUT). This two-phase output capability can be very useful for driving power MOSFET configurations.
TYPICAL APPLICATIONS
PIN CONFIGURATIONS
+5V
+15V
y+
+5V
Dual·1 n·lina Package
r-
NC
I
I
NC
I
'N~~i
I
OUT'
5I
OUTl
I
IN 1
I
I
V+
I
I
1. 1
TOP VIEW
I
I
I
:~
:
10n
IL. _____ .JI
VR
•
~9__________~
Driver for VMOS H-Switch
Driver for Dual Totem·Pola VMOS Switches
Figure 1
1-20
Silicanix
ORDER NUMBERS D169AP
SEE PACKAGE 11
D169AK OR D169CK
SEE PACKAGE 9
D169CJ
SEE PACKAGE 7
lOGIC
OUT
lm'f
0
1
v-
v+
V-
V+
ABSOLUTE MAXIMUM RATINGS
V+toV-,V+toVR,andV+toV o .................. 36V
VLtoV R, V1NtoV R, andVLtoV 1N .................... 10V
VRtoV-,VLtoV-,andVotoV- ................... 36V
Current (Any Terminal) DC ........................ 40 rnA
Peak (Pulsed 1 ms, 10% Duty Cycle) ............. 150 rnA
Operating Temperature-"A" Suffix
(A Suffix) .............................. -55to 125°C
(C Suffix) .................................. 0 to 70°C
Storage Temperature
(A Suffix) .............................. -65tol50oC
(C Suffix) .............................. -65to125°C
Power Dissipation
"P" Package* ............................... 825mW
"J" Package* ................................ 470 mW
Thermal Resistance (El JA, J Package) .......... 0.16°C/mW
* All leads soldered or welded to PC board. Derate P package
11 mW 1°C abo"e 75°C. Derate J package 6.5 mW1°C above
25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low
temperature limits to assure conformance with specifications.
CHARACTERISTIC
D169AP
D169CJ
MAX LIMITS
MAX LIMITS
25 DC
-55°C 25 DC
TVPt
-
---2.
4
5
6
DoC
70°C
25°C
TEST CONDITIONS,
UNLESS NOTED:
V+ =15V, V L=5V,
V- = -15V, VR=O
Output Voltage, High
(V+ to Vol
0.7
1.1
1.0
1.0
1.1
1.0
1.0
IOUT=l rnA
VoH/VOfi
1.5
2.5
2.5
3.1
2.5
2.5
3.1
IOUT=40mA
VOL/VQ[
Output Voltage, Low
(VotoV-)
-.75
-1.2
-3.0
-1.2
-3.0
-1.2
-4.0
-1.2
-3.0
-1.2
-3.0
-1.2
-4.0
IINH
Input Current,
Input Voltage High
1.0
5.0
5000
5.0
200
nA
V1N =3V
IINL
Input Current,
Input Voltage Low
-25
-50
-50
-50
-50
,..A
VIN=O
ns
See Switching Time Test
Circuit (C L= 35 pF)
l1li
-CD...
V
200 pF Load
~
1
2
125 DC
UNIT
-2.2
-100
-70
7 tl+1
Switching Time, Low to
High, Delay Plus Rise Time
100
170
170
8 tl-i
Switching Time, High to
Low, Delay Plus Fall Time
130
200
200
9 Vxo
Switching ';rossover Level
.9
10
1+
Positive Supply Current
-
0.1
0.1
11
IL
Logic Supply Current
3.2
4.0
4.0
12
1-
Negative Supply Current
-2.2
-3.0
-3.0
13
IR
Reference Supply Current
1.0
1.5
1.5
IOUT=l rnA
IOUT=40 rnA
:::I
rnA
tTypical values are for Design Aid only, not guaranteed and not subject to production testing.
..
"CD
No Load, V1N1 = V 1N2 = OV
CMOS
LEVEtSHIFTER
LEVEL DETECTOR
V
V1H =2 V for
VOH/Vrn:
V1L =0.8 V for
ViSfi/VOL
COMPLEMENTARV
FOLLOWER OUTPUTS
~
v,
~)~r.,
700!~
IN
Q,
0,
1---
"0
,,,
r---
Q2
'M'
"
0,
I
.,
S"
.,
51'
OU,
0,
0,
v.
0,
--11
I~
~M
0"
v-
Figure 2. Schematic Diagram. One Channel
Siliconix
1-21
•...
a
0-
ELECTRICAL CHARACTERISTICS (CONT'd)
VL
SWITCHING TESTS
1
r- f---
TEST CONDITIONS
TEST
1
2
3
4
5
6
Vl
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
VR
0.7V
0.7V
0.7V
0.7V
0
0
V+
10V
15V
10V
10V
15V
15V
V-
VIN
Cl
0
0
0
0
-15V
-15V
200
0
200
1000
200
1000
Rl
pF
510
pF
pF
pF
pF
v'
n
-
-
-
Vll
VIH
1.OV
1.OV
1.OV
1.OV
0
0
3.5V
3.5V
3.5V
3.5V
3.5V
3.5V
--,
II (D
WAVE·
FORMS
A
I.
V'N
B
B
B
B
B
I
sI
I
I
I
I
I
,.1
I
I
I
I
I
OUT
13
~J J,'.1
~I~"'
±CL}L
0'.9
,.,.
OUT
,,.
I
I
I
111
I
I
I
I
VOUT
VOUT
__
-
L...-I---f--...1
•
9
VR
V-
Figure 17. Switching Test Circuit
V'N3::.~
o
I
I
I
I .
I
I
Vour
I
I
I
I
_ _+I_-'il
I
I
I
I
I
I
I
I
I
I
I
I
I
------+-
t
--9.%
I
I
-]------t--i-,
10%
~I
i'd-I·" I
WAVEFORMS A
I
WAVEFORMS B
Table 1.
Test 2
(Fig. 17)
Test Conditions
Resistive,
lo=25mA
Tests 3 & 4
(Fig. 171
Tests 5 & 6
(Fig. 17)
V+ = +15V, V = -15V
Capacitive load
Typ
200 pF
Typ
low·to·High
Delay Time, t /
Rise Time, t /
70
35
95
60
High·to·low
Delay Time, tdFall Time, t f -
50
25
50
110
1000 pF
Typ
V+ = +15V, V =0
Capacitive load
200 pF
1000 pF
Units
Typ
Typ
220
240
110
55
230
200
ns
ns
80
400
55
80
80
275
ns
ns
Complementary Emitter-Follower Output
Transistors Q 7 through Q10 form complementary emitterfollower outputs connected to each side of the Q3- ~ level
shifter. This permits resistive loads requiring up to 40 rnA to be
driven at high speeds (rise and fall times under 50 ns - see Figure 10). Also high peak currents are available to drive capacitive loads (see Figures 11 and 12 for capacitive switching
data). The switching times are generally independent of output swing, except for the fall time which is influenced by the
negative rail, V - .
The PNP transistors have a relatively high collector series
resistance. Consequently, when a steady-state current is being drawn by the PN P which exceeds about 2 rnA, the transistor becomes saturated and minority carrier storage takes place
in the base and collector regions. Upon a change of state, a
1·22
storage delay occurs which can be substantial if a large current
is being switched (see Figures 6 and 16). This delay can be
utilized when a long "dead time" is needed during change of
state and when only the portion of the voltage waveform more
positive than zero is of interest. This storage delay does not
occur when capacitive loads are being driven, regardless of
output levels, or when the load and V - are returned to
ground.
The output levels as a function of DC output current are
shown in Figures 13 and 14. Note that no current limiting is
used in the output stages. Consequently, care must be exercised to avoid exceeding the maximum current rating of the
device.
Siliconix
TYPICAL CHARACTERISTICS
-100
4.0
N6 Lo1o
;;
;.V
V"
./
V
/'
~
V
~
./
fli
fli
:>
13
,
...
...
~
~
~
./' 'R
H]
11
-55
-15
t~7 r--
V
300
S
L
w 200
VV
"
;::
z
"
~
100
i-"""
70
~
~
30
SEE
'.
'fj
";::
~
w
>
~
50
"'0
."
-
I---'
-
40
100
>
1.0
~
05
~
",
...... ./'
0
>"
0.2
0.1
50
20
100
200
500
1000
2000
20
50
80
15
60
-
"~"
w
;::
"
";:z
0
10
40
500
1000
Figure 7. Effect of Load
Figure 8. Effect of Load
Capacitance on Crossover Level
---
20
2000
2000
SE,irEsr d3
.-:,
1000
700
500
1',
-
t'
....:-
'f
-
./
300
200
100
70
50
0
>"
200
Capacitance on Crossover Time
::><
~
~
100
CL - LOAD CAPACITANCE
CL - LOAD CAPACITANCE
SEE TEST #1
~0
T~ST::1
20
>
::i
10
20
"~
0
20
20
>
.",..
30
Figure 6. Switching Times
with Resistive Load
::i>
~
0
:3,
SEE
50
200
100
~0
'd
10
Logic I nput Voltage
YS.
10
T~ST =1
'1 0 _ OUTPUT CURRENT (rnA)
~
w
VIN - LOGIC INPUT VOLTAGE (VOL IS)
Figure 5. Logic Input Current
300
~
-
20
•
\
+125
500
!w
V -'
4
""\
w
/
./
50
r--
T - TEMPERATURE ( C)
1000
f-V-= -1OV
.65
'25
-20
Figure 4. Effect of Temperature
on Supply Currents
1000
f-v+! +10V
-40
g
'R
1.0
(V L - VR!- LOGIC SUPPLY VOLTAGE (VOL IS)
700
"
,
.."
a"
Figure 3. Supply Current Variation
with Logic Supply
500
-60
"...
~
2.0
~
0:::::::
_80
.3
30
!
V~=5~_
VA= OV
;;
SEE TESr #~
./
-
~ f:1
'y
~i"'"
,.10"
30
C/
/'
"'"
'd
20
15
20
25
30
20
10
I v+ 1+ I v-I- OUTPUT SWING (VOLTS)
30
40
Figure 9. Effect of Voltage
~
t~
v+ lOV 30V
1000 -SEE TEST #3
700
~
"
200
:t,
100
;::
~
~
.::-
70
50
30
20
l
RATio Dc
CURRENi-
/y
V
~ V)'OV
-
./ ./
100
200
V
500
1000
2000
~
5000
RATED DC
CURRENT
J~V~
,../'''
~~
50
2000
PULSED}8,~.Ils.12%
PULSEO,i.o...i2%
X/
w 300
1000
with Capacitive Load
V-.-15V/ 1/
500
SOD
200
Figure 11. Switching Times
Figure 10. Resistive Load Switching
L/
I
100
CL - LOAD CAPACITANCE (pFI
Output on Crossover Level
2000
50
10 - LOAD CURRENT (mAl
5000
Cl - LOAD CAPACITANCE (pF)
Figure 12. Fall Time with Capacitive Load
10
v-=o
.........
20
30
40
50
60
70
IOL - OUTPUT "LOW" CURRENT (mAl
Figure 13. Output "Low" Characteristic
Siliconix
80
-
10
~
20
30
~- I-Vi' -lSt
40
50
60
70
80
IOH - OUTPUT "HIGH" CURRENT (mAJ
Figure 14. Output "High" Characteristic
1-23
Figure 15. Switching Waveform
40 mA Load, V+
V- = 0
Figure 16. Switching Waveform
= 20V,
±40 mA Load, V+ = 10V,
V- = -10V
OPERATING GUIDELINES
For proper performance of the Dl69 circuit, certain guidelines must be followed for the power supply and input terminals. These
are listed below:
ALLOWABLE CONDITIONS
TERMINAL
V+ (Pin 6)
V- (Pin 9)
V R (Pin B)
Any positive voltage
~
+_
Any negative voltage or 10V::; V - V ::; 36V
zero volts
~ VEE + lV (Input Threshold = V R + l.4V)
V L (Pin 7)
VL-VR~4V
INl L, IN2L (Pins 5. 10)
~ VEE + 1V
IN1H, IN2H (Pins 5,10)
~ VEE + 3V
CIRCUIT OPERATION
The Dl69 circuit has three sections: (1) an input level detector, (2) a level shifter, and (3) a pair of complementary emitterfollower outputs. This arrangement provides a high input
impedance, high output drive capability, and compatibility
with a wide range of power supply levels. The input threshold
level can be easily varied to accept various logic levels. Output
swing is set by the V+ and V- power supply levels.
Level Detector
Transistors Q 1 and Q2 form a differential input pair. Transistor
00, resistor R1, and diodes D1, D2 form a current source of
about 1 mA which drives the common emitter connection.
The voltage between supply levels V L and V R determines the
value of the current source and the current through the bias
string (diodes Dl through D4 and resistor R2). The current
from the supply V L and the current out of the terminals V R and
V - is shown in Figure 3. Temperature variations are shown in
Figure 4. The voltage on the base of Q2 determines the trip
point where the circuit changes state. With V R grounded, the
trip point is about 1.4 volts, depending somewhat on the voltage V L• The input characteristics are shown in Figure 5.
Level Shifter
Schottky-clamped transistors Q3 and C4 along with P-channel
MOSFETs Q 5 and Os form a complementary-coupled switching stage. This configuration draws no idle current and per-
'·24
mits a change of state within 100 ns after the input signal
passes the trip point. The circuit delays are such that the
switching action approaches a "break-before-make" sequence as shown in Figure 15. The response times are essentially independent of the input signal level and rise time.
The time measured from the input signal step to where the
output waveforms from OUT and OUT cross is called crossover time. The voltage level at that time with respect to V - is
called crossover voltage. This point is of importance when
driving certain loads where a break-before-make action is necessary to avoid high current surges. The crossover time is
essentially independent of output voltage swing, but is
affected by the load capacitance as shown in Figure 7. The
delay time of the negative going waveform from OUT and
OUT is not significantly affected by load capacitance;
however, the delay time of the positive going waveform experiences a delay which is fairly sensitive to load capacitance.
This feature reduces the dependence of crossover voltage on
the load capacitance as shown in Figure B. However, the output voltage swing does exert considerable influence upon
crossover level as indicated in Figure 9.
In order to provide adequate drive to Q3 and C4, the voltage at
the collector of the differential pair must be more positive than
the V - level plus the base emitter drop of the Schottky transistors. This dictates that the "low" level of VIN should exceed
V - by at least one volt.
Siliconix
.,...
APPLICATIONS
••
+ 1 5 V o - - - - - - - - -.......- - - -......._ _---,
01,02, OJ, AND 04
AREYNJSAK
Figure 18. Totem-Pole Driver with Bootstrapping
Totem-Pole Driver with Bootstrapping
When driving VMOS in a totem-pole output configuration (see
Figure 18), it is necessary to have the gate voltage 10 to 15
volts positive with respect to the source in order to handle load
currents near the VMOS maximum ratings. The 0169 lends
itself to bootstrapping because of its high voltage ratings.
In the circuit shown, the voltage on the 2000 pF bootstrap
capacitors is applied via diode "OR" gates to the V + terminal.
Therefore, regardless of which output is high, 30 volts is present at V+. Maximum switching frequency is determined by
the input capacitance of the VMOS transistors used.
-...
~
CD
aft
",
CD
r--~-'-""""
c,
I
I
I
I
",
I
I
",
10K
I
I
I
I
our2
I
L._
I
•
--r,-_.J
6'
Figure 19. 0169 Used as a Voltage-to·Frequency Converter
Voltage-to-Frequency Converter
A simple, low-cost VFC can be designed using the 0169 and a
single op amp (see Figure 19). The 0169 serves as a level
detector and provides complementary outputs. The op amp is
used to integrate the input signal V'N with a time constant of
R,C,. The input, which must be negative, causes a positive
ramp at the output of the integrator which is then summed
with a negative zener voltage. When the ramp is positive
enough to cause the 0169 input (pin 10) to exceed the logic
threshold of 1.4 V, then the 0169 outputs change state and
OUT 2 flips from negative to positive. This positive output of
approximately 11 V puts transistor 0, into saturation which
then resets the integrator to near zero. The integrator peak differential voltage AV will be approximately 9.2 V. The output
frequency f 0' neglecting the short reset interval, will be
The pulse repetition rate, fo' is directly proportional to the
negative input voltage V'N'
Siliconix
1-25
H
Siliconix
Telecommunications _
Index
TELECOMMUNICATIONS
Title
Page
DF320/320A/322 .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
DF328 ....................................................................................... 2-12
LOOP DISCONNECT DIALERS
Product
DF3201 DF320AI DF322
DF328
Description
Application
Crystal Oscillator
LC or Crystal Oscillator
Replacing Conventional
Rotary Dial Phones with
Push Button Keyboard Phones
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) devices without
resulting in permanent damage. This is a stress rating only and not subject to production testing. Exposure
to absolute maximum rating conditions for extened periods may effect device reliability.
CMOS Loop Disconnect
Dialers
H
Siliconix
BENEFITS
•
designed for . . .
•
Eliminates the Need for Regulated Supplies
o 2.5 V to 5.5 V VDD Range
Minimizes Power Consumption
o Standby Dissipation - 6 flW
• Push Button Telephones
•
Low Cost
o Simple Support Circuitry
o Power On Reset
• Repertory Dialers
•
• Telex
• Mobile Telephones
• Security and Fire Alert Systems
Minimizes External Components
o On Chip Circuitry for: Keyboard Debouncing; Last Number Repeat; Input
Pull Up/Pull Down Terminations
•
Versatile
o Selectable Mark/Space Ratios, Impulsing
Speeds
• Emergency Number Dialers
o Hold Facility to Delay Impulsing
o Fixed lOP: 8 Times Impuls'ing Period
DESCRIPTION
The DF320 series of monolithic CMOS Loop Disconnect Dialers each contain all the logic necessary to interface a standard
double contact keyboard to a telephone system requiring loop disconnect signalling.
A dial pulsing output and two masking output options are provided to control the impulsing (loop disconnect) and muting
functions. The circuit is capable of storing a number string of up to 20 digits and re-dialing this stored number automatically at a later time, initiated by a RE-DIAL input code. Impulsing mark/space ratio (M/S), and impulsing rate are pin
programmable to meet most telephone authority specifications.
IEII
The use of Siliconix low voltage CMOS technology allows operation with an unregulated supply voltage down to a guaranteed
minimum of 2.5 V. This feature, together with low operating current, negligible standby current and high noise immunity
make the DF320 series easy to interface to long telephone lines.
CD
CD
External component count is minimized by the inclusion of an on·chip clock oscillator, high impedance pull-down terminEtions to programming inputs as well as pull-Up terminations to the keyboard giving direct interfacing.
The DF320 provides the functions most commonly required in the push button telephone application. M1 is the masking
option which remains at logic "1" throughout the dialing sequence. The DF322 is identical to the DF320 except that M2 is
offered instead of M1. The M2 masking option is at logic "1" only during impulsing, allowing the telephone line to be monitored during the lOP. The DF320A has an extended post impulsing pause of 500 ms.
PIN CONFIGURATION
DP
M'"
MIS:
I
~
~HOlD
IT
IT
~V4
~ V3
~
4
DF320DJ
DF320DK
~
15 V2
r7
DF320ADJ
DF320ADK
DF3220J
DF322DK
~
F01
L.:!.
F02
~
, r;:;-
[I
XTALIN ~
CE
XTAL OUT
lI:
"o
:I
3
c
:s
..--0
"
D
~
(It
~ V1
r.;:;,
~ X3
~ X2
~Xl
~ Vss
---''--""'TO''''P''-V''',E,-w-r"M2 ON DF322DJ, DF322DK
ORDER NUMBERS DF320DJ, DF320ADJ OR DF322DJ
SEE PACKAGE 19
ORDER NUMBERS DF320DK, DF320ADK OR DF322DK
SEE PACKAGE 23
Siliconix
-
o
DUAL-IN-LINE PACKAGE
Voe
....jI
2-1
ABSOLUTE MAXIMUM RATINGS
VDD - VSS . . . . . . . . . . . . . . . . . . . . -0.3 V to 8 V
Voltage on Any Pin . . . . . . VSS - 0.3 V to VDD + 0.3 V
Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature . . . . . . . . . . . . . . -40 to +85°C
Storage Temperature (K Package) ...... -65 to +150°C
(J Package) ...... -65 to +125°C
Power Dissipation
(J and K Package) ....... 450mW
"Derate 6.3 mWtC above 25°C. All leads soldered to PC
board.
ELECTRICAL CHARACTERISTICS
All voltages referenced to VSS unless otherwise noted.
Test Conditions Unless Noted:
Min
Characteristic
1
I-2
I-
s
U
p
3
4
Supply Voltage Operating Range
5.5
V
lOSS
2.0
10.0
I'A
CE
100
Operating Supply Current
155
250
I'A
3.579545 MHz Crystal. CXTAlOUT = 12 pF
-6
-10.0
I'A
VIN
= VSS
nA
VIN
= VOO
= VSS
= VOO
Pull-Up Transistor Source Current
5
IIH
Input Leakage Current
6
U
IlL
Input Leakage Current
7
IIH
Pull-Down Transistor Sink Current
8
Vil
logic "0" level
9
VIH
logic "1" level
l- T
11-
o
VOL
Low Level
11
T
VOH
High Level
12
~
13
l16,
I-
0
20
N
21
M
I
C
V
Hold
V
0
0.01
V
2.99
3
V
0.5
1.5
mA
VOUT'" 2.3 V
--{).5
VOUT
1.5
mA
Output Rise Time
1.0
I'S
tf
Output Fall Time
1.0
I'S
'ClK
Maximum Clock Frequency
P-Channel Source
MHz
3.58
= 0.7 V
= 50 pF
3.579545 MHz Crystal
Note 1
Mark to Space Ratio
lOP
Interdigital Pause
Impulsing Rate
= 1T
= Selected Impulsing Period, Note 1
ms
T
Hz
Note 1
ms
Timed from CE
pF
Any Input
0.3T
ms
5T
ms
DF320, DF322,
DF320A
16
20
23
1-
8T
10
932
1-
-
0.65
MIS, F01, F02,
OP, M1, M2
N·Channel Sink
1- A
tON
Clock Start Up Time
1.5
CIN
Input Capacitance
5,0
POIP
Post Impulsing Pause
26
-
VIN
3:2
I- V
25
VIN
I'A
tr
MIS
18
I19
24
nA
10.0
X1. X2. X3.
Y1. Y2. Y3. Y4
2:1
I-
1-
3.0
Drive Current
17
22
--{).1
0.5
OP, M1, M2, CL
15
1-
I-
0.1
No load
IOH
14
--{).5
= VSS
All Inputs
10
1-
2.5
2.45
1 - U I---- Voltage Levels
l-
VDD = 3.0 V. TA = 25'C
'ClK = 3.57945 MHz
Units
Standby Supply Current
III
I--
Max
VOO
N
P
I-- I
Typ·
27
4
= logic "1"
T
= Selected
*Typical parametric values are for Design Aid Only. not guaranteed and not subject to production testing. Timing waveforms are subject to
production functional test.
NOTES:
1. See Pin Function, Table 1
2·2
Siliconix
Impulsing Period
C
FUNCTIONAL BLOCK DIAGRAM
FOI
F02
"1'1
W
HOLD
MiS
t-.)
C
C
XTAL IN
0--+---1
XTAL OUT
0--+---1
"1'1
W
t-.)
c
l>
CEo--+----~-------_t_i--~
c
"II
W
t-.)
~
MI
M2
DP
VDD
Vss
l1li
INPUT OUTPUT SCHEMATICS
-I
,..CD
CD
VDD
VDD
;r
o
r::l :~J-
3
3
L:J~~
c
VSIAS
VSS
Vss
:::a
-.
Vss
MIS, F01, F02, HOLO
Xl' X 2 , X 3 , Y l , Y 2 , Y 3 , Y 4
XTAL IN
Figure 1
Figure 2
Figure 3
..'"-.
C
o
~
fit
-lK
n
CE
DP, Ml, M2
XTAL OUT
Figure 4
Figure 5
Figure 6
*Circuit Protection Not Shown
Siliconix
2-3
TYPICAL CHARACTERISTICS
Typical Dynamic Current
vs Supply Voltage
Typical Quiescent Current vs
Temperature
10000
12
-
~....
.-
-
~
~
f-
~
~
~
C
I
E
Voo
-2
CL -12pF
"
z
>0
./
-40 -20
0
20
40
60
80
..-V
/
100
-4
-60
. . . ..v
500
I
0
_0
3V
-I
/
1000
iE
l-
I-- ~
:;
5000
a:
a:
::>
u
u
Voo= 5V
a>l'l
Typical Percentage Deviation
of Dynamic Current vs
Temperature (Normalized
to 25°C)
100
-1
TA _25°C
I
-2
-60 -40
o
Voo - SUPPLY VOL rAGE (V)
TA - TEMPERATURE ('C)
Typical Input Pull-Up Current
vs Supply Voltage
(X1, Y2, X3, Y1, Y2, Y3, Y4)
Typical XTAL IN Input Clamp
Characteristics
-20
0
20
40
60
80
100
TA - TEMPERATURE ('C)
Typical Input Pull-Up
Characteristics
1000
TA '" 25 C
TVP TEMP. COEFFICIENT = -0.2%/ C
;;
.3
>-
~
cc
VALIDONLYIF~~ VOO=5V
750
"u;
.,
~
~
250
o
-4
~
-8
>-
~
cc
cc
a: -12
a:
::>
u -16
~
::> -20
a
/
~ -24
....
~ -28
~
1 I-- -
~
Voo" 3V
I
~
~
-7
-6
Typical Input Pull-Down Current
vs Supply Voltage
(M/S, F01, F02, Hold)
~
a:
a:
::>
u
-4
-3
-2
-8
-8
-1
I
-
V
-2
-4
-6
VIN -INPUT VOLTAGE (V)
Typical Input Pull-Down
Characteristics
Typical CE Sink Current
140
TA = 2S'C
TVP TEMP COEFFICIENT" -l.0j'-C
12 -TA- 25°C
_
TYPICAL TEMP.
COEF. "" -O.6%fc
10
/
/
L
0
0
:l
~
....
~
./
V
L
!--
~~__~=+==*=~VDD'5Vr--
(
120 _ T A =25°C
;;
-
.3 100
~
I
a:
cc
::>
u
V
l!!u;
"'
u
/
80
/
60
/
40
V
20
o
Voo - SUPPLY VOLTAGE (Vl
~6~1~~L_~E2~fc
....
J.
2-4
Voo = 5 V
-
14
:;
~
I
-5
-6
Voo - SUPPLY VOLTAGE (VI
XTAL INPUT VOL lAGE IV)
1
....
o.&x.rc
f--COEF.
-40
o
IVDo13V
rt1/
-4
....
.,
~
r--- T A'" 2SoC
-32 r--- TYPICAL TEMP.
_= -36
If'
TVP TEMP. COE1FFICI1ENT = -0.7%1 C
-2
~
'?
:l
V
>~
~
/
500
~
>-
V
::>
u
Z
TA = 25 C
f--
VIN - INPUT VOLTAGE (V)
Siliconix
,./
o
CE SUPPLY VOLTAGE (VCE = VDO)
TYPICAL CHARACTERISTICS (Cont'd)
Typical CE Source Current
.,
-'0
1...
til
0:
0:
:J
"w
":J
0:
g
w
"I
.5
...
-30
iii0:
-50
:::>
.,
"
5I--T~.JC
-90
0:
0
-130
COEF.• -0.2%/'C
:J:
~
Z
,
I
-170
z
-7
-6
-5
-4
-3
S'
-,
-2
/
,
0
0
V
2
/
V
Drain Characteristics (DP, M 1, M2)
o
TAl.
0:
/
-3
Z
V
z
" -,
:J:
~
0-
/
I
0-
3
,
_0
5
6
7
_7
Voo - SUPPLY VOLTAGE (VI
CE INPUT VOLTAGE (VeE =Vool
V
/
-2
0
-'
w
J
COEF. - -O.2%fC/
0:
z
25,b
-TVPIC~L TEMP.
-1
:::>
.,"
/
3
2
"
-150
-'
iii0:
/
4
z
.,
...
-'
w
Z
Typical P·Channel Output
.5
TYPICAL TEMP.
Z
-110
-'90
6
0:
TA-25~C
TYPICAL TEMP.
COEF. c O.3%rC
-70
Typical N·Channel Output
Drain Characteristics (DP, Ml, M2)
-6
-5
-4
-3
-2
-,
0
Voe - SUPPLY VOLTAGE (V)
i
Table,
PIN FUNCTION
OESCRIPTION
Veo
Positive voltage supply
ep
Dial Pulsing Output Buffer
Ml
Mask 1 (Buffered Output)
M2
Mask 2 (Buffered Output) "" Logic "1" during an Impulse
MIS
Mark/Space (Break/Make) Ratio select. On-chip active pull-down to VSS'
a C
I
FO'. F02
Vee
= Logic
2:1
I
3:2
I
--
"1" during Dialing Sequence
Note:
a
...
CD
CD
C = Open circuit, see Figure 7
ft
o
3
3
Impulsing Rate Selection. On-chip active pull-down to VSS.
Nominal
Actual·
Impulsing Rate
System
Clock Frequency
FO'
F02
o c
a c
10 Hz
10.13 Hz
303.9 Hz
a C
VOO
20 Hz
19.42 Hz
582.6 Hz
VOO
o C
932 Hz
932.17 Hz
27,965.1 Hz
Voe
Vee
16 Hz
15.54 Hz
466.1 Hz
*Assumes fCLK
Impulsing Rate
XTAL IN
Crystal Input. Active. clamped low if CE
XTALOUT
Crystal Output. Buffer to drive crystal. Capacitive load on-chip.
VSS
System ground
X,. X2. X3
Column keyboard inputs having active pull-ups to VOO. Active LOW
y,. Y2. Y3, Y4
Row keyboard inputs having active pull-ups to VOO. Active LOW
HaLO
Prevents further impulsing. On-chip active pull-down to VSS
C
._.
a
o
Chip Enable. Input/Output, left open it is internally controlled by keyboard decode logic. Can be externally forced for
manually enabling chip.
VOO
-.
::s
ft
= 3.579545 MHz
CE
La
c
::s
III
= "0", high impedance if CE = "1".
Normal Operation
I
No ImpUlsing. If activated during impulsing, hold occurs when the currentJ
digit is complete.
Siliconix
2·5
FUNCTIONAL DESCRIPTION
'.0 Clock Oscillator - The on·chip oscillator amplifier is
connected between the XTAL IN and XTAL OUT pins.
The oscillator is completed by connecting a 3,579,545 Hz
crystal in parallel with a 'OM [2 resistor between XTAL IN
and XTAL OUT. When CE ; "a" an N·channel transistor
clamp is activated, disabling oscillator operation. On the
transition of CE to logic "'" a fast oscillator turn·on circuit
kicks XTAL IN voltage to the amplifier bias point allowing
oscillator operation within 4 ms. The basic clock frequency
of 3.58 MHz is predivided by a programmable counter to
provide the chip system clock.
As an alternative, an LC oscillator can be formed as shown in
Figure 15. Selection of fCLK ; 38.4 kHz with FOl connected to VDD will give an impulsing rate of 10 Hz.
It is also possible to control the DF320, DF320A, DF322
from an external clock applied to XTAL IN.
2.0 Chip Enable, CE - The Chip Enable pin is used to
initialize the chip system. CE ; "a" forces the chip into
the static standby mode. In this mode the clock oscillator
if OFF, internal registers are reset with the exception of the
WRITE ADDRESS COUNTER and the circuit is ready to
receive a new number or re-dial. While CE ; "a" data cannot be received by the chip, but data previously entered
and stored is maintained. When CE ; "1" the clock oscillator is operating, the internal registers are enabled, and
data can be entered from the keyboard up to a maximum
of 20 digits.
CE is primarily controlled by a logic gate with function
F; KEYBOARD INPUT+ Ml + HOLD
where + denotes logical OR.
To operate this gate, a resistor and capacitor should be
connected in parallel between CE and VSS. When the chip
is used in the CE INTERNAL CONTROL MODE power ON
reset occurs when VaD is applied, since a logic "a" appears
on the CE pin. The chip remains in the static standby condition until it receives the first valid keyboard input after
VDD is applied. This is statically decoded and causes
CE ; "1", hence enabling the clock oscillator. The debounce counter is then clocked by the system clock until
the valid data condition is recognized. Data is then written
into the on-chip RAM. CE is maintained at logic "'" by
M' during dialing.
The WRITE ADDRESS COUNTER is reset on recognition
of the first val id debounced keyboard input provided that it
is decoded during td of the pre-impulsing pause PIP (see
Figure 8). In the CE INTERNAL CONTROL MODE this
condition will always apply. When all keyed digits have
been dialled, M 1 goes to logic
and hence the ch ip
returns to the static standby condition. If digits are sub-
"a ..
2-6
sequently keyed during the same OFF·hook period, after a
pause in dialling for example, the digit string will be recog·
nized as a new number. This is not important provided
RE·D IAL operation is not required.
The alternative to the CE INTERNAL CONTROL MODE
is to override the internal logic gate with an externally
derived signal. This mode of operation is referred to as the
CE EXTERNAL CONTROL MODE. Figure 7 shows that
if CE goes to logic "1" in the absence of a keyboard input,
a single pulse of duration td is generated on M 1. This pulse
is intended to initialize a bistable latching relay used as
shown in Figure 12. Immediately prior to Ml going to
logic ",", the WRITE ADDRESS COUNTER is reset.
All digits keyed subsequently are entered into consecutive
RAM locations up to a maximum of 20. After the WR ITE
ADDRESS COUNTER has been reset, the RE-DIAL input
code will not be recognized by the circuit. It is necessary
that CE be maintained at logic "a"
f.1s after VDD is
applied in order to ensure correct system initializing. If
CE is linked to VDD by the method shown in Figure 12,
adequate delay is obtained.
>,
3.0 Data Entry - Data is entered to the circuit via a double
contact keyboard connected as shown in Figure 10. Keyboard inputs are active low and encoded as shown in
Table 2.
Keyboard Code
Table 2
No. of O/P
Pulses
Digit
Y1
Y2
Y3
Y4
X1
a
a
a
1
1
1
1
1
1
1
a
a
a
1
1
1
X2
X3
a
1
1
1
a
1
1
1
1
a
1
a
1
1
1
1
a
1
1
1
1
1
0
1
a
1
1
1
1
a
1
1
1
1
1
a
a
1
1
1
a
1
1
2
2
3
3
4
4
1
5
5
1
6
6
1
7
7
1
1
8
8
9
1
1
1
1
a
a
a
a
1
1
1
1
1
1
9
10
RE-DIAL
a
a
NOTE: "0" Indicates pin taken low.
Keyboard inputs are fully decoded eliminating any possibility of invalid codes being recognized. A BCD format is used
on-chip for data storage. Valid inputs have contact bounce
removed via the debounce counter. Operation is illustrated
in Figure 9. Input data is not written into the RAM until
the input code has been present for a minimum of 3P and
maximum of 4P (P ; System Clock Period). The 1P
uncertainty arises since data entry is not synchronized to
the system clock. This is indicated by the shaded area on
the keyboard entry waveform of Figure 9. The trailing
edge of a keyboard entry is also debounced. The operation
Siliconix
FUNCTIONAL DESCRIPTION (Cant'd)
incremented on each digit entry. The contents of this
counter indicate the length of the number to be dialled.
The RE·DIAl code is recognized only if it is presented to
the chip a maximum of 5P after CE = "1 ". Decoding of
RE·DIAl then inhibits the reset of the WRITE ADDRESS
COUNTE R, initiates the dialling sequence and the previous
number string entered is dialled. If the circuit application
is to utilize RE·DIAl, external CE control is necessary in
some cases to ensure that CE = "1" from the first keyboard
entry throughout dialling in order to ensure all digits
entered are stored consecutively should a delay occur
during dialling.
of the debounce circuitry results in a maximum data entry
rate of SYS ClK -;- 9. Referring to Figure 9, data must
remain stable during the RAM data entry period. Maximum
contact bounce rejection is 10 ms at 10 Hz, 6.3 ms at 16 Hz
or 5 ms at 20 Hz impulsing rates. Minimum data valid time
is 16.7 ms at 10 Hz, 10.4 ms at 16 Hz or 8.4 ms at 20 Hz
impulsing rates.
Upon recognition of the first keyboard input of a number
string, the dial out sequence is initiated by a pre·impulsing
pause (Figure 7). The WRITE ADDRESS COUNTER is
VDD
CE
Ml
--1 t-
KEYBOARD
ENTRY
tb
BREAK
D P - - + + + - - - + - t - + - - - - + t - - - - - - - ; - - I l J U L ,____
~~~~_h-
M2
~
-,DP.8T-~_MAKE
PIP---
'm
DIGIT J IMPULSED
'd
--
DIALLING
lOP'" 8T
COMPLETE
DIGIT 4 IMPULSED
POIP
NOTES:
(1) td=10xP
P = System clock period = T 130
T is selected impulsing period
(2) Pre-Impulsing Pause (PIP) = aT + td
(3)
(4)
.CD...
Post·lmpulsing Pause (POIP) is equal to td ms on DF320, DF322 and
5T on DF320A.
tb/tm is the BREAKIMAKE RATIO. T = (t m + tbl ms.
tm = 10 x P for 2:1 MIS ratio. tm = 12 x P for 3:2 MIS ratio.
CD
ft
Loop Disconnect Dialler Timing Diagram CE-External Control
Figure 7
o
3
3
c
vooJ
~----------------~.~----------------~II.~~-----------------------<
-.:::s
.
svs eLK
ft
a
-.
o
CE
Ml
:::s
----I-!
1ft
KEYBOARD
ENTRY
DP
M2
HOLD
'm
f----IDP----t--NOTE:
(1 I ti = tON
POIP
+ td where tON = Clock Start Up Time
Loop Disconnect Dialler Timing Diagram CE-Internal Control
Figure 8
Siliconix
2-7
FUNCTIONAL DESCRIPTION (Cant'd)
4.0 Dialling Sequence - The dialling or impulsing sequence
is initiated on recognition of the first keyboard entry after
CE ; "1". The dialling sequence is identical for both
internal and external control of CEo (See Figure 7 and
8).
The dialling sequence can be interrupted by applying logic
"'" to HOLD. If HOLD; "'" is applied during dialling of
a digit, the circuit does not enter the HOLD mode until
the digit is complete. In the HOLD mode M1 = "0", allowi"ng
the telephone line to be monitored. When HOLD is released
dialling continues preceded by an IDP. (See Figure 8).
HOLD is used to extend the I DP allowing intermediate dial
tone recognition if RE·DIAL is used in a PABX for example.
Operation can be manual or via external control logic as
shown in Figure 13.
The basic impulsing pulse train is derived from the TIMING
COUNTER AND DECODE. The lOP is timed by forcing a
code on the OUTPUT COUNTER and inhibiting DP for the
duration of IDP. The READ ADDRESS COUNTER then
addresses the RAM and the first digit is used to program
the decode of the OUTPUT COUNTER. A number of dial
pulses is output via DP corresponding to the BCD data read
from the RAM. At the completion of the digit, the READ
ADDRESS COUNTER is incremented. The sequence con·
tinues until coincidence is recognized between the READ
ADD RESS COUNTER contents and the WR ITE ADDRESS
COUNTER contents. The post·impulsing pause POIP, is
then generated. The circuit then enters the dynamic standby
condition if CE is maintained at logic "'" by external
control, or the static standby condition if CE INTERNAL
CONTROL MODE is used.
NOTES:
(1) The keyboard input decoding is mask programmable to
suit different input codes.
(2) The timing circuitry is mask programmable to give
different MIS ratios and IDP values.
(3) The clock predivision circuitry is mask programmable
allowing use of different crystal or external clock
frequencies.
(4) The logic sense of DP, M1 and M2 outputs is mask
programmable.
Impulsing rates, impulsing mark·to·space ratio and inter·
digital pause are programmable as shown in Table 1.
SYSCLK _ _ _ _ _ _.....
CONTACT
Lf"l§1_ _--....I11l1...mI
KEYBOARO--------,
ENTRY
NOISE
DATA ENTRY
TO RAM
DEBQUNCEO
-l I-
f-!,-----..,
KEY~~~=e------------...J1
~
________
Keyboard Input Debounce Timing Diagram
Figure 9
APPLICATIONS
The circuit of Figure 10 shows a method of connecting the
D F320 in parallel with the telephone network.
When the handset is lifted and power applied to the circuit
02 is fed base current through R2 which in turn drives 01.
C2 is charged via R3 in series with D1 to (VZ1 - 0.7)V.
When the minimum operating VDD voltage is reached,
power ON reset occurs via the CE network of C, and R8.
02 is maintained in the ON condition by G1 while 03,
and hence 04, are held OFF by G2. The DF320 network
appears in parallel with the telephone as an impedance
> 10K n in the standby condition with the telephone
network connected in circuit through 01.
On recognition of the first keyed digit, the DF320 clock is
started. M1 then goes to logic "1" causing 02, 01 to turn
OFF, and 03, 04 to turn ON. Hence the majority of the
line loop current now flows through 04, and Z1. When
2-8
impulsing occurs 03 and 04 are turned OFF by DP acting
on G2. Line loop current is then reduced to approximately
50 /lA taken through R2, R4 and G2 in series.
When dialling is complete M1 goes to logic "0" causing the
telephone network to be reconnected. The D F320 then
returns to the static standbY condition. If the line loop is
interrupted by the cradle switch during dialling, impulsing
will continue until C2 discharges to a voltage such that R8
pulls CE to logic "0" causing the DF320 to reset.
The diode bridge protects the network from line polarity
reversal.
The circuit of Figure 11 shows a simple method of series
connection of DF320 into the telephone set suitable for
PABX or short line applications.
Siliconix
APPLICATIONS (Cant'd)
When dialling is complete the circuit returns to the static
standby condition and Q1 is switched OFF. Circuit reset
during a Iine interruption by the cradle switch is as for the
parallel connection mode.
When the telephone handset is lifted,C1 is charged via 01
to (VZ1 - 0.7) volts and OF320 power ON reset occurs.
When the first keyed digit is recognized, M1 goes to logic
"1" muting the telephone network by switching on the low
ON resistance JFET Q1, and maximizing the line loop cur·
rent for impulsing. Impulsing occurs through OP switching
Q2,and hence Q3,OFF. Rapid discharge of C1 through Z1
is prevented during line break by the blocking diode 01.
If a requirement exists that no semiconductor components
should appear in the telephone loop during normal speech,
the circuit of Figure 12 is required.
a,
a4
2N4403
HOOK
z,
2N6520
"3
SWITCH
3.9
4.7K
~
0,
C2
22/.lF
IN40Q4
"4
Vz
4.7K
TELEPHONE
+
LINE
~
".
'OM
III
.....
-
CD
CD
KEYBOARD
DF320 Parallel Telephone Connection
Figure 10
'":Io
:I
c
-.
'"Q
-.
o
~
..
0,
HOOK
SWITCH
IN4004
Z,
-/.
3.3Vz
~
M'
.,
TELEPHONE
LINE
til
VDD
DP
'2
-/.
'3
DJ01I1
KEYBOARD
!!ImlIl
mlIlm
El!:2l0
V,
V2
V3
"3
'M
"4
1.2K
V4
"5
'OK
DF320 Series Telephone Connection
Figure 11
Siliconix
2-9
APPLICATIONS (Cont'd)
short circuited by the keyboard common switch. M1 then
goes to logic "1" switching the bistable relay hence main·
taining the DF320 network in circuit. Impulsing occurs
through DP switching 01 OFF which in turn switches 02.
When dialling is complete the bistable relay is pulsed,
switching the telephone network back in circuit and short
ci rcu iti ng the D F320 network.
While the circuits of Figures 10 and 11 did not require a
common keyboard contact, it is necessary to have a common changeover switch in this case operating in conjunction
with a bistable relay. In this application external control
of CE is provided by the R 1, C2 network. If, when the
handset is lifted, the relay contact is such that the DF320
network is connected in circuit, it is necessary to initialize
this relay to reconnect the telephone network. This is
achieved by the single pulse which occurs on M1 if CE goes
to logic "1" in the absence of a keyboard input (Figure 7).
The circuit of Figure 13 shows additional gating circuitry
to provide an automatic access pause after the first digit is
dialled, by controlling HOLD. This is useful in PABX
applications, eliminating the need for a manual hold facility
if RE-DIAL is used.
When the first digit is keyed, the DF320 network is con·
nected into the telephone loop and the telephone network
HOOK
SWITCH
-/.'-1-----,
TELEPHONE
LINE
[]]mm
m
mm
mmm
KEVBDARD
El01!l
OF320 Bistable Relay Telephone Connection
Figure 12
TEL.EPHONE
Re·Oial with automatic single digit access pause for PABX
0
NETWORK
VDD
-------------,
I
I
CONTINUE
Z,
56VZ
VDD
Zz
M'
R2
470K
3.9VZ
HOOK
SWITCH
,On,c,
0,
TELEPHONE
2N440D
....---.--y
LINE
R.
10K
[]]mm
mmm
mmm
El01!l
o F320 Series Telephone Connection
Figure 13
2-10
Siliconix
R.
'M
APPLICATIONS (Cont'd)
The basic interface circuit is similar to that shown in
Figure 11. Muting is achieved by 03 and line switching by
02 driven by 01.
In the ON-hook condition, 01 is held OFF by G13 and
standby current is suppl ied to the D F320 network by R a;
providing voltage limiting. CE is clamped to logic "0" by
G3. The DF320 is in the static standby mode and the
previously dialled number is stored.
When the handset is lifted, G13 goes to logic "0" switching
01, and hence 02, ON. The DF320 network VDD is now
given by (VZ2 - 0.7) volts. The DF320 remains in the
static standby mode until the first key operation. G 1
decodes the common key function toggling the latch
formed by G2 and G3 causing CE = "1 ". CE remains at
logic "1"throughoutthe remainder of the OFF·hook condition ensuring that all digits keyed are stored by the DF320
as one number string. (See FUNCTIONAL DESCR IP·
TlON, 3.0 DATA ENTRY).
If the first key operated is RE·DIAL, this condition is
decoded by G5, and via Ga sets the latch formed by G7
and Ga. G9 is enabled and the first dial pulse causes the
latch formed by G 11 and G 12 to be set taking HO LD
to logic "1". When the first digit is complete M1 goes to
logic "0" enabling the telephone network. When dial
tone is recognized the CONTI NU E switch is operated
causing HOLD = "0" by resetting the latches formed by
G11, G12 and G7, Ga. The remainder of the number is
then re·dialled. Subsequent operation of RE·DIAL is
blocked by Ga.
Figure 14 shows a simple method of interfacing a single
contact matrix·type keyboard to the D F320. Operation of
a key causes the on-chip pull·up transistor of the Y input
to provide base drive current to the corresponding X input
external bipolar transistor, which sinks the X input pull-up
current through its collector. Hence, a valid code is pre·
sented.
As an alternative to the crystal oscillator it is possible to
operate the DF320 from an LC combination connected as
shown in Figure 15. F01 is connected to VDD selecting
the 932 Hz impulsing condition. An oscillator frequency of
3a.4kHz will give a 10Hz impulsing rate.
III
i
-
L-+---~-4----~-oY,
CD
L-+---~-4----~-oY2
"o
3
3
c
~+----+-4----+--oY3
0-+------oY4
-.:::s
"Q-.
c,
~------+--<>
..
X2
~------~----~-OX,
o
:::s
1ft
LC Oscillator
Figure 15
Single Contact Keyboard Interfac.
Figure 14
Siliconix
2-11
10
E CMOS
a
Loop
Disconnect Dialer
H
BENEFITS
designed for . . .
•
Push Button Telephones
•
Repertory Dialers
• Telex
• Mobile Telephones
•
Security and Fire Alert Systems
•
Emergency Number Dialers
Siliconix
DESCRIPTION
•
Eliminates the Need for Regulated Supplies
o 2.5 V to 5.5 V VDD Range
•
Minimizes Power Consumption
o Standby Dissipation <3 pW
•
Low Cost
o Simple Support Circuitry
o No External Power Up Reset Compon·
ents
•
Minimizes External Components
o On·Ch ip Circu itry for: Keyboard
Debouncing; Last Number Repeat; Input
Termination
•
Versatile
o Selectable Mark/Space Ratio, Impulsing
Speeds
o Oscillator Uses Either LC Network or
Crystal
The DF328 monolithic CMOS Loop Disconnect Dialers each contain all the logic necessary to interface a standard double
contact keyboard to a telephone system requiring loop disconnect signalling.
A dial pulsing output and muting output are provided to control the impulsing (loop disconnect) and muting functions_
The circuit is capable of storing a number string of up to 20 digits and re-dialing this stored number automatically at a later
time, initiated by a RE-DIAL input code. Impulsing mark/space ratio (M/S) and impulsing rate are pin programmable to
meet most telephone requirements.
The use of Siliconix low voltage CMOS technology allows operation with an unregulated supply voltage down to a guaranteed
minimum of 2.5 V. This feature, together with low operating current, negligible standby current and high noise immunity
make the DF328 easy to interface from long telephone lines.
External component count is minimized by the inclusion of an on-chip clock oscillator, high impedance pull-down terminations to programming inputs as well as pull-up terminations to the keyboard giving direct interfacing.
The DF328 provides the functions most commonly required in the push button telephone application. M1 is the muting,
output which remains at logic "1" throughout the dialing sequence.
FUNCTIONAL BLOCK DIAGRAM
PIN CONNECTION
DUAL-IN-LINE PACKAGE
ORDER NUMBER DF328DJ
SEE PACKAGE 8
2-12
Siliconix
ABSOLUTE MAXIMUM RATINGS
vDD - VSS • . . . . . . • . • . . • . . . . . . .
-0.3 V to 8 V
(J Package)' . . . . . . . . . 450mW
Power Dissipation
Voltage on Any Pin ••...• VSS - 0.3 V to VDD + 0.3 V
......................
Current at Any Pin
10mA
Operating Temperature . . . . . . . . . . . . . . -40 to +85°C
Storage Temperature
(J Package)
...
.
'Derate 6.3 mWfC above 25°C. All leads soldered to PC
-65 to +125°C
board .
ELECTRICAL CHARACTERISTICS
All voltages referenced to VSS unless otherwise noted.
Characteristic
r---22
~
s
U
P
4
r-5
6-
7
-
8
-
I
N
P
U
T
9
10
- 11
~
- 13
0
U
T
14
- 20
I-21
In
123
7
0
Y
N
A
M
I
C
Supply Voltage Operating Range
Typ'
2.5
Max
Units
5.5
V
Test Conditions Unless Noted
VOO = 3.0 V. TA = 25'C.
fCLK = 3.579545 MHz
.-
lOSS
Standby Supply Current
1.0
15.0
/LA
CE = VSS
100
Operating Supply Current
180
250
/LA
3.579545 MHz Crystal. CXTALOUT - 12 pF
IlL
Pull·Up Transistor Source Current
-3.0
-10.0
,..A
VIN - VSS
IIH
Input Leakage Current
0.1
nA
VIN
IlL
Input Leakage Current
-0.1
nA
VIN
IIH
Pull-Down Transistor Sink Current
10.0
/LA
VIN
VIL
Logic "0" Level
0.65
V
VIH
Lo gic "1" Level
~
Voltage Levels
~
IOH
Drive Current
-0.5
0.5
3.0
V
2.45
0
Low Level
VOH
tr
JI
16
- 17
- 18
- 19
VOO
Min
High Level
N-Channel Sink
P·Channel Source
tf
Output Fall Time
Clock Frequency
MIS
Mark to Space Ratio
lOP
I nterdigital Pause
Yl. Y2. Y3. Y4
MIS FOl
....
V
0.5
2.0
rnA
VOUT- 2.3 V
-0.5
-1.5
rnA
VOUT= 0.7 V
Il5
1.0
/LS
OP.Ml
OP. Ml
ft
o
CL
:I
:I
c
= 50 pF
MHz
3.58
0.03
-
CD
CD
No Load
3
1.0
lEI
All Inputs
2.99
Output Rise Time
fCLK
V
0.01
Xl. X2. X3.
= Voo
= VSS
= VOO
2:1
I mpulsing Rate = 1IT
....
::I
..-.
See Table 1
3:2
8T
ms
10
T
ft
= Impulsing Period
Hz
See Table 1
ms
Timed from CE
IQ
o
932
tON
Clock Start Up Time
1.5
CIN
Input Capacitance
5.0
pF
Any Input
POIP
Po
/
500
~
~
~
250
/
If
-2
-
~
;;
=
25 C
-j
COE1FFICI1ENT = -07%1 C
TYP TEMP
-2
~
a
/
~
~
ii'
>ii'
:;
/
"
I
1
>-
/
~
~
;;
1
>-
ia
/
u
"inz
-
VALID ONLY IF~~ Vao ~ sv
.3
~
Typical Input Pull-Up
Characteristics
1/
13v
IVOD
I
~
::>
~
~
-4
~
>-
II
-6
Voo ,,3 v
~
;;
J
-
TA' 25 C
TYP TEMP COEFFICIENT'
I
-6
~
Vao
V
1--"-
5V
-
07%/ C
-8
-4
·6
XTAL INPUT VOL TAGE IV)
Voo - SUPPL V VOL lAGE (V)
-6
VIN
Typical Input Pull-Down
Current vs Supply
Voltage (MIS. FOll
Typical Input Pull-Down
Characteristics .
-2
-4
INPUT VOLTAGE IVI
Typical Chip Enable Sink
Characteristics
160
TA'" 25 C
TYP TEMP COEFFICIENT = -1 0%/ C
~
/
I
~
I-- - - .
-
~0:
I
L
il
z
/
V
'"
I
ii'
>ii'
r
0
0
I--
/
1
>-
~
a
"2
in
~
~
II
TA = 25 C
TYP TEMP COEFFICIENT
140
E
TYP TEMP COEFFICIENT" -10%/ C
-
-071 C
vooJ",SV-
100
80
:;'"
60
5
40
E
20
~
.I
0
IY
VIN - INPUT VOLT AGE IV)
.CD...
"o
I
VOO ,,3V
3
3
0
Vao - SUPPL Y VOL rAGE (V)
-CD
/
I
o
~
120
w
~
Voo" 3V
~
TA = 25 C
o
Voo = 5V
f-
CHIP ENABLE INPUT VOLTAGEIVI
c
-.
a"
:I
Typical Chip Enable Source
Characteristics
TA" 25 C
I-
:;
0:
tr:
-40
w
U
-60
5l"
_80
"u
TYP TEMP COEFFICIENT" -03%/ C
-20
/
~ -100
:;
a.. -12Q
I
/
II
-160
-8
VDO
V
I
/
V
I'"
z
z
E
-4
Voo ~ 5 V
I
-2
(V)
;;
!
>-
~
az
~
0
Z
Z
~
CHIP ENABLE INPUT VOL rAGE
-T+-
w
5
j5V
-6
/
=
/
1/
~
5 -140
bl
TA" 25 C
TYP TEMP COEFFICIENT
I
I./'
Vao" 3V
0:
Typical Output P-Channel
Drain Characteristics
(DP. MIl
Typical Output N-Channel
Drain Characteristics
(DP. M II
o
IVDDI'3V
-2
./
-4
-Voo=5V
r"""": V
...
-.
o
V
:I
1ft
/
./
z
z
vool~ 3 v
1/
~
5
-6
~
TA = 25 C
TYP TEMP COEFFICIENT = -02%1 C
~
E
f-
-B
o
-8
Vos - DRAIN TO SOURCE VOL TAGE IV'
Siliconix
-6
-4
-2
Vos - CRAIN TO SOURCE VOLTAGE IV)
2·15
Table 1
PIN FUNCTION
OESCRIPTION
vOO
OP
Positive voltage supply
Ml
Mask 1 (Buffered Output):= Logic "'" dunng Dialling Sequence
MIS
Mark/Space (Break/Make) RatLo select. On-chip active pull·down to VSS
Dial Pulsing Output Buffer
I O/C
vOO
FOI
I
2.1
3.2
I
Note DIG
=
Open
Circuit,
see Figure 7.
Impulsing Rate Selection On-chip active pull·down to VSS.
FOI
Nominal
Impulsing Rate
OIC
vOO
Actual·
System
Impulsing Rate
Clock Frequency
10 Hz
932 Hz
10 13 Hz
932.17 Hz
3039Hz
27.965.1 Hz
• Assumes felK = 3.579545 MHz
CE
Chip Enable Input/Output, left open It IS lOternally controlled by keyboard decode logIC Can be externally forced for manually
enabling chip
XTAL
IN
Crystal Input. Active. clamped low If CE = "0", high Impedance If CE = "1"
XTAL OUT
Crystal Output Buffer to drive crystal. CapaCitive load on·chlp
VSS
System ground
X,. X2. X3
Column keyboard mputs havmg active pull-ups to VOO Active LOW.
Y,. Y2. Y3. Y4
Row keyboard Inputs haVing active pull-ups to VDO. Active LOW
FUNCTIONAL DESCRIPTION
1.0 Clock Oscillator - The on-chip oscillator amplifier is
connected between the XTAL IN and XTAL OUT pins.
The oscillator is completed by connecting a 3,579,545 Hz
crystal in parallel with a 10M n resistor between XTAL IN
and XTAL OUT. When CE = "0" an N-channel transistor
clamp is activated, disabling oscillator operation. On the
transition of CE to logic "1" a fast oscillator turn-on circuit
kicks XTAL IN voltage to the amplifier bias point allowing
oscillator operation within 4 ms. The basic clock frequency
of 3.58 MHz is predivided by a programmable counter to
provide the chip system clock.
CE is primarily controlled by a logic gate with function
F= KEYBOARD INPUT+Ml
where + denotes logical OR.
It is also possible to control the D F328 from an external
clock applied to XTAL IN.
To operate this gate, a resistor and capacitor should be
connected in parallel between CE and VSS. When the chip
is used in the CE INTERNAL CONTROL MODE power ON
reset occurs when V DD is applied, since a logic "0" appears
on the CE pin. The chip remains in the static standby condition until it receives the first keyboard input after V DD is
applied. This is decoded and causes CE = "1", hence
enabling the clock oscillator. The debounce counter is then
clocked by the system clock until the valid data condition
is recognized. Data is then written into the on-chip RAM.
CE is maintained at logic "1" by M1 during dialling.
2.0 Chip Enable, CE - The Chip Enable pin is used to
initialize the chip system. CE = "0" forces the chip into the
static standby mode. In this mode the clock oscillator is
OFF, internal registers are reset with the exception of the
WRITE ADDRESS COUNTER and the circuit is ready to
receive a new number or re-dial. While CE = "0" data cannot be received by the chip, but data previously entered
and stored is maintained. When CE = "1" the clock oscil·
lator is operating, the internal registers are enabled, and
data can be entered from the keyboard up to a maximum
of 20 digits.
The WRITE ADDRESS COUNTER is reset on recognition
of the first valid debounced keyboard input provided that it
is decoded during td of the pre-impulsing pause PI P (see
Figure 8). In the CE INTERNAL CONTROL MODE this
condition will always apply. When all keyed digits have
been dialled, Ml goes to logic "0" and hence the chip
returns to the static standby condition. If digits are sub·
sequently keyed during the same OFF·hook period, after a
pause in dialling for example, the digit string will be recog·
nized as a new number. This is not important provided
RE·DIAL operation is not required.
As an alternative, an LC oscillator can be formed as shown
in Figure 14. Selection of fCLK = 38.4 kHz with FOl
connected to V DD will give an impUlsing rate of 10 Hz.
2·16
Silicanix
FUNCTIONAL DESCRIPTION (Cont'd)
The alternative to the CE INTERNAL CONTROL MODE is
to override the internal logic gate with an externally derived
signal. This mode of operation is referred to as the CE
EXTERNAL CONTROL MODE. Figure 7 shows that if CE
goes to logic "1" in the absence of a keyboard input, a
single pulse of duration ttd is generated on Ml. This pulse is
intended to initialize a bistable latching relay used as shown
in Figure 12. Immediately prior to Ml going to logic "1",
the WRITE ADDRESS COUNTER is reset. All digits keyed
subsequently are entered into consecutive RAM locations
up to a maximum of 20. After the WRITE ADDRESS
COUNTER has been reset, the RE-DIAl input code will
not be recognized by the circuit. It is necessary that CE be
maintained at logic "a" > 1 J.!.s after V DD is applied in
order to ensure correct system initializing. If CE is linked to
V DD by the method shown in Figure 12, adequate delay is
obtained.
3.0 Data Entry - Data is entered to the circuit via a double
contact keyboard connected as shown in Figure 10.
Keyboard inputs are active low and encoded as shown in
Table 2.
Keyboard inputs are fully decoded eliminating any possibility of invalid codes being recognized. A BCD format is
used on-chip for data storage. Val id inputs have contact
bounce removed via the debounce counter. Operation is
illustrated in Figure 9. Input data is not written into the
RAM until the input code has been present for a minimum
of 3P and maximum of 4P (P = System Clock Period). The
1P uncertainty arises since data entry is not synchronized
to the system clock. This is indicated by the shaded area on
the keyboard entry waveform of Figure 9. The trailing edge
of a keyboard entry is also debounced. The operation of
the debounce circuitry results in a maximum data entry
rate of SYS ClK 7 9. Referring to Figure 9, data must
remain stable during the RAM data entry period. Maximum
VDD
---1r-,-----,
---1
ENTRY
---1
No. of O/P
Pulses
V-
'-----'
'd'd-
NOTES:
III td=10xP
P = System clock period = T130
T is selected impulsing period
Yl
Y2
Y3
Y4
Xl
X2
X3
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
2
3
3
4
4
5
6
5
6
7
7
8
9
10
8
9
1
O·
RE·DIAL
NOTE:
"a"
0
1
0
1
1
1
0
1
0
1
0
1
0
indicates pin taken low.
contact bounce rejection is 10 ms at 10 Hz impulsing rate.
Minimum data valid time is 16.7 ms a~ 10 Hz impUlsing
rate.
Upon recognition of the first keyboard input of a number
string, the dial out sequence is initiated by a pre-impulsing
pause (Figure 7). The WRITE ADDRESS COUNTER is
incremented on each digit entry. The contents of this
counter indicate the length of the number to be dialled.
The RE-DIAl code is recognized only if it is presented to
the chip a maximum of 5P after CE = "1". Decoding of
RE-DIAl then inhibits the reset of the WRITE ADDRESS
COUNTER, initiates the dialling sequence and the previous
number string entered is dialled. If the circuit application is
to utilize RE-DIAl, external CE control is necessary in
some cases to ensure that CE = "1" from the first keyboard
entry throughout dialling in order to ensure all digits
entered are stored consecutively should a delay occur
during dialling.
-...
CD
CD
ft
o
3
3
c
_.
~
I
"D
L- ...
-.
ft
ii
-1
~3
DP
td'd~~
Digit
2
v--- ~
Ml
KEYBOARD
Keyboard Code
Table 2
~
II
I
L-
I
4
"-
-I t~
tb
BREAK
~,~~"~",,,
-PIP---
tm
} -L j~"
DIALLING
IDP::8T
DIGIT 31MPULSED
COMPLETE
DIGIT 4 IMPULSED-
PQIP
131 Post· ImpulSIng Pause (POIPI is equal to td ms
(41 tb/tm is Ihe BREAKIMAKE RATIO. T = (1m + Ibl ms.
1m = 10 x P for 2:1 MIS ral,o. 1m = 12 x P for 3:2 MIS rallo.
(21 Pre·lmpulsing Pause (PIP) = aT + Id
Loop Disconnect Dialler Timing Diagram CE-External Control
Figure 7
Siliconix
2·17
o
~
fit
10
"Q...
FUNCTIONAL DESCRIPTION (Cont'd)
COlt
4.0 Dialling Sequence - The dialling or impulsing sequence
is initiated on recognition of the first keyboard entry after
CE = "1 ". The dialling sequence is identical for both
internal and external control of CEo (See Figures 7 and 8).
decode of the OUTPUT COUNTER. A number of dial
pulses is output via DP corresponding to the BCD data read
from the RAM. At the completion of the digit, the READ
ADDRESS COUNTER is incremented. The sequence con·
tinues until coincidence is recognized between the READ
ADDRESS COUNTER contents and the WRITE ADDRSSS
COUNTER contents. The post·impulsing pause POIP, is
then generated. The circuit then enters the dynamic
standby condition if CE is maintained at logic "1" by
external control, or the static standby condition if CE
INTERNAL CONTROL MODE is used.
The basic impulsing pulse train is derived from the TIMING
COUNTER AND DECODE. The lOP is timed by forcing a
code on the OUTPUT COUNTER and inhibiting DP for the
duration of lOP. The READ ADDRESS COUNTER then
addresses the RAM and the first digit is used to program the
,----------------~,------------------~,.~~'----------------------~'.~
vooJ
syse:: -------~~~~~~~-. . .,--------------------------~...=:,
.
-------Ml
.omc=
---+-!
KEVBOARD
ENTRY
NOTE:
111 I, = ION + td where tON = Clock Start Up Time
Loop Oisconnect Oialler Timing Diagram CE-Internal Control
FigureS
SYSCLK _ _ _ _ _ _....
KEYBOARD _ _ _ _ _ _ _ _ _ _ _ _ _ _
ENTRY
CONTACT
NOISE
LJI?$J.........__IUUJ
DATA ENTRY ~
TO RAM
OEBOUNCEO
~
I I
l--'-------,
1
KEYBOARO _________________________.....
ENTRY
'----------
Keyboard Input Debounce Timing Diagram
Figure 9
2-18
Siliconix
\....
a...
APPLICATIONS
w
The circuit of Figure lOuses a minimum number of
components and provides very low current operation.
When the handset is lifted, power is applied through the
diode bridge to the dialer circuit. Current flows through
Dl' CRl and Z2, establishing VDD for the DF328 and
charging Cl' When the minimum operating voltage (VDD)
is reached, power on reset occurs via the CE network of C2
and Rl' Initially, both DP and Ml are LOW,givinga LOW
at the gate of 01 to hold it off, while the HIGH at the gate
of 02 turns it on, connecting the telephone network. The
current limiting diode, CRl serves two purposes. First, it
limits the total dialer circuit current drawn from the loop
to less than 1 mA, and secondly, maintains a high dialer
circuit shunting impedance across the telephone set
network. Zl is a high voltage, high surge capability device
which provides protection against loop transients and office
inductance spikes. The device should limit all transients to
less than the breakdown voltages of CR1, 01 and 02 (100
volts).
On recognition of the first keyed digit, the DF328 clock is
started. Ml then goes HIGH, causing 02 to turn off and 01
to turn on. This mutes the receiver in the network and
allows loop current flow to continue through R3 and 01'
When dial pulse breaks occur, DP will go HIGH, causing G3
output to go LOW and turning off 01' Loop current flow
during breaks is controlled by CR 1.
When dialing is complete, Ml goes LOW causing 01 to open
and the telephone network to be reconnected. The D F328
then returns to the static standby condition and the
oscillator is turned off.
~
co
The diode bridge protects the dialer circuit from line
polarity reversal. Dl prevents rapid discharge of Cl during
makes in dialing if the voltage across R3 and 01 is lower
than the voltage across Cl'
The VMOS devices combine low ON resistance and high
breakdown voltage with very high input impedance. The
high input impedance allows direct drive from CMOS logic
and very low dialer circuit current consumption when
compared to bipolar devices. This is important because of
the wide variation in circuit operating conditions resulting
from the need to accommodate both long and short loops.
Another approach is illustrated in Figure 11. The circuitry
is similar to Figure 10 except for the dailing and muting
functions. During non-dialing periods when the phone is
off·hook, both DP and Ml will be LOW. 02 will be held
OFF by DP, allowing 01 gate voltage to equal the drain
voltage. A bias voltage will exist from gate to source,
keeping it ON and allowing current flow through the
telephone network. 03 is also held OFF by Ml. This in
turn allows ~ and 05 to be ON. Since 05 is in series with
the receiver, no muting occurs.
IEII
...
CD
CD
TIP
'":Io
01
IN4004
RING
CRI
J552(J9100)
I
DP
1
1
1L ___ _
XTAl
IN
-.g::s
'"..._.
I
Jo--c:-f~
1-----;1-+
Mlr----~,---r-~
DF328
:I
c
r----- ------------------,
VDD
1
i
o
I
1
_____~~~ ________ J
:s
1ft
XTAL
OUT
81·183
1
1
1
I
1
1
1
1
1
I
1
1
1
1
1
1
1
1
I
LITI0ITJ
L__
L- ____
IL... _ _ _ _ _ _
KEYBOARD
000
000
G00
DF328 Dialer Circuit Connection
Figure 10
Siliconix
2-19
:!I
~
II.
Q
APPLICATIONS (Cont'd)
When a key is depressed for dialing, Ml goes HIGH, turning
ON 03 and turning OFF 04 and aS, thus muting the
receiver. DP goes HIGH during dial pulse breaks, turning
ON 02 and turning OFF 01. After dial pUlsing is complete,
DP and Ml return LOW, reconnecting the network and
receiver for speech transmission. 01 and 02 should both be
high voltage devices.
If a requirement exists that no semiconductor components
should appear in the telephone loop during normal speech,
the circuit of Figure 12 is required.
While the circuits of Figures 10 and 11 did not require a
common keyboard contact, it is necessary to have a
common changeover switch in this case operating in
conjunction with a bistable relay. In this application
external control of CE is provided by the R1, C2 network.
If, when the handset is lifted, the relay contact is such that
the DF328 network is connected in circuit, it is necessary
to initialize this relay to reconnect the telephone network.
This is achieved by the single pulse which occurs on Ml if
CE goes to logic "1" in the absence of a keyboard input
(Figure 7).
occurs through DP switching 01 OFF which in turn
switches 02. When dialing is complete the bistable relay is
pulsed, switching the telephone network back in circuit and
short circuiting the D F328 network.
Figure 13 shows a simple method of interfacing a single
contact matrix-type keyboard to the DF328. Operation of
a key causes the on-chip pull-up transistor of the Y input to
provide base driver current to the corresponding X input
external bipolar transistor, which sinks the X input pull-Up
current through its collector. Hence, a valid code is
presented.
As an alternative to the crystal oscillator it is possible to
operate the DF328 from an LC combination connected as
shown in Figure 14. FOl is connected to VDD selecting the
932 Hz impulsing condition. An oscillator frequency of
38.4 kHz will give a 10 Hz impulsing rate. High values of
inductance and a should be used to ensure that the loop
gain does not fall below unity. Typical values are given in
Table 3 for F = 38.4 kHz.
Table 3
When the first digit is keyed, the DF328 circuit is
connected into the telephone loop and the telephone
network short circuited by the keyboard common switch.
Ml then goes to logic "1" switching the bistable relay,
hence maintaining the DF328 network in circuit. Impulsing
L
1.718
a
100
C1
0.02
mH
).IF
0.02
TIP
HOOK
SWITCH
"ING
a'
VK1010
o-l1..- ~_.I
'~$
Z, ••
I
I
J552(J9'OOI
",
111-
~
'OOK
I
VOO
~
3·~T
~~
Z2
5.1V
10.F
OP
"2
"'"
02
20K
".
C
'K
"s
~G4
DF32B
XTAL OUT
1
CE
M,
O,02/IF
Vss
220
K
I
1
KEV
BOARD
lOOK
"3
I
DF328 Parallel Telephone Connection
Figure 11
2-20
V
NETWORK
RCVR
,OM
MH,
+
200K
XTAL IN
" ""
Siliconix
V
...... 03
81·184
APPLICATIONS (Cont'd)
HOOK
SWITCH
-/.'-t------,
r--~-IXTAl IN
Voo
D.
g
DF32B
M'I-+--+--;
TELEPHONE
liNE
R,
10K
KEYBOARD
OF328 Bistable Relay Telephone Connection
Figure 12
IEII
....
CD
~~--~~--~-oY,
-
~~--~~--~-oY,
CD
"o
3
3
c
:a
-"a
c,
__---+-0 x,
felK
~---~----4--ox,
.
1
jE'i"+"C2
b';~
LC Oscillator
Figure 14
-o
:a
Single Contact Keyboard Interface
Figure 13
1ft
Siliconix
2-21
.H
Siliconix
Analog Switches _
Index
ANALOG SWITCHES
Title
Page
DG123 .....................................................................................
DG125 .....................................................................................
DG126/134 .................................................................................
DG1291133 .................................................................................
DG139/144 .................................................................................
DG1401141 .................................................................................
DG142/143 .................................................................................
DG145/146 .................................................................................
DG1511153 .................................................................................
DG152/154 .................................................................................
DG161/163 .................................................................................
DG162/164 .................................................................................
DG172 .....................................................................................
DG180-191 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DG200 .....................................................................................
DG200A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DG201 .....................................................................................
DG201A ....................... ......... ......... .................... ......... ......... . ....
DG202 .....................................................................................
DG211 .....................................................................................
DG212 ...................................................... .'..............................
DG243 .....................................................................................
DG281-290 Series ............................................................................
DG300-307 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DG381-390 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DG300A-390A Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DG308 .....................................................................................
DG309 .....................................................................................
DG5040-5045 Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Si3002 ......................................................................................
3-3
3-6
3-9
3-12
3-15
3-18
3-21
3-24
3-27
3-30
3-33
3-36
3-39
3-42
3-48
3-52
3-55
3-58
3-61
3-63
3-69
3-71
3-75
3-79
3-81
3-86
3-90
3-94
3-96
3-101
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) to devices without resulting in
permanent damage. This is a stress rating only and not subject to production testing. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.
Analog Switches
Basic
Part
No.
(Note l'
Switch
Type
Analog
Voltage
Range
IV)
INote 4)
rOSlon)
Max
loloffl
1m
InAI
(Note 41
Switching
Time
(j!sec)
'ON
'oFF
logic Levels
IV)
VINH
VINL
1+)
Sup_
V+
Opt. Supply Voltage
IV)
1-)
logic
Sup.
Sup.
V-
VL
Ref.
Comments
Switch Configuration
Sup.
VR
TWO CHANNEl SPOT
DGl89
N·JFET
+ 10 to - 12.5
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
Plus 40 CMOS
N-JFET
10
10
30
30
75
75
50
300
50
50
50
50
50
50
50
50
DG243
DG290
DG303
DG303A
DG307
DG307A
DG390
DG390A
DG5043
CM05
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
+15to -7.5
+ 10 to - 12.5
+15to-7.5
+ 10 to -15
+ 15 to -10
+15to-15
+15to -7.5
+15to-15
+15to-15
+15to-15
+15to -15
+15to-15
+15to -15
+ 15 to - 15
DG5044
CMOS
+15to-15
DG100
DG191
10
10
1
1
1
1
1
0.2
1
0.3
0.3
0.15
0.15
0.25
0.25
0.5
0.15
0.3
0.3
0.25
0.25
0.3
0.3
1.0
0.25
0.25
0.13
0.13
0.13
0,13
1.0
0,13
0.25
0.25
0.15
0.15
0.25
0.25
0.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
4.0
4.0
11.0
11.0
4.0
4.0
2.0
10
15
10
15
10
15
15
15
15
15
15
15
15
15
15
-20
2
15
-15
TTL Compatible
2.0
2.0
2.0
2.0
2.0
2.0
2.0
4.0
4.0
11.0
11.0
4.0
4.0
2.0
10
15
10
15
10
15
15
15
15
15
15
15
15
15
-20
-15
-20
-15
-20
-15
-15
-15
-15
-15
-15
-15
-15
-15
Break-Before-Make
15 V Supplies
Break-Before-Make
15 V Supplies
Break-Before-Make
15 V Supplies
Break-Before-Make
low Power, TTL In
Low Power, TTL In
Low Power, CMOS
low Power, CMOS
Low Power, DGl84
low Power, DGl84
O.B
O.B
O.B
O.B
O.B
O.B
O.B
O.B
0.8
O.B
3.5
3.5
O.B
O.B
O.B
-15
-20
-15
-20
-15
-15
-15
-15
-15
-15
-15
-15
-15
-15
Break-Before-Make
15 V Supplies
Break-Before-Make JAN/l1107
15 V Supplies
Break-Befere-Make JAN/l1108
15 V Supplies
Make-Before~Break IOG19' Pin Out)
Break-Before-Make
Low Power, TTL In JAN/11604
Low Power, TTL In
Low Power, CMOS In JAN/11608
Low Power, CMOS In
Low Power, DGl90 Pin Out
Low Power, DGl90 Pin Out
2 SPOT Switches per Package
~'"-<>~'"-<>
~~
o-O-t>-J
o-O-t>-J
ONE CHANNEL DPST
U1
rr0
::J
)C'
1.0
0.5
O.B
1 DPST Switch per Package
TWO CHANNEL DPST
DGl83
DGl84
DG185
DG284
DG302
DG302A
DG306
DG306A
DG3S4
DG384A
DG5045
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
+10to -12.5
+15to-7.5
+10to-12.5
+15to -7.5
+10to -15
+15to-1O
+15to -7.5
+15to -15
+15to -15
+15to -15
+ 15 to - 15
+15to-15
+15to -15
+15to-15
10
10
30
30
75
75
300
50
50
50
50
50
50
50
10
10
1
1
1
1
0.2
0.3
0.3
0.15
0.15
0.25
0.25
0.15
0.3
0.3
0.25
0.25
0.3
0.3
1.0
0.25
0.25
0.13
0.13
0.13
0.13
0.13
0.25
0.25
0.15
0.15
0.25
0.25
0.5
O.B
O.B
O.B
O.S
O.B
O.B
O.B
O.B
O.B
3.5
3.5
O.B
O.B
O.B
2 DPST Switches per Package
~"-<> ~"-<>
~'"-<>
In
In
Pin Out
Pin Out
o-O-t>-J
0-----1"-<>
o-O-t>-J
NOTES:
1. The devices shown in boldface ate recommended parts for new designs.
2. The appropriate switching characteristic for multiplexers is tTRANSITION' not tON. tOFF.
3. VREF = 1.5 V is used when supply voltages < ± 15 V are used. Not needed when supply voltages of ± 15 are used.
4. Analog voltage range is a function of supply voltages. Where a FET switch is PMOS or CMOS, rDS is also a function of Supply Voltage and Analog Voltage. See individual data sheets for more detail. Values
shown are for temperature suffix A.
5. DeVice normally operates with resistor to + 10 V.
~
saq)i!MS 60IDU"
II
ap!n9 JOI)alas I)npOJd paJJafaJd
Preferred Product Selector Guide
c.>
r\,
Analog Switches (Cont'd)
Basic
Part
No.
INote1)
Switch
Type
Analog
Voltage
Range
IVI
(Note 4)
rOSlonl
Max
IDloff)
Switching
Time
101
InAI
(l4sec)
(Note 4)
tON
toFF
Opt. Supply Voltage
IVI
logic Levels
IVI
VINl
1+1
I-I
Sup.
Sup.
Logic
Sup.
Ref.
Sup.
V+
V-
VL
VR
2
15
-15
TTL Compatible
2.0
2.0
2.0
2.0
2.0
2.0
2.4
2.4
2.0
4.0
4.0
11.0
11.0
4.0
4.0
2.0
10
15
10
15
10
15
15
15
15
15
15
15
15
15
15
15
-20
-15
-20
-15
-20
-15
-15
-15
-15
-15
-15
-15
-15
-15
-15
-15
Break-Hefare-Make
15 V Supplies
Break-Hefare-Make
15 V Supplies JAN/11101
Break-Before-Make
15 V Supplies JAN/l1102
2.4
2.4
2.4
2.4
2.4
11.0
11.0
15
15
15
15
15
15
15
-15
-15
-15
-15
-15
-15
-15
2.0
2.0
2.0
2.0
2.0
2.0
2.0
4.0
4.0
11.0
11.0
4.0
4.0
4.0
10
15
10
15
10
15
15
15
15
15
15
15
15
15
-20
-15
-20
-15
-20
-15
-15
-15
-15
-15
-15
-15
-15
-15
V 1NH
Comments
Switch Configuration
SINGLE CHANNEL SPST
DG504II
Pfus40 CMOS
+15to -15
1.0
50
0.5
0.8
1 SPST Switch per Package
lWO CHANNEL SPST
DGl80
N-JFET
+ 10 to -12.5
-+ 10 to - 7.5
10
10
DG181
N-JFET
+ 10 to -12.5
30
30
DG1B2
N-JFET
DG20D
DG300
DG300A
DG304
DG304A
DG381
DG3B1A
OG5041
CMOS
Plus 40 CMOS
N-JFET
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
Plus 40 CMOS
+10to -7.5
+10to -15
+10to -10
+15to -15
+15to -15
+15to -15
+15to -15
+ 15 to - 15
+ 15 to ~ 15
+15to -15
+ 15 to -15
+15to-15
+ 15 to - 15
75
75
70
70
300
50
50
50
50
50
50
50
DG201
OG201A
DG202
OG211
OG212
DG308
DG309
CMOS
Plus 40 CMOS
Plus 40 CMOS
Plus 40 CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
of 15 to
+15to
+15to
+ 15 to
+1510
+15to
+ 15 to
175
175
175
175
175
100
100
OG200A
DG2S1
IP.
n'0
:J
)C'
10
10
1
2
0.2
1
0.3
0.3
0.15
0.15
0.25
0.25
1.0
1.0
0.15
0.3
0.3
0.25
0.25
0.3
0.3
1.0
0.25
0.26
0.13
0.13
0.13
0.13
0.5
0.5
0.13
0.25
0.25
0.15
0.15
0.25
0.25
0.5
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
3.5
3.5
0.8
0.8
0.8
(Note 3)
JAN!l23OJ
TIL In
Low Charge Injection
Low Power, TIL In JAN/11601
Low Power, TIL In
Low Power. CMOS In JAN/11605
Low Power, CMOS In
Low Power. OGle1 Pin Out
Low Power, OG181 Pin Out
TIL Compatible
2 SPST Switches per Package
~"-O ~"-O
<>-Q-t>-J
<>-Q-t>-J
FOUR CHANNEL SPST
-15
-15
-15
- 15
-15
-15
- 15
1.0
1.0
1.0
0.5
0.6
0.2
0.2
0.5
0.5
0.5
0.4
0.45
0.15
0.15
0.8
0.8
0.8
0.8
0.8
3.5
3.5
(Note 3)
JAN/l2304
TIL In
TILln
Low Cost, TTL In
Low Cost, TTL In
Low Cost CMOS In
Low Cost CMOS In
4 SPST Switches per Package
~"-O
~"-O
<>-Q-t>-J
<>-Q-t>-J
~"-O ~"-O
<>-Q-t>-J
<>-Q-t>-J
ONE CHANNEL SPOT
OGl86
OG187
OG188
DG2B7
DG301
DG301A
OG305
OG305A
OG387
DG381A
DG5042
N-JFET
N·JFET
N-JFET
N-JFET
N-JFET
N-JFET
N-JFET
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
Plus 40 CMOS
CMOS
+ 10 to -12.5
+ 15 to -7.5
+ 10 to -12.5
+15to -7.5
+ 10 to -15
+1510-10
+1510 -7.5
+15to-15
+15to -15
+ 15 to - 15
+ 15 to - 15
+ 15 to - 15
+15to -15
+ 15 to - 15
10
10
30
30
75
75
300
50
50
50
50
50
50
50
10
10
1
1
1
1
0.2
1
1
1
1
1
1
1
0.3
0.3
0.15
0.15
0.25
0.25
0.15
0.3
0.3
0.25
0.25
0.3
0.3
1.0
0.25
0.25
0.13
0.13
0.13
0.13
013
0.25
0.25
0.15
0.15
0.25
0.25
0.5
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
3.5
3.5
0.8
0.8
0.8
Break-Before-Make
15 V Supplies
Break-Before-Make
15 V Supplies JAN/11105
Break-Before-Make
15 V Supplies JAN/l1106
Break-Before-Make
Low Power, TTL In JAN/11602
Low Power, TTL In
Low Power, CMOS In JAN/11605
Low Power, CMOS In
Low Power, OG187 Pin Out
low Power, DG187 Pin Out
TTL Compatible
NOTES,
1. The devices shown in boldface are recommended parts for new designs.
2. The appropriate switching characteristic for multiplexers is tTRANSITION, not tON, tOFF'
3. VREF"" 1.5 V is used when supply voltages < ± 15 V are used. Not needed when supply voltages of ± 15 are used.
4. Analog voltage range IS a function of supply voltages. Where a FET switch is PMOS or CMOS. rOS is also a function of Supply Voltage and Analog Voltage. See individual data sheets for more detail. Values
shown are for temperature suffix A.
5. Device normally operates with resistor to + 10 V.
1 SPST Switch per Package
~"-O
o------r'-o
<>-Q-t>-J
5-Channel SPST PMOS
Switches with Drivers
..
ell
H
Q
Siliconix
t-.:»
W
i
designed for .
• •
BENEFITS
•
Minimizes Standby Power Requirements
o 550/..f.W
• Communication Systems
•
• Portable, Battery Operated Units
Low Leakage
o ,,;;; 1 nA
•
• Make-Before-Break Switching
i.e. Feedback Resistor Switching
in Variable Gain Op-Amps
Reduces External Component Requirements
o Internal Zener Diodes Protect All MaS
Gates
DESCRIPTION
The DG 123 contains five MaS field·effect transistors designed to function as electronic switches. Level·shifting drivers
enable a low·level input (004 to 1.3 V) to control the ON·OFF condition of each switch. In the ON state each switch can·
ducts current equally well in either direction, and in the OFF state the switches will block voltages up to 20 V peak·to·peak.
In the OFF state, total circuit power dissipation is < 0.5 mW. Positive logic "1" at the input turns the switch ON. Switch
action is make·before-break. Not recommended for new designs.
FUNCTIONAL DIAGRAM
SCHEMATIC
V+
V+
11
s, ~
DIAGRAM
l====::::r====::::;:::~3D
.......- - - 1
lEI
82 <'>+----+-0-'1
83'O'·+-----+-+~
3>
8.''''3+-_ _ _-+-+-+-o/i
85'0:2+-_ _ _-+-+-+--+-0'1
~
+--.-'"
-
5
IN, 0.
D
6
IN 2 <>+-+-<.......
o
ca
CIt
...--~
ft
::r
CD
fit
SWITCHES CLOSED FOR LOGIC "1" INPUT
(POSITIVE LOGIC)
PIN CONFIGURATIONS
Flat Package
Dual·ln·Line Package
D
F=---'=~:- 53
5.
55
v-
v+
52
8,
IN,
V R (INHIBIT)
IN2
1N5
IN3-~::5'7'--;=~- IN.
,
lOP VIEW
ORDER NUMBER:
DG123AL
SEE PACKAGE 5
ORDER NUMBERS:
DG123AP OR DG123BP
SEE PACKAGE 11
Siliconix
V-
D
3·3
ABSOLUTE MAXIMUM RATINGS
...... . . . ...
........ ... .
VstoV-. ... . .......... . ....... . . ...
VD to VS· ....• ................ . ..... .
Vs to VD· . . . . . ........ . ....... . ., ....
VR to V-.... . . ......... ....... . . .....
VIN to V- . . . . . ................ . ......
VR to VIN ... . . ................ . ..... .
VIN to VR . . . . . ...................... .
V+to V- . . . . . . . . . . . . . . . . .
VD to V- . . . . . . . • . . . . . . . . .
36V
36V
36V
25 V
25 V
30V
30 V
6V
2V
Current (Any Terminal)
. ................. 30mA
.............. -65 to 150°C
Storage Temperature .
Operating Temperature (A Suffix) . . . . . . .
(6 Suffix) . . . . . . .
'Power Dissipation*
-55 to 125°C
-20 to 85°C
. .....................
. .....................
Flat Package"
14 Pin DIP'"
750mW
825mW
• All leads soldered or welded to PC board .
"Derate 10 mW/oC above 75°C .
"'Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
A SUFFIX
B SUFFIX
_55°C
25°C
125°C -20°C
25°C
85°C
100
100
125
125
125
150
200
200
250
225
225
300
450
450
600
500
500
600
CHARACTERISTIC
1-2
2
13
1_ 5
Drain-Source
'OSlon)
ON Resistance
Source OFF
4 ~ ISloff)
I- T
5 C 1010ffi
I-H
6
1010n) + ISlon)
9
:~
0
11 N
A
I- M
12 I
I-C
13
14
I~
1-8
16 u
-5
-100
-1
4000
-10
-300
4
4000
10
300
1
1
100
5
5
100
"A
VIN =O.4V
1.3
1
0.3
2
0.8
1.3
1
0.5
2
1
V
liN = 1 rnA
"'
See SWitching Time Test Circuit
Channel ON
Leakage Current
Logic Input Current,
I nput Voltage Low
I nput Voltage, High
Turn·ON Time
Turn-OF F Time
CSloff)
Source OFF
Capacitance
3 Typ'
COloffi
Drain OFF
Capacitance
7 Typ·
Negative Supply Current
Reference Supply
Current
I-p
t~P 1+
Positive Supply Current
18 L 1I-y
19
IR
VO=-10V.VS=10V
VO=VS= 10V
3 Typ'
liN = 1 rnA
VS· 0.10 = 0
Negative Supply Current
Reference Supply
Current
f== 1 MHz
7 Typ'
Typ
Positive Supply Current
IR
nA
pF
Off Isolation
1+
1-
VS=-10V.VO=10V
VIN =O.4V
Drain OFF
y toff
IS'" -1 rnA,
liN = 1 rnA
-1000
Leakage Current
~on
Vo = 10 V
Vo =0
VO=-10V
!l
-1
Leakage Current
7
I IINL
I S N VINH
TEST CONOITIONS. UNLESS NOTEO:
V+ = 10 V. V- = -20 V. VR = 0
UNIT
Vo = 0, IS = 0
RL· 100H. CL ·3 pF
> -50 dB at 5 MHz·
3
-6
3
-6
-0.5
-0.5
15
-20
25
-40
-10
-20
rnA
liN
"A
VIN "" 0.4 V, All Channels OFF
= 1 rnA,
One Channel ON
IBAF-A+ MABA
"Typical Values are for DESIGN AID ONL Y. not guaranteed and not subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
V+
LOGIC "," = sw. ON
LOGIC
INPUT
t r <10ns
tf<10ns
SWITCH
INPUT
SWITCH
OUTPUT
3·4
2.4 V
0--'
VS =+10V
'--LOGIC
Vs
0.•
0-
-
f-1
'0.
D.'
f-
-
~
S
-'
1.2V"'j
?'OV
SWITCH
INPUT
1.6K .\1
~
.60v
V
toft
=V
V
o
Siliconix
Va
2K.\1
35.F
.~,
(REPEAT TEST FOR 5 CHANNELS)
-20V
R
SWITCH
OUTPUT
J: l~L
c[
I
IN,
'~i
D
V-
R_L__
__
8 RL + '08(on)
TYPICAL CHARACTERISTICS
rDS(on) vs V D and
Temperature
~
e:I: 'K
u
"'
b-
~
V+'" lOV
V • 20V
• TEST 12S"C
• TEST -55"C
AND 25"C
12S"C
10
"- ;::: ::::t::: ~ :-:-
u
_25°C
is
~
100
-
a:
::I
'-
iil
,/
~,
eS(etf)
-
u
;;
a:
,
o
C
.2.
o
10
-10
-10 -8 -6 -4 -2
'0
VOlV s - DRAIN/SOURCE VOL lAGE (VOL IS)
L
-----
/'
..-'
Vo '" +10 V
BOO
toft
r-r
)
)
'on
L
,..VO --l0V
~
~
,
RC times.
5
25
45
65
'OV
o
~
§
>
/'
i-": I--"
a:
vo -
~
siolf)
(B
a:
1.0
25
45
65
B5
T - TEMPERATURE
"
I
3.0
~
~ 0.6
"ill
E.
i-
I I
,
V
z
.::- 0.2
/
0.2
V /
0.4
I
O.B
0.6
~
2.0
u
1.5
,
II-we
LOGIC INPUT
-0.4
SUFFIX~ ~
105
I
125
II
rei
.....
" ...... r---
-- I
I
-..!.i:
-- -.!f-.II
1.0
'R
o
-60 -40 -20 0
V,N - LOGIC INPUT VOLTAGE (VOL lS)
20
40
60
BO 100 120 140
-2
~
I'
V GEN =+5V
-2
I
" r-...
2.5
::I
II I J
/
g
,g;
ZU
:>
Supply Current vs
Temperature
3.5
J
0.4
0.1
85 105 125
II_25~c
::I
O.B
~a:
- 'stoffl (A SUFFIX)
I
'25"C
Ui-
az
OW
'"
4.0
1.4
1.6
1.2
~«
!!:.§.
'CioffI (A SUFFIX) :T
10
liN vs VIN and Temperature
u
If RGEN. RL or CL is increased. there will
be proportional increases in rise andlor fall
i::1_
"'
'.B
i-
10
'0(011) (B SUFFIX) .
T - TEMPERATURE (OC)
illa:
8
100
~
:g;
Vo -+l0V ..........
-55 -35 -15
I-
G
i-
~II:
El
r-
.-
200
1
4
! 1000
100Q
400
2
ID(off)/IS(off) vs
Temperature
1200
>=,
0
VO/VS - DRAIN/SOURCE VOLTAGE (VOLTS)
Switching Time vs V D
and Temperature
~ 600
I
lO']ff)
~
-:wc
z
.e
switching transients in this circuit.
'2
~
a:
Typical delay. rise. fall. settling times. and
Capacitance vs VD
III
J>
I,
:::I
-
a
o
V GEN =+1 V
-4
0
~
CD
"'
«
:;"
0
>
~
,
::I
0
en
...--~
l
i-
-2
V GEN - OV
-4
":::r"
>0
CD
T - TEMPERATURE roC)
1ft
"OFF" Isolation vs RL
and Frequency
-2
'00
~
z
>=
S
70
~
60
tt:
50
P
40
-'-
30
'j,
20
""
10
~
::;,
...
-4
,
11111111
11111111
BO
0
VGEN=-lV
11111111
90
I.......
RL'" 100
lli
"NJ
RL'" lKn
n
-2
SIGNAL
SOURCE B
-4
Z=500
I
-6
VGEN--SV
.....
L1L
III
III
L
-B
"OFF" ISOLATION @ 20 LOG JV1NJ
IVLJ
A - DRAIN OF "OFFHSWITCH
B - SOURCE OF "OFF" SWITCH
t-TIME (/-Is)
f - FREQUENCV (Hz)
Siliconix
3·5
e 5-Channel SPST PMOS
H
Silicanix
8 Switches with Drivers
designed for .
• •
BENEFITS
• Communication Systems
•
Minimizes Standby Power Requirements
• Portable, Battery Operated Units
•
Low Leakage
o .;; 1 nA
• Make-Before-Break Switching
i.e. Feedback Resistor Switching
in Variable Gain Op-Amps
•
Reduces External Component Requirements
o Internal Zener Diodes Protect All MOS
Gates
o 550llW
DESCRIPTION
The DG125 contains five MOS field-effect transistors designed to function as electronic switches. Level-shifting drivers
enable a low-level input (0.4 to 5 V) to control the ON-OFF condition of each switch. In the ON state each switch conducts
current equally well in either direction, and in the OFF state the switches will block voltages up to 20 V peak-to-peak. In
the OFF state, total circuit power dissipation is < 0.5 mW. Positive logic "1" at the input turns the switch OFF. Switch
action is make-before-break. Not recommended for new designs_
FUNCTIONAL DIAGRAM
SCHEMATIC DIAGRAM
V+
11
8,~2+=======~~~====~~3D
8 0-'+------i-o'l ~---;
4 +-_ _ _-+-+....-:
3'3
:'0:-
84,0-2+------i-+-j.--~
..
8.~.t-=--=.~---+-+--!--j-o'1
IN1V""
9
IN. <>-1-+-0..-....
SWITCH STATES ARE FOR LOGIC "1" INPUT
(POSITIVE LOGIC)
PIN CONFIGURATIONS
Flat Package
82
Dual·ln-Line Package
===;:::::ii~~~=:=' 83
8,
S4
85
v-
V+
IN,
VL !ENABLE)
IN2
IN.
IN3~=--""~
,
IN4
TOPVIEW
ORDER NUMBER: DG125AL
SEE PACKAGE 5
3-6
ORDER NUMBERS:
DG125AP OR DG125BP
SEE PACKAGE 11
Silicanix
v-
ABSOLUTE MAXIMUM RATINGS
..
V+toV-.
vD to V-.
Vs to V-.
VD to VS·
Vs to VD .
VL to V-.
VIN to V....
VL to VIN
Current (Any Terminal)
..
..·. ·.
..
..
· . ·.
·. · .
..
..
36 V
36 V
36 V
25 V
25 V
30 V
30V
6V
30mA
Storage Temperature . . ........ . . ... -65 to 150°C
Operating Temperature (A Suffix) ..
-55 to 125°C
(B Suffix) ..
-20 to 85°C
Power Dissi pation'
Flat Package" . ..
..
..
750mW
14 Pin DIP'" ...
..
..
825mW
'All leads soldered or welded to PC board.
"Derate 10 mW/oC above 75°C .
"'Derate 11 mW/oC above 75°C .
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
A SUFFIX
'OSlon)
125
125
125
150
200
250
225
225
300
450
600
500
500
600
Source OFF
Leakage Current
-1
-1000
-5
-100
Drain OFF
Leakage Current
-1
-4000
-10
-300
4
4000
10
300
-0.7
-0.7
-1
-1
-1
mA
VIN =0.5V
10
'10
'10
'10
"A
VIN =4.1 V
"'
See SWitching Time Test Circuit
ON Resistance
3 S
-w
-
4
~
ISloft)
-
Logic Input Current,
Input Voltage Low
·0.7
Logic Input Current,
Input Voltage High
±1
"
Turn-OFF Time
toft
N
11 A CSloff)
_M
14
450
Turn-ON Time
10
y
-
~
200
Leakage Current
9 D ton
12
100
Channel ON
1010n) + ISlon)
7
IINL
_I
N
S
IINH
- 13
100
COloft)
!
0.3
0.5
2
2
Source OFF
Capacitance
3 Typ'
Dram OFF
Capacitance
7 Typ*
VIN =0.5V
VO=-10V
Vs = -10 V. VD = 10 V
nA
VO=-10V.VS= 10V
VIN =0.5V
VO=lOV.IS=O
Typ
Off Isolation
> -50 dB at
IEII
VS=O.IO=O
f = 1 MHz
~
::I
VO=O.IS=O
7 TVp"
5 MHz'
a
o
ca
-
RL = 100H. CL = 3 pF
3
3
15 U 1-
Negative Supply Current
-6
-6
IL
LogiC Supply Current
3
3
lay
1+
PositLve Supply Current
15
25
1-
NegatLve Supply Current
-20
-40
19
IL
Logic Supply Current
10
20
o~
Is=-lmA,
Vo =0
pF
PosItive Supply Current
1e P
Vo = 10 V
H
3 Typ'
1+
-s
85"C
VIN =4.1 V
C
5 H IOloft)
6
125"C
TEST CONDITIONS. UNLESS NOTED:
V+ = 10 V. V- = -20 V. VL = 4.5 V
25"C
Drain Source
25"C
UNIT
-20"C
1
2
B SUFFIX
-55"C
mA
V I N = 0.5 V. One Channel ON
"A
VIN '" 4.1 V, All Channels OFF
.
CIt
-.~
"::r-
IBAF·B + MABA
*Typical Values are for DESIGN AID ONLY, not guaranteed and not subject to productLon testing.
CD
fA
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs ~ constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
~~~J~ 45V~
"
'f
.,--50%
10ns
10ns
0
~~~!~~
0
Va
--
~
'00
0.'
1--
--
Va
IN,
.....r::
I
~
n VO~VS
0.'
_
toff
?lOV
?-45V
swnCH
INPUT S
Vs" +10 V
lOGIC
INPUT
SWITCH
Vs
INPUT
v.
VL
lOGIC "0" '" SWaN
__
R_L_.~
Rl + fOS(onl
·20
V-
D
SWITCH
OUTPUT
R'~l ~CL
2K"_
1
35
Va
"
v
~
(REPEAT TEST FOR 5 CHANNElS)
Siliconix
3·7
TYPICAL CHARACTERISTICS
rDS(on) vs VD and
Temperature
~
§
Capacitance vs V D
lK
v+ 10V
V '" 20V·
• TEST 12SD C
• TEST _55D C
AND 25D C
w
~
~
iiia:
isw
100
Ii
g"
125"c
10
~Ollff) l"Y
I"-.. ~ ::=i=:: ~ l--25°C
1"--
=
-
1= =~wc
2
cSloff)
"
a:
c
I
'C
S
~
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
12
o
10
10
-10
-10 -8 -6 -4 -2
0
2
4
6
8
10
vaNs - DRAIN/SOURCE VOLTAGE (VOLTSI
VrYVs - DRAIN/SOURCE VOLTAGE (VOL TSI
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
Switching Time vs VD
and Temperature
I D(off)/IS(off)
vs Temperature
1 1000
1600
~
1400
1200
a~
/'
:g 1000
vD=+10~
I-- -
/'
'off
w
::E 800
"!
RC times.
V
./
/'
ICloff) (B SUFFIX)
IDloff) (A SUFFIXI:1
~
./
VO -
w
~
10V-
:;""
100
w
0
>-
10
>
"~ ~
I
600
VO=-10V
I-ton
200
u
j
b=
400
a:
o
Vo=+10V
E
5
25
45
65
~ Stoff) (B SUFFIX~ ~
-ISloff) (A SUFFIX)
85 105 125
-
~
t
-I
o
-55 -35 -15
v: ,/'
,
0.1
25
45
65
85
105
125
T - TEMPERATURE (CC)
T - TEMPERATURE 1°C)
4.0
.§.
f-
""
1.5
I
...... ...... .....!,-
2.5
2.0
a:
I
.......
3.0
:'ia:
......
-2
I
.....
~
~
1.0
--==f
~
-60 -40 -20 0
I~
20 40
If
VGEN=+lV
-4
0
~
w
"
;!
F-
5>
f-
~
I
o
VGEN=+5V
-2
I
\
3.5
:\..
II
Supply Current vs
Temperature
;;
I-
f-
V
"
0
60 80 100120 140
I
-2
I
!f
VGEN- OV
-4
0
>
T _ TEMPERATURE 1°C)
"OFF" Isolation vs RL
and Frequency
100
Oi
:;!
2
0
"S~
~
70
50
P
-~
30
I
-2
~-
.......
.(
60
40
~
...
rn
"NJ.
10
III
III
III
VGEN '" -1 V
-4
RL -loon
RL = lKn
20
-2
11111111
11111111
11111111
90
80
-2
SIGNAL
SOURCE B
Z = 50n
-4
....
"OFF" ISOLATION
~
20
lOGI~1
VGEN=-5V
-8
IVLI
A - DRAIN OF "OFF" SWITCH
B - SOURCE OF "OFF" SWITCH
108
f - FREQUENCY 1Hz)
3-8
/
I
-6
III
III
III
106
'I
II
Siliconix
t-TIME (/.ls)
2-Channel Drivers with SPSY
and DPSY FEY Switches
designed for .
• •
H
Siliconix
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby .Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
These switching circuits contain two channels in one package; each channel consists of a driver circuit controlling SPST or
DPST junction FET switches. The driver interfaces with DTL, TTL or RTL logic signals for multiplexing, commutating,
and D/A converter applications. Logic "1" at the input turns the FET switch ON, and logic "0" turns it OFF. Switches
have make-before-break action. It is recommended that the DG185 and DG182 be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
Flat Package
,.
v+
Dual-In-Line Package
°2
82
8.
IN2
8.
D.
V-'
D.
NC
V+
NC
D3
V R {ENABLEJ
D3
83
IN,
83
D,
.,
D,
11
D2
IDI
J>
~
a
o
ca
-
TQPVIEW
ORDER NUMBER:
DG126AL
SEE PACKAGE 5
ORDER NUMBERS:
DG126AP OR DG126BP
SeE PACKAGE 11
._.
CIt
~
":::r
CD
Flat Package
82
°2
(II
Dual-In-Line Package
,.
D2
DG126
v-'2
DG134
v-
v+
NC
IN2
NC
NC
V-'
NC
NC
V+
NC
NC
VR (ENABLE)
NC
NC
IN,
NC
.,
D,
D,
11
IN2
TOPVIEW
ORDER NUMBER:
DG134AL
SEE PACKAGE 5
ORDER NUMBERS:
DG134AP OR DG134BP
SEE PACKAGE 11
• Common to Substrate and Base of Package
10
SWITCH STATES ARE FOR LOGIC ","INPUT
Siliconix
V R (ENABLE)
12
3-9
ABSOLUTE MAXIMUM RATINGS
V+toV- .....
V+ to VD .....
VD or Vs to VVD to VS.
V+to VR ..
VR to V-.
VIN to VV+ to VIN
VIN to VR
..
·.
·.
..
·.
·.
·.
·.
·.
.. . · . · .
·.·. ..
·.·. ..
. . ·.
. · .. .
·.
"
·.
·.
..
·.
·.
·.
"
36 V
36 V
36 V
±22 V
25 V
25 V
30V
25V
±6V
Current (Any Terminal) . ........
. .... 30mA
,,5 to 150° C
Storage Temperature . . ........ .
-55 to 125°C
Operating Temperature (A Suffix). ...
(B Suffix) ...... -20 to 85°C
Power Dissipation'
Flat Package'- ... . .................. 750mW
14 Pin DIP'-- .. . . .................. 825mW
'All leads welded or soldered to PC board.
"Derate 10 mW/oC above 75°C.
"*Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25"C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
OG126A.OG134A
CHARACTERISTIC
-SS'C
1
12S'C
SO
150
80
!'2
'OS(on)
Drain-Source
ON ReSistance
13 5
,-w
Source OFF
Leakage Current
1
IS(oft)
ST
'--: C 10(olfi
6 H
Drain OFF
Leakage Current
1
Channel ON
Leakage Current
-2
4 I
17
!"8
10(on) + IS(on)
11
112
1-
15
C
116
17
2S'C
8S'C
100
100
150
5
100
"
Vo
100
IS = -10 rnA,
VIN = 2.5 V'
Vs = S V, Vo = -S V
VIN = O.S V·
5
100
-5
-100
4
4
VO=10V,VS=-10V
Vo=SV,Vs=-SV
-100
2
= 10 V
=S V
VS=10V,VO=-10V
100
0.1
TEST CONDITIONS. UNLESS NOTED:
V+ = 12 V, V- = -18 V, VR = 0
Vo
Vo = Vs = -10 V
4
VIN = 2.5 V'
VO=VS=-BV
VIN = 0.8 V'
"A
120
60
60
150
100
'on
Turn·ON Time
0.6
1
toff
Turn·OFF Time
1.6
2
Source OFF
Capacitance
100
VIN = 2.5 V'
See SWitching Time Test Circuit
"'
2.4 TYPical""
VS= 0, 10= 0
f = 1 MHz
pF
Dram OFF
Capacitance
CO(on) + CS(on)
2.4
Channel ON
Capacitance
1+
I~Y
IR
Typlcal~·
Vo = 0, IS = 0
2.8 Typical" ..
Off Isolation
116 1I-S
19 U IR
I- P
20 P 1+
1- L
122
0.1
Input Current,
Input Voltage HIgh
0
13 Y CS(off)
N
I-A
14M CO(off)
I-I
UNIT
_20 c C
nA
Input Current,
Input Voltage Low
9
IINL
I-I
N
10
IINH
OG126B.OG134B
2S"C
VO=VS=O
RL '" 75 n
Typ:;.. 60 dB at 1 MHz**
Positive Supply Current
3.0
3.3
Negative Supply Current
-l.B
-2.0
Reference Supply
Current
-1.4
-1.5
Positive Supply Current
25
25
Negative Supply Current
-25
-25
Reference Supply
Current
-25
-25
rnA
VIN
"A
Both VIN:: 0*, All Channels OFF
=
2.5 V, One Channel ON
LOOC + NC
*VIN must be a step function with a minimum rise and fall rate of 1 V/lJs.
UTypical Values are for DESI GN AI D ONLY, not guaranteed and not subject to productIOn testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs ~ constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
t r < 10ns
tf< 10ns
SWITCH
INPUT
3V
2.5V
-'
I-
D.•
SWITCH
OUTPUT
3·10
IN,
LOGIC
INPUT
Vs
D-
-
~
'on
n
O.,
I--
-
toff
-=-
10 V A SUFFIX
Vs
Vs - 8 V B SUFFIX
Siliconix
1--
S,
ton.+Vs
loff_' Vs
1'---
0---'
'?VV.
SWITCH
INPUT
LOGIC "1" = SW ON
LOGIC
INPUT
--Q-t>J
6VR
V-6
OV
Vo
-1SV
RL
Vs
~. + rOSlonl
SWITCH
OUTPUT
0,
R~i
Va
J,C L
35
""-=-1
,'
(REPEAT TEST FOR S3
AND 1N2_ S2 AND 5 4 1
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
Capacitance vs V D
r- ~~~~~'~:~~~6SM ~
f'"
~
I--
MHz
's:= 0
TEST TERMINAL
4
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
TO COMMON.
w
<.J
Z
;::
~
"
2 1-+-+-+-+ CO(offJ+-+-+--1t-1-I
<.J
I
<.J
11-+-+-+-+-I-+-+-+-J.-1
o
L-..L--L-L---L_L-..L--L-L---L~
-10 -8 -6 -4 -2
Switching Time vs V D
and Temperature
2
!'000
I .•
~
1.4
j
100
a:
4
6
B 10
111111
::>
1.2
~
~
1
0
~ 0.8
a:
w
iil
I
VD
I
0.2
-55 -35 -15
5
25
45
65
85
4
2
0
-2
9I
V 1N - LOGIC INPUT
z
>'
25
105 125
.5
45
B5
105
T - TEMPERATURE (OC)
T - TEMPERATURE fOCI
VIN vs Temperature
Supply Current vs
Temperature
125
4
W--t..,Jt:::t::::j::u.ll-J
--
~-+++~~~I\~~~~
0f-+-.f--l-:--l--+..,...J...\,.-b.,.j......j.-I
2
-2
~~-L~V~G~EN~··~5_V~__
~L-~-L~
.I-~.,...~~-~~.,...~~--.j
2.• ,-.,...-,-.,........,,-.,...-,-.,...-,
v~. 0 I
V+::: +12 V
2
'"
I---
1
0.1
OL-..L---'-----L_L-..L-...J.----L_'--'
0
~~
i;
ffi
±lOV
~
z
::>
0.•
w
~ ~
10
<.J
0.4
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
o
>-
<.J
w
">=
2
IS(off) vs Temperature
I
I.B
0
Vo - DRAIN VOLTAGE (VOLlSI
T - TEMPERATURE (OC)
1-~~~I-~-I-~-N+-1I--V-' -18 V
<
I
I--f.--
1..---
ffi
1.8
-2
8::~
1.4
~
6
o
ca
I-~~~~-~~~~__--l
."-.
1.0
OJ
is
II
1-I~--.j-4-4-+~~-+-+-1
V GEN =+1 V
~ -4 I-..L-...L-L-""-'-~-L-L---L--l
<.J
If---I-+-t-t---t--+-I-I
~
:s
:~mjjjj
+'t:!.---t=-01-",,*='f--+
E
a:
~
OFF
2.2
CIt
2f-1-+A-+-+-++++-+--l
0.6
~
I
0.2
0'---'---'--1._'---'---'---1.--1
-75
-25
25
75
125
T - TEMPERATURE (OCI
"OFF" Isolation vs RL
and Frequency
-50 -25
0
25
50
75
100
90
il
80
§
'
60
50 1-+H1+H1It-+H-l~:I-+....+ttfI
z
>'
40
o
__-~~~~__--.j
2 1-+-+-~--l---L-I-I--+-+---1
1-+H1+H1I1--'''kH-l+H1+-+....+tHl
V GEN = -5 V
o H--+4+-:;:':':-'--+---IV~--+---I
-2H-+~4-+-~I/~+-~
1-+f+H~-t~TIB~I'-~~~
-. tt!!l:±::t::tt:t:::tj
-4
30
20
10
-: t:!fi=EE£:fftj
41-~~~
70 1-+H1~II-I'--t+HtHtt--t-+1l+HcHl
~
PI
til
-4 1-+-+-+-4--+-+-~-+-4--.j
Li'....:·''kt-ttttHt-l-+ttttttt---t-+l-t+tHl
&:
'i!
CD
2 I-+-~~---L__~L-~-+-+--l
Equivalent "OFF" Circuit
100
~
:s-
125
T - TEMPERATURE 1°C)
-10
v+ '" +12 V. v- = -1a v HfI+-+I-H~
VR ;;O,R L =7S!l
VIN
10
20
30
40
1- TIME !psl
~ 2~~ ~l~ RMS
f - FREQUENCY (Hz)
Siliconix
3·11
=2-Channel Drivers with SPSY
g
H
Siliccnix
and DPSY FEY Switches
designed for .
•
•
•
•
• •
Switching High Frequencies
Switching in Satellite
Applications
Portable, Battery Operated
Circuits
Low Signal Distortion Switching
Circuits such as Audio Switching
BENEFITS
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
• Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
These switching circuits contain two channels in one package; each channel consists of a driver circuit controlling SPST or
DPST junction FET switches. The driver interfaces with DTL, TTL or RTL logic signals for multiplexing, commutating,
and D/A converter applications. Logic "1" at the input'turns the FET switch ON, and logic "0" turns it OFF. Switches
have make-before-break action. It is recommended that the DG184 and DG181 be used for new designs.
SCHEMATIC DIAGRAMS
PIN CONFIGURATIONS
Flat Package
V+
Dual-In-Line Package
8. =:11---,.
_....f'I, .........
0.=:11--r'
11
V_
NC
0a
c:::jJ--,.
V R (ENABLEI
8 a C:::::II--r'
7
8
TOP VIEW
ORDER NUMBERS:
DG129AP OR DG129BP
SEE PACKAGE 11
ORDER NUMBER:
DG129AL
SEE PACKAGE 5
,.
VR (ENABLE)
Flat Package
,.
°2
Dual-I n-Line Package
82
DG129
82
O2
'2
v-
V+
NC
IN2
NC
IN2
NC
V-"
NC
V-
NC
V+
NC
NC
V R (ENABLE)
NC
NC
IN,
NC
8,
0,
0,
7
"
8
TOP VIEW
ORDER NUMBER:
DG133AL
SEE PACKAGE 5
lie
ORDER NUMBERS:
DG133AP OR DG133BP
SEE PACKAGE 11
Common to Substrate and Base of Package
SWITCH STATES ARE FOR LOGIC "1" INPUT
3-12
Siliccnix
,.
vR IENABLE)
DG133
v- '2
ABSOLUTE MAXIMUM RATINGS
36 V
36 V
36 V
±22 V
25 V
25 V
30 V
25 V
±6 V
V+toV- . . . . . . .
V+ to VD· . . . . . .
VD or Vs to VVD to VS· ...
V+toVR··
VR to V- ..
VIN to V-.
V+ to VIN
VIN to VR .
Current (Any Terminal)
. . . . . 30mA
-65 to 150°C
Storage Temperature ..
Operating Temperature (A Suffix) .
-55 to 125°C
(8 Suffix) . . . . . .
-20 to 85°C
Power Dissipation*
FI at Package ** .. .
750 mW
14 Pin DIP*** .. .
825 mW
* All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
DG129A. DG133A
_55 c c
1
_w
4 I
10(on)
9
-
85c C
50
75
5
100
60
1
VIN = O.S V'
+ IS(on)
-2
Channel ON
I nput Current,
Input Voltage Low
100
-5
-100
4
4
VIN = 2.5 V'
0.1
0.1
2
4
ton
D toff
Turn-OFF Time
1.6
2
~
Source OFF
Capacitance
CS(offl
~
CO(offl
Capacitance
15
Co (on) + CS(on)
Channel ON
Capacitance
16
Off Isolation
-
120
60
60
150
100
2.8 Typical ~ ..
Typ
>
3.0
3.3
Negative Supply Current
-1.S
-2.0
IR
Reference Supply
Current
-1.4
-1.5
H
Positive Supply Current
25
25
Negative Supply Current
-25
-25
Reference Supply
Current
-25
-25
-
mA
S
p
L
21
Y 1-
22
IR
Vo = 0, IS = 0
RL
60 dB at 1 MHz**
Positive Supply Current
~
--
See Switching Time Test Circuit
f"" 1 MHz
3>
~
VO=VS=O
1+
-
"S
pF
1-
20
VIN =2.5V·
2.4 TYPical"''''
17
-
100
VS=O,IO=O
1ii
19
VIN = O.S V·
2.4 Typical .....
Drain OFF
C
VO=VS=-SV
"A
12
A
Vo = S V. Vs = -S V
VO=VS=-10V
Leakage Current
IINL
I
N
5
-100
1
14
Vs=SV,vo=-SV
VO=10V,VS=-lOV
0.6
-
IS'" -10 mA,
VIN = 2.5 V'
nA
Leakage Current
Turn-ON Time
13
Vo = 10 V
Vo - S V
100
1
Drain OFF
IINH
-
TEST CONDITIONS, UNLESS NOTED:
V+ = 12 V, v- = -18 V, VR = 0
Vs = 10 V, Vo = -10 V
11
-
n
100
Input Current.
Input Voltage High
10
UNIT
25"C
Leakage Current
T
C IO(off}
H
8
_20 c C
50
Source OFF
IS(off}
"7
30
ON Resistance
3"S
5
5
30
Drain-Source
rOS(on}
2
DG129B, DG133B
125 c C
25"C
=
Q
75 51
o
ca
VIN = 2.5V*, One Chunnel ON
(It
"A
~
-...
Both VIN = 0*, All Channels OFF
":r
CD
LODC + NC
*VIN must be a step function with a minimum rise and full rate of 1 V/iJ.s.
VI
* *Typical Values are for DESIGN AID ON L Y, not guaranteed and not subject to productIon testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for VS = constant with logic input waveform as shown. Note that VS may be + or - as per
switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
lOGIC "1 '=lOGIC
INPUT
lr<'10ns
tf < lOllS
SWITCH
INPUT
SWITCH
INPUT
sw. ON
3V
2.5 V
s,
/'
o-I-----if/l ..
-f-1'-----
r-
0---'
INt~
lOGIC
INPUT
Vs
09SWITCH
OUTPUT
0-
-
f.--1
'00
f--
~
toff
I
-~~v
It
0.'
VS'" '10VASUFFIX
Vs ~ 8 V B SUFFIX
Siliconix
V-
Vo
=
(REPEAT TEST FOR S3
AND IN 2 . S2 AND $4)
Rl
Vs RL + rDS(on}
3-13
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
;;;
"'Q"
ili0:
z
w
~
f-"'"
... V
10
c-
--
~
0
i;;
0
Capacitance vs V D
~
w
::>
~
3
~
2
",
"
z
;;;
a:
,
0
.0
w
">=
-55 -35 -15
•
.I..
1
5V
z
~
"
~
~
0
w
10
g
1
j
25
~
0:
;;C
!
1
l.B
0:
1.4
::>
~
.!.
I-- ~
11-(on)1
-25
25
75
100
90
~
80 ....
Z
0
70
I'-...
60
~
, 50
I'-...
p 40
I
30
20 V+ = +12 V, V- '" -18 V
:>
R '" 0, RL '" 75n
10 VV 1N
:!!! 220 mV RMS
0
10·
106
107
"RI[""_ f-- !--
0.2
::>
~
0
-50 -25
25
50
75 100 125
I
V
iN
~
1g
T~t
I
IL
3.B pF
o
C
108
f - FREQUENCY (Hz)
Siliconix
I
0
0.1 pF
~I 3~P;
::>
0
>
Equivalent "OF F" Circuit
~
~
0
>
T - TEMPERATURE (OC)
5
'"~"
I-
125
"OFF" Isolation vs RL
and Frequency
8
6
4
2
0
-2
6
4
2
0
-2
~ -4
6 6
105
"~
Ol
0
-75
B5
I+(O~
2.2 I-- I--
I-
'"
z
:>
65
2.6
II-
I
45
z
Supply Current
vs Temperature
f"'i
0
B
6
>4
~~
zO
-> 2
,,0
5
g -2
I
-
0:
::>
~
OFF
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
T - TEMPERATURE ("C)
V~ =0 I
>
V-
0
105 125
V+=+12V
V-=-18V
~~
,~-lBV
VR
w
0.1
~
ON
Rkl
CL
10K
-=- I'0PF
"'~"
"
I
J
I-
T - TEMPERATURE ("C)
"'~"
0
1\
-=-
-10 -8 -6
S!,
V O "'±10V
0
V'N
PULSE
0:
I
L
2. 45 65 85
+ VGEN S
::>
~f; :,...... 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG139 contains four junction-type field-effect transistors designed to function as electronic switches. Level-shifting
drivers enable low-level inputs ( 2 to 3 V) to control the ON-OFF state of the switches. The driver inputs are connected
differentially so that with input IN2 connected to a 2.5 voltage reference, a positive logic "0" at input IN1 will turn
switches 1 and 3 OFF and switches 2 and 4 ON. A positive logic "1" at IN1 will turn switches 1 and 3 ON and switches 2
and 4 OFF. The normally-grounded VR terminal may be used as an "Inhibit" terminal, in which case'all switches may be
held OFF with a positive voltage applied to VR. In the ON state, each switch conducts equally well in either direction, has a
series resistance of < 30 ohms, and a shunt leakage of < 2 nA. In the OFF state the switches will hold off voltages up to
20 V peak-to-peak. Switches have make-before-break action. The DG144 is similar to the DG 139, except that it contains
two FETswitches instead of four. It is recommended that the DG190 and DG187 be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
Flat Package
Dual-In-Line Package
::s
a
5,
o
D,
DPDT
NC
v+
Da
V R (INHIBIT)
Sa
IN,
D, c:::~=r=~~~~
5,
7
,
LOGIC
TOPVIEW
ORDER NUMBER:
DG139AL
SEE PACKAGE 5
-) II
D2~~~~~~~~~52
0
1
CQ
CIt
SW1
SW3
SW2
SW4
OFF
ON
ON
OFF
~
...--
TOP VIEW
"CD::s-
ORDER NUMBERS:
DG139AP OR DG139BP
SEE PACKAGE 11
Flat Package
Dual-In-Line Package
ORDER NUMBER:
DG144AL
SEE PACKAGE 5
ORDER NUMBERS:
DG144AP OR DG144BP
SEE PACKAGE 11
1ft
NC
NC
NC
NC
NC
* Common to Substrate and Base of Package
SWITCH STATES ARE FOR
VIN1 = LOGIC "1" INPUT AND VIN2 = 2.5 V BIAS
(POSITIVE LOGIC)
Siliconix
DG144
12
v-
3-15
••C!)...
Q
...
0M
C!)
Q
ABSOLUTE MAXIMUM RATINGS
36 V
V+ to v-, VD or Vs
36 V
VDorVstoV±22 V
VD to Vs· . . . . . . . .
25 V
V+toVR······ .
25 V
V+ to VIN1 or VIN2
25 V
VR to V- . . . . . . . .
±6 V
VIN1 to VIN2· ... .
±6 V
VIN1 or VIN2 to VR
30 V
VIN1 or VIN2 to VCurrent (Any Terminal) . . . . . . . . . . . . . . . . . . 30mA
-£5 to 150°C
Storage Temperature ..
Operating Temperature (A Suffix).
-55 to 125°C
(B Suffix) . . . . . .
-20 to 85°C
Power Dissipation'
Flat Package" . . . . . . . . . . . . . . . . . . . . ..
750 mW
14 Pin DIP'"
. . . . . . . . . . . . . . . . . . . . . . 825 mW
• All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
"*Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25 u C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
1
1raS{an)
2
I_ S
3W
1--:;1
6 H
30
30
Drain-Source
ON Aesistance
11
Drain OFF
Leakage Current
1
100
-2
-100
I D(on) + IS(on)
Channel ON
Leakage Current
IIN1L
Input 1 Current,
Input 1 Voltage Low
0.1
0.1
2
4
4
VINl =2V*
0.1
0.1
2
4
4
VIN2 == 2 V*, VIN1 = 2.5 V"
120
60
60
150
100
VIN1oo3V"
60
60
150
100
VIN2 = 3 V", VIN1 = 2.5 V"
IIN2L
Input 1 Voltage High
Input 2 Current,
12
I'N2H
Input 2 Voltage High
13
ton
Turn-ON Time
0~8
14
toff
Turn-OFF Time
..
15 y CSlo1i1
N
I-A
,_,
Drain OFF
CJpacltance
17
Channel On
Cap 60 dB at 1 MHz·'"
1+
Positive Supply Current
4.2
4.5
1-
Negative Supply Current
-2
-2.2
-2.2
-2.4
Reference Supply
Current
21 ~
-p
22 L 1+
1"23 y 1-
'R
124
VO=10V,VS=-10V
~-5
Input 1 Current,
Source OFF
Capacitance
VS=BV,VO=-BV
5
Input 2 Voltage Low
I'N1H
VSoo10V,VO=-10V
100
5
Input 2 Current,
1-
C
V,Nl = 3 V' (SWl 30NI.
V,Nl = 2 V' (SW2:4 aNI
Vo = 8 V
ID(oHl
N
I-D
Is=-10mA
50
1
110
I-I
TEST CONDITIONS, UNLESS NOTED:
V+ '" 12 V, V- "" -18 V, VR = 0, VIN2 = 2.5 V"
Source OFF
Leakage Current
7
9
UNIT
60
50
1-
18
B SUFFIX
IS(off)
I-T
I~C
A SUFFIX
'R
Positive Supply Current
25
25
Negative Supply Current
-25
-25
Reference Supply
Current
-25
-25
mA
VINl == 2 V" or VINl
VIN1
·VIN must be a step function With a minimum rise and fall rate of 1 V l!J.s.
*""TYPlcal values are for DESIGN AID ONLY, not guaranteed and not subject to productIOn testing.
eo
=
3 V .. , One Channel ON
VIN2 = 0.8 V*, All Channels OFF
LODF + NC
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for VS = constant with logic input waveform as shown. Note that VS may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC "1
LOGIC
INPUT
Ir "-- 10 ns
tf ~- 10 ns
SWITCH
INPUT
'=sw
SWITCH
ON
INPUT
3v
2.5
v
1'---
Vs
0.9
SWITCH
OUTPUT
0~
3·16
1-1
'00
0.1
f--
-
I V+
SWITCH
OUTPUT
-
0---'
l~V
toff
Siliconix
CI
...
TYPICAL CHARACTERISTICS
Q
w
rOS(on) vs
Temperature
CAPACITANCE IS
- --
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
Capacitance vs V 0
I--
MEASURED FROM
TEST TEAMINAL
TO COMMON.
~
w
u
JOlon)
~
'"
COl off)
CI
...
Q
Is =0
+12V
z
~
f= lMHz
r- -
00
.DI
.DI
u
I
u
-50
-25
0
25
50
75 100
-10 -8 -6 -4 -2
125
0
2
4
6
8
10
If RGEN, RL or CL is increased, there will
Vo - DRAIN VOLTAGE (VOL TSI
T - TEMPERATURE lOCI
be proportional increases in rise and/or fall
Switching Time vs V 0
and Temperature
1.4
1.2
";::
~
::;;:
O.B
-
D.•
-r'1
k:-:' ........
F-toff
........
~
~
0.2
-55 -35 -15
25
45
65
w
100
~
a
>-
w
~~
10
u
za
a:
g
I
§
----
'E
:>
0.1
25
.5
45
105
B5
T - TEMPERATURE ("C)
T - TEMPERATURE (OC)
VIN(th) vs Temperature
Supply Current vs
Temperature
125
~
2.2
1••
a:
a:
=> 1.4
u
~
il:
1.0
a
D.•
"'"z
.,~
~
a
-50 -25
0
25
50
75
100
125
T - TEMPERATURE 1°C)
-50 -25
T-
CD
CIt
"'C;"
a
...=>>
25
50
75
100
TEMPERATURE (OCI
125
Equivalent "OFF" Circuit
:t
...--
VI
1\ V
~ -2
:>
a -4
V GEN
=
"CD::r-
0
I
a
>
"OFF" Isolation vs RL
and Frequency
o
VOEN=+lV
-4
w
H
0.2
:>
~
D
\..
?
.'.
I
Z
~
-2
II (on)1
l - I - hi
IIRlon11
I-- I--
'-
•
I
---I-- I--
I
VGEN=+5V
-2
I--
I+~
l- I-
--
I
/
2.•
E
...
1;i
Y,N - LOGIC INPUT
-2
I
Z
ffi
85 105 125
4
~2.
=>
I I
I I
5
~a:
~
VO -±10V
o
...
a
VO=+lDV
J
~
a
I I
I
ton
0.4
-
vol"Jov ~
1.6
w
1000
I I
1B
.=,
RC times.
IS(ott) vs Temperature
I I
Vi
VGEN=-lV
11
V GEN =-5V
1ft
r
-2
100
-4
iii
90
z
a
BO
~
60
os
5
it
f'
~
~
:>
-6
.....
I
70
r-......
r
50
I'-.
40
-2
-.
II
-4
30
V+=+12V,V-=-lBV
VR=O.R L =75n
20
10
VIN
105
-1.0
20
3.0
40
t-TiME (j.ls!
~ 22~ ~:~ RMS
10·
10
107
lOB
f - FREQUENCY (Hz)
Siliconix
3-17
........ 2-Channel Drivers with SPST
8 and DPST FET Switches
....
H
Siliconix
o
""
designed for . • •
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG 140 contains four junction-type field-effect transistors (JF ETs) designed to function as two double-pole singlethrow electronic switches_ Level-shifting drivers enable low-level inputs (0_8 to 2.5 V) to control the ON-OFF state of each
switch. With a positive logic "0" at the driver input the switches will be OFF. With a positive logic "1" at the input the
switches will be ON. In the ON state each switch will conduct current in either direction, and in the OFF state each switch
will block voltages up to 20 V peak-to-peak. ON series resistance is < 10 ohms, and ON shunt leakage is < 2 nA. With both
drivers in the "switch OFF" state total power consumption is < 750 JlW. Switches have make-before-break action. The
DG141 is similar to the DG140 except that it contains two SPSTswitch functions. It is recommended that the DG183 and
DG 180 be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
v+
Flat Package
11
14
2=:=;=:iii~~;S::::;:=:=:J'2
O
v-"
v+
VR (ENABLE)
'---ll:::::J IN,
7
,
TOP VIEW
ORDER NUMBER:
DG140AL
SEE PACKAGE 5
Flat Package
Dual-In-Line Package
10
VA (ENABLE)
14
02
=:=;::;~2....JF~:=::J'2
DG140
v+
NC
11
NC
v+
NC
NC
VR iENABLE)
NC
IN,
o,c::~~~-1~~=::J"
7
,
TOPVIEW
ORDER NUMBERS:
ORDER NUMBER:
DG141AL
DG141AP OR DG141BP
SEE PACKAGE 11
SEE PACKAGE 5
·Common to Substrate and Base of Package
SWITCH STATES ARE LOGIC "1" INPUT
3-18
Siliconix
,0
V R (ENABLE)
,2
DG141
·v-
a
ABSOLUTE MAXIMUM RATINGS
V+ to V- . . . . .
.. .
.. .
V+ to VD or Vs
...
VD or Vs to V·.
..
VD to VS·
·.
V+ to VR .
·.
VR to V-.
VIN to V.. . . . .
V+ to VIN
..
. . . . ..
..
VIN to VR
Current (Any Terminal) . . . . . . . . . . . . . . ..
36 V
36 V
32 V
±22 V
25 V
25 V
30 V
25 V
±6 V
30mA
.. .
Storage Temperature . . . . . . . . . . . . ..
Operating Temperature (A Suffix) .
(B Suffix) . . . . . .
Power Dissipation *
Flat Package**
14 Pin DIP*** .. .
.
--65 to 150°C
-55 to 125°C
-20 to 85°C
750mW
825mW
...
Q
A
o
a
......
Q
A
* All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample· tested for AC parameters and
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
OG140A.OG141A
OG140B.OG141B
UNIT
-55"C
25°C
125°C -20"C
25"C
85"C
10
10
20
Drain-Source
......2 rOSlon)
l!
ON Resistance
2
15
15
25
I---;s
10
1000
Source OFF
14 WI ISlo1I1
Leakage Current
15
300
15 T
10
1000
Dram OFF
nA
c
1010ffi
16 H
Leakage Current
15
300
17
-100
-2
ChilnnelON
16 IDlor.1 + ISlonl Leakage Current
-100
-5
9
I-
10
I
N
11
112
1- 0
Input Current,
Input Voltage Low
IINL
Input Current,
IINH
Input Voltage High
ton
Turn-ON Time
toff
Turn-OFF Time
13 V CSloffl
I-N
A
14 M CDloffi
I-I
15 C COlon) + eSlon)
116 Off Isolation
17
1+
Ils 11- S
19 ~ IR
1-
I~ ~
0.1
0.1
120
2
60
60
1
2.5
4
150
100
3 TVp
3 TVp
Channel ON
2.8 TVp
2.8 TVp
..
Negative Supply Current
Reference Supply
Current
1+
Positive Supply Current
21 V 1122
IR
Negative Supply Current
Reference Supply
Current
Vo = 10 V
VO=8V
VS=10V.VD=-10V
Vs =8 V. Vo = -8 V
VD=10V.VS=-10V
VD = 8 V. Vs = -8 V
VD=VS=-10V
Vo = Vs = -8 V
-1.4
-1.5
25
--25
25
··25
-25
··25
VIN = 2.5 V'
VIN =2.5V·
See SWltchmg Time Test Circuit
pF
VD=O.IS=O
VD
l1li
rnA
f = 1 MHz
~
= Vs = 0
RL = 100
3.3
-2
VIN = 0.8 V'
VIN =0.8 V'
> 50 dB at 1 MHz**
3
-1.8
IS = -10 rnA.
VIN = 2.5 V'
Vs = O.ID = 0
..
Typ
TEST CONDITIONS. UNLESS NOTED:
V+ = 12 V. V- = -1 BV. VR = 0
"A
"'
..
"
Positive Supply Current
100
..
3 TVp
Drain OFF
Capacitance
Capacitance
4
15
2.5
..
3 TVp
Source OFF
Capacitance
4
high and low temperature limits
ll.
~
-
Q
CL = 3 pF
o
ca
VIN '" 2.5 V *, One Channel ON
.'"-.
CIt
~
"A
Both VIN :: 0·. All Channels OFF
::r'
*VIN must be a step function with a minimum rise and fall rate of 1 V If.lS.
**Typlcal values are for DESIGN AID only. not guaranteed and not subject to production testmg.
CD
VI
LODe + NIP
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for VS = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test ci rcu it. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
SWITCH
INPUT
SWITCH
OUTPUT
3V
25V,
5,
ton· +VS
tou. Vs
~
o---l
1?VV,
SWITCH
INPUT
LOGIC "1" = 5W. ON
LOGIC
INPUT
t r < 10ns
tf< 10ns
'----
IN,
LOGIC
INPUT
Vs
0.9
0-
-
n
-1
'oo
0.1
~
~
toff
-::Vs" 10 V A SUFFIX
Vs = 8 V B SUFFIX
Siliconix
1'--
--Q-t>-J
6VR
OV
Vo "V 5
v-6
-1B V
0,
SWITCH
OUTPUT
Vo
R'i Je l
'K"-::- 135PF
(REPEAT TEST FOR 53 (OG140),
AND lN 2 • 52 AND 54 (DG140)j
Rl
RL t rOS(on)
3·19
TYPICAL CHARACTERISTICS
~l:
g
rDS(on) vs
Temperature
Capacitance vs V D
CAPACITANCE IS
MEASURED FROM
TEST TERMINAL
TO COMMON.
w
.,
U
Z
I;;
'"
z
I-- f-
0
10
C-
.,"'"0
l - I-
f= 1 MHz
IS= 0
,
r- r-
iii
w
u
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
100
COlon)
-
COloff)
z
;;
'"
C
I
0
~
-50 -25
25
50
75
100
o
125
-10 -8 -6 -4 -2
T - TEMPERATURE (OC)
~
1.2
l
0.8
0.6
0.4
6
8
-- -
RC times.
1000
-vr
......
./
w
IJ
I-
~;~
"~
~Iov
~
~-'
zo
;:;2
I 1
Vo
0.2
g
.....
" ...
I
I I
'on
§
±10V
5
25
45
65
85
:>
0.1
105 125
25
65
105
B5
125
-2
-
2 .•
V-"'-18V
;;
.E
2.2
15a:
1.8
...
"u>'" I.'
.,"~ 1.0
-F"
z
0
-
I-
I+lo!!,..
-2
;
l - I - 1-1I~lon}1
l- I-
D.•
~
76
25
50
75
100
T - TEMPERATURE fOCI
125
V
V
...
'i
IV
V
A
III
~g
-50 -25
125
T - TEMPERATURE 1°C)
r- I-Vi E\
-4
w
0.2
25
V?ENI5~
1/\
II-Ion)i
l - t--
2-25
r-
-4
V~ =0 I
V+ = +12 V
-75
I
II
Supply Current vs
Temperature
VIN(th) vs Temperature
OFF
45
T _ TEMPERATURE (OCI
T - TEMPERATURE (OCI
~ ~~
V 1N - LOGIC INPUT
-2
I
Z
I I
-55 -35 -15
10
If RGEN, RL or CL is increased, there will
Vol= -1~V
I.---
~
;:
4
IS(off) vs Temperature
~J
1.6
1.4
2
be proportional increases in rise and/or fall
Switching Time vs VD
and Temperature
1.8
0
Vo - DRAIN VOLTAGE (V)
~
-2
"o
-4
VGEN-OV
l\l
V
I
"OFF" Isolation vs RL
and Frequency
10
20
;;;
:!!
40
S
50
111
60
0
1111I1111
111111111
-2
RL = lKfl
-6
-4
I--
lL I-'""
V OEN - -1 V
1\
I I I
r--
SIGNAL
SOURCE B
Z=50n
RL -100n
~
LOGI~I
BO
"OFF" ISOLATION
90
A - DRAIN OF "OFF"SWITCH
B - SOURCE OF "OFF" SWITCH
0.01
IJ1 ,--JGEJ =-kv
I-"""
-2
70
100
0.1
10
20
IVll
100
f - FREQUENCY (MHz)
3-20
A
III
30
z
0
;:
......
,;>
Silicanix
-4
6
t - TIME {ps}
Drivers with Normally Open &
Normally Closed Switches
designed for. . .
H
Siliconix
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB
@
1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Orivers
•
Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG142 contains four junction-type field-effect transistors designed to function as electronic switches. Level-shifting
drivers enable low·level inputs (2 to 3 V) to control the ON-OF F state of the switches. The driver inputs are connected
differentially so that with input IN2 connected to a 2.5voltage reference, a positive logic "0" at input INl will turn switches
1 and 3 OFF and switches 2 and 4 ON. A positive logic "1" at IN1 will turn switches 1 and 3 ON and switches 2 and 4 OFF.
The normally-grounded VR terminal may be used as an "Inhibit" terminal, in which case all switches may be held OFF with
a positive voltage applied to VR. In the ON state, each switch conducts equally well in either direction, has a series resistance
of < 80 ohms, and a shunt leakage of < 2 nA. In the OFF state the switches will hold off voltages up to 20 V peak-to-peak.
Switches have make·before·break action. The DG143 is similar to the DG142, except that it contains two FET switches
instead of four. It is recommended that the DG 191 and DG 188 be used for new designs.
SCHEMATIC DIAGRAMS
PIN CONFIGURATIONS
Flat Package
Dual·1 n·Line Package
:s
a
s,
IN,
NC
v-v+
°3
V R (INHIBIT)
0,
S3
'N,
0,
S,
7
TOPVIEW
,
ORDER NUMBER:
DG142AL
SEE PACKAGE 5
Flat Package
o
CD
.
tit
-.~
TOPVIEW
LOGIC
o
1
SW 1
SW3
SW2
SW4
OFF
ON
ON
OFF
ORDER NUMBERS:
DG142AP OR DG142BP
SEE PACKAGE 11
"::r
II
Dual·ln·Line Package
0,
12
vDG142
NC
NC
NC
NC
NC
0,
7
TOPVIEW
-J>
0,
,
LOGIC SW1
SW2
ORDER NUMBER:
ORDER NUMBERS:
OFF
ON
0
DG143AL
DG143AP OR DG143BP
1
ON
OFF
SEE PACKAGE 5
SEE PACKAGE 11
·Common to Substrate and Base of Package
SWITCH STATES ARE FOR
VIN1 = LOGIC "1" INPUT AND VIN2 = 2.5 V BIAS
(POSITIVE LOGIC)
Siliconix
12
vDG143
3-21
ABSOLUTE MAXIMUM RATINGS
36 V
V+ to v-, VD or VS.
. ........ .
36V
VD or Vs to V- ..
..
. ... .
±22 V
VD to VS. . . . . . . .
..
.•. ..
..
25 V
V+toVR··· . . . . . . . . . . . . . . . . . .
25 V
V+ to VIN1 or VIN2.
...
...
..
VR to V-. . . . . . ..
....
. . ..
..
25 V
±6 V
VIN1 to VIN2. . . . .
....
. . .. ..
..
±6 V
VIN1 or VIN2 to VR
...
... .
..
30V
VIN1 or VIN2 to V. ..
. .. ..
..
Current (Any Terminal) . . . . . . . . . . . . . . . . . . 30mA
Storage Temperature ..
--65 to 150°C
Operating Temperature (A Suffix) ..
-55 to 125°C
(8 Suffix) .....
-20 to 85°C
Power Dissipation*
Flat Package** . . . . . . . . . . . . . . . . . . . . .. 750 mW
14 Pin DIP*** . . . . . . . . . . . . . . . . . . . . . . 825 mW
* All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25 u C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
A SUFFIX
CHARACTERISTIC
-55"C
1
Drain-Source
!--2
-a
rOSlon)
80
80
B SUFFIX
125"C
TEST CONDITIONS. UNLESS NOTED:
V+ = 12 V, v- = -18 V. VR = 0, VIN2 = 2.5V*
UNIT
-20"C
25"C
ss·'c
100
100
150
Vo = 10 V
150
ON Resistance
H
IS'" -10 mA,
i--c:--::-,-,-----l VINl '" 3 V* (SW, 3 ON),
Vo - B V
VINI .2 V' 1SW2:4 ONI
Sr-------s-o-u-rc-e-o-F-F----r---t--~,-t-,~O=O-t---i---r---r---t-V~S---,~0~V~.~V~D----~10~V~-~---~~---I
'4 ~
ISloft)
-- T
5 C I
6
2S"C
Leakage Current
5
Drain OFF
H Dloffl
1
-2
5
100
-5
-100
4
4
V,
Vo '" -8 V
r.-"'--:-:=-"---:-::-:-:-i
nA
Leakage Current
7
Vs '" 8
100
100
-100
Vo - 10 V. VS· -10 V
Vo '" 8 V. Vs =- -8 V
8
lolon) + IS(on)
Channel ON
Leakage Current
~
IINIL
:~:~:~e~;;:;;'LOW
0,1
0.1
10 IIN2L
:~:~: ~ ~~~;:;;'LOW
0,1
0.1
IIN1H
:~:~: ~ ~~~;:;;'Hi9h
120
60
60
150
100
100
V,Nl ·3 V'
IIN2H
Input 2 Current.
Input 2 Voltage High
120
60
60
150
100
100
V,N2· 3 V', V,Nl ·2.5 V'
ton
Turn-ON Time
2
4
Vo - VS· -10 V
Vo = Vs = -8 V
V,Nl ·2 V' ISW, 30FFI.
V,Nl. 3 V' 1SW2:4 OFF)
V,Nl·2V·
VIN2 = 2 V*, VINl = 2.5 V*
--~r---------~~~~~~~-----r----r----r----+---~--~
11
-12
13
O,B
:14
..
V,Nl· 3 V' ISW,.3 ONI.
V,Nl ·2 V' ISW2,4 ON)
"'
See Switching Tlme Test CirCUit
rnA
V,Nl '" 2 V* or V,N1 '" 3 V*, One Channel ON
toft
Turn-OF F Time
1.6
I--D~~----------------------+_----+-----~--~----_+----_+----~----~--------------._---------------I
15 V CS(off)
Source OFF
VS·O.IO·O
2.4
Typ
2.4 Typ
N
Capacitance
- - A~------------D~ra-;n--O-F-F---------+-----+--·-·--+-----+-----~--.-.--~--~
pF
f = 1 MHz
Vo • 0, IS • 0
16 M COlaW
Capacitance
2.4 Typ
2.4 Typ
I--Ir---------~~~------+---_+----+---_+----~--_+--~
17 C
Channel ON
2.B Typ
2.B Typ
COlon) + CS(onl
Capacitance
1_
Typ > 60 dB at 1 MHz ....
18
Off Isolation
19
1+
Positive Supply Current
120
1_
Negative Supply Current
4.2
4,5
-2
-2,2
I--S~--------~R~e~f.-re-nc-e~Su-p~PI-y---+----~--~~--~----~---+--~
21 U IR
Current
-2.2
-2.4
1-p~----------~~~--------+-----~--~~--_+----_+----_+-----r----_r-------------------------------I
22 p 1+
Positive Supply Current
25
25
:~ ~ f:.1--------,N"'e-g-at.,-;v-.":'SU.:.P:...P.:.,v"'c:-u-rr-e-nt+--+--":'2:-5-+---+---+-_"'2:-:5,-11--,-1
24
~~;~;~~ce Supply
IR
-25
V,N1 "" V,N2 = O.B V*, All Channels OFF
-25
·V,N must be a step function with a minimum rise and fall rate of 1 VIllS.
"Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
LODF + NC
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
2.5V
SWITCH
INPUT
LOGIC "," .. sw. ON
LOGIC
INPUT
t r < 10 ns
1f<10ns
SWITCH
INPUT
SWITCH
OUTPUT
3V,'---------"
1'----
0---'
Vs
-I-;;:;-:];:==+==;-0.9
0-1--1
-
3·22
-r-
2.5V-,
'on
0.1
I--
-
'off
Siliconix
I'N2
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
Capacitance vs V D
f=lMHz
IS" 0
r- ~~~~~'~:~~~bsM - f-
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
TEST TERMINAL.
TO COMMON.
r-r- '----
+12V
co!on!
eO(off)
-50 -25
25
50
75
100
125
-10 -8 -6
Switching Time vs V D
and Temperature
1.4
~
~
>=
~
1.2
0.8
~f-""""
~
0
25
45
65
T - TEMPERATURE
~
o
>-
~~
......
Sl
I
4
~45
25
rei
65
85
105
125
z
->
T - TEMPERATURE (OC)
I
Supply Current vs
Temperature
;;
2.2
I-
1.8
.s
i'5
a:
If
- -
-
:::s
.!.
~
I--
0.6
IIRlon)1
f
- I---
CIt
0
~
w
"C;
75
100
V\
>
125
-50 -25
25
50
75
100
125
T - TEMPERATURE (OC)
~
::>
0
I
0
"OFF" Isolation vs RL
and Frequency
z
90
80
>
I
II
~
~
~
P
...
~
->
70
~I 3~PF
.......
50
I
.......
40
ViN
30
v- "" -18 V
V R ;; 0, RL .. 75 n
V+"' +12 V,
10
/"
.
10·
-
1g
T~j
3.8 pF
I
o
IL
0
VIN '"" 220 mV RMS
105
V GEN =-lV
-4
0.1 pF
60
20
CD
IA
V GEN " -SV
I /"
II
-2
-.
-4
-1.0
107
(II
I
-2
...
0
,!il
VGEN = 0
-4
Equivalent "OFF" Circuit
":s-
\ /"
-2
100
~
...--~
4
0.2
T - TEMPERATURE (OC)
ca
VGEN =+1 V
-4
0
50
I\.
-2
~
g, 1.0
Z
-o
II
1/
11-(on)1
OJ
•
I--'+(~
a: 1.4
0
l1li
1\\..
V GEN =+5V
-2
::>
u
25
VIN - LOGIC INPUT
-2
I
0.1
85 105 125
2.•
0
t- -
u-
VI N (th) vs Temperature
-50 -25
-
~§?
~
ffi
I I
5
"'
10
::>
I I
-55 -35 -15
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RCtimes.
100
"'~
I I
o
10
a:
~
0.2
8
::>
u
V O -±10V
'on
0.4
6
I-
V O -+l0V
I---'
0.6
4
1
f.--t"" I
~ F- 'f.- .-
2
IS(off) vs Temperature
v~=Jov :;:;
1.6
0
1000
I I
1.8
-4 -2
Vo - DRAIN VOLTAGE (VOL IS)
T - TEMPERATURE r'C)
1.0
2.0
3.0
4.0
1- TIME lJ.ls)
108
f - FREQUENCY (Hz)
Siliconix
3-23
Drivers with Normally Open &
Normally Closed FEY Switches
designed for . . .
H
Siliconix
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
•
Minimizes Standby Power Requirements
o <1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG145 contains four junction-type field-effect transistors designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (2 to 3 V) to control the ON-OFF state of the switches. The driver inputs are connected
differentially so that with input I N2 connected to a 2.5 voltage reference, a positive logic "0" at input IN 1 will turn switches
1 and 3 OFF and switches 2 and 4 ON. A positive logic "1" at IN1 will turn switches 1 and 3 ON and switches 2 and 4 OFF.
The normally-grounded VR terminal may be used as an "Inhibit" terminal, in which case all switches may be held OFF with
a positive voltage applied to VR. In the ON state, each switch conducts equally well in either direction, has a series resistance
of < 10 ohms, and a shunt leakage of < 2 nA. In the OFF state the switches will hold off voltages up to 20 V peak-to-peak.
Switches have make-before-break action. The DG146 is similar to the DG145 except that it contains two FET switches
instead of four. It is recommended that the DG189 and DG186 be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
Flat Package
V-'
LOGIC
v,
V R (INHIBIT)
0
1
IN,
SW1
SW3
SW 2
SW4
OFF
ON
ON
OFF
D,=~~r-=~~~::Js,
7
TQPVIEW
ORDER NUMBER:
DG145AL
SEE PACKAGE 5
Flat Package
Dual-In-Line Package
,2
NC
IN2
NC
V-'
DG145
,,,
V'
NC
NC
VA (INHIBIT)
NC
IN,
D, =~~~7"";;'-.e~~=S,
TOPVIEW
ORDER NUMBER:
DG146AL
SEE PACKAGE 5
LOGIC
SW 1
SW2
0
OFF
ON
ON
OFF
1
ORDER NUMBERS:
DG146AP OR DG146BP
SEE PACKAGE 11
* Common to Substrate and Base of Package
SWITCH STATES ARE FOR
VIN1 = LOGIC "1" INPUT AND VIN2 = 2.5 V BIAS
(POSITIVE LOGIC)
3-24
Siliconix
DG146
V-
ABSOLUTE MAXIMUM RATINGS
V+ to v-, VD or Vs . .
VD or Vs to V- . . . .
VD to Vs . . . . . . . . .
V+toVR . . . . . . . ·
V+ to VIN1 or VIN2
VR to V- . . . . . . . .
VIN1 to VIN2 .....
VIN1 or VIN2 to VR
VIN1 or VIN2 to V- ..
·.
·.
·.
'"
.
'"
.
36
32
±22
25
25
25
±6
±6
30
·.
·.
·.
· . ·.
·.·.
.
..
..
Current (Any Terminal)' . . . . . . . . .
Storage Temperature . . . . . . . . . . .
Operating Temperature (A Suffix) .. .
(B Suffix) .. .
Power Dissipation'
Flat Package"" . . . . . . . . . . . . . . . . . . .
14 Pin DIP"'" . . . . . . . . . . . . . . . . . . .
V
V
V
V
V
V
V
V
V
. . . . . 30mA
-65 to 150°C
-55 to 125°C
-20 to 85°C
.
.
750mW
825mW
'All leads welded or soldered to PC board.
"'Derate 10 mW/oC above 75°C .
""Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25 u C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
A SUFFIX
CHARACTERISTIC
-SSoC
1
12S"C
10
20
10
Draln·Source
rOSton}
1"2
25"C
B SUFFIX
25"C
V+
15
15
25
15
300
= 12 V. v- '" -18 V, VA "" 0, VIN2 '" 2.5 V·
IS = -10 mA
VINl :. 3 V' (SW',3 ONI.
VINl '" 2 V' ISW2.40NI
VO'" lOV
VO==BV
Source OFF
Leakage Current
10
'Sloff)
Dram OFF
Leakage Current
10
1000
'Oloff)
-2
-100
1010ni + 'Slonl
Channel ON
Leakage Current
IINll
Input 1 Current,
Input 1 Voltage Low
0.1
01
2
I'N2l
Input 2 Current,
Input 2 Voltage Low
01
0.1
2
I'N1H
Input 1 Current,
Input 1 Voltage High
120
60
60
150
100
100
VINl '" 3V'
12
'IN2H
Input 2 Current,
Input 2 Voltage High
120
60
60
150
100
100
V,N2 -' 3 V', VINl - 2.5 V·
13
ton
Turn-ON Time
I. ~
IS T
IS ~
1"1
1--'8
9
110
I-I
11
N
1-
I,.
1-0
VS'" lOV,Va= -lOV
-100
4
4
4
4
4
4
25
~
VIN2 '" 2 V', V,Nl
=
=
3 V' (SW'.3 ONI.
2 V' (SW2.4 ON)
2 5 V'
T~P
3 Typ
Channel ON
Capaci lance
..
28 Typ
J>
Vs - 0, 10 '" 0
pF
..
VD '" 0, IS
28 Typ
Vo
Typ> 50 dB at f - , MHz"
~
=
a
::I
f" 1 MHz
-
a
o
Vs '" 0
ca
RL-100n,cL=3pF
18
Off IsolatIOn
19
1+
POSitive Supply Current
42
45
1-S
21 U IR
Negative Supply Current
-2
-2.2
-22
-2.4
Reference Supply
Current
l1li
See SWitching Time Test Circuit
"'
25
3
24
VINl
VINl
-8 V
VINl '" 2V'
..
Dram OFF
Capacitance
22 "
8 v. Vs = -8 V
vb" Vs -
1.5
1
A
16 M COloftl
_I
-"
23~
-
e:
"A
3 Typ
20
Vo
300
-5
3 f;p
H C COlon) + CS(on)
V'Nl '" 2 V' (SW1,3 OFF).
VINl = 3 V· (SW2,4 OFF)
VO=10V,VS--1OV
VO=VS=-10V
15 Y CS(off)
_N
VS"'SV,VO=-8V
nA
15
Turn·OFF Time
toff
1000
Source OFF
Capacitance
-
TEST CONDITIONS, UNLESS NOTED:
UNIT
8S'C
11
ON Resistance
13" s
-20' C
1+
POSitive Supply Current
25
25
1-
Negative Supply Current
-25
-25
IR
Reference Supply
Current
-25
-25
mA
V,Nl
=
2 V' or VINl "3 V', One Channel ON
"A
VINl
~
VIN2" 08 V'. All Channels OFF
(It
_.
~
•
It
::I""
CD
VI
·V,N must be a step functIOn With a minimum rrse and fall rate of 1 V//ls
··TYPlcal values are for DESIGN AID ONl Y, not guaranteed and not subJect to production testing.
LODF + NIP
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
'y2V
2. 5VI
SWITCH
LOGIC "'" " sw. ON
LOGIC
INPUT
Ir'" IOns
If'-'0 ns
SWITCH
INPUT
SWITCH
OUTPUT
IN2
V+
SWITCH
OUTPUT
V
2.5 V..,
0--'
Vs--~~;====+~-0.9
o-f.-J
-
i
INPUT
3V,~-----"\
'on
::;;, ~Js
S2
-r
VS '±10VASUFFIX
S,
.......
VS=±8V8SU::~X~rc
IN, ~
~
1
Va
'K~~ I~~PF
L....J'V
INPUT
O2
0.1
I--
--
loff
VO=VS _ _
R_L_
RL +rOS(onj
Siliconix
11.
-=
I
o~VR
I
_l~VV-
-==--=-
(REPEAT FOR S3 ANOS 41
(OG1451
3·25
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
i
Capacitance vs V D
Q100
~
~
illa:
-
z
..-I -
o
~
~
10
CAPACITANCE IS
MEASURED FROM
TEST TERMINAL
TO COMMON.
I
-
I--
COlon)
f-
COloff)
I-- ' -
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
,= 1 MHz
IS'" 0
+12V
g
'a:z;;"
T?L
"
i
I
g
~
-so
o
-25
0
25
50
75
100
125
-10 -8 -6 -4 -2
T - TEMPERATURE 1°C)
0
2
4
6
8
10
VD - DRAIN VOL TAGE (V)
If
Switching Time vs VD
and Temperature
1.4
-
"
1.2
;::
I
08
0.6
'L .....t""'""
.....- I I
.....,~~ ~ ~DV
I-I I
0.4
1
...
~
~
0
5
25
45
65
85
10
U
a:
::>
~0
.......
.... I-- -
.,
...>
;::
[l
u
a
I
g
~ tc= ~
~
_Vi
I I
-55 -35 -15
~
u
VD=~10V
0.2
/
100
::>
I I
ton
RCtimes.
'S(off) vs Temperature
1000
vD"_l~v
1.6
0.1
105 125
=
25
-
45
65
Z
:>
85
105
T - TEMPERATURE r"C)
V'N(th) vs Temperature
Supply Current vs
Temperature
.,
...
2.2
~a:
1.8
u
1.4
::>
~
iil
z
0
1.0
125
I-- I-- I+~
-2
-2
I
I-- I-- _,!lR(on)1
I-- f--
~
::-r
25
50
75
100
-50 -25
25
50
75
100
T - TEMPERATURE (OC)
125
...>
~
::>
,
0
~
Z
40
3
50
~
0
V
V
/1-'"'"
f-
-6
r- ]
SIGNAL
SOURCE B
RL = loon
Z" 50
VGEN",-lV
TI
,!
I
\.
I " -5l V
f--v GEN
n
I--"
-2
LOGI~I
-4
VL'
-6
80
"OFF" ISOLATION Q 20
90
A - DRAIN Of "Off" SWITCH
B - SOURCE Of "OFF" swnCH
01
10
I-"""
A
-2
100
I - TIME
100
f - FReQUENCY (MHz)
3·26
VGEN ~ 0 V
-4
-4
70
0,01
-2
1\
111111111
RL = lKH
~ so
A
>
30
0
V
V
I v
'\
0
1IIIilili
10
r 'I
~
125
V
VGEN: 1 V
0
(~C)
5~
0
"OFF" Isolation vs RL
and Frequency
20
r-
-4
"!
~
0.2
T - TEMPERATURE
VrEN ,'
1\
I
z
-
-4
11-(on)1
I-- I--
0.6
I
--
2.6
oS
VIN - LOGIC INPUT
-2
I
=r=~
~-
T - TEMPERATURE ("CI
:>
RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
I I
1.8
OPF
Siliconix
(~l)
2-Channel Drivers with SPSY
and DPSY FEY Switches
designed for .
..
.
c
H
......
c
...
Q
Siliconix
VI
Q
BENEFITS
VI
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation
Drivers
o Bipolar Drivers
•
Resistance than
W
PMOS
Minimizes Standby Power Requirements
< 1 mW Standby Power
o
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG153 contains four junction-type field-effect transistors (JFETs) designed to function as two double-pole singlethrow electronic switches_ Level-shifting drivers enable low-level inputs (0_8 to 2_5 V) to control the ON-OFF state of each
switch_ With a positive logic "0" at the driver input the switches will be OFF_ With a positive logic "1" at the input the
switches will be ON_ In the ON state each switch will conduct current in either direction, and in the OFF state each switch
will block voltages up to 15 V peak-to-peak_ ON series resistance is < 15 ohms, and ON shunt leakage is < 2 nA_ With both
drivers in the "switch OFF" state total power consumption is < 750 /lW. Switches have make-before-break action_ The
DG151 is similar to the DG153 except that it contains two SPST switch functions. It is recommended that the DG180 and
DG 183 be used for new desi gns.
PIN CONFIGURATIONS
--
SCHEMATIC DIAGRAMS
Flat Package
v+
11
Dual-In-Line Package
J>
NC
IN2
NC
v-"
NC
v+
NC
V R (ENABLE)
NC
IN,
:I
Q
o
CD
.'"-.
D,=~~~""""1~~~::JS,
fit
~
7
•
TOPVIEW
ORDER NUMBER:
DG151AL
SEE PACKAGE 5
ORDER NUMBERS:
DG151AP OR DG151BP
SEE PACKAGE 11
::r-
.,.CD
Flat Package
14
D2
S2
s,
IN2
D,
v-"
NC
v+
D3
V R (ENABLE)
S3
.,
IN,
D,
7
•
TOP VIEW
ORDER NUMBER:
DG153AL
SEE PACKAGE 5
·Common to Substrate and Base of Package
SWITCH STATES ARE FOR LOGIC "'" INPUT
Siliconix
,.
V R (ENABLE)
DG153
v-'2
3-27
ABSOLUTE MAXIMUM RATINGS
......
lit
"a
... . · . · . . . . ..
..
·.·.
·. ·.
·.
..
·.
..
·.
..
·.
·.
V+ to V- or VD .. . .
VD'to V-.
..
VD to Vs . . . . . .
V+toVR····· .
V+ to VIN1 or VIN2 .
VR to V- . . . . . . . .
VIN1 to VIN2 .....
VIN1 or VIN2 to VR
VIN1 or VIN2 to V-
36
32
±22
25
25
25
±6
±6
30
..
·.
V
V
V
V
V
V
V
V
V
Current (Any Terminal). ....... . .. . . .... 30mA
-u5 to 150°C
Storage Temperature . . . ....... . .
-55 to 125°C
Operating Temperature (A Suffix).
(B Suffix) ......
-20 to 85°C
Power Dissipation*
Flat Package** . , . . .................. 750mW
14 Pin DIP*** . .. .................. . 825mW
* All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
DGI51A. DG153A
OGI51B. DG153B
UNIT
-55'C
25'C 125'C -20'C
25'C
85'C
15
15
30
1
Drain-Source
!!
12" 'DSlon)
ON Resistance
20
20
35
13S
10
1000
Source OFF
14 w ISlolI)
Leakage Current
15
300
I
15 T
10
1000
Drain OFF
nA
C 10(011)
Leakage Current
15
300
H
-2
-100
Channel ON
IS 1010n) + ISlon)
Leakage Current
-5
-100
:~
Input Current,
I nput Voltage Low
9 IINL
I-I
N
10 IINH
11
112
I- D
13 Y
I-N
A
14M
I-I
15 C
116
ton
Turn-ON Time
toff
Turn-OFF Time
CSloff)
Source OFF
Capacitance
COloff)
Drain OFF
Capacitance
COlon) + CSlon)
60
60
..
3 Typ
..Typ
3
..
2.8 Typ
Capacitance
4
4
VD=7.5V
Vo = 5.5 V
Vs = 7.5 V, Vo = -7.5 V
Vs = 5.5 V, Vo = -5.5 V
Vo = 7.5 V, Vs = -7.5 V
Vo = 5.5 V, Vs = -5.5 V
Vo = Vs = -7.5 V
Vo - Vs = -5.5 V
IS = -10 mAo
VIN = 2.5 V'
VIN = 0.8 V·
VIN = 2.5 V'
VIN = 0.8 V·
4
150
100
100
1.5
2.5
VIN = 2.5 V·
~s
..
3Typ
..
3Typ
..
2.8 Typ
Positive Supply Current
Positive Supply Current
Negative Supply Current
1-
Negative Supply Current
IR
Reference Supply
Current
See Switching Time Test CircUit
VS=O,IO=O
pF
Vo = 0, IS = a
f:: 1 MHz
Vo = Vs = a
RL = 100 n, CL = 3 pF
Typ> 50 dB at 1 MHz··
Off Isolation
P
2ii
_ L 1+
22
2
1
2.5
Channel ON
Reference Supply
Current
-
120
Input Voltage High
1+
Is
1_S
19 ~ IR
y
0.1
TEST CONDITIONS. UNLESS NOTED:
V+ = 15 V. V- = -15 V. VR = 0
~A
Input Current,
17
21
0.1
high and low temperature limits
3
-1.8
3.3
-2
-1.4
-1.5
25
-25
25
-25
-25
-25
mA
VIN
~A
VIN = 0*, All Channels OFF
"'VIN must be a step function with a minimum rise and fall rate of 1 V/IJS.
"Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
= 2.5
LODe
V*, One Channel ON
+ NIP
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
+15V
SWITCH
V+
INPUT
?
LOGIC
INPUT
t,< ,Ons
tt< 10n5
SWITCH
INPUT
3V
LOGIC "'" = SW. ON
ton'+Vs
toff. -;-VS
-'
2.5V
1'---
0---'
OUTPUT·
3-28
IN,
LOGIC
INPUT
vs
Il
0.'
SWITCH
S,
0-
O.t
--1
- "'. - -
toft
.".
Vs = ±1.5 V A SUFFIX
Vs = ±S.S V B SUFFIX
Siliconix
'f
~
6VR
OV
V~'~V
Rl
Va'" Vs RL + rOSl on )
D,
SWITCH
OUTPUT
Vo
Rhi :bel
'K".". I3."F
(REPEAT TEST FOR S3 (DG1S3)
AND 12, S2 AND S4) IDG153)
lei
Q
TYPICAL CHARACTERISTICS
u;
~
g 100
Capacitance vs V D
"z
CAPACITANCE IS
MEASURED FROM
TEST TERMINAL
TO COMMON.
4
"
in
"a:
~
-
z
0
w
10
0
"...z
u
- -
1
5V
1
-50 -25
0
25
50
75 100
125
2
1.2
l.- i-"
toff-
w
1
~ 0.8
~
0.6
I---'
-
l.-
~
~
0
-55 -35 -15
I
25
45
65
""e;
0
4
~
~
zo
2
a
0
w
~~
i-"'"
10
a
9
4
65
85
105
125
-2
;;
E.
...
,.....
ffi
2.2
......
:>
1.8
""~
il:
1.0
z
0.6
~
-
0.2
I
4
25
75
T - TEMPERATURE lOCI
+-
~
11-lon)1
0
~
w
to
I--
-50 -25
125
IIRII"I'_
0
l - t-
25
50
75
100
125
:l
50
!il
60
0
70
~
~
4
~
:>
-2
0
-4
4
IIIII
V,N
SIGNAL'~
SOURCE
B "'"
z=son
-loon
11
8
I /. I
son
A
VL
:
l.\l
A
2
VI
III
Lt""
-2
lK n
I-
vGEN::-1V
,"1 I
1\
r-~ t--t~· -~V
0
3 . : ± iRL
.
--~
"CD:::r
V
VGEN-OV
-6
RL
en
LA
III
2
0
I
I' '\ IV
:::s
a
o
ca
V
6
>
...
VIEN
-4
-4
RL'"
40
0
r-
0
IIIII
20
z
e;"
>
T - TEMPERATURE (Oel
"OFF" Isolation vs RL
and Frequency
30
) II
III
0
0
-25
~
l\J'
6
-2
a:
a: 1.4
0
I
10
r- f-VfE\ 5,
-4
I+(~
l - t-
--
1/
0
2
;;:
0
I
2
45
25
I
1
0
j:
6
:>
2.6
:c
j
VIN - lOGIC INPUT
z
1
r-r-r-
0
0.1
V-=-18V
~~
.~-15V
V-
-2
I
105 125
ON
OFF
0
-75
;::;2!
VIN vs Temperature
90
:>
6
... u;
>
T - TEMPERATURE (UC)
f.@
CL
10pF
8
~
Supply Current vs
Temperature
>
z
a:
a:
0
I
V+=+12V
2
w
to
w 100
z
~
J!i
±10V
85
V~' 0
r
10
1...
T - TEMPERATURE 1°C)
~
0
8
@
I I
5
6
4
":>a:
I I
I 1
VD
2
-=
Rkl
10K
IS(off) vs Temperature
~v
'on
0.4
0
W
Vo
1000
I I
0.2
VI
D
If RGEN, RL or CL is increased, there will
be proportional increases in rise andlor fall
RCtimes.
VD:'~
1.4
iVR
~
-2
-4
"OFF" ISOl.ATION
80
~
20 l.OG
1~1
1Vl.1
A - DRAIN OF "OFF"SWITCH
B - SOURCE OF "OFF" SWITCH
90
-6
0
1
2
3
4
t - TIME (/ls)
100
0.01
0.1
1
10
lei
Q
Vo - DRAIN VOLTAGE (VI
I I
1.8
1.6
n
~
-=
0
-10 -8 -6 -4 -2
Switching Time vs V D
and Temperature
~
a:
V,N
PULSE
T - TEMPERATURE (~CI
~
w
V GEN S
.l
I
9
j:
--!-
COloff)
2
"
1"-
RGEN '" 0
"
C
I
""
"
V+
?-15V
3
;;;
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
5
w
ilia:
......
...
VI
rDS(on) vs
Temperature
100
f - FREQUENCY (MHzl
Siliconix
3-29
2-Channel Drivers with SPSY
and DPSY FEY Switches
designed for . • •
H
Siliconix
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG154 contains four junction-type field-effect transistors (JFETs) designed to function as two double-pole singlethrow electronic switches. Level-shifting drivers enable low-level inputs (0.8 to 2.5 V) to control the ON-OFF state of each
switch. With a positive logic "0" at the driver input the switches will be OFF. With a positive logic "1" at the input the
switches will be ON. In the ON state each switch will conduct current in either direction, and in the OFF state each switch
will block voltages up to 15 V peak-to-peak. ON series resistance is < 50 ohms, and ON shunt leakage is < 2 nA. With both
drivers in the "switch OFF" state total power consumption is < 750 /lW. Switches have make-before-break action. The
DG152 is similar to the DG154 except that it contains two SPST switch functions. It is recommended that the DG181 (or
DG182) and DG184 (or DG185) be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
,.
v+
Dual·ln-Line Package
Flat Package
11
D2C=~=;~~~~~~~S2
NC
NC
v-"
NC
V+
NC
VR (ENABLE)
NC
IN,
D,c::~~~"""!=~~~s,
7
8
TOP VIEW
ORDER NUMBER:
DG152AL
SEE PACKAGE 5
ORDER NUMBERS:
DG152AP OR DG152BP
SEE PACKAGE 11
Flat Package
Dual-I n-Line Package
,.
D2C=~==~~~~~~~S2
v+
NC
V R (ENABLE)
'----ft::::J IN,
0, C::~~~""";~!=~~:::JS'
7
8
TOP VIEW
ORDER NUMBER:
DG154AL
SEE PACKAGE 5
ORDER NUMBERS:
DG154AP OR DG154BP
SEE PACKAGE 11
'0
V R (ENABLE)
"'Common to Substrate and Base of Package
SWITCH STATES ARE FOR LOGIC "1" INPUT
3-30
Siliconix
DG154
v-'2
ABSOLUTE MAXIMUM RATINGS
V+ to V- or VD .. .
..
VD to V-.
VD to VS· .... ..
V+toVR···· . ..
V+ to VIN1 or VIN2.
VR to V- . . . . . . . .
VIN1 to VIN2· ....
VIN1 or VIN2 to VR
VIN1 or VIN2 to V-
. . .. . · . . .
.. ·.
.. ·.
.. ·.
.·. · . · . . . · . · .
. · . · . · . . . · . ·.
.. .
·. ·.
..
.. . · .
..
·.
·.
.. ..
·. · .
36 V
36 V
±22 V
25 V
25 V
25 V
±6 V
±6 V
30 V
..... 30mA
Current (Any Terminal) ....... . . .
--65 to 150° C
Storage Temperature ......... . . .
Operating Temperature (A Suffix) . .. . . . -55 to 125°C
-20 to 85°C
(B Suffix) . . . . . . .
Power Dissipation'
Flat Package" .. . . .................. 750mW
14 Pin DIP'" . . . .................. 825mW
'All leads welded or soldered to PC board.
"Derate 10 mW/oC above 75°C.
"'Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
OGI52A.DGI54A
DGI52B.DG1S4B
-5S"C
25"C 12S"C -20"C
2S"C
8S'"C
50
50
100
100
100
150
1
100
5
100
1
100
5
100
-2
-100
-5
-100
CHARACTERISTIC
1
'""2
rDS{on)
Drain-Source
ON ReSistance
4~
ISloft)
Source OFF
Leakage Current
-3S
5T
--.,.C IOlolf)
~H
'""8
Dram OFF
Leakage Current
Channel ON
+ IS(on)
IO{on)
Leakage Current
Input Current,
IINL
Input Voltage Low
10
IINH
Input Current,
Input Voltage High
11
ton
Turn-ON T,me
12
toff
Turn-OFF Time
9
-~
-0
0.1
0.1
120
2
60
60
0.6
1.6
Source OFF
Capacitance
2.4" Typ
14~ COloff)
-I
15 C COlon) + CSlon)
Drain OFF
Capacitance
2.4 Typ
-16
Off Isolation
20
_LP
21
-
22
y
1+
1-
POSitive Supply Current
3
TEST CONDITIONS. UNLESS NOTED:
V+' 15 V. V-' -15 V. VR' 0
vD:7.5V
IS - --10 rnA
VIN: 2.5 V·
VD' 5.5 V
VS: 7.5 V. Vo : -7.5 V
VS' 5.5 V. VO' -5.5 V
VIN: 0.8 V'
VO' 7.5 V. Vs : -7.5 V
Vo : 5.5 V. Vs : -5.5 V
VO' VS' -7.5 V
VIN : 2.5 V'
VO' VS: -5.5 V
VIN:0.8V'
"A
100
"S
VIN : 2.5 V'
See SWitching Time Test ClrcuLt
II1II
VS:O.IO:O
pF
VO:O.IS:O
~
f == 1 MHz
:::a
-
D
VD' VS: 0
> 60 dB at 1 MHz··
o
en
RL' 75 n
Negative Supply Current
-1.8
Reference Supply
Current
-1.4
-1.5
Positive Supply Current
25
-25
25
-25
-25
-25
Reference Supply
Current
IR
100
3.3
··2
Negative Supply Current
4
..
2.8 Typ
Typ
1+
-18 1_S
19 ~ IR
17
150
nA
..
2.4 Typ
..
2.4 Typ
..
..
2.8 Typ
Capacitance
4
!Z
1
2
13 Y CSloff)
_N
Channel ON
4
UNIT
ca
mA
VIN == 2 5 V*, One Channel ON
"A
VIN '" 0*, All Channels OFF
...:e--
n
::r-
.,.CD
*VIN must be a step function with a minimum rise and fall rate of 1 V/}J.s.
LODC + NC
"'Typical values are for DeSIGN AID ONLY. not guaranteed and not subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
+15V
SWITCH
jV'
LOGIC ·'1" "SW. ON
INPUT
SWITCH
LOGIC
3V
OUTPUT
INPUT
D,
s,
100. +Vs
-'
2.5V ft r < 10n5
VD
toff. -VS
If<100s
0--'
;'---
IN,
SWITCH
INPUT
SWITCH
OUTPUT
LOGIC
INPUT
Vs
D.•
0-
-
'DO
n
D.t
f..-1
I--
-
-::toff
Vs == ±7.5 V A SUFFIX
VS'" ±5.5 V B SUFFIX
Siliconix
--r:
-Q-t>J
6VR
DV
V-.¢
-15V
Rt
'KR'i
"-::-
Jet
135PF
[REPEAT TEST FOR S3
(DGl54J, AND IN2' S2
AND S4 (00154)]
VO=VS--RL + rOSlon)
3-31
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
100
w
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
Capacitance vs V D
w
u
10
~
§~
ua
9
j
±1DV
6
>e- W
,.
::>
8
0
~
10
0.1
85 105 125
25
45
85
65
125
lOS
4
2
0
V IN - LOGIC INPUT
-2
I
z
T - TEMPERATURE (OC)
8
"
•
T - TEMPERATURE fOCI
4
Supply Current vs
Temperature
0
I
II
2
VIN vs Temperature
VR -0
I
V+=+12V
2
~ ~ ~N
"~
;;
oS
V-=-1SV
e-
15a:
0
>
a:
OFF
::
"""'"
0
1
-
-
0.2
-2.
25
75
T - TEMPERATURE (OC)
-50 -25
125
I
-
r--
w
4
""~
6
2
0
25
50
75
100
T - TEMPERATURE (OCI
>
e-
0
I!:
::>
-2
125
>
4
0
90
-4
....
#1
3'~P: 1
I T~l
0.1 pF
i'-.
80
50
g
i'-.
40
Vr
30
20
3.8pF
I
a
V+ = +12 V, V- = -18 V
V R '" 0, RL =7SU
10
VIN
O!
220 ~;i RMS
106
V GEN = 0
1\
107
108
f - FREQUENCY (Hz)
Siliconix
V
I I
11\
V GEN = -1 V
V
I
-6
4
2
0
I
II
V GEN =-5V
V
-2
/
-4
-6
-1.0
0
1.0
20
t-TIME (",s)
0
105
IL
a
V\
0 -4
I
0
2
Equivalent "OFF" Circuit
I
3·32
~0
~
URlon)1
0
I\,
VGEN =+1 V
-4
-2
~
"
II-Con)1
o.•
II
-2
100
70
~
2
0
::>
0
-75
80
~
1.0
0
I
Z
p
~
4
I+(~
'e-e-"
~I
"
1.4
'"
6
1.8
::>
i!:
a:
2.2
\
VGEN =+5V
-2
2.6
~
z
V-
w
""~
0.2
~
r
IS(off) vs Temperature
f.-
1.2
0.8
Rki
10K"::"
1000
I
1.8
1.6
!
--Q-t>--J
Va
10
Vo - DRAIN VOLTAGE (V)
1
D
"::"
-50 -25
";:
V,N
5V
PULSE
1
1
~
V GEN S
.l
I
~
0
=
3.0
4.0
Drivers with Differentially
Driven Normally Open and
Normally Closed FEY Switches
designed for . . .
H
Siliconix
CJ
Q
...
CI"
W
BENEFITS
• Switching High Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
•
Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG 163 contains four junction-type field-effect transistors designed to function as electronic switches_ Level-shifting
drivers enable low-level inputs (2 to 3 V) to control the ON-OFF state of the switches. The driver inputs are connected
differentially so that with input IN2 connected to a 2.5 voltage reference, a positive logic "0" at input IN 1 will turn switches
1 and 3 OFF and switches 2 and 4 ON. A positive logic "1" at IN 1 will turn switches 1 and 3 ON and switches 2 and 4
OFF. The normally-grounded VR terminal may be used as an "Inhibit" terminal, in which case all switches may be held
OFF with a positive voltage applied to YR. In the ON state, each switch conducts equally well in either direction, has a
series resistance of < 15 ohms, and a shunt leakage of < 2 nA. In the OFF state the switches will hold off voltages up to
15 V peak-to-peak. Switches have make-before-break action. The DG161 is similar to the DG163, except that it contains
two FET switches instead of four. It is recommended that the DG186 and DG189 be used for new designs.
PIN CONFIGURATIONS
J>
SCHEMATIC DIAGRAMS
Flat Package
~
-
Dual-In-Line Package
G
o
°2
'2
NC
IN2
NC
V-"
NC
V+
NC
VR(lNHIBIT)
NC
IN,
0,
ca
CIt
--...~
ft
:r-
"
7
TOPVIEW
ORDER NUMBERS:
DG161AL
SEE PACKAGE 5
ORDER NUMBERS:
'---'-_.1-.::":":"'---..1.""':::''-'---' DG161AP OR DG161BP
DG161
CD
(II
'2
V-
SEE PACKAGE 11
Flat Package
°2 C:::=;:::::i~~F~~'2
LOGIC
a
1
SW 1
SW3
SW2
SW4
OFF
ON
ON
OFF
_
~
IN2
04
v-*
NC
V+
°3
V R (INHIBIT!
IN,
'3
o,=~~f9!=:~= "
7
8
TOPVIEW
ORDER NUMBER: DG163AL
SEE PACKAGE 5
• Common to Substrate and Base of Package
SWITCH STATES ARE FOR V IN1
= LOGIC "1"
INPUT AND
V IN2 = 2.5 V BIAS (POSITIVE LOGIC)
Siliconix
DG163
'2
V-
3-33
..8
..
•o..
"•
ABSOLUTE MAXIMUM RATINGS
V+toV- ...... · . · . . . . . · . ..
V+ to VD or Vs
·.
·.· .
VD orVs to V- . . · . · . ..
·.
VD to VS .........
V+ to VR .........
..
V+ to VIN1 or VIN2. · .
VR to V- .... .... · .
·.
VIN1 tOVIN2····· · .
·.
VIN1 or VIN2 to VR · .
·.
. . . ...
VIN1 or VIN2 to V-
Cli
0
36
36
32
±22
25
25
25
±6
±6
30
•••
Current (Any Terminal) . . . . . . . . . . . . . . .... 30mA
Storage Temperature .......... . . . . --65 to 150° C
Operating Temperature (A Suffix) .
-55 to 125°C
(B Suffix) ....... -20 to 85°C
Power Dissipation'
Flat Package** ... . .................. 750mW
14 Pin DIP"* . .. . .................. 825mW
*All leads welded or soldered to PC board.
"Derate 10 mWtC above 75°C.
*"Derate 11 mW/oC above 75°C.
V
V
V
V
V
V
V
V
V
V
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
-5S-C
1
12
13S
IS
f----J
,
13
rw
r-
D
I.
300
15
300
-5
-100
0.1
0.1
2
4
4
4
IIN2L
0.1
0.1
2
4
4
4
'IN1H
Input 1 Current,
Input 1 Voltage High
120
60
60
150
100
100
I'N2H
Input 2 Current,
Input 2 Voltage High
120
150
100
100
Turn·ON Time
60
1
2.5
60
ton
Turn·OFF Time
Source OFF
Capacitance
..
..
3 Typ
Channel ON
Capacitance
28Typ
Off Isolation
,+
'R
-5.5 V
=
Vo '" Vs = -7.5 V
VIN' = 3 V" (SW',3 ON),
VO'" Vs '" -5.5 V
V,Nl = 2 V* ISW2,4 ON}
=
2.5 V*
V,Nl '" 3 V·
VIN2 '" 3 V .. , V,Nl '" 2.5 V*
"'
..
..
..
a
See SWltchmg Time Test CirCUit
VS'" 0, 10
pF
3 Typ
Typ
=:
0
f'" 1 MHz
Vo '" O,IS = 0
VD"'" Vs
=-
a
AL -" 100 n, CL '- 3 pF
Positive Supply Current
4
4.4
Negative Supply Current
-2
-2.2
Reference Supply
Current
-2
-2.2
Negative Supply Current
25
-25
25
-25
Reference Supply
Current
-25
-25
Positive Supply Current
,-
VIN1 '" 2 V' ISW',3 OFFl.
VIN' = 3 V"' (SW2,4 OFF)
7,5 V. Vs - -7.5 V
V,N2 = 2 V*, VINl
Typ", 50 dB at 1 MHz·"
,
=
Vo '" 5.5 V, Vs
"A
3 Typ
2
Vo
V,Nl =2V·
1.5
2.5
3 Typ
Drain OFF
Capacitance
Is=-10mA
VIN' '" 3 V' (SW, ,3 ON),
VIN' '" 2 V" (SW2,4 ON)
7.5 V
=:
Vo '" 5.5 V
VS:: 5.5 V, Vo '" -5.5 V
nA
-100
Input 2 Current,
Input 2 Voltage Low
toff
"
Vs =-7.5V,VO--7.5V
Input 1 Current,
Input 1 Voltage Low
'R
,+
-El
23 V
2'
15
TEST CONDITIONS, UNLESS NOTED:
v+ -15 V. v- - -15 V. VR - O. V'N2 - 2.5 v·
Vo
I'N1L
21 ~
-p
-
35
Leakage Current
COlon) + CSlon)
20
_S
20
1000
-2
Channel ON
15 V CSloffl
N
r-A
16M COloff)
r - 'C
17
1a
85"C
1000
10
Drain OFF
Leakage Current
10(on) + 'Slon)
•
10
UNIT
2S-C
Leakage Current
H
r10
r-N
11
r12
-20 C
20
Source OFF
T
C IOloff)
ra
15
125·C
30
ON ReSistance
I . W'Stoff)
,
15
25"C'
15
Drain-Source
rOSlon)
B SUFFIX
ASUFFIX
mA
V,Nl '" 2 V· or VIN1 '" 3 V*. One Channe' ON
"A
V'Nl '" V'N2 "" 0.8 V*, All Channels OFF
·VIN must be a step function with a mu'Umum rise and fall rate of 1 VIps.
··TYPlcal values are for DESIGN AID ONLY, not guaranteed and not subJect to production testing.
LODF+NIP
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
lOGIC
INPUT
t,<10ns
tf<10ns
SWITCH
INPUT
SWITCH
OUTPUT
3·34
3V
2.5V
lOGIC "1"" SW. ON
-'
2.5Vj
o-oJ
1'--D.•
-
U
Ion
ton.+VS
toff. -VS
S2
VS ",±7.5VASUFFIX
S,
+lt~+
....
·'~'~"':,::;rp.t>-J
Vs
0-
-y'N2
SWITCH
INPUT
r--
-
A--~
INPUT
0.1
toff
n
VO"'VS _ _R_L_
Rl + roSlonl
Siliconix
-=-
"~.vbv-
0V R
O2
-15 V
,,~:
SWITCH
OUTPUT
le
Vo
L
-=-IJ5PF
(REPEAT FOR S3ANO S4)
(DG163)
c
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
u;
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
Capacitance vs V D
"
glaD
CAPACITANCE IS
w
u
MEASURED FROM
TEST TERMINAL
TO COMMON.
z
~
i1i
~
I--
10
::>
o
-
"
-
VIN - LOGIC INPUT
-2
Z
--
>-
I
0.1
25
45
65
85
105
125
T - TEMPERATURE (DC)
-2
Supply Current vs
Temperature
VIN(th) vs Temperature
2.6
~
2.2
I-- I--
>-
1.B
::>
1.4
~
u
~
z
0
-2
11-(on)1
~0
I'R(on)l_
T
-
f--
25
50
75
100
125
:;;
~
0
>-
-50 -25
25
50
75
100
T - TEMPERATURE (OC)
"OFF" Isolation vs RL
and Frequency
20
~
z
0
i=
30
n
50
60
125
~
0
I
VGEN=OV
-4
-
f-
I
:rCD
....-
VGEN=-lV
I
j
VI
I\,
L I
.!
I l
I--VGEN"'-5V
j.--"
IV,NI
"OFF" ISOLATION ~ 20 LOGIVLI
A - DRAIN OF "OFF" SWITCH
B - SOURCE OF "OFF" SWITCH
I
70
iV
A
/I
SIGNAL
SOURCE B
Z '" 50 n
n
BO
~
I
-4
rf
..'"_.
/1-
-2
H'
RL'" 100
o
CIt
-2
I
-
/'
A
-6
I
I,
40
j
~
I
!
RL = lK
~
0
111111111
=, v
r'l I IV
:s
Q
1\
>
IIIIIIIII
III
ca
0
10
/'
»
V GEN
-
-4
>
0.2
0
IV
~
f---
I
T - TEMPERATURE fOC)
VrENI" 5~
1\
I--
1.0
0.6
-
-4
-
1+(0;2.-
.s
-50 -25
I-
~
g
T - TEMPERATURE (UC)
z
;;
-
,-
>
u
0
-'"
:;;
~0
ii:
Sl
I I
I I
o
-
I-'"
10
u
"::>
0.2
-
~
w
I I
0.4
/
u
0
Vo = +10 V
I
c- t 100
::>
..I..--t""
:::;::: .- hf.... V
0.6
1>-
vo!=-Jov :::;:::
.....-1:]
1.6
L
OPF
o
125
Vo - DRAIN VOLTAGE (VOLTS)
1.8
-2
-4
-6
90
100
0.01
0.1
10
0-
Q
f----~ CD~On)
-
"oz
......
c
...
Q
100
i-FREQUENCY (MHz)
Siliconix
3·35
Drivers with Differentially
Driven Normally Open and
Normally Closed FEY Switches
designed for . . .
H
Silicanix
BENEFITS
• Switching High.Frequencies
• Switching in Satellite
Applications
• Portable, Battery Operated
Circuits
• Low Signal Distortion Switching
Circuits such as Audio Switching
•
Higher Signal Bandwidth Switching Capabilities
o OFF Isolation> 60 dB @ 1 MHz
• Better Radiation Resistance than PMOS
Drivers
o Bipolar Drivers
• Minimizes Standby Power Requirements
o < 1 mW Standby Power
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
DESCRIPTION
The DG164 contains four junction-type field-effect transistors designed to function as electronic switches_ Level-shifting
drivers enable low-level inputs (2 to 3 V) to control the ON-OFF state of the switches_ The driver inputs are connected
differentially so that with input IN2 connected to a 2.5 voltage reference, a positive logic "0" at input IN 1 will turn switches
1 and 3 OFF and switches 2 and 4 ON. A positive logic "1" at IN1 will turn switches 1 and 3 ON and switches 2 and 4 OFF.
The normally-grounded VR terminal may be used as an "Inhibit" terminal, in which case all switches may be held OFF with
a positive voltage applied to VR. In the ON state, each switch conducts equally well in either direction, has a series resistance of < 50 ohms, and a shunt leakage of < 2 nA. In the. OFF state the switches will hold off voltages up to 15 V peak-topeak. Switches have make-before-break action. The DG162 is similar to the DG164, exceptthat it contains two FET
switches instead of four. It is recommended that the DG187 (or DG188) and DG190 (or DG191) be used for new designs.
PIN CONFIGURATIONS
SCHEMATIC DIAGRAMS
Dual-I n-Line Package
Flat Package
NC
NC
NC
NC
NC
D,=~='f=~~~::JS,
~OPVIEW
.------r------,--....,
ORDER NUMBER:
DG162AL
SEE PACKAGE 5
Flat Package
,TOP VIEW
ORDER NUMBERS:
DG162AP OR DG162BP
SEE. PACKAG E 11
Dual-In-Line Package
'2
DG162
v-
DG164
V-
V-'
V+
V R (INHIBIT)
IN,
D,=~=f"::;;;~~~::JS'
7
•
TOP VIEW
ORDER NUMBER:
DG164AL
SEE PACKAGE 5
LOGIC
0
1
SW1
SW3
SW2
SW4
OFF
ON
ON
OFF
TOPVIEW
ORDER NUMBERS:
DG164AP OR DG164BP
SEE PACKAGE 11
*Common to Substrate and Base of Package
SWITCH STATES ARE FOR V IN1 = LOGIC "1" INPUT AND
V 1N2 = 2.5 V BIAS (POSITIVE LOGIC)
3-36
Silicanix
,2
ABSOLUTE MAXIMUM RATINGS
36 V
36 V
36V
±22 V
25 V
25 V
25 V
±6 V
±6V
30V
V+to V- .....
V+ to VD or Vs
VD or Vs to vVD to Vs· . . . . . . . .
V+toVR·· ...... .
v+ to VIN1 or VIN2.
VR to V- . . . . . . . .
VIN1 to VIN2 .... .
VIN1 or VIN2 to VR
VIN1 or VIN2 to v-
Current (Any Terminal).
. . . . . . . . . 30mA
--65 to 150° C
Storage Temperature ..
Operating Temperature (A Suffix) .... .
-55 to 125°C
(B Suffix) ..... . -20 to 85°C
Power Dissipation*
Flat Package** . . . . . . . . . . . . . . . . . . . . .. 750 mW
14 Pin DIP*** . . . . . . . . . . . . . . . . . . . . . . 825 mW
*All leads welded or soldered to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25"C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
A SUFFIX
-5S"C
1
12
13
S
14 W
'--S
16
1___
50
Drain-Source
ON Aesistance
roston)
12S"C
50
100
UNIT
_20ue
2S"C
85~C
100
100
150
5
100
C 'Cloft)
Leakage Current
______________________
~
____
~
____
Channel ON
Is
'O(on) + 'S(onl
____
~
____
~
__5
~
Input 2 Cu"ent,
0.1
0.1
0.1
0.1
Vo - Vs - -5.5 V
100
4
"N2L
Input 2 Voltage Low
11
"N1H
:~:~: ~ e~~::;;'Hi9h
120
60
60
150
100
100
IIN2H
Input 2 Current.
Input 2 Voltage High
120
60
60
150
100
100
13
1--'4
I___
V,Nl = 2 V·ISW,.3 OFFI,
V,Nl = 3 V' ISW2,4 OFFI
V,N1 = 2 V· (SW2,4 ON)
VIN1 =2V·
10
12
-7.5 V
VO'" 5.5 V. Vs = -5.5 V
~
VIN2::: 2 V·, VIN1:::: 2.5 V·
I---~~--------~--~~~--~----+---~----~--~----~--~
1---
v. Vs -
f-V,::O~=_V.:'S'-=-,-7:_.5::-V,.,---_1 V I N 1 = 3 V' ISW 1 ,3 0 N I
-5
:~:~: ~ ~~~;::;' Low
[---
100
____
Vo - 7.5
nA
100
leakage Current
IIN1 L
9
~
-2
-7.5 V
VS'" 5.5 V. VD = -5.5 V
~~-----------o-r-ai-n-o-F-F--------t-----1---72-+--,~070-+-----t-----t----~
H~
Is=-10mA
V,Nl = 3 V' ISW'.3 ONI.
V,Nl = 2 V' ISW24 ONI
Vo - 5.5 V
VS· 7.5 V. Vo
Leakage Current
7
TEST CONDITIONS, UNLESS NOTED:
V+ "" 15 V. v- = -15 V. VR = D. V'N2::Z 2.5 V·
5!
100
Source OFF
'Sloff)
B SUFFIX
2SoC
ton
Turn-ON Time
0.8
1
1-"'''----------=~=-=~----_t----_1--=_+----_+----_+---=_t----4
Drt~of~f__________T_u_'n_.0_F_F_T_i_m_e____-+____~---1.-6-+-----+-----+____
2-+____
VIN2 = 3 V*, VIN1 = 2.5 V*
ps
See Switching Time Test Circuit
-r____-+______________~r_----------------1
15 y CS(off)
~:~~:t~~:
2.4·Tvp
2.;~YP
---~r_--------_=~~~------t_----r_~_r----t_--_f----~--~
16 M CO{off)
~~:~:i~;:e
2.4·~VP
2.';~yp
Capacitance
2.8 Typ
2.8 Typ
I--'r-------~--~~--~----+_=_+_--_r--_+~_+--~
C
Channel ON
....
'I"
I~
CO(on) + CS(onl
Vs = 0,10::: a
pF
......
~
a0~
Vo::: 0, IS::: O f : : : 1 MHz
_
Vo = Vs:::: a
1--'8~+-O-"-I-so-'a-ti-on------------------~------r_---T,yrP->-6-0-d,B_a_t_'_M_H,Z·_·____, -____+-____~-R~L~--7-5-n----------------------------ICEI
19
1+
Positive Supply Current
IA
~:!;~~7ce Supply
4
4.4
-2
-2.2
;~ S 1-'_-___________N..:e.:.ga_ti_ve..:S..:u.:.p~PI.:.Y_C.:.u'_'e..:n.:.tt_----1_---;:.2_+_____+----_+---2::.2=-t_---l
21
~
rnA
~
VIN1 ::: 2 V" or VIN1 ::: 3 V·, One Channel ON
~.
i~Pr.I-+----------~p:-OrsitriV-.~S-Up-pr,Y-C~U-'-r.-nt-t----~---2-5-t-----t-----t---25--t-----~----+----------------------------------1 ~
-
·~
___
23~r,-------------N-e-~-ti-~-SrU-p-PI-Y-C-U'-'e-n-t+-----~---2-5-+-----+-----+----25--+---~
Reference Supply
-25
pA
.
"::r
VIN1 ::: VIN2 = 0.8 V .. , All Channels OFF
CD
-25
·VIN must be a step function with a minimum rise and fall rate of 1 V/lJs.
"·Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
LOOF + NC
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC "1" .. SW. ON
3V,r-----..,.
LOGIC
INPUT
t r <10ns
2.5 V..,r-
tf< 10ns
0---'
SWITCH
INPUT
SWITCH
OUTPUT
Vs
-I-':-:};:==+=~-0 .•
o-f--..l
-
ton
0.1
r--
~
t.ff
Siliconix
3·37
TYPICAL CHARACTERISTICS
rDS(on) vs
Temperature
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
Capacitance vs V D
100
CAPACITANCE IS
MEASURED FROM
TEST TERMINAL
TO COMMON.
-- --
- - -
f= 1 MHz
Is= 0
l - f-
colon)
CO(offl
-50 -25
0
25
50
75
o
100 125
-10 -8 -6 -4 -2
0
2
4
6
8 10
T _ TEMPERATURE 1°C)
Vo - DRAIN VOLTAGE IVI
Switching Time vs V D
and Temperature
.3
1.'
1.2
'"
"
>=
0 .•
~
1
vJ""Jov ~
1.6
..
IS(off) vs Temperature
1000
I I
1.•
~
p.- k
...
't..- i--"'"
~
0.6
..-r
-55 -35 -15
I- '"
~~
"
"iil
§
z
0.1
85 105 125
25
45
65
85
105
2.2
-
oS
I-
~
a:
"">
it
1.B
z
~;;:
0
I
I
1.0
0.6
0.2
50
75
100
-
-
125
~
VGEN"'+lV
-4
~
w
IIRlonl'
'1'-
r-
!i
~>
-
n
...
-50 -25
T - TEMPERATURE (CCI
25
50
75
100
T - TEMPERATURE (OC)
125
~
"
VGEN = 0
0 -4
I
0
-2
Z
80
>=
70
,~
60
...
0.1 pF
#1
3~P; 1
t T --;r-t
0
S
~
"
~
P
-'
,.~
40
30
20
Vi"
I
o
V+a+12V.V-=-18V
VR"'O,R L =750
10
3.BpF
10'
107
10·
f - FREQUENCY (Hz)
3·38
I I
IA
VGEN=-5V
V-
-2
IL
-4
0
-6
_1.0
I
1.0
/
2.0
I-TIME (loIsl
V1N ~ 22~ ~I~ RMS
105
V-
-6
g
"
50
I I
VGEN=-lV
I I
-4
90
i
~
Equivalent "OFF" Circuit
100
1\ V-
-2
>
"OFF" Isolation vs R L
and Frequency
'"'
I\..
-2
II-(onll
-
1\
VGEN"+ 5V
-2
--
I+(o,:!.-
1.'
OJ
25
i
1/
Supply Current vs
Temperature
"
0
125
T _ TEMPERATURE (OC)
2.6
-50 -25
-2
,.
VIN(th) vs Temperature
Z
-
VIN - LOGIC INPUT
I
j
T - TEMPERATURE (CC)
:>
4
~2:
t-
I
I I
65
l - f-
>-
10
'"a:
I I
25 45
~
o
~
~
0
I I
5
w
100
""
V O -+l0V
I
o
~
a:
J.......-r"'"
I
0.2
!z
I
Vo '" +10 V
ton
0.4
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
Siliconix
3.0
4.0
Monolithic 4-Channel Driver
with PMOS Switches
designed for . . .
H
Siliconix
BENEFITS
• Make-Before-Break Switching
i.e. Feedback Resistor Switching
in Variable Gain Op-Amps
• Low Leakage Switching such
as Sample and Hold Circuits
•
Easily Interfaced
o TTL, CMOS, DTL Direct Drive Compatibility
•
Reduces External Component Requirements
o No Interface Components Required
o Voltage-Limiting Diodes Protect PMOS
Gates
DESCRIPTION
The DG172 contains four MOS field-effect transistors designed to function as electronic switches_ Level-shifting drivers
enable a low-level input (0.8 to 2.0 V) to control the ON-OFF condition of each switch. In the ON state, each switch will
conduct current equally well in either direction. In the OFF state, the switches will block voltages up to 20 V peak-to-peak.
Positive logic "0" at the driver input will turn each switch ON. A common driver terminal VL may be used to clock all four
switches by switching the device from the ENABLE mode (;;. 4 V) to the INHIBIT mode (.:;; 0.4 V).
FUNCTIONAL DIAGRAM
v+
SCHEMATIC DIAGRAM
'2
'0
13
VL
V+
12
3
s, 00-11-----0": ....----r--/-OO
3
S2 ''''4-/-_ _ _--l.....,._, ' - - _ - - . ,
0
S3~'~----+--l.....,.-,
2
S4 <>-i-----+--+--+-O"I
9
I
I
I
:
:
I
I
I
I
I
I
S,
lEI
i i l
IN,
__ J
'4
II
____ ...J
~
S2
:a
I
6
IN4
'3
_______ JI
0-+--+-«""""
-
Q
,
0
CD
S3
."_.
eft
~
2
054
::r-
CD
SWITCH STATES ARE FOR LOGIC "1" INPUT.
(POSITIVE LOGICI
PIN CONFIGURATIONS
S3
S4
o
V-
Flat Package
fit
5
Dual·ln-Line Package
C:::=::;=::::ij2-~::::;;~ S2
S,
V+
NC
V-·
IN4
,
8
TQPVIEW
ORDER NUMBERS: DG172AP OR DG172BP
SEE PACKAGE 11
ORDER NUMBER: DG172AL
SEE PACKAGE 5
·Common to Substrate and Base of Package
Siliconix
DG172CJ
SEE PACKAGE 7
3·39
ABSOLUTE MAXIMUM RATINGS
V+to V-. · . · . · . .. . ... . · .
· . · . 36V
V+ to VD . · .
· . · . .. . . . · . · . · . · . 25 V
25 V
V+ to Vs
· . ... · . · . · . · . · .
·.
. . ·. · . ·.· .
36V
VstoV-. · .
. . · . · . · . · . · . 36 V
VD to V-. · .
Vs to VD.
· . · . .. . .. . · . · . · . · . 25 V
VL to V-.
· . . . · . .. . · . · . · . · . 30V
VL to VIN
· . ... ... . .... . · . ±6 V
VL to VR·
· . ... . ... . .... . · . ±6V
±6V
VIN to VR
· . · . . ......... · . · .
Current (Any Terminal) · . ...... . . . . · . · . 20mA
Storage Temperature (A & B Suffix) ....
-65 to 150°C
(C Suffix) .......
-65 to 125°C
-55 to 125°C
Operating Temperature (A Suffix)
-20 to 85°C
(B Suffix)
o to 70°C
(C Suffix)
Power Dissipation'
Flat Package"
750mW
14 Pin DIP (ceramic)'"
825mW
14 Pin.Plastic DIP"" .
470mW
'All leads welded or soldered to PC board
"Derate 10 mWfC above 75°C
-"Derate 11 mWfC above 75°C
""Derate 6.3 mWfC above 25°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
-!-
~ s
-2.
4
-
-
Drain·Source
rOSlon)
ON ReSistance
W
i
IOlon) + 'S(on)
7 I
IINL
a N IINH
9
ton
10 D toff
-'" Y
11 N CSloff)
-A
12 M COloftl
-I
13 C COlon) + CSlon)
1If
--ji-
TaS
--'.:. U
250
350
600
Input Current,
Input Voltage High
Turn-ON Time
Turn-OFF Time
Source OFF
Capacitance
Drain OFF
Capacitance
Channel ON
Capacitance
DG172B
2SOC
150
225
500
150
225
500
200
300
600
200
300
600
8SoC
-1
-1000
-5
-100
-10
-4000
-10
-300
-10
4
4000
-0.5
-0.5
-0.5
-1
0.1
0.1
10
0.1
0.3
0.75
300
1.0
-1
-1
mA
1
10
1
"A
VIN '" 5 V
"'
See SWitching Time Test Circuit
Vo = VS= lOV
0.08 Typ·
0.5 Typ*
Vs = 0, 10 = a
pF
VO=VS=O
RL'" 100n,cL:::: 3pF
5.7
2.1
C~r~~:~ce ~upp y
-3.6
-3.6
-3.6
1+
POSitive Supply Current
Negative Supply Current
IL
Logic Supply
10
-20
4.5
10
10
-20
4.5
10
10
-20
4.5
10
IR
Reference Supply
Current
-4.5
-4.5
-4.5
Logic Supply Current
-S.l
Curre~t
f = 1 MHz
VO=O,IS=O
Typ> 50 dB at 5 MHz'"
I
VIN =0.8 V
VIN = 0
28 Typical·
IL
VIN = 2 V
VO=-10V,VS=10V
10
0.5
1
3
IS"" -1 rnA
VIN = 0.8 V
VS=-10V,VO=10V
nA
18 TYPical·
Positive Supply Current
Negative Supply Current
~L I
Vo'" 10 V
0
VO--l0V
Vo
"
-1
3
-5.1
5.7
2.1
1+
TEST CONDITIONS. UNLESS NOTED:
V+ = 10 V, v- == -20 v, VL '" 5 V, VA = 0
UNIT
5 Typical *
-T,"Y
~
24
DG172C
2SoC
_2oDe
-4
Channel ON
Leakage Current
Input Current.
Input Voltage Low
12SOC
Off Isolation
19 P IR
~p
150
200
450
Leakage Current
Drain OFF
leakage Current
6
15
150
200
450
Source OFF
ISIoff)
5 ~ ICloff)
14
-5SoC
DG172A
2SOC
3
-5.1
5.7
2.1
mA
~ VIN = 0, One Channel ON
"A
mA
"A
VIN = 5 V, All Channels OFF
IR 0
mA
CMD
"'Typical Values are for DESIGN AIO ONLY, not guaranteed and not subject to production testing
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs ; constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC
5V---,
INPUT
t r < 10ns
2.5V
tf< 10ns
0
SWITCH Vs
INPUT
J~~~~~
3·40
0
,.---
'1
VS"'+10V
Va
-
VL
SWITCH
INPUT
LOGIC
INPUT
D.•
/
'on
Va
'--
~
0.1
IN,
It
'off
-=
-Y
V+
-Q-t>J
6VR
OV
{114 CIRCUIT SHOWN}
REPEAT FOR 52 - 54'
Siliconix
I
1--
SWITCH
OUTPUT
D,
Vo
135PF
Rhi :keL
2."-=
v-6
-20 V
RL
Va = V5 RL + rDS(oni
TYPICAL CHARACTERISTICS
rOS(on) vs Vo and
Temperature
en
800
g
"'"
700
"'uz
600
"~
80
~
u
"'z
500
o
cr
~ 200
,
"U>u
",
12S"C
2S"C
V
~ 300
z
~
CAPACITANCE IS MEASURED
FROM TEST TERMINAL TO _
70
cr
z 400
:J
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
Capacitance vs Vo or Vs
I"'<; ~~1.:
1t
-55"C
u
~
100
f==lMHz
50
40
-10 -8 -6
-4 -2
0
2
4
6
8
20
V
eOloffi
l/
J
I
a
2
eSloff)
-10 -8 -6 -4 -2
10
COlon)
30
10
c
l - I-
C~MMpN.
60
4
6
B
10
Vo OR Vs - DRAIN OR SOURCE VOL lAGE (VOLTS)
Vo - DRAIN VOLTAGE (VOLTS)
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
Switching Time vs Vo
and Temperature
IO(off)fIS(off) vs
Temperature
800
./
600
-
-
!
~
;:
Vo "'+10V
,;...400
I
200
I-II-
Vo -
~
o
>
toff
10V
~>
~~
9
V O -+l0V-
Vo -
o
25
45
65
~
:§
10V 85 105 125
~
T - TEMPERATURE 1°C)
100
,--r"'T"-r-,-,---r"'T"-r-,-,
80
~+-~-+~--~+-~-+~~
'\...
Supply Current vs
Temperature
:J
u
-4
VINH=5V
60
_~L_
-ILL
40k--'.....++-:±=='-+-+~-+--1
"
20
.....
IlH AND 'RH
IL~
'RL
:f.
-
~
2
~
0
"'~
-2
V 1N - LOGIC INPUT VOLTAGE (VOLTS)
5
25
45
65
T - TEMPERATURE
85 105 125
fOe)
-
a
o
ca
~GEr'~
o -4
>
~
~
o
.
CIt
:c--
4
I
>-
>5
-55 -35 -15
~
in
o
>-
,
:I>
V1NL=OV
ir
~
9
lEI
~GEr5,V
-2
1fi
~
LO,GlC ,'N
-2
0.1 L..'!-..J......J..-'_'-..J......J...-l.--''--'
105
125
65
25
45
85
liN vs VIN and Temperature
;
2
:>
T - TEMPERATURE (OC)
"
-
Z-'
t:.l :7
5
I-
>-:J~
-l:;: "on
-55 -35 -15
"'
.A
i--""'"
"
0
-2
"::r
~GErO,V
-4
CD
VI
"OFF" Isolation vs RL
and Frequency
100
~
z
;:
70
~
60
it
50
S
P
"
",,-z
~
"-
I,......
RL -100n
JJj
N-lJ
10
II
III
II
V?EN , -l, V
-4
1111111
RL '" lKfl
20
-2
1111111
40
30
I
I LlIllll
'I
90
80
0
SIGNAL
SOURCE B
Z= son.
....
-2
III
"OFF" ISOLATION
ILl
20 LOG
I~I
IV ,
L
A - DRAIN OF "OFFHSWITCH
B - SOURCE OF "OFF" SWITCH
III
106
~
7
~GEN,' ~v
-4
-6
-,
t-TIME (jJs)
'08
f - FREQUENCY (Hz)
Siliconix
3-41
;r-~~~~------~--~~------~~----------~====~
·i High-Speed Driver with
=
JFET Switches designed for...
...
"...
"
siIi!!nix
0-
Q
I
o
GO
Q
• Fast Acquisition Speed in
Sample and Hold Circuits
• Low Leakage Switching
Applications i.e. Sample and
Hold Circuits
• High Frequency Signal
Switching such as Video Signals
• Low Distortion Switching.
Audio Signals
• Low Level Switching in Low
Impedance Circuits
• Fast, Low Resistance DI A
Ladders
BENEFITS
•
Eliminates Large Signal Error
o < 2 nA Leakage from Signal Channel in
Both ON and OFF States
•
Increased Current Handling Capabilities
o 200 mA Maximum Switching Current
•
Higher Bandwidth Switching Capabilities
o Cross-Talk and OFF Isolation> 55 dB
at 1 MHz (75 n Load)
•
Easily Interfaced
o TTL, DTL, RTL Direct Drive
Compatibility
•
Less Signal Distortion than CMOS or PMOS
Switches
o Constant ON Resistance
• Low Voltage Drop Across Switch in the ON
State
o rds(on)';;; 10 n
DESCRIPTION
The DG180 series contains two to four N-channel junction-type field-effect transistors (JFET) designed to function as
electronic switches. Level-shifting drivers enable low-level inputs (0.8 to 2.0 V) to control the ON-OFF state of each switch.
The driver is designed to provide a turn-off speed which is faster than turn-on speed, so that break-before-make action is
achieved when switching from one channel to another. In the ON state each switch conducts current equally well in either
direction. In the OFF condition the switches will block voltages up to 20 V peak-to-peak. Switch-OFF input-output feedthrough is> 60 dB at 10 MHz, because of the low output impedance of the FET-gate driving circuit.
FUNCTIONAL DESCRIPTION
3-42·
SCHEMATIC DIAGRAM (Typical Channel)
PART
NUMBER
TVPE
RON
(MAX)
DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG191
DualSPST
Dual SPST
DualSPST
Dual DPST
Dual DPST
Dual DPST
SPDT
SPDT
SPDT
Dual SPDT
Dual SPDT
Dual SPDT
10
30
75
10
30
75
10
30
75
10
30
75
IN
o
Siliconix
PIN CONFIGURATIONS
Q
Metal Can Package
Flat Package
Dual-In-Line Package
,.
S2
DUAL SPST
D,
S,
S2
D,
D2
NC
NC
NC
NC
IN,
IN2
V+
V-"
S,
S2
D,
D2
NC
NC
NO
NC
IN,
IN2
V+
V-
vL
vR
IN,
SWITCH STATES ARE
vL
FOR LOGIC "1"INPUT
vR
vL
TQPVIEW
(POSITIVE LOGIC)
.,
...•
.,
7
ORDER NUMBERS:
DG1BOAAOR DG1BOBA
DG1B1AA OR DG1B1BA
DG1B2AA OR DG1B2BA
SEE PACKAGE 2
C
I
......
Q
00
CIt
ft)
-.
~
ft)
8
TOPVIEW
ORDER NUMBERS:
DG1BOAP OR DG1BOBP
DG1B1AP OR DG1B1BP
DG182AP OR DG182BP
SEE PACKAGE 11
ORDER NUMBER:
DG1B1AL
SEE PACKAGE 5
*Common to Substrate and Base of Package
(II
*Common to Substrate and Case
Dual-In-Line Package
Flat Package
D.
DUAL DPST
03
D,
0,
5,
5,
IN,
IN,
V.
v-"
SWITCH STATES ARE
,
FOR LOGIC "1" INPUT
TQPVIEW
(POSITIVE LOGIC)
ORDER NUMBERS:
DG183AP OR DG183BP
DG184AP OR DG184BP
DG185AP OR DG185BP
SEE PACKAGE 12
ORDER NUMBERS:
DG184AL OR DG185AL
SEE PACKAGE 5
*Common to Substrate and Base of Package
Metal Can Package
SPDT
Flat Package
-~
Dual-I n-Line Package
~
NC
SWITCH STATES ARE
FOR LOGIC "1"INPUT
(POSITIVE LOGIC)
NC
NC
D,
".------u-~ D2
S,
S2
IN
NC
o
CG
.."
CIt
V-"
V+
VL
D
,
~
-.
,
TOPVIEW
ORDER NUMBERS:
DG186AA OR DG186BA
DG187AA OR DG1B7BA
DG188AA OR DG188BA
SEE PACKAGE 2
ORDER NUMBERS:
DG187AL OR DG1BBAL
SEE PACKAGE 5
'Common to Substrate and Base of Package
ORDER NUMBERS:
DG186AP OR DG186BP
DG187AP OR DG187BP
DG188AP OR DG188BP
SEE PACKAGE 11
~
ft)
(II
*Common to Substrate and Case
Flat Package
Dual-In-Line Package
DUAL SPDT
D.
LOGIC
SW 1
SW2
SW3
SW4
0
1
OFF
ON
ON
OFF
SWITCH STATES ARE
FOR LOGIC "1" INPUT
(POSITIVE LOGIC)
O2
52
IN2-:'L~''''
V+
VLc=~~~,r--'~~~~VR
TOPVIEW
ORDER NUMBERS:
DG190AL OR DG191AL
SEE PACKAGE 5
'Common to Substrate and Base of Package
Siliconix
ORDER NUMBERS:
DG1B9AP OR DG189BP
DG190AP OR DG190BP
DG191AP OR DG191BP
SEE PACKAGE 12
3-43
.,.
.-..
CD
ABSOLUTE MAXIMUM RATINGS
CD
......
0
en
v+ to v-
36V
V+ 10 VD
33 V
VD 10 V-
33 V
±22V
VD 10 Vs
VL 10 V-
0-
Q
I
...
0
0
CO
n. 75 n .
Ion Only .
Currents (S or D) 30
Storage Temperature
Operating Temperature (A Suffix)
(8 Suffix)
36V
VL 10 V,N .
BV
VL'OVR
BV
.
V,NIOVR.
BV
VR'oV- .
VR 10 V,N .
27 V
. 30mA
. 200mA
-65 to 150"C
-55 to 125°C
-20 10 85°C
Power Dissipation·
Metal Can-· •
14 Pin Dlp··- •
16 Pin DIP-·_· .
Flat Pack··*·· .
* All leads welded or soldered to PC board.
*·Derate 6 mWfC above 75C1C.
*··Derate 11 mWfCabove7SoC.
****Derate 12 mWrCabove 7Sc C.
***·*Oerate 10 rnwtC above 7SoC.
2V
Current (Any Terminal except S or 01 .
.
30mA
450mW
825mW
900mW
900mW
Q
ELECTRiCAL CHARACTERISTICS All DC parameters are 100% tested at 25·o C. Lots are sample tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
-ss"c
25°C
12s"C
_20G e
Drain Source
rOSlon)
,
f-; ,
I- ,
10(onl+ ISlon)
lOSS
SaturatIon Ora1l'lCUrrent
"
8
'INl
Input Current,
Input Voltage Low
IINH
InpUICurrent,
Input Voltage HIgh
'0'
Turn-ON T,me
tolf
Turn-QFFT'me
Cs(off)
Source OFF Capacllanc:e
21 TYPIcal'
CO(off)
Oreon OFF Capaellance
17 Typu:al'
CO(on) + CSt on)
Channel ON Capacitance
'7 TYPlcal 4
9
c~
~
f-;;"
f-;-;
f-;;;
Y
N
W
4
gf-;"
Oraln-Source
ON Reslnance
rOSlonl
ISloff)
Source OFF
leakage Current
IOloffi
OralnOFF
leakage Current
Q
•
1010n)+ ISlon)
leakageCurrenl
E
,
" "I-
IINl
InpUICurrenl,
InpulVollage low
~
B
IINH
Input CUrrent,
InpUI Voltage HIgh
°"'
~~
C
Source OFF
Cap8(.ltance
COloff)
CapacItance
COlon) +CSlon)
ChannelDN
Capacitance
Oraln-Source
ON Resl51ance
I-
~f-;
ISloff)
Sourc:eOFF
leakage Current
IOloff)
OldonOFF
leakage Current
81-
:- •
" Ii~I-
1010n)+ 1510n)
Channel ON
leakage Current
7
IINl
Input Current,
'nput Voltage lew
8 8
Ii 9
i;~
01-
IINH
Input Current.
Input Voltage HIgh
"
II-" ,
13
C
30
VO"SV,IS"O
VO"VS"O
RL ~75n
TYPlcal>55dBatl MHl'
30
Is"-10mA
VO"-75V
SO
50
V+~IOV,V
100
VIN~OBVor2.0V
Vs -7.5V, Vo --7.SV
·'0
VO"VS"-7SV
·'00
-2S0
,A
"
VIN-O
VIN
~SV
See Switching TIme Tesl CorCUlt
9 TYPIcal'
VS"-SV,IO"O
6 TYPIcal'
"
14 TypIcal'
VO"-5V,IS"O
VO-VS"'O
RL=1SU
75
100
150
VO"-10V
100
VS" IOV, VO· -IOV,
V+-IOV,V-=-20V
'S,,-,OmA
VIN~08Vor20V
VS-IOV,VO--10V
VO" 10V, VS'" -IOV.
V+-,OV,V---20V
100
-200
-2S0
VIN~20VorO_8V
NOle2
VO" 10V,VS= IOV
100
VO"'VS=-10V
-250
V'N"O
,A
VtN"'SV
10
Turn-OFF TIme
9 TYPIcal'
COloffl
OramOFF
CapacItance
6 TYPIcal-
CO{on)+ CSlon)
Channel ON
c"pacltence
'4 TYPIcal'
See SwitchIng TIme Teu Coreult
150
VS"-5V.IO"'O
,F
V or 2.0 V to turn ON switch under test.
2. VIN
VO"-5V,IS-O
VO-VS=O
TYPIcal> 50 dB at 10 MHz
= 0.8
VIN m20VorO.BV
NOle2
VO" 7.5 V, VS" -7.SV
Source OFF
Capacitance
NOTES: 1. VIN
___ 20V
VO-l0V,VS--IOV,
V+-,OV,V-=>-20V
CSlell)
""
I-;.-
3-44
VIN -5V
VS"-SV,IO "0
,F
"
A
M
Note 2
150
CSloff}
rOSlon)
I-;
I--"4
VIN~2.0VorO.8V
_7.S V
300
TYPIcal >SOdBat ,OMHz
S
W
~
350
180
I14
1
7.5 V. Vs
VIN-O
"A
"
10
A
I-" ,
~
VO "'VS "-7.SV
loll
N
M
13
300
Vo -IOV, VS" _IOV
V+"'IOV,V---20V
2msecPuiseOuratlon
'0'
9
"
l-
VS-75V,V O --7.SV
T
;1Ii
Note I
.. -IOV
Vs-tOV.VO~-IOV,
C
H
VIN-08Vor2.0V
300
300 TYPIcal·
OFF IsolatIOn
,
I, ,
I,...:. ,
I,· IOmA
VO "-7,5V
See SWItching TIme Test CirCUIt
A
M
!l
Vo
7
!
~
15
Dram OFF
leakage Current
8
~
~
15
Channel ON
leakage Current
81-
25
V+~IOV,V-"'-20V
Source OFF
leakageCurrenl
15(011)
IOlolfl
~~
~~
15
VS~10V,VD
4
.f-
V+"15V, V---15V, Vl. -!iV,VR-O
25"c 85"C
15
ON Resistance
I-
TEST CONDITIONS, UNLESS NOTED:
BSUFFIX
ASUFFIX
= 0.8
Rla7SH
V or 2.0 V to turn OFF switch under test.
Siliconix
Note 1
ELECTRICAL CHARACTERISTICS Power Supply Current (25°C)
A OR B SUFFIX MAX LIMITS
DG18o,DG181
DG182,DG189
DG19o,DG19l
CHARACTERISTIC
DG183
DG184
DG185
DG186
DG187
DG188
1+
Positive Supply Current
1.5
3
1-
Negative Supply Current
-5
-5.5
-3
IL
Logic Supply Current
4.5
4.5
3.2
IR
Reference Supply Current
·-2
-2
-2
1+
Positive Supply Current
1.5
0.1
0.8
1-
Negative Supply Current
·-5
-4
-3
IL
Logic Supply Curren t
4.5
4.5
3.2
IR
Reference Supply Current
-2
-2
-2
TEST CONDITIONS, UNLESS NOTED:
V+= 15 V, V-=-15V, VL =.5V, VR =0
UNIT
0.8
AIIVIN=OV
mA
CMJA + NC - DG184,DG185
CMJA + NIP - DG183
All VIN = 5 V
CMJB + NC - DG18l, DG182,
DG190,DG19l
CMJB + NIP - DG180, DG189
CMJC + NC - DG187, DG188
CMJC + NIP - DG186
SWITCHING TIME TEST CIRCUITS
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as
per switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result
in spikes at leading and trailing edge of output waveform.
. .
DG1BO - DG185
VL
?-5V
1--
INPUT 8,
LOGIC
INPUT
VO=VS _ _
R_L_
RL + rOSlon)
11
-=-
5V
~
A.vR
DV
'5V
,Vee
SWITCH
?'5V
SWITCH
Ion. Vs = +3 V
toff. Vs '" -3 V IN,
DG1B6 - DG191
v+
I"L
INPUT
SWITCH
D,
S3
OUTPUT
'O".VS=+3V (
JC L Va
R1
3OD~-=-
toff,VS=-3V
-r
5,
"'----
coo:t
D3
SWITCH
OUTPUT
~
0,
V
IN~
13DPF
.~-'5V
n
(REPEAT TEST FOR
IN2 AND 8 2 )
3V
LOGIC
INPUT
t r < 10 ns
t1< 10 ns
1.5 V
Vo=Vs _ _R_L_
RL + rOSlon)
-=
_~YR
OV
O
RL
INPUT
V-
1
-" _I ~~PF
!
VEE
-15V
- -
(REPEAT TEST FOR
INZ' 52 AND 54)
-'
f-
D
NOTE: LOGIC INPUT WAVEFORM
IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE
"--
0--'
o
ca
LOGIC SENSE CONTROL
SWITCH
INPUT
SWITCH
OUTPUT
Vs
:±3 V
0.9 Va
0-
-
-~
::I
LOGIC "'" = SW. ON
CIt
~
~
--
0,1 Va
'0" I -
-
toff
~
It
::r-
APPLICATION HINTS*
CD
v+
Positive
Switch
Supply
Family
Voltage
(VI
vVL
Negative Logic
Supply Supply
Voltage Voltage
(VI
(VI
VIN
Logic Input
VR
Reference
Voltage
Supply
VINH MinI
Voltage VINL Max
(VI
IVI
III
Vs
Analog
Voltage
Range
(VI
10n
+15**
-15
+5
Gnd
2.010.8
-7.5 to +15
and
+10
-20
+5
Gnd
2.0/0.8
-12.5 to +10
30 n
+12
-12
+5
Gnd
2.0/0.8
-4.5 to +12
+15**
-15
+5
Gnd
2.010.8
-lOto+15
+10
-20
+5
Gnd
2.010.8
-15 to+10
+12
-12
+5
Gnd
2.0/0.8
-7to+12
75 n
* Application Hints are for DESIGN AID ONLY, not guaranteed and not
subject to production testing.
··Electrical Parameter Chart based on V+ = +15 V, V- = -15 V, VL = 5 V,
VR = Gnd.
Siliconix
3-45
.-I
TYPICAL CHARACTERISTICS
....
8
i..
8
t-
Supply Current vs Temperature
el
liN vs VIN and Temperature
100
"'-"'-~:""'"",:-l
V.Nl - a
t--t----t-t--t----t-t- V,NH = 5 V
"
0-
80
1"<;:1--+-1-+--+-1-+--+---1
60
1"- .....- ~IINL
I-+--+-.p....!_.....
40
r-+--+-t--r--+-~~~--i
20
I-+--+-t-+--+-t-+-i--i
'"
::i~
1l
b...
>-
~_
......
I
........
2
1+
I-
o~~~~~~~~~r
-55 -35 -15
5
25
45
65
"NH
-55 -35 -15
T - TEMPERATURE ("Cl
~
25
65
85 105 125
30n
7sn
DG18l
DG184
DG187
DG190
DG182
DG185
DG188
DG19l
rDS(on) vs Temperature
""oom~
Vo - -VA(max)
IS "-10mA
i'!
!!l
"';;;,,0
iiiII:
~
W1°MR
"
o
1000
~
i3
II:
rDS(on) vs Temperature
~
Z
rDS(on) vs Temperature
~m~~~~~
Vs = -v A (MAX).
10 1 rnA
z
II:
..
"
::>
51
z
II:
o
0
I
1
0
50
75 lOa
125
25
II:
T - TEMPERATURE lOCI
65
10
-55
130
120
EEHfHf=E
110
1-+--+-+-+-1--1-+1/-"<[/':./
9~~5~-3=5-_~'~5~5~2~5-7.~~OO=-~85~'~00~'25
-55 -35 -15
5
25
45
65
85 105 125
T - TEMPERATURE (OC)
Leakage vs Temperature
105
Switching Time vs VD
and Temperature
120
t-+-I--j----t-t--t---t--j--i
50L-~~~~~~~__~~~
-55 -35 -15
5
25
45
65
85 105 125
I D(off) vs Temperature
1000 ~~"F.::~~':T.""T.'~;="'=:F.,;,!,!
TEST LIMITS ~ ~ V+" 10 V. V - 20 V
BSUFFIX
V L =5V,V R =O
• ASUFFIX VO=-10V.VS=10V
.
65
T - TEMPERATURE (OC)
ID(off) vs Temperature
!
25
./
50~~~-~~~-~~~--
rei
-15
T - TEMPERATURE ("C)
Switching Time vs VD
and Temperature
]" 100I--I-I-Vo-7.5V
100 V+"'10V
V =-20V
~
100
T - TEMPERATURE (OC)
Switching Time vs VD
and Temperature
230 r-"'T'"--r-r-"'T'"--r-,-,,-,
T - TEMPERATURE
t=
ASUFFIX
z
II:
25
100
W
"0
::>
0
BSUFFIX
0
~
-50 -25
46
10 n
~
~
5
T - TEMPERATURE (OC)
DG180
DG183
DG186
DG189
9.
!
+--+-i-+--+-+--i
o==~~bd~========
85 105 125
=
1 I"'~~I~!'~I
1000 ~~~~~~~~~~~~
TEST LIMITS ~
v+ -10 V. v- - 20 V
=
• BSUFFIX
• ASUFFIX -
vL-SV.VR"o
VO=-10V.VS=10V
'00
_IO(on)
+ IS(onl
~~ 10~~~~~~~~~~~~
f-- BSrF~
~
1
ASUFFIX
0.1
25
T _ TEMPERATURE (Ge)
3·46
85
85
105
T - TEMPERATURE ("C)
Siliconix
125
0.1 1--'---1-.......-1.-'----''-'--'--'--....
25
45
65
85
105
125
T - TEMPERATURE (OC)
8...
TYPICAL CHARACTERISTICS (Cant'd)
Capacitance vs VD or Vs
10 n FET
Typical delay, rise, fall, settling times,
and switching transients in this circuit.
L
V+
V
?-5V
~
V GEN S
.l
IN
-Q-t>-J
LOGIC II
INPUT
~
w
D
""c:;
Va
-=
Rki
10K
I'O
~
L
"I
"
6-20V
V-
iVR
-=
f
16
~
r0-
1 8 - ~ COlon) + eSlon)
ro-
~DIO\f'- r= F
14
12
10
8
6
-8
-4
0
~
eSCoffl
r-
C~'O~- f -
CAPACITANCE ISMEASUREb
F~OM
_
TEST TERMINAL TO COMMON
0
-10 -8 -6 -4 -2
8
4
Voor Vs - DRAIN or SOURCE VOLTAGE (VOL lSI
If RGEN, RL or CL is increased, there
will be proportional increases in rise
and/or fall times.
r---.
.......
,..... ....... r-
2
...
...
Q
4
I
10
MHz
14
""c:;
;!
:
""I
"
N
~a
VINL" O.S v
VINH'"2V
f='
CO(onl + eSlon)
w
_'.
I
I
18
"'MHz
eSloff)
22
;!
C P
F
20
VINL -O.SV
VINH=2V
I
I
26
?'OV
RGEN = 0
-l-
30
Capacitance vs VD or Vs
30-75 n FET
0
2
4
6
8
10
Vo or Vs . DRAIN or SOURCE VOLTAGE (VOLTS)
.
I'
-Ii
Equivalent "OFF" Circuit
30-75 n FET
01 pf
w
~I 3:~PF 1 g
DG181, DG182, DG184,
DG185, DG187, DG188,
DG190, DG191
DG180, DG183, DG186
DG189
\ t T ~l
ViN
~
0
C;
""
0
6
5 iii
4
B
2
>
~>-
!::
2~
~
-
>-
0
"g
LOGIC INPUT
I
+4
"g(;
+2
->
10
5
0
4
I
2
0
r-- I --
=
200!!
,
'4
'2
0
VGEN-5V
I
IJ
w
II....
RL:::; 7SH
VIN >220 mV RM"
V GEN =5V
60
2
0
f
":;"
0
>
I-""
-2
>-
::>
~
VGEN - 0
I
0
IA
It ~
-2
-
I
2
0
o
>
.A
\
-2
'2
0
,
-4
-6
V
IA
-2
I
-4
VGEN=-5V
\
I
-10
1/
0
0.4
0.8
1.2
t - TIME haec)
0
CD
:s-
106
107
108
"OFF" Isolation vs Frequency
30-75 n FET
100
-6
V GEN '" -5 V
90
;;;
80
+5
0
70
0
:3
>=
I
-5
VGEN '" -10 V
ft
f - fREQUENCY (I-b)
5
0
20
105
os
z
-5
.
--~
VGEN = 0
::>
0
0
>
Zl::.
'i:~
/'
1/
-10
V GEN '" -10 V
1.6
0
0.4
08
12
t - TIME (iJs)
16
.....
60
"-
~
50
it
40
I
30
V+=+15V
v-= -15V
V R =0
10
VLOGIC '" +5 V
RL = 75 n
VIN L 220 mV RMS
P
»"1-' 20
0
105
106
107
108
f - FREQUENCY (Hz)
Siliconix
~
:s
(It
r---.
40
'2
--
a
o
ca
VA = 0 ,
VL=5V
~
w
>
IL
V+ 15V
V-=-15V
80 .......
~0
::>
14 pF
lOV
100
""C;
~
VGEN
ViN
+6
0
::>
0
,
lL
g
"OFF" Isolation vs Frequency
10 n FET
J
0
1
+5
~
0
LOGIC INPUT
+10
I
J
6
>-
1i:
\ ,t T+~l1
0.1 pf
0
I
VOEN - 10 V
~
Equivalent "OFF" Circuit
10 n FET
->"
Z
IL
+6
ir
;;
'4PF
200"
3-47
UI
Dual Monolithic SPST CMOS
Analog Switch
H
Siliconix
BENEFITS
designed for . . .
•
• Low Transient Switching
i.e. Sample and Hold Circuits
• Switching Multiple Signals
such as Multiplexing Inputs
• TTL Compatible Switching
Systems
• High Frequency Signal
Switching, such as Video Signals
•
Environmentally Rugged
o Latch-proof CMOS
Easily Interfaced
o TTL, DTL and CMOS Direct Control
Interface
Range
•
Over
Military
Temperature
Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
•
•
Reduced System Cross-Talk
o Break-Before-Make Switching
Eliminates Signal Error
o 10 pA Typical Leakage From Source or
Drain
o Low Charge Coupling
DESCRIPTION
The DG200 is a 2-channel, single-pole, single-throw analog switch which employs CMOS technology to insure low and
nearly constant ON resistance over the entire analog signal range_ The switch will conduct current in either direction with
no offset voltage in the ON condition, and block voltages up to 30 V peak-to-peak in the OFF condition_ The ON-OFF state
of each switch is controlled by a driver_ With a logic "0" at the input to the driver (0 V to 0_8 VI the switch will be ON,
and a logic "1" (2.4 V to 15 VI will turn the switch OFF _The input can thus be directly interfaced with TTL, DTL, RTL.
CMOS and certain PMOS circuits_ Switch action is break-before-make. For new designs, use the DG200A.
PIN CONFIGURATIONS
Metal Can Package
Dual-In-Line Package
v+ (SUBSTRATE AND CASEI
ORDER NUMBERS:
DG200AP OR DG200BP
SEE PACKAGE 11
v+
(SUBSTRATE)
DG200CJ
SEE PACKAGE 7
02
TOP VIEW
ORDER NUMBERS:
DG200AA OR DG200BA
'Optlonal (Normally Left Open)
SEE PACKAGE 2
SWITCH STATES ARE FOR LOGIC "1" INPUT (POSITIVE LOGIC)
SCHEMATIC DIAGRAM (Typical Channel)
v+
.---11-_--0 D
IN
SKu
·OPTIONAlINORMALl Y LEFT OPEN)
v-
3-48·
Siliconix
ABSOLUTE MAXIMUM RATINGS
Storage Temp. (A & B Suffix)
(C Suffix)
Power Dissipation (Package)'
Metal Can"
14 Pin DIP'"
14 Pin Plastic DIP""
-0.3 V, V+
0, -32 V
0,32 V
16V
-16V
30mA
20mA
VIN and VREF to Ground
Vs or VD to V+
Vs or VD to VV+ to Ground
V-to Ground
Current, Any Terminal Except S or D
Current, S or D
Current, S or D Pulsed
(1 msec, 10% Duty Cycle Max)
Operating Temp. (A Suffix)
I(B Suffix)
(C Suffix)
-65 to 150°C
-65 to +125°C
450mW
825mW
470mW
'Device mounted with all leads welded or soldered
to PC board .
"Derate 6 mWfC above 75°C
. "'Derate 11 mWfC above 75°C
····Derate 6.5 mWfC above 25°C
100mA
. -55 to 125°C
-20 to 85°C
o to 70°C
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25°C. Lots ale sample-tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
TVPt
25·C
CHARACTERISTIC
Minimum Analog Signal
A SUFFIX
-5SoC
±15
2SOC
125·C
±lS
'15
±15
"5
45
70
70
100
BO
BO
100
fDSlon)
Drain Source
ON ReSistance
45
70
70
100
80
BO
100
+0.01
2
100
5
100
-"5
'S'oft)
Source OFF
Leakage Current
-0.02
-2
100
5
100
~H
Drain OFF
+0.01
2
100
5
100
'O(oft)
Leakage Current
-0.02
2
100
-5
100
1
VANALOG
~
---t S
---T ~
T
--::- C
~
~
9
10 I
---,,- N
I~p
I-~
Handling Capability
Y,N - O.B V,
V D --l0V
IS=-1 mA
Vs - 14 V. Vo
14 V
14V, Vo
14 V
Vs
+0.1
2
200
-5
200
-0.1
0.0009
200
-10
-5
1
200
10
Vo Vs -14 V
Y,N - 2.4 V
"NH
Input Current
Input Voltage High
-2
-1
0.005
1
10
1
10
Peak Input Current
liN/peak)
ReqUired for TranSition
Inpul Current,
Input Voltage Low
Turn-ON Time
440
1000
1000
toff
Turn-OFF Time
370
500
500
CS(oft)
Source OFF
Capacitance
9.0
CD(ofil
Dram OFF
Capacitance
9.0
COlon) + CS(on)
Channel ON Capacitance
20
1+
-10
-1
-I
OFF Isolation
P
V'N=O.BV
V ,N = 15V
I
Y,N = 0 V
~ee
ns
pF
i
I
Switching Time Test CirCUit
I
I
Vo - Vs - 0, Y,N - a
+2.3
4
4
-2.3
-4
-4
Pos~tlve
+0.7
2
2
-06
-2
-2
I
n.
Y,N - 5 V. RL - IK
CL = 15 pF,
Vs = 7 VRMS, f = 500 kHz
dB
"
ICXE
~
CD
1ft
··"OFF" Isolation .:;} 20 log VSIVO' VS:= Input to OFF switch, VO:= output
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown, Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
+1~Vv+
O?N
VREF
SWITCH
INPUT
LOGIC "0" = SW ON
,,----
(r' 20 ns
SWITCH
INPUT
0
IN,
LOGIC
INPUT
V5
SWITCH 0
OUTPUT
5,
vs=+sv
50%
tf" 20ns
VI
Ion
-
Vo
-=-
0'
0,
~
-Q-t>J "hi
IK"_
11
-
_¢_1
Vo
J,CL
135PF
(REPEAT TE-ST FOR IN21
v-
6GND
OV
SWITCH
OUTPUT
-1SV
"L
VO=VS--RL + rOSlon)
'off
Siliconix
o
...~_.
Both Channels "OFF," V1N:O 5 V
..... FunctlonaJ operation IS possible for supply voltages less than 15 V, but the Input logic threshold will shift. For V+:= -V- = 10 V, 1.4 V may be
applied t~ V REF termmal. The V R EF termmal has R IN::::: 21 K U. See Applications SectIOn.
3.5 v-----.
~
(It
Both Channels "ON," VIN = 0
·IO(on)IS leakage from driver mto "ON" sWitch.
~~~~~
J>
CD
rnA
NOTES:
tTypical Values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
-a
f= 140kHz
V O =O,V'N=5V
25
Negative Supply Current
Negative Supply Current
1- Standby
V ,N=2.4V
14 V
VS=O,V'N=5V
POSitive Supply Current
Supply Current
14 V
See Curve 'IN vs V1N
-10
72
'--""21 Su 1I~
1+ Standby
nA
~A
-150
-.0015
19
I~
n
= 10 mA
Leakage Current
"NL
1-
SWitch ON IS
V D - 10 V
Channel ON
ton
16 N
I-A
17 M
I-I
18 C
V
'D(on)
14
I~v
v+ = 15 V, v- "" -15 V. Gnd = 0, VREF = Open*u
Vo 14V,V S Vo - -14 V, Vs
Vo Vs 14 V
13
I~D
TEST CONOITIONS. UNLESS NOTED:
BIC SUFFIX
UNIT
-201 2SoC
851
DoC
lOoe
3-49
TYPICAL CHARACTERISTICS
rOS(on) vs Vo and
Temperature
rOS(on) vs Vo and Power
Supply Voltage
Typical delay, rise, tall, settling times, and
switching transients in this circuit.
V+" +15 V
V-=-15V
I
...
125,1c
i--
-~5·~-'"
.
A
.......
~55!C
A - V+ = .... '5 V, v- = -15 V
B -V+ =+l2V, V-= -f2V
C -V+ =+lOV, V-= -lOV
D-V+ =+8V.V-=-BV
o
-15
-10
-5
10
10
-5
15
15
Vo - DRAIN VOLTAGE (VOL lSI
Vo - DRAIN VOLTAGE (VOLTS)
Switching Time
vs Temperature
IS(oft) or I o (off)
vs Temperature"
,.
It RGEN, RL or CL is increased, there will
be proportional increases in rise and lor tall
RC times. Applying VGEN to 0 rather than
S results in much greater spikes.
V+=+15V
V-=-15V
800
]
~
>=
z
600
f-
400
":;:
"
....-:
~
-----
~
I-:"'"
tr
I
f
w
~
g
~~
~6
52:1
200
-55 -35
15
5
25
45
65
85
105 125
;;
-"
I-
V+o:+15V
II
-200
I
-150
r
VGEN'" 10V
V-=-15V
5
2~.~
6
4
12S"C
f-
~
2
Z
U -100
§
=!
\
-55"C
15
I
20
r-.....
I
II:
II:
a
-2
10
IO(on) vs Temperature"
-2SO
LOGIC INPUT
I
15
T - TEMPERATURE (OC)
T - TEMPERATURE (OCI
2
.;;
z
o
r- ....,
4
"
VGEN=5V
2
-so
]
1
='C0.01 25
TVPV Th 2
VIN - lOGIC INPUT VOLTAGE (VOL lSI
2
45
65
105
85
T - TEMPERATURE (OC)
VTh (Input Logic Threshold)
Supply Current
vs Temperature
vs Power Supply Voltage
~0
~ I»"
,..,. ,..,.
~ I»"
:10
~
~~
~
I I
I I
.......
II:
l:
"<;
9
~
l:;;;
-!c
o
10
11
12
13
14
15
V+ = IV-I. POWER SUPPLY VOLTAGE (VOLTS)
IL-
11-1 BOJH
I IT
J
5
25
C~AN~ELS
T -1-~FF
45
65
85 105 125
5
0
5
I
0
-1
t-TIME {/lsI
Siliconix
/'
VGEN = -tOY
5
T _ TEMPERATURE (OCI
*The net leakage into the source or drain is the n·channel leakage minus the p·channel
leakage. This difference can be positive, negative, or zero depending on the analog
voltage and temperature, and will vary greatly from unit to unit.
3-50
VGEN = -5 V
I-+-li I
- -,1.
-55 -35 -15
4
6
8
f-
>
-2
0
0.5
f-
0
1+, ii-I BOTH CHANNELS ON
f-
VGEN = a
2
V+=+15V
v""j=-1 5V
t<::\
2
-4
1.5
~
r
125
TYPICAL CHARACTERISTICS (Cont'd)
"OFF" Isolation Equivalent Circuit and Data
'F-
0.1 pF
'00
V+ II +1SV,V
=
-15V
VGND" 0
2.5pF
lSI
l
2'~rF
IGI
IDI
"
1.3K
:::l6.6PF
°i9C--
~r
II'T2_
Vs
4.2K
O'i~
O'~fF
t'-
0
0
I
0
1.3K
'\
Vs '" 2.2 VRMS
' \ 75"
lKU
VD
'f 'n-
I
0
I
In--
ClOAD = 15 pF
""I::::
0
'0·
1- FREQUENCV (H:r.)
~
>~~! ~ -4i 1=j:::j::j:j:tttlt:=f:::j:j::tt:IlIt=:t=ml*l
i-9~~+H~-+~~»-+-H+~
Application Hints'
V,N
V+
VVREF
Logic Input
Positive Negative Reference
Voltage
Supply Supply
Pin
V,NH Mini
Voltage Voltage Connection
V,NL Max
(V)
(V)
(V)
(V)
+15"
Vs or
VD
Analog
Voltage
Range
(V)
-15
Open
+12
-12
Open or
1.4 V
2.4/0.8
-12 to +12
+10
-10
1.4 V
2.4/0.8
-10 to +10
-8
1.4 V
2.4/0.8
-8 to +8
+8···
0 r-rTTTTmr-"T"TTTTTTrr--r-rrrrrm
~ §-l~~+H~-+~~»-+-H+~
APPLICATIONS
2.4/0.8
€"
-225
I-Httftltt--f-t+tlttlt-+HtttRl
~ ~50~~+H~-+~~»-+-H+~
~
-15 to +15
-6 7s
I-Httftltt--f-t+tlttlt-+HtttHl
,,'
,,'
,0'
FREQUENCY (HI)
• Application Hints are for DESIGN AI D ONLY, not
guaranteed and not subject to production testing.
""Electrical Characteristics chart based on V+ = +15 V,
V-= -15 V, VREF = Open.
-J:.
~
"'Operation below ±8 V is not recommended.
II
Logic Inputs
Logic input circuitry protects the input MOS gate from static transients. A series MOS device shuts off when V,N exceeds
the positive power supply. Negative transients are clamped to ground by a diode clamp.
The input voltage characteristics have a current spike occurring at the transition voltage when the logic goes from V,NH
to V,NL. If a series resistor is used for additional static protection, it should be limited to less than 4.7 Kn to insure
switching with worst case current spikes.
The Function of VREF
VREF is an internal connection which allows the user to establish the logic threshold voltage at which the switch changes
state. The actual threshold voltage is equal to the voltage on the VREF pin. VREF is internally connected for a 1.4 V
threshold at V+ = +15 V. For other thresholds and/or supply voltages, one may connect VREF to a voltage source or
resistive divider whose output voltage is equal to the desired threshold. The internal impedance of VREF is 21 Kn ±30%.
Additionally, to adjust VREF, a single pullup resistor can be used from the VREF pin to a positive supply voltage to shunt
the upper internal divider resistor. The equation below shows the calculation of the shunt resistor for the desired logic
threshold voltage - this calculation is based on nominal internal resistor values, which are ±30% in absolute magnitude.
The adjusted trip point voltage (VREF) should be limited to an upper level of 5 V to avoid input logic switching transition
hysteresis.
R1 x
R2(~-1)
RSHUNT} _ R2
(f-')]
Calculation of RSHUNT
Where
R1
R2
~
~
220 KH:
23 Kn
nominal values,
±30% run to run
Example: for V+ = 15 V, VTRIP = 5 V, using nominal R1, R2 calc RSHUNT = 58 KH.
Siliconix
3·51
o
en
CO
...~--
"CD:rIII
; Dual Monolithic SPST
§ CMOS Analog Switch
H
Siliconix
designed for . . .
BENEFITS
•
Analog Multiplexing
•
Servo Control Switching
•
Video Signal Switching
•
Remove Switching under TIL Logic
Control
•
Environmentally Rugged
o 44V Power Supply Maximum Rating
o Static Protected Logic Inputs
o Latch proof
•
Easily Interfaced
o TTL and CMOS Compatible without
Pull·Up Resistors
•
Pin for Pin Compatible with
o Analog Devices ADG200
o Harris HI200
o Intersil DG200
o Siliconix DG200
DESCRIPTION
The DG200A designed on the Siliconix PLUS-40 CMOS process provides solid state switch action with 70 ohms contact
(ON) resistance and very high OFF resistance. True switch action takes place over the full analog signal range of ±15 V, with
Break-Before-Make operation to o/event momentary shorting of signal inputs.
PIN CONFIGURATIONS
Dual·ln·Line Package
Metal Can Package
V+ (SUBSTRATE AND CASEI
v+
(SUBSTRATE)
ORDER NUMBERS:
DG200AAA OR DG200ABA
SEE PACKAGE 2
ORDER NUMBERS:
DG200AAK OR DG200ABK
OR DG200ACK
SEE PACKAGE 9
DG200ACJ
SEE PACKAGE 7
02
TOP VIEW
SWITCH STATES ARE FOR LOGIC "1" INPUT (POSITIVE LOGIC)
SCHEMATIC DIAGRAM (typical channel)
v+o---......---r--~~-----
GNOo---....I
IN X
0---"""......- .....--'
~--~--~~-----Oox
v-o---~-----~~-----*-------~
3·52
Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VV+ . . . . . . . . . . . . . .
GND . . . . . . . . . . . . . .
Digital inputs 4 , VS, VD .
· . .... . . . . . . . . . . . 44 V
· . ....
. . . . . . . . . . . 25 V
. . · . .... -2 V to (V+ +2 V) or
20 mA, whichever occurs first.
Current, Any Terminal Except S or D
30mA
Current, S or D
20mA
Current, S or D Pulsed
(1 msec, 10"10 Duty Cycle Max)
100mA
. -55 to 125°C
Operating Temp. (A Suffix)
(B Suffix)
-20 to B5°C
(C Suffix)
o to 70°C
Storage Temp. (A & B Suffix)
(C Suffix)
Power Dissipation (Package)'
Metal Can "
14 Pin DIP*"
14 Pin Plastic DIP""
-65 to 150°C
-65 to +125°C
450mW
B25mW
470mW
'Device mounted with all leads welded or soldered
to PC board.
"Derate 6 mWfC above 75°C
"'Derate 11 mWfC above 75°C
""Derate 6.5 mWfC above 25°C
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
Typl
CHARACTERISTIC
1
VANAlOG
I~
25'C
Minimum Analog Signal
Handling Capability
1--;-
rOS{on)
Drain Source
ON Resistance
I- S
4 W
I-I
5 T
I-C
6 H
' Sloff)
Source OFF
Leakage Current
1-
'Oloff)
Drain OFF
Leakage Current
7
l-g
Channel ON
19
'Olon?
10
I-I
11 N
leakage Current
U
T
13
1---,-;;1--'-'-
=15
=15
45
70
70
100
80
=15
80
100
45
70
70
100
80
80
100
21
'----n
S
U
P
!l
Vo = 10 V
Vs = + 14 V. VO'" - 14 V
5
-5
+0.01
2
100
5
100
-0.02
-2
-100
-5
-100
+0.1
2
200
-5
200
V,N =0.8 V
IS = -1 rnA
Vo = -10V
Vs = -14 V. Vo = 14 V
100
-100
VD"14V.VS--14V
V,N = 2.4 V
nA
Vo = -14 V. Vs = 14 V
VD=VS"14V
III
V,N =0.8V
-0.1
-2
-200
-5
-200
0.0009
-1
-10
-1
-10
V,N = 2.4 V
0.005
1
10
1
10
V,N = 15 V
-.0015
-1
-10
-1
-10
Turn·ON Time
440
1000
1000
toff
Turn-OFF Time
370
500
500
Charge Injection
-10
Vo = Vs = -14 V
pA
~
:I
G
V,N = 0 V
ns
See Switching Time Test Circuit
pC
CL - 1000pF. VGEN -
9.0
av. RGEN -
-o
CG
Oll
.
CIt
Vs = O. V,N = 5 V
-.~
"CD:I'"
f = 140 kHz
Drain OFF
Capacitance
9.0
Channel ON Capacitance
25
OlRR3
OFF Isolation
75
CeRR
Channel to
Channel Crosstalk
90
1+
Positive Supply Current
1-
Negative Supply Current
pF
Vo = O. V,N = 5V
Vo = Vs = O. V,N = 0
V,N = 5 V
:20
V
100
2
-2
ton
Source OFF
TEST CONDITIONS. UNLESS NOTED:
V+ =15V.V- = -15V.Gnd =0.
UNIT
-100
+0.01
Input Current
Input Voltage Low
Capacitance
=15
-0.Q2
"NL
CDlon) + CSlon)
'---;g
=15
Input Current
Input Voltage High
15
a
I- 0
V
16 N CSloff)
A
1 - MI
17 C COloff)
l-----;s
-55'(;
I'NH
I-P
12
25'(;
MAX LIMITS
BIC SUFFIX
201
851
125'(; 0'(;
25'(; 70'(;
A SUFFIX
dB
Vs = 2 Vpp
0.8
2
2
-.23
-1
-1
NOTES:
rnA
III
Zl = 7511
f= 1 MHz
Both Channels "ON", or "OFF" VIN = 0 or 2.4 V
ICME
1. Typical Values are for DESIGN AID ONLY. not guaranteed and not subject to production testing.
2. ID(on) is leakage from driver into "ON" switch.
3. "OFF" isolation
~. 20
log VSNO. Vs = input to OFF switch. Vo = output
Sx. Ox
4. Signals on
or INX exceeding V+ or V- will be clamped by internal
diodes. limit forward diode current to maximum current ratings.
Siliconix
3·53
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for VS = constant with logic input waveform as shown. Note that VS may be + or - as per
switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC "0" •
~~~~
sw ON
SWITCH
INPUT
3V
VS=+5V
t,<
SWITCH
OUTPUT
S,
o-r-----if
20nl
tf< 20ns
RL
Vo = Vs RL + rOS(on)
. CHARGE INJECTION TEST CIRCUIT
AVO ~ MEASURED VOLTAGE ERROR DUE TO CHARGE IN) EeTICN
THE ERROR VOLTAGE IN COULOMBS IS .6.0= C L x 6.V o .
OIRR OFF ISOLATION TEST CIRCUIT
CCRR CHANNEL TO CHANNEL
CROSSTALK TEST CIRCUIT
+15V
+15V
~r---·v+~----------'
501l
DG211
ANALYZER
CHANA
CHAN 8
-15V
C· .001p.F/I . heF
CHIP CAPACITORS
3-54
c = ,001/J.FIf ,1J.1F
CHIP CAPACITORS
Siliconix
CCRR=20LOG
I~I
V D2
Quad Monolithic SPST CMOS
Analog Switch
H
SilicDnix
BENEFITS
designed for . . .
•
• Low Transient Switching
i.e. Sample and Hold Circuits
• Switching Multiple Signals
such as Multiplexing Inputs
• High Frequency Signal
Switching
• TTL Compatible Systems
•
Environmentally Rugged
o Latch-proof CMOS
Reduced Switching Error
o Low Charge Coupling
•
Easily Interfaced
o TTL, DTL and CMOS Direct Control
Interface
Range
•
Over
Military
Temperature
Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
•
•
Reduced System Cross-Talk
o Break-Before-Make Switching
Eliminates Signal Error
o 10 pA Typical Leakage From Source or
DESCRIPTION
Drain
The DG201 is a 4-channel single pole signal throw analog switch which employs CMOS technology to insure low and nearly
constant ON resistance over the entire analog signal range. The switch will conduct current in either direction with no offset
voltage in the ON condition, and block voltages up to 30 V peak-to-peak in the OFF condition. The ON-OFF state of each
switch is controlled by a driver. With a logic "0" at the input to the driver (0 V to O.B V) the switch will be ON, and a logic
"'" (2.4 V to '5 V) will turn the switch OFF. The input can thus be directly interfaced with TTL, DTL, RTL, CMOS and
certain PMOS circuits. Switch action is break-before-make. For new designs, use the DG201 A.
--
PIN CONFIGURATION
Dual-In-Line Package
IN1
IN2
0,
5,
ORDER NUMBERS:
DG201AP OR DG201BP
SEE PACKAGE 12
J>
::I
a
o
DG201CJ
SEE PACKAGE 8
5,
ca
0,
IN,
._.
CIt
-...=_--'-=-r-
~
·Optional (Normally Left Open)
SWITCH OPEN FOR LOGIC "1" INPUT (POSITIVE LOGIC)
ft
:r-
SCHEMATIC DIAGRAM (Typical Channel)
CD
v+
til
r---1I-~--O 0
IN
23K 11
* OPTIONAL (NORMAL LV LEFT OPEN)
v-
SilicDnix
3-55
ABSOLUTE MAXIMUM RATINGS
-0.3 V, V+
0, -32 V
VIN and VREF to Ground
Vs or VD to V+
Vs or VD to VV+ to Ground.
O,32V
V- to Ground.
-16V
Operating Temperature (A Suffix)
(B Suffix)
(C Suffix)
Power Dissipation (Package)'
16 Pin DIP"
16V
Current, Any Terminal Except S or D
Continuous Current, S or D
Peak Current, S or D
'Device mounted with all leads soldered or welded
to PC board.
"Derate 12 mWfC above 75°C
"'Derate 6.5 mWfC above 25°C
70mA
-65 to 150°C
-65 to 125°C
Storage Temperature (A & B Suffix)
(C Suffix)
900mW
470mW
16 Pin Plastic DIP'"
30mA
20mA
(pulsed at 1 msec, 10% duty cycle max)
-55 to 125°C
-20 to 85°C
o to 70°C
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25° C. Lots are sample-tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
TYPt
CHARACTERISTIC
BIC SUFFIX
ASUFFIX
2SOC
_5S o C
2SOC
12Sc C
_20 c CI
8SoCI
700 e
±15
:'.t5
200
200
5
250
250
100
100
100
o°c
1
."
'"2's
'-;
"....::;
VANALOG
Minimum Analog Signal
Handling Capability
:t15
rOSlon)
Drain-Source
ON ReSistance
115
75
T'
~ CI'SIOff)
Source OFF
Leakage Current
I~
IOfoff)
Dram OFF
Leakage Current
'O(on)·
Dram ON
Leakage Current
,~ H,
7
,~
,~
10 I
'_N
11 P
I- u
12 T
113
I~
Input Current,
Input Voltage Low
ton
Turn-ON Time
CS(off)
17
CD(off)
Drain OFF
Capacitance
COlon) + CS(on)
Channel ON
Capacitance
1-
19
-.0004
"NL
20
S
1,-=-= u
:!:15
175
175
1
-1
1
-1
1
250
250
100
100
100
-1
1
.003
200
200
--5
5
-5
5
-5
-1
1
-100
200
-200
-10
10
-100
-.0004
-1
5BO
370
1000
500
-10
-1
1+
1-
nA
Vs 14V,VO 14V
VD 14V, Vs- 14V
VD- 14V. Vs - 14V
"Io(on)
IS
VIN = 0.8 V
VIN-2.4V
V,N 15 V
-10
See Curve 'iN vs V,N
VIN=O
ns
See SWitching Time Test Circuit
Vs = D, V,N "'SV
7
pF
f=140KHz
VD =0, VIN =S V
Vo = Vs '" 0, VIN = 0
dB
Positive Supply Current
2.1
-2.1
t.4
4.0
-4.0
3,0
4.0
-4.0
3.0
Negative SUpply Current
-1.4
-3.0
-3.0
VIN=SV,R L =1Kn,C L =20pF
Vs = 7 VRMS, f = SOO kHz
One Channel "ON," V,N = 0
mA
All Channels "OFF," VIN = S V
ICX'F
IVsl
leakage from driver Into "ON" switch .
IS
VIN°74V
Vo - Vs '" t4V
VD Vs - 14V
tTypical Values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
..... Functional operation
VIN=O.8V,IS=-1 rnA
VS-14V,VO---14V
20
Negative Supply Current
Switch ON IS = 10 rnA
VD - 10V
7
POSitive Supply Current
TEST CONDITIONS, UNLESS NOTED:
v- '" -15 V. Gnd = D, VREF = Open"·
V+ "" 15 V.
Vo = 10 V
!l
.A
54
p
p 1+ Standby
L
: 23 V 1- Standby
V
200
200
-10
10
-120
Off Isolatlon*"
1122
22
1-
15
-,
-0,15
Peak Input Current
ReqUired for Transition
Turn-OFF Time
~
0.01
-0,02
0.1
IINlpeak)
Source OFF
Capacitance
-1
18 C
0.01
Input Current,
Input Voltage High
toff
175
175
0,02
"NH
I...!!! 0
16 Y
I-N
i
UNIT
2SOC
.... "OFF.. Isolation = 20 log IVol
possible for supply voltages less than 15 V, but the Input logiC threshold will shift. For V+ '" IV-I = 10 V, +1.4 V
may be applied to the V REF terminal. The V~EF terminal has RIN ~ 21 K n. See the Applications Section.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
OPEN
LOGIC "0" = sw ON
- ~-VREF
+ 1V+
LOGIC
INPUT3'5V~
1,-< 20 n$
tf<20ns
50%
'""'. 'r
o
O-t---'
3-56
'on
S,
I
IN,
LOGIC
INPUT
-
-f
Vs = +2 V
SWITCH V
SWITCH
OUTPUT
SWITCH
INPUT
Vo
toft
0.1
-Q-t>J
n
-=-
Siliconix
bGND
OV
0,
R1
lK"_
.~.1
V-15V
SWITCH
OUTPUT
!CL
Va
RL
Va = Vs RL + rOSlon)
135PF
(REPEAT T-EST FOR IN2,IN3AND IN 4)
APPLICATIONS
Application Hints'
V IN
V+
VV REF
Logic Input
Positive Negative Reference
Voltage
Supply Supply
Pin
VINH Mini
Voltage Voltage Connection
VINL Max
(V)
(V)
(V)
(V)
·A .... llcatlon Hints are for DESIGN AID ONLY. not
guaranteed and not subiect to .. roductlon testing.
•• Electrical CharacterIStics chart based on V+ = + 15 V.
V- = -15 V. VREF = Open.
+15"
• "Operation below ±8 V is not recommended.
Vs or
Vo
Analog
Voltage
Range
(V)
-15
Open
2.4/0.8
-15 to +15
+12
-12
Open or
1.4 V
2.4/0.8
-12 to +12
+10
-10
1.4 V
2.4/0.8
··10 to +10
-8
1.4 V
2.4/0.8
-8 to +8
+8'"
Logic Inputs
Logic input circuitry protects the input MOS gate from static transients. A series MOS device shuts off when VI N exceeds
the positive power supply. Negative transients are clamped to ground by a diode clamp.
The input voltage characteristics have a current spike occurring at the transition voltage when the logic goes from VINH
to VINL. If a series resistor is used for additional static protection, it should be limited to less than 5.6 KQ to insure
switching with worst case current spikes.
'The Function of VREF
VREF is an internal connection which allows the user to establish the logic threshold voltage at which the switch changes
state. The actual threshold voltage is equal to the voltage on the VREF pin. VREF is internally connected for a 1.4 V
threshold at V+ = +15 V. For other thresholds and/or supply voltages, one may connect VREF to a voltage source or
resistive divider whose output voltage is equal to the desired threshold. The internal impedance of VREF is 21 KQ ±30%.
Additionally, to adjust VREF, a single pullup resistor can be used from the VREF pin to a positive supply voltage to shunt
the upper internal divider resistor. The equation below shows the calculation of the shunt resistor for the desired logic
threshold voltage - this calculation is based on nominal internal resistor values, which are ±30% in absolute magnitude.
The adjusted trip point voltage (VREF) should be limited to an upper level of 5 V to avoid input logic switching transition
hysteresis.
( V+)
Rl x R2 - - - 1
RSHUNT = [
( "::
Calculation of RSHUNT
)1
Wh",
R1
~ 220 KQ
R2:::: 23 KQ
~
Rl-R2 - - 1
Vtr
D
o
Example: for V+ = 15 V, VTR IP = 5 V. using nominal R I, R2 calc RSHUNT = 58 Kn.
ca
Sample and Hold
."
CIt
NC
14
--~
15
I
L
::r
16
CD
(II
10
+1SV
+15V
5m"5~'
1
50pF
+---+--oVOUT
-: mell n
30pF
TYPICAL PERFORMANCE
AOUISITION TIME
"2SI'SEC
APERATURE TIME
" l .. SEC
SAMPLE TO HOLD OFFSET "" 5 mV
DROOP RATE
-:..
"Om;",
""""
±30% run to run
-15 V
LOGIC
INPUT
HIGH" HOLD
-15V
"5 mY/SEC
Siliconix
3·57
Quad Monolithic SPST CMOS
A,nalog Switch
designed for. . .
H
Siliconix
BENEFITS
• Analog Multiplexing
Remote Switching under
• TTL
Logic Control
• Servo Control Switching
• Sampled Data Systems
Programmable Gain
• Amplifiers
• Environmentally Rugged
o 44V Power Supply Maximum Rating
o Static Protected Logic Inputs
o Latchproof
• Easily Interfaced
o TTL and CMOS Compatible without
Pull-Up Resistors
o Logic Inputs Accept ± Comparator
Transitions without Series Current Limiting Resistors
• Pin for Pin Compatible with
o Analog Devices ADG201
o Harris H 1201
o Intersil DG201
o Siliconix DG201
DESCRIPTION
The DG201A designed on the Siliconix PLUS-40 CMOS process provides solid state switch action with 175 ohms contact
resistance and very high OFF resistance. True switch action takes place over the full analog signal range of ±15V. with
Break-Before-Make operation to prevent momentary shorting of signal inputs. Charge injection has been reduced by design
to minimize spikes during switching transitions.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM (typical channell
Dual·1 n·Line Package
v+
LEVEL
SHIFTER
LOGIC
INTERFACE
AND
PROTECTION GND
ORDER NUMBERS:
DG201AAK. DG201ABK OR DG201ACK
SEE PACKAGE 10
DG201ACJ
SEE PACKAGE B
SWITCH OPEN FOR LOGIC "1" INPUT IPOSITIVE LOGIC)
3-58
Siliconix
v-
-r"
L.
SWITCH
CONTACT
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VV+ . . . . . . . . . . . . . . .
GND . . . . . . . . . . . . . .
Digital inputs 3 VS, VD ..
"
. . .. . . . . . . . . . . . 44V
. . . . ........... 25 V
. ... -2 V to (V+ +2 V) or
20 mA, whichever occurs first.
Current, Any Terminal Except S or D
30mA
Continuous Current, S or D
20mA
Peak Current, S or D
(pulsed at 1 msec, 10% duty cycle max)
70mA
-65 to 150°C
-65 to 125°C
Storage Temperature (A & B Suffix)
(C Suffix)
Operating Temperature (A Suffix)
(B Suffix)
(C Suffix)
-55 to 125°C
-20 to 85°C
o to 70°C
Power Dissipation (Package)'
16PinDIP"
16 Pin Plastic DIP'"
900mW
470mW
• Device mounted with all leads soldered or welded
to PC board.
"Derate 12 mW/C above 75°C
"'Derate 6.5 mW/C above 25°C
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
1
VANALOG
Minimum Analog Signal
Handling Capability
rOS(on)
Drain Source
ON Resistance
12
l--S
l---:t S
w
1---;- I
1---;; CT
1-
H
7
"
N
U
T
13
II~
15
I17
l-;e
0
y
N
A
M
I
C
::!:15
::::15
BIC SUFFIX
20"C1
850CI
250C
700C
O'C
::!::15
::!:15
105
175
175
250
200
200
250
115
175
175
250
200
200
250
TEST CONDITIONS. UNLESS NOTED:
UNIT
V+ =15V,V- = -15V.Gnd =0
V
n
Vo
~
10 V
Vo
~
-10 V
100
5
100
Vs
~14
-100
-5
-100
Vs
~
-14 V, Vo
0,01
1
100
5
100
Vo
~
14 V, Vs
1010ffi
Drain OFF
Leakage Current
1010nl'
Drain ON
Leakage Current
IINH
Input Current
Input Voltage High
IINL
Input Voltage Low
'on
Turn-ON TIme
'off
Turn-OFF Time
Q
Charge Injection
Input Current
Source OFF
CSloffl
Capacitance
COloffl
Drain OFF
Capacitance
V, V D
~
~
-1
-100
-5
-100
Vo
~
-14 V, Vs
1
200
5
200
Vo
~
Vs
~
14 V
Vo
~
Vs
~
-14 V
-0.15
-1
-200
-5
-200
-,0004
-1
-10
-1
-10
,003
1
10
1
10
-1
-10
-,0004
-1
480
600
600
450
450
370
-10
20
14 V
VIN
~
2,4 V
VIN
~
0,8 V
--
- 14 V
0,1
VIN
J.S'C
,
MInimum Analog
Signal Handling
VANALOG
BIC SUFFIX
A SUFFIX
-55DC
± 15
>S'C
12SGC
± 15
± 15
-2I1'CI
Il'C
TEST CONDITIONS.
UNLESS NOTED: V+ =15 V.
UNIT
85GC!
>S'C
V-=-15 V, GND=O
7Il'C
± 15
V
± '5
Capability
2
3
4
5
6
S
rOS(on)
I
T
C
'05
175
'75
250
200
200
250
115
'75
175
250
200
200
250
Vo=-1OV
-,
'00
5
,00
VS-14V, VO--14V
·'00
-5
-,00
'00
5
,00
H
-'00
-5
-'00
Vo = -14 V. Vs == 14 V
8
JOlon)
-0.02
0.0'
Drain OFF
Leakage Current
IDloft)
7
0.Q1
Source OFF
Leakage Current
ISloft)
-0.02
0.'
Drain ON
2
Leakage Current
-0,15
IINH
Input Current.
Input Voltage High
-.0004
IINL
Input Current,
Input Voltage low
'3
,4
'00
'off
'5
9
,0
11
I
N
'2
U
•
T
,6
0
Y
,7
N
A
M
I
'8
C
,
,
-,
,
-,
-,
200
Vo =V s =14V
-200
V o ""V s =-14V
V1N =24V
,0
,
-,0
-'0
-,
VIN =2.4 V
-'0
-,
,
-,
Turn-ON Time
480
600
600
Turn-OFF Time
370
450
450
a
Charge Injection
20
CSloffl
Source OFF
Capacitance
COlotfl
Drain OFF
Capacitance
5
,6
V 1N
=15V
VIN=O
ns
See SWitching Time Test Circuit
pC
CL = tOOOpF, VGEN
pF
70
20
CCRR
Channel to
Channel Crosstalk
90
1+
Positive Supply
Current
.9
2
2
1-
Negative Supply
Current
-.3
-,
-,
y
,A
-'0
=0 V, RGEN =00
VS=O, VIN=OV
Off Isolation
l
,0
5
COlon) + CSlon)
22
V1N =O.8V
Vo=14V, Vs=-14V
5
OIRR
••
Vs=-14V. Vo=14V
nA
-5
,9
S
U
VIN =2.4 V,
Is =-1mA
200
·.0004
.003
!l
-200
Channel ON
Capacitance
2'
Vo ",'0V
Drain-Source
ON ReSistance
W
f= 140 KHz
Vo=O, VIN=OV
VO=VS=O, VIN =5V
dB
VIN=OV
Vs=2 Vpp, f= 100 KHz, ZL =75!1
rnA
All Channels "ON" or "OFF,"
VIN =0 or 2.4 V
NOTES:
1. Typical Values are for DESIGN AID ONl V, not guaranteed and not subject to production testing.
2. 1010ni is leakage from driver into "ON" switch.
3. Signals on Sx. Ox or INX exceeding V + or V - will be clamped by Internal
dioded. limit forward diode current to maximum curtent ratings
ICMC·D
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in spikes at
leading and trailing edge of output waveform.
+15V
lOGIC
INPUT
1r< 20 ns
1f< 20 ns
SWITCH
INPUT
SWITCH
OUTPUT
3-62
SWITCH
INPUT
3V-F1-
?V+
5,
50%
~
Vs = "'2V
IN,
V5
0
-
VI:
'00
lOGIC
INPUT
JVO D."
Il
-=-
toff
-Q-t>J
60ND
DV
6
v-15V
Rl
Vo = Vs Rl + rOSlon)
Siliconix
0,
SWITCH
OUTPUT
R;1
'K" _ I 35pF
Vo
kel
(REPEAT TEST FOR
IN2.IN3.IN4)
Quad Monolithic SPST CMOS
Analog Switch
designed for . . .
H
Siliconix
BENEFITS
•
• Low Transient Switching
i.e., Sample and Hold Circuits
• Switching Multiple Signals
such as Multiplexing Inputs
• High Frequency Signal
Switching e.g., Computer
Peripheral Equipment
• TTL Compatible Systems
Including Microprocessor
Systems
•
Environmentally Rugged
o Latchproof
o Power Supply Overvoltage to 40V Max
Reduced Switching Error
o Low Charge Coupling
•
Easily Interfared
o TTL, DTL and CMOS Compatible
without Pull Up Resistors
•
Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
•
Reduced System Cross-Talk
o Break-Before-l\I1ake Switching
•
Eliminates Signal Error
o 0.01 nA Typical Leakage From Source
Or Drain
•
Pin for Pin Compatible with
o Intersil IH5052, IH201
•
Low Cost
DESCRIPTION
The DG211 designed on the Siliconix PLUS-4Q CMOS process is a 4-channel single pole single throw analog switch with low and
nearly constant ON resistance over the entire analog signal range. The switch will conduct current in either direction with no offset voltage in the ON condition, and block voltages up to 30 V peak-to-peak in the OFF condition. The ON-OFF state of each
switch is controlled by a driver. With a logic "0" at the input to the driver (-15 V to 0.8 V) thw switch will be ON, and a logic "1"
(2.4 V to 15 V) will turn the switch OFF. The input can thus be directly interfaced with TTL, DTL, RTL, CMOS and certain PMOS
circuits. Switch action is break-before-make. Logic inputs can directly connect to op-amp output swings.
-J>
~
a
o
ca
CIt
..._.
~
PIN CONFIGURATION
"::r
CD
I
LOGIC
l
~
I
I ~~F
'"
I
SWITCH
J
ORDER NUMBER:
DG211CJ
SEE PACKAGE 8
TOP VIEW
SWITCH OPEN FOR LOGIC "1" INPUT (POSITIVE LOGIC)
Siliconix
3·63
......
ABSOLUTE MAXIMUM RATINGS
"oCI
V+ to
v- ...................................
VIN to Ground
Storage Temperature .......•......... -65 to 125°C
Operating Temperature . . . . . . . . . . . . . . . . . . 0 to 700 e
Power Dissipation (Package)·
16 Pin Plastic DIP**
... . .............. 470mW
40 V
V-, V+
--0.3 V, 25 V
............................
VL to Ground ..••...•. , .........•....
Vo 10 V+ . . . . . . . . . . . . . . . . . . . . . . 0, -40 V
Vo 10 V- . . . . . . . . . . . . . . . . . . . . . . . 0,40 V
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -25 V
Current, Any Terminal Except S or 0 . . . . . . . . . 30mA
Continuous Current,S or 0 ............... 20mA
Peak Current, S or 0
(pulsed all msec, 10% duty cycle maxi ..... 70mA
Vs or
Vsor
V+ to
V- 10
ELECTRICAL CHARACTERISTICS
* Device mounted with all leads soldered or welded to
PC board.
"Derate 6.5 mW/oC above 25°C
All DC parameters are 100% tested at 25°C. lots are sample·tested for AC parameters
and high and
low temperature limits to assure conformance with specifications.
MAX
LIMITS
CSUFFIX
CHARACTERISTIC
Typ1
2S°C
I
-
--:t""
-----s-S
---,-
S
W
I
T
C
H
-S
-----g~
-
I
11
N
12
U
T
~
14
-
-
Min, Analog Signal
Handling Capability
rOS(onl
Drain Source
ON ReSistance
IStotU
Source OFF
Leakage Current
10(011)
Drain OFF
Leakage Current
OrainON
Leakage Current
0.1
5
10(on)2
-0.15
-5
Vo = Vs = -14 V
-0.0004
-1
VIN = 2.4 V
16
0
17
I
C
175
115
175
0.01
5
-0.Q2
-5
0.01
5
-0.02
-5
"NL
Input Current,
Input Voltage Low
'on
Turn-ON Time
460
1000
toffl
Turn-OFF Time
360
500
toff2
Turn-OFF Time
450
C510ffl
Source OFF
Capacitance
COlo1f1
Drain OFF
Capacllance
COlon} + CS(on)
Channel ON
Capacitance
M
18
"5
"NH
V
N
A
,15
105
Input Current.
Input Voltage High
P
-;s-
-
VANALOG
2
----;-
0.003
I
-0.0004
-1
Interchannel
Crosstalk
Isolation
90
-;J
p
VIN = 08 V,IS '" -1 rnA
V O "'-10V
Vs - -14 V. Vo = 14 V
nA
VO'" 14V.VS=-14V
VIN '" 2.4 V
Vo = -14 V, Vs = 14 V
Vo = Vs = 14 V
V,N' 0.8 V
VIN -15V
VIN = 0
ns
Vs = 2 V
RL = 1K n
C L = 35 pF
See SWitching Time
Test CirCUit
Vs = 0, VIN = 5 V
5.
20
S
Vo = 10 V
VS'" 14 V, Vo - -14 V
pF
16
70
U
n
5
OFF Isolatlon 3
22
V
.A
19
~
TEST CONDITIONS, UNLESS NOTED:
V+ .. 15 V, V-= -15 V,Gnd= 0, VL ""5 V
UNIT
2S°C
f= 1 MHz
Vo = 0, V1N '" 5 V
Vo = Vs = 0, VIN = 0
dB
1+
Positive Supply Current
0.35
0.48
1-
Negative Supply Current
0.30
0.48
'L
Logic Supply Current
0.5
1.2
rnA
VIN=5V,RL=lKH,CL=15pF
V S "'- 1 VRMS, f "'- 100 kHz
V IN =Oor2.4V
ICMC·A
1. Typical values are for DESIGN AID ONLY, not guaranteed and
not subject to production testing.
2. 1010n) is leakage from driver Into ON switch.
IVSI
3. OFF Isolation'" 20 log - , VS" input to OFF switCh,
IVOI
VD '" output.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
~1~VV.
.--
LOGIC
INPUT (IN,1 - - "
50%
1r< 20nl
1,< 20nl
0
~
SWITCH
Vs
INPUT
SWITCH
OUTPUT IVai -
-r---1 f--
VL
~
5,
Vs· ~2 V
LOGIC
INPUT
0.9VO
o.g Vo
'on
3-64
toff1~
y
SWITCH
INPUT
IN,
1\
0.1 Vo
-=-
10112
Siliconix
~
6GNO
OV
0,
"hi 1350F
JC
'0"_
.~.1
V-
-15V
RL
Va "VS Rl + fOS{onJ
SWITCH
OUTPUT
Vo
L
{REPEAT TE-ST FOR IN2, INa AND IN41
c
TYPICAL CHARACTERISTICS
The electrical characteristic table guarantees the OG211 for operation at
±15 V, ±10%; however, functional operation occurs over the designed
range of ±5 V to ±20 V power supplies. These characteristic graphs show
the effect of device parameters over several parameter permutations
including power supply variations. These graphs are for design aid only
and are not subject to production testing.
Q
......
Typical delay. rise. fall, settling times.
."."
and switching transients in this circuit.
rOS(ON) VS Vo and
Power Supply Voltage
rOS(ON) vs Vo
Tem peratu re
6OOr---,---,---,---,---,---,
600
500
2
o
0,--
""'-
A Iv+ .. +sl.
v! = -5) TA " 25°C
-~ ~:: :;::.' ~:: :~:~-f--
,zv, v- = -12V
.0
V+" ..
E
V+" +lSV,
V-" -1SV
If AGEN, AL or CL is increased, there
will be proportional increases in rise
andlor fall RC times. Applying VGEN
to 0 rather than S results in much
greater ton spikes.
-
12S"C
25°C
5S·C
0
-15
-10
-5
10
~1~5---_~10---_~5--~--~---7.1O~-7.'·5
15
Vo - DRAIN VOL TAGE (VOL lSI
Vo - DRAIN VOLTAGE lVOLTS)
Maximum Channel to Channel
Va9~iation of ROS(ON) in Each Oevice
Switch Cu rrent vs
Switch Voltage
OVo ... ,OV,
0 - .Vo .. -lOV
I
70r-.--r-r-.--,-,--.-.-.r-o
!!Il -v. ·15V -t--f--t-+~.L.j/----l
I
1 50 -~~ : 5~5V-t--f--t-+/rr-t----l
SAMPL.E SIZE" 100 UNITS
40 -TA .. 2S"C -t--f--t-+-+-t----l
0
I ::f-+-+-t-t--t-~-r-t--~
u
G
g
2
>"
!..OGIC INPUT
1O~+-~-+-4--~1--r-+--~
u
0
i
~
~
20
-10f-+-+-t-t+t-+-r-t--t---l
5 -20f-+-+-t-J'---t-+-r-t--t---l
!: -JDf-+-+-tJ~- SLOPE = HRaSIONI
~ -40f-+-+-+y--t-+-r-t--t---l
. :. -50f-+-+-Lf--t--t-+-r-t--t---l
0
0
0r-r-
or-r-
15
10
1\
II
-60~+--:I"-+-4--+-+-r-+--~-I
Ii
2
3
4
5
6
7
8
9
10
10
8
-6
4
2
0
2
4
6
8
VOS - SWITCH. DRAIN TO SOURCE
-5
10
VOLTAGE {VOlTSI
RaSION) BETWEEN SWITCHES IN EACH PACKAGE (OHMS)
20
IO(ON) vs Temperature'
IO(OFF) or IS(OFF) vs Temperature'
l1li
VGEN = +10V
70
o ,
MAXIMUM .lROS/ONI - MAXIMUM 01 FFERENCE IN
:I>
15
1O~'--.--'--r-.--~-r--r..~
::I
10
II
a
-o
\
V GEN • +5V
~
~
-5
G
10
."-.
CIt
~
~
~
~
-5
5
-10
o
~
!
6Q
-v~
• .\5V
v- .. -1SV
8 -VL -+5V
I
"- ......
>
~
4
-
~:POWER
.i
20
r- -
I
15
5 25
45
65
85
T- TEMPERATURE' Cl
lOS
125
I
II
II
-I 0
I~ IOF"~
-I 5
-
-60
-.
5
IOWNI
0
vl.'5v
VI.. = 5V
I
0
-100
V GEN .. -5V
-2 0
IS {OFF I
-20
I
- F=
TO CONDUCT
1\
5
SUPPLY SWITCH
SUBSTRATE DIODES BEGIN
~
~
~
I
o
a
~ -40
"
1
r(
2
I
-55 -35
40
.
' l - c--
~H!N tNIA'~G lxdEE6:tt
i
i
"'"
1ft
Leakage Current vs Analog Voltage
Supply Current vs Temperature
"
CD
~
T - TEMPERATURE [ C)
0
:r
V GEN = OV
-15
I
I I
v- = -15V
T A " 25 C
I
I
I
FOR 10 {OFF!' Vs • OV
FOR IS {OFF!, Vo" OV
-15
-10
-5
0
5
10
15
VANAI..OG - ANALOG VOLTAGE {VOLTS!
*The net leakaQe into the source or drain is the n-channel leakage minus the p-channel
leakage. This difference can be positive, negative, or zero depending on the analog
voltage and temperature, and will vary greatlv from unit to unit.
Siliconix
1\
5
V"
I
\
-I 0
-I 5
VGEt'li .. -10V
-20
2
0
8
1.0 12
1.4
16
T - TIME {" SEC!
NOTE: Turn-off time is primarily limited here by the RC time constant (50ns)
of the load.
3-65
TYPICAL CHARACTERISTICS (Cont.)
;;
"~
~
~
Insertion loss vs Frequency
"".
"'"'
""'" ' ' ' '1 "".
0
-'r-~---t---r--~--+-~
0
"O..
"
,
v" ..
,
"
i'.
-101-==+==+==+0="1=-:=01::--==1
~I ~ r- ~: : ~~v ~;x oo"L~~~
Channel to Channel Crosstalk
vs Frequency
OFF Isolation vs Frequency
+-_"L_--+50_'_'-I
0
I-- TES, SETUP t GURE I
0
TEST SETUP AGU"E ,
"'.~L =50U
,.... ,
"r--... I'-..
"i'.
Vs '" lVAMS
15V Y- II -lSV I 111111
VL '" SV 1NX = LOGIC "1"
Vs = IYRMS
0
UM' P"'!---''''-:l-'''-;;[----'_f_ "L = 50P
AL= 5011
"~
I'-.. ["
1'-..'
RL ~ lKIl
"L = 10Kli
'~KII
ao}--!---''''-:l-'''-;d--'''''RL = lKl!
f-+--+-"'"-.If----"-lL' ,,,,I,
~
,,,..l,,,,,,
""" "'''' ""'"..OM
F-
TEA~INATOR
[TERMINATOR)
"L =
F _ FREQUENCY (H2)
I
',I
v"
= 15V Y- = -ISV ~AL =
VL
=
SV
Vs
= lVRMS
I'
looKI'
\
T~~riu~E:~P -t--t---::+-:::--',I'
"u..
FREQUENCY (Hz)
FREQUENCY
TESTED
SIGNAL
GENERATOR
ANALYZER
100tG 1MHz
WAVETEK
MOO 142
HP3575A
GAIN-PHASE METER
1M TO 100MHz
TEKTRONIX HP8405A
MOO191
VECTOR VOLT METER
C s OOI"FIf I.11F
CHIP CAPACITORS
Figure 1
Testing Insertion Loss vs Frequency
SIGNAL
--f.ir-r_-,
FREQUENCY
TESTED
GENERAT:.:O::.:"--._ _ _
f
100 TO 50KHz
SIGNAL
GENERATOR
ANALYZER
HP3580A
HP3580A
TRACKING OSC SPECTRUM ANALYZER
1M TO 100MHz
TEKTRONIX
HP8405A
MOD 191
VECTOR VOLT METER
100K TO 10MHz HP8568A
HP8568A
TRACKING OSC SPECTRUM ANAL YZER
ANALVZER
CHANA
CHANe
_15V
Figure 2
Testing OFF Isolation vs Frequency
.15\1
FREOUENCY
TESTED
100 TO 50KHz
SIGNAL
GENERATOR
H ..' TO 100MHz TEKTRONIX
MOD 191
100K TO 10MHz HP8568A
TRACKING OSC
C 001~f
'_F
CHIP CAPACITORS
ANALYZER
HP3580A
HP3580A
TRACKING OSC SPECTRUM ANALYZER
HP8405A
VECTOR VOL T METER
HP8568A
SPECTRUM ANAL YZER
Figure 3
Testing Crosstalk vs Frequency
The data plotted in the frequency response graphs are measured in a special coax test fixture. Each lead of the IC package fits into the
center conductor of a solid 50 ohm coax. The fixture eliminates stray capacitance normally encountered in printed circuit (PCI board layouts and sockets. The OFF isolation versus frequency degrades from the values shown with careless PC board layout. The best layout tech·
niques include good ground planes, guardtraces between signal paths and bypassed power supplies.
3-66
Siliconix
c
TYPICAL CHARACTERISTICS (Cont.)
10
v- ..
Capacitance vs V D or Vs
""'''' """I "':'~. """ V."~'1S;"'"
f.,LH2
-1SV
r- TA '"
4
VL'" 5V
70r--+PSRR=20I09.lV~-
25"C
~
Vs=2V pp
8
RL .. loon
CD(0.1+~
'E
a
RL " 10KH
...
%
OIJ
~
2
~
6=
J
R L " lKfl
,
,
lK
10K
'OOK
F - FREQUENCV (Hz}
Charge Injection
vs Analog Voltage
70
i
r-
60
y,
VA.AU~__
9 50 I--
88 .. I-~
I
~
§
~-2
~
lj!3000
V -'0.
-
"~ 0
~-1 0
~
:
..--
0
i
~
1000
!}
V+
-5
0
5
10
·15V
¥~ :~oc
\
"-
,\N
'oN
1\." ,::-......
~FF;'--
0
-to
15
5
'0
V+ - POSITIVE SUPPL V IVOLlSI
VANALOG (VOL lSI
Switching Time vs Positive &
Negative Supply Voltage
-
toFF 1
300
15
o
-5
-10
-15
V- NEGATIVE SUPPLY (VOLTS)
Switching Time vs
Input Logic Amplitude
Switching Time vs Temperature
'000
~! :~oc
U
iw
550
1\
2000
I
~~~v-
:~oc
TA .. 25"C
-30
-15
....
Cs ,aFF'--= ~
;;
~
V L = 5V
v- • -15V
¥!
REVERSE "0 FOR 00$ MEASUREMENT - : : :
! '0 "
I
L" J
Switching Time vs
Negative Supply Voltage
;::
.aD
IN,. "'"
Switching Time vs
Positive Supply Voltage
.DoDO -C"\V o
0
-PSRR
L .. SOpF
F _ FREQUENC'IIH:z1
~ 4000
£
w
0._1_0"
~
ov
RL = SOOKII
',!:-,-",I"""
1I1I,,'!:"-,UC"~III'~K-'-'-'"~lll"!!!:8K:-,I~
11I1II'~B8K::!-,-~"",'.,-JIL.W
II"~,,".
u
C- 1000pF
Vs ..
-15
-10
-5
0
5
10
15
Yo OR Vs - DRAIN OR SOURCE VOLTAGE (VOLTSI
....
L
,vo"I
f
0
~
l
r-
~ 30
C- CD
""r--.-
1-----
= -15V
VL .. 5V
f--b=+--+--+c
0
'00
Y-
H6 O t - - - PSRR =20109 .lV~-
'~~A"25~C
hJ
Power Supply Rejection
vs Frequency
0
"~
E V"15~'''1
4000
1\
lj!3000
i~
·,5V
VL
.. 5V
V_ = -15V
Vs = 2V
CL ., 35 pF
V+ =+lSV
v- = -lSV
vL '" +5V
Vs • +2V
TA "25'C
~ 600 f---t---tf--f--f--f---l
~
i""
~ i"""'" ~
~~
"'''
'oFF, ...............
o
o
V+,
v- -
!5
!to
~
--...-;:
ffi 300f----jf----j-COFF1----=~-+-~
2000~--~--~---7-1·--7_--7_~
!IS
POSITIVE 21 NEGATIVE SUPPLY (VOL.TS)
Input Switching Threshold vs
Logic Supply Voltage
"a
~;: ;~Ic
~
~
6
o
o
5
~'~
~
-'~
... 4 f---f---t---f,~'I------l
5
~
~ 3f-----f----f,~~--f------l
~
i
2
1--7~--~--~--~
...
%
>
o
V+,
v-
5
10
15
'20
POSITIVE III NEGATIVE SUPPLIES (VOLTSI
10
15
V L - LOGIC SUPPL. Y (VOL. TS)
Siliconix
o
55 -35
15
20
3>
::I
pF
D
S
~
;;
o
25
45
65
85
r C)
105
CD
CIt
~
COrF1
T - TEMPERATURE
V 1NH - INPUT L.OGIC AMPLITUDE (VOL TSI
Input Switching Threshold vs
V+ & V-- Supply Voltages
5
r---
.9
--
- ".-.
~~
'oN
~400r---t-~\---+---+---+---j
.9
= lK
= 35
~....-:
~ 500~--r-~t=::t:::~~~--1
I
"21000
!}
Rl
Cl
"z
\~N
~
V+
1700f--t---i-+-~~NL ~ ~~
\
~
;::
..
Q
Total Harmonic Distortion
vs Frequency
125
::r
CD
1ft
Some applications of the DG211 will
find the logic control inputs (IN x ) driven
from the output of comparators or op~
amps with nearly plus to minus 15 volt
transitions. In these applications the user
can shift the input logic transition volt~
age from the normal 1.6 V of TTL to
zero volts by connecting the V L pin to
the GND pin. In this mode of operation
the input offset voltage between IN x and
VL (= GND) measure less than ±500mV.
V L =5V presets the input threshold voltage for TTL logic compatibilitY. Improved noise immunitY for CMOS logic
compatibility results by connecting V L
to the VDD terminal of the CMOS logic.
3·67
SCHEMATIC DIAGRAM (Typical Channel)
v+o---------------~------~------------_,
V L o-~--___,
LOGIC
TRIP-
POINT
REF
GND o-~----'
IN
L----+----~-------oDX
xo-------'Wv-----_+_---'
v-o----~------~------~--------~
APPLICATIONS
'N,
'N,+___--'
'N,+-------~
'N.+-----------..J
Figure 4. Four Channel Analog Multiplexer
PRECISION ATTENUATOR
V'N o-----------.,~,
~----~----------~
GAIN ERROR IS DETERMINED ONl Y ElY
THE RESISTOR TOLERANCE OP AMP
OFFSET AND CMAR WILL LIMIT ACCURACY
GAIN]
AV - 20
Figure 6. Microprocessor Controlled Analog Signal Attenuator
3-68
Figure 6. Precision·Weighted Resistor Programmable-Gain Amplifier
Siliconix
Quad Monolithic SPST CMOS
Analog Switch
designed for • • •
H
Siliconix
BENEFITS
• Low Transient Switching
o.e., Sampie and Hold Circuits
.. Switching Multiple Signals
such as Multiplexing Inputs
• High Frequency Signal
Switching e.g •• Computer
Peripheral Equipment
• TTL Compatible Systems
Including Microprocessor
Systems
•
Environmentally Rugged
o Latch proof
o 40 V Power Supply Max Rating
•
Reduced Switching Error
o Low Charge Coupling
•
Easily Interfaced
o TTL, DTL and CMOS Compatible without Pull Up Resistors
• Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
•
Reduced System Cross-Talk
o Break-Before-Make Switching
•
Eliminates Signal Error
o 0_01 nA Typical Leakage From Source
or Drain
o Pin for Pin Compatible with
o Intersil IH5053,IH202
•
Opposite Logic Control of DG211
•
Low Cost
DESCRIPTION
-l>
The DG212 designed on the Siliconix PLUS-40 CMOS process is a 4-channel single pole single throw analog switch with low
and nearly constant ON resistance over the entire analog signal range. The switch will conduct current in either direction
with no offset voltage in the ON condition, and block voltages up to 30 V peak-to-peak in the OFF condition. The ONOFF state of each switch is controlled by a driver. With a logic "0" at the input to the driver (-15 V to 0.8 V) the switch
will be OFF, and a logic "1" (2.4 V to 15 V) will turn the switch ON. The input can thus be directly interfaced with TTL,
DTL, RTL, CMOS and certain PMOS circuits. Switch action is break-before-make. Logic inputs can directly connect to
op-amp output swings.
~
II
o
ca
_.
...
CIt
~
"CD::r-
PIN CONFIGURATION
1ft
Dual-I "-Line Package
SWITCH
OFF
ON
ORDER NUMBER:
DG212CJ
SEE PACKAGE 8
TOP VIEW
SWITCH CLOSED FOR LOGIC "1" INPUT (POSITIVE LOGIC)
Siliconix
3-69
ABSOLUTE MAXIMUM RATINGS
V+ to
v- ...................................
............................
VIN to Ground
VL to Ground ••.......•....•.•.......
Storage Temperature .....•........... -65 to 12SQ C
Operating Temperature ......•........... 0 to 70°C
Power Dissipation (Package"·
16 Pin Plastic Dlp u
........ . .. . ..... 470mW
40V
V-, V+
-0.3 V, 25 V
Vsor Vo to V+ . . . . • • . . . • • . . . • . . . . . . . 0, -40 V
Vsor Vo to V- . . • . • • . . . • • . . . . . . . . • . . . 0,40 V
V+ to Ground ................
. 25 V
V- to Ground ..........•......
. -25 V
Current, Any Terminal Except S or 0
30mA
Continuous Current, S or 0 .......
. 20mA
*Device mounted with all leads soldered or welded to
.........
..... . ..
.......
..... . .
Peak Current, S or 0
(pulsed at 1 msec, 10% duty cycle maid
. . .. .
PC board .
··Derate 6.5 mW/oC above 2SoC
70mA
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and
low temperature limits to assure conformance with specifications.
CHARACTERISTIC
1
Mm. Analog Signal
Handling Capability
"5
,,5
Drain Sourc!!
ON Resistance
175
"5
'75
0.01
5
IStoff}
Source OFF
Leakage Current
-0.02
-5
0.0'
5
1010111
Drain OFF
Leakage Current
-0.02
-5
10(on1 2
Dram ON
Leakage Current
0.'
5
-0.15
-5
Vo = Vs = -14 V
-0.0004
--,
Y,N = 2.4 V
2
~
r--s
r---s-
~
rOSion)
S
W
I
T
C
H
r--a
r--g
'0
"NH
'nput Current,
Input Voltage High
"NL
Input Current,
Input Voltage Low
I~
ton
Turn-ON Time
460
1000
t---;s-
toff1
Turn·OFF TIme
360
500
toff2
Turn-OFF Time
450
CS(offl
Source OFF
Capacitance
5
COlo11i
Drain OFF
Capacitance
5
Coton) + CSlon)
Channel ON
Capacitance
16
t-;'1
f-'2
I
N
P
U
T
14
-
'6
Y
-
-
D
17
N
A
M
18
I
C
0.003
I
- 0.0004
-I
t9
OFF Isol8110n 3
70
20
Interchannel
Crosstalk
isolation
90
2'
~
23
S
U
P
TEST CONDITIONS. UNLESS NOTED:
V+ '" 15 V, V- '" -15 V. Gnd '" O. VL" 5 V
UNIT
25"C
105
VANALOG
f--
f----j"-
MAX
LIMITS
CSUFFIX
Typl
25"C
V
n
Y,N = 2.4 V, IS = -1 rnA
VO=-10V
Vs - 14 V, VO': -14 V
Vs =. 14 V, Vo - 14 V
V'N=0.8V
nA
VO:: 14 V, Vs =
'4V
VO=-14V,VS- 14V
Vo '" VS:: 14 V
Y,N = 2.4 V
Y,N = 15V
.A
V'N:: 0
ns
VS:: 2V
R L :: lK H
C L = 35 pF
See SWItching Time
Test CirCUit
Vs = 0, V,N = 0 V
pF
VO=O, V'N=OV
1= 1 MHz
VO=VS=O, V,N=5 V
dB
1+
VO'" 10 V
Positive Supply Current
,.-
0.35
0.4B
Negative Supply Current
0.30
0.48
'L
LogiC Supply Current
0.5
, 2
rnA
VIN =0 V, RL = tK n, CL = 15 pF
Vs = , VAMS, f " 100 kHz
V ,N :: 0 or 2.4 V
ICMC·C
1. Typical values are for DESIGN AID ONLY, not guaranteed and
not subject to production testing.
2. 10(onl is leakage from driver into ON switch.
1VSI
3. OFf Isolation = 20 log - . Vs '" input to OFF sWitch.
IVOI
Vo '" output.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown, Note that Vs may be + or - as per
switching time test circuit, Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
+jVv.
+y~VL
SWITCH
INPUT
LOGIC
INPUT (IN,) 3V
t r< 20 ns
tf< 20 ns
SWITCH
INPUT
SWITCH
OUTPUT
3-70
'f
S,
VS'" +2 V
SO%
OV - - '
--
Vs
IVOl
-
{
tan
9V
~
LOGIC
INPUT
tOffl~
0.9
Vo
O.,VO
O
-
IN,
n
-=-
toff2
Siliconix
D-t>J
6GNO
OV
_~.'
V-15V
"L
VO'" \is RL + rOSlonl
D,
"1
SWITCH
OUTPUT
Vo
d:c
'K"_ 135P'
L
(REPEAT TEST FOA 1N2, IN3 AND IN4t
Monolithic General Purpose
CMOS Analog Switch
designed for . . .
H
Siliconix
BENEFITS
•
Programmable Gain Amplifiers
•
Analog Multiplexing
•
Servo Control Switching
• Transient Suppression
o Make-Before-Break Switch Operation
•
Environmentally Rugged
o 40V Power Supply Rating
o Static Protected Logic Inputs
o Latchproof
•
Easily Interfaced
o TTL and CMOS Compatible without
Pull Up Resistors
•
Reduces External Component Requirements
o Full Rail to Rail Analog Signal Range
o No Diode Protection Required Between
VL and V+ for Power Supply Sequencing
•
Pin for Pin Compatible with
o Intersil IH5043
o Harris HI5043
o Siliconix DG5043, DG191, DG390
DESCRIPTION
The DG243 designed on the Siliconix PLUS-40 CMOS process provides solid state switch action with 50 ohms contact
resistance and very high OFF resistance. True switch action takes place over the full analog signal range of ±15 volts, with
Make-Before-Break operation improving transient response in programmable gain amplifiers.
-~
PIN CONFIGURATIONS
::3
D
FUNCTIONAL DIAGRAM (typical channel)
o
CG
VD
=:
....
....
Dual-In-Line Package
DUAL SPOT
LOGIC
SW 1
SW2
ft
VL
S1
SW 3
SW4
0
OFF
ON
1
ON
OFF
V+
IN1
VGND
VL
ALL SWITCHES SHOWN IN
THE LOGIC "1"
SWITCH STATE
IN2
INX
LOGIC
INTERFACE
AND
PROTECTION GND
LEV·EL
SHIFTER
V-
-r"
Lo,
SWITCH
CONTACT
TOP VIEW
ORDER NUMBER:
DG243AK or DG243CK
SEE PACKAGE 10
DG243CJ
SEE PACKAGE 8
Siliconix
3-71
::s-
CD
til
ABSOLUTE MAXIMUM RATINGS
Storage Temperature (A Suffix)
(C Suffix)
Operating Temperature (A Suffix)
(C Suffix)
Power Dissipation*
Metal Can and Plastic DIP"*
16 Pin DIP--**
Flat Pack*****
Voltages referenced to VV+ ......
. . . . .. . . . . . . . . . . . . . . 44V
.. ..
. . (GND -0.3 V) to 44 V
VL ... ·· .
GND ....... .. .
.... . . . . . . . . . . . . 25V
Digital inputs 5 VS, VD .. . . .... . -2 Vto (V++2 V) or
30 mA, whichever occurs first.
Current, Any Terminal Except S or D .
Continuous Current, S or D .
Peak Current, S or D
(pulsed at 1 msec, 10% duty cycle max) .
30mA
30mA
-65 to 150°C
-65 to 125°C
-55 to 125°C
o to 70°C
450mW
900mW
900mW
* All leads welded or soldered to PC board.
**Derate 6 mWfC above 75°C
****Derate 12 mWfC above 75°C
*****Derate 10 mWfC above 75°C
.100mA
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25° C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
MAX LIMITS
A SUFFIX
CHARACTERISTICS
-55OC
1
VANALOG
I~
--;1----;;-
5
---s
---:;-
S
W
I
T
C
H
-----a
----g
10
-
125"C
O'C
25'C
70'C
±15
±15
±15
±15
50
75
50
50
75
50
75
50
50
75
1
100
1
100
-1
'OSlon)3
Drain Source
ON Resistance
50
ISloff)3
Source OFF
Leakage Current
-100
-1
-lOa
Drain OFF
leakage Current
1
100
1
100
1010ff)3
-1
-lOa
-1
-100
Drain ON
Leakage Current
2
200
2
200
-2
-200
-2
-200
±1
±1
±1
±1
Input Current
Input Voltage High
IINH3
P
11
U
T
12
-----;;114
V+ "" 15V, V-
UNIT
50
1010n)3
I
N
Minimum Analog Signal
Handling Capability
25'C
TEST CONOITIONS
C SUFFIX
VL
~
= -15V
5V. GNO
~
OV
V
Vo
=
10 V, IS
Vo
~
-10 V. IS
=
-10 mA
II
~
-10 mA
Vs ~14 V. Vo ~ - 14 V
Vs ~ -14 V. Vo ~ 14 V
Vs ~ -14 V. Vo ~ 14 V
Note 1
nA
Vs ~ 14 V. Vo ~ - 14 V
Vs =VO = 14 V
Vs ~VO ~ -14 V
VINH ~ 2.0 V
pA
IINL3
Input Current
Input Voltage Low
±1
±1
±1
t on 4
Turn-ON Time
500
700
'00
Turn-OFF Time
1000
1200
0
Charge Injection
CSloff)
Capacitance
COloff)
Capacitance
VINL ~ 0.8 V
±1
ns
Vs = ±lOV, Rt
= lK!!
Note 2
CL ~ 35 pF
60 Typical
pC
CL ~ 1000pF. RGEN ~ On.
VGEN ~ 0 V
pF
Vs ~ Vo ~ 0 V.
f ~ I MHz
115
--16
I-
0
y
N
A
M
I
C
17
COlon)
l-----;s
20
1----;;1----;;123
S
U
Drain OFF
+ CS(on)
17 Typical
Channel ON
45 Typical
Capacitance
OFF Isolation
75 Typical
CCRR
Interchannel
Crosstalk
Isolation
89 Typical
1+ 3
Positive Supply Current
1_ 3
Negative Supply Current
I L3
Logic Supply Current
IGNO
Ground Supply Current
P
p
L
y
15 Typical
OIRR
119
Source OFF
Note 1
dB
300
300
300
300
300
300
-300
-300
-300
-300
-300
-300
300
300
300
300
300
300
-300
-300
-300
-300
-300
-300
pA
ZL ~ 7511
Vs ~ 2 Vpp
f
=
1 MHz
VIN = 0 V or 2.4 V
ICMK·C
NOTES:
1: VIN = Input voltage to perform proper function.
For Logic "'" - VINH = 2.0 V
For Logic "0" - VINL = 0.8 V
2: See Switching Time Test Circuit.
3·72
3: Limits of these paramaters are tested 100% at 25 "C and 125"C for "/883"
devices.
4: For "/883" devices these parameters are 100% tested at 25"C.
5: Signals on Sx. Ox or 1NX exceeding V+ or V- will be clamped by internal diodes.
Limit forward diode current to maximum current ratings.
Siliconix
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC
INPUT (lN1l 3V
tr<20ns
t,<20ns
OV
SWITCH
INPUT
Vs
+15V
+5V
50%
SWITCH
OUTPUT
SWITCH
INPUT Sl
-t-C~-.--o Vo
Vs= .10V
SWITCH
OUTPUT IVol
Note:
IREPEAT TEST FOR IN21
Logic input waveform is inverted for switches
v
that have the opposite logic sense control.
-VS
RL
0RL + 'OSlonl
CHARGE INJECTION TEST CIRCUIT
t.Vo
RGEN
Sx
r--\~
T
Vo
--
VO-
~
VGEN
INX
~
ON
OFF
~
'------------'
ON
:I>
::s
a
o
ca
I:>.Vo ~ measured voltage error due to charge injection.
The error voltage in coulombs is ~Q = CL x .t:J.VO.
CIt
...--~
SCHEMATIC DIAGRAM (typical channell
V+
ft
::s-
CD
fit
VL 0-.............--...,
GNO 0---4>-----'
~----+_----~--------oox
INX o----"I/I('r----;............I
V-
Siliconix
3-73
~
APPLICATIONS
~
C!)
Q
The Make-Before-Break operation of the DG243 provides simple transient suppression in these two important applications.
V'N _________________________
~--------------~--~VOUT
10K
VOUT~
1K
'N--.J
J1. o-_ _ _-".'N,-I.:>...1
'00
CLEAN TRANSITIONS NO GLITCHES DUE
TO CHARGE COUPLING
1/2 DG243
PRECISION PROGRAMMABLE GAIN AMPLIFIER
Figure 1. Improving Transient Response in Programmable
Gain Amplifiers. uGetting Rid of Glitches",
Figure 1 shows a minimum amount of glitching during changes of gain states. The relatively low impedance of the gain
setting resistors 10K, 1 K, 100D shunt the injected charge to ground minimizing transient effects ocurring at the inverting
input of the op amp. Consequently, these transients are not amplified to VOUT.
>---<1>-0 vOUT
Figure 2. Minimizing Glitches in Audio Switching
Figure 2 takes advantage of the Make-Before-Break operation of the DG243 by shorting transition current to real ground
instead of virtual ground. The proper offset voltage specification for op amp selection gives the best results.
The circuit outperforms its Break-Before-Make cousin, the DG5043 in this application.
3·74
Siliconix
Low-Charge Coupling JFET
Analog Switches
designed for •••
H
Siliconix
BENEFITS
•
• Low Error Sample and Hold
Circuits
• 100 MHz Signal Switching with
High OFF Isolation
• Presettable Integrators with
Minimum Offset Error
• Low Distortion Click Free
Audio Switching
Minimum Signal Errors
o Low Charge Feedthrough 7 Picocoulombs
Typical
o Low "ron x ID(OFF) Error Factor
o Low Leakage Less Than 10 Picoamps
Typical
o Low Distortion - Constant ON Resistance
•
Easily Interfaced
o TTL and CMOS Logic Compatibility
Over Full Temperature Range
•
Compact Circuit Layouts
o Several Form Factors Available in Single
Packages (eg_ 2XSPST, SPDT, 2XSPDT,
2XDPST)
DESCRIPTION
The DG281 series incorporates N-channel junction-type field-effect transistors (JF ETs) designed to function as electronic
switches_ Level-shifting drivers enable TTL or CMOS outputs to control the ON-OFF state of each switch_ The driver is
designed to provide break-before-make action when switching from one channel to another_ The low switch capacitance
results in a minimal amount of charge-feedthrough into the analog signal path_ In the ON state each switch conducts current
equally well in either direction_ In the OFF condition the switches will block voltages up to 22_5 V peak-to-peak_
PIN CONFIGURATIONS (Top View)
Dual-In-Line Package TO-116
V'
"
"
--
SCHEMATIC DIAGRAM (Typical Channel)
Metal Can Package TO-l00
DUAL SPST
J>
::s
IN,
II
V'
o
VL
ORDER NUMBERS:
DG281AA OR DG281BA
SEE PACKAGE 2
ORDER NUMBERS:
DG281AP OR DG281BP
SEE PACKAGE 11
~~t~:'~~'~.~
D~'~~
IN
J
~
v+
1
:.]
co",9'DT
a
v-*
1
6
~L
OFF
ON
,.,
~~:
ON
OFF
vR *Common to Substrate and Case
ORDER NUMBERS:
DG287AA OR DG287BA
SEE PACKAGE 2
I ::
:~
v+
ti
9
v-
Vt.
1
8
VA
ORDER NUMBERS:
DG287AP OR DG287BP
SEE PACKAGE 11
=="-'==-:-:-1
Dual-In- Line Package
Dual-In-Line Package . .
CD
~
II
II
VR
v+
Positive
+15 ....
DUAL SPOT
SW 1 SW3
LOGIC
SW2
SW4
0
ORDER NUMBERS:
DG284AP OR DG284BP
SEE PACKAGE 12
1
OFF
ON
CD
v-
fft
APPLICATION HINTS*
Voltage
IVI
IN,
"::s-
I I ~+------+----.r---'
II
Supply
0,0:;:;:;:=:3;;;",
.-.
CIt
NC
ON
OFF
VIN
Logic Input
vVL
VR
Negative
Logic Reference Voltage
Supply Supply
Supply VINH MinI
Voltage VINL Max
Voltage Voltage
IVI
IVI
IVI
IVI
Vs
Analog
Voltage
Range
IVI
15
+5
Gnd
2.0/0.8
-7.5 to +15
+10
·20
+5
Gnd
2.0/0.8
-12.5 to +10
+12
. 12
+5
Gnd
2.0/0.8
-4.5 to +12
*Appllcatlon Hints are for DESIGN AID ONLY, not guaranteed
ORDER NUMBERS:
SWITCH STATES ARE DG290AP OR DG290BP
FOR LOGIC "1" INPUT
SEE PACKAGE 12
(POSITIVE LOGIC)
and not subject to production testing.
HEleClncal Parameter Chart ba,ed on V+ = +15 V, V- = -15 V,
VL = 5 V, VA = Gnd.
Siliconix
3·75
ABSOLUTE MAXIMUM RATINGS
Wm~ ............................. ~V
Wm~ ............................ mv
VD to v- ............................ 33 V
..
Power Dissipation*
Metal Can" . . . . . . . . . . . . . . . . . . . . ..
14 Pin DIP"" . . . . . . . . . . . . . . . . . . . .
16 Pin DIP"'- . . . . . . . . . . . . . . . . . . ..
VD to Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
VLtoV- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
VL toVIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . BV
VL toVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . BV
VINtoVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . BV
VR to V- .,. ',' . . . . . . . . . . . . . . . . . . . . . . . 27 V
VRtoVIN . . . . . . . . . . . . . . . . . . . . . . , ..... BV
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . 20 mA
Storage Temperature .. . . . . . . . . . . .. -65 to +150°C
Operating Temperature (A Suffix) ..... -55 to +125°C
(B Suffix) .....
-20 to +85°C
450 mW
825 mW
900 mW
• All leads welded or soldered to PC board.
**Derate 6 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
****Derate 12 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested, at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications .
CO
MAX LIMITS
"~a
DG281A,DG284A
DG287A,DG290A
CHARACTERISTIC
_55°C
Drain Source
rDS(on)
2
Source OFF
Leakage Current
Drain OFF
Leakage Current
10(on) + IS(on)
IINL
I
N
IINH
ton
25°C 125°C -20°C
300
ON ReSIStance
S
W 'S(oft)
I
T
C IDloffl
H
Channel ON
Leakage Cu'rrent
Input Current,
Input Voltage Low
-250
DG281B, DG284B
DG287B, DG290B
25°C 85°C
500
300
500
0.5
100
100
0,2
100
100
-2
-200
-10 -200
-250
-250
10
20
n
nA
Input Voltage High
10
Turn-ON Time
150
180
Turn-OFF Time
130
150
0
Source OF F
10
A
Drain OFF
11
C
6 TYPical"
____________~~~C-D-I-Of-f)-------c~a~p~ac~"~an~c~e------+---------------------____~
12
''0
13
2 TYPical"
pF
See SWitching Time Test Circuit
VD=-5V,
IS = 0
VD
14-17 Typical'"
=
f= 1 MHz
Vs = 0
Vs = 7.5 V
11 Typical'"
ChargeFeedthrough
r-------------------------------Vs - 5V,
10=0
____________~~~C-S-lo-f-fl-------c~a~p~ac~it~an~c~e------+-----------------________~
Channel ON
COlon) + CS(on) Capacitance
tt
20
ns
9
tt
VD=7.5V,
VS=-7.5V
VD =
VS=-7.5V
"A
Input Current,
Is=-lmAtt
VD=-7.5V
VS=7.5V,
VD=-7.5V
-250 -250
-250
TEST CDND ITIDNS,
UNLESS NOTED:
V+""15V,V-"'-15V.
VL =5 V, VR =0
UNIT
See Charge-Feed·
pC
through Test Circuit
VS=-7.SV
4 TYPical
POWER SUPPLY CURRENTS
CHARACTERISTIC
25°C MAX LIMITS
14
DG281
DG284
1,5
DG287
DG290
0.8
1.S
1+
Positive Supply Current
1-
Negative Supply Current
-5
-5.5
-3
-S
LogiC Supply Current
4,5
4.5
3.2
4.S
17
'L
1+
POSitive Supply Current
1.5
0.1
0.8
1.S
18
1-
Negative Supply Current
-5
-4
-3
-S
'L
LogiC Supply Current
4.5
4.5
3.2
4.S
'R
Reference Supply Current
-2
-2
-2
-2
15
16
19
S
U
V
20
UNIT
tt Swit~h being tested ON or OFF as indicated, Input Logic Low 0.8 V.
Input Logic High 2V.
TRUTH TABLE
3-76
IN 1
SW1
O.SV
2.0 V
ON
OFF
DG2S4
0.8V
2.0V
OFF
ON
DG287
0.8 V
2.0 V
OFF
ON
DG290
O.SV
2.0V
OFF
ON
IN 2
SW2
0.8 V
2.0 V
ON
OFF
O.S V
2.0V
OFF
ON
SW3
OFF
ON
SW4
OFF
ON
ON
OFF
ON
OFF
O.SV
2.0 V
Siliconix
OFF
ON
ot
Y,N
5
=
vt
Both VIN "" 5 V. VIN '" 0
*Typical values are to DESIGN AID ONLY, not guaranteed and not subject to production testing_
DG281
Y,N =
mA
t If driver has two channels, both are active.
DEVICE
TEST CONDITIONS'
ON
OFF
DG281
DG284
DG287
DG290
CMJB-NH
CMJA-NH
CMJC-NH
CMJB-NH
CHARGE INJECTION TEST CIRCUIT
Charge Feedthrough vs
RGEN and VGEN
..
?L 5V
?+1SV
20
I
SWITCH
......--:
RGEN
-l-
V
*
GEN
LOGIC
Va
S
'N
n
~
iVR
t H390pF
O La
3V
\ ---.-L
/
2
0
L-I
'Vo
I
Va
RGEN-on
4
LOGIC "0" .. SWITCH OFF
VGEN
..l--t-_
I-"'
,/
• ./
~
It <10ns
1,
>
~ ~
25
,
Z
0
2.0
0
Supply Current vs
Temperature
"OFF" Isolation vs
Frequency
!
,
CD
DG281
T - TEMPERATURE I C)
T - TEMPERATURE fOCI
90
. . . . p. .
,~ -
'0
0
-dI
o
25
OG2a1
~
a
0
Supply Current vs
Temperature
,
Supply Current vs
Temperature
OG290
'::::::
3
I
...............
r-.... r-....
d--
k' .......
2
,~-
,
,.
0
-55 -35 -15
,
25
45
65
85 105 125
T _ TEMPERATURE ('CI
3-77
liN vs VIN and Temperature
rDS(on) vs Temperature
,.
(ij
1000
§
Vs
7.5 V
10"'-1 mA
V1NL =0
V 1NH "'5V
w
~
"
~
80
ilirr:
rr:
;;:
.!!
I.........
60
z
o
w
~
::>
z
~
o
1
e
,,/'
100
-55
VV
V
,,/'
,..... ....-
.....- ......-
"::>>~
U
:';
........
65
CAPACITANCE IS MEASURED ON
14
- - r- TEST TERMINAL
12
TI
COiMor
-'vIN~=oL
10
VINH '" 2 V
f= 1 MHz
cr~
1
~ 20
I
16
;3
I
"
r-
25
"«>-z
.......
40
CD(off)
'INH
-55 -35 -15
-15
w
I'-.. "NL
::>
C~'D": + C~'ODI I
18
t-...
>-
illrr:
5)
Capacitance vs VD or Vs
20
100
105
5
25
45
65
I
85 105 125
-10~
T - TEMPERATURE 1°C)
~
~
-2
0
2
4
8
TYPICAL SWITCHING TRANSIENTS
LOGIC INPUT
Equivalent "OFF" Circuit
a"
+6
+4
g
1
H-;::+=+=~Hlitl
t--tt-t-+-+-tt--+-+-+-+---i
+2 ~~~-+-~-t-~~-+-+-~
z
;;
VGEN=5V
+6
+4
If RGEN. RL or CL 15 Increased, there will be
proportional increases in me and/or fall timos.
I
+2
\
J
......
Application: THREE MODE INTEGRATOR
u;
!:i~
I=g
S~
+2
1«
0>-
SET
>5
>
-----"I"""---+--..::..:-r
INPUT ' .........
t~}"
-2
-2
FEATURES
VGEN = -5 V
,
+2
/
I
-4
/
-6
• MINIMAL INTEGRATION ERROR
DUE TO LOW CHARGE FEEDTHROUGH
• LOW LEAKAGE
1
0.4
0.8
2
T - TIME (,.,.Sl
LOGIC INPUTS
Application: VIDEO/BLANKING/SYNC. SIGNAL COMBINER
DG281
VIDEO
INPUT
\AAAAAAAAI
VVVVVVVVV
0*
VIDEO INPUT
0----+--------':.0-......+---1>-0 ~~T~~T
0* I
BlANKINGJL
_+-<>I
BLANKINGo--.....
SYNCJL
LrAN' ,
VIOE0'M
OUTPUT
,
,
0*
FEATURES
• MINIMAL OUTPUT SPIKES
DUE TO LOW CHARGE FEEDTHROUGH
• NEGLIGIBLE FEEDTHROUGH
DURING BLANKING INTERVAL
3·78
10
Vo OR Vs - DRAIN OR SOURCE VOLTAGE (VOLTS)
T - TEMPERATURE (OC)
SYNC
0----+-<>1
Siliconix
1/2
x DG281
1.2
1.6
Monolithic CMOS Analog
Switches
designed for
c
H
Q
Silicanix
c
BENEFITS
• • •
•
Battery Operated Circuits •
• Portable,
Leakage Switching
• Low
i.e. Sample and Hold Circuits
Systems
• Communication
Level Switching Circuits
•• Low
Fast Switching Circuits
•
•
Q
Environmentally Rugged
o Latchproof CMOS
Low Standby Power
o 0.06 /lW Typical
w
o
.....
(It
.,-.
CD
Minimizes Signal Error
o 0.1 nA Typical Leakage
m
Low Operating Power
o 0.06 /lW Typical for DG304-307
•
such as Multiplexers
• Standard Linear Dual Supply
Voltages or Single Supply"-.'------.
Systems
~.,--
Reduced Voltage Drop Across Switch in ON
Condition
o rds(on) < 50 n
• Minimizes Switching Time
o Typ ton & toff < 180 ns
• Minimizes System Power Requirements
o Single Supply Operation Capabilities
•
Easily Interfaced
o TTL, DTL and CMOS Input Compatible
•
Reduces External Component Requirements
PIN CONFIGURATIONS
DUAL SPST DG300 or DG304
Metal Can Package
Dual-In-Line and Flat Package
OROER NUMBERS:
V+ (SUBSTRATE AND CASE)
NC
D,
14
V+ DG300AP OR DG300BP
, I
D2 DG304AP OR DG304BP
1~ NC
NC
S,
IN,
11
NC
SEE PACKAGE 11
52
NC
., IN2
V-
DG300CJ
w
IN,
GND
GND
'-1..._ _-""
ORDER NUMBERS:
DG301AP OR DG301BP
DG305AP OR DG305BP
C
D1
NC
DG301CJ
~~
DG304CJ
DG305CJ
SEE PACKAGE 7
SEE PACKAGE 16
N
SEE PACKAGE 11
SEE PACKAGE 7
DG300AL OR DG304AL
TOP VIEW
TOP VIEW
ORDER NUMBERS:
SPDT DG30' or DG305
Dual-In-Line and Flat Package
~
1
14
J
J
:
IN "
-~-,
V
+
.J
Metal Can Package
V+ (SUBSTRATE AND CASE)
13
02
01
12
NC
81)
i
IN
J
i :~ ~~
GNO'
DG301AL OR DG305AL
SEE PACKAGE 16
1
'0
1
~
°2
H
82
I
NC
" NC
" V-
GND
TOP VIEW
TOP VIEW
ORDER NUMBERS:
OG300AA OR OG300BA
"-:=::0=-:0--:::::-::-1 OG301AA OR OG301BA
DG304AA OR DG304BA
f--::--t-=::-t~-:-1 DG305AA OR DG305BA
SEE PACKAGE 2
SEE PACKAGE 2
DUAL DPST DG302 or DG306
DUAL SPDT DG303 or DG307
Dual-In-Line and Flat Package ORDER NUMBERS:
ORDER NUMBERS:
NC~"
V+
8
3
DG302AP OR DG302BP
'J S4 OG306AP OR OG306BP
j
D3
t
D,
4
I
8,;
I
I
11
D4
I
11
:
10
02
82
I
IN, •
GND
., IN2
1
8
TOP VIEW
DG303AP OR DG303BP
DG307 AP OR DG307BP
SEE PACKAGE 11
SEe PACKAGE 11
DG302CJ
OFF
ON
DG306CJ
ON
OFF
SEE PACKAGE 7
V- DG302AL OR DG306AL
SEE PACKAGE 16
DG303CJ
Dual-In-Line and Flat Package
NC
83
~'4 8V+
4
l
1]
D3 ]
12
04
02
82
D,
4
I
I
11
DG307CJ
8,
&
:
I
10
SEE PACKAGE 7
IN, •
DG303AL OR DG307AL GND
SWITCH STATES ARE FOR LOGIC "I" INPUTS IPOSITIVE LOGIC) SEE PACKAGE 16
Silicanix
w
o
o
• IN2
I
B
V-
TOP VIEW
3-79
ABSOLUTE MAXIMUM RATINGS
Power Dissipation *
14 Pin Sidebraze DIP (P)**
14 Pin Plastic DIP (J)***
Metal Can (A)****
Flat Package (L)*****
V+ +18 V, V+ -36 V
V IN to Ground
V+ to V-Vs or VD
+36 V
V+ to Ground .
V+ to V+36 V
Current, Any Terminal (Except S or D)
30mA
Current, S or D, Continuous
30mA
Pulsed 1 ms 10% Duty Cycle
100mA
-55 to +125°C
Operating Temperature (A Suffix)
(B Suffix)
-20 to +85°C
(C Suffix)
o to +700 C
Storage Temperature (A & B Suffix)
-65 to +1500 C
(C Suffix)
-65 to +125°C
825
470
450
750
mW
mW
mW
mW
* Device mounted with all leads welded or soldered to
PC board.
**Derate 11 mWfC above 75°C
***Derate 6.5 mWfC above 25°C
****Derate 6 mWfC above 75°C
*****Derate 10 mWfC above 75°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
Max Limits
TVp1
2SD C
1
Minimum Analog Signal
Handling Capability
rOSl on )
Dram Source
ON Resistance
ISloft)
Source OFF
Leakage Current
IOloffJ
Dram OFF
Leakage Current
1010nl
Channel ON
Leakage Current
Input Current
DG30o-3030nlv
-0.001
"NH
Input Voltage High
DG300-307 Only
0.001
-0.001
-1
2
13
I4
I5
1I~
1
1-
S
W
I
T
C
H
8
19
10
I'll
112
I
N
P
U
T
S
_55°C/
_20°C
VANALOG
1-
C Suffix
AlB Suffix
Characteristics
±15
2So C
12SoC
85°C
±15
±15
O°C
Unit
Test Conditions
V+ = +15 V, V- = -15 V. Gnd '" 0 V
25°C 10°C
±15
±15
V
SWitch ON IS = 10 mA
30
50
50
15
50
50
15
30
50
50
15
50
50
15
Vo = -10 V. IS '" +10 mA
Vs = +14 V, Vo '" -14 V
Vo = +10 V,IS '" -10 mA
n
Note 2
0.1
1
100
5
100
-0.1
-1
-100
-5
-100
0.1
1
100
5
100
-0.1
-1
-100
-5
-100
0.1
1
100
5
100
Vo = VS= +14 V
-0.1
-2
-200
-5
-200
Vo" Vs "'-14 V
-1
-1
-1
-1
1
1
1
1
-1
-1
-1
Vs =-14V, Vo = +14 V
Note 2
nA
VO=+14V,VS=-14V
VO=-14V,VS=+14V
V'N~ +5.0
"A
v
V 1N ",+15V
IINL
Input Current Input Voltage Low
13
ton
TurnON Time
14
toff
Turn OFF Time
15
ton
Turn ON Time
toff
Turn OFF Time
ton - toff
Break-Before-Make OG301/303
Interval
DG305/307 Only
50
CS(offi
Source 0 F F Capacitance
14
Vs
Co (off)
Drain OFF Capacitance
14
V D '" D, Note 2
Cotonl + CS(onl
Channel ON Capacitance
40
C'N
Input Capacitance
11-
116
111
I18
I19
120
121
122
1-
0
V
N
A
M
I
C
DG300-303
Only
150
130
250
DG304-307
Only
110
250
10
150
1+
Positive Supply Current
Negative Supply Current
OG300-303
Only
21
28
-30
29
31
pF
= Vs = 0, Note 2
f= 1 MHz
Y,N
0, RL - 1 K fl, C L - +15 pF
Vs = 1 V RMS ' f = 500 kHz
0.23
1
0.5
0.5
1
-0.001
-10
-10
-100
-100
rnA
VIN = 4 V (One Input! tAli Other Inputs = 01
S
U
p
P
L
V
1+
Positive Supply Current
1-
Negative Supply Current
0.001
10
10
100
100
-0.001
-10
-10
-100
-100
VIN = O.S V (Allinputsl
1+
Positive Supply Current
1-
Negative Supply Current
1+
Positive Supply Current
1-
Negative Supply Current
0.001
10
10
100
100
-0.001
-10
-10
-100
-100
"A
VIN = +15 V tAlIlnputsl
OG304-307
Only
0.001
10
10
100
100
-0.001
-10
-10
-100
-100
VIN = 0 (All Inputs)
~~~:~~~s~~;~~~~~ !~~ ~~~cP4/~85=h~~:Uat ~/g;i~ :!:e~nVfa~~~~~~~ OFF Isolation generally improves by
7 dB @ 500 KHz over value Shown here.
3-80
Vo
VIN =+15 V
dB
NOTES:
1. Typical values are for DESIGN AID ONLY,.not guaranteed and not subject to production testing.
2. VIN = Input voltage to perform proper function. DG300-303: VIN - For logic ",",..4 V, for logic "0" = 0.8 V.
DG304-307: V,N - For logic "'" = " V, for logic "0" = 3.6 V
3.
= 0, Note 2
VIN = 0
58
1-
26
See Break-Before-Make Time Test Circuit
3.5
25
-
nS
6
24
1-
VIN "'0
300
See SWitching Tim!! Test Circuit
OFF Isolatlon 3
23
Note 2
Silicanix
DG300 ICMA-A
DG302 ICMB-A
OG301 ICMA-B
OG303 ICMB-B
OG304 ICMA-C
OG306 ICMB-C
OG305 ICMA-O
OG307 ICMB-O
Monolithic CMOS Analog
Switches
designed for • •
H
Siliconix
BENEFITS
•
Environmentally Rugged
o Latchproof CMOS
iii
• Portable, Battery Operated Circuits·
• Low Leakage Switching
i.e. Sample and Hold Circuits
Low Standby Power
o 0.06 IlW Typical
•
Minimizes Signal Error
o 0.1 nA Typical Leakage
o Low Operating Power
o 7.5 mW Typical
• Communication Systems
•
• Low Level Switching Circuits
Fast Switching Circuits
such as Multiplexers
•
Linear Dual Supply
• Standard
Voltages or Single Supply Systems
Reduced Voltage Drop Across Switch in ON
Condition
o rds(on) < 50 n
• Minimizes Switching Time
o Typ ton & toff < 180 ns
• Minimizes System Power Requirements
o Single Supply Operation Capabilities
•
Easily Interfaced
o TTL, DTL / CMOS Input Compatible
o Pin to Pin Replacement for DG180 Series
Switches
•
Reduces External Component Requirements
o Logic Input Overvoltage Protection
DESCRIPTION
The DG381 through DG390 switch family features four switching functions using CMOS technology for low and nearly
constant ON resistance (less than 50 n) over the full analog signal range. In the ON condition the switches will conduct
current in either direction with no offset voltage. With low power dissipation, a few milliwatts, this series of switches
becomes an ideal candidate for battery·powered or remote switching applications. The switching speed is among the fastest
available with the low quiescent power dissipation. In the OFF condition, the switches will block voltages up to 30 V
peak·to·peak. A logic input driver controls the ON/OFF state of the switches. (See the "Pin Configuration" for switch
status with a logic "1" input.) The switches are TTL and CMOS input compatible and have a logic "0" state with an input
less than 0.8 V and a logic "1" state with an' input greater than 4.0 V. A pull-up resistor should be added for totem pole
TTL outputs. The logic inputs are protected against overvoltage up to 18 V above and 36 V below the positive supply. The
combination of low cost, low power, low resistance and fast speed optimizes system design.
_
:J>
::::I
D
0
_
r------------------------------.----------------------------~~
DUAL SPST DG381
Metal Can Package
D1~
_~~ ~21N2
S1
IN1 '
V+*
.
, V-
.
,
GND
NC
TOP VIEW
ORDER NUMBERS:
DG381AA OR DG381BA
SEE PACKAGE 2
SPOT DG387
Dual-In-Line Package
Dual-In-Line Package
,~~~":~
V+ "
NC '
SWI
SW2
ON
OFF
LOGIC
., V• GND
LOGIC
SW 1
a
OFF
ON
1
SW2
ON
OFF
~~~:
-=
:I
"~
0
XI
OG381-390
~l~
I
~
OG304-307
_
20
'"
106
105
~
g§
107
+10
10
+5
~~~~I~~~I
~
10
~
0.1
~
w
"uI
25
65
45
85
125
105
25
45
T - TEMPERATURE (OC)
85
65
125
105
T - TEMPERATURE (OC)
n~channel
70
2
60
20
Y+"'+15V
V-=-15V
~
Vs"'Vc
w
V
/'
....
40
./
_I--"""
.
....
13
~u
....
i<
~
I
C
"
-o
II
"
""-
CD
CIt
VGEN=5V
."-.
~
+5
....
?
~
CD
VGEN = OV
-5
V+=+15V
V-'= -15 V
TA=25°C
16
-5
u
50
~
,
III
2
.:r
30
12
I--
VGEN=-5V
IOGJ04~~~07) ..... l /
--- -
/t- TR~~~I~~~ci~~~~T~~~~~ATE
~
-5
j.....-
i
,.. ....
\
2
0
~
Input Capacitance vs
Input Voltage
Output ON Capacitance
vs Drain Voltage
If
-....: r-
5"
~
leakage minus the p-channel
leakage. This difference can be positive, negative, or zero depending on the analog voltage
and temperature, and will vary greatly from unit to unit.
~
III
·SEE NOTE
>
....
0.01
-
*The net leakage into the source or drain is the
"0I
.......
VGEN=10V
~
o
C
"
E
0.1
+5
o
~
o
u
I
I I
I
~
;2
~~
~
-,
w
""
"
~~
2
T
T
I
I
I
a'"
"'~
"....
-r
0!304i THJu 0630J'iINPUT"1
LOGIC INPUT
i:;
~~
-!!
w
u
10
,.... f- ....,
10"
....
0"-
u:
15
10(on) vs Temperature*
1
~
ii
~~
u
;;
~
'" w
I~
"
g
f - fREQUENCV (Hz)
100~~
~~
LOGIC INPUT
2
10 100 lK 10K lOOK 1M
LOGIC SWITCHING FREQUENCY (Hz)
50% DUTY CYCLE
TH~U dG30L
->
0
IS(off) or 10(off) vs Temperature*
a:~
i<
....
I
II
0.1
5
I:l
I
i2
0
~
2
40
~
0
-<
~
DG300-303
D63J
OG384 THRU OG390
OGr81 IINVE!"TEID L~GIC
(DG300-DGlOl)
(DG381-DG390)
-10
I
L..--
I
r'
VGEN=-lOV
+
j
Q
u
0.4
20
10
12
14
Vo - ORAIN VOLTAGE (VOLTSI
16
10
12
VIN - INPUT VOL TAGE (VOL TSJ
Siliconix
14
16
0.8
1.2
1.6
t - TIME (,,51
*Note: The turn-off time IS prlmarilv hmlted here bV the
RC time constant (100 n51 of the load.
3-83
TYPICAL CHARACTERISTICS' (Cont'd)
Switching Time vs Temperature
Switching Time vs Temperature
OG304-307
OG300-303, OG381·390
22.
v+
200
18.
J
'"
""z
";:
"
~'"
160
140
120
100
80
60
220
+15V
---V-"- 15V
VINH=4.0V
VINL
SWITCHING TIME TEST CIRCUIT
(DG300-307 DG381-390)
=ov
toN
,.......
,..,
200 -V+_+i5V I
,/
V-=-15V
!
180 -VINH=+15V
160 -VINL" ov
~
140
!;j
i..--'
i..--' f-""
tOFF
~ 120
i
100
iii
80
~
lOGIC
INPUT
/'
.....-
~
t r < 20ns
tf< 20ns
./
OV
Vs
to~F
SWITCH
OV
OUTPUT
60
40
40
20
20
o
o
-65 -35 -15
5
25
45
65
85
-55 -35 -15
105 125
T - TEMPERATURE (OC)
5
25
45
65
85 105 125
00300-303
T - TEMPERATURE fOCI
OG381·0G390
DG3()4.307
Switching Time and Break-Before-Make Time
vs Positive Supply Voltage
Switching Time
vs Positive Supply Voltage
OG300-303,OG381-390
+15V
TA
VrNH=4.0V
\
"
!I:!
r-..."-
r-- "-
1\
1
i"'-o=: b -
40
o
10
o
15
10
V+ - POSITIVE SUPPLY VOLTAGE (VOLTS)
Switching Time
vs Negative Supply Voltage
Switching Time
vs Negative Supply Voltage
Input Switching Threshold
vs Positive Supply Voltage
OG304-307
OG300.307,OG381-390
V+
'"
""";: ~
I:!
~
100
'off
240
+15V
TA "'2S·C
VINH" +4.0 V
VINL "0
200
150
15
V+ - POSITIVE SUPPLY VOL rAGE (VOLTS)
OG300-303,OG381-390
z
-
I'....
80
-15V
'-
tbbm DG301/DG3D3 ONt V
250
]
'on
\.
I
Vo
'\:
1\ 'off
120
SWITCH
OUTPUT
\
z
;:
I, I\,
o
\
~160
\
toff
'on
1\
:g 200
'"
VINL =QV
=-15V
=25"C
VINH-V,
VINL = 0
VTA
=-15V
= 25° C
1\
·,NVERTED lOGIC FOR OG381
OG304-307
240
V
4V
15 V
!
v+
200
"
!;j
.....
I
"z";:
160
I:!
~
120
.
80
-+15V
TA = 25°C
VINH = +15 V
VINL "0
",",'on
-..........
...........
r---
I
1
{
50
'off
40
o
-15
-10
-5
v -
NEGATIVE SUPPLY VOLTAGE (VOLTS)
-5
-10
-15
10
V- - NEGATIVE SUPPLY VOL rAGE (VOL TSI
15
V+ - POSITIVE SUPPLY VOLTAGE (VOLTSl
BREAK·BEFORE·MAKE TIME TEST CIRCUIT SPDT (DG301, DG303, DG305, DG307, DG384, DG390)
r---.. .\.
LOG IC
LOGIC "1" = SWITCH ON
INPUT
-.JVINH
50%
OV
f::::==:-:===:::---,V-'::'4"!!.VH'-j
,OG300-303
DG304-307
+15V
DG381·0G390
V+
15 V
SWITCH
OUTPUT
'
vS1---------~::::::~--------
~~----~~r_t_~---.----.~OVOI
~4-----c',.~~~~--~-.--_+~V02
~~!~~ 0 V_V.::O~1_ _- '
CL2
33pF
SWITCH
OUTPUT
3·84
Siliconix
CII
PARTIAL SCHEMATIC OF TYPICAL SWITCH (DG300-307, DG381-390)
v+o-~~--~----~----~----~
__
2
c
------~----~----~----~-----.
f»
CII
Q
~
c
.....
GNDO--------------4---~
CII
Q
L---~--~~--__oD
...
~
v-o-------------------------~--------~----~----~----_+------~
INPUT PROTECTION
OCt
ANALOG SWITCH
LOGIC INTERFACE AND SWITCH DRIVERS
I
CII
Q
APPLICATIONS
The OG300 series of analog switches will switch positive analog signals while using a single positive supply. This will allow
use in many applications where only one supply is available. The trade·ofts or performance given up while using single
supplies are: 1} Increased rOS(ON); 2) slower switching speed. Typical curves for aid in designing with single supplies are
supplied in the Figures below. As stated in the absolute maximum ratings section of the data sheet, the analog voltag~
should not go above or below the supply voltages which in single operation are V+ and 0 volts.
Switching Time vs V+ - Positive Supply Voltage
ROS(on) vs Analog and Positive Supply Voltage
With V-= OV
110
"l
'50
in
:z: 130
"
110
z
0
1
I
e
v--ov
TA '" 2SOC
III
'\
w
~
iiirr:
v--ov
TA '" 25°C
II
f!
"z
V+=+5V
90
~
10
.".
50
30
10
=
~
Single Supply Operation
vl=Lov
.,.....
~
\'or
'i---:off '}....
TiTI
10
:I>
\
12
14
10
"o-
fa
15
."-.
V+ - POSITIVE SUPPLY VOLTAGE (VOLTS)
V A - ANALOG VOLTAGE (VOLTS)
CIt
~
Input Threshold Voltage vs Positive Supply
::r-
CD
1ft
Single Supply Range:
(V- and GN D Tied Together)
V+: +5 V to +25 V
Analog Signal Range:
V-.;; VANALOG';; V+
'0
'5
V+ - POSITIVE SUPPLY VOLTAGE (VOL lS)
Siliconix
3-85
c
0
GIll
~
0Q
..
Versatile CMOS
Analog Switches
H
Siliconix
I
c designed for . . .
co
~
•
~ •
g•
C •
•
0 •
0Q
0
~
I
0
0
~
BENEFITS
• Environmentally Rugged
o 40 V Power Supply Maximum Rating
o Static Protected Logic Inputs
o Latch Proof
Portable, Battery Operated
Circuits
• Minimizes System Power Requirements
o Operates Off Single Supply when V - Tied
toGND
o Power Dissipation .06 I1W Typical DG304A307A
Low Level Switching Circuits
Sample and Hold Circuits
• Fast ton and toft <110 nsec DG304-DG307A
• MInImIzes SIgnal Error
o Low rOSlon) 30 ohm Typical
o Low Leakage 40 pA @ 25°C
1 nA @ 125°C
o Full Rail to Rail Analog Signal Range
High Speed Switching
Programmable Gain Amplifiers
Single or Dual Supply Systems
• Easily Interfaced
o TTL and CMOS Compatible
• Pin for Pin Compatible With
o Harris HI·3XX Family
• DG381A-DG390A are Pin for Pin Compatible with DG180 Series
Q
DESCRIPTION
The DG300A and DG381 A series designed on the Siliconix PLUS-4O CMOS process provides solid state switch action with 30 ohms
contact (ON) resistance and very high OFF resistance. True bidirectional switch action occurs over the full analog signal range of
± 15V, with Break-Before-Make operation to prevent momentary shorting of signal inputs.
FUNCTIONAL DESCRIPTION
3-86
FUNCTIONAL DIAGRAM (typical channel)
PART
NUMBER
TYPE
SWITCH
COMPATIBILITY
DG300A
DG301A
DG302A
DG303A
DG304A
DG305A
DG306A
DG307A
DG381A
DG384A
DG387A
DG390A
Dual SPST
SPOT
Dual DPST
Dual SPOT
Dual SPST
SPOT
Dual DPST
Dual SPOT
Dual SPST
Dual DPST
SPOT
Dual SPOT
TTL
TTL
TTL
TTL
CMOS
CMOS
CMOS
CMOS
TTL
TTL
TTL
TTL
L
>-
V
~
INX 0-LOGIC
INTERFACE
~D
~
C
PROTECTION GND
Siliconix
r
Y
LEV·EL
SHIFTER
T
~
V-
I- -
L
SWITCH
CONTACT
sx
~
CII
Q
w
PIN CONFIGURATIONS
Dual·ln·Llne and Flat Package
Dual-ln·Line and Flat Package
V+ (SUBSTRATE AND CASE)
NC~"
NC
S,
S1 '
DG304AAA OR DG304ABA
SEE PACKAGE 2
: ' S2
NC
NC
IN,
ORDER NUMBERS:
V+ V+ (SUBSTRATE AND CASE)
IN '
IN2
ORDER NUMBERS:
GND ..._ _--'- VDG3DDAAK OR DG3DDABK
TOP VIEW
OR DG3DDACK
DG304AAK OR DG304ABK
OR DG304ACK
SEE PACKAGE 9
DG3DDACJ
I
: "NC
IN'
NC
NC
.J,
ORDER NUMBERS:
GND , VDG301AAK OR DG3D1ABK
TOP VIEW
OR DG301ACK
DG305AAK OR DG305ABK
OR DG306ACK
LOGIC SW 1
SEE PACKAGE 9
0
DG3D1ACJ
DG304ACJ
DG305ACJ
SEE PACKAGE 7
DG3DDAAL OR DG304AAL
SEE PACKAGE 16
SEE PACKAGE 7
DG301AAL OR DG305AAL
SEE PACKAGE 16
~
- NC
'v-
~
)II
I
", -;
NC
DG300AAA OR DG300ABA
Metal Can Package
~~, _~,:' ~~ SI~D'~2S2
D,
GND
TOP VIEW
o
o
SPDT DG301 A or DG305A
DUAL SPST DG300A or DG304A
Metal Can Package
GND
TOP VIEW
OROER NUMBERS
DG301AAA OR DG301ABA
DG306AAA OR DG306ABA
SEE PACKAGE 2
CII
Q
w
o
;:
CII
Q
...w
at
)II
I
CII
Q
DUAL DPST DG302A or DG306A
DUAL SPDT DG303A or DG307A
Dual-ln·Line and Flat Package
Dual-In-lme and Flat Package
~~~:::~!
ORDER NUMBERS:
DG303AAK OR DG303ABK
OR DG303ACK
DG307AAK OR DG307ABK
OR DG307ACK
SEE PACKAGE 9
ORDER NUMBERS:
DG302AAK OR DG302ABK
OR DG302ACK
T
I
DG306AAK OR DG306ABK
D, • I
I " D2
OR DG306ACK
S,_
I
:
'" S2
SEE PACKAGE 9
IN, ,_
- IN2
DG3D2ACJ
GND'
, VDG306ACJ
SEE PACKAGE 7
TOP VIEW
DG302AAL OR DG306AAL
SEE PACKAGE 16
DG303ACJ
DG307ACJ
SEE PACKAGE 7
DG303AAL OR DG3D7AAL
SEE PACKAGE 16
~~~I-:~~:
D3 ' _
D"S,
'--,:
I
-_
I
IN1"
I
w
ooD
o
)II
,- D4
"D2
S2
"
I
'"
" IN2
GND '
, VTOP VIEW
III
Metal Can Package
SPDT DG387A
Dual-In-line Package
Dual-In-Line Package
~
,~~p].
" m
.
SI ~~
D"
DUAL SPST DG 381 A
" IN 2
_.
, V-
IN, ,
,
V+*
~
GND
NC
TOP VIEW
ORDER NUMBERS:
DG381AAA OR DG381ABA
SEE PACKAGE 2
V+ "
NC '
-, V, GND
0
1
,
SWI
SW2
SI --
ON
OFF
'(SUBSTRATE
AND CASE)
'(SUBSTRATE
AND CASE)
53'
54'
D4'
NC I
__
--
" GNO
I
"NC
" V+
1
10lN2
02 •
-, V,
GNO
ORDER NUMBERS:
DG387AAK OR DG387ABK
OR DG387ACK
SEE PACKAGE 9
DG387ACJ
SEE PACKAGE 7
IN
"
S2
"NC
I
I
V+*
,
4
"
I.
V-
GND
ORDER NUMBERS:
DG387AAA OR DG387ABA
SEE PACKAGE 2
NC
I
'" INI
01
1I l l , " S
I
,
0
, 52
SWI
SW2
SW3
SW4
D3'
I
"V-
53'
"__
" GND
OFF
ON
ON
OFF
S4'
04
---
"NC
ti
I
11
V+
NC
I
i
10
IN2
02
8
9
82
ORDER NUMBERS:
DG~AAKORDG~ABK
DRDG~ACK
SEE PACKAGE 10
DG~ACJ
SEE PACKAGE 8
SWITCH STATES ARE FOR LOGIC "I" INPUTS (POSITIVE LOGIC)
Siliconix
.
--~
It
:r
CD
TOP VIEW
TOP VIEW
UI
(ft
Dual-I n-Line-Package
LOGIC
a
o
CIt
NC
TOP VIEW
DUAL SPDT DG390A
Dual·'n·Llne Package
NC'
i "S
I~ IN,
01e
I
03'
I
"V-
II, NC
TOP VIEW
DUAL DPST DG384A
ORDER NUMBERS:
DG3B4AAK OR DG3B4ABK
OR DG3B4ACK
SEE PACKAGE 1~
DG3B4ACJ
SEE PACKAGE 8
J
IN --
V+ "
NC I
TOP VIEW
ORDER NUMBERS:
DG381AAK OR DG381ABK
OR DG381ACK
SEE PACKAGE 9
DG381ACJ
SEE PACKAGE 7
~"2
~~~:
--, ::~i ~ -
D2
LOGIC
)II
:::I
Metal Can Package
3·87
ABSOLUTe MAXIMUM RATINGS
Voltages referenced to VV+ .............................................. 44V
GND ............................................. 25V
Digital inputs4, VS, VD ............. -2Vto (V+ +2V)or
30 mA, whichever occurs first
Current Any Terminal (Except S or D) ............... 30 mA
Current, S or D, Continuous ....................... 30 mA
Pulsed 1 ms 10% Duty Cycle .................... 100mA
Operating Temperature (A Suffix) ............ -55to 125°C
(9 Suffix) ............. -20 to 85°C
(CSuffix) ................ Oto70oC
Storage Temperature (A & 9 Suffix) ......... -65to 150°C
(C Suffix) ............. -65to 125°C
Power Dissipation*
Cerdip (K)'* ................................... 825mW
Plastic DIP (J)'" ............................... 470 mW
Metal Can (A)···· .............................. 450 mW
Flat Package IL)····· ........................... 750 mW
'Device mounted with all leads soldered or welded to
PC board.
"Derate 11 mW/oC above 75°C.
*'*Derate 6.5 mW/oC above 25°C.
****Derate 6 mW/oC above 75°C.
*****Derate 10 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits to
assure conformance with specifications.
MAX LIMITS
TYP'
2S'C
CHARACTERISTIC
,
VANALOG Minimum Analog Signal Handling Capability
2
rOSlon)
3
S
4 W
'Sloff)
5 I
T
6 C
H Ictoff)
7
8
IOlon)
Drain Source ON Resistance
Source OFF Leakage Current
Channel ON Leakage Cunent
9
I
'0 N
IINH
P
U
'2 T IINL
"
Input Current
Input Voltage High
'oo
Turn-ON Time
'4
'off
Turn-OFF Time
'5
'00
Turn ON Time
'6
'off
Turn OFF Time
'7
ton-toff
Break-BeforeMake Interval
'8 V 0
N
'9 A CSloffl
M
20 I COloffl
C
COlonli;
2'
DG300A-307A Only
DG38'A·390A
DG300A-303A Only
DG304A-307A Only
DG30'A/303A/305A/307A
3fI1A/390A Only
± '5
50
75
30
50
50
75
50
50
75
Vo=-lOV, IS= +10mA
'00
5
'00
V S - +14V. Vo--14V
-'00
-5
-'00
Vs=-14V. Vo= +14V
'00
5
100
-0.'
-'00
·5
-'00
Vo=-14V. Vs= +14V
0.'
1
'00
5
100
VO:Vs= +14 V
-0.'
-2
-200
-5
-200
Vo=Vs=-14V
0.'
-0.00'
-0.00'
-,
,
-,
-,
,
-,
250
250
70
'50
3
'4
Drain OFF Capacitance
'4
Channel ON Capacitance
40
1+
Positive Supply Current
27
1-
Negative Supply Current
DG38' A·390A
1+
Positive Supply Current
DG300A-303A Only
VIN = +15V
"A
V1N-0
See Switching Time Test Circuit
n,
See Break-Before-Make Time
Test Circuit
mV
RGEN =QQ. VGEN ::=OV. CL=.01 /AF
Vs=O. Note 2
Vo=O. Note 2
pF
Vo=Vs=O. Note2
V1N= +15V
0.23
,
0.5
0.5
,
-0.00'
·'0
-'0
-,00
-100
o,(xn
'0
'0
'00
'00
-0.00'
·'0
-'0
-,00
-'00
Positive Supply Current
0.001
'0
'0
'00
'00
-0.00'
-'0
-'0
-'00
-'00
32
1+
Positive Supply Current
O,(X)l
33
1-
Negative Supply Current
-0.00'
=,
V1N=0. RL
KQ.
Vs = , VRMS' f = 500 KHz
dB
Negative Supply Current
DG304A-307A Only
f=lMHz
VIN=O
7
Negative Supply Current
Nota 2
V'N=+5.0V
6
26
Nota 2
Vo=+14V,VS=-14V
nA
50
Source OFF Capacitance
Note 2
300
'30
74
L
-,
,
-,
110
Channel to Channel Crosstalk
V 1-
-,
,
-,
'50
CCRR
3'
Vo - +10V. 15=-10 rnA
Q
,
-,
,
-,
0.'
25
1+
V
± '5
50
62
30
TEST CONDITIONS.
UNLESS NOTED: V+ =15 V.
V-=-'5V. GND=OV
75
OFF Isolalion3
P
71l"C
±'5
OIRR
U
UNIT
2S'C
50
24
28 S
O'C
±'5
Input Capacitance
29 P 1-
'2S'C1
B5"C
50
C'N
23
2S"C
30
Charge Injection
Cs on
22
±'5
0.00'
Input Current Input Voltage Low
'3
D
-55"C1
-20'C
-0.'
Drain OFF Leakage Current
B/C SUFFIX
A SUFFIX
10
'0
'00
'00
-'0
-'0
-'00
-'00
mA
V1N = 4V lane Inputl
(All Other Inputs"" 0)
V1N =0.8 V (All Inputs)
"A
V 1N = + 15V IAII Inputs)
V 1N = 0 ,IAII Inputs)
NOTES:
1. Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
2. V1N = input voltage to perform proper function,
DG300A-303A. DG381A-390A: V1N - For logic "'" =4 V. for logic "0" =O_BV
DG304A-307A: VtN-For logic "'''=11 V. for logiC "O"=3_5V
3. "OFF" isolation=20 log VsIV o • Vs = input to OFF switch. Vo = Output
4· Signals on Sx. Ox or 1NX exceeding V + or V - will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
3·88
Siliconix
DG381A ICMJ·C
DG384A ICMJ·A
DG300A ICMJ·A
DG301A ICMJ·B
DG302A ICMJ·A
DG303A ICMJ·C
DG387A ICMJ·B
DG390A ICMJ-C
DG304A ICMJ-D
DG305A ICMJ-E
DG306A ICMJ·D
DG307A ICMJ-F
CI
CHARGE INJECTION TEST CIRCUIT
Q
w
e
e
AVO
J>
I
CI
Q
w
e
;:
aVo ~ MEASURED VOLTAGE ERROR DUE TO CHARGE INJECTION
THE ERROR VOLTAGE IN COULOMBS IS e.Q '" CL x
c.vo·
CI
..
Q
w
SCHEMATIC OF TYPICAL SWITCH
C»
J>
v+O-----,_---1----~----1_------_t----~----,_--~~--__,
I
CI
CONTROL
Q
w
INo-J\!I."""'~
00
e
J>
GNDo--+-------4----~
V-o--4-----------------+------~~--~----~--_+------~
~ ~,--------------~------------~ ~--------~--------~
LOGIC INTERFACE AND SWITCH DRIVERS
INPUT PROTECTION
ANALOG SWITCH
TEST CIRCUITS
BREAK-BE FORE-MAKE TIME TEST CIRCUIT SPDT
(DG301A, DG303A, DG305A, DG307A, DG384A, DG390A)
J
LOGIC
INPUT
LOGIC "1" = SWITCH ON
r---------ccV-IN~H
IDG300·303
50%
\
.
DG38'·DG390
OG304·307
4
--
+15 V
V'
V
J>
SWITCH
15 V
~
OUTPUT
OV
o-+_-------<~~;_~----_t------~--oVo,
VS'----~~======~----
o-+-------<~i~+_~~--~-t----;_-oV02
a
o
co
ell
SWITCH
33 pF
VOl •
OUTPUT 0 V - - " ' - ' - - - - '
..
(It
VS2 ----+------+---
~
-.
-15V
SWITCH
OUTPUT
ft
:s-
CD
III
SWITCHING TIME TEST CIRCUITS (DG300A-307A, DG381A-390A)
LOGIC
INPUT
~;~ ~~~:
+15V
ov
VS--I---;--;:::::.=::I=~-o~i~~~ ov-----+---'
DG300·303
OG304·307
DG381·0G390
4V
15 V
-INVERTED LOGIC FOR OG3Bl
Siliconix
3-89
Quad Monolithic SPST
CMOS Analog Switch
designed for...
•
•
•
•
•
•
•
•
H
Siliconix
Portable, Battery Instrumentation
Automotive Applications
Computer Peripherals
Communication Systems
Hgh Speed Multiplexing
Low Leakage Switching
Sample and Hold
Data Acquisition Systems
BENEFITS
•
•
High Speed Switching with
Break-Before-Make
o ton = 130 nsec Typical
o toft = 90 nsec Typical
Single Supply Operation
o +5 V to +30 V
•
CMOS Compatible (positive logic)
•
Wide Signal Range ±15 V
•
Low Standby Power
o <30 tLWatt Typical
•
Minimizes Signal Error
o ros 80 n Typical
100 pA Typical
o I O(off)
•
<
<
Environmentally Rugged
o Latchproof CMOS Process
DESCRIPTION
The DG30B is a monolithic quad single-pole single-throw analog switch fabricated in complementary MOS technology.
In the ON condition, each switch will conduct current in either direction and in the OFF condition each switch will block
voltages up to 30 volts peak to peak. The ON-OFF State of each switch is controlled by a driver. With CMOS logic '1' at
the input the switch will be ON, with logic '0' at the input the switch will be OFF.
PIN CONFIGURATION
Dual-In-Line Package
13
IN.
~-=";""""";":::..I'_
V+ (SUBSTRATE)
ORDER NUMBER:
DG30BCJ
SEE PACKAGE 7
IN3
TOP VIEW
LOGIC
SWITCH
0
OFF
ON
1
SWITCH CLOSEO FOR LOGIC "1" INPUT (POSITIVE LOGIC)
3-90
Siliconix
ell
Q
w
ABSOLUTE MAXIMUM RATING
o
•
Storage Temperature (C Suffix) ........ -65 to + 125°C
Power Dissipation (Package)*
16 Pin Plastic DIP ........................................ 470 mW
VIN to Ground .......................... V++18V,V+-36V
VSorVD················································ ........ V+toVV+to Ground ................................................... +36 V
V+ to V- ............................................................ +36 V
Current, Any Terminal (Except S or D) ......... 30 mA
Current, S or D, Continuous ........................... 20 mA
Pulsed 1 ms 10% Duty Cycle .................... 100mA
Operating Temperature (C Suffix)
o to +70°C
.Device mounted with all leads soldered or welded
to PC board.
--Derate 6.5 mWI"C above 25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
(Note 11
TYP
25°C
CHARACTERISTIC
Minimum Analog
VANALOG Signal Handling
Capability
1
2
3
4
5
6
7
8
9
I
N
P
U
T
10
11
12
V
Switch ON IS = 10 mA
100
100
5
-5
125
125
100
-100
.n
V D - 10 V,IS - -1 mA
VD 10 V,1S-1 mA
Vs = +14V, VD = -14V
Vs = -14 V, VD = +14 V
5
100
nA
-0.1
0.1
-0.1
-5
5
-5
-100
200
-200
Vs = -14V, VD = +14 V
Vs = +14V VD = -14 V
VD - Vs - + 14 V
V D - Vs - - 14 V
Input Current
Input Voltage High
0.001
1
Input Current
Input Voltage Low
-0.001
-1
130
90
150
ID(offl
Drain OFF
Leakage Current
ID(on)
Drain ON
Leakage Current
ton
toft
13
70
60
0.1
15
16
17
S
U
P
19
Turn-ON Time
Turn-OFF Time
Source OFF
200
ns
dB
VIN = 0 V, RL = 1K .n, CL = 3 pF
Vs = 70m V rms, f = 500 kHz
p.A
VIN = 15 V or 0 V
Vo = Output
IVsl
Vs = Input to OFF Switch
-
v-=
0"
~~
"
~
c
~~100
~!
...
I
~o
A V'
"
15
100
1K
RL - IkO
-15
=
·10
~
ffi
~
+15V, V- '" -15V"-
·5
0
5
10
Va-DRAIN VOLTAGE (VOLTS)
10
is
:~:: nJ~'f: :i~~-
0
5
~:~~"C
~
.
B
65
Vo - DRAIN VOLTAGE !VOLTSI
Log.: Input
15V
z
f?t:l
TA= 12S'C
V' _
•..
01\
I
~iii
0'
~§
0'
CI,lQ
0
Sl~gle
100
V' = +15V
~iii
·5
VI
Device Power Dissipation
vs Switching Frequency
200
...,
:::r
ICMO
IVol
'os lanl vs Vo and
Power Supply Voltage
Temperature
V' = +15V
-15V
·15
ft
CD
3. OFF Isolation = 20 109,0
ros Ion I vs Vo and
0
~
-100
TYPICAL CHARACTERISTICS
~i5
.-.
CIt
100
0.001
for logic '0' = 3.SV
TA- 2S'C
o
CD
VD=VS=OV,V IN=15 V
1. Typical values are for DESIGN AID ONLY, not guaranteed
and not subject to production testing.
2. V1N = Input Voltage to perform proper function
~~
D
V D = 0 V, VIN = 0 V
pF
NOTES:
~~1)()
)II
:s
Vs = 0 V, VIN = 0 V
78
Negative Supply
-0.001
Current
III
See Switching Time Test Circuit
22
1-
roo
(Note 2)
VIN = 0 V
8
1+
= , tV,
(Note 2)
VIN = 15 V
8
Positive Supply
Current
for logic '"
(Note 2)
/LA
OFF Isolation (Note 3)
18
100
100
-0.1
0.1
D CS(offl
Y
N CDloff) Drain OFF
Capacitance
A
M
Channel ON
CD(on)+
I
C CS(on) Capacitance
14
70°C
±15
Source OFF
Leakage Current
IINL
25°C
TEST CONDITIONS
V+ = +15 V
V- = -15 V, Gnd = 0 V
UNIT
±15
IS (off)
IINH
O°C
±15
rDS(ON) Drain S?urce
ON ReSistance
S
W
I
T
C
H
MAX LIMITS
C SUFFIX
15
1
~
01
1
II
101C 100K 1M
LOGIC SWITCHING fREQUENCY (Hl)
50"4 OUTY CYCLE
Siliconix
3-91
Typical delay, rise, fall. settling times, and
switching transients in this circuit.
'SWITCHING TIME TEST CIRCUIT
·15V
V·
If R GEN • RL or C L is increased. there will be
proportional Increases in rise andlor fall RC
times. Applying VGEN to 0 rather than S
results in much greater spikes.
TYPICAL CHARACTERISTICS continued
100
OFF-Isolation, Insertion Loss
vs Frequency
OFF
~lINl!I
111tl~'
~ 80
z
~
II OFIIII
RL
~
I
I
,..... r-r
I 1111
"L" '000
I
I
LOGIC INPUT
INSERTION
lkQ
LOSS
60
~
IS(oll) or 10(011) vs Temperature"
_LIII
II 111111 IIIII
"L
250
10
o "'
I
V .... 15V, V
CLOAD ~ JpF
..
'r1'lIIIIlIMS I II
10'
r -
FREOUENCY 1Hz)
as
105
T - TEMPERATURE
NOTE
r-..
VGEN '" 10V
125
rei
·5
J
Output ON Capacitance
vs Drain Voltage
10(on) vs Temperature"
1
.. see
I
J
'" -15V
J-.....
VGEN=5V
~ '" ,---,--,--r---,---,--r---,----,
10
i!! ·5
~
a
i
~
0.1
!,
w
~
~
5
IoU
g0
301--+-+-+-+-+
g
201--.......,=1--+-_+_1---+----I
I
VGEN = OV
-s
5 0
~
5 -5
-
\
VGEN
I
<:
-5V
~
10.01
-
25
45
85
105
Vo -
DRAIN VOLTAGE (VOLTS)
-15
Switching Time
vs Temperature
Input Capacitance vs
Input Voltage
~ e-
I
t
-5
126
T -TEMPERATURE I'C)
V
VGEN = -IOV
0-4
0-8
t-TIME
12
1-6
(~81
-Note: the turn-off time is primarilv limited here by
the RC tIme constant f100ns) of the load.
180 ~::~a~
'JINH = +15V
160
140
'I(NL"
ov
+--+--++-+-1--1
I--+-+--+f--+;'~"""+""-;-"'--t-I
'20I---I"'''F-+---1--1--1I--+-+-I
~0r-i:j:=i~~~'o~.F-+__r_i
;§
I.
I--+-+_+-+-+-----'I---+r---j
.01---+--+-+---1-1--1--+-+-1
"1--+-+-+---1-1--1--+-+-1
4Of--l--t-+-t--t--t---t-iH
IDI--+-+--t--t--t-+--t-+--i
OL-L-L-~~~~~-L~
8
VIN -
10
121ft
16
20301005060
t)
TEMPERATURE
7080
("<:)
Switching Time
vs Negative Supply Voltage
200 r---,--,----r-,---r-,
y' = 1SV
v - -15V
I---+--+-+-+~N~ !S;,
1600
0
T-
Switching Time
vs Positive Supply Voltage
2000
-10
INPUT VOLTAGE (VOLTS)
p..o;::-l--+-+--+~N~ !5"f,sv
VtNl = 0
160
1-----1t---..._""I-',,'"i;::-I---t_"_NL_-t-.--j
"The net leakage into the source or
drain is the n-channel leakage minus
the p-channel leakage. This difference can be positive, negative, or
zero depending on the analog voltage and temperature, and will vary
greatly from unit to unit.
Input Switching Threshold
vs Postitive Supply Voltage
v-
=~'5V
TA, = 25"(;
f---t--t-+-+----If---i
120
~
I
........ 1'"-..
1200
f--If---f--+-+--t-r----I
~
.4/:
800 f---t--t1f-+-+----If---i
~-
400 I-+-+~
\-t--il-+-i
-
toff'
40~~~~
10
V' -
3-92
POSITIVE SUPPLIf {VOL TSI
15
o
-5
v _
_
_L_~_4_~
-10
NEGATIVE SUPPLY {VOLTS I
Siliconix
-15
10
V' -
POSITIVE SUPPLY (VOLTSI
PARTIAL SCHEMATIC OF TYPICAL SWITCH
V+
~--~--~--~--~----~--4r----~---4~--~----'
s
GNO o____________
~--~'_--...J
a
V-
Switch closed for Logic '" Input (VINH)
Single Supply Operation
The DG308 will switch positive analog signals while using a single positive supply. This will allow use in many applications where only
one supply is available. The performance trade-offs while using single supplies are: 11 Increased rOSION); 21 slower switching speed.
Typical curves for aid in designing with single supplies are supplied in the Figures below. As stated in the absolute maximum ratings
section of the data sheet, the analog voltage should not go above or below the supply voltages which in single operation are V+ and
o volts.
Single Supply Range: (V- and GND Tied Togetherl V+: +5 V to +25 V
Analog Signal Range: V - .. V ANALOG" V+
rOS(onl vs Analog and
Positive Supply Voltage
with V- = OV
Switching Time vs V+
Input Switching Threshold
vs Postitive Supply Voltage
- Positive Supply Voltage
v- - OV
TA
~
v- u10v
25 C
TA ~ 2S·C
iii
~ 2
e_ 5
o
z
\
11
VA -
ANALOG VOLTAGE (VOLTS)
~g
l1li
14
'--I---
-
10
v+
-
./
V;y
V- ~'
~
~r-
~I'~'~~~-r-+-~
l
:::s
-
~~ 2t--~-~~-r-+--t___1
\
toll
12
~~
~g4
'0"
i
10
+-t--t__--t/-7l
~g 6r-~--+--r-+_~~,' ~/
V' '" +12V
POSITIVE SUPPLY (VOL IS)
II
o
10
'5
V· -
CD
IS
POSITIVE SUPPLY (VOLTS)
en
.."-.
~
::r
CD
fit
Siliconix
3-93
Quad Monolithic SPST
CMOS Analog Switch
designed for ...
•
H
Siliconix
BENEFITS
•
Environmentally Rugged
o 40 V Power Supply Max Rating
o Static Protected Logic Inputs
o Latchproof
•
Minimizes System Power Requirements
o Operates Off Single Supply When VTied to GND
o Low Quiescent Power <30 I1W Typ
•
Fast ton < 200 ns
toff < 150 ns
•
Minimizes Signal Error
o rDS(ON) < 100n
o ID(OFF)<5nA
o Full Rail-to-Rail Analog Signal Range
Portable, Battery Instrumentation
•
Computer Peripherals
•
Communication Systems
•
High Speed Multiplexing
•
Sample and Hold
•
Single or Dual Supply Systems
•
Easily Interfaced
o CMOS Logic Compatible
o Available in Normally Open or Normally
Closed
• DG201A/DG202 are TTL Input Pin-forPin Compatible
DESCRIPTION:
The DG309 designed on the Siliconix PLUS·40 CMOS process provides solid state switch action with 100 ohms contact
(ON) resistance and very high OFF resistance. True bidirectional switch action occurs over the full analog signal range of
±15 V, with Break·Before·Make operation to prevent momentary shorting of signal inputs.
FUNCTIONAL DIAGRAM (typical switch)
PIN CONFIGURATION
Dual·1 n·Line Package
V+
r
-~
LD'
Sx
S.
'3
D.
03
IN X
LOGIC
INTERFACE
AND
PROTECTION GND
IN3
ORDER NUMBER:
DG309CJ
See Package 8
SWITCHES ARE SHOWN IN THE LOGIC "1" INPUT STATE
3·94
Siliconix
LEV·EL
SHIFTER
V-
SWITCH
CONTACT
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
(C Suffix) ............... 0 to +70°C
Storage Temperature
(C Suffix) " ...........-65 to +125°C
Power Dissipation (Package)'
16 Pin Plastic DIP" .......... 470 mW
Voltages referenced to VV+ ...............•.......... 44 V
GND ......................... 25 V
Digital inputs 4, VS, VD . -2 V to (V+ +2 V) or
20 mA, whichever occurs first.
Current, Any Terminal
(Except S or D) ............... 30 mA
Current, S or 0, Continuous ........ 20 mA
Pulsed 1 ms 10% Duty Cycle ..... 100 mA
'Device mounted with all leads soldered or
welded to PC board.
"Derate 6.5 mWtC above 25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25'C. Lots are sample tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
C SUFFIX
(Note II
TYP
CHARACTERISTIC
25'C
Minimum Analog
VANALOGSignal Handling
Capability
1
2
3
4
5
6
7
__
8_
9
S
W
I
T
C
H
I
N
P
U
T
10
11
±15
V
125
125
100
-100
n
-0.1
100
100
5
-5
70
60
0.1
rDS(ON) Drain S?urce
ON Resistance
Source OFF
Leakage Current
ID(off)
Drain OFF
Leakage Current
0.1
5
100
-0.1
-5
'D(on)
Drain ON
Leakage Current
0.1
-0.1
5
-5
-100
200
-200
Input Current
Input Voltage High
0.001
1
IINH
IINL
Input Current
Input Voltage Low
-0.001
-1
130
90
200
toff
CS(off)
Source OFF
8
CD(off)
Drain OFF
Capacitance
8
CD(on)+ Channel ON
CS(on) Capacitance
22
OFF Isolation (Note 3)
78
15
16
17
18
S
U
P
19
Vs = -14V, VD = +14V
(Note 2)
(Note 2)
Vs = -14V, Vo = +14 V
nA
Vs = +14V Vo = -14 Ii
V D - Vs = + 14 V
V D = Vs = - 14 Ii
(Note 2)
VIN = 15 V
ns
lEI
See Switching Time Test Circuit
J>
Vs = 0 V, VIN =15V
:s
-
Q
VD = 0 V, VIN =15 V
pF
o
ca
VD=VS=OV,VIN=OV
Positive Supply
Current
0.001
100
1-
Negative Supply
-0.001
Current
-100
V 1N = Input Voltage to perform proper function
for logic '" = l1V, for logic '0' = 3.SV
VIN = 0 V
150
1+
NOTES:
I. Typical values are for DESIGN AID ONLY, not guaranteed
and not subject to production testing.
2.
VD - 10 V,IS - -1 mA
VD = -10 V,lS = 1 mA
Vs = +14 V, VD = -14 V
",A
13
Y
100
100
IS (off)
Turn-ON Time
Turn-OFF Time
0
70'C
±15
ton
N
A
M
I
C
25'C
±15
12
14
O'C
TEST CONDITIONS
V+ = +15 V
V- = -15 V, Gnd = 0 V
UNIT
dB
V,N =15V, RL = lK n, CL = 3 pF
Vs = 70m V rms, f = 500 kHz
CIt
/-LA
VIN = 15 V or 0 V
ft
IVDI
Vo
IV51
Vs == Input to OFF Switch
3. OFF Isolation = 20 10910 -
4. Signals on
...--~
:r
leMF·B
== Output
Sx. Ox
or 1NX exceeding V+ or V- will be clamped by
internal diodes. limit forward diode current to maximum current
ratings.
SWITCHING TIME TEST CIRCUIT
L(x;(
LOG(INPUT
ir<20ns
I, < 2On5
F9o;:--
SWITC~_V
OUTPUT
V'Nl = OV
'on
T
V·
SWITCH ON
~
SWITCH
INPUT
V'NH=1SV
~1·.
50%
v;:;Vs=3Y
~SO%
t~~
S
rIN
Siliconix
,
fD--t>--~
tND
v-Lv
SWITCH
D
OUTPUT
R~l ~CL Va
IKn~ IlSPf
.,
Vo=Vs-RL + tOS(onl
3-95
m
Monolithic General
Purpose CMOS
Analog Switches
H
SilicDnix
designed for . . .
BENEFITS
•
Programmable Gain
Amplifiers
•
Environmentally Rugged
o 44V Power Supply Rating
o Static Protected Logic Inputs
o Latchproof
•
Analog Multiplexing
•
•
Servo Control Switching
Easily Interfaced
o TTL and CMOS Compatible without
Pull Up Resistors
•
Sampled Data Systems
•
•
Synchronous Demodulators
Reduces External Component Requirements
o Full Rail to Rail Analog Signal Range
o No Diode Protection Required Between
VL and V+ for Power Supply Sequencing
• Pin for Pin Compatible with
o IH5040 Family
o HI5040 Family
DESCRIPTION
The DG5040 through DG4045 series designed on the Siliconix PLUS-40 CMOS process provides solid state switch action
with 50 ohms contact resistance and very high OFF resistance. True switch action takes place over the full analog signal
range of ±15 volts, with Break-Before-Make operation to prevent momentary shorting of signal inputs_
FUNCTIONAL DESCRIPTION
PART NUMBER
DG5040
DG5041
DG5042
DG5043
DG5044
DG5045
3-96
FUNCTIONAL DIAGRAM (typical channel)
TYPE
Dual
Dual
Dual
SPST
SPST
SPDT
SPDT
DPST
DPST
¥
INXo--
r
~
'">-- ~':'Rr-L~
LEVEL
~
LOGIC
INTERFACE
AND
C)
PROTECTION GND
SilicDnix
sx
V-
SWITCH
CONTACT
CII
Q
PIN CONFIGURATIONS
VI
ALL SWITCHES SHOWN IN
THE LOGIC "1"
SWITCH STATE
CERDIP (KI OR
PLASTIC (JI
SEE PACKAGE 8 or 10
FLAT PACK (LI
SEE PACKAGE 5
Z
o
METAL CAN (AI
SEE PACKAGE 2
CII
Q
VI
SPST
DG5040
Z
VI
CIt
.,-.
m
CD
LOGIC
SWITCH
0
OFF
1
ON
V-
GND
GND
ORDER
NUMBER:
Y-
DG5040AK or DG5040CK
or DG5040CJ
DG5040AL
DUALSPST
DG5041
v'
VL
VL
v'
VL
5,
D,
14
,
-"
IN,
LOGIC
SWITCH
0
OFF
1
ON
IN,
D,
5,
GND
5,
"
0,
,
IN,
-~
IN,
IN,
-",,
,
I',
So
D,
III
:I>
So
:I
Q
-
VGND
ORDER
NUMBER:
5,
V-
o
ca
DG5041AK or DG5041CK
or DG5041CJ
DG5041AL
~
:e......
DG5041AA
ft
::s-
SPDT
DG5042
VL
VL
,.
5,
LOGIC
SW 1
0
OFF
ON
ON
OFF
SW 2
0,
0,
So
5,
CD
1ft
v'
"
0,
0,
So
IN
IN
IN
GND
OND
GND
ORDER
NUMBER:
So
DG5042AL
DG5042AK or DG5042CK
or DG5042CJ
Siliconix
v-
V-
DG5042AA
3-97
.-..
;
J:
PIN CONFIGURATIONS Continued
1ft
ALL SWITCHES SHOWN IN
THE LOGIC "1"
SWITCH STATE
~
DUALSPDT
DG5043
I
a
8
VL
VL
SW3
SW4
LOGIC
0
OFF
ON
ON
OFF
V"
V"
0,
0,
"
SWI
SW2
"
IN,
0,
0,
IN,
IN,
IN,
.
0,
0,
s,
..
0,
s,
D•
v-
GND
v-
OND
ORDER
NUMBER:
DG5043AK or DG5043CK
or DG5043CJ
DG5043AL
DPST
DG5044
..
VL
,.
I,
LOGIC
SWITCH
0
OFF
1
ON
..
D,
DZ
I,
.
"
VL
D,
"
0,
"
ORDER
NUMBER:
..
V-
DG5044AK or DG5044CK
or DG5044CJ
..
VL
VL
.
. .
v'
.
D,
D,
,,
-"
IN,
0
OFF
1
ON
...
I.,
-1
INZ
Sz
D2
D.
OND
b"
y-
OND
ORDER
NUMBER:
DG5045AL
,.
D.
v-
DG5045AK or DG5045CK
or DG5045CJ
Siliconix
V-
y-
(DG185 EQUIVALENT)
SWITCH
0,
GND
OND
DG5044AL
DUAL DPST
DG5045
LOGIC
V"
IN
IN
OND
3·98
METAL CAN (A)
SEE PACKAGE 2
(DG191 EQUIVALENT)
o
I1ft
CERDIP (K) OR
PLASTIC (J)
SEE PACKAGE 8 or 10
FLAT PACK (L)
SEE PACKAGE 5
DG5044AA
g
ABSOLUTE MAXIMUM RATINGS (T A = 25° unless otherwise noted)
Voltages referenced to VV+ ... ... . . " .
. . . .. . . . . . . . . . . . . 44V
VL·········· .. · . .. . .. (GND -0.3 V) to 44 V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital inputs 5, VS, VD..... ... . . -2 V to (V+ +2 V) or
30 mA, whichever occurs first.
Current, Any Terminal Except S or D . . . . . . . . . . 30 mA
Continuous Current, S or D. . . . . . . . . ...... ..30mA
Peak Current, S or D (pulsed at 1 msec,
10% duty cycle max) . . . . . . . . . . . .. . .... 100mA
Storage Temperatu re (A Suffix)
-65 to 150°C
(C Suffix)
-65 to 125°C
Operating Temperature (A Suffix)
(C Suffix)
Power Dissipation *
Metal Can and Plastic DIP" . ... . .
16 Pin Dip···· ......... .. , . . . . .
Flat Pak····· . . . . . . . . . . . . . . .... .
. ..
-55 to 125°C
a to 70°C
. ... 450 mW
.... 900mW
.... 900 mW
VI
Io
a
Q
VI
IVI
"All leads welded or soldered to PC board.
""Derate 6 mWtC above 7SoC.
""""Derate 12 mW/oC above 75°C.
"""""Derate 10 mWtC above 7SoC.
..-.
CIt
CD
m
ELECTRICAL CHARACTERISTICS All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC
parameters and high and low temperature limits to assure conformance with specifications.
Max Limits
Characteristics
A Suffix
_55°C
1
VANALOG
-
-+3
-45
-+
-
I
T
C
H
7
-+-
10
-
15
17
l-
20
S
U
p
p
l-
V
22
23
L
1
1
100
-100
100
1
-1
100
-100
2
-2
200
-200
2
-2
200
-200
.,
.1
.,
.,
"
4
Drain ON
Leakage Current
Input Current,
Input Voltage High
Input Current.
Input Voltage Low
50
50
.1
.1
Turn"()N Time
1000
1200
Turn-OFF Time
500
700
Q
Charge Injection
Cs(olll
Source OFF
Capacitance
15 Typical
Drain OFF
Capacitance
17 Typical
Channel ON
75 Typical
CCRR
Interchannel
Crosstalk
Isolation
89 Typical
Positive Supply Current
1_3
Negative Supply Current
IL3
Logic Supply Current
IGNO
Ground Current
Vo = 10V. I = -10 rnA
Vo = 10V. I, = -10 rnA
V, = 14V. Vo = -14V
V, - 14V, Vo = 14V
nA
Noto 1
V, = -14V, Vo = 14V
V, = 14V, Vo = -14V
V, = Vo = 14V
V, = Vo - 14V
III
VINH = 2.0V
"A
VINL = 0.8V
n,
V, = .10V, RL
CL = 35 pF
= lKn,
rnV
CL = 10,000 pF, RGEN
VGEN = OV
Note 2
= on,
300
300
-300 -300
300
300
-300 -300
300
pF
300
JOO
300
-300
-300
300
300
300
-300 -300
-300
-300
dB
ZL = 75n
V, = 2 Vpp,
1 = 1 MHz
"A
VIN
2: See Switching Time Test Circuit.
:::s-
1ft
=OV or 2.4V
3: Limits of these paramaters are tested 100% at 25 "C and 125"C for "/883"
devices.
4: For "/883" devices these parameters are 100% tested at 25"C.
Ox or INX exceeding V+ or V- will be clamped by internal diodes.
Limit forward diode current to maximum current ratings.
5: Signals on SX,
Siliconix
ft
CD
ICMK-A, B
For Logic "'" - VINH = 2.0 V
For Logic "0" - VINL ::: 0.8 V
-.
~
V, = Vo = OV,
1 = 1 MHz
NOTES:
1: VIN ::: Input voltage to perform proper function.
-
ca
Note 1
-300 -JOO
300
J>
:::s
a
o
CIt
45 Typical
OFF Isolation
1+ 3
.,
3 Typical
OIRR
19
l21
1-
n
-100
capacitance
18
75
75
1
N
A
M Co (off)
I
C
Co (on I + Cs(onl
16
100
100
50
50
-1
toff4
V
75
75
V
Drain OFF
Leakage Current
ton
0
50
VL • 5V, GND ·OV
±15
10(0111 3
IINL3
14
50
50
70"C
±15
1
1
T
12
50
Handling Capability
O"C
Source OFF
Leakage Current
IINH 3
-~
±15
15(0111 3
I
N
P
U
11
±15
Drain Source
ON Resistance
10(on)3
9
125°C
Tnt Conditions
V+ = 15V, V- • -15V
Unit
rOS(onl 3
S
W
25°C
Min. Analog Signal
C Suffix
25°C
3-99
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Va is' the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC
INPUT (l N l)
3V
t,<20ns
t, <20 ns
OV
SWITCH
INPUT
Vs
+15V
+5V
SWITCH
INPUT 51
SWITCH
OUTPUT
Vs = ±10 V
Vo
-i--::k:======;t"-;;-;
CL
lKn
SWITCH
OUTPUT (Vo)--+_..1
135
PF
":"
V-
Note: Logic input waveform is inverted for switches
that have the opposite logic sense cont,ol.
V
- V
(REPEAT TEST FOR IN2)
RL
0- 5 RL + 'OS (on)
CHARGE INJECTION TEST CIRCUIT
RGEN
Vo
Sx
J
VGEN
INX
~.
ON
~
0OFFFF
'------------'
ON
AVO ~ measured voltage error due to charge injection.
The error voltage in coulombs is.6.Q = CL x AVO.
SCHEMATIC DIAGRAM (typical channel)
v+
r--~,",",-~,",",--+-o()
Sx
LOGIC
TRIP·
POINT
REF
GNO O-~---..I
INX
o--_......w'v---..--'
~--~-----6--------oox
V-
3·100
Siliconix
Monolithic SPST MOS Switch
with Driver
designed for . . .
H
Siliconix
BENEFITS
•
• Switching Analog Signals such as
Reference Signals
Reduces External Component Requirements
o Internal Zener Diodes Protect All MOS
Gates
• Easily Interfaced
o TTL and DTL Integrated Logic
DESCRIPTION
The SI3002 contains two P-channel MOS field-effect transistors designed to function as single-pole double-throw electronic
switches. A level-shifting driver enables a low-level input (0.8 to 2 V) to control the ON-OFF state of the switches. In the
ON state, each switch will conduct current equally well in either direction. In the OFF state the switches will block voltages
up to 20 V peak-to-peak. With logic "0" at the driver input, a common drain (0) is connected through an ON switch to
source (Sl). With logic "1" at the input, "0" is connected to S2. Switch action is make-before-break.
PIN CONFIGURATIONS
Metal Can Package
Dual-In-Line Package
v+
-:.
~
VR
a
o
ca
TOP VIEW
ORDER NUMBER: Si3002AA
SEE PACKAGE 2
ORDER NUMBER: Si3002BP
SEE PACKAGE 11
."-.
LOGIC STATES ARE FOR LOGIC "1" INPUT
(POSITIVE LOGIC)
(It
~
::r
SCHEMATIC DIAGRAM
CD
r-----------------~~----------~~----~~V+
CIt
5,
IN
D
~--~~~
________
_+--------------~
Siliconix
______
~V-
3-101
ABSOLUTE MAXIMUM RATINGS
V+to V- .... .
V+ to Vs or VD ..
V+ to VR or VIN
VD to V-. .. .
Vsto V-. · .
VD to VS. · .
VIN to VR · .
Current (Any Terminal)
Storage Temperature ..
.. . · . . .
.. . · .
. . · . ..
.. ·.
. . .. · .
.. ·.
. . .. .
·.
.. .
·.
.. . .. . · .
.
36 V
25 V
12 V
36 V
36 V
±25 V
.. . ±6V
... 30mA
-65 to 150°C
Operating Temperature
(A Suffix) .
(8 Suffix) .
. -55 to 125°C
-20 to 85°C
Power Dissipation*
Metal Can** ..... ................... 450mW
14 Pin DIP***
825mW
*Device mounted with all leads soldered or welded to PC
board .
**Derate 6 mW/oC above 75°C.
H*Derate 11 mwfc above 75°C .
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
ASUFFIX
2SoC
-5SoC
12SOC
1
I~
I~
Drain-Source
S rOSlan)
W
ON ReSistance
I-I
4 T ISloffl
C
I-H
5
10(on) + ISlon}
2SOC
100
150
100
100
150
150
150
250
150
150
250
400
400
500
400
400
500
-1
-1000
-5
-100
Leakage Current
-2000
-10
-200
-O.S
-1.0
-0.8
-0.8
mA
Input Voltage Low
Input Current.
VIN :: 0 (Swl ON)
Input Voltage High
0.1
0.1
10
0.1
0.1
10
"A
VIN ::: 5.5 V (Sw2 ON)
"'
See SWitching Time Test Circuit
toft
Turn·OFF Time
1.5
1.5
10
CS(off)
Source OFF
Capacitance
11
1+
Positive Supply Current
1-
Negative Supply Current
6 Typ*
-3
-3
-0.1
Positive Supply Current
3
3.5
Negative Supply Current
-3
-3
-1.5
-1.5
IR
Reference Supply
Current
16
0.8 V (Swl0N)
2.0 V (Sw2 ON)
I
VS'" 0
f= 1 MHz
3.5
-0.1
1-
r
=
VO=-10V,IS=O
6 Typ*
3
Reference Supply
Current
13 U IR
I- P
1+
14
l-,sv
=
VS"'-10V,VD= lOV
-2
1.0
1-
VINL
VINH
I
VO--l0V
-0.8
1.0
1--;:;
1--'- s
lis = -1 mA
a
Vo -
-1.0
Leakage Current
Input CUrrent,
Turn·ON Time
I~~
I
Vo -10V
n
nA
Channel ON
8
ton
I-D
TEST CONDITIONS, UNLESS NOTED:
V+= 10V, V-= -20V. VR =0
UNIT
8SoC
100
Source OFF
I
6 N IINL
I-P
7 U IINH
T
B SUFFIX
_20o e
mA
VIN
=
0
mA
VIN
=
5V
"Typical values are for DESIGN AID ONLY. not guaranteed and not subject to production testing.
CMBC
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
LOGIC
INPUT
t r < 10ns
t, < 10ns
X
O 9VO
.
~on(S21-1
toff (51)
S2
8t
-,oIf IS
LOGIC
:-:..1
,1-r
h , vo
ton (52)
Siliconix
I
IN
Rl
1Kn
.J
INPUT~
SWITCH
OUTPUT
a
~
ton. Vs '" -10 V
toff. Vs '" +10V [ 82
SWITCH
INPUT
SWlTCH
OUTPUT
3-102
v+
8,
0--'
0
y
SWITCH
INPUT
3V
1.5V
le
Vo
1
l
350
AVR
.~.v-
-20 V
'
~'-=-
RL
VO=VS--RL + rOS(on}
TYPICAL CHARACTERISTICS
Supply Current
vs Temperature
rDS(on) vs VD
and Temperature
in
e"w
x
400
u
350
~
300
13
a:
z
250
u
w
200
"E)z
150
z
3
's-
,!+
~
,
0
~
2
E.
50
9
"
"u
.!.
t";;: ~ r-;.25·CI'.....
'H+
1
r--l.. :-t-f-- 55°C
r- -
....
~
~ 1- ,25,C
0
-10 -8 -6 -4 -2
'RH
0
2
4
6
8
10
-60 -40 -20 0
Vo - DRAIN VOLTAGE (VOLlSI
800
~
:l:
taff+'TOV 1N
700
200
-- -r
100
r-- - ton
>= 500
~ 400
300
,;'
~
.....-
~
~
w
a:
B SUFFIX
10
20 40 60
25
>-
~
a: 200
u
>~
"
c;
\5'C\
125'C \
r
-~
0
0
~O
-
............ 1\\"55'C
100
9,
1\
\\
1"- [\.\
1
105
85
125
c;
,z
9
>-
0
LOGIC INPUT
-2
8
z
-20
~
-30
......~
0
-50
,
-60
~-'
-70
,
VGEN-+5V
-2
~
::I
Q
6
4
~'
,
RL III lK n
2
~0
V
~
w
R t -lOOn
,
I
>'
111111111
-90
'"~
IIII
0
0.1
1
10
f - FREQUENCY (MHz)
V 1N - LOGIC INPUT VOLTAGE (VOLTS)
100
0
-2
-4
0
ca
I
VGEN=+1V
(It
6
2
>
I
-4
~
0
, i
-2
>
"0,
........
0
4
>-
111111111
-100
0.01
3
\.
0
,
~ -80
-
2
-40
--
6
2
o r-T'''''I1T1r"""T''Tnrnr-r-TTnmr-rrmnn
~ -10
0
~
u
4
2
4
V+=+10V
V-=-20V
"-
65
6
~
u
"OFF" Isolation vs RL
and Frequency
;--;;--;---r--~--~--,
~ ...........
45
8
>
T - TEMPERATURE I"C)
VIN vs liN
and Temperature
VR
A SUFFIX
O"~.
80 100 120 140
T - TEMPERATURE lOCI
.
"
>-
V
1
o
300
'""
0
V
E"
'"
_0
±10 V 1N
~
V
0
-~ffJ'0J'N;;... II
-60 -40 -20 0
~0
100
j
.A"
,;'f
I
600
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
1000~mm
I
~~:~PF I
900
60 80 100 120140
IS(off)
vs Temperature
I
V+=+lDV
V-=-20V
1000
20 40
T _ TEMPERATURE (OCI
Switching Time
vs Temperature
1100
-
'L - '"
'H
15
a:
a:
VR;ZO
~
>-
;; 100
v+=+tOV
V-"-20V
1 mA
0
Typical delay, rise, fall, settling times, and
switching transients in this circuit.
...~_.
I
I
!
"::r
CD
iV
I'
VGEN=OV
1ft
6
4
"OFF" Isolation Circuit
v-fv
V+=+10V
y
·""1
SOURCE
Z=50n
n
0
-2
VGEN--1 V
-4
/.
B
V'N
2
A
VL
2
0
-L...
500
VR~OV
"OFF" ISOLATION
~ 20 LOG
'"f
RL
/'
-2
-4
':'
IV1rJ
IVtl
-6
V GEN =-5V
-8
0
1
2
t-TIME
Siliconix
3
4
(~sl
3-103
H
Siliconix
Analog Multiplexers
III
Index
Page
Title
DG501 ...................................................................................... 4-1
DG503 ...................................................................................... 4-5
DG506/507 .................................................................................. 4-9
DG506A/507A ................................................................................ 4-12
DG508/509 .................................................................................. 4-17
DG508A/509A .........•.................•.................................................... 4-25
DG528/529 .................................................................................. 4-29
Si3705 ................................................ .' ...................................... 4-37
ANALOG MULTIPLEXERS
Analog
a••lc
Part
No.
Procell
Type
rDSlon)
Mo.
Voltage
Ranga
IVI
INo,a41
1m
(Nota 4)
IDlolfl
InAI
Transition
Time
,,,sec)
(Nota 21
Supply Voltage
IVI
I-I
logic Levels
IVI
VINL
VINH
Comments
1+1
Sup.
V+
Sup.
V-
-20
-20
Logic Pullup Resistors
10
EIGHT CHANNEL MUX+ ENABLE
DG501
PMOS
+510-5
150·240
DG503
PMOS
+1010 -10
150-800
DG5Q8A
CMOS
+1010 -15
400
DGm
CMOS
+1510 -15
400
1.5
0.6
3.5
1.5
0.6
8.5
10
1.0
0.8
2.4
15
-IS
Break-Before-Make
10
1.0
0.8
2.4
+15
-IS
Latches On Inputs
2.4
IS
-IS
Break-Sefore-Make
8
_ SIXTEEN CHANNEL MUX + ENABLE
DG506A
CMOS
+15to -15
400
10
1.0
0.8
FOUR CHANNEL DIFFERENTIAL MUX+ ENABLE
DG609A
CMOS
DGIi2!I
CMOS
+1510 -15
+1510 -15
400
10
1.0
0.8
2.4
IS
-IS
Sreak-Before-Make
400
10
1.0
0.8
2.4
IS
-IS
Latches On Inputs
2.4
+15
-15
Break-Before-Make
EIGHT CHANNEL DIFFERENTIAL MUX+ ENABLE
DG507A
CMOS
+15to -15
400
1.0
0.8
Switch Configurations
Multlple.er
Differential Multiplexer
Dln(_Urnl.~
INPUTS
'.
B-Channel
4·Channel
8·Channel
NOTES:
1. The devices shown in boldface are recommended parts for new designs.
2. The appropriate switching characteristic for mltttiplexers is trRANSITION. not tON' tOFF.
3. VREF'" 1.5 V is used when supply voltages < ± 15 V are used. Not needed when supply voltages of ± 15 ere used.
4. Analog voltage range is a function of supply voltages. Where a FETswitch is PMOS or CMOS, rOS is also a function of Supply Voltage and Analog Vohage. See Individual data sheets for more
detail. Values shown are for temperature suffix A.
5. Device normally operates with resistor to + 10 V.
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) to devices without resulting in
permanent damage. This is a stress rating only and not subject to production testing. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.
8-Channel Multiplex Switch
with Decode
designed for . . .
H
Siliconix
BENEFITS
•
• Multiplexing Signals
• Data Acquisition
Reduces Cross-Talk in Systems
o Break-Before-Make Switching
• Easily Interfaced
o Pull-Up Resistors on Inputs for TTL
Compatibility
DESCRIPTION
The DG501 is designed to function as a single-pole, a-position (plus OFF) electronic switch. The function is implemented
by using eight P-channel MOS field-effect transistors as analog switches. In the ON state, each switch will conduct current
equally well in either direction and in the OFF state each switch will block voltages up to 10 V peak-to-peak. The ON-OFF
state of each switch is controlled by drivers, which are in turn controlled by a 3-bit binary word plus an Enable-Inhibit
input. The truth table shown below indicates the binary word required to select anyone of the eight switch positions. Logic
input levels "L" and "H" correspond to positive logic "0" and "1". Assuming supply voltages of +5 V and -20 V, logic "L"
~ 0.6 V and logic "H" 2:: 3.5 V. "Pull-up" resistors are provided at each logic input to improve TTL compatibility. The rise
and fall times of the drivers are designed to provide break-before-make switch action.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
Dual-In-Line Package
SIGNAL INPUTS
-:..
~
1
ENo------t-r-r+-rt-t~~~~-rt-~
D
ORDER NUMBERS: DG501AP OR DG501BP
SEE PACKAGE 12
o
ca
DG501CJ
SEE PACKAGE 8
3
o
.-_.
~
*Soth V+ lines are internally connected, either one
or both may be used. V+ common to substrate.
c
"-
TRUTH TABLE
LOGIC INPUTS
Siliconix
CD
>C
CHANNEL
AD
A1
A2
En
'ON'
L
L
L
H
S,
S2
H
L
L
H
L
H
L
H
S3
H
H
L
H
84
L
L
H
H
S5
H
H
H
S6
L
H
L
H
H
H
H
S7
H
H
S8
X
X
X
L
OFF
CD
iii
4-1
ABSOLUTE MAXIMUM RATINGS
-0.3, +30 V
V+to V·. ·. ..
-0.3, +30 V
V+to VA, VEn
·. ·.
-0.3, +30 V
V+ to VD or VS.
· . ·.·.
±25 V
VD to VS····· ..
·.·. ·.
. . · . · . .. .
30V
VA, VEntoV- .. . .
VD or Vsto V- .. .
.. . · . . . .. . . . . . 30V
Current (Any Terminal) .. . · .
-20mA
. .. ..
Storage Temperature (A & 6 Suffix)
.. . -65 to 150°C
(C Suffix) ........ -65 to 125°C
Operating Temperature (A Suffix) ...
-55 to 125°C
(6 Suffix) ...
-20 to 85°C
(C Suffix) .......
oto 70°C
Power Dissipation'
16 Pin DIP"* ... . . . . . . .
..... 900mW
16 Pin Plastic DIP*~~ . . . ..
. ... 470mW
*Device mounted with all leads welded or soldered
to PC board .
**Derate 12 mWtC above 75°C
***Derate 6.5 mWtC above 25°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
OG501A
CHARACTERISTIC
DG501B/C
_2oo el
2Soc
TEST CONDITIONS. UNLESS NOTED:
v-" -20 V. V+ = 5 V. VEN::: 3.5 V
VAL =0.6 V. VAH::: 3.5 V
UNIT
-ss"'c
2Soc
125"'C
1
150
150
225
150
150
200
VD" 5 V
"2
200
200
300
200
200
300
Vo - a
Drain-Source
250
250
375
250
250
350
Vo" -5 V
ON ReSistance
200
200
300
200
200
300
Vo -5V
250
250
375
250
250
350
Vo" a
600
600
900
600
800
900
Vo = -5 V
-1
-1000
-3
-150
-8
-4000
-10
-500
8
4000
10
500
o'c
l
..."5!
rOSlon)
6 I
T
C
7 H 'Sloft)
Source OFF
8
IDiom
Dram OFF
Leakage Current
9
I O(on) + IS(onl
Leakage Current
85°C/
70°C
IS
~
v-
0
-1 rnA,
-20 V
!!
IS = -100 p.A.
V-"'-15V
VS=-SV,VO=5V
VEN = 0.6 V
10
I
N
11
l'
liB
IINL
-1.2
mA
VAL =
IINH
Input Current.
Input Current High
-150 Mm
-150 Min
"A
VAH '" 3.5 V
ttransltlOn
SWitching Time of
Multiplexer
ton
Turn-ON Time
19
I,.
~
V-=-20V
V-"'-15V
Break-Before-Make
Interval
O.S Typ*
O.S Typ"
005 Typ*
0.05 Typ*
2.0 Typ"
O.S Typ"
08 Typ"
CS(oftl
Source OFF
Capacitance
10Typ"
10 Typ"
CO(ottl
Dram OFF
CapaCitance
20 Typ'
20 Typ·
"'
Orain Supply Current
-6
1+
Source Supply Current
8
8
1-
Dram Supply Current
-6
-6
1+
Source Supply Current
7
7
See SWitching Time Test CirCUit
VS(alll = 1 V
VS""VO"5V
VEN =0
All VA = 0
mA
VEN = 3.5 V
IPAA
APPLICATION HINTS*
VIN
Vef"
Enable Input Logic Input
Voltage
Voltage
Min High/
VINH Min/
Max Low
VINL Max
IV)
IV)
Supply
Voltage
IV)
vNegative
Supply
Voltage
IV)
+5+*
-20
3.5/0.6
3.5/0.6
-5 to +5
+5
-15
3.5/0.6
3.5/0.6
-5 to +5
VsorVD
Analog
Signal
Range
IV)
* Application Hints are for DESIGN AID ONLY, not guaranteed
and not subject to production testing.
··Electrical parameters chart based on V+ = 5 V, V- = -20 V.
4·2
VEN '" 0.6V,f" 1 MHz
-6
"TYPical values are for DESIGN AID ONL V, not guaranteed and not subject to production testing.
v+
I VS1 "'! 1 V, VSS '" +1 V, VS2-7"
Same as Above. Except V-= -1SV
pF
Positive
J See SWitching Time Test CriCUlt
1.2Typ*
2.0 Typ"
21 S l-
I", ~
Iz, p
2.0
3.0
Turn-OFF Time
120
1.5
1.2 Typ*
Turn-OFF Time
a
2.5
Turn-ON Time
ton
I
toft
C
1_
VO=VS=5V
-1.2
15 D toft
y
16 N t open
I" ~
Leakage Current
Vo = -5 V. VS" 5 V
Input Current,
Input Voltage Low
12
13
Channel ON
nA
Siliconix
gnd
TYPICAL CHARACTERISTICS
rOS(on) vs Vo
and Temperature
+5V
-20V
CO(off), CS(off) vs Vo
1000
OUTPUT
~+-+52~Y=
I"I"-
'-
--
l- I-
I L
l"- I-
~
~
W
u
+2~'!<=:
2
3
20
~
15
u
10
Cd{offl
l - I-
I
o
4
5
-5 -4 -3 -2 -1
Vo - DRAIN VOL rAGE (VOLTS)
t1- t -
:::>
"
o :E:
~
0
l- I-
0-
I- W
~~
a: I-
100
o !a
Iffl
=
V+
+5V'
V
-15V-
l"-t--
l- I- r-
1
2
3
4
5
If RGEN, RL or CL is increased, there will
IO(off)/IS(off) vs
Temperature
1000
~Ci)
a
~
Vo - DRAIN VOLTAGE (VOLTS)
rOS(on) vs Vo
and Temperature
w
~
l- t-
u
II
1
z
"
I I
a
25
;!
55°C";;;
10
-5 -4 -3 -2 -1
:---r-~-r-O
J+ .15)
30 r-v-= -15V
u
a:
:::>
- rw:
t--
55"C-
~~
Izl"-
'Oloff)
10
~ ~
o
z
z
~
"
;;
a:
Y
I
IS(off)
o
~
.::;..
8
RC times.
100
W
g
125"C
be proportional increases in rise and/or fall
....
0.1
a
=1==
"'-
'ii
a
u ~
w
"
o '"
~I
~
»z o O
----
i-+--±--t--t'-t-+_--I
IN
§
10
-5 -4 -3 -2 -1
..
-"
W
0.0 1
0
1
2
3
4
5
25
45
B5
Switching Time vs
Temperature
Supply Current vs
Tem peratu re
I II
V-=-20V
tan Va
ALL INPUTS'" 0
3.0
1-
2.5
I 1.....-
l- t-
toff Vo = +5 v-l...+---l
11-1
I-'
0.5
toff V o - 5V
o
-55 -35 -15
5
25
45
j
i I
o
65
85 105 125
-60-40 -20
T - TEMPERATURE (Oe)
:I
g
VGEN=+lV
-
I- t:!;,
u
1.0
-4
J>
i
-2
l"-
I-
I
l1li
v
~
~onJo=15V
'"
I
V+ - +5 V
5V
H-n
"
125
105
T - TEMPERATURE (Oe)
>= 2.0
I-"
~ lz
:;: 1.5
~
65
Vo - DRAIN VOL TAGE (VOLTS)
'111Ai
0
20 40
rl - I-
60 80 100 120 140
T _ TEMPERATURE (OCI
0
CD
~0
s:
--
.
~
w
'"~
-2
-4
VGEN
-ov
C
0
>
l-
i'
I-
"OFF" Isolation vs RL
and Frequency
100
90
80
~
70
0
60
z
>=
5
II
Jl
=
~
30
CD
>C
CD
I-
-20V
111111
:::> -2
0
>
.
-4
-6
V GEN - -1 V
,,"L -loon
VI
lK
~
50
40
II III
"-
0
I
+5V
111111
I'NJ.
RL
~
0
II
:::>
-2
"
II
-4
........
-6
VGEN--5V
-8
20
-1
10
·2
t-TIME (us)
106
107
f - FREQUENCY (Hz)
lOB
+5V
+5V
"OFF" ISOLATION'" 20 LOG 1VOUT 1
IVINI
Siliconix
4-3
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
5V
INPUT
+5V
-20 V
OV
VSl
OUTPUT
IV
OUTPUT
VS(ALL) = +1 V
VS2·7
OUTPUT
VS1 = -1 V
t open
Va
VSS=+1 V
S7
S.
Vsa
EN
OUTPUT
V S1
-=
=
+1 V
VS8 "'-1 V
Va
ttransitlon
SCHEMATIC DIAGRAM
~--~~~~~~~~~~--~~~~~~--~~~~~~--~~~~~~~-oV
(NEGATIVE
SUPPLY)
EN'o-~----+---+---l.....,..., !o:!
V+
}:
V+
A'
0-...-----+---+..
-=
(SUBSTRATE
AND POSITIVE
SUPPLY)
LOGIC INPUT
A' o-~----+-<..,
D.
r-+---+~-l----+-~+---l--~+-------------<) ~~~~~
4·4
Siliconix
8-Channel Multiplex Switch
with Decode
designed for . . .
BENEFITS
• Multiplexing Signals
•
H
Siliconix
Reduces Cross-Talk in Systems
o Break-Before-Make Switching
• Data Acquisition
DESCRIPTION
The DG503 is designed to function as a single-pole, 8-position (plus OFF) electronic switch. The function is implemented
by using eight P-channel MOS field-effect transistors as analog switches. In the ON state, each switch will conduct current
equally well in either direction, and in the OFF state each switch will block voltages up to 20 V peak-to-peak. The ON-OFF
state of each switch is controlled by drivers, which are in turn controlled by a 3-bit binary word plus an Enable-Inhibit
input. The truth table shown below indicates the binary word required to select anyone of the eight switch positions. Logic
input levels "L" and "H" correspond to positive logic "0" and "1". Assuming supply voltages of 10 and -20 V, logic "L"
:::; 0.6 V and logic "H"::::: 8.5 V. The rise and fall times of the drivers are designed to provide break-before-make switch action_
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
Dual In-Line Package
-) II
~
Q
ORDER NUMBERS: DG503AP OR DG503BP
SEE PACKAGE 12
3
D
o
CD
* Both V+ lines are internally connected, either one
or both may be used. V+ common to substrate.
3:
-._...
c
TRUTH TABLE
LOGIC INPUTS
Siliconix
AO
A1
L
H
-
'a
CD
CHANNEL
A2
En
'ON'
L
L
H
Sl
L
L
H
S2
L
H
L
H
S3
H
H
L
H
S4
L
L
H
H
S5
H
L
H
H
S6
L
H
H
H
S7
H
H
H
H
Sa
x
x
X
L
OFF
.
>C
CD
til
4-5
ABSOLUTE MAXIMUM RATINGS
V+ to V- . . . . .
V+ to V A, YEn .
V+ to VD or VS.
VD to VS· . . . .
VA, YEn to V-.
VD or Vs to V-.
· . . . .. . . . .. . · .
. . ...
·.
.. .
·.
·.
· . ·.
·. . .
·.·. ·.
.. . . . .. . · . · . · .
--0.3,33 V
--0.3,33 V
--0.3,33 V
±25 V
33V
33V
. .......
Current (Any Terminal)
Storage Temperature (A & 8 Suffix)
Operating Temperature (A Suffix) .
(8 Suffix) .
Power Dissipation* . . . . . . . . . . .
· . .. , .
-20mA
· . . -65 to 150°C
. . . . · . . -55 to 125°C
· . . -20 to 85°C
. .....
900mW
*AII leads soldered or welded to PC board. Derate
12 mW/'C above 75°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
CHARACTERISTIC
_55°C
150
250
600
1
1'2
TOS(on)
'3 WS
I_
I
4 T 'Slo'O
I-c
5 H 101 0 ff)
1-
6
10(onl + IS(onl
7 I
"NL
I_N
8
9 0
1-;0
y
117~
-2000
-3
-150
Dram OFF
leakage Current
-8
-4000
-10
-500
8
4000
10
500
Channel ON
Leakage Current
Input Current,
-1
Input Voltage Low
-1
H
TEST CONDITIONS. UNLESS NOTEO,
v- "" -20 V, V+ "" 10 V, VEn "" 8.5 V
VAL = 0.6 V. VAH =8.5V
VD = 10 v
Vo '" 0
VD--l0V
2.0
ton
Turn-ON Time
toff
Turn-OFF Time
0.8 Typ'
O.B Typ"
0.05 Typ'
0.05 Typ'
Source OFF
Capacitance
5 TypO.
5 Typ'
Drain OFF
Capacitance
20 Typ"
20 Typ'
-6
8
7
Break-Before-Make
Interval
l-
Orain SUPPlY Curren.t
1+
Source Supply Current
l-
Orain Supply Current
-6
8
-6
1+
Source Supply Current
7
nA
IS = -100 "A
VD = -10 V. Vs = 10 V
VD = Vs = 10 V
VAL"'Q
See Switching Time Test Circuit
VS1=11V VSS=+1V,VS2_7=gnd
"'
See SWitching Time Test Circuit
pF
Vs = VD = 0
VSlall) = 11 V
VEn" 0
mA
-e
VEn = 8.5 V. VA =0
IPAA
*Typlcal values are for OESIGN AID ONLY. not guaranteed and not subject to production testing.
APPLICATION HINTS*
VEn
Enable Input
Voltage
Min High/
Max Low
(V)
VIN
Logic Input Vsor Vo
Analog
Voltage
Signal
VINH Min/
Range
VINL Max
(V)
(V)
v+
v-
Positive
Negative
Supply
Voltage
(V)
Supply
Voltage
(V)
+10**
-20
8.5/0.6
8.5/0.6
-10 to +10
+5
-20
3.5/0.6
3.5/0.6
-10 to +5
+10
-15
8.5/0.6
8.5/0.6
-5 to +10
+5
-15
3.5/0.6
3.5/0.6
-5 to +5
"Application Hints are for DESIGN AID ONLY, not guaranteed
and not subject to production testing.
""Electrical parameters chart based on V+ = +10 V, V- = - 20 V.
4·6
IS'" -1 rnA
Vs = -10 V. VD = 10 V
"A
1.2 Typ'
CD(off)
UNIT
VEn:: 0.6 V
1.5
114 S
I-u
I~P
16 P
-2
1.2Typ·
I-N
11 A t open
I_M
I
12 C CSloffl
13
Source OFF
Leakage Current
SWitching Time
of Multiplexer
ttransition
1-
Drain-Source
ON ReSistance
MAX LIMITS
ASUFFIX
BSUFFIX
25"C
125°C _20°C
25°C
85°C
150
225
150
150
200
250
375
250
250
350
800
600
800
1000
1250
Siliconix
VEn = 0.5 V.
f;: 1 MHz
CJ
Q
TYPICAL CHARACTERISTICS
VI
o
rOS(on) vs Vo
and Temperature
V+
v:::
+10
v- -2DV=
II: '"
I"-
:J:
~~
z z
~I ::l~
100
r-.... ....... r-..
r..... r-....
I"-
I-- f-
+25°C
+125°C
20
"z>-
"
15
~
55°C
_II:
~z
10
"
"
;;;0
.....:0-'oUTPUT
,--""';'-0-11--<("' ~_,+o..,
V-=-20V-
25
~
w
btl: r- l- t-:::,
W
-20V
+5V
J+=l,D~
30
w
u_
"'"o 0"
Vo
CO(off)' CS(off) vs
1000
VV
Cd(off)
I-- I-- I-I-
I
!?
10
-10 -8 -6 -4 -2
0
2
4
6
C')Offl
8 10
-10 -8 -6 -4 -2
Switching Time vs
0
2
4
6
8
10
V o - DRAIN VOLTAGE (VOLTS)
Vo - DRAIN VOLTAGE (VOLTS)
If RGEN, RL or CL is increased, there will
be proportional increases in rise and/or fall
RC times.
IO(off)/IS(off) vs
Temperature
Vo
100
3.0
~
~
;::
['\
V-=-20V-
I'\.
2.0
1.5
~
1.0
~
"
~ " z
2.5
"iz
u
LJ'DJ
10
I-- I-- i=
~ ~
['\
"
II:
'O(offl
A
II:
:J
V
oI "W
1'\
=~
'on
tI:;' r- l- t::::
0.5
~~
~~
0.1
1/
IS(oft)
/
IN
-2
E
,
0.01
-10 -8 -6 -4 -2
0
2
4
6
B 10
25
45
Vo - DRAIN VOLTAGE (VOLTS)
Switching Time vs
Temperature
V+
S
w
"
;::
"iz
2.5
'on
1.5
I
1.0
I
_
,.....
i,..-'
,
V
20 40
~
""
Vor8tV
1+.,'1-1 I
I
60 80 100 120 140
T - TEMPERATURE (Oe)
90
80
li;
';::z"
70
60
S
50
~
0
0
r
l>
20
40
VGEN-+ 1V
rI-- I--
J
60 SO 100 120 140
D
I
J.
f--l-
I
o
CD
I
.
3:
,
~
o
-'a
-.
c
-2
1
VGEN-DV
-4
>
•
;:
!
6
-20V
::s
I
-4
CD
I
>- -2
~
III IIIII
III DOn
11111
I
--
~
+5V
--
!
I
,
-4
CD
VOEN=-lV
-6
~L=l
RL"" lK
0
~
I
I
o
-60 -40 -20
I'\.
VGEN =+5V
-2
-2
T - TEMPERATURE (OCI
"OFF" Isolation vs RL
and Frequency
100
I
J
VOE=ov
0.5
0
125
V+=+10V
v- = -20V-
r-- f::t:+..
II:
II:
toft
-60 -40 -20
105
I+.L I_I-r-
r-... ....... .......
1
VI-"
.. V
85
Supply Current vs
Temperature
VO=+l V....
2.0
~
~
+10V
~~:~~ov
cL =30pF
3.0
65
T - TEMPERATURE (OC!
-2
"
40
II
4
I"'
30
6
VGEN=-SV
20
8
-1
10
t-TIME (j.Is}
106
10 7
f - FREQUENCY (Hz)
108
+10V
+10V
'·OFF" ISOLATION = 20 LOG IVOUT 1
IV1NI
Siliconix
4-7
S
SWITCHING TIME TEST CIRCUIT
1ft
C!)
CII
+10V
-20V
v-
s,
vs, 0---0--1---<";'
ov
"--_-+-0-__-0 OUTPUT
S2
OUTPUT
'"
OUTPUT
----1-..
OUTPUT
---+-'
'topen
EN
VS1 "'+1 V
VSS ;-lV
!------t-ttransition
SCHEMATIC DIAGRAM
~~~_~~
__
~~~~~_~~~-~~
__
~~-~r-~
__
~~~~-¢v
(NEGATIVE
SUPPLY)
ENo-~--+--+--\-,
A'
0--+---1--_+--,
f
v+
-=-
AND POSITIVE
V+
(SUBSTRATE
SUPPLY)
lOGIC INPUT
A'o-.....- - t - - .
D,
r-+----+-,~t_-_t_~_+--t__
4·8
Siliconix
_ t _ - - - - - - - < J ~I~~p~~
Differential a-Channell
16-Channel CMOS
Analog Multiplexer
c
H
Q
Siliconix
BENEFITS
•
Environmentally Rugged
o Latchproof CMOS
• Easily Interfaced
o TTL, DTL and CMOS Direct Control
Over Military Temperature Range
• Low Stand-By Power
o 36 mW Typical Stand-By Power
• Reduces System Cross-Talk
o Break-Before-Make Switching Action
• Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
designed for...
• Data Acquisition Systems
Iii Multiplexing Reference Signals
• Communication Systems
VI
o
0-
C
Q
VI
o
.....
DESCRIPTION
The DG506 is a single-pole 16-position (plus OFF) electronic switch array [DG507 is a double-pole 8-position (plus OFF)]
which employs 16 pairs of complementary MOS (CMOS) field-effect transistors designed to function as analog switches_
In the ON condition each switch will conduct current in either direction, and in the OFF condition each switch will block
voltages up to 30 volts peak-to-peak_ The ON-OFF state of each switch is controlled by drivers, which are in turn controlled
by a 4-bit binary word (DG507 by a 3-bit binary word) input plus an Enable-Inhibit input_ The truth table below shows the
binary word required to select anyone of the 16 switch positions, provided a positive logic "1" is present at the Enable
Input_ With logic "0" at the Enable input all switches will be OFF_ The logic decoder and the Enable inputs will recognize
voltages between 0 and 0_8 V as logic "0" voltages, and voltages between 2.4 and 15 V as logic "1" voltages_ The input can
thus be directly interfaced with TTL, DTL, RTL, CMOS and certain PMOS circuits_ Switch action is break-before-make_
For new designs, use the DG506A and DG507A
FUNCTIONAL DIAGRAMS
8 Channel MUX DG507
16 Channel MUX DG506
r~
8,
1::
Vi~7
~g
82 21
S3~2
I
~1 26
I
~H~
~~: ~
s~~
I
I
:
I
II
I
:
I I
I
I
I
I
~~f-------i"
9
I
:
I
I
I
I
I I
I
I
I
I I
I
I
I
II
I
I
I
:
I I
I I
Vref*
1,2
'f'3
--
-------"'~
l' '
,
:
,
28 Da
858<>-'24
I
I
Gnd
127
~~~~~
I
~g:~~
v-
1,
S1a ~g
52a<>-=21
I
84-23
~10
v+
G1,dz v
28 0
S2b
9
S5b
6
S~~
~6~~
I
I
06506 CMOS DECODE LOGIC
:
SSa 25
87.
SSa l'
~lb 10
S~~
I
,
,I
:
;
I
--±-r~
,
I
:'
,
, i +-+
I
2
J:-
Db
::::I
:
'
sa
0
a
OG507 CMOS DECODE LOGIC
""OPTIONAL (NORMALLY LEFT OPEN)
TRUTH TABLE
A3
A2
Al
AO
En
X
0
0
0
0
0
0
0
0
1
1
1
X
X
0
0
X
0
1
0
1
0
1
0
0
1
1
1
1
1
()
0
0
0
1
1
1
1
1
0
0
1
~
PIN CONFIGURATIONS
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DG506
ON
SWITCH
NONE
1
2
1
1
1
1
3
4
v+
NC
D
G
5
5
0
1
1
1
1
1
1
1
1
1
1
1
6
1
Logic "0" = VAL::; O_BV, Logic "1" = V AH
9
10
11
12
13
14
15
16
~
-
D
G
5
0
6
.
0a.'
27i=D
y-
N~
'
25i=D
~?.a
87
5
8'5
8,.
. S1b
ss.
8'3
S5.
8'2
54.
s3'
52&
8.
S'b
GND
'G~D
*vREF
A3
*VR:EF
NO
-
<1:.
<:r::
7
23
22
~8
~.
2'
20
<.I:
rD
i;.I?
I:g
tp.
,. p>
'8P>
17P>
'6!;P>
'5
"
v.
85
S4Q
8.
83
S2.
Sl.
8,
. E.
'''p.
111 .
-
'a
CD
>C
CD
88
sa.
p> ~
<:.E "
0
~
1ft
82
EN
AD
A,
A2
TOP VIEW
*OPTIONAL (NORMALLY LEFT OPEN)
V+ COMMON TO SUBSTRATE
2.4 V, Screen is OG507
Siliconix
ORDER NUMBERS:
DG506AR OR DG506BR
DG506CJ
DG507AR OR DG507BR
DG507C
SEE PACKAGE 14
SEE PACKAGE 13
4-9
ABSOLUTE MAXIMUM RATINGS
VIN (A, En, or VREF) to Ground
· . .. . -0.3 V, V+
Vs or VD to V+ ....
..
.. . . . 0, -32 V
..
0,32 V
Vs or VD to V..
V+ to Ground ......
.. . .. · .
. .. 16 V
V- to Ground ...... . . .. . . .
·.
· . -16 V
Current (Any Terminal, Except S or D)
· . 30mA
Continuous Current, S or D .......
· . 20mA
Peak Current, S or D
(Pulsed at 1 msec, 10% Duty Cycle Max) .... 40mA
Storage Temperature (A & B Suffix) ...
-65 to 150°C
(C Suffix) ........ -65 to 125°C
-55 to 125°C
-20 to 85°C
. . o to 70°C
Operating Temperature (A Suffix) ...
(B Suffix).
(C Suffix).
Power Dissipation (Package)"
28 Pin DIP"" ........ . .. .
28 Pin Plastic DIP'"
.. .. .
.
..
..
1200 mW
625mW
• All leads soldered or welded to PC board.
"Derate 16 mW/oC above 75°C.
"'Derate 8.3 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MEASURED
TERMINAL
CHARACTERISTIC
I,
1
13
1-
VANALOG
Minimum Analog Signal
Handling Capability
rOS(onl
Drain Source
ON Resistance
.draSCon)
Dram-Source ON
MAX LIMITS
NO.
Note 1)
TESTS
PER
TEMP
TYP
25'C
A SUFFIX
f-';5'C
±15
Stc 0
BIC SUFFIX
25D C 125°C
"5
:!:15
-20/
O"c
25D C
UNIT
B5/
70°C
"5
±15
16
270
400
400
500
450
450
550
16
230
400
400
500
450
450
550
16
6
V
!l
Greatest Change in
4
StoO
OG506
,
10(on)
Channel ON Leakage
(Note 21
CUrrent
'AH
Address Input Current,
Input Voltage High
iA(peak)
Peak Address
Input Current
'AL
Address Input Current,
Input Voltage Low
N
20
21
D
Y
N
A
M
I
C
-
25
2s
T,28
S
2a~
SoP
31~
±1
±50
,5
,50
VS-10V,VO--10V
'50
'5
±50
VS=-10V,VO""0V
±300
:1:20
t300
Vo = 10 V, Vs = -10 V
1
-0.03
"
±10
1
-0.03
:t10 t300
::!:20
t300
V O "-10V,V S ·10V
±5 ±200
,,0
:t200
VO=10V,VS=-10V
-0.015
D
±10
±200
VO--10V,VS-10V
-0.06
±10 t300
±20
t300
VS(al!)
16
-0.06
,20
±3oo
VS(sl1} = Vo '" -10 V
16
-0.03
"0 t300
,5 ±200
±10
:1:200
VSlall) -
VSlall) - Vo =-10 V
,5 ,200
±10
:1:200
0.002
10
30
10
30
VA
(5i4
0.006
10
30
10
30
VA=15V
-75
-0.002
-10
-30
-10
-30
VEN - 2.4 V
1 -0.002
-10
-30
-10
-30
VEN = 0
1
.A
0.6
0.2
tonlENI
Enable Turn-ON Time
0
1
1.0
1.5
tcfflEN)
Enable Turn-OFF Time
D
1
OA
1
,+
,,,+
0
~
OG507
16
6
D
1
2
45
23
dB
iAIIVA=O
See Figure 2
VEN ""D,RL = 1K .n.el = 15pF
Vs = 7 YAMS. f = 600 KHz
Vs = a
V EN =O,f=140KHz
pF
VO=O
Positive Supply Current
V+
1
5,2
10
10
v-
1
-5.2
-10
-10
POSItIVe Supply Current
v+
1
1.2
2.5
2.5
Negative Supply Current
v-
1
-1.2
-2.5
-2.5
VEN;: 5 V
rnA
NOTES:
1.
TYPical Values are for DESIGN AID ONLY. not guaranteed and not subject to production testing
2.
1010n) is leakage from driver Into "ON" sWitch.
1VOI
20 log IVS I Vs = Input to "OFF" switch Vo = output due to VS·
3.
OFF isolation
4.
Functional operation IS possible for supply voltages less than 15 V. but the input logic threshold Will shift.
For V+ = IV-I'" 10 V, 1.5 V may be applied to the VREF terminal. The VREF terminal has RIN £l: 45K n
(See the applications section.)
4-10
.'
Negative Supply Current
e-
See Curve "IAvsVA"
See Figure 1
68
S
Sequence each sWitch on
VAL = 0.8 v. V AH to 2.4 V
v
3
D
Coloffl
2,4
(5i4
D
Dram OFF
Capacitance
Vo = 10 V
-0.03
Break-Before-Make
Interval
eSloff)
Vo '" 1 a v
16
of Multiplexer
OFF Isolation (Note 3)
C
(5i4
t open
VEN =0
nA
,5 '200
16
2 -0.015
AO. A,. A2.
(Aa) EN
SWltchmg Time
Source OFF
Capacitance
rOSlon) AVE
VS" 10V
OS;;;;
16 -0.005
2
I Sequence each switch on
I VAL = 0.8 V. VAH = 2.4 V
Coscon) MAX - 'OSlon) MIN)
16 -0,005
ttran51tlon
1-
24
D
DG507
17 P
U
T
-
DG506
1"13
119
1"22
123
1-
S
OG507
15
17s
1-
Source OFF Leakage
Current
Drain OFF Leakage
Current
Vo --10 V, IS =-200J,lA
-10V
T
C
H
IOloft)
Vo .. 10 V, 15 - -200 p.A
AraSlan) '"
Resistance Between
S
W
I ISloff)
SWitch ON IS" 10 rnA
%
Channels
15
1I...!.
7
18
18
110
I"
liz
1"13
I,.
TEST CONDITIONS, UNLESS NOTED:
V+ = 15 V. v- - -15 V. Ground = O. VREF = Open
(Note 41
Siliconix
All VA = 0
VEN = 0
DGS06
DGSD7
ICXBA.
leXBB
SCHEMATIC DIAGRAM
V+ [SUBSTRATE)
(+SUPPI. y)
Typical Logic Interface
Typical Switch
+-_-j__+--I AO
CH m
[
o:le~
'm
D~le~ 1-1-----..,
9
013
v+
v-
DECODE
R2
450K
ANO
SWITCH
DRIVE
R3
50K
v-
EN'
GND
{CMOS LEVELSI
GNO
(-SUPPLY)
SWITCHING TIME TEST CIRCUIT
SWITCH OUTPUT
VOb
(SEE FIG 11
O.S VSBb
V SBb
ItranSltlon
-"-
0.1 Va
SWITCH OUTPUT
VOb
(SEE FIG 21
+15 V
OPEN
~
:::I
0.9 Vo
Vo
Sla THRU
VSlb
SSa' Da
S2b THRU Sab
DG507
1--0-'--1Kl
LOGIC INPUT
Ir < 20ns
tf< 20n$
lK !!
1
SWITCH
OUTPUT
VOb
-"a...
-.
'
-
Figure 2
V+
Positive
Supply
Voltage
(V)
V REF
Negative Reference
Pin
Supply
Voltage Connection
(V)
(V)
+15"
-15
Open
+12
-12
+10
+8'"
CD
Application Hints'
v-
V IN
Logic Input
Voltage
V INH Mini
V INL Max
(V)
Vs
.
>C
CD
or
VD
Analog
Voltage
Range
III
'Application Hints are for DESIGN AID ONLY, not
guaranteed and not subject to production testing.
(V)
2.4/0.8
-15 to +15
Open or
1.4 V
2.4/0.8
-12to+12
-10
1.4 V
2.4/0.8
-10 to +10
-8
1.4 V
2.4/0.8
-8 to +8
3:
c
35P
APPLICATIONS
o
ca
.l!-*
Electrical
Ch~racteristics
chart based on V+
=
+15 V,
V-= -15 V, V REF = Open.
***Operation below.::+:8 V is not recommended.
Siliconix
4·11
16-Channel and
Dual a-Channel
Analog Multiplexers
H
Siliconix
designed for . . .
•
•
•
BENEFITS
Data Acquisition Systems
Multiplexing Reference Signals
Communication Systems
•
Environmentally Rugged
o 40V Power Supply Max Rating
o Static Protected Logic Inputs
o Latchproof
•
Easily Interfaced
o TTL Compatible without Pull-Up
Resistors
•
Improved System Accuracy
o rDS(on) < 400n
OVER ROR = 150 Microvolts at 125°C
= ID(on) x rDS(on)
o ~rDS(on) < 6%
for -10V < VANA < +10V
• Pin for Pin Compatible with IntersillH6116.
Harris HI506 and Analog Devices AD7506
DESCRIPTION
The DG506A and DG507A designed on the Siliconix PLUS-40 CMOS process provides solid state switch action with 400
ohms contact (ON) resistance and very high OFF resistance. True bidirectional switch action takes place over the full analog
signal range of ±15 volts, with Break-Before-Make operation to prevent momentary shorting of signal inputs. The DG506A
provides 16 channel single ended multiplexing and demultiplexing of ±15 volt analog signals. The D'G507 A provides 8 channel differential multiplexing and demultiplexing of ±15 volt common mode plus differential signals.
FUNCTIONAL DIAGRAMS
y,
y"
' ....
...-:1'0-
" ,."
A".n-ri
" "
, "
~ri-
m
, "
'
... "
..., ",
.... ""
..
..
.A'.I~i
", "
",
, ,
,
I,
S,
...,-: 1
1
""-:1 1 ! i
i j 1 I
I
I I i
i
I I
1 1 1 I
...,-: 1
A':.
i
i
I
1
1
!
i
iii i i
1 ! 1 1 I
1 1 1
...-:
....-:1
"
".~ ~i
I
I
1
:
1
1
J."
A,C·
A,C'
.,
f!!o
., .~
"
,O-!
I
!"
DG506A
16 CHANNEL SINGLE ENDED MUL TIPLEXER
4·12
k
I
,
1
1
I
I
I
1
I
,I
,
I
1
J.--:
v...
1
I
,
,
....-:
I
I
,,
,
1
I
I
:,
, .A--:
...t-:
,
J--: ,,
,
,,
I
,,
y"
.........
-1',, -----+,
'
1
,
i,
,
:
,
b'A,
~"
!!o,
1
,,
,
I
I
,
,1
I
: r~
t .._+I
.!.o
I
,
I
I
I
,1
DG507A CMOS DECODE LOGIC
b"
A,
'.
I
,
I
,
I
,
,,,
,,
:,
,,,
/,.
---(4
·,
" ·
,
, ·
iii iii
..,-:
,
/.
,
1
I 1 1
1
1 : I :
b"
"
y"
A'".
, "
I I 1
DG506A CMOS DECODE LOGIC
y"
'" "
"
"
A".
A':.
""-:'
n
I,
y,
y"
y"
r
I
'.
DG507A
DIFFERENTIAL 8 CHANNEL MULTIPLEXER
Siliconix
PIN CONFIGURATIONS
Dual-In-Line Package
V+
II
NC
IT
~o
S,.
[!
S"
15
rg
f1f
r;o
5,0
).1 I
......11 11 1
./1' "
.Y. i ""
""T
I
GND@
A3
[Th
I
12m S,
sab
[!
[!
S,b
IT
56b
'6
6rZb 54
II
....' I, II I
!lIDs,
I III II II
~ fmEN
Im
.-.t: "
I
S3
I rrn
:1Q
S'b
'"ii
I "l'!""
r
NC
A2
1r
I (II, I ,
mS, •
m5'a
r0-
IIIIIII~ mEN
DeCODe
lir
II
iB
S5.
S4i1
.n. 53a
: 1::1 i.:!
III II n~1
, II III I!".
[E
~S6a
Im
~L:
I I II i..::i
,,'Ti!..
'l'i"J.".
GND@
NC
1~
i:i.J
'111.0.
S3b'1i'
S2b
~sa.
l2sl 57a
i,..,
""":
"fl,
IT
S4b' :1
I. ~Ao
~Al
II
~v-
.'1.
!.-.
S5b
rllL S'
'11,11 ' ,
DeCODe
rn
NC
~Ss
,.., I I ,"
~Da
~
~SB
I
......J..:'
J..:!III
""In
NC
..... '"
II
Dbt.!
iws.
.-1. ' ,
.;J.'
r.
5'3 r-r
S'4
S"
_.J.l
.Y.
':--J
V+
~v-
.-1.
NC []:
5,2
Dual-In-Line Package
mAo
[!!]Al
~ l!m
A2
Top View
Top View
ORDER NUMBERS:
DG506AAR OR DG506ABR
SEE PACKAGE 13
ORDER NUMBERS:
DG507AAR OR DG507ABR
SEE PACKAGE 13
DG506ACJ
SEE PACKAGE 14
DG507ACJ
SEE PACKAGE 14
--
TRUTH TABLES
J>
a
o
DG507A
DG506A
A3
A2
Al
AO
En
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ON
SWITCH
NONE
1
2
3
4
5
6
7
a
::::I
A2
Al
AO
En
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
1
0
1
ON
SWITCH
CD
NONE
1
2
3
4
5
6
.---
Ic
•.
'a
7
a
CD
9
10
11
12
13
14
15
16
CD
til
Logic "0" = VAL ..
o.av. Logic "1" = VAH ;>2.4V
Siliconix
4·13
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to V-
Operating Temperature (A Suffix).
(B Suffix).
(C Suffix).
Power Dissipation (Package)'
28 Pin DIP" ...... .
28 Pin Plastic DIP'"
.. . . . . . . . . . . 44V
. . . . . . . . . . . . 25 V
GND ............. .
. -2 V to (V+ +2 V) or
Digital inputs 5 VS, VD ..
20 mA, whichever occurs first.
30 mA
Current (Any Terminal, Except S or D)
Continuous Current, S or D
20mA
Peak Current, S or D
(Pulsed at 1 msec, 10% Duty Cycle Max)
40mA
Storage Temperature (A & B Suffix) .
-{i5 to 150° C
(C Suffix) ....... . -{i5 to 125° C
V+ . . . . . . . . . . . . . . .
-55 to 125°C
-20 to 85°C
o to 70°C
1200 mW
625mW
• All leads soldered or welded to PC board.
"Derate 16 mW/oC above 75°C.
"**Derate 8.3 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
TEST CONDITIONS, UNLESS NOTED:
V+ = 15 V. V- = -15 V. Ground" 0,
INota4)
CHARACTERISTIC
1
±15
±15
±15
±15
v
270
400
400
500
450
450
n
230
400
400
500
450
450
550
550
±15
-2
"'3
rOS(on)
Drain Source
ON Resistance
.6r0510n)
Source ON Resistance
16
16
5to 0
-
=
10 V, IS = -200j.lA
Vo = -10 V, IS = -200 j.lA
Greatest Change in Drain-
.6.rOS(on)
16
SloD
Vo
=
(
rOSIOn) MAX
Between Channels
~
~ ~r'S_'_Of_f1____~__'ffi_n_t______-r_____+------~~~16~-~~.0~0~5~--_r~'~1-r~'5~0_r--+-~'5~~'~50~
VS=-10V,VO""0V
...!...
~
16
OG506A
~~~~:n~FF Leakage
-
-
0
2
~
11
Channel ON
Current
..2..:.
14
15
I
16 N
leakage
DG507A
IAH
Address Input Current,
Input Voltage High
1"7 P _------------I
~ IAL
18
Address Input Current,
AD,
A"
ttrans,tion
Switching Time of Multiplexer
~
toeen
Break·Before-Make Interval
A2,
(A3 1 EN
Input Voltage Low
~
21
MIN)
±50
±50
VS=10V,VO--10V
±1
0.020
:1:10
:1:300
:1:20
:1:300
VO"'0V,VS"'-10V
-0.03
0.007
:tl0
:t300
±20
±300
VO"'-10V.Vs=10V
±5
±200
±10
±200
-0.015
:!:5
±200
flO
±200
VEN" 0
16
0.03
f10
±300
±20
:t300
16
-0.06
±10
±300
:1:20
:1:300
16
0.015
±5
±200
±10
±200
nA
Vo-10V.VS"-10V
Vo--l0V.VS""0V
VSla11) = Vo = 10 V
DG506A
-
-
is
0.002
DG507A
"'i2
_
rOSlon)
-10V.c;VS.c; 10V
Source OFF Leakage
1010ffi
VAL =O.BV. VAH =2.4V
VEN" 2.4 V
rOSlon) AVE
-~
8
-;
Sequence each sWitch on
16
-0.03
i5
±200
:1:10
:1:200
(5)4
-0.002
--30
10
-30
(5)4
0.006
30
10
30
3
-C
V+
EN
EN
DG501A
ALL SAND Da
CD
Vs· +5 V
~
fft
DG506A
A2
DG507A
"::"
A,
SWITCH
SWITCH
LOGIC
INPUT
OUTPUT
135
lK n
"::"
"::"
"::"
"::"
Vo
lOGIC
INPUT
.
'K01
SOn
PF
"::"
"::"
"::"
OUTPUT
V
I'.PF a
"::"
Figure 3
Figure 2(bl
Siliconix
4-15
....C
o1ft
SCHEMATIC DIAGRAM
"
v+
Q
00--1~_ _----'~-""---------'
r---~----~----+--o~
C
o1ft
00
Ai<
DECODER
"
GND
Q
~---+----~-------oDX
~~
LOGIC
INPUT
EN
vTYPICAL
SWITCH
LOGIC INTERFACE
AND LEVEL
SHIFTER
4-16
Siliconix
8-Channel/4-Channel
Differential CMOS
Analog Multiplexer
designed for...
• Data Acquisition Systems
• Multiplexing Reference Signals
• Communication Systems
H
Siliconix
BENEFITS
•
Easily Interfaced
o TTL, DTL and CMOS Direct Control
Over Military Temperature Range
III Low Stand-By Power
o 36 mW Typical Stand-By Power
• Reduces System Cross-Talk
o Break-Before-Make Switchinq Action
• Reduces External Component Requirements
o ±15 V Analog Signal Range with ±15 V
Supplies
• Environmentally Rugged
o Latch-proof CMOS
DESCRIPTION
The DG50B is a single-pole B-position (plus OFF) electronic switch array [DG509 double-pole, 4-position (plus OFF)) , which
employs B pairs of complementary MOS (CMOS) field-effect transistors designed to function as analog switches. In the ON
condition each switch will conduct current in either direction, and in the OFF position each switch will block voltages up to
30 V peak-to-peak. The ON·OFF state of each switch is controlled by drivers, which are in turn controlled by a 3-bit binary
word input plus an Enable,lnhibit input. The truth table below shows the binary word required to select anyone of the B
switch positions, provided a positive logic "1" is present at the Enable Input. With logic "0" at the Enable input all switches
will be OF F. The logic decoder and the Enable inputs will recognize as logic "0" any voltage between a and O.B V, and any
voltage between 2.4 and 15 V as logic "1" inputs. The inputs can thus be directly interfaced with TTL, DTL, RTL, CMOS
and certain PMOS circuits. Delays are designed into logic decode and driver circuits to insure that switch action is breakbefore-make. For new designs, use DG50BA and DG509A.
DECODE TRUTH TABLE
D
G
5
0
B
PIN CONFIGURATIONS
ON
En
A2
A1
AO
SWITCH
r-~+-~~~-r~~~~~
X
X
.X
0
NONE
0
0
0
1
1
0
1
0
2
0
0
1
3
0
1.
1
4
5
0
0
0
6
0
7
8
FUNCTIONAL DIAGRAM DG508
v-
V+
Gnd
13
1'3
1'4
~r------/~(-+/. I
I
~+----/ro.....iiH'-+-+:--i
;:/"'
, , Iii
i
I
I
A2
&'6
A1
En
V+'
V-
S'b
S,
Logic "1" =
V AH;;' 2.4 V
Logic "a" =
VAL'; 0.8 V
S2
s,;
s'"
s..
S3
s,;
~
~
S4
81
54a
D_--,._ _ _ _ _.r--S8
S4b
D.~_;.
_ _ _ _ _.r_~Db
~2
AO
En
CD
Dual-In-Line Package
c
Dual-In-Line Package
.
3:
-.-
"-.c
CD
CD
Ul
FUNCTIONAL DIAGRAM DG509
V+
V-
Gnd
s""..:~======~~
... ,....;::t-----::-...-:~--1-!
...
S3. 0---,;t----:;---1 ~--f---+_+
D.
V+ COMMON TO SUBSTRATE
S'b o-:;;t---+---f----+-~...,
S2b.o-;:;t-+-+-"'-:~--1-!
S3b ~it-+---1.---+---:-+
S4b""""'t;~=±=::±=::::::l~
:a-
:s
II
o
ORDER NUMBER:
ORDER NUMBER:
DG509AL
DG50BAL
SEE PACKAGE 17
SEE PACKAGE 17
'Camman to Substrate and Base of Package
I
&'
l1li
-
TOPVIEW
:I
DG508CMOS
DECODE LOGIC
&'6
.!'......,o
Flat Package
Flat Package
~
ORDER NUMBERS:
DG50BAP OR DG50BBP
SEE PACKAGE 12
DG50BCJ
SEE PACKAGE B
Siliconix
ORDER NUMBERS:
DG509AP OR DG509BP
SEE PACKAGE 12
DG509CJ
SEE PACKAGE 8
4-17
ABSOLUTE MAXIMUM RATINGS
Storage Temperature (A & 8 Suffix)
(C Suffix)
Power Dissipation (Package)*
16 Pin DIP**
16 Pin Plastic DIP***
Flat Package****
VIN (A, EN) to Ground
-0.3 V, V+
0, -32 V
Vs or VD to V+
0,32 V
VsorVDtoV16 V
V+ to Ground.
V- to Ground.
-16 V
Current (Any Terminal, Except S or D)
30mA
Continuous Current, S or D
20 mA
Peak Current, S or D
(Pulsed at 1 msec, 10% Duty Cycle Max)
40mA
. -55 to 125°C
Operating Temperature (A Suffix).
-20 to 85°C
(8 Suffix) .
(C Suffix) .
o to 70°C
-65 to 150°C
-65 to 125°C
900mW
470mW
750mW
* All leads soldered or welded to PC board.
**Derate 12 mWfC above 75°C
***Derate 6.3 mWfC above 25°C
****Derate 10 mWfC above 75°C
ELECTRICAL CHARACTERISTICS
All DC para meters are 1 00% tested at 25° C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
NO.
MEASURED TESTS
TERMINAL
PER
TEMP.
CHARACTERISTIC
MAX LIMITS
TYPt
ASUFFIX
25°C
_5S c C
2S"C
-20"C
DoC
2SOC
TEST CONDITIONS, UNLESS NOTED:
UNIT
BIC SUFFIXES
12S"C
V+= 15 V,
v- =
15V, Ground'" 0
85°C
70c e
Minimum Analog Signal
1
VANALOG
11-2
3
1-
Dr~In-Sourcc
rOS(on)
4
I~ ~
1---2
1-2
Greatest Change In Dram
Source ON ReSistance
Between Channels
Source OFF
IS(off)
Oram OFF
Leakage
10(011)
9
Current
1010n)
15
,
116
I-
.
Oram ON
Leakage
Current
u
116
1-;;;
21
N
'-
,
A
24 M
c
25
-
~
27
L
Y
500
400
500
:15
450
450
550
450
450
500
8
6
8
-0.005
8
-0.005
1
VS=10V,VO=-10V
±50
VS--l0V,VO-l0V
-0.015
±10
±200
±20
±200
VO-lOV,VS
1
-0.015
±10
±200
±20
±200
VO=-10V,VS=10V
2
-O.OOB
!10
1100
!20
!100
VO=10V,VS=-10V
2
O.OOB
no
±100
'20
±100
VD -
8
-0.03
±10
±200
±20
±200
VS(all) - Vo - 10
Enable Turn·OFF Time
Aa,A, (A 2 )
EN
v
±1O
±200
±20
:':200
VS(alll- V O -
8
~la
~
100
±20
±100
VS(all) - Vo = 10 V
8
-0.015
~
10
~
100
±20
.!.l00
VS(all) - Vo =
10V
Sequence each SWitch on
VAL = 0.8 V, V AH '" 2.4 V
10V
VA - 2.4 V
VA= 15V
(4) 3
-75
(3)2
-0.002
-10
-3D
-10
-3~
VEN - 2.4 V
1
-0.002
-10
3D
-10
-3~
VEN = 0
06
1
"A
See Curve "1 A vs V A
..
J
All VA =
a
See Figure 1
0.2
I
"'
1
10
15
0
1
0.4
1
0
8
68
S
8
5
0
0
1
2
25
12
POSitive Supply Current
V+
1
35
8.0
8.0
Negative Supply Current
V-
1
-3.5
-B.O
-8.0
1+ Standby
POSitive Supply Current
V+
1
1.0
24
28
1- Standby
Negative Supply Current
V-
1
-1.0
-2.4
-2.8
See Figure 2
dB
VEN=O,RL ~ lKQ,C L '" 15pF
Vs = 7 VRMS, f = 500 kHz
Vs = 0
pF
OG50B
OG509
VEN = 0
10V,V S =10V
-0 03
3D
EN
oA
-O.OlS
-3~
0
I
MIN)
10 V
8
10
0
Drain OFF
Capacitance
=
fOS(on} AVE
±5
-10
Enable Turn·ON Time
CO(oH)
OS(on) -
±SO
30
ton(EN)
CS(off)
I Sequence each sWitch on
I VAL 0.8 V, V AH '" 2.4 V
_ CDS(On~ MAX - fOS(on)
"±1
-3D
t open
Source OFF
Capacitance
-200 p.A
Vo - -lOY, IS'" 200,uA
±50
10
D
..
VO-1OV,IS
±5
-10
Break·Before·Make
Interval
toff(EN)
n
SWitch ON IS'" 10 rnA
±50
0.006
ttransltlon
OFF Isolation
V
%
-0002
SWitching Time of
Multiplexer
"
31
400
±lS
1413
'AL
28 S
I~
230
!15
A O' Al IA 2 J (4) 3
Address Input Current
Input Voltage Low
i-;;- ~ ,-- P
OG509
Peak Address
Input Current
11"23
I"";';;
D
IA(peak)
122 0
y
OGSOB
Address Input Current,
Input Voltage High
T
20
D
DGS09
I---
270
8
!15
400
-10 V':;; VS:::;; 10 V
'AH
N
17 P
S to 0
OGSOB
t---
8
400
D.r
S
Leakage Current
H
1"10
I"
1"12
113
I,.
S to 0
ON Resistance
6r05(on)
I- S
5 W
1--= ,
±15
Handling Capability
VEN"" 0, f '" 140 kHz
VO=O
VEN = 5 V
mA
AIIVA"'O
VEN = 0
ICXG·A DG508
ICXG·B DG509
t Typical Values are for DESIGN AID ONLY, flot guaranteed dnd not subject to production testing.
~ID(on) IS leakage from driver Into "ON" SWitch
··OFF Isolation
4·18
~ 20 log :~~:
,VS" Input to "OFF" SWitch, Vo = output due to Vs
Siliconix
TYPICAL CHARACTERISTICS
Typical delay, rise, fall, settling times, and
rOS(on) vs Vo and
Power Supply Voltage
rOS(on) vs Vo and Temperature
'DO
l5V
z
600
ow
600
I-I-I-I-I-I-hj£-k-I-I-H
500
1-t-t-t-tT-l-t-t-t-'lrt-H
~ 400
l-t-hl"-l=±£:....F-I-PI-H
_
~tii
§ ~ 500
"'"
~ ~
"1~~ 400
:i;
00
"z
"z
12S"C
ca: ....
" 300
~~
~'§m~ t=~~~~~~~~~~tA~~~t;t:t~t=~'""~
v-
2"C
.sa: 200
e
300
200
~
-10
-5
10
-10
-15
15
Logic Threshold vs
Power Supply Voltage
c
~
90
1.5
:1:
....
;;
1.0
"
~
....
.,
~
..-- - ~
9
0.5
a:
aw
'"
;2
~
~
c
w
~
I
.8
.,0
IA vs VA
(Terminals AO' Al, A2, EN)
-125
I
I
;;
.3
.... -100
a:
~
"
~
"~
o
>
....
i<
"
§"
T - TEMPERATURE (OCt
r
-75
VGEN '" +10 V
2~Oci
6
w
-25
o
>
....
~
TYPV Th
11111111
z
~I~
11M
11111111
60
20
AL
10megU
~~lrF.
105
Vs=
f - FREQUENCY (Hz)
3.0
107
125
2.0
I
1.5
1.0
0.5
V-=-lSV
.......
-
VGEN=+5V
2
o
~
5
CD
3:
I
....
-2
VGEN =
-.
c
a
~
-
"D
2
CD
>C
CD
0
..
2
~EN=2.4V
4
r--..
-
::::I
II
2
?"
J_ V+=+15V
.......
2.5
iil
:
71~~~S
106
""~
~
VGNO=O,VEN=O
CLOAO =
3.5
it:
111111111
v+ = +15 V. v_=I_~51~11I1I
4.5
4.0
i'a:li
a:
r-
105
Power Supply Current
vs Temperature
.s....
..... 111111
40
85
T - TEMPERATURE '"C)
;;
l~ !IWI,,-
0
0
I
65
45
2
5.0
80
J>
4
-50
100
~
~
l1li
5
OFF Isolation vs Frequency
5
§l
10
5
V+" +15 V
V-:c-15V
12S'"C
1
S
LOGIC INPUT
2
I
Z
:>
IO(off) and IOlon) vs Temperature'
VIN - LOGIC INPUT VOLTAGE (VOL lSI
:s
PF
~
9
]:
I'5
o
;;
I
cL
.,
_SSDC
i'a:li
00
0
If R GEN , RS ' or C L i, increased, there will be
proportional increases in rise and/or fall RC
times.
.,5
.,2
VOUT
OG508
"
O·'IB
V+ ANDV- POWER SUPPLY VOLTAGE (VOLTS)
""....
~
'S65
RGEN = 100 n
15
!~ 1°'~~~bX]
l=
@
I
.z
:>
'4
0
IS(off) vs Temperature'
~~
:1:
:aa:
VI
'S32
"::"
-15 V
10
Q
Vo - DRAIN VOLTAGE (VOL lS)
Va - DRAIN VOLTAGE {VOL lSI
2.0
-5
•C
'I
O-V+=+SV.V-=-8V
0
-15
~
c
I--H'-l-t~ =~:: :~~~: ~=: =~~ ~
100
o
-15V
RS"100U
.....
A - V+ - +15 V.
100
+lSV
v
ge
C
Q
VI
cuit for DG509).
'oo~flElm
V+ - +15 V
V
z
0
switching transients in this circuit (similar cir-
V EN " 0
v
I
I
VGEN=-5V
6
-
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
0
5
-1 0
1ft
I I
I I
~GEN:,-jOV l - I-- I-I I
-1
t - TIME (,uSee)
*The net leakage into the source or drain is the n-channel leakage minus the p-channeJ
leakage. This difference can be positive, negative, or zero depending on the analog
voltage and temperature, and will vary greatly from unit to unit.
Siliconix
4·19
SCHEMATIC DIAGRAM
Typical Switch
Typical Logic Interfaca
V+ (SUBSTRATE)
(+SUPPLV)
V+
D
t--+--I---"""1 AD
CHM
{D:le~
D:le~ 1-t------4..;
9
v-
DECODE
AND
SWITCH
DRIVE
EN'
GND
(CMOS LEVELSl
GND
SWITCHING TIME TEST CIRCUIT
V(-SUPPLYI
+2.4 V
+15 V
V+
S1
0.8
""
THRU
~~~ ...-----1.,
OG508
57
Sa
SWITCH OUTPUT
VD
(SEE FIG 11
SWITCH
1--o~---....oOUTPUT
VD
1M!!-::-
0.8 Vsa
Vsa
Figure 1(a)
ttranSttlon
-~
SBON
S10N
+2.4 V
+15 V
I'.PF
APPLICATIONS
v+
Positive
Supply
Voltage
(V)
a
Application Hints'
vNegative
Supply
Voltage
(V)
V IN
Voltage
V INH MinI
V INL Max
(V)
Vs or
Vo
Analog
Voltage
Range
(V)
Logic Input
Q
VI
o
co
"Application Hints are for DESIGN AID ONLY, not
guaranteed and not subject to production testing.
+15**
-15
2.4/0.8
-15 to +15
•• Electrical Characteristics chart based on V+ = + 15 V,
V-=-15V.
+12
-12
2.4/0.8
-12to+12
***Operation below ±8 V is not recommended due to the
+10
-10
2.4/0.6
-10 to +10
-8
2.4/0.4
-8 to +8
a
Q
VI
o
•
shift in V1NL(MAX)'
+8***
Logic Inputs
Logic input circuitry protects the input MOS gate from static transients. A series MOS device shuts off when V I N exceeds
the positive power supply. Negative transients are clamped to ground by a diode clamp.
The input voltage characteristics have a current spike occurring at the transition voltage when the logic goes from VINH
to VINL. If a series resistor is used for additional static protection, it should be limited to less than 9.1K .\1 to insure
switching with worst case current spikes.
Truth Table
MUX
SEQUENCE
RATE
a
1
1
1 ""Ioe
2pul.e.
ENABLE
0
G
5
0
9
1
MUX INPUTS
OG50BSWITCH PAIR STATES
(- DENOTES OFF)
54
55
57
53
56
AO
Al
A2
51
52
0
x
x
x
-
0
0
o·
- - -
0
ON
-
1
0
0
-
ON
0
!
0
-
-
- - -
3
4 pulses
1
1
C
- -
1
0
0
1
-
-
1
5 pulses
1
0
1
-
-
-
-
-
-
-
flU'....
1
1
6 pulses
0
1
1
1
7 pulses
1
1
1
-
1
8 pulses
0
0
0
ON
-
ON
-
ON
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ON
-
-
-
-
ON
-
-
-
-
-
ON
-
-
-
-
ON
-
-
-
-
lEI
Differential 4 Channel Sequential Mux/Demux.
8 Channel Sequential Mux (Demux)
+15V
+15V
sa
-
J>
-15V
::I
-
-15V
D
o
-~[
INPUT
(OUTPUTS)
+15V
CD
4
5,
5 5
6
2
53
7 5
12 4
11 55
DIFFERENTIAL
ANALOG
INPUTS
(OUTPUTS)
ANALOG
OUTPUT
(INPUTS)
DIFFERENTIAL
ANALOG
] OUTPUTS
(INPUTS)
10 56
57
9 5.
CD
>C
CD
v+
0.
·'N
Oc
DM7493
NC
A'N
9
~'5V
VI
10
Co 12
14
°A
13
--....
-
"a
AD
CLOCK
'N
I
c
NC
a
14
12
7 J
IN
a
1/2 MM74C73
1/2 MM74C73
CLOCK
CLOCK
CLOCK
_ 13
a
NC
10 K
CLEAR
--l
EN~BLEo-_ _""'_ _ _ _ _ _ _ _ _ _ _ _ _
a•
(MUX ON-OFF CONTROL)
E~!:~~o-----~--------------------~------~
Siliconix
4-21
DG50a DG509
.l>-
i\,
+15V
»
Industrial Control Multiplexing
Thermistor Multiplexer
I\)
Transducers
-15V
"r"
Monitor
Multiplexer
C')
~
+V
o
:2
o=jS'A
C/)
(=)
TEMP
o
....
:I
SZA
INSTRUMENTATION
DA
~
AMPLIFIER
OA'
STRAIN
S3A
OG509
VD
v
SONIC
OPTIC
INTERFACE
AND
DECODE
.,
L!._
-6
DG50B
VREF
6
DB ,-
POSITION
-15V
J
VELOCITY
VOLTAGE
CALIBRATE
S,.
Control Output
m
DG509 Thermocouple Multiplexer
0'
o
-15V
EN
J
)C'
LOGIC
INPUTS
MATERIAL "A"
--, ~rs'A
;Al"B"
TC1~
8 Input Sample-and-Hold
TCZ~
-15V
+15V
SZA
.1
TC3'LAJ\_J'o. A -
00508
RS+
30au
D~
VOUT
~
'Z
s,.
OG509
SZ.
I
D.
CHOLO-r
16 115 12
CHANNEL {
• The ac~uisition time and droop rate
depend on the size of the hold
capacitor and the characteristics of
the buffer amp.
,.
S3.
HIGH = SAMPLE
LOW = HOLD
~~p~; 0 - - - - - - - - '
greater than 300 n or the analog
signal range is restricted to less
than ±5 V, RS may be omitted.
I
r ---1
R
-::-
OR
r ---- i
I
S4.
I
"A"
I
I
SELECT
+ If the signal source impedances are
V
L-
11
IN8
+15V
S4A
TC4~
IN,
MATERIAL
"A"
S3A
LOGIC
INPUT
"s"
I
I
I
I
COPPER
0
I
L ____ ---1
CONSTANT
TEMPERATURE
COPPER
~
"g
r(=)
»
-I
o2
An 8 Channel Mux/Demux System
en
no
-15V
:::I
-15V
".
Co
OUT
S,
S,
5
~
• S2
7 S3
S4
12
INPUTS ~
DI"
OG508
\\
olD
DG508
11 85
10 56
9 S7
So
AO
""""Ti
~
5('
A2
EN
AO
+1SV
16 115 12
A,
IN
y::-:+
1
14
EN
+5V
+15V
+15V
CLOCK
A2
1- 11. 115 12
+5V
0'
0
J
A,
~12
+15V
10K
A 12
BDIN
2N4402
B 9
MM74C90
C
5K
"91
I
V..l
"l;t;! •.:" ...... "Ul
0, 02 03 04 05 06 07 08
10K
D,
I
L _______
Ne
/-
L---------I';r:;~~
08
°
11
"U4! 0
---TRANSMITTER- - - - - - - - -
-=-
_L ___ - - - - - -
--
--AECEIVER------------.J
..,.
~
s.Jaxaldlllnw 60lDUY
II
60S90 80S90
DG508 DG509
"""
N
~
"""
"
r(")
~
Differential Mux/Demux System
-f
o
2
en
-15V
+15V
'~I
m
:J
SC'
S1A
b~
7
13
S3A
S4A
DG509
S'8
12 S2B
--------------===~\~\==============--_l
081"'--------I
'N
V+
14
VOUT
'I
\5 - - - - - - - - - - -
11 SaB
10 S4B
AO
A, EN
16 12
+15V
+5V
~llJ
+15V
CLOCK
::::I
'I
+5V
ir
o
5
6 S2A
no
...c:
+lSV
+15V
10K
A~NC
A'N
IJ'
2N4402
MM74C90
10K
CLOCK
/
-=-
-=-
1
_ 13
o
Ne
10
CLOCK
-l
KaNe
1+15~
'N914
~------------_ib*I--_r~·
+5V
GNO
L
_________
01020304
01 0 203 D4
-TRANSMITTER- -
MM74COO OR CD4011
I
-=-
-
-
-
-
-
-
-
L -
-
-
-
-
-
-
-
-
-
-
_
-RECEIVER- _ _ _ _ _ _ _ _ _ _
J
8-Channel/Dual
4-Channel CMOS
Analog Multiplexer
H
Silicanix
BENEFITS
•
•
designed for•••
Easily Interfaced
() TTL, DTL and CMOS Direct Control
Over Military Temperature Range
Low Power
o 30 mW Typical Quiescent Power
•
• Data Acquisition Systems
•
Reduces System Cross-Talk
o Break-Before-Make Switching Action
Environmentally Rugged
o Latchproof PLUS-40 CMOS
o 44V Power Supply Maximum Rating
o Static Protection Circuitry on all Inputs
• Multiplexing Reference Signals
• Communication Systems
DESCRIPTION
The DG508A a single ended 8 channel analog multiplexer connects 1 of 8 inputs to a common output decoded from 3 binary
inputs (AD, A 1, A 2 ).
The DG509A a differential input 4 channel analog multiplexer connects 1 of 4 differential inputs to a common differential
output decoded from 2 binary inputs (AD, A 1 ). In the ON state each switch conducts current in either direction, and in the
OFF state blocks voltage up to the power supply rails, generally 30 volts peak-to-peak. Bidirectional current switching also
insures equal operation as a demultiplexer. An enable (En) ,input provides a package select function. All control inputs
address (Ax) and enable (En) are TTL or CMOS compatible over the full operating temperature range of the product. The
multiplexers operate in a Break-Before-Make (BBM) switch action between any two decoded switch selections protecting
against momentary shorting of the input transducers. Additionally BBM action occurs between package selection. See the
DG528 and DG529 for the same function plus latches on the A 2 , A 1, AD, En inputs.
FUNCTIONAL DIAGRAMS
III
J>
v-
v+
113
C>
4
5
6
7
12
11
10
9
0--
v+
Gnd
13
-1~
r---o-
.
flo
I
....-:1
,I
I
I
I
I
I
I
I
I
I
:
I
I
,
I
I
I
I
I
I
,I
I
I
I
I
I
I
I
:
:
b15
b16
bl
AO
~0
I
I
I
I
I
I
I
I
DG508ACMOS
DECODE LOGIC
I
:s
a
o
ca
-
Gnd
114
~
~i
v-
51a
52a
53a
S4.
Slb
52b
53b
54b
4
5
6
7
13
12
11
10
~
I
I
I
Da
.-.3:
I
I
I
~
I
I
I
I
c
Db
-
"D
CD
DG509A CMOS
I
>C
CD
U1
F
DG50BA
8 Channel Single Ended
Multiplexer
DG509A
Differential 4 Channel
Mu Itiplexer
Silicanix
4-25
C
0-
PIN CONFIGURATIONS
0
1ft
Flat Package
"a
C
10
0
. Flat Package
AO
A,
Au
En
A2
En
v-
Gnd
v-
v+"
S,
v+"
So
S2.
S2b
S.
S3.
1ft
"a
A,
S'b
Slb
S,
"'b
Db
S8
TOP VIEW
TOP VIEW
ORDER NUMBER:
DG50BAAL
SEE PACKAGE 17
ORDER NUMBER:
DG509AAL
SEE PACKAGE 17
·Common to Substrate and Bese of Package
Dual-In-Line Package
Dual-I n-Line Package
"
TOPVIEW
TOP VIEW
V+ COMMON TO SUBSTRATE
V+ COMMON TO SUBSTRATE
ORDER NUMBERS:
DG50BAAK, DG50BABK or DG50BACK
SEE PACKAGE 10
DG50aACJ
SEE PACKAGE a
ORDER NUMBERS:
DG509AAK, DG509ABK or DG509ACK
SEE PACKAGE 10
DG509ACJ
SEE PACKAGE a
TRUTH TABLES
DG60BA
DG509A
A2
A1
AO
En
ON
SWITCH
X
X
X
0
NONE
AD
En
ON
SWITCH
X
X
0
NONE
0
1
1
A,
0
0
0
1
1
0
0
0
1
1
2
0
1
1
2
0
1
0
1
3
1
0
1
3
1
1
1
4
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
a
Logic "0" = VAL" o.av, Logic "1" = V AH" 2.4V
4-26
Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to V-
Storage Temperature (A & B Suffix)
(C Suffix)
Power Dissipation (Package)'
16 Pin DIP"
16 Pin Plastic DIP'"
Flat Package····
V+ . . . . . . . . . . . . . . . . .. . . .............. 44 V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Digital inputs4 , VS, VD········· -2 V to (V+ +2 V) or
20 mA, whichever occurs first.
Current (Any Terminal, Except S or D)
30mA
Continuous Current, S or D
20mA
Peak Current, S or D
(Pulsed at 1 msec, 10% Duty Cycle Max)
40mA
Operating Temperature (A Suffix).
. -55 to 125°C
(B Suffix) .
-20 to 85°C
(C Suffix).
o to 70°C
-65 to 150°C
-65 to 125°C
900mW
470mW
750mW
• All leads soldered or welded to PC board.
"Derate 12 mWtC above 75°C
"'Derate 6.3 mWtC above 25°C
····Derate 10 mWtC above 75°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
NO.
MEASURED TESTS
TERMINAL
PER
TEMP.
CHARACTERISTIC
,
-
VANALOG
2
-
Minimum Analog Signal
Handling Capabilitv
Drain·Source
3
15
I6
1---;-
w
ON·Assislance
6rOS(onl
Greatest Change In Crain
Source ON Aesistance
Between Channels
ISloffi
I
Source OFF
SIO 0
I~H
:2:
9
:!:15
:!:15
400
400
500
450
450
550
8
230
400
400
500
450
450
500
8
6
8
0,002
'2
1-
1010n)2
'3
I~~
'9
20
-D
2' V
-N
22 A
-M
23 I
'AH
24
%
"
:!:50
,5
t50
VS=-10V,VO=10V
i20a
:t20
:t200
VO""0V,VS .. -l0V
I -0.015
,'0
:!:200
±20
±200
Vo '" -lOV, VS· 10 V
VEN = 0
0.005
±10
±100
,20
dOa
2 -0.008
,'0
"00
,20
,'00
VO=-10V.VS=10V
0.Q15
dO
±200
±20
±200
VSfall) = VO" 10 V
8 --0.030
,,0
,200
±20
:!:200
VSlall)
=
VO" -10 V
8
0.007
±10
±100
±20
:dOO
VSla1i1
=
Vo '" 10 V
8 -0.015
,'0
±10Q
±2D
il00
VSla1l1
=
Vo '" -10 V
-C
CD
.
Vs = 0
pF
VEN· 0, f· 140 kHz
VO" 0
DG509A
Negative Supply Current
V-
Positive Supply Current
V+
Negative Supply Current
V-
,
2.4
UI
2.4
VEN = 2.4 V
-1.5
-0.7
-1.5
1.3
2.4
2.4
-<).7
-1.5
-1.5
All VA "0, or
mA
2.4 V
VEN = 0 V
NOTES:
1. Typical Values are for DESIGN AID ONLY, not guaranteed and not subJect to production testing.
2. 'Olonl is leakage from driver into "ON" switch.
ICMG·A
ICM
a
o
ca
i
c
VEN =0
"'
1.5
'.0
,
1+ Standby
3. OFF .solation .. 20 log
=
See Figure 1
0.2
,
"A
VA
SeQuence each sWitch on
VAL = O.B V. VAH = 2.4 V
AIIVA=O
0
1-
--...::::.. L
30 V 1- Standby
MIN)
VS'"10V,VO"'-10V
0,010
OG5Q9A
Drain ON
Leakage
IV AL" 0.8 V, VAH" 2.4 V
rOSionl AVE
t50
D
L.eakage
Current
ISequence each sWitch on
(rOSIOn) MAX - rOSion)
,5
IAL
25
-200~A
Vo = -10 V, IS = -200 /JA
.drOS(on) =
-c
-
VO= 10V,IS"
±50
,
'4
I~'
'6 N
1-.
n
OG508A
Current
1-
V
"
tl0
8 -0.005
8
I~
-
t15
270
S
l.eakageCurrent
Drain OFF
IOfoffl
!15
8
TEST CONDITIONS, UNLESS NOTED:
V+ '" 15 V. v- .. 15 V. Ground = 0
UNIT
-10V" VS" 10V
T
I-c
-20/
85/
-5"C 2SoC 125°C O'C 2"C 70°C
S to 0
rOSlon)
S
25°C
!15
14
MAX LIMITS
ASUFFIX
BlC SUFFIXES
TYP'
4·27
C
00
SWITCHING TIME TEST CIRCUIT
~
0
+2.4 V
+15 V
Q
3V
LOGIC INPUT
t r <20ns
tf<20ns
C
CO
50%
0
~
0
Q
SWITCH
OUTPUT
LOGIC
INPUT
-=-
SWITCH OUTPUT
Vo
Vo
50
n
1M
n
(SEE FIG. 1)
135PF
TRANSITION
TIME
-=-
-=-
-=Figure 1(al
+2.4 V
0
+15V
a. 1Vo
SWITCH OUTPUT
Vo
(SEE FIG. 21
ENABLE ~12~l/tIOFFI 0.' Vo
Vo
Vs
SWITCH
OUTPUT
SWITCH
VOb
OUTPUT
V
ISEE ,!lG.31
1
-=-
35PF
-=-
-=-
-=-
OPEN TIME
Vs
50%
OV
(B.S.M. INTERVAL)
'oPEN
Figure l(bl
+15 V
v+
S,
EN
Ao
S2
CGSOBA
THRU
50
A,
-=-
SWITCH
OUTPUT
LOGIC
INPUT
Vo
1Kn
I
35PF
Figure 2(al
+15 V
+15
+2.4 V
v
V+
EN
S'b
All SAND Da
S'a THRU
S4a,Da.
AO
S2b'
8a:bo S4b
-=-
OG509A
DG509A
SWITCH
OUTPUT
VOb
GNO
50
Vo
n
'K
l35PF
-=-
-=-
-:;-
Figure 2(bl
4-28
-=-
-=-
1
35PF
-=Figure 3
Siliconix
SWITCH
OUTPUT
AO. A,. (A 2 1
LOGIC
INPUT
1Kn
-=- -=-
+5V
CGSOBA
a-Channel and
Dual 4-Channel
Latchable Multiplexers
• Microprocessor Bus Compatible
o Accepts 300 nsec WRITE Pulse Width
o Direct RESET
•
designed lor . . .
•
•
•
•
H
Data Acquisition Systems
Automatic Test Equipment
Communication Systems
Microprocessor Controlled Systems
Siliconix
BENEFITS
Environmentally Rugged
o 44V Power Supply Rating
o Static Protected Logic Inputs
o Latch-Proof
•
Easily Interfaced
o TTL Compatible Without Pullup Resistors
VINH = 2.4V
•
Improved System Accuracy
o rDS(on) <400n
o Verror=80f..!V Max at 125°C
= ID(on) X rDS(on)
o t.rDS(on) Channel to Channel is Less
DESCRIPTION
Than 6%
The DG528 and DG529 designed on the Siliconix PLUS-40 CMOS Process provides solid state switch action with 400
ohms contact (ON) resistance and very high OFF resistance. True bidirectional switch action takes place over the full analog
signal range of ±15 volts, with break-before-make operation to prevent momentary shorting of signal inputs. The DG528
provides 8-channel single-ended mUltiplexing and demultiplexing of ±15 volt analog signals. The DG529 provides 4-channel
differential multiplexing and demultiplexing of ±15 volt common mode plus differential mode signals.
Four input latches on the binary coded switch-state inputs (AO, A1, A2, En) result in microprocessor bus compatibility.
Two control lines, WR and RS, store or clear the the switch-state input (AO, A1, A2, En) latches. Programming the enable
input (En) latch with a logic zero turns all analog switches OFF. The direct chip reset RS simplifies switch turn OFF during
system power up or system reset.
FUNCTIONAL DIAGRAMS
DG528
v+
v-
v+
GNO
s,~4-----------------------~
S,.
S20-~------------------~Y
S2.
DG529
v-
III
GND
J>
::I
a
o
-
D,
S3~4-----------------~
S3.
~~~------------~
S..
550·~13~--------~y
56~124-______~1 A-~~--~--7-~~
0
o-+----<:r
~
.---..
c
14
S,b
13
S2b
Db
12
II
57
ca
S3b
•
~
CD
11
S4b
CD
~
WR 0 - 4 - - - - - - - - /
8 Channel Single Ended Multiplexer
Differential 4 Channel Multiplexer
Siliconix
4-29
PIN CONFIGURATIONS
DG528
DG529
Dual-In-Line Package
Dual-I n-Line Package
Top View
Top View
ORDER NUMBERS:
DG52BAK OR DG52BBK
SEE PACKAGE 23
DG52BCJ
SEE PACKAGE 19
ORDER NUMBERS:
DG529AK OR DG529BK
SEE PACKAGE 23
DG529CJ
SEE PACKAGE 19
TRUTH TABLES
DG529
DG528
A2
A,
AO
En
WR
X
X
X
X
S
X
X
X
X
X
AS
0
On Switch
4·30
X
0
0
X
0
,
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
On Switch
Ao
En
WR
X
X
X
S
NONE
X
X
X
X
X
0
0
X
0
0
0
0
NONE
0
2
0
0
3
4
(latches cleared)
X
0
0
0
0
AS
A,
Maintains previous switch
condition
,
NONE
2
3
4
5
6
7
B
Maintains previous switch
condition
0
NONE
(latches cleared)
,
0
Logic"''': V AH ;>2.4V
Logic "0": VAL <;; O.BV
Siliconix
,
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
(A Suffix) -55 to 125°C
(B Suffix)
-20 to 85°C
(C Suffix)
o to 70°C
Storage Temperature (A & B Suffix) -65 to 150°C
(C Suffix)
-65 to 125°C
Power Dissipation (Package)'
18 Pin DIP"
..................... 900mW
18 Pin Plastic DIP*** ............... 470mW
Voltages referenced to VV+ . . . . . . . . . . . . . . .
GND . . . . . . . . . . . . . .
Digital inputs 5 • VS. VD·
Operating Temperature
. . .. . . . . . . . . . . . . . 44 V
. . .. . . . . . . . . . . . . . 25V
.. . .... -2 V to (V+ +2 V) or
20 rnA. whichever occurs first.
Current (Any Terminal Except S or D) .... 30mA
Continuous Current. S or D ............ 20mA
Peak Current. S or D
(Pulsed at 1 msec. 10% Duty Cycle Max) . 40 rnA
• All leads soldered or welded to PC board.
"Derate 12 mWfC above 75°C.
"'Derate 6.3 mWfC above 50°C
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC
ELECTRICAL CHARACTERISTICS
parameters and high and low temperature limits to assure conformance with specifications.
Measured
Terminal
Characteristic
No.
T"",
Pa.
ramp.
,
Max Limits
TVp
Nota1
Test Conditions, Unless Noted:
ale Suffixes
A Suffix
25~C
-5SoC
2SoC
125°C
-20"C
o"C
25°C
osoe
MlOlmum Analog Signal
VANALOG
12
1-,
"5
±IS
t1S
±IS
8
270
400
400
500
450
450
550
8
230
400
400
SOO
450
450
500
8
6
±IS
Handling Capability
Dram-Source
5100
'OSionl
ON Resistance
.o. r0510nl
Source ON ReSistance
Between Channels
1-
V
n
Greatest Change 10 Drain
4
I - Sw
I--=- 1
6
1-,
1---.
1--.
1-;0
1--;;-
T
C
ISloft)
H
'Oloffl
1-----,;-
1---;3
1----,.;
I~
'6
1010ni
S10 0
Source OFF
Leakage Current
Oram OFF
Leakage
Current
OrainON
Leakage
Current
Note 2
-
S
OG528
0
OG529
-
OG528
0
OG529
,
'AH
Logic Input Current,
Input Voltage High
N
p
1- U
'8 T
'AL
Logic Input Current,
Input Voltage Low
ttransition
SWitching Time 01
MUltiplexer
0
topen
Break-Belore-Make
Interval
0
tonlEN, WR}
Enable Turn-ON Time
0
toiIIEN, AS)
Enable and RS Reset
Turn-OFF TIme
0
a
Charge Coupling
0
117
,.
120 D
i-v
2' N
_A
22 M
-I
23 C
-
24
S
25 U
p
p
L
V
----;e
-T,
----;e
---;g
V+ .. 15. V- .. -15. Ground .. a
WR = 0, As = 2.4V
Unit
OFF Isolauon
Note 3
em
LogiC Input
Capacitance
CSloffi
Source OFF
Capacitance
COloff)
OramOFF
Capacitance
"
1-
AD, At, IA21,
En,WR,
As
0
S
OG529
0
Positive Supply Current
V.
Negative Supply Current
V-
tt.rOS(onl"
rOSlon}
,5
.so
V '" 10V, Vo '" -lOV
,50
Vs = -10V, VO" 10V
"0
.t200
.t20
:1:.200
VO=10V,VS=-10V
-o.D15
"0
:t200
<20
:1:.200
Vo - -10V, Vs = 10V
-0.008
"0
:1:.100
,20
:1:.100
Vo = lOV, Vs - -10V
-0.015
2
"
"
oA
2
-0.008
,'0
:1:.100
,20
:1:.100
8
-0.03
"0
:t200
'20
t200
VSlall} = Vo = 10V
B
-0.03
"0
:1:.200
:1:.20
:1:.200
VSla111 = Vo - -lOV
8
-0.015
,'0
t100
,20
<100
VSla1i1
VSlaIU"' Vo = -10V
8
-o.Ot5
<10
:tl00
.20
:1:.100
516'
5 (6)
-0.002
"0
-30
-'0
-30
0.006
'0
5161
-0.002
-'0
,
,
,
06
0.2
1.0
0.4
30
-30
10
30
-'0
-30
.A
,
,
,
2
Vo = -10, Vs = 10V
VD
10V
Sequence each SWitch on
VAL" o.av, VAH" 2.4V
~
::::I
D
VA = 15V
VEN = 0
All VA = O,WR =0, AS= 0
.
~
See Figure 5
,
,
"'
c
-.-
See Figures 4 and 6
See Figure 4 and 7
68
pC
See Figure 8
dB
VEN '"-O,AL ·'Kn,cL ""15pF
Vs .. 7 VRMS, I = 500 kHz
"CD
>C
CD
1= 1 MHz
5
pF
Vs "0
VEN"O,I-140kHz
25
U1
VO=O
'2
2.5
2.5
-1.5
-1.5
NOTES:
1. Typical Values are for DESIGN AID ONL V, nOl guaranteed and
not subject to production testing.
2. 'Olon} is leakage from driver into "ON" switch.
3. OFF i50lation=20 log IVsl, VS"lnput to "OFF" SWitch, VO=
output due to VS'
IVol
4. Period of Reset (AS) pulse must be at least 50 ,usec dUring or
after power ON.
5. Signals on Sx. Ox or 1NX exceeding V+ or V- Will be clamped by Internal diodes. Llm,t lorward
diode current to maximum current ratings.
Siliconix
mA
VEN =OV
-
o
ca
See Figure 3
2.5
8
VEN =0
VA = 2.4V
,
4.0
8
AVE
-lOV';; VS" 10V
.s
-0.005
Sequenco each sWitch on
I VAL =O.SV, VAH =2.4V
('DSIOO,MAX -'DSIOO,MIN)
,50
-0.005
,
,
En. WR, AS
0
Vo =-10V,IS--200IJ,A
.so
8
B
AO. A,. (A21
OG528
"
Vo = IOV, IS = -200 IJA
AIIVA=O
ICML-A DG528
ICML-B DG529
4-31
.",
"
1ft
TIMING DIAGRAMS
o
a
Minimum Input Timing Requirements
co
Parameter
"
1ft
o
a
Min Limits
over full temp range
Measured Terminal
tww
WRITE Pulse Width
WR
300
31
tow
A. En Data Valid to WRITE
(Stabilization Time)
AO. Al. (A21. En
WR
180
32
two
A. En Data Valid after WR ITE
(Hold Time)
WR
AO. Al. (A21. En
30
33
tRS
RESET Pulse Width
RS
30
Unit
Test Circuit
ns
See Figure 1
See Figure 2
500
Vs; 5V
Note 4
3Vl
1
1.5V
Figure 2.
Figure 1.
SWITCHING TIME TEST CIRCUITS
LOGIC INPUT
t r <20ns
tf<20ns
0.8
SWITCH OUTPUT
Vo
3:L
50%
o
~~;".-\
I~
lal
0
+2.4 V
!
O.B VSB
VSB
r---.....f
i1"'-
ltransition-I
S, ON
1-
-
-
~ransition
S80N
1rO_
AO
r -.....---4>-<>--I A,
LOGIC
INPU~
GNO
;0 n
iiiiR
4-32
Siliconix
SWITCH
VOb
i-J_-r_:"-""';;';':""'-j,"'5V-.J'M n ~ 135 pF
L";;
Ibl
Figure 3. Transition Time Test Circuit
1
0bl--<>1___......-o OUTPUT
v-
a
..
SWITCHING TIME TEST CIRCUITS (Cont'd)
Q
VI
~
2.4V
a
v
+15
Q
VI
-5 V
~
-0
S2
THRU
AD
Sa
A,
':'
OG528
SWITCH
OUTPUT
VOb
0
3V
LOGIC INPUT
t r < 20 ns
tf<20n5
50%
lK n
':"
-
':"
'::'
':"
':"
I
35PF
(al
-toff(En)
O. 1VO
SWITCH OUTPUT
Vo
2.4V
O•• VO
Vo
-5 V
Vs
S'a THRU
AD
54a. Oa.
S21y S3b. S4b
':"
OG52.
SWITCH
OUTPUT
VOb
LOGIC
INPUT
n
':"
lKn
':"
':"
':"
':"
I
35PF
III
{bl
Figure 4. Enable tonftoff.Time
:a::::a
-
Q
0
CD
.-_.
i
+15 V
+2.4 V
lOGIC INPUT
t r < 20 ns
C
3V
50%
-
V+
tf< 20 ns
EN
AS
SWITCH OUTPUT Vs
Vo
80%
OV
t
Iv
ALL 5 AND Da
+5V
DG528
OG52.
SWITCH
OUTPUT
Vo
I-
lK
1
35PF
'oPEN
':"
':"
':"
-=
Figure 5. Open Time {B.B.M. Intervall
Siliconix
4·33
'a
CD
>C
CD
..
.,.
=:
SWITCHING TIME TEST CIRCUITS (Cont'd)
1ft
o
Q
10
C"'4
1ft
+15V
+2.4V
oQ
V+
S10R
SIb
REMAINING
SWITCHES
3
WRl.5~~
F
'oniwRr--.j
r;;;o
SWITCH
_ _ _....;.._ _ _ _ _ _ _...
OUTPUT OV
Vo
DEVICE MUST BE RESET PRIOR TO
APPLYING WR PULSE
...-----0--1 R!:
DG528
DG529
SWITCH
°b' D 1--<>.........-0 OUTPUT
Vo
r---<>-IWR
LOGIC
INPUT
lK
-=
135PF
Figure 6, Write Turn·On Time ton(WR)
+15V
V+
S10R
SIb
iiSl.~~~
F I
OV
Ao- A" IA2)
'o"IRS)
DG528
DG529
3j..0.8Vo
SWITCH
OUTPUT
Vo
REMAINING
SWITCHES
1'-
SWITCH
r---<>-I RS
1--<>.........-0 e~TPUT
Figure 7. Reset Turn·Off Time toff(RS)
+15V
AO,Al,
IAZ)
RGEN
Sx
DG5Z8
DG529
r~~~T~
VGENI
.....-;---;r---Vo IS THE MEASURED VOLTAGE ERROR
DUE TO CHARGE INJECTION. THE ERROR
VOLTAGE IN COULOMBS IS Q=CLX!>Vo.
DETAilED DESCRIPTION
The internal structure of the DG528 and DG529
provides a 5 volt logic interface with input protection circuitry followed by a latch, level shifter,
decoder and finally the switch constructed with
parallel Nand P channel MOSFETs (see figure 9).
Following the latches the Ox signals are level
shifted and decoded to provide proper drive levels
for the CMOS switches. This level shifting insures
full ON/OF F switch operation for any analog signal
present between the V+ and V- supply pins.
looking at figure 9, the input protection on the
logic lines AQ, A" A2, En and control lines WR,
RS minimize susceptibility to static encountered
during handling and operational transients.
Power Supplies
The final data sheet will provide graphs showing
the effect on power supply sensitive parameters.
The logic interface circuit compares the TTL input
signal against a TTL threshold reference voltage.
The output of the comparator feeds the data input
of a D-type latch. The level sensitive D latch continuously places the Dx input signal on the Ox
output when the ClK (WR) input is low, resulting
in transparent operation. As soon as ClK (WR)
returns high the latch holds the data last present on
the Dx input at the Ox output, subject to the
"Minimum Input Timing Requirements" table.
r-------------------------------------------------~~--------------~V+
. . . - - ' - - - - . TTL THRESHOLD
VOLTAGE
COMPARATOR
INTERFACE
00
•
•
•
an
•
•
LEVEL
SHIFT
•
.........---H----<> 0
------- -c" .-..
4...----+----<> s,
~--
ClK RESET
J>
~
DECODE
4WIOE
lATCH
l1li
a
-
o
CD
i
c
L---------*---------*-----------------oV-
-
VI
Figure 9. DG528 Simplified Internal Structure
Siliconix
-.
"'D
CD
>C
CD
4·35
APPLICATIONS
The DG528 and DG529 minimize the amount of
interface hardware between a microprocessor system
bus and the analog system being controlled or
measured. The internal TTL compatible latches give
these multiplexers memory, that is, they can be
programmed to stay in a particular switch state
(e.g., switch 1 ON) until the microprocessor determines it is necessary to turn a different switch ON
or turn all switches 0 F F.
The input latches become transparent when WR is
held low; therefore, these multiplexers operate by
direct command of the coded switch state on A2,
A1, AQ. In this mode the DG528 is identical to the
very popular DG508 even sharing the same pin
locations. The same is true of the DG529 versus
the popular DG509.
Circuit Operation: (See Figure 10)
Initially during system power-up RS would be
active low maintaining all 8 switches in the OFF
state. After RS returned high the DG528 maintains
all switches in the OFF state. As soon as the system
program was ready to perform a write operation to
the address assigned to the DG528, the address
decoder would provide aCS active low signal which
is gated with the WRITE (WR) control signal. At
this time the data on the DATA BUS (that will
determine which switch to close) is stabilizing.
When the WR signal returns to the high state,
(positive edge) the input latches of the DG528 save
the data from the DATA bus. The coded information in the AQ, A1, A2 and En latches is decoded
and the appropriate switch is turned ON.
The En latch allows all switches to be turned OFF
under program control. This becomes useful when
two or more DG528s are cascaded to build 16-line
and larger analog signal input multiplexers.
+15V
)
DATA BUS
AO
A1
A2
EN
'":::J
'"w
:E
DG528
RS
RESET
f-
'">'"0c::
'"'"uw
0
c::
+5V
WR
WR'
-=
c..
ADDRESS
BUS
cs
D
-=
v-15V
Figure 10
4-36
Siliconix
1 OF 8
ANALOG
OUTPUT
Monolithic 8-Channel
Multiplex Switch with Decode
designed for . . .
BENEFITS
• Multiplexing Analog Signals
•
-.
CIt
H
W
Siliconix
.....
o
VI
Reduces External Component Requirements
o On Board Decoding
o Internal Zener Diodes Protect MaS Gates
• Minimizes Channel Cross-Talk Problems
o Break-Before-Make Switching
DESCRIPTION
The Si3705 is designed to function as a single-pole, 8-position (plus OFF) electronic switch. The function is implemented
by using eight P-channel MaS field-effect transistors as analog switches. In the ON state, each switch will conduct current
equally well in either direction, and in the OFF state each switch will block voltages up to 5 V peak-to-peak. The ON-OFF
state of each switch is controlled by drivers, which are in turn controlled by a 3-bit binary word plus an Enable-Inhibit
input. The truth table shown below indicates the binary word required to select anyone of the eight switch positions.
Logic input levels "L" and "H" correspond to positive logic "0" and "1". Assuming supply voltages of 5 and -20 V,
logic "L" .;;; 0.6 V and logic "H" ;;. 3.5 V. The rise and fall times of the drivers are designed to provide break-before-make
switch action.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
Dual-In-Line Package
-:I>
::I
a
1
ENo------t-r-r+-rt-+~+-~~-r+-+i
ORDER NUMBERS: Si3705142K, Si3705143K,
Si3705192K OR Si3705193K
SEE PACKAGE 10
o
CD
ORDER NUMBER: Si3705192P
SEE PACKAGE 12
3
D
.-_.
3:
c
tBoth V+ lines are internally connected, either one
or both may be used. V+ common to substrate.
-
"a
CD
>C
CD
TRUTH TABLE
LOGIC INPUTS
Siliconix
CHANNEL
AO
A1
A2
En
'ON'
L
L
L
H
S,
H
L
L
H
52
53
L
H
L
H
H
H
L
H
54
L
L
H
H
55
H
L
H
H
56
L
H
H
H
57
H
H
H
H
5a
X
X
X
L
OFF
UI
4-37
ABSOLUTE MAXIMUM RATINGS
...
V+ to V- .....
V+toVA, VEn.
V+ to VD or VS.
VD to VS· ....
VA,VEntoV-.
VD or Vs to V-
-0.3,35
-0.3,35
-0.3,35
±25
35
35
..
·.
·.
·.
Current (Any Terminal) ........ .
. ... -20 mA
'-65 to 150° C
Storage Temperature . . . ........
. -55 to 125°C
Operating Temperature (A Suffix).
(C Suffix) . . . . . . . . . o to 70°C
Power Dissipation* . .. ........... . . .. 900mW
* All leads soldered or welded to PC board. Derate 12 mWfC
above 75°C
V
V
V
V
V
V
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
-
1
2S
I- W
Drain-Source
ON Resistance
rOS(on)
3 I
I-T
4 HC ISlofli
,-5
150
200
150
200
225
300
400
400
400
400
-1
-100
Leakage Current
-8
Leakage Current
Input Current,
N IINL
ttransition
Switching Time
400
400
-3
-150
-500
-10
VO" 5 V
VO" 0
n
VO" -5 V
IS=-1 rnA
-142 and
-192 only
VS:: -5 V, Vo
-500
=5 V
"A
VAL" 0
See Switching Time Test circuit
VSl = ±1 V. VS8 =: +1 V, Vs2-7:: gnd
2.0
2.0
1.2 Typ*
1.2 Typ*
Turn·OFF Time
0.8 Typ"
0.8 Typ*
0.05 Typ*
0.05 Typ"
Source OFF
Capacitance
10 Typ'
10 Typ*
Drain OFF
Capacitance
20 Typ*
20 Typ*
175
175
Of Multiplexer
YEn = 0.6 V
Vo "-5 V. VS" 5 V
-1
Turn·ON Time
Break-Before-Make
Interval
10 N t open
1- A
11 ~ CSloff)
I-c
12 COloffi
113 Po
200
300
-1
Input Voltage Low
Ie ton
Ie
I-e toft
150
200
TEST CONDITIONS, UNLESS NOTED:
v-:::: -20 V, V+ c 5 V, YEn "" 3.5 V
VAL"" 0.6 V, VAH = 3.5 V
nA
Drain OFF
6 1
UNIT
S13705192/513705193
2SOC
70°C
O°C
150
200
Source OFF
10(011)
7
SI3705142/513705143
-5SoC
25°C 85°C
"'
See Switching Time Test Circuit
VSlall) "1 V
VS" VO" 5 V
YEn
pF
Power Dissipation
mW
=
0.6 V
f= 1 MHz
VO"5 V
V-"'-31 V,V+=O
IPAA
"Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be + or - as per
switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.
5V
S2
S3
S.
V S2 _7
50%
St
Sl
V
o--
.l.....-.l.....-A---
'.l.....--
S6
. .l.....--
58
VS8
AO1
INPUT~
"1 ±."oo~'
, V
QUTPUT_
VS(ALLl = +1 V
-',,~
90%
-
---topen
V S1 = -1 V
.l.....--
Vsa=+1 v
'0%
A---
A'l A21
r
+5V
V S1 =+1 V
Vsa= -1 v
Siliconix
I
~toff--
['0%
OUTPUT
OUTPUT
4·38
-j
ov
0
S5
5,
::----l
INPUT,
tr,tf< 20 ns
-2t:_
+y
V+
7
ttranSttlon
- - - Vo
~
7
r-VO
L:
'--VO
ttransltlon
TYPICAL CHARACTERISTICS
rOS(on) VS Vo
and Temperature
;;
g"
1000
V+"'+5V
V " 20V
w
"
~
iiiII:
ilw
u
II:
100
::>
g
+5V
--- -
t- I- +\25'~-
r- l-
25
"z
20
"
~
""
15
10
I
Z
C
II
I
10
-5 -4 -3 -2 -1
0
1
2
3
4
5
~
~~
Vo - DRAIN VOLTAGE (VOL IS)
Vi=J5V I
V-=-20V-
.3
2.5
RL = 1K
C L =30pF -
">=z
2.0
":;:
~
1.0
~
~
r-
toft
==
~
>=
0
1
2
3
4
5
V
0.1
2.0
-
..... - -
"
-;;
-,.
zo
;;>
."..
-20
25
45
65
85
105
1
.
E
II:
a:
......
il
~f
100
T - TEMPERATURE I'CI
I
I
I
-
90
80
~
70
--
lIo01lSS
60
S
50
~
~
~
0
40
30
-
a
o
I
a
I
I
.-.-
I
-60
-20
20
60
100
140
~
"
~>
c:
! 1 i
cl
~
w
T - TEMPERATURE lOCI
-2
"-
VGEN=OV
-4
I-
1=
::>
:
0
I
111111
::> -2
0
>
.
,
I-
Your
100n
CD
>C
CD
::>
-20 V
I
-4
VI
VGEN"'-1V
Rl "1K
z
0
i'o"RL
11
V GEN "'+1 V
-4
'IIIIII
II
~
;
-2
0
140
+5V
JJ
III
I
IjPUTS = 0 V
"OFF" Isolation vs RL
and Frequency
100
"-
V GEN =+5V
-2
~
I
60
125
V-"'-20V
A~L
I
20
IN
-2
0.01
§
vL+~v I I
t~n
o
-60
~
w
0"
-'I~
Supply Current vs
Temperature
Rt = lK
Cl =30pF
0.5
If RGEN. RL or CL is increased. there will
be proportional increases in rise and/or fall
RC times.
";;
Switching Time vs
Temperature
V-=-20V
Vo =+1 V
1.0
5
~~
z_ 0-'
T - TEMPERATURE (·CI
2.5
I
4
V
Vo - DRAIN VOLTAGE (VOLlSI
3.0
1.5
3
I stoff)
v~=15vl
~
~
~
'E
-5 -4 -3 -2 -1
":;:z
2
V
o
.3
1
A
l"""- I-
0$
..
0
1010ffi
1',
1.5
~
-1
IO(off)/IS(off) vs
Temperature
3.0
w
~
Vo - DRAIN VOLTAGE (VOLTS)
Vo
Switching Time vs
..
I---' ."..
esloff)
"
I I
II:
~ ."..
I-
55'C=
"
.,,/
w
~
g
~
OUTPUT
'---t--!-o-r-.--o
V+=+5V
V-=-15V
30
-20V
Vo
CO(off)' CS(off) vs
r-
-6
"-
......
-2
20
-4
10
-6
II
VGEN"'-SV
+5V
f - FREQUENCY (Hz)
+5V
"OFF" ISOLATION" 20 LOG 1Vour'
IVIN '
Siliconix
-8
-1
t-TIME (}lsi
4-39
SCHEMATIC DIAGRAM
~--~~~~~~~~~~~~~~~~~~~~~--~~~~~~~V
(NEGATIVE
SUPPLY)
ONo--__---+----+---+--, !o:!
J;
A2 o--~---+---'-t---,
V+
V+
(SUBSTRATE
":'" AND POSITIVE
SUPPLYl
LOGIC INPUT
r-+---+-__+---+-_-+----f---.--+-------------<>~~~p~;
4-40
Siliconix
H
Siliconix
Multi-Channel FETs _
Index
MULTI-CHANNEL FETs
Title
Gl15 ........................................................................................
Gl16.................. ......................................................................
Gl17 ........................................................................................
Gl18........ .................................... ............................................
Gl19..................................................................... .......... .........
Gl22 ........................................................................................
Gl23 ........................................................................................
Page
5-1
5-3
5-5
5-7
5-9
5-11
5-13
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) to devices without resulting in
permanent damage. This is a stress rating only and not subject to production testing. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.
Monolithic 6-Channel
Enhancement-Type MOS FET
Switch
designed for •
•
•
• •
Switching Analog Signals
Multiplexing
Q
H
..II
..II
SilicDnix
VI
BENEFITS
•
Reduces External Component Requirements
o Internal Zener Diode Protects the Gate
o Six Switches Per Chip
o Integrated MaS F ET for Each Gate to
Provide "Pull-Up" Current for GateDriver Circuit
DESCRIPTION
The G 115 contains six enhancement-mode P-channel MaS FETs designed to function as analog switches. In the ON state
each switch will conduct current equally well in either direction, and in the OFF state each switch will block voltages up to
30 V peak-to·peak. The switches are integrated on a silicon substrate (body). The switches have a common drain terminal
(D) which will function equally well as a common source. In the same manner, the source terminals (S) will function equally
well as drains. Each gate (G) is provided with a normally OFF "pull-up" MaS FET which may be turned ON to provide a
current source to the gate-driving circuit. The pull-ups are turned ON or OFF by connecting the "P" terminal to a negative
supply or to the "8" terminal respectively.
FUNCTIONAL DIAGRAM
Gj
G2
G3
G.
G5
G6
9
9
9
"cU cQ cd rW cO rU
8~
,
82
a
S30
84 0
iI
~
II
I
~
I
I
!
i
I
I
I
I
I
I
I
i
I
I
I
I
~
85 0
86 0
PIN CONFIGURATION
PDo
G,a
~Sl
~S2
,
P
G,
JL
(!:
G3
Q
~S3
G4
Q
~S4
s (!
P2? ss
8 a 0 13
~B(V+)
84 0 12
G6
~S6
c.;I
NC(!
2
S1~]
G2
G
._.•..
n
::r
a
~
~
~
-
CD
-::-
82 0 14
85
G2
G3
G.
G5
3
4
5
6
~L lL
TOP VIEW
ORDER NUMBERS: G115AP OR G115BP
SEE PACKAGE 12
3:
c
0
SCHEMATIC DIAGRAM
Dual-In-Line Package
Pr::I
~
--
o BIV+J
a"
S6 010
SilicDnix
II
G6
IL lL lL
J]
J]
"'II
In
B (V+l
..
7 ... r
~
9
-::16
0
1]
JIL
5-1
..o
1ft
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..
Operating Temperature (A Suffix).
(B Suffix) .
Power Dissipation' ...
-2 to 30 V
-2 to 30 V
±30V
35V
100mA
5mA
VB to Vs ..
VB to VD ..
VD to VS..
. ....... .
VB to VG, VB to Vp ...... .
IS,ID ...
IG'
Ip ..... .
--65 to 150° C
-55 to 125°C
-20 to 85°C
900mW
'All leads soldered or welded to PC board. Derate 12 mWtC
above 75°C.
100llA
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample-tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
-55'c
GnSA
25'C
'00
200
CHARACTERISTIC
~
Orein-50urce
ON ReSistance
rOS(onl
450
1-
Source OFF
IS(offl
Leakage CUrrent
1-
25'C
85'C
'00
125
'25
'25
'50
200
250
250
250
300
500
450
600
500
600
-0.6
-500
-6
-500
-2500
-'0
-1000
Drain OFF
Leakage Current
-2.5
6 S IGlonl
GateQNCurrent
-0.8to-2.4
1I-T
7
~
1- I
Gate-Channal
Leakage Current
lOSS
VOB"O,VPB=O
VoS=O,VGO=-30V
n
Voa=-10V,VGO=-20V
Voa=-20V,VGO=-10V
I
IIS .. -lmA
I
VSD" -20 V, VGO = 0
oA
1010ffi
5
TEST CONDITIONS, UNLESS NOTED:
UNIT
G1158
_zooc
12SOC
rnA
-0.810 -2.4
-0.5
-5
-500
VOS = -20 V, VGS = 0, Vss '" 0
-500
oA
VGS = -30 V, Vps = -30 V
VGS=-20V
8 C VGShhl
Gate-Source
Threshold Voltage
9
BVoSS Min
orain·Source
Sreakdown Voltage
-30
-30
-30
-30
-30
-30
to = -50 /.lA, VGS = 0, VSS = 0
SVSoS Min
Source·oraln
Breakdown Voltage
-30
-30
-30
-30
-30
-30
IS =-10IolA,VGO= 0
BVGBS Min
Gate-Body
Breakdown Voltage
-35 to-90
-3510-90
-35 to -90
-35 to-90
-35 to-90
'2
BVPBS Min
Pull·Up Gate·Body
Breakdown Voltage
-35 to-90
-35 to-90
13
C"
Gale·Source
Capacitance
O,9Typ·
0,9 Typ·
Gate-Drain
Capacitance
0,9 Typ·
0,9 Typ·
oraln·Sourca
OFF Capacitance
0.4 Typ"
04Typ·
11'0
111
1-
1-
'4 ~ Cgd
1-
N
15 A Cdsloff)
I-MI
17
-3510 -90
-35 to -90
Source·Body
Capacitance
16 C Csb
1-
Oraln·Bocly
Capacitance
c"b
10 = -101JA, VOG" 0, VSS'" 0
-1.5 to -4.0 -1.5 to -4.0 -1.5 to -4.0 -1.5 to -4.0 -1.5 to -4.0 -1.5 to --4.0
-35 to -90
-35 to-90
-35 to -90
Ip'" -lOIJA, VGS" 0
Oram Guarded
VOS = VSB = 0,
Body Guarded
Source Guarded
pF
Gale Guarded
r---------~--------~
2 Typ"
2 Typ'
12 Typ*
12Typ*
·Typlcal values are for OESIGN AIO ONLY, nOI guaranteed and not subject to producllon testing
VOB" 0, VSB = -5 V
Gate and Orain Guarded
VSB" 0, VOB:' -5 V
Gale and Source Guarded
VGS=O
f= 1 MHz
MAB-A
TYPICAL CHARACTERISTICS
IS(off)' ID(off) vs
Temperature
rDS(on) vs VGS
Capacitance vs VDB or VSB
1000 _ _
5O~-r~rT'-~-r'-~-r~
'00 _ _ _
to~1M
~
, ....t'
Cd(onl IV G8" 30 VI
20H-t-t-Hu.-rt-t-'f:::±;;l.,f"'f---b.rt
10 Cdb NGD" 0 VI
CsbIVGS=OVI
1!! -30
-25
-20
-15
-TO
-6
Vas - GATE-SOURCE VOLTAGE (VOLTS)
25
45
65
85
105
'25
-30
-20
Voa OR V SB - DRAIN·BODY OR
T - TEMPERATURE I'CI
SOURCE·BODY VOLTAGE (VOLTSI
5-2
Siliconix
-to
-20
VpB - PULL·UP GATE TO BODY
VOLTAGE (VOLTS)
-30
Monolithic 5-Channel
Enhancement-Type MOS FET
Switch
designed for
• • •
......
Q
H
Siliconix
G"
BENEFITS
•
• Switching Analog Signals
II Multiplexing
Reduces External Component Requirements
o Internal Zener Diode Protects the Gate
o Five Switches Per Chip
o Integrated MaS FET for Each Gate to
Provide "Pull·Up" Current for Gate·
Driver Circuit
DESCRIPTION
The Gl16 contains five enhancement·mode P·channel MaS FETs designed to function as analog switches. In the ON state
each switch will conduct current equally well in either direction, and in the OFF state each switch will block voltages up to
30 V peak·to·peak. The switches are integrated on a silicon substrate (body). The switches have a common drain terminal
(D) which will function equally well as a common source. In the same manner, the source terminals (5) will function equally
well as drains. Each gate (G) is provided with a normally OFF "pul!·up" MaS FET which may be turned ON to provide a
current source to the gate·driving circuit. The pull-ups are turned ON or OFF by connecting the "P" terminal to a negative
supply or to the "8" terminal respectively. It is recommended that the G 115 be used for new designs.
FUNCTIONAL DIAGRAM
PIN CONFIGURATIONS
Flat Package
"
D
G,
S,
G2
S2
G3
S3
G4
S4
G5
S5
NC
-3:
c
-..•..
B(V+)*
7
TOPVIEW
ORDER NUMBER: G116AL
SEE PACKAGE 5
·Common to Substrate and Base of Package
n
~
a
SCHEMATIC DIAGRAM
G5
Dual·1 n·Line Package
::a
::a
B (V+)
6
...
8
CD
"'1'1
In
"
1ft
----~~---+----~----+_--~_oD
S2~~--------~1~----r----+----~--~
S3g__
ORDER NUMBER: G116AP
SEE PACKAGE 11
--------------~JJj--~~--_+--_+
~~~--------------------__1~--~r_~
s56~--------------------------~J~
Siliconix
5-3
ABSOLUTE MAXIMUM RATINGS
Operating Temperature ...
Power Dissipation*
Flat Package * *
14 Pin DIP*** . . . . . . .
-2 to 30 V
-2 to 30 V
±30 V
35 V
100 rnA
5mA
.100j.LA
--65 to 150° C
VB to Vs ..
VB to VD ..
VD to VS ..
VB to VG. VB to Vp .
IS.ID ....
IG············· .
Ip . . . . . . . . . . . . .
Storage Temperature ..
750mW
825mW
* All leads soldered or welded to PC board.
**Derate 10 mW/oC above 75°C.
***Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
CHARACTERISTIC
G116A
_55°C
1
1---;
Drain-Source
ON Resistance
rOSlon)
1---:;
1-
•
•
1-
IOloff)
6 s IGtonl
T
7 A lOSS
I_T
I
8 c VGS(thl
I-
8SoC
2S"C
Q
100
100
125
125
125
150
200
250
250
250
300
'50
'50
600
500
500
600
Leakage Current
-0'
-500
-.
-500
Dram OFF
Leakage Current
-2.5
-2500
-10
-1000
Gate ON Current
-08 to -2.4
Gate·Channel
Leakage Current
-0'
Gate-Source
Threshold Voltage
l-
-20 C
200
Source OFF
IS(offl
1-
125"C
Vos - 0, VGO '" -30 V
VDB~-10V.VGD=-20V
"
Vas =
VSO=-20V.VGO=O
Ves = -20 V, VGS=O, VSB = 0
-.
-500
mA
VGS = -30 V, VPB = -30 V
oA
VG8=-20V
-1.510-4.0 -1.5 to -4.0 -1.5 to-4.0 -1.4 to -4.0 -1.5 to -4.0 -1.5 to -4.0
ID'"
-10~A.
10=
-so ",A, VGS= O. VSB = 0
VSB =0, VOG = 0
BVOSS Min
Orain-Source
Breakdown Voltage
BVSOS Mm
Source-Dram
Breakdown Voltage
-30
-30
-30
-30
-30
"
BVGBS Min
Gate-Body
Breakdown Voltage
-35 to -90
-35 to -90
-35 to-90
-35 to-90
-35 to -90
-35 to -90
IG=-10J-lA
12
BVPBS Mm
Pull-Up Gate-Body
Breakdown Voltage
-35 to -90
-35 to -90
-35 to-90
-35 to-90
-35 to -90
-35 to -90
Ip"'-10",A.VGB=0
C"
Gata-Source
Capacitance
0.9 Typ·
0_9 Tvp·
Cgd
Gate-Dram
capacitance
0,9 Typ·
0.9Typ·
0.4 Typ·
0.4 Typ·
9
110
1113
,. ~
I,.
1-
N
-30
Dram-Source
OFF capacitance
A Cdsloff)
M
I
16 C Csb
f-
117
-30
Cdb
-30
-30
-30
Ils=-lmA
20V,VGO'" 10V
oA
-08to -2.4
-500
TEST CONDITIONS, UNLESS NOTED:
Voe" 0, VPB = 0
UNIT
G1168
25'C
-30
-30
V
IS'" -10 ",A. VGO = 0
Dram Guarded
VDB "" VSB = 0,
Body Guarded
Source Guarded
VGB=O
Gate Guarded
0'
f= 1 MHz
Source-Body
Capacitance
6 Typ·
6 Typ·
VDB=O,VSB=-5V
Gate and Dram Guarded
Drain-Body
capacitance
12 Typ·
12TVp·
VSB = 0, VDB = -5 V
Gate and Source Guarded
MAR·A
·Tvpical values are for DESIGN AID ONLY. not guaranteed and not subject to production testing.
TYPICAL CHARACTERISTICS
rDS(on)
VS
IS(off). ID(off) vs
Temperature
V GS
Capacitance vs VDB or VSB
IG vs VpB
W~-rT;rr'-~-r,-~-r~
1000mft_
10'IfIIIt!I/
Cd(on} IV GB = -30 VI
20H-+-f-+-H
L+=t=-i:::l>.f""I---hH
10 CdbIVGO-OVI
II!
-30
-25
-20
-15
-10
-.
VGS- GATE-50URCE VOLTAGE (VOLTS)
5·4
CsbIVGS"OV}
O.1~ISIOff)
25
45
65
8'
105
T - TEMPERATURE I'C}
125
-20
-30
I
-10
V OB OR VS B - DRAIN·BODY OR
SOURCE-BODY VOLTAGE (VOLTS)
Siliconix
-20
V pB - PULL·UP GATE
TO BODY VOLTAGE (VOLTS)
-30
Monolithic 5-Channel
Enhancement-Type MOS FET
Switch
designed for
• • •
• Switching Analog Signals
• Multiplexing with Enable Switch
......
.....
Q
H
Silicanix
BENEFITS
•
Reduces External Component Requirements
o Internal Zener Diode Protects the Gate
o Five Switches Per Chip
o Integrated MaS F ET for Each Gate to
Provide "Pull-Up" Current for GateDriver Circuit
DESCRIPTION
The G 117 contains six enhancement-mode P-channel MaS FETs designed to function as analog switches. In the ON state
each switch will conduct current equally well in either direction, and in the OFF state each switch will block voltages up to
20 V peak-to-peak. The switches are integrated on a silicon substrate (body). The drains of five of the switches are internally
connected to the source of the sixth switch. This arrangement is intended for use of the device as a 5-channel first-level
and one-channel second-level multiplexer. Each of the six gates are provided with an internal "pull-up" current which may
be turned ON or OFF by connecting the pull-up control terminal (P) to a negative supply or to the body (8) terminal.
FUNCTIONAL DIAGRAM
-I
c
._...
I
PIN CONFIGURATION
n
::r
a
SCHEMATIC DIAGRAM
Flat Package
G6
G,
a
2
:::s
:::s
B (V+)
8
-
CD
S,
Sa
s.
Ss
Gs
C:~=~~-'~~~:::J
B(V,+I"
7
8
TOP VIEW
ORDER NUMBER: G117AL
SEE PACKAGE 5
12
"20
11
Sa 0
'1!
'j!
10
84 0
9
SsO
·Common to Substrate and Base of Package
Silicanix
5-5
..o
......
ABSOLUTE MAXIMUM RATINGS
.. -2 to 30 V
VB to VS· .
.. -2 to 30 V
VB toVO··
±30V
Vo toVS ..
35V
VB to VG. VB to Vp . . . . . . . . . . . . . . . . .
100mA
15. 10 . . . . . . . . . . . . . . . . .
5mA
IG· . . . . . . . . . . . . . . . . . . . . .
Ip. .... ... ..
. ........ .
100J,lA
Storage Temperature . . . . . . . . . . . . . . . -65 to 150°C
-55 to 125°C
Operating Temperature (A Suffix) .
(B Suffix) ..... . -20 to 85°C
Power Dissipation * ....
750mW
* All leads soldered or welded to PC board. Derate
10 mWtC above 75°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
-SS~C
~2
---;-
-
rOSlon}"
4
'SlolI)
1-
- •
ICloffl
6 S IDloffl
T
-
7 A IGton)
_T
I
-
8 C IGSS
-
-20~C
2S~C
100
12.
12'
12.
150
200
200
450
450
250
250
2.0
300
600
500
500
600
-0.5
-500
-.
-2500
-10
-500
Leakage Current
-0'
-500
-5
-100
Gate ON Current
-0.810 -2.4
Leakage Current
Drain OFF
Gate-Channel
10
VGSlthl
Gate-Source
Threshold Voltage
11
BVOSS Min
12
BVSDS Min
Dram-Source
Breakdown Voltage
Source·Draln
Breakdown Voltage
-500
-SOD
-5
-1.5to-4.0 -1.5to-4.0
-1.5to-4.0
-1.5to-4.0 _1.5to-4.0
-1.S10-4.0
-1.5\0-4.0 -1.510-4.0
-1.5to-4.0
-1.510-4.0
-1.5to-4.0
-1.5to-4.0
I
VD8 = 0, Vao = -30 V
"
VOS = -20 V. VGO = -10 V
,A
Vos" -20 V, VGS '" 0, VGSS '" -30 V, VS8 = 0
VOS = -10 V, VGO '" 20 V
-10
-0.8 to -2.4
-0.5
Leakage Current
Gate-Source
Vos'"o,Vps"'O
8S~C
-2.S
Threshold Voltege
IS" -1 mA, VGSD" VGO
VSO=-20V.VGO"'0
VOS = -20 V, VGS = -30 V, V GSS = 0, VSB = 0
mA
V08 = -30 V. V08 '" -30 V
,A
VG8=-20V
IS" 10j..lA. VOG1-5 = 0, VGSS = -20 V
IS1 .. 10 Jl,A. VOGS
C
O. V~B1 = -20 V
-30
-30
-30
-30
-30
-30
10 = -SOJJ.A, VGS = 0, VSB = 0
-30
-30
-30
-30
IS = -10JJ.A, VGD =0
-30
-30
-35 to -90
-35 to -90
-35 to-90
-35 to-90
-35 to-90
-35 to-90
IG "'-10Jl,A
-35 to -90
-35 to -90
-35 to-90
-35 to -90
-35 to-90
-35 to-90
Ip=-10JJ.A,VGS=0
13
BVGBSMin
Gate-Body
Breakdown Voltage
14
BVPBS Min
Pull-Up Gate-Body
Breakdown Voltage
Cg.
Gate-Source
Capacitance
0.9 Typo.·
0.9 Typo.·
Gate-Dram
Capacitance
0.9 Typ··
0.9 Typo.·
0.4 Typ"·
0.4 Typ··
VOB .. 0, VSB '" -5 V
VStl-SIB = O. VGII-SIB '" O. VGSS" -30 V, VOB = -5 V,
All Gates and Sources Guarded
18
-
-
100
Dram OFF
VGSlthl
- " ~ Cg.
-
125~C
Source OFF
Leakage Current
9
-.
-
Onlln-Soun:e
ON Capacitance
25"C
TEST CONDITIONS. UNLESS NOTED:
UNIT
G117B
G117A
CHARACTERISTIC
N
17A
M
18
"
~
Dram-Source
Cclsloffl-
OFF Capacitance
Csb
Source-Body
Capacitance
2 Typ··
2 Typ··
Cdb
Orain·Body
capacitance
12TVp·"
12Typ··
Dram Guarded
VOB"'VSS=O,
Source Guarded
Body Guarded
1-------1
Gate Guarded
pF
"This is resistance (capacitance) from each source to common internal node. Multiply resistance by two for total resistance from inputs to output.
"'TYpical values are for OESIGN AID ONLY, not guaranteed and not subject to production testing.
VG8· 0
f"'1 MHz
Gate and Dram Guarded
MAB
TYPICAL CHARACTERISTICS
IS(off)' 10(off) vs
Temperature
Cd vs VOB
100
60
VSS=VGS-VPS'"0
VOGO'" lOV
'-'MHz
-
20
10
2.
45
65
85
105
T - TEMPERATURE (·C)
5·6
125
-30
-25
-20
-15
/
V
-10
-5
VOS - ORAIN·BODY VOLTAGE (VOLTS)
Siliconix
0
Vps - PULL UPGATE·BODY VOLTAGE (VOLTS)
Monolithic 6-Channel
Enhancement-Type MOS FET
Switch
designed for • • •
BENEFITS
• Switching Analog Signals
•
II
Multiplexing
...•...
Q
H
Siliconix
Reduces External Component Requirements
o Internal Zener Diode Protects the Gate
o Six Switches Per Chip
DESCRIPTION
The Gl18 contains six enhancement-mode P-channel MaS FETs designed to function as analog switches. In the ON state
each switch will conduct current equally well in either direction, and in the OFF state each switch will block voltages up to
20 V peak-to-peak. The switches are integrated on a common substrate (body). They have a common drain terminal (D)
which will function equally well as a common source; likewise, the source terminals will function as drains.
PIN CONFIGURATIONS
FUNCTIONAL DIAGRAM
Flat Package
G,
G2
G3
G,
G5
G6
?
?
?
?
?
?
I
I
5,~
82
0
~
53 0
84 0
55 0
B
(v+).c:~~~r""~;;~:::J
7
I
~
0
:
I
~
56 0
I
:
~
0
I
I
~
l1li
8
TOPVIEW
i
.--•...
n
c
ORDER NUMBER: Gl18AL
SEE PACKAGE 5
SCHEMATIC DIAGRAM
·Common to Substrate and Base of Package
::r
a
B(V+)
G,
~
~
Dual·ln-Line Package
-rn
CD
8
0
"'II
...
'3
52
a
'2
S3 0
11
54
0
'0
85 0
9
S6 0
ORDER NUMBER: Gl18AP
SEE PACKAGE 11
Siliconix
1ft
TI!
l~
l~
5·7
..o
•
Operating Temperature (A Suffix) .. . .
-55 to 125°C
(B Suffix) .. . .
-20 to 85°C
Power Oissipation*
Flat Package ** ... . . ................
750mW
14 Pin OIP*** ... . . ................
825mW
* All leads soldered or welded to PC board .
**Oerate 10 mWfC above 75°C.
***Derate 11 mWfC above 75°C.
ABSOLUTE MAXIMUM RATINGS
. . . . · . ............ -2 to 30 V
VB to VS ..
. . · . ............ -2 to 30 V
VB to VO.
Vo to VS. · . .. . · . ... . · . · . .. . · . · . ±30V
35 V
VB to VG. · . . . .. . · . . ... · . · . .. . · . · .
IS. 10 .. . · . .... . · . ... . · . · . .. . · . · . 100 mA
5mA
IG····· . .. . .... . · . . . . . · . · . . .. · . · .
Storage Temperature · . . . . . · . · . ...
-65 to 150°C
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample·tested for AC parameters and high and low temperature limits
to assure conformance with specifications.
MAX LIMITS
I.
CHARACTERISTIC
1---2.
2
4
125
25"C
85"C
125
125
150
200
200
250
250
250
300
450
450
600
500
500
600
ISloft)
- 6
>
'BO
m
O.B
40
t-TIME (psi
60
45
BO
0 f--
,
'0
'00
FREQUENCY (Hz)
Siliconix
6-3
.....3
APPLICATIONS
Instrumentation Amplifier
Active Filter
V+=l.SV
VIN
R4
750 Kn
R3
10 Kn
BAND
PASS
-=-
0= 26
Ho = 26
PO"'35,..W
AV"l+~
~
fo= lK Hz
R3
Qmax<
Vas (TYP) RTI .. 0.45 mV
-3Ho -1 fo,Ho«
PO;; 7.5 mW
~
~
5
C, =C 2
R5=R6=R7
Precision Phase Splitter
Double-Ended Limit Comparator
v+=
lOV
+15V
R4
PO=7.5mW
~=!!2..:!:J!J.
VIN
1 Mn
R1
VOUT;; "lOW" WHEN:
VHIGH> VIN > VLOW
V-=-10V
DIRECT CMOS OUTPUT
500 Hz Tone Detector
C4
O.05Io1F
R8
RB
l00Kn
320Kn
SV
0,
IN914
o
GIVEN
n, fa. C
LET
C =C3"C4
RS= 211'fo C
1 -....
+OVOUT
,~
convenience.
IN THIS CIRCUIT:
H.
R9
30K
Silicanix
VLOW=
Vm RQ- 14 RA
RA+RB
H
Siliconix
-
Functionl Application of the ,..
...
L144 Programmable Micropower .DI.DI
Triple Op Amp
-
INTRODUCTION
The L144 is a monolithic triple operational amplifier circuit
with an external programming feature for power dissipation
and input bias current control. It finds application in RC
active filters, instrumentation amplifiers, micropower comparators, and numerous general signal processing circuits_ The
L144 is a practical industry standard op amp wherever low
current drain, low voltage, low power, or very small physical
size are the controlling criteria_
This Application Note describes the Ll44, how to program
it, what the effects of slew rate limiting are, and some practical circuit applications_
The Ll44 has three operational amplifiers programmed by
one external current setting resistor. It operates from power
supplies ranging from ±IB Y to as low as ±1.5 Y with quiescent supply currents of from 10 ..uA to greater than 1 rnA
independent of supply voltage. The schematic shown in Figure I reveals a general-purpose PNP input transistor op amp
with an outstanding difference. The master bias current is
not set by an internal resistor strung from y+ to Y-, but is
brought out to an external pin. This allows the user to determine the operating currents of each stage through a system
of current mirrors. Of special interest to the designer are the
equal collector currents of Q I and Q2, which are derived
from the output of Q4' These collector currents, divided by
a beta of approximately 50, determine the input bias currents
for each amplifier. The ratio between the set current and the
collector current ofQ4 is unity, which allows one to program
the input bias current simply by changing the set current
input of the device.
IDI
,..
ONE AMPLIFIER
-.
+Vs
:I
CD
II
..
-IN
+INo--+----if--'
1K 51
-Vs
OUT
L144 Schematic
Figure 1
Siliconix
6-5
-......
II1II'
II1II'
-
Input Bias Current and Supply Current
Frequency Response
The relationship between supply current, supply voltage, and
the setting resistor is shown in the graph and set current
model of Figure 2. The two diodes of the set current model
correspond to the base·emitter junctions of Q16 and Q\7'
At the data sheet standard supply current of 250 JlA the
typical Bode plot is as shown in Figure 4. The low frequency
gain of approximately 95 dB rolls into a uniform -20 dB/de·
cade slope until after the 0 dB unity gain crossing point. The
variation of open loop gain with temperature is typically
-2 dB per !Oooe of temperature rise. The 600 kHz unity
gain crossover gives a gain bandwidth product (GBWP) of
600,000. Figure 5 shows the variation of GBWP with sup·
ply current.
10
co
•
~
4
~
a:
V
.40~A -
L
V
/
I/. V
~
~1"A
V
V
V
100
t-80
.,..l-
V
-
250J.lA
~PA
V
r-
±10
_ 15
f'.
60
!'
40
,!,
±18
20
I'
SUPPLY VOL TAGE (V)
I
L 144 SET CURRENT MODEL
I
-20
v'
10
V+ OR GND
105
10 3
100
10·
f - FREQUENCY (Hz)
L 144 Open Loop Gain vs Frequency
Figure 4
v-
1.4
1.2
Supply Current vs Bias Resistor and Supply Voitage
Figure 2
v
1.0
Figure 3 shows the essentially linear relationship between
input bias current and total quiescent supply current for the
Ll44. The low input bias currents at low supply current
levels allow the Ll44 to maintain good input specifications
even with the large feedback and load resistor values normal·
ly encountered in micropower applications.
0.8
0.6
I
V
0.4
0.2
V
100llA
The slightly lower input bias currents at the higher supply
voltages are due to the narrower base width and higher beta
encountered at V S = ± 15 V.
1
f-
1-::
vs=.I,I.5v~'15V
a:
:::l
u 100
:;J
f-
a:
~
10
~
100
1000
ISUPPL Y (IJ A)
Input Bias Current vs Supply Current
Figure 3
6·6
L144 Gain Bandwidth Product vs Supply Current
Figure 5
Slew Rate
iii
~
lOrnA
The vertical axis is linear whereas the horizontal ICC axis is
logarithmic, demonstrating that the GBWP does vary with
ICC, but at much less than the I-to·I-ratio observed for
other parameters.
1000
iiia:
lmA
ISUPPLY
Slew rate is almost a direct function of supply current as
shown in Figure 6. This follows from the fact that slew rate
limiting is actually caused by the finite limits of the internal
current sources (which charge and discharge the second stage
compensation capacitor) varying with the externally-determined set current. An amplifier output changes from the
small signal response shown on the Bode plot to a slew-ratelimited response when the rate of change of the output
voltage exceeds the rate of change determined by slew rate
limit of the amplifier. Since the maximum rate of change of
Siliconix
0
V+'" 1.5V
Vs - 11.5+' 15V
-.....
1
w
r-
!--+--+-0 VO UT
-T5V
"6
320K
PD= 7.5mW
Tone Detector Circuit
Figure 10
Tone Detector
Another example of a single L144 providing the amplifiers
for an entire system is shown in Figure 10. This tone detector
circuil is made up of a two-amplifier multiple feedback bandpass filler followed by an AC-to-DC detector section and a
Schmitt Trigger. The bandpass filter (with a Q of 25) passes
only 500 Hz inputs which are in turn rectified by D 1 and
filtered by R9 and CA- This filtering action in combination
with the trigger level of 5 V for the Schmitt device insures
that at least 55 cycles of 500 Hz input must be present before
the output will react to a tone input. The actual integrating
capacitor waveform shown in Figure II was taken with a I
voll peak 500 Hz sine wave input. The ratio between capacitor C A charge and discharge is I: II, due to resistors R9
and RIO'
In the example shown in Figure 10 the chosen value of k = 2
and the passive components used resulted in a measured Q
of 23.1. The center frequency of 495.7 Hz and Ho of 9.9
were close to the calculated values of 500 Hz and 10.
The detector RC was designed to have a 3 dB down frequencyof:
(9)
while the Schmitt trigger operated around the reference
vollage with trip points determined by:
For frequencies other than the 500 Hz center frequency
shown in the example the relevant bandpass filter 2 equations are:
GIVEN:
Q, f o , Ho (Q normally from 10 to 50)
LET:
C = C3 = C4
I
< k < 10 (k chosen for componen t
VREF RB - 14 RA
RA +RB
(2)
(3)
value convenience)
THEN:
(10)
(II)
where ±14 V is the output swing with ±15 V supplies. The
measured trip points agreed with the calculated values of
5.089 V and 4.81 V within 0.2% in the circuit of Figure 10.
(4)
(5)
E
.:::
(6)
>
(7)
10 msee/ em __
Detector Output Voltage
(8)
6-8
Siliconix
Figure 11
YS
Time
~
3 Amplifier Active Filter
Z
The active filter shown in Figure 12 is a state variable filter
with band-pass, high-pass and low-pass outputs. I t is a classical analog computer method of implementing a filter using
three amplifiers and only two capacitors. With the Ll44
triple op amp it becomes cost-effective to use this configuration with its attendant high Q values and low sensitivities. 3
The practical maximum value of Q is:
"-'I
W
750 K!!
BAND
Afo
Qmax =-3-
3 Amplifier Active Filter
Figure 12
+40
The controlling design equations are:
RS = R6 = R7
CI = C2
!
m
+20
:!!
Q, fo ' and Ho (bandpass output)
1'-
z
(13)
g
-20
(Chosen for compo- (14)
nent value convenience)
-40
./'
HIGH-PASS
.",
+40
R4
Afo
=3H o -I for Ho « - 3 R3
THEN:
Ho
R2 C2 = 21TfoQ
(15)
~
'"
~
+20
\
z
;;:
'"
-20
BAND-PASS
ttI
I I
!
1
"r-....I
I
LOW-PASS
I It
-40
100
Q= 26
fo = I kHz
Ho = 26
l\.
+40
(17)
The design example shown in Figure 12 was calculated as
follows:
1K
FREOUENCY (Hz)
10K
Bode plots of Active Filter Output
(18)
RS = R6 = R7 = 20k
CI = C2 = .0081lF
R3 = 10k
THEN:
-
-20
-40
Q
LET:
I
+20
z
;;:
(16)
RICI = 21TfoHo
PO~75mW
PASS
(12)
where Afo is the open loop gain of amplifier A 1 at the
resonant frequency.
LET:
-..
R,
RJ
10 K!!
GIVEN:
-•,.......
I
Figure 13
Micropower Double-Ended Limit Detector
R4 = ( 3Ho - 1) R3 = 770k "" 7S0k
(19)
The double-ended limit detector. shown in Figure 14 uses
three sections of an L144 and a DC4011 type CMOS NAND
-.,..
~
CD
a
V+= 10V
(20)
~
(21)
giving an actual calculated fo and Ho of
Ho = 1/3 (1 +
~:
(22)
) = 25.3
1M!!
R,
f
Q
o
=---':---,,.......,.c-
21T RI CI Ho
994.7 Hz
1 MIl
(23)
V-=-10V
PO=290p.W
The measured values of Q, Ho, and fa using I % components
were 26.9, 26.3 and 996 respectively. Figure 13 shows the
Bode plots of the high-pass, band-pass, and low pass outputs.
Siliconix
Vour" "lOW" WHEN:
VHIGH> VIN > VLOW
DIRECT CMOS OUTPUT
Micropower Double-Ended Limit Detector
Figure 14
6-9
I
..........
~
-
r-----------------------------------------------------------------~
gate to make a very low power voltage monitor. If the input
voltage V IN is above V HIGH or below V LOW the output
will be a logical high. If (and only if) the input is between
the limits will the output be low. The I Mn resistors R 1, R2'
R3 and R4 translate the bipolar ±IO V swing of the op amps
to a 0 to 10 V swing acceptable to the ground· referenced
CMOS logic.
Total power dissipation is typically 290 !1W while in limit
and 330 !1W while out of limit. Within the ±9 V input range
of the circuit the comparator r~solution'is typically 2 mV
with the offset adjust determined by trimming V HIGH and
V LOW ' Since the L144 is operating at only 14.5!1A of supply current the slew rate is a corresponding low .063V/!1sec.
6-10
CONCLUSION
The preceding practical circuit examples are intended to
show a few of the many possible applications of the LI44
micropower triple op amp.
REFERENCES
I. M.K. VanderKooi, "Slew Rate Limiting ofIC Op Amp is
Easy to Predict and to Avoid," EON, October, 1972;
pp.36-37.
2. J.G. Graema, G.E. Tobey, and L.P. Huelsman; "Operational Amplifiers Design and Application," McGraw·Hill
Co., New York, N.Y., 1971, pp.293-295.
3. S.K. Mitra, "Active Inductorless Filters," IEEE Inc., New
York, N.Y., 1971, pp. 74-78.
Siliconix
Micropower Quad
Comparator
designed for • ., •
,...
....
H
....
0-
Siliconix
BENEFITS
Comparators
• Voltage
Comparators
• Window
lLevel Detectors
• CMOS
Line Receivers
• Oscillators
• Ramp Generators
• Phase Comparators
• BaHery Powered Circuits
•
• Minimizes System Power Requirements
o Operates on 15!.1W
• Reduces External Component Requirements
o Programmable Output Drive Capability
o Direct Wire-OR of Output
o Input Sensing Near Ground
o Direct CMOS Logic Compatibility
• Easily Tailored to Your System
o Single Programming Resistor Simultaneously Alters Supply Current, Input Bias
Current, Slew Rate and Power Consumption
• Minimizes Number of Supply Voltages in
Your System
o Operates with ± 1.0 V to ± 18 V
o Single Supply Operation
DESCRIPTION
The L161 is a monolithic quad micropower comparator circuit, with an external control for varying supply current, input
bias current and output current drive_ This is accomplished by a single resistor connected to V+ which controls the bias
current to 010 which, via a series of current mirrors, supplies bias to the differential amplifier. The L161 finds applications
in areas where low powered battery operation and CMOS compatibility are required. The ability to control comparator
characteristics makes this a very versatile device.
SCHEMATIC DIAGRAM (ONE COMPARATOR)
PIN CONFIGURATIONS
Flat Package
+v
+IN,
OUTPUT
-IN1
ISET
+INZ
NC
-IN2
OUT,
- IN3
DUTZ
a
+l N3
+v
-IN4
OUT4
+IN4
-v
...
Il""
"'
:i
CD
TOP VIEW
'SET
H
a
ORDER NUMBERS L161AL
OR L161BL
SEE PACKAGE 17
~
Dual-In-Line Package
(+Io---+----+---+--~-...J
~--~---~--~--~~~_+--~-~_r_o-v
L _______ _
ORDER NUMBERS L161AP
OR L161BP
SEE PACKAGE 12
ORDER NUMBER L 161CJ
SEE PACKAGE 8
Siliconix
6-11
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage
±18 V
Differential Input Voltage.
±30 V
Input Voltage' (A Suffix) .
±18 V
(B Suffix) .
±18 V
Output Short Circuit Duration" (I ndefinite)
Operating Temperature (A Suffix)
-55 to +125°C
(B Suffix)
-20 to +85°C
(C Suffix)
o to +70°C
Storage Temperature (A and B Suffix) .
-65 to +150°C
(C Suffix)
-65 to +125°C
Power Dissipation'"
Flat Package
750 mW
16 Pin DIP (Side Braze)
900mW
16 Pin Plastic DIP
470 mW
'For supply voltages < ± 18 V, maximum input voltage
is equal to supply voltage
"Continuous short circuit current is allowed for case
temperature to +125°C and ambient temperature to
+70°C
'" All leads welded or soldered to PC board. Derate
10 mWfC above 75°C for the flat package, 12 mWfC
above 75°C for the sidebraze DIP and 6.3 mWfC
above 25°C for the plastic DIP.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25°C. Lots are sample tested for AC parameters and high and low temperature limits to
assure conformance with specifications.
Low Power Characteristics
L161B/C
L161A
Test Conditions. Unless Otherwise Noted:
Characteristics
I~
2
1-
1+
I5
,
N
P
VOS
'OS
U
0
U
T
P
0
16
V
N
A
M
I
C
17
S
I14
115
I-
1""'18
1~
20
U
P
P
L
V
3.0
-20'C/
DoC
25'C
6.0
5.0
mV
1.0
Max
20
25
Typ"
1.0
1.0
nA
Max
100
200
Typ*
20
20
DC Open Loop
Voltage Gain
Min
10
20
20
5
10
10
AVDL
Typ*
25
30
35
25
30
35
VOL
Low Output
Voltage
Min
Typ"
Min
V OH
High Output
Voltage
Typ"
CMR
Common Mode Range
Typ"
t,
Response Time
Typ*
CMRR
Cornman Made
Rejection Ratio
Min
PSRR
IS
-2.6
-2.6
-2.95
-2.95
2.5
2.5
nA
V/mV
V
V
2.9
2.9
+1.3/
-3.0
V
5.0
5.0
,usee
75
75
TVp*
90
90
Power Supply
Rejection Ratio
Min
65
65
Tvp"
BO
80
Supply
Current
Typ·
-3.0
300
300
210
350
300
300
RL =20Kn
RL = 20K"
+1.3/
Max
VS::; ±3 V. 'SET = 10 JlA. RL ::; 10M n
C L = 10 pF
Unit
G
1.0
Typ*
+85°CI
70 e
Input Bias
T
12
13
5.0
+125°C
Current, Total
1- U
1.2!...
Max
25'C
'BT
7
I~
Input Offset
Current
T
16
16
1-
Input Offset
Voltage
-55'C
dB
R
=
200K
n
R
::; 200K
n
See Note 1
100 mV Overdrive
V ,N = CMR
dB
350
210
.A
All Inputs Grounded
RL = -
IBAJ
*Typical values are for Design Aid only, not guaranteed and not subject to production testing.
NOTE:
1. The output current drive of the L161 is non-symmetrical. This facilitates the wire-~Ring of two comparator outputs. The output pulldown
current pulldown current capability is typically 75-150 times the pullup current.
6-12
Siliconix
......
r-
ELECTRICAL CHARACTERISTICS (Cont'd)
0High Power Characteristics
L161A
L161B/C
Test Conditions, Unless Otherwise Noted:
_55°C
Characteristics
1
Vas
"'2
I-I
3 N
1-'- P
4 U
I-;-T
lOS
16
1ST
6.0
Voltage
Typ"
Input Offset
Current
Max
60
90
TVp·
5.0
5.0
400
100
500
50
100
50
100
M..
Typ·
170 AV
Voltage
Gain
Typ"
I-U
I"":"" T
10 P
I- U
11 T
Low Output
Min
Voltage
TVp·
VOH
High Output
Mon
Voltage
TVp·
CMR
Common Mode Range
t,
CMAR
112
13
0
114 ~
11s~
I- I
16 C
17 S
I""iii"" U
I- P
19 P
I-L
20 V
IS
25.0
75.0
Min
6.0
6.0
1.5
15
75
14.5
14.9
14.5
14.9
Tvp*
+131
-15.0
-15.0
Response Time
Typ·
1.0
1.0
Common Mode
Rejection RatiO
Min
75
75
Typ·
90
90
Min
65
80
65
80
Typ·
Supply
Max 4000
3500
Current
TVp·
2100
nA
30
100
4000
V/mV
R = 20K n
V
RL =20KH
R
R
V
+131
3750
C L '" 10 pF
nA
30
100
-14.6
-14.9
Vs = .15 V,I SET = 100.A, RL = 2M n
Unit
mV
800
100
-14.6
-14.9
Power Supply
Rejection Ratio
PSRR
3.0
1.5
70°CI
+85°C
25°C
_20°C
Max
Input Bias
VOL
OOCI
+12SoC
Input Offset
Current. Total
7
25°C
See Note 1
n
n
= 20DK
': 200K
V
100 mV Overdrive. C L = 10 pF
.usee:
VIN = CMR
dB
dB
3750
3500
2100
All Inputs Grounded
.A
RL = ~
IBAJ
"Typical values are for Design Aid only. not guaranteed and not subject to production testing.
NOTE:
[(+Vl - (2VSEI - (-VI]
1. Set current (ISETI and supply current (JSUPPL yl can be determined by the following formulas: ISET =
;
RSET
ISUPPL y~ :?,1 x ISET.
TYPICAL CHARACTERISTICS (TA
= 25°C, VSUPPLY = ±15 V
unless otherwise noted)
RSET vs VSUPPL y for
Input Bias Current vs Supply Current
100
Supply Current vs Temperature
E
Various ISUPPLI ES
lK
10
VS· :!:.15V,
1
I-
~
~
s' ;
~
10
~
'0
~
VS"~
~
1
1
!!.'
111111111 I
0.1
1
100
10
I-
It
20'
0
lK
-4'
10K
Slew Rate vs Supply Current
~
20.
'60
~
'4'
~
~
'20
0
'00
~
8.
z
~
~
w
,I'
NEGATIVE
r- TRANSITIO/,
60
~ 2.
40
i;l
z
./
V
••
9
•
7
~~~~~i'ONI~
1./
YS. :!:.15V
VIN = ± 100 mVp
/
RL:O 10Mn
CL =,OpF
'00
V
400
~
::!
~
;:
~
/
I
50.
IS -SUPPLY CURRENT
800
(~AI
12.
8'
~
~
5
0
4
r
3
~
2
,
•
1000
z
~
~
~
::;
~
~z
0.'
~:~
~
"
~
"
"!:;
C
:;
>
I
I---'
6.
....... 1""
r-
~
z
8.
"
w
60
....... 1""
0
4'
>
I
>
C
~
~V~~I"5V
~
"~
i-"'"
VS" t3V
WIll
'0
111111
20
-4.
0
40
T - TEMPERATURE
so
'~CI
Siliconix
±15
111111
111111
100
E
140
0
.
:1:.10
Voltage Gain vs Supply Current
12.
VS=!lSV
10'
,5
CD
a
Vs - SUPPLY VOLTAGE (VOLTS)
18.
w
-.::s
r-
,~
'.4
IS =1 mA
:;
.
~~
ZSOf.l A
•
Voltage Gain vs Temperature
6
/
4'
22.
10
I
'8'
w
•
,"
',;..1'
T - TEMPERATURE (Oel
'SUPPLY SUPPL V CURRENT ("AI
~
,
FALL TIME 90% TO 10% (Jolt)
Response Time vs Input Overdrive
Positive Transition
2DO
Vs= 115V,IS= 1 rnA
1DOmV
100
,"mV
!!
>
.mV
~
-5mV
I.
,.
10
10
-.
-1D
-1' o
-20mV
-100
1\
~~
I!:~
::00
VS .. :t15V
IS=lmA
100
!!
>
-100
~?
10
II'S'
Response Time vs Input Overdrive
Negative Transition
.s
\
10
200
"\.
Rl = 10Mn
CL'''10 pF
"\.
20mV
lOOmV
I
1\
.mV
I
TIME
lOOmV
/
'mV
/
!//
!:iiii
~~
~~
V
::00
~?
//
-1.
.........
20mV -100mV
-1'
Rl.'"'OMn
CL. = lOpF
V
D
TIME I/Js)
I~II
Note:
The output current drive of each comparator in the L161 is non-symmetrical. The pull-up current is
typically 2 [V+ -1 - (V-)/RSET) and the pull·down current capability is typically from 75 to 150
times the pull-up current.
APPLICATIONS
v+
v-
Zero Crossing Detector
v+
RSET
16Ma
.-'W'Ir--oV+
VOUT
For V = ±5 V
Po
=601'W
v-
Voltage Level Detector
Double Ended Limit Detector
6-14
Siliconix
100
......
r-
APPLICATIONS (Cont'd)
+5V
0-
+5 V
ISUPPLY = 800 /lA
OUT
-12V@5mA
560Kn
A Regulated DC to DC Converter
"3
1 MEGn
"2
+9V
100Kn
ISUPPLY = 10 JJA
CMOS Line Receiver
",
, MEGn
+15V
'6
"2
TRIP 5A~~S~>;t--....-I
+10V
2N4274
"3
15Kn
",
30aK n
>.:.:'3~'-OOUT
"2
300Kn
Jo.oo,
CCOMP
The L161 as an X100 Operational Amplifier
A Low Battery Indicator
Squarewave Oscillator
,OV
ISUPPL V = 350 fJA
RSET2
10Mn
250Kn
'6
CLOCK
",
75Kn
....,..:::s
CD
a
.,
':~
"
C
~.O'"F -=
A Versatile 2<1> Pulse Generator
Siliconix
6-15
......
,.-
H
-,.
....
Siliconix
.....
•
.....
Z
Function/Application of the L161
Micropower Comparator
C
INTRODUCTION
The L161 is a monolithic quad micropower comparator
with an external control for varying its AC and DC characteristics. The variation of a single programming resistor will
simultaneously alter parameters such as supply current, input
bias current, slew rate, output drive capability, and gain.
By making this resistor large, operation at very small supply
current levels and power dissipations - typically in the low
microwatt region - is possible. The L161 is therefore ideal
for systems requiring minimum power drain, such as battery·
powered instrumentation, aerospace systems, CMOS designs,
and remote security systems.
network. QI-Q6 and DI form a darlington differential amplifier with double· to-single ended conversion. Q6 is a dual
current source whose outputs are exactly twice the current
flowing through Q8. The collector current of Q8 is a function of the current supplied externally to Q9·Q 10, which in
turn is known as the set current or I SET. This set current is
established by a resistor connected between the ISET terminal and a voltage source, most commonly the positive
supply. Ql1 prevents excessive current from flowing through
Q9 and QlO in the event the ISET terminal is shorted to the
positive supply; it has no effect on circuit operation under
normal conditions.
Description
The set current can be expressed as:
The Ll61 is fabricated on a 48 x 54 mil chip using standard
bipolar processing. The circuit (Figure I) is composed of
five major blocks - four comparators and a common bias
[(+V) - (2VBE) - (-V)]
ISET
RSET
BIAS CIRCUIT, COMMON TO
ALL FOUR AMPLIFIERS
r----
r-----------------------~~~------_4__O+v
I
I
I
I
I
+IN
i---t__o'SET
Q,
-'N o---+-----l--------1------l---
L-----~----~----_4------~--~~~-----4----~_o-V
Schematic of One Channel of the L 161
Plus the Common Bias Network
Figure 1
6·16
Siliconix
(1)
where +Y is the voltage to which the control resistor is con·
nected, -Y is the negative supply voltage, YBE is the base
emitter drop of Q9 or QIO (about 0.7 V), and RSET is the
value of the external control resistor or set resistor. Equation
I is simply a derivative of ohms law. There is also an analyti·
cal relationship between ISET and the total supply current:
ISUPPLY
= [rSET (current sourced by Q6 to Q8)
+ 2 ISET (current sourced to the differen·
tial amplifier by Q6)
Gain varies 10garithmicalJy with changes in supply voltage
and linearly with changes in set current. Primary causes are
the decrease in output impedance of Q7 with decreasing sup·
ply voltage and an increase in transistor betas with increasing
set current. Other AC parameters such as slew rate and
transition time are also effected by set current; however
current dependent parameters such as beta and chip capaci·
tances make mathematical expressions imprecise. These rela·
tionships have been determined emperically and are pre·
sented in Figures 3 and 4.
-.........
-
GIll
+ 2 ISET(current sourced to the compara·
tor output by Q6]
200
x 4 (the total numbers of comparators)
I
I
180
+ ISET (current sourced through QII,
QIO, and Q9 to -V)
160
140
V
rTRANsITIO~
LL
100
IL
60
40
The output current pulldown capability (IOL) of the LI61
is about 2 orders of magnitude greater than the high output
drive current, (IOH), which allows wire·ORing the outputs.
IOH is simply the current sourced by Q6:
IOH =2 x ISET
POSITIVE
/
80
21 ISET
V
V
NEGATIVE
120
[I SET + 2 ISET + 2 ISET] x 4 + ISET
1/
20
10
V-
1/
~I_
TRfNSIi"Ol
/
L
Vs=:: 15V
Y,N
= i
lOa mVp
RL = 10 Mn
CL = 10 pF
200
400
600
800
tOaD
'SUPPLY - SUPPL V CURRENT (I/AI
(3)
Slew Rate vs Supply Current
Figure 3
IOL is found by multiplying the current sourced by the
collector of Q6 by the gain of Q7:
(4)
IOL = (3 (Q7) x 2 ISET
1000
The beta ofQ7 is about 75·150.
<
...
...
~
~
Input bias current is a function of the betas of input devices
Q] ·Q2 and I SET . This is difficult to express analytically
because (3 varies greatly with both processing and collector
current; however it is roughly proportional to the set cur·
rent and can easily be determined experimentally (see Fig·
ure 2).
a:
""
~
'DO
~FALL TIME
RISE TIME
1"-
III
II:
...-.
Ol
I
~
-'"
II:
.§
10
1
l"-
10
::I
CD
100
a
RISE TIME 10% TO 90% (,..s)
~
Rise and Fall Times vs SupplV Current
With One CMOS Load
Figure 4
1
...
~
'"
"":1'"
;;
...
10
"~
I
:a
ffi
0.1
10
100
10K
lK
'SUPPl Y - SUPPL V CURRENT
(~AI
Input Bias Current vs Supply Current
Figure 2
The designer's ability to program the key parameters of the
LI 61 enables him to program just enough supply current to
meet his design objectives. This coupled with the LI61's
performance using only micro watts of power makes it ideal
for any micropower or battery·powered system, as well as a
replacement for existing higher power comparators. The
folJowing applications ilJustrate the flexibility and unique
capabilities of the LI 61.
Siliconix
6·17
-...
P '"
..0
-....
P'"
•
....
..0
Z
C
+5V
Micropower Applications
A classic comparator application is the double-ended limit
detector or window comparator shown in Figure 5. V OUT
is high whenever the input voltage is within the two limits.
Because the Darlington input stage extends the commonmode input range below the negative supply, the lower
limit may be as low as -0.4 V with the V- terminal at
ground. A comparison about ground is therefore possible
with only one supply.
ISUPPLY '" 8OOJJ,A
OUT
'ov
"3
1 MEG n
R2
lOOK n
-:
CMOS Line Receiver
Figure 7
Mating the L161 with CMOS logic is natural since the Ll61
draws microamps from a single 5 V supply. However, the
L161 will also drive TTL when a suitable pull-up resistor is
provided. Figure 8 shows this combination. Total power
drain of the circuit is much heavier due to the presence of
the 7402. Propagation delays through the circuit are about
I Jlsec.
+5 v
VOUT
Double-Ended Limit Comparator
With Wire OR'd Outputs
Figure 5
The L16l is especially suited for this application because of
its wire OR capability; low output on either comparator will
pull both outputs to ground. For this example a supply
current of 90 JlA was chosen to provide a slew rate of about
5 VIJls. If greater output drive current or decreased transition times are needed, lower R SET '
The zero crossing detector shown in Figure 6 is useful in
sine wave squaring circuits and AID converters. This circuit
also takes advantage of the L161's ability to detect signals
below its negative rail, so only a positive supply is needed.
The positive input may either be grounded or connected to
a nulling voltage which cancels input offsets and enables
accuracy to within microvolts of ground. The CMOS output
will switch to within a few millivolts of either rail for an
input voltage change of less than 200 JlV.
The circuit in Figure 6 may be modified to produce a line
receiver (Figure 7). The trip point is set half way between
the supplies by Rl and R 2; R3 provides over 200 mV of
hysteresis to increase noise immunity. With 800 JlA of quiescent supply current the maximum frequency of operation
is about 300 kHz. If response to TTL levels is desired, change
R2 to 39K. The trip point is now centered at 1.4 V.
Driving TTL
Figure 8
In many situations further power savings can be achieved by
reducing or eliminating ISET during part of the operating
time. This is desirable. for example, when a system is multiplexed at a low duty cycle. The Ll61 may be strobed off
completely by reducing ISET to zero as shown in Figure 9.
The 3N163 P-channel MOSFET is OFF when the strobe
input is high so no set current flows into the L161. For a
low strobe input, the 3NI63 turns ON, pulling RSET to the
positive supply and turning on the comparator. The drainsource resistance of the 3NI63 (3000 Q) is negligible compared to R SET ' If the negative supply terminal of the Ll61
is returned to ground, the 3NI63 may be eliminated and
RSET connected directly to the output of a CMOS gate.
The L161 will now be ON when the CMOS output is high.
When the L161 is strobed OFF, its outputs assume a highimpedance state; this "three state" operation facilitates the
connection of many outputs to a single bus.
+v
ISUPPL V - 10 .. A
+5Vo-'-~--~--------1--
ZERO DETECT INPUT
OUTPUT
-v
Strobing the L 161 ON and OFF
Figure 9
Zero Crossing Detector
Figura 6
6-18
Siliconix
The L161 will switch itself into a standby mode if one of its
outputs is connected to the ISET terminal as illustrated in
Figure 10. The diode blocks current when the output of Al
is HIGH, and operation of the other three comparators is
normal. When the output goes low, however, the IN914
conducts most of ISET to the negative supply. 10L is therefore nearly equal to I RSET, and (from Equations 2 and 4),
ISUPPLY = 21 ISET(actual) =
2110L
2B
= IRSET
10
(5)
lN914
Figure 11 shows an1161 low battery indicator which flashes
an LED when the battery· voltage drops below a certain
threshold. The 2N4274 emitter-base junction serves as a
zener which establishes about 6 V on the 1161 's positive
input. As the battery dies, the voltage at the negative input
drops more quickly; when the low battery threshold (typically 7.5 V) is reached, the 1161 output goes HIGH. This
turns on the Darlington, which discharges C I through the
LED. The interval between flashes is roughly equal to RICI'
which in this case is 2 seconds. By flashing the LED at a very
low duty cycle, this circuit gives a low battery warning with
only 10 p.A average power drain.
J>
Z
.....
.....
0I
-....
r-
-
0-
Waveform Generators
HIGH IS NORMAL
LOW .. STANDBY
Figure 12 is a square wave generator which is operable to
over 100 kHz while Figure 13 depicts the typical frequency
vs capacitance performance of the circuit. The low frequency
limit is determined only by the size of C I. Frequency is constant for supply voltages down to +5 V; below that the
charging rate of CI in the positive direction is determined
by 10H and not R 4 . For lower voltage operation, increase
R4 (and lower C accordingly) or decrease R SET .
+10V
Switching the L161 to a Low Current
"Standby" Mode
Figure 10
if a {3 of 105 is assumed. Equation 5 states that the supply
current of the 1161 is reduced from 21 xl RI (normal operation) to I R I/IO, a factor of 210 (or twice whatever (3 of
Q7 is). Total supply drain is simply the current through
R SET . This circuit has an important advantage over the
previous strobe circuit - even though the 1161 is operating
at a greatly reduced supply current, it is still ON and continues to function. If a lesser reduction in supply current is
desired, connect a resistor in series with the diode.
"2
lOOK n
III
Squarewave Oscillator
Figure 12
-.
r-
+9V
::I
CD
..a
'SUPPLV = 10/JA
",
1 MEGn
"2
TRIP
'6
5A~~S~~--'--I
2N4274
f - FREQUENCY (Hz)
Frequency vs the Value of C1
for the Squarewave Oscillator
Figure 13
A Low Battery Indicator
Figure 11
Siliconix
6-19
....•...
-
~
.....
•
.....
•z
r--------------------------------------------------------------------------------------,
feeds two variable window comparators formed by IC2A To generate pulses the positive and negative charging rates of
the capacitor must be unequal. Figure 14 illustrates a method
using diodes and unequal resistors. The duty cycle of the
output pulse is equal to R4/(~ + RS) x 100%. For duty
cycles ofJess than 50%, 1 can be eliminated and R2 raised
according to the formula,
IC2B and IC2C - IC20 respectively. The voltage on pin I of
ICIA ramps up as CI charges through RI' When this voltage
exceeds approximately 5 V (the potential on pin 20fIC IA),
the output of IC IA goes lllGH, forcing IC IB and ICIC
LOW. C 1 is quickly discharged by 10L of IC I B, and the
comparators reset to their normal state (ICIA LOW, ICIB
and IC IC HIGH).
°
R·
_ R5 x R4(eft)
4( actual) - RS - R4(eft)
II(
(6)
As the ramp rises, its value passes through the two windows
defined by the differences between the voltages on R4 and
RS in the case of <1>1, and R6 - R7 for <1>2' IC 2 is set for a
supply current of 20 f.lA; at this level its slew rate is too
slow for the window comparators to respond to the fast
negative transition of the ramp. By adjusting R4 - R6, 1,
and <1>2 may be set for any width up to the period of the ramp
(Figure 16 contains typical waveforms). If longer pulse
lengths are needed, increase Cl since t (ramp) 0.7 RICI
(neglecting IOH of IC I Band IC I C>. A higher rep rate is
obtained by lowering Cl but RSI and RS2 may also need
to be lowered to insure IC I and IC 2 have adequate slew
rates.
where R 4(eff) is the effective value of R2 in the circuit and
R4(actual) is the actual value used; R4(actual) will always be
larger than R 4(eff)' A similar analysis could be made for
eliminating 02 when t > 50%. Figure 13 may be used to
determine frequency (= I/period) if 1/2 (R4 + RS) = lOOK.
+10V
0,
R,
JOOK n
=
02
1N914
1N914
R4
56K n
*
AS
560K
n
c,
~'~'-+-o~
0.00'
I
100/olS
CAPACITOR
I
=::=::c:::=::"'~7.~:o-PTIN-2-'C..!,---.,...-......:.---""'---REFERENCE
V~~:~E =.-'-P~IN~'~'C;2~:j::;;;;;i"f==----+__j__:::;::;-~=---___1b......+-- REFERENCE
PIN 11C2
1MS
"2n
REFERENCE
PIN 4 re2
lOOK
",
PIN 61C2
CLOCK
100Kn
"
Pulse Generator
Figure 14
CLOCK
,2
The versatile two phase clock generator of Figure IS uses
two L161's to generate pulses of adjustable widths and phase
relationships. ICI is the heart of a ramp generator which
t=O
350j.lSEC
Typical Waveforms of the Two Phase
Pulse Generator
Figure 16
,ov
ISUPPLY" 350 /lA
250K
n
'6
RSET2
10Mn
",
,ov
50KU
CLOCK
",
75Kn
C
To.01;.1F
..l..
"2
SDK
oJL5L
11
" +-------<
10V
CLOCK
A Versatile 2<1> Pulse Generator
Figure 15
6·20
SilicDnix
rl
o~
r1
L-J L
Figure 17 is a low power D.C. to D.C. converter obtained by
adding a flyback circuit to the square wave oscillator. Oper·
ating frequency is 20 kHz to minimize the size of Ll and C 2.
Regulation is achieved by zener diode D 2 ; when the output
is less than -12 V, the zener breaks down and discharges
C 1 slightly which reduces the duty cycle of the oscillator
below 50%. Maximum current available before the converter
drops out of regulation is 5.5 rnA at an overall efficiency
of 71 %. With no load the converter draws 590 /lA.
performance is the low slew rate (0.3 V//lsec) imposed by
IOH charging Ccomp ' The effects of slew rate and compensation are shown in Figure 19. A lower gain amplifier
~
-
a-
"AX p.p OUT_
>
~
"'w-
10
:;'"
>-
::>
::::>
=VOUT FOR 0.005 V p.p IN
0
I
IIII1
-:
II IIIIII
0.1
lK
IIIIIII
1M
lOOK
10K
f - FREQUENCY 1Hz!
Frequencv Response and Maximum Output
for the X100 Op Amp
Figure 19
560K
u
-12V@5mA
A Regulated DC to DC Converter
Figure 17
Operational Amplifiers
While designed primarily as a comparator, the L161 will
perform as an op amp if proper compensation is applied.
Figure 18 is a simple gain of 100 amplifier with a gain·
bandwidth product of20 MHz! The primary limitation in the
requires a larger C comp ' which in turn further reduces slew
rate. For this reason it may actually be advantageous in
certain cases to lower the gain by placing a resistive divider
at the input rather than raising R l' Figure 20 shows a
700/lwatt XIO op amp whose slew rate is 0.02 V//lsec and
is 3 dB down at 100 kHz.
>3V
+15V
ISUPPLY '" 120tlA
R3
15K Il
>';:.3-+-<> OUT
",
2.2K !l
220K 11
"1
CCOMP
JO.001
lOOKH
910Ku
r
lOll
...-.
CCOMP
0.003
~
A Micropower X10 Op Amp
Figure 20
The L161 .s. X100 Operational Amplifier
Figure 18
CD
D
~
Siliconix
6-21
Regulating Pulse
Width Modulators
designed lor .
•
• •
H
Siliconix
BENEFITS
•
Direct Pin for Pin Replacement for
SG1525A/1527A
•
Improved Performance Over SG1525A/
1527A
o Greatly Reduced Crossover Current
Through Output Transistors
o Greatly Reduced Transients With
Separated Ground System
o Fully Operational Up to 200 kHz
Oscillator Frequency and a Typical 10%
Pulse Width
Switched Mode Power
Supplies (SMPS)
• Wide Versatility
o 8 to 35 Volt Operation
o 100 Hz to 500 kHz Oscillator Range
o Separate Oscillator Sync Terminal
o Adjustable Deadtime Control
o Internal Soft-Start
o Input Undervoltage Lockout.
o Latching PWM to Prevent Multiple Pulses
•
DESCRIPTION
Lower Overall Parts Count
o 5_1 Volt Onboard Reference Trimmed
to ±1%
o Dual 100 mA Source/Sink Output Drivers
The Si1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and
lowered external parts count when used to implement all types of switching power supplies. In addition to being a direct
replacement for the SG1525A/1527 A the Si1525B/1527B features low crossover current through the output transistors and
full operation up to 200 kHz while maintaining a typical 10% pulse width. The on-chip +5.1 volt reference is trimmed to
±1% initial accuracy and the input common-mode range of the error amplifier includes the reference voltage, eliminating
external potentiometers and divider resistors_ A Sync input to the oscillator allows multiple units to be slaved together, or
a single unit to be synchronized to an external system clock_ A single resistor between the CT pin and the Discharge pin
provides a wide range of deadtime adjustment_ These devices also feature built-in soft-start circuitry with only a timing
capacitor required externally. A Shutdown pin controls both the soft-start circuitry and the output stages, providing instantaneous turn-off with soft-start recycle for slow turn-on_ These functions are also controlled by an undervoltage lockout
which keeps the outputs off and the soft-start capacitor discharged for input voltages less than that required for normal
operation. Another unique feature of these PWM circuits is a latch following the comparator_ Once a PWM pulse has been
terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clo\=k
pulse_ The output stages are totem-pole designs capable of sourcing or sinking 100 mA_ The Si 1525B output stage features
NOR logic, giving a LOW output for an OFF state_ The Si1527B utilizes OR logic which results in a HIGH output level
when OFF_
PIN CONFIGURATION
Dual-In- Line Package
IfN
N.I.
If..lPUT~
'NPurlI
SYNC
't,..J
II
Si1525BK
Si2525BK
Si3525BK
~ OUTPUT B
~Vc
Cr~
DISCHARGE
ORDER NUMBERS:
~+VIN
OSCOUTPUT~
RT
~ VREF
~GND
~
See Package 10
~ OUTPUT A
12
~ SHUTDOWN
t!l
SOFT-START[!
COMPENSATION
-"---~
Top View
6-22
Si1527BK
Si2527BK
Si3527BK
Siliconix
BLOCK DIAGRAM
i---- vC--U.V.
LOCKOUT
REFERENCE
REGULATOR
13
I
I
I
Irl=::::::::::::::r~
11
'
JL
Q
_____aH=mV
F/F
R
COMPENSATION
9
S
)--------_---1
LATCH
~
_
14
Jl
~15~B~~~U:!T~E_1
I
I
I
I
11l)
50"A
SHUTOOWN
5K
101}----'V1Iv--+---[
50K
14lJ
5K
--:s....
..
CD
a
ABSOLUTE MAXIMUM RATI NGS* (T A = 25°e unless noted otherwise)
Supply Voltage (+VIN) ................. +40V
Collector Supply Voltage (Ve) ........... +40V
Logic Inputs ................. -0.3V to +5.5V
Analog Inputs ................ -0.3V to +VIN
Output Current, Source or Sink ........ 200 mA
Reference Output Current. . . . . . . . . . . .. 50 mA
Oscillator Charging Current ............. 5 mA
Power Dissipation at TA = +25°C** .... 1000,mW
Thermal Resistance: junction
to ambient. . . . . . . . . . . . . . . . . . . .. 100° C/W
Power Dissipation at Te =+25°C***.... 2000 mW
Thermal Resistance: junction to case .... 60°C/W
Operating Junction Temperature ....... +150°C
Storage Temperature Range .... -65°C to +150°C
Lead Temperature
(Soldering, 10 seconds) ............. +300°C
*Values beyond which damage may occur.
**Derate at 10 mwtC for ambient temperatures above +50oC.
*"*Derate at 16 mwtC for case temperatures above +25°C.
Siliconix
6·23
RECOMMENDED OPERATING CONDITIONS 1
Input Voltage (+VIN)' . . . . . . . . . +8V to +35V
Collector Supply Voltage (V C), .. +4.5V to +35V
Sink/Source Load Current
to 100 mA
(each output) . . . . . . . . . . . . .
Reference Load Current . . . . . . . . .
to 20 mA
Oscillator Frequency Range .. 100 Hz to 500 kHz
Oscillator Timing Resistor . . . . . 2k.l1 to 150k.l1
Oscillator Timing Capacitor . . . .001 p.F to 0.1 p.F
o
o
o
to 500.11
Deadtime Resistor Range . . • . . . . . .
Operating Ambient Temperature Range
Si3525B, Si3527B . . . . . . . . . . O°C to +70°C
Si2525B, Si2527B . . . . . . . . -25°C to +85°C
Si1525B, Si1527B . . . . . . . -55°C to +125°C
1 Range over which the device is functional and parameter limits
are guaranteed.
ELECTRICAL CHARACTERISTICS (+VIN = 20V, and over operating temperature, unless otherwise noted)
Parameter
S115258/25258
S115278/25278
Conditions
SI35258
SI35278
Units
Min
Typ
Max
Min
Typ
Max
5.05
5.00
Reference Section
1
Output Voltage
Tj = 25°C
5.10
5.15
5.10
5.20
2
line Regulation
VIN = 8 to 35V
10
20
10
20
mV
20
50
20
50
mV
50
mV
3
Load Regulation
IL = 0 to 20 mA
4
Temperature Stability 2
Over Operating Range
5
Total Output Variation 2
line, Load, and Temp
6
Short Circuit Current
VREF = 0, Tj = 25°C
80
100
7
Output Noise Voltage 2
10 Hz';; f';; 10 kHz, Tj = 25°C
40
8
Long Term Stability 2
Tj = 125°C
20
20
5.00
50
5.20
20
4.95
V
5.25
V
80
100
mA
200
40
200
/1Vrms
50
20
50
mV/khr
Oscillator Section 3
9
Initial Accuracy2,3
Ti = 25°C
±2
±6
±2
±6
%
10
Voltage Stability 2,3
VIN = 8 to 35V
±0.3
±1
±1
±2
%
11
Temperature Stability2
Over Opsrati ng Range
±3
±6
±3
±6
%
12
Minimum Frequency
RT = 150 kn, CT = 0.1 /1F
100
Hz
100
13
Maximum Frequency
RT = 2 kn, CT = 1 nF
400
14
Current Mirror
IRT=2mA
1.7
2.0
15
Clock Amplitude 2,3
3.0
3.5
16
Clock Width 2,3
0.3
0.5
17
Sync Threshold
1.2
18
Sync Input Current
Ti = 25°C
Sync Voltage = 3.5V
400
2.2
kHz
1.7
2.0
3.0
3.5
1.0
0.3
0.5
1.0
2.0
2.8
1.2
2.0
2.8
V
1.0
2.5
1.0
2.5
mA
2 These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
3 Tested at IOSC = 40 kHz (RT =3.6 kn, CT = .01 /IF, RD = On).
2.2
mA
V
/1Sec
CMCD
TENTATIVE DATA SHEET. This page provides tentative information on a new product. Siliconix reserves the right to
change specifications for this product in any manner without notice.
6·24
Siliconix
ELECTRICAL CHARACTERISTICS (CONT)
Parameter
Si 1525B/2525B
Si1527B/2527B
Conditions
Min
Error Amplifier Section (VCM
= 5.1
Max
Units
Typ
Max
5
2
10
mV
10
1
10
/lA
1
/lA
Min
Volts)
19
I nput Offset Voltage
20
Input Bias Current
21
Input Offset Current
22
DC Open Loop Gain
RL >10 Megn
23
Gain-Bandwidth Product 4
Av
24
Output Low Level
25
Output High Levpl
26
Common Mode Rejection
VCM
Supply Voltage Rejection
VIN
27
Typ
Si3525B
Si3527B
0.5
1
1
= 0 dB, Tj = 25°C
60
75
60
75
dB
1
2
1
2
MHz
0.5
0.2
5.6
3.8
= 1.5 to 5.2V
= 8to 35V
0.5
0.2
3.8
V
5.6
V
60
75
60
75
dB
50
60
50
60
dB
45
49
45
49
P.W.M. Comparator
28
Minimum Duty Cycle
29
Maximum Duty Cycle
30
Input Threshold 5
Zero Duty Cycle
31
Input Threshold 5
Max Duty Cycle
32
I nput Bias Current 4
0
0.6
%
0
0.9
0.6
%
V
0.9
3.3
3.6
3.3
3.6
V
.05
1.0
.05
1.0
/lA
80
/lA
Soft-Start Section
33
Soft Start Current
VSHUTDOWN
34
Soft Start Voltage
VSHUTDOWN
35
Shutdown I nput Current
VSHUTDOWN
Output Drivers (Each Output) (V C
37
38
1 - Output High Level
39
Undervoltage Lockout
Collector Leakage 6
42
Rise Time 4
43
Fall Time 4
44
Shutdown Delay4
50
25
80
50
0.4
0.6
0.4
0.6
V
0.4
1.0
0.4
1.0
rnA
0.2
0.4
0.2
0.4
V
1.0
2.0
1.0
2.0
V
Volts)
ISINK
1 - Output Low Level
41
25
= 20 rnA
ISINK = 100 rnA
ISOURCE = 20 rnA
ISOURCE = 100 rnA
VCornp and VSS = high
Vc = 35V
CL = 1 nF, Tj = 25°C
CL = 1 nF, Tj = 25°C
VSH = 3V, Cs = 0, Tj = 25°C
36
40
= 20
= OV
= 2V
= 2.5V
18
19
18
19
V
17
18
17
18
V
6
7
6
7
8
200
8
V
200
/lA
100
600
100
600
nsec
50
300
50
300
nsec
0.5
/lsec
0.2
0.5
0.2
,...
-:::s
..
CD
a
Total Standby Current
45
I
Supply Current
I
VIN
= 35V
I
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14
I
20
I
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14
I
20
I
rnA
CMCD
4 These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
5 Tested at IOSC = 40 kHz (RT = 3.6 kn. CT = .01 I'F, RD = on).
6 Applies to SiI5258/25258/35258 only, due to polaritY of output pulses.
TENTATIVE DATA SHEET. This page provides tentative information on a new product. Siliconix reserves the right to
change specifications for this product in any manner without notice.
Siliconix
6-25
H
Siliconix
AID Converters
l1li
Index
AID CONVERTERS
DEVICES
Page
LDll0/LDlllA 3% Digits, 2 V, 200 mY, 20 mV .................................................. 7-15
LD120/LD121A4% Digits,2V,200mV ........................................................... 7-41
LDl22/LD121A4% Digits,2V, 200 mV,20 mV .................................................... 7-66
APPLICATION NOTES
Title
ANSl-2
ANS1-l
AN74-1
AN77-1
ANSO-S
Introduction to Quantized Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Microprocessor Interface Techniques as Applied to the Siliconix A/ D Converter Family .......
Function/ Application ofthe LDll0/LDlll .............................................
Function/ Application of the LD120/ LD121A ...........................................
Function/ Application ofthe LOl22/LD121A ...........................................
7-1
7-11
7-23
7-50
7-70
DESIGN AIDS
DA74-1
DA77-2
Design Aid ofthe LOll0/ LOll1 ...................................................... 7-35
Design Aid ofthe LD120/L0121A ..................................................... 7-60
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Introduction to
Quantized Feedback
INTRODUCTION
Siliconix' "Quantized Feedback" (or charge
balancing as it is sometimes called) approach
towards AID conversion is an integrating technique,
implemented through the use of an analog processor and digital controller. Intrinsic features of this
approach are Auto-Polarity, Auto-Zero and ratiometric operation. As we shall see, this technique
offers superior linearity, normal mode rejection
and stability over that of other integrating techniques while at the same time requiring no critical
components except a stable voltage reference.
Recalling basic op-amp operation, it is easy to see
that the output voltage Vo is equal to the algebraic
sum of VSI and VS2 appropriately scaled. By
taking this simple adder circuit and a few
DIGITAL
REPRESENT A T I ON
Let's begin our discussion by considering the
following op-amp adder:
Figure 2.
II1II
Rudimentary AID Converter
.......
additional components it is possible to construct a
rudimentary AID converter as shown in Figure 2.
....
..
RI
VS20--t--'l'N,.,-----'
Vo
Figure 1.
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VSI must be stable
0 during conversion :. requires SIR in front end.
VSI
VS2
R< - - - :.
R2
Vo R<
If VS I is the unknown voltage that we would like
to measure and VS2 an input voltage that we
control, then by examining the state of V0 and
feeding back a VS2 sufficient to cancel out VSI,
(Le. keep V0 as close to zero as possible) we can
digitally keep track of VS I as diagrammed in
Figure 2.
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This is the technique used by successive appro ximation and counting type converters. Although
conceptually simple and apparently easily implemented, this technique is entirely dependent upon
the linearity and stability of the feedback D/A. In
addition, the complexity of a very high precision
DI A (greater than 8 bits input) which would be
necessary to construct a high-precision A/D could
prove prohibitive both in cost and circuit
complexity. A more accurate and less complex
approach as we shall see, would be to feed back
just 2 voltage levels (say + Vrefl, -Vre f2) instead
of the multitude of voltages possible with a D/A.
However in using this approach we become
interested in the time average of the feedback
voltage as compared to the voltage under
measurement, since we are now restricted to 2
voltage levels which should bracket the input
voltage to be measured.
VS1 VS2
we are interested in integrating ( - + ) is in
RI
R2
reality a current. But recalling that the integral of a
current is charge, Q = f idt, what we are really
trying to balance in order to keep V0 as close to
zero as possible is the charge on the capacitor C as
supplied by VSI and VS2' But since in our
averaging process the feedback VS2 can only
assume one of 2 voltage levels for an integer
number of time units. we can only add or take
away capacitor charge in quantum lumps (-l/C
Vrefl dt
Vref2 dt
), thus giving us our
R
or + l/C
2
R2
technique name quantized feedback. A block
diagram of such an AID converter is shown in
Figure 4.
This being the case we now want to change our
simple op-amp adder (of Fig. 1) into an integrator
(Fig. 3) to perform the necessary averaging
function.
f--
IREF
A/S
VSI
c
RI
VSI o---AV\jI\r--~
DIGITAL
REPRESENTATION
VS2o---YlJ\r---.l
Va
1
Figure 4.
Quantized Feedback AID Converter
Figure 3.
Op·Amp Integrator
whereVO=-I/Cf(:~1
+
Once again VS 1 is the unknown voltage we would
like to measure and VS2 one of two voltage levels
returning from our feedback network. We examine
Vo and feed back a voltage (VS2) such that the
time average of VS2 is sufficient to cancel out the
analog unknown, VS I. However since the input
node (point A in Figure 3) to our analog adder is
really a virtual ground, what we are really trying to
balance out are the 2 currents flowing into the
VS1
VS2
node (i.e. and - ) . This is easily seen in the
Rl
R2
integrator circuit (Fig. 3) where the quantity that
7·2
Figure 4 is the quantized feedback technique in its
most basic form. As previously mentioned, by
feeding back only 2 voltage levels we can
significantly improve our linearity and accuracy in
high precision measurements while reducing our
feedback circuit complexity to a switch and stable
voltage reference. Although our digital control
logic is now somewhat more complex as compared
to a counting technique, we are able to effect
significant gains in precision with only modest
increases in digital control circuit complexity. And
since in this technique both the unknown and
reference voltages are simultaneously integrated
with the objective of keeping the integrator output
as close to zero as possible, large voltage swings at
the integrator output as typically seen in Dual
Slope converters are avoided, thus easing integrator
requirements. This dynamic feedback measurement
process also ensures equally spaced count transition windows under varying conversion rates; even
Siliconix
around zero. Although timing is now critical to
proper high resolution operation, our task is easily
met through dedicated digital-control logic. Another feature inherent in this technique is that
since we are trying to balance charges which are
proportional to the input voltages, scale changes
are easily accomplished through simple ratiometric
resistor (R I and R 2) changes (i.e. Fullscale ~
RI/R2)·
measuring single ended inputs (i.e. no common
mode voltage). Siliconix however, has overcome
these problems through an enhancement of the
basic technique in which only I polarity Vref is
necessary for auto-polarity operation and where a
zeroing measurement is automatically performed.
Briefly, the way it is done is through the use of
negative feedback to impress a system offset
voltage when zeroing.
The basic principles underlying the quantized
feedback technique should now be apparent, as
well as the fundamental relationship between the
voltage-under-measurement (VIN' formerly VsO
and our 2 feedback voltage levels Vrefl and Vre f2.
That is, the current supplied by VIN must be of
opposite polarity and lie within the range bounded
by the reference currents, I re f2 < lin < Irefl, (see
Fig. 4) in order for VIN to be measured. So in
order to measure a ± VIN using our simple system,
we would have to supply both a ± reference
voltage. We are also limited in our simple system to
Let's now look at Figure 5 which is a diagram of
the analog processor architecture as found in the
Siliconix LDIIIA, LDl20 and LDl22 (the input
buffer is user-supplied). Note that outside of a
few additions, this circuit closely resembles our
basic Quantized Feedback Converter (Figure 4).
We still have the integrator summing node, pin 9
fed by a voltage reference source, unknown input
voltage source, and (new here) an Auto-Zero
(whose use will soon be explained) voltage source.
The control logic near the Auto-Zero buffer is
used by the digital controller to implement the
LD IliA
LD 120
LD 122
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Figure 5. Silica nix Analog Processor
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measurement algorithm. All of the inputs are now
unity buffered so that loading effects on inputs
are effectively eliminated. As before the output of
the integrator is fed to a comparator whose output
COMP S is monitored by the digital control logic.
A feedback control signal UP/DOWN, U/D 4 ,
from the digital controller determines which of
2 reference voltage levels (Vref or GND) are to be
fed back. The addition of the Measure/Zero
M/Z 3 control line permits the division of our
sampling process into 2 parts, a zeroing and a
measuring interval.
The aforementioned system offset impression is
accomplished in an auto-zeroing interval which is
of sufficient duration to ensure equilibrium
conditions. In the auto-zeroing interval the M/Z
line is set low, connecting the input buffer to the
input signal ground (or negative input if doing
differential measurements). With the combination
of the other 2 control lines UID and COMP, the SR
latch is set, forcing the switch between pins @
and qj) closed. The digital control logic toggles
the U/D line at a SO% duty cycle rate, thereby
feeding a doc pulse train (of amplitude Vref) to the
reference buffer. Ignoring all other contributions
to the sum node, the reference buffer will
contribute a current equal to VredRI to the node
half of the time with the average current being
Vref
- - . The output of the integrator feeds the
2RI
comparator, but the comparator output is ignored
in the zeroing interval so that this route can be
disregarded for now. By virtue of the closed
Auto-Zero switch however, the integrator output is
also fed back to the A/Z buffer which in turn
supplies current to the integrator summing node
thereby forming a closed negative feedback loop.
Along the way though, the integrator output Vo
charges up a capacitor CSTRG which, as we shall
see, is instrumental to proper operation. Resistor
R4 is used to guard against oscillations by assuring
'that the negative feedback gain is less than unity.
RS is used to provide low pass filtering action in
conjunction with CSTRG. Now since our buffers
have such high input impedances, let's assume that
the voltage on CSTRG is the same as that on
pin @ ,the input to the A/Z buffer or VSTRG·
Because of the filtering action provided by RS CSTRG, VSTRG will be the average of the
integrator
output.
Therefore,
a current
VSTRG/R3, opposite in polarity to that supplied
by the reference buffer will be fed to the summing
node. With a little imagination we can envision that
7·4
the DC or time average of all the currents flowing
into the integrator sum node will eventually cancel
each other out and in eqUilibrium the net current
will equal zero. There will however, be an
integrator output voltage Vo the average of which
will be VSTRG and both will be opposite in
polarity to the Vref voltage. Thus far all mention
of the input buffer and error/offset currents have
been avoided, but it can easily be seen that any
current supplied through the input buffer from the
negative differential input (Hi-Quality Ground
(1) ) as well as any error currents will simply
either aid or oppose the A/Z buffer in its attempts
to balance out current from the reference source.
Consequently in equilibrium, the VSTRG will be
shifted slightly from what it would have been had
none of these other current sources been present.
Of course we assume that these additional sources
do not change appreciably with lime when we later
move into the measurement interval. The key point
to remember here is that the reference buffer is
constantly supplying an average current of 1/2
Vref
(--) to the integrator sum node and in auto-zero
RI
equilibrium the sum of all other sources of current
(A/Z, INPUT, ERROR) are equal and opposite to
Vref
1/2 (--). This auto-zero equilibrium current
RI
Vref
VSTRG
balance ( - )
- - - (supplied by A/Z,
2RI avg
R3
INPUT, etc.) = 0 is our desired offset impression
and its use in the measurment process will now be
described.
One of the things that we have succeeded in doing
in the auto-zeroing process is to determine the
average integrator output voltage level ( VSTRG or
A/Z output buffer voltage) when our system is
zeroed. By tracing back the negative input of the
comparator, we can see that this is the voltage that
our integrator output is compared against when we
actually do our measurements. When we leave the
auto-zeroing interval to do a measurement, the
M/Z line goes high, reconnecting the input buffer
to the + end of the voltage under measurement and
opening the switch between @ and qj) . We can
now appreciate the importance of CSTRG, for in
addition to averaging out the integrator output, it
holds for us the value of VSTRG necessary for
proper comparator operation and charge balancing.
During the measurement interval VIN begins to
supply current to the sum node and the
comparator output is closely monitored by the
Siliconix
digital controller. In response to the state of
COMP, the controller feeds back either Vref or
GND to the reference buffer by toggling the UID
line. Measurement now is exactly as described in
our simple AID converter circuit (Figs. 3 & 4).
However since all of our equilibrium conditions in
Vref
auto-zero were calculated with an average -2being fed into the reference buffer, feeding back a
constant Vref will result in a net current over and
above that in equilibrium of + Vre r/2R 1 being sent
to the sum node. Likewise feeding back a constant
GND will cause a net current of -Vrer/2Rl (from
A/Z, etc.) to flow into the sum node. So whatever
polarity VIN may be, we will be able to balance it
out with appropriate resistor scaling. An interesting
aside here is that in all of our discussions the
absolute polarity of Vref (Le. + or - with respect
to GND) was never specified and any polarity
could have been used with equal, but differing
polarity results. However due to the nature of the
switch Siliconix uses with the Vref buffer (PMOS)
only positive references will work.
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THE "QUANTIZED FEEDBACK" ALGORITHM
The measurement algorithm used by all of our
digital processor chips (LDllO, 114, 121 A) is
basically the same. There are some minor variations due to slightly different analog control
structures and the different precision that each
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BCD OUTPUT
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DIGIT STROBES
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processor offers. For an example, the LDllO
(114),3% digits and the LD121A, 4% digits.
The LD114 is the same as the LD110, but with
additional digital functions pinned out. All chips,
though for greater stability and accuracy derive
their timing from a stable clock signal generated
either internally or externally. Inside the chip
the clock is further divided by 2, or split into
a 2-phase signal as the case may be. However,
for our discussion, the timing signal as used by
all of the internal circuitry will be the clock.
Figure 6 shows the internal organization, pinout
and typical analog processor interfacing for each
of the digital controllers.
BCD OUTPUTS
DIGIT STROBES
10
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REFERENCE BUFFER
4
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UiO
5
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7·6
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Every sampling interval is composed of an integral
number of clock periods (LDI 10= 6144, LDl21A =
49,152). The sampling interval can be further
subdivided into 2 operational periods, the AutoZero (AIZ) and Measure intervals. The A/Z interval, as we know, gives us a means of nulling offset
voltages and establishing a second tracking reference
voltage necessary for bipolar conversion. The
interval is signified by the Measure-Zero control
line (M/Z) going low and consists of the following
number of clocks: LDlIO = 2048, LD 121 A =
16,384. In the Measurement interval (when MIZ =
1), the actual charge balancing process is implemented and consists of the following number of
clocks: LDllO = 4096, LD12lA=32,768. As you
may have noticed, A/Z makes up 1/3 and Measure
Interval 2/3's of the sampling interval. The reason
why such a significant fraction of time is devoted
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to AID to insure that equilibrium zero conditions
are attained. The M/Z line is the principal signal to
the analog circuitry to tell it which interval it is in
so that the appropriate switches can be closed. The
Up-Down (U/D) line, on the other hand, is responsible for controlling the reference voltage fed back
in the A/Z and Measure Intervals. As we may recall,
during the A/Z interval a 50% duty cycle pulse
train of VREF amplitude is fed back in the analog
system. This is accomplished by toggling the U/D
line once every 4 clocks in the LD 110 and once
every 8 clocks in the LD I 21 A.
Figure 7 shows typical waveforms in the auto-zero
interval for the LD 11 O. The LDl2l A has essentially the same timing except that twice as many
clocks are required for UID toggling.
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LD121A
LDll0
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CYCLE 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
CLOCK
INPUT
M/Z
1 ....______________________
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Figure 7
Auto-Zero Timing
Siliconix
7-7
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In the measure interval, where we attempt to
balance integrator charge, U/D is set in response to
the state of the COMP input, so that the
appropriate reference voltage will be fed back in
the analog system. A counter automatically
increments or decrements once every clock cycle,
depending on the state of the U/D line, so that an
accurate record can be kept of the net number of
charge packets fed back. Ordinarily one would
think that once every clock cycle the U/D would
be set accordingly. However, since this technique is
as dependent on timing as it is 011 feedback voltage
level, we really have to be mindful of U/D
LD110
UfD DUTY CYCLE A
UfD DUTY CYCLE B
transitions since they bring with them error in the
form of rise and fall time. One way around this
problem is to insure that in every measure interval
there is always the same number of U/D
transitions, irrespective of the unknown, YIN' This
can be done by dividing the measure interval into
an integral number of duty cycle periods in which
the U/D line can assume 1 of 2 duty cycle
waveforms. In the LD121A the duty cycle period
consists of 16 clocks while it's 8 in the LDllO.
The 2 duty cycle waveforms possible in each 16
or 8 clock period is:
n
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DUTY CYCLE COUNTER 10
STATE
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4
5
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17
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CLOCK
LD121A
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UfD DUTY CYCLE A
UfD DUTY CYCLE B
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DUTY CYCLE COUNTER 10
STATE
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5
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8
CLOCK
Figure 8 Duty Cycle Waveforms
7·8
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9
10
II
12
13
14
115
I
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So instead of depositing a maximum possible (±16
or ±8) charge packets every duty cycle period, we
have to be content with a net maximum of ±14 or
±6. Consequently the maximum counts possible
are: LDllO = 3072, LDl2lA = 28,672. However,
since these maximum counts are larger than the
advertised precision of the A/D's, overrange
capability is possible and built into some of the
converters.
Since we can only feedback rather large lumps of
charge (±14, ±6 counts), when the measure interval
comes to an end, there will, undoubtedly, be some
residual charge left over to be resolved to the
nearest count. This is done in a brief override
period at the start of the A/Z interval where
normal A/Z operation is temporarily inhibited
while we fine tune (i.e. abandon duty cycles and
feedback charge packets one at a time). The
override period starts at the end of the measure
interval when M/Z ~ low and the input buffer is
switched to input 'gnd' so that no more charge is
accumulated. The U/D line is set high and held
until the comparator goes high and the next state 8
of the duty cycle counter comes around at which
time U/D is set low. When the comparator next
goes low again, the override period is ended (M/Z =
0, COMP = 0, U/D = 0, Auto-Zero switch closes
initiating normal Auto-Zero action). The counter
which until now has been faithfully keeping track
of the charge packets fed back, is inhibited and its
count used to update the data outputting latches
on the next clock pulse. Figure 9 shows typical
Measure, Override, and Auto-Zero waveforms in an
LDl20/LD 121 A system.
Now that the measurement algorithm has been
described, a few words about the relationship
between the count and unknown input voltage are
in order. What the count represents is the net
V REF
1
number of reference charge units ( ± - - - - )
2RI fCLK
which were needed to cancel out the charge as
supplied by the unknown input
VIN
# clocks in measure interval
(-
R2
~
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...
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fCLK
Neglecting signs, this equality is:
VREF
1_
COUNT - 2R 1 - fCLK VIN # clocks in measure interval
rearranging, this becomes:
V IN
Rl
COUNT=-- - - - 2
VREF R2
(# clocks in measure interval).
For an LD121A with 32,768 clocks in the measure
interval, this equality becomes:
V IN
Rl
COUNT=-- - - - 65536
VREF R2
'
By manipulating the resistor ratios and VREF we
could theoretically scale the A/D to any input
voltage range desired. Practical circuit limitations,
though, prevent us from getting carried away.
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U/D DUTY CYCLE A
U/D DUTY CYCLE B
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DUTY CYCLE
COUNTER STATE
9
0
10
11
12
13
14
16
CLOCK
M/Z~
DUTY
----------~--------A--------~~--------
CYCLE
un________
UlO~
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COMPARATOR SAMPLE
POINTS FOR NEXT
DUTY CYCLE SELECTION
COMPARATOR
OUTPUT _ _ _ _.....
INTE~~~~~~~--~~~~---------------------------------4-----------------~~~----------~~--_____________
COUNTER CONTENTS. -14
DUTY CYCLE
CONVERTER
STATE M/Z
U/o
INTEGRATOR
OUTPUT
VSTRG
-14 NET COUNTS ADDED
TO COUNTER TOTAL
COMPARATOR
Figure 9. Up/Down and I ntegrator Waveforms
7-10
Siliconix
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Microprocessor
Interface Techniques
As Applied
to the Siliconix
AID Converter Family
INTRODUCTION
When attempting to interface a microprocessor system with
a peripheral device (in this case an A/D) that operates at a
substantially slower speed, the communications process between the system and peripheral can be thought of as lying
between two extremes, synchronous and asynchronous
operation. Either mode of operation will offer trade-offs
between speed or throughput, and hardware complexity.
For instance, in a synchronous communications approach,
overall system speed is effectively reduced to that of the
slow peripheral as the system must wait for a response or
handshake from it. In an asynchronous approach however,
both the system and the peripheral are able to operate at
their own respective clock rates, with the speed differen tial
problem being solved through the use of an interface buffer
between the two. Hardware complexity is considerably
higher here though than in a handshaking synchronous in terface because such an asynchronous buffer is usually implemented through the use of latches to retain all of the data.
proach taken is the use of a peripheral interface chip such as
an 8255 PPI or a 6820 PIA. While this approach will ultimately get the job done, it's extremely costly in terms of all
of the negative features of both asynchronous and synchronous approaches (high hardware cost - peripheral interface
chips aren't cheap; slowness - we are essentially operating
synchronously with the A/D). As an added drawback,
there's the software overhead necessary to initialize the
chip and implement the synchronizing software routines.
It's possible however, as we'll soon see, to construct totally
synchronous and asynchronous interfaces out of common
TTL parts costing only 1/3 to 1/2 the price of a peripheral
interface chip and requiring none of the software overhead.
The circuits to be presented were built with the LDI2IA,
but are of a sufficiently general nature that they can
easily be modified to accommodate the other A/D's in the
Siliconix product line.
More often than not in A/D application notes or data sheets
where an interface to a microprocessor is shown, the ap-
Siliconix
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LD121A DATA FORMAT
Just to review, Figure I shows the output data format of
the LD121A digital controller and as you can see, data is
BCD and sent out digital serial - bit parallel, perfect for
multiplexed displays for which it was designed. The sequence in which the BCD digits are sent out is D5, D4,
D3, D2, D1, repeating continously as indicated. Note that
the BCD data for a particular digit is available (16 LD121A
clock cycles) both before and after the digit strobe comes
on, a feature of which we shall make good use. Sign data
appears 250 ns after the D5 strobe and is valid for the duration of D5. Although not shown here, a means of deter-
CVCLES
D5
~
t-r--,-----640CLOCKCYCLES
1-96--1
r---:
______
32CLOCK1
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mining that the A/D has completed a measurement and has
new data available is the positive edge of a signal called
M/Z which occurs once every measurement interval. Complete LD120/LD121A operational information may be obtained by consulting the data sheet. All of the LD121A
digital output signals can drive 1 standard TTL load and the
M/Z line - 1/2 a load, a factor which contributed to the
use of 74L8 parts as much as possible in my circuits.
Since the synchronous interface is the simpler of the two,
let's start with it first.
---------11
___________________
______________________ ____________________
__________________~r--l~
~r---l~
~n'L
n3 ____________~r---l~
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_______________________________
D2------------------~r---l~------
_____________________________
D, ________________________
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·2 -----~
·3
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DATA
0
SIGN/OR/UR
POLARITY
BLINKING
INHIBIT
1
tIt
I
OVERRANGE/UNDERRANGE SIGNALS
00 NOT REPEAT UNTIL THE
OVERRANGE 2
>25,000
INPUT
NEXT CONVERSION CYCLE
OVERRANGE 1
;;. 20.000
UNDER RANGE
<:; 1,799
Figure 1. LD121 Digital Output Timing Diagram
SYNCHRONOUS AID INTERFACE
In Figure 2 we have the schematic of an LD121A synchronous interface which was built and operated in an Intel
SDK-85 .system. Key to the operation of this circuit is the
READY line which can be found on Intel, MOS Technology
and other microprocessors. For those not familiar with it,
the READY line is an input to the processor through which
slow memories and in this case, slow peripherals can make
the processor wait while data to be read in is being placed
on the data bus. In this way the processor can be SYNCHRONIZED to the rate at which the slow peripheral is
giving data, while running at full speed when other, faster,
memories and peripherals are being accessed. The operation
of the circuit is as follows. Normally the output to the
READY input, A5 pin 5 is high, permitting full-speed processor operation. To accomplish this, all of the inputs to A5
must be low which is possible if none of the first 5 outputs
of the 4 to 10 line decoder are active (low). Although the A,
7-12
B, C inputs of A2 may change continously, by using the D
input as a chip enable, the outputs in question will remain
high. However when a valid chip select (read peripheral
operation) comes along, the tristate bus buffer Al will be
enabled as well as the 4 - 10 line decoder. Now depending
on the valid address on ADR 0, 1,2 one of the decoder outputs, corresponding to a particular LD121A digit, will go
low. Assuming that all of the digit strobes are low (inactive),
the READY line goes loy.' causing the processor to wait up.
As soon as the digit strobe in question goes high, indicating
valid data is available, the READY line rises again allowing
the processor to continue its read operation. Note that the
digits may be read in any order as the synchronization is
accomplished automatically. However the processor does
have to wait for the right digit strobe to come along. The
74LS74 D type F.F. in the circuit is used as an interrupt
indicator latch, generating a latched high level interrupt
Siliconix
signal when the positive M/Z edge comes along (new data
ready) and resetting when a data read occurs. Depending
on how the chip select is generated, the circuit may be set
up as regular or memory mapped I/O, the choice is up to
the user. As set up, the BCD data is located in ,he low data
nibble and the sign is the high order data bit. However considerable lattitude is possible both in data word configuration and parts selection, particularly in choosing the tristate
bus buffer and decoder chips.
Lastly, after receipt of a valid chip select there's only a 3
gate delay in generation of a correct READY signal, permitting the circuit to be used with even the fastest of
processors providing that they have a READY input.
ASYNCHRONOUS AID INTERFACE
In Figure 3 we have the schematic of an asynchronous
LD121A interface, also built and operated with an SDK-8S.
Although it's somewhat more complex than:the previous circuit, relatively common parts are used and hardware costs
are still well below that of a peripheral interface chip.
Briefly, this circuit uses a 210lA memory as a S word X 4
bit latch to store the BCD data for immediate access later
on by the microprocessor (Le. no wait states). The 210lA
was chosen because of its separate data inputs and outputs
and is relatively cheap as far as memories go. Ordinarily
LDI21A BCD data is being written into the 210lA memory
at addresses determined by encoding the LD 121A digit
strobes into 3 bit binary. The encoding is done by the A4
OR gates and the address is gated to the memory by the A2,
A3 AND-NOR gates.
Note that 1/2 of the A3 AND-NOR chip is used to permit
the storage of sign information as data bit DI4 during digit
strobe 5. The memory write pulse is generated by A7 and
A8 and is a low level pulse of minimum duration so as not
to interfere during microprocessor reads (Le. lock up the
AS read-write arbitrator logic unnecessarily). Note the
0.01 pF capacitor on the trigger input to the A8 monostable. It's used to delay the generation of the write enable
pulse so that the sign information which is slightly delayed
from DS (by 2S0 ns) will be valid. AS is arbitration logic
which determines whether a microprocessor read or LD 121A
data write is to be performed on the 210lA memory. The
AS outputs, pins 3, 6 control the A2, A3 AND-NOR gates
and determine whether the 210lA memory address is to be
supplied by the system address bus (read) or encoded digit
strobes (write). AS is also set up so that if a data write pulse
is present from the monostable, its output pins 3, 6 will not
change state (Le. lock up). However when the write pulse
ends, AS will change state if necessary to reflect whether
or not we have a valid chip select present (microprocessor
read). If sO,it will enable the memory data bus drivers,
lock out monos table write pulses and gate the system
address bus to the 210IA memory so that the read can
be performed. When the chip select is in control of the AS
logic, further updating of the memory by the LDI21A is
J>
inhibited until the chip select is removed.
Although I was using a 2101A-2N with a 2S0 ns access
time, measurements showed that data could be obtained
within 2S0 ns after application of a valid chip select, providing that there was no monostable write pulse to lock up
the AS logic at the time. In which case it would have taken
2S0 ns plus the width of the monostable write pulse. However I found it very difficult to coiricidence the chip select
and write pulse since the write pulse is so short and so
infrequent. So except on very rare occasions, my read
access time from application of a valid chip select was at
most 2S0 ns. By being careful about how and when the
processor determines that there is new data to be read in
(Le. further qualify the interrupt signal) any possible coincidence of chip select and write pulse can be totally
avoided.
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As in the previous circuit, the A9-74LS74 is used as an
interrupt latch. The entire circuit is of sufficiently general
purpose design that the only real limitation to using it with
any processor is its 2S0 ns access time. Again, depending on
how the chip select is generated the circuit may be set up as
either regular or memory mapped I/O.
Through careful examination of both the asynchronous and
synchronous schematics it can be seen that in each, the
correspondence between a system address supplied and the
BCD digit read is:
ADR2
ADR 1
ADRO
Digit
0
0
0
Ol
0
0
0
02
0
1
0
03
0
1
1
04
1
0
0
05
A rough estimate of the savings in time possible using an
asynchronous rather than an synchronous interface approach in this application would be something on the order
of 1 complete LD121A data output cycle each time we read
in all S digits. For a LD121A running at maximum clock
frequency (2S0 KHz, S conversions/second) this is a savings
of about 2.S milliseconds each and every time. Since the
asychronous circuit acts as though it were memory as far
as the processor is concerned, the amount of time necessary
to read in new data from it is essentially how quickly the
processor can execute memory or I/O read commands, as
the case may be, providing of course that read access times
are met.
REFERENCES
1. Intel MCS-8S Users Manual, September 1980 Intel
Corporation.
Siliconix
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1 2 A6-74lS74
74LS367 HEX BUS DRIVERS. 3 STATE OUTPUTS
A2-74LS424 LINE TO 10 LINE DECODERS, BCD TO DECIMAL
A3-74LS02 QUAD 2 INPUT POSITIVE NOR GATES
A4-74LS02
AS-74LS2S0 DUAL 5 INPUT POSITIVE NOR GATES
A6 74LS74 DUAL 0 TYPE F F
LO 121 SIGN
Figure 2. Synchronous Interface
LDI21-SIGN ,----~R
LOl21-0S
LD121-B3--'::""--I-!-IL...._,/
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L__
INTERRUPT
lo121-BO Lo121-B1
Lo121-B2
LD121-01
15
L0121-02
01,
LD121-D3
LD121-D4
lO121-D5
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250ns ACCESS TIME
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L0121-04
SYSTEM
ADDRESS BUS
ADR 1
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PARTS LIST
Al-2101A-2N
A2-74LS51
A3-74LS51
A4 14LS32
A5-14LSOO
A6-14LS04
A1-14LS260
AS-74121
A9-14LS74
Figure 3. Asvnchronous Interface
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Siliconix
SYSTEM DATA BUS
22
-SV
31f2 Digit AID Converter Set
designed for . . .
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Siliconix
BENEFITS
• High Performance Digital
Voltmeters
• Digital Panel Meters
• Digital Instrumentation Readouts
..
....
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r-
o Three Usable Ranges with a Single Resistor
Change. 1.999 V, 199.9 mV, 19.99 mV
• Excellent System Performance From Basic
0.02% ±1 Count Accuracy
• Wide Sampling Rate: 1/3 to 40/Second
• High Gain Stability (5 ppm/oC) with Buf·
fered Reference Input
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•
• Microprocessor AID Interface
Subsystem
• Auto-Zeroed Microvolt or StrainGauge Systems
Reduced Signal Loading with MOSFET
Input (liN> 109 S1)
• Auto-lero System Minimizes Internal and
External Offset and Drift Over Temperature
• Auto·Polarity with a Single Reference
• Easy Interface to Displays with Strobed
BCD Output Format
• Overrange and Underrange Signals Available
DESCRIPTION
The "Quantized Feedback" conversion scheme used in the LD110/LD111A set provides an Auto-Zeroing, Auto·Polarity
A/D system requiring only a single reference voltage.
The monolithic LD111A high performance analog processor contains a bipolar comparator, a bipolar integrating amplifier,
a bipolar reference amplifier, two MOSFET input unity gain amplifiers, several P-channel enhancement mode analog
switches and the necessary level shifting drivers to allow the analog and digital processors to be directly interfaced. The high
impedance input and reference buffer amplifiers eliminate source loading errors and provide the outstanding temperature
coefficient inherent in this system. Break-before·make switch action insures that neither the analog input nor the reference
voltage will be shorted to ground at any time.
The PMOS LD110 synchronous digital processor combines the counting, storage and data multiplexing functions with the
random logic necessary to control the quantized charge-balancing function of the analog processor. Seventeen static latches
store the 3 1/2 digits of BCD data as well as overrange, underrange and polarity information. Nine push-pull output buffers
(capable of driving one standard TTL load each) provide the sign, digit strobe and multiplexed BCD data outputs, all of
which are active high. The digit scan is an interlaced format of digits 1,3, 2 and 4.
FUNCTIONAL DIAGRAM
PIN CONFIGURATIONS
Dual-In-Line Package
PARALLEL
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ABSOLUTE MAXIMUM RATINGS
liN (Pin 15,2).
V1 - V2 (LD111A)
VSS
VSS-V2(LD110)
V On Any Pin Relative to VSS (LD110)
VREF
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30V
6V
20 V
0.3 V to -20 V
V1
Operating Tern perature
Storage Temperature
Power Dissipation (Package)'
o to 70°C
-65 to +125°C
750mW
'Device mounted with all leads welded or soldered to PC
board. Derate 6.3 mWfC above 25°C.
ELECTRICAL CHARACTERISTICS
All DC parameters are 100% tested at 25° C. Lots are sample tested for AC parameters to assure conformance with specifications.
Characteristics
-
1
Linearity
2 G
I- E
-
3
4
5
1-
-
Typ
Min
Noise
N
E
R
A NMR
L
fiN
Gain T.C.
6
rDS(on)
ON Resistance, Auto Zero Switch
7
ICL
Clock Input Current, Low
I
N
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9 U
T
10
IINL
B
1-
12
1- A
0.1
LSB
dB
fnoise = 60 Hz
30.7
250
kHz
50% Duty Cycle
6
20
Kn
VAZlin) = -4.0 V, IS = -30 I"A
-500
I"A
pA
40
Isource
Reference Buffer
Isink
AZ Buffer
-1500
-700
-400
-800
TA = 70°C
-50
I"A
M Isink
1- P
14
Isource
BOO
Input Buffer
400
BOO
V AZ = -4 V, VOUT = 0 V
Input Buffer
-50
-100
VIN = -2 V, VOUT = 0 V
VIN=2V,VOUT=OV
1-
15
Voffset
AZ Buffer
16
VOLl
Measure/Zero Voltage, Low
VOHl
Measure/Zero Voltage, High
VOL2
Up/Down Logic Voltage, Low
17
1lB
1-
0
19
VOH2
1- U
T
20
VOH3
1- P
21 U VOL3
I- T
22
VOL4
-100
100
1-
VOH4
Up/Down Logic Voltage, High
2.4
Analog Comparator Voltage
2.4
VOH5
Digits, Sign Voltage, High
11
Supply Current
126
12A
27
S 120
U
P ISS
P
L PSRRl
V
PSRR2
1128
-
29
-
30
-
31
0.6
IOL = 250 I"A
IOH =-200I"A
IOH =-100I"A
IOL = 1.6 mA
0.65
2.4
24
IOL
V
Sign Voltage, Low
2.4
IOL = 1.6 mA
IOH =-200I"A
IOH = -800 I"'A
2.2
4.0
Supply Current, LDlll A
-l.B
-4.0
Supply Current, LOll 0
-17
-23
17.4
24
mA
Supply Current
Power Supply Rejection Ratio, V 1
80
85
Power Supply Rejection Ratio, V2
60
65
dB
Reference Voltage Rejection
1
%ardg/
aVREF
RREF = R2 = lOOK n, VIN = 2 V
Typical values are for DESIGN AID ONLY, not guaranteed and not subject to production testing
7·16
= 150l"A
0.6
0.6
Data Bits Voltage, High
VOUT=OV
IOH =-200I"A
Digits, Bits, Voltage, Low
25
mV
2.4
123
VIN = -12 V
VINL (U/D) = O.B V, VOUT = 0
I"A
13
1-
VCLOCK in = 0.4 V
TA=25°C
Input Bias Current
Camp. LDll0
Peak-to-Peak Noise Apparent When Going From
One Steady Readin" tu Alloih~r
ppm/DC
4
.11
% rdg
40
2
Test Conditions, Unless Noted:
V1 = +12 V, V2 = -12 V, VSS = 5 V
VREF = 8.2 V, TA = 25°C, R1 = 100K n
Unit
0.02
5
Normal Mode Rejection
Clock Frequency
Max
Siliconix
LD110IPANIl
LD11A CMAMI-A
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INPUT/OUTPUT SCHEMATICS
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LD110 COMPARATOR, CLOCK INPUTS
LD110 OUTPUT BUFFERS
(Digits, Bits, Sign, M/Z, UfO)
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BUFFER
AMP
HI-QGNO
(VREF)
M/Z
(UiOI
LD111A Comparator Output
LD111A Inputs NIN, VREF)
TYPICAL CHARACTERISTICS
Input Bias Current vs
Temperature
Supply Currents vs
Temperature
0
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V1 = 12V
V2--12V
Vss-SV
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40
50
60
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40
50
60
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DESCRIPTION OF PIN FUNCTIONS - LD111A
DESCRIPTION OF PIN FUNCTIONS-LD110
BUF OUT - The output of this unity gain input buffer am·
Vss - Positive Supply Voltage. Recommended level is +5 V
±10%.
plifier is applied to the integrator summing node through a
scaling resistor R2' The value of this resistor is typically
10K it for a 200.0 mV full scale and lOOK it for a 2.000 V
full scale. The digital output is inversely proportional to the
value of this resistor.
C
VIN
Count=-VREF
8192
HI-QUALITY GNO - This pin, typically connected to a
High Quality Ground point for single ended inputs can be
used as the inverting input for differential signals. The digital
output will be VIN - VHI_Q' When using this differential
mode, it is important that resistor R3 be less than resistor
R2 for proper operation.
M/Z - Measure/Zero Logic Input. I nternal level shifting
drivers operate the PMOS switches in response "[0 this digital
signal.
U/O - Up/Down Logic Input. The logic signal applied to
this pin operates a SPDT switch to provide Quantized pulses
of charge to the integrator.
COMP - This analog comparator output is an open collector
configuration which goes to V2 when "low."
V2 - Negative Supply Voltage. Recommended level is -12 V
±10%.
GND - Analog Processor Ground. Should be kept separate
from Digital Grounds.
REF out - This buffered voltage output of the SPDT U/D
switch, converted to a current by resistor R 1, supplies the
reference current to the integrator.
I NT. IN - I ntegrator Summing Node.
V REF - A stable positive reference voltage (2 to 10 V)
applied to this pin is the standard to which the input voltage
V I N is measured. Ratio measurements can be made by
applying a variable to this input (1.0 to 10 V).
INT. OUT - The output of the integrating amplifier is made
available for application to the Auto-Zero amplifier by means
of resistor R4'
AZ OUT - The output of the unity gain Auto-Zero amplifier provides a second negative reference current to the
integrator through resistor R3'
AZ FI LTER - The Auto-Zero Capacitor (CAZ) connected to
this pin stores D.C. voltage components to balance amplifier
offset and drift com ponents.
AZ IN - This input is switched into the AZ filter during the
zeroing interval.
VIN - Analog Voltage Input. The A/D System digitizes the
voltage appearing at this input.
V 1 - Positive Supply Voltage. The recommended level is
+12 volts ± 1 0%.
7-18
V2 - Negative Supply Voltage. Recommended level is -12 V
±10%.
CLOCK IN - This input accepts a TTL or MOS level clock
to drive the synchronous digital circuitry. Acceptable duty
cycles on the external clock range from 30% high, 70% low
to 70% high, 30% low for clock frequencies from 2 kHz to
250 kHz. Although any clock frequency between 2 kHz
3nd 250 kHz may be used, clock frequencies that are integer divisions of 2048FL (FIN = 2048FL/n, n = 1,2,3, ... ,
51), (FL = Line Frequency) provide measure and zero periods that are integer multiples of the line frequency period
(T zero = n/F L, T measure = 2n/F U. Line frequency interference is minimized by the selection of one of these 51
frequencies.
This input has an active pull-up to VSS'
M/Z - Measure/Zero Logic Output. This 0 to 5 volt logic
output successively provides Autozero and Measurement
intervals of 2048 and 4096 clock periods respectively. This
output is compatible with CMOS logic and directly interfaces
with the LD 111 A analog processor.
U/O - Up/Down Logic Output. This output has logic levels
of 0 and +5 volts to provide pulse-width modu lation of the
reference current when used with the LD 111 A analog processor. This output is CMOS compatible.
COMP - Analog Comparator Input. This input has an active
pull-up to VSSfor a comparator "high" state. This pin must
be pulled down to V2 for a "low" comparator state.
An End-of-Conversion Signal can be decoded from the three
interconnecting logic lines (M/Z, U/D, Comp) using the following CMOS logic.
MIZ + U/D + Comp = E.O.C.
B1, B2, B3. B4 - BCD Data Bit Output. B4 represents the
most significant bit and Bl the least significant bit of the
BCD output. Bit 4 of digit 4 goes high for an underrange
condition (less than 100 counts). These outputs are compatible with 1 standard TTL load.
MUX Underrange = B4 x D4 (5% of full scale)
01, 02, 03,04 - Digit Strobe Outputs. D4 is the most significant and Dl the least significant digit of the 3 1/2 digit
output. The digit strobes are each selected in turn when the
BCD data bits for that digit appear at the bit outputs (see
Figure 4).
MUX Overrange = Dl + D2 + D3 + D4
(100% of full scale, count;;;' 2000)
SIGN - Sign of Analog Input Polarity. This TTL level output is a static signal which is either 0 or VSS for a negative
or positive input polarity respectively.
GNO - Digital Processor Ground. Should be kept separate
from Analog Grounds. Common connection should be made
at the power supply.
Siliconix
FUNCTIONAL OPERATION
tracking reference voltage necessary for bipolar A/D conversion.
The Connection Diagram of Figure 1 should be referred to
along with the timing diagrams of Figures 2, 3, and 4 in this
discussion of functional operation.
The Auto-Zero sequence is initiated when the M/Z (Measure/
Zero) signal switches the input buffer amp to analog ground.
After a brief count-correcting override period, the AZ switch
is closed connecting the AZ amplifier and Integrator together
in a closed-loop second-order system. During this time the
control logic ignores the comparator output and pulses the
U/D switch at a 50% duty cycle of 4 clock periods "Up"
and 4 "Down" (see Figure 2). Equilibrium of this closedloop system is attained when the average currents through
R1 and R3 are equal and opposite. This is achieved when
VAZ, the Auto-Zero voltage, is equal to -% VREF (R1 = R3).
Establishing V AZ and storing it on CAZ gives the U/D logic
the capability of switching either a + or - reference current
to the integrator during conversion. Thus when U/D is "Up,"
11 + 13=-VREF/2R1 and when U/D is "Down," 11 + 13 =
VREF/2R1. The Auto-Zero interval is of sufficient duration
to insure that V AZ will be well established.
Time Base Counter: An external clock signal using either
TTL or MOS logic levels drives a 2-rfJ clock generator on the
synchronous digital chip. The clock frequency is divided by
the time base counter into sampling intervals of 6144 pulses
of which 4096 constitute the measurement interval/and 2048
the auto-zero interval. Intermediate frequency divisions are
utilized by both the control logic and the 1 of 4 decoder for
the digit enables and bit scan.
AUTO-ZERO INTERVAL
The Auto-Zero interval provides a means to null out the
offset voltages of the amplifiers used in the LD110/LD111A
system. In addition, it automatically establishes a second
PARALLEL
BCD OUTPUT
Vss
SIGN
,...
C
....o....
,...
........C
....
~
DIGIT STROBES
~
~
81 82 83 84
D, 02 03 04
10
REFERENCE BUFFER
4
HIGH
QUALITY
GND ":"
UfO
9
I
I
I
CONTROL
LOGIC
5 COMP 8
I
I
I
I
I
~
I
L - - - - - - - - - - - - ........-~"-_-F-o--Q';.:;0f+-_ _ _ _ _ _ _ _ _ _--'
-
CLOCK IN
GND
ANALOG
GND
LD110
LD111A
~
Connection Diagram
Figure 1
0, 23'~"O", ••• ,0,.,. •• ,0 12,
~OI"""O
M/Z
I\J1JIIIIIIIJIJ
M/Z
------~~O;V~R~D~~::::~AU~T~O~.Z~E;RO;::::::
AZ
AZ _ _ _ _ _ _ _- - '
UID
UID
COMPARATOR
COMPARATOR
OUTPUT
'"c
,0
n
o
:I
<
CD
------1
-Az--II'------MEASURE - - - - - - ~~_______________________
.....
CD
OUTPUT
OUTPUT
INTEGRATOR
...
A
A
fft
A
A
I
'~V
,
A
A
VAZ
\---\A/V.
....
INTEGRATOR--'r-iV~V-\-v~·
OUTPUT
Auto-Zero Timing
Measure I "tarval Timing
Figure 2
Figure 3
Siliconix
7-19
.........c
ca
o...
...ca
...I
...I
FUNCTIONAL OPERATION (Cont'd)
DATA FLOW
MEASUREMENT INTERVAL
Following the count correcting override sequence; the contents of the BCD counters and sign flip-flop are loaded into
the internal latches. Counter states of less than 100 or greater
than 1999 are decoded as underrange or overrange conditions
respectively. The underrange signal is forced on Bit 4 during
D4 time. The over range signal will be used to blank the
display during the zero interval giving a visual overrange cue
by means of a blinking display.
The "Quantized Feedback" conversion system is characterized by a single phase Digitization interval in which a digital
control system feeds back quantized units of charge in
response to the sampled state of an analog comparator.
These quanta of charge balance the charge being supplied
to the integrator by the analog voltage. The magnitude
(VREF/2R1 x 6/f clock ) of the Quantized charge being fed
back and its sign (+ or -) arise from the fact that the control
logic has two U/D duty cycles available during the Measure
interval as shown in Figure 3.
The U/D logic is "up" one clock cycle and "down" 7 cycles
for a high comparator output in the clock cycle preceding a
set of 8 cycles. This will be designated duty cycle" A." With
a low comparator output in clock cycle number 7 the U/D
The BCD data stored in the latches is continuously scanned
every 32 clock periods (8 clock times per digit). This data
format is shown in Figure 4. Sign information is available
as a static signal on a separate pin (high for +, low for -).
The BCD data output is an interlaced scan of digits 1, 3, 2,
and 4 where digit 4 is the most significant digit. All outputs
are active high and TTL compatible.
logic will be "up" for 7 cycles and "down" for 1 cvcle in
the following 8 clock cycles. This is duty cycle "B." The
effect of these two reference current duty cycles on the
integrator output is shown in Figure 3. It can be seen that
the "up" state of the U/D logic drives the integrator output
voltage up. The up/down BCD counter increments by each
clock pulse when the UfD logic is "up" and decrements by
each clock pulse when the U/D logic is "down." Consequently the net count goes up 6 counts for a "B" duty cycle
and down 6 for an "A" duty cycle.
Input polarity is determined by the first appearance of two
consecutive duty cycles of the same type. The control logic
would determine the analog input to be negative if two" A"
duty cycles occur in succession and positive if two "B" duty
cycles occur in succession.
Since the counting process is done by increments (or decrements) of 6 during the measure interval, a short override
interval is required at the end of the Measurement to "fine
tune" the count to the nearest LSB. This occurs within the
first 32 clock periods of the AZ interval.
16
24
32
APPLICATIONS INFORMATION
(Refer to Figure 5)
1. Power Supplies
a) The recommended supply voltages are:
=12V±10%
=-12 V±10%
=5V±10%
= 2.00 V to 10 V
Operation is possible with V1 and V2 supplies from ±9 V to
±15 V. These minimum voltages (±9 V) require that the
LD 11 O/LD 111 A system be operated on the 200.0 mV scale
to maintain input buffer linearity. It should be realized that
operation below ± 10.8 volts is not guaranteed. V 2 voltages
greater than -13.2 V allows the LD110 to dissipate a considerable amount of power (400 mW, warm to the touch).
A 150 Q resistor in series with pin 11 of the LD 11 0 will
limit the current resulting in cooler operation and longer
life with large values of V2.
40
48
02 _ _ _ _ _ _ _- - '
03 _ _ _ _..J
04lL_ _ _ _ _ _ _ _ _ _--J
Data Output Format (Output = 14921
Figure 4
7-20
Siliconix
56
64
APPLICATIONS INFORMATION (Cont'd)
2. Input Protection. Under normal operating conditions the
inputs of the LD 111 A should not be exposed to a voltage
exceeding either V 1 or V2 (see absolute maximum ratings).
In many applications however, such as a DMM/DVM, the
VIN or VREF input may have a high voltage source connected which is capable of supplying destructive currents
into the LDlllA. To prevent such an occurrence, a current
limiting resistor should be placed in series with the appropriate input pin. The 1 mA maximum current rating should
be observed. A 1 M n resistor in series with pin 15 of the
LDlllA would offer input protection up to a 1000 V
overvoltage.
4. Resistor Selection. Resistor R2 is the scaling resistor and
is selected to provide 10 nA per LSB into the integrator
summing junction. Thus,
3. Operation Over the Full Sampling Range. Any sampling
The reference resistor R 1 is chosen to satisfy the relationship
R _
VIN(Full Scale)
2 - (2000 Counts) (10 nA/Count)
10K n (200.0 mV Scale)
1 K n (20.00 mV Scale)
rate from 1/3 to 40 samples/second can be accommodated by
simply changing the values for CINT and CAZ (R3 and R4
will remain as shown in Figure 5).
Rl
(Trimmed)
To find the proper value for CINT and CAZ, (shown as Cl
and C2 respectively on Figure 5) find the needed clock frequency for a specific sampling rate from the following
relationship.
f clock
=
n (2.000 V Scale)
= lOOK
Mn
VREF
81.92 V
5. 20.00 mV Scale (10 pV Resolution). The improved noise
performance of the LD 111 A allows it to be used in a
20.00 mV DPM when R2 is selected to be 1 K n. This high
resolution range, while useful, does not have the same degree
of zero and LSD stability as the 200.0 mV and 2.000 V
ranges. Extreme care in layout is required to minimize noise
and offsets at VIN and Hi-Q GND.
Sampling Rate x 6144
Once the clock frequency has been determined, the values
for CI NT and C AZ can be found.
6. Ratio Operation. The LD 11 O/LD 111 A is a ratio measuring system - the output being
200 pF/sec
CINT""---fclock
,
""
lOOn
"12
'3
I~
+1
-10
MAN4630
~3
I-
I--
III-
'0
'6J
i-'
~
IiFI-I
I-I
r,-I. I--I. If!=: -I.
I--
MAN4610
~4
fa] r<~6':6
MAN4610
'"1
rKi
Ijf~
3.a
~a
~b
~c
~d
~.
~f
~g
~
9374
",.
A3r---2
A2r---
5' a
,
". a_,
A'IAD 7
4.3K
61
l1li
Q7
MPS All
r
-=-
MPSA13
5
,
2
3
MPSA13
'-...I
6
-::r- ,
H=~
I 4
555
a
7
6
5
i
I
"7
3K 0
7
a
10Kn
1
.:::!:
C4
O.OO22/.1FT
L,
r--r--
'6
s-== ~
LD111A
-::C5
R
[7: K'O
-12V
0.01/.1F
160Kn
.
"3
::::l
33Kn
~
il.
'o-
12Kn
l
~~
n
o
~
<
CD
",
I-
2
'5
3
'4
45'3-
~7
Ra
C3
~ 0.022,F
"2
"'0
•
........
CI
V,N
::!::
'6 I--
'5
'4 I '3
: 5 '2
LD110
Q2
+5V
J>
"5
lMa
r---
.YJ
C2
c,
[0."Flo.ooa2,F
CD
U1
10Kn
{-
NC
Q,
NATIONAL
2N4274
":'"
~
+12V
3M. Digit DVM (±200.0 mVI Common Anode Display
Figure 5
Siliconix
7-21
.........c
....
o...
...
Q
....Q
APPLICATIONS INFORMATION (Cont'd)
The high impedance input and reference buffer amplifiers
offer a system with ratio operation and minimal source
loading. The ratio curve shown with the typical characteristics illustrates the ratio performance.
7. Zero Adjustment. The LD 11 O/LD 111 A converter set is
an Auto-zeroing system. Many applications exist, however,
in which a means of nulling out external offsets is needed.
The circuit of Figure 6 provides this offset nulling feature.
10. "Hold". The last conversion of the LD 11 O/LD 111A may
be held indefinitely by means of the added circuitry shown
in Figure 7. Forcing the comparator input of the LD110 to
the high state eliminates any future data transfers. The
resistor protects the LD111A comparator output. Opening
the connection to VSS allows normal comparator action and
data transfer. The first conversion after a "hold" will always
be in error since the AZ voltage has not been maintained
Vss
10K n
P~~Z3
LD111A
r
68K n V2N4400
-=-
lOOK
47 pF
n
.-jf-+
9. Data Valid (End-of Conversion). The BCD data from the
LDll 0 is changed only once per conversion, at the end of
the override interval. The 3Y:z digits of data are then repeatedly multiplexed out during the rest of the zero and for the
full Measure Interval. Since the data cannot change during
the Measure Interval and since the Measure Interval occurs
once each sampling interval, this high state of the MIZ line
can be used as a Data Valid or End-of-Conversion signal.
TO
CAZ
(PIN 13)
.J,,~:
Offset i\iuiiing Circuit
__ /1&... ... 1..1"
UUIIII~
!lVIU
•
Figure 6
Vss
8. Replacing the LDlll with the LDlllA. The LD111A
offers a significant improvement in linearity, noise and
temperature stability over the LD 111. It also eliminates,
the need for the integrator clamp zener required on the
LD111. The LD 111A is a plug-in replacement for the LD111.
7-22
Siliconix
t
":=t:LO+--+CONVERT
COMP
LD111A
(PIN 5)
10K 51
"Hold" Circuit
Figure 7
COMP
LD110
(PIN 8)
H
Siliconix
FunctionlApplication of the
LD110/LDlll 3V2 Digit AID
Converter Set
INTRODUCTION
This Application Note describes the functional operation of
the LDllO/LDIll A/D converter chip set, provides a basis
for criteria in external component selection, and offers
some practical circuit applications.
The Siliconix LDll0/LDIll 3J6-digit A/D converter integrated circuit set offers high performance and versatility
with a minimum of required external circuitry. The set consists of a monolithic PMOS synchronous digital processor
(LDUO) and a monolithic bipolar-PMOS analog processor
(LDII1). The salient features of the A/D converter set include an accuracy of 0.05% (of reading) ±I count; a 4 pA
typical input bias current; an input impedance of greater
than 1,000 M.I1; autozeroing; and a single reference voltage requirement. External user-selected components will
allow for two different voltage ranges (2.000 V and
200.0 mY) and a wide range of sampling rates (1/3 to 12
samples per second) to accomodate a variety of applications.
Functional Operation
The conversion technique balances the charge supplied by a
current proportional to the input voltage, over a measure
interval, with an accumulation of quantized charges equal
to a BCD count. The units of quantized charge are provided
through pulsewidth modulation of a reference current. In
Figure 1, the A/D converter set is shown with the external
RC components required to analyze the functional operation.
PARALLEl
v,
V,
GNO
SIGN
BCD OUTPUT
DIGIT STROBES
B, 62
0, 02 03 04
--------- --------B394
16
l1li
VON
GNO
~
I
I
CDMP
........
Ie
CONTROL
LOGIC
~
n
o
I
L ___ _
:=
-l
I
I
L
t(
MIZ
CD
...
to, to,
"'\I
3--10
CD
13
V,
U1
Al FILTER
GNO
CLOCK IN
LD110
LD111
• P·channel Enhancement Mode MOS·FET Switches
UtD Shown in Down State (logic "0") MtZ in Zero State (logic "0")
Functional Diagram
Figure 1
Siliconix
7-23
-.........
CLOCK
INPUT
CYCLE
...
......
......
Q
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
J
4
5
6
7
0
1
2
3
4
5
6
7
0
M!Z~
.......
0
UfO
Ul'---_ _--'
DUTY
Q
U
I
CYCLE
Lf
I
I
COMPARATOR
I
IIIiI'
.....
INTEGRATOR
OUTPUT
Z
CI:
Measure Interval Timing
F:gu~e
The clock frequency is divided by the time-base counter of
the LDII 0 digital processor into sampling intervals of 6144
cycles; 4096 cycles constitute the measurement interval and
2048 cycles make up the auto-zero interval.
The auto-zero interval allows the effects of offset, temperatures and drift to be impressed on the auto-zero storage
voltage, Vstrg, which is maintained as a reference by Cstrg.
Therefore, during the succeeding measure interval these effects will be balanced out. In addition, Vstrg acquires a
voltage component available at the AZ amplifier output,
which provides a current equal to -12 VREF/RI through
resistor R3. The net current provided to the integrator summing node by the sum ofVstrg/R3 and the current through
RI is either + or -. VREF/2RI, depending on the position
of the Up/Down switch. The input of the buffer amplifier
is grounded during this jnterval.
The input voltage VIN is applied to the input buffer amplifier during the measure interval. This amplifier, in conjunction with R2, supplies an additional current VIN/R2 to the
integrator summing node. The comparator transmits the
state of the integrator output (with respect to Vstrg) to the
control logic. The control logic attempts to establish equilibrium in the circuit by operating the Up/Down switch at
one of the two available duty cycles (7 clock cycles UP, one
cycle DOWN; I clock cycle UP, 7 cycles DOWN) while the
counter keeps track of the net UP count. The integrator
output, Measure/Zero (M/Z), Up/Down (U/D) and comparator levels during the measure interval are shown in
Figure 2.
The following equations describe the measurement technique:
/':,Q = 0
WHERE:
/':,Q= VIN Mmeasure ~
7·24
VREF (NU)
~I~N
.~
~I~N
2
WHERE:
(NU) = (# counts UP) and
(ND) = (# counts DOWN)
BUT:
# counts UP + # counts DOWN = 4096 (clock cycles in
the measure interval)
(2)
# counts UP - # counts DOWN = net count
(3)
THEN:
0= VIN /':,tmeasure R2
VREF
(net count)
(4)
2RI fIN
BUT:
/':,tmeasure = 4096/fIN
(5)
Substituting and multiplying by fIN yields
Net count = VIN . ~ . 8192
(6)
R2
VREF
Equation (6) is fundamental to the application of the
LD 11 O/LD III A/D converter set.
Component Selection
Application of the LDIIO/LDIII A/D converter set should
begin with the selection of power supplies and the clock
frequency. The recommended supply voltages are VI = 12 V
± 10%, V2 = -12 V ± 10% and VSS = 5 V ± 10%. Clock frequencies between 2 kHz and 75 kHz are recommended.
The duty cycle of the clock is not of particular importance;
the logic "0" time should however, be greater than 5 f..Isec.
The sampling rate and clock frequency are related as follows:
(ND) (1)
Sampling Rate = fIN/6144
Siliconix
(7)
The clock frequency may be chosen to minimize line frequency interference. If the auto-zero and measurement
periods are integral multiples of the line frequency (fL) period, line frequency rejection will be maximized:
LHZERO = 2048/fIN (iltmeasure
=2 iltzero)
2048 = ~ where n = 1, 2,3, ... 51
fIN
fL
(8)
(9)
THEN:
fIN
=2048 fL
(10)
n
Once the clock frequency is chosen, the proper values for
the external RC components may be determined.
Equation (6) defines the relationship between the ratio
RI/R2 and the reference voltage VREF when a full-scale
voltage range VIN (F .S.) is chosen. This relationship is:
R2 = VIN (F.S.)
2000
8192
(11)
VREF
It is usually more convenient to select VREF before assigning resistance values because of the implications of temperature coefficients, availability, or other considerations.
VREF should be greater than 5 V, but less than VI' As
VREF is increased the UID switch ON resistance decreases,
as is shown in Figure 3. Rl also increases with VREF, thus
decreasing the proportion of the total resistance provided
by rDS(ON)- Consequently, a large VREF minimizes the
effects of the UID switch ON resistance. It is very important
that VREF have a low temperature coefficient to minimize
drift and the resulting count error.
v,I.,lv l-
1000
V2~·12V,_
900
'"
70"C
~ 800
2-
"'i-.
~
25G C
~
700
o'c
500
o
1
2
3
4
5
6
7
8
9 10
ilCount
=2000
VIN
VIN (ES.)
ilRI
Rl
(13)
'1
The net error that can be attributed to temperature effects
is the sum of the errors due to the changes in VREF and the
RDS(ON) of the UID switch. Temperature compensation
for the AID converter circuit, then, can be approached in
two different ways. The first method would be to provide a
large VREF (less than VI, however) with a very low temperature coefficient. This would require a large value of resistance for RI, reduce RDS(ON) and make changes in
RDS(ON) negligible. The alternative method is to note that
a reference voltage with a positive temperature coefficient
produces an error in the count which tends to oppose the
error caused by the positive temperature coefficient of
RDS(ON)- Thus the two effects can be used to counteract
one another (an example is provided in Appendices A and
B).
VREF - REFERENCE VOL.TAGE (VI
(14)
Equation (12) shows the change in count which will OCCUI
for a fractional change in VREF (see Appendix A, Page 10)
VIN
VIN(F.S.)
z
...~•
-....ar...
o
.......
r.........
C
-
l1li
~
.......
a
n
o
~
ROSION) IUfO Switch) vs. VREF and Temperature
Figure 3
ilcount = -2000
~
Since the count is proportional to the ratio RI/R2, equal
temperature coefficients for these resistors should allow
this ratio (and the count) to be maintained even with a
change in the ambient temperature. It is desireable, however, to use resistors with low temperature coeffients for RI
and R2 to reduce any errors resulting from the differences
in these coefficients.
The specified accuracy of the AID converter will be maintained if the integrator capacitor CINT is chosen so that the
voltage swing of the integrator is held to within 0.75 volt of
Vstrg. An analysis of this constraint, shown in Appendix C,
(Page 11) results in the following relationship for CINT
'I-.
60 a
R2 should be chosen to supply a full scale current of 20 Jl.A
into the integrator summing node (100 Kn for 2.000 V
and 10 Kn for 200.0 mY). RI can then be determined by
Equation (11). R 1, R2 and VREF and the basic temperaturesensitive components of the system. The auto-zero interval
makes the system essentially independent of changes in
CINT, R3, R4, R5, Cstrg and the offset voltages of the
amplifiers. In Figure 3, note that the UID switch ON resistance has a temperature coefficient of about 0.2/"C. This
temperature-dependent resistance must be considered as a
part of R 1, the reference resistor. The error in count resulting from a change in this total resistance R 1 is examined in
Appendix B (Page 10) and found to be:
(12)
Consequently, the count will decrease by 1 for each +0.05%
change in VREF, for VIN =VIN (F.S.)
This capacitor and the zener diode to be placed in parallel
with it should have a combined leakage of less than 10 nA
(see Appendix D, Page 11) to minimize this possible source
of error.
The storage voltage, Vstrg, should be maintained between
-2 V and -5 V for normal operation. The ON resistance of
Siliconix
7·25
.
<
CD
.,
CD
til
-.........
CI
~
.......
......
-...•
o
CI
~
~
Z
C
the auto-zero (AZ) switch is typically 11 KQ at Vstrg =
-4 V (V 2 = -12 V), and will increase significantly with an
increasingly negative storage voltage. Resistor R3 can be
selected to provide the desired Vstrg by using Equation (17).
The integrator output, which swings around V strg during
the measure and zero intervals, must always be more positive than -9 V to maintain the functionality of the analog
processor. This can be accomplished by placing back-toback Zener diodes in parallel with CINT (the second diode
is to prevent the Zener from being forward biased). It then
becomes important that the integrator output voltage not
exceed the breakdown voltage of the Zener diodes, for the
maximum input voltage for which an accurate readout is
desired. The relevant equations are:
The illustrated connection of the analog circuit grounds
(pins 2 and 7 of the LDIII) and the digital circuit ground
(Pin 12 of the LDIIO) is for schematic convenience only.
The digital component grounds should be connected together and brought to a reference point such as the input
voltage ground, and not directly to the pins of the LDlli.
Vo(min) > -Vzener
Input D of decoder = B4 . D4
(IS)
WHERE:
7
VO(rPJn) = Vstrg - - - - fINCINT
(see Appendix C)
_ -VREF R3
Vstrg - - - - - 2
Rl
~
r
VIN(max~(I6)
R2
VHi-Q (If Hi-Q Gnd
J"
is not at zero potential)
If Vo(min) exceeds the breakdown voltage value of the
selected Zener diodes, either Vstrg or CINT must be adjusted to maintain this inequality (see Equation (IS».
A number of engineering tradeoff considerations must be
made in selecting RC components for the AIZ filter (R4,
R5 and Cstrg)' Some of these are covered in Appendix E.
Various component values for different clock frequency
ranges are presented in Table I, along with the recommended
values for the integrator capacitor, CINT.
Cstrg
(J-/F)
(J-/F)
2 to
10 to
20 to
40 tu
10
20
40
75
0.1
0.039
0.022
0.01
1.0
(~&)
(~P2)
68
15
47
0.056
0.056
240
120
0.056
82
33
18
APPLICA TlONS
Digital Voltmeters
The circuits shown in Figure 4 present the LD llOlLD III
AID converter set in typical ±2.000 V digital voltmeter
applications. The clock frequency of 24.5 kHz provides a
sampling rate of 5 samples per second. Trimmer resistor
R6 calibrates the DVM. R 1 and R2 are metal film resistors.
7·26
when the count exceeds 1999. If the grounding system is
poor, erroneous readings will result for counts of 2000 and
above.
The data output format is an interlaced scan of Digits, 1,3,
2 and 4 with Digit 4 as the most significant digit. This permits the use of Sperry displays with clock frequencies of
25 kHz or less. All outputs are active high and TTL-compatible.
The overrange and underrange signals may be obtained by
external logic, Le.,
MUX Underrange = B4 . D4 (5% offull scale)
MUX Overrange
full scale)
=DI
+ D2 + D3 + D4 (100% of
(19)
(20)
Autoranging DVM
TABLE I
Auto/Zero Filter Values
CINT
The display will blink at a rate equal to the sampli.tlg rate
(17)
R2
fIN
(18)
where Bn is the nth BCD data bit and Dn is the nth digit.
VREF +
L 2RI
(kHz)
The use of a seven-segment LED for Digit 4 will allow the
DVM to be employed up to the maximum count of 3100.
The output of the BCD-to-seven-segment decoder will be
erroneous during Digit 4 time, however, because under·
range information is encoded on bit 4 during Digit 4 time.
The bit 4 input of the decoder in Figure 4a (bit 4 is the
most significant bit) should be clamped to ground during
Digit 4 time to provide the correct Digit 4 readout, as in:
The circuit in Figure 5 shows how the decoded underrange
and overrange signals can be used to make an automaticranging DVM. The circuit will cycle through five ranges
(200 mV to 2,000 V), starting with the most sensitive
range and proceeding through the less sensitive ranges until
the proper operating range is attained.
When the cycle proceeds from the most sensitive to the
least sensitive range, the proper range will be achieved for
voltages which will provide a count between 1000 and 2000.
If the cycle began at the least sensitive range, a voltage such
as 15.0 V would be read on the 200 V range, since the
count of 150 would not initiate an underrange signal to advance the circuit to a more sensitive range.
The two-input NOR gate decodes the underrange signal to
preset the shift register with a "I" logic at each of the
parallel bit outputs. A Siliconix DG201 quad SPST CMOS
Siliconix
~
Z
...~
-...a
...o
..........a
I
r-
1,~W
'"
........
r-
lM!l
-
Q,
002"F
RS
331-t.
0,
..
DVM Autoranging Circuit
Figure 5
Siliconix
7·27
.....
..
-.....
~ r-------------------------------------------------------------------------------------~
..
..
analog transmission gate is employed in the circuit so that
each of the four switches of the DG20I will be OFF when
a logic "1" signal appears at the appropriate input.
.......
Diodes DI and D2 clamp the input of the LDIII processesor
at ±s V to prevent damage which could result from large input voltages. The presence of the overrange signal(Equation
(20», decoded by the combination of the five inverters and
NAND gate 1, transfers the logic "0" signal which appears
at NAND gate 2 into the shift register. I"ogic "0" appears
at the A output of the shift register and turns on the DG20I
switch which is associated with R2, producing a voltage
division of 10: 1. The serial input of the shift register remains at logic" 1" when any of the outputs are at logic "0",
this insures that only one of the four DG20I switches is ON
at a given time. The logic "0" signal is shifted through the
register until the proper range is acquired. When the input
voltage is removed the decoded underrange signal returns
the shift register to the initial state.
a
o
a
I
;!:
Z
CI:
The ON resistance of the four switches in the DG20I quad
transmission gate is typically 160 n with ± 12 V supplies.
This resistance has been considered in determining the values
of range resistors R2, R3, R4 and RS. Some trimming may,
however, be necessary .
The input impedance is greater than 10 Mn on all ranges .
Since the circuit changes range once every sampling period, the time required to attain a reacling on the highest
range is 30no/fIN.
Isolated Analog Processor
The isolation circuit shown in Figure 6 provides a floating
analog processor for measurement of off-ground signals
such as those found in medical, nuclear, and process control
instrumentation.
The current-sinking capability of the shift register can be
used to turn on the appropriate decimal point cathode of
the LED display, with the only additional required component being alSO n current-limiting resistor. Inverters 1
through 4 can be used as inverters 1-4 of the DVM circuit
shown in Figure 4. The filter R6 C 1 insures that there will
be only one range change for each overrange signal, while
the filter comprised of R7 C2 eliminates an erroneous underrange signal which can occur if bit 4 of Digit 2 time
overlaps into Digit 4 time.
Tne three anaiog-to-digitai interface signals (MiZ, UID and
comparator) are isolated via high-speed optical couplers
with a 2,500 V insulation. Transistors QI, Q2 and Q3 pro..:
vide TTL level drive capability to interface the optical
couplers with the LDllO/LDlli system signals. The isolators in the M/Z and UID channels are used in the non-inverting mode while the isolator in the comparator interface
is used in the inverting mode. Transistor Q4 shift the TTL
level signal to the MOS level required at the LDIIO comparator input.
The R6 CI and R 7 C2 filters are optimized for the 24.5 kHz
clock frequency of the DVM circuit in Figure 4. Clock frequencies of less than 10kHz or greater than 40 kHz may
require the adjustment ofCI and C2.
Although the isolators tend to shorten the pulse length of
the LD 11 O/LD 111 system signals, the unique conversion
technique of the system automatically compensates for
this, and no additional adjustments are necessary.
+5VISOLATED
LOUD
., "
601<[1
COMPARATOR
25K n
'--+--------o.5Y
'9
U/O
o------+c
MIZ
Optical Isolation Circuit
Figure 6
7·28
Siliconix
3>
Z
~
Ratio Measurements
Equation (6) shows that the LDllOILD111 AID converter
measures input voltage as a ratio: the count is proportional
to the ratio of the input voltage and the reference voltage.
This system conversion technique is ideally suited to the
measurement of ratio. Ratio measurements using a reference
voltage which is also the excitation voltage of the ratio device allows measurements to be independent of variations
in the excitation voltage. Typical ratio-measuring circuits
are shown.
VREF
+12V
I
(RANGE RESISTOR)
RANGE
RANGE RESISTOR
r---'I/II"<--~ 2~~n
Rll 51K
n
8f9.2n
8.192 Kn
81.92 Kn
830Kn
8.51Mn
163Mn
20 Kn
...---'VIfV---, 2~ ~~
VRfF
20Mn
VREF
""
X (UNKNOWN)
RSEl
J Mn
lOVIN
........
-
+12V
S1Kn
X,VREF
- - - 0 J~D~\~I
...
-.a.....
...o
...a
.........
(LD1111
>.;;--<>---oVREF·
TO VREf INPUT
(L01l1)
HI-QUALITY
L - - - - - f - - - - o TDGROUND
lL0111)
lal POTENTIOMETER
fbi BRIDGE MEASUREMENTS
Ratio Measurements
Figure 7
Resistance To Voltage Converter
Figure 8
TIle output of the potentiometer in Figure 7A (which can
represent position, level, etc.) can be substituted in Equation (6) to demonstrate this capability:
Count = XVREF . -RI
R2
Substituting into Equation (6) yields
Count = 8192
RX
(25)
(21)
Bridge transducer measurements, as shown in Figure 7B,
can also be normalized to an external reference. The Hi-Q
ground input of the LDIII functions as the inverting input
of a difference amplifier to provide a count proportional to
the difference of the two inp~t voltages VA and VB.
Current-To-Voltage Converter
A current-to-voltage converter featuring eight decades of
current range is shown in Figure 9. The circuit is intended
to be used with the 200.0 mV range of the DVM.
+12V
Count =
l1li
"1
(22)
Ratio measurement techniques can also be extended to ~e
sistance measurement. The resistance-measuring circuit
shown in Figure 8 will measure accurately to 20 MU when
associated with a buffer amplifier (AI) having a low input
bias current (lIN < 30 nA). The circuit illustrated uses two
of the three amplifiers contained in the Siliconix Ll44
micropower triple op amp.
3>
........
VIN=VREF
(R~ x)
(23)
-=
(24)
Siliconix
...
""I
-f2V
RANGE
200nA
2pA
,OpA
200pA
'mA
20 rnA
200mA
'A
[ 1- _ X ]
R+X
n
o
:::a
<
CD
(200 mV RANGEl
CURRENT
This circuit exhibits a very high reference voltage rejection
ratio, as shown by the following pertinent equations. (1)
a
TO VIN (L0111)
"1
"2
500K!l
500Kn
50Kn
5Kn
SOKn
5Kn
1Kn
5QKn
50K!l
50Kn
SOKfl
"3
CD
UI
0
50K
0
0
".
5.0 K
5.0 K
5.0 K
n
1.0 n
10.0
.1 n
.01n
Current To Voltage Converter
Figure 9
7-29
-.........
Q
."
.......
o
......
-...•
Q
The arrangement actually comprises two different circuits,
as examination of the table of resistance values in Figure 9
will show. The more sensitive ranges (up to 200 J.l.A) use the
amplifier in a differential mode to give an output equal to
-2 IINRI. This configuration effectively cancels the contribution of the input bias currents to the output voltage.
(Since this error would be insignificant on the 200J.l.A range.
R2 is eliminated.)
FET input buffer amplifier, coupled to a classical absolute
value circuit which essentially eliminates the effect of the
forward voltage drop across diodes 01 and 02.
The less sensitive ranges (2 rnA to 2 A) use the amplifier in
an inverting configuration to provide an output equal to
-lIN R4 RI/R3.(2) Input protection is provided by diodes
01 and 02.
Digital Frequency Meter
A ftIter removes the OC component of the rectified AC,
which is then scaled to RMS. The output is linear from
40 Hz to 10 kHz or higher .
."
=:
z
c
A digital frequency meter can be fashioned by using the circuit shown in Figure II with the basic 2-volt DVM circuit
shown in Figure 4.
AC-To-DC Converter
The circuit converts frequency to voltage by taking the
average OC value of the pulses from the 74121 monostable
multivibrator. The one-shot is triggered by the positivegoing AC signal at the input of the 529 comparator. The
amplifier acts as a OC ftIter, and also provides zeroing. This
circuit "ill maintain an accuracy of 2% over 5 uecaues of
range. The input signal to the comparator should be greater
than 0.1 volt peak-to-peak, and less than 12 volts peak-topeak for proper operation.
When an AC-to-OC converter is designed using the LOIIO/
LOllI converter set, the input impedance and input bias
currents should approximate those of the LOlli input buffer amplifier. This is particularly true if the auto ranging circuit of Figure 5 is used so that the same range resistors can
be employed for both AC and DC measurements. The ACto-DC converter shown in Figure 10 fulftlls these requirements. The circuit includes a PMOS enhancement-mode
R.
R7
2. K
5K
ZERO~--------Wl,------.,
-=-
ADJUST
R5
-12V
24 K 1%
GAIN ADJUST
R.
A,
A6
3.9 K
2. K
A.
24 K 1%
12 K 1%
°2
R3
24 K 1%
lN914
TOVIN
(L01"1
A2
1.5 K
AC1N
V, +12V
+12V
AC-to DC Converter
Figure 10
r-""1'""-t-o+12V
(!6V MAXI
INPUT
lOVIN LOll'
R,
R225K
lOO!1
-12V
2 kHz
20 kHz
200kHz
100pF
C,
I
·CALIBRATE AT 1000 COUNTS
~'2V
Frequency To Voltage Converter
Figura 11
7·30
RANGE
Silicanix
CT
.082J.l.F
.0082J.LF
820pF
2MHz
82pF
20MHz
8.2pF
Digital Thermometer
Multiplexed BCD To Parallel BCD Converter
A digital thermometer can be constructed by using the
change in forward voltage drop across a PN junction as the
temperature-sensitive element in the circuit. This change is
typically -2.3 mV/"C. The circuit shown in Figure 12 has
the base-emitter junction of a bipolar transistor biased with
a 470 /lA current source.
Although the multiplexed BCD output of the LDI101
LD III AID converter set is useful for digital displays, there
are applications (such as printer inputs) in which the BCD
data for all four digits should be available in a parallel format. The multiplexed BCD-to-paralle1-BCD converter shown
in Figure 13 will provide the proper interface for such applications.
CR033
The converter consists of 4 quad bistable latches activated
in the proper sequence by the digit strobe output of the
LDIIO. The complemented outputs (Q) of the quad latch
set will reflect the state of the bit outputs when the digit
strobe goes high, and will maintain this state when the digit
strobe goes low. The latches will be updatep with the next
digit strobe. This parallel BCD output will not then be affected by the blinking-off of the digit strobes when the
count exceeds 1999 (overrange), and can be used to drive
a non-blinking display up to a full scale ot 3000 counts.
The parallel BCD output can be put in a "hold" state by
-Iamping all digit strobes to ground to prevent the uplating of the latches.
R"
43KH
330~A
+--_____+-_____V_BEOTO(~~~~ND
•z
...~•
-a...
..........
o
a
.........
r-
r-
-
V_ZE--O-JYII'..--HH
1. R3=Sl KU
1-+""4'----------0 : : : : }
2 R2 = 23 K!! (CENTIGRADE SCALE)
l' KH (FARENHEITSCALEI
3
HI~aUALITV
OIGIT 3
1-+'-'-----0 BIT 2
GND NO L.ONGER CONNECTED TO
GROUND
1-r"-------OBITl
L::C==----'7475 aUAD LATCH
02D----[>---~_r~-r___-~
Temperature To Voltage Converter
Figure 12
1-+"'-'4----0
The junction voltage VBE is applied to the input buffer
amplifier of the analog processor which functions as a differential amplifier. The buffer resistor R2 is scaled to give a
count proportional to temperature as shown by the following equations:
:::: }
OIGiT 2
a
1-+"---------0 BIT 2
n
o
::::I
<
CD
1-;-"---081T 1
1/61417
L::C==-----' 7475 QUAD LATCH
1/67404
Count = RI 8192
R2 VREF
[VZERO - VBE (T)]
1-+'''--------0 BIT 2
DIGIT 1
(LSD)
.Ol"'F~
[ VZERO - VBE (T)]
BIT 1
L::C==-----' 7475 QUAD LATCH
(27)
Gain A must be approximately 5 for the Centigrade scale
and 9 for the Farenheit scale.
Siliconix
...
..
CD
fit
h------O
AND SO:
Count = 1000 A
H.:.:'4'----_--o :::: }
(26)
-•
.......
Multiplexed BCD To Parallel BCD Converter
Figure 13
7·31
-.........
Q
~
.......
......
-...•
o
Q
~
~
Z
C
CONCLUSIONS
THEREFORE:
'The LDI10/LD111 AID converter integrated circuit set
lends itself to a wide range of applications in which analog
information is desired in digital format. High accuracy and
long term stability combined with a minimum of external
circuitry and calibration requirements make this converter
set a superior choice for any application. The circuit examples presented are intended to be of general interest, and
do not touch upon the wide variety of more' specialized applications.
A Count = _ Count AVREF
VREF
REFERENCES:
(1)
R. Milner, "Integrate with a DMM?", Electronic DeOctober 25, 1973, pp. 93-96.
~
(2)
M.K. Vander Kooi, "Simple Ie Meter Amplifier Circuit Measure 100 Nanoamps Full-Scale", ED/Elili.,
April 15, 1972, pp. 40-41.
(3)
J. D~Azzo a..tld C. Houpis, Feedback Control System
Analysis and Synthesis, McGraw-Hill Co. New York,
1960, pp. 81-83.
(33)
This can be related to VIN by noting that the full-scale
count is 2000, thus:
A Count = -2000
VIN (F.S.)
AVREF
VREF
(34)
The reference supply shown in Figure 4 has a typical temperature coefficient of ±20 ppmtC. Therefore the reference
voltage would change by 0.1 %for an increase in temperature
of 50°C (20°C to 70°C). The maximum error will occur
when VIN equals the full scale voltage VIN (F.S.) as shown
below.
ACount = -2000 VIN (F.S.)
VIN (F.S.)
(.001)
ACount =-2
(35)
(36)
If no other effects were present, the DVM in Figure 4 will
show a decrease of 2 in the count for a 50°C increase in
temperature, if the reference Zener diode has a positive
20 ppmtC temperature coefficient.
APPENDIX A.' ERROR ANALYSIS FOR VREF
Equation (6) will be used to derive the count error to be
expected for changes in the reference voltage VREF due to
temperature changes or load regulation.
R1
Count' = VIN R2
8192
-VREF'
(6)
(28)
The analysis of the readou t error caused by a change in the
RDS(on) of the U/D switch will proceed along similar logic
as that of Appendix A. Again we look at Equation (6).
(29)
Count' = VIN RI'
R2
WHERE:
Count' = Count (Ideal) + ACount (Error)
AND
VREF' = VREF + A VREF
(V
8192
)
REF + A VREF
(30)
(6)
Count' = Count (Ideal) + ACount (Error)
(28)
AND
Count· VREF + Count· AVREF + A Count . VREF
+ ACount . A VREF = VIN Rl
8192
Rl' = RI (Ideal) + ARI
Substituting (28) and (37) into (6)yields,
The quantity ACount . AVREF is very small in relation to
the other factors and can beReliminated. The product
Count· VREF is equal to VIN R~ 8192 and so these factors can be eliminated from both sides of equation (31)
leaving
Count . AVREF + A Count . VREF = 0
(37)
(31)
R2
7·32
8192
VREF
WHERE
Substituting (28) and (29) into (6) yields
R1
Count + ACount = VIN R2
OR:
APPENDIX B.' TEMPERATURE EFFECT OF
RDS(on) (U!D SWITCH)
(32)
RI 8192
ARI 8192
Count + ACount = =VIN - - + VIN - - (38)
R2 VREF
R2 VREF
Eliminating Equation (6) from (38) gives the change in
count (A Count).
ARI
A Count = VIN -R2
Siliconix
8192
VREF
(39)
BUT:
7
VREF = VIN Rl 8192
R2 Count
(40)
[ 2.048 VIN (F.S.) + VIN (F.s.)l (49)
R2
R2
J
Count
(41)
or by relating the count to the input voltage VIN we see
that:
ACount = 2000 __
V~IN-,-
VIN (F.S.)
(42)
IA Vol = 21.336 VIN (F.S.)
R2 CINT fIN
(50)
Setting this absolute deviation equal to 0.75 volts gives
C
- 28.45 VIN (F.S.)
INTR f
2 IN
(51)
fIN = 24.5 kHz
From equation (51) then:
(52)
Net Count Error = ACount (YREF) + ACount (RI)
(44)
APPENDIX D: ERROR DUE TO CINTLEAKAGE
(45)
In order to determine how much leakage from integrator capacitor CINT is tolerable we must first fmd the relationship between read-out error and leakage current IL.
From Equation (1) it can be seen that the charge Q proportional to 1 count is:
and we choose the closest standard value which is 0.022 tlF .
-VREF
Q per count = - - -
In order to maintain good accuracy, the integrator output
Vo should not be allowed to deviate from Vstrg by more
than 0.75 volts. The maximum deviation from V~t~g will
occur when the maximum input current VIN (F .. J is of
R2
the same sense as the reference current. These considerations are shown in the following mathematical expressions:
r
)0
VIN(F,S,)+VREF
R2
2Rl
Therefore, to maintain an error ofless than 1 count, the net
charge leaked from CINT during the measure interval must
be less than the charge associated with 1 count.
IL Atmeasure <
~V-"RE~F_
(54)
2 Rl fIN
<
VREF
2 Rl fIN
........
(55)
o
THUS
L
SO
(47)
VREF
8192 Rl
(56)
Rl = 2000 VREF R2
8192 VIN (F.S.)
Substituting (48) into (47) yields
Ul
(48)
THEN:
IL < 10 nA to have less than 1 count error
Siliconix
...<
CD
VREF = 6.8 volts
See Eq. (6)
::I
CD
Given the values "for the application circuit of Figure 4,
R 1 = 83 K (after trimming)
BUT:
ell
n
dt (46)
<
D
~
OR
4096 IL
fIN
I
VREF + VIN (F.S.) ]
[
2Rl
R2
(53)
2 Rl fIN
APPENDIX C: PROPER SELECTION OF THE
INTEGRATOR CAPACITOR CINT
IAVol=_ICINT
o
r-
........
VIN (F.S.) = 2.000 volts
Net Count Error = -2 + 2.41 =.41 counts
)
r-
-
R2= 100Kn
CINT = 0.0232 tlF
7/fIN (
~
ell
ACount = 100 n
2000 = 2.41
(43)
83Kn
The net count error will then be due to the sum of the error associated with VREF and the error due to the change
is RDS(ON) which is:
If the reference resistor R 1 and the input resistor R2 have
the same temperature coefficients, the temperature effects
of these resistors will be balanced out.
....
....
ell
For the application circuit of Figure 4:
We can now examine how the temperature dependency of
RDS(on) (U/D Switch) will affect the accuracy of the DVM
application circuit of Figure 4. Using Figure 3, it can be
seen that RDS(on) will increase by 100 n when the ambient
temperature changes by about 50°C (VREF = 6.8 volts).
The maximum error (YIN = VIN (F.S.)) will be:
~
Z
•
AND
so that by substituting (40) into (39) yields
A Count = ARI
Rl
IAVol=--CINT fIN
7·33
~
...
::
Q
....
........
......
....
-...
o
Q
I
;!:
Z
O_
- -_
-
I
750
1
13
11
10 Mn
1 Mn
100 Kn
10 KG
r
I
ANALOG
INPUT
! L,"~~J~~!
1
~~____ .":" ~____~~JI
IL.: ~ __~>-_-:-~~
5
I
oP2 1
OP11
:
. ..!!... -.!.. _.2.2 -,
I
3C
0
10.lf the readout has a slight negative
offset with a grounded input. an
optional trim capacitor can be added
to the board (where TR 1M is marked).
This can be a 4-40 pF trimmer or a
fixed capacitor as needed to zero
the reading.
I
I
If
:;"
"
....
"
A..
z
N
I
o!:z
-J20K-
-IM-lOOK-
=:
-75K-
"V
....
N
-----
C;
"".
"
"",022-
-510--
~
C>
.I
-33K-
....
."
N
CIRCUIT BOARD
(Top View)
...I
'"I
Z
o
o
7416
9368
-150- - - - - - -
-150-
III
I III III
Siliconix
LED DISPLAY BOARD
(Front View)
N
(;
,...
o,...
o
,...
..I
..I
..I
o
o
J>
........
c
N
n
o
o
I II iii
::::I
.:
<
CD
~
CD
CAUTION!
The AC Ime I/O/tages ,"IOClated With this bOard can be fatal to human 'lfe. Proper
pncautions for opllratmg thIS Instrument must be obserred by the user. S,licon/J(
assume' no llab/My fOf unsafe operation.
Siliconix
7·37
OA14-l (LOllO/LOlll)
..,.
l.>
BASIC DVM
Electrical Parts List
CD
Quantity
Required
~
0'
o
J
)C'
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
32
1
OPTIONAL POWER SUPPLY
Electrical Parts List
Recommended Manufacturer
And Part Number
Description
Analog IC
DigitallC
BCD to 7 Segment Decoder/Driver
Timer IC
Hex Buffer/Inverter
±1 Overflow LED Display
7 Segment LED Display
NPN Transistor
NPN Transistor
PNP Transistor
Current Limiting Diode
0.0221lF BO Volt Mylar Cap.
0.0561lF BO Volt Mylar Cap.
0.0022 Ceramic Cap.
4-40 pF Trimmer Cap. (Optional)
Johanson 9304
O.OIIlF Ceramic Cap.
10K Potentiometer
75n
l{, watt
5% Resistor
150n
% watt
5% Resistor
510n
l{, watt
5% Resistor
l{,watt
3Kn
5% Resistor
l{, watt
10Kn
5% Resistor
12Kn
l{, watt
5% Resistor
l{, watt
33 Kn
5% Resistor
75 Kn
l{, watt
5% Resistor
100Kn
l{, watt
5% Resistor
120Kn
l{, watt
5% Resistor
lMn
Y.& watt
5% Resistor
Socket Pins (use for LDll0 and LOllI)
1B pin .Edge Connector
CTS X201Rl03B
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Molex
AmphenoI143-01B-03
--
Quantity
Required
Siliconix LOllI
Siliconix LDll0
Fairchild 9368DC
Signetics N E555V
NationalDM7416N
Litronix DL-701
Litronix DL-702
Motorola 2N4400
National 2N4274
Fairchild 2N5139
Siliconix J507
Sprague 192P2239R B
Sprague 192P5639 R8
--
--
-
Description
Supply Transfc,rmer
PNP Transistor
NPN Transistor
5.6 Volt Zener Diode
11 Volt Zener Diode
100 Volt Recti-fier Diode
1,000 IlF 25 Volt Electrolytic
500 IlF 25 Voll Electrolytic
0.01 IlF Ceramic Cap.
lOOn
Y..watt
10% Resistor
39n
2 watt
10% Resistor
l{, watt
510n
5% Resistor
560n
Y.. watt
10% Resistor
~watt
5% Resistor
1 Kn
Power Cord, 2IVire
Fuse Holder
I/BAmp Slo--Blo Fuse
Heat Sink (for ;!N 1711 transistor)
1
1
1
1
2
4
1
1
3
1
1
1
1
1
1
1
1
1
Recommended Manufacturer
And Part Number
*Signal or EWC DPC24-450
Fairchild 2N5139
Motorola 2N 1711
Motorola IN752
Motorola IN962
Motorola IN4002
Sprague 503DIOSG025EU
Sprague 503D477G025EK
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Allen-Bradley
Little-fuse 357-001
Wakefield 205-CB
OPTIONAL 5 RANGE VOLTAGE DIVIDER
1
1
1
1
1
1
2
10Mn
0.1%
Y.. watt Resistor
l{, watt Resistor
lMn
0.1%
l{, watt Resistor
100Kn
0.1%
l{, watt Resistor
100Kn
0.1%
l{, watt Resistor
1.11 Kn 0.1%
2 Pole 5 Position Rotary Switch
Banana Jacks
*This transformer may be ordered from:
Signal Transformer Co.
1 Julius Street
Brooklyn, NY 11212
(only direct from factory)
-
1-.
-
-------
The divider resistors should
be mounted _~n the rotary
range switch.
Centralab PA-3 and 30° Index
EWC, inc (#DPC-24-450BI9)
725 Federal Avenue
Kenilworth, NJ 07033
(available through factory or
West coast distributors)
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Siliconix
7-39
LD110/111 3% Digit DVM Demonstrator
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41/2 Digit AID Converter Set
designed for . . .
• Digital Scales, Thermometers
• Microprocessor Data Acquisition
Systems
• Scientific Instrumentation
~LD121
with LD121A
Replace
.
DESCRIPTION
C
H
Siliconix
BENEFITS
• High Accuracy Digital Voltmeters,
Panel Meters
~
...
...
...
......
:I>
• 0.005% ±1 Count Accuracy Ensures High
System Performance
• Two Ranges, ±2.0000 V or ±200.0 mV,
With Single Resistor Change
• 28,672 Count Maximum For 42.5% Overrange
• Sample Rate From One to Five/Second
• Auto-Zero Cycle Nulls Out Internal and
External Amplifier Offsets
• Auto·Polarity Operation with One Reference
• Multiplexed BCD Output For Easy Interface
To Displays
• Two Overrange Outputs, Underrange Output,
Blink Inhibit, and Convert-On-Command
Capabil ities Allow Easy Interface to External
Circuitry and Microprocessors
~
C
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The LD122/LD121 A 4'1:. digit A/D system uses Siliconix's "Quantized Feedback" conversion technique. Intrinsic features
of this system are Auto·Polarity, Auto·Zero and ratiometric operation. No critical components are required except for a
stable voltage reference and a low noise op amp. The technique offers superior linearity, normal mode rejection, and stabil·
ity due to the simultaneous integration of the unknown input and the reference voltages. Unlike other conversion tech·
niques, the integrator output voltage never represents more than 100 counts, thus critical, high resolution performance is
not required of either the integrator or comparator.
The LD 120 analog processor is fabricated with a unique combined PMOS/Bipolar process. It contains all the necessary
amplifiers, MOSFET switches, and switch driver circuits for the system. The reference voltage input is fully buffered on the
LD120 to eliminate the reference switch resistance as a source of error. All the amplifiers are internally compensated. The
LD120 directly interfaces the LD121A digital processor with no additional active components required.
The LD121 A synchronous processor contains all the digital circuitry for the quantized feedback system. Device outputs
supply two overrange signals, underrange, sign and 41/2 digits of multiplexed BCD data. (All outputs are TTL compatible).
Overrange is also indicated by blinking digit strobes above 20,000 counts. An input is provided to inhibit this feature at
user option. Microprocessor controlled operation is simplified by a start conversion input that allows conversion·oncommand.
Both devices are supplied in space saving 300 mil dual-in-line plastic packages. The LD120 has 16 pins and the LD121A has
18 pins.
FUNCTIONAL BLOCK DIAGRAM
1&1
PIN CONFIGURATIONS
Dual-In-Line Package
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QUALITI
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CD
ORDER NUMBER LD120CJ
SEE PACKAGES
.,...
Dual-In-Line Package
CD
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LD120
LD121A
SWITCH STATES ARE FOR A LOGIC "0" AT UtD AND MtZ INPUTS.
Siliconix
ORDER NUMBER LD121ACJ
SEE PACKAGE 19
7·41
ABSOLUTE MAXIMUM RATINGS
Operating Temperature . . . . . . . . . . . . . . . . . o to 70°C
Storage Temperature ............... -65 to 125°C
Power Dissipation (Package) * ............. 750mW
VIN (Pin 15,2 LD120) . . . . . . . . . . . . V--
LD121A Clock 'nput
Start Convert
vLD120 Comparator Output
_.r4>Vss
IN
t
v,N
*
LD121A Comparator 'nput
7-43
....
CD
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......c
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c-4
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c-4
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FUNCTIONAL SYSTEM OPERATION
Timing: The external oscillator is divided to generate a 2-¢
clock on the synchronous digital chip. A time base generator
divides the clock frequency into sampling intervals of
49,152 pulses of which 16,384 pulses are the Auto-Zero
interval and 32,768 pulses are the measure interval.
Auto-Zero Interval: The connection diagram in Figure
illustrates the system during the Auto·Zero interval. The
input buffer is switched to reference ground and supplies
a current equal to its offset voltage divided by R2 to the
integrator summing mode. The U/D buffer is toggled by the
digital processor between VREF and ground with a 50%
duty cycle. This results in a current flow equal to VREFI
R 1 to the summing node half of the time. The AZ capaci·
tor, CSTRG, assumes a voltage, VSTRG' that is equal to
the average value of integrator output. The AZ buffer
supplies a current to the summing node equal to the
VSTRG voltage divided by R3.
The system will reach an equilibrium when the sum of the
DC currents into the summing node equal zero. At this
time, the current through R3 equals -'I:. VREF/R1 plus
the small currents necessary to cancel the offset of the
input buffer and integrator input bias current. Capacitor
CSTRG "stores" VSTRG when the AZ switch opens at
the end of the Auto-Zero interval. The digital BCD counter
is inactive during Auto-Zero. It is reset to zero during the
last clock pulse of the Auto·Zero interval.
THE UfD CONTROL DURING THE MEASURE
INTERVAL
The UfD buffer is switched to VREF when the UfD control
is low. In this state the currents through R1 and R3 sum to
'I:. V R EFIR,. A high level on the UfO control connects the
UfO buffer to ground. During this state the sum of the
currents through R1 and R3 sum to -'I:. VREFIR1' In one
clock cycle, a charge equal to VREF/2R1flN coulombs is
either added or subtracted to the integrator capacitor.
The BCD counter is decremented for each addition of this
quantized charge and incremented for each subtraction of
quantized charge.
THE ~..~EASURE ALGORITHI'..1
The input is connected to VIN during the measure interval
and supplies a current to the integrator equal to VIN/R2.
DIGIT STROBES
BCD OUTPUTS
REFERENCE BUFFER
4
HIGH
QUALITY
GND
-=
UfO
5
I
I
I
I
I
I
I
I
IL ________ _
5 COMP 3
MIZ
13
AZ FILTER
ANALOG
GND
7.5K n
elK
Vss
Vss
*CSTRG
LD121A
LD120
Connection Diagram
Figure 1
7-44
Siliconix
VDD
GND
r0-
FUNCTIONAL SYSTEM OPERATION (Cont'd)
This causes the integrator output to move away from
VSTRG' The digital processor attempts to keep the inte·
grator output near VSTRG by adding or subtracting
quantized charge to CINT' The net amount of charge
required to accomplish this is totaled by the BCD counter.
The BCD count at the end of conversion equals the number
of charge parcels necessary to cancel the input current
supplied through R2' The resulting count is proportional to
the voltage at V IN'
integrator output toward VSTRG and accumulating counts
in the BCD counter in groups of 14 counts. This dual duty
cycle control technique results in a fixed number of UfD
control transitions, regardless of the value of V IN; therefore,
these transitions cannot cause linearity error. The first few
periods of the measure interval are illustrated in Figure 3
for a negative V IN'
UfD DUTY CYCLE CONTROL DURING THE MEASURE
INTERVAL
The BCD counter contents equal a multiple of 14 counts at
the end of the measure interval. A residual voltage on CI NT
represents the remaining unresolved portion of the input
voltage. This voltage is cancelled and the corresponding
counts accumulated during a brief override period at the
start of the AZ interval. Normal AZ interval action is
inhibited until this residual count is resolved.
The digital processor contains a modulo 16 duty cycle
counter that provides the UfD control output. This counter
examines the state of the comparator once each 16 clock
cycles during state 15. If the comparator is high, the UfD
control will be high for one cycle and low for 15 cycles
in the next 16 clock cycle period of the duty cycle counter.
If the comparator output is low, the UfD control will be
high for 15 cycles and low for one cycle in the next period
of the duty cycle counter. Figure 2 illustrates these waveforms. The effect of these two duty cycles is to source or
sink a net 14 charge parcels to CINT' thus driving the
U/DDUTYCYCLEA
UfD DUTY CYCLE B
...
C
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...
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AUTO-ZERO OVERRIDE AT THE END OF MEASURE
The override period starts at the end of the Measure Interval. The input buffer is switched to reference ground as no
additional charge is desired from V IN. The UfD control is
set high. After the comparator goes high, the UfD control
is switched low at the next state 8 of the duty cycle
counter. The next transition of the comparator ends the
nL.__________________...J1L
I
L
DUTY CYCLE
COUNTER STATE
9
0
10
11
12
13
14
15
CLOCK
Modulo 16 Dual Duty Cycle Counter Waveforms
Figure 2
I
1'1
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M/Z~
III
III
III
III
II
II
III
II
I
I
DUTY
CYCLE
I
I
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U/D~
I
I
COMPARATOR SAMPLE
POINTS FOR NEXT
DUTY CYCLE SELECTION
COMPARATOR
OUTPUT
A
A
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I I
III
III
I II
III
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II
II
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COUNTER
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COUNTER
=
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COUNTER = -14
Measure Interval Timing IVIN ~ -1 VI
Figure 3
Siliconix
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INTEGRATOR
OUTPUT
ID
7-45
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FUNCTIONAL SYSTEM OPERATION (Cant'd)
CSTRG and results in highly stable Auto-Zero loop characteristics_
conversion and the BCD counter is synchronously inhibited_
The output latches are updated on the next clock pulse
with the sign and contents of the BCD counter_ The override period ends (end of conversion) and normal AZ action
is initiated by the closing of the AZ switch. The duty cycle
counter now drives the UfD control high during states 0
through 7 and low during states 8 through 15 for the required AZ interval 50% duty cycle .
DIGITAL INTERFACE FUNCTIONAL DESCRIPTION
BCD Outputs- (Pins 9, 10, 11 and 12): The output latch
contents are time multiplexed in a digit serial, bit parallel
fashion through 4 push-pull TTL compatible output buffers.
A high level (sourcing current from VSS) indicates a one
and a low level (sinking current to ground) indicates a zero.
BO is the least significant Bit. Figure 5 illustrates the
timing relationship. All BCD outputs are valid during digit
strobe ti me.
Figure 4 illustrates the events at the end of the measure
interval. The slope of the dotted lines is proportional to
the unknown current through R2 .
Digit Strobes-(Pins 1,2, 16,17 and 18): Figure 5 indicates
the operation of these outputs. The strobes are TTL compatible. Only one strobe is high at one time. The strobe period
The self oscillation following the override period keeps
VINT near VSTRG until sync is achieved with the duty
cycle counter. This feature eliminates large transients on
DUTY CYCLE
CONVERTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . . ,
I
~M
l
MlZ SWITCH OPENS
UfO
INTEGRATOR
OUTPUT
VSTRG
COMPARATOR
Alogrithim Waveforms at the End of the Measure Period
Figure 4
-------jl
05~~--------------------__~r___l~_____________________
32CLOC"-I
CYCLES _
I
~~------640 CLOCK CYCLES
1--96--j
04 ______~r___l~
______________________
0 3 - - - - - -______~r___l~
~nIL
_____________________
_________________________________________
02 __________________~r___l~
___________________________________
Dl--______________________~r___l~
___________________________
·o---...J
., J
·2 - - - - - '
·3 _____________-"
DATA
SIGN/OR/UR
POLARITY
BLINKING
INHIBIT
1
OVERJANGE 2
:.. 25,000
1
INPUT
OVERRANGE 1
~ 20,000
UNDERRANGE
.;;:; 1,799
LD121 Digital Output Timing Diagram
Figure 5
7·46
Siliconix
I
t
QVERRANGE!UNDERRANGE
DO NOT REPEAT UNTIL THE
NEXT CONVERSION CYCLE
I
SIGNALS
FUNCTIONAL SYSTEM OPERATION (Cont'd)
is equal to 640 clock cycles with a 15% duty cycle. An
inter-digit blanking period of 32 clock cycles permits easy
interface with gas discharge displays. The strobe sequence is
D5 (MSD), D4' D3, D2 , Dl (LSD).
Clock Input (Pin 8): Pin 8 requires an external clock input.
The system operates from the positive clock transition allowing a 30 to 70% duty cycle in the external oscillator
waveform. To maintain the linearity specifications of the
A/D converter set the short term stability of this oscillator
'should be better than 1 part in 2 x 104 .
Sign/Overrange/Underrange (Pin 13): This pin operates as
a TTL compatible output during Dl' D2' D3 and D5 strobe
times and as an input during D4 strobe time. Figure 5
indicates the timing relationship. Information is presented
to this output as follows:
At D5 Time -
At D4 Time -
At D3 Time -
At D2 StrobeTime
At Dl StrobeTime
Polarity is indicated by a high level for
positive and a low level for negative. It is
valid approximately 0.25 Ilsec after D5
goes high unti I the end of each D5 strobe.
The output buffer assumes a high impedance state. An input latch samples
the voltage level imposed on this pin
during D4 time. A high level will inhibit
the overrange blinking (digit strobes are
suppressed during zero interval). An
internal pull down resistor will hold
the pin voltage low if the pin is
unconnected or the load is high impedance. An alternative method for selecting
overrange blinking is the choice of output buffer. A TTL buffer connected to
pin 13 provides a pullup inhibiting overrange blinking. A NPN buffer driver
provides a pulldown yielding normal
overrange blinking.
If the count is equal to or greater than
20,000, a single positive going pulse will
occur at the beginning of the first D3
time after the end of conversion cycle.
The pulse width equals one clock cycle.
The overrange blinking is momentarily
inhibited when overrange pulses are
present to prevent the display blinking
feature from interfering with the
decoding of the overrange output.
A second overrange pulse occurs at the
beginning of the first D2 time, after
the end of conversion, if the count is
equal or exceeds 25,000 counts.
A single pulse occurs at the beginning
of the first Dl time after the end of
conversion, if the count is less than
1800 cou nts.
All overrange and underrange signals are one clock pulse
wide. They occur only once per measure/zero cycle.
Start Conversion (Pin 7): A low level on this TTL compatible input holds the system in the zero mode continuously.
A positive going pulse at least one clock time wide initiates
one conversion cycle within 16 clock cycles after system has
completed minimum auto zero cycle. The di gital data is
valid after 32,850 clock cycles. A static high level on this
input provides normal cyclical operation. An internal pull up
resistor allows this input to remain unconnected when
conversion control is not desired.
APPLICATIONS
,...
"...
,...
"......
~
C
~
1. The recommended supply voltages are:
V+= 12 V ±10%
VDD, V- = -12 V ±10%
:I>
VSS=5V±10%
VREF = 2 V to 10 V
2. The reading is essentially the proportionality of VIN
compared to VREF as shown in the gain equation:
R1
65,536
E
OUT
R AD
= (VIN - VHI-Q GND). • -COUNT
R2
VREF
R 1 is independent of the U/D switch resistance due to
the incorporation of the U/D buffer amplifier in the
LD120. Gain can be calibrated either by varying VREF
or trimming the resistance of Rl to obtain the correct
full scale reading.
3. The output of the integrator should always be more
positive than -9 V (for VDD = -12 V) to obtain specified accuracy:
Va (min)
Va
.
(min)
> -9 V
VIN ImaX)]
-- + ----
VREF R3
15
[VREF
2RI
fCLKCINT
2RI
= - --- -
R2
Change value of CINT to set VINT(P-P),
Large integrator swing provides the best performance.
VINT (P-P) = 6 to 8 volts is recommended.
30
VINT (P-P) =
fCLK CINT
[VREF
VIN (max) ]
- - +---2Rl
R2
4. Although any oscillator frequency from 50 kHz to
250 kHz can be used, frequencies that provide integer
number of line frequency cycles per measure period
provide maximum line noise rejection. These frequencies
are:
fCLK =
32,768 F LI N E
n
• n = 8,9,10, ... 40
fCLK = 163,840 is popular since it provides both 50
and 60 Hz rejection.
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.......
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5. The sampling rate = fCLK/49,152 cycles/sample.
~
6. After a start conversion pulse, data is valid 32,850
clock pulses later and remains valid until at least 32,768
clock pulses after the next start pulse. During continuous cycle operation, data is assured valid when M/Z
is high or 100 clock cycles after the one/zero transition
of M/Z.
7. Any capacitive coupling between U/D and Compo is
detrimental to proper algorithm operation. PC board
layouts should not allow these traces to be adjacent.
Siliconix
7-47
CD
Ul
APPLICATIONS (Cont'd)
8. All power supplies should be capacitively bypassed to
ground for maximum count stability.
9. CINT and CSTRG should be selected for low leakage.
Silvered mica is recommended for CINT and mylar for
CSTRG. Polypropylene capacitors also work well for
both CSTRG and CI NT.
10. For a given leakage into CSTRG of ISTRG:
fl.t IAZ
fl.VSTRG = CSTRG
where fl.t = a measure interval = ~
FSAMPLE
fl.VSTRG will inject a fl.1 integrator of fl.VSTRG/R3
Now a fl.1 integrator would have been equivalent to a
LWIN/R2
11. Interfacing the LD120/LD121A to Microprocessors: A
description of interfacing the LD120/LD121 A to the
8080 J.!P is given in AN77-3. Some of the timing details
warrant description here.
The end-of-conversion is determined by gating M/Z
• U/D • COMPo At this time, all BCD latches are updated with the contents of the latest conversion.
We recommend using the positive edge of M/Z to
interrupt the processor. Next, test for a high 05 digit
strobe (MSD). Once 05 is high load the BCD data from
BO-B3 lines and the polarity information from the
SIGN/OR/UR line. Next delay 128 LD121A clock
times (this assures that the 04 data is valid) then load
BO-B3 lines containing the 04 data. Next delay
another 128 LD121A clock times (this assures that
the 03 data is valid) then load BO-B3 lines containing
the 03 data. Repeat this process for 02 and finally the
01 (LSD) data load. In flowchart form (see Figure 6).
So the equivalent input drift is
1 R2
b.VIN= - 2 R3
2
ISTRG
3 FSAMPLE. CSTRG
INTERRUPT ON
M/z POSITIVE EDGE
the Y, factor is provided by integrator action.
OR
TEST FOR MIl POSITIVE
Example: We wish to see 1 count (0.1 mV of LWIN on
the 2 V range) of drift for the circuit of Figure 7 with
ISTRG = 100 pA @70°C. What CSTRG is needed?
Answer:
R2
CSTRG = R3 3
ISTRG
FSAMPLE· fl.VIN
lOOK n 1
10- 10 F
62Kn x x 3Hzxl0-4V
-a
= 0.18 J.!F Minimum
READ DATA IBo-83)
ANO
STORE INTO MEMORY
Typical Leakage Over Temperature
'0{)0
DELAY TO NEXT
DIGIT STROBE
128 LD121A
eLK PERIODS
'AZ. Vs = ±15~
/. /"
'00 EIAZ. VS" ±12V
'0
./
./
/. /"
~ ,/
-'IN. Vs - ±15 V
I
,
25
./
/lIN. Vs '" ±12 V
35
45
55
65
75
85
Figure 6
7-48
Siliconix
CIRCUIT BENEFITS
• Overrange Blinking
• 0 ~ ±1.9999 Input Voltages
• Zero Adjust to Null Offset Introduced by PC Board
Leakages and Comparator
HEWLETT PACKARD DISPLAVS
13
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7653
14
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OS8857J
NATIONAL
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16
15
7653
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---4
-12V
RT~ 13 Kn;
USE4,7KTRIMMER
18111615'4131211'0
IN SERIES WITH '0 K
H
LD121A
'ZERO ADJUST AC COUPLES SMALL
AMOUNTS OF POSITIVE OR NEGATIVE
CHARGE ONTO THE STORAGE CAPACITOR
FROM THE MIZ SIGNAL
INPUT
R,
R2
R3
R4
RS
AS MARKED
lDOKn~l%
C,
C2
1200pF MICA
10J.lFPOLVCARBONATE
62KU
47KH
47Kl1
1MU
CR)(XX ARE CURRENT
REGULATOR DIODES,
see
SILICON IX FET OESIGN CATALOG
ALL RESISTORS ~5% 0 125 WATT
METAL FILM UNLESS NOTED
+12V
D-<~--:::"----------I
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Siliconix
7-49
~r---------------------------------------------------~========l
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Siliconix
...
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Function/Application of the
-
LD120/LD121A 41f2 Digit AID
Converter Set in Measurement
Systems
Q
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...
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C
il"vTRODUCTiOIV
ible with regard to analog signal range, external voltage
reference level, and output display format.
The SiIiconix LD 120 and LD 121A Integrated Circuits permit
the building of low cost and physically' small 4-1/2 digit
panel meters, voltmeters, and other A/D conversion systems
where resolution and accuracy are of prime importance.
The set can provide basic ranges of ±2 V and ±200 mV
full-scale and, with an external amplifier and analog switch,
can read ±20 mV full-scale. The quantized feedback algorithm of A/D conversion provides inherent auto-polarity
and auto-zero operation, and the PMOS/Bipolar technology of the LD120 analog chip provides >109n input
impedance and buffered reference input. The set is flex-
This application note will describe the basic operation and
circuit constants, and will develop some typical applications
circuits.
Description of Operation
There are two main periods in a sample of analog data;
the auto zero period and the measure period. Descriptions
of these periods will be referred to Figure I.
BCD QUTPUTS
REF
OUT
HI
QUALITY
GND "::"
REFERENCE BUFFER
I
I
I
I
I
I
I
I
M/Z
IL ________ _
AZ FILTER
GND
elK
ANALOG
R5
GND
Vss
LD120
LD121A
Connection Diagram
Figure 1
7-50
Siliconix
Auto-Zero Interval
measure interval. The charge balancing in the measure interval calculates so:
In the auto-zero period, the input buffer is connected to
high-quality ground and the auto-zero buffer is connected
to the integrator output. Ignoring up/down and transient
waveforms for the moment, the DC currents presented to
the integrator are:
Q=
VIN - VHI-Q
R2
J>
Z
....
....•
...
I VREF
L1t == Count - - - fOSC 2RI
where L1t = 32,768/fOSC and is the measure period.
Rearranging,
I
I
- VOFFSET, INPUT BUFFER
INT = BIAS, INT =
R2
+
Count =
VOFFSET, AZ BUFFER +
VIN-VHI-Q RI
VREF
• 65,536.
R2
R3
VOFFSET, REFERENCE BUFFER
------~------------------+
RI
VAZ, OFFSET + VHI_Q
R3
R2
VAZ OFFSET is the fraction of the auto-zero voltage
acros~ CAZ which will null all the other quantities mentioned above. Also being injected into the integrator input
is VREF/2RI since the up/down line is being toggled at
50% duty cycle by the LDI2IA. When the dynamics of the
system settle out toward the end of the zero period, CAZ
will have the voltage
R3
VAZ=VAZ OFFSET-- VREF·
,
2RI
The measure interval cannot resolve single counts; it can
only resolve multiples of 14 counts. Immediately after the
measure and into the auto-zero period is the override
period. The input buffer is reconnected to VHI-Q and the
CAZ switch is left open. The LDI21A sends the integrator
positive with respect to VAZ (see Figure 3), then returns it
to VAZ potential, stopping when the LDI20 comparator
changes states, keeping track of the count in single clock
times. The override period can exist a maximum of 56
clock times into the zero period, assuming a non-overload
VIN·
Since only 14 of the 16 counts in the U/D waveform
produce net counts, there are ±28,672 counts maximum
out of the 32,768 clock times available.
Component Selection
-VREF R3/2R I provides a reference quantity of exactly
negative one-half the integrator input current injected by
the reference current through R I.
The auto-zero period is 16,384 clock times long.
RI and R2: The nominal currents into the integrator are
20 !LA full-scale through R2 and 80 !LA through RI. These
values are chosen for minimum system noise consistent
with maximum amplifier linearities. Then
VIN (F.S.)
R2---20 !LA
Measure Interval
During the measure interval, the input buffer is connected
to VIN and the auto-zero capacitor is disconnected from
the integrator output. The quantity VAZ, OFFSET remains on CAZ, and analog offsets are nulled out. Due to
the quantity -VREF R3/2RI being held on CAZ, an
effective VREF/2 or -VREF/2 is applied through RI when
U/D is 0 and I, respectively.
Referring to Figure 2, the U/D waveforms are of 2 kinds:
I clock time up and 15 down; and 15 clock times up and I
down. The LDI21A iogic generates these waveforms in response to the LDI20 comparator output. The system
attempts to return the integrator output to VAZ regardless
of the input. Since the integrator sees both input and
reference currents simultaneously, its output does not
vary far from VAZ.
The BCD counter counts up once per clock time when
U/D=I and down once per clock time when U/D=O, causing
the displayed count to be proportional to the amount of
VREF/2RI that was required to null VIN/R2 during the
VREF
RI=--·
80 !LA
VREF should be in the range of 2 V to 8 V, for reasons of
system gain stability and noise characteristics. Some trimming of either R2 or R I is required for exact full-scale
reading.
IIJI
R2 is determined by the equation previously given
.......
J>
a
n
o
::I
<
CD
R2 = 65,536 RI [VIN (FULL-SCALE) - VHI-Q] .
VREF Count (FULL-SCALE)
..
The oscillator frequency is determined from fOSC
49,152 x Sample Rate.
.
~
Values of R3 and CINT are derived from the consideration
that the integrator output should be at least 3 V from either
supply rail. The negative rail is the one of interest, since
VAZ is negative. A starting point is to set the integrator
AC swing at about 6 V pop. Then
VREF
CINT== - RI
Siliconix
30
6V
fOSC
7·51
CD
1ft
-....c
...
C"I4
Q
UIO DUTVCVCLE A
..I
o'"
C"'I
Ufo DUTY CYCLE B
...
-.........
nL_______________________
I
L
DUTY CYCLE
COUNTER STATE
Q
..I
0
9
10
11
12
13
14
15
CL.OCK
I
.....
M/Z~
z
.c
----+I----A----~----A----_r----
DUTY
CYCLE
U/D~
~~
______
~nL_
________
~
L
COMPARATOR SAMPLE
POINTS FOR NEXT
DUTY CYCLE SELECTION
COMPARATOR
OUTPUT _ _ _ _- '
INTE~~~~~~~------~~---------------------------------4--------~--------~~~-----------,~--_____________
COUNTER CONTENTS = -14
STATE M/Z
LII,Z
utD
INTEGRATOR
OUTPUT
VSTRG
COMPARATOR
Up/Down and Integrator Waveforms
Figure 2
7-52
Siliconix
SWITCH OPENS
y
•.-...-..
...
-...
~
Z
.----i1')---1>1
~I---"-------"""-o 6t~PUT
L3 30Lo-R
/J.H
•
~
...
~
+ c,
~50$.lF
2N..~~L.
:.;,: 22K
;r:.oo
'1
rC
C2
;O~/J.F O~~~UT
12 V
VCCI-'B'+....._ ,
3 OUT
~
555
~ ~ ~
"
u
0
I' 15 l'
RESET.!...
TRIGGER
L-
l/ZW
22K J-6_ 0.,::
I
E
Ca
50
w
o
j,lF
........
rC
-=
......
THRESH
'OK
P
h)
J-1o.0T5V~'20PF
-•
CLOCK OUTPUT
(lS0 KHz)
0.01 jJ.F
22K
LD120/121A Power Supply and Clock
Figure 3
The factor of 30 results from the fact that 2 cycles, I
up and I down, each having an effective IS clock times
before folding back for I clock time, are required to cause
the 6 V pop swing. The envelope of integrator waveform can
be almost completely above VAZ or below it; so a VAZ =
-3 V is appropriate. Neglecting the offset components of
VAZ, which are relatively small, we have
and setting VAZ
The 13 V output is pulled to 4.3 V upon connecting 5 V
input. This allows the 555 to start oscillating, driving Q I
and Q2. Q2 pulls current through L for approximately 50%
of the time, and releases it to allow the flyback voltage to
charge C I. The negative edge of Qis collector waveform
charges C3 through its associated rectifier circuitry, and the
12 V zener absorbs all unused energy available from L in
shunt regulator style.
The circuit performs adequately for a supply of 4.5 V to
5.5 V input, and the 555 being run from the 13 V output,
is not modulated by the 5 V power line noise.
=-3 V,
Display Formats
CAZ is chosen from the range of 0.1 to I/lF, as determined
by zero drift considerations given in appendix A.
R4 and R5 are selected in consideration of settling time of
Figures 4 and 5 show common cathode and anode type
light-emitting diode (LED) display circuits. Both are
multiplexed to conserve supply current.
the system in the auto-zero period. Typical values are 47K
and 4.7K for CINT = 1200 pF at 3 samples/second.
As for component quality, R3, R4, and R5 are non-critical.
RI and R2 should be metal film or wirewound. CINT
should be mylar or better quality and CAZ must be mylar,
polycarbonate, or polypropylene, the latter being best with
regards to dielectric absorption characteristic.
Finally, the oscillator must be short term stable, even
though long term drift is not a problem.
APPLICATIONS CIRCUITS
Power Supplies
The plus and minus 12 V supplies can be obtained from a
standard 5 V supply, as well as the required oscillator signal,
with the circuit in Figure 3.
The duty cycle of each strobe is 15%. If an average LED
current of 5 rnA is desired, each digit strobe switch must be
able to pass 5 rnA x 7 segments/0.15 =233 rnA, necessitating
the use of strong drivers. Also the decoder/driver must be
able to pass 5/0.15 or 33 rnA. The use of high-efficiency
LED's, running at an average of 3 rnA, would be advisable,
but not necessary.
Figure 5 shows a simple circuit for leading zero blanking
when a decoder/driver has that function built in. There are
2 flip flops in the circuit. D5 initiates the G3/G4 latch to
begin a scan in the order D5-D4-D3-D2-DI. G3 enables the
GI/G2 latch until DX resets G4 and G3, disabling GI/G2.
GI and G2 form a ones-catching latch through RBI and
RBO; RBO = I resets the latch, disabling RBI. Thus either
DX or RBO can terminate a zero blanking sequence.
Siliconix
7-53
III
•c
........
n
o
~
<
CD
....
..
CD
fIt·
-....c
...
.....
-..
5V
CIII4
5V
Q
120n
........
0
CIII4
-/
Q
.....
......
I
Z
C
APPROPRIATE INVERTERS:
MC75452 (MOTOROLA)
APPROPRIATE DISPLAYS:
~~::~ (NATIONAL)
"9967
(FAIRCHILD)
ANY NPN DARLINGTON TRANSISTOR
J
APPROPRIATE DECODER/DRIVERS: 088857
+1
FND71
(FAIRCHILD)
5082·7656 (H.P.)
~~~'---JL!M~A~N~a64~O.-!'!!!M~ON~S~A~N~TO~J
74C48
Common Cathode LED Display (±19,999 Counts max. with Blinking)
Figure 4
BCD
DECODERI
DRIVER
MINUS
SIGN
FROM
1------------OD1
L-____________________________
LQ121A
~D2
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-QDa
L-____________________________________________
~D4
L-____________________________________________________
~D5
2N4402 " ' J - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - o S I G N
AP:~G~:R~'ATEBUFFER'
5V
APPROPRIATE DECOOER/DRIVERS: 7447
088873/088874 (NATIONAL)
STROBE
APPROPRIATE LED DISPLAYS: FND507
5082·7651
MAN3610
9374
2N4403
1/6 X 74C04
(FAIRCHILD)
(FAIRCHILD)
(H,P.)
(MONSANTO)
DIGIT
ANODE
Common Anode LED Display (±28,672 Counts max. without Blinking)
Figure 50
74L02 OR 74LS02
5V
RBO
DECODER/CRIVER
.. 04 ALLOWS ONE DIGIT BLANKED
03 ALLOWS TWO DIGITS BLANKED
.. Ox
ETC.
GROUND FOR ALL DIGITS
Leading Zero Blanking
Figure 5b
7·54
Siliconix
Figure 6 shows an LCD display circuit. The Siliconix DF4I2
accepts BCD data in strobe fashion, latches it, and presents
decoded 7-segment drive to the LCD display. The overrange,
sign, and leading" 1" are provided by CMOS decoding and
RC memory circuits through the exclusive-or LCD drivers.
The effective LCD drive is 12 V POp with a 6 V supply for
the DF4l2 and CD4030.
characteristics to be used down to a stable 1 J.l.V/LSB
sensitivity. This is necessary for sensitivities greater than
200 mV full-scale because the PMOS transistors of the
LDI20 do not have good I/F noise characteristics.
Figure 7 shows the arrangement for a 20 mV full-scale
front end. If an extremely low source impedance were
used, such as thermocouple, then an amplifier such as the
LM20lA could be used for AI. For higher impedances,
lower bias currents are required until at about IK n or
above, a JFET amplifier will be required. Note that MOS
input op-amps are not quiet enough.
Preamplifiers
A feature of the quantized-feedback conversion is the
ability to use external preamplifiers within the auto-zero
loop. This allows a preamp that is quiet but has poor DC
EXCLUSIVE·DRS ARE CD4030
NANOS ARE CD4011
6V
~
2N4402
IOO1J.LF
-=-
220K
-=
1°.°'
6V
4.7M
~~~ I 1 7 CI 1 7 1_7
f::}fi.>-lrPl 1_7 1_7 1_7 1_7
C
~
o
......
r-
......
3>
C
-
L.
"Fi'0M
.-
'2V
4.7K
()
...
-...r-
.-
.':1~
:r·O'"F~~
Z
.-..
.-..•
~
BP
22M
3>
CD403U
ANDCQ40"
±o.'"F
_
_
-
-
.
,
6V
SUPPLY TO
VOO
BACK I-
OUTPUTS
4.7K
PLANE
DF412
STROBE IN
;~osc,
O.OO'"F~
°4
03
02
.
BCD IN
,,
0,
B
4
2
II
i'
GN°I1-B
I
BCD,
COo
BC02
BCD,
01
02
0
04
)
FROM
LD121A
,
D.
sIGN, OR. UR
-
3>
......
LCD Display
c
Figure 6
n
VREF (=6.BV)
INPUT
t' ~-'2V
[ +0--"+--00 ,"'o-----t''-t---r~ "'---,.-.""".....
-O-""-:-+----l-.::.J
l
o
'0
::I
...
<
+---"-1
.;
CD
M/Z )
u/o
TO LD121A
CD
caMP
U1
L _ _ .J
R, 82K) ,%
=
R2 = 20K
R3 = 6SK
6
M/Z FROM
L0121
lOT
500
SCALE
lOT
FOR A, SELECTION, see TEXT
20 mV F.S. Meter (Front End)
Figure 7
Siliconix
7-55
~ ~--------------------------------------------------------------------------------------,
c
,..
"',.."
470n
r----......
OUTPUT (x1001
'OOK2%
30pF
,K2%
•
......
z--c
~CR022
47051
,2V
~5PF
Ultra-Low-Leakage Preamp
Figure 8
Even the BI-FET op-amps are only good for a 20K n input
resistance up to 7SoC. The circuit of Figure g has an input
leakage of only 2 pA typical at 7SoC and would be usable
with 1M n input resistance_ Although not covered here,
there are ways to reduce leakage effects over temperature
by a factor approaching 10.
Auto-Ranging Voltmeter
The usual auto-ranging voltmeter simply has an input
attenuator whose division ratio is controlled by analog
switches:
1.111M 51
f
101.0K
n
I
-:
CLOSE FOR
2000V RANGE
Calibration is done in this order:
LEAVE SWITCHES OPEN
(I)
(2)
FOR 2V RANGE
CLOSE FOR
20QV RANGE
The problem with this approach is that only 10 pA of total
leakage at the divider node causes I count of offset on the
2 V range. 10 pA is not easily met over temperature.
The circuit of Figure 9 is another approach to the problem_
The input signal is fed through a 10M n input resistor to
the summing junction of an inverting-gain op-amp whose
gain is controlled in 2 ranges. The output of the op-amp is
fed through 2 R2 resistor paths to the integrator input of
the LD 120; the input buffer amplifier and switch of the
LD I 20 are not used. Here is a table of the resistance paths
used in each scale excluding the trimmers:
Range
Op-Amp Feedback
R2 to integrator
2V
20V
200 V
2000 V
3.9Mn
3.9Mn
3_9M n 1139K n
3.9M n I 139K n
390K n I I 43K n
390Kn
390K n I 143K n
390Kn
7-56
Digital control of the range switches is accomplished by
decoding the LDl21A overrange and underrange outputs
and driving a 2-bit counter with the resulting "count up"
and "reset downward" signals_
Although not tried here, a 200 mV range seems possible,
but does require 5 scale ranges_
n
1J --
CLOSE
FOR20V---
RANGE
10.01K
The U426 JFET monolithic pair has extremely low leakage
and is used as the input measure/zero switch_ During the
zero period QI is on and Q2 is off so that the op-amp sees
10M n + RDS FET I to ground as an input. During the
measure interval, QI is OFF and Q2 is ON so that the
op-amp sees 10M n + RDS FET 2 in series with the input
voltage. Since the input (and feedback) resistances are
identical in measure and in zero the auto-zero voltage of the
LDI20 suppresses input offsets over temperature_
(3)
(4)
Offset zero is set with input shorted_
The LD 120 scale factor is adjusted with the auto
ranger in the 20 V range.
Trimmer 2 is adjusted for scalp, factor in the 2 V range.
Timmer I is adjusted on the 200 V range_
Microprocessor Interface
This circuit is used with the Fg series microprocessor,
but the general approach taken is applicable to many
processors.
Figure 10 shows the port wiring and flowchart. The falling
edge of the M/Z line is used to request an interrupt from
the processor, whereupon the I/O program waits for a
decoded end of conversion. This end of conversion signal
occurs when U/D = 0, M/Z = 0, and compo = O. The
program then waits for D5 to occur to synchronize subsequent data pickup_ A delay causes the actual BCD data
to be read in the middle of the strobe, and all subsequent
strobes are sampled in the middle of their intervals_ After
5 strobes have been read in, the data is packed and left in
a location of memory.
Siliconix
:J>
Z
........
......
•
,2V
..
....
r-
EFFECTIVE R2
INPUT o--'>N~+--\M.~o-_--l
o
TO INTEGRATOR
~
o
.......
r-
Q1
U426
1/2
S.aK
o
x OG300
43K2%
....,
T2
,ST
2K
-
:J>
L0121A
FROM lD121A
lSI:~
o,o---~-'~~~----~~--------~
Auto-Ranging Amplifier; 2-2000 V Ranges
Figure 9
EXTERNAL
M/z
INTERRUPT
INPUT
BO
BeDO
B,
BCD,
B2
BeDz
FROM
B3
seo3
LD121A
B.
SIGN
BS
Os
B6
UfO
B7
COMPARATOR
F-B
CPU
I/O
PORr
l1li
:J>
.......
o
n
6.5K
o
::s
<
CD
5.6K
.,...
SV
CD
U1
F-B/LD121A Interface
Figure 10
Siliconix
7-57
~ ~------------------------------------------------------------------------------------~
C
APPENDIX A: ERROR TERMS
..
C"'4
Q
...
.......
.....
-......
....
oC"'4
a
I
z
C
Zero Drift - The main source of zero drift is leakage from
the input and auto zero buffers. Figure 11 shows typical
input and auto zero leakages over temperature. The error
component due to lIN is simply
I:lVIN =I:lIIN • RSOURCE.
For a 1M .n input resistance, and I:lIIN = 30 pA at 75°C,
I:lVIN = 30 J.!V, corresponding to a 0.3 bit offset at 2 V
full-scale, and 3 count offset at 200 mV full-scale. This
offset can be reduced by reducing RSOURCE or by inserting a compensating RSOURCE between VHI-Q and
ground.
The drift due to IAZ is independent of scale factor, and is
caused by the voltage on CAZ drifting during the measure
interval. The magnitude of drift will be
=
The drift caused by thermocouple junctions on the LDI20
is much less than that caused by leakages.
Gain Drift - Full-scale gain drift is caused mainly by
changes in VREF. One count in 20,000 stability per
degree C is 50 ppmtC, so the zener reference should have
at least 10 ppmtC stability and the system burned-in
to reduce long term drift .
The resistors at R2 and R I should track each other over
temperature at least as well as the temp co of the reference.
APPENDIX B
Grounding - The optimum grounding scheme is shown
in Figure 12.
IAZ '32,768
CAZ 'fOSC
This will cause an effective input current to the integrator
of I:lVAZ/2R3, the factor two resulting from the fact that
the ramp of auto-zero drift is averaged by the algorithm.
This input current due to drift is analogous to an input
signal of I:lVAZ R2/2R3, so the count drift is
I:lCount
SO given I:lIAZ = 100 pA when up at 70°C, RI =60K =R3,
CAZ = 0.1 J.!F, fOSC = 150KHz, and VREF = 6.2 V,
I:lCount = 1.16 due to I:lIAZ only.
I:lIAZ
=- - - - - -
·2.15XI09
CAZ fOSC VREF
The main considerations are: analog ground is common to
VREF, CAZ, ±12 V commons, ±12 V bypass, ground of the
signal source, common power ground, case ground; isolation
of currents in the 5 V circuits from those of analog
grounds; a 3-wire input connection for remote signal
sources.
These connection methods will alleviate AC and DC pickup
in signal inputs and integrator positive input (analog
ground) from noise currents caused by the display and AC
environment.
..
ANALOG SUPPLIES
DISPLAY SUPPLY
~
12V
-12V
COMMON GND
5V
r---------,
,
f-l!1000~~
~
100
§
IAZ.VS"±15~
/v
IAZ. Vs" ±12 V
I
Ii'
I ti
,--,
SIGNAL
SOURCE
10
~~/~/~./.~,/~~
g
'IN.VS·±15V
1~~I~~'~IN~.V~S_·~±1_2_V~
I_~I---I
25
35
45
55
65
75
85
TEMPERATURE (Gel
Typical Leakage Over Temperature
Figure 11
7-58
Y,N
V
HI·Q
-
1.-----1
::
v+
I
I
VREF
I
,
~~
v-
I
5V
DISPLAY
LD121A
LD120
V
AND
DRIVERS
ANALOG
AZ
GND
GND
T
J
~
h
L ___ !!!!E.!:!?!::.._J..J
LD120/LD121A Grounding System
Figure 12
Silicanix
+
-
T
~
APPENDIX C: TROUBLESHOOTING
Z
Problem
Jittery Display
.....
.....
...
ra...
Causes
I
rOSC is not stable (short-term)
AC voltage on VIN, VHl-Q, power supplies, or VREF
AC fields passing through unshielded circuit board
Nt
o
r-
Rl, R2, or R3 being carbon composition type
........
Excessively small full-scale sensitivity implemented
...a...
VAlor VREF too small
Offset Drift
Excessive input resistance or CAl too small (see appendix A)
~
-
Circuit board leakages excessive due to flux or moisture absorption
~
A variable offset in grounding system
Poor quality capacitors for CINT or CAl
Sample rate too slow «I sec)
Thermocouple junctions in the 200 mV range
Poor Linearity
Poor quality CINT
V+ or V-less than 10 V
Circuit board leakages to CINT
Noise pickup on UID or loading of UID
VREF modulated by display ground currents
No digit strobes from LDI21A
Clock not functioning
Some terminal of the LDI21A more positive than VSS
~
........
a
n
o
:s
<
CD
.
.,
CD
iii
Siliconix
7-59
~r-----------------------------------------------~======~
......ca:
H
C"4
Siliconix
...
........
Q
Design Aid of the
LD120/LD121A 4112 Digit DVM
o
...
C"4
...
Q
C"4
.....•
.....
ca:
Q
INTRODUCTION
The 4 1/2 Digit AC powered DVM schematic, P.C. board
layout and parts list are intended to aid and speed the
evaluation of the Siliconix LD120/LD121A precision A/D
converter. As all converters of this resolution are sensitive
to trace layout, this pattern demonstrates proper grounding
and signal protection. A switchable 100: 1 input signal
divider is provided to enable the demonstrator to become
a useful laboratory DVM after the evaluation of the system
has been completed.
The metal pattern and component placement diagram are
both printed to a 1: I scale. The component placement art
is intended to be silk-screened on the top side of the board
to provide easy component installation. It can, however,
be used simply as a loading diagram.
The demonstrator DVM features,
•
•
•
•
•
•
±1 count linearity
0.75 count LSD count stability (2 V scale)
1M n source impedance seen by converter input
Auto Polarity
Au to Zero cycle
200 mV F.S. range with:
• less than 2 counts instability
• ±1 count linearity
• 10 JlV resolution
(3}36!1 ±5%, 025WATT
36G±5%
0.25 WATT
rt
r
1.6Kn
C
51
A
7656
Ml'
~~.r-----+---~-------+
Nle
FAIRCHilD
VR3
(4) lN4001
I
-12V
,sj,7 16-"5 14 13 12
11 10
R.
O.OO5.uf
'Kn
~
03
O.005.uF
Sy.
~
H,
360/JH
D~,
SIL.ICmJIX
-
.022,uF
R, AS MARKED
RZ lOOKil±'"
R3 62K n
R4 47KO
RS 4.7Kn
R,6. R17 :nn,l/2WATT
C,
Cz
Cs
lj.lFPOL.YCARBQNATE
1,..F TANTALUM
CS.C7 D.l.uFCERAMIC
e,l 330jjF
C12 l000"F
9.8Kn-
es,,~2N4274
0,
_ NATIONAL ONLY
ALL RESISTORS ±5% 0 125 WATT METAL FILM UNLESS NOTED
7-60
INPUT
1200pFMICA
Siliconix
R4
lMO-
+
·PRECISION RESISTORS !1%
CONSTRUCTION HINTS
LA YOUT PRECAUTIONS
1.
The following layout precautions have been taken and
should be observed on the user's P.C. board:
A solid line between two holes represents a jumper wire.
2.
A copper dot is placed by pin one of the IC's.
3.
The dotted area denotes the power supply. If bench
power supplies are available, connect to the pads marked
+15 and -15. The positive source must supply 300 mAo
The negative source must supply 30 mAo
4.
I. VIN(+) trace is adjacent to ground only.
2. Traces from LDI20 pins 9, 13, 15 are not adjacent to
signal traces carrying AC signals.
3. UID and compo signals (LDl20 pins 4 and 5) are
separated by digital ground.
The tab of the CRI60 aligns to + mark.
5.
The LDI20 should be socket mounted.
6.
The 2N4274 voltage reference must be selected for a
reference voltage equal to or greater than 6.6 V. A
6.6 V to 6.S V zener reference may be substituted.
7.
The CRI60 current source may be replaced with a
36K n resistor. Some degradation in stability and gain
tempco may result.
8.
The display board may be directly soldered to the circuit
board, eliminating the edge connector.
9.
C3 is a mica dielectric.
C I may be mica or polycarbonate dielectric.
C2, and C6 may be mylar or polycarbonate dielectric.
CIO is tantalum dielectric.
Cll and CI2 are electrolytic dielectric.
C4, C5, C7, Cs and C9 are ceramic disc capacitors.
10. All resistors are ±5% metal film unless otherwise noted.
11. Regulators VR 1 and VR2 operate too hot to touch
"" (S5°C or IS5°F)
12. Total power dissipation is 6 watts.
4. Digital circuitry ground paths return to the transformer
(or power supply) via a different path than analog
grounds from LD120.
5. The path from V( -) input to Hi-Quality ground (pin 2)
does not carry any other currents.
6. The ground path from the reference and CSTRG (C2)
travel directly to Analog Ground (pin 7 of LD 120).
7. Int Input (LDI20, pin 9) node connections are kept
short and compact. This node has a relatively high
impedance and is therefore subject to AC line noise
pick up.
S. The +5 V supply to the LDI21A should not share a
current path with the display currents.
AC SHIELDING
Improper AC shielding will result in excessive LSD run
around. Therefore, the following precautions should be
taken:
I. Use coaxial wire for the input and range select leads to
the chassis front panel.
13. Break off steel screw tab from transformer nearest
analog input. Connect other tab to earth ground wire
from the power cord.
14. CLEAN BOARD THOROUGHLY after assembly. Any
salts, finger oil, or solder flux remaining in analog
circuitry may allow leakage currents detrimental to
high quality performance.
5. Shield the power switch leads with earth ground.
15. LED displays are intensity coded. To avoid an unattractive display, check these codes for uniformity.
The diagram below illustrates good packaging practice:
2. Enclose DVM in a metal enclosure.
3. Keep decimal point select wires separated from the
input leads.
4. Keep AC line cord enclosed in box to a minimum
and close to the chassis.
II1II
l>
........
EARTH
POWER
TRANSFORMER
b=
==[)~=e~.JO.1PF
r=
500V
o
::::I
<
ENCLOSURE
ECONDARY
THREE PRONG
c
n
POWER
CHASSIS
GROUNDED
.,
INPUT
CD
CIRCUIT
GROUND
o-+-I-i--t-- RANGE SELECT
~
CD
VI
CHASSIS
TRANSFORMER
CASING
DECIMAL PT. SELECT
Siliconix
7-61
-...c
...
.......
o
...
c-.
Q
~
LED4
LE05
c-.
LED 2
LED 1
~
~
~
m
m
Q
LED3
~
PRECISION DEMONSTRATOR
:D
0
-a
0
Z
3:
c
w
u..
,...
CI
~
...
-
J:
Q
""
moo
til
:Po
:z::
_
..,
::.t!
...J
~
Z
0
a::
0
a..
Component PI acement 0"
(Top View)
,agram
Metal Pat tern for DVM
(Bottom V",ew) Board
(refer to last page of design aid f or 1:1 P.C. pattern)
FABRICATION HINTS
All holes re ~Ulre
. a #60 drill
which
reqUIre a #54
drill.. except for the foll owmgholes
.
CAUTION"
~oard
can 'be ~he
line vol tages associ
onstrumen
atal.AC
Proper
assumes
..must be ObS/recautions for ated with this
,abilitv for
rved by th
operating thO
unsafe
user!
n~
operation~
Siliconi~
a.
b.
dc.
.
Transformer
AC inputs
Edge connector
VIN (+ and-)
~R~an~~~e~c~o~n~t,:roIPins
f. ecnnal pOint
. select
_________________________:e._
Siliconix
7-62
-----------
I
PARTS LIST
Part
Numbers
Quantity
Description
ICI
IC2
IC3
IC4
LED 1-4
LED 5
VRI
VR2
VR3
QI
Q2
Q3
CSI
HI
SI
S2
CI
C2
C3
C4
C5
C6
C7-9
CIO
Cll
I
I
I
I
4
I
I
I
I
I
I
I
I
1
1
1
I
I
I
I
I
I
3
I
I
C12
I
TI
T2
T3
I
I
I
2
2
I
I
I
2
I
3
4
2
I
I
Analog Processor IC
Digital Processor IC
Display Decoder/Driver
Seven Buffer/Driver
Seven Segment 0.43" LED Display
±I Overflow 0.43" LED Display
+5 V Voltage Regulator
+ 12 V Voltage Regulator
-12 V Voltage Regulator
NPN Transistor
PNP Transistor
N-Channel JFET
1.3 or 1.6 rnA Current Source
360 }.IH Inductor ±5%
DPDT Miniature Toggle Switch
SPST Miniature Toggle Switch
1200 pF Mica Capacitor
1 }.IF Polycarbonate Stocked Foil Cap.
400 pF Mica Capacitor
.0047 }.IF Mylar Capacitor
.047 }.IF Mylar Capacitor
.022 }.IF Mylar Capacitor
0.1 }.IF Ceramic Disc Capacitor
I.2}.1F Tantalum Cap - 10 V
330 }.IF Electrolytic Cap - 25 V
Radial Lead
1000 }.IF Electrolytic Cap - 25 V
Radial Lead
5K n Multiturn Trimpot
lOOK n Multiturn Trimpot
500 n Multiturn Trimpot
Bannana Jacks
lOOK n ±I%, I/S Watt Resistor
62K n ±5%, I/S Watt Resistor
47K n ±5%, I/S Watt Resistor
4.7K n ±5%, 1/8 Watt Resistor
IK n ±5%, 1/8 Watt Resistor
1.6K n ±5%, I/S Watt Resistor
10K n ±5%, I/S Watt Resistor
36n ±5%, 1/4 Watt Carbon Camp.
33 n ±5%, 1/2 Watt Carbon Camp.
1M n ±I%, 1/8 Watt Wire Wound
9760 n ±I%, 1/8 Walt Wire Wound
RI-2
R3
R4
R5
R6,R7
R8
R9-11
R12-I5
R16-17
RI8
RI9
-..
....
Recommended Manufacturer
and Part Number
r-
CI
Siliconix LD 120CJ
Siliconix LDI21ACJ
National DSSS57J
Fairchild 9667PC
Hewlett-Packard 50S2-7653
Hewlett-Packard 50S2-7656
Fairchild }.IA7805UC
Fairchild }.IA78LI2AWC
Fairchild}.lA 79MI2HC
National (Only) 2N4274
Motorola 2N4402
Siliconix 1211
Siliconix CR130 or CRI60
~
o
.......
rCI
h:t
-
J>
C&K 7201
C&K 7101
Siemens B32 541-1.00/5/100
Sprague 192P4729RS
Sprague 192P504739RS
Sprague 192P2239RS
-
Sprague I9SDI25X90225Hl
Mallory VTT330125
Mallory VTTIOOOM25
Spectrol 43P502
Spectrol64YI04
Spectrol64Y501
Allen Bradley
Allen Bradley
Allen Bradley
Allen Bradley
Allen Bradley
Allen Bradley
Allen Bradley
Allen Bradley
-
J>
.......
CI
n
o
:::I
<
CD
-
.,...
AC Power Supply Parts
TX I
CRI_4
-
I
4
I
24 V C.T. Transformer
Rectifier Diodes
3-Wire Power Cord w/Plug
Siliconix
CD
TRIAD F-359XP
Motorola IN4002
U1
-
7-63
Metal Pattern
Scale 1:1
A
B'
LD120/LD121A 41/2 Digit DVM
7·64
Siliconix
Component Placement Diagram
Scale 1:1
A'
A
Siliccnix
LED 5
LED 4
LED 1
LED 2
LED 3
PRECISION DEMONSTRATOR
::IJQ"tIOZ:l:
rr;c--:I:G)"T1mOC"'lCJl>
C'
C
50
250
kHz
50% Duty Cycle
78
470
Hz
fCLK ... 640
Vss
Pm14
Pm 16
V'
w'"="o.
BUfFER AMP
Pm 1
HI-Q
GNO
Pm 2
MJZ
LD122 Input
1~
T" t
LD121A Output Buffers
(Digits, Bits. Sign, M/Z UfDI
a
n
o
:I
<
CD
~~'"'
INPUT/OUTPUT SCHEMATICS
Pm 15
V,N
"F. RIN::; lOOK n
Bit Lines, Sign/OR/UR Digit Strobes
D
Y
N
V
V
VOL
VOH
200 mV Scale
0.5
VOL
VOH
Count
4.0
VOL
- 21
-
-10.8
(Note 4)
D
,14-
5
5.5
100
I10
111
1
5
2 V Scale
ppmfC
15
4.5
Zero Dnft
6
dB
5
Gam T.e.
and 3)
l----s
40
BO
TEST CONDITIONS
UNLESS NOTED OTHERWISE
V+ = 12 v; V- = VDD = -12 V.
VSs= 5 V. TA = 25'C
Pm 5
VSS
~
I--
v- Pln6
LD122 Comparator Output
~
I
V,N
J.
~~
---[>-
~.r4>t
IN
Pm3
V,N
LD121A Clock Input
Siliconix
VSS
Start Convert
J.
LD121A Comparator Input
7-67
.....
CD
UI
......c
....
...
ELECTRICAL CHARACTERISTICS (Cont'd)
C"oII
TEST CONDITIONS
Q
CHARACTERISTIC
MIN
TVP
MAX
V+
9
12
15
P
0
W
E
R
V-
-9
-12
-15
I
N
VA
U
T
rOSlonl
V+ = 12 V; V- = VDD = -12 V,
VSS = 5 V, TA = 25'C
C"oII
C"oII I23-
....Q
UNLESS NOTED OTHERWISE
UNITS
V
24
125
I26
1-
1+
3.5
1-
-3
mA
27
0
-2
mA
-3
+3
V
IGNO
I28
I-
INote71
P
29
1-
I~
I~
I~
V, Nor
On Resistance,
5.5
H i~Q Switches
kfl.
M/Z, UIO = 2.4 V
V A -+1V
VA
8.0
= -1
V
S
W
L
I
T
0
1
2
2
C
J
33
134
1-:;:I~
36
I37
I38
139
I-
Leakage Current, Switch
ILEAKAGE
2
ON or OFF
C
pA
V A = ±2.8 V
H
-100
ISOURCE
A
Z
L
I
N
E
A
B
U
F
F
R
R B
MA
ISii\ii<.
vvv
-50
Switch Resistance (on) (Note 8)
E U
F F
40
141
II-
ISOURCE
Pin 8
ISINK
Pin 8
ISOURCE
I
N
T
42
6
-400
C
0
M
P
44
-100
400
800
"A
10
V
±5
UfO' nputs
IlL
VIN (lnt.INI = 100 mV, Vo = 0 V
V
-5
M/Z,
VIH IUID INI = 2.0 V, Vo = 2 V
VIN lint. INI = -100 mV, Vo = 0 V
"A
RL=10kto+5V,AZFILTERIN=
100 mV
mV
INTEGRATOR OUT = 0 V
20
"A
VIH=2.0V
-100
MA
VIL = 0.8 V
IIH
47
VSTRG = -4 V,IOS = 30MA
VIL IUIO INI, = 0.8 V, Vo = 0 V
-10
VOFFSET
1-
kn
-800
-50
VOUT
46
VOUT = 0 V
20
(Note 9)
Output Swing
1--;j5
1-
TA = 70'C
mV
100
ISINK
43
1-
pA
50
100
ISTRG
VOFFSET
Typical values are for Design Aid Only, not guaranteed and not subject to production testing.
L0122 - CMAM-C
L0121A-IPOCVI
NOTES:
1. Bit width over which reading is stable 95% of the time.
2. System Parameters are not directly tested.
3. fCLK
= 163.84 kHz, VREF = 6.8 V.
4. All outputs disconnected.
5. Pin characteristic only during D4 strobe time.
6. Minimum positive going pulse width to initiate a conversion.
7. Maximum voltage range for VINPUT (pin 1) or hi-quality GND (pin 218. VSTRG must be more positive than -4 volts.
9. Reference Source Impedance must be less than 10K
n.
TYPICAL CHARACTERISTICS
VIN and V Hi - O GND Switches
Typical Input Leakage vs Temp and VA
Input Leakage Test Set-up
Typical rOS(on) vs V A and Temp
+12V
10K
9.
10K
~
~
V+"+12V
v---uv
"K
~ 12K
V --12V
~\
_
'"
,.
~
10"
==
5V
L
H;~Dk
L
GND
+ ':"
ov
O,A
V
'\'
~ ~ 17 .5V
:§:
25"C
0"
ov
+1V+2V+3V+4V+5V
VA - VOLTAGE PIN 15 (VIN) OR PIN 2IHI·Q GNO)
7-68
F=
O.l PA IT
W
20°
-12V
Y~-
VIN 15
VA~I
~
~:-....
-5V .... v-:JV-2V_1V
..
10pA
l
I~~
81<
OK
~;y
100pA
V+-+12V
30'
40°
50"
50"
10'
T - TEMPERATURE lOCI
WITH RESPECT TO ANALOG GND PIN 7
Siliconix
80'
J
7
-bAnalOg
Picoampme~r GNO
VA
1,
4
3
J
~WD~,MIZ
OV
OV
10
BUFF IN
cui try to reduce stray R F and hum pickup. Having the OP·
07 included in the Auto-zero loop cancels front end amplifier bias·offsets. and more important drift with temperature.
Reference drift is reduced by using an LM399 precision
voltage reference with built in heater.
Figure 1 shows the arrangement for a 20 mV full scale. 1 J..IV
resolution DVM. The OP·07 provides the necessary low
noise operation to achieve stable 1 J..IV readouts. Proper
layout is necessary for the LD122 and OP·07 front end cir·
CIRCUIT BENEFITS
•
•
•
•
1 J..IV Resolution
Overrange Blinking
0-> 19.999 mV Input Voltages
Zero Adjust to Null Offset Introduced by PC Board
Leakages and Comparator
~
fz
~ ~ 3an .5%. 0.25 WATT
6
~7lB
HEWLETT·PACKARDDISPlAYS
~
+I.I - l.lE
I -if-
~
41
~
_
gl '0 l"l
~
~~
_
~
14
I. :::
~
:
D,"57J
NATIONAL
m
~
14
14
~!~+=:::;-l
r!L-
h
15-4-
------------------L-NC
~-i===--
:L
f-
114
~
pt
1_7.
~
_
-7t:
~ 1_
f-
-I
_ I. t=
~~ ~~ ~~ ':'::~~LD.4~
~~
_____________________
0
I
~---Jl
12V
RT"" 13 Kr2;TRIM UNTIL
fCLK·163.840Hz
I:'RTERS
CD4049
.A
·ZERO ADJUST AC COUPLES SMALL
AMOUNTS Of POSITIVE OR NEGATIVE
CHARGE ONTO THE STORAGE CAPACITOR
FROM THE M/Z SIGNAL
.lc[
AS MARKED
C,
100Kn±1%
Cz
62K n
47K n
4.7Kn
4.7 Kll
470K
1 Kn
7sn.l/1WATT
2"F, TANTALUM
1 "F. TANTALUM
1200 pF MICA
l.o,uFPOLYCARBONATE
r;;;--1a
i~tE
200 pF
lOOK
1,1,.
~
5
4
3
1lf
2
B
n
1
A5
6.95 V
r
1
Aa
I
Ag·....l.!
~
-:!F3
I
LM399
Voltage
31
+12Vo-4""",,,,,...,~3
.~
..A
~D122PIn'O
,*C4
l1li
Aa
A,
=::0.01"
~
......
INPUT
OP·07
pO 11 12 13 14 15 16
f-l
C,
GNO-::!:-_
I
F
p
AT
+_
LDl22
1%
ALL RESISTORS :tS" 0.125 WATT
METAL FILM UNLESS NOTED
CATALOG.
L---t1 ~
~~~~
:.....--~9
CRXXX ARE CURRENT REGULATOR
DIODES,SEE SILICONIX FET DESIGN'
I
+5 V o-.--+.Z..
EA"'O".H.........;,M~
10K n
R,
R2
R3
R4
RS
RS
R7
RS
R9
C3
C4
-l-,oo
=r
l00Kn
>--
f-iiI-
Z
eo
0
•
eo
V+ +12 t3V
I
BUFFER
r-
BUFF OUT:
CD:
I
®
I
I
.2
L~~!!.!.U!."~~.!.N~~~J
INT IN
COMP
~
~
®
AlZ
.......
r-
....
BUFFER
INTOUT
a
.3
~
-
••
MIl
J>
UfD
Analog Processor Expansion Diagram
Figure 2
Since the LDI22/LDI21A converter is essentially a
L0120/L0121A system suitably modified (in Figure 2) and
numerous dissertations on the quantized feedback technique can be found in the Siliconix LSI Data Book,
discussion of basic converter operation will be foregone in
favor of specific precautions, guidelines and applications to
follow when doing very low voltage measurements. For
those desiring basic operational information I refer you to
the L0120/LDI21A data sheet" and application note
AN77-I.
Applications Tailor Made for the L0122/L0121A include:
Microvolt Digital Volt Meters
Thermocouple Temperature Measurement Systems
~-
High Precision strain gauge measurement systems
Scientific Instrumentation and others
L0122-L0120 Similarities
APPLICA TlONS INFORMATION
Probably the best way to think of the LD 122 is as if it were
an LDI20 with the VIN input amplified. So anywhere you
see an expression for the differential LDI20 input
(VIN-VHl-Q) substitute X(VIN-VHI-Q) where X is the gain
of the user supplied input buffer. Doing so, our A/D output
count relation becomes:
Features and Applications
With its long list of high performance features:
Wide choice of input voltage ranges
High resolution
4~
digit operation
Output Count =
0.005% ± 1 count accuracy
Highly linear operation with simultaneous unknownreference integration
Auto Polarity operation with only I external reference
Fully buffered inputs
TTL output drive
Automatic Zeroing cycle
X(YIWV HI _Q)
RI
VREF
R2
J>
.......
a
- 65,536
Now in addition to being able to scale the converter for
different input ranges by changing the RI/R2 ratio, we can
also alter the input buffer gain =X.
Figure 3 shows a typical application of the LDI22/LDI2IA
chip set. The system is set up to indicate full scale if 2V
(100 IN/LSB) is applied to R2 by the input gain buffer.
However the input gain X is 100 so that a 20mV
(1IlV/LSB) signal applied to the input buffer results in a
fullscale reading. If the input gain were only 10, then a
200mV (lOIlV/LSB) signal would be necessary to cause a
full scale reading.
Siliconix
l1li
7-71
n
o
:I
<
CD
.,...
.,CD
fit
-...
CC
...
c-4
..........
Q
...
...c-4
c-4
Differential Measurements
Using the differential input capability of the LDl2X AID
series, ratio metric type measurements as typically found in
bridge circuits can easily be accomplished. Consider for
example the following bridge configuration, Figure 4 ,
typical of strain gauge systems .
Q
where Output Count
co
o
CO
Z
CC
XCV A- VB)
= _--'00--=='VREF
v
TOVIN
LD122
Rl
, - , 65,536
R2
I
X('!...
VREF
) (_R,,-,14,--_
R13
'-----+------~TO HI QUALITY
GND LD122
Rl
(R2) , 65,536
+ R14
Figure 4
Using appropriate input amplifier gain, very minute bridge
changes can be measured.
Figure 3 shows the arrangement for a 20 mV full scale, 1
jJ.V resolution DVM. The OP-07 provides the necessary low
noise operation to achieve stable I jJ.V readouts. Proper
layout is necessary for the LDI22 and OP-07 front end
circuitry to reduce stray RF and hum pickup. Having the
OP-OJ induded in the Auto-zero loop cancels front end
amplifier bias-offsets, and more important drift with
temperature.
CIRCUIT BENEFITS
•
•
•
•
1jJ.V Resolution
Overrange Blinking
0 ..... 19.999 Input Voltages
Zero Adjust to Null Offset Introduced by PC Board
Leakages and Comparator
·ZERO ADJUST AC COUPLES SMALL
AMOUNTS OF POSITIVE OR NEGATIVE
CHARGE ONTO THE STORAGE CAPACITOR
FROM THE M/Z SIGNAL
R,
R2
R3
R4
ASMARKED
looK!]!1"
62Kn
47Kn
C,
1200pFMICA
Cz 1.0pFPOlYCARBONATE
RS 4.7K n
R6 4.7 KG
R, .70K
ALL RESISTORS :t5% 0.125 WATT
METAL FILM UNLESS NOTED
CRXXX ARE CURRENT REGULATOR
'--.w~-+--...JVBUfnAED
DIODES,SEE SILICONIX FET DESIGN
CATALOG.
Figure 3
7-72
Siliconix
SCAUDT02V
fOA2!lmV
FULL SCALE INPUT
Input Gain Buffers
Figure 5 shows the arrangement for a 20 mV full-scale front
end. If an extremely low source impedance were used, such
as thermocouple, then an amplifier such as the LM20lA
could be used for AI' For higher impedances, lower bias
currents are required until at about lK n or above, a JFET
amplifier will be required. Note that MOS input op-amps
are not quiet enough.
Even the BI-FET op-amps are only good for a 20K n input
resistance up to 75°C. The circuit of Figure 6 has an input
leakage of only 2 pA typical at 75°C and would be usable
with 1M n input resistance. Although not covered here,
there are ways to reduce leakage effects over temperature
by a factor approaching 10.
J>
Z
o
•
•
•
VREF 1=6.8VI
PART OF
LD122
,~~
r___
10
12
R,
M/Z
HI_-O_G_N_O_-<>-+-,
UfO
LD122
O<:HI--
1
TO LD121A
11
47K
COMP
14
20 mV F.S. Meter (Front End)
Figure 5
470n
r - -....-------t--'VI/'Ir-012V
100K
2%
lOOK
2%
R1
8 REF OUT
R2
91NTIN
OUTPUT IX 1001
PART OF
LD122
V 1N
15
R3
12 AZ OUT
r----..
lOOK 2%
CINT
11 INTOUT
1 BUFF IN
GUARD
2
1K2%
J>
.......
a
30 pF
R4
HI-QGND
l1li
14AZIN
n
0
:::I
470n.
L------_~---'VI/'Ir-o_12V
LD122
..
<
CD
CD
M/Z
VI
Ultra-Law-Leakage Preamp
Figure 6
Siliconix
7-73
.."..
...
""..
...
~ r-------------------------------------------------------------------------------------~
C
a
......
a
co
e•
co
Input Buffer Selection Considerations
Ideally we would like the user supplied input buffer to have
constant gain over the entire input voltage range so that the
converter's linearity and accuracy can be preserved .
Unfortunately real life op-amp characteristics, principally
common mode voltage, prohibit such an ideal situation and
must be reckoned with when choosing an op-amp.
Consider first of all the following unity gain voltage
follower configuration in Figure 7.
If we now use a buffer with a gain of 100 as diagrammed in
Figure 9, a full scale input (20 mY) to the buffer will result
in a 2 volt output signal. Since we would like to resolve to I
part in 20,000 (1 /lV input, 100 /lV output) the output
I
CMRR error must be less than - - . 2V (Le. for ± I
20,000
count operation CMRR better than 86 dB over the input
voltage range) or 100 /lV over the entire voltage range. If
noise is significant, (thermal, junction, etc.) the sum of
CMRR error and noise must be less than
Z
C
ov
+0
9>-.+--1!_
0+
J
I_ X output
L20,000
buffer voltagj for ± 1 count resolution.
ov
± VOFFSET
II~
"1
Figure 7
+
1+ / '
o---------.V
-1
~With an ideal op-amp, inputting OV should give us a OV
output. With a real amplifier though, there is a small error
offset VOFFSET present as shown. Assuming that this
offset is constant over the entire input voltage range, it is
easily taken care of by the LD122 in the Auto-Zero interval where such error offsets are easily corrected for.
Suppose that we now input a 20 mV signal to our unity
buffer. See Figure 8.
• _,
r._
.~_..l-----
Z
C»
o
•
-..
C»
r-
C
~
~
.......
r-
....
C
~
-
l>
In addition, since we are talking about gain setting
resistances, they should track each other over the
operational temperature range lest a gain error result.
When a user supplied input buffer of appreciable gain is
used, the burden of quality becomes shifted to the input
buffer components since any noise there is appreciably
magnified, while R2 now faces a large input signal in
relation to its possible noise contribution. The gain setting
resistors must therefore be of appropriate quality. In either
case, resistor quality should be appropriate to its relative
noise contribution.
The integrator capacitor CINT should be mylar or better
quality. The autozero capacitor CSTRG should be mylar,
polystyrene, polycarbonate, or polyproplene, the latter
being best with regards to dielectric absorption. Resistors
R3, R4, RS quality is not critical, but should be long term
stable. Above all, capacitive losses (leakage, dielectric
absorption, etc.) must be kept to a minimum for proper
operation as Appendix A explains.
l1li
l>
.......
c
n
o
::I
<
CD
.
~
CD
Ul
Siliconix
7·75
....
...
.....
~ r-----------------------------------------------------------------------~
cC
APPENDICES
C"I4
APPENDIX A:
ERROR TERMS
Q
......
C"I4
C"I4
Q
co
o•
CO
Z
cC
Zero Drift - The main source of zero drift is leakage from
the input and auto zero buffers. Figure 12 shows typical
input and auto zero leakages over temperature. The error
component due to liN is simply
For a 1M n input resistance, and dllN =30 pA at 75°C,
dVIN = 30 /lV, corresponding to a 0.3 bit offset at 2 V
full-scale, and 3 count offset at 200 mV full-scale. This
offset can be reduced by reducing RSOURCE or by
inserting a compensating RSOURCE between VHI_Q and
ground.
"
The drift due to I AZ is independent of scale factor, and is
caused by the voltage on CAZ drifting during the measure
interval. The magnitude of drift will be
dV AZ
IAZ
=
32,768
CAZ • fOSC
This will cause an effective input current to the integrator
of dVAZ/2R3' the factor two resulting from the fact that
the ramp of auto-zero drift is averaged by the algOrithm.
This input current due to drift is analogous to an input
signal of dVAZ R2/2R3' so the count drift is
• 2.15 X 109
So given dlAZ = 100 pA when up at 70°C, Rl =60K =R3,
CAZ = 0.1 /IF, fOSC = 150KHz, and VREF = 6.2 V,
dCount = 1.16 due to dlAZ only .
The drift caused by thermocouple junctions orithe LD120
is much less than that caused by leakages.
.
Gain Drift - Full-scale gain drift is caused mainly by
changes in VREF' One count in 20,000 stability per degree
C is 50 ppmtC, so the zener reference should have at least
10 ppmtC stability and the system burne"d-in, to reduce
long term drift.
The resistors at R2 and R 1 should track each other over
temperature at least as well as the tempco of the reference.
APPENDIXB
Grounding - The optimum ground scheme is shown in
Figure 13.
The main considerations are: analog ground is common to
VREF, CAZ, ±12 V commons, ±12 V bypass, ground of the
signal source, common power ground, case ground;
isolation of currents in the 5 V circuits from those of
analog grounds; a 3-wire input connection for remote Signal
sources.
These connection methods will alleviate AC and DC pickup
in signal inputs and integrator positive input (analog
ground) from noise currents caused by the display and AC
environment.
-12 V
'2V
r--f--1
COMMON GND
I tt
SIGNAL
SOURCE
f-
1
,.
-liN. Vs
25
35
45
!15V
TEMPERATURE
65
75
HI·a
v
VRE>
85
(~CI
Typical Leakage Over Temperature
Figure 12
7-76
LD122
V
:
!12V
55
V'N
V-
1--I
:~
/
I~IN'VS"
V+
ANALOG
AZ
GNO
1
/': [7
. /[7
1
1
t--i-......__-... I I
:12 V
1
I
1
~ IAZ. Vs.
5V
-n
~r-
I
100
D~LV
ANAlOG.SUPPlIES
,
L ___
I
1
5V
1
1
LD121A
I
I
DISPLAY
1
1
I
~E.!;E6J
LD120/LD121A Ground System
Figure 13
Siliconix
ANO
DRIVERS
GNO
1
~V-
+
1
~
l>
Z
APPENDIX C: TROUBLESHOOTING
Problem
Jittery Display
00
C
Causes
I
-...
00
fOSC is not stable (short-term)
rCJ
AC voltage on VIN. VHI-Q. power supplies. or VREF
AC fields passing through unshielded circuit board
....:t
....:t
Rl. R2. or R3 being carbon composition type
........
Excessively small full-scale sensitivity implemented
Offset Drift
V Al or VREF too small
rCJ
Insufficient power supply bypass capacitor
....:t
...
...l>
-
Excessive input resistance or CAl too small (see appendix A)
Circuit board leakages excessive due to flux or moisture absorption
A variable offset in grounding system
Poor quality capacitors for CINT or CAl
Sample rate too slow{<1 sec)
Thermocouple junctions in the 200 mV range
Poor Linearity
Poor quality CINT
V+ or V- less than 10 V
Circuit board leakages to CINT
Noise pickup on UjD or loading of UjD
VREF modulated by display ground currents
No digit strobes from LDI21A
Clock not functioning
Some terminal of the LDI21A more positive than VSS
l1li
l>
........
CJ
n
o
~
<
CD
.
~
CD
;:
Siliconix
7-77
H
Siliconix
D/A Converters _
Index
D/A CONVERTERS
Title
Page
DG515/DG516 ................................................................................. 8-1
Stresses listed under "Absolute Maximum Ratings" may be applied (one at a time) to devices without resulting in
permanent damage. This is a stress rating only and not subject to production testing. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.
D/A Converter Switches
c
H
Q
...
VI
Siliconix
designed for . . .
BENEFITS
• 4, 10 or 14 Bit DACs
•
Easily Interfaced
o Binary Weighting of ON Resistances
Q
• Binary or BCD DACs
• Multiplying DACs
• Successive Approximation ADC
•
Minimizes System Power Requirements
o 40 pW Operating Power
a-
•
Reduces Systems Costs
o Single Supply Operation
VI
c
...
VI
• Frequency Synthesizers
• Virtual Ground Switches
DESCRIPTION
The DG515 and OG516, 4 and 10 bit SPOT switches, combine NMOS analog switches with CMOS switch drivers. These
switches feature low channel ON resistance, binary weighting of ON resistance and channel resistance matching to minimize
the errors that can lead to non·monotonicity in O/A converters. The binary ON resistance weighting (doubling for each bit)
is continued from the OG515 to the OG516 to allow the pairto be used as a 14 bit OAC.
PIN CONFIGURATIONS/BONDING DIAGRAMS
Dual In-Line Package
1_ _ _ _ _ 0.070
I
(178)
SUBSTRATE·'
Dual In-Line Package
0',0
I"
"I
(279)
[!]
s,
o0
00
000
S:z
ANALOG
S3 ANALOG 54
GM,
G.. d2
v-
SUMJCT
v'
B,
B,
B,
E!I B
@]
GJ
84
@]
Ss
s,
s.
s,
s,
s,
s,
Sg
G'"
s,
0510
B,
B,
[!JB10
s"
E!I"
B,
B,
B,
B.
[illBa
@lB7
BS
ORDER NUMBERS:
DG516AR
DG516BR
SEE PACKAGE 13
DG516CJ
SEE PACKAGE 14
• CONTACT FACTORY FOR TESTING AND INSPECTION CRITERIA
•• SHOULD BE LEFT UNCONNECTED OR CAN BE TIED TO V+
ORDER NUMBERS:
DG515AP
DG515BP
SEE PACKAGE 11
DG515CJ
SEE PACKAGE 7
56
Ss
S~2~
A~r!d0Ge!J
Sl~
1
0082
BB
1
$1
[!]v-
v-
B"
B,
''''
iii/50!
Sa
ANALOG
S,
1
El El 0 0 §] @l §Is,
• ORDER NUMBERS:
DG515ADICE
DG515BDICE
DG515CDICE
SUMJCT@l
v+[TII
B:'~B
El @ E!I E!l E!I 2
Bt Bs
Bot
(208(
1
• ORDER NUMBERS:
DG516ADICE
DG516BDICE
DG516CDICE
-
FUNCTIONAL DIAGRAMS
DG515
V+
C
......
DG516
8,
V+
s.
s,
~
Sg
n
o
::I
<
CD
'-+-+.....++....,H-4+-o SUM JeT '
...
CD
~
L......t-......+-11-=-o ~~t.LOG
L-+-_-+---f---l~+-oANALOG
Gndl
U1
14
v-
10
B1
11
·2
'2
'3
84
v-
8,
83
84
86
8,
Bg
8'0
SWITCH STATES ARE FOR LOGIC "1" INPUT
Siliconix
8-1
...
00
ABSOLUTE MAXIMUM RATINGS
1ft
"...
"
CI
1ft
1ft
CI
Vs to Sum Jet or Analog Gnd
VIN (Bit Logic Input)t .
ISWITCH
Current (Any Terminal Except Switch)
Storage Temperature (A & B Suffix~
(C Suffix)
Operating Temperature
(A Suffix)
(B Suffix)
(C Suffix)
Power Dissipation (Package) *
14 Pin Ceramic DIP**
14 Pin Plastic DIP"*
'. -200 mV
28 Pin Ceramic DIP'**'
1200mW
28 Pin Plastic DIP**'*'
625mW
* Device mounted with all leads welded or soldered
to PC board
**Derate 11 mWfC above 70°C
'**Derate 6.3 mWfC above 25°C
'***Derate 10 mWfC above 25°C
**'**Derate 8.3 mWfC above 25°C
tNOTE: Exceeding these voltage limits can result in a latch·
up condition, excessive 1+ and possible destruction to
the device. Placing a 2K n resistor in series with V+ will
protect the device and allow recovery (without power sup·
ply cycling) after the overvoltage is removed.
.V-~VIN~V+
10mA
30mA
-65 to 150°C
-65 to 125°C
-55 to 125°C
-20 to 85°C
o to 70°C
825mW
470mW
ELECTRICAL CHARACTERISTICS
Aii DC parameters are 100% tested at 25°C. Lots are sample tested for AC parameters to assure conformance with specifi·
cations. DICE are sorted by DC parameter tests and visual inspections.
DG515
Characteristic
Typt -55"c
@25"C To
DG515 MAX LIMITS
DG515C
DG515A/B
125"C
7(f'C
o°c
25°C
25"C
To
-zO"e
1----2.
2
1-,
1---.
1----. s
l----i
1----7
I~
1----.
1-;0
8SoC
rOSlon)
Switch 1
6.25
6.25
9.0
78
7.B
112
rOSlon)
SWitch 2
12.5
12.5
lBO
156
15.6
22.5
rOSlon)
Switch 3
25.0
25.0
36.0
312
31.2
45.0
SO.O
50.0
72.0
62.5
62.5
90.0
OG516
DG516 MAX LIMITS
DG516A/B
DG516C
12s<'C
2SoC
O'C
70°C
To
200 e
85°C
Typt 1-"5'C
2SoC
To
@l2SoC
rOSlon)
SWitch 4
SWitch 1
100
144
125
125
lBO
SWitch 2
'200
200
28B
250
250
360
SWitch 3
400
400
576
500
500
120
SWitch 4
BOO
BOO
1150
1000
1000
1440
rOSlon)
SWitch 5
1600
1600
2300
2000
2000
2880
rOSlon}
SWltc::h6-10
3200
3200
4600
4000
4000
5760
4rOStonl
SWItc::h to ANLG GND
SWltc::h to SUM JCT
100
40
2000
100
40
2000
11
100
12
lOIoffl
100
20··
20'"
40
100
40
n
%
VINH = B.OV, V'NL = OV
nA
VANALOGGnd-OV,
VS=-l00mV
'ANALOG Gnd (off!
2000
100
IOloffl
nA
2000
40
100
40
15
116
1---;'7
IIii
119
I
N
p
U
T
26
VSUMMING Jet = 0 V,
Vs '" +20 mV
Turn.QN Time
120
180
120
IBO
toft
Turn-OFF Time
170
250
170
250
CD
Output Capacitance
ANLGGND
60
20
CD
Output CapaCitance
SUMJCT
40
14
CD
Output Capacitance
ANLG GND
40
14
CD
Output CapaCitance
SUMJCT
60
20
1+
Positive Supply
Current
1-
Negative Supply
Current
~ow
1+
PoSitIVe Supply
Current
1-
Negative Supply
Current
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
+1.0
+1.0
+1.0
+1.0
+1.0
+1.
+1.0
+1.0
+1.0
+1,0
+1.0
+1.0
VINL"
av
.A
5.0
5.0
150
5.0
5.0
150
50
5.0
150
50
5.0
150
-5.0
-5.0
-150
-5.0
-5.0
-150
-5.0
-5.0
-ISO
-5.0
-5.0
-150
VINH = S.O V
n,
See SWitching Time Test
ClfCUlt
of
VINL = 0 V
of
VINH=80V f=lMHz
f= 1 MHz
VINH =8.0V
.A
5.0
5.0
150
5.0
5.0
ISO
50
5.0
150
5.0
5.0
150
-5 .•
-5.0
-ISO
-5,0
-50
-150
-5.0
-5.0
-ISO
-5.0
-5.0
-150
VINL = OV
NOTES:
t TYPIcal values are for DeSign AId only, not guaranteed and not subject to production testing
• Delta rOSlon) as percent of maximum reustance.
--ThiS IS the worst tYPIcal mismatch seen on a device.
8-2
V
ton
1-
2000
40
Input Current
Input Voltagv High
125
4.0
IINH
124
40
Input Current
Input Voltage
123
100
IINL
122
2000
Threshold
121
40
2000
V,N
120
100
VANALOGGnd-OV,
Vs = -20mV
VSUMMING Jc::t = 0 V,
VS=+100mV
ISUMMING
Junction (off)
2000
1---;:;I-
IS= 10mA
IS=0.1 rnA
113·
Test Conditions
v+-a.ov,v-"OV
IS= lOrnA
rOSlon)
W
1 rOSlon)
T
C ros on
H 'OSlon)
I~
Unit
Siliconix
DG51S-ICAS
DG516·ICAT
TYPICAL CHARACTERISTICS
RDS(on) vs Temperature
Leakage vs Temperature
RDS(on) vs Supply Voltage
~
~
J:
J:
ew
ew
vs-ov
V+= BV
Z
~
Hia:
100
z
o
~
iiia:
SWITCH 1 OG516
r-... dG51~ IS~ITC~ 11
100
z
0
w
w
i;1
g
z
:;:
10
DG51~ 13
"::>a:
I
Sl
"-
10
z
SWITCH 1 OG515
:;:
I I I I
DG515 (SWITCH
11
/
"eI
.g
1
~
-55
"
I
I
65
in
a:
105
"
a:
T - TEMPERATURE (OCI
~
II
0
25
-15
~
1
E
10
65
85
125
105
Typical Channel (DG515 or DG516)
100
V+
45
T - TEMPERATURE (OCI
Quiescent Supply Current
vs Temperature
Supply Current vs Toggling Rate
0.0 1
25
(V+ TO V-I - VOLTS
"
DG516J ~
a:
a:
!
~
a:
200 mV
Vo (SUM JeT)
"
"
v+
BV
1
lK
1/
OG515
0
::>
1/II
"
~
.,
OG516-
it
iil
1/
/
I
+
o. 1
-55
1/ ./
-15
+-
I
V
25
65
105
ANALOG
Gnd
T - TEMPERATURE (OC)
f - FREOUENCY (Hz)
Switching Time Test Circuit
&
-
Switching Test Waveforms
v
RD
__
CD
Sn
DG515or
OG516
ANALOG
Gnd
J:
30PF
@ SUMMING JeT
Your
SWITCH
AD (ohmsl
DG515 DG516
1
50
300
2
100
300
3
200
300
4
200
510
LOGIC
ell
........
INPUT
ov
J>
VOUT
(POSITION 2)
5
510
6
1000
7
1000
8
1000
9
1000
Your
10
1000
(pOSITION 1)
n
o
~
..
<
CD
~
CD
til
Siliconix
8-3
APPLICATIONS
4 Bit Multiplying Current Switch D/A
The following Application Circuits are intended to illustrate the following points:
'V+
1. A 2K n resistor should be in series with
V+ to limit supply current with negative
ringing of the bit inputs.
10Kn
20Kn
40Kfl:
2K
2. Temperature compensation for RDS(on)
can be provided in the feedback path of
the Op-Amp.
BOKU
5K
OG515
3. 4 Quadrant multiplication is possible by
using the Analog Gnd current.
4. Bipolar reference voltages can be used in
all configurations.
5. Resistor weighting other than Binary can
be used.
TYPICAL FEEDTHROUGH ERROR
OF 2 mV pop FOR VREF • 10 V pop
AND f "100 MHz
Figure 1
10 Bit DJ A Converter
V+
2"
2"
2K
21
23
25
2"
2"
26
2"
2"
2"
2"
2"
2"
2"
2.
27
"-
OG516
.,
2.
(MSB)
19
·2
17
·3
"4
.
14
15
"
"6
BINARY INPUT
"TYPICALLY 25K n
··TEMPERATURE COMPENSATION
"1.
(LSBI
FOR CHANGE IN ROS(on)
WITH TEMPERATURE
TYPICAL FEEDTHROUGH ERROR
OF 10 mV p-p FOR YoftEF = 10 V pop,
f= 100kHz AND R = 25Kn
Figure 2
Unipolar Binary Operation
DIGITAL INPUT
ANALOG OUTPUT
111111111 1
-VREF (1 _2'",01
1000000001
-VREF (112 + 2- 101
1 000000000
-VREF/2
o1
-VREF (1/2 - 2'"'01
1 1 1 1 1 1 1 1
0000000001
-VREF (2- 101
0000000000
0
Figure 3
NOTE:
Op-Amp characteristics effect D/A accuracy and settling time. The following Op-Amps. listed in order of increasing speed, are
suggested:
1.
8-4
LM101A
2. LF156A
3. LMl18
Siliconix
c
APPLICATIONS (Cont'd)
Q
...VI
'"
10 Bit, 4 Quadrant Multiplying DAC
(Offset Binary Coding)
c
Q
2R
2R
2R
2R
2.
25
2R
2R
2R
2R
2R
Bipolar (Offset Binary)* Operation
I 1 1 1 1 1 1 1 1 1
-VREF 11 - 2-9 ,
1000000001
-VREF IT9,
1000000000
0
o1
V REF 12-9 ,
DIGITAL INPUT
V REF 11 - 2-9 ,
0000000001
0000000000
'"00...
10M 12
Unipolar Binary Operation
ANALOG OUTPUT
1 1 1 1 1 1 1 1
2R
2.
27
OIGITAL INPUT
2R
V REF
ANALOG OUTPUT
111 11111111 111
-VREF 11 _2- 14,
10000000000001
-VREF 11/2 + 2- 14,
1 0000000000000
-VREF/2
o
-VREF 11/2 _2- 14,
1 1 1 1 1 1 1 1 1 1 1 1 1
00000000000001
-VREF 12- '4 ,
00000000000000
0
NOTE: 1 LSB '" 2-9 V REF
·Complementing 8 1 (MSBI will give 2"5 complement codmg.
Figure 6
14 Bit Binary DAC (unipolar)
2R
21
23
2R
2R
25
2.
2R
27
2R
2R
2R
2R
2R
2R
-
2R
2.
c
.......
J>
DG516
•1 1~f]1r' HI 1.
I i
I
1
•
12
n
3
i
11
22
13
84
o
24
~
U·
.
<
CD
"TVPICALL y 25K n
20
B5
19
17
16
BB
B6
BINARY INPUT
15
B9
14
13
B11
11
B'2
~
10
B13
CD
8,4
~
Figure 7
NOTE:
A.Op-Amp characteristics effect D/A accuracy and settling time. The following Op-Amps, listed in order of increasing speed, are
suggested:
1. LM101A
2. LF156A
3. LMl18
Siliconix
8-5
1ft
H
Siliconix
Die Process & Topography __
I
Index
DIE PROCESS AND TOPOGRAPHY INFORMATION
Title
Page
Die Process Information ......................................................................... 9-1
Die Ordering Information ........................................................................ 9-4
Die Topography Information (Monolithic) ......................................................... 9-6
Die Topography Information (Multichip) .......................................................... 9-44
Title
Page
DF412 ................................... 9-7
DG172 ................................... 9-7
DG200 ................................... 9-8
DG200A .................................. 9-8
DG201 ................................... 9-9
DG201A .................................. 9-9
DG202 ................................... 9-10
DG211 ................................... 9-10
DG212 .....................•............. 9-11
DG243 ................................... 9-11
DG300 ................................... 9-12
DG300A .................................. 9-12
DG301 •.................................. 9-13
DG301A .................................. 9-13
DG302 ................................... 9-14
DG302A .................................. 9-14
DG303 ................................... 9-15
DG303A .................................. 9-15
DG304 ................................... 9-16
DG304A .................................. 9-16
DG305 ................................... 9-17
DG305A .................................. 9-17
DG306 ................................... 9-18
DG306A .................................. 9-18
DG307 ................................... 9-19
DG307A .................................. 9-19
DG308 ................................... 9-20
DG309 ................................... 9-20
DG381 ................................... 9-21
DG381A .................................. 9-21
DG384 ................................... 9-22
DG384A .................................. 9-22
DG387 ................................... 9-23
DG387A .................................. 9-23
DG390 ................................... 9-24
DG390A .................................. 9-24
DG501 ................................... 9-25
Title
Page
DG503 ................................... 9-25
DG5040 .................................. 9-26
DG5041 .................................. 9-26
DG5042 .................................. 9-27
DG5043 .................................. 9-27
DG5044 .................................. 9-28
DG5045 ................................... 9-28
DG506 ................................... 9-29
DG506A .................................. 9-30
DG507 ................................... 9-31
DG507A .................................. 9-32
DG508 ................................... 9-33
DG508A .................................. 9-33
DG509 ................................... 9-34
DG509A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-34
DG515 ................................... 9-35
DG516 ................................... 9-35
D123 ..................................... 9-36
D125 ..................................... 9-36
D129 ..................................... 9-37
D139 ..................................... 9-37
D169 ..................................... 9-38
G115 ..................................... 9-38
G116 ..................................... 9-38
G117 ...................................... 9-38
G118 ..................................... 9-38
G119 ...............•..................... 9-39
G122 ..................................... 9-39
G123 ..................................... 9-39
G124 ..................................... 9-38
LD110 .................................... 9-40
LD111A ................................... 9-41
LD120 .................................... 9-41
LD121A ................................... 9-42
LD122 .................................... 9-43
L144 ...................................... 9-43
L161 ...................................... 9-43
a--
H
Siliconix
CD
."
.
"
-...
o
CD
III
III
~
..3
Die Process Information
o
Siliconix is a large-volume supplier of die to the hybrid industry. Both military and industrial grades are available. Screening includes 100% DC electrical probe and 100% visual inspection of each die.
...--
II
o
~
PHYSICAL DATA
Physical layout and dimensions are presented in the Die Topography section. Die are supplied to length and width dimensions
which have an accuracy of ± 0.003 inches. Thickness will be 0.015 inches ( ± 0.(01) for integrated circuit die and 0.008 inches
( ±0.(02) for FETs.
Bonding pad location may be identified from the die topography shown. Contact factory for ordering information.
Each die or wafer is passivated with approximately 8,000 angstroms of non-crystalline glass.
FET chips are supplied with gold backing; gold backing is available as an option for integrated circuits.
Die metallization is deposited aluminum approximately 12,000 angstroms thick.
DIE SCREENING CRITERIA
Electrical Probe - All dice are 100% probed in wafer form at 25°C to DC criteria designed to support "A" suffix DC parameters.
An optional screen to "c" suffix limits is available.
Visual Criteria - All die receives a visual inspection to MIL-STD-883, Method 2010, Condition B criteria. Siliconix QC Department samples each lot to an LTPD of 10%. Alternate visual criteria, including Method 2010, Condition A, or Siliconix Industrial
criteria are available as options.
PACKAGING
Die are supplied in dust-proof, anti-static waffle packs (see illustration).
l1li
ASSEMBLY
The customer's interests will best be served if static sensitivity handling procedures are used.
PART NUMBER DESIGNATIONS
See ordering information.
Siliconix
9-1
c
o
--...
D
....
E
o
-c
VI
VI
G)
.
U
o
D.
--Q
G)
Options
(Price will be quoted upon request.)
SEM - Scanning electron microscope examination and control in accordance with MIL-STD-883 Method 2018 can be
ordered on die and wafers. SEM, wafer qualification should be specified as a separate line item on a request for quote.
Wafer Qualification to Unprobed Parameters
Wafer Qualification to Unprobed Parameters - Sample testing of purchased die to demonstrate capability to perform at
data sheet temperature extremes or to switching time test limits by use of LTPD techniques can be provided at additional
cost.
Alternate Electrical Probe - A 100% DC electrical probe to support "C" Suffix 25°C electrical specs is available for mono-
lithic parts only. ("IDICE" ordering information.)
Visual inspection to customer generated specifications can be provided.
Alternate Electrical Probe - A 100% DC electrical probe to support "C" Suffix 25° electrical specs is available for mono-
lithic parts only ("DICE" ordering information.)
Gold Backing - Die may be purchased with gold alloyed to the backside. This is a special order item. Gold thickness would
be as follows:
•
•
FETs (NC, NH, NIP)
IC's (all)
750A min
3500A min
Hot Probe - Siliconix has chip processing distributors with hot probe capability available.
9-2
Siliconix
a--
Chip and Wafer Processing
CD
-a
o
- - - - - -I
I
~
CHIPS
WAFER
------PROCESSING
VISUAL
INSPECTION
L
100%
ELECTRICAL
PROBE
~ac
ELECTRICAL
MONITOR
~
GOLOBACK
(OPTIONAL)
I
I
I
I
~
I
I
I
~
I
ac
I
I
~
I
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I --- -SAW
AND
FRACTURE
100%
VISUAL
INSPECTION
(VISUAL)
CARRIER
LOADING
I
I
I
I
I
I
I
I
I
I
I
-I
"1ftCD
-...
1ft
:::s
SAMPLE ASSEMBLED
o
FOR WAFER
QUALIFICATION
(OPTIONAL)
~
3
G
-o
~
:::s
PACKING AND SHIPPING
Chip Packaging
Chips are packaged as individual die in the flat waffle carrier illustrated in Figure 1. The carrier has a cavity size adequate
to allow ease of loading/unloading and also prevents die from rotating within the cavity.
NOTE: CARRIER TOP & BOnOM SECURED BV CLIPS
Figure 1
Siliconix
9-3
c
.-...
H
0
Silicanix
IS
.....
E
Die Ordering Information
0
-c
I S)
.
..
0
.-C
1.
Monolithic Chips:
CD
Example:
."
DG
-,...
501
--r-
A
DICE
lL.-__
.-QCD
Form
.....- - - - - - - - - - Screening Criteria
.....- - - - - - - - - - - - - Device Number
' - - - - - - - - - - - - - - - - - - - Device Family
DEVICE FAMILY
(1, 2 or 3 Letters)
D
- Drivers for FET Switches
DG
- Analog Switches
DGM - Analog Switches
G
- Multi-Channel FETs
Si
- Siliconix Second Source Part
DEVICE NUMBER
(3 or 4 Digit Numbers)
SCREENING CRITERIA
(1 Letter)
A
- Electrically probed @ 25°C to "A" Suffix of respective data sheet;
visual criteria screening to MI L-STD-883, Method 2010 Condition B.
- Electrically probed @ 25°C to "C" Suffix of respective data sheet;
visual criteria screening to Siliconix Specification 5018.
FORM
(4 Letters)
DICE - Chips waffle packed per Figure 4 in Die Process Information
9·4
Silicanix
CJ
2. Multichip
To order die which form multichip devices the driver chip and corresponding JFETs should be ordered using the geometry
designations as shown in Table 1 below.
-o
CD
~
A.
Example:
For D9190 die, order
CMJB1000
and NC1000
CD
-::s
~
To determine number of JFETs required to go with each driver in a multichip device, see number in parenthesis following
geometry codes as shown in table below.
ca
-...::s
o
~
.
Table 1
Siliconix
Part No.
DGl23
DG125
DG126
DGl29
DGl33
DGl34
DGl39
DGl40
DG141
DG142
DGl43
DGl44
DGl45
DGl46
DG151
DGl52
DGl53
DGl54
DG161
DGl62
DGl63
DGl64
DGl80
DG181
DGl82
DGl83
DGl84
DGl85
DGl86
DG187
DGl88
DGl89
DGl90
DG191
DG281
DG284
DG287
DG290
:I
g
Geometry Code
FET
Technology
See Dl23 and Gl15
See D125 and Gl15
NC2000(4)
NC1000(4)
NC1000(2)
NC2000(2)
NC1000(4)
NIP1000(4)
NIP1000(2)
NC2000(4)
NC2000(2)
NC1000(2)
NIP1000(4)
NIP1000(2)
NIP1000(2)
NC1000(2)
NIP1000(4)
NC1000(4)
NIP1000(2)
NC1000(2)
NIP1000(4)
NC1000(4)
NIP1000(2)
NC1000(2)
NC2000(2)
NIP1000(4)
NC1000(4)
NC2000(4)
NIP1000(2)
NC1000(2)
NC2000(2)
IIIIPl000(4)
NC1000(4)
NC2000(4)
NH1000(2)
NH1000(4)
NH1000(2)
NH1QOO(4)
PMOS Switch
PMOS Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
JFET Switch
Driver
IBAF/MABA
IBAF/MABA
LODC1000
LODC1000
LODC1000
LODC1000
LODF1000
LODC1000
LODC1000
LODF1000
LODF1000
LODF1000
LODF1000
LODF1000
LODC1000
LODC1000
LODC1000
LODC1000
LODF1000
LODF1000
LODF1000
LODF1000
CMJB1000
CMJB1000
CMJB1000
CMJA1000
CMJA1000
CMJA1000
CMJC1000
CMJC1000
CMJC1000
CMJB1000
CMJB1000
CMJB1000
CMJB1000
CMJA1000
CMJC1000
CMJB1000
o-::s
III
3. Options
The following options are considered "special" and a special part number will be assigned:
1.
2.
3.
4.
Die in wafer form
Goldbacking on Integrated Circuit die
Class A visual
Customer visual criteria
Please identify as "similarto _ _ _ _ _ with following additional condition"-s_ _ _ _ _ _ _ _ _ _ _ _ _ __
Siliconix
9·5
.-.
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Die Topography Information
fa.
Monolithic
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9·6
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~------------------------------~~~------------------------------~
PAD NO.
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Substrate
VDD
e1
91
f1
BP
a2
b2
c2
d2
e2
92
f2
a3
b3
PAD NO.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FUNCTION
PAD NO.
FUNCTION
"3
d3
e3
93
f3
a4
b4
c4
d4
e4
94
f4
BO
B1
29
30
31
32
33
34
35
36
37
38
39
40
B2
B3
01
02
03
04
VSS
OSC
a1
b1
"1
d1
= V DD
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
DF412
Pin numbers are for
dual in·line packages
PIN NO.
FUNCTION
1
2
3
SOURCE 3
SOURCE 4
DRAIN
V- (SUBSTRATEI
INPUT 4
INPUT 3
INPUT2
INPUT 1
VL
VR
V+
SOURCE 1
SOURCE 2
5
6
7
B
9
10
11
12
13
14
1---------i;~1~~ - - - - - - - - - - o j
•
3:
o
~
.
--::r
-o
ft
DG172
Siliconix
9-7
..
c
.-o
D
E
...c
~
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-.c>-
PIN NO.
1
3
5
6
A-
7
D
B
9
~
D)
10
12
14
o
A-
o
....
FUNCTION
INPUT2
GROUND
SOURCE 2
DRAIN 2
VVREF
DRAIN 1
SOURCE 1
V+ (SUBSTRATE)
INPUT 1
Pin numbers are for dual in line packages.
.-o
G)
I-------------~~~-------------
DG200
PIN NO.
FUNCTION
1
3
INPUT 2
GROUND
SOURCE 2
DRAIN 2
VDRAIN 1
SOURCE 1
V+ (SUBSTRATE)
INPUT 1
5
6
7
9
10
12
14
Pin numbers are for dual in line packages.
f---------~iO~) ----~
DG200A
9-8
Siliconix
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NOTE ROUND PAD (# 1)
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o
UI
PIN NO.
FUNCTION
1
2
3
4
5
6
INPUT 1
DRAIN 1
SOURCE 1
7
8
9
10
11
12
13
14
15
16
a
."
:r
-it
'<
v-
~
GND
SOURCE 4
DRAIN4
INPUT 4
INPUT 3
DRAIN 3
SOURCE 3
, VREF
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT 2
~
EI
--...
g
o
~
Pin numbers are for dual in line packages
OG201
PIN NO.
FUNCTION
1
INPUT 1
DRAIN 1
SOURCE 1
2
3
4
5
6
(1.831
7
8
9
10
11
13
14
15
16
vGND
SOURCE 4
DRAIN 4
INPUT 4
INPUT 3
DRAIN 3
SOURCE 3
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT 2
III
f
o
-:r-...~
Pin numbers are for dual in-line packages
--
n
OG201A
Siliconix
9·9
c
--...o
D
....
E
o
PIN NO.
-.c>c
1
2
3
4
5
6
.a.
D
0.072
11 .•31
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o
a.
o
....
--QCP
FUNCTION
10
11
13
14
15
16
INPUT 1
DRAIN 1
SOURCE 1
VGROUND
SOURCE 4
DRAIN 4
INPUT4
INPUT3
DRAIN 3
SOURCE 3
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT 2
PIN NO.
FUNCTION
1
2
3
4
5
6
INPUT 1
DRAIN 1
SOURCE 1
VGROUND
SOURCE 4
DRAIN 4
INPUT 4
INPUT 3
DRAIN 3
SOURCE 3
VL
V+ (SUBSTRATE).
SOURCE 2
DRAIN 2
INPUT 2
7
8
9
~
_ _ _ _ _ _ _ _ _ 0.080
(2.031---------
I
DG202
0.012
(1.83)
7
8
9
10
11
12
13
14
15
16
-----------~~~---------------
DG211
9-10
Siliconix
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION
INPUT 1
DRAIN 1
SOURCE 1
VGROUND
SOURCE 4
DRAIN 4
INPUT 4
INPUT 3
DRAIN 3
SOURCE 3
VL
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT 2
~----------------~~~-----------------4
DG212
PIN NO.
1
3
4
5
6
8
9
10
11
12
13
14
15
16
FUNCTION
DRAIN 1
DRAIN 3
SOURCE 3
SOURCE 4
DRAIN 4
DRAIN 2
SOURCE 2
INPUT 2
V+ (SUBSTRATE)'
VL
GND
VINPUT 1
SOURCE 1
Pin numbers are for
dual·in·line packages
~----------~~~----------~
DG243
Siliconix
9-11
c
--...0
D
.....
-.cc>..
E
0
D-
O
G)
0
DO
~
-
--.G»..
DG300
~-----------------~~~-------------------
DG300A
PIN NO.
FUNCTION
2
4
DRAIN 1
SOURCE 1
INPUT 1
GROUND
6
7
8
v-
9
INPUT 2
SOURCE 2
DRAIN 2
V+ (SUBSTRATE)
11
13
14
Pin numbers are for dual in-line packages
9-12
Siliconix
CI
CD
--I
0
"a
..a
-...
.
:I
0
CD
"a
:7'
'<
::::I
0
...--
a
0
0.072
11.83)
::::I
DG301
DG301A
PIN NO.
FUNCTION
2
4
6
7
DRAIN 1
SOURCE 1
INPUT 1
GROUND
8
v-
11
13
14
SOURCE 2
DRAIN 2
V+ (SUBSTRATE)
III
::o
::::I
o
...---
--:7'
It
Pin numbers are for dual in-line packages
Siliconix
9-13
c
o
--...
II
....
E
o
-c>-
.c
Do
a
.
II)
o
Do
o
t-
--QCD
PIN NO.
FUNCTION
2
3
4
SOURCE 3
DRAIN 3
DRAIN 1
SOURCE 1
INPUT1
GROUND
5
6
7
8
9
DG302
10
11
12
13
14
vINPUT 2
SOURCE 2
DRAIN 2
DRAIN 4
SOURCE 4
V+ (SUBSTRATE)
Pin numbers are for dual in·line packages
0,087
12.21)
~----------------~~:----------------~
DG302A
9·14
Siliconix
c
-CD
-I
o
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o
.
ca
a
'U
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.....o-:s
3
a
...
-o
:s
PIN NO.
FUNCTION
2
3
4
SOURCE 3
DRAIN 3
DRAIN 1
SOURCE 1
INPUT 1
GROUND
5
6
~----------------~~~-----------------
DG303
7
8
9
10
11
12
13
14
vINPUT 2
SOURCE 2
DRAIN 2
DRAIN4
SOURCE 4
V+ (SUBSTRATE)
Pin numbers are for dual in·line packages
III
~
o
:s
o
-...-:r
--
r-----------------~~:,----------------~
ft
DG303A
Siliconix
9-15
.
c
--0
a
.....E
-.cc>a.
..a
0
IS)
0
a.
...
0
0.072
f1.831
CD
Q
--
DG304
DG304A
PIN NO.
FUNCTION
2
4
DRAIN 1
SOURCE 1
INPUT 1
GROUND
6
7
8
9
11
13
14
vINPUT 2
SOURCE 2
DRAIN 2
V+ (SUBSTRATE)
Pin numbers are for dual in-line packages
9-16
Siliconix
"-CD
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0
".
"-<::r
...-.
0
fa
Q
::I
0
.
3
Q
--0
0.072
(1.831
::I
DG305
-
~----------------~~~------------------
DG305A
PIN NO.
FUNCTION
2
4
ORAIN 1
SOURCE 1
INPUT 1
GROUND
6
7
8
II
13
14
~
o
::I
o
.-----
vv+
:r
SOURCE 2
DRAIN 2
(SUBSTRATE)
"
Pin numbers for dual in·line packages
Siliconix
9-17
.
c
o
e_
G
....
E
o
-.cc>-
..
0.
G
m
o
0.
o
...
CD
e-
O
I----------~;~~---------
DG306
PIN NO.
FUNCTION
2
3
4
5
SOURCE 3
DRAIN 3
DRAIN 1
SOURCE 1
INPUT 1
GROUND
6
7
8
9
10
11
12
13
14
vINPUT 2
SOURCE 2
DRAIN 2
DRAIN 4
SOURCE 4
V+ (SUBSTRATE)
Pin numbers are for dual
~--------~~---------~
DG306A
9-18
Siliconix
in~line
packages
c
--
CD
-t
o
"ca..o
a
"::r
'<
...o.-:::s
.
:3
a
o-:::s
---------f;~;3~--------
DG307
PIN NO.
FUNCTION
2
3
4
SOURCE 3
DRAIN 3
DRAIN 1
SOURCE 1
INPUT 1
GROUND
5
6
7
8
9
10
11
12
13
14
vINPUT 2
SOURCE 2
DRAIN 2
DRAIN 4
SOURCE 4
V+ (SUBSTRATE)
Pin numbers are for dual in-line packages
;:
o
:::s
-.::r.
o
~
_________ __________
~o:
~
--
"
DG307A
Siliconix
9-19
c
.-...o
D
....
E
o
FUNCTION
PIN NO.
->c
1
INPUT 1
DRAIN 1
SOURCE 1
2
3
4
5
6
.c
D.
fU)
7
8
0,066
11.67)
o
o
D.
...
.-QCD
v-
I
9
10
11
13
14
15
16
I
GROUND
SOURCE 4
DRAIN 4
INPUT 4
INPUT3
DRAIN 3
DRAIN 3
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT2
I
Pin numbers are for dual in-line packages
~-----------------~~~------------------~
DG308
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
FUNCTION
INPUT 1
DRAIN 1
SOURCE 1
VGROUND
SOURCE 4
DRAIN 4
INPUT 4
INPUT 3
DRAIN 3
DRAIN 3
V+ (SUBSTRATE)
SOURCE 2
DRAIN 2
INPUT 2
Pin numbers are for dual in-line packages
DG309
9·20
Siliconix
--cCD
-I
0
"a
0
ca.,
a
"a
::r
-...
'<
0.063
!1.60)
::I
.,0
3
a
-0
~
::I
0.072
(1.83)
DG381
PIN NO.
FUNCTION
1
2
SOURCE 1
DRAIN 1
INPUT 1
V+ (SUBSTRATE)
VR
VINPUT 2
DRAIN 2
SOURCE 2
5
6
8
9
10
13
14
Pin numbers are for dual inMline packages
3:
o
::I
o
-::r-~
-ft
DG381A
Siliconix
9-21
c
.-...o
a
....
E
o
-c>-
.c
D.
a
.o
G)
A.
o
tel»
g
.-
I---------~;';;'~--------
DG384
PIN NO.
FUNCTION
1
3
4
5
6
DRAIN 1
DRAIN 3
SOURCE 3
SOURCE 4
DRAIN 4
DRAIN 2
SOURCE 2
INPUT 2
V+ (SUBSTRATE)
GROUND
VINPUT 1
SOURCE 1
8
9
10
11
13
14
15
16
Pin numbers are for dual in-line packages
1---------
r,D:: - - - - - - - - 1
DG384A
><
'f
o
,Y
Iii
9·22
Siliconix
c_.
...otD
"a
o
ca
.,
a
"a
~
-...:s
'<
.,o
.-.
3
a
o
::I
1----------~iO;~---------I
DG387
PIN NO.
FUNCTION
3
4
DRAIN 1
SOURCE 1
INPUT 1
V+ (SUBSTRATE)
VR
VSOURCE 2
DRAIN 2
5
6
8
9
11
12
Pin numbers are for dual in-line packages
l1li
3:
o
:a
o
I-------------~~:--------~
--:::r. .
DG387A
-.
ft
Siliconix
9-23
c
--...0
a
.....
E
0
-c>-
.c
a.
a
..
m
0
a.
0.096
(2.44)
0
t-
-
--...
el)
DG390
PIN NO.
FUNCTION
1
3
4
5
6
INPUT 1
DRAIN 3
SOURCE 3
SOURCE 4
DRAIN 4
DRAIN 2
SOURCE 2
INPUT 2
V+ (SUBSTRATE)
GND
VINPUT 1
SOURCE 1
8
9
10
11
13
14
15
16
Pin numbers are for dual in·line packages
~---------------~~~----------------~
DG390A
9·24
Siliconix
c
-CD
....
o
~
o
PIN NO.
1
2t
3
4t
5
6
7
8
9
10
11
12
13
14
15
16
.
-:....s
.3
CO
FUNCTION
a
ENABLE
V+ (SUBSTRATE)
DRAIN
V+ (SUBSTRATE)
SOURCE 8
SOURCE 7
SOURCE 6
SOURCE 5
SOURCE 4
SOURCE 3
SOURCE 2
SOURCE 1
VADDRESS 0
ADDRESS 1
ADDRESS 2
~
:::r
'<
o
.-a
o
:s
*138 is connected to V-
t Pins 2 and 4 are interconnected,
either one may be used
Pin numbers are for dual in-line packages
I--------~i~~~--------I
DG501
0,089
12.261
PIN NO.
FUNCTION
1
2'
3
4'
5
6
7
8
ENABLE
V+ (SUBSTRATE)
DRAIN
V+ (SUBSTRATE)
SOURCE 8
SOURCE 7
SOURCE 6
SOURCE 5
SOURCE 4
SOURCE 3
SOURCE 2
SOURCE 1
VADDRESS 0
ADDRESS 1
ADDRESS 2
9
10
11
12
13
14
15
16
~
o
:s
o
.-----
*Pins 2 and 4 are interconnected,
either one may be used
:::r
Pin numbers are for dual in-line packages
ft
1--------~i05~~-------
DG503
Siliconix
9·25
..
c
.-0
a
.
->a.
a.
E
....0c
.c
U)
0
a.
0.t07
0
(2.72)
l-
.-QCD
I
I--_ _ _ _ _ _ _ _ ~O:~-------I
PIN NO.
1
PIN NO.
FUNCTION
1
11
12
13
14
15
16
DRAIN 1
V+ (SUBSTRATE)
VL
GND
VINPUT 1
SOURCE 1
8
9
10
11
12
13
14
15
16
DRAIN 1
DRAIN 2
SOURCE2
INPUT 2
V+ (SUBSTRATE)
VL
GND
VINPUT 1
SOURCE 1
DG5041
DG5040
9·26
FUNCTION
Siliconix
II:»
-....
o
CD
"o
a
":::r
'<
CO
~
:...;.
I
o
~
.-3
D
o
:I
1 - - - - - - - - ~;o,"s'; - - - - - - - - 1
PIN NO.
FUNCTION
1
3
4
11
12
13
14
15
16
DRAIN 1
DRAIN 2
SOURCE 2
V+ (SUBSTRATE)
VL
GND
VINPUT 1
SOURCE 1
PIN NO.
FUNCTION
1
3
4
5
6
DRAIN 1
DRAIN 3
SOURCE 3
SOURCE 4
DRAIN 4
DRAIN 2
SOURCE 2
INPUT2
V+ (SUBSTRATE)
8
9
10
11
12
13
14
15
16
l1li
VL
GND
VINPUT 1
SOURCE 1
~
o
:I
--:::r.-
o
DG5043
DG5042
--
"
Siliconix
9-27
.
c
.-0
IS
..
-.c>E
...c
0
.a.m
IS
0
a.
0
0107
(2.72)
~
.-CI
G)
0.069
(1.75)
,_ _ _ _ _ _ _ _ _ O.069 _ _ _ _
,(175)
PIN NO.
PIN NO.
FUNCTION
1
3
4
11
12
13
14
15
16
DRAIN 1
DRAIN 2
SOURCE 2
V+ (SUBSTRATE)
VL
GND
VINPUT 1
SOURCE 1
1
3
4
5
6
8
9
10
11
12
13
14
15
16
~~_1
FUNCTION
DRAIN 1
DRAIN 3
SOURCE 3
SOURCE 4
DRAIN 4
DRAIN 2
SOURCE 2
INPUT 2
V+ (SUBSTRATE)
VL
GND
VINPUT 1
SOURCE 1
Pin numbers are for dual·in·line packages.
DG5044
9-28
DG5045
Siliconix
c
-CD
-I
o
"a
o
.
-.....o
c.a
a
"a
:r
'<
::::I
PIN NO.
FUNCTION
1
4
5
6
7
V+ (SUBSTRATE)
SOURCE 16
SOURCE 15
SOURCE 14
SOURCE 13
SOURCE 12
SOURCE 11
SOURCE 10
SOURCE 9
GROUND
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
..
3
a
o--
...
::::I
VREF
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS 0
ENABLE
SOURCE 1
SOURCE 2
SOURCE 3
SOURCE 4
SOURCE 5
SOURCE 6
SOURCE 7
SOURCE 8
VDRAIN
Pin numbers are for dual in·line packages
~
o
::::I
o
--:r...--
ft
DG506
Siliconix
9·29
..
c
.-o
a
....
-
E
o
c
PIN NO.
FUNCTION
1
4
5
6
7
B
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V+ (SUBSTRATE)
SOURCE 16
SOURCE 15
SOURCE 14
SOURCE 13
SOURCE 12
SOURCE 11
SOURCE 10
SOURCE9
GROUND
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS 0
ENABLE
SOURCE 1
SOURCE 2
SOURCE 3
SOURCE 4
SOURCE 5
SOURCE 6
SOURCE 7
SOURCE 8
vDRAIN
Pin numbers are for dual in-line packages
1 - - - - - - - - - ~1~~---------I
DG506A
9-30
Siliconix
NOTE SLANTEO EOGE
PIN NO.
FUNCTION
1
2
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V+ (SUBSTRATE)
DRAIN b
SOURCE 8b
SOURCE 7b
SOURCE 6b
SOURCE 5b
SOURCE 4b
SOURCE 3b
SOURCE 2b
SOURCE1b
GROUND
VREF
ADDRESS 2
ADDRESS 1
ADDRESS 0
ENABLE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
VDRAIN
1a
2a
3a
4a
6a
6a
7a
8a
a
Pin numbers are for dual in-line packages
~-------------------~~~--------------------4
DG507
Siliconix
9-31
.
e
o
e_
IS
....E
-.ce>a.
.a
o
m
o
a.
o
I-
eI>
e-
O
PIN NO.
FUNCTION
1
.2
4
5
6
7
8
V+ (SUBSTRATE)
DRAIN b
SOURCE 8b
SOURCE 7b
SOURCE 6b
. SOURCE 5b
SOURCE 4b
SOURCE 3b
SOURCE 2b
SOURCE1b
GROUND
ADDRESS 2
ADDRESS 1
ADDRESS 0
ENABLE
SOURCE1a
SOURCE 2a
SOURCE 3a
SOURCE 4a
SOURCE 5a
SOURCE 6a
SOURCE 7a
SOURCE 8a
VDRAIN a
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin numbers are for dual in·line packages
~----------------~~;,----------------~
DG507A
9-32
Silicanix
"...-o
CD
NOTE ROUND PAD (= 1)
~
o
.
fa
II
~
:r
'<
.....o~
:I
...--
II
o
~
-----------------~~~------------------
~---------------~~~--------------~
DG508
DG508A
PIN NO.
FUNCTION
1
2
3
4
5
6
7
ADDRESS 0
ENABLE
8
9
10
11
12
13
14
15
16
vSOURCE 1
SOURCE 2
SOURCE 3
SOURCE 4
DRAIN
SOURCES
SOURCE 7
SOURCE 6
SOURCE 5
V+ (SUBSTRATE)
GROUND
ADDRESS 2
ADDRESS 1
3:
o
~
o
...:r----
Pin number are for dual in·line packages
ft
Siliconix
9·33
..
c
.-o
a
E
....
-.cc>..oa
o
A.
CD
A.
o
J-
.-oCD
I---------~i~;~---------
I---------~~~--------~
DG509
DG509A
PIN NO.
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADDRESS 0
ENABLE
vSOURCE la
SOURCE 2a
SOURCE 3a
SOURCE 4a
DRAIN a
DRAIN b
SOURCE 4b
SOURCE 3b
SOURCE 2b
SOURCElb
V+ (SUBSTRATE)
GROUND
ADDRESS 1
Pin numbers are for dual in-line packages
9-34
Siliconix
CI
CD
--
...o
"a
o
CD
~
a
"a
:r
'<
...o:::I
~
3
...
a
-o
:::I
I -_ _ _ _ _ _ _ _ ~;O,'~--------PIN NO.
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
I_ _ _ _ _ _ _ ~;O..~-------
PIN NO.
FUNCTION
1
3
4
5
6
7
8
9
10
11
12
13
14
SOURCE 4
ANALOG GROUNO 2
SOURCE 3
SOURCE 2
ANALOG GROUND 1
SOURCE 1
SUM JCT
V+ (SUBSTRATE)
Bl
B2
B3
B4
V-
Pin numbers are for dual in-line packages
FUNCTION
SOURCE 6
SOURCE 7
SOURCE 8
SOURCE 9
SOURCE 10
VBl0
B9
B8
B7
66
65
64
B3
B2
61
V+ (SUBSTRATE)
SUM JCT
SI
ANALOG GROUND
S2
S3
S4
85
,
3:
o
:::I
o
...---
Pin numbers are for dual in-line packages
DG515
DG516
:r
--
"
Siliconix
9·35
.
c
--0
a
E
....
0
-.cc>-
l
J
.
Q.
a
0.040
(1.011
at
0
Q.
...
0
-
--CD
FUNCTION
1
2
3
4
5
6
7
8
V- (SUBSTRATE)
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT5
INPUT 6
VR
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
9
10
11
12
13
i4
I
0052
11.32)
W
PIN NO.
Pin numbers are for dual in-line packages
0123
l
~J
0,040
PIN NO.
FUNCTION
1
2
3
4
5
6
7
V- (SUBSTRATE)
INPUT 1
INPUT 2
INPUT 3
INPUT4
INPUT 5
INPUT6
VL
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
8
9
10
11
12
13
14
~---------~~~----------~
Pin numbers are for dual in-line packages
0125
9·36
Siliconix
"-CD
-I
o
PIN NO.
FUNCTION
1
2
3
4
5
6
7
INPUT 1
INPUT 2
INPUT 3
INPUT4
INPUT 5
INPUT 6
INPUT 7
VR
V- (SUBSTRATE)
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VL
8
9
10
11
12
13
14
"cao.
a
"'<::r
-...
o
:::a
..:1
--...
a
o
:::a
Pin numbers are for dual in line packages
0129
PIN NO.
FUNCTION
3
4
OUTI
OUTI
INPUT 1
V+
VL
VR
V- (SUBSTRATE)
INPUT 2
OUT2
5
6
7
8
9
10
11
12
B,
I
o
0u'f2
Pin numbers are for dual in-line packages
:::a
--...-
o
::r
I--_ _ _ _ ~;O~_----
-ft
0139
Siliconix
9-37
c
.-...o
D
E
...c
~
o
-.c
PAD NO.
FUNCTION
3
OUT1
OUT1
IN1
>.
4
5
6
D-
8
9
V+
VL
VR
V-
10
11
12
IN2
OUT2
OUT2
7
IS
~
D)
o
DO
...
Substrate
=V-
.-gCD
D169
0.045
11.141
0.062
(1.571
*Both "'D"' pads are electrically common. Either can be used for drain contact.
PAD
tG1
tG2
tG3
tG4
tGS
tG6
B
D
S6
Ss
S4
S3
S2
S1
G115
G116
DUAL IN·LINE
DUAL IN-LINE
PACKAGE
PACKAGE
PIN NO.
PIN NO.
PIN NO.
G118
G124
DUAL IN·LINE
DUAL IN·LINE
PACKAGE
PACKAGE
PIN NO.
PIN NO.
8
8
1
2
3
4
S
6
7
14
NOT USED
NOT USED
14**
8
9
9
9
10
11
12
13
10
11
12
13
10
11
12
13
14
TIED TO
SUBSTRATE
2
3
4
S
2
3
4
S
6
7
9
6
16
10
11
12
13
14
1S
G117
FLAT PACK
NOT USED
3
4
S
6
7
2
P
t Any unused gates should be connected to the substrate V+; unused sources can be left open
**The G117 uses the S6 pad as the drain output (pin 14 on package).
9·38
Siliconix
2
3
4
S
NOT USED
NOT USED
14
NOT USED
NOT USED
10
11
12
13
8
FUNCTION
GATE 1
GATE 2
GATE 3
GATE 4
GATES
GATE 6
BODY (SUBSTRATE) V+
DRAIN
SOURCE 6
SOURCE S
SOURCE 4
SOURCE 3
SOURCE 2
SOURCE 1
PULL UP GATE INPUT
CJ
--
...
"ca
a
":r
CD
o
o
-o:s
..:I
'II(
-ta
...--
II
I------~;~~-----
o
PAD
FLAT PACK
Ga
Gb
Gc
Gc
Gb
Ga
B
Db
SF
SE
So
Sc
SB
SA
Da
P
FLAT PACK
FUNCTION
PIN NO.
PIN NO.
GATE 1
GATE 3
GATE 5
3
4
5
FUNCTION
GATE2
3
tNOT USED
GATE 1
5
6
7
9
10
11
12
13
14
1
2
:s
G122
G119
BODY (SUBSTRATE V+)
DRAIN 2
SOURCE 2
SOURCE 4
SOURCE 6
SOURCE 5
SOURCE 3
SOURCE 1
DRAIN 1
PULL UP GATE INPUT
8
9
10
11
NOT USED
NOT USED
12
13
14
1
BODY (SUBSTRATE V+)
DRAIN 1
SOURCE 1
SOURCE 2
SOURCE 3
SOURCE 4
DRAIN 2
PULL UP GATE INPUT
t Any unused gates should be connected to the substrate V+; unused sources can be left open.
G119
G122
PIN NO.
FUNCTION
1
2
3
4
P (PULL UP GATE INPUT)
GATE 1
GATE 2
GATE 3
GATE 4
BODY (SUBSTRATE)V+
DRAIN 2
SOURCE 4
SOURCE 3
SOURCE 2
SOURCE 1
DRAIN 1
5
8
9
10
11
12
13
14
D
3:
o
:s
o
-...-:r
--
Pin numbers are for dual in-line packages.
ft
-----~;O,_.;;-----
G123
Siliconix
9·39
c
0
--•
IS
....
E
0
-c>-
.c
a.
..
IS
IS)
0
a.
0
I-
--G)
0.129
f3.28)
W
----------------~~5~ - - - - - - - - - - - - - - - - 1
PAONO. FUNCTION
1
01
2
02
3
03
4
04
5
SIGN
6
VSS
7
CLOCK IN
8
COMP
9
UfO
10
MfZ
, 11
V2
12
GNO
13
B4
14
83
15
B2
16
B1
Substrate = Vss
'Leave unused pads floating
LD110
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
9-40
Siliconix
CJ
--
...
CD
o
"a
0.090
12.29)
PAD NO.
FUNCTION
1
2
3
4
5
6
7
BUFF OUT
HI-Q GNO
MfZ
o
ca
a
.
"a
:r
'<
UfO
-
COMP
V2
GNO
REF OUT
INT IN
8
9
10
11
12
13
14
15
16
::::I
.
~
o
3
..--
VREF
)NT OUT
AZOUT
AZFILTER
AZIN
VIN
VI
a
o
::::I
Substrate = V2
-------------------~~~-------------------
LD111A
PAD NO.
FUNCTION
1
2
3
4
5
BUFF OUT
HI·Q GNO
MfZ
UfO
COMP
V-
6
7
8
0.090
(2.29)
9
10
11
12
13
14
15
16
Substrate
ANALOG GNO
REFOUT
INTIN
VREF
INTOUT
AZOUT
AZ FILTER
AZIN
IIJI
3:
JtJ
o
::::I
o
--.-
=V
:r
--
"
1------------------ ~20;~ ----------------__
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
LD120
Siliconix
9-41
c
.-...o
a
E
r..
o
It-
C
.c>a.
a
m
r..
o
a.
o
...
.-oG)
~-----------------------------------~~~----------------------------------I
PAD NO.
FUNCTION
1
2
3
4
5
02
01
6
7
8
9
10
11
12
13
14
15
16
17
18
COMP
GNO
U/O
M/Z
START
OSC
BO
B1
B2
B3
SIGN/OR/UR
VSS
VOO
05
04
03
Substrate = VSS
*Leave unused pads floating
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
9·42
LD121A
Siliconix
--a
CD
....
o
"cao
"
'<
-a.
~
Q
:::I"
o
~
.--
3
Q
o
:::I
PAD NO.
FUNCTION
1
2
3
4
5
6
7
BUFFIN
HI·Q GND
M/Z
UID
COMP
VANALOG GND
REFOUT
INT IN
VREF
INT OUT
AZOUT
AZ FILTER
AZIN
VIN
V+
8
9
10
11
12
13
14
15
16
1 - - - - - - - ~;"i.;'; - - - - - - -
Substrate = V-
PAD NO.
FUNCTION
1
2
3
4
5
6
9
10
11
12
13
14
SET
OUT 1
-IN2
+IN2
+lN3
-IN3
OUT3
-Vs
OUT2
+INI
-INI
+Vs
Substrate = -Vs
L144
LD122
PAD NO.
0.048
TiT2f
1
2
3
4
5
6
7
8
9
------
10
11
12
13
15
16
~;":~ - - - - - - - - j
FUNCTION
D
+IN I
-INI
+ IN 2
--IN2
- IN 3
+IN 3
-IN4
+IN4
-V
OUT4
OUT3
OUT2
OUTI
ISET
+V
3:
o
:::I
o
.
--:::I"
--
'"
Substrate = -V
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
L161
Siliconix
9·43
.-.o
c
IS
.....
-1-c
E
o
Die Topography Information
Multichip
Q.
to
Q.
o
.-
.CD
Q
9-44
Siliconix
--c
H
CD
Siliconix
Die Topography Information
....
o
o
ca
a
"..
"
'<
-...o:::s
~
,Some of Siliconix's analog switches are of multi-chip
design with inter-chip connections. The DG123, for example, consists of a separate driver chip (I BAF) and a separate
'MaS switch chip (MABA). Figure '--iTiustrates the bonding arrangement in the DIP package. Note that the two
chips are mounted on electrically separate islands. This
is due to the different substrate potentials, the MABA
substrate is at the positive supply voltage while the EID
substrate is at the negative supply voltage.
The JFET switches, for example, are also of multi-chip
design. The DG 190 consists of a separate driver chip
(CMJB) and four separate JFET transistors (NC). Figure 2
illustrates the bonding diagram arrangement in the DIP
package. The driver and the JFET switches are mounted so
that the substrates are electrically isolated. The substrate
of the driver is at the negative supply voltage while the
substrate of the JFET switches is the gate connection. A
bond wire connects the driver to the JFET gate.
The pin connections for the JFET switch chips can be
determined from the chip section and switch pin-out
in the data sheet. For example, from the DG 190 pin
configuration we see that the DG190 has 4 JFETs in
one package; D3 and S3 are the drain and source of the
third JFET.
..3
.-a
o
:::s
Die Diagrams/Dimensions
These negative image photos are of the metallization
pattern. Scale is ""32x. Bonding pads are 4 mil (0.10 mm)
square, glass-free aluminum metallization. Pad identification
numbers correspond to pin numbers for the dual-in-line
package on data sheets. The "geometry" is an alpha code
used in the factory for identification.
The following pages contain layout, die dimensions and
pad identification.
LEAD TRACE
TOPIN
l1li
SEPARATE DIE ATTACH
ISLANDS TO ELECTRICALLY
CHIP
INTERCONNECT
WIRES
ISOLATE THE SUBSTRATE
.---
~.
c
ft
~
--
"
Figure 1. DG123 Analog Switch (Multi-Chip I
Siliconix
9-45
c
.-o
.p
a
E
....
Die Topography Information
(Continued)
o
-
c
.c>a.
a
.o
m
a.
....o
.-oeI)
DIE ATTACH ISLAND FOR
JFET SUBSTRATES
Figure 2. DG190 JFET Analog Switch
NOTE: Die Topography is for reference only
9·46
Siliconix
CMJA1000 -
a--
DRIVER CHIP CHARACTERISTICS
CD
All parameters are specified under the following conditions: V + = 15 V. V - = -15 V. VR = 0 V. VL = 5 V. T A =25°C.
-I
0
DC PARAMETERS
Characteristics
2
3
4
5
6
7
Min
Max
9
"a
.
0
Test Conditions
CQ
IINL
Input Current
Input Voltage Low
-250
p.A
VIN=O V
IINH
Input Current
Input Voltage High
20
p.A
VIN=5 V
"a
VIN=O V
'<
VIN=5 V
~
IL
4.5
Logic Supply Current
4.5
IR
Reference Supply Current
1-
Negative Supply Current
-2
-2
-5.5
-4
8
10
Unit
1+
3
Positive Supply Current
0.1
mA
a
~
....-
VIN=O V
mA
0
VIN=5 V
3
a...
VIN=O V
mA
VIN=5 V
--
VIN=O V
mA
0
~
VIN=5 V
VIN =0.8 V or 2.0 V
INTERCHIP PAD CONNECTIONS
10
11
12
13
14
15
A
B
C
0
E
F
G
H
FUNCTION
PAD NO.
v-
INPUT 2
V+
VL
VR
(SUBSTRATE)
INPUT 1
FROM JFET 1. SOURCE
TO JFET 1. GATE
TO JFET 3. GATE
FROM JFET 3. SOURCE
FROM JFET 4. SOURCE
TO JFET 4. GATE
TO JFET 2, GATE
FROM JFET 2. SOURCE
-----~;01~-----I
1m
3:
CMJA1000 is used for following devices:
DEVICE
JFETUSED
NO.OFJFETs
DGl83
DGl84
DG185
DG284
NIP1000
NC1000
NC2000
NH1000
4
Siliconix
--.-..
"-c
4
~
4
4
"a
9·47
.
C
0
--
IS
......
-.c
.
E
CMJB1000 - DRIVER CHIP CHARACTERISTICS
All parameters are specified under the following conditions: V+ = 15 V, V- = -15 V, VR =0 V, VL =5 V, TA =25°C.
DC PARAMETERS
Max
Unit
Test Conditions
IINL
Input Current
Input Voltage Low
Characteristics
-250
/LA
VIN=O V
IINH
Input Current
Input Voltage High
20
/LA
VIN=5 V
IL
Logic Supply Current
IR
Reference Supply Current
I-
Negative Supply Current
0
C
>.
D.
IS
IS)
0
D.
0
2
3
4
5
6
7
l-
8
--G)
iO
-
9
Min
4.5
-2
VIN=5 V
VIN=O V
mA
-2
-5
-5
1+
VIN=O V
mA
4.5
1.5
Positive Supply Current
1.5
VIN=5 V
VIN=O V
mA
VIN=5 V
VIN=O V
mA
VIN=5 V
VIN =0.8 V or 2.0 V
INTERCHIP PAD CONNECTIONS
A
B
C
0
PAD NO.
10
11
12
13
14
15
E
F
G
H
FUNCTION
INPUT 2
V+
VL
VR
A
B
C
V - (SUBSTRATE)
INPUT 1
0
E
F
G
H
~--------~~~--------~
CMJB1000 is used for following devices:
9·48
DEVICE
JFETUSED
NO.OFJFETs
DGl80
DG181
DG1B2
DGl89
DGl90
DG191
DG2Bl
DG290
NIP1000
NC1000
NC2000
NIP1000
NC1000
NC2000
NH1000
NH1000
2
2
2
4
4
4
2
4
Siliconix
With 2 JFETs:
NO CONNECTION
NO CONNECTION
TO JFET 2, GATE
FROM JFET 2, SOURCE
FROM JFET I, SOURCE
TO JFET I, GATE
NO CONNECTION
NO CONNECTION
With 4 JFETs:
FROM JFET I,
TO JFET I,
TO JFET 3,
FROM JFET 3,
FROM JFET 4,
TO JFET 4,
TO JFET 2,
FROM JFET 2,
SOURCE
GATE
GATE
SOURCE
SOURCE
GATE
GATE
SOURCE
"...--
CMJC1000 - DRIVER CHIP CHARACTERISTICS
CD
All parameters are specified under the following conditions: V+ = 15 V, V- = -15 V, VR=O V, VL =5 V, TA=25°C.
0
DC PARAMETERS
Characteristics
2
3
4
5
6
7
10
Max
Unit
-250
pA
VIN=O V
IINH
Input Current
Input Voltage High
10
p,A
VIN=5 V
IL
Logic Supply Current
IR
1-
1+
3.2
3.2
-2
Reference Supply Current
-2
-3
Negative Supply Current
-3
0.8
Positive Supply Current
0.8
"
"-<:::r
...0
Test Conditions
IINL
8
9
Min
Input Current
Input Voltage Low
CD
~
Q
VIN=OV
mA
VIN=5 V
~
VIN=O V
mA
0
~
VIN=5 V
3
VIN=O V
mA
...--
Q
VIN=5 V
VIN=O V
mA
0
~
VIN=5 V
INTERCHIP PAD CONNECTIONS
0.080
(2.03)
PAD NO.
FUNCTION
5
6
7
INPUT1
A
B
C
v+
0
VL
VR
NOT CONNECTED
V- (SUBSTRATE)
E
F
G
H
8
9
10
NOT CONNECTED
FROM JFET 2. SOURCE
NOT CONNECTED
NOT CONNECTED
TO JFET 2. GATE
NOT CONNECTED
TO JFET 1, GATE
FROM JFET 1. SOURCE
~--------~~~---------
l1li
~
CMJC1000 is used for following devices:
DEVICE
JFETUSED
NO.OFJFETs
OG186
OGl87
OGl88
OG287
NIP1000
NC1000
NC2000
NH1000
2
2
2
2
Siliconix
--:::r-...
"--
C
"
9·49
~
-E
....
o
-c>..
D
LODC1000 - DRIVER CHIP CHARACTERISTICS
All parameters are specified under the following conditions: V + = + 12 V. V - = -18 V. VR = 0 V. T A = 25°C.
DC PARAMETERS
Max
Unit
IINL
Input Current
Input Voltage Low
Characteristics
0.1
p.A
VIN=0.8 V
2
IINH
Input Current
Input Voltage High
100
p.A
VIN=2.5 V
D.
D
3
1+
Positive Supply Current
3.3
p.A
4
1-
Negative Supply Current
-2.0
p.A
D)
5
IR
Reference Supply Current
-1.5
p.A
6
1+
Positive Supply Current
25
p.A
7
1-
Negative Supply Current
-25
p.A
8
IR
Reference Supply Current
-25
p.A
.J:
.
o
D.
o
...
--a
Q)
Min
Test Conditions
VIN=2.5 V. One Channel On
Both VIN = 0 V. All Channels Off
NOTES:
1. VIN must be a step function with a minimum rise and fall rate of 1 V/p,S.
2. The supply vOltage condition of + 12 V/- 18 V is standard test condition. Specs will also be met with + 15 VI -15 V supplies, but are not tested.
l
INTERCHIP CONNECTIONS
0,036
J
PAD NO.
9
10
11
12
13
FUNCTION
INPUT 1
VR
v+
V- (SUBSTRATE)
INPUT 2
' - -_ _ _ _ _ _ _ 0.063 _ _ _ _ _ _ _ _1
,-
(1.60)
LODC1000 is used for following devices:
9·50
A
B
C
D
DEVICE
JFETUSED
NO.OFJFETs
DG126
DG129
DG133
DG134
DG140
DG141
DG151
DG152
DG153
DG154
NC2000
NC1000
NC1000
NC2000
NIP1000
NIP1000
NIP1000
NC1000
NIP1000
NC1000
4
4
2
Siliconix
2
4
2
2
2
4
4
A
B
C
o
With 2 JFET.:
TO GATE 2
NO CONNECTION
TO GATE 1
NO CONNECTION
With 4 JFETs:
TO GATE 4
TO GATE 2
TO GATE 3
TO GATE 1
"...--
LODF1000 - DRIVER CHIP CHARACTERISTICS
All parameters are specified under the following conditions: V +
otherwise noted, TA ~ 25°C.
~
+ 12 V, V -
~
CD
-18 V, VR ~ 0 V, VIN2 ~ 2.5 V unless
o
o
'a
.
-...
.3
DC PARAMETERS
Characteristics
Min
Max
Input Current
Input Voltage Low
0.1
0.1
IlA
VINl ~2 V, VIN2~2.5 V
VIN1 = 2.5 V, VIN2 = 2 V
2
IINH1
IINH2
Input Current
Input Voltage High
100
100
IlA
VINl ~3 V, VIN2~2.5 V
VINl ~2.5 V, VIN2~3 V
3
1+
Positive Supply Current
4.5
IlA
4
1-
Negative Supply Current
-2.2
IlA
5
IR
Reference Supply Current
-2.4
IlA
6
1+
Positive Supply Current
25
IlA
7
1-
Negative Supply Current
-25
p.A
8
IR
Reference Supply Current
-25
IlA
ca
a
'a
::r
Test Conditions
Unit
IINL1
IINL2
'<
:::s
VINl ~2 V or VINl ~3 V,
One Channel On
o
...-,
a
VINl ~VIN2~0.8 V,
All Channels Off
o
. :::s
NOTES:
1. VIN must be a step function with a minimum rise and fall rate of 1 VIp.5.
2. The supply voltage condition of + 12 V/-1B V is standard test condition. Specs will also be met with + 15 V/-15 V supplies, but are not tested.
l
0.036
(0.91)
INTERCHIP CONNECTIONS
PAD NO.
FUNCTION
9
INPUT 1
VR
V+
V- ISUBSTRATE)
INPUT2
10
11
12
13
A
B
C
D
With 2 JFETs:
TO GATE 2
NO CONNECTION
TO GATE 1
NO CONNECTION
A
B
C
D
With 4 JFETs:
TO GATE
TO GATE
TO GATE
TO GATE
4
2
3
1
~------------~~~--------------I
LODF1000 is used for following devices:
DEVICE
JFETUSED
NO.OFJFETti
DGl39
DG142
DGl43
DGl44
DGl45
DGl46
DG161
DG162
DGl63
DGl64
NC1000
NC2000
NC2000
NC1000
NIP1000
NIP1000
NIP1000
NC1000
NIP1000
NC1000
4
4
2
2
4
2
2
2
4
4
Siliconix
III
Ic
.---..
"::r
--
'a
9·51
.
c
o
--
G
.....oE
-.cc>-
.aa.
G)
o
a.
o
...
.=
G)
NC1000 JFET SWITCH CHARACTERISTICS
DC PARAMETERS TA=25°C
Characteristics
Min
Max
Unit
-35
1
BVGDS
Gate-Drain Breakdown Voltage
2
ID(otf)
Drain Cut Off Current
1.0
nA
V
3
IS(off)
Source Cut Off Current
1.0
nA
4
rDS(on)
Drain Source-ON Resistance
30
0
Max
Unit
Test Conditions
IG= -1 p.A
VDS=22 V, VGS= -6.2 V
VDS=22 V, VGS= -6.2 V
VGS=O V, GDS=0.2 V
NC2000 JFET SWITCH CHARACTERISTICS
DC PARAMETERS TA=25°C
Characteristics
1
BVGDS
Min
Gate-Drain Breakdown Voltage
-35
Test Conditions
IG= -1 p.A
V
2
ID(offl
Drain Cut Off Current
1.0
nA
VDS=22 V, VGS= -3.9 V
3
'Stoff)
Source Cut Off Current
1.0
nA
VDS=22 V, VGS= -3.9 V
4
rDS(on)
Drain Source-ON Resistance
75
0
.l
j31
INTERCHIP
CONNECTIONS
FUNCTION
S
D
SOURCE
DRAIN
0.021
s.
VGS=OV, GOS=0.2V
Gate is on backside of chip
LO.021_1
(0.53)
NC1000/NC2000
NH1000 JFET SWITCH CHARACTERISTICS
DC PARAMETERS TA = 25°C
Characteristics
Min
Max
Unit
-33
Test Conditions
1
BVGDS
Gate-Drain Breakdown Voltage
V
IG= -1 p.A
2
ID(off)
Drain Cut Off Current
200
pA
VOS=22 V, VGS= -6.2 V
3
IS(off)
Source Cut Off Current
200
pA
VDS=22 V, VGS= -6.2 V
4
rDS(on)
Drain Source-ON Resistance
300
0
VGS=OV, GDS=0.2V
GATE ALSO BACKSIDE CONTACT
~
I
9-52
1
~I!I 'J
~:I~~
(O3871
INTERCHIP PAO
CONNECTIONS
FUNCTION
S
D
G
SOURCE
DRAIN
GATE
300n
JFET SWITCH CHIP
NIP1000 JFET SWITCH CHARACTERISTICS
Min
Max
Unit
-33
Gate-Drain Breakdown Voltage
Test Conditions
V
IG= -11JA
2
Drain Cut Off Current
10
nA
VGS= -6.2 V, VDS=22 V
3
Source Cut Off Current
10
nA
VGS= -6.2 V, VDS= -22 V
4
Drain Source
10
Q
VGS=O V, GDS=0.2 V
-...::s
.,o
BOTH GATE PADS ARE COMMON.
GATE ALSO ON BACKSIDE
1
INTERCHIP PAD
CONNECTIONS
FUNCTION
S
D
G
SOURCE
DRAIN
GATE
0,030
(0.76)
.
3
a
o-.
::s
* Either gate pad can be used,
backside is also gate
LD.D3D_1
10.76)
III
~
-._.
c
"::r
-.
"a
Siliconix
9-53
c
.-...o
1
II
.....oE
0,040
~J
-.cc>-
..
0.045
I------~~~------II
G.
II
m
o
G.
o
t-
PIN NO.
FUNCTION
4
5
6
V- (SUBSTRATE)
INPUT 1
INPUT 2
INPUT 3
INPUT4
INPUT 5
VR
7
.-oCD
B
9
10
--------~i~;~--------11
PIN NO.
FUNCTION
1
2
3
4
11
12
13
14
SOURCE 2
SOURCE 1
DRl\11'J
VV+ (SUBSTRATE)
SOURCE 5
SOURCE 4
SOURCE 3
INTERCHIP PAD CONNECTIONS
A
B
C
D
E
TO
TO
TO
TO
TO
GATE
GATE
GATE
GATE
GATE
1
2
3
4
5
J
INTERCHIP PAD CONNECTIONS
A
B
C
D
E
GATE
GATE
GATE
GATE
GATE
1
2
3
4
5
Pin numbers are for dual in-line packages
DRIVER CHIP
MOS SWITCH CHIP
DG123
l
0.045
J
PIN NO.
'--_ _ _ _ _ _ _ 0.062 _ _ _ _ _ _ _ 1
~
11.57)
FUNCTION
V-(SUBSTRATE)
INPUT 1
INPUT2
INPUT 3
INPUT4
INPUT 5
VL
4
5
6
7
B
9
10
INTERCHIP PAD CONNECTIONS
A
B
C
D
E
TO
TO
TO
TO
TO
GATE
GATE
GATE
GATE
GATE
1
2
3
4
5
PIN NO.
FUNCTION
1
2
3
4
11
12
13
14
SOURCE 2
SOURCE 1
DRAIN
VV+ (SUBSTRATE)
SOURCE 5
SOURCE 4
SOURCE 3
A
B
C
D
E
Pin numbers are for dual in-line packages
DRIVER CHIP
MOS SWITCH CHIP
DG125
9-54
INTERCHIP PAD CONNECTIONS
Siliconix
GATE
GATE
GATE
GATE
GATE
1
2
3
4
5
H
Siliconix
Burn-In Pin Connections _
III
.,
C
Burn-In Pin Conn_ections
~
-•
~
The following table lists the standard Burn-In Pin Connections for most Siliconix Integrated Circuits. Devices are listed in AlphaNumerical order according to package type. Following the tables are two examples illustrating Burn-In Pin Connections for different
switches and packages.
"n-.
~
o
Part
Type
Package
Type*
1
2
3
4
5
GND
-30 V
1131
(141
(141
(141
P/L
(7)
(7)
171
GND
171
171
Dl231
Dl25
P/L
-30 V
(141
(141
(141
(141
(141
(141
0169
P/L
-
-
9
7
Dl29
10K- 10KPin 4 Pin 3
8
6
10K+5V
Dl39
~
~
Pins
+5V +10V +5V
GND
-20V GND
DGl23
P/L
GND
GND
GND
4.7K- 4.7K- 4.7K- 4.7K- 4.7K-20V
+5V +5V +5V +5V +5V
-20V GND
DGl25
P/L
GND
GND
GND
DG126
DGl29
DGl33
DGl34
DGl39
DGl40
DG141
DG142
DGl43
DGl44
DGl45
DGl46
DG151
DGl52
DGl53
DGl54
DG161
DGl62
DGl63
DGl64
P/L
10KGND
+10V
10KGND
-
+10V
DG172
P/L
To
GND
Pin 14
GND
-
DGleo
DGlal
DGl82
DGl86
DGl87
DGl88
DG281
A
+15V
10KGND
GND
DGleo
DGlal
DGl82
DG281
P/L
+15V
10KGND
-
DGl83
DGl84
DGl85
DGl39
DGl90
DG191
DG284
DG290
P
11
12
13
14
1131
1131
10K+5V
+5V
(141
(141
(141
10KGND
10K- 10KPin 12 Pin 11
-
-
GND
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
10KGND
10KGND
+10V GND
GND
+10V -20V GND
-20V GND
+5V
+5V
+5V
+5V
GND
+5V
To 7.5KPin 14 -20V
-15V GND
10KGND
+15V
-
-
10K+15V
GND
+15 V +5V
-
10
GND
GND
+15V +5V
GND
-15V GND
15
16
17
18
.
CD
'"o_.
~
fit
+10V
1m
10KGND
-
10K10K-15V -15V
GND
GND
-
10K+15V GND
GND
+15V +5V
GND
-15V GND
+15V
Parentheses indicate direct connection to indicated pin i.e .• f2)=connect to pin 2; All voltages ±5%.
·Package types: P=AII Dual-In-Line Packages. L=AII Flat Packages, A=Alll0-Lead TO-59, R=28 Pin Dual-In-Line Packages.
Silicanix
10-1
fit
C
-."..
o
Burn-In Pin Connections (Continued)
G»
C
C
o
u
c
--D.
-..c•
C
~
III
Part
Type
DGI83
DGI84
DGI86
DG186
DGI87
DGI89
Package
Type'
Pin.
1
2
6
4
3
6
7
8
9
P/L
L
DG200
A
DG200A
P/L
DG201
DG201A
P/L
-15V
10K- 10K+15V GND
GND GND
+15V +5V
GND
-15V GND
10K+15V
GND
+15V +15V GND
(91
(91
-15V
-
(91
+15V
-
GND
-
(101
(101
-15V
-
+i5V
tiS;
(15/
-1611 GND
(151
(15/
P
+15V
(151
(151
A
(9)
19)
GND
-
GND
-15V GND
DG300
DG300A
DG301
DG301A
DG302
DG302A
DG303
DG303A
DG304
DG304A
DG305
DG305A
DG306
DG305A
DG307
DG307A
P/L
-
(13)
(131
(13)
(13)
GND
GND
-15V GND
DG308
DG308A
P
+15V
(151
(151
-15V GND
(151
(151
+15V +15V
+10V
(12)
(12)
(121
(12)
4
(281
5
6
(281
(281
7
(281
8
(281
See DG181
AlP
See DGI84
AlP
See DGI87
AlP
See DGI90
P/L
(151
+15V +15V
DG211
AlP
-15V GND
(101
DG300
DG300A
DG301
DG301 A
DG304
DG304A
DG305
DG305A
DG501
DG503
SI3705
11
12
1151
+15V +15V
(9)
+15V
14
15
18
17
-
+15V
-
+15V
(151
(15/
-
+15V
(151
101<- +15V
(151
10KGND
(151
1151
+5V +15V
(131
(13)
(13)
(151
(151
-
(121
(121
(12)
-10V -15V (16)
9
(28)
10
(28)
11
(28)
12
GND
26
27
(261
-15V
(41
(41
1
+15V
2
(281
-
GND
GND
GND
GND
1261
(281
(281
(281
(28)
(28)
(26)
3
R
DG506
DG508A
P/L
GND
GND
-15V
1121
(12)
(12)
(12)
(12)
(12)
(121
(121
DG509
DG509A
P/L
GND
GND
-15V
1131
1131
(13)
1131
(13)
(13)
1131
1131
-
17 '
-18 - 19- - 20 - -21
Parentheses Indicate direct connection to indicated pin i.e•• (2)
- -23 - 24- - 2622
=connect to pin 2; All voltages
GND
+15V
10K+15V
GND
(16)
- 16 - -18
10K- 10K-15V
GND GND
10KGND
DG506
DG506A
DG507
DG507A
-
(13)
± 5%.
Silicanix
10K+15V
GND
+15V
13
--
(15)
10K+15V
GND
(16)
GND
14
GND
- 26 - -
28 Pins
10KGND
10K+15V GND
GND
·Package types: P=AII Dual-ln-L1ne Packages, L=AII Flat Packages, A=AII fO-Lead TO-5a. R =28 Pin Dual-tn-Line Packages.
10-2
13
L
DGI89
DG190
DG191
DG284
DG290
DG381
DG381A
DG384
DG384A
DG387
DG387A
DG390
DG390A
10
GND
GND
10K+15V GND
GND
GND
16
III
.,
C
:s
•
:s
Burn-In Pin Connections (Continued)
Part
Type
Pins
Package
Type-
1
2
3
4
5
6
7
8
9
10
11
12
DG528
P
GND
GND
GND
-15 V
113)
1131
113)
1131
1131
1131
1131
1131
DG529
P
GND
GND
GND
-15 V
114)
114)
114)
1141
1141
114)
114)
1141
-
10K-
DG5040
DG5041
DG5042
DG5043
DG5044
DG5045
-
13
14
10K+15V
GND
114)
15
16
17
18
GND
GND
GND
GND
GND
GND
GND
10K+15V
GND
"n:s-.
o
:s
:s
CD
P
10KGND
GND
-15V -15 V
DF320
P/J
33Q
to5V
4.7kQ
t05V
4.7kQ
to5V
10kQ
to 5V
141
DF328
P/J
33Q
to 5V
4.7kQ
t05V
4.7kQ
t05V
10kQ
t05V
14)
10KGND
141
-
10KGND
GND
+15V +5V
10kQ 33kQ 4.7kQ
4.7kQ
GND
to GN[ t05V to GNC
to GND
10kQ 33kQ 4.7kQ
o GNC t05V to GN[
GND
4.7kQ
to GN[
110)
GND
-15V
GND
+15V
111)
111)
1111
111)
1111
110)
110)
110)
1101
110)
1161
10k+10V
G115
P/L
1161
-15 V -15V -15 V -15 V -15 V -15V
1161
1161
116)
116)
116)
116)
1161
G116
P/L
1141
-15V -15V -15V -15V -15 V -15V
1141
1141
114)
114)
114)
114)
10K+10 V
G118
P/L
114)
1141
114)
114)
114)
114)
114)
10K+10 V
G119
P/L
1141
114)
1141
1141
114)
114)
1141
114)
10K+10 V
Gl22
P/L
1141
-15V -15V -15V -15V -15V -15V
1141
1141
1141
114)
114)
1141
10K+10 V
Gl23
P/L
1141
-15V -15V -15V -15V -15V -15V
1141
1141
114)
114)
1141
114)
10K+10 V
L144
P/L
3MQ+15V
-
16)
131
GND
121
L161
P
-
-
-
-15V -15V -15 V -15V -15 V -15 V
1141
113)
-15V -15V -15V
111)
GND
GND
1141
19)
-
..._.
ft
+15V
-15V +15 V -15V +15V -15 V +15 V -15V +15V -15V
220-15 V
-
o
:s
VI
111)
1111
-
+15V
-
3MQ+15V
+15V
Parentheses indicate direct connection to indicated pin i.e .• 121-connect to pin 2; All voltages ±5%.
"Package types: P = All Dual-In-Line Packages, L = All Flat Packages, A = All lD-Lead TO-55, R:::: 28 Pin Dual-In-Line Packages.
Siliconix
10-3
lit
C
.-o
...
c"
c
o
u
.-c
Q)
Burn-In Pin Connections (Continued)
Examples of Burn-In Circuit Configurations
A.
-..
C
+15 V
+5 V
I
C
::)
a:I
,.
l___ IT J
V-
IN,
S,
'5
GND
'3
"
~-,
0,
v+
IN,
" '"
S,
9
,-4
t
, 6'
VL
'2
,
3
S3
03
r1--5
S4
•6
0,
7
8
02
~
10K
.n
10KH
lOKS"!
-15V
GND
DG190/DG191 (PACKAGE TYPE P)
+15V
GND
-15V
DG200 (PACKAGE TYPE A)
10-4
10KD:
Siliconix
.H
Silicanix
Package Data
lID
Index
PACKAGE DATA
Package
2
5
7
8
9
10
11
12
13
14
16
17
18
19
20
22
23
Letter Code .
A
L
J
J
K
K
P
P
R
J
L
L
L
J
P
J
K
Package Type
10 Lead Metal Can ................................................
14 Lead Bottom-Braze Flatpack .....................................
14 Pin Plastic Dual-In-Line .........................................
16 Pin Plastic Dual-In-Line .........................................
14 Pin Cerdip DuaHn-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16 Pin Cerdip Dual-In-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
14 Pin Side-Braze Dual-In-Line .....................................
16 Pin Side-Braze Dual-In-Line .....................................
28 Pin Side-Braze Dual-In-Line .....................................
28 Pin Plastic Dual-In-Line .........................................
14 Lead Bottom-Brace Flatpack ....................................
16 Lead Bottom-Braze Flatpack .....................................
10 Lead Bottom-Braze Flatpack .....................................
18 Pin Plastic Dual-In-Line .........................................
18 Pin Side-Braze Dual-In-Line .....................................
40 Pin Plastic Dual-In-Line .........................................
18 Pin Cerdip Dual-In-Line .........................................
Page
11-1
11-1
11-2
11-2
11-3
11-3
11-4
11-4
11-5
11-5
11-6
11-6
11-7
11-8
11-8
11-9
11-9
H
Siliconix
~
0.305
(fJ.W
(7.75)
8:WsJ ~i;~~o)l
CD
CD
MIN
f1.lfJ1
(4.19)
1
5'...
0.040
rJ.=t:;==n
(1.02)
D
MAX
!!.31.Q.
0.335
lJMQ1
(B. 51)
Lr==-'--'
10 LEADS
0.050 (.127)--1
INSULATOR
MAX
!!Jlli!. ~4B3) DIA
0.016 (.406)
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
PACKAGE 2
10 LEAD TO-l00 TYPE METAL CAN (A)
-Ir
2
1. 14
3
0.010
I
(0.25) MIN
13
t
12
4
11
5
10
6
7
~
9
8
L 1-~;~:~-L~;~:lJ
0.750
(6.10)
(6.35)
(/9.7) MIN
t
0.280 (7.11)
(6.10)
0.240
1
0.019
0.D15 TYP
(O.4B)
(0.3B)
,
TOP VIEW
0.035 (0.B9)
--0.D15 (0.3B)
L
-J
0.210
0.150
(5.33)
'I
"Jr'
D
J
l-
(3.BI)
iL
IT
0.006
0.004
(0.15)
(0.10)
I
0.085
0.070
(2.16)
(1.7B)
PACKAGE 5
14 LEAD FLATPAC (L)
(BOTTOM BRAZE)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP ANDIOR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP ANDIOR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP ANDIOR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
Siliconix
11·1
.8
D
t
G)
!!.2ZQ.
0.230
[M§1
(5.84)
CD
--.l
~B~"""~9.,....~10~'"T:"11:T"-r.:1:-::2,..-T1~3~'"T:"14":T"...
D
~
""'1-,
1
l."
TOP VIEW
~
ll.Z.Im. {J..£Jll.
~;~~
0.700 (17.8)
(.51)
mm~:
I
U
JL
t
"g:~~~
0Bl
I
I
~:~~g
,- -
I
I.L.Zf1J. TYP
TYP
(.76)
(.38)
~i~:;:!
TYP --,
TOLERANCE
NON-ACCUMULATIVE
!!cl1Q.
0.290 (7.871
(7.37)
,.---Oi~~G· g.~~-I~
PACKAGE 7
14 LEAD DUAL IN LINE PACKAGE (J)
(PLASTIC)
e
'O
11
12
13
TOP VIEW
Q.l!52.
!!..ZB5.
{J..£Jll.
0.700 (17.8)-----~1
0.020
tL2ZJ.
(.5~
J
~f,W~
~ ~ ~ ~ 1~ll ~ ~ [. I~rffr
JL~,y.J =JJ~~~lm-J
~
(.38)
I.L.Zf1J.
(.76)
TOLERANCE
NO~J-ACCUMULATIVE
PACKAGE 8
16 LEAD DUAL IN LINE PACKAGE(J)
(PLASTIC)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
11-2
Siliconix
\~
rdn
(.20)
TYP
"a
a
'"a~
ca
CD
CI
.
a
a
0.060
0.015
J
(1.52)
(0.38)
t 0.200
MAX
(5.08)
t
SEATINGt
PLANE
0.200 (5.08)
0.125 (3.18)
-I
Lo.023
0.014 TYP
(0.58)
(0.36)
U
0.070
0.030
(1.78) TYP
(0.76)
t
0.110 £2..Z9J. TYP
0.090 (2.29)
TOLERANCE
NON-ACCUMULATIVE
PACKAGE 9
14 LEAD DUAL IN LINE PACKAGE (K)
(CERDIP)
---r
0.310
0.220
il ~~~~
Lr-r--r--r-'--'-'-"T""'T'"-r-T~r--r-T"T~-I~
C
10
11
1 : : j 116
5
0.060
0.015
(1.52)
0.840 (21.34) MAX
J
(0.38)
tr=or==!r==t-r~-r~LJ==~r=~~d
't
0.200 MAX
(5.08)
-F---'--+~ SEATING
PLANE
-IL~
0.014 TYP
(0.58)
(0.38)
0.070
0.030
I
-l
(1.78) TYP
(0.76)
TOLERANCE
NON-ACCUMULATIVE
lID
PACKAGE 10
16 LEAD DUAL IN LINE PACKAGE (K)
(CERDIP)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSIONI ON TOP OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
Siliconix
11-3
PACKAGE 11
14 LEAD DUAL IN LINE PACKAGE (P)
(SIDE BRAZE)
7
8
6
5
4
3
2
1,~~~L
0.275
11.811
9
10
11
I
12
14
13
15
~)
16
I
TOPVIEW
0.050
1-._------,o~.8~3~0 l21JJ.-------l. 0020
0.740 118.8)
li.211
1.511
m-1'T'IT"""""'IF~:;r:::rr==;rii==ii=IF:::;r::n::::n;-j:;J~
li li li li lUI li li
.
jL
J
~ TYP
0.070
0.040
11.181 TYP
(.38)
(1.02)
_
li~
J l
I
::~~~t'
"OO"M,
:
I--,.",
Wl"':j
0.008 1.20)
0.11012.19I TyP
0.090 12.291
TOLERANCE
NON-ACCUMULATIVE
PACKAGE 12
16 LEAD DUAL IN LINE PACKAGE (P)
(SIDE BRAZE)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND)OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BODOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
11-4
P91111
Siliconix
0.320 18.131
0.290 11.31)
-~
14
13
12
l
"D
~
11
10
9
8
7
6
5
4
3
2
1
J"
1
~
a::a
!l.§l!D.
CD
0.568
..
l1.5..W.
15
16
17
19
18
20
21
22
23
24
25
26
27
28
C
D
D
I~-.-------------------------~~-----------------------I~
~
~
~
~
~
~
~
~~rn
~
~
~
~
~
~
(J,,@
~i~~
VVVVVvJUl v v v v v v V~ I ~ ifil~G "
j l~
j LaJN
I
II
i-!!.211.{';1..1l
0.008 (.20)
aIm
Mm
~
TYP
1.38)
~------~ g~~~
TYP
~ TYP
~~~~~~~~E
1.76)
NON-ACCUMULATIVE
'I
--J
PACKAGE 13
28 LEAD DUAL IN LINE PACKAGE (R)
(SIDE BRAZE)
-1
0.560
0.530
(1422)
~~-r.~~~~~~~rT~~~~rT~~~~rT~~~ 'l~
:::_________________~--::-~-~-~-;~-~-~;-~-~-~-~-~-~-~-~_~_~:...;II:::: ~~:
J~
I
--ii~~
TVP
-
_~.~~~TVP
--O.1QO(2.S4JTVP
~~~~~~~~~ULATIVE
-j--I~~~~~
I (3;)~:~kNG
0.150
t \
'----------
0.100 (2.541
=
!
~~OTVP_I ----~::~~ ~;!~~~~J-
(0.58) TVP
~
(0.33)
(0.20)
l1li
(030)
PACKAGE 14
28 LEAD DUAL IN-LINE PACKAGE (J)
(PLASTIC)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (I NK OR IMPRESSION) ON TOP AND/OR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP ANOIOR BOTTOM
Siliconix
11-5
..,.,
Q
0.019 (0.48)
0.015 (0.38)
.,
CD
D)
y
~
u
:.
=li
t
1
2
14
13
3
12
4
11
~
5
6
7
10
9
8
=f~
0'·'"
"."'1
0.270 (6.86)
0.390
-1-"'" ""I 0.250 (6.35)
0.750 (19.05)
MIN
E
(9.91) MAX
0.050 (1.21)
TYP
0.025
0.01U
(0.64)
(0.38)
=t
J
t
0.006
O. iOG (2.54)
0.075 (1.91)
(0. i 5)
0.004 (0.10)
PACKAGE 16
14 LEAD FLATPAC (L)
(BOTTOM BRAZE)
.
0.019 (0.48)
0.015 (0.38)
-
1
16
2
15
3
14
4
13
5
12
6
11
7
10
9
8
~l
---1.
t
(1.62) __
0.260 (6.60)
I
0.250 (6.35)
0.750 (19.05)
MIN
L
---1
0.050 TYP
(1.21)
1__ 0.370 (9.40) _
1_ 0.300
FJ
0.200 (5.08)1_
0.180 (4.51)
0.025
0.D15
(0.64)
!
t
(0.3U
=t
0.006 (0. 15)
0.004 (0.10)
PACKAGE 17
16 LEAD FLATPAC (L)
(BOTTOM BRAZE)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP AND/OR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
11·6
0.44o
(11.1 8)' MAX
Siliconix
t
0.100 (2.54)
0.075 (1.91)
"a
a
n
~
a
co
CD
..
c
a
a
0.050 TYP
(1.27)
C:::::=========It'~1
I
-
:~ ~~.~
I
0.290 (7.37)
0.370 (9.40)
0.250 (6.35)---- 0.250 (6.35) -
1 - - - - - - - - - - 0 . 7 5 0 (19.05)--------~1
MIN
0.019 (0.48)
0.015 (0.38)
0.025
0.015
(0.611
I
1=====1--- ----~(O·r~
I
-
0.190 (4.83) I
I0.160
(4.06)-
0.006 (0.15)
0.004 (0. 10)
t
0.100 (2.54)
0.075 (1.91)
PACKAGE 18
10 LEAD FLATPAC (L)
(BOTTOM BRAZE)
l1li
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP AND/OR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
Siliconix
11-7
a
•a
-----r-
Q
0.280
0.220
(7.11)
(5.59)
CD
m
a
.~~~~~~~~~~~~~
~
o
~
:."
11
12
13
14
TOP VIEW
1~16
17
18
0.020
(.51)
MIN
0.925 MAX
(23.50)
-1-:-+
~.200MAX
PLANE
II
-, r
(2.54)
MIN
0.023
0.015 TVP - ,
0.070
0.030 TVP
(0.58)
(0.38)
(1.78)
(0.76)
I
--l
0.110 (2.79)
!--0.090 (2.29) TYP
~
I/
I
_ /
TOLERANCE
7
TVP
NON·ACCUMULATIVE
0.015j\0.008
(.38)
PACKAGE 19
18 LEAD DUAL IN·LlNE PACKAGE (J)
(PLASTIC)
~
.----.
9
8
.----.
7
~
.---.
.---.
.----.
6
5
4
3
~
2
(.20)
.---.
1
(
10
I.~
11
12
13
14
15
16
17
18
'--'
TOP VIEW
.
..
0.925 (23.50)
0875 (2223)
0.050
0.020
(1.27)
(O'l~
~-~ :::::~i~~F,G
JL
J ~- ~:~~~ ~:~~~--t
0.200 (5.08)
f
o:12s
II
~
(3.18)
f
0.023
0.070 _
0.110
0.015
0.040
0.090
(0.58) TVP
(1.78) TVP
(2.79) TVP
(0.38)
(1.02)
(2.29)
(1.65)
(0.51)
PACKAGE 20
18 LEAD DUAL IN·LlNE PACKAGE (P)
(SIZE BRAZE)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP AND/OR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
11·8
Siliconix
(0.30;
(0.20)
TVP
0.320 (8.13)
0.290 (1.37)-
~:~~: ~:~~:;
----------1
""
D
~
D
CD
CD
"
0.570
0.520
17448/
Ie
...
LfTT"~rT~~TT~~~~~~~~rT~~~~~~~M~
~~::~
0.210
0.060 TVP
iT9ij
j ~IL
D.'2D
-------rr -0.020
-
t
0 630
~OO:~ TVP ;~ ~~;
t
~~5" TVP
-J I
(7600/-.1
i.58O;T4'13J
I~
(381)
f30~
- II o.io SEATlNGPLANE
I
" 52):0 TVP
NON·ACCUMULATIVE
o 100
D.07s
(254)
(406) 0.150
I
r---------,-
0.100 (2541
(203/
7152i
(533)
'il.1'6o
I~TOLERANCETYP
D
D
-I
,
OO'OTVP
(025)
I-
ft 02)
PACKAGE 22
40 LEAD DUAL IN·LlNE PACKAGE (J)
(PLASTIC)
C
O
11
12
1~17
18
INDEX MAY BE PARTIALLY
13
TOP VIEW
FILLED WITH GLASS
0.060
0.015
(1.52)
0.960 (24.38) MAX
(0.38)
.------------,Ji~AX
U U UlUi U U U U u_
II
0.023
0.070
(0.36)
(0. 76)
~~~~~TYP
I
~~~TYP ~
I
"I"
"J
0.110 (2.79) TYP
r-~~~~R~~~~
/
'I
NON·ACCUMULATIVE
(0.38)
(0.20)
lID
PACKAGE 23
18 LEAD DUAL IN·LlNE PACKAGE (K)
(CERDIP)
PIN 1 INDEX IS ONE OR MORE OF THE FOLLOWING
• DOT (INK OR IMPRESSION) ON TOP AND/OR BOTTOM OF PACKAGE
• NOTCH OR HOLE IN PIN 1 VISIBLE FROM TOP AND/OR SIDE
• NOTCH IN END OF PACKAGE VISIBLE FROM TOP AND/OR BOTTOM
ALL DIMENSIONS IN INCHES
(ALL DIMENSIONS IN MILLIMETERS)
Siliconix
11·9
H
Silicanix
Appendices
lID
Index
APPENDICES
Title
Page
Publications Index ............................................................................ 12-1
Glossary of Terms and Abbreviations ..........•................................................. 12-3
Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-5
"'a
C
-_.
cr
ft
-.o...
D
Publications Index
Catalog Document
(See Key) Number
Catalog Document
(See Key) Number
Title
Application Notes
AN70·1
F
AN70·2
AN71·1
F
A
F
A
AN72·1
AN72·2
AN73·1
AN73·2
A
AN73·3
AN73·4
A
• AN73·5
AIC
AN73·6
F, A
AIC
• AN73·7
• AN74·1
A
AN74·2
AN74·3
F
• AN74·4
A
• AN75·1
AN76·1
VA
• AN76·3
A
• AN76·6
AIC
• AN76·7
AIC
• AN77·1
VA
• AN77·2
VA
• AN79·1
VA
• AN79·3
VA
• AN79·4
AN79·5
VA
• AN79·6
AN79·7
FET Cascode Circuits Reduce
Feedback Capacitance
FETs for Video Amplifiers
A High Resolution CMRR Test
Method
FETs in Balanced Mixers
FETs as Analog Switches
FETs as Voltage·Controlied Resistors
IC Multiplexer Increases Analog
Switching Speeds
Switching High·Frequency Signals
With FET Integrated Circuits
Junction FETs in Active Double·
Balanced Mixers
Driver Circuits for the JFET Analog
Switch
Function/Application of the l144
Programmable Micro·Power Triple
Op Amp
An Introduction to FETs
Function/Application of the lD110/
lD111 3V2 Digit A/D Converter Set
Analog Switches in Sample and Hold
Circuits
Designing Junction FET Input
Op Amps
Audio·Frequency Noise
Characteristics of Junction FETs
CMOS Analog Switches-A Powerful
Design Tool
Measuring High Frequency
S·Parameters on the Dual Gate
MOSFET
VMOS-A Breakthrough in Power
MOSFET Technology
DG300 Series Analog Switch
Applications
Function/Application of the l161
Micropower Comparator
Function/Application of the lD120/
lD121 4 Vz Digit A/D Converter Set in
Measurement Systems
Don't Trade Off Analog Switch
Specs. VMOS-A Solution to High
Speed, High Current, low Resistance
Analog Switches
A 500 KHz Switching Inverter for
12 V Systems
Dynamic Input Characteristics of a
VMOS Power Switch
Driving VMOS Power FETs
Using the VN64GA High Current,
High Power VMOS Power FET
Using VMOS Transistors to Interface
from IC logic to High Power loads
Applications of the VN10KM VMOS
Power FET
VA
• AN80·1
VA
AN80·2
AN80·3
AN80·4
• AN80·5
VA
AN80·6
AIC
AN80·8
AIC
AN81·1
AIC
F
AN81·2
• AN81·3
AIC
• DA77·2
~
VI
Title
A Key to the Advance of Switching
Power Supplies
Meet the VMOS FET Model
Ultralinear Broadband Amplifier
Enjoy VHF Power Amplifier Design
An Alternative Power Amplifier
Design
AGC for the VMOS RF Power
Amplifier
Function/Application of the
lD122/lD121A ±4Vz Digit A/D
Converter Set in Measurement
Systems
Microprocessor Interface Techniques
As Applied to the Siliconix A/D
Converter Family
Introduction to Quantized Feedback
Composite Op Amp for High
Performance
Design Aids
DA78·4
VA
• DA80·1
DA81·1
DA81·2
Design Aid of the lD120/lD121 4Vz
Digit DVM
Build a Smoke Detector With the
SM110lC
A low Cost Regulator for
Microprocessor Applications
logic Interfacing Made Easy with the
DG308
logic Interfacing Made Easy with the
DG308
Design Ideas
F
• D171·1
D171·4
DI71·5
DI71·6
D171·8
F
D171·9
F
• D173·2
D180·1
The FET Constant Current Source
Wideband Mixer·Preamplifier Using
FETs
A FET Frequency Doubler
Using FETs in Selective VHF
Amplifiers
Using JFETs in Ultra·Wideband UHF
Amplifiers
Wideband UHF Amplifier with High
Performance FETs
High Performance FETs in low·Noise
VHF Oscillators
A 5 Watt, Parallel·Mode Crystal
Oscillator
Technical Articles
TA70·1
F
A
• TA70·2
• TA73·1
A
TA73·2
Siliconix
TA76·1
lID
High Frequency Junction FET
Characterization and Application
FET Biasing
Multiplexer Adds Efficiency to
32·Channel Telephone System
Designing with Monolithic FET
Switches
VMOS Power FETs in Your Next
Broadband Driver
12·1
"
H
CD
."
C
-
Siliconix
1ft
-.
C
o
Publications Index (Cont'd)
IS
--"
.D
::t
Catalog Document
(See Key) Number
tiL
TA76-2
VA
* TA78-2
Title
Title
A New Technology: Application of
VMOS Power FETs for High
Frequency Communications
Designing a VMOS 250 Watt Off-Line
Inverter
Catalogs
Analog Switch & IC Product Data Book
Analog Switches and Their Applications ($7.95
charge)
FET Design Catalog
VMOS Power FETs Design Catalog
VMOS Power FETs Applications Handbook
OEM Pricing with Cross Reference
RF Power FET Short Form Catalog
Siliconix Short Form Selector Guide
Key
Catalogs
F = FET Design Catalog
AIC= Analog Switch &
IC Product Data
VA VMOS Applications
Book
Handbook
A Analog Switches and
Their Applications
Reprints & Reports
• Siliconix, Inc_ Annual Report.
• Designing a VMOS 250 Watt Off-Line Inverter_
David C. Hoffman, Powercon 3/78
• Designing with CODECs: Know Your A's and p.'s.
Thomas J. Mroz, EON 5176
• Log Data under p. Control. Gary Grandbois,
Electronic Design 5/76
• Higher Power Ratings Extend VMOS FETs'
DOfninion. Arthur D. Evans, David C. Hoifman,
Edwin S. Oxner, Walter Heinzer and Lee Shaeffer.
Electronics 6/78
• CODEC has On-Chip Signaling for Phone
Applications, Walter Heinzer and Steve Bolger,
Electronics 6/7179
• A Microprocessor Controlled VMOS Power
Supply, David C. Hoffman
• Control Analog Signals with Voltage, Stephen
Moore, Electronic DeSign, 1978
• Exploit VMOS FETs' Advantages to Drive Bipolar
Power Transistors, F. Michael Barlage, Powercon
5/78
• Rely on IC Analog Switches for Fast Small-Signal
Control, EON, August 5, 20, Sept. 5, 1980
• Composite Op Amp Outperforms FET-Input ICs,
EON, May 27,1981.
=
=
* Available In bound catalog only.
12-2
Siliconix
Book
Designing with Field-Effect Transistors, Edited by
Arthur D. Evans_ Available at your technical
bookstore or write to Suite 26-1; McGraw HIli
Book Co.; 1221 Avenue of the Americas; New
York, NY 10020.
-
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fit
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Glossary of Terms and Abbreviations
3
a
fit
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D.
J>
cr
cr
Av
-
DC Closed Loop Voltage Gain
10L
-
AVOL
AZIN
-
DC Open Loop Voltage Gain
los
IR
-
Reference Supply Current
AZOUT
BCD
- Auto-Zero Amplifier Output
- Binary Coded Decimal
IRH
-
IRL
-
Integrator Capacitance
Is
-
Reference Supply Current, Input Voltage
High
Reference Supply Current, Input Voltage
Low
Supply Current or FET Source Current
- Output Short Circuit Current
- Source OFF Leakage Current
- Auto-Zero Amplifier Input
Bn
-
CAZ
C INT
- Auto-Zero Storage Capacitance
-
BCD Data Bit Outputs
Output Current, Output Voltage Low
Input Offset Current
CL
CMR
-
Load Capacitance
Common Mode Range
Isc
ISlolfl
CMRR
-
Common Mode Rejection Ratio
Iss
I,
-
Source Supply Current
-
Positive Supply Current
-
Negative Supply Current
-
Positive Supply Current
-
Negative Supply Current
COMP
- Analog Comparator Output
Cosc
C STRG
-
Dn
EOC
-
Digit Strobe Outputs
12
1+
1-
-
End of Conversion Signal
LSB
-
Least Significant Bit
-
Most Significant Bit
Oscillator Capacitance
- Auto-Zero Storage Capacitance
fCLK
fiN
-
Clock Frequency
MSB
-
Clock Input Frequency
MIZ
-
Measure-Zero Logic Output
fL
-
Line Frequency
NC
-
Resonant Frequency
NMR
-
No Connection
Normal Mode Rejection at Input
-
Full Scale
Gain at the Resonant Frequency
OC
-
Open Collector Logic
OF
-
Overflow Logic Output Pulse
- Overrange Logic Output Pulse
fo
FS
Ho
ISlAS
ICL
IDD
liN
-
Input Bias Current
OR
-
Clock Input Current, Clock Voltage Low
P
-
Drain Supply Current
Input Current
Po
P-P
-
Peak to Peak
IINH
-
Logic Input Current, Input Voltage High
PSRR
-
Power Supply Rejection Rate
IINL
INT IN
-
Logic Input Current, Input Voltage Low
Q
-
Quality Factory
-
Integrator Summing Node (Input)
rDSlon)
INT OUT
-
Integrator Amplifier Output
- ON Resistance of FET Switch
- Drain-Source ON Resistance
(D.C. measurement)
10
-
Output Current
-
Reference Output Voltage
-
Output Current, Output Voltage High
REF out
10H
Rin
-
Input Resistance
Siliconix
.,
CD
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fit
Pull-Up Gate
Power Dissipation
12-3
UI
..-C
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Glossary of Terms and Abbreviations
(Cont'd)
~
cC
"'a
C
a
UI
E
a.
I-
RL
-
Load Resistance
V GO
-
Gate-Drain Voltage
Rs
-
Input Source Resistance
V GS
-
Gate-Source Voltage
RSET
S
SCAN
-
Set Current Resistance
VGS(offl
-
Gate-Source Pinchoff Voltage
-
Source
Sequential/Interlace Digit Scan Logic Input
VGS(thl
V H1 _Q
-
Gate-Source Threshold Voltage
High Quality Ground Input Voltage
- Slew Rate
- Ambient Temeprature
V 1N
-
Input Voltage
V INH
-
Logic Input Voltage, High
- Temperature Coefficient
V INL
-
Logic Input Voltage, Low
~
SR
...
TA
TC
C
toff
- Turn-Off Time
VL
-
Logic Supply Voltage
~
tofflEnl
ton
-
-
Output Voltage
- Turn-On Time
Vo
V OH
-
Output Voltage, High
toni En)
t open
t,
-
Enable Turn-On Time
VOL
-
Output Voltage, Low
-
Break-Before-Make Interval
-
Input Offset Voltage
ttransition
-
Response Time
Switching Time of Multiplexer
Vos
V OUT
Vp
-
U/D
-
Up/Down Logic Output
V PB
-
Pull-Up Gate to Body Voltage
UR
-
Underrange Logic Output Pulse
VR
-
Reference Voltage
VA
V AH
- Address Input Voltage
V REF
VAL
V AZ
- Address Input Voltage, Low
- Auto-Zero Amplifier Output Voltage
Vs
V SB
- Threshold Reference Voltage
- Positive Reference Voltage
- Source Supply Voltage
-
Source-Body Voltage
V AZlin )
- Auto-Zero Switch Input Voltage
Vss
-
VB
-
Source Supply Voltage; Positive for PMOS,
Negative for NMOS and CMOS
- Auto-Zero Loop Storage Voltage
Drain-Body Voltage
V STRG
V1
V2
Drain Supply Voltage; Negative for PMOS,
Positive for NMOS and CMOS
a
UI
UI
o
-o
- Address Input Voltage, High
VCLOCK IN Vo
Voa
Voo
12-4
Enable Turn-Off Time
-
- Output Voltage Swing
Body Voltage
Clock Logic Input Voltage
Drain Voltage
Pull-Up Gate Voltage
-
Positive Supply Voltage
-
Negative Supply voltage
V+
V-
-
Positive Supply Voltage
-
Negative Supply Voltage
V En
-
Enable Input Voltage
ZIN
-
Input Impedance
VG
V GB
-
Gate Voltage
drOSlon)
-
-
Gate-Body Voltage
Fractional Change in Drain-Source ON
Resistance (D.C. measurement)
Siliconix
u.s. Sales Offices
Eastern
Central
Silicon Ix Incorporated
31 Bailey Avenue
Ridgefield, CT 06877
(203) 431-3535
Siliconix Incorporated
1327 Butterfield Rd" Suite 620
Downers Grove, IL 60515
(312) 960-0106/07/08
Twx: 910-695-3232
Siliconix Incorporated
395 Totten Pond Rd.
Waltham, MA 02154
(617) 890-7180
Twx: 710-324-1783
Siliconix Incorporated
Two King James South, Suite 143
24650 Center Ridge Road
Westlake, OH 44145
(216) 835-4470
Siliconix Incorporated
P.O. Box 487
(403 E. Wall)
Grapevine, TX 76051
(817) 481-5815/6
Northwestern
Southwestern
Siliconix Incorporated
1525 E. 17th SI., Suite L
Santa Ana, CA 92701
(714) 547-4474
Twx: 910-595-2643
Siliconix Incorporated
2201 Laurelwood Rd.
Santa Clara, CA 95054
(408) 988-8000
Twx: 910-338-0227
u.S. Sales Representatives
ALABAMA, Huntsville (358031
Rep. Inc.
11527 S. Memorial Pkwy.
(205) 881-9270
Twx: 810-726-2102
ARIZONA, Tempe (B52811
Quatra Associates, Inc.
1801 S. Jen Tilly
Suite C-14
(602) 894-2808
Twx: 910-950-1153
CALIFORNIA. Cupertino (950t41
Costar Incorporated
10080 North Wolfe Rd., Suite SW3-175
(408) 446-9339
Twx: 910-338-0206
CALIFORNIA. Fountain Valley (9270BI
Bager Electronics Inc.
17220 Newhope SI., #211
(714)957-3367
(213)433-1687
COLORADO, Englewood (801121
Delta Sales Assoc.
Bldg. 8 - Penthouse F
14 Inverness Dr. E.
(303) 741-0646
Twx: 910-935-0717
CONNECTICUT. Rldgafleld (06B771
Phoenix Sales Company
389 Main Street
(203) 438-9644
Twx: 710-467-0662
FLORIDA. Largo (335401
Perrott Associates
511 Rosery Rd. NE
(813)585-3327
Twx: 810-866-0328
FLORIDA. Orlando (32807)
Perrott Associates
1607 Forsyth Road
(305)275-1132
Twx: 810-850-0103
FLORIDA, Sunrise (33313)
Perrott Associates
5975 W. Sunrise Blvd., Suite 212
(305)792-2211
Twx: 510-955-9831
GEORGIA. Norcross (306921
Montgomery Marketing
3640 Peachtree Corner W., #303
(404)447-6124
ILLINOIS, Del Plaines (600181
Electron Marketing Corp.
3166 Des Plaines Ave.
Suite 35
(312)298-2330
INDIANA, Carmel (46D321
Wilson Technical Sales Inc.
597 Industrial Drive
(317) 844-5977
IOWA. Cedar Rapids (52402)
Technical Reps Inc.
1930 SI. Andrews Dr. N.E.
(319)393-1300
Twx: 910-525-1351
KANSAS. Wichita (67206)
Technical Reps Inc.
360 No. Rock Rd., #4
(316)681-0242
MARYLAND, Baltimore (2120BI
Pro Rep
107 Sud brook Lane
(301 )653-3600
Twx: 710-862-0862
MASSACHUSETTS, Reading (01 B671
Kanan Associates
270 Main Street
(617)944-8484
Twx: 710-393-6552
MICHIGAN. Brighton (48116)
A.P.J. Associates
P.O. Box 777
9880 E. Grand River Ave.
(313)229-6550
Twx: 810-242-1510
NEW JERSEY, Teaneck (076661
R.T. Reid Associates
705 Cedar Lane
(201)692-0200
Twx: 710-990-5086
TEXAS, Grapevine (760511
Electronics Marketing Assoc.
P.O. Box 487
(403 E. Wall)
(817)481-7502 or 7503
NEW YORK. Endwell (13760)
Tri-Tech Electronics
3215 E. Main SI.
(607)754-1094
Twx: 510-252-0891
TEXAS. Houston (770421
Electronics Marketing Assoc.
P.O. Box 42388
11450 Dissonnet, #309
(713)498-8120
NEW YORK. Fairport (144501
Tri-Tech Electronics
590 Perinton Hills Office Park
(716)223-5720
Twx: 510-253-6356
VIRGINIA. Charlottesville (22901 I
Pro Rep
1616 Inglewood Dr.
(804)997-0031
Twx: 710-236-9011
NEW YORK. Fayetteville (130661
Tri-Tech Electronics
6836 E. Genesee SI.
(315)446-2881
Twx: 710-541-0604
WASHINGTON. Seattle (981071
Blair Hirsh Co., Inc.
4013 Leary Way NW
(206)783-3423
NEW YORK. Poughkeepsie (126031
Tri-Tech Electronics
19 Davis Ave.
(914)473-3880
WISCONSIN. Milwaukee (53227)
JM Sales
9431 W. Beloit Rd., 1/119
(414)546-0040
Twx: 910-651'5977
NORTH CAROLINA. Cary (275111
Montgomery Marketing
P.O. B. 520 (1391 N. Harrison Ave.)
(919)467-6319
Twx: 510-920-0634
CANADA
MINNESOTA. Burnsville (553371
Electromec Sales Inc.
101 W. Burnsville Pkwy.
(612) 894-8200
Twx: 910-576-0232
OHIO, Cleveland (441431
Arthur H. Baier Company
67 Alpha Park
(216)461-6161
Twx: 810-427-9278
ONTARIO. Etoblcoke (M9C lE71
R.F.O. Ltd.
385 The West Mall, Suite 251
(416)626-1445
Twx: 610-492-2540
MISSOURI. Earth City (630451
Technical Reps Inc.
502 Earth City Plaza, #201
(314)291-0001
Twx: 910-762-0685
OHIO. Dayton (454141
Arthur H. Baier Company
4940 Profit Way
(513)276-4128
ONTARIO. Ottawa (K2B 7E91
A.F.Q. Ltd.
2249 Carling Ave., #204
(613)820-8445 or 820-8446
MISSOURI, Kansas City (6411 II
Technical Reps Inc.
406 W. 34th, #616 VFW Bldg.
(816)756-3575
Twx: 910-749-6412
NEBRASKA. lincoln (68507)
Technical Reps Inc.
2332 No. Cotner, Suite 0-12
(402) 486-3488
NEW JERSEY. Marlton (080531
B.G.A. Associates
3001 Greentree Exec. Campus
(609)428-2440
Twx: 510-665-5685
OREGON. Beaverton (970051
Blair Hirsh Co., Inc.
9645 S.W. Beaverton Hwy.
(503)641-1875
TENNESSEE. Jellerson City (37760)
Rep Inc.
P.O. B. 287 (113 So. Branner Ave.)
(615)475-4105
Twx: 810-57()'4203
TEXAS, Austin (787531
Electronics Marketing Assoc.
607 A Deen Avenue
(512)837-0893
Siliconix
U.S. CHIP
DISTRIBUTORS
FLORIDA. Orlando (328071
Chip Supply Inc.
1607 Forsyth Road
(305)275-3810
Twx: 810-850-0103
lEI
PENNSYLVANIA. Malvern (193351
Hybrid Die Technology
111 Great Valley Pkway.
(215)296-5905
Twx: 510-668-6123
12-5
VI
G)
--u
~
VI
G)
-en
D
U.S. Distributors
ALABAMA. Huntsville (35805)
CALIFORNIA. Tustin (92680)
INDIANA. Carmel (46032)
MICHIGAN. Livonia (48150)
Hamilton/Avnet
4692 Commercial Drive
(205)837-7210
Twx: 810-n6-2162
Anthem Electronits. Inc.
2661 DoYi Ave.
(714)730-8000
Twx: 910-595-1585
Hamilton/Avnet
485 Gradle Drive
(3! 7)844-9333
Twx: 810-260-3966
Hamilton/Avnet
32487 Schoolcraft
(313)522-4700
Twx: 810-242-8775
ALABAMA. Huntsville (35805)
COLORADO. Englewood (80111)
INDIANA. IndianapoliS (46250)
MICHIGAN. Livonia (48150)
Pioneer/Huntsville
1207 Putman Dr. NW
(205)837-9300
Twx: 810-n6-2197
Hamilton/ Avnet
8765 E. Orchard Rd., Suite 708
(303)740-1000
Twx: 910-931-0510
Pioneer /Indiana
6408 Castle place Drive
(317)849-7300
Twx: 810-260-1794
Pioneer /Michigan
13485 Stamford
(313)525-1800
Twx: 810-242-3271
ARIZONA, Scottsdale (85253)
COLORADO. Thornton (80241)
KANSAS. Merrlan (66202)
MINNESOTA, Minneapolis (55435)
Components Plus
7500 E. Butherus, Ste. T
(602)991-6510
Twx: 910-950-1184
Wyle Distribution Group
451 E. 124th Ave.
(303)457-9953
Twx: 910-936-0770
Components Plus
8015 W. 63rd SI., Ste. 1
(913)236-8555
Industrial Components
5229 Edina Industrial Blvd.
(612)831-2666
Twx: 910-576-3153
ARIZONA, Tempe (85281)
COLORADO, Wheatrldge (80033)
Hamilton/Avnet
505 South Madison Dr.
(602)894-9600
Twx: 910-950-0077
Bell Industries
8155 W. 48th Ave.
(303)424-1985
Twx: 910-938-0393
Hamilton/Avnet
9219 Quivira Rd.
(913)888-8900
Twx: 910-743-0005
CALIFORNIA, Costa Mesa (92626)
CONNECTICUT, Danbury (06810)
Avnet Elec.
350 McCormick Ave.
(714)754-6111
Twx: 910-595-1928
Hamilton/ Avnet
Commerce Drive, Commerce Park
(203)797-2800
Twx: 710-460-0594
CALIFORNIA, Costa Mesa (92626)
Hamilton Electro Sales
3170 Pullman SI.
(714)641-4100
Twx: 910-595-2838
CALIFORNIA, Culver City (90230)
Hamilton Electro Sales
10912 W. Washington BI.
(213)558-2121 or (714)522-8200
Twx: 910-340-6364
CALIFORNIA. Irvine (92714)
Components Plus
17811 Skypark Circle
(714)754-0471
Twx: 910-595-2554
CALIFORNIA. San Diego (92121)
Anthem Electronics, Inc.
4125 Sorrento Valley Blvd.
(714)453-9005
Twx: 910-335-1515
CALIFORNIA. San Diego (92123)
Hamilton/ Avnet
4545 Viewridge Ave.
(714)571-5710
Twx: 910-335-1216
CALIFORNIA. Santa Clara (95052)
Wyle Distribution Group
3000 Bowers Ave.
(408)727-2500
Twx: 910-379-6480
CALIFORNIA, Sunnyvale (94086)
Bell Industries
1161 No. Fairoaks Ave.
(408)734-8570
Twx: 910-339-9378
CALIFORNIA, Sunnyvale (94086)
Components Plus
491 Macara Ave., Ste. 1006
(408)732-0990
CALIFORNIA. Sunnyvale (94086)
Hamilton/ Avnet
1175 Bordeaux
(408)743-3355
Twx: 910-339-9332
12-6
CONNECTICUT, Walllnglord (06492)
Mashall Industries
Village Lane
Barnes Industrial Park
(203)265-3822
Twx: 710-465-0747
FLORIDA, Ft. Lauderdale (33309)
Hamilton/ Avnet
6801 N.W. 15th Way
(305)971-2900
Twx: 510-995-3097
KANSAS. Overland Park (66215)
MARYLAND. Baltimore (21227)
Components Plus
4805 Benson Ave.
(301)247-3620(MD)
(202)621-2590(DC & N. VA)
(800)838-8878(S. VA)
MARYLAND, Columbia (21045)
Hamilton/Avnet
6822 Oak Hall Lane
(301)995-3500(MD)
(301)621-5410(DC)
Twx: 710-862-1861
MARYLAND. Gaithersburg (20760)
Pioneer /Washington
9100 Gaither Rd.
(301 )948-071 0
Twx: 710-828-0545
MARYLAND. Gaithersburg (20760)
FLORIDA. Orlando (32809)
Pioneer Elec.
6220 S. Orange Blossom Trail. Ste. 412
(305)859-3600
Twx: 810-850-0177
FLORIDA, SL Petersburg (33702)
Hamilton/ Avnet
3197 Tech Drive No.
(813)576-3930
Twx: 810-863-0374
Marshall Industries
16760 Oakmont Ave.
(301 )840-9450
Twx: 710-828-0223
MASSACHUSETTS. Burlington (01803)
Milgray Electronics
79 Terrace Hall Ave.
(617)2n-6800
Twx: 510-225-3673
MASSACHUSETTS. Burfington (01803)
GEORGIA, Norcross (30092)
Marshall Industries
1 Wilshire Rd.
(617)2n-8200
Twx: 710-332-6359
Hamilton/Avnet
5825 Peachtree Corners E-D
(404)447-7500
Twx: 810-766-0432
MINNESOTA, Minnetonka (55343)
Hamilton/ Avnet
10300 Bren Rd. East
(612)932-0600
Twx: 910-576-2n9
MINNESOTA, Minnetonka (55343)
Pioneer/Twin Cities
10203 Bren Rd. East
(612)935-5444
MISSOURI. Earth City (63045)
Hamilton/Avnet
13743 Shoreline CI.
(314)344-1200
Twx: 910-762-0606
NEW JERSEY. Cherry Hili (08003)
Hamilton/ Avnet
One Keystone Ave.
(609)424-0100
Twx: 710-940-0262
NEW JERSEY, Clifton (07015)
Marshall Industries
1111 Paulison Ave.
(201)340-1900
Twx: 710-989-7052
NEW JERSEY. Fairfield (07006)
Hamilton/ Avnet
10 Industrial Rd.
(201)575-3390
Twx: 710-734-4388
NEW JERSEY, Mt. Laurel (08057)
Marshall Industries
102 Gaither Dr., Unit 2
(609)234-9100 NJ (215)627-1920 PA
Twx: 710-941-1361
NEW MEXICO. Albuquerque (87123)
Alliance Electronics
MASSACHUSETTS. Framingham (01701) 11030 Cochiti S.E.
GEORGIA. Norcross (30093)
(505)293-3360
Twx: 910-989-1151
Marshall Industries
4364B Shakeiford Rd.
(404)923-5750
Cadence
14 Burr 51.
(617)879-3000
Twx: 710-380-6908
ILLINOIS, Chicago (60645)
MASSACHUSETTS, Framingham (01701) 11728 Linn NE
Bell Industries
3422 W. Touhy Ave.
(312)982-9210
Twx: 910-223-4519
ILLINOIS. Elk Grove Village (60007)
Pioneer /Chicago
1551 Carmen Drive
(312)437-9680
Twx: 910-222-1834
ILLINOIS. Schiller Park (60176)
Hamilton/Avnet
3901 N. 25th Ave.
(312)678-8310
Twx: 910-227-0060
NEW MEXICO, Albuquerque (87123)
BeJllndustries
Components Plus
14 Burr SI.
(617)237-2503
(505)292-2700
Twx: 910-989-0625
MASSACHUSETTS. Woburn (01801)
Hamilton/Avnet
2524 Baylor Dr., SE
(505)765-1500
Twx: 910-989-0614
Hamilton/Avnet
50 Tower Office Park
(617)953-9700
Twx: 710-393-0382
MICHIGAN, Grand Rapids (49508)
Hamilton/Avnet
2215-29th 51. S.E.
Space #85
(616)243-8805
Siliconix
NEW MEXICO. Albuquerque (87119)
NEW YORK. 8ullalo (14202)
Summit Distributors, tnc.
916 Main Street
(716)887-2800
Twx: 710-522-1692
CIt
u.s. Distributors (Continued)
NEW YORK. East Syracuse (13057)
NEW YORK. Rochester (14623)
Hamiltonl Avnet
1600 Corporate Circle
(315)437-2642
Twx: 710-541-1560
Marshall Industries
1260 Scottsville Rd.
(716)235-7620
Twx: 510-253-5470
OREGON. Lake Oswego (97034)
Hamiltonl Avnet
6024 SW Jean Road, Bldg. C, Ste. 10
(503)635-8836
Twx: 910-455-8179
NEW YORK, Endwell (13760)
Marshall Industries
10 Hooper Rd.
(607)754-1570
Twx: 510-252-0194
NORTH CAROLINA, Greensboro (27406)
Pioneer INC
103 Industrial Ave.
(919)273-4441
Twx: 510-925-1114
PENNSYLVANIA, Horsham (19044)
Pioneer Elec.
261 Gibraltar Rd.
(215)674-4000
Twx: 510-665-6778
NEW YORK, Freeport (11520)
Milgray Electronics, Inc.
191 Hanse Ave.
(510)225-3673
Twx: 516-546-5600
NORTH CAROLINA, Raleigh (27609)
Hamiltonl Avnet
2803 Industrial Dr.
(919)829-8030
Twx: 510-928-1836
PENNSYLVANIA, Pittsburgh (1523B)
Pioneer IPittsburgh
259 Kappa Dr.
(412)782-2300
Twx: 710-795-3122
NEW YORK. Hauppauge (117B7)
Cadence
40-4 Oser Ave.
(516)231-6722
OHIO. Cleveland (44105)
Pioneer ICleveland
4800 E. 131st Street
(216)587-3600
Twx: 810-422-2210
TEXAS. Addison (75001)
Quality Components
4257 Kellwa y Circle
(214)387-4949
Twx: 910-860-5459
OHIO, Dayton 145459)
Hamiltonl Avnet
954 Senate Dr.
(513)433-0610
Twx: 810-450-2531
TEXAS, Austin (78758)
Hamiltonl Avnet
2401 Rutland Dr.
(512)837-8911
Twx: 910-874-1319
OHIO. Dayton 145424)
Pioneer IDayton
4433 Inter point Blvd.
(513)236-9900
Twx: 810-459-1622
TEXAS. Austin 178758)
Quality Components
2427 Rutland Drive
(512)835-0220
Twx: 910-874-1377
OHIO. Warrensville Heights 144128)
Hamiltonl Avnet
4588 Emery Industrial Parkway
(216)831-3500
Twx: 810-427-9452
TEXAS. Dallas 175243)
Components Plus
13777 No. Central Expwy., Suite 502
(214)783-6060
Twx: 910-867-9414
OKLAHOMA. Tulsa (74129)
Quality Components
9934 E. 21 st St. South
(918)664-8812
TEXAS. Houston 177063)
Hamiltonl Avnet
8750 Westpark
(713)780-1771
Twx: 910-881-5523
NEW YORK. Hauppauge (11787)
Components Plus
40 Oser Ave.
(516)231-9200
Twx: 510-227-9869
NEW YORK. Hauppauge (11787)
Hamilton/Avnet
5 Hub Drive
(516)454-6000
Twx: 510-224-6166
NEW YORK. Port Chester 110573)
Zeus Components, Inc.
100 Midland Ave.
(914)937-7400
Twx: 710-567-1248
NEW YORK. Rochester (14623)
Hamilton/Avnet
333 Metro Park
(716)475-9130
Twx: 510-253-5470
-
a
CD
fit
TEXAS. Houston (77036)
Quality Components
6126 Westline
(713)772-7100
o
TEXAS, Irving (75062)
Hamiltonl Avnet
2111 W. Walnut Hill Lane
(214)659-4151
Twx: 910-860-5929
"m
=
--
UTAH, Salt Lake City (B4120)
Bell Industries
3639 West 2150 South
(801)972-6969
Twx: 910-925-5686
UTAH, Salt Lake City IB4119)
1585 West 2100 South
(801 )972-2800
Twx: 910-925-4018
WASHINGTON. Bellevue (98005)
Hamilton/Avnet
14212 NE 21st St.
(206)453-5844
Twx: 910-443-2469
WASHINGTON. Bellevue 198005)
Wyle Distribution Group
1750 - 132nd Ave. NE
(206)453-8300
Twx: 910-443-2526
WISCONSIN. Milwaukee 153214)
Marsh Electronics, Inc.
1563 So. 101st St.
(414)475-6000
Twx: 910-262-3321
WISCONSIN. New Berlin 153151)
Hamiltonl Avnet
2975 Moorland Rd.
(414)784-4510
Twx: 910-262-1182
European Distributors/Representatives
AUSTRtA
Ing. Ernst Steiner
Hummelgasse 14
A-1130 Vienna
Tel: 0222/827474
Tlx: 135026
FRANCE
Almex
48 Rue de L'Aubepine
92164 Antony Cedex
Tel: 377-07-87
Tlx: 250067
BELGtUM
Ritro Electronics BV
172 Plantin en Moretuslei
B-2000 Antwerpen-B
Tel: 031-353272
Tlx: 33637
Alrodis
40 Rue Villon
69008 Lyon
Tel: (78)00.87.12
Tlx: 380636
CYPRUS
Eltrom IPoly Electronics
P.O. Box 5393
Nicosia
Tel: 21 61088
Tlx: Tronics Cy 3529
DENMARK
Ditz Schweitzer A.S.
Vallensbaekvel41
Dk-2600 Glostrup
Tel: (01)45-30-44
Tlx: 33257
FtNLAND
Oy Findip AB
Teollisuustie 7. P.O.B. 34
SF 07200 Kauniainen
Tel: 358-0-5052255
Tlx: 12-3129
Quest Components
57 Rue Mannoir de Servigne
Zl, Route de Lorient
B.P.3209
35013 Rennes Cedex
Tel: (99)54.01.53
Tlx: 740311
Sanelec Electronique
7 Rue de la Couture
Z1, de la Pilaterie
59700 Marcq-en-Baroeuil
Tel: (20)98-92-13
Tlx: 160 143F
Aquitaine Composants
Avenue Gustave Eiffel
B.P.81
33605 Pes sac Cedex
Tel: (56)36.40.40
Tlx: 550696F
SCAIB
80 Rue d'Arcueil
94523 Rungis Cedex
Tel: 687-23-13
Tlx: 204 674F
Aquitaine Composants
55 Avenue Louis Breguet
31400 Toulouse
Tel: (61)20.82.38
GERMANY
Ditronic GmbH
1M Assemwald 48
7000 Stuttgart 70
Tel: (0711)724844
Tlx: 07-255638
Aquitaine Composants
183 Route de Paris
86000 Poitiers
Tel: (49) 88.60.50
Tlx: 791525F
A. Baltzinger
18-26 Route du Gal de Gaulle
B.P.63
67042 Strausbourg Cedex
Tel: (88)331852
Tlx: 870952F
Ing. Buro K.H. Dreyer
Flensburger Strasse 3
2380 Schleswig
Tel: (04621)24055
Tlx: 02-21334
Siliconix
Ing. Buro K.H. Dreyer
Albert Schweitzer - Ring 36
2000 Hamburg 70
Tel: (040)669027
Tlx: 2164484
EBV Elektronik GmbH
Oberweg 6
0-8025 Unterhaching
Tel: 089-61105-1
Tlx: 05-24535
EBV Elektronik GmbH
Alexanderstrasse 42
7000 Stuttg art 1
Tel: (0711)247481
Tlx: 07-22271
EBV Elektronik GmbH
Ostrasse 129
4000 Dusseldorf
Tel: (0211)84846/7
Tlx: 08-587267
III
EBV Elektronik GmbH
Kiebitzrain 18
3006 Burgwedell/Hannover
Tel: (05139)5038
Tlx: 09-23694
EBV Elektronik GmbH
Myliusstrasse 54
6000 Frankfurt 1
Tel: 06111720416/7
Tlx: 04-13590
12-7
European Distributors/Representatives
(Continued)
Ing. Buro Rainer Konig
Konigsberger Strasse 16A
1000 Berlin 45
Tel: 030 772 6009
Tlx: 184 707
IV--electronic
Klaus Vespermann Kg
Bachstrasse 30a
6380 Bad Homburg v.d.H.
Tel: (06172)23061-5
Tlx: 0415864
Ultratronik GmbH
Munchner Strasse 6
8031 Oberalting-Seefeld
Tel: (08152)7774
Tlx: 05-26459
GREECE
General Electronics, Ltd.
209 Thevon SI.
Nikala, Piraeus 77
Tel: 361-8145
Tlx: 212949 GELT GR
General Electronics Ltd.
6 Skoufa SI.
Athens 136
Tlx: 219250 RETE GR
HOLLAND
Koningen Hartman Elektrotechniek BV
P.O. Box 43220
30 Koperwerf
2504 A EThe Hague,Netherlands
Tel: 070-210101
Tlx: 31528
ITALY
Dotl. Ing. Giuseppe DeMico
Via Vittorio. Veneto 8
20060 Cassina De Pecchi. Milano
Tel: (02)9520551
Tlx: 330869
NORWAY
A. S. Kje" Bakke
Postbox 143
2010 Strommen. Nygaton 48
Tel: (02)711872-71 5350
Tlx: 19407
PORTUGAL
Telectra S.A.R.L.
Rua Rodrigo da Fonseca 103
1000 Lisbon
Tel: 686072
Tlx: 12598
Redis Logar SA
Lopez de Hoyos,
78 DPDO, Madrid 2
Tel: 4113561
Tlx: 23967
SWEDEN
Komponentbolaget NAXAB
Box 4115
S-17104 Solna
Tel: 08.985140
Tlx: 17912 KOMP
SWITZERLAND
Kontron Electronic AG
Bernerstrasse Sud 169
8048 Zurich
Tel: 01-62-82-82
Tlx: 588.36
SOUTH AFRICA
Electro Link. Ltd.
P.O. Box 1020
Capetown 8000
Tel: 215-350
Tlx: 572-7320
UNITED KINGDOM
Dage Eurosem Ltd.
Rabans Lane
Aylesbury
Bucks HP19 3RG
Tel: 0296-32881
Tlx: 83518
SPAIN
Redis Logar SA
Casanova 56
Barcelona 11
Tel: 2549048
Hartech Ltd., Smugglers Lane
Bosham, Nr. Chichester, SUSSEX
Tel: (0243)573164
Tlx: 86230
Linburg Electronics Ltd.
36-38 Dickson Street
Elgin Industrial Estate
Dunfermline KY 16 7SL
SCOTLAND
Tel: (0383)32231
Tlx: 72819
Macro-Marketing Ltd.
Burnham Lane,
Slough, Berks
Tel: (06286)4422
Tlx: 847945
Semiconductor Specialists (UK) Ltd.
Carrol House
159 High Street
West Drayton
MIDOI.ESEX UBI ?XB
Tel: (08954)45522146415
Tlx: 21958
Barlec Ltd.
Foundry Road, Horsham
WEST SUSSEX RH13 5PX
Tel: 0403-51881
Tlx: 877222
YUGOSLAVIA
Belram SA
83 Avenue des Mimosas
1150 Brussels, Belgium
Tel: 734.33.32 734.26.19
Tlx: 21790
International and Canada
Distributors and Sales Offices
DISTRIBUTORS
OF CANADA
ONTARIO, Nepean IK2E 7LS)
BRITISH COLUMBIA
Burnaby IV5G 4J7)
Hamilton/ Avnet
2110 Colonade Road
(613)226-1700
Tlx: 0534971
RAE Industrial Elec. Ltd.
3455 Gardner Court
(604)291-8866
Tlx: 04-356533
Twx: 610-929-3065
Future Electronics
4800 Dufferin SI.
(416)663-5563
ONTARIO, Mississauga IL4V lR2)
Hamilton/ Avnet
2845 Rexwood Dr.
(416)677-7432
Twx: 610-492-8867
ONTARIO, Ottawa IK2C 3P2)
Future Elec.
Baxter Centre
1050 Baxter Rd.
(613)820-8313
ONTARIO, Downsvluw IM3H 5SB)
QUEBEC, Polnle Claire 149C 5C7)
Future Elec.
237 Hymus Blvd.
(514)694-7710
Twx: 610-421-3251
QUEBEC, SI. LaurenllH4S 1M2)
Hamilton/Avnet
2670 Sabourin St
(514)331-6443
Twx: 610-421-3731
EUROPEAN
SALES OFFICES
FRANCE
HONG KONG
Siliconix S.A.R.L.
70-72 Avenue du General de Gaulle
Echat 660
94022 Creteil Cedex
Tel: 377.07.87
Tlx: Silconx 230389F
Siliconix (H.K.) Ltd.
5/6/7th Floors
Liven House
61-63 King Yip Street
Kwun Tong, Kowloon
Tel: 3-427151
Tlx: 44449SILXHX
WEST GERMANY
Siliconix GmbH
Postlach 1340
Johannesstrasse 27
0-7024 Filderstadt-l
Tel: (0711)702066
Tlx: 7-255553
JAPAN
Nippon Siliconix Incorporated
I-I, Uchisaiwai-cho, 2-Chome
Chiyoda-ku, Tokyo 100
Tel: (03)506-4670
Tlx: J-23548
UNITED KINGDOM
TAIWAN
Siliconix Ltd.
Brook House
Northbrook Street
Newbury, Berks
RG131AH
Tel: (0635)47609
Tlx: 849357
Siliconix (Taiwan) Ltd.
Nantze Export Processing Zone
Kaohslung
Tel: 362010, 362019
Tlx: 785 712 35
Siliconix Ltd.
Morriston, Swansea
United Kingdom SA6 6NE
Tel: (0792)74681
Tlx: 48197
12-8
FAR EAST
SALES OFFICES
Siliconix
Other International
Distributors/Representatives
ARGENTINA
ISRAEL
MEXICO
TAIWAN
EMSE Electronica SA
Div. Semiconductores
Ayacucho No. 311
1025 Buenos Aires
Tel: 40-2071
Tlx: 2-2185 FINCO-AR
Telsys Ltd.
12, Kehilat Venetsia SI.
Tel Aviv
Tel: 482126-7-8
Tlx: 032392
Mexel
Tlacoquemecatl No. 139-401
Mexico 12, D.F.
Tel: 575-78-68, y 575-79-24
Tlx: MEXEL 017 71823
AUSTRALIA
JAPAN
NEW ZEALANO
Don Business Corp. 3 FL
354 Chang Chung Rd.
Taipei
Tel: 571-2911
Tlx: 25641 DONBC
Cable: "DONBC" TAIPEI
Teijin Advanced Products Corp.
1-1 Uchisaiwai-cho, 2-Chome
Chiyoda-Ku, Tokyo, 100
Tel: (03)506-4670
Tlx: J-23548
S.T.C. Auckland
10 Margot SI.
Epsom, Auckland 3
Tel: 500-019
Tlx: NZ21888
STC Cannon Components PTY. LTD.
248 Wickham Road - P.O. Box 62
Moorabbin, Victoria 3189
Tel: Melbourne 555-1566
Tlx: Melbourne AA 30877
Cable: CANNONLEC - MELBOURNE
BRAZIL
Comercio a Representacoes
Rua da Consolacao, de Eletronicos Cosele Ltda
867-Cj 22
01310 Sao Paulo
Tel: 230-1253 or 230-1496
Tlx: 1130869-CSEL-BR
INDIA
Zenith Electronics
541 Panchratna
Mama Parmanand Marg
Bombay 400004
Tel: 384214
Tlx: 011-3152
Authorized U.S. Agent:
Fegu Electronics Inc.
3308 Middlefield Rd.
Palo Alto, CA 94306
Tel: (415)493-1788
Tlx: 345599
KOREA
PHILIPPINES
Yeonil & Co. Ltd.
498-5,Dapsipri-Dong
Dongdaemoon-Ku
Seoul
Tel: 967-0475 or 968-6745
Tlx: K24123
Alexan Commercial
812 EI Cano SI.
P.O. Box 4459, Manila
Tel: 405923
Tlx: 27484
LATIN AMERICA
Intectra Inc.
2629 Terminal Blvd.
MI. View, CA 94043
Tel: (415)967-8818
Tlx: 345545 Intectra MNTV
Cable: INTECTRA
MALAYSIA
Carter Semiconductor
(M.) SON. Berhad
Jalan Lapangan Terbang
Ipoh
Tel: 513400
Tlx: MA44050
Cable: CARXISTOR IPOH
VENEZUELA
P. Benavides SRL
Avilanas a Rio
Edificio Rio Caribe, Local9
La Candelaria
Apartado #20249
San Martin, Caracas
Tel: 52 92 97
Tlx: 21801 PBTH
SINGAPORE & MALAYSIA
Carter Semiconductor PTE. Ltd.
807, 8th Floor Front Block
Orchard Road, Orchard Towers
Tel: 235 6653
Tlx: RS 36443
SOUTH AFRICA
Electro link (Pty) Ltd.
P.O. Box 1020
Capetown 8000
Tel: 215350
Tlx: 57-27320
Manufacturing Facilities
UNITED KINGDOM
TAIWAN
Siliconix Ltd.
Morriston SWANSEA SA6 6NE
Tel: (0792)74681
Tlx: 48197
Siliconix (Taiwan) Ltd.
Nantze Export Processing Zone
Kaohsiung
Tel: 362010, 362019
Tlx: 78571235
UNITED STATES
Siliconix Incorporated
2201 Laurelwood Rd.
Santa Clara, CA 95054
Tel: (408)988-8000
Twx: 910-338-0227
HONG KONG
Siliconix (HK) Ltd.
51617th Floors
liven House
61-63, King Yip Street
Kwun Tong, Kowloon
Tel: 3-427151
Tlx. 44449 SILXHX
VENEZUELA
P. Benavides SRL
Avilanas a Rio
Edificio Rio Caribe, Local 9
La Candelaria
Apartado #20249
San Martin, Caracas
Tel: 52 92 97
Tlx: 21801 PBTH
Siliconix
12-9
' ..
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