1982_Systems_Data_Catalog 1982 Systems Data Catalog
User Manual: 1982_Systems_Data_Catalog
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SYSTEMS DATA CATALOG
JANUARY 1982
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
The
follo~ing
are trademarks of Intel Corporation and may only be used to identify Intel Products:
BXp, CREDIT, i, ICE, iCS, im , iMMX, Insite, Intel, intel, Intelevision,
Intellec, iOSP, iRMX, iSBC, iSBX, Library Manager, MCS,
Megachassis, Micromainframe, Micromap, Multimodule,
Plug-A-Bubble, PROMPT, RMX/80, System 2000 and UPI.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of
Mohawk Data Sciences Corporation .
• MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Department SV3-3
3065 BowersAvenue
Santa Clara, CA 95051
©INTELCORPORATION,1981
Table of Contents
CHAPTER 1
Integrated Microcomputer Systems
SYSTEM 86/330 Microcomputer System .................................................... 1-1
CHAPTER 2
Single Board Computers
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
80/04 Single Board Computer ........................................................ 2-1
80/05 (or pSBC 80/05) Single Board Computer ........................................ 2-7
80/10B (or pSBC 80/10B) Single Board Computer .................................... 2-12
80/20-4 (or pSBC 80/20-4) Single Board Computer ........................... , ........ 2-19
80/24.(or pSBC 80/24) Single Board Computer ....................................... 2-26
80/30 (or pSBC 80/30) Single Board Computer ....................................... 2-35
86/05 Single Board Computer ....................................................... 2-43
86/12A (or pSBC 86/12A) Single Board Computer .................................... 2-51
86/14 and iSBC 86/30 Single Board Computers ...................................... 2-59
88/25 Single Board Computer ....................................................... 2-67
88/40 Measurement and Control Computer ......................................... " 2-75
310A High Speed Mathematics Unit ................................................. 2-83
CHAPTER 3
iSBX™ MULTIMODULE™ Boards
iSBX
iSBX
iSBX
iSBX
331
332
350
351
Fixed/Floating Point Math MULTIMODULE Board ................ ; ................. 3-1
Floating Point Math MULTI MODULE Board ........................................ 3-7
Parallel I/O MULTIMODULE Board ............................................... 3-12
Serial I/O MULTIMODULE Board ........................................ , .... , ... 3-16
CHAPTER 4
iCS™ Industrial Control Series
iCS 80 Industrial Chassis .................................................................. 4-1
iCS 910/920/930 Signal Conditioning/Termination Panels .................................... 4-6
iSBC 941 Industrial Digital Processor ..................................................... 4-14
CHAPTER 5
Run-Time Systems Software
iRMX 80 Real-Time Multi-Tasking Executive ................................................ 5-1
iMMX 800 MULTIBUS Message Exchange Software .................................. ; ....... 5-6
iRMX 86 Operating System ............................................................... 5-10
iRMX 86 Languages ............................... : ..................................... 5-16
iRMX 88 Real-Time Multi-Tasking Executive ............................................... 5-21
iSBC 957B iAPX 86, 88 Interface and Execution Package ......................... ; ......... 5-27
iOSP 86 iAPX 86/30 and iAPX 88/30 Support Package ...................................... 5-32
CHAPTER 6
Peripheral Controllers
iSBC 204 Single Density Flexible Diskette Controller ........................................ 6-1
iSBC 208 Flexible Disk Controller .......................................................... 6-4
iSBC 215A/iSBC 215B/215C Winchester Disk Controller ..... ; ............ ; ....... ; .......... 6-8
iSBX 218 Flexible Disk Controller ......................................................... 6-13
iSBC 220 SMD Disk Controller ............................................. , ..•.. , .... " .. 6-17
iSBX 270 Video Display Controller ....................................................•... 6-21
CHAPTER 7
Memory Expansion Boards
iSBC
iSBC
iSBC
iSBC
012B RAM Memory Board ...........................................................
016A/032A/064A/028A/056A RAM Memory Boards ....................................
064 RAM Memory Board .............................................................
090 Memory System .................................................................
7-1
7-3
7-6
7-8
iSBC 094 4K-Byte CMOS RAM Memory Battery Backup Board ..............................
iSBC 108A/116A Combination Memory and I/O Expansion Boards ..........................
iSBC 300 (or pSBC 300) 32K-Byte RAM Expansion Module, iSBC 340 (or pSBC 340)
16K-Byte EPROM Expansion Module ..................................................
iSBC 301 4K-Byte RAM MULTIMODULE Board .............................................
iSBC 302 8K-Byte MULTIMODULE RAM ...................................................
iSBC 303 MULTIMODULE Parity ..........................................................
iSBC 341 28-Pin MULTIMODULE EPROM ..................................................
iSBC 416 16K EPROM Expansion Board ..................................................
iSBC 464 64K-Byte EPROM Expansion Board ..............................................
7-12
7-15
7-20
7-24
7-27
7-29
7-33
7-35
7-37
CHAPTER 8
. Digital I/O Expansion and Signal Conditioning Boards
iSBC 337 MULTIMODULE Numeric Data Processor .......................................... 8-1
iSBX 488 GPIB MULTI MODULE Board ...................................................... 8-9
iSBC 517 Combination I/O Expansion Board ............................................... 8-13
iSBC 519 (or pSBC 519) Programmable I/O Expansion Board ............................... 8-17
iSBC 556 Optically Isolated I/O Board ................. : ................................... 8-21
iSBC 569 Intelligent Digital Controller ..................................................... 8-23
CHAPTER 9
Communication Controllers
iSBC 534 Four Channel Communications Expansion Board .................................. 9-1
iSBC 544 Intelligent Communications Controller ............................................ 9-5
iSBC 550 Ethernet' Communications Controller ....... '" ... , .............................. 9-12
iSBX 352 Bit Serial Communications MULTIMODULE Board ................................ 9-16
CHAPTER 10
Analog I/O ExpanSion and Signal Conditioning Boards
iSBX 311 Analog Input MULTIMODULE Board ............................................. 10-1
iSBX 328 Analog Output MULTIMODULE Expansion Board ................................. 10-5
CHAPTER 11
System Packaging and Power Supplies and Service
iSBC 604/614 Modular Cardcage/Backplane ............................................... 11-1
iSBC 660 System Chassis ................................................................ 11-3
iSBC 680/iSBC 681 Multistore User System Package ....................................... 11-6
iSBC 635 Power Supply ................................................................. 11-10
iSBC 640 Power Supply ................................................................. 11-13
iSBC 665/iSBC 645 System Chassis and Power Supply .................................... 11-15
iMBX 100/110/120 MULTIBUS Exchange Hardware Subscription Service .................... 11-19
CHAPTER 12
Microcomputer Development Systems
Model 225 Intellec Series 11/85 Microcomputer Development System ......................... 12-1
Model 286 Intellec Series III Microcomputer Development System ........................... 12-6
Model 675 Development System for Ethernet' ............................................ 12-13
CHAPTER 13
Microcomputer Development Systems Options
MDS 201 Expansion Chassis Intellec Series II Microcomputer Development System ........... 13-1
MDS 384 Mainframe Link for Distributed Development ..................................... 13-3
Model 503 Double Density Upgrade Kit for Intellec Microcomputer Development System ...... 13-6
Model 556 iAPX 86 Resident Processor Board Package .................................... 13-8
Model 677 DS/E Upgrade (Ethernet)' .................................................... 13-11
ISIS II Software Tool Box ................................................................ 13-15
Credit CRT Based Text Editor Microcomputer Development System ...... , .................. 13-17
CHAPTER 14
Flexible Disk Systems
MDS 720 Intellec Single/Double Density Flexible Disk System ............................... 14-1
CHAPTER 15
MCS-SO/SS™ Development Systems and Options
FORTRAN 808080/8085 ANS FORTRAN 77 Intellec Resident Compiler ...................... 15-1
Basic-80 Extended ANS 1978 Basic Intellec Resident Interpreter ............................. 15-5
PASCAL 80 Software Package ............................................................ 15-8
8080/8085 Fundamental Support Package (FSP) .......................................... 15-13
iCIS COBOL Software Package .......................................................... 15-17
PUM 80 High Level Programming Language Intellec Resident Compiler .................... 15-21
ICE-80 8080 In-Circuit Emulator ......................................................... 15-24
ICE-85B In-Circuit Emulator ............................................................. 15-30
CHAPTER 16
iAPX S6/SS Support Options
iAPX 86, 88 Software Development Package for Series II ................................... 16-1
iAPX 286 Evaluation Package ........................................................... 16-11
PL/M 86/88 Software Package .......................................................... 16-13
PASCAL 86/88 Software Package ..... , ... , ................ '" ........................... 16-18
FORTRAN 86/88 Software Package ...................................................... 16-21
8087 Software Support Package ................................. , ....................... 16-25
8087 Support Library ................................................................... 16-28
8089 lOP Software Support Package ............................. , ... , ...... , ......... '" 16-32
ICE-86A iAPX 86 In-Circuit Emulator ..................................................... 16-35
ICE-88 8088 In-Circuit Emulator ......................................................... 16-43
CHAPTER 17
Prototype Microcomputer Kits
SDK-86 System Design Kit ................................................................ 17-1
SDK-C86 ................................................................................ 17-3
SDK-85 System Design Kit ............................................................... 17-9
SDK-51 System Design Kit .............................................................. 17-15
SDK-2920 System Design Kit ............................................................ 17-20
CHAPTER 18
MCS-4STM Development Systems
Intellec PROMPT 48 ..................................................................... 18-1
HSE-49 High-Speed Emulator ............................................................ 18-7
ICE-49, MCS-48 In-Circuit Emulator ...................................................... 18-13
EM-1 8021 Emulation Board ............................................................. 18-18
EM-2 8022 Emulation Board ............................................................. 18-21
ICE-22 8022 In-Circuit Emulator ......................................................... 18-24
MCS-48 Diskette-Based Software Support Package ....................................... 18-30
CHAPTER 19
MCS-S1TM Development Systems
8051 Software Development Package ..................................................... 19-1
EM-51 8051 Emulation Board ............................................................. 19-4
ICE-51 8051 In-Circuit Emulator ........................................................... 19-7
CHAPTER 20
UPI-41ATM Development Systems
ICE-41A, UPI-41A In-Circuit Emulator
..................................................... 20-1
CHAPTER 21
2920 Signal Processor Development Systems
2920 Signal Processing Applications Compliler ............................................. 21-1
2920 Software Support Package .......................................................... 21-6
CHAPTER 22
Memory Systems
Series 90 General Purpose Memory System ............................................... 22-1
Series 90 iOX Intelligent Memory System .................................................. 22-4
CM 5044E UNIBUS' Add-in Memory ............................... :...................... 22-S
in-1671 PDP' 11/70 Add-on Memory System ............................................. ; 22-10
in-5034 PDP' 11/04, 11/34 Add-in Memory. Board .......................................... 22-15
in-5160 Nova' 3 Add-In Memory ......................................................... 22-17
in-5770 Video Refresh Memory System ................................................... 22-22
MU-5750 VAX' 11/750, PDP' 11/70 Add-in Memory Card ................................... 22-27
MU-57S0 VAX'-11/7S0 Add-In Memory Card .............................................. 22-29
iSBC 254 Bubble Memory Board ........................................................ 22-32
iPAB Plug-A-Bubble Memory System .................................................... 22-36
iSBX 251 Magnetic Bubble Multimociule Board ........................................... 22-42
CHAPTER 23
Insite™ User's Program Library ............................................................ 23-1
CHAPTER 24
Software Distribution Operation
Digital Research Inc. CP/M 2.2 Operating System ........................................... 24-1
Digital Research Inc. CP/M-S6 Operating System ............................................ 24-4
Microsoft MACRO-SO Utility Software Package .............................................. 24-7
Microsoft BASIC SO Interpreter Software Package ........................................... 24-9
Microsoft COBOL SO Software Package ................................................... 24-11
Microsoft FORTRAN SO Software Package ................................................. 24-15
Microsoft BASIC 86 Interpreter Software Package .......................................... 24-17
Jovial 86 Cross-Compliler ................................................................ 24-19
'Ethernet is a registered trademark of Xerox Corp.
'VAX, PDP and UNIBUS are registered trademarks of Digital Equipment Corp.
NOVA is a registered trademark of Data General Corp.
Integrated
Microcomputer
Systems
1
SYSTEM 86/330
MICROCOMPUTER SYSTEM
MUL TIBUS® system bus (IEEE-796)
multiprocessor architecture
• Compact desk-top or rack-mount
integrated microsystem
1/1
• High performance 16-bit iAPX 86120
processor set (iSBC™ 86112A + iSBC™
337 boards)
.. 35MB Winchester and 1MB OOIDS 8"
. floppy for program, data storage and
back-up
• Full function iRMX™ 86 real-time,
multitasking operating system
III
.. Intel® resident languages include
PLlM-86 and ASSEMBLER-86_ Intel@
PASCAL-86, FORTRAN-86, plus
independent software vendor
languages (BASIC, COBOL, C), also
available
320KB of high speed RAM memory to
execute multiple jobs and tasks
.. Extensive self-test routines for reliable
operation and simple fault isolation
III
Modular,standard products allow
flexible decomposition of the system
to board level products for custom
configurations
The Intel SYSTEM 86/330 Microcomputer System is a comprehensive integrated, 16-bit hardware and soft,
ware package designed to give the OEM the fastest path to high performance VLSI. The system, which is
based on standard Intel MULTIBUS system bus board level products, also incorporates the VLSI operating
system, iRMX 86, state-of-the-art high capacity mass storage and high density RAM memory boards. In addition to thE') 8ci86 general purpose microprocessor, the system provides 3 to 5 times the numeric performance of low-end minicomputers through the use of the 8087 numeric data processor. The system's
capabilities can be greatly expanded through the use of additional general purpose processors and intelligent I/O boards.
The following are trademarks of Intel Corporation and may be used only to desc~ibe Intel products: Intel, CREDIT, Index, Insite, Intellee, library Manager, Megachassis,
Mlcromap, MULTISUS, PROMPT, UPI, I'Scope, Promware, MeS, ICE; JAMX, iSSe, ISBX,'MULTIMODULE and ies, Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
1-.1 •
October, 1981
Order Number: 210275·001
SYSTEM 86/330
NUMERIC PROCESSING EXTENSION
SYSTEM TECHNICAL DESCRIPTION
Also included with the base SYSTEM 861330 is
the iSBC 337 Numeric Data Processor. This
MUL TIMODULE board contains the Intel 8087
numeric co-processor. The co-processor interface
between the 8087 and the 8086 host CPU provides
a simple means of extending the instruction set of
the system with over 60 additional numeric instructions supporting six additional data types.
The data formats used in the SYSTEM 86/330 conform to the proposed IEEE floating point standard
insuring highly accurate results. Dramatic numeric
performance improvements are provided by the
8087 co-processor. For example a 50X improvement in the Whetstone benchmark over the stand·
ard 8086 processor is afforded by the 8086 numeric
co-processor.
Hardware
PROCESSOR SECTION
The single board computer used in the SYSTEM
86/330 is the MULTIBUS-based iSBC 86/12A board.
The central processor of the iSBC 86/12A board is
the powerful 5 MHz 16-bit 8086. The architecture
includes four 16-bit byte addressable registers,
two 16-bit index registers, all accessed by a total
of 24 operand addressing modes for complex data
handling and flexible memory addressing.
The base SYSTEM 86/330 is supplied with 320KB
of high speed RAM memory. There is 64KB of dual
ported (iSBC 300 memory expansion board supplied) RAM accessible to both the local and
MULTIBUS system bus on the iSBC 86/12A processor board. The system can address up to 1
megabyte of main memory. The processor board
includes an RS232C serial channel for the connection of a user supplied terminal. Cabling to the rear
panel of the system is provided. Asynchronous
baud rates of 110 to 19.2K are supported by the
system. A parallel 110 interface is also available on
the processor board. The port has been configured
to be interfaced to a Centronics compatible line
printer.
The 8087 arithmetic, logarithmic, transcendental
and trigonometric instructions are fully supported
by ASM-86, as well as other Intel higher level
languages such as PLlM-86, PASCAL-86 and
FORTRAN-86.
MEMORY EXPANSION
In addition to the 64KB of dual ported RAM on the
iSBC 86i12A processor board, the SYSTEM 86/330
also includes a 256KB memory expansion board.
SWITCHING POWER
SUPPLY WITH
FAN HOUSING
ISSC" 2158
WINCHESTER DISK
CONTROLLER
ISBX'" 218
FLEXIBLE DISK CONTROLLER
Isec'" 056A
256K RAM MEMORY BOARD
ISBC'" 337 MULTIMODULETIII
NUMERIC DATA PROCESSOR
ISBCN 300 32K BYTE RAM
MULTIMODULE'" BOARD
Figure 1. SYSTEM 86/330 Microcomputer System
1-2
AFN·02107A
SYSTEM 86/330
This brings the system RAM memory supplied
with the base SYSTEM 86/330· to 320KB. The
256KB memory board uses the latest technology
64K bit dynamic RAMs. Through the use of optional
memory expansion boards, the total memory
capacity of the SYSTEM 86/330 may be expanded
to 1 megabyte.
out service access. In addition to providing the
necessary voltages for the MULTI BUS cards, Hie
efficient switching power supply also provides the
24 volts needed for the DC powered Winchester
drive. The SYSTEM 86/330 has been designed to
meet UL, CSA, FCC and VDE safety and EMI/RFI
requirements. Supplied with the SYSTEM 86/330
are connectors for the RS232 channel, parallel line
printer, and additional floppy disk and Winchester
disk drives. Cut-outs are also available for OEM
supplied connectors.
MASS STORAGE
Intelligent Controller - The SYSTEM 86/330 uses
the intelligent, 8089-based iSBC 215B Winchester
controller. This high performance interface contains firmware which is executed directly on the
8089 processor. This intelligent I/O ,processor
coupled with an on-board RAM buffer off loads a
significant portion of disk I/O overhead from the
host 8086 processor. In addition to the Winchester
control firmware, there is also 8089 firmware resident on the iSBC 215B board to control the iSBX
218 floppy disk controller. The floppy controller
plugs directly onto the iSBC 215B board via one of
the two available iSBX connectors.
System Decomposition for Low Cost
The ,entire SYSTEM 86/330, both hardware and
software, is built using standard, modular off-theshelf Intel products that are available separately.
The system is designed so that the OEM can easily
decompose the SYSTEM 86/330 into the individual
Intel products needed to tailor a custom system.
Through the use of industry standard modules and
interfaces, the OEM can perform his own system
integration without changing software code, thus
lowering his end product cost.
Mass storage expansion beyond the single Win~
chester and floppy diskette drives configured with
the system is easily accomplished by the OEM
through the use of daisy chain connector on the
back panel of the SYSTEM 86/330 chassis. In addi
tion to the Winchester and Floppy interfaces provided with the system, Intel also can provide a
board level interface and iRMX 86 software for
SMD compatible disk drives.
System Software
The SYSTEM 86/330 can be used for iRMX 86 software development, as well as being the target
system for the OEM application.
VLSI OPERATING SYSTEM (iRMX™ 86)
Winchester Disk Drive - The SYSTEM 86/330 contains a high performance 35MB (32MB formatted)
8" Winchester technology hard disk drive for pro- .
gram and data storage. The drive has an average
access time of 43 ms and a transfer rate of 6.44
Mbits/sec.
Floppy Diskette Drive - A double density/double
sided, 8", 1MB, floppy disk drive is included in the
base system. This high density floppy drive, which
has an average access time and a transfer rate of
250Kbits/sec, can be used for both data storage
and system backup.
SYSTEM CHASSIS
The chassis used in the SYSTEM 86/330 is the
compact iSBC 680 Multistore User System Package. This 21.0" x 16.75" x 12.25" package houses
up to six MULTIBUS cards (two available forexpansion in the SYSTEM 86/330). The 8" Winchester'
disk drive and 8" floppy disk drive are housed in
the iSBC 680 package with simple slide-in, slide1-3
The powerful iRMX 86 Operating System is an
easy-to-use, comprehensive multiprogramming
software system designed not only for the
SYSTEM 86/330, but for iAPX 86/88-based iSBC
board and component level designs.
Services provided by the RAM-based iRMX 86
Operating System include facilities for executing
programs concurrently, sharing resources and information, servicing asynchronous events, and interactively controlling system resources and utilities. In addition, the iRMX 86 Operating System
provides all major real-time facilities, including
priority-based system resource allocation, means
for concurrently monitoring and controlling multiple external events, real-time clock control, interrupt management, and task dispatching. The iRMX
86 Operating System contains the following
modules: an object-oriented Nucleus; Device Independent Basic and Extended I/O Systems; Terminal Handler; Bootstrap and Application
Loaders; Human Interface with complete command line interpreter; and an interactive, objectoriented Debugger.
AFN·02107A
SYSTEM 86/330
Because the modules and services provided by the
operating system are user selectable, application
specific operating systems .can be created by
iRMX 86 users. The iRMX 86 Operating System
therefore eliminates the need for custom operating system design, thereby reducing development
time, cost, effort, and risk.
capability suitable for novice users as well as advanced capabilities for sophisticated users. Its
key features include a macro processor capable of
creating and executing complex strings of commands, which ease the editing chore,as well as
defining blocks of text which may be included
anywhere in the text file. EDIT offers variable command sourcing, symbolic line numbering and
reference by symbol. The facilities of EDIT allow
users to create, maintain and manipulate extensive libraries of source code with minimal effort:
For more information on iRMX 86 EDIT, see the
EDIT Software Package data sheet (143883).
iRMX™ UTILITIES PACKAGE (iRMXTM 860)
TheiRMX Utilities Package consists of the following software:
iRMX™ 86 EDIT - The iRMX 86 EDIT program provides users with a powerful, sophisticated, lineoriented editing facility. EDIT delivers a range of
iRMX™ 86 LINK/LOCATE - The iRMX 86 LINK!
LOCATE program connects object modules which
INDEPENDENT
SOFTWARE
VENDOR
LANGUAGES
INTEL®
LANGUAGES
~________________~U~N_'V_ER_S_AL_R_UN_'T_'M_E_'N_T_ER_F_AC_E_(U_D_')________________~~
OEM
~.C'
~
OR
PRODUCT
•.
VEHICLE
SYSTEM
881330
<:
BOARD.LEVEl
MULTIBUS@SYSTEM,BUS
DESIGNS
>
Figure 2. Software Development Process
1-4
AFN'()2107A
SYSTEM 86/330
have been individually compiled into a single,
relocatable object module. The input object code
may have been produced by any Object Module
Format-compatible compiler. Output object
modules may be recombined into larger object
modules, allowing work from a large programming
staff to be easily integrated into an application
system.
lems, the SYSTEM 86/330 is supplied with three
levels of diagnostic routines:
SCT (System Confidence Test) - Automatically
executed at power on and system reset, the SCT
performs a GO-NO GO condition for the processors, memory and devices in the system.
SOT (System Diagnostic Test) - In the event that
the SCT finds a system problem, the SDTmay be
executed by the user for a detailed analysis of the
hardware status. This menu driven monitor program can perform tests on all hardware boards in
the system and mass storage peripherals.
iRMX™ 86 LIB - the iRMX 86 LIB "Library
Manager" allows creation and maintenance of object module libraries. These libraries allow easy
collection of related object code to reduce the
overhead of maintaining many separate modules ..
Users may create new libraries, add and delete object modules, as well as list the contents of the
library and their public symbols.
SAT (System Analysis Test) - This diagnostic tool
tests the integration of the hardware and software
at the system level. This helps to isolate intermittent failures by running a load stress test on both
hardware and software.
PLlM-86 (iRMXTM 863)
The PUM-86 compiler provides users with a powerful, microcomputer-oriented system programming
language. The PUM-80 Language was introduced
in 1976 by Intel. It was the first microcomputeroriented, block structured, high-level language
available. Since 1976, thousands of users, shipping over millions of microcomputer-based systems
have generated their system software with
PUM-80 and PUM-86.
SYSTEM DEBUGGING TOOLS
The iRMX 86 Operating System provides a comprehensive tool for interactive software debugging.
The Debugger has two capabilities that greatly
simplify the process of debugging a multitasking
system. First, the Debugger allows users to debug
several tasks while the balance of the application
system continues to run in real-time. Second, the
Debugger allows programmers to interactively
view and modify system constructs as well as the
system RAM and CPU registers. The debugger is
structured to enable system designers to track
system-wide problems easily. It can also remain in
the final application as a continuous maintenance
tool.
PUM-86 is a compatible superset of PUM-80 which
offers easy portability of software across the full
range of microcomputers supplied by Intel. For
more information about PUM-86, see the PUM
86/88 Software Package data sheet (402175).
FULL REALMATH SUPPORT
OEM SOFTWARE LICENSING
The iRMX 86 Languages support the REALMATH
floating point standard. This allows users of all
iRMX 86 languages to access the iAPX 86/20
Numeric Data Processors using the iSBC 337
MULTIMODULE board. These numeric processors
offer over 100 times greater performance than
comparable software-implemented algorithms,
and reduce the system memory requirements by at
least 16KB. The REALMATH standard (proposed
IEEE standard) provides universal consistency in
results of numeric computations. The iRMX 86
Languages provide efficient object code generation and access to the highest performance floating point package available on microcomputers.
The Intel software products listed above require
the signing of an Intel Master Software License
Agreement. All products include 1 year of update
service. Software is shipped on floppy media in
two object forms: 1) a ready-to-run, fully configured system, and 2) a configurable version of all
software products.
OPTIONAL INTEL® SOFTWARE SUPPORT
In addition to ASM-86 and PUM-86 included in the
base SYSTEM 86/330, the following Intel languages are available for use on the system:
PASCAL-86 (iRMX™ 861) - The PASCAL-86 compiler provides a strict implementation of the proposed ISO language standard. All source programs are validated by the compiler to ensure its
conformance to the standard. Many extensions to
COMPREHENSIVE SELF-TEST AND SYSTEM
DIAGNOSTICS
In order to insure correct system operation and
rapid location of both hardware and software prob1-5
AFN'()2107A
SYSTEM 86/330
550 board), serial communications controller (iSBC
544 board) and analog measurement and control
computer (iSBC 88/40 board) can greatly expand
the capabilities and proceSsing power of the
SYSTEM 86/330.
the language are available which allow PASCAL
programs to be written specifically for microcomputers. Separate module. compilation and .iAPX
86/20, .88/20 Numeric Data Processor support are a
few of its many features. The ISO standard "source
evaluator" can be switched off to accept these extensions. For more information on iRMX 86
PASCAL features, see the PASCAL 86/88 Software
Packagedata sheet (121680) ..
INDEPENDENT SOFTWARE VENDOR SUPPORT
- Through the use of the standard UDI (Universal
Development Interface) a wide variety of language
products, .bothcompilersand. interpreters, are
now available for use on iRMX86 from independent software, vendors. COBOL, BASIC, CBASIC,
and C are a few examples .of the available languages. Contact your Intel sales representative for
more information.
FORTRAN-86 (iRMX™ .862) - The. iRMX 86 FORTRAN compiler provides users total compatibility
with existing FORTAN 86 language-generated
code, plus many new language features provided
by the FORTRAN 77 language standard. These
new features offer FORTRAN programmers many
new capabilities, including "IF-THEN-ELSE", random access 1/0 and character variables. For a more
detailed explanation of iRMX 86 FORTRAN,see
the FORTRAN 86/88 Software Package data sheet
(400630).
System Options
HARDWARE
Any Intel MULTI BUS boardmay be installed by the
OEM.into the two available expansion slots in the
system chassis.
iMMX 800 MULTIBUS® Message Exchange - The
advanced design of the MULTIBUSsystem bus
coupled with. the iMMX 800 software package
allows the SYSTEM 86/330 to easily support additionalS and/or 16-bit Intel single board computers.
This powerful option enables OEMs to increase
the SYSTEM 86/330's general purpose processing
power with boards such as the iSBC S6/05 (8 MHz
8086) and iSBC88/25 (5 MHz8088). Intelligent, high
performance microprocessor based b,oards such
as the Ethernet' communications controller (iSBC
SOFTWARE
Optional language products are available from
both Intel and independent software vendors.
Operating system support for additional 8085,
8088 and 8086-based processor boards is available
through the use of iRMX 80, iRMX 88 and iRMX 86
software. Multiprocessor software support, iMMX
800, is also available for the SYSTEM 86/330.
• Ethernet is a trademark of Xerox Corp.
SPECIFICATIONS
Serial - Configurable from 110 to 19.2K baud
(asynchronous)
Word Size
Parallel.;... A parallel 1/0 port configured to inter;
face with an industry standard .Centronicsinterface pri nter
Instruction - 8, 16, or32 bits
Data....,.. 8/16 bits
Instruction Cycle Time
AC Requirements
400 nanoseconds for fastest executable instructions (assuming instruction is in the queue).
6.5A @ 88 to 126 VAC, 60 Hz, single-phase (US
oilly);3.25A @ 176 to 252 VAG, 50 HZ,single,phase
(Europe only). Maximum total power consumption
350W.
1.0 microseconds for fastest executable instructions (assuming instruction is not in the queue).
Product Safety Standards
Memory Capacity
The system is listed under UL standard 114 Safety
of Electronic Data Processing Units and Systems.
It is .also certified by the .CanadianStandards
Association, standard C22.2 154-1975 Safety of
Data Processing Equipment. The system complies
with the International Electronics Commission
standard IEC 435 Safety of Data Processing Equip-
RAM - 320K bytes supplied with the base system.
Memory may be expanded to 1 megabyte.
Interface
EIA Standard RS232C signals provided and supported.
1-6
AFN·02107A
SYSTEM 86/330
ment. The system also conforms to the applicable
RFI/EMI requirements of VDE 0871/6.78, VDE
0875/6.77 and FCC rule 47 CFR part 15 subpart J
Emmission Limits for Computing Devices.
Relative Humidity - 20% to 80% non-condensing
Environmental Requirements
Relative Humidity - 20% to 80% non-condensing
over the operating temperature range'
Sea level to 6000 feet
Vibration -
1.0g @ 10 to 55 Hz
Extensive System Documentation
The SYSTEM 86/330 is shipped with six documentation binders containing over 28 in-depth
manuals on all aspects of hardware and software
operation. A system installation and maintenance
manual, in addition to a system overview manual,
are also included.
"NOTE: The environmental combination of humidity and tem·
perature together cannot exceed 26 'C wet bulb.
NON-OPERATING
Temperature -
- 25°C to 60 °C
ORDERING INFORMATION
Part Number
Description
SYS 86/330 PKG
Desk-top, 120V 60 Hz
SYS 86/330E PKG
Desk-top, 220V 50 Hz
SYS 86/331 PKG
Rack-mount, 120V 60 Hz
SYS 86/331 E PKG
Rack-mount, 220V 50 Hz
SYS 86/330 DOC
Complete hardware and software documentation set (included with system; use this
order code for additional
sets)
1.0g for 5 ms shock
Width - 16.75 in. (42.55 cm)
Height - 12.25 in. (31.12 cm)
Depth - 21.00 in. (53.34 cm)
Weight - 75 pounds (34.02 kg)
15°C to 35°C
Altitude -
Sea level to 12,000 feet
Vibration -
Physical Characteristics
OPERATING
Temperature -
Altitude -
1-7
":~.
"
..
./",
I'"
Single Board
Computers
2
inter
iSBC 80/04
SINGLE BOARD COMPUTER
• Programmable 14-bit binary timer
• 8085A CPU used as central processor
• 256 bytes of static readlwrite memory
II
• TTL serial 1/0 interface with hole
patterns for RS232C line drivers and
receivers
Sockets for 4K bytes of erasable
reprogram mabie read only memory
• 22 programmable parallel 1/0 lines with
sockets for interchangeable line drivers
and terminators
• Four-level vectored interrupt
• Optimized for stand-alone applications
with provisions for on-board + 5V
regulator, heat sink, and mounting
holes for attachment to.user's
equipment
• Upward compatibility with iSBC 80105
• Single + 5V power supply
The iSBC 80/04 Single Board Compute(is a member of Intel's complete line of OEM computer systems which take full
advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for OEM applications. The iSBC 80/04 is a complete computer system on a single 6.75 x 7.85-inch printed circuit card. The CPU, system
clock, read/write memory, nonvolatile read only memory, I/O ports and drivers, serial interface, priority interrupt logic,
and programmable timer all reside on the board.
2-1
AFN·00259A
iSBC 80/04
RAMIIO/Timer. The system software is used to con·
figure the I/O lines in any combination of unidirectional
input or output ports as indicated in Table 1. The I/O in·
terface may, therefore, be customized to meet specific
peripheral requirements. In order to take full advantage
of the large number of possible I/O configurations,
sockets are provided for interchangeable I/O line drivers
and terminators. Hence, the flexibility of the I/O inter·
face is further enhanced by the capability of selecting
the appropriate combination of optional line drivers and
terminators to provide the required sink current, polar·
ity, and drive/termination characteristics for each appli·
cation, The 22 programmable I/O lines and signal ground
lines are brought out to a 50·pin edge connector that
mates with flat, woven, or round cable.
FUNCTIONAL DESCRIPTION
Intel's powerful8·bit n·channel8085A CPU, fabricated on
a single LSI chip, is the central processor for the iSBC
80/04. The 8085A CPU is directly software compatible
with the popular intel8080A CPU. The 8085A contains six
8·bit general purpose registers and an accumulator. The
six general purpose registers may be addressed individ·
ually or in pairs, providing both single and double preci·
sion operators. Minimum on·board instruction execu·
tion time is 2.03 microseconds. A block diagram of iSBC
80/04 functional components is shown in Figure 1.
Memory Addressing
The 8085A CPU has a 16·bit program counter which
allows addressing of up to 65,536 bytes of memory. An
external stack, located within any portion of iSBC 80/04
read/write memory, may be used as a last·in/first·out
storage area for the contents of the program counter,
flags, accumulator, and all of the six general purpose
registers. A 16·bit stack pOinter controls the addressing
of this external stack. This stack provides subroutine
nesting bounded only by memory size.
Stand·Alone Applications
The iSBC 80/04 is designed to be a cost'E1ffective solu·
tion for applications requiring a self·contained com·
puter on a single board without the need for external
memory or I/O options. In order to help minimize power
supply cost in small systems, the iSBC 80/04 includes
provision for an on·board + 5V regulator allowing unreg·
ulated voltage to be connected directly on the board.
Regulated DC voltages are applied to the board through
two 12·pin edge connectors which mate with flat,
woven, or round cables. The iSBC 80/04 also includes
pins that will accept MOLEX·type connectors for con·
nection of regulated DC Voltages. Mounting holes are
provided in the corners of the iSBC 80/04 board which
permit direct attachment to the user's equipment,
thereby eliminating the need for card cage and back·
plane.
Memory Capacity
The iSBC 80/04 contains 256 bytes of read/write memory
using the Intel8155 RAM/IOlTimer. Two sockets for up to
4K bytes of nonvolatile read only memory are provided
on the board. Read only memory may be added in
2K·byte increments using Intel 2716 erasable and elec·
trically reprogrammable ROMs (EPROMs). Optionally, if
only 2K bytes are required, read only memory may be
added in 1K·byte increments using Intel 2708 EPROMs.
Compatibility with iSBC 80/05
Parallel 1/0 Interface
The iSBC 80/04 is fully upward compatible with the iSBC
80/05 Single Board Computer. Pin assignments for
parallel I/O, serial I/O, and regulated DC voltages are
The iSBC 80/04 contains 22 programmable parallel I/O
lines implemented using the I/O ports of the Intel 8155
EXTERNAL
INTERRUPT
REQUEST
LINE
22 PROGRAMMABLE
I/O liNES
SERIAL
I/O INTERFACE
(TTL LEVELS)
SERIAL
I/O INTERFACE
(RS232C lEVELS)
2110 INTERRUPT
REOUEST LINES
8085
ceu
Figure 1. iSBC Block Diagram Showing Functional Components
2-2
AFN·00259A
iSBC 80/04
Table 1. InputlOutput Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines
(qty)
Input
Unlatched
1
8
2
3
8
3
4
3
Output
Latched &
Strobed
X
X
X
X
X
X
Latched
X
X
X
X
Control
Latched &
Strobed
X
X
X1
X2
Notes
1. Port 3 must be used as a control port when port 1 is used as a latched and strobed input or a latched and strobed output port.
2. Port 4 must be used as a control port when port 2 is used as a latched and strobed input or a latched and strobed output port.
indentical to those of the iSBC 80/05. Additionally, soft·
ware developed for the iSBC 80/04 will execute directly
in the iSBC 80/05. In addition to the iSBC 80/04 features,
the iSBC 80/05 contains a total of 512 bytes of readlwrite
memory, allows for expansion of memory and 1/0
capacity, and· provides full MULTIBUS arbitration con·
trol for multi master applications.
Serial I/O Interface
The iSBC 80/04 prvides serial 1/0 capability through the
serial input data (SID) and serial output data (SOD) func·
tions of the Intel 8085A CPU. These functions are controlled exclusively by software through execution of the
8085A RIM and SIM instructions. The baud rate for the
serial 1/0 interface is determined by the system time
available for execution of serial 1/0 support software.
Hence, the maximum baud rate supported by the iSBC
80/04 is solely dependent on the overall system real·
time software requirements. Serial 110 signals are TTL
compatible, and hole patterns are provided on the board
for optional installation of RS232C line drivers and
receivers.
Programmable Timer
The iSBC 80/04 provides a fully programmable binary
14·bit interval timer utilizing the Intel 8155
RAM/IO/Timer. The systems designer simply configures
the time via software to meet system requirements.
Whenever a given timer delay is needed, software com·
mands to the programmable timer select the desired
functions. Four functions are available as shown in
Table 2. The contents of the timer counter may be read
at any time during system operation.
Interrupt Capability
The iSBC 80/04 takes advantage of the powerful interrupt processing capability of the 8085A CPU. Interrupt
requests are routed to four interrupt inputs of the 8085A
CPU (i.e., TRAP, RST 7.5, RST 6.5, and RST 5.5 in order of
priority, TRAP highest), and each input generates a
unique memory address (i.e., TRAP: 26 16, RST 7.5: 3C 16 ,
RST 6.5: 34 16, RST 5.5: 2C 16 ). A single 8085A jump in·
struction at each of these addresses then provides
linkage to locate each interrupt service routine in·
dependently anywhere in memory. All interrupt inputs
with the exception of one (TRAP) may be masked via
software. The trap interrupt should be used for condi·
tions such as power-down sequences which require attention by the 8085A CPU.
Table 2. Programmable Timer Functions
Function
Operation
Programmable
pulse
Timer out goes low during the sec·
ond half of count. Therefore, the
count loaded in the count length
register should be twice the pulse
width desired.
Square wave
rate generator
Timer out remains high until one·
half the count has been completed,
and goes low for the other half of the
count. The count length is auto·
matically reloaded when terminal
count is reached.
Rate generator
Divide by N counter. A repetitive
timer out low pulse is generated and
new timeout initiated every time ter·
minal count is reached.
Programmable
strobe
A single low pulse is generated upon
reaching terminal count. This func·
tion is extremely useful for genera·
tion of real·time clocks.
Interrupt Generation - The iSBC 80/04 accepts interrupts from four sources. An interrupt is automatically
generated by the programmable interval timerlevent
counter upon completion of the selected function. Two
interrupts are automatically generated by the 1/0 ports
section of the 8155 when ports 1 or 2 of the 8155 are programmed to operate in the "latched and strobed"-niode
(see Table 1). The fourth interrupt source is available to
the user and should be used to inform the 8085A CPU of
catastrophic errors such as power failure. This userdefined source is connected to the trap input of the
8085A CPU.
2-3
AFN-00259A
iSBC 80/04
capability to program in a natural, algorithmic language
and eliminates the need to manage register usage or
allocate memory. PUM programs can be written in a
much shorter time than assembly language programs
for a given application.
Systems Development Capability
The development cycle of the iSBC 80/04-based products may be significantly reduced using an Intellec
microcomputer development system. The resident
macroassembler, text editor, and system monitor
greatly simplify the design, development, and debug of
iSBC 80/04 system software. An optional diskette oper·
:lting system provides a relocating macroassembler, a
relocating loader and linkage editor, and a library manager. A unique in-circuit emulator (ICE-85) option pro·
vides the capability of developing and debugging software directly on the iSBC 80/04.
PUM·80 - Intel's high level programming language,
PUM, is also available as a resident Intellec microcomputer development syste,m option. PUM provides the
FORTRAN·80 - For applications requIring computa·
tional and formatted 1/0 capabilities, the high level
FORTRAN-80 programming language is also available
as a resident option of the Intellec system. The FORTRAN compiler produces relocatable object code that
may be easily linked with PUM or assembly language
program modules. This gives the user a wide flexibility
in developing software.
SPECIFICATIONS
Interrupts
Word Size
Four-level interrupt routed to 8085 CPU interrupt inputs.
Each interrupt automatically vectors the processor to a
unique memory location
Programming Capability
Instruction - 8, 16, or 24 bits
Data - 8 bits
Condition
Cycle Time
User·defined
Basic Instruction Cycle. - 2.03 '"'s, ± 0.1 %
Timer
110 Port 2
110 Port 1
Note
Interrupt
Input
Memory
Address
TRAP
RST 7.5
RST 6.5
RST 5,5
24 16
3C16
34 16
2C16
Prtorlty
Type
Highest
Non·maskable
Maskable
Maskable
Maskable
t
Lowest
Basic instruction cycle Is defined as the fastest Instruction (Le., four
clock cycles),
Memory Addressing
Timer
ROM/EPROM - O-OFFFH
RAM - 3FOO H
'"'S period nominal)
Input Frequency Reference -
122.88 kHz ±0.1% (8.14
Output FrequencieslTiming Intervals
Memory Capacity
ROM/EPROM - 4K bytes (sockets only)
RAM -256 bytes
Timer/Counter
Function
1/0 Addressing
On-Board Programming 1/0 -
see Table 1
Port
Control
8155
Port 1
8155
Port 2
8155
3&4
8155
Ports
8155 Timer
Low·Order
Byte
8155 Timer
Hlgh.Order
Byte
Address
00
01
02
03
04
05
Programmable pulse
Square wave rate generator
Rate generator
Programmable strobe
Min
Mex
8,14 ~s
7,50 Hz
7,50 Hz
8,14 ~s
66.67 ms
61.44 kHz
61.44 kHz
133,33 ms
Interfaces
1/0 Capacity
Parallel 1/0 - All signals TTL compatible
Interrupt Request - All TTL compatible (active-low)
Serial 1/0 - TTL; hole patterns available for user installation of RS232C line drivers and receivers
Parallel - 22 programmable lines (see Table 1)
Serial Communications Characteristics
SID and SOD functions of the 8085 CPU are used for
serial 1/0. Controlled by software through RIM and SIM
instructions of the 8085A CPU. Baud rate determined by
system time available for serial 1/0 handling. On-board
timer may be used to greatly ease serial 1/0 timing requirements.
System Clock (8085 CPU)
1.966 MHz ±0.1%
2-4
AFN·00259A
iSBC 80/04
Line Drivers and Terminators
Connectors
110 Drivers - The following line drivers are all compati·
ble with the I/O driver sockets on the iSSC 80104'
Interface
+5V, + 12V,
_5V 2
Voltages
+5V, -12V3
Unregulated
+5V
Parallel 110
Serial 1/0
Pins
(no.)
7
single·
sided
7
singlesided
Center
(In.)
Molex 09·66·1071
Connector
Molex 09·50·7071
Connector
0.156
Characteristic
Sink Current (rnA)
7438
I,oe
48
7437
I
48
7432
NI
16
7426
I,oe
16
7409
NI,oe
16
7408
7403
NI
I,oe
16
16
7400
I
16
Nole
AMP 87194·6
Connector
AMP 3-87025·4
Connector
I = Inverting; NI = non-Inverting; oe = open colleclor.
I/O Terminators - Intel provides 220Q/330Q divider and
1 kQ pull·up resistive terminator packs for termination
of I/O lines programmed as inputs. These options are as
follows:
Molex 09·66·1071
Connector
Molex 09·50·7071
Connector
0.156
AMP 87194·6
Connector
AMP 3·87025·4
Connector
220Q
+5V----------~~------'
0.156
50
double·
sided
0.1
~~-------"-----~O ISBC 901
220Q/330QL
Molex 09·66·1021
Connector
Molex 09·50·7021
Connector
2
single'
sided
7
single·
ended
Mating Connectors 1
Driver
OPTION
1 kQ
1 kQ
+ SV --------~vv-,r------------~o
iSBC 902 OPTION
RS232C Drivers and Receivers
AMP 89194·1
Connector
AMP 2·87025·5
Connector
The following RS232C drivers and receivers are compatible with the RS232C socket on the iSSC 80104:
RS232C Driver - National DS1488 or TI SN75188
RS232C Receiver - National DS1490 or TI SN75189
3M 3415·000
(flat cable)
Sockets
Sockets may be installed in the hole patterns provided
for the RS232C drivers and receivers. The following
sockets are compatible with the iSSC 80104: TI
C93·14·02 and SCANSE US·2·14-160-N·S.
Molex 09·66·1071
Connector
Molex 09·50·7071
Connector
0.156
Compatible Voltage Regulator
AMP 87194·6
Connector
AMP 3·87025·4
Connector
National LM 323 - 3A, 5V Positive Regulator
Fairchild !A780S KM - 1A, 5V Positive Regulator
Compatible Heat Sink
IERC - LA Series or
AAVID Engineering, Inc. Notes
1. Connectors and pins from a given vendor may only be used with connectors and pins from the same vendor.
2. A single 86-contact edge-on connector may be used to connect the
two groups of regulated voltages (i.e., + 5V, + 12V, - 5V, and + 5V,
-12V).
Series 5051
Physical Characteristics
Width Height Depth Weight -
3. Required only when RS232C line drivers and receivers arB used.
2-5
7.85 in. (19.94 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 em)
6.0 oz (169.9 gm)
AFN·00259A
iSBC80/04
1--------------7.350------------_
----1-----2.462---_
I
5.950
6.75
6.20
I
-0-
.146
1-------------6.767--------~--'-'-'-'_i
7.85--~------------I
Figure 2. iSBC 80/04 Dimensions
Electrical Characteristics
Environmental Characteristics
O°C to + 55°C
Operating Temperature -
DC Power Requirements
Voltage
(:!:5%)
VCC~
+5V
VDD~,+12V4
VBB~-5V4
VAA~ -12V5
Without
PROM1
With 2716
With 2708
EPROM2
EPROM3.
(max)
(max)
ICC~600mA
IDD~O
IBB~O
IAA~O
(max)
1.45A
7 mA5
1.25A
0
23 mA5
90 mA
23 mA5
Reference Manual
137 mA
9800482·02 - iSBC 80/04 Hardware Reference Manual
(NOT SUPPLIED)
Notes
1. Does not include pow~r required for optional EPROM/ROM, I/O
drivers, and 110 terminators.
2. With two Intel 2716 EPROMs and 220Qf330Q terminators Installed
for 22 input ports; all terminator inputs low.
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
3. With two Intel 2708 EPROMs and 220Q/330Q terminators installed
for 22 input ports; all terminator inputs low.
4. Required for 2708 EPROMs.
5. Required only when RS232C, capability required.
ORDERING INFORMATION
Part Number
Description
SBC 80/04
Single Board Computer
2-6
AFN-00259A
iSBC 80105 (or pSBC 80/05*)
SINGLE BOARD COMPUTER
• Programmable 14-bitbinarytimer
• BOB5A CPU used as central processor
• 512 bytes of static read/write memory
• TTL serial 110 interface with sockets for
RS232C line drivers and receivers
• Sockets for 4K bytes of erasable
reprogram mabie or masked read only
memory
• Four-level vectored interrupt
• 22 programmable parallel 110 lines with
sockets for interchangeabie line drivers
and terminators
• Fully compatible with optional iSBC
expansion boards and peripherals
• Full M ULTIBUS control logic allowing .
up to 16 masters to share system bus
• Single + 5V power supply
The iSBC 80/05 Single Board Computer is a member of Intel's complete line of OEM computer systems which take full
advantage of Intel's LSI technology to p(ovide economical, self-contained computer-based solutions for OEM applications. The iSBC 80/05 is a complete computer system on a single 6.75 x 12.00-inch printed circuit card, The CPU,
system clock, read/write memory, nonvolatile read only memory, I/O ports and drivers, serial interface, priority interrupt logic, programmable timer, MULTIBUS control logic, and bus expansion buffers all reside on the board:
'Same product, manufactured by Intel Puerto Rico, Inc.
2-7
AFN·Q026QA
iSBC 80105
FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel 8085 CPU, fabricated on
a single LSI chip, is the central processor for the iSBC
80/05_ The 8085A CPU is directly software compatible
with the popular Intel8080A CPU. The8085A contains six
8-bit general purpose registers and an accumulator. The
six general piJrpose registers may be addressed individually or in pairs, providing both single and double precision operators. Minimum on-board instruction execution time Is 2.03 microseconds. A block diagram of iSBC
80/05 functional components is shown in Figure 1.
Memory Addressing
The 8085A CPU has a 16-bit program counter which
allows direct addressing of up to 65,536 bytes of memory. An external stack, located within any portion of
readlwrite memory, may be used as a last-in/first-out
storage area for the contents of the program counter,
flags, accumulator, and all of the six general purpose
registers. A 16-bit stack pointer controls the addressing
of this external stack. This stack provides subroutine
nesting bounded only by memory size.
Memory Capacity
The iSBC 80/05 contains 512 bytes of readlwrite memory
using Intel's low power static RAMs. Two sockets for up
to 4K bytes of nonvolatile read only memory are provided
on the board. Read only memory may be added in
2K-byte increments using Intel 2716 erasable and electrically reprogrammable ROMs (EPROMs). Optionally, if
only 2K bytes are required, read only memory may be
added in 1 K-byte increments using Intel 2708 EPROMs.
Parallel 1/0 Interface
The iSSC 80/05 contains 22 programmable parallel I/O
lines implemented using the I/O ports of the Intel 8155
RAMIlOlTimer. The system software is used to con-
figure the I/O lines in any combination of unidirectional
input or output ports as indicated in Table 1. The I/O interface may, therefore, be customized to meet specific
peripheral requirements. In order to take full advantage
of the large number of possible I/O configurations,
sockets are provided for interchangeable 110 line drivers
and terminators. Hence the flexibility of the 110 interface
is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity,
and driveltermination characteristics for each application. The 22 programmable 110 lines and signal ground
lines are brought out to a 40-pin edge connector that
mates with flat, woven, or round cable.
Multimaster Capability
The iSBC 8085A is a full computer on a single board with
resources capable of supporting a great variety of OEM
system requirements. For those applications requiring
additional processing capacity and the benefits of
multiprocessing (i.e., several CPUs andlor controllers
logically share systems tasks with communication over
the system bus), the iSBC 80/05 provides full MULTI BUS
arbitration control logic. This control logic allows up tq
three bus masters (i.e., any combination of iSBC 80/05,
iSSC 80/20-4, DMA contrbller, diskette controller, etc.) to
share the system bus in serial (daisy-chain) priority
fashion, and up to 16 masters may share theMULTIBUS
with the addition of an external priority network. The
MULTIBUS arbitration logic operates synchronously
with a MULTIBUS clock (provided by the iSBC 80/05 or
optionally connected directly to the MULTIBUS clock)
while data is transferred via a handshake between the
master and slave modules. This allows different speed
controllers to share resources on the same bus, and for
transfers via the bus to proceed asynchronously. Thus,
transfer speed is dependent on transmitting and receiving devices only. This design prevents slow master
modules from being handicapped in their attempts to
22PROGAAMMABlE
SERIAL 110
INHRfACE
1I0llNES
ITTLUVELSI
S!RIAL'/O
INTERFACE
lnS232CLEVELS!
~
~
Figure 1. iSBC 80/05 Block Diagram Showing Functional Components
AFN·00260A
iSBC 80/05
Table 1_ Input/Output Modes of Operation
Mode of Operation
Port
Unidirectional
Lines
(qty)
Input
Unlatched
1
8
2
3
8
3
4
3
Output
Latched &
Strobed
X
X
X
X
Latched
X
X
X
X
X
X
Control
Latched &
Strobed
X
X
X1
X2
Notes
1. Port 3 must be used as a control port when port 11s used as a latched and strobed input or a latched and strobed output port.
2. Port 4 must be used as a control port when port 21s used as a latched and strobed Input or a latched and strobed output port.
gain control of the bus, but does not restrict the speed
at which faster modules can transfer data via the same
bus. The most obvious applications for the master-slave
capabilities of the bus are multiprocessor configurations, high speed direct-memory-access (DMA) operations and high speed peripheral control, but are by no
means limited to these three.
Table 2. Programmable Timer Functions
Programmable Timer
The iSSC 80/05 provides a fully programmable binary
14-bit interval timer utilizing the Intel 8155 RAMIIOI
Timer. The system designer simply configures the timer
via software to meet system requirements. Whenever a
given time delay is needed, software commands to the
programmable timer select the desired function. Four
functions are available as shown in Table 2. The contents of the timer counter may be read at any time during system operation.
Serial 110 Interface
The iSSC 80/05 provides serial I/O capability through the
serial input data (SID) and serial output data (SOD) functions of the Intel BOB5A CPU. These functions are controlled exculslvely by software through execution of the
8085A RIM and SIM instructions. The baud rate for the
serial I/O interface is determined by the system time
available for execution of serial I/O support software.
Hence, the maximum baud rate supported by the iSSC
80/05 is solely dependent on the overall system realtime software requirements. Serial I/O signals are TTL
compatible and sockets are provided on the board for
optional connection of RS232C line drivers and receivers.
Function
Operation
Programmable
pulse
Timer out goes low during the
second half of count. Therefore, the
count loaded in the count length
register should be twice the pulse
width desired.
Square wave
rate generator
Timer out will remain high until one·
half the count has been completed,
and go low for the other half of the
count. The count length is automatically reloaded when terminal
count is reached.
Rate generator
Divide by N counter. A repetitive
timer out low pulse is generated and
new timeout initiated every time terminal count is reached.
Programmable
strobe
A single low pulse is generated upon
reaching terminal count. This function is extremely useful for generation of real-time clocks.
instruction at each of these addresses then provides
linkage to locate each interrupt service routine independently anywhere in memory. All interrupt inputs with the
exception of one (TRAP) may be masked via software.
The trap interrupt should be used for conditions such as
power-down sequences which require immediate attention by the 8085A CPU.
Expansion Capabilities
Memory and I/O capacity may be expanded and additional functions added using Intel MULTISUS compatible expansion boards. High speed integer and floatingpoint arithmetic capabilities may be added by using the
iSSC 310A High Speed Mathematics Unit. Memory may
be expanded to 65,536 bytes by adding user specified
combinations of RAM boards, EPROM boards, or combination boards. Inputloutput capacity may be increased
by adding digital I/O and analog I/O expansion boards.
Mass storage capability may be achieved by adding
Interrupt Capability
The ISSC 80/05 takes advantage of the powerful interrupt processing capability of the 8085A CPU. Interrupt
requests are routed to the four interrupt inputs of the
B085A CPU (i.e., TRAP, RST 7.5, RST 6.5, and RST 5.5 in
order of priority, TRAP highest), and each input generates a unique memory address (i.ec, TRAP: 24 16 , RST 7.5:
3C 16, RST 6.5: 34 16, RST 5.5: 2C 16). A single B085A jump
2-9
AFN·00260A
iSBC 80/05
single or double density diskette controllers as subsystems. Modular expandable backplanes and cardcages are available to support multi board. systems.
A unique in-circuit emulator (ICE-85) option provides the
capability of developing and debugging software directlyon the iSBC 80/05.
Systems Development Capability
Programming Capability
The development cycle of iSBC 80/05-based products
may be significantly reduced using an Intellec microcomputer development system. The resident macroassembler, text editor, and system monitor greatly
simplify the design, development, and debug of iSBC
80/05 system software. An optional diskette operating
system provides a relocating macroassembler, a relocating loader and linkage editior, and a library manager.
PL/M-80 - Intel's high level programming language,
PUM, is also available as a resident Intellec microcomputer development system option. PUM provides the
capability to program in a natural, algorithmic language
and eliminates the need to manage register usage or
allocate memory. PUM programs can be written in a
much shorter time than assembly language programs
for a given application.
SPECIFICATIONS
and SIM instructions of the 8085A CPU: Baud rate is
determined by system time available for serial I/O handling. On-board timer may be used to greatly ease serial
I/O timing requirements.
.
Word Size
Instruction - 8, 16, or 24 bits
Data - 8 bits
Interrupts
Cycle Time
Basic Instruction Cycle -
Four-level interrupt routed t08085A CPU interrupt inputs.
Each interrupt automatically vectors the processor to a
unique memory location.
2.03 '"'s, ± 0.1 %
Note
Basic instruction cycle is defined as the fastest instruction (Le., four
clock cycles).
Memory Addressing
ROM/EPROM - O-OFFFH
RAM - 3EOO H
Memory Capacity
Port
Control
8155
Port 1
8t55
Port 2
Address
00
01
02
03
8155 Timer
Low·Order
Byte
8155 Timer
Hlgh·Order
Byte
04
05
Programmable pulse
Square wave rate generator
Rate generator
Programmable strobe
Priority
Type
Highest,
Non-maskable
Maskable
Maskable
Maskable
~
Lowest
Timer/Counter
Min
Max
8.14 ~s
7.50 Hz
7.50 Hz
8.14 ~s
66.67 ms
61.44 kHz
61.44 kHz
133.33 ms
Interfaces
Bus - All signals TTL compatible
Parallel I/O - All signals TTL compatible
Interrupt Request - All TTL compatible (active-low)
Serial 110 - TTL; sockets available for RS232C line
drivers and receivers
1/0 Capacity
Parallel -
24 16
3C16
34 16
2C16
Function
see Table 1
8155
Port
TRAP
RST 7.5
RST 6.5
RST 5.5
Input Frequency Reference...,.. 122.88 kHz ±0.1% (8.14
fls period nominal)
Output FrequencieslTiming Intervals
1/0 Addressing
8155
Ports
3&4
Memory
Address
Timer
On:Board ROM/EPROM- 4K bytes (with Intel 2716) or
2K bytes (with Int(12708)
On-Board RAM - 512 bytes
Off-Board' Expansion - Up to 65,536 bytes in user
specified combination of RAM, ROM, and PROM
On-Board Programmable I/O -
Interrupt
Input
22 programmable lines (see Table 1)
Note
The iSSC 80105 may be expanded to 1102 programmable input/output
lines by using optional iSSC 80 110 boards.
Serial Communications Characteristics
System Clock (SOSSA CPU)
SID and SOD functions of the 8085A CPU are used for
serial I/O. They are controlled by software through RIM
1.966 MHz ± 0.1 %
2-10
AFN·00260A
iSBC 80/05
Line.
(qty)
Center.
(In.)
Bus
86 double·slded
0.156
Viking 2KH4319AMK12
Parallel 110
50 double·slded
0.100
3M 3415·000
Interface
RS232C Drivers and Receivers
Mating Connector
The following RS232C drivers and receivers are compatible with the RS232C socket on the iSBC 80105:
RS232C Driver - National DS1488 or TI SN75188
RS232C Receiver - National DS1490 or TI SN75189
Molex 09·66·1071
Connector
Molex 09·50·7071
Connector
Serial If0'
7 single·sided
0.156
Physical Characteristics
AMP 87194·6
Connector
AMP 3·87025·4
Connector
Width - 12.00 in. (30.49 em)
Height - 6.75 in. (17.15 em)
Depth - 0.50 in. (1.27 em)
Weight - 12.0 OZ (339.8 gm)
Note
1. Connectors and pins from one vendor may only be used with connec-
tors and pins from the same vendor.
Electrical Characteristics
Line Drivers and Terminators
DC Power Requirements
I/O Drivers - The following line drivers are all compatible with the 1/0 driver sockets on the iSBC 80105'
Driver
7438
7437
7432
7426
7409
7406
7403
7400
Characteristic
Sink Current (rnA)
I,oe
I
NI
I,oe
Nl,oe
NI
I,oe
I
Vee= +5V
VDD=+12V4
46
46
16
16
16
16
16
16
VBS=-5V4
VAA= -12V 5
lee=I.60mA
IDD=O
18B=0
IAA=O
With 2716
With 6708
EPROM2
(max)
EPROM3
(max)
2.65A
7 mA5
2.45A
0
23 mA5
90 rnA
137 rnA
23 mA5
Notes
1. Does not include power required for optional EPROMIROM, 1/0
drivers, and 110 terminators.
2. With two Intel 2716 EPROMs and 220QJ330Q terminators Installed
for 22 input ports; aI/ terminator inputs low.
Not.
I = inverting; NI::::: non-inverting; DC:::; open collector.
3. With two Intel 2706 EPROMs and 220Q/330Q terminators installed
for 22 input ports; all terminator inputs low.
I/O Terminators - Intel provides 220Q/330Q divider and
1 kQ pull-up resistive terminator packs for termination
of 1/0 lines programmed as inputs. These options are as
follows:
4. Required for 2706 EPROMs.
5. Required only when RS232e capability required.
+5V--==;---
Environmental Characteristics
O·C to + 55·C.
220Q
~----,
Operating Temperature -
330Q
220Q/330Qr
_ - - - . . L - - - < o iSBC 901 OPTION
Reference Manual
1 kQ
1 kQ
Without
PROMl
(max)
Voltage
(±S%)
+ 5V ----~Vv'.r-------O
iSBC 902 OPTION
9800483D - iSBC 80105 Hardware Reference Manual
(NOT SUPPLIED)
Bus Drivers
Driver
Data
Address
Commands
Characteristic
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Sink Current (rnA)
Tri·sldle
Trl·stat.
Trl·stc·e
50
50
32
ORDERING INFORMATION
Part Number
Description
SBC 80105
Single Board Computer
2-11
AFN·00260A
iSBC™80/10B (or pSBC 80/10B*)
SINGLE BOARD COMPUTER
• Programmable synchronous/asynchro·
nous communications interface with
selectable RS232C or teletypewriter
compatibility
• Upward compatible with iSBC™ 80110A
Single Board Computer
• 8080A CPU used as central processing
unit
• One iSB)(TM bus connector for iSB)(TM
MULTIMODULfTMboard expansion
• Single level interrupt with 11 interrupt
sources
• 1 K byte of read/write memory with
• Auxiliary power bus and power·fail
interrupt control logic for RAM battery
backup
sockets for expansion up to 4K bytes
• Sockets forup to 16K bytes of read
only memory
• 48 programmable parallel 1/0 lines
with sockets for interchangeable line
drivers and terminators
• 1.04 millisecond interval timer
• Limited master MULTIBUS® interface
The Intel® iSBC 80/10B board is a member of Intel's complete line of OEM microcomputer systems which
take full advantage of Intel's LSI technology to provide economical, self-contained computer-based
solutions for OEM applications. The iSBC 80/10B board is a complete computer system on a single 6.75 x
12.00-inch printed circuit card. The CPU, system clock, iSBX bus interface, readlwrite memory, read only
memory sockets, 1/0 ports and drivers, serial communications interface, bus control logic, and drivers all
reside on the board.
'Same product, manufactured by Intel Puerto Rico, Inc.
2-12
AFN·01688A
iSBC 80/10B
on-board expansion with small iSBX boards. One
iSBX bus connector interface is prdvided to
accomplish plug-in expansion with any iSBX
MUL TIMODULE board. iSBX boards are available
to provide expansion equivalent to the I/O available
on the iSBC 80/10B board or the user may configure
entirely new functionality such as math directly onboard. The iSBX 350 programmable I/O MUL TIMODULE board provides 24 I/O lines using an
8255A programmable peripheral interface. Therefore, the iSBX 350 module together with the iSBC
80/10B board may offer 72 lines of programmable
I/O. Alternately, a serial port may be added using
the iSBX 351 serial I/O multimodule board or math
may be configured on-board with the iSBX 332
floating point math MUL TIMODULE board.
FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel MOS 8080A CPU,
fabricated on a single LSI chip, is the central
processor for the iSBC 80/10B board. The 8080A
contains six 8-bit general purpose registers and an
accumulator. The six general purpose registers
may be addressed individually or in pairs, providing
both single and double precision operators. A block
diagram of iSBC 80/10B board functional components is shown in Figure 1.
iSBX Bus MULTIMODULE Board
Expansion
The new iSBX bus interface brings an entirely new
dimension to system design offering incremental
R5232C
COMPATIBLE
,0
"_'M~"~O
o""~
S ERIAL
DATA/CONTROL
DATA/CON TROL
INTER FACE
PARALLEL 110 LINES
INTERFACE
AS232C
TIY
INTERFACE
INTERFACE
8AUD RATE
SELECTOR
(JUMPERS)
POWER
FAIL
INTERRUPT
'Yi~"
R
3
I
\/
1
1
1,)2
INf~~A,:,=-
II
II
II
I
-
us
~~~
AR:D
is ex BUS
MUl TIMODULE
CONNECTOR
L-J+ __/\
-
l,[
INTERRUPT SELECTOR
(JUMPERS)
I
\I
1K x 8 RAM
(SOCKETS TO
4K II 8)
PROGRAMMABLE
COMMUNICATIONS
INTERFACE (USARTl
{~
f~
PROGRAMMABLE
PERIPHERAL
INTERFACES
8080A
CPU
'~
{~
ON-BOARD SYSTEM BUS
I
MULTIBUS
INTERFACE
<
BOARD
.no~O
.--
,---,
SELECTED
0
TERMINATOR
INTERFACE
/\
l f
16K II a
ROM/EPROM
(SOCKETS)
DRIVERI
1.04 MSEC
INTERVAL
TIMER
_.
USER DESIGNATED
Isex MUL TIMODULE
USER
DESIGNATED
PERIPHERALS
TIY
V
J
MULTIBUS· SYSTEM BUS
..
..
Figure 1. iSBC™ 80110B Single Board Computer Block Diagram
2-13
AFN-016BBA
iSBC80/10B
in 2K byte increments up to 8K bytes(using Intel
2716); or in4Kbyte increments.up to 16Kbytes (using Intel 2732). All on-board RoM or EPROM read
operations are performed at maximum processor
speed. .
The iSBX board is a logical extension of the onboard programmable I/O and is accessed by the
iSBC 80/10B single board co'mputer as common
I/O port locations. The iSBX board is coupled
directly to the8080A CPU and therefore becomes
an integral element of the iSBC 80/1 OB single board
computer providing optimum performance.
\
Parallel 1/0 interface
The iSBC 80/10B board contains 48 programmable
parallel I/O lines implemented using two Intel
8255A programmable peripheral interfaces. nie
system software is used.to configure the I/O lines in
any combination of unidirectional input/output,
and bidirectional ports indicated in Table 1. Therefore,the I/O interface may be customized to meet
specific peripheral requirements, In order to take
full advantage of the large number of possible I/O
configurations, sockets are provided for interchangeable I/O line drivers anq terminators. Hence,
the flexibility of the I/O interface is further enhanced
by the capability of selecting the appropriate
combination of optional line drivers and terminators
to provide the required sink current,polarity, and
drive/termination characteristics for each, application. The 48 programmable I/O lines and signal
ground lines are brought out to two 50-pin edge
connectors that mate with flat cable or round cable.
Memory Addressing
The 8080A has a 16-bit program counter which
allows direct addressingofupt064K bytes of
memory. An external stack, located within any
portion of read/write memory, may be used asa
last-in/first-out storage area for the contents of the
program counter, flags, accumulator, and all of the
six general purpose registers. A 16-bit stack pointer
controls the addressing of this external stack. This
stack provides subroutine nesting bounded only by
memory size.
Memory Capacity
The iSBC 80/10B board containS 1K bytes of
read/write static memory. In addition, sockets for
up to 4K bytes of RAM memory are provided on
board ... Read/write memory may be added in 1K
byte increments using two 1K x 4 Intel 2114A-5
static RAMs. All on-board RAM read and. write
operations are performed at maximum processor
speed. Sockets for up to 16K bytes of nonvolatile
read-only-memory are provided on the board.
Read-only-memory may be added in 1 K byte increments up to 4K bytes (using Intel 2708 or 2758);
Serial 1/0 Interface
A programmable communications interface using
the Intel® 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on the board. A jumper selectable baud rate
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port
'.
Lines
(qty)
Input
Output
Unlatched
Latched &
Strobed
Latched
Bidirectional
Latched &
Strobed
1
8
X
X
X
X
2
8
X
X
X
X
3
8
X
X
4
8
X
X
5
8
X
X
6
4
X
4
X
Control
!
X
XI
X
X
..
......
Notes
Port 3 must be used as a control portwhen either port 1 or port2 are used asa latched and strobed input or a latched and strobed output
port or port 1 is used as a bidirectional port.
.
d
2-14
•
AFN·01666A
iSBcaO/10B
generator provides the USART with all common
communications frequencies. TheUSART can be
programmed by the system software to select the
desired synchronous or asynchronous serial data
transmission technique (including IBM BicSync).
The mode of operation (i.e., synchronous or asynchronous), data format, control character format
and parity are all under program control. The 825.1A
provides full duplex, double-buffered transmit and
receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The inclusion of jumper selectable TTY or RS232C
compatible interfaces on the board, In conjunction
with the USART, provides a direct interface to
teletypes, CRTS, RS232C compatible cassettes, and
asynchronous and synchronous modems. The
RS232C or TTY command lines, serial data lines,
and signal ground lines are brought out to a 26-pin
edge connector that mates with RS232C compatible flat or round cable.
Interrupt. Capability
Interrupt requests may originate from 11 sources.
Two jumper selectable interrupt requests can be
automatically generated by the programmable
peripheral interface when a byte of information is
ready to be transferred to the CPU (i.e., input buffer
is full) or a byte of information has been transferred
to a.peripheral device (i.e., output buffer is empty).
Three jumper selectable interrupt requests can be
automatically generated by the USART when a
character is ready to be transferred to the CPU (i.e.,
receive channel buffer is full), a character is ready
to be transmitted (i.e., the USART is'ready to accept
a character from the CPU), or when the .transmitter
is empty (i.e., the USART has no character to
transmit). These five interrupt request lines are all
maskable under program control. Two interrupt
request lines may be interfaced directly to user
designated peripheral devices; one via the MLJLTIBUS system bus and the other via the I/O edge
connector. One jumper selectable interrupt request
may be interfaced to the power-fail interrupt
control logic. One jumper selectable interrupt
request may originated from the interval timer.Two
general purpose interrupt requests are' jumper
selectable from the iSBX interface. These two
signals permit a user installed MUL TIMODULE
board to interrupt the 8080A CPU. The eleven
interrupt request lines share a single CPU interrupt
level. When an interrupt request is recognized, a
restart instruction (RESTART 7) is generated. The
processor responds by suspending program execution and executing a user defined interrupt service
routine originating at location 3816.
2-15
Power-Fail Control
A power-fail interrupt may be detected through the
AC-Iow signal generated by the powersupply. This
signal may be configured to interrupt the 8080A
CPU to initiate an orderly power down instruction
sequence.
Interval Timer
A 1.04 millisecond timer is available for interval
interrupts or as a clock output to the parallel 1/0
connector. The timer output is jumper selectable to
the programmable parallel interface,. the parallel
I/O connector (J1), or directly to the 8080ACPU.
MULTIBUS®System
Expansion Capabilities.
Memory and I/O capacity may be expanded and
additional functions added using Intel MUL TIBUS'·
system compatible expansion boards. Memory may
be expanded to 65,536 bytes by adding user specified combinations of RAM boards, EPROM boards,
or combination boards. Input/output capacity may
be increased by adding digital 1/0 and analog 1/0
expansion boards. In addition, the iSBC 80/10B
board performs as a I.imited bus master in that it
must occupy the lowest priority when used with
other MUL TIBUS masters. The bus master may
take control of the MUL TIBUS system bus by halting the iSBC 80/10B board program execution. Mass
storage capability may be achieved by adding single
density diskette, double density diskette, or hard
disk controllers. Modular exp'1ndable backplanes
and cardcages are available to support multiboard
systems.
Real-Time Software
The iRMX 80 executive, which contains all major
real-time facilities including priority-based system
resource allocation, intertask communication and
control, interrupt driven control for·s·tandard I/O
devices, and interrupt handling, occupies 2K bytes
of memory which can be stored on-board in
EPROM. Optional linkable and relocatable
modules for console control (CRT orTTY), disk file
system, and analog subsystems are provided with
the iRMX 80 package. User configurability is aided
on the Intellec ·microcomputer development
system by the Interactive Configuration Utility program provided with the iRMX 80 package.
.
System Development Capability
The development cycle of iSBC 80/10B-based
products may be significantly reduced using Intel's
system development tools available today. The
AFN·01668A
iSBC 80/10B
or
Intellec Series II family of compatible microcomputer development systems p,rovides a range of
capability from a low cost disk-pased edit debug
workstation to a high performance, fully compatible
hard-disk-based software development system.
Also, a unique in-circuit emulator (ICE-BO) option
provides the capability of developing and debugging software directly on the iSBC BO/1 DB board.
with PUM
assembly language program
modules. In addition, theiSBC B01 FORTRAN-BO
run-time package is a complete, ready-to-use set
of linkable object modules which are fully com,
patible with iRMX80 systems. The modules, when
combined with tHe FORTRAN-BO coded applica'
tion, provide the appropriate interfaces tothedisk
file and terminal 1/0 of iRMX BO, and to theiSBC
310A Math Unit for applications requiring high
speed math.
Programming Capability
BASIC-80 - A high level language Interpreter is
available with extended disk capabilities which
operates under the iRMX BO Real-Time Multitasking Executive and translates BASIC-BO source programs into an internaliy executable form. This
language interpreter, provided as a set of linkable
object modules, is ideally suited to the OEM who
requires a pass through programming language.
The BASIC-BO programs maybe created; stored,
and interpreted on the iSBC 80 based systems using the iSBC 802 BASIC-SO Configurable iRMX 80
Disk-Based Interpreter. The iSSC 802 Interpreter
has a complete ready-to-use set of linkable object
modules which are fully compatible with Intel's
iRMX 80 Real-Time Multitasking Executive Software. The modules provide interfaces to disk file
and terminal 1/0, softwC/-re floating point, or interface to other routines provided by the user.
PLlM-80 "- Intel's high level programming language, PL(M, is also available as a resident Intellec
microcomputer development system option. PLiM
provides the capability to program in a natural,
algorithmic language and eliminates the need to
manage register usage or allocate memory. PLiM
programs can be written in a much shorter time
than assembly language programs for a given
application.
FORTRAN-80 - For applications requiring computational and formatted 1/0 capabilities, the ANSI 77
standard high level FORTRAN-BO programming
language is available as a resident option of the
Intellec system. The FORTRAN compiler produces
relocatable object code that may be easily linked
On-Board RAM
1K byte with user expansion in lK increments
to 4K bytes using Intel 2114A-5RAMs
SPECIFICATIONS
Word Size
Instruction - 8, 16, or 24 bits
Data '-' 8 bits
Off-Board Expansion
. Up to 64K bytes using user specified combinations of RAM, ROM, and EPROM.
Cycle Time
Basic Instruction Cycle -
1/0 Addressing
1.. 95 f-/Sec
On-Board Programmable 1/0
Note
Basic instruction cycle is defined as the fastest instruction (i.e.,
four clock cycles).
Device
Memory Addressing
On-Board
O-OFFF
0-1 FFF
0-3FFF
ROM/EPROM
using 2708, 2758
using 2716
using 2732
1/0
Address
8255A No.1
Port A
Port B
Port C
Control
8255A No.2
Port A
On-Board RAM
3COO-3FFF with no RAM expansion
3000-3FFF with 2114A-5 expansion
Port B
Port C
Control
Note
All RAM configurations are automatically moved up to a base
address of 4XXX when configuring EPROM for 2732.
E4
E5
E6
E7
E8
E9
EA
EB
8251A
Data
Control
Memory Capacity
iSBX -Multimodule
MCSO
MCS1
On-Board ROM/EPROM
16K bytes (sockets only)
2-16
EC
ED
FO-F7
F8-FF
AFN·01688A
iSBC 80/10B
I/O Capacity
Interfaces
Parallel - 48 programmable lines
Serial - 1 transmit, 1 receive
MUL TIMODULE - 1 iSBX Bus MUL TIMODULE
Board
MUL TIBUS iSBX Bus -
All signals TTL compatible
All Signals TTL compatible
Parallel I/O -
Serial Baud Rates
Serial I/O - RS232Cor a 20 mil current loop TTY
interface (jumper selectable)
Baud Rate (Hz)
Frequency (kHz)
(Jumper Setectable)
All signals TTL compatible
Synchronous
Interrupt Requests - All TTL compatible (activelow)
Asynchronous
(Program Selectable)
307.2
153.6
76.8
38.4
19.2
9.6
6.98
4.8
-
38400
19200
9600
6980
4800
-;- 16
19200
9600
4800
2400
1200
600
300
-;- 64
4800
2400
1200
600
300
150
110
75
Clocks
System Clock -
2.048 MHz ± 0.1 %
Interval Timer -
1.042 msec
± 0.1 % (959.5 HZ)
Connectors
Serial Communications Characteristics
Synchronous '- 5-8 bit characters; internal or external character synchronization; automatic sync
insertion
Asynchronous - 5-8 bit characters; break character generation; 1, 1'h, or 2 stop bits; false start bit
detectors
Double·Slded
Pins
(qty)
Interface
Centers
(In.)
Mating Connectors
Viking 2KH43/9AMK12
Wlre·wrap
MULTIBUS
System
86
0.156
ISBX Bus
36
0.1
ISBX 960·5
Parallel 1/0 (2)
50
0.1
3M 3415'()00
Flat
Serial 1/0
26
0.1
AMP 87194·6
Flat
Interrupts
Single-level with on-board logic that automatically
vectors the processor to location 38H using a restart instruction (REST ART7). I nterru pt req uests
may originate from user specified I/O (2); the programmable peripheral interface (2); the iSBX MULTIMODULE board (2); the programmable communications interface (3); the power fail interrupt (1);
or the interval timer (1).
Physical Characteristics
Width -
12.00 in. (30.48 cm)
Height -
6.75 in. (17.15 cm)
Depth -
0.05 in. (1.27 cm)
Weight -
14 oz. (484.4 gm)
Electrical Characteristics
DC Power Requirements
Voltage
Without EPROM 1
= +5V ±5%
= +12V ±5%
Vse = -5V ±5%
100
VAA = -12\1 ±5%
Vee
Voo
= 2.0A
= 150 rnA
With 2708 EPROM 2
14ee
=1~~;;~p:~:3
Power Down Requirements
(RAM and Support Circuit)
3.1 A
3.46 A
84 mA + 140 rnA/K (2114A-5)
400 mA
150 rnA
Not Required
IBe = 2 rnA
200 rnA
2 mA
Not. Required
lAA = 175 rnA
175 rnA
175 rnA
Not Required
NOTES:
1. Does not include power required for optional ROM/EPROM, 1/0 drivers, or 1/0 terminators.
2. With four Intel 2708 EPA OMS and 2200/3300 for terminators, installed for 48 input lines. All terminator inputs low.
3. Same as #2 except with four 2758s, 2716s, or 2732s installed.
4. Icc shown without RAM supply current. For 2114A-5 add 140 mA per K byte to a maximum of 560 mA.
2-17
AFN.Q16BBA
iSBC80/10B
Line Drivers and Terminators
MULTIBUS Drivers
1/0 Drivers - The following line drivers and terminators are all compatible with the liD driver sockets
on the iSBC 80/108 Board:
Driver
Characteristic
Sink Current (mAl
7438
7437
7432
'7426 '
7409
7408
7403
7400
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I
48
48
16
16
16
16
16
16
Function
Characteristic
Sink Current (mAl
25
Data
Tri~State
Address
Tri-Stat.
25
Commands
Tri-State
25
Environmental Characteristics
Operating Temperature -
Note
I - inverting, NI - non-inverting, OC - open collector.
O°C to 55°C
Equipment Supplied
iSBC 80/10B Single Board Computer
iSBC 80/10B Schematics
Port 1 has 25 nA totem pole drivers and 1 kO terminators.
1/0 Terminators - 2200/3300 divider or 1 kO pull
up.
Reference Manual
9803119-01 - iSBC 80/10B Single Board Computer
Hardware Reference Manual (NOT SUPPLIED). ,
Manuals may be ordered from any Intelsales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
Cal iforn ia 95051.
1kQ
1.U + 5 - - -.....rvv"-·_ _ _ _ _ _ _ _-00 SBCt020PTIO""
ORDERING INFORMATION
Part Number
SBC 80/10B
Description
Single Board Computer
2-18
AFN·01688A
iSBC 80/20-4 (or pSBC 80/20-4*)
SINGLE BOARD COMPUTER
• Full MULTIBUS control logic allowing
up to 16 masters to share system bus
• 8080A CPU used as central processor
• 4K bytes of static read/write memory
• Two programmable 16-bit BCD and
binary timers
• Sockets for up to 8K bytes of erasable
reprogram mabie or masked read only
memory
• Eight-level programmable interrupt
control
• 48 programmable parallel 1/0 lines with
sockets for interchangeable line drivers
and terminators
• Compatible with optional memory and
1/0 expansion boards
• Programmable synchronous/asynchronous RS232C compatible serial.
interface with fully software selectable
baud rate generation
• Auxiliary power bus, memory protect,
and power-fail interrupt control logic
provided for battery backup RAM
requirements
The iSBC 80/20-4 Single Board Computer is a member of Intel's complete line of OEM computer systems which take
full advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for OEM
applications. Each iSBC 80/20-4 is a complete computer system on a single 6.75 x 12.00-inch printed circuit card. The
CPU, system clock, read/write memory, nonvolatile read only memory, 110 ports and drivers, serial communications
interface, priority interrupt logic, two programmable timers, MULTI BUS control logic, and bus expansion drivers all
reside on each board.
'Same product, manufactured by Intel Puerto Rico, Inc.
2-19
AFN-01499A
iSBC 80120-4
memory may be added in 1K-byte increments using Intel
2708 erasable and electrically reprogrammable ROMs
(EPROMs), or read only memory may be added in 2K-byte
increments using Intel 2716 EPROMs_ All on-board ROM
read operations are performed at maximum processor
speed.
FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel MOS 8080A CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 80/20-4_ The 8080A contains six 8-bit general
purpose registers and an accumulator. The six general
purpose registers may be addressed individually or in
pairs, providing both Single and double precision operators_ Minimum instruction execution time is 1_86 . microseconds. A block diagram of iSBC 80/20-4 functional
components is shown in Figure 1.
Parallel 1/0 Interface
The iSBC 80/20-4 contains 48 programmable parallel I/O
lines implemented using two Intel 8255 programmable
peripheral interfaces. The system software is used to
configure the I/O lines in any combination of the unidirectional input/output, and bidirectional ports indicated in Table 1. Therefore, the I/O interface may be
customized to meet specified peripheral requirements.
In order to take full advantage of the large number of
possible I/O configurations, sockets are provided for interchangeable I/O line drivers and terminators. Hence,
the flexibility of the I/O interface is further enhanced by
the capability of selecting the appropriate combination
of optional line drivers and terminators to provide the
required sink current, polarity, and drive/termination
characteristics for each application. The 48 programmable I/O lines and Signal ground lines are brought out
to two 50-pin edge connectors that mate with flat,
woven, or round cable.
Memory Addressing
The 8080A has a 16-bit program counter which allows
direct addressing of up. to 65,536 bytes of memory. An
external stack, located within any portion of read/write
memory, may be used as a last-in/first-out storage area
for the contents of the program counter, flags, accumulator, and all of the six general purpose registers. A
16-bit stack pointer controls the addressing of this
external stack. This stack provides subroutine nesting
bounded only by memory size.
Memory Capacity
The iSBC 80/20-4 contains 4K bytes of static read/write
memory using Intel low power static RAMs. All on-board
RAM read and write operations are performed at maximum processor speed. Power for on-board RAM memory is provided on an auxiliary power bus, and memory
protect logic is included for battery backup RAM requirements. Sockets for up to 8K bytes of nonvolatile
read only memory are provided on the board. Read only
Serial 1/0 Interface
A programmable communications interface using
Intel's 8251 Universal Synchronous/Asynchronous ReceiverlTransmitter (USART) is contained on the iSBC
HSt3~C
COMPATIBl£
mVICE
2
PROGRAMMABLE
TIMERS
r~~~__L
8 INTERRUPT
ADDRESS BUS
Rt::)oUESTLlNfS
SBe 80
DATA BUS
' -_ _ _- - ' CONTROL BUS
SYSTEM
BUS
Figure 1_ iSBC 80/20 and iSBC 80/20-4 Block Diagram Showing Functional Components
2-20
AFN-01499A
iSBC 80/20·4
80120-4 board. A software selectable baud rate generator
provides the USART with all common communications
frequencies. The USART can be programmed by the system software to select the desired asynchronous or synchronous serial data transmission technique (including
IBM Bi-Sync). The mode of operation (i.e., synchronous
or asynchronous), data format, control character parity,
and baud rate are all under program control. The 8251
provides full duplex, double-buffered transmit and
receive capability. Parity, overrun, and framing error detection are all incorporated in the USART. The RS232C
compatible interface on each board, in conjunction with
the USART, provides a direct interface to RS232C compatible terminals, cassettes, and asynchronous and synchronous modems. The RS232C command lines, serial
data lines, and Signal ground line are brought out to a
26-pin edge connector that mates with RS232C compatible flat or round cable.
bus control is attained, a bus bandwidth of up to 5M
byteslsec may be achieved.
The bus controller provides its own clock which is
derived independently from the processor clock. This
allows different speed controllers to share resources on
the same bus, and transfers via the bus proceed asynchronously. Thus, transfer speed is dependent on transmitting and receiving devices only. This design prevents
slow master modules from being handicapped in their
attempts to gain control of the bus, but does not restrict
the speed at which faster modules can transfer data via
the same bus. Once a bus request is granted, single or
multiple readlwrite transfers can proceed at a maximum
rate of 5 million data words per second. The most obvious applications for the master-slave capabilities of the
bus are multiprccessor configurations, high speed
direct-memory-access (DMA) operations and high speed
peripheral control, but are by no means limited to these
three.
Multimaster Capability
Programmable Timers
The iSBC 80120-4 is a full computer on a Single board
with resources capable of supporting the majority of
OEM system requirements. For those applications requiring additional processing capacity and the benefits
of multiprocessing (i.e., several CPUs andlor controllers
logically share system tasks with communication over
the system bus), the iSBC 80120-4 provides full MULTIBUS arbitration control logic. This control logic allows
up to three iSBC 80120-4 or high speed controllers to
share the. system bus in serial (daisy chain) priority
fashion, and up to 16 masters may share the system bus
with the addition of an external priority network. Once
The iSBC 80120-4 board provides three fully programmable and independent BCD and binary 16-bit interval
timerslevent counters utilizing an Intel 8253 Programmable Interval Timer. Two of these timerslcounters are
available to the systems designer to generate accurate
time intervals under software control. Routing of these
counters is jumper selectable. Each may be independently routed to the programmable interrupt controller,
the 110 line drivers and terminators, or outputs from the
8255 programmable peripheral interfaces. The third interval timer in the 8253 provides the programmable baud
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines
(qty)
Input
Unlatched
Latched
Latched &
Strobed
1
8
X
X
X
X
2
8
X
X
X
X
3
I
Bidirectional
Output
Latched &
Strobed
Control
X
4
X
X
X,
4
X
X
X,
X
4
8
X
X
X
X
5
8
X
X
X
X
6
4
X
X
X2
4
X
X
X2
Notes
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output
port or port 1 is used as a bidirectional port.
2. Part 01 port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output
port or port 4 is used as a bidirectional port.
2-21
AFN·01499A
iSBC 80/20-4
assignments may be reconfigured dynamically via software at any time during system operation_ The PIC
accepts interrupt requests from the programmable
parililel and. serial I/O interfaces, the programmable
timers, the system bus, or directly from peripheral
equipmenL The PIC then determines which of the
incoming requests is of the highest priority, determines
whether this request is. of higher priority than the .Ievel
currently being serviced, and if appropriate, issues an
interrupt to the CPU. Any combination of interrupt levels
may be masked through storage via software, of a single
byte to the interrupt register of the PIC.
rate generator for the iSBC 80/20-4 RS232C USART
serial port. In utilizing the iSBC 80/20-4, the systems
designer simply configures, via software, each timer independently to meet system requirements_ Whenever a
given time delay. or count is f]eeded,· software commands to the programmable timers/event counters
select the desired function. Sever) functions are available, as shown in Table 2. The contents pf each counter
may be read at any time during system operation with
simple read operations for. event counting applications,
and special commands are included so that the contents of each counter can be used "on the fly".
Table 2. Programmable Timer Functions
Function
Table 3. Programmable Interrupt Modes
~--~----~---.-
.' Operation
Interrupt on
terminal count
When terminal count is reached, an
interrupt request is generated_ This
function is extremely useful for
generation of real-time clocks.
Programmable
one-shot
Output goes low upon receipt of an
external trigger edge or software
command and returns high when
terminal count is reached. This
function is retriggerable_
Rate
generator
Divide by N counter. The output wi.11
go low for one input clock cycle,'
and. the period from one low-going
pulse to the next is N times theinput clock period.
Square-wave
rate generator
Output will remain high until onehalf the count has beencompleted,
and go low for the other half of the
count.
Software
triggered
strobe
Output remains high until software
loads count (N). N counts after
count is loaded, output goes low for
one input clock period_
Hardware
triggered
strobe
Output goes low for one clock
period N counts after rising edge on
counter trigger input. The counter
is retriggerable.
Event counter
On a j~ri1per selectable basis, the
clock input becomes' an input from
the external system_ CPU may read
the number of events occurring
after the counting ;'window" has
been enabled or an interrupt may be
generated after N events occur in
the system.
Interrupt Capability
Operation and Priority Assignments - An Intel 8259
Programmable Interrupt Controller (PIC) provides vectoring for eight interrupt levels. As shown in Table 3, a
selection of four priority processing modes is available
to the systems designer so that the manner in which
requests are processed may be configured to match
system requirements. Operating mode and priority
Mode
- _ .. ---
Operation
f-------+-----c-.- --------'---- .-...- - - - - -
Fully
nested
Interrupt request line priorities fixed at O.
as highest, 7 as lowest.
Autorotating
Equal priority. Each level, after receiving
service, becomes the lowest priority level
until the next interrupt occurs.
Specific
priority
System software assigns lowest priority
level. Priority of all other levels based in
sequence numerically on this assignment.
Polled
System software examines priority-encoded system interrupt status via interrupt status register.
Interrupt Addressing -'- The PIC generates a unique
memory address for each interrupt level. These addresses are equally spaced at intervals of 4 or 8 (software
selectable) bytes. This 32- or 64-byte block may be
located to begin at any 32- or 64-byte boundary in the
65,536-byte memory space. A Single 8080 jump instruction at each of these addressed then provides linkage to
locate each interrupt service routine independently any·
where in memory.
Interrupt Request Generation - Interrupt requests may
originate from 26 sources. Four jumper selectable interrupt requets can be automatically generated by the programmable peripheral interface when a byte of information is ready to be transferred to the CPU (i.e., input buf. fer is full) or a byte of information has been transferred
to a peripheral device (i.e_, output buffer is empty)_ Two
jumper selectable interrupt requests can be automatically generated by the USART when a character is ready
to be transfer to the CPU (i.e., receive channel buffer is
full), or a character is ready to be transmitted (i.e., transmit channel data buffer is empty)_ A jumper selectable
request can be generated by each of the programmable
timers. Nine additional interrupt request lines are avail. able to the user for direct interface to user designated
peripheral devices via the system bus, and eight interrupt request lines may be jumper routed directly from
peripherals via the parallel I/O driver/terminator section:
Power'Fail Control -'- Control logic is also included for
generation of a power-fail interrupt which works in conjunction with the AC·low signal from iSBC635 Power
Supply or equivalent.
2-22
AFN·01499A
iSBC 80/20-4
software directly on the iSBC B0/20-4 single board computer.
Expansion Capabilities
Memory· and 110 capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. High speed integer and floatingpoint arithmetic capabilities may be added by using the
iSBC 310A High Speed Mathematics Unit. Memory may
be expanded to 65,536 bytes by adding user specified
combinations of RAM boards, EPROM boards, or combination boards. Inputloutput capacity may be increased
by adding digital 1/0 and analog 1/0 expansion boards.
Mass storage capability may be achieved by adding
single or double density diskette controllers as subsystems. Modular expandable backplanes and cardcages
are available to support multiboard systems.
Programming Capability
PUM-80 - Intel's high level programming language,
PUM, is also available as a resident Intellec microcomputer development system option. PUM provides the
capability to program in a natural, algorithmic language
and eliminates the need to manage register usage or
allocate memory. PUM programs can be written in a
much shorter time than assembly langauge programs
for a given application.
FORTRAN·80 - For applications requiring computational and formatted 1/0 capabilities, the high level
FORTRAN·BO programming language is also available
as a resident option of the Intellec system. The FORTRAN compiler produces relocatable object code that
may be easily linked with PUM or assembly language
program modules. This gives the user a wide flexibility
in developing software.
Real-Time Software
The iSBC 80/20-4 is totally compatible with Intel's iRMX
80 Real-Time Multi-Tasking Executive. iSBC 80/20-4
based user programs (tasks) can take advantage of the
iRMX BO executive to do all necessary scheduling, intertask communication, and memory space allocation.
iRMX BO also provides standard 1/0 support software
such as disk file handling, Intel analog board handling,
and terminal handling.
BAsrC-80 - A high level language interpreter with
extended disk capabilities which operates under the
RMX/BO Real·Time Multi-Tasking Executive and translates BASIC-BO source programs into an internally executable form. This language interpreter, provided as a
set of linkable object modules, is ideally suited to the
OEM who requires a pass through programming Ian·
guage. The BASIC-BO programs may"be created, stored
and interpreted on the iSBC 80 based system. The
BASIC-BO language has a rich complement of statements, functions, and commands to programapplications requiring a full range of 1) string manipulation and
disk 110 for data processing, 2) Single and double precision floating point and array handling for numeric analysis, or 3) port 1/0 with mask operations controlled
through bit-wise Boolean logical operators.
System Development Capability
The development cycle of iSBC B0/20-4 based products
may be significantly reduced using an Intellec microcomputer development system. The resident macroassembler, text editor, and system monitor greatly
simplify the design, development, and debug of iSBC
B0/20-4 system software. An optional diskette operating
system provides a relocating macroassembler, a relocating loader and linkage editor, and a library
manager. A unique in·circuit emulator (ICE-BO) option
provides the capability of developing and debugging
SPECIFICATIONS
Memory Capacity
On-Board ROMIEPROM - BK bytes (sockets only)
Word Size
On-Board RAM -
Instruction _ B, 16, or 24 bits
Data - B bits
Cycle Time
Basic Instruction Cycle Nole
Basic instruction cycle
clock cycles).
1.B6
Nole
ROM/EPROM may be added in 1K or 2K·byte increments.
flS
!s defined as the fastest
instruction (Le., four
I/O Addressing
On-Board Programmable 1/0 (see Table 1)
Memory Addressing
On-Board ROMIEPROM (2716)
4K bytes
Off-Board ExpanSion - Up to 65,536 bytes in user specified RAM, ROM, and EPROM
O-OFFF (270B) or 0-1 FFF
8255 No.1 8255 No.2
Port
On-Board RAM - 4K bytes ending on a 16K boundary
(e.g., 3FFF H ,7FFF H , BFFFH , ... FFFF H)
Address
2-23
1 1213
41 5 1 6
E41E51E6
EsI E9 1EA
8255
No.1
8255
No.2
Control Control
E7
EB
USART USART
Oala Control
EC
ED
AFN·01499A
iSBC 80120·4
Output FrequenclesfTImlng Intervals
1/0 Capacity
Parallel -
48 programmable lines (see Table 1)
Single Timer/Counter
Function
Note
Expansion to 504 input and 504 output lines can be accomplished using
optional 1/0 boards.
Dual Timer/Counter
(Two Timers Cascaded)
Min
Max
Min
Real-time
interrupt
1.86.s
60.948 ms
3.72.s
1.109 hr
Programmable
one-shot
1.86.s
60.948 ms
3.72.s
1.109 hr
Rate generator
16.407 Hz
537.61 kHz
0.00025 Hz
268.81 kHz
16.407 Hz
537.61 kHz-
0.00025 Hz
268.31 kHz
Asynchronous - 5-8 bit characters; break character
generation; 1,1112, or 2 stop bits; false start bit detection
Square-w'ave
rate generator
Software
triggered
strobe
1.86.s
60.948 ms
3.72 ,s
1.109 hr
Baud Rates
Hardware
triggered
strobe
1.86."
60.948 ms
3.72.s
1.109 hr
Serial Communications Characteristics
Synchronous - 5-8 bit characters; internal or external
character synchronization; automatic sync insertion
Frequency (kHz)
(Software Selectable)
Baud Rate (Hz)
Synchronous
-
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
38400
19200
9600
4800
2400
1760
Asynchronous
-;- 16
-;- 64
9600
4800
2400
1200
600
300
150
110
2400
1200
600
300
150
75
Max
Interfaces
Bus - All Signals TTL compatible
Parallel I/O - All signals TTL compatible
Interrupt Requests - All TTL compatible
Timer - All Signals TTL compatible
Serial I/O - RS232C compatible, data set configuration
-
System Clock (808OA CPU)
-
2.1504 MHz ±0.1%
Note
Freque'ncy selected by 110 write of appropriate 16·bit frequency factor to
baud rate register.
Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.
Register Address (hex notation, I/O address space)
DE Baud rate register
Note
Baud rate factor (16 bits) is loaded as two sequential output operations
to same address (DEH).
Memory Protect
An active-low TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on
the board. This input is provided for the protection of
RAM contents during system power-down sequences.
Interrupts
Register Addresses (hex notation, I/O address space)
DA Interrupt request register
DA In-service register
DB Mask register
DA Command register
DB Block address register
DA Status (polling register)
Connectors
DoubleSided Pins
(qty)
Centers
(In.)
MULTIBUS
System
Bus
86
0.156
ELFAB BS1562043PBB
Viking 2KH43/9AMK12
Soldered PCB Mount
EDAC 337086540201
ELFAB BW1562D43PBB
EDAC 337086540202
ELFAB BW1562A43PBB
Wire Wrap
Auxiliary
Bus
60
0.100
EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB
Wire Wrap
Paraliell/O
(2 )
50
0.100
3M 3415-001 Flat Crimp
GTE Sylvania
6AD01251A1DD
Soldered
Serial 1/0
26
0.100
. AMP 15837151
EDAC 345026520202
PCB Soldered
3M 3462-0001
AMP 88373-5 Flat Crimp
Interface
Note
Several registers have the same physical address; sequence of access
and one data bit of control word determine which register will respond.
Timers
Register Addresses (hex notation, I/O address space)
OF Control register
DC Timer 1
DO Timer 2
Note
Timer counts loaded as two sequential output operations to same
address, as given.
Input Frequencies
Reference
1.075,2 MHz ± 10% (0.930/-(5 period, nominal)
Note
Maximum rate for external events in event counter function.
Mating Connectors *
*Note: Connectors compatible with those listed may also be used.
2-24
AFN-01499A
iSBC 80/20-4
Line Drivers and Terminators
Physical Characteristics
110 Drivers - The following line drivers are all compati·
ble with the I/O driver sockets on the iSBC 80/20·4.
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 em)
Depth - 0.50 in. (1.26 cm)
Weight - 14 oz (397.6 gm)
Driver
Characteristic
Sink CUrront (rnA)
7438
7437
7432
7426
7409
7408
7403
7400
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I
48
48
16
16
16
16
16
16
Electrical Characteristics
DC Power Requirements
Voltage
(:!:5'10)
Noto
I = inverting; Nt = non·inverting; OC = open collector.
Ports 1 and 4 have 20 mA totem·pole bidirectional
drivers arid 1 kG terminators.
I/O Terminators -
1
Wlth4K
PROM 2
(rna.)
With
IS8C530 3
(max)
RAM
Only·
(rna.)
1.1A
Vee= +5V
lee= 4.0A
4.9A
4.9A
Voo= + 12V
loo=90mA
350 mA
450mA
Vee= -5V
VAA =-12V
lee=2 mA
180 mA
180mA
I AA=20mA
20 mA
120 mA
-
Wlth8K
PROMS
(rna.)
5.2A
90mA
2mA
20mA
220G/330G divider or 1 kG pull·up
Notes
1. Does not include power required for optional PROM, 1/0 drivers, and
110 terminators.
2200
2. Wilh four 2708 EPROMs and 2200/3300 input terminators installed for
32 110 lines, all terminator inputs low.
+ S V - - - - " : : . . . . - ._
2200/3300
Without
PROM'
(max)
3. With four 2708 EPROMs, 2200/3300 input terminators installed for 32
110 lines, all terminator inputs low, and iSBC 530 Teletypewriter Adapter
drawing power from serial port connector.
~,...----....- - - 0 isac 90' OPTION
4. RAM chips powered via auxiliary power bus.
5. With four 8716 EPROMs and eight 220W330n input terminators in·
stalled, all terminator inputs low.
Environmental Characteristics
Operating Temperature -
Reference Manual
, kO
, kO +sv - - - - - - " ' M...- - - - - - - - 0 isac 902 OPTiON
98003170 - iSBC 80/20·5 Hardware Reference Manual
(NOT SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Bus Drivers
Driver
Characteristic
Sink Curront (rnA)
Data
Address
Commands
Trl·state
Tri·state
Tri·state
50
50
32
0 'C to 55 'CC
ORDERING INFORMATION
Part Number
Description
SSC 80/20·4
Single Board Computer with 4K bytes
RAM
2-25
AFN·01499A
iSBC™ 80/24 (or pSBC 80/24 *)
SINGLE BOARD COMPUTER·
• Programmable synchronous/asynchronous RS232C compatible serial
interface with software selectable
baud rates
• Full MULTIBUS® control logic for
multi master configurations and
system expansion
• Upward compatible with iSBC 80/20-4
Single Board Computer
• 8085A-2 CPU operating at 4_8 or 2.4 MHz
Ii Two iSBX™ bus connectors for iSBX
MULTIMODULE™ board expansion
'. 4K bytes of static read/write memory
expandable on-board to 8K bytes using
the iSBC 301 MULTIMODULE Board
• Two programmable 16-bit BCDor binary
timers/event counters
.
• 12 levels of programmable interrupt
control
'
• Sockets for up to 32K bytes of read only
memory
• Auxiliary power bus, memory protect,
and power-fail interrupt control logic
provided for battery backup RAM
requirements
• 48 programmable parallel 1/0 lines with
sockets for interchangeable line drivers
and terminators
The Intel® iSBC 80/24 Single Board Computer is a member of Intel's complete line of OEM microcomputer
systems which take full advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for OEM applications. The iSBC 80/24 board is a complete computer system on a
single 6.75 x 12.00-inch printed circuit card. The CPU, system clock, iSBX bus interface, readlwrite
memory, read only memory sockets, 1/0 ports and drivers, serial communications interface, priority interrupt logic, and programmable timers all reside on the board. Full MULTIBUS interface logic is included to
offer compatibility with the Intel OEM Microcomputer Systems family of Single Board Computers, expansion memory options, digital and analog 1/0 expansion boards, and peripheral and communications controllers.
'Same product, manufactured by Intel Puerto Rico, Inc.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Index, Intel, In site, Intellec, Library Manager, Megachassis, Mlcromap,
MULTI BUS, PROMPT, iRMX, UPI, ~Scope, Prom ware, MeS, ICE, iSSC, iSaX, MULTI MODULE and ieS. Intel Corporation assumes no responsibility for the use of any circuitry
other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1980, 1981
2-26
September 1981
142927.01
iSBC™ 80/24
available to provide expansion. equivalent to the
I/O available on the iSBC 80/24 board or the user
may configure entirely new functionality, such as
math, directly on board. The iSBX 350 Parallel I/O
MULTIMODULE board provides 24 I/O lines using
an 8255A Programmable Peripheral Interface.
Therefore, two iSBX 350 modules together with
the iSBC 80/24 board may offer 96 lines of programmable I/O. Alternately,a serial port may be
added using the iSBX 351 Serial I/O MULTIMODULE board and math may be configured on-board
with the iSBX 332 Floating Point Math or iSBX 331
Fixed/Floating Point Math MULTIMODULE board.
Future iSBX products are also planned. The iSBX
MULTIMODULE board is a logical extension of the
on-board programmable I/O and is accessed by
the iSBt 80/24 single board computer ascommon
I/O port locations. The iSBX board is coupled
directly to the 8085A-2CPUand therefore becomes an integral element of the iSBC 80/24
single board computer providing optimum
performance. In addition, 'RAM memory capacity
may be expanded to 8K bytes using the iSBC 301
4K Byte RAM MULTIMODULEboard. Ali MULTIMODULE boards ranging from the iSBC 301
module to the iSBX modules offer incremental
expansion, optimum performarice,' and minimal
cost.
FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's powerful8-bit N-channeI8085A-2 CPU fabricated on a single LSI chip, isthe central processor
for the iSBC 80/24 board operating at either 4.8 or
2.4 MHz (jumper selectable). The 8085A-2 CPU is
directly software compatible with the Intel 8080A
CPU_ The 8085A-2 contains six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs, providing single and double precision operators. Minimum instruction execution
time is 826 nanoseconds. A block diagram of the
iSBC 80/24 functional components is shown in
Figure 1.
MULTIMODULE Board Expansion
The new iSBX bus interface brings an entirely new
dimension to system design offering incremental
on'board expansion at minimal cost. Two iSBX
bus MULTIMODULE connectors are provided for
plug-in expansion of any iSBX MULTIMODULE
board. The iSBX MULTIMODULEconcept provides
the ability to adapt quickly to new technology, the
economy of buying only what is needed, and the
ready availability of a spectrum of functions for
greater application potential. iSBX boards are
..
RS2l2C
PROGRAMMABLE
COMPATIBLE
DEVICE
PARALLEL
tlOLINES
USER
DESIGNATED
PERIPHERALS
USER DESIGNATED
Isex MULTI MODULE
Figure 1_ iSBC 80/24 Single Board Computer Block Diagram
2-27
AFN·01485A
inter
ISBC™80124
.Memo,ry Addressing·
Parallel 1/0 Interface
The 8085A·2. has a 16·bit program counter which
allows direct addressing of up to 64K bytes of
memory. An .external stack, located within any
portion of read/write memory, may be. used as a
last.inlf.irs~·out storage area for the contents of
the programcoul)ter, flags, accumulator,and all
of thesi.x general purpose registers. A 16·bit stack
pOinter controls the addressing of this .. el(ternal
stack. This stack provides subroutine, nesting
bounded only by memory size;
The iSBC 80/24 board contains 48 programmable
parallel I/O lines implemented using two Intel
8255A Programmable Peripheral Interfaces. The
system software is used to configure the I/O lines
in any combination of unidirectional input/output
and bidirectional ports as indicated in Table 1.
Therefore, the I/O interface may be customized to
meet specific peripheral requirements. In order to
take full advantage of the large number of possi·
ble I/O configurations, sockets are, provided for in·
terchangeable I/O line drivers and terminators.
Hence, the flexibility of the I/O interface is further
enhanGed by the capability of selecting the appro·
priate combination of optional line drivers and ter·
minators to prOvide the required sink current,
polarity, and drive/termination characteristics for
each application. The 48 programmable I/O lines
and signal ground lin.es ;ire brOught out to two
50·pin edge connectors that mate with flat, woven,
or round cables. .
.
Memory Capacity
The. ISB080/24 bo~rd contains 4K bytes of static
read/write memory using Intel 8185.2 RAMs. In
addition, .the on·board RAM capacity may be ex·
panded to 8Kbytes with the iSBC 301 ·4K byte
RAM MULTIMODULE board. All RAM read and
write operations are performed at maximum proc·
essor speEld. Power for the on· board RAM may be
'provided on an auxiliary power bus,and melTlory
protept logic is included 'for RAM battery backup
requirements.
Serial 1/0 Interface
A programl)1able communications interface using
F.our s~cketsare prOvided for up to 32K bytes'of
nonvolatile'read only memory on the iSBC 80/24
board. EPROM may be added in 1K byte incre·
ments up to 4K bytes (using Intel 2708 or 2758); in
2K byte increments up to 8K bytes (using Intel
2716); in 4K byte increments up to 16K bytes
(using Intel 2732); or in 8K byte increments up to
32K bytes (using ,Intel 2764).
the IIltel 8251A Universal Synchronous/Asynchro·
nous Receiver/Transmitter (USART) .is. contained
on the iSBC 80/24 board. A software selectable
baud rate generator prOvides the USART with all
common communication frequencies. The USART
can be prOgrammed by the system software to
select the desired asynchronous or synchronous
serial data transmission technique (including IBM
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines
(qty)
Input
• Unlatched
Output
Latched &
Strobed
Latched
Bidirectional
Control
.Latched &
Strobed
8
8
X
·X
2
X
X
3
4
,.X
.
X
4
X
X
4
8
X
X
5
8
4
X
X
X
X
X2
4
X
X
X2
1
6
X·
X
X
X
X
X1
...
. X"
X
X
X
.~.
. ..
X1
X
NOTES:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and
strobed output port or port 1 is used as a bidirectional port.
2; Part ·of port 6 must be used as a control port when either port 4 or port 5 are used as a latched 'and strobed input or a·latched and
strobed output port or port 4 is used asa bidirectional p o r t . '
.
2-28
AFN-01485A
iSBC™ 80/24
Bi-Sync). The mode of operation (i.e. synchronous
or asynchronous), data format, control character
format, parity, and baud rate are all under program
control. The 8251A provides full duplex, double
buffered transmit and receive capability. Parity,
overrun, and framing error detection are all incor·
porated in the USART. The RS232C compatible interface, in conjunction with the USART, provides a
direct interface to RS232C compatible terminals,
cassettes, and asynchronous and synchronous
modems. The RS232C command lines, serial data
lines, and signal ground line are brought out to a
26-pin edge connector that mates with RS232C
.compatible flat or round cable.
terval Timer. Each counter is capable of operating
in either BCD or binary modes. Two of these
timers/counters are available to the systems de·
signer to generate accurate time intervals under
software control. Routing for the outputs and
gate/trigger inputs of two of these counters is
jumper selectable. The outputs may be independ·
ently routed to the 8259A Programmable Interrupt
Controller, to the 1/0 line drivers associated with
the 8255A Programmable Peripheral Interface, or
may be routed as inputs to the 8255A chip. The
gate/trigger inputs may be routed to I/O terminators associated with the 8255A or as output
connections from the 8255A. The third interval
timer in the 8253 provides the programmable baud
rate generator for the RS232C USART serial port.
In utilizing the iSBC 80/24 board, the systems
designer simply configures, via software, each
timer independently to meet system require-
Multimaster Capability
The iSBC 80/24 board is a full computer on a
single board with resources capable of supporting
a large variety of OEM system requirements. For
those applications requiring additional processing capacity and the benefits of multiprocessing
(i.e. several CPUs andlor controllers logically sharing system tasks through communication over the
system bus), the iSBC 80/24 board provides full
MULTIBUS arbitration control logic. This control
logic allows up to three iSBC 80/24 boards or other
bus masters to share the system bus in serial
(daisy chain) priority fashion, and up to 16 masters
to share the MULTIBUS system bus with the addi·
tion of an external priority network. The MULTI·
BUS arbitration logic operates synchronously
with a MULTIBUS clock (provided by the iSBC
80/24 board or optionally connected directly to the
MULTIBUS clock) while data is transferred via a
handshake between the master and slave modu·
les. This allows different speed controllers to
share resources on the same bus since transfers
via the bus proceed asynchronously. Thus, trans·
fer speed is dependent on transmitting and reo
ceiving devices only. This design provides slow
master modules from being handicapped in their
attempts to gain control of the bus, but does not
restrict the speed at which faster modules can
transfer data via the same bus. The most obvious
applications for the master-slave capabilities of
the bus are multiprocessor configurations, high
speed direct memory access (DMA) operations,
and high speed peripheral control, but are by no
means limited to these three.
Table 2_ Programmable Timer Functions
Function
Programmable Timers
The iSBC 80/24 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable In·
2-29
Operation
Interrupt on
terminal
count
When terminal count is reached,
an interrupt request is generated.
This function is extremely useful
for generation of real·time clocks.
Programmable
one·shot
Output goes low upon receipt of
an external trigger edge or software command and returns high
when terminal count is reached;
This function is retriggerable. .;
Rate generator
Divide by N counter. The output
will go low for one input clock 'cy·
cle, and the period from one lowgoing pulse to the next is N times
the input clock period.
Square-wave
rate generator
Output will remain high until onehalf the count has been com·
pleted, and go low for the other
half of the count.
Software
triggered
strobe
Output remains high until software loads count (N). N counts
after count is loaded, output goes
low for one input clock period.
Hardware
triggered
strobe
Output goes low for one clock
period N counts after rising edge
on counter trigger input. The
counter is retriggerable.
Event counter
On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
may read the number of events occurring after the counting "win·
dow" has been enabled or an interrupt may be generated after N
events occur in the system.
AFN-01485A
inter
iSBC™ 80/24
ments. Whenever a given time delay or count'is
needed, software commands to the programmable timers/event counters select the desired
function. Seven functions are available, as shown
in Table 2. The contents of each counter may be
read at any time during system operation with
simple read operations for event counting applications, and special commands are included so that
the 'contents of each counter can be read "on the
fly".
Table 3 Programmable Interrupt Modes
Mode
Operation
Fully nested
Interrupt request line priorities fixed
at 0 as highest, 7 as lowest.
Autorotating
Equal priority. Each level, after re. ceiving service, becomes the lowest
priority level· until next interrupt occurs.
Specific
priority
System software assigns lowest priority level. Priority of all other levels
based in sequence numerically on
this assignment.
Polled
System software examines priorityencoded system interrupt status via
interrupt status register.
Interrupt Capilbility
The iSBC 80/24 board provides vectoring for 12 interruptlevels. Four of these levels are, handled
directly by the interrupt processing capability of
the 8085A-2 CPU and represent the four highest
priority interrupts of the iSBC 80/24 board. Requests are routed to the 8085A-2 interrupt inputsTRAP, RST 7.5, RST 6.5, and RST 5.5 (in decreasing order of priority), each of which generates a
call instruction to a unique address (TRAP: 24H;
RST 7.5: 3CH; RST 6.5: 34H; and RST 5.5: 2CH). An
8085A-2 JMP instruction at each of these addresses then provides linkage to interrupt service
routines located independently anywhere in memory. All interrupt inputs with the exception of the
trap interrupt may be masked via software. The
trap interrupt should be used for conditions such
as power-down sequences which requireimmediate attention by the 8085A-2 CPU. The Intei8259A
Programmable Interrupt Controller (PIC) provides
vectoring for the next eight interrupt levels. As
shown in Table 3, a selection of four priority processing modes is available to the systems designer
for use in designing request processing configurations to match system requirements. Operating
mode and priority assignments may be reconfigured dynamically via software at any time during
system operation. The PIC accepts interrupt re e
quests from the programmable parallel and serial
I/O interfaces, the programmable timers, the system bus, iSBX bus, or directly from peripheral
equipment. The PIC then determines which of the
incoming requests is of the highest priority, determines whether this request is of higher priority
than the level currently'being serviced, and, if appropriate, issues an .interrupt to the CPU. Any
combination of interrupt levels may be masked,
via software, by storing a single byte in the interrupt mask register of the PIC. The PIC generates a
unique memory address for each interrupt level.
These addresses are equally spaced at intervals of
4 or 8 (software selectable) bytes. This 32 or
64-byte block may be located to begin at any 32 or
64-byte boundary in the 65,536-byte memory
space. A single 8085A-2 JMP instruction at each
of these addresses then provides linkage to locate
each interrupt service routine independently anywhere in memory.
Interrupt Request Generation
Interrupt requests may originate from 23 sources.
Two jumper selectable interrupt requests can be
generated by each iSBX MULTIMODULE board.
Two jumper selectable interrupt requests can be
automatically generated by eiJ,ch programmable
peripheral interface when a byte of information .is
ready to be transferred to the CPU (i.e., input buffer is full) or a byte of information has been transferred to a peripheral device (i.e., output buffer is
empty). Three jumper selectable interrupt reo
quests can be automatically generated by. the
USART when a character is ready to be transferred
to the CPU (Le., receiver channel buffer is full), a
character is ready to be transmitted (i.e., the
USART is ready ·to accept a character. from the
CPU), or when the ,transmitter is empty (i.e., the
USART has no character to transmit). A jumper
selectable request can be generated by each of
the programmable timers. Nine interrupt request
lines are available to the user for direct interface
to user designated peripheral devices via the
MULTIBUS system bus. A power-fail signal can
also be selected as an interrupt source.
Power· Fail Control
A power-fail .interrupt may be detected through
the AC-Iow signal generated by the power supply.
This signal may be configured to interrupt the
8085A-2 CPU to initiate an orderly power dow(l in.
struction sequence.
MULTIBUS System Expansion
Capabilities
Memory and I/O capacity may be expanded and
additional functions added using Intel MULTIBUS
system compatible expansion boards. Memory
may be expanded to 65,536 bytes by adding user
specified combinations· of RAM boards, EPROM
boards, or combination boards. Input/output capa2-30
AFN·01485A
iSBC™ 80/24
city may be increased by adding digital I/O and
analog I/O expansion boards. Mass storage capability may be achieved by adding single or double
density diskette or hard disk controllers as subsystems. Expanded communication needs can be
handled by communication controllers. Modular
expandable backplanes and card cages are available to support multi board systems.
Intellec microcomputer development system option. PUM provides the capability to program in a
natural, algorithmic language and eliminates the
need to manage register usage or allocate memory. PUM programs can be written in a much
shorter time than assembly language programs.
FORTRAN-aO-For applications requiring computational and formatted I/O capabilities, the ANSI
77 standard high level FORTRAN-BO programming
language is available as a resident option of the
Intellec system. The FORTRAN compiler produces relocatable object code that may be easily
linked with PUM or assembly language program
modules. In addition, the iSBC B01 FORTRAN-BO
Run-Time Package is a complete, ready-to-use set
of linkable object modules which are fully
compatible with iRMX BO systems. The modules,
when combined with the FORTRAN-BO coded application,provide the appropriate interfaces to the
disk file and terminal I/O of iRMX BO, and to the
iSBC 310A Math Unit for applications requiring
high speed math.
Real-Time Software
The iRMX™ 80 executive, which contains all major
real-time facilities including priority-based system
resource allocation, intertask communication and
control, interrupt driven control for standard I/O
devices, and interrupt handling, occupies 2K
bytes of memory which can be stored on-board in
EPROM. Optional linkable and relocatable modules for console control (CRT or TTY), disk file system, and analog subsystems are provided with the
iRMX 80 package. These facilities eliminate the
need for users to design and implement application specific executives, greatly simplifying application design and reducing development time and
risk.
BASlc-aO-A high level language interpreter is
available with extended disk capabilities which
operates under the iRMX BO Real-Time Multitasking Executive and translates BASIC-BO source programs into an internally executable form. This
language interpreter, provided as a set of linkable
object modules, is ideally suited to the OEM who
requires.a pass through programming language.
The BASIC-BO programs may be created, stored,
and interpreted on the iSBC BO-based systems
using the iSBC B02 BASIC-BO Configurable iRMX
BO Disk-Based Interpreter. The iSBC B02 Interpreter has a complete ready-to-use set of linkable
object modules which are fully compatible with Intel's iRMX BO Real-Time Multitasking Executive
Software. The modules provide interfaces to disk
file and terminal I/O, software floating point, or interface to other routines provided by the user.
System Development Capability
The development CyClE3 of iSBC 80/24-based products may be significantly reduced using Intel's
system development tools available today. The Intellec Series II family of compatible microcomputer development systems provides a range of
capability from a low cost disk-based edit debug
workstation to a high performance, fully compatible hard-disk-based software development system. Also, a unique in-circuit emulator (ICE-85A)
option provides the capability of developing and
debugging software directly on the iSBC BO/24
board.
Programming Capability
PUM-aO-lntel's high level system programming
language, PUM, is also available as a resident
Memory Addressing
SPECI FICATIONS
Cycle Time
On-Board EPROM
O-OFFF using 270B, 275B (1 wait state)
0-1FFF using 2716 (1 wait state)
0-3FFF using 2732 (1 wait state)
using 2732A (no wait states)
0-7FFF using 2764A (no wait states)
Basic Instruction Cycle
B26 nsec (4.B4 MHz operating frequency)
1.65 ,..sec (2.42 MHz operating frequency)
On-Board RAM
3000-3FFF with no RAM expansion
2000-3FFF with optional RAM (iSBC 301 board)
NOTE:
Basic instruction cycle is defined as the fastest instruction
(Le., four clock cycles).
NOTE:
Default configuration-may be reconfigured to top end of any
16K boundary.
Word Size
Instruction-B, 16, or 24 bits
Data-B bits
2-31
AFN-01485A
inter
iSBC™ 80124
Memory Capacity
Serial Communications Characteristics
On-Board EPROM
32K bytes (sockets only)
May be added in 1 K (using Intel 2708 or 2758), 2K
(using Intel 2716), 4K (using Intel 2732), or 8K
(using Intel 2764) byte increments.
Synchronous-5-8 bit characters; internal or external character synchronization; automatic sync
insertion
Asynchronous-5-8 bit characters; break'character generation; 1, 11/2, or2 stopbits; false start bit
detectors
On-Board RAM
4K bytes (8K bytes using iSBC 301 4K byte RAM
MULTIMOOULE Board)
Baud Rates
.Output
Frequency
in kHz
Off-Board Expansion
Up t064K bytes using user specified combinations of RAM, ROM, and EPROM.
Up to 128K bytes using bank select controlvia 1/0
port and 2 jumper options.
Baud Rate (Hz)
Synchronous
+16 +64
9600 2400
4800 1200
2400
600
1200
300
600
150
300
75
150
-'110
-
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
May be disabled using PROM ENABLE via 1/0 port
and jumper option, resulting in off-board RAM
overlay capability_
Asynchronous
38400
19200
9600
4800
2400
1760
NOTE:
Frequency selected by I/O write of appropriate 16·bit frequency
factor to baud rate register.
110 Addressing
Device
I/O Address
8255A No.1
Port A
Port B
Port C
Control
DE
Baud rate register
NOTE:
8255A No.2
Port A
Port B
Port C
Control
8251A
Data
Control
iSBX MULTIMODULE
MCSO
MCS1
1/0 address
Register Address (hex notation,
space)
On-Board Programmable 1/0
I
E4
E5
E6
E7
Baud rate factor (16 bits) is loaded as two sequential output operations to same address (DE H)·
E8
E9
EA
EB
Addresses for 8259A Registe.rs (hex notation, 1/0
address space)
Interrupts
OA
OA
DB
OA
DB
OA
EC, EE
ED, EF
JO
CO-C7
C8-CF
iSBX MULTI MODULE J6
MCSO
MCS1
08
08
09
08
09
08
Interrupt request register
In-service register
Mask register
Command register
Block address register
Status (polling register)
NOTE:
Several registers have the same physical address; sequence of
access and one data bit of control word determine which register will respond.
FO-F7
F8-FF
Interrupt levels routed to 8Q85A-2 CPU automatically vector the processor to unique memory locations:
1/0 Capacity
Parallel-48 programmable lines
Serial-1 transmit, 1 receive, 1 SID, 1 SOD
iSBX MULTIMODULE Boards
or
or
or
or
or
or
2 iSBX MULTIMOOULE
2-32
Interrupt
Input
Memory
Address
TRAP
RST 7.5
RST 6.5
RST 5.5
24
3C
34
2C
Priority
Type
Highest
Non-maskable
Maskable
Maskable
Maskable
+
Lowest
AFN-0148SA
inter
iSBC™ 80/24
backup of read/write memory. Selection of this
auxiliary RAM power bus is made via jumpers on
the board.
Timers
Register Addresses (hex notation, I/O address
space)
OF Control register
DC Timer 0
DO Timer 1
DE Timer 2
Connectors
Interlace
NOTE:
Double·
SldadPln.
(qty)
Conters
(In.)
Mating Connectors·
Timer counts loaded as two sequential output operations to
same address as given.
MULTIBUS
System
Bus
86
0.156
Input Frequencies
Reference: 1.0752 MHz ± 0.1 % (0.930 !,-sec period,nominal)
Event Rate: 1.1 M Hz max.
ELFAB BS1562043PBB
Viking 2KH4319AMK12
Soldered PCB Mount
EDAC 337086540201
ELFAB BW1562D43PBB
EDAC 337086540202
ELFAB BW1562A43PBB
Wire Wrap
Auxiliary
Bus
60
0.100
EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB
Wire Wrap
ISBX Bus
(2)
36
0.100
ISBX 960·5
Parallel 110
(2 )
50
0.100
3M 3415-001 FtatCrlmp
GTE Sylvania
6AD01251A1DD
Soldered
Serial 110
26
0.100
AMP 15837151
EDAC 345026520202
PCB Soldered
3M 3462-0001
AMP 88373·5 Flat Crimp
Output Frequencies/Timing Intervals
Function
Single Timer/Counter
Dual Timer/Counter
(Two Timers Cascaded)
Min.
Max.
Min.
Max.
Real·Time
Interrupt
1,86 psec
60.948 msec
3.72 "sec
1.109 hrs
Programmable
One·Shot
1.86 "sec
60.948 msec
3.72 "sec
1.109 hrs
Rate
Generator
16.407 Hz
537.61 kHz
0.00025 Hz
268.81 kHz
Square-Wave
Rate
Generator
16.407 Hz
537.61 kHz
0.00025 Hz
268.81 kHz
Software
Triggered
Strobe
1.86 "sec
60.948 msec
3.72 "sec
1.109 hrs
Hardware
Triggered
Strobe
1.86 psec
°Note: Connectors compatible with those listed may also be used.
Memory Protect
Input frequency to timers is 1.0752 MHz (default configuration).
An active-low TTL compatible memory protect signal is brought out on the auxiliary connector
which, when asserted, disables read/write access
to RAM memory on the board. This input is provided for the protection of RAM contents during
system power-down sequences.
Interfaces
line Drivers and Terminators
MULTIBUS-AII signals TTL compatible
I/O Drivers-The following line drivers and terminators are all compatible with the I/O driver sockets on the iSBC BO/24 Board:
60.948 msec
3.72 "sec
1.109 hrs
NOTE:
iSBX Bus-All signals TTL compatible
Parallel I/O-All signals TTL compatible
Seriall/0-RS232C compatible, configurable as a
data set or data terminal
Timer-All signals TTL compatible
Interrupt Requests-All TTL compatible
System Clock (8085A·2 CPU)
Driver
Characteristic
Sink Current (mA)
7438
7437
7432
7426
7409
7408
7403
7400
I,oe
I
NI
I,oe
NI,Oe
NI
I,oe
I
48
48
16
16
16
16
16
16
NOTE:
4.B4 or 2.42 MHz ±0.1% (jumper selectable)
I = inverting; NI = non-inverting; OC = open collector.
Auxiliary Power
Ports E4 and EB have 32 mA totem-pole drivers
and 1K terminators.
An auxiliary power bus is provided to allow separate power to RAM for systems requiring battery
110 Terminators-220!1l330{2 divider or 1 k{2 pullup
2-33
AFN·01485A
iSBCM 80124
220W330!! (iSBC 901 OPTION)
22011
+5V--~----------~AN~~----------~-,
330\l
1'--------~~------~~
3. Does not include power for optional EPROM, I/O drivers,
and 110 terminators. Power for iSBC 530 Adapter is supplied
via 'serial p·ort connector.
4. Includes power required for four EPROM chips, and 110 ter·
minators installed for 16 110 lines; all termin.atorinputs low.
Environmental Characteristics
Operating Temperature-O°C to 55'C
Reference Manual
1 kil (iSBX 902 OPTION)
1 k!l
+5V--~~-----,--~~---------------:--,----
Bus Drivers
Function
Characteristic
Sink Current (mA)
Data
Address
Commands
Tri·State
Tri·State
Tri·State
32
32
32
142648-001--iSBC 80/24 Single Board Computer
Hardware Reference Manual (NOT SUPPLIED)
Manuals may be ordered from any. Intel sales representative, distributoroffice orIrom Intel literature Department, 3065 Bowers Alienue,Santa
Clara, California 95051.
Physical Characteristics
Width-12.00 in. (30.48 cm)
Height-:-6.75 in. (17.15 .cm)
Depth-0.50 in. (1.27 cm)
Weight-12.64 oz. (354 gm)
Electrical Characteristics
DC Power Requirements
Current
Configuration
Requirement~
V cc =+5V
:!:5% (max)
Voo=+12V
±S%(max)
Without
EPROM'
3.34A
40 mA
RAM Only2
0.14A
-
-
-
With
iSBC 530 3
3.34A
140 mA
-
120 mA
With 4K
EPROM 4
(using 2708)
3.74A
300 mA
180 mA
20 mA
With 4K
EPROM 4
(using 2758)
4.43A
40 mA
-
With 8K
EPROM 4
(using 2716)
4.43A
. 40 inA
-
20 mA
With 16K
EPROM 4
(using 2732)
4.71A
40 mA
-
20 mA
With 32K
EPROM 4
(using 2764)
4.71A
40 mA
-
20mA
Vee= -5V VAA=-12V
±5%(max)
±S%(max)
-
20 mA
.
20 mA
NOTES:
1. Does not include power for optional EPROM, 110 drivers,
.
and 110 terminators.
2. RAM chips powered via auxiliary power bus.
ORDERING INFORMATION
Part Number
Description·
SBC 80/24
Single Board. Computer
2-34
AFN·01485A
iSBC™ 80/30 (or pSBC 80/30*)
SINGLE BOARD COMPUTER
• 8085A CPU used as central processing
unit
• 16K bytes of dual port dynamic read/
write memory with on-board refresh
• Sockets for up to 8K bytes of read only
memory
• Sockets for 8041A18741 A Universal
Peripheral Interface and interchangeable line drivers and line terminators
• 24 programmable parallel 11/0 lines with
sockets for interchangeable line drivers
and terminators
• Programmable synchronous/asynchronous RS232C compatible serial
interface with fully software selectable
baud rate generation
• Full MULTIBUS® control logic allowing
up to 16 masters to share the system
• 12 levels of programmable interrupt
control
• Two programmable 16-bit BCD or binary
.
counters ..
• Auxiliary power bus, memory protect,
and power-fail interrupt control logic
for RAM battery backup
• Compatible with optional iSBC 80 CPU,
memory, and I/O expansion boards
The iSBC 80/30 Single Board Computer is a member of Intel's complete line of OEM computer systems which take full
advantage of Intel's LSI technology to provide economical self-contained computer-based solutions for OEM applications. The iSBC 80/30 is a complete computer system on a single 6.75 x 12.00-inch printed circuit card. The CPU,
system clock, readlwrite memory,nonvolatile read only memory, universal peripheral interface capability, 1/0 ports and
drivers, serial communications interface, priority interrupt logic, programmable timers, MULTIBUS control logic, and
bus expansion drivers all reside on the board.
'Same product, manufactured by Intel Puerto Rico, Inc.
AFN-00263A
iSBC 80/30
FUNCTIONAL DESCRIPTION
Bus Structure
The iSSC 80/30 has an internal bus for all on-board memory and 110 operations and a system bus (i.e., the
MULTISUS) for all external memory and I/O operations.
Hence, local (on-board) operations do not tie up the system bus, and allow true parallel processing when several bus masters (i.e., DMA devices, other single board
computers) are used in a multimaster scheme. A block
diagram of the iSSC 80/30 functional components is
shown in Figure 1.
Central Processing Unit
Intel's powerful 8-bit n-channel 8085A CPU, fabricated
on a single LSI chip, is the central processor for the
iSSC 80/30. The 8085A CPU is directly software compatible with the Intel 8080A CPU. The 8085A contains six
8-bit general purpose registers and an accumulator. The
six general purpose registers may be addressed individually or in pairs, providing both single and double precision operators. The minimum instruction execution
time is 1.45 microseconds. The 8085A CPU has a 16-bit
program counter. An external stack, located within any
portion of iSSC 80/30 read/write memory, may be used
as a last-Inlfirst-out storage area for the contents of the
program counter, flags, accumulator, and all of the six
general purpose registers. A 16-bit stack pointer controls the addressing of this external stack. This stack
provides subroutine nesting bounded only by memory
size.
RAM Capacity
The ISSC 80/30 contains 16K bytes of dynamic
read/write memory using Intel 2117 RAMs. All RAM read
and write operations are performed at maximum processor speed. Power for the on-board RAM may be provided on an auxiliary power bus, and memory protect
logic is included for RAM battery backup requirements.
The iSSC 80/30 contains a dual port controller, which
provides dual port capability for the on-board RAM memory. RAM accesses may occur from either the iSSC
80/30 or from any other bus master interfaced via the
US,ER DESIGNATED
SERIAL
RS232C
DATA
INTERFACE
COMPATIBLE
DEVICE
PERIPHERALS
42 PROGRAMMABLE
PARALLEL 110 LINES
POWER FAIL
INTERRUPT
4 INTERRUPT
REQUEST LINES
2 INTERRUPT
REQUEST LINES
8 INTERRUPT
REQUEST
LINES
TWO
PROGRAM·
MABLE
TIMERS
MUlTIBUS
Figure 1_ iSBC 80/30 Single Board Computer Block Diagram
2-36
AFN·OO263A
iSBC 80/30
MULTIBUS. Since on-board RAM accesses do not
require the MULTI BUS, the bus is available for any other
concurrent operations (e.g., DMA data transfers) requiring the use of the MULTIBUS. Dynamic RAM refresh is
accomplished automatically by the iSBC 80/30 for
accesses originating from either the CPU or via the
MULTIBUS. Memory space assignment can be selected
independently for on-board and MULTIBUS RAM
accesses. The on-board RAM, as seen by the 8085A
CPU, may be placed anywhere within the 0- to
64K-address space. The iSBC 80/30 provides extended
addressing jumpers to allow the on-board RAM to reside
within a one megabyte address space when accessed
via the MUL TlBUS. In addition, jumper options are provided which allow the user to reserve 8K- and 16K-byte
segments of on-board RAM for use by the 8085A CPU
only. This reserved RAM space is not accessible via the
MULTIBUS and does not occupy any system address
space.
ity of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional
line drivers and terminators to provide the required sink
current, polarity, and drive/termination characteristics
for each application. The 24 programmable I/O lines and
signal ground lines are brought out to a 50-pin edge connector that mates with flat, woven, or round cable.
Universal Peripheral Interface (UPI)
The iSBC 80/30 provides sockets for a user supplied Intel 8041A/8741 A Universal Peripheral Interface (UPI) chip
and the associated line drivers and terminators for the
UPI's I/O ports. nle 8041A18741A is a single chip
microcomputer containing a CPU, 1K bytes of ROM
(8041A) or EPROM (8741A), 64 bytes of RAM, 18 programmable I/O lines, and an 8-bit timer. Special interface
registers included in the chip allow the 8041A to function as a slave processor to the iSBC 80/30's 8085A CPU.
The UPI allows the user to specify algorithms for controlling user peripherals directly in the chip, thereby
relieving the 8085A for other system functions. The
iSBC 80/30 provides an RS232C driver and an RS232C
receiver for optional connection to the 8041A/8741A in
applications where the UPI is programmed to handle
simple serial 'interfaces. For additional information, including 8041A18741A instructions, refer to the UPI-41A
User's Manual and application note AP-41.
EPROM/ROM Capacity
Sockets for up to 8K bytes of nonvolatile read only
memory are provided on the iSBC 80/30 board. Read only
memory may be added in 1K-byte increments up to a
maximum of 2K bytes using Intel 2708 or 2758 erasable
and electrically reprogrammable ROMs (EPROMs); in
2K-byte increments up to a maximum of 4K bytes using
Intel 2716 EPROMs; or in 4K-byte increments up to 8K
bytes maximum using Intel 2732 EPROMs. All on·board
EPROM/ROM operations are performed at maximum
processor speed.
Serial 110
A programmable communications interface using the
Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on the iSBC
80/30. A software selectable baud rate generator provides the USART with all common communication frequencies. The USART can be programmed by the system software to select the desired asynchronous or
synchronous serial data transmission technique (including IBM By-Sync). The mode of operation (I.e., synchronous or asynchronous), data format, control
character format, parity, and baud rate are all under program control. The 8251A provides full duplex, double
buffered transmit and receive capability. Parity, overrun,
and framing error detection are all incorporated in the
Parallel 110 Interface
The iSBC 80/30 contains 24 programmable parallel I/O
lines implemented using the Intel 8255A Programmable
Peripheral Interface. The system software is used to
configure the I/O lines in any combination of unidirec·
tional input/output and bidirectional ports indicated in
Table 1. Therefore, the 110 interface may be customized
to meet specific peripheral requirements. In order to
take full advantage of the large number of possible I/O
configurations, sockets are provided for interchangeable I/O line drivers and terminatorS. Hence, the flexibil-
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines
(qty)
Input
Output
Bidirectional
Unlatched
Latched &
Strobed
Latched
Latched &
Strobed
Control
1
8
X
X
X
X
2
8
X
X
X
X
4
X
X
X1
4
X
X
X1
3
X
Nole
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched'and strobed input or a latched and strobed output port
or port 1 is used as a bidirectional port.
2-37
AFN-00263A
iSBC 80/30
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a direct
interface to RS232C compatible terminals, cassettes,
and asynchronous and synchronous modems. The
RS232C command lines, serial data lines, and signal
ground line are brought out to a 26'pin edge connector
that mates with RS232C compatible flat or round cable.
Whenever a given time delay or count is needed, software commands to the programmable timers/event
counters select the desired function. Seven functions
are available, as shown in Table 2. The contents of each
counter may be read at any time during system opera·
tion with Simple read operations for event counting applications, and special commands are included so that
the contents. of each counter can be read "on the fly".
Multimaster Capability
Table 2. Programmable Timer Functions
The iSBC 80/30 is a full computer on a single board with
resources capable of supporting a great variety of OEM
system requirements. For those applications requiring
additional processing capacity and the benefits of
multiprocessing (i.e., several CPUs and/or controllers
logically sharing system tasks through communication
over the system bus), the iSBC 80/30 provides full
MULTIBUS arbitration control logic. This control logic
allows up to three iSBC 80/30's or other bus masters to
share the system bus in serial (daisy chain) priority fashion, and up to 16 masters to share the MULTIBUS with
the addition of an external priority network. The MULTI·
BUS arbitration logic operatessynchronbusly with a
MULTI BUS clock (provided by the iSBC 80/30 or option·
ally connected directly to the MULTIBUSclock) while
data is transferred via a handshake between the master
and slave modules. This allows different speed controllers to share resources on the same bus, and trans·
fers via the bus proceed asynchronously. Thus, transfer
speed is dependent on transmitting and receiving
devices only. This design prevents slow master modules
from being handicapped in their attempts to gain control of the bus, but does not restrict the speed at which
faster modules can transfer data via the same bus. The
most obvious applications for the master·slave capabilities of the bus are multiprocessor configurations, high
speed direct memory access (DMA) operations, and high
speed peripheral control, but are by no means limited to
these three.
Programmable Timers
The iSBC 80/30 provides three independent, fully pro·
grammable 16-bit interval timers/event counters utilizing the Intel 8253 Programmable Interval Timer. Each
counter is capable of operating in either BCD or binary
modes. Two of these timers/counters are available to
the systems designer to generate accurate time intervals under software control. Routing for the outputs and
gateltrigger inputs of two of these counters is jumper
selectable. The outputs may be independently routed to
the 8259A Programmable Interrupt Controller, to the I/O
line drivers associated with the 8255A Programmable
peripheral Interface, and to the 8041A/8741A Universal
Programmable Interface, or may be routed as inputs to
the 8255A and 8041A/8741A chips. The gateitrigger inputs may be routed to I/O terminators associated with
the 8255A or as output connections from the 8255A. The
third interval timer in the 8253 provides the programmabie baud rate generator for the iSBC 80/30 RS232C
USART serial port. In utilizing the iSBC 80/30, the
systems deSigner simply configures, via software, each
timer independently to meet system requirements.
Function
Operation
Interrupt on
terminal count
When terminal count is reached, an
interrupt request is generated. This
function is extremely useful for gen·
eration of real·time clocks.
Programmable
one·shot
Output goes low upon receipt of an
external trigger edge or software
command and returns high when ter·
minal count is reached. This func·
tion is retriggerable.
Rate
generator
Divide by N counter. The output will
go low for one input clock cycle, and
the period from one low'going pulse
to the next is N times the input clock
period.
Square·wave
rate generator
Output will remain high Until one·
half the count has been completed,
and go low for the other half of the
count.
Software
triggered
strobe
Output remains high until software
loads count (N). N counts after count
is loaded, output goes low for one in·
put clock. period.
Hardware
triggered
strobe
Output goes low for one clock
period N counts after rising edge on
counter trigger input. The counter is
retriggerable.
Event counter
On a jumper selectable. basis, the
clock input becomes an input from
the external system. CPU may read
the number of events occurring after
the counting "window" has been
enabled or an interrupt may be gen·
erated after N events occur in the
system.
Interrupt Capability
The iSBC 80/30 provides vectoring for 12 interrupt
levels. Four of these levels are handled directly by the
interrupt processing capability of the 8085A CPU and
represent the four highest priority interrupts of the iSBC
80/30. Requests are routed to the 8085A interrupt inputs,
TRAP, RST 7.5, RST 6.5, and RST 5.5 (in decreasing order
of priority) and each input generates a unique memory
address (TRAP: 24H; RST 7.5: 3CH; RST 6.5: 34H; and
RST 5.5: 2CH). An 8085A jump instruction at eac!) of
these addresses then provides linkage to interrupt ser-
2-38
AFN·00263A
iSBC 80/30
vice routines located independently anywhere in memo
ory. All interrupt inputs with the exception of the trap
interrupt may be masked via software. The trap interrupt
should be used for conditions such as power·down
sequences which require immediate attention by the
8085A CPU. The Intel 8259A Programmable Interrupt
Controller (PIC) provides vectoring for the next eight
interrupt levels. As shown in Table 3, a selection of four
priority processing modes is available to the systems
designer for use in designing request processing con·
figurations to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PIC accepts interrupt requests from the
programmable parallel and serial I/O interfaces, the pro·
grammable timers, the system bus, or directly from
peripheral equipment. The PIC then determines which
of the incoming requests is of the highest priority, deter·
mines whether this request is of higher priority than the
level currently being serviced, and, if appropriate, issues
an interrupt to the CPU. Any combination of interrupt
levels may be masked, via software, by storing a single
byte in the interrupt mask register of the PIC. The PIC
generates a unique memory address for each interrupt
level. These addresses are equally spaced at intervals of
4 or 8 (software selectable) bytes. This 32· or 64·byte
block may be located to begin at any 32· or 64·byte
boundary in the 65,536·byte memory space. A single
8085A jump instruction at each of these addresses then
provides linkage to locate each interrupt service routine
independently anywhere in memory.
eral interface, eight additional interrupt reqClest lines
are available to the user for direct interface to user
designated peripheral devices via the system bus, and
two interrupt request lines may be jumper routed
directly from peripherals via the parallel I/O driver/termi·
nator section.
Power·Fail Control
Control logic is also included to accept a power· fail
interrupt in conjunction with the AC·low signal from the
iSBC 635 Power Supply or equivalent.
Expansion Capabilities
Memory and I/O capacity may be expanded and addi·
tional functions added by using Intel MULTIBUS com·
patible expansion boards. High speed integer and
floating point arithmetic capabilities may be added by
using the iSBC 310A High Speed Mathematics Unit.
Memory may be expanded to 65,536 bytes by adding user
specified combinations of RAM boards, EPROM boards,
or combination boards. Inputloutput capacity may be in·
creased by adding digital I/O and analog I/O expansion
boards. Mass storage capability may be achieved by add·
ing single or double density diskette controllers as sub·
systems. Modular expandable backplanes and card·
cages are available to support multi·board systems.
Real· Time Software
Intel's iRMX 80 Real·Time Multi·Tasking 'Executive' soft·
ware, specifically designed for Intel iSBC 80 single
board computers, provides the capability to monitor and
control multiple asynchronous external events. The
iRMX 80 executive, which synchronizes and controls the
execution of multiple tasks, is provided as a linkable and
relocatable module requiring only 2K bytes of memory
space. Optional linkable and relocatable modules for
teletypewriter and CRT control, diskette file system,
high speed math unit, and analog subsystems are also
available.
Table 3. Programmable Interrupt Modes
Mode
Operation
Fully
nested
Interrupt request line priorities fixed at 0
as highest, 7 as lowest.
Auto·
rotating
Equal priority. Each level, after receiving
service, becomes the lowest priority level
until next interrupt occurs.
Specific
priority
System software assigns lowest priority
level. Priority of all other levels based in
sequence numerically on this assignment.
Polled
System software examines priority·
encoded system interrupt status via inter·
rupt status register.
System Development Capability
The development cycle of iSBC 80/30·based products
may be significantly reduced using the Interrec series
microcomputer development systems. The resident
macroassembler, text editor, and system monitor
greatly simplify the deSign, development, and debug of
iSBC 80/30 system software. An optional diskette oper·
ating system provides a relocating macroassembler,
relocating loader and linkage editor, and a library man·
ager. A unique in·circuit emulator (ICE·85) option pro·
vides the capability of developing and debugging soft·
ware directly on the iSBC 80/30.
Interrupt Request Generation - Interrupt requests may
originate from 18 sources. Two jumper selectable inter·
rupt requests can be automatically generated by the
programmable peripheral interface when a byte of infor·
mation is ready to be transferred to the CPU (I.e., input
buffer is full) or a byte of information has been trans·
ferred to a peripheral device (I.e., output buffer is
empty). Two jumper selectable interrupt requests can be
automatically generated by the USART when a character
is ready to be transferred to the CPU (I.e., receive chan·
nel buffer is full), or a character is ready to be trans·
mitted (I.e., transmit channel data buffer is empty). A
jumper selectable request can be generated by each of
the programmable timers and by the universal peri ph·
Programming Capability
Intel's high level programming language,
PUM, is also available as a resident Intellec microcom·
puter development system option. PUM provides the
capability to program in a natural, algorithmic language
and eliminates the need to manage register usage or
allocate memory. PUM programs can be written in a
much shorter time than assembly language programs
for a given application.
PLfM·80 -
2-39
AFN-00263A
iSBC 80/30·
FORTRAN'80 -For applications requiring computational and formatted 1/0 capabilities, the high level
FORTRAN-80 programming language is also available
as a resident option of the intellec system. FORTRAN-80 meets and exceeds the ANS FORTRAN 77
subset language specification. The FORTRAN-80 compiler produces relocatable object code that. may be
easily linked with other FORTRAN,80, PUM, or assembly language program modules. This gives the user wide
flexibility in developing software by using the best software tool for a particular functional.module within the
user's application.
BASIC·80 - A high level language interpreter with extended disk capabilities which operates under the iRMX
80 Real-Time Multi-tasking Executive and translates
BASIC-80 source programs into an internally executable
form. This language interpreter, provided as a set of
linkable object modules, is ideally suited to the OEM
who requires a pass thru programming language. The
BASIC-80 programs may be created, stored and interpreted on the iSBC 80-based system. The BASIC-80
language has a rich complement of statements, functions, and commands to program applications requiring
a full range of 1) string manipulation and disk 1/0 for data
processing, 2) single and double precision floating pOint
and array handling for numeric analysis, or 3) port 1/0
with mask operations controlled through bit-wise
Boolean logical operators.
SPECIFICATIONS
Serial Communications Characteristics
Synchronous - 5-8 bit characters; internal or external
character synchronization; automatic sync insertion.
Asynchronous - 5-8 bit characters; break character
generation; 1, 1V2, or 2 stop bits; false start bit detection.
Word Size
Instruction - 8,16, or 24 bits
Data - 8 bits
Cycle Time
Baud Rates
Basic Instruction Cycle -
1.45 "'s
Frequency (kHz)
(Software Selectable)
Note
Basic i~struct;on cycle is defined as the fastest instruction (i.e., four
clock cycles).
Baud Rate (Hz)
Synchronous
-
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
Memory Addressing
On-Board ROM/EPROM - 0-07FF(using 2708 or 2758
EPROMs); O-OFFF (using 2716 EPROMs); 0-1FFF (using
2716 EPROMs; 0-1 FFF (using 2732 EPROMs).
On-Board RAM - 16K bytes of dual port RAM starting
on a 16K boundary. One or two 8K-byte segments may
be reserved for CPU use only.
38400
19200
9600
4800
2400
1760
Asynchronous
-;- 16
-;- 64
9600
4800
2400
1200
600
300
150
110
2400
1200
600
300
150
75
-
Note
Frequency selected by 1/0 write of appropriate 16·bit frequency factor to
baud rate register (8253 Timer 2).
Memory Capacity
Interrupts
On-Board Read Only Memory - 8K bytes (sockets only)
On-Board RAM - 16K bytes
OIl·Board Expansion - Up to 65,536 bytes in user
specified combinations of RAM, ROM, and EPROM
Addresses for 8259A Registers (Hex notation, 1/0 address space)
Note
Read only memory, may be added in 1K, 2K, or 4K-byte increments.
DA
DB
Mask register
1/0 Addressing
DA
Command register
On-Board Programmable 1/0 (see Table 1)
I
Port
I
8255A
I
I 1 I 2 I 3 IControl I
8041A18741A
Data
I
I Control I
USART
I
Data Control
DAlnterrupt request register
In-service register
DB
Block address register
DA
Status (polling register)
Note
Several registers have the same physical address; sequence of access
and one data bit of control word determine which register will respond.
1/0 Capacity
Parallel - 42 programmable lines using one 8255A (24
1/0 lines) and an optional 8041A/8741A (18110 lines)
Serial - 2 programmable lines using one 8251A and an
optional 8041 A/8741 A programmed for serial operation
Note:
For additional information on the B041A/8741A refer to the UPI-41 User's
Manual (Publication 9800504).
2-40
Interrupt Levels' routed to 8085A CPU automatically vec'
tor the processor to unique memory locations:
Interrupt
Input
Memory
Address
TRAP
RST 7.5
RST 6.5
RST 5.5
24
3C
34
2C
Priority
Type
Highest
Non-maskilble
Maskable
Maskable
Maskable
~
Lowest
AFN·00263A
iSBC 80/30
Timers
Connectors
Register Addresses (Hex notation, I/O address space)
DF
Control register
DC
DD
Timer 0
Timer 1
DE
Timer 2
Interlace
Pin.
(qty)
Centers
(In.)
Mating Connector.
Bus
66
0.156
Viking 2KH4319AMK12
Parallel 110
50
0.1
3M 3415'()OO
Serial 1/0
26
0.1
3M 3462'()00
Note
Timer counts loaded as two sequential output operations to same
address, as given.
Memory Protect
An active-low TIL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on
the board. This input is provided for the protection of
RAM contents during system power-down sequences.
Input Frequencies
Reference: 2.46 MHz ± 0.1 % (0.041 IJs period, nominal);
1.23 MHz± 0.1 %(0.81 IJs period, nominal); or 153.60 kHz
±0.1%(6.51 IJs period nominal).
Note
Above frequencies are user selectable
Event Rate: 2.46 MHz max
Line Drivers and Terminators
Note
Maximum rate for external events In event counter function.
I/O Drivers- The following line drivers are all compatl'
ble with the I/O driver sockets on the iSSC 80/30.
Output FrequencieslTiming Intervals
Single TlmerlCounter
Function
Min
Ma.
Driver
Dual Timer/Counter
(Two Timers Cascaded)
Min
7436
7437
7432
7426
7409
7406
7403
7400
Ma.
Real·tlme
interrupt
1.63
~s
427.1 ms
3.26
~s
466.50 min
Programmable
1.63
~s
427.1 ms
3.26 ~s
466.50 min
I
one-shot.
Rate generator
2.342 Hz
613.5 kHz
0.000036 Hz
306.6 kHz
Square-wave
rate generator
2.342 Hz
613.5 kHz
0.000036 Hz
306.6 kHz
Software
triggered
strobe
1.63
~s
427.1 ms
3.26
~s
466.50 min
Hardware
triggered
strobe
1.63 ~s
427.1 ms
3.26
~s
466.50 min
~
Characteristic
Sink Current (mA)
46
46
16
16
16
16
16
16
I.OC
I
NI
LOe
NI.Oe
NI
LOe
I
Note
I = inverting: NI ;;; non-inverting: OC ;;; open collector.
Port 1 of the 8255A has 20 mA totem-pole bidirectional
drivers and 1 kQ terminators.
I/O Terminators -
220Q/330Q divider or 1 kQ pullup
220~?
+5V
---.------::---~
Interfaces
220Q/330Qr------vvv-·-------·---l---------o iSBC 901 OPTION
MULTIBUS - All signals TIL compatible
Parallel 110 - All signals TIL compatible
Interrupt Requests - Ali TIL compatible
Timer - Ali signals TIL compatible
Serial 110 - RS232C compatible, data set configuration
1
1 k>2
k~}
+ 5V .------~----_A../V'V----.-----.. ---~
iSBC 902 OPTION
Bus Drivers
Function
Characteristic _t-_Sl_n_k_C_ur_re_"_t~(m_A~)_--j
Data
Tri-state
System Clock (SOSSA CPU)
Address
Tri-state
50
50
2.76 MHz ±0.1%
Commands
Td-state
32
Auxiliary Power
Physical Characteristics
An auxiliary power bus is provided to aliow separate
power to RAM for systems requiring battery backup of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.
Width - 12.00 in. (30.48 em)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 18 oz. (509.6 gm)
2-41
AFN'()0263A
iSBC80/30
Electrical Characteristics
Environmental Characteristics
DC Power Requirements
Operating Temperature -
O°Cto 55°C
Current Requirements
Conflgu·
VCC= +5V
VOO= +12V
ration
±5,%(max)
±5%(max)
Without
±S%(max)
166 = -
ICC=3.5A
100=220 rnA
With
604116741 2
3.6A
220 rnA
-
EPROM 1
Reference Manual
Vee= -5V· VAA= -12V
±S%(max)
9800611 B - iSBC 80/30 Single Board Computer Hardware Reference Manual (NOT SUPPLIED)
IAA=50rnA
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
50 rnA
RAM only3
350 rnA
20 rnA
2.5 rnA
-
With
iSBC 5304
3.5A
320 mA
-
150 rnA
With 2K
EPROM.5
(using 6706)
4.4A
350 rnA
95 rnA
40 mA
With 2K
EPROM 5
(using 2756)
4.6A
220 rnA
-
50 rnA
With4K
EPROM 5
(using 2716)
4.6A
220 rnA
-
50 rnA
With6K
EPROM 5
(using 2332)
4.6A
220 rnA
-
50 rnA
,
.
Notes
1. boes not include power required for optional EPROMIROM, 8041AI
8741A 110 drivers, and If 0 terminators.
2. Does not include power required for optional EPROMIROM, ItO drivers
and If terminators.
°
3~ RAM chips powered via auxiliary power bus
4. Does not iriclude power required for optional EPROMIROM, 8041AI
8741A 110 drivers, and 110 terminators. Power for iSBC 530 is supplied
through the serial_port connector.
5. Includes power required for two EPROMIROM chips, 8041AI8741A
and 2200/3300 input terminators installed for 34 110 lines; all termillator
inputs low.
'
ORDERING INFORMATION
Part Number
Description
SBC 80/30
Single Board Computer
with 16K bytes RAM
2-42
AFN·00263A
iSBC 86105™
SINGLE BOARD COMPUTER
• iAPX 86/10 (8086-2) Microprocessor
with 5 or 8 MHz CPU clock
• Programmable synchronous/asynchronous RS232C compatible serial interface,with software selectable baud
rates
• Fully software compatible with iSBC
86/12A Single Board Computer
• Optional iAPX86/20 Numeric Data
'Processor with iSBC 337
MULTIMODULEProcessor
.. 8K bytes ofstatic 'RAM; expandable
on-board to 16K bytes
• Socketsfor upto 64K bytasof JEDEC
. 24/28-pin standa'rd memory devices;
expandableon:board to 128K bytes
Ii Two iSBX™ bus connectors
• 24 programmable parallel I/O lines
• Two programmable 16-bit BCD or binary
timers/event counters
• 9 levels of vectored interrupt control,
expandable to 65 levels
• MULTIBUS interface for multimaster
configurations and system expansion
• Supported by a complete family of
single board computers, memory,
digital and analog 110, peripheral
controllers, packaging and software
The iSBC 86/05 SingleBoardGomputer is a member of Intel's complete line of OEM microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained, computerbased solutions for OEM applications, The iSBC 86/05 board is a complete computer system on a single
6.75x 12.00-in. printed circuit card. The CPU, system clock, readlwrite memory, nonvolatile read only
memory, 110 ports and drivers,serial communications interface, priority interrupt logic and programmable
timers, all reside on the board. The large control storage capacity makes the iSBC 86/05 board ideally
suited for control-oriented applications such as process control, instrumentation, industrial automation,
and many others.
2-43
AFN-01819A
inter
iSBC 86105™
FUNCTIONAL DESCRIPTION
ponential instructions. Supported data types include 16, 32, and 64-bit integer, and 32 and 64-bit
floating point, 18-digit packed BCD and 80-bit temporary.
Central Processing Unit
The central processor for the iSBC 86/05 board is
Intel's iAPX 86/10 (8086-2) CPU. A clock rate of 8
MHz is supported with a jumper selectable option
of 5 MHz. The CPU architecture includes' four
16-bit byte addressable data registers, two 16-bit
memory base pOinter registers and two 16-bit index registers, all accessed by a total of 24 operand
addressing modes for comprehensive memory addressing and for support of the data structures
required for today's structured, high level languages as well as assembly language.
Architectural Features
A 6-byte instruction queue provides pre-fetching
of sequential instructions and can reduce the 750
nsec minimum instruction cycle to 250 nsec for
queued instructions. The stack-orientedarchitecture readily supports modular programming by
facilitating fast, simple, inter-module communication, and other programming constructs needed
for asynchronous real-time systems. The memory
expansion capabilities offer a 1 megabyte addressing range. The dynamic relocation scheme
allows ease in segmentation of pure procedure
and data for efficient memory utilization. Four
segment registers (code, stack, data, extra) contain program loaded offset values which are used
to map 16-bit addresses to 20-bit addresses. Each
register maps 64K bytes at a time and activation of
a specific register is controlled explicitly by pro·
gram control and is also selected implicitly by
specific functions and instructions. All Intel languages support the extended memory capability,
relieving the programmer of managing the megabyte memory space, yet allowing explicit control
'
when necessary.
Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand instructions), 8-bit and 16-bit signed and unsigned arithmetic operators for binary, BCD and
unpacked ASCII data, and iterative word and byte
string manipulation functions.
For enhanced numerics processing capability, the
iSBC 337 MULTIMODULE Numeric Data Processor extends the iAPX 86/10 architecture and data
set. Over 60 numeric instructions offer arithmetic,
trigonometric, transcendental, logarithmic and ex-
I
I
I
(41< 2168}
:
L ________
J
MUL TLBUS'· SYSTEM BUS
Figure 1. iSBC 86/05 Block Diagram
2-44
AFN·01819A
iSBC 86105™
Memory Configuration
drivers and terminators, allowing the selection
of the appropriate combination of optional line
drivers and term."ai..J:s with the required drive/
termination characteristics. The 24 programmable
I/O lines and signal ground lines are brought out
to a 50-pin edge connector.
The iSBC 86/05 microcomputer contains 8K bytes
of high-speed static RAM on-board. In addition,
the on-board RAM may be expanded to 16K bytes
with the iSBC 302 MULTIMODULE RAM option
which mounts on the iSBC 86/05 board. All onboard RAM is accessed by the 8086-2 CPU with no
wait states, yielding a memory cycle time of 500
nsec.
Serial 110
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained
on the iSBC 86/05 board. A software selectable
baud rate generator provides the USART with all
common communication frequencies. The mode
of operation (i.e., synchronous or asynchronous),
data format, control character format, parity, and
baud rate are all under program control. The 8251 A
provides full duplex, double buffered transmit and
receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The RS232C compatible interface on each board,
in conjunction with the USART, provides a direct
interface to RS232C compatible terminals, cassettes, and asynchrono',:s and synchronous modems.
The RS232C command lines, serial data lines and
signal ground line are brought out to a 26-pin edge
connector.
In addition to the on-board RAM, the iSBC 86/05
board has four 28-pin sockets, configured to accept JEDEC 24/28-pin standard memory devices.
Up to 64K bytes of EPROM are supported in
16K-byte increments with Intel 27128 EPROMs.
The.iSBC 86/05 board is also compatible with the
2716,2732, and 2764 EPROMs offering expansion
to.8, 16 and 32K bytes, respectively.
With the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these
devices is doubled, providing up to 128K bytes of
EPROM capacity on-board.
Parallel 1/0 Interface
The iSBC86/05 Single Board Computer contains
24 programmable parallel I/O lines implemented
using the lritel 8255A Programmable Peripheral
Interface. The system software is used to configure the I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In order to take advantage of the
large number of possible I/O configurations, sockets are provided for interchangeable I/O line
Programmable Timers
The iSBC 86/05 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines·
(qty)
Input
Output
Latched
Latched &
Strobed
X
X
Latched
Latched &
Strobed
X
X
X
X
Bidirectional
Control
X
2
8
8
X
X
3
4
X
X
Xl
4
X
X
Xl
1
NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or. a latched and
strobed output port or port 1 is used as a bidirectional port.
2-45
AFN·01819A
inter
iSBC 86105™
Interval Timer. Each counter is capable of operating in either BCD or binary modes. Two of these
timers/counters are available to the systems designer to generate accurate time intervals under
software control. Routing for the outputs and
gate/trigger inputs of two of these counters is
jumper selectable. The outputs may be independently routed to the 8259A Programmable Interrupt Controller and to the I/O terminators associated with the 8255A to allow external devices or an
8255A port to gate the timer or to count external
events. The third interval timer in the 8253 provides the programmable baud rate generator for
the iSBC 86/05 board RS232C USART serial port.
The system software configures each timer independently to select the desired function.· Seven
functions are available as shown in Table 2. The
contents of each counter may be read at any time
during system operation.
iSBX MULTIMODULE On·Board
Expansion.
Two 8/16-bit iSBX MULTIMODULEconnectors are
provided .on the iSBC 86/05 microcomputer.
Through these connectors, additionai on-board
110 functions may be added. iSBX MULTIMODULES optimally support functions provided by
VLSI. peripheral components such as additional
parallel and serial 110, analog 110, small mass
storage .device controllers (e_g_, cassettes and
floppy disks), and other custom interfaces tomeet
specific needs. ~y mounting directly on the single
board computer, less interface logic., less power,
simpler packaging,higher performance, and .19wer
cost result when compared to. other alternatives
such as MULTI BUS form 'factor compatible
boards. The iSBX connectors on the iSBC 86/05
provide all signals necessary to interface to the
local, on-board bus, including 16 data lines for
maximum data transfer rates. iSBX MULTIMOD;
ULE boards designed with 8-bit data paths and
using the 8-bit iSBX connector are also supported
on the iSBC 86/05 microcomputer. A broad range
of iSBX MULTIMODULE options are available.in
this family from Intel. Custom iSBX modulesmay
alsobedesigned for use on theiSBC 86/05 board.
AniSBX bus interface specification and iSBX connectors are ava:ilable from InteL
Table 2. Programmable Timer Functions
Function
Operation
Interrupt on
terminal count
When terminal count is reached,. an
interrupt request is generated. This
function is extremely useful· for
generation of real·time clocks.
Output goes low upon receipt of an
external trigger edge or software
command and returns high when
terminal count is reached. This
function is retriggerable.
Divide byN co~nter. The· output
will go low for' one. input clock
cycle, and the period from one low
gOing pulse to the next is N times
the input clock period.
Output will remain high until onehalf the count has been completed,
and go low for the other half of the
count.
Output remains high until software
loads count (N). N counts after
count is loaded, output goes low
for one input clock period.
Output goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.
On a jumper selectable basis, the
clock input becomes an input from
the external system. CPU may read
the number of events occurring
after the counter "window" has
been enabled or an interrupt may
be generated after N evel)ts occur
in the system.
Programmable
one-shot
Rate
generator
Square-wave
rate generator
Software
triggered
strobe
Hardware
triggered
strobe
Event counter
MULTIBUS™ SYSTEM BUS AND
MULTIMASTER CAPABILITIES
Overview
The MULTIBUS system bus is Intel's industry
standard microcomputer bus structure. Both 8
and 16-bit single board computers are supported
on the MULTI BUS structure with 24 address and
16 data lines. In its simplest application, the
MULTIBUS system bus allows expansion of functions already contained on a single board computer (e.g., memory and digital I/O). However, the
MULTI BUS structure also allows very powerful
distributed processing configurations with multiple processors and intelligent slave 110, and
peripheral boards capable of solving the most
demanding microcomputer applications_ The
MULTIBUS system bus. is supported with abroad
array of board level products, LSI interface components, detailed published specifications and
application notes.
.
. Expansion Capabilities
Memory and 110 capacity may be expanded and
additional functions added using Intel MULTI BUS
2-46
AFN·01819A
iSBC 86105™
MUL TIBUS system bus, to generate additional
vector addresses, yielding a total of 65 unique
interrupt levels.
compatible expansion boards. Memory may be
expanded by adding user specified combinations
of RAM boards, EPROM boards, or combination
boards. Input/output capacity may be added with
digital I/O and analog I/O expansion boards. Mass
storage capability may be achieved by adding
single or double density diskette controllers, or
hard disk controllers. Modular expandable backplanes andcardcages are available to support
multi board systems.
Table 3. Programmable Interrupt Modes
Mode
Operation
Fully nested
Interrupt request line priorities fixed
at 0 as highest, 7 as lowest.
Equal priority. Each level, after reo
ceiving service, becomes the lowest
priority level until next interrupt oc·
curs.
System software assigns lowest
priority level. Priority of all other
levels based in sequence numeric·
ally on this assignment.
System software examines priorityencoded system interrupt status via
interrupt status register.
Auto·rotating
Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e., several CPUs and/or controllers
logically sharing system tasks through communication of the system bus), the iSBC 86/05 board
provides full MULTIBUS arbitration control logic.
This control logic allows up to three iSBC 86/05
boards or other bus masters, including iSBC 80
family MULTIBUS compatible 8,bit single board
computers to share the system bus using a serial
(daisy chain) priority scheme and allows up to 16
masters to share the MULTIBUS system bus with
an external parallel priority decoder. In addition to
the multiprocessing configurations made possible with multimaster capability, it also provides a
very efficient mechanism for all forms of DMA
(Direct Memory Access) transfers.
Interrupt Capability
Specific
priority
Polled
Interrupt Request Generation
Interrupt requests to be serviced by the iSBC
86/05 board may originate from 24 sources. Table
4 includes a list of devices and functions supported by interrupts. All interrupt signals are
brought to the interrupt jumper matrix where any
combination of interrupt sources may be strapped
to the desired interrupt request level on the 8259A
. PIC or the NMI input to the CPU directly.
The iSBC 86/05 board provides 9 vectored .interrupt levels. The highest level is the NMI (NonMaskable Interrupt) line which is directly tied to
the 8086 CPU. This i~terrupt is typically used for
signaling catastrophic events (e.g., power failure).
The Intel 8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the
next eight interrupt levels. As shown in Table 3, a
selection of four priority processing modes is
available for use in designing request processing
configurations to match system requirements for
efficient interrupt servicing with minimal .Iatencies. Operating rl10de and priority assignments
may be reconfigured dynamically via software at
any time during system operation. The PIC ac·
cepts interrupt requests from all on-board I/O
resources and from the MUL TIBUS system bus.
The PIC then resolves requests according to the
selected mode and, if appropriate, issues an interrupt to the CPU. Any combination of interrupt
levels may be masked via software, by storing a
single byte in the interrupt mask register of the
PIC. In systems requiring additional interrupt
levels, slave 8259A PICs may be interfaced via the
Power-Fail Control and Auxiliary Power
Control logic is also included to accept a powerfail interrupt in conjunction with the AC-Iow signal
from the iSBC 635 and iSBC 640 Power Supply or
equivalent, to initiate an orderly shut downoHhe
system in the event of a power failure. Addition-'
ally, an active-low TTL compatible memory protect
signal is brought out on the auxiliary connector
which, when asserted, disables read/write access
to RAM memory on the board. This input is provided for the protection of RAM contents during
system power-down sequences. An auxiliary
power bus is also provided to allow separate
power to RAM for systems requiring battery backup of read/write memory. Selection of this auxiliary RAM power bus is made via jumpers on the
board.
System Development Capabilities
The development cycle of iSBC 86/05 products
can be significantly reduced and simplified by
2-47
AFN-01619A
ihtel'
iSBC 86105™
using the Intellec Series Microcomputer Development Systems. The Assembler, Locating Linker,
Library Manager, Text Editor and System Monitor
are all supported by the ISIS-II disk-based operating system. To facilitate conversion of 8080AI
8085A assembly language programs to run on the
iSBC 86105 board, CONV-86 is available under the
ISIS-II operating system.
language and eliminates the need to manage register usage or allocate.memory while still allowing
explicit control of- the system's resources when
needed.
Run·Time Support
Intel also offers two run-time support packages;
iRMX 88 Realtime Multitasking Executive and the
iRMX 86 Operating System. iRMX 88 is a simple,
highly configurable and efficient foundation for
small, high performance applications. Its mUltitasking structure establishes a solid foundation
for modular system design and provides task
scheduling and management, intertask communication and synchronization, and interrupt servicing 'for a variety of peripheral devices. Other configurableoptions include terminal handlers, disk
file system, debuggers and other utilities. iRMX 86
is a high functional operating system with a very
rich set of features and options based on an
object-oriented architecture. In addition to being
modular and configurable, functions beyond the
nucleus include a sophisticated file management
and I/O system, and powerful human interface.
Both packages are easily customized and extended by the user to match unique requirements.
IN-CIRCUIT EMULATOR
The ICE-86 In-Circuit Emulator provides the
necessary link between the software development
environment provided by the Intellec system and
the "target" iSBC 86/05 execution system. In addition to providing the mechanism for loading executable code and data into the iSBC 86/05 board,
the ICE-86 In-Circuit Emulator provides a sophisticated command set to assist in debugging software and final integration of the user hardware
and software.
PUM·86
Intel's system's implementation language,
PUM-86,is also available as an Intellec Microcomputer Development System option. PUM-86 provides the capability to program in algorithmic
Table 4. Interrupt Request Sources
Device
Function
MULTIBUS interface
Requests from MULTI BUS resident peripherals or other CPU
boards
.
8255A Programmable
Peripheral Interface
8251A USART
8253 Timers
iSBX connectors
Bus fail safe timer
Power fai I interrupt
Power line clock
External interrupt
iSBC 337 MULTIMODULE
Numeric Data Processor
Signals,input buffer full or output buffer empty; also BUS
I NTR OUT general purpose interrupt from driverlterminator
sockets
Transmit buffer empty and receive buffer full
Timer 0, 1 outputs; function determined by timer mode
Function determined by iSBX MULTIMODULE board
Indicates addressed MULTIBUS resident device has not responded to command within 6 msec
Indicates AC power is not within tolerance
Source of 120 Hz signal from power supply
General purpose interrupt from auxiliary (P2) connector on
backplane
Indicates error or exception condition
2-48
Number of
Interrupts
8; may be expanded to
64 with slave 8259A
PICs on MULTIBUS
boards
3
2
2
4
(2 per iSBX connector)
1
1
1
1
1
AFN·01S19A
iSBC 86105™
SPECIFICATIONS
Serial Communications Characteristics
SYNCHRONOUS - 5-8 bit characters; internal or
external character synchronization; automatic
sync insertion
Word Size
INSTRUCTION - 8, 16, 24, or 32 bits
DATA - 8, 16 bits
System Clock
ASYNCHRONOUS - 5-8 bit characters; break
character generation; 1,1 V2, or 2 stop bits; false
start bit detection
5.00 MHz or 8.00 MHz ± 0.1 % (jumper selectable)
BAUD RATES
Cycle Time
Frequency (kHz)
(Software
Selectable)
BASIC INSTRUCTION CYCLE
At 8 MHz -
750 nsec
250 nsec (assumes instruction in the
queue)
At 5 MHz- 1.2 p'sec
- 400 nsec (assumes instruction in the
queue)
NOTES:
Basic instruction cycle is defined as the fastest instruction
time (i.e., two clock cycles).
Asynchronous
+ 16
9600
4800
2400
1200
600
300
150
110
38400
19200
9600
4800
2400
1760
+64
2400
1200
600
300
150
75
-
NOTES:
Frequency selected by I/O write of appropriate 16-bit frequency
factor to baud rate register (8253 Timer 2).
RAM - 500 nsec (no wait states)
EPROM - Jumper selectable from 500 nsec to
875 nsec
Timers
INPUT FREQUENCIES
Reference: 2.46 MHz ± 0.1 % (0.041 p'sec period,
nominal); or 153.60 kHz ± 0.1 % (6.51 p'sec period,
nominal)
Memory Capacity/Addressing
ON· BOARD EPROM
Total Capacity
8K bytes
16K bytes
32K bytes
64K bytes
Synchronous
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
Memory Cycle Time
Device
2716
2732
2764
27128
Baud Rate (Hz)
Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
NOTES:
Above frequencies are user selectable.
Event Rate: 2.46 M Hz max
OUTPUT FREQUENCIES/TIMING INTERVALS
WITH iSBC 341 MULTIMODULE EPROM
Device Total Capacity
Address Range
2716
16K bytes
FCOOO-FFFFFH
32K bytes
2732
F8000-FFFFFH
2764
64K bytes
FOOOO-FFFFFH
27128
128K bytes
EOOOO-FFFFFH
NOTES:
iSBC 86/05 EPROM sockets support J EDEC 24/28-pin standard
EPROMs and RAMs; iSSC 341 sockets also support E2PROMs.
Function
Single
Timer/Counter
Min
Real·time
1.63 ~s
Interrupt
Programmable 1.63 ~s
one-shot
Rate generator 2.342 Hz
Square·wave 2.342 Hz
rate generator
Software
1.63 ~s
triggered
strobe
Hardware
1.63 ~s
triggered
strobe
ON·BOARD RAM
8K bytes - 0-1FFFH
WITH iSBC 302 MUL TIMODULE RAM
16K bytes - 0-3FFFH
I/O Capacity
PARALLEL - 24 programmable lines using one
8255A.
SERIAL - 1 programmable line using one 8251A
iSBX MUL TlMODULE - 2 iSBX MUL TIMODULE
boards
Event
counter
2-49
-
Dual
Timer/Counter
(Two Timers
Cascaded)
Max
Min
Max
427.1 ms
3.26s
466.50 min
427.1 ms
3.26s
466.50 min
613.5 kHz 0.000036 Hz 306.8 kHz
613.5 kHz 0.000036 Hz 306.8 kHz
427.1 ms
3.26s
466.50 min
427.1 ms
3.26s
466.50 min
2.46 MHz
-
-
AFN·01819A
iSBC 86105™
Interfaces
MULTIBUS Drivers
MUL TIBUS - All signals TTL compatible
iSBX BUS - All signals TTL compatible
PARALLEL 110 - All signals TTL compatible
SERIAL 110 - RS232C compatible, configurable
as a data set or data terminal
TIMER - All signals TTL compatible
INTERRUPT REQUESTS - All TTL compatible
Double·
Sided Centers
(in.)
Pins
(qty)
MULTIBUSTM
System
iSBX™ Bus
8·Bit Data
16·Bit Data
86
0.156
Characteristic
Sink Current (rnA)
Tri·State
Tri·State
Tri·State
Open Collector
50
50
32
20
Physical Characteristics
WIDTH - 12.00 in. (30.48 cm)
HEIGHT - 6.75 in. (17.15 cm)
DEPTH - 0.70 in. (1.78 cm)
WEIGHT - 14 oz (388 gm)
Connectors
Interface
Function
Data
Address
Commands
Bus Control
Mating
Connectors
Electrical Characteristics
DC POWER REQUIREMENTS
Viking
3KH43/9AMK12
Wire Wrap
Current Requirements
(All Voltages ± 5%)
Configuration
36
44
0.1
0.1
iSBX 960·5
iSBX 961·5
Parallel 1/0
(2)
50
0.1
3M 3415·000 Flat
or
TI H312125 Pins
Serial 1/0
26
0.1
Without EPROM'
RAM only2
With 8K EPROM'
(using 2716)
With 16K EPROM'
(using 2732)
3M 3462·0001
Flat or
AMP 88106·1 Flat
110 DRIVERS - The following line drivers are all
compatible with the 110 driver sockets on the iSBC
86/05 board
Driver
Characteristic
Sink Current (rnA)
7438
7437
7432
7426
7409
7408
7403
7400
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I
48
48
16
16
16
16
16
16
+12V
-12V
4.7A
25 mA
23 mA
120 mA
5.0A
25 mA
23 mA
4.9A
25 mA
23mA
4.9A
25 mA
23 mA
With 32K EPROM'
(using 2764)
Line Drivers and Terminators
+5V
NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus in power·down
mode.
3. Includes power required for 4 ROM/EPROM chips, and I/O
terminators installed for 16 I/O lines; all terminator inputs
low.
Environmental Characteristics
OPERATING TEMPERATURE - O°C to 55°C
RELATIVE HUMIDITY - to 90% (without conden·
sation)
NOTES:
I = inverting; NI = non·inverting; OC = open collector.
Reference Manual
143153·001 - iSBC 86/05 Hardware Reference
Manual (NOT SUPPLIED)
Port 1 of the 8255A has 20 mA totem·pole bidirec·
tional drivers and 1 kn terminators
Manuals may be ordered from any Intel sales rep·
resentative, distributor office or from Intel Litera·
ture Department, 3065 Bowers Avenue, Santa
Clara, California 95051.
1/0 TERMINATORS -220nt330n divider or 1 kn
pullup
220fll330{l (iSBC 901 OPTION)
22011
---~;-~-------------:---
<
4
3
A
A
o
2
EAA
R is reserved for future use
= is equal (for FCOMP and FTST)
> Is greater than (for FCOMP and FTST)
< is less than (for FCOMP and FTST)
and:
ERR is a 3-bit error code that specifies one of
the following error conditions:
000 No error
001 Divide by zero
010 Square root of negative number
011 Overflow
100 Underflow
101 First argument valid
110 Second argument valid
111 Reserved
Fixed Point Integer (16·BII)
Mamory Location
I
I
7
=
where:
Nota
F Is always normalized (I.e., a "1"ls assumed in the highest bit position),
yielding an effective 24·blt fraction.
M+1
F30 - F24
Contains the following information:
S = sign bit
Base Address (M)
L
S
where: S = sign bit
F30 - Fo = two's complement Integer
Memory Location
Base Address (M)
F7 - FO
F15 - Fa
F23 - F16
F7 - FO
F15 - Fa
where:
F 15 - Fo = 16-bit integer
2-85
AFN·00273A
iSBC 310A
Status Byte
connected to any of the 8 interrupt levels on the iSBC 80
bus via jumper selection.
Contains the following information:
6
I
5
4
R
R is
B is
C is
E is
where:
·0
2
R
E
I
c
Bus Interface
BI
All signals are TTL compatible.
reserved for future use
busy
operation complete without error
operation complete with error
Bus Connector
Bus Connector - 86-pin", double-sided PC edge connector withO.156·in. contact centers.
Mating Connector""'; Viking 3KH43/9AMK12
Addressing
I/O Addressing - Used to pass operation codes,
memory address boundaries, and result and status bytes
between host processor and iSBC 310A.
Port Address
Base (P)
P+1
P+2
P+3
P+4
P+5
P+6
P+7
output
OP CODE
MEM LOW
MEMHIGH
R
R
R
R
R
Inpul
R
Result byte
R
R
R
R
R
Status byte
Physical Characteristics
Width -12.00 in (30.48cm)
Height - 6.75 in. (17.15 em)
Depth - 0.50 in. (1.27 cm)
Weight - 12 oz (340.5 gm)
Electrical Characteristics
DC Power Requirements
ICC
6.7A max; 4.9A typ "
P = I/O base address of XO or X8 (where
X = any hex digit)
R = reserved for iSBC 310A usage
.OP CODE = mathematic commands (see Table 1)
MEM LOW, _ programmable base address (see MemMEM HIGH - ory Addressing)
where:
Environmental Characteristics
Operating Temperature -
O°C to 55°C
Equipment Supplied
High speed mathematics units
Standard preprogrammed ROMs (installed)
Schematics
Assembly drawing
Memory Addressing - Sixteen memory locations are
used; the first eight are used for argument/result storage; the second eight are reserved for future use.
Memory addresses are assigned from the host proc·
essor via an I/O output instruction (see I/O Addressing).
MEM LOW (the lower address byte) must be XO (where X
is any hex digit). MEM HIGH (the upper address byte)
may be any value.
Reference Manual
9800410A - iSBC 310A Hardware Reference Manual
(NOT SUPPLIED)
Reference manuals are shipped with each product"only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Interrupts
Interrupts are generated on operation complete and
operation error. Either one or both interrupts may be
ORDERING INFORMATION
Part Number
Description
SBC 310A
High Speed Mathematics Unit
2-86
AFN"00273A
iSBXTM Multimodule™
Boards
3
iSBX 331
FIXED/FLOATING POINT MATH
MULTIMODULE BOARD
• iSBX bus compatible high speed
fixedlfloating point math expansion
• Square root, log, and exponential
functions
• 4 M Hz operation
• Float-to-fixed and fixed-to-float
conversions
• Fixed point single and double precision
(16/32-bit)
• End of operation interrupt
• Floating point double precision (32-bit)
• Software reset control
• Binary data formats
• Low power requirements
• Add, subtract, multiply and divide
• iSBX bus on-board expansion eliminates MULTIBUS system bus latency
and increases system throughput
• Trignometric and inverse trigonometric
functions
The Intel'" iSBX 331 Fixed/Floating Point Math MULTIMODULE Board is a member of Intel's new line of
iSBX bus compatible MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any
iSBX bus compatible host board offering low cost incremental on-board expansion. As a result, any iSBX
bus compatible host board may be expanded to perform high speed math computations, affording up to a
40 x improvement in speed compared to software math. The iSBX 331 module performs single/double
(16/32-bit) precision fixed point plus double (32-bit) precision floating point arithmetic operations. In addi·
tion, the module performs transcendental, data manipulation, and fixed to float/float to fixed point conver·
sion operations. The command operations run entirely independent of the host board permitting efficient
concurrent processing. The iSBX board is closely coupled to the host board through the iSBX bus, and as
such, offers maximum on·board performance and frees MULTIBUS system traffic for other system
resources. Incremental power dissipation is minimal requiring only 2.73 watts.
3-1
iSBX 331
returned to TOS. There are four types of transcendental operations that can be performed in floating point numbers: trigonometric functions, logarithms, exponentials, and square roots. The results of these operations will be returned to TOS.
There are four types of data manipulation operations that can be performed in either fixed or floating point numbers: sign change of TOS, exchange
of TOS and NOS and copying or popping operands
onto or of! of TOS. Fixed to floating point conversion can be performed on floating point instructions and floating point to fixed point conversion
can be performed on fixed point instructions.
FUNCTIONAL DESCRIPTION
The iSBX 331 module uses the Intel 8231 Arithmetic Processing Unit (APU) to accomplish high
speed (4 MHz) math operation. The system software may communicate with the iSBX 331 module
across the iSBX bus using 1/0 readlwrite commands. All transfers, including operand, result,
status, and command information, take place over
an 8-bit bidirectional data bus. Operands are
pushed onto an internal stack and. commands are
issued to perform operations on the data. Results
are then available from the stack. A status byte
may be read to monitor execution completion and
the nature of the result (zero, sign, or errors). In addition, control logic is included on the iSBX 331
module to facilitate single instruction software
reset control.
The execution times of the commands are shown
in Table 2.
Interrupt Requests
There is one interrupt line from the APU that may
generate an interrupt request to the host: END
(MINTRI). The END interrupt line is active upon
command completion. The END signal is cleared
by a reset or status register read.
Command Functions
The iSBX 331 module commands fall into three
categories: double precision floating point, single
precision fixed point, and double precision fixed
point (see Table 1). There are four arithmetic operations that can be performed in either fixed or
floating point numbers: add, subtract, multiply,
and divide. These operations require two operands. The 8231 assumes these operands are located in the internal stack as Top of Stack (TOS)
and Next on Stack (NOS). The result will always be
Installation
The iSBX 331 module plugs directly into the
female iSBX connector on the host board. The
module is then secured at one additional point
with nylon hardware to insure the mechanical
security of the assembly (see Figures 1 and 2).
INTEL iSBX 331
__ ~ MULTIMODUlE
BOARD
HOST BOARD
/
;:,/
INTEL Isax
MULTIMODULE
CONNECTOR
Figure 1. Installation of iSBX 331 Module on a Host Board
3-2
AFN-01486A
iSBX 331
Table 1. Command Summary
Double Precision Floating Point Instructions (32-Bit)
Instruction
Hex
Code
Description
Stack Contents
After Execution(1)
A B C D
Status Flags
Affected(3)
ACOS
Inverse Cosine of A
0
6
R U U U
ASIN
Inverse Sine of A
0
5
R U U U
S,Z, E
S,Z, E
ATAN
Inverse Tangent of A
0
7
R B U U
S,Z
CHSF
Sign Change of A
1
5
R B C D
S,Z
COS
0
3
R B U U
S,Z
EXP
Cosine of A (radians)
eA Function
0
A
R B U U
S,Z, E
FADD
Add A and B
1
0
R C D U
S,Z, E
FDIV
Divide B by A
1
3
R C D U
S,Z, E
FLTD
32-Bit Fixed to Floating Point Conversion
1
C
R B C U
S,Z
FLTS
16-Bit Fixed to Floating Point Conversion
1
D
R B C U
S,Z
FMUL
Multiply A and B
1
2
R C D U
S,Z, E
S,Z, E
FSUB
Subtract A from B
1
1
R C D U
LOG
Common Logarithm (base 10) of A
0
8
R B U U
S,Z, E
LN
Natural Logarithm of A
0
9
R B U U
S,Z, E
POPF
Stack Pop
1
8
B C D A
S,Z
PTOF
Stack Push
1
7
A
A
B C
S,Z
PUPI
Push
onto Stack
1
A
R A
i3 C
PWR
BA Power Function
0
B
R C U U
S,Z, E
11"
S,Z
SIN
Sine of A (radians)
0
2
R B U U
S,Z
SQRT
Square Root of A
0
1
R B C U
S,Z, E
TAN
Tangent of A (radians)
0
4
R B U U
S,Z, E
XCHF
Exchange A and B
1
9
B A C D
S,Z
Double Precision Fixed Point Instructions (32-Bit)
Instruction
Hex
Code
Description
Stack Contents
After Execution(1)
A B C D
Status Flags
Affected(3)
CHSD
Sign Change of A
3
4
R B C D
S,Z,O
DADD
Add A and B
2
C
R C D A
S,Z,C, E
DDIV
Divide B by A
2
F
R C D U
S,Z, E
DMUL
Multiply A and B (R = lower 32 bits)
2
E
R C D U
S,Z,O
DMUU
Multiply A and B (R = upper 32 bits)
3
6
R C D U
S,Z,O
DSUB
Subtract A from B
2
D
R C D A
S, Z,C,O
FIXD
Floati ng to Fixed Point Conversion
1
E
R B C U
S,Z,O
POPD
Stack Pop
3
8
B C D A
S,Z
PTOD
Stack Push
3
7
A A
B C
S,Z
XCHD
Exchange A and B
3
9
B A C D
S,Z
AFN-Ot486A
3-3
iSBX 331
Table 1. Command Summary (continued)
Single Precision Fixed Point Instructions (16·Bit)
Instruction
Hex
Code
Description
Stack Contents
Status Flags
After Execution(2)
Affected(3)
Au AL Bu BL C u C L Du DL
CHSS
Change Sign of Au
7
4
R AL Bu BL Cu CL Du DL
FIXS
Floating to Fixed Point Conversion
1
F
R Bu BL Cu C L U U U
S,l,O
POPS
Stack Pop
7
8
AL Bu BL Cu CL Du DL Au
S,l
S,l,O
PTOS
Stack Push
7
7
Au Au AL Bu BL Cu CL Du
S,l
SADD
Add Au and AL
6
C
R Bu BL Cu CL Du DL Au
S,l,C, E
SDIV
Divide AL by Au
6
F
R Bu BL Cu CL D~ DL U
S,l, E
SMUL
Multiply AL by Au (R = lower 16 bits)
6
E
R Bu BL Cu CL Du DL U
S,l, E
SMUU
Multiply AL by Au (R = upper 16 bits)
7
6
R Bu BL Cu CL Du DL U
S,l, E
SSUB
Subtract Au from AL
6
D
R Bu BL Cu CL Du DL Au
S,l, C, E
XCHS
Exchange Au and AL
7
9
AL Au Bu BL Cu CL Du DL
S, l
NOP
No Operation
0
0
Au AL Bu BL Cu CL Du DL
NOTES:
1. The stack initially is composed of four 32-bit numbers (A, B, C, D). A is equivalent to Top Of Stack (TOS) and B is Next On Stack
(NOS). Upon completion of a command the stack is composed of: the result (R); undefined (U); or the initial contents (A, B, C, or D).
2. The stack initially is composed of eight 16-bit numbers (Au, AL, Bu, BL, Cu, CL, Du, Dc). Au is the TOS and AL is NOS. Upon completion of a command the stack is composed of: the result (R); undefined (U); or the initial contents (Au, AL, Bu, BL,... ).
3. Nomenclature: Sign (S); Zero (Z); Overflow (0); Carry (C); Error Code Field (E).
Table 2. Command Execution Times
Command Mnemonic
!,Seconds
Command Mnemonic
!,Seconds
SADD
SSUB
SMUL
SMUU
SDIV
DADD
DSUB
DMUL
DMUU
DDIV
FIXS
FIXD
FLTS
FLTD
FADD
FSUB
FMUL
FDIV
SORT
SIN
COS
TAN
4.25
7.5
21-23.5
20-24.5
21-23.5
5.25
9.5
48.5-52.5
45.5-54.5
52
23-54
25-86.5
24.5-46.5
24.5-94.5
13.5-92
17_5-92.5
36.5-42
38.5-46
200
1116
1029.5
1438.5
ASIN
ACOS
ATAN
LOG
LN
EXP
PWR
NOP
CHSS
CHSD
CHSF
PTOS
PTOD
PTOF
POPS
POPD
POPF
XCHS
XCHD
XCHF
PUPI
1917
1933.5
1501.5
1118.5-1783
1074.5-1739
948.5-1219.5
2072.5-3008
1
5.75
6.75
4.5
4
5
5
2.5
3
3
4.5
6.5
6.5
4
NOTE: Assumes 4 MHz operation.
3-4
AFN-Q1486A
iSBX 331
r_- -JL. C. ;.oN_'~_:~_TO. ;.R_'_
I
_
__L_ _ _....L._
(FEMALE)
__.
""'llm,no)
Figure 2. ISBX 331 MUL TIMODULE Board Mounting Clearances (Inches)
Bits 0-14: Values in the range from - 32, 768 to
+ 32,767.
SPECIFICATIONS
Word Size
Double Precision Fixed Point (32 bits)
Data-8 bits.
Isill 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I
On· Board Clock Rate
VALUE
4.0 MHz ±0.1%.
o
Bit 31:
1/0 Addressing
Function
Type of
Operation
iSBX
Connector
Port Address
Data Transfer
Command Transfer
Status Transfer
Reset
Read or Write
Write
Read
Write
XO, X2, X4, or X6
X1,X3,X5,orX7
X1, X3, X5, or X7
X8 through XF
Bits 0-30: Values in the range from - 2, 147,483,
648 to + 2, 147, 483, 647.
NOTE:
The port addresses are determined on the host iSBC micro·
computer. Refer to the Hardware Reference Manual for your
host iSBC microcomputer to determine the first digit (X) of the
connector port addresses.
Double Precision Floating Point (32 bits)
I
EXPONENT.
31 30
Bit 31:
See Table 1.
Data Formats
'I
n
AFN-01486A
,
24 23
0
MS = Sign of the mantissa. 1 represents negative and 0 represents positive.
Bits 0-23: The mantissa is expressed as a 24-bit
(fractional) value. The 8231 APU requires that floating point data be represented by a fractional manti'ssa
value between 0.5 and 1 multiplied by
2 raised to an appropriate power (exponent). This is expressed as follOWS:
sl I 1 1 1 I 1 I 1 1 I 1 1 1 I
Bit 15:
MANTISSA
Bits 24-30: ES = the exponent expressed as a
two's complement 7-bit value having a
range of - 64 to + 63.
Single Precision Fixed Point (16 bits)
VALUE
I'
~I ~I 1 1 1 I 1 1 1 1 1 1 1 1 1 I 1 I I 1 1 1 1 1 1 I I 1 1 1
Arithmetic Functions
I
S = Sign of operand. Positive values
are represented by a sign of zero (S =
0). Negative values are represented by
the two's complerilet of the corresponding positive value with a sign bit
equal to 1 (8= 1).
0
8 =Sign of the operand. Positive
values are represented by a sign bit of
zero (8 = 0). Negative values are represented by the two's complement of
the corresponding positive value with
a sign bit equal to 1 (S = 1).
Value = mantissa x 2exponent
3-5
I
iSBX 331
Device Status
Interrupts
Device status is provided by means of an internal
status register whose format is shown below:
One interrupt request may originate from the APU
indicating command completion (END).
I
BUSY
I
SIGN
I
ZERO
I
I
-I'
ERRORCODE---.
CARRY
I
Interface
iSBX Bus-All signals TTL compatible
BUSY: Indicates that 8231 is currently executing
a command (1 = Busy)
SIGN: Indicates that the value on the top of stack
is negative (1 = Negative)
Physical Characteristics
Width-6:35 cm (2.50 in.)
Length-9.40 cm (3.70 in.)
Height*-2.04 cm (0.80 in.) iSBX 331 Board
-2.86 cm (1.13 in.)iSBX331 Board +
Host Board
Weight-51 gm (1.79 oz)
ZERO: Indicates that the value on the top of stack
is zero (1 = Value is zero)
ERROR CODE: This field contains an indication
of the validity of the result of the last operation.
The error codes are:
0000 No error
1000 Divide by zero
0100 Square root or log of ne'gative number
1100- Argument of inverse sine, cosine, or
eX too large
XX10- Underflow
XX01- Overflow
'See Figure 2.
Electrical Characteristics
DC Power Requirements
Vee= +5V ±5%
lee=365 mA max.
Voo= + 12V ± 5%
100= 75 mA max.
CARRY: Previous operation resulted in carry or
borrow from most significant bit. (1 = Carry/Borrow, 0= No Carry/No Borrow.)
Environmental
If the BUSY bit in ,the status register is a one, the
other status bits are not defined; if zero, indicating
not busy, the operation is complete and the other
status bits are defined as given above.
Operating Temperature-DOC to 55°C
Free moving air across the base board and iSBX
board.
Access Time
Reference Manual
Read-1900 ns (max.)
Write-1900 ns (max.)
142668-01-iSBX 331 Floating Point Math
MULTIMODULE Board (NOT SUPPLIED)
NOTE:
Actual transfer speed is dependent upon the cycle time of the
host microcomputer. The listed times assume no operation in
progress. If an operation is executing when an access is at·
tempted, the command execution time must be added to the
above times for all accesses except status read.
Reference manuals may be ordered from any Intel
sales representative, distributor office or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, California 95051.
ORDERING .INFORMATION
Part Number
Description
SBX 331
Fixed/Floating Point Math
MULTIMODULE Board
3-6
iSBX 332
FLOATING POINTMATH
MULTIMODULE BOARD
• Add, subtract, multiply and divide
• iSBX bus compatible high speed
floating point math expansion
functions
.4 MHz operation
• End·of·operation and error interrupts
• Compatible with proposed IEEE format
and existing Intel floating point '
standard
• Software reset control
• Accessed as 110 port locations
• Single (32·bit)/double (64·bit) precision
arithmetic and data manipulation .
commands
• Low power requirements
• iSBX bus on~board expansion elimi·
nates MULTIBUSsystem bus latency
and increases system throughput
• Performs functions independently and
concurrently with the MULTIBUS host
board
The Intel® iSBX 332 Floating Point Math MULTIMODULE Board is a member of Intel's new lineof iSBX bus oompatible
MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host board
offering incremental on-board expansion. The iSBX 332 module performs single (32-bit) and double (64-bit) precision
floating point add, subtract, multiply, and divide functions compatible with the proposed IEEE floating point standard.
The command operations run entirely independent of the host board permitting efficient concurrent processing. The
iSBX board is closely coupled to the host board through ttieiSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS system tratfic for other system resources. In addition, incremental power dissipation is
minimal requiring only 2.73 watts .
3-7
AFN-01383A
iSBX332
The results will be rounded to preserve the accuracy. In
addition to the arithmetic operations, the 8232 implements eight data manipulating operations. These
include changing the sign of a double or single
preCision operand located in TOS, exchanging single
precision operands located at TOS and NOS, as well as
copying and popping single or double precision operands. See also the sections on status register and
operand formats.
FUNCTIONAL DESCRIPTION
The iSBX 332 module uses the Intel® 8232 Floating
Point Processor (FPP) to accomplish high speed math
operation. The system software may communicate with
the iSBX 332 module across the iSBX bus using 110 readl
write commands. All transfers, including operand,
result, status, and command information, take place
over an 8-bit bidirectional data bus. Operands are
pushed onto an internal stack and commands are
issued to perform operations on the data stack. Results
are then available to be retrieved from the stack. A
status byte may be read to monitor execution completion and the nature of the result (zero, sign, or errors). In
addition, control logic is included on the iSBX 332
module to facilitate single instruction software reset
control.
The execution times of the commands are all data
dependent. Table 2 shows one example of each command execution time.
Interrupt Requests
There are tVoio interrupt lines from the FPP that may generate an interrupt request to the host: END (MINTR1)
and ERINT (MINTRO). The END interrupt line is active
upon command completion and the ERINT line is active
when the current command execution results in an error
condition. The error conditions are: attempt to divide by
zero, exponent overflow and exponent underflow. Both
the END and ERINT signals are cleared by a reset or
status register read.
Command Functions
The iSBX 332 module commands fall into three categories: single precision arithmetic, double preCision arithmetic and data manipulation (see Table 1). There are
four arithmetic operations that can be performed with
single precision (32-bit) or double preCision (64-bit) floating point numbers: add, subtract, multiply and divide.
These operations require two operands. The 8232
assumes that these operands are located in the internal
stack as Top of Stack (TOS) and Next on Stack (NOS).
The result will always be returned to the previous NOS
which becomes the new TOS. Results from an operation
are of the same precision and format as the operands.
Installation
The iSBX 332 module plugs directly into the female iSBX
connector on the host board. The module is then
secured at one additional point with nylon hardware to
insure the mechanical security of the assembly (see
Figures 1 and 2).
INTEL ISBX 332
MULTIMODULE
BOARD
HOST BOARD
/'
'::"
.. >';;
~
.. j'~
INTEL ISBX
....--MULTIMODULE
CONNECTOR
.;::~
Figure 1. Installation of iSBX 332 Module on a Host Board
3-8
AFN·01383A
iSBX 332
Table 1. Command Summary
Command Bits
7 6 5 432 1 0
Mnemonic
Description
SADD
Add TOS to NOS single precision and result to NOS. Pop stack.
X 0 0 0 001 0
SSUB
Subtract TOS from NOS single precision and result to NOS. Pop stack.
X 0 0 0 0 0 1 1
SMUL
Multiply NOS by TOS single precision and result to NOS. Pop stack.
X 0 0 0 000 1
X 0 0 0 0 1
o0
o1
SDIV
Divide NOS by TOS single precision and result to NOS. Pop stack.
CHSS
Change sign of TOS single precision operand.
XOOO01 1 0
PTOS
Push single precision operand on TOS to NOS.
X 0 000 1 1 1
POPS
Pop single precision operand from TOS. NOS becomes TOS.
X 0 0 0 1 000
XCHS
Exchange TOS with NOS single precision.
Change sign of TOS double precision operand.
X 0 0 0 0 1
o1
CHSD
1 1 0
PTOD
Push double precision operand on TOS to NOS.
1 1 1
POPD
Pop double precision operand from TOS. NOS becomes TOS.
CLR
CLR status.
X 0 1 0 1 1
X 0 1
X 0 1
o1
o1
X 0 0 0 0 0 0 0
X 0 1
X 0 1
X 0 1
o 1 001
o1 o1 0
0 1 o1 1
X 0 1 0 1 1 0 0
DADD
Add TOS to NOS double precision and result to NOS. Pop stack.
DSUB
Subtract TOS from NOS double precision and result to NOS. Pop stack.
DMUL
Multiply NOS by TOS double precision and result to NOS. Pop stack.
DDIV
Divide NOS by TOS double precision and result to NOS. Pop stack.
NOTE:
X = Don't care. Operatiun for bit combinations not listed above is undefined,
Table 2. Execution Times
Command
TOS
SADD
SSUB
SMUL
SDIV
CHSS
PTOS
POPS
XCHS
CHSD
PTOD
POPD
CLR
DADD
DSUB
DMUL
DDIV
3F800000
3F800000
40400000
3F800000
3F800000
3F800000
3F800000
3F800000
3FFOOOOOOOOOOOOO
3FFOOOOOOOOOOOOO
3 F FOOOOOOOOOOOOO
3FFOOOOOOOOOOOOO
3FFOOOOOAOOOOOOO
3FFOOOOOAOOOOOOO
BFF8000000000000
BFF8000000000000
Result
NOS
40000000
00000000
40900000
3FOOOOOO
BF800000
3F800000
3F800000
3FCOOOOO
40000000
-
BFFOOOOOOOOOOOOO
-
8000000000000000
8000000000000000
3FF8000000000000
3FF8000000000000
3FFOOOOOAOOOOOOO
3FFOOOOOAOOOOOOO
C002000000000000
BFFOOOOOOOOOOOOO
-
40000000
-
-
Clock Periods
TimeCits)
58
56
198
228
10
16
14
26
24
40
26
4
578
578
1748
4560
14.5
14.0
49.5
57.0
2.5
4.0
3.5
6.5
6.0
10.0
6.5
1.0
144.5
.144.5
437.0
1140.0
NOTE:
lOS, NOS and result are in hexadecimal; clock period is in decimal.
3-9
AFN·01383A
iSBX 332
40
O.
r
ax
.)
.-___.LL._....I..L-_ _ _.L-_ _ _ _......_ _""'\
O.SOLimax.)
'.', '
.,,'., ,
1.13 (max.)
;SBX
CONNECTOR
I
iMALE)
__
,
""-'L.C_O_N_i~_:_~T_O_R-'-_-'-I.
_ _ _ _ _L-_---,
o.5°1im;n.)
iFEMALE)
Figure 2. Mounting Clearances (inches)
(bit 22) of the mantissa. In other words, the
mantissa is assumed to be a 24·bit normal·
ized quantity and the most significant bit,
which will always be 1 due to normaliza·
tion, is implied. The FPP restores this
implied bit internally before performing
arithmetic, normalizes the result, and strips
the implied bit before returning the results
to the external data bus. The binary pOint is
between the implied bit and bit 22 of the
mantissa.
SPECIFICATIONS
Word Size
Data -
8 Bits
1/0 Addressing
Function
iSBX Connector Port
Address
Type of Operation
Read or Write
XO, X2, X4, or X6
Write
X1, X3, X5, orX7
Status Transfer
Read
X1, X3. X5. or X7
Reset
Write
X8 through XF
Data Transfer
Command Transfer
Double Precision Floating Point (64 Bits)
NOTE:
Is
The port addresses are determined on the host iSBC microcomputer.
Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit (X) of the connector port address.
63
Arithmetic Functions
Bit 63:
See Table 1
M
E I
62
52
51
S = Sign of the mantissa. 1 represents neg·
ative and 0 represents positive.
Floating Point Format
Bits 52-62: E = Biased exponent. The bias is 210 - 1 =
1023.
Single Precision Floating Point (32 Bits)
Bits 0-51:
[IMPLIED BIT
S
E I
31
30
Bit 31:
M
23
22
2
o
=
S Sign of the mantissa. 1 represents neg·
ative and 0 represents positive.
=
Bits 23-30: E These 8 bits represent a biased expo·
nent The bias is 27 -1 127.
Bits 0-22:
=
M = 23·bit mantissa. Together with the sign
bit, the mantissa represents a signed frac·
tion in sign·magnitude notation. There is an
implied 1 beyond the most significant bit
3-10
M = 51·bit mantissa. Together with the sign
bit, the mantissa represents a signed frac·
tion in sign·magnitude notation. There is an
implied 1 beyond the most significant bit
(bit 51) of the mantissa. In other words, the
mantissa is assumed to be a 53·bit normal·
ized quantity and the most significant bit,
which will always be a 1 due to normal·
ization, is implied. The FPP restores this
implied bit internally before performing
arithmetic, normalizes the result, and strips
the implied bit before returning the result
to the external data bus. The binary point is
between the implied bit and bit 51 of the
mantissa.
AFN-01383A
iSBX 332
Status Byte
Interrupts
Contains the following information:
Two interrupt requests may originate from the FPP indicating command completion (END) and error conditions
(ERINT).
Interface
Bit 0 Reserved.
iSBX Bus - All signals TTL compatible
Bit 1 Exponent Overflow (V): When 1, this bit indicates
that exponent overflow has occurred. Cleared to
zero otherwise.
Physical Characteristics
Bit 3 Divide Exception (D): When 1, this bit indicates
that an attempt to divide by zero has been made.
Cleared to zero otherwise.
Width - 6.35 cm (2.50 in.)
Length - 9.40 cm (3.70 in.)
Height" - 2.04 cm (0.80 in.) iSBX 332 Board
- 2.86 cm (1.13 in.) iSBX 332 Board + Host
Board
Weight - 51 gm (1.79 oz)
Bit 4 Reserved.
·See Figure 2
Bit 2 Exponent Underflow (U): When 1, this bit indicates that exponent underflow has occurred.
Cleared to zero otherwise.
Bit 5 Zero (Z): When 1, this bit indicates that the result
returned to TOS after a command is all zeros.
Cleared to zero otherwise.
Electrical Characteristics
DC Power Requirements
Bit 6 Sign (S): When 1, this bit indicates that the result
returned to TOS is negative. Cleared to zero other,
wise.
Vee= +5V ±5%
Voo=+12V±5%
Bit 7 Busy: When 1, this bit indicates the APU is in the
process of executing a command. It will become
zero after the command execution is complete.
All other status bits should be considered to be
undefined if this bit is set.
Operating Temperature -
lee=365 mA max.
loo=75mAmax.
Environmental
O°C to 55°C
Free moving air across the base board and iSBX board.
Access Time
Reference Manual
Read - 1900 ns (max.)
Write - 1900 ns (max.)
9803204-01 - iSBX 332 Floating Point Math
MULTI MODULE Board (NOT SUPPLIED)
NOTE:
Actual transfer speed is dependent upon the cycle time of the host
microcomputer. The listed times assume no operation in progress. If an
operation is executing when an access is attempted, the command exe·
cution time must be added to the above times for all accesses except
status read.
Reference Manuals may be ordered from any Intel sales
representative, distributor office or from Intel Literature
Department,3065 Bowers Ave., Santa Clara, California
.95051.
ORDERING INFORMATION
Part Number
Description
SBX 332
Floating Point Math MULTIMODULE
Board
3-11
AFN-01383A
iSBX 350
PARALLEL 1/0 MULTIMODULE BOARD
• iSBX bus compatible 1/0 expansion
• Accessed as 1/0 port locations
• 24 programmable 1/0 lines with sockets
for interchangeable line drivers and
terminators
.
• Single + 5V low power requirement
• iSBX bus on·board expansion elimi·
nates MULTIBUS system bus latency
and increases system throughput
• Three jumper selectable interrupt
request sources
The Intel® iSBX 350 Parallel 110 MULTIMODULE Board is a member of Intel's new line of iSBX bus compatible
MULTIMODULE products. The iSBX MULTI MODULE board plugs directly into anyiSBX bus compatible host board
offering incremental on·board expansion. The iSBX 350 module provides 24 programmable 110 lines with sockets for
interchangeable line drivers and terminators. The iSBX board is closely coupled to the host board through the iSBX
bus, and as such, offers maximum on·board performance and frees MULTIBUS system traffic for other system
resources. In addition, incremental power. dissipation is minimal requiring only ..1.6 watts (not including optional
driverlterminators).
3·12
AFN.Q1382A
iSBX 350
volt power (jumper configurable) are brought to a 50·pin
edge connector that mates with flat, woven, or round
cable.
FUNCTIONAL DESCRIPTION
Programmable Interface
The iSBX 350 module uses an Intel® 8255A-5 Program·
mabie Peripheral Interface (PPI) providing 24 parallel I/O
lines. The base·board system software is used to con·
figure the I/O lines in any combination of unidirectional
input/output and bidirectional ports indicated in Table 1.
Therefore, the I/O interface may be customized to meet
specific peripheral requirements. In order to take full
advantage of the large number of possible I/O configura·
tions, sockets are provided for interchangeable I/O line
drivers and terminators. Hence, the flexibility of the I/O
interface is further enhanced by the capability of select·
ing the appropriate combination of optional line drivers
and terminators to provide the required sink current,
polarity, and driver/termination characteristics for each
application. In addition, inverting bidirectional bus
drivers (8226) are provided on sockets to allow conven·
ient optional replacement to non·inverting drivers (8216).
The 24 programmable I/O lines, signal ground, and + 5
Interrupt Request Generation
Interrupt requests may originate from three jumper
selectable sources. Two interrupt requests can be auto·
matically generated by the PPI when a byte of informa·
tion is ready to be transferred to the base board CPU
(i.e., input buffer is full) or a byte of information has
been transferred to a peripheral device (i.e., output buf·
fer is empty). A third interrupt source may originate
directly from the user I/O interface (J1 connector).
Installation
The iSBX 350 module plugs directly into the female iSBX
connector on the host board. The module is then
secured at one additional point with nylon hardware to
insure the mechanical security of the assembly (see
Figure 1 and Figure 2).
USER 110
CONNECTOR~
INTEL iSBX 350
MUL TIMODULE
BOARD
HOST BOARD
/
INTEL iSBX
~""--MUL TIMODULE
~~
eONN,eTO'
Figure 1. Installation of iSBX 350 Module on a Host Board
3-13
AFN·01382A
iSBX 350
, ,_.,~L ":.~'"
MOL .....___..u._.....Ju...._ _ _......______..........,._""'\
___
,.
1
"-C_O_NIN_S~_~_T_O_R
......_ _--'_ _S_O_C":"K_E_T_..L_ _...,
(FEMALE)
O.SOl(m,n.)
Figure 2. Mounting Clearances (Inches)
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Input
Lines
(qty)
Port
Output
Bidirectional
Unlatched
Latched &
Strobed
Latched
Latched &
Strobed
Control
A
8
X
X
X
X
B
8
X
X
X
X
C
4
X
X
X,
4
X
X
X'
X
NOTE:
1. Part of port C must be used as a control port when either port A or port 8 are used as a latched and strobed input or a latched and strobed output port
or port A is used as a bidirectional port.
1/0 Capacity
SPECI FICATIONS
24 programmable lines (see Table 1)
Word Size
Access Time
Data - 8 Bits
Read - 250 ns max.
Write - 300 ns max.
1/0 Addressing
8255A·5 Ports
NOTE:
Actual transfer speed is dependent upon the cycle time of the host
microcomputer.
iSBX 350 Address
Port A
XO or X4
Port B
X, or X5
Port C
X2 or X6
Control
X3 or X7
Reserved
X8 to XF
Interrupts
Interrupt requests may originate from the program·
mabie peripheral interface (2) or the user specified 1/0
(1 ).
NOTE:
Interfaces
The first digit of each port 1/0 address is listed as "X" since it will
change dependent on the type of host iSBC microcomputer used. Refer
to the Hardware Reference Manual for your host iSBC microcomputer to
determine the first digit of the port address.
iSBX™ Bus - All Signals TTL compatible
Parallel 1/0- All signals TTL compatible
3-14
AFN-01382A
iSBX 350
Parallel Interface Connectors
Interlace
No. of
Palrsl
Pins
Parallel 110
Connector
Parallel 110
Connector
Physical Characteristics
Vendor
Vendor
Part No.
Female
3M
3415'()001 with
Ears
Female,
Soldered
GTE
Sylvania
Canters
Connector
(In.)
Type
25/50
0.1
25/50
0.1
Width - 7.24 cm (2.85 in.)
Length - 9.40 cm (3.70 in.)
Height" ~ 2.04 .cm (0.80 in.) iSBX 350 Board
- 2.86 cm (1.13 in.) iSBX 350 Board
Board
Weight - 51 gm (1.79 oz)
6AD01251A1DD
+ Host
·See Figure 2.
Note: Connector compatible with those listed may also be used.
Line Drivers and Terminators
Electrical Characteristics
1/0 Drivers - The following line drivers and terminators
are all compatible with the I/O driver sockets on the
iSBX 350.
DC Power Requirements
Characteristic
Driver
I,oe
48
7437
I
48
NI
. I,oe
7426
7409
Configuration
+ 5V@ 320 mA
Sockets XU3, XU4. XU5, and XU6 empty las
shipped).
+ 5V@ 500 mA
Sockets XU3, XU4, XU5, and XU6 contain
7438 buffers.
+5V@620mA
Sockets XU3, XU4, XU5, and XU6 contain
iSBC 901 termination devices .
Sink Current (rnA)
7438
7432
Power Requirement
16
16
NI,oe
16
7408
NI
16
7403
I.oe
16
7400
I
16
Environmental
Note:
Operating Temperature -
I;;: .Inverting, NI = Non-Inverting, OC::::;; Open Collector
O°C to 55°C
Port 1 has 25 mA totem pole drivers and 1 kO termi·
nators.
Reference Manual
I/O Terminators -
220013300 divider or 1 kO pull up.
9803191-01 - iSBX 350 Parallel I/O MULTIMODULE
Manual (NOT SUPPLIED)
22011/33011 (is Be 901 OPTION)
22011
;
+5V
..L
1 kl1 (iSBC 902 OPTION)
a
Reference Manuals may be ordered from any Intel sales
representative, distributor office or from Intel Literature
Department, 3065 Bowers Ave., Santa Clara, California
95051.
1 kll
+5V -------.../Wf'-.- - - - - - - - 0
ORDERING INFORMATION
Part Number
Description
SBX 350
Parallel I/O MULTIMODULE
Board
3-15
AFN·01382A
iSBX 351
SERIAL 1/0 MULTIMODULE BOARD
• iSBX bus compatible 1/0 expansion
• Four jumper selectable interrupt
request sources
• Programmable synchronous/asynchronous communications channel with
RS232C or RS449/422 interface
• Accessed as 1/0 port locations
• Low power requirements
• Single + 5V when configured for
RS449/422 interface
• Software programmable baud rate
generator
• iSBX bus on-board expansion elimi·
nates MULTIBUS system bus latency
and increases system throughput
• Two programmable 16-bit BCD or binary
timerslevent counters
The Intel® iSBX 351 Serial I/O MUL TIMODULE board is a member of Intel's new line of iSBX bus compatible
MUL TIMODULE products. The iSBX MUL TIMODULE board plugs directly into any iSBX bus compatible
host board offering incremental on-board I/O expansion. The iSBX 351 module provides one RS232C or
RS449/422 programmable synchronous/asynchronous communications channel with software selectable
baud rates. Two general purpose programmable 16-bit BCD or binary timers/event counters are available to
the host board to generate accurate time intervals under software control. The iSBX board is closely
coupled to the host board through the iSBX bus, and as such, offers maximum on-board performance and
frees MULTI BUS system traffic for other system resources. In addition, incremental power dissipation is
minimum requiring only 3.0 watts (assumes RS232C interface).
3-16
AFN·01381A
iSBX 351
FUNCTIONAL DESCRIPTION·
and framing error detection are all incorporated in
the USART. The command lines·, serial data lines,
and signal ground lines are brought out to a double
edge connectorconfigurable for either an RS232C
or RS449/422 interface (see Figure 3). In addition,
the iSBX 351 module is jumper configurable for either
point-to-point or multidrop network connection.
Communications Interface
The iSBX 351 module uses the Intel® 8251A Universal
Synchronous/Asynchronous Receiver/Transmitter
(USART) providing' one programmable communications channel. The USART can be programmed
by the system software toiridividually select the
desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync).
The mode of operation (Le. synchronous or asynchronous), data format, control character format,
parity, and baud rate are all under program control.
The 8251A provides full duplex,double buffered
transmit and receive capability. Parity, overrun,
1.6-Bit Interval Timers
The iSBX 351 module uses an Intel 8253 Program"
mabie Interval Timer (PIT) providing 3 fully programmable and independent BCD and binary 16-bit
USER I/O
CONNECTOR _____
INTEL ISBX 351
MUL TIMODULE
BOARD
HOST BOARD
/
~
INTEL iSBX
. .;.:;.. _MULTIMODULE
. .;;..
.
CONNECTOR
.;:;;;::;..
.
..:
..
Figure 1. Installation of iSBC 351 Module on a Host Board
3-17
AFN.()1381A
iSBX 351
interval timers. One timer is available to the system
designer to generate baud rates for the USART
under software control. Routing for the outputs
from the other two counters is jumper selectable to
the host board. In utilizing the iSBX 351 module, the
systems designer simply configures, via software,
each timer independently to meet system requirements. Whenever a given baud rate or time delay is
needed, software commands the programmable
timers to select the desired function. The functions
of the timers are shown in Table 1. The contents of
each counter may be read at any time during
system operation.
hardware to insure the mechanical security of the
assembly (see Figures 1 and 2).
Table 1. Programmable Timer Functions
Operation
Function
Interrupt on
terminal count
When terminal count is reached, an interrupt
request is generated. This funetiol') is useful
for generation of real-time clocks.
Programmable
one-shot
Output goes low uppn receipt of an external
trigger edge and returns high when terminal
daunt is reached. This function is retri9gerable.
Rate generator
Divide by N counter. The output will go low
for one input clock cycle, and the period
from one low going pulse to the next is N
times the input clock period.
Interrupt Request Lines
Interrupt requests may originate from four sources.
Two interrupt requests can be automatically generated by the USART when a character is ready to
be transferred to the host board (i.e. receive buffer
is full) or a character has been transmitted (i.e.
transmit buffer is empty). In addition, two jumper
selectable requests can be generated by the programmable timers.
Square-wave
Output will remain high until one-half the
rate generator
count has been completed, and go low for the
other half of the count.
Software
triggered strobe
Output remains high until software loads
count (N). N counts after count is loaded,
output goes low for one input clock period.
Hardware
triggered strobe
Output goes low for one clock period N
counts after rising edge counter trigger input. The counter is retriggerable.
Event cou nter
On a jumper selectable basis, the clock input
becomes an input from the external system.
CPU may read the number of events occurring after the counting "window" has been
enabled or an interrupt may be generated
after N events occur in the system.
Installation
The iSBX 351 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nylon
1
.40
.80
MAX
" [ ' r-____
-L~~~ ~
______
_______S_O_C_K_ET______
~ ~
____
iSBX 351 MULTIMODULE BOARD
T
1.13
MAX
iSBX
CONNECTOR
(MALE)
.50
~ ~
CONNECTOR
____L-___
is_B_x__
(FEMALE)
r
____
_______S_O_c_K_ET_______ L_ _ _ __ylM'N
Figure 2. Mounting Clearances (inches)
3-18
AfN·01381A
iSBX 351
RS232C CABLING
RS449f422 CABLING
Figure 3. Cable Construction and Installation for RS232C and RS449/422 Interface
Serial Communications
SPECIFICATIONS
Word Size
Data -
Synchronous - 5 - 8-bit characters; internal character synchronization; automatic sync insertion;
even, odd or no parity generation/detection,
8 bits
I/O Addressing
I/O
Address
XO, X2, X4,
or X6
X1, X3, X5,
or X7
Chip
Select
8251A
USART
Furiction
Write: Mode or Command
Read Status
X8 or XC
Write: Countei 0
(Load Count -;- N)
Read: Counter 0
X9 or XD
Write: Counter 1
(Load Count -;- N)
Read: Counter 1
8253
PIT
Asynchronous - 5 - 8-bit characters; break character generation and detection; 1, 1 '1:>, or 2 stop
bits; false start bit detection; even, odd or no parity
generation/detection.
Write: Data
Read: Data
XA or XE
Write: Counter 2
(Load, Count -=- N)
Read: Counter 2
XB or XF
Write: Control
Read: None
Sample Baud Rate:
8251 USAAT Baud Aate (Hz)'
8253 PIT Frequency1
(kHz, Soflware Selectable)
307.2
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76
NOTE: The first digit of each port 1/0 address is listed as "X" since it will
change depending on the type of host iSBC microcomputer used.
Refer to the Hardware Reference Manual for your host iSBC
microcomputer to determine the fjrst digit of the 1/0 address.
Access Time
Read Write -
Synchronous
38400
19200
9600
4800
2400
t760
Asynchronous
-;- 16
19200
9600
4800
2400
1200
600
300
150
110
-;- 64
4800
2400
1200
600
300
150
75
-
-
NOTES: 1. Frequency selected by 110 writes of appropriate l6-bit frequency factor to Baud Rate Register.
250 nsec max
300 nsec max
2.
Note
Actual transfer speed is dependent upon the cycle time of the
host microcomputer.
3-19
Bau~ rates shown here are only a sample subset of possible
software-programmable rates available. Any frequency from
18.75 Hz to 614.4 kHz may be generated utilizing on-board
crystal oscillator and l6-bit Programmable Interval Timer
(used here as frequency divider).
AFN·01381A
inter
iSBX351
Interval Timer and Baud Rate Generator
Interfaces
Input Frequency (selectable):
ISBX Bus -
1.23 MHz ±0.1% (.813 f./Sec period nominal)
Serial - configurable for EIA Standards RS232C or
RS449/422
153.6 kHz ±0.1% (6.5 f./Sec period nominal)
EIA Standard RS232C signals provided
and supported:
Clear to Send (CTS)
Data Set Ready (OSR)
Data Terminal Ready (OTR)
Request to Send (RTS)
Receive Clock (RXC)
Receive Data (RXO)
Transmit Clock (OTE TXC)
Transmit Data (TXO)
Output Frequency:
Rate Generator
(Frequency)
Reat-Time Interrupt
(Interval)
Min.
Ma••
Min.
Ma••
Single
Timer1
18.75 Hz
614.4 kHz
1.631JSec
53.3 msec
Single
Timer"
2.34 Hz
76.8 kHz
13.0 lJSec
426.7 msec
Dual
Timer"
(Counters
o and 1
in series)
0.000286 Hz
307.2 kHz
3.261JSec
58.25 min
Dual
Timer 4
(Counters
o and 1
in series)
0.0000358 Hz
38.4 kHz
26.0 lJSec
7.77 hrs
all signals TTL compatible.
EIA Standard RS449/422 signals provided
and supported:
Clear to Send (CS)
Data Mode (OM)
Terminal Ready (TR)
Request to Send (RS)
Receive Timing (RT)
Receive Data (RO)
Terminal Timing (TT)
Send Data (SO)
NOTES: '1. Assuming 1.23 mHz clock input.
2. ,Assuming 153.6 kHz clock input.
Physical Characteristics
3. Assuming Counter 0 has 1.23 mHz clock input.
Width Length Height· -
4. Assuming Counter 0 has 153.6 kHz clock input.
-
Interrupts
Interrupt requests may originate from the USART
(2) or the programmable timer (2).
Weight -
*
7.24 em (2.85 inches)
9:40 cm (3.70 inches)
2.04 cm (0.80 inches)
iSBX 351 Board
2.86 cm (1.13 inches)
iSBX 351 Board and Host Board
51 grams (1.79 ounces)
(See Figure 2) .
..
Serial Interface Connectors
Configuration
Mode'
MULTIMODULE Edge Connector
Cable
Connector 8
25-pin', 3M-3482-1oo0
RS232C
DTE
26-pin'. 3M-3462-0001
3M3_3349/25
RS232C
DCE
26-pin', 3M-3462-0001
3M3_3349/25
25-pin', .3M-3483-1 000
RS449
DTE
.4o-pin6 , 3M-3464-0001
3M4_3349/37
37-pin', '3M-3502-1000
RS449
DCE
4o-pin6 , 3M-3464-0001
3M4_3349/37
37-pin'. 3M-350:l-:1000
NOTES: 1. Cable housing 3M-3485-4000 may be used with the connector.
2. DTE - Data Terminal mode. (male connector), DCE ..,. Data Set mode (female connector).
3. Cable is tapered at one end .to fit the 3M-3462 conneCtor.
4, Cable is tapered to fit 3M-3464 connector.
5: Pin 26 of the edge connector i.riot conne,cted.to the flat cable.
6. Pins 37, 39, and 40 of the edge connector are not connected to the flat cable.
7. May be used with 'cable housing 3M-3485-1000.
8. Connectors compatible with those listed may also be used.
3-20
AFN-oI381A
isex
351
Electrical Characteristics
Environmental Characteristics
DC Power Requirements
Temperature - 0 - 55°C, free moving air across the
base board and MUL TIMODULE board.
Mode
RS232C
RS449/422
Voltage
+5V ±0.25V
9803190·01 - iSBX 351 Serial 110 MULTIMODULE
Manual (NOT SUPPLIED)
Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Ave., Santa
Clara, California, 95051.
460 mA
+12V ±0.6V
30 mA
-12V ±0.6V
30 rnA
+5V ±0.25V
Reference Manual
Amps
(Ma •• )
530 rnA
ORDERING INFORMATION
Description
Part Number
SBX 351
Serial 1/0 MUL TiMODULE
Board
3-21
AFN-01381A
iCSTM Industrial
Control Series
4
iCS 80
INDUSTRIAL CHASSIS
• MULllBUS standard 4·slot backplane,·
expandable to 12 slots
• Slide in/out mounting rails for iSBC
power supplies
- Quick disconnect cabling for
serviceability
- Your choice of supply
• Vertical board orientation for
convection cooling
• 19·inch wide RElMA rack mounting or
NEMA type backwall mounting
brackets
• Lockable serVice panel
• All front access serviceability
- iSBC boards
- Power supplies
- Interrupt and reset buttons
- Operation indicators and fuse
• Four fans for forced·air cooling
• Submitted for approval as a UL
recognized component
• Recessed mounting space for signal
conditioning/wire termination panels
• 110/230V, 50/60 Hz operation
The iCS 80 Industrial Chassis provides industrially oriented mounting space for Intel single board computer (iSBC)
products, associated iSBC power supplies, and related iCS 9XX analog and digital signal conditioning/termination
panels. The base unit provides a 4-slot MULTIBUS backplane (iSBC 604) with expansion space and cabling to expand to
12 MUL TIBUS backplane slots by adding additional 4-slot iSBC 614s as needed (up to two). All of the 25-plus Intel
MUL TIBUS bus-compatible iSBC boards can be inserted into anyoneofthe 12 slots. In addition, over 50 products from 30
independent manufacturers have been designed for mounting into the MUL TIBUS backplane. Full MUL T1BUS
compatibility in the iCS 80 chassis also allows configuration of multiple single board computers to share system tasks
through communication over the bus (through multimaster bus arbitration built on the multiple iSBC processors).
4-1
AFN·01260A
ICS 80
FUNCTIONAL DESCRIPTION
Power Supply Flexibility
Or Large Power and Point Counts in a
Small Package
To provide a modular base on which to build a variety of
configurations, no power supply is provided in the iCS
80 Industrial Chassis. Users choose one of the low cost
Intel iSBC 635 (14-amp) or iSBC 640 (30-amp) power supplies based on their application. Slide inlout mounting
rails are provided to match the iSBC 635 and iSBC 640
supplies, and quick disconnect cabling and connectors
are provided for rapid service replacement. An AC wiring
barrier strip allows simple wiring connections for integration into larger systems (see Figure 4).
At the high end of performance for the iCS 80 chassis, a
user can build a 12-slot configuration with the Intel iSSC
640 Power Supply. This iCS 80 chassis can support the
iSSC 86/12A 16-bit computer with 112K bytes memory
(96K RAM, 16K ROM), 64 differential analog inputs, 180
digital inputs, 52 isolated digital outputs, and 8 analog
outputs (four current loops); in total a 304-channel,
mixed analog and isolated digital, input and output controller,large enough for most dedicated applications
(see Figure 3 for two other examples).
The chassis mounts directly into 19-inch standard width
RETMA (Radio-Electronics-Television Manufacturers
Association) customer provided rack. Alternately,
mounting brackets and power cabling access are provided for mounting directly on a backwall, such as the
backwall panel of a NEMA-type (National Electrical
Manufacturers Association), front-access-only cabinet.
Self Contained Low Cost Controllers
Small, self contained industrial controllers can be configured with the 4-slot cardcage and iSSC 635 power
supply. As shown in Figure 2, this packaging can also
accommodate the iCS 9XX series signal conditioningl
termination. panels.
Industrial Rack Mounting
Engineered for Industrial Applications
The MULTIBUS slbts are mounted vertically to improve
convection cooling and the top, bottom and sides are
engineered to allow maximum air·flow over the boards.
Four fans are provided as standard .to increase air flow,
allowing users to eliminate or minimize the need for
supplementary fans or air conditioning.
Front Access Serviceability
To simplify serviceability, front access is provided for all
iSBC boards, the power supply, operation indicator
lights, interrupt and reset buttons, and the AC power
fuse.
TOP VIEW
1
=Ir-------rlbl
1"'1·>------17.4-----~·1
•
0
Irnooo o
00000000
0
~-----19.0 ------~
SIDE VIEW
FRONT VIEW
Figure 1.. iCS 80 Chassis Dimensions
4-2
AFN·01280A
iCS 80
Typical Small Configuration
•
•
•
•
•
•
•
8-bit 8088 processor (iSSC 88/40)
4K bytes RAM (8K optional)
2K-16K bytes E2PROM or8K-128K bytes ROM/EPROM
16-64 analog inputs
8 analog outputs
8 isolated digital inputs
8 isolated digital outputs
OR
• 12 TIL outputs
• 12 TIL inputs
Figure 2, Small Configuration ICS 80 with ISBC 635, iCS 910 and ICS 930 Signal Conditioning/Termination Panels
Typical Maximum Configuration
• 16-bit 8086 processor (iSSC 86/30 w/RAM
MULTIMODULE)
• l68K bytes RAM (2 - iSSC 056)
• 128K bytes EPROM (or 16K E2PROM)
• 240 analog inputs (3 - iSSC 88/40 w/2 ea_ iSSX 311)
• 24 analog voltage outputs
OR
• 24 analog current outputs (4-20 mAl
• 72 isolated digital inputs/outputs
• 144 TIL digital inputs/outputs (2 - iSSC 519s)
(All iCS,9XX Signal Conditioning/Termination Panels are
not shown)
Figure 3_ iCS 80 with 12 MUL TIBUS Card Slots and iSBC 640 Power Supply, Large Configuration
Figure 4_ Rear View iCS 80 Chassis Showing Power Distribution Panel, and Cabling from ICS 80 Chassis to iCS 9XX
RETMA Mounted Signal Conditioning Panels (Top of iCS 80 Chassis)
4-3
AFN-01280A
iCS80
Process Control Equipment, UL1092. When installed as
described In the ICS 80 Installation Manual, the iCS 80
chassis provides adequate protection against shock,
fire and casualty hazards, and should comply with most
local and regional requirements for installation in ordinary locations. In addition, the ICS 80 chassis was
designed to comply with the UL requirements for Data
Processing Equipment, UL478. It has also been submitted to the Canadian Standards Association and approval
is pending under CSA category C22.2 No. 142, the Canadian Standard for Safety for Process Control Equipment
and C22.2 No. 154 for Data Processing Equipment.
Lockable Service Panel
To assist In development, checkout and service,· two
pushbuttons are provided. The .RESET button pulls low
theinitiali.ze line (INIT) on the. MULTIBUS backplane. The
INTERRUPT button pulls low one Interrupt line on ihe
MULTIBUS backplane (lNT1). Logic within the'iGS 80.6n·
sures that these buttons function with all versions of
Intel single board computers. From the front of the iCS
80 chassis, without a CRT or other panel,an operator or
service person can reset or interrupt on-going ICS 80
system operations to get attention, signal an alarm, or
start a self-test operation.
.,'
Mounting Space for Signal
Conditioning/Wire Terminations.
A front panel key provides three positions: OFF (AC
power off and key removable), ON (AC power on, pushbuttons enabled, key unremovable), and LOCK (AC
power on, pushbuttons disabled, key removable).
The iCS 80 chassis has received full Underwriters Laboratory approval (F.6 #E70842) as U.L. IJsted component
under the Underwriters Lab~rat6ries Safety Standard for
The cardcages and power supplies in the iCS 80 chassis
are recessed behind the front edge of the rack mounting
ears to provide mounting space for the iCS 9XX series
signal conditioning/termination panels and field wiring.
For smaller systems with only one or two iSeC 604/614
cardcages (4to 8 slots), up to two iCS 910, iCS920, oriCS
930 signal conditioning/termination panels can be
mounted vertically over the area where the second orthird
cardcage would mount (see Figure 2). The benefit of this
design is a completely self-contained industrial chassis
with iSBC cards, power supply,signal.conditioning and
field wiring terminations, all if] one enclosure.
SPECIFICATIONS
Equipment Supplied
Three indicator light emitting diodes record basic
chassis status. POWER ON (GREEN); RUN (GREEN);
and HALT (RED); the RESET or INTERRUPT buttons will
remove the HALT state.
U.L. Approved
a:
iCS 80 industrial chassis, mree fans for cardcages, one fan
for power supply, 4-slotcardcage with MULTIBUS
backplane, control panel with switches, indicators, keylock, power distribution barrier strip, ACpower fuse, line
filter, 115V power cable, and logic for interrupt and reset
buttons. An installation package is also provided,
including a NEMA cabinet mounting kit, power supply
extension cables, and RETMA cabinet mounting screws,
110/230 VAC operation.
Capacity
Four slots for MULTIBUS compatible single board computers, memory,IIO or other e.xpanslon boards
Expandable to 12 slots using customer plug-together
.
ISBC 614 cardcages
Front Panel Controls
Pushbuttons
.
.....
RESET: Connected to Initialize! on MULTIBUS backplane
INTERRUPT: Connected to Interrupt 1!line on MULTIBUS backplane.
.Software
See the RMX/80 Real-time Multitasking Executive
specifications for industrial related applications. In
addition, system monitors for most of the Intel single
board computers are available in the INSITE (Intel's
Software Index and Technology Exchange) User's
Program Library.
Panel Indicator Lights (LEOs)
POWER ON (green): + 5V power exists on the MULTIBUS backplane
RUN (green): CPU Is executing an instruction. Light
goes out if CPU is in WAIT or HALT state
HALT (red): CPU has executed a HALT instruction
Physical Characteristics
Height - 39.3 em (15.7 in.)
Width - 48.5 cm (19.0 in.) at front panel
43.5 cm (17.4 in.) behind front panel
Depth - 30.0 em (12.0 in.) with all protru'slons
Weight - 16.8 kg (37.0 Ib) without power supplies
Keylock
OFF: AC power off, key removable
ON: AC power on, pushbuttons enabled, key unremovable
LOCK: AC power on, push buttons disabled, key removable
(Ambient at iCS-80 air intake, bottom of chassis)
Fuse -
.Humidity;',.Upto 90% relative, noncondensing at 40·C
Environmental Characteristics
Temperature (Ambient)
Operating: O°C to 50·C (32°F to 122°F)
N.on-operating: - 40°C to :I- 85~C .
AC power (6A)
4-4
AFN'()1280A
iCS80
Electrical Characteristics
supply) peak-to-peak, max (DC to 500 kHz)
The iCS 80 chassis provides mounting space for either the
iSBC 635 or iSBC 640 power supply. Unless otherwise
stated, electrical specifications apply to both power
supplies when installed by user in iCS 80 chassis.
load change.
Output Transient Response - Less than 50 /lsec for ±50%
Maximum Watts Dissipation (load plus losses) -
Installation
Frequency: 47 to 63 Hz. Voltage (Nominal)
(Single Phase): 100, 115,215, or 230 VAC +10%, jumper
selectable.
Current:
(Including fans)
Power, max:
With ISBC 635
WllhlSBC640
3.0A max
S.6A max
103 VAC
1.SA max
2.8A max
20B VAC
315 watts
580 watts
Complete instructions for installation are contained in
the iCS 80 Site Planning and Installation Guide, including RETMA and NEMA cabinet mounting, and field
signal, ground wiring and cooling suggestions.
Input Vollage
Warranty
The iCS 80 Industrial Chassis is warranted to be free
from defects in materials and workmanship under normal use and service for a period of 90 days from date of
shipment.
Output Power
Voltage
Output Current (max)
ISSC635
ISBCB40
2.0A
14.0A
0.9A
0.8A
4.SA
30.0A
1.7SA
1.7SA
+ 12V
+SV
-SV
-12V
500W
(iSBC 640 supply). 250W (iSBC 635 supply)
Input Power
Overyollage Protection
iSSC 635
+ 14V to
+ S.8V to
- S.8V to
-14V to
ISBC 640
+ lBV
+ B.6V
- B.6V
-lBV
+ 14V to
+ S.8V to
- S.8V to
-14V to
Reference Manuals
+ lBV
+ 6.BV
- B.6V
-16V
9800799A:"" iCS 80 Industrial Cnassis Hardware Refer-
ence Manual (SUPPLIES)
9800798 - iCS 80 Industrial Systems Site Planning and
Installation Guide (SUPPLIED)
9800708A - iSBC 604/614 Cardcage Hardware Refertlnce Manual (SUPPLIED)
Combined Line/Load Regulation - ±1% at ±10% static
line change and ±50% static load change, measured at the
output connector (±0.2% measured at the power supply
under the same conditions).
Remote Sensing -
Provided for
+5
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
VDC output line
regulation.
Output Ripple and Noise -1 0 mV (iSBC 635 and iSBC 640
ORDERING INFORMATION·
The iCS 80 I ndustrial Chassis must be ordered as a kit with
an Intel power supply of your choice. Ordering as a kit will
ensure shipment of the power supply and iCS 80 chassis at
the same time. Typical configurations and ordering
instructions are:
Part Number
Description
ICS 80 Kit 635
iCS 80 system consisting of:
iCS 80 Industrial Chassis
iSBC 635 Power Supply
ICS 80, Kit 640
iCS 80 system consisting of:
iCS 80 Industrial Chassis
iSBC 640 Power Supply
4-5
AFN·01280A
iCS910/920/930
SIGNAL CONDITIONINGITERMINATION PANELS
• Digital signal conditioning (iCS 920/930)
- Sockets for optically isolated input
filters and solid state output
switches
- Pad space for transient suppres·
sors, current limiting resistors,
and voltage dividers
- Socketed fuse for overload
protection (iCS 930)
- LED/channel status indicators
• Interconnects iSBC and digital 110 ports
to field signal/control wiring
• Ribbon cable connection from panel is
pin compatible with iSBC analog, CPU,
and digital board 1/0 ports
• Barrier strip screw terminals. for
-iCS 910: 32 single·ended analog
inputs (or 16 differential signal plus
shield) plus four analog voltage
outputs. or two analog 4to 20 mA
current outputs
- iCS 920: 24 medium power digital
inputs arid/or outputs (55V, 300 mA
.
max)
- iCS 930: 16 high power AC or DC
digital inputs or outputs (280 VAC,
3A max)
• Engineering printed circuit mounting
space for customer analog input
components (iCS 910)
~ Noise fiters
- Current loop resistors
- Open circuit detection resistors
- Voltage divider resistors
- Thermistor bias current
• Flexible rnounting kits for
- 19" width RETMA rack
- NEMA type backwall
- iCS 80 Industrial Chassis
• Submitted for UL recognition
The iCS 910/920/930 Signal Conditioning/Termination Panels are heavy duty printed circuit boards with screw
terminations which allow industrial customers to easily connect their heavier gauge field signal wiring to Intel's line of 8and 16-bit single board computers, and iSBC analog and digital I/O boards. Flat ribboncabl.es connectthe iCS 910 panels
to any of the Intel iSBC 700 series analog input and output board pin-outs. Flat ribbon cables also connect the iCS 920
panels and iCS 930 panel to the 50-pin digital I/O ports (8255 or UPI) on Intel's single board computers and digital I/O
boards. Power for opto-isolators or line drivers (+5 VDC) can be supplied via thiscable from the iSBC boards. Jumpers
and a screw terminal block are provided on the iCS 920/930 panels to allow an external supply of +5V power. A similar
jumper/terminal block is provided on the iCS 910 panel to allow users to connect external +15V (or greater) compliance
voltage for larger analog output loads.
4-6
AFN'()1277A
iCS 910/920/930
FUNCTIONAL DESCRIPTION COMMON
TO iCS 91019201930
Large Wire or Spade Lug Connections
The barrier strip screw terminations on the iCS 910/920/
930 panels provide familiar connection points for factory
electricians to terminate the heavier gauge wiring often
pulled through conduits from sensors or control
elements. These screw terminals securely connect up to
14 AWG gauge wire size (16-gauge on iCS 910/920
panels). Alternately, spade lugs can be crimped on field
wiring and inserted under the screw terminals.
Mounting Flexibility and Serviceability
The iCS 910/920/930 panels were designed to be
phYSically separate from iSSC boards or the iCS 80
chassis to allow maximum mounting flexibility and ease of
serviceability. The panels and field wiring can be
mounted in one area of the cabinet where electricians
have access. Flat ribbon cable can then be run to the area
where control electronics technicians have access.
Figure 2. iCS 910/920 Signal Conditioning/Termination
Panel Mounted on a NEMA Cabinet Backwall
The iCS 910/920/930 panels may be mou nted horizontally
in a 19" standard width (RETMA) rack using a recessed
mounting panel (see Figure 1). Alternately, the panels
can be mounted on a cabinet wall (e.g., NEMA cabinet
backwall) using standoffs provided (see Figure 2). Or, for
the most compact packaging, users can mount up to two
iCS 910/920/930 panels vertically, directly on the front of
the iCS 80chassis using standoffs and holes provided (see
Figure 3).
A black metal labelling strip is provided with each iCS
910/920/930 panel. White, blank gummed labels are in·
cluded so that users can custom identify each input or
output channel. A clear plastic cover is provided to pro·
tect against inadvertent touching or damage to the
screw terminals or customer mounted components.
Figure 3. iCS 910/930 Signal Conditioning/Termination
Panels Mounted on iCS 80 Industrial Chassis
iCS 910 ANALOG SIGNAL
CONDITIONING/TERMINATION PANEL
Mixed Analog Input and Output Signals
A single iCS 910 panel connects up to 32 single ended
analog inputs (or 16 differential analog inputs plus shield)
to the iSSC 711 or iSSC 732 analog input boards. In
addition, the same iCS 910 panels canconnect up to four
analog output voltages from the iSSC 724 analog output
board, or two voltage or 4 to 20 mA current loop outputs
trom the iSSC 732 combination analog input/output
board. Three flat ribbon cables are included in the iCS
910 installation kit (two analog inputs. one analog output)
to route signals to iSSC 711/724/732 boards.
Figure 1. iCS 930 AC and ICS 920 Digital Signal
Conditioning/Termination Panel Mounted on
a 19" Width RETMA Rack
4-7
AFN·01277A
iCS 910/920/930
Engineered Signal Conditioning
Mounting Space
circuit area onto which users may mount components to
signal condition analog input signals. Pad traces and
holes are designed to allow easy mounting of R-C noise
filters, input voltage resistor/divider networks, current
loop input resistors, open circuit detection resistors, or to
supply thermistor bias current (see Figure 4 for schematic
of a typical analog input channel).
Printed circuit traces on the iCS 910 panel connect each
screw terminal analog input channel to the flat ribbon
cable connector. Users can jump straight through signal
connections if they desire. Each input channel trace,
however, passes through a custom engineered printed
OPEN CIRCUIT
DETECTION OR
THERMISTOR BIAS
RESISTORS
BARRIER
STRIP
I''']
NOISE FILTER
I
I
I
I
_L
f
I
I
..
VOLTAGE
DIVIDER
RESISTOR
I /J
FIELD WIRING
FROM
TRANSDUCER
I
I
I
I
DECOUPLING
I
I
-T-
CAPACITORS FOR
I
I
I
SIN~~~~~DED
_1..
I
-V
SHIELD
.~
I
"T~
C~~AFcrL~~=s
RIBBON
CABLE TO
ISBC-711!132
ANALOG INPUT
BOARD
_1_
-r
I
I
I
1Q]f--------------..<6>-----6---fu
Figure 4_ iCS 910 Analog Input Signal Conditining Examples
iCS 920 DIGITAL SIGNAL
CONDITIONING/TERMINATION PANEL
mounting voltage divider/threshold resistors and protection diodes.
Groups of four inputs can have. mixed voltage levels,
opto·isolation, or straight through connections in
groups of two. Output groups of four can be mixed optoisolated or high current drive in groups of two. DIP components from a wide variety of vendors are selected and
inserted by users based on their application. The iCS
920 manual recommends several alternative components and offers design assistance for your 110 configuration. Digital signal conditioning examples for several
common industrial voltages are shown in Table 1 and in
the diagrams below (see Figure 5).
The iCS 920 panel interconnects up to 24, 2-wire digital
input or output channels from barrier strip screw terminals
to the 16- or 24-bit digital .1/0 ports, standard on many
Intel single board computers and digital I/O expansion
boards. Screw terminals allow for one each 16 AWG size
wire for differential (2-wire) connections. or two each
AWG 18-gauge wire for daisy chaining grounds or power
for external 'contact sensing.
Flexibility in Isolation and Serviceability
Active Channel Indicators
Dual-in-line sockets are in series with each channel (see
Figure 5) to allow customer jumpering for straight
through connections (TTL 110), or for insertion of popular DIP packaged opto-isolators or digital output high
current driver transistors. Circuit pads are available for
Light emitting diodes (LEDs) are mounted adjacent to
each channel's screw terminals and may be jumpered in
to.indicate the Hi-Lo status of each of the 24 input or
output channels.
4-8
AFN·01277A
iCS 910/920/930
iSBC BOARD
CURRENT LIMITING
AND
THRESHOLD RESISTORS
IN FROM
FIELD
+
OPTO·ISOLATOR
SOCKETS
rI
I" (;,.; TIL 117) I
I
I
I
RIBBON
CABLE
Ry
iSBC 902
I
I
8255
I
SCREW
TERMINALS
I
I
I
1 OF 4
CHANNELS
I
I
L ___ --l
J
OPTICALLY ISOLATED DC INPUT EXAMPLE (iCS-920 panel)
+
OPTO·ISOLATOR
SOCKETS
(e.g. TIL 113)
+
iSBC BOARD
[-----,
I
I
8255
I
I
I
L- _ _ _ _
.JI
---1"
OPTICALLY ISOLATE;D DC OUTPUT EXAMPLE (iCS-920
p~mel)
iSBC BOARD
LINE DRIVER
I
I
..J
CURRENT DRIVER OUTPUT (55V, 300 mAl EXAMPLE (iCS-920 panel)
Figure 5. Digital Signal Conditioning Examples
4-9
AFN·01277A
iCS 910/920/930
Table 1. ICS 920 Digital 110 Signal Conditioning Plug·ln Component Examples
Digital Voltage Input or
Output Load Voltage
Maximum Input Current
Threshold Voltage
(rnA)
(V)
Opto·lsolators·
Diode Protection·
TIL 117
TIL117
TIL117
1N4002
1N4002
1N4002
4N36
1N4002
Opto-Isolated Input
5 VDC
12 VDC
24 to 26 VDC
48 VDC
50
50
40
3
6
6
20
12
Maximum Output Current
(rnA)
Line Driver·
Opto-Isolators·
Opto-Isolated Output
12 VDC
24 VDC
100
100
-
TIL113
TIL119
48 VDC
100
-
MCS 2
300
TI75472
-
300
150
-
GE4N40
MCS 2
Current Drivers
55 VDC
Half Wave Rectifier Outputs
24 VAC SCR
115 VAC SCR
-
• Example component - alternate source components are listed in the iCS 920 Hardware Reference'Manual.
iCS 930 AC Signal Conditioning/Termination
Panel
'
The iCS 930 panel interconnects 16 2-wire digital input or
output channels from barrier strip screw terminals to 16
bits of the digital I/O ports available on many Intel single
board computers and digital I/O expansion boards. The
iCS 930 panel differs from the iCS 920 digital signal'
conditioning/termination panel in that the iCS 930 panel
handles higher AC or DC voltages and currents (up to
280V, 3A), such as those found on many 115 VAC
machines, motor starters, and industrial control panels.
The iCS 930 panel is also recommended for optically
isolated DC outputs greater than 100 mAo
The iCS 930 screw terminals accept up to 14 AWG size
wire each for differential (2 wires per channel) connections, or two 14 AWG size wires for daisy chaining
grounds or power from external sources.
each channel can be individually mixed for AC or DC input (or AC or DC output). The user pays only for those
channels implemented. User supplied compatible modules are shown in Table 2.
DC and AC input modules are current actuated and thus
provide a 5-ms filter against spurious noise spikes or
contact bounce. AC solid state output modules provide
zero crossing turn on to minimize arcing.
Protection Circuitry
Each of the 16 channels contain a socketed fuse to protect against overload. In addition, mounting pads are
available on each channel output for user su'pplied voltage transient RC "snubber" components or inductive
pulse suppression, e.g., metallic-oxide-varistor (MOV)
for large motor starting.
Active Channel Indicators
Modular Isolation/Switching with Easy
Serviceability
Light emitting diodes (LEDs) are mounted adjacent to
each channel's screw terminals and opto-module to
indicate Hi-Lo status of that channel and to assist in
troubleshooting servicing.
Each iCS 930 panel accepts up to 16 user supplied, optically isolated input modules or optically isolated solid
state switches, for either AC or DC voltages (see Figure
6). Each module is screw mountable/replaceable and
can be mixed for AC or DC input, or AC or DC output, in
groups of four. Among groups of four inputs (or outputs)
Examples of iCS 930 input and output schematics are
shown in Figure 6.,
4-10
AFN,01277A
iCS 910/920/930
Table 2. Optically Isolated Modules Compatible with ICS 930 Signal ConditioninglTermlnation Panel
Signal Conditioning Desired
Voltage Rating
Maximum Input Current
Opto·22 Number"
Motorola Number"
AC Input -
115 VAC
220 VAC
95 to 130 VAC
180 to 280 VAC
10 mA
10 mA
IAC5
IAC5A
IAC5
DC Input -
5 )lsec Filter
Fast, 50 )lsec On
10 to 32 VDC
4 to 16 VDC
32 mA
14 mA
IDC5
IDC5B
IDC5
Output Current Rating
AC Output
12 to 140 VAC
24 to 280 VAC
3A
3A
OAC5
OAC5A
OAC5
DC Output
10 to 60 VDC
200 VDC
3A
1A
ODC5
ODC5A
ODC5
* Motorola and Opto-22 sales offices are tocated in North America, Europe, and Japan.
+5V
-,
I
,-----------
SCREW
TERMINALS
I
+
I
3
I
I
OPTO·ISOLATOR
--,
I
ISBC·902
II
I
8255
I
I
I
iSBC BOARD
~
AC INPUT EXAMPLE (iCS-930 panel)
+5V
TRANSIENT
,---------,
f:~lj ?-ZENER
DIODE
r-----,
I
RIBBON
CABLE
,--<{-'I-'---1
I
I
8255
I
L _ _ _ ~·~~ ___ ...J
I
I
..J
ISBC BOARD
DC SOLID STATE OUTPUT
8255
FUSE 3A
I
L __ ~g~~~
I
__
-.J
I
I
..J
ISBC BOARD
AC SOLID STATE RELAY OUTPUT EXAMPLE (iCS-930 panel)
Figure 6. Typical ICS 930 Signal Conditioning Examples
4-11
AFN·01277A
iCS91019201930
FLAT RIBBON CABLE
(3 'Included with
ICS·910 and 1 with
ICS-920 and 930
EOGE C.ONNECTOR TO
ISBC ANALOG OR
DIGITAL BOARDS
IC5-910, 920, or 930
SIGNAL CONDITIONING PANEL
~
RETMA BRACKET OR
NEMA BACKWALL
MOUNTING SPACERS
HIGH VOLTAGE
PROTECTION
CLEAR PLASTIC COVER
BLANK LABELS TO
IDENTIFY INPUT/OUTPUT
CHANNELS
Figure 7. Mounting Arrangements for Signal CondilioninglTerminal Panels
SPECIFICATIONS
(For iCS 910/920/930 panels unless otherwise specified)
iCS 910
Weight:
455 gm(16 oz)
Number of Lines
les 910 Panel
iCS 920
iCS 930
(Minimum, PC panel only)
455 gm (16 oz)
681 gm (24 oz)
(Maximum with all components and mounting kit installed)
1.6 Kg (56 oz)
Analog Inputs - Sixteen 3-wire (differential signal plus
shield) or 32 single ended
Analog Outputs - Four 2-wire voltage output (iSSC 724
Analog Soard) or two 2-wire current output (iSSC 732
Analog Soard)
iCS 920 Panel - Zero to 24 digital inputs or outputs in
groups of four
iCS 930 Panel -Zero to 16 digital inputs or outputs in
groups of four
Depth:
1.8 Kg (64 oz)
3.4 Kg (120 oz)
(With components and clear plastiC cover installed)
5.08 cm(2.0 in.)
5.08 cm (2.0 in.)
5.08 cm(2.0 in.)
(Barrier strip)
Connectors:
2156 screws
48 AI
12AO
2 power
2156 screws
48 DIlDO
2 + 5V power
6/32 screws
32 DIlDO
2 + 5V power
(Jl, J2, J3 to iSBC boards)
50-pin
0.1 in. centers
(2.54 mm)
Isolation Characteristics
Line-to-Line Isolation - 250 VDC or RMS AC (iCS
910/920 panels), 500 VDC or RMS AC (iCS 930 panel)
Input/Output Isolation - 250 VDC or RMS AC (iCS 920
panel), 500 VDC or RMS AC (iCS 930 panel)
50-pin
0.1 in. centers
(2.54 mm)
50·pin
0.1 in. centers
(2.54 mm)
(Mating connector: 3M .3415-0000 or TI H3-12125)
Maximum Distance from iSBC Boards
The iCS 910/920/930 panels are shipped with A-It. long
cables. With customer provided 50-conductor or twisted
pair ribbon cable, however, the iCS 910/920/930 panels
can be mounted remote from the iSSC analog or digital
I/O boards. In electrically quiet environments using
normal iSSC board line driver/receivers, the iCS
910/920/930 panels should be able to operate up to 25 ft.
(7.69m) from the iSSC board:
Physical· Characteristics
Width: 36.63 cm (14.65 in.)
Height: 8.13 cm (3.25 in.)
Thickness: 0.24 cm (0.093 in.), iCS 910/920 panel
0.32 cm (0.125 in.), iCS 930 panel
4-12
AFN·01277A
ICS 910/920/930
les 930 - AC Signal Conditioning/Termination Panel,
one 4-ft, 50-conductor ribbon cable with connectors, and
installation kit below
Electrical Characteristics
Power Requirements
iCS 920 panel - +15V ±5%, 25 mA max if iSBC 724 or iSBC
732 ±15V power is used for user mounted open circuit
detection, or thermistor bias components. Additional
power must be supplied via +15V terminal block.
Installation kit consisting of RETMA (19" rack) mounting bracket, clear plastic safety cover, labelling strip
with blank gummed labels, hex standoffs and mounting
screws
iCS 920 panel - +5V ±5%, 1.46A max (24 channels high
current drive)
ICS 920 Channel
Configuration
Documentation· Supplied
Maximum per Channel Currenl
(Includes pull ups, LEDs,
Isolalors, drivers)
TIL in
TIL out
Opto·lsolated in
Opto-isolated out
Open collector driver
output
A schematic diagram and assembly diagram are supplied
with each iCS 910/920/930 panel.
23mA
23mA
23 rnA
41 rnA
61 mA
Reference Manuals
9800800A - iCS 910 Analog Signal ConditioninglTermination Panel Hardware Reference Manual (NOT SUPPLIED).
.
Note: Both iCS 920 and iCS 930 panels have jumpered provision for
externally supplied +5V power via a screw terminal block.
9800801A - iCS 920 Digital Signal ConditioninglTermlnation Panel Hardware Reference Manual (NOT SUPPLIED)
iCS 930 panel - +5V ±5%, 320 mA max. Output AC or DC
channel: 20 mA/chan max; Input AC or DC channel: 12
mA/chan max.
9800802A - iCS 930 AC Signal ConditioninglTermination Panel Hardware Reference Manual (NOT SUPPLIED)
Maximum Power Dissipation
iCS 910 panels - 3 watts with 16 channels analog input
signal conditioning and +15Vexternal compliance voltage
iCS 920 panels - 12 watts with 24 channels each
containing high current driver outputs
iCS 930 panels - SO watts with 16 channels of AC or DC
output
9800798A - iCS 80 Systems Site Planning and Installation Guide (NOT SUPPLIED), but supplied with iCS 80
Industrial Chassis
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Underwriters Laboratory (ULl Recognition
The iCS 910/920/930 signal conditioning/termination
panels have been submitted to Underwriters Laboratories
for approval as a UL recognized component under the UL
safety standard for process control equipment, UL 1092.
Installation
Complete instructions for installation and service are
contained in the. applicable iCS 910/920/930 Hardware
Reference Manual. Additional system level information
is available in the iCS 80 Systems Site Planning and Installation Guide, including RETMA and NEMA cabinet
mounting, field signals, ground wiring and cooling suggestions.
Environmental Characteristics
Operating Temperature - 0 to 70°C (32°F to 15S0F)
Relative Humidity - 0 to 90%, noncondensing
Hardware Supplied
les 910 - Analog Signal Conditioning/Terminating
Panel, three 4-ft, 50-conductor flat ribbon cables with
connectors, and installation kit below
les 920 - Digital Signal Conditioning/Termination
Panel, one 4-ft, 50-conductor flat ribbon cable with connectors, and Installation kit below
warranty
The iCS 80 Industrial Chassis is warranted to be free
from defects in materials and workmanship under normal use and service for a period of 90 days from date of
shipment.
ORDERING INFORMATION
Part Number
Description
ICS 910
Analog signal conditioning/
termination panel
iCS 920
Digital signal conditioning/
termination panel
iCS 930
AC signal conditioningltermlnation
panel
4-13
AFN·01277A
iSBC 941
INDUSTRIAL DIGITAL PROCESSOR
• Provides measurement and control of
common industrial digital.input and.
..
output signals·
• Compatibiewith8041A Universal
Peripheral Interface (UPI·41A) sockets
such as those provided on Intel iSBC
80/30 and theiSBC 569 Intelligent
Digital Processor
- Sense change state
- Pulse counting
- Pulse generation .
- Period measurement
- Frequency measurement
• Applications include
- Switch sensing
- Motor speed control
- Stepper motor actuation
- Serial communications
.Off·loads host. processor from time·
consuming task·of digital 1/0
processing
• 16 progl'ammablel/O lines, TTL.
compatible
• Simplified comMand protocol with
MCS 80/85/86 "Master" Processor
• Single +5V supply
The iSBC 941 Industrial Digital Processor is a 40~pin DIP device ""hich provides the user with easy-to-useprocessing of
digital input and output signals desired in many industrial automation environments. One 6f nine digital 1/0 functions can
be selected at anyone time for measuring, counting, or controlling up to 16 separate 1/0 lines. Additional utility
commands. allow reading. or setting the condition of unused 1/0 lines. Simplex serial input and output modes can
assemble or.disassemble bytes transmitted asynchronously over TTL lines, including insertion and deletion of start/stop
bits.· The device has two a-bit, TTL compatible 1/0 ports.
'
BLOCK DIAGRAM
PIN CONFIGURATION
X,
x,
=
Vee
Vss Voo
4
CLOCK {
~~
RESET
WR
CONTROL
INTERFACE
Rii
{ WR
~
CS
4-14
} To. 'T1 TEST INPUTS
,SYNC.
AFN-01454A
iSBC 941
Stepper motors designed for up to eight
phase control may be controlled directly
or stepper motor translator signals may
be generated ..
FUNCTIONAL DESCRIPTION
Industrial Digital Processor
Designed to operate as a slave device, the iSBC 941
processor may be requested to implement one of nine
Primary Functions. These Primary functions are subroutines which are stored in program memory of the iSBC
941 device. Each Primary Function has a specific 1/0
task. Available Primary Functions include:
EVENT
-
Monitors and counts up to·eight input
lines for event counting or comparison
to a preset count for each" line.lnterrupts may be generated or counter can
.be read ·on-the-f.ly· without changi ng its
state ..
FCOUNT
-
Measures frequency of· one of eight
digital inputs over a programmable
period. Inputs may be selected under
user program control or iSBC 941 processor may be requested to automatically scan inputs in sequential order,
update, and hold or interrupt for reading
.each 16-bit counter. Input frequencies
up to 18 KHz may be measured.
FREQ
-
-
Measures the period of up to four inputs (single cycle).
SCAN
-
Monitors up to 16 input lines for change. of-state and direction of change.
Change-of-state interrupts may be
generated. User can individually disable inputs.
-
Control Commands available are:
EN FLAG - Enables the iSBC 941 processor to send interrupts via its I/O lines tothe host processor.
-
Enables simplex transmission of asynchronous serial' data bits for communications applications. Includes
insertion of start/stop bits. Baud rates
up to 1200 baud may be programmed.
SHOT1
-
Emulates a gated one-shot pulse generator (edge triggered and retriggerable modules) with programmable delay
and period. Complimentary, synchronous one-shots can ,be created on
separate output' lines, on up to eight
lines,
INITPF
- Selects the desired Primary Functio(1 and
initializes parameters used by the Primary
Function.
. '
LOOP
- Continuously executes the selected Primary
Function at a specific rate.
PACIFY - Resets all iSBC 941 processor I/O lines to
the input state and clears all control variables .
PAUSE
Enables simplex reception and 8-bit byte
assembling of asynchronously transmitted serial data bits for communications applications. Includes detection/
deletion of start/stop bits. Baud rates up
to 1200 baud may be programmed.
SEROUT
STEPPER
Commands recognized by the iSBC 941 Industrial Digital
Processor are defined by one of two categories, Control
Commands or Utility Commands. Control Commands
are used to start and stop a Primary Function. Utility
Commands are typically associated with moving a byte of
information or reading the status of the iSBC 941 processor through the COMMAND/DATA Bus Buffer.
Generates up to eight gated frequency
outputs with separately programmable
pulse. width and periods and complementary synchronous outputs.
PERIOD
SERIN
Any of the sixteen UPI processor 1/0 lines that are not
used by a Primary Function are available for general purpose use; e.g., direct status reads or latched digital outputs, through the use of Utility Commands.
- Commands the iSBC 941 processor to exit
the LOOP or INITPF mode.
Utility Commands include:
CLRP1
- Sets (to logic level 0) selec.ted iSBC 941
(CLRP2)
processor Port 1 (Port 2) output lineS. All
other lines are unaffected. ..
ENP11N - Enables user-defined mask to inhibit the
(ENP2IN)
writingof.:O's by theiSBC 941 processor to
Port 1 (Port 2) input lines. This function is
used by SETP1 (SETP2), CLRP1 (CLRP2),
STEP and LOOP.
- Generates up' to eight programmable
outputs that may be use.d for control of
stepper motors. Step rate, .step count,
and step direction are u'ser defined.
4-15
IDEN
....:. Requests the identity code of the iSBC 941
processor accessed.-
LATCH
-
Transfers to holding area for reading ail eight
counters used by the EVENT Primary Function.
RDEC
-
Enables host processor to read one of eight
user-specified event accumulators used by
the EVENT Primary Function.
RDFQ
-
Reads bytes from the iSBC 941 processor's
AFN-01454A
iSBC 941
RDHR
-
first-in-first-out (FIFO) buffer (used by
SCAN and SEROUT Primary Functions).
(5) Enable selected SCAN input lines (Parameter byte)
(enabled in groups of eight)
Enables the host processor to read the contents of the iSBC 941 holding register
specified (used by PULSE, PERIOD, and
EVENT Primary Functions).
(6) Terminate parameter list
RDIDV
- Enables the host processor to read the iSBC
941 processor's input-data-valid (IDV) flags.
RDLC
- Enables host processor to read one of eight
user specified EVENT counters previously
stored by LATCH command.
RDP1
(RDP2)
- Reads data byte present at iSBC 941 processor Port 1 (Port 2) and sends to host processor.
SETOE
- Sets output enable parameter bits.
(Command byte)
(7) Enable iSBC ·941 processor inter- (Command'byte)
.rupt outputs
(8) Request execution
_ (Command byte)
PIN DESCRIPTION
SETP1
- Sets (to logic level 1) selected iSBC 941
(SETP2)
processor Port 1 (Port 2) output lines. All
other lines are unaffected.
Signal
Description
Do-~
Three-state, bidirectional COMMAND/DATA
BUS BUFFER lines' used to interface the iSBC
941 processor to an 8-blt master system data
bus.
'
Plo-P 17 8-bit, PORT 1 Quasi-bidirectional I/O lines.
SETSF
- Sets the Time Reference Period scale
factor for value.
P20-P27 8-bit, PORT 2 quasi-bidirectional 1/0 lines.
Control can configure P24 as OBF (Output
Buffer Full), P25as IBF (Input Buffer Full) to send
interrupt signals to·master CPU.
WRP.1
(WRP2)
- Allows host processor to write to iSBC 941
processor Port 1 (Port 2).
I/O write input which enables the master CPU
to write data and command words to the iSBC
941 COMMAND/DATA BUS BUFFER.
Simple Command Protocol
iSBC 941 functions may be implemented with minimum
software overhead required of the host processor. An
easy-to-implement protocol ensures that communication between the iSBC 941 processor and host CPU is
straightforward and uncomplicated.
Implementing a Primary Function- involves simple programming; the host processor transmits to the iSBC 941
processor a command byte followed by parameter bytes
(the number of parameter bytes required is dependent
upon the Primary Function selected). For example, to
execute the Primary Function SCAN:
(1 ) Initialize iSBC 941 processor
I/O read input which enables the master CPU
to read data 'and status words from the COMMAND/DATA BUS BUFFER or status register.
CS
Chip select Input used to select one iSBC 941
processqr out of several connected to a common data bus.
.
Ao
Address input used by the master processor to
indicate whether byte transfer is data or command.
To, TI
Input pins used by variousiSBC 941 processor
routines.
XI, X2
Inputs for a crystal, LC or .an external timing
signal todeterrTiine the internal oscillator
frequency.
SYNC
Output signal which occurs once per ISBC 941
instruction cycle. SYNC can be used as a
strobe for-external circuitry.
RESET
Input used to reset status flip-flops and to
prepare iSBC· 941 processor to receive com·
mands ..
(Command byte)
(2) Select SCAN as Primary Function (Parameter byte)
and select internal or external time
reference
(3) Program Time RefereJJce Period (Parameter byte)
(scan rate - this byte is required
only if internal time reference was
selected in (2) )
(4) Define return 'message format
RD
(Parameter byte)
4-16
Vcc
+ 5V power supply pin.
Voo
+ 5V during normal operation.
Vss
Circuit ground potential.
EA
Circuit ground potential.
58
Connect to +5V through 10K-ohm pull-up
resistor"
..
AFN'()1454A
iSBC941
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings·
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This Is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not implied. Exposure to absolute maximum rating con·
dltlons for extended periods may affect device reliability.
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150'C
Voltage on Any Pin With Respect
to Ground .......................... 0.5V to + 7V
Power Dissipation .......................... 1.5 Watt
D.C. and Operating Characteristics
TA=O'C to 70·C, vss=ov, vcc= +5V ±5%
Symbol
Parameter
Min.
Max.
Unit
-0.5
0.8
V
V
Test Conditions
VIL
Input Low Voltage (All Except X .. X2l
VIHI
Input High Voltage (All except Xl, X2, RESET, WR, CS)
2.0
Vcc
V IH2
Input High Voltage (Xl' X2, RESET)
3.0
Vcc
V
V IH3
Input High Voltage (WR, CS)
2.2
Vcc
V
VOLl
Output Low Voltage (02-07, Sync)
0.45
V
IOL=2.0 rnA
VOL2
Output Low Voltage (All Other Outputs Except Prog)
0.45
V
IOL= 1.6 rnA
VOHI
Output High Voltage (0 0-0 7)
2.4
V
IOH= -400,..A
VOH2
Output High Voltage (All Other Outputs)
2.4
V
IOH= -50,..A
IlL
Input Leakage Current (To, T l , RD, WR, CS, Ao,)
±10
,..A
VSS';;VIN';;V CC
loz
Output Leakage Current (00-07, High Z State)
± 10
,..A
Vss + 0.45';;V IN .;;VCC
lUI
Low Input Load Current (PIOP17, P20P27)
0.5
rnA
V IL =0.8V
IU2
Low Input Load Current (RESET, SS)
0.2
rnA
VIL =0.8V
100
Voo Supply Current
15
rnA
Icc+ 100
Total Supply Current
125
rnA
Max.
Unit
A.C. Characteristics
TA=O·C to 70·C, vss=ov, vcc= voo= + 5V ±5%
DBB READ
Symbol
Min.
Parameter
RD~
0
ns
0
ns
Test Conditions
tAR
CS, Ao Setup to
tRA
CS, Ao Hold After ROt
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
225
ns
C L=150pF
tRO
RD~
225
. ns
C L =150pF
100
ns
ns
250
to Data Out Delay
tRoF
ROt to Data Float Delay
tRV
Recovery Time Between Reads And/Or Write
300
tCY
Cycle Time
2.5
15
,..s
Min.
Max.
Unit
ns
DBBWRITE
Symbol
Parameter
WR~
tAW
CS, Ao Setup to
0
ns
tWA
CS, Ao Hold After WRt
0
ns
tww
tow
WR Pulse Width
250
ns
Data Setup to WRt
150
two
Data Hold Aftert WRt
ns
0
ns
4-17
Test Conditions
AFN.()1454A
iSBC 941
1. READ OPERATION-DATA BUS BUFFER REGISTER.
I_--+-IRV---_
-----.-'AR-
I----',,-----!
"\
Y
--,o'-l
~--"D-I
6~"TA BUS
. _'AD
(OUTPUT)
-tRA_
\
(READ CONTROLI
<~---OATAVALIO=----1»'----------
2. WRITE OPERATION..,.. DATA BUS BUFFER REGISTER.
". .
4
~ -'A-W-_-~-.-'----'W-W----U--~_'-W_~A-~--'-----------(WRITE
B OR Ao
.....
~
.
(SYSTEM'S
ADDRESS BUS)
. ,-'..
CON TROll
_,Dw_fl,WD.
'V
UNPUTI____M_Ay_C_"_AN_G_'-:---'--JI'
DATA BUS
DATA
_OATAVALIO ______
W
DATA
Jt\'-_ _ _ _M_Ay,. .C_"_AN_G_'_____
Reference Manuals
iSBC 941 Industrial Digital Processor User's
Guide (NO:r SUPPLIED)
9803077 -
Reference manuals are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or fromiritel Literature Department, 3065.Bowers
Avenue, Santa Clara,Ca:iifornia95051.
ORDERING INFORMATION
Part Number ·Description
SBC 941
Industrial Digital Processor
AFN·01454A
Run- Time Systems
Software
5
iRMX 80
REAL·TIME MULTI·TASKING EXECUTIVE
• Small, efficient nucleus
• Designed for Intel® iSBC 80110B,
iSBC 80120·4, 80124 and iSBC 80130
based applications
• Simple user task interface
• Comprehensive 110 support
• Completely user configurable through
interactive configuration .utility
• Library of flexible modules
• Structured application environment
• Priority·oriented scheduling
The Intel@ iRMX 80 Real-Time Multi-Tasking Executive is an easy-to-use, sophisticated software system
which operates on Intel's 8-bit single board computers and System 80 packaged systems. The iRMX 80
executive provides real-time facilities for priority-based resource allocation, intertask communications,
standard 1/0 device control, and other features suitable for many applications including medical
electronics, industrial process control, instrumentation, test systems, and data communications. The
iRMX 80 package provides the framework that allows system developers to begin immediate application
software implementation. The implementation and integration process is aided by the Interactive Con'
figuration Utility (ICU80) program, a configuration tool which accelerates the development process.
Figure 1_ Structure Diagram
5-1
iRMX80
time facilities such as intertask communication
and control are included.
FEATURES
The iRMX 80 executive provides users of Intel
Single Board Computers simple, easy-to-use tools:,
"PrioritY-Oriented Scheduler
for creating a wide range of application systems.
The most popular features of the iRMX 80 are:
The iRMX 80 scheduler insures that the highest
priority task. which is ready tO,execute is given
Structured Environment
system control, allowing the application,system
to be responsive to its external world.
The iRMX 80 executive provides a consistent
structure, as diagrammed iii Figure 1, from application to applica,tion thl)s allo""ing experience
Comprehensive 1/0 Support
gained on one system to be easily'transferred to
The iRMX 80 libraries contain support for a wide
otherll. Often, entire programs may be used in
range of 1/0< boards supplied by Intel, simplifying
.
multiple applications.
the addition of peripherals to an application
,
system. For applicatio,ns whiqhrequirecustom
boards the iRMX 80 device handler philosophy
allows easy addition of user written handlers,
Simple Interface
The iRMX 80 executive provides a simple, straightforward program interface for user programs. This
int(!rface is consistent throughout the range of
facilities offered, reducing the number of concepts which must be learned.
.
Li~rary Modu!es
The'iRMX 80 executive is constructed in a thor·
oughly modular manner with the full. range of. facil"
ities being offered in multiple library modules; see
Table 1, allowing easy selection of the exact facil'
ities required.
Small Nucleus
The iRMX 80 nucleus provides a small, efficient
foundation upon which application systems may
be easily built. A wide range of multi-tasking, real-
.
'Interactively Configurable
The Interactive Configuration Utility (ICU80) pro·
gram provides the user .with an easy-to-use method of configuration of' iRMX 80-basedapplications. Responding to. questions from the ICU80
program runnjrigon the Intellec Microcomputer
Development System, the. user tailors the application system- by selecting modules, e.g., nucleus
flexibility as shown in Figure 2, from the wide
.., variety of iRMX 80 facilities. The resultant system
contains only the modules necessary for its use,
. allowing the iRMX 80 executive to fit a wide range
of applications from small special purpose dedicatedapplications to large general purpose systems.
.
Figure 2. Configuration Flexibility Provides Application Freedom. The IRMX 80 executive allows you the
freedom to choose from a wide range of iSBC family processors and peripherals upon which
your application may be built. It allows you to break the software "chain" which ties your appli,
cation to a Single processor type and thereby gain application freedom.
5-2
AFN-01553A
iRMX 80
Board Technological Support
iRMX 80 DFS allows for either Intellec Development Systems, ISIS-II compatible media format, or
a user specified format. iRMX 80 DFS offers the
following services in an ISIS-II compatible media
format:
The iRMX 80 executive provides support for a
range of processor technologies from. the 8080based iSBC 80/10 Single Board Computer to the
8085-based iSBC 80/30 Single Board Computer.
Applications are offered an easy upgrade path
with the iRMX 80 executive which allows greater
price/performance to be achieved without expensive software modification.
•
•
•
•
•
•
•
Extensive Debugging Aids
The iRMX 80 executive provides two user oriented, interactive software" debugging aids. The
debuggers allow memory examination and modification, execution breakpoints, and automatic
stack overflow monitoring. These powerful aids
allow simplified task debugging and faster application system development.
OPEN a file for processing
READ data from file
WRITE data to a file
SEEK to a specific location within a file
CLOSE a file to further processing
RENAME a file
DELETE a file.
a
For those applications which require unique
media formats the iRMX 80 executive offers a
level of processing which allows complete user
flexibility in formatting data. The services offered
are:
The various facilities offered by the iRMX 80 executive are provided as independent library modules, thus allowing simple inclusion or exclusion,
depending on the user's specific requirements.
These facilities are described below.
•
•
•
•
•
•
•
Nucleus
Terminal Handler
The iRMX 80 executive provides nuclei for operation on various iSBC single board computers. The
nuclei provide real-time scheduling, interrupt
handling, intertask communications, and task
control. The services offered are:
The iRMX 80 terminal handler provides a data path
between a console device (CRT or TTY) and user
tasks. Communications between task and device
are affected by using the nucleus services SEND
and WAIT. Two versions of the terminal handler
are offered:
FACILITIES
• Send a message from one task to another
• Accept a message from another task
• Wait for a message to be transmitted from
another task
• Transmit a special interrupt message to a task
• Suspend execution of a task temporarily
• Continue execution of a previously suspended
task.
SEEK to a specific track
READ a sector
WRITE a sector
FORMAT a track
RECALIBRATE to Track 0
VERIFY a sector
DELETE a sector.
1) Full Terminal Hand/er - The full terminal handier has a built-in interface to the debugger. It
also provides for:
• Correction of data previously input
~ Automatic buffering of data prior to a read request
• Priority output path which allows "emergency" messages to bypass any other messages which may be queued for output
• Automatic baud rate search to determine
communications terminal speed.
Disk File System
The iRMX 80 Disk File System (DFS) provides for
the filing and retrieving of data using di.sks. The
Table 1_ iRMX 80 Memory Requirement
Memory Requirements··
(Bytes)
Module
Nucleus
Full
Terminal
Handler
Minimal
Terminai
Handler
Free
Disk
Space
File
Manager System
Minimum Development System
Requirements
Disk
I/O
Analog
I/O
Bootstrap
Loader &
Initializer
Operating
System
Memory
Size
(Bytes)
Minimum
Diskette
Drives
ISIS-.11
64K RAM
2
PROM"
2K
3K
600
1K
5.5K
700
800
600
RAM
250
950
120
250
1.6K
100
50
900
·Indlcates amount of code which can be configured In PROM .
•• All figures are a'pproximate.
AFN·01553A
5-3
iRMX 80
The minimal terminal .handler provides a limited feature version of the full terminal handler for memory
space critical applications. The minimal terminal handler provides for correction of data previously input.
set of questions on the terminal of the Intellec
Development System and elicits the configuration
information about the application system, e.g.
CPU TYPE: BO/30,or TERM HNDLER: FULL. After
describing the application system configuration
the ICU80 program will initiate the housekeeping
chores (linking and locating), thereby supplying
the target iRMX 80 application. The result is the
rapid development of the target iRMX 80 application system.
2) Minimal Terminal Handler -
Free Space Manager
The iRMX 80 free space manager provides the
capability of dynamically allocating RAM memory
based upon user requests. Requests may be made
for any size memory blocks and will be accommodated based on memory availability. The free
space manager services are:
The iRMX 80 generation process allows application programs written in PUM-80, FORTRAN-80,
BASIC-80, or 8080/8085 Assembly Language to be
merged with the specific iRMX 80 modules desired, see Figure 3. The system may then be debugged using Intel's sophisticated In-Circuit Emulation (ICE™) products oriRMX 80 debugger. The
final application system is then available for
either PROM or disk-based systems.
• Request memory
• Release memory.
Analog Handlers
The iRMX 80 analog handlers provide a convenient
mechanism for obtaining and transmitting analog
values between user tasks and Intel'siSBC 711,
724 and 732 Analog Boards. The analog handlers
offer a full range of services including:
•
•
•
•
•
Repetitive channel input
Sequential channel/single gain input
Sequential channel/variable gain input
Random channel/variable gain input
Random channel output.
The input and output modules are individually
configurable allowing greater application flexibility.
Bootstrap Loader
The iRMX 80 bootstrap loader allows those applications using disk to create essentially a "soft"
system that may be loaded into RAM from disk
rather than being permanently PROM" resident.
This provides greater application flexibility in
building and supporting disk-based systems.
iRMX 80
LIBRARY
Interactive Configuration
The Interactive Configuration Utility (ICU80) program provides relief from the burden of manually
creating hardware configuration tables and combining selected software components. Using the
environment information, the iRMX 80 nucleus effectively controls and orchestrates the application system.
DEBUG
r-:-l
W
{j D
APPLICATION
SYSTEM
EXECUTE
v=> 0
The iRMX 80 package provides two avenues. for
configuring applications; an effective macro
mechanism allows specific detail manipulation of
structures for the experienced iRMX 80 user or,
secondly, an easy-to-use interactive ICU80 utility
program generates the structures automatically.
This latter program displays a clear and concise
Figure 3. The System Generation Process"
5-4
AFN-01553A
iRMX80
Free Space Manager
Disk File System
Analog Handlers
Debuggers
Bootstrap Loader
Configuration Macros
Interactive Configuration Utility Program
(ICU80)
Problem Reports
Reference Manuals
SPECIFICATIONS
Supported Hardware
SINGLE BOARD COMPUTERS
iSBC 80/10A
iSBC
iSBC
iSBC
iSBC
iSBC
80/10B
80/20
80/20·4
80/24
80/30
MASS STORAGE CONTROLLERS
Reference Manuals
iSBC 202
iSBC 204
9800522 - iRMX 80 User's Guide (SUPPLIED)
9803087 - iRMX 80 Installation Instructions (SUPPLIED)
142603 - iRMX 80 Interactive Configuration Utility User's Guide (SUPPLIED)
143238 - Introduction to the iRMX 86/88 RealTime Multitasking Executives
Reference Manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representa·
tive, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.
ANALOG BOARDS
iSBC 711
iSBC 724
iSBC 732
iSBC 711A
iSBC 724A
iSBC 732A
iRMX 80 Executive Shipping Package
Single and double density diskettes containing:
iSBC 80/10, 80/20, and 80/30 Nuclei
Terminal Handler
Minimal Terminal Handler
ORDERING INFORMATION
Part Number
Description
RMX 80
Real·Time Multi·Tasking
Executive
AFN·01553A
5-5
iMMX 800
MULTIBUS®MESSAGE EXCHANGE SOFTWARE
• Supports 8 and 16·bit multiprocessing
on the MULTIBUS® system bus
.
• Manages shared address space and
transfers 8 and 16·bit data
• Provides a uniform easily·used inter·
face for iRMX™ 80, iRMX™ 86, iRMX™
88·based distributed microcomputer
processing applications
• Meets the Intel MULTIBUS® Inter·
processor Protocol (MIP) standard for
reliable process· to· process message
transfers
• Supports variable· length message
transfers, up to 64K bytes, between
MULTIBUS® devices
• Supports iSBC™ 550 Ethernet* Com·
munications Controller with an iRMX™
110 system driver interface
The iMMX 800 MULTIBUS Message Exchange Software implements the MIP standard proces~-to-process
message transfer protocol for loosely-coupled multiprocessing on the MULTI BUS bus. The iMMX 800 software reliably transfers a message, using shared memory, between processes based on iRMX 80, iRMX 88
Executives or the iRMX 86 Operating System residing on different iSBC board products (iSBC 80/24, iSBC
80/30, iSBC 86/05, iSBC 86/12A, iSBC 88/25, iSBC 88/40, iSBC 544, iSBC 550, iSBC 569.boards and compatible customer-designed products). The iMMX software provides a standard, easy-to-use system call to implement multiprocessing solutions for greater total application throughput; functions can be assigned to
separate iSBC microcomputers, yet the communication and sharing of data remains straight-forward. New
functions can be added to an existing system using the standard iMMX routine, thereby extending the
useful life of a system.
Figure 1. iMMX 800 Real-Time Executive Interface
The following are trademarks of Inte\ Corporation and may be used only to describe Intel products: Intel, CREDIT, Index, Insite, Intellec, Library Manager, Megachassls,
Micromap, MULTIBUS, PROMPT, UPI, /tScope, Prom ware, MCS, ICE, iRMX, iSSC, iSaX, MULTIMODULE and ICS. Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
*
ETHERNET is a trademark of Xerox Corp.
© INTEL CORPORATION, 1981
5-6
October, 1981
Order Number: 143875·002
inter
iMMX800
The virtual interface is the application task's access to the iMMX services. Through this interface,
Task A can request connection (CONNECTION-ID)
to an identified Task B. Using the CONNECTIONID for Task B, Task A requests the iMMX memory
manager to transfer a message via that CONNECTlON-ID.
FUNCTIONAL DESCRIPTION
The iMMX 800 MULTIBUS Message Exchange
Software provides the iRMX 80, iRMX 88 Real-Time
Executives and the iRMX 86 Operating System a
standardized, process-to-process communications
protocol. This protocol provides the fundamental
capabilities needed to exchange data between
multiple 8-bit and 16-bit microcomputers residing
on the same MULTIBUS system bus. User-defined
application tasks, on different devices, .can exchange messages in a consistent manner. iMMX
software supports error detection and reporting
such that the user task can take appropriate action
to ensure reliable message transfers.
The logical protocol supportsa message manager
fUnction. The Message Manager prepares the
message for delivery to a specific destination port
based on the connection specified. In addition,
the logical protocol returns status information
about the transfer.
Thephysical protocol i$ totally concerned with the
hardware-related elements of message delivery.
These elements are data flow control, mutual ex:
cJusion mechanics, address recognition and interac.tive signalling requirements.
MULTIBUS®·Based Networking
The iMMX 800 software supports a loosely-coupled
MULTIBUS-based network system. The software
interface is composed of simple, easy-to-use,
modules (see Table 1). By supporting the addressing, data transfer, control, and memory management functions, the software, as shown in Figure
2, divides the operation into three functions; the
virtual interface, the logical protocol, and the
physical protocol.
Four differentinter'device signalling mechanisms
are supported. These asynchronous mechanisms
include MULTIBUS interrupt-mapped, memorymapped (i.e., "flag" bytes), polling, and 1/0 portmapped.
8and 16·Bit Distributed Microcomputing
Table 1_ iMMX 800 Software Memory
Requirements
Executive
iRMXTM 80
iRMXTM 88
iRMXTM 86
The application solution can be a heterogeneous
set of processors and real-time executives as
shown in Figure 1.. The iMMX 800 software pro,
vides a uniform interface to applications Cind
manages a myriad of hardware combinations including multiple-function boards, single-function
boards, master boards, slave boards, dual-port,
K Bytes
3.7
4.5
6.8
DEVICE A
DEVICE B
VIRTUAL
INTERFACE
TASK A
.. S
TASK B
-
410.
iMMX
LOGICAL
~-- PROTOCOL - - - - .
FACILITY
~PHYSICAL~
PROTOCOL
~I
"" ."'r
iMMX
FACILITY
I
~
MUL TIBUS® BUS
-V
Figure 2. Inter-Device Task-to-Task Communications
5-7
AFN-01970B
iMMX800
private or public memory, 8-bit or 16-bit data
transfers, and inter-device interrupt signalling
methods. In particular, programs written to access
8 or 16-bit data through IMMX software can do so
independently of actual data format.
TRANSFER MESSAGE
The Transfer Message service causes messages
to be delivered via the specified CONNECTION-ID.
The competition status on the message's delivery
is returned as a status variable.
iRMX™ Uniform Interface
DEACTIVATE PORT
The iMMX software package provides a uniform interface across all iRMX-based software environments. The iMMX software services are provided
as a set of tasks, system procedures, and interrupt
drivers.
The Deactivate Port service closes an active
system-port. All successive messages sent to that
system-port are returned to the sender.
Support is supplied for the iAPX 86/88-based
microcomputers that support the iRMX 86 Operating System and the iRMX 88 Executive. In addition,
software support is provided for the iRMX 80 Executive for the Intel8085-based products: the iSBC
80/24 and iSBC 80/30 processor boards, and the
iSBC 569 and iSBC 544 intelligent slave boards.
The CONNECTION-ID provided by the initial Find
Port request loses further reference to the system
port. The CONNECTION-ID is no longer usable.
LOSE PORT
Shared Address Space
The iMMX 800 software package provides a memory management service that supports shared
memory address spaces. An application transfers
a message through a locally addressed port. The
iMMX 800 memory manager maps that message,
via a shared memory address, to the receiving
port's same or aliased memory space. The receiving port then accesses the port through local addressing.
Message Transfer Mechanism
The iMMX software operational model is based on
a message-passing model. Based on available
memory space, the maximum message size is 64K
bytes.
Shown in Table 2 are five different services available: Find Port, Activate Port, Transfer Message,
Deactivate Port and Lose Port.
Interprocessor Protocol Architecture
ACTIVATE PORT
The Intel MULTIBUS Interprocessor Protocol (MIP)
specifies an architecture by which processes executing on different MULTIBUS single board computers can communicate with one another in a
reliable, controlled manner within that system. A
system can consist of a heterogeneous set of processors, executing a heterogeneous set of real:
time executives and application software.
The Activate Port service allows a task to receive
messages sent via iMMX software. The application utilizes a convenient virtual-level interface,
and does not have to maintain configurationdependent information.
Based on a simple internal structure, the MIP
specification defines a functional consistency
across several product lines and provides the
means to support efficient operation in multiple
processor environments.
FIND PORT
The Find Port service returns a CONNECTION-ID,
which is used by iMMX 800 software to pass
messages to the destination port.
Table 2. System Calls
Function
FIND PORT
ACTIVATE PORT
Name
CQFIND
CQACTV
TRANSFER MESSAGE
CQXFER
DEACTIVATE PORT
CQDACT
LOSE
CQLOSE
Description
Find the system-port and return a CONNECTION·ID.
Activate a local system-port for receiving messages from other
tasks.
Transfer the message to the system· port identified by the
CONNECTION·ID.
Deactivate an active system-port. Messages addressed to it are
no longer delivered, and are returned to the sender.
Loses the active CONNECTION·ID to a port.
5-8
AFN-01970B
inter
iMMX800
iRMX™ 1/0 System Driver
Since an iRMX-based application may be using the
iRMX I/O System's independent device driver interface, the iMMX 800 software is usable by device
drivers.
'----r--'
An example of maintaining the iRMX-based application interface, the iMMX 800 package provides an iSBC 550 Ethernet Communications Controller device driver. This device driver uses iMMX
800 routines to communicate to the iSBC 550 controller (see Figure 3).
iRMX'M 86
APPLICATION
iRMXT}' 86
' - - - , - _ - ' APPLICATION
ETHERNET
Figure 3. Ethernet Communications
SPECIFICATIONS
INTELLIGENT CONTROLLERS
SINGLE BOARD COMPUTERS
iSBC 544 (Communications)
iSBC 550 (Communications)
iSBC 569 (Digital)
iSBC 80/24
iSBC 80/30
iSBC 86/05
iSBC 86/12A
iSBC 88/25
iSBC 88/40
143808 - iMMX 800 Reference Manual and Users'
Guide
ORDERING INFORMATION
MMX 800 ABY
Single Density ISIS Media. Includes incorporation fee
buyout.
MMX 800 BBY
Double Density ISIS Media. Includes incorporation fee
buyout.
MMX 800 DBY
Single Density iRMX 86 Media.
Includes incorporation fee
buyout.
MMX 800 AWX
Single Density ISIS Media. Update service for an additional
year.
MMX 800 BWX
Double Density ISIS Media.
Update service for an additional year.
iSBC™ Supported Hardware
Reference Manual (Supplied)
Description
The iMMX 800 MULTIBUS Message Exchange
Software is a licensed product that provides users
of Intel Single Board Computers and the iRMX 80,
iRMX 86, and iRMX 88 (Version 1.0) Real-Time Executives software implementing a standardized,
memory-based, task-to-task communication protocol. This protocol provides the capabilities
needed to exchange data between multiple 8-bit
and 16-bit microcomputers residing on the same
MULTIBUS system bus.
Part Number
Description
MMX 800 ARO
Single Density ISIS Media. Requires incorporation fee for
each derivative work.
MMX 800 BRO
Double Density ISIS Media.
Requires incorporation fee for
each derivative work.
MMX 800 DWX
Single Density iRMX 86 Media.
Update service for an additional year.
MMX 800 DRO
Single Density iRMX 86 Media.
Requires incorporation fee for
each derivative work.
MMX 800 LST
Human readable source
listings for the iMMX 800 software modules.
5-9
iRMX 86™
OPERATING SYSTEM
• Structured multiple application
environment
• Complete bootstrap and application
loaders
• Object-oriented architecture
• Powerful error management
• (P)ROM .or RAM based
• Comprehensive I/O system
• User configurable and extensible
• Extensive human interface
• Real-Time priority-oriented scheduler
• Interactive system debugger
The Intel iRMX 86 Operating System is an easy to use, comprehensive multiprogramming software
system for Intel iSBC 86 and 88 Single Board Computers and other iAPX 86 and iAPX 88-based microcomputers. The iRMX 86 Operating System extends the architecture of the underlying processor by providing
a collection of new operations that act on the Operating System objects provided by the system or user
created extensions. The multiprogramming environment of the iRMX 86 Operating System, based on a
real time, event-driven scheduler, provides an efficient foundation for applications including process control, intelligent terminals, office systems, data communications and medical electronics.
Each layer of the operating system simplifies user access to the underlying hardware by taking advantage
of the mechanisms provided by the layers below. Each layer of the iRMX 86 Operating System is configurable to allow applications to customize the system to particular needs.
iRMX 86™ Operating System Layers
The following are trademarks of Intel Corporation and may be used to describe Intel products: CREDIT, Index, Intel, In site, Intell~c, Library Manager, Megachassis, Micromap,
MULTIBUS, PROMPT, UPI, ItScope, Promware, ICE, iRMX, iSeC, iSeX, MULTIMODULE and ICS, and the combination of ICE, ISaC, iSaX, iRMX or iCS, and a numerical suffix.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are Implied.
© INTEL CORPORATION, 1981
5-1 0
~f;~~~
inter
iRMX 86™
necessary for any application. It also provides a
mechanism for users to create their own object
definitions and use them as part of the basic
operating system. Each of the outer layers of the
system add to the list of available objects by using
this same extension mechanism.
FUNCTIONAL DESCRIPTION
Services provided by the iRMX 86 Operating
System include facilities for executing programs
concurrently, sharing resources and information,
servicing asynchronous events, and interactively
controlling system resources and utilities. In addition, the iRMX 86 Operating System provides all
major real time facilities including priority-based
system resource allocation, means for concurrently monitoring and controlling multiple external events, real time clock control, interrupt
management, and task dispatching. The iRMX 86
Operating System contains the following
modules: An object-oriented Nucleus; Device Independent Basic and Extended 1/0 Systems; Terminal Handler; Bootstrap and Application
Loaders; Human Interface with complete command line interpreter; and an interactive, objectoriented Debugger.
(P)ROM or RAM Based
The iRMX 86 Operating System can be made resident in (P)ROM or can be loaded into RAM from a
secondary storage device using one of the supplied Loaders. Being able to place all system software in (P)ROM offers three benefits: 1) Systems
may be moved to harsh environments that
preclude the use of disks; 2)The overhead expense of providing mass storage devices can be
eliminated; and 3) System performance can be increased by eliminating the wait states required for
most RAM's, and disk accesses required for most
disk-based operating systems.
Because the modules and services provided by
the operating system are user selectable, application specific operating systemscan be created by
iRMX 86 users. The iRMX 86 Operating System
therefore eliminates the need for custom
operating system design, thereby reducing
development time, cost, effort, and risk.
User Configurable
Users of the i RMX 86 Operating System are able to
use a wide range of features or select only those
which meet the specific requirements of a particular application. Each system call provided by
the operating system may be removed from the
system if it is not used. Each task can specify the
use of the 8087 Numeric Data Processor. Jobs can
be configured with specific running environments. Individual 1/0 port addresses are also configurable, making the system ideal for component
level applications.
FEATURE OVERVIEW
The .iRMX 86 Operating System provides users
with simple, easy-to-use, quality software tools for
creating a wide range of application systems.
Some important features are:
This complete modularity along with many other
user options allows users to configure systems in
a cost-effective manner regardless of the application environment. Each layer of the system may be
configured in this manner, or (with the exception
of the Nucleus) left out of the system altogether.
Structured Application Environment
The iRMX 86 Operating System provides a consistent structure from application to application, and
CPU to CPU, thus allowing experience gained on
one system to be easily transferred to others.
Often entire programs can be ported from one application to another.
Nucleus
The Nucleus of the iRMX 86 Operating System
provides the foundation upon which a variety of
applications systems can be built. It includes the
facilities to manage the basic objects of the
system necessary to perform multiprogramming,
multitasking, critical section management, and
extensive task-to-task communication and
control.
Object·Oriented Architecture
The iRMX 86 Operating System extends the
capability of .the underlying CPU by adding a
number of new data structures (objects) and a
number of functions to operate on these objects.
This architecture provides a simple, symmetric,
and ei:l.sy to learn interface to a comprehensive
system. The Nucleus provides the means to
create, manipulate, and delete the basic objects
Embedded in the Nucleus are the facilities to support concurrent program execution and handling
5-11
AFN·01723B
iRMX 86™
of simultaneous asynchronous events .. These
facilities allow interrupts coming from specialized
peripheral devices to be serviced in an efficient
manner. The iRMX 86 Operating System allows
the CPU hardware to be used by multiple applications, thus reducing the overall system size, complexity, and cost. These facilities are built from
four key concepts:
designated as using the 8087Numeric Data Processor, it also has its own copy of the NDP
registers, stack, and status. Task execution is
based on an event-driven, priority-based
scheduling algorithm.
• JOBS - Permit isolation of application tasks,
objects, and memory to provide.a multiprogramming environment. Jobs encapsulate an
application and limit the degree of interaction
between sets of tasks.
OBJECT MANAGEMENT - Just as floating pOint
numbers are data structures using operators such
as multiply and subtract to operate on them, iRMX
86 objects are data structures with system calls to
manipulate them. Because of the uniform structure of the system, users have a foundation on
which to tailor the Nucleus to the application by
removing system calls not necessary for the application and by adding objects and system calls
customized for the application. The basic objects
of the Nucleus are:
• COMPOSITE OBJECTS - Permit users to
create objects not found in the set of Nucleus
objects. These new objects appear to other
facilities in the iRMX 86 system as if they are
part of the original system. This ,means that
Composite .objects can be manipulated using
the Mailboxes and Object Directories in.exactly
the same manner as other objects.
.
SCHEDULING - The iRMX 86 Nucleus offers a
priority-oriented, event'driven scheduling mechanism that supports up to 255 different priority
levels. The scheduler uses the task priority to
determine which task receives control of the CPU,
and to ensure that the highest priority task ready
to execute is given control of the system. That
task will continue to run until a higher priority interrupt occurs, or until the running task ~equests
resources that are not available. This priority
scheduling ailows the system to be responsive to
the· external environment. while allocating
resources among the application tasks.
• SEGMENTS Store data in dynamically
created RAM buffers with a specified length.
• MAILBOXES - Provide a mechanism for intertask and interprogram object and data transfer.
Mailboxes are locations for objects to be sent
and received. For example, using a mailbox for
intertask communication permits a time-critical
task to forward data to a non-time-critical task
for processing. Mailboxes are generally used to
pass data segments from task to task, although
any object (user or system defined) may be
transferred.
INTERRUPT MANAGEMENT The iRMX 86
Operating System provides two levels of interrupt
management: Interrupt Handlers and Interrupt
Tasks. The first opUmizes response time, the
other optimizes response capabilities. Interrupt
tasks allow use of all iRMX 86 system callsand
mask only lower priority interrupts.· Interrupt
handlers permit direct control over the CPU's interrupt logic and only allow the use of interrupt
system calls. This structure allows users to easily
perform buffering of data while leaving complex
processing of the data to interrupt tasks.
• SEMAPHORES - Manage mutual exclusion
and. synchronization. A semaphore is used to
signal another task when processing has been
completed or when resources are available. A
semaphore provides a low-overhead signalling
mechanism.
• REGIONS - Control access to critical sections
by allowing only one task at any given time to
access a portion of code. Examples are a nonreentrant procedure or code for controllirig a
peripheral device that can only service one request at a time. In addition, regions can be used
to protect .datastructures from being manipulated by more. than one procedure at a time.
For systems requiring more than the 8 interrupt
levels of the master 8259A interrupt controller,the
iRMX 86 Operating Systemallows applications to
configure up to 7 slave 8259A"s. Using the slave
devices, systems can respond in real time to as
many as 57 interriJpt sources ..
• TASKS - Perform the actual work of the.application by executing software modules. Each
task in the system has the characteristics of a
unique processor. It has its own code, priority,
stack, data area, and status. If the task is
ERROR MANAGEMENT -When a task issues an
iRMX 86 system call, the resultsmaynot always
5-12
AFN·01723B
inter
iRMX 861M
be what the task expects to achieve. For example,
the task may request memory that is not available,
or it may use an invalid parameter. The iRMX 86
Operating System may be configured to provide
two levels of comprehensive error. management:
hierarchical error.handling .and selective errorprocessing.
quiring a minimum of design time and effort. Furthermore, the device-independent nature of the
system allows use of different devices without
redesign.
The 1I0System·provides access to three types of
files:
Hierarchical error handling permits a task to
handle various errors at different levels of the
system. Errors common to a number of tasks can
be addressed by system-wide error handlers.
Application-specific errors can b(3 routed to joblevel handlers. In addition, if a task has a need for
a unique error handler, an error handler can be
specified for that task. This flexibility means
global errorhandlers can be created for the majority of the errors, reducing the amount of error
handling software to be written.
• NAMED FILES - allow applications to refer to
collections of bytes (files) by using a name.
These names are catalogeq in directories to
allow file access by different tasks and jobs.
Directories are special named files that store
directory and access information about other
named files and directory files.
• PHYSICAL FILES - provide a mechanism to
make actual physical connections to storage
devices. This type of file is typically used to
communicate with simple devices such as
printers and terminals.
In addition, each application can select the type of
error to be processed by the error handlers. The
errors are divided into two categories: programmer errbrssuch as invalid parameters; and environmental condition errors such as detection of
insufficient memory to meet requirements.
• STREAM FILES - are mechanisms for communicating between tasks and jobs as if the
data were written and then read from a FIFO
file.
The named files may be organized in ahierarchical structure as shown in Figure 1, where the
triangular files are named data files, and the rectangular files represent directories. This hierarchy
allows data to be grouped logically and accessed
with a minimum of overhead.
Terminal Handler
The Terminal Handler supports real time, asynchronous 1/0 between the operator's terminal and
application tasks. It provides a line buffer which
stores ASCII characters as they are input from the
console. Special editing characters are used to
control the terminal and the buffer contents, and
are not entered into the data. The Handler may be
configured as an output·only version to support
those applications not requiring terminal input.
1/0 System
The iRMX 861/0 System provides an extensive
facility for device independent 1/0 through a
series of supplied device drivers, or any number of
user supplied device drivers that can be Gonfigured to operate at any 1/0 port address. The
Basic 1/0 System (BIOS) implements an asynchronous interface to the device drivers allowing
users to explicitly overlap 110 functions with other
operations. The Extended 1/0 System (EIOS) performs all of the synchronization necessary to do
read·ahead and write-behind buffering
automatically, and to reference files with logical
names. By configuring the appropriate interface,
applications can develop an 110 subsystem with
the optimum degree of device control while re-
CJ
6 '
,
=
~:r.E~'lE
,
BATCti BATCH
Figure 1. Example of Named-File Tree
Loaders
The iRMX 86 Operating System contains two
loaders: A Bootstrap Loader capable of loading a
file from mass storage into system RAM; and an
Application Loader available to tasks as 1/0
system calls.
5-13
AFN·01723B
iRMX 86™
The Bootstrap Loader can be configured to load
from a specific device, or to use the first device
that becomes ready after the system has been
started. It can also be configured to load a file
specified by the operator at the system console.
ing, deleting, and renaming files; loading and
starting application programs; formatting a device
volume; and submitting a command file in a batch
mode. The Human Interface also provides some
utilities useful in debugging applications: a debug
command enabling users to start commands via
the system debugger, and a file copying facility
used in conjunction with the iSSC 957A Monitor
to convert MDS files to and from the iRMX 86 file
format.
The Application Loader provides a simple mechanism for loading application code and data files
into the system. It can be used to load absolute
code into a fixed location, or to load relocatable
code into dynamically allocated memory locations. It can also be used to support code overlay
functions.
Interactive System Debugger
Human Interface commands supplied with the
iRMX 86 Operating System include commands to
perform: creating a directory file; creating, copy-
The iRMX 86 Operating System provides a comprehensive tool for interactive software debugging. The Debugger has two capabilities that
greatly simplify the process of debugging a
multitasking system. First, the Debugger allows
users to debug several tasks while the balance of
the application system continues to run in realtime. Second, the Debugger allows programmers
to interactively view and modify system constructs as well as the system RAM and CPU
registers. The debugger is structured to enable
system designers to track system-wide problems
easily. It can also remain in the final application as
a continuous maintenance tool.
SPECIFICATIONS
MULTIMODULETM BOARDS
Human Interface
The Human Interface is the uppermost layer of the
iRMX 86 Operating System. It supports the user by
providing a number of utilities useful in typical applications. It also provides the application programmer with a number of tools to generate
custom utilities using the basic system utilities or
by interfacing directly to the Command Line Interpreter.
iSBX 218
SINGLE BOARD COMPUTERS
Flexible disk controller (when used
with the iSBC 215)
iSBC 337 Numeric data processor
iSBX 351 Serial 1/0 channel
iSBC 88/40
iSBC 86/05
iSBC 86/12A
User iAPX 86 and iAPX 88 Based Systems
iSBCTM Supported Hardware
The iRMX 86 system runs on user designed
boards with the following components:
8253
Programmable Interval Timer
8259A
Programmable Interrupt Controller
8251A
USART (When the Terminal Handler
is configured into the system)
8087
Numeric Data Processor (when NDP
tasks are configured into the system)
MASS STORAGE
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
iSBC
204 Flexible disk controller
206 Hard disk controller
208 Flexible disk controller
215A Winchester disk controller
215B Winchester disk controller
220 SMD disk controller
254 Bubble Memory board
5-14
AFN·017238
iRMX B6™
ORDERING INFORMATION
The ordering options for the iRMX 86 Operating
System are listed below. All options include a full
year of update service. All the options including
the word "KIT" are shipped with a complete set of
manuals, the iSBC 957B system monitor for the
iSBC 86/12A and iSBC 88/40 Single Board Computers, and an iRMX 86 Customer Training Course
credit voucher that is valid for 6 months after the
date of purchase.
Part Number
Description
RMX 86 KIT ARO,
Single and double
and RMX 86 KIT BRO: density OEM license requiring an Incorporation
Fee for each derivative
work
RMX 86 KIT AST,
and RMX 86 KIT BST:
Single and double
density license for one
additional development
site
RMX 86 KIT.ABY,
Single and double
and RMX 86 KIT BBY: density OEM Buy-out
requiring no further
Incorporation Fee
RMX 86 AWX,
and RMX 86 BWX:
Single and double
density update service
for an additional year.
RMX 86 LST:
Source listings provided
on Microfiche.
5-15
iRMX™ 86 LANGUAGES
• Newest technology languages
iRMX 861-ISO PASCAL
iRMX 862-ANS 77 Subset FORTRAN
iRMX 863-lntel PUM 86
• Provide full software development
capability for the OEM's iSBC™ 86/88 or
iAPX™ 86/88 "target" systems
• Programming languages for OEMs to
pass through to system end-users
..
.
• Compilers optimized to increase
application performance and decrease
application size
• All languages generate Intel® Universal
Run-Time Interface (URI) compatible
programs in the Intel Standard Object
Format (OMF)
• Fully compatible .with Intei Intellec®
development system language
.
products
• All implement the REALMATWM standard
for consistent and reliable results
using the iAPX 88/20 or 86/20 Numeric
Data Processors
• iRMX86 utility software, including
MACRO ASSEMBLER,EDIT; LINK,
LOCATE and LIB
• Resident on the iRMX 86 Real-Time
Multiprogramming Operating System
The iRMX 86 Languages provide users of Intel's iAPX 86/88 or iSBC 86/88 microcomputers with full "on'
the-target-system" development capability. This allows OEMs to provide their erid-users with the facility
to make on-the-spot modifications and add additional capability to their applications. All languages generate code which is compatible with Intel's Universal Run-Time Interface. This ensures users that their application system will run on the iRMX 86 or iRMX 88 Operating System using any iSBC 86/88 or iAPX
86/88-based system supporting the Universal Run-Time Interface. The IRMX 86 Languages are fully compatible with Series III Development System-based language products.
,
r------, '---O-=-B-::JE~C=-T------
~
~
SOURCE
CODE
I
OTHER
I
IL.COMPILERS
l
__ , ___ J
I
I
CODE
I
I
UNIVERSAL DEVELOPMENT INTERFACE
(UDI)
r - - - ---,
I CUSTOMER I
I OPERATING :
IL.. ______
SYSTEM ....I
DEVELOPMENT
TARGET &
DEVELOPMENT
TARGET
TARGET
The following are trademarks of Intel Corporation and may be used only to describe Intel products: CREDIT,' Index, Inslte, Intellec, library Manager, Megachassis, Micromap,
REALMATH, MULTIBUS, PROMPT, UPI, ~Scope, Promware, MeS, ICE, iRMX, iSSC, iSaX, MULT1MODULE, les, iAPX and iMMX. Intel Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in an Intel product. No other Circuit patent licenses are implied.
© INTEL CORPORATION, 1981
5-16
June, 1981
143878
inter
iRMXTM 86 LANGUAGES
This allows maximum flexibility in allowing applications to easily move from one processor to
another, and from one operating system to another.
FEATURES AND BENEFITS
Major features of the iRMX 86 Languages and
their benefits include:
All iRMX 86 Languages generate code compatible
with the Intel Object Module Format (OMF) standard. This provides users with the capability to
mix languages on a single application system. In
this way a user can select exactly the right language tool for specific parts of the application
rather than a project as a whole.
Target System Development
OEMs may accomplish application software development on their target application hardware.
This provides the greatest possible utility of the
OEM's application system. Additionally, OEMs
may provide an entirely new dimension in flexibility - reprogrammability of his system by the
end-user.
Intel Series III Development System languages
provide all of the same benefits described, allowing users to develop their software on a system
optimized for program development and then
easily move it to the final system for test, debug
and minor redevelopment.
Since they .are resident on the iRMX 86 Operating
System, the languages allow users to reduce the
learning curve investment necessary for new application systems with only one operating system
to learn.
Full REALMATH Support
New Technology Languages
The iRMX86 Languages support the REALMATH
floating point standard. This allows users of all
iRMX 86 languages to access the iAPX 86/20 or
iAPX 88/20 Numeric Data Processors or iSBC 337
MULTIMODULE™ board. These numeric processors offer over 100 times greater performance
than comparible software-implemented algorithms, and reduce the system memory requirements by at least 16 KB. The REALMATH standard
(proposed IEEE standard) povides universal
consistency in results of numeric computations.
The iRMX 86 Languages provide efficient object
code generation and access to the highest
performance floating pOint package available on
microcomputers.
The iRMX 86 Languages provide OEMs with the
newest programming languages available. iRMX
86 PASCAL is fully compatible with the proposed
ISO language standard. iRMX 86 FORTRAN provides the majority of the ANS 77 FORTRAN language features, including IF-THEN-ELSE, Zero
Case Do-Loops, and Direct Access 1/0. The complex arithmetic capability, the only missing major
feature, will be supplied in a later release.
Efficient Application Code
The iRMX 86 Language products are optimized to
provide a maximum efficiency in object code generation. This provides users with the smallest,
fastest programs which a high-level language can
generate.
Complete Set of Languages and Utilities
The iRMX 86 Languages offer a broad selection of
modern, highly efficient language products and a
complete set of target system software.
Full Language Compatibility
The iRMX 86 Language products are compatible in
three ways. They provide a Universal Run-Time environment for application programs, allow object
modules to be linked together regardless of compiler used, and are fully source and object compatible with the Series III Development System
language products.
iRMX 86 Languages allow you to select the correct language for your application.
•
•
•
•
The Universal Run-Time environment allows users
to create their application software without regard
for which Intel operating system it will run on.
Technical - FORTRAN or PASCAL
Systems Programming - PUM
Commercial - PASCAL
Size Optimized - MACRO ASSEMBLER
All necessary software for development is provided, including EDIT, LINK, LOCATE, and LIB.
5-17
AFN·01974A
inter
iRMXTM 86 LANGUAGES
Software Development Process
<
UNIVERSAL RUN·TIME INTERFACE (UDI)
~
,~----V
LANGUAGE HIGHLIGHTS
iRMX 86 PASCAL (iRMX 861)
The iRMX 86 Languages allow OEMs to choose
from a broad spectrum of specific language features and "on-the-target-system" development
utilities.
The iRMX 86 PASCAL compiler provides a strict
implementation of the proposed ISO language
standard. All source programs are validated by the
compiler to ensure its conformance to the standard. Many extensions to the language are avail-
5-18
AFN-01974A
inter
iRMXTM 86 LANGUAGES
able which allow PASCAL programs to be written
specifically for microcomputers. Features such as
separate module compilation and iAPX 86/20,
88/20 Numeric Data Processor support are a few
of its many. The ISO standard "source evaluator"
can be switched off to accept these extensions.
For more information on iRMX 86 PASCAL features, see the PASCAL 86/88 Software Package
data sheet (121680).
iRMX 86 FORTRAN (iRMX862)
The iRMX86 FORTRAN compiler provides users
total compatibility with existing FORTRAN 66
language-generated code, plus many new language features provided by the FORTRAN 77
language standard. These new features offer
FORTRAN programmers many neW capabilities,
including "IF-THEN-ELSE", random access I/O
and character variables. For a more detailed explanation of iRMX 86 FORTRAN, see the FORTRAN
86/88 Software Package data sheet (400630).
iRMX 86 PUM (iRMX 863)
The iRMX 86 PUM compiler provides users with a
powerful, microcomputer-oriented system pro·
gramming language. The PUM 80 Language was
introduced in 1976 by Irltel. It was the first microcomputer·oriented, blo~k structured, high-level
language available. Since 1976, thousands of
users, shipping over millions of microcomputerbased systems, have generated their system software with PUM 80 and PUM 86.
iRMX 86 PUM 86 is a compatible superset of PUM
80 which offers easy portability of software across
the full range of microcomputers supplied by
Intel. For more information about iRMX 86 PUM,
see the PUM 86/88 Software Package data sheet
(402175).
iRMX 86 Utilities (iRMX 860)
iRMX 86 EDIT
The iRMX 86 EDIT program provides users with a
powerful, sophisticated, line·oriented editing
facility. EDIT delivers a range of capability suitable for novice users as well as advanced capabilities for sophisticated users. Its key features include a macro processor capable of creating and
executing complex strings of commands, which
ease the editing chore, as well as defining blocks
of text which may be included anywhere in the
text file. EDIT offers variable command sourcing,
symbolic line numbering and reference by symbol.
The facilities of EDIT allow users to create, maintain and manipulate extensive libraries of source
code with minimal effort. For more information on
iRMX 86 EDIT, see the EDIT Software Package
data sheet (143883).
iRMX 86 LINK/LOCATE
The iRMX 86 LINK program connects object mod·
ules which have been individually compiled into a
single, relocatable object module. The input
object code may have been produced by any Ob·
ject Module Format-compatible compiler. Output
object modules may be recombined into larger
object modules, allowing work from a large programming staff to be easily integrated into an
application system.
The iRMX 86 LOCATE program maps the relocatable object code into the iAPX 86/88 memory
segments. Modules may be targeted for specific
memory types. For example, those portions of the
application which must be PROM resident can be
mapped directly to the appropriate address range.
Both iRMX 86 LINK and LOCATE provide listings
of resultant memory and symbol maps for easy
reference and simplified debug. For more information on iRMX 86 LINK and LOCATE, see the
8086/8088 Software Development Package data
sheet (9800757·04).
iRMX 86 LIB
The iRMX 86 LIB "Library manager" allows creation and maintenance of object module libraries.
These libraries allow easy collection of related
object code to reduce the overheadof maintaining
many separate modules. Users may create new
libraries, add and delete object modules, as well
as list the contents of the library and their public
symbols. Individual modules within the library will
automatically be included in a total application
system by the iRMX 86 LINK program. For more
information on iRMX 86 LIB, see the 8086/8088
Software Development Package data sheet
(9800757·04).
5-19
AFN-01974A
iRMXTM a6 LANGUAGES
SPECIFICATIONS
Required Software
Required Hardware
iRMX 86 Operating System, version 1.40r later, including BIOS, EIOS, HI (128 KB of memory). An additional 96 KB is required for dynamic work space
for the languages.
Any iAPX 86/88 or iSBC 86/88-based system
capable of running the iRMX 86 Operating System,
version 1.4 or later.
Documentation· Packages
With:
• 96 KB of additional memory for the iRMX 86
Languages and utilities.
• Two iRMX 86-compatible disks (flexible andlor
hard) with one flexible disk required for softdistribution.
• System console device
Package
Optional Hardware
iAPX 86/20, iAPX 88/20 or iSBC337 Numeric Data
Processors for support of the REALMATH standard.
Manual Included
iRMX861
PASCAL 86/88 User's Guide (121539)
iRMX862
FORTRAN 86/88 User's Guide (121539)
iRMX863
PUM 86/88 User's Guide (121636)
iRMX860
-
EDIT User's Guide (143587)
Macro Assembly Language Reference Manual (9800640)
- Software Development Utilities
Manual (980639)
ORDERING INFORMATION
The products listed below require the signing of
an Intel® Master Software License Agreement. All
ORO products below include 1 year of update service.
Ordering
Code
Description
iRMX 86 Utility (EDIT, LINK, LOCATE,
Package
LIB, MACRO ASSEMBLER)
iRMX 86 FORTRAN 86188
iRMX 862 ORO
Single density, iRMX 86
compatible diskettes
iRMX 862 DWX Update service on single
density diskettes
iRMX 860 ORO
Single density, iRMX 86
compati ble diskettes
iRMX 860 DWX Update service on single
density diskettes
iRMX 86 PASCAL 86188
iRMX 86 PLIM 86188
iRMX 861 ORO
iRMX 863 ORO
Single density, iRMX 86
compatible diskettes
iRMX 863 DWX Updateserviceonsingle
density diskettes
Single density, iRMX86
compatible diskettes
iRMX 861DWX Update service on single
density diskettes
5-20
AFN·01974A
iRMX™ 88
REAL·TIME MULTITASKING EXECUTIVE
• Event·driven multitasking executive
software supports iSBC™ 86/05,
86/12A, 88/25, 88/40 or iAPX 86, 88
based applications·
.
• Supports component or iSBC™·based
system generation through Interactive
Configuration Utility
• 1/0 system provides compatible
iRMX™ 86 files and device independent
1/0 interface
• Small,high·performance, PROMable
executive supports high sample rates
• Provides simple, intertask communica·
tions and synchronization
• 1/0 system supports the User Run·time
Interface (URI) for PLlM, PASCAL and
FORTRAN coded application tasks
• Supports the 8087 Numeric
Processor Extension (N PX) for
arithmetic applications
• Memory management of full megabyte
iAPX 86, 88 memory
The iRMX 88 Real-Time Multitasking Executive is a small, event-driven single-user executive system.
Designed for dedicated computer applications using iSBC 86/05, 86/12A, 88/25, 88/40 or iAPX 86, 88
custom products, the modular software package provides real-time application support for PASCAL, FORTRAN, PUM, and assembler coded tasks. Application tasks utilize intertask communications, .asynchronous 110 control, priority-based resource allocation and file support for the iSBC 204, 208, 215,
215/218, and 220 Disk Controllers, and the iSBC 254 Bubble Memory product.
The small, high performance iRMX 88 Executive can be located in EPROM or bootstrapped into RAM
memory. The iRMX 88 Executive offers features that are suitable for performance-critical process control
applications, production test stand units, sophisticated laboratory analysis, instrumentation, specialized
data acquisition systems or monitoring stations. The iRMX 88 design, based upon the iRMX 80 Real-Time
Executive, offers iRMX 80-like interfaces for those 8-bit applications which are upgrading to 16-bit solutions for the 1 Megabyte addressing, expanded application functions, and higher performance data sampling requirements.
USER
APPLICATION
Figure 1. Module Representation
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, CREDIT, Index, Insite, Intellec, Library Manager, Megachassis,
Micromap, MULTIBUS, PROMPT, UP!, p.Scope, Promware, MeS, ICE, iRMX, iSBC, iSBX, MU,LTIMODULE and ieS. Intel Corporation assumes no responsibility,for the use of any
circuitry other than circuitry embodied in an Intel product, No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
5-21
October, 1981
Order Number: 143130-002
iRMX™ 88
ance flexibility since it masks all interrupts and
supports burst-rate data sample gathering. The interrupt task is useful for lower frequency interrupts, masking only lower priority interrupts.
FUNCTIONAL DESCRIPTION
The iRMX 88 Real-Time Multitasking Executive
Software package provides facilities for executing
tasks concurrently, managing resources and servicing asynchronous events to users of Intel's
single board computers and custom iAPX 86,
88-based products. The foundation modules support real-time dedicated computer applications
with priority-based task scheduling, interrupt
dispatching, real-time clock control with 1 ms
resolution, multiple event monitoring and control,
and file services for flexible, hard, Winchester,
SMD disk units and bubble memory devices. The
software package includes the primary modules:
Nucleus, Free Space Manager, Terminal Handler,
1/0 System and Bootstrap Loader. The Interactive
Configuration Utility (ICU) executes on a Series III
Intellec System, or iRMX 86 Operating System
with a Universal Development Interface (UDI).
Small High·Performance Executive
The iRMX 88 Executive software utilizes a simple,
straightforward architecture which minimizes the
memory requirements, as shown in Table 1. In addition, the modules are designed to be totally
EPROM resident for those systems where mass
storage devices cannot be used because of the
danger of contamination.
Real-time microcomputer solutions require the
recognition of interrupts. The performance of the
system is with respect to data samp'le rates. If
there is no activity in progress when an interrupt
occurs, the time to handle that interrupt is dependent on the number of instructions executed, e.g.,
175 microseconds interrupt latency time on an
iSBC 86/12A board. Most real-time solutions have
multiple events occurring and background operations in progress. Seldom does a background task
have critical sections of code which cannot be interrupted.
FEATURE OVERVIEW
Event·Driven Multitasking
The i RMX 88 Executive provides a control software
foundation called a Nucleus. The iRMX 88 Nucleus
provides two major functions: first, the facility for
concurrerit task execution; secondly, the facility
for handling simultaneous asynchronous events.
Intertask Communications
The iRMX 88 Nucleus provides a simple, easy-touse intertask communications mechanism based
upon a message. Messages are transferred between tasks with two basic procedure calls, a send
(ROSEND) and a wait (ROWAIT). Task "A" requests
the Nucleus to ROSEND the pointer to a message
buffer to Task "B" (see Figure 2). The Nucleus controls the message flow by activating the higherpriority Task B, or queuing the message if a lowerpriority Task B is not waiting for the message. The
receiving task does an ROWAIT to get the message pOinter and can now access the data which
may be for synchronization or real-time control
operations.
The structured multitasking environment permits
segmenting of the application tasks. The number
of tasks, managed by the Nucleus, is limited only
by the available 1 Megabyte memory space. The
tasks are prioritized such that the highest-ranked
task is executing, e.g., an alarm event preempts
the lower priority executing task. The Nucleus
supports 255 priority levels.
Since internal or external events (interrupts) occur
randomly, the Nucleus synchronizes the event
with a task. The Nucleus supports either an interrupt service routine or an interrupt task. The interrupt service routine offers high-speed perform-
Table 1. iRMX™ 88 Module Memory Requirements
MODULE
NUCLEUS
TERMINAL
HANDLER
FREE
SPACE
MANAGER
PHYSICAL""
NAMED""
BOOTSTRAP
EPROM"
(K bytes)
3.0
1.3
0.6
20.0
32.0
0.5
1/0 SYSTEM
• amount of code configured in EPROM; all numbers are approximate
•• includes one 3K byte device driver (named file plus physical file is 34.0K bytes)
5-22
AFN·01723B
inter
iRMX™ 88
Numeric Data Processor
TASK ENTRY POINT
TASK A
The iRMX 88 Nucleus fully supports the 8087
Numeric Processor Extension (NPX) functions for
high·speed arithmetic functions of real·time ap·
plications. High·performance numeric processing
applications, which utilize 8',16',32· and 64·bit in·
tegers, 32·, 64· and 80·bit floating point or 18·digit
BCD operations, are accelerated up to 100 times
over a iAPX 86, 88 software solution. The NPX
functions, including trigonometric, logarithmic
and exponential functionals, are essential in
scientific, engineering, navigational or military ap·
plications.
INITIALIZE TASK
•
PERFORM FUNCTION
l.
INITIALIZE OPERATION (ROSENDI
(SEND MESSAGEI
TASK B
TASK ENTRY POINT
WAIT FOR RESPONSE (ROWAITI
INITIALIZE TASK
.
Nucleus Primitives
WAIT FOR MESSAGE (ROWAITI
FROM TASK A
The Nucleus performs other functions as shown in
Table 2, in addition to the message communica·
tions management. Some primitives like CREATE
TASK and DELETE TASK allow dynamic crea·
tion/deletion of tasks during run·time. This
dynamic capability allows the Nucleus tables to
PERFORM FUNCTION
1.
SEND RESPONSE (ROSENDI
TO TASK A
Figure 2. Intertask Communications
Table 2. Nucleus Primitives
NAME
FUNCTION
ACCEPT
Accept a message from specified exchange. Returns message ad·
dress if available, zero otherwise.
CREATE TASK
Create task by building new Task Descriptor based on specified
Static Task Descriptor.
CREATE EXCHANGE
Create exchange at specified RAM address.
DISABLE INTERRUPT
Disable specified interrupt level.
DELETE EXCHANGE
Delete specified exchange.
DELETE TASK
Delete the task specified.
ENABLE INTERRUPT
Initialize message portion of the Interrupt Exchange Descriptor
associated with the specified interrupt level (the first time called
only), and enable specified interrupt level.
END INTERRUPT
Signals specific end·of·interrupt for the specified interrupt exchange
in a user·supplied interrupt service routine.
INTERRUPT SEND
Send an interrupt message to the specified interrupt exchange.
RESUME
Resume a task that has previously been suspended.
SEND
Send the message located at "msg·addr" to the exchange specified
by"exch·addr."
SET INTERRUPT
Set interrupt vector address. An interrupt is to be serviced by. the
user·supplied routine starting at the address, thus bypassing
Nucleus interrupt software.
SUSPEND TASK
Suspend execution of the task specified by the Task Descriptor.
WAIT
Wait at the specified exchange until a message is available or time
limit expires. Return address of system timout message or user
message.
5-23
AFN·01723B
iRMX™88
expand and accommodate,infrequently us~dtasks
which are loaded into memory from ~ mass
sloragedevice."
,
,
files cali be "double buffered" so that the task can
'be processing data in o'ne buffer while the lOS is
filing another.
','
The lOS provides access to two types of files:
• Named Files allow applications to refer to col-,
lections of bytes (files) by using a name. These
names are cataloged in a directory which allows
files to be accessed by different tasks.
• Physical Files allow applications to make a
physical connection to a storage device.
Typically used for simple devices 'such as,
printers, terminals or sequential data logging
where file structures are not necessary.
Interactive System 'Generation
The iRMX 88 Executive is constructed in a
thoroughly modular manner with the full range of
facilities being offered in library, modules, By
selecting the appropriate features and combining
them with the user-written application tasks the
generated system is tailorecj to the application's
requirements ,minimizing memory overhead for
u'nused features.
'
An Interactive Configuration U~ility provides a
query-based tool that configures the i RMX
88-based application. Responding to 'questions
from the ICU utility program executing on a Series
In Intellec Microcomputer Development System or
an iRMX 86-based system, the user quickly tailors
the real-time application system;'
The file types are a compatible subset of the iRMX
86 Basic 1/0 System with a flat (non-hierarchical)
directory.
Bootstrap Loader
The iRMX 88 lOS has a Bootstrap Loader which
loads a file from mass sto~age' into system
memory. The configurable Bootstrap Loader loads
the file ,from a specific device, automatically from
the first-readydevice of a designated device'list,
or accepts the file name from a terminal. Storing
the system sOftware on disk allows easier future
chimges to the application system.
1/0 System
The iRMX 88 1/0 System provides ali extensive
facility for device-independent 110. Through a
series of supplied ,iRMX 86 compatible device
drivers,the'IIO System supports a wide-range of
ISBC peripheral controllers. Custom 'peripheral
controllers are supported through user-written,
device drivers which are integrated with the 110,
System at system configuration time. The deviceindependent nature of the system allows use of
different devices without application redesign.
The I/O System (lOS) procedures manage real-time
file operations supporting both sequential and
random access (see Table 3). The lOS maximizes
system throughput :by"allowing multiple disk
operations to proceed' in parallel. For example,
',::
Run-Time Interface
The iRMX88 Executive provides the User Run-time
.Interface (URI). This URI interface",inaddition to
encompassing the 1/0 System services, provides
additional functionality for tasks. The additional
functionality includes a trap function anp me!T'lory
management routines which provide the run-time
foundation for PASCAL-86,FORTRAN~86; or
, ' PUM-86 coded application tasks.
.
Table 3_ .110 System Services
FUNCTION
SERVICE
Data Transfer
Services
File Connection
Services
.,
Volume Preparation
CLOSE
OPEN
,
READ
SEEK
TRUNCATE
IJI.'RITE
ATIACH
CREATE
CONNECTION STATUS
',.c
:
DELETE
DETACH
'RENAME
"
FORMAT
'
'
Closes a file connection.
Opens a file connection for access.
Reads a number of bytes from a file.
,Seeks to the indicated pOSition.
Truncates a file.
,Vlr,ites a number of bytes to thatfi,le.
Attaches to a file connection.
,creates aJileand returns a file connection.
Returns the file connection status.
Marks the file for deletion.
.Detaches a file connection.
,Renames an existing file.
Forma,ts the disk for files.
AFN'()1723B
inter
iRMX™ 88
MULTIMODULETM BOARDS
SPECIFICATIONS
iSBX 218 Flexible Disk Controller (when used with
the iSBC 215 Controller)
iSBC 337 Numeric Data Processor
iSBX 351 Serial 110 Board
Intellec® System Configuration and
Generation Requirements
Series III Intellec Microcomputer Development
System with UDI support and a minimum of 2
diskette drives.
CUSTOM iAPX 86, 88-BASED SYSTEMS
REQUIREMENTS
iRMXTM~Based
Configuration and
Generation Requirements
8253 or 8254 Programmable Interval Timer
8259A Programmable Interrupt Controller
8251A USART or iSBX 351 board (when the Terminal Handler is configured into the system).
8087 Numeric Processor Extension (when NPX
tasks are configured into the system).
iRMX 86-based system with UDI support and a
minimum of 2 diskette drives.
Supported Hardware
iSBC™ SUPPORTED MICROCOMPUTERS
iSBC 86/05 Board
iSBC 86/12A Board
iSBC 88/25 Board
iSBC 88/40 Board
Reference Manuals (supplied)
143238 - Introduction to the iRMX 80/88 RealTime Multitasking Executives
MASS STORAGE
143241 - iRMX 88 Installation Instructions
iSBC 204 Flexible Diskette Controller
iSBC 208 Flexible Disk Controller
iSBC 215A Winchester Disk Controller
iSBC 215B Winchester Disk Controller
iSBC 220 SMD Disk Controller
iSBC 254 Bubble Memory Board
143232 - iRMX 88 Reference Manual
142603 - iRMX 80/88 Interactive Configuration
User's Guide
142926 - Guide to Writing Device Drivers for the
iRMX 86 and iRMX 88 1/0 Systems
5-25
AFN·01723B
iRMX™88
ORDERING INFORMATION
Part Number Description
Part Number Description
RMX88 ABY
Single Density ISIS media. Includes incorporation fee
buyout.
RMX88 BBY
Double Density ISIS media. Includes incorporation fee
buyout.
RMX 88 DBY
Single Density RMX-86 media.
Includes incorporation fee
buyout.
RMX 88 AWX
One year Single Density ISIS
media update service.
RMX 88 BWX
One year Double Density ISIS
media update service.
RMX 88 DWX
One year Single Density
RMX-88 media update service.
RMX 88 LST
Human readable source listings
for iRMX 88 software.
RMX 88 LWX
Update service for human
readable source listings.
RMX 88 RF
Incorporation fee.
RMX88
RMX 88 ARO
A licensed product which includes Nucleus, Terminal
Handler, Free Space Manager,
and I/O System object modules.
Package also includes UDIcompatible Interactive Configuration Utility program for
system generation and a complete set of manuals. Purchase
price includes an iRMX 88
Customer Training Course
credit.
Single Density ISIS media. Requires derivative work incorporation fee.
RMX88 BRO
Double Density ISIS media. Requires derivative work incorporation .fee.
RMX 88 DRO
Single Density RMX-86 media.
Requires derivative work incorporation fee.
5-26
infel~
iS8C™ 9578
iAPX 86, 88 INTERFACE AND EXECUTION PACKAGE
• Supports target system debugging for
iSBC™ 86/05, 86/12A, 88/25, 88/40 or
iAPX 86, 88·based applications
• Supports the 8087 Numeric Processor
Extension (NPX) functions for high.
speed arithmetic applications
• Interactively extends the Intellec®
development environment to the target
system for code execution and
symbolic displays of results
• Utilizes a parallel or serial connection
between the Intellec® Development
System and the target system
• Supports custom and iRMX™
operating systems with application
access to ISIS·II files
• Provides an applications bootstrap
from iRMX™ 86 and 88 file compatible
peripherals
The Intel iS8C 9578- package contains the necessary hardware, software, cables, terminator packs and
documentation required to interface, through a serial or parallel connection, an iSBC 86/05, 86/12A, 88/25,
88/40 or iAPX 86, 88 target system to an MDS 800, Seriesll or Series III Intellec Microcomputer Development System for full-speed execution and debugging of application software. The iS8C 9578 package supports the OEM's choice of a custom operating system, iRMX 86 Operating System or iRMX 88 Real-Time
Multitasking Executive for the target application system. OEM's may utilize any iRMX 86, 88 supported
target system peripheral for a bootstrap of the application system or have full access to the ISIS-II files of
the Intellec system.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, CREDIT, Index, Insite, IntaJlee"Library Manager, Megachassis,
Mlcromap. MULTIBUS, PROMPT, UPI, IlScope, Promware, MCS, ICE, iRMX, isse, iSBX, MULTI MODULE and iCS. Intel Corporation assumes no responsibility for the use of any
circuitry ather than circuitry embodied In an Intel product. No other circuit patent licenses are implied.
© INTELCOAPOAATION, 1981
5-27
October, 1981
Order Number: 210221·001
iSBC™ 957B
on the target system. Pre-configured EPROM resident monitors are supplied for the iSBC 86/05,
86/12A and 88/40 products. The monitor software
is configurable as to the selection of the communication link, processor. board, numeric processor extension. and the bootstrap loader functions. The OEM would burn the configured
monitor into EPROMs for the target system.
FUNCTIONAL DESCRIPTION
Overview
Extenqing the software development capabilities
of the Intellec Microcomputer Development
System, the iSBC 957B, iAPX 86, 88 Interface and
Execution Package provides a link to executing
and debugging in a target system. The application
software, developed under the Intellec-resident
ISIS-II Operating System, can readily be downloaded to an iSBC 86, 88 Single Board Computer or
a custom iAPX 86, 88 system using the included
monitor and its powerful, interactive debugging
commands via the Intellec console. Programmers
can effectively develop applications to ensure
timely product availability.
The execution command environment (see Table
1) supported by the resident monitor loads object
code into 'memory, executes it at full speed, sets
breakpoints and examines the results. The
monitor selecti~ely ,ex~cutes portions of program
modules based on breakpoints and single stepping requests. The monitor also provides' commands to examine memory; manage memory
movement by block, search for values, compare
contents, and modify its value. Other program
debugging information is provided through the
displaying, examining or modifying of the iAPX 86,
88 registers.
Target System Debugging
The iSBC 957B package includes a communications link and target system resident monitor software for target application debugging. The target
system monitor supports debugging through an
attached CRT or the Intellec System. The Intellec
resident communications software manages the
link (serial or parallel) between the Intellec system
and the target system. The communications software passes the appropriate console-requested
commands to the monitor software. The monitor
software, invoked interactively through the Intellec
system, effectively exercises the object modules
Numeric Data Processor Support
Arithmetic applications utilizing the 8087 Numeric
Processor Extension (NPX) are fully supported by
the iSBC 957B Monitor. In addition to executing
applications with the full NPX performance, programmers may examine and modify the NPX's
registers using decimal and real number format.
Table 1. Monitor Commands
Command
Function
B
Bootstraps an application from the target system's peripheral device.
C
Compares two memory blocks.
0
Displays a memory block's contents.
E
F
Exits the Intellec@ -based (APXLOD) program and returns to the ISIS-II Operating System.
Searches a memory block to find a specified constant.
G
The .GO command transfers execution to the user program.
I
Inputs and displays data obtained from the input port.
L
Loads the Intellec@ object file into memory.
M
Moves the specified memory block,
N
The N command displays an instruction's single step execution.
0
Outputs data to the output port.
P
Prints values of literals.
R
Runs the program after the iAPX 86, 88 object file is loaded.
S
Substitutes the input value for the memory location.
T
Transfers a block of memory to an Intellec@ file.
X
Allows iAPXTM 86, 88 or NPX registers to be examined or modified.
*
Indicates remainder of the line is a comment.
5-28
AFN·02072A
iSBC™ 957B
The programmer feels confident that correct and
meaningful numbers are entered for the application without having to encode and decode complex real, integer, and BCD hexadecimal formats.
data transfer and command requests, occurs over
this line.
As shown in Figure 1, the connection to the target
iSBC 86/12A system is accomplished with the
iSBC 86/12A serial port through an RS232C serial
line interconnected to Serial port 1 of an Intellec
Series II Model 220 or Model 230 or the CRT port of
an Intellec 800 Development System. In some
target iSBC application systems, the serial 110 port
may not be available for debugging. The example
connection, shown in Figure 2, shows how the
parallel port of the iSBC 86/12A board is connected through the parallel cable to the UPP port
of the Intellec system.
Easy·To·Use Connection
The physical interface between the Intellec Microcomputer Development System and the target
iAPX 86, 88 system is accomplished with the supplied iSBC 957B cables. The cabling arrangement
is either a serial or parallel line and varies depending on whether the development system is of the
Intellec MDS 800 family or one of the Intellec
Series II or III family. All communication, including
SERIAL 1/0
PORT
INTELLEC"SERIES II
MODE~ 220, 230
iSBC'" 66f12A
Figure 1. Intellec® Series Models 220, 230 Serial Connection
INTELLEC' SERIES II
MODELS 220, 230, 240
iSBC"" 86112A
BOARO
Figure 2. Intellec® Series Models 220, 230, 240 Parallel Connection
5-29
AFN·02072A
iSBC™ 957B
Table 2. Routines for 1515·11 Services Available
to Target System Applications
Application Bootstrap Loader
The bootstrap loader, invoked from a stand-alone
CRT attached to the iSBC product or the Intellec
console, dynamically loads the application system
into the target system's memory from an attached
peripheral through the iRMX 86, 88 compatible
bootstrap loader. This configurable function can
be included with the iSBC 957B monitor and installed in the iAPX 86, 88 target system. The programmer may load application code modules or an
entire system from bubble memory, floppy diskettes, Winchester disks or other iRMX supported
mass storage devices.
Routine
Target System Function
ATTRIB
CI
Changes an ISIS·II file attribute.
Returns a character input from the
console.
Closes an opened ISIS·II file.
Transfers a character for console
output.
Deletes the specified ISIS-II file.
Displays an error message on the
Intellec® console.
Exits to the target system monitor.
Loads target system memory with
ISIS·II object code file.
Opens an ISIS·II file for access.
Reads up to 4096 bytes from an ISIS-II
file to memory.
Renames an ISIS·II disk file.
Seeks to the specified ISIS-II file
location.
Writes up to 4096 bytes from memory
to an ISIS·II file.
CLOSE
CO
DELETE
ERROR
EXIT
LOAD
Application Access to ISIS·II Files
Application programs have read or write access to
the ISIS-II file system from the iAPX 86, 88 target
system through simple, easy-to-use, ISIS-like
routines (as shown in Table 2). The routines are
used by applications running in the target system
to transfer files from the ISIS environment into the
environment of the target system. User written applications, utilizing the target operating system,
can manipulate or store data on the target
system's peripherals.
OPEN
READ
RENAME
SEEK
WRITE
..
SPECIFICATIONS
2. Serial or parallel interface (8251 USART or 8255
Programmable Peripheral Interface)
Intellec® Configuration Environment
3. iSBC 86, 88-based single board computer or
custom iAPX 86, 88-based board
The Intellec Microcomputer Development System
is utilized for application program development
and requires the following to support the iSBC
957B package:
Hardware
SUPPORTED iSBC™ MICROCOMPUTERS
1. 64K bytes RAM
iSBC 86/05 Single Board Computer
iSBC 86/12A Single Board Computer
iSBC 88/25 Single Board Computer
iSBC 88/40 Single Board Computer
iSBC 337 Numeric Data Processor
2. Double density diskette or single density diskette subsystem
3. ISIS-II Operating System and associated
language translators
Data Transfer Rates
Intellec®
System Family
MDS·800
Series II, III
Serial
K Bytes/min
37
37
SUPPORTED iSBC™ PERIPHERAL
CONTROLLERS
Parallel
K Bytes/min
96
29
iSBC 204 Flexible Diskette Controller
iSBC 215 Winchester Disk Controller
iSBC 220 SDM Disk Controller
iSBC 254 Bubble Memory Board
iAPX 86,88 Target System Environment
SUPPORTED iSBX™ MUL TIMODULE™ BOARDS
Supporting the iAPX 86, 88-based final product
configuration, the iSBC 957B software package requires:
iSBX 218 Flexible Disk Controller (when mounted
on an iSBC 215 controller)
iSBX 350 Parallel 110 MULTIMODULE Board
iSBX 351 Serial 110 MULTI MODULE Board
1. iSBC 957B cable and EPROMmed monitor
5-30
AFN·02072A
intel'
iSBC™ 957B
iSBC™ 957B Package Contents (Supplied)
INTERFACE AND EXECUTION SOFTWARE
DISKETTES
CABLES
1 - Single density, ISIS compatible
1 - Serial 1/0 port of iSBC or iAPX 86, 88 compat·
ible product to male RS232C connector
1 - Intellec System RS232C port to female RS232C
connector
1 - Double density, ISIS compatible
SYSTEM MONITOR EPROMs
1 - Parallel load cable to mate between Intellec
System UPP port and parallel 110 port on iSBC
or iAPX 86, 88 compatible product
Microcomputer
ISBCTM 86/05,
86/12A
PARALLEL INTERFACE ADAPTER
iSBCTM 88/40
1 - Parallel port status adapter for iSBC products
using parallel cable
Address
RAM
ROM
OOOOOH·
007FFH
FCOOOH·
FFFFFH
OOOOOH·
006FFH
FDOOOH·
FFFFFH*
• Allows 2816 E2PROM to be used at
Supports
NPX
Yes
No
FCOOOH
I/O DRIVER AND TERMINATORS
Reference Manual (Supplied)
4 -iSBC901 - 2200hm/330 ohm terminator packs
4 - iSBC 902 - 1K ohm terminator packs
4 - 7437 line driver packs
143979·002 - User's Guide for the ISBC 957B,
iAPX 86, 88 Interface and Execution Package
ORDERING INFORMATION
Part Number Description
SBC 957B
Intellec to iAPX 86, 88 Interface
and Execution Package including
software, cables and EPROMs.
5-31
AFN·02072A
iOSP™ 86
iAPX 86/30 AND iAPX88/30 SUPPORT PACKAGE
• Development and run·time support for
iAPX 86/30 and 88/30 Operating
System Processors
• Compatible with Intel®PL/M 86/88,
PASCAL 86/88, FORTRAN 86/88, and
iAPX 86/88 ASSEMBLER
• Total iRMX™ 86 Operating System
software compatibility
• Supports (P)ROMor RAM based
system
• Extendable with iRMXTM 86 Operating
System calls
• Complete system initializaUonaids
• Complete system configuration aids
The Intel iOSP 86 Support Package for the iAPX 86/30 and 88/30 Operating System Processors contains a
comprehensive set of easy-to-use tools necessary to develop (P)ROM or RAM-based applications that use
the 80130 Operating System Firmware component. All O'f the system initialization and run-time facilities
are provided in libraries that may. be configured to specific requirements, and linked to application programs written in either iAPX 86 or iAPX 88 Assembler or a high level programming language such as
PASCAL 86 and PUM 86. The iOSP 86 Package provides users with the basic initialization and interface
routines needed to build application software based on the fundamental operating system functions of the
iAPX 86/30 and 88/30 Operating System Processors. The iOSP86 Package also enables users to add higher
level I/O functions from the fully compatible iRMX 86 Operating System, or to form custom, .real-time
systems.
The following are trademarks of Intel Corporatlon and may be used only to describe Intel products: Intel, CREDIT, Index, Insite, Intellec, Library Manager, Megachassis,
Micromap, MULTIBUS, PROMPT, UPI, l4$cope, Promware, MCS, ICE, iRMX, iSSe, iSBX, MULTIMODULE, iO$Pand iCS. Intel Corporation assumes no responsibility forthe use of
any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
5-32
October, 1981
Order Number: 210236·001
inter
iOSP™ 86
itialization routines. They also form a simple interface between application software and the
operating system primitives of the 80130 OSF
component. The various configuration options include:
FUNCTIONAL DESCRIPTION
The iAPX 86/30 and iAPX 88/30 Operating System
Processors (OSPs) provide an easy-to-use foundation on which many real-time applications may be
built. They provide the functions and system support needed to implement both simple and complex applications that require multiple tasks to run
concurrently (see Figure 1). These services are
made possible by the addition of the five new data
types integrated into the 80130 Operating System
Firmware (OSF) component. The 80130 OSF extends the basic data types of the CPU (integer,
byte, character, etc.) by adding new system data
types (JOB's, TASK's, MAILBOX's, SEGMENT's,
and REGION's), and extensive timer, interrupt,
memory, and error management designed to give
real-time response to multitasking and multiprogramming applications. As shown in the second half of the figure, other operating system functions such as mass storage 1/0 services and an
easy-to-use Human Interface can be added easily,
by using modules from the complete operating
system services of the iRMX 86 Operating System.
The iOSP 86 Support Package provides both an interface between application software and the
Operating System Processors, and development
tools designed to make the implementation and
initialization of real-time, multitasking systems
much simpler.
Memory and 1/0 Addressing
The 80130 OSF requires a 16K byte block of
memory address space to be reserved for accessing
internal functions. The iOSP 86 Support Package
is used to specify the base address of the 80130
and the beginning of the initialization routines.
All Interrupt and Timer management of the OSF is
controlled via a reserved 16-byte 1/0 address block
that may be selected by the user. In addition, from
1 to 7 slave 8259A interrupt controllers can be
specified in order to provide the system with up to
57 priority interrupt sources. The OSF baud rate
generator may also be configured to support an
optional terminal interface.
Extending the 80130 OSF
The 80130 OSF allows users to add their own
operating system extensions. These extensions
may take advantage of the detailed and efficient
intertask communication and synchronization
primitives already provided by the 80130, andlor
may utilize custom functions tailored to specific
applications. The Support Package also enables
users to extend the OSF with the extensive services of Intel's iRMX86 Operating System, thereby
allowing applications to grow without having to
change or alter application software already written, or having to write other operating system software. Use of the 80130 with the iRMX 86 Operating
system greatly reduces the amount of memory
needed for the iRMX 86 Nucleus layer, and enables
applications to take advantage of the increased
The iOSP 86 Support Package provides system
developers with the configuration options necessary to tailor the iAPX 86/30 and 88/30 Operating
System Processors to custom applications. Using
the Linking and Locating ·facilities of either an
Intel Intellec Development System, or a suitably
equipped iRMX 86 system, the interface libraries
provided in the package can be added to application software modules to form easy-to-use in-
COMPLEX
APPLICATION SOFTWARE
COMPILERS
MULTITASKING, REAL·TIME
APPLICATION SOFTWARE
HUMAN INTERFACE
EIOS
BASIC 1/0 SYSTEM
iRMXTI,I 86 NUCLEUS
iOSpu , 86 INTERFACE LIBRARIES
8087
(OPTIONAL)
I
8086
OR
8088
I
IOSpn. 86 INTERFACE LIBRARIES
80130
8087
(OPTIONAL)
I
B086
OR
8088
I
80130
Figure 1. Structure of Typical Systems
5-33
AFN·02085A
in1:er
iOSP™86
performance and reduced size requirements inherentin the iAPX 86130 and 88130 VLSI Operating
System Processors_ As each of the services provided by the 80130 is completely iRMX 86-compatible, applications have an automatic upward path
to support complete filesystems and multiple pro:
cessor environments_
plication JOB's that require initialization when the
system is started. The user may also specify the
configuration of the interrupt system (including
slave 8259A interrupt controllers) and the clock
rate used for system timing .. These choices are
automatically programmed into the various
devices when the system is initialized.
Application Interfaces
Operating System Calls
Two interface libraries are included in. the iOSP 86
Support Package_ The first allows programmers to
write application software modules in the Compact Model of computation supported by Intel's
compilers_ The second. provides an interface to
program segments written in either the Medium or
Large Models_ .
The 80130 OSF performs a total of 35 operating
system primitives all of which are completely compatible- with the equivalent iRMX 86 Operating
System calls. The iOSP 86 Support Package provides user-level interfaces· to these primitives to
enable applications to create, delete, control, and
exchange. the new data types provided by. the
801300SF.ln general, these interfaces allowapplication software to manage all ofthe resources
of an iAPX 86130 or 88130 OSP (and an optional
8087 Numeric Processor .Extension) system via
any of the 35 normal Assembly Language system
calls shown inFigure 2.
.
The interface libraries provide the means of accessing all of the primitives supported by the
Operating System Processors_ With this interface,
and all the memory management primitives of the
OSPs, applications have full access to 1M byte of
memory, and ali of the addressing modes of the
CPU.
Required Development Hardware
The iAPX 86130 and 88130 OSPs allow applications
to take full advantage of the Compact, Medium,
and Large models of computation afforded by the
segment model of the CPU's.
Use of theiOSP 86 Support Package requires an
Intel MDS Development System supporting either
single or double density diskettes, or any iRMX 86
system supporting a standard floppy diskette
drive and the iRMX 860 Assembler, Linker, and
Locator Package. Use of the 80130 requires only a
minimal system including either the iAPX 86130 or
88130 Operating System Processor,and enough
system memory to contain the application programs and approximately 2Kbytes of initialization
and interface software provided in. the iOSP 86
Support Package.
These libraries are fully compatible with object
modules produced by the MACRO.86188
Assembler, and the PASCAL 86188 and FORTRAN
86188 and PLlM86188 Compilers.
Application Initialization
The iOSP 86 Support Package provides for the configuration of the system Root JOB,and all user apJOB GROUP
CALL RO$CREATE$JOB
TASK GROUP
CALL
CALL
CALL
CALL
CALL
CALL
CALL
RO$CREATESTASK
ROSDELETESTASK
RO$SUSPENDSTASK
ROSRESUMESTASK
RO$SLEEP
RO$GET$TASK$TOKENS
RO$SET$PRIORITY
SEGMENT GROUP
CALL ROSCREATE$SEGMENT
CALL ROSDELETE$SEGMENT
MAILBOX GROUP
CALL
CALL
CALL
CALL
RO$CREATE$MAILBOX
RO$DELETE$MAILBOX
RO$SEND$MESSAGE
ROSRECEIVESMESSAGE
REGION GROUP
CALL
CALL
CALL
CALL
CALL
RO$CREATE$REGION
RO$DELETE$REGION
RO$SEND$CONTROL
RO$RECEIVE$CONTROL
RO$ACCEPT$CONTROL
DELETION CONTROL GROUP
CALL RO$DISABLE$DELETION
CALL RO$ENABLE$DELETION
INTERRUPT MANAGEMENT GROUP
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
RO$SET$OS$EXTENSION
RO$SET$INTERRUPT
RO$ENTER$INTERRUPT
ROSEXITSINTERRUPT
RO$WAIT$INTERRUPT
RO$SIGNAL$INTERRUPT
RO$RESET$INTERRUPT
ROSENABLE
RO$DISABLE
RO$GETSLEVEL
ERROR CONTROL GROUP
CALL
CALL
CALL
CALL
RO$SET$EXCEPTION
ROSSIGNAL$EXCEPTION
RO$GETSEXCEPTION
RO$GETSTYPE
Figure 2. Operating System Primitives
5-34
AFN·02085A
inter
iOSp™ 86
ORDERING INFORMATION
Part Number
Description
Each of the ordering options listed below include
all the necessary initialization and interface procedures needed to use the iAPX 86/30 and iAPX
88/30 Operating System Processors. Purchase of
the iOSP 86 Package requires verification of an
Intel Master Software License. Each package also
includes an iOSP 86 User's Manual (Document
Number 143331), and a one-year update service.
OSP 86 A
iOSP 86 Support Package contained on an ISIS-II compatible, single density diskette.
OSP 86 B
iOSP 86 Support Package contained on an ISIS-II compatible, double density diskette.
OSP 86 E
iOSP 86 Support Package contained on an iRMX 86 format,
double density diskette.
5-35
Peripheral
Controllers
6
iSBC 204
SINGLE DENSITY FLEXIBLE DISKETTE CONTROLLER
• Full compatibility with iSBC 80, iSBC
86, and iSBC 88 Single Board
Computers
• DMA input/output allows single board
computers to process in parallel with
diskette transfer operations
• Direct compatibility with most singledensity, soft-sectored standard- (8")
and mini-size (5%") flexible diskette
drives
• Programmable track-to-track access,
head-settling, and head-load times
• On-board data separation logic
• Read, write, verify, and search on single
or multiple sectors
• Software supported by iRMX 80,
iRMX 86 and iRMX 88 Real-Time Multitasking Executive disk file system
• Single
+ 5V supply
The Intel iSSC 204 Single Density Flexible Diskette Controller is a single board universal diskette controller capable of
supporting virtually any software-sectored, single density diskette drive_ The standard iSSC 204 Controller can control
two drive surfaces (two single-sided drives or one double-sided drive). With the addition of a second (optional) Intel
8271 component, up to four drives can be supported_ In addition to the standard ISM 3740 formats, the controller supports sector lengths of up to 4096 bytes plus mini-size drive formats_ The iSSC 204's wide range of drive compatibility
is achieved without compromising performance. The operating characteristics (track-to-track access, head-load, and
head-settling times) are specified under user program control. The controller can read, write, verify, and search either
single or multiple sectors.
6-1
AFN·01279A
iSBC 204
FUNCTIONAL DESCRIPTION
Interface Characteristics
Intel's 8271 Floppy Disk Controller (FDG) circuit is the
heart of the iSBC 204 Controller. On-board data separation logic performs standard FM encoding and
decoding, obviating external separation circuitry at the
drive. Diskette data transfers are DMA (direct memory
access) through an on·board Intel 8257 DMA controller
circuit which manages DMA transfers and signals the
master iSBC processor on completion of the transfer. A
block diagram of the iSBC 204 Controller ,is shown in
Figure 1.
Expandability - Each standard iSBC 204 Controller in,cludes a single 8271 FDC circuit capable of supporting
two drive surfaces. Optionally the iSBC 204 may be expanded to support fOUf single·sided (or two doublesided) drives with the insertion of a second 8271 component into an on-board socket.
Simplified Interface - The cables between the iSBC 204
Controller and the drive(s) may be either low cost, "fiat
ribbon cable with mass termination connectors or
twisted pair conductors with individually wired ,connecttors. An on-board, cross-connect matrix allows optional
drive control and status Signals to be connected while
maintaining pin·to-pin compatibility.
Universal Drive and MULTIBUS Compatibility
Because the iSBC 204 Controller has universal drive
compatibility, it can be used to control virtually any
standard- or mini·sized single density diskette drive.
Moreover, the iSBC204 Controller fully supports the
microcomputer industry standard MULTIBUS system
bus and can be used with any single board computer or
system compatible with Intel's bus., Because the iSBC
204 Controller is programmable, its performance is not
compromised by its universal drive compatibility. The
track·to·track access, head·load, and head-settling
characteristics of the selected drive model are program
specified. Data may be organized in a fully compatible
IBM 3740 sector format, in sectors up to 4096 bytes in
length, or in formats compatible with the mini·sized
diskette drives.
'
Programming
The powerful 8271 FDC circuit is capable of executing
high-level commands that simplify system software
development. The device can read, write, and verify'both
single and multiple sectors. CRC characters are'gener·
ated and checked automatically. Up to two tracks on
each surface may be deSignated "bad" and logically
removed from the diskette.
Sector Scanning - Scan commands permit sectors to
be searched for a specified data pattern or "key". During
scan operations the pattern image from memory is continuously compared with a sector or multiple sectors
J1
CON~~~LLER I - - - - r - - - - - - - - I
8257
DMA
CONTROLLER
8271
13
FDC
AO, A1
TO
1
DRIVE
DATO/-DAT71
MULTIBUS
P1
BASE
ADDRESS
DeCODE
J2
8271 '
ADRO/·A0131
FDC
2
(OPTIONAL)
IN~~~~~:T
13
TO
DRIVE
1-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'-_ _-1---1
L-_--I
Figure 1. iSBC 204 Single Density Diskette Controller Block Diagram
6-2
AFN·01279A
iSBC204
read from the diskette. No CPU intervention is required
until a match is found or all specified sectors have been
searched.
mode are specified for the DMA controller. Data
transfers occur in response to commands output by the
CPU.
Program Initiation - All diskette operations are initiated by standard input/output (1/0) port operations
through an iSSC single board computer. System software first initializes the controller with the operating
characteristics of the selected drive. The diskette is
then formatted under program control. For subsequent
transfers, the starting memory address and transfer
Data Transfer - Once a diskette transfer operation has
been initiated, the controller acts as a bus master and
transfers data over the MULTISUS at high speed. No
CPU intervention is required until the transfer is complete as indicated either by the generation of an interrupt on the bus or by examination of a "done" bit by the
CPU.
Equipment Supplied
SPECIFICATIONS
isec 204 Controller
Reference Schematic
Controller-to-drive cabling and connectors are not supplied with the iSSC 204 Controller_ Cables can be
fabricated easily using either flat ribbon cable or
twisted pair conductors with commercially available
connectors as described in the iSSC 204 Hardware
Reference Manual.
Compatibility
CPU - Any iSSC MULTI SUS computer or system mainframe.
Drive - Single density, standard- (8") and mini-sized
(5 1/4 ") diskette drives. The standard iSSC 204 Controller
supports two single-sided drives or one double-sided
drive. Sy adding an (optional) 8271 FDC, four singlesided or two double-sided drives may be supported. The
following drives are known to be compatible:
Optional Equipment
8271 Flexible Diskette Controller Component - Adding
a second 8271 device to the fully tested circuit on the
iSSC 204 Controller allows four drive surfaces to be sup;
ported.
Mini Size
Standard Size
CDC 9404
GSl110
MEMOREX 550
MEMOREX 552 (dual·sided)
SHUGART 800
SHUGART 850 (dual·sided)
WANGCO 76S
PERTEC 650 (SOlDO, OSl. Head)
PERTEC FD200
SHUGART SA400
WANGCO 82
Physical Characteristics
Width - 6.75 in. (17.15 cm)
Height - 0.5 in. (1.27 cm)
Length - 12.0 in. (30.48 cm)
Shipping Weight - 1.75 Ib (0.80 kg)
Mounting - Occupies one slot of iSSC system chassis
or iSSC 604/614 cardcage.
Diskette - Unformatted ISM Diskette 1 (or equivalent
single-sided); unformatted ISM Diskette 2 (or equivalent
double-sided); unformatted Shugart SA 104 Diskette (or
equivalent mini).
Electrical Characteristics
Power Requirements -
Data Organization and Capacity
Temperature - O'C to 55'C (operating); -55°C to
+ 85'C (non-operating)
Humidity - Up to 90% relative humidity without condensation (operating); all conditions without condensation or frost (non-operating)
(Standard Size Drives)
Non-IBM Format
IBM Format
Bytes per sector
128
Sectors per track
26
I
I
256
15
I
I
512
1024
I
2048
I
4096
8
4
I
2
I
1
Tracks per diskette
77
Up to 255
Bytes per diskette
(77 tracks)
256,256
(128·byle sector)
295,680
(256·byte sector)
315,392
(512-byte sector)
315,392
Reference Manuals
9800568 - iSSC 204 Diskette Controller Hardware Reference Manual (NOT SUPPLIED).
9800522 - RMX/80 User's Guide (NOT SUPPLlED)_
Reference manuals 'are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Sowers
Avenue, Santa Clara, California 95051.
Drive Characteristics
Standard Size
Mini Size
Transfer rate (KB/sec)
250
125
Disk speed (RPM)
360
300
1 to 255 ms
in 1 ms steps
2 to 510 ms
in 2 ms steps
o to 255 ms
o to 510 ma
in 1 ms steps
in 2 ms steps
o to 60 ms
o to 120 ms
in 4 ms steps
in 8 ms steps
Track-Ie-track access
(programmable)
Head settling time
(programmable)
Head load time
(programmable)
5.0V (±5%), 2.5A max
Environmental Characteristics
ORDERING INFORMATION
6-3
Part Number
Description
SSC 204
Universal Flexible Diskette
Controller
AFN-01279A
iSBC 208
FLEXIBLE DISK CONTROLLER
• Compatible with all iSBC 80, iSBC 86,
and iSBC 88 Single Board Computers
• Phase lock loop data separator assures
maximum data integrity
• Controls most single and double
density diskette drives
• Read and write on single or multiple
sectors
• On-board iSBX bus for additional
.. Single + 5VSupply
functions
• User-programmable drive parameters
allow wide choice of drives
• Capable of addressing 16M bytes of
system memory
The Intel iSBC 208Flexible Disk Controller isa diskette controller capable of supporting virtually any soft·
sectored, double density or single density diskette drive. The standard controller can control up to four
drives with up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats,
the controller supports sector lengths of up to 8192 bytes. The iSBC 208 board's wide range of drive
compatibility is achieved without compromising performance. The operating characteristics. are specified
under user program control. The controller can read, write, verify, and search either single or multiple
sectors. Additional capability such as parallel or serial 1/0 or special math functions can be placed on the
iSBC 208 board by utilizing the iSBX bus connection.
6·4
AFN-01629A
iSBC 208
Universal Drives and the iSBC 208 .
Controller
FUNCTIONAL DESCRIPTION
Because the iSBC 208 Controller has universal
drive compatibility, iIcan be used to control virtually any standard- or min i-sized diskette drive. Moreover, the iSBC 208 Controller fully supports the
iSBX bus and can be.used with any iSBXmodule
compatible with this bus. Because the iSBC 208
Controller is programmable, its performance is not
compromised by its universal drive compatibility.
The track-to-track access, head-load, and headunload characteristics of the selected drive model
are program specified. Data may be organized in
sectors up to 8192 bytes in length.
Intel's 8272 Floppy Disk Controller (FOG) circuit is
the heart of the iSBC 208 Controller. On-board
data s~paration logic performs standard M FM
(double density) and FM (single density) encoding
and decoding, eliminating the need for external
separation circuitry at the drive. Data transfers
between the controller and memory are managed
by a DMAdevice which completely controls transfers over the MULTIBUS system bus. A block diagram of the iSBC 208 Controller is shown in
Figure 1.
STANDARD DRIVES
(8")
MINI· DRIVES
(5114 ")
D
C
J1
CONNECTOR
ISBX
CONNECTOR
I
ft
i
DATA BUS (8)
I
'---
I
I
1
.
.
I
.z
ADDRESS
BUFFER
~
.
..(
::D
~
(16)
(24)
.A
1 ir
I
(20)
8218
BUS
CONTROLLER
AUX
PORT
TIMING
PLL
SEGMENT
REGISTER
l1
ADDER
~
I
-:J
~
r----
8272
FDC
I--
fr
I
V
~
8237
DMAC
)
'Ii' 1
l
--
J2
CONNECTOR
10
DECODE
DATA
BUFFER
I
(8)
ADDRESS
BUS ..
DATA
BUS
-"
MULTIBUS SYSTEM BUS P1
.
..
Figure 1. iSBC 208 Flexible Disk Controller Block Diagram
6-5
AFN·01629A
iSBC 208
System software first initializes the controller
with the operating characteristics of the selected
drive. The diskette is then formatted under program control. For subsequent transfers, the starting memory address and transfer mode are specified for the DMA controller. Data transfers occur
in response to commands output by the CPU.
Interface· Characteristics
The standard iSBC 208 Controller -includes an
Intel 8272 Floppy Disk Controller chip which supports up to four drives, single or double sided.
SIMPLIFIED INTERFACE-The cabies between
the iSeC 208 Controller and the drive(s) may be low
cost, flat ribbon cable with mass termination connectors. The mechanical interface to the board is
a right·angle header with locking tabs for security
of connection.
Data Transfer-Once a diskette transfer operation
has been initiated, the controller acts as a bus
master and transfers data over the MULTI BUS at
high speed. No CPU intervention is. required until
the transfer is complete as indicated either by the
generation of an interrupt on the bus or by examination of a "done" bit by the CPU.
PROGRAMMING - The power-fIJi 8272 FDC circuit
is capable of executing high-level commands that
simplify system software development. The device
can read and write both single and multiple sectors. CRC characters are generated and checked
automatically. Recording density is selected at
each Read and Write to support the industry standard technique of recording basic media information on Track 0 of Side 0 in single density, and then
switching to double density (if necessary) for
operations on other tracks.
iSBX BUS SUPPORT - One connector is available
on the iSBC 208 board which supports the iSBX
system bus. This connector supports single-byte
transfer as well as higher-speed transfers supervised by the DMA controller. Transfers may take
place in polled or interrupt modes, user-selected.
The presence of the iSBX bus allows many different functions to be added to the board. Serial 110,
parallel 110 and various special-purpose math
functions are only a few of the capabilities available on iSBX MULTIMODULE boards.
Program Initiation-All diskette operations are
initiated by standard inputloutput (110) port operations through an iSBC single board computer.
Equipment Supplied
SPECIFICATIONS
iSBC 208 Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available
connectors as described in the iSBC 208 Hardware Reference Manual
Compatibility
CPU-Any iSBC MULTIBUS computer or system
main frame
Devices-Double or single density standard (8")
and mini (5%") flexible disk drives. The drives
may be single or double sided. Drives known
to be compatible are:
Physical Characteristics
Standard (8")
Caldisk
143M
Remex
RFD 4000
Memorex 550
MFE
700
Siemens FDD 200-8
Shugart
SA 850/800
Perlee
FD650
CDC
9406-3
Mini (51/4 If)
Shugart
Mieropolis
Pertee
Siemens
Tandon
CDC
MPI
Width-6.75 inches (17.15 cm)
Height-0.5 inches (1.27 cm)
Length-12.0 inches (30.48 cm)
Shipping Weight-1.75 pounds (0.80 Kg)
Mounting-Occupies one slot of iSBC system
chassis or iSBC 6041614 CardcagelBackplane.
With an iSBX MULTIMODULE board mounted,
vertical height increases to 1.13 inches (2.87
cm).
450 SA 400
1015-IV
250
200-5
TM·100
9409
51/52/91/92
Diskette-Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted IBM
Diskette 20 (or equivalent double:sided).
Electrical Characteristics
Power Requirements- + 5 VDC@ 3.0A
6-6
AFN·01629A
iSBC 208
Data Organization and Capacity
Standard Size Drives
Double Density
IBM System 34
Single Density
Non-IBM
IBM System 3740
Non-IBM
Bytes per Sector
256
512
1024
2048
4096
8192
128
256
512
1024
2048
4096
Sectors per Track
26
15
8
4
2
1
26
15
8
4
2
1
Tracks per Diskette
77
Bytes per Diskette
(Formatted, per
diskette surface)
512,512
(256 bytes/sector)
591,360
(512 bytes/sector)
630,784
(1024 bytes/sector)
Drive Characteristics
256
256
77
630,784
256,256
(128 byte/sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/sector)
315,392
Standard Size
Mini Size
Double/Single Density
Double/Single Density
62.5/31.25
31.25/15.63
Disk Speed (RPM)
360
300
Step Rate Time
(Programmable)
1 to 16 msec/track in
1 msec increments
2 to 32 msec/track in
2 msec increments
Head Load Time
(Programmable)
2t0254msecin
2 msec increments
4t0508msecin
4 msec increments
Head Unload Time
(Programmable)
16t0240msecin
16 msec increments
32t0480 msec in
32 msec increments
Transfer Rate (K bytes/sec)
Environmental Characteristics
Reference Manual
Temperature-O°C to 55°C (operating); - 55°C to
+ 85°C (non-operating)
Humidity-Up to 90% Relative Humidity without
condensation (operating); all conditions without condensation or frost (non-operating)
143078-001-iSBC 208 Flexible Disk Controller
Hardware Reference Manual (NOT SUPPLIED).
Reference manuaJs may be ordered from any Intel
sales representative, distributor office, or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051.
ORDERING INFORMATION
Part Number
SBC208
Description
Flexible Disk Controller
6-7
AFN·01629A
iSBC™ 215AliSBC™ 215BliSBC™ 215C
WINCHESTER DISK CONTROllER
II
Controls up to four 51fi1", 8" or 14"
Winchester disk drives
II
Over 100MB of storage per controller
II
Two iSBXTMconnectors on-board
II
II
Removable back-up storage available
through the iSB){TM 218Flexible Disk
Controller
Provides ANSI 1226 standard interface
II
Software drivers available for iRMXTM 86
and iRMXTM 88 operating systems
II
Intel® 8089 1/0 Processor provides DMA
channels plus user-programmable
intelligence
II
On-board diagnostics and ECC
II
Full sector buffering on-board
II
Capable of addressing 1 MB of system
memory
The iSBC 215 Winchester Disk C()ntroller wilrenhancethe mass storage capabilities of any iSBC 80, iSBC
88, or iSBC 86-based MULTIBUS system. The controller will interface to industry standard Winchester
disk drives currently available in formatted capacity from 4.5 to 26.7 MB. Recording densities are expected to increase rapidly in the near future and the iSBC 215 controller has been designed .to accommodate these increases.
The iSBC 215 board will control up to four 51/4 ",8" or 14" drives. The iSBC 215Aboard controls open-loop
drives; iSBC.215B board controls closed-loop drives; iSBC 215C board controls ANSI standard 1226
drives.
Two iSBX connectors are provided on the board to interface with the iSBX 218 Flexible Disk Controller,
providing up to 4 MB of removable storage.
Increased computing power made availabie inthe iSBC board products has led to a requirement for larger,
more reliable mass storage subsystems, The Winchester disk controller provides a high capacity, low
cost disk solution that is well matched to single board computer applications.
6-8
AFN.()1793A
iSBCTM 215A/iSBCTM 215B/iSBCTM 215C
FUNCTIONAL DESCRIPTION
iSBX Interface
The software interface and data buffering capabilities used for Winchester drives are also available
for both iSBX MULTIMODULE interfaces. Soft·
ware developed for the iSBC 215 controller can
also be used to transfer data to and from an iSBX·
compatible I/O device.
Programming
Programming the iSBC 215 controller is simplified
by the use of memory-based parameter blocks. A .
linked list technique is used, allowing the user to
perform multiple disk operations.
Full On-Board Buffer
Expanded I/O Capability
The iSBC 215 controller contains enough on-board
RAM for buffering one full data sector. The controller is designed to make use of this buffer in all
transfers. The on-board sector buffer prevents
data overrun errors and allows the iSBC 215 Winchester Disk Controller to occupy any priority slot
on the MULTIBUS.
The iSBC 215 controller allows the user to execute
user-written 8089 programs located in on-board or
MULTIBUS system RAM. Thus the full capability
of the 8089 I/O processor can be utilized for customer I/O requirements.
ECC
High data integrity is provided by on-board Error
Checking Code (ECG) logic. When writing sector
10 or data fields, a 32-bit Fire code, for burst error
correction, is appended to the field by the controller. During a Read operation, the same logic regenerates the ECC polynomial and compares this
second polynomial to the appended ECC. The
ECC logic can detect an erroneous data burst up
to 32 bits in length and using an 8089 algorithm
can correct an erroneous burst up to 11 bits in
length.
i-------------------------l
I
I
I
J3
I
I
I
J4
I
I
I
I
I
I
I
8089
lOP
I
lOP
J1
I
I
I
MULTI BUS'"
BUS
SYSTEM
MEMORY
110 COMMUNICA·
TIONS BLOCKS
Figure 1. Block Diagram of iSBC 21S™ Winchester Disk Controller
6-9
AFN-Q1793A
<:7
inter
iSBCTM 215A/iSBCTM 215B/iSBCTM 215C
DRIVE 0
DATA SEPARATOR
SA1200 OR
DATA EXPRESS'
READIWRITE
CONTROL
READ/WRITE
CONTROL
Isec 215A™
CONTROLLER
INTERFACE WITH SHUGART S'/QUANTUM/RMS DRIVES
INTERFACE WITH MEMOREXISHUGART 14'/CDC/FUJITSU DRIVES
L-_-'~:-_--' CONTROL AND '----~~---'
READ/WRITE
READ/WRITE
CONTROL
INTERFACE WITH PERTEC AND PRIAM DRIVES
• Data Express is a trademark of Rotating Memory Systems Inc.
Figure 2. Controller to Drive Interfacing
6-10
AFN·01793A
intJ
iSBCTM 215A/iSBCTM 215B/iSBCTM 215C
MULTIBUS
REMOVABLE BACKUP
(OPTIONAL)
Isac 215A1215B'"
WINCHESTER DISK CONTROLLER
i~:::~~~===-~:==-~-------------~-~-~
i
CONNECTOR
---- --- ---
ISBX218'"
DOUBLE DENSITY
DISKETTE CONTROLLER
Figure 3. System Configuration (with Optional Diskette Backup)
SPECIFICATIONS
Equipment Supplied
iSSC 215 Winchester Disk Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available
connectors as described in the iSSC 215 Hardware Reference Manual.
Compatibility
CPU - Any iSSC MULTISUS computer or system
mainframe
Disk Drives - Winchester Disk Drives; both openloop and closed-loop head positioner types_ The
following drives are known to be compatible:
Open-Loop (iSBC 215A)
Physical Characteristics
Shugart SA 1000 Series
Shugart SA 4000 Series
Memorex 100 Series
Quantum Q2000 Series
Fujitsu 2301, 2302
CDC 9410
RMS 51/4" Series
Width - 6.75 in. (17.15 cm)
Height - 0.5 in. (1.27 cm)
Length - 12.0 in. (30.48 cm)
Shipping Weight -- 19 oz (54 kg)
Mounting - Occupies one slot of iSSC system
chassis or cardcage/backplane
With an iSSX MULTIMODULE board mounted, vertical height increases to 1.13 in. (2.87 cm).
Closed-Loop (iSBC 215B)
Pertee 08000 Series
Priam 8" and 14" Drive Series
Electrical Characteristics
ANSI (lSBC 215C)
Power Requirements
+ 5 VDC @ 3.25A max
-5 VDC @ 0.15A max1
+ 12 VDC @ 0.15A max2
-12 VDC @ 0.03A max 2
3M 8430 Series
BASF 6170 Series
IMI 7700 Series
Kennedy 7300 Series
Pertee 0800 Series
Priam 8" Series
SLI Cheyenne
Noles:
1. On-board regulator and jumper allows + 12 VDC usage from
MULTIBUS.
2. Required for some iSBX MULTIMODULE boards.
iSBX MULTIMODULE Boards
iSBX 218 Flexible Disk Controller
iSBX 350 Parallel 110
iSBX 351 Serial 110
iSBX 311 Analog Input
iSBX 328 Analog Output
Drives per Controller
5V4" Winchester Disk Drives -
Up to four RMS
drives.
6-11
AFN·01793A
iSBCTM 215A/iSBCTM 215B/iSBCTM 215C
8" Winchester Disk Drives - Up to four ANSI,
Shugart, Pertec, Quantum or Priam drives; up to
two Memorex, CDC, or Fujitsu drives.
14" Winchester Disk Drives - Up to four Priam
drivers; up to two Shugart drives.
Flexible Disk Drives - Up to four .drives through
the optional iSBX 218 Flexible Disk Controller
connected to the iSBC 215 board's iSBX connector.
Humidity - Up to 90% relative humidity without
condensation (operating); all conditions without
condensation or frost (non-operating)
Reference Manual
121593-002,- iSBC 215 Winchester Disk.Controller Hardware Reference Manual (NOT SUPPLIED)
Reference manuals may be ordered from any Intel
sales representative, distributor office, or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051
Environmental Characteristics
Temperature - 0° to 55°C (operating); - 55°C to
+ 85°C (non-operating)
Data Organization and Capacity
Sectors/Track1
Bytes/Sector
Priam 8"
Priam 14"
RMS/Shugart/Quantum
Memorex
Pertec
128
256
512
1024
70
42
23
12
104
62
34
18
54
31
17
9
.64
38
21
11
69
42
24
12
...
Nole 1•. Maximum allowable for corresponding seleclion of bytes per sector.
Formatted Capacity/Drive 2
Bytes/Sector
Shugart
Quantum
Pertec
Priam
Memorex
RMS
128
256
512
1024
7.08MB
8.12
8.91
9.43
7.08MB
8.12
8.91
9..43
12.35 MB
15.03
17.17
17.18
23.29 MB
27.94·
30.62
31.95
7.99 MB
9.49
10.49
10.98
8.40MB
9.65
10.58
11.21
Nole 2. Shugart SA 1004, Quantum Q2010, Priam 3450, Pertec DBOOO, Memorex 101, RMS 512
ORDERING INFORMATION
Part Number
Description
SBC 215A
Winchester Disk Controller
(open'loop)
Winchester Disk Controller
(closed-loop)
Winchester Disk Controller
(ANSI interface)
SBC 215B
SBC 215C
i •. ,
6-12
AFN·01793A
iSBX 218
FLEXIBLE DISK CONTROLLER
• iSBX MULTI MODULE controller
provides flexibility at low cost
• Phase lock loop data separator assures
maximum data .integrity
• Controls most single and double
. density diskette drives
• Read and write on single or multiple
sectors
• User-programmable drive parameters
allow wide choice of drives
• Single +5V supply
The Intel iSBX 218 Flexible Disk Controller is a double-wide iSBX board diskette controller capable of
supporting virtually any soft-sectored, double density or single density diskette drive. The standard
controller can control up to four drives with up to eight surfaces. In addition to the standard IBM 3740
formats and IBM System 34 formats, the controller supports sector lengths of up to 8192 bytes. The iSBX
218 board's wide range of drive compatibility is achieved without compromising performance. The
operating characteristics are specified under user program control. The controller can read, write, verify,
and search either Single or multiple sectors,
6-13
AFN-01867A
iSBX 218
specified. Data may be organized in sectors up
to 8192 bytes in length.
FUNCTIONAL DESCRIPTION
Intel's 8272 Floppy Disk Controller (FDG) chip is
the heart of the iSBX 218 Controller. On-board
data separation logic performs standard MFM
(double density) and FM (single density) encoding
and decoding, eliminating the need for external
separation circuitry at the drive. Data transfers
between the controller and memory are managed
by the intelligent device (usually an Intel 8-bit or
16-bit CPU chip) on the host board. A block
diagram of the iSBX 218 Controller is shown in
Figure 1.
Interface Characteristics
The standard iSBX 218 Controller includes an Intel
8272 Floppy Disk Controller chip which supports
up to four drives, single or double sided.
Universal Drive and iSBX 218 Controller
SIMPLIFIED INTERFACE-The cables between
the iSBX 218 Controller and the drive(s) may be
low cost, flat ribbon cable with mass termination
connectors. The mechanical interface to the
board is a right-angle header with locking tabs for
security of connection.
Because the iSBX 218 Controller has universal
drive compatibility, it can be used to control virtually any standard- or mini-sized diskette drive.
Moreover, the iSBX 218 Controller fully supports
the iSBX bus and can be used with any single
board computer which furnishes this bus.
Because the iSBX 218 Controller is programmable, its performance is not compromised by its
universal drive compatibility. The track-to-track
access, head-load, and head-unload characteristics of the selected drive model are program
PROGRAMMING - The powerful 8272 FOC circuit
is capable of executing high-level commands that
simplify system software development. The device
can read and write both single and multiple sectors, CRC characters are generated and checked
automatically. Recording density is selected at
each Read and Write to support the industry standard technique of recording basic media information on Track 0 of Side 0 in single density, and then
switching to double density (if necessary) for
operations on other tracks.
sv
t
~
REseT
RD
WR
RESET
IORDI
IOWRI
MAO
MINTR1
BUS
MFM MODE
veo
CS
AD
INT
ORa
MeSOI
Isax
DATA WINDOW
MORor
MDACK}
OPTO
DATA
RECOVERY
SYNC
,
RD DATA
PRE-SHIFTD
8272
FOC
OACK
TC
PRE-SHIFT'
CHIP
WDOATA
J
_I
PRE-COMP
FAUL TITRACK 0
FL T RESET/STEP
LOW CURRENT/DIR
DATAIJ..7
.~~
WRITE DATAl
WRITE PROTECTI
TWO-SIDEDI
FAULTI
TRACK 01
WD PROT 12 SIDED
MDOM07
READ DATAl
CIRCUIT
MUX
FLEXIBLE
DISK
DRIVE
FLT RESETI
STEPI
LOW CURRENT I
,
DIRECTION
8MHz
OSC
AtW/SEEK
!
~
READYI
WRITE ENABLEI
INDEXI
HEAD LOAD!
WRITE
CLOCK
SIDE SELECT
051/
US,
US,
GEN
~
0531
{-
MUX
~
Figure 1_ Block Diagram of iSBX 218 Board
6-14
AFN·01867A
iSBX 218
require a data transfer every 13 microseconds
(double density) or 26 microseconds (single density). Most CPUs will operate in a polled mode,
checking controller status and transferring bytes
when the controller is ready. Boards utilizing the
Intel 8080 chip, such as the iSBC 80/10B board,
will be restricted to single density operation with
the iSBX 218 Controller, due to these speed requirements. A programming example illustrating
the iSBC 80/10B handler is contained inthe Hardware Reference Manual.
PROGRAM INITIATION-All diskette operations
are initiated by standard ISBX bus input/output
(I/O) operations through the host iSBC single
board computer. System software first initializes
the controller with the operating characteristics
of the selected drive. The diskette is then format·
ted under program control. Data transfers occur in
response to commands output by the CPU.
DATA TRANSFER-Once a diskette transfer
operation has been initiated, the controller will
SPECIFICATIONS
Diskette-Unformatted IBM. Diskette 1 (or equivalent single-sided media); unformatted IBM
Diskette 2D (or equivalent double-sided).
Compatibility
CPU-Any iSBC single board computer or 1/0
board compatible with the MULTIBUS system
bus and implementing the iSBX bus and connector.
Devices-Double or single density standard (8")
and mini (51/4 ") flexible disk drives. The drives
may be single or double sided. Drives known
to be compatible are:
Equipment Supplied
iSBX 218 Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Gables can be fabricated with flat cable and commercially-available
connectors as described in the iSBX 218 Hardware Reference Manual.
Nylon Mounting Bolts
Physical Characteristics
Standard (8")
Caldisk
143M
Remex
RFD 4000
Memorex 550
MFE
700
Siemens FDD 200·8
Shugart
SA 850/800
Pertec
FD 650
CDC
9406-3
Mini (51/4 ")
Shugart
Micropolis
Pertec
Siemens
Tandon
CDC
MPI
Width-2.85 inches (7.24 cm)
Height-O.S inches (1.27 cm)
Length-7.5 inches (19.05 cm)
Shipping Weight-1 pound (0.46 Kg)
Mounting-Occupies one double-wide iSBX MULTIMODULE position on boards; increases
board height (host plus iSBX board) to 1.13
inches (2.87 cm).
450/400
1015-IV
250
200-5
TM-100
9409
51/52/91/92
Data Organization and Capacity
Standard Size Drives
Single Density
Double Density
IBM System 34
Non-IBM
Non-IBM
IBM System 3740
Bytes per Sector
256
512
1024
2048
4096
8192
128
256
512
1024
2048
4096
Sectors per Track
26
15
8
4
2
1
26
15
8
4
2
1
Tracks per Diskette
77
Bytes per Diskette
(Formatted, per
diskette surface)
512,512
(256 bytes/sector)
591,360
(512 bytes/sector)
630,784
(1024 bytes/sector)
256
630,784
6-15
77
256,256
(128 byte/sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/sector)
256
315,392
AFN-01867A
iSBX 218
Drive Characteristics
Standard Size
Mini Size
Double/Single Density
Double/Single Density
62.5/31.25
31.25/15.63
Disk Speed (RPM)
360
300
Step Rate Time
(Programmable)
1 to 16 msecitrack in
1 msec increments
2 to 32 msecitrack in
2 msec increments
Head Load Time
(Programmable)
2 to 256 msec in
2 msec increments
4 to 512 msec in
4 msec increments
Head Unload Time
(Programmable)
oto 240 msec in
16 msec increments
oto 480 msec in
32 msec increments
Transfer Rate (K bytes/sec)
Electrical Characteristics
Power Requirements-
Reference Manual
+ 5 VDC @ 0.81A
121S83-001-iSBX 218 Flexible Disk Controller
Hardware Reference Manual (NOT SUPPLIED).
Environmental Characteristics
Temperature-O°C to 55°C (operating); - 55°C to
+ 85°C (non-operating).
Humidity-Up to 90% Relative· Humidity without
condensation (operating); all conditions without condensation or frost (non-operati ng).
Reference manuals may be ordered from any Intel
sales representative, distributor office, or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051.
ORDERING INFORMATION
Part Number
SBX218
Description
Flexible Disk Controller
6-16
AFN·Ol867A
inter
iSBC™ 220
SMD DISK CONTROLLER
• Software drivers available for
iRMX™ 86 and iRMX™ 88 operating
systems
• Controls up to four SMD interface
compatible disk drives
• 12 MB to 2.4 GB per controller
• On·board diagnostic and ECC
• Compatible with all iSBC™ 80,
iSBC™ 88, and iSBC™ 86 Single Board
Computers
• Full sector buffering on·board
• Intel® 8089 110 Processor provides two·
high speed DMA channels as well as
controller intelligence
• SMD interface available on 14"
Winchester, CMD, SMD and large
fixed·media drives
• Capable of addressing 1 MB of system
memory
The iSBC 220 SMD Disk Controller brings.very large mass storage capabilities to any iSBC 80, iSBC 88, or
iSBC 86 MULTIBUS system. The controller will interface to any disk drive conforming to the industry standard SMD interface. Using simplified cable connections, up to four drives may be connected to the iSBC
220 Controller Board to give a total maximum capacity of 2.4 gigabytes. The Intel 8089 1/0 Processor simplifies programming through the use of memory-based parameter blocks. A linked list technique allows
the user to perform multiple disk operations.
The following arB trademarks at Intel Corporation and may be used only to describe Intel products~ CREDIT. Index, Intel, Inslte, lntellec, Library Manager, Megachassls,
Micromap, MULTiBUS, PROMPT, UPt, ~Scope, Promware, MeS, ICE, IRMX. ISaC, iSaX, MULTIMODULE and ICS, and the combination of MeS, ICE, iSeC, Isex or ICS, and a
numerical suffix. Intel Corporation assumes no responsibility for the use of any cIrcuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are
Implied.
© INTEL CORPORATION, 1980
AFN-01794A
6-17
November 1980
143283
iSBC 220™
to 32 bits in length and using an 8089 alrogithm
can correct an erroneous burst up to 11 bits in
length.
FUNCTIONAL DESCRIPTION
Full On-Board Buffer
The iSBC 220 SMD Controller contains enough onboard RAM for one full sector buffering. The controller is designed to make use of this buffer in all
transfers. The on-board sector buffer prevents
data overrun errors and allows the iSBC 220 SMD
Controller to occupy any priority slot on the
MULTIBUS.
SMD Interface
High speed, reliable data transfers are a major
benefit of using the SMD interface. A data transfer
rate of 1.2 MB is accomplished by using separate
(radial) differential data line cabling for each drive.
Control signals are daisy-chained from drive to
drive.
ECC
Defective Track Handling
High data integrity is provided by on-board Error
Checking Code (ECC) logic. When writing sector
ID or data fields, a 32-bit Fire code, for burst error
correction, is appended to the field by the controller. During a Read operation, the same logic regenerates the ECC polynomial and compares this
second polynomial to the appended ECC. The
ECC logic can detect an erroneous data burst up
When a track is deemed defective, the host processor reformats the track, giving it a defective
track code and enters the address of the next
available alternate track. When the controller accesses a track previously marked defective, the
controller automatically seeks to the assigned
alternate track. The alternate track seek is totally
automatic and invisible to the user.
,---------- ---- ---- -- --- --l
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~~:
I
I
I
I
I
lOP
MULTIBUS"O
INTERFACE
LOCAL
BUS
INTERFACE
I
I
I
I
MULTIBUS'M
BUS
I
I
I
SYSTEM
MEMORY
\/0 COMMUNICA·
TIONS BLOCKS
I
I
I
I .
I
L _____ ~ ____ ~~~~~~~~~~~ ___________ J
Figure 1. Simplified Block Diagram of iSBC 220™ SMD Disk Controller
6-18
AFN·01794A
inter
iSBC 220™
TERMINATOR
DRIVEO
CONTROL
CABLE
DRIVE 3
DRIVE 2
DRIVE1
READ/WRITE
READ/WRITE
'----'Ce::A"'B.:::LE=-----_ _ _
C~ABLE
,-----I
I
I
I
I
IL ________ _
READ/WRITE
CABLE
READ/WRITE
CABLE
--I
I
,....::;...:.....----=~.....
P2
(NOTUSED)
P1
_
_ _ _ _ _ ~B~O~ONTR~E~ _ _ _ _ _
J
I
I
I
I
I
MULTIBUS™
CONNECTOR
MULTIBUSTIII
Figure 2. Typical Multiple Drive System
Electrical Characteristics
SPECIFICATIONS
Power Requirements
+ 5 VDC @ 3.25A max
-5 VDC @ 0.75A max 1
Compatibility
CPU - Any iSBC MULTIBUS computer or system
mainframe
Disk Drive - Any SMD interface·compatible disk
drive
Note 1: On·board voltage regulator allows optional -12 VDC
usage from MULTI BUS.
Equipment Supplied
Data Organization and Capacity
iSBC 220 SMD Disk Controller
Reference schematic
Bytes per Sector2 - 128 256 521 1024
Sectors per Track 2 - 108 64 35 18
Note 2: Software selectable.
Controller·to·drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially:available
connectors as described in the iSBC 220 SMD
Disk Controller Hardware Reference Manual.
Table 1. Drive Characteristics (Typical)
Physical Characteristics
Width - 6.75 in. (17.15 cm)
Height - 0.5 in. (1.27 cm)
Length - 12.0 in. (30.48 cm)
Shipping Weight - 19 oz (0.54 kg)
Mounting - Occupies one slot of iSBC system
chassis or cardcage/backplane
6-19
Disk (spindle) Speed
3600 rpm
Tracks per Surface
823
Head Positioning
Closed loop servo type, track
following
Access Time
Track to Track
Average
Maximum
Data Transfer Rate
1.2 megabytes/second
Storage Capac ity
12 to 2.4 gigabytes
6 ms
30 ms
55 ms
AFN·01794A
iSBC 220™
Environmental Characteristics
Reference Manual
Temperature - O°C to 55°0 (operating); -55°C.to
121597-001 - iSBC 220 SMD Disk Controller Hardware Reference Manual(NOT SUPPLIED)
+ 85°C (non-operating)
Up to 90% relative humidity without
condensation (operating); all conditions without
condensation or frost (noll-operating)
Humidity -
ORDERING INFORMATION
Part Number
Description
SBC 220
SMD Disk Controller
Reference manuals may be ordered from any Intel
sales representative, distributor office, or ifrom
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051.
iSBX™ 270
VIDEO DISPLAY CONTROLLER
• Complete video display controller on a
dOllble~wide iSBX™ MULTIMODULE™
b~a~
..
.
.
• Keyboard and light pen interface
provided on-board
• 50 Hz or 60Hz frame rate operation
• Interfaces to either black and white or
co.l,or display monitors
• Displays 7 x 9, 5 x 7 or 6 x 8 character
fonts
• Provides cursor control, reverse video,
blinking, underline; highlight and page
or scroll mode
..
• HighJevel software interface via a
pre-programmed 8041A UPI
• Compatible with all 8/16 bit iSBC™
.boards which support the Intel iSBX™
bus
• Interchangeabl~chara~terfonts
available in EPROM
• Graphics capability via pre-defined
graphic character fonts
The iSBX 270 Video. Display Centreller (VDC) is acemplete video. centroller en a standard deuble wide Intel
iSBX MULTIMODULE beard. Providing either black and white (B&W) er eight-celer displays, the iSBX 270
VDC bring~ alphanumeric video. centrol to. the iSBX bus. Any cemputer beard er .system supperting the
Intel iSBX MULTIMODULE bus is compatible with the iSBX 270 VDC, including mest beard and system preducts fr~m Intel. Additienally, the iSBX 270 VDC supperts key beard and light pen 1/0 en-beard; this
simplifies the design ef intelligent terminals.
The iSBX 270 medule allews the user to. add high level video. display capability to. hislher cemputer system
with a minimal cost and effort. Typical applications fer the iSBX 270 VDC include video. displays fer industrial eperater statiens, werd precessing systems,data base management preducts and many ether
uses.
The· following are trademarks ·01 Intel Corporation ·and may be used only to describe Intel products: Intel, CREDIT, Index,' In site. Intellee, Library Manager, Megachassis,
Mlcromap, MULTIBUS, PROMPT, UPI, ¢leope, Promware.,MCS, ICE, iRM~, /SSC,ISaX, MULllMODUlE and les. Intel C~rporatlon assumes no responsibility forthe use of any
Circuitry other than Circuitry embodied in an Intel product. No ot'her circuit patent licenses are Implied:
© INTELCORPORATION,1981
6-21.
October, 1981
Order Number: 210220-001
iSBX™ 270
When operating in the color mode, the iSBX 270
module provides TIL level 75 ohm line drivers for
Red, Green, and Blue Video and sync allowing 8
different colors to be displayed.
FUNCTIONAL DESCRIPTION
iSBX™ Interface
The iSBX 270 VDC interfaces to the Intel iSBX bus
via the 8041A Universal Peripheral Interface (UPI)
Microcomputer. The 8041A, under firmware control, provides communication between the base
board and the iSBX 270 controller circuitry via the
iSBX data and control lines. Data may be displayed
immediately following power up, using default initialization provided by the 8041A UPI. In addition,
eight high·level commands are provided by the
iSBX 270 firmware; these eight commands are
used to alter the default initialization of the controller and determine status. Following initialization, characters are displayed on the CRT by simply writing to the proper 1/0 port.
CompOSite video is not provided onthe iSBX 270
MULTIMODULE board; however, With n1inimal external circuitry, composite video can be added (circuit design available; contact the local Intel Sales
Office for details).
Table 1 lists several CRT vendors compatlbiewlth
the iSBX 270 VDC.
Table 1. CRT's (B&W and Color)l
TYPE
VENDOR
MODEL II
B&W
Ball Brothers
Motorola
TSD
ELSTON
Ball Brothers
lOT
CONRAC
NEC
MITSUBISHI
TIL 120, TV 120, TV 50
M3570
MDC-15
DM30·12BO-51·A04
Nl15·0131
19AC
5711C13
12020H
C·3419
CRT Interface
Color
The iSBX 270 VDC will interface to many B&W and
RGB color display monitors. For B&W monitors,
the iSBX 270 board provides TIL level signals for
video, vertical sync and horizontal sync. Additionally, in B&W, two levels of intensity (normal
and highlight) are supported under program control.
CRT
CONNECTION
lNOTE: This in no way constitutes an endorsement by Intel
Corporation of these companies' products. The com·
panies listed are known to provide prciduciscompatl·
. ., ,
. ble with the Isex 270 board.
LIGHT PEN
INPUT
KEYBOARD· ,
CONNECTION
CONNECTOR
Jl
CONTROL
ADDRESS
BUS
~======~ISBX'.~BUS=========)
Figure 1. iSBX™ 270 VDC Block Diagram
6-22
AFN'()2071A
iSBX™ 270
Figure 2. The iSBX™ 270 VDC Interfaces to a User·Supplied Video CRT, Keyboard and Light Pen
CRT Controller
Table 2 lists several keyboards that interface to
the iSBX 270 VDC.
The CRT Controller performs all timing and data
buffering functions for the CRT. The iSBX 270 VDC
uses the Intel 8275 CRT Controller (for additional
details refer to the 8275 data sheet available from
Intel).
Table 2. Keyboards'
VENDOR
Advanced Input Devices
Cherry
Cherry
Chomerics
Cortron
Keytronic
Keytronic
Keytronic
Keytronic
Microswitch
Microswitch
Screen Refresh
The iSBX 270 VDC contains 4K bytes of high speed
static RAM, as well as a high speed DMA con·
troller (8237A). The 8237A, under the control of the
8041A UPI, takes care of both writing data to the
screen and refreshing the screen.
Character Generation
MODELl
8K·067
B70·05AB
CB80·07AA
AN26109/AE26203
35·500014
L1648
L1660
L1674·03
L1752
66806·7
878030·8
'NOTE: This in no way constitutes an endorsement by Intel
Corporation of these companies' products. The com·
panies listed are known to provide products compati·
ble with the iSBX 270 board.
The character fonts (128 characters, including
alphabetic, numeric, and special characters) that
are displayed on the CRT are stored in EPROM.
The need may arise to display different character
fonts, i.e., those used in international systems or
custom symbols which are application specific.
With the iSBX 270 VDC the user may modify any or
all of the character fonts by simply reprogramming
the EPROM. In addition, the user may utilize a
larger EPROM to obtain up to 256 characters.
Light Pen Interface
Light pen I/O devices may be directly interfaced to
the iSBX 270 VDC. A light pen hit is triggered on
the rising edge of the light pen signal and is in·
dicated by a status bit in the UPI 8041A and/or an
interrupt.
Table 3 lists a light pen vendor whose product in·
terfaces to the iSBX 270 VDC.
Keyboard Interface
The iSBX 270 VDC also interfaces to a keyboard
I/O device via the J1 edge connector. The keyboard
interface of the iSBX 270 VDC accepts up to eight
TTL parallel data lines and one TTL strobe, either
positive or negative. Keyboard input is indicated
by a status bit in the 8041A and/or an interrupt. In
addition, control lines are provided for visual
and/or audible indicators.
Table. 3.. Light Pens '
VENDOR
MODELl
Information Control Co.
Lp·700
'NOTE: This in no way constitutes an endorsement by Intel
Corporation of this company's products. The company
listed is known to provide products compatible with
the iSBX 270 board.
6-23
AFN·0207'A
iSBXTM 270
SPECIFICATIONS
Physical Characteristics
Controller Characteristics
Width - 3.08 inches (7.82 cm)
Height - 0.8 inches (2.05 cm)
DISPLAY
Length - 7.5 inches (19.05 cm)
Programmable to a maximum of 35 rows x 80 columns of characters_
Shipping Weight - 0.5 pounds (0.175 Kg)
Mounting ...,. Occupies one double-wide iSBX
MULTIMODULE position on boards; increases
board height (host plus iSBX board) to 1.14 inches
(2.90 cm).
CRT OUTPUTS
B&W - TIL level HSYNC, VSYNC, Video_
Color - TIL level, 75 ohm line drivers for RGB and
combined sync provide 8 different display colors.
Electrical Characteristics
FRAME RATE
Power Requirements
+ 5 Vdc
@
1.3A.
50 Hz or60 Hz via jumper settings (non-interlaced).
Environmental Characteristics
CHARACTER FONTS
Temperature - O°C to 55°C (operating); - 55°C to
+ 85°C (non-operating).
5 x 7, 7 x 9 or 6 x 8 jumperable with appropriate
crystal. Character generator uses 2716 EPROM.
Also compatible with 2732A EPROM's. For generation of special fonts, please refer to iSBX 270 VDC
Hardware Reference Manual.
Humidity - Up to 90% relative humidity without
condensation (operating); all conditions without
condensation or frost (non-operating).
Equipment Supplied
VIDEO CONTROL
Reverse video, blinking, underline, highlight, cursor control and page or scroll mode.
iSBX 270 VDC Controller
Reference Schematic
TV MONITOR
Cabling and connectors from the VDCcontroiler
to the CRT, keyboard and light pen are not supplied with the controller. Cables can be fabricated
with commercially available cable and connectors
as described in the iSBX 270. Hardware Reference
Manual.
Most video display monitors with a 10 MHz bandwidth or better.
LIGHT PEN INPUT
TIL level pulse, maximum 50 ns rise time, minimum 100 ns hold time.
Reference Manual
Compatibility
143444-001 - iSBX 270 Video Display Controller
Hardware Reference Manual (NOT SUPPLIED).
CPU
Reference manuals may be ordered from any Intel
sales representative, distributor office or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051:
Any iSBC single board computer or 110 board compatible with the MULTIBUS system bus and implementing the iSBX bus and connector.
ORDERING INFORMATION
Part Number
Description
SBX 270
Video Display Controller
MULTIMODULE Board
6-24
Memory Expansion
Boards
7
iSBCTM 012B
RAM MEMORY BOARDS
• iSBC 86, iSBC 88 and iSBC 80 board
RAM expansion through direct
MULTIBUS® interface
• Assignable anywhere within a 16
megabyte address space
• Jumper selectable base address on any
16K byte boundary'
• 512K of read/write memory
• On·board parity generator/checker and
error status register
• Auxiliary power bus and memory pro·
tect control logic for battery backup
RAM requirements "
• Requires a single + 5 volt power supply
The iSBC012B RAM memory board is a member of Intel's complete line of iSBC memory and 110 expansion
boards. The board interfaces directly to any iSBC 86, iSBC 88 or iSBC 80 Single Board Computer via the
MULTIBUS interface to expand system RAM capacity. The iSBC 012B board contains 512K bytes of
readlwrite memory implemented using dynamic RAM components. An on-board dynamic RAM controller
refreshes a portion of these components every 16 microseconds. Each refresh cycle utilizes memory for
550 nanoseconds (maximum).
The iSBC 012B board generates byte oriented parity during all write operations and performs parity checking
during all read operations. When a parity error is detected, the board can generate an interrupt on the
MULTIBUS interface. In addition, the row and bank of the RAM array containing the error are stored in a Parity
Flag Register. This register is accessible as a MULTIBUS 110 port. An on-board LED also provides a visual indication that a parity error has occurred.
The following are trademarks of Intel Corporation and may be used to describe Intel products: CREDIT, Index, Inslte, Intellee, Library Manager, Megacpassis, Micromap,
MULTIBUS, PROMPT, UPI, pScope, Promware, MeS, ICE, iAMX, iSSe, iSBX, MULTIMODULE, les, iAPX and iMMX. Intel Corporation assumes no responsibility-forthe useaf any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
7-1
July. 1981
143876
inter
iSBCTM 012B
SPECIFICATIONS
this auxiliary RAM power bus is made via jumpers
on the board.
Word Size
Memory Protect
8 bits and 16 bits
Memory Size
524,288 bytes (iSBC 012B)
Access Time
330 nsec (worst case)
300 nsec (typical)
Physical Characteristics
Cycle Times (Worst Case)
Read - 500 ns max.
Write - 500 ns max.
Refresh - 550 ns max.
Width - 12.00 in. (30.4B cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 14 oz. (397 gm)
. Electrical Characteristics
Interface
All address, data and command signals are TTL
compatible.
.
..
Address Selectic:m
Memory ..,.. Base address is jumper selectable on
any 16K byte boundary in a 16 megabyte address
space. On·board RAM cannot cross a 4 megabyte
address boundary.
Parity Flag Register;'" The I/O address of the Parity
Flag Register is jumper selectable to be between
OOH to OFH or 40H to 4FH.
Connector
Edge connector- 86 pin double·sided PC edge
connector with 0.156 in. contact.centers.
Mating connector equivalent.
Viking 3KH43/9AMK12 or
Auxiliary Power
An auxiliary power bus is provided to allow
separate powerto RAM array for systems requiring
battery backup of read/write memory, Selecti.on of
ORDERING INFORMATION
Part Number Description
SBC 012B
An active·low TTL compatible memory protect
signal is brought out on the auxiliary connector
which, when asserted, disables read/write access
to RAM on the board. This input is provided for the
protection of RAM contents during system power·
down sequences.
512K-Byte RAM Board with Parity
D.C. POWER REQUIREMENTS
All Gonfigurations·require only
+5 volts ± 5%.
Normal System Operation (max.)
4.8A (worst case)
3.46A (typical) .
Auxiliary Power No RAM Access (max.)
1.35A (worst case)
O.BBA (typical)
Environmental Characteristics
+ 55°C
Operating Temperature - O°C to
Relative Humidity tion)
to 90% (without condensa·
Reference Manual
143865·001 - iSBC 056B/012B Hardware Refer·
ence Manual (not supplied)
Manuals may be ordered from any Intel sales
representative, distributor office, or· from Intel
Literature Dept., 3065 Bowers Avenue, Santa Clara,
California 95051.
iSBCTM 016A/032A/064A/028A/056A
RAM MEMORY BOARDS
• iSBC 86, iSBC 88 and iSBC 80 board
RAM expansion through direct
MULTIBUS® interface
• Assignable anywhere within a 16
megabyte address space
• 16K, 32K, 64K, 128K or 256K bytes of
read/write memory
• Jumper selectable base address on any
4K byte boundary
• On-board parity generator/checker and
error status register
• Requires a single
• Auxiliary power bus and memory
protect control logic for battery backup
RAM requirements
+ 5 volt power supply
The iSBC 016A, iSBC 032A, iSBC 064A, iSBC 028A and iSBC 056A RAM memory boards are members of Intel's complete line of iSBC memory and I/O expansion boards. Each board interfaces directly to any iSBC
80, iSBC 88 or iSBC 86 Single Board Computer via the MULTIBUS interface to expand system RAM capacity. The iSBC 016A, iSBC 032A, iSBC 064A, iSBC 028A and iSBC 056A boards contain 16K, 32K, 64K, 128K
or 256K bytes of read/write memory implemented using dynamic RAM components. An on-board LSI
dynamic RAM controller refreshes a portion of these components every 14 microseconds. Each refresh
cycle utilizes memory for 480 nanoseconds (maximum).
The iSBC 032A, iSBC 064A, iSBC 028A and iSBC 056A boards generate byte oriented parity during all write
operations and perform parity checking during all read operations. When a parity error is detected, these
boards can generate an interrupt on the MULTIBUS interface. In addition, the row and bank of the RAM array
containing the error are stored in a Parity Flag Register (see Figure 1). This register is accessible as a MULTIBUS I/O port. An on-board LED also provides a visual indication that a parity error has occurred. To facilitate
testing of these boards, parity generation and checking can be changed from even to odd under software
control.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: CREDIT, Index, Insile, Inleliee, Library Manager, Megachassis, Micromap,
MULTI BUS, PROMPT, UPI, IIScope, Prom ware, MeS, ICE, iAMX, iSBe, ISBX, MULTIMODULE, les, iAPX and iMMX. Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No other circuil patent licenses are implied.
© INTEL CORPORATION, 1981
7-3
July, 1981
143877
iSBCTM 016A/032A/064A/028A/056A
BIT POSITION
IOIX
X
XI'IPJIBlIIBOI
--"--1 11 t
B11-0
BOlt 0
PARITY ERROR SENSED IN BANK 0 (EVEN BYTE).
PARITY ERROR SENSED IN BANK 1 (ODD BYTE).
PJ=O
RO~ 1 OF MEMORY WAS READ WHEN PARITY ERROR SENSED.
RI= 1
ROW 0 OF MEMORY WAS READ WHEN PARITY ERROR SENSED.
1 = ALWAYS ONE.
X = RESERVED.
0= ALWAYS ZERO.
Figure 1. Parity Flag Register Format
SPECIFICATIONS
Interface
Word Size
All address, data and command signals are TIL
compatible.
8 bits and 16 bits
Address Selection
Memory Size
Memory - Base address is jumper selectable on
any 4K byte boundary in a 16 megabyte address
space. On-board RAM cannot cross a megabyte address boundary.
16,384 bytes (iSBC 016A); 32,768 bytes (iSBC032A);
65,536 bytes (iSBC 064A); 131,072 bytes (iSBC
028A); or 262,144 bytes (iSBC 056A)
Parity Flag Register - The I/O address of the Parity
Flag Register is jumper selectable to be between
OOH to OFH or 40H to 4FH.
Access Time
iSBC 016A1032A1064A
400 ns max. (worst case)
360 ns max. (typical)
Connector
Edge connector - 86 pin double-sided PC edge
connector with 0.156 in. contact centers.
iSBC 028A
500 ns max. (worst case)
460 ns max. (typical)
Mating connector equivalent.
iSBC056A
570 ns max. (worst case)
530 ns max. (typical)
Viking 3KH43/9AMK12 or
Auxiliary Power
An auxiliary power bus is provided to allow
separate power to RAM array for systems requiring
battery backup of read/write memory. Selection of
this auxiliary RAM power bus is made via jumpers
on the board.
Cycle Times (Worst Case)
Read
iSBC 016A1032A1064A1028A - 600 ns max.
iSBC 056A - 650 ns max.
Memory Protect
Write
iSBC 016A1032A1064A1028A - 600 ns max.
iSBC 056A - 650 ns max.
An active-low TIL compatible memory protect
signal is brought out on the auxiliary connector
which, when asserted, disables read/write access
to RAM on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.
Refresh
iSBC 016A1032A1064A1028A - 480 ns max.
iSBC 056A - 600 ns max.
7-4
AFN.()1972A
inter
iSBCTM 016A/032A/064A/028A/056A
Physical Characteristics
iSBC 032A1064A -
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight- 14 oz. (397 gm)
iSBC 028A1056A -
0.41A
0.33A
0.55A
0.45A
(worst case)
(typical)
(worst case)
(typical)
Electrical Characteristics
Environmental Characteristics
D.C. POWER REQUIREMENTS
Operating Temperature - O°C to + 55°C
Relative Humidity - to 90% (without condensa·
tion)
All configurations require only + 5 volts ± 5%.
Normal System Operation (max.)
iSBC 016A - 3.3A (worst case)
2.65A (typical)
iSBC 032A1064A - 4.0A (worst case)
3.20A (typical)
iSBC 028A1056A - 4.57A (worst case)
3.66A (typical)
Reference Manual
143572·001 - iSBC 016A/032A/064A/028A/056A
Hardware Reference Manual (not supplied)
Manuals may be ordered from any Intel sales
representative, distributor office, or from Intel
Literature Dept., 3065 Bowers Avenue, Santa Clara,
California 95051.
Auxiliary Power No RAM Access (max.)
iSBC 016A - 0.37A (worst case)
0.30A (typical) .
ORDERING INFORMATION
Part Number Description
SBC 016A
SBC 032A
SBC 064A
SBC 028A
SBC 056A
16K·Byte RAM Board
32K·Byte RAM Board with Parity
64K·Byte RAM Board with Parity
128K·Byte RAM Board with Parity
256K·Byte RAM Board with Parity
7-5
AFN·01972A
inter
iSBC™ 064
RAM MEMORY BOARDS
• iSBC™ 80, iSBC™ 86 and iSBC™ 88
RAM memory expansion through
direct MULTIBUS® interface
• Auxiliary power bus and memory
protect control logic provided for bat·
tery backup RAM requirements
• 64K bytes of read/write memory
• Jumper selectable starting address on
any 64K boundary in a megabyte
address space
• On·board hardware for refresh of all
dynamic memory elements
• TTL compatible data, address, and
command signal interface
• Read/write data buffers
The iSBC 064 RAM Memory Board is a member of Intel's complete line of iSBC memory and I/O expansion boards. Each
board interfaces directly to any Intel iSBC 80, iSBC 86 or iSBC 88 Single board computer via the MULTIBUS interface to
expand RAM memory capacity. The iSBC 064 contains 64K bytes of read/write memory implemented using dynamic
RAM memory components. On-board refresh hardware refreshes a portion of RAM memory every 14 microseconds.
Each refresh cycle utilizes memory for 585 nanoseconds. If a read or write cycle is in progress when a refresh cycle is
scheduled to begin, the refresh cycle is postponed until the end of the cycle. Read/write buffers reside on each board to
buffer all data written into or read from the memory array. All data, address, and command signals on the bus interface
are TTL compatible.
7-6
AFN·00258A
iSBC™ 064
READ'
r-"
WRITE
ADDRESS
DATA
BLOCK
SELECT
JUMPERS
BUFFERS
4
MEMORY
ARRAY
(16K x8)
CONTROL
(BUS
~ANOSHAKE
ADDRESS
& REFRESH
ADDRESS
DECODE
LOGIC)
ADDRESS BUS
DATA BUS
CONTROL BUS
}
nMULTIBUS
l-I'NTERFACE
Figure 1. RAM Memory Expansion Boards Block Diagram
Memory Protect
SPECIFICATIONS
An active·low TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory
on the board. This input is provided for the protection .of
RAM contents during system power·down sequences.
Word Size
8 bits and 16 bits
Memory Size
65,536 bytes
Physical Characteristics
Width - 12.00 in. (30.48 cm)
Height - 6.76 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 14 oz (415.2 gm)
Access Time
450 ns max
Cycle Times
Electrical Characteristics
Read Cycle - 700 ns max
Write Cycle - 600/1240 ns max
Refresh Cycle - 700 ns max
DC Power Requirements
Normal System
Operation
(max)'
Voltage
Interface
vee= +5V ±5%
All address, data, and command signals TTL compati·
ble.
voo= + 12V
V ss =-5V±5%
Address Selection
Icc =3.2A
100=600 rnA
Iss= 10 rnA
AUX Power
No RAM Access
(max)
1.lA
600 mA
10 rnA
lo7A
120 rnA
3 rnA
Notes
1. All current values Include AUX power.
2. RAM chips and RAM controll091c powered via auxiliary power bus.
3. Power necessary to refresh RAMs and maintain data, as after system
power failure.
Jumper selection of a 64K byte page in a megabyte ad·
dress space.
Connectors
Environmental Characteristics
Edge Connectors - 86·pin double·sided PC edge con·
nector with 0.156·in. contact centers.
Mating Connector -
± 5%
AUX Power
RAM Access
(max)2
Operating Temperature -
0 'C to + 55 'C
Reference Manual
Viking 3KH43/9AMK12
9800488B - iSBC 032/048/064 Hardware Reference
Manual (NOT SUPPLIED)
Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery back up of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.
Manuals may be ordered from any Intel sales represen·
tative, distributor office or from Intel Literature Depart·
ment, 3065 Bowers Avenue, Santa Clara, California
95051.
ORDERING INFORMATION
Part Number
Description
SBe 064
64K·Byte RAM Board
7-7
AFN- iSBC 090 Memory System is a random-access dynamic memory system to be used with Intel's MULTIBUS™
System and iSBC 80186™ product line~ The ISBC 090 Memory System can provide upto 1 Megabyte of memory in
256K-byte Increments or up to 512K-bytes in 128K-byte increments_ It consists of a: MULTI BUS Interface Board and a
Series 90 Random Access Dynamic Memory_ The Interface Board plugs directly into the MULTI BUS backplane, and
through four ten-foot cables interfaces the MULTIBUS system and the memory_
The Interface Board is a 12.0 inch by 6.75 inch printed circuit board that occupies anyone slot in the MULTIBUS
backplane~ It allows the user to select the beginning and ending addresses to which the iSBC 090 Memory System will
respond; it permits either 8-blt or 16-bit bus masters, or mixes of both, as well as supporting the normal read,; write,
refresh, and inhibit RAM cycles of the MULTIBUS system. Operating power for the interface is supplied by the
MULTIBUS·chassis and is not affected by increases in memory capacity.
The memory is a self~contained unit measuring 5.21 inches high by 19.00 inches wide and by 19.5 inches deep; It includes a
memory storage area, which provides up to 1 Megabyte of memory. In addition, its control interface provides single-bit
error detection and correction, double-bit error detection, and refresh arbitration. The memory also includes an error
logger and error display, as well as its.own power supplies and blower assembly. It is available as a table-top system with
either 115 or 220 VAC input power.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Index, Intel, Inslte, Intellec. Library Manager, Megachassls,'Micromap,
MULTI BUS, PROMPT, ~MX. UPI,,,,5cope, Promware, MCS, ICE. iSSC, isex, MULTI MODULE and ICS. and the combination of MCS, RMX, ICE. iSSe, Isex or iCS and a numerical
suffix. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are implied.
@INTELcORPORATION.1981.
AUGUST 1981
7-8
AFN-IJ1256B
iSBC 090™
any size, ranging from 4K-bytes to one megabyte, starting and ending on any 4K boundary.
FUNCTIONAL DESCRIPTION
The memory portion of the iSBC 090 Memory System
(Figure 1) provides the memory storage area and the error detection and correction functions for the system_
Error Logger and Display
The Error Logger is a random·access memory which
stores (logs) ECC syndrome bits that identify the failing
bit and its location. The logger memory can store a maximum of 4096 single and double-bit errors. A display
panel shows error information for user reference.
The MULTI BUS Interface Board provides address compatibility between the MULTIBUS system and the
memory; supports the four types of data transfer across
the MULTI BUS interface; and generates the required
control and status signals_ Interface Board address circuits permit the iSBC 090 System to fit any address
space from 4K-bytes to one megabyte, starting at any 4K
boundary.
The error logger operates in three modes: log (write),
scan (read), and clear. In normal system operation, the
logger is operated in log mode and accessed only when
one or more of the syndrome bits go active, indicating
an error condition. The syndrome pattern identifying the
error and the address of the error location are stored in
the logger memory.
The Error Logger and Display records error, syndrome,
and status signals, then on request displays them for
quick location of memory errors_
To look at the stored error information, the logger is
placed in scan mode, taking it off-line. The logger
memory is sequentially scanned until error information
is reached. Scanning stops and the memory card identification, the card row, the data byte and the data bit are
displayed on the logger display panel. The scan can be
resumed using a scan control button.
Capacity
The iSBC 090 Memory System provides up to one megabyte of memory in 256K increments. Each 256K-byte increment is provided by adding one memory module in the
memory. Three standard system capacities are offered:
512K, 768K and 1024K-bytes. The 768K-byte and 512K
systems can be expanded to 1024K-bytes by the addition
of one or two memory modules respectively.
INSTALLATION
The MULTIBUS Interface Board plugs directly into the
MULTI BUS backplane. All operating power is furnished
through the MULTIBUS connectors. Interface to the
memory portion of the iSBC 090 Memory System is
made using four 50-pin flat-ribbon cables, supplied with
the System.
Addressability
The address space which the iSBC 090 Memory System
will occupy in the MULTI BUS addressing scheme is
determined by two eight-position DIP switches on the
Interface Board_ The switches allow the memory to be
l
J
MEMORY MODULES
MEMORY SELECT
AND
ADDRESS BITS
l
CONTROL/STATUS
SIGNALS
READ/WRITE
DATA
J
BXP'· BUS
MEMORY SELECT
AND
ADDRESS BITS
1
CONTROL/STATUS
SIGNALS
READ/WRITE
DATA
CONTROL INTERFACE
ADDRESS
CIRCUITS
ji
ERROR
DATA
CONTROL
LOGIC
READ/WRITE
DATA
BUFFERS/
DRIVERS
II
II
MULTIBUS'-
ERROR
LOGGER
MULTIBUS'M
INTERFACE
BOARD
Figure 1_ iSBC 090™ Memory System, Block Diagram
7-9
AFN-01256B
iSBCO90™
The iSBC 090 is avililat;>le as a 19-inch rack-mounted unit
with slide attachments or as a table top configuration
with side covers instead of slides.
Depending on the configuration selected, the memory is
connected to either 115 VAC, 50/60 Hz, single:phase, or
220 VAC,50/60 Hz, single·phase power.
SPECIFICATIONS
Logic Levels Output
Storage Capacity
Logic'High ~ +2.5V to +5.25V at 0.1 mA
Logic Low :"'O.OV to +0.5V at 16.0 mA
512K, 768K, 1024K bytes
Physical Characteristics
Word Length
iSBC Interface Board
Height
- 6.75 in. (17.15 cm)
Width
- 12.0 in. (30.48 cm)
Thickness"":' 0.5 in. (1.27 em)
.
Weight
- 3 Ibs. (1.4 Kg) (with interfacecabie,s)
8/16 bits plus 6 bits for ECC
Operating Cycles
Read Cycle
Write Cycle
Inhibit RAM Cycle
Refresh Cycle
Series 90 Memory System
Height
Width.,
Depth
Weight
Mounting
Read Access Time (8· or 16·8it Transfer)
450 nsec max (MRDC* to XACK*)
Write Access Time
- 5.21 in. (13.2 cm)
- 19.0 in. (48.25 cm)
- 19.5 in, (49.53 cm) •
-30 Ibs. (13.5 Kg) max.
- table top
.Electri.cal Characteristics
MULTI BUS Interface Board
8·Bit Transfer - 485 nsec max (MWTC* to XACK*)
16-Bit Transfer- 150 nsecmax (MWTC* to XACK*)
+5V±6.0%
2 Amps typical
3 Amps worst case
*MWTC= Memory Write Cornmand
XACK = Trans.ier Acknowledge
MRDC= Memory Read Command
Series 90 MemorySysteni
115 .VAC, .50/60 Hz, 2.8A
220 VAC, 50/60 Hz, 1.6A
(Reference MULTIBUS Manual 9800683)
Read Cycle Time (8· or 16·8it Transfer)
Environmental Requirements
485 nsec max
Ambient Operating Temperature - O'C to 50'C
Relative Humidity-10 to 90% without condensation
Write Cycle Time
REFERENCE MANUAL
8-Bit Transfer - 700 nsec max
16·Bit Transfer - 400 nsec max
The iSBC 090 Memory System is supported by a full line
of documentatioil,aslisted below:
Refresh Cycle Time (8· or 16·Bit Transfer)
450 nsec max
111710, Technical Manual fo'r iSBC 090™ Memory
System
Logic Levels Input
111784, Technical Manual for Series 90 Random Access
Memory Systems with CI·9000 Control Interface
LogiC High - +2.0V to 5.25V
Logic Low - -0.5V to ±0.80V
111764, Technical Manual for Series 90, CM·90
Dynamic Memory Module
7-10
AFN-Q1256B
iSBC 090™
ORDERING INFORMATION
Model Number
Description
SBC-090-x1 K
512K Byte Multibu5-compatible dynamic RAM memory system with ECC. Expandable to 1024K Bytes
using CM-90100-H22 memory module (below). "x" in model number must be specified per
NOTE below to define input voltage and chassis configurations.
SBC-090-x1 L
768K Byte memory system. Otherwise identical to SBC-090-x1 K.
SBC-090-x1 M
1024K Byte memory system. Not expandable. Otherwise identical to above SBC-090-x1 K.
CM-90100-H22
256K Byte memory module for expansion of SBC-090-x1K or L.
SBC-090/556 Kit
768K Byte memory system-provides an enhanced compile environment when used with the Model
556 Functional Series III Upgrade Package for Intellec Series 11/80, Series 11/85 Microcomputer
Development System (110V/60Hz or 220V/60Hz).
SBC-090/5561 Kit
768K Byte memory system-provides an enhanced compile environment when used with the Model
556 Functional Series III Upgrade Package which consists of the Model 556 software and hardware
performance package and the integrated 8085 processor board (IPC-85). This upgrade package is for
Intellec Series 11/80 Development System (110V/60Hz or 220V/50Hz).
NOTE
To order SBC 090, the "x·· in model no. must be specified as shown below to define input voltage and chassis
configuration.
x = 2 for table-top unit, 110 VAC
x = 3 for table-top unit, 220 VAC
7-11
iSBC 094
4K·BYTE CMOS RAM MEMORY
BATTERY BACKUP BOARD
• Base address selectable to start on any
4K memory address boundary
• iSBC 80, iSBC 86 and iSBC 88 non·
volatile RAM memory expansion
through the MULTIBUS
• 4K bytes of low power static CMOS
RAM memory
• On· board rechargeable batteries and
charging circuitry for 96·hour data
retention
.
• On·board power· fail interface logic
• Single
+ 5V power requirement
The iSBC 094 4K-Byte CMOS RAM Memory/Battery Backup Board .is a member of Intel's complete line of iSBC memory
and I/O expansion boards. The iSBC 094 interfaces directly to iSBC single board computer via the system bus to expand RAM memory capacity. The board contains 4K bytes of read/write memory, implemented using 32 Intel 5101
CMOS RAM memory components. On· board rechargeable batteries and charging circuitry insure that data contained
in RAM will be retained for at least 96 hours after system bus power (+ 5V) is removed. Critical system parameters
stored in the iSBC 094 RAM will thus be saved during temporary system power failures. Full power·fail interface logic
is provided on the board to generate a CPU interrupt when system power fails. Orderly system shutdown procedures
may then be executed and critical system parameters may be retrieved and stored. The use of CMOS RAM on the iSBC
094 also reduces power dissipation during normal system operation. The iSBC 094 contains jumpers for use in selecting a contiguous 4K·byte address segment beginning on any 4K memory address boundary (OOOOH, 1000H, 2000H,
etc.). Read/write buffers reside on the board to buffer all data written into or read from the memory array. All address,
data, and command signals on the bus interface are TTL compatible.
7-12
AFN-01284A
iSBC 094
BATTERIES
~
ON·BOARD
BATTERY
CHARGER
I-
+5V
MEMORY
ARRAY
+
4K X 8
RAM
SELeCT
ADDRESS
BLOCK
SELECT
JUMPERS
ADDRESS
DECODE
t
t
L--
POWER·FAIL
"INTERRUPT
LOGIC
ACLOW
(FROM
I - POWER
Y
Ii\
ADDRESS BUS
DATA BUS
CONTROL BUS
SUPPLY)
M ULTIBUS
I NTERFACE
Figure 1. ISBC 094 Memory Backup Board Block Diagram
vided for the protection of RAM contents during system
power-down sequences. This signal is automatically
asserted by the power-fail interface logic 3.6 ms after
the AC low signal is received from the system power
supply to signify that system power is beginning to fail.
SPECIFICATIONS
Word Size
8 bits and 16 bits
Memory Size
Address Selection
4096 bytes
4K segments starting at any jumper selectable base address on a 4K-byte boundary (e.g., OOOOH, 1000H, ...
FOOO H). The memory will appear in every 64K-byte memory page.
Memory Response Time
Operation
Access (ns, max)
Cycle (ns, max)
Read
750
900
Write
-
900
Mating Connectors
Pins
(qty)
Centers
Bus
86
0.156
Viking 3KH4319AMK12
Auxiliary 1
60
0.1
AMP PE5·14559 or
TI H311130
Interface
Interface
All address, data, and command signals are TTL compatible.
(In.)
Mating Connectors
Note
1. Connector Dimensions vary from vendor to vendor. Review vendor
specifications to ensure that connector heights and wire-wrap pin
lengths to conform to your system packaging requirements.
Power Fail Interrupt
Control logic is also included for generation of a powerfail interrupt to the MULTIBUS interface, which works in
conjunction with the AC low signal from the Intel iSBC
635 Power Supply or equivalent.
Data Retention
96 hours minimum after + 5V bus power is removed.
Battery Characteristics
Memory Protect
Type - Nickel-Cadmium, rechargeable
Capacity - 150 mA hr
Voltage - 3.6V nominal
An on-board memory protect signal disables read/write
access to RAM memory on the board. This input is pro-
7-13
AFN·01284A
iSBC 094
Battery Charger Characteristics
Environmental Characteristics
Charge Time
14 hours for full charge (150 mA hr)
Full overcharge protection
Full short-circuit protection
Operating Temperature -
O'C to 55'C
Physical Characteristics
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.60 in. (1.27 cm)
Weight - 12 oz (340.5 gm)
Reference Manual
98004498 - ISBC 094 Hardware Reference Manual
(NOT SUPPLIED)
Electrical Characteristics
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California
95051.
Average DC Current
Vee = +5V DC ±5%
lee=0.8A typ, 1.7A max
ORDERING INFORMATION
Part Number
Description
SBC 094
4K-Byte CMOS RAM Memory
Battery Backup Board
7-14
AFN·01284A
iSBC 108A/116ATM
COMBINATION MEMORY AND
I/O EXPANSION BOARDS
8K or 16K bytes of read/write memory
(iSBC 108A™, iSBC 116ATM boards
respectively) .
48 programmable I/O lines with sockets
for interchangeable line drivers and
terminators.
Sockets for up to 32K bytes of EPROM.
Synchronous/asynchronous communications interface with RS232C drivers
and receivers.
Auxiliary power bus and memory
protect control logic provided for
battery backup RAM requirements.
Eight maskable interrupt request lines
with a pending interrupt register.
RAM and EPROM assignable
anywhere within a one megabyte
address space.
1 msec interval timer.
The iSBC 108A and iSBC 116A Combination Memory and 1/0 Boards are members of Intel's complete line
of iSBC memory and 1/0 expansion boards. Both boards interface directly with any iSBC 80, iSBC 86 or
iSBC 88 single board computer via the MULTIBUS interface to expand RAM, EPROM, serial 1/0 and parallel
1/0 capacity. This mixture makes the iSBC 108A and 116A combination boards ideal for small microcomputer systems where the on-board resources of a single board computer are insufficient for incrementing
the memory and 1/0 capacities of larger multiple board systems.
7-15
AFN·01302A
iSBC 108A/116A
FUNCTIONAL DESCRIPTION
Memory Capabilities
The iSBC 108A board contains 8K bytes and the
iSBC 116A board contains 16K bytes of RAM implemented with eight dynamic RAM components.
An Intel 8202A dynamic RAM controller is used to
provide all timing, control and refresh signals.
Starting on a 4K byte boundary, RAM may be
located anywhere in the MULTIBUS one megabyte
memory address space.
Both combination boards contain four 28-pin
sockets for adding up to 4K bytes (using Intel 2708
or 2758 EPROMs), 8K bytes (using Intel 2716
EPROMs), 16K bytes (using Intel 2732 or 2732A
EPROMs), or32K bytes (u~ing Intel 2764 EPROMs)
of non-volatile read-only-memory.
Parallel 1/0 Interface
Each combination board contains 48 programmable I/O lines implemented using two Intel 8255A
programmable peripheral interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input/output. and bidirectional ports indicated in Table 1. Therefore.
the I/O interface may be customized to meet speci-
fied peripheral requirements. In order to take full
advantage of the large number of possible I/O configurations, sockets are provided for interchangeable
I/O line drivers and terminators. Hence, the flexibility
of the I/O interface is further enhanced by the
capability of selecting the appropriate combination
of optional line .driversand. terminators to provide
the required sink current, polarity, and drive/termi~
nation characteristics for each application. The 48
programmable I/O lines and signal ground lines are
brought out to two 50-pin edge connectors that
mate with flat, round. or woven cable.
Communications Interface
A programmable communications interface using
Intel's 8251A Universal Synchronous/AsynchronQus
Receiver/Transmitter (USART) is contained· on
each board. A jumper selectable baud rate genera C
tor provides the USARTwith all common communications frequencies between 75 Hz and 38.4 kHz.
The USART can be programmed by the system
software to select the desired asynchronous or
synchronous serial data transmission technique
(including IBM Bi-Sync). The mode of operation
(i.e .. synchronous or asynchronous), data format,
control character format, parity. and asynchronous
serial transmission rate are all under program con-
RSL32C
COMPATIBLE
USER DESIGNAHO PERIPHERALS
DEvlCfS
~ ,"TEgRUPT
REQUEST
LINES
..-----':"'-----.
CONTROL BUS
1
tNTE RRUPTS OAtGINA TlNG FROM THE PROGRAMMABL £ COMMUNICA T IONS IN TE R FACE
ANO PROGRAMMABLE PE R IPHE RAL IN T E Rf ACf J\Rf JUMP( A Sf lE C T,ASL E
Figure 1. iSBC 10SAl116A'· Combination Memory and I/O Expansion Board Block Diagram
7-16
AFN-01302A
iSBC 108A/116A
trol. The 8251A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The inclusion of a comprehensive RS232C
interface on the boards in conjunction with the
USART provides a direct interface to CRTs, RS232C
compatible cassettes, and asynchronous and synchronous modems. The RS232C, serial data lines,
and signal ground lines are brought out to a 26-pin
edge connector which mates with RS232C compatible flat or round cables.
ferred to the CPU (i.e., receive buffer is full) or a
character has been transmitted (transmit buffer is
empty). Two interrupt request lines may be interfaced directly from user designated peripheral
devices via the 110 edge connector. An on-board
register contains the status of all eight interrupt
request lines, and may be interrogated by the
CPU. Each interrupt request line is maskable
under program control. Routing for the eight interrupt request lines is jumper selectable. They may
be ORed to provide a single interrupt request line
for the iSBC 80/10A, or they may be individually
provided to the MUL TIBUS interface for use by the
other iSBC single board computers.
Interrupt Request Lines
Interrupt requests may originate from eight sources.
Four jumper selectable interrupt requests can be
automatically generated by the programmable
peripheral interfaces when a byte of information is
ready to be transferred to the CPU (i.e., input buffer
is full) or a character has been transmitted (i.e., out~
put data buffer is empty). Two jumper selectable
interrupt requests can be automatically generated
by the USART when a character is ready to be trans-
Interval Timer
Each board contains a jumper selectable 1 ms interval timer. The timer is enabled by jumpering one of
the interrupt request lines from the liD edge con~
nector to a 1 ms interval interrupt request signal
originating from the baud rate generator.
Table 1. InputlOutput Port Modes of Operation
Mode of Operation
Unidirectional
Port
Lines
(qty)
Input
Bidirectional .
Output
Unlatched
Latched &
Strobed
Latched
Latched &
Strobed
X
X
X
X
Control
8
X
X
2
8
X
X
3
4
X
X
4
X
X
4
8
X.
X
X
X
5
8
X
X
X
X
6
4
X
X
X'
4
X
X
X'
1
X
X'
X'
X
Notes
1. Part of port 3 niu;t be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output or port 1
is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 40r port Sare used as a latched and strobed input or a latched and strobed output or port 4
is used as a bidirectional port.
7-17
AFN-01302A
iSBC 108A/116A
SPECIFICATIONS
Serial Communications Characteristics
Memory Word Size
Synchronoils - 5 - 8 bit characters; internal or
external character synChronization; automatic sync
insertion.
8 bits only. 16·bit single board computers may use
this memory only for the storage of 8·bit data.
Asynchronous - 5 - 8 .bit characters; break characters generation; 1. 1 'h. or 2 stop bits; false start bit
detectors.
Memory Addressing
EPROM - Up to 4K,8K, 16K or 32K bytes of read·
only·memory may be located anywhere within a
one megabyte address range. The base address
must be located on a 4K byte boundary. EPROM
addresses may not cross 32K byte boundaries.
Interrupts
Eight interrupt request lines may originate from the
programmable peripheral interface (4 lines). the
USART (2 lines) or user specified devices via the
I/O edge connector (2 lines). or interval timer.
RAM - 8K (iSBC 108A) or 16K (iSBC116A) bytes
of RAM may be located anywhere in a one mega·
byte address range. The base address must be
located on a 4K byte boundary. RAM addresses
may not cross 32K byte boundaries.
Interrupt Register Addresses
XX1
XXO
Interrupt mask register
Interrupt status register
Note
XX is any Iwo hex digits assigned by jumper selection.
Memory Response Time
Memory
Access (ns)
Cycle (ns)
RAM
450 max*
580 max'
EPROMIROM
450 max
635 max
Timer Interval
1.003 ms ±0.1 % when 110 baud rate is selected.
1.042 ms ±0.1 % for all other baud rates.
• Without refresh contention.
Interfaces
Bus- All signals TTL compatible
Parallel I/O - All signals TTL cOmpatible
Serial I/O - RS232C
Interrupt Requests - All TTL compatible
I/O Transfer Rate
Parallel- Read or write acknowledge time 575 ns max.
Serial -
(USART)
Connectors
Baud Rale (Hz)
Frequency (kHz)
(Jumper Selectable)
Synchronous
Interface
Asynchronous
(Program Selectable)
Bus (Pl)
-
307.2
153.6
76.8
38.4
19.2
9.6
4.8
6.98
-.
38400
19200
9600
4800
6980
c- 16
c- 64
19200
9600
4800
2400
1200
600
300
4800
2400
1200
600
300
150
75
110
-
No. 01
Pins
Centers
(In.)
86
0.156
Viking 3KH43/9AMK12
Mating Connectors
Parallel 1/0
50
0.1
3M 3415·000 or
TI H312125
Serial 1/0
26
0.1
3M 3462-000 or
TI H312113
Aux. Power (P2)
60
0.1
AMP PE5-14559 or
TI H311130
NOTE: Connector heights and wire:'wrap pin lengths are not guaranteed to conform to Intel OEM packaging.
I/O Addressing
Port
1
2
3
4
5
6
8255A
No.1
Control
8255A
No.2
Control
USART
Data
Control
Address
XX4
XX5
XX6
XX8
XX9
XXA
XX7
XXB
XXC or XXE
XXD or XXF
USART
Note
XX is any two hex digits assigned by jumper selection,
7-18
AFN.Q1302A
in1:ef
iSBC 108AI116A
Auxiliary Power
Bus Drivers
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.
Function
Data
Commands
Memory Protect
An active-low TTL compatible memory protect signal is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.
Physical Characteristics
Electrical Characteristics
Voo :;:
Vee ::
Vas ::;:
+12t5%
+5t5%
-stS%
-12t5%
250 rnA
2.9 A
-
70 rnA
4 27085 and
6 Terminators
520 rnA
3.6 A
180 rnA
70 rnA
4 27165 and
No Terminators
250 rnA
3.3 A
-
70 rnA
4 27325 and
No Terminators
250 rnA
3.5 A
-
70 rnA
Aux. Power
RAM Accessed
175 rnA
0.45 A
3 rnA
-
20 rnA
0.45 A
3 rnA
-
No EPROM or
Terminators
Sink Current (mAl
48
48
16
16
16
16
16
16
I.OC
I
NI
I.OC
NI.OC
NI
I.OC
I
7438
7437
7432
7426
7409
7408
7403
7400
32
32
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 14 oz (397.3 gm)
I/O Drivers - The following line drivers and terminators are all compatible with the I/O driver sockets
on the iSBC 108A/116A board. Ports 1 and 4 have
25 mA totem-pole drivers and 1 kO terminators,
Characteristic
Sink Current (mAl
Tri-State
Tri-State
Average DC Current
linE! Drivers' and Terminators
Driver
Characlerislic
Aux. Power
No· RAM Access
VAA
=
Nole
I
~
inverting; NI
~
non-inverting; DC
~
open collector.
Environmental Characteristics
I/O Terminators - 2200/3300 divider or 1 kO pullup.
22011133011
O°C to +55°C.
Reference Manuals
!~~
33(II~i- - - - -......- - - - 0 0 sac !JOT
OPTION
liell
, ItLJ
Operating Temperature -
.5 ---~.I\/'v~--------_<>o
sec !HI20PTIQN
9800862 - iSBC 108A/116A Board Hardware Reference Manual (NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.
ORDERING INFORMATION
Part Number
Description
SBC 108A
Combination Memory and
I/O Expansion Board with
8K bytes RAM
SBC 116A
Combination Memory and
I/O Expansion Board with
16K bytes RAM
7-19
AFN·01302A
iSBC 300 or (pSBC 300*)
32K·BYTE RAM EXPANSION MODULE
iSBC 340 or (pSBC 340*)
16K·BYTE EPROM EXPANSION MODULE
• On~board memory expansion
eliminates MULTIBUS system bus
• On·board memory expansion for iSBC
86112A Single Board Computer
latency and increases system
throughput
• iSBC 300 module provides 32K bytes of
dual port dynamic RAM and plugs
directly into the iSBC 86112A board,
• Low power requirements
• iSBC 340 module provides sockets for
up to 16K bytes of additional EPROM
and plugs directly into the iSBC 86112A
board
• Simple, reliable mechanical and
electrical interconnection
The iSBC 300 32K-byte RAM expansion module and the iSBC,340 16K-byte EPROM expansion module provide simple,
low cost expansion of the memory complement available on the iSBC 861.12A single board computer. Each module
utilized individually or together can double the iSBC 86/12A board's on-board RAM and EPROM memory, capacity. The
iSBC 300 32K-byte RAM expansion module and the iSBC 340 16K-byte EPROM expansion module options for the iSBC
86/12A board offer system designers a new level of flexibility in defining and implementing Intel@ single board computer systems. These options allow the systems designer to double the memory complement of an iSBC 86/12A board
with a minimum of system implications. Because they expand the memory configuration on-board, they can be accessed as quickly as the existing iSBC 86/12A memory by eliminating the need for accessing the additional memory
via the MULTI BUS system bus. With the iSBC 86/12A board mounted in the top slot of an iSBC 60,4 or iSBC 614 cardcage, sufficient clearance exists for mounting both the iSBC 300 and/or the iSBC 340 expansion module option(s). If
the iSBC 86/12A board is inserted into some other slot, the combination of boards will physically (but not electrically)
occupy two cardcage slots. Incremental power required by the options is minimal; for instance, only 305 mW is needed
for the iSBC 300 RAM expansion module.
'Same product, manufactured by Intel Puerto Rico, Inc,
7-20
AFN-01282A
iSBC 300/340
FUNCTIONAL DESCRIPTION
iSBC 340 16K·byte MULTIMODULE EPROM
The iSBC 340 module expands the iSBC 86/12A Single
Board Computer's on-board EPROM capacity from 16K
bytes to 32K bytes. It measures 3.3" by 2.8" and consists
of a PC board with six 24-pin special sockets. Two of the
sockets have extended pins which mate with two of the
EPROM sockets on the iSBC 86/12A board. Two of the
EPROMs which would have been inserted on the iSBC
86/12A board are then reinserted in the iSBC 340
module. Additional pins also mate for bringing chip
selects for the remaining EPROM devices (see Figure 2).
The mechanical interface is similar to that used on the
iSBC 300 RAM module and consists of two additional
mounting holes and the necessary mounting hardware.
iSBC 300 32K-Byte MULTIMODULE RAM
The iSBC 300 module contains sixteen 16K-byte dynamic RAM devices, sockets for the Intel® 8202A Dynamic
computer. It expands the iSBC 86/12A board's on-board
dual port RAM capacity from 32K bytes to 64K bytes.
The iSBC 300 module contains sixteen 16K-byte dynamic RAM devices, sockets for the Intel® 8202 Dynamic
RAM Controller and memory interface latching. To install the iSBC 300 module, the latches and .controller
from the iSBC 86/12A board are removed and inserted
into the sockets on the iSBC 300 module. The add-on
board is then mounted onto the iSBC 86/12A board. Pins
extending from the controller's and latches' sockets
mate with the devices' sockets underneath (see Figure
1). Additional pins mate to supply power and other signals to complete the electrical interface. The module is
then secured at three additional points with nylon hardware to insure the mechanical security of the assembly.
The iSBC 340 module supports Intel® 2732 EPROM. One
section of the iSBC 86/12A on-board memory and
MULTIBUS address decode PROMs (the same decode
PROMs mentioned for the iSBC 300 module) is already
preprogrammed to support the iSBC 340 module with
Intel® 2732 EPROMs. This section is selected through
the EPROM configuration switches on the iSBC 86/12A
board. The iSBC 340 board can optionally be configured
by the user to support Intel® 2758 or 2761 EPROMs by
programming new iSBC 86/12A decode PROMs to sup,
port these devices. Necessary documentation and
PROM map listings are in the iSBC 86/12A Hardware
Reference Manual (order number 9803074'01).
To complete the installation, two socketed PROMs are
replaced on the iSBC 86/12A board with those supplied
with the iSBC 300 kit. These are the on-board memory
and MUL TIBUS address decode PROMs which allow the
iSBC 86/12A board logic to recognize its expanded
on-board memory complement.
MEMORY lATCHES
(FROM iSBC 86/12A)
REPLACEMENT
MEMORY ADDRESS
DECODE PROMS
(SUPPLIED WITH
iSBC 300 OPTION)
NYLON MOUNTING HARDWARE
(3 PLACES)
(SUPPLIED WITH iSBC 300 OPTiON)
Figure 1. Installation of iSBC .300 MULTIMODULE RAM on iSBC 86/12A Single Board Computer
7-21
AFN·01282A
iSBC 300/340
SPECIFICATIONS
ISBC 86/12A board + ISBC 340 module (32K bytes
max) FEOOO-FFFFFH (using 2758 EPROMs);
FCOOO-FFFFFH (using 2716 EPROMs); F8000FFFFFH (using 2732 EPROMs).
Word Size
8 or 16 bits (16-bit data paths)
Memory Size
On-board EPROM/ROM is not accessible via the
MULTIBUS interface.
iSBC 300 Module - 32,768 bytes of RAM
iSBC 340 Module - 16,384 bytes (max) of EPROM
Auxiliary Power/Memory Protection
Access Time
iSBC 300 Module - Read: 1 fLsec, write: 1.2 fLsec
iSBC 340 Module - Standard EPROMs (450 nsec): 1
fLsec, fast EPROMs (350 or 390 nsec): 800 nsec
Interface
The interface for the iSBC 300 and iSBC 340 module options is designed only for Intel's iSBC 86/12A Single
Board Computer.
The low power memory protection option included on
the iSBC 86/12A boards supports the iSBC 300 RAM
module.
"Local Only" Memory Protection
The iSBC 86/12A Single Board Computer supports
dedication of on-board RAM for on-board CPU access
only in 8K, 16K, 24K, or 32K-byte segements. Installation
of the iSBC 300 option allows protection of 16K, 32K, 48K,
or 64K-byte segments.
Memory Addressing
Physical .Characteristics
On-board RAM
CPU Access
ISBC 86/12A board only (32K bytes) - 00000-07FFFH.
ISBC. 86/12A board + ISBC 300 module (64K bytes) OOOOO-OFFFFH.
MULTIBUS Access - Jumper selectable for any 8Kbyte boundary, but not crossing a 128K-byte boundary.
Isec 300
Isec 340
Width
5.75"
3.3"
Length
2.35"
2.8"
.718
.718'
13 oz.
5 oz.
Height of iSSC 86(12A
plus mounted option
Weight
On-board EPROM
ISBC 86/12A board only (16K-bytes max.) - FFOOOFFFFFH (using 2758 EPROMs); FEOOO-FFFFFH (using
2316E ROMs or 2716 EPROMs); and FCOOO-FFFFFH
(using 2332A ROMs or 2732 EPROMs).
~Includes
EPROMs
All necessary mounting hardware (nylon, screws,
spacers, nuts) are supplied with each kit.
Isac 340
OPTION
Isac 86/12A
~
Figure 2. Installation of iSBC 340 MULTIMODULE EPROM Option on iSBC 86112A Single Board Computer
7-22
AFN·01282A
ISBC 300/340
Electrical Characteristics
Environmental Characteristics
DC power requirements:
Operating Temperature - 0° to +55°(:;
Relative Humidity - to 90% (without condensation)
Vollage
ISBC 300
ISBC 340
+5 ±5%
1 rnA
+12 ±5%
24 rnA
-
-12 ±5%
1 rnA
-
120 rnA'
Note:
1. Loaded with Intel 2732 EPROMs.
Reference Manuals
All necessary documentation for the iSBC 300 MUL TIMODULE RAM and iSBC 340 MULTIMODULE EPROM/
ROM is included in the iSBC 86/12A Hardware Reference
Manual; order #9803074-01. (NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, CA 95051.
ORDERING INFORMATION
Part Number Description
SBC 300
32K byte MUL TIMODULE RAM
SBC 340
16K byte MUL TIMODULE EPROM
7-23
AFN·01282A
"
iSBC™ 301
:4K-BYTE RAM .
". MULTIMObuLE™ BOARD
..
• O.S watts incremental power
.
dissipation
• On·board memory expansion to 8K
bytes for iSBC™ 80/24 and iSBC™88140
Single Board Computers
• On·board memory. expansion ' .
eliminat~s MULTIBUS system bus.
latency anCtincreases system
throughput'
• Provides 4K bytes of static RAM
directly on·board
• Uses S MHz (818S·2) RAMs
• Single
• Reliable mechanical and electrical
interconnection
+ SV supply
The Intel iSBC 301 4K-Byte RAM MULTlMODULE Board provides simple, low cost expansion to double the
RAM capacity on the iSBC 80/24 or iSBC 88/40 Single Board Computer to 8K bytes. This offers system
designers a new level of flexibility in defining and implementing system memory requirements. Because
memory is configured on-board, it can be accessed as quickly as the existing iSBC 80/24 or iSBC 88/40
memory, eliminating the need for accessing the additional memory via the MULTIBUS system bus. As a
result, the iSBC 301 board provides a high speed, cost effective solution for systems requiring incremental
RAM expansion. Incremental power required by the iSBC 301 module is minimal, dissipating only 0.5
watts.
7-24
AFN·01487A
iSBC 301
FUNCTIONAL DESCRIPTION
The iSBC 301 board measures 3.95" by 1.20" and
mounts above the RAM area on the iSBC 80/24 or
iSBC 88/40 single board computer. It expands the
on-board RAM capacity from 4K bytes to 8K bytes.
The iSBC 301 MULTIMODULE board contains four
1K byte static RAM devices and a socke.t for one of
the RAM devices on the iSBC 80/24 or iSBC 88/40
board. To install the iSBC 301 MULTIMODULE
board, one of the RAMs is removed from the host
board and inserted into the socket on the iSBC 301
board. The add·on board is then mounted into the
vacated RAM socket on the host board. Pins ex-
tending from the RAM socket mate with the
device's socket underneath (see Figure 1). Additional pins mate to the power supply and chip
select lines to complete the electrical interface.
The MULTIMODULE board is then secured at two
additional points with nylon hardware to insure
mechanical security of the assembly. With the
iSBC 80/24 or iSBC 88/40 board mounted in the top
slot of an iSBC 604 or iSBC 614 cardcage, sufficient clearance exists for mounting the iSBC 301
option. If the iSBC 80/24 or iSBC 88/40 board is inserted into some other slot, the combination of
boards will physically (but not electrically) occupy
two cardcage slots.
RAM DEVICE
FROM HOST BOARD
/
~
~
iSBC™ 301 OPTION
-----_~ HARDWARE (2 PLACES)
NYLON MOUTING
(SUPPLIED WITH
iSBC™ 301 OPTION)
Figure 1. Installation of iSBC'M 301 4K-Byte RAM MULTIMODULE™ Board
7-25
AFN·01487A
iSBC301
3.95 in. (10.03 cm)
.44 in. (1.12 cm) iSBC 301 Board
.56 in. (1.42 cm)
iSBC 301 Board + host board
Weight - .69 oz. (19 gm)
Length -
SPECIFICATIONS
Height -
Word Size
8 bits
Memory Size
Electrical Characteristics
DC Power Requirements:
10 mA at + 5 Volts incremental power
4096 bytes of RAM
Access Time
Read: 140
200
Write: 150
190
ns
ns
ns
ns
(from
(from
(from
(from
Environmental Characteristics
READ command)
ALE)
READ command)
ALE)
Operating Temperature - 0° to + 55° C
Relative Humidity - to 90% (without condensation)
Reference Manuals
Memory Addressing
All necessary documentation for the iSBC 301
MULTIMODULE board is included in the CPU
board Hardware Reference Manual (NOT SU PPLIED)
Memory addressing for the iSBC 301 4K-Byte RAM
MULTIMODULE Board is controlled by the host
board via the address and chip select signal lines
and is contiguous with the host board RAM.
iSBC 80/24 - Order No. 142648-001
iSBC 88/40 - Order No. 124978-001
iSBC 80/24 and iSBC 301 board: 02000-02FFF
iSBC 88/40 and iSBC 301 board: 00000-01 FFF
Manuals may be ordered from any Intel sales
representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
Physical Characteristics
Width -
1.20 in. (3.05 cm)
SPECIFICATIONS
Part Number
Description
SBC 301
4K Byte RAM MULTIMODULE
Board
7-26
AFN-014B7A
iSBC™ 302
8K·BYTE MULTIMODULE™ RAM
• Expands on·board memory of the
iSBC™ 86/05 and iSaC™ 88/25 Single
Board Computers
• Uses four Intel® 2168 static RAMs
- • Single + 5V supply
• On·board memory expansion
eliminates system bus latency and
increases system throughput
• Reliable mechanical and
interconnection
electric~1
The Intel iSBC 302 8K-Byte MULTIMODULE RAM provides simple, low-cost expansion to double the RAM
capacity on the iSBC 86/05 Single Board Computer to 16K bytes or increase RAM capacity on the iSBC
88/25 Single Board Computer to 12K bytes. This offers system designers a new level of flexibility in implementing system memory. Because the MULTIMODULE memory is configured on-board, it can be accessed as quickly as the standard on~board iSBC 86/05 or iSBC 88/25 memory, eliminating the need for accessing additional memory via the MULTIBUS system bus. As a result, the iSBC 302 board provides a high·
speed, cost-effective solution for !'lY!'ltems requiring incremental RAM expansion.
7-27
AFN-01824A
intJ
iSBC 302
FUNCTIONAL DESCRIPTION
The iSBC 302 board measures 2.S0" by 2.30" and
mounts above the RAM area on the iSBC 8S/05 or
iSBC 88/25 Single Board Computer. The iSBC 302
MULTIMODULE board contains four 4K x 4 static
RAM devices and sockets for two of the RAM
devices on the iSBC 8S/05 board. With the iSBC
302 module mounted on the iSBC 88/25 board, the
two sockets on the iSBC 302 module may be filled
with 4K'x 4 static RAMs. The two sockets on the
iSBC 302 module have extended pins which mate
with two sockets on the base board. Additional
pins.mate to the power supply and chip select
lines to complete the electrical interface. The
mechanical integrity of the assembly is assured
with nylon hardware securing the module in .two
places. With the iSBC8S/05 or iSBC 88/25 board
mounted in the top slot of an iSBCS04/S14 card·
cage, sufficient clearance exists for the mounted
iSBC 302 option. If the is!3C 8S/05 or iSBC 88/25
board is inserted into some other slot; the com·
bination of boards will physically (but not elec·
trically) occupy two cardcage slots.
after that of the iSeC 88/25 board's 4K RAM (i.e.,
default configuration ...,...
SPECIFICATIONS
Word Size
iSBC88/25 board's RAM.....;. O-OFFFH
iSBC 302 board's RAM - 01000H-02FFFH).
8mi bits
Physical Characteristics
Mem()ry Size
WIDTH -
1S,384 bytes of RAM
LENGTH .,... 2.3 in. (5.84 cm)
HEIGHT -
0.5S. in. (1.42 cm) iSBC 302 board
iSBC 86/05 or iSBC 88/25 board
WEIGHT -
1.25 oz (35 gm)
Cyple Time
Provides "no wait state" memory operations on
the iSBC8S/05 board at 5 MHzor8 MHzorthe iSBC
88i25 board at 5 MHz.
5 MHz cycle time - 800 ns
8 MHz cycle time - 500 ns
2.6 in. (6.60 cm)
+
Electrical Characteristics
DC POWER REQUIREMENTS . incremental power
720 mA at + 5V
Environmental Characteristics
Memory Addressing
OPERATING TEMPERATURE -
Memory addressing for the iSBC 302 MULTI MOD·
ULE board is controlled by the host board via the.
address and chip select signal lines.
RELATIVE HUMIDITY -
O'C to + 55'C
to 90% (without con·
densation)
Reference Manuals
With the iSBC 8S/05 board:
AI! necessary documentation for the iSBC 302
MULTIMODULE board is included in the CPU
board .Hardware Reference Manuals (NOT SUP·
The 8K bytes of RAM on the iSBC 302 board oc·
cupy the 8K·byte address space immediately
after that of the iSBC 8S/05 board's 8K RAM (i.e.,
default configuration -
PLIED).
iSBC 8S/05 - Order No. 143153-001
iSBC 88/25 - Order No. 143825-001
iSBC 8S/05 board's RAM - 00000-01 FFFH
iSBC 302 board's RAM - 02000-03FFFH).
Manuals may be ordered from any Intel sales
representative, distributor office, or from Intel
Literature Department, 30S5 Bowers Avenue;.$anta
Clara, California 95051.
With the iSBC 88/25 board:
The 8K bytes of RAM on the iSBC 302 board oc·
cupy the 8K byte address space immediately
ORDERING INFORMATION
Part Number
Description
SBC 302
8K·Byte MULTIMODULE RAM
7-28
AFN·01B24A
iSBC™ 303
MULTIMODULE™ PARITY
• Add-on parity op1ion for iSBC 86112A
Single Board Computer
• Two LED error indicators
• Two interrupt requests for error
. repor.ing
• Supports 32KB or 64KB (with iSBC.300
MULTIMODULE RAM) on-board RAM·
• No degradation of memory
performance
• Byte parity with programmable
odd/even detection/generation
:
.
• Memory diagnostic capability
'
'"
'
.:.
The iSBC 303 M ULTI MODULE Parity option provides on-board parity support for the on-board RAM of th!'l
iSBC 86/12A Single Board Computer. Memory parity generation/detection is invaluable fOJ those applications in which execution of erroneous instructions or data must be prevented, as in critical process control, medical and firiancial transaction systems. When used on single board computers in conjunction
with MULTIBUS@-based, parity-protected RAM expansion boards in large memory configurations, the
iSBC 303 MULTIMODULE Parity option provides consistent protection throughout all system RAM.
The following are trademarks·of Intel Corporation and may-be used only to describe'lntel products: CREDIT, Index,lnslte,lntellec, Library Manager,' Megachassis, Micromap.
MULTIBUS. PROMPT, UPl,pScope, Promware, MeS, ICE, iRMX, iSeC, Il:?BX, ~ULTIMODUL.E, leS, iAPX and iMMX.lnlel Corporation assumes no responsibility forlhe use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
7-29
June. 1981
143890
inter
iSBCTM 303
FUNCTIONAL DESCRIPTION
The iSBC 303 MULTIMOOULE Parity option Is a
complete subsystem, providing all necessary
logic and display to support the iSBC 86/12A onboard RAM. Operation of the iSBC 303 option,
once initialized, is transparent to the system, as
the option caus~.s no memory performance degradation. If an error is detected and interrupts are
enabled, an interrupt request will be issued to the
iSBC 86/12A board. Included on-board is the parity
generator/checker and parity memory RAM, the interrupt request logic, error display, cpmmand register and the necessary interface for address; data
and control (inputs) and interrupt requests (outputs) (See Figure 1). The parity generator/checker
is a 74S280 MSI device. The memory devices are
four Intel® 2118 dynamic RAMs. Parity is
generated/detected on a byte basis; for a 32KB
RAM configuration, only two of the'parity RAMs
are used. When the iSBC 303 board is used in conjunction with the iSBC 300 32KB MULTIMOOULE
RAM ,option (which provides a total of 64KBonboard RAM), all four parity RAMs are used. Odd or
even parity may be programmatically selected
through the command register. This feature also
provides the ability to "force errors" to verify
operation of the board.
Error Reporting
Two interrupt requests are provided: one which
can be connected to the NMI input of the Intel
8086 CPU, and another which can be wired to the
Intel 8259A interrupt controller and/or Intel 8255A
Programmable Peripheral Interface on theiSBC
86/12A board. The 'NMI req'uest' can be
enabled/disabled via the command register or optionally with the NMIMASK signal which can be
controlled by the 8255A PPI. Additionally, a power
fail request signal originating from the system
power supply can be "OR'ed" with the parity NMI
request, allowing both signals to be issued to the
8086 CPU.
The error display logic contains two LEOs which
indicate errors for high and low bytes. High and
low byte error signals can also be connected to
the 8255A, to read error status under program control. The LEOs and error signals are controlled by
the command register.
Base·board Interface
The address, control and data signals are generil,ted by the iSBC 86/12A RAM logic, and are connected to tne iSaC 303 module through the sockets of the Intel 8202A RAM controller and the data
latches (see Figure 2). The,other I/O signals to/
from the iSBC 303 board are brought out to an
8-pin connector trom which a cable assembly (not
supplied) establishes connections to the iSBC
86/12A board. Mechanical integrity is assured by
three-point mounting with nylon hardware. The
iSBC 86/12A and iSBC 303 boards can be mounted
in the end slotof an Intel iSBC 604/614 cardcage.
If mounted in other than the top slot, it will
physically occupy two slots. The iSBC 86/12A,
300, 303 board combination will not fit in the top
slot, and also occupies two ciudcage positions
when mounted.
DATA
ERROR
INTERRUPTS
PFIN
NMIMASK
Figure 1_ ISBC™ 303 Functional Block Diagram
7-30
AFN·01983A
intJ
iSBCTM 303
MEMORV LATCHES
(FROM iSBC 86112A)
NVLON MOUNTING HARDWARE
(3 PLACES)
(SUPPLIED WITH ISBC 303 OPTION)
Figure 2~ iSBC™ 303 Option Installation
parity mode (e.g. even). These reads should cause
detectable errors and interrupts will be generated,
verifying the error detecting and reporting
capability.
Programmatic Control
The command register is a 4-bit, memory mapped
register through which the operation of the iSBC
303 module is controlled (see Figure 3). Read/
write access to all bits is available through either
location OH or 400H (jumper selectable). Initialization software should enable the NMI interr4pt and
the maskable interrupt and LED, as required. It
should also select odd or even parity generation
(odd is recommended for detection of catastrophic
RAM failure).
0- ODD PARITV
1 - EVEN PARITY
0- LED CLEAR
1 - LED ENABLED
Diagnostic Capability
o- INTR CLEAR
1 - INTR ENABLED
Operation of the iSBC 303 module and the integrity of the RAM can be checked with a diagnostic
software routine which can 'force errors' in parity
memory. This is accomplished by writing data in
one parity mode (e.g. odd), toggling the odd/even
bit and then reading data with the complementary
0- NMI CLEARIMASK
1 - NMI ENABLED
Figure 3. iSBC™ 303 Option
Command/Status Register
'7-31
AFN-01983A
inter
iSBCTM 303
SPECIFICATIONS
Physical Characteristics
Word Size
Width -
6.375 in. (16.2 cm)
Height - Height of iSBC 86/12A board + iSBC 303,
module: 0.718 in. (1.82 cm)
Height of iSBC 86/12A board + iSBC 300
module + iSBC 303 module:
1.05 in. (2.66 cm)
Byte parity on 8 and 16·bit words.
Cycle Time
'Supports ISBG86112A memory cycle times with
no additional wait states.
Depth -
2.40 in. (6.1 cm)
Weight -2;3 oz. (28.5 gm)
:Memory Capacity
All necessary mounting hardware (screws, nuts,
spacers) are supplied with each kit.
Supports 32KBof iSBC86/12A on·board RAM or
64KB with iSBC 300 MUlTIMODULE RAM option.
Electrical Characteristics
+ 5 VDC (± 5%)
Interface'
605 mA max.,
All sign,als Til compatible.
Environmental Characteristics
O·C to + 55·C
Connector (Not Supplied)
Operating Temperature Pins
Shells
Reeled
loose
AMP 87456·4
86491·3
87045·2
Berg 65043·033
47564
47744
Relative Humidity tion)
Reference Manual (Not Supplied)
,"
All necessary documentation for the iSBC 303
MUlTIMODUlE Parity option is contained in the
iSBC 86/12A Single Board Computer Hardware
Reference Manual; order #9803074·02.
Auxiliary Power/Memory Protection
The auxiliary power (i.e. battery backup operation)
,and memory protection (i.e. write disable on out·
of·limits power supply voltages) features of the,
iSBC 86112A Single Board Computer are sup' '
ported on the iSBC 303 module.
,
ORDERING INFORMATION
Part Number
Description
,SBC 303
MUlTIMODUlE Parity
To 90% (without condensa'
7-32
Manuals may be ordered from any Intel sales rep·
resentativ~, distributor office or from Intel Litera·
ture Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.
iSBC 341™
28·PIN MULTIMODULE EPROM
• Sockets for up to 64K bytes of expan·
sion with Intel® 27128 EPROMs
• On·board memory expansion for iSBC
86/05, iSBC 88/25, and iSBC 88/40
microcomputers
• On·board expansion provides "no wait
state" memory access with selected
devices
• Supports JEDEC 24/28·pin standard
memory devices, including EPROMs,
byte·wi~e RAMs, and E2PROMs
• Simple, reliable mechanical and
electrical interface
The iSBC 34128-pin MULTIMODULE EPROM board provides simple, low-cost expansion of the on-board
EPROM capacity of the iSBC 86/05 Single Board Computer, the iSBC 88/25 Single Board Computer and the
iSBC 88/40 Measurement and Control Computer. Four additional 28-pin sockets support JEDEC 24/28-pin
standard devices, including EPROMs, byte-wide static and pseudo-static RAMs.
The MULTIMODULE expansion concept provides the optimum mechanism for incremental memory expansion. Mounting directly on the microcomputer, the benefits include low cost, no additional power requirements beyond the memory devices, and higher performance than MULTI BUS-based memory expansion.
7-33
AFN-01825A
iSBC 341
FUNCTIONAL DESCRIPTION
are then reinserted in the iSSC 341 sockets. Addi·
tional interface pins also connect chip select
lines and power. The mechanical integrity of the
assembly is assured with nylon hardware secur·
ing the unit in two places.
The iSSC 341 28'pin MULTIMODULE EPROM op·
tion effectively doubles the number of sockets
available for EPROM on the base microcomputer
board on which it is mounted. The iSSC 341 board
contains six 28·pin sockets. Two of the sockets
have extended pins which mate with two of the
sockets on the base board. Two of the EPROMs
which would have been inserted in the base,board
Through its unique interface, the iSSC 341 board
can support 8 or 16·bit data paths. The data path
width is deterlT)ined by the base board - being 8
bits for the iSS9 88/40 and iSSC 88/25 microcom·
puters, and 8/16 bits forthe iSSC 86/05 board.
SPECIFICATIONS
Auxiliary Power
Word Size
There are no provisions for auxiliary power (bat·
tery backup) on the iSSC 341 option.
8 or 8116 bits (determined by data path width of
base board).
Physical Characteristics
WIDTH -
3.4 in. (8.64 cm)
Memory Size
LENGTH - 2.7 in. (6.86 cm)
32K bytes with available technology (JEDEC stan·
dard defines device pin·out to 128K·bit devices).
HEIGHT - 0,78 in. (1.98 cm))*
WEIGHT -
Device Size
, (Bytes)
EPROM
Type
Max. iSBC 341 Capacity
(Bytes)
2Kx8
4Kx8
8Kx8
16Kx8
2716
2732
2764
27128
8K
16K
32K
64K
All necessary mounting hardware (nylon screws,
spacers, nuts) is supplied with each kit.
Environmental Characteristics
OPERATING TEMPERATURE - O°C to + 55°C
RELATIVE HUMIDITY - to 90% (without conden·
sation)
Access Time
Reference Manuals
Varies according to base board and memory
device access time. Consult data sheet of base
board for details.
All necessary documentation for the iSSC 341
module is included in the CPU board Hardware
Reference Manua.ls (NOT SUPPLIED)
Memory Addressing
iSSC 86/05 iSSC 88/25 iSSC 88/40 -
Consult data sheet of base board for addressing
data.
2716
2732,2732A
2764
Max. Current
@
5V
Order No. 143153·001
Order No. 143825·001
Order No. 124978·001
Manualsmay be ordered from any Intel sales rep·
resentative, distributor office, or from Intel Litera·
ture Department, 3065 Sowers Avenue, Santa
Clara, California 95051.
POWER REQUIREMENTS
Devices 1
5 oz (141.5 gm)
"Includes height of mounted memory devices and base board,
:!: 5%
' 420 rnA
600 rnA
600 rnA
ORDERING INFORMATION
NOTE:
1, Incremental power drawn from host board for four addition·
al devices.
7-34
Part Number
Description
SSC 341
28·Pin MULTIMODULE EPRPM
iSBC 416
16K EPROM EXPANSION BOARD
• Allows iSBC 80 EPROM/ROM
expansion through the MULTIBUS
interface
• Switches enable or disable each
memory block
• Jumper selectable addresses for each
8K block
• Sockets for up to 16K bytes of Intel
2708 programmable and erasable
PROM
• Buffered address and data lines
The ISBC 416 16K EPROM Expansion Board Is a member of Intel's complete line of ISBC memory and 1/0 expansion
boards. The ISBC 416 Interfaces directly to any ISBC 80 single board computer via the system bus to expand EPROM
memory capacity. The board contains 16 sockets that can house Intel 2708 programmable and erasable EPROMs.
EPROM memory can be added In 1K·byte Increments. The ISBC 416 contains a set of jumpers allowing the selection of
the base address of Independent 8K memory blocks, to begin on any 8K boundary. Switches are used to enable on·
board memory In 1K block Increments.
7-35
AFN-00274A
iSBC 416
V
TIMING
CONTROL
PROM
REAO REQUEST
SELECTEO
ADDRESS
ADDRESS,
CONTROL
BLOCK
~
>
SOCKETS FOR
.'18K BYTES
OF
EPROM
MEMORY
_UDATA',
DATA LINE BUFFERS
ADDRESS BUS
I
!
DATA BUS
COMMAND BUS
~'MULriBUS
~INreRFACE
Figure 1. IS,BC416 PROM Expanslcm Board Block Diagram
"
,
Physical CharacteristiC::s '
SPECIFICATIONS
Width - 12.00 in. (30.40 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 12 oz (340.5 gm)
Word Size
8 bits
Memory Size
Electrical Characteristics
Sockets for up to 16K bytes. Memory maybe added in
1K-byte increments.
DC Power Requirements
wiihout
Memory
Compatible Intel Memory
+sv
-SV
+12V
EPROM - 2708
O.7SA
-
With 2608
Typ
O.77A
O.OOlA
O.SBA
With 2708
Max
Typ
Max
O.79A
O.010A
O.96A
O.BSA
O.4BA
O.BOA
O.91A
O.7SA
1.04A
Interface
All address, data, and command signalS are TTL compatible and iSBC 80 bus c o m p a t i b l e . '
Environmental Characteristics
Operating
Tempe~ature
- 0 ·C, to 5,5·C
Address Selection
Switches and jumpers allowing the selection of a base
address for each independent 8K block of memory, on
any 8K boundaries
Fleference Mimuals
Connectors
Manuals may be ordered from any Intel salesrepresen·
tative, distributor office or tromlntel Literature Depart·
ment, 3065 Bowers Avenue, Santa Clara, ,Calif,ornis
95051.
' ,
9800265A - iSBC 416 Hardware Reference Manual
(!'lOT SUPPLIED)
Edge Connector - 86:pin double-sided PC edge connector with 0.156-in. (0.40 cm) contact centers.
Mating Connector - Viking 3KH43/9AMK12
ORDERING INFORMATION
Part Number
Description
SBC 416
16K EPROM Expansion Board
7-36
AFN.()()274A
iSBC™ 464
64K BYTE EPROM EXPANSION BOARD
• Switch selectable base address on 4K
byte boundaries for each memory bank
• Provides EPROM/ROM expansion of
iSBC™ 80, iSBC™ 86 and iSBC™ 88
systems via direct MULTIBUS
interface
• Assignable anywhere within a 1
megabyte address space
• EPROM components which are not
enabled are placed in standby power
mode
.
• Sockets for up to 64K bytes of EPROM
• Compatible with Intel® 2758, 2716 or
2732/2732A erasable PROMs
• Requires a single + 5V power supply
The iSBC 464 is a member of Intel's complete line of iSBC memory and 1/0 expansion boards. The iSBC 464 board interfaces directly to the iSBC 80, iSBC 86 or iSBC 88 single board computers via the MULTIBUS system bus, to expand
system EPROM memory capacity.
7-37
AFN·01283A
iSBC 464
FUNCTIONAL DESCRIPTION
Memory Configuration
Memory Banks - When used in the 8 bit mode, the iSBC
464 board is organized into four banks (labeled A-D) of
four sockets each. Depending on the type of memory
components used, each bank may contain a maximum of
4K, 8K or 16K bytes of memory. Unused memory sockets
may be deselected by bank or individually in bank D. Deselecting a bank or individual socket frees that address
space for use elsewhere in the system. In the 1618 bit
mode, banks A & Band C & D are paired together to form
two banks (labeled AB, CD) which are 16 bits wide. Each
of these banks has four socket pairs. Bank AB may be
deselected as a single unit. Socket pairs in bank CD may
be deselected individually. Thus, board configurations
using fewer than 16 memory components do not fill
memory address space with unused sockets. Selectionl
deselect ion is accomplished by setting switches on the
board.
The iSBC 464 board contains sixteen sockets which provide a maximum of 64K bytes of memory expansion. The
actual capacity of the board is determined by the type
and quantity of EPROM components installed by the
user; The board is compatible with three different sizes
of Intel EPROM devices. These are the 1Kbyte 2758
EPROM, the 2K byte 2716 EPROM, and the 4K byte 2732
EPROM.
Mode of Operation - The iSBC 464 board can operate in
one of two modes: the 8 bit only mode or the Hi/8 bit
mode. The 8 bit mode provides the most efficient
memory configuration for systems handling 8 bit data.
The 1618 bit mode allows 16 bit words to be accessed by
16 bit processors. In the 1618 bit mode, 16 bit and 8 bit
microprocessors may also access either the high order
byte or the low order byte of a 16 bit word. The mode of
operation is selected by placing two option jumper
blocks in the appropriate sockets.
20
ADDRESS
SELECTION
LOGIC
Memory Access Time - The iSBC 464 board operates
with one of 15 switch selectable memory access times
ranging from 35 to 1435 nanoseconds. This feature
allows the board to be tailored to the performance of the
installed components and the system CPU.
SOCKETS FOR
16K132K164K BYTES
OF EPROM MEMORY
16
EVEN ADDRESS
DATA BYTES
1I
I
I
MULTIBUS
INTERFACE
LOGIC
I
I
CONTROL
LOGIC
I
I
I
I
I
I
I
L_
ADDRESS
LINES 20
ODD ADDRESS
DATA BYTES
8
----
8
---l
I
I
I
I
I
I
I
I
I
I
I
_J
MULTIBUSTM
Figure 1. ISBC 464 Block Diagram
7-38
AFN·01283A
iSBC 464
their active level power with no degradation in access
time. The iSBC 464 board is designed so that only two
memory components are enabled during a read operation.
Memory Addresses
Switch selectable options on the ISBC 464 board allow
the board to be assigned anywhere within a 1 megabyte
address space. In either operating mode, the base address of each memory bank may be set to any 4K byte
boundary within a 64K byte memory page. There is one
exception. If the 4K byte devices are used in the 16/8 bit
mode, then base addresses are restricted to 8K byte
boundaries. If the board is used in a system with an
address range greater than 64K bytes, memory on the
iSBC 464 board may reside in one or two 64K byte memo
ory pages. Any two pages out of a possible 16 may be
chosen by setting switches on the board.
RAM Overlap
Memory banks of the iSBC 464 board can be overlapped
with the addresses of system RAM by setting on·board
switches. The process of addressing a memory bank will
drive the Inhibit RAM (INH1/) signal true. This signal is
Issued to the MULTIBUS system bus in order to prevent
any MULTIBUS accessable RAM in the system from responding to the current address. If an EPROM is addressed which has its corresponding RAM overlap
switch on, an access time of 15 clock cycles is imposed.
This allows overlapped dynamic RAM to refresh before
the address on the MULTIBUS is changed. The RAM
overlap feature does not apply to RAM which is not on
the MULTIBUS system bus.
Standby Power Operation
The iSBC 464 board takes advantage of the standby
modes of the Intel 2758, 2716 and 2732. When they are
not enabled, these components draw as little as 25% of
Mating Connector - Viking 3KH43/9AMK12 or compatible connector
SPECIFICATIONS
Word Size
Physical Characteristics
8 bits or 16 and 8 bits
Memory Size
Sockets are provided for up to 16K bytes in 1K increments or 32K bytes in 2K increments or 64K bytes in 4K
increments
Length - 30.48 em (12 in.)
Height - 17.15 em (6.75 in.)
Depth - 1.27 em (0.5 in.)
Weight - 294 gm (10.5 oz) without EPROM
Environment
Compatible Intel® Memory
EPROM -
Operating Temperature - O·C to + 55·C
Relative Humidity Limits - < 90% non·condensing
2758 or 2716 or 2732
INTERFACE - All 20 address, 16 data, and 6 control
signals are TIL compatible and Intel MULTIBUS com·
patible
Reference Manual
9800643A - iSBC 464 Memory Expansion Board Hardware Reference Manual (NOT SUPPLIED)
Electrical Characteristics
Manuals may be ordered from any Intel sales represen·
tative, distributor office or from Intel Literature Depart·
ment, 3065 Bowers Avenue, Santa Clara, California
95051.
DC Power (max)
VCC: +5V DC ±5%
ICC: 1.1 amps without EPROMs
ICC: '/.6 amps with (16) 2716s or 2758s
ICC: 1.3 amps with (16) 2732s or 2732As
ORDERING INFORMATION
Connectors
Bus - 86-pin double-sided PC edge connector with 0.40
cm (0.156 in.) contact centers
7-39
Part Number
Description
SBe 464
64K EPROM Expansion Board
AFN·01283A
Digital 110 Expansion
and Signal
Conditioning Boards
8
inter
iSBCTM 337
MULTIMODULETM NUMERIC
DATA PROCESSOR
• Extends host CPU instruction set with
arithmetic, logarithmic, transcendental
and trigonometric instructions
• High speed fixed and floating point
functions for iSBC 86, 88 and iAPX 86,
88 systems
.
• MULTIMODULE option containing 8087
Numeric Data Processor
• 50 x performance improvements in
Whetstone benchmarks over iAPX 86110
performance
• Supports seven data types including
single and double precision integer and
floating point
• Software support through ASM·86/88
Assembly Language and High Level
Languages
• Implements proposed IEEE Floating
Point Standard for high accuracy
The Intel iSBC 337 MULTIMODULE Numeric Data Processor offers high performance numerics support
for iSBC 86 and iSBC 88 Single Board Computer users, for applications including simulation, instrument
automation, graphics, signal processing and business systems. The coprocessor interface between the
8087 and the host CPU provides a simple means of extending the instruction set with over 60 additional
numeric instructions supporting six additional data types. The data formats conform to the proposed
IEEE Floating Point Standard insuring highly accurate results. The MULTIMODULE implementation
allows the iSBC 337 module to be used on all iSBC 86 and iSBC 88 Microcomputers and can be added as
an option to custom iAPX 86 and iAPX 88 board designs.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Index, Intel, MULTIBUS, AMX, iRMX, UPI, ICE, iS8C, iSBX, MULTIMODULE,
iAPX and ieS. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied.
©
I~TELCORPORATION,
1981
8-1
June, 1981
143087.01
iSBC 337
socket, installing the iSSC 337 processor into the
host's CPU socket, and reinstalling the host CPU
chip into the socket provided for it on the iSSC
337 processor (see Figure 1). All synchronization
and timing signals are provided. via the coprocessor interface with the host CPU.Thetwo
processors also share a common address/data
bus. (See Figure 2.) The 8087 Numeric Data Processor (NDP) component is capable of recognizing and executing 8087 numeric instructions as
they are fetched by the host CPU. This interface
allows concurrent processing by the host CPU
and the 8087. It also allows 8087 and host CPU instructions to be intermixed in any fashion to provide the maximum overlapped operation and the
highest aggregate performance.
OVERVIEW
The iSSC 337 MULTIMODULE Numeric Data Processor provides arithmetic and logical instruction
extensions to the 8086 and.8088 CPU's of the
iAPX 86 and iAPX 88 families, to provide
iAPX 86/20 and iAPX 88/20 Numeric Data Processors. The instruction set cOMists of arithmetic,
transcendental, logical, trigonometric and exponential instructions .which can all operate on
seven different data types. The data types are 16,
32, and 64 bit integer, 32 and 64 bit floating point,
18 digit packed SCD and 80 bit temporary.
Coprocessor Interface
The coprocessor interface between the host CPU
(8086 and 8088) and the iSeC 337 processor provides easy to use and high performance math processing. Installation of the iSSC 337 processor is
simply a matter of removing the host CPU from its
High Performance and Accuracy
The 80-bit wide internal registers and data paths
contribute significantly to high performance and
CONNECTOR FOR
INTERRUPT REQUEST
FROM Isec 337
MODULE
iSBC or IAPX 86 or 88 BOARD
Figure 1. IS Be 337 Module Installation
8-2
AFN..()1654A
iSCB 337
CPU overhead. Once started, the 8087 can process
in parallel with and independent of the host CPU.
For resynchronization, the NDP's BUSY signal informs the CPU that the NDP is executing an instruction and the CPU WAIT instruction tests this
signal to insure that the NDP is ready to execute
subsequent instructions. The NDP can interrupt
the CPU when it detects an error or exception. The
interrupt request line is routed to the CPU through
an 8259A Programmable Interrupt Controller. This
interrupt request signal is brought down from the
iSBC 337 module to the iSBC 86, 88 Single Board
Computer through a single pin connector (see
Figure 1). The signal is then routed to the interrupt
matrix for jumper connection to the 8259A Interrupt Controller. Other iAPX 86 and 88 designs may
use a similar arrangement, or by masking off the
8086's "READ" pin from the iSBC 337 socket, provisions are made to allow the now vacated pin of
the host's CPU socket to be used to bring down
minimizes the execution time difference between
single and double precision floating point formats. This 80-bit architecture, in conjunction with
the use of the proposed IEEE Floating Point Standard provides very high resolution and accuracy.
This precision is complemented by extensive exception detection and handling. Six different
types of exceptions can be reported and handled
by the 8087. The user also has control over internal precision, infinity control and rounding control.
SYSTEM CONFIGURATION
As a coprocessor to an 8086 or 8088, the 8087 is
wired in parallel with the CPU as shown in Figure
2. The CPU's status and queue status lines enable
the NDP to monitor and decode instructions in
synchronization with the CPU and without any
ADDRESS/DA TA BUS.
ADOA/DATA
808S
OR
8088
HOST CPU
CLK(S MHz)
8284A
READY
STATUS LINES
CLOCK
GEN.
RESET
STATUS
TEST
r-
-
-
as
RO/GT
_.
--- -
---,
I
I
I
I
I
I
I
-
I
I
BUSY
I
as
RO/GT
I
STATUS
I
I
I
ADDRIDATA
I
I
I
I
I
I
I
I
I
;--
.
8067
NDP
I
I
I
I
I
IL _ _ _ _ ...,
ISBC 337
MODULE
I
I
I
L _____________________
ERROR OR EXCEPTION
INTERRUPT
(To 8259A Inlerr upl
Controller)
I
~
Figure 2. iSBC 337 System Configuration
8-3
AFN-01654A
iSBC 337
Table 1. 8087 Datatypes
Most Significant Byte
Range
Preci·
sion
Word Integer
104
16 Bits
1'5
Short Integer
109
32 Bits
131
Long Integer
10'9
64 Bits 163
Packed BCD
10'8
Short Real
10±38
24 Bits
S IE7 Eol F,
Long Real
10±308
53 Bits
S IE,o
Temporary Real
10±4932
64 Bits
S IE'4
Data
Formats
Note:
Integer: I
Fraction: F
Exponent: E
7
18 Digits S I -
07
07
07
07
07
07
07
07
Two's Complement
loJ
loJ
Eo I F,
F521
Eo I Fo
Bias = 127 for Short Real
1023 for Long Real
16i383 for Temp Real
Table 2. Execution Time for Selected 8087 Actual
and Emulated Instructions
PROGRAMMING INTERFACE
Computations in the 8087 use the processor's
register stack. These eight 80-bit registers provide
the equivalent capacity of 40 16·bit registers. The
8087 register set can be accessed as a stack, with
instructions operating on the top stack element,
or as a fixed register set, with instructions operating on explicitly designated registers.
Table 3 lists the 8087's instructions by class. Assembly language programs are written in ASM
86/88, the iAPX 86, 88 assembly language. Table 2
gives the execution times of some typical numeric
instructions and their equivalent time on a 5 MHz·
8086.
Fo Implicit
F63J
Floating Point Instruction
Table 1 lists the seven data types the 8087 supports and presents the format for each type.
Internally, the 8087 holds all numbers in the temporary real format. Load and store instructions
automatically convert operands represented in
memory as 16-, 32-, or 64-bit integers, 32- or 64-bit
floating point numbers or 18-digit packed BCD
numbers into temporary real format and vice
versa.
Dol
Fo Implicit
F23 1
the interrupt request signal for connection to the
base board and then to the 8259A. Another alternative is to use a wire to establish this connection.
Two's
Complement
10 ,
0 ,6 1
Sign: S
BCD Digit (4 Bits): 0
0
Two's Complement
10 I
10 ,7
07
Add/Subtract Magnitude
Multiply (single precision)
Multiply (extended precision)
Divide
Compare
Load (double precision)
Store (double precision)
Square Root
Tangent
Exponentiation
Approximate Execution
Time (microseconds)
8087
8086
(5 MHz Clock) Emulation
14/18
19
27
39
9
10
21
36
90
100
1,600
1,600
2,100
3,200
1,300
1,700
1,200
19,600
13,000
17.100
FUNCTIONAL DESCRIPTION
The NDP is internally divided into two processing
elements, the control unit (CU) and the numeric execution unit (NEU), providing concurrent operation
of the two units. The NEU executes all numeric instructions, while the CU receives and decodes instructions, reads and writes memory operands and
executes processor control instructions.
Control Unit
The CU keeps the 8087 operating in synchronization with its host CPU. 8087 instructions are intermixed with CPU instructions in a single instrucAFN·01654A
iSBC 337
Table 3. 8087 Instruction Set
Data Transfer Instructions
Arithmetic Instructions
Real Transfers
Addition
load real
FLD
FST
FSTP
FXCH
Store real
Store real and pop
Exchange registers
FADD
FADDP
FIADD
Add real
Add real and pop
Integer add
Subtraction
Integer Transfers
Integer load
Integer store
Integer store and pop
FILD
FIST
FISTP
Packed Decimal Transfers
FBLD
FBSTP
FSUB
FSUBP
FISUB
FSUBR
FSUBRP
FISUBR
Subtract real
Subtract real and pop
Integer subtract
Subtract real reversed
Subtract real reversed and pop
Integer subtract reversed
FMUL
FMULP
FIMUL
Multiply real
Multiply real and pop
Integer multiply
FDIV
FDIVP
FIDIV
FDIVR
FDIVRP
FIDIVR
Divide real
Divide real and pop
Integer divide
Divide real reversed
Divide real reversed and pop
Integer divide reversed
FSQRT
FSCALE
FPREM
FRNDINT
FXTRACT
FABS
FCHS
Square root
Scale
Partial reminder
Round to integer
Extract exponent and signiflcand
Absolute value
Change sign
Multiplication
Packed de.elmal (BCD) load
Packed decimal (BCD) store and pop
Comparison Instructions
Division
FCOM
FCOMP
FCOMPP
FICOM
FICOMP
FTST
FXAM
Compare real
Compare real and pop
Compare real and pop twice
Integer compare
Integer compare and pop
Test
Examine
Processor Control Instructions
FINIT/FNINIT
Initialize processor
FDISI/FNDISI
Disable Interrupts
FENIIFNENI
Enable interrupts
FLDCW
Load control word
FSTCW/FNSTCW
Store control word
FSTSW/FNSTSW
Store status word
FCLEXlFNCLEX
Clear exceptions
FSTENV/FNSTENV Store environment
FLDENV
Load environment
FSAVEiFNSAVE
Save state
FRSTOR
Restore state
FINCSTP
Increment stack pOinter
FDECSTP
Decrement stack pointer
FFREE
Free register
FNOP
No operation
FWAIT
CPU wait
Other Operations
Transcendental Instructions
FPTAN
FPATAN
F2XM1
FYL2X
FYL2XP1
Partial tangent
Partial arctangent
2"-1
Y'log,x
Y.'092(X+ 1)
tion stream. The CPU fetches all instructions from
memory; by monitoring the status signals emitted
by the CPU, the NDP control unit determines
when an 8086 instruction is being fetched. The CU
taps the bus in parallel with the CPU and obtains
that portion of the data stream.
instruction is a load, the CU additionally captures
the data word when it becomes available on the
local data bus. If data required is longer than one
word, the CU immediately obtains the bus from the
CPU using the request/grant protocol and reads the
rest of the information in consecutive bus cycles.
In a store operation, the CU captures and saves the
store address as in a load, and ignores the data
word that follows in the "dummy read" cycle.
When the 8087 is ready to perform the store, the CU
obtains the bus from the CPU and writes the
operand starting at the specified address.
After decoding the instruction, the host executes all
opcodes but ESCAPE (ESC), while the 8087 executes only the ESCAPE class instructions. (The
first five bits of all ESCAPE instructions are identical). The CPU does provide addressing for ESC instructions, however.
Numeric Execution Unit
An 8087 instruction either will not reference memory, will require loading one or more operands from
memory into the 8087, or will require storing one or
more operands from the 8087 into memory. In the
first case a non-memory reference escape is used
to start 8087 operation. In the last two cases, the
CU makes use of a "dummy read" cycle initiated by
the CPU, in which the CPU calculates the operand
address and initiates a bus cycle, but does not capture the data. Instead, the CPU captures and saves
the address which the CPU places on the bus. If the
The NEU executes all instructions that involve the
register stack; these include arithmetic, logical,
transcendental, constant and data transfer
instructions. The data path in the NEU is 80 bits
wide (64 fraction bits, 15 exponent bits and a sign
bit) which allows internal operand transfers to be
performed at very high speeds.
When the NEU begins executing an instruction, it
activates the 8087 BUSY signal. This signal is
8-5
AFN.Q1654A
iSBC 337
Status Word
used in conjunction with the CPU WAIT instruction to resynchronize both processors when the
NEU has completed its current instruction.
The status word shown in Figure 4 reflects the overall state of the 8087; it may be stored in memory and
then inspected by CPU code. The status word is a
16-bit register divided into fields as shown in Figure
4. The busy bit (bit 15) indicates whether the NEU is
executing an instruction (B = 1) or is idle (B = 0).
Several instructions which store and manipulate the
status word are executed exclusively by the CU, and
these do not set the busy bit themselves.
Register Set
The 8087 register set is shown in Figure 3. Each of
the eight data registers in the 8087's register stack
is 80 bits wide and is divided into "fields" corresponding to the NDP's temporary real data type.
The register set may be addressed as a push down
stack, through a top of stack pointer or any register
may be addressed explicitly relative to the top of
stack.
DATA FIELD
EXPONENT
SIGN
The four numeric condition code bits (CO-C3) are
similar to the flags in a CPU: various instructions update these bits to reflect the outcome of NDP operations.
TAG FIELD
.--
SIGNIFICAND
Bits 14-12 of the status word point to the 8087
register that is the current top-of-stack (TOP).
I--I--I---
Bit 7 is the interrupt request bit. This bit is set if
any unmasked exception bit is set and cleared
otherwise.
I---
I--I--I--15
0
CONTROL REGISTER
----
Bits 5-0 are set to indicate that the NEU has detected an exception while executing an instruction.
Tag Word
STATUS REGISTER
INSTRUCTION POINTER
I-
The tag word marks the content of each register
as shown in Figure 5. The principal function of the
tag word is to optimize the NDP's performance.
The tag word can be used, however, to interpret
the contents of 8087 registers.
DATA POINTER
Figure 3. 8087 Register Set
15
I
B
I
c,
ITO
pic,
I
~,
I
c,
IIR
I
X I PE I UE
I
OE I ZE
I
DE liE I
l
EXCEPTION FLAGS (1 = EXCEPTION HAS OCCURRED)
INVALID OPERATION
DENORMAL1ZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT REOUEST
(1)
CONDITION, CODE
TOP OF STACK POINTER
(2)
NEU BUSY
(1) IR Is set it 8'lY unmasked exception bit is set, cleared otherwise.
(2)
Top Values:
000 = Register 0 is Top at Stack.
001 = Register! is Top of Stack.
111 = Register 7 is Top of Stack.
Figure 4. 8087 Status Word
8-6
AFN-01654A
iSBC 337
Exception Handling
The 8087 detects six different exception conditions
that can occur during instruction execution. Any or
all exceptions will cause an interrupt if unmasked
and interrupts are enabled.
TAG VALUES:
00 = VALID
01 = ZERO
10 = SPECIAL
11 = EMPTY
If interrupts are disabled the 8087 will simply suspend execution until the host clears the exception.
If a specific exception class is masked and that exception occurs, however, the 8087 will post the exception in the status register and perform an on-chip
default exception handling procedure, thereby
allowing processing to continue. The exceptions
that the 8087 detects are the following:
Figure 5. 8087 Tag Word
Instruction and Data Pointers
The instruction and data pointers (see Figure 6)
are provided for user-written . error handlers.
Whenever the 8087 executes an NEU instruction,
the CU saves the instruction address, the operand
address (if present) and the instruction opcode.
The 8087 can then. store this data in memory .•
15
1. INVALID OPERATION: Stack overflow, stack
underflow, indeterminate form (010, - , etc.)
or the use of a Non-Number (NAN) as an
operand. An exponent value is reserved and any
bit pattern with this value in the exponent field
is termed a Non-Number and causes this exception. If this exception is masked, the 8087's
default response is to generate a specific NAN
called INDEFINITE, or to propagate already existing NANs as the calculation result.
0
INSTRUCTION POINTER (15,0)
INSTRUCTION POINTER
(19·16)
I I
0
INSTRUCTION OPCODE (10,0)
DATA POINTER (15·0)
DATA POINTER (19·16)
0
I
Figure 6. 8087 Instruction and Data Pointers
Control Word
The NDP provides several processing options which
are selected by loading a word from memory into
the control word. Figure 7 shows the format and encoding of the fields in the control word.
2. OVERFLOW: The result is too large in
magnitude to fit the specified format. The 8087
will generate the code for infinity if this exception is masked.
15
I
xx
X
II C I
R C I
P C I M I
x
I I
PM
UM 1 0M
I I
ZM
DM 11M
I
I
EXCEPTION MASKS (1 = EXCEPTION IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT MASK (1 = INTERRUPTS ARE MASKED)
PRECISION CONTROL
II.
ROUNDING CONTROL I2f
INFINITY CONTROL (0 = PROJECTIVE. 1 =AFFINE)
(RESERVED)
(I!
Precision Control
00=24 bits
01 = Reserved
10=53 bits
11 =64 bits
It)
Rounding Control
00 = Round to Nearest or Even
01 = Round Down (Ioward . )
10 = Round Up (toward + )
11 = Chop (truncate toward zero)
Figure 7. 8087 Control Word
8-7
AFN·01654A
iSBC337
3. ZERO DIVISOR: The divisor is zero while the
6. INEXACT RESULT: If the true result is not ex,
actly representable in the specified format, the
result is rounded according to the rounding
mode, and this flag is set. If this exception is
masked, processing will simply continue.
dividend is a non-.iilfinite, non-zero number.
Again, the 8087 will generate the code for infinity if this exception is masked.
4. UNDERFLOW: The result is non-zero but too
small in magnitude to fit in the specified format. If this exception is masked the 8087will
denormalize (shift right) the fraction until the
exponent isin range. This process is called
gradual underflow.
SOFTWARE SUPPORT
5. DENORMALIZED OPERAND: At least one of
the operands or. the result is denormalized; it
has the smallest exponent but a: non-zero
significand. Normal processing continues if
this. exception i~ masked off.
The iSBC 337 module is supported by Intel's
ASM-86/88. Assembly Language andPUM-86/88
Systems Implementation Language. In addition to
the instructions provided in the languages to support the additional math functions, a software
emulator is also available to allow the execution
of iAPX 86/20 instructions without the need for the
iSBC 337 module. This allows for the development
of software in an environment without the iAPX
86/20 processor and then transporting the code to
its final run time environment with no change in
mathematical results.
SPECIFICATIONS
Environmental Characteristics
Operating Temperature -
Physical Characteristics
0 DC to 55 DC
Free air moving across base board and iSBC 337
module.
Width - 5.33 cm (2.100")
Length - 5.08 cm (2.000 ")
Height - 1.82 cm ( .718")
iSBC 337 board +
host bOard
Relative Humidity densation.
Weight - 17.33 grams (.576 oz.)
Reference Manual
Electrical Characteristics
142887·001 - iSBC 337 MULTIMODULE Numeric
Data Processor Hardware Reference Manual (NOT
SUPPLIED)
Manuals may be ordered from any Intel sales repre'
sentative, distributor office, or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.
DC Power Requirements (8087 only)
Vee = 5V ± 5%
Icc = 475 mA max.
ORDERING INFORMATION
Part Number
SBC 337
Up to 90% R.H. without con-
Description
MULTIMODULE Numeric Data
Processor·
8-8
iSBX 488™
GPIB MULTIMODULE BOARD
• Complete IEEE 488·1978 talkerllistener
functions including:
- Addressing, handshake protocol,
s~rvice request, serial and parallel
polling schemes
• Software functions built into VLSI
hardware for high performance, low
cost and small size
• Standard iSBX™ Bus interface for easy
connection to Intel iSBC™ boards
.
• Complete IEEE 488·1978 controller
functions including:
- Transfer control, service requests
and remote enable
• IEEE 488·1978 standard electrical in·
terface transceivers
• Simple read/write programming
• Five volt only operation
The Intel iSBX 488 GPIB Talker/Listener/Controller Multimodulebbard provides a standard interface from
any Intel iSBC board equipped with an iSBX connector to over 600 instruments and computer peripherals
that employ the use of the IEEE 488-1978 standard (General Purpose Interface Bus). The single-wide iSBX
488 Multimodule board implements the complete IEEE 488-1978 Standard Digital Interface for Programmable Instrumentation by taking full advantage of Intel's VLSI technology. The iSBX 488 Multimodule
board incorporates the 8291A GPIB Talker/Listener, 8292 GPIB Controller and two 8293 GPIB Transceiver
devices on a single low cost 3.7" by 2.85" iSBX Multimodule board. The iSBX 488 board represents a
significant step forward in joining microcomputers and instrumentation using industry standards such as
the Multibus system blJs, iSBX bus and IEEE 488-1978. The high performance iSBX 488 Multimodule board
mounts easily on Intel iSBX bus compatible single board computers and provides functions which
previously required aboard eight times its size.
The iSBX 488 board provides a simple programming interface to the user for easy reading, writing and
monitoring of all GPIB functions. The intelligent interface provided by the iSBX 488 board minimizes the
impact of the host processor bandwidth.
The following are trademarks of Intel Corporation and may be .used only to describe Intel products: Inlel, MULTIBUS, iRMX, iSSe, iSBX, MULTIMODULE, les and iEBC, and the
combination of MeS, ICE, iRMX, ISSC, ISeX, les or JEBC, and a numerical suffix. InteJ Corporation assumes no responsibility for the use of any circuitry other than circuitry
embodied in an Intet product. No other circuit patent licenses are implied.
©INTELCORPORATION,1981
8-9
AP~~~;:~
iSBX 488™
handshaking techniques for very high speed
transfers.
FUNCTIONAL DESCRIPTION
The iSBX 488 Multimodule board is a single-wide
iSBX bus compatible I/O expansion board that
provides a complete implementation of the IEEE
488-1978 Standard Digital Interface for Programmable Instrumentation. The iSBX 488 Multimodule board may be configured to be a GPIB
controller, talker, listener or talker/listener. The
hardware implementation of the iSBX 488 board
takes full advantage of Intel's VLSI capability by
using the Intel 8292 GPIB controller, 8291A
talkerllistener and two (2) 8293 bus transceivers.
All communication between the host iSBC board
and the iSBX 488 Multimodule board is executed
via the Intel standard iSBX connector. Many of the
functions that previously were performed by user
software have been incorporated into VLSI hardware for high performance and simple programming. Both the Intel 8291A GPIB Talker/Listener
device and the· 8292 device can each communicate independently with the host proces~or
on the iSBC board depending on configuration.
Communication from the host iSBC board to
either device on the iSBX 488 board is flexible and
maybe either interrupt or poll driven depending
on user requirements. Data transfers to or from
the GPIB may be executed by the. host processor's
I/O Read and 110 Write commands or with DMA
DEVICE
FUNCTION
I
I
I
GPIB Talker/Listener Capabilities
The Intel 8291A device on theiSBX 488 Multimodule .board handles all talkerliistener communications between the .host iSBC processor
board and the GPIB. Its capabilities include data
transfer, bus handshake protocol, talker/listener
addressing procedures, device clearing and triggering, service requests, and both serial and
parallel polling schemes. In executing most procedures the iSBX 488 board does not interrupt the
microprocessor on the iSBC processor board
unless a byte of data is waiting on input or a byte
is sent to an empty output buffer, thus offloading
the host CPU of GPIB overhead chores.
SIMPLE PROGRAMMING INTERFACE - The
GPIB talker/listener functions can be easily.programmed using the high level commands made
available by the Intel 8291A on .the iSBXA88
Multimodule board. The 8291A device arc~itecture
includes eight registers for input and eight
registers for output One each of these read and
write registers is used for direct data transfers.
The remaining write registers are used by the pro-
TRANSCEIVER
& SUPPORT
LOGIC
GPIB INTERFACE
FUNCTIONS
GPIB·
I
iSBX".
I
CONNECTOR:
DATA
8293
XCVR
P1 r--,------~~
TRANSFER
J1
ADDRESS.
SELECT.
IOR/W
MGMT.
SYSTEM
CONTROL
JUMPER
LOGIC
TALKER
LISTENER
ADDRESS
Figure 1_ iSBX 488™ Multimodule Board Block Diagram
8-10
inter
iSBX 488™
grammer to control the various interface features
of the Intel 8291A device. The remaining read
registers provide the user with a monitor of GPIB
states, bus conditions and device status.
Intel 8041 A eight bit microcomputer that has been
preprogrammed to implement all IEEE 488-1978
controller functions. The internal RAM in the
8041A is used as a special purpose register bank
for the 8292 GPIB Controller. Just as with the
8291A GPIB Talker/Listener device, these
registers are used by the programmer to implement controller monitor, read and write commands on the GPIB.
SOFTWARE FUNCTIONS BUILT INTO VLSI
HARDWARE - Additional features that have
migrated from discrete logic and software into
Intel VLSI incl ude programmable data transfer
rate and three addressing modes that allow the
iSBX board to be addressed as either a major or a
minor talkerllistener with primary or seconqary addressing. The iSBX 488 Multimodule board can be
programmatically configured into almost any bus
talker, listener, or talkerllistener configuration.
Writing software to control these and other iSBX
488 board functions is simply a matter of reading
or writing the control registers.
When configured as a bus controller the iSBX 488
board will respond to Service Requests (SRO) and
will issue Serial Polls. Parallel Polls are also
issued to multiple GPIB instrument devices for
receiving simultaneous responses. In. applications requiring multiple bus controllers, several
iSBX 488 boards may each be configured as a con·
troller and pass the active control amongst each
other. An iSBX 488 board configured for a System
Controller has the capability to send Remote
Enable (REN) and Interface Clear (IFC) for initializing the bus to a known state.
IEEE 488-1978 Functions 1
Function
Source Handshake (SH)
Acceptor Handshake (AH)
Talker (T)
Extended Talker (TE)
Listener (L)
Extended Listener (LE)
Service Request (SR)
Remote Local (RL)
Parallel Poll (PP)
Device Clear (DC)
Device Trigger (DT)
Controller (C)
iSBX 488™
Supported
IEEE Subsets
GPIB Physical Interface
SHO, SH1
AHO, AH1
TO through T8
TEO through TE8
LO through L4
LEO through LE4
SRO, SR1
RLO, RL1
PPO, PP1, PP2
DCO through DC2
DTO, on
CO through C28
The iSBX 488 Multimodule board interfaces to the
GPIB using two Intel 8293 bidirectional transceivers. The iSBX 488 board meets or exceeds all
of the electrical specifications defined in IEEE
488-1978 including the required bus termination
specifications. In addition, for direct connection
to the GPIB, the iSBC 988 cable, a 26 conductor
0.5 meter GPIB interface cable is also available
from Intel. The cable is terminated with a 26-pin
edge connector at the iSBX end and a 24-pin GPIB
connector at the other. The cable is also supplied
with shield lines for simple grounding in electrically noisy environments.
1 For detailed information refer to I EEE Standard Digital Inter·
face for Programmable Instrumentation published by The
Institute of Electrical and Electronics Engineers, Inc., 1978.
Installation
The GPIB controller functions supplied by the
iSBX 488 board are provided by the Intel 8292
GPIB controller device. The 8292 is actually an
The iSBX 488 Multimodule board plugs directly
onto the female iSBX connector available on many
Intel iSBC boards. The Multimodule board is then
secured at one additional point with nylon hardware (supplied) to insure the mechanical security
of the assembly.
SPECIFICATIONS
Physical Characteristics
Interface Information
Width - 3.70 in (.94 cm)
Length - 2.85 in (7.24 cm)
Height - 0.8 in (2.04 cm)
Weight - 3.1 oz (87.8 gm)
Controller Capabilities
iSBXTM Bus - All signals TTL compatible
26-pin edge connector - Electrical levels compatible with IEEE 488-1978.
8-11
AFN-01923A
iSBX488™
GPIB Data Rate*
GPIB Electrical and
Mechanical Specifications
300K bytes/sec transfer rate with DMA host iSBC
board
Conforms to IEEE 488·1978 standard electrical
levels and mechanical connector standard when
purchased with the iSBC 988 GPIB cable.
50K bytes/sec transfer rate using programmed I/O
730 nsec Data Accept Time
Environmental Characteristics
• Data rates are iSeX board maximum. Data rates will vary
and can be slower depending on host iSee board and user
software driver.
0° to 60°C (32° to
140°F)
Relative Humidity - Up to 90% R.H. without con·
densation . .
Operating Temperature -
Electrical Characteristics
Reference Manual
DC power requirements -
iSBX 488 GPIB Talker/Listener/Con·
troller Multimodule Board Hardware Reference
Manual (not supplied).
143154-001 -
Vee= +5 Vdc ±5%
lee=600 milliamps maximum
ORDERING INFORMATION
Part Number
Description
SBX 488
SBC 988
GPIB Multimodule
0.5 meter GPIB cable for
iSBX 488 Multimodule Board
8·12
iSBC 517
COMBINATION 110 EXPANSION BOARD
II
48 programmable I/O lines with sockets
for interchangeable line drivers and
terminators
II
Synchronous/asynchronous communications interface with RS232C drivers
and receivers
II
Eight maskable interrupt request lines
,with a pending interrupt register
II
1 ms interval timer
The iSBC 517 Combination I/O Expansion Board is a member of Intel's complete line of iSBC memory and I/O expansion boards. The board interfaces directly with any iSBC single board computer via the system bus to expand serial
and parallel I/O capacity. The combination I/O board contains 48 programmable parallel I/O lines. The system software
is used to configure the I/O lines to meet a wide variety of system peripheral requirements. The flexibility of the I/O interface is significantly enhanced by the capability of selecting the appropriate combination of optional line drivers and
terminators to provide the required sink current, polarity, and drive/termination characteristics for each application. A
programmable RS232C communications interface is provided on the iSBC 517. This interface may be programmed by
the system software to provide virtually any asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). A comprehensive RS232C interface to CRTs, RS232C compatible cassettes, and asynchronous and
synchronous modems is thus on the board. An on-board register contains the status of eight interrupt request lines
which maY,be interrogated from the system bus, and each interrupt request line is maskable under program control.
The iSBC 517 also contains a jumper selectable 1 ms interval timer and interface logic for eight interrupt request lines.
8-13
AFN·Q0304A
iSBC 517
FUNCTIONAL DESCRIPTION
Programming Flexibility
The 48 programmable I/O lines on the iSBC 517 are
implemented utilizing two Intel 8255 programmable
peripheral interfaces. The system software is used to
configure these programmable I/O lines in any of the
combinations of unidirectional input/output, and bidirectional ports indicated in Table 1. In order to take
full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable
I/O line drivers and terminators to provide the required
sink current, polarity, and drive/termination characteristics for each application. The 48 programmable I/O
lines and signal ground lines are brought out to two
50-pin edge connectors that mate with flat, round, or
woven cable. Typical I/O read access time is 280
nanoseconds. Typical I/O read cycle time is 600
nanoseconds.
Communications Interface
The programmable communications interface on the
iSBC 517 is provided by an Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART).
The USART can be programmed by the system software
to select the desired asynchronous or synchronous
serial data transmission technique (including IBM BiSync). The mode of operation (i.e., synchronous or asynchrOnous), data format, control character format, parity,
and asynchronous serial transmission rate are all under
program control. The 8251 provides full duplex, doublebuffered transmit and receive capability, and parity,
overrun, and framing error detection are all incorporated in the USART. The comprehensive RS232C interface on the board provides a direct interface to
RS232C compatible equipment. The RS232C serial data
lines and signal ground lines are brought out to a 26-pin
edge connector that mates with RS232C compatible flat
or round cables.
Interrupt Request Lines
Interrupt requests may originate from eight sources.
Four jumper selectable interrupt requests can be
automatically generated by the programmable
peripheral interface when a byte of information is ready
to be transferred to the CPU (i.e., input buffer is full) or a
character has been transmitted (i.e., output data buffer
is empty). Two jumper selectable interrupt requests can
be automatically generated by the USART when a
character is ready to be transferred to the CPU (i.e.,
receive buffer is full) or a character has been transmitted (transmit buffer is empty). These six interrupt
request lines are all maskable under program .control.
Two interrupt request lines may be interfaced directly
from user designated peripheral devices via the I/O edge
connector. An on-board register contains the status of
all eight interrupt request lines, and may be interrogated by the CPU. Each interrupt request line is
RS232C
COMPATIBLE
DEVICES
USER DESIGNATED PERIPHERALS
D
iNTERRUPT
REQUEST
LINES
U4B
PROGRAMMABLE
I/O LINES
.-------"-----,
ADDRESS BUS
L
_______
+-_~_______+--D-AT-A_B_US__
CONTROL BUS
}
(>
~~~~~~gE
Nons: INTERRUPTS ORIGINATING FROM THE PROGRAMMABLE COMMUNICATIONS INTERFACE
AND PROGRAMMABLE PERIPHERAL INTERFACE ARE JUMPER-SELECTABLE.
Figure 1. iSBC 517 Combination I/O Expansion Board Block Diagram
AFN-00304A
iSBC 517
Table 1. InputlOutput Port Modes of Operation
Mode of Operation
Unidirectional
Lines
(qty)
Ports
Input
Output
Bidirectional
Unlatched
Latched &
Strobed
Latched
Latched &
Strobed
Control
1
8
X
X
X
X
2
8
X
X
X
X
3
4
X
X
Xl
4
X
X
Xl
4
8
X
X
5
8
X
X
6
4
X
X
X2
4
X
X
X2
X
X
X
X
X
X
Note.
1. Part of port 3 must be used as control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output port
or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output
port or port 4 is used as a bidirectional port.
Interval Timer
maskable under program control. Routing for the eight
interrupt request lines is jumper selectable. They may
be ORed to provide a single interrupt request line for the
iSBC 80/10B, or they may be individually provided to the
system bus for use by other iSBC single board computers.
Each board contains a jumper selectable 1 ms interval
timer. The timer is enabled by jumpering one of the
interrupt request lines from the I/O edge connector to a
1 ms interval interrupt request signal originating from
the baud rate generator.
SPECI FICATIONS
Serial Communications Characteristics
1/0 Addressing
Synchronous - 5-8 bit characters; internal or external
character synchronization; automatic sync insertion.
Asynchronous - 5-8 bit characters; peak characters
generation; 1, 1 'I" or 2 stop bits; false start bit detectors.
Port
Address
1
2
3
4
5
8255
8255
USART USART
No.1
No.2
Data Control
Control Control
6
X4 X5 X6 X8 X9 XA
X7
XB'
XC
XD
Note
Interrupts
X is any hex digit assigned by jumper selection.
Eight interrupt request lines may originate from the programmable peripheral interface (4 lines), the USART (2
lines), or user specified devices via the I/O edge connector (2 lines) or interval timer.
1/0 Transfer Rate
Parallel - Read or write cycle time 760 ns max
Serial - (USART)
Baud Rate (Hz)
Frequency (kHz)
(Jumper Selectable)
153.6
76.8
38.4
19.2
9.6
4.8
6.98
Synchronous
38400
19200
9600
4800
6980
Interrupt Register Address
Asynchronous
(Program Selectable)
+16
+64
9600
4800
2400
1200
600
300
2400
1200
600
300
150
75
110
-
X1
XO
Interrupt mask register
Interrupt status register
Note
X is any hex digit assigned by jumber selection.
Timer Interval
1.003 ms ± 0.1 % when 110 baud rate is selected
1.042 ms ± 0.1 % for all other baud rates
8-15
AFN·OO304A
iSBC517
Interfaces
Bus Drivers
Bus - All signals TTL compatible
Parallel 1/0 - All signals TTL compatible
Serial 1/0 - RS232C
Interrupt Requests - All TTL compatible
Characteristic
Sink Current (rnA)
Data
Tri-state
50
Commands
Tri-state
25
Function
Connectors
Pins (qty)
Centers (in.)
Bus
Interface
86
0.156
CDC VPB01E4GAOOA1
Parallel ItO
50
0.1
3M 3415·000 or
TI H312125
Serial ItO
26
0.1
3M 3462·000 or
TI H312113
Auxiliary 1
60
0.1
AMP PE5·14559 or
TI H311130
Mating Connectors
Physical Characteristics
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 14 oz (397.3 gm)
Note
1. Connector heights and wire-wrap pin lengths are not guaranteed to
conform to Intel OEM or system packaging. Auxiliary connector is used
for test purposes only.
Line Drivers and Terminators
1/0 Drivers - The following line drivers and terminators
are compatible with all the I/O driver sockets on the
iSBC 517:
Driver
Characteristic
Sink Current (rnA)
7438
7437
7432
7426
7409
7408
7403
7400
I,OC
I
NI
I,OC
NI,OC
NI
I;OC
I
48
48
16
16
16
16
16
16
Note
Does not include power required for optional 1/0 drivers and 1/0 terminators. With eight 220Q/330Q input terminators installed, all ter·
minator inputs low.
Environmental Characteristics
Note
I
Electrical Characteristics
Average DC Current
Vcc= +5V ±5%
V DD = +12V ±5%
V AA = -12V ±5%
Icc = 2.4 mA max
IDD= 40 mA max
IAA = 6Q mA max
Operating Temperature -
= inverting; NI = non-inverting; OC = open-collector.
0 'C to + 55 'C
Ports 1 and 4 have 25 mA totem·pole drivers and 1 kQ
terminators.
1/0 Terminators -
Reference Manual
220Q/330Q divider or 1 kQ pull up
9800388B - iSBC 517 hardware Reference Manual (NOT
SUPPLIED)
220Q
+5V~------~~r-------.
220Q/330QL
~r.---------<'---~O iSBC 901 OPTION
1 kQ
1 kQ
+ SV - - - - - - - - - ' V V \ . - - - - - - - - - { O
iSBC 902 OPTION
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California
95051.
ORDERING INFORMATION
Part Number
Description
SBC 517
Combination I/O Expansion Board
8-16
AFN-00304A
iSBC 519 (or pSBC 519*)
PROGRAMMABLE 1/0 EXPANSION BOARD
• Jumper selectable 0.5, 1.0,2.0, or 4.0 ms
interval timer
• iSBC 1/0 expansion via direct
MULTIBUS Interface
• 72 programmable 1/0 lines with sockets
for interchangeable line drivers and·
terminators
• Jumper selectable 1/0 port addresses
• Eight maskable interrupt request lines
with priority encoded and program·
mabie interrupt algorithms
The iSBC 519 Programmable I/O Expansion Board is a member of Intel's complete line of iSBC memory and I/O expan·sion Iloards. The iSBC 519 interfaces directly to any iSBC single board computer via the system bus to expand input
and output port capacity. The iSBC 519 provides 72 programmable I/O lines. The system software is used to configure
the I/O lines to meet a wide variety of peripheral requirements. The flexibility of the I/O interface is further enhanced by
the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required
sink current, polarity, and drive/termination characteristics for each application. Address selection is accomplished
by using wire-wrap jumpers to select one of 16 unique base addresses for the input and output ports. The board operates with a single + 5V power supply.
'Same product, manufactured by Intel Puerto Rico, Inc.
8-17
AFN·0027BA
iSBC 519
FUNCTIONAL DESCRIPTION
Typical I/O read/write cycle time is 450 nanoseconds.
The interval timer provided on the iSBC 519 may be used
. to generate real time clocking in systems requiring the
periodic monitoring of I/O functions. 1he time interval is
derived from the constant.clock (BUSCCLK) and the tIming interval is jumper selectable. Intervals of 0.5,1.0,2.0,
and 4.0 milliseconds may be selected when an iSBC
single board computer is used to generate the clock.
Other timing intervals may be generated if the user provides a separate constant clock reference in the system.
The 72 programmable 1/0 lines on the iSBC 519 are implemented utilizing three Intel 8255 programmable
peripheral interfaces. The system software is used to
configure the 1/0 lines in any combination of unidirec'
tional inputloutput and bidirectional ports indicated in
Table 1. In order to take full advantage of the large
number of possible 1/0 configurations, sockets are provided for interchangeable 1/0 line drivers and terminators. The 72 programmable 1/0 lines and signal
ground lines are brought out to three 50-pin edge connectors that mate with flat, round, or woven cable.
Eight·Level Vectored Interrupt·'
An Intel 8259 programmable interrupt controller (PIC)
provides vectoring for eight interrupt levels. As shown
in Table 2, a selection of three priority processing algorithms is available to the system designer"so that the
Interval Timer
Typical 1/0 read access time is 350 nanoseconds.
Table 1. Input/Output Port Modes of Operation
Mode of Operation
Ports
Unidirectional
Lines
(qty)
Input
Latched &
Strobed
Output
Latched &
Strobed
Unlatched
1,4,7
8
X
X
X
X
2,5,8
8
X
X
X
X
3,6,9
4
X
4
BidirectiOnal
Control
Latched
X
X
:
X
X1.2.3
X
X1.2.3
No•• s
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output
port or port 1 Is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a latched and strobed output
port or port 4 is used as a bidirectional port.
3. Part of port 9 must be used as a control port when either port 7 or port B are used as a latched and strobed input or a latched and strobed output
port or port 7 is used as a bidirectional port.
.
USER DESIGNATED
PERIPHERALS
.
J
INTERRUPT
REQUEST
LINES
6
INTERRUPT
1
INTERRUPT
REQUEST.
REQUEST
LINES
LINE
ADDRESS BUS
DATA BUS
CONTROL BUS
CONSTANT CLOCK rCClK]
iS8C 80
BUS
Figure 1. iSBC 519 Programmable I/O Expansion Board Block Diagram
8·18,
AFN-00278A
iSBC 519
fable 2. Interrupt Priority Options
Algorithm
incoming requests is of the highest priority, determines
whether this request is of higher priority than the level
currently being serviced, and if appropriate, issues an
interrupt to the system master. Any combination of
interrupt levels may be masked through storage, via
software, of a single byte to the interrupt mask register
of the PIC.
Operation
Fully nested
Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.
Auto·rotating
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
Specific priority
System software assigns
lowest priority level. Priority of
all other levels are based in se·
quence numerically on this
aSSignment.
Interrupt Request Generation - Interrupt requests may
originate from 10 sources. Six jumper selectable inter·
rupt requests can be automatically generated by the
programmable peripheral interfaces when a byte of in·
formation is ready to be transferred to the system
master (I.e., input buffer is full) or a character has been
transmitted (i.e., output data buffer is empty). Three
interrupt request lines may be interfaced to the PIC
directly from user deSignated peripheral devices via the
1/0 edge connectors. One interrupt request may be gen·
erated by the interval timer.
manner in which requests are serviced may be config·
ured to match system requirements. Priority assign·
ments may be reconfigured dynamically via software at
any time during system operation. The PIC accepts
interrupt requests from the programmable parallel 1/0
interfaces, the interval timer, or direct from peripheral
equipment. The PIC then determines which of the
Bus Line Drivers - The PIC interrupt request output
line may be jumper selected to drive any of the nine in·
terrupt lines on the MULTIBUS. Any of the on· board reo
quest lines may also drive any interface interrupt line
directly via jumpers and buffers on the board.
SPECIFICATIONS
Interfaces
Addressing
Bus - All signals TTL compatible
Parallel 1/0 - All signals TTL compatible
Interrupt Requests - All TTL compatible
8255
Pori
1
2
3
Address XO XI X2
8255
No.1 4
Control
X3
5
6
X4 X5 X6
No.2
Control
X7
8255
7
8
9
X8 X9 XA
No.3
Control
Connectors
XB
Pins
(qty)
Centers
(in.)
Bus
86
0.156
Viking 3KH43/9AMK12
Parallel 110
50
0.1
3M 3415·000 or
TI H312125
Serial 110
26
0.1
3M 3462·000 or
TI H312113
Auxiliary 1
60
0.1
AMP PE5·14559 or
TI H311130
Interface
Interrupts
Register Addresses (hex notation, 1/0 address space)
XD Interrupt request register
XC In·service register
XD Mask register
XC Command register
XD Block address register
XC Status (polling register)
Note
1. Connector heights and wirewrap pin lengths are not guaranteed to
conform to Intel OEM or System packaging.
Note
Several registers have the same physical address; sequence of access and
one data bit of control word deteimines which register will respond.
Ten interrupt request lines may originate from the pro·
grammable peripheral interface (6 lines), or user
specified devices via the 1/0 edge connector (3 lines), or
interval timer (1 line).
Mating Connectors
Line Drivers and Terminators
1/0 Drivers - The following line drivers and terminators are
compatible with all the 1/0 driver sockets on the iSBC
519:
Interval Timer
Output Register - Timer interrupt register output is
cleared by an output instruction to I/O address XE or
XF1.
Timing Intervals - 500, 1,000, 2,000, and 4,000 ms
± 1 %; jumper selectable 2.
Driver
Characteristic
Sink Current (mA)
7438
7437
7432
7426
7409
7408
7403
7400
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I
48
48
16
16
16
16
16
16
Notes
1. X is any hex digit aSSigned by jumper selection.
Note
2. Assumes constant clock (CCLK) frequency of 9.216 MHz ± 1% . - -
I
8-19
= inverting; NI =
non·inverting; OC
= open·collector.
AFN'()0278A
iSBC 519
110 Terminators - 220Q/330Q divider or 1 kQ pullup
PhYSical Characteristics
Width Height Depth Weight -
220Q
+5v---'~~--:---:-----'1
~~:---~·'---o ISBC 901 OPTION
220Q/330QJ
12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
.14 oz (397.3 gm)
1 kQ
1 kQ
+ SV -----'0A~-------o
Electrical Characteristics
ISSC 902 OPTION
Ports 1,4, and 7 may use any of the drivers or terminators
shown above for unidirectional (input or output) port configurations. Either terminator and the following bidirectional drivers and terminators may be used for ports 1,4,
and 7 when these ports are used as bidirectional ports.
Average DC Current
Bidirectional Drivers
Note
NI,TS
25
I,TS
50
With Termlnatlon2
ICC = 1.5A max
3.5A max
1. Does not include power required for optional 1/0 drivers and 110 terminators.
Sink Current (rnA)
Characteristic
Without Termination 1
2. With 18 220QI330Q Input terminators installed, all terminator inputs
low.
Note
I = inverting; NI ;:;; non-inverting; TS = three-state.
Environmental Characteristics
Terminators (for ports 1, 4, and 7 when used as bidirectional ports)
Operating Temperature -
Supplier
Product Series
eTS
760·
Dale
LDP14k·02
Beckman
899·1
Reference Manual
9800385B - iSBC 519 hardware Reference Manual (NOT
SUPPLIED)
Bus Drivers
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature Department, 3065 Bowers Avenue, Santa Clara, California
95051.
Sink Current (mA)
50
25
ORDERING INFORMATION
Part Number
Description
SBC 519
Programmable I/O Expansion
Board
O·C to + 55·C
8-20
iSBC 556
OPTICALLY ISOLATED 1/0 BOARD
• iSBC 80 and MULTIBUS compatible
• Provisions for plug-in, optically isolated
receivers, drivers, and terminators
• Up to 48 digital optically isolated
input/output data lines
• Voltate/current levels
- Input up to 48V
- Output up to 30V, 60 mA
• Choice of
- 24 fixed input lines
- 16 fixed output lines
- 8 programmable lines
• Common interrupt for up to 8 sources
• +5V supply only
The iSBC 556 Optically Isolated I/O Board provides 48 digital input/output lines with isolation between process application or peripheral device and the iSSC 80 series single board computers. The iSSC 556 contains two 8255A programmable interface devices, and sockets for user supplied optically isolated drivers, receivers, and input resistor terminators, together with common interrupt logic and iSSC 80 bus interface logic. Input signals can be single-ended or
differential types with user defined input range (resistor terminator and opto-isolatedreceiver selection), allowing
flexibility in design of voltage and threshold levels. The output allows user selection of Opto-Isolated Darlington Pair
.
which can be used as an output driver either as an open collector or current switch.
8~21
AFN·00281A
iSBC 556
Table 1. 110 Ports Opto·lsolator Receivers, Drivers, and Terminators
Port No.
X=1I0 Base
Address
Lines
(qty)
Type of
1/0
Input
Output
Inputl
Control
Input
Output
Inputl }
Output Control
X+O
X+1
X+2
X+4
X+5
X+6
X+7
.-
Dual
Opto-Isolator
Resistor
Darlington
Terminator
Dual
Pair
Driver
Pac Rp
Opto·lsolator
7438
16·Pln DIP
8·Pin Dip
6·Pin DIP
Monsanto or Equivalent
Bourns
Monsanto
4N29,30
4116R·00
MCT6~
or Equivalent or Equivalent
31,32
or Equivalent
8
8
8
1
8
1 if Input
8
8
2 if output
8
8
1
8
8
-
-
4
1
-
-
4
SPECIFICATIONS
Pull·Up
ISBC 902
2 if input
Connectors
Number of Lines'
Intertaee
24 input lines
16 output lines
8 programmable lines: 4 input -
PllSBC bus
Jl 16 fixed Input &
8 fixed output lines
J2 8 fixed output, 8
fixed output, & 8
programmable
Input/output lines
4 output
1/0 Interface Characteristics
Line·to·Line Isolation - 235V DC or peak AC
Input/Output Isolation - 500V DC or peak AC
Pins
(qty)
Centers
In.
86
50
0.156
0.1
50
0.1
Mating Connectors
em
Viking 3KH4319AMKI2
3M 3415·000 or
TI M312125
3M 3415·000 or
TI M312125
Physical Characteristics
Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 12 oz (397.3 gm)
Electrical Characteristics
Average DC Current
Rp DETERMINES VOLTAGE AND CURRENT RANGE.
Vcc= +5V±5%, 1.0A without user supplied isolated
receiverldriver
Icc 1.6A max with user supplied isolator receiver/driver
Bus Interface Characteristics
=
All data address and control commands are iSeC 80
bus compatible.
110 Addressing
A
Address
Environmental Characteristics
8255 #1
Port
j
B
j
8255.2
Control
C
X+OjX+ljX+2
A
X+3
j
B
j
Temperature - O·C to 55·C
Relative Humidity - 0 to 90%, non-condensing
Control
C
X+4jX+5jX+6
X+7
Reference Manual
Where:
base address is from OOH to 1FH ijumper selectable)
9800489·02 - iSBC 556 Hardware Reference Manual
(NOT SUPPLIED)
Reference manuals are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
SBC 556
Description
Optically Isolated 110 Board
8-22
AFN·OO281A
iSBC 569
INTELLIGENT DIGITAL CONTROLLER
• Single board digital 110 controller with
up to four microprocessors to share the
digital input/output signal processing
• 2K bytes of dual port static. read/write
memory
• Sockets for up to 8K bytes of Intel 2758,
2716,2732 erasable programmable read
only memory
• 3 MHz 8085A central control processor
• Three sockets for 8041/8741 A Universal
Peripheral Interface (UPI·41A) for dis·
tributed digital I/O processing, such as:
-
• 48 programmable parallel I/O lines with
sockets for interchangeable line drivers
or terminators
Industrial signal processor
(iSBC 941)
Custom programmed 8041A18741A
• Three programmable counters
• 12 levels of programmable interrupt
control
• Single + 5V supply
• Three operational modes
.-
• MULTIBUS standard control logic
Stand·along digital controller
MULTIBUS master
Intelligent slave (slave to
MULTIBUS master)
compatible with optional iSBC80 and
iSBC 86 CPU, memory, and I/O .
expansion. boards
The Intel iSBC 569 Intelligent Digital Controller is a single board computer (8085A based) with sockets for three
8041A/8741A Universal Peripheral Interface chips (UPI-41A). The I/O processing algorithm may be·tailored to application
requirements using designer selected combinations of standard Intel industrial signal processors (e.g., iSBC 941) or user
programmed UPI-41A processors. These devices may be used to offload the 8085A processorfrom time consuming tasks
such as pulse counting, event sensing, and parallel or serial digital 110 data formatting with error checking and
handshaking. The iSBC 569 board is a complete digital controller with up to four processors on a single 6.75 inches x 12.00
inches (17.15cm x ·30.48cm) printed circuit board. The 8085A CPU, system clock, read/write memory, nonCiiolatile
memory, priority interrupt logic, programmable timers, MUL TIBUS control and interface logic;optional UPI processors
and optional line driver and terminators all reside on one board.
8-23
AFN-01270A
iSBC 569
work on the more important application programming of
machine or process optimization. Controlling the Intel
UPI-41A processors becomes a Simple task of reading or
writing command and data bytes to or from the data bus
buffer register on the UPI device. Programming the iSBC
941 Industrial Digital Processor to produce a pulse output,
for example, is as simple as sending command and
parameter bytes indicating initialization, pulse output
selection, period and delay parameters,' followed by a
command to begin execution.
FUNCTIONAL DESCRIPTION
Intelligent Digital Controller
Three modes of operation - the iSBC 569 Intelligent
Digital Controller is capable of operating in one of three
modes; stand alone controller, bus master, or intelligent
slave.
Stand alone controller - the iSBC 569 board may
function as a stand alone, single board controller with
CPU, memory, and I/O elements on a single board. Five
volt (+5VDb) only operation allows configuration of low
cost controllers with only a Single power supply
voltage. The on-board 2K bytes RAM and up to 16K bytes
ROM/EPROM, as well as the assistance of three UPI-41A
processors, allow significant digital I/O control from a
single board.
Central Processing Unit
A powerful Intel 8085A 8-bit CPU, fabricated on a single
LSI chip, is the central processor for the iSBC 569 ™
controller. The six general purpose 8-bit registers may
be addressed individually or in pairs, providing both
single and double preCision operations. The program
counter can address up to 64K bytes of memory using
iSBC expansion boards. The 16-bit stack pointer
controls the addressing of an external stack. This stack
provides sub-routine nesting bounded only by memory
size. The minimum instruction execution time is 1.30
microseconds. The 8085A CPU is software compatible
. '
with the Intel 8080A CPU.
Bus master - in this mode of operation, the iSBC 569
controller may interface with and control iSBC expansion
memory and '1/0 boards, or even other iSBC 569
Intelligent Digital Controllers configured as ,int~!,igent
slaves (but no additional bus masters).
. .i"
Intelligent slave - the iSBC 569 controller can perform as
an intelligent slave to any .8- or 16-bit MUL TIBUS master
CPU by offloading the master of digital control related
tasks. Preprocessing of data for the master is controlled
by the on-board 8085A CPU which coordinates uptothree
Upl-41A processors. Using the iSBC 569 board as an
intelligent slave, multi-channel digital control can be
managed entirely on-board, freeing a system master to
perform other system functions. The dual port RAM
metnory allows the iSBC 569 controller to process and
store data without MU LTI BUS memory contention.
Bus Structure
The iSBC 569 Intelligent Digital Controller utilizes atriple
bus architecture concept. An internal bus is used for onboard memory and I/O operations. A MUL TIBUS
interface is available to provide access for all external
memory and I/O operations. A dual port bus with
controller enables access via the third bus to. 2K bytes of
static RAM from either the on-board CPU or a system
master. Hence, common data may be stored in on-board
memory and may be accessed either by the on-board
CPU or by system masters. A block diagram of the iSBC
569 functional components is shown in Figure 1.
Simplified Programming
By using Intel UPI-41A processors for common tasks such
as counting, sensing change of state, printer control and
keyboard scanning/debouncing, the user frees up time to
Figure 1. iSBC 569 Intelligent Digital Controller Block Diagram
8-24
AFN·01270A
iSBC 569
RAM Capacity
Programmable Timers
The iSBC 569 board contains 2K bytes of read/write
memory using Intel 2114 static RAMs. RAM accesses
may occur from either the iSBC 569 controller or from any
other bus master interfaced via the MUL TIBUS system
bus. The iSBC 569 board provides addressing jumpers to
allow the on-board RAM to reside within a one megabyte
address space when accessed via the system bus. In
addition, a switch is provided which allows the user to
reserve a 1K byte segment of on-board RAM for use by the
8085A CPU. This reserved RAM space is not accessible
via the system bus and does not occupy any system
address space.
The iSBC 569 Intelligent Digital Controller board provides
three independently programmable interval timer/
counters utilizing one Intel 8253 Programmable Interval
Timer (PIT). The Intel 8253 PIT provides three 16-bit
BCD or binary interval timer/counters. Each timer may
be used to provide a time reference for each UPITM
processor or for a group of UPI processors. The output of
each timer also connects to the 8259A Programmable
Interrupt Controller (PIC) providing the capability of
timed interrupts. All gate inputs, clock inputs, and timer
outputs of the 8253 PIT are available at the I/O ports for
external access.
EPROM/ROM Capacity
Two sockets for up to 16K bytes of nonvolatile read only
memory are provided on the iSBC 569 board. Nonvolatile
memory may be added in 1K-byte increments up to a
maximum of 2K bytes using Intel 2758 erasable and
electrically reprogrammable ROMs (EPROMs); in
2K-byte increments up to a maximum of 4K bytes using
Intel 2316 ROMs or 2716 EPROMs; in 4K byte increments
up to 8K bytes maximum using Intel 2732 EPROMs; or in
8K-byte increments up to 16K bytes maximum using Intel
2364 ROMs (both sockets must contain same type
ROM/EPROM). All on-board ROM/EPROM operations
are performed at maximum processor speed.
Timer Functions - In utilizing the iSBC 569 controlier"the
systems designer simply configures, via software, each
timer to meet systems requirements. The 8253 PIT modes
are listed in Table 1. The contents of each counter may be
read at any time during system operation with simple read
operations for event counting applications. The contents
of each counter can be read "on-the-fly" for time stamping
events or time clock referenced program initiations.
Table 1. 8253 Programmable Timer Functions
Universal Peripheral Interfaces (UPI-41A)
The iSBC 569 Intelligent Digital Controller board provides
th ree sockets for user suppl ied Intel 8041 A/87 41 A
Universal Peripheral Interface (UPI-41A) chips. Sockets
are also provided for the associated line drivers and
terminators for the UPII/O ports. The UPI-41A processor
is a single chip microcomputer containing a CPU, 1K
bytes of ROM (8041A) or EPROM (8741A). 64 bytes of
RAM, 16 programmable I/O lines, and an 8-bit timer/event
counter. Special interface registers included in the chip
allow the UPI-41A processor to function as a slave
processor to the iSBC 569 controller board's 8085A
CPU. The UPI processor allows the user to specify
algorithms for controlling peripherals directly thereby
freeing the 8085A for other system functions. For
additional information, including UPI-41A instructions,
refer to the UPI-41 User's Manual (Manual No. 9800504).
Function
Operation
Interrupt on
terminal count
When terminal count is reached,
an interrupt request is generated.
Programmable
one·shot
Output goes low upon receipt of
an external trigger edge or soft·
ware command and returns high
when terminal count is reached.
This function is retriggerable.
Rate
generator
Divide by N counter. The output
will go low for one Input clock cy·
cle, and the period from one low·
going pulse to the next is N times
the input clock period.
'
Square·wave
rate generator
Output will remain high until one·
half the count has been com·
pleted, and go low for the other
half of the count.
Software
triggered
strobe
Output remains high until soft·
ware loads count (N). N counts
after count is loaded, output goes
low for one input clock period.
Hardware
triggered
strobe
Output goes low for one clockpe·
riod N counts after riSing edge on
counter trigger input. The .counter
is retriggerable.
Event counter
On a jumper selectable basis, the
clock input becomes an input
froni the external system. CPU
may read the number of events oc·
curring after the counting "win·
dow" has been enabled or an in·
terrupt may be generated after N
counts occur in the system.
Industrial Digital Processor (iSBC 941)
The iSBC 941 Industrial Digital Processor is a 40-pin DIP
device which provides the user with easy-to-use
processing of digital input and output Signals desired in
·many industrial automation environments. One of nine
digital I/O functions can be selected at anyone time for
measuring, counting, or controlling up to 16 separate I/O
lines. An additional eight utility commands allow reading
or setting the condition of unused I/O lines. Simplex
serial input and output modes can assemble or disassemble bytes transmitted asynchronously over TTL lines,
including insertion and deletion of start/stop bits. The
iSBC 941 processor plugs into any of the three UPI-41A
sockets on the iSBC 569 board. Simple programming
commands from the master 8085A processor can thus
implement up to 48 lines of preprocessed digital I/O
signals. For specific commands and further information,
refer to the iSBC 941 Data Sheet in this document.
8-25
AFN·01270A
iSBC 569
Interrupt Capability
The iSBC 569 IntelligehtDigitalControlierprovides
interrupt service for up to 12 interruptsources. Any olthe:
12 sources may interrupt the on-board processor. Four
interrupt levels are handled directly by the 8085A CPU
and eight levels are serv(ced from an' Intel 8259A
Programmable Interrupt Controller (PIC) routing an
interrupt request output to the INTR input olthe 8085A.
8085Alnterrupt ~ Each of four direct 8085A interrupt
inputs has a unique vector memory address, An 8085A'
jump instruction at each of these addresses then provides
software linkage to interrupt service routines located
independently anywhere in the memory.
8259Alnterrupts ~ The eight interrupt sources.originate
from both on-board controller functions and the system
bus:
UPI~41A Processors -cone interrupt from each.of three
UPlprocessor sockets.
8253 PIT- one interrupt from each of three timer outputs:
MUL TIBUS System Bus - one of eight MUL TIBUS
interrupt lines may be jumpered to either of two 8259A
PIC interrupt inputs.
Programmable Reset ~The iSBC 569 Intelligent Digital
Controller. board has .a. programmable output latch used
to control on-board functions. Three of the outputs are
connected to separate UPI-41A RESET inputs. 'Thus, the
user can reset anyor all of the UPI-41 Aprocessors under
softwareconnol. A fourth latch output may be used to
generate an' interrupt. request onto the MUL TIBUS
interruptlines. A fifth latch. output is connected to a lightemittingdiode which may be used for diagnostic
purposes.
Expansion Capabilities
When the iSBC 569 controller is used as a single board
digital controller, memory and I/O capacity may be
expanded using Intel MULTI BUS compatible expansion
boards .. 1n this mode,no other bus masters may be. in the
system. Memory maybe expanded to a 64K byte capacity'
by adding .user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/output
capacity may be in~reased by adding I/O expansion
boards, Multiple is'BC 569 boards may be included in an
SPECIFICATIONS
SOSSA CPU
Word Size - 8, 16 or 24 bits
Cycle Time - 1.30 Ilsec'± .1% for 'fastest executable
instruction; i.e.;foui" dock cycles.
ClockRate - 3.07 Ml1z
± .1%
System Access Time
Dual'port memory -:-725 risec.
Memory Capacity.
.
On-board ROM/EPROM -2K, 4K, 8K, or 16K bytes of
user installed ROM or EPROM
On-board RAM - 2K bytes of static RAM. Fully
expanded systemusi~g one iSBC 569 Intelligent Digital
Controll.eras the system master and additional controllers as intelligent slaves.
""
Intelligent Slave Programming
When used as an intelligentslave,the iSBC569 controller
appears as an additional RAM memory module. System
bus masters communicate with the iSBC 569 board as if it
were just an extension of system memory. To simplify
this communication, the user has been given sonie
specific tools:
Flag Interrupt - The Flag Interrupt is generated any time
a write command is performed by an off-board CPU to the
first location of iSBC 569 RAM. This interrupt provides a
means for the master CPU to notify the iSBC 569
controller that it wished to establish. a communications
sequence. The flag interrupt is cleared when the onboard processor reads the. first location of its RAM. I.n
systems with more than one intelligent slave, "the flag
interru.ptprovidesa unique interrupt to eachslave outside
the nOrmal MUL TIBUS. interrupt lines (lNTO/-INT7/).
RAM"'-- The on-board 2K byte RAM area that is accessible
to both an off~board CPU and theon-board 8085Amaybe
configured for system access on. any2K boundary ..
MULTIBUS Interrupts - The. third tool to improve systern
operation as an intelligent slave is access to the
MUL TlBUS interrupt lines. TheiSBC 569 controller can
both respond to interrupt signals from an off-board CPU,
and generate an interrupt to the off-bo"ard CPU via the
system bus.
System Development Capability
S~ftware development for the iSBC 569 Intelligent Digital
Controller board is supported by the Intellec® Micro~
computer Development System including a resident
rmicroassembler, text editor,system monitor, a linker,
object code locator, and Library Manager. In addition,
bothPLlM and FORTRAN langu~ge programsdm be
compiled to run on the iSBC 569 board. A unique incircuit emulator (ItE~85TM) option pro~ides the capability
of developing and debugging software directly on. the
iSBC 569 board. This greatly simplifies the design,
development, and' debug of iSBC 569 system software.
accessiblefromon-board 8085A.Separately addressable
from system bus.
.
.Off"board expansion ~ up to 64K bytes of E.PROM/ROM
or.RAM capacity.
I/O. Capacity.
Parallel-Timers - Three timers, with independent .gate
input, clock input,and timer output user-accessi.b.le.
Clock inputs can bestrappedtoan.external source-arto
anon-board 1.3824MHz reference. Each timer is
connected to a 8259A Programmable Interrupt Controller
and ,may also be optionally connected to UPI processors.
UPI-I/O"'- Three UPI'-41Ainterfaces;each with two 8-bit
I/O ports plus the two UPI Test Inputs. The8-bit ports are
user-configurable (as inputs or outputs) in groups of four.
AFN·01270A
iSBC 569
Serial-1 TTL compatible serial channel utilizing SID and
SOD lines of on-board 8085A CPU
Depth - 17.15 cm (6.75 inches)
Thickness - 1.27 cm (0.50 inch)
Weight - 3.97 gm (14 ounces)
On-Board Addressing
Electrical Characteristics
DC Power Requirements - + 5V
All communications to the UPI-41A processors, to the
programmable reset latch, to the timers, and to the
interrupt controller are via read and write commands from
the on-board 8085A CPU.
@ 2.58A with no optional devices installed. For each 8741 A add 135 mAo For
each 220/330 resistor network, add 60 mAo Add the following for each EPROM/ROM installed.
Memory Addressing
On-board ROMIEPROM - 0-07FF (using 2758 EPROMs);
O-OFFF (using 2716 EPROMs or 2316 ROMs); 0-1FFF (using
2732 EPROMs); 0-3FFF (using the 2364 ROMs)
On-board RAM - 8000-87FF System access - any 2K
increment 00000-FF800 (switch selectable); 1K bytes may
be disabled from bus access by switch selection.
+s.ov Current Requirement
Type
lROM
110 Addressing
Source
8253
UPIO
UPll
UPI2
PROGRAMMABLE RESET
8259A
Driver
7438
7437
7432
7426
7409
7408
7403
7400
Input frequencies - jumper selectable reference
Internal: 1.3824 MHz ± .1% (.723 !,sec, nominal)
External: User supplied (2 MHz maximum)
Output Frequencies (at 1.3824 MHz)
Min'
Max'
1.45 ",sec
47.4 msec
Rate Generator
(frequency)
21.09 Hz
691.2 KHz
2ROMS
125
125
240
55
55
mA
mA
mA
mA
mA
I/O Drivers - The following line drivers are all compatible
with the 1/0 driver sockets on the iSSC 569 Intelligent
Digital Controller.
Timer Specifications
Function
mA
mA
mA
mA
mA
Line Drivers and Terminators
Addresses
OEOH-OE3H
OE4H-OE5H
OE6H-OE7H
OE8H-OE9H
OEAH-OEBH
OECH-OEDH
Real-time
interrupt interval
100
100
120
40
40
2758
2716
2316E
2732
2364
Note
Characteristic
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I
Sink CUrrent (mA)
48
48
16
16
16
16
16
16
I;;: inverting; Nt = non-inverting: OC = open collector.
1/0 Terminators -
220!ll330fi divider or 1 kfi pullup
220Q
+5V-----::~---'
220Q/330Q-.r=
1. Single 16-bit binary count
~~.- - - - - + - - _ 0 Isac 901
OPTION
Interfaces
1kQ
MUL TIBUSTM Interface - All Signals compatible with
iSSC and MUL TISUS architecture
Parallel 1/0 - All signals TTL compatible
Interrupt Requests - All TTL compatible
Timer - All signals TTL compatible
Serial 1/0 - All signals TTL compatible
1 kQ
-----'VV'.~-------o iSBC 902 OPTION
Environmental Characteristics
Operating Temperature - DoC to 55°C (32°F to 131°F)
Relative Humidity - To 90% without condensation
Reference Manuals
Connectors
Pins
(qty)
Centers
(In.)
Mating Connectors
Bus
86
0.156
Viking' 3KH43f9AMK12
ParalielliO
50
0.1
3M 3415'()00 or
TI H312125
Inlerlace
+ 511
9800845·01 - iSBC 569 Intelligent Digital Controller
Soard Hardware Reference Manual (NOT SUPPLIED)
9803077 - iSSC 941 Digital Signal Processor User's
Guide (NOT SUPPLIED)
Reference manuals are shipped with each product only if
designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Sowers
Avenue, Santa Clara, California 95051.
Physical Characteristics
Width - 30.48 cm (12.00 inches)
ORDERING INFORMATION
Part Number
Description
SSC 569
Intelligent Digital Controller
8-27
AFN·01270A
Communication
Controllers
9
iSBC™ 534 (or pSBC 534*)
FOUR CHANNEL COMMUNICATION EXPANSION BOARD
• Serial 1/0 expansion through four pro·
grammable synchronous and asyn·
chronous communications channels
• Jumper selectable interface register
addresses
• 16·bit parallel 1/0 interface compatible
with Bell 801 automatic calling unit
• Individual software programmable
baud rate generation for each serial
1/0 channel
• RS232C/CCITT V.24 interfaces plus
20 mA optically isolated current loop
interfaces (sockets)
• Two independent programmable 16·bit
interval timers
• Programmable digital loop back for
diagnostics
• Sixteen maskable interrupt request
lines with priority encoded and pro·
grammable interrupt algorithms
• Interface control for auto answer and
auto originate modems
The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of memory and 1/0
expansion boards. The iSBC 534 interfaces directly to any single board computer via the MULTI BUS to provide expansion of system serial communications capability. Four fully programmable synchronous and asynchronous serial channels with RS232C buffering and provision for 20 mA optically isolated current loop buffering are provided. Baud rates,
data formats, and interrupt priorities for each channel are individually software selectable. In addition to the extensive
complement of EIA Standard RS232C Signals provided, the iSBC 534 provides 16 lines of RS232C buffered programmable parallel 1/0. This interface is configured to be directly compatible with the Bell Model 801 automatic calling unit.
These capabilities provide a flexible and easy means for interfacing Intel iSBC based systems to RS232C and optically
isolated current loop compatible terminals, cassettes, asynchronous and synchronous modems, and distributed processing networks.
·Same product, manufactured by Intel Puerto Rico, Inc.
9-1
AFN-002BOA
iSBC 534
FUNCTIONAL DESCRIPTION
time delay is needed, software commands to the programmable timers select the desired function. Three
functions of these timers are supported on the iSBC
534, as shown in Table 1. The contents of each counter
may be read at any time during system operation.
Communications Interface
Four programmable communications interfaces using
Intel's 8251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) are contained on the.
board.' Each USART can be programmed by the system
software to individually select the desired asynchronous
or synchronous serial data transmission technique (including IBM Bisync). The mode of operation (Le., synchronous or asynchronous), data format, control
character format, parity, and baud rate are all under pro·
gram control. Each 8251A provides full duplex, double
buffered transmit and receive capability. Parity, overrun,
and framing error detection are all incorporated in each
USART. Each set of RS232C command lines, serial data
lines, and signal ground lines are brought out to 26'pin
edge connectors that mate with RS232C flat or round
cables.
Table 1. Programmable Timer Functions
Function
Operation
Interrupt on terminal count
When terminal count is reached
an interrupt request is generated.
This function is used for thegeneration of real-time clocks.
16·Bit Interval Timers
Divide by .N counter. The output
will go low for one input clock cycle and high ·for N -1 input clock
periods.
Square wave rate Output will remain high for onehalf the count and low for the
generator
other half of the count.
The iSBC 534 provides six fully programmable and in·
dependent BCD and binary 16-bit interval timers utilizing two Intel 8253 programmable interval timers.' Four
timers are available to the systems designer to generate
baud rates for the USARTs under software control.
Routing for the outputs from the other two counters is
jumper selectable. Each may be independently routed
to the programmable interrupt controller to provide real
time clocking or to the USARTs (for applications requiring different transmit and receive baud rates). In utilizing the iSBC 534, the systems designer simply configures, via software, each timer independently to meet
system requirements. Whenever a given baud rate or
Two independent Intel 8259A programmable interrupt
controllers (PIC's) provide vectoring for 16 interrupt
levels.' As shown in Table 2, a selection of three priority
processing algorithms is available to the system
designer. The manner in which requests are serviced
may thus be configured to match system requirements_
Priority assignments may be reconfigured dynamically
via software at any time during system operation. Any
combination of interrupt levels may be masked through
storage, via software, of a single byte to the interrupt
mask register of each PIC. Each PIC's interrupt request
Rate generator
Interrupt Request Lines
,
I'<-~--j
PROGRAMMABLE
TIMERS
Figure 1. iSBC 534 Four Channel Communications ExpanSion Board Block Diagram
9-2
AFN·00280A
iSBC 534
Table 3. Interrupt Assignments
output line may be jumper selected to drive any of the
nine interrupt lines on the MULTIBUS.
Table 2. Interrupt Priority Options
Algorithm
Fully
nested
Autorotating
Specific
priority
Interrupt
Request
Line
Operation
Interrupt request line priorities fixed at 0
as highest, 7 as lowest.
0
1
2
3
4
5
6
Equal priority. Each level, after receiving
service, becomes the lowest priority level
until next interrupt occurs.
System software assigns lowest priority
level. Priority of all other levels based in
sequence numerically on this assignment.
7
PIC 0
PORT 0 Rx
PORT 0 Tx
PORT 1 Rx
PORT 1 Tx
PORT 2 Rx
PORT 2 Tx
PORT 3 Rx
PORT 3 Tx
The iSBC 534 provides 16 RS232C buffered parallel 1/0
lines implemented utilizing an Intel 8255A program-
Interval Timer and Baud Rate Generator
Frequencies
SPECIFICATIONS
Serial Communications Characteristics
Input Frequency (On-Board Crystal Oscillator) MHz±0.1% (0.813I's period,nominal)
Synchronous - 5-8 bit characters; internal or external
character synchronization; automatic sync insertion.
Asynchronous - 5-8 bit characters; break character
generation; 1, 1'/2, or 2 stop bits; false start bit detection.
Single Timer
Function
Min
153.6
76.8
38.4
19.2
9.6
4.8
6.98
Real-Time
Interrupt
Interval
1
38400
19200
9600
4800
6980
Baud Rate (Hz)
Rate Generator
(Frequency)
Asynchronous
.;- 16
.;- 64
9600
4800
2400
1200
600
300
2400
1200
600
300
150
75
110
-
PIT 1 counter 1
PIT 2 counter 2
Ring indicator(all ports)
Present next digit
Carrier detect port 0
Carrier detect port 1
Carrier detect port 2
Carrier detect port 3
'Complete operational details on the Intel 8251A USART, the Intel 8253
Programmable Interval Timer, the Intel 8255.Programmable Peripheral Interface, and the Intel B259A Programmable, ,'nterrupt Controller are contained in the Intel 8080 Microcomputer System User's Manual and 8085
Microcomputer System User's Manual.
Systems Compatibility
Frequency2
(kHz, Software Seleclable) Synchronous
ROY
ROY
ROY
ROY
ROY
ROY
ROY
ROY
mabie peripheral interface (PPI) configured to operate in
mode 0.' These lines are configured to be directly compatible with the Bell 801 automatic calling unit (ACU).
This capability allows the iSBC 534 to interface to Bell
801 type ACUs and up to four modems or other serial
communications devices. For systems not requiring interface to an ACU, the parallel 110 lines may also be used
as general purpose RS232C compatible control lines in
system implementation.
Interrupt Request Generation - As s.hown in Table 3, interrupt requests may originate from 16 sources. Two
jumper selectable interrupt requests (8 total) can be
automatically generated by each USART when a
character is ready to be transferred to the MULTIBUS
system bus (i.e., receive buffer is full) or a character has
been transmitted (transmit buffer is empty). Jumper
selectable requests can be generated by two of the programmable timers (PITs), and six lines are routed directly
from peripherals to accept carrier detect (4 lines), ring in'
dicator, and the Bell 801 present next digit request lines.
Sample Baud Rates
PIC 1
Max
1.2288
Dual/Timer Counter
(Two Timers Cascaded)
Min
Max
1.63"s
53.3 ms
3.26 "s
58.25
minutes
18.75 Hz
614.4 kHz
0.0029 Hz
307.2 kHz
Interfaces - RS232C Interfaces
EIA Standard RS232C Signals provided and supported:
Carrier detect
Receive data
Clear to send
Ring indicator
Oata set ready
Secondary receive data
Oata terminal ready
Secondary transmit data
Transmit clock
Request to send
Receive clock
Transmit data
NOles:
1. Baud rates shown here are only a sample subset of possible
software-programmable rates avaiiable.Any frequency from 18.75 Hz to
614.4 kHz may be generated utilizing on· board crystal oscillator and
16·bit programmable interval timer (used here as frequency divider).
Parallel 110 - 8 input lines, 8 output lines, all signals
RS232C compatible
Bus - All signals MULTIBUS system bus compatible
2. Frequency selected by 1/0 writes of appropriate 16-bit frequency factor to Baud Rate Register.
9-3
AFN-002BOA
iSBC 534
I/O Addressing
Physical Characteristics
The USART, interval timer, interrupt controller, and
parallel interface registers of the iSBC 534 are con·
figured as a block of 16 I/O address locations. The loca·
tion of this block is jumper selectable to begin at any
16·byte I/O address boundary (Le., OOH, 10H, 20H, etc.).
Width - 12.00 in. (30.48 em)
Height - 6.75 in. (17.15 em)
Depth - 0.50 in. (1.27 em)
Weight - 14 oz (398 gm)
1/0 Access Time
Average DC Current
Electrical Characteristics
400
400
400
400
ns
ns
ns
ns
USART registers
Parallel I/O registers
Interval timer registers
Interrupt controller registers
Voltage
Compatible Connectors/Cable
Interface
Bus
Serial and
parallel ,liD
Pins
(qty)
Centers
(in.)
86
0.156
26
0.1
Mating Connectors
Viking 2KH43/9AMK12
3M 3462·0001 or
TI H312113
Without
Opla-Isolators
With
Opto-lsolators 1
VCC = +5V
1.9 A, max
1.9 A, max
VDD=+12V
275 rnA, max
420 rnA, max
VAA = -12V
250 rnA, max
400 rnA, max
Note
1. With iour 4N33 and four 4N37 opto·isolator packages installed in
sockets provided to implement four 20 rnA current loop interfaces.
Cable
N/A
Intel
iSBC955
Environmental Characteristics
O·C to + 55·C
Operating Temperature -
Compatible Opto-Isolators
Function
Supplier
Reference Manual
9800450·02 - iSBC 534 Hardware Reference Manual
(NOT SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Part Number
Driver
Fairchild
General Electric
Monsanto
4N33
Receiver
Fairchild
General Electric
Monsanto
4N37
ORDERING INFORMATION
Part Number
Description
SBC 534
Four Channel Communication Expansion Board
9-4
AFN·00280A
iSBC 544
INTELLIGENT COMMUNICATIONS CONTROLLER
lIiSBC Communications Controller acting
as a single board communications
computer or an intelligent slave for
communications expansion
• Ten programmable parallel I/O lines
compatible with Bell 801 Automatic
Calling Unit
• On-board dedicated 8085A Microprocessor providing communications
control and buffer management for
four programmable synchronous/
asynchronous channels
• Twelve levels of programmable
interrupt control
III
Sockets for up to 8K bytes of read only
memory
III
16K bytes of dual port dynamic read/
write memory with on-board refresh
III
Extended MUL TlBUS addressing
permits iSBC 544 board partitioning
into 16K-byte segments in a 1-megabyte
address space
• Individual software programmable baud
rate generation for each serial I/O
channel
• Three independent programmable
interval timer/counters
• Interface control for auto answer and
auto originate modem
The iSBC 544 Intelligent Communications Controller is a member of Intel's famiiy of single-board computers, memory,
I/O, and peripheral controller boards. The iSBC 544 board is a complete communications controller on a single
6.75 x 12.00 inch printed circuit card. The on-board BOB5A CPU may perform local communications processing by
directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous
serial I/O ports, RS232/RS366 compatible parallel I/O, programmable timers, and programmable interrupts.
9-5
AFN·01271A
iSBC 544
to coordinate up to four serial channels. Using the iSBC
544 as an intelligent slave, multichannel serial transfers
can be managed entirely on-board, freeing the bus
master to perform other system functions.
FUNCTIONAL DESCRIPTION
Intelligent Communications Controller
Two Mode Operation - The iSBC 544 board is capable
of operating in one of two modes: 1) as a single board
communications computer with all computer and communications interface hardware on a single board; 2) as
an "intelligent bus slave" that can perform communications related tasks as a peripheral processor to one or
more bus masters. The iSBC 544 may be configured to
operate as a stand-alone single board communications
computer with all MPU, memory and I/O elements on a
single board. In this mode of operation, the iSBC 544
may also interface with expansion memory and I/O
boards (but no additional bus masters). The iSBC 544
performs as an intelligent slave to the bus master by
performing all communications related tasks. Complete
synchronous and asynchronous I/O and data
management are controlled by the on-board 8085A CPU
I-
SERIALIIO
Architecture - The iSBC 544 board is functionally parti·
tioned into three major sections: I/O, central computer,
and shared dual port RAM memory (Figure 1). The I/O
hardware is centered around the four Intel 8251 A USART
devices providing fully programmable serial interfacing.
Included here as wellis a 10-bit parallel interface compatible with the Bell 801 automatic calling unit, or equivalent. The I/O is under full control of the on·board CPU
and is protected from access by system bus masters.
The second major segment of the intelligent communications controller is a central computer, with an 8085A
CPU providing powerful processing capability. The
8085A together with on· board EPROM / ROM, static
RAM, programmable timers/counters, and program:
----- PARAUELIIO -
SERIALIIO
I
I
I
I
I
I
I
I
I
I
II
L,-_ _ _
LL--~
~------,,-------------~------------~~~
11_-
8 INTERRUPTS:
2 PROGRAMMABLE
PROGRAMMABLE I/O
-r--------
8 INTERRUPTS:
RECEIVER READY
RING INDICATOR
TRANSMITTER READY
CARRIER DETECT
jI -
------ -----l-l. L - P~~~~I~~~I~;:::~:;
TIMER INTERRUPTS
FLAG INTERRUPT
I
I
I
16K x8
DYNAMIC
RAM
I
r------..l---'----,
ON BOARD SYSTEM BUS
~--------~---,
i
I
L
CENTRAL COMPUTER
/'---------
\------Figure 1. iSBC 544 Intelligent Communications Controller Block Diagram
9-6
AFN·01271A
iSBC 544
mabie interrupt control provide the intelligence to manage sophisticated communications operations on-board
the iSBC 544 board. The timer/counters and interrupt
control are also common to the 110 area providing programmable baud rates to the USARTs and prioritizing
interrupts generated from the USARTs. The central com·
puter functions are protected for access only by the onboard 8085A. Likewise, the on-board 8085A may not gain
access to the system bus when being used as an intelligent slave. When the iSBC 544 is used as a bus
master, the on-board 8085A CPU controls complete
system operation accessing on-board functions as well
as memory and 110 expansion. The third major segment,
dual port RAM memory, is the key link between the iSBC
544 intelligent slave and bus masters managing the
system functions. The dual port concept allows a common block of dynamic memory to be accessed by the
on-board 8085A CPU and off-board bus masters. The
system program can, therefore, utilize the shared dual
port RAM to pass command and status information
between the bus masters and on-board CPU. In addition,
the dual port concept permits blocks of data
transmitted or received to accumulate in the on-board
shared RAM, minimizing the need for a dedicated
memory board.
Central Processing Unit
Intel's powerful 8-bit n-channel 8085A CPU, fabricated
on a single LSI chip, is the central processor for the
iSBC 544. The 8085A CPU is directly software compatible
with the Intel 8080A CPU. The 8085A contains six 8-bit
general purpose registers and an accumulator. The six
general purpose registers may be addressed individually
or in pairs, providing both single and double precision
operators. The minimum instruction execution time is
1.45 microseconds. The 8085A CPU has a 16-bit program
counter. An external stack, located within any portion of
iSBC 544 read/write memory, may be used as a last-in/
first-out storage area for the contents of the program
counter, flags, accumulator, and all of the six general
purpose registers. A 16-bit stack pOinter controls the addressing of this external stack. This stack provides subroutine nesting bounded only by memory size.
EPROM/ROM Capacity
Sockets for up to 8K bytes of nonvolatile read only memory are provided on the iSBC 544 board. Read only memory may be added in 2K-byte increments up to a maximum of 4K bytes using Intel 2716 EPROMs or masked
ROMs; or in 4K-byte increments up to 8K bytes maximum
using Intel 2732 EPROMs. All on-board EPROM/ROM
operations are performed at maximum processor speed.
Serial I/O
Four programmable communications interfaces using
Intel's 8251 A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) are contained on the
board and controlled by the on-board CPU in combination with the on-board interval timer/counter to provide
all common communication frequencies. Each USART
can be programmed by the system software to individually select the desired asynchronous or synchronous
serial data transmission technique (including IBM
Bisync). The mode of operation (i.e., synchronous or
asynchronous), data format, control character format,
parity, and baud rate are all under program control. Each
8251 A provides full duplex, double-buffered, transmit
and receive capability. Parity, overrun, and framing error
detection are all incorporated in each USART. Each
channel is fully buffered to provide a direct interface to
RS232C compatible terminals, peripherals, or synchronous/asynchronous modems. Each channel of
RS232C command lines, serial data lines, and signal
ground lines are brought out to 26-pin edge connectors
that mate with RS232C flat or round cable.
RAM Capacity
The iSBC 544 contains 16K bytes of dynamic read/write
memory using Intel 2117 RAMs. Power for the on-board
RAM may be provided on an auxiliary power bus, and
memory protect logic is included for RAM battery backup requirements. The iSBC 544 contains a dual port controller, which provides dual port capability for the onboard RAM memory. RAM accesses may occur from
either the on-board 8085A CPU or from another bus
master, when used as an intelligent slave. Since onboard RAM accesses do not require the MUL TIBUS, the
bus is available for concurrent bus master use. Dynamic
RAM refresh is accomplished automatically by the iSBC
544 for accesses originating from either the CPU or from
the MULTIBUS.
Addressing - On board RAM, as seen by the on-board
8085A CPU, resides at address 8000-BFFF. On -board
RAM, as seen by an off-board CPU, may be. placed on
any 4K-byte address boundary. The iSBC 544 provides
extended addressing jumpers to allow the on-board
RAM to reside within a one megabyte address space
when accessed via the MULTI BUS. In addition, jumper
options are provided which allow the user to protect 8Kor 12K-bytes of on-board RAM for use by the on-board
8085 CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any
system address space.
Parallel 110 Port
The iSBC 544 provides a 10-bit parallel 110 interface controlled by an Intel 8155 Programmable Interface (PPI)
chip. The parallel 110 port is directly compatible with an
Automatic Calling Unit (ACU) such as the Bell Model
801, or equivalent, and can also be used for auxiliary functions. All signals are RS232C compatible, and the inter·
face cable signal assignments meet RS366 specifications. For systems not requiring an ACU interface, the
parallel 110 port can be used for any general purpose
interface requiring RS232C compatibility.
Static RAM - The iSBC 544 board also has 256 bytes of
static RAM located on the Intel 8155 PPI. This memory is
only accessible to the on-board 8085A CPU and is located
at address 7FOO H-7FFF H .
9-7
AFN·01271A
iSBC 544
Programmable Timers
Table 1. Programmable Timer Functions
The iSBC 544 board provides. seven fully programmable
and independent interval timer/counters utilizing two
Intel 8253 Programmable Interval Timers (PIT), and the
Intel 8155. The two Intel 8253 PITs provide six independ·
ent BCD or binary 16·bit interval timer/counters and the
8155 provides one 14-bit binary timer/counter. Four of
the PIT timers (BDGO-3) are dedicated to the USARTs
providing fully independent programmable baud rates.
Rate Generator Divide.by N counter.
(Mode 2)
The output will go low
for one input clock
cycle and high for N-1
input clock periods.
Square·Wave
Output will remain
Rate Generator high until one-half the
(Mode 3)
TC has·tieen com·
pleted,and go low for
the other half of the
count. This is the pri·
mary operating mode
used for generatinga
Baud rate clocked to
the USARTs.
Timer Functions - In utilizing the iSBC 544 board, the
systems designer simply configures, via software, each
timer independently to meet systems requirements.
Whenever a given baud rate or interrupt interval is
needed, software commands to the programmable
timers select the desired function; The on·board PITs
together with the 8155 provide a total of seven timer/
counters and six operating modes. Mode 3 of the 8253 is
the primary operating mode of the four dedicated USART
baud rate generators. The timer/counters and useful
modes of operation for the general use timer/counters
are shown in Table 1.
. .
Software
Triggered
Strobe
(Mode 4)
When the TC is loaded,
the counter will begin.
On TC the output will
go low for one input
clock period.
Single Pulse
Single pulse when TC
reached.
Repetitive
Single Pulse
Interrupt Capability
Interrupt Sources - The 21 interrupt sources originate
from both on-board communications functions and the
Multibus. Two ·interrupts are routed from each of the
four USARTs (8 interrupts total) to indicate that the
transmitter and receiver are ready to move a data byte to
or from. the on-board CPU. The PIC is dedicated to
accepting these 8 interrupts to optimize USART service
request. One of eight interrupt request lines are jumper
selectable for direct interface from a bus master via the
system bus.Two auxiliary timers (TINTO from 8155 and
TINT1 from 8253) are jumper selectable to provide
general purpose counter/timer interrupts. A jumper
selectable Flag Interrupt is generated to allow any bus
master to interrupt the iSBC 544 by writing into the base
address of the shared dual port memory accessable to
the system. 'The Flag Interrupt is then cleared by the
iSBC 544 when the on-board processor reads the base
address. This interrupt provides an interrupt link between
Counter
Interrupt on
When terminal count
Terminal Count is reached, an inter·
rupt request is gener(ModeO)
ated. This function is
useful for generation
of real·time clocks.
Three General Use Timers - The fifth timer (BDG4) may
be used as an auxiliary baud rate to any of the four
USARTs or may alternatively be cascaded with timer six
to provide. extended interrupt intervals. The sixth PIT
timer/counter (TINT1) can be used to generate interrupt
intervals to the on-board 8085A. In addition to the timer/
counters on the 8253 PITs, the iSBC 544 has a 14·bit
timer available on the 8155 PPI providing a third general
use timer/counter (TINTO). This timer output is jumper
selectable to the interrupt structure of the on-board
8085A CPU to provide additional timer/counter capability.
The iSBC 544 board provides interrupt service for up to
21 interrupt sources. Any of the 21 sources may interrupt
the intelligent controller, and all are brought through the
interrupt logic to 12 interrupt levels. Four interrupt levels
are handled directly by the interrupt proceSSing capa·
bility of the 8085ACPU and eight levels are serviced
from an Intel 8259A Programmable Interrupt Controller
(PIC) routing an interrupt request output to the INTR
input of the 8085A (see Table 2).
Operation
Function
,
Repetitiv.e single pulse
each time TC is
reached until a new
, command is loaded. ,
8253
TINT1
8253
BDG4*
8253
BDGO·4
TINT1
8253
BDG4 *
TINT1
8155
TINTO
8155
TINTO
,
•. BDG4 is jumper selectable as an auxiliary baud rate ge'nerator to the
USARTs or as a cascaded output to TINT1. BDG4 may be used in modes
2 and 4 only when configured as a cascaded output.
Table 2. Interrupt Vector Memory Locations
Vector
Location
Interrupt
Source
Interrupt
Level
1
Power Fail
8253 TINT1
8255TINTO
TRAP
RST.7.5
24H
3C H
2
Ring Indicator (1)
Carrier Detect
RST6.5
34 H
3
RST5.5
Flag Interrupt
INTOHNT7/ (1 of 8)
INTR
RXRDYO
TXRDYO
RXRDY1
TXRDY1
RXRDY2
TXRDY2
RXRDY3
TXRDY3
2C H
4
Programmabie
5·12
(1) Four ring indicator interrupts and four carrier'.detect interrupts are
summed to the RST 6.5 input. The 8155may be interrogated to inspect
anyone of the eight'signals.
AFN-01271A
iSBC 544
a bus master and intelligent slave (See System Programming)_ Eight inputs from the serial ports are monitored
to detect a ring indicator and carrier detect from each of
the four channels_ These eight interrupt sources are
summed to a single interrupt level of the 8085A CPU_ If
one of these eight interrupts occur, the 8155 PPI can then
be interrogated to determine which port caused the
interrupt. Finally, a jumper selectable Power Fail Interrupt is available from the Multibus to detect a power
down condition_
mode, no other bus masters may be configured in the
system. Memory may be expanded to a 65K byte
capacity by adding user specified combinations of RAM
boards, EPROM boards, or combination boards .. Input!
output capacity may be increased by adding digital 110
and analog 110 expansion boards. Furthermore, multiple
iSBC 544 boards may be included in an expanded
system using one iSBC 544 board as a single board communications computer and additional controllers as
intelligent slaves.
8085 Interrupt - Thirteen of the twenty-one interrupt
sources are available directly to four interrupt inputs of
the on-board 8085A CPU_ Requests routed to the 8085A
interrupt inputs, TRAP, RST 7_5, RST 6_5 and RST 5.5
have a unique vector memory address_ An 8085A jump
instruction at each of these addresses then provides
software linkage to interrupt service routines located
independently anywhere in the Memory_ All interrupt
inputs with the exception of the TRAP may be masked
via software_
System Programming
In the system programming environment, the iSBC 544
board appears as an additional RAM memory module
when used as an intelligent slave. The master CPU communicates with the iSBC 544 board as if it were just an
extension of system memory. Because the iSBC 544
board is treated as memory by the system, the user is
able to program into it a command structure which will
allow the iSBC 544 board to control its own 110 and
memory operation. To enhance the programming of the
iSBC 544 board, the user has been given some specific
tools. The tools are: 1) the flag interrupt, 2) an on-board
RAM memory area that is accessible to both an offboard CPU and the on-board 8085A through which a
communications path can exist, and 3) access to the
bus interrupt line.
8259A Interrupts - Eight interrupt sources signaling
transmitter and receiver ready from the four USARTs are
channeled directly to the Intel 8259A PIC_ The PIC then
provides vectoring for the next eight interrupt levels_
Operating mode and priority assignments may be reconfigured dynamically via software at any time during
system operation_ The PIC accepts transmitter and receiver interrupts from the four USARTs. It then
determines which of the incoming requests is of
highest priority, determines whether this request is of
higher priority than the level currently being serviced,
and, if appropriate, issues an interrupt to the CPU. The
output of the PIC is applied directly to the INTR input of
th.e 8085A. Any combination of interrupt levels may be
masked, via software, by storing a single byte in the
interrupt mask register of the PIC. When the 8085A
responds to a PIC interrupt, the PIC will generate a
CALL instruction for each interrupt level. These addressses are equally spaced at intervals of 4 or 8 (software selectable) bytes. Interrupt response to the PIC is
software programmable to a 32- or 64-byte block of
memory. Interrupt sequences may be expanded from
this block with a single 8085A jump instruction at each
of these addresses.
Flag Interrupt - The Flag Interrupt is generated anytime a write command is performed by an off-board CPU
to the base address of the iSBC 544 board's RAM. This
interrupt provides a means for the master CPU to notify
the iSBC 544 board that it wishes to establish a communications sequence. In systems with more than one
intelligent slave, the flag interrupt provides a unique interrupt to each slave outside the normal eight
MULTIBUS interrupt lines (I NTO/-I NT7/).
On-Board RAM - The on-board 16K byte RAM area that
is accessible to both an off-board CPU and the on-board
8085A can be located on any 4K boundary in the system.
The selected base address of the iSBC 544 RAM will
cause a flag interrupt when written into by an off-board
CPU.
Bus Access - The third tool to improve system
operation as an intelligent slave is access to the Multibus, interrupt lines. The iSBC 544 board can both respond to interrupt signals from an off-board CPU, and
generate' an interrupt to the off-board CPU via the
MULTIBUS.
Interrupt Output - In addition, the iSBC 544 board may
be jumper selected to generate an interrupt from the onboard serial output data (SOD) of the 8085A. The SOD
signal may be jumpered to anyone of the 8 MUL TIBUS
interrupt lines (I NTO/-INT7/) to provide an interrupt signal
directly to a bus master.
System Development Capability
Power-Fail Control
The development cycle of iSBC 544 board based products may be significantly reduced using the Intellec
series microcomputer development systems. The Intellec resident macroassembler, text editor, and system
monitor greatly simplify the design, development and
debug of iSBC 544 system software. An optional ISIS-II
diskette operating system provides a linker, object code
locater, and library manager. A unique in-circuit
emulator (ICE-85) option provides the capability of
developing and debugging software directly on the iSBC
544 board.
Control logic is also included to accept·a power-fail
interrupt in conjunction with the AC-Iow signal from the
iSBC 635 Power Supply or equivalent.
Expansion Capabilities
When the iSBC 544 board is used as a single board communications controller, memory and 110 capacity may be
expanded and additional functions added using Intel
MULTIBUS™ compatible expansion boards. In this
9-9
AFN·01271A
iSBC 544
SPECIFICATIONS
On·Board Dynamic RAM (MULTIBUS access) - any 4K
increment OOOOO·FFOOO which is switch and jumper
selectable. 4K· 8K: or 16K·bytes can be made available
to the bus by switch selection.
Serial Communications Characteristics
Synchronous -
5·8 bit characters; automatic sync
insertion; parity.
Asynchronous -
5·8 bit characters; break character
generation'; 1, 1'/2, or 2 stop bits;
false start bit detection; break
character detection.
110 Capacity
Serial - 4 programmable channels using four 8251A
USARTs.
.
Parallel - 10 programmable lines available for Bell 801
ACU, or equivalent use. Two auxiliary jumper selectable
signals.
Baud Rates
Frequency (KHz)1
(Software Selectable)
307.2
153.6
76.8
55.8
38.4
19.2
9.6
4.8
6.98
1/0 Addressing
Baud RatejHz)2
Synchronous
Asynchronous
--
-55800
38400
19200
9600
4800
6980
+ 16
19200
9600
4800
3500
2400
1200
600
300
--
On·Board Programmable 1/0
+64
4800
2400
1200
870
600
300
150
75
110·
Data
Control
USARTO
USARTI
USART2
USART3
8155 PPI
DO
02
04
06
E9 (Port A)
EA(Port B)
EB (Port C)
01
03
05
07
E8
Interrupts
Notes:
1) Frequency selected by 1/0 writes of appropriate 16·bit frequency factor
to Baud Rate Register.
Addresses for 8259A Registers (Hex notation, 1/0 ad·
dress space)
2) Baud rates shown here are only a sample subset of possible software'
programmable rates available. Any frequency from 1B.75 Hz to 614.4
KHz may be generated utilizing on-board crystal oscillator and 16·bit
Programmable Interval Timer (used here as a frequency divider).
E6
E6
E7
E6
E7
E6
8085ACPU
Word Size -
Port
8,16 or 24 bitslinstruction; 8 bits of data
Cycle Time -1.45/usec ±.1 % for fastest executable
ihstruction; i.e. four clock cycles.
Clock Rate - 2.76 MHz ±.1 %
Interrupt request register
In·service register
Mask register
Command register
Block address register
Status (polling register)
Note: Several registers have the same physical address: Sequence of
access and one data bit of the control word determines which register
will respond.
Interrupt levels routed to the 8085 GPUautomatically
vector the processor to unique memory locations:
24
TRAP
3C RST7.5
34. RST6.5
2C RST5.5
System Access Time
Dual port memory - 740 nsec
Note: Assumes no refresh contention
Memory Capacity
Timers
On·Board ROM/PROM - 4K, or 8K bytes of user installed
ROM or EPROM.
Addresses for 8253 Registers (Hex notation, 1/0 address
space)
On· Board Static RAM - 256 bytes on 8155.
Programmable Interrupt Timer One
08
TimerO
BDGO
BDG1
09
Timer1
Timer2
BDG2
DA
DB
Control register'
On·Board Dynamic RAM (on·board access) - 16K bytes.
Integrity maintained during power failure with user·
furnished batteries (optional).
On·Board Dyanmic RAM (MULTIBUS access) - 4K, 8K,
or 16K·bytes available to bus by switch selection.
Programmable Interrupt Timer Two
DC
Timer 0
BDG3
DO
Timer 1
BDG4
DE
Timer2
TINT1
OF
Control register
Memory Addressing
On·Board ROM/PROM - O·OFFF (using 2716 EPROMs or
masked ROMs); 0·1 FFF (using 2732 EPROMs)
Address for 8155 Programmable Timer
E8 Control
EC Timer (LSB) TINTO
ED Timer (MSB) TINTO
On·Board Static Ram - 256 bytes: 7FOO·7FFF
On·Board DyriamicRAM (on·board access) - 16K bytes:
8000·BFFF.
9-10
AFN-01271A
iSBC 544
Memory Protect
Input frequencies - Jumper selectable reference
1.2288 MHz±.1 % (.814 usec period nominal) or 1.843
MHz±.1 % crystal (0.542 usec period, nominal)
An active-low TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on
the board. This input is provided for the protection of
RAM contents during the system power-down sequences.
Output Frequencies (at 1.2288 MHz)
Single timer/counter
Dual timer/counter
(two timers cascaded)
Function
ReaHime
Min
Max
Min
Max
1.63 usee
53.3 usee
3.26 usee
58.25 min
18.75 Hz
614.4 KHz
0.00029 Hz 307.2 KHz
Bus Drivers
Function
interrupt interval
Rate Generator
(frequency)
Characteristic
Sink Current (mA)
Data
Tri-state
50
Address
Tri-state
15
Commands
Tri-state
32
Interfaces
Note: Used as a master in the single board communications c'omputer
mode.
Serial 110 - EIA Standard RS232C signals provided and
supported:
Receive Data
Carrier Detect
Ring Indicator
Clear to Send
Secondary Receive Data *
Data Set Ready
Data Terminal Ready
Secondary Transmit Data *
Transmit Clock
Request to Send
Transmit Data
Receive Clock
DTE Transmit Clock
Physical Characteristics
Width:
Depth:
Thickness:
Weight:
30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.27 cm (O:50inch)
3.97 gm (14 ounces)
Electrical Characteristics
" Optional if parallel 110 port is not used as Automatic Calling Unit.
DC Power Requirements
Parallel 110 - Four inputs and eight outputs (includes
two jumper selectable auxiliary outputs). All signals
compatible with EIA Standard RS232C. Directly compatible with Bell Model 801 Automatic Calling Unit, or
equivalent.
MUL TIBUS - Compatible with iSBC MULTIBUS ..
With4K
EPROM
(using,2716)
On· Board Addressing
Without
EPROM
Current Requirements
Configuration
Vee= +5V
;t5% (max)
RAM only (1)
All communicaiions to the parallel and serial 110 ports,
to the timers, and to the interrupt controller, are via read
and write commands from the on-board 8085A CPU.
ICC:::: 3.4 max
max
:!::12Vl
VDO=
±5% (max)
VBB = - 5V(3) VAA= -12V
::!:S% (max)
::!:S% (max)
100:::: 350mA ISS= SmA max IAA:::: 200mA
max
max
3.3A max
350 rnA max
5 mA max
200 rnA max
390 mA max
390 mA max
176 mA max
5 rnA max
-
20 mA max
5 mA max
RAM(2)
refresh only
Notes: 1. For operational RAM only. for AUX power supply rating.
2. For RAM refresh only. Used for battery backup requirements. No RAM
Auxiliary Power
accessed.
3. VSS is normally derived on· board from V AA' eliminating the need for a
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.
Environmental Characteristics
Connectors
Operating Temperature: 0 'C to 55 'C (32' F to 131 'F)
Relative Humidity: To 90% without condensation
Interface
Pins
(qty)
Centers
Ves
Bus
86
0.156
Viking 2KH43/9AMK12
ParalielliO
50
0.1
3M 3415·000 or
AMP 88083·1
Serial 110
26
0.1
3M 3462-000 or
AMP 88373-5
Ves
from the bus, the current
Reference Manual
Mating Connectors
(In.)
supply. If it is desired to supply
requirement is as shown.
98006168 - iSBC 544 Intelligent Communication Controller Board Hardware Reference Manual (NOT SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
iSBC544
Intelligent Communications
Controller
9-11
AFN·01271A
iSBC™550
ETHERNETTM COMMUNICATIONS CONTROLLER
• Meets the version 1_0 tri-corporate
Ethernet specification
• Easy-to-use MULTIBUS® interprocessor protocol supported in
firmware
• Ethernet data link layer support
• Data encapsulation
• Framing and packet control
• Buffer management
• Power-up confidence test assures
integrity of on-board memory and
programmable LSI
• Ethernet physical link layer support
• Serial/deserialization
• 10 Mbits per second data rate
• CRC generation/check
• Carrier-sense mUltiple-access with
collision detection (CSMA/CD)
• Transceiver interface compatibility
• Traffic, errors and collision
information maintained for network
management
• Excellent foundation for Ethernet
local area· end-to-end network
The iSBC 550 Ethernet Communications Controller meets the tri-corporate (DEC, Xerox, Intel) specification for Ethernet local area networks. All the functions of the Ethernet data link layer and physical link
layer are provided on two 6.75 x 12" circuits boards and associated firmware. The MULTIBUS compatible
controller can be utilized as .the foundation for a single board computer (iSBC)-based Ethernet local area
network or as a prototype for Intel® 8085, iAPX™ 88, or iAPX 86 component-based Ethernet applications.
The iSBC 550 controller's firmware (supplying the Ethernet and system interface) has an easy-to-use
MULTIBUS InterprocessorProtocol (MIP) facility, which is readily accessed from anotheriSBC Board
using a custom run-time software system or Intel's iRMX™ 80/88/86 Real-Time Executive software and the
iMMX™ 800 (MULTIBUS Message Exchange) software package. The Ethernet data link functions are
divided between the processor board which provides the data link layer's software to control the data encapsulation and the link management, and the serial/desei'ialization (SerDes) board which provides the
10-MBit per second serial interface to the Ethernet transceiver.
The following are trademarks of Intel Corporation and may be used to describe Intel products: CREDIT, Index, Insile, Intellec, Library Manager, Megachassis, Micromap,
MULTIBUS, PROMPT, UPI, /iScope, Promware, MeS, ICE, iRMX, iSBC, iSBX, MULTIMODULE, les, iAPX and iMMX. Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTELCORPOAATION, 19B1
-EthernetTM is a trademark of Xerox Corporation
9-12
June, 1981
143882
associated data), and the required Ethernet information.
FUNCTIONAL DESCRIPTION
The iSBC 550 Ethernet Communications Controller is a two-board MULTI BUS-compatible set that
offers high-speed Ethernet-compatible data transfer between digital devices operating at a 10-Mbit
per sec data rate_ The iSBC 550 controller can effectively support the needs of local area network
applications, . such as office automation, distributed data processing, factory data collection,
research data collection, intelligent terminal and
other EDP-related products_
(14 byles)
(1 byle)
(7 byles)
iSBC 550 { RESERVED DATA
CONTROLLER COMMAND
INFORMATION RESERVED DATA
DESTINATION
ETHERNET { SOURCE
INFORMATION TYPE
DATA
(6 byles)
(6 byles)
(2 byles)
(46-1500 byles)
Figure 1. Data Link for SUPPLYBUF Command
Format·
Ethernet Specification
Shown in Table 1 are eight external Ethernet controller commands available to a user's application
via the MIP interface. The commands manage the
Ethernet multicast address recognition, message
type connection, message flow, and overall network statistics.
The Ethernet network is a local area network concept that is jOintly being supported by Intel Corporation, Digital. Equipment Corporation, and Xerox
Corporation. The network is designed to link systems over a distance of up to 2500 meters using
an available 50-ohm coaxial cable. Several hundred stations may be connected to the cable
which supports a data rate of 10 Megabits per second. The data is encapsulated in a packet message format. The data signal is a base-band,
Manches"ter-encoded type that is self-synchronizing.
Table 1_ External Controller Commands
Command
The jointly developed Ethernet speCification, "The
Ethernet, A Local Area Network Data Link Layer
and PhYsical Link Layer Specification, Version
1.0, September 30, 1980", precisely defines the
two lower layers of a local area network architecture where the system is a series of independent
layers. The lowest layer, the physical link layer, is
concerned with coaxial cable interface. The data
link layer supports the peer protocol's statistical
contention resolution (CSMA/CD) and link management functions. All additional network layers
are defined by the user during the implementation
of the application-specific layers.
Function
CONNECT
Indicates the data link message
TYPE to be connected to user program.
DISCONNECT
Disconnects the data IinkTYPE from
the user's application.
ADDMCID
Adds a multicast ID for recognition.
DELETEMCID
Delete the specified multicast ID.
TRANSMIT
Transmit a data packet to the Ethernet link.
SUPPL YBUF
Supplies a buffer for packet reception from the Ethernet link ("receive"
function).
READ
Read the statistical variables maintained by data link layer.
READC
Read and clear the statistical variables.
Ethernet Data Link Layer Support
Ethernet Physical Link Layer Support
The iSBC 550 processor board provides the data
link layer's software to control the data encapsulation and the link management, including frame
delimitation, address handling, error detection,
and collision handling. After the iSBC 550 processor board is initialized upon system start-up or
reset, the data link firmware is ready to service the
local area network commands. An example of a
command structure sent the iSBC controller to
receive a packet of data from the Ethernet link is
shown in Figure 1. The message passed via the
MIP (MULTIBUS Interprocessor Protocol) interface is composed of two parts, the iSBC 550 controller information (including the command and
The Serialization/Deserialization (SerDes) board
provides the required electrical characteristics of
the physical link layer of the Ethernet architecture
for a transceiver interface. The transceiver is a
device physically attached to the coax cable
which does signal conditioning for transmitting
and receiving.
Many major functions are controlled by the
SerDes board. These functions include serialization/deserialization, packet framing, Manchester
encoding/decoding, transmit data flow control,
receive data flow control, destination address decoding for received message, CRC generation and
9-13
AFN·01979A
checking, and diagnostics for CRC error, loopback, transmit timeout, and CSMA/CD (CarrierSense Multiple-Access with Collision-Detection)_
and error totals. This information can be effectively utilized by the user's application to understand the network's operation.
Easy·To·Use Interface
One of the iSBC 550 controller boards is an iAPX
88-based processor board which has firmware
support for the user's application interface. The
programmatic interface utilizes the MULTIBUS
Interprocessor Protocol (MIP) interface to the processor board. This interface is concerned with the
message-passing protocol between multipleprocessors. The iMMX 800 (MULTIBUS Message
Exchange) software supports the MIP interface
and offers a convenient quick-start method for
users of Intel's iRMX 80, iRMX 88 executives and
iRMX 86 operating system products for an Ethernet-based application.
Confidence Test
An effective diagnostic function is implemented
in firmware on the processor board. This function
is invoked at system initialization during both
power-up and system reset time. These functions
include: packet CRC checking, memory test, controller loopback, and other error tests. The tests
provide a fundamental level of controller integrity.
Network Statistics
Statistics maintained by the data link firmware include packet traffic counts, collision information
End·To·End Networking Foundation
The iSBC 550 controller provides the foundation
data link layer and the physical link layer for a
local area network architecture. Typically, the
higher levels are user-defined and include the
transport and the session control layers. The
transport control layer is concernedwitti the endto-end communications and the virtual channel
connection via a port-to-port address. The session
control layer provides the process-to-process control function which includes symbolic name binding and the establishment of the virtual connection via the transport control layer. In addition, the
session control provides the specific error and recovery control responsible for message delivery.
The higher levels of the 10caJ area network architecture (see Figure 2) which use the data link layer
are outside of the Ethernet standard, but can be
implemented quickly on companion iSBC boards
(e.g., iSBC 80/24, iSBC 88/25, iSBC 86/12A) running
under the iRMX 80/88/86 Real-Time Multitasking
Executives, respectively, and associated iMMX
MULTIBUS Message Exchange (iMMX. 800) software. Special iSBC 550 device driver software
compatible with the iRMX 86 and iRMX 88 file systems is provided in the iMMX 800 package.
_g~"L~_----:::b:::;SS:::SS=::j__
I
I
TRANSCEIVER~
TRANSMIT AND
RECEIVE FUNCTION
TRANSCEIVER CABLE
50 melers MAX. ~
(LESSSERDES CABLE)
SEA DES TO
TRANSCEIVER CABLE~
0.55 meter
ENCODE AND
iRMX 88 OR iRMX 86
MMX SOFTWARE
+
DECODE FUNCTION
CSMAICO
10 Mbit/sec
isec
550
SERDES BO~RD
isac 550
ETHERNET
iSBC
801iri,JO
I
LINK MANAGEMENT
lRMX 80
86/05
86112A
88125
88140
CONTROLLER
FUNCTION
DATA ENCAPSULATION
FUNCTiON
iSBC 550 .
CONTROLLER PROCESSOR
BOARD
MIP INTERFACE
(STATION INTERFACE)
MUlTIBUS INTERPROCESSOR PROTOCOL(MIP)
Figure 2. Ethernet Architecture and Implementation
9-14
AFN-01979A
SPECIFICATIONS
SerDes to Transceiver Cable
Memory Addressing Capability
Length - 0.55 meter (22 in.). Four pair twistedwire cable with SerDes connector and transceiver
interface connector.
MULTIBUS System Bus -
(OOOOO-EFFFF)
Ethernet 1/0 Channels
Electrical Characteristics
One Ethernet electrically-compatible transceiver
line on the SerDes board.
Power requirements for both boards
+ 5 VDC @ 9.0A max.
+ 12 VDC @ 0.5A max.
Interface Specifications
MULTIBUS System Bus patible.
Environmental Characteristics
All signals TTL com-
Operating Temperature -
Transceiver - All signals Ethernet specifications
transceiver compatible.
Relative Humidity tion)
Serial Communications Characteristics
Connectors
Bit Serial Frame - Provides 64-bit preamble,
48-bit destination address, 48-bit source address,
16-bit type, 46-1500 bytes for data, and a frame
check sequence of 32 bits.
Interface
MULTIBUS
System
SerDes
Edge
Connector
Transceiver
Ethernet Network Specifications Supported
Coax Cable Length - 500-meter max.
Transceiver Cable Length - 50-meter max.
Number of Stations - 100 max.
Baud Rate - 10-Mbitlsec
O°C to 55°C
To 90% (without condensa-
Pins Centers
(in_)
(qty)
Mating Connectors
86
0.156
Viking 2KH43/9AMK12
10
0.1
AMP 87631-5 Housing
AMP 87195-9 Pins
15
0.1
Cinch Type DA51220-1
Reference Manuals
121746 -iSBC 550 Ethernet Communications
Controller Hardware Roference Manual (NOT SUPPLIED)
.
System Clock
5.00 MHz, ±0.1%
Physical Characteristics (Both Boards)
121769 - The Ethernet Communications Controller Programmer's Reference Manual (NOT SUPPLIED)
Width Height Depth Weight -
Manuals may be ordered from any Intel sales representative, distributor office or from Intel literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.
12.00 in. (30.48 cm) (each board)
6.75 in. (17.15 cm) (each board)
0.5 in. (1.27 cm) (each board)
3.5 Ib (1.6 kg) (both boards)
ORDERING INFORMATION
Part Number
Description
SBC 550
Ethernet Communications Controller for 10 Mbitlsec coaxial
transmission. Includes Ethernet
data link control software and
cable to transceiver.
9-15
iSBX™ 352
BIT SERIAL COMMUNICATIONS
MUlTIMODUlE™ BOARD
• Software programmable baud rate
generation up to 64K baud
synchronous and 9.6K baud self·
clocking
• Provides an HOLC/SOLC l1alflfull·
duplex communications channel for
iSBX™ bus compatible micro·
computers
• Supports RS232C (including modem
support) or RS449/422A interface
• Supports synchronous or self·clocking
NRZI point·to·point, multidrop and
self·clocking NRZI SOLC loop data link
interfaces
• Single +5V when configured for
RS449/422A interface
The Intel iSBX 352 Bit Serial Communications MULTIMODULE board offers incremental on-board 110. expansion support for ISO/CCITI's HDLC or IBM's SDLC communication. Plugging directly into any iSBX
bus compatible host board, the iSBX 352 module provides one RS232Cor RS449/422A programmable bit
serial communications channel with software selectable baud rates (up to 64K baud for half-duplex synchronous operations). Data link interfaces supported are: synchronous point-to-point, multidrop and SDLC
loop. The phase lock loop feature provides NRZI self-clocking 9.6K baud operation.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, CREDIT, Index, Insite, Inteliee, Library Manager, Megachassis,
Micromap, MULTIBUS, PROMPT, UPI, p.Scope, Promware, MeS, ICE, iRMX, ISSC, iSaX, MULTIMODULE and ieS. Intel Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
9-16
October, 1981
Order Number: 210218-001
inter
iSBX™ 352
Addressing an iSBX 352 board by using a port address, the program performs the 8-bit data transfer
required, using buffered or non-buffered transmit/
receive and abort sequences.
FUNCTIONAL DESCRIPTION
Communications Interface
The iSBX 352 module uses the Intel 8273 Programmable HOLC/SOLC Protocol Controller. The iSBX
352 module provides one bit-serial communications channel for iSBX bus compatible host microcomputers. (See Figure 1.) An iSBC microcomputer or MULTIBUS-based application is easily
connected tO,an HOLC/SOLC point-to-point, multidrop, or an SOLC loop configuration.
Serial data transfer control is provided by the 8273
controller of the iSBX 352 module which interfaces the parallel iSBX bus to the serial channel.
Ouring a transmit sequence, the iSBX 352 modUle
accepts data and commands from the iSBX bus interface, translates and formats the data into
HOLC/SOLC protocol formats, provides the proper
RS232C or RS422A interface control signals, and
passes data onto the serial channel. The receive
operation is the inverse of the previous sequence.
The Higl:\,Level Oata Link Control (HOLC) is the International Standards Organization (ISO) standard
discipline used to impleITl§nt X.25 packet switching communications. The Rynchronous Oata Link
Control (SOLC) is an IBM communication protocol
used to implement ttl'e'System Network Architecture (SNA). Both protocols, HOLC and SOLC, are
bit oriented, code i~dependent, and support fullduplex operations.' '
Data Link Configurations
The supported data link configurations are shown
in Table 1. The following example configurations
provide an overview and a figure for five typical
data link configurations:
Table 1. iSBXTM 352 Supported Configurations
Data Link Interface
Connection
The control lines, serial data lines and signal
grounq lines are brought out to the double edge
connector of the iSBX ~52 module and are configurable for RS232C or RS449/422A interface (see
Figure 2).
.
point-to-point
Asynchronous
Synchronous
Modem Direct Modem· Direct
X
X
X
X
multidrop
loop
X
X
X
X
NA
NA
X
X
• Modem should not respond to a break.
USER I/O
CONNECTOR~
INTEL® ISBX'" 352
- - - MULTIMOOULEu ,
BOARO
HOST BOARD
/
.
~.
INTEL@ISBX'"
..:::: .. .......------ MUlTIMOOULE'"
. .;.;.:':;.'
CONNECTO~
,.
~.
Figure 1. Installation of iSBX™ 352 MULTIMODULE™ Board on a Host Board
9-17
AFN·02069A
iSBX™ 352
CONNECTOR PIN 1
Figure 2. Cable Construction and Installation for RS232C and RS4491422A Interface
SYNCHRONOUS POINT·TO·POINT INTERFACE
SELF·CLOCKING POINT·TO·POINT INTERFACE
Figure 3 shows a synchronous point·to·point
mode of operation for the iSBX 352 module. This
RS232C example uses a modem for generation of
the receive clock for coordination of the data
transfer. The iSBX 352 module generates the
transmit synchronizing clock for synchronous
transmission.
The iSBX 352 module is used in an asynchronous
mode interface when configured as shown in
Figure 4. The point·to·point RS232C example uses
the self·clocking mode interface for NRZI encod·
ing/decoding of data. The digital phase lock loop
allows operation of the interface in either halfduplex or full-duplex implementation with or
without modems.
CONNECTOR
CONNECTOR,
J1
J1
TxC
TxO
RxC
RxD
RTS
RTS
iSBX'1,j 352 CTS
BOARD
RxC
RxD
DSR
DTR
J1
CTS
CTS
iSBXT.. 352 TxD
RxD
BOARD
TxD
DSR
CONNECTOR
J1
RTS
CTS iSBX'M 352
TxC BOARD
DTR
CONNECTOR
Figure 3. Synchronous Point-to· Point Modem
Interface Configuration Example RS232C
RxD
TxD
DTR
DSR
DSR
iSBX™ 352
BOARD
DTR
Figure 4. Self·Clocking Point·to·Point Modem
Interface Configuration Example RS232C
9-18
AFN'{)2069A
iSBX™ 352
configuration. This self-clocking example uses
the 8273 digital phase lock loop and NRZI data encoding.
SYNCHRONOUS MULTIDROP
The iSBX 352 MULTIMOOULE is used as both a
master anda slave node in the RS449/422A example shown in Figure 5. This synchronous multidrop
application is effective for high-speed data
transfers between slave stations and a central
master station.
SOLe Loop
The SOLe self-clocking loop configuration shown
in Figure 7 permits longer networks since each
secondary slave station is arepeater set in one-bitdelay mode. The data sent out by the primary station (the loop controller) are relayed bit-for-bit
through each secondary station and finally back to
the master station.
ASYNCHRONOUS SELF-CLOCKING MULTIDROP
The iSBX 352 MULTIMOOULE example in Figure 6
shows a master and multiple slaves in a multidrop
CONNECTOR
J1
MASTER
TT
..
SO
RT
iSBX'" 352
BOARD
RD
TR
OM
CONNECTOR
J1
l
CONNECTOR
J1
RS
OM
SD
TT
RO
RT
I
RS
OM
SO
TT
RD
iSBX'" 352
iSBX'" 352
BOARD
BOARD
SLAVE A
SLAVE B
RT
NOTE:
The last slave device in the system must contain termination resistors on all signal lines received oy the slave ooard.
The master device must contain resistors on all received signal lines.
Figure 5_ Synchronous Multidrop Network Configuration Example - .RS422A
...
SLAVE B
MASTER
SLAVE A
SLAVE C
iSBX™ 352 BOARD
iSBX'" 352 BOARD
iSBX'" 352
RD
BOARD
MASTER
SO
RD
SO
RD
SO
SO
-
..,....-
iSBX'M 352
BOARD
RD
SO
.RD
iSBX rlol 352
BOARD
SO
RD
I
SO
8(5)
12(9)
RD
SO
RD
Isex'" 352 BOARD
iSBX™ 352 BOARD
SLAVE B
SLAVE 0
iSBX"" 352
BOARD
SLAVE A
Figure 7. Self·Clocking SOLC Loop Network
Configuration Example
Figure 6. Self-Clocking Multidrop Configuration
Example - RS422A
9-19
AFN·02069A
iSBX™ 352
SPECI FICATIONS
RATE GENERATOR FREQUENCIES
Baud
Rate
bits/sec
Data Size
8 Bits
Device
Selected
Function
Performed
8·bit 16·bit
XO
XO
X1
X2
125
TX Clock
32X Clock
143
48K
19.2K
167
417
-
-
-
-
9.6K
833
1,667
X2
X4
Read Counter 2
Write Counter 2
X3
X6
Write Control
X4
X8
Read Status
Write Command
X5
XA
Read Result
Write Parameter
X6
XC
X7
XE
YO
YO
Y4
4.8K
Read Counter 1
Write Counter 1
,
.. ,'
26
1,667
52
104
2.4K
3,333
3,333
1.2K
O.6K
6,667
13,333
0.3K
26,667
'6,667
13,333
26,667
208
417
833
SERIAL RS449/422A SIGNALS
CS
Read Receive Data
Write Transmit Data
NOTE: Refer to the Hardware Reference Manual for your host
iSBCTM microcomputer to determine the upper digit
(either X or Y) of the MULTIMODULETM port address.
Interfaces
iSBX™ BUS -
833
NOTE: All numbers are in decimal notation .
8273
Read Transmit Interrupt
HDLC/SDLC Write Reset
CONTROLLER Read Receive Interrupt
Y8
Self:CloC;kir:!!iI
64K
Read Counter 0
Write Counter 0
8254·2
PIT
Synchronous
56K'
1/0 Port Addresses
Port
Address
8254·2 ,Divide Count
All signals TTL compatible
Clear to Send
DM
Data Mode
RC
Receive Common
RD
Receive Data
RS
RT
Request to Send
SC
Send Common
Receive Timing
SD
Send Data
SG
TR
Signal Ground
Terminal Ready
TT
Terminal Timing
SERIAL RS232C SIGNALS
CTS
Clear to Send
DSR
Data Set Ready
DTE TXC
Transmit Clock
OPERATING SPEEDS
24 MHz on·board crystal
8 MHz clocking of the 8254·2 PIT
DTR
Data Terminal Ready
FG
Frame Ground
RTS
RXC
Request to Send
Receive Clock
DATA THROUGHPUT SPEED
RXD
Receive Data
64K baud maximum for half-duplex operation
SG
Signal Ground
TXD
Transmit Data
48K baud for full-duplex operation issuing commands during transmit operations
4 MHz clocking of the 8273 Device
9-20
AFN'()2069A
inter
iSBX™ 352
SERIAL INTERFACE CONNECTORS
Mode2
MULTIMODULE™
Edge Connector
Cable
Connector
RS232C
DTE
26·pin 5 , 3M·3462·0001
3M3·3349/25
25·pin 7 ,3M·3482·1000
RS232C
DCE
26·pin 5 , 3M·3462·0001
3M3·3349/25
25·pin 7 ,3M·3483·1000
RS449
DTE
40·pin6, 3M·3464·0001
3M4·3349/37
37·pin,,3M·3502·1000
RS449
DCE
40·pin6, 3M·3464·0001
3M4·3349/37
37·pin,,3M·3503·1000
Configuration
NOTES:
1. Cable housing 3M·3485·4000 may be used with the connector.
2. DTE - Data Terminal Equipment mode (male connector); DCE - Data Set Equipment mode (female connector).
3. Cable is tapered at one end to fit the 3M·3462 connector.
4. Cable is tapered to fit 3M·3464 connector.
5. Pin 26 of the edge connector is not connected to the flat cable.
6. Pins 38, 39, and 40 of the edge connector are not connected to the flat cable.
7. May be used with the cable housing 3M·3485·1000.
Electrical Characteristics
Physical Characteristics
Width -
DC POWER REQUIREMENTS
Interface
RS 232C
Voltage
Current
(max)
+ 5± 0.25V
595 rnA
-12±0.6V
+12±0.6V
RS 449/422A
+ 5±0.25V
30 rnA
Length - 9.40 em (3.70 inches)
Total
Power
3.8 watts
4.1 watts
1.40 cm (0.56 inches)
Weight -
72 gm (2.53 ounces)
143983 - iSBX 352 Bit Serial Communications
MULTIMODULE Board Hardware Reference
Manual.
Environmental Characteristics
Reference manuals may be ordered from any Intel
sales representative, distributor office or from
Intel Literature Department, 3065 Bowers Ave.,
Santa Clara, California 95051.
Temperature - 0 - 55°C, free moving air across
base board and MULTIMODULE board
Humidity -
Height -
Reference Manual (Not Supplied)
30 rnA
775 rnA
7.27 em (2.85 inches)
to 90%, without condensation
ORDERING INFORMATION
Part Number
Description
SBX 352
HDLC/SDLC Serial I/O
MULTIMODULE Board
9-21
Analog 110 Expansion
and Signal
Conditioning Boards
10
iSBX 311
ANALOG INPUT MUL TIMODULE BOARD
• Low cost analog input for iSBX MULTIMODULE compatible iSBC boards
• 12·bit resolution analog·to·digital
converter
• 8 differential/16 single·ended, fault
protected inputs
• 0.035% full scale accuracy (11 bits) at
25°C
• 20 mV to 5V full scale input range,
resistor gain selectable
• 18 kHz samples per second through·
put to memory
• Unipolar (0 to + 5V) or bipolar ( - 5V to
+ 5V) input, jumper selectable
• Connector compatible with iCS 910
Analog Termination Panel
The Intel iSBX 311 Analog Input MULTIMODULEboard provides simple interfacing of non-isolated analog
signals to any iSBC board which has an iSBX compatible bus and connectors_ The single-wide iSBX 311
plugs directly onto the iSBC board, providing data acquisition of analog signals from eight differential or
sixteen single-ended voltage inputs, jumper selectable. The iSBX 311 MULTIMODULE is connector and
pinout compatible with the Intel iCS 910 Analog Signal Conditioning/Termination panel so that field wiring can easily be terminated and current loop-to-voltage conversion resistors can be mounted for current
loop analog signal monitoring. Resistor gain selection is provided for both low level (20mv full scale
range) and high level (5 volt FSR) signals. Incorporating the latest high quality IC components, the iSBX
311 MULTIMODULE board provides 12 bit resolution, 11 bit accuracy, and a simple programming interface, all on a low cost iSBX MULTIMODULE board.
10-1
iSBX 311
FUNCTIONAL DESCRIPTION
ground. For noisier environments, differential input mode can be configured to achieve 8 separate
differential signal inputs,or 16 pseudo-differential
inputs.
The iSBX 311 Analog Input MULTIMODULE board
is a member of Intel's growing family of
MULTIMODULE expansion boards,designed to
allow quick, easy, and inexpensive expansion for
the Intel single board computer product line. The
iSBX 311 Analog Input MULTIMODULE. Board
shown in figure 1, is designed to plug onto any
host iSBC microcomputer that contains an iSBX
bus connector (P1). The board provides 8 differential or 16 single-ended analog input channels that
maybe jumper-selected as the application
requires. The MULTIMODULE board includes a
user-configurable gain, and a user-selectable
voltage input range (0 to + 5 volts, or - 5 to + 5
volts), The MULTIMODULE board receives all
power and control signals through the iSBX bus
connector to initiate channel selection, sample
and hold operation, and analog-to-digital conversion.
Resolution
The iSBX 311 MULTIMODULES provide 12-bit
resolution with a successive approximation
analog-to-digital converter. For bipolar operation
( - 5 to + 5 volts) it provides 11 bits plus sign.
Speed
The A-to-D converter conversion speed is 35
microseconds (28KHZ samples per second). Combined with the sample and hold, settling times and
the programming interface, maximum throughput
via the iSBX bus and into memory will be 54
microseconds per sample, or 18 KHZ samples per
second, for a single channel, a random channel, or
asequential channel scan. A-to-D conversion is initiated via the iSBX connector and programmed
command from the iSBC base board. Interrupt on
end-of-conversion is a standard feature to ease
programming and timing constraints.
Input Capacity
Sixteen separate analog signals may be randomly
or sequentially sampled in single-ended mode
with the sixteen input multiplexers and a common
HIGH
IMPEDANCE
BUFFER
AMP
•
8 CHANNEL
INPUT
MULTIPLEXER
INTR
GAIN
RESISTOR
DIFFERENTIAL
TO
SINGLE
ENDED
AMP
ANALOG
INPUT
SIGNALS
SIGNAL
GROUND
GAIN
SELECT
•
OFFSET
ADJUST
SAMPLE
•
DATA
HOLD
AMP
LINES
START
CONVERSION
AND
CHANNEL
SELECTOR
LOGIC
Figure 1_ iSBX 311 Analog Input MULTIMOPULE Board
10-2
AFN-01628A
iSBX 311
Accuracy
OUTput Command start conversion.
High quality components are used to achieve 12
bits resolution and accuracy of .035% full scale
range ± 1/2 LSB. Offset and gain are adjustable to
± 0.024 % FSR ± 112 LSB accuracy at any fixed
temperature between O°C (gain = 1). See specifications for other gain accuracies.
7
Bit Position
Select input channel and
6
5
4
Input Channel
320
IC31 <:;21 C1 ICO I
INput Data - Read converted data and status (low
byte) or Read converted data (high byte). Reads
can be with or without reset of interrupt request
line (INTRO/).
Gain
To allow sampling of millivolt level signals such
as strain gauges and thermocouples, gain is made
configurable via user inserted gain resistors up to
250 x (20 millivolts, full scale input range). User
can select any other gain range from 1 to 250 to
match his application.
Bit Position
7
6
5
4
3
2
0
Low/status Byte
I
OPERATIONAL DESCRIPTION
High Byte
101110101091081071061051041
The host iSBC microcomputer addresses the iSBX
311 MULTI MODULE board by executing IN or OUT
instructions to the iSBX 311 MUL TIMODULE as
one of the legal port addresses. Analog-to-digital
conversions can be programmed in either of two
modes: 1. start conversion and poll for end-of-conversion (EOG), or 2. start conversion and wait for
interrupt (INTRO/) at end of conversion. When
conversion is complete as signaled by one of the
above techniques, INput instructions read two
bytes (low and high bytes) containing the 12 bit
data word plus status information as shown
below.
Fastest data conversion and transfer to memory
can be obtained by dedicating the microcomputer
to setting the channel address/starting conversion, polling the status byte for EOC/, and when it
comes true, read the two bytes of the conversion
and send the start conversion/next channel address command. For multitasking situations it
may be more convenient to use the interrupt
mode, reading in data only after an interrupt signals end of conversion.
SPECIFICATIONS
Accuracy -
Inputs - 8 differential. 16 single-ended. Jumper
selectable.
Gain
1
5
50
250
Full Scale Input
Voltage Range - - 5 to + 5 volts (bipolar). 0 to
+ 5 volts (unipolar). Jumper selectable.
031 021 01
IDO I Istarttl busytl Eoetl
Accuracy at 25°C
±
±
±
±
0.035%
0.035%
0.035%
0.035%
±
±
±
±
V2
V2
V2
1/2
LSB
LSB
LSB
LSB
NOTE:
Figures are in percent of full scale reading. At any fixed tem·
perature between O· and 60·C, the accuracy is adjustable to
± 0.035% of full scale.
Gain - User-configurable through installation of
two resistors. Factory-configured for gain of X1;
gains above 250 not recommended.
Dynamic Error- ± 0.015% FSR for transitions
Resolution - 12 bits over full scale range (1.22 mv
at 0·5 v, 5)Jv at 0-20 mv)
Gain TC (at Gain =1): 30 PPM per degree centigrade (typical); 56 PPM per degree centigrade
(max).
10-3
AFN·01628A
iSBX 311
Physical Characteristics
Offset TC (in percent of FSR/°C):
Width - 9.40 cm (3.7 inches)
Gain
Offset
1
5
50
250
Length - 6.35 cm (2.5 inches)
Height - 2.03 cm (0.80 inch) MULTIMODULE
board only
2.82 cm (1.13 inches) MULTIMODULE and iSBC
board
.0018
.0036
.024
.116
Weight - 68.05 gm (2.4 ounces)
Offset is measured with user·supplied 10 PPM/oC gain resis·
tors installed.
Input Protection -
± 30 volts.
Electrical Characteristics (from iSBX can·
nectar)
Input Impedance -
20 megohms (minimum).
Vcc = ± 5 volts (± 0.25V), Icc = 250 mAmax
Conversion Speed -
Common Mode Rejection Ratio mum).
Sample and hold microseconds.
Vdd
Vss
50 microseconds (nominal).
60 db (mini-
Environmental Characteristics
Operating Temperature (32° to 140°C)
sample time 15
Shock Tested At -
Connectors -
Class B Specification
Reference Manuals
Interface
Pins
Centers
(Qty)
in
cm
Mating
Connectors
P1 iSBX Bus
36
0.1
0.254
iSBC iSBX
connector
0.254
3m 3415-000 or
T1 H312125 or
iCS 910 cable
50
0.1
142913·001 - iSBX 311 Analog Input MULTIMODULE Board Hardware Reference Manual (NOT
SUPPLIED)
Manuals may be ordered from any Intel sales
representative, distributor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
SBX 311
0 ° to 60°C
Relative Humidity - to 90%
(without condensation)
Aperature - hold aperature time: 120
nanoseconds.
J1 8116
channels
analog
= + 12 volts (± 0.6V), Idd = 50 mAmax
= -12 volts (± 0.6V), Iss = 55 mAmax
Description
Analog Input MULTIMODULE
Board
10-4
iSBX 328
ANALOG OUTPUT MULTIMODULE
EXPANSION BOARD
• Low cost analog output for iSBX M ULTI·
MODULE compatible iSBC Boards
• 0.035% full scale volage accuracy
@ 25°C
• 8 channels output, current loop or
voltage in any mix
• Connector compatible with iCS 910
Analog Termination Panel
• Intel design based on UPI control for
high density and low cost
• 4-20 rnA current loop; 5V unipolar or
bipolar voltage output
• Programmable offset adjust in current
loop mode
• 12·bit resolution
The Intel iSBX 328 MULTIMODULE board provides analog signal output for any iSBC board which has an
iSBX compatible bus and connectors. The single-wide iSBX 328 plugs directly onto the iSBC board, providing eight independent output channels of analog voltage for meters, CRT control, programmable
power supplies, etc. Voltage output can be mixed with current loop output for control of popular 4-20ma
industrial control elements. By using an Intel single chip computer LSI (8041) for refreshing separate
sample-hold amplifiers through a single 12 bit DAC, eight channels can be contained on a single
MULTIMODULE board, for high density and low cost per channel. High quality analog components pro- .
vide 12 bit resolution, 11 bit accuracy, and slew rates per channel of 0.1 volt per microsecond. Program·
ming the iSBX 328 MULTIMODULE board is done via a simple two byte protocol over the iSBX bus. Maximum channel update rates are 5KHZ on a single channel to 1 KHZ on all eight channels. Outputs are
compatable for screw termination of field wiring on the iCS 910 Analog Signal Conditioning/Termination
Panel.
10-5
iSBX 328
FUNCTIONAL DESCRIPTION
The iSBX 328 MULTIMODULE board, shown in
figure 1 is designed to plug onto any host iSBC
microcomputer that contains an iSBXbus connector. The board uses an 8041 UPI device to control
eight analog output channels that may be userconfigured through jumpers to operate in either
bipolar voltage output mode (- 5 to + 5 volts),
unipolar voltage output mode (0 to + 5 volts), or
current loop output mode (4 to 20 mAl applications. Channels may be individually wired for
simultaneous operation in both current loop output and voltage output applications. The outputs
from 50·pin edge connector J1 on the MULTI·
MODULE board are pin-compatible with the iCS
910 SignalConditioninglTermination Panel.
bus connector, to determine if the UPI is ready to
receive updates to analog output channels.
OPERATIONAL DESCRIPTION
The host iSBC microcomputer addresses the
MULTIMODULE board by executing IN or OUT instructions specifying the iSBX 328 MULTIMODULE asa port address. The UPI on the iSBX
328 is initialized to select whether software or
hardware offset is to be used and how many channels will be active. Then a 2 byte transfer to each
active channel sets the 12 bit output value, the
channel selected and the current or voltage mode.
Commands
OUTput Command 7
Initialization of UPlfiSBX 328
OBit
Interfacing Through th.e Intel iSBX Bus
All data to be output through the MULTIMODULE
board is transferred from the host iSBC microcomputer to the MULTIMODULE board via the
iSBX bus connector. The UPI device on the MULTIMODULE board accepts the binary digital data
and generates a 12-bit data word for the Digital-toAnalog Converter (DAC) and a four bit channel
decode/enable for selecting the output channel.
The DAC transforms the data into analog signal
outputs for either voltage output mode or current
loop output mode. Offsetting of the DAC voltage
in current output mode may be performed by the
UPI software offset routine or by the hardware offset adjustments included on the board. The MULTIMODULE board status is available via the iSBX
NN: 0,0 = unipolar configuration
last channel
to be output
software current offset
0,1 = no mixing
1,0 = bipolar configuration
software current offset
OUTput Command -
Data Bytes
7
High Byte
~4--+--+-~~~4--+~
Low Byte
DAC Data
DAC channel
to receive data
1 = SBC generates offset ~_ _ _ _ _ _---J
in current loop mode
o = UPI generates offset
BUFFER
CURRENT·TO·VOlTAGE
....-----,
AMP
8041A
AMP
CONVERTER
ANALOG
OUTPUT
MULTI·
12·BIT
PlEXER
DIGITAl·TO
ANALOG
INTEL'
AMPLIFIER
LOOP
<
}
6'-{>-- V~~~AR~~~O
'-
ANALOG
OUTPUT
B CHANNEL
J1
RESOLUTION
UP\""
SAMPLE/HOLD
CAPACITOR
MULTIPLEXER CONTROL
DEMULTI·
PLEXER.
Figure 1_ iSBC 328 Analog Output MULTIMODULE Board Block Diagram
10-6
AFN·01627A
iSBX 328
INput Command -
Status Buffer Read
Interrupts
No interrupts are issued from the iSBX 328 to the
host iSBC microcomputer. Data coordination is
handled via iSBC software polls of the status
buffer.
SPECIFICATIONS
Outputs - 8 non-isolated channels, each independently jumpered for voltage output or current loop output mode.
Output Impedance - 0.1 ohm. Drives capacitive
loads up to 0.05 microfarads. (approx. 1000 foot
cable)
Voltage Ranges-O to +5 volts (unipolar operation)
- 5 to + 5 volts (bipolar operation)
Temperature Coefficient - 0.005 %/OC
Connectors -
Current Loop Range-4 to 20 mA (unipolar operation only)
Interface
Pins
(Qly)
in
em
P1 iSBX Bus
36
0.1
0.254
J1 8/16
channels
analog
50
0.1
0.254
Output Current- ± 5 mA
mode-bipolar operation)
maximum
(voltage
Load Resistance - 0 to 250 ohms with on-board
iSBX power. 1000 ohms minimum with 30 VDC
max. external supply
Centers
Mating
Connectors
iSBC iSBX
connector
3m 3415-000 or
T1 H312125or
iCS 910 cable
Compliance Voltage-12 V using on-board iSBX
power. If supplied by user, up to 30 VDC max
Physical Characteristics
Resolution -12 bits bipolar or unipolar
Slew Rate-0.1 volt per microsecond minimum
Width -
9.40 cm (3.7 inches)
Single Channel
Update Rate-5KHz
Length -
6.35 cm (2.5 inches)
Height -
1.4 cm (0.56 inch) MULTIMODULE board
only
2.82 cm (1.13 inches) MULTIMODULE
and iSBC board.
Weight -
85.06 gm (3.0 ounces)
Eight Channel
Update Rate-1KHz
AccuracyAccuracy
Ambient
Temp
±0.025% FSR
±0.035% FSR
±0.08% FSR
±0.19% FSR
@ 25'C
@25'C
@ 0' t060'C
@ O' to 60'C
Voltage-Bipolar, typical
Voltage-Bipolar, maximum
Voltage-Bipolar, typical
Voltage·Bipolar, maximum
0.025% FSR
0.035% FSR
0.09% FSR
0.17% FSR
@25'C
@25'C
@O' to 60'C
@O' t060'C
Current
Current
Current
Current
0.07%
0.08%
0.17%
0.37%
@ 25'C
@25'C
@O' to 60'C
@ O' to 60'C
Mode
Voltage·Unipolar, typical
Voltage·Unipolar, maximum
Voltage·Unipolar, typical
Voltage·Unipolar, maximum
Loop, typical
Loop, maximum
Loop, typical
Loop, maximum
FSR
FSR
FSR
FSR
Electrical Characteristics
Vcc = ± 5 volts (± 0.25V), Icc = 140 ma max
Vdd
± 12 volts (± 0.6V), Idd
(voltage mode)
= 45 ma max
= 20Ci ma max
(current loop
mode)
Vss
10-7
-12 volts (± 0.6V), Iss = 55 ma max
iSBX 328
Environmental Characteristics
Reference Manuals
Operating Temperature.;... 0 ° to 60 DC (32°to
1~oq
. .
142914·001 - iSBX 328 Analog Output MULTIMODULE Board Hardware Reference Manual
(NOT SUPPLIED)
Manuals may be ordered from any Intel sales
representative, distributor office or from .Intel
Literature Department, 3065 Bowers Avenue, Santa Clara, California 95051
Relative Humidity - to 90 % (without condensation)
Shock Tested At -
Class B specifications
ORDERING INFORMATION
Part Number
SBX 328
Description
.
Analog Output MULTIMODULE
Board
10-.8
System Packaging
and Power Supplies
and Service
11
iSBC 604/614 or (pSBC 604/614 *)
MODULAR CARDCAGE/BACKPLANE
• Interconnection on MULTIBUS system
bus and housing for up to four Intel
iSBC boards
• Cardcage mounting holes facilitate
interconnection of units
• Strong cardcage structure helps
protect installed iSBC. single board
computers and expansion boards
against warping and physical damage
• Compatible with 3.5·inch RETMA rack
mount increments
• Dual backplane power supply
connectors and signal line termination
circuits on iSBC 604 Cardcagel
Backplane
• Connectors allow interconnection of
two or more cardcage/backplane
assemblies
The iSBC 604 and iSBC 614 Modular Cardcage/Backplane units provide low-cost, off-the-shelf housing for OEM products using two or more Intel single board computers. Each unit interconnects and houses up to four boards. The base
unit, the iSBC 604 Cardcage/Backplane, contains a male backplane PC edge connector and bus signal termination circuits, plus power supply connectors. It is suitable for applications requiring a single unit, or may be interconnected
with the iSBC 614 Cardcage/Backplane when more then one cardcage/backplane unit is needed. The ISBe 614 Cardcage/Backplan~ contains both male and female backplane connectors, and may be interconnected with iSBC 604/614
Cardcage/Backplane units. Both units are identical, with the exception of the power connectors and bus signal terminator features. A single unit may be packaged in a 3.5-inch RETMA rack enclosure, and two interconnected units may
be packaged in a 7-inch enclosure. The units are mountable in any of three planes.
·Same product, manufactured by Intel Puerto Rico, Inc.
11-1
AFN'()0282A
iSBC 604/614
1_ _- - - 12. 8 7 5 - - - _
-I
B.SO
j
'SBC61.0NLY
1.1
2.750
.300 ................
SIDE VIEW
I"
I
END VIEW
-I
".20
l-Dtt~:t1\ +
t
1'1
.42 35....
.
II
'SBCOO'ONLY
13.500
.,
.120 DIA. X .60 DEEP .
-.4 HOLES
:
BOTTOM VIEW
Figure 1. ISBC 604/614 Modular Backplane and Cardcage Dlinenslons
Physical Dimensions
SPECIFICATIONS
Backplane Characteristics
Bus Lines - All MULTIBUS system bus address, data,
and command bus lines are bussed to all four connec·
tors on the printed circuit backplane
Power Connectors - for ground,
-12V, -10V power supply lines
Height Width Depth Weight -
8.5 in. (21.59 cm)
14.2 in. (36.07 cm)
3.34 in. (8.48 cm)
35 oz (992_23 grn)
+ 5V, - 5V, + 12V,
ISBC 604 - Bus signal terminators, backplane male PC
edge connector only, and power supply headers
ISBC 614 -
Environmental Characteristics
Backplane male and female connectors
Operating Temperature - O·C to 55·C
Mating Power Connectors
Connector
AMP
Molex
87159-7
Pin
87023-1
Polarizing key
87116-2
Connector
09-50-7071
Pin
08-50-0106
Polarizing key
15-04-0219
Reference Mahual
Note
1_ Pins from a given vendor may only be used with connectors from the
same vendor.
9800708 - iSBC 604/614 Cardcage Hardware Reference
Manual (NOT SUPPLIED)
ORDERING INFORMATION
Part number
Description
Part Number
SBC 604
Modular Cardcage/Backplane (Base
Unit)
SBC 614
11-2
Description
Modular Cardcage/Backplane
(Expansion Unit)
AFN-00282A
iSBC 660
SYSTEM CHASSIS
• Eight-slot card cage and backplane for
iSBC computers and expansion
boards
• Attractive, versatile pop-off front panel
• 19-inch wide rack mountable chassis
• Heavy duty power supply with all
standard iSBC voltages
• Horizontal board mounting for
compactness
• Compatible with all Intel single board
computers
• Forced-air cooling
• 110/220V, 50/60 Hz operation
The iSBC 660 System Chassis is an attractive, 7-inch high system chassis designed for use with Intel OEM computers.
It has eight slots for single board computers, memory, 110, or other expansion modules. The iSBC 660 is ideal for applications requiring multiple board solutions. DC power output is provided at + 12V, + 5V, -12V, and - 5V levels. The
current capabilities of each of these output levels have been chosen to provide power over a O·C to 50·C temperature
range for the majority of applications requiring combinations of computers, memories, peripherals, and other 110
capabilities. Current limiting and over-voltage protection is provided at all outputs. Standard logic recognizes a
system AC power failure and generates a TTL signal for use in power-down control. For user convenience, a reset
switch is provided on the front panel. The reset signal generated and sent to the system bus can be used for external
system control.
11-3
AFN-00285A
iSBC 660
FRONT VIEW
1---------'-·,9.00--------1'1
11.38
I
1
0--
-11'1
I
2.10
q
I
i==
:=TI
~61
69
t 145
I I
-1"5r.. _ 1
1.9S!TOP VIEW
I~__~__________~~L
o
o
18.9
..
Figure 1. iSBCSystem Chassis Dimensions
SPECI FICATIONS
Remote Sensing regulation.
Electrical Characteristics
Output Ripple and Noise mum (DC to 500 kHz).
Input Power
Frequency: 50 Hz ± 5%, 60 Hz± 5%
Voltage: 115V ±10%,230V±10%, 215 VAC.±10%,
100 VAC ± 10% via user configured wiring options
Output Power
Power
Output Current
(Max)
+ 12V
+5V
-5V
-12V
4.5A
30A
U5A
1.75A
Current Limit
Ove,·Voltage
(Amps)
Protection
5A
15V± 1V
6.2V ± OAV
-6.2V ± OAV
-15V ± 1V
3.6
2.1
2.1
Combined Line/Load Regulation - ± 1% at ± 10%
static line change and ± 50% static load change, meas·
ured at the output connector (± 0.2% measured at the
power supply under the same conditions).
Provided for
+5
VDC output line
10 mV peak·to·peak maxi·
Output Transient Response ± 50% .Ioad change.
Less than 50 I'S for
Output Transient Deviation - Less than ± 5% of linitial
voltage for ± 50% load change.
Power Failure Indication (AC Low) - A TTL open collec·
tor high signal is provided when the input voltage drops
below 90% cif its nominal value. DC voltages will remain
within 5% of their nominal values for 3.0 milliseconds
(minimum) after AC low goes true.
The "AC Low" signal will reset to a TTL low level when
the AC input voltage is restored and after all output volt·
ages are within specified regulation.
The "AC Low" threshold is adjustable for optimum
power·down performance at other input combinations
(i.e. 100 VAC, 215 VAC, 50 Hz).
AFN-00285A
iSBC 660
Humidity -
Up to 90% relative, non-condensing
I/O connectors for single board computers
Schematics for cardcagelbackplane, chassis
Outline drawing
Physical Characteristics
Height Width
7 in. (17.8 em)
Reference Manuals
At Front Panel: 19 in. (48.3 em)
Behind Front Panel: 17 in. (43.2 em)
Depth - 20 in. (50.8 em) with all protrusions
Equipment Supplied
9800505A - iSBC 660 Hardware Reference Manual
(NOT SUPPLIED)
9800505 - iSBC 660 System Chassis Hardware Reference Manual (NOT SUPPLIED)
9800803 - iSBC 640 Power Supply Hardware Reference
Manual (NOT SUPPLIED)
9800708 - iSBC 604/614 Cardcage Hardware Reference
Manual (NOT SUPPLIED)
iSBC 660 System Chassis with iSBC 640 Power Supply,
iSBC 604/614 Cardcage/Backplane, dual fans, pop-off
front panel
Connector pack with RS232C cable (terminal/modem interface to single board computers), two 50-pin parallel
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Environmental· Characteristics
Temperature
Operating: O°C to 50°C
Non-Operating: - 40°C to
+ 85°C
ORDERING INFORMATION
Part Number
Description
SBC 660
System Chassis
11-5
AFN·00285A
iSBC™ 680/iSBC 681
MUL TISTORE™ USER SYSTEM PACKAGE
• Complete system package for user·
selected Intel® iSBC boards and up to
two 8" peripheral drives
• Available in table·top (iSBC 680 package) or rack-mount (iSBC 681 package)
configurations
• Holds up to six iSBC boards compatible
with the MULTIBUS® system bus
• Designed to meet UL safety requirements and FCCIVDE EMI limits
• Supplies::!: 5, ::!: 12, ::!: 24 VDC to power
boards and peripheral drives
• Power supply provides 8 msof powerfail warning, plus a real·time clock
The iSBC 680/iSBC 681 Multistore User System Package products make available to the OEM a new way to
assemble his systems for those applications requiring rotating memory or other peripherals built in the 8"
ind.ustry-standard form factor. The Multistore package allows the OEM to select the iSBC boards required
for the job, and to independently choose from a wide variety of peripherals to complete the system. The
switching power supply provides sufficient current at all voltage levels to power most manufacturers'
drives, as well as furnishing the standard MULTIBUS system bus voltages to the iSBC boards in the
package's cardcage. The appearance of the packages provides an attractive addition to the OEM's system,
while the construction allows easy access to the interior for service.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, MULTIBUS, iAMX, isse, iSBX, MULTIMODULE, Multlstore and iCS.lntel
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
© INTEL CORPORATION, 1981
11-6
July, 1981
143884
.
' ./
intJ
iSBC™ 680/iSBC 681 MULTISTORE™
FUNCTIONAL DESCRIPTION
Physical Packaging
PACKAGE CONSTRUCTION - The Multistore
package is constructed entirely of metal, and all
cover pieces are gasketed to completely contain
high-frequency noise from the power supply and
the system boards within the package.
drives, allowing the drives to be installed/removed
from the front of the package (Figure 2).
Blank covers with ventilation slots are provided
with the package for the unused peripheral positions and for those peripherals not furnished with a
cosmetic cover.
MOUNTING OPTIONS - The iSBC 680 package is
a table-top structure; the iSBC 681 package is the
rack-mount version with slides attached to the side
panels and a wider trim bezel to cover the. mounting rails.
COOLING - The boards and peripherals installed
in the package are cooled by air brought in at the
bottom of the front panel and drawn through the
power supply, with the heated air discharged to the
rear of the package.
CARDCAGEIBACKPLANE - The cardcage/backplane accepts up to six iSBC boards compatible
with the Intel MULTIBUS system bus (Figure 1).
Figure 2. iSBC 680 Package with Winchester Drive
Pulled Out for Servicing
System Power
BASIC POWER SUPPLY - The supply provided
with the package is an advanced-technology
switching power supply, offering large current
capabilities over the six DC voltages supported.
Sockets for drive power are located on the power
supply bulkhead at the rear of the peripheral cavity
(Figure 3).
Figure 1. Boards Mounted in theCardcage of the
iSBC 680 Package
PARALLEL PRIORITY - Up to six bus masters
may be. installed in the package because of the
parallel priority logic which is an integral part of the
backplane.
ENHANCED NOISE IMMUNITY - The integrity of
the package is enhanced by a new backplane for
the system boards, which offers improved noise
immunity through advanced design techniques.
PERIPHERAL MOUNTING - Two positions are
provided for mounting of peripheral drives conforming to the de facto industry standard for size
and mounting pOints on 8" peripherals. The rnounting system provides slides for the bases of the
Figure 3. Power Supply. Showing Three Power
Connectors (Two for Peripherals, One
for the Cardcage/Backplane)
~ 1-7
AFN·01982A
iSBC™ 680/iSBC 681 M ULTISTO RETM
INTERNATIONAL ACCEPTANCE"':" The package
is a UL-recognized component, and 'it has been
designed to meet the safety requirements of CSA
and VDE.
. . ..
DEVICE INTERFACE - Witli tlie package designed
for maximum suppression of both EMI and ESD
(electrostatic discharge) the preferred interface
between the. installed boards and external devices
iswith shielded cablesisolaled through .usersupplied connectors installed in the panel provided
at the rear of the package (Figure 4). The six cut:
outs, sized for 50-pin cormectors, are furnishe'd
.
with individual cover plates.'
MEETS EMI STANDARDS - The FCC standards
for conducted and radiated EMI (electromagnetic
interference), as well as the VDE requirements
(0871/0875), are met by the package.
POWER-FAIUAUTO-RESTART SYSTEM The
package gives the user a set of logic signals providing advanced warning of power failures and protection .for· battery backed-up memory as the DC
voltages fall. It also furnishes a real-time clock
derived from the line frequency, thus ensuring
long-term stability in user time-keeping.
User Interface
USER CONTROLS - At the front of the package
the user has access to both the AC power switch
(with integral circuit breaker) and controls and indicators for the microcomputer system itself.
"RESET" and "INTERRUPT" switches are prpvided, along with "RUN" and :'HALT'~ LED indi;
cators_
Figure 4_ iSBC 680 Package Showing External
Device Connection Panel
1 ms of iS8uanceofPFIN/; tile ±.5and ± 12 VDC
outputs will remain within specification for at least
8 ms, after'which MPROI will go true to protect nonvolatile mElI1'ioties from being written into as .DC
power fails.'
.
SPECIFICATIONS
Input Power
Frequency -
47-66 Hz'
Voltage - 90-126 VAC/180-252 VAC, single phase
(user-selectable).
Periodic and Random Deviation (PARD) peak-to-peak, all outputs.
.
System Clock ~ ThepoVliersupply provides a 2 x
line frequency clock output, available on the P2
connector of the cardcage/backplane: ..:
50 mV
Output Regulation (Combined Line and Load) ± 1% under any conditions of AC input voltage
variation (within operational range) and output load
change.
Nominal
Voltage
Lille Transient Tolerance - A signal of up to 1000
VDC, with a pulse width of up to 50 P.s, Will have no
affect on system operation.
+5
-5
. + 12
~12
Output' Power
+24
-24
Power Fail Indication - PFINI is generated approximately 8 ms after the input drops below
901180 VAC. PFINI is available on the P2 connector
of thecardcage/backplane for generation of an interrupt. The ± 24 VDC outputs will go to zero within
Current1
(Max
Amps)
30.0
2.0
2.9.
.3.0
7.8
1.6
Typical Peripheral"
Power Requlrements 2
8"
"
Winchester
Diskette
Drive
5.1
0.25
.1.0
0.07
-
0.7
4.0
-
.,-
-
1.8
...,.
NOTES:
1. The maximum pqwer available from the supply, from all outputs, is 300 watts.
.
. . . . . ' ..
2. These are wcirst~case data, drawn from man'ufacturers' data
"sheets:'
.
.
. . . . . ..
.
11-8
AFN.()1982A
"
,
iSBC™ 680liSBC 681 MULTISTORE™
Humidity - 20% to 80% RH, non-condensing for
the chassis and typical peripheral content.
Physical Characteristics (Figure 5)
16.8/19.0 in. (42.5/48.3 cm)
iSBC 680liSBC 681 Packages
Length - 21.5 in. (54.6 cm)
Height - 12.2 in. (31.1 cm)
Weight - 40 Ib (18.2 kg) (approximate)
Width -
NOTE: The photos of the Multistore packages in this data sheet
show boards, an 8" Winchester hard disk drive, and an 8" flexible disk drive installed. The packages do not include these
boards and peripherals; they are shown in the photographs to illustrate physical arrangements in the Multistore package,
Equipment Supplied
Board Slots - Six @0.665 in. on centers between
boards. The board in the top slot may contain any
iSBX and/or iSBC MULTIMODULE boards.
iSBC 680 Chassis, -
Includes table-top package
with aluminum sheet metal, 6-slot cardcage/backplane, combination On/Off switch and circuit
breaker, peripheral mounting hardware (user must
supply power and signal cabling for peripherals),
and power supply with AC power cord.
Peripheral Size - The drives must fit within an
envelope 8.55 in, high by 14.25 in. deep by 4.65 in.
wide.
Data Separator Board Location - A space is provided within the package to secure a Winchester
drive data separator board, if required.
Same as iSBC 680 chassis,
plus rack-mount chassis slides and wider bezel.
iSBC 681 Chassis -
Reference Manual
Environmental Characteristics
iSBCTM 680/681 Multistore™ Chassis
Hardware Reference Manual (NOT SUPPLIED)
162432 -
The inlet air
temperature, with peripheral drives installed, may
not exceed 35°C. This is for the protection of the
peripherals, as both diskette and Winchester drives
have ambient maximums of 40°C in most instances.
Ambient (Inlet) Air Temperature -
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara, CA
95051.
CARDCAGEI
BACKPLANE
PERIPHERAL
DRIVE
Figure 5. Physical Dimensions of the iSBC 680 Multistore User System Package
ORDERING INFORMATION
Part Number
Description
SBC 680
Multlstore User System Package
(Table-Top)
SBC 681
Multlstore User System Package
(Rack-Mount)
11-9
iSBC 635
POWER SUPPLY
• Compact single chassis
• ± 5V and ± 12V iSBC 80 and iSBC 86
system power
• Sufficient power for one fully loaded
Intel single board computer plus
residual power for up to three Intel
i$BC expansion boards
• Current limiting and overvoltage
protection on all outputs
• DC power cables and connectors mate
directly to iSBC 604 Modular Cardcage/
Backplane assembly
• "AC low" power failure TTL logic level
output provided for system powerdown control
• 100V, 115V, 215V, and 230V AC
operation
• 50 Hz or 60 Hz input
The iSBC 635 Power Supply provides low cost, off-the-shelf, single chassis power generation for OEM products using
Intel single board computers. The iSBC 635 supply, provides regulated DC output power at + 12V, + 5V, -12V, and
-12V levels. The current capabilities of each of these output levels have been chosen to provide power over a O·C to
+ 55°C temperature range for one Intel single board computer fully loaded with 1/0 line terminators and drivers and
EPROMs, plus residual capability for most combinations of up to threeiSBC memory, 1/0 or combination expansion
boards. Current limiting and overvoltage protection is provided on all outputs. Access for AC input Is provided via a
standard 4-pin keyed connector. DC output power levels are provided on cables with keyed connectors directly compatible with the iSBC 604 Modular Cardcage/Backplane assembly. The iSBC 635 supply includes logic whose purpose
'
is to sense system AC power failure and generate a TTL signal for clean system power-down control.
11-10
AFN'()()284A
iSBC635
PO
P6
~p
CD
HARNESS LENGTHS ARE FROM CENTER OF SURFACE
"A" TO CONNECTOR
a
b.
DC OUTPUT 24 ,05INCHESTOP6CQNN.
DC OUTPUT 16 '05 INCHES TO PO CONN.
e AC INPUT 12 . 0 5lNCHES TO P2 CONN
Q)
o
LOCATION OF "AC LOW" SIGNAL CONNECTOR IS WITHIN
CROSS·HATCHED VOLUME, ORIENTATION MAY VARY
ALL FOUR MOUNTING HOLES THREADED FOR 1024
MACHINE SCREWS.
$--------------
I
I
I
I
I
I
I
I
t
I
I
I
I
r-~nW~
I
L~
L20-i
Figure 1. ISBC 635 Mounting Information
SPECIFICATIONS
Electrical Characteristics
Mating Connectors 1
Input Power - Frequency: 47 - 63 Hz. Voltage (Nominal)
(Single Phase): 100, 115, 215, or 230 VAC +10%
AC Input
03·09-1042 or equivalent
Output Power:
02·09-1118 or equivalent
(18 to 22 gauge wire)
Nominal
Current
Current limit
Max Short
Over-Voltage
Voltage (AMPS)(MAX) Range (AMPS) Circuit (AMPS)
Protection
DC Output 2
I
Header
Molex
09-66-1071
AMP
87194-6
Molex
09-50-7071
AMP
87159-7
+12
+ 5
- 5
-12
"AC Low" Control
Connector
Polarizing key
I
Pin
Molex
15-04·0219
AMP
87116-2
Molex
08·50-0106 (18 to 22 gauge wire)
AMP
87023·1 (18 to 22 gauge wire)
1. Pins from a given vendor may only be used with connectors from the
same vendor.
2. iSBC 635 DC output connectors are directly compatible with power
input power connectors on ISSC 604 Modular Cardcage/Backplane
assembly. Two connectors are provided.
Height - 3.19 in. max (8.11 cm)
Width - 6.03 in. max (15.32 cm)
Depth - 12.65 in. max (32.12 cm)
Weight - 13 Ib (5.90 kgm)
2.1-3.0
14.7-21.0
0.9-1.4
0.8-1.2
1.0 (Foldback) +14 to +16 V
7.0 (Foldback) +5.8 to +6.6 V
1.4
-5.8 to -6.6 V
1.2
-14 to -16V
Combined Line/Load Regulation - ±1'10 at ±10% static
line change and ±50% static load change, measured at the
output connector (±0.2% measured at the power supply
under the same conditions).
Remote Sensing - Provided for +5VDC output line
regulation.
Output Ripple and Noise -1 0 mV peak-to-peak maximum
(DC to 500 KHz)
Output Transient Response - Less than 50 f.lsec for ±50%
load change
Output Transient Deviation - Less than ±5'10 of initial
voltage for ±50% load change.
Notes
Physical Characteristics
2.0
14.0
0.9
0.8
Power Failure Indication (AC Low) - A TTL open collec·
tor high Signal is provided when the input voltage drops
below 90% of its nominal value. DC voltages will remain
within 5% of their nominal values for 3.0 milliseconds
(minimum) after AC low goes true.
11-11
AFN·00284A
iSBC635
The "AC Low" signal will reset to a TIL low level when
the AC input voltage is restored and after all output
voltages are within specified regulation.
Equipment Supplied
The "AC Low" threshold is adjustable for optimum
powerdown performance at other input combinations
(Le. 100 VAC, 215 VAC, 50 Hz).
Environmental Characteristics
Operating Temperature moving air
Non·Operating -
ODC to
- 40 DC to
+ 55 DC with
35 CFM
+ 85 DC
iSBC 635 Power Supply with AC and DC cables and con·
nectors attached as shown in Figure 1.
Reference Manual
9800298C - iSBC 635 Power Supply Hardware Refer·
ence Manual (includes schematics) (NOT SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
ORDERING INFORMATION
Part Number
Description
SBC 635
Power Supply
11-12
AFN·OO284A
iSBC 640
POWER SUPPLY
• Compact single chassislslide rail
mounts in iCS 80 Industrial Chassis or
OEM environments
• ± 5V and ± 12V iSBC 80/86 power
• Sufficient power for 8-12 MULTIBUS
computer, memory, and peripheral
boards
• DC power cables and connectors mate
directly to iSBC 604 Modular Cardcagel
Backplane assembly
• Current limiting and overvoltage
protection on all outputs
• "AC low" power failure TTL logic level
output provided for system power-down
control
• 100,115,215, and 230V ACoperation
• 50 Hz or 60 Hz input
The iSBC 640 Power Supply provides low cost, off-the-shelf, single chassis power generation for OEM and industr'ial
system products using Intel single board computers. The ISBC 640 supply provides regulated DC output power at
+ 12V, + 5V, - 5V and -12V levels. The current capabilities of each of these output levels have been chosen to provide
power over a O°C to + 55°C temperature range for one fully loaded Intel single board computer; plus residual capability
for most combinations of up to eleven iSBC memory, 1/0, or combination expansion boards. Current limiting and overvoltage protection is provided on all outputs. Access for AC input is provided via a standard 4-pin keyed connector. DC
output power levels are provided on cables with keyed connectors directly compatible with the iSBC 604/614 Modular
Backplane/Cardcage assemblies. The iSBC 640 supply includes logic whose purpose is to sense system AC power
failure and generate a TTL signal for clean system power-down control.
11-13
AFN'()1275A
iSBC 640
SPECI FICATIONS
DC Output2
Electrical Characteristics
Housing
Input Power
Frequency: 50 Hz±5%, 60 Hz±5%
Voltage: 115V ± 10%, 230V ± 10%, 215VAC± 10%,
100VAC± 10%
Via user configured wiring options
Molex
Pins
Key
Output Power
Nominal
Current
Current Limit Short Circuit
Voltage (Amps)(Max) Range (Amps) (Amps)(Max)
+12V
+ 5V
- 5V
-12V
iI.5A
30A
1.75A
1.75A
4.7- 6.8
3.1.5-45.0
1.8- 3.2
1.8- 3.2
2.3
15.0
0.9
0.9
Molex
Amp
Amp
Molex
Amp
26'()3·3071
3-87025-3
08-50-0187
or
08-50-0189
87023-1
15'()4-9209
,87116-2
Compatible with'Molex 09-66-1071 Header
Notes
1. Pins from given 'vendor may only be used with connectors from the
same vendor.
2. iSBC 640 DC output connectors .are directly compatible with Input
power conDe,ctors on ISBC ,604 Modular, Cardcage/Backplane
assembly. Four connectors are' provided.
Overvoltage
Protection
15V± 1V
6.2V±0.4V
-6.2V±0.4V
-15V±1V
Combined Line/Load Regulation - ±1% at ±10% static
line change and ±50% static load change, measured at the
output connector (±0.2% measured at the power supply
under the same conditions).
Remote Sensing - Provided for +5 VDC output line
regulation.
Output Ripple and Noise -10 mV peak-to-peak maximum
(bC to 500 KHz)
Output Transient Response - Less than 50 I'sec for ±50%
load change.
Output Transient Deviation - Less than ± 10% of initial
v,oltage for ± 50% load change.
Power Failure Indication (AC Low) - A TTL open
collector high signal is provided when the input voltage
drops below 90% of its nominal value. DC voltages will
remain within 5% of their nominal values for 3.0
milliseconds (minimum, 7.5 ms typical) after AC Low goes
true.
The ';AC Low" signal will reset to a TTL low level when
the AC input voltage is restored and after all output
voltages are within specified regulation.
The "AC Low" threshold is adjustable for optimum'
powerdown performance at other input combinations
(i.e. 100 VAC, 215 VAC, 50 Hz).
Physical Characteristics
Height Width Depth Weight -
6.66 in_ max_ (16_92 cm)
8_19 in_ max. (20_80 cm)
12.65 in_ max_ (32_12 em)
30 Ibs_ max (13_63 kg)
Environmental Characteristics
,Temperature - O·C to 55·C with 55 CFM moving air
Non-Operating - - 40·C to + 85·~
Equipment Supplied
.
iSBC 640 Power Supply with AC and DC cables with
keyed connectors.
..
Reference Manuals
9800803 - iSBC 640 Power Supply Hardware Reference
Manual (includes schematic and assembly drawings)
(NOT SUPPLIED)
9800798 - iCS 80 Systems Site Planning and Inst,allation Manual (for installation of iSBC 640 supply into iCS
80 Industrial Chassis) (NOT SUPPLIED)
Mating Connectors'
Reference manuals are shipped with each product only if
designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
AC Input
03'()9·2042 or equivalent
02'()9·2118 or equivalent
(18 to 22 gauge wire)
ORDERING INFORMATION
Part Number
Description
SBC 640
Power Supply
11-14
AFN.()1275A
iSBC 665/iSBC 645™
SYSTEM CHASSIS AND POWER SUPPLY
• Intel MULTIBUSTM system bus 4·slot
packaging
• Complete package of rack·mounting,
cooling, controls, and power
• Advanced 110 watt switching power
supply generates ± 5, ± 12 VDC
• Meets U.S. and International EMI and
safety requirements
• Wide AC voltage margins keep systems
running during "brownouts"
• Front panel switches, indicators, and
adjustments for operational and service
convenience
• Power sense circuitry interrupts
system 6 msec prior to power failure
The Intel iSBC 665liSBC 645 Chassis system provides the MULTI BUS system bus user with a compact set
of products offering new standards in 4-slot rack-mount packaging. A high-efficiency switching power
supply allows use of 115/230 VAC (+15/-20%), with large surge and noise components, to deliver
smooth, stable DC power to the OEM board load. Advanced power-fail sense and restart logic gives the
user sufficient time to bring the system to an orderly shutdown in the event of AC mains power failure.
Mechanical design features include EMI suppression and a retainer/cover for system boards and I/O edge
connectors.
Bre
The following
trademarks of Intel Corporation and may be used only to describe Intel products: CREDIT. Index, Intel, Insite. Intellec, Library Manager. Megachassls,
Mlcromap, MULTIBUS, PROMPT, U~I.IlScope, Promware, MeS, ICE, IRMX, ISBC,ISBX. MULTIMOOULE and JCS, and the combination of MeS, ICE, iSBC, iSeX, iRMX or ICS, and
a numerical suffix. Intel· Corporation assumes no responsibility for the USa of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are
Implied.
©INTELCORPORATION.1981
11-15
April 1981
143581
inter
iSBC 665/iSBC 645™
Table 1. iSBC 665™ Chassis/iSBC 645™ Power
Supply Control Panel Functions
FUNCTIONAL DESCRIPTION
iSBC 665™ System Chassis
Label
The iSBC 665 Chassis is a complete microcomputer package providing .four board slots in a
3.5" vertical space.
Controls
DC ONIOFF
RESET
RACK MOUNT PACKAGE
The iSBC 665 Chassis mounts in a 19" EIA standard rack, using its front panel and hangers at the
rear of the chassis to secure it to both sets of rails
in the cabinet. If slide mounting is preferred, a tray
with slides should be used as a platform for the
chassis. The physical integrity of the system is
enhanced by addition of a connector retainer at
the (rear-facing) opening of the cardcage.
INTRPT
Indicators
HALT, RUN
ACON
INTEGRAL COOLING
OV
The fan on the power supply is utilized to draw
ambient air across the boards prior to its being
used to cool the supply.
AC LO
Adjustments
+5
-V
FRONT PANEL
The front panel of the iSSC 665 Chassis forms a
complete control center for the system installed
in the chassis (see Figure 1).
AC LO
iSBC 645 Power Supply
The 110-watt supply of the iSBC 665 Chassis is
designed to provide advanced features to the Intel
system builder who faces complex power supply
and chassis requirements.
Function
Controls all DC power to ih~ chassis.
Generates RESETI signal to pin 14
of P1 (MULTI BUS system bus)
backplane.
Generates INTI signal to pin 42 of
P1.
Indicate status of system CPU
board.
Indicates ACpower present in supply (AC power switch is located at
the rear of the supply).
Indicates power supply shut-down
due to an overvoltage condition on
+ 5 or ± 12 VDC outputs.
Indicates that AC voltage is below
the operating range and the supply
has shut down.
Adjusts + 5 VDC output voltage.
Adjusts negative adjustable voltage; set to - 5 VDC at the factory.
Adjusts AC sense threshold at
which the system generates powerfail signals; set to 88/176 VAC at
factory.
INTERNATIONAL ACCEPTANCE
The supply is a UL-recognized component; the
supply/chassis combination is also designed to
meet the safety requirements of CSA (Canada)
and VOE (Germany) as industrial, computer, and
office equipment. 1
EMI STANDARDS
The FCC standards for conducted and radiated
EMI (electromagnetic Interference) are met by the
supply, thus the chassis packaging will enhance
the OEM's efforts to assemble systems which
must comply'with the FCC Part 15 Rules. In addition, the supply/chassis design meets the most
stringent VOE requirements (0871/0875) for conducted and radiated EMl.l
NOTE:
1. CSA and VDE testing have not been officially completed;
testing at Independent laboratories Indicates that these
safety and EMI requirements are met. Official testing
should be completed In late 1981.
Figure 1. ISBC 66.5™ Chassis Front
Panel Controls
11-16
AFN'()1830A
iSBC 665/iSBC 645™
BROWNOUT PROTECTION
POWER pNE CLOCK
The wide AC voltage input range allows microcomputer systems packaged in the chassis to.
function normally at extremely low AC voltage
supply levels.
A clock signal is developed from the AC line at
twice the line frequency; this gives the system
user an extremely accurate time base.
;' .,<,
'.
POWER-FAIL WARNING AND RECOVERY'
In the event of a complete power failure, an interrupt is generated 6 ms prior to the supply's issu- .
ing a subsequent memory protect signal, giving
sufficient time for execution of a user program to
bring the entire system to an orderly shLJt-down.
POWER TRANSIENT TOLERANCE
The supply provides immunity for the system from
the high-voltage transient surges and spikes seen
in AC power systems. The supply itself provides
this isolation with a metal-oxide varistor (MOV)
and line filter in the input circuitry.
.' Figure 2." iSBC 645™ Power Supply
i.'·'
SPECIFICATIONS
INPUT POWER
Frequency: 47-66 Hz
Voltage: 115/230 VAC Single Phase
Range: 90 to 126 VAC/180 to 252 VAC
Consumption (Max.): 230 watts
PERIODIC AND RANDOM DEVIATION (PARD)50 millivolts peak·to·peak, all outputs.
LINE TRANSIENT TOLERANCE - A signal of up
to 1000 VDC, with a pulse width of up to 50
microseconds, will have no affect on operation.
OUTPUT POWER
Current 2 Current
Limit
(Max.
Point
Amps)
(Amps)
"
OUTPUT REGULATION (COMBINED LINE AND
LOAD) - ± 1 % under any conditions of AC mains
voltage variation (within operational range) and
output load change ...
Electrical Characteristics
Nominal
Voltage
,
Overvoltage
Protection 3
+5
+ 12
-12
15
18.75
5.25 to 6.25
3
1
3.75
1.25
12.6 to 15.0
-12.6 to -15.0
- Adjustable4
1
1.25
N/A
NOTES:
2. Total output power is 110 watts; a maximum of 128 watts Is
available, but proper operation of the power·fall circuitry Is
not guaranteed above 110 watts.
3. A minimum load Is required on the + 5 voe output; this load
must be at least V. the sum of the loads (In watts) of the
remaining three outputs.
4. - 2.5 to - 12 voe; factory set to - 5 voe.
POWER FAIL INDICATION - An AC low condition generates ACLO and PFINI after AC voltage
drops belOW the allowed voltage range. These
signals are available on the P2 connector to
generate interrupts. The DC voltages will remain
within specifications for 6 milliseconds (worst
case) following these interrupts, after which
Memory Protect (MPRO/) will go true.
OUTPUT VOLTAGE TEMPERATURE COEFFICIENT - 0.03% per ·C over the operating range.
SYSTEM CLOCK - 2x line frequency clock
signal available on P2 connector.
AFN.()1830A
ISBC 66511SBC 645™
Physical CharaCteristics (See Figure 3)
142918 - iSBC 645™ Power Supply Hardware
Reference Manual
WIDTH - 19.0 In. (48.3 cm)
LENGTH - 16.25 In. (41.3 cm)
HEIGHT - 3.5 In. (8.9 cm)
WEIGHT - 12.0 Ib (5.4 kg)
9800708 - iSBC 6041614™ Modular Cardcagel
Backplane Hardware Reference Manual
Environmental Characteristi.cs
Manuals may be ordered from any Intel sales representative, distribution office, or from Intel literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.
AMBIENT (INLET) AIR TEMPERATURE
Chassis: O·C to 55·C; Power Supply: O·C to 65·C
(Full Rated Output)
9088683 -
Intel MULTIBUS Specification
STANDARD REAR SUPPORT BRACKETS
HUMIDITY - Up to 95% non-condensing.
L-~---I
Equipment Supplied
ISBC 665 SYSTEM CHASSIS - Includes iSBC 645
Power Supply, iSBC 604 Modular Cardcagel Backplane, connector retainer, schematics for
cardcage/backplane, chassis, and power supply.
ISBC 645 POWER SUPPLY - Includes power supply, schematics for supply.
Reference Manuals (Not Supplied)
142836 - ISBC 665™ System Chassis Hardware
Reference Manual
Figure 3. ISBC 665™ System Chassis
PhYSical Dimensions
ORDERING INFORMATION
Part Number
Description
SBC 665
SBC 645
System Chassis
Power Supply (110 Watt)
l1c18
3.In
(o.31m)
,-_.-
iMBX 100/110/120
MULTIBUS® EXCHANGE
HARDWARE SUBSCRIPTION SERVICE
• Monthly product updates
• History of Engineering Change Orders
• Offers full update alternatives documentation, parts kit, and factory
update
• Customized to the subscriber's selec·
tion of Intel@ board level products
• Timely announcements of techno·
logical and product developments
• Ancillary Notes clarifying and correct·
ing product documentation
• Available for iSBC,TM ICS,rM and iSBX™
products
The Intel MULTIBUS EXCHANGE hardware subscription service consists of a monthly update publication
which provides summary descriptions of Engineering Change Orders that alert and inform subscribers of
all the latest developments and/or improvements applicable to their Intel board level products. In addition,
the update contains order numbers and prices for optional update parts kits. This timely service allows
users to closely track product changes and, by evaluating or implementing these changes, to take advan·
tage of technological and product developments.
The following are trademarks of Intel Corporation and may be used only to describe Intel producta: Intel, CREDIT, Indlx, Inlltl, Intillec, LIbrary Manager, Mlgachaslls,
Mlcromap, MULTI BUS, PROMPT, UPI, ~COPI, Promware, MCS, ICE, IRMX, ISaC, ISaX, MULTI MODULE and ICS.lntel Corporation aslum•• no responsibility for the use of any
circuitry other than circuitry embodied in an Intel prOduct. No other circuit patent IIcensls are Implild.
© INTEL CORPORATION. 1981
11-19
October, 1981
Onlo, Number: 21027HOI
intJ
IMBX 100/110/120
PRODUCTS
The MULTIBUS EXCHANGE hardware subscription service supports Intel manufactured Single
Board Computer, Industrial Control Series and
MULTIMODULE products. Users can subscribe to
any combination of over 60 products.
his product. Subscribers receive the monthly update even if no changes have occured to their products.
ORDERS
New subscribers receive a history (back to the
earliest purchase date of each product) for each
subscribed-to product and a handsome notebook
in which future updates may be orderly stored.
Orders for the MULTIBUS EXCHANGE are a combination of a base (iMBX 100) order, plus orders for
each product to be included (iMBX 110s and/or
iMBX 120s). For each MULTIBUS board, power
supply, or chassis, an iMBX 110 is ordered. For
each MULTIMODULE board, an iMBX 120 is
ordered.
MONTHLY UPDATES
CHARGES
Each month MULTIBUS EXCHANGE subscribers
receive an update containing summaries of
Engineering Change Orders and documentation
clarification articles relating to each subscribedto product. Each change description includes the
change made, the rationale behind the change,
and the user's alternatives concerning updating
For an annual subscription fee, subscribers
receive twelve monthly updates. All new subscribers will also receive a history for each subscribedto product at no extra charge. For additional
specified charges, subscribers can purchase the
associated documentation and parts kits listed in
the MULTIBUS EXCHANGE updates.
NEW SUBSCRIBERS
ORDERING INFORMATION
Part Number
Description
MBX 100
Base order for the MULTIBUS
EXCHANGE hardware
subscription service for one
year
MBX 110
MULTIBUS EXCHANGE
subscription covering one
MULTIBUS board, power supply or chassis for one year
MBX 120
MULTIBUS EXCHANGE
subscription covering one
MULTIMODULE board for one
year
11-20
Microcomputer
Development Systems
12
MODEL225
INTELLEC@SERIES 11/85
MICROCOMPUTER DEVELOPMENT SYSTEM
• Complete microcomputer development
system for.MCS®·S6, MCS®·S5,
MCS®·SO, MCS®·4S, and MCS®·51
microprocessor families
• Integral 250K byte floppy disk drive
with total storage capacity expandable
to over 2M bytes of floppy disk storage
and 7.3M bytes of hard disk storage
• High performance SOS5A-2 CPU,
64K bytes RAM memory, and
4K bytesROM memory
• Powerful ISIS-II Disk Operating System
with relocating macroassembler,
linker, locater, and CRT based editor
CREDIT
• Supports PL/M, FORTRAN, BASIC,
PASCAL and COBOL high level
languages
• Self-test diagnostic capability
• Built-in interfaces for high speed paper
tape reader/punch, printer, and universal PROM programmer
• Software compatible with previous
Intellec' systems
The Intellec Series 11/85 Model 225 Microcomputer Development System is a performance enhanced, complete microcomputer development system integrated into one compact package_ The Model 225 includes
a CPU with 64K bytes of RAM, 4K bytes of ROM, a 2000-character CRT, detachable full ASCII keyboard
with cursor controls and upperllower case capability, and a 250K-byte floppy disk drive_ Powerful ISIS-II
Disk Operating System software allows the Model 225 to be used quickly and efficiently for assembling
and debugging programs for Intel's MCS-86, MCS-85, MCS-80, MCS-48, or MCS-51 microprocessor
families. ISIS-II performs all file handling operations for the user, leaving him free to concentrate on the
details of his own application. When used with an optional in-circuit emulator (ICETM) module, the Model
225 provides all of the hardware and software development tools necessary for the rapid development of a
microcomputer-based product. Optional storage peripherals provide over 2 million bytes of floppy disk,
and 7.3 million of hard disk storage capacity.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: axp. lntellec. Mullihus. i. iSBC. Mu1timodule. ICE. iSBX, PROMPT. ieS. Library
Manager; Promware; Insite, MeS. RMX. Inlet, Megachassis. UPI. [ntelevision. Micromap, J,.!Scope and the combination of ICE. ieS. iSBC. iSBX. Mes. or RMX and a numerical
suffix.
© Intel Corporation 1980
121599-001 Rev. A
12-1
intJ
IIiIODEL225
high technology LSI components. Known as the
integrated processor card (lPC), it occupies the
first slot in the cardcage.Asecohd slave CPU card
is responsible' for all' remaining 110 control
including the CRT and keyboard interface. This
card, mounted on the rear panel, also contains its
own microprocessor, RAM and ROM memory, and
1/0 interface logic, thus, in effect, creating a dual
processor environment. Known as the 1/0 controller (lOC), the slave CPU card communicates
with the IPC over an 8-bit bidirectionaldata bus.
FUNCTIONAL DESCRIPTION
Hardware Components
The Intel lee Series 11/85 Model '225 is a highlyintegrated microcomputer development system
consisting of a CRT chassis with a 6-slot cardcage,
power supply, fans, cables, single floppy disk
drive, and two printed circuit cards. A separate,
full. ASCII keyboard is connected with a cable.
A block diagram' of the Model 225 is shown in
Figure 1.
Expansion -:- Five remainingslotsin the cardcage
are available for system expansion. Additional
expansion of 4 slots can be achieved through the
addition of an Intellec Series II expansion chassis.
CPU Cards c:- The master. CPU, card .contains its
own microprocessor, memory, 110, interrupt and
bus interface circuitry implemented with Intel's
LOCAL
INTERRUPT
CONTROL
8259A
....
64K BYTES
RAM
"
4KBYTES
ROM
8·LEVEL
PRIORITY·
INTERRUPT
,
, 8259A
~
-?.
.
PANEL
CONTROL "
.
BUS
CONTROLLER
8219
PRIORITY
RESOLUTION
CiJ C?
DMA
.. ,...
.
"""
8271
FLOPPY
CONTROLLER
.. ,...
..
SYSTEM
CLOCKS
8080A·2
CPU
+
8228
SYSTEM
CONTROLLER
8KROM
,
!
.. ,...
.'
SERIAL
CHANNELl
8251A
I
I
I
I
8085A·2
CPU
,
IOC BUS
T
I
CABLE BUS
..01""
, 8253
INTERVAL
TIMER
~
UPP
PRINTER
t
,J
8041A
CPU
.... 1oo,J
,
PIO BUS
!
GENERATOR &
REAL·TIME CLOCK
' . 8253A
81DIRECTIONAL
DRIVER
I
t
BAUD RATE
J-...c-
,J
. '
!
KEYBOARD
l
I
.
!
"""
8275
CRT
CONTROLLER
+
SERIAL
CHANNELO
, ,8251A
INTELLEC BUS
..
~
J
"
!
TAPE
PUNCH
t
,J
t
TAPE
READER
Figure 1. Intellec Series 11/85 Model 225 Microcomputer Development System BlockDiagram
12-2
AFN·014248
MODEL225
System Components·
The heart of the IPC is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K
bytes of RAM memory are prbvided on the board
using 16K RAMs. 4K of .ROM is provided, preprogrammed with system bootstrap "self-test"
diagnostics and the Intellec Series 11/85 System
Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259A interrupt
controller, the interrupt system may be user programmed to respond to individual needs.
Input/Output
IPC Serial Channels - The I/O subsystem in the
Model 225 consists of two parts: the 10C card and
two serial channels on the IPC itself. Each serial
channel is RS232 compatible and is capable of running asynchronously from 110 to 9600 baud or synchronously from 150 to 56K baud. Both may be
connected to a user defined data set or terminal.
One channel contains current loop adapters. Both
channels are implemented using Intel's 8251A
USART. They can be programmed to perform a
variety of I/O functions. Baud rate selection is
accomplished through an Intel 8253 interval timer.
The 8253 also serves as a real-time clock for the
entire system. I/O activity through both serial
channels is signaled to the system through a
second 8259A interrupt controller, operating in a
polled mode nested to the primary 8259A.
IOC Interface - The remainder of system I/O
activity takes place in the 10C. The 10C provides
interface for the CRT, keyboard, and standard
Intellec peripherals including printer, high speed
paper tape reader/punch, and universal PROM
programmer. The 10C contains its own independent microprocessor, an 8080A-2, The CPU controls
all I/O operations as well as supervising
communications with the IPC. 8K bytes of ROM
contain all I/O control firmware. 8K bytes of RAM
are used for CRT screen refresh storage. These
do not occupy space in· Intellec Series II main
memory since the 10C is a totally independent
microcomputer subsystem.
Integral CRT
Display - The CRT is a 12-inch raster scan type
monitor with a 50/60 Hz vertical scan rate and
15.5kHz horizontal scan rate. Controls are provided for brightness and contrast adjustments.
The interface to the CRT is provided through an
Intel 8275 single-chip programmable CRT con-'
12-3
troller. The master processor on the IPC transfers
a character for display to the 10C, where it is
stored in RAM. The CRT controller reads a line at a
time into its line buffer through an Intel 8257 DMA
controller and then feeds one character at a time
to the character generator to produce the video
signal. Timing for the CRT control is provided by
an Intel 8253 interval timer. The screen display is
formatted as 25 rows of 80 characters. The full set
of ASCII characters is displayed, including lower
case alphas.
Keyboard - The keyboard interfaces directly to
the 10C processor via an 8-bit data bus. The
keyboard contains an Intel UPI_41™ Universal
Peripheral Interface, which scans the keyboard,
encodes the characters, and buffers the
characters to provide N-key rollover. The
keyboard itself is a high quality typewriter style
keyboard containing the full ASCII character set
An upper/lower case switch allows the system to
be used for document preparation. Cursor control
keys are also provided.
Peripheral Interface
A UPI-41 Universal Peripheral Interface on the 10C
board provides interface for other standard
Intellec peripherals including a printer, high
speed paper tape reader, high speed paper tape.
punch, and universal PROM programmer. Communication between the IPC and 10C is maintained
over a separate 8-bit bidirectional data bus. Connectorsfor the four devices named above, as weli
as the two serial channels, are mounted directly
on the 10C itseif.
Control
User control is maintained through a front panel;
consisting of a power switch and indicator,
reset/boot switch, run/halt light, and eight interrupt switches and indicators. The front panel circuit board is attached directly to the IPC, allowing
the eight, interrupt swi'tches to connect to the
primary 8259A, as well as to the Intellec Series II
bus.
Integral Floppy Disk Drive
The integral floppy disk is controlled by an Intel
8271 single chip, programmable floppy disk controller. It transfers data via an Intel 8257 DMA controller between an 10C RAM buffer and the
diskette. The8271 handles reading and writing of
data, formatting diskettes, and reading status, all
upon appropriate commands from the 10C
microprocessor.
AFN·014248
MODEL225
MULTIBUS™ Interface Capability
All Intellec Series 11/85 models implement the
industry standard MUL TlBUS protocol. The
MULTIBUS protocol enables several bus masters,
such as CPU and DMA devices, to share the bus
and memory by operating at different priority
levels. Resolution of bus exchanges is synchronized by a bus clock signal derived
independently from processor clocks. Read/write
transfers may take place at rates up to 5 MHz.The
bus structure is suitable for use with any Intel
microcomputer family .
SPECIFICATIONS
Memory Access Time
Host Processor (lPC)
RAM - 470 ns max
PROM - 540 ns max
8085,l1.-2 based, operating at 4.0 MHz,
RAM....,. 64K on the CPU card
ROM - 4K (2K in monitor, 2K in boot/diagnostic)
Bus.,... MULTIBUS™ bus, maximum transfer rate
of 5 MHz
Clocks - Host processor, crystal controlled at
4.0 MHz, bus clock, crystal controlled at 9.8304
MHz
I/O Interfaces
Two Serial 110 Channels, RS232C, at110-9600 baud
(asynchronous) or 150-56K baud (synchronous).
Baud rates and serial format fully programmable
using Intel 8251A USARTs. Serial Channel 1 additionally provided with 20 mA current loop. Parallel
I/O interfaces provided for paper tape punch,
paper tape reader, printer, and UPP-103 Universal
PROM Programmer.
Integral Floppy Disk Drive
Floppy Disk System Capacity 250K bytes (formatted)
Floppy Disk System Transfer Rate 160K bits/sec
Floppy Disk System Access Time Track to Track: 10 ms max
Average Random Positioning: 260 ms
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: FM
Physical Characteristics
Interrupts
CHASSIS
8-level, maskable, nested priority interrupt network initiated from front panel or user selected
devices.
Width -17.37 in. (44.12 cm)
Height -15.81 in. (40.16 cm)
Depth -19.13 in. (48.59 cm)
Weight - 731b. (33 kg)
Direct Memory Access (DMA)
KEYBOARD
Standard capability on MULTIBUS interface;
implemented for user selected DMA devices
thri)ugh optional DMA module-maximum transfer
rate of 5 MHz.
Width -17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth....,. 9.0 in. (22.86 cm)
Weight - 61b. (3 kg)
12-4
AFN·Q14248
MODEL225
Electrical Characteristics
Equipment Supplied
Model 225 Chassis including:
Integrated Processor Card (IPC)
110 Controller Board (IOC)
CRT
ROM-Resident System Monitor
Detachable keyboard
ISIS-II System Diskette with MCS-80/MCS-85
Macroassembler
ISIS-II CREDIT Diskette CRT-Based Text Editor
DC POWER SUPPLY
Volts
Supplied
Amps
Supplied
Typical
System
Requirements
+ 5±5%
+12±5%
-12± 5%
-10±5%
+15±5%'
+24±5%'
30.0
2.5
0.3
1.0
1.5
1.7
17.0
1.1
0.1
0.08
1.5
1.7
Documentation Supplied
A Guide to Microcomputer Development Systems,
9800558
'Not available on bus.
Intellec~ Series II Model 22X/23X Installation
Manual, 9800559
ISIS-II System User's Guide, 9800306
Intellec® Series II Hardware Reference Manual,
9800556
8080/8085 Assembly Language Programming
Manual, 9800301
AC REQUIREMENTS FOR MAINFRAME
110V, 60 Hz - 5.9 Amp
220V, 50 Hz - 3.0 Amp
ISIS-II 8080/8085 Assembler Operator's Manual,
9800292
Intellec' Series
Listing, 9800605
II Systems
Monitor Source
Intellec" Series II Schematic Drawings, 9800554
ISIS-II CREDIT (CRT-Based Text Editor) User's
Guide, 9800902
Environmental Characteristics
Additional manuals may be ordered from any Intel
sales representative or distributor office, or from
Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, California 95051.
Operating Temperature -16°C to 32°C
(61°F to 90°F)
Humidity - 20% to 80%
ORDERING INFORMATION
Part
Number
Description
MDS-225' Intellec' Series 11/85 Model 225
Microcomputer
Development System (110V 160 Hz)
MDS-226' Intellec' Series 11/85 Model 226
Microcomputer
Development System (220V 150 Hz)
• "MOS" is an ordering code only. a",d is not used as a product
name or trademark. MDS'"~ is a registered trademark of
Mohawk Data Sciences Corp.
.
12-5
AFN-014248
MODEL 286
INTELLEC® SERIES III
MICROCOMPUTER DEVELOPMENT SYSTEM
• Supports Intellec 432/100 Evaluation
and Educational System
• 96K Bytes of User Program RAM
Memory.Avaiiable for iAPX 86,88
Programs
• Compatible with iSBC-090 Series 90
Memory System Upgrade: 512K Byte
to 1M Byte
• Series 11/80 and Series 11/85
Upgradeable to 8085/iAPX 86 Series III
Functionality
• Complete 16-bit High. Performance,
Microcomputer Development Solution
for Intel iAPX 86,88 Applications" Also
Supports MCS~85TM, MCS:'80 and
.
MCS-48 Families
• .Intellec Model 800 Upgradeable to
8080/iAPX 86 Series III Functionality
• Compatible with Intellec Distributed
Development Systems
.
• Supports Full Range of iAPX 86,88Resident, High-Level Languages: PL/M
86/88, PASCAL 86/88, and FORTRAN
86/88
I
• 2 Host CPUs-iAPX86 and 8085A-for .
Enhanced System Performance and.
Two Native Execution Environments ....
• Compatible with Previous Intellec
Systems
• Software Applications Debugger for
User iAPX 86,88 Programs
• Upgradeable to a Complete Ethernet*.
Communications Development System
Environment, Using the Model 677
Upgrade
The Intellec Series-III Microcomputer Development System is a high-performance system solution designed
specifically for iAPX86,88 microprocessor development. It contains two host CPUs, an iAPX 86 and an 8085,
that provide two native execution environments for optimum performance and compatibility with the Intellec
software packages for both CPUs. The basic system includes 96K bytes of iAPX 86,88 user RAM memory and a
250K byte floppy disk drive.The powerful Disk Operating System maximizes system processing by utilizing the
power of both host processors. Standard;software includes a full range of iAPX 86,88 resident software. The
high-level languages PLIM 86/88, PASCAL 86/88, and FORTRAN 86/88 are also available. A ROM.resident
software debugger not only provides self-test diagnostic capability, but also gives the user a powerful iAPX
86,88 applications debugger.
"Ethernet is a trademark of XeroxC()rporation.
12-6
121670-002
inter
MODEL 286
A third CPU card performs all remaining I/O including interface to the CRT, integral floppy disk, and
keyboard. This card, mounted on the rear panel,
contains its own microprocessors, RAM and ROM
memory, and I/O interface logic. Known as the I/O
controller (laC), this slave CPU card communicates
with the IPC-8S over an 8-bit bidirectional data bus.A
64K byte RAM expansion memory board is also
included.
FUNCTIONAL DESCRIPTION
Hardware Components
The Intellec Series III is contained in a single package consisting of a CRT chassis with a 6-slot card
cage, power supply, fans, cables, single floppy disk
drive, detachable upper/lower case full ASCII keyc
board, and four printed circuit cards. A block diagram of the system is shown in Figure 1.
Expansion
System Components
Two additional slots in the system cardcage are
available for system expansion. The Intellec expansion chassis Model 201 is available to provide 4 additional expansion slots for either memory or I/O expansion.
Two CPU cards reside on the Intellec MUL TIBUS
bus, each containing its own microprocessor,
memory, I/O, interrupt and bus interface circuitry
implemented with Intel's high technology LSI components. The integrated processor card (IPC-8S),
occupies the first slot in the cardcage. A second
CPU card, the resident processor board (RPB-86)
contains Intel's 16-bit HMOS microprocessor. These
CPUs provide the dual processor environment.
THE INTELLEC DEVELOPMENT SYSTEM FOR
ETHERNET (DS/E)
The Intellec Serie~ III can be expanded to provide the
user with the to'ols necessary to develop and test
Figure 1. INTELLEC Series III Block Diagram
12-7
AFN·015B6B
inter
MODEL 286
communications software and applications that will
use Ethernet as a communications subsystem. The
power of the Intellec Series III combined with Model
677 allows the user to develop either 8- or 16-bit
Ethernet-based applications.
THE INTELLEC 432/100 EVALUATION AND
EDUCATIONAL SYSTEM
The Intellec Series III provides a complete system
environment necessary for evaluation of the Intel
iAPX 432 32-bit micromainframe. The iSBC 432/100
board plugs into a Multibus slot in the Intellec Series III, sharing system memory and resources. A
comprehensive set of documentation, system
software and hardware provides the evaluation and
educational environment for the powerful iAPX 432.
iAPX 286 Evaluation System
The Intellec Series III provides a complete system
environment for evaluation of the iAPX 286 microprocessor's architecture and its instruction set, segmentation timing, memory mapping and protection
features. A user can begin the development of complex iAPX 286 programs, systems and operating system nuclei with the Intellec Series III and iAPX 286
evaluation package.
CPU Cards
IPC·8S
The heart of the IPC-85 is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K
bytes of RAM memory are provided on the board
using 16K dynamic RAMs. 4K of ROM is provided,
preprogrammed with system bootstrap "self-test"
diagnostics and the Intellec System Monitor. The
eight-level vectored priority interrupt system allows
interrupts to be individually masked. Using Intel's
versatile 8259A interrupt controller, the interrupt
system may be user programmed to respond to individual needs.
Input/Output
IPC·8S SERIAL CHANNELS
The I/O subsystem in the Series III consists of two
parts: the lac card and two serial channels on the
IPC-85 itself. Each serial channel is independently
configurable. Both are RS232-compatible and is capable of running asynchronously from 110 to 9600
baud or synchronously frOm 150 to 56K baud. Both
maybe connected to a user defined data set or terminal. One channel contains current loop adapters.
Both channels are implemented using Intel's 8251A
USART. They can be programmed to perform a variety of I/O functions. Baud rate selection is accomplished through an Intel 8253 interval timer. The
8253 also serves as a real-time clock for the entire
system. I/O activity through each serial channel is
independently signaled to the system through a
second 8259A (slave) interrupt controller, operating
in a polled mode nested to the master 8259A.
IOC INTERFACE
The remainder of the system I/O activity is handled
by the lac. The lac provides the interface and control for the keyboard, CRT, integral floppy disk drive,
and standard Intellec-compatable peripherals including printer, high speed paper tape reader/
punch, and universal PROM programmer. The lac
contains its own independent microprocessor, an
8080A-2. This CPU issues commands, receives
status, and controls all I/O operations as well as
supervising communications with the IPC-85. The
lac contains interval timers, its own lac bus system
controller, and 8K bytes of ROM for all I/O control
firmware. The 8K bytes of RAM are used for CRT
screen refresh storage. Neither the ROM nor the
RAM occupy space in the Intellec Series III main
memory address range because the lac is a totally"
independent microcomputer subsystem.
Integral CRT
RPB·86
The heart of the RPB-86 is an Intel HMOS 16-bit
microprocessor, the iAPX 86 (8086), running at 5.0
MHz. 64K bytes of RAM memory are provided on the
board. 16K of ROM is provided on board, preprogrammed with an iAPX 88/86 applications debugger
which provides features necessary to debug and
execute application software for the iAPX 88/86
microprocessors.
DISPLAY
The CRT is a 12-inch raster scan type monitor with a
50/60 Hz vertical scan rate and 15.5 kHz horizontal
scan rate. Controls are provided for brightness and
contrast adjustments. The interface to the CRT is
provided through an Intel 8275 single chip programmable CRT controller. The master processor
on the IPC-85 transfers a character for display to the
laC, where it is stored in RAM. The CRT controller
reads a line at a time into its line buffer through an
Intel 8257 DMA Controller. It then feeds one character at a time to the character generator to produce
the video signal. Timing for the CRT control is
provided by an Intel 8253 programmable interval
The 8085A-2 and iAPX 86 access two independent
memory spaces. This allows the two processors to
execute concurrently when an iAPX 88/86 program
is run. In this mode, the IPC-85 becomes an intellegent I/O processor board to the RPB-86.
12-8
AFN-015888
inter
MODEL 286
timer. The screen display is formatted as 25 rows of
80 characters. The full set of ASCII characters are
displayed, including lower case alphas.
Dual Drive Floppy Disk System (Option)
The Intellec Series III Double Density Diskette System provides direct access bulk storage, intelligent
controller and two diskette drives. Each drive
provides 1/2 million bytes of storage with a data
transfer of 500,000 bits/second. The controller is
implemented with Intel's powerful Series 3000 Bipolar Microcomputer Set and supports up to four diskette drives to allow more than 2 million bytes of
on-line storage.
KEYBOARD
The keyboard interfaces directly to the IOC processor via an 8-bit data bus. The keyboard contains
an Intel UPI-41A Universal Peripheral Interface,
which scans the keyboard and encodes the characters to provide N-key rollover. The keyboard itself is
a typewriter style keyboard containing the full ASCII
character set. An upper!lower case switch allows the
system to be used for document preparation. Cursor
control keys are also provided.
The diskette controller consists of two boards, the
channel board and the interface board. These two
PC boards reside in the Intellec Series III system
chassis. The channel board receives, decodes and
responds to channel commands from the 8085A-2
CPU on the IPC-85. The interface board provides the
diskette controller with a means of communication
with die disk drives and with the Intellec system bus.
The interface board also validates data during disk
transactions.
Peripheral Interface
A UPI-41A Universal Peripheral Interface on the IOC
board provides built-in interface for standard
Intellec-compatable peripherals including a printer,
high speed paper tape reader, high speed paper
tape punch, and universal PROM programmer.
Communication between the IPC-85 and IOC is
maintained over a separate 8-bit bidirectional data
bus. Connectors for the four devices named above,
as well as the two serial channels, are mounted directly on the IOC itself.
An additional cable and connectors are also
supplied to optionally convert the integral floppy
disk from single density to double density.
Control
User control is maintained through a front panel,
consisting of a power switch and indicator, reset!
boot switch, run/halt light and eight interrupt
switches and LED indicators. The front panel circuit
board is attached directly to the IPC-85, allowing the
eight interrupt switches to connect the master
8259A, as well as to the Intellec Series III bus.
Hard Disk System (Option)
The Intellec Series III Hard Disk System provides
direct access bulk storage, intelligent controller and
a disk drive containing one fixed platter and one
removable cartridge. Each provides approximately
3.65 million bytes of storage with a data transfer rate
of 2.5 Mbits/second. The controller is implemented
with Intel's Series 3000 Bipolar Microcomputer Set.
The controller provides an interface to the Intellec
Series III system bus, as well as supporting up to 2
disk drives. The disk system records all data in Double Frequency (FM) on 2 surfaces per platter. Each
platter can be write protected by a front panel
switch.
User program control in the iAPX 88/86 environment
of the Intellec Series III is also directed through keyboard control sequences to transfer control to the
iAPX 88/86 applications debugger, abort a user program or translator and returning control to the
IPC-85.
DISK SYSTEM
Integral Floppy Disk Drive
HARD DISK CONTROLLER BOARDS
The disk controller consists of two boardS which
reside in the Intellec Series III system chassis. The
disk system is capable of performing six operations:
recalibrate, seek, format track, write data, read data,
and verify CRC. In addition to supporting a second
drive, the disk controller may co-exist with the
double-density diskette controller to allow up to 17
million bytes of on-line storage.
The integral floppy disk is controlled by an Intel 8271
single chip, programmable floppy disk controller.
The disk provides capacity of 250K bytes. It transfers
data via an Intel 8257 DMA Controller between an
IOC RAM buffer and the diskette. The 8271 handles
reading and writing of data, formatting diskettes,
and reading status, all upon appropriate commands
from the IOC microprocessor.
12-9
AFN-015888
inter
MODEL286
8cbittranslations and applications are' handled by
the 8,bit CPU, and 16-bit translations arid applica c
tions are handled by the 8086.This feature provides
complete compatibility for current systems and
means that software running on current Intellec Development Systems will run on the new system.
MULTI BUS Interface Capability·
All. models of the IritellecSeries III implement the
industry standard MULTIBUS protocoL The MULTIBUS architecture allows several bus m'asters, such
as CPU and DMA 'devices, to share the bus and
memory by operating at different priority levels.
Resolution of· bus exchanges is synchronized by a
bus clock signal derived' independerltlyfrom pr()cessor clocks. Read/writetransferS may take place
at rates up to 5 MHz. The bus structure is suitable for
use with any Intel microcomputer family.
High-Level Languages for iAPX 86,88-The Model
286allows the current Intellecsystem user to take
advantage of a.breadth Of new resident iAPX 86,88
high-level languages: PL/M B6/BB, PASCAL B6/BB,
and FORTRAN B6/BB. The iAPX B6,BB Resident
Macro Assembler and these high-level language
compilers execute on the BOB6.host CPU, thereby
increasing system performance.
System Software Features
The Model 286.offers many key advantages foriA~'x
86,88 applications .and Intell.ec, Dev!llopment. Systems: enhanced system performance through a,dual
host ,CPU environment, a full sp.ectrum. oUAPX
86 ,88-nisi dent hi g h-I evellan g uages, expande<;l.ljser
program space for iAPX 86,88 programs, and a powerful high-level ,software application~ debugger for
iAPX 86,88 microprocessor software.
Expanded Program Memory-By adding a Model
286 toanexisting Intellec Development System, 96K
bytes of user.program RAM memory are made available for iAPX 86,B8 programs. System memory is
expandable by adding additional RAM memory
modules .. This, combined with the two host CPU
system architecture, dramatically increases the processing power ·of the system.
Dual Host CPU-The addition of a 16-bit 8086 to the
existing a-bit host CPU increases iAPX 86,88 com"
pilation speeds and provides for iAPX 86,88 code
execution. When the 8086 is executing a program,
the 8-bit CPU off-loads all 1/0 activity and operates
as an intelligent 1/0 controller to double buffer data
to and from the 8086. The 8086 also provides an
execution vehicle for 8086 and 8088 object .code. An
added benefit of two host microprocessors is that
Software' Applications . Debugger-The RPB-B6
contains the applications debugger which allows
iAPX 86,BB programs to be developed, tested, and
debugged within the Intellec system, The debugger
provides a subset of In-Circuit Emulator commands
such as symbolic debugging, control structures and
compound commands specifically oriented toward
software. debug needs.
SPECIFICATIONS
Integral Floppy
Host Processor Boards.
Capacity-250K bytes (formatted)
Transfer Rate-160K bitslsec
Access, TimeTrack to Track: 10 ms max.
Average Random Positioning: 260 ns
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: FM
INTEGRATED PROCESSOR CARl?
-(IPC-85) .8085A-2 based, operating at 4 MHz
-64K RAM, 4K ROM (2K in monitor and 2K in boot!
diagnostic)
RESIDENT PROCESSOR BOARD
-(RPB-86) 8086 based, operating at 5 MHz, 64K
RAM, 16K ROM (applications debugger)
Dual Floppy Disk Option
BUS
-MUL TIBUS IJUS, maximum transfer rate of 5 MHz
Capacity~
DIRECT MEMORY ACCESS '
Standard capability on the MULTIBUS bus;
implemented for user. selected' DMA devices
through optional DMA module
-Maximum transfer rate of 2 MHz
~(DMA)
Dis~,
Per Disk: 4.1 megabits (formatted)
Per Track: 53.2 kilo bits (formatted) ,
Transfer Rate-,;-500 kilobitslsec
Access TimeTrack to Track: 10 ms
Head Setting Time:. 10 ms
Average Random Positioning Time-260ms
12-10
AFN-01588B
inter
MODEL 286
Rotational Speed-360 rpm
Average Rotational Latency: 83 ms
Recording Mode: M2 FM
ELECTRICAL CHARACTERISTICS
DC Power Supply
Hard Disk Drive Option
Type-5440 top loading cartridge and one fixed
platter
Tracks per Inch-200
Mechanical Sectors per Track-12
Recording Technique-double frequency (FM)
Tracks per Surface-400
Density-2,200 bits/inch
Bits per Track-62,500
Recording Surfaces per Platter-2
CapacityPer Surface-15M bits
Per Platter-29M bits
Per Drive-59M bits
Per Drive-7.3M bytes(formatted)
Transfer Rate-2.5M bits/sec
Access TimeTrack to Track: 13 ms max
Full Stroke: 100 ms
Rotational Speed: 2,400 rpm
Typical
System
Requirements
Volts
Supplied
Amps
Supplied
+ 5 ± 5%
30.0
+12 ± 5%
2.5
1.1
-12 ± 5%
0.3
0.1
-10 ± 5%
1.0
0.08
+15±5%"
1.5
1.5
+24 ± 5%"
1.7
1.7
17.0
"Not available on bus
AC Requirements for Mainframe
110V, 60 Hz-5.9 Amp
220V, 50 Hz-3.0 Amp
ENVIRONMENAL CHARACTERISTICS
System Operating Temperature'--O° to 35°C
(32°F to 95°F)
..
Physical Characteristics
Humidity-20% to 80%
Width-17.37 in. (44.12 cm)
Height-15.81 in. (40.16 cm)
Depth-19.13 in. (48.59 cm)
Weight-81 lb. (37 kg)
DOCUMENTATION SUPPLIED
Intellec Series III Microcomputer Development System Product Overview, 121575
KEYBOARD
Width-17.37 in. (44.12 cm)
Height-3.0 in. (7.6 cm)
Depth-9.0 in. (22.86 cm)
Weight-6 lb. (3 kg)
A Guide to Intellec Series III Microcomputer Development Systems, 121632-001
Intellec Series 111 Microcomputer Development System Console Operating Instructions, 121609
Intellec Series III Microcomputer Development System Pocket Reference, 121610
DUAL FLOPPY DRIVE SYSTEM (OPTION)
Width-16.88 in. (42.88 cm)
Height-12.08 in. (30.68 cm)
Depth-1.0 in. (48.26 cm)
Weight-64 lb. (29 kg)
Intellec Series III Microcomputer Development System Programmer's Reference, 121618
iAPX 88/86 Family Utilities User's Guide for 8086Based Development Systems, 121616
8086/8087/8088 Macro Assembly Language Reference Manual for 8086-Based Development Systems,
121627
HARD DISK DRIVE SYSTEM (OPTION)
Width-18.5 in. (47.0 cm)
Height-34.0 in. (86.4 cm)
Depth-29.75 in. (75.6 cm)
Weight-202 lb. (92 kg)
8086/8087/8088 Macro Assembly Language Pocket
Reference, 9800749
12-11
AFN·01588B
MODEL 286
BOB61BOB71BOBB Macro Assembler Operating Instructions for BOB6-Based Development Systems,
121628
Intel/ec Series III Microcomputer Development System Instal/ation and Checkout Manual, 121612
ISIS-II CREDIT (CRT-Based Text Editor) Pocket Reference, 9800903
The B086 Family User's Manual, 9800722
The 8086 Family User's Manual, Numeric Supplement, 121586
Intel/ec Series 11/ Microcomputer Development System Schematic Drawings,121642
For Series III Plus Hard Disk'Systems Only:
ISIS-II CREDIT (CRT-Based Text Editor) User's
Guide, 9800902
Model 740 Hard Disk Subsystem Operation and
Checkout, 9800943
ORDERING INFORMATION
DS287FD KIT Intellec Series III Model 287 Microcomputer Development System with
Dual Double Density Flexible Disk
System (220V/50Hz)
Part Number Description
DS286 KIT
DS287 KIT
Intellec Series III Model 286 Microcomputer Development System
(110V/60Hz)
Intellec Series III Model 287 Microcomputer Development System
(220V150Hz)
DS286FDKIT Intellec Series III Model 286 Microcomputer Development System with
Dual Double Density Flexible Disk
System (11 OV/60Hz)
DS286HD KIT Intellec Series III Model 286 Microcomputer Development System with
Pedestal Mounted Hard Disk.
(110V/60Hz)
DS287HD KIT Intellec Series III Model 287 Microcomputer Development System with
Pedestal Mounted Hard Disk.
(220V/50Hz)
Requires Software License
12-12
AFN-Q1588B
MODEL 675
INTELLEC® DEVELOPMENT SYSTEM
FOR ETHERNET* DSIE
• Complies with the Intel, DEC, and Xerox
Tricompany Ethernet Specification
• Provides a complete Ethernet Communications Development System
Environment
• Includes an Ethernet Data Link Layer
.Software Library to allow user programs
to access the Ethernet Data Link from
the 8085 in Model 675 systems
• Supports the Ethernet Data Link and
Physical Link Control via the MULTIBUS
Ethernet Communications Controller
• Includes a special 10 meter Interconnect
Cable for connecting two Model 675s
for Ethernet software prototyping
• Supports the full range of iAPX
86, 88-resident, High-Level Languages:
PLIM 86/88; PASCAL 86/88; and
FORTRAN 86/88
• Includes a Software Applications
Debugger for iAPX 86, 88 user programs
• Upgradable from Intellec Series 11/85
and Series III
The Intellec Development System for Ethernet (DS/E) provides the user with the tools necessary to develop
and test communication software and applications that will use Ethernet as a communication subsystem. It
combines the power of the Intellec Microcomputer Development System with a dual board Ethernet Communications Controller for microprocessor development. This combination allows the user to develop either
8- or 16-bit Ethernet-based applications.
The Ethernet Communications Controller incorporates the Ethernet Data Link and Physical Link Control to
meet the Ethernet specification for 10 Mbit per second data transmission rate over coaxial cable. The controller consists of two MULTI BUS compatible boards, the Processor board and the SerializationiDeserializalion (SerDes) board. The Processor board provides the function of packet buffering, processing, and transferring of the processed packets to system memory. The SerDes board performs the serialization/deserializalion, framing, CRC generation and checking, Manchester encoding/decoding, and destination address
recognition. A10 meter interconnect cable is included to permit two Model 675s to be connected in a functioning Ethernet environment without the need for Ethernet transceivers and coaxial cable .
• Ethernet is a trademark of Xerox Corporation.
Intel Corporation Assumes No Responsibilty lor the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
© INTEL CORPORATION. 1981.
12-13
AFN-01975A
MODEL 675
COMPONENTS
Hardware Components
The Model 675 consists of a CRT chassis with a
6·slot cardcage, power supply, fans, cables, single
floppy diskette drive, a detachable upper/lower
case full ASCII keyboard, and six printed circuit
boards. A block diagram of the Model 675 is shown
in Figure 1.
System Components
Two CPU boards, the IPC-85 and the RPB-86, reside
on the Model 675 MULTI BUS system bus, each con·
taining its own microprocessor, memory, I/O, inter·
rupt and bus interface circuitry implemented with
Intel's high technology LSI components. The IPC·85
integrated processor board consists of an Intel
NMOS 8·bit microprocessor, the 8085A·2, and 64
Kbytes of on board memory. The RPB-86 resident
processor board contains Intel's HMOS 16·bit
microprocessor, the iAPX 86 (8086), and 64 Kbytes of
on board memory.
A third CPU board, known as the I/O controller (IOC)
performs all remaining I/O including the interface to
the CRT, integral floppy disk, and keyboard. The 10C
contains its own microprocessor, RAM and ROM
memory, and I/O interface logic. It is a slav.e CPU
board which communicates with the IPC·85 over an
8·bit bidirectional data bus.
The Model 675 also includes an additional 64 Kbyte
MULTI BUS compatible RAM board supplying the
user with a total of 192 Kbytes of RAM. The.two reo
maining boards are the Ethernet .Communications
Controller.
.
Figure 1. Model 675 DS/E Block Diagram
12-14
AFN·01975A
intJ
MODEL 675
Expansion
The Intellec expansion chassis Model 201 is included in the basic Model 675. All Model 675 systems contain 10 MULTI BUS board slots-6 in the
main system and 4 in the Model 201 chassis. The
table below indicates the number of slots available
for expansion in each.
Model
675
675FD
675HD
Available Expansion Slots
4
2
2
Ethernet Communications Controller
PROCESSOR BOARD
The processor board interfaces to the MULTI BUS
system bus and contains the Intel5 MHz 8088 CPU,
16 Kbytes dynamic RAM for Ethernet and host interface program execution, 8K EPROM pre-programmed for the Data Link Control, and an 8K static
RAM for transmit and receive channel DMA data
buffering. The Processor board provides the
necessary commands and control to the SerDes
board and receives status and data from it.
SerDes BOARD
The SerDes board meets the required electrical
specification to the transceiver and provides the
Data Link Layer of the Ethernet architecture. The
major functions of the SerDes board include serialization/deserialization, framing, Manchester encoding/decoding, transmit data flow control,
receive data flow control, destination address
decoding for received message, CRC generation
and checking, and diagnostic for CRC error, loopback, transmit timeout, and if used with transceivers, CSMA/CD (carrier-sense multiple-access
with collision-detection).
DATA BUFFERING
All data transfers from the Ethernet Data Link control of the SerDes board are buffered through the 8K
static RAM. This minimizes the amount of bus time
used by the Ethernet Communications Controller
by eliminating the possibility of data overruns and
subsequent repeated I/O operations. In addition,
the buffer allows the Ethernet Communications
Controller to have a bus priority below higherpriority, time-critical parts of the system.
DIAGNOSTICS
Diagnostic functions are resident on the SerOes
board and can be invoked on demand by the program on the Processor board. These functions
incude: transmitting packets with a bad CRC; receiving all packets regardless of address; reading
data received in error; SerDes loop-back, this function allows data from static RAM to be transmitted
and received simultaneously (the received data is
verified but not written to the Static RAM). The CRC
generation and checking can be used to verify
transmit and receive data.
When the 10 meter interconnect cable between two
Model 675s is used, point-to-point diagnostics are
available to verify station-to-station c:;ommunications, cable data sensitivity, CRC, packet length errors, and external carrier sense. In addition to these
functions, a loop-back diagnostic is provided for
use with transceivers. This function is similar to the
SerDes loop-back diagnostic except the transceiver
cable is also verified.
Figure 2 is a block diagram of the Ethernet Communications Controller.
Software
Three levels of program interface are provided to
users of the Model 675 for Ethernet software prototyping and evaluation.
MULTIBUS MESSAGE EXCHANGE (MMX)-ISIS-II
MULTI BUS Message Exchange (MMX)-ISIS-II is a
simple processor-to-processor protocol which permits ISIS-II user programs to communicate with the
software residing on the Ethernet Communications
Controller.
The model of use of MMX is as follows: The calling
program will allocate a segment of memory in the
64 Kbyte segment accessible by ISIS-II, fill in application defined fields, and transmit via MMX to a
socket on the Ethernet Communications Controller.
The program then waits for the application level response to the command just given. There is an MMX
module in ROM on the Ethernet Communications
Controller, and another in the HOST RAM.
EXTERNAL DATA LINK (EDL)
The External Data Link (EDL) presents a subset of
the Data Link Layer interface to users at the
MMX-ISIS-II interface level. This allows a user to
write Ethernet application programs to access the
Ethernet Data Linkon the 8085A-2 in ISIS-II systems.
The External Data Link resides in the ROM on the
Ethernet Communications Controller.
12-15
AFN·01975A
MODEL 675
MULTIBUS
(a) Processor Board
TRANSMIT REQUEST, COMPLETE
COLLISION
DETECT
TRANSMIT
DATA
LOOp·BACKI
NORMAL
SELECT
RECEIVE DATA
SHIFT
REGISTER
RECEIVE
DATA
RECEIVE REQUEST, COMPLETE
(b) SerDes Board
Figure 2. Block Diagram of the Ethernet Communications Controller
12-16
AFN·01975A
MODEL 675
ETHERNET DATA LINK LIBRARY
The Ethernet Data Link Library is provided to
simplify the External Data Link (EDL), MMX-ISIS-II
interface. This library provides synchronous interface procedures for the EDL functions. These procedures allow the user to simply call a subroutine
without being aware of the MMX-ISIS-II transaction
which is made with the Ethernet Communications
Controller. The Ethernet Data Link Library is provided on a diskette. It is designed to be linked with
the user's software residing in the HOST RAM.
DISK SUBSYSTEMS (OPTIONAL)
Dual Drive Floppy Disk Subsystem
The Model 675FD Double Density Diskette System
provides direct access bulk storage, intelligent controller and two diskette drives. Each drive provides
1/2 Mbytes of storage with a data transfer of 500,000
bits/second. The controller provides an interface to
the Model 675 system bus, as well as supporting up
to four diskette drives to allow more than 2 Mbytes
of on-line storage.
About the Ethernet
Hard Disk Subsystem
The Ethernet local area network provides a communication facility for high speed data exchange
among digital devices located within a moderate
sized geographic area. The Ethernet architecture
defines the system as a series of independent
layers.
The lowest layer, the Physical Link Layer, is
concerned with the coaxial cable interface. It completely specifies the essential physical charaCteristics of the Ethernet, such as data encoding, timing,
and voltage levels.
The Data Link defines a medium-independent link
level communication facility, built on the mediumdependent physical channel provided by the Physical Layer. It supports the peer protocol statistical
contention resolution (CSMA/CD), variable size
frames, and link management functions.
The higher levels of the overall network architecture, which use the Data Link Layer, are collectively
referred to as the Client Layer. The identity and function of this layer are user specific. The intent, however, is that the Ethernet Physical and Data Link
Layers support the higher layers of the ISO model
(Network Layer, Transport Layer, Session Layer,
etc.).
The overall structure of the layered architecture is
shown in Figure 3.
The Model 675HD Hard Disk System provides direct
access bulk storage, intelligent Controller and a
disk drive containing one fixed platter and one
removable cartridge. Each provides approximately
3.65 Mbytes of storage with a data transfer rate of
2.5 Mbits/second. The controller provides an interface to the system bus, as well as supporting up to 2
disk drives. The disk system records all data in
Double Frequency (FM)on 2 surfaces per platter.
Each platter can be write protected by a front panel
switch.
SPECIFICATIONS
Host Processor Boards
INTEGRATED PROCESSOR CARD
-(IPC-85) 8085A-2 based, operating at 4 MHz
-64K RAM, 4K ROM (2K in monitor and 2K in boot/
diagnostic)
RESIDENT PROCESSOR BOARD
-(RPB-86) 8086 based, operating at 5 MHz
-64K RAM, 16K ROM (application debugger)
BUS
CLIENT LAYER
-MULTI BUS system bus, maximum transfer rate of
5 MHz
INTERFACE
DIRECT MEMORY ACCESS
-(DMA) standard capability on the MULTIBUS
system bus; implemented for user selected DMA
devices through optional DMA module
-Maximum transfer rate of 2 MHz
Figure 3. Ethernet Architectural Layering
12-17
AFN·01975A
inter
"' .. :";.:
MODEL' 675
Transfer Rate-2.5 Mbits/sec.' ",
Access r'fime-'. Tr'ack Track: 13 ms max
, Full·Stroke: 100 ms'" '
, Rotational Speed: 2,400 rpm ' '
Ethernet CommunicationS .Cohtr'oller
.
PROCESS9R; ',' '; ,", ':>;'::; . ,;;, '
-8088 based; operating at 5 MHz
--: 16K.dynamic .RAM for program execution
-8K EPROM,for. prqgram execution, '
-8K Static RA,MJor datil buffer '
'
-:-3 DMA,channelsfor receive data
- t, DMA chan,nEiI for transIT,Iit dCl.ta
SerD~~',
"
"','
....:.S~rialization/Deserialization
, ;
.
to
~
. , ,. , - ; 'r.~, "
Physical
Cha~acteristics
'
Width'"-17.37 in.(44~12cm), '
Height:":"·15.81 in, (40.16 em) ,
Depth'--'-19.13 in: (48;59 cm)'
Weight-84.5 lb. (38.6 kg)
.'
-Framing
-CRC generation and checking
-Manchester encoding/d~c:()ding
-Destination address recognition
,'.1
,
Expansion Chassis
",
,:'.'.",.
Width:....:17.3i in: (44.12 cm)' ."
Height....:4.81Ih~(17.22 cm) :
Deptti....:19.13 ih: (48.59cmj
Weighf,::':'42Ib; (19 kg) "
Integral.FI()ppy Di$k' '
CapCl.city::-?50 Kbytes, (for~atted);, ,
Transfer Rate...,.160.Kbits/sec. '
Ac:cess Time~,
.
Track to Track;1Q rns !T1a~ . '
, Average Random Positioning:,260ns '
, Rotationa.1 SPI3,ed:360rpm: '. .,
Av~rage Rotati,C?naILa!ency:83 ms
Recording Mode: FM
Keyboard
Width-'-:17.3Zin. (44.1:i'drn )
Heig~t: 3:0 in. (22.86Cri1), "", ".
Deptl);"'9 . O,h:l.{22.86cm),'"
Vlieight~6Ib.(3kg)'
,
DualFloppy,Drive System (Option) :
Dual Floppy Disk Option
in. (42.88 em),::,
Height""" 12.08i n. (30;68cm),
Depth=,1.0,in; (48,26,cm) ,
"',
Weight-64Ib;(29 kg),;;; .,',
Width~16.88
Capacity"•
Per Disk: 4.1 Mbits (formatted)
Per Track: 53.2 Kbits (formatted),
Transfer Rate- 500 Kbitsisec
"
Access TimeTrack to Track: 10 ms ."
Head Setting Tiin'~: 10ms
, ..
Average Randor;n,positioil,ing:260 ms
Rotational Speed: 360 rpm
Recording Mode: M2 FM
Hard Disk Drive Option , ,
,'.
'
:.'~
... 'I.
.
Hard
'Disk Drive
System (Option)
:
.."..:
,
.'
.,.'
;
Width~18.5Iri:(47.0 cm)
Height....:34.0in. (86.4 cm) , ."
Depth"':'29.75 in;;(75.6cm)
Weight..1202 Ib.(92 k~},' "
'; ')
Type~5440t~pI6ading'ciHnidge a~d
~.
"
;,'
.• · .•• 1.\
one fixkd
.
platter'
., , , "
Tracks per Inch-200
Mechanical Sectors per Track-12
Recording Technique-double frequency (FM)
Tracks per Surface-400 bits/inch'
"
Density-2,200 bits/inch
Bits per Track-62,500
Recording Surfaces per Platter-2
Capacity. ,.. :~';" ' '
,:PerSLJrface"":15 Mbits ' '
'Per Plcitter....:29 Mbits ' "'," '.'
Per Drive":"'59 Mbits'
Per Drive-7.3Mbytes (formatted)
ELECTRICAL CHARACTERISTICS
,
,
DC Power Supply for Mainframe
.'
Volts
Supplied
Typical
Amps
..._System
Supplied "
Requirements
..
. 17.0
' 30.0
.,.
2..5 "
1.1
,.
..
"
0.3
0.1
,1.0 ,
0.08
1.5
1.5
1.7
1.7
"
,
"
..... ;
[
."j'
+5±5%
+12±5%
-12±5%
-10±5%
+15±5%*
+24±5%*
*Not
12'-18
,
.~.
avllilable on bus,
AFN,01975A
inter
MODEL 675
AC Requirements for Mainframe
Intel/ec Series /II Microcomputer Development
System Console Operating Instructions, 121609.
110V, 60 Hz-5.9 Amp
220V, 50 Hz-3.0 Amp
Intel/ec Series /II Microcomputer Development
System Pocket Reference, 121610.
DC Power Supply for Expansion Chassis
Intel/ec Series /II Microcomputer Development
System Programmer's Reference, 121618.
Volts
Supplied
Amps
Supplied
Typical
System
Requirements
+5±5%
+12±5%
-12±5%
-10±5%
24
2.0
0.3
1.0
None
None
None
None
iAPX 88186 Family Utilities User's Guide for
8086-Based Development Systems, 121616.
80861808718088 Macro Assembly Language Reference Manual for 8086-Based Development Systems, 121627.
80861808718088 Macro Assembly Language Pocket
Reference, 9800/49.
80861808718088 Macro Assembler Operating Instructions for 8086-Based Development Systems,
121628.
AC Requirements for Expansion Chassis
50-60 Hz, 115/230V AC
Intel/ec Series /II Microcomputer Development
System Instal/ation and Checkout Manual, 121612.
ENVIRONMENTAL CHARACTERISTICS
System Operating Temperature-16°C to 32°C (61°F
to 90°F)
Humidity-20% to 80%
Intel/ec Series /II Microcomputer Development
System Schematic Drawings, 121642.
ISIS-I/ CREDIT (CRT-Based Test Editor) User's
Guide, 9800902.
ISIS-I/ CREDIT (CRT-Based Test Editor) Pocket Reference, 9800903.
DOCUMENTATION SUPPLIED
Ethernet Communica tions Control/er Programmer's
Reference Manual, 121769.
Ethernet Development System Upgrade Kit Instal/ation and Checkout Manual, 121778.
The 8086 Family User's Manual, 9800722.
The 8086 Family User's Manual, Numeric Supplement, 121586.
For Series III Plus Hard Disk System Only:
Intel/ec Series /II Microcomputer Development
System Product Overview, 121575.
Model 740 Hard Disk Subsystem Operation and
Checkout, 9800943.
ORDERING INFORMATION
DS6758FD KIT Intellec Model 675 Development
System for Et,hernet with Dual Density Flexible Disk System (220VI
60 Hz)
Part Number
Description
DS675A KIT
Intellec Model 675 Development
System for Ethernet (110V/60 Hz)
DS6758 KIT
Intellec Model 675 Development
System for Ethernet (220V/50 Hz)
DS675AFD KIT Intellec Model 675 Development
System for Ethernet with Dual Density Flexible Disk System (110VI
60 Hz)
12-19
DS675AHD KIT Intellec Model 675 Development
System for Ethernet with Pedestal
Mounted Hard Disk (110V/60 Hz)
DS6758HD KIT Intellec Model 675 Development
System for Ethernet with Pedestal
Mounted Hard Disk (220V/50 Hz)
All models listed above require a Software License.
AFN·01975A
Microcomputer
Development Systems
Options
13
EXPANSION CHASSIS
INTELLEC® SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
• Four Expansion Slots for Intellec®
Series II Systems
• Cable Connectable to Main Intellec®
Bus
• Internal Power Supply
• Standard Intellec MULTIBUS™ with
Multi·Processor and DMA Capability
• Snug Fit Beneath Allintellec® Series II
Units
• Compatible with Standard Intellect
iSBC™ Expansion Modules
The Intellec Series II Expansion Chassis provides four expansion slots for use with Intellec Series II microcomputer development systems. With its own separate power supply, the expansion chassis may be fully
loaded with any boards needed to expand a user's Intellec Series II system. With the addition of the expansion
chassis, Intellec Series II Models 220 and 230 contain a total of ten slots, sufficient for any configuration
Intellec Series II system. The Intellec Series II Expansion Chassis is a compact chassis with a four slot
card cage, power supply, fans, and cable assemblies. It is designed to fit under any Intellec Series II system,
connect directly to the system bus through an opening in the top of the chassis, and provide additional slots
for the system users. The power supply is linked directly to the main chassis power supply, allowing power to
flow to both chassis when the main power is turned on.
13-1
AFN-OOB22B
EXPANSION CHASSIS
SPECI FICATlONS
Environmental Characteristics
Physical Characteristics
Operating Temperature -
17.37 in. (44.12 cm)
Height - 4.81 in. (17.22 cm)
Depth - 19.13 in. (48.59 cm)
Weight - 42 lb. (19 kg)
Width -
0' to 35'C (95'F)
Equipment Supplied
Expansion chassis
Cables
Reference Manuals
Intellec Series II Installation and Service
Guide (SUPPLIED)
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
9800550 -
Electrical Characteristics
DC Power Supply
Volts
Supplied
Amps
Supplied
+.5±5%
+12±5%
-12±5%
-10±5%
24
2.0
0.3
1.0
AC Requirements -
System
Requirements
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
None
None
None
None
50·60 Hz, 115/230V AC
ORDERING INFORMATION
Part Number
Description
MDS-201*
Intellec® Series II
Expansion Chassis
• MDS is an ordering code only and is not used as a product name or trademark. MDS" is a registered trademark of Mohawk Data Science.
13-2
AFN-OOB22B
intel'
MAINFRAME LINK FOR
DISTRIBUTED DEVELOPMENT
• Integrates user mainframe resources
with Intellec® Development Systems.
• Software runs under ISIS-II on any
Intellec® Development System .
• Communicates with remote systems on
dedicated or switched (dial-up)
telephone lines.
• Uses IBM 2780/3780 standard BISYNC
protocol supported by a majority of
mainframes and minicomputers.
• Package also includes tests and a
connector for loop-back self-test
capability.
• Protocol supports full error detection
with automatic retry.
The Mainframe Link consists of software, modem cable to connect the development system to the modem and
a loopback connector for diagnostic testing. The software runs under ISIS-II on Intellec DevelopmentSystems. It emulates the operation of an IBM 2780 or 3780 Remote Job Entry (RJE) terminal to (1) transmit ISIS-II
files to a remote system or (2) receive files from a remote system using standard BISYNC 2780/3780 protocoL
The remote system can be any mainframe or minicomputer which supports the IBM 2780 or 3780 communicationsinterface standard. Files may contain ASCII or binary data so that either program source files (ASCII) or
program object files (binary) may be transmitted.
The Mainframe Link allows the user to integrate in-house mainframe resources with Intellec Microcomputer
Development resources. The mainframe can be used for storage, maintenance and management of program
source and object files. The program source can be downloaded to a development system for compilation,
assembly, linkage, and/or location. The linked modules can be transmitted and saved on the mainframe to be
shared by all programmers. The linked 'program can then be downloaded to a development system for
debugging using ICE emulation.
USE MODEL 240 TO:
• COMPILE
• LINK/LOCATE
• ASSEMBLE
I
I
/
USE MAINFRAME TO:
•
•
•
•
•
•
•
CREATE SOURCE PROG, USING MULTIPLE CRT's
STORE BACKUP & MAINTAIN LARGE DISK FILES
LIST PROGRAMS USING FAST PRINTERS
TRACK UPDATES & VERSION CONTROL
PROTECT ACCESS TO SOURCE/OBJECT FILES
SHARE COMMON LIBRARIES & MASTER PROGRAMS
ORGANIZE. CONTROL. MANAGE LARGE PROJECTS
CRT
USE MODEL 230 FOR:
• SYMBOLIC DEBUGGING
USING ICE
Thefoltowing are trademarks of Intel Corporation and may be used only to identify Intel products: i, Intel,lNTEL,lNTELLEC. Mes, 1m, iCS, ICE, UPI, exp, iSSe, iSBX, INSITE. iRMX,
CREDIT, RMXIBO,J,LScope, Multibus, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE. sec. RMX or iCS and a numerical
suffix; e.g., iSBC-80.
©.Intel Corporation 1980
13-3
121633'()1A
~
inter
MAINFRAME LINK, .
FEATURES
Automatic tr,anslation from ASCII to EBCDIC
and vice versa
.. ;;,.'
• Runs under ISIS-II on any IntellecGll Microcomputik'Delielopment System.
.
.
Receive chaining fOr receiving multiple files
• Intel mode is, used mainly for file transfers between two. Intelle.ce!> Development Systems. The
files are duplicated exactly.
• Communicates with a remote system using IBM
2780/3780 standard BISYNC ~)rotocol, which is
supPorted .. by· a 'majotityof minicomputers and
mainframes, on dedic!ltedor switched (dial-up)
,.
'...,
.
telephone lines.
• Console. commands support all standard features
including:
SEND data in Transparent or Non-transparent
mode, with or without translation to EBCDIC
• The modem cable supplied with the package can
be used to connect the IntellecGll Development
.. , System to the modem'(ormodem eliminator)
, using the standard'RS232C pOrt.
.';
-
--
:'
.
RECEIVE in Transparent or Non-transparent
mode,\vith
or without
translation to
EBCDIC
.' .
.
. ,..'
. . ..
.
,
• :,~upports, user .selectable data transmission rates
.' of. uP to 9600 baud.
'.
Support for an IBM RJE console (such as HASP)
• Special utility prognunsare provided. STRZstrips
extra binary zero's from the end .of objecUiles.
CON SOL assigns system console input tei an ISISII disk f i l e . '
'
Ii' ~~tkage h;cludes diagnostic tests used to verify
the operation of the IntellecGll Development Sys',temusing the 'loop-back connector supplied and
'data',transmission up to the modem using the
analog loop,back feature. '
• Can process 'commarids'i~teractiveIY from the
console or sequentially from an ,ISIS-II file under
the SUBMIT facility for semi-automatic. batch
.operation.'
"
.
."SYstem can ~e.configured to m~tch the requirements of the installation, i.e., using modem
eliminators for conne.ctions up to fifty (50) feet, or
by using modems' and telephone lines.
• Error detection in line transmission and error recoverjby automatic retransmission.
• Software can be configured from several configuration options such as:
• A special command such as DIAGNOSE, allows
logging of all data activity on the line, during
transmission and reception.
2780,3780 or Intel Mode. ' ; ;
• When not used for communicating with the mainframe, the Intallece!> Development System is available as a complete, stand-alone system.
Transparent mode for binary, data
Non-transparent mode for ASCII data "
BENEFITS
• The compiled and/or linked object files may be
transmitted back to tl)e remote for storage. Updates and ,version nlJmbers and dates can be
tracked to ensure tha~ the latest version is always
used and back-up files are available. Binary object
files can be later downloaded to an Intellec Development Systemf.or. debugging using an ICE
emulator.
• Allows the customer to use an in-house mainframe or minicomputer for program sourcepreparation, editing, back-up and maintenance
using inexpensive CRT's and multi-terminal access. The common files may be shared and others
protected.
.
• Many programmers can use and share the hlghperformance devices normally avaiiable on large
computer systems, e.g., fast printers to reduce
listing time, the large capacity disks with their fast
access time to store large program files.
• In short, provides a powerful and flexible tool
combining the best of both micro and mainframe
worlds, i.e., powerful .CPU with large disk capacity,file sharing, miJlti-terminal access, etc.,
·from a mainframe' or minicomputer with Intel's
versatile, and compatible, software support systems (including PUM, PASCAL, FORTRAN, Assembler, R & L) and sophisticated debugging
tools such as ICE emulators.
• The source files can be downloaded using the
Mainframe Link to an Intellec Development System (e.g., Model 240 or 245) for compilation, linking and locating.
13-4
inter
MAINFRAME LINK
SPECIFICATIONS
Remote System Requirements
Operating Environment
• IBM 2780/3780 BISYNC protocol as supported by
a majority of mainframes and minicomputers including: all IBM-360/370 Systems, PDP-11/70,
VAX-11/780, Data General ECLIPSE.
Required Hardware:
• Users should purchase this standard software
package from the remote system vendor and any
additional required. hardware such as a synchronous communications interface.
Intellecrt haul
synchronous modems and telephone lines.
Required Software:
• For distances greater than four miles, use synchronous modems and telephone lines. The following BELL modems or their equivalents are
recommended:
ISIS-II Diskette Operating System
Single or Double Density
BELL 201C 2400 bits/second
'.
. (half dupleJ:<, switched line)
.. BELL 208A. 4800 bits/second'
. '(full duplex, leased line)
'. BELL 208B4800, bits/second
(half duplex, switched line)
BELL209A 9600 bits/second
.
(full duplex, leased line)
Documentation Package
Mainframe Link User's Guide '(121565-001).
Shipping Media
Flexible Diskettes
Single and Double Density
• Modems at eit!1e~ end must be cOrT)patible.
ORDERING INFORMATION
Part Number
Description
*MDS-384 Kit
Mainframe Link for
Distributed Development
*MDS is an ordering code only and is not used as a product name or trademark.
MDSO THEN
DO;
NUMCH = NUMCH + 1; DIGITS(NUMCH) = C;
C= DIGITS(NUMCH)/10;
DIGITS(NUMCH)= DIGITS(NUMCH) - 10*C;
END
END;
24
2
END FACTORIAL;
25
END;
1able 1. PL/M·80 Compiler Sample Factorial Generator Procedure
SPECI FICATIONS
Operating Environment
Required Hardware
Intellec microcomputer development system
65K bytes of memory
Dual diskette drives
System console - teletype
Optional Hardware
CRT as system console
line printer
Required Software - ISIS·II. diskette operating system
ORDERING INFORMATION
Shipping Media
Diskette
Reference Manuals
980026 - PUM 80 Programming Manual (SUPPLIED)
9800300 - ISIS·II PUM 80 Compiler Operator's Manual
(SUPPLIED)
Reference manuals are shipped with each product only
If designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Requires software license
Product Code
Description
MDS-PLM*
PUM 80 High level language compiler
• MDS is an ordering code only and is not used as a product name or trademark. MDS" is a registered trademark of Mohawk Data Sciences
Corporation.
15-23
ICE-BOTM
BOBO IN-CIRCUIT EMULATOR
• Connects Intellec® System to User'
Configured System Via an External
Cable and 40~pin Plug, Replacing the
User System 8080
• Eliminates Need for Extraneous
Debugging Tools Residing in User
System
• Allows Real-Time (2 MHz) Emulation of
User System 8080
• Provides Address, Data, and 8080
Status Information on Last 44 Machine
Cycles Emulated
• Shares Intellec® RAM, ROM, and PROM
Memory andlntellec® I/O Fa.cilities with
User System '
• Provides Capability to Examine and
Alter CPU Registers, Main Memory, Pin,
and Flag Values
,
.
.
• Checks for Up to Three Hardware and .
Four Software Break Conditions
• Integrates Hardware and Software
Development Efforts
• Offers Full Symbolic Debugging
Capabilities
• Available in Diskette or Paper Tape
Versions
The Intellec ICE-80 8080 In-Circu.itEmulator is an Intellec resident module designed to interface with any user configured 8080 system. With' ICE-80as a replacement for a prototype system 8080, the designer may emulate the
system's 8080 in real time, single step the system's program, and substitute Intellec memory and I/O for user system
equivalents. Powerful Intellec debug functions are extended into the user system. For the first time the designer may
examine and modify his system with symbolic references instead of absolute values.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: i, Intel, INTEL, INTELLEC, MeS, i m, les, ICE, UPI, BXP, iSBC, iSBX, iNSITE, iRMX,
CREDIT, RMXJ80, MScope, Multibu5, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE.. SSC, RMXor leS and a numerical
suffix; e.g., iSBG-SO.
7
© Intel Corporation 1980
15 24
ICE·801M IN·CIRCUIT EMULATOR
during system debugging. By referring to symbolic
memory addresses, the user may be assured of examin·
ing, changing, or breaking at the intended location.
FUNCTIONAL DESCRIPTION
Integrated Hardware/Software Development
Symbolic Reference - ICE·80 provides symbolic defini·
tion of all 8080 registers, flags, and selected pins. The
following symbolic references are also provided for user
convenience: TIMER, a.16·bit register containing the
clock pulses elapsed during emulation;
number of
ADDRESS, the address of the last instruction emulated;
INTERRUPTENABLED, the user 8080 interrupt mechan·
ism status; and UPPERLIMIT, the highest RAM address
occupied by user memory.
Use of the ICE·80 module enables the system integra·
tion phase, which can be so costly and frustrating when
attempting to mesh completed hardware and software
products, to become a convenient two·way qebug tool
when begun early in the design cycle. The user proto·
type need consist of no more than an 8080 CPU socket
and a user bus to begin integration of software and hard·
ware development efforts. With the ICE·80 mapping
capabilities, system resources may be accessed for
missing prototype hardware. Hardware designs may be
tested using system software to drive the final product.
A functional block diagram of the ICE·80 module is
shown in Figure 1.
'2
Debug Capability Inside User System
ICE·80 provides for user debugging of full prototype or
production systems without introducing extraneous
hardware or software test tools. ICE·80 connects to the
user system through the socket provided for the user
8080 in the user system (See Figure 2). Intellec memory
is used for the execution of the ICE·80 software, wh ile
1/0 provides the user with the ability to communicate
with ICE·80 and receive information on the generation of
the user system. A sample ICE·80 debug session is
shown in Figure 3.
Symbolic Debugging Capability
ICE·80 provides for user·defined symbolic references to
progr;lm memory addresses and data. Symbols may be
substituted for numeric values in any of the ICE·80 com·
mands. The user is thus relieved from looking up
addresses of variables or program subroutines.
Symbol Table - The user symbol table generated along
with the object file during a PUM·80 compilation or a
MAC80 or resident assembly, is loaded to memory along
with the user program to be emulated. The user may add
to this symbol table any additiona.l symbolic values for
meniory addresses, constants,or.variables found useful
110 Mapping and Memory
Memory and 1/0 for the user system may be resident in
the user system or "borrowed" from the Intellec system
through ICE·80's mapping capability.
.
16 ADDRESS
8DATAOUT
8 OATA IN
CONTROL
r-----------------l
I
I
I
I
I
I
I
I
I
I
I
I
I
~--~--------------~
~
~~---------I
I
I
I
L_
CONTROL}
8 DAT4B~TS
It ADDRESS BITS·
INTELLEC sus
• Figure 1. Functional Block Diagram of ICE·SO Module
15-25
ICE·80™IN.CIRCUIT EMULATOR
ICE·BO trace board .. ICE·BO and the system alsocommu·
nicate through a control block resident in the Intellec
main memory, which contains detailed configuration
and status information transmitted at an em uIatio 11
break: ICE·BO hardware consists of two PC boards - the
processor and trace boards residing in the Intellec chas·
sis- and a 6·foot cable interfacing to the user system,
The trace.and processor boards communicat.e with the
sYstem on the bus, and also with each other on a separ·
ate ICE·BO bus. ICE·BO connects to the user system
through a cable that. plugs directly. into the socket
provided for .th~user's BOBO.
.
TraceBoa~d
The trace board .talksto the system as a peripheral
device. It receives commands to ICE·BOand returns
ICE·BO. responses. While ICE·BO is executing the user
program, the trace board collects data for each machine
cycle emulated (snap data). The informationis·continu;
ously stored in high·speed bipolar. memory.,
Figure 2. ICE·SO Module Installed in User System
Memory Blocking -, ICE·BO separates user memory into
16 4K blocks .. User 1/0 is divided into 1616,port blocks.
Each block of memory or 1/0 may be defined independ·
ently. The user may assign system equivalents to take
the place of devices not yet designed for the user sys·
tem during prototyping. In addition, memory or I/O may
be accessed in place of user system devices during pro·
totype or production checkout.
Error Messages - The user may also designate a block
of memory or 1/0 as nonexistent. ICE·BO issues error
messages when memory or 1/0 designated as nonexist·
ing is accessed by the user program.
Real· Time Trace
ICE·BO captures valuable trace information while the
user is executing programs in real time. The BOBO status,
the user memory or port addressed, and the data read or
written (snap data), is stored for the last 44 machine
cycles executed. This provides ample data for determin·
ing how the user system was reacting prior to emulation
break. It is available whether the break was user initio
ated or the result of an error condition. For detailed
information on the actions of CPU registers, flags, or
other system operations, the user may operate in single
or multiple step sequences tailored to system debug
needs.
Hardware
The heart of the ICE·BO is a microcomputer system uti·
lizing Intel's BOBO microprocessor as its nucleus. This
system communicates with the Intellec host processor
via 1/0 commands. Host processor commands and
ICE·BO status are interchanged through registers on the
Breakpoint -The trace board also contains two 24·bit
hardware breakpoint registers which can be loaded by
the user. While in emulation mode, a hardware compari·
tor is constantly monitoring address and status lines for
amatch t,o terminate anemulat.ion. A user probe is a.lso
available for attachinentto any user sjgnaLWhen this
signal goes true a break condition is recognized.
Interrogation- The trace board signals the processor
board when a command to ICE·BO or break condition has
been detected. The ICE·BO CPU then sends data stored
on the trace board to the c,ontrol block in memory. Snap
data, along with information on BOBO registers and pin
status and the reason for the emulation break, are then
available for access during interrogation mode. Error
conditions, if present, are transmitted and automatically
displayed for the user.
Processor Board
An BOBO CPU resides on the processor board. During
emulation it executes instructions from the user's pro·
gram. At all other times it executes instructions from
the control program in the trace module's ROM.
Timing - The processor board contains an internal
clock generator to provide clocks to the user emulation
CPU at 2 MHz. The CPU can alternately be driven by a
clock derived from user system signal lines. The clock
source is selected by a jumper option on the board. A
timer on the trace board counts theh clock pulses duro
ing emulation and can provide the user with the exact
timing of the emulation.
On/Off Control - The processor board turns on an emu·
lation when ICE·BO has received a run command from
the system. It terminates emulation when a break condi·
tion is detected on the trace board, or the user's pro·
gram attempts to access mem,ory or I/O ports
deSignated as nonexistent in the user system, ,or the
user BOBO is inactive for a quarter of a second.
Status Storage -The address map Ibcated on the proc·
essor board stores the assigned location of each user
memory or I/O block. During emulation the processor
board determines whethertosenci/receiveinformation
15-26
ICE·80™IN·CIRCUIT EMULATOR
ISIS BOBO MACROASSEMBLER, Vl.0
PAGE 1
:USER PROGRAM TO OUTPUT A SERIES OF
:CHARACTERS TO SDK·BO CONSOLE DEVICE
1320
01E3
CO
13200601
13223A3613
1354F
1326 CDE301
132979
132A 93
132B 32371'3
132E FE40
1330 C22513
1333 C32013
START:
1336 SA
1337
0000
DAn:
RSLT:
LOOP:
ORG
EOU
1320H
lE3H
MVI
LOA
MDV
CALL
MOV
SBB
STA
CPI
.JNZ
JMP
B,l
DAn
C,A
CO
A,C
B
RSLT
40H
LOOP
START
DB
OS
END
:SDK·BO CONSOLE OUT DRIVER
:SET UP B VALUE
:LOAD A WITH DAn VALUE
:SEND C VALUE TO CONSOLE
:RESTORE A
:SUBTRACT B FROM A
:STORE RESULT IN RSLT
:LAST VALUE TO PRINT
:LOOP AGAIN IF A>40H
:ELSE RESTART WHOLE PROCEDURE
5AH
ISIS, Vl.0
INITIAL ICE·BO SESSION
-ICE80
(Nole: The SOK-SO Monitor has already been used to initialize the SDK-SO Board)
ISIS ICE·BO, Vl.0
··XFORM MEMORY 0 TO 1 U
·XFORM 10 OFH U
CD
®
@
@
®
®
o
®
·LOAD PROG. HEX
ERR = 067
STAT=l1H TYPE=06H CMND=07H ADDR=1320H GOOD=06H BAD=04H
·CHANGE MEMORY 1321H = FFH
ERR = 067
STAT=l1H TYPE=06H CMND=07H ADDR=1321H GOOD=FFH BAD=FDH
·LOAD PROG. HEX
·GO FROM START UNTIL RSLT WRITTEN
EMULATION BEGUN
ERR=067
STAT=l1H TYPE=07H CMND=02H
·DISPLAY CYCLES 5
STAT=A2H ADDR=1326H DATA=CDH
STAT = B2H ADDR = 1327H DATA = E~H
STAT=B2H ADDR=132BH DATA=OlH
STAT = 04H ADDR = FFFFH DATA = 13H
STAT= 04H ADDR = FFFEH DATA = 29H
·CHANGE DOUBLE REGISTER SP = 13FFH
·BASE HEX
·EaUATE STOP=.1333H
·GO FROM START UNTIL STOP EXECUTED THEN DUMP
EMULATION BEGUN
B= 01H C=41H D=OOH E =OOH H = OOH L= OOH F= 56H A=40H P= 1320H • = 1333H S= 13FFH
EMULATION TERMINATED AT 1333H
·EXIT
·FFFF
Notes
1. Set up user memory and 110. The program is set up to execute in block 1 (1000H-1FFFH) of user memory, and requires access to the SDK-80
monitor (block 0) and 110 ports in block OFH. Both ports and memory are defined as available to the user system. All other memory and 110 is initial·
ized by ICE'80 as nonexistent (guarded).
2. A load command generates an error. The type and command numbers indicate that a data mismatch occurred on a write to memory command.
The data to be written to address 1320H should have been OBH. When ICE·80 read the data after writing it, a 04H was detected. A change command
to a different memory address hints that bit 1 does not go to 1 anywhere in this memory block. Examination indicates that a pin was shorted on the
RAM located at 1300H-13FFH in the prototype system. The problem is fixed and a subsequent load succeeds.
3. A real·time emulation is begun. The program is executed from 'START' (1320H) and continues until 'RSLT' is written [in location 1328H, the can·
tents of the accumulator is stored in (written into) 'RSLT'J.
4. An error condition results: TYPE 07, CMND 02 indicate the progr~m accessed is a guarded area.
5. The last 5 machine cycles executed are displayed. The last Instruction executed was a call (CDH). The fourth and fifth cycles are a push operation (designated by status 04H) to store the program counter before executing the call. The stack pointer was not initialized in the program and is accessing memory location FFFFH.
6. After making a note to initialize the stack pointer in the next assembly, a temporary fix is effected by setting the stack pointer to the top of user
available memory.
7. After setting the base for displays to hex and adding the symbol 'STOP' to the symbol table, emulation is started which will terminate when the
instruction at 1333H ('STOP') is executed. When emulation terminates, a dump of the contents of user8080 registers is requested. One can see that
the value of the accumulator Is. set at 40H, the stack pointer is set at 13FFH, the last address executed (.) is 1333H. and the program counter has
been set to 1320H.
8. Exit returns control to the MDS monitor.
Figure 3. Sample ICE·aO Debug Session
15-27
ICE·801M IN·CIRCUIT EMULATOR
on the Intellec or user bus by consulting the address
map. The processor board allows the ICE-80 CPU to gain
access to the bus as a master to "borrow" Intellec facilities. At an emulation break, the processor board stores
the status of specified 8080 input and output signals,
disables all interaction with the user bus, and commands the trace board to send stored information to a
control block in Intellec memory for access during interrogation mode.
Cable Card
a broad range of modifiers to provide the user with maximum flexibility in describing the operation to be performed. Listings of emulation commands, interrogation
commands, and utility commands are provided in Table
1, Table 2, and Table 3, respectively.
Base
Establishes mode of display for output
data.
Display
Prints .contents of memory, 8080 registers, input ports, 8080 flags, 8080 pins,
snap data, symbol table, or other diagnostic data on list device. May also be
used for base-to-base conversion, or for
addition or subtraction in any base.
Change
Alters contents of memory, register, out.
put port, or 8080 flag.
XFORM
Defines memory and I/O status.
Search
Looks through memory range for specified value.
The cable card is included for cable driving. It transmits
address and data bus information to the user system
through a 40-pin connector that plugs into the user system in the socket designed for the 8080 when enabled
by the processor module's user bus control logic.
Software
The ICE-80 software driver is a RAM-based program providing easy to use English language commands for
defining breakpoints, initiating emulation, and interrogating and altering the user system status recorded
during emulation. ICE-80 commands are configured with
Operation
Command
Operation
Command
Table 2. ICE-SO Interrogation Commands·
Command
Operation
Load
Fetches user symbol table and object
code from input device,
Save
Sends user symbol table and object code
to output device.
Initiates emulation in single or multiple
instruction increments. User may specify
register dump or tailor diagnostic activity to his needs following each step, and
define conditions under which stepping
should continue.
Equate
Enters symbol name and ·value to user
symbol table.
Fill
Fills memory range with specified value.
Move
Moves block of memory data to another
area of memory.
Range
Delimits blocks of instructions for which
register dump or tailored diagnostics are
to occur.
Timeout
Enables/disables user CPU 1/4 second
wait state timeout.
List
Continue
Resumes real-time emulation.
Defines list device (diskette-based version only).
Call
Emulates user system interrupt.
Exit
Returns program control to monitor.
Go
Step
Initiates real-time emulation and allows
user to specify breakpoints, data retrieval,
and conditions under which emulation
should be reinitiated.
Table 1. ICE-SO Emulation Commands
Table 3_ ICE-SO Utility Commands
SPECI FICATIONS
Diskette·Based
Operating Environment
Paper Tape·Based
Operating Environment
Required Hardware
Intellec system
32K bytes RAM memory
System console
Intellec diskette operating system
ICE-80 module
Required Hardware
Inteliec system
System console
Reader device
Punch device
ICE-80 module
Required Software
System monitor
Required Software
System monitor
ISIS-II
15-28
<:::7"
".
ICE·80lM IN·CIRCUIT EMULATOR
System Clock
Crystal controlled 2.1B5 MHz±0.01%. May be replaced
by user clock through jumper selection.
100 = 79 mA max; 45 mA typ
V BB = -9V, ±5%
IBB= 1 mA max; 11'A typ
Environmental Characteristics
Physical Characteristics
Operating Temperature -
12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - B.OO Ib (3.64 kg)
Width -
Operating Humidity -
O·C to 40·C
Up to 95% relative humidity
without condensation
Equipment Supplied
Printed circuit modules (2)
Interface cables and buffer board
ICE·BO software driver, paper tape version
(ICE·BO software driver, diskette·based version is sup·
plied with diskette operating systems)
Operator's Manual
Electrical Characteristics
DC Power Requirements
Vee= + 5V, ± 5%
lee = 9.81 A max; 6.90A typ
Voo= + 12V, ± 5%
ORDERING INFORMATION
Part Number
Description
MDS·BO·ICE'
BOBO CPU in·circuit emulator, cable
assembly and interactive software
included
'MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences
Corporation.
15-29
inter
ICE-858™
MCS-85™ IN-CIRCUIT EMULATOR
'WITH MULTI-ICE™ SOFTWARE
• Connects the Intellec® system
resources to the user-configured' .
system via a 40-pin adaptor plug
• Executes user system software· in
real-time (5 MHz clock)
• Allows user-configured system to
share Intellec® memory and I/O
facilities
• Offers full symbolic debugging
capability for both assembly language
and Intel's high-level compiler
languages PL/M-80 and FORTRAN-80
• The Multi-ICETMsoftware provides:
-for two In-Circuit Emulators to
operate simultaneously in a single
Intellec Microcomputer Development
System.
.
• Provides 1023 states of 8085 trace data
-support for ICE 85/85™;85/49TM, and
85/41A:MEmulator.combinations
• Displays trace data from the user's
8085 in assembler mnemonics and
allows personality groupings of data
sampled by the external 18-channel
trace module
-enhanced software features:
symbolic display of addresses,
.. macro commands, compound
commands, software
synchronization of processes, and
INCLUDE file capability.
The ICE-858™ module resides in the Intellec® Microcomputer Development System and interfaces to the user
system's 8085. It provides the ability to examine and alter MCS-85™ registers, memory, flag values, interrupt
bits and I/O ports. Using the ICE-858 module, the designer can execute prototype software in real-time or
single-step mode and can substitute Intellec® system memory and I/O for user system equivalent. ICE
capability can be extended to the rest of the user system peripheral circuitry by allowing the user to create and
execute a library of user-defined peripheral chip analyzer routines.
Multi-ICE In-Circuit Emulator is a software product which allows two Intel In-Circuit Emulators to run
simultaneously in a single Intellec Microcomputer Developme.nt System. Multi-ICE software used in lieu ofthe
standard ICE software gives users full control of the two ICE modules for debugging of multi-processor
systems.
©INTEL CORPORATION, 1980.
AFN·01557A
ICE-85BTM IN-CIRCUIT EMULATOR
SYMBOLIC DEBUGGING CAPABILITY
to provide ready acknowledge when accessing
resources mapped to the Intellec.
ICE-858 allows the user to make symbolic references to I/O ports, memory addresses and data in his
program. Symbols and PUM-80 statement number
may be substituted for numeric values in any of the
ICE-85 commands. The user is relieved from looking
up addresses of variables or program subroutines.
The user symbol table generated along with the object file during a PUM-80 or FORTRAN-80 compilation or by the ISIS-II 8080/8085 Macro Assembler is
loaded into the Intellec® System memory along with
the user program which is to be emulated. The user
may add to this symbol table any additional symbolic
values for memory addresses, constants, or variables that are found useful during system debugging. 8y referring to symbolic memory addresses,
the user can examine, change or break at the intended location.
ICE-858 provides symbolic definition of all 8085 registers, interrupt bits and flags. The following symbolic references are also provided for user convenience:TIMER, the low-order 16 bits of a register
containing the number of 2 MHz clock pulses
elapsed during emulation; HTIMER, the high-order
16 bits of the timer counter; PPC, the address of the
last instruction emulated; 8UFFERSIZE, the number
of frames of valid trace dat.a (between 0 and 1022).
The user can also designate a block of memory or I/O
as nonexistent. ICE-858 issues error messages
when memory or I/O designated as nonexistent is
accessed by the user program.
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The user prototype need consist of no more than an
8085 CPU socket and a user bus to begin integration
of software and hardware development efforts.
Through ICE-858 mapping capabilities, Intellec®
System equivalents can be accessed for missing
prototype hardware. Hardware designs can be
tested using the system software which will drive the
final product.
The system integration phase, which can be so
costly when attempting to mesh completed hardware and software products, becomes a convenient
two-way debug tool when begun early in the design
cycle.
PERSONALITY GROUPED DISPLAYS
Trace data in the 1023 by 42-channel real-time trace
memory buffer is displayed in easy to read format.
The user has the option to specify trace data displays in actual 8085 assembler instruction
mnemonics. The data collected from the External
Trace Module can be grouped and symbolically
named according to user specifications and displayed in the appropriate number base designation.
Simple ICE-858 commands allow the user to select
any portion of the 42-bit trace buffer for immediate
display.
MEMORY AND I/O MAPPING
INTERROGATION AND
UTILITY COMMANDS
DISPLAY/
CHANGE
Display/Changes the values of symbols
and the contents of 8085 registers,
pseudo-registers, status flags, interrupt bits, I/O ports and memory.
EVALUATE Displays the value of an expression in
the binary, octal, decimal or hexadecimal.
Memory and I/O for the user system can be resident
in the user system or "borr,owed" from thelntellec®
System through ICE-858's mapping capability.
SEARCH
Searches user memory between locations in a user program for specified
contents.
ICE-858 separates user memory into32 2K blocks.
Each block of memory can be defined independently. The user may assign Intellec® System equivalents to take the place of devices not yet designed
for the user system during prototyping. In addition,
Intellec® System memory or I/O can be accessed in
place of suspect user system devices during prototyping or production checkout.
CALL
Emulates a procedure sterting at a
specified memory address in user
memory.
ICALL
Executes a user-supplied procedure
starting at a specified memory address
in thelntellec® System memory.
EXECUTE
Saves emulated program registers and
emulates a user-supplied subroutine to
access peripheral chips in the user's
system.
User ready synchronization-resource borrowing
from the Intellec System is (at user option) independent of the user system; the user does not need
15-31
ICE-85BTM IN-CIRCUIT EMULATOR
REAL TIME TRACE
EXTERNAL TRACE MODULE
ICE-85S captures valuable trace information from
the emulating CPU and the External Trace Module
while the User is executing programs in ,real time.
The 8085 status, the user memory orport addressed,
the data read or written, the serial data lines and data
from 18 external signals, is stored for the last 1023
machine states executed (511 machine cycles).This
provides ample data for determining how the user
system was reacting prior to emulation break. It is
availablewhetherthe break was user-initiated or the
result 01an error condition.
TTL level signals from 18 points in the user system
may be synchrbnously sampled by the External
Trace Module and collected in ICE"85S'strace buffer. The signals can be collected from asingle peripheral chip viathe supplied40-pin DIP clip or may
be placed by the user on up to 18 separate signal
nodes using the supplied 18 individual probe clips.
These signals are included in the 42-channel break"
pOint comparisons and clock qualifiers. Also, data
from:these.18 channels maybe displayed in meaningful,' user-defined groupings.
'
For detailed informatiori onthe actions of CP,U registers,flags, or other system operations,' the user
may operate in single or mUlti-step sequences tai":
lored to system debug needs.
SYNCHRONOUS OPERATION
WITH OTHER DESIGN AIDS
ICE-85Scanbe synchronized with other Intellec®
design aids by means of two external synchronization lines. These lines are used to enable and disable
ICE-85S trace data collection' and to cause break
conditions based on an external signal which may
not be included in the ICE-85S breakpoint registers.
In addition, ICE~85S cangeherate signals on these
lines which may be used to control other design
aids.
'.
,
BREAK REGISTERS!
TRACE MEMORY
ICE-85S has two breakpoint registers which are
used to break emulation, and two traceqlJalifier
registers which areusedto"control the collection of
trace" data during "emulation. Each register is 42
entries wide, one eritry for each channel and each
entrY can take anyone of the three values 0, 1 or
"don'feare."
"
"
EMULATION CONTROLS AND
COMMANDS
GROUP
GO
STEP
PRINT
'Defines into a symbolically named
group, a channel Or combination of
channels from the 8085 Microprocessor
and/or the External Trace Module.
Initiates reaHime emulation and controls emulation break conditions.
Initiates emulation in single instruction
steps. User may specify the type and
amount of information displayed following each step, and define conditions
" uride(whichstepping'should coritinue."
Prints the user-specified portion of the
trace memory to the selected Iist device.
15-32
The trace buffer, also 42 entries wide; collects data
salllpledfrom 24 8085 processor channels and 18
external channels sampled by the External Trace
Module. The Signals collected from the 8085 include
address lines, data lines, status lines and serial input
and output lines. The 18 channels ,extending- from
the External Trace Module synchronously sample
and collect into the trace buffer any usercspecified
TTL compatible signal from the rest of the prototype
system, "Sreak" and "trace qualification"may
therefore occur as a result of a match'of any combination of up, to,42 channels of CPU and external
circuitry signals.
MULTI-ICE™OPERATION
Multi-ICE software is a debug tool which allows two
ICE emulators to begin and stop in sequence: Once
started, two ICE emulators emulate simultaneously
and independently. Thus,'Multi-ICE software permits the debugging of asynchronous or synchronous' multi-processor systems.
ICE-8SB™ IN-CIRCUIT EMULATOR
Macro Command
A conceptual model for the Multi-ICE software can
be illustrated with the following block diagram.
A macro is a set of commands which is given aname.
Thus, a group of commands which is executed frequently may be defined as a macro. Each time the
user wants to execute that group of commands, he
may just invoke the macro by typing a colon followed by the macro name. Up to ten parameters may
be passed to the macro.
Block Diagram of Multi-ICETM Operation
There are three processes in the Multi-I.GE environment: the Host process and the two ICE proceSses to
control the two ICE hardware modules. The processorfor these three processes is the microcomputer in the Intellec Microcomputer Development
System. Only the Host process is active when MultiICE software is invoked. The Parser interfaces with
the console, receives commands from the console
or from a file, translates them into intermediate
code, and loads the code into the Host command
code buffer or ICE command code buffers.
The Host process executes commands from its
command code buffer using the execution software
and hardware of the Host's current environment,
either environment 1 or environment 2 (EN1 or EN2),
as required. EN1 and EN2 are the operating
environments of the two In-Circuit Emulators.
The user can change the execution environment
(from EN1 to EN2 or vice versa) with the SWITCH
command. Once the environment is selected, ICE
operation is the same as with standard ICE software.
In addition, the enhanced software capabilities are
available to the user.
The two ICE processes (PR1 and PR2) execute
commands from their command code buffers in
their own environments (PR1 in EN1 and PR2 in
EN2). The main functions of the two ICE execution
processes are to control the operations of the two
ICE hardware sets. The ACTIVATE command controls the execution ofthe ICE processes. Commands
are passed on to each ICE unit to initiate the desired
ICE functions.
The two ICE hardware units accept commands from
the Host process or ICE processes. Once emulations
start, the two ICE hardware sets will operate untila
break condition is met or processing is interrupted
by commands from the ICE execution processes.
Macro commands may be defined at the beginning
ota debug session andthen can be used throughout
the whole session. If the user wants to save the
macros for later use, he may use the PUT command
to save the macro on diskette, or the user may edit
the macro file off-line using the Intellec text editor.
Later, the user may use the INCLUDE command to
bring in the macro definition file that he created.
Example:
-DEFINE MACRO
INITMEM
.*SWITCH
=' EN1
.*BYTE 0 TO 100=0
.*LOAD:F1 :DRIVER
.*SWITCH = EN2
.*LOAD:F1 :DR2
.*EM
;This macro clears the .
memory and then loads the
programs.
;Select environment 1 (ICE
Module 1)
;Initialize memory to O.
;Load user program into
memory for ICE Module 1.
;Select environment 2 (ICE
Module 2)
;Load user program into
memory for ICE Module 2
; End of Macro
;To execute this Macro, user
types :INITMEM
Compound Command
Compound commands provide conditional execu c
tion of commands (IF Command) and execution of
commands repeatedly until certain conditions are
met (COUNT, REPEAT Commands).
Compound commands and Macro commands may
be nested any number of times.
Example:
-DEFINE .1 = 0
-COUNT 100H
.*IF .1 AND 1 THEN
..*BYT.I = .1
..*END
,*.1 = .1
.*END
+1
;Define symbol .1 to 0
;Repeat the following
commands 100H times
;Check if .1 is odd
;Fill the memory at location .1
to value .1
;Increment .1 by 1
;Command executes upon
carriage-return after' END
Symbolic Display of Addresses
INCLUDE File Capability
The user has the option of displaying a 16-bit
address in the form of asymbol name or line number
.
plus a hex number offset.
The INCLUDE command causes input to be taken
from the file specified until the end of the file is
encountered,at which pOint,input continues to be
15-33
-
ICE-85BTM IN-CIRCUIT EMULATOR
taken from the previous source. Nesting of INCLUDES is permitted. Since the command code file
can.be complex, the ability to edit offline becomes
desirable. The INCLUDE command allows the user
to pull.in command code files and Macro commands
created offline which can then be used for the particular debugging session.
Software Synchronization of Processes
Up to three processes (Host, PR1 and PR2) can be
active simultaneously in the system. An ICE process
can be activated (ACTIVATE), suspended (SUSPEND), killed (Kill), or continued (CONTINUE). The
Host process can wait for other processes to become dormant before it becomes active again.
Through these synchronization commands, the user
can create a system test file off-line yet be able to
synchronize the three processes when the actual
system test is executetj.
Example:
'INCLUDE :F1 :PROG1
'MAP 0 lENGTH 64K·
=USER
'MAP 10 0 TO FF
=USER
'SWITCH = EN2
'lOAD :F2:lED.HEX
'SWITCH ;"EN1
PROCESSOR 1
PAOCESSOR 1
DORMANT
;Cause input to be taken
from file PROG1
;Contents of the file
PROG1 are listed on
screen as they are
executed.
Example:
The capabilily of the software synchronization
commands is demonstrated by the following example. The flowchart shows the synchronization
requirements. The program steps show the actual
implementation.
;End of the file PROG1
;After the end of file is
reached, control is
returned to console.
HOST PROCESSOR
I
PROCESSOR 2
I
I
1
- - TAC-;;E-
ACTIVATE PROCESSOR 1
I PROCESSOA 2
I DORMANT
'ACTIVATE PAl
,'GO FROM 800
:END
PR1 EMULATION BEGUN
'SWI='EN2
'REPEAT.
. 'WHILE PC < > .LOOP
,'ACT PA2
.:GO TilL .LOOP OR .END
--~-.-
.,'REGISTER
.. ·END
:WAIT PR2
:IF PC=.LOOP THEN
.."SUSPEND PR1
.,·END
,'END
:Activale PAt
:Start ICE Module 1
;End of Activate block
:Switch execution Environment to EN2
;Repeat the following block of
commands while PC is not equal to .Loop
;Activate PR2
;Go till instruction at location .Loop
or at location .END is executed
;Display the registers
;End of Activate block
:Wait until PR2 is dormant
:End of IF block
;End of REPEAT block
I PAOCESSOR 2
I OOfU....~T
Flowchart of the Example for Demonstrating Multi-ICETM Synchronization Capability .
15-34
'OJ
ICE,.85B™IN-CIRCUIT EMULATOR
SPECIFICATIONS
Emulation Clock
ICE·858™ Operating Environment
User's system clock.or ICE-85B adaptor socket
(10.0 MHz Crystal)
Required Hardware:
Intellec® Microcomputer Development System
(S4K bytes RAM for Multi-ICE software)
(32K bytes RAM single ICE software)
System Console
Intellec® Diskette Operating System
ICE·85B Module
Required Software:
System Monitor
ISIS-II
ICE-85B or Multi-ICE Software
Physical Characteristics
Printed Circuit Boards:
Width: 12.00 in. (30.48 cm)
Height: S.75 in. (1715 cm)
Depth: 0.50 in. (1.27 cm)
PackagedWeight: S:OO Ib (2.73 kg)
Electrical Characteristics
DC Power:
Vee = + 5V ± 5%
lee = 12A maximum; 10A typical
V DO = + 12V ± 5%
...
100 = 80'mA maximum; SO mA typical
V BB = - 10V ± 5%
I BB = 1 mA maximum; 10 /LA typical
Equipment Supplied
18-Channel External Trace Module
Printed Circuit Boards (2)
Interface Cable and Emulation Buffer Module
Operator's Manuals
ICE-85B Software
Multi-ICE Software
Contains software that supports 85/85
Emulators, 85/49 Emulators and 85/41A
Emulators
Environmental Characteristics
Operating Temperature: 0° to 40°C
Up to 95% relative
Operating Humidity:
humidity without
condensation.
,-----
r--~.::....-...,~~
I
CHIP DATA I
TRACE DATA
I
I,
TIME CLOCI<
CONTROL
I
ADDRESS
,I
,
"
SVNCO
J
TO USER'S
SOCKET
L _________________ _ t~~I=======!::=;;;;~:::!-----~SVNCl
L ____________________
FORCE TRACE
_~
ICE
as TRACE
BOARD
~
BOBS CHIP CONTROLLER
r--------- -,
I
SIGNAL BUFFERS
K===J ~~~~~~
IL __________ -II
18 EXTERNAL TRACE BUFFER
ICE-85BTM BLOCK DIAGRAM
15-35
TRACE
ICE-85BTM IN-CIRCUIT EMULATOR
Ordering Information
Part Number
Description
MDS'-85S-ICE
8085 CPU In-Circuit Emulator,
18-Channel External Trace
Module and Multi-ICE
software
M DS' -85U-1 CE
Upgrade kit to convert ICE-85
or ICE-85A to ICE-85S
functionality. Consists of
Multi-ICE software and 5MHz
Hardware
"'MDS" is an ordering code only, and is not used as a product
name or trademark. MDS'" is a registered trademark of Mohawk
Data Sciences Corp.
15-36
15-37
iAPX 86/88 Support
Options
16
iAPX 86,88
SOFTWARE DEVELOPMENT PACKAGES
FOR SERIES II
• CONV 86/88 Converter for Conversion
of 8080/8085 Assembly Language
Source Code to iAPX 86; 88 Assembly
Language Source Code
• OH 86/88 Object-to"Hexadecimal
Converter
• LIB 86/88 Library Manager
• PL!M 86/88 High Level Programming
Language
.
• ASM 86/88 Macro Assembler for
iAPX 86,88 Assembly Language
Programming
• LINK 86/88 and LOC 86/88 Linkage and
Relocation Utilities
The iAPX 86,88 Software Development Packages for Series II provide a set of software development tools for
the iAPX 86/10 and iAPX 88/10 CPUs and the iSBC 86/12A single board computer. The packages operate under
the ISIS-II operating system on Intellec Microcomputer Development Systems-Model 800 or Series II-thus
minimizing requirements for additional hardware ortraining for Intel Microcomputer Development System
users.
These packages permit 8080/8085 users to efficiently upgrade existing programs into iAPX 86/10 and 88/10
code from either 8080/8085 assembly language source code or PUM80source code.
.
For the new Intel Microcomputer Development System user, the packages operating on an Intellec Series II,
such as a Model 235, provide total iAPX 86,88 software development capability.
.
.
The following are trademarks of Intel Corporation and may be used only 10 identify Intel prOducts: i, Intel, INTEL, INTELLEC"MCS, jm, leS, ICE, UPI, exp, iSSe, iSBX,' INSITE; iRMX,
CREDIT, RMXJ80, p.Scope. Multibus, PROMPT. Promware, Megachassis, Library Manager. MAIN MULTI MODULE, and the combination of MeS, ICE. ssc, AMX or ieS and a numerical
suffix: e.g., iSeG-aO.
APRIL 1981
© INTEL· CORPORATION. 1981.
16-1
9800757·04
inter
iAPX 86,88 SOFTWARE DEVELOPMENT PACKAGES FOR SERIES II
PL/M 86/88 COMPILER
FOR SERIES II
• Language is Upward Compatible from
PL/M 80, Assuring MCS-80/85™ Design
Portability
• Supports 16-bit Signed Integer and
32-bit Floating Point Arithmetic in
Accordance with IEEE Proposed
Standard
• Produces Relocatable Object Code
Which is Linkable to All Other 8086
Object Modules
• Easy-to-Learn, Block-Structured
Language Encourages Program
Modularity
• Code Optimization Assures Efficient
Code Generation and Minimum
Application Memory Utilization
• Supports Full Extended Addressing
Features of the iAPX 86/10 and 88/10
Microprocessors (Up to 1 Mbyte)
Like its counterpart for MCS-80/85 program development, PUM 86/88 is an advanced, structured high-level
programming language. The PUM 86/88 compiler was created specifically for performing software development for the Intel iAPX 86,88 Microprocessors.
'
PUM 86/88 has significant new capabilities over PUM 80 that take advantage of the new facilities provided by
the iAPX 86,88 microsystem, yet the PUM 86/88 language remains compatible with PUM 80.
'
With the exception of hardware,dependent modules, such as interrupt handlers, PUM 80 applications may be
recompiled with PUM 86/88 with little need for modification. PUM 86/88, like PUM 80, is easy to learn,
facilitates rapid program development, and reduces program maintenance costs.
PUM is a powerful, structured, high-level system implementation language in which program statements can
naturally express the program algorithm. This frees the programmer to concentrate on the logic of the
program without concern for burdensome details of machine or assembly language programming (such as,
register allocation, meanings of assembler mnemonics, etc.).
The PUM 86/88 compiler efficiently converts free-form PUM language statements into equivalent 86/10 or
88/10 machine instructions. Substantially fewer PUM statements are necessary for a given application than if
it were programmed at the assembly language or machine code level.
The use of PUM high-level language for system programming, instead of assembly language, results in a high
degree of engineering productivity during project development. This translates into significant reductions in
initial software development and follow-on maintenance costs for the user.
FEATURES
structure allows the use of REENTRANT which is
especially useful in system design.
Major features of the Intel PUM 86/88 compiler and
programming language include:
Language Compatibility
PUM 86/88 object modules are compatible with object modules generated by all other 86/88 translators. This means that PUM programs may be
linked to programs written in any other 86/88
languages.
Block Structure
PUM source code is developed in a series of modules, procedures, and blocks. Encouraging program
modularity in this manner makes programs more
readable, and easier to maintain and debug. The
language becomes more flexible by clearly defining
the scope of user variables (local to a private procedure, global to a public module, for example).
Object modules are compatible with ICE-88 and
ICE-86 units; DEBUG compiler control provides the
In-Circuit Emulators with symbolic debugging
capabilities.
PUM 86/88 Language is upward-compatible with
PUM 80, so that application programs may be easily
ported to run on the iAPX 86 or 88.
The use of procedures to break down a large problem is paramount to productive software development. The PUM 86/88 implementation of a block
16-2
AFN-01239C
intel'
iAPX 86, 88 SOFTWARE DEVELOPMENT PACKAGES FORSERIES II
Supports Five Data Types
Interrupt Handling
PL/M makes use of five data types for various applications. These data types range from one to four
bytes, and facilitate various arithmetic, logic, and
addressing functions:
PL/M has the facility for generating interrupts to
the iAPX 86 or 88 via software. A procedure may be
defined with the INTERRUPT attribute, and the
compiler will automatically initialize an interrupt
vector at the appropriate memory location. The
compiler will also generate code to same and restore the processor status, for execution of the
user-defined interrupt handler routine. The procedure SET$INTERRUPT, the function retuning
an INTERRUPT$PTR, and the PLIM statement
CAUSE$INTERRUPT all add flexibility to user programs involving interrupt handling.
-Byte:
-Word:
-Integer:
-Real:
-Pointer:
8-bit unsigned number
16-bit unsigned number
16-bit signed number
32-bit floating point number
16-bit or 32-bit memory address
indicator
Another powerful facility allows the use of BASED
variables that map more than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.
Segmentation Control
The PLIM 86/88 compiler takes full advantage of
program addressing with the SMALL, COMPACT,
MEDIUM, and LARGE segmentation controls. Programs with less than 64KB total code space can
exploit the most efficient memory addressing
schemes, which lowers total memory requirements.
Larger programs can exploit the flexibility of extended one-megabyte addressing.
Two Data Structuring Facilities
In addition to the five data types and based variables,
PL/M supports two data structuring facilities. These
add flexibility to the referencing of data stored in
large groups.
-Array:
-Structure:
Code Optimization
The PL/M 86/88 compiler offers four levels of optimization for significantly reducing overall program
size.
Indexed list of same type data
elements
Named collection of same or different type data elements
-Combinations
of Each:
Arrays of structures
structures of arrays
-Combination or "folding" of constant expressions; and short-circuit evaluation of Boolean expressions.
-"Strength reductions" (such as a shift left rather
than multiply by 2); and elimination of common
SUb-expressions within the same block.
-Machine code optimizations; elimination of
superfluous branches; re-use of duplicate code;
removal of unreadable code.
-Byte comparisons (rather than 20-bit address calculations) for pointer variables; optimization of
based-variable operations.
or
8087 Numerics Support
PL/M programs that use 32-bit REAL data may be
executed using the Numeric Data Processor for improved performance. All floating-point operations
supported by PL/M may be executed on the 8087
NDP, or the 8087 Emulator (a software module)
provided with the package. Determination of use of
the chip or emulator takes place at link-time, allowing compilations to be run-time independent.
Compiler Controls
Built-In String Handling Facilities
The PLIM 86/88 compiler offers more than 25 controls that facilitate such features as:
The PL/M 86/88 language contains built-in functions
for string manipulaiton. These byte and word functionsperform the following operations on character
strings: MOVE, COMPARE, TRANSLATE, SEARCH,
SKIP, and SET.
-Conditional compilation
-Intra- and Inter-module cross reference
-Corresponding assembly language code in the
listing file
-Setting overflow conditions for run-time handling
16-3
AFN·01239C
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iAPX 86, 88 SOFTWARE DEVELOPMENTPACI(AGES FOR SERIES II
BENEFITS
PLIM 86/88 is designed to be an efficient, costeffective solution to the special',requirements of
iAPX 86 or 88 Microsystern Software Development,
as illustrated by the following benefits of PLIM lJse:,
because less programming resources are required.
for a given programmed function.
Increased Reliability
PLIM 86/88 is designed to aid in the development of
reliable software (PLIM 86/88 programs are simple
statements of the program algorithm). This substantially reduces the risk 0.1 costly correction of errors in
systems that ,have ah'eady reached full production
status, as the more simply stated the program is, the
more likely it is to perform its intended function.
Low Learning Effort
PLIM 86/88 is easy to learn and to use, even for the
novice programmer.
Earlier Project Completion
Critical projects are completed much earlier than
otherwise possible because'PL/M 86/88, a
structured high-level language, increases pro,grammer productivity.
Easier Enhancements and Maintenance
Programs written in PLIM tend to be selfdocumenting, thus easier to read and understand.
This means it is easier to enhance and maintain
PLIM programs as the system capabilities expand
' ,
and future products are developed.
Lower Development Cost"
Increases in programmer productivity translate'immediately into lower software development costs
iAPX 86,88 MACRO ASSEMBLER
FOR SERIES II
• Powerful and Flexible Text Macro
Facility with Three Macro Listing
Options to Aid Debugging
,
• High-Level Data Structuring FacUities
Such as "STRUCTUREs" and
"RECORDs"
• Highly Mnemonic and Compact
Language, Most Mnemonics Represent
Several Distinct Machine Instructions
• Over 120 Detailed and Fully Documented Error Messages
• "Strongly Typed" Assembler Helps
Detect Errors at Assembly Time
• Produces Relocatable and Linkable
Object Code
ASM 86/88 is the "high-level" macro assembler for the iAPX 86,88 assembly language. ASM 86/88translates
symbolic 86/10, 88/10 assembly language mnemonics into 86/10, 88/10 relocatable object code.
ASM 86/88 should be used where maximum code efficiency and hardware control is needed. The iAPX 86,88
assembly language includes approximately 100 instruction mnemonics. From these few mnemonics the
assembler can generate over 3,800 distinct machine instructions. Therefore, the software development task is
simplified, as the programmer need know only 190 mnemonics to generate all possible 86/10,88/10 machine
instructions. ASM 86/88 will generate the shortest machine instruction possible given no forward referencing
or given explicit information as to' the characteristics of forward referenced symbols.
'
ASM 86/88 offers many features normally Jound only in high-level languages. The iAPX.86,88 assembly
language is strongly typed. The assembler performs extensive checks.on the usage of variables and labels.
The assembler uses the attributes which are derived explicitly when a variable or label is first defined, then
makes sure that each use of the symbol in,later instructions conforms to the usage defined for that symbol.
This means that many programming errors will be detected when the program is assembled, long before it is
being debugged on hardware.
16-4
AFN-01239C
inter
iAPX 86, 88 SOFTWARE DEVELOPMENT PACKAGES FOR SERIES II
FEATURES
Over 120 Detailed Error Messages
Major features of the Intel iAPX 86,88 assembler and
assembly language include:
-
Powerful and Flexible Text Macro Facility
-
-
Macro calls may appear anywhere
Allows user to define the syntax of each macro
Built-in functions
conditional assembly (IF-THEN-ELSE, WHILE)
repetition (REPEAT)
string processing functions (MATCH)
support of assembly time I/O to console (IN, OUT)
Three Macro. Listing Options include a GEN
mode which provides a complete. trace of all
macro calls and expansions
Support for ICE-86™ Emulation and
Symbolic Debugging
-
-
Debug options for inclusion of symbol table in
object modules for In-Circuit Emulation with
symbolic debugging.
Generates Relocatable and Linkable
Object Code-Fully Compatible with
LINK 86/88, LOC 86/88 and LIB 86/88
High-Level Data Structuring Capability
-
Appear both in regular list file and error print file.
User documentation fully explains the occurrence of each error and suggests a method to
correct it.
STRUCTURES: Defined to be a template and
then used to allocate storage. The familiar dot
notation may be used to form instruction
ac:ldresses with structure fields.
ARRAYS: Indexed list of same type data elements.
RECORDS: Allows bit-templates to be defined
and used as instruction operands and/or to allocate storage.
-
Permits ASM 86/88 programs to be developed
and debugged in small modules. These modules
can be easily linked with other ASM 86/88 or
PL/M 86/88 object modules and/or library
routines to form a complete application system.
Fully Supports iAPX 86,88
Addressing Modes
-
-
BENEFITS
Provides for complex address expressions involving base and indexing registers and
(structure) field offsets.
Powerful EQU· facility allows complicated expressions to be named and the name can be used
as a synonym for the expression throughout the
module.
The iAPX 86,88 macro assembler allows the extensive capabilities of the 86/10 and 88/10 CPU's to be
fully exploited. In any application, time and space
critical routines can be effectively written in ASM
86/88. The 86,88 assembler outputs relocatable and
linkable object modules. These object modules may
be easily combined with object modules written in
PLIM 86/88-lntel's structured, high-level programming language. ASM 86/88 compliments PLIM
86/88 as the programmer may choose to write each
module in the language most appropriate to the task
and then combine the modules into the complete
applications program using the iAPX 86,88 relocation and linkage utilities.
Powerful STRING MANIPULATION
INSTRUCTIONS
-
Permit direct transfers to.or from memory or the
accumulator.
Can be prefixed with a repeat operator for repetitive execution with a count-down and a condition test.
16-5
AFN·01239C
inter
iAPX 86, 88 SOFTWARE DEVELOPMENT PACKAGES FORSERIES II
CONV 86/88
MCS-80/85™ to iAPX 86,88 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
• Translates 8080/8085 Assembly
Language Source Code to iAPX 86,88
Assembly Language Source Code
• Provides a Fast and Accurate Means
to Convert 8080/8085 Programs to the
iAPX 86/10 and the 88/10, FaCilitating
.
Program Portability
• Automatically Generates Proper ASM
86/88 Directives to Set Up a "Virtual
8080" Environment .that is Compatible
with PL/M 86/88
In support of Intel's commitment to software portability, CONV 86/88 is offered as a tool to move 8080/8085
programs to the iAPX 86/10 and the 88/1 O. A comprehensive manual, "MCS-86 Assembly Language COnll!!rter
Operating Instructions for ISIS-II Users" (9800642), covers the entire conversion process. Detailed methodology of the conversion process is fully described therein. .
.
.
.
-
CONY 86/88 will accept as input an error-free
8080/8085 assembly-language source file and
optional controls, and produce as output, optional PRINT and OUTPUT files.
.
-
The PRINT file is a formatted copy of the 8080/
8085 source and the 86/10 and 88/10 source file
with embedded caution messages.
Because CONY 86/88 is a transliteration process,
there is the possibility·of as much asa 15%-20%
code expansion over the 8080/8085 code. For compactness and efficiency it is recommended that critical portions of programs be re-coded in iAPX 86,88
assembly language.
Also, as a consequence of the transliteration,some
manual editing may be rl;lquired for converting i,,~
structiorisequences dependent on:.·
...
-
The OUTPUT file is an 86/10 and 88/1 0 source file.
-
CONY 86/88 issues. a caution message when it
detects a potential problem in the converted
86/10, 88/10 code.
-instruction length, timing, or encoding
'-interrupt ·processing'
-PL/M parameter passing conventions'
-
A transliteration of the.8080/8085 programs oc"
curs, with each 8080/8085 conl\truct mapped to
its exact 86/10, 88/10 counterpart:
'Mechanical editing procedures for these
gested in the converter manual.
Registers
Condition flags
Instruction
Operands
Assembler directives
Assembler control lines
Macros
The accompanying figure illustrates the flow of the
conversion process. Initially, the abstract program
may be represented in 8080/8085 or iAPX 86,88 assembly language to execute on that respective
target machine. The conversion process is porting a
source destined for the 8080/8085 to the 86/1 0 or the
88/10 via CONY 86/88.
16-6
aie sug..
AFN-01239C
intel·
iAPX 86,- 88 SOFTWARE DEVELOPMENT PACKAGES FOR SERIES II
ABSTRACT PROGRAM
SOURCE CODE
IN BOBO/BOBS
ASSEMBLY LANG
SOURCE CODE
IN B6/10. BB/l0
ASSEMBLY LANG
ALGORITHM
Q'~
FOR
ASSEMBLE
FOR
86/1D,88110
CONV B6/BB
8080/8085
EXECUTE.
ON
BOBOiBOBS
---------------------
EaUIVALENT
FUNCTION
-----------------------
EXECUTE
ON
B6/10. BB/l0
Figure 1. Porting 8080/8085 Source Code·to the iAPX 86/10 and 88/10
. LINK 86/88
• Automatic Combination of Separately
Compiled or Assembled iAPX 86, 88
Programs Into a Relocatable Module
• Automatic Generation of a Summary
Map Giving Results of the LINK 86/88
Process
• Automatic Selection of Required
Modules from Specified Libraries to
Satisfy Symbolic References
• Abbreviated Control Syntax
• Relocatable Modules maybe Merged
into a Single Module Suitable for
Inclusion in a Library
• Extensive Debug Symbol
Manipulation, Aliowing·Line Numbers,
Local Symbols, and Public Symbols to
be Purged and ListedSelec~ively
• Supports "Incremental" Linking
• Supports Type Checking of Public and
External Symbols
LINK 86/88 combines object modules specified in the LINK 86/88 input list into a single output module. LINK
86/88 combines segments from the input modules according to the order in which the modules are·listed.
LINK 86/88 will accept libraries and object modules built from PUM 86/88, ASM 86/88, or any other translator
generating Intel's iAPX 86/10 Relocatable Object Modules.
Support for incremental linking is provided since an output module produced by LINK 86/88 can be an input to
another link. At each stage in the incremental linking process, unneeded public symbols may be purged.
LINK 86/88 supports type checking of PUBLIC and EXTERNAL symbols reporting arierrorif their types are not
consistent.
LINK 86/88 will link any valid set of input modules without any controls. However, controls are available to control the output of diagnostic information in the LINK 86/88 process and to control the content of the output
module.
LINK 86/88 allows the user to create a large program as tlie combination of several smaller, separately compiled modules. After development and debugging of these component modules the user can link them
together, la·cala them using LOC 86/88 and enter final testing with much ofthe work accomplished.
16-7
AFN·Ol239C
inter
iAPX 86, 88 SOFTWARE DEVELOPMENT PACKAGES FOR SERIES II
LIB 86/88
• Libraries Can be Used as Input to
LINK 86/88 Which Will Automatically
Link Modules from the Library that
Satisfy External References in the
Modules Being Linked
• LIB 86/88 is a Library Manager
Program which Allows You to:
Create Specially Formatted Files to
Contain Libraries of Object Modules
Maintain These Libraries by Adding or
Deleting lIIIodules
Print a Listing of the Modules and
Public Symbols in a Library File
• Abbreviated Control Syntax
Libraries aid in the job of building programs. The library manager program LIB 86/88 creates and maintains
files containing object modules. The operation of LIB 86/88 is controlled by commands to indicate which operation LIB 86/88 is to perform. The commands are:.
CREATE:
ADD:
DELETE:
LIST:
EXIT:
creates an empty library file
adds object modules to a library file,
deletes modules from a library file
lists the module directory of library files
terminates the LIB 86 program and returns control to ISIS-II
When using object libraries, the linker will call only those object modules that are required to satisfy external
references, thus saving memory space.
..L.OC 86/88'•
. -.1.:'::
• Automatic Generation of a Summary
Map Giving Starting Address, Segment
Addresses and Lengths, and Debug
• Automatic and Independent·
Relocation of Sfi!gments; Segments
May Be RelQcated to Best. Match
Users Memory Configuration
Symbols and their Ad.dresses
• Extensive Capability to Manipulate the
Order and Placement of Segm~nts in
iAPX 86/10, 88/10 Memory .. ....:•.
• Abbreviated Control Syntax
• Extensive Debug Symbol
Manipu.l~tion,Allowlng I,.lneNumbers,
Local Symbols, and Public Symbols to
be Purged and Listed Selectively
Relocatability allolivs the programmer to code programs or sections of programs without having to know the
final arrangement of the object code in memory.
LOC 86/88 converts relative addresses in an input module to absolute addresses. LOC 86/88 orders the segments in the input module and assigns absolute addresses to the segments. The sequence in which ,the segments in the input module are assigned absolute addresses is determined by their order in the input module
.and the controls supplied with the c.ommand..:.
LOC 86/88 will relocate any valid input module without any controls. However, controls are available to control
the.output of diagnostic information in the LOC 86/88 process, to control the content of the output module,or
both.'
.
'.
....
.. '
The program you are developing will almost certainly use some mix of random access memory (RAM), readonly memory, (ROM), and/or p.rograr:nmable read-~)r)ly memory (P~OM). Therefore"theJocationof your .pro~
gram affects both cost and performanceinyour app.l.ica~ion. The relocati.on feature allows you to develop YQur
program on thelntellec development system and then simply relocatl:j the object code to suit your application.
16-8
AFN-GI239C
inter
iAPX 86, 88 SOFTWARE DEVELOPMENT PACKAGES FOR SERIES II
OH 86/88
• Converts an Absolute Module to a
More Readable Format that can be
Displayed on a CRT or Printed for
Debugging
• Converts an iAPX 86/10, 88/10 Absolute
Object Module to Symbolic
Hexadecimal Format
• Facilitates Preparing a File for Later
Loading by a Symbolic Hexadecimal
Loader, such as the iSBC™ Monitor·
SDK-86 Loader, or Universal PROM
Mapper
The OH 86/88 command converts an 86/10, 88/10 absolute object module to the hexadecimal format. This
conversion may be necessary to format a module for later loading by a hexadecimal loader such as the iSBC
86/12 monitor or Universal Prom Mapper., The conversion may also be made to put the module in a more
readable format that can be displayed or printed.
The module to be converted must be in absolute format; the output from LOC 86/88 is in absolute format.
Figure 2. iAPX 86,88 Software Development Cycle
16·9
AFN·01239C
inter
iAPX 86,88 SOFTWARE' DEVELOPMENT PACKAGES FOR SERIES II
SPECIFICATIONS
Operating Environment
Documentation
PL/M~86
REQUIRED HARDWARE
InteliecCll>·Microcomputer Development System'
- Model 800
- Series II
Programming Manual (9800466)
ISIS-1/ PL/M-86 Compiler Operator's Manual
(9800478)
MCS~86,User's
Manual (9800722)
64K Bytes of RAM Memory
MCS-86 Software DeveloPment Utilities Operating
InstructionsJor ISIS-1/ Users (9800639)
Dual Diskette Drives
- Single or Double-Density
MCS-86 Macro Assembly Language Reference'
Manual (9800640)
System Console
- CRT or Hardcopy Interactive Device
MCS-86 Macro Assembler Operating Instructions
for ISIS-1/ Users (9800641)
.. MCS-86 Assembly Language Converter Operating
Instructions for ISIS-1/ Users (9800642)
.) .
OPTIONAL HARDWARE
Universal PROM Programmer
ICE-86™ Emulator
Universal PROM Programmer User's Manual
(9800819A)
.
,
REQUIRED SOFTWARE
Shipping Media
ISIS-II Diskette Operating System
-
ORDERING INFORMATION
The PUM Compiler, Assembler, and Utilities Package is also available in the following development
support packages:
iAPX 86,88 Software D~v~lopment
Packages for Series II:
Part No.
Description
'
.
. .
_.
MDS-308*
Assembler and Utilities
Package '
Single- and Double-Density Diskettes
SP86A-KIT
Includes ICE-86™ In-Circuit
Emulator (MDS-86 ICE) and
iAPX 86,88 Software Develppment .Package (MDS~311)
SP86B-KIT
MDS-309*
MDS-311"
SP86A Support Package (for
Intelleclll> Model 800)
PL/M compiler and Utilities
Package
SP86B Support Package (for
Series II)
Includes ICE-86™ In-Circuit
Emulator (MDS-a6-ICE),
iAPX 86,88 Software Development Package (MDS/311),
and Series II Expansion
Chassis (MDS-201)
PUM compiler, Assembler,
and Utilities Package
All Packages and Kits Require Software Licenses
"MDS is an ordering code only and is not used as a product name or trademark. MDSCII> is a registered trademark of Mohawk Data SCiences Corporation.
16-10
AFN-Q1239C
iAPX 286
EVALUATION PACKAGE
• Provides elementary program
development and debug capability for
the iAPX 286 microprocessor:
Assembly
System/task build
Symbolic debug
• Provides a programmatic
understanding of the iAPX 286
architecture:
Instruction set
Memory protection
Segmentation
Program timing
• Easy evaluation of all microprocessor
dependencies: architecture, execution
speed, program benchmarks
• Includes an iAPX 286 demonstration
program that exploits and illustrates
architectural features of the 286
The Intel iAPX 286 Evaluation Package is an integrated set of software tools that aids the programmer in
understanding how to use the· iAPX 286 microprocessor. The package runs on a Series III Microcomputer
Development System.
The Evaluation Package will allow a programmer to create, build, execute, and debug an assembly-level iAPX
286 task. It will also show how a programmer can take advantage of iAPX 286 architecture features.
The software tools contained in the package are a macro assembler, a task builder, run-time support procedures, an iAPX 286 simulator, and a demonstration program. The simulator has a built-in timer for benchmarking code sequences and programs. It also provides symbolic debugging capability, in addition to iAPX 286
program execution.
The benefits of using the iAPX 286 Evaluation Package are two-fold. System designers may now learn the iAPX
286 architecture (and determine its applicability) in the quickest manner possible. In addition, software may be
developed now for a future 286 application, thereby getting a head start on a very time-consuming phase of
design.
~I1UN
ACCESS
_:F!: SM286E
SERIES III
LIMIT
BASE ADDRESS
iAPX 286 Evaluation Package Simulator, Vl.e
? LOAD DM286E
"the demo program
Program Size'" Hl432
Total Memory = 6111128
? GO
Interrupt 3 at 0118:0D72
?
? TH ·contents of the task register
0250
• RPL."''''
.11"'''
.INDEX=[l0411
?
? TSS
,..-
7
•
0
0
E
A 8
0
0
0
5 C
·current task state segment
LINK=00'Hl SPO".,0"" 550"026" SPl=iHHHl SSl=.1l39 SP2=000fl 552=0142 IP=[lD73
n=C21J4 AX=0004 CX=0021 OX""""" BX=06B4 SP=FFAfl BP=FFM SI=003F DI=FFB5
ES="261l CS=0118 55=01260 D5""118 RLDT=[H1l8
?
? GO
Interrupt 13 at 1l118:0P73 General Protection Ecode = 000"
?
? LDT
LDT (1T) DSEG BASE=IHlO430 L1"111=0107 P"'l OPL=1l EO-=O W=l A=O SR=OOOO
LOT (2T) OSEG BASE=iH1E100 LIMIT"e005 P=l OPL=3 ED"'O W"'l A=l SR=0flOO
~63
? GOT (HIT) -the 10th global descriptor table entry
GOT (l(J1) TSS BASE=IH1EA80 LIMlT"'(Hl5C 8"'0 P"l DPL"'O SR=0058
48
I
? EXIT
Sample Simulator Session
16
40
16-BIT SELECTOR
I
O~
GOT (10T)
Segment Descriptor Table
The following are trademarks of Intel Corporation and may be used only to identify Intel products: BXp, CREDIT, i, ICE, lCS, 1m , Insite, Intel, intel, Intelevision, lnteUee, iRMX, iSBC, iSBX,
Library Manager, MCS, Megaehassis, Mleromap, Multibus, Multimodule, PROMPT, Promware, RMXJ80, System 2000, UPI, J,tScope, and the combination of ICE, iCS, iRMX, iSBC, iSBX,
SEPTEMBER 1981
MCS, or RMX and a numerical suffix.
© Inlel Corporation, 1981.
AFN'()2052A
16-11
inter
iAPX 286 EVALUATION PACKAGE
FUNCTIONAL DESCRIPTION
iAPX 286 Evaluation Macro Assembler
The Evaluation Assembler (AS286E) accepts a
source module written in the 286 Macro Assembly
Language, and generates an object module and a
listing file. The assembler is based upon ASM-86, and
therefore performs type-checking on operands, supports complex data structures, and utilizes the same
macro processor.
iAPX 286 Evaluation Builder
The Evaluation Builder (BD286E) accepts a single
assembler object module, and generates a'singletasking executable load module. The Evaluation
Builder performs the following functions:
-Assigns attribu'tes to 286 segments: Privilege
level,Access Rights, Base Address, Segment
Length.
-Creates descriptor table entries (GOT & LOT)
from segments.
-Initializes Segment Registers.
-Allows call gates, interrupt gates, and trap gates
, to be explicitly created, via the Interrupt
Descriptor Table.
'
-Automatically creates call gates for X286E runtime procedures.
-Creates the Task State Segment for a one-task
program.
-Produces a map showing all segments, gates,
and public symbols.
-Binds segments to absolute addresses.
The Simulator has a built-in instruction timer to aid in
benchmarkingiAPX 286 programs. Another timer,
which also counts clock cycles, can be used to
generate interrupts at specific time ,intervals.
Run-Time Support Procedures
The Evaluation Package contains a set of run-time
procedures (X286E) that may be "linked" to a user
program at build-time to perform several software
functions. These functions include creating llnd
modifying segments, descriptors, and tables, creating new tasks, and dynamically allocating free
memory for segments~
The Demonstration Program
The Demo Program(DM286E)is an application package that uses the Evaluation Tools (AS286E, BD286E,
SM286E, X286E) to teach users how to program the
iAPX 286. '
"
'
It not only guides a programmer through the ,use, of
these tools, but the demo program itself illustrates
how software can exploit the architecture of the 286.
The following features are illustrated:
-Memory Protection using object descriptors.
"-Gate creation and manipulation.
'---:Task switching, procedure entry and exit. '
-Interrupt handling.
-Dynamic task creation.
-Inter-task communication.
iAPX 286 Evaluation Simulator
The Evaluation Simulator (SM286E) loads and executes a 286 object module created by the Builder.
Program execution functionally duplicates iAPX 286
processor operation; data protection, gates, processor traps and interrupts, and segmentation acce~s
are all supported in the same way as the iAPX 286.
Compatibility mode and numerics are not included.
The symbolic debugger portion of the simulator supports two simultaneous code break-points and
single-step execution, as well as modification of
variables, registers, descriptor tables, and the task
state segment. Code disassembly is also provided.
16-12
The demonstration consists of a nucleus, a real-time
clock interface, a time-of-day clock, a CPU-utilization
spy, and a command interpreter. The user may execute these simultaneously on the simulator, and gain
an understanding of how the 286 handles the functions listed above.
ORDERING INFORMATION
Product Code
Description
MDS-322
iAPX 286 Evaluation Package
(Requires Software License)
PL/M 86/88 SOFTWARE PACKAGE
•
Language Is Upward Compatible from
PL/M 80, Assuring MCS-80/8S Design
Portability
Improved Compiler Performance Now
Supports More User Symbols and
Faster Compilation Speeds
•
•
Supports 16-Bit Signed Integer and
32-Bit Floating Point Arithmetic in
Accordance with IEEE Proposed
Standard
Produces Relocatable Object Code
Which Is Linkable to All Other 8086
Object Modules
•
Code Optimization Assures Efficient
Code Generation and Minimum
Application Memory Utilization
•
Easy-To-Learn Block-Structured
Language Encourages Program
Modularity
•
Built-In Syntax Checker Doubles
Performance for Compiling Programs
Containing Errors
•
Executes on Series III iAPX 86
Processor for Fastest Compilations
•
Like its counterpart for MCS-80/85 program development, PUM 86/88 is an advanced, structured high-level
programming language. The PUM 86/88 compiler was created specifically for performing software development for the Intel 8086 and 8088 Microprocessors.
PUM is a powerful, structured, high-level system implementation language in which program statements can
naturally express the program algorithm. This frees the programmer to concentrate on the logic of the program without concern for burdensome details of machine or assembly language programming (such as register allocation, meanings of assembler mnemonics, etc.).
The PUM 86/88 compiler efficiently converts free-form PUM language statements into equivalent 8088/8086
machine instructions. Substantially fewer PUM statements are necessary for a given application than if it were
programmed at the assembly language or machine code level.
The use of PUM high-level language for system programming, insfead of assembly language, results in a high
degree of engineering productivity during project development. This translates into significant reductions in
initial software development and follow-on maintenance costs for the user.
NOTE:.The InteJlec' Microcomputer Development System pictured here IS not Included with the PUM 86/88 Software Package but merely depicts a language In liS operating
environment.
The following are trademarks o! Intel Corporation and may be used only t~ Identify Intel products: i, Intel, INTEL. INTELLEC, M~S, ~m, IGS, ICE, UPI, BXP, )SSC, iSBX, INSITE, iRMX,
CREDIT, RMX/80, p:Scope, Multlbu5, PROMPT, Promware, Megachassls, library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE. SSC. AMX or IGS and a numerical
suffix; e.g., iSBC-80.
© Intel Corporation
1980
16-13
September 1980
inter
PL/M 86/88 SOFTWARE PACKAGE
FEATURES
Another powerful facility allows the use of BASED
variables that map more than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.
Major features of the Intel PUM 86/88 compiler and
programming language include:
Block Structure
Two Data. Structuring Facilities
PUM source code is developed in a series of modules, procedures, and blocks. Encouraging program
modularity in this manner makes programs more
readable, and easier to maintain and debug. The
language becomes more flexible, by clearly defining
the scope of user variables (local to a private procedure, global to a public procedure, for example).
In addition to the five data types and based variables,
PUM supports two data structuring facilities. These
add flexibility to the referencing of data stored in
large groups.
-
The use of procedures to break down a large problem is paramount to productive software development. The PUM 86/88 implementation of a block
structure allows the use of REENTRANT (recursive)
procedures, which are especially useful in system
design.
Array: Indexed list of same type data elements
Structure: Named collection of same or different
type data elements
Combinations of Each: Arrays of structures or
structures of arrays
.
8087 Numerics Support
PUM programs that use 32-bitREAL data maybe
executed using the Numeric Data Processor for im c
proved performance. All floating-point operations
supported by PUM may be exec.uted on the iAPX
86/20 or 88/20 NDP,orthe 8087 Emulator (a software
module) provided with the package. Determination
of use of the chip or Emulator takes placeat linktime, .allowing compilations to be rUn-time
independent.
Language Compatibility
PL/M 86/88 object modules are compatible with object modules generated by all other 86/88 translators. This means that PLiM programs may be
linked to programs written in any other 86/88
language.
Built-In String Handling Facilities
Object modules are compatible with ICE-88 and
ICE-86 units; DEBUG compiler control provides the
In-Circuit Emulators with symbolic debugging
capabilities.
The PUM 86/88 language contains built-infunctions
for string manipulation. These byte and word functions perform the following operations on character
. strings: MOVE, COMPARE, TRANSLATE, SEARCH,
SKIP, and SET.
PUM 86/88 Language is upward-compatible with
PL/M 80, so that application programs may be easily
ported to run on the iAPX 86 or 88.
Interrupt Handling
Supports Five Data Types
PL/M makes use of five data types for various applications. These data types range from one to fou r
bytes, and facilitate various arithmetic, logic, and
addressing functions:
-
Byte: 8-bit unsigned number
Word: 16-bit unsigned number
Integer: 16-bit signed number
Real: 32-bit floating point number
Pointer: 16-bit or 32-bit memory address
indicator
16-14
PUM has the facility for generating interrupts to the
iAPX 86 or .88 via software. A procedure may be
defined with the INTERRUPT attribute, and the
compiler will automatically initialize an interrupt
vector at the appropriate memory location. The
compiler will also generate code to same and restore the processor status, for execution of the
user-defined interrupt handler routine. The procedure SET$INTERRUPT, the function retuning
an INTERRUPT$PTR, and the PUM statement
CAUSE$INTERRUPT all add flexibility to user
programs involving interrupt and handling.
AFN-01661A
PL/M 86/88 SOFTWARE PACKAGE
Compiler Controls
-
Including several that have been mentioned, the
PUM 86/88 com piler offers more than 25 controls
that facilitate such features as:
-
-
Conditional compilation
Including additional PUM source files from disk
Intra- and Inter-module cross reference
Corresponding assembly language code in the
listing file
Setting overflow conditions for run-time handling
Segmentation Control
The PUM 86/88 compiler takes full advantage of
program addressing with the SMALL, COMPACT,
MEDIUM, and LARGE segmentation controls. Programs with less than 64KB total code space can
exploit the most efficient memory addressing
schemes, which lowers total memory requirements.
Larger programs can exploit the flexibility of extended one-megabyte addressing.
Code Optimization
The PUM 86/88 compiler offers four levels of optimization for significantly reducing overall program
size.
-
Combination or "folding" of constant expressions; and short-circuit evaluation of Boolean expressions.
-
"Strength reductions" (such as a shift left rather
than multiply by 2); and elimination of common
sub-expressions within the same block.
Machine code optimizations; elimination of
superfluous branches; re-use of duplicate code;
removal of unreadable code.
Byte comparisons (rather than 20-bit address
calculations) for pointer variables; optimization
of based~variable operations.
Error Checking
The PUM 86/88 compiler has a very powerful feature
to speed up compilations. If a syntax or program
error is detected, the compiler will skip the code
generation and optimization passes. This usually
yields a 2X performance increase for compilation of
programs with errors.
A fully detailed set of programming and compilation
errors is provided by the compiler.
Compiler Performance
Performance benchmarks may provide valuable information in estimating compile times for various
programs. It is extremely important to understand,
however, the effect of varying conditions on compiler performance. Storage media, coding style,
program length, and the use of INCLUDE files significantly change the compiler's overall performance.
We tested typical PUM programs of varying lengths.
The results are listed in Table 1.
. Table 1. PL/M Program Compile Times
Program Size
Compile Time(Sec)
Lines/Minute
SMALL (71)
20
213
MEDIUM (610)
54
678
LARGE (1710)
128
802
129
653
LARGE (1403)
(with very dense code,
plus include file)
NOTE: These programs were run on a Series III with ISIS 4.1 and a hard disk. The lines per minute figures reflectfifleen percent blank lines
and comme"nts.
The compiler allows approximately 1000 ten-character user symbols.
16-15
AFN-01661A
PL/M,86/88 ,SOFTWARE: PA'CKAGE
:.,;
M:DO: ,.
..
Beginni~g,qt modu,le
•
..
,
;'.
. . :
.. ,.
/' Parameters:
.'
PTR is pointer tcnirst record.
,COUNT: is nllmb~r.of:record5·to be sorted:.
, :i
~~~I~S~~~i~b~t~~~b~fit?6~~'~iit~~a;~cr~~~~~~~~~ ~~~f~' scalar'
.t:, b~.. I;J~ed ~S; ~ort ~ey' .. '(
,
DECLARE RECORD BASED PTA (1) BYTE,
CURRENT (128) BYTE,
II. J)INTEGER:,. , . i '
SORT:
.!
RECSIZE:KEYINDEX)~
',',' SORTP80C: PROCEDURE (PTR, COUNT,
'" " '" DECLAFl,E"PTR ~OINTER, {COUNT" ,RECSIZE, KEYINDEX) INTEGER.
f.
PUBLIC and EXTERNAL att"r'it:!utes promote
program modlliariiy,
:",.
"Based" Varia.~les allow manipl:/lation of external data by ,
passing the base of the data structure (a pointer): This '
minirriz~s the,STACK space used for parameter passing, and
the execution time to perform many STACK operations.
DO J
1 TO COUNT-l:
CALL MOVBI@RECORDIJ-,RECSIZE),
, RECSIZE):
,"','IJ:
',,":;',"
' ,
,';"'-'-'----<..;.
" ,FIND ...
'-: '
': DO WHILE 1,0'"
'
,
,
,
AND RECQRDIIIJ)"RECSIZE. KEYINDEX)
, , ,CURRENTIKEYINDEX):
CALL MOVB(@RECORDIII "lVRECSIZE),
The "AT' operator ,returns the address of a
variable, instead of its contents. This is very useful
in pa.ssing painters for based variables. '
~:l~~~~I~,RE~SIZE).
I~ I 1:
END FIND:
(@CURRENT. @RECORDII'RECSIZE), RECSIZEi:
'On'e ~h;~v~ral'PUM
manipulaHon,
'
END SORTPROC;
END M:
rEnd of module'/
buil:t'~i~ '~r'OC~dures for st'r'ing
.'
"
:
F,igure1:'sa~pie PLIM 86/88 Program
",',,,.
PUM,8,!li~8is desi,gned~obe ~~~fJi'ciel']t, c.Qstc
effective solution to the sPEl:oialrequ,ireme(Jtsof
iAPX 86 or 88 Microsystem Software Development,
as illustrated by the following benefits of PUM use:
because less programming resources are required
for. a given programmed function.
Increased Reliability
,,' ,,PUM 86/88 is designed to aid in the development of
reliable software (RUM 86/88 programs are simple
PLiM 86/88,i1:! easy, tP.J.ear~ and to us~, ~~en .for th(3
',."statements of the program algorithm), This substannovice program.m,er.
tially reduces the risk of costly correction of errors in,
systems that have already reached full production
status, as the more simply stated the program is, the
Earlier Project Completion
more likely it is to perform its intended function,
Critical projects,are completed much earlier than
otherwise possible because PUM 86/88, a strucEasier Enhancements
tured high-level language, increases programmer
and Maintenance
productivity.
Low Learning Effort
,d.
Lower Development Cost
Increases in programmer productivity translate immediately into lower software development costs
Programs writt~n inPL/M tend to be self,documenting, thus easier to read and understand, This means
, ' .it is easier to enhance"and maintain PL/M programs
" 'as the system ca'pabilities~xpand and future prod~
ucts are developed,
16-1:6
AFN-Ol661A
inter
PL/M 86/88 SOFTWARE PACKAGE
SPECIFICATIONS
REQUIRED SOFTWARE:
ISIS-II Diskette Operating System, V4.1 or later
Series III Operating System
Operating Environment
Documentation Package
REQUIRED HARDWARE:
Intellec® Microcomputer Development System
- Series III or equivalent
Dual Diskette Drives
- ~InQlb- or Double-Density
System Console
- CRT or Hardcopy Interactive Device
PL/M-86 User's Guide for 8086-b!3sed Development
Systems (121636)
OPTIONAL HARDWARE:
Universal PROM Programmer
Line Printer
ICE-86™
ORDERING INFORMATION
Part Number
Description
MDS-313'
PL/M 86/88 Software Package
Requires Software License
'MDS is an ordering code only and is not used as a product name or trademark. MDS" is a registered trademark of Mohawk Data Sciences
Corporation.
16-17
AFN·01661A
PASCAL 86/88
SOFTWARE PACKAGE
• Resident on iAPX 86 Based Intellec®
Series III Microcomputer Development
System for Optimal Performance
• Object Compatible and Linkable with
PL/M 86/88, ASM 86/88 and FORTRAN
86/88
• ICE™ Symbolic Debugging Fully
Supported
• Implements REALMATH for Consistent
and Reliable Results
• Supports iAPX86/20, 88/20 Numeric
Data Processors
• Strict Implementation of ISO Standard
Pascal
• Useful Extensions Essential for
Microcomputer Applications
• Separate Compilation with TypeChecking Enforced Between Pascal
Modules
• Compiler Option to Support Full RunTime Range-Checking
PASCAL 86/88 conforms to and implements the ISO Draft Proposed Pascal standard, The language is
enhanced to support microcomputer applications with special features, such as separate compilation, interrupt handling and direct port I/O. To assist the development of portable software, the compiler can bedirected
to flag all non-standard featu res.
The PASCAL 86/88 compiler runs on the iAPX 86 Resident Intellec® Series III Microcomputer Development
System. A well-defined I/O interface is provided for run-time support. This allows a user-written operating system to support application programs as an alternate to the development system environment. Program modules compiled under PASCAL 86/88 are compatible and linkable with modules written in PL/M 86/88, ASM
86/88 or FORTRAN 86/88. With a complete family of compatible programming languages for the iAPX 86,88
one can implement each module in the language most appropriate to the task at hand.
PASCAL 86/88 object modules contain symbol and type information for program debugging using ICE-86™
emulator. For final production version, the compiler can remove this extra information and code.
Note: The lnte1lee'll: microcomputer development system pictured here is not included with the Pascal 86/68 Software Package but merely depicts the language in its operating
environment.
The following are trademarks of Intel Corporation and may be used only to identity Intel products: BXP, CREDIT, Intellee, Multibus, i, iSBC, Multimodule, ICE, iSBX, PROMPT, iRMX,
iCS, library Manager, Promware, Insite, MeS, RMX, Intel, Megachassis, UPI, Intelevision, Micromap, fLScope and the combination of iCE, iGS. iSBC, isex, MeS, or RMX and a numerical suffix.
© Intel Corporation 1980
121680-001 Rev. A
inter
PASCAL 86/88
FEATURES
Includes all the language features of Jensen & Wirth
Pascal as defined in the ISO Draft Proposed Pascal
Standard.
Supports required extensions for microcomputer
applications.
-Intelr upt "andling
Supports numerous compiler options to control the
compilation process, to INCLUDE files, flag nonstandard Pascal statements and others to control
program listings and object modules.
Utilizes the IEEE standard for Floating-Point Arithmetic (the Intel REALMATH standard) for arithmetic
operations.
-Direct port I/O
Separate compilation extensions allow:
-Modular decomposition of large programs
Well-defined and documented run-time operating
system interfaces allow the user to execute the applications under user-designed operating systems.
-Linkage with other Pascal modules as well as
PLIM 86/88, ASM 86/88 and FORTRAN 86/88.
-Enforcement of type-checking at LINK-time
BENEFITS
Provides a standard Pascal for iAPX 86, 88 based
applications.
-Pascal has gained wide acceptance as the portable application language for microcomputer
applications
-It is being taught in many colleges and universities
around the world
-It is easy to learn, originally intended as a vehicle
for teaching computer programming
-Improves maintainability: Type mechanism is
both strictly enforced and user extendable
Provides run-time support for co-processors. All
real-type arithmetic is performed on the 86/20 numeric data processor unit or software emulator.
Run-time library routines, common between Pascal
and other Intel languages (such as FORTRAN), permit efficient and consistently accurate results.
Extended relocation and linkage support allows the
user to link Pascal program modules with routines
written in other languages for certain parts of the
program. For example, real-time or hardware dependent routines written in ASM 86/88 or PL/M 86/88
can be linked to Pascal routines, further extending
the user's ability to write structured and modular
programs.
-Few machine specific language constructs
Strict implementation of the proposed ISO standard
for Pascal aids portability of application programs. A
compile time option checks conformance to the
standard making it easy to write conforming
programs.
PASCAL 86/88 extensions via predefined procedures for interrupt handling and direct port I/O make
it possible to code an entire application in Pascal
without compromising portability.
Standard Intel REALMATH is easy to use and provides reliable results, consistent with other Intel
languages and other implementations of the IEEE
proposed Floating-Point standard.
PASCAL 86/88 programs "talk" to the resident
operating system using Intel's standard interface for
translated programs. This allows users to replace
the development operating system by their own
operating systems in the final application.
PASCAL 86/88 takes full advantage of iAPX 86, 88
high level language architecture to generate
efficient machine code without using timeconsuming optimization algorithms.
Compiler options can be used to control the program listings and object modules. While debugging,
the user may generate additional information such
as the symbol record information required and
useful for debugging using ICE emulation. After debugging, the production version may be streamlined
by removing this additional information.
16-19
AFN·016S2A
PASCAL 86/88
SPECIFICATIONS
REQUIRED SOFTWARE
ISIS-II Diskette Operating System V4.1 or later
Operating Environment
Documentation Package
REQUIRED HARDWARE
Intellec® Series III Microcomputer Development
System
-System Console
-Double Density Dual Diskette Drive OR Hard Disk·
PASCAL 86 User's Guide (121539-001)
Shipping Media
Flexible Diskettes
-Single and Double Density
ORDERING INFORMATION
Part Number
Description
MDS'-314
PASCAL 86/88 Software Package
Requires software license .
• MOS is an ordering code only and is not used as a product name or trademark. MOS" is a registered trademark of Mohawk Data Science.
AFN-Q'6S2A
FORTRAN 86/88
SOFTWARE PACKAGE
• Features high-level language support
for floating-point calculations,
transcendentals, interrupt procedures,
and run-time exception handling
• Meets ANS FORTRAN 77 Subset
Language Specifications
• Supports iAPX 86/20, 88/20 Numeric
Data Processor for fast and efficient
execution of numeric instructions
• Uses REALMATH Floating-Point
Standard for consistent and reliable
results
• Offers powerful extensions tailored to
microprocessor applications
• Offers upward compatibility with
FORTRAN 80
• Provides FORTRAN run-time support for
iAPX 86,88-based design
• Provides users ability to do formatted
and unformatted 1/0 with sequential or
direct access methods
FORTRAN 86/88 meets the ANS FORTRAN 77 Language Subset Specification and includes many features of
the full standard. Therefore, the user is assured of portability of most existing ANS FORTRAN programs and of
full portability from other computer systems with an ANS FORTRAN 77 Compiler.
FORTRAN 86/88 programs developed and debugged on the iAPX 86 Resident Intellec Series III Microcomputer
Development System may be: tested with the prototype using ICE symbolic debugging, and executed on an
RMX-86 operating system, or on a user's iAPX 86,88-based operating system.
FORTRAN 86/88 is one of a complete family of compatible programming languages for iAPX 86,88 development: PLlM, Pascal, FORTRAN, and Assembler. Therefore, users may choose the language best suited for a
specific problem solution.
© Intel Corporation, 1961.
16-21
APRIL 1981
AFN-01653A
intel'
FORTRAN 86/88 SOFTWARE PACKAGE
FEATURES
Intel® Microprocessor Support
Extensive High-Level Language
Numeric Processing Support
FORTRAN 86/88 language features support of iAPX
86/20, 88/20 Numeric Data Processor
Single (32-bit), double (64-bit), and double extended
precision (80-bit) floating-point data types
Compiler generates in-line iAPX 86/20, 88/20 Numeric Data Processor object code for floating-point
arithmetic (See Figu re 1)
REALMATH Proposed IEEE Floating-Point Standard) for consistent and reliable results
Intrinsics allow user to control iAPX 86/20, 88/20
Numeric Data Processor
Full support for all other data types: integer, logical,
character
iAPX 86,88 architectural advantages used for indexing and character-string handling
Ability to use hardware (iAPX 86/20, 88/20 Numeric
Data Processor) or software (simulator) floatingpoint support chosen at link time
Symbolic debugging of application using ICE-86
and ICE-88 emulators
ANS FORTRAN 77 Standard
FLOATING-POINT-STATMENT
TEMPER = (PRESS - VOLUM I QUEK) - 3.~5 I (PRESS - VOLUM I QUEK)
- (PRESS - VOLUM I QUEK) * (PRESS - VOLUM I QUEK)
&
OBJECT CODE GENERATED
Intel FORTRAN-86 Compiler
IAPX 86/20, 88/20
MACHINE CODE
0013
0018
0010
0022
0025
0026
002E
0031
0034
0037
003A
0030
0040
0045
9909060COO
9908360000
99082E080a
960001
962E083EOOOO
9609C9
960002
960EE9
9609C1
9808C8
9800C2
960EE1
98D91E0400
98
ASSEMBLER MNEMONICS
FLJ
POlV
FSUBo<
F ST
FDlVo<
FXCHG
PST
FSU8RP
FLO
FMUL
FFREE
FSU9P
FSTP
WAIT
I.,
STATEMENT
It
2
VOLUM
QUEK
PRESS
T~S+1H
CS:@CONST
TOS+1H
TOS+2H
T:JS+1 H
TOS
TDS+2H
TEMPER
Figure 1. Object Code Generated by FORTRAN 86/88 for a Floating-Point Calculation Using iAPX 86/20,
88/20 Numeric Processor
16-22
AFN.()1653A
FORTRAN 86/88 SOFTWARE PACKAGE
Microprocessor Application Support
Early Project Completion
-Direct byte- or word-oriented port I/O
FORTRAN is an industry-standard, high-level
numerics processing language. FORTRAN programmerscan use FORTRAN 86/88 on microprocessor projects with little retraining. Existing FORTRAN software can be compiled with FORTRAN
86/88 and programs developed in FORTRAN 86/88
can run on other computers with ANS FORTRAN 77
with little or no change. Libraries of mathematical
programs using ANS 77 standards may be compiled
with FORTRAN 86/88.
-Reentrant procedures
-Interrupt procedures
Flexible Run-Time Support
Application object code may be executed in iAPX 86,
88-based environment of user's choice:
-a Series III Intellec Development System with Series III Operating System
-an iAPX 86,88-based system with iRMX-86 Operating System
Application Object Code
Portability for a Processor Family
-an iAPX 86,88-based system with user-designed
Operating System
Run-time exception handling for fixed-point
merics, floating-point numerics, and I/O errors
FORTRAN 86/88 modules "talk" to the resident Intellec development operating system using Intel's
standard interface for all development-system
software. This allows an application developed on
the Series III operating system to execute on iRMX/
86, or a user-supplied operating system by linking in
the iRMX/86 or other appropriate interface library. A
standard logical-record interface enables communication with non-standard I/O devices.
nu-
Relocatable object libraries for complete run-time
support of I/O and arithmetic functions. In-line code
execution is generated for iAPX 86/20, 88/20 Numeric Data Processor
BENEFITS
Comprehensive, Reliable
and Efficient Numeric Processing
FORTRAN 86/88 provides a means of developing
application software for the Intel iAPX 86,88 products lines in a familiar, widely accepted, and
industry-standard programming language. FORTRAN 86/88 will greatly enhance the user's ability to
provide cost-effective software development for
Intel microprocessors as illustrateq by the
following:
The unique combination of FORTRAN 86/88, iAPX
86/20. 88/20 Numeric Data Processor, and
REALMATH (Proposed IEEE Floating-Point Standard) provide universal consistency in results of
numeric computations and efficient object code
generation.
SPECIFICATIONS
REQUIRED SOFTWARE
ISIS-II Diskette Operating System V4.1 or later
Operating Environment
REQUIRED HARDWARE
Intellec® Series III Microcomputer Development
System
Documentation Package
FORTRAN 86/88 User's Guide (121539-001)
-System Console
-Double-Density Dual-Diskette Drive. A Hard Disk
is recommended
Shipping Media
-Hard Disk"
Flexible Diskettes
"Recommended.
-Single- and Double-Density
16-23
AF~1653A
FORTRAN 86/88 SOFTWARE PACKAGE
ORDERING INFORMATION
Part Number
Description
MDS**-315
FORTRAN 86/88 Software Package
Requires Software License
•• MDS is an ordering code only and is not used as a product name or trademark. MDS'" is a registered trademark of Mohaw.k Data Science.
Printed in USNH-2010481ICBMIBL
16-24
8087
SOFTWARE SUPPORT PACKAGE
• Program Generation for the 8087
Numeric Data Processor on the
Intellec® Microcomputer Development
System
• 8087 Emulator Duplicates Each 8087
Floating-Point Instruction in Software,
for Evaluation of Prototyping, or for
Use in an End Product
• Consists of: 8086/8087/8088 Macro
Assembler, 8087 Software Emulator.
ill Macro Assembler and 8087 Emulator
• Macro Assembler Generates Code for
8087 Processor or Emulator, While
Also Supporting the 8086/8088
Instruction Set
are Fully Compatible with Other
8086/8088 Development Software
• Implementation of the IEEE Proposed
Floating-Point Standard (the Intel®
Realmath Standard)
The 8087 Software Support Package is an optional extention of Intel's 8086/8088 Software Development
Package that runs under ISIS-lion an Intellec or Series II Microcomputer Development System.
The 8087 Software Support Package consists of the 8086/8087/8088 Macro Assembler, and the Full 8087
Emulator. The assembler is a functional superset of the 8086/8088 Macro Assembler, and includes instructions for over sixty new floating-point operations, plus new data types supported by the 8087.
The 8087 Emulator is an 8086/8088 object module that simulates the environment of the 8087, and executes
each floating-point operation using software algorithms. This emulator functionally duplicates the operation
of the 8087 Numeric Data Processor.
Also included in this package are interface libraries to link with 8086/8087/8088 object modules, which are
used for specifying whether the 8087 Processor or the 8087 Emulator is to be used. Thisenables the run-time
environment to be invisible to the programmer at assembly time.
The following are trademarks of Intel Corporation and may be used only to Identify Inlel products: axp, CREDIT, Intellee, Multlbu9, i, ISSC, Multlmodule, ICE, iSaX, PROMPT, iRMX,
ICS, Library Manager. Promware, Insite, MeS, RMX, In lei, Megachassis, UPI, Intelevislon, Mlcromap. ~Scope and the combination of iCE, iCS, iSaC, iSaX, MeS, or RMX and a
numerical suffix.
© Intel Corporation 1980
16.. 25
121653-001 Rev. A
8087 SOFTWARE SUPPORT PACKAGE
floating-point instructions, the macro assembler
also introduces two new 8087 data types: QWORD
(8 bytes) and TBYTE (ten bytes). These support the
highest precision of data processed by the 8087.
FUNCTIONAL DESCRIPTION
8086/8087/8088 Macro Assembler
The 8086/8087/8088 Macro Assembler translates
symbolic macro assembly language instructions
into appropriate machine instructions. It is an extended version of the 8086/8088 Macro Assembler,
and therefore supports all of the same features and
functions, such as limited type checking, conditional assembly, data structures, macros; etc. The
extensions are the new instructions and data types
to support floating-point operations. Realmath
floating-point instructions (see Table 1) generate
code capable of being converted to either 8087 instructions or interrupts' for the 8087 Emuiator. The
Processor/Emulator selection is made via interface
libraries at LINK-time. In addition to the new
Full 8087 Emulator
The Full 8087 Emulator is a 16"kilobyte object module that is linked to the application program for
floating-point operations. Its functionality is identical to the 8087 chip, and is ideal for prbtotyping and
debugging floating-point applications. The
Emulator is an alternative to the use of the 8087 chip,
although the latter executes floating-pointapplications up to 100 times faster than an 8086 with the
8087 Emulator. Furthermore, since the 8087 is a
"co-processor," use of the chipwill allow many operations to be performed in parallel with the 8086.
Table 1. 8087.lnstructions
Processor Control Instructions
Ariihmetic Instructions
Addition
FADD
FADDP
FIADD
Add real
Add real and pop
Integer add
Subtraction .
FSUB
FSUBP
FISUB
FSUBR
FSUBRP
FISUBR
Subtract real
Subtract real and pop
Integer subtract
Subtract real reversed
Subtract real reversed and
pop
Integer su btract reversed
Multiplication
FMUL
FMULP
FIMUL
Multiply real
Multiply real and pop
Integer multiply
FIDIVR
Divide real
Divide real and pop
Integer divide
Divide real reversed
Divide real reversed and
pop
Integer divide reversed
FABS
FCHS
FENI/FNENI
Enable interrupts
Disable interrupts
FLDCW
Load control word
FSTCW/FNSTCW
Store control word
FSTSW/FNSTSW
Store status word
FCLEX/FNCLEX
Clear exceptions
FSTENV/FNSTENV
Store environment
FLDENV
Load environment
FSAVE/FNSAVE
Save state
FRSTOR
Restore state
Increment stack pointer
FDECSTP
Decrement stack pointer
FFREE
Free register
FNOP
No operation
FWAIT
CPU wait
Comparison Instructions
FCOM
Other Operations
FSQRT
FSCALE
FPREM
FRNDINT
FXTRACT
Initialize processor
FINCSTP
Division
FDIV
FDIVP
FIDIV
FDIVR
FDIVRP
FINIT/FNINIT
FDISI/FNDISI
Square root
Scale
Partial remainder
Round to Integer
Extract exponent and
significand
Absolute value
Change sign
i
16-26
Compare real
FCOMP
Compare real and pop
FCOMPP
Com pare real and pop
twice
FICOM
Integer compare
FICOMP
Integer compare and pop
FTST
Test
FXAM
Examine
I,
AFN-01574A
8087 SOFTWARE SUPPORT PACKAGE
Table 1. 8087 Instructions (cont'd)
Data Transfer Instructions
Transcendental Instructions
FPTAN
Partial tangent
FPATAN
Partial arctangent
F2XM1
2'-1
FYL2X
y. 10g,X
y. 10g,(X+ 1)
FYL2XP1
Real Transfers
FLD
FST
FSTP
FXCH
Load real
Store real
Store real and pop
Exchange registers
Integer Transfers
FILD
FIST
FISTP
Constant Instructions
FLDZ
Load +0.0
FLD1
Load +1.0
FLOPI
Load
FLDL2T
Load log,10
FLDL2E
Load log,e
FLDLG2
Load log ,,2
FLDLN2
Load log,2
Integer load
Integer store
Integer store and pop
Packed Decimal Transfers
FBLD
1T
FBSTP
SPECIFICATIONS
Packed decimal (BCD)
load
Packed decimal (BCD)
store and pop
REQUIRED SOFTWARE
ISIS-II Diskette Operating System
-Single or Double Density
Operating Environment
8086/8088 Software Development Package
REQUIRED HARDWARE
Intellec® Microcomputer Development System
-Model 800
-Series II (Models 220, 225 or equivalent)
Documentation Package
8086/8087/8088 Macro Assembly Language Reference Manual for 8080/808S-Based Development
Systems (121623-001)
64K Bytes of RAM Memory
Minimum One Diskette Drive
-Single or Double* Density
8086/8087/8088 Macro Assembler Operating Instructions for 8080/808S-Based Development Systems (121624-001)
System Console
-CRT or Hardcopy Interactive Device
The 8086 Family Users Manual Supplement for the
8087 Numeric Data Processor (121586-001)
OPTIONAL HARDWARE
Universal PROM Programmer*
Line Printer*
Shipping Media
'Recommended
1 Single and 1 Double Density Diskette
ORDERING INFORMATION
Part Number
Description
MDS*-387
8087 Software Support Package
Requires Software License
*MOS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences
Corporation.
16-27
AFN-01574A
8087 SUPPORT LIBRARY
• Library to support floating point
arithmetic in PLlM·86 and ASM·86
• Common elementary function library
provides trigonometric, logarithmic
and other useful functions
• Full 8087 Software Emulator for soft·
ware debugging without· the 8087
component
• Accurate, verified and efficient imple·
mentation of algorithms for functions
• Decimal conversion module supports
binary·decimal conversions
• Error·handler module simplifies
floating point error recovery
• Supports proposed IEEE Floating
Point Standard for high accuracy and
software portability
The 8087 Support Library provides PUM·86 and ASM·86 users with the equivalent numeric data processing capability
of Fortran·86. With the Library, it is easy for PUM·86 and ASM·86 programs to do floating pOint arithmetic. Programs
can link in modules to do trigonometric, logarithmic and other numeric functions, and the user is guaranteed accurate,
reliable results for all appropriate inputs. The 8087 Support Library implements Intel's REALMATH.standard and also
supports the proposed IEEE Floating Point Standard. Consequently, by using this Library, the PUM·86 user not only
saves software development time, but is guaranteed that the numeric software meets industry standards and is
portable-his software investment is maintained.
The 8087 Support Library consists of the common elementary function library, the decimal conversion module, the
error handler module, the full 8087 Software emulator and interface libraries to the 8087 and to the 8087 emulator.
B.PLM
A.PLM
mqo,TNN, PROCEDURE (THETA) REAL EXTERNAL;
DECLARE THETA REAL;
ENOmq..TNN;
DECLARE (INPUT_VALUE, OUTPUT_VALUE) REAL;
INPUT_VALUE .0.62;
I' Te.t value '/
O!JTPUT_ VALUE .mqe,TNN(lNPUT_ VALUE);
I' Now with the t.. t Input, OUTPUT_VALUE 1, .bout
0.55112803'/
D.ASM
C.ASM
, Thl. EXTRM mUll .ppear "ut,ld. oJ.U SEGMENT·ENDS
I-------"'~ LlNK86
;pa,n:
EITRN mq.,TNH: FAR
INPUT_VALUE
DQ 4062
• ,nll!.hul!on". t••!
; .. Iuo
1-----1
ASM·66 I------.~
LINKED USER
OBJECT MODULE
; Th.lol!"w,nQ cod.duphc.to.the.bovoPLIN
; ."iqnm.nl 'l.temul, ",copt w,th LONG _fU:AL
;v.".bl••
: :.~~ ,h.
p.,..",.t., onto th. aOB7
CALL mq.rTNH
; take tho hy.,boho tonqont
rSTP OUTPUT_VALUE .•IOJ. 110. on."..' ond pop Ih.
;8087."ck
, Wilh lhe ,•• , input, OUTPUT VALUE" now oboul
;0.55112803
The following are trademarks of Intel Corporation and may only be used to Identify Intel products: BXP, CREDIT, Intellec, Multibus, ISSC, Multimodule, ICE, iSSX, PROMPT, lCS,
Library Manager, Promware, In site, MCS, RMX, Intel, Megachassis, UPI, Intelevision, Micromap, j.!Scope and the combination of ICE, iCS, ISSCICS, 1m, Inslte, Intel, jntelevlsion,
Intellec, iSeC, iSeX, MCS, or RMX and a numerical suffix.
October 1981
© INTEL CORPORATION, 1981
16-28
Lit 2-210209'()Ol
8087 SUPPORT LIBRARY
CEL87.LlB
THE COMMON ELEMENTARY FUNCTION LIBRARY
CEL87.LlB contains commonly used floating point functions. It is used along with the 8087 numeric coprocessor or
the 8087 emulator and it provides a complete package of elementary functions, giving valid results for all appropriate
inputs. This library provides PUM-86 and ASM-86 users all the math functions supported intrinsically by the
Fortran-86. Following is a summary of CELS7 functions, grouped by functionality.
Rounding and Truncation Functions:
mqerlEX, mqerlE2, and mqerlE4 round a real number to the nearest integer; to the even integer if there is a tie. The
answer returned is real, a 16-bit integer or a 32-bit integer respectively.
mqerlAX, mqerlA2, mqerlA4 round a real number to the nearest integer, to the integer away from zero If there is a tie;
the answer returned is real, a 16-bit integer or a 32-bit integer, respectively.
mqerlCX, mqerlC2, mqerlC4 truncate the fractional part of a real input; the answer is real, a 16-blt integer or a 32-bit integer, respectively.
Logarithmic and Exponential Functions:
mqerLGD computes decimal (base 10) logarithms.
mqerLGE computes natural (base e) logarithms.
mqerEXP computes exponentials to the base e.
mqerY2X computes exponentials to any base.
mqerYI2 raises an Input real to a 16-bit integer power.
mqerYI4 is as niqerYl2, except to a 32-bit integer power.
mqerYIS is as mqerYl2, but it accommodates PUM-86 users.
Trigonometric and Hyperbolic Functions:
mqerSIN, mqerCOS, mqerTAN compute sine, cosine, and tangent.
mqerASN, mqerACS, mqerATN compute the corresponding inverse functions.
mqerSNH, mqerCSH, mqerTNH compute the corresponding hyperbolic functions.
mqerAT2 is a special version of the. arc tangent function that accepts rectangular coordinate Inputs.
Other Functions:
mqerDIM Is FORTRAN's positive difference function.
mqerMAX returns the maximum of two real Inputs.
mqerMIN returns the minimum of two real inputs.
mqerSGH combines the sign of one Input with the magnitude of the other input.
mqerMOD computes a modulus, retaining the sign of the dividend.
mqerRMD computes a modulus, giving the value closest to zero.
DCON87.LIB
THE DECIMAL CONVERSION
LIB~ARY
DCON87.LlB Is a library of procedures which. convert binary representations of floating point numbers and ASCIIencoded string of digits.
The binary-te-decimal procedure mqcBIN DECLOW accepts a binary number in any of the formats used for the
representation of floating point numbers In the 8087. Because there are so many output formats for floating pOint
numbers, mqcBIN_DECLOW does not attempt to provide a finished, formatted text string. Instead, It provides the
"building blocks" for you to use to construct the output string which meets your exact format specification.
16-29
AFN02063A
intel"
8087 SUPPORT LIBRARY
The decimal-to-binary. procedure mqcDEC_BIN accepts a text string. which consists of a decimal number with
optional sign, decimal'point,and/or power-of-ten exponent. It translates the string into the caller's choice of binary
formats.
Decimal-to-binary procedure mqcDECLOW_BIN is provided for cal,lers who have already broken the decimal number
into its constituent parts.
.
The procedures mqcLONG_TEM P, mqcSHORT_ TEM P, mqcTEM P_LONG, and mqcTEM P_SHORT convert floating
point numbers between the longest binary format, TEMP_REAL, and the shorter formats.
.
EHS7.LlB
THE ERROR HANDLER MODULE
EH87.LlB 15 a library of five utility procedures which a user can utilize for writing trap handlers. Trap handlers are
'
called when an unmasked 8087 error occurs.
The 8087 error reporting mechanism can be used not only to report errorconditions, but also to let software Implement
IEEE standard options not directly supported by the chip. The three such extensions to the 8087 are: normalizing
mode, non-trapping not-a-number (NaN), and non-ordered comparison. The utility procedures support these, extra
features.
'
DECODE is called near the beginning of the trap handler. It preserves the complete state of the 8087, and also identifies what function called the trap handler, a,nd returns available arguments and/or results. DECODE eliminates much
of the effort needed to determine what error caused the trap handler to be called.
NORMAL provides the "normalizing mode' I capability fo'rhandling the "D" exception. By calling NORMAL in your trap
handler, you eliminate the need to write code in your application program which tests for non-normal inputs.
SIEVE provides two capabilities for handling the "I" exception. It. implements non-trapping NaN's and non-ordered
comparisons. These two IEEE standard features are useful for diagnostic work.
ENCODE is called near the end of the trap handler..!t restores the state of the 8087 saved by DECODE, and performsa
choice of concluding actions, by either retrying tlie offending functionor returning a specified result.
'
FILTER calls each of the above four procedures. If your error handler does nothing more than detect fatal errors and,
implement the features supported by SIEVE and NORMAL, then your interface to EH87.LlB can be accomplished with
a single call to FILTER,
ESOS7
THE FULLSOS7 EMULATOR
E8087 is an object module that functionally emulates the 8087 coprocessor chip. It Is Ideal for use during prototyplng
and debugging floating point programs. However, the target system should use the 8087 component because.it exe.
cutes 1000 times faster and uses significantly less memory.
16-30
AFN02063A
8087 SUPPORT LIBRARY
E8087.LlB, 8087.LlB, 87NULL.LlB
INTERFACE LIBRARIES
EBOB7. LIB, BOB7.LlB and B7NULL. LIB libraries configure a user's application program for his run·time environment:
running with the emulator, with the BOB7 component or without floating point arithmetic, respectively.
SPECIFICATIONS
OPERATING ENVIRONMENT
Optional Hardware
BOB6/BOBB Based Microcomputer System
Universal PROM Programmer"
Line Printer"
DEVELOPMENT.ENVIRONMENT
Required Software .
Required Hardware
For Series II:
BOB6/8CfB8 Software Development Package-"MDS-308,
MDS-309 or MDS-31l .
Intellec Microcomputer Development System
- Model BOO
- Series II (Models 220, 225 or equivalent)
- Series III
64K Bytes of RAM Memory
Documentation Package
Numeric Support Library Manual
Minimum One Diskette Drive
-Single or Double" Density
Shipping Media
System Console
- CRT or Hardcopy Interactive Device
1 Single and 1 Double Density Diskette
·Recommended
ORDERING INFORMATION
Part Number
Description
MDS" 319
BOB7 Support Library
Requires Software License
'MDS Is an ordering code only and Is not used as a product name or trademark. MDS Is a registered trademark of Mohawk Data Sciences Corporation.
16-31
AFNa2063A
8089 lOP
SOFTWARE SUPPORT PACKAGE
• Program Generation for the 8089 I/O
Processor on the Intellec®
Microcomputer Development System
• Supports 8089-Based Addressing
Modes wit~ II Structure Facility that
Enables Easy Access to Based Data.
• Contains 8089 Macro Assembler, plus
Relocation and Linkage Utilities
• Powerful Macro Capabilities
• Relocatable Object Module
Compatible with All iAPX 86 and iAPX
88 Obj~ct Modules
• Provides Timing Information in
Assembly Listing
• Fully Supports Symbolic Debugging
with the RBF-89 Software Debugger
• Fully Detailed Set of Error Messages
The lOP Software Support Package extends Intellec Microcomputer Development Systemsupport to the SOS9
I/O Processor. The macro assembler translates symbolic SOS9 macro assembly language instructions into
relocatable machine code. The relocation and linkage utilities provide compatibility with iAPX S6, iAPX SS, and
SOS9 modules, and make structured, modular programming easier.
The macro assembler also provides symbolic debugging capability when used with the RBF-S9 software
. debugger. SOS9 program modularity is supported with inter-segment jumps and calls. The macro assembler
also provides instruction cycle counts in the listing file, for giving the programmer execution timing information. The programs in the SOS9 Software Support Package run on any Intellec Series II or ModelSOO with 64K
bytes of memory.
expo
The following are trademarks of Intel Corporation and may be used only to identify Intel products:
CREDIT.lntellec, Multibus,l,lSBC, Multimodule, ICE. iSex. PROMPT,ICS.
iRMX, Library Manager, Promware, Insite, MeS, RMX.lntel. Megachassls, UPl,lntelevlslon, Mlcromap,l'Scope and the combination of ICE, iS8C,Isax, MCS, Dr RMX and 8 numerical
suffix.
-lnl.1 Corporation 1979. 1980
16-32
911Q0999.02 Rev. B
intel'
8089 lOP SOFTWARE SUPPORT PACKAGE
FUNCTIONAL DESCRIPTION
so that any changes to that sequence need to be
made in only one place in the program. Common
code sequences that differ only slightly can also be
referred to with a macro call, and the differences can
be substituted with macro parameters.
The lOP Software Support Package contains:
ASM89 -The 8089 Macro Assembler.
LlNK86 - Resolves control transfer references between 8089 object modules, and data references in 8086, 8088, and 8089
modules.
LOC86 -Assigns absolute memory addresses to
8089 object modules.
OH86
-Converts absolute object modules to
hexadecimal format.
UPM
-The Universal PROM Mapper, which supports PROM programming in all iAPX
86/11 and iAPX 88/11 applications.
ASM89 translates symbolic 8089 macro assembly
language instructions into the appropriate machine
codes. The ability to refer to both program and data
addresses with symbolic names makes it easier to
develop and modify programs, and avoids the errors
of hand translation.
ASM89 provides symbolic debugging information in
the object file. The RBF-89 debugger makes use of
this information, so the programmer can symbolically debug 8089 programs. ASM89 also provides
cycle counts for each instruction in the assembly
listing file (see Table 1). These cycle counts help the
programmer determine how long a particular
routine or code sequence will take to execute on the
8089.
ASM89 provides relocatable object module compatibility with the 8086 and 8088 microprocessors.
This object module compatibility, along with the
8086/8088 relocation and linkage utilities, facilitates
the designing of iAPX 86/11 and iAPX 88/11 systems.
The powerful macro facility allows frequently used
code sequences to be referred to by a single name,
ASM89 fully supports the based addressing modes
of the 8089. A structure facility allows the user to
define a template that enables accessing of based
data symbolically.
SPECIFICATIONS
Documentation Package
Operating Environment
REQUIRED HARDWARE
Intellec® Microcomputer Development System
-Model 800
-Series II (Models 220, 225 or equivalent)
64K Bytes of RAM Memory
8089 Macro Assembler User's Guide (9800938)
8089 Macro Assembler Pocket Reference (9800936)
MCS-86 Software Development Utilities Operating
Instructions for ISIS-I/ Users (9800639)
Universal PROM Programmer User's Manual
(9800819)
Minimum One Diskette Drive
-Single or Double* Density
System Console
-CRT or Hardcopy Interactive Device
OPTIONAL HARDWARE
Universal PROM Programmer*
Line Printer*
Shipping Media
-Single and Double Density Diskettes
ORDERING INFORMATION
REQUIRED SOFTWARE
ISIS-II Diskette Operating System
-Single or Double Density
Part Number
Description
MDS*-312
8089 lOP Software Support Package
Requires Software License
*MDS is an ordering code only and is not used as a product name
or trademark. MDS" is a registered trademark of Mohawk Data
Sciences Corporation.
*Recommended
16-33
AFN·00840B
inter
8089 lOP SOFTWARE SUPPORT PACKAGE
Table 1. Sample Program Listing
1;;1$-11 .:.IIU I'IRt~O ~SH"9LE:f: KillS M$;$EI'I8L'I OF HODULE THSk
M!JDULE PI.ACE~ ,~ ·rl. TMS~: OBJ
I .. VOKED 8'1'1
lIS!I!,)q :rl:t"uk.,,9' 9." ","ero d.bug pag.wldth(132) print(:'I:tukx.1st.)
09.I EtT
4<;;i!;~!I!.ER
'l!IJ£CT
to(a£
TIP'lI!H.:
IFtC "He
LINE SOURCE
.,,
.. 4" .......... •
1
•••• • ........................... , ................ .
,.l
8889 TASK PROGRA"
5
?
,e
"
BBBD
................ "' .............................................. .
n,,'1'
TASt:
TtlS': •• lJllent
In the t i I"st port of t.h i S sIlI"pl. progr·a" dat.o. Is "oved rro"
818' systu R,.H t.o "liter'll 10clll to the 888' lOP.
In ·t.hl· •• cond
port. the dat.a i I "ovid frol'l t.hl local "e"ory t.o 0. dot.o port.
cd,o in t.he 888' 110 SpIlCI.
II
..
12
OJ
15 dotol)port.l8251
equ
IG (OI'lfll'lndlPport.U251 .qu
1? buU,rUBB'J
,qu
':8111
CIIII
11211
ScSIIBh
DeBllih
12Uh
"
!9 !xt.rn
butt,r88186
21 I-.:trn
V
2!
:;.dlf,n. ( .. oero.l>
gb.burre"';U889
2J t
Ipd i
gc. 'II
1I0vb
be. [gc I
"
""
",
27 t.d./i ne (flac:ro w2(po.ro.fl wl. poro.".2)
28 (
Inc
'=poro."wl
dec
'=poro".2
j nz
'=parofl.2.%loop
JI)
320NEI
Ipdl
2'
3B
'IIn ...
BIBI
1118
BlU
3138 •• 12
888A
Sill
BIll
6182
8812
8816
8818
" "
".," '17
"
........
.."'"
71
•.,1 aaeo
1 ~ ..
2138
'44
,]4
an.
881M
413C
,s<
BIle
4841 F3
17 ~
"IF
1111 Ilea
t 118 ltea
2B'!I
'19
236
,,,
191.
Ball
1138 .112
5118 . . .118811
6182
8833
Bl16
8191
8821
sea
'1
'1
'1
.....
.,.,
.,
lilA
aa]~
2838
Dale
483C
UJE
n·n
BOil
It
Ull
~81j.
FD
lice
..."
...
"'17
377
2148
HE '1EH. ' (O"PLEfE,
n,
'"
'"
-.,.,
'" ". .,.,
'" .,.,
'"
4848 F2
]-'~
~o
ERRtH!';.
flOVi
Ipd;
flovb
""
"
lIou burrlr address Into cli
loo.d pOint.r to count into .Ct
Hove byte count int.o Bt
.
'OCo.\ loop
I Incl".I!'".nt pOlnt..r Into 10urCI
O.cr'fI.nt byte count
I loop bock I r bytl c.ount ) B
I
lood r.gl ster C,. WI th oddr •••
SBeG burr.r
or
Hov, burr.r o.ddr ••• Into ca
Lood pOint." to count Into CC
Hov. byte count into 8C
gb. bvf(e,.UB89
gc • ..,
bc,[gc J
38
[gb J. [90.]
"OVI byte r"o" 8886 to S899 bur,.~
.39 loopll: "ovb
tncr .... nt. po I ntl'" Into 888' burr,r
4.
Inc
41 :':no.crO w2(gb. 9C)
42
inc
,=PARAH wl
"3
gb
J Incrl".nt polntlr Into
44
dlc
k.PARAH.2
'"
gc
I Dlcrllunt blJt.. count
46
J n1"
:':P~RAHw2
47
ge.%LOOP
I loop bock I r butt count) 8
49
lOOPBB
,.
... ., ..
". .,
'" "., .,.,-,
2:!j"
IRAII burr.", In 888' systeli ·"I"ory·
110cct.lon or t.he burr.r. count
34 ::"ocro 1
.1
'2
8823
"
18251 OP on 8889 locill bUI
18251 tP on 8889 loclII bUI
IR,.1I bu·rrer In.B8899 110 SPAC'
lood CA With o.ddrus: or 8251 DP
load CC with oddrtu or 82:51 tP
58 TWO=
51
52 :;"o.cro 1
go. dllt.0.9port98251
go.. cOfl"ondlport.IU51
J
"
"""
gb.burrerUQB'J
gc.y
bed gc J
I Kov. burfer address Into C8
LOQd pOintlr t.o count int.o CC
Hove byte" count int.o at
-54
",9
.""
!copl'l1
.""
""
"
=
t gc]. B.1oopEll
Jnbl;
flollb
(go.l.[gbJ
gb. ge)
~nQcro_2(
o .... SI(
,b
go
"
,,,
,'::LDJP
"'
LOOf-IH
%PAR~H_l
; Incr.H'IG'nt pOinter into .ource
P .:a RIl H• ,"!
: DG'cr"('\Int. byt.' count
:;PARAl1w2
~;
: Loop back i r byte count) B
"It
end:;
:-8 EHD
~(!U~Ir..
16-34
AFN.()()840B
ICE-86ATM
iAPX 86 IN-CIRCUIT EMULATOR
• Disassembly of Trace or Program
Memory from Object Code into
Assembler Mnemonics
• Software Debugging With or Without
User System
• Handles Full 1 Megabyte
Addressability of iAPX 86
• Enhance Existing ICE-86 ™ Emulators
to ICE-86A ™ Capabilities with
ICE-86U™ Upgrade Package
• Real-Time In-Circuit Emulation of iAPX
86 Microsystems
• Emulate Both Minimum and Maximum
Modes of 8086 CPU
• Full Symbolic Debugging
• Breakpoints to Halt Emulation on a
Wide Variety of Conditions
• Comprehensive Trace of Program
Execution
The Intel® ICE-86A In-Circuit Emulator provides sophisticated hardware and software debugging capabilities
foriAPX 86 microsystems and iAPX 86 Single-Board Computers. These capabilities include In-Circuit Emulation for the 8086 Central Processing Unit plus extensions to debug systems including the 80891/0 Processor
and 8087 Numeric Processor Extension. The emulator includes three circuit boards which reside in any
Intellec® Microcomputer Development System. A cable and buffer box connect the Intel/ec system to the user
system by replacing the user's 8086, thus extending powerful Intellec system debugging functions into the
user system. Using the ICE-86A module, the designer can execute prototype 8086 or 8089 software in
continuous or single-step modes and can SUbstitute blocks of Intellec system memory for user equivalents.
Breakpoints allow the user to stop emulation on user-specified conditions of the iAPX 86 system, and the trace
capability gives a detailed history of the program execution prior to the break. All user access to the prototype
system software may be done symbolically by referring to the source program variables and labels.
The ICE-86U In-Circuit Emulator upgrade package converts any existing ICE-86 module (non-A version) to the
capabilities of an ICE-86A module.
The following are trademarks of Intel Corporation and its affiliates and may be used only to
products: ,
tnsite, iRMX, System 2000, CREDIT, iRMXlSO, MULTIBUS, PROMPT, Promware, Megachassis, Library Manager, MAIN
iCS and a numerical suffix.
© INTEL CORPORATION.
1981.
16-35
ICE-86A™ IN-CIRCUIT EMULATOR
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The ICE-86A emulator allows hardware and software
development to proceed interactively. This is more
effective than the traditional method of independent
hardware and software development followed by
system integration. With the ICE-86A module, prototype hardware can be added to the system as it is
designed. Software and hardware testing occurs
while the product is being developed.
Conceptually, the ICE-86A emulator assists three
stages of development:
1. It can be operated without being connected to
the user's system, so the ICE-86A module's
debugging capabilities can be used to facilitate
program development before any of the user's
hardware is available.
2. Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8086 socket.
Through ICE-86A emulator mapping capabilities,
Intellec memory, ICE module memory, or diskette
memory can be substituted for missi ng prototype
memory. Time-critical program modules are
debugged before hardware implementation by
using the 2K-bytes of high-speed ICE-resident
memory. As each section of the user's hardware is
completed, it is added to the prototype. Thus
each section of the hardwC!re and software is
"system" tested as it becomes available.
3. When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-86A module is then used for real-time
emulation of the 8086 to debug the system as a
completed unit.
Thus the ICE-86A module provides the user with the
ability to debug a prototype or production system at
any stage in its development without introducing
extraneous hardware or software test tools.
SYMBOLIC DEBUGGING
Symbols and PUM statement numbers may be substituted for numeric values in any of the ICE-86A
emulator commands. This allows the user to make
symbolic references to 1/0 ports, memory addresses, and data in the user program. Thus the user
need not remember the addresses of variables or
program subroutines.
Symbols can be used to reference variables, procedures, program labels, and source statements. A
variable can be displayed or changed by referring to
it by name rather than by its absolute location in
memory. Using symbols for statement labels, program labels, and procedure names simplifies both
tracing and breakpoint setting. Disassembly of a
section of code from either trace or program
memory into its assembly mnemonics is readily
accomplished.
PLUG INTO
USER
8086 SOCKET
r - - - - - - - - - - - - -
I ..- ____ -,
I I
I I
I I
I
I
I
I
II
- ---- - - - - - --- - -- -- -- --- T·CABLE
--,
I
I
I
I
I
I
I
I
I
I IN~~LS\EC
I
I
I
IL ____ - lI
AUXILLIARY CONNECTOR
L ____________________________
I
I
I
II
~N~L~~T!.MJ
Figure 1. ICE-8SA ™ Emulator Block Diagram
16-36
AFN·01950A
ICE-86A ™ IN-CIRCUIT EMULATOR
A typical iAPX 86 development configuration. It is based on Intellec® Series III Development System, which
hosts the ICE·86A™ emulator. The ICE·86A™ module is shown connected to a user prototype system, in this
case, an SDK·a6.
Furthermore, each symbol may have associated
with it one of the data types BYTE, WORD, INTEGER,
SINTEGER (for short, 8·bit integer), POINTER,
REAL, OREAL, or TREAL. Thus the user need not
remember the type of a source program variable
when examining or modifying it. For example, the
command "!VAR" displays the value in memory of
variable VAR in a format appropriate to its type, while
the command "!VAR = !VAR + 1" increments the
value of the variable.
The user symbol table generated along with the ob·
ject file during a PUM·86, PASCAL·86 or FORTRAN·
86 compilation or an ASM·86 assembly is loaded into
memory along with the user program which is to be
emulated. The user can utilize the available symbol
table space more efficiently by using the SELECT
option to choose which program modules will have
symbols loaded in the symbol table. The user may
also add to this symbol table any additional symbolic
values for memory addresses, constants, or
variables that are found useful during system
debugging.
The ICE·86A module provides access through sym·
bolic definition to all of the 8086 registers and flags.
The READY, NMI, TEST, HOLD, RESET, INTR,
MN/MX, and RQ/GT pins of the 8086 can also be
read. Symbolic references to key ICE·86A emulation
information are also provided.
MACROS AND COMPOUND COMMANDS
The ICE-86A module provides a programmable diagnostic facility which allows the user to tailor its operation using macro commands and compound
commands.
A macro is a set of ICE-86A commands which is given
a single name. Thus, a sequence of commands
which is executed frequently may be invoked simply
by typing in a single command. The user first defines
the macro by entering the entire sequence of commands which he wants to execute. He then names
the macro and stores it for future use. He executes
the macro by typing its name and passing up to ten
parameters to the commands in the macro. Macros
may be saved on a disk file for use in subsequent
debugging sessions.
Compound commands provide conditional execution of commands (IF), and execution of commands
until a condition is met or until they have been executed a specified number of times (COUNT,
REPEAT).
Compound commands and macros may be nested
any number of times.
16-37
AFN·01950A
ICE-86A™ IN-CIRCUIT EMULATOR
emulation and provide a detailed trace of execution
in any part of the user's program. A summary of the
emulation commands is shown in Table 1.
MEMORY MAPPING
Memory for the user system can be resident in the
user system or "borrowed" from the Intellec System
through the ICE-86A emulator's mapping capability.
The speed of run emulation by the ICE-86A module
depends on which mapping options are being used.
Table 1. Summary of ICE-86ATM Emulation
Commands
Command
The ICE-86A emulator allows the memory which is
addressed by the 8086 to be mapped in 1K-byte
blocks to:
GO
1. Physical memory in the user's system, which provides 100 percent real-time emulation atthe usersystem clock rate (up to 5 MHz) with no wait
states.
where START and DELAY are statement
labels.
STEP
4. A random-access diskette file, with emulation
speed comparable to Intellec System memory, except the emulation must wait when a new page is
accessed on the diskette.
The user can also designate a block of memory as
non-existent. The ICE-86A module issues an error
message when any such "guarded" memory is addressed by the user program.
As the user prototype progresses to include
memory, emulation becomes real time.
Initializes emulation and allows the user to
specify the starting point and breakpoints.
Example:
GO FROM .S:TARTTILL .DELAY EXECUTED
2. Either of two 1K-byte blocks of ICE-86A module
high-speed memory, which allow nearly fullspeed emulation (with two additional wait states
per 8086-controlled bus cycle).
3. Intellec System memory, which provides emulation at approximately 0.02 percent of real-time with a
5 MHz clock.
Description
Allows the user to Single-step through the
program.
Breakpoints: The ICE-86A module has two breakpoint registers that allow the user to halt emulation
when a specified condition is met. The breakpoint
registers may be set up for execution or nonexecution breaking. An execution breakpoint consists of a single address which causes a break
whenever the 8086 executes from its queue an instruction byte which was obtained from the address.
A non-execution breakpoint causes an emulation
break when a specified condition other than an instruction execution occurs. A non-execution breakpoint condition, using one or both breakpoint
registers, may be specified by anyone of or a combination of:
1. A set of address values. Break on a set of address
values has three valuable featu'res:
OPERATION MODES
a. Break on a single address.
The ICE-86A software is a RAM-based program that
provides the user with easy-to-use commands for
initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters. ICE-86A commands are
configured with a broad range of modifiers which
provide the user with maximum flexibility in describing the operation to be performed.
Emulation
Emulation commands to the ICE-86A emulator control the process of setting up, running and halting an
emulation of the user's iAPX 86 System. Breakpoints
and tracepoints enable the ICE-86A module to halt
b. The ability to set any number of breakpoints
within a limited range (1024 bytes maximum)
of memory.
c. The ability to break in an unlimited range. Execution is halted on any memory access to an
address greater than (or less than) any 20-bit
breakpoint address.
2. A particular status of the 8086 bus (one or more
of: memory or I/O read or write, instruction fetch,
halt, or interrupt acknowledge).
3. A set of data values (features comparable to
break on a set of address values, explained in
point one).
4. A segment register (break occurs when the register is used in an effective address calculation).
16-38
AFN'()1950A
intel·
ICE-86A™ IN-CIRCUIT EMULATOR
Emulation break can also be set to occur on an
external signal condition. An external breakpoint
match output and emulation status lines are provided on the buffer box. These allow synchronization
of other test equipment when a break occurs or
when emulation is begun.
Tracepoints: The ICE-86A module has two
tracepoint registers which establish match conditions to conditionally start and stop trace collection.
The trace information is gathered at least twice per
bus cycle, first when the address signals are valid
and second when the data signals are valid. If the
8086 execution queue is otherwise active, additional
frames of trace are collected.
Each trace frame contains the 20 addressldata lines
and detailed information on the status of the 8086.
The trace memory can store 1,023 frames, or an
average of about 300 bus cycles, providing ample
data for detemining how the 8086 was reacting prior
to emulation break. The trace memory contains the
last 1,023 frames of trace data collected, even if this
spans several separate emulations. The user has the
option of displaying each frame of the trace data or
displaying by instruction in actual ASM-86 Assembler mnemonics. Unless the user chooses to disable
trace, the trace information is always available after
an emulation.
Interrogation and Utility
Interrogation and utility commands give the user
convenient access to detailed information about the
user program and the state of the 8086 that is useful
in debugging hardware and software. Changes can
be made in both memory and the 8086 registers,
flags, input pins, and 1/0 ports. Commands are also
provided for various utility operations such as loading and saving program files, defining symbols and
macros, displaying trace data, setting up the
memory map, and returning control to ISIS-II.A summary of the basic interrogation and utility commands is shown in Table 2.
Table 2. Selected ICE-86A ™ Module Interrogation and Utility Commands
Memory/Register Commands
Display or change the contents of:
• Memory
• 8086 Registers
• 8086 Status flags
• . 8086 Input pins
• 8086 I/O ports
• ICE-86A Pseudo-Registers (e.g. emulation timer)
RQ/GT
Set or display the status of the Request/Grant facility which
enables the ICE-86A module to share the system bus with
coprocessors.
Memory Mapping Commands
Display, declare, set, or reset the ICE-86A memory mapping.
CAUSE
Display the cause of the most recent emulation break.
Symbol Manipulation Commands
Display any or all symbols, program modules, and program
line numbers and their associated values (locations in
memory).
BUS
Display which device in the user'siAPX 86 system is currently master of the system bus.
PRINT
Display the specified portion of the trace memory.
LOAD
Fetch user symbol table and object code from the inputfile.
Set the domain (choose the particular program module) for
the line numbers.
EVALUATE
Display the value of an expression in binary, octal, decimal,
hexadecimal, and ASCII.
Define new symbols as they are needed in debugging.
Remove any or all symbols, modules, and program
statements.
Change the value of any symbol.
Select program modules whose symbols will be used in
debugging.
CLOCK
Select the internal (lCE-86A module provided, for standalone mode only) or an external (user-provided) system
clock.
TYPE
Assign or change the type of any symbol in the symbol table.
RWTIMEOUT
Allows the user to time out READ/WRITE command signals
based on the time taken by the 8086 to access Intellec
memory or diskette memory.
DASM
Disassemble user program memory intoASM-86Assembler
mnemonics.
ENABLE/DISABLE RDY
Enable or disable logical AND of ICE-86Aemulator Ready
with the user Ready signal for accessing Intellec memory,
ICE memory, or diskette memory.
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AFN·01950A
inter
ICE-86A™ IN-CIRCUIT EMULATOR
iAPX 86/20 DEBUGGING
The ICE-86A module has the extended capabilities to
debug iAPX 86/20 microsystems which contain both
the 8086 microprocessor and the 8087 Numeric
Processor Extension (NPX). An iAPX 86/20 system is
configured in the 8086's "maximum" mode and
communication between the processors is accomplished through the RO/GT signals. Debugging can
be done either using theB087 chip itself (in which
case the 8086 ESCAPE instruction is interpreted as a
floating point instruction) or using the 8087
software emulator E8087 (where the 8086 INTERRUPT instruction is interpreted as a floating point
instruction). Three new data types are defined to use
the NPX:
REAL (4 byte Short Real)
OREAL (8 byte Long Real)
TREAL (10 byte Temporary Real)
While the 8087 NPX is not a programmable part, it
does interact closely with the 8086 and can execute
instructions in parallel with it. The ICE-86A module
provides information about the relative timing of
instruction execution in each processor so that the
complete system can be debugged. Other debugging capabilities available through the ICE-86A
module are: symbolically disassemble NPX call instructions from memory or trace history; display or
change the control, status and flag values of the
NPX; display the NPX stack either in hexadecimal or
disassembled form; and display.the last ,instruction
address, last operand, and last operand address.
iAPX 86/11 DEBUGGING
The 8089 Real-Time Breakpoint Facility (RBF-89) is
an extension of the ICE-86A emulator that aids in
testing and trouble-shooting iAPX 86/11 systems designed around a combination of the 8086 CPU and
the 8089 Input/Output Processor (lOP). RBF-89 interrogates 8089 registers, sets breakpOints in 8089
programs, and performs its other functions by preparing special control blocks in application system
memory. It then issues input/output channelattention commands to the 8089 in the user's system
to perform these functions. While using the RBF-89
extension, the user can also enter and execute the
other standard ICE-86A emulator commands.
RBF-89 allows the user to. load his application
(channel) program from diskette into 8089 lOP
memory and execute it in real time. The program can
reside in either local (system) RAM (accessible by
both the 8086 and 8089 microprocessors), or remote
RAM (aCCessible by the 808910P only). The user may
request execution to begin at any location and continue until normal termination, a specified breakpoint is reached, or tt')e program 'is otherwise
aborted. If a program is modified during a debugging session, RBF-89 can save the latest version by
copying it from application system memory to a diskette file.
Breakpoints
RBF-89 supports setting up to twelve breakpoints
(six per 8089 channel) in the user program. RBF-89
implements each breakpoint by inserting a HALT
instruction at the breakpoint location, while saving
the overwritten instruction in temporary storage.
When a breakpoint is reached during program execution the program h,alts. At this point the user can
examine 8089 registers, flags, and memory, and optionally resume program execution. The invoked
breakpoint address is recorded in one of two breakpoint registers-one register for each 8089 channel.
Through simple RBF-89 commands the user can
display or change the contents of these registers.
Symbolic Debugging
As in the ICE-86A emulator, theRBF-89 extension
accepts symbolic references for variables and
labels, including symbols in the symbol table
generated by the ASM-89 assembler.
Through RBF-89, the user can display and change
the contents of :
-
memory, which can be displayed as either
numeric data or disassembled (8089 assemblylanguage mnemonic) code.
-
all 8089 registers except the channel control
pointer (CCP) and status flags.
Multiprocessor Operation
The ICE-86A emulator and RBF-89 support 8089
configurations in both local and remote modes. The
ICE-86A emulator may be operating either in minimum or maximum mode. In maximum mode, the
8086 RO/GT lines are employed. This is required for
the 8089 local mode configuration to provide local
bus arbitration between the two processors. Using
RBF-89, the user can:
16-40
AFN'()1950A
ICE-86A ™ IN-CIRCUIT EMULATOR
program, running on the 8089, reads and writes
data to and from 8089 memory and registers, and
sets and removes breakpoints in the user's task
program.
Set RO/GT to operate for a local or remote
configuration.
Display status to determine which processor controls the system bus.
The 200 bytes of RAM.required by the utility program must be accessible to both the ICE-86A
emulator and the 8089.
Start and halt 8089 channel programs.
RBF-89 permits the 8089 and emulated 8086 to run
simultaneously as well as sequentially. The user can
specify breakpoints and begin program execution in
three operating sequences:
DC CHARACTERISTICS OF THE
ICE-86A™ MODULE USER CABLE
1. Output Low Voltages [Vo(,(Max)=O.4V]
Set breakpoints, start the 8089, and return control
to the console until a breakpoint is reached or the
program runs to completion or is aborted. Use this
sequence when the 8086 and 8089 programs do
not need to be executed simultaneously.
IOL (Min)
ADO-AD15
A16/S3-A19/S7, BHE/S7, RD,
LOCK, OSO, OS1, SO, S1, S2,
WR, M/iO, DT/R, DEN, ALE,
INTA
Set breakpoints, start the 8089, return control to
the console, and start the 8086. This sequence lets
both microprocessors run simultaneou~!I'
Set breakpoints, start the 8086, and allow that
program to drive the 8089 program in a master/slave relationship. This sequence would be
used, for instance, to verify the 8086 communication driver program.
HLDA
8 mA
(16 mA @ 0.5V)
7 mA
16 mA
2. Output High Voltages [VOH (Min)=2.4V]
IOH (Min)
ADO-AD15
RBF-89 System Components
A16/S3-A19/S7, BHE/S7, RD,
LOCK, OSO, OS1, SO, S1, S2,
WR, M/IO, DT/R, DEN, ALE,
INTA, HLDA
RBF-89 is furnished as a superset of the ICE-86A
emulator software. Its main components are:
A HOST PROGRAM that resides in Intellec development system RAM, where it serves as an extension of the ICE-86A emulator's software driver.
This program, executed by the development system, translates the user's keyboard input into lowlevel directives that can be processed by the
RBF-89 control program (described below), and
converts information supplied by the control program into easily understood display output.
A CONTROL PROGRAM that resides in ICE-86A
emulator memory. Running on the emulator's 8086
microprocessor, the control program monitors
such operations as preparing program control
blocks for communication with the 8089 microprocessor; issuing commands to the 8089 to start,
terminate, and continue the 8089 task program;
and directing the 8089 to start execution of the
RBF-89 utility program (described below).
12 mA
(24 mA @ O.5V)
RO/GT
-3 mA
-2.6 mA
250 mA
3. Input Low Voltages [VIL (Max)=O.8V]
IlL (Max)
ADO-AD15
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1 JLf to GND)
-0.2
. -0.4
-0.8
-1.4
-3.3
mA
mA
mA
mA
mA
. 4. Input High Voltages [VIH (Min)=2.0V]
IIH (Max)
ADO-AD15
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1 JLF to GND)
80JLA
20JLA
40JLA
-0.4 mA
-1.1 mA
5. No current is taken from the user circuit at
Vee pin.
A UTILITY PROGRAM that resides in the 8089 RAM
in the user's prototype application system. This
16-41
AFN'()1950A
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ICE-86A™ IN-CIRCUIT EMULATOR
SPECIFICATIONS
Physical Characteristics
ICE-86A Operating Environment
PRINTED CIRCUIT BOARDS
Width: 12.00 in (30.48 cm)
Height: 6.75 in (17.15 cm)
Depth: 0.50 in (1.27 cm)
Packaged Weight: 9.00 Ib (4.10 kg)
REQUIRED HARDWARE
Intellec microcomputer development system with:
1. Three adjacent slots for the ICE-86A module.
2. 64K bytes of Intellec memory. If user prototype
program memory is desired, additional memory
above the basic 94K is required.
System console
Intellec diskette operating system
ICE-86A module
Electrical Characteristics
DC POWER
Vcc = +5V +5%-Wo
Icc = 17A maximum; 11A typical
Voo = +12V ±5%
100 = 120 mA maximum; 80 mA typical
VBB = -10V ±5% or -12V ±5% (optional)
IBB = 25 mA maximum; 12 mA typical
REQUIRED SOFTWARE
System Monitor
ISIS-II, version 3.4 or subsequent
ICE-86A software
Equipment Supplied
Printed circuit boards (3)
Interface cable and emulation buffer module
Operator's manual
ICE-86A software, diskette-based
Environmental Characteristics
OPERATING TEMPERATURE
0° to 40°C
Emulation Clock
User system clock up to 5 MHz or 2 MHz ICE-86A
internal ciock in stand-alone mode
OPERATING HUMIDITY
Up to 95% relative humidity without condensation.
ORDERING INFORMATION
Part Number
Description
MDS*-86A-ICE
iAPX 86 microsystem in-circuit emulator, cable assembly, and interactive software
MDS*-86U-ICE
Upgrade kit to convert ICE-86 emulators to ICE-86A emulator capabilities.
'MOS is an ordering code only and is not used as a product name or trademark. MOS" is a registered trademark of Mohawk Data
Sciences Corporation.
16-42
inter
ICE-88™
8088 IN-CIRCUIT EMULATOR
• Hardware In-Circuit Emulation
• 2K Bytes of High Speed ICE-88™
Mapped Memory
• Full Symbolic Debugging
• Breakpoints to Halt Emulation on a
Wide Variety of Conditions
• Software Debugging with or without
User System
• Comprehensive Trace of Program
Execution, Both Conditional and
Unconditional
• Handles Full 1 Megabyte
Addressability of 8088
• Disassembly of Trace or Memory from
Object Code into Assembler
Mnemonics
• Compound Commands
• Command Macros
The ICE-88 module provides In-Circuit Emulation for the 8088 microprocessor. It includes three circuit boards
which reside in Intellec® Microcomputer Development Systems. A cable and buffer box connect the Intellec
system to the user system by replacing the user's 8088. Powerfullntellec debug functions are thus extended
into the user system. Using the ICE-88 module, the designer can execute prototype software in continuous or
single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints allow
the user to stop emulation on user~specified conditions, and the trace capability gives a detailed history of the
program execution prior to the break. All user access to the prototype system software may be done symbolically by referring to the source program variables and labels.
The following are trademarks of Intel Corporation and may be used only to identify Intet products: i, Intel, INTEL, INTELLEC, MeS, im, ieS, tCE, UPI, exp, iSSC, iSeX, lNSITE, iRMX,
CREDIT, RMXI80, ~Scope, Multibus, PROMPT, Promware, Megachassis, library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE, SSC, RMXoriCS and a numerical
suffix; e.g., iSeC-BO.
© Intel Corporation 1980
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AFN·0145A
ICE-88™ IN-CIRCUIT EMULATOR
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
SYMBOLIC DEBUGGING
Symbols and PLiM statement numbers may be substituted for numeric values in any of the ICE-88 commands. This allows the user to make symbolic references to 1/0 ports, memory addresses, and data in the
user program. Thus the user need not remember the
addresses of variables or program subroutines.
The ICE-88 emulator allows hardware and software
development to proceed interactively. This is more
effective than the traditional method of independent
hardware and software development followed by
system integration. With the ICE-88 module, prototype
hardware can be added to the system as it is designed.
Software and hardware testing occurs while the product
is being developed.
Symbols can be used to reference variables, procedures, program labels, and source statements. A variable can be displayed or changed by referring to it by
name rather than by its absolute location in memory.
Using symbols for statement labels, program labels,
and procedure names simplifies both tracing and breakpoint setting. Disassembly of a section of code from
either trace or program memory into its assembly
mnemonics is readily accomplished.
Conceptually, the ICE-88 emulator assists three stages
of development:
1. It can be operated without being connected to the
user's system, so ICE-88 debugging capabilities can
be used to facilitate program development before
any of the user's hardware is available.
2. Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8088 socket. Through
ICE-88 mapping capabilities, Intellec memory, ICE
memory, or diskette memory can be substituted for
missing prototype memory. Time-critical program
modules are debugged before hardware implementation by using the 2K·bytes of high-speed ICE·resident
memory. As each section of the user's hardware is
completed, it is added to the prototype. Thus each
section of the hardware and software is "system"
tested as it becomes available.
Furthermore, each symbol may have associated with it
one of the data types BYTE, WORD, INTEGER,
SINTEGER (for short, 8-bit integer) or POINTER. Thus
the user need not remember the type of a source program variable when examining or modifying it. For
example, the command "!VAR" displays the value in
memory of variable VAR in a format appropriate to its
type, while the command "!VAR = !VAR + 1" increments
the value of the variable.
The user symbol table generated along with the object
file during a PLlM-86 compilation or an ASM-86 assembly is loaded into memory along with the user program
which is to be emulated. The user may add to this
symbol table any additional symbolic values for
memory addresses, constants, or variables that are
found useful during system debugging.
3. When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-88 module is then used for real time emula·
tion of the 8088 to debug the system as a completed
unit.
The ICE-88 module provides access through symbolic
definition to all of the 8088 registers and flags. The
READY, NMI, TEST, HOLD, RESET, INTR, and MN/MX
pins of the 8088 can also be read. Symbolic references
to key ICE-88 emulation information are also provided.
Thus the ICE-88 module provides the user with the
ability to debug a prototype or production system at any
stage in its development without introducing extraneous hardware or software test tools.
Y·CABLE
BUFFER BOX
~PLUGINTO
USER
8088 SOCKET
CBLE
1 - - - - - - ----I
I
I
I
I
1---'
I
I
I
I
I IN1Jo~~C" I
I
I
----------------
-
T-CABLE
I
FIRMWARE
CONTROLLER
BOARD
TRACE BOARD
I
88·CONTROLLER
BOARD
1
I
l
I'
, L ___ --1,<
L ___________________________
MULTlBUS5'!
AUXILIARY-CONNECTOR
Figure 1_ ICE_SST" Emulator Block Diagram
16-44
-,
I
I
I
I
I
I
I
~~~
AFN·0145A
intel'
ICE·88™ IN·CIRCUIT EMULATOR
A typicallCE·aa development configuration. It is based on a Model 235 Development System, which also
includes a Double Density Diskette Operating System and a Model 201 Expansion Chassis (which holds
the ICE·aa emulator). The ICE·aa module is shown connected to a user prototype system.
MACROS AND COMPOUND
COMMANDS
The ICE·88 module provides a programmable diagnostic
facility which allows the user to tailor its operation
using macro commands and compound commands.
The user can also deSignate a block of memory as nonexistent. The ICE-88 module issues an error message
when any such "guarded" memory is addressed by the
user program.
Compound commands provide conditional execution of
commands (IF), and execution of commands until a con·
dition is met or until they have been executed a specified number of times (COUNT, REPEAT).
Compound commands and macros may be nested any
number of times.
MEMORY MAPPING
Memory for the user system can be resident in the user
system or "borrowed" from the Intellec System through
ICE-88's mapping capability.
The ICE-88 emulator allows the memory which is
addressed by the 8088 to be mapped in 1K-byte blocks
to:
1. Physical memory in the user's system,
2. Either of two 1K-byte blocks of ICE-88 high-speed
memory,
3. Intellec memory,
4. A random-access diskette file.
Description
Command
A macro is a set of ICE·88 commands which is given a
single name. Thus, a sequence of commands which is
executed frequently may be invoked simply by typing in
a Single command. The user first defines the macro by
entering the entire sequence of commands which he
wants to execute. He then names the macro and stores
it for future use. He executes the macro by typing its
name and passing up to ten parameters to the com·
mands in the macro. Macros may be saved on a disk file
for use in subsequent debugging sessions.
GO
Initializes emulation and allows the
user to specify the starting point
and breakpoints. Example:
GO FROM .START TILL .DELAY
EXECUTED
where START and DELAY are statement labels.
STEP
Allows the user to
through the program.
single-step
Table 1. Summary of ICE·aa Emulation Commands.
OPERATION MODES
The ICE-88 software is a RAM-based program that provides the user with easy-to-use commands for initiating
emulation, defining breakpoints, controlling trace data
collection, and displaying and controlling system parameters. ICE-88 commands are configured with a broad
range of modifiers which provide the user with
maximum flexibility in describing the operation to be
performed.
Emulation
Emulation commands to the ICE-88 emulator control
the process of setting up, running and halting an emulation of the user's 8088. Breakpoints and tracepoints
enable ICE-88 to halt emulation and provide a detailed
trace of execution in any part of the user's program. A
summary of the emulation commands is shown in Table 1.
Breakpoints - The ICE-88 module has two breakpoint
registers that allow the user to halt emulation when a
16-45
AFN0145A
ICE·88™ IN·CIRCUIT EMULATOR
specified condition is met. The breakpoint registers
may be set up for execution or non-execution breaking_
An execution breakpoint consists of a single address
which causes a break whenever the 8088 executes from
its queue an instruction byte which was obtained from
the address. A non-execution breakpoint causes an
emulation break when a specified condition other than
an instruction execution occurs. A non-execution breakpoint condition, using one or both breakpoint registers,
may be specified by anyone of or a combination of:
program files, defining symbols and macros, displaying
trace data, setting up the memory map, and returning
control to the ISIS-II operating system. A summary of
the basic interrogation and utility commands is shown
in Table 2.
Memory/Register Commands
Display or change the contents of:
• Memory
• 8088 Registers
• BOBB Status flags
• BOBB Input pins
• BOBB 110 ports
• ICE·BB Pseudo·Registers (e.g. emulation timer)
1. A set of address values. Break on a set of address
values has three valuable features:
a. Break on a single address.
b. The ability to set any number of breakpoints within
a limited range (1024 bytes maximum) of memory.
Memory Mapping Commands
Display, declare, set, or reset the ICE·BB memory mapping.
c. The ability to break in an unlimited range. Execution is halted on any memory access to an address
greater than (or less than) any 20-bit breakpoint
address.
.
Symbol Manipulation Commands
Display any or all symbols. program modules, and program
line numbers, and their associated values (locations in
memory).
2. A particular status of the 8088 bus (one or more of:
memory or 110 read or write, instruction fetch, halt, or
interrupt acknowledge).
Set the domain (choose the particular program module) for
the line numbers.
3. A set of data values (features comparable to break on
a set of address values, explained in point one).
Remove any or all symbols, modules, and program statements.
Define new symbols as they are needed In debugging.
Change the value of any symbol.
4. A segment register (break occurs when the register. is
used in an effective address calculation).
TYPE
An external breakpoint match output for user access is
provided on the buffer box. This allows synchronization
of other test equipment when a break occurs.
ASM
Assign or change the type of any symbol in the symbol table.
Disassemble user program memory into ASM-86 Assembler
mnemonics.
Tracepoints - The ICE-88 module has two tracepoint
registers which establish match conditions to conditionally start and stop trace collection. The trace information is gathered at least twice per bus cycle, first
when the address signals are valid and second when
the data signals are valid. If the 8088 execution queue is
otherwise active, additional frames of trace are collected.
PRINT
Display the specified portion of the trace memory.
LOAD
Fetch user symbol table and object code from the input file.
SAVE
Send user symbol table and object code to the output .file.
LIST
Each trace frame contains the 20 addressldata lines
and detailed information on the status of the 8088. The
trace memory can store 1,023 frames, or an average of
about 300 bus cycles, providing ample data for
determining how the 8088 was reacting prior to
emulation break. The trace memory contains the last
1,023 frames of trace data collected, even if this spans
several separate emulations. The user has the option of
displaying each frame of the trace data or displaying by
instruction in actual ASM-86 Assembler mnemonics.
Unless the user chooses to disable trace, the trace
information is always available after an emulation.
Send a copy of all output (including prompts, input line
echos, and error messages) to the chosen output device (e.g',
disk, printer) as well as the cbns018.
EVALUATE
Display the value of an expression in binary, octal, decimal,
hexadecimal, and ASCII.
SUFFIX/BASE
Establish the default base for numeric values in input
textfoutput display (binary, octal, decimal, or hexadecimal).
CLOCK
Select the internal (ICE·BBprovided, for stand·alonemode
only) or an external (user-provided) system clock.
RWTIMEOUT
Allows the user to time out READ/WRITE command signals
based on the time taken by the 8088 to access Intellec
memory or diskette memory.
Interrogation and Utility
Interrogation and utility commands give the user convenient access to detailed information about the user
program and the state of the 8088 that is useful in
debugging hardware and software. Changes can be
made in both memory and the 8088 registers, flags,
input pins, and 110 ports. Commands are also provided
for various utility operations such as loading and saving
ENABLEIDISABLE ROY
Enable or disable logical AND of ICE·BB Ready with the user
Ready signal for accessing Intellec memory, ICE memorY,'or
diskette memory.
Table 2. Summary of Basic ICE·S8 Interrogation and
Utility Commands.
16-46
AFN0145A
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ICE-88™ IN-CIRCUIT EMULATOR
DIFFERENCES BETWEEN ICE-88™
EMULATION AND THE 8088
MICROPROCESSOR
DC CHARACTERISTICS OF ICE-88™
.
USER CABLE
1. Output Low Voltages [VodMax) = 0.4 VI
10dMln)
The ICE·88 module emulates the actual operation of the
8088 microprocessor with the following exceptions:
ADO·AD?, A8·A15, SSO,
A16/S3·A19/S?, RD,
LOCK, OSO, OS1, SO, 81, 82,
WR, M/iO, DT/A, DEN, ALE,
INTA
.
• The ICE·88 module will not respond to a user system
NMI or RESET signal when it is out of emulation.
• Trap is ignored in single step mode and on the first
instruction step of an emulation.
• The MINIMAX line, which chooses the "minimum" or
"maximum" configuration of the 8088, must not
change dynamically in the user system.
8mA
(16mA @ 0.5V)
HLDA
5mA
MATCHO OR MATCH1 (on
buffer box)
16 mA
2. Output High V!)ltages [VoH(Mln) = 2.4 V]
10H(Mln)
• In the "minimum" mode, the user HOLD signal must
remain active until HLDA 'is output by the ICE·88
emulator.
ADO·AD?, A8·A15
A16/S3·A19/S?, SSO, RD,
LOCK, OSO, OSl, So, 81, 82,
WR, MilO, DTlR, DEN, ALE,
INTA
HLDA
• The RO/GT lines in the "maximum" configuration are
not supported.
The speed of run emulation by the ICE·88 module
depends on where the user has mapped his memory. As
the user prototype progresses to include memory,
emulation becomes real time.
MATCHO OR MATCHl (on
buffer box)
-2.0mA
-3.0mA
-0.8mA
3. Input Low Voltages [V1L(Max)= 0.8V]
Memory
Mapped To
ADO·AD?
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (O.l"f to GND)
Estimated Speed
User System
100% of real time", up to 5 MHz
clock
ICE
2 wait states per 8088·controlled
bus cycle
4. Input High Voltages [V1H(Mln) = 2.0 V]
Intellec
Approximately 0.02% of real time
at 5 MHz clock
Diskette
""
ADO·AD?
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1"F to GND)
IIH(Max)
• 100% of real time is emulation at the user system clock rate
with no wait states.
•• The emulation speed from diskette is comparable to Intel lee
memory, but emulation must wait when a new page is
IldMax)
-0.2mA
-O.4mA
-0.8mA
-1.4mA
-3.3mA
80"A
20"A
60"A
-O.4mA
-1.1 mA
5. RO/GTO, RO/GT1 are pulled up to +5V through a
5.6K ohm resistor. No current is taken from user
circuit at Vcc pin.
accessed on the diskette.
16-47
AFN-0145A
inter
ICE-88™ IN-CIRCUIT EMULATOR
SPECIFICATIONS
Emulation Clock
Operating Environment
User system clock up to 5 MHz or 2 MHz ICE-SS
internal clock in stand-alone mode
ReqLl\red Hardware
Intellec microcomputer development system with:
1. Three adjacent slots for. the ICE-SS module. (Series 11
requires Model 201 Expansion Chassis).
2. 64K bytes of Intellec memory. 11 user prototype program memory is desired, additional memory.above
the basic 64K is required.
System console
Intellec diskette operating system
ICE-SS module
Physical Characteristics
Printed Circuit Boards
Width: 12.00 i.n (30.4S em)
Height: 6.75 in (17.15 cm)
Depth: 0.50.in (1.27 cm)
Packaged Weight: 9.00 Ib (4.10 kg)
Electrical' Characteristics
DC Power
Required Software
System monitor
ISIS-II, version 3.4 or subsequent
ICE-SS software
Vce =. +5V +5%-1 %
Ice = 15A maximum; 11 A typical
Voo= +12V±5%
.
100 = 120mA maximum; SOmA typical
Vss '" -10V±5% or -12V±5% (optional)
Iss =25mA maximum; 12mA typical
Equipment Supplied
Environmental Characteristics
Printed circuit boards (3)
.'
Interface cable and emulation buffer module
Operator's manual
ICE-SS software,diskette-pased
Operating Temperature: 0' to 40 'c
Operating Humidity: Up to 95% relative humidity without condensation.
ORDERING INFORMATION
Part Number
Description
MDS-88'ICE'
BOBS CPUin'circuit emulator
'MDS is an ordering code only and is not used as a produbt nam~ or trademark. MDS® is a registe'red trademark of Mohawk Data Science
Corporation.
16-4S
Prototype
Microcomputer Kits
17
inter
SDK-C86
MCS-86™ SYSTEM DESIGN KIT
SOFTWARE.AND CABLE INTERFACE TO
INTELLEC® DEVELOPMENT SYSTEM
• Provides the Software and Hardware
Communications Link Between an
Intellec® Development System and the
SDK-86
• Enhances and Extends the Power and
Usefulness of the SDK-86
• Intellec® System Files can be Accessed
and Down-Loaded to the SDK-86
Resident Memory
• Allows the SDK-86 to Become an
Execution Vehicle for ISIS-II Developed
8086 Object Code Using the Series II
8086/8088 Software Development
Packages
• Data in SDK-86 Memory can be
Uploaded and Saved in Intellec®
System Files
• All SDK-86 Serial Port Mode Commands
Become Available at Console of the
Intellec® System
The SDK-C86 product provides the software and hardware link for using the SDK-86 monitor in conjunction
with an Intellec® Development System while adding features of data transfer between SDK-86 memory and Intellec® System files. The user may enter programs and data into the SDK-86 and then save them on a diskette.
Also, programs and data may be created on the Intellec® System uS;,lg the Series 118086/8088 Software Development Packages, then loaded into the SDK-86 for testing and checkout. This provides a real time execution
environment of the SDK-86 as a peripheral to the Intellec® System.
© Intel Corporation 1980
SDK-C86
HARDWARE
Th.ere are two serial ports on the I ntellec® System back
panel, TTY and CRT. Assuming that one of the ports is
used for the Intellec® console, the SDK-C86 cable can
plug into the unused port. The SDK-86 is jumper
selectable to accept either the CRT (RS232) orTTY (20mA
current loop) signals.
The edge connector on the SDK-86 has the MUL TIBUS"
form factor. No signals are connected to the fingers
except the power supply traces. Therefore, the SDK-86
can plug directly into the Intellec® motherboard to obtain
power while using the SDK-C86 cable as the communication link.
• Upload/Download: In this mode the SDK-C86 software,
in the Intellec®, recognizes the mnemonic for Upload or
Download from the terminal. It "translates" the
Download command to an R (Read hexadecimal tape)
command and the Upload command to a W (Write
hexadecimal tape). The Rand W commands are then
passed on to the. SDK-86 monitor. Using these paper
tape commands allows for a checksummed transfer of
data between the Intellec® and the SDK-86 memory.
COMMAND SUMMARY
• Reset - starts the SDK-86 monitor.
• Execute with Breakpoint (G) Allows you to execute a user program and cause it to halt at a predetermined program step - useful for debugging.
SOFTWARE
Two programs must be invoked to operate in the SDK-86
slave mode. One program runs on the SDK-86, and
another runs in any ISIS-II environment that includes a
diskette drive.
• Single Step (N) - allows you to execute a user program
one instruction at a time - useful for debugging.
The serial I/O monitor is installed on the SDK-86 and
operates as though it was talking to a terminal. The
software in the Intellec® allows the Intellec®, with a
console device, to behave as if it were a terminal to the
SDK-86.
• Substitute Memory (S, SW) - allows you to examine
and modify memory locations in byte or word mode.
• Examine Register (X) - allows you to examine and
modify the 8086's register contents.
The SDK-C86 software program in the Intellec reads the
console input device, then passes the character to the
SDK-86 through the serial port. It also receives the
characters from the SDK-86 and displays them at the
console output device. Besides the basic transfer
function, this program also recognizes and performs the
Upload and Download functions.
• Block Move (M) - allows you to relocate program and
data portions in memory.
• Input or Output (I, IW, 0, OW) -allows direct control of
the SDK-86's I/O facilities in byte or word mode.
• Display Memory (D) - allows you to print or display
large blocks of memory information in HEX format.
COMMAND MODES
• Load (L) - allows you to load hex format object files
into SDK-86 memory from an Intellec.
• Transparent: In this mode, the SDK-C86 software
passes all characters through without any processing.
All the commands of the SDK-86 monitor (except paper
tape commands) are available and will function in
exactly the same manner as if the terminal were
attached directly to the serial port of the SDK-86.
• Transfer (T) - allows you to save contents of SDK-86
memory in a hex format object file in the Intellec.
SERIAL~
PORTS
CABLE
--A"",=======:::::'::==:::::=:;iI"
~______~~
INTELLEC®
DEVELOPMENT
SYSTEM
CRT OR TTY
GD"...,"
SDK-86/lntellec® Slave Mode Configuration
17-2
-
SERIAL
PORT
SDK-86
SDK-a6
MCSm86™ SYSTEM DESIGN KIT
o Wire Wrap Area for Custom Interfaces
• Complete Single Board Microcomputer
System Including CPU, rJlemory, and I/O
13
• Easy to Assemble Kit Form
• High Performance 808616-Bit CPU
III
• Interfaces Directly with TTY or CRT
Extensive System Monitor Software in
ROM
Comprehensive Design Library
Included
• Interactive LED Display and &'eyboard
The SDK-86 MCS-86 System Design Kit is a complete single board 8086 microcomputer system in kit form. It contains
all necessary components to complete construction of the kit, including LED display, keyboard, resistors, caps, crys·
tal, and miscellaneous hardware. Included are preprogrammed ROMs containing a system monitor for general soft·
ware utilities and system diagnostics. The complete kit includes an 8-digit LED display and a mnemonic 24-key key·
board for direct insertion, examination, and execution of a user's program. In addition, it can be directly interfaced
with a teletype terminal, CRT terminal, or the serial port of an Intellec system. The SDK-86 is a high performance proto·
type system with designed·in flexibility for simple interface to the user's application.
17-3
SDK·86
FUNCTIONAL DESCRIPTION
A block diagram of the 8086 microprocessor Is shown In
Figure 2.
The SDK-86 is a complete MCS-86 microcomputer system on a single board, In kit form_ It contains all necessary components to build a useful, funCtional system.
Such items as resistors, caps, and sockets are Included.
Assembly time varies from 4 to 10 hours, depending on
the skill of the user. The SDK-86 functional block diagram is shown in Figure 1.
System Monitor
A compact but powerful system monitor is supplied
with the SDK-86 to provide general software utilities and
system diagnostics. It comes in preprogrammed read
only memories (ROMs).
Communications Interface
8086 Processor
The SDK-86 is designed around Intel's 8086 microprocessor. The Intel 8086 is a new generation, high performance microprocessor implemented in N-channel, deple- .
tion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor
features attributes of both 8-bit and 16-bit microprocessors in that it addresses memory as a sequence
of 8-bit bytes; but has a 16-bit wide physical path to
memory for high performance. Additional features of
the 8086 include the following:
• Direct addressing capability to one megabyte of
memory
• Assembly language compatibility with 8080/8085
• 14 word x 16-bit register set with symmetrical operations
• 24 operand addressing modes
• Bit, byte, word, and block operations
• 8 and 16-byte signed and unsigned arithmetic in
binary or decimal mode, including multiply and divide
• 4 or 5 or 8 MHz clock rate
The SDK-86 communicates with the outside world
through either the on-board light emitting diode (LED)
display/keyboard combination or the user's TTY or CRT
terminal (jumper selectable), or by means of a special
mode in which an Intellec development system
transports finished programs to and from the SDK-86.
Memory may be easily expanded by Simply soldering in
additional devices in locations provided for this purpose. A large area of the board (22 square inches) is laid
out as general purpose wire-wrap for the user's custom
interfaces.
Assembly
Only a few Simple tools are required for assembly: soldering iron, cutters, screwdriver, etc. The SDK-86
assembly manual contains step-by-step instructions for
easy assembly with a minimum of mistakes. Once construction is complete, the user connects his kit to a
power supply and the SDK-86 is ready to go. The monitor
starts immediately upon power-on or reset.
Commands - Keyboard mode commands, serial port
commands, and Intellec slave mode commands are
summarized In Table 1, Table 2, and Table 3, respectively. The SDK-86 keyboard Is shown in Figure 3.
CONTROL
LINES
CONNECTOR
ADDRESS
BUS EXPANSION
CONNECTOR
I
BAUD RATE ~----_I
GENERATOR
L,-=c::..,...J
LED DISPLAY
Figure 1_ SDK-06 System Design Kit Functional Block Diagram
17-4
SDK·86
Documentation
In addition to detailed information on using the monItors, the SDK·86 user's manual provides circuit dia·
grams, a monitor listing, and a description of how the
system works. The complete design library for the
SDK·86 is shown in Figure 4 and listed In the speclflca·
tions section under Reference Manuals.
EXECUTION UNIT
8US INTERFACE UNIT
REGISTER FILE
I R~~~~;t,rI~~E I
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5 WORDS)
DATA,
POINTER, ANO
INOEX REGS
(8 WORDS)
Figure 4. SDK·86 Design Library
,..--""''''--,...- SHE/57
Table 1_ Keyboard Mode Commands
A'rs.
A,$tS3
Command
Operation
FLAGS
iNfA.RD.WR
3
3
Reset
Starts monitor.
Go
Allows user to execute user
program, and causes it to halt
at predetermined program
stop. Useful for debugging ..
Single step
Allows user to execute user
program one instruction at a
time. Useful for debugging.
Substitute
memory
Allows user to examine and
modify memory locations in
byte or word mode.
Examine
register
Allows user to examine and
modify 8086 register contents.
Block move
Allows user to relocate pro·
gram and data portions in
memory.
Input or output
Allows direct control of
SDK·86 I/O facilities in byte or
mode.
•
DTlR,DEIii,AlE
a·BYTE
INSTRUCTION
QUEUE
T~t ___ r------~~------~
INT--_
NMI---
CONTROL & TIMING
HOLO--HlDA,_--.-.__- .__- . -__- .__"",,",
elK
RESET
READY
Figure 2. 8086 Microprocessor Block Diagram
Table 2. Serial Mode Commands
SYSTM
RESET
INTR
+
REG
C
liP
D
E
IFL
F
8
IW/CS
9
OW/DS
4
IB/SP
5
6
7
OB/BP
MV/SI
EW/DI
1
ER/BX
2
GO/eS
ST/DX
0
EB/AX
A
IISS
Command
Operation
Dump memory
Allows user to print or display
large blocks of memory infor·
mation in hex format than
amount visible on terminal's
CRT display.
Start/continue
display
Allows user to display blocks
of memory information larger
than amount visible on ter·
minai's CRT display.
Punch/read
paper tape
Allows user to transmit fin·
ished programs into and out of
SDK·86 via TTY paper tape
punch.
B
IES
3
Figure 3. SDK·86 Keyboard
17-5
SDK·86
8086 INSTRUCTION SET
Table 4 contains a summary of processor instructions
used for the 8086 microprocessor.
Table 4. 8086 Instruction Set Summary, .
Mnemonic and
Description
Instruction Code
Instruction Code
Data Transfer
10V = 11m:
t a, 4.3
7 I Ii" 3 2 1 0
Register/memory lolllam register
Immediate 10 regislerlmemory
tmmedialelo register
Memory It. accumulator
II 0 0 '0 1 0 d w Imod
reg
Z I'D
1010000 w
7 Iii" 3 Z
'0
71 Ii" 3 2 1 a
rim
110001 t w moo 0 n 0 rim
1011 w reg
data
addr-Iow
Accumulator 10 memory
data itw·'
dala il
w~l
addr-high
adar-h!gh
Register/memory
01010lell
Segment register,
000 reg. 1 10
POP
= Pap:
Register/memory
10001 111
Regisler
01011 fell
Segment/tgister
xeMS
s
1000011 w mod
Aegisterwilhaccumulalor
1 0010 reg
III = Inpul
]-,110010 w
!
Variable pori
\"
I
10110 w
rell
data
10 0 1 1 1 1 1 1
~:"'!-:.;.:;:.:~;"-:"-::'+=mC:-odC:'-='-='-',C:,m:-i
I
11 t-, 0'1 1 w
1101,0100
11110 II W
1 I 11 0 1 1 w
"010101
10011 000
100 I 100 I
7'5431:11
clala il $:w-O,
:t-===.:..J
~'i'±'±, ±lOt.tt:=::;;;::J~,;;:,,~,~ifw~'
~::-_~::~p~~a(~~:i~~:rd:ubtract
SIl~/SAl·Shil1togical/arithmetic left
SIIR·Shlllloglcal righl
SAR=Shil1arithmelicrighl
RDloRotalelefl
ROR-Rotalerrght
RCl-Rotate through carry flag tell
RCR-Rotale through carry right
POlt
1110011 w
111 0 1 II w
11010111
1 0 0 0 1 1 0 I mod
110 DO 1 0 1 mod
11000 tOO mod
port
AND
r~
modI 0 1 rim
00001010
mod 1 10 rim
mod 1 1 I rim
000010'0
r~
r~
<
tIll 011
, 1. 0 I 0 0 v
110100 v
110100 v
1 10-' 0 0 y
11 D·' 0 0 v
110100 v
1 1010 0 ~
W
W
w
w
w
w
modO 1 0
mod 1 00
modI 0 I
mod ,"
modO 0 0
modO 0 1
w modO I 0
w modO 1 1
rim
rIm
11m
rim
rIm
rim
rim
And:
Reg_lmemo,~ and leglster 10 either ~'~':.;'~'~'~'~';;,wofm;:;'e.',.;,,,;;,,,,;;;"m~_--'~--'r--,c-,.,,..-...,....,
rim
rIm
rim
::::::::: ::
\ 0 0 I 11 1 1
:::i~:~:::~ory
F.;~:~:"':~:"':~:":ofm;:;';.d1"""?-,~,=,,,",'m9_"C,.:',::::~:a:.~_~,+--"""'' ' ' ' ' .' '.'....J
~:,:t;r ~;:~:~:':Onnd I~e:li:~:; no rllullr..,-=,-=,-=,7,-:-,::-,w-'-m-.''--,,-,-,-'-'m-O
100 I' II 0
10'01'11.0.0
100 II 101
::::::::: ::::
:~: :::i;:~:;:~ory F.:~;~:~;~:~;::=~:~m;;;od~'~',,:;,:~,:,;;'m9_,;:',,~:'~i:::,._.,'+---""C:"':':"':"':.:.'...J
OR - Or:
Reg_lmemoryandregistertoeither
tmmediatelo register/memory
Immediate to accum'ulator
ArithmetiC
ADD = Add:
:::i~:::;:~ory
71543210
Logic
rim
OUT = Oulput
Reg.lmemorywithregisterloeilher
rim
rim
tmmedlate With accumulatOr
AAI-ASCII adjust for subtract
"DT-In~ert
Filled pall
:::::::: ::
±,
7154321D
1000regl111
Registerlmemorywllhregisltr
. XLAT~Translate byte to. Al
lEAsload EA to register
LDlsload pointer to OS
LEI~load pointer to ES
LA"f~load AH with !tags
lI\"f~StDle AH into lIags
'UlHFspush lIags
roPF=Pop flags
DOt 1 1 0 d w mod reg
, 0 0000 s w mod I "
modO 0 0 rim
Exchln,l:
fixed porI
Variable port
11&43210
Regjsteflmemor~ and regisler
Immediate With register/memory
I.Ul-lnleger multiply (signed)
AAM-ASClI adjust tor multiply
DIV-Oi~ide (unSigned)
IDIV-Inleger divide (signed)
A"g-ASCII adjust lor divide
CIW-Convert b~te to word
CWD·Convert word to double'word
PUBH = Pulh:
Register
CMP=Colllp.n:
~'~'~'~'~'~'I':::w~m~,[,;,,~,~"m!:l_---'-:-_r--:-:c"-~
,;,:
F.;~:~:~:~:;': ;;.:¥m~'::.:dO;,:';,:,~:"":,;;"m9_.,,,"'::,:~~;a:,.w_'"+-""""-""-'''''w",.,''-.1'
000010 d w mod reg rim
'000000 w modO 0 I rIm
0000110 w
data
data
data IIw·1
datailw-'
XOR = Exclu,IVlII':
Rell.lmemory and register to either
Immediate to register/memory
F.'. ,'-i;'-i;'~'~Od,..w~m~od~"'1;'.;';;;'m~_-"7"--r_=='T1
Fi'",';";"~',..oo,...~m;;;":.;'..;',,,:;~,~:,;;'m9~;:;,,,,~,,,=;-+--,"~=".::.iI.::.W'':'''...J
AOC = Add wllh ;my:
Reg.lmemorywithr~gisler.loeither
Immediate to registerlmemor~
Immediate to accumulator
INC = Incnl'llllnl:
Register/memory .
RegiSI~r
AM-ASCII adjusllor add
W .. o.clmaladjust tor add
lUI
000,100 d w mod reg rim
100000 s w modO 1 0 rim
0001010 w
data
1
0
0
0
data its:w-01
dataitw·1
SIring Manipulation
I 1 1 1 I \ W mod 0 0 0 rim
1 0 0 0 reg
0 I 101I 1
0 10 0 1 1 ,
.1.1.1;'0()'lz
= au.ll'Kt:
Reg./memory and regisler 10 either
:::::::::
:~:: ::i;:::;:~ory
F.'~'~'~'-i;'~';:.';;.w¥m;;;.~':.::,,,,,:-'~'m~_--':;:-_r-==:7.l
MOYS= Move byte/word
CMPS = Compare bytelword
SCAS = Scan byte/word
lOOS = Load byte/~d to AUAX
1'0,100' 0 w
10 100 1 , W
I 0 1 0 1 1 ',w
, ,0 1 0 1 , 0 w
sTDS:,~:Stor:bytEiiwd Ii"'; AUA"";'
'·0" 0 I 0 I 'w
F.;"':"':';:';:';:~:~:+m;;:':.d1~'~':~l:",lm"=-!_~,,::;t:a~i:a~"':'l-t-",,,,,,=-,'"I'",.'""",,,'
Con.trol Tra!"sler
CAll ~ CIII:
Oir.c~
DEC ~ OIenmlnl:
Register/memory
Register
IiIEA-Change sign
25
11 III I 1 W modO 0 1 rIm
0'1001 reg
1II1101lwimodOll rim
Within segment
dlsp-hlQh
Indir~t""'Jhlfl_segmen.'
Dlfec\ intersegrn_enl'Indirectlntersegment
ollseHow
·'seg·low
1 I 1 1 1 111 mod 0 11 rim
o!lset-hlgh
seg-hlQh
continued
17-6
SDK·a6
Table 4. 8086 Instruction Set Summary (Continued)
Mnemonic and
Description
Mnemonic and
Description
Instruction Code
Jlp· Uncandlllon.1 JLlmp:
715432'10
O,ree! wnhm Homen!
1,1101001
Direct wllh'IlHgmenl·shorl
711543210
I
Indlrectwllhln SC\lmenl
dlsp·~IOh
7154321011543210
J
JNS Jump on nol $'lIn
oUseI·low
I
OUSeHIQh
I
uro/eQual
~-~~
Inclueel mlersegmenl
11 I 1 1 11 Illmod 101 "m
l~ro
JCJl·Jump on ex
dlSp
J
11100010
lOOH/lDOP!-LoopwMllewOlcQual
LDBrllllOOP'U lOop.,.h,'enol
mod 1 0 0 rim
1111010101
1011110011.
lOOP loop ex limes
dlsp
11 1 1 1 1 1 1
Olrecllnlersegmenl
11H3210
!lISp· low
11101011
Instruction Code
11100001
11100000
11100011
I
INT
Inl.rrupt
11001101
TvpespeCITlcd
TvpeJ
I~ET
type
11001100
rllTO Interrupt on
o~erllow
\11001110 \
1'100111'1
Interrupl lelum
Processor Control
ClCClearcarry
11111000
eMe Complemenl cal1Y
11110101
STeSelcarry
11111001
elOCleardlteC1l0n
11111100
STO-SeldlreClloll
11111101
eLI Clearlnlerrupl
11111010
Sf!
Set
ml~f(upl
11111011
liLT Hall
1111101001
WAIT Wall
11 0011011
11 1 0 1 1 x x _I mod _
ESC
I
fs~ape
[Iotllernal
de~lnl
lOeKBuslockprelrx
111110000
~
_ rim
I
Notes
Al" 8-bit accumulator
AX" 16-btI accumulator
ex" Count register
OS" Data segment
ES" Extra segment
Abovelbelow refers to unSigned value
Greater"' more positive:
less" less positive (more negative) signed values
(I
d
=,
then "10" reg; if d = a then "from" reg
if w" 1 then word instruction: if w
=
., s.w = 01 then 16 bits 01 Immediate data form the operand.
"s:w= 11 then an immedIate data byte IS Sign extended 1~
form the 16·bit operand.
11'1=0 then "count" =1, il '1=0 then ·'counl'· In (~l)
x=don·' care.
"v = 0 then ·'counr' = 1: II '1=1 then '·count'· In (eLl register.
l IS used lor stnn~ primitives lor comparison With IF FLAG
0 then byte instruction
SEGMENT OVERRIDE PREFIX
001 reg 110
if
if
if
il
mod"
mod"
mod"
mod ~
11 then
00 then
01 then
10 then
if rim" 000 then
if rim" 001 then
if rim" 010 then
if rim = 011 then
if rIm = 100 then
if rim" 101 then
if rim" 110 then
if rim" 111 then
DISP follows 2nd
REG IS assigned accordmg to the loll OWIng table:
rim is treated as a REG field
III-Bill_ ~ II
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 DI
DISP " 0·. disp·low and disp·high are absent
OISP " disp·low sign·extended to 16-bits. disp·high IS absent
OISP = disp·high: dlsp·low
EA" (BX) + (51) + OISP
EA '" (BX) + (01) + DISP
EA = (BP) + (51) • DISP
EA" (BP) + (01) + OISP
EA = (51) + DISP
EA ~ (01) .. DISP
EA " (BP) + DISp·
EA" (BX) + DISP
byte of instruction (before data if reqUIred)
~
Segment
00 ES
01 CS
10 SS
11 OS
Instructions which relerence the flag register Ii Ie as a l&bit object use the symbol FLAGS to
represent the liIe:
FLAGS
·except if mod" 00 and rIm
II-BIII_ ~ 01
000 AL
001 CL
010 OL
011 BL
100 AH
101 CH
110 OH
111 BH
110 then EA "disp·high: disp·low
~
X:X:X:X:(OFI:(DFI:IIF):ITFI:(SFI(ZFI.X:(AFIX(PF):X:(CF)
Mnemonics 'c, Intel, 1978
SPECIFICATIONS
AddreSSing
Central Processor
ROM - FEOOO-FFFFF
RAM - 0-7FF (800-FFF available with additional
2142's)
CPU - 8086 (5 MHz clock rate)
Nole
The wlre·wrap area of the SDK·86 PC board may be used for additional
custom memory expansion.
Nole
May be operated at 2.5 MHz or 5 MHZ, jumper selectable, for use with
8086.
Input/Output
Memory
Parallel - 48 lines (two 8255A's)
Serial - RS232 or current loop (8251A)
Baud Rate - selectable from 110 to 4800 baud
ROM - 8K bytes 2316/2716
RAM - 2K bytes (expandable to 4K bytes) 2142
17·7
SDK·86
Interfaces
Electrical' Characteristics
Bus - All signals TIL compatible
Parallel 1/0 - All signals TIL compatible
Serial 1/0 - 20 mA current loop TTY or RS232
DC Power Requirement
(Power supply not included in kit)
Note
The user has access to all bus signals which enable him to design custom system expansions into the kit's wire-wrap area.
Interrupts (256 vectored)
Maskable
Non-maskable
TRAP
Current
3.SA
O.3A
(VTTY required only if teletype is connected)
Environmental Characteristics
Operating Temperature -
DMA
Hold Request input.
0-50·C
Jumper selectable. TTL compatible
Reference Manuals
9800697A SDK-86 MCS-86 System Design Kit
Assembly Manual
9800722 - MCS-86 User's Manual
9800640A - 8086 Assembly Language Programming
Manual
8086 Assembly Language Reference Card
Software
System Monitor - Preprogrammed 2716 or 2316 ROMs
Addresses - FEOOO-FFFFF
Monitor 1/0 - Keyboardldisplay or TIY or CRT (serial
1/0)
Physical Characteristics
Width Height Depth Weight -
Voltage
VCCSV±S%
VTTy-12V±10%
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers'
Avenue, Santa Clara, California 95051.
13.5 in. (34.3 cm)
12 in. (30.5 cm)
1.75 in. (4.45 cm)
approx. 24 oz. (3.3 kg)
ORDERING INFORMATION
Part Number
Description.
SDK-86
MCS-86 system design kit
17-8
SDK-8S
MCS-8S™ SYSTEM DESIGN KIT
• Complete Single Board Microcomputer
System Including CPU, Memory, and I/O
• Easy to Assemble, Low Cost, Kit Form
• Popular 8080A Instruction Set
• Interfaces Directly with TTY
• Extensive System Monitor Software in
ROM
• High Performance 3 MHz 808SA CPU
(1.3 J.Ifi Instruction Cycle)
• Interactive LED Display and Keyboard
• Comprehensive Design Library
Included
• Large Wire-Wrap Area for Custom
Interfaces
The SDK·85 MCS·85 System Design Kit is a complete single board microcomputer system in kit form. It contains all
components required to complete construction of the kit, including LED display, keyboard, resistors, caps, crystal,
and miscellaneous hardware. Included is a preprogrammed ROM containing a system monitor for general software
utilities and system diagnostics. The complete kit includes a 6·digit LED display and a 24·key keyboard for a direct in·
sertion, examination, and execution of a user's program. In addition, it can be directly interfaced with a teletype ter·
minal. The SDK·85 is an inexpensive, high performance prototype system that has designed·in flexibility for simple in·
terface to the user's appl ication.
17-9
SDK·85
FUNCTIONAL DESCRIPTION
The SDK-85 is a complete 8085A microcomputer system
on a single board, in kit form_ It contains all necessary
components to build a useful, functional system_ Such
items as resistors, capacitors, and sockets are included.
Assembly time varies from three to five hours, depend,ng on the skill of the user. The S~K-85 funGtional olock
diagram is shown 'n Figure 1.
808SA Processor
ROM/IO (8355)
EPROM/IO (8755)
ADDRESS
DECODER
Addressing - The 8085A uses a multiplexed data bus.
The 16-bit address is split between the 8-bit address bus
and the 8-bit address/data bus. The on-chip address
latches of 8155/8156/8355/8755 memory products allows
a direct interface with the 8085A.
System Monitor
The SDK-85 is designed around Intel's 8085A microprocessor. The Intel 8085A is a new generation, complete
8-bit parallel central processing unit (CPU). Its instruction set is 100% software upward compatible with the
8080A microprocessor, and it is designed to improve the
present 8080A's performance by higher system speed.
Its high level of system integration allows a minimum
system of three IC's: 8085A (CPU), 8156 (RAM), and
8355/8755 (ROM/PROM). A block diagram of the 8085A
microprocessor is shown in Figure 2.
CPU
System Integration - The 8085A incorporates all of the
features that the 8224 (clock generator) and 8228 (system controller) provided for the 8080A, thereby offering
a high level of system integration.
A compact but powerful system monitor is supplied
with the SDK-85 to provide general software utilities and
system diagnostics. It comes in a pre-programmed
ROM.
Communications Interface
The SDK-85 communicates with the outside world
through either the on-board LED display/keyboard combination, or the user's TTY terminal (jumper selectable'
RAM/IO/COUNTER
KEYBOARD/DI$PlA Y
FOR BUS EXPANSION
ADDRESS
DATA
FIELD
FIELD
r-~~6--'ff
~
_____ J
8
r----'
INTERRUPT
INPUTS
I
8216
I
l - _____ .J
ADDRESS , - - - - ' ' ' ' - - ' - ' - , . - - - '
BUS
'--+-_~
~
L--L""'-.....,_ _ _ _- ' - - ' -_ _ _ _ _ _- '
-------,-,---+-
----'-'---+1I-
CONT~~~ r----"'~----'-- _ _ _ _ _ _ _ _ _ _ _ _ _ _'--_ _ _ _ _ __
r- - ~
L _ _ ....
OPTIONAL
A PLACE HAS HElN PROVIDED ON THE PC BOARD FOR THE DEVICE BUT THE
DEVICE IS NOT INCLUDE"D
Figure 1. SDK-aS System Design Kit Functional Block Diagram
17-10
DATA
BUS
SDK·85
INSIDE THE 8085:
500
'81
'81
REG,
0
REG.
18'
,(8)
REG.
L
'81
REG.
CYCLE
PROGRAM COUNTER
POWER{_ +5V
SUPPLY
_OND
'81
REG.
STACK POINTER
ENCODING
1161
(16)
INCREMENTER OECREMENTER
AD7,AOo
ADDRESS/DATA BUS
A1S-AS
ADDRESS BUS
•
•
REGISTER
ARRAY
SEVEN 8·BIT REGISTERS. SIX OF THEM CAN BE LINKED
IN REGISTER PAIRS FOR CERTAIN OPERATIONS.
8-BIT ALU.
•
•
16·BIT STACK POINTER (STACK IS MAINTAINED
OFFBOARD IN SYSTEM RAM MEMORY) .
16-BIT PROGRAM COUNTER.
Figure 2. SOSSA Microprocessor Block Diagram
Both memory and 1/0 can be easily expanded by simply
soldering in additional devices in locations provided for
this purpose. A large area of the board (45 sq. in.) is laid
out as general purpose wire·wrap for the user's custom
interfaces.
Commands - Keyboard monitor commands and teletype
monitor commands are provided in Table 1 and Table 2 reo
spectively.
Table 2. Teletype Monitor Commands
Assembly
Command
Only a few Simple tools are required for assembly;
soldering iron, cutters, screwdriver, etc. The SDK-85
user's manual contains step·by·step instructions for
easy assembly without mistakes. Once construction is
complete, the user connects his kit to a power supply
and the SDK-85 is ready to go. The monitor starts imme·
diately upon power·on or reset.
Display memory
Substitute memory
Insert instructions
Table 1. Keyboard Monitor Commands
Move memory
Command
Examine register
Operation
Reset
Go
Starts monitor.
Allows user to execute user pro·
gram.
Single step
Allows user to execute user pro·
gram one instruction at a timeuseful for debugging.
Substitute memory Allows user to examine and
modify memory locations.
Examine register
Allows user to examine and
modify 8085A's register con·
tents.
Vector interrupt
Serves as user interrupt button.
Go
Operation
Displays multiple memory loca·
tions.
Allows user to examine and
modify memory locations one
at a time.
Allows user to store multiple
bytes in memory.
Allows user to move blocks of
data in memory.
Allows user to examine and
modify the 8085A's register
contents.
Allows user to execute user
programs.
Documentation
In addition to detailed information on using the
monitors, the SDK-85 user's manual provides circuit dia·
grams, a monitor listing, and a description of how the
system works. The complete deSign library for the
SDK-85 is shown in Figure 7-11 and listed in the Specifi·
cations section under Reference Manuals.
17·11
SDK-SS
Figure 3. SDK-85 Design Library
SOSSA INSTRUCTION SET
Table 3 contains a summary of processor instructions
used for the SOSSA microprocessor.
Table 3. Summary of 808SA Processor Instructions
Mnemonic!
1
Description
Instruction Code2
1
I 1 Clock 3
07 06 Os 04 03 02 0, DO Cycles
MOVE, LOAD, AND STORE
Mnemonic!
LXI SP
MOVr1r2
Move register to register
MOV M.r
MOV r.M
0
1
Move register to memory
0
1
1
Move memory to register
0
1
D
MVt r
Move immediate register
0
0
D
0
MVI M
Move Immediate memory
LXI B
Load immediate
D
D
S
S
S
4
1
0
S
S
S
7
D
D
1
7
0
1
1 0
1 '. 0
'7
D
0
0
1
1
0
1
1
0
10 '
reglst~r
0
0
0
0
0
0
0
1
10
LXI D
Load Immediate register
Pair 0 & E
0
0
0
1
0
0
0
1
10
LXI H
load Immediate register
0
0
1
0
0
0
0
1
10
Pair,B & C
Pair H & L
1
Description
Inslructlon Code2
1
01 Clock 3
07 D6 Os 04 03 02 0, DO Cycles
Load immediate slack
pointer
0
0
1
1
0
0
0
INX SP
Increment stack pointer
0
0
1
1
0
0
DCX SP
Decrement stack
pOinter
0
0
1
1
1
0
1
10
1
1
6
1
1
6
JUMP
JMP
Jump unconditional
1
1
0
0
0
0
1
1
10
JC
Jump on carry
1
1
0
1
1
0
1
0
7110
JNC
Jump on no carry
1
1
0
1
0
0
1
0
7/10
JZ
Jump on zero
1
1
0
0'
1
0
1
0
7/10
JNZ
Jump on no zero
1
1
0
0
0
0
1
0
7110
0
1
0
7
JP
Jump on positive
1
1
1
1
0
0
1
a
7110
0
1
0
7
JM
Jump on minus
1
1
1
1
1
0
1
0
7/10
Load A Indirect
a o '0 a a
0 a 0 1 0
0 0. a 0 1
0
1
0
7
JPE
Jump on parity even
1
1
1
0
1
0
1
0
7/10
Load A indirect
0
0
0
1
1
0
1
0
7
JPQ
Jump on parity odd
1
a
0
0
1
a
7110
STA
St'ore A direct
0
0
1
1
0
0
1
0
13
PCHL
1
0
1
0
0
1
6
LOA
Load A direct
0
0
1
H & L to program
counter
1 1
1 '1
SHLD
Store H & L direct
0
0
LHlO
Load H & L direct
0
0
XCHG
Exchange D & E, H & l
registers
1
1
Push register pair B & C
on stack
1
1
0
0
0
1
0
1
12
PUSH D
Push register,pair 0 & E
on stack
'
1
1
0
1
0
1
0
1
12
PUSH H
Push register pair H & l
on stack
1
1
1
0
0
1
0
1
12
PUSH PSW
Push A and flags on
stack
1
1
1
1
0
1
0
1
12
POP B
Pop register pair B & C
off stack
1
1
0
0
0
0
a
1
10
POP 0
Pop register pair 0 & E
off stack
1
1
0
1
a a
0
1
10
pOP H
Pop register pair H & L
off stack
1
1
1
0
0
a
0
1
10
POP PSW
Pop A and flags off
stack
1
1 ,1
1
0
0
0
1
10
XTHL
Exchange top of stack.
H & L
1
1
1
SPHL
H & L to stack
1
1
1
STAX B
Store A indirect
STAX D
Store A Indirect
LDAX B
LDAX D
1
1
1
0
13
1
a
a a a
1
0
16
1
0
1
0
1
0
16
CAll
Call unconditional
1
1
0
0
1
1
a
1
18
1
0
1
0
1
1
4
CC
Callan carry
1
1
0
1
0
0
9/18
CNC
Call on no' carry
1
STACK OPS
PUSH B
p~inter
0
1
0
a
1
0'0
1
,
1
CALL
1
0
1 1
1• 0
1
0
0
9/18
CZ
Call on zero
,I
1
0
0
1
1
0
0
9/18
CNZ
Callan no zero
1
1
0
0
0
1
0
0
9118
CP
Cali on positive
1
1
1
1
0
1
0
0
9/18
CM
Callan minus
1
1
1
1
1
1
0
0
9118
CPE
Call on parity even
1
1
1
a
1
1
0
0
9/18
CPO
Callan parity odd
1
1
1
0
0
1
0
0
9/18
a
a
1
10
0
6/12
RETURN
RET
Return
1
1
0
a
1
0
RC
Return on carry
1
1
0
1
1
0
RNC
Return on no carry
1
1
0
1
0
0
0
0
6112
RZ
Return on zero
1
1
0
0
1
0
0
a
6/12
RNZ
Return on no zero
1
1
0
a
0
0
0
0
6112
RP
Return' on
posit'ive
1
1
1
1
0
0
0
0
6112
RM
RetUrn on minus .'
1
1
1
1
1
0
0
0
6/12
16
6
continued
17-12
SDK·85
Table 3; Summary of BOSSA Processor Instructions (Continued)
Mnemonlc1
I
Description
I
I
I Ctock3
Instruction Code2
RPE
Return on parity even
1 1
1
0
1
0
0
RPO
Return on parity odd
1
1
0
0
0
0
Restart
..
1 1 A
RESTART
R5T
I Cycles
D7 D6 Ds D4 D3 D2 D, DO
1
A
A
1
1
0
0
1
6112
6/12,
12
INCREMENT AND DECREMENT
Mnemonlc1
I
Description
I
D7 D6 DS D4 D3 D2 D, DO
ANAr
And register with A
1
0
1
0
0
5
5
5
4
XRAr
Exclusive Or register
with A
1
0
1
0
1
5
5
5
4
ORAr
Or register with A
1
0
1
1
0
5
5
5:
4
CMPr
Compare reg~sler:wl~h A
1
0
1
1 1
5
5
5
4 ..
0
1
1
1
1 0
1 0
0
1
1
1
1
0
'7
1
0
7
1
1
7
1
1
0
0
1
Increment register
0
0
0
0
0
1
0
0
4
ANAM
And memory with A
1
0
1 ,0
OCR r
Decrement register
0
0
1
4
XRA M
0
1
1
0
0
0
10
Exclusive Or memory
with A
1
1
1
1
0
Increment memory
0
0
0
INR M
0
0
il
OCR M
Decrement memory
0
0
1
1 0
1
Or memory with A
1
0
1
1
0
0
0
0
0
0
1
1
ORA M
Increment B & C
registers
0
1
10
INX B,
6
CMPM
Compare memory withA
1
Increment 0 & E
registers
0
0
0
1
0
0
1
1
6
ANI
And Immediate with A
0
1
1
INX 0
1
1
0
XRI
1
1
0
0
1
INX H
Increment H & L
registers
0
0
1
0
0
0
1
1
6
Exclusive Or immediate
with A
1
1
ORI
Or immediate with A
Decrement B & C
0
0
0
0
1
1
6
CPI
1
1
1
1
0
1
1
1
Decrement 0 & E
0
0
0
1
DCX H
Decrement H, & L
0
0
1
0
1
1
6
6
Compare immediate
with A
1
DCX 0
0 1
0" 1 .. 1
1
1
1
DCX B
0
0
0
0
0
0
1
0
0
0
1
0
0.' 1
1
1
ADD
ADDr
Add register to A
ADCr
Add" register to A with
carry
1
0
"1
0
0
a0
0
1
5
5
5
4
5
5
5
4
0.
1
0
0
0
0
1
1
0
'7
ADCM
Add memory to A with
carry
1
0
0
0
1
1
1
0
7
ADI
Add immediate to A
1
1
0
0
1
1
0
7
ACI
Add i~medlat.e to A
wltl) carry ..
1
1
0
0
0
1
1
0
7
DAD B
AddB&C10H&'L
q
DAD 0
AddD&E1oH&L
0
0
0
0
0
0
1
1
10
10
DAD H
AddH&LtoH&L
0
0
0
0
0
0
1
ADDM
DAD5P
. Add. memory. tl? A
Add stack pOinter to
H&L
ICyctes
LOGICAL
INAr
0
I Ctock3
Instruction Code2
I
7
7
7
i
1
0
0
: 7
1
1
1
4
1
1
1
4
0
1
1
1
4
1
1
1
1
4
ROTATE
RLC
Rotate A left
0
RRC
Rotate A right
RAL
Rotate A lelt through
carry
0
0
RAR,
-Rotate A right through
carry
0
SPECIALS
0
"
"0 ,0
0
0 "I
0 1 1
I' '0 1
1 1 1
1
CMA
Complement A
0
0
1
5TC
Set carry
0
0
1
0
1
CMC
Complement
DAA
Decimal adjust A
0
0
0
0
1
1
1
0
carry
1
1
1
1
4..
0
1
1
1
4
1
1
1
1
4
0
1
1
I'
4
"
',0'
10
INPUT/OUTPUT
IN
Input
1
1
0
1
1
0
1
1
10
OUT
Output
1
1
0
1
0
0
1 "I
10
'\
'I
1
1
1
0
1
1
4
1
1
1
1
1
4
0
1
0
1
0
1
0
0
1
" 0
0
0
0
0
4
0
1
0
1
0
5
0
0
0
1 0
1 1
0
0
0
4
0
0
4
SUBTRACT
5UBr
Subtract register from A
SBBr
Subtract register from A
with borrow
1
1
0
0
0
1
0
1
0
1
5
5
5
4
5
5
5
4
SUBM
Subtract memory from A
1
0
5BBM
Subtract memory from
A with borrow
1
0
SUI
Subtract immediate
from A
1
1
0
1
0
1
1
0
7
5BI
Subtract immediate
from A with borrow
1
1
0
1
1
1
1
0
7
0
0
1
0
1
1
0
7
1
1
1
1
0
7
CONTROL
"
EI
Enable interrupts
01
Disable interrupts
NOP
No-operation
HLT
Hall.: .
"
NEW 80.65 INSTRUCTIONS
RIM
Read interrupt mask
51M
Set interrupt mask
0
0
0
0
Notes
1. All mnemonics copyright © Intel Corporation 1977.
2. DDDorSSS: 6=000, C=OOI, 0=010, E=Ol1, H=100, L= 101, Memory = 110, A= 111.
3, Two possible cycle times. (6112) indicates instruction cycles dependent on condition flags.
SPECIFICATIONS
Addressing
Central Processor
ROM - 0000-07FF (expendable to OFFF with an addl·
tional 8355/8755A)
RAM - 2000-20FF (2800-28FF available with an addl·
tional 8155)
CPU - 8085A
Instruction Cycle Tcy - 330 ns
1.3 ,..s
Memory
ROM - 2K bytes (expandable to 4K bytes) 8355/8755A
RAM - 256 bytes (expandable to 512 bytes) 8155
Note
The wlre·wrap area of the SDK·85 PC board may be used for additional
custom memory expansion up to the 64K·byte addressing limit of the
80850\.
17-13
SDK~85
Input/Output
Physical CharacterIstIcs
Par.allel.~38 lines. (expandable. to]6 lines)
Serial·.;'" Through'SID/SOD ports of 8085A. Software
.
generated baud rate.
Baud Rate .... 110
. Width - 12.0 In. (30.5 em)
Height - 10 II). (25_4 em)
Depth- 0.50 in. (1.27 em)
Weight --approx~ 12 oz
Electrical CharacterIstics
Interfaces
DC Power Requirement (power supply not Included In
kit)
.
Bus - All signals TTL compatible
Parallel 1/0 -All signals TTL compatibleSerial 1/0 - 20 mA current loop TTY
,.',.
Voltag.
Current
1.3A
VCC 5V,;,5%
Note
Sy populating the buffer area of t~e board, the userhas access to all bus
signals that enable him to design custo.m system e~parislons Into the
kit's wire-wrap area.
...
0.3A
(VTTY required only if teletype
is connected) ,
VTTY-l0V:I: 10%
Environmental Characteristics
Interrupts
Operating Temperature - O-55°C
Three Le~l$
(RST 7.5) - Keyboard Interrupt
(RST 6.5) - TTL input
(INTR) - TTL Iflput
Reference Manuals
DMA
Hold Request - Jumper selectable.· TTL compatible
i n p u t . ·.
Software
System Monitor - Pre-programmed 8755A or 8355 ROM
Addresses - 00OO-07FF
... .
Monitor 1/0 - Keyboardldlsplay or TTY (serial 110)
9800451 - SDK-85 User's Manual (SUPPLIED)
9800386 - MCS-85 User's Manual (SUPPLIED)
9800301 - 8080j8085 Assembly Language Programming Manual (SUPPLIED)
.
8085/8080 Assembly Language Reference Card (SUP- ;
~~
.
.
Reference manuals are shipped with each product only
If deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue; Simla Clara, California 95051.
.
ORDERING INFORMATION
Part Number
Description
SDK-85
MCS-85 system design kit
..
-.;
11·14
.
inter
SDK-51
MeS-51 SYSTEM DESIGN KIT
• Complete single-board microcomputer
kit:
-
Intel 8031 CPU
-
ASCII keyboard and 24-character
alpha-numeric display
• Extensive system software in ROM:
- Single-line assembler and
disassembler
- System debugging commands
Go
Step
Breakpoints
-User-configurable RAM
• Interface software:
- Serial port
- Audio cassette
- Intellec® system
-
• User's guide, assembly manual, and
MCS-51 design manuals
.-
Wire-wrap area for custom
circuitry·
Serial and parallel interfaces
The SDK-51 MCS-51 System Design Kit contains all of the components required to assemble a complete
single-board microcomputer based on Intel's high-performance 8051 single-chip microcomputer. SDK-51
uses the external ROM version of the 8051 (8031). Once you have assembled the kit and supplied + 5V
power, you can enter programs in MCS-51 assembly languagemnemonics, translate them into MCS-51 object code, and run them under control of the system monitor. The kit supports optional memory and interface configurations, including a serial terminal link, audio cassette storage, EPROM program memory,
and Intellec® development system upload and download capability.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: intel, (ntellee, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are
implied.
© INTEL CORPORATION, 1980
AFN'()1792A
17-15
November 1980
162549
SDK·51
FUNCTIONAL DESCRIPTION
The 8031, 8051, and 8751 CPUs
The SDK-51 is a kit which includes hardware and
software components to assemble a complete
MCS-51 family single-board microcomputer. Only
common laboratory tools and test equipment are
required to assemble the kit. Assembly generally
requires 5 to 10 hours, depending on the experience of the user.
The 8031,8051, and 8751 CPUs each combine, on
a single chip, a 128 x 8 data RAM; 32 input/output
lines; two 16-bit timer/event counters; a fivesource, two-level nested interrupt structure; a
serial I/O port; and on-chip oscillator and clock circuits. An 8051 block diagram is shown in Figure 1.
The MCS·51 Microcomputer Series
MCS-51 is a series of high-performance singlechip microcomputers for use in sophisticated
real-time applications such as instrumentation,
industrial control and intelligent computer peripherals. The 8031, 8051, and 8751 microcomputers
belong to the 8051 family, which is the first family
in the MCS-51 series.
In addition to their advanced features for control
applications, MCS-51 family devices have a microprocessor bus and arithmetic capability such as
hardware multipy and divide instructions, which
make the SDK-51 a versatile stand-alone microcomputer board.
The 8031, the SDK-51's CPU, is a CPU without onchip program memory. The 8031 can address 64K
bytes of external program memory in addition to
64K bytes of external data memory. For systems
requiring extra capability, each member of the
8051 family can be expanded using standard memories and the byte-oriented MCS-80 and MCS-85
peripherals. The 8051 is an 8031 with the lower 4K
bytes of program memory filled with on-chip
mask-programmable ROM while the 8751 has 4K
bytes of ultraviolet light-erasable, electrically programmable ROM (EPROM).
The 8031 CPU operates at a 12 MHz clock rate,
resulting in 4 ",s multiply and divide and other instructions of 1 ",s and 2 "'s.
For additional information on the 8051 family, see
the 8051 User's Manual or MCS-51 Macroassembier User's Guide.
REFERENCE
r-
COUNTERS
-i------------------
OSCILLATOR
&
TIMING
--1
4096 BYTES
PROGRAM
MEMORY
(8051 & 8751)
128 BYTES
DATA MEMORY
TWO 16·BIT
TIMER/EVENT
COUNTERS
64K·BYTE BUS
EXPANSION
CONTROL
PROGRAMMABLE
I/O
PROGRAMMABLE
SERIAL PORT
• FULL DUPLEX
USART
• SYNCHRONOUS
SHIFTER
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS,
& I/O PINS
8051
CPU
11
--r--~-
L
INTERRUPTS
Figure 1_ 8051 Block Diagram
17-16
SERIAL
IN
SERIAL
OUT
SDK·51
Table 1. SDK-51 Commands
System Software
A compact but powerful system monitor is contained in 8K bytes of pre-programmed ROM. The
monitor includes system utilities such as command interpretation, user program debugging,
and interface controls. Table 1 summarizes the
SDK-51 monitor commands.
Command
Set breakpoint
Display cause
The ROM devices also include a single-line assembler and disassembler. The assembler lets
you enter programs in MCS-51 assembly language
mnemonics directly from the ASCII keyboard. The
disassembler supports debugging by letting you
look at MCS-51 instructions in mnemonic form
during system interrogation.
Upload, download
Save, load
Set top of
program memory
Set baud
Memory
Display memory
The two 64K external memory spaces are combined into a single memory space which you can
configure between program memory and data
memory. The kit includes 1K-byte of static RAM.
The board has space and printed circuitry for an
additional 15K bytes of RAM and 8K bytes of
ROM.
Assemble
Disassemble
Go
User Interface
Step
The kit includes a typewriter-format, ASCII-subset
keybo~rd and a 24-character, alpha-numeric LED
Operation
Define addresses for breaking
execution.
Ask the system why execution
stopped.
Transfer files to and from Intellecl!> development system.
Transfer flies to and from optional cassette interface.
Define' partition between program memory and data memory.
Define baud rate value of serial
port.
Examine and change program
memory or data locations.
Translate an MCS-51 assembly
mnemonic into object code.
Translate program memory into
MCS-51 assembly language
mnemonics.
Start execution between a selected pair of addresses.
Execute a specified number of
instructions.
USER·
CONFIGURABLE
MEMORY
ADDRESS
& DATA BUSES
UPI
BUS
Figure 2. Block Diagram of SDK·51 System Design Kit
17-17
SDK·51
display. The standard keyboard and display pro·
vide full access to all of the SDK·51's capabilities.
All of the SDK·51 interfaces are controlled by a
pre·programmed Intel 8041 Universal Peripheral
Interface.
A 3 x 4 matrix keyboard can be jumperecj to port 1
of the 8031.
Optional Interfaces
TERMINAL
An RS·232-compatible CRT or printing terminal or
a current-loop-interface terminal may be. used as a
listing device by connecting it to· the board's
serial interface connector and supplying + 12 and
- 12 volts to the board.
Debugging
Hardware breakpoint logic in the SDK-51 checks
the address of a program or external data-memory
access against values defined by the user. and
stops execution when it sees a "break" condition.
After a breakpoint, you can examine and modify
registers, memory locations, and other points in
the system. A step command lets you execute instructions in a single-step mode.
Assembly and Test
The SD·K-51 assembly manual describes hardware
assembly in a step-by-step process that includes
checking each hardware subsystem as it is installed. Building the system requires only a few
common tools and standard laboratory instruments.
AUDIO CASSETTE
The kit includes hardware, software, and user's
guide instructions to connect and operate an
audio cassette tape recorder for low-cost program
and data storage.
INTELLEC SYTSTEM
An SDK-51 and an Intellec Model 800 or Series II
development system with ISIS-II can upload and
download files through the serial interface without adding any software to· the Intellec system.
Parallel 1/0
The kit includes an Intel 8155 parallel I/O device
which expands the 8031 I/O capability by providing 22 dedicated parallel lines. Three 40-pin headers between the 8031 and 8155 devices and the
wire-wrap area facilitate interconnections with the
user's custom circuitry.
Figure 3. SDK-51 Assembled with Additional RAM
and ROM Devices Installed
SPECIFICATIONS
Control Processor
Interfaces
Intel 8031 microcomputer
12 MHz clock rate
Keyboard - 51-key, ASCII subset, typewriter format~ 12-key (3 x 4) matrix
Memory
Display - 24-character, alpha-numeric
RAM - 1K-byte static, expandable in 1K segments to 16K-byte with 2114 RAM devices; userconfigurable as program or data memory.
ROM - Printed circuitry for 8K bytes of program
memory in 4K segments using 2732A EPROM devices.
Serial - RS-232 with user-selectable baud rate.
Printed circuitry for 110 baud 20 mA current loop
interface. 8031 serial port.
17-18
Parallel - 22 lines, TTL compatible
Cassette- Audio cassette tape storage interface
SDK·51
Software
Electrical Characteristics
System monitor preprogrammed in on-board ROM
MCS-51 assembler and disassembler preprogrammed in on-board ROM
Interface control software preprogrammed in
8041's on-chip ROM
DC Power Requirement (supplied by user, cable
included with kit)
Voltage
+ 5V ±5%
+ 12V ± 5% *
-12V ±5%*
Assembly and Test Equipment Required
Needle-nose pliers
Small Phillips screwdriver
Small diagonal wire cutters
Soldering pencil, :5 30 watts, 1/16" diameter tip
Rosin-core, 60-40 solder, 0.05" diameter
Volt-Ohm-Milliammeter, 1 meg-ohm input impedance
Oscilloscope, 1 volt/division vertical sensitivity,
200 Its/division sweep rate, single trace, internal
and external triggering
Physical Characteristics
Length - 13.5 in. (34.29 cm)
Width - 12 in. (30.48 cm)
Height - 4 in. (10.16 cm)
Weight - 3 Ib (1.36 kg)
Description
MCI-51·SDK
MCS-51 System Design Kit
3A
100 mA
100 mA
• ± 12 volts required only for operation with serial interface.
Environmental Characteristics
Operating Temperature - 0 to 40°C
Relative Humidity - 10% to 90%, non-condensing
Reference Manuals
SDK-51
SDK-51
SDK-51
MCS-51
MCS-51
ence
ORDERING INFORMATION
Part Number
Current
17-19
User's Manual
Assembly Manual
Monitor Listing
Macro Assembler User's Guide
Macro Assembly Language Pocket Refer-
SDK·2920
2920 SYSTEM DESIGN KIT
• Complete 2920 program development:
- 2920 assembly language keyboard
- Single-line assembler/disas.sembler
- 24-character, alphanumeric display
- 2920 memory display and modify
- List program memory to line printer
with symbol. table
• File handling capabilities:
- Up/down load of object file to
Intellec or audio cassette
- Up load source file with symbol
table to Intellec
- 2920 EPROM programming
• Decimal-to-binary conversion program
• Breadboarding area
• Real-time execution of a programmed
2920
The SDK-2920 contains all of the components required to assemble a complete single board microcomputer system for programming and evaluation of the 2920 Analog Signal Processor. The 8085/8041A
microcomputer-based program development section allows you to immediately enter programs in 2920
assembly mnemonics, translate them to 2920 object code, and program the on-board 2920 EPROM. The
kit supports basic filing options such as up/down loading to/from an Intellec, audio cassette, and .line
printer. The SDK-2920 also provides the user with a 2920 run mode section allowing real-time execution of
a programmed 2920. This section comes complete with BNC connectors and Intel's 2912 PCM line filters
required for one input and one output network. The kit supports optional input and output circuitry on the
run mode section.
17-20
SDK·2920
Tables 1 and 2 show the 2920 instruction set and
op codes.
FUNCTIONAL DESCRIPTION
The SDK-2920 is a kit which includes all the
necessary hardware and software components to
assemble, using common laboratory tools and
test equipment, a complete single board 2920 programmingand evaluation aid. Assembly generally
requires 4 to 8 hours, depending on the experience of the user.
Table 1. Shift Op Codes
Operation
Mnemonic
Shift Right 13 Bits
Shift Right 12 Bits
R13
R12
.
.
The 2920 Signal Processor
The Intel® 2920 Signal Processor is a programmable, single chip analog and digital si9ral processor specifically designed to replace analog
subsystems in real-time processing applications.
Its instruction set plus the high precision (25 bits)
digital arithmetic logic unit provides the capability
to implement very complex subsystems. Typical
functions performed by the 2920 include: lowpass
and bandpass filters with up to 20 complex pole
and/or zero pairs; threshold detectors; limiters;
rectifiers; up to 25-bit multiplication and division;
approximations to nonlinear functions such as
square law and logarithm; logical operations; input and output multiplexing of signals; logical
outputs for decision type processing; and analog
outputs for multi frequency oscillators, waveform
generators, etc. In addition, several 2920's may be
cascaded for very" complex processing applications with no loss in throughput rate.
Shift Right 1 Bit
No Shift
Shift Left 1 Bit
Shift Left 2 Bits
Op Code
1 1 0 0
1 0 1 1
·
·
·
R01
.··.
. ·· ·· .
0 0 0 0
ROO
L01
L02
1 1 1 1
1 1 1 0
1 1 0 1
SIGOUT(2)
SIGOUT(3)
SIGOUT(4)
SIGOUT(5)
D/A
SIGOUT(6)
t---------.----.I
SIGOUT(7)
"EXTERNAL COMPONENTS
M2
Figure 1. 2920 Function Block Diagram (Run Mode)
17-21
1
2
4
The monitor ROM devices also include a singleline assembler and disassembler. The assembler
lets you enter programs in 2920 assembly language mnemonics. The disassembler supports
debugging by letting you look at or change either
hexadecimal values or 2920 instructions during
program interrogation.
SIGOUT(l)
CLOCK LOGIC
&
PROGRAM
COUNTER
2- 1
System Software
SIGOUT(O)
=
2- 13
2",2
A compact but powerful system monitor is contained in 6K bytes of preprogrammed ROM. The
monitor includes system utilities such as command interpretation, user program debugging,
and interface controls.
PROGRAM STORAGE
(EPROM)
192 x 24
XlICLK
Scale
3 2 1 0 Factor
SDK·2920
Table 2. Instruction Set and Op Codes
Op Codes[11
Mnemonics
Code Condition
Digital·lnstructions
ADD
SUB
LDA
XOR
AND
ABS
ABA[11)
ALU
2,1,0
110
101
111
000
001
011
100
010
110
LIM
ADD CND(
)[2)
SUB CND(
)[2,8)
101
LDA CND(
)[2)
111
ABA[11) CND( )[9)
XOR CND( )[9)
ADF
1,0
ADK
2,1,0
1 1
[3]
[3]
j j
100
000
Operations
Notes
(AX2 N)+B - B
B-(Ax2 N) - B
(Ax2 N)+0 - B
(Ax2 N)eB - B
(Ax2 N)_B - B
I(Ax2N)1 - B
I (A x 2N) I + B - B
Sign(A} - ± F.S. -" B[4)
(A x 2N) + B - B [FF DAR(K)= 1
B - B [FF DAR(K) = 0
B-(Ax 2N) -'8 & CY - DAR(K) [FF CYp= 1
B+(AX2N) - B &CY - DAR(K) IFF CYp=O
(A x 2N) - B [FF DAR(K) = 1
B - B [FF DAR(K)= 0
(Ax2N)+ B - B
(Ax2N)e B - 8
[5]
Analog Instructions
[N(K)
OUT(K)
CVTS
CVT(K)
EOP
NOP
CND(K)
CNDS
o
I
00
10
00
01
j
do
0-3
0-7
6
0-7
5
00
1,
00
0-7
7
[7]
4
Signal sample from input channel K
D/A to output channel K
Determine sign bit
Perform AID on bit K
Program counter to zero
No operation
Select bit K for conditional instructions
Select sign bit for conditional instruCtions
2 3 4
[6]
5
101112101 111A11B11A21 IB21A31B31A41 IB41A5IB5IAol IBolol1121
I... ADK--I...ADF....I.......c-----MEMORY ADDRESSES-----I- SHF-I.....-ALU---I
Note: The input pins for each nibble bit from left to right are DO, 01, 02, 03.
NOTES:
1. Op codes ALU and ADF are in binary notation, ADK is in decimal notation and represents the value "K" when appropriate.
2. CND( ) can be either CND(K) or CNDS testing amplitude bits or the sign bit of the DAR respectively.
3. Determined by analog instructions below.
4. B is set to full scale (F.S.) amplitude with the same sign as the "A" port operand.
5. The previous carry bit (CYp) is tested to determine the operation. The present carry bit (CY) is loaded into the Kth bit location of
the DAR. "Present carry (CY) is generated independent of overflow. It will represent the carry (CY)·of a calculated 28·bit result."
6. EOP will also enable overflow correction if it was disabled during a program pass. The EOP must occur in ROM location 188.
7. Determined by digital instructions above.
8. For SUB CNDS Operation CY- DAR(S).
9. Does not affect DAR. In this case, CND Is used with XOR/ABA to enable/disable the ALU overflow saturation algorithm. Use of
either instruction causes the ALU output to roll over rather than go to full scale with sign bit preserved. An EOP instruction will
also enable the ALU overflow saturation algorithm.
10. Clarification of CYOUT sense for certain operations. For LOA, XOR, AND, ABS; CY OUT - O.
Memory
User Interface
The kit contains 1.25K bytes of RAM for 2920 program development. The RAM is used as 2920 pro·
gram memory for up to a 192·instruction 2920 pro·
gram. The RAM space is also used for a symbol
table up to 40 user defined symbols,
The kit includes a function· and hex keyboard and
a formatted 24·character, 18-segment display for
easy 2920 code entry, The interactive keyboard
and display enables the system monitor fo step
the user through a command entry sequence with
17·22
SDK·2920
the friendliness of a menu-driven operating system.
Assembly and Test
The SDK-2920 assembly manual describes assembly in a step-by-step process that includes checking segments of.hardware as they are installed.
Building the system requires only a few common
tools and standard instruments.
Optional Interfaces
An RS-232 or 20 mA current loop compatible CRT
or printer may be used as a listing or file storage
device by connecting it to the board's serial interface connector and supplying + 12 and-12 vdlts
to the board. In addition, the kit provides an audio
cassette interface, allowing the use of an audio
cassette as a mass storage device.
Debugging
Program development is made easy by use of interactive error messages that will inform the user
of illegal entries at the time of program development. Syntax errors are checked for at time of
EPROM programming, giving the user the option
to continue the programming or not.
The run-mode section allows the user to execute a
programmed 2920 in real time, with his own input
stimulus and output circuit or instrumentation.
The kit is supplied with the 2920-18 and a 5 MHz
crystal (800 ns instructions). However, the kit will
support the 2920-16 (600 ns instructions) with a
6.67 MHz crystal or clock.
CONTROL
SECTION
RESET
LIST
LOAD
- -
HEX/ASM
EDIT
INSRT
NEXT
DEL
SHIFT
2920 DATA KEYS
KP
KN
ADD
e
+/-
SUB
R
L
PREY
CONY
eR
Figure 3_ Assembled SDK-2920
•
.
IN
ABS
ABA
E
AND
F
9
LIM
A
XOR
B
OUT
cvrs
,
eVT
eND
2
EOP
0
LOA
5
DAR
Nap
eNDS
y
0
1
2920.
~
~
7
SYSTEM DESIGN KIT • • •
3
Figure 4_ Display Layout
Figure 2_ Keyboard Arrangement
Figure 5. SDK-2920 Functional Block Diagram
17-23
SDK·2920
Table 3. SDK·2920 Control Commands
RESET
Sets the monitor to its initialization program and responds to the selection of one of the four modes.
The display will prompt the user with EDIT? LOAD? LIST? CONY?~
SHIFT
Selects the upper case characters or functions.
EDIT
Selects the edit mode, allowing for 2920 program entry and/or modification. The commands available
in the edit mode are shown below in Table 4.
LOAD
Selects the load mode, providing for up/down loading to/from the RS·232, cassette, or the 20mA cur·
rent loop interfaces. It also provides for 2920 EPROM read, program and verify.
LIST
Selects the list mode, providing for listing the 2920 program source code, symbol table, and 2920 hex
code to a line printer via the RS·232 interface.
CONY
Selects the decimal·to·binary·to·decimal conversion program.
Table 4. Edit Mode Commands
Cursor Right
The blinking cursor is moved right one positiOn unless at the end of displayed
field.
Cursor Left
Blinking cursor is moved left until the sequence number is encountered, then it
skips to the left edge of the display.
NEXT
Next Instruction
The next 2920 instruction is displayed unless at end of memory.
PREY
Previous Instruction The previous 2920 instruction is displayed unless at beginning of memory.
LIST
List Memory
Send disassembled 2920 instructions to serial port.
IHEX/ASM I Mode Toggle
Toggle edit mode between symbolic assembly and hexadecimal.
INSRT
Insert Instruction
Expand the program in memory by one location and insert a NOP at current
memory display address.
DEL
Delete Instruction
Contract the program in memory by one location and remove the instruction at
the current memory display position.
EDIT LOAD LIST CONV
NOTE: WILL BLINK IF NOT
SOCKETED PROPERLY
AFTER (CR)
NOTE: CAN ENTER SINGLE
CHARACTER
+
2920_1 AUX_ 2 CASS= 3
,
VERIFY 2920 SOCKETED (CR)
.
t
I
t
ITO ·SDK = 1 FROM ·SDK = 2(
Lr.R::":E"'AD::"=""1"::P"::'RO""G"'IV""E=-R=-2"'C""M""PR:,,='-3"",II START AUX II OBJ=l
~SH
C.R TO P:OGRAM
START
SOURCE=2 I
L ENTER FILE XX(CR)
•
I
ITO ·SDK _1 FROM ·SDK _ 2
:ux. THEN (C;)
t
START CASS
t
START CASS THEN (CR)
•
2920 TRANSFER ACTIVE
CHECKSUM
11
t
r--'
-xx. (CR)
(DATA DISPLAYED AS TRANSFERRED)
t
LOAD COMPLETE (CR)
Figure 6. Load Command and Display Tree
17-24
+
(DISPLAY BLANK)
xx LOADED (CR)
SDK·2920
Control Processor
• Oscilloscope, 1 volt/division vertical sensitivity,
200 Its/division sweep rate, single trace, internal
and external triggering
Intel 8085A microprocessor
6.144 MHz clock rate
Physical Characteristics
SPECIFICATIONS
Memory
RAM ROM -
1.25K-byte static
6K-byte
Length - 16 in. (40.64 cm)
Width - 10 in. (25.40 cm)
Height - 4 in. (10.16 cm)
Weight - 3 Ib (1.36 kg)
Interfaces
Electrical Characteristics
Keyboard - 28-key with shift, providing 54 functions and characters
Display - 24-character, 18-segment LED
Serial - RS-232 with user-selectable baud rate
and 20 mA current loop
Cassette - Hardware and software for audio cassette tape storage interace
DC Power Requirements (supplied by user, cables
included with the kit)
Software
Run Mode Section:
System monitor preprogrammed in ROM
2920 assembler and disassembler preprogrammed in ROM
Interface control software preprogrammed in 8041
on-chip ROM
Voltage
+5V ±5%
Current
300 mA
200 mA
-5V ±5%
250 mA
200 mA
Program Development Section:
Assembly and Test Equipment Required
•
•
•
•
•
•
•
Needle-nose pliers
Small Phillips screwdriver
Small flat-blade screwdriver
Small diagonal wire cutters
Soldering pencil, <30 watts, 1/16" diameter tip
Rosin·core, 60-40 solder, 0.05" diameter
Volt-ohm-milliameter, 1 meg ohm input impedance
Description
MCI-20-SDK
2920 System Design Kit
Current
1.0A
100 mA
-12V±5%
100 mA
Comments
Required for program development
Required for 2920 EPROM program·
ming and RS·232 interface
Required for RS·232 interface
Comments
Required for operation as supplied
Required for each additional 29121
74LS324 pair
Required for operation as supplied
Required for each additional 29121
74LS324 pair
Environmental Characteristics
Operating Temperature - 0 to 40°C
Relative Humidity - 10% to 90% non-condensing
Reference Manuals
SDK-2920 System Design Kit User's Guide
SDK-2920 System Design Kit Assembly Manual
2920 Analog Signal Processor Design Handbook
ORDERING INFORMATION
Part Number
Voltage
+5V ±5%
+12V±5%
17-25
MCS-48™ Development
Systems
18
inter
INTELLEC PROMPT 48
MCS·48 MICROCOMPUTER DESIGN AID
Complete low cost design aid and
EPROM programmer for revolutionary
MCS-48 single component computers
256 bytes expandable RAM data memory
in PROMPT system
Simplifies microcomputing, allowing user
to enter, run, debug, and save machine
language programs with calculator-like
ease
Utilizes two removable 8-bit MCS-48
CPUs
8748 CPU with erasable, reprogrammabie on-chip program memory
8035 CPU with off-chip program
memory
27 on-chip TTL compatible expandable
1/0 lines
On-chip clock, internal timerlevent
counter, two vectored interrupts, eight
level stack control
Single + 5V DC system power
requirement
Integral keyboard and displays (no teletypewriter or CRT terminal required)
1 K-byte erasable, reprogram mabie onchip (8748), expandable program memory, 1 K-byte RAM in PROMPT system
Extensive PROMPT 48 monitor, allowing
system 1/0, bus, and memory expansion
64 bytes RAM on-chip, expandable
register memory
Includes comprehensive design library
The Intel lee Prompt 48 MCS-48 Microcomputer Design Aid is a low cost, fully-assembled design aid for the revolutionary 8748 single component microcomputer. PROMPT 48 simplifies the programming of MCS-48 systems - programs may be entered and debugged with calculator-like ease on the large, informative display and keyboard panel.
The comprehensive design library with tutorial manual is ideal for newcomers to microcomputing. PROMPT 48's
panel connector allows easy access to 1/0 ports and system bus. Thus users can expand program memory beyond the
1K bytes provided internally.
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIED IN AN INTEL PROOUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPliED.
INTEL CORPORATION. 1979
©
18-1
AFN-003S2A-01
INTELLEC PROMPT 48
FEATURES
Single Component Computer
The 8748 is the first microcomputer fully integrated on
one component. All elements of a computing system are
provided, including CPU, RAM, 1/0, timer, interrupts, and
erasable, reprogrammable nonvolatile program memory.
Programming Socket
PROMPT's programming socket programs this revolutionary "smart PROM"-the 8748-in a highly reliable,
convenient manner. A fail-safe interlock ensures the
device is properly inserted before applying programming pulses. Each location may be individually programmed, one byte at a tim'e. A read-before-write
programming algorithm' prevents device damage by
inadvertently programming unerased memory.
real time - after each instruction the MCS-48 program
counter is compared against pending breakpOints. If no
break is encountered, execution resumes. The go single
step (GO SINGLE STEP) mode exercises one instruction
at a time. Commands are like sentences, with parameters separated by I'J NEXT. Each command ends with
I'J EXECUTE/END. In addition to the PROMPT basic
commands, thirteen functions simplify programming.
Each is started merely by preSSing a hex datalfunction
key and entering parameters as required, as shown in
Table 1.
MCS·48 Processors
The execution socket accepts either an 8035 or an 8748
MCS-48 processor. Both are supplied with each
PROMPT 48, and either can serve as heart of the
PROMPT system. There are no processors within the
PROMPT 48 mainframe,which instead contains monitor
ROM and RAM, user RAM, peripherals, drivers, and
sophisticated control circuitry. Once a processor is
seated in the execution socket and power is applied, the
PROMPT system comes to life. Various access modes
may be selected such as' program execution from
PROMPT system RAM,or from on~chip PROM. Thus programs may first be executed from PROMPT RAM with
the 8035 processor. When debugging is complete, the
8035 (execution socket) processor can program the 8748
(programming socket) processor. Finally, a programmed
8748 processor may be exercised by itself from the
execution socket.·The execution socket processor runs
either monitor or user programs.
System Monitor
The system reset command initializes the PROMPT
system and enters the monitor. The monitor interrupt
command exits a user program gracefully, preserving
system status and entering the monitor. The user interrupt command causes an interrupt only if the PROMPT
system is running a user program. A comprehensive
system monitor resides .in four 1K-byte read only
memories. It drives the PROMPT keyboard and displays
and responds to commands and. functions. The top 16
bytes of on-chip program memory must be usecj by the
PROMPT system to switch between monitor and user
programs. It requires one level of the MCS-48 eight-level
stack.
Commands
PROMPT 48's commands are grouped and color-coded
to simplify access to the 8748'sseparate program and
data memory. Registers, data memory,.or program memory, may be examined and modified with the examine
and modify commands. Then either the next or previous
register and memory locations may be accessed with
one keystroke. Programs may be exercised in three
modes. The go no break (GO NO BREAK) runs in real
time. The go with break (GO WITH BREAK) mode is not
18-2
AFN-00352A-02
INTELLEC PROMPT 48
Cable Interface
Kay
An optional cable, PROMPT·SER, directly connects the
PROMPT system to virtually any terminal via a rear
access slot.
111
Port 2 map
Allows specification of direction of each pin
on port 2. Port 2 is multiplexed to address
external program memory and expand 110.
Thus it must be buffered; the P2 map command establishes the direction of buffering.
[!J
I}]
Program EPROM
Byte search
(with optional
mask)
Programs 8748 EPROMs.
Sweeps through register, data, or program
memory searching for byte matches. Start·
Ing and ending. memory addresses are spe·
clfied.
I])
Word search
(with optional
mask)
Sweeps through register, data, or program
memory searching for word matches. Start·
ing and ending memory addresses are specified.
[!]
Hex calculator
Computes. hexadecimal sumS and differ·
ences.
[!]
8748 program
for debug
Similar to program EPROM, but ensures that
the top of program memory contains moni·
tor re-entry code for debugging.
[!]
Compare
Verifies any portions 'of EPROM program
memory against PROMPT memory.
[!]
.Move memory
Allows blocks of register, data, or program
memory to be moved.
~
Access
Specifies one of six access modes for PROMPT 48. For example EPROM, PROMPT
RAM, or external program memory, and a
var.iety of ·.inpuUoutput options may be
selected.
I!I
Breakpoint
Allows any or all of the eight breakpoints to
be set and clea~ed.
@]
Clear
Clears portions of register, data, or program
memory.
@]
Dump
Dumps register, data, or program memory to
PROMPT's serial channel: for example, a
teletypewriter paper tape punch.
[]]
Enter
Enters (reads) register, data, or program
memory from PROMPT's serial channel.
[£]
Fetch
Fetches programs from EPROM to PROMPT
RAM.
Function
Operation
Table 1. PROMPT 48 Commands and FUnctions
Access
Easy access·to the pins of the executing 'processor is
provided via the 110 ports and bus connector. Only the
EA external access, SS single step, and Xl, X2 clock
inputs are reserved for the PROMPT system.
Expansion
Program or data memory may be expanded beyond that
provided on·chip or in the PROMPT system: 110 ports
may be expanded, as with the 8243, orperipheral can·
trollers may be memory·mapped. The 116 ports and Bus
connector al/ows the execution socket processor to be
directly interfaced to prototype systems, yet be con·
trol/ed from the PROMPT pane/.
Control
The command/function group panel keyboard. and dis·
plays completely control PROMPT 48-a teletypewriter
or CRT terminal is not needed. A hyphen prompting
character appears whenever a command or function can
be entered. Addresses and data are shown whenever
examining registers and memory. Parameters for com·
mands and functions are also shown.
18-3
AFN-ll0352A·03
INTELLEC PROMPT 48
FUNCTIONAL DESCRIPTION
Compatibility - For systems requiring additional compatibility, the MCS-48 can be expanded with the new
8243 1/0 expander, 8155 1/0 and 256-byte RAM, 8755 1/0
and 2K-byte EPROM, or 8355 1/0 and 2K ROM devices.
MCS·48 processors readily interface to MCS·80/85
peripherals and standard memories.
"PROMPT" stands for PROgraMming Tool. It Is a programmer for 8748 EPROMs, and a versatile aid for
debugging MCS·48 programs. Programs can be entered
via Its Integral panel keyboard, programming socket, or
serial channel. Almost any terminal can be Interfaced to
the serial channel, Including a teletypewriter, CRT, or an
Intellec microcomputer development system. Intellec
PROMPT 48 simplifies the programming of MCS-48
systems. Like the 8748 It Is radically new, highly in·
tegrated, and expandable. Like the MCS·48 family, it is
low cost, and Ideal for small applications and programs.
It Is a design aid, not a development system with
sophisticated software and peripherals.
Memory Capacity
PROMPT 48 is a comple~e, fully assembled and powered
microcomputer system including program memory, data
memory, 1/0, and system monitor beyond that available
on MCS-48 Single component computers. 1K bytes of
PROMPT system RAM serve as "writable program memory" - a ROM simulator for the program memory on
each MCS-48 computer. 256 bytes of PROMPT system
RAM serve as "external data memory," beyond the 64
register bytes on each MCS·48 computer. Users may further expand program or data memory via the panel 1/0
ports and bus connector.
MCS·48 processors
PROMPT 48 comes complete with two of Intel's revolutionary MCS·48 processors: an 8748·4 Single Compo·
nent 8-Blt Microcomputer and and 8035·4 Single Compo·
nent 8-Blt Microcomputer. Advances In n·channel MOS
technology allow Intel, for the first time to integrate into
one 40·pin component all computer functions:
8-blt CPU
1K x 8-blt EPROMIROM program memory
64 x 8·blt RAM data memory
27 input/output lines
8·bit timerlevent counter
Programming
Programs written first in assembly language, are
entered in machine language and debugged with
calculator-like ease on the large, informative display
and keyboard panel. Most MCS-48 operations can be
specified with only two keystrokes. Once entered,
routines can be exercised one instruction (single step)
or many Instructions at a time. The principal MCS-48
register - the accumulator - is displayed while single
stepping. Programs can be executed in real time (GO
NO BREAK) or with as many as eight different breakpOints (GO WITH BREAK).
Performance - More than 90 instructions - each one
or two cycles - make the single chip MCS-48 equal in
performance to most multi-chip microprocessors. The
MCS·48 Is an efficient controller and arithmetic pro·
cessor, with extensive bit handling, binary, and BCD
arithmetic instructions. These are encoded for
minimum program length; 70% are Single byte opera·
tlon codes, and none is more than two bytes.
Flexibility - Three interchangeable, pin-compatible
devices offer flexibility and low cost in development and
production, as follows:
8748 - with user-programmable and erasable EPROM
program memory for prototype and pre-productions
systems.
8048 - with factory·programmed mask ROM memory
for low·cost, high volume production.
8035 - without program memory, for use with external
program memories.
Control
PROMPT 48 canbe fully controlled either by the panel
keyboard and displays, or remotely by a serial channel.
Thus a teletypewriter or CRT can be used but neither is
required.
Access
The PROMPT panel 1/0 ports and bus connector allow
easy access to all MCS-48 pins except those reserved
for control by the PROMPT system, namely EA external
access, SS single step, and X1, X2 clock inputs.
Optional Expansion
Circuitry - Each MCS·48 processor operates on a
Single + 5V supply, with internal OSCillator and clock
driver, and circuitry for interrupts and resets. Extra circuitry is In the 8048 ROM processor to allow l.ow power
standby operation. The 64 x 8 RAM data memory can be
Independently powered.
PROMPT 48 may be expanded beyond the resources on
both the MCS-48 single component computer and the
PROMPT system. External program and data memory
may be interfaced and Inputlout ports added with the
8243 1/0 expander.
18-4
AFN-00352A-04
INTELLEC PROMPT 48
Documentation
The PROMPT 48 manual Includes chapters for the
reader with little or no programming experience. Topics
treated range from number systems to microcomputer
hardware design. A novel, unifying set of tutorial
diagrams - MICROMAPS - simplify microcomputer
SPECIFICATIONS
User Interrupt - causes an Interrupt only If the
PROMPT system is. running a user program.
Timing
The processor traps to location 316 . The MCS-48 timer/event counter is not used by the PROMPT system and is
available to the user. Either timer flag or interrupt will
signal when overflow has occurred. The timer interrupt
can be used only in the go-no-break (real time) mode.
Basic Instruction - 2.5 J-Is
Cycle Time - tCY = 2.5 J-IS
Clock - 6 MHz ± 0.1%
Memory Bytes
The 8748 contains 64 bytes of register memory, no ex·
ternal data memory, and 1024 bytes of RAM program
memory. The PROMPT system provides 256 bytes of ex·
ternal data memory, and 1024 bytes of RAM program
memory. PROMPT RAM program memory can be used
in place of the on·chip EPROM program memory; thus
programs less than 1024 bytes may be designed. For
larger programs additional memory can be directly interfaced to the MCS-48 bus via the PROMPT panel 110
ports and bus connector.
Memory Configuration
Memory
Register
Data
Progra.m
concepts. PROMPT's handy, pocket·slzed reference
card let can be affixed to the mainframe. Programming
pads aid In the organization and documentation of pro·
grams. These features, plus a comprehensive design
library of manuals, articles, and application notes,
make the Intellec PROMPT 48 ideal for the newcomer to
mlcrocomputlng.
Maximum
On Chip
In PROMPT 48
64
3328
4096
64
0
1024 EPROM
0
256
1024 RAM
EPROM Programming
PROMPT 48 provides a programming socket to directly
program 8748s. Programs are loaded into the PROMPT
RAM program memory via keyboard. EPROM, teletypewriter, or other serial interface. A fail·safe interlock
ensures programming pulses are applied only if the
device is properly inserted. Inadvertant reprogramming
is prevented by a read-before·write programming algorithm. Each location maybe individually programmed,
one byte at a time.
Panel 1/0 Ports and Bus Connectors
110 Ports
All MCS-48 110 ports are accessible on the PROMPT
panel connector.
Bus - A true bidirectional 8-bit port with associated
strobes. If the bidirectional feature is not needed, bus
can serve as either a statically latched output port or a
non·latching input port. Input and output lines cannot
be mixed.
Ports 1 and 2 - Data written to these 8-bit ports is
latched and remains unchanged until written. As inputs
these lines are not latching. The lines of ports 1 and 2
are called quasi bidirectional. A special output structure
allows each line of port 1 and half of port 2 to serve as an
input, an output, or both. Any mix of input, output, and
both lines is allowed.
TO, T1, and INT - Three pins that can serve as inputs. TO
can be deSignated as a clock output. Input/output can
be expanded via the PROMPT panel connector with a
special 110 expander (8243) or standard peripherals.
Ali MCS-48 pins, except five, are accessible on the 110
ports and bus connector. The five reserved for PROMPT
system control are EA external access, SS single step,
X1, X2 crystal inputs,and 5V. Due to internal buffering
of the MCS-48 bus, access times will be negligibly
degraded by the PROMPT system .. Since MCS-48 processors do not communicate internal address gate
status, bus data must be driven out if neither PSEN nor
RDis asserted.
System Devices
Both user programs and the PROMPT monitor enjoy access to system devices: serial 110, panel displays, and
keyboard. These are memory-mapped .to program
memory addresses beyond 2K.
Serial 110 - The serial 110 port (data 820 16 , control 821 16 )
is'defined by software and jumpers for 110 baud, 20 mA
current loop, but can easily be jumpered for other baud
rates and RS232C levels. Asynchronous or synchronous
transmission, data format, control characters, and parity can be programmed.
Panel Displays - Eight display ports (data 810-817 1sl
allow each of the panel displays to be written from user
programs. Data written on a display device wili time out
after a fixed interval. Displays must be refreshed on a
polied or interrupt-driven basis. User programs can cali
software drivers which provide this capability.
Reset and Interrupts
Reset - initializes the PROMPT system and enters the
monitor.
Monitor Interrupt - exits a user program gracefully,
preserving system status and entering the monitor.
18-5
AFN-OD3S2A-OS
INTELLEC PROMPT 48
Keyboard - Software Is used to debounce the panel
keyboard (data 810 16 ). The monitor's input routines (see
Software Drivers) provide this debouncing and can be
called from user programs.
Equipment Supplied
Commands
Single step}
With break
No break
PROMPT 48 mainframe with two MCS·48 processors
(8748, 8035), display/keyboard, EPROM programmer,
·power supply, cabinet, and ROM·based monitor.
110 V AC power cable
110 or 220 V AC
Fuse
Panel I/O ports
Bus connector cable set
Go
Register}
{ Data
Memory
Program
Open previous/clear/entry II] Next 0 Execute/End
Examine/modify
Functions
~
~
iii
~
[§J
ILl
~
[[]
·IAJ
lID
~
[j!]
lID
[fJ
Panel 110 Ports and Bus Connector - 3M 3425 Flat
Crimp. A complete cable set including wlrewrap header
for prototyplng Is included with each PROMPT.
Physical Characteristics
Port 2 map
Program EPROM (8748)
Search (R, D or Pl· memory for 1 byte, optional
mask
Search (R, D or P) memory for 2 bytes, optional
mask
Hexadecimal calculator + ,8748 program EPROM for debug
Compare EPROM with memory
Move memory (R, D or P)
Access
Breakpoint
Clear memory (R, D or P)
Dump memory (R, D or P)
Enter (read) memory (R, D or P)
Fetch EPROM program memory
Height - 5.3 in. (13.5 cm) max
Width - 17 in. (43.2 cm)
Depth - 17 in. (43.2 cm) max
Weight - 21 lb. (9.6 kg)
Electrical Characteristics
Pt'· ·er Requirements - either 115 or 230V AC (± 10%)
may be switch selected on the mainframe. 1.8 amps
max current (at 125 VAG).
Frequency - 47·63 Hz
Environmental Characteristics
Operating Temperature - O°C to + 40°C
Non·Operating Temperature - 20°C to +65°C
Reference Manuals
Note
• R, D, or P is register, data, or program.
9800402 Intellec PROMPT 48 User's Manual
(SUPPLIED)
9800270 - MCS·48 User's Manual (SUPPLIED)
9800255 - MCS·48 and UPI·41 Assembly Language
Programming Manual (SUPPLIED)
Software Drivers
Panel Keyboard In - KBIN, KDBIN
Panel Display Out - DGS6, DGOUT, HXOUT, BLK,
REFS, ENREF
Serial Channel - CI, CO, RI, PO, CSTS
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Connectors
Serial I/O - 3M 3462·0001 Flat Crimp/AMP 88106·1 Flat
Crimp/ TI H312113 Solder/AMP 1·583485·5 Solder.
ORDERING INFORMATION
Part Number Description
PROMPT·48 or
PROMPT·48·220V
Intellec PROMPT 48 MCS·48 micro·
computer design aid. Complete with
two MCS·48 processors (8748 and
8305), EPROM programmer, integral
keyboard, displays, and system
monitor in ROM.
PROMPT·SER
Serial cable for connecting PROMPT
to TTY, CRT
18-6
AFN-00352A-06
HSE·49
HIGH·SPEED EMULATOR
• Single-board execution and debugging
vehicle with integral keypad and display
• Real-time 11 MHz emulation of user
system
• Breakpoints on user program and
external data addresses
.• System monitor firmware in ROM
• Wire-wrap area for prototyping
• Examine and alter MCS® -48 registers,
memory and status values
• Intellec@l..system compatible power
pick-up card and serial-link cable
• No-break triggering of oscilloscope or
logic analyzer
The HSE-49™ emulator is a fully-assembled stand-alone development tool with on-board 33-key keypad,
8-character display, two 8039microcontrollers, 2K bytes of user-program RAM, a serial port and cable, and
a ROM-based monitor which supervises the emulator operation and user interface. The emulator provides
a means for executing and debugging programs for the 8048/8049 family of microcontrollers at speeds up
to 11 MHz. It interfaces to a user-designed system through an emulation cable and 40-pin plug, which
replaces the MCS-48™device in the user's system. Using the HSE-49 keypad, a designer can run programs
in real-time or single-step modes, set up to 8000 breakpoint flags, and display or change the contents of
user program memory, internal and external data memory, and internal MCS-48 hardware registers. When
linked to a host Intellec® development system, the HSE-49 emulator system-debugging capabilities, with
the development system program assembly and storage facilities, provide the tools required for total
product development.
18-7
HSE·49
HIGH·SPEED EMULATOR
using the emulator'S capabilities to break emulation and to examine and change the user program
and processor status values. The completed
system may be final tested prior to ROM-code entry by replacing the HSE-49 emulation plug with a
programmed 874X device in the user-system
MCS-48 device socket, and running the system
(with crystal input and power supplied) at full
speed. Figure 1 shows a typical development configuration utilizing a host Intellec development
system and the HSE-49 emulator, with the emulation cable interface to a user-designed system.
FUNCTIONAL DESCRIPTION
The HSE-49 High-Speed Emulator is a stand-alone
execution and debugging tool for 8048/8049 family
microcontroller-based systems which are designed to run at speeds up to 11 M Hz_ It may be
used alone or with other Intel microcomputer
development system products to facilitate system
integration early in the product development cycle, in parallel with hardware and software development. The convenient two-way debugging
which early integration permits results in reduced
total development time and cost.
For enhanced system debugging capabilities the
designer may elect to use Intel's ICE-49™ incircuit emulator. The ICE-49 module permits realtime emulation of the user system up to 6 MHz,
and offers the added benefits of symbolic debugging, 255 instruction-cycle real-time trace, and full
emulation without the stack, interrupt or 1/0 limitations to which the HSE-49 emulator is subject
(see discussion under "Limitations" heading).For
further information on the ICE-49 emulator, refer
to the ICE-49™ In-Circui~ Emulator Data Sheet
(order number 305200).
System Development
SOFTWARE DEVELOPMENT
After an application program has been written in
MCS-48 assembly language, the HSE-49 emulator
may be used to debug software even if prototype
hardware is not yet available.
Stand-alone Mode
The designer first hand assemb'les the source
code from ASM-48 mnemonics into hex code, and
then loads the program into the HSE-49 emulator
user-program RAM through the or-board hex keypad, or through the serial port from a hex file
stored on a user-supplied peripheral device. The
emulator may then be used to execute the user
program in a variety of debugging modes, and to
alter the program as necessary. The altered program may then be uploaded to a user-supplied
storage device.
Development System Mode
With an Intellec development system, the designer assembles the source code using the
MCS-48 macroassembler and downloads the resulting hex file through the serial port and cable to
the HSE-49 emulator user-program RAM. The emulator is then used to execute and debug the program as above. Finally, the resulting program is
uploaded to the development system and stored
in a disk file.
Figure 1. Intellec® System Based HSE·49
Emulator Connected to User Prototype
System
Emulator Overview
EMULATION AND MASTER PROCESSORS
The user's program is emulated by an 8039 microprocessor, the emulation processor (EP), which
executes code that is stored in 2K bytes of external RAM for ease of program development. Additional RAM may be added by the user in the provided sockets to expand program and external
data memory to 4K bytes each.
HARDWARE/SOFTWARE INTEGRATION
Prototype hardware may be developed off-board
or on the wire-wrap area provided on the HSE-49
emulator board. The HSE-49 emulator interfaces
to the user-system hardware through the supplied
emulation cable, which plugs into the MCS-48
device socket in the user system. With the plug in
place, the emulator executes code from the userprogram memory and exercises the prototype
hardware. Additional hardware is added as it becomes available, and the system is debugged
A second microcontroller - an 8039 with off-chip
ROM program memory - is used to scan the onboard keypad and display, interpret and imple18-8
AFN·01658A
intel·
HSE·49
HIGH·SPEED EMULATOR
USER
SYSTEM
PROTOTYPE
Figure 2. HSE·49
Figure 3. HSE·49
Emulator Signal Flow Diagram
Emulator Command Keypad Organization
data RAM, accumulator, PSW, PC, timer/counter,
working registers, and internal RAM; executing
the user's program from arbitrary addresses in var·
ious debugging modes; and uploading or down·
loading object or data files from diskettes using a
host development system. No special software is
needed for the Intellec system other than ISIS II
Version 3.4 or later. The data format is compatible
with the standard Intel hex file format produced by
ASM-48; the baud rate may be altered from 110
baud (default state) up to 1200 baud from the. onboard keypad. Blocks of data may be transmitted
to a CRT or printer and displayed in a tabular format.
ment commands, drive serial interfaces, etc. In
general, this master processor (MP) is used to in·
terface the emulation processor's memory spaces
with the outside world and control the operation
of the EP. Figure 2 shows how the two processors
interrelate with the rest of the system. Figure 3
shows the layout of the 33·key keypad through
which the user interfaces to the emulator.
MP MONITOR
The monitor program executed by the MP includes commands for filling, reading, or writing
the various memory spaces, including the execution processor's program RAM, external ("MOVX")
18-9
AFN·01658A
inter
HSE·49
HIGH·SPEED EMULATOR
cution mode, and the EP is released to run at full
speed until the next break situation is encountered.
INTERPROCESSOR COMMUNICATION
An 8212 8-bit latch is used to communicate data
and commands between the master and emula'
tion processors_ Under control of the MP, this register, call the "Link" register, may be logically
mapped into either the program or data RAM address spaces. When this is done, the RAM in the
respective memory space is disabled and the link
responds to all accesses regardless of address.
Operation Modes
When the M P detects that the EP has been halted
by the breakpoint hardware, or when the operator.
presses a key while the program is executing, the
program break sequence is initiated. The loworder 23 bytes of user-program memory is read
into a buffer within the internal RAM of the MP. A
short program for reading and transmitting internal EP status is written into the low-order userprogram memory. (This is one of several "minimonitors" overlayed on the user-program area.)
The link register is mapped logically into the userprogram memory, and loaded with the 8049 machine code for a "CALL" instruction to the minimonitor program area. The EP is then allowed to
fetch a single instruction from the lihk, forcing the
"CALL" to the mini-monitor onto the EP data bus.
The link register is then mapped to the external
data RAM address space. A block diagram of the
system at this point is shown in Figure.4.
From this point on, the EP executes code contained in the mini-monitor which makes the EP accumulator, timer/counter and PSW values available to the MP (through "MOVX" instructions to
the link register) so that the EP internal status may
be saved in the MP internal data RAM. The MP
then loads a different mini-monitor into the same
EP program RAM area which allows it to read and
save the internal RAM of the EP.
The HSE-49 firmware is a ROM-based program
that provides the user with simple key-stroke commands .for initiating emulation, defining breakpoints, and displaying and controlling system
parameters, A summary of the HSE-49 emulator
commands is given ih Table 1.
SIX EMULATION MODES are provided by the
HSE-49 emulator to aid in hardware and software
debugging. The user may single-step through a
program or have the emulator automatically step
through the program with a user-defined idle time
between steps. Three real-time emulation commands allow 1) real-time emulation with breakpoints not enabled (a user-accessible pulse is
generated each time a breakpoint is encountered,
however, facilitating user-defined logic analysis),
2) real-time emulation with breakpoints enabled,
and 3) real-time emulation with automatic breakpointing, whereby the emulator executes in real
time between breakpoints, and pauses at each
breakpoint for a user-defined time before automatically resuming real-time emulation. A final
command initiates real-time execution, beginning
emulation at user-program location OOOH, from
the Emulator Processor hardware reset state.
BREAKPOINTS may be set at any combination of
program memory and external data memory address locations from OOOH to FFFH. This unlimited capability to specify breakpoints for all
possible combinations of addresses complements the somewhat different breakpointing
features available with the ICE-49 emulator.
At this point, the HSE-49 emulator may be interrogated or given instructions by the operator from
the hex keypad. The emulator operation remains
transparent to the user, who need not be concerned, for example, with the actual (altered) location of the EP low-order program RAM or internal
data RAM.
The ICE-49 emulator permits the symbolic specification of breakpoints on program memory and external data memory addresses, or external data
memory address reads or writes individually, and
upon the input of an external synchronization sig~
nal.
In order to' resume user-program execution, a
status restoration mini-monitor is overlayed. This
restores the EP internal status using a scheme
analogous to the one in which the status was originallysaved. The final step of the last mini-monitor
is an ~'RETR" instruction, after which the EP is
again halted. The low-order program memory
saved earlier is rewritten into the appropriate area,
the break logic is configured for the desired exe-
INTERROGATION AND UTILITY commands are
provided by the HSE-49 emulator which allow the
user to examine, change or fill the various emulator memory spaces. Additional commands are
provided to upload or download the contents of
the memory spaces to or from a host Intellec development system, or other peripheral device,
through the HSE-49 emulator serial port.
18-10
AFN·01658A
intel'
HSE·49
HIGH·SPEED EMULATOR
EXECUTION
PROCESSOR
MASTER
PROCESSOR
Figure 4.. Communication between EP and MP
Table 1. HSE·49
Emulator Command Description
Command
Modifier
Command
Description
Begins emulation:
GO
NO BRK
Real·time breakpoints not enabled
W/BRK
Real-time breakpoints enabled
SING STP
Steps program one instruction
AUTO STP
Automatically steps/pauses/steps/ ...
AUTO BRK
Automatically emulates real·time/pauses at breakpoint/emulates realtime/ ...
GO/RESET
(NONE)
Begins real-time emulation from EP hardware reset state, beginning at
program location OOOH
B,C
(PROG MEM, DATA MEM)
Sets (B) or Clears (C) breakpoint at specified address within Program or
External Data memory
SYS RST
(NONE)
Resets emulation and master processors and clears all breakpoints
·
·
·
·
·
..
EXAM/CHA
FILL
LIST
DNLOAD
UPLOAD
PROG MEM
Examine/Change memory location
Fill range of memory addresses with a single data value
List memo·ry to output device through HSE-49 serial port
Download hex-file format memory to HSE-49 emulator through HSE-49
serial port
Upload memory within a range of addresses through HSE-49 serial port
to Intellec Development System or external peripheral device
.
= Memory types allowed for above commands:
User-program memory
DATA MEM
External data memory (if installed)
PROG BRK
User-program breakpoint memory
DATA BRK
External data breakpoint memory
REGISTER
Register memory and internal data memory
HARD REG
Hardware registers/system control parameters
18-11
AFN·01658A
HSE·49
HIGH·SPEED EMULATOR
dress within an interrupt servicing routine; if it
is, the EP may incorrectly recognize an interrupt request which should be ignored.
Limitations
The HSE-49 emulator was not designed to have
the same capab'ilities that Intel's ICETMin-circuit
~mulators have, and certain features have been
deleted to keep the circuitry relatively simple. Asa
result, the following limitations exist and should
be taken into account when using the s'ystem,
3. The 1/0 status of ports PO and P22-P23 with respect to user-supplied hardware is determined
by the HSE-49 emulator hardware configuration
rather than by software. Therefore the 1/0
modes of these ports may not be altered while
a program is executing. These ports may be
configured as is inputs, latched outputs or bidirectional ports by changing socketed HSE-49
emulator hardware.
1. As explained previously, user-program execution is terminated by forcing the EP to execute
a "CALL" instruction to the mini-monitor. Because this requires one level of the EP subroutine stack, the user program can be using a
maximum of seven levels of stack when a break
is initiated.
4. The "ANL BUS, #nn" and "DRL BUS, #nn" instructions may not be used in the user program, as external hardware cannot properly
restore these functions.
2. Because program execution is initiated by forc,
ing the EP to execute an "RETR" instruction,
the EP interrupt-in-progress flip-flop will be
cleared. Therefore, if interrupts are enabled,
emulation should not be resumed from an ad-
Several other minor I,imitations with the HSE-49
emulator operation are explained in the Operating
Instructions.
SPECIFICATIONS
Physical Characteristics
Equipment Supplied
Width: 14.0 in (35.6 cm)
Length: 10.0 in. (25.4 cm)
Height 0.5 in. (1.27 cm)
Packaged Weight: 4.0 Ib (1.8 kg)
Printed Circuit Board with Integral Keypad, Display, ROM Monitor, (2) 8039 microprocessors and
2K bytes user program RAM
,.
Emulation Cable and Plug
Serial-Link Cable
Power Pick-up Card with Cable
Power Cable
'
D.C. Electrical Characteristics
vee =+5V ±5%
lee
= 2.0A max; 1.5A typical
VRS232= +12V ±5%; -12V ±5%
IRS232= 0.020A max; 0.015A typical
(VRS232 required only if using RS232 mode of
serial port)
Emulaticln Clock
11 MHz supplied, or user supplied crystal for 3.6
MHz to 11 MHz clock
. ,
Environmental Characteristics
Operating Temperature: O· to 55·C
Serial 1/0
20 rnA Current Loop or RS232 (jumper seleCtable)
ORDERING INFORMATION
Part Number
Desc~i_ption
MCI-49-HSE
8048/8049 family CPU highspeed (11 MHz) emulator, cable
assembly and ROM firmwlue
18-12
Operating Humidity: Up to 90% relative humidity
'
without condensation
ICE·49
MCS·48 IN·CIRCUIT EMULATOR
Emulates 8049, 8048, 8748, 8039, 8035, and 8021* MIcrocomputers
Extends Intellec microcomputer develop·
mentsystem debug power to user con·
figured system via external cable and
40·pln plug, replacing system MCS·48
device
Emulates user system MCS·48 device in
real time
Eliminates need for extraneous debug·
ging tools residing in user system
Collects bus, register, and MCS·48
status information on instructions
emulated
Shares static RAM memory with user
system for program debug
Provides capability to examine and alter
MCS·48 registers, memory, and flag
values, and to examine pin and port
values
Provides hardware comparators for user
designated break conditions
Integrates hardware and software efforts
early to save development time
The ICE-49 MCS-48 In-Circuit Emulator module is an Intellec-resident module that interfaces with any MCS-48 system.
The MCS-48 family consists of the 8049,8048,8748,8039,8035, and 8021 microcomputers. The ICE-49 module interfaces with an MCS-48 system through a cable terminating in an MCS-48 pin-compatible plug which replaces the
MCS-48 device in the sytem. With the ICE-49 plug in place, the designer has the capability to execute the system in.
real time while collecting up to 255 instruction cycles of real-time trace data. In addition, he can single step the system
program to monitor more closely the program logic during execution. Static RAM memory is available through the
ICE-49 module to emulate MCS-48 program and data memory. The designer can display and alter the contents of data
and replacement RAM control memory, internal MCS-48 registers and flags and 1/0 ports. Powerful debug capability is
extended into the MCS-48 system while ICE-49 debug hardware and software remain inside the Intellec system. Symbolic reference capability allows the designer to use meaningful symbols rather than absolute values when examining
and modifying memory, registers, flags, and 1/0 ports in this system.
*EM1 emulator board is also required.
18-13
AFN-01103A-01
ICE-49
FUNCTIONAL DESCRIPTION
Integrated Hardware/Software Development
Debug Capability Inside User System
The ICE·49 module provides the user with the ability to
debug a full prototype or production system without
introducing extraneous hardware or software test tools.
The module connects to the user system through the
socket provided for the MCS·48 device in the user
system. Intellec memory is used for the execution of the
ICE·49 software. The Intellec console and file handling
capabilities provide the designer with the ability to com·
municate with the ICE·49 module and display informa·
tion on the operation of the prototype system. The
ICE·49 module block diagram is shown in Figure 1.
Batch Testing
In conjunction with the ISIS·II diskette operating
system, the ICE·49 module can run extensive system
diagnostics without operator intervention. The designer
or test engineer can define a complete diagnostic exer·
cise, which is stored in a file on the diskette. When actio
vated with an ISIS·II submit command, this file can
instruct the ICE·49 module to execute the diagnostic
routine and store the results in another file on the
diskette. Results are available to the designer at his con·
venience. In this way, routine diagnostics and long term
testing may be done without tying up valuable man·
power.
The user prototype need consist of no more than an
MCS·48 socket and timing logic to begin integration of
software and hardware development efforts. Through
the ICE·49 module mapping capabilities, Intellec system
resources can be accessed to replace prototype memo
ory. Hardware designs can be tested using the system
software to drive the final product. Thus, the system in·
tegration phase, which can be costly when attempting
to mesh completed hardware and software products,
becomes a convenient two·way debug tool when begun
early in the design cycle.
Real-Time Trace
The ICE·49 module captures trace information while the
designer is executing programs in real time. The instruc·
tions executed, program counter, port values for bus 0,
port 1 and port 2, and the values of selected MCS·48
status lines are stored forthe last 255 instruction cycles
executed. When retrieved for display, code is disassem·
bled for user convenience. This provides data for deter·
mining how the user system was reacting prior to emu·
lation break, and is available whether the break was user
initiated or the result of an error condition. For more
detailed information on the actions of internal registers,
flags, or other system operations, the user may operate
in Single or multiple step sequences tailored to system
debug needs.
CONTROL PROCESSOR BOARD
EMULATOR BOARD
-------1 r------------I
I
II
I
r-'--'---,.JI-------l
II
I
USER SOCKET
SYNC 0
I
CABLE
BUFFER
SYNC 1
I
II
I
II
II
II
II
I
I
I
I
I
I
f---,--"':::.::..:.:;
II
I I
Pl
P2A
8049 OR 8048
W/INTERNAL
MONITOR P~~t---------::-:-:::-:---'
8080
CONTROL
PROCESSOR
~
~
~
~
....~
~
I
I
L __ _
w
~
II
I
I
CONTROL
PROGRAM
I
I
I
I
I
I
I
I
I
I
II
I
_______ .J L____________ --.J
Figure 1. ICE·49 Module Block Diagram
18-14
AFN-Q1103A-02
ICE·49
Memory Mapping
The 8049, 8748 and 8048 contain internal program and
data memory. Both program and data memory can be
expanded using external memory devices.
Internal Memory - When the MCS-48 microcomputer is
replaced by the ICE-49 socket in a system, the ICE-49
module supplies static RAM memory as a replacement
for the internal microcomputer memory. The ICE·49
module has enough RAM memory available to emulate
up to the total 4K control memory capability of the system. The ICE-49 module also provides for up to 384
bytes of data memory.
External Memory - The ICE-49 module separates
replacement control memory into sixteen 256-byte
blocks. Replacement external data memory consists of
one 256·byte block. Each block of memory can be defined separately as supplied by the user system or supplied by the ICE-49 module. The user may assign ICE-49
equivalent memory to take the place of external memory
n.ot yet supplied in his system.
Symbolic Debugging
ICE-49 software provides symbolic definition of all
MCS-48 registers, flags, and selected MCS-48 pins.
Symbolically defined pseudo registers provide access
to the sense of MCS-48 flip flops which enable time,
counter, interrupt, and flag-0/flag-1 options. In addition,
the user may reference locations in program and data
memory, or their contents, symbolically. The user,symbol table generated along with the object file during a
program assembly may be loaded to Intellec memory for
access during emulation. The user is encouraged to add
to this symbol table any additional symbolic values for
memory addresses, constants, or variables he may find
useful during system debugging. Symbols may be sub'
stituted for numeric values in any of the ICE-49 commands. Symbolic reference is a great advantage to the
system designer. He is no longer burdened with the
need to recall or look up those addresses of key locations In his program that can change with each assembly. Meaningful symbols from his source program may
be used instead. For example, the command:
GO FROM .START TILL XDATA. RSLT WRITTEN
begins execution of the program at the address referenced by the label START in the designers assembly
program. A breakpoint is set to occur the first time the
microprocessor writes to the external data memory
location referenced by RSLT. The designer does not
have to be concerned with the physical locations of
START and RSLT. The ICE-49 software driver supplies
them automatically from information· stored in the
symbol table.
Hardware
The ICE-49 module is a microcomputer system utilizing
Intel's 8049 or 804818748 microcomputer as Its nucleus.
The 8049 provides the 8049, 8039 emulation characteristics. The 8048/8748 provides the 874818048/8035/8021
emulation characteristics. The ICE-49 module uses an
18·15
Intel 8080 to communicate with the Intellec host pro·
cessor via a common memory space. The 8080 also controls an InternallCE-49 bus for Intramodule communica·
tlon. ICE-49 hardware consists of two PC boards, the
controller board, and the emulator board, all of which
reside in the Intellec chassis. A cable interfaces the
ICE·49 boards to the MCS·48 system. The cable terminates In a MCS·48 pin compatible plug which
replaces any MCS·48 device in the user system. The
ICE-49 module block diagram is shown in Figure 1.
Real·Time Trace
Trace Buffer - While the ICE·49 module is executing
the user program, it is monitoring port, program
cou!lter, data, and status lines. Values for each instruction cycle executed are stored in a 255 x 44 real-time
RAM trace buffer. A resetable timer resident on the controller board counts Instruction cycles.
Controller Board
The ICE-49 module talks to the Intellec system as a
peripheral device. The controller board receives commands from the Intellec system and responds through
the parameter block. Three 15-bit hardware breakpoint
registers are available for loading by the user. While in
emulation mode, a hardware comparator is constantly
monitoring address and status lines for a match to terminate an emulation. The breakpoint registers provide a
signal when a match is detected. The user may disable
the emulation break capability and use the signal to synchronize other debug tools. The controller board returns
real-time trace data, MCS-48 register, flag, and pin
values, and ICE-49 status information, to a control block
in the Intellec system when emulation is terminated.
This information is available. to the user through the
ICE-49 interrogation commands. Error conditions, when
present, are automatically displayed on the Intellec
system console. The controller board also contains
static RAM memory, which can be used to emulate
MCS-48 program and data memory in real time. 4K of
memory is available in sixteen 256·byte pages to emulate MCS-48 PROM or PROM program memory. A 256·
byte page of data memory is available to access In place
of MCS-48 external data memory. The controller board
address map directs the ICE-49 module to access either
replacement ICE-49 memory or actual user system external memory in 256·byte segments based on informa·
tion provided by the user.
Emulator Board
The emulator board contains the 8049* and peripheral
logic required to emulate the MCS-48 device in the user
system. A software selectable 6 MHz or 3 MHz clock
drives the emulated MCS-48 device. This clock can be
disabled and replaced with a user supplied TTL clock in
the user system.
·Use 8048 with internal monitor program when emulating 8748180481
803518021.
AFN-DllD3A-D3
ICE·49
Cable Card
The cable card is included for cable driving. It transmits
address and data bus information to Ihe user system
through a 40-pln connector which 'plug's Into the user
system in the socket designed for the MCS-48 devlc,e.
Command
Operation
Display
Prints contents of memory; MCS-48
device registers, 1/0 ports, flags,' pins,
real-time trace data, symbol table, or
other diagnostic data on lis/device:
Alters contents of memory, register,
output port, or flag: Sets of alters breakpoints and display registers,
'
Defines memory status.' "
,
Establishes mode of display for,output
data.
Establishes mode of display input data"
Change
Software
The ICE-49 software driver Is a RAM-based program
which provides the user with an easy to use command
language (see Table 1, Table 2, and Table 3) for defining
breakpoints, initiating real-time emulation or single step
operation, and interrogating and altering user system
status recorded during emulation. The ICE-49 command
language contains a broad range cif modifiers to provide
the user with maximum flexibility in defining the operation to be performed. The ,ICE-49 software driver, ill
available on diskette' and operates in 321< of Intellec
RAM memory.
Go
Step
Interrupt
Suffix
Table 2. ICE·1I9 Interrogation Commands
Operation
Command
Load
Operation
Save
Activates breakpoint and display registers for ,use with go and step com·
mands.
Initiates real-time emulation and allows
user to specify breakpoints and data
retrieval.
Initiates emulation in Single instruction
increments. Each step is followed by
register dump., User may optionally
tailor other 'diagnostic activity 10 his
needs':
Emulates user system interrupt.
I,' Define
Command
Enable
M?p
Base
,Molle
List
Exit
Evaluate
Remove
Reset
Fetches user symbol table and object
code from 'input device.
''
Sends user symbol table and object
code to output device.
Enters symbol mime and vi;lIueio\lser
symbol table.·
'
Moves block of memory data to another,
area of memory,
.'
,Defines list device.:
Returns program control to ISIS-II.
Converts "expression to' equivalent'
values in binary, octal" deci'mal, and:
hex.
, '
Deletes symbols from symbol tllble.
Reinitializes ICE-49 hardware.
Table 3_ ICE-lI9 Utility Commands
Table 1.ICE·49 Emulation Commands
SPECIFICATIONS
System Clock
ICE·49 Operating Environment,
Crystal controlled 6.0 MHz Internal, 3.0 MHz internal or
user supplied TIL external: software selectable,
Required Hardware
Intellec microcomputer development system
System console
Intellec diskette operating system
ICE-49 Module
Physical Characteristics
Width '.:,.. 12.00 in. (30.48 cm)
Height - 6.75 in. (17_15 cm)
Depth - 0.50 In. (1.27 em)
Welght- 8.00 Ib_ (3.64 kg)
Required Software
System monitor
ISIS-II
Electrical Characteristics
Equipment Supplied
Printed circuit boards (control board, emulator' board)
Interface cables and buffer module
ICE-49 software, diskette-based version (single density
or double density)
8048 with internal monitor program
18-16
DC Power Requirements
Vee = +5V ±5%
Icc = 10A r:nax; 7.0A typ
Voo= +12V±5%,
100 = !~ mA max; 45 mA typ
Vee,= :.. 10V ± 5'Yo
lee =:= 20 mA max
AFN-01103A-04
ICE·49
Input Impedance - @ ICE·49 user socket pins:
VIL = 0.8V (max), IlL = -1.6 mA,
VIH = 2.0V (min), IIH = 40/AA
For Bus:
VIL = 0.8V (max), IlL = -250/AA
VIH = 2.0V (min), IIH = 20/AA
Environmental Characteristics
Operating Temperature perature)
Operating Humidity without condensation
Output Impedance - @ ICE·49 user socket pins:
P1, P2:
VOL
0.5V (max), IOL
16 mA
VO H = Vee (10K pullup)
=
=
=
=
ORDERING INFORMATION
Description
MDS·49·ICE
8049,8048,8039,8748,8035,8021
CPU in·circuit emulator. Cable
assembly and interactive diskette
software Included
ICE·49 Operator's Manual (SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers"
Avenue, Santa Clara, California 95051.
= 16 mA
= -400/AA
Part Number
Up to 95% relative humidity
Reference Manuals
9800632 -
For Bus:
VOL = 0.5V (max), IOL = 25 mA
VOH = 3.65V (min), IOH = -1 mA
Others:
VOL
0.5V (max), IOL
VOH" 2.4V (max), IOH
O°C to 40°C (Room Tem·
18-17
EM1
802,1 EMULATION BOARD
EPROM functional equivalent of 8021 single component 8·bit microcomputer
Based oi18748 - user programmablel
erasable. E~ROM 8·bitcomputer
Operates with ICE·49™ module to provide
full in·circuit debugging of 8021 prototype
system
Connects to prototype system through
8021 pin compatible plug
On·card 3.0 MHz or external TTL driven
clock
Portable 4" x 7" microcomputer circuit
assembly
The EM1 emulator board is a ready-to-use 4" x 7" microcomputer circuit assembly that emulates the Intel 8021
microcomputer. A 12-inch flat-cable assembly connects the board to the 8021 socket in a prototype system. The board
is designed so that it can be mounted either as a stand-alone unit, or within the prototype assembly.
The 8021 microcomputer has 1K x 8 mask-programmable ROM program memory and 64 by 8 RAM data memory. The
EM1 is controlled by an Intel 8748, with 1K of EPROM program memory and a 64 byte data memory. The EPROM can be
programmed and erased repeatedly during hardware and software development. The EM1 has several ancillary circuits
that perform the following functions which are specific to the 8021:
.
Zero crossing detector
Crystal controlled clock/buffer
Port 0 simulator
For prototype debugging, the 8748 can be removed from its socket and replaced with a cable to an ICE-49 module.
When used with the EM1, ICE-49 module emulates the 8021 in real-time, or single-steps the 8021 program at the user's
command. A full range of capabilities for examining and modifying 8021 memory and status are supplied through
ICE-49 module.
18·18
AFN-OOS01A-01
EM1
HARDWARE
Zero Cross Detection Simulator
The EM1 emulation board uses the 8748 to perform the
emulation.
PO Simulator
Port 0 of the 8021 is a quasi*-bidirectional port. The PO
simulator converts the data bus of the 8748 into a quasi·
bidirectional port.
Crystal Control Clock Buffer
The zero cross detection simulator enables the 8748's
T1 input to detect zero-crossings. The circuitry provides
a high level signal on a positive crossing and a low level
signal on a negative crossing of zero to the T1 input of
the 8748.
Reset Buffer
The 8021 resets on a logic HIGH level signal. However,
the 8748 resets on a logic LOW level, thus an inverter is
provided on the EM1 to make the two chips compatible.
The EM1 allows user to select an on·board oscillator or a
TTL clock driven from the 8021 user's prototype system
via a Cambion Suitcase jumper.
Jumper
W1
Position
State
A- B
On·Board
External
TTL Clock
C-D
* A bidirectional port which serves as an input port, output port, or both even though outputs are statically
latched.
Optional Pull·Ups
Resistors are provided to simulate the optional pull·up
resistors on T1 input and Port 0 of the 8021. A removable
resistor pack is used on Port O. The T1 input pull up can
be installed by soldering in a 50K resistor.
Software
When emulating the 8021 with EM1, the user must
observe the 8021 instruction set.
DB0- DB7
P10 - P17
P20- P28
ALE
8748
OR
40-PIN
PLUG
40
LINES
8021
CABLE
PLUG
PROG
CABLE TO
ICE·49
MODULE
12 INCHES
FLAT CABLE
XTALl
~-------------,---;Tl
Tl~~------~------i
RESETt---r--------------------------<<:
~----+----1 RESET
,.,..--..,
I
I
RESET BUFFER
roiiiC:'ARD'"
I
CLOCK
L
2!:!1~...J
28
LINES
I
:
28-PIN
SOCKET
OPTIONAL
L PULL-UP
_ _ ...J
18·19
AFN~00801 A-02
EM1
SPECIFICATIONS
Operating Environment
Stand-Alone
Required Hardware:
EM1 emulation board
In-Circuit Emulation
Required Hardware:
EM1 emulation board
Intellec Microcomp\lter DEivelopment System configurated with ICE-49 module
.
Equipment Supplied
System Clock
Crystal controlled 3_0 MHz on board or user supplied
TTL extermilclock: hardware jUmper selectable_
Physical Characteristics
Width: 7_0 in (17_78 cm)
Height: 4.0 in. (10:16 cm)
Depth: 0.75 in, (1.91 cm)
Weight: < 1.0 Ibs. (0.45 kg)
Electrical Characteristics
DC Power:
Vcc5V ±5%
Icc 300 mA (max.)
EM1 printed circuit board
Environmental Characteristics
12" long flat cable terminating in 28-pin plug, pin compatible with 8021
Operating Temperature: 0 -.55°C
EM1 Operator's Manual
Operating Humidity: up to 95%
without con.densation
relative humidity
ORDERING INFORMATION
PART NUMBER
Description
MDS-EM1
8021 Emulation Board
18-20
AFN-OOB01A-03
inter
EM2
8022 EMULATION BOARD
Portable 4.25" x 2.75" microcomputer
circuit assembly
Provides Intel® 8755A -
Connects directly into prototype system
through Intel® 8022* pin compatible
socket
EPROM functional and electrical
equivalent of Intel® 8022 - single
component 8·bit computer
2K x 8 EPROM
The EM2 emulator board is a ready-to-use 4.25" x 2.75" microcomputer circuit assembly that emulates the Intel® 8022
single chip microcomputer. The emulator board is designed to plug directly into the 8022 socket. No interfacing and
interconnection cables are necessary. Power is obtained from the user's system.
The EM2 emulator board provides the user a full EPROM functional and electrical equivalent of the 8022 single component 8-bit microcomputer.
The EM2 emulator board consists of an Intel® 8022 emulator chip and an Intel® 8755A, providing the EM2 emulator
board with a 2K x 8.EPROM program memory which can be programmed and erased repeatedly during hardware and
software development.
The 8022E emulator chip is a modified version of the 8022 intended for use in design support systems. Instead of
using resident ROM memory as the 8022, the 8022E uses an external 2K EPROM 8755A memory for program storage,
allowing easy program modification.
'See Intel® 8022 Data Sheet.
EM2
EM2 BLOCK DIAGRAM
40·PIN SOCKET CONFIGURATION
P26
Vee
P27
P25
AVec
P24
PROG
VAREF
AN1
P23
ANO
P22
AVss
P21
TO
P20
VTH
P17
POO
P16
P01
P15
P02
P14
P03
P13
P04
P12
P05
P11
P06
P10
P07
RESET
ALE
XTAL2
T1
XTAL1
Voo
SUBST
o
,--,--1
40·PIN
SOCKET
8755A
8022 EMULATOR CHIP
o
PIN 1
SQUARE SOLDER PAD
PIN DESCRIPTION
Desig·
nation
Pin 1#
Desig·
nation
Function
Vss
20
Vee
40
+ 5V circuit power supply.
PROG
37
Output strobe for Intel® 8243 1/0 ex·
pander.
9
Pin 1#
Function
RESET
24
Input used to initialize the processor
by clearing status flip·flops and setting
the program counter to zero.
AVss
7
AID converter GND potential. Also
establishes the lower limit of the con·
version range.
AVec
3
AID
SUBST
21
Substrate pin used with a bypass capa·
citor to stabilize the substrate voltage
and improve AID accuracy.
VAREF
4
AID converter reference voltage. Estab·
lishes the upper limit of the conversion
range.
ANO,
AN1
6,5
Analog inputs to AID converter. Soft·
ware selectable on·chip via SEL ANO
and SEL AN1 instructions.
ALE
18
Address Latch Enable. Signal occur·
ring once every 30 input input clocks
(once every single cycle instruction),
used as an output clock.
XTAL1
22
One side of crystal, inductor, or reo
sistor inputfor internal oscillator. Also
Input for external frequency source.
(Not TTL compatible.)
XTAL2
23
Other side of timing control element.
This pin is not connected when an ex·
ternal frequency source is used.
Circuit GND potential.
POO-P07 10-17 8·bit open·drain port with comparator
Port 0
inputs. The switching threshold is set
externally by VTH . Optional pull·up reo
sistors may be added via ROM mask
selection. (The emulator board has
switch selection of this option.)
VTH
2048
EPROM
MEMORY
+ 5V power supply.
Port 0 threshold reference pin.
P10-P17 25-32 8·bit quasi·bidirectional port.
Port 1
P20-P27 33-36 8·bit quasi·bidirectional port.
Port 2
TO
T1
38-39 P20-P23 also serve as a 4·bit 1/0 ex·
1-2 pander for Intel® 8243.
8
19
Interrupt input and input pin testable
using the conditional transfer instruc·
tions JTO and JNTO. Initiates an inter·
rupt following a low level input if inter·
rupt is enabled. Interrupt is disabled
after a reset.
Input pin testable using the JT1 and
JNT1 conditional transfer instructions.
Can be designated the timerlevent
counter Input using the STRT CNT In·
struction. Also serves as the zero·cross
detection input to allow zero·crossover
sensing of slowly moving AC inputs.
Optional pull·up resistor may be added
via ROM mask selection.
18-22
AFN-OOBOOA-02
EM2
On the EM2 Board:
The Intel'" 8755A EPROM can be programmed using any
of the modules listed in Table 1.
Module
Description
UPP-103
Universal PROM Programmer.
Requires UPP·955, which in·
eludes 8755A Personality Card
with 40·pin adapter socket.
PROMPT-48
Intel lee'" MCS·48 Microcomputer Design Aid. Requires
PROMPT-475 Programming
Adapter.
PROMPT·80/85
The 8755A EPROM is erased when exposed to light with
wavelengths shorter than approximately 4000 Ang·
stroms (A). Sunlight and certain fluorescent lamps have
wavelengths in the 3000A to 4000A range. If the 8755A is
to be exposed to sunlight or room fluorescent lighting
for extended periods, then opaque labels should be
placed over the window to prevent unintentional
erasure.
The recommended erasure procedure is exposure to
ultraviolet light which has a wavelength of 2537 A. The
integrated dose (UV intensity multiplied by exposure
time) for erasure should be a minimum of 15W-sec/cm.
The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with a 12,0001'
W/em 2 power rating. Place the 8755A within one inch of
the lamp during erasure. Some lamps include a filter
which should be removed before erasure.
Intellec'" 8080/8085 Microcomputer Design Aid. Requires
PROMPT-975 Programming
Adapter.
Table 1. 8755A Proramming Module
Physical Characteristics
SPECIFICATIONS
Width: 2.75 in. (6.98 em)
Height: 4.25 in. (10.79 em)
Depth: 1.5 in. (3.81 em)
Weight: 0.5 Ib (0.23 kg)
Operating Environment
Intel'" 8755A EPROM Programming
UPP·103
PROMPT·48
PROMPT-80/85
Electrical Characteristics
Intellec Microcomputer Development System
DC Power
Vcc=5V ±5%
Icc = 300 mA (maximum)
Software
8048 Assembler
ISIS-II Diskette Operating System
Environmental Characteristics
Equipment Supplied
Operating Temperature - 0 to 55°C
EM2 Printed Circuit Board
EM2 Reference Manual
Operating Humidity without condensation
Up to 95% relative humidity
ORDERING INFORMATION
Part Number
Description
MDS-EM2
8022 Emulation Board
18-23
AFN·ooaOOA-03
inter
ICE·22™
8022 IN·CIRCUIT EMULATOR
• Single·line assembler allows mnemonic
program instruction changes
• Full symbolic debugging
• 500 instruction cycle· trace
conditionally triggered
-16 user·definable trace probes
- symbolic groupings and display
• ICE™·resident user·program RAM for
real·time execution
• 32·bit half·microsecond emulation
timer
• Examine and alter 8022 registers,
memory, and digital port values, and
examine analog port data
• HELP facility summarizes ICE·22™
command syntax at the console
• Two user·specified breakpoint registers
• User confidence test of ICE·22™
hardware
The ICE-22 module resides in the Intellec® Microcomputer Development System and interfaces to any
user-designed 8022 system through a cable terminating in an 8022 emulator microprocessor and a pincompatible plug. The emulator processor, together with 2K bytes of user-program RAM located in the
ICE-22 buffer box, replaces the 8022 device in the user system while maintaining the 8022 electrical and
timing characteristics. Powerful Intellec debugging functions are thus extended into the user system.
Using the ICE-22 module, the designer can emulate the system's 8022, including full AID converter function, in real-time or single-step mode. Breakpoints allow the user to stop emulation on user-specified conditions, and a trace qualifier feature allows the conditional collection of 500 instruction cycles of trace
data. The ICE-22 trace includes 8022 status information and, through ICE-22 external logic probes, can
provide data on up to 16 signal nodes in the user-system peripheral circuitry. For the first time in any ICE
module, the designer may alter program memory using ASM-48 mnemonics and symbolic referen'ces
without returning to ISIS II control. In addition, user-created peripheral chip analyzer routines may be applied to the logic probe data, thereby expanding the in-circuit emulation function to the entire system.
18-24
inter
ICE·22™ IN·CIRCUIT EMULATOR
FUNCTIONAL DESCRIPTION
Integrated Hardware/Software
Development
The ICE-22 emulator allows hardware and software development to proceed interactively_ This is
more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-22 module, prototype hardware can be added to the system as it is designed. Software and hardware testing occur while the product is being developed.
Conceptually, the ICE-22 emulator assists three
stages of development:
It can be operated without being connected to
the user's system, so ICE-22 debugging capabilities can be used in. conjunction with the
Intellec text editor and MCS-48™ macroassembler to facilitate program development
before any of the user's hardware is available.
Integration of software and hardware can begin
when any functional element of the user systemhardwareis connected to the 8022 socket.
As each section of the user's hardware is completed, it is added to the prototype. Thus,each
section of the hardware and software is "system" tested as it becomes available.
When the user's prototype is complete, it is
tested with the final version of the user system
software. The ICE-22 module is then used for
real-time emulation of the 8022 to debug the
system as a completed unit, and verify system
performance before any ROM codes are entered. A final product verification test may be
performed prior to ROM code entry by using the
separately available EM-2 8022 emulation board
(8022 EPROM equivalent) within the eventual
product package.
For each symbol that is used for memory reference in an ICE-22 emulator command, the emulator supplies the symbol value location as stored in
the ICE-22 emulator symbol table. This table can
be loaded with the symbol table produced by the
assembler during application program assembly.
Furthermore, the user can interactively modify the
emulator symbol table by adding new symbols or
changing or deleting old ones. This feature provides great flexibility in debugging and minimizes
the need to work with hexadecimal values.
Through symbolic references in combination with
other features of the emulator, the user can easily:
• Disassemble program memory to mnemonics
• Assemble mnemonic instructions into executable code.
e Examine or modify 8022 internal registers, data
memory, or digital port contents.
• Examine analog port data
• Symbolically define groups of user probes, and
use these groups to symbolically specify breakpoints and trace qualifiers, or to format external
trace data output.
Operation Modes
The ICE-22 software is a RAM-based program that
provides the user with easy-to-use commands for
initiating emulation, defining breakpoints, controlling trace data collection, and displaying and
controlling system parameters. ICE-22 commands
are configured with a broad range of modifiers
which provide the user with maximum flexibility in
describing the operation to be performed.
EMULATION
Thus, the ICE-22 module provides the user with
the ability to debug a prototype or production system at any stage in its development without introducing extraneous hardware or software test
tools.
Symbolic Debugging
The ICE-22 emulator permits the user to define
and use symbolic rather than absolute references
to program and data memory addresses; additional symbols are predefined by the ICE-22 software for referencing registers, flags, and input!
output ports. Thus, the user need not become involved with machine code, or recall or look up the
addresses of key locations in his program as they
change with each assembly.
The ICE-22 module can emulate the operation of a
prototype 8022 system, including full emulation of
the 8022 analog to digital converter, at real-time
speed (0.6 to 3.6 MHz) or in single or multiple
steps. Emulation commands to the ICE-22 module
control the process of setting up, running, and
halting an emulation of the user's 8022-based
system. Breakpoints, comparison registers, and
tracepoints enable 'the ICE-22 emulator to halt
emulation and provide a detailed trace of execution in any part of the user's program. A summary
of the emulation commands is shown in Table 1.
Breakpoints
The ICE-22 hardware includes two breakpoint registers that allow the user to halt emulation when
specified conditions are met. The emulator continuously compares the values stored on the
breakpoint registers with the status of specified
18-25
AFN-01586A
ICE·22™ IN·CIRCUIT EMULATOR
data, addresses, and/or external logic probes, and
halts emulation when this comparison is satisfied. When an instruction initiates a break, that instruction is executed completely before the break
takes place. The ICE·22 emulator then regains
control of the console and enters the Interrogation Mode. With the breakpoint feature, the user
can request an emulation break when his program:
• Executes an instruction at a specific address or
within a range of addresses
• Executes a particular opcode
• Receives a specific signal on a logic probe, digital port pin, or group of probes or pins
• Fetches a particular data value from the user
program memory
Breakpoints can be composed of conditions on 22
channels which reflect internal 8022 activities,
plus the 16 external logic probe channels; all but
one of the channels may be specified as "Don't
Care" channels. Address ranges must be specified as a range of pages (rOOH) to sFFH), a range of
16-byte paragraphs within a page (prOH) to psFH),
or a range of bytes within a paragraph (pqrH to
pqsH) where, in each case, s is a digit greater than
or equal to the digit r.
Table 1. Major Emulation Commands
Command
Trace and Tracepoints
Tracing is used with both real-time and singlestep emulation to record diagnostic information in
the trace buffer as a program. is executed. The information collected includes opcodes executed,
program counter and Port 2 values, and 16 logic
probe values for the la!;t 500 instruction cycles.
(There are one or two cycles per instruction, depending on the particular instruction.) This information can be displayed as assembler instruction
mnemonics, if desired, for analysis during Interrogation or Single-Step Mode. The trace-collection
facility may be set to run conditionally or unconditionally. One unique trace qualifier, specified in
the same way as a breakpoint, governs conditional
trace activity. It can be used to condition trace
data collection to take place as follows:
• Under all conditions (constantly occurring)
• Only while the trace qualifier is satisfied
• For the 500 instruction cycles preceding the
time when a.trace qualifier is first satisfied (pretriggered trace)
• For the next 500 instruction cycles after a trace
qualifier is first satisfied (post triggered trace).
Description
GO
Begins real-time emulation and op·
tionally specifies break conditions.
BRa, BR1, BR
Sets or displays either or both
Breakpoint Registers used for stop·
ping real-time emulation.
STEP
Begins single·step emulation and
optionally specifies terminating
conditions.
CRO, CR1,
CR2, CR3, CR
Sets or displays comparison cri·
teria in all or individual Comparison
Registers used for stopping auto·
matic single·step emulation.
TR
Specifies or displays trace·data col·
lection conditions, and optionally
sets Qualifier Register (QR).
INTERROGATION AND UTILITY
Interrogation and utility commands give the user
convenient access to detailed information about
the user program and the state of the 8022 that is
useful in debugging hardware and software.
Chariges can be made in both memory and the
8022 registers, flags, and digital port values. Commands are also provided for various utility operations such as loading and saving program files,
defining symbols and logic probe groups, displaying trace data, controlling system synchronization
and returning control to ISIS-II. A summary of the
basic interrogation and utility commands is
shown in Table 2. Two new emulator features are
discussed below.
The single-line assembler (ASM command) is a new in·circuit emulation feature that permits the designer to examine and alter program memory using assembly
language mnemonics, without leaving emulation
mode or requiring time-consuming program· reassembly. When assembling new mnemonic instructions into program memory, previously de-
S/NGLE,L/NE ASSEMBLER -
Comparison Registers
Four comparison registers are provided that allow
the user to halt single step emulation when the
single condition specified in anyone of these registers is satisfied. The comparison registers differ
from the breakpoint registers in that, 1) the compari sons <, :5, >, ;:,:, and 1= are perm itted in add iAFN·01586A
tion to the = condition, 2) more 8022 and ICE varibles may be compared, and 3) the comparators
themselves may be variables.
18-26
ICE·22™ IN·CIRCUIT EMULATOR
HELP - The HELP file is a new ICE feature that allows the deSigner to display ICE-22 command syntax information at the Intellec console. By typing
"HELP", a listing of all items for which help
messages are available is displayed; typing
"HELP < Item>" then displays relevant information about the item requested, including typical
usage examples. The "HELP" listing and a "HELP
ASM" message for the ASM command are shown
in Table 3.
fined symbolic references (from the original program assembly, or subsequently defined during
the emulation session) may be used in the instruction operand field, and the emulator will supply
the absolute address or data values as stored in
the emulator symbol table. These features greatly
reduce the designer's time spent translating to
and from machine code and searching for absolute addresses, with a corresponding reduction in
transcription errors.
Table 2_ Major Interrogation and Utility Commands
Command
LOAD
Description
Loads user object program (8022 code) into user-program memory, and user symbols into
ICE-22 emulator symbol table.
DEFINE/REMOVE
Defines/removes symbols in ICE-22 emulator symbol table.
SAVE
Saves ICE-22 emulator symbol table and/or user object program in ISIS-II hexadecimal file.
LIST
Copies all emulator console input and output to ISIS-II file.
ChangelDisplay
Commands
Change or display value of symbolic reference in ICE-22 emulator symbol table, or contents
of key-word references (including registers, I/O ports, and status flags), or memory
references.
Group Commands
Define, change, remove, or display user-defined logic probe channel groups.
Trace Commands
Position trace buffer pointer; select and format trace output; enable or disable automatic display of trace data and register contents during single-step emulation.
PRINT
Displays·trace data pOinted to by trace buffer pointer.
Synchronization
Line Commands
Set and display enabled/disabled status of SYNCO and SYNC1 synchronization line outputs
or latched inputs (used to allow real-time emulation or tracing to start and stop synchronously with external events).
ASM
Assembles mnemonic instructions into user-program memory, or disassembles and displays
user-program memory contents.
INTERRUPT
Simulates external or timer interrupt sequence.
EVALUATE
Evaluates expression and displays resulting value.
SECONDS
Displays contents of emulation timer, in microseconds.
HELP
Displays help messages for ICE-22 emulator command-entry assistance.
EXIT
Terminates ICE-22 emulator operation.
18-27
AFN-01586A
ICE·22™IN·CIRCUIT EMULATOR
Table 3. HELP Command
"
*HELP
Help is available fo.r 'the fellewing items. Type HELP fellewed by the
item name.
(Fer mere infermatien abeut HELP. type HELP HELP.)
,
Real-Time Emulatien:
GO GR, SYO
BR BRO BRI
(B1?EAKSREG>
(MATCHSCOND>
Step Emulatien:
STEP
SR
CR CRO CRl CR2 CR3
(COMPARISONSCOND>
EVALUATE
EXIT
IiELP
INfERRUPT
LOAD
SAVE
Trace Cellectien:
TR QRSYl
OIATCHSCOND>
'frace Display:
TRACE
OLDEST
NEWEST
MOVE
PRINT
DUMP
(EXPRSlO>
< IDENTIFI ER>
Change/Display/Define/Remeve:
ASM
REGISTER
DEFINE
CBYTE
STACK
REMOVE
DBYTE
SECONDS
GROUP
(CHANGE>
(CPUSREF>
SYMBOL
(DISPLAY> (ICESREF>
State/Mode:
BASE
ENABLE
SUFFIX
DISABLE
LIST
RESET
< INSTRUC'UON>
(MASKEDSCONSTANT>
,
(NUMERICsCONSTANT>
(PATlINAME>
SYMBOLIC
SYNC
(SYSTEMSGROUP>
(USERSGROUP>
*HELP ASM,
ASM - Cemmand to. display er change 8022 cede memery using assembler
instructiens.
(1) ASM (ADDRESS> [TO/LENG~H(AI>DRESS»
(display 8022 code memery as assembler instructieris)
(2) ASM (ADDRESS>
END
(changememery starting at (ADDRESS»:
Ex:
M,M 100 MOV A.~RO
'JNZ 100
END
(3) ASM (ADDRESS> TO/LENGTH (ADDRESS> (INSTRUCTIONSLIST>
EUD
(Change several lecatiens and perfermrange checking er repetitien.
If the "instructiens require mere memery than the size ef the range.,
an errer eccurs. I f the instructiens, require less memery. then
the data is repeated Ilntil the range is filled.)
(INSTRUCTIONSLIST> - Standard 8022 instructiens typed ene per line. The
operand M'(EXPR>- can be used where -'data- is recrtlired. and the eperand
-- can be used where Maddr- is required. A centinuatien
prempt
is issued after each carriage return is typed.
-.*-
AFN·01586A
18-28
ICE·22™ IN·CIRCUIT EMULATOR
SPECIFICATIONS
Environmental Characteristics
ICE·22 Operating Requirements
Operating Temperature: 0° to 40°C
Operating Humidity: Up to 95% relative humidity
without condensation.
Intellec® Microcomputer Development System
(32K RAM required)
System console
Intellec® Diskette Operating System (single or
double density) ISIS-II v_ 3.4 or later
Equipment Supplied
• Printed circuit boards (2)
• Emulation buffer box, Intellec interface cables,
and user-interface cable with 8022 emulation
processor
• 16 external trace probes
• Synchronization cables
• Crystal power accessory
• Operating instructions manual
• Diskette-based ICE-22 software (single and double density)
Packaged Weight: 8.0 Ib (3.63 kg)
Electrical Characteristics
DC Power Requirements
Vee = +5V, +5%, -1%
Icc = 13.2A max; 11.0A typical
Voo= + 12V, ± 5%
100 =0.1A max; 0.05A typical
Vss= -10V, ±5%
Iss = 0.05A max; 0.01 A typical
Emulation Clock
ORDERING INFORMATION
Description
MCI-22-ICE
8022 Microcontroller In-Circuit
Emulator, cable assembly and
interactive diskette software
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Buffer Box
Width: 4.5 in. (11.43 cm)
Length: 10.0 in. (25.40 cm)
Depth: 1.25 in. (3.18 cm)
User's system clock (0.6 to 3.6 MHz) or ICE-22
crystal power accessory (3.0 MHz)
Part Number
Physical Characteristics
18-29
MCS™-48
DISKETTE-BASED SOFTWARE
SUPPORT PACKAGE
• Extends Intellec microcomputer
development system to support MCS-48
development
• Takes advantage of powerfullSIS-Ufile
handling and storage capabilities
• Provides assembler output in standard
Intel hex format
• MCS-48 assembler provides conditional
assembly and macro capability
The MCS-48 assembler translates symbolic 8048 assembly language instructions into the appropriate machine
operation codes, and provides both conditional and macroassembler programming. Output may be loaded
either to an ICE-49 module for debugging or into a Universal PROM Programmer for 8748 PROM programming.
The MCS-48 assembler operates under the ISIS-II operating system on Intellec Microcomputer Development
systems.
18-30
inter
MCS·48
FUNCTIONAL DESCRIPTION
Table 1. Sample MCS·48 Diskette·Based
Assembly Listing
The MCS·48 assembler translates symbolic 8048
assembly language instructions into the appropriate
machine operation codes. The ability to refer to program
addresses with symbolic names eliminates the errors of
hand translation and makes it easier to modify programs
when adding or deleting instructions. Conditional
assembly permits the programmer to specify which por·
tions of the master source document should be includ·
ed or deleted in variations on a basic system design,
such as the code required to handle optional external
devices. Macro capability allows the programmer use of
a single label to define a routine. The MCS·48 assembler
will assemble the code required by the reserved routine
whenever the macro label is inserted in the text. Output
from the assembler is in standard Intel hex format. It
may be either loaded directly to an in·circuit emulator
(ICE·49) module for integrated hardware/software
debugging, or loaded into a Universal PROM Program·
mer for 8748 PROM programming. A sample assembly
listing is shown in Table 1.
I~~:1I8!!~MACRo-As·SEM8-L-ER.V'·o ~~~- ---S:~CE STAT~~::~----------1
2
3
•
5
6
7
a
9
10
"
000"
''''''
'0032
"
iOWO
""
".
"
""
""
21
~:~
I 0104
13
14
15
:~;i
BA32
16:~ ~~
:6~~~ ~~
22
,OIOA Al
;010816
OlOC 19
0100 EAOl
,OECIMAl ADDITION ROUTINE. ADD BCD NUMBER
.AT LOCATION 'BETA' TO BCD NUMBER AT 'ALPHA' WITH
.RESULT IN 'ALPHA' LENGTH OF NUMBER IS 'COUNT' DIGIT
,PAIRS.IASSUME BOTH BETA AND ALPHA ARE SAME LENGTH
AND HAVE EVEN NUMBEA OF DIGITS OR MSD IS 0 IF
0001
INIT
11
MACRO
MOV
MOV
MOV
AUGNO,ADOND,CNT
RO._AUGNO
RI,'ADOND
R2,'CNT
ENOM
ALPHA
BETA
COUNT
ECU
EQU
ECU
0"0
INIT
MO'
MO'
MO'
28
ADOl';
MO'
@RO.A
MO'
e.
'"c
'"C
DJNZ
'"'
ALPHA COOlE
Ll
0102
ALPHA, BETA, COUNT
RO,'ALPHA
RI .• BETA
R2,IICOUNT
C
A.@RO
A.(¢Rl
Gee
LP
,""
"oe
A
eo
"'
R2.LP
ASSEMBLY COMPLETE. NO ERRORS
I ISIS II ASSEMBLER SYMBOL CROSS
ALPHA
BETA
I
13_
11
14.
17
REFERENCE. Vl 0
r~~~NT :~: :~
lce
SPECIFICATIONS
Operating Environment
Shipping Media
Required Hardware
Diskette
Intellec Microcomputer Development System
32K RAM (non·macro use)
48K RAM (use of macro facility)
One or two Floppy disk drives
- Single or Double density
System Console
- CRT or interactive hardcopy device
Reference Manuals
Required Software
9800255 -
MCS·48 and UPI·41 Assembly Language Pro·
gramming Manual (SUPPLIED)
9800236 -
Universal PROM Mapper Operator's Manual
9800306 -
ISIS·II User's Guide
ISIS·II Diskette Operating System
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.
Optional Hardware
ICE·49 In·Circuit Emulator
Line Printer
Universal PROM Programmer with 8748 personality card
ORDERING INFORMATION
Product Code
Description
MDS·D48
Diskette·based assembler for MCS·48
family.of microprocessors.
18-31
AFN.()()819B
·":'
.
~
..
.
MCS-51TM Development
Systems
19
inter
8051 SOFTWARE DEVELOPMENT PACKAGE
relocatable assembly
• Symbolic
language programming for 8051
Macro Assembler features conditional
• assembly
and macro capabilities
microcontrollers
Intellec® Microcomputer
• Extends
Development System to support 8051
program development
•
Produces Relocatable Object Code
which is linkable to other 8051 Object
Modules
•
Encourage modular program design
for maintainability and reliability
CONV51 Converter for translation of
• 8048
assembly language source code
to 8051 assembly language source
code
Provides upward compatibility from
• the
MCS-48™ family of single-chip
microcontrollers .
The 8051 software development package provides development system support for the powerful 8051 family of single
chip microcomputers. The package contains a symbolic macro assembler and MCS·48 source code converter.
The assembler produces relocatable object modules from 8051 macro assembly language instructions. The object
code modules can be linked and located to absolute memory locations. This absolute object code may be used to pro·
gram the 8751 EPROM version of the chip. The assembler output may also be debugged using the ICE·51™ in·circuit
emulator.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide software com·
patibility between the two families of microcontrollers.
This diskette·based software package runs under ISIS·II on an Intellec Microcomputer Development System with 64K
bytes of memory.
The following are trademarkes of Intel Corporation and may be used only to identify Intel products: exp, CREDIT, Intellee, Multibus, i, iSSC, Multimodule, ICE, iSeX, PROMPT,
ieS, Library Manager, Promware, Insite, MeS, RMX, Intel, Megachassis, UPI, In television, Micromap, p.Scope and the combination of ICE. ieS t iSSC, iSeX, MeS. or RMX and a
numerical suffix.
October, 1981
© Intel Corporation 1981
19-1
162771
AFN 019448
intel'
8051 SOFTWARE DEVELOPMENT PACKAGE
8051 MACRO ASSEMBLER
• Supports 8051 family program development on Intellec®· Microcomputer
Development Systems
• Gives symbolic access to powerful
8051 hardware features
• Produces object file, listing file and
error diagnostics
• Object files are linkable and locatable
• Provides software support for many
addressing and data allocation
capabilities
• .Symbolic Assembl~r supports syrnbol
table, cross-reference, macro
capabilities, and conditional assembly
The 8051 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language modules into linkable and
locatable object code modules. Assembly language mnemonics are easier to program and are more readable than
binary or hexadecimal machine instructions. By allowing the programmer to give symbolic names to memory locations
rather than absolute, addresses, software design'and debug are performed more quickly and reliably. Furthermore,
since modules are linkable and relocatable, the programmer can do his software in modularfashion. Thismakes pro·
grams easy to understand, maintainable and reliable.
The assembler supports macro definitions and calls. This is a convenient way to program a frequently used code
sequence only once. The assembler also provides. conditional assemblycapabilities.
Cross referencing is provided in the symbol tabl,e listing, showing the user the lines in which each symbol was defined
and referenced. .
.
.
,.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These features
include referencing for bit and byte locations, and for providing 4·bit operations for BCD arithmetic. The assembler
also provides symbolic access to hardware registers, I/O ports! control bits, and RAM addresses.
Math routines are enhanced by the MUltiply and DIVide instructions.
If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which are
included in the assembly listing or on another file. Program testing may be performed by using the Universal PROM
Programmer and 8751 personality card to program the 8751 EPROM version of the chip, or by using the ICE·51 in·
circuit emulator.
RL51 LINKER AND RELOCATOR PROGRAM
• Links modules generated by the
assembler
• Enables modular programming of software for efficient program development
• Locates the linked object to absolute
memory locations
• Modular programs are easy to
understand, maintainable and reliable
The 8051 linker andrelocator (RL51) is a utility which enables 8051 programmers to develop software in a modular
fashion. The linker resolves all references between modules and the relocator assigns absolute memory locations to
all the relocatable segments, combining relocatable partial segments with the same name.
With this utility, software can be developed more quickly because small functional modules are easier to understand,
design and test than large programs.
The number of symbols in the software is very large because the assembler symbol limit applies only per module not
the entire program. Therefore programs can be more readable and better documented.
Modules can be saved and used on different programs. Therefore the software investment of the customer is maintained.
RL51 produces two files. The absolute object module file can be directly executed by the 8051 family. The listing file
shows the re~ults of the link/locate process.
19-2
AFN01944B
inter
8051 SOFTWARE DEVELOPMENT PACKAGE
CONV51
8048 TO 8051 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
• Enables software written for the
MCS·48™ family to be upgraded to run
on the 8051
• Preserves comments; translates 8048
macro definitions and calls
• Provides diagnostic information and
warning messages embedded in the
output listing
• Maps each 8048 instruction toa corre·
sponding 8051 instruction
The 8048 to 8051 Assembly Language Converter is a utility to help users of the MCS-48 family of microcomputers
upgrade their deisgns with the high performance 8051 architecture. By converting 8048 source code to 8051 source
code, the software investment developed for the 8048 is maintained when the system is upgraded.
The goal of the converter (CONV51) is to attain. functional equivalence with the 8048 code by mapping each 8048
instruction to a corresponding 8051 instruction. In some cases a different instruction is produced because of the
.
enhanced instruction set (e.g., bit CLR instead of ANL).
Although CONV51 tries to attain functional equivalence with each instruction, certain 8048 code sequences cannot be
automatically converted. For example, a delay routine which depends on 8048 execution speed would require manual
adjustment. A few instructions, in fact, have no 8051 equivalent (such as those involving P4-P7). Finally, there are a
few areas of possible intervention such as PSW manipulation and interrupt processing, which at least require the user
to confirm proper translation. The converter always warns the user when it cannot guarantee complete conversion.
CONV51 produces two files. The output file contains the ASM51 source program produced from the 8048 instructions.
The listing file produces correlated listings of the input and output files, with warning messages in the output file to
pOint out areas that may require users' intervention in the conversion.
SPECIFICATIONS
OPERATING ENVIRONMENT
Required Hardware:
Required Software:
Intellec Microcomputer Development System with
ISIS-II Diskette Operating System (V3.4 or later)
Documentation Package:
64K Bytes of RAM
MCS-51 Macro Assembler User's Guide
MCS-51 Utilities User's Guide for 8080/8085 Based
Development System
MCS-51 Macro Assembly Language Pocket Reference
MCS·51 Assembler and Utilities Pocket Reference
MCS·51 8048:to·8051 Assembly Language Converter
Operating Instructions for ISIS·II Users
Flexible Disk Drive(s)
System Console
-CRT or hard copy device
Optional Hardware:
Universal PROM Programmer
Line Printer
ICE-51 In-Circuit Emulator
ORDERING INFORMATION
Part Number
Description
MCI·51·ASM
8051 Software Development Package
19·3
AFN01944B
inter
EM·51
8051 EMULATION BOARD
• Emulates 8051/8751/8031 functions on
a 2.75" x 5.25" board assembly
• Plugs directly into 80511875118031
sockets
• Replaces the 8051/8751/8031 in
prototype systems
• Includes a 2732A EPROM device for
program memory
The EM-51 emulation board is a small, ready-to-use microcomputer assembly that replaces an Intel 8051
family single-chip microcomputer in a prototype system. EM-51 includes sockets for 2716 or 2732 EPROMs,
which substitute for the 8051/8751 on-chip program memory during prototype development. An Intel 2732A
4K x 8 EPROM is included with the board. With the memory in place, an EM-51 board becomes a full
functional and electrical equivalent of the 8051 or 8751 microcomputer.
19-4
EM-51
EPROM as an option. Table 1 lists the memory
device options by speed and power.
FUNCTIONAL DESCRIPTION
The EM-51 emulator board uses an Intel 8051
family single-chip microcomputer. The microcomputer is configured with additional input and output
lines to let its on-chip ROM/EPROM program
memory be replaced by EM-51 memory. The 8051's
internal address, data, and control lines are connected
through buffers to two sockets which accommodate
the memory device(s).
Clock Options
EM-51 operates with either a prototype system
crystal or an on-board crystal supplied by the user.
For example, the on-board option is helpful if you
need to reduce the crystal-to-chip spacing. Intel
Application Note AP-35 describes crystal selection
criteria.
Jumpers on the EM-51 board are used to select
among memory, clock, and power options.
Power Options
An EM-51 can be powered from the prototype 8051
socket, an external 5-volt power supply, or a combination of the two. The combination option lets
your prototype power supply support the 8051
while an external supply powers the additional
EM-51 circuitry.
Memory Options
The EM-51 board uses an Intel 2732A EPROM,
which provides 4K bytes of memory to replace the
on-chip program memory. The board has two
EPROM sockets, permitting you to use 2716 2K X 8
3"n1
.04
'1-
In. _I k- .79 In.
t
j----------j
I
I
I
j----------j
II
I
I
I
I~
---........ PINS APPRQX .
. 08 in .
.......
~I ! _ _ - - - - - - - - - - 4 . 4 4 In·------------.~I
T
I
/PINl
.47 in.
i
D
,..-------...,
8051E
2.75 In.
I
I
I
I
L _______ ..J
- - - - - - - - - - - - - - 5 . 2 5 I n . - - - - - - - - - ' - - - - - - -.... ,
11 .......
Figure 1. Dimensions
19-5
EM~51
Table 1.
EM-51 Memory Options
, Memory Device
2732A-2
Size per device
2732A
4K
2732
2716-1
>< 8
2716-2
2K
2716
>< 8
Access time (ns)
(from address)
(from output enable)
200
70
250
100
450
120
350
120
390
120
450
120
Maximum Operating Frequency (MHz)
12.0
12.0
8.0
. 9.5
9.0
8.0
225
500
225
500
225
500
225
550
225
550
225
550
Maximum Power Consumption (mA)
(8051) *
(other circuitry)
* The
8051 configuration used on EM-51 may require more power than standard 8051, 8751, or 8031 devices.
SPECIFICATIONS
Physical Characteristics
Equipment Supplied
Length:
Width:
Depth:
Weight:
EM-51 board assembly
EM-51 Operator's Manual
2732A EPROM
5.25 in. (13.34 cm)
2.75 in. (6.99 cm)
0.75 in. (1.91 cm)
4 oz. (113 gm)
Electrical' Characteristics
Equipment Required
DC Power: Vcc = 5V ±5%
Icc = 775 mA (maximum)
EPROM programmer
Power supply
Timing:
Same as Intel 8051 microcomputer
Environmental Characteristics
Operating Temperature: 0° Cto 55°C
Operating Humidity: 95% (Maximum) relative
humidity, non-condensing
,
Optional Equipment
Crystal for on-board clock
ORDERING INFORMATION
Part Number: MCI-51-EM
Description: 8051 Emulation Board
19-6
intel"
ICE·51™
8051 IN·CIRCUIT EMULATOR
• Precise, full·speed, real·time emulation
- Load, drive, timing characteristics
- Full·speed program RAM
- Serial and parallel ports
• Full symbolic debugging
• Single·line assembly and disassembly
for program instruction changes
• Macro commands and conditional
block constructs for automated·
debugging sessions
• User·specified breakpoints
• Execution trace
- User·specified qualifier registers
- Conditional trigger
- Symbolic groupings and display
-:- Instruction and frame modes
• HELP facility: ICE·51 command
reference at the console
• User confidence test of ICE·51
hardware
• Emulation timer
The ICE-51 module resides in the Intellec® Microcomputer Development System and interfaces to any
user-designed 8051 system through a cable terminating in an 8051 emulator microprocessor and a pincompatible plug. The emulator processor, together with 8K bytes of user program RAM located in the
ICE-51 buffer box, replaces the 8051 device in the user system while maintaining the 8051 electrical and
timing characteristics. Powerful Intellec debugging functions are thus extended into the user system.
Using the ICE-51 module, the designer can emulate the system's 8051 in real-time or single-step mode.
Breakpoints allow the user to stop emulation on user-specified conditions, and a trace qualifier feature
allows the conditional collection of 1000 frames of trace data. Using the single-line 8051 assembler the
user may alter program memory uSing ASM51 mnemonics and symbolic references, without leaving the
emulator environment. Frequently used command sequences can be combined into compound commands and identified as macros with user-defined names.
The following are trademarks of Inlel Corporation and may be used only to describe Inlel products: Intel, Inlellee, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix. Intel Corporation 'assumes no responsibility fOf the use 01 any circuitry other than circuitry embodied in an Intel product. No other circuit palent licenses are
implied.
August 1981
© INTEL CORPORATION, 1981
162886
19-7
ICE·51™
Symbolic Debugging
FUNCTIONAL DESCRIPTION
The ICE-51 emulator permits the user to define
and use symbolic, rather than absolute, references to program and data memory addresses; additional symbols are predefined by the ICE-51 software for referencing' registers, flags, and input!
output ports. Thus, the user need not recall or look
up the addresses of key locations in his program
as they change with each assembly, or become
involved with machine code.
Integrated Hardware and Software
Development
The ICE-51 emulator allows hardware and soft-,
ware development to proceed interactively_ This
approach is more effective than the traditional
method of independent hardware and software
development followed by system integration. With
the ICE-51 module,prototype hardware can be
added to the system as it is designed. Software
and hardware integration occurs while the product is being developed.
It can be operated without being connected to the
user's system before any of the user's hardware is
available. In this stage ICE-51 debugging capabilities can be used in conjunction with the Intellec
text editor and 8051 macroassembler to facilitate
program development.
When a symbol is used for memory reference in an
ICE-51 emulator command, the emulator supplies
the corresponding location as stored in the ICE-51
emulator symbol table. This table can be loaded
with the symbol table produced by the assembler
during application program assembly. The user
can obtain the symbol table during software preparation simply by using the "DEBUG" switch in
the ASM51 macroassembler. Furthermore, the
user can interactively modify the emulator symbol
table by adding new symbols or changing or deleting old ones. This feature provides great flexibility
in debugging and minimizes the need to work with
absolute men10ry values.
HARDWARE DEVELOPMENT
Through symbolic references in combination with
other features of the emulator, the user can easily:
The ICE-51 emulator assists four stages of development:
SOFTWARE DEBUGGING
The ICE-51 module's precise emulation characteristics and full-speed program RAM make it a
valuable tool for debugging hardware, including
time-critical serial port, parallel port, and timer interfaces.
• Interpret the results of emulation activity collected during trace.
• Disassemble program memory to mnemoniCS,
or assemble mnemonic instructions to executable code.
• Examine or modify 8051 internal registers, data
memory, or port contents.
• Reference labels or addresses defined in a user
program.
SYSTEM INTEGRATION
Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8051 socket. As
each section of the user's hardware is completed,
it is added to the prototype. Thus, each section of
the hardware and software is "system" tested in
real-time operation as it becomes available.
Automated Debugging and Testing
MACRO COMMAND
SYSTEM TEST
When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-51 module is then used for real-time emulation of the 8051 to debug the system as a completed unit.
A macro is a set of commands which is given a
name. A group of commands which is executed
frequently can be defined as a macro. The user
can execute the group of commands by typing a
colon followed by the macro name. Up to ten
parameters may be passed to the macro.
The final product verification test may be performed using the 8751 EPROM version of the 8051
microcomputer. Thus, the ICE-51 module provides
the user with the ability to debug a prototype or
production system at any stage in its development without introducing extraneous hardware or
software test tools.
MacroGommands can be defined at the beginning
of a debug session and then used throughout the
whole session. The user can save one or more
macro definitions on diskette for later use. The
Intellec text editor may be used to edit the macro
file. The macro definitions are eas'yto include in
any later emulation session.
19-8
AFN-02026
inter
ICE·51™
tinuously compares the values stored in the breakpoint registers with the status of specified address, opcode, operand, or port values, and halts
emulation when this comparison is satisfied.
When an instruction initiates a break, that instruction is executed completely before the break
takes place. The ICE-51 emulator then regains
control of the console and enters the Interrogation Mode. With the breakpoint feature, the user
can request an emulation break when his program:
The power of the development system can be applied to manufacturing testing as well as development by writing test sequences as macros. The
macros are stored on diskettes for use during
system test.
COMPOUND COMMAND
Compound commands provide conditional execution of commands (IF command) and execution of
commands repeatedly until certain conditions are
met (COUNT, REPEAT commands).
Compound commands may be nested any number
of times, and may be used in macro commands.
,
'
• Executes an instruction at a specific address or
within a range of addresses.
• Executes a particular opcode.
• Receives a specific signal on a port pin.
• Fetches a particular operand from the user program memory.
• Fetches an operand from a specific address in
program memory.
,
Example:
'DEFINE .1=0
'COUNT 100H
.'IF.I AND 1 THEN
.. 'CBYTE .1 = .1
.. 'END
:.1=.1+ l'
:END
; Define symbol .1 to 0
; Repeat the following
commands 100H times.
; Check if .1 is odd
; Fill the memory at location .1
to value .1
; End if structure
; Increment .1 by 1.
; Command executes upon
carriage-return after END
Table 1_ Major Emulation Commands
Command
(The characters', .', and .. ' shown in this example are system prompts which include an indication of the nesting level of compound commands.)
Description
Begins real-time emulation and optionally specifies break conditions.
BRO, BR1, BR Sets or displays either or both
Breakpoint Registers used for stopping real-time emulation.
Performs single-step emulation.
STEP
QRO, QR1, QR Sets or displays match conditions
for qualified trace.
Specifies or displays trace-data colTR
lection conditions and optionally
sets Qualifier Register (QRO, QR1).
SY, SY1,SYO Set and display status of synchronization line outputs or latched inputs. Used to allow real-time emulation or trace to start and stop synchronously with external events.
GO
Operating Modes
The ICE-51 software is an Intellec RAM-based program that provides the user with easy-to-use commands for initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters.
ICE-51 commands are configured with a broad
range of modifiers which provide the user with
maximum flexibility in describing the operation to
be performed.
EMULATION
The ICE-51 module can emulate the operation of a
prototype 8051 system, at real-time speed (1.2 to
12 MHz) or in single steps. Emulation commands
to the ICE-51 module control the process of setting up, running, and halting an emulation of the
user's 8051-based system. Breakpoints and tracepoints enable the ICE-51 emulator to halt emulation and provide a detailed trace of execution in
any part of the user's program. A summary of the
emulation commands is shown in Table 1.
Trace and Tracepoints
Tracing is used with both real-time and singlestep emulation to record diagnostic information in
the trace buffer as a program is executed. The information collected includes opcodes executed,
port values, and memory addresses. The ICE-51
emulator collects up to 1000 frames of trace data.
This information can be displayed as assembler
instruction mnemonics, if desired, for analysis
during interrogation or single-step mode. The
trace-collection facility may be set to run conditionally or unconditionally. Two unique trace qualifier registers, specified in the same way as break-
Breakpoints
The ICE-51 hardware includes two breakpoint registers that allow the user to halt emulation when
specified conditions are met. The emulator con-
19-9
AFN·Q2026
ICE·51™
point registers, govern conditional trace activity.
The qualifiers can be used to condition trace data
collection to take place as follows:
• Under all conditions (forever).
• Only while the trace qualifier is satisfied.
• For the frames or instructions preceding the
time when a trace qualifier is first satisfied (pretrigger trace).
• For the frames or instructions after a trace qualifier is first satisfied (post-triggered trace).
Table 2 shows an example Of a trace display.
Table 2. Trace Display (Instruction Mode)
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INTERROGATION AND UTILITY
Interrogation and utility commands give the user
convenient access to detailed information about
the user program and the state of the 8051 that is
useful in debugging hardware and software.
Changes can be made in memory and in the 8051
registers, flags, and port values. Commands are
also provided for various utility operations such
as loading and saving program files, defining symbols, displaying trace data, controlling system
synchronization and returning control to ISIS-II. A
summary of the basic interrogation and utility
commands is shown in Table 3. Two time-saving
emulator features are discussed below.
SINGLE-LINE ASSEMBLERI DISASSEMBLER
The single-line assemblerldisassembler (ASM and
DASM commands) permits the designer to examine and alter program memory using assembly
language mnemonics, without leaving the emulator environment or requiring time-consuming
program reassembly. When assembling new
mnemonic instructions into'program memory;previously defined symbolic references (from the
original program assembly, or subsequently defined during the emulation session) maybe used
in the instruction operand field. The emulator will
supply the absolute address or data values as
stored in the emulator symbol table. Thesefeatures eliminate user time spent translating to and
from machine code and searching for absolute addresses, with a corresponding reduction in transcription errors.
Table 3. Majof'interrogation and Utility Commands
Description
Command
HELP
Displays help messages for ICE-51 emulator command-entry assistance.
LOAD
Loads user object program (8051 code) into user program memory, and user symbols into
ICE·51 emulator symbol table.
Saves ICE·51 emulator symbol table and/or user object program in ISIS·II hexadecimal file,
SAVE
LIST
Copies all,emulator console input and output to ISIS·" file.
EXIT
Terminates ICE-51 emulator operation.
DEFINE
Defines ICE·51 emulator symbol or macro.
REMOVE
ASM
Removes ICE·51 emulator symbol or macro.
Assembles mnemonic instructions into userprowam memory,
DASM
ChangelDisplay
Commands
EVALUATE
MACRO
INTERRUPT
Disassembles and displays user program memory contents.
Change or display value of symbolic reference in ICE-51 emulator symbol table, contents of
key· word references (including registers, I/O ports,and status flags), or memory references,
Evaluates expression and displays resulting value.
Displays ICE-51 macro or macros.
SECONDS
Displays serial, external" or timer interrupt register settings.
Displays contents of emulation timer, in microseconds.
Trace Commands
PRINT
Displays trace data pointed to by trace buffer pOinter.
Position trace buffer pointer and select format f()r \race display. '
19-10
AFN-02026
ICE·51™
Emulation Accuracy
HELP - The HELP file aJlows the user to display
ICE-51 command syntax information at the Intellec console_ By typing "HELP", a listing of all
items for which help messages are available is
displayed; typing "HELP < Item>" then displays
relevant information about the item requested, including typical usage examples. Table 4 shows
some sample HELP messages.
The speed and interface demands of a highperformance single-chip microcomputer require
extremely accurate emulation, incllJding fullspeed, real-time operation with the full function of
the microcomputer. The ICE-51 emulator achieves
accurate emulation with an 8051 bond-out chip,
special configuration of the 8051 microcomputer
family, as its emulation processor.
a
Each of the 40 pins on the user plug is connected
directly to the corresponding 8051- pin on the
bond-out chip. Thus the user system sees the
emulator as an 8051 microcomputer at the 8051
socket. The resulting characteristics provide extremely accurate emulationof the 8051, including
speed, timing characteristics, load and drive
values, and crystal operation. The emulator may
draw more power from the user system than a
standard 8051 family device.
Additional bond-out pins provide signals such. as
internal address, data, clock, and control lines to
the emulator buffer box .. These signals let static
RAM in the buffer box substitute for on-Chip program ROM or EPROM or external program memory. The 8Kbytes of full-speed RAM in the buffer
box can be mapped in 4K blocks to anywhere within the 64K program memory space of the 8051. The
bond-out chip also gives the emulator "backdoor" access to internal chip operation, so that
the emulator can break and trace execution without interfering with the values on the user-system
pins.
Figure 1. A Typical 8051 Development Configuration_ The host system is an Intellec
Model 225, plus 1 megabyte dual doubledensity flexible disk storage. The ICE-51
module is connected to an SDK-51 system design kit.
Table 4_ HELP Command
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19-11
AFN·02026
ICE·51™
SPECIFICATIONS
Physical Characteristics
ICE·51 Operating Requirements
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Buffer Box
Width: 8.00 in. (20.32 cm)
Length: 12.00 in. (30.48 cm)
Depth: 1.75 in. (4.44 cm)
Weight: 4.0 Ib (1.81 kg)
Intellec® Microcomputer Development System
(64K RAM required)
System console
Intellec® Diskette Operating System (single or
double density) ISIS-II v. 3.4 or later
Equipment Supplied
• Printed circuit boards (2)
• Emulation buffer box, Intellec interface cables,
and user-interface cable with 8051 emulation
processor
• Crystal power accessory
• Operating instructions manual
• Diskette-based ICE-51 software (single and double density)
Emulation Clock
User's system clock (1.2 to 12 MHz) or ICE-51
crystal power accessory (12 MHz)
Environmental Characteristics
Operating Temperature: 0° to 40°C
Operating Humidity: Up to 95% relative humidity
without condensation.
Electrical Characteristics
DC Power Requirements (from Intellec system)
Vee= +5V, +5%, ,-1%
lee = 13.2A max; 11.0A typical
Voo= + 12V, ± 5%
100 =0.1A max; 0.05A typical
Vss=-10V,±5%
Iss = 0.05A max; 0.01A typical
User plug characteristics at 8051 socket
Same as 8031, 8051, or 8751, except that the user
system will see an added load of 25 pF capacitance and 50 p.A leakage from the ICE-51 emulator
user plug at ports 0, 1, and 2.
ORDERING INFORMATION
Part Number
Description
MCI-51-ICE
8051 Microcontroller In-Circuit
Emulator, cable assembly and
interactive diskette software
19-12
UPI-41ATM
Development Systems
20
ICE·41A™
UPI·41A IN·CIRCUIT EMULATOR
Extends Intellec microcomputer develop·
ment system debug power to user con·
figured system via external cable and
40·pin plug, replacing user UPI·41A™
devices
Emulates user system
in real time
UPI~41ATM
Eliminates. need for extraneous debug·
ging tools residing in user system
Collects address, data, and UPI·41A™
status information on machine cycles
emulated
devices
Provides capability to examine and alter
UPI·41ATM registers, memory, and flag
values, and to examine pin and port
values
Allqws user configured system to use
static RAM memory for program' debug
Integrates hardware and software efforts
early in engineering cycle to save devel·
opment time
Provides hardware comparators for user
designated break conditions
The ICE'41A UPI-41A In-Circuit Emulator module is an Intellec system resident module that interfaces to any user configured UPI-41A system_ The ICE-41A inoduleinterfaces with a UPI-41A pin-compatible plug which replaces the UPI41A device in the system. With the ICE-41A plug in place, the designer has the capability to execute the system in real
time while collecting up to 255 instruction cycles of real time trace data. In addition, lie can single step the system program during'execulion. Static RAM memory is available through the ICE-41A module to store UPI-41A programs. The
designer may display and alter the contents of program memory, internalUPI-41A registers and flags, and 110 ports.
Powerful debug capability is extended into the UPI-41A system while ICE-41A debug hardware and software remain inside the Intellec system. Symbolic reference capability allows the designer to use symbols rather than absolute values
when examining and modifying memory, registers, flags, and 110 ports in the system,
20-1
OOB04A
ICE·41A™
GO FROM .START TILL CODE. RSLT
FUNCTIONAL DESCRIPTION
begins execution of the program at the address referenced by the label START in thlil deSigner's assembly
program. A breakpoint Is set to occur the first time the
microprocessor executes the program memory location
referenced by RSLT. The designer does not have to be
concerned with the physical locations of START and
RSLT. The ICE-41A software driver supplies them
automatically .from Information stored In the symbol
table.
Debug Capability Inside User System
Intellec memory is used for the execution of the ICE-41 A
software. The Intellec CRT console and the file handling
capabilities provide the designer with the ability to communicatewlth the ICE-41A module and display Information on the operation of the prototype system. The ICE41A module block diagram is shown in Figure 1.
Symbolic Debugging
Symbol Table - ICE-41A software allows the user to
make symbolic references to 110 ports, memory addresses, and data In his program. The user symbol table
which is generated along with the object file during a
program assembly can be loaded to Intellec memory for
access.durlng emulation. The user may add to this symbol table any additional symbolic values for memory addresses, constants, or variables that he may find useful
during system debugging. By referring to symbol
memory addresses, the user can examine, change or
break at the Intended location. In addition, ICE-41A provides symbolic definition of all UPI-41A registers and
flags.
Symbolic Reference - SymbOlic reference is a great
advantage to the system designer. He Is no longer
burdened with the need to recall or look up addresses of
key iocatlons In his program which can change with
each assembly. Meaningful symbols .from. his source
program can .be used Instead. For example, the com.
mand:
Memory Replacement
The 8741/8741A and 8041/8041A contain internal program and data memory. When thlil UPI-41A microcomputer Is replaced by the ICE-41A socket In a system, the
ICE-41A mOdule supplies static RAM memory as a
replacement for the Internal microcomputer memory.
The ICE-41A module has enough RAM memory available
to emulate up. to the total 1K control memory capability
of the system.
Real·Tlme Trace
The ICE-41A module captures trace Information while
the designer is executing programs in real time. The instructions executed, program counter, port values for
port 1 and port 2, and the values of .selected UPI.-41A
status lines are stored for the last 2.55 Instruction cycles
executed. When retrieved for display, ,code is disassembled fOr u,ser convenience. This provides data for
determining how the user system wa,s. reacting prior to
emulating break.
USER SOCKET
SVNO
SYN1
CABLE
INTERNAL
BUFFER
TIMER
CONTROL
PROGRAM
8080.
CONTROL
PROCESSOR
Figure 1. ICE-41A Module Block Diagram
20-2
00804A
ICE·41A™
Integrated Hardware/Software Development
vide the user with maximum flexibility in defining the
operation to be performed. The ICE-41A software driver
is available on diskette and operates in 32K of Intellec
RAM memory.
The user prototype systems need no more than a UPI41A socket and timing logic to begin integration of software and hardware development efforts. Through the
ICE-41A module, Intellec system resources can be accessed to replace the prototype system. UPI-41A software development can proceed without the prototype
hardware. Hardware designs can be tested using
previous.ly tested system software.
Command
Hardware
The ICE-41A module is a microcomputer system utilizing Intel's UPI-41A microprocessor as its nucleus. This
system communicates with the Intellec system 8080A
processor via direct memory access. Host processor
commands and ICE-41A status are interchanged
through a DMA channel. ICE-41A hardware consists of
two printed circuit boards, the controller board and the
emulator board, which reside in the Intellec system
chassis. A cable assembly interfaces the ICE-41A
module to the user's UPI-41A system. The cable terminates in a UPI-41A pin-compatible plug which
replaces any UPI-41A device in the user system.
Operation
Enable
Activates breakpoint and display registers for use with go and step commands.
Go
Initiates real-time emulation and allows user to specify breakpoints and
data retrieval.
Step
Initiates emulation in single instruction increments. Each step is followed
by register dump. User may optionally
tailor other diagnostic activity to his
needs.
Interrupt
Emulates user system interrupt
Table 1_ ICE-41A Emulation Commands
Controller Board
Command
The ICE-41A module interfaces to the Intellec systems
as a peripheral device. The controller board receives
commands from the Intellec system and responds
through a DMA port. Three 10-bit hardware breakpoint
registers are available which can be loaded by the user.
While in emulation mode, a hardware comparator is constantly monitoring address lines for a match which will
terminate an emulation. The controller board returns
real-time trace data, UPI-41A registers, flag and port
values, and status information to a control block in the
Intellec system when emulation is terminated. This information is available to the user through the ICE-41A
interrogation commands. Error conditions, when
detected, are automatically displayed on the I ntellec
system console.
Display
Prints contents of memory, UPI-41A
device registers, I/O ports, flags, pins,
real-time trace data, symbol table, or
other diagnostic data on list device.
Change
Alters contents of memory, register,
output port, or flag. Sets or alters
breakpoints and display registers.
Base
Establishes mode of display for output
data.
Suffix
Establishes mode of display for input
data.
Operation
Table 2_ ICE-41A Interrogation Commands
Emulator Board
Command
The emulator board contains the 8741A and peripheral
logic required to emulate the UPI-41A device in the user
system. A 6 MHz clock drives the emulated UPI-41A
device. This clock can be replaced with a user supplied
TTL clock in the user system or can be strapped internally for 3 MHz operation.
Load
Fetches user symbol table and object
code from input de,!ice.
Save
Sends user symbol table and object
code to output device.
Define
Enters symbol· name and value to user
symbol table:
Move
Moves block of memory data to another area of memory.
Print
Prints user specified portion of trace
memory to selected list device.
Cable Card
The cable card is included for cable driving. It transmits
address and data bus information to the user system
through a 40-pin connector which plugs into the user
system in the socket designed for the UPI-41A device.
Software
The ICE-41A software driver is a RAM-based program
which provides the user with command language (see
Table 1, Table 2, and Table 3) for defining breakpoints,
initiating real-time emulation or single step operation,
and interrogation and altering user system status
recorded during emulation. The ICE-41A command
language contains a broad range of modifiers which pro-
Operation
List
Defines list device.
Exit
Returns program control to ISIS-II.
Evaluate
Converts expression to equivalent values in binary, octal, decimal, and hex.
Remove
Deletes symbols from symbol table.
Reset
Reinitializes ICE-41A hardware.
Table 3. ICE-41A Utility Commands
20-3
00804A
Voo= +12V, ±5%
100= 100 mA max; 60 mA typ
Vss= -10V
'
Iss=30mA
SPECIFICATIONS·
ICE·41A Operating Environment
Required Hardware
Intellec microcomputer development system
System console
Intellec diskette operating system
ICE·41A module
Input Impedance
@ ICE·41A user socket pins:
V IL =0.8V max; IIL= 1:6 mA
VIH = 2.0V min; IIH= 40 IJA
@ Bus:
V IL = 0.8V max; IlL = 250 ".A
V IH = 2.0V min; VIH = 20 ,..A
Output Impedance
@ P1, P2:
VOL = 0.5V max; IOL = 16 rnA
Vo H.= Vee (10K pullup)
@Bus: .
VOL = 0.5V max; IOL = 25 mA
VOH = 3.65V min; IOH=1 mA,
Required Software
System monitor
ISIS·II
ICE·41A diskette·based software
System Clock
Crystal controlled 6.0 MHz or 3.0 MHz internal or user
supplied TTL external
Physical Characteristics
Others
VOL = O.5V max; IOL = 16 mA
VoH';"2.4V max; IOH=4PO,..A
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 em)
Weight: 8.00 Ib(3.64 kg)
Equipment Supplied
Controller board,
Emulator board
Interface cables and buffer module
Operator's manual
ICE·41A diskette based software
Cable Buffer Box
Width: 8.00 in. (20.32 cm)
Height: 4.00 in. (10.16 cm)
Depth: 1.25 in. (3.17 cin)
Flat Cable: 4.00 ft (121.92 cm)
User Cable: 15.00 in. (38.10 cm)
Reference Manuals
9800465 -ICE·41A Operator's Manual (SUPPLIED)
RefEm3nce manuals are shipped with each product only
if designated SUPPLIED (see above).' Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051:'
Electrical Characteristics
DC Power Requirements
Vee= +5V, ±5%
lee= 10A max; 8A typ
ORDERING INFORMATION
Part Number
Description
MDS·41A·ICE
UPI·41A (8741, 8041, 8741A, 8041A)
CPU
In·circuit emulator, cable assembly
and interactive diskette software
included
20-4
OOB04A
2920 Signal Processor
Development Systems
2'1
inter
2920 SIGNAL PROCESSING APPLICATIONS COMPILER
• Compiler generates 2920 Assembly
Language Code
• Interactive software support tool for
2920 Signal Processor
• Extensive command set for designing
electrical filters
• Extends Intellec® Microcomputer
Development System support of the
2920
• Graphics capability enhances analysis
of filter response
• Contains MACRO library,for several
standard filters and signal processing
functions
• Powerful MACRO capability for
executing frequently used routines
The 2920 Signal Processing Applications Compiler (SPAS20) is an interactive tool for designing software to
execute on the 2920 Signal Processor.
The SPAS20 package can be visualized as being comprised of three inter-related sections: A compiler
section, a filter design section, and a MACRO section.
Among the capabilities of SPAS20 are: ability to generate 2920 assembly language code directly from
specifications of signal processing building blocks such as filters and waveform genrators; ability to
generate 2920 assembly language code for several classes of algebraic equations such as Y=C • X, Y=C •
Y, and Y=C • X + Y where X,Y are variables and C is a constant; ability to examine time and frequency
responses of filter sections specified by continuous or sampled poles and zeroes; ability for users to
implement more complex commands by grouping sets of commonly used commands into a MACRO.
The SPAS20 package runs under ISIS-II on any Intellec Microcomputer Development System with 64K
RAM. The output of SPAS20 can be assembled with the 2920 assembler, tested with the 2920 Simulator,
and programmed into the 2920 chip with the Universal PROM Programmer for prototyping.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: BXP, Intellec, Multibus, i, iSBC, MuJtimodule, ICE. iSBX, PROMPT. ieS. Library
Manager, Promware. In site, MeS, RMX, Intel, Megachassis. UPI, Intelevision. Micromap, ,.Scope and the combination of ICE. ieS. iSBC. iSBX, MeS. or RMX and a numerical
suffix.
© Intel Corporation 1980
21-1
121563-001 Rev. A
2920 SIGNAL PROCESSING APPLICATIONS COMPILER
FUNCTIONAL DESCRIPTION
The 2920 Signal Processing ApplicafionsCompiler
gives the analog designer a "high levellang'uage"
for his 2920applications'--'it decreases the need to
code 2920 assembly language. Furthermore, the
compiler is interactive. This feature enables the
designer to define a filter, graph its response, and
change its parameters many times, without having
to program and test the filter in an actual 2920
implementation. The command language is very
similar to that of Intel's In-Circuit Emulators."
HOLD
Command to correct attenuation
due to sample-and-hold distortion:
if ON, it corrects absolute gain by
sin(x)!x and phase by adding x,
where x=TS*FREQ*n. It corrects
group delay by subtracting n*TS.
EVALUATE
Gives the decimal numeric value of
any expression.
CODE
Once a filter is realized by moving poles and zeros
in the continuous and sampled planes, the filter
may be coded and written onto an ISIS file. Several
other file commands are available to store and
retrieve command sequences for SPAS20
sessions.
The SPAS20 compiler also recognizes the followingcommands for file handling:
PUT!
APPEND
Writes out objects (commands) to
a specified file, either creating a
new one or appending an existing
one. This enables the user to
store all or part ofa SPAC20 session on a diskette to be brought
back later with the INCLUDE
command.
DISPLAY
Copies the contents of a file to the
console.
INCLUDE
Executes a sequence of
instructions from a diskette file as
if they were typed in from the console.
LIST
Creates a file containing
console interactions.
SPAS20 Command Language
DEFINE
This command defines a pole or
zero by associating it with a
number (Le., POLE 3), and with real
and imaginary coordinates in the
continuous or sampled plane.
This command also defines a symbol by associating a name with a
numeric value, or a MACRO by providing a pointer to a specified command sequence.
GRAPH!
OGRAPH
This command graphically displays
the values of object(s) specified.
For example, GRAPH GAIN and
GRAPH PHASE are used to display
filter response. The OGRAPH command will "overgraph" the new
response over the old response,
after any changes have been
made. (You may also graph Group
Delay, Step, and Impulse.)
MOVE
Allows the definition of a pole or
zero to be changed-its coordinates, its plane, or both.
REMOVE
Deletes the definition of a pole,
zero, symbol, or macro.
HELP
Types an explanatory message on
the console, pertaining to a command or its attributes;
. Creates 2920 assembly language
code for given poles, zeros, and
equations.
ali
In addition to naming macros for specific command sequences, compound and conditional
commands may be formed using all of the above
statements. These compound commands are:
21-2
IF
Establishes conditional flow of
control within a block of
commands.
REPEAT
Used for repetition of a block of
commands; executes indefinitely
or until a condition is met (using
WHILE, UNTIL, and END
statements).
COUNT
Establishes the number of times a
command sequence is to be
executed, in a looping fashion.
AFN-013BSA
inter
2920 SIGNAL PROCESSING APPLICATIONS COMPILER
SPAS20 MACRO Facility
Define a macro, specifying its name,and an'y
parameters that are to be used by the block.
This definition is followed by the contents of
the macro (commands) and the EM statement
to end its definition.
A macro is a sequence of commands that is stored
on a temporary diskette file. The command
sequence is executed when the macro name is
entered as a command. This saves repetitive entry
of the sequence, and permits alogorithms to be
saved on diskette for future use. This SPAS20
facility allows you to do the following:
•
List the names of all defined macros.
•
•
Remove any or all macros.
Invoke a macro by entering its name and
appropriate values for any parameters.
Display the text of any macro.
SAMPLE SPAS20 SESSION
-:FI
:SP~C20.SFT
ISIS-II 2920 SIGNAL PROCESSING APPLICATIONS
O~EFINE
POLE
CO~PILER.
VI,O
I CREATE A POLE IN CONTINUOUS S-PLANE
= -707.707
1
OPZ
; LIST ALL POLES AND ZEROS
PO.E I = ,707,00000.707,00000.CONTINUOUS
•*rSCALE
::I
otc'fSCALE
100~
, ESTABLISHES FREQUENCY RANGE OF INTEREST
10000
ESTABLISHES
-45,1
PLOT
~AGNITU~E
~AGNITUOE
RESPONSE RANGE OF INTEREST
RESPONSE OF POLE PAIR
G41 H
1 0
............ 1
- t
-;
-?
~
- 11)
- 1Z
- 1~
- 1';' 5
- 1.3. ;"
-21)
~
-23
- 2'3
-z?
-2~
,
- 31
-H ,)
-3'; 2
-3)
4
- of I)
-41'
-45
..
I)
~BIHZ
.... ..
I"
100 150 200
300 400 500
700 1000 1400 2000
.... !
3000
5000
10000
'J THE UNITS USED IN GRAPHING GAIN ARE SHOWN IN THE LOYER LEFT CORNER,
.; GAIN IN DECIBELS IS GRAPHED VERSES FREQUENCY IN HERTZ,
.; PREPARE TO ~OYE TO THE DIGITAL OO"AIN,
.; SA~PLE RATE MUST 8E SPECIFIED,
.rs
TS
= 1/13020
7,6805004/10"5
=
RATE FOR
1~2
INSTRUCTION PROGRA" AND 10"H2 CLOCK
21-3
AFN-01386A
2920 SIGNAL PROCESSING APPLICATIONS COMPILER
SAMPLESPAS20 SESSION (Cont'd.)
o~OVE
POLE TO Z
1 POLES/2EPOES "OVED
or
'POLE
=
j
I CONVERT FILTER TO DIG1TAl YIA "ATCHED-Z TRANSFOR"lTION
LIST TRANSFORKED POLE
0 71092836,0.341183.9,2
.; tOKPARE RESPONSES OF THE ANALOG AND DIGITAL FILTERS BY GRAPHING THE
.' HEW RESPONSE OVER THE OLD
. !
j
~
--
,
'-'5
-
,t-.
+-
-11)
-1l'
-H
+'
1
t' .
-: .;
- t
+' -
.. '_;
-
~
+
-23
-25
-
t.
'
++
-2""
-.+
...
-2~
++
- 3]
++
-30 •
tt
-4')
- 4 ,1
--415
C'B I H2
.
.•
100 150 200
300 400 500
700 1 DOD 1400 2000
,
3000
..
10000
5000
0; PLUS SIGHS INDICATE OLD CURYE .
• ; HOTE THAT THE DIGITAL FILTER RESPONSE BEGINS TO INCREASE AGAIN
' ; AT HALF THE SA"PLE RATE ( 6510 HZ >.
0: THE PHASE CHARACTERISTICS OF THIS FILTER CAN BE EXA"INED.
o
.Y8C~LE
•OCRAPH
= -PI,PI
PHASE
..
PH~SE
I ESTABLISHES RANGE OF INTEREST
. .
. .
. .. .... .
,
. ....
.
..
. !
3 !.t
2 $4
2 54
2
1
1
1
1
24
H
';5
35
05
0 75,
0 45
Q 15
-0 15
-0 45
-0 75
-1
, . 11 ... _ _ _ _ _ _ _
I
, __
..
1)5
-1 35
'-
--' ,
.5
- 1
-1 H
-2 .24
-2 54
-2 84
-3 14
RAOIH2
p.
• PUT
•C,)LJ f.
I.
... .
.
.
:Fl ;POLE PZ
.
,
300 400 500
100 150 200
I
700 1000 1400 2000
SAVE THE PO LE LOCATION IN
; ~i:.N~~~H-i i::
F C:L t. 1 IHSTJUT I_PI, OUTD-PI ,ROO
OUTI_PI-I.OOOOOOOooOUTO_PI
QUTO_PI,OUlI_PI,ROS
: OUTO_PI-I.00000000oOUTO_PI-O.0312S0000o0UTl_PI
OUTO_PI,OUTO_PI,R03
OUTO_PI=I.12S00000o0UTO_PI-O.OJ5156250o0UTl_Pl
OUTO_PI, OUlI_PI, R02
: OUTO_PI-I. 12500000'OUTO_PI~O.21484375*OUTI_PI
OUTO_PI, OUTLPI ,ROI
; OUTO_PI-I. 1250000000UTO_PI+O.21484375'0UTI_PI-0 50000000'0UT2_PI
OUTO_PI,OUT2_PI,ROB
, OUTO_PI-I. 1250000000UTO_PI+0.21484375'OUTI_PI~O.50390'25*OUT2_PI
OUTO_PJ,OUTLPLRII
: OUTO_PI-I. 1250000000UTO.PI+O.2148437S*OUTI.PI-O.50341796*OUT2_PI
OUTO_PI, OUTLPI ,R09
: OUTO_PI-I. 12500000o0UTO.PI+O.2148437S.0UTI_PI-O.S05J7109*OUT2_PI
OUTO_P\, INO_P I, ROO
, OUTO_PI-I. 1250000000UTO_PI+0.2148437So0UTI_PI-O 5053710900UT2_PI+I .OOOOOOOO-IND_PI
OUT2_PI=I.000~OOOO'OUTI_PI
SUB
ADD
ADD
SUB
SUB
ADD
SUB
ADD
'J
OJ
OJ
OJ
0;
OJ
TNE CODE COftnANO SPECIFIED THAT THE POLE PAIR BE CODED IN LESS THAN II
INSTRUCTIONS, SO 10 INSTRUCTIONS WERE GENERATED, YITH COftUNTS.
THE FINAL ERROR IN RADIUS AND ANGLE FOR THE POLE PAIR WAS OF THE
ORDER DF 1/10005 AS IHOICATED ABOYE IN PERROR.
THIS OPTIftIZEO 2920 AISEnBLY CODE CAN NOW BE APPENDED TO A FILE
WHICH ftAY COHTAIH OTHER CODED FUNCTIONAL BLOCKS OF A 2920 PROGRA"
SPECIFICATIONS
OPTIONAL SOFTWARE:
Operating Environment
MCI-20-SPS (Contains 2920 Signal Processor
Applications Compiler and the 2920 Assembler
Simulator.)
REQUIRED HARDWARE:
Intellec'" Microcomputer Development System
-Model BOO
-Series II (Model 220, 230, or 240)
64K bytes of memory
One or two floppy diskette drives
-Single or Double Density
System Console
-CRT or TTY
2920 Signal Processing Applications Compiler
User's Guide (121529)
REQUIRED SOFTWARE:
Single and Double Density Flexible Diskettes
Documentation Package
Shipping Media
ISIS-II diskette operating system, V3.4 or later
ORDERING INFORMATION
OPTIONAL HARDWARE:
iSBC-310 High Speed Mathematics unit
(Speeds calculations by factor of 4X or more).
Universal PROM Programmer
21-5
Product Code
Description
MCI-20-SPAS
2920 Signal Processing
Applications Compiler
AFN·Q1386A
2920 SOFTWARE SUPPORT PACKAGE
• Complete software design imd
development support for the 2920
• Extends Intellec®· Microcomputer
Development System to support 2920
software development
The 2920 Software Support Package furnishes a 2920 Signal Processing Applications Software/Compiler, 2920
Assembler, and 2920 Software Simulator. These three software design and development tools run on the Intellec®
Microcomputer Development System.
The 2920 Signal Processing Appiication Software/Compiler is an interactive tool for designilJg software to be
executed on the 2920 Signal Processor. The compiler accepts English-like statements from the user and generates
2920 assembly language code.
The assembler tra,lslates symbolic 2920 assembly language programs into the machine operation code. The user can
load the code into the simulator for 2920 simulation or to the Universal PROM Programmer for 2920 EPROM
programming.
The simulator, operating entirely in software, allows the user to test and symbolically debug 2920 programs. The user
can specify input signals, simulate program execution, set up breakpoints, display input and output, and display and
alter the contents of the 2920 registers and memory locations. The simulator can also stop or trace the program and
constructively give the user access to the key elements im,ide a 2920 for analyzing his program.
The compiler, assembler, and simulator enable ·the designer to develop and test an entire program without a
complete prototype design. The 2920 designer works on the Intellec® Microcomputer Development System rather
than on a breadboard. The development system can program, store and recall programs or routines and aid in 2920
program design.
2920 Software Support Package
The fOllowing are Irade~arks of I"nlel Corproation and may be used only I? identif.y Intel products: BXP, Intellec, Mult!bus. i. iSBC, Mu!Hmodule, le'E. iSBX, PROMPT, iCS~ Lib~ary
Manager, Promware. Insite, MeS. RMX, Intel, Megachassis. UPI, Intelevlsion, Mlcroamp, /IScope and the combination of ICE, iCS, ISSC. ISBX. MeS, or RMX and a numerICal
suffix.
Sept 1980
Intel Corporation 1980
1662208
21-6
2920 SOFTWARE SUPPORT PACKAGE
2920 SIGNAL PROCESSING APPLICATIONS
SOFTWARE/COMPILER
• Interactive software support tool for
2920 Signal Processor
• Compiler generates 2920 Assembly
Language Code
• Extensive command set for designing
electrical filters
• Extends Intellec® Microcomputer
Development System support of the
2920
• Graphics capability enhances analysis
of filter response or piecewise linear
function approximations
• Contains. MACRO library for several
standard filters and signal processing
functions
• Powerful MACRO capability for
executing frequently used routines
The 2920 Signal ProceSSing Applications Software/Compiler (SPAS20) is an interactive tool for designing
software to execute on the 2920 Signal Processor.
The SPAS20 package can be visualized as being comprised of four inter-related sections: A compiler section,
a.filter design section, a curve fitting section, and a MACRO section.
Among the abilities of SPAS20 are: ability to generate 2920 assembly language code directly from
specifications of signal processing building blocks such as filters and waveform generators; ability to
generate 2920 assembly language code for several classes of algebraic equations such as Y = C· X, Y =C· Y,
and Y = C· X + Y where X, Yare variables and C is a constant; ability to generate 2920 assembly language
code for one variable function Y(X) = F(X); ability to examine time and frequency responses of filter sections
specified by continuous or sampled poles and zeroes; ability to examine piecewise linear approximation of
specific function; ability for users to implement more complex commands. by grouping sets of commonly
used commands into a MACRO.
The SPAS20 package runs under ISIS-lion any Intellec® Microcomputer Development System with 64K
RAM. The output of SPAS20 can be assembled with the 2920 assembler, tested with the 2920 Simulator, and
programmed into the 2920 chip with the Universal PROM Programmer for prototyping.
21-7
AFN·01386A
inter
2920 SOFTWARE SUPPORT PACKAGE
FUNCTIONAL DESCRIPTION
DATA
The 2920 Signal Processing Applications Software!
Compiler gives the analog designer a "high level
language" for his 2920 applications-it decreases
the need to code 2920 assembly language. Furthermore,the compiler is interactive. This feature
enables the designer to define a filter, or transfer
function, graph their response, and change their
parameters many times, without having to program
and test in an actual 2920 implementation.
This command allows for specification of a set of vertices (i.e. X - Y
coordinate pairs) which determine a
piecewise linear approximation of
some defined function, filter
response characteristics, etc.
HOLD
Command to correct attenuation
due to sample-and-holddistortion:
if ON, it corrects absolute gain by
sin(x)!x and phase by adding x,
where x=TS*FREQ*1I. It corrects
group delay bysubtracting 1I*TS.
EVALUATE
Gives the decimal numeric value of
any expression.
CODE
Creates 2920. assembly language
code for given poles, and zeros,
equations, and user definedfunctions.
Once a filter is realized by moving poles and zeros
in the continuous and sampled planes, the filter
may be coded and written onto an ISIS file. Similarly, after a function Y = F(X) has been defined, the
code for a piecewise linear approximation can be
stored onto an ISIS file. Several other file commands are available to store and retrieve command
sequences for SPAS20 sessions.
The SPAS20 compiler also recognizes the following commands for file handling:
SPAS20 Command Language
DEFINE
This command defines a pole or
zero by associating it with a
number (i.e., POLE 3), and with real
and imaginary coordinates in the
continuous or sampled plane.
This command also defines a symbol by associating a name with a
numeric value, or a MACRO by providing a pointer to a specified com_
mand sequence.
GRAPH!
OGRAPH
MOVE
This command graphically displays
the values of object(s) specified.
For example, GRAPH GAIN and
GRAPH PHASE are used to display
filter response. The OGRAPH command will "overgraph" the new
response over the old response,
after any changes have been
made. (You may also graph Group
Delay, Step, and Impulse.)
Deletes the definition of a pole,
zero, symbol, or macro.
HELP
Types an explanatory message on
the console, pertaining to a command or its attributes.
FIT
This command performs curve fitting, i.e. it approximates an arbitrary
user supplied function with a piecewise linear function.
Writes out objects (commands) to
a specified file, either creating a
new one or appending an existing
one. This enables the user to
store all or part of a SPAS20 session ona diskette to be brought
back later with the INCLUDE
command.
DISPLAY
Copies the contents of a fileto the
console.
INCLUDE
Executes a seq·uence of
instructions from a diskette file as
if they were typed in from the console.
LIST
Creates a file containing
console interactions.
all
In addition to naming macros for specific command sequences, compound and conditional
commands may be formed using all of the above
statements. These compound commands are:
Allows the definition of a pole or
zero to be changed-its coordinates, its plane, or both.
REMOVE
PUT!
APPEND
21-8
IF
Establishes conditional flow of
control within a block of
commands.
REPEAT
Used for repetition of ?block of
commands; executes -indefinitely
or until a condition is met (using
WHILE, UNTIL, and END
statements).
COUNT
Establishes the number of times a
command sequence is to be
executed, in a looping fashion.
AFN·01386A
intJ
2920 SOFTWARE SUPPORT PACKAGE
Intel also supplies several MACRO library files con·
taining the following commonly needed MACROs:
• Filter design MACROS
- Butterworth filter
- Chebyshev filter
- Bilinear transform
.- Evaluate gain or phase of digital filter
in parallel form
.,- Time response simulation
Function design MACROs·
- Code and error optimization
- Calculate instertitial error
·MACROs for generation of 2920 code
- Code for all·POLE filter
- Input and AID conversion
- Multiplication
- Division
- Logarithm functions
- Square·root functions
- Sinewave oscillator
SPAS20 MACRO Facility
A macro is a sequence of commands that is stored
on a temporary diskette file. The command
sequence is executed when the macro name is
entered as a command. This saves repetitive entry
of the sequence, and permits alogorithms to be
saved on diskette for future use. This SPAS20
facility allows you to do the following:
•
Display the text of any macro.
•
Define a macro, specifying its name and any
parameters that are to be used by the block.
This definition is followed by the contents of
the macro (commands) and the EM statement
to end its definition.
•
Invoke a macro by entering its name and
appropriate values for any parameters.
•
List the names of all defined macros.
•
Remove any or all macros.
SAMPLE SPAS20 FILTER DESIGN SESSION
-!
PI
SPAS20 • SFT
!
ISIS-II 2920 SIGNAL PROCESSING APPLICATIONS COMPILER. V2.0
o
, CREATE A POLE IN CONTINUOUS S-PLANE
o&EFINE POLE I • -707,707
oP:
POLE
I
•
; LI ST ALL POLES AN~ ZEROS
-707.00000.707.00000.CONTINUOUS
oFSCALE' 100,10000
, ESTABLISHES FREQUENCY RANGE OF INTEREST
o
.Y'C4LE
~ACNITUDE
ESTABLISHES
-45,1
·RESPOHSE RANCE OF INTEREST·
o
PLOT
oGRAPH GAIN
CAl"
I
~ACNITUDE
RESPONSE OF POLE PAIR
.................................................... .
•
••
0
,
1.0
-4. ~
•••
,
-
-
•••••••••••••••••
-::. ""
·s. i
-?~
-! I). I)
-1,L!
-H.;
-11).5
-I ~ .•
-2r). ,
-2',1
- 2'. J
- 2? S
-2~.
':"
-3L
~
-H.~
-31).2
-J! .4
-4') • .;.
-4l'. ~
-45 .. (l
DB I HZ
~
••••• "' .... A
100 150 200
~
.......... ".
• • ....
300 400 500
•
• • ... •
• •
.....
•
•
•
...................... A
700 1000 1400 2000
3000
•••••••••
5000
!
10000
o•
•• ;
THE UNITS USED IN GRAPHING GAIN ARE SHOWN IN THE LOWER LEFT CORNE~ .
• , CAIN IN DECIBELS IS CRAPHn· VERSES FREQUENCV IN HERTZ
o
., PREPARE TO nOVE TO THE &ICITAL &O"AIN .
• , SA"PLE RATE "UST 8E SPECIFIED.
.
o
.rs • UI3020
rs = 7.'805004/10'05
RATE FOR "2 IHSTRUCTION PROCRA". AND 10"H2 CLOCK
21-9
AFN·O,386A
2920 SOftWARE SUPPORT PACKAGE
SAM·PLE SPAS20 FILTER DESIGN SESSION (Cont'd.)
.""YE POLE TO Z
I POLES/ZE'OE~ ~OVED·
;
CONVERT FILTER TO DIGITAL VIA RATCNU-z' TRANSFORRATlOti
•
. p . , ' LIST TRAHSFOR"EO POLE
POLE I
0.710'2836,O.34118369,Z
•
•
.,
~oii·PARE RESPONSES OF THE ANALOG AND DIGITAL FILTERS BY GRAPHINC THE
.: HEY .RESPONSE OYER THE OLD. '
•
.OI:P!~P~ ·.GA~
G~.
:.1
t'I
I ..... ' ... ' .. '. ,'. ' ....... ' .... '. :. .. ' ... :-: ... ' ........
.... --- .... -- -,- --- ... _- ---,-" ----- ...
.. '3.4
,~;
..
-Ij.~
..
-1 ,), I)
'-.+- •
-12'. 1
.. 1".3
....'.
-7.
i. ..... ' ........ '. I
~
'
-:..).~
-lL':"
.'-
+'"
..'. •• .. ..
+ '-.
+. -.
-lO.?
-lJ.l
-25.;
_,21.'5
'--
'
••
-2~.'"
.. 31. 'it
-H.,)
-J';'.Z
-B.4
-4,) ...
-42. ~
-45·"
,,81HZ
I
......
...,,"
...
A
...
...
100' iso '200" • 300 '400' 500' • 700' i.ooo· i 400 '2000'
,.
• 3000"
••. + .:
••
I
A
.. 5000'"
••
.
'iciooo
•
.; PLUS SIGNS INDICATE OLD CURVE
.; NOTE THAT THE DIGIr'AL FILTER RESPONSE BEC·INS TO INCREASE AGAIM
.; AT HALF THE SA"PL£ RATE ( 6510 HZ ),
., THE PHASE CHARACTUISTICS OF THIS FlUEt CAN BE ,EXA"INED
•
•.CRAPH
.YSC~LE
PHtlSE
3,1'"
2.$4
2.54
• -PI.PI
I
ESTABLISHES RANCE OF INTEREST
PHASE
I. '"
."" • • • " • • • • • "' •• ,"" • • • "" • • • ,A, . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . .
!
2.24
1.94
1.65
1.35
I. 05
0.75
0.45
0.15
-0.15
-0.45
-0.75
-1.05
-1.35
, .. , , ' --------
-I 65
-I : , .
-2.24
-2.54
-2.84
-3·\4
RADIHZ 1', •••.• "' ••. "' ••.•• A
p.
•.PUT
•.C·)O(
100 150 200
'FI'POLE PZ
P'OLE I
8,=1 339B"'0
INST.~ll
••
~'"
.....
~.~
•• "
..... "
•.•• "
... ; ••.•. , ... ,
300 400 500 .700 1000 1400.2000
I
...............................
3000
5000
1
10000
SAVE THE PO(E LOCATION IN A DISK FILE BACKUp
I
GlH~RA'1 ~ ~~lU ASH~tLY
I;OOE FUR THIS t IL 1~~,·
B2--0.50541914
21-10
AFN.()1386A
2920 SOFTWARE SUPPORT PACKAGE
SAMPLE SPAS20 FILTER DESIGN SESSION (Cont'd.)
OPTI"IZED 2'20 CODE IS NOW GENERATED TO SAVE SPACE, SO"E
OF THE SCREEN OUTPUT HAS BEEH DELETED NOR"ALLY ALL ATTE"PTS
BY THE CO"PILER TO GEHERATE CODE ARE ECHOED OH THE SCREEH
IHST=IO
POLE I = 0.71089458,0.34116779,Z
BE';!: PERROR = 33795874/10"S,I.588465i7/10 •• S
; NOTE: "AKE SURE SIGNAL IS <0 74635571
QUT2_PI,OUTI_PI,ROO
OUT2_PI-I OOOOOOOO-OUTI_PI
LD~ OUT I_PI, OUTO_PLROO
OUTI_PI-I.OOOOOOOOoOUTO_PI
SUB OUTO_PI,OUTI_PI,R05
; OUTO_PI'I .00000000oOUTO_PI-O 03125000000UTI_PI
ADD OUTO_PI,OUTO_PI,R03
OUTO_PI-I.1250000000UTO_PI-0.03515625000UTI_PI
ADD OUTO_PI,OUTI_PI,R02
; OUTO_PI-I.1250000000UTO_PI+0.2148437S00UTI_PI
SUB OUTO_PI, OUTLPI ,ROI
; OUTO_PI-I 1250000000UTO_PI+O.2148437500UTI_PI-O.SOOOOOOOoOUT2_PI
SUB OUTO_PI,OUT2_PI,ROB
OUTO_PI·I. 1250000000UTO_PI+O.2148437S00UTI_PI-O.S0390625o0UT2_PI
ADD OUTO_PI. OUTLPLRII
: OUTO_PI'I.1250000000UTO_PI+0 214B437S00UTI_PI-0 S034179600UT2_PI
SUB OUTO_PI,OUT2_PI,R09
LD~
: OUTO_Pl-1.12500000.0UTO_Pl+Q
21.e437~.OUT1_PI-0
5053710~.OUT2_Pl
ADD OUTO_PI. INO_P I, ROO
; OUTO_PI-I 12S0000000UTO_PI+0.21484375.0UTI_PI-0.SOS37109*OUT2_PI_I OOOOOOOOoINO_PI
.;
.;
0;
.;
•;
.;
THE CODE CO""AHD SPECIFIED THAT THE POLE PAIR BE CODED IH LESS THAN II
INSTRUCTIONS, SO 10 INSTRUCTIONS WERE GENERATED, WITH CO"UNTS.
THE FINAL ERROR IH RADIUS AND ANGLE FOR THE POLE PAIR WAS OF THE
ORDER OF 1/10"5 AS INDICATED ABOVE IN PERROR .
THIS OPTI"IZED 2920 ASSE"BLY CODE CAN NOW BE APPENDED TO A FILE
YHICH "AY CONTAIN OTHER CODED FUNCTIONAL BLOC~S OF A 2920 PROGRA"
.
• E;*
o
*
o *
o *
o *
o *
1
1
I
o *
I
I
*
o *
o *
1
SIMULATION TERMIN~TED
*
I
1
2 1
3 •
*EXIT
SPECIFICATIONS
Optional Software
Operating Equipment
FORTRAN-80 (Product Code MDS-301)
Required Hardware
Intellec® Microcomputer Development System
-Model 800 or 888
-Series II Model 220, 225, 230
64K Bytes of RAM Memory
One or two Floppy Disk Drives
--Single or Double Density
System Console
-CRT or interactive hard copy device
Documentation Package
2920 Assembly User's Guide (9800987)
2920 Simulator User's Guide (9800988)
2920 Signal Processing Application Compiler
User's Guide (121529)
Required Software
ISIS-II Diskette Operating System
Optional Hardware
Shipping Media
Line Printer
iSBC-310 High-Speed Mathematics Unit
Universal PROM Programmer
Flexible Diskettes
-Single and Double Density
ORDERING INFORMATION
Product Code
Description
MCI-20-SPS
2920 Software Support Package
Includes 2920 Signal Processing
Application Software/Compiler and 2920
Assembler/Similator Software
21-16
AFN-01366A
Memory Systems
22
SERIES 90
GENERAL PURPOSE MEMORY SYSTEM
Memory Modules only or Fully Inte• grated
and Tested Packaged Systems
• Multiple System Packages Available
of Storage Technologies and
• Variety
Performances
Enhancement Modules Avail• Optional
able Including ECC
• User Configurable for Each Application
• Standard BXp™ Memory Bus
• 10 MHz Word Transfer Rates (Maximum)
• Word Widths from 16 Bits to 88 Bits
The Intel® Series 90 is a family of general purpose memory products which are available as standard systems
and are user configurable to provide an optimum solution for individual applications. The system can
incorporate new and future generations of technologies as they become available, without changing the user's
system design, providing an easy growth path for the future. All systems are fully tested to Intel's quality
standards in the user's configuration.
For full information, refer to the Series 90 Data Catalog.
The following are trademarks of Intel Corporation and maybe used only to identify Intel products: i, Intel, INTEL, INTELLEC, MeS, im , ieS, ICE. UP!, BXP, iSBC. iSBX, INSITE, iRMX,
CREDIT, RMXIBO, ~Scope, Muttibus, PROMPT, Promware, Megachassis. Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE, sec, RMX or iCS and a numerical
suffix; e.g., iSeC-eO.
JUNE 1981
© Intel
Corporation, 1981.
22-1
AFN-01720B
intel·
SERIES 90
FUNCTIONAL DESCRIPTION
INTERFACE TYPES
The heart of the Series 90 is the standard BXP™
(Byte Exchange Path) memory bus, which provides
a common data exchange and control path for a
wide variety of memory storage media. Basic system
architecture is shown' in Figure 1. The user has the
option of interfacing to the system either to, the BXP
bus (System 90 and.System 92 only) or to the gen,eral
purpose enhancimi'enl modules described below.
As stated above, the Series 90 may be used by interfacing either to the BXP bus or to a general purpose
enhancement module. This section gives the user an
overview of the product features and enablEl,s a
preliminary selection of the optimum configuration.
There are three ba~ic systems presently in the Series
90 family. The System 90 is a high-performance
dynamic memory system with performances of 275
and 350 Ilanosecond cycle tim,es ,and capacities
ranging from 2,56, kilobytes up to 16 megabytes
within a single chassis. The System.91 is a ,lower-cost
product with slower cycle times of 500 and 650
nanoseconds and capacities up to 32 megabytes in a
single chassis. Greater capacities can be easily accommodated by daisy-chaining systems together. '
The System 91 becomes cost effective at capacities
greater than a megabyte.
The System 92 is the highest-performance member
of the Series 90 family and uses static technology
with a cycle time of 100 nanoseconds. See capacities
range from 64 Kb to 4 Mb in a single chassis.
BXpTM Systems
The BXP memory bus provides an extremely flexible, yet easy to use, set of protocols; The bus may be
operated in either a synchronous or asynchronous
mode of operation, for read, write, read-modifywrite, or swap cycles. Interleaving is an imp'ortanf
feature of these'systems, improving thruput byoverlapping. 'memory module cycles. Interleaving
enables word data rates up to 10 MHz bus limitation,
independent of the cycle time of the memory modules and can be achieved with either synchronous
(sequential addresses) cycles or asynchroncius
cles.
Cy-
For users who do not need the additional features of
the general purpose enhancement modules, the
BXP systems provide an efficient solution, and are
available within either the System 90 or System 92
members of ttil:l family.
EN~~~~8~EE!,T
MODULES
(OPTIO~AL)
Figure 1. Sy~tell1 Architectu re
. 22-2
AFN-01720B'
intel'
SERIES 90
Enhancement Features
remote error reporting and fault-isolation; offloading of memory management overhead; and
simple message-driven interface protocol.
These enhancements provide additional degrees of
functionability over and above that provided by the
ECX (error correcting) and iQX (intelligent controller). See Table 2 for a feature comparison, including memory module speeds and capacities.
SYSTEM PACKAGES
The Series 90 is available as a completely tested and
packaged system. There are two Series 90 packaged
systems available for.19" rack mount.
ECX
This feature essentially performs all the functions of
the BXP systems, and provides additional functions,
primarily Error Checking and Correction (ECC). This
corrects all single bit errors and detects double bit
errors. These systems.are also available with an optional error logger and display to facilitate maintenance and diagnostics.
The 5%" high HMS chassis has self-contained power
supplies and cooling, and will house up to four
memory modules.
The 12%" high VMS has self-contained power supplies and requires externally supplied vertical air
flow. An optional 5%" rack-mountable blower assembly is available. The VMS will house up to 16 memory
modules.
iQX
For asynchronous applications that do not require
interleaving, this intelligent enhancement offers advanced features such as ECC; fault-tolerant
(uninterruptible) operation; versatile maintenance
tools; selHest and automatic memory diagnostics;
The maximum system capacities as a function of the
module capacities shown in Table 2 are shown in
Table 3.
Table 2. Feature Comparison
Enhancement Features
BXpTM Systems
System 90
System 91
System 92
iQX
ECX
275 ns cycle, 256 Kb;
350 ns cycle, 256 or 1024 Kb;
synchronous or asynchronous;
interleaved
Not Available
275 ns cycle, 256 Kb;
350 ns cycle, 256 or 1024 Kb;
synchronous or asynchronous;
EGG interleaved;
500 or 650 ns cycle; 2048 Kb;
synchronous or asynchronous;
EGG
100 ns cycle, 64 Kb or 256 Kb;
synchronous or asynchronous
110 ns cycle, 64 or 256 Kb;
synchronous or asynchronous;
EGG
500 ns cycle, 256 or 1024
Kb; asynchronous;
EGG plus fault tolerance;
. advanced diagnostics
800 ns cycle; 2048 Kb;
asynchronous;
EGG plus fault tolerance;
advanced diagnostics
Not Available
Table 3. System Capacity Versus Module Capacity. Kb (Kilobytes), Mb (Megabytes)
Kb per Memory
Module
HMS Maximum
Capacity
System 90
256 Kb
1024 Kb
1 Mb
4 Mb
System 91
System 92
2048 Kb
64 Kb
256 Kb
8Mb
256 Kb
1024 Kb
VMS Maximum
Capacity
4 Mb
16 Mb
- - - ---- - - - -
~
32 Mb
1Mb
4 Mb
ORDERING INFORMATION
Consult Series 90 Configuration Guide.
22-3
AFN·Q172QB
SERIES 90/iQX
INTELLIGENT MEMORY SYSTEM
• Uninterrupted System Availability
• Simple Message-Driven Interface
• Memory Task Processing
• ECC Plus Soft-Error Scrubbing
• Built-In Diagnostics
Maintenance and Error
• Remote
Reporting
• Word Widths Upto 80 Bits Plus ECC
• Up to 32 Megabytes Capacity
• Cycle Time: 500 ns and 800 ns
• Asynchronous, Bidirectional Operation
• Power Supply Monitoring and Control
Optional Hand-Held Maintenance
• Terminal
The Intel Series 90/iQX is an optional intelligent enhancement to the Series 90 family of random-access memory
systems. It is available as System 90/iQX, a high-performance dynamic RAM system; and System 91/iQX, a
high-density dynamic RAM system. The enhancement feature, which is based on an Intel 8086 microprocessor,
provides uninterrupted system availability, memory tasking, ECC plus soft-error scrubbing, extensive built-in
diagnostics, remote maintenance, and error-reporting capabilities. An integral power-supply monitor and
control unit monitors, reports, and margins up to four power supplies.
Optionally available for the Series90/iQX is a hand-held maintenance terminal (the Service Communicator)
which allows the operator to communicate with the Series 90/iQX using a versatile set of simple instructions.
The Series 90/iQX can provide up to 32 megabytes of memory in a self-contained system. Two system configurations are available, a horizontal mount system and a vertical mount system.
.
For full information, refer to Series 90 Data Catalog.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: i, Intel, INTEL. INTELLEC, MeS, 1m, ieS, I.CE, UPI, exp, iSaC, iSaX, INSITE, iRMX,
CREDIT, RMXJ80, jJ.Scope, Multibu5, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE, sac, RMX or ieSand a numerical
suffix; e.g., iSBC-BO.
NOVEMBER 1981
© Intel
Corporation, 1981.
22-4
AFN-01742B
SERIES 90/iQX
FUNCTIONAL DESCRIPTION
The Service Communicator (option) is a hand-held
unit by which the operator, through a 40-key alphanumeric keyboard and a 16-character LED display,
can communicate with the Series 90/iQX.lts primary
function is as a maintenance tool for running diagnostic programs. Approximately 40 commands are
available to the operator.
The Series 90/iQX system (Figu re 1) consists of a Series 90 vertical or horizontal mount memory system.
The vertical system provides up to 16 memory modules and up to 32 megabytes of memory; the horizontal system provides up to 4 memory modules and
up to 8 megabytes of memory. The iQX module is
located between the user and the BXP™ bus; it
provides the memory system's intelligence features,
such as fault tolerance, diagnostics, and memory
tasking. In addition, a power-supply monitor and
control unit is included to monitor, report on, and
margin up to four power supplies. It will automatically issue a warning if an out-of-tolerance voltage
is detected.
The memory system is operated in an asynchronous,
non-interleaved mode on bidirectional lines and
performs the five basic operating cycles (read, write,
byte write, read-modify-write, and swap). Refresh
operations are user-programmed to be either burst,
distributed, or distributed bursts. Word widths of up
to 80 bits plus 8 ECC bits can be accommodated.
TO HOST SYSTEM
1- - I
-R~~J~E
DATA -
--------1
ADDRESSES
CONTROU
STATUS
SIGNALS
S~::J~L
I
I
I
MAINTENANCE A
TERMINAL
/(OPTIONAL)
Y
1'------'
I
~~~~~EJlIj~L
I
I
" 7'
.--_Ll_NE_S--,
<=-=I "-)
POWER SUPPLY A
MONITOR AND
CONTROL UNIT"
"
'7
lax MODULE
v
DATA
CONTROUSTATUS
ADDRESSES
SIGNALS
'7
I
BXP'" BUS
I
I
ADDRESSES
CONTROU
STATUS
SIGNALS
DATA
I
I
I
I
I
MEMORY MODULES
(UP TO 16)
I
,I
L ___
~
_ _ _ _SERIES gO/lax MEMORY SYSTE~
_ _ , _ _ _ .:..- _ _
.J
IOX·OOl
Figure 1. Series 90/iQX Memory System, Block Diagram
22-5
AFN·01742B
SERIES 90/iQX
3. The SOS6-based modul.e also serves as a conimunications controller that links the system,
. through a modem, to a remote. diagnostic site.
The aforementioned on-board diagnostics and
fault.reporting can all be requested.and directed
from the remote site, resulting in fewer site visits
by service personnel and shortening the visits
that are required. This remote capability helps
OEM and network services implement centralized maintenance and system control.
RELIABILITY
The Series 90/iQX provides uninterrupted system
availability through a comprehensive fault-tolerant
mechanism that includes ECC, soft-error scrubbing,
and dynamic memory re-allocation.
The error correction circuitry corrects single-bit
errors and detects double-bit errors. Soft errors are
generally transient single-bit errors. However,
cumulative soft errors may lead to uncorrectabie
double-bit errors. The soft-error scrubber monitors
the error detection circu its for si ngle-bit errors. If the
errors are soft, they are corrected and restored; if
hard, they are handled by the memory re-allocation
mechanism, which automatically redirects memory
selection away from failed locations to spare memory. The re-allocation activities are totally transparent to the host system. An alert message is sent to
the host when the spare memory reserve is low.
MESSAGE-DRIVEN INTERFACE
(MAILBOX) AND TASKING
Tasking allows the iQX intelligent memory controller to perform operations on itself or on the data
contained in the memory system. To accomplish
tasking, a "mailbox" protocol is used. The "mailbox" is a portion of the memoryset aside for the
iQX/host communication. The host places a command word and parameters in the mailbox and activates an alert signal. The iQX reads the mailbox,
executes the command, stores any resulting data in
the mailbox, and returns a "task complete" signal.
This message-driven (or "mailbox") protocol can
support a more extensilieexchange of control information with a simple interface. Furthermore',
tasking can relieve the host of such chores as moving blocks of memory, filling parts of the memory
with constants, setting/resetting memory protect, or
executing diagnostic programs and reporting results. All tasking software resides in the intelligent
controller module.
With ECC, soft-error scrubbing, and memory reallocation, data integrity and system reliability are
greatly improved. The mean time between failures of
the system is extended by effective checks against
system degradation over repeated hard-error and
soft-error occurrence. By proper spare-memory design, full system availability can be attained between
longer service intervals.
MAINTAINABILITY
The Series 90/iQX is designed to reduce maintenance and repair costs over the life ofthe equipment
through a complete package of versatile maintenance tools from error logging and on-board diagnostics to a friendly interactive procedure with the
iQX controller. Highlights of the maintenance features are described below:
CAPACITY AND PERFORMANCE
1. The Service Communicator can be connected to
the memory system to read out error counts and
locations logged during system operation. The
error locations are interpreted by the SOS6 and
displayed to service personnel by rows and
columns.
The total capacity of the Series 90/iQX is determined
by the memory module and system package (hori. zontal or vertical). The capacities available are listed
under Specifications, Storage Capacity, in this data
sheet. With the VMS the capacity is up to 32 mega. bytes of dynamic RAM. System capacity can be
further increased, up to a total of four Series 90
chassis.
2. The service communicator can perform diagnostics on the memory system in either the "off-line"
or "on-line" modes of the host. The on-board
diagnostic capability allows system troubleshooting without using host time or requiring
special test routines on the host. Voltage margin
operation for preventive maintenance can also
be controlled from the. terminal.
The Series 90/iQX memory system is available with
system cycle times of 500 and sao nanoseconds,
depending on memory module type. Refer to the
Specifications section of this document, the Series
90 Configuration Guide, or the Series 90 Data Catalog for further information.
22-6
AFN-01742B
SERIES 90/iQX
CHASSIS
chassis measures 5.21 in. (13.2 cm) high by 19 in.
(48.2 cm) wide by 19.5 (49.5 cm) deep, and weighs
approximately 30 Ibs (13.5 Kg).
Two chassis configurations are available for the Series 90/iQX: a horizontal mount chassis and a vertical mount chassis. Each system is available with
either 115 or 220 VAC input power.
The horizontal mount chassis (HMS) includes up to
four memory modules, its own DC power supplies,
and a blower assembly to provide cooling air. The
The vertical mount chassis (VMS) includes up to 16
memory modules and its own DC power supplies.
The vertical mount system does not include an integrated blower. A separate blower assembly is available. The vertical chassis measures 12.25 in. (31.1
cm) high by 19.0 in. (48.2 cm) wide by 17.5 in. (44.4
cm) deep, and weighs approximately 100 Ibs (45 Kg).
SPECIFICATIONS
System 91/iQX
Cycle and Access Times
System 90/iOX
System 91/iQX
Cycle Time
. Access Time
500
800
500
800
HMS: Up to 8 Mb in 2 Mb
increments
VMS: Up to 32 Mb in 2 Mb
increments
Operating Cycles
Read Cycle
Write Cycle
Byte Write Cycle
Read-Modify-Write Cycle
Swap Cycle
Word Lengths
16, 32, 37, 64, and 80 bits plus ECC
Environmental Requirements
Storage Capacity
System 90/iQX
Ambient Operating Temperature-O°C to +50°C
Ambient Storage Temperature-40°C to + 125°C
Relative Humidity-10%to 90% without
condensation
Operating Altitude-O to 10,000 feet (0 to 3,048
meters)
Non-Operating Altitude-O to 50,000 feet (0 to
15,240 meters)
HMS: Up to 1 Mb in 256 Kb
increments or up to 4 Mb in
1 Mb increments
VMS: Up to 4 Mb in 256 Kb
increments or up to 16 Mb
in 1 Mb increments
ORDERING INFORMATION
Consult Series 90 Configuration Guide
22-7
AFN-Q1742B
CM·5044E
UNIBUS*, ADD·IN MEMORY
• PDP*11144, PDP11124 and other
UNIBUS computers
• Capacities to 1 megabyte
• ECC version..,.. single bit correct,
double bit correct
• ~ardwarelsoftware compatible
• Switches set addressing on 128K byte
boundaries
Control statusre~ister (CSR)
Sockets spa're RAMs
On-lineloff·line switch
Supports interleaving and battery
b.ack~up
,
• ..Service available,
•
•
•
•
The Intel® CM-5044E memory card is designed for use in any DEC' UNIBUS, modified UNIBUS, or extended
UNIBUS computer. It is an ECC version similar to and compatible with the DEC MS11 M memory used on the PDP
11/44. Compatibility extends to hardware, operating system, and diagnostic software. The CM-5044E can also
be used as an ECC replacement for the DEC MS11 L parity memory used on the PDP 11/24, PDP 11/34 and other,
UNIBUS computers. '
..
'.
The CM-5044E is available in capacities of 256K, 512K or1 M,byte. This gives the user space and power
savings while performance is equal to.or better'than the MS11 models. The card occupies a single ,slot
and addressing is switch selectable to 128K byte boundaries so that the CM-5044E can be used withaily
number of MS11 memory cards. Features supported include interleaving (switchselectable), battiirybackup, and a Control Status Register which allows the processor to read and manipulate status on the
memory card. The Intel CM-5044E also contains power, select and error indicators, socketted memory
chips and spare memories"and an on-line/off-line switch. All Intel memory cards are fully tested andin-.
clude a one year factory warranty. In addition, the CM5044E is fully supported by Intel's field service plans
which include installation and on-site contracts for maintenance.
·PDP, DEC, UNIBUS are Trademarks. of Digital Equipment Corporation
22-8
CM-5044E
SPECIFICATIONS
Word Size
32 bits + 7 ECC bits
Compatibility
PDP 11/04, 11/24, 11/34, 11/44, 11/45, 11/55, 11/60
computers
Memory Capacity
Interface protocol is compatible with unibus, modified unibus, and extended unibus protocols.
256K, 512K, 1024K Bytes
5044 can be used in any system as a replacement
for MS11 L (parity) or MS11 M (ECG) memory
modules.
Performance
500 ns cycle (maximum)
500 ns read access (maximum)
250 ns write access (maximum)
Completely software compatible with all
erating systems and CZMSD Diagnostics.
Power
Dimensions
Configuration
Operating, Max
Standby, Max
256 KB
512 KB
1 MB
7.3 AMPS
7.5 AMPS
7.9 AMPS
5.6 AMPS
5.8 AMPS
6.2 AMPS
15.7 in (39.88 cm) Width
8.5 in (21.69 cm) Height
0.375 in (0.953 cm) Depth
2.2 Ibs (1.0 kg) Weight
Address Selection
Environment
DIP switches select the starting address or any
64K word (128K Byte) boundary.
O°C to 50°C Operating
-40°C to 125°C non-operating
0% to 90% relative humidity (no condensation)
Modes of Operation
Read
Write (full word)
Byte Write
Reference Manual
Refresh (Transparent)
Memory Initialization
(Transparent)
Interleaving
112586 CM-5044E Technical Manual.. (supplied)
ORDERING INFORMATION
Model Number
Capacity
Equivalent
CM-5044E·256
CM·5044E-512
CM·5044 E·1 M B
256 Bytes with ECC
512K Bytes with ECC
1 Megabyte with ECC
One MS11MB
Two MS11MB
FourMS11MB
22-9
op-
in·1671
*PDp·11/70 ADD·ON MEMORY SYSTEM
• Total hardware and software
compatibility with *PDP-11170
• in-1671256K-byte basic system
expandable to two megabytes in
256K-byte increments
.
• User access to full *PDP-11/70 main
memory space at nearly four
megabytes
• MOS RAMs provide high-density
memory with low system cost
• Two-way memory system interleaving
II
ECC and error coding for single-bit
error correction and double-bit error
detection_
• High-speed CPU data transfer rate
-write cycle time 550 ns
-byte write cycle time 1000 ns
-read cycle time 770 ns
-refresh cycle time 550 ns
-access time 550 ns (no error)
-access time 600 ns (with single"bit
error)
• Installation and maintenance available
from Intel
• U L recognition
The Intel® in-1671 'PDP-11/70Add-On Memory System is a monolithic memory system offering up to two megabytes
of add-on memory for' PDP-11/70 users, thus improving' PDP-11/70 system performance with increased capacity, increased data transfer speed, improved functional and component reliability, and reduced cost. The complete in-.1671
utilizes five types of printed circuit cards: power control card, memory unit cards, control unit card, data.card, and error logging card. All components are fully hardware- and software-compatible with the DEC' central processing unit
(CPU) and are engineered to meet or exceed the specifications of similar DEC components. The Intel in-1671 is used in
'PDP-11/70 computer systems as a direct replacement for the memory module (MJll) supplied by DEC, and uses
cables and interface Signals identical to those used in DEC memory mOdu.les. The. unit may be installed without
change or modification to the DEC software, CPU, memory bus, or 1/0 structure. High-density memory is provided by
dynamic MOS RAM devices, and is expandable in 256K-byte increments to 2048K bytes.High-speed 770-nanosecond
read and 550-nanosecond write cycle times allow maximum utilization of Unibus' data throughput. The in-1671 system
includes error check and correction (ECC), error monitoring, and error logging.
22-10
inter
in·1671
FUNCTIONAL DESCRIPTION
Compatibility
The in-1671 semiconductor memory system is specifically designed as an add-on memory for the DEC
·PDP-11170 processor. The basic memory device is a
moriolithic integrated circuit using N-c.hannel MOS transistors. The complete system uses five types of printed
circuit cards: 1) control card containing address and
control circuitry; 2) data card to provide interfacing and
parity checking for read and write data; 3) error logger
card to monitor and log data error conditions; 4) memory
cards (MU-167As) for storage; and 5) power control card
to provide AC and DC low status to the processor. Each
memory module contains its own power supply and
cooling. All on-line operating sequences are controlled
by processor-supplied controller signals -and by
internally-generated response signals sent to the processor from the memory, and all system components are
engineered to meet or exceed the specifications of
similar DEC components. A simplified block diagram of
the in-1671 memory system is shown in Figure 1.
The in-1671 is specifically designed for use in ·PDP-11170
computer systems as a direct replacement for the DECsupplied memory module (MJ-l1), and uses cables and
address, data, and interface control signals identical to
those in DEC memory modules. The unit may be installed in the DEC central processing unit (CPU)
memory cabinet without change or modification to the
DEC software, CPU, memory bus, or 110 structure. All
system voltages, currents,. timing, and. 110 signal requirements are compatible with the ·PDP-11170.
0
r--- ,,
CACHE
Capacity
Card Capacity- Each memory card in the in-1671
memory system has a capacity of 128K bytes. Two
memory cards make up the basic 256K-byte storage area
of the in-1671 memory system. A fully-expanded
memory system contains two megabytes. Interleaving is
possible between two memory systems with the same
capacity.
DATA
I
I
I
·PDP 11f70
• 16
-
r--
MU·167A
MU·167A
I
'\
DATA
.I
I
I
MU DATA 1401
V
)
l\-
DATA ROY
L
UJ
--'
0
a:
I-
Z
0
()
ADDR & CONTROL)
I
ERROR LOG
ill
I
-"
'\
"ADDRESS & CONTROL
CONTROL
'\
I
ACK. BOCC. PAR
I"
I
AC, DC LOW
-
'---
AC, DC LOW-!
I
POWER
CONTROL
DC FAIL
I
I
POWER
SUPPLY
Figure 1. in-1671 Add-On Memory System Block Diagram
22-11
AFN·01904A
in-1671
System Capacity-The storage area. of the in-1671
system consists of 16 Intel MU-167A memory system
units. Each MU-167A contains 80 Intel 2117 16K
dynamic MOS RAMs to provide a capacity of 64K words
by 20 bits per card. The 16 MU-167As in the system are
configured to provide 2 megabytes of storage with a
double-word 40-bit interface. Thirty-two bits are assigned
as interface data and eight bits to error check and correction (ECG). These systems are housed in a chassis with
power supplies and fan assemblies. Two such chassis may
be mounted in one equipment rack and interfaced in
daisy-chain fashion with the processor.
Card Controls-The following controls are located
either on the control card or on the error logger card:
Expandability- Each unit is easily field-upgradable to
larger capacities with the addition of memory cards or a
memory rack containing cards. A diagram showing CPU
and memory cabinet dimensions is shown in Figure 2.
• Error logger scan switch(2)
CPU CABINET
EXPANSION
SPACE
MEMORY CABINET
INTEL
1920K BYTES
MAX
11170 CPU
DEC
128K BYTES
RESIDENT
MEMORY
_____
W=42" - - - - - -
Figure 2. PDP-11/70 CPU Cabinet and in·1671 Add·On
Memory Cabinet Dimensions
Maintainability
The in-1671 memory system provides convenient controls, reconfiguration switches, and status indicators as
standard maintainability features, all located to provide
easy maintenance access to the user.
Rear Panel Controls-The following controls
located on the rear panel of the memory module:
• Memory on-line/off-line switch to disconnect the
in-1671 from the PDP-11/70 memory bus(1)
• Reset logic switch(1)
• Error logger on-line/off-line switch(2)
• Lamp test(2)
• EGG on/off switch(2)
Card Indicators- The following indicators are provided
either on the control card or on the error logger card:
•
•
•
•
•
•
•
Address parity error indicator(1)
Mismatch error indicator(1)
Write data parity error indicator(1)
Address display(2)
Syndrome bits display(2)
Single-bit mode or double-bit mode indicator(2).
ECC on-line/off-line mode indicator(2)
(1) on control card
(2) on error logger card
INTEL
2M BYTES
MAX
H=72"
0=30" I~
-
• Address select switches to set the starting address
for the memory bank(1)
are
• AG circuit breaker
• Three power supply output voltage adjustments
22-12
The in-1671 memory system includes error check and
correction (EGC) as a standard feature. During read and
byte-write operations, multiple bit errors are detected
and single-bit errors are corrected prior to the transfer of
data. The standard • PDp·11170 parity bits (one per eightbit byte) are also generated and are included in the data
transfer. The in-1671 EGG improves memory system
reliability 10 to 25 times over systems with parity checking only. During write operations, the four standard par·
ity bits are used to check the 32-bit word for errors and
then EGC logic removes the parity bits from the data
word and generates eight EGG bits to be stored with the
data word_ During a read operation, the eight ECG bits
are read from memory with the 32·bit data word. All 40
bits are processed to generate eight· syndrome bits
which indicate whether or not a single- or multiple-bit er;
ror has occurred. Single·bit errors are automatically cor·
rected before the data is sent to the processor. Multiplebit errors cause all four standard parity bits to be forced
to the error state and to be sent to the processor. The er·
ror logger records the location of the row of memory
chips in error and which MU·167A board failed.
Reliability
Each unit is fully tested in a temperature·cycling en·
vironment. Because of the 100% burn· in performed on
each card, the user is assured of receiving Intel's proven
quality and reliability. All Intel DSC-compatible products
are covered by a one-year warranty.
AFN·01904A
in-1671
Physical Characteristics
SPECIFICATIONS
Width - 17.12 in. (43.48 cm)
Height - 10.5 in. (26.67 cm)
Depth - 25.0 in. (63.50 em)
Weight - Less than 70 Ib (31.5 kg)
Storage Capacity
up to 2048 bytes in 256K·byte increments
Word Length
Electrical Characteristics
16 bits per memory word, plus 4 parity bits per double
word
AC POWER REQUIREMENTS
Performance
Cycle Time Access Time -
1000 ns max
600 ns max
Requirement
115V AC (max)
220V AC (max)
Voltage
98V AC to
132V AC
187V AC to
252V AC
Frequency
47 to 63 Hz
single·phase
47. to 63 Hz
single·phase
Input current
8A max
4A max
Operational Modes
Read
Write
Byte write (1 or 2 bytes)
Environmental Characteristics
Interface Characteristics
Temperature - O°C to50°C operating ambient, - 40°C
to + 85°C non·operating
TTL·compatible
36 bidirectional data input/output lines
23 binary address input lines (single·ended)
Humidity -'-- 10% to 90% non·condensing
Altitude - 10,000 It max,operating; 40,000 It max, non·
operating
Installation Requirements
Equipment Supplied
All cables and connectors supplied by Intel
1 DEC memory cabinet (21"W x 30"D x 72"H)
1 in·1671 memory system
Ribbon cable supplied for installation
Reference Manuals
Notes
1. Installation can be done by the customer or pur·
chased from Intel.
2. Maintenance contracts are aV;lilable from Intel.
TM·1670·000 (SUPPLIED)
22-13
in·1670Iin·1671 Technical Manual
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative.
AFN-01904A
in·1671
ORDERING INFORMATION
SY-1671-256D/I' - 256K bytes (128K words)
Add-On Memory System for PDP-11/70
SY-1671-512D/1 - 512K bytes (256K words)
Same as above except for capacity
SY-1671-768D/1 - 768K bytes (384K words)
Same as above except for capacity'
SY-.1671-1024DII - 1.024M bytes (512K words)
Same as above except for capacity
SY-1671-1280D/1 - 1.280M bytes (640K words)
Same as above except for capacity
SY-1671-1536D/1 - 1.536M bytes (768K words)
Same as above except for capacity
SY-1671-1792D/1 - 1.792M bytes (896K words)
Same as above except for capacity
SY-1671-2048D/1 - 2.048M bytes (1.024M words)
Same as above except for capacity
'Specify
SY-1671-256D for domestic (115VAC)
SY-1671,2561 for international (220VAC)
XF-1671-256
EX-1671
XX-1671-001
XX-1671-002
XX-1671-003
XX-1671-004
XX-1671-005
XX-1671-006
XX-1671·007
XX-1671-008
XX-.1671-009
XX-1671-010
XX-1671-011
256K bytes expansion for in-1671
PDP-11/70
Card Extender
Memory Card
Data Interface Card
Control Interface Card
Error Logger Card
Terminator Card
Power Control Card
I/O Cable Assembly (Short)
Power Supply
Diagnostic Memory Tape
Branch Spare Kit
(contains EX·1671 and XXX-1671-001
thru -009)
I/O Cable Assembly (Long)
22-14
AFN-01904A
inter
in·5034
PDP*·11/04, 11/34 ADD·IN MEMORY CARD
Low Cost
On·Board Address Select DIP Switches
High Speed
Spare Memory Chips On·Board
Total Hardware and Software
Compatibility
On· Board Parity Checking and
Generation
Low Power
On·Board Control Status Register (CSR)
High Reliability
Battery Backup Provision
Hex·Height Card Size
One Year Warranty
The Intel® in-5034 is a 64K x 18 bit plug in memory card designed for use in any PDP-11/04. 11/34 computer memory
slot. It is totally hardware and software compatible with the PDP-11 system. No modifications or jumpers to the computer or memory module are required for installation.
The in-5034 memory. with alladdress and control circuitry. is contained on a single Hex-Height PC card. This memory
card requires only one modified Unibus slot.
The in-5034 is designed for low power dissipation. When operating at full speed in a PDP-11f34. or PDP-11/04. the
in-5034 dissipates 25.5 watts_ In standby. the power dissipation is 12.7 watts. The power dissipation is calculated for
worst case maximum. The in-5034. upon detection of power-fail. switches to refresh cycles only. The contents of the
memory will be retained provided that there are battery backups on +5VBB. +15VBB and -15VBB voltages.
The in-5034 provides on-board parity checking and generation. Control Status Register (CSR) is also included onboard at no extra cost. Parity check and CSR perform the equivalence of DEC's parity controller modules function for
the in-5034 memory.
22-15
in·5034
Two pre·tested memory devices plugged into sockets are
provided on board for spare. These spare memory devices
can be used to replace any failing memory devices in the
field. The failing memory devices can be pinpointed with the
aid of the address decode chart and DEC memory
diagnostic messages.
The In·5034 features maximum read and write cycle times of
600 nanoseconds alowing maximum utilization of modified
Unibus throughput.
With DEC's memory management, up to 128K words of
in·5034 memory can be added to the PDp·11 system. The
address range for each card is set by on·board DIP
switches.
Each memory card is fully tested in a temperature cycling
environment. Because of the 100% burn·in performanced
on each card, the customer is assured of receiving Intel's
provent quality and reliability. In addition, all Intel PDp·11
compatible products are covered by a one year Intel
warranty.
PRODUCT SPECIFICATIONS
DC POWER REQUIREMENTS
POWER
OPERATING
STANDBY
2 Amps
0.7 Amps
0.7 Amps
30mA
2 Amps
0.1 Amps
0.1 Amps
20mA
System Power
+5V±5%
+15V±5%*
+20V±5%**
-15V±5%
Battery Backup
Power
500mA
100mA
100mA
+5V±5%
+15V±5%*
+20V±5%**
-15V±5%
200mA
• Used if semiconductor backplane.
"Used if core memory backplane.
Temperature:
O°C to +50°C operating ambient,
-40°C to +125°C non·operating
Relative Humidity: Up to 90% with no condensation
Altitude:
0 to 10,000 feet operating. Up to
50,000 feet non·operating
.
Dimensions:
Weight:
15.4" W x 8.5" 0 x 0.375" H
Less than 3 Ibs.
Storage Capacity:
64K words per board
Word Length:
16·bits plus 2 parity bits
OTHER INTEL PDp·11 PRODUCTS
Cycle Time:
600ns
• The in·1671 provides up to 2 megabytes of add·on
memory with Error Correction Codes for PDP,11/70
users.
Read Access Time:
410ns
Write Access Time:
320ns
Modes of Operation: Read
Write
Read byte
Write byte
Address Input:
18 Lines, binary, (Single·ended)
Data Input/Output:
18 Lines, bi·directional,
(Single·ended)
Input Control:
3 lines, (Single Ended)
Output Control:
1 line, (Single Ended)
Interface:
Modified UNIBUS compatible,
1 bus load
ORDERING INFORMATION
Model
CM-5034-864
22-16
Capacity
64K x 18
Description
PDp·11/04 and PDp·11/34
Add·ln memory
in·5160
NOVA* 3 ADD·IN MEMORY
Software compatibility with NOVA 3
family
High circuit density, reducing system
cost
On-board parity control
Low power dissipation
Optional error correction with on-board
error logger and error display
Battery backup operation supported
Optional on-board memory management
and protection unit
Full commercial operating temperaturel
humidity range
64K, or 128K word capacity and
compatible with resident core memory
One year warranty
The Intel in-5160 is a 64K, or 128K word plug compatible memory card designed for use in the Data General NOVA 3
computer. It is totally hardware and software compatible with the NOVA 3, and configures easily with fesident Data
General memory boards. All in·5160 control memory, address, parity, bus driving, and voltage regulator circuitry, as
well as all options, are contained on one 15-inch x 15-inch printed circuit card, which occupies only one card slot. This
high circuit density allows a NOVA 3/4 to be configured with the maximum addressable memory, a memory manage·
ment unit, the memory protect option, and the parity generate/check option, with two slots left for a disk controller and
a serial controller or any other two cards. The in-5160 is designed for low power dissipation and uses a maximum of 50
watts (40 watts typical). In case of power failure the contents of the memory will be retained if a battery backup is pro·
vided. With this low power dissipation, no additional cooling fans are required. The parity feature and the optional
memory management and protection unit (MMPU) are functionally identical to the corresponding units available from
Data General and both features are fully compatible with the NOVA 3 software. The parity feature generates and
checks parity on a 16-bit data word and will work not only for the in-5160, but for any other 17-bit memory in the same
system. The optional MMPU allows memory addressing and allocation up to 128K words and provides several system
protect functions under software control. The optional ECC error check and correction provides error correction
facilities on the board along with an error logger. All Single bit errors will be corrected; all double bit errors and a
significant portion of multiple bit errors are detected.
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED
© INTEL CORPORATION. 1979
NOVEMBER 1979
22-17
·NOVA is a registered trademark of Data General Corporation.
in·5160
FUNCTIONAL DESCRIPTION
The in-5160 NOVA 3 Add·ln Memo~y is a semiconductor
memory system specifically designed as a single card
add·in containing the maximum amount of memory ad·
dressable by existing software. Also on the board are all
memory associated system functions previously avail·
able only on a separate card, or not available at all: parity
generation and checking, memory management, memo
ory protection, error detection/correction, and error log·
ging with error location display. All normal memory
functions are also contained on the card: address buf·
fers and decoding logic, data transceivers, control logic,
timing, mode enable logic, and refresh control logic. On·
line operating sequences are controlled by processor
supplied control signals, signals received from data
channel devices and by internal control signals.
Response signals sent to the central processing unit
(CPU) are generated by the parity logic, MMPU, and
other control logic circuitry. All system components are
engineered to meet or exceed the specifications of
similar Data General components.
Compatibility
The in-5160 can be inserted into any NOVA 3 series com·
puter and will work with any 17-bit memory already in
the system. The 96kW version must be positioned in
lower memory, Other capacities may starfon any 32kW
boundary. If the previous memory capacity is not a
multiple of 32K words, the in-5160 is set to occupy the
address range from zero up to the in-5160 card capacity.
The previously installed memory is then set to follow
the ending address of the in-5160. For example, a 64K
word in-5160 could be used as shown in Table 1.
Condition
Address Range
for In·5160
Address Range for
Resident NOVA Memory
No previous memory
0-64KW
-
16K resident memory
0-64KW
64KW-SOKW
32K resident memory
32KW-96KW
0-32KW
64K resident memory
64KW-12SKW
0-64KW
Table 1. in-5160 Memory Address Range
Capacity
The in-5160 is manufactured with two types of memory
devices: a 16K x 1-bit dynamic RAM and an 8K x 1-bit
dynamic RAM. Both chips are manufactured with NMOS
technology and are tested to the same specifications.
Addressability
Card select for the in-5160 is determined by the decode
of the three extended address inputs and the settings
of the address select switches on the card. These
switches enable the card's starting and ending ad·
dresses.to be set on any 32K word boundaries within the
128K word address field available with memory manage·
ment.. For cards with memory capacity greater than 32K
words, the address range must be selected so that the
memory occupies contiguous 32K address blocks.
----.----------------------·--------C~O~NT~R~OL~S~'G~N7.AL~S----------------·----------------,1
12SK x 22 (MAX)
STORAGE ARRAV
MEM <0-15:->, MEMP (READ AND WAITE DATA)
Figure 1. in·5160 NOVA·3 Add·ln Memory Simplified Block Diagram
22-18
in·5160
Operating Modes
Parity
The in-5160 emulates all of the operating modes supported by Data General on the NOVA 3 series computers. In normal operation, the in-5160 performs read,
read-hold, write, and read-modify-write processor controlled cycles. Refresh cycles are timed out internally
and use chip row addresses generated by a counter on
the board. The in-5160 offers the largest storage capacity th'al can be handled by existing software and has a
higher effective speed than the NOVA 3 semiconductor
memories. Read or write operations required 500 nanoseconds and the read-modify-write operation is completed in 1100 nanoseconds, whether initiated when the
memory is idle or immediately following a preceding
cycle. On consecutive memory cycles, the Data General
NOVA. 3 memory requires 500 nanoseconds for read
cycles, 1200 nanoseconds for write cycles and 2200
nanoseconds for read-modify-write. Since consecutive
memory cycles occur frequently, the Intel memory can
provide significantly faster throughput. The data valid
time is extended during the read-hold cycle by the processor pulling the hold input low. The longer data valid
time is required during defer cycles, console initiated
read cycles (the examine switch), or during data channel
read cycles. For data channel memory cycles, the
memory operates in either write or read-hold modes. All
read, write, or read-modify-write cycles can be performed with or without Single bit error correction, map,
memory protection, or parity error reset or interrupt.
The parity feature is standard on all in-5160 memory
boards. During write operations, the parity logic generates a parity bit for the 16-bit data word. Data and parity
bit are then stored in the memory. During read operations, 16 bits of data and one parity bit are read out from
the memory and checked for a pariiy error. If a parity
error is detected, the address and parity bit are latched
in the parity error address register, and either a reset or
interrupt Signal (jumper selectable) is returned to the
processor. The GPU reads the contents of the parity error address register by using standard 110 instructions.
The parity feature services not only the in-5160, but all
17-bit memories in the same system. On boards with the
EGG option, the parity logic still functions for other
17-bit memories in the system and reports multiple bit
errors detected by the EGG logic to the GPU as parity
errors.
Memory Management and Protection
Unit (MMPU)
Memory expansion - The MMPU provides the capability to use a memory of up to 128K words and supplies'
the hardware necessary to make use of the NOVA 3 sofF
ware protection features. The expansion of memory
capacity is accomplished by replaCing the 'five highest
order address ,bits (the logical address) with seven bits
from a location in the translation memory (the physical
address). Each logical address is 'mapped' (or translated) to one, and only one, physical address, which may
be anywhere within the 128K physical address field. The
contents of the translation memory (the map) may beset
up using ordinary 110 instructions.
Error Correction and Error Logger
The in-5160 error correction circuitry (EGG) provides onboard capability to correct any single bit error and
detect any double bit error in the read data. Many errors
of more than 2 bits will also be detected. EGG greatly
increases memory reliability and minimizes nonrecoverable system failures. The multiple bit errors are
flagged to the processor as parity errors. All errors are
logged as they occur and are simultaneously displayed
on the in-5160's control panel. The error correction function can be disabled by a switch on the control panel;
however, the error logger will continue to monitor and
store error information. The chip location of Single bit
errors and row location of double bit and multiple bit
errors are stored in the error logger memory and
displayed on LEDs on the control panel as they occur.
The error logger controls and indicators are shown in
Figure 2.
ERR BIT 16,8,4,2,1
SK (SEEK) -
Memory protection - The memory protection function
of the MMPU provides detection capability for five types
of software violations:
• Write protect tected 1K page
FOR ERROR INFORMATION.
prevents writing into a write pro'
CLR (CLEAR) -
PUSHBUTTON SWITCH. CLEARS ERROR LOGGING MEMORY.
INH(INHIBIT) -
TOGGLE SWITCH. IN ON POSITION INHIBITS ERROR CORRECTION
FUNCTION. DOES NOT INHIBIT ERROR LOGGER.
ROW 4.2,1.V~
protects against runaway defer cycles
THESE INDICATORS SHOW ROW lOCATION OF FAULTY RAM
(BINARY CODED).
LOG -
THIS INDICATOR COMES ON TO INDICATE ERROR LOGGING IN
ERR -
INDICATES ERROR IS DETECTED; SINGLE BIT OR DOUBLE BIT/MULTIPLE BIT
PROGRESS.
• 110 - enables 110 violation detection in the GPU
• Auto Index -
PUSHBUTTON SWITCH. WHEN PUSHED AND HELD, PERFORMS LED
TEST. WHEN RElEASED{ERROR LOGGING MEMORY IS SEARCHED
• Validity - prevents accessing, in any manner, a page
declared invalid
• Defer -
THESE INDICATORS SHOW FAULTY OATA BIT (BINARY CODED).
EXAMPLE: INDICATORS 1 AND 4 ON, INDICATES BIT 5 IN ERROR.
Prevents auto-indexing operations.
When a violation is detected, the MMPU initiates a map
interrupt routine in the processor.
Figure 2. Error Logger Control Panel and Indicators
22-19
in·5160
the 128K in-5160 dissipates 170 Btu/hr; in battery
backup (standby) mode, it dissipates 55 Btu/hr_ This
results in a cooler running system, an increased margin
for power supply operation, and improved system reliability_ Every card is fully tested in a temperature
cycling environment for eight hours and in a NOVA 3
computer to test all options with the NOVA software.
Because of the 100% burn-in performed on each card,
the. user is assured of receiving Intel's proven quality
and reliability_ In addition, all Data General compatible
products manufactued by Intel are covered by a one year
warranty.
INSTALLATION
The installation of the in-5160 on a NOVA 3 system is
covered in detail by the technical manual which accompanies the product. The ma.in points of consideration
during installation are address selection and. parity
error action (RESET or interrupt)_ The loCation of these
switches and jumpers are illustrated in the manual for
easy location_
RELIABILITY
The in-5160 is designed for low power dissipation_ When
operating with all options, and at full speed in a NOVA 3,
Memory Data Input/Output - 16 bidirectional lines
I/O Data Input/Output - 16 bidirectional lines
Control Inputs - 36 lines
Control Outputs - 14 lines
SPECIFICATIONS
Storage Capacity
64K, or 128K words
Word Length
Physical Characteristics
Standard - 16 data bits and one parity bit
With ECC - 16 data bits and six EGG check bits
Width - 15 in. (38.1 cm)
length - 15 in. (38.1 cm)
Height':" 0.4 in. (1.02 cm)
Weight - Less than 3 Ib (1.36 kg)
Cycle Time
Read or Write Cycle RMW - 1100 ns
500 ns
Electrical Characteristics
Access Time
DC Power Pequirements (128K, all options)
300 ns (access and cycle times are extended 100 ns if
error correction takes place)
Voltage
(:!:5%)
+5V
+15V
-5V
Operating Modes for Memory
Processor - Read, read-hold, write, read-modify-write
Data Channel - Read-hold, write
MMPU - Translation enabled/disabled
Parity - Disabled/generate even parity, generate odd
.
.
parity
Active
Current
Battery Backup
6.8A
890mA
5mA
2.2A
350mA
Environmental Characteristics
Temperature - 0 'G to 50'G operating ambient; -40'G
to 120 'G non-operating ambient
.
Relative Humidity -Up to 90% with no condens.ation
Interface Characteristics
Interface - NOVA-3 backplane compatible, one card
slot required
Note: If the in·5160 is equipped with MMPU option. backplane slot 2 is
required.
Address Input DS 0-5: 6 lines
MADR 1-15: 15 Lines; ALU 0-6: 7 lines;
Altitude operating
10,000 ft max operating; 50,000 ft max non-
Reference Manuals
TM-5160-000 - in-5160 Technical Manual, Number
111768 (SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative.
Address Input/Output -MADR 1-15
(Generated in MMPU) X MADR 0-2
22-20
in·5160
ORDERING INFORMATION
Model
CM·5160A·064
CM·5160A·128
CM·5160B·064
CM·5160B·128
CM·5160C·064
CM·5160C·128
CM·5160D·0364
CM·5160D·128
Capacity Description
64K
128K
64K
128K
64K
128K
64K
128K
x
x
x
x
x
x
x
x
17·bit
17·bit
22·bit
22·bit
22·bit
22·bit
22·bit
22·bit
64K memory with parity
128K memory with parity
64K memory with ECC
128K memory with parity and ECC
64K memory with parity and MMPU
128K memory with parity and MMPU
64K memory with parity, ECC and MMPU
128K memory with parity, ECC and MMPU
22-21
in-S770
VIDEO-REFRESH MEMORY SYSTEM
• Single-card memory system complete
with addressing and timing logic
• Utilizes MOS dynamic RAMs for
maximum bit density at low system
cost
• 256K-word x 4-bit capacity in four
image planes, each 256K x 1 bit wide
• Operates in both parallel- and single-bit
mode control
• Four-bit resolution, allowing 16 shades
of grey for image enhancement
• Provides automatic refresh or
externally initiated refresh
• Expandable in multiple card systems
for greater resolution in both grey scale
and multicolor displays
• High-speed 14.3 MHz bit rate in serial
read mode
The Intel in-5770 Video-Refresh Memory System is a special-purpose, single-card, random-access memory
system designed to store and retrieve digital video image data for sophisticated computer-driven CRT displays.
The storage capacity of each card is 256K (K = 1024) 4-bit words arranged in four image planes to provide the 16
grey shades necessary to ensure the high picture quality required for medical and scientific laboratory
computer modeling displays; a typical image enhancement application is the detailed analysis and interpretation of black-and-white x-ray images. Multiple in-5770 cards may be used in parallel for systems applications
requiring more than four bits per picture element for special graphic displays such as color enhancement,
overlays, or enlargements of portions of the display. The in-5770 refresh memory is specifically designed for
image enhancement applications; refresh may be accomplished either by normal read and write cycles or by
user-generated refresh cycles within the specified retention time. Each memory card contains all the logic and
timing circuitry required to generate memory addresses and clock pulses, and utilizes 16K x 1 MOS dynamic
RAM technology for maximum bit density at low system cost. An optional chassis is available for multiple card
housing.
22-22
in-5770
FUNCTIONAL DESCRIPTION
Capacity
The in-5770 is a video-refresh, random-access
memory card system designed specifically for storing and retrieving digital video image data with high
resolution, but also used for conventional storage
applications. The complete system consists of one 16
x 11.25-inch edge connector-type printed circuit
card containing the semiconductor storage area and
all the required address and data latches and control
logic needed to operate the memory. The two standard configurations are 512 x 512 using Intel's 16K x
1 dynamic MaS RAM and 512 x 256 using the 8K x 1
dynamic MaS RAM. The memory is arranged in four
planes either 16K x 16 or 8K x 16: A block diagram of
the in-5770 memory system is shown in Figure 1.
Each CM-5770 memory card has the capacity to
store a 512 x 512 display with four bits per picture
element. The two standard configurations are 512 X
512 x 4 (CM-5770-512) and 512 x 256 x 4 (CM-5770256). The memory storage area in the 512 x 512 version consists of 64 Intel 16K x 1 dynamic N-channel
MaS RAM silicon-gate memory chips. The 16,384
storage cells on each chip are arranged in a 128 x 128
array requiring seven row and seven column addresses to select one cell. Each cell holds one bit of
information. The memory chips are arranged in four
rows of 16 chips each, with each 4 x 4 block of chips
representing one 16K x 16 plane of data. The memory
, storage area in the 512 x 256 version uses 641ntel8K
CLKENBLO
~
MA020. MA03Q
_RMwa
TIMING
AND
CAS
I
I
:~~~RLELceT~ONA L
LOGIC
-,
TYPICAL OF EACH PLANE
r-------
CO~TROl
BITMODEl
[16
SETWEMODl
16
.c.::..;+----J
.....
I
I
......-- MADao, MAOTO
SINGLE
.1'N
B'T
WE
WE
tvlASK
16
--'----t---l
OUT
DATA
'N
READ
ENABLE
16
Il--I----'
16
16
GEN
ClRMQ
16
SERIAL
VIDEO
DATA
_------j
PMSKOo.PMSKJO
WRTD
I
I
L
_____________J
Figure 1. in-S770 Video Refresh Memory System Block Diagram
22-23
AFN-02113A
in-S770
x 1 dynamic N-channel MOS RAM memory chips with
8192 storage cells arranged as a 64 x 128 array. The
8K RAMs are partial 16K devices with only one half of
the array operational. The in-5770memory capacity
may be expanded using up to a maximum of 24
CM-57.70 cards per system.
1---
---16.00"
Figure 2. in-S770 Card Dimensions
Operation
The in-5770 provides both paraUel- and single-bit
mode control to perform four basic memory
operations plus the refresh operation. The card is
read in a sequential manner for CRT refreshing, with
random-access read, write, or read-modify-write
operations performed in between the CRT refresh
reads. During a CRT refresh read, 16 bits of data from
each plane are read on the memory card and are
internally converted to serial bit lines, clocked at
70-nanosecond or longer intervals.
each memory plane. The parallel write mode writes a
16-bit data word selectively in any or all of the planes,
under control of a piane selec;:t ,mask. During singlebit write operations, four bits(one pixel) are received
at the interface and stored with one bit in each
memory plane.
READ-MODIFY-WRITE OPERATION
In a read-modifycwrite operation, internal memory
timing is arranged so that read data is output .trorn
the card during thefirst portion of the cycle, followed
by a 90 ns modify perioo during which a new data
word is generated by the user and stored inthe
memory. During a parallel read-modify-write operation, a fu II 16-bit word is read and rewrittEln in each
memory plane. During a single bit read-modify-write
operation, a single-bit is read and rewritten into each
memory plane.
CLEAR OPERATION
A clear mode provides a convenient way for clearing
the screen and for generating test patterns. During a
clear mode operation, the data applied on the single~
bit input lines is written into al116 bits of the selected
address in all four memory planes.
VIDEO REFRESH OPERATION
In image enhancement applications, photographic
or video images are converted to a matrix of picture
elements with binary elements designating the in. tensity, assigned to each. This information is sent
from the computer to the refresh memory and stored
for later CRT display. Since data sent directly to a
screen from the computer quickly fades, the in-5770
continuously recreates stored graphic images as re e
quired by projecting a512 x.512 matrix of shaded
pictureelememts onto the C8.r:~9reen.
READ OPERATION
In all read modes, a full 16-bit data word is read out
from the addressed location in each memory plane.
During parallel read operations, a 16-bit data word is
read from each plane of the memory array and placed
on the output lines, 64 lines in all, resulting in 64 bits
being simultaneously available at the interface. During serial read operations, 16 bits from each memory
plane are loaded into shift registers and transferred
out serially on four output lines. During single-bit
read operations, a 16-bit word is read from each of
the four memory planes, but only one bit from each
plane is transferred to the single-bit output lines.
MEMORY REFRESH OPTIONS
All rows of memory devices within the in-5770 must
be refreshed once every 2 milliseconds to prevent
loss of data. The refresh operation takes place automatically during serial read for video refresh:
However: if normal read operations do not use all 128
chip rows within the memory, refresh cycles must be
externally initiated. Data refreshing in N-Channel
MOS RAMs is normally achieved by sequentially
scanning the memory at the rate of 128 times each 2
milliseconds.
WRITE OPERATION
In write modes, 64 bits of data are stored in the
location specified by the address inputs. During parallel write operations, 64 bits are received at the
interface, and stored as four 16-bit words, one in
INPUT/OUTPUT
All in-5770 input/output signals are compatible with
TTL integrated circuits. The input and output signal
operations for the in-5770 are summarized in Tables
2 and 3, respectively.
Interface
22-24
AFN-02113A
intel
in-5770
Table 2. in-5770 Input Signal Operations
Signal
Operation
Addresses
(0-17)
Controls address selection of
both single bit data and parallel
data on 18 bidirectional lines.
Card select
Enables memory activity on
card when low.
Memory cycle
start
Initiates memory cycle upon
going from high to low.
Bit mode
Indicates to memory, when low,
that single bit write cycle or
read-modify-write cycle is to be
performed. Enables parallel
operation when high.
Write
Initiates write operation when
held low at beginning of
memory cycle.
Read-modify-write
Initiates read operation when
held low at beginning of
memory cycle. Initiates write
operation after 90 ns delay.
Writes user supplied data into
location initially read out.
Plane select write
mask
Inhibits writing operation,
when driven low during write or
read-modify-write operation on
data within given planes, on all
data withi n that plane.
Operation
Signal
Clear mode
Initiates write operation, when
held low at beginning of cycle,
of data on single bit write data
lines into all 16 bits of addressed word.
Parallel read
enable
Enables, when low, readout of
data onto 64 bidirectional lines.
Video data load
sync
Enables, when low, parallel
loading of shift registers for
serial transfer out of video data
during serial read operations.
Video data serial
clock sync
Clocks shift registers, upon
going from low to high, for
serial transfer out of video data
during serial read operations.
Refresh mode
Initiates refresh cycle, when
held low at beginning of
memory cycle, on address location specified by internal
refresh counter.
Single bit write
data (0-3)
Transfers single bit write data
to memory on four bidirectional lines, 16 for each plane.
Parallel memory
data (0-15)
Transfers parallel data to and
from memory on 64 bidirectionallines, 16 for each pla~
Table 3. in-5770 Output Signal Operations
Reliability
Signal
Intel manufactures all the integrated circuit devices
from which all Intel memory systems are produced.
Because of this vertical integration, Intel controls the
quality of its equipment from the beginning process
of making the device through the final test and
delivery of the system, thus assuring the users of
products with proven quality and reliability. In addition all Intel memory systems products are covered
by a one year Intel warranty.
Operation
I
Data available
Indicates to processor, upon
going high at access time, that
valid read data is available on
data bus.
Single bit data
(0-3)
Transfer single bit read data out
of memory on four unidirec-
Serial video data
(0-3)
tional lines.
Transfers serial video data out
of memory on four unidirectional lines.
SPECIFICATIONS
Performance
Storage Capacity
CYCLE TIME
Read, Write, or Refresh: 450 ns max
Read~Modify-Write: 780 ns max
256K x 4 bits, addressable as 64-bit words (16 bits
per image plane), or as 4-bit words (1 bit per image
plane)
Word Length
ACCESS TIME
Parallel Data: 380 ns max
Single Bit Data: 390 ns max
16 bits on the parallel bus per image plane
1 bit on the single bit bus per image plane
1 bit on the serial data bus per image plane
RETENTION TIME
2 ms max
22-25
I
I
AFN-02113A
intel
in-S770
SERIAL DATA RATE
14.3 MHz max
CONTROL OUTPUT
Data available
Interface Signals
Operational Modes
Parallel write (16 bits)
Parallel read-modify-write (16 bits)
Single bit write
Single bit read-modify-write
Parallel read (16 bits)
Single bit read
Serial read
Clear mode write
Memory refresh'
Interface Characteristics
CONNECTOR
Two 80-pin double-sided PC edge, 0.125 in. centers,
type SAE 8100 (Stanford Applied Engineering) or
equivalent
INPUT/OUTPUT
TTL compatible (single ended)
INPUT
Low .................... ...,1.0V to +0.8V @ 2 mA
High .................. +2.2V to +5.5V @ 100 p,A
OUTPUT
Low ................... -0.5V to +0.5V @ 15inA
High .................. +2.4V to +5.2V @ 200 p,A
Physical Characteristics
CARD
Width ....................... 11.25 in. (28.58 cm)
Length ........... , ............ 16 in. (40;64 cm)
Weight ................... ; ........... 2 Ib (1 kg)
MciuntingCenters ............ 0.625 in. (1.59 cm)
Electrical Characteristics
DC POWER REQUIREMENTS
Voltage (±5%)
+12V
+5V
-5V
ADDRESS INPUT
18 binary lines
DATA INPUT
Parallel Data: 64 bidirectional lines
Single Bit Data: 4 unidirectional lines
DATA OUTPUT
Parallel Data: 64 bidirectional lines
Single Bit Data: 4 unidirectional lines
Serial Mode Data: 4.unidirectionallines
CONTROL INPUT
17 lines: memory cycle start, write, single bit mode,
read-modify-write, card select, refresh, plane select
write masks 0 through 3, clear mode, parallel read
enable 0 through 3, serial data clock, serial data .
load enable, video data load sync
Current (max)
2.5A
2.75A
100 mA
Environmental Requirements
TEMPERATURE
O°C to 55°C operating ambient
-40°C to 125°C non-operating
RELATIVE HUMIDITY
Up to 90% non-condensing
ALTITUDE
10,000 ft max, operating
40,000 ft max, non-operating
COOLING
200 linear ft per minute
ORDERING INFORMATION
Model
Capacity
Description
CM-5770-512
256K x 4
512 x 512 x 4 video refresh memory system card
22-26
AFN-02113A
MU-5750
VAX* 11/750, PDP* 11/70 ADD-IN MEMORY
• Replaces DEC* MS750AA or MS750AB
• Hardware/software compatible
• 256K or 512K byte capacity
• Supports battery backup
• On-line/off-line switch
The Intel® MU-5750 is an add-in memory board for use in the DEC' VAX' 11-750 or PDP' 11/70 computers and is
functionally equivalent to DEC's own memory board. The VAX or PDP 11/70 memory subsystem provides all of
the necessary control and timing for this memory board. No modification to the computer is necessary to use
the MU"5750. An on-line/off-line switch is provided on-board to allow memory boards to be isolated for
diagnostic purposes without being removed.
The 256KB MU-5750 is a direct replacement for one DEC M8728 memory board (MS750AA) and the 512KB
MU-5750 replaces two M8728 boards (MS750AB).Up to eight 256KB boards or up to four 512KB boards can be
used to expand the VAX 11/750 memory capacity up to a full 2M bytes. Similarly, the MU-5750 can be used to
expand the PDP 11/70 to its full capacity of 4M bytes.
·DEC, PDp, and VAX are trademarks of Digital Equipment Corporation, Maynard, Massachusetts.
The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products: i,lntel, INTEL, INTEL,LEC, MeS. 1m, ies, ICE, UPI, exp, iSBC, iSBX,
Insite, iAMX, System 2000, CREDIT. iAMXl80, MULTI BUS, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, 8/i'1d the combination of MeS.ICE, iSBC. iRMX or
ieS and a numerical suffix.
©
INTEL CORPORATION. 1981.
22 .. 27
A~~~O~~:1
MU·5750
Storage Capacity
Dimensions
256K or 512K Eight-Bit Bytes
Length ........ , ................ 8.0 in. (20.3 cm)
Height ....................... 15.69 in. (39.0 cm)
Width .................... (256KB) One Card Slot
(512KB) Two Card Slots
Word Length
32 Data Bits Plus 7 Error Check and Correction
(ECC) Bits
Environment
Speed
Access Time ...... ; ........... 285 Nanoseconds
Cycle Time .................... 350 Nanoseconds
TEMPERATURE
O°C to 50°C ..................... ; ..... Operating
-40°C to 125°C .................. NoncOperating
Operational Cycles
HUMIDITY
Up to 90% Without Condensation
Read, Write, By1e Write,lnitialize, Refresh
ALTITUDE
Up to 10,000 ft. (3,030m) .............. Operating
Up to 50,000 ft. (15,150m) ......... Non-Operating
Interface Characteristics
-TTL Compatible
-7 Chip Rowand Column Address Lines
-13 Control Lines
RELIABILITY
Electrical
Model
(KB)
Voltage
(Volts)
Standby
Current
(mA)
Operating
Current
(mA)
256
+12
+5
-5
234.00
2.60
7.80
1540.50
1.59
13.70
512
+12
+12
-5
46S:00
3.10
15.60
1774.50
3.12
25.35
Intel tests each MU-5750 at elevated voltages and
temperatures for a period proven to bring out most
latent defects in semiconductor devices. This process, together with temperature cycling, is designed
to remove all potential failures before the memory
card reaches the customer. Because of the 100%
burn-in performed on each card, the user is assured
of Intel's proven quality and reliability. This product
is covered by a one-year warranty.
ORDERING INFORMATION
Model
Capacity
Equivalent VAX 11/750
Equivalent PDP 11/70
MU-5750-256
MU-5750-512
256K eight-bit bytes
512K eight-bit bytes
MS750-AA (one M8728)
MS750-AB (two M8728)
(one M8728)
MK11-CE (two M8728)
22-28
MU-S780
VAX*-11/780 ADD-IN MEMORY CARD
• Replaces DEC* MS780·DA, DB or DC
• 256KB,512KB or 1024KB Capacity
• On·Line/Off·Line Switch
to 1, 2 or 4 DEC M8210
• Equivalent
Memory Modules
Hardware and Software
• Complete
Compatibility
• Supports Battery Back Up
The Intel® MU·5780 Add·ln Memory Card is a 256KB, 512KB or 1024KB plug·compatible memory card
designed for use in any DEC VAX·11/780 computer, to expand the MS780·C or MS780·CC basic VAX·11/780
memories up to 4096K bytes (four megabytes). The MU·5780 operates at speeds controlled by the
VAX·11/780 memory controller. Typical read cycle and access times are 530 and 250 nanoseconds respec·
tively. All card components are hardware· and software·compatible with the VAX·11/780 computer. The
MU·5780 can be installed without change or modification to either the computer or the memory module by
plugging it into the proper memory bacl(plane slot. The MU·5780 measures 39.8 cm (15.7 inches) by 31.4
cm(12.4 inches) and requires the same + 5VDC, - 5VDC, + 12VDC, and + 5VDC battery backup as the
memory card it replaces.
·VAX and DEC are registered trademarks of Digital Equipment Corporation.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: i, Intel, INTEL, INTELlEC, MeS, im. leS, ICE, UP!, BXP, iSBC, iSBX, INSITE, iRMX,
CREDIT, RMXJ80.p.Scope, Multibus. PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS, ICE, sec. RMX or iCS and a numerical
October 1981
suffix; e.g., iSeC-SO.
© Intel
Corporation 1980
22-29
AFN·01734A
MU-5780
FUNCTIONAL DESCRIPTION
block diagram of the MU-5780 memory system is
shown in Figure 1.
The MU-57BO Add-In Memory Card consists of a
single printed-circuit card designed to fit into the
memory backplane of a DEC VAX-11/780. It contains
all circuitry required for memory operation,
including address-decoding circuits, memorycontrol circuits, and a memory storage area. Allsystem components are engineered to meet or exceed
the specifications of similar DEC components. A
;--
Compatibility
The MU-S780 can be operated with or in place of the
DEC Model M8210 Semiconductor Array. It must be
used in conjunction with the DEC M8213 Memory
Controller, the M8212 Memory Data Path, and the
M8214 Memory SBllnterface Boards.
WOE
Ol
a:
ROE
w
BUS MOS DATA
& CHECK BITS
>
c
a:
~~
I
ffi2:
DATA
v
w
[;l
a:
)
c'
MEMORY
ARRAY
'--:-;--
I
ARY ADR 1-6
>
=>
MUXCNTL
ARY ADR 7-12
cs
":I!
~
a:
ffl
> ~
-
READ
Ol
""
256KB/512KBI1024KB
(72.144 OR 288
2121 MEMORY
DEVICES)
)(
Ol
a:
ARY ADR EXT
I
r----
c
c
'-~
r-r/'
I
SLOT CODE LS8- L88 + 3
:;;
Figure 1. MU-5780 Block Diagram
22-30
AFN.o1734B
intel'
MU-S7BO
Capacity
INSTALLATION
The MU-5780 is available in three configurations,
256K bytes (MU-5780-256), 512 bytes (MU-5780-512)
or 102.4K bytes (MU-5780-1 MB). The configurations
are organized as 32K x 72 bits, 64K x 72 bits or
128K x 72 bits. Each word contains 64 data bits
and 8 check bits. The memory storage area consists of either 72, 144, or 288, Intel 2121, 32K x 1
dynamic memory IC's.
The Intel'!') MU-5780 memory cards are installed in
Slots 3 through 17 of the DEC MS-780 Memory
System Backplane. Since some MU-5780s 'have a
higher capacity than the DEC boards they replace,
all memory slots may not be used in the MU-5780
application. With the MU-5780 512 version, the
first card is installed in the first vacant memory
slot (17 or lower), and in every alternate slot. With
the MU-5780 1MB version, the first card is installed in the first vacant slot (17 or lower) and then in
every fourth slot. Intel-supplied continuity boards
must be installed in the empty slots between
these MU-5780s. Continuity boards simulate the
memory cards which would normally be installed
in the slots and also direct air flow over the
memory cards.
Addressability
The MU-5780 memory address circuitry consists of
19 address inputs plus four slot-code bits supplied
to the memory by the VAX computer. The four slotcode bits are subtracted from the last four address
bits (AAY ADA 16, 17, 18, and 19). Each subtraction
selects a 256KB memory segment of the MU-5780
installed in the addressed slot.
Reliability
An on-board multiplexer, under control of the MUX
CNTAl command, applies seven address bits as row
addresses, which select one of 128 rows on the
memory modules, and seven column addresses,
which select one of 128 columns on the memory
modules. One address bit, 13, selects the memory
bank. Figure 2 shows the address configuration.
Each MU-5780 is fully tested in a temperaturecycling environment. Because of the 100% burn-in
performed on each card, the user is assured of
receiving Intel's proven quality and reliability. In
addition, the MU-5780 is covered by a one-year Intel
warranty.
SELECTS 1 OF 128 COLUMNS ON THE
MEMORY MODULE
SELECTS 1 OF 128 ROWS ON THE
MEMORY MODULE
SELECTS EITHER BANK 0 OR BANK 1 OF
THE MEMORY ARRAY
57.CHloe
PROVIDES 16 MEMORY CARD ADDRESSES
EACH CARD ADDRESS SELECTS 256KB OF MEMORY
Figure 2_ MU-S780 Address Configuration
22-31
AFN'()1734B
intel'
MU-S780
Interface Characteristics
SPECIFICATIONS
Address Lines:
Data Inputs/Outputs: 72 bidirectional lines (64
data lines, 8 ch~ck bit line~)
Storage Capacity
Control Inputs:
256KB .......................... MU·5780·256
512KB ................... , ...... MU·5780·512
1024KB ........................ MU·5780·1 MB
Seven lines low-power
Schottky
.
Power Requirement: +5VDC, -5VDC, +12VDC,
+5VDC battery backup
Word Length
Physical Characteristics
64 data bits plus 8 check bits
Width .................... 39.8 cm (15.7 inches)
Height, .. " .............. 31.4 cm (12.4 inches)
Thickness .........•. '" , ......... One card slot
Weight ..........• ;.......... 2.05 kilos (4.5 Ibs.)
Performance (Cycle Times-Maximum)
Read .......................... 600
Write .......................... 600
Initialize ....................... 600
Refresh ........................ 600
Environmental Characteristics
nanoseconds
nanoseconds
nanoseconds
nanoseconds
TemperatLire:
(Times shown are for the VAX memory controller.
MU-5780 performance is 530 nanoseconds cycle
time and 250 nanoseconds access time.)
Initialize
Refresh
. O°C to 50", operating ambient
-'40·C to +125°C, nonoperating
Relative Humidity:
Up t090o/ciWithout
condensation
Altitude:
3,030 meters (10,000 tt)
maximum, operating
15,151 meters (50,000 tt) .
maximum, non-operating'
Operational Modes
Read
Write
23 lines, including four slot
code lines
Reference Manuals
MU-S7BOAdd-ln Memory Card (supplied),
112388
Reference manuals are shipped with each product
only if designated (see above). Manuals may be
ordered from any Intel sales representative.
Refresh Rate
14 microseconds
ORDERING INFORMATION
Part Number Capacity
MU·5780·256
MU·5780·512
MU·5780·1MB
Description
256K Bytes 256KB, 32K x 72
512K Bytes 512KB, 64K x 72
1024K Bytes 1024KB, 128K x 72
22-32
iSBC 254™
BUBBLE MEMORY BOARD
• 128K Byte to 512K Byte Capacity on
Single iSBCTM Board
• 48MS Average Access Time
• Low Power Consumption
35 Watts for 512 KB Version
• Non-Volatile Storage
• Multiple I/O Modes, Including DMA
• Driver Software for Operation with
RMX 80/86
The iSBC 254™ is a non-volatile memory utilizing the Intel 7110 one-megabit bubble memory element. The
board is offered in three capacities: 128K, 256K, or 512K bytes.
The iSBC 254 can be operated in three 110 modes: polled status, interrupt-driven, or DMA. The 128K byte version can operate at a maximum transfer rate of 12.5K bytes per second. The multiple bubble elements of the
256K byte and 512K byte versions can be accessed in parallel to achieve maximum transfer rates of 25K and
50K bytes per second, respectively.
The physical outline of the iSBC 254 is the standard 12 inch by 6.75 inch iSBC card format. The depth of the
board, however, is 0.62 inches, requiring two normally spaced card slots for adequate mechanical clearance.
Power requirements for the iSBC 254 are 4 Amps at +5 volts and 1.2 Amps at + 12 volts, maximum.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: i. Intel. INTEl,INTELLEC, MCS. 1m, leS, ICE, UP" exp, iSBe, ISeX, INSITe, IAMX,
CREDIT, RMX/BO,JLScope, Multibus, PROMPT, Promware. Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS. ICE,SSC. AMXoriCSand a numerical
suffix; e.g., iSBC-80.
© Intel
Corporation 1980
22-33
A~17_
iSBC 254™ BOARD
OPERATIONAL DESCRIPTION
Three distinct modes of operation relate to the transfer of data. Each is briefly described below.
Data Transfer
In DMA (Direct Memory Access) Mode, the iSBC 254
board utilizes the Intel 8257 DMA Controller, in conjunction with the 7220 Bubble Memory Controller, to
perform three distinct types of DMA operation: DMA
Read, DMA Write, and DMA Verify. In a DMA Read
operation, data is transferred from memory to the
FIFO (first-in/first-out RAM) of the 7220 BMC(Bubble
Memory Controller). In a DMA Write operation, data is
transferred from the 7220 BMC FIFO to memory. In a
DMA Verify operation, the iSBC 254 board gains control of the bus, but no actual transfer of data takes
place. DMA Read and DMA Write operations are used
for high-speed data transfers involving busaccessible memory; DMA Verify operations are
typically used to maintain control of the system bus
while verification tasks, suCh as checking newly acquired data, are being performed.
In Polled Mode, the CPU periodically checks the
Status Register of the 7220 BMC. The Status Register can indicate a variety of conditions, one of which
is that the BMC FIFO is ready to receive data or that
the FIFO contains data to be read.
In ORO (Data Request) Mode, when the FIFO of the
7220 BMC is half empty (during a write operation) or
half full (during a read operation), the ORO pin
becomes active and an interrupt is issued, signalling
that data may be written (bus to iSBC 254 board) or
read (iSBC 254 board to bus).
Two distinct modes of operation relate to monitori ng
the bubble memory board status (via the 7220
Bubble Memory Controller). Each is briefly described
below.
Status Monitoring Modes
In Interrupt Mode, a change in the 7220 BMC Status
Register will cause an interrupt to occur, and the host
processor will then look at that register to see what
change has occurred. Any of the following may be
indicated: the BMC sequencer is busy; an operation
has been completed; an operation has failed; a
timing error has ()ccurred; and/or a correctable, uncorrectable, or parity error has occurred.
In Polled Mode, as described above under Data
Transfer, the CPU periodically checks the Status.Register of the 7220 BMC. The Status Register canilldicate a variety of conditions: that the BMC Sequencer
is busy; that an operation is complete; that an operation has failed; that a timingerror has occurred; that·
a correctable, uncorrectable, or parity error has occurred; or, in terms of data transfer, that the BMC
FIFO is ready to receive data or that the FIFO contains data to be read.
SOFTWARE DESCRIPTION.
The iSBC 254.boardcan run under either the
iRMXl80 or the iRMXl86 operating system.
Under the iRMXl80 operating system, the Bubble
Manager (BMGR), software task that runs with the
iRMXl80 operating system, keeps track of free or
available space •on the Magnetic Bubble Memory.
Another task, Bubble I/O (BUBIO), controls all iSBC
254 board operations. Bubble I/O can run with or
without the Bubble Manager.
a
Under the iRMXl86 operating system, the iSBC 254
board is supported as an integral part of the I/O
system software, which is part of the iRMXl86 operating system. (The iRMXl86 operating system device
driver for the iSBC 254 board is linked with the I/O
system software, whichis in turn linked with the
iRMXJ86 .operating system.) Because the iRMXl86
operating system provides convenient codes for performing operations, because all devices "look" the
same when running under this operating system,
and because ofa variety of built-in features, the the
iRMXl86 operating system provides great flexibility.
Software programs on both single- and doubledensity diskettes are provided with the iSBC 254
board. EX-254 is a set of programs that
demonstrates how to use.the various iSBC 254 board
software commands.
22-34
AFN-01735B
inter
iSBC 254™ BOARD
7220
BUBBLE MEMORY
CONTROLLER
-
EXPANSION
INTERFACE
1
MULTIBUS'" SYSTEM
~
Figure 1. iSSC 254™ Board, Siock Diagram
SPECIFICATIONS
Connector
Memory Size
128K, 256K, or 512K bytes
86-pin double-sided PC edge connector with 0.40 cm
(0.156 in.) contact centers.
Mating Connector: Control Data VFB01 E43DOA 1 or
Viking 2VH43/1ANE5.
Interface
Physical Characteristics
All address, data, arid control signals are TTLcompatible and Intel MULTIBUS system compatible.
Length: 30.48 cm (12 in.)
Height: 17.15 cm (6.75 in.)
Depth: 1.57 cm (0.62 in.)
Nole: Because of its depth, the iSBC 254 board requires
Electrical Characteristics
D.C. Power
+5 volts D.C. ±5%, 3.0A (max.)
+ 12 volts D.C. ±5%, 1.4A (max.)
two card slots.
Environment
Board Operating Temperature: 0-55°C
Equipment Supplied
Performance
Rotating Field Rate: 50KHz
Maximum Data Rate: 50K bytes/second
Average Access Time: 48ms
iSBC 254 Bubble Memory Board
iSBC 254 Operation Manual
iSBC 254 Software (single- and double-density
diskettes)
22-35
AFN'()1735B
iPAB
PLUG-A-BUBBLE™
MEMORY SYSTEM
• Removable bubble memory cassette
• Average access time of 48 ms
• 128K bytes storage capacity per
cassette
• Burst data rate of 12.5K bytes per
second
• Ruggedized cassettes
• Designed to support DMA
• Optional interface to iSBX™
multi module bus
• Operates from standard +5Vand +12V
power supplies
• Automatic error correction
• Low power consumption
• Non-volatile storage
• Accommodates up to sixteen holders
and cassettes
• Powerfail data protection
• Write protection
The Plug-A-Bubble™ system (iPAB) is a bubble memory system designed for easy removal and replacement of
media (bubble memory cassettes), similar to the removal and replacement of media (magnetic discs) in disc
systems.
The "media" of the iPAB system is a sturdy protective casing that contains a one-megabit bubble
memory, support components, three LEOs, and discrete capacitors and resistors. The protective casing is
designed to protect these devices from dust, shock, and other elements of an adverse environment.
For users of single-board computers with the iSBX bus, an iSBX Multimodule interface card (MMI/O card) is
available for generating the required signals for the cassette holder.
iPAB is a bubble memory system and is therefore non-volatile memory. Like disc systems, the iPAB system has
write protection (a switch on the cartridge holder-provides this); it also has powerfail protection.
Below is a photo of the components that can make up an iPAB system. The photo shows: top left, standard cable
(iPAB 0362); top cente;, chassis (iPAB 525); top rigtit (slightly lower), holder and cassette (iPAB 381); bottom
left, Multimodule interface (MMI/O) card (iPAB 258); bottom right, cassette (iPAB 128). (For various configurations of an iPAB system, see Figure 1.)
22-36
iPAB MEMORY SYSTEM
GENERAL DESCRIPTION
A Plug-A-Bubble™ iPAB system may be configured
in various ways, depending on a user's needs, but
common to every iPAB system is at least one iPAB
cassette and one iPAB holder (iPAB 381).
An iPAB cassette consists of a PC board with a onemegabit bubble memory device, support components including a controller, three LEDs, a number of
discrete resistors and capacitors, and a protective
casing that encloses the PC board and protects it
from dust, shock, and other elements of an
adverse environment.
An iPAB cassette holder "holds" a cassette (a holder
and a cassette are mated via a plug on the holder and
a jack on the cassette); it also contains a jack for the
required external signals to/from the holder. The
holder provides logic for selection of the cassette,
bidirectional circuitry for gating of data, and write
protection logic.
Variable components of an iPAB system are the
standard data cable, (iPAB 0362), an MMI/O card
(iPAB 258), a chassis (iPAB 525). (See Figure 1 for
various user and iPAB system configurations.)
the required signals for the iPAB cassette holder(s).
Note that a holder has manual switch setting and
address lines that allow the user to select anyone of
sixteen different holders, so that with sufficient
power a single iPAB system without an MMI/O card
may support up to sixteen holders and cassettes.
The iPAB chassis houses two iPAB holders. Its dimensions are 5.75 x 3.25 x 8.0 inches, so that it
occupies the same space as a 5.25-inch floppy disc
drive.
COMMUNICATION
Communication with individual iPAB cassettes is accomplished via reading/writing two I/O ports in the
7220-1 Bubble Memory Controller (BMC). (The 72201 BMC is one of the bubble memory support components contained in the iPAB cassette.) These two
ports allow access to a variety of registers in the
7220-1 BMC, so that commands may be issued,
status may be read, and a variety of parameters relating to bubble memory operation may be set.
MODES OF OPERATION
The standard cable is shielded and 36 inches long. It
comes with four connectors: Two are for connecting
holders; one is for connecting the cable to an MMI/O
card, if an MMI/O card is used, or to a user-supplied
device that generates the required holder signals, if
an MMI/O card is not used; and one is for connecting
the end of the cable to a terminator card in the last
holder.
The MMilO card is an iSBX Multimodule interface
card available for users with single-board computers
with the iSBX bus. The function of this card is to
generate, under control of the user's system, the
required signals for the iPAB cassette holder(s).
Without external power, a single MMI/O card can
support two holders and cassettes; with external
power, up to eight holders and cassettes can be
supported. The MMI/O card contains: latches for the
address lines that are used for iPAB cassette selection; data gating circuitry; parity generating circuitry; MMI/O status logic; circuitry for generating a
wait signal for a DMA controller (not contained in the
iPAB system) or the CPU; circuitry for generating the
iPAB clock; and jumpers for selecting a variety of
options. The MMI/O card comes with the standard
cable described above.
If the MMI/O card is not used, the user must generate
There are three possible modes of operating: Interrupt Mode, Polled Mode, and DMA (Direct Memory
Access) Mode. Interrupt Mode and Polled Mode are
used both for data transfers and for monitoring
status; DMA Mode, which requires some additional
circuitry to implement, is used for data transfers only.
In terms of data transfers, Interrupt Mode is implemented by connecting the Data Request line to a
host interrupt line, the Data Request line indicating,
when active, that the FIFO of the 7220-1 Bubble·
Memory Controller is half empty (during a write operation) or half full (during a read operation), and
hence that service is required by the host processor.
(The 7220-1 BMC FIFO is a First-In/First-Out register
used as a data buffer between host and bubble
memory.) In Polled Mode, the host processor periodically checks the status register of the 7220-1 BMC to
determine whether service is required. With some
additional circuitry, a third mode, DMA Mode, is possible. (The 7220-1 BMC has DMA handshaking capability for DMA transfers, but to implement this mode a
user-supplied DMA controller is necessary.)
In terms of monitoring cassette status, Interrupt
Mode is implemented by connecting the 7220-1 BMC
Interrupt (INT) line to a host interrupt line and setting
22-37
AFN-01903B
iPAB MEMORY SYSTEM
USER CONFIGURATIONS
I.
.
7'"
OPTIONAL
.. orr
'PAR
INTERFACE
0'
",
CARD
!i
,TO@.@.OR@
CABLE
AS SHOWN BELOW
CAOD
II.
USER
INTERFACE
ANY
CPU
TO@.@,OR@
TO
iPAB
SYSTEM
AS SHOWN BELOW
GENERATES
SAME SIGNALS
ASMMIIO
iPABSYSTEM
, - - - - - - ----------...,.,
:®
I
CAB"
I
f------,/
/
C~~:IS
-=
(IPA8525)
~:~~S
L _____
~
_________
I
I
I
I
I
I
~~
r-----------------~
I
I
tj)\
\!lj
I
CONNECTOR
FOR 2ND
I
(OPTIONAL)
HOLDER/CASSETTE
I
I
I
I
I
I
I
I
I
IPA8381
I
L ______ ~ ____________ J
r-->-- ------ -- --- - ---- -- ----l
I
I
@
~5~If~g~D~~~:~~:M~~~~~UlRES
WITH
CUSTOMER SUPPLIED CABLE AND ADDITIONAL POWER.
>
I
I
I
I
I
I
I
POWER
I
I
ADDITIONAL POWER
(USER SUPPUEDI
I
L ____ _
-----------------~
Figure 1. User iPAB Configurations/Options
22-38
AFN·01903B
iPAB MEMORY SYSTEM
MOO 7
•
8
8
MOO 7
MeSOI, MCS11
•
•
TO
MINTHO
Isax
lORDI, IOWAI
FROM
IS8X;
BUS
(V'A
BASE
BOARD)
BUS
(VIA
MINTR1
BASE
BOARD)
MAO·2
MMIIO
CARD
CIRCUITRY
(OPTIONAL)
3
MDACK/
MORDT
MWAITI
REseT
OPTO,I
BCFGlI.
BCFG21,
WPYIOLl,
LAMI
THE SE (271 LINES
FLAT
~:iL~ ----. BINT~!,
PABCLK,
SELD-3.
•I
/ 8
BDO-7,
10V BROI.
awn/.
PAR
BOROI.
AST/,
aWAIT/,
LOPTI
BOACKI, AD
•
ro-
TERMINATION
CARD
(LAST HOLDER
ONLY)
.7
17
WRITE
PROTECT
SWITCH
iPAS HOLDER
(1 OF UPTO
CAR'8~~~~mTRY
N HOLDERS)"
eLK.
ADI.WAf
aSWAPENl,
QBOOTSWAPENI,
SWAPEN!,
BASIC
BOOTSWAPENI.
~:~:
'PAS
SYSTEM
l!
/5
II
9 00-8
11
LWP/.
CS1/,
PWRFAIU.
WAIT/
OACKI.
AO
BUSY
Vee
LOPTI'~
WRITE
PROTECT
LEO
(10FUPTO
N CASSETTES)"
~
iPAS
CASSEnE
CIRCUITRY
~
USE LED
o.
'Currently N 2. Wilh lulure design chang ••, the value
N may be Increased (up 10 N
For ease ot presenlallon. only one IPAS basic system Is shown.
8).
Figure 2. IPAB System Overall Block Diagram (with optional MMI/O card)
22-39
AFN·01903B
iPAB MEMORY SYSTEM
various bits in the enable register (Enable lCD,
Enable RCD, and/or Interrupt Enable (Error) for error
interrupts; Interrupt Enable (Normal) for an interrupt
to occur at the completion of a task). Then either (or
both) the completion of a task or the occurrence of
an error will result in an interrupt. In Polled Mode, the'
host processor periodically reads the 7220-1 BMC
status register to determine if an operation has been
completed or if an error has occurred.
For users with the iRMX/86 or iRMX/88 operating
systems, who wish to perform data transfers in
DMA Mode, iPAB software drivers are available as
part of those operating systems.
For users who want to write their own drivers,
detailed instructions are provided in the iPAB
technical manual (Part Number 112583) on how to
program the registers for desired bubble memory
operation, and technical support is available from
the Intel Application group.
SOFTWARE
Actual control of bubble memory operation is accomplished via reading or writing various registers
in the 7220-1 Bubble Memory Controller as
described above. But for most users it is convenient
to talk to bubble memory in a higher-level language
-or via a software "driver" that translates the
higher-level language into the language of the
bubble memory.
For users wi.th Intel Microcomputer Development
Systems, a Bubble Demo package is available on
floppy disc, allowing users to read data from, and
write data to, the bubble system; test its operation;
read the bubble's bootloop; and test the iPAB's write
protection switch.
----------------------------------------------------------------------------------
SPECIFICATIONS
Power Requirements
Capacity per Cassette ............... 128K bytes
Page Length ........... 68 bytes-ECC disabled;
64 bytes-ECC enabled
Number of Pages ......................... 2,048
Rotating Field Rate ..................... 50 kHz
Date Rate .......... 12.5K bytes/sec. (burst rate)
Average Access Time ..................... 48 ms
Current
Voltage
Holder
Cassette
VCC +5V ± 5%
280 ma
290 ma
VDD +12V ± 5%
N/A
400 ma
Total Power Consumption
PDM = 7.65W (Maximum)
PDT = 5.1W (Typical)
Environmental Specifications
~.
Environmental Parameter
Specification
Operating Temperature
o to 55"C
I---'-
Non·Operating Temperature (with Data Retention)
-40 to +100"C
Humidity (Without Condensation)
o to 95% FRH
--
Shock
30g over 11 ms with V2 sinewave shape
Vibration
5 Hz to 15 Hz @ .50 inches double-amplitude
displacement (.65g to 6g); 15 Hz to 2000 Hz@ 5g (.42 to
.000025 inches double-amplitude displacement)
Insertion Cycles
2000
22-40
AFN-01903B
in1:e1'
iPAB MEMORY SYSTEM
ORDER INFORMATION
Part Number
Description
iPAB381
Cassette holder (7.75" x 3.8" x 1") and one 128K byte cassette (6.1" x 3.6" x .81").
(Note: When fully inserted in the holder, the cassette extends 2.5" from the end of
the holder into which it is inserted.)
iPAB 128
128K-byte bubble memory cassette.
iPAB 258
iSBX Multimodule interface card (MMI/O card). This comes with shielded 36" cable
with connectors for two cassette holders.
iPAB 525
This is a 5.75" x 3.25" x 8.0" chassis housing two iPAB cassette holders. It
occupies the same space as does a 5.25" floppy disc drive.
iPAB 0362
Shielded 36'; cable with connectors for two cassette holders.
Software
iRMX™/86 iPAB Driver
Comes with iRMX/86 software.
iRMX/88 iPAB Driver
Comes with iRMX/88 software.
Bubble Demo
This is also available from MSO Intel upon request (Order No. 113073-001).
22-41
inter
iSBX 251™
MAGNETIC BUBBLE
MULTIMODULETM BOARD
• iSBX™ bus compatible
• Capacity: 128K bytes
Performance:
• -average
access time: 48ms
-burst data rate: 12.5K bytes/sec
•. DMA compatibility
Non-volatile storage
• Automatic error correction
from standard +5V and +12V
• Operates
power supplies
Software compatibility with iRMXTM
• Operating
System
Power
fail
data
protection
•
• Low power consumption
The Intel iSBX 251 magnetic bubble MULTIMODULE board is a completely assembled and tested non-volatile
memory based on the Intel 7110 one-megabit bubble memory. This board plugs into any Intel iSBC Single
Board Computer equipped with an iSBX connector, providing immediate, high density storage. This arrangement frees the MUL TIBUS for other traffic while the host iSBC board accesses the bubble memory.
Support circuitry provides the user with a simple interface to the bubble memory. For instance, sixteen
commands are available to transfer data and to view the operational status of the iSBX 251 board. Additionally,
memory reliability is increased if the automatic Error Check and Correction (ECC) feature of the support
circuitry is selected.
The iSBX 251 board can be wired to transfer data in one of three modes: polled access, interrupt driven, and
Direct Memory Access (DMA). The user may also select polled or interrupt driven access to the 7220-1 Status
Register. Thus, the user can tailor the type of access to the individual application.
The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products: i, Intel, INTEL, INTEL,LEG, MeS, 1m. leS, ICE, UPI. exp, isec, ,sex,
Inslte, iRMX, System 2000, CREDIT, IRMXJ80, MULTI BUS, PROMPT, Promware, Megschassis, Library Manager, MAIN MULTI MODULE, and thecombioationof MeS, ICE, iSeC, iRMX or
ieS and a numerical suffix. © INTEL CORPORATION. 1981.
AUGUST 1981
AFN'()2016A
22-42
SPECIFICATIONS
Interface Requirements
-TTL compatible
-iSBX 251 male connector plugs into 36-pin or
44-pin host female connector
-Connector located per Intel iSBX Bus
Specification (order number 142686) double
wide form factor
Storage Capacity
-128K Eight-Bit Bytes
-2048 Pages
-Page Length:
64 bytes with ECC
68 bytes without ECC
Physical Characteristics
Operational Modes
Width ......................... 7.24 cm (2.85 in.)
Length ....................... 19.05 cm (7.50 in.)
Height ....................... 2.53 cm (0.996 in.)
Weight ...................... 362.9 gm (12.8 oz.)
Polled, Interrupt Driven, or DMA (with Host DMA
Controller)
Electrical Requirements
Environment
D.C. power, supplied through iSBX connector:
+5V ±5%,365 mA (max.)
+12V ±5%,400 mA (max.)
Temperature:
O°C to 60°C (32°F to 140°F) ............ Operating
-40°C to 100°C (-40°F to 212°F) .. Non-Operating
with Data Retention
Performance
Rotating Field Rate ...................... 50 KHZ
Maximum Data Rate .............. 12.5K byte/sec
Average Access Time ..................... 48 ms
Relative Humidity:
0% to 95% without condensation
RELIABILITY
Intel tests each iSBX 251 board at elevated voltages and temperatures for a period proven to bring out most
latent defects. This process, together with temperature cycling, is designed to remove all potential failures
before the memory board reaches the customer. Because of the 100% burn-in performed on each board, the
user is assured of Intel's proven quality and reliability.
r------------------------l
I
I
I
I
I
I
I
7110
BUBBLE
HOST Isac BOARD
(WITH OPTIONAL DMA CONTROLLER)
MEMORY
CHIP
Figure 1_ Block Diagram
22-43
Insite™ User's Program
Library
23
intel
INSITE™
PROGRAM LIBRARY
• Diskettes, Paper Tapes, and Listings
Available for Library Programs
• Program Library Catalog Offering
Hundreds of Programs
• Updates of New Programs Sent During
Subscription Period
• Programs for 8008, 8048, 8080, 8088
and 8086 Processors
• Accepted Program Submittals Entitle
You to a Free Membership or Free
Program Package
Insite, Intel's Software Index and Technology Exchange Library, is a collection of programs, subroutines,
procedures, and macros written by users of Intel's microcomputers, single-board computers, and Intellec
development systems. Thanks to customer contributions to Insite, Intel is able to make these programs
available to all users of Intel microcomputers who are Library members. By taking advantage of the availability of these general-purpose routines, the microcomputer design engineer and programmer can save
many hours of programming and debugging time. The library of programs also serves as a good learning
tool for those unfamiliar with Intel assembly language or the high-level languages for Intel's family of
microcomputers.
Membership. Membership in Insite is available on an annual basis. Intel customers may become members
through an accepted program contribution or membership fee. New members should use the membership
form below.
Program Sabmittals. The Insite Library is built on user submittals. Customers are encouraged to submit
their programs. (Details and forms are available through the Insite Library.) For each accepted program,
submittors will receive a choice of three free regular priced programs on diskette, three paper tapes, or a free
membership with Insite.
Program Library Service. PAPER TAPES, DISKETTES OR SOURCE LISTINGS are available for every
program in Insite. Diskettes are available on single or double density. Membership is required to purchase
programs.
Insite ™ Program Library Catalog. Each member will be sent the Program Library Catalog consisting
of an abstract for each program indicating the function of the routine, required hardware and software, and
memory requirements.
Insite members will be updated with abstracts of new programs submitted to the Library during the subscription period. For catalog and yearly subscription fee please refer to the Intel OEM Price List or contact the
nearest Intel Sales Office.
The following are trademarks of Intel Corporation and may be used only to identify Intel products: Inslte, Intel, Intel, Intel!ec. ©Inlel Corporation 1981
insite™
PROGRAM LIBRARY MEMBERSHIP FORM
I am interested in becoming a member of Insite™
Enclosed is
0 Check or Money Order 0 Program Submittal
0 Purchase Order (Inside U.S. only)
NAME: ___________________
COMPANY:
TELEPHONE:
SHIP TO:
SEND TO NEAREST LOCATION:
North America: Intel Corporation, Insite Program Library MS 6-5000, Microcomputer Systems, 3065 Bowers, Santa Clara, California 95051, Ph.
408·987.s080
Europe: Intel International Corp. S.A., Insite Program Library, Rue du Moulin a Papier 51, Boite 1, 8-1160 Brussels, Belgium, Ph. 02-660-3010
Orient: Inlel Japan K.K .• Insile Program library. Flowerhill·Shinmachi, Easl Bldg .. 1·23·9 Shinmachi, Selagaya-ku, Tokyo 154. Japan, Ph. 813-426-9261
(PME & FSE). 813-426-9267 (CS & Fin.)
23-1
AFN-02045A
INSITE PROGRAM
SUBMITTAL REQUIREMENTS
-8080/8085 Assembly Language Programming
Manual, Stock Number 401100
.:....8086 Assembly Language Reference Manual,
Stock Number 402105
~BASIC-80 Reference Manual, Stock Number
400710
-ICIS-COBOL Language Reference Manual,.
Stock Number 409115
-Fortran-80 Programming Manual, Stock
Number 400625
-PUM-80 Programming· Manual, Stock Number 401700
-PUM-86 Programming Manual, Stock Number 402325
-Intellec Series
III Microcomputer
Development System Programmer's Reference Manual, Stock Number 404440
-PASCAL-80 Language Reference Manual,
Stock Number 400660
Submittal Requirements
Programs submitted for Insite review must follow the
guidelines below:
A. Programs must support Intel products
B. Program submittals must be packaged to include:
-Complete submittal form
-Source listing (the output of a compilation/assembly)
-Well-documented source code and executable
code furnished on ISIS-formatted diskette or
ASCII-coded paper tape
-Detailed instructions (step-by-step from
source code compilation/assembly through
program execution)
-Test program demonstrating accurate operation and output
C. Programs must be written in a language capable
of compilation/assembly by the currently supported version of an Intel standard compiler/ assembler. Acceptable languages are
documented in the following manuals (available
through Intel's Literature Department):
-MCS-48/UPI-41 Assembly Language Manual,
Stock Number 305000
Submittal Acknowledgement
Program acceptance/rejection will be acknowledged
through correspondence. Programs accepted by Insite
become the property of the Insite Library. Programs
rejected by Insite will be returned to the submittor with
an explanation for the rejection.
23-2
__IN_T_E_L®_R_U_SE_R_'__
S L_IB_R_A_R_Y_S_U_B_M_IT_T._A_L_FO
__
RM_
insi~M
o
(use additional sheets if necessary)
8008 0 8048 0 8080/8085 0 Other
Program
Title
Function
Required
Hardware
Required
Software
Input
Parameters
Output
Results
Registers Modified:
Programmer:
RAM Required:
Company:
ROM Required:
Address:
Maximum Subroutine Nesting Level:
City:
Assembler/Compiler Used:
State:
© Intel Corporation, 1978.
23-3
98-034E
Software Distribution
Operation
24
DIGITAL RESEARCH INC.
CP/M* 2.2 OPERATING SYSTEM
• High-performance, single-console
operating system
• General-purpose subroutines and
table-driven data-access algorithms
provide a truly universal data
management system
• Simple, reliable file system matched to
microcomputer resources
• Upward compatibility from all previous
versions
• Table-driven architecture allows field
reconfiguration to match a wide variety
of disk capacities and needs
• More than 500 commercially available
compatible software products
• Extensive documentation covers all
.facts of CP/M applications
CP/M 2.2 is a monitor control program for microcomputer system and application development using the Intel
SOSO/SOSS-based microcomputer with IBM-compatible flexible disks for backup storage (see the CP/M-86*
Operating System data sheet for information on CP/M for Intel SOS6/S0SS-based systems). CP/M provides a
general environment for program construction, storage, and editing, along with the program assembly and
check-out facilities.
The CP/M monitor provides rapid access to programs through a comprehensive file management package. The
file subsystem supports a named file structure, allowing dynamic allocation of file space as well as sequential
and random file access. Using this file system, a large number of distinct programs can be stored in both
source- and machine-executable form.
CP/M also supports a powerful'context editor, Intel-compatible assembler, and debugger subsystems. Optional
software includes a powerful Intel-compatible macro assembler, and a symbolic debugger, along with various
high-level languages.
FEATURES
CP/M is logically divided into four distinct modules:
-Uses less than 4K Of memory
810S-8asic I/O System
-Makes programs transportable from system to
system
-Entry points include the following primitive
operations which can be programmatically
accessed:
-Provides primitive operations for access to disk
drives and interface to standard peripherals
(teletype, CRT, paper tape reader/punch, and userdefined peripherals)
SEARCH
-Allows user. modification for tailoring to a particular hardware envi ron ment
BOOS-Basic Disk Operating System
-Provides disk management for one to sixteen disk
drives containing independent file directories
-Implements disk allocation strategies for fully
dynamic file construction and minimization of
head movement across the disk
24-1
Look for a particular disk file by
name
OPEN
Open a file for further operations
CLOSE
Close a file after processing
RENAME
Change the name of a particular file
READ
Read a record from a particular file
WRITE
Write a record to a particular file
SELECT
Select a particular disk drive for
further operations
DIGITAL RESEARCH, INC.
CP/M 2.2
CCP-Console Command Processor
ASM
-Provides primary user interface byreading and
interpreting commands entered through the
console
Fast 8080 Assembler-uses standard
Intel mnemonics and pseudo
operations with free-format input, and
conditional assembly features
DDT
Dynamic Debugging Tool-contains
an integral assembler/disassembler
module that lets the user patch and
display memory in either assembler
mnemonic or hexadecimal form and
trace program execution with full
register and status display;
instructions can be executed between
breakpoints in real-time, or run fully
monitored, one instruction at a time
SUBMIT
Allows a group of CP/M commands to
be batched together and submitted to
the operating system by a single
command
STAT
-Programs created under CP/M can be checked out
by loading and executing these programs in
theTPA
Lists the number of bytes of storage
remaining on the currently logged
disks, provides statistical information
about particular files, and displays or
alters device assignments
LOAD
-User programs, loaded into the TPA, may use the
CCP area for the. program's data area
Converts Intel hex format to absolute
binary, ready for direct load and
execution in the CP/M environment
SYSGEN
Creates new CP/M system.disks for
back-up purposes
-Loads and transfers control to transient programs,
such as assemblers, ~ditors, and debuggers
-Processes built-in standard commands including:
ERA
Erase specified files
DIR
List file names in the directory
REN
Rename the specified file
SAVE
Save memory contents in a file
TYPE
Display the contents of a file on
the console
TPA-Transient Program Area
-Holds programs which are loaded from the disk
under command of the CCP
-Transient commands are specified in the same
manner as built-in commands
MOVCPM Provides regeneration of CP/M
systems for various memory
configurations and works in
conjunction with SYSGEN to provide
additional copies of CP/M
-Additional commands can be easily defined by the
user
-Defined transient commands include:
PIP
ED
Peripheral Interchange Program
-implements the basic media transfer
operations necessary to load, print,
punch, copy, and combine disk files;
PIP also performs various
reformatting and concatenation
functions. Formatting options include
parity-bit removal, case conversion,
Intel hex file validation, subfile
extraction, tab expansion, line number
generation, and pagination
BENEFITS
-Easy implementation on any computer configuration which uses an Intel 8080/8085 Central Processing Unit (see the CP/M-86 data sheet for CP/M
applications on the iAPX86 CPU)
-Extensive selection of CP/M-compatible programs
allows production and" support of a comprehensive software package at low cost
Text Editor-,...allows creation and
modification of ASCII files using
extensive context editing commands:
string substitution, string search,
insert, delete and block move; ED
allows text to be located by context,
line number, or relative position with a
macro command for making extensive
text changes with a single command
line
-Easy migration path to timesharing systems with
multiprogramming and multiterminal features
(see the MP/M*, CP/NET*, and MP/NET* data
sheets)
-Field programmability for special-purpose operating system requirements
-Upward compatibility from previous versions of
CP/M release 1
24-2
AFN'()2111A
intel'
DIGITAL RESEARCH, INC.
CP/M 2.2
-Provides field specification of one to sixteen logical drives, each containing up to eight megabytes
-Files may contain up to 65,536 records of 128 bytes
each but may not exceed the size of any single disk
-Each disk is designed for 64 distinct files-more
directory entries may be allocated if necessary
-Individual users are physically separated by user
numbers, with facilities for file copy operations
from one user area to another
-Relative-record random-access functions provide
direct access to any of the 65,536 records of an
eight-megabyte file
SPECIFICATIONS
Hardware Required
Shipping Media
Intellec Microcomputer Development System
-Series II or
-Model 800
(Specify by Alpha Character when ordering.)
Optional:
A-single density (Intellec compatible,
IBM 3740/1 format)
RAM up to 64K
Order Code
-additional floppy disk drives
-Winchester disk drive
Product Description
Availability: January 1982
Documentation Package
Part Number
Title
121865
and optional
binder
121864
CP/M 2.2 documentation consisting
of 7 manuals:
An Introduction to CP/M Features
and Facilities
CP/M 2.2 User's Guide
CP/M Assembler (ASM) User's
Guide
CP/M Dynamic Debugging Tool
(DDT) User's Guide
ED: A Context Editor for the CP/M
Disk System User's Manual
CP/M 2 Interface Guide
CP/M 2 Alteration Guide
An Intel Master Software License and Amendment required.
·CP/M is a registered trademark of Digital Research, Inc.
·CP/M-BB, MP/M, CP/NET, and MP/NET are trademarks of Digital Research, Inc.
24-3
AFN-02111A
inter
DIGITAL·RESEARCH INC.
CP/M-86*OPERATING SYSTEM
• High-performance, single-user
operating system for 16-bit computers
based on Intel's iAPX-86 (8086) and
compatible iAPX-88 (8088)
microprocessors
• CP/M-86 files are completely
compatible with versions of CP/M* used
with Intel 8-bit 8080- and 808S-based
microcomputer systems
• CP/M-86 manages up to 1 Mbyte of online RAM storage for full support of
programs as large and. as powerful as
those found on minicomputers
• The standard CP/M-86 package
includes an assembler, an interactive
debugger, and additional utilities for
complete program development
• Supports up to 16 logical drives, each
containing up to eight megabytes for a
total of 128 megabytes of on-line
storage
CP/M-B6 is a single-user operating system designed especially for 16-bit computers based on the Intel iAPX-86
(8086) and compatible iAPX-88 (80B8) microprocessors. The system fully utilizes the one megabyte (1,048,576
bytes) of main memory available for application programs.
CP/M-B6 occupies only 11 K of memory with a floppy disk-based I/O System occupying about 1K, depending on
the number of peripherals supported. The remainder of the 8086/B088 address space. may be defined by the
user. Flexibility is provided by the system's ability to reside anywhere in memory, and it can be relocated by the
user without changing the operating system.
Because CP/M-86 files are completely compatible with CP/M for Intel 8-bit microprocessors, there is an easy
upgrade of existing CP/M applications software to 16-bit iAPX-86 (8086)-based systems.
FEATURES
Major features of the CP/M-B6 operating system
include:
Modular Design
-BIOS: Basic Input/Output System
The physical variant portion of the operating system, BIOS contains the system-dependent input/output device handlers
Based on a proven, modular design, the system includes the:
CP/M Compatibility
-CCP: Console Command Processor
The CCP is the human interface to the operating
system and performs decoding and execution of
user commands
CP/M-B6 files are completely compatible with CP/M
for 80BO- and 80B5-based microcomputer systems.
This simplifies the conversions of software
developed under CP/M and allows full advantage of
16-bit 8086-based systems.
-BOOS: Basic Disk Operating System
The BOOS is the logical, invariant portion of the
operating system; it supports a named file system
with a maximum of 1610gical drives, containing up
to 8 megabytes each for a potential of 128
megabytes of on-line storage
The user will notice no significant difference between CP/M and CP/M-86. Commands such as OIR,
TYPE, REN, ERA, PIp, ED, and STAT respond the
same way in both systems.
24-4
inter
DIGITAL RESEARCH, INC.
CP/M-a6
CP/M-S6 uses the S086 registers corresponding to
S080 registers for system call and return parameters
to further simplify software transport. The execution
environment in CP/M-86 allows code and data segments to overlap, making the mixture of code and
data that often appears in 8-bit applications acceptable to the 8086.
File Management
CP/M-86 can support up to 16 logical drives, each
containing up to eight megabytes, for a maximum of
1.2S megabytes of on-line storage. Anyone file can
reach the full drive size, with space dynamically allocated and released. Each device has a directory of
file control blocks that map the physical location of
each file on the disk. Disk definition tables in the
BIOS translate this logical drive, directory, and file
structure to the physical characteristics of the disk.
This file system is identical to the file system of CP/M.
Memory Management
CP/M-S6 can reside anywhere in memory and is
easily located to minimize dependence on absolute
addresses. Multiple programs may reside in memory
simultaneously. Also, a transient program may load
additional programs for execution under its own control. Up to a total of 8 programs may use noncontiguous memory areas which are managed
through a user-defined memory configuration table.
Basic I/O System (BIOS) Organization
The distribution version of CP/M-86 is set up for operation with the Intel iSBC 86/12A and an Intel 204
diskette controller. All hardware dependencies are,
however, concentrated in subroutines which are collectively referred to as the Basic I/O System, or BIOS.
A CP/M-S6 system implementor can modify these
subroutines to tailor CP/M-S6 to fit nearly any S086 or
80S8 operating environment.
To simplify the preparation of a custom BIOS, a
source listing of a working BIOS, a skeleton for a
custom module, and cross-development utilities are
supplied. The cross-development programs allow
development of custom BIOS and CP/M-86 applications software on an S-bit CP/M system.
firmware brings the CP/M-S6 loader into the system
and sets up the hardware to initialize CP/M-S6.
Utilities
CP/M-86 is supplied with eight utilities:
PIP
The Peripheral Interchange Program provides file
transfer between devices and disk files and performs
various reformatting and concatenation functions.
Formatting options include parity-bit removal, case
conversion, Intel "hex" file validation, subfile extraction, tab expansion, line number generation, and
pagination.
ED
The CP/M-86 Text Editor allows creation and modification of ASCII files using extensive commands:
string substitution, string search, insert and delete.
ED allows text to be located by context, line number,
or relative position with a macro command for making extensive text changes with a single command
line.
ASM-86
ASM-86, the CP/M-86 Assembler is an 8086 assembler using standard Intel mnemonics. It also allows
users to define unique instructions with the codemacro facility. ASM-86 is supplied in two forms: an
8086 cross assembler designed to run under CP/M
(an 8-bit system), and an 8086 assembler designed to
run under CP/M-S6.
DDT-86
The CP/M-86 Dynamic Debugging Tool allows the
user to test and debug programs interactively in a
CP/M-86 environment. The command set allows
users to trace program execution with full register
and status display. DDT-86 contains an integral assembler/disassembler module that lets users patch
and display memory in assembler mnemonic form.
SUBMIT
Allows a group of CP/M-86 commands to be batched
together and submitted to the operating system by a
single command.
STAT
PROM Loader
Lists the number of bytes of storage remaining on
the currently logged disks, provides statistical information about particular files, and displays or alters
device assignments.
For users who have the iSBC S6/12 hardware configuration, there is an optional PROM Loader. The
GENCMD and LMCMD
GENCMD and LMCMD are used to produce CMD
24-5
AFN·02112A
inter.
DIGITAL RESEARCH, INC.
CP/M-86
memory image files suitable for execution under
CP/M"86. The GENCMD, utility processes Intel files,
which may be produced either by Digital Research's
ASM-86 or by Intel's OH86 utility. LMCMD processes
Intel L-module files resulting from the standard Intel
LOC86 Object Code Relocator Utility. These commands allow generatioh of new utilities.
BENEFITS
-Designed especially for full advantage of Intel
iAPX-86/12A (8086)-based computer systems
-Complete compatibility with versions of CP/M for
Intel 8080/8085-based microcomputer systems
makes it easy to upgrade existing CP/M applications software to preserve software investment
(see the CP/M Operating System data sheet for
additional' CP/M benefits)
-Cross-development to'ols, including the ASM-86
assembler and the GENCMD utility, can reside on a
8080/8085-based CP/M system; with these tools,
the programmer can assemble a custom BIOS program and generate a loadable object
that runs
on the target system
file
-Proven modular design occupies a small amount
of memory to give maximum user-defined space
for'application programs in the available onemegabyte main memory.
-Allows up to 128 megabytes of on-line magnetic
storage
-CP/M-86 manages up to 1 Mbyte of on-line RAM
storage for full support of programs as large and
as powerful as those found on minicomputers
-Allows multiple programs in memory for transient
program execution; multiple programs may use
non-contiguous memory areas for application
programs
-ASM-86 and DDT-86 provide the basic tools for
assembly language development and program
debugging using the iAPX-86/12A (8086) microprocessor
-CP/M-86 is a complete system including the operating system and development tools; a
comprehensive set of manuals describes system
operation, customization, interfacing of applications programs, listings of sample programs, a.nd
operation of the assembler, debugger, and editor
~ The
CP/M-86 package includes full documentation
for the product; documentation is also available
separately; a CP/M-86 PROM loader is available for
.the Intel SinglecBoardComputer
SPECIFICATIONS
Hardware Required
Shipping Media
-iSBC 86/12A
-iSBC204
-CRT
(Specify by Alpha .Character when ordering.)
Optional:
-upto 1 megabyte RAM
-up to 16 disk drives (8 megabytes each)
A- Single Density (Intellec compatible,
IBM 3740/1 format)
Order Code
Description
Availability: January 1982
Documentation Package
: .Description
Part Number
CP/M-86 system, program and
121866
user's guides
An Intel Master Software License and Amendment required.
'CP/M is a registered trademark of Digital Research, Inc.
'CP/M-B6 is a trademark of Digital Research, Inc.
AFN-02112A
inter
MICROSOFT* MACRO-SO UTILITY
SOFTWARE PACKAGE
• Includes the MACRO-80 macro
assembler, L1NK-80 linking loader, and
CREF-80 cross-reference facility
• Supports a complete, Intel-standard
MACRO facility, including IRP, IRPC,
REPEAT, local variables, and EXITM
• Supports conditional assembly,
including testing of assembly pass,
symbol definition, and parameters to
MACROs
• Code is assembled in relocatable
modules for easy manipulation by the
L1NK-80 linking loader
• Assembly rate of over 1000 lines per
minute
• Provides "big computer" assembler
features without sacrificing speed or
memory space
• Provides a complete set of listing
controls
• L1NK-80 loads relocatable modules at
user-specified locations
• CREF-80 cross-reference facility
alphabetizes program variables and
shows where each is defined and
referenced
The Microsoft Utility Software Package is a complete system for developing assembly language programs,
routines, and subroutines. The Utility Software Package includes the MACRO-BO macro assembler, the LlNK-BO
linking loader, and the CREF-BO cross-reference facility. The CP/M" version also includes the LlB-BO Library
Manager.
The Utility Software Package is supplied with all Microsoft compilers to provide assembly language subroutine
support to main programs in the high-level programming languages. The LlNK-BO linking loader is used
by all Microsoft compilers for linking and loading compiled relocatable modules. Thus, LlNK-BO allows the
programmer to link together relocatable modules from different Microsoft languages.
FEATURES
MACRO-80 Macro Assembler
MACRO-BO incorporates almost all "big computer"
assembler features without sacrificing speed or
memory space. The assembler supports a complete,
Intel-standard macro facility, including IRP, IRPC,
REPEAT, local variables, and EXITM. Macro names
take precedence over instruction mnemonics and
pseudo operations. Nesting of macros is limited only
by memory. Code is assembled in relocatable
modules that are easily manipulated with the flexible
linking loader. Conditional assembly capability is
greatly enhanced by an expanded set of conditional
pseudo operations that include testing of assembly
pass, symbol definition, and parameters to macros.
Conditionals may be nested up to 255 levels.
More MACRO-BO features:
-Comment blocks
-Variable input radix from base 2 to base 16
-Octal or hex listings
-INCLUDE statement assembles an alternate
source file into the current program
-PRINTX statement for printing assembly or
diagnostic messages
-PHASE/DE PHASE statements allow code to
reside in one area of memory but execute in
another
-Complete set of listing controls
24-7
MICROSOFT
MACRO-SO UTILITY
LINK-SO Linking Loader
CREF-80 Cross-Reference Facility
With LlNK-80, any number of programs may be
loaded with one command, relocatable modules may
be loaded in user-specified locations, and external
references between modules are resolved automatically by the loader. The loader also performs library
searches for system subroutines and generates a
memory load map showing the locations of the main
program and subroutines.
The Cross-Reference Facility that is included with the
Utility Software Package supplies a convenient alphabetic list of all program variable names, along
with line numbers where they are referenced and
defined.
SPECIFICATIONS
Operating Environment
Documentation Package
MACRO-80 resides in approximately 19K bytes of
memory. LlNK-80 resides in approximately 14K bytes
of memory. CREF-80 requires about 6K bytes. The
MACRO-80 Utility Software Package is compatible
with the CP/M' operating system.
One copy of each manual is supplied with the
software package. Additional copies are available.
Required Hardware
Shipping Media
Intellec® Microcomputer Development System
(Specify by Alpha Character when ordering.)
-Model 800 or
-Series II
-minimum of 1 diskette drive
A-Single Density (Intellec® compatible,
IBM 3740/1 format)
B-Double Density (Intellec® compatible,
M2FM format)
Part Number
Description
121797
Microsoft Utility Software Manual
Required Software
CP/M Operating System or MP/M-W Operating
System.
ORDERING INFORMATION
Order Code
Description
SD106CPM80A
Microsoft MACRO-80 Utility Software Package, CP/M version (Single-Density Diskette)
SC106CPM80B
Microsoft MACRO-80 Utility Software Package, CP/M version (Double-Density Diskette)
An Intel Master Software License and Amendment required.
'Microsoft is a trademark of Microsoft, Inc.
'CP/M is a registered trademark of Digital Research. Inc.
'MP/M-II is a trademark of Digital Research, Inc.
24-8
intel~
MICROSOFT* BASIC-SO INTERPRETER
SOFTWARE PACKAGE
II
Compatible with other Microsoft BASIC
compilers and interpreters
II
Sophisticated string handling and
structured programming features for
applications development
II
II
II
Direct transfer of BASIC programs to
the 8085, 8086 and 8088
Random and sequential file
manipulation where random file record
length is user-definable
II
Meets the requirements for the ANSI
subset standard for BASIC, and
supports many enhancements
II
Extensive text editing features built-in
II
Automatic line number generation and
renumbering
II
Supports assembly language
subroutine calls
II
Trace facilities for easier debugging
Read or write memory location
capabilities
BASIC Release 5.0 from Microsoft is an extensive implementation of BASIC. Microsoft BASIC gives users what
they want from a BASIC-ease of use plus the features that are comparable to a minicomputer or large
mainframe.
BASIC-80 meets the requirements ·for the ANSI subset standard for BASIC, as set forth in document BSRX3.601978. It supports many unique features rarely found in other BASICs.
FEATURES
-Four variable types: Integer (-32768, +32767),
String (up to 255 characters), Single-Precision
Floating Point (7 digits), Double-Precision
Floating Point (16 digits).
-Formatted output using the PRINT USING facility,
including asterisk fill, floating dollar sign,
scientific notation, trailing sign, and comma
insertion.
-Trace facilities (TRON/TROFF) for easier
debugging.
-Direct access to I/O ports with the INP and OUT
functions.
-Error trapping using the ON ERROR GOTO
statement.
-Extensive program editing facilities via EDIT
command and EDIT mode subcommands.
-PEEK and POKE statements to read or write any
memory location.
-Assembly language subroutine calls (up to 10 per
program) are supported.
-Automatic line number generation and
renumbering, including reference line numbers.
-IF/THEN/ELSE and nested IF/THEN/ELSE
constructs.
-Matrices with up to 255 dimensions.
-Supports variable-length random and sequential
disk files with a complete set of file manipulation
statements: OPEN, CLOSE, GET, PUT, KILL,
NAME, MERGE.
-Boolean operators OR, AND, NOT, XOR, EQV,
IMP.
24-9
MICROSOFT
BASIC·SO INTERPRETER
Arithmetic Functions
BASIC·SO Commands, Statements,
Functions
AUTO
LIST
NULL
TROFF
CLEAR
LOAD
RENUM
WIDTH
CO NT
MERGE
RUN
DELETE
RANDOMIZE
COMMON
DEF FN
ERROR
POKE
RESUME
SWAP
DEFDBL
DEFSTR
DEFSNG
DEFINT
LOG
FIX
COS
RND
TAN
String Functions
Program Statements
CALL
GOSUB
END
GOTO
STOP
WHILE/
WEND
CHAIN
DEF USR
LET
REM
SIN
CDBL
CSNG
CINT
SQR
ABS
INT
SGN
ATN
EXP
NAME
SAVE
EDIT
NEW
TRON
ASC
LEN
STRING$
CHR$
LEFT$
RETURN
WAIT
ON GOSUB
DIM
FOR/NEXT/
STEP
IF/THEN/
ELSE
ON ERROR
GOTO
OPTION BASE
INSTR
RIGHT$
MID$
SPACE$
STR$
HEX$
OCT$
VAL
Operators
1\
<=
<
>
<>
XOR
NOT
EQV
MOD
IMP
OR
AND
+
\
>=
Input/Output Statements and Functions
CLOSE
KILL
OUT
RESTORE
READ
TAB
DATA
LINE
INPUT
PRINT
WRITE
LPRINT
GET
POS
FIELD
LSET/RSET
PRINT
USING
LOC
MKI$
MKS$
MKD$
LLiST
LPOS
NAME
PUT
EOF
SPC
INKEY$
INPUT
OPEN
CVD
CVI
CVS
Special Functions
VARPTR
PEEK
ERR
FRE
ERL
USR
SPECIFICATIONS
Operating Environment
Required Software
The standard disk version of Microsoft BASIC-80 occupies 24K bytes of memory. Microsoft BASIC-80
Interpreter is compatible with the CP/M* operating
system.
CP/M Operating System or MP/M-II* Operating
System.
Required Hardware
Documentation Package
One copy of each manual is supplied with the
software package. Additional copies are available.
Intellec Microcomputer Development System
Part Number
-Model 800 or
-Series II
-minimum of 1 diskette drive
121806
121857
24-10
Description
BASIC-80 Reference Manual
BASIC Reference Book
AFN'()2086A
intel~
MICROSOFT* COBOL-SO
SOFTWARE PACKAGE
• GSA validation at low-intermediate
level implementation of ANSI 74
requirements
• Highly efficient pseudo-code compiler
produces compact, fast code
• Complete utility software package,
including macro assembler, linking
loader, and MICROSOFT M/SORT
• Combines the most useful Level 1 and
Level 2 ANSI 74 features, making it the
most extensive implementation of
COBOL for microcomputers
• Tailorable screen-formatting facilities
allow configuration to any intelligent
terminal for menu and forms
generation
• Interactive accept/display features
allow direct interaction between data,
program and operator
• COBOL offers four kinds of files for
simplicity and speed in data retrieval
COBOL has been the language of choice for commercial data processing for over two decades, and because of
its established superiority, more useful business software has been written in COBOL than in any other
language. That means quality, full-function packages, many written by the field's foremost experts, are available
now. Existing systems for payroll, accounts receivable, general ledger, inventory, order entry, and forecasting
can run under Microsoft COBOL-80.
COBOL offers the flexibility that makes products adaptable, versatile, and available to thousands of microcomputer users. COBOL-80 not only retains the high-level features of standard COBOL, but also introduces
superior interactive capabilities and user-oriented features which represent a major advance in the commercial
use of COBOL. With COBOL-80, direct interaction between data, program, and operator becomes possible. The
immediate acknowledgement or rejection of user-entered data facilitates equally immediate corrections and
modifications.
FEATURES
validated by GSA as a low-intermediate implementation of the ANSI 74 standard. Microsoft COBOL is
approved for federal government installations, plus
you have assurance that Microsoft COBOL will perform to specifications.
COBOL-80 ANSI Standard
and GSA Validated
COBOL-80 supports such special features as:
Because COBOL is so widely used, assurances of
compatibility and portability are important to all
users. The American National Standards Institute
has established guidelines which provide a basis for
making informed comparisons of different COBOL
compilers. Elements of the COBOL language are allocated to twelve different functional processing
modules, .at two different levels. Microsoft COBOL
combines the most useful Level 1 and Level 2
features.
Advanced verbs:
STRING, UNSTRING, COMPUTE, SEARCH,
PERFORM (VARYING/UNTIL)
Abbreviated and compound conditions
Sequential, Relative, and Indexed files
ASCII, packed and binary data formats
Runtime assignment of file names
Full COPY facility
Line Sequential files
Trace style debugging
COMP-3 data format
Program CHAIN
Program Segmentation
Formatted screen ACCEPT/DISPLAY
with a single command
The United States government, through the General
Services Administration (GSA), tests COBOL compilers to validate their compatibility and their implementation of the ANSI 74 standard. Microsoft
COBOL for the CP/M operating system has been
24-11
infel'
MICROSOFT
COBOL·SO
Program Structuring
COBOL's unique suitability to the business environment is due in large part to the structuring capabilities built into the language. COBOL-80 programs
have a natural, logical organization which reflects
the nature of commercial data. This efficient, clean,
top-down design makes COBOL-80 programs faster
to write and easier to maintain than those written in
other computer languages.
OOOO-MAIN-LiNE.
PERFORM 1000-INITIALIZE.
PERFORM 2000-ENTER ORDER
UNTIL END-SESSION.
IF REPORT-REQUIRED
PERFORM 3000-PRINT SUMMARY.
PERFORM 4000-TERMINATE.
CHAIN "MAINMENU".
1ODD-INITIALIZE.
DISPLAY SIGN-ON-SCREEN.
ACCEPT SIGN-ON-SCREEN.
PERFORM 1100-CHECK-SECURITY-CODE.
MOVE ZERO TO ORDER-COUNT
ERROR-CODE.
SESSION-TOTAL.
Data Structuring
The data in COBOL programs is arranged hierarchically. Information is stored in a logical structure with
direct interconnection between related pieces of
data. (Note here how COBOL's PICTURE specification allows exact decimal arithmetic for precise
representation of any dollar amount.)
05 TRANSACTION
10 TRAN-REF.
10TRAN-DATE.
15TRAN-MM
15TRAN-DD
15 TRAN-YY
10 POST-DATE.
15 POST-MM
15 POST-DO
15 POST-YY
10 TRAN-AMOUNT
10 TRAN-AMOUNT
PIC X(12).
PIC XX.
PIC XX.
PIC XX.
changed. Any chance of inconsistencies between
programs is eliminated. At execution, each item in a
COBOL-80 data structure may be referenced individually, or grouped items may be manipulated as easily.
Processing code accesses the structure at any appropriate level:
MOVE JOURNAL-TRAN TOTRANSACTION.
MOVE CURRENT-DATE TO POST-DATE.
IF TRANS-AMOUNT <0
MOVE TRANSACTION TO CR-TRAN.
ELSE
MOVE TRANSACTION TO DB-TRAN.
Screen Handling
COBOL's move from the batch environment to on!!;-,,:;
applications has brought a new emphasi"ls to the
interaction between the application and the terminal
operator. COBOL-80 provides a SCREEN SECTION
for the definition of formatted screens. Special syntax is available for cursor positioning, protected and
unprotected fields, highlighting, full and partial
screen erase, and for defining connections between
fields defined on the screen and data source!
destination fields in WORKING-STORAGE. Data
entry forms, menus, reports and other screens are
ACCEPTed or DISPLAYed with a single command, so
coding is simple. At execution time, related data
items can be keyed, viewed together, and corrected
before being entered into the program.
COBOL-80's screen handling facilities are Data General compatible, and learning to use the features is
easy. Data descriptions are generally of the same
form as in other sections of the Data Division. The
screen section allows full screen descriptions without forcing allocation of WORKING-STORAGE space
for unused portions of the screen.
On output, COBOL's extensive formatting capabilities provide neat, precise reports with minimal effort.
Program Chaining
PIC XX.
PIC XX.
PIC XX.
PIC S9(8)V99.
PICX(4).
Once this structure has been coded it can be stored
in a file and used in any program. Only one statement
is needed to retrieve it: COPY TRANSDEF.COB.
COBOL-80 obviates the need to recode every program in a system when a single definition is added or
COBOL-80's CHAIN verb facilitates interactiVe systems. Any number of separately coded applications
or application segments can be reached through a
main menu. These menU-driven applications which
make ideal use of COBOL-80's interactive capabilities, allow smooth transfer of control from one program to another. With CHAIN, control is transferred
from the menu program to any executable module as
specified at runtime. COBOL-80 programs can also
CALL COBOL-80 subprograms or Microsoft
FORTRAN-80 or assembly language subroutines.
24-12
AFN.Q2090A
MICROSOFT
COBOL-80
File Handling
Indexed Sequential
COBOL-BO aims for simplicity and speed in data
retrieval. COBOL-BO offers four kinds of files, so data
storage can aptly correspond to the application for
which it will be used. Each file type has unique
characteristics:
Sequential
The fastest possible
access to test, packed,
and binary data in any
combination.
Line Sequential
Text data in line format.
Compatible with the files
generated by many text
editors.
Relative
Random access by record
number. Direct disk
access makes relative files
extremely fast, yet data
can be accessed in any
sequence, deleted or
updated interactively, and
cross-referenced by key
across files.
Segmentation
COBOL-BO's program segmentation capability
makes maximum use of memory when large programs are executed. Segmentation brings individual
program sections into memory as they are needed.
This allows execution of programs whose size may
exceed machine memory by several times. Program
segmentation is easily implemented by assigning a
single number to each program section which indicates whether the section is to be resident in memory
or overlaid during execution. Any section to be overlaid is automatically read into a preallocated section
of memory during execution.
Microsoft COBOL-80 and
the ANSI Standard
Module
Nucleus
The most powerful data
access method available
from any data processing
language in any environment. A field within each
record is chosen as a
key, and the value of this
key identifies a record to
be read, written,
updated, or deleted.
VERBS:
Extensions to the
functions of ACCEPT
and DISPLAY for
formatted screen
handling
ACCEPTance of data
from DATE/DAY/TIME
STRING and
UNSTRING statements
COMPUTE with
multiple receiving
fields
PERFORM VARYING
Features of
Microsoft COBOL
All of Level 1, plus these
features of Level 2:
CONDITIONS:
Level BB conditions
with value series or range
Use of logical
AND/OR/NOT in
conditions
Use of algebraic
relational symbols
«,>,=)
Implied subject, or
both subject and
relation, in relational
conditions
Sign Test
Nested IF statements;
parentheses in
conditions
IDENTIFIERS:
Mnemonic-names for
ACCEPT or DISPLAY
devices
Procedure-names
consisting of digits
only
Qualification of names
(in Procedure Division
statements only)
24-13
AFN·02090A
inter
Sequential,
Relative,
and Indexed 1/0
MICROSOFT
COBOL-80
All of Level 1 plus these
features of Level 2:
RESERVE clause
Multiple operands in
OPEN & CLOSE, with
individual options per file
Value of FILE-ID is dataname
Sequential 1/0
EXTEND mode for OPEN
WRITE ADVANCING data
name lines
LINAGE phrase and AT
END-OF-PAGE clause
Relative and
Indexed 1/0
DYNAMIC access mode
(with READ NEXT)
START (with key
relationals EQUAL,
GREATER, or NOT LESS)
Utility Software Package
Library
Level 1
Inter-Program
Communication
Level 1
Table Handling
All of Level 1
Full Level 2 formats for
SEARCH statement
Debugging
Special extensions to
ANSI-74 Standard
providing convenient
trace style debugging.
Conditional Compilation:
lines with "D in column
7" are bypassed unless
"WITH DEBUGGING
MODE" is given in
SOURCE-COMPUTER
paragraph.
Segmentation
Level 1
statements. For M/SORT-C, the source of the input
records may be one or a set of disk files; or, records
may be constructed in memory by a user-written
COBOL procedure and RELEASED to M/SORTone at
a time.
COBOL-80 includes the Microsoft Utility Software
Package. The Utility Software Package includes the
MACRO-80 macro assembler, the L1NK-80 linking
loader, and the CREF-80 Cross-Reference Facility.
Refer to the description of the Utility Software Package for full details.
M/SORT
Similarly, the sorted output records may be automatically written to a disk file; or, records may be left in
memory for processing by a user-written OUTPUT
PROCEDURE within the COBOL program. M/SORTC can load an indexed sequential file.
The COBOL-h'osted version of M/SORT (M/SORT-C)
is a record-sorting facility available to the programmer through the 1974 ANSI COBOL SORT/MERGE
M/SORT-C provides for a special SORT STATUS register which can collect and return any errors
encountered during a sort.
SPECIFICATIONS
Required Software
Operating Environment
CP/M' Operating System or MP/M-II' Operating
System.
COBOL-80 requires about 40K bytes of user memory
in addition to the operating system's space. COBOL
object programs will run on systems as small as 32K
bytes.
Required Hardware
Documentation Package
One copy of each manual is provided with the
software package. Additional copies may be ordered.
Part Number
121801
121802
121797
121862
Intellec Microcomputer Development System
-Model 800 or
-Series II
-minimum of 1 diskette drive
24-14
Description
COBOL-80 Reference Manual
COBOL-80 User's Guide
Microsoft Utility Software Manual
M{SORT Reference Manual
AFN'{)2090A
MICROSOFT* FORTRAN-80
SOFTWARE PACKAGE
• Full ANSI standard FORTRAN X3.9-1966
(except the complex data type)
• Provides numerous enhancements to
the 1966 ANSI standard
• Compiles several hundred statements
per minute in a single pass
• Optimizes the generated object code by
common subexpression, elimination,
peep hold optimization, constant
folding, and branch optimizations
• Provides diagnostic output: descriptive
error messages, error summaries, and
fully symbolic listings of generated
machine language
• Supplies an extensive library of
efficient subroutines
• Supports user-written non-standard I/O
drivers for each logical unit number to
interface non-standard devices to
FORTRAN programs
Microsoft FORTRAN-80 brings the most popular science and engineering programming language to 8080/8085
microcomputers. FORTRAN-80 is comparable to FORTRAN compilers on large mainframes and minicomputers.
The FORTRAN-80 package includes full ANSI Standard FORTRAN X3.9-1966 except the COMPLEX data type.
With this compiler, users may take advantage of many applications programs already written in FORTRAN.
FEATURES
FORTRAN-80 enbances the 1966 ANSI Standard in
several ways·
-Sin,Q1'e-byte LOGICAL variables which can be
LiSed as integer quantities in the range + 127
to -127.
-DO loops which use LOGICAL variables for
tighter, faster execution of small loops.
-Mixed-mode arithmetic expressions.
-Hexadecimal constants.
-Hollerith (character) literals accepted.
-Logical operations on integer data .. AND., .OR.,
.NOT., .x0R., can be used for 8-bit, 16-bit, or
32-bit Boolean operations.
-READ/WRITE End-of-File or Error-Condition
transfer. END=n and ERR=n (where n is the
statement number) can be included in READ
or WRITE statements to transfer control to the
statement specified by n when an error or end-offi Ie is detected.
-ENCODE/DECODE for FORMAT operations to
memory.
-IMPLICIT statement for redefining default
variable types by specifying a type and a range of
initial letters.
-INCLUDE statement for including commonly used
subroutines, code, or declarations from another
file.
-INTEGER'4 variables and constants using 32 bits
in the range of +2,147,483,647 to -2,147,483,648.
-Support for CP/M' version 2.x providing access
to a maximum of 65,535 random records in a file
as large as 8 megabytes.
24-15
MICROSOFT
FORTRAN-SO
COMPILER DESCRIPTION
Subroutine Library
FORTRAN-80 compiles several hundred statements
per minute in a single pass. It requires no more
than 27K bytes of memory to compile most
programs. Additional memory, when available, is
used for symbol table storage and optimizations.
Compiled programs are relocatable modules that
are linked and loaded at runtime.
FORTRAN-80 supplies an extensive library of efficient subroutines. Only the necessary subroutines
are loaded by the linker at load time. The FORTRAN
library includes the following Intrinsic Functions:
The FORTRAN-80 compiler optimizes generated
object code in several ways:
Common Subexpression Elimination
Common subexpressions are evaluated once;
the value is automatically substituted in
subsequent occurrences of the subexpression.
Peephole Optimization
In special cases, small sections of code can
be replaced by more compact code.
Example: 1=1+1 uses an INX H instruction
instead of a DAD.
Constant Folding
Integer constant expressions are evaluated at
compile time.
Branch Optimizations
The number of conditional jumps in
arithmetic and 10gicailFs is minimized.
The compiler also provides diagnostic output.
Descriptive error messages include the preceding
twenty characters. At program's end, the compiler
generates an error summary. A fully symbolic listing
of the generated machine language is also produced.
This is supplemented by tables of addresses assigned
to labels, variables, and constants.
SPECIFICATIONS
Operating Environment
The FORTRAN-80 compiler occupies approximately
24K bytes of memory, using the CP/M operating system. Most programs can be compiled within 27K
bytes of additional memory. At link time, the LlNK-80
linking loader occupies about 14K bytes. The Runtime Library requires 2K-14K bytes, depending on the
type of program being run.
ABS
AINT
ALOG
ALOG10
AMAXO
AMAX1
AMINO
AMIN1
AMOD
ATAN
ATAN2
COS
DABS
DATAN
DATAN2
DBLE
DCOS
DEXP
DIM
DLOG
DLOG10
DMAX1
DMIN1
DMOD
DSIGN
DSIN
DSORT
EXP
FIX
FLOAT
lABS
101M
IDINT
INP
INT
ISIGN
MAXO
MAX1
MIND
MIN1
MOD
OUT
PEEK
POKE
SIGN
SIN
SNGL
SORT
TANH
The library also contains efficient routines for 16-bit
and 32-bit integer arithmetic and 32-bit and 64-bit
floating point arithmetic.
Utility Software Package
The FORTRAN-80 package includes the Microsoft
Utility Software Package. The Utility Software Package includes the MACRO-80 macro assembler, the
LlNK-80 linking loader, and the CREF-80 CrossReference Facility. Refer to the description of the
Microsoft Utility Software Package for full details.
Custom I/O Drivers
Users may write non-standard I/O drivers for each
Logical Unit Number, so interfacing non-standard
devices to FORTRAN programs is straightforward.
Required Hardware
Intellec Microcomputer Development System
-Model 800 or
-Series II
-minimum of 1 diskette drive
Required Software
CP/M' Operating System or MP/M-II* Operating
System.
24-16
AFN·02089A
inter'
MICROSOFT*SASIC-86 INTERPRETER
SOFTWARE PACKAGE
• Compatible with other Microsoft BASIC
compilers and interpreters
• Sophisticated string handling and
structured programming features for
applications development
• Direct transfer of BASIC programs to
the 8080, 8085 and 8088
• Random and sequential file
manipulation where random file record
length is user-definable
• Meets the requirements for the ANSI
subset standard for BASIC, and
supports many enhancements
• Extensive text editing features built-in
• Automatic line number generation and
renumbering
• Supports assembly language
subroutine calls
• Trace facilities for easier debugging
• Read or write memory location
capabilities
BASIC Release 5.0 from Microsoft is an extensive implementation of BASIC. Microsoft BASIC gives users what
they want from a BASIC-ease of use plus the features that are comparable to a minicomputer or large
.
mainframe.
BASIC-86 meets the requirements for the ANSI subset standard for BASIC,·as set forth in document BSRX3.601978. It supports many unique features rarely found in other BASICs.
FEATURES
-Four variable types: Integer (-32768, +32767),
String (up to 255 characters), Single-Precision
Floating Point (7 digits), Double-Precision
Floating Point (16 digits).
-Formatted output using the PRINT USING facility,
including asterisk fill, floating dollar sign,
scientific notation, trailing sign, and comma
insertion.
-Trace facilities (TRON/TROFF) for easier
debugging.
-Direct access to I/O ports with the INP and OUT
functions.
-Error trapping using the ON ERROR GOTO
statement.
-Extensive program editing facilities via EDIT
command and EDIT mode subcommands.
-PEEK and POKE statements to read or write any
memory location.
-Assembly language subroutine calls (up to 10 per
program) are supported.
-Automatic line number generation and
renumbering, including referenced line numbers.
-IF/THEN/ELSE and nested IF/THEN/ELSE
constructs.
-Matrices with up to 255 dimensions.
-Supports variable-length random and sequential
disk files with a complete set of file manipulation
statements: OPEN, CLOSE, GET, PUT, KILL,
NAME, MERGE.
-Boolean operators OR, AND, NOT, XOR,
EQV, IMP.
24-17
in1:el
MICROSOFT
BASIC-8S INTERPRETER
BASIC-8S Commands, Statements,
Functions
AUTO
LIST
NULL
TROFF
CLEAR
LOAD
RENUM
WIDTH
CO NT
MERGE
RUN
DELETE
NAME
SAVE
EDIT
NEW
TRON
RANDOMIZE
COMMON
DEF FN
ERROR
POKE
RESUME
SWAP
DEFDBL
DEFSTR
DEFSNG
DEFINT
ABS
INT
SGN
ATN
EXP
SIN
CDBL
CSNG
CINT
SQR
LOG
FIX
COS
RND
TAN
String Functions
Program Statements
CALL
GOSUB
END
GOTO
STOP
WHILE/
WEND
CHAIN
DEF USR
LET
REM
Arithmetic Functions
RETURN
WAIT
ON GOSUB
DIM
FOR/NEXT/
STEP
IF/THEN/
ELSE
ON ERROR
GOTO
OPTION BASE
ASC
LEN
STRING$
CHR$
LEFT$
STR$
HEX$
OCT$
VAL
INSTR
RIGHT$
MID$
SPACE$
Operators
/\
<=
<
>
<>
XOR
NOT
EQV
MOD
IMP
OR
AND
Input/Output Statements and Functions
CLOSE
KILL
OUT
RESTORE
READ
TAB
DATA
LINE
INPUT
PRINT
WRITE
LPRINT
GET
POS
FIELD
LSET/RSET
PRINT
USING
LOC
MKI$
MKS$
MKD$
LLiST
LPOS
NAME
PUT
EOF
SPC
INKEY$
INPUT
OPEN
CVD
CVI
CVS
Special Functions
ERL
USR
ERR
FRE
VARPTR
PEEK
SPECIFICATIONS
Required Software
Operating Environment
CP/M-86*Operating System or MP/M-86*Operating
System.
The standard disk version of Microsoft BASIC-86 occupies 32K bytes of memory. Microsoft BASIC-86
Interpreter is compatible with the CP/M-86 operating system.
Documentation Package
Required Hardware
One copy of each manual is provided with the
software package. Additional copies are available.
Part Number
Microsoft* BASIC-86 Interpreter will operate with
any currently supported configuration of CP/M-86 or
MP/M-86.
121810
121857
24-18
Description
BASIC-86 Reference Manual
BASIC Reference Book
AFN.Q2087A
MICROSOFT
BASIC-8S INTERPRETER
Shipping Media
(Please specify by Alpha Character when ordering.)
A-Single Density (Intellec compatible, IBM 3740/1 format)
ORDERING INFORMATION
Order Code
SD203CPM86A
Description
Microsoft BASIC-86 Interpreter Software Package, CP/M-86 version (Single-Density Diskette)
An Intel Master Software License and Amendment required.
'Microsoft is a trademark of Microsoft, Inc.
'CP/M-BS is a registered trademark of Digital Research, Inc.
'MP/M-BS is a trademark of Digital Research, Inc.
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AFN·02087
JOVIAL-86
CROSS-COMPILER
• IBM 370 or DEC*-10 host
• Full MIL-STD-1589B language
implementation
• Extensively optimized object code
• Supports IEEE floating-point math with
8087 coprocessor
• Functional simulation capability on the
host
II
RAM/ROM separation of constants and
code supported
• Object compatible and linkable with
Intel's languages for 8086/8088
• Generates source symbols, lines and
type information for debugging with
ICE-86A
II
Type-checking of parameters between
modules optionally enforced by the
timer
• Choice of silicon or software
implementation for floating point
• Supports 1 MB of code space
JOVIAL was developed in the late 1950s by Jules Schwartz and colleagues to aid in programming large complex
realtime systems. The language was adopted by the U.S. Air Force in 1967 and its use is now required for
programming of all embedded avionics systems.
Intel's JOVIAL Compiler implements the latest published standard of this language MIL-STD-15898 for the iAPX
86/20 microprocessor. Intel's implementation of J73 offers a complete solution for programming applications in
JOVIAL from compiling modules on the mainframe to downloading software to Intel's Series III development
system where a host of JOVIAL-86-compatible languages, relocation and linkage software, symbolic debugger
and an in-circuit emulator (ICE-86A) are available.
FEATURES
JOVIAL language was designed for programming
large complex realtime systems. The language is a
derivative of Algol and has borrowed compound
statement and control structures from it. JOVIAL
supports fixed and floating-point, Signed and unsigned integers, strings, tables and status items
(enumerated type) and permits items to be any
length from 1 bit to 256 bytes. The language provides
access to almost any configuration of logical or arithmetic values including packed structures of flexible
description. The communication pool (COMPOOL)
permits sharing of system data among many subprograms by providing a centralized data and procedure description which enforces uniform usage and
simplifies centralized configuration management of
a JOVIAL system data base.
JOVIAL COMPILER DESCRIPTION
The JOVIAL compiler operates in multiple passes.
The front-end phase analyzes the input program and
translates it into an intermediate language. The
global optimizer phase analyzes the intermediate
code and applies extensive optimizations such as
constant and value folding, multiply distribution and
operator reassociation for efficient address calculation, compile time short-cut booleans, unreachable
code deletion, and unnecessary store suppression.
The code generator phase generates relocatable
object code from this intermediate code. Other functions in the final phase are responsible for generating deficient listings and COMPOOL output.
The compiler supports development of complex and
large applications by providing a comprehensive
cross-reference listing that identifies the statement
number where the variable is set. The compiler can
also generate a statistical listing showing the distribution of various symbol table classes and intermediate language operators. The assembly language
output listing displays the object program in assembly mnemonics. And optionally, the compiler can produce a reformatted source program.
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inter
JOVIAL-86
CROSS-COMPILER
PROGRAM DEVELOPMENT PROCESS
The JOVIAL source programs may be developed and
maintained on the mainframe IBM 370 or DEC-10, or
alternately, the source programs may be created an
maintained on the Intellec Series III Microcomputer
Development System, sent to the mainframe for compilation and brought back to the Series'" for further
processing. The ONLINE utility allows the Series III to
act as a terminal to the mainframe to edit and examine files, etc. The transfer of source and object files
between the mainframe and the Series'" is accomplished with either the 2780/3780 emulator or the
upload/download software on Series III.
The object code produced by the compiler is in Intel's
standard object module format and is, therefore,
compatible with the standard Series III utilities like
LlNK86, LOC86, LlB86 and OH86. The compatibility with subprograms written in PASCAL86,
FORTRAN86, ASM86 and PUM-86 is assured by
following Intel's standard parameter passing and
register usage conventions. The compiler generates
source program symbols, lines and type information
in the object code to allow symbolic debugging with
the Series III debugger and in-circuit emulator.
The compiler generates 8087 instructions for
floating-point operations. In the absence of the 8087
processor, the 8087 emulator software may be linked
with the JOVIAL program to execute the floatingpoint instructions.
SPECIFICATIONS
Operating Environment
Documentation Package
Intel's JOVIAL compiler runs under MVS on IBM 370
and requires a 500 Kb partition. The DEC-10 version
runs under TOPS-1 0 operating system and requires
75K words.
One copy of each manual is provided with the
software package. Additional copies may be ordered.
Required Hardware
-
121887
Inteilec Series III Microcomputer Development
System
Necessary Modems and Cables for Serial Link
Required Software
-
Series'" Operating System
iAPX86 Family Utilities
Shipping Media
Mainframe Link (2780/3780 Emulator)
8086/8087/8088 Relocatable Assembler
ORDERING INFORMATION
Order Code
JOVIAL Language Specification
JOVIAL-86 User's Guide
One (1) Phase encoded, 1600 B.P.1. Magnetic Tape
One (1) Single-density Diskette (Intellec
Compatible)
One (1) Double-density Diskette (Intellec
Compatible)
Optional Software
-
Description
Part No.
121886
Description
Availability: Second Quarter 1982
"DEC and DECsYSTEM-l0 are registered trademarks of Digital Equipment Corporation.
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.'"
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