1982_Toshiba_MOS_Memory 1982 Toshiba MOS Memory
User Manual: 1982_Toshiba_MOS_Memory
Open the PDF directly: View PDF 
.
Page Count: 286
| Download | |
| Open PDF In Browser | View PDF |
-.
TOSHIBA AMERICA INCORPORATED
JBe
TOSHIBA
MOS MEMORV PRODUCTS
DATA BOOK
TABLE OF CONTENTS
Memory Selection Guide . . . . . . . . . . . . . . . . .. . ........ .
Byte-Wide Memory Pin Out Table ...................... .
Memory Cross Reference ............................ .
1
7
8
19 '6";"I;.'Q"6';'I'I""'"
TMM416P/D
TMM4164C
TMM4164P
16,384 Bit (16kx1)············
65,536 Bit (64kx1)· .......... .
65,536 Bit (64kx1) ........... .
13
25
33
M'NM4"';;;;;.I"'"
TMM314AP/APL
4,096 Bit (1kx4). : .........
4,096 Bit (4kx1) ..... , .....
TMM315D
TMM2016P/D
16,384 Bit (2kx8)· ..........
TMM2016AP Ad.en .. 'n'.,meto.n 16,384 Bit (2kx8)· ..........
TMM2016HDAd.en.. 'n'.,mot,.n 16,384 Bit (2kx8)· ..........
.
.
.
.
.
4k Bit CMOS RAM TC5514/TC5513 Comparison Table ......
16k Bit CMOS RAM TC5516/TC5517 /TC5518 Comparison Table· .
CMOS RAM Data Retention Characteristics .... ... . . . . . . . .
TC5501 P/D
1,024 Bit (256x4).. . . . . . . . . .
TC5508P
1,024 Bit (1 kx1) .. . . . . . . . . . .
TC5047AP
4,096 Bit (1kx4) ...........
4,096 Bit (4kx1) . . . . . . . . . . . .
TC5504AP/ AD
TC5514P
4,096 Bit (1 kx4) . . . . . . . . . . . .
TC5514AP/AD
4,096 Bit (1kx4).. . . . . . . . . ..
TC5513AP/AD
4,096 Bit (1kx4).. . . .. .. . . ..
TC5516AP/AD/AF
16,384 Bit (2kx8) ." .. .. . . . . ..
TC5517AP/AD/AF
16,384 Bit (2kx8).. .... .. ....
TC5517BP/BD/BF
16,384 Bit (2kx8) . . .. .. . .. . . .
TC5518BP/BD/BF
16,384 Bit (2kx8) . . . . . . . . . . . .
TC5564P
65,536 Bit (8kx8)· . . . . . . . . . . .
TC5565P
65,536 Bit (8kx8) ..........
"';"-;;"1;;;';;"-·• •*1"""'4
TMM323D
TMM323DI
TMM2732D
TMM2732DI
TMM2764D
16,384 Bit
16,384 Bit
32,768 Bit
32,768 Bit
65,536 Bit
65
66
67
69
77
83
91
99
105
113
119
131
139
147
155
163
.
.
.
.
.
173
179
185
193
201
(2kx8)· .... " ..... .
(4kx8)· .... " ..... .
(4kx8)· .......... .
(8kx8)· .......... .
(8kx8)" .......... .
(8kx8)· ........ " ..
(32kx8)·· ........ .
211
215
219
223
231
233
235
32k Bit CMOS Mask ROM Comparison Table ..... " .... " . . .
TC5332P
32,768 Bit (4kx8)· " . . . . . . . . .
TC5333P
32,768 Bit (4kx8)· .... " . . . . . .
TC5334P
32,768 Bit (4kx8)· ...... " . . . .
TC5335P
32,768 Bit (4kx8)· ....... " . . .
65,536 Bit (8kx8)· . . . . . . . . . . .
TC5364P Ad..... 'n••'m.to.n
TC5365P Ad ••n.. ,n'.,meto.n
65,536 Bit (8kx8)· ........ " . .
243
245
253
259
265
271
273
".,U""';;';';"li••II'4""
TMM334P
TMM333P
TMM2332P
TMM2364P
TMM2365P Adv.nctl Inform.tlon
TMM2366P Advencelnformetlon
TMM23256P
16,384 Bit
32,768 Bit
32,768 Bit
65,536 Bit
65,536 Bit
65,536 Bit
262,144 Bit
(2kx8)· ..........
(2kx8)- ..........
(4kx8)·· .........
(4kx8)· ..........
(8kx8)· ...........
43
49
53
59
61
i
i
i
i
MEMORY
PRODUCT
GUIDE
.
-
1 -
1. Dynamic RAM
Device Number
Capoclty
16K Bit
64KBlt*
··
Organization
TMM416D/P 2
TMM416D{P 3
TMM416D/P 4
TMM4164C-3
TMM4164C 4
TMM4164P 2
TMM4164P-3
TMM4164P-4
16384 x 1
Pro_
N-MOS
65536 x 1
N-MOS
A ....
Time
Max.
Cycle
(ns)
Ins)
150
'200
250
150
200
120
150
200
320
375
410
320
330
260
260
330
Tim."
Min.
'Power Dissipation
Max.
Power
Supplies
Pins
(mW)
activa
(V)
stand-bv
+5
-5
+12
462
20
16
+5
275
27.5
16
2. CMOS Static RAM
A.....
Capadty
Organization
Device Number
TC5501P/D
TC5501 PID- 1
TC5508P
TC5508P-4
TC5508P-l
TC5047AP-l
TC5047AP-2
TC5504API AD-2
TC5504API AD-3
TC5504APLiADL-2
TC5504APLiADL-3
TC5514AP/AD-2
TC5514AP 1AD-3
TC5514APL/ADL-2
TC5514APL/ADL-3
TC5513AP/A[)·2
TC5513APL/AD L-2
TC5514P
TC5514P-l
TC5514P-2
TC5516AP1ADI AF
TC5516AP/AD/AF-2
TC5516AP LI AD LI AF L
TC5516APL/ADLi AF L-2
TC5517AP/ADfAF
TC5517AP/AD/AF-2
TC5517 APLiADLiAFL
1 KBit
4KBit
I----
16K Bit
··
··
·
··
·
256 x 4
C-MOS
1024 x 1
C-MOS
1024 x 4
C-MOS
C-MOS
4096 x 1
1024 x 4
C-MOS
1024 x 4
TC5517BP/BD/BF
TC5517BPL/BDL/BFL
TC55188P/BD/BF
TC5518BPL/BDLiBFL
TC5564P
__
TC5565P
TC5565P-l
TC5565PL
Time
Max.
Cycle
Time
Min.
(ns)
(ns)
450
650
370
450
550
550
800
200
300
200
300
200
300
200
300
450
650
450
550
700
650
1000
300
420
300
420
200
300
200
300
200
C-MOS
102-4 x 4
C-MOS
2048 x 8
C-MOS
450
650
800
250
200
250
200
250
200
250
200
C-MOS
2048 x 8
Te5517 APL/ADL/AF L-2
:~~~1
~1
64KBlt.
Process
P PlastiC,
Pins
(V)
active
stand-by
+5
83
0.055
22
+5
55
0.055
16
+5
110
0.11
20
27.5
0.11
27.5
0.005
27.5
011
275
0.005
18
+5
+5
+5
+5
I
18
275
I
~ ~~5
138
011
110
0.11
385
24
0.005
0165
+5
385
-
+5
55
~
0005
2048 x 8
C-MOS~
200
+5
55
~
0.005
~---j~
150
100
150
100
150
C-MOS
CerdlP,
C
Ceramic,
-
F
2 -
I
I
150
100
150
100
150
Flat package
24
0005
200
C-MOSj-~~-~
18
-
200
8192 x 8
18
0.165
+5
C-MOS
8192 x 8
0
450
650
800
250
200
250
200
250
200
250
200
Max.
(mW)
2048 x 8
TC5565PL 1
Note Package Material
.. New Products
200
I
Powe' Dissipation
Power
Supplies
f--24
24
011
+5
55
-
28
0005
55
+5
55
,-------055
28
•
3. Static RAM
Organization
DevleeNumber
Capecity
TMM314AP
TMM314AP 3
TMM314AP-l
TMM314APL
TMM314APL-3
TMM314APL-l
TMM315D
TMM315D-l
TMM2016D/P 1
TMM2016D/P
TMM2016D/P-2
4KBit
16K Bit
1024 x 4
P......
N-MOS
A-.
Cvele
Tim.
Time
Max.
(ns)
Min,
450
300
450
300
200
450
200
450
300
300
200
4096 xl
-
70
55
100
150
N-MOS
2048 x8
N-MOS
200
In,>
200
70
55
100
150
200
Power
Power DI......lon
Mex.
Supplies
PI ..
(mW)
active
stand-by
550
-
385
-
+5
B80
990
110
+5
660
550
770
(V)
+18
+5
185
83
83
185
18
24
4. Erasable Programmable ROM
Time
Cycle
Time
Max.
Mo"
(ns)
(ns)
A .....
Capacity
Organization
Dnica NUmber
TMM323D
TMM323D-l
TMM323DI
TMM323DI-l
TMM27320
TMM2732D-2
12K Bit
TMM2732DI
TMM273201-2
.. TMM27640
64K Bit
TMM2764D-2
Procoa
450
2048 x8
16K Bit
N--MOS
..
.
350
450
350
350
4096)( 8
N-MOS
8192 )(8
N-MOS
250
350
250
250
200
450
350
450
350
350
250
350
250
250
200
P.....,
Supplies
(V)
+5
Power Di.ipation
Max.
Pins
(mW)
active
stend-by
525-
132
138
158
185
24
550
525
660
+5
788
~
~~
1---210
24
+5
630
184
28
I
Note TMM323DI/DI-l and TMM2732DI/OI-2 are Industrial spec parts
(operating temperature range
_40°C ...... 850(;)
5. Mask Programmable ROM
Capacity
Organization
Device Number
P...-
A....
Cycle
Time
Tim.
Mllx.
Min.
(nl)
(ns)
16KB~
64K Bit
TMM334P TMM333P
TMM2332P
TC5332P
TC5333P
TC5334P
TC5335P
TMM2364P
256K Bit
TMM23256P
..
32KBit:
Note Package Material P PastIC,
2048 x 8
4096 x 8
4096 x8
4096 )(8
4096 )(8
4096 )(8
4096 )(8
8192 x 8
32768 x8
0
Cerdlp,
N-MOS
N-MOS
N-MOS
C-MOS
C-MOS
C-MOS
C-MOS
NMOS
N-MOS
C Ceramic,
450
450
350
450
450
450
450
250
150
F PlastiC Flat
*MEMORY New Products
-
3 -
450
450
350
450
540
450
540
350
230
Powor
Supplies
(V)
+5
+5
+5
+5
+5
+5
+5
+5
+5
Power Dilupation
Max,
.-.
440
525
550
39
39
39
39
220
220
Pinl
(mW)
lUnd-by
83
0_11
0.11
0.11
0.11
83
55
24
24
24
24
24
24
24
28
28
MEMORY SELECTION GUIDE 1.
800
TC55047 AP-2
TC5514P-2
700J
TC5501P/D
TC5514P-l
TC5508P-'
TC5047AP-l
TC5510P/0-l
TC5508P-4
TC5514P, TMM314AP
60' J
Access
Time In
Nanosecond
50' J
TMM323-D/DI
TMM334P
TC5332P, TC5333P, TC5334P
TC5535P. TMM333P
TMM323D/DI-l
TMM2732D/DI
TMM2332P
TC5516AP, TMM416P10-4
TC5517AP
TMM2732D/DI-2
40, )
TC5508P
....
30' )
TC5504AP/AO-3, TMM314AP-3
TC5514AP1AO-3
200)
100 ) - -
TC5504AP/AO-2, TMM314AP-, TC5516AP-2, TMM2016P/D-2
TC5514AP/AD·2
TMM416P/D-3. TC5517AP-2.
TC5513AP/AD-2
TC5517BP, TC5518BP
TMM4164P/C-4. TMM2764D-2
TMM2016P/D. TMM416P/D-2
TMM4164P/C-3, TMM4164P-2
TC5564P-l. TC5565P-l
TMM2q16P/D-l
TC5564P. TC5565P
TMM315D
TMM315D-l
1 K BIt
TMM2364P. TMM2764D
4 K BIt
16K BIt
32 K BIt
Memory Capacity
64 K BIt
TMM23256P
256 K BIt
MEMORY SELECTION GUIDE 2.
MEMORY
1----
DEVICE
TYPE
f---
MEMORY CAPACITY
1 K Bit
----
16 K Bit
4 K Bit
32 K Bit
-RAM
CMOS Static RAM
EPROM
ROM
U1
Nch MASK ROM
CMOS MASK ROM
-~--
TMM2016PiD
TMM314AP
Nch Static RAM
TMM315D
TC5501P/O
TC5508P
256 K Bit
TMM4164PiC
TMM416P/D
Dynamic RAM
64 K Bit
TC5047AP
TC5504AP I AD
TC5514P
TC5514AP/AD
TC5513AP I AD
,
ITC5516APiADiAF
TC5517AP/AD/AF
TC5564P
I TC5517BP/BD/BF
TC5565P
TC551BBPiBDiBF
TMM323D
TMM32301
TMM2732D
TMM2732DI
TMM334P
TMM333P
TMM2332P
TMM2764D
TMM2364P
TMM23256P
TC5332P
TC5333P
TC5334P
TC5335P
•
:.
MEMORY SELECTION GU1D£3
~R~8IT
1 Bit
4 Bit
8 Bit
j--WORD
TC5501P/D
256
TMM314AP
1,024
TC5508P
TC5514P/AP
TC5047AP
TC5513AP/AD
2,048
TMM2016P/D
TC5516AP/AD/AF
TC5517 AP/AD/AF
TC55178P/8D/8F
TC551BBP/8D/8F
TMM323DiDI
TMM334P
4,096
TMM2732D/OI
TC5332P
TC5333P
TC5334P
TC5335P
TMM333P
TMM2332P
J>
TC5504AP
TMM315D
TMM2764D
TMM2364P
TC5564P
TC5565P
8.192
16,384
TMM416P/O
TMM23256P
32.76B
65,536
TMM4164P/C
co
•
.'!:::
10'"
"'~
."
'"
~
~
MROM (TMM23266)
~ .; .;
c
.;
I~
.; I~
~
II:
U
w
.;
I~
Ii
MROM (TMM2364)
li
~
.; I~
I~
EPROM (TMM2764)
~ I~
q
.;
I~
I~
"
~
.;
I~
I~
CMOS MROM (TC6333)
iii
<
CRAM (TC5564/65)
i1i
~
.(
N
z
CMOS MROM (TC5332)
.; I~
~I~
MROM (TMM2332)
.;
If!
~
'"
M
~
I:::I
o
z
CRAM (TC6617)
~
CRAM (TC6516/18)
~
a:
Ii
SRAM (TMM2016)
I~
I~
MROM (TMM334)
J;
u
~
a::
>
a:
o
~
EPROM (TMM323)
< .; :!
~
C IS c
C
c
...
10
I~
I~
I~
I~
If!
l§
§
I~ < f ~
c
0
.....,.....,,:...,.....,.....,.....,.....,.....,,-2; ..............
::E
w
::E
w
'"'" '" '" C;;'"
-T
10
~
Q
~
w
~
fi
~
...
<
.(
.(
;t
N
~
§:
M
~
~
~
'"'"
~
§
N
e;;::
§
'" ... '"
!il ~ !!!
iii ;::: iii in
:: :: :: ::
E §: §:
-
;:
< <
~
0
C
,....,,....,,...,
~
;
g -
-'"
-
C;;
::
N
::
:!:
C>
M
CI>
'"
M
L...IL..JL...IL..J==-L...IL..JL...IL..JL...IL...IL...I~
I-
~
EPROM (TMM323)
:i
i
a:
iii
~
I~
- -.
.; I~~
EPROM (TMM2732)
~
~
10
~
<
~
.(
.[
.(
N
C 0
~
MROM (TMM334)
iii
~
SRAM (TMM2016)
~
CRAM (TC5516/18)
CRAM (TC5517)
EPROM (TMM2732)
~
iii
MROM (TMM2332)
~
t:l
CMOS MROM (TC5332)
CMOS MROM (TC5333)
EPROM (TMM2764)
~
iii
~
MROM (TMM2364)
i1i
.
>
q
z
CRAM (TC6564/65)
co
.1:::
ID'"
"'~
MROM (TMM23266)
N
.;
q
z
.
.;
-
7 -
<-
.; .t C 0
C
IS
z
CI
CROSS REFERENCE
1. 16 K Bit Dynamic RAM
====
Access Time
150n.
TMM416D·2/p·2
Toshiba
2OOn.
TMM416D·3/P-3
F16K·2
MB8116H
HM4716A·2
2117·2
Fairchild
Fujitsu
Hitachi
Intal
Intenil
F16K·3
MB8116E
HM4716A·3
2117-3
IM7116·3
M5K4116·3
MK4116-3
MCM4116C-3
MM5290·3
IlPD416C/D·2
TMS4116·20
M5K4116·2
MK4116·2
MCM4116C-2
NM5290·2
IlPD416C/D·3
TMS4116·15
Mitsubi.hi
Mostak
Motorola
National Semi.
NEC
TI
250n.
TMM416D-4/P-4
F16K4
MB8116N
HM4716A4
21174
IM71164
M5K41164
MK41164
MCM4116C4
IlPD416C/D·1
TM4116-25
2. 64 K Bit Dynamic RAM.
120m
TMM4164P·2
Toshiba
150 no
TMM4164P/C-3
MB8264-15
HM4864-2
2164-15
M5K4164N·15
MCM6665-15
Il PD4164-3
MSM3764·15
TMS4164-15
Fujitsu
Hitachi
Intol
Mlt.ubi.hl
Motorolo
NEC
OKI
TI
3.
M5M3764·12
200ns
TMM4164P/C-4
MB8264-20
HM4864·3
2164·20
M5K4164N·20
MCM6665·20
IlPD41 64-2
MSM3764·20
TMS4164·20
4K BitSbtic RAM
~.. Timo
Toshiba
AMD
AMI
Fujitsu
Hitachi
Intal
Inbroll
Mitsubi.hi
Motorola
National
NEe
SYNERTEK
TI
200 no
TMM314AP·l/APL·l
Am9114EPC
52114·2
MB8114EL
HM472114AP·2
2114-2/L2
IM7114·2/L2
M5L2114LP,S·2
MCM2114·20
MM2114·2/-2L
IlPD2114LC/D-3
1,024 x 4
300m
TMM314AP·3/APL·3
Am9114CPC
52114·3
MB8114NL
HM472114AP-3
2114·3/L3
TMM314AP/APL
4,096 xl
55 n.
70n.
TMM315D·l
TMM315D
Am9114BPC
M5L2114LP, 5-3
MCM2114-30
MM2114·3/-3L
IlPD2114LC/D-1
TMS4045·20
-
450 no
8 -
MB8147H
HM6147-3
2147-3
HM472114AP4
2114/L
IM7114L
M5L2114LP, S
MCM211445
MM2114/-L
IlPD2114LC/D
MCM2147-55
MM2147·3
IlPD2147D·3
TMS404545
TM52147-5
S2147
MB8147E
HM6147
2147
MCM2147·70
MM2147
IlPD2147D·2
SY2147
TM52147·7
•
4.
1K/4K Bit CMOS RAM
1 K Bit
Toshiba
Fujitsu
Harris
Hitachi
Intel
Intersil
Mitsubilhi
NEC
Oki
RCA
5.
256x4
TC5501P
TC5501D
HM6501
HM435101
15101L
4K Bit
1,024 x4
TC5514P
TC5514APITC5513A
4,096 x 1
TC5604P
TC5504AP
MB8401
HM6508
MB8414
HM6514
HM4334
MBB404
HM6504
HM4315
IM6508
IM6514
M58981S45
"PD444
MSM5114
MWS5114
IM6504
1.024 xl
l,024x4
TC5508P
TC5047AP
M5L5101p·1
"PD5101
¢'D445
"P0443
MSM5104
16 K Bit NMOS/CMOS Static RAM
16 K Bit
Toshiba
Fujitsu
Hitachi
Mitsubilhi
NEC
OKI
6.
NMOS
T)IIIM2016P
TC5516AP
MB8128
(HM6116)
M58725
1'1'04016
MSM2128
CMOS
TC5517APIBP
TC5518BP
MB8417
TM8416
(HM6116)
MB8418
(HM6117)
"PD447
MSM5127
"P0446
MSM5128
"PD449
MSM5129
ROM (EPROM & MROM)
EPROM
Toshiba
Fujitsu
Hitachi
Intel
Mitsubilhi
Mostek
Motorola
NEC
Oki
TI
16 K Bit
32 K Bit
TMM323D
TMM2732D
M88516
HN462716
i2716
M5L2716K
MK4716
MCM2716
"PD2716D
MSM2716AS
TMS2516
MB8532
HN462732
12732
M5L2732K
64 K Bit
TMM2764D
MB2764
HN482764
12764
MROM
32K Bit
TMM333P
TMM2332P
HN46332P
i2332
MK32000
"PD2732D
MSM2732AS
¢'D2332
MSM2764AS
TMS4732
-
9 -
64KBit
TMM2364P
i2364
MK37000
-llh~' ,
Dynamic Random _Access Memories
-
11 -
TMM416P/D-2, TMM4I 6P/D-3,
TMM416P/D-4
16384 WORD x 1 BIT DYNAMIC RAM
N CHANNEL SILICON GATE MOS
The TMM416P/D IS a 16,384 words by 1 bit MOS
random access memory circUit fabricated with
TOSH I BA 's double poly N-channel sll Icon gate process for high performance and high functional density.
The TMM416P/D uses a single transistor dynamic
storage cell and dynamic control circuitry to achieve
high speed and low power dissipation Multiplexed
address Inputs permit the TMM416P/D to be packaged In a standard 16 pin plastiC and cerdlp DIP ThiS
package size provides high system bit densities and IS
compatible with widely available automatic testing
• 16,384 words by 1 bit organization
• Fast access time and cycle time
• Output unlatched at cycle end allows two-dimensional chip select
• Common I/O capability uSing "Early Write" opera-
DEVICE
~416P/D-2
TMM416P/D-3
TMM416P/D4
tRAC
tRc
150 ns
200 ns
250 ns
320 ns
375 ns
410 ns
tion
• Read-ModlfyWrlte, RAS-only refresh, and PageMode capability
• All Inputs and output TT L compatible
• 128 refresh cycles / 2 msec
• Compatible with MK4116
• Industry standard 16 pin DIP
• Standard ± 10% power supply (+12V, ± 5V)
• Lower power 462mW ope rat Ing (max)
20mW standby (max)
(TOP VIEW)
VSS
and insertion equipment
• Package
PlastiC
Cerdlp
DIp· TMM416P
DIP. TMM416D
BLOCK QIAGftAM
CAS
DOUT
A,
WRfTEo-------;:::::::~--~~=>
A3
t>INNAMES
AO-A6
Address Inputs
CAS
Column Address Strobe
D,N
Data In
°OUT
Data Out
RAS
Row Address Strobe
WAITE
ReadlWnte Input
VBB
Power (-5V)
VCC
Power (+5V)
VDD
Power (+12V)
VSS
Ground
-
13 -
I
RATING
VALUE
UNITS
NOTES
~
-05'"" +20
VV
1
t---CVC:o--Cl-ta-'g-e-o-nc-Vc-o~o~,~Vc-e-e-s-u-p--cPlc-le-s~re"'la~t-,v-e-t-~C-vc-,,-s~~--~-~~t--~-_-;-1-=0-_~+CC15:----t-~~':-:-~--- --1-"~
Voltage on any Pin relative to VBS
"-~~~-
VBB'VSS (Voo,Vss>OVI
r-----'-:-I/,-~-i~~-=-l~~--I
0
--.----"-- ---- -~-0 -70
r-~,,-;°c:Cc-,,_~t--~~l:-~--I
- - -- - - - - -----=55 "':"'50- °C
1
~;;;t;~T;'m-;---~ - - ~~ ~~ 260-16--~;;c - - ---- , - - Operating temperature
Storage temperature
I
TMM416P
I
TMM416D
Power diSSipation
I
--==1I
n~600
-
---
-----~
mW
1
mA'- - - - , -
10:
I'
Short Circuit output current
_
__-'--_ _-'
(Ta = 0 - 70°C) (Note 21
SYMBOL
PARAMETER
MIN
Voo
Vee
Supply Voltage
MAX
TYP
UNITS
120
132
V
3
45
50
55
V
3,4
3
Vss
0
0
0
V
VBB
-45
-50
-55
V
27
70
V
24
70
V
-10
08
V
VIHe
Input High Voltage, RAS, CAS, WRITE
VIH
Input High Voltage, except RAS, CAS, WR ITE
VIL
Input Low Voltage, all Inputs
I
NOTES
108
3
I
3
3
i
3
i
(Voo = 12,OV ± 10%, Vee = 5,OV± 10%, Vss = OV, VBB = -5,OV± 10%, Ta = O°C -70°CI (Note 21
--,SYMBOL
,-,--,~--
MIN,
PARAMETER
MAX,
UNITS
NOTES
35
mA
5
200
15
JlA
mA
10
JlA
100
27
JlA
mA
10
JlA
200
27
JlA
mA
200
JlA
-10
10
JlA
-10
10
JlA
,~~~---.
loot
OPERATING CURRENT
lecl
Average power supply operating current
6
-~-
minim~m value)
IBBI
(RAS, CAS cycling
1002
STANDBY CURRENT
ICC2
Power supply standby current
tRC
0:=
-10
C----'
IBB2
(RAS = VIHC, 00UT = High Impedancel
1003
REFRESH CURRENT
ICC3
Average power supply current, refresh mode.
IBB3
1004
(RAS cycling, CAS = VIHC
PAGE-MOOTcURFfENT
ICC4
Average power supply current, page mode operation
IBB4
(RAS = VIL, CAS cycling
,~-----,
-10
tRC = minimum value)
f----
----~~
I
tpc = minimum value)
-I
5
5
6
INPIH LEAKAGE CURRENT
IIILI
Input leakage current, any input (Vs B = -5V
I
OV';; VIN .;; +7 OV, all other pins not under test = OVI
OUTPUT LEAKAGE CURRENT
10 ILl
VOH
VOL
(DOUT
IS
disabled, OV';; VOUT';; +5,5VI
OUTPUT LEVELS
24
Output "Hit level voltage !lOUT =-5mAI
OUTPUT LEVELS
OA
Output "L" level voltage (lOUT =4.2mAI
-
14 -
i
I
V
4
V
4
•
. EWECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(VOO
= 12 OV± 10%,
SYMBOL
Vcc
= 5.0V± 10%, Vss = OV, VBB = -5 OV± 10%, Ta = O'C -70'CI
TMM416P/D-2
PARAMETER
MIN.
MAX
TMM416P/D-3
TMM416P/D-4
MIN
MIN_
UNITS
NOTES
410
ns
9
425
ns
9
405
500
ns
9
225
275
ns
Random read or write cycle time
320
375
tRwC
Read-write cycle time
320
375
tRMW
Read-modify-write cycle time
320
tpc
Page mode cycle time
170
~c
(NOTES 2, 7,8,101
MAX,
MAX
tRAC
Access time from RAS
150
200
250
ns
11,13
tCAC
Access time from CAS
100
135
165
ns
12,13
tOFF
Output buffer turn-off delay
tT
Transition time (rise and fall)
tRP
RAS precharge time
100
tRAS
RAS pulse width
150
tRSH
RAS hold time
100
135
165
tCSH
CAS hold time
150
200
250
teAs
CAS pulse width
100
10,000
135
10,000
165
10,000
ns
tRCO
RAS to CAS delay time
20
50
25
65
35
85
ns
teRP
CAS to RAS precharge time
tASR
Row Address set-up time
tRAH
Row Address hold time
tASC
Column Address set-up time
teAH
Column Address hold time
tWCH
tWCR
~
Read command hold time
-.--.
__.__. _ - - - - - - - - -
Wnte command hold time
Write command hold time
--
referenced to RAS
twp
Write command pulse wIdth
tRWL
Wrtte command to RAS lead tIme
tewL
Wrtte command to CAS lead time
tos
Data~in
tOH
tOHR
tcp
tREF
0
50
0
60
ns
14
35
3
50
3
50
ns
10
120
32,000
200
150
32,000
-20
0
--_.-
Read command set-up time
-
40
-20
referenced to RAS
tRCS
tRCH
3
Column Address hold time
tAR
--------
- - f---~- ---
-,.. --
25
32,000
1-------
ns
ns
ns
-20
0
20
250
ns
0
ns
35
ns
-10
ns
-10
-10
45
55
75
ns
95
120
160
ns
0
0
0
ns
0
l--.,j-5
0
0
ns
55
75
ns
95
120
160
ns
I--~
55
1--~5
ns
----
50
f----- f-50
~b- f-----
15
ns
85
ns
70
85
ns
0
0
0
ns
16
Data-m hold tIme
45
55
75
ns
16
Data-In hold time referenced to RAS
95
set-up tIme
CAS precharge time (for pagemode cycle only)
--
60
120
160
80
100
2
Refresh penod
2
ns
-
ns
2
ms
twcs
Wnte command set-up tIme
-20
-20
-20
ns
17
tewo
CAS to WR ITE delay
60
80
90
ns
17
tRWD
RAS to WR ITE delay
110
145
175
ns
17
-
15 --
• READ CYCLE
'RC
tRAS
ADDRESSES
-----------------------OPEN--------------~
VALID DATA
@oon'tcare
• WRITE CYCLE (EARLY WRITE)
'RC
tRAS
ADDRESSES
WRiTE
DOUT
VtHC
-------------------------------------OPEN
-
16 -
•
READ-WRITE/READ-MODIFY-WRITE CYCLE
I
ADDRESSES
VIHC-
V'C -----r---....J
DOUT
DIN
~
•
Don'teare
"RAS-ONLY" REFRESH CYCLE
ADDRESSES
VOH-
VOC
OPEN - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ __
----------------
~
Note
CAS = VrHC. WRITE = Don'teare
-
17 -
Don't Care
•
PAGE MODE READ CYCLE
V,H
ADDRESSES
V IL
DOUT
WRITE
[ZJ Don't Care
•
PAGE MODE WRITE CYCLE
ADDRESSES
VIH
V,L
-
18 -
..
;~
:~.
,
"
,< ::,: . ' •
/
IVoo = 12,OV± 10%, Vee = 5 OV± 10%, VSS = OV, Vss = -5 OV± 10%, f = 1MHz, Ta =O·C - 70·C)
SYMBOL
CI I
CI,
Co
PARAMETER
Input Capacitance IAo·A.), D,N
Input Capacitance RAS, CAS, WRITE
Output Capacitance IDo UT)
70
!
;
!
TYP,
4
B
5
f--Y,-
~
,
"H-+++-1H-+1'+-H
,.
7
~
.~,<
I-W,~~
"
~~v'l-'
~" I/f
~
/
~ ....
I
/
,
CyeIIR ... {MH.I-IOl/tRC enol
FOI'
10
T . . . . . RC
"
UNIT
pF
pF
pF
. _, .
"
f-+-
T. (MnJ
MAX.
5
"
"
Cvcl.PI... ,toIIH.'_10S"'IIC ''''''
F.3
'lie"
..
IDDa
Cycl.T''''· ... C'ItO,
I
.,
C .... I.II_'MH.'·,0 3ftpC
C,_R. . It,lH<1 * 1000ltRC {n ••
Fig" "'CVIIIDO ..
F,,2 'Re'" '00'
NOTES
1 5trs_s greater than those listed under "Absolute Maximum Ra·
tlngs" may cause permanent damage to the device
2
TillS spaclfled her. for operation at frequencies to
tRC
tAC (min) Operation at higher cycle rates With reduced
amb.ent temperatures and higher power dlss'patlon .1 perml'l,ble,
however, prOVided AC operating paramatefs are met Se. Fig 1
for decatlRg curve
3
4
11
>
All lIolta"" are raferenced to VSS
12
13
14
Output voltage Will SWInD from VSS to Vee when activated With
no currant !oadlng For purposes of mamtalnlng data
In
standby
mode, Vee may be reduced to VSS Without affecting refresh
operations or data retention However, the VOH (min) specification IS not guaranteed In thll mode
5 1001, 1003 and 1004 depend on cycle rate See figures 2,3 and
4 for 100 limits at other cycle rates
6 ICC1 and ICC4 depend upon output loading DUring readout of
high level data VCC IS connected through a low Impedance to data
_ out At all other times ICC consists of leakage currents only
7 After the appllcatton of supply voltages or after extended periods
of btas (greater than tRE F 2ms) Without clocks, the davlca must
parlorm about eight tnlttahzatlon cycles prior to normal operation
B AC measuraments aHuma tT .. 6ns
9 The specifications for tRC (min ), tRMW (min I and tRWC (min I
16
16
17
If twcs ~ twcs (min " the cycle IS an .. rly Write cycle and the
data out pin WIll remain open CirCUit (high Impedance) throustlout
the entire cycle
'
If tcwo ~ tcwo (m,n I and tRWO ~tRWO (min I, the cycle IS a
read-wrr'l8 cycle and the data out Will contllln date reed from the
lelectad cell If neither of the above ..ts of conditions IS Ntlsflad,
the condition of the data out (at acc... time) IS indeterminate
:~er:: f~I~I:e,:~~~~c;.~a~:170 ~~~: <~~~~r~Pa:su~aratlon
10
measuring timing of Input ligna II Also, transition times ara m .. surad between VIHC or VIH and VIL
Assumel that tRCO ~tRCO (max I If tRCO IS greater than the
maximum recommended value shown In thIS tabla, tRAC Will Incr.... by the amount that tRCO exceeds the value Ihown
Anum.. that tRCO ~tRCO (max I
Measured With a load equIValent to 2 TTL loads and 100pF
tOFF (max) defln .. the time at which the output achieves the
open CirCUit condition and IS not referenced to output voltage
levell
Operation Within the tRCO (max) limit lna"'81 that tRAC (max)
can be mat tRCO (max) II specified a reference pOint only If
tRCO IS greater than the Ipeclfled tRCO (max I limit, then acc...
time IS controlled exclUSIvely by tCAC
The.. parameterl are referenced to CAS leading edge In early wrrte
cycles and to WRITE leading edge In delayed wrtte or readmodifY-Write cycles
twcs, tcwo and tRWO are not restrictive operating parameters
They are Included In the data Sheet al electrical ch.rl8Ctertltlcs
only
VIHC (min) or VIH (min) and VIL (max I are referenceleVals for
19 -
ADDRESSING
The 14 address bits required to decode 1 of the
16,384 cell locations within the TMM416P/D are
multiplexed onto the 7 address inputs and latched
into the on-chip address latches by externally applyIng two negative going TTL-level clocks
The first clock, the Row Address Strobe (RAS),
latches the 7 row address bits into the chip. The
second clock, the Column Address Strobe (CAS),
subsequently latches the 7 column address bits into
the chip. Each of these signals, RAS and CAS, triggers a sequence of events which are controlled by different delayed internal clocks.
The two clock chains are linked together logically
in such a way that the address multiplexing operation
is done outside of the critical path timing sequence
for read data access. The later events in the CAS
clock sequence are inhibited until the occurence of a
delayed signal derived from the RAS clock chain.
This "gated CAS" feature allows the CAS clock to be
externally activated as soon as the Row Address Hold
Time specification (tRAH) has been satisfied and the
address inputs have been changed from Row address
to Column address information.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched
into an on-chip register by a combination of WR ITE
and CAS whi Ie RAS is active. The later of the signals
(WRITE or CAS) to make its negative transition is the
strobe for the Data In (DIN) register. This permits
several options in the write cycle timing In a write
cycle, if the WR ITE input is brought low (active)
prior to CAS, the DI N IS strobed by CAS and the setup and hold times are referenced to CAS. If the
input data is not available at CAS time or If it IS
desired that the cycle be a read-write cycle the
WRITE signal will be delayed until after CAS has
made its negative transition. In this "delayed write
cycle" the data input set-up and hold times are
referenced to the negative edge of WR ITE rather than
CAS. (To illustrate thiS feature, DI N IS referenced to
WRITE in the timing diagrams depicting the readwrite and page-mode write cycles while the "early
write" cycle diagram shows DI N referenced to CAS).
Data is retrieved from the memory in a read cycle
by maintaining WRITE in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.
DATA OUTP!JT CONTROL
The normal condition of the Data Output (DOUT)
of the TMM416P/D is the high Impedance (opencirCUit) state. That is to say, anytime CAS IS at a high
level, the Do UT pin will be floating. The only time
the output will turn on and contain either a logic 0 or
logic 1 is at access time during a read cycle. DOUT
will remain valid from access time until CAS is taken
back to the inactive (high level) condition.
If the memory cycle in progress is a read, readmodify write, or a delayed write cycle, then the data
output Will go from the high impedance state to the
active condition, and at access time Will contain the
data read from the selected cell. This output data is
the same polaroty (not inverted) as the onput data.
Once having gone active, the output will remain valid
until CAS IS taken to the precharge (logic 1) state,
whether or not RAS goes onto precharge.
If the cycle in progress is an "early-wrote" cycle
(WRITE active before CAS goes active), then the
output pin will maontain the high impedance state
throughout the entire cycle. Note that With this type
of output configuration, the user is given full control
of the DOUT pin simply by controlling the placement
of WRITE command during a write cycle, and the
pulse width of the Column Address Strobe during
read operations. Note also that even though data IS
not latched at the output, data can remal n valid from
access time until the beginning of a subsequent cycle
without paYing any penalty in overall memory cycle
time (stretching the cycle).
PAGE MODE OPERATION
The '''age-Mode'' feature of the TMM416P/D allows for successive memory operations at mu Itlple column locations of the same row address With increased
speed Without an increase in power. ThiS IS done by
- 20 -
rent waveforms in Fig, 5) In system applications
requiring lower power diSSipation, the operating
frequency (cycle rate) of the TMM416P/D can be reduced and the (guaranteed maximum) average power
dissipation of the device will be lowered in accordance With the 1001 (max,) spec limit curve Illustrated
in Fig, 2,
It IS pOSSible to operate certain versions of the
TMM416P/D family (-2 and 3 speed selections for
example) at frequencies higher than specified, provided all AC operating parameters are met, Operation at
shorter cycle times « tRC mm,) results in higher
power dissipation and, therefore, a reduction in
ambient temperature is required, Refer to Fig 1 for
deratmg curve,
strobing the rfYoN address into the chip and mamtalnmg the RAS signal at a logic 0 throughout all successive memory cycles in which the rfYoN address IS common, ThiS "page-mode" of operation Will not diSsipate the power associated with the negative gomg
edge of RAS Also, the time required for strobing in
a new rfYoN addre-;s is elimmated, thereby decreasing
the access and cycle times
REFRESH
Refresh of the dynamiC cell matnx IS accomplished
by perform mg a memory cycle at each of the 128
row addresses Within each 2 millisecond time mterval
Although any normal memory cycle Will perform the
refresh operation, thiS function IS most easily accomplished with "RAS-only" cycles, RAS only refresh
results in a substantial reduction m operatmg power,
ThiS reduction in power IS reflected m the 1003
specification
POWER UP
The TMM416P/D reqUires no particular power supply sequencmg so long as the Absolute Maximum
Rating Conditions are observed, However, in order to
insure complianoe With the Absolute Maximum RatIngs, TOSHIBA recommends sequencing of power
supplies such that VBB IS applied first and removed
last, VBB should never be more positive than Vss
when power IS applied to Vo 0,
POWER CONSIDERATIONS
Most of the CIrCUitry used m the TMM416P/D IS
dynamiC and most of the power drawn IS the result of
an address strobe edge (refer to the TMM416P/D cur-
LONG
FiAJ/CDCVCLE
iiiA"S/C"'Ai CYCLE
IiiAI ONLY CYCLE
I
I I
I I
'--
VOO"U2V
v•• .. ~5V
T. . . HOC
0
'cc
0
'"
0
ImA)
IAI
II I'
~
0
(mA)
0
IlL
AI\
I
I\r.
lJl\1
\I,
V
WI
/I
.~
11J\
'\
\i
A
1\
1111
0
o-
111ll
,
\,
j
A
'"
J
1'-,
t--
0
(mA)
NI\
AIl
) U'
-c-
f-
1/
n
Ai II
lJIl
11
.. .
f'-
A
,L'~
""l- i-" v
IKI ... /DM ......
- 21 -
I'
I~U
I-~
Ii
ll\
.I'- 1-1-'
I
Nor....Uzed Ac:gal Tim. tRAC
Norm.llzed Acc." Tim. 'RAC
No.m.nted Ace... Tim. tRAC
'" VOO Supply Vol~
"'Vee Supp,y Vo't.""
",VCCSupplyVolt.""
Tj -50"(:
Vee (V)
Voo (v)
No......llnd A _ TI ....
1001 (Ave ••",,)
",TjJl,lncdon T .... p4I. . tur.
.... Voo Supply Vola,.
1001 (Av...",,)
v.TjJunc:tlonT ..... _.,u..
VOO·,32V
Vee- """ISV
,
.
.
VCC (V)
/
V
V
Vee _45V
tRC-315nl
tRC _315n.
_l--
..
"
V
TJ- 50"(:
n •
"
Voo (V)
(RAS Only)
1002 (Sundby)
1002 (St.ndby)
'003
'" VOO SUpply Volt.
.... T] JunctlonTemp41'-"u"
.... voo Supply Volt.""
VeB---45V
Vea - ...... BV
Tj_ISOOC
VOO _132V
'RC-315no
---
_f--Voo
(VI
--voo
- 22 -
(VI
•
1003 (RAS Only)
vs T J Junct,onTlmplriltUre
1004 (PIp Modlj
1004 (PIgI Modi)
... T, JunCt,DnTlrnp...lturl
vi Voe Supply Valtlp
VSS--4!1V
VSS--4SV
VOO ~ 13 2V
Tj-!lO"C
Veo- 132V
tRC - 375n_
tpc-22Snl
tpc-22Snl
Vaa - --4SV
_I--r-
"
Veo (V)
VIHC.VllC Input l....r.
VIH VIL Input l._11
VIHC. VILC Input LlvII,
... VOO Supply VDltllp
VSVoo Supply Valt.ge
... VSsSupplyValt_
I
I
I
J
t---t---t---\
"
Vaa - -6 !IV far VIH
VSS - -5 SV for VIHC
I
~
Vas - --4 !IV for VILC
VSS
T J -50"C
T.-5D"C
Voo
(V)
Veo
Veo - 13 2V for VIHC
-4 !IV for VIL
VOO-10aVfarVllC
T."!IO"C
(V)
Vss
Iv)
VIH,VII..lnputl..lYel5
VIHC. VIl.C Input 1..1l1li,
VIH,VII.. Input LIYIII
vs VSS Supp.ly VDtllP
vs T J JuncttanTln'lperaturl
... Tj Junction Tln'lpentu..
I
r Voo - 13 2V for VIH
VOO-10aVf«vll
T,-IIO"c
I--
Vee" 13 2V, Vas - -5 5V for VIHC
Voo" 10 av, Vaa" --4 Sv for VILC
V9S (V)
-
23 -
1
J
>
i
>
-
Voo .. 13 2V, VS8" -5 IIV for VIH
VOO" 10 av, Vas" -4 5V far VIL
I
_laSHISA
OUTtJNE DRAWINGS
•
Plastic Package
16
15
14
13
12
11
10
Unit
9
In
mm
tt:~~:~:)
12345678
199 MAX
762±025ao
~
o
~
a
+01
1 4±O 15
i--2 54±O 25
•
Cerdip Package
I
.~.
025-005
762-aaO
O
I
.
o !liD 15
[:::::}1
IY Y
Y
4
5
6
,
81
L-200MAX
046±015
Note
Note:
© Feb.,
1
Each lead pitch IS 2 54mm
All leads are located Wlthm o 25mm of their true longitudinal POSition with re5pe<;t to No
2
No 161ead$
All dlmen',,;.ns are In millimeters
Toshiba does not assume any responsibility for use of any circuitry described, no circuit patent license. are implied. and Toshiba reserve.
the right. 81 any time without notice, to change said circuitry.
1981 Toshiba Corporation
- 24 -
TOSIIBA MOS MEMORY PRODUCTS
TMM4164C-3
TMM4164C-4
65,536 WORD X 1 BIT DYNAMIC RAM
N<:HANNEL SILICON GATE MOS
Multiplexed address Inputs permit the TMM4164C
to be packaged In a standard 16 pin ceramic DIP
ThiS package size prOVides high system bit denSities
and IS compatible With Widely available automated
testing and insertion equipment
System oriented features Single power supply of 5V
Include ± 10% tolerance, direct interfacing capability
With high performance logiC families such as Schottky
DESCRIPTION
The TMM4164C IS the new generation dynamiC
RAM organized 65,536 words by 1 bit, It IS successor
to the Industry standard TMM416D/P
The TMM4164C utilizes TOSHIBA's double poly
N-channel Silicon gate process technology as well as
advanced circuit techniques to provide Wide operating
margins, both Internally and to the system user
TTL
FEATURES
• 65,536 words by 1 bit organization
• Industry standard 16 Pin ceramic DIP
• Output unlatched at cycle end allows two-dlmenslonal chip selection
• Common I/O capability uSing "EARLY WRITE"
operation
• Read-Modlfy-Wrlte, RAS-only refresh and Page
Mode capability
• All Inputs and output TTL compatible
• 128 refresh cycles/2ms
V BB generator
• Low power, 275mWoperating (MAX)
, 27 5mW standby (MAX)
PIN CONNECTION
(TOP VIEW)
BLOCK DIAGRAM
NC
------0
Vss
CAS
D,N
WRITE
DOUT
A.
A3
RAS
A.
A,
A,
Vee
A.
As
A,
A,
=---:::::=
A,
A,
A,
A.
A,
- - No'::: C'--o-nn-e-ct-,-o-n---------1
A,
A,
PIN NAMES
r--Ac;-.-c_-Ac;-,-~-A~dC;-d:'-r-ess--1 npu·":-------------- - I---=CA:..=.S_ _+_C=-o=-I_"um=n.:.A____d:.=-dress Strobe _~-_
Data In
D,N
r----NC-
~~---+~~~~==~-------------
__ ~~: ~~-~-re-ss-S-trObe--
r-%~~T
----
-
~~TE
ReadIWnte Input
I ~:
~~:-U-~-'-d(,--+-5-V-,--)- - - - - - - - - - - - - 1
-
25 -
Vee
I
ITEM
SYMBOL
Input and Output Voltage
RATING
UNITS
NOTES
VIN.VOUT
-1-7
V
1
-1-7
V
·C
1
Operating Temperature
VCC
T OPA
Storage Temperature
TSTG
-55-150
·C
1
TSOLDEA
260 . 10
1
Po
1
°C . sec
W
lOUT
50
mA
1
Power Supply Voltage
-,
Soldering Temperature· Time
Power Dissipation
Short Circuit Output Current
SYMBOL
PARAMETER
0-70
MIN.
MAX,
UNITS
NOTES
50
55
V
2
24
65
V
2
-10
08
V
2
Supply Voltage
45
VIH
Input High Voltage
VIL
Input Low Voltage
·,.ftI..:(Vee
SYMBOL
Icc.
Icc.
= 5V ± 10%" Ta = 0 - 70·CI
PARAMETER
MIN
OPERATING CURRENT
Average Power Supply Operating Current
(RAS, CAS Cycling tAC =tAC MIN
STANDBY CURRENT
Power Supply Standby Current
(RAS = VIH. DoUT = High Impedance)
TYP
MAX
UNITS
NOTES
50
mA
3.4
5
mA
mA
3
mA
3.4
ICC,
REFRESH CURRENT
Average Power Supply Current. Refresh Mode
(RAS Cycling, CAS = VIH tAC =tAC MIN
40
Icc.
PAGE MODE CURRENT
Average Power Supply Current. Page Mode
(RAS = VIL. CAS Cycling tpc =tpc MIN
40
II III
INPUT LEAKAGE CURRENT
Input Leakage Current, any Input (OV ~ VIN
All Other PinS Not Under Test = OV)
VOH
OUTPUT LEAKAGE CURRENT
(DoUT IS disabled. OV ~ VOUT ::;; +5 5V)
OUTPUT LEVEL
Output "H" Level Voltage (lOUT = -5mA)
VOL
OUTPUT LEVEL
Output "L" Level Voltage (lOUT = 4 2mA)
10 ILl
1
TYP.
Vcc
jilQ\ll.m*~~'."t".~.~--~'CI-
1
---
~ 6 5V.
-10
10
Il A
-10
10
Il A
V
24
04
-
26 -
V
." '"y
;.
.
•.
'
~'
ELE~lU~:A(..~RtstIC8ANO "~&QPiftATI_.~
(Vee =5V ± 10%, Ta =0 - 70"C) (Notes 5, 6, 7)
SYMBOL
TMM4164C·3
MIN
MAX
PARAMETER
TMM4164C4
MIN
MAX
UNITS
NOTES
~~tA~c~--~~R~an~d~o~m~R~ea~d~o~r~W~r~lt~e~C~y.,c~le~T~1~m~e______+-~3~2O~-+_______i---·3~~
ns
-------~~~+----~~
350
ns
405
ns
ns __~----~
225 __+-______+-~,~
~~~~--~--~Pa~g~e~M~o~d~e~C~y~c~le~T~I~m~e~------------~I--~l~7~0__+-______+-~~
150
200
ns
8,10
tRAC
Access Time from RAS
-I 100
tCAC
Access Time from CAS
ns
l~
-- - - - - - ~13~ ___
I 40
!oFF
Output Buffer Turn-Off Delay
,0
ns
0
50
11
ns
6
tT
TranSition Time (Rlse~an~d~F~a::':IJ,____________~3~-I!__ ....:::3~5__
.2.____ ...:50,-"----I__--"''--.....:
__--'''--_i
ns
~~_~R~A~S~Pr~e~ch~a~~~e~T~I~m~e'--------------~---l~oo--+_------~-l~2~0'--~------+_--~--~,------_i
tAAS
RAS Pulse Width
'150
10,000
200
10,000
ns
tAwc
tAMW
Read-Wnte Cycle Time
Read-ModlfY-Wnte Cycle Time
320
320
I,
-~--
r- ___
~t~A~s~H--+_~R~A~S~H~01~d~T~lm,.~e----------------_L__~10~0,-~----__+-~13~5,__
~t~e",s",H--+--;C:;.A;::S.-:H01.'! T~~e
~.:!te=!AS~--~-.:CA;.:::S..:PulseWldth
tACO
teAP
RAS to- CAS Delay TI";~CAS to RAS Precharge Time
_
LJ_50
10,000
50
,25
Row Address Hold Time
----?---+---
20
0
55
Column Address Hold Time
I
45
Column Address Hold Time
iI
95
120
o
0
Referenced to RAS
Read Command Set-Up.T,me
:::L ::::: ~::::~: ::'~~::-;':e-
I
\----
--t---____ _
__ "'--_-Ins
ns
ns
ns
ns
ns
o
9__ _
15
I' t~sc- - >-------c.;,u-mnAd~e1..:-U:.:p:::.T--,m-e----------r____o
tcAH
200
135 --l--~~OO
65
0
------r------=O- -
~.:..tAS~A'----I-__:.:R::ow::.:A::d~~d~re~s~s::Se~t..:-U::.'p::..:.T::.lm:::e:..._________ .;..__
tAAH
__
_~ _____ " __ 100
----t------
_ ___ +-~n~s___+-____~
-1-__ -"-'--
---
r-
I
12
ns
ns
-t-:-- ~ - :.:. -~- +- ----+-..;.-- :-----
~~tCW=L'---~--W:.:c":~te:..::Co-;;;;;;;;d"W"cAsL~-------+--'~-- -----tos
Data-In Set-UpTime
___ ~ 0 1---
~.:!to",-H'----I----D=at~a..:-I~n~H~o~ld:..:T!me---_--- ____ =_ _ .. ~5---t----tOHA
Data-In Hold Time Referenced to RAS
95
CAS Precharge Time (for Page Mode
tep
60
Cycle Only)
tAEF
RefreshPe"o.
:i:
->
......
a:
0
•
1. 5
I"
fil
N
Vee - B.DV
1
......
0.8
1.
•
0 ••
0.7
-20
20
40
60
80
100
•
120
2.
-20
40
6.
80
100
120
T. (Ocl
,.
10
Vee" 5.0V
V
\,:~
~~~
-<.• .,.~
.c.
..I
9
~
2~~
~ '/
4
Vee" B.DV
~
V
:r
9
~V
7
M
~
4
~
~
~
00
"
0.1
'0
~"
~
0.2
0.3
0.4
VOL
(v)
I
06
0.6
0.7
- 47 -
•
20
[""110
22
24
2.6
28
VOH
IV)
30
32
34
Unit In mm
"".
::!
22.8 MAX.
o
o
2.64±O.21
~
O.5±O.15
No_
each INd pItCh I. 2.54 mm. All I.... ara 10Clited within
0.25 mm of thalr 'trua longitudinal position with raspltCt to
No.1 and No.1 8 I..eIL
Nou: Tolhlbe dCMS not ...uma any responsibilitY for u. of any circuitry d..crlb.t; no circuit pet8nt
tha right. at .ny time without notice, to ch..,... Uld circuitry.
C)Mar., 1880 To.... b. Corporation
DI....lbuted by
- (8 -
IIc~...
a,. Impll.t. and Toshiba raterVel
TMM315D
TMM315D-1
4096 WORD x 1 BIT STATIC RAM
N CHANNEL SILICON GATE DEPLETION LOAD
.'1111
r
TMM315DfTMM315D-1 are 4096 word x 1 bit
read write memories operated with 5V single power
supply. The memories are static in operation and
require no clocks or refresh period. This device has
two types in data access - address access and chip
select access which are equal and very high speed.
When CS goes high, this device is deselected and
changes into the low power standby mode automatically, and keep its state during the period that CS is
high. Accordingly, this deVice is suitable for use in
larger memory system which the majority of devices
are deselected, and is suitable for use in cache memory required very high speed. TMM315DfTMM315D-1
are directly TTL compatible and its output can drive
the TTL up to 5. TMM315DfTMM315D-1 are fabncatea With N-channel silicon gate depletion load type
technology for stable and high performance. The
chip is mounted in the standard 18 pin package of 0.3
inch Width for low cost purpose.
•
•
•
•
•
• Current and Access time (Maximum value)
Fully decoded 4096 word x 1 bit organization
Static operation - No clocks
5V single power supply
Easy memory expansion - CS input
Standby feature - CS = V, H
• I/O separate
• Three state output
• Directly TTL compiltible
Vee Ad A7
18
Aa Ag
AIO All DIN
a
16
13
10
14
12
"
PARAMETER
TMM3150-1
TMM315D
Active Current (Max.)
lSOmA
l60mA
Standby Currant (Max.)
30mA
20mA
Address Access time
55n.
55ns
7001
Chip select Access time
Ao
AI
2
3
4
5
7
•
70nl
• Pin to pin compatible - i2147li2147-3
• Inputs protected - All inputs have protection
against static charge.
A2
A,
9
-Vee
Memory
-GND
CeI' Arrey
(64 x e.)
"-
As
D,N
Ao -As
At -All
Row Address inputs
Column Address inputs
DIN
DOUT
CS
Data input
Data output
Chip select input
WE
Write enable input
Vcc/GND
Power supply
C!I
Wi
- 49 -
DOUT
I
eS"
H
L
L
SYMBOL
Vee
VIN.OUT
Topr
.
High·lmpedance
Standby
H
Data out
Active
Oeselected
Read
L
High·lmpedance
Active
Write
WE
Output
ITEM
Power supply voltage
Input and output ""Itage
Operating temperature
Tstrg
Storage temperature
Tsolder
Soldering temperature· time
Po
Power dissipation (Ta = 70·C)
DC output current
lout
SYMBOL
Vil
PARAMETER
Input high voltage
Input low voltage
Vee
Power supply voltage
VIH
Power
CONDITIONS
-
MIN.
2.0
-
-10
Mode
RATING
-15-70
-1.5-7.0
0-70
-55-150
260 . 10
·C
°C . sec
1.0
20
W
mA
4.5
UNIT
V
V
DC
TYP.
MAX.
-
60
0.8
50
55
UNIT
V
V
V
~"'r_.~R""
Ta = 0 -70·C. Vee = 5.0V± 10%.unless otherwise noted
SYMBOL
VOH
VOL
IOH
IOl
III
PARAMETER
Output high voltage
Output low voltage
CONDITIONS
lsource = -4.0 mA
Isink =8 mA
MIN.
2.4
Output high current
Output low current
I nput leakage current
VOH =2.4V
VOL =0.4V
VIN eO-Vee
VOUT =0 -4.5V
CS=VIH orWE =Vll
TMM315D
CS = Vil
output open
-
ILO
Output leakage current
lee
Operating current
Isa
Standby current
Isap
Peak power on current
output open
TMM315D·l
TMM315D
TMM315D·l
CS" = VIH
TMM315D
during power on
TMM315D·l
CS-VIH
• Typical values are at Vee = 5.0V. Ta = 25DC.
-
50 -
TYP.
MAX.
-
-4.0
8.0
-
-
-
-
-
-
V
mA
mA
fO.Ol
flO
IlA
fO.l
f50
IlA
-
160
mA
180
mA
mA
-
0.4
UNIT
V
20
30
50
70
mA
mA
mA
Ta
= 0 -70°C,
•
READ CYCLE
Vee
=
5V± 10%,unless otherwise noted.
SYMBOL
TMM315D-1
PARAMETER
TMM315D
MIN.
MAX.
MIN.
MAX.
tAC
Read cycle time
55
-
70
-
tACC
Address access time
-
55
-
70
teal
Chip select access time 1
-
55
-
70
teo2
Chip select access time 2
-
65
-
80
-
5
-
5
10
-
10
-
0
40
0
40
Chip selection to power up time
0
-
-
30
0
Chip deselection to power down time
-
30
tOH
Output hold from address change
tLZ
Chip selection to output
tHZ
tpu
Chip deselection to output in high Z
tPD
•
WRITE CYCLE
I
SYMBOL
In
low Z
TMM315D-1
PARAMETER
TMM315D
MIN.
MAX
MIN.
MAX.
70
55
-
55
-
15
-
30
10
-
tWA
Write recovery time
10
tDS
Data set up time
25
tDH
Data hold time
10
-
tODw
Write enable to output in high Z
0
30
0
35
two
Output active from end of write
0
-
0
-
twc
Write cycle time
55
tcw
Chip selection to end of write
45
tAW
Address valid to end of write
45
tAS
Address set up time
twp
Write pulse width
0
35
0
40
• AC TEST CONDITIONS
I
I
Input pulse levels
0-3.5V
Input rise and fall times
10 ns
Input and output timing reference levels
1.5V
Output load
See Fig. 1
Fig.·1 Output load
SYMBOL
PARAMETER
CIN
Input capacitance
COUT
Output capacitance
rhis parameter is periodically sampled and is not 100% tested.
- 51 -
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
..
M~=: V'.;;c;-'Aco------~L=:
Do~
v'"
-.....
-~:]a-..:::=------
::
I--.~
... ----- - ""1
-y
,-----a
..
-
-t
-
D,.
...
'-
'l\'r
....-
.I±::::......-
...'":..t
X
YD'
Now. (1 J ~ . . to vel'" prior to or coinckMnt with eI trMlition low.
(2) teo': Chip It "'_ecWd for. time thet 'I grHte, th., ea n. prior to "Ktlan.
'cO2: Chip fI . . . . .-.d for • time th. 111_ th., &15 n. prior to ..teedon.
Unit In mm
7.1:1:0.21
Note. 1. lech ,.... pitch is 2.M mrn. All
,. . . arelQCII_ wl.... 1n 0.21 mm of
...., true longItudlnlll pOiltlon with
NIIPeCt to No.1 end No. '8 ....L
2. All dimension..... In mlll~
0.48:1:0.11'
Tolhilla doll. not ..... m .....y !'HPOnllbllity for u. of any circuitry d--=rlt.d; no circuit P8hM IlcIeMH .... Implied, ....d Tolhlbe ,...rvn the
rllht. aI.,y time without notice. to chen.. aid clrcl,lluy.
CAutI•• '880 TOIhIb. Corpcntlon
Note:
- 52 -
TMM2016P/0
TMM20 I 6P- I /0- I
TMM2016P-2/0-2
2048 WORD X 8 BIT STATIC RAM
N CHANNEL SILICON GATE DEPLETION LOAD
The TMM2016P/D IS a 16384-bit static random access memory organized as 2048-words by 8-bits and
operates from a single 5V power supply Common
8-blt mput/output, output enable (OE) and pin-compatibility with 2716 type EPROM (TMM323D) allow
a wide application in microprocessor peripheral
memory
In memory expanSion, low power application IS
pOSSible by usmg the chip select Input (CS). When CS
IS m V,H level, the device IS In low power standby
mode
TMM2016P/D IS fabricated With Ion Implanted Nchannel silicon gate technology Th.s technology provides high performance and high reliability. The
TMM2016P/D IS offered In both standard 24 Pin
plastic and cerdip packages, 0.6 Inch In Width.
• Pin compatible with 2716 type EPROM
• Smgle 5V supply - Vee ~ 5V ± 10%
• Output buffer control - OE
• Easy memory expansion - CS
• Static operation - No clock or timing strobe reqUired
• Directly TTL compatible - All inputs and outputs
• Common data mput and output
• Three state outputs - Wired OR capability
• Inputs protected - All inputs have protection
against static charge.
• Access t Ime and cu rrent
=.:::::::::::::
TMM2016P/D TMM2016P-l/0-1
TMM2016P..2JD~
Access lime (MAX I
150 ns
100 ns
200 ns
Operatlllg current (MAX)
l00mA
l20mA
l40mA
l5mA
l5mA
30mA
Standby current (MAX)
• Power down feature -
CS
"As
....,
As
,
.
2
3
~
;;
iiE
...
.'1"Au0:1 • g ,
."
10
'10:1
GND
11
"
',.
co
.",
.to,
.",
As
As
..
"As
',.
.-:::
:::
'--
" '/0,
13
IF
!
'100
~ ~
;:..;
NAME
SYMBOL
Ao- A 3
~f--
Column Address Inputs
A4- A lO
Row Address Inputs
es
Chip Select Input
WE
Write Enable Input
I/O, -1/08
Data Input/Output
OE
OutPut Enable Input
Vee
Power (5V)
GND
Ground
:o---fl::::=:
-=---- 53 -
"'mort
CellAr,."
+---0 Vee
+--oGNO
(12811: 18x81
11
./OQ-.
Co!umnOlcodef
~ ~~
~
f1~1. ~
f--
I
I
I
II
ITEM
SYMBOL
Vee
VIN. OUT
TOPA.
Operating Temperature
TSTG
Storage Temperature
TSOlDEA
PD
UNIT
RATING
--{J 5-70
Power Supply Voltage
Input and Output Voltage
--{J5-70
V
V
0-70
·C
-55 -150
·C
Soldering Temperature· Time
260 10
°c .sec
Power Oissipation ITa - 70·C)
10
W
~
SYMBOL
VIH
PARAMETER
Input High Voltage
Vil
I nput Low Voltage
Vee
Supply Voltage
~MBOL
MIN
TYP
22
-05
-
45
PARAMETER
Input Leakage Current
Y,N =0-55V
IOH
Output High Current
VOUT =24V
IOl
VOH
Output Low Current
Output High Voltage
VOUT =04V
lOUT = -lOrnA
VOL
Output Low Voltage
lOUT = 21rnA
IlO
Output Leakage Current
*Issp
Peak Power·on Current
IS8
Standby Current
Icc
Operating Current
• Not.
ICC ."~I ISS maximum during powe, on
50
CONDITIONS
III
CS = V IH or WE = V il or OE = VIH
UNIT
+ 10
V
08
V
55
V
MIN
TYP
MAX
UNIT
-
-
±10
p.A
-10
-
rnA
21
-
24
-
-
-
-
04
V
V
-
-
±10
p.A
-
-
30
45
rnA
rnA
-
-
15
rnA
-
30
rnA
VOUT =O-Vee
CS = Vee
lOUT =OrnA
dunng power on
TMM2016P/P-l/D/D-l
f--
TMM2q16P-2/D-2
CS = V IH
TMM2016P/P-l/D/D-l
lOUT =OrnA
TMM2016P-2/D-2
CS =Vll
TMM2016P-l/D-l
-
TMM2016P-2/D-2
-
TMM2016P/D
lOUT =OrnA
A pull-up ,,,Iatar to Vee on the
PARAMETER
CONDITIONS
Input Capacitance
VIN = A C Ground
Output Capacitance
VOUT = A C Ground
ThiS parameter II perlochcally sampled and .s not 100% tested
- 54 -
rnA
-
100
rnA
-
120
rnA
140
Cs mput .s r~ulred to keep the device d ...lected,
power-on current apprOllChes ICC IIctl\lft
• Note
MAX
Vee
rnA
otharw...,
A.C; CHARACTERIstiCS (~a" 0 - 70"0, Vee. 5V t 1~
READ CYCLE
------PARAMETER
SYMBOL
TMM2016P/D
MAX
MIN
TMM2016P·l/D·l
MAX
MIN
TMM2016p·2/D·2
MIN.
MAX
150
-
100
-
200
-
Address Access Time
-
150
100
Chip Select Access Time
-
150
tOE
Output Enable Time
35
tOH
Output Hold Time from Address Change
10
-
200
tco
-
telz
Output In Low-Z from CS
tCHz
Output
tRC
Read Cycle Time
tAce
In
Hlgh-Z from CS
tOLZ
Output In Low-Z from OE
tOHz
Output
tpu
tpo
Chip Selection to Power up Time
In
Hlgh-Z from
200
55
10
-
10
10
10
-
-
55
-
40
10
-
-
50
0
-
Chip Oeselectlon to Power down Time
100
-
5
OE
55
5
-
60
35
0
-
50
55
5
-
0
-
-
-
-
50
-
60
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
SYMBOL
PARAMETER
TMM2016P/D
MAX
MIN
TMM2016p·l/Dl
MIN
MAX
TMM2016P·2/D·2
MIN
MAX
twc
Write Cycle Time
150
-
100
-
200
-
tcw
Chip Selection to End of Wnte
120
90
150
tAS
twp
-
-
Wnte Pulse Width
tWR
20
-
100
-
Wnte Recovery Time
10
40
10
Address Set up Time
tDS
Data Set up T I me
60
-
tDH
Data Hold Time
15
-
tWLZ
Output In Low-Z from WE
tWHZ
Output
In
5
-
H,gh-Z from WE
Input Pulse Levels
0-35V
10n5
Input and Output Timing Reference Levels
15V
Output Load
Note
See Note
Output Load -1TTL Gate and CL '" 100pF
(Including scope and Ilg)
-
55 -
10
50
Input Rise and FaU Times
20
70
5
-
35
20
120
10
-
60
-
15
-
5
-
50
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
IA) READ
CY~C""
~
r::~~--------------'RC-------------~~
~-----------------------------'O-H--------------------
ADDRESS
OE
OUTPUT DATA VALID
°OUT
UNKNOWN
(8) READ CYCLE (2)
DOUT
SUPPL Y
CURRENT - - - - - - - - - - - -
IC)WRITE CYCLE (1)
~-----------------'WC----------------~~
ADDRESS
---------JI~------------------------------------~r~-----------
OE
I----------'cw---------i
WE
°OUT
_ _ _~,C_'DS--'------
_____________________________~DATAINSTABL~
- 56 -
(0) WRITE CYCLE (2)
ADDRESS
I
cs
WE
°OUT
°ll-J
• Note
READ CYCLE Il} READ CYCLE (2) WRITE CYCLE (2) -
WE IS high for Read Cycle
Device IS continuously selected,
Cs '"
VtL
All addresses are valid prtor to or comcldent with
De = VIL'
DE = VIL
we IS high for Read Cycle
- 57 -
Cs tranSition low.
• Plastic package
24 2322212019181716 16 14 13
1
2 3 4
6 6
7
B 9 10 11 12
324MAX
• Cerdip packlllJll
24232221 20191817 16 15 '4 13
X
~
C
--
~.
~
"!
!2
,
2
3 4 6
6 7 8 910"
f2.
z
~
15.24±O.3
1$
1
~
O.2S~~.~~ U
15.24-17.7.
.1
Nots' Each laad pitch '12.54 mm AIII ••ds ar. located wlth,n 0.25 mm 01 their true longitudinal position with rlllP8Ct to
No.1 and No. 24 'ead••
All dlrnenllonl are In mlilimeten
Note
Toshiba doe. not assume any resPonsibility for use of any clfcultry described, no cirCUit patent hce"IItS are Implied, and Toshiba re.erve.
the nght, at any time without notice, to change .ald circuitry
©Oct, 1981 Toshiba Corporation
PRELIMINARY
Characteristic, ar. subject to change without notice
- 58 -
TMM2016AP: 2K WORD x 8 BIT STATIC RAM
TMM2016AP
N CHANNEL SILICON GATE OEPLETION LOAD
*Thls IS advance informattan and specifications are
subject to change without not....
I PEATURGS]
• Fully Static Operation
• Easy Memory ExpanSion CS
• All Inputs and Outputs Directly
TTL Compatible
• Common Data Input/Output
• Three State Outputs
• 24 Pin Standard PlastiC Package
(both 0.6 Inch and 0.4 Inch Width)
• Fast Access Time lOOns
• Power DISSipation
Operating Current
65mA (MAX)
Standby Current
7mA (MAX)
• 5V Single Power Supply
• Power Down Feature CS
• Output Buffer Control
m:
Vee
A,
A,
WE
OE
A,
A,
A,
1/°1
1/°2
A.
A,
A,
A,
A,
A,
Memory
Cell Array
1128.16><81
--aVec
--oGNO
A"
I/O,
GNO~~______~J
hJSfnI.~
I/O.o-1~-~f_J
SYMBOL
Ao -A,
Ao -A,.
CS
Chip Select Input
wt
Write Enable Input
1/0, -1/0,
Data I nput/Output
Output Enable Input
Power (5VI
Ground
aE
Vcc
GND
110, D-,,;,,, <:.'/, ,,"
I
I
Note.
© Apr.,
TClltuba does not ••um. any responSIbility for use of any CirCUitry d4tSCrlbed, no CirCUit patent hcansel are Implied, and Toshiba r...rves
the nght. at any tlma without notice. to chan. said Circuitry
1982 Toshiba Corporation
- 60 -
TMM2016HD: 2K WORD x 8 BIT STATIC RAM
TMM2016HD
N CHANNEL SILICON GATE DEPLETION LOAD
-This II_vence information .nd lPHificdlons ....
subject to eM". without notice.
Output Buffer Control !JE
Easy Memory Expansion CS'
Common Data Input/Output
All I nputs and OUJputs Directly
TTL Compatible
• Three State Outputs
• 24 Pin Standard Cerdip Package
(0.6 Inch and 0.3 inch width)
•
•
•
•
• Fast Access Time
tACC = 35/45 ns
• Power DIssipation
Operating Current
150mA
Standby Current
20mA
• 5V Single Power Supply
• Fully Static Operation
• Power Down Feature. CS'
A,
Vec
A,
A,
I
A,
A"
A,
C!
Memory
A"
1/0,
C.II Array
1/0 1
1/0,
I/0 l
1/06
t/O J
I/0s
GND
1/0,
1'28x'6x81
11111.'.11
SYMBOL
Ao -A.
A4 -A to
CS
WE
I/O, -I/O.
DE
Vcc
GND
NAME
Column Address Inputs
Row Address Inputs
Chip Select Input
Write Enable Input
Data Input/Output
Output Enable Input
Power (5V)
Ground
-
61 -
----oVec
--oGND
Note
Tmhlba does not assume any responSibility for use of any circuitry described, no circuit patent licenses are Implied, and Toshiba reserves
the nght, at any time without notice, to change Soilid circuitry
@Apr., 1982 Toshiba Corporation
- 62 -
CMOS Static Random Access Memories
- 63 -
4 KBit CMOS STATIC RAM COMPARISON TABLE
1Kx4 CMOS STATIC RAM
Device Number
OPERATION
MODE
TC5514AP
~e
Mode
CE
R/W
Addresses
WRITE
L
L
Valid
READ
L
H
STANDBY
.
.
H
H
TC5513AP
1/0, __
1/0, __
Power
CE
R/w
Addresses
DIN
1000
L
L
Valid
DIN
1000
L
H
Valid
DoUT
1000
H
.
.
Hlgh-Z
100S
Valid
DOUT
1000
Fixed
'H' or'L'
Hlgh-Z
100S
TranSition
Hlgh-Z
1000
All address Input CircUits are not controlled by
CE
--
Power
-
:All address Input Circuits are controlled by CE
g:
CE
Ao
Difference In control function
I
Ao
Address
I
Buffers
A.
A.
Once address transition occur, the device
IS
activated
Independent of CE Input levels
Difference
In
access lime from
address and chip enable
Address
Buffers
Only when address transition occur under the
condition of
CE = L, the device IS activated
Address Access time
200ns
Address Access time
200ns
Chip Enable Access time
70 ns
Chip Enable Access time
200ns
16KBit CMOS STATIC RAM COMPARISON TABLE
PIN CONFIGURATION
TC5517AP
TC5516AP
TC5518BP
TC5517BP
;-----,
'""\
VDD
VDD
A.
A.
A,
A,
A,
V DD
A.
A.
A,
A/W
A/W
A/W
eel
5E
CE
A"
A"
A"
CE
CE
GEl
1/0&
I/O S
l
I/Os
OPERATION MODE
I
Device Number
0'>
0'>
I
~
Mode
Name
TC5517AP
TC5517BP
TC5516AP
CE,
CE,
RIW
Ao-A IO
9-11
13-17
1/0 , _ 8
18
20
21
1-8,22
23,19
18
Power
20
21
I
TC5518BP
1-8,22
23,19
9..... 11
13-17
CE
OE
R/W
Ao ..... A to
1/°,_8
Power
Ao-A lO
9-11
13-17
1/0, _ 8
18
20
21
1-8,22
23,19
CE,
CE,
R/W
Power
I
WRITE
L
L
L
Valid
D,N
IDoO
L
.
L
Val,d
D,N
1000
L
L
L
Val,d
DIN
1000
I
READ
L
L
H
Valtd
DOUT
1000
L
L
H
Valtd
DOUT
1000
L
L
H
Val,d
DOUT
1000
STANDBY 1
L
H
*
*
H,gh-Z
1000
*
H
*
*
H,gh-Z
loos
STANDBY 2
H
*
*
*
H,gh-Z
loos
H
. . .
Hlgh-Z
100S
i
OUTPUT
DESELECT
I~ I~ I~ I~ I~ I~
r\I~. ~. ~~~
H
L
*
H
. .
H'gh-Z
loos
Hlgh-Z
1000
I~ l~ I~ I~ I~ ~
-~-- -~
-V%~~
PARAMETER
CONDITIONS
Min.
Max.
UNIT
VOR
Data Retention Voltage
2.0
5.5
V
loos
Data Retention Current
OV" CE" 0.2V
or
VDD-0.2V" CE" Voo '(3)
-
Note (11
JlA
SYMBOL
Chip Deselectlon to
tCDR
0
Data Retention Time
tR
tRC Note (2l
Recovery Time
Note (1)
Refer to 10DS specification
In
-
JlS
-
JlS
indIVIdual data sheet.
(2)· Read cycle time.
I
TIMING CHART
DATA RETENTION MODE
Voo - - - - - - , .
4.5V
45V
Voo
GNO-----r-----------------+--------CE
Note (3)' For 16K Bit CMOS RAM, VOO-O.5V ~
DetaIls are specified
In
CE
~ VOO
TC5516/17/18 data sheets.
- 67 -
TO$IIBA r.tQ$ MEMORY. PR.OIII8Ts_
, ' .,
"
.. '~ '-,' "
.
'."
.""
:.
">'~;'
"";'~:~'
~,"
.
T C S SOl P / - I
TCSSO 10/- I
256 WORD x 4 BIT CMOS RAM
The TC5501P/D IS a fully static read write memory
organized as 256 words by 4 bits using CMOS technology. Because of ultra low power dissipation, the
TC5501 P/D can be used as battery operated portable
memory system and also as a nonvolatile memory
with battery back up. The TC5501P/D operates from
a single 5V power supply with a static operation, so
that the no refresh periods are required This slmpli·
fles the power supply circuit design.
• Low Power Dissipation
· 55,tW (MAX.) STANDBY
· 83mW (MAX.) OPERATING
• Single 5V Power Supply
• Data Retention Voltage 2V to 5 5V
• Package
· PlastiC DIP TC5501 P
· Cerdip DIP. TC5501 D
The three state outputs simplify the memory ex·
pansion making the TC5501 P/D suitable for use In a
microprocessor peripheral memory. Since the mini'
mum data retention voltage IS 2V, the battery back
up system needs only simple circuit. By uSing Toshiba's
original C'MOS technology, the device circUitry IS
not only Simplified but Wide operating margin and
noise margin are also realized.
The TC5501 P/Dis offered In standard 22 Pin plastic
and cerdlp packages, 0 4 Inch In Width
•
•
•
•
Fully static operation
Three State Output
Input/output, TTL Compatible
Access T Ime
TC500l P/D
,tACC ~ 400ns (MAX.)
TC5501 P·l /D-l, tACC ~ 600ns (MAX.)
:fl!f(~'
(TOP VIEW)
voo
A4
RIW
CEl
DOUTl
00
CE 2
DOUT1
16
00UT4
DOUT2
15
DIN4
14
DOUT3
13
DIN3
CE, <>-".D.>--r-.
DOUT3
CEl
DOUT4
DIN2"1-_ _ _ _
'2. . DOUT2
RIW
P1NNAMES
Ao- A7
RIW
Address Inputs
eEl. eEl
Chip Enable Inputs
01Nl-4
oOUT1-4
00
Voo/GNo
Read Wnte Input
Data Inputs
Oata Outputs
Output Disable Input
Power SupplV Termmals
-
69 -
SYMBOL
ITEM
V
-03- Voo +0.3
V
O-Voo
800
mW
Power Supply Voltage
VIN
I nput Voltage
VOUT
Po
Power Dissipation (Ta - 85·C)
TSOLoER
Soldering Temperature· Time
TSTG
Storage Temperature
-55-150
TOPR
Operati n9 Temperature
-30-85
Output Voltage
SYMBOL
UNITS
RATING
-03-70
Voo
V
°C· sec
·C
·C
260 10
PARAMETER
TYP.
MAX.
Voo
Power Supply Voltage
4.5
-
55
V
VIH
Input High Level Voltage
2.2
Input Low Level Voltage
-0.3
Voo +0 3
0.65
V
VIL
VOH
-
Data Retention Voltage
20
-
55
V
MIN
TYP(1)
MAX.
UNITS
-
±005
±10
p.A
-
02
10
j.:A
15
± 1.0
p.A
SYMBOL
PARAMETER
MIN
CONDITIONS
UNITS
V
liN
1nput Current
1005
Standby Current
1000
ILO
Operating Current
Voo = 5.5V, teye = lp.s
10H
Output leakage Current
Output High Current
O:::::VOUT:::::Voo
Voo = 4.5V, VOH = 2.4V
-1.0
-2.0
-
mA
10L
Output Low Current
Voo - 4.5V, VOL - 0.4V
2.0
3.0
-
mA
PARAMETER
Input Capacitance
Output Capacitance
Note (2)
O:::::VIN:::::VoO
Voo = 2.0V to 5.5V
CE, = 0.2V, Output open
CONDITIONS
VIN =OV, f = lMHz
VOUT =OV, f = lMHz
This parameter is periodically sampled and Is not 100% tested.
- 70 -
-
6.2
±0.05
mA
•
READ CYCLE
SYMBOL
TC5501P/D
PARAMETER
TC5501P·l/D·l
UNIT
MIN
MAX
MIN
MAX
450
-
650
-
ns
450
650
ns
600
ns
700
ns
350
ns
tAC
Read Cycle Time
tACC
Address Access Time
tACC1
CE, Access Time
-
tACC2
eE 2
-
500
-
toaD
00 Access Time
-
250
-
tCOE
Output Enable Time
-
0
-
ns
tOIS
Output Disable Time
0
0
130
150
ns
tOH
Output Data Hold Time
0
-
0
0
-
ns
Access Time
400
I
• WRITE CYCLE
SYMBOL
TC5501P/D
PARAMETER
TC5501P·1/D·1
UNIT
MIN
MAX
MIN
MAX
650
-
ns
150
-
ns
twc
Wnte Cycle Time
450
tAW
Address Setup Time
130
-
tew
CE, Setup Time
130
-
150
-
ns
twp
Write Pulse Width
250
400
Data Setup Time
250
400
-
ns
tos
-
tOH
Data Hold Time
50
100
-
ns
tWA
Write Recovery Time
50
50
-
ns
A.C. TEST CONDITIONS
100 pF + 1 TTL Gate
• Output Load
045V,24V
• Input Pulse Levels
• Timing Measurement Reference Levels
Input
0 65V, 2.2V
Output
0 65V, 2 2V
• Input Pulse Rise and Fall Times
10ns
-
71 -
-
ns
Rood Cycle
A.DDRESS
CE1
CE,
00
DOUT
!We
Write Cycle 1
ADDRESS
co,
'cw
"'"
R/W
V'H
00
DOUT
0,.
Write Cycle 2
'We
ADDRESS
STABLE
V.H
V,
C<.
V,
c.,
R/W
00
.....
'H
V,H
V,
V'l
V'H
'0.
DOUT
D'N
- 72
-
tACC- VOO
eo0
BOO
.........
0
.......
0
......
-
CL" l00pF
i--
"""
VOOo.45V
CL-l00pF
Tao. 25°C
fcs
""r-
J
J-
...-
~-~
TCSJ,P/D
-
>-----
20 0
0
600
"/
0
0
-30
5
800
-
--
l--
-
TC5501P /O
30
Ta roC)
twP - Voo
VOO(V)
t A CC
-;?
T1C5501 p_\I0-1
CL
600
~
-
1,.-'~
P1-
C!>~O"'~ -
~
Ta" 2SoC
VOO"45V
,
-
I--
300
..........
~
100
...
0
200
-
600
I-- ~lP-'IO_l
.......... I-.. TCSSOiJPIO
-r=-
0
30
800
CL (pF)
twP
6_0
50
VOOIV)
1000- VOO
Ta
0
Til'" 2SoC
\'00 - 4 SV
300
!)
6
200
TCS501P-1
L-- I--
l
0
fOo!.- l--
Tcss61 P /O
100
otC'iC ..
I--
",{csl3O'f' I
5t...- t::::- ~"""-"I
I0
I
A~ V
d06fIO '"
:\tC'iC
0
-30
I
I
6
VOOIV)
100S - VOO
20
100
VOO- 4.SV
Ta" 2SoC
6
•o
E
o
E
•.
0
\-.. ±-- TCS50JP/O tCyc "'450 n.
5 >----- TCSiJP'JIO.
"I' tCyc'" 6So n,
0
-30
I
40 0
Ta- 25°C
~
~
E
-
60
90
001
2
VDO (V)
- 73 -
7_0
•
1005 - Ta
0
Ta" 25°C
VOO" 3 OV
VOD"'45V
-60
0
.
//
1-
V
1
,....
!,
2
Y
..........
.........
........
-20
.......
~
./
00 1
/"
o
60
-30
10
1""-
50
'OH-TII
0
0
VOO= 45V
VOH "24V
Ta" 2SoC
0
V
0
0
r-
r--
0
o
-
60
30
/"
/
0
J
90
-
/
1.0
05
VOl-IV)
VIH - VOO
0
0
VOO;: 4 5V
Ta = 2SoC
VOL =06V
0
0
Or-f--
-
0
- r--
0
oV
0
60
--
r-
0
---Voo
tos -
-
--
~
- - r---
(V)
VOO
0
Ta = 2S c C
Ta _ 2SoC
300
0
~
.9
0
O~
200
~ .......
I--
TC5501P-l/0-1
TCSj1PID
o
0
5
VOOIV)
30
50
VOO(V)
- 74 -
60
•
tos- Ta
400
Voo = 4 5V
300
!
200
k
U>
9
~cSno~VI-"'"
100
~O
~C
o
-30
60
90
twR - VOO
tWR - Ta
40
0
Ta = 25°C
Veo"" 4 5V
0
30
......
20
""-...
0
.......... "
r----.. t--..
10
~
-----
I
o
3
10
-- --
.........
r-
0
-30
60
90
Vee (V)
100
100
75
;:
:-
i'-: t'--.........
f-----
,
50
r----' -
25 f---
--
Ta
r--
rCS5{)
=
25°C
5
,~
-:.::::.' p, '/0"
~~ F=
- -
~C~50'P-' I~'
!----
~
iC550Wli
50
--
I
--
5
I
30
-- Veo = 4.5V
r-.....
r----40
5,0
60
7,0
-30
Veo (V)
- 75 -
60
90
OUTLINE DRAWINGS
PLASTIC PACKAGE
~~~!~~~~
1
2
3
4
5
8
7
8
Unit I" mm
9 10 "
..
10.16
±o.o&
o.25~~.~5
10.4' .... ".&1
CERDIP PACKAGE
C::::::::JJ
1 2
3
4
5
6
7
8
9 10 "
o S±O 15
Not..
each Iud pitch II 2 154 mm All I..ds .r. located within
0215 mm of thalr true longitudinal pOliti on with retpKt to
No 1 and No 22 I..ds
.....:
Tothtbll doa not naume any responsibility for use of any cirCUitry d..cntMd. no ClfCUlt
right,8t any time without notice. to ch8nge "Id cirCUitry
OM.,., , . ., TOIhIba Corpor8tlon
'
- 76 -
~t.nt
hcen....r. Implied, and Toshiba , ...rves the
TC5508P
TC5508P-1
1024 WORD X 1 BIT CMOS RAM
SILICON GATE CMOS
TC5508P-4
The TC5508P is a static read write memory
organized as 1024 words by 1 bit using CMOS
technology. Because of ultra low power dissipation,
the TC5508P can be used as battery operated
portable memory system and also as a nonvolatile
memory with battery back up. The TC5508P operates from a single 5V power supply with a static
operation, so that the no refresh periods are required.
This simplifies the power supply circuit design.
The three state output simplify the memory
expansion making the TC5508P suitable for use in a
microprocessor peripheral memory. Since the minimum data retention voltage is 2V, the battery back
up system needs only simple circuit. By uSing
Toshiba's original C'MOS technology, the device
circuitry is not only simplified but wide operating
margin and noise margin are also realized.
The TC5508P family is moulded in a dual-in-line
16 pin plastic package, 0.3 Inch in width.
• Low Power Dissipation
. 55jlW (MAX.) STANDBY
. 55mW (MAX.) OPERATING
• Single 5V Power Supply
• Data Retention Voltage; 2.o-5_5V
• 16 PI N Plastic Package
• Static Operation
•
•
•
•
Three State Output
Input/Output; TTL Compatible
Latched Address Inputs
Access Time
TC5508P ; tACC = 370ns (MAX.)
TC550BP-4, tAce = 450ns (MAX.)
TC5508P-1; tACC = 550ns (MAX.)
(TOP VIEW)
CI
1
Veo
A,
2
D,N
A.
3
AIW
A,
4
A,
A"
•
A.
DOUT
GND
•
7
32
A,
A,
A.
D,N
8
A -A
A/W
AddreSi Inpun
Read Write Input
CE
Chip Enable Input
Veo/GND
Power Supply Termlnels
08talnput
0------','"
AIW o--Hf--
A.
D
A,
A,
~"
a
<
w
Il:
---<>voo
w
0
~
a
MEMORY
~ELL
s:0
~GND
ARRAY
64 x 64
cr
Data 1/01
A,
Data 1102
Data 1/0"
Data 1/03
Data 1/0 3
Data 1/04
PIN NAMes
Address Inputs
R/W
Read Wnte Input
Data 110,......
Data Input/Output
00
0 utput DIsable Input
VOO/GND
Power SupplV Termmals
CE,r-~~"-----~-'
CE 1 O------~J
R/Wo-----j-d.....J
ooo---~~=r-----------------~
-
83 -
I
,
ITEM
SYMBOL
VIN
VOUT
Po
TSOlOEA
TSTG
TOPA
SYMBOL
Output Voltage
700
Storage Temperature
-55-150
-30-85
Operating Temperature
PARAMETER
Input Low Level Voltage
Data Retention Voltage
ITa =
TYP
MAX.
4.5
50
5.5
V
Voo-15
-03
2.0
-
Voo+0.3
0.6
5.5
V
V
V
PARAMETER
CONDITIONS
OV~VIN ~Voo
Voo = 2-55V
CE, = 0 2V. Output Open
Standby Current
1000
IlO
Operating Current
Output Leakage Current
Voo=55V. tCyc=llJ.S
10H
Output High Current
Output Low Current
Voo=4 5V. VOH - 2.4V
Voo = 4.5V. Vo l = 0.4V
f-1MHz
Note .1)
Note (2)
121
UNIT
MIN
100S
Co
rnW
°C· sec
°c
C
30-85° C)
Input Current
10l
C, (2)
V
V
260' 10
Vil
VOH
liN
V
-03- Voo + 03
a-Voo
Power DISSipation (Ta - 85°C)
VIH
SYMBOL
-03-70
Soldenng Temperature· Time
Power Supply Voltage
Input High Level Voltage
Voo
UNIT
RATING
Power Supply Voltage
Input Voltage
Voo
I "put Capacitance
Output Capacitance
T. - 26° C, VDD - BV
This p.r8fl1et8' II pertOdicelly ..mpled and
OV~VOUT~VOO
f = 1MHz
.s not 100% .sted.
- 84 -
MIN
TYP.111
MAX.
UNIT
0
to.05
t10
/lA
0
02
20
/lA
a
0
10
20
rnA
to 1
t50
-1.0
-2.0
1.6
20
-
-
5
7
10
15
/lA
rnA
rnA
pF
pF
.'
~1.~~FlATIN(JCONOlTfONS
• TC5047 AP.1
MIN
MAX
UNIT
TRC
Read Cycle Time
650
-
ns
twc
Wnte Cycle Time
CE Setup Time
-
ns
tCES
650
2013)
tCEH
tpc
CE Hold Time
VDD ~4 5- 5 5V
20'3)
-
ns
Precharge Time
CL
100pF
100
-
ns
tCE
twp
CE Pulse Width
V,H ~ VDD - 1 5V
550
ns
Write Pulse Width
-VDD + 03V
300
tDS
Data Setup Time
V'L~-03-06V
300
Ta ~ -30- 85"C
-
ps
ns
SYMBOL
CONDITIONS
PARAMETER
~
0
tDH
Data Hold Time
tew
Wnte Setup Time
350
tRS
Read Setup Time
0
tRH
Read Hold Time
0
ns
ns
ns
ns
ns
tees + tCEH ~ 100 ns
Note (3)
• TC5047AP-2
MIN.
MAX.
UNIT
t RC
Read Cycle Time.
1000
ns
twc
Write Cycle Time
tCES
CE Setup Time
1000
2014)
tCEH
tpc
CE Hold Time
PARAMETER
SYMBOL
CONDITIONS
Precharge Time
CE Pul"" Width
VDD =4 5- 55V
CL ~ 100pF
2014)
-
200
-
ns
800
-
ns
tCE
twp
Write Pulse Width
tDS
Data Setup Time
V'H=VDD -15V
-VDD +03V
V ,L =-03-06V
tDH
Data Hold Time
Ta ~ -30 - 85°C
500
500
0
tew
WnteSetup Time
550
tRS
Read Setup Time
0
tRH
Read Hold Time
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Nou (4) tees + tCEH ~ 200 ns
::~i~tS'itcs·
(Ta=-30-85°C)
• TC5047AP·1
SYMBOL
PARAMETER
MIN
TYP
MAX.
UNIT
-
550
ns
CL = lOOpF
-
100
ns
VOH ~2 4V. VOL =0.6V
-
100
-
ns
MIN
TYP
MAX
UNIT
-
800
ns
-
-
200
ns
-
200
-
ns
CONDITIONS
tACC
Access Time
VDD = 4 5- 5 5V
tDiS
Output Disable Time
tCOE
Output Enable Time
• TC5047AP·2
PARAMETER
SYMBOL
CONDITIONS
tAce
Access Time
tDiS
Output Disable Time
VDD = 4 5- 5 5V
CL ~ 100pF
tCOE
Output Enable Time
VOH
-
~2
4V. VOL = 06V
85 -
I
~'JIIBI"'"
• Read Cyd.
:x
ADDRESS
t~
STABLE
~H
tee
V,L
~
I~
-.-/
VIH
K
V,H
V,H
V,L
V,H
VIH
V,L
V,L
V,H
V,H
tpc
CE,
~
,~
V,L
V,H
00
J
V,L
.J+:~
f!~r
V,H
R/W
or
V,H
tAce
I
~
0
tOIS
tcaE
01/0
HIGHZ
VOH
-~
~
VALID DATA
VOL
HIGH Z
UNKNOWN
twc
• Write Cycle
IX
ADDRESS
t~
~
V,H
V,H
V,L
STABLE
~H
tee
V,L
I-----
Ir '---\
VIH
K
teEs
V,H
VIH
V,L
V,L
~
CE,
~
V,H
V,H
~
V,L
tcw
00
twp
R/W
,
'\
V,L
\ ._______ VIL
tos
0110
"
HIGH Z
£VIH
-~VIL
/
-
86 -
DATA IN
STABLE
V,H
______ J
/
~
V'H
V,L
DON'TeARE
VOH -
IOH - Ta
IOH
-B 0
-B 0
Ta = 2SoC
VOO"'4SV
VOH'" 2 4V
VOO" 4.SV
_6 0
<'E
r
-40
.9
-6 0
~---
--
-- - -
-40
~
..............
.......
-20
20
10
.9
........
~
-20
""
40
30
VOH (V)
-
o
5.0
-30
60
30
90
Ta tCI
IOL - Ta
0
BO
II
0
I
0
VOO = 4 SV
Ta= 2SoC
I
/
VOL = 0 4V
VOO=45V
60
0
I
20
o
0~5
1.0
1 5
-30
20
o
I
r-- t--
30
60
90
Ta (oC)
VOL (V)
4. 0
50
Ta
=
Ta=2SoC
2SoC
40
3. 0
~
~
-
~
20
/
of
- ---
,........,. ,.....
30
>
20
i.-"
10
3.0
...40
V
0
....-V-
0
~
5.0
60
0
30
70
--
_f--
~~
40
5.0
VOO (vI
VOO (V)
-
87 -
6.0
7.0
I
tACC- T •
tACC - Vee
800
800
"'"
600
!
u
"
400
U
~
........
'-...
........
3.0
4.0
CL'" 100 pF
600
r-.....
~CSoo
~c>
NC504,Jp.,
200
o
V O O-4.SV
Ta·2SoC
CL-100pF
...........
5.0
TC5047AP·2
--6.0
-I-- to-
]:
u
u
~
400
Tcbo47 AP·1
~
r--
200
o
7.0
-30
60
91
Vee (V)
twp - VOO
400
800
-~ - -VOO-4.&V
600 ~
!
u
~C.J..,"P"_
400
I--
U
~
200
T.-
I\..
T.-2SoC
300
.~
'"
.......
I" ...........
200
......
2SoC
~04'4PJ... _ C-~.l l -I--
~
~~.,
100
o
o
0
200
400
600
800
4.0
3.0
CL (pF)
5.0
7.1
6.0
Vee (V)
tpc - VOO
400
200
TCSO~7AP.2
300
T. _ 25°C
VOO = 4.SV
15 0
I
200
~
100
TCS047AP·1
......
'00
0
-30
50
o
30
60
90
o
3.0
r4.0
...... 1-- ~7A,P_2
-
5.0
Voe (V)
- 88 -
-
~
6.0
7.1
1000 -
1000 - Ta
Voo
20r---~--~--~--~---r----------~
20
Voo" 4 SV
Ta"" 25° C
tCYC'" 1.0,us
'5~--t---t---+---+---~---r---'--1
'5
<
!
0
'0
c
E
-~
3.0
I--
40
- ----S.O
60
<
!
o
'°r---t---t---+---+---~--~---r--1
c
c
~3~0--~--~--~--~3~0~~--~6~0--~--~90
70
Ta ("C)
VOO (V)
100S - VoO
100S - Til
'00
'00
'0
'0
Voo '" 3.0V
<
..-
<
'"
3-
/
3c
E
i'l
E
0.'
".,/
.,/
0.'
00'
2.0
".,V
./
3.0
4.0
50
0.01
60
30
60
90
Voe (V)
tos - Veo
tpc - Ta
200
400
f--
:--,.
VOO" 4 5V
'50
300
TC5047 AP-2
c
E'
c
'00
'"
E
.tcs044AP-1
50
o
-30
200
"' ""
"'-
~
'00
30
60
90
o
3.0
4.0
Ta"" 2SoC
........
b-..
. . . r- ~
rfo/=
04}..q,o,<_
50
VOO (V)
Ta tCI
- 89 -
6.0
,----
~
7.0
I
tos - Ta
tOH - Ta
400
'Or---~--~--T_--T_--~---------VOO=4.5V
Te50A1~ r-
]
'"
~
200
1
Tb5041 p .,
'00
a
-30
VOO =4 5V
---
300
60
-20~--+---+---+_--+_--~--~--~--
~0_~3=0~L---L---~--3~0~~--~60~~~
90
Ta (oe)
Umt Inmm
e::i:::::[!
1
2
3
4
5
6
7
8
9
10
27.5 MAX.
I,
z
I!------+-----,f- ~
E
o
12±O.15
254±0.25
0.5±0.15
1016+01
I
z
i
.
I
Note Each lead pitch IS 2 54mm
All lead
are located within 0 25 mm of the
true longitudinal pOSItion with re ..... ~(
to No 1 and No 20 leads
-005
10.16 -1180
I
.
N
M
Note
ToshIba does not assume any responsibIlity for use of any circuitry described, no circuit patent hcanses are Implied, and Toshiba reserves
the right, at any time without notice, to change said cIrcuitry.
©Mar, 1980 ToshIba CorpOration
Olstnbuted by
-
90 -
4096-WORD x 1 BIT CMOS STATIC RAM
SILICON GATE CMOS
TC5504AP-2/-3, TC5504APL-2/-3
TC5504AD-2/-3, TC5504ADL-2/-3
The TC5504AP/AD IS a 4,096 bit high speed and
low power static random access memory organized as
4,096 words by 1 bit usmg CMOS technology, and
operates from a smgle 5-volt supply.
On chip latches are provided for addresses, data
mput and output, and read write control allowmg
effiCient mterfacmg with microprocessor systems
The TC5504AP/AD is a fully CMOS RAM, therefore It IS suited for use in low power applications
where battery operation and battery back up for non-
volatility are required Furthermore the TC5504APL/
AD L guaranteed a standby current equal to or less
than 1p.A at 60'C ambient temperature
The TC5504AP/AD IS guaranteed for data retention at a power supply as low as 2 volts The TC5504
AP/AD IS directly TTL compatible m all mputs and
output
The TC5504AP/AD is offered m both standard 18
pin plastiC and cerdip packages, 0.3 mch in width
• Standby Current
o 2p.A (Max) at Ta = 25'C }
1.0p.A (Max) at Ta = 60'C
TC5504APL/ADL
20p.A (Max.)
. TC5504AP/AD
• Low Power DIssipation
15mW (Typ) operating
• Smgle 5V Power Supply
5V ± 10%
• Data Retention Supply Voltage _ 2 - 55V
• All Inputs and Output Directly TTL Compatible
• Access Time
200ns (Max) TC5504AP/APL/AD/ADL-2
300ns (Max) TC5504AP/APL/AD/ADL-3
• Static Operation
• On Chip Address Register
• Three State Output
• Package
PlastiC DIP
TC5504AP/APL
Cerdip DIP TC5504AD/ADL
(TOP VIEW)
AD
1
18
AI
2
17 A11
A4
As
A,
A.
•
•
Voo
16 AID
,.
A,
A,
16 A.
6
•
A.
I.
A?
DOUT
7
12
A.
R/W
8
11
D,N
GNO
9
I.
CE
0'"0-----1
PINNAMU
Ao -A 11
Address Inputs
R/W
Read Wnte Control Input
CE
Chip Enable Input
D,N
Data Input
DOUT
Data Output
VOO
Power
GND
Ground
- 91 -
I
SYMBOL
RATING
ITEM
UNIT
VDD
Power Supply Voltage
--{)3-70
V
VIN
Input Voltage
--{).3-7.0
V
\tOUT
Output Voltage
PD
POlJIJef Dissipation
I
TC5504AP/APL
(Ta =85·C)
I
TC5504AD/ADL
TOPR
SYMBOL
rnW
550
800
Soldering Temperature Time
TSOLDER
TSTG
V
O-VDD
260
rnW
°c -sec
10
Storage Temperature
-55-150
·C
Operatil)Q Temperature
-30-85
·C
TYP.
MAX.
VDD
Power Supply Voltage
PARAMETER
4.5
5.0
5.5
V
VIH
Input High Voltage
2.2
VDD +0.3
V
VIL
VDtj
Input Low Voltage
--{).3
0.8
V
Data Retention Voltage
-
5.5
V
1IIIIIIIIIIVoo
- SYMBOL
MIN.
2.0
=SV t
10%. Ta =-30·C to 8S·C. unless otherwise noted)
PARAMETER
CONDITIONS
MIN.
IlL
I nput Leakage Current
OV:O; VIN ~ VD D
ILO
OutPu~t
CE =VDD -02V,OV~VOUT~VDD
Leakage Current
UNIT
-
Typ.lll MAX
-
UNIT
±10
p.A
±5.0
p.A
10H
Output High LevelCurrent
VOH =24V
-10
10L
.output Low Level Current
VOL=OllV
2.0
-
-
-
-
02
-
-
10
-
005
20
-
-
100
rnA
30
5.0
rnA
VDD = 2V - 5.5V
IDDS
IDD01
Standby Current
Operating Current
"1
TC5504AP L Ta - 25·C
TC5504ADL ITa = 6O·C
CE = VDD - 0.2V
other inputs =
TC5504AP
o 2V or VDD
TC5504AD
- 0.2V
tcycle = 1p.S, IDUT = OrnA
tcycl. = lp.S, V IH = V DD,vIL =OV, IDUT - OrnA
IDD02
Note (1) V DD = 5V, Ta = 25·C
• • • • • • ITa = 2S·C)
PARAMETER
CONDITIONS
Input Capacitance
Output Capacitance
VIN =OV f = lMHz
VOUT = OV f = lMHz
Note (2). This· parameter is periodically sampled and
IS
not 100% tested
- 92 -
rnA
rnA
p.A
p.A
.1l•••••II.llvoo =5V
SYMBOL
± 10%.
PARAMETER
Ta = -30·C to SS·C. unless otherwise noted)
TC5504AP-2/APL-2
TC5504AD-2/ADL-2
MAX
MIN.
420
-
ns
420
-
ns
580
-
ns
5
-
60
-
80
80
-
100
--
300
-
ns
200
-
300
ns
70
-
100
ns
-
ns
tRC
Read Cycle Time
300
Wnte Cycle Time
300
tRMWC
Read Modify Wnte Cycle Time
390
tAS
Address Setup Time
tAH
Address Hold Time
Precharge Time
tCEH
Chip Enable Hold Time
tACC
Access Time
Output Disable Time
Output Enable Time
Read Setup Time
Read Hold Time
Wnte Setup Time
Write Hold Time
Data Setup Time
Data Hold Time
too
tCOE
tRS
tRH
tws
tWH
tos
tOH
!wCH
tMO
Write Enable to CE Hold Time
Modify Time
UNIT
MIN
!wc
tpc
TC5504AP-3/APL-3
TC5504AD-3/ADL-3
200
0
0
0
0
60
5
-
0
0
0
0
-
80
5
-
5
60
80
-
80
-
150
0
Output Load
100pF + lTTL Gate
Input Pulse Levels
06- 24V
Timing Measurement Reference Levels
Input
0.8V and 2.2V
0.8V and 2.2V
Output
Input Pulse Rise and Fall Times _ 10 ns
- 93 -
0
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
I
"'III'
'.,
:t
~<
;:.",,'
• .READ CYCLE
UNKNOWN
• WRITE CYCLE
Addr...
rv2
I
'AH
L,----------
X~STABLE e:~"'f<
-----f.,pc
X
'Wc
tCEH
CE
A/W
HIGH IMPEDANCE
DOUT
• READ MODIFY WRITE CYCLE
t-jA
J>tEA;tr'
-____________x::::=
Add'... _ _ _ _
tpc IL
Vil
tRMWC
~----~~--~~==~
A/W
DOUT
-------~~:J~OO~~HI-~~~---_h~--VALID
UNKNOWN
-
94 -
•
.1-,
i.•• ',
100.0
T.·26°C
EE-voo
VIN-VOO
6.0
<
oS
III
< 10.0
4.0
3.0
0
E
IOOS VS. T.
IOOS VS. VOO
6.0
2.0
1.0
0
--- -- -- -3.0
4.0
VOO (V)
/
~
5.0
1
0:....w
6.0
V
/
/
o
T.-26°C
VOO-6.6V
EE-6.6V
\
T.-25"C
VOO-5.6V
EE-6.6V
1\
\\
10
1
I\.
.........
I
2
---
4
o
o
6
I'--- .......
!cycle (pSI
1000 VS. T.
1000 VS. VOO
6
8
VOO-6.6V
tcycle -, pS
T.-25°C
tcyclo -1 pS
4
g
E
2
o
3
2
VIN (V)
1
80
40
T. (oC)
IOOS VS. tcycle
3
I'---
V
/
1.0
IOOS VS. VIN
V
/
oS
30
o
o
/
VOO- 5.6V
CE=VoO
VIN=VOO
-
f.--
4.5
--- -6.0
VOO (V)
5.6
1
f.--
4
r2
o
a.o
-
-40
95 -
o
40
T. (OC)
80
I
:'
.,
VIH • VIL VS. Voo
1000 VS. tevel.
3.0
6
1\
1
\
4
Ta -2S0C
~ 2.0
\
o
c
9
T.·25°C
VOO=5.5V
---
..J
'>
~
X
""
2
o
o
'-....
'>
1.0
I-o
3
2
IOH
vs.
""'r-..
9
'"
-8.0
..........
X
-10
o
--- o
-40
1
-
vs.
T. - 25°C
VOO-4.5V
'\.
'" \
§
-4.0
'-
o
80
40
T. (oC)
IOL
3.0
2.0
Ta
30
\
4.0
VOH (V)
IOL VS. VOL
9
10
o
-40
5.0
Ta = 25°C
VOO·4.5V
VOL~0.4V
....
\
80
VOO-4.5V
20
6.0
-12.0
-20
..s
5.0
IOH VS. VOH
T.
VOO=4.5V
VOH-2.4V
;(
f..--
VIL
4.0
VOO (V)
3.0
tevel. (1lS)
-30
~
I--
.........
----- -o
40
1
/'
40
V
..J
9
20
o
80
T. (oC)
-
96 -
/
/
/
/
o
0.5
1.0
VOL (V)
1.5
Normalized tACC VS. T.
Normalized tACC VS. VOO
1.4
3.0
T.-25D C
VOO=4.5V
!:l
$ 1.2
,/
".~
1
/'
z 1.0
0.8
/'
/"
z 1.0
o
80
40
T. tC)
3.0
10
o
V
/'"
100
V
V V
200
'"
i'......
4.0
'"""-
-t-- ~
6.0
VOO (V)
T. -26°C
VOO-4.5V
20
\
!
30
]
2.0
I
V
o
-40
V
~
300
CL (pF)
- 97 -
6.0
I
• PLASTIC PACKAGE
18 17 16 15 14 13 12 11 10
Unltmmm
123466789
22.8 MAX.
2.54±O.26
D.S±O.15
• CERDIP PACKAGE
Oft
,;
[:::::]J
1
2
3
•
15
•
7
8
•
22' MAX
182j:025
048%0115
E.ch Iud pitch Is 2 54 mm Alii. . . . . . loca:Md wllhln 0 21mm of 1he,r IOIlfl,NdIM' po.trOll
""thrllll»CftoNo 'enciNo 181__
All dlm..... _.r.ln mllllrnelwt.
Note:
© Feb.,
Toshiba do.. not assume any ,..ponllblllty for u •• of any circuitry
right, at any tlma without notice. to change .. Id circuitry.
1981 Toshiba Corporation
d8ICrlb~.
- 98 -
no circuit
patent
lie.,... .r. Implied, and Ta.hlba
reMrVft
the
TC55 I 4P TC55 I 4P-1
TC5514P-2
1024 WORD X 4 BIT CMOS RAM
SILICON GATE CMOS
au
II
The TC5514P is a full static read write memory
organized as 1024 words by 4 bits using CMOS
technology. Because of ultra low power dissipation,
the TC5514P can be used as battery operated
portable memory system and also as a nonvolatile
memory with battery back up. The TC5514P operates from a single 5V power supply with a static
operation, so that the no refresh periods are required.
This simplifies the power supply circuit design
The three state outputs Simplify the memory
expansion making the TC5514P suitable for use in a
microprocessor peripheral mel1"\ory. Since the minimum data retention voltage is 2V, the battery back
up system needs only simple circuit By uSing
Toshiba's original C2 MOS technology, the device
circuitry is not only simplified but wide operating
margin and noise margin are also realized.
The TC5514P family is moulded in a dual-in-line
18-pin plastic package, 0.3 inch in width.
• Low Power Dissipation
110"W (MAX.) STAND BY
110mW (MAX.) OPERATING, TC5514P-l/-2
138mW (MAX.) OPERATING, TC5514P
• Data Retention Voltage 2V to 5.5V
• Single 5V Power Supply
• 18 PIN Plastic Package
•
•
•
•
Full Static Operation
Three State Outputs
Input/Output TTL Compatible
Access Time
TC5514P ,tACC = 450ns (MAX.)
TC5514P-l, tACC = 650ns (MAX.)
TC5514P-2; tACC = 800ns (MAX.)
(TOP VIEW)
voo
A.
17
A,
A,
,.,.
Ao
A.
A2
CE
GNO
5
•
•
•
7
Ao
,.
,."
,.
",0
Aa
A.
Oat.I/OI
Data 1/02
Datal103
Date 1/04
RIW
• •1• • •
Ao-Ao
RNI
CE
Data 110.-.
Voo/GNO
Address Inputs
Road Write Input
Chip Enable Input
Data Input/Output
Power Supply Terminal
- 99 -
I
UNIT
RATING
ITEM
SYMBOL
V
Voo
Power Supply Voltage
-Q.3-7.0
VIN
Input Voltage
-Q.3-Voo + 0.3
VOUT
Po
Output Voltage
V
V
mW
O-Voo
550
Power Dissipation (Ta -85 C)
·C sec
Soldering Temperature· Time
260·10
TSTG
Storage Temperature
-55-150
·C
TOPR
Operating Temperature
-30-85
·C
TSOlOER
MIN.
PARAMETER
SYMBOL
Voo
Power Supply Voltege
4.5
VIH
Input High Level Voltage
2.2
Vil
Input Low Lewl Voltage
-Q.3
VOH
Data Retention Voltage
TYP.
MAX.
UNIT
5.0
5.5
V
Voo+0.3
V
0.65
V
5.5
V
2.0
-
(T. = -30 - _·CI
SYMBOL
PARAMETER
Input Current
liN
CONDITIONS
O~VIN ~Voo
=2V to 5.5V
CE = Voo -Q.2V; Output f'pen
Other Inputs =0.2V or Voo -Q.2V
Voo = 5.5V. !eve -1 jJ$ I TC5514P
Voo
IOOS
Standby Currant
1000
Operating Current
I.t.o
Output Leskage Current
O~VOUT~VOO
IOH
Output High Current
Voo -4.5V. VOH =2.4V
TYP. III
MAX.
UNIT
-
to.05
t1.0
jlA
-
02
20
IlA
-
13
25
mA
10
20
mA
-
to.05
t1.0
p.A
-1.0
-20
mA
Output Low Current
Voo = 4.5V. VOL =,0.4V
2.0
3.0
-
(2)
Input Capacitance
j-1MHz
-
5
10
pF
(2)
Output Capacitance
j-1MHz
-
7
15
pF
IOl
Cr
Co
I TC5514p·1/·2
Output Open
MIN.
Note (1) T. - 2SGe
voo • BV
(2) Thlt .......... perlodlc.Uy ..mpled M'd 1. not '00% tened.
- 100-
mA
TC5514P
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
tAe
Read Cycle Time
450
-
ns
twe
Write Cycle Time
450
-
ns
twp
Write Pulse Width
350
-
ns
tDS
Data Setup Time
200
tDH
Data Hold Time
tWA
Write Recovery Time
tAW
Addres, Setup Time
30
-
tOH
OutpjJt1lata Hole Time
30
-
ns
MIN.
MAX.
UNIT
650
ns
650
-
350
-
ns
200
-
ns
0
-
ns
0
-
ns
V DD =4.5 - 5.5V
CL = 100pF + 1 TTL Gate
VIH =22-V DD+03V
=--0.3 - 0 65V
Ta = -30 -85°C
V 1L
0
0
UNIT
ns
ns
ns
ns
TC5514P-l
SYMBOL
PARAMETER
tRe
Read Cycle Time
twe
twp
Write Cycle Time
tDS
Data Setup Ti me
tDH
Data Hold Time
tWA
Write Recovery Time
tAW
Address Setup Time
tOH
Output Data Hold Time
Write Pulse Width
CONDITIONS
VDD =4.5 - 5.5V
CL = 100pF + 1 TIL Gate
=2.2 - VDD + 0.3V
VIL = --0.3 - 0.65V
Ta = -30 - 85°C
VIH
50
30
ns
ns
ns
TC5514P-2
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
tAe
Read Cycle Ti me
800
ns
twe
Write Cycle Time
800
twp
Write Pulse Width
tDS
Data Setup Ti me
tDH
Data Hold Time
tWA
Write Recovery Time
tAW
Address Setup Time
50
-
tOH
Output Data Hold Time
30
-
ns
VD D = 4.5 - 5.5V
= l00pF + 1 TIL Gate
V 1H = 2.2 - VDD + 0.3V
VIL = --0.3 - 0 65V
Ta = -30 - 85°C
CL
- 101-
450
250
0
0
ns
ns
ns
ns
ns
ns
I
(Ta - -30 - 85·C)
TC6514P
SYMBOL
tACe
teo
tOIS
teoE
PARAMETER
Access Time
CE Access Time
Output Disable Time
Output Enable Time
CONDITIONS
Voo ~ 4.5 - 5.5V
CL = 100 pF
VOH =2.2V. VOL =065V
MIN.
TYP.
MAX.
UNIT
-
-
ns
ns
ns
-
-
-
450
450
150
20
150
-
ns
MIN.
TYP.
MAX.
UNIT
-
-
650
-
650
20
150
-
ns
ns
ns
ns
MIN.
TYP.
MAX.
UNIT
-
-
800
20
200
ns
ns
ns
ns
TC6514P·1
SYMBOL
PARAMETER
tACe
teo
Access Time
CE Access Time
tOlS
Output Disable Time
Output Enable Time
teOE
CONDITIONS
VOO -4.5-5.5V
CL = 100 pF
VOH
=2.2V. VOL ~ 0.65V
150
TC6514P·2
SYMBOL
CONDITION S
PARAMETER
tACe
Access Time
teo
CE Access Time
tOIS
Output Disable Time
teoE
Output Enable
'--==-_..J'---'-_
_ _Time
__
Voo - 4.5 - 5.5V
CL -100 pF
VOH
=2.2V. VOL =0 .65V
---
- 102-
-
800
200
-
:
•
,,-'
•
R.... Cycle(1)
____~-d~;=.::::::::::.:A=C::::::::::;::t
ADDRESS
I
• Write Cycle 1 IRIW Controll...)
ADDRESS
_(2)
CE
AIW
DOUT
• Writ. Cycle 2
Ice Controll... )
ADDRESS
AIW
DOUT
Note.: (1) F4/W Is high for _ R-.d Cycle.
(2) If the CE low t,.n,ltlon occurs ,lmulteneou,ly with the A/W low tr.n,ltlon. the output
bufftl,. remeln In _ hltlh Impedance It. . .
- 103-
18 17 16 15 14 13 12 11 10
Unit In mm
RIO
123466789
x
"
:Ii
.
22.8 MAX
o
2.54±0 25
o.e±015
In
"
Note.
Now:
EMlh Iud pitch II 2.5....... m. Allleedl e,. 10cllUld within 0.25mm of their true longitudinal
polltlon with respect to No.1 end No. 181eMl..
T~.'"
the
C_.. ,.
not _nne • ., NIPOftIIbIII'CY for UI8 of • ., circuitry cl8earltJcl; no circuit pa-.t licentea .... Impl.... end TOI....
... eny time without notice. to .........Id circuitry.
T_bleo_1on
- 104-
......vel
1024 WORD X 4 BIT CMOS STATIC RAM
TC5514AP-2/-3. TC5514APL-2/-3
TC5514AD-2/-3. TC5514ADL-2/-3
SILICON GATE CMOS
r
IIIE
The TC5514AP/AD is a 4,096 bit high speed and
low power static random access memory organized as
1,024 words by 4 bits using CMOS technology, and
operates from a single 5-volt supply.
The TC5514AP / AD is compatl ble with the industry produced NMOS 2114 type 4KRAM, yet offers a
more than 90% reduction In power of their NMOS
equivalents.
The TC5514AP/AD IS a fully CMOS RAM, therefore it is SUited for use in low power applications
where battery operation and battery back up for
nonvolatility are required Furthermore the TC5514
APUADL guaranteed a standby current equal to or
less than 111 A at 60· C ambient temperature is available
The TC5514AP/AD IS guaranteed for data retention at a power supply as low as 2 volts The TC5514
AP/AD is directly TTL compatible In all Inputs and
outputs
The TC5514AP/AD IS offered in both standard 18
Pin plastiC and cerdip packages, 0.3 inchs in width
1111 I I II
• Standby Current
0.2I-
,.
V'H
i
/
,.
,.
"..,.,..
-- -"..,.,..
1.0
4
I
V'H
i
"."..,.,.."
1••
I
oJ
1••
--~
1.0
•
-40
VOO(V)
- 109-
o
V'L
I
40
T.,"C)
80
I
,.
1000 VS. Te
1000 VS. Voo
'2
'0
Voo- B.SV
teyel.- 1,.s
tcyel.- 11&S
8
I
r---
I
I
--... VIN - 2.2V,08V
VIN - 2.2V, O.BV
I
•
Te" 2SoC
./
I '" Y"
VIN" VOO-o.2V, 0.2V . /
I
/
I
4
VIN" B.3V, 0.2V
~
I
I
0
-40
6
4
80
VOO tV)
1000 VS. tcyel.
100S VS. VOO
Voo- s.sv
Te·2~C
VIN" 2.2V, O.BV
"g
!
Voo-a.6V
T.- 2SoC
\
8
8
i'-... ...........
9
4
r-- r--
-
~
4
--
f..--
-
_r---
3
o
4
leyel. (US)
VOO (V)
100S VS. VIN
•
IOH VS. VOH
-30
VOO-4.SV
T.- 25°C
VOO- S.5V
ce- S.BV
_ '0
-20
i
""'" "'-
C
l!!
!
i\
9
•
J
J
l:
9
-'0
\
"\
---
•
2.0
VIN tv)
" "'3.0
- 110-
"
40
VOH (V)
5.0
IOL VS
VOL
60
VDO • 4.I5V
Te.215oC
0
•
/"
!
oJ
9
0
V
1/
o
/'"
/
0.6
1.0
1.5
VOL (V)
~D' &.IV
CE • I.IV
V
100
/
60
V
0
/
6
3
I
o.
•
o.3
o. 1
-40
[7
/
V
o
80
- 111-
I
• PLASTIC PACKAGE
·,,1::::::]]
18 17 16 15 14 13 12 11 10
123456789
Unit Inmm
..x
::!
22.8 MAX
~----------------.:~~
o
"'
2.54±O.25
D.S±OlS
...
Itt
• CERDIP PACKAGE
[:::::::1]
1234187.,
228MAX
214TVP
112iOH
EM:h .... pitch" 2 14......" All ........ IQ~ within 0 21mm of the.r l/H9tucf.N' ~tlon
wlttll'..-cttoNo 1 .... No , . . . . .
All dIIn-* _ _ 1ft mllllm......
Notes
C> Oct.,
Toshiba don not ...um. any reaponllbllltv for u.. of any circuitry deICrlbed; no circuit patant 119.,... .r. Implied, and Toshiba,......,.. the
fight, at any tim. without notice, to eMftO': .Id circuitrY.
1981 Toshiba Corporation
- 112-
1024 WORD
x 4 BIT
TC55.13AP-2/TC5513APL-2
TC5513AD-2/TC5513ADL-2
CMOS STATIC RAM
SILICON GATE CMOS
PRELIMINARY: The specification limits are subject to chanlll without notice.
The TC5513AP/AD is a 4,096-bit high speed static
random access memory organized as 1,024 words by
4 bits and operates from a single 5-volt supply.
The TC5513AP/AD is a fully CMOS RAM and is
therefore suited for use in low power applications
where battery operation and/or battery back up for
nonvolatility are required. The TC5513AP/AD is
guaranteed for data retention at power supply voltage as low as 2.0 volt. All inputs and outputs are
TTL compatible.
The TC5513AP/AD is packaged in a standard 18pin dual-in-line plastic and cerdip package, 0.3 inch
width.
• Low Power Dissipation
27.5m W/MHz (MAX.):Operating
• Standby Current
O.2/lA (MAX.) at Ta= 25°C_}
1.0/lA (MAX.) at Ta = 60°C TC5513APUADL
• Data Retention Supply Voltage
2V to 5.5V
• Fu IIy Static Operation
• On-chip Address Transition Detector
• Three State Outputs
• Inputs and outputs Directly TTL compatible
• Plastic DIP: TC5513AP-2/APL-2
Cerdip DIP: TC5513AD-2/ADL-2
20/lA (MAX.) TC5513AP/AD
• Fast Access Ti me
tACC: 200ns (MAX.)
• Single 5V Power Supply
• • • • • • • • (TOP VIEW)
voo
,
A,
A.
A.
A.
A.
Datal/O l
Data 110,
Data 1/0'
Data 110"
'1..:_ _ _::t' R/W
A,,-A,
AIW
Address Inputs
Read Write Input
CE
Data 1/0,--4
Chip Enable Input
VDD/GND
Power Supply Terminals
A.
.~
A,
A.
11.
~~
or
a: a:
~
".
~i
JO
o¥
a:C
Memory can
Array
(64 x 64)
A,
0 1/0 1
o---+~---l
0110,
O---+-+r----j _ __
I
ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
Voo
RATING
Power Supply Voltage
-03V-70V
VIN
Input Voltage
-0.3V - Voo + 0.3
VitO
-03V-Voo +03
Po
Input/Output Voltage
Power DissipatIOn (Ta = 85'C)
TSTG
Storage Temperature
0.8W (0.45W) *
-55'C - 150'C
TOPR
Operating Temperature
-30'C-85°C
TSOLDER
Soldering Temperature Time
260°C
10 sec
'Plestic FP
".J•• :,:~_:
SYMBOL
PARAMETER
VOO
Power Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Data Retention Voltage
SYMBOL
MIN.
PARAMETER
-
Voo + 0.3
V
0.8
2.0
-
5.5
V
V
MAX.
UNIT
-
:1:1.0
±5.0
IJ.A
-1.0
-2.0
rnA
VOL - O.4V
2.0
3.0
-
CE, - 2.2V
-
1.0
3.0
rnA
-
0.2
0.05
1.0
-
5.0
30
40
70
30
55
I/O Leakage Current
Cl:,
10H
Output High Current
VOH = 2.4V
i()L
Output low Current
CE",
= VIH, OV $; VitO $; Voo
= Voo -0.5V
Standby Current
VOO =2-5.5V
CE",
CE",
10002
V
2.2
-0.3
TYP
ILO
Operating Current
UNIT
-
o$; VIN $; Voo
10001
5.5
MIN.
Inpu~ Leakage Current
100S2
MAX.
5.0
CONDITIONS
IlL
100S'
TYP.
4.5
= OV, VIN
TC5516APL/
Ta - 25°C
ADL/AFL
Ta = 60°C
-
Ta = 25°C
-
TC5516API
AD/AF
Ta = 60°C
Ta = 85°C
VIHNIL , lOUT -OrnA
= OV, VIN = Voo/GND, lOUT = OrnA
Note: Typical values are at Ta = 25°C, Voo = 5V.
PARAMETER
Input Capacitance
Input/Output Capacitance
Note: This parameter is periodically sampled and is not 100% tested.
- 120-
iJ.A
rnA
1.0
IJ.A
rnA
e RoadCycle
TC5516AP-2/APL-2
TC5516AD-2/ADL-2
TC5516AF-2/AFL-2
PARAMETER
SYMBOL
TC5516AP/APL
TC5516AD/ADL
TC5516AF/AFL
UNIT
MIN
MAX.
MIN.
200
-
250
MAX.
-
ns
Access Time
-
200
250
ns
CE I to Output Valid
-
100
ns
200
-
250
ns
tRC
Read Cycle Time
tACC
tCOI
tc02
IT2
!cOE
CE I or IT2 to Output Active
10
-
10
-
ns
too
Output High-Z form Deselectlon
-
BO
-
BO
ns
tOH
Output Hold from Address Change
10
to Output Valid
100
ns
10
e Wrote Cycio
TC5516AP-2/APL-2
TC5516AD-2/ADL-2
TC5516AF-2/AFL-2
PARAMETER
SYMBOL
Write Cycle Time
MIN.
MAX.
200
160
-
twc
twp
Write Pulse Width
tAW
Addresss Set Up Time
0
tWR
Write Recovery Time
10
toow
Output Hlgh-Z from R/W
-
80
tOEW
Output Active from R!W
10
-
tos
tOH
Data Set Up Time
80
-
Data Hold Time
Output Load
Input Pulse Levels
Timing Measurement Reference Levels
Input
Output
I nput Pulse Rise and Fall Times
0
100 pF + ITTL Gate
0.6V,2.4V
0.8V and 2.2V
0.8V and 2.2V
10ns
'RC
eRead Cvcle
Addr.....
DOUT
- 121-
TC5516AP/APL
TC5516AD/ADL
TC5516AF/AFL
MIN.
250
UNIT
MAX.
-
ns
-
80
ns
10
-
ns
120
-
ns
0
-
ns
200
0
10
ns
ns
ns
I
• Write Cycle 1
Addr.....
AIW
DOUT
DATA IN STABLE
• Write Cycle 2
Addresses
AIW
DDUT
------------------~~>-----------+-+---------------------
DATA IN STABLE
~
UNKNOWN
- 122-
':".""
.. :
;'
NOTE
(1) R/W IS high for a Read Cycle
(2) twp IS specified as the logical "AND" of CE 1, CE2 and R/W.
twp IS measured from the latter of CE 1 , CE 2 or R/W going low to the earlier of C E 1 , CE 2 or R/W
going high.
(3) tOH, tos are measured from the earlier of CE 1 , CE2 or R/W going high.
(4) If the CE 1, or CE2 low transition occurs simultaneously with or latter from the R/w low transition
in a Write Cycle 1, the output buffers remain in a high Impedance state in this period.
(5) If the CE 1 or CE2 high transition occurs prior to or simultaneously with the R/W high transition
In a Write Cycle 1, the output buffers remain In a high Impedanoe state in this period.
(6) If the R/W IS low or the R/W low transition occurs prior to or simultaneously with the CE 1 or
CE2 low transition, the output buffers remain In a high Impedance state in this period.
(7) A write occurs during the overlap of a low CE 1, low CE2 and low R/W. In write cycle 2, write IS
controlled by either CE 1 or CE2.
~~!Jl1!r!lr;~~~T.';; ~ ::~ :~:::lr;~;:~;~:!r ~
SYMBOL
PARAMETER
Data Retention Power Supply Voltage
VOR
Standby Current
loos
TC5516APL/
Ta -25·C
AOL/AFL
Ta = 6O·C
TC5516AP/
AO/AF
=25·C
Ta = 60·C
Ta =B5·C
Ta
From Chip Oesalectlon to Data Retention Mode
tCOR
tR
Recover Time
Note (1) tRr
MIN.
TYP.
2.0
-
-
0
tRC III
-
MAX.
55
-
1.0
10
-
5.0
-
V
0.2
0.05
-
UNIT
p.A
30
-
p.s
p.s
Read Cycle Time.
VOD--------------~
DATA RETENTION MODE
VOD-O.5V
VIL
GND----_________________________________________________________________
Not.: (2)
If the VIH ,...,., of CEl'S 2 2V, durlnvth. period thatth. VDD voltage 's going down from 4.5V to 2.7V. ISSD1 curr.ntfloWL
(Ref.r to D.C. CHARACTERISTICS or TYPICAL CHARACTERISTIC FIGURES.)
- 123-
te01
200
YL
Voo
T .... 2&oC
T. - 2SOC
25.
CL'" 100pF
CL- 100pF
15.
200
!u
""'"
u
!-
16.
100
!
§
...........
" .....
100
50
r--
•
4
-
4
Voo (V)
Voo (V)
tAce te01 VL Te
8.
1.4
VOO-4.6V
CL - 100pF
Te- 215°C
8.
o1.2
...
./
11
~
i
VetS'- 4.6V
tcOl~
t:/'
..,... V
~ P.::"cc
I .•
I
~
... '7
z
•.8
2.
/
./
./
-4.
•/
8.
./
100
V
200
300
400
&00
CL (pF)
2.5
T .... 25°C
~ 2.0
oJ
>
:i
-> 1.6 ..........
I .•
4
--
V
V,H
--
V,L
~
...-
..........
2 ••
VIH. VOO
0=
5.BV
~> 2··t:t=EE:f;I::cr=J
-- ---
~ 1.61---+--+---+--+--+--+---+--1
7
5
1---+--+--+-+---1
VIL, Veo'" 4.6V
.......
•
8
Veo tV)
- 124-
8.
IOOOVL T.
1000 YL Voo
80
VOO-5.6V
70
ee2 - OV
0
CE2-0V
Ta - 26 C
60
~
!
o
o
E
7'
40
7
--- v
20
0
7
C
60
"-
!
o
/'
o
E
.......
&0
..............
-
r--.......
40
4
•
0
voo(V)
80
-40
..0
90~__~__~__~~ID~D~O~~~t~cy~c~'.____________~
IODS1 VL VOO
Ta-26Dc
3.0
eE2" 2.2V
70~--+---~--~--~---+---.---.--~
~
!
~
E
~
0
•
O.
o.3
30~--4----+--~----~--4----+--~--~
1.0
1.
/
,/"
/
100S1 VL Te
IODS2VL VOO
Voo -5.BV
Te-2SDc
ee2" 2.2V
.......
-O.B-2.2V
"'ii;;
1.2
eE2 - Voo -D.SV
other Inpu1S
1.4
~
r.........
t--.......
E
-
!
1.0
o
3.2
8
E
j-...
-40
8
8
VooCV)
1.8
~
_ o.a_Z.2V
V
tcycla (us)
!
otMrlnputl
V
o. 1
0.0
I"-
3.0
1...-- I--
~
1002.8
80
4
•
VOO(V)
- 125-
-
~
IODS2
2.0
'.5
\
1 '.0
Voo - 6.5V
- O.B_2.2V
1 '0~--+----+---+~--~--4----r---'--~
:g
r\.
"
0.5
0
'.0
'.0
other Inputs
T. - 26°C
""'\
9
VIN CCl"2)
30~--+---~---+~--~--~
-Q.S-2.2V
Ta- 2&oC
fj
Yt.
60r=.+:::::::!r==t=+=T~--:-:~1
VOO-I5·5V
other Input'l
.~--+----+---+-t--~--4----+---i---;
9
" """
4.0
\
5.0
3.0
5.0
4.0
6.0
IOH va. VOH
-'0
Voo" 4.5
IODS2 va. T.
VOO- 6.5V
500
CE2 - 5.0V
300
•
-.
Ta" 2SoC
5
~ I-.....
E
-; -1 0
f':
9
/
.00
J
II
50
30
5
7
3
'.0
•
I
3.0
2.0
20
7
••
/
""" "
4.0
.J
9
I
f7
V
/
VoO'" 4.BV
T." 26°C
7
110
V
• J
"'-
VOH (V)
/
o. 5
O.
-40
0
/
.0
0.3
5
/
)
o
o
80
7
o
0.4
08
VOL (V)
- 126-
'.2
,
,
,
,
•
;.~'"
~,
.;..,.a;,,~.m.;;'lii<",,';;'~~
·~:f~'~
• Plastic DIP
~~:::]]
1
2 3 4 5 6 7 8 9 1011 12
2.54 ±0.26
CJ
i. 1::1,
I.
1.4±0.115
0.I5±o.16
17.< MAX.
.,;
.
• Cordip DIP
32.4 MAX.
~~~3]
1 2 3
4 5 6 7 8 9101112
z
;~.
; I
:I
~ 1025+0.,. ~
1
z
..
i
Note.
'''2< to.'
.
-0.'0
' .. 24_17.7.
I
eech Iud pitch's 2.54mm. AIII ..ds ere located within O.25mm of 'their 'true longlwdlne' pOiltion WI'th r.pect"tO No. 1 end
No. 24 ,..eta. All dlmen.lons ere In milltm.nrs.
- 127-
./
:
......
..
~'
"
, ..
i
.'
",'<•
'I"
• Platl. FP
J
~
N
+--+..."
-+---''-.I.(
--11.0.•• ±0.06
16.& MAX.
NoW:
Eech ,..d pitch I. 1.27mm.
AlllNda .r. locned within O.1rnm of their tN. longitudinal pOiltion with r.pect to No.1 and No. 24 Iud..
- 128-
tj
.,..~
•
~',
.> (".
N
This new flat package is a very small and thin compared with conventional standard dual-in-line package.
Differences are as follows.
1. Difference in dimension between flat and
standard package.
Flat package
Length
Width
Lead Pitch
Thickness
Unit mm
Standard package
16.5
9.0
1.27
1.6
3. Advantage of this package
•
•
•
4.
2. Comparison in occupied space_
DIP
32.4
14.2
2.54
5
D
Small dimensions
Capability of High Density Assembly
Capability of thin Assembly - Capability of Assembly on both side of PC board.
PC pattern layout example
- 129-
Note
©
Toshiba does not anume any responsibility for use of any circuitry described, no circuit patent hcenses are Implied, and Toshiba reserves
the right, at any time without nOtiCe, to change said circuitry
Apr., 1982 Toshiba Corporation
- 130-
51 LICON GATE CMOS
The TC5517AP/AD/AF IS a 16384-blt static random access memory organ Ized as 2048 words by 8
bits uSing CMOS technology, and operates from a
single 5 volt supply.
The TC5517AP/AD/AF IS featured by output
enable and chip enable Inputs, that IS, Cil: for fast
memory access and CE for a minimum standby current mode, and IS sUited for low power application
where battery operation or battery back up for non-
.fiAJ~
• Standby Current
o 2p.A (Max) at Ta = 25°C} TC5517APL/
1 O/lA (Max) at Ta = 60°C
ADL/AFL
1 O/lA (Max) at Ta = 25°C} TC5517 AP/
5 O/lA (Max.) at Ta = 60°C
AD/AF
• Low Power DIssipation . 200mW (Typ )
operating
• Single 5V Power Supply 5V ± 10%
• Data Retention Supply Voltage 2 0 - 5 5V
• Fully Static Operation
'PlI!I.,~OIf
volatility are reqUired Furthermore the TC5517APL/
ADL/AFL guaranteed a standby current equal to or
less than l/lA at 6Q°C ambient temperature IS available
The TC5517AP/AD IS also featured by Pin com
patlbility with 2716 type EPROM. This means
that the TC5517AP/AD and EPROM can be Interchanged In the same socket, and the flexibility
In the definition of the quantity of RAM versus
EPROM obtained as a result allows the Wide application In microcomputer system
• Access Time
250ns (Max)
TC5517AP/APL/AD/ADL/AF/
AFL
200ns (Max)
TC5517AP-2/APL-2/AD-2/
ADL-2/AF-2/AFL-2
Two Control Input (CE, DE)
Pin Compatible with Nch Static RAM TMM2016P
All Inputs and Outputs Directly TTL Compatible
Three State Outputs
Package
PlastiC DIP
TC5517AP/APL
Cerdip DIP
TC5517AD/ADL
Plast)c FP
TC5517AF/AFL
•
•
•
•
•
(TOP VIEW)
BLOCK DlAGMM.
A.
A,
R/W
CE
OE
A,
A"
~
110,
liD,
1/0 6
lIas
I/O ..
PIN NAMES
At, R/W
A,.
Address Inputs
ReadIWnte Control Input
OE
Output Enable Input
CE
Chip Enable Input
1/0, -1/0.
Data InputlOutput
Voo
GND
Power (+5V)
Ground
- 131-
I
ITEM
SYMBOL
RATING
VOO
Power Supply Voltage
-03V-70V
Y'N
VI/O
Po
Input Voltage
-0 3V- Voo+O 3V
Input/Output Voltage
-0 3V - Voo+O 3V
08W 10 45W)*
Power 0 ISSI pat Ion ITa - 85 C)
TSTG
Storage Temperature
TOPR
Operating Temperature
-55 C-150°C
-30oC- 85°C
TSOLDER
Soldering Temperature· TIme
260 C • 10sec
* Plastic FP
__llIi.IIII•••
IIl••!.Jl_II
•_I
• ••II
•_M~
•
SYMBOL
MIN
TYP
MAX
UNIT
Voo
Power Supply Voltage
45
5.0
55
V
V,H
Input High Voltage
22
V,L
Input Low Voltage
-03
Voo+O 3
08
V
VOH
Data Retention Voltage
-
55
V
SYMBOL
PARAMETER
PARAMETER
Input Leakage Current
I'L
ILD
I/O Leakage Current
IOH
Output High Current
IOL
Output Low Current
100Sl
2.0
CONDITIONS
0" Y'N "Voo
CE = V,H. OV" VI/O" Voo
VOH = 24V
VOL =04V
CE = 2.2V
TC5517APL/ Ta = 25 C
100S2
Standby Current
cr = Voo - 05V
ADL/AFL
Voo = 2- 5 5V
TC5517AP/
AD/AF
10001
10002
Note
Ta = 60 C
Ta = 25 C
Ta = 60 C
Ta = 85 C
CE = OV. Y,N - V,HN,L • lOUT - OrnA
Operating Current
-
TYPical values are at Ta - 25
CE = OV. Y,N = Voo/GND. lOUT = OrnA
C. Voo -- 5V
- 132-
MIN
TYP
-
-
-10
-20
20
-
V
MAX
±10
UNIT
pA
t50
pA
rnA
30
-
10
30
rnA
-
02
rnA
10
005
10
-
-
50
-
40
30
70
pA
30
55
rnA
• ReadCycle
t~gg~bYIX'de2
PARAMETER
SYMBOL
tRC
Read Cycle Time
tACC
Access Time
tOE
iJE" to Output Valid
TC5517AF-2/AFL-2
TC5517 AP/APL
TC5517 ADlADL
TC5517AF/AFL
MIN
MAX_
MIN_
200
-
250
-
200
-
tco
cr to Output Valid
-
tCOE
OE or CE to Output Active
10
too
Output Hlgh-Z from Deselectlon
-
tOH
Output Hold from Address Change
10
100
200
-
-
10
80
-
-
10
UNIT
MAX
-
ns
250
ns
100
ns
250
ns
-
ns
80
ns
-
ns
• Write Cycle
SYMBOL
PARAMETER
t~~r
T
17 AP-~f'PL-2
AD-2/ADL-2
T
17AF-2/AFL-2
MIN
twc
twp
MAX.
Write Cycle Time
200
Write Pulse Width
150
-
TC5517AP/APL
TC5517AD/ADL
TC5517AF/AFL
MIN.
MAX
250
-
200
Address Set Up Time
Wnte Recovery Time
0
-
0
tWR
10
-
10
toow
Output Hlgh-Z from R/W
-
80
tOEW
Output Active from R/W
10
tos
Data Set Up Time
80
-
tOH
Data Hold Time
tAW
. .D''';'
0
10
120
0
~~J.r
Output Load
Input Pulse Levels
Timing Measurement Reference Levels
Input
Output
Input Pulse Rise and Fall Times
lOOpF + lTTL Gate
O.6V, 2 4V
O.8V and 2.2V
O.8V and 2.2V
lOns
.~~~
• Read Cycle (1)
Addr....
- 133-
\(OH
OUTPUT
VOL
DATA VALID
-
UNIT
ns
ns
ns
-
ns
80
ns
-
ns
ns
ns
I
•
Write Cycle 1 (1)
Addr. . . .
R/W
•
Write Cycle 2 (2)
Addr.....
R/W
DOUT
~:
UNKNOWN
- 134-
NOTE
(1) R/W IS high for a Read Cycle.
(2) OE = V,H or V,L If OE = V,H during write cycle, the output buffers remain in a high impedance
state.
and R/W.
(3) twp IS specified as the logical "AND" of
twp is measured from the latter of CE of R/W gOing low to the earlier of CE or R/W going high
(4) tOH, tDs are measured from the earlier of CE of R/W gOing high
(5) If the CE low transition occurs simultaneously with or latter from the R/W low transition In a Write
Cycle 1, the output buffers remain In a high Impedance state In this period.
(6) If the CE high transition occurs prior to or simultaneously with the R/W high transition In a Write
Cycle 1, the output buffers remain In a high Impedance state in this period
(7) If the R/W is low or the R/W low transition occurs prior to or simultaneously with the CE low
transition, the output buffers remain In high Impedance state In this period
cr
PARAMETER
SYMBOL
Data Retention Power Supply Voltage
VDR
Standby Current
IDDS2
TC5517APL/
Ta - 25°C
ADL/AFL
Ta = 60°C
TC5517API
AD/AF
Ta = 25°
Ta - 60°C
Ta - 85°C
tCDR
From Chip Deselectlon to Data Retention Mode
tR
Recovery Time
Note (1) tRC
Read Cycle Time
MIN
TYP
MAX
UNIT
20
-
55
V
-
02
10
005
10
-
50
-
-
30
0
-
-
/lS
-
p.s
tRc( 1)
/lA
DATA RETENTION MODE
VDD--------------~
VOO-05V
GND----------______________________________________________________________
Note
(2)
If the VI H level of CE 152.2V, dUring the penod that the VOO voltage IS gOing down from 4 5V to 2.7V, IODS1 current flows
- 135-
I
• Plastic DIP
~:::~j]
1
2
3 4
6
6
7
8 9 101112
• eenlip DIP
32.4 MAX.
~~~j-l
1 2
3
4
5
6
7 8
9101112
I
15.24+0.3
10.25:g:1&
/. 15.24-17.7.
I
,
I
Note. each lead pitch Is 2,54 mm All leads afe locaTed wlt:h,n 0.25 mm of their true longitudinal position Wltn respect to No 1 and No 24 leads
All dimenSions are In mllhmeters.
- 136-
• Plastic FP
N
..g
.;
0-1.27
II
16.5 MAX.
Note: each lead pitch I, 1.27 mm.
All 'elld. are located within 0.1 mm of their true lonllttudlnal position with respect to No 1 and No. 241eadL
- 137-
0.15tO.06
This new flat package is a very small and thin compared with conventional standard duai-]n-Ilne package
Differences are as follows.
Difference
package
In
dimension between flat and standard
Unit
Flat package
2. Comparison In occupied space
mm
Standard package
Length
16.5
324
Width
9.0
14.2
Lead Pitch
127
254
Thickness
1.6
5
DIP
D.
3. Advantage of this package
Small dimensions
Capability of High Density Assembly
Capability of thin Assembly--Capability of Assembly on both side of PC board
4. PC pattern layout example
Note
Toshiba ~ '8' not assume anV responslbllltv for use of any circuitry descrIbed, no CirCUIt patent hcenses are Implied, and Toshiba reserves
the right, at any tim. Without notice, to change said Clrcultrv
©Nov. 1981 Toshiba Corporation
Distributed by
- 138-
TC5517BP, TC5517BPL
2048 WORD x 8 BIT CMOS STATIC RAM
TC55I 7BD, TC55I 7BDL
TC55I 7BF, TC55I 7BFL
SILICON GATE CMOS
The TC5517BP/BD/BF IS a 16384-blt high speed
and low power fully static random access memory
organized as 2048 words by 8 bits usmg CMOS
technology, and operates from a smgle 5 volt supply.
The TC5517BP/BD/BF has a output enable mput
(OE) for fast memory access and output control and
chip enable mput (CE) which IS used for device
selection and can be used m order to achieve the
mmimum standby current mode easily for battery
back up.
Also the high speed and low power characteristics
which maximum access time IS 200ns and maximum
operating current IS 5mA/MHz are achieved.
Thus the TC5517BP/BD/BF is most suitable for
use in low power applications where battery operation
or battery back ·up for nonvolatility are required.
Furthermore the TC5517BPL/BDL/BFL guaranteed a
standby current equal to or less than l/lA at 60°C
ambient temperature available.
And the TC5517BP/BD IS pin compatible with
2716·type EPROM. This means that the TC5517BP/
BD and EPROM can be mterchanged in the same
socket, and the flexibility in the definition of the
quantity of RAM versus EPROM allows the wide
application m microcomputer system.
• Fast Access Time
tACC = 200ns (Max.)
tOE = 70ns (Max.)
• Output Buffer Control. OE
• On-chip Address Transition Detector
• All Inputs and outputs Directly TTL Compatible
• Three State Outputs
• Package
Plastic DIP TC5517BP/BPL
Cerdlp DIP. TC5517BD/BDL
Plastic FP TC5517BF/BFL
• Low Power Dissipation
27.5mW/MHz (Max.) Operating
• Standby Current
0.2/lA (Max.) at Ta = 25°C) TC5517BPL/
1.0/lA (Max.) at Ta = 60°C BDL/BFL
1.0/lA (Max.) at Ta = 25°C } TC5517BP/BD/
5.0/lA (Max.) at Ta = 60°C BF
• Smgle 5V Power Supply 5V±10%
• Data Retention Supply Voltage 2.0 - 5.5V
• Fully Static Operation
(TOP VIEW)
A7
VDD
A6
As
As
A4
Ao -- A 10
RNV
DE
CE
I/O, -1/0 8
A9
A/W
A,
DE
A,
A,
CE
A,.
A.
I/Og
1/0 1
1/07
1/02
1/06
1/0 3
1/0 5
GND
1/04
Address Inputs
Read/VVnte Control Input
1/0 8
Output Enable Input
____________________
"'~--.
Chip Enable Input
Data Input/OutPut
VOD
Power (+5V)
GND
Ground
RM~~~=>
CEO-
139 -
~
I
1II1i_ _Il'
MODE
Read
Write
IT
DE
L
L
L
H
L
.........
Output Deselect
**Standby
SYMBOL
VDD
VIN
VIO
PD
TSTG
TOPA
TSOLDEA
R/W
H
L
-
A.-A,
Stable
Stable
H
I/O
Data Out
Data In
High Impedance
High I rnpedance
POWER
I
ID
IDDO
IDDS
* H or L
Data Retention Mode
Note
ITEM
III
RATING
-0 3V -7 OV
-0.3V - V DD + 0 3V
-0.3V - VOD + 0 3V
o 8W IOA5W) •
-55'C - 150'C
-30'C - 85'C
260 'c 10 sec .
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation (Ta 85 C)
Storage Temperature
Operating Temperature
$oldenng Temperature Time
• Plastic FP = 0 45W
...
SYMBOL
VDD
VIH
VIL
VoH
PARAMETER
Power Supply Voltage
Input High Voltage
MIN
45
2.2
03
20
Input Low Voltage
Data Retention Voltage
TYP
5.0
-
III II• •I.~~~"-~.~"
PARAMETER
SYMBOL
CONDITIONS
IlL
ILO
10H
IOL
IDoS1
Input Leakage Current
I/O Leakage Current
OutPut High Current
Output Low Current
O--
VppO--<>NO 0 - -
-j
I
~~: vpp~wer Supply
0,
0_
13 0,
I
--
Outputs
1 Chip Select
_
j
vpp
MODE SELECTION
~PD/PGM
MODE
Read
Deselect
Power Down
Program
Program
(18)
I
CS
(20)
Vpp
(21)
I
Vee
(24)
. .
VIL
VIH
5v15v
5V
5V
5V
5V
i VIH
25V I 5V
V,L
1 VIH
iJlJL V,H
V,L
Verify
i
V,L'
I VIL
25V
Program
Inhibit
I
V,L
i VIH
25V 15V
*
i
5V
Outputs
19-11. 13-17)
Dout
High Z
High Z
D
o
,
In
It
1
r
•
,
16384 bit Memoly Cell
( 28 ~ow
out
16 Column x a
I
High Z
:
VIL or VIH
- 173-
bT
:
!
UNIT
RATING
SYMBOL
ITEM
-0.3-+7
V
VPP Supply Voltage with respect to Ground
Vcc
Vpp
-0.3-+26.5
V
All Input Voltages with respect to Ground
VIN
-0.3-+7
V
All Output Voltages with respect to Ground
VOUT
-03-+7
Power Dissipation
PD
Vcc Supply Voltage with respact to Ground
V
W
°C . sec
15
TSOLOEA
260·10
Storage Temperature
TSTG
Operating Temperature
TOPA
-65-+ 125
0-70
Soldering Temperature Times
..-.•
·C
·C
._----
~~
~
PARAMETER
SYMBOL
Power supply
Vec
(1,2)
Power supply
Vpp
(2)
TYP
MAX
475
5
525
V
TMM323D'1
45
5
55
V
I
III
:
ILO
Ipp,
Vcc Current (Stand_by)
:
Icc,
Vcc Current (Active)
I
Icc.
~t Leekage Current
(Reed)
~------
5
Vcc-O 6
SYMBOL
PARAMETER
I nput Load Current
VPP___
Current
c------'--'
MIN.
TMM323D
Input Low Voltage
Input High Voltage
I--::-'-- - -----
VIL
-01
VIH
2.0
Output Low Voltage
VOL
Output High Voltage
VOH
TYP. C31
MIN.
MAX.
VCC +06
IJ,A
IJ,A
5
rnA
10
25
mA
57
100
mA
0.8
V
VCC + 1
0.45
V
2.4
,
V
CONDITIONS
UNIT!
±10
±10
UNIT
VIN =525V
VOUT = 5.25V/0.45V
Vpp =585V
PD/PGM - VIH, CS =VIL
I
PDIPGM - CS - VIL
V
IOL =2.1mA
V
IOH =-400IJ,A
Ta = 0 -70·C, Vpp = Vce ± 0.6V
PARAMETER
SYMBOL
TMM323D
MIN
MAX
TMM323D-l
MIN.
MAX
UNIT
CONDITIONS
Address to Output Delay
tACC'
450
350
ns
PD/PGM· ~ - VIL
PD/PGM to Output Delay
tACC'
teo
450
350
ns
CS -VIL
Chip Select to Output Delay
120
120
ns
PD/PGM = VIL
PD/PGM to Output Float
tpF
0
100
0
100
ns
Chip Deselect to Output Float
tDF
0
100
0
100
ns
CS = VIL
PD/PGM = VI
Address to Output Hold
toH
0
ns
PDIPGM = CS = VIL
0
• A.c. Tilt Condition.
Output Load: ITTL + lOOpF
Input Rise and Fall Times (lCl%-90%) : ~ 20ns
Input Pulse Levels: VIL - 0.8V, VIH ·2.2V
Tim ing Maesurement Reference Level Inputs 1V & 2V, Outputs 0.8V & 2V
- 174-
(Note 4)
~rtANCI
Ta = 25°C,f= lMHz
PARAMETER
I
SYMBOL
I
Input Capacitance
C,N
I
Output Capacitance
COUT
I
A. Read Mode
I
Min
I
I
LIMITS
Typ
I
Max.
I
I
4
B
CONOITIONS
UNIT
. 6
pF
Y,N =OV
12
pF
Vout=OV
PO/PGM - VIL
Addr...
teo
12Onl)
MAX
tAce.
(460n.MAX)
Output _ _
~H:!!I'!!h.!Z__~~(==~D~"~.~O~U~'~V~.'~I.~==~~~__
B. Standby Mode
Addr... ---------,_~------------AddreaN+m
po/PGM
-=~~~~~)~-t!!!~=~~t~·"~V~.;II.~~~~
+
Output _
Note
for Add,... N
Vee ~
Vee mUlt be applied SImultaneously or before Vpp and cut off simuttanltOUily or after Vpp _
1
High Z
m
The Vpp tarmlnall. permitted to connect the Vee terminal directly dUring non-programming.
V ...
~
Typlca' veluM .r. at Ta .. 2SoC and nomina' supply volt.get
4. This parameter'l periodically ump'" and I, not 100% telted.
6 The tACC2 'I • output data dalay tim. (I e. ace•• time) from add,.. or PD/PGM whichever changes late.
Ta = 25°C±5°C, Vee = 5V±5%, Vpp = 25V± IV (Notal. 2, 3)
94_" . _
L __
~.~
SYMBOL
PARAMETER
I
Input Current
Vpp Supply Current
Vpp Supply Current
During Programming Pulse
Vee Supply Current
I nput Low Level
Input HIgh Level
.. ~.
-
MIN
TYP.
MAX.
UNIT
CONDITIONS
IlA-- I-VIN =5.25V/045V
III
Ipp,
±10
5
rnA
PD/PGM = V,L
Ipp,
30
rnA
PD/PGM =V,H
rnA
lOUT =0 rnA
lee
V,L
V,H
100
-01
20
- 175-
- I--~-~
Vee+ 1
--':I_- I - V
I
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
Address Setup Time
tAS
2
p.s
es- Setup Time
tess
2
p.s
Data Setup Time
tos
2
p.s
Address Hold Time
tAH
2
p.s
tesH
2
p.s
tOH
2
Chip Deselect to Output FloatDelay
tOF
0
Chip Select to Output Delay
teo
tpw
es Hold Time
Data Hold Time
-- --
Program Pulse Rise Time
tPAT
45
5
Program Pulse Fall Time
tPFT
5
Program Pulse Width
•
MIN.
CONDITIONS
p.s
50
120
ns
PDIPGM = VIL
120
ns
PD/PGM
55
ms
= VIL
,
ns
ns
A.C. Test Condhlon.
Input Aise and Fall Times (10% - 90%) • 20ns
Input PuiS. Levels: VIL· O.BV, VIH e2.2V
Timing Measurement Aeference Level. Input 1V & 2V, Output OBV & 2V
'£
-----.p
Vpp- HV±1V. vee -ev%I"
p'........
Ad....
0 ...
---;;I
PDIPGM
-------'iI'"
Note:
tpFT
(6n.MIN)
,. v cc mUll b. epplled tlmultaneou.ly 9' b.to... Vpp and cut off simultaneously or after VPP.
~
vcc-.J
,..--,
Vpp---J
L
L...-
2. Sometlm.. removing the device from socket and MUlng tha d..,lce In socket unci... the condition Vpp - 2&V ± 1 V may destroy Its
d..,lce. 10 It Ihould be noted during programming.
3. VI" Npply voltage I. permlt18d up to 28V programming. SO the voltaoll over 26V should not be applied to Vpp.
Partlcylerly when switching pul.. votUI' It applied to VpP. al.o the over-shoot volt. of Ita pul.. mould not be exCMded 28-volt.
- 176-
.. ',",
The TMM323D's memory cell data can be erased
by applying light with wavelengths shorter than 4000
A. (lA = 10-8 cm)
Sunlight and the fluorescent lamps may Include
3000 - 4000 A wavelength components
Therefore when used under such lighting for
extended periods of time, an opaque seal (Toshiba
EPROM Protecting Seal AC 901 etc) will be required
to protect the TMM323D Generally, ultraviolet light
with a wavelength of 2537 A IS recommended for
TMM323D-eraslng, and in this case the integrated
dose (ultraviolet light intenSity [w/cm') x time [sec])
should be over 15 [w sec/cm' ]
When Toshiba sterilIZIng lamp GL-15 IS used and
the device is exposed at a distance of l-cm from the
lamp surface, erasure should be completed in about
60 minutes.
And uSing a lamp whose ultraviolet light intensity
is a 12000 [IIw/cm') will reduce the exposure time
to about 20 minutes.
(In this case the Integrated dose should be 12000
[,lw/cm') x (20 x 60) [sec) '" 15 [w·sec/cm') )
~~:
TMM323D-operatlon-modes are classified Into SIX
types, as shown In the following table Each mode
can be selected by TTL level signals only. The VCC
and V PP power supplies required are only 5-volt for
read operation, and the Vpp power supply required IS
25-volt during program operation only.
~
MODE
Read
Read Operation
Deselect
Power Down
Program
Program Operation
Program Verify
Program Inhibit
PD/PGM
CS
Vpp
(18)
(20)
(21)
V,L
V,L
V,H
.
V,H
...f1.fL V,H
V,L
V,L
V,L
Outputs
Vce
(24)
(9-11,13-17)
.
5V
5V
D out
5V
5V
High Z
5V
5V
High Z
V,H
25V
5V
D
V,L
V,H
25V
5V
D out
25V
5V
High Z
10
* VIL or V,H
Read Mode
Deselect Mode-
Assuming that PD/PGM = V,L and CS = V'L, the
output data is available within tACCI (MAX.) after
stabilizing of the address.
And assuming that PD/PGM = V,H or CS = V'H, the
outputs wi II become high impedance in state
When all addresses are in the fixed state and CS =
V'L, the output data is available within tACC,
(MAX.) after the PD/PGM input is changes to V,L
from the V,H level (Outputs change to data available
state from a high impedance state.)
When all addresses are in the fixed state and PDI
PGM = V'L, the output data is available within tco
(MAX.) after the CS input is changed to V,L from
the V,H level. (Outputs change to data available state
from a high impedance state)
Assuming that CS = V'H, the outputs will be In a
high Impedance state So two or more TMM323Ds
may be tied together on the same data bus. And the
CS Input of the selected chip must be at the V I L
level, and that of the other chip must be at the V,H
level
- 177-
I
"-' Down Mode
Assuming that PD/PGM = VIH. the power dIssipation will be reduced to one-fourth of normal active
power. (Le.525mW -+ , 32mW)
Then all outputs will become high impedance in state
independent of the CS Input level.
Program Mode
Initially when received by customers all bits of the
TMM323D are in the "'" state which is the erased
state.
Therefore programming is carned out by electrical·
Iy writing in the "0" state at the desired bit locations.
Programming can be completed by applying the
TTL level pulse signal with a pulse width of from 45
to 55 ms to PD/PGM input under the condition
where Vpp = 25V and CS = VIH.
Programming the TMM323D is permitted in any
sequence and also at any particular bit location.
But the PD/PGM pulse width applied at one bit
location should be over 45ms up to 55ms. and
rewriting into the'written location is not permitted.
When programming is carried out by applying a
DC voltage (VIH level) instead of a pulse to the PDI
PGM input. erroneous writing may occur sometimes.
32i1MAXI
so a pulse whose recommended width IS 50ms shou·
be used in programming.
Programming the same data to two or more TMI
323Ds simultaneously can be accomplished by COl
necting the respective pins together.
Program Verify Mode
In this mode the Vpp power supply is 25V,
But assuming that PD/PGM = VI Land CS = VI L
it can be possible to read written data.
For normal read operation. the Vpp power suppl'
voltage required is 5V.
Program Inhibit Mode
Assuming that PD/PGM = VIL and CS =VIH under
Vpp = 25V. it is able to inhibit the programming.
According to the above. programming into two 0
more TMM323Ds mounted on a board will be pos
sible.
Programming into a desired chip tied on a commor
bus line independently is possible by connecting al
respective inputs except PD/PGM together and apply
ing a pulse to the PD/PGM input of a desired chip anc
applying DC voltage at the VI L level to the PD/PGtv
inputs of the other chip.
Note
to Each Ind pitch I. 2 54 mm.
All I••d, .re locaMci
within 0.26 mm of thalr true longitudinal pOiltion
with r-.:lect to No.1 end No. 24 I....
2
This valua
f. mauured at the end of lead •.
3. All dun.nllan••r. In mllltmMeF1.
,
2
3
..
5
II
7
•
,
L ",.to, I
I."~,,
\
I ,,,~::. I
NoU1
Note:
Toshiba does not DIU,.,. any retPonlfblllty for u. of eny circuitry dftcrlbed; no Circuit
the right. at MY tim. without notice. to change.kI circuitry.
@Jun., 11SO TOIhlbe Corporetion
- 178-
pa~nt
llcen....... l'1'plled. MId Toshiba .......ws
TMM323DI
TMM323DI-l
2048 WORD x 8 BIT EPROM
•._-
N CHANNEL SILICON STACKED GATE MOS.
The TMM323DI is a 2048 word x 8 bit ultraviolet
erasable and electrtcally programmable read only
memory
For read operation It reqUires a single
5-volt power supply only The maximum active power dissipation IS 525mW while the maximum standby
power dissipation IS only 158mW, a 70% savings.
Programming can be executed by applYing 25-volt
and 5-volt at the Vpp and Vcc terminals respectively,
and applYing a TTL level signal at the other Input
terminals Programming the one bit location reqUires
• Wide operating temperature range
Ta = -40 - 85°C
• Single 5-volt power supply
TMM323DI , 450ns (MAX.)
• Access time
TMM323DI-l 350ns (MAX.)
TMM323DI
Current 100mA (active)
TMM323DI-l
120mA (active)
30mA (standby)
only a Single pulse, and It IS pOSSIble to program
sequentIally, IndIvidually or at random Under the
condItIon Vpp = 25V, read operatIon IS perml11ed In
the program vertfy mode, and also programming IS
Inhlbl11ed by selecting the program InhIbIt mode
The TMM323DI IS fabricated with the N-channel
silIcon double layer gate MOS technology and IS
packaged In a standard 24-pm dual-In-Ilne cerdlp
package
•
•
•
•
•
Three state output
Particular b,t location programming
Programs With one 50ms pulse
Total programming t,me 100 second
Inputs and outputs TTL compatIble during read
and program
• Pin to pm compatible to 2716 type EP·ROM
~ILOCK. DIAGRAM
A.-A ,o
0 0 -0,
CS
PD/PGM
Vee, Vpp
GND
Addresses
Outputs
ChIp Select
I
VccO--VppO--
0000--
Powerdownl
Program
Power Supply
Ground
~---
~S
MODE
Read
Deselect
Power Down
Program
Program
Verify
Program
Inhibit
•
PD/PGM CS
(lB)
(20)
. .
V,L
V'L
V'H
V'H
JUL V'H
Vpp
(21)
Vee
(24)
5V
5V
5V
5V
5V
5V
Output.
(9-11,13-17)
Dout
HI9h-Z
HI9h-Z
IV'H
25V
5V
V'L'
V'L
25V
5V
00U1
V'L
V'H
25V
5V
H,gh-Z
V'L
i
I
I
Din
I
I
I
I
!
I
I
•
18384 bIt Memory Cell
28 Row x 16 Column JIt 8 bit)
! ! i i
! i I!
1
V'L or V'H
- 179-
! !
I
!
:
!
ITEM
SYMBOL
UNIT
RATING
-~-------
-0.3 - + 7
V
Vpp Supply Voltage with respect to Ground
Vee
Vpp
-0.3 - + 26.5
V
All Input Voltages with respect to Ground
VIN
V
All Output Voltages with respect to Ground
VOUT
-0.3 - + 7
-03-+7
Power Dissipation
Po
Vee Supply Voltage with respect to Ground
V
Tso LOER
260·10
W
°C . sec
Storage Temperature
TSTG
-65-+125
·C
Operating Temperature
TOPR
--40-85
·C
Soldering Temperature· Times
1.5
----
D.C. ond A.c. OPERATING CONDITIONS
PARAMETER
SYMBOL
Power supply
Power supply
Vee
(1.21
Vpp
(21
TMM323DI
TMM323DI·l
MIN.
TYP
MAX
UNIT
4.75
5
525
V
45
5
55
V
Vee-a 6
5
Vcc +06
V
Ta = --40 _ 85·C
PARAMETER
SYMBOL
Input Load Current
MIN.
MAX.
UNIT
tID
tlO
p.A
VIN =525V
p.A
VOUT = 5 25V10 45V
5
mA
Vpp - 5 85V
10
30
rnA
PD/PGM - VIH. CS = VIL
57
100
57
120
rnA
PDIPGM = CS = VIL
III
Output Leakage Current
Vpp Current (Readl
ILO
Ipp
Voc Current (Standby 1
Icc,
.ITMM323DI
Voc Current (Activel!TMM323DI_l
Icc.
Input Low Voltage
VIL
-0.1
Input High Voltage
VIH
2.2
Output Low Voltage
VOL
Output High Voltage
VOH
Ta = --40 _ 85·C. Vpp = Vee
Typ.(31
08
V
Vee + 1
045
V
24
CONDITIONS
V
IOL-21mA
V
IoH = --400p.A
to 6V
PARAMETER
SYMBOL
TMM323DI
MIN
MAX
TMM323DI-l
MIN.
MAX
UNIT
CONDITIONS
Address to Output Delay
tAee,
450
350
ns
PD/PGM to Output Delay
tAce.
450
350
ns
PD/PGM = CS = VIL
Cs = V IL
Chip Select to Output Delay
120
120
ns
PD/PGM=V
PD/PGM to Output Float
teo
tpF
a
100
a
100
ns
Chip Deselect to Output Float
tOF
0
100
a
100
ns
CS = VIL
PD/PGM = VI
Address to Output Hold
tOH
0
ns
PD/PGM = CS = VIL
a
• A.C. Tilt Condition.
Output Load ITTL + l00pF
Input Rise and Fall Times (10%-90%1 ~ 20ns
Input Pulse Levels VIL = 0 8V. V IH = 22V
Timing Measurement Referenoe Level Inputs IV & 2V. Outputs a BV & 2V
- 180-
~ote
4)
,::APACITANCE
ra=25·C.f=lMHz
T
PARAMETER
Input Capacitance
i
Output Capacitance
I
1
I
SYMBOL
LIMITS
MIN
TYP
T
I
i
C'N
COUT
1
T
4
8
T
MAX
CONDITIONS
UNIT
T
6
pF
Y,N =OV
I
12
pF
Vout=OV
TIMING WAVEFORMS IREAD)
A. Read Mode
PD/PGM - VIL
8. SUndby Mode
Addr... - - - - - - - - -....
".------------AddNMN +m
PDIPGM
No.: 1. Vee must be
IPpll~ Ilmuluneoully or !Mfo,. Vpp and cut off ,Imullan_ully or aft8r VpP. _
r.
2. Tho Vpp _mln.II, ..nnl..... to connoc. _
Vee ...m'n.,d,_,.
VCC~
Vpp ~.
d.,'no non-p'..'ommlno.
3. Typlca' valu ... at T. - 2SoC and nominal supply volta....
4. This parameter 'I periodically ..mpl.t and I, not 100" ten8d.
Ii, The tACC2 iI. output ~ delay time (I •• acce. time) from IIdd,... or PDIPGM whlchner chengH ,. . .
T. = 2S·C ± S·C. Vee = SV ± S%. Vpp = 2SV ± 1V (Note 1. 2. 3)
'.
,
...-
PARAMETER
f--.
I nput Current
Vpp Supply Current
.
'
..
..
'~'
SYMB~)L
MIN.
TYP.
ILl
Ipp,
MAX.
.±10
5
UNIT
CONDITIONS
Y,N = 5.25VIO.45V
JJA
mA
PDIPGM - VIL
Vpp Supply Current
During Programming Pulse
Vee Supply Current
Ipp,
30
mA
PD/PGM =V,H
lee
100
mA
IOUT=OmA
I nput Low Level
VIL
-01
08
V
Input High Level
VIH
20
Vcc+l
V
- 181-
I
:: '
"
I,!
"
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNIT
Address Setup Time
tAS
2
p.s
CS"Setup Time
tess
Data Setup Time
tos
2
2
p.s
p.s
Address Hold Time
tAH
2
p.s
CSHoid Time
tesH
2
p.s
tOH
2
Chip Deselect to Output FloatDelay
tOF
0
Chip Select to Output Delay
Program Pulse Width
teo
tpw
Program Pulse Rise Time
tPRT
45
5
Program Pulse Fall Time
tPFT
5
Data Hold Time
-----
CONDITIONS
p.s
ns
PD/PGM = V,L
120
ns
PD/PGM = VIL
55
ms
120
50
--
ns
ns
• A.C. Tut Condition.
Input Rise and Fall Times (10% - 90%) . ~ 20ns
InputPulseLevels V'L=08V.VIH=22V
Timing Measurement Reference Level Input 1V & 2V. OutputO.8V & 2V
Vpp - 2!V±1V, Vee" 5V±S%
Add .....
Dot.
--~
PD/PGM
tpw
(45"""'55",,)
Note:
1. Vee mutt be .ppll«I slmult.....ou.ly pr b.t'ore Vpp .nd cut off .Imulteneously or .fter VPP.
~
vcc..J ,-----,
Vpp--l
L
L--.
2. Sometime. removing the device from socket end setting the device In socket under the condition Ypp - 26V ± 1V mey dntroy Its
device, 110 It should be noted dUring Pl"OIIrernmlng.
3. Vpp .upply volt... I. permlttllcl up to 28V programming. so the voltege ov.r 28V mould not be eppll«l 1:0 Vpp.
P.rtlculerly when switching pul.. vott... I•• ppll«l 1:0 Vpp, .Iso the over-shoot volt. of Its pul•••hould not be exceeded 2&-volt.
- 182-
EIW!URECIWJACT~
The TMM323DI's memory cell data can be erased
by applYing light With wavelengths shorter than 4000
A_ (lA = 10-8 cm)
Sunlight and the fluorescent lamps may Include
3000 - 4000 A wavelength components
Therefore when used under such lighting for
extended periods of time, an opaque seal (Toshiba
EPROM Protecting Seal AC 901 etc) Will be required
to protect the TMM323DI. Generally, ultraviolet light
With a wavelength of 2537 A IS recommended for
TMM323DI-eraslng, and In thiS case the Integrated
dose (ultraviolet light intensity [w/cm' I x time [sec I )
should be over 15 [w sec/cm' I
When Toshiba steriliZing lamp GL-15 IS used and
the deVice IS exposed at a distance of l-cm from the
lamp surface, erasure should be completed in about
60 minutes
And uSing a lamp whose ultraviolet light intensity
IS a 12000 [llw/cm'l will reduce the exposure time
to about 20 minutes_
(In thiS case the Integrated dose should be 12000
[llw/cm'l x (20 x 60) [secl '" 15 [w sec/cm'I.)
.~_JNFO""~noN.
TMM323DI-operation-modes are classified Into six
types, as shown In the follOWing table Each mode
can be selected by TTL level signals only The Vcc
and Vpp power supplies required are only 5-volt for
read operation, and the Vpp power supply required IS
25-volt dUring program operation only.
~
MODE
Read
Read Operation
(Ta = --40 - 8S0C)
Deselect
Power Down
Program
Program Operation
(Ta =2S± SoC)
PD/PGM
CS
VPp
(18)
(20)
(21)
Vcc
(24)
VIL
VIL
.
SV
SV
o
VIH
SV
SV
High-Z
SV
SV
High-Z
VIH
2SV
SV
Din
.
VIH
...fln.... VIH
VIL
Outputs
(9-11,13-17)
out
Program Verify
VIL
VIL
2SV
SV
Oout
Program Inhibit
VIL
VIH
2SV
SV
Hlgh-Z
* VIL or VIH
Read Mode
D_lectMode
Assuming that PD/PGM = Vil and CS = Vll, the
output data IS available within tACC, (MAX.) after
stabilizing of the address.
And assuming that PD/PGM = VIH or CS = VIH, the
outputs will become high impedance in state
When all addresses are in the fixed state and CS =
Vll, the output data is available Within tACC,
(MAX.) after the PD/PGM Input is changes to VIL
from the VIH level. (Outputs change to data available
state from a high impedance state.)
When all addresses are in the fixed state and PDI
PGM = VIL, the output data is available within tco
(MAX) after the CS input is changed to VIL from
the VIH level (Outputs change to data available state
from a high impedance state.)
Assuming that CS = VI H, the outputs will be in a
high impedance state So two or more TMM323Dls
may be tied together on the same data bus. And the
CS Input of the selected chip must be at the VI L
level, and that of the other chip must be at the VIH
level.
- 183-
I
Power Down Mode
Assuming that PD/PGM = V I H, the power dIssipation will be reduced to one-fourth of normal active
power_
Then all outputs will become high Impedance in state
Independent of the CS Input level.
Program Mode
Initially when received by customers all bits of the
TMM323DI are In the "'" state which is the erased
state_
Therefore programming IS carned out by electrically writing In the "0" state at the desired bit locations.
Programming can be completed by applYing the
TTL level pulse signal with a pulse width of from 45
to 55 ms to PD/pGM Input under the condition
where Vpp = 25V and CS = VIH
Programming the TMM323DI is permitted in any
sequence and also at any particular bit location
But the PD/PGM pulse width applied at one bit
location should be over 45ms up to 55ms, and
rewriting Into the written location is not permitted
When programming IS carned out by applying a
DC voltage (VIH level) Instead of a pulse to the PDI
PGM Input, erroneous Writing may occur sometimes,
32. MAX
so a pulse whose recommended width IS 50ms shou
be used In programm Ing.
Programming the same data to two or more TM
323Dls simultaneously can be accomplished by co
nectlng the respective pinS together
Program Verify Mode
In this mode the Vpp power supply IS 25V
But assuming that PD/PGM = VI Land CS = Vil
It can be possible to read written data
For normal read operation, the Vpp power suppl
voltage required IS 5V.
Program Inhibit Mode
Assuming that PD/PGM = VI Land CS = VI H unda
Vpp = 25V, It IS able to inhibit the programming.
According to the above, programming Into two c
more TMM323Dls mounted on a board will be POi
sible
Programming Into a desired chip tied on a commo
bus Ii ne Independently IS possible by connecting a
respective Inputs except PD/PGM together and applv
ing a pulse to the PD/PGM Input of a deSired chip an.
applying DC voltage at the VIL level to the PD/PG~
Inputs of the other chip.
No. ,
1. Each lead pitch's 264 mm. All lead, art! located
wlth,n 026 mm of thair true longitudinal position
71:1:02
2
With r.'Pact to No 1 and No. 24 leads
ThiS value 'I ma •• ured at the and of lead,
3
All dlmenllons ar. In millimeter•.
Note 2
Note 1
Nota·
Toshiba doH not anum. any responsibility for
u.
of any circuitry described, no circuit patent hClln... a,.. Implilld. and Toll1ltNi ,...rv..
the tlgh't, 8t any tlma without nottce, to change Mid circuitry
©Nov. 1981 Tolluba Corporation
- 184-
TMM2732D
TMM2732D-2
)96 WORD x 8 BIT UV ERASABLE AND ELECTRICALLY
ROGRAMMABLE ROM
-CHANNEL SILICON STACKED GATE MOS
DESCfttPiION ,
The TMM2732D IS a 4096 word x 8 bit ultraviolet
,ght erasable and electrically programmable read only
nemory,
For read operation, the TMM2732D's
naxlmum access time IS 350ns/250ns, and the
[MM2732D operates from a single 5-volt power sup)Iy and has a low power standby mode which reduces
he power dissipation without increasing access time.
[he standby mode IS achieved by applying a TTLllgh level signal to the CE Input. The maximum
Ictlve current IS 150mA and the maXlmllm standby
:urrent IS 25mAl35mA
For program operation, the programming IS achieved by applYing a 50ms active TTL low program pulse
to the CE Input, ancldt is pOSSible to program sequentlally, individually, or at random.
The TMM2732D IS fabr Icated With the N-channel
Silicon double layer gate MOS technology and IS
packaged In a standard 24 pin dual In line cerdlp
package,
, Single 5-volt power supply
, Fast access time
350ns
TMM2732D
TMM2732D-2
250n$
, Power diSSipation
150mA (Max.) (Active)
25mA (Max.) (Standby TMM2732D)
35mA (Max.) (Standby TMM2732D-2)
• Low power standby mode
CE
•
•
•
•
•
•
•
PJII~crlON
Output buffer control
OE
Fully Static operation
Programs with one 50ms pulse
Single location programming
Total programming time about 200 seconds
Three state outputs
Inputs and Outputs
Directly TTL compatible
• Pin compatible with 12732 and ROM-TMMi332P
~Ot~
Output
BuffWII
Ao
'1
Column I/O
"
As
Ao -- All
Address Inputs
0.-0,
Data Outputs (Inputs)
CE
OENpp
Vcc
GND
A.
AS
A,
A,
A,
Chip Enable Input
Output Enable I nput/Program Power
A,
Power (+5V)
A,.
Ground
AU
- 185-
AlTay
4,096
II:
•
I
SYMBOL
ITEM
Vee
OENpp
RATING
UNIT
Vee Supply Voltage
-0.3-7.0
V
Program Supply Voltage
-0.3-26.5
V
V
VIN
Input Voltage
-03-7.0
VOUT
Output Voltage
-03-70
V
Po
Power Dissipation
TSOLOER
Soldering Temperature Time
1.6
260 . 10
W
°C . sec
TSTRG
TOPR
Storage Temperature
-65-125
Operating Temperature
·C
·C
0-70
READ OPERATION
SYMBOL
TYP.
MAX.
Vee
Vee Supply Voltage
PARAMETER
475
5.0
5.25
V
VIH
Input High Voltage
2.0
Input Low Voltage
-0.3
Vee + 1.0
0.8
V
VIL
-
MIN.
UNIT
V
(Ta = 0 -70·C. Vee = 5V f 5%. unless otherwise noted)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
CE = VIL
-
Output Low Voltage
IOL -2.1mA
-
Output High Vo ltage
IOH - --4OOjJ.A
2.4
-
IlL
Input Load Current
VIN = 0 - 5.25V
ILO
Output Leakage Current
VOUT = 0.4 - 525V
icc.
Vee Current (Standby)
CE = VIH
lee.
Vee Current (Active)
VOL
VOH
I TMM2732D
I TMM2732D-2
- 186-
MAX.
UNIT
±10
jJ.A
flO
25
35
jJ.A
rnA
150
rnA
0.4
V
-
V
I
(Ta = 0 -70·C, Vee = 5V ± 5%, unless otherwise noted)
SYMBOL
PARAMETER
CONDITIONS
TMM2732D-2
TMM2732D
MIN.
MAX.
UNIT
MIN.
MAX.
250
ns
250
ns
100
ns
350
OE to Output Valid
OE = V,l
CE - V,l
-
120
-
tOF1
CE to Output In Hlgh-Z
OE = V,l , CE = V,H
0
100
0
90
ns
tOF2
OE to Output In Hlgh·Z
0
100
0
90
ns
tOH
Output Data Hold Time
CE = V'l, OE - V,H
CE - OE = V,l
0
-
0
-
ns
lAcc
Address Access Time
CE = OE = Vil
tCE
CE to Output Valid
toE
350
Output Load
!TTL Gate and CL (l00pF)
Input Pulse Rise and Fall Times
:::;; 20 ns
I nput Pulse Levels
O.S - 2.2V
Timing Measurement Reference Level
Inputs
1V and 2V
Outputs a SV and 2V
_..
SYMBOL
• (Ta = 25·C, f = lMHz)
PARAMETER
CONDITIONS
C,NI
C,N2
Input Capacitance Except OENpp
Input Capacitance (ITENpp)
Y,N =OV
Y,N =OV
COUT
Output Capacitance
VOUT -OV
MIN
TYP.
MAX.
UNIT
-
-
6
pF
20
pF
12
pF
-
* This parameger IS penodlcally sampled and IS not 100% tested
I
°0 . . . °7
- 187-
."
te
CO
"
T.-26·C
300
Vee
T.·25"C
300
\
\
s""
"
""-
'50
r-...
r--
,'"
•
•
Vee (V)
Vee (V)
,
toE n Vee
200
..
T."'25"C
,
~ '00
g
tACe teE toE
'II
VCC- SOy
,
\
CL -l00pF
~
0
..
Ta
~
.~
'3
•
•
Vee (VI
•
,
,
7
7
ICC2 .... Vee
60
..
Vcc-50V
T... 25"'C
, '1-+-t--+-j--1
,......
r- - -
20
~, , r--r- ---j---t-t-+-j---j
1
,...... / '
llOl-t--t--:±--r4r-:-::- - - -
200
400
300
500
CL (pFI
ICCl
VI
Vee
,
, -t--
10 ' " --
---
>- C5
Vee (V)
,
::::: p
B
---
--
--~"-.-
!,o-r-- --"-f--,. - ,---
t.r-f--
--r--...
5.
ICCl vs T.
Vee-5OV
201-+- -j-+-+--j
CE"-20V
::::--
•
r,,
,.
- --
~
7
55
1--+-+--+ --r-
TI=2~C
--
5
Vee (VI
11r--r-,-.-r"CO""",,;.:....;T,,'--_---,
B"-20V
,r-- f--
o
..
'0t---r~--r-t---r~--r-i
,/
'00
e-- ___ ~ ~ ____ _
i
.,-
60
90
- 188-
VCC=5OV
.
"
PROGRAM OPERATION
;O».:.~~~T_~"'·
SYMBOL
PARAMETER
TYP.
MIN
VIH
Input High Voltage
20
VIL
I nput low Voltage
-03
Vee
Vpp
Vee Supply Voltage
475
Program Input Voltage
24
UNIT
MAX.
-
Vee
+ 1.0
V
08
V
50
5.25
V
25
26
V
(Ta = 25± 5°C. Vee = 5V ± 5%, Vpp = 25V ±IV)
MIN
TYP.
MAX.
UNIT
III
Input Current
VIN =0-525V
-
±10
p.A
VOH
Output High Voltage
IOH =-400p.A
24
-
VOL
Output Low Voltage
IOL =2.1mA
-
ICC
Ipp
Vee Supply Current
SYMBOL
CONOITIONS
PARAMETER
Vpp Supply Current
-
-
!
CE = VIL, OE = Vpp
-
-
-
V
0.4
V
150
mA
30
mA
(Ta=25±5°C. Vee = 5V±5%, Vpp = 25V± IV)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
tAS
Address Set Up Time
2
-
p.s
tOES
OE Set Up Time
2
tos
Oata Set Up Time
2
-
(lltAH
Address Hold Time
0
-
tOEH
OE Hold Time
2
tOH
Oata Hold Time
2
tOF
CE to Output
teE
tpw
CE to Output Valid
-
-
Program Pulse Width
45
tpRT
Vpp Pulse Rise Time
50
tVR
Vpp Recovery Time
2
Note (1)
In
Hlgh·Z
tAH (Program Operation 1) = Op.s min.
tAH (Program Operation 2) = 2p.s min.
Refer to Tlmlng,Waveforms
• Input Pulse Rise and Fall Times
• I nput Pulse Levels
• Tlmlng'Measurement Reference Level
;;; 20ns
Inputs
Outputs
O.8V- 2.2V
lV&2V
O.8V & 2.0V
- 189-
-
p.s
p.s
p.s
-
p.s
100
ns
p.s
350
ns
50
55
ms
-
-
p.s
ns
.1.fl_II..
(PROGRAM OPERATION)
Program Operation 1.
PROGRAM MODE
PROGRAM
VERIFY MODE
OE/Vpp
DATA OUT
(ADDRESS N)
00""07
Program Operation 2. (OENpp· Vpp)
ADDRESS N
DATA IN (ADDRESS N)
Nota
1.
Vee mUlt ba applied slmultaneou.ly or before Vpp and cut off simultaneously or after Vpp
2.
Sometimes removing the device from lockat and .etting the devIce In locket under the condition Vpp "" 25V ± 1 V may cause parmanent
damage to the device,
The Vpp supply voltage II permitted up to 26V for program opftratlon. 10 the voltage ovar 26V should not ba applied to the Vpp Input.
When the switching pul .. voltage 'I applied to the Vpp tnpU[, the Qva,-shoot voltage of ItI pulse should bot be exceeded 26V
3,
The TMM2732D's erasure IS achieved by applYing
shortwave ultraviolet light which has a wavelength of
2537 A (Angstroms) to the chip through the trans·
parent Window. Then Integrated does (ultraViolet
light Intensity [w/cm'] x exposure time [sec.] ) for
erasure should be a minimum of 15 [w. sec/cm'].
When the Toshiba steriliZing lamp GL-15 IS used
and the device IS exposed at a distance of lcm from
the lamp surface, the erasure Will be achieved Within
60 minutes.
And uSing commerCial lamps whose ultraviolet
light Intenslsty is a 12000 [!,w/cm2] Will reduce the
exposure time to about 20 minutes (I n thiS case, the
Integrated does IS 12000 [!'w/cm'] x (20 x 60)
[sec] '" 15 [w. sec/cm] )
The TMM2732D's erasure begins to occur when
exposed to light With wavelength shorter than 4000A
The sunlight and the fluorescent lamps will mclude
3000 - 4000A wavelength components. Therefore
when used under such IIghtmg for extended periods
of time, the opaque seals· Toshiba EPROM Protect
Seal AC901 . are available
190 -
•
The TMM2732D's SIX operation modes are listed In
the following table. Mode selection can be achieved
by applYing TTL level signal to all inputs except for
OE/Vpp In the read operation mode, a single 5·volt
~.)
MODE
READ
OPERATION
ITa = 0 _70°C)
PROGRAM
OPERATION
ITa = 25 ± 5°C)
READ
OUTPUT DESE LECT
STANDBY
PROGRAM
PROGRAM VERIFY
PROGRAM INHIBIT
power supply is reqUi red and the levels required for
all inputs are TTL.
In the program operation mode the OE/Vpp IS
pu Ised from a TT L level to 25V.
CE (18)
GENpp (20)
Vcc 124)
.
VIL
VIH
+5V
+5V
+5V
+5V
+5V
+5V
VIL
.
VIH
VIL
VIL
VIH
Vpp
VIL
Vpp
00
-
0, (9·11,13·17)
DATA OUTPUT
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA INPUT
DATA OUTPUT
HIGH IMPEDANCE
READ MODE
The TMM2732D has two control functions. Chip
Enable (CE) controls the operation power and should
be used for device selection. Output Enable (OE)
controls the output buffers, Independent of device
selection
Assuming that CE = OE = VIL, the output data IS
valid at the outputs after address access time (350ns/
250ns max,) from stabilizing of the addresses.
The CE to output valid (tCE) Isequal to the address
access time
Assuming that CE = VIL and address are stable, the
output data IS valid at the outputs after toE (120ns/
lOOns max) from the failing edge of OE,
OUTPUT DESELECT MODE
Assuming that OE = VIH, the outputs Will be in a
high Impedance state. So two or more TMM2732D's
can be connected together on a common bus line.
When CE IS decoded for device selection, all deselected devices are In low power standby mode.
STANDBY MODE
The TMM2732D has a low power standby mode
controlled by CE signal. By applYing a TTL high
level signal to the CE Input, the TMM2732D IS placed
In the standby mode which reduce the operating cur-
rent from l50mA to 25mA/35mA, and then the outputs are In a high Impedance state, independent of
the OE input.
- 191-
.~
,
"
", :'1',
~
.,.
.::,
PROGRAM MOM
Initially, when received by customers, all bits of
the TMM2732D are in the '1' state which IS erased
state. Therefore the program operation is to introduce 'Os' data Into the desired bit locations by electrically programming. The TMM2732D IS set up in the
program operation mode when applied the program
input voltage (+25V) to the OE/Vpp input under
CE = VIH.
Then programming is achieved by applying a 50ms
active low TTL program pulse to the CE input after
the addresses and data are stable. ThiS program pulse
should be a single pulse with 50ms pulse width per
address word, and its maximum value is 55mS. The I '
levels required for the address and data inputs are
TTL. The TMM2732D can be programmed at any
time individually, sequentially, or at random. The
TMM2732D must not be programmed with a DC
signal applied to the CE input
PROGRAM VERIFY MODE
The verify mode is to check that the desired data is
correctly programmed on the programmed bits. The
verify is accomplished with Ol:/Vpp and CE at VIL.
Data should be verified after teE (350ns max.) from
the falling edge of cr.
PROGRAM INHIBIT MODE
Under the condition that the program input voltage (+25V) is applied to the Ot:/Vpp Input, a TTL
high level CE input inhibits the TMM2732D from
being programmed.
Programming of two or more TMM2732D's in
paralled with different data is easily accomplished.
That is, all inputs except for cr are commonly connected, and the program pulse is applied to the CE
Input of the desired device only and the TTL high
level signal is appliedjl:o the other devices.
OUTLINE DRAW1NGS
I
327~::
2423 22 21 20"'817 1815 14
I
~I
-+----+]
......
1 2 3 4 5 8 7 8 It 101112
Nate 1
2.
3.
each lead pitch Is 2 54mm. Alii_ads are located within 0 2t5mm of their true longitudinal pOiltlon with r"pect to No, 1 and No. 24 IIhdL
This value Is m..sured at the and of leads
All dimension, ara in mllhmeters
©Nov. 1981 Toshiba CorpOration
- 192-
TOSItBA MOS MEMORY PRODUCTS
4096 WORD x 8 BIT UV ERASABLE AND ELECTRICALLY
PROGRAMMABLE ROM
N CHANNEL SILICON STACKED GATE MOS
TMM2732DI
TMM2732DI-2
DIiiSCRIPTION
The TMM2732DI IS a 4096 word x 8 bit ultraviolet
light erasable and electrically programmable read only
memory
For read operation, the TMM2732DI's
maximum access time IS 350ns /250ns and the
TMM2732DI operates from a single 5-volt power
supply and has a low power standby mode which
reduces the power diSSipation without increasing access time The standby mode IS achieved by applYing
a TTL-high level signal to the CE Input The maxImum active current IS 150 mA and the maximum
standby current is 30 mA/40 mAo
FEATURES
• Wide operating temperature range
Ta = -40 - 85°C
• Fast access time
TMM2732DI
350 ns
TMM2732DI-2, 250 ns
• Power dissipation
150 mA Max. lactive current)
30 mA Max Istandby TMM2732DI)
40 mA Max Istandby TMM2732DI-2)
PIN CONNECTION
A,
A,
A,
A,
A,
A,
A,
,
,
,
,
,
,
For program operation, the programming IS achieved by applYing a 50 ms active TTL low program pulse
to the CE Input, and It IS possible to program sequentially, Individually, or at random
The TMM2732D I IS fabricated with the N-channel
silicon double layer gate MaS technology and IS
packaged In a standard 24 pin dual In line cerdlp
package
•
•
•
•
•
•
•
•
•
BLOCK DIAGRAM
Vee
A.
A.
OElVpp
Aw
""
A,
,
0,
9
0,
"
0,
0,
0,
0,
0,
0,
PIN NAMES
Ao -All
~O7
CIO
OE I Vpp
Address Inputs
Data Outputs (Inputs)
Chip Enable Input
Output Enable I nput/Program Power
Vcc
Power (+5V)
GND
Ground
Low power standby mode CE
Output buffer control OE
Fully static operation
Programs with one 50 ms pulse
Single location programming
Total programming time about 200 second
Three state outputs
Inputs and outputs TTL compatible
Pin compatible with 12732 and ROM TMM2332P
- 193-
•
MODE SELECTION
~
MODE
Read
CE
(181
OE / Vpp
(201
vee
(241
.
V,L
+5V
DOUT
V,H
+5V
High Impedance
+5V
High Impedance
V,L
Output Deselect
Outputs
(9 -11, 13- 171
Standby
V,H
.
Program
V,L
Vpp
+5V
D,N
Program Verify
V,L
V,L
+5V
DOUT
Program Inhibit
V ,H
Vpp
+5V
High Impedance
I
MAXIMUM RATINGS
I
I
ITEM
SYMBOL
Vee Supply Voltage
Vee
~IVpp
Program Supply Voltage
_ _ VIN
Input Voltage
~UT
1
-~
Output Voltage
Power DISSipation
PD
RATING
T SOLDER
Soldering Temperature
T STRG
Storage Temperature
TOPR
Operating Temperature
Time
UNIT
-03-70
V
-03 - 26 5
V
-03
70
V
1
I
-65-125
I
W
16
260 10
I
I
I
V
-03 -7 0
I
=1
°c
sec
---j
~
°c
°c
-40- 85
READ OPERATION
D.C. RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
TYP
MAX
475
50
525
Input High Voltage
22
-03
-
Vee + 1 0
Input Low Voltage
Vee
V,H
Vee Supply Voltage
V,L
MIN
UNI1:_
V
V
08
V
D.C. and OPERATING CHARACTERISTICS
(Ta: -40 ...... 85Q C Vee = 5V ± 5% unless otherwise noted)
----~L
IlL
l---'LO
PARAMETER
I nput Load Current
Output Leakage Current
ICC 1
Vee Current (Standby)
Vee Current (Active)
CE
Output Low Voltage
IOL - 2.1mA
VOL
VO H
---.::~
Output
___
High Voltage
MIN
._---
= 0 - 5.25V
VOUT = 04- 5.25V
I TMM2732DI
1-----CE = V ,H
r TMM2732DI2
V ,N
lee2
L-~
~-
CONDITIONS
= VIL
IOH - -400 jJ.A
- 194-
I
-
I
24
TYP
-
MA2<_ l-..lJ.~
±10
jJ.A
+10
30
t - 40
---=-150
-
jJ.A
mA
mA
04
V
-
V
•
A.C. CHARACTER Isncs
Output Load
1TTL Gate and CL (100 pFJ
Input Pulse Rise and Fall Times
:;:;: 20 ns
Input Pulse Levels
08- 22V
Timing Measurement Reference Level
Inputs
1V and 2V
Outputs a 8V and 2V
fm
r~~~----L :~~;~:~~~!t;~~;~~=. t-~~:~~~o0'+--.- '. ~~~
CAPACITANCE * ITa: 25"C, f= 1MH,z)
eAe~me
, "Me"
~
[
co'm~M"
_J
Output Capacitance
* ThiS parameter
IS
periodically sampled and
IS
VOUT
~
ovT=-_.
not 100% tested
TIMING WAVEFORMS (READl
CE
DE
- 195-
M"
±
UNIT
2;- _+-~~ -
~--=-_~_~~_ 1_
pF
[
PROGRAM OPERATION
D.C. RE~D·orMAT.Jl\lO CONQIT~N8
SYMBOL
PARAMETER
VIH
Input High Voltage
VIL
Input Low Voltage
Vee
Vpp
Vee Supply Voltage
Program Input Voltage
MIN
TYP
MAX
UNIT
22
--{)3
-
Vee + 10
08
V
475
5.0
525
V
24
25
26
V
V
D.c. Pf:'OGRAMMJNG CHARACTERIStICS
(Ta = 25 ± 5°C. Vee = 5V ± 5%, Vpp = 25V ± 1V)
SYMBOL
MIN
TYP
MAX
UNIT
III
V OH
Input Current
VIN =0-525V
CONDITIONS
-
±10
p,A
Output High Voltage
10H = -400p,A
24
-
-
V
VOL
Output Low Voltage
10L =21 mA
lee
Ipp
Vee Supply Current
PARAMETER
Vpp Supply Current
CE = V IL OE = Vpp
-
-
04
V
-
150
mA
-
-
30
mA
~.PQOG~~B"
(Ta = 25 ± 5°C, Vee = 5V ± 5%, Vpp = 25 ± 1V)
SYMBOL
PARAMETER
MIN
tAS
Address Set Up Time
2
tOES
OE Set Up Time
2
Data Set Up Time
2
tos
(1) tAH
TYP.
MAX
UNIT
-
-
p,s
-
p,s
50
p,s
Address Hold Time
0
tOEH
OE Hold Time
2
tOH
Data Hold Time
2
tOF
CE to Output m Hlgh-Z
teE
tpw
CE to Output Valid
-
Program Pulse Width
45
tPRT
Vpp Pulse RISe Time
50
-
-
ns
tVR
Vpp Recovery TIme
2
-
-
p,s
Note (1) tAH (ProgramOperatlOn1)=0p,smm
tAH (Program Operation 2) = 2 p,s min
Refer to Timing Waveforms
,Mi,tfa.-IJ. . .·
Input Pulse Rise and Fall Times
;:; 20 ns
Input Pulse Levels
08- 22V
Timing Measurement Reference Level - Inputs
1V & 2V
Outputs O.8V & 2 OV
- 196-
p,s
-
p,s
100
ns
p,s
350
ns
55
ms
·,': .
.,',
•
Program Operation 1
PROGRAM
VERIFY MODE
PROGRAM MODE
tCE
Program Operation 2 (OENpp
= Vpp)
ADDRESS N
tpw
00- 0 ,
NOTE
DATA IN (ADDRESS Nl
1. Vee must be applied simultaneously or before Vpp and cut off simultaneously or after Vpp.
2. Sometimes removing the devioe from socket and setting the devloe in socket under the condition
Vpp =25V :t 1V may cause permanent damage to the devioe.
3. The Vpp supply voltage is permitted up to 26V for program operation, so the voltage over 26V
should not be applied to the Vpp input. When the switching pulse voltage is applied to the Vpp
input, the over-shoot voltage of ItS pulse should not be exoeeded 26V.
ERASURE CHARACTERISTICS
The TMM2732DI's erasure is achieved by applying shortwave ultraviolet light which has a wavelength of 2537A
(Angstroms) to the chip through the transparent window Then integrated dose (ultraviolet light Intensity
[w/cm'] x exposure time [sec 1) for erasure should be a minimum of 15 [w sec/cm'].
When the Toshiba sterilizing lamp G L·15 IS used and the devloe IS exposed at a d,stanoe of 1 cm from the lamp
surface, the erasure will be achieved Within 60 minutes And uSing commercial lamps whose ultraViolet light
intenSity IS a 12000 [jlw/cm'] will reduoe the exposure time to about 20 minutes (In thiS case, the Integrated
dose IS 12000 [jlw/cm'] x (20 x 60) [sec] '" 15 [w sec/em'] )
The TMM2732DI's erasure beginS to occur when exposed to light With wavelength shorter than 4000A The
- 197-
sunlight and the fluorescent lamps Will Include 3000 - 4000A wavelength components Therefore when used
under such lighting for extended periods of time, the opaque seals - Toshiba EPROM Protect Seal AC901 are available
The TMM2732DI's SIX operation modes are listed In the follOWing table Mode selection can be achieved by
applYing TTL level signal to all Inputs except for OENpp In the read operation mode, a signal 5-volt power
supply I~ required and the levels required for all Inputs are TTL
In the program operation mode the OENpp IS pulsed from a TTL level to 25V
~
MODE
READ
OPERATION
READ
OUTPUT DESE LECT
STANDBY
PROGRAM
OPERATION
CE 1181
.
V,L
OENpp 1201
Vcc 1241
V ,L
+5V
+5V
+5V
+5V
+5V
+5V
.
V,H
V,H
PROGRAM
V,L
Vpp
PROGRAM VERIFY
V,L
PROGRAM INHIBIT
V,H
V,L
Vpp
O.
-0,
19-11,13-17)
DATA OUTPUT
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA INPUT
DATA OUTPUT
HIGH IMPEDANCE
The TMM2732DI has two control functions Chip Enable (CE) controls the operation power and should be
used for deVice selection. Output Enable (OE) controls the output buffers, Independent of deVice selection
Assuming that CE = OE = VIL, the output data IS valid at the outputs within address access time (350 ns max.)
after stabilIZing of the addresses.
The CE to output valid (tCE) IS equal to the address access time
Assuming that CE = VIL and addresses are stable, the output data IS valid at the outputs within tOE (120 ns
max) after the falling edge of OE.
Assuming that OE = VIH or CE = VIH, the outputs Will be In a high Impedance state So two or more
TMM2732Dlscan be connected together on a common bus line When CE IS decoded for deVice selection, all
deselected deVices are In low power standby mode
- 198-
•
STANOIY MODI
The TMM2732D I has a low power standby mode controlled by CE Signal By applYing a TTL high level Signal
to the CE Input, the TMM2732D I IS placed In the standby mode which reduce the operating curr~nt from 150 mA
to 30mA, and then the outputs are In a high Impedance state, Independent of the OE Input
PROGRAM MODE
Initially, when received by customers, all bits of the TMM2732DI are In the "1" state which IS erased state
Therefore the program operation IS to Introduce "as" data Into the deSired bit locations by electncally programming The TMM2732D I IS set up In the program operation mode when applied the program Input voltage (+25V)
to the OE!Vpp Input under CE = VIH
Then programming IS achieved by applYing a 50 ms active low TTL program pulse to the CE Input after the
addresses and data are stable ThiS program pulse should be a Single pulse With 50 ms pulse width per address
word, and ItS maximum value IS 55 ms The levels reqUired for the address and data Inputs are TTL The
TMM2732D I can be programmed at any time indiVidually, sequentially, or at random The TMM2732D I must not
be programmed With a DC Signal applied to the CE Input
PROGRAM VERIFY MODE
The venfy mode IS to check that the deSired data IS correctly programmed on the programmed bits The venfy
IS accomplished With OE!Vpp and CE at V,L Data should be venf,ed Within tCE (350 ns max) after the failing
edge of CE
PROGRAM INHIBIT MODE
Under the condition that the program Input voltage (+25V) IS applied to the OE!Vpp Input, a TTL high level
CE Input inhibits the TMM2732D I from being programmed
Programming of two or more TMM2732DI s In parallel With different data IS easily accomplished That IS, all
Inputs except for CE are commonly connected, and the program pulse IS applied to the CE Input of the deSired
deVice only and the TTL high level Signal IS applied to the other deVices
- 199-
I
32.41 MAX.
I,'
t
7 .,% •.•
I
I
]
A 0.64
"..
«
l!
1 Ei.24±0.3
"!
0215+0 •16
-0.10
"«"
l!
O.46~.~:
N
16.2-17.6
Note 2
Note 1
Note: 1. Eech lad pitch I. 2.M mm All leMls .re locatacl within 0.26 mm of thel, true longltudlnel position With 'MPect to No.1
.ndNo.24I....
2. Thl. velu. Is m.sured n the end of I..ds.
3. All dl~MloM ere In mllllmftW••
Note:
Tolhlbe; do. not .....me ItfIY '.POnsibllity for u.. of eny circuitry d...:rlbed. no circuit
right. et eny time without notice, to
Id drcultt.y.
ct.,.. ..
@Oct.., 188t T.,Ib11 Corporetlon
- 200-
~
lie..,... .,.Implled. end Toehlbll NMfYel the
TMM2764D
TMM2764D-2
8,192 WORD x 8 BIT UV ERASABLE AND ELECTRICALLY
PROGRAMMABLE READ ONLY MEMORY
N~HANNEL
SILICON STACKED GATE MOS
2
The TMM2764D is a 8192 word x 8 bit ultraviolet
light erasable and electrically programmable read only
memory. For read operation, the TMM2764D's access
time is 200 ns, and the TMM2764D operates from a
single 5·volt power supply and has low power stand·
by mode which reduces the power dissipation without increasing access time. The standby mode is
achieved by applying a TTL-high level signal to the
The maximum active current is 120mA
power supply
•
• Fast access time . TMM2764D
TMM2764D-2
250 ns
200 ns
• Power dissipation
120 mA (active current)
Max.
35 mA (standby current) Max.
• Low power standby mode : IT
(TOP VI EW)
Vpp
A'2
A7
As
As
A9
A"
OE
A,o
cr
GND
Output buffer control
. OE
Fully static operation
Programs with one 50 ms pulse
Single location programming
Three state outputs
Inputs and outputs TTL compatible
Pin compatible with 12764 and ROM TMM2364P
Lower 24 PinS compatible with 32K
bit EPROM TMM27320
(TOP VIEW)
A.
A3
A2
A,
Ao
17
16
15
•
•
•
•
•
•
•
TMM2732D
~
PGM
N.C.
As
A.
A3
A2
A,
AD
00
0,
°2
and the maximum standby current is 35mA.
For program operation, the programming is achieved by app)Ylng a 50ms active TTL low program pulse
to the PGM input<- and It is possible to program
sequentially indi~ldually., or at random.
The TMM2764D is fabricated with the N-channel
silicon double layer gate MOS technology and IS
packaged In a standard 28 pin dual in line cerdlp
package.
00
0,
O2
GND
Vee
As
A9
A"
01:/Vpp
A,o
CE
07
0.
Os
0.
03
Array
8192 x 8 bits
oqv;I:%~o,~;
lAo -A'2
O. - 0,
I
I
--"t-""-'--F"-I'I"022".'1+',,1',,-1~1:3JT'911 Powe,
Address Inputs_______---j
Outputs (I nputs)
l
~aOut
CV I
I
+--_+-----+_H---+
,
~
Program
P-,og-,om---
l,
I,
.
'H
,1,;-)
____ J __~
L
I
!
I
I
IActive I
I Standby I
i
~vData I;:;---·t-~
5V H~'-'I
i!
Impedance "
21V i~,5-v-1H;Qh -----: Active
!
II
<.0
lnhlblt
High
Impedance
5VI,IHI9h
5V
I mpedance
' Standby
I
i
r
I H
~- __ ~~~
I
~a~H'----L":--,-.":L--,-_-,-'"5V."..l'.':D"",,,<>'''0...
",,---J._---.J
Note
- 201-
*
HorL
SYMBOL
ITEM
RATING
+ __-O--=".6=--
f----,-"'-"c"'c_ _ _-+__-,"'-"c"'c_P-'o-"we-,-r'--S::.:u"-p-'-P:.:.ly_V'-'o:.:.lt:.:::ag"'ec- ________
I
UNIT
7.0
V
-t ___
--;:0-,6:--_2;:-2-;:.0_ _-+___--:-VV:---_ _--1
"'VPPIN
Program Supply Voltage
VOUT
Po
-06 - 7
O_u-'-tP_u--,t:-V_o:-ltag--"--e_ _ _ _ _ _ _ _ _--1___
Power DIssipation
1.5
TSOLDER
Soldering Temperature Time
f------c'-!"'-___+ __-:I:-:np"'u::.:t-'Vc:.o::"lt=age"=-_.~
°
-_0_.6~-~~-7~.-O::~~~~~-:~~~~~~~~V~~~~~~~~
W
260
10
--+----6"'5 ..... 125
=i~~~~--:_ ~e~:t~e;=~::~::re
---+----------
0--70 -.::
°C sec
°C
_r~~oc
--
READ OPERATION
D.C. RltOMMENDED QP.11'ta1UIG CDNPIT~
-~PARAMET~
SYMBOL
-
---TM~t
·TYP.
r---~I~ _ _ _ ~~ ~~~~;~:;;____~ __+___~ ______ =~I--_~~____
L.
Vpp
_
Vcc Power Supply Voltage
Vpp _Power Supply Vo~tage _
-+
I
4.75
__ 2:.0 _
(Ta
_
VCC
.,
MAX.
-_~~;
~-'---_---1
1:0'_+__
_5-;:--,:--+_ _ cV-;-_--1
+---:cc-5_.2
VCC + 0 6
=0 -70°C. Vce =5V ± 5% Unless otherwise noted)
- 202-
UNIT
V
••
Ta = a -70°C, VCC = 5V± 5%, Vpp = 2 OV - Vcc
SYMBOL
+ a 6V, Unless otherwise notedl
PARAMETER
CONDITIONS
--"TMM2764D.2
TMM2764D
UNIT
______-+__________.________-r~~~~---===_--~--~M~I~N--~~M,~A~X~..~-M~IN~._+~M~A~X~._+----_+
tAce
Address Access Time
tCE
CE to Output Valid
CE "" OE ;: VIL._~~_.=
VH.i___ __ ,___
~~____
250
os
250
ns
~:
ns
a
90
90
ns
ns
ns
___ I--_()____ 6O""'" ----.Cl.
90
ns
=.__ ...3()()"'.
..~ - V,L I'GM = V,H _ _ _ _ _
__.ctO"-E,-__+",OE,,E=to__
Occu..:..tput ValiCl _____c:E.:.'.IlL. PGM=-""f:l.__.___ +-.~'l[)
•
•
•
•
___~
.. ~
.o.......f-----6.'l...............Cl.....
tpGM
tOFt
tOF2
I'GMtoOutputVal,d
OE=CE=VIL
'~'----f-----=--~.2Cl..
crtoOutPutinHlgh'Z _ _ _~=VI",--I'GM~-",~ __ ._. ___
OE to Output In High·Z
CE = VIL,I'GM = V IH
a
60
tOF3
I"G1Vl to Output
tOH
Output Data Hold Time
In
at = cr = VIL
High·Z
IT - OE -- VIL, PGM - VIH
Output Load
Input Pulse Rise and Fall Times
Input Pulse Levels
Tlmmg Measurement Reference Level
.0__.
-----=-_----=-_ ._____.____
n~ __
1 TTL Gate and CL = 100pF
10ns Max.
0.8V to 22V
Inputs lV and 2V, Outputs 0.8V and 2.0V
* (Ta=25°C, f=lMHz)
PARAMETER
1------,=____+
CONDITIONS
__--'-'1nput Capacitance
Output Capacitance
VIN = OV:c-;-____+ ___
____~__ V~O~U~T_=_O_V____~ _______ L
* This parameter is periodically sampled and
IS
not 100% tested.
I
High Z
- 203-
PROGRAM OPERATION
MIN.
TYP.
VIH
Input High Voltage
PARAMETER
2.0
VIL
Input Low Voltage
-0.3
-
SYMBOL
Vee
_ . .Vpp
.
__. -
..
Vee Power Supply Voltage
4.75
Vpp Power Supply Voltage
.-~.------
--
5.0
21.0
20.5
- - - - _ ..
MAX.
Vee
UNIT
+ 1.0
V
0.8
V
5.25
V
21.5
V
(Ta - 25±5°C, Vee = 5V± 5%, Vpp - 21V ±0.5VI
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I nput Current
VIN-O-Vee
-
±10
Output High Voltage
IOH - -400/lA
2.4
-
/lA
V
VOL
Output Low Voltage
IOL = 2.1mA
Icc
IpPl
Vee Supply Current
-
Vpp Supply Current
Vpp = 21.5V
-
-
III
-----vqH.
PARAMETER
(Ta
SYMBOL
tAS
PARAMETER
0.4
V
120
mA
30
mA
25+5°C, Vee =5V+5%. Vpp =21V±05VI
CONDITIONS
MIN.
Address Setup Time
Typ
MAX
2
/lS
)--_t",A"-H,-_+~A=d,,,dc..rec..s.=.s_H-,o-,ldc..T,-I-,m-,e_ _ _ _ _t--_______+_-=2_--+ ___ ..___
teES
CE Setup Time
UNIT
/lS
/lS
2
~EH ___ t __~Ct~H_O~I_d_T_'m=e_____________)--______________+-___2~_+- _____~____~__~/l_S_~
t05
Data Setup Time
2
~~tO~H~--4-~D~a-ta~H~o-ld~T~,-m-e------------}--------·--·-·----· ~ ...-
~_t.:'p-,,-s_ _+-__J5GM..s"t_u_p_TI~ ___. _ _ _ ..
_ ... _ _ _ _ _ _ _ .__
tpH
tOES
J5GM Hold Time
DE Setup Time
tvs
tpw
Vpp Setup Tlme_. __. _ _ _ _ .~........;:..---.Program Pulse Width
PGM = CE = VIL._
tcp
Program Recovery Time
~RT
~FT -- -
--
:~:I
•
•
•
•
--2-
5
10 Oui~H,QhZ-----
Output Load
Input Pulse Rise and Fall Times
Input Pu Ise Levels
Timing Measurement Reference Level
_-'1
5
-- --
__
..l..
-----
. __...._. __.__ _
5 ---J---.!)() _)--_ ~
___ ~ __ ~ _ _ _ _ _0_
DE to Output Valid - - - -O-E
Ct
DE to Out£ljl Irl_HI9."- Z
---:2~===~========~==::...-~~--j:~--~/l~S~~~~
2
~-
Program Pulse Rise Time
Program Pulse Fall Time
--Ie~--- --CEWOuw;rtVaiid~---
~~--
-=..
lots
/ls
I
-=--
__
-----r-
--+
J=--_-- -
-= -- -- - =--1---:"-- -
~ VI-L
-
----- -
IT - VIL
-_-
~-
250
/lS
ms
J.LS
I
ns
--~
ns
O'
lO 11----;;---nSs
gO
.
-=_ . ~
1TTL Gate and CL (100 pF)
10ns Max
a B - 22V
Input 1V and 2V
Output O.BV and 2.0V
- 204-
-
/ls
---/l;-
gO
ns ---
PROGRAM OPERATION 1. (VP. = 21V±O.5V)
tos
tpFT
tvs
Vpp
PROGRAM OPERATION 2. (V••
= 21V ± O.5V)
I
High Z
tvs
vpp
Note. 1. Vee must be applied simultaneously or before Vpp and cut off simultaneously or aftar VPP.
2. Removing the device from socket and setting the device in socket with Vpp" 21V may cau •• parmanent damage to the device.
3. The Vpp supply voltage II permitted up to 22V for program operation, 10 the voltage over 22V should not be applied 10 the Vpp
terminal.
Whan the switching puis. voltage Is applied to the Vpp terminal, the over-shoot voltage of Its pulse should not be exceeded 22V.
- 205-
..~
The TMM2764D's erasure is achieved by applying
shortwave ultraviolet light which has a wavelength of
2537A (Angstroms) to the chip through the transparent window. Then integrated dose (Ultraviolet
light Intensity [w/cm'] x exposure time [sec.]) for
erasure should be a minimum of 15 [W sec/cm'].
When the Toshiba steriliZing lamp G L-15 IS used
and the device is exposed at a distance of 1 cm from
the lamp surface, the erasure will be achieved within
60 minutes. And using commercial lamps whose
ultraviolet light Intensity is a 12000 [Ilw/cm'] will
reduce the exposure time to about 20 minutes. (Ir
this case, the integrated does is 12000 [Ilw/cm']
x (20 x 60) [sec] '" 15 [w. sec/cm'] .)
The TMM27640's erasure beginS to occur whee
exposed to light with wavelength shorter than 400C
A. The sunlight and the fluorescent lamps will
Include 3000 - 4000 A wavelength components.
Therefore when used under such lighting for extend·
ed periods of time, the opaque seals - Toshiba
EPROM Protect Seal AC901 - are available.
The TMM2764D's SIX operation modes are listed In
the follOWing table Mode selection can be achieved
by applYing TTL level signal to all Inputs. In the read
operation mode, a Single 5V power supply IS required
and the levels required for all Inputs are TTL.
r--------
READ
OPERATION
(Ta = 0 -70°C)
PROGRAM
OPERATION
(Ta = 25±5°C)
Note
-------
---
-- - -
--
-
Read
Output Deselect
*
*
L
Standby
Program
Program
Inhibit
Program Venfy
----
PGM
(271
H
I
*
H
H
t-
--- ,-= ------CE
(20) __
L
*
H
---L
H
L
L
--- --0 0 """ 0 7
vcc
f.-111-13.15-19)
~~~~ __ -~§~
L
Data Out
5V
High Impedance
H
5V
OE
---
r--'----~
~.
vpp
. _*. - -
-----
*
*
H
L
21V
High Impedance
Data In
5V
...-
~h Impedance
Power
Active
Active
~-"---i
I Active
iA~
~ High Impedance
Active
Data Out
-
Active
_:.J
H, VIH. L VIL, *, VIH or VIL
The TMM27640 has three control functions. The
chip enable (CE) controls the operation power and
should be used for device selection.
The output enable (OE) and the program control
(PGM) control the output buffers, Independent of
deVice selection.
Assuming that CE = OE = VIL and PGM = VIH, the
output data IS valid at the outputs after address access
time from stabiliZing of all addresses.
The CE to output valid (tCE: IS equal to the address
access time (tACCI.
Assuming that CE = VIL, PGM = VIH and all addresses are valid, the output data is valid at the outputs after tOE from the failing edge of OE.
And assuming that CE = OE = VIL and all addresses
are valid, the output data IS valid at the outputs after
tPGM from the riSing edqe of PGM.
- 206-
•
OUTPUT DESELECT MOOE
Assuming that CE = VIH or OE = VIH, the outputs
'III be In a high Impedance state. So two or more
MM2764D can be connected together on a common
bus line. When CE IS decoded for deVice selection, all
deselected deVices are In low power standby mode.
STANDBY MOOE
The TMM2764D has a low power standby mode
ontrolled by the CE signal By applYing a TTL high
)Vel to the CE Input, the TMM2764D IS placed In the
tandby mode which reduce the operating current
from l20mA to 35mA, and then the outputs are In a
high Impedance state, Independent of the OE and the
PGM Inputs.
PROGRAM MODE
Initially, when received by customers, all bits of
he TMM2764D are In the "1" state which IS erased
tate.
Therefore the program operation IS to Introduce
'Os" data Into the deSired bit locations by electrically
Jrogrammlng.
The TMM2764D IS set up In the program operation
node when applied the program voltage (+21V) to
he Vpp terminal under CE = PGM = OE = VIH
The program operation occurs during the overlap
Jf the CE low and the PGM low Then the programnlng IS achieved by applYing a 50ms (tpw) active low
program pulse to the CE or the PGM Input after the
addresses and data are stable
This program pulse should be a Single pulse With
50ms pulse width per address word, and ItS maximum
value IS 55ms
The levels reqUired for all Inputs are TTL
The TMM2764D can be programmed any location
at anytime - either individually, sequentially, or at
random
The TMM2764D should not be programmed With
DC. signal applied to both CE and PGM Inputs.
The verify mode IS to check that the deSired data IS
correctly programmed on the programmed bits.
The verify IS accomplished With OE and CE at VIL
and PGM at VIH.
Under the condition that the program voltage
(+21V) IS applied to Vpp terminal, a high level CE or
PGM Input inhibits the TMM2764D from being programmed. Programming of two or more TMM2764Ds
In parallel With different data IS easily accomplished.
That is, all inputs except for CE or PGM may be
commonly connected, and a TTL low level program
pulse IS applied to the CE and PGM .of the desired
deVice only and TTL high level signal is applied to the
other devices.
- 207-
I
1918
17 16 15
10 11
12 13 14
------l]
AO.84
1
2
3
4
6
6
7
8
9
15.24:t0.3
\'I
'\
O.25~:~:
...
.
.;
N
I'i
0.48~:~:
Note 1
I.
17.4 MAX.
Note 2
.I
Note:
1. Each I••d pitch I. 2.54mm. All leeds are lOCated within 0.25mm Of their true longltudlnel position with resp-=t No.1 end No. 28 l..dL
2. Thll value Is m...ured at the and of leadL
3. All dlmanslons ara In millimeters.
Note
Toshiba do.. not assume .ny responSibility for use of any circuitry described, no cirCUit patent hcen581l ara Implied, and Toshiba reserves the
right, at any time Without nOtice, to change said circuitry
©Nov., 1981 Toshiba Corporation
- 208-
Mask Programmable Read Only Memories
- 209-
TOSHIBA Mas MEMORY PRODUCTS
2048 WORD x 8 BIT MASK ROM
TMM334P
N CHANNEL SILICON GATE DEPLETION LOAD
DESCRIPTION
TMM334P IS a 16,384 bits read only memory
organized as 2048 words by 8 bits and IS compatible
with 12716 type (16K EPROM). It IS sUitable for use
In programming of production apparatus used micro
processor because of ItS low cost per bit.
TMM334P's mask making IS camed out by com·
puter uSing punched paper tape data of customer and
then sample manufacturing will start Then for customer, 16384 bits memory data and three chip select
Input active logiC are programmable.
Therefore TMM334P manufactUring -procedure
goes through three steps before mass production
First step IS a acceptance of customer's punched
•
•
•
•
•
•
•
•
paper tape data. Second step IS a presentation of
programmed sample (Engineering Sample) for customers. Third step IS a verification of Engineering
Sample verification is most
Sample by customers
important and Toshiba will enter into mass production after above three steps are concluded. Then
Toshiba will adopt a established on-line system and so
can respond to a customer's needs qUickly and can
maintain a stable delivery.
TMM334P IS fabricated Jilth Ion Implanted Nchannel silicon gate technology. ThiS technology
allows a production of high performance TMM334P
IS moulded In a 24 pin standard plastiC pac~age
FEATURES
Single 5V supply voltage, Vee = 5V ± 10%
Access time, tAee = 450 ns (Max)
Directly TTL compatible, All Inputs and outputs
Programmable chip select Inputs, CS1, CS2, CS3 Easy memory expansion
Three state output, OR tie capability
Static operation, No clocks are required
Input protected, All Inputs have protection against static charge
Pin to Pin compatible, TMM323C, 12316E, 12716
BLOCK DfAGRAM
PIN CONNECTION
vee
(TOP VIEW)
TT
A,
CS3/CS3
CSI/CSI
AlO
I
CS2/CS2
cs,jcs,
CS2/CS-2
CSJ/CS3
0,
0,
0,
Os
0,
0,
GND
0,
A,
A,
A,
PIN NAMES
Ao - A6
---A7 "" A lo
Do -0 7
es,/ES; - eS,/C5,
Vee
GND
_.-
A"
AO
Row address Inputs
A.
Column address Inputs
A,
Data outputs
A)
Chip select Inputs
Vee Power Supply Voltage
A,
AS
A,
Ground
211 -
Memory cell array
128 x 128
SYMBOL
ITEM
VCC
VIN.VOUT
RATING
UNIT
Power supply voltage
-0.5-70
V
I nput and output voltage
-0.5-7.0
V
0-70
°c
Topr
Operating temperature
Tstg
Storage temperature
Soldering temperature time
TSOLDER
PD
Power Dissipation (Ta
SYMBOL
=
-55 -150
260 . 10
°c
°c sec
10
W
70 0 e)
PARAMETER
MIN.
TYP
20
-05
-
Input low voltage
-
Power supply voltage
-
45
VIH
VIL
I nput high voltage
VCC
CONDITIONS
..
,~
~
.'.
MAX.
Vee
-
UNIT
+'
V
O.S
V
55
V
"q.~M~'·
".no>
SYMBOL
PARAMETER
IIH
Input high current
IlL
I nput low current
VOH
Output high voltage
VOL
Output low voltage
10H
Output high current
10L
Output low current
ILO
Output leakage current
Icc
Supply current
CONDITIONS
,VIN = Vce
VIN = GND
ISOURCE = -0 4mA
ISINK =2.1mA
---------.-~--~,---
--
VOUT = 2.4V
VOUT = O.4V
VOUT = O.4V to Vce
lOUT =OmA
..•..
."
·w..
.....
.",
SYMBOL
PARAMETER
-
TYP
-
0.Q1
10
I'A
-0.01
-10
2.4
3.0
-
I'A
V
-
0.2
1--:=04
MAX.
04
UNIT
V
5.0
-
-
±0.01
±1O
I'A
-
40
SO
mA
2.1
CS' = O.SV. CS' = 2.0V
• Ta = 25°C. Vee = 5V
MIN.
-3.0
mA
rnA
-"
CONDITIONS
MIN
TYP.·
MAX
UNIT
tACC
Access time
tAC .,; lOOns
-
270
450
ns
tco
Output delay time from chip select
tAC ~ tACC
-
SO
120
ns
too
Output deselect time
RL = lOOn
0
70
100
ns
tAC
Read cycle time
-
450
-
ns
-
• Ta = 25°C. Vce = 5V
PARAMETER
CONDITIONS
UNIT
Input capacitance
VIN = A. C. GND
pF
Output capacitance
VOUT = A. C. GND
pF
Note. This parameter is periodically sampled and is not 100% tested.
- 212-
'"
cs/cs
nched paper tape data must be a positive logic and use a 7 to 8 bit ASC II code.
rmat 1 (including Data and Check sum every word).
NUl.L
'f' TMM334P· XXXX ..
CR L.F
.... MSB-D, ..
Take NULL more than fifty characters.
Contents in single quotation mark ('II' . .. 'II') indicates a comment and XXX X is a user's
number.
CR and LF indicate carriage return and line feed respectively.
Specify MSB pin. (D, or Do)
CR LF
N8;
N8 indicates a 8·bit mask pattern.
Semicolon ( ;) indicates a punctuation of data.
CR LF
RuuuO; X07P3; .... ; XF1Pf5;
CR LF
R indicates an absolute address.
words.
Enter the address by decimal code every eight
X Indicates hexadecimal code. So enter the data represented by hexadecimal code
every word after X.
CR LF
R2040; X01Pl; . .. : X3AP4;
CR L.F
P indicates a check sum of its word. So enter a sum of one's number in a word by
decima I code after P.
Data modification: Enter the modified address before the End mark and then enter
the data following above procedure independently or serialy. Modification can be
allowed from 0 address to 2047 address.
(CSt-G)
CR LF
Customers can program the active logic of three chip select inputs independently.
Specify the active logic of chip select input in the brackets.
The example is shown in Figure. In this example, chip is active under the condition
that CS1 = 'O~ and CS2 = '1' and CS3 = '0'.
CR L.F
(CS3" 0)
CR LF
$ Indicates an End mark.
CR LF
NULL.
Take NUL L more then fifty characters.
- 213-
I
Format 2 (including Data only every word)
NULL
"'TMM334P - XXXX'Y
CFI l.F
.Msa .. o,.
CR loF
N8:
CR LF
RuuuO, X075A ••
3BF1;
CR LF
R2032; XBCAE ••• 0085:
R Indicates an absolute address. Enter the address by decimal code every sixte,
words.
X indicates a hexadecimal code and so enter the data of sixteen words continuous
after X.
Data modification. This procedure is following to Format 1. Otherwise specified
Format 1.
CR LF
Format 1 and Format·2 are Toshiba preferred Format.
CR Lf
The other acceptable Format I, Intel BNPF Format.
CR LF
CR LF
242322212019181716151413
CR loF
----lI-J
NULL
R1,5
1
2
3 4
5 6
7
8
9 1011 12
.r.
CJ
Note: Each lead pitch il 2.54 mm. AU I••ds
locatl8d within
0.25 mm of their true longitudinal pOlltlon with respect
to No.1 and No. 24 lead'
All dimensions ar. In mllllm• • r.
~
O.S±O.15
Note:
[
17
a.StO.1S
i
"
c
e~
I
17.4 MAX.
I
,;
Note. Each teed pitch's 2.54 mm. All ,••ds are loeated within 0.25 mm longitudinal pOlltion With respect to No.1 and No. 24 Illads.
All dimensions ar. In millimeter•.
- 222-
~.
64K BIT (8K WORD X 8 BIT) MASK PROGRAMMABLE ROM
TMM2364P
N CHANNEL SILICON GATE
The TMM2364P IS a 65536 bit read only memory
organized as 8192 words by 8 bits with a low bit cost,
thus being most sUitable for use In programming of
production apparatus uSing mlcro-prooessor
Consisting of static memory cells and clocked penpheral circuitry, the TMM2364P provides a high
speed and low power dissipation (access time 250ns,
operating current 40mA)
The TMM2364P also features an automatic standby power mode When deselected by Chip Enable
(CE), the operating current IS reduced from 40mA to
15mA Output Enable (OE) IS effective In preventing
data confliction on a common bus line
The TMM2364P uses the address latch system that
the failing edge of CE latches all inputs except for
OE, thus can be easily connected to a system where
address and data buses are commonly used
The TMM2364P IS fabncated with Ion Implanted
N-channel silicon gate technology. This technology
allows a production of high performance
The TMM2364P IS moulded In a 28 pin standard
plastic package, 0 6 Inch In width
• Single 5V ± 10% power Supply
• Access Time 250ns max
• Low Power Dissipation
Average Current 40mA max.
Standby Current 15mA max.
• I nput and Output TTL Compatible
• Three State Outputs Wired OR Capability
• Edge En~bled Operation CE
• Output Buffer Control. OE
• Programmable Chip Select CS I , CS2
Easy Memory Expansion
• Pin Compatible with i2364
• I nputs protected
All inputs have protection
against static charge.
N.C.
28
~12
Vee
CSl/CSt
A,
A,
A,
cs,/CS,
A,
&J
A,
A,
A,
A,
D.
0,
0,
GND
DE
A,
Address inputs
Do - 0,
Data outputs
cstcs
Chip select Inputs
DE
No connection
Vcc
Power supply terminal
GND
Ground
I
es, iCS,
Ao-_s---,
..
~------1-~~~~~
A,
A,
Ao
A,
A,
Output enable Inpu
CE
NC
0, 0, 0, 0, 0, 0, 0, 0,
CS1/CS 1
~
Ao ..... All
~-===:-===
A,
OE
~
CE
0,
0,
0,
0,
0,
II
Vee GND
A.
Chip enable Input
A..
A"
A,,_-t......_-'
- 223-
65536 bits
Memory cell
array
SYMBOL
Vcc
VIN. VOUT
TOPR
TSTRG
TSO
Po
SYMBOL
ITEM
Power Supply Voltage
Input and Output Voltage
RATING
-0.5 -7.0
-05-7.0
0-70
-55 -150
Operating Temperature
Storage Temperature
Soldering Temperature· Time
PARAMETER
Input High Voltage
V,l
Input Low Voltage
Vcc
Power Supply Voltage
'c
'c
'c
250 10
10
Power Dissipation (Ta = 70'C)
V,H
UNIT
V
V
CONDITIONS
-
sec
W
MIN
TYP.
MAX
UNIT
22
-0.5
4.5
-
Vcc + 1
08
5.0
5.5
V
V
V
ITa = 0 - 70'C)
SYMBOL
I'H
I,l
VOH
VOL
IlOH
ILDl
ICCI
Icc.
PARAMETER
Input High Current
CONDITIONS
I nput Low Current
Y,N =5.5V
Y,N =GND
Output High Voltage
Output Low Voltage
IOH = -4OOp.A
IOl =3.2mA
Output Leakage Current
VOUT = 5.5V
I CE=22Vor
I 5E =2.2V
Standby Current
VOUT =0 4V
CE = 2.2V
Average Current
tCYC = 350ns. lOUT = OmA
• Typical values.reat Ta - 2SoC and Vee" 6V.
- 224-
MIN.
TYP.
MAX.
UNIT
p.A
-
0.05
10
-0.05
-10
p.A
24
3.3
-
V
-
0.3
0.4
10
-20
V
p.A
-
0.05
-0.1
8
20
15
40
p.A
mA
mA
• • •11• • • • (Ta =0 YMBOL
PARAMETER
70°C, Vee
=5V ± 10%)
CONDITIONS
tCE
CE pulse width
-
tAS
Address Setup Time
-
tAH
tACC
Address Hold Time
Access Time
-
too
Output Delay Time from DE
-
tOD
Output Turn off Delay
-
CE off Time
-
~
teye
Cycle Time
vpical values are at Ta" 2S0C and
tAS = Ons,
MIN
TYP
MAX
UNIT
250
0
50
-
-
ns
-
ns
250
120
70
ns
-
ns
-
ns
-
tr. tf
= 5ns
90
350
150
50
40
-
ns
ns
ns
Vee = 5V
Output Load: ITTL Gate + 100pF
Input Rise and Fall Times (10% - 90%)' 5ns
Input Pulse Levels 08- 24V
Timing Measurement Reference Levels Input, 1V and 2.2V
Output, 0.8V and 2.0V
I
- 225-
••••111
(Ta
=25·C. f =1MHz)
PARAMETER
CONDITIONS
UNIT
pF
Input Capacitance
VIN =AC GND
Output Capacitance
VO UT - A.C GND
pF
Note: This parameter Is pariocllcally sampled and is not 100% tested
ADDRESS, CS" CS,
MA~ CHANGE X~
______
CSt. CS2
'cc
'CE
'00
OE
HIGH-Z
00- 0 7
HIGH-Z
tCYC
Note (1)
too
Is specified from
De or CE. whichever occurs first.
- 226-
•
OPERATION MODE
~ote
CE
CS 1 , CS" Address
OE
OUTPUT
H
(1)
High Z
<-
Valid
(1)
(1)
L
(2)
L
(lJ
Don't care
(2)
CSt, CS2, Address may change after tAH
MODE
Standby
High Z
Latch
Data out
Read
1 cycle
r-
~
APPLICATION INFORMATION
60
1. POWER SUPPLY DECOUPLING
The operating current Icc waveforms for TMM2364P are shown In Fig
ICC
(mA)
50
40
30
1,2
20
The TMM2364P IS a clocked deVice, so the transient current peaks are produced on the CE transition and CE active level
The Icc current transients requrre adequate decoupllng of Vcc power
supply
10
100
200
300
400
500
Time (ns)
Fgl 1 ICC
\IS
tlma (CS
Select)
1 cycle
2. POWER ON
The TMM2364P requrres initialization prror to normal operation
Initialization methods are as follows.
Two
(1) A minimum 100!,s time delay IS requrred after 'the application of
Vcc (+5V) before proper deVice operation IS achieved And durrng
thiS perrod, CE must be at V ,H level
(2) A minimum 100!,s time delay IS requrred after the application of
Vcc (5V), and then a minimum of one Initialization cycle must be
performed before proper deVice operation is achelved
i-"1
ce-VIH
V,L
60
ICC
50
(mA)
40
30
20
10
o
io"'"
a
200
300
400
500
Time (nsl
Fig 2
Initialization cycle
100
tcc vs time (CS
Deselectl
An initialization cycle is one Chip Enable clock cycle from the frrst down edge of the
CE till the next down edge
I
- 227-
Use 7 or 8-bit (even parity) ASCII code paper Tape for ROM data input.
Two acceptable formats which are described in section A and B are available.
A. Format 1 (when a check sum per word is used)
Preceding the first data field and following the last data field there must
be a leader/trailer length of at least 50 null characters
NULL
'TMM2364P.QODO' )
Contents
·MSB = 0 , )
In
a single quotation mark (,
,) signify a comment and
DOD 0 indicates a four-digit user pattern number
NO. )
ROOOJ, X7FP7,
ROODs.
R DO 16,
,X07P3, )
X38P3,
Xl0Pl,.
. ,XE5P5, )
. "X6BP5.
)
) indicates carnage return and line feed
Spec.,fy the most significant bit (MSB) of the deVice outputs (0, or.oo)
N8 indicates that the mask pattern IS an 8-blt pattern
Semicolon ( , ) signifies a punctuation of data
R signifies an address. Enter the address with the four deCimal digits
every 8-words after the character R
X signifies a hexadecimal digit
Enter the data with the two hexadecimal digits every-word after the
character X
P signifies the check sum per word
Enter the sum of 1 In a one word deCimal after the character P
RS17G, X4DP4,
,XB5P5,,,
R8184, X2CP3,
,XA4P3.)
ICS, = 1) )
ICS,
= 0) )
$ )
NULL
• Data Mod Ificatlon
ModifYing single and continuous word data can be carned out by
specifying the modifYing addresses and inputting the data following the
above procedure before the end symbol
Modification can be allowed from to 8191 addresses.
a
Specify the actIve logic of chip selects (CS, and CS,) In the parentheses
respectively
Enter" 1" and "0" when active at high and low levels, respectively
An example is shown in the left figure
In thiS example. the deVice is selected under the condition that CS, and
CS, are at high and low levels, respectively
$ signifies the End symbol
- 228-
3 Format 2 (When a check sum per word
IS
not used I
NULL
'TMM2364P-DDDD .)
'MSB" 07,)
N8,~
RODDa,
X7F5A..
39ES")
RoD16 . Xl08C
8241; )
RD032 . X2DBA
.. 36C7, )
R signifies an address.
Enter the address with the four decimal digits every sixteen words after
the character R.
X signifies a hexadecimal digit
Enter the data of sixteen words continuously after the character X
Otherwise specified
R8160, X1EC5..
In
Format 1
.310E,)
RS'76, X4DA6
1 BA4,
)
(CSt"" 1) )
ICS, -01 )
$
,
NULL
In additIon, Toshiba can also accept programming and masking information for TMM2364P in the form
of punched paper tape with Intel BNPF format or master deVIces (EPROMsl.
I
- 229-
Unit
28 27 26 25 24
23 22
mm
21 20 19 18 17 16 15
~:~~~~[:~~]]
1
2
3
4
5
6
7
8
9
10 11 12 13 14
374 MAX.
1524 TYP
5°
5°
x
..""
Z
2
264±026
Note
1 4±0 15
02 MAX
"
M
025+01
-005
I.
17 4 MAX
.1
EKh leed pitch IS 2 54 mm.
All leeds are located Within 026 mm of thel' true longitudinal pOSition with respect to No 1
end No 28 leads
Note. Toshiba do .. not ...ume any responslblhtY for use of any Circuitry dascrlbed, n'O circuit patent llcen..s a,.. Implied, and Toshiba , ...rv..
the fiGht, 111: any tune without notice, to change uld CirCUitry
©AUII., 1980 Toshiba Corporation
- 230-
TMM2365P: 8K WORD x 8 BIT MASK ROM
TMM2365P
N CHANNEL SILICON GATE
*This is advance information and specifications.,.
subject to chenge without notice.
• Access T I me 200ns
• Power Dissipation
Operating Current. 100mA (MAX.)
Standby Current
25mA (MAX.)
• 5V Single Power Supply
5V ± 10%
• Fully Static Operation
• Three Programmable Chip Select Inputs
CS,/CS-" CS 2 /CS 2 , CS 3 /CS-3
• All Inputs and Outputs Directly
TTL Compatible
• Three State Outputs
• Compatible With 2764 type EPROM TMM2764D
• 28 Pin Standard Plastic Package
64k Bit EPROM
TMM2764D
(Top View)
VCCGND
N.C.
Au
A,
A.
A,
A.
A,
A,
A,
A,
Vee
CS1/CS,
CS 1 /CS1
ii
Vee
Au
A,
l'ml
A.
A,
A.
A,
A,
A,
A,
A,
A.
0,
0,
0,
0,
0,
0,
GND
GND
N.C.
Do~D,
CS,/CS.
A"
~
A"
CSt/CSt
Cl!"
0,
o.
0,
O.
0,
CS1 /CS3
6E
A,
Ao '" An
Do - 0 7
CS" CS2 • CS 3
~
Address Inputs
Outputs
Chip Select Inputs
OE
Output Enable Input
Vee
GND
Power Supply (5V)
Ground
An
- 231-
I
•
~
co
f
e
..
~
Memory Cell
Arrav
8kx8
Nate:
TCiltuba does not a ...... any respon.bllity for u .._of any cIrCuitry dncrlbad: no ClfC,"t patant lleanses ara Impll«l. and TO.... lba ,...",..
the right. at any tl,.,. without notice. 10 chan. . aid CircUitry.
@Apr•• '982 ToshibeCorporetlon
- 232-
TMM2366P: 8K WORD
x 8 BIT MASK HUM
TMM2366P
N CHANNEL SILICON GATE
*Thls is advance information and specifications are
subject to change without notice.
• Fully Static Operation
• Programmable Chip Select CSICS
• All Inputs and Outputs Directly TTL
Compatible
• Three State Outputs
• 24 Pin Standard Plastic Package
• Access Time 200ns
• Power DIssipation
Operating Current
100mA
Standby Current
25mA
• 5V Single Power Supply
5V ± 10%
32k Bit Mask ROM
TMM333P
(Top View)
Vee
A.
A,
CS1/CS1
CS,lCS,
A,
A.
A,
A.
A,
A,
A,
0,
0,
D.
0,
0,
o.
A.
0,
0,
0,
GND
0,
GND
A,
L..._ _ _- '
Do - D7
CSICS
Voo
GND
Address Inputs
Outputs
Chip Select Input
Power Supply (5VI
Ground
rr
00 - 0 ,
CS/CS
A"
A"
0,
D.
'-------'
0,
D.
0,
Pm Compatible with 32K Bit ROM TMM333P
for Memory Expansion
Ao -All
Vee GND
I
[
I
[
A,
I
A"
- 233-
~.,"
Memory Cell
Array
8kx8
I
Note:
TDlhiba does not assume any responsibility for use of any circuitry described, no circuit patent hcenses are Implied, and Toshiba reservu
the right, at any time without notice, to change said CirCUitry
©Apr•• 1982 Toshiba Corporation
- 234-
MEMORY
TMM23256P 256K BIT (32K WORD x 8 BIT) MASK PROGRAMMABLE ROM
T M M 2 3 256 P
N-<:HANNEL SILICON GATE MOS
The TMM23256P is a 262,144 bit read only
memory organized as 32,768 words by 8 bits with a
low bit cost, thus being most suitable Ifor use in
character generator.
Consisting of static memory cells and clocked peripheral cirCUitry, the TMM23256P provides a high
speed and low power dissipation (access time 150ns,
operating current 40mA)
The TMM23256P also features an automatic standby power mode. When deselected by Chip Enable
(CE). the operating current IS reduced from 40mA to
10mA. Output Enable (DE) is effective in preventing
data confliction on a common bys line.
The TMM23256P uses the address latch system
that the falling edge of CE latches all inputs except
for OE, thus can be easily connected to a system
where address and data buses are commonly used.
The TMM23256P is fabricated with ion implanted
N-channel silicon gate technology. This technology
allows a production on high performance.
The TMM23256P is moulded in a 28 pin standard
plastic package, 0.6 inch in width.
• Single 5V Power Supply
• Fast Access Time
150ns (Max.)
• Low Power Dissipation
Average Current : 40mA (Max.)
Standby Current : 10mA (Max)
• Inputs protected
All I nputs have Protection
Against Static Charge
•
•
•
•
•
N.C.[
~ pvcc
Au[ 2
A7[
3
A6[ 4
A,[ •
A4[ •
A,e 7
A;[
8
A;[ 9
A~[
A" -
~~14
2.
27
25
24
23
22
10
19
18
12
17
0,[ 13
GNO[ 14
16
A,.
Do - 0 7
OE
CE
p~13
AS
PA 9
pAn
poe
DODID:J03D4D SD 6D ,
OE
Output
Buff....
Chip, Enable
eE
Input Buffer
and Clock
21 PA,O
2.
Doe 11
Ol[
Edge Enabled Operation : CE
Output Buffer Control : DE
Input and Output: TTL Compatible
Three State Outputs: Wired OR Capability
28 pin Standard Plastic DIP
16
pee
P07
bo.
po,
po.
AO
AI
A,
A,
po,
A.
AS
A.
AS
Data Outputs
¥
0
~
Chip Enable Input
No Connection
Po"",,r Supply Terminal
GND
Ground
j
.
Output Enable Input
Vce
8 x 64
A~
Address Inputs
N.C.
Column
DecOder
II:
- 235-
512
262,144 bits
Memory can
array
I
SYMBOL
Vcc
Y,N, VOUT
RATING
UNIT
Power Supply Voltage
ITEM
-05-70
V
Input and Output Voltage
-05-70
T OPR
Operating Temperature
TSTRG
Storage Temperature
-55- 150
TSOLDER
Soldering Temperature Time
260
Po
Power DISSipation (Ta " 70°C)
SYMBOL
PARAMETER
V,H
Input High Voltage
V,L
Input Low Voltage
Vcc
Power Supply Voltage
SYMBOL
PARAMETER
0-70
V
I
°C
,I~:
°C sec
10
W
10
CONDITIONS
-
MIN
TYP
-05
45
CONDITIONS
MAX
-
22
Vcc
5,0
MIN
I
°C
TYP
UNIT
+1
V
08
V
55
V
MAX
UNIT
I'H
I,L
Input High Current
Y,N = 5 5V
-
005
10
/lA
1nput Low Current
Y,N - GND
-
-005
-10
/lA
VOH
Output High Voltage
IOH = -400/lA
24
33
-
V
VOL
Output Low Vo Itage
IOL - 3 2mA
03
ILOH
Output Leakage Current
VOUT = 5 5V
ICE = 22Vor
-
VOUT =04V
0,05
I 5E = 2 2V
-
-01
ICCI
Standby Current
CE = 2 2V
lee2
Average Current
tcvc = 230ns, lOUT = OmA
-
-
ILDL
• TYPical values are at Ta = 25°C and Vee = 5V
(Ta = 25°C, f = 1MHz)
PARAMETER
Note
CONDITIONS
Input Capacitance
VIN -A C GND
Output Capacitance
VOUT = A C GND
This parameter IS periodically sampled and IS not 100% tested
- 236-
04
10
V
/lA
-20
/lA
10
mA
40
mA
a -70'C,
ITa =
•
Vcc = 5V ± 10%)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tCE
CE pulse width
-
150
-
ns
tAS
Address Setup Time
-
a
-
ns
tAH
Address Hold Time
-
30
-
-
tAce
Access Time
-
Output Delay Time form OE
150
70
too
Output T urn off Delay
70
ns
tcc
CE off Time
70
-
ns
too
-
-
ns
tCYC
Cycle Time
230
-
SYMBOL
PARAMETER
TYPical values are at Ta
=
-
-
tAS - Ons, t r. tf
25f'C and Vee
= 5ns
-
ns
ns
ns
= 5V
~~~
•
•
•
•
Output Load . 1TT L Gate + 100pF
Input Rise and Fall Times (10% - 90%)
Input Pulse Levels
0.8 - 2.4V
Timing Measurement Reference Levels
)<
AO -A14
5ns
Input
1V and 2.2V
Output, 0.8V and 2.0V
K
ADDRESS
VALID
ADDRESS MAY
~~
CE
CH~NGE
X
tcc
tCE
I
~
~--
I
too
'\l-
OE
/
tAce
HIGH·Z
00- 0 7
~
~
tCYC
Note (1)
too
IS specified from
OE
or
CE, whichever occurs first.
- 237-
~.,..
DATA VALID
¥
HIGH-Z
I
put buffers, independent of device selection .. Assuming that OE = VIL, the output data IS valid at the
outputs after tACC (150ns) from the failing edge of
the CEo
The TMM23256P has two control functions.
The chip enable (CE) controls the operation power
and should be used for device selection. The falling
edge of the CE will activate the device and latch the
addresses. The output enable (OE) control the out-
The operation modes of tt18 TMM23256P are listed in the following table
MODE
Standby
Latch
Read
Output Deselect
Note
•
.
CE
H
ADDRESS
""L-
Valid
L
L
...
OE
..
OUTPUT
High Impedance
High Impedance
,-
L
H
Data Out
High Impedance
Active
Don't care
Address may change after tAH.
- 238-
POWER
Standby
Active
. '; ..
"
_L~~1'lON
1. POWER SUPPLY DECOUPLING
The operating current IcC waveforms for TMM
23256P are shown In Fig 1,2
The TMM23256P IS a clocked device, so the transient current peaks are produced on the CE transition
and CE active level
The Icc current transients require adequate decoupling of Vcc power supply.
1 cycle
Co
2. POWER ON
The TMM23256P reqUires Initialization pnor to
normal operation. Two initialization methods are as
follows
(1) A minimum 100llS time delay IS required
after the application of Vcc (+5V) before
proper device operation IS achieved And durIng thiS penod, cr must be at V,H level.
(2) A minimum 100lls time delay IS required
after the application of Vcc (5V), and then a
minimum of one Initialization cycle must be
performed before proper del/Ice operation IS
achelved
Initialization cycle. An initialization cycle IS one
Chip Enable clock cycle from the first down edge of
the CE till the next down edge.
oe
2.2V
o.OV
<
.§
80
U
60
E
IL - _1.1
oov
•
/\
J" 1'\
40
20
.NT
~
,II
'./ Ir--.I
~
100
200
300
400
1 cycle
_
20V
Oe
OOV
20V
c.
~- -I-'
O.OV
!<
~
80
60
40
20
I
,11\
"- 'IiI
o
100
200
I-
II
Vir 1--1/
300
400
Time (ns)
FIG 2
- 239-
600
Time ens)
ICC liS. Time (2)
500
Unit: mm
~Lf~~~~I~~::3]
,
2
3
4
5
6
7
8
9
10 11 12
13 14
15.24 Typ.
2.54±O.25
1.4±O.15
02 MAX.
i
:i
N
M
Note
I.
17.4 Max.
Each lead pitch IS 2,54 mm
All leeds .relocated within 0.25 mm of their true Ilngitudinal position with respect to No.1 and No 28 leadl.
Note.
Toshiba does not assume any responsIbIlity for use of any circUItry described, no circuit patent licenses are Implied, and ToshIba reserve.
the fight, at any tlme without notice, to change said circuitry.
© Nov,
1981 Toshiba Corporation
- 240-
"
'"
MOS Mask Programble Read Only Memory
- 241-
32 K Bit CMOS MASK ROM COMPARISON TABLE
PIN CONFIGURATION
TC5334P
TC5333P
TC5332P
Voo
AS
A,
5.E2!~Ei
___ __ _
AIO
All
All
07
07
Operation Mode Table
TC5333P
TC5332P
~PinName
CE/CE
Ol:
(18)
(20)
Address Latch
Read
Standby
~
H/L
L/H
H/L
~
L
CEI/CE I
CE,/IT,
l'lumber
Output Deselect
.
Addresses
Valid
··
--------
Power
IT
OE
(18)
(20)
~
t-
ActIve
Standby
L
H
Outputs
Dout
-------H,gh-Z
H,gh-Z
Active
H
Fully Static Operation (Asynchronous Type)
Operation Mode
Number
Addresses Latch
Read
Standby 1
Standby 2
Output Deselect
Operation Mode
(20)
-H/L
L!H
--------
.
(21)
-------L/H
Power
Hlgh-Z
Dout
High-Z
ActIve
Standby
L
-
H
Hlgh-Z
Active
L
Address Latched OperatIon (Synchornous Type)
TC5535P
Power
Addresses
Outputs
~
~
Valid
Dout
H,gh-Z
Active
----------Standby
Hlgh-Z
Standby
. ·
·
----- ----H/L
Outputs
Valid
· ·
· ··
TC5534P
~r~Name
Addresses
--
-----
Fully StatIc OperatIon (Asynchronous Type)
- 243-
CE
OE
(20)
(21)
'L
H
·
·
L
Addresses
Outputs
Valid
Hlgh-Z
-
Oout
Active
Hlgh-Z
Standby
··
·
----------
Power
~
Hlgh-Z
H
Active
-----------------Address Latched OperatIon (Synchronous Type)
L
,
(
, '\ ~,,',
,
---
,:..
".,
/~
.';"
.
.
.....
:~
tOstlBA MOSMEMORY PRODUCTS
.K WORD x 8 BIT CMOS MASK ROM
TC5332P
,ILICON GATE CMOS
DESCRIPTIoN
The TC5332P is a 32,768 bit low power read only
lemory organized as 4,096 words by 8 bits using
:MOS technology, and operates from a single 5V sup,Iy.
The TC5332P has a programmable chip enable
lput (CE/CE) for device selection and a output
nable Input (OE) for fast access and output control.
"he maximum access times from address and chip
mble are both 450 ns.
The TC5332P is pin compatible with the industry
produced NMOS ROM TMM2332P, yet offers a more
than 90% reduction in power of their NMOS equivalent. The TC5332P's maximum operating and standby current IS 7mA and 20p.A, respectively. Thus the
TC5332P is most suitable for use in low power
applications such as battery operated system.
The TC5332P is molded in a 24 pin standard
plastic package.
f!!A lURES
• Access Time' 450ns
• Low Power DiSSipation
1000 = 7mA (Max.) : Operating
loos = 20p.A (Max.) : Standby
• All Inputs and Outputs: TTL Compatible
• Three state outputs
•
•
•
•
•
•
'~~DrCONNEcTION ITOP VIEW}
Fully Static Operation
Two Control Functions' CE/CE, OE
Programmable Chip Enable: CE/CE
Output Control, 5E
Pin Compatible with TMM2332P and TMM2732D
Standard 24 pin Plastic Package
BLOCK DIAGRAM
VDD GND
OE
o----- 2=5~C5V
/
0.4
08
12
VOL [vI
IODS2 vs Ta
100
10
-40
40
I
80
Ta (oCI
- 249-
Use 7 or B-bit (even parity) ASCII code paper tape for ROM data input.
Two acceptable formats which are described in section A and Bare avai 1able.
A. Format 1 (when 8 check sum per word it ullld)
Preceding the first data field and following the last data field there must
a leader/trailer length of a least 50 null characters.
NULL
TC5332P-0000)
'MSB= 0,'
N8;
)
.J
ROOOO; X7FP7; .... ; X07P3;)
R0008; X38P3; .... ; XE5P5; .J
R 0016; Xl0Pl; .... ; X6BP5;)
Contents In a single quotation mark (. . . . . . .I signify a comment a
0000 indicates a four-digit user pattern number.
) indicates carriage return and line feed.
Specify the most significant bit (MSB) of the device outputs (0 7 or 0
N8 indicates that the mask pattern is an B-bit pattern.
Semicolon ( ; ) signifies a punctuation of data.
R signifies an address. Enter the address with the four decimal digits evel
8-words after the character R.
X signifies a hexadecimal digit.
Enter the data with the two hexadecimal digits every word after the chara.
ter X.
P signifies the check sum per word.
Enter the sum of 1 in a one word decimal after the character P.
R4080;X40P4; .... ;X8BP5;)
R4088;X2CP3; .... ;XA4P3;1
(CS=l»)
• Data Modification
Modifying single and continuous word data can be carried out by specif.,
ing the modifying addresses and inputting the data following the abov
procedure before the end symbol.
Modification can be allowed from 0 to 4095 addresses.
Specify the active logic of chip enable CE/CE (18PIN) in the parentheses
Enter CS = 1 and CS = 0 when active logic of chip enable is at high and lOY.
levels, respectively.
An example is shown in the left figure.
_
In this example the device is selected under the condition that CE/CE il
at high level.
NULL
$ signifies the End symbol.
- 250-
•
3, Format 2 (When a check sum per word is not used)
NULL
TC5322P·0000)
'MSB
= D,)
NS; )
I
39E5, )
R 0000, X7F5A .
R 0016, X10BC .... B241,)
R 0032, X2DBA..
36C7,)
R signifies an address
Enter the address with the four deCimal digits every sixteen words after the
character R
X signifies a hexadecimal digit.
Enter the data of sixteen words continuously after the character X
Gtherwlse specified In Format 1.
R4064, X1EC5
31DE;)
R40S0, X4DA6.
(CS
. 1BA4, )
= 1))
$ )
NULL)
In addition, Toshiba can also accept programming and masking information for TC5332P
paper tape with Intel BNPF format or master deVices (EPROMs).
- 251-
In
the form of punched
242322212019181716151413
-----11-]
1
2 3 4
5 6
7 8 9101112
o
UIUII/_--J...~
~
Not. each Iud pitch IS 2 54 mm All I.adt are locat.d within 0 25 mm of th.lr true longitudinal pOllltlon with respect to No 1 and No 24 leads
All dlm.nslons ara In mllllm.t....
Nota Toshiba does not anum. any responsibility for UH of any CircUity descnbed, no Circuit pat.nt IIc.n ... are Implied and Toshiba reserve the right,
at any tim. Without notice, to change said Circuitry
CI Spt. 1981 Toshiba Corporation
- 252-
4,096 WORD X 8 BIT CMOS MASK ROM
TC5333P
SILICON GATE CMOS
The TC5333P is a 32,768 bit low power read only
memory organized as 4,096 words by 8 bits using
CMOS technology, and operates from a single 5V
supply.
The TC5333P has a chip enable input (CE) for
device selection and ~ output enable input (OE)
for fast memory access and output control. And the
TC5333Puses the address latch system that the falling
edge of CE latches all inputs except for OE, thus
can be connected to a system where address and data
buses are commonly used. The maximum access
• Access Time: 450 ns
• Low Power Dissipation
IDDO = 7mA (Max.) : Operating
IDDS = 20l'A (Max.) Standby
• All Inputs and Outputs: TTL Compatible
• Three State Outputs
time from chip enable is 450 ns.
The TC5333P is pin compatible with the industry
produced NMOS ROM TMM2332P, yet offers a more
than 90% reduction in power of their NMOS equivalent.
The TC5333P's maximum operating and
standby current is 7 mA and 20 I'A, respectively.
Thus the TC5333P is most suitable for use in low
power appl ications such as battery operated system.
The TC5333P is moulded in a 24 pin standard
plastic package.
•
•
•
•
•
Two Control Functions. CE, OE
Address Latches: CE
Output Control: OE
Pin Compatible with TMM2332P and TMM2732D
Standard 24 pin Plastic Package
111111111111 (TOP VIEW)
Voo GND
I I
VDD
A.
A,
A,
A.
A3
DE
A.
DE
All
A2
A,O
AI
CE
CE
Ao
07
Do
D.
0,
0,
AI
02
0,
A2
03
A3
AO
A,
As
Ao-Al1
Address Inputs
A.
Do - D7
CE
OE
Data Outputs
Chip Enable Inout
Output Enable Input
A7
A.
A.
Voo
Power (+5V)
A,O
GND
Ground
All
- 253-
~..
..
-I'
~
£
..
~
128
Mwnorv Cell Arr.y
(266)( 128)
-+
SYMBOL
Voo
VIN
--
ITEM
RATING
Power Supply Voltage
-0 3V -7.0V
Input Voltage
-0 3V-7 OV
VOUT
Output Voltage
Po
Power DISSipation (Ta - 85°C)
TSTG
Storage Temperature
OV-Voo
TOPR
OperatIng Temperature
TSOLOER
Soldenng Temperature Time
SYMBOL
Voo
..
+-
~ ______ ,
_V,L_____
_
260°C ,0 sec
r~~1
'b."'>i~"!
PARAMETER
-'-----1;,'
..
08W
-55°C - ,50°C
-40°C_85°C
Power Supply Voltage
Input High Voltage
MIN.
TYP
MAX.
4.5
50
55
V
Voo+0.3
08
V
2.2
UNIT
-0.3
V
·-;-I_n~p=::..u-:-t~_L-:O~W~_V-:..o_:.l-:-t_'a-"g:e~_-~~~~~~~~~~-~~~~~~~~~~_-1:~~3j;~_-1:~_-~~~~_+::}::i::~1~~_--:j~_-_-1.J
.........
PARAMETER
-...s.Yf,,1BOL
_!IL
0 ~ V,N
--'.L9._-C!ut p ut L"akage Current
~___
Output High Current
_I~L
J.~E = V'H.,o."'£"""t ~ Voo
, VOH = 2 4V
_
I
..
-
Standby Supply Current
10001
InP~~,_~ VIH
or VIL
ICE =VOO -02V
"ther Inputs = 0 2V or Voo -0 2V
I
CE = V,L, teye - , IJS,
I Operating Supply
V,N = V,H N,L, lout = OmA
'I'S.
Current
CE = OV, teye V,N = VOO/GND. lout = OmA
10002
Nota. TYPical values are at Ta'" 25°C, Voo
SYMBOL
I other
=
MIN
TYP
MAX
-
-
±'O
p.A
±50
IJA
rnA
-1.0
20
CE = 2 2V
100S2
5V.
PARAMETER
Input Capacitance
COUT
I
< Voo
O~~~~_,,~~W Current___ ~~I,._~ _o~~y
100S1
--
CONDITIONS
,
Input Load Current
Output Capacitance
Note' This parameter IS periodically sampled and is not 100% tested.
- 254-
40
-
20
50
-40
I
i
-
-
I
I
0.05
I
UNIT
rnA
20
rnA
IJA
' - 1-----
60
,0.0
mA
40
70
rnA
:f'll.'I!f:~K.:
MIN,
TYP,
MAX.
UNIT
-
450
ns
Output Enable Access Time
-
150
ns
tAS
Address Setup Time
30
-
ns
tAH
Address Hold Time
30
70
-
ns
CE OFF time
-
-
100
ns
540
-
-
ns
SYMBOL
PARAMETER
tACC
Chip Enable Access Time
tOE
tcc
---"
tCEH
Chip Enable Hold Time
too
Output Desable Time
tCYC
Cycle Time
450
A.C. TEST CONDITIONS
Output Load
100pF + lTTL Gate
Input Pulse Levels
a 6V, 2 4V
Timing Measurement Reference Levels
Input
8V and 2 2V
Output a 8V and 2 2V
Input Pulse Rise and Fall Times
10 ns
a
OPERATION MODE
MODE
Read
Standby
Address
Latch
OUTPUTS
CE
OE
ADDRESS
L
L
.
*
*
High Z
*
Valid
High Z
H
L
Data out
Don't care
- 255-
ns
ns
Use 7 or 8-bit (even parity) ASCII code paper tape for ROM data input.
Two acceptable formats which are descnbed In section A and B are available.
A
Format 1 (when a check sum per word is used)
NULL
'TC5333P-Oooo' )
'MSB
= 07')
N8,)
RoooO,X7EP7,
,X07P3, )
RoooB,X38P3;. . .
,XE5P5,)
ROO16,Xl0Pl, .
,X6BP5; )
R4080,X40P4;.
. ,XB5P5; )
R4088,X2CP3,. ... ,XA4P3,)
Preoadlng the first data field and follwing the last data field there
must be a leader/trailer length of at least 50 null characters.
Contents in a single quotation mark (' . . . . . ') signify a comment
and DODO indicates a four-digit user pattern number.
)
Indicates carriage return and line feed.
Specify ,the most Significant bit (MSB) of the devioa outputs (07 or Do)
N8 indicates that the mask pattern IS an 8-bit pattern.
Semicolon (.) Signifies a punctuation of data.
R Signifies an address. Enter the address with the four decimal digits
every 8-words after the character R.
X signifies a hexadecimal digit. Enter the data with the two hexadecimal digits every word after the
character X.
P. signifies the check sum per word.
Enter the sum of 1 in a one word deCimal after the character P.
• Data Modification
ModifYing single and continuous word data can be carned out by
speCifYing the modifYing addresses and Inputting data following the
above procedure before the end symbol.
Modification can be allowed from 0 to 4095 addresses.
$)
NULL
$ signifies the End symbol.
- 256-
B
Format 2 (when a check sum per word f,s not used)
NULL
'TC5333P-OOOO' )
'MSB
= D7')
N8,)
ROOOO,X7F5A
39E5, )
J
RP016,Xl08C
B241.
R0032,X2DBA
36C7, )
R4064,Xl EC5
31DE, )
R4080,X4DA6
lBA4,
R sign if,es an address.
Enter the address with the four aecimal digits every sixteen words
after the character R.
X signifies a hexadecimal digit.
Enter the data of sixteen words continuously after the character X.
Otherwise specified in Format 1.
J
$ )
NULL
In addition, Toshiba can also accept programming and masking Information for TC5333P in the form of
punched paper tape with Intel BNPF format or master devices (EPROMs).
- 257-
~~~:~~~~:~]]
1
2
3
4
5
6
7
8
9 10 11 12
o
~
I
17.4 MAX.
.I
Note' Each teed pitch's 2.64 mm. All leeds ere located within 0.215 mm of theIr true longitudinal polltlon with r •• pect to No.1 and No. 24 leed••
All dimensions ... In mTlllmlt'htn.
Nota Toshiba do.. not anuma any responsibility for use of any circuity descrtbed, no CirCUit patent IIcttnses are Implied and Toshiba reserve the right,
at any tima without notice, to change seld circuitry
e Mar., 1982 Toshiba corporation
- 258-
TOSHIBA MOS MEMORY PRODUCTS
4,096 WORD x 8 BIT CMOS MASK ROM
TC5334P
SILICON GATE CMOS
DESC8IPTtC:*
The TC5334P IS a 32,768 bit low power read only
memory organ !Zed as 4,096 words by 8 bits uSing
CMOS technology, and operates from a single 5V
supply.
The TC5334P has two programmable chip enable
Inputs (CE1/CEl and CE2/CE2) for device selection.
The maximum access times from address and chip
enable are both 450 ns
The TC5334P IS pin compatible with the Industry
produced NMOS ROM TMM333P, yet offers a more
than 90% reduction In power of their NMOS equIvalent
The TC5334P's maximum operating and
standby current IS 7mA and 20/lA, respectively Thus
the TC5334P IS most sUitable for use In low power
applications such as battery operated system
The TC5334P IS molded- In a 24 Pin standard
plastiC package.
-~
• Fully Static Operation
• 'wo Programmable Chip Enables
CE 1ICE 1, CE 2/CE2
• Pin Compatible with TMM333P
• Standard 24 pin PlastiC Package
• Access Time 450 ns
• Low Power DISSipation
1000 = 7 mA (Max.) Operating
loos = 20/lA (Max.) Standby
• All Inputs and Outputs TTL Compatible
• Three State Outputs
VOD GND
I I
VDD
As
DO 0102030405 06 07
o
A,
eE2/eE2
eel/eEl
AIO
c
eE2
All
07
0,
AO
0,
Al 0 - - -
0,
A,
0,
A,
A'0As
I
Ao
-All
Do - 0
7
Address Inputs
A6
Data Outputs
A7
CE llCE l
I
Chip Enable Inputs
l-_~C_E.-.,:.../C_E-','------t . ___ .__ -_.-----------1
AS
A,
VDD
Power (+5VI
AlO
GNO
Ground
AIIO
- 259-
<
~
~
~
~
12.
Memory Cell Array
(256 x 128)
I
I
~OL
ITEM
RATING
V DD
Power Supply Voltage
-0 3V -70V
VIN
Input Voltage
-0 3V -7 OV
VOUT
PD
Output Voltage
OV-VDD
08W
Power Dissipation (Ta - 8SoC)
TSTG
Storage Temperature
_55°C - 150°C
lOPR
Operating Temperature
-40°C - 85°C
TSOlDER
Soldering Temperature Time
250°C· 10 sec
PARAMETER
SYM80L
r-------
VDD
t------=----~
MIN
Power Supply Voltage
TYP
MAX.
UNIT
4.5
5.0
5.5
V
-
VDD+O 3
08
V
-----------
VIH
Input High Voltage
22
_'1IL..._
Input Low Voltage
-0 3
SYMBOL
CONDITIONS
PARAMETER
III
I nput Load Current
OSVINSVDD
ILO
Output Leakage Current
CE = Vil ICE = VIH), OV S Vout SYD D
IOH
Output High Current
VOH -24V
Output Low Current
VOL =OAV
CE, - a 8V'or CE, - OS-V
IOl
I-c--,--1--IDDSt
Standby Supply Current
IDDS2
leE, =22VorIT, =22V)
CE, = a 2V or CE, = a 2V
leE'=VDD -02VoreE, =VDD -02V)
CE, = CE, = VIH
r--~
IDD01
ICE, = eE, = Vll) teye = 1jlS
Operating Supply
VIN = VIHNll lout = OmA
Current
CE, - CE, - VDD
IDD02
lIT, = eE, = OV) teye = 1IJ.s
VIN = VDD/GND lout = OmA
Note
Typical value, are at Ta '"' 25°C. VOO "" 5V
SYMBOL
PARAMETER
I----"C"IN'-_ _ _ _+-_~lnput Capacitance
COUT
Output Capacitance
Note. This parameter Is perlodlc.l1y sampled and 15 not 100% tested
- 260-
V
MIN
TYP
MAX
-
-
±1.0
IJ.A
-
.±5 a
-10
-40
20
40
-
IJ.A
mA
-
05
50
-
005
-
UNIT
mA
mA
20
JJ.A
50
10 a
mA
40
70
mA
I
-
MIN
TYP
MAX
UNIT
IACC
tCE
SYMBOL
Address Access Time
PARAMTER
-
450
ns
Chip Enable
-
-
450
ns
taD
Out put Desable Time
100
tCYC
Cycle Time
ns
ns
Access-Time
450
-
-
A.C. TEST CONDITIONS
Output Load
100pF + 1TTL Gate
Input Pulse Levels
a 6V, 2 4V
Timing Measurement Reference Levels
Input
O.BV and 2.2V
Output· O.BV and 2 2V
Input Pulse Rise and Fall Times
MODE
Read
10 ns
CE,(CE,I CE,ICE,I ADDRESS
HIL)
Valid
Hill
Standby
LlH)
'1')
*1*1
LlHI
*
*
OUTPUTS
Data out
HlghZ
High Z
Don't care
- 261-
I
1'1
Use 7 or S-bit (even parity) ASCII code paper tape for ROM data input.
Two acceptable formats which are described in section A and B are available.
A. Format 1 (when a check sum per word is used)
NULL
'TC5334P-0000 )
'MSB = 07')
N8,)
. ;X07P3, )
RoOOO,X7FP7,
,XE5P5,)
Roo08;X38P3;
,X6BP5,~
Roo16,XlOP1,
Preceding the first data field and following the last data field therE
must be a leader/trailer length of at least 50 null characters.
Contents in a single quotation mark (' . . . . . ') signify a comment
and 0000 indicates a four-digit user pattern number
~ indicates carriage return and line feed.
Specify the most significant bit-{MSB) of the device outputs (07 or Do)
NS indicates that the mask pattern is an S-bit pattern.
Semicolon(;) signifies a punctuation of data.
R signifies an address. Enter the address with the four decimal digits
every S-words after the character R.
X signifies a hexadecimal digit.
Enter the data with the two hexadecimal digits every word after the
character X
P signifies the check sum per word.
Enter the sum of 1 in a one word decimal after the character P.
• Data Modification
Modifying single and continuous·word data can be carried out by
specifying the modifying addresses and inputting data following the
above procedure before the end symbol.
Modification can be allowed from 0 to 4095 addresses.
R4080,X40P4,
. ,XB5P5; )
R4088,X2CP3;
.. ;XA4P3, )
(CS, = 1) )
(CS. = 01 )
$)
Specify the active logic of chip enables CE ,tCEl (20 PIN) and CE2/
CE2 (21 PIN) in the parentheses respectively.
Enter CS1 = 1 or CS1 = 0 when active logic of CE ,tCEl is at high
or low levels, respectively.
Enter CS2 = 1 or CS2 = 0 when active logic of CE 2/CE2 is at high
or low levels, respectively.
An example is shown in the left figure.
In this example, the device is selected under the condition that CE 1/
CEl and CE2/CE2 are at high and low levels, respectively.
$ signifies the End symbol.
NULL
- 262-
B. Format 2 (when a check sum per word IS not used)
•
NULL
TC5334P-DDDD)
'MSB = D7')
N8.)
RDDDO.X7F5A
39E5)
RDD16.X108C
B241 "/
RDD32.X2DBA
38C7 )
R4064.X1 EC5
31 DE )
R4080.X4DA6 .
(CS,
R signifies an address.
Enter the address with the four decimal digits every sixteen words
after the character R.
X signifies a hexadecimal digit.
Enter the data of sixteen words continuously after the character X.
Otherwise specified In Format 1
1 BA4 )
= 1) )
(CS, = 0) )
$)
NULL
In additon, Toshiba can also accept programming and masking Information for TC5334P in the form of
punched paper tape with Intel BNPF format or master devices (EPROMs).
I
- 263-
~~~~~j]
1
~±O.215
2
3
4
5
8
7 8
8 10 "
1.4±O.15
O.5±O.15
12
r:::J
-B
I.
".----,,---\
(
for Memory Expansion
SYMBOL
VDD GND
VDD
A,
A9
eE2/ eE2
AI.
A.
Do
DI
D,
GND
• Programmable Chip Enable
CE/CE
• All Inputs and Outputs Directly TTL
Compatible
• Three State Outputs
• 24 Pin Standard Plastic Package
Au
- 273-
a:
8k xS
0-,
Note.
Tcshlba does not assume any responslbllltv for use of any Clrcultrv descnbed, no Circuit patent licenses are Implied, and Toshiba reserves
the right, at any time without notice, to change said CircUitry
©Apr., 1982 ToshIba Corporation
- 274-
MEMO
I
- 275-
MEMO
- 276-
MEMO
I
- 277-
MEMO
- 278-
I
- 279-
- 280-
CORPORATE OFFICE
2441 Michelle Drive
Tuston, CA 92680
(714) 730- 5000
TLX: 183812
EASTERN AREA
60 State St. - Ste. 405
Boston, MA 02109
(617) 742-2040
TWX' 710-321-6730
WESTERN AREA
1400 Quail St - Ste 100
Newport 8each, CA 92660
(714) 752-0373
TWX. 910-596-1886
CENTRAL AREA
1 Corporate Center
7505 Metro Blvd. - Ste. 370
Edona, MN 55435
(612) 831 -2566
TWX' 910-576-1321
The Information In thiS gUide has been carefully checked and IS believed to be reliable, however,
no responsibility can be assumed for maccuracles that may not have been caught All information In
thiS gUide IS subject to change Without prior notice Furthermore, Toshiba cannot assume responSibility
for the use of any !Icense under the patent rights of Toshiba or any third parties
TOSHIBA AMERICA. INC.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:07:29 09:17:14-08:00 Modify Date : 2013:07:29 09:21:42-07:00 Metadata Date : 2013:07:29 09:21:42-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:4d1fa49f-cab0-8c40-91a2-55f748282718 Instance ID : uuid:613e4a90-8e03-9549-b283-0e71f0c3703e Page Layout : SinglePage Page Mode : UseNone Page Count : 286EXIF Metadata provided by EXIF.tools