1983_84_Components_Data_Book 1983 84 Components Data Book
User Manual: 1983_84_Components_Data_Book
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31 4
!Data
ook
ilog
Pioneering the
Microworld
Copyright 1982, 1983 by Zilog, Inc. All rights reserved. No
part of this publication may be reproduced, stored in a
retrieval system, or transmitted, in any form or by any means,
electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Zilog.
The information contained herein is subject to change
without notice. Zilog assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Zilog product. No other circuit patent licenses are implied.
Microcomputers in Every Form
Zilog offers microprocessors in
every form: from components and
development systems to boardlevel products and complete
general-purpose microcomputer
systems. This edition of the Zilog
Data Book describes Zilog components, development systems,
and microcomputer boards. You'll
also find a section on the in-depth
training courses now offered for
most Zilog products.
Zilog components, the basic
building blocks for our other
microcomputer products, include
the 8-bit Z80® Microprocessor
and its family of intelligent
peripherals, the Z8™ Family of
Single-Chip Microcomputers, and
the 16-bit Z8000™ Microprocessor and its family of intelligent peripherals.
New produc~s introduced in
this data book are the Z800™
Family of Microprocessors, which
continues the Z80® tradition, and
the Z80,OOOTM Microprocessor,
which establishes Zilog's
supremacy in the 32-bit market.
Also new is the Z8070 APU
Arithmetic ProceSSing Unit for the
Z800, Z8000, and Z80,OOO
microprocessor families.
iii
Zilog offers a wide variety of .
development environments, ranging from the inexpensive Z8 and
Z8000 Development Modules to
the more elaborate EMS 8000
Development ·System.
Also offered are Models 11, 21,
and 31 of the System 8000 highperformance, time-sharing com·
puter system. In addition, EMS
8000 and Z-SCAN 8000 both provide in-circuit emulation for the
Z8000 Family of Microprocessors,
and Z-SCAN 800 provides incircuit emUlation for the Z800
Family.
Table of Conlenls
Z80 Family.....................................................................................
28400 CPU Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28410 DMA Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28420 PIO Parallel Input/Output Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
28430 CTC Counter/Timer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28440/1/2 SIO Serial Input/Output Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28470 DART Dual Asynchronous Receiver/Transmitter ............................................ :. . ..
3
5
27
45
59
71
87
Z80L Low Power Family
28300 CPU Central Processing Unit ................................................................. 101
28320 PIO Parallel Input/Output AC & DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 123
28330 CTC Counter/Timer Circuit AC & DC Characteristics ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127
28340 SIO Serial Input/Output AC & DC Characteristics ................................................ 131
Z8000 Family .............. , .................................................................... 137
2800112 CPU Central Processing Unit ........................... '.................................... 139
28003/4 Z-VMPU Virtual Memory Processing Unit ........................................... '" ....... 167
28010 2-MMU Memory Management Unit ................ , ...........................................
28015 PMMU Paged Memory Management Unit .................. " ...................................
28016 2-DTC Direct Memory Access Transfer Controller ...............................................
28030 2-SCC Serial Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28031 2-ASCC Asynchronous Serial Communications Controller .... "
28036 2-CIO Counter/Timer and Parallel I/O Unit ......... ~ .... .., .......................................
28038 2-FIO FIFO Input/Output Interface Unit ........................................................
28060 2-FIFO Buffer Unit and 2-FIO Expander ....................................... ~ ................
28065 2-BEP Burst Error Processor ..................................................................
28068 2-DCP Data Ciphering Processor ..............................................................
28070 APU Arithmetic Processing Unit (see Z?O,OOO section)
28090/4 and 28590/4 2-UPC/UPC Universal Peripheral Controllers
(see 28 section)
.j'• • • • • • • • • • "
••••••••• :
••••••••••••
199
215
235
267
289
309
335
367
375
389
Universal Peripherals ............ " ......................... '............................ ~ . . . . . . . .. 407
28090/4 and 28590/4 2-UPC/UPC Universal Peripheral Controllers
(see 28 section)
28038 2-FIO FIFO Input/Output Interface Unit (see 28000 section)
28060 FIFO Buffer Unit and 2-FIO Expander (see 28000 section)
28530 SCC Serial Communications Controller ........................................................
28531 ASCC Asynchronous Serial Communications Controller ..........................................
28536 CIO Counter/Timer and Parallel I/O Unit ......................................................
28581 CGC Clock Generator and Controller .........................................................
409
431
451
475
Z8 Family .... .'............ " ................................. " .... '............................. 485
28601l28603/28601L MCU Microcomputer ...........................................................
28611/2/3 MCU Microcomputer ............ '........................................................
28671 MCU Microcomputer with BASIC/Debug Interpreter ....................................... , .....
2868112 ROMless Microcomputer ...................................................................
28090/4 and 28590/4 2-UPC/UPC Universal Peripheral Controllers ......................................
487
505
523
543
563
Z800 Family .................................................................................... 589
2800 MPU Family .... , ..... " ................................ ; ........... " ....................... 591
Z80.000 Family . ................................................................................. 663
28070 APU Arithmetic Processing Unit .............................................................. 665
280000 CPU Central Processing Unit ................................................................ 691
v
'",
Table of Conlents (Continued)
Additional Information
Zilog Z-BUS Component Interconnect ............. ; .................................................. 741
Z-BUS Backplane Interconnect ..................................... ; ................................ 759
High Reliability Microcircuits ........................... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 763
Packaging Information
Package Summary ................................. '..............................................
18-Pin Packages .................................................................................
28-Pin Packages ............................ ; ....................................................
40-Pin Packages ......................................... ; .......................................
48-Pin Packages ............................................................. '.' ..................
64-Pin Packages .................................................................................
28-,44-, 52-, and 68-Pin LeadlessPackages ..........................................................
Leadless Chip Carriers (Pin Assignments) ...........................................................
769
770
771
772
774
775
776
779
Zilog Development Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual-Processor Upgrade Package ............................................................... ; ..
EMS 8000 Emulator Subsystem ................. '....................................................
28000 Development Module .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8 Development Module ................................. ".........................................
2-SCAN UPC Development Module ..... , ... ~ ... , ........... , ............ '" ...................... "
Z-SCAN 8 ..................................... " ................................ " ............ , ..
Z-SCAN 800 . : ...................................................................................
Z-SCAN 8000 ... , ................................................................................
System 8000, Models 21 & 31 .......................................................................
System 8000, Model 11 ...................................................................... ;.....
787
789
791
795
799
803
805
811
815
819
823
Zilog Software Development Products ............................ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z8000 PLZlSYS Compiler ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28070 Floating-Point Software Emulation Package .....................................................
2RTS 2ilog Real-Time Software ................... ~ .................................................
Z80 PL2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2800 Cross'-Software Package ........ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Software Development Product ..................................................................
827
829
831
839
843
845
849
vi
FunctloKUan Hndex
Single-Chip Microcomputers
28090
28094
28590
28594
28601
28601L
2800 2-UPC Universal Peripheral Controller ............................................... ,.
28000 2~UPC Universal Peripheral Controller with External RAM ................................
UPC Universal Peripheral Controller .......................................................
UPC Universal Peripheral Controller with External RAM, Protopack .............................
28 8-Bit Single-Chip Microcomputer with 2K ROM ............................................
28 8-Bit, Low-Power, Single-Chip Microcomputer with Memory
Interface, 64-Pin, 4K External ROM .........................................................
28 Prototyping Device with EPROM Interface, 64-Pin, 2K External ROM .' .........................
28 8-Bit Single-Chip Microcomputer with Memory Interface, 64-Pin, 4K External ROM ..............
28 8-Bit Microcomputer with Memory Interface, 64-Pin, 4K External ROM .........................
28 Prototyping Device with EPROM Interface, Protopack, 4K External ROM .......................
28 8-Bit Single-Chip BASIC/Debug Interpreter ...............................................
288-Bit, Single-Chip Microcomputer with No On-Chip ROM ............... '.....................
487
487
505
505
505
523
543
a-Bit Microprocessors
28300
280L Low-Power 280 Central Processing Unit .................................................
28320
280L PIO Low-Power Parallel Inpu~Output Controller .........................................
280L CTC Low-Power Counter/Timer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28330
28340
280L SIO Low-Power Serial Input/Output Controller ...........................................
280 CPU Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28400
28410
280 DMA Dual-Port Direct Memory Access Controller. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . ..
28420
280 PIO Dual-Port Parallel Input/Output Controller ................................ , . . . . . . . . ..
280 CTC Four-Channel Counter/Timer Circuit .............................................. ,
28430
280 SIO/O Dual-Channel Synchronous/Asychronous Serial Input/Output Controller ........... : . . ..
28440
28441
280 SIO/1 Dual-Channel Synchronous/Asychronous Serial Input/Output Controller. . . . . . . . . . . . . . ..
28442
280 SIO/2 Dual-Channel Synchronous/Asynchronous Serial Input/Output Controller .... '.' . . . . . . . ..
28470
280 DART Dual-Channel Asynchronous Receiver/Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28108
2800 MPU Microprocessing Unit ...........................................................
28208
2800 MPU Microprocessing Unit ...........................................................
101
123
127
131
5
27
45
49
71
71
71
87
591
591
28603
28611
28612
28613
28671
28681
563
563
563
563
487
IS-Bit Microprocessors
28001
28002
28003
28004
28010
28015
28016
28030
28031
28036
28038
28060
28065
28068
28070
28090
28094
28116
28216
2ilog 2-BUS Component Interconnect .......................................................
2-BUS Backplane Interconnect ..............................................................
16~Bit Segmented Central Processing Unit .............................................. , ....
16-Bit Nonsegmented Central Processing Unit ................................................
28000 2-VMPU Virtual Memory Processing Unit ...............................................
280002-VMPU Virtual Memory Processing Unit .................... '.' .........................
28000 2-MMU Memory Management Unit ....................................................
28000 PMMU Paged Memory Management Unit .............................. ; ................
28000 2-DTC Direct Memory Access Transfer Controller .......................................
28000 2-SCC Serial Communications Controller ................ ; .............................
28000 2-ASCC Asynchronous Serial Communications Controller ................................
28000 2-CIO Counter/Timer and Parallel I/O Unit .............................................
28000 2-FIO FIFO Input/Output Interface Unit ................................................
28000 2-FIFO Buffer Unit and 2-FIO Expander .................................... , ...........
28000 2-BEP Burst Error Processor ..........................................................
28000 2-DCP Data Ciphering Processor ......................................................
28000 APU Arithmetic Processing Unit ......................................... ~ ............
28000 2-UPC Universal Peripheral Controller ................................................
28000 2- UPC Universal Peripheral Controller with External RAM ................................
2800 MPU Microprocessing Unit ...........................................................
2800 MPU Microprocessing Unit ..................... : ................. '. . . . . . . . . . . . . . . . . . . .
vii
741
759
139
139
167
167
199
215
235
267
289
309
335
367
375
389
665
563
563
591
591
Funclionallndex (Continued)
~
•
',.
•
j
•
.",'.
~.'
,
l
.... •
•
"
\
.... ' • ..,.. wi
r'''-
32-Bit Microprocessors
Z8070
APU Arithmetic Processing Unit ............................................................ 665
Z80,OOO Z80,OOO CPU Central Processing Unit ....................................................... 691
Microprocessor Peripherals
Serial Communications Controllers
Z8030
Z8000 Z-SCC Serial Communications Controller ..............................................
Z8031
Z8000 Z-ASCC Asynchronous Serial Communications Controller ................................
Z8440 'Z80 SIO/O Dual-Channel Synchronous/Asychronous Serial InpuVOutput Controller. . . . . . . . . . . . . . ..
Z8441
Z80 SIO/l Dual-Channel Synchronous/Asychronous Serial InpuVOutput Controller. . . . . . . . . . . . . . ..
Z8442
Z80 SIO/2 Dual-Channel Synchronous/Asychronous Serial InpuVOutput Controller. . . . . . . . . . . . . . ..
Z8470
Z80 DART Dual-Channel Asynchronous Receiver/Transmitter. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ..
Z8530
SCC Serial Communications Control fer ............... ~ .....................................
Z8531
ASCC Asynchronous Serial Communications Controller .......................................
267
289
71
71
71
87
409
431
Parallel
Z8036
Z8038
Z8060
Z8536
309
335
367
451
I/O and Counter/Timers
Z8000 Z-CIO Counter/Timer and Parallel I/O Unit .. ! • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Z8000 Z-FIO FIFO InpuVOutput Interface Unit ........................ ~ .......................
Z8000 Z-FIFO Buffer Unit and Z-FIO Expander ................................................
CIO Counter/Timer and Parallel I/O Unit ....................................................
Clock Products
Z8581
CGC Clock Generator and Controller ...................................................... 475
Universal Peripheral Controllers
Z8090
Z8000 Z-UPC Universal Peripheral Controller ................................................
Z8094
Z8000 Z-UPC Universal Peripheral Controller with External RAM ................................
Z8590
UPC Universal Peripheral Controller ....................... , ...............................
'Z8594
UPC Universal Peripheral Controller with External RAM .......................... '.............
563,
563
563
563
Development Products
Dual-Processor Upgrade Package for Z80 Systems ..................................................... 789
EMS 8000 In-Circuit Emulator Subsyst~m ............................................................. 791
Z8 Development Module, 2K Prototyping and Evaluation Board .............. ' ............................ 799
Z8 Development Module, 4K Prototyping and Evaluation Board .......................................... 799
Z8001 Development Module, Prototyping and Evaluation Board .......................................... 795
Z8002 Development Module, Prototyping and Evaluation Board .......................................... 795
Z-SCAN UPC Development Module ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Z-SCAN 8 In-Circuit Emulator ...... -............................................................... 805
Z~SCAN 800 In-Circuit Emulator ................................. ~ ................................. 811
Z-SCAN 8000 In-Circuit Emulator .................................................................. 815
System 8000 Multiuser Development System, Model 11 .............. ; .................................. 823
System 8000 Multiuser Development System, Model 21 ............................................. '.... 819
System 8000 Multius~r Development System, Model 31 ................................................. 819
Software Development Products
Z8000 PLZlSYS Compiler for user with PDS 8000/05, PDS 8000115, and ZDS-l Series ....................... ~
Z8070 Floating-Point Unit Software Emulation Package .................................................
ZRTS Z8000 Real-Time, Multitasking Software Tools ...................................................
Z80 ptz Compiler for the Z80 . . . . . . . . .. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ..
Z800 Cross-Software Package .... ,' .................................................................
Z8 Software Development Package, Cross-Assemblerfor user with PDS 80001120A ..........................
viii
829
831
839
843
845
849
Part Number
05-0103-00
05-0122-00
05-0207-00
05-1044-00
05-6101-01
05-6158-01
05-6168-01
05-6219-00
05-6222-01
05-8011-00
05-8021-00
05-8031-00
07-0086-01
07-3301-01
07-3302-01
07-3363-01
28000
28001
28002
28003
28004
28010
28015
28016
28030
28031
28036
28038
28060
28065
28068
28070
28090
28094
28108
28116
28208
28216
28300
28320
28330
28340
28400
Description
2800 Cross-Software Package .........................................................
280 PL2 Compiler for the 280 .................................. , . . . . . . . . . . . . . . . . . . . . . ..
2-SCAN 2800 In-Circuit Emulator ......................................................
2-SCAN 8000 In-Circuit Emulator ......................................................
EMS 8000 In-Circuit Emulator Subsystem ...............................................
2-SCAN UPC Development Module ........................ '............................
2-SCAN 8 In-Circuit Emulator .........................................................
28002 Development Module ............ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28 Development Module, 2K Prototyping and Evaluation Board .............................
28001 Development Module ...........................................................
Dual-Processor Upgrade Package for 280 Systems ........................................
28 Development Module, 4K Prototyping and Evaluation Board .............................
System 8000 Multiuser Development System, Model 11 ....................................
System 8000 Multiuser Development System, Model 21 ....................................
System 8000 Multiuser Development System, Model 31 ....................................
28 Software Development Package, Cross-Assembler for use with PDS 8000/20A ...............
28000 PLZlSYS Compiler for use with PDS 8000/05 and PDS 8000/15 .........................
28000 PLZlSYS Compilerfor use with 2DS-l Series . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28 Software Development Package, Cross-Assembler for use with PDS 8000/20 and PDS 8000/30 .
28070 Floating-Point Unit Software Emulation Package ................................... ,
2RTS 28000 Real-Time, Multitasking Software Tools .......................................
16-Bit, Segmented Central Processing Unit ..............................................
16-Bit, Nonsegmented Central Processing Unit .... ; ..................................... ,
28000 2-VMPU Virtual Memory Processing Unit ..........................................
28000 2-VMPU Virtual Memory Processing Unit ............... " .........................
28000 2-MMU Memory Management Unit .................. " ...........................
28000 PMMU Paged Memory Management Unit ..........................................
28000 2-DTC Direct Memory Access Transfer Controller ...................................
28000 2-SCC Serial Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..
28000 2-ASCC Asynchronous Serial Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . ..
28000 2-CIO Counter/Timer and Parallel I/O Unit ........................................
28000 2-FIO FIFO InpuVOutput Interface Unit ...........................................
28000 2-FIFO Buffer Unit and 2-FIO Expander ...........................................
28000 2-BEP Burst Error Processor .....................................................
28000 2-DCP Data Ciphering Processor ............................. '....................
APU Arithmetic Processing Unit .......................................................
28000 2-UPC Universal Peripheral Controller ............................................
28000 2-UPC Universal Peripheral Controller, External RAM-Based .........................
2800 MPU Microprocessing Unit
2800 MPU Microprocessing 'Unit
2800 MPU Microprocessing Uni t
2800 MPU Microprocessing Unit
280L CPU Low-Power 280 Central Processing Unit ........................................
280L PIO Low-Power Parallel InpuVOutput Controller ................................. ; ..
280L CTC Low-Power Counter/Timer Circuit ........................................... ,
280L SIO Low-Power Serial InpuVOutput Controller ......................................
280 CPU Central Processing Unit .............................. .' . . . . . . . . . . . . . . . . . . . . .. .
ix
845
843
811
815
791
803
805
795
799
795
789
799
823
819
819
849
829
829
849
831
839
139
139
199
199
199
215
235
267
289
309
335
367
375
389
665
563
563
101
123
127
131
5
Pari Number ladex (Continued)
Part Number
Z8410
Z8420
Z8430
Z8440
Z8441
Z8442
Z8470
Z8530·
Z8531
Z8536
Z8581
Z8590
Z8594
Z8601
Z8601L
Z8603
Z8611
Z8612
Z8613
Z8671
Z8681
Z8682
Z80,000
Descrlptlon
Z80 DMA Dual-Port, Direct Memory Access Controller ............ ~ . . . . . . . . . . . . . . . . . . . . . ..
Z80 PIO Dual-Port, Parallel Input/Output Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 CTC Four-Channel Counter/Timer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 SIO/O Dual-Channel Synchronous/Asynchronous Serial I/O Controller ............ ~ . . . . ..
Z80 SIO/1 Dual-Channel Synchronous/Asynchronous Serial I/O Controller ... . . . . . . . . . . . . .. ..
Z80 SIO/2 Dual-Channel Synchronous/Asynchrorious Serial I/O Controller. . . . . . . . . . . . . . . . . ..
Z80 DART Dual-Channel Asynchronous Receiver/Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SCC Serial Communications Controller .................................................
ASCC Asynchronous Serial Communications Controller ..................................
CIO Counter/Timer and Parallel I/O Unit ......' .........................................
CGC Clock Generator and Controller ..................................................
UPC Universal Peripheral Controller ................................................. ,.
UPC Universal Peripheral Controller with External RAM, Protopack .........................
Z8 8-Bit, Single-Chip Microcomputer with 2K ROM .......................................
Z8 8-Bit Low-Power, Single-Chip Microcomputer .........................................
Z8 Prototyping Device with EPROM Interface, 64-Pin, 2K External ROM ......................
Z8 8-Bit, Single-Chip Microcomputer with Memory Interface, 64-Pin, 4K External ROM .........
Z8 8-Bit Microcomputerwith Memory Interface, 64-Pin, 4K External ROM ....................
Z8 Prototyping Device with EPROM Interfape, Protopack, 4K External ROM ...................
Z8 8-Bit, Single-Chip BASIC/Debug Interpreter ..........................................
Z8 8-Bit, Single-Chip Microcomputer with No On-Chip ROM ...............................
Z8 8-Bit, Single-Chip Microcomputer with No On-Chip ROM ...............................
Z80,000 CPU Central Processing Unit ..................................................
• AI185XX components are compatible with processors other than Zilog's Z8oo1, Z8oo2, Z8oo3,
and zs004. For further Information refer to the Individual product specifications.
x
,
27
45
59
71
71
71
87
409
431
451
475
563
563
487
487
487
505
505
505
523
543
543
691
rEJ@(ffiO
~(£)\W
Pioneering the
Microworld
&H!iii¥
~efts fthe llImcdluslry
~namlCdlalld1 {lor 8 Bils
September 1983
Zilog remains an industry
leader, thanks to continuing innovation in microcomputer concepts and integrated design as
exemplified in the Z80 Family
microcomputer products.
At Zilog, innovation means
using proven, sophisticated mainframe and minicomputer concepts and translating them into
the latest LSI technologies. Integration means more than
designing an ever-greater number
of functions onto
a single chip. Zilog integrates
technologies-LSI design
enhanced by advances in
computer-based system architecture and system design
technologies.
Zilog offers microprocessor
solutions to computing problems:
from components and development systems to OEM board-level
products and general-purpose
microcomputer systems.
This guide to the Z80 Family of
state-of-the-art microprocessors
and intelligent peripheral controllers demonstrates Zilog's continued support for the Z80
microprocessor and the other
members of the Z80 product
family-a family first introduced
in 1976 that continues to enjoy
growing customer support while
family chips are upgraded to
newer and ever-higher standards.
The Za400 zao CPU Central
Processing Unit rapidly
established itself as the most
sophisticated, most powerful, and
most versatile 8-bit
microprocessor in the world. It
offers many more features and
functions than its competitor.
In addition to being sourcecode compatible with the 8080A
microprocessor, the Z80 offers
more instructions than the.8080A
(158 vs. 78) and numerous other
features that simplify hardware
requirements and reduce programming effort while increasing
throughput. The dual-register set
of the Z80 CPU allows high-speed
context switching and more efficient interrupt processing. Two
index registers give additional
memory-addressing flexibility and
simplify the task of programming.
Interfacing to dynamic memory is
simplified by on-chip, programmable refresh logic. ~Iock moves
plus string- and bit-manipulation
instructions reduce programming
effort, program size, and execution time.
The new Z80l low·Power
Family widens the. range of
possible Z80 applications. Products in this family retain all the
functions of the standard components while providing dramatic
power savings and increased
reliability. Available now in low. power versions are the Z80 CPU,
Z80 CTC, Z80 Pia, and Z80 SIO.
The four traditional functions of
a microcomputer system (parallel
I/O, serial I/O, counting/timing,
and direct memory access) are
easily implemented by the Z80
CPU and the following wellproven family of Z80 peripheral
devices: Z80 Pia, Z80 SIO, Z80
DART, Z80 CTC, and Z80 DMA.
3
The easily programmed, dualchannel Za420 zao PIO Parallel
Input/Output Controller offers
two 8-bit I/O ports with individual
. handshake and pattern recognition logic. Both I/O ports operate
in either a byte or a bit mode. In
addition, this device can be programmed to generate interrupts
for various status conditions.
All common data communications protocols, asynchronous
as well as synchronous, are
remarkably well handled by the
Za440 zao 510 Serial Input/Out·
put Controller. This dual-channel
4
receiver/transmitter device offers
on-chip parity and CRC generation/checking. FIFO buffering and
flag- and frame-detection generation logic are also offered.
If asynchronous-only applications are required, the costeffective Za470 zao DART Dual
Asynchronous Receiverl
Transmitter can be used in place
of the Z80 SID. The Z80 DART
offers all Z80 SID asynchronous
features in two channels.
Timing and event-counting
functions are the forte of the
Za430 zao CTC Counter/Timer
Controller. The CTC provides
four counters, each with individually programmable
prescalers. The CTC is a convenient source of programmable
clock rates for the SID .
With the Za410 zao DMA
Direct Memory Access Con·
troller, data can be transferred
directly between any two ports
(typically, I/O and memory). The
DMA transfers, searches, or
search/transfers date in. Byte-byByte, Burst, or Continuous modes.
This device can achieve an impressive 2M bits per second data
rate in the Search mode.
Z8400
Z80®CPU Central
Processing Unit
Product
Specification
Zilog
September 1983
Features
• The instruction set contains 158 instructions.
The 78 instructions of the 8080A are
included as a subset; 8080A software compatibility is maintained.
• Eight MHz, 6 MHz, 4 MHz and 2.5 MHz
clocks for the Z80H, Z80B, Z80A, and Z80
CPU result in rapid instruction execution
with consequent high data throughput.
11 The extensive instruction set includes string,
bit, byte, and word operations. Block
searches and block transfers together with
indexed and relative addreSSing result in
the most powerful data handling capabilities
in the microcomputer industry.
II
The Z80 microprocessors and associated
family of peripheral controllers are linked
by a vectored interrupt system. This system
M1
may be daisy-chained to allow implementation of a priority interrupt scheme. Little, if
any, additional logic is required for daisychaining.
II
Duplicate sets of both general-purpose and
flag registers are provided, easing the
design and operation of system software
through single-context switching, background-foreground programming, and
single-level interrupt processing. In addition, two 16-bit index registers facilitate program processing of tables and arrays.
III There are three modes of high-speed inter-
rupt processing: 8080 similar, non-Z80
peripheral device, and Z80 Family
peripheral with or without daisy chain.
• On-chip dynamic memory refresh counter.
~
Al
SYSTEM
CONTROL
1
MREO
A2
IORO
A3
RO
A4
WR
As
All
Al0
Ar,
A12
Ag
A7
Ar,
Ag
CONTROL
CPU
1
All
Z 80 CPU
ADDRESS
BUS
A13
A8
Au
A7
AIS
As
ClK
As
04
A4
03
A3
Os
A2
Os
Al
+5V
02
CPU {
BUS
CONTROL
07
RFSH
00
M1
01
2001-0210,0211
RESET
iNr
BUSREO
NMI
WAIT
HALT
BUSACK
MREO
WR
AD
IORO
Figure 1. Pin Functions
~
GNO
Figure 2. Pin Assignments
5
General
Description
The Z80, Z80A, 280B, and Z80H CPUs are
third-generation single-chip microprocessors
with exceptional computational power. They
offer higher system throughput and more efficient memory utilization than comparable
second-and third-generation microprocessors.
The internal registers contain 208 bits of
read/write memory that are accessible to the
programmer. These registers include two sets
of six general-purpose registers which may be
used individually as either 8-bit registers or as
16-bit register pairs. In addition, there are two
sets of accumulator and flag registers. A group
of "Exchange" instructions makes either set of
main or alternate registers accessible to the
programm'er. The alternate set allows operation
in foreground-background mode or it may be
reserved for very fast interrupt response.
The Z80 also contains a Stack POinter, Program Counter, two index registers, a Refresh
register (counter), and an Interrupt register.
The CPU is easy to incorporate into a system
since it requires only a single + 5 V power
source. All output signals are fully decoded
and timed to control standard memory or
peripheral Circuits, and it is supported by an
extensive family of peripheral controllers. The
internal block diagram (Figure 3) shows the
primary functions of the Z80 processors.
Subsequent text provides more detail on the
Z80 I/O controller family, registers, instruction
set, interrupts and daisy chaining, and CPU
timing.
+5V -+-
GND -+CLOCK ....
Figure 3.
6
zao CPU Block Diagram
2001-0212
Z8D Microprocessor
Family
each of which has an 8-bit prescaler. Each
of the four channels may be configured to
operate in either counter or timer mode.
The Zilog Z80 microprocessor is the central
element of a comprehensive microprocessor
product family. This family works together in
most applications with minimum requirements
for additional logic, facilitating the design of
efficient and cost-effective microcomputerbased systems.
Zilog has designed five components to provide extensive support for the Z80 microprocessor. These are:
CJ The DMA (Direct Memory Access) con-
troller provides dual port data transfer
operations and the ability to terminate data
transfer as a result of a pattern match.
IJ
EJ The PIO (Parallel Input/Output) operates in
both data-byte I/O transfer mode (with
handshaking) and in bit mode (without
handshaking). The PIO may be configured
to interface with standard parallel
peripheral devices such a.s printers, tape
punches, and keyboards.
lJ
Z8D CPU
Registers
The SIO (Serial Input/Output) controller
offers two channels. It is capable of
operating in a variety of programmable
modes for both synchronous and asynchronous communication, including
Bi-Sync and SDLC.
[] The DART (Dual Asynchronous Receiver/
Transmitter) device provides low cost
asynchronous serial communication. It has
two channels and a full modem control
interface.
The CTC (Counter/Timer Circuit) features
four programmable 8-bit counter/timers,
Figure 4 shows three groups of registers
within the Z80 CPU. The first group consists of
duplicate sets of 8-bit registers: a prinCipal set
and an alternate set (designated by I [primEd,
e.g., A'). Both sets consist of the Accumulator Register, the Flag Register, and six
general-purpose registers. Transfer of data
between these duplicate sets of registers is
accomplished by use of "Exchange" instructions. The result is faster response to interrupts
and easy, efficient implementation of such versatile programming techniques as background-
foreground data processing. The second set of
registers consists of six registers with assigned
functions. These are ·the I (Interrupt Register),
the R (Refresh Register), the IX and IY (Index
Registers), the SP (Stack Pointer), and the PC
(Program Counter). The third group consists of
two interrupt status flip-flops, plus an additional pair of flip-flops which assists in identifying the interrupt mode at any particular
time. Table 1 provides further information on
these registers.
ALTERNATE REGISTER SET
MAIN REGISTER SET
A
ACCUMULATOR
F
FLAG REGISTER
A'
ACCUMULATOR
F'
FLAG REGISTER
B
GENERAL PURPOSE
C
GENERAL PURPOSE
B'
GENERAL PURPOSE
C'
GENERAL PURPOSE
0
GENERAL PURPOSE
E
GENERAL PURPOSE
0'
GENERAL PURPOSE
E'
GENERAL PURPOSE
H
GENERAL PURPOSE
L
GENERAL PURPOSE
H'
GENERAL PURPOSE
L'
GENERAL PURPOSE
_SBITS---.
_ - - - - - - - 1 6 BITS - - - - - - - _
INTERRUPT
FLlP·FLOPS
B
IX INDEX REGISTER
~~ :
4
IY INDEX REGISTER
STATUS
G---.
INTERRUPTS DISABLED
STORES IFF1
INTERRUPTS ENABLED
DURING NMI
SERVICE
SP STACK POINTER
INTERRUPT MODE FLlp·FLOPS
PC PROGRAM COUNTER
I INTERRUPT VECTOR
I
IMFa
R MEMORY REFRESH
_SBITS---.
IMFb
INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2
Figure 4. CPU Registers
2001·0213
7
zaD CPU
Registers
(Continued)
Register
A, A'
F, F'
Accumulator
. Flags
Size (Bits)
Remarks
8
Stores an operand or the results of an operation.
8
See Instruction Set.
Can be used separately or as a 16-bit register with C.
B, B'
General Purpose
8
C, C'
General Purpose
8
See B, above.
D, D'
General Purpose
8
Can be used separately or as a 16-bit register with E.
E, E'
General Purpose
8
See D, above.
H, H'
General Purpose
8
Can be used separately or as a 16-bit register with L.
L, L'
General Purpose
8
See H, above.
Note: The (B,C), (D,E),
B - High byte C D - High byte E H - High byte L -
Interrupt Register
8
Stores upper eight bits of memory address for vectored interrupt
processing.
R
Refresh Register
8
Provides user-transparent dynamic memory refresh. Lower seven
bits are automatically incremented and all eight are placed on
the address bus during each instruction fetch cycle refresh time;
IX
Index Register
16
Used for indexed addressing.
IY
Index Register
16
Same as IX, above.
SP
Stack Pointer
16
Holds address of the top of the stack. See Push or Pop in instruction set.
PC
Program Counter
16
IFF 1-IFF2
Interrupt Enable
Flip-Flops
Set or reset to £ndicate inte'rrupt status (see Figure 4).
Holds address of next instruction.
IMFa-IMFb
Interrupt Mode
Flip-Flops
Reflect Interrupt mode (see Figure 4).
Table 1.
Interrupts:
General
Operation
zao CPU Registers
The CPU accepts two interrupt input signals:
NMI and INT. The NMI is a non-maskable
interrupt and has the highest priority. INT is a
lower priority interrupt and it.requires that
interrupts be enabled in software in order to
operate. INT can be connected to multiple
peripheral devices in a wired-OR configuration.
The Z80 has a single response mode for
interrupt service for the non-maskable interrupt. The maskable interrupt, INT, has three
programmable response modes available.
These are:
!II
8
and (H,L) sets are combined as follows:
Low byte
Low byte
Low byte
Mode a - similar to the 8080 microprocessor.
II Mode 1 -
Peripheral Interrupt service, for
use with non-8080/Z80 systems.
• Mode 2 - a vectored interrupt scheme,
usually daisy-chained, for use with Z80
Family and compatible peripheral devices.
The CPU services interrupts by sampling the
NMI and INT signals at the rising edge of the
last clock of an instruction. Further interrupt
service processing depends upon the type of
interrupt that was detected. Details on interrupt responses are shown in the CPU Timing
Section.
Interrupts:
General
Operation
(Continued)
Non-Maskable Interrupt (NMI). The nonmaskable interrupt cannot be disabled by program control and therefore will be accepted at
all times by the CPU. NMI is usually
reserved for servicing only the highest priority
type interrupts, such as that for orderly shutdown after power failure has been detected.
After recognifion of the NMI signal (providing
BUSREQ is not active), the CPU jumps to
restart location 0066H. Normally, software
starting at this address contains the interrupt
service routing.
Maskable Interrupt (INT). Regardless of the
interrupt mode set by the user, the 280
response to a maskable interrupt input follows
a common timing cycle. After the interrupt has
been detected by the CPU (provided that
interrupts are enabled and BUSREQ is not
active) a special interrupt processing cycle
begins. This is a special fetch (MI) cycle in
which IORQ becomes active rather than
MREQ, as in normal MI cycle. In addition, this
special MI cycle is automatically extended by
two WAIT states, to allow for the time required
to acknowledge the interrupt request.
Mode 0 Interrupt Operation. This mode is
similar to the 8080 microprocessor interrupt
service procedures. The interrupting device
places an instruction on the data bus. This is
normally a Restart instruction, which will initiate a call to the selected one of eight restart
locations in page zero of memory. Unlike the
8080, the 280 CPU responds to the Call instruction with only one interrupt acknowledge
cycle followed by two memory read cycles.
Mode I Interrupt Operation. Mode 1 operation is very similar to that for the NMI. The
principal difference is that the Mode I interrupt has a restart location of 0038H only.
Mode 2 Interrupt Operation. This interrupt
mode has been designed to utilize most effectively the capabilities of the 280 microprocessor and its associated peripheral family. The
interrupting peripheral device selects the
starting address of the interrupt service
routine. It does this by placing an 8-bit vector
on the data bus during the interrupt acknowledge cycle. The CPU forms a pointer using
this byte as the lower 8-bits and the contents of
the I register as the upper 8-bits. This points to
an entry in a table of addresses for interrupt
service routines. The CPU then jumps to the
routine at that address. This flexibility in
selecting the interrupt service routine address
allows the peripheral device to use several different types of service routines. These routines
may be located at any available location in
memory. Since the interrupting device supplies the low-order byte of the 2-byte vector,
bit 0 (Ao) must be a zero.
Interrupt Priority (Daisy Chaining and
Nested Interrupts). The interrupt priority of
each peripheral device is determined by its
physical location within a daisy-chain configuration. Each device in the chain has an interrupt enable input line (IEI) and an interrupt
enable output line (lEO), which is fed to the
next lower priority device. The first device in
the daisy chain has its IEI input hardwired to a
High level. The first device has highest
priority, while each succeeding device hasa
corresponding lower priority. This arrangement permits the CPU to select the highest
priority interrupt from several simultaneously
interrupting peripherals.
The interrupting device disables its IEO line
to the next lower priority peripheral until it has
been serviced. After servicing, its IEO line is
raised, allowing lower priority peripherals to
demand interrupt servicing.
The 280 CPU will nest (queue) any pending
interrupts or interrupts received while a
selected peripheral is being serviced.
Interrupt Enable/Disable Operation. Two
flip-flops, IFFI and 1FF2, referred to in the
register description are used to signal the CPU
interrupt status. Operation of the two flip-flops
is described in Table 2. For more details, refer
to the Z80 CPU Technical Manual and Z80
Assembly Language Manual.
IFFl
IFF2
Comments
CPU Reset
o
o
Maskable int~rrupt
INT disabled
DI instruction
execution
o
o
Maskable interrupt
INT disabled
Action
EI instruction
execution
Maskable interrupt
INT enabled
LD A,I instruction
execution
IFF2 - Parity flag
LD A,R instruction
execution
IFF2 - Parity flag
Accept NMI
RETN instruction
execution
o
IFF2
IFFl
IFFl - IFF2
(Maskable interrupt INT disabled)
IFF2 - IFF} at
completion of an
NMI service
routine.
Table 2. State of Flip-Flops
9
Instruction
Set
o
o
o
o
o
8-Bit
Load
Group
o
o
o
o
o
o
The Z80 microprocessor has one of the most
powerful and versatile instruction sets
available in any 8-bit microprocessor. It
includes such unique operations as a block
move for fast, efficient data transfers within
memory or between memory and I/O. It also
allows operations on any bit in any location in
memory.
The folloWing is a summary of the Z80
instruction set and shows the assembly
language mnemonic, the operation, the flag
status, and gives comments on each instruction. The Z80 CPU Technical Manual
(03-0029-01) and Assembly Language
Programming Manual (03-0002-01) contain
significantly more details for programming
use.
The instructions are divided into the
following categories:
o
o
o
Extended
Indexed
o Register
General-purpose arithmetic and CPU
control
LD r, r'
LD r, n
r - r'
LD r, (HL)
LD r, (IX+d)
r r -
(HL)
(IX+d)
LD r, (IY +d)
r -
(IY +d)
LD (HL). r
LD (IX + d). r
(HL) - r
(IX+d) - r
LD (IY +d). r
(IY+d) - r
LD (HL). n
(HL) - n
LD (IX+d). n
(IX+d) -'n
LD (IY +d). n
(IY+d) - n
X
X
X
X
· ·
·· ··
X
X
X
X
X
· ·
Opcode
No.ol No.ol M No.ol T
76 5'3 210 Hex Byte. Cycles State.
II 011 101
01 r 101
-dII III 101
01 r 110
-dOl 110 r
II 011 101
01 110 r
-dII III 101
01 110 r
-d00 110 110
· ·
. · ·
· ·
X
Bit
X
. ·· ·
DD
7
19
FD
19
II III 101
00 110 110
-d-
FD
19
X
X
X
00 001 010
00 011 010
00 III 010
OA
IA
3A
7
7
13
00 000 010
00 010 010
00 110 010
02
12
32
7
7
13
010
011
100
101
III
D
E
H
L
A
-n-
-n-
A - (BC)
A - (DE)
A - (nn)
X
X
X
LD (BC). A
LD (DE). A
LD (nn). A
(BC) - A
(DE) - A
(nn) - A
X
X
X
·· ·
A - I
X
X IFF
0
0
·
19
19
X
·
FD
10
II 011 101
00 110 110
-d-
·
··
7
19
36
X
X
X
DD
DD
36
X
X
Comment.
~
000
B
001
C
r'
r
r 110
-n01 r 110
X
X
X
C
Register indirect
Ifl!.plied
01
00
X
X
LD A, (BC)
LD A, (DE)
LD A, (nn)
LDA, I
Immediate extended
o
o
o
8-bit arithmetic and logic operations
Flags
H
P/V N
Input and output operations
o Relative
Exchanges, block transfers, and searches
Z
Calls, returns, and restarts
Modified page zero
o
16-bit loads
S
Bit set, reset, and test operations
Jumps
Immediate
'0
Symbolic
Operation
Rotates and shifts
A variety of addreSSing modes are
implemented to permit efficient and fast data
transfer between various registers, memory
locations, and input/output devices. These
addressing modes include:
8-bit loads
Mnemonic
16-bit arithmetic operations
36
-n-
X
X
X
-n-
LDA, R
A-R
X
0
X IFF
LD I, A
I - A
X
LDR, A
·
X
R-A
X
· ·
X
II
01
II
01
II
01
II
01
101
010
101
011
101
000
101
001
101
III
101
III
101
III
101
III
ED
57
ED
5F
ED
47
ED
4F
NOTES: r, r' means any of the regJSters A, E, C, D, E, H, L.
IFF the content of the interrupt enable flip, flop, (IFF) is
copied into the PlY flag,
For dn explanation of !lag notation and symbols for
mnemonic tables, see Symbolic Notation section
following tables,
10
2001-001
IS-Bit Load
Group
Mnemonic
Flag.
H
P/V N
Z
C
No.of No.of M No.of T
76 543 210 Hex Byte. Cycle. State.
dd - nn
X
X
00 ddO 001
10
LD IX, nn
IX - nn
X
X
-n11 011 101 DD
00 100 001 21
14
LD IY, nn
IY - nn
X
X
LD HL, (nn)
H - (nn+l)
L '- (nn)
X
X
11 III 101 FD
00 100 001 21
-n00 101 010 2A
16
LD dd, (nn)
ddH - (nn+l)
ddL - (nn)
X
X
LD IX, (nn)
IXH - (nn+ I)
IXL - (nn)
X
X
-nII Oil 101 DD
00 101 010 2A
LD IY, (nn)
IYH - (nn+ I)
IYL - (nn)
X
X
LD (nnl. HL
(nn+l) - H
(nn) - L
X
X
LD (nn), dd
(nn+l) - ddH
(nn) - ddL
X
X
-nII 101 101 ED
01 ddO Oil
20
20
11 III 101 FD
00 101 010 2A
-n00 100 010 22
20
20
20
16
§
20
8
LD (nnl. IX
(nn+I)-IXH
(nn) - IXL
X
X
LD (nn), IY
(nn+l) - IYH
(nn) - IYL
X
X
-·n II III 101 FD
00 100 010 22
LD SP, HL
LD SP, IX
SP - HL
SP - IX
X
X
X
X
LD SP, IY
SP - IY
X
X
PUSH qq
(SP-2) - qqL
(SP-I) - qqH
SP - SP -2
(SP-2) - IXL
(SP-I) - IXH
SP - SP -2
(SP-2) - IYL
(SP-I) - IYH
SP - SP -2
qqH - (SP+I)
qqL - (SP)
SP - SP +2
IXH - (SP+I)
IXL - (SP)
SP - SP +2
IYH - (SP+I)
IYL - (SP)
SP - SP +2
X
X
X
X
II Oil 101 DD
II 100 101 E5
IS
X
X
11 III 101 FD
II 100 101 E5
IS
X
X
II qqO 001
10
X
X
II 011 101 DD
II 100 001 EI
14
X
X
II III 101 FD
II 100 001 EI
14
POPqq
POP IX
POPIY
NOTES:
-nIII 001
011 101
111 001
III 101
111 001
qqO 101
F9
DD
F9
FD
F9
6
10
10
II
qq
00
01
10
II
Pair
BC
DE
HL
AF
dd is any 01 the register pairs BC, DE, HL, SP.
qq is any 01 the register pairs AF, BC, DE, HL.
(PAIR1H, (PAIR)L reler to high order and low order eight bits 01 the register pair respectively,
e.g., BCL = C, AFH = A.
DE - HL
AF - AF'
BC - BC'
DE - DE'
HL - HL'
H - (SP+l)
L - (SP)
IXH - (SP+I)
IXL - (SP)
IYH - (SP+I)
Iyt - (SP)
X
X
X
X
X
X
II 101 011 EB
00 001 000 08
II Oil 001 D9
X
X
II 100 011 E3
X
X
X
X
11
11
II
II
LDI
(DE) - (HL)
DE - DE+I
HL - HL+I
BC - BC-I
X
0
X
LDIR
(DE) - (HL)
DE - DE+I
HL - HL+I
BC - BC-I
Repeat until
BC = 0
X
0
X
EX DE, HL
EX AF, AF'
EXX
EX (SP), HL
EX (SPl. IX
EX (SP), IY
NOTE:
~
~
-nII 011 101 'DD
00 100 010 22
II
II
11
11
II
II
Comment.
dd
Pair
~
01
DE
10
HL
11
SP
14
-nII 101 101 ED
01 ddl Oil
PUSH IY
2001-001
S
LD dd, nn
PUSH IX
Exchange.
Block
Transfer.
Block Search
Groups
Symbolic
Operation
CD
Oil
100
III
100
101
011
101
011
DD
E3
FD
E3
Register bank and
auxiliary register
bank exchange
19
23
23
11 101 101 ED
10 100 000 AO
16
II 101 101 ED
10 110 000 BO
21
16
CD
CD PlY flag is 0 il the result oi BC - 1 = 0, otherwise P/V
Load (HL) into
(DE), increment
the pointers and
decrement the byte
counter (BC)
!fBC
0
!f BC =0
*
= 1.
11
Exchange.
Block
Transfer.
Block Search
Croups
Symbolic
Operallon
Mnemonic
S
Flags
H
P/V N
Z
C
Opcode
No.of No.of M No.of T
76 5'3 210 Hex Byte. Cycle. States
Comments
CD
LDD
(DE) - (HL)
DE - DE-I
HL - HL-I
BC - BC-I
X
0
X
LDDR
(DE) - (HL)
DE - DE-I
HL - HL-I
BC - BC-I
Repeat until
BC = 0
X
0
X
CPI
A - (HL)
HL - HL+ I
BC - BC-I
CPIR
A - (EL)
(Continued)
A - (EL)
HL - HL-I
BC - BC-I
CPDR
A - (HL)
II 101 lOl ED
lO III 000 B8
21
16
11'101 lOl ED
lO 100 001 Al
16
IfBC * 0
If BC = 0
(j)
@
X
X
X
X
CD
@
II 101 lOl ED
21
10 110001 BI
16
II lOl 101 ED
lO lOl 001 A9
16
II 101 101 ED
21
10 III 001 B9
16
IfBC*Oand
A", (HL)
If BC = 0 or
A = (HL)
CD
~
X
X
X
X
1
CD
G>
HL - HL-l
BC - BC-I
Repeat until
A = (HL) or
BC = 0
'NOTES:
16
Q)
HL - HL+I
BC - BC-I
Repeat until
A = (HL) or
BC = 0
CPD
II 101 101 ED
lO lOl 000 A8
IfBC",Oand
A", (HL)
If BC = 0 or
A = (HL)
(j) PlY flag IS 0 if the result of Be - I
ev PlY flag
IS
= O. otherwise PlY = I.
0 ot completion of instruction only.
G) Z flag is I if A = (HL). otherwise Z = O.
a-Bit
.Arithmetic
and Logical
Group
X
X 'V
10~ r
X
X
V
II
ADD A. (EL)
A - A + (HL)
ADD A. (lX+d) A - A + (IX+d)
X
X
X
X
v
ADD A. (IY +d) A - A + (IY +d)
X
X
V
lO [QQQ]
II 011
10 lQQQ]
d
II III
lO IQQQJ
d
ADDA. r
ADDA. n
V
0
~
ruiQJ llO
-
-[QQIJ
110
lOl
llO
-
101
llO
DD
19
FD
19
A - A+s+CY
I'
X
X
V
I
X
X
V
SBC A. s
A - A-s
A - A-s-CY
X
X
V
ANDs
A-Al\s
X
X
OR s
A-AVs
X
XOR s
A- A e s
A-s
X
X
P
X
X
V
INC r
INC (EL)
INC (IX+d)
r- r + I
(EL) -(HL)+I
(IX+d) .,..
(IX+d)+1
X
X
V
00 r (i]Q]
X
X
X
X
V
V
INC (lY +d)
(lY+d) (IY+d)+1
X
X
V
00 110 IIW
II 011 101 DD
00 llO IIQQ]
d
II III 101 'FD
00 llO IIQQ]
d
DEem
m -m-I
X
X
V
[QIQ]
[QIT]
[QQ)
[jJ]J
[IQj]
P
X ,P
000
001
010
011
100
101
III
B
C
D
E
H
L
A
s Is any of r. n.
(HL). (IX+d).
(lY + d) liS shown
for ADD instruction,
The indicated bits
replace the [QQQ] in
the ADD set above.
ADCA. s
SUB s
CPs
12
A- A + r
A-A+n
[j}]
0
-
-
[@]
II,
23
23
m is any of r. (HL).
(IX+d). (lY+d)
as shown for INC,
DEC same format
and states liS INC,
Replace [QQ) with
[@] in opcode,
2001-001
GeneralPurpose
Arithmetic
and
CPU Control
Groups
Symbolic
Operation
Mnemonic
DAA
CPL
X
X
X
X
X
NEG
A-O-A
CY -
SCF
NOP
HALT
CY - I
No operation
CPU halted
IFF - a
IFF - I
Set interrupt
mode a
Set interrupt
mode 1
Set interrupt
mode 2
*
EI
IMO
IMI
1M2
NOTES:
Flags
H
P/V N
Z
Converts acc. content
into packed BCD
following add or
subtract with packed
BCD operands.
A-A
CCF
01*
S
CY
X
X
X
P
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C
Opcode
No.of No.of M No.of T
76 543 210 Hex Bytes Cycles States
Commonts
00 100 III 27
DeCimal adjust
accumulator.
00 101 III 2F
Complement
accumulator (one's
complement) .
Negate acc. (two's
complement) .
Complement curry
flag.
Set carry flag.
II 101 101 ED
01 000 100 44
00 III 111 3F
00
00
01
II
II
II
01
II
01
II
01
110
000
110
110
111
101
000
101
010
101
all
111
000
110
all
all
101
110
101
110
101
110
37
00
76
F3
FB
ED
46
ED
56
ED
5E
4
4
4
4
4
8
IFF indicates the interrupt enable f1ip·f1op.
CY indicates the carry flip· flop.
indicates interrupts are not sampled at the end of EI or DI.
~
*
IS-Bit
Arithmetic
Group
ADD HL,
S8
HL - HL+ss
X
X
X
00 ssl 001
II
ADC HL,
S8
HL - HL+ss+CY
X
X
X
V
II 101 101 ED
01 ssl 010
15
V
II
01
II
01
SBC HL,
X
X
X
X
X
ADD IY, rr
IY - IY + rr
X
X
X
II III 101 FD
00 rrl 001
15
INC ss
INC IX
ss - ss + 1
IX - IX + 1
X
X
X
X
6
10
INCIY
IY - IY + 1
X
X
DECss
DEC IX
ss - ss-1
IX - IX-l
X
X
X
X
DECIY
IY - IY-l
X
X
00
11
00
11
00
00
11
00
11
00
~-L[i~i}J
X
X
00 000 III
07
Rotate left circular
accumulator.
l@j~
X
X
00 010 III
17
Rotate left
accumulator.
RRCA
L~~
X
X
00 001 111
OF
Rotate right Circular
accumulator.
RRA
~@l
X
X
00 all III
IF
Rotate right
accumulator.
II 001 all
OO[QQQ]r
II 001 all
00 [QQQ] 110
CB
CB
15
II all 101
II 001 all
d
00 [QQQ] 110
DD
CB
23
II III 101
II 001 all
d
FD
CB
23
ssO
all
100
III
100
ssl
all
101
III
101
RLC r
X
X
RLC (HL)
X
X
P
X
P
RLC (lX+d)
~~::J
X
a
r,(HL),(!X + d),(!Y + d)
RLC (IY+d)
- -
X
a
X
P
X
X
P
IQIQ]
X
X
p
I22Il
-
l@j~
-
00 ~ 110
mar,(HLl.(lX+dJ.(IY +d)
RRC m
DD
23
FD
23
DD
2B
FD
2B
15
pp
00
01
10
II
rr
00
01
10
II
Reg.
BC
DE
IX
SP
Reg.
BC
DE
IY
SP
10
6
10
10
ss is any of the register pairs BC, DE, HL, SP ..
pp is any of the register pairs BC, DE, IX, SP.
rr is any of the register pairs BC, DE, IY, SP.
RLCA
RLm
all
101
all
101
all
all
101
all
101
all
~
e:J
15
X
RLA
L~~
m .. r,(HLJ.(IX + dJ.(IY + d)
2001-001
101 ED
010
101 DD
001
HL - HL-ss-CY
IX - IX + pp
NOTES:
Rotate and
Shift Group
101
ssO
all
ppl
~
00 BC
01 DE
10 HL
II SP
ADD IX, pp
S5
C
6
Rotate left circular
register r.
~.
000
001
010
all
100
101
III
B
C
D
E.
H
L
A
Instruction format
and states are as
shown for RLC's.
To form new
opcode replace
lQQQ] or RLC's
with shown code.
13
Rotate and
Shift Group
(Continued)
Symbolic
Operation
Mnemonic
S
~@J
RRm
Flags
H
P/V N
Z
C
Opcode
76 5'3 210
X
X
[iQQ]
X
X
I.@]
X
X
P
[ill]
I
X
X
P
II 101 101
01 101 III
ED
6F
18
I I
X
X
P
II 101 101
01 100 III
ED
67
18
dJ=D-~
Comments
IQill
X
@]~o
me r,(HL).'{IX + dl.(IY + d)
SRAm
No.of No.of M No.of T
Bytes Cycles States
X
l-
P
m"r,(HL).(lX +dl.(IY +d)
SLAm
Hex
m.,r,(HLl.(IX +d).(lY +d)
SRL m
o~@]
mE r,(HLl.(IX + dl.(IY + d)
RLD
EI$l
!7jgO!
A
(HL)
!7-4!3fol
RRD
!
A
Bit Set. Reset
and Test
Group
/-3!!} °
a
(HL)
BIT b, r
Z - rb
X
X
X
X
BIT b, (HL)
Z - (HL)b
X
X
'X
X
X
X
X
X
II 001 all CB
01
b
r
II 001 all CB
01
BIT b, (IX + d)b Z - (IX + d)b
b 110
II all 101 DD
11 001 011 CB
d
01 b 110
12
BIT b, (lY +d)b Z - (IY +d)b
SET b, r
rb -,I
X
X
X
X
X
X
20
-
-
11 111 101 FD
11 001 all CB
d
01 b 110
11 001
b
II 001
[!) b
11 all
II 001
d
b
11 III
11 001
d
[!] b
20
Rotate digit left and
right between
the accumulator
and location (HL).
The content of the
upper half of
the accumulator is
unaffected.
~
000 B
001 C
010 D
all E
100 H
101 L
III A
b
Bit Tested
000 a
001 1
010 2
all 3
100 4
101 5
110 6
III 7
all CB
[ill
SET b, (HL)
SET b, (IX+d)
(HL)b - 1
(lX'+d)b - 1
X
X
X
X
-
SET b, (IY +d)
RES b, m
NOTES:
Jump
Group
JP nn
mb - a
m. r, (HL),
(IX+d).
(IY+d)
X
X
X
X
15
110
101 DD
all CB
23
110
101 FD
-
110
[Q]
To form new
opcode replace
[ill of SET b, s
with [Q]. Flags
and time states for
SET instruction.
The notation mb Indicates bit b (0 to 7) or loc.tion m.
PC - nn
X
X
11 000 all C3
10
n
11 cc 010
10
If condition cc is
true PC - nn,
otherwise
continue
X
X
JR e
PC - PC+e
X
X
JR C, e
If C = 0,
continue
IfC = I,
PC - PC+e
IfC = I,
continue
If C = 0,
PC - PC+e
If Z = a
continue
If Z = I,
PC - PC+e
If Z = I,
continue
If Z· = 0,
PC - PC+e
PC - HL
X
X
X
X
X
X
11 101 001 E9
PC - IX
X
X
11 011,101 DD
11 101 001 E9
JP Z, e
JR NZ, e
JP (HL)
JP(IX)
23
all CB
JP cc, nn
JR NC, e
14
IDJ
(IY+d)b - I
all CB
X
X
X
X
00
00
-
all 000 18
e-2 III 000 38
e-2 -
12
cc
Condition
000 NZ non· zero
001 Z zero
010 NC non· carry
all C carry
100 PO parity odd
101 PE parity even
110 P sign positive
111 M sign neg.tive
If condition not ~et.
12
If condition is met.
12
If condition is met.
12
If condition is met.
12
If condition is met.
00 110 000 30
- e-2 -
If condition not met.
If condition not met.
00 101 000 28
- e-2 -
If condition not met.
00 100 000 20
- e-2 -
2001-001
Jump Group
(Continued)
Mnemonic
S
Flags
P/V N
H
Z
JP (lY)
PC - IY
X
X
DJNZ, e
B - B-1
If B = 0,
continue
If B *- 0,
PC - PC+e
X
X
NOTES:
Call and
Return Group
Symbolic
Operation
C
Opcode
No.of No.of M No.of T
76 543 210 Hex Bytes Cycles States
II
II
00
-
III 101 FD
101 001 E9
010 000 10
e-2 -
Comments
If B = O.
13
If B *- O.
e represents the extension in the relative addressing mode.
a is a signed two's complement number In the range < -126, 129 >.
e - 2 in the opcode provides an effective address of pc + e as PC is incremented
by 2 prior to the addition of e.
CALL nn
(SP-I) - PCH
(SP-2) - PCL
PC - nn
X
X
II 001 101 CD
CALL cc, nn
If condition
cc is false
X
X
II cc 100
17
continue,
10
If cc is false.
17
If cc is true.
otherwise same as
CALL nn
RET
PCL - (SP)
PCH - (SP+ 1)
X
X
11 001 001 C9
RET cc
If condition
cc is false
X
X
11 cc 000
10
11
continue,
otherwise
same as
RET
RET!
RETN1
RST p
Return from
interrupt
Return from
non·maskable
interrupt
X
X
X
X
(SP-I)
(SP-2)
PCH PCL -
X
X
- PCH
- PCL
0
p
11
01
11
01
101
001
101
000
101
101
101
101
11
t
III
e
If cc is false.
ED
4D
ED
45
14
14
·11
9
If cc is true.
cc
000 NZ
001 Z
010 NC
011 C
100 PO
101 PE
110 P
111M
Condition
non-zero
zero
non-carry
carry
parity odd
parity even
sign positive
sign negative
~
000
001
010
011
100
101
110
III
OOH
OSH
IOH
ISH
20H
2SH
30H
3SH
NOTE: . 'RETN loads IFF2 - IFFI
Input and
Output Group
IN A, (n)
A - (n)
INr, (C)
r - (C)
if r = 110 only the
flags will be affected
INI
(HL) - (C)
B - B-1
HL - HL + 1
(HL) - (C)
B - B-1
HL - HL + 1
Repeat until
B = 0
INIR
OUT (n). A
(HL) - (C)
B - B-1
HL - HL-I
(HL) - (C)
B - B-1
HL - HL-I
Repeat until
B = 0
(n) - A
OUT (C), r
(C) - r
OUTI
(C) - (HL)
B - B-1
HL - HL + I
(C) - (HL)
B - B-1
HL - HL + I
Repeat until
B = 0
IND
INDR
OT!R
(C) - (HL)
B - B-1
HL - HL-I
OUTD
NOTE:
X
X
X
X
P
11 011 011 DB
n
11 101 101 ED
01 r 000
-
11
-
12
n toAD - A7
Ace. to AS - A15
C to AD - A7
B to AS - A15
CD
X
X
X
X
X
X
11 101 101 ED
10 100 010 A2
X
X
X
X
X
11 101 101 ED
10 110010 B2
@
X
5
(If B*-O)
4
(If B=O)
16
C to AO - A7
B to AS - A15
21
C to AD - A7
BtoAS- A I5
16
CD
X
X
X
X
X
X
II 101 101 ED
10 101 010 AA
X
X
X
X
X
11 101 101 ED
10 III 010 BA
@
X
X
CD
1
C to AD - A7
BtoAS-·AI5
21
C to AD - A7
B to AS - AI5
16
X
X
11 010 011 D3
II
X
X
11 101 101 ED
01 r 001
12
16
C to AD - A7
B to AS - AI5
21
C to AD - A7
B to AS - A15
X
,X
X
X
X
II 101 101 ED
10 100011 A3
X
X
X
X
X
11 101 101 ED
10 110 011 B3
@
X
5
(If B*-O)
4
(II B=O)
16
5
(If B*-?)
4
(If B=O)
n toAD - A7
Ace. to AS - AI5
C toAO - A7
BtoAS - AI5
16
CD
X
X
X
X
X
X
11 101 101 ED
10 101 011 AB
16
C to AD - A7
B to AS - AI5
CD If the result of B-1 is zero the Z flag is set, otherwise it is reset.
Q) Z flag
2001-00i
. I
is set upon instruction completion only.
15
Input and
Output Group
(Continued)
16
Flags
H
P/V N
Z
X
(C) - (HL)
B - B-1
HL - HL-I
Repeat until B = 0
OTDR
Opcode
No.of No.of M No.of T
76 543 210 Hex' Bytes Cycles States
C
Comment.
X
I
X
X
X
X
II 101 101 ED
10 III 011
5
4
(If B=O)
.
21
(If B*O)
C to AO - A7
B to Aa - AI5
16
(i) Z !lag IS set upon instruction completIon only.
Instruction
ADD A. s; ADC A, S
SUB s; SBC A, s; CP s; NEG
ANDs
OR s, XOR s
INCs
DEC s
ADD DD, ss
ADC HL, ss
SBC HL, ss
RLA,RLCA,RRA;RRCA
RL m; RLC m; RR m;
RRC m; SLA m;
SRA m; SRL m
RLD; RRD
DAA
CPL
SCF
CCF
IN rIC)
INI, IND, OUT!; OUTD
INIR; INDR; OT!R; OTDR
LDI; LDD
LDIR; LDDR
CPI; CPIR; CPD; CPDR
LD A, I, LD A, R
BIT b, s
Symbolic
Notation
S
Q)
NOTE:
Summary of
Flag
Operation
Symbolic
Operation
Mnemonic
0.,
S
I
X
X
X
X
X
I
X
Z
I
I
I
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X·
X
X
I
0
X
0
X
X
0
0
X
X
X
I
I
I
X
X
X
X
X
X
X
X
X
X
X
P/V
N
V
V
P
P
V
V
0
I
0
0
0
I
0
0
I
0
0
V
V
P
X
X
X
X
X
X
X
X
X
X
X
P
P
X
X
IFF
X
P
X
X
I
0
0
0
I
I
0
0
I
Do
C
Comments
I
I
a·bit add or add with carry.
a·bit subtract, subtract with carry, compare and negate accumulator.
~}
Logical operations.
a·bit increment.
a·bit decrement.
16·bit add.
16·bit add with carry.
16·bit subtract with carry.
Rotate accumulator.
Rotate and shift locations.
Rotate digit left and right.
Decimal adjust accumulator.
Complement accumulator.
Set carry.
Complement carry.
Input register indirect.
:}
:}
Block input and output. Z = 0 if B * 0 otherwise Z = O.
Block tra'nsfer instructions. P/v = I if BC * 0, otherwise P/V = O.
Block search instructions. Z = I if A = (HL). otherwise Z = O. P/V = I
if BC * 0, otherwise P/V = O.
The content of the interrupt enable flip·flop (IFF) is copied into the P/V flag.
The state of bit b of location s is copied into the Z flag.
Operation
Symbol
Sign flag. S = 1 if the MSB of the result is 1.
S
Zero flag. Z = 1 if the result of the operation is O.
Z
Parity or overflow flag. Parity (P) and overflow
P/V
(V) share the same flag. Logical operations affect
this flag with the parity of the result while
arithmetic operations affect this flag with the
overflow of the result. If P/V holds parity, PlY
1 if the result of the operation is even, P/V = 0 if
result is odd. If PlY holds overflow, PlY = 1 if
the result of the operation produced an overflow.
Half-carry flag. H = 1 if the add or subtract
H
operation produced a carry into or borrow from
bit 4 of the accumulator.
AddlSubtract flag. N = 1 if the previous operaN
tion was a subtract.
Hand N flags are used in conjunction with the
H&N
decimal adjust instruction (DAA) to properly correct the result into packed BCD format following
addition or subtraction using operands with
packed BCD format.
CarrylLink flag. C = 1 if the operation produced
C
a carry from the MSB of the operand or result.
Operation
Symbol
The flag is affected according to the result of the
I
operation.
The flag is unchanged by the operation.
The flag is reset by the operation.
0
The flag is set by the operation.
1
The flag is a "don't care."
X
P/V flag affected according to the overflow result
V
of the operation.
PlY flag affected according to the parity result of
P
the operation.
Anyone of the CPU registers A. B, C, D, E, H, L.
Any 8-bit location for all the addressing modes
allowed for the particular instruction.
Any 16-bit location for all the addressing modes
ss
allowed for that instruction.
Anyone of the two index registers IX or IY.
ii
Refresh counter.
R
8-bit value in range < 0, 255 >.
n
16-bit value in range < 0, 65535 >.
nn
2001-001
Pin
Descriptions
Ao-AlS' Address Bus (output, active High,
3-state). Ao-A15 form a 16-bit address bus. The
Address Bus provides the address for memory
data bus exchanges (up to 64K bytes) and for
I/O device exchanges.
BUSACIC Bus Acknowledge (output, active
Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus,
data bus. and control signals MREQ, IORQ,
RD, and WR have entered their highimpedance states. The external circuitry
can now control these lines.
BUSREQ. Bus Request (input, active Low).
Bus Request has a higher priority than NMI
and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, IORQ, RD, and WR to go to a highimpedance state so that other devices can
control these lines. BUSREQ is normally wireORed and requires an external pullup for
these applications. Extended BUSREQ
periods due to extensive DMA operations can
prevent the CPU from properly refreshing
dynamic RAMs.
00-07' Data Bus (input/output, active High,
3-state). Do-D7 constitute an 8-bit bidirectional
data bus, used for data exchanges with
memory and I/O.
HALT. Halt State (output, active Low). HALT
indicates that the CPU has executed a Halt
instruction and is awaiting either a nonmaskable or a maskable interrupt (with the
mask enabled) before operation can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.
INT. Interrupt Request (input, active Low).
Ml. Machine Cycle One (output, active Low).
MI, together with MREQ, indicates that the
current machine cycle is the opcode fetch
cycle of an instruction execution. MI, together
with IORQ, indicates an interrupt acknowledge
cycle.
MREQ. Memory Request (output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.
NMI. Non-Maskable Interrupt (input, negative
edge-triggered). NMI has a higher priority
than INT. NMI is always recognized at the end
of the current instruction, independent of the
status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at location 0066H.
RD. Read (output, active Low, 3-state). RD
indicates that the CPU wants to read data from
memory or an I/O device. The addressed I/O
device or memory should use this signal to
gate data onto the CPU data bus.
RESET. Reset (input, active Low). RESET
initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the interrupt status
to Mode O. During reset time, the address and
data bus go to a high-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minimum
of three full clock cycles before the reset
operation is complete.
RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bits of the s'ystem's address bus can be
used as a refresh address to the system's
dynamiC memories.
Interrupt Request is generated by I/O devices.
The CPU honors a request at the end of the
current instruction if the internal softwarecontrolled interrupt enable flip-flop (IFF) is
enabled. INT is normally wire-ORed and
requires an external pullup for these
applications.
WAIT. Wait (input, active Low). WAIT
IORQ. Input/Output Request (output, active
WR. Write (output, active Low, 3-state). WR
Low, 3-state). IORQ indicates that the lower
half of the address bus holds a valid I/O
address for an I/O read or write operation.
IORQ is also generated concurrently with MI
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be
placed on the data bus.
indicates to the CPU that the addressed memory or I/O devices are not ready for a data
transfer. The CPU continues to enter a Wait
state as long as this signal is active. Extended
WAIT periods can prevent the CPU from
refreshing dynamic memory properly.
indicates that the CPU data bus holds valid
data to be stored at the addressed memory or
I/O location.
17
CPU Timing
The Z80 CPU executes instructions by proceeding through a specific sequence of operations:
• Memory read or write
I/O device read or write
II
II
Interrupt acknowledge
Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). Approximately one-half clock cycle later,
MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the
CPU data bus.
T,
TW
The basic clock period is referred to as a
T time or cycle, and three or more T cycles
make up a machine cycle (MI, M2 or M3 for
instance). Machine cycles can be extended
either by the CPU automatically inserting one
or more Wait states or by the insertion of one
or more Wait states by the user.
The CPU samples the WAIT input with the
falling edge of clock state T2. During clock
states T3 and T4 of an MI cycle dynamic RAM
refresh can occur while the CPU starts
decoding and executing the instruction. When
the Refresh Control signal becomes active,
refreshing of dynamic memory can take place.
Ta
CLOCK
Ao-A15
_-+-_..J
«« ~
RFSH
----F/j/~-~r~
f-®11
r-
---------1
NOTE: Tw-Wait cycle added when necessary for slow ancilliary devices.
Figure 5. Instruction Opcode Fetch
18
2005-882
CPU
Timing
(Continued)
Memory Read or Write Cycles. Figure 6
shows the timing of memory read or write
cycles other than an opcode fetch (Ml) cycle.
The MREQ and RD signals function exactly as
in the fetch cycle. In a memory write cycle,
MREQ also becomes active when the address
bus is stable. The WR line is active when the
data bus is stable, so that it can be used
directly as an R/W pulse to most semiconductor memories.
RD
OPERA~~~~
{
00- 0 7
WR
OPER~~II~~
{
Do-D7----------~--~--------~~--~~~------------~
Figure 6. Memory Read or Write Cycles
2005-883
19
CPU
Timing
(Continued)
inserts a single Wait state (Tw). This extra Wait
state allows sufficient time for an I/O port to
decode the address from the port address lines.
Input or Output Cycles. Figure 7 shows the
timing for an I/O read or I/O write operation.
During I/O operations, the CPU automatically
CLOCK
AO-A7 __+-J1~__~________~~~~ ----~-------H-4--~~,--
+-__~~~__________~__~~~-JI
WAIT __
110 {
READ
OPERATION
WR
WRI~~
OPERATION { 00- 0 7
---------~t:::::::::::::::~~::::::~~~::::::}
NOTE: Tw* = One Wait cycle automatically inserted by CPU.
Figure 7. Input or Output Cycles
During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an a-bit vector on the
data bus. The CPU automatically adds two
Wait states to this cycle.
Interrupt Request/Acknowledge Cycle. The
CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of
any instruction (Figure 8). When an interrupt
is accepted, a special Ml cycle is generated.
AO-A15
PC
-----------+--,~--------------~------~~~----~_4~J~----
I.-------~@D~------~I
WAIT
----------_4--------------~--------*_--~-J
00-07
NOTE: 1)TL = Last state of previous instruction.
2) Two Wait cycles automatically inserted by CPU(*).
Figure 8. Interrupt Request/Acknowledge Cycle
20
2005-884, 885
CPU
Timing
(Continued)
Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the maskable interrupt input INT but has higher priority
and cannot be disabled under software control.
The subsequent timing is similar to that of a
normal instruction fetch except that data put
on the bus by the memory is ignored. The
CPU instead executes a restart (RST) operation
and jumps to the NMI service routine located
at address 0066H (Figure 9).
CLOCK
Ao-A15
-----------+J-}__l---~--__l--J.l__----+--I_---_+'
I
9
• Although NMI is an -asynchronous input, to ~antee its being
recognized on the following machine cycle, NMI's falling edge
must occur no later than the rising edge of the clock cycle
preceding TLAST.
Figure 9. Non-Maskable Interrupt Request Operation
B~s Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock period of any machine cycle (Figure
10). If BUSREQ is active, the CPU sets its
address, data, and MREQ, IORQ, RD, and WR
Tx
lines to a high-impedance state with the rising
edge of the next clock pulse. At that time, any
external device can tale control of these lines,
usually to transfer data between memory and
I/O devices.
Tx
Tx
T,
CLOCK
BUSREQ
--------~~~--~4---~,~------J
Ao-A'5 _ _ _ _ _ _ _ _ _ _~-..r~,J----...;.,;;;.;.;,;...----'"'"'i""1
DO-D7
MREQ
==========j=}-......"J----~!!!...----_i~
------------!-,L
~~~--~--------J-;-......"J----~;.;.;,;...-----l-1
-®-
HALT
----------------+---------------------------
NOTE: TL = Last state of any M cycle.
UNCHANGED
TX = An arbitrary clock cycle used by requesting device.
Figure 10. Z-BUS Request/Acknowledge Cycle
2005-0218, 886
21
CPU
Timing
(Continued)
received. When in the Halt state, the HALT
output is active and remains so until an interrupt is received (Figure 11).
Halt Acknowledge Cycle. When the CPU
receives a Halt instruction, it executes NOP
states until either an INT or NMI input is
M1
CLOCK
•
~.
I•
M1
~
~
•
~
36
~
I•
~
M1
~
-®
.
HALT=::~
~_._ _ _ _ _ _ _ _ _ _ __
Received
U-
NMI
NOTE: lNT will also force a Halt exit.
·See note, Figure 9.
Figure 11. Halt Acknowledge Cycle
Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept it. As long as RESET remains active, the
address and data buses float, and the control
outputs are inactive. Once RESET. goes
inactive, three internal T cycles are consumed
before the CPU resumes normal processing
operation. RESET clears the PC register, so the
first opcode fetch will be to location 0000
(Figure 12).
1__- - - M 1 - - - -
-
-:
CLOCK
-@~~----~~------~------------~,,--
00- 0 7
FLOAT
-@M1
I
)
----------------~
1!R~
R~~--------~~r7~7~~----~/~/~---------------T-----------RFSH,
BUSACK
1111/11
\'---_
__
-
HALT
Figure
22
~2.
Reset Cycle
2005-887, 888
AC Characteristics
Number Symbol
Parameter
Z80 CPU
Min Max
Z80A CPU
Min Max
Z80B CPU
Min Max
Z80H cPut
Min Max
TcC
Clock Cycle Time
400*
250*
165*
125*
2
TwCh
Clock Pulse Width (High)
180*
110*
65*
55*
3
TwCl
Clock Pulse Width (Low)
180
4
TfC
Clock Fall Time
30
30
20
5-TrC
Clock Rise Time
30
30
20-
6
TdCr(A)
Clock I to Address Valid Delay
7
TdA(MREQf)
Address Valid to MREQ
I Delay
2000
110
145
125*
2000
65
110
65*
2000
55
2000
10
-10-
90
35*
80
20*
8
TdCf(MREQf)
Clock I to MREQ I Delay
100
85
70
60
9
TdCr(MREQr)
Clock I to MREQ t Delay
100
85
70
60
10 -
TwMREQh - - MREQ Pulse Width (High) - - - 170*
110*
65*
11
TwMREQl
220*
135*
12
TdCf(MREQr)
Clock I to MREQ t Delay
100
85
70
60
13
TdCf(RDf)
Clock I to RD I Delay
130
95
80
70
14
TdCr(RDr)
Clock I to RD I Delay
100
15 -
TsD(Cr) - - - Data Setup Time to Clock I - - - 50
MREQ Pulse Width (Low)
16
ThD(RDr)
Data Hold Time to RD t
17
TsWAIT(Cf)
WAIT Setup Time to Clock I
18
ThWAIT(Cf)
WAIT Hold Time after Clock I
19
TdCr(Mlf)
360*
85
35
0
70
45*100*
70
60
30-
30
0
0
70
60
0
50
0
0
0
0
Clock I to Ml I Delay
130
100
80
70
20 -
TdCr(Mlr) - - Clock I to Ml t Delay
130
100
21
TdCr(RFSHf)
Clock I to RFSH I Delay
180
130
110
95
22
TdCr(RFSHr)
Clock I to RFSH t Delay
150
120
100
85
60
80-
23
TdCf(RDr)
Clock I to RD I Delay
110
85
70
24
TdCr(RDf)
Clock t to RD I Delay
100
85
70
25 -
TsD(Cf) - - - Data Setup to Clock I during - - 60
M2 , M3 , M4 or Ms Cycles
26
TdA(IORQf)
Address Stable prior to IORQ I
27
TdCr(IORQf)
Clock t to IORQ I Delay
28
TdCf(IORQr)
Clock I to IORQ t Delay
29
TdD(WRf)
Data Stable prior to WR I
30 -
TdCf(WRf) - - Clock I to WR I Delay
31
TwWR
WR Pulse Width
32
TdCf(WRr)
Clock I to WR t Delay
33
TdD(WRf)
Data Stable prior to WR I
34
TdCr(WRf)
Clock t to WR I Delay
35 -
TdWRr(D) - - Data Stable from WR t
36
TdCf(HALT)
Clock I to HALT t or I
37
TwNMI
NMI Pulse Width
38
TsBUSREQ(Cr) BUSREQ Setup Time to Clock t
50
90
110*
75
110
220*
100
20*
80
80
70- - -60100*
70
65
60
55*
60
30*
300
300
60
5*
-55*
60*
55
70
135*
-10*
120*
75*
25*
80
90
360*
60
65
85
80*
190*
-70-
30-
40
180*
320*
I
9
55
15*-
260
225
80
80
70
60*
80
50
50
40
'For clock periods other than the minimums shown in the table,
calculate parameters using the expressions in the table on the
following page.
r Units in nanoseconds (ns). All timings are preliminary and
subject to change.
23
AC Characteristics (Continued)
Number Symbol
Z80 CPU
Min Max
Parameter
ThBUSREQ(Cr) BUSREQ Hold Time after Clock I
39
40 -TdCr(BUSACKf)-Clock I to BUSACK I Delay
0
TdCf(BUSACKr) Clock I to BUSACK I Delay
TdCr(Dz)
Clock I to Data Float Delay
42
TdCr(CTz)
Clock I to Control Outp~Float
43
DelaliMREQ, IORQ, RD,
and WR}
TdCr(Az)
Clock I to Address Float Delay
44
45-TdCTr(A) --MREQ I, IORQ I, RD I, and--160*
,
WR I to Address Hold Time
49
50
51
52
53
TsRESET(Cr)
RESET to Clock I Setup Time
ThRESET(Cr)
RESET to Clock I Hold Time
TsINTf(Cr)
INT to Clock I Setup Time
ThINTr(Cr}
INT to Clock I Hold Time
-TdMlf(IORQf)-Ml I to IORQ I Delay
TdCf(IORQf)
Clock I to IORQ I Delay
TdCf(IORQr)
Clock I to IORQ I Delay
TdCf(D)
Clock I to Data Valid Delay
Z80B CPU
Min Max
0
120
41
46
47
48
Z80A CPU
Min Max
0
0
90--- -80
110
100
100
90
90
110
90
80
80
70
110
90
80
60
0
70
110
100
230
0
365*
565*
0
55
0
0
70
45
0
80
920*
60
20*-
35*
60
0
80
70
80
80*
90
Z80H cPut
Min Max
85
85
150
0
270*-
70
70
60
60
130
115
"For clock periods ~ther than the minimums shown in the table,
calculate parameters using the following expressions. Calculated
values above assumed TrC = TfC = 20 ns.
i Units in nanoseconds (ns). All timings are preliminary and
subject to change.
Footnotes to AC Characteristics
zao
Number Symbol
2
Z80A
Z80B
TeC
TwCh + TwC1 + TrC + TfC
TwCh + TwC1 + TrC + TfC
TwCh + TwC1 + TrC + TfC
TwCh
Although static by design,
TwCh of greater than 200 p.s
is not guaranteed
Although static by design,
TwCh of greater than 200 p.s
is not guaranteed
Although static by deSign,
TwCh of greater than 200 p.s
is not guaranteed
7 -TdA(MREQf)-TwCh + TfC - 75 ----TwCh + TfC - 65----TwCh + TfC - 5 0 - - - 10
TwMREQh
TwCh + TfC - 30
TwCh + TfC - 20
TwCh + TfC - 20
11
TwMREQl
TcC - 40
TcC - 30
TcC - 30
26
TdA(lORQf)
TcC - 80
TcC - 70
TdD(WRf)
TeC - 170
29
TcC - 210
31-TwWR---TcC - 4 0 - - - - - - - T c C - 30
TcC - 3 0 - - - - - - -
33
TdD(WRf)
TwC1 + TrC - 180
TwC1 + TrC - 140
TwC1 + TrC - 140
35
TdWRr(D)
TwC1 + Tre - 80
TwC1 + TrC - 70
TwC1 + TrC - 55
45
TdCTr(A)
TwC1 + TrC - 40
TwC1 + TrC - 50
TwC1 + TrC - 50
50
TdMlf(IORQf) 2TcC + TwCh + TfC - 80
2TcC + TwCh + TfC - 65
2TcC + TwCh + TfC - 50
AC Test Conditions:
VIH = 2.0 V
VIL = 0.8 V
VIHC = VCC -0.6 V
VILC = 0.45 V
24
TcC - 55
TcC - 140
VOH = 2.0 V
VOL = 0.8 V
FLOAT = ±0.5 V
Absolute
Maximum
Ratings
Storage Temperature ........ -65°C to + 150 °C
Temperature
under Bias ........ Specified operating range
Voltages on all inputs and
outputs with respect to ground. -0.3 V to + 7 V
-Power Dissipation ..... ~ .............. 1.5 W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to' the device.
This is a stress rating only; operation'of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND (0 V). Positive current flows into the
referenced pin. Available operating
temperature ranges are:
[J S* = O°C to + 70°C,
+4.75 V :S Vee:S +5.25 V
IJ E* = -40°C to +85°C,
+ 4.75 V :S Vee:S + 5.25 V
[J M* = -55°C to + 125°C,
+ 4.5 V :S Vee:s + 5.5 V
All ac parameters assume a load capacitance
of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for
the data bus and 100 pF for address and control
lines.
+5V
'See Ordering Information section for package
temperature range and product number.
DC
Characteristics
VILe
Clock Input Low Voltage
-0.3
VIHe
Clock Input High Voltage
V
Input Low Voltage
Vee-· 6
-0.3
Vee + .3
VIL
0.8
V
VIH
Input High Voltage
2.0
Vee
V
VOL
Output Low Voltage
0.4
V
Io L = 1.8 rnA
VO H
Output High Voltage
V
IOH
= -250 p.A
Icc
Power Supply Current
Z80
Z80A
Z80B
= 0 to .vee
= 0.4 to Vee
Input Leakage Current
ILO
3-State Output Leakage Current in Float
L For military grade parts. ICC is 200 rnA.
2. Typical rate for lBOA is 90 rnA.
Capacitance
Test Condition
Min
III
Symbol
Parameter
Max
Unit
Parameter
Symbol
0.45
2.4
-10
V
150 1
200 2
200
rnA
rnA
rnA
10
10 3
p.A
VIN
p.A
VOUT
3. A15-AO. D7-DO. MREQ. IORQ. RD. and WR.
Min
Max
Unit
C eLOeK
C IN
Clock Capacitance
35
pF
Input Capacitance
5
pF
COUT
Output Capacitance
10
pF
Note
Unmeasured pins
returned to ground
TA = 25°C. f = 1 MHz,
8085-029
25
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Temp
Speed
Description
28400
CE
2.5 MHz
280 CPU (40-pin)
28400A
CMB
4.0 MHz
280A CPU (40-pin)
28400
CM
2.5 MHz
Same as above
28400A
CS
4.0 MHz
Same as above
28400
CMB
2.5 MHz
Same as above
28400A
DE
4.0 MHz
Same as above
28400
CS
2.5 MHz
Same as above
28400A
DS
4.0 MHz
Same as above
28400
DE
2.5 MHz
Same as above
28400A'
PE
4.0 MHz
Same as above
28400
DS
2.5 MHz
Same as above
28400A
PS
4.0 MHz
Same as above
28400
PE
2.5 MHz
Same as above
28400B
CS
6.0 MHz
280B CPU (40-pin)
28400
PS
2.5 MHz
Same
28400B
DS
6.0 MHz
Same as above'
28400A
CE
4.0 MHz
280A CPU (40-pin)
28400B
PS
6.0 MHz
Same as above
28400A
CM
4.0 MHz
Same as above
qS
above
"NOTES: C == Ceramic, D == Cerdip, P == Plastic; E == -40°C to + 85°-C, M == -55°C to + 125°C, MB == -55°C to + 125°C with
MIL-STD-883 Class B processing, S == O°C to +70°C.
26
00-2001-03
Z8410
Z80® DNA Direct
Memory Access Controller
Product
Specification
Zilog
September 1983
Features
.. Transfers, searches and search/transfers in
Byte-at-a-Time, Burst or Continuous modes.
Cycle length and edge timing can be programmed to match the speed of any port.
II Dual port addresses (source and destination)
generated for memory-to-I/O, memoryto-memory, or I/O-to-I/O operations.
Addresses may be fixed or automatically
incremented!decremented.
r.:J
General
Description
Next-operation loading without disturbing
current operations via buffered starting-
The 2-80 DMA (Direct Memory Access) is a
powerful and versatile device for controlling
and processing transfers of data. Its basic
function of managing CPU-independent
transfers between two ports is augmented by
an array of features that optimize transfer
speed and control with little or no external
logic in systems using an 8- or 16-bit data bus
and a 16-bit address bus.
" ,.!
DATA
BUS
D.
Ao
0,
A,
external logic.
Transfers can be done between any two ports
(source and destination), including memory-toI/O, memory-to-memory, and I/O-to-I/O. Dual
port addresses are automatically generated for
each transaction and may be either fixed or
incrementing/decrementing. 'In addition, bitmaskable byte searches can be performed
either concurrently with transfers or as an
operation in itself.
A,
0,
A,
A4
40
As
'39
A,
As
38
lEI
37
OO/PUlSE
Os
0,
0,
A,
SYSTEM
ADDRESS
BUS
SAo
A,.
zao DMA
Wii~ 8
RO
9
A"
A12
iORQ
1D
+5VL.."
IORQ
MAEQ
_iiii
iVA
A15
ROY
CElWAIT _
OO/PUlSE
lEI
lEO
}
}
OMA
CONTROL
~N~:::~~T
2032-0125, 0126
lEO
zao DMA
35
D.
34
0,
33
32
0,
0,
31
30
D.
GND
MREQ
12
29
Os
BACi
BAi
13
28
0,
14
27
0,
BUSREQ
15
26
M1
CEJwAIT L.. 18
25
ROY
A4
A15
17
24
Au L.. 18
23
An
22
Au
Figure 1. Pin Functions
As
36
elK
Au
M1
A,
A.
BAi
An
{
Il3 Direct interfacing to system buses without
0,
As
SYSTEM
CONTROL
BUS
• Extensive programmability' of functions.
CPU can read c~mplete channel status.
II Standard 2-80 Family bus-request and
prioritized interrupt-request daisy chains
implemented without external logic.
Sophisticated, internally modifiable inter:rupt vectoring.
D.
BUSREQ
BUS {
CONTROL
address registers. An entire previous
sequence can be repeated automatically.
19
g
P
2D _ _ _21
I..-.
....J
A.
A,.
A"
Figure 2. Pin Assignments
27
General
'" The Z-80 DMA contains direct interfacing to
Description
and independent control of system buses, as
(Continued)
well as sophisticated bus and interrupt controls. Many programmable features, including
variable cycle timing and auto-restart,
minimize CPU software overhead. They are
especially useful in adapting this specialFunctional
Description
Classes of Operation. The Z-80 DMA has
three basic classes of operation:
II Transfers of data between two ports (memory
or I/O peripheral)
13 Searches for a particular 8-bit maskable
byte at a single port in memory or an I/O
peripheral
m Combined transfers with simultaneous
search between two ports
\ Figure 4 illustrates the basic functions
s~rved by these classes of operation.
\ During a transfer, the DMA assumes control
of\the system address and data buses. Data is
read from one addressable port and written to
the\other addressable port, byte by byte. The
ports may be programmed to be either system
mai1\ memory or peripheral I/O devices. Thus,
a bldck of data may be written from one
peri~heral to another, from one area of main
mem6ry to another, or from a peripheral to
main ~emory and vice versa.
SYSTEM
BUSES
vL-\
~
y
DMA
CPU
-
INT
~ ROY
lEI
+5V
T
lEI
ZCtTOj
CTC
ZCtT02
INT
lEO
TxCA
lEO
TxCB
W/ROYA
W/ROYB
510
I
J\
Byte-at-a- Time: data operations are performed one byte at a time. Between each
byte operation the system buses are released
to the CPU. The buses are requested again
for each succeeding byte operation.
ra Burst: data operations continue until a
port's Ready line to the DMA goes inactive.
The DMA then stops and releases the system
buses after completing its current byte
operation.
[J Continuous: data operations continue until
the end of the programmed block of data is
reached before the system buses are
released. If a port's Ready line goes inactive
before this occurs, the DMA simply pauses
. until the Ready line comes active again.
IJ
.
lEO
iNT
lEI
110
PERIPHERAL
L...-t--t-ROY
DMA
1. Search memory
J\
2. Transfer memory·la-memory (optional search)
Y
3. Transfer memory·la-IIO (optional search)
4. Search 110
5. Transfer 110·10·110 (optional search)
Figure 3. Typical Z-BO Environment
28
Modes of Operation. The Z-80 DMA can be
programmed to operate in one of three transfer
and!or search modes:
Z·80 DMA
iNT
RxCB
During a search-only operation, data is read
from the source port and compared byte by
byte with a DMA-internal register containing a
programmable match byte. This match byte
may optionally be masked so that only cert'ain
bits within the match byte are compared.
Search rates up to 1.25M bytes per second can
be obtained with the 2.5 MHz Z-80 DMA or 2M
bytes per second with the 4 MHz Z-80A DMA.
In combined searches and transfers, data
is transferred between two ports while
simultaneously searching for a bit-maskable
byte match.
Data transfers or searches can be programmed to stop or interrupt under various
conditions. In addition, CPU-readable status
bits can be programmed to reflect the
condition.
-
lEI
RxCA
purpose transfer processor to a broad variety
of memory, I/O and CPU environments.
The Z-80 DMA is an n-channel silicon-gate
depletiqn-Ioad device packaged in a 40-pin
plastic or ceramic DIP. It uses a single + 5 V
power supply and the standard Z-80 Family
single-phase clock.
Figure 4. Basic Functions of the Z-BO DMA
2032-0127,0128
Functional
Description
(Continued)
In all modes, once a byte of data is read into
the DMA, the operation on the byte will be
completed in an orderly fashion, regardless of
the state of other signals (including a port's
Ready line).
Due to the DMA's high-speed buffered
method of reading data, operations on one
byte are not completed until the next byte is
read in. This means that total transfer or
search block lengths must be two or more
bytes, and that block lengths programmed into
the DMA must be one byte less than the
desired block length (count is N-I where N is
the block length).
Commands and Status. The 2-80 DMA has
several writable control registers and readable
status registers available to the CPU. Control
bytes can be written to the DMA whenever the
DMA is not controlling the system buses, but
the act of writing a control byte to the DMA
disables the DMA until it is again enabled by a
speCific command. Status bytes can also be
read at any such time, but writing the Read
Status Byte command or the Initiate Read
Sequence command disables the DMA.
Control bytes to the DMA include those
which effect immediate command actions such
as enable, disable, reset, load starting-address
buffers, continue, clear counters, clear status .
bits and the like. In addition, many modesetting control bytes can be written, including
mode and class of operation, port configuration, starting addresses, block length, address
counting rule, match and match-mask byte,
interrupt conditions, interrupt vector, statusaffects-vector condition, pulse counting, auto
restart, Ready-line and Wait-line rules, and
read mask.
Readable status registers include a general
status byte reflecting Ready-line, end-of-block,
byte-match .and interrupt conditions, as well as
2-byte registers for the current byte count,
Port A address and Port B address.
Variable Cycle. The 2-80 DMA has the
unique feature of programmable operationcycle length. This is valuable in tailoring the
DMA to the particular requirements of other
system components (fast or slow) and maximizes the data-transfer rate. It also eliminates
external logic for signal conditioning.
There are two aspects to the variable cycle
feature. First, the entire read and write cycles
(periods) associated with the source and
destination ports can be independently programmed as 2, 3 or 4 T-cycles long (more if
Wait cycles are used), thereby increasing or
2032-0129
decreasing the speed with which all DMA
signals change (Figure 5).
Second, the four signals in each port
specifically associated with transfers of data
(1/0 Request, Memory Request, Read, and
Write) can each have its active trailing edge
terminated one-half T-cycle early. This adds a
further dimension of flexibility and speed,
allowing such things as shorter-than-normal
Read or Write signals that go inactive before
da ta starts to change.
Address Generation. Two 16-bit addresses are
generated by the Z-80 DMA for every transfer
operation, one address for the source port and
another for the destination port. Each address
can be either variable or fixed. Variable
addresses can increment or decrement from
the programmed starting address. The fixedaddress capability eliminates the need for
separate enabling wires to 1/0 ports.
Port addresses are multiplexed onto the
system address bus, depending on whether the
DMA is reading the source port or writing to
the destination port. Two readable address
counters (2 bytes each) keep the current
address of each port.
Auto Restart. The starting addresses of either
port can be reloaded automatically at the end
of a block. This option is selected by the Auto
Restart control bit. The byte counter is cleared
when the addresses are reloaded.
The Auto Restart feature relieves the CPU of
software overhead for repetitive operations
such as CRT refresh and many others. Moreover, when the CPU has access to the buses
during byte-at-a-time or burst transfers, different starting addressas can be written into
buffer registers during transfers, causing the
Auto Restart to begin at a new location.
Interrupts. The 2-80 DMA can be programmed
to interrupt the CPU on three conditions:
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
eLK
~
'.""'~""''""'''
3.CYCLE~ FOR CONTROL SIGNALS
4·CYCLE
,
I
Figure 5. Variable Cycle Length
29
Functional
Description
(Continued)
Any of these interrupts cause an interruptpending status bit to be set, and each of them
can optionally alter the DMA's interrupt vector. Due to the buffered constraint mentioned
under "Modes of Operation," interrupts on
Match at End of Block are cau'sed by matches
to the byte just prior to the last byte in the
block.
The DMA shares the Z-80 Family's elaborate
interrupt scheme, which provides fast interrupt service in real-time applications. In a
Z-80 CPU environment, the DMA passes its
internally modifiable 8-bit interrupt vector to
the CPU, which adds an additional eight bits
to form the memory address of the interruptroutine table. This table contains the address
of the beginning of the interrupt routine itself.
In this process, CPU control is transferred
directly to the interrupt routine, so that the
next instruction executed after an interrupt
acknowledge is the first instruction of the interrupt routine itself.
Pulse Generation. External devices can keep
track of how many bytes have been transferred
by using the DMA's pulse output, which provides a signal at 256-byte intervals. The interval sequence may be offset at the beginning by
1 to 255 bytes.
The Interrupt line outputs the pulse signal in
a manner that prevents misinterpretation by
the CPU as an interrupt request, since it only
appears when the Bus Request and Bus
Acknowledge lines are both active.
Pin
Description
Ao-AIS. System Address Bus (output, 3-state).
system address bus is the DMA's address,
thereby allOWing a transfer of control or command bytes from the CPU to the DMA. As a
WAIT line from memory or I/O devices, after
the DMA has received a bus-request acknowledge from the CPU, it causes wait states
to be inserted in the· DMA' s operation cycles
thereby slowing the DMA to a speed that
matches the memory or I/O device.
Addresses generated by the DMA are sent to
both source and destination ports (main
memory or I/O peripherals) on these lines.
BAl. Bus Acknowledge In (input, active Low).
Signals that the system buses have been
released for DMA control. In multiple-DMA
configurations, the BAI pin of the highest
priority DMA is normally connected to the Bus
Acknowledge pin of the CPU. Lower-priority
DMAs have their BAI connected to the BAO of
a higher-priority DMA.
BAO. Bus Acknowledge Out (output, active
Low). In a multiple-DMA configuration, this
pin signals that no other higher-priority DMA
has requested the system buses.BAI and BAO
form a daisy chain for multiple-DMA priority
resolution over bus control.
BUSREQ. Bus Request (bidirectional, active
Low, open drain). As an output, it sends
requests for control of the system address bus,
data bus and control bus to the CPU. As an
input, when multiple DMAs are strung
together in a priority daisy chain via BAI and
BAO, it senses when another DMA has
requested the buses and causes this DMA to
refrain from bus requesting until the other
DMA is finished. Because it is a bidirectional
pin, there cannot be any buffers between this
DMA and any other DMA. It can, however,
have a buffer between it and the CPU because
it is unidirectional into the CPU. A pull-up
res'istor is connected to this pin.
CE/WAIT. Chip Enable and Wait (input,
active Low). Normally this functions only as a
CE line, but it can also be programmed to
serve a WAIT function. As a CE line from the
CPU, it becomes active when WR and IORQ
are active and the I/O port address on the
30
CLK. System Clock (input). Standard Z-80
single-phase clock at 2.5 MHz (Z-80 DMA) or
4.0 MHz (Z-80A DMA). For slower system
clocks, a TTL gate with a pullup resistor may
be adequate to meet the timing and voltage
level specification. For higher-speed systems,
use a clock driver with an active pullup to
meet the VIH specification and risetime
requirements. In all cases there should be a
resistive pullup to the power supply of 10K
ohms (max) to ensure proper power when the
DMA is reset.
'
Do-D7. System Data Bus (bidirectional,
3-state). Commands from the CPU, DMA
status, and data from memory or I/O
peripherals are transferred on these lines.
lEI. Interrupt Enable In (input, active High).
This is used with IEO to form a priority daisy
chain when there is more than one interruptdriven device.'A High on this line indicates
that no other device of higher priority is being
serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI is High and the
CPU is not servicing an interrupt from this
DMA. Thus, this signal blocks'lower-priority
devices from interrupting while a higherpriority device is being serviced by its CPU
interrupt service routine.
Pin
Description
(Continued)
Internal
Structure
INT/PULSE. Interrupt Request (output, active
Low, open drain). This requests a CPU interrupt. The CPU acknowledges the interrupt by
pulling its IORQ output Low during an Ml
cycle. It is typically connected to the INT pin
of the CPU with a pullup resistor and tied' to
, all other INT pins in the system. This pin can
also be used to generate periodiC pulses to an
external device. It can be used this way only
when the DMA is bus master (Le., the CPU's
BUSREQ and BUSACK lines are both Low
and the CPU cannot see interrupts).
IORQ. Input/Output Request (bidirectional,
active Low, 3-state). As an input, this indicates
that the lower half of the address bus holds a
valid I/O port address for transfer of control or
status bytes from or to the CPU, respectively;
thisDMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously
active. As an output, after the DMA has taken
control of the system bUf)es, it indicates that
the 8-bit or 16-bit address bus holds a valid
port address for another I/O device involved in
a DMA transfer of data. When IORQ and MI
are both active simultaneously, an interrupt
acknowledge is indicated.
Ml. Machine Cycle One (input, active Low).
Indicates that the current CPU machine cycle
is an instruction fetch. It is used by the DMA
to decode the return-from-interrupt instruction
(RET!) (ED-4D) sent by the CPU. During twobyte instruction fetches, MI is active as each
The internal structure of the 2-80 DMA
includes driver and receiver circuitry for interfacing with an 8-bit system data bus, a 16-bit
system address bus, and system control lines
(Figure 6). In a 2-80 CPU environment, the
DMA can be tied directly to the analogous pins
on the CPU (Figure 7) with no additional buffering, except for the CE/WAIT line.
The DMA's internal data bus interfaces with
the system data bus and services' all internal
logic and registers. Addresses generated from
this logic for Ports A and B (source and destination) of the DMA's single transfer channel
are multiplexed onto the system address bus.
opcode byte is fetched. An interrupt acknowledge is indicated when both Wand
IORQ are active.
MREQ. Memory Request (output, active Low,
3-state). This indicates that the address bus
holds a valid address for a memory read or
write operation. After the DMA has taken control of the system buses, it indicates a DMA
transfer request from or to memory.
RD. Read (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to read status bytes from the DMNs read
registers. As an output, after the DMA has
taken control of the system buses, it indicates a
DMA-controlled read from a memory or.I/O
port address.
RDY. Ready (input, programmable active Low
or High). This is monitored by the DMA to
determine when a peripheral device associated
with a DMA port is ready for a read or write
operation. Depending on the mode of DMA
operation (Byte, Burst or Continuous), the RDY
line indirectly controls DMA activity by causing the BUSREQ line to go Low or High.
WR. Write (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to write control or command bytes to the DMA
write registers. As an output, after the DMA
has taken control of the system buses, it
indicates a DMA-controlled write to a memory
or I/O port address.
Specialized logic circuits in the DMA are
dedicated to the various functions of external
bus interfacing, internal bus control, byte
matching, byte counting, periodic pulse
generation, CPU interrupts, bus requests, and
address generation. A set of twenty-one
writable control registers and seven readable
status registers provides the means by which
the CPU governs and monitors the activities of
these logic circuits. All registers are eight bits
Wide, with double-byte information stored in
adjacent registers. The two address counters
(two bytes each) for Ports A and B are buffered
by the two starting addresses.
SYSTEM
DATA j'L--L--'--.l\
SYSTEM
ADDRESS
BUS \ ........-.--r-,/
(8 BIT)
CONTROL \r---...,/I
BUS
(16 BIT)
CONTROL
AND
STATUS
REGISTERS
BYTE
MATCH
LOGIC
Figure 6. Block Diagram
2032-0130
31
Internal
Structure
(Continued)
The 21 writable control registers are
organized into seven base-register groups,
most of which have multiple registers. The
base registers in each writable group contain
both control/command bits and pointer bits
that can be set to address other registers within
the group. The seven readable status registers
have no analogous second-level registers.
The registers are designated as follows,
according to their base-register groups:
system bu's, however, may not be pre-empted.
Any DMA that gains access to the system bus
keeps the bus until it is finished.
Write Registers
WRO
Base register byte
Port A starting address (low byte)
Port A starting address (high byte)
Block length (low byte)
Block length (high byte)
WRO-WR6 - Write Register groups 0
through 6 (7 base registers plus 14.associated registers)
RRO-RR6 - Read Registers 0 through 6
WRI
Base register byte
Port A variable-timing byte
WR2
Base register byte
Port B variable-timing byte
Writing to a register within a write-register
group involves first writing to the base
register, with the appropriate pointer bits set,
then writing to one or more of the other
registers within the group. All seven of the
readable status registers are accessed sequentially according to a programmable mask contained in one of the writable registers. The section entitled "Programming" explains this in
more detail.
A pipe lining scheme is used for reading data
in. The programmed block length is the
number of bytes compared to the byte counter,
which increments at the end of each cycle. In
searches, data byte compariso'ns with the
match byte are made during the read cycle of
the next byte. Matches are, therefore, discovered only after the next byte is read in.
In multiple-DMA configurations, i'riterruptrequest daisy chains are prioritized by the
order in which their IEI and IEO lines are con,
nected (Zilog Application Note 03-0041-01, The
Z-80 Family Program Interrupt Structure). !he
WR3
Base register byte
Mask byte
Match byte
WR4
Base register byte
Port B starting address (low byte)
Port B starting address (high byte)
Interrupt control byte
Pulse control byte
Interrupt vector
WR5
Base register byte
WR6
Base register byte
Read mask
RRO
Status byte
RRI
Byte counter (low byte)
Read Registers
RR2
Byte counter (high byte)
RR3
Port A address counter (low byte)
RR4
Port A address counter (high byte)
RR5
Port B address counter (low byte)
RR6
Port B address counter (high byte)
COMMON:
iNT
BUSREQ
, - - - - - - - - 1 BUSACK
Mi
CPU
10RQ
MREQ
Wli
ClK
FROM HIGHER·PRIORITY
INTERRUPTING DEVICE
TO LOWER·PRIORITY
INTERRUPTING DEVICE
FROM
110
DEVICE
FROM
110
DEVICE
Figure 7. Multiple-DMA Interconnection to the Z-80 CPU
32
2032-0131
Programming
The Z-80 DMA has two programmable fundamental states: (1) an enabled state, in which
it can gain 'control of the system buses and
direct the transfer of data between ports, and
(2) a disabled state, in which it can initiate
neither bus requests nor data transfers. When
the DMA is powered up or reset by any means,
it is automatically placed into the disabled
state. Program commands can be written to it
by the CPU in either state, but this automatically puts the DMA in the disabled state,
which is maintained until an enable command
is issued by the CPU. The CPU must program
the DMA in advance of any data search or
transfer by addressing it as an I/O port and
sending a sequence of control bytes using an
Output instruction (such as OTIR for the
Z-80 CPU).
Writing. Control or command bytes are written into one or more of the Write Register
groups (WRO-WR6) by first writing to the base
register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers
in a group are sequentially accessed by first
writing a byte to the base register containing
register-group identification and pointer bits
(l's) to one or more of that base register's
associated registers.
This is illustrated in Figure 8b. In this
figure, the sequence in which associated
registers within a group can be written to is
shown by the vertical position of the associated
registers. For example, if a byte written to the
DMA contains the bits that identify WRO (bits
DO, D I and D7), and also contains l's in the
bit positions that point to the associated "Port
A Starting Address (low byte)" and "Port A
Starting Address (high byte)," then the next
two bytes written to the DMA will be stored in
these two registers, in that order.
Reading. The Read Registers (RRO-RR6) are
read by the CPU by addressing the DMA as an
I/O port using an Input instruction (such as
INIR for the Z-80 CPU). The readable bytes
contain DMA status, byte-counter values, and
port addresses since the last DMA reset. The
registers are always read in a fixed sequence
beginning with RRO and ending with RR6.
However, the register read in this sequence is
determined by programming the Read Mask in
WR6. The sequence of reading is initialized by
writing an Initiate Read Sequence or Set Read
Status command to WR6. After a Reset DMA,
the sequence must be initialized with the
Initiate Read Sequence command or a Read
Status command. The sequence of reading all
registers that are not excluded by the Read
Mask register must be completed before a new
Initiate Read Sequence or Read Status
command.
Fixed-Address Programming. A special circumstance arises when programming a destination port to have a fixed address. The load
command in WR6 only loads a fixed address to
a port selected as the source, not to a port
selected as the destination. Therefore, a fixed
destination address must be loaded by temporarily declaring it a fixed-source address
and subsequently declaring the true source as
such, thereby implicitly making the other a
destination.
The following example illustrates the steps in
this procedure, assuming that transfers are to
occur from a variable-address source (Port A)
to a fixed-address destination (Port B):
1. Temporarily declare Port B as source in
WRO.
2. Load Port B address in WR6.
3. Declare Port A as source in WRO.
4. Load Port A address in WR6.
S. Enable DMA in WR6.
Figure 9 illust~ates a program to transfer
data from memory (Port A) to a peripheral
device (Port B). In this example, the Port A
memory starting address is 10S0H and the Port
B peripheral fixed address is OSH. Note that·
the data flow is I 00 1H bytes-one more than
specified by the block length. The table of
DMA commands may be stored in consecutive
memory locations and transferred to the DMA
with an output instruction such as the Z-80
CPU's OTIR inst~uction.
Read Register 0
Read Register 2
0, D. Os 0, 0 3 0, 0, Do
1X 1X 1 I 1 1xiii
Iii
I
I
a1 ==
a=
a=
a=
L..I
DMA TRANSFER HAS OCCURRED
READY ACTIVE
INTERRUPT PENDING
MATCH FOUND
END OF BLOCK
BYTE COUNTER (LOW BYTE)
Read Register 3
11....-11....-1....1_II......IL....-JI~___-...II
PO,RT A ADDRESS COUNTER (LOW BYTE)
Read Register 4
11...-1....1-1-1-1-1_IL....-JI~L....-J--II PORT A ADDRESS COUNTER (HIGH BYTE)
Read Register 1
II....-II....-II....-IL....-JIL....-JIL....-JL....-J-...II
....J....I....J....I....J....I-"-I_IL....-J___:....-..II
STATUS BYTE
BYTE COUNTER (HIGH BYTE)
Read Register 5
II...-II...-II....-I'--IIL....-JIL....-JL....-J-...II
PORT B ADDRESS COUNTER (LOW BYTE)
Read Register 6
-1-1-1-1-1-1.....1.-1-.:IL--IL....-J--II
LI
PORT B ADDRESS COUNTER (HIGH BYTE)
Figure 8a. Read Registers
2032-0132
33
Programming
Write Register 4 Group
Wrlle Register 0 Group
0, 0, 0, D. 0, 0, 0,
(Continued)
I0 1
Do
0, 0, 0, D. 0, 0, 0,
I BASE REGISTER BYTE
1 1 1 1 1 1
!
I
!
I
11 1 1 1 1
Do
10 11
I BASE REGISTER BYTE
J1
DO NOT USE
o
1" TRANSFER
1
1
0 " SEARCH
1" SEARCHITRANSFER
BYTE
CONTINUOUS" 0
BURST" 1
DO NOT PROGRAM .. 1
0" PORT B -PORT A
1 = PORT A -PORT B
1
0
1
...-.,...-..,........-L..,........,....t...,.--...,...-.
PORT B STARTING ADDRESS
L-..I.-...L-..l-,-..l..y...J-..J--L.....J (LOW BYTE)
.--.......,.......,..........,......,..-..,..-...,.---, PORT A STARTING ADDRESS
L..-......................-'--'--'-........... (LOW BYTE)
...-.,...-..,..-...-L..,........,.--...,.--...,...-. PORT B STARTING ADDRESS
r-...,..-I-,-J~L..r-...,......,...--r....., PORT A STARTING ADDRESS
L-..I.-...L-..l-,-...l-..J.....-L..-L.....J (HIGH BYTE)
L-J...,.~...L-...L-...I--...I---L..-J (HIGH BYTE)
L..-~~~~~~--'
.--.......,.........,..-..,.--..,.--...,.--...,.---, BLOCK LENGTH
INTERRUPT CONTROL BYTE
L..-"-rJ...-.L-...L--'--'--'--' (LOW BYTE)
....-.........--..--..--..,..-..,.......,.---, BLOCK LEN GTH
L-J...-..I.-...L-...L-..J......I---'-..... (HIGH BYTE)
Write Register 1 Group
L.....J--J.-.I..........--'---'-......L..-J
0, 015 Os 0, 0] 02 D1 00
I0 1
1 1 1 11 10 10
I 1
o 0
o 1
~
~
1"=
I BASE REGISTER BYTE
PORT A IS MEMORY
=!
VECTOR IS AUTOMATICALLY
MODIFIED AS SHOWN
ONLY IF "STATUS
AFFECTS VECTOR" BIT IS SET
1
PORT A IS 110
= PORT A ADDRESS DECREMENTS
= PORT A ADDRESS INCREMENTS
I=
I
PORT A VARIABLE TIMING BYTE
I 11 1=
ENDS V. CYCLE EARLY
Ali ENDS 'fa CYCLE EARLY = 0
MREQ ENDS 'fa CYCLE EARLY" 0
{OI 0I
0
1
1
1
0
1
PORT A ADDRESS FIXED
~'----l---'---l..---'---'--'--"'"
WR
1--'--'-.1.--'---'---1-...............
INTERRUPT VECTOR
"INTERRUPT ON ROY
"INTERRUPT ON MATCH
"INTERRUPT ON END OF BLOCK
"INTERRUPT ON MATCH
AND END OF BLOCK
Write RegisterS Group
0, D. 0, D. 0, 0, 0,
=
PULSE CONTROL BYTE
Do
11 10 1 , 1 10 11 , 0 I BASE REGISTER BYTE
CYCLE LENGTH
4
0 1" CYCLE LENGTH a 3
1 0 = CYCLE LENGTH .. 2
DO NOT USE
1 1
o " l"OiiQ ENDS 'I. CYCLE EARLY
II I"
=
1~
o ..
READY ACTIVE LOW
READY ACTIVE HIGH
O .. CEONLY
1
CElWAIT MULTIPLEXED
=
STOP ON END OF BLOCK
1 = AUTO RESTART ON END OF BLOCK
Write Register 2 Group
0, D. 0, D. 0, 0, 0, Do
I0 1
1 1 1 10 10 10
I
1"
1
~
~
o
o
0
1
IBASE REGISTER BYTE
Write Register 6 Group
0, D. 0, D. 0, 0, 0,
PORT B IS MEMORY
1 " PORT B IS 110
PORT B ADDRESS DECREMENTS
"PORT B ADDRESS INCREMENTS
I-
I
11 1
=
I
1 1
IIIII
HEX
0= C3 =
1
C7
o " CB =
PORT B ADDRESS FIXED
=
L-..I.-...L-..J......l-...I--...J-........-J PORT B VARIABLE TIMING BYTE
Wii ENDS 'I.
Iili
a
0
CYCLE LENGTH" 4
1 = CYCLE LENGTH .. 3
0" CYCLE LENGTH" 2
1
DO NOT USE
0" Rilm ENDS Va CYCLE· EARLY
1
0
1
1
= AF = DISABLE INTERRUPTS
o ~ AB " ENABLE INTERRUPTS
o = A3 = RESET AND DISABLE INTERRUPTS
1 = B7 = ENABLE AFTER RETI
1
Write Register 3 Group
0, 0, 0, D. 0, 0, 0,
J
I
DMA ENABLE a
INTERRUPT ENABLE" 1
1 10
o
o
Do
, 0
1BASE REGISTER BYTE
= BF = READ STATUS BYTE
1
0
0
1
1
0
8B = REINITIALIZE STATUS BYTE
= A7 = INITIATE READ SEQUENCE
0 = B3 = FORCE READY
1
1
= 87 = ENABLE DMA
o = 83 = DISABLE DMA
J"
r-
STOP ON MATCH
L-...L--'-~""""""""-'-~"'"
0
Llc"," 1
MASK BYTE (0
a
1 1 1 0 = BB = READ MASK FOLLOWS
I I 1 1 I I READ MASK (1 = ENABLE)
IIIII
COMPARE)
•
I--'--'--J.........--,O--'-.............
MATCH BYTE
Figure
34
RESET PORT B TIMING
o = 03 = CONTINUE
o=
11 1 1 1
COMMAND NAME
RESET
= RESET PORT A TIMING
1 = CF = LOAD
I I 11 !"
CYCLE EARLY,,!
EN OS 'I. CYCLE EARLY = 0
~ ENDS 'I. CYCLE EARLY
Do
11 11 1BASE REGISTER BYTE
ab.
~STATUSBYTE
~~i~ gg~~i~= l~?~
PORT
PORT
PORT
PORT
A ADDRESS
A ADDRESS
B ADDRESS
B ADDRESS
BBYYW)
(LOW BYTE)
(HIGH BYTE)
(LOW BYTE)
(HIGH BYTE)
Write Registers
2032·0132
~
.........
~
0 ...
o 0
w
~
6
~lQ
W
::::3
w
§ 8
~B
-6'
lQ
Comments
07
06
05
04
03
02
01
WRO sets DMA to receive
block length, Port A starting address and temporarily
sets Port B as source.
a
1
Block Length
Upper
Follows
1
Block Length
Lower
Follows
1
Port A
Upper
Address
Follows
1
Port A
Lower
Address
Follows
a
a
Port A address (lower)
a
a
1
0
a
a
a
a
a
a
a
a
00
Block length (upper)
a
a
a
a
50
Block length (lower)
a
a
a
a
0
a
a
a
a
a
a
a
1
Port A address (upper)
WR1 defines Port A as
memory with fixed
incrementing address.
a
a
a
a
1
a
14
No Timing
Follows
a
Address
Changes
WR2 defines Port B as
peripheral with fixed
address.
a
a
1
Fixed
Address
a
1
a
28
No Timing
Follows
WR4 sets mode to Burst,
sets OMA to expect Port B
address.
1
1
a
1
Port BLower
Address
Follows
a
1
C5
Port B address (lower)
a
a
WR5 sets Ready active High.
1
0
No Auto
Restart
1
a
1
1
1
WRO sets Port A as source. *
a
a
0
1
WR6 enables OMA to start
operation.
--
--
1
-
---
---
Temporary
for
Loading B
Address*
1
Port is
10
a
a
No Upper
Address
a
a
a
1
a
1
05
a
0
a
1
a
8A
No Wait
States
1
ROY
Active High
a
0
1
1
1
1
CF
a
a
a
1
A ----..B
0
1
Transfer, No Search
05
a
1
1
a
a
1
a
a
0
- - - - - - ------
_._-
'-----
-
1
1
--
1
--
'---
--
vEla 081
\
10
110
Figure 9, Sample DMA Program
CJ1
79
Transfer, No Search
NOTE: The actual number of bytes transferred is one more than specified by the block length.
*These entries are necessary only in the case of a fixed destination address.
c.u
HEX
1
Port is
Memory
No Address or Block
Length Bytes
WR6 loads Port A address
and resets block counter.
B~A
Do
No Interrupt
Control Byte
Follows
Burst Mode
WR6 loads Port B address
and resets block counter.*
1
Address
Increments
I
--
1
CF
1
87
Inactive
In its disabled or inactive state, the DMA is
State Timing addressed by the CPU as an 1/0 peripheral for
(DMA as CPU write and read (control and status) operations.
Peripheral)
Write timing is illustrated in Figure 10.
Reading of the DMA's status byte, byte
, counter or port address counters is illustrated
in Figure 11. These operations require less
than three T-cycles. The CE, 'IORQ and
RD lines are made active over two rising edges
of CLK, and data appears on the bus approximately one T-cycle after they become active.
\
C:~~1-----
lORa
WR
Do-D7
-----
-_-1-_--+__
.
Figure 10. CPU-to-DMA Write Cycle
Figure 11. CPU-to-DMA Read Cycle
Active State Default Read and Write Cycles. By default,
Timing
and after reset, the DMA's timing of read and
(DMA as Bus .write operations is exactly the same as the 2-80
Controller)
CPU's timing of read and write cycles for
,memory and 1/0 peripherals, with one exception: during a read cycle, data is latched on
the falling edge of T3 and held on the data bus
across the boundary between read and write
cycles, through the end of the following write
cycle.
Figure 12 illustrates the timing for memoryto-I/O port transfers and Figure 13 illustrates
I/O-to-memory transfers. Memory-to-memory
and I/O-to-I/O transfer timings are simply permutations of these diagrams.
The default timing uses three T-cycles for
memory transactions and four T-cycles for 1/0
transactions, which include one automatically
I - MEMORY READ
I T, I T2 I
inserted wait cycle between T2 and T3. If the
CE/WAIT line is programmed to act as a
WAIT line during the DMA's active state, it is
sampled on the falling edge of T2 for memory
transactions and the falling edge of Tw for 1/0
transactions. If CE/WAIT is Low during this
time another T-cycle is added, during which
the CE/,WAIT line will again be sampled. The
duration of transactions can thus be indefinitelyextended.
Variable Cycle and Edge Timing. The 2-80
DMA's default operation-cycle length for the
source (read) port and destination (write) port
can be independently programmed. This
variable-cycle feature allows read or write
cycles consisting of two, three or four T-cycles
(more if Wait cycles are inserted), thereby
increasing or decreasing the speed of all
signals generated by the DMA. In addition,
_1. .
- - - - 1 / 0 WRITE - - - .. 1
T3
T,
T2
Tw
T3
eLK
Ao-A15
..mEa
READ {
RD
lona
WROTE {
wn
Do-D7
CElWAIT
Figure 12. Memory-to-I/O Transfer
36
2032-0134, 0135, 0136
Active State'
Timing
(DMA as Bus
Controller)
(Continued)
,....- - - - 1 1 0 READ - - - _
Tl
T2
eLK
!X
Ao-A15
~.{
I
IORQ
RO
\
I
'-
I
~
00-07
110 DRIVES DATA
T
,
DMA DRIVES DATA BUS
\
r-
\
UREQ
WIDTE{
'- W
WR
CEJWAIT
I
-
~--
.... --
.... -- ~-- r;J
II
o
----- -rt ----- --- iJrt ---
tI
=
Figure 13. 1I0-to-Memory Transfer
the trailing edges of the IORQ, MREQ, RD and
WR signals can be independently terminated
one-half cycle early. Figure 14 illustrates this.
In the variable-cycle mode, unlike default
timing, IORQ comes active one-half cycle
before MREQ, RD and WR. CE/WAIT can be
used to extend only the 3 or 4 T-cycle variable
. memory cycles and only the 4-cycle variable
I/O cycle. The CE/WAIT line is sampled at the
falling edge of T2 for 3- or 4-cycle memory
cycles, and at the falling edge of T3 for 4-cycle
1/0 cycles.
During transfers, data is latched on the
clock edge causing the rising edge of RD and
held through the end of the write cycle.
I
CLK
&0-&..
I
T,
~R~
T,
I
T.
I
SUL..JLrUL
""-~-t""~
CLK
L_ L_ ',-_
.ORQ'
RD, WR
I
T,
Bus Requests. Figure 15 illustrates the bus
request and acceptance timing. The RDY line,
which may be programmed active High or
Low, is sampled on every rising edge of CLK.
If it is found to be active, and if the bus is not
in use by any other device, the follOWing rising
edge of CLK drives BUSREQ low. After receiv~ BUSREQ the CPU acknowledges on the
BAI input either directly or through a
multiple-DMA daisy chain. When a Low is
detected on BAI for two consecutive rising
edges of CLK, the DMA will begin transferring
data on the next rising edge of CLK.
-----"l
r-r-I I
--
r
-r- -,-
--
t
3·CYCLE
-,-
\.--.L....L-...L2·CYCLE
t .t·
,,·CYCLE
- - - - - --1
- r!----.,'!-,,J
iii -______
D"A
INACTIVE
D'"
ACTIVE
EARLY END EARLY END EARLY END
Figure 14. Variable-Cyclo and Edge Timing
2032-0137, 0138, 0139
Figure 15. Bus Request and Acceptance
37
Active State
Timing
(DMA as Bus
Controller)
( Continued)
Bus Release Byte-at-a-Time. Irt~yte-at-a
Time mode, BUSREQ is brought High-on the
rising, edge of CLK prior to the end of each
read cycle (search-only) or write cycle
(transfer and transfer/search) as illustrated in
Figure 16. This is done regardless of the state
of RDY. There is no possibility of confusion
when a 2-80 CPU is used since the CPU
cannot begin an operation until the following
T-cycle. Most other CPUs are not bothered by
this either, although note should be taken of it.
The next bus reguest for the next byte will
come after both BUSREQ and BAI have
returned High.
Bus Release at End of Block. In Burst and
Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Figure 17). The last
byte i~ the block is transferred even if RDY
goes inactive before completion of the last byte
transfer.
Bus Release on Not Ready. In Burst mode,
when RDY goes inactive it causes BUSREQ to
go High on the next rising edge of CLK after
the completion of its current byte operation
(Figure 18). The action on BUSREQ is thus
somewhat delayed from action on the RDY
line. The DMA always completes its current
byte operation in an orderly fashion before
releasing the b=u..",.s."..,.==-==
By contrast, BUSREQ is not released in
Continuous mode when RDY goes inactive.
Instead, the DMA idles after completing the
current byte operation, awaiting an active RDY
again.
Bus Release on Match. If the DMA is programmed to stop on match in Burst or Continuous modes, a match causes BUSREQ to go
inactive on the next DMA operation, Le., at
the end of the next read in a search or at the
end of the follOWing write in a transfer (Figure
19). Due to the pipelining scheme, matches
are determined while the next DMA read or
write is being performed.
The RDY line can go inactive after the
matching operation begins without affecting
this bus-release timing.
Interrupts. Timings for interrupt acknowledge
and return from interrupt are the same as timings for these in other 2-80 peripherals. Refer
to 2ilog Application Note 03-0041.-01 (The Z-aD
Family Program Interrupt Structure).
Interrupt on RDY (interrupt before requesting bus) does not directly affect the BUSREQ
line. Instead, the interrupt service routine
must handle this by issuing the follOWing
commands to WR6:
1. Enable after Return From Interrupt (RETD
Command - Hex B7
2. Enable DMA - Hex 87
3. An RET! instruction that resets the
Interrupt Under Service latch in the
2-80 DMA~
CLK~1....r1.JLJLJL
I~._ _ _ _-
BUSREQ
B.ii
-
•
RDY
I
I (,CJJ
_ _ _--HI
I'
.
DMA ACTIVE _ \ - DMA INACTIVE
Figure 16. Bus Release (Byte-at-a-Time Mode)
Figure 17. Bus Release at End of Block
(Burst and Continuous Modes)
ACTIVE
RDY
_CTlVE
~~--~-------
rc
RDY
INACTIVE
BUSREQ
L~CURRENT BYTE~
r----
OPERATION
DMA
-~I-- INACTIVE
--------~.~----------~:~----~
f--
BYTEA _ _-;'~I_'
READ IN
_
8YTEn+1
READ IN
AND
MATCH FOUND
ON BYTE"
Figure 18. Bus Release When Not Ready
(Burst Mode)
38
Figure 19. Bus Release on Match
(Burst and Continuous Modes)
2032-0140,0141,0142,0143
Absolute
Maximum
Ratings
Operating Ambient
Temperature Under Bias ... As Specified Under
Ordering Information.
Storage Temperature ........ -65°e to + 150 0 e
Voltage On Any Pin with
Respect to Ground .......... -0.3 V to + 7.0 V
Power Dissipation .................... 1.5 W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of.the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
o
C S* = ooe to + 70 e,
+4.75 V =:; Vee =:; "!-5.25 V
EJ E* = - 40 0 e to + 85°e,
+4.75 V =:; Vee =:; +5.25 V
EJ M* = -55°e to + l25°e,
+4.5 V =:; Vee =:; +5.5 V_
All ac parameters assume a load capacitance
of 100 pF max. Timing references between two
output signals assume a load difference of 50
pF max.
+5V
2.1K
·See Ordering Information section for package
temperature range and product number.
DC
Characteristics
Symbol
Parameter
VILe
VIHe
VIL
Min
Max
Clock Input Low Voltage
-0.3
0.45
V
Clock Input High Voltage
Vee -·6
5.5
V
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
5.5
V
VOL
Output Low Voltage
0.4
V
loL = 3.2rnA for BUSREQ
IOL = 2.0 rnA for- all others
VOH
Output High Voltage
V
IOH
= 250 JlA
Icc
Power Supply Current
2-80 DMA
2-80A DMA
= 0 to Vee
= 0.4 V to Vee
rnA
rnA
10
Input Leakage Current
3-State Output Leakage Current in Float
±1O
~
JlA
VIN
ILO
ILD
Data Bus Leakage Current in Input Mode
±10
JlA
OsVINsVec
= 5
Symbol
VO UT
V ± 5% unless otherwise specified, over speCified temperature range.
Parameter
Min
Max
Unit
Test Condition
C
Clock Capacitance
35
pF
Unmeasured Pins
C IN
Input Capacitance
5
pF
Returned to Ground
C OUT
Output Capacitance
10
pF
Over specified temperature range; f
8085-0209
150
200
ILl
Vee
Capacitance
2.4
Unit Test Condition
= I
MHz
39
Inactive
State
AC
Characteristics
Number Symbol
Parameter
TcC
Clock Cycle Time
TwCh
Clock Width (High)
2
TwCl
Clock Width (Low)
3
Clock Rise Time
4
TrC
Clock Fall Time
- 5-TfC
Th
Hold Time for Any Specified Setup Time
6
TsC(Cr)
IORQ, WR, CE I to Clock , Setup
7
TdDO(RDf)
RDl to Data Output Delay
8
TsWM(Cr)
9
Data In to Clock' Setup (WR or Ml)
-10- TdCf(DO) --IORQ I to Data Out Delay (INTA Cycle)
TdRD(Dz)
RD , to Data Float Delay (output buffer
11
disable)
TsIEI(lORQ)
IEII to IORQ I Setup (INTA Cycle)
12
TdIEOr(lElr)
13
lEI I to lEO I Delay
TdIEOf(lEIf)
14
lEI I to lEO I Delay
_15_TdMl(1EO)_Ml I to lEO I Delay (interrupt just prior to
Mll)
TsMlf(Cr)
16
Ml I to Clock I Setup
TsMlr(C£)
17
Ml I to Clock I Setup
TsRD(Cr)
RD I to Clock I Setup (Ml Cycle)
18
Tdl(lNT)
19
Interrupt Cause to INT I Delay (INT generated
only when DMA is inactive)
_20 _ TdBAlr(BAOr)_BAI 'to BAO , Delay
TdBAIf( BAO£) BAI I to BAO I Delay
21
22
TsRDY(Cr)
RDY Active to Clock I Setup
NOTE:
I, Negative minimum setup values mean that the
40
lirst-mention~d
Z-80 DMA
Z-80A DMA
Min
Max
Min
Max
400
170
170
4000
2000
2000
30
30
250
110
110
ns
4000
2000
ns
2000
ns
ns
30
30--nsns
ns
380
ns
ns
160--ns-
0
280
0
145
500
50
50
340
160
140
110
140
210
190
160
130
300
210
20
240
190
90
-10
115
500
200
200
150
100
event can come alter the second-mentioned event.
Unit
ns
ns
ns
ns
ns
ns '
ns
ns
500
ns
150--ns_
150
ns
ns
Inactive
State
AC
Characteristics
CLOCK
OUTPUT
INPUT
"1"
"0"
4.2 V 0.' V
2.0 V 0.8 V
2.0 V 0.1 V
CLK
(Continued)
00-07
ii1
II0
lEI
tI
=
lEO
INT
INTERRUPT
CONDITION
DAI
BAD
ACTIVE
ROY
INACTIVE
NOTE:
Signals in this diagram bear no relation to one another unless specifically noted as a numbered item.
2032-0144
41·
Active
Number Symbol
State
AC
TcC
CharacterTwCh
2
istics
TwC1
3
4
TrC
5-TfC
6
Parameter
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
Z-80 DMA
Min{ns)
Max{ns)
400
180
180
30
Clock Fall Time
30
Address Output Delay
145
Clock t to Address Float Delay
110
7
TdA
TdC(Az)
8
TsA(MREQ) Address to MREQ I Setup (Memory Cycle) (2) + (5)-75
9
TsA(IRW)
*10-TdRW(A)-RD, WR t to Addr. Stable Delay
*11
TdRW(Az) RD, WR t to Addr. Float
TdCf(DO)
Clock I to Data Out Delay
12
*13
TdCr(Dz)
Clock t to Data Float Delay (Write Cycle)
14
TsDI(Cr)
Data In to Clock t Setup (Read cycle when
rising edge ends read)
Data In to Clock I Setup (Read cycle when
falling edge ends read)
15 -TsDl(Cf) -
250
2000
2000
Clock Rise Time
Address Stable to IORQ, RD, WR I Setup
(I/O Cycle)
*16
TsDO(WfM) Data Out to WR I Setup (Memory Cycle)
17
*18
TsDO(WfI)
Data Out to WR I Setup (I/O cycle)
TdWr(DO)
WR t to Data Out Delay
Th
Hold Time for Any Specified Setup Time
19
20-TdCr(Mf)-Clock I to MREQ I Delay
Z-80A DMA
Min{ns)
Max{ns)
110
110
30
30110
90
(2) + (5)-75
(1)-80
(1)-70
(3) + (4)-40
(3) + (4)-60
(3) + (4)-50
(3) + (4)-45
230
150
90
90
50
35
60
(1)-210
50
(1)-170
100
(3) + (4)-80
(3) + (4)-70
100
0
0
100
85-
21
TdCf(Mf)
Clock I to MREQ I Delay
100
85
22
23
TdCr(Mr)
TdCf(Mr)
Clock I to MREQ I Delay
100
100
85
Clock I to MREQ t Delay
MREQ Low Pulse Width
24
TwMl
*25-TwMh--MREQ High Pulse Width
85
(1)-40
(1)-30
(2) + (5)-30
(2) + (5)-20
26
TdCf(lf)
Clock I to IORQ I Delay
110
85
27
TdCr(lf)
TdCr(lr)
Clock I to IORQ I Delay
Clock t to IORQ t Delay
90
100
75
85
TdCf(lr)
Clock I to IORQ I Delay
110
85
85-
28
*29
30-TdCr(Rf)-Clock t to RD I Delay
100
Clock I to RD I Delay
130
95
Clock t to RD I Delay
100
110
85
31
32
TdCf(Rf)
TdCr(Rr)
TdCf(Rr)
Clock I to RD I Delay
33
TdCr(Wf)
Clock I to WR I Delay
34
35-TdCf(Wf)-Clock I to WR I Delay
36
37
TdCr(Wr)
TdCf(Wr)
85
80
90
65
80-
100
Clock I to WR t Delay
Clock I to WR I Delay
WR Low Pulse Width
TwWl
38
WAIT to Clock I Setup
TsWA(Cf)
39
40-TdCr(B)-Clockl to BUSREQ Delay
TdCr(lz)
Clock t to IORQ, MREQ, RD, WR Float
41
Delay
80
80
100
(1)-30
(1)-40
70
70
150
100
NOTES:
I. Numbers in parentheses are other parameter·numbers in this taQle; their values should be substituted in equations.
2. All equations imply DMA default (standard) liming.
3. Data must be enabled onto data bus when RD is active.
4. Asterisk (') before parameter number means the parameter is not illustrated in the AC Timing Diagrams.
42
2000
2000
10080
Active
State
AC
eLK
Character-
istics
(Continued)
Ao-At5
INPUT
Do-D7 { OUTPUT
--+-oH----++------++-----+----H...,.
MREQ
N
00
0
I
iii)
WR
IORQ
iii)
WR
WAIT
BUSREQ
NOTE:
Signals in this diagram bear no relation to one another unless specifically noted as a numbered item.
2032-0145
43
Ordering
Information
Product
Number
Description
(40~pin)
Product
Number
Package/
Temp
Speed
PE
2.5 MHz
Description
Z8410
CE
2.5 MHz
ZSO DMA
Z8410
CM
2.5 MHz
Same as above
Z8410
PS
2.5 MHz
Same as above
Z8410
CS
2.5 MHz
Same as above
Z8410A
CS
4.0 MHz
ZSOA DMA (40-pin)
Z8410
DE
2.5 MHz
Same as above
Z8410A
DS
4.0 MHz
Same as above
Z8410
DS
2.5 MHz
Same as above
Z8410A
PS
4.0 MHz
Same as above
'NOTES: C
44
Package/
Speed
Temp
= Ceramic,
D
= Cerdip,
P
= Plastic;
E
= -40°C to
Z8410
+85°C, M = -55°C to + 125°C, S
= O°C to
Z80 DMA (40-pin)
+70°C.
00-2032-02
Z8420
Z80® PIC Parallen
input/Output Conun[(-~ - - - - - ~-!~ ~{___J~r--------------------
00- 0 7
II
o
S
-----------------...{~DA:_;;TA;_;;IN;_\.)- - - - - - - - - - - - - - - - -
• Timing Diagram Refers to Bit Mode Read
t.
DATA WORD 1 PLACED ON BUS
Figure 17. Mode 3 Bit Mode Timing
Interrupt Acknowledge Timing. During Ml
time, peripheral controllers are inhibited from
changing their interrupt enable status, permitting the Interrupt Enable signal to ripple
through the daisy chain. The peripheral with
lEI High and IEO Low during INTACK places
a preprogrammed 8-bit interrupt vector on the
data bus at this time (Figure 18). IEO is held
Low until a Return From Interrupt (RET!)
instruction is executed by the CPU while lEI is
High. The 2-byte RETI instruction is decoded
internally by the PIO for this purpose.
'
~ri
I I I I I I
T,
T,
TIlA
T..
T.
eLK
,..--___
IORQ AND M1
INDICATE
INTERRUPT
} ACKNOWLEDGE
INTACK
lEO
lEI
Figure 18. Interrupt Acknowledge Timing
Return From Interrupt Cycle. If a 2-80 peripheral has no interrupt pending and is not
under service, then its IEO = lEI. If it has an
interrupt under service (i.e., it has already
interrupted and received an interrupt acknowledge) then its IEO is always Low, inhibiting
lower priority devices from interrupting. If it
has an interrupt pending which has not yet
been acknowledged, IEO is Low unless an
"ED" is decoded as the first byte of a 2-byte
opcode (Figure 19). In this case, lEO goes
High until the next opcode byte is decoded,
whereupon it goes Low again. If the second
byte of the opcode was a "4D," then the
opcode was an RET! instruction.
After an "ED" opcode is decoded, only the
peripheral device which has interrupted and is
currently under service has its lEI High and its
lEO Low. This device is the highest-priority
device in the daisy chain that has received an
interrupt acknowledge. All other peripherals
have IEI = IEO. If the next opcode byte
decoded is "4D," this peripheral device resets
its "interrupt under service" condition.
T,
T,
T.
T,
T,
T,
T,
T.
T,
eLK
iii1\
1
'----I
iffi
00-07
~
~
1
110 _ _ _ _ _ _ _ _ _ _ _----,----,_ _ _ _ _
Figure 19. Return From Interrupt
2006-0329, 0330, 0331
53
AC
Characteristics
CLOCK
CE
B/i,C/6
iiD,lORQ
Do-D7
{OUT
IN
--------------~~
----f-----.."Jt----+-------.J. r--II-+-----+----
------------~----,~-----+----------------~
lEI
lEO
READY
(ARDY OR BRDY)
5TRoiiE
(ASTB OR BSTB)
MODED
MODE1
MODE2
MODE3
54
2006-0332
Z-BO PIO
Max
Min
Z-BOA PIO
Max
Z-BOB PIO[9]
Min Max
(ns)
(ns)
(ns)
(ns)
(ns)
[ 1)
250
105
105
[ 1)
2000
2000
30
30
1"65
65
65
[ 1)
2000
2000
20
20
Min
Number Symbol
Parameter
(ns)
Clock Cycle Time
400
Clock Width (High)
170
Clock Width (Low)
170
Clock Fall Time
Clock Rise Time
CE, BIA, CIO to RD,
IORQ I Setup Time
50
7
Th
Any Hold Times for Specified
Setup Time
0
TsR1(C)
8
RD, IORQ to Clock t Setup
Time
115
9 -TdR1(DO) --RD, IORQ Ito Data Out Delay
TdR1(DOs)
10
RD, IORQ t to Data Out Float
Delay
TsD1(C)
11
Data In to Clock t Setup Time
50
12
TdIO(DOl)
IORQ I to Data Out Delay
(INTACK Cycle)
13 -TsMl(Cr) --MI I to Clock t Setup Time--21O
TsMl(Cf)
14
MI.-Lto Clock I Setup Time
(MI Cycle)
0
TdMl(IEO)
15
MI I to IEO I Delay (Interrupt
Immediately Preceding MI I)
TsIEI(IO)
16
lEI to IORQ I Setup Time
(INTACK Cycle)
140
17 -TdIEI(IEOf)- lEI I to IEO I Delay
1
TcC
TwCh
2
3
TwCl
4
TfC
5-TrC
TsCS(Rl)
6
IEI t to IEO t Delay (after ED
Decode)
TcIO(C)
19
IORQ t to Clock I Setup Time
(To Activate READY on Next
Clock Cycle)
20 -TdC(RDYr)-·- Clock I to READY t Delay
18
2000
2000
30
30
50
50
0
0
115
430
CL
70
0
0
190
24
25
26
27
28
29
~
fI::!I
[5,7]
100
100
190
130
120
210
160
160
(7)
[5)CL = 50 pF
TdIEI(IEOr)
200
220
200
[5]
170
190
[5]-
170
TdC(RDYf)
TwSTB
TsSTB(C)
Clock I to READY I Delay
STROBE Pulse Width
150
STROBE t to Clock I Setup
Time (To Activate READY on
220
Next Clock Cycle)
-TdIO(PD)-- IORQ t to PORT DATA Stable
Delay (Mode 0)
TsPD(STB)
PORT DATA to STROBE t
Setup Time (Mode 1)
260
TdSTB(PD)
STROBE I to PORT DATA
Stable (Mode 2)
-TdSTB(PDr)- STROBE t to PORT DATA Float
Delay (Mode 2)
TdPD(INT)
PORT DATA Match to INT I
Delay (Mode 3)
TdSTB(INT)
STROBE I to INT I Delay
NOTES:
[IJ TcC = .TwCh + TwCI + TrC + TIC.
[2J Increase TdRI(DO) by 10 ns for each 50 pF increase in load
up to 200 pF max.
[3J Increase TdIO(DOI) by 10 ns for each 50 pF, increase in
loading up to 200 pF max.
[41 For Mode 2: TwSTB > TsPD(STB).
[5] Increase these values by 2 ns for each 10 pF increase in
loading up to 100 pF max.
= 50 pF
150
120
[5]
[4]
220
150
[5]
150
140
120
180
200
230
160
[5]
[5]
190
230
210
180
200
180
160
540
490
490
440
430
350
CL
r!'.J
CO
(3
e
[8)
CL
21
22
23
= 50 pF
[3)
120
90
140
[2)--
70
40
160
300
0
300
110
50
340
(6)
70
380
160
Comment
= 50 pF
[6J TsCS(RI) may be reduced. However, the lime subtracted
from TsCS(RI) will be added to TdR!(DO).
[7] 2.5 TcC > (N-2)TdIEI(IEOf) + TdMI(lEO) + TsIEI(IO)
.±... TTL Buffer Delay, if any.
[8] MI must be active for a minimum of two clo~k cycles to
reset the PI~.
[9] Z80B PIO numbers are preliminary and subject to change.
55
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As SpeCified in
Ordering Information
Storage Temperature ........ -65°C to +150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these speCifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Test
Conditions
The characteristics below apply for the
folloWing test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
m S* = O°C to + 70°C,
+4.75 V:5 Vee:5 +5.25 V
El E* = - 40°C to + 85°C,
+ 4.75 V :5 Vee:5 + 5.25 V
II M* = - 55°C to + 125°C,
+ 4.5 V :5 Vee:5 + 5.5 V
All ac parameters assume a load capacitance
of 100 pF max.
+5V
2.1K
·See Ordering Information section for package
temperature range and product number.
DC
Characteristics
Symbol
Parameter
Min
VILe
VIHe
Clock Input Low Voltage
VIL
VIH
Input Low Voltage
Input High Voltage
+2.0
VOL
VOH
ILl
ILO
Output Low Voltage
Output High Voltage
+2.4
lee
IOHD
Clock Input High Voltage
Max
-0.3
+0.45
Vee -0.6 Vee+ 0 .3
-0.3
+0.8
± 10.0
3-State Output Leakage Current in Float
± 10.0
Power Supply Current
Test Condition
V
V
V
V
Vee
+0.4
Input Leakage Current
Darlington Drive Current
Unit
100.0
-1.5
V
V
p.A
IOL = 2.0 rnA
IOH = -250 p.A
p.A
rnA
rnA
VOUT =0.4 V to Vee
VoH =1.5 V
REXT = 390 n
VIN = 0 to Vee
Over speCified temperature and voltage range.
Capacitance
Symbol
C
C IN
C OUT
Parameter
Clock Capacitance
Input Capacitance
Output Capacitance
Over specified te\Tlperalure range; f'= lMH z
56
Min
Max
Unit
10
pF
pF
pF
5
10
Test Condition
Unmeasured
pins returned
to ground
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Speed
Temp
Description
28420
CE
2.5 MHz
280 PIO (40-pin)
28420A
CMB
4.0 MHz
28420
CM
2.5 MHz
Same as above
28420A
CS
4.0 MHz
28420
CMB
2.5 MHz
Same as above
28420A
DE
4.0 MHz
280A PIO (40-pin)
Same as above
Same as above
28420
CS
2.5 MHz
Same as above
28420A
DS
4.0 MHz
Same as above
28420
DE
2.5 MHz
Same as above
28420A
PE
4.0 MHz
Same as above
28420
DS
2.5 MHz
Same as above
28420A
PS
4.0 MHz
Sa,me as above
28420
PE
4.0 MHz
Same as above
28420B
CS
6.0 MHz
Same as above
28420
PS
4.0 MHz
Same as above
28420B
DS
6.0 MHz
Same as above
28420A
CE
4.0 MHz
280A PIO (40-pin)
28420B
PS
6.0 MHz
Same as above
28420A
CM
4.0 MHz
Same as above
·NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -40°C to +85°C, M = -55°C to + 125°C, MB = 55°C to + 125°C with
MIL-STD·883 Class B processing, S = O°C to + 70°C.
I)i3
eo
0
'"
C::r.I
0
00-2006-02
57
18430
~80® CTC {C@Ulloofter/
~imer
Circuil
Product
Zilog
Specciiilcafti@ml
September 1983
Features
General
Description
IJ
Four independently programmable
counter/timer channels, each with a
readable downcounter and a selectable
16 or 256 prescaler. Downcounters are
reloaded automatically at zero count.
I'D
Three channels have 2ero Count/Timeout
outputs capable of driving Darlington
transistors.
The 2-80 CTC four-channel counter/timer
can be programmed by system software for a
broad range of counting and timing applications. The four independently programmable
channels of the 2-80 CTC satisfy common
microcomputer system requirements for event
counting, interrupt and interval timing, and
general clock rate generation.
System design is simplified because the CTC
connects directly to both the 2-80 CPU and the
2-80 SIO with no additional logic. In larger
systems, address decoders and buffers may be
required.
Programming the CTC is straightforward:
CPul~
DATA
BUS
CTC
CONTROL
FROM
CPU
-
--
1-
DAISY {
CHAIN
INTERRUPT
CONTROL
-
_
00
CLKITRGo
0,
ZCITOo
02
03
CLKITRG,
04
ZCITO,
CLKITRG2
07
ZCfT02
CE
CSo
CS,
mer
M1
lORa
R1i
lEI
I'J Interfaces directly to the 2-89 CPU or-for
baud rate generation-to the 2-80 S10.
each channel is programmed with two bytes; a
third is necessary when interrupts are enabled.
Once started, the eTC counts down, reloads
its time constant automatically, and resumes
counting. Software timing loops are completely
eliminated. Interrupt processing is Simplified
because only one vector need be speCified; the
CTC internally generates a unique vector for
each channel.
The 2-80 CTC requires a single + 5 V power
supply and the standard 2-80 single-phase
system/clock. It is fabricated with n-channel
silicon-gate depletion-load technology, and
packaged in a 28-pin plastic or ceramic DIP.
-
Os
06
Selectable positive or negative trigger
initiates timer operation.
E'J Standard 2-80 Family daisy-chain interrupt
structure prOVides fully vectored, prioritized
interrupts without external logic. The CTC
may also be used as an interrupt controller.
C
Z80 CTC
Z80A CTC
lEO
iNf
CHANNEL
SIGt.ALS
04
03
Os
02
06
0,
07
00,
GNO
+5V
RO
CLKlTRGo
ZC/TOo
CLKfTRG,
ZCITO,
CLKlTRG2
ZCIT02
CLKITRG3
lORa
CS,
lEO
CSo
iNT
RESET
lEI
CE
Mi
CLK
ttt
CLK +5V GNO
Figure 1. Pin Functions
2041-0154,0155
Figuro 2. Pin Assignmonts
59
Functional
Description
The Z-80 CTC has four independent counter/
timer channels. Each channel is individually
programmed with two words: a control word
and a time-constant word. The control word
selects the operating mode (counter or timer),
enables or disables the channel interrupt, and
selects certain other operating parameters. If
the timing mode is selected, the control word
also sets a pres caler , which divides the system
clock by either 16 or 256. The time-constant
word is a value from 1 to 256.
During operation, the individual counter
channel counts down from the preset time constant value. In counter mode operation the
counter decrements on each of the CLK/TRG
input pulses until zero count is reached. Each
decrement is synchronized by the system
clock. For counts greater than 256, more than
one counter ca~ be cascaded. At zero count,
the down-counter is automatically reset with
the time constant value.
The timer mode determines time intervals as
small as 4 /LS (Z-80A) or 6.4 /LS (Z-80) without
additional logic or software timing loops. Time
intervals are generated by diViding the system
clock with a prescaler that decrements
a preset down-counter.
Thus, the time interval is an integral multiple of the clock period, the prescaler value
'(16 or 256) and the time constant that is preset
in the down-counter. A timer is triggered automatically when its time constant value is 'programmed, or by an external CLK/TRG input.
Three channels have two outputs that occur
at zero count. The first output is a zerocount/timeout pulse at the ZC/TO output. The
fourth channel (Channel 3) does not have a
ZC/TO output; interrupt request is the only
output available from Channel 3.
The second output is'Interrupt Request
(lNT), which occurs if the channel has its
interrupt enabled during programming. When
the Z-80 CPU acknowledges Interrupt Request,
the Z-80 CTC places an interrupt vector on the
data bus.
The four channels of the Z-80 CTC are fully
prioritized and fit into four contiguous slots in
a standard Z-80 daisy-chain interrupt structure. Channel 0 is the highest priority and
Channel 3 the lowest. Interrupts can be
indiVidually enabled (or disabled) for each of
the four channels.
Architecture
The CTC has four major elements, as shown
in Figure 3.
Internal Control Logic. The CTC internal
control logic controls overa'll chip operating
functions such as the chip enable, reset, and
read/write logic.
Interrupt Logic. The interrupt control logic
ensures that the CTC interrupts interface properly with the Z-80 CPU interrupt system. The
logic controls the interrupt priority of the CTC
as a function of the lEI Signal. If IEI is High,
the CTC has priority. During interrupt
• CPU bus I/O
• Channel control logiC
• Interrupt logic
• Counter/timer circuits
CPU Bus 110. The CPU bus I/O circuit
decodes the address inputs, and interfaces the
CPU data and control signals.to the CTC for
distribution on the internal bus.
DATA
FROM
zeo CPU
{
CPU
BUS
110
CONTROL
ZCITO
CLKlTRG
Figure 3. Functional Block Diagram
60
2041-0157
Architecture
(Continued)
processing, the interrupt logic holds lEO Low,
which i'Ilhibits the interrupt operation on lower
priority devices. If the lEI input goes Low,
priority is relinquished and the interrupt logic
drives lEO Low.
If a channel is programmed to request an
interrupt, the interrupt logic drives lEO Low at
the zero count, and generates an INT signal to
the Z-80 CPU. When the Z-80 CPU responds
with interrupt acknowledge (M1 and IORQ),
then the interrupt logic arbitrates the CTC
internal priorities, and the interrupt control
logic places a unique interrupt vector on the
data bus.
If an interrupt is pending, the interrupt logic
holds lEO Low. When the Z-80 CPU issues a
Return From Interrupt (RET!) instruction, each
peripheral device decodes the first byte
(ED16)' If the device has a pending interrupt,
it raises lEO (High) for one M1 cycle. This
ensures that all lower priority devices can
decode the entire RET! instruction and reset
properly.
INTERNAL BUS
ZCITO
CLKlTRG
CLOCK
-----I~I
~I
PRESCALER
~
Figure 4. Counter/Timer Block Diagram
Counter/Timer Circuits. The CTC has four
independent counter/timer circuits, each containing the logic shown in Figure 4.
Channel Control Logic. The channel control
logic receives the 8-bit channel control word
when the counter/timer channel is programmed. The channel control logic decodes
2041·0158
the control word and sets the following
operating conditions:
c Interrupt enable (or disable)
Operating mode (timer or counter)
Timer mode prescaler factor (16 or 256)
Active slope for CLK/TRG input
EI Timer mode trigger (automatic or CLKITRG
input)
r:J Time constant data word to follow
[] Software reset
&a
!I
III
Time Constant Register. When the counter/
timer channel is programmed, the time constant register receives and stores an 8-bit time
constant value, which can be anywhere from 1
to 256 (0 = 256). This constant is automatically loaded into the down-counter when the
counter/timer channel is initialized, and subse, quently after each zero count.
Prescaler. The prescaler, which is used only
in timer mode, divides the system clock frequency by a factor of either 16 or 256. The
prescaler output clocks the down-counter during timer operation. The effect of the prescaler
on the down-counter is a multiplication of the
system clock.period by 16 or 256. The prescaler factor is programmed by bit 5 of the
channel control word.
Down-Counter. Prior to each count cycle, the
down-counter is loaded with the time constant
register contents. The counter is then
decremented one of two ways, depending on
operating mode:
I!I
D
By the prescaler output (timer mode)
By the trigger pulses into the CLK/TRG
input (counter mode)
Without disturbing the down-count, the Z-80
CPU can read the count remaining at any time
by performing an I/O read operation at the
port address assigned to the CTC channel.
When the down-counter reaches the zero
count, the ZC/TO output generates a p')sitivegoing pulse. When the interrupt is enabled,
zero count also triggers an interrupt request
signal (INT) from the interrupt logic.
61
Programming
Each Z-80 CTC channel must be programmed prior to operation. Programming
consists of writing two words to the I/O port
that corresponds to the desired channel. The
first word is a control word that selects the
operating mode and other parameters; the
second word is a time constant, which is a
binary data word with a value from 1 to 256. A
time constant word must be preceded by a
channel control word.
After initialization, channels may be
reprogrammed at any time. If updated control
and time constant words are written to a chan. nel during the count operation, the count continues to zero before the new time'constant is
loaded into the counter.
If the interrupt on any Z-80 CTC chgnnel is
enabled, the programming procedure should
also include an interrupt vector. Only one vector is required for all four channels, because
the interrupt logic automatically modifies the
vector for the channel requesting service.
A control word is identified by a 1 in bit O.
A 1 in bit 2 indicates a time constant word is to
follow. Interrupt vectors are always addressed
to Channel 0, and identified by a 0 in bit O.
Addressing. During programming, channels
are addressed with the channel select pins CSl
and CS2. A 2-bit binary code selects the
appropriate channel as shown in the following
table.
Channel
CSI
CSo
0
1
2
0
0
1
1
0
1
0
1
3
Reset. The CTC has both hardware and software resets. The hardware reset terminates all
down-counts and disables all CTC interrupts
by resetting the interrupt bits in the control
registers. In addition, the ZC/TO and Interrupt
outputs go inactive, lEO reflects IEI, and
Do-D7 go to the hi<]h-impedarice state. All
channels must be completely reprogrammed
after a hardware re~et.
The software reset is controlled by bit 1 in
the channel control word. When a channel
receives a software reset, it stops counting.
When a software reset is used, the other bits in
the control word also change the contents of
the channel control register. After a software
reset a new time constant word must be written
to the same channel.
If the channel control word has both bits Dl
and D2 set to I, the addressed channel stops
operatirig, pending a new time constant word.
The channel is ready to resume after the new
constant is programmed. In timer mode, if
D3 = 0, operation is triggered automatically
when the time constant word' is loaded.
Channel Control Word Programming. The'
channel control word is shown in Figure 5. It
sets the modes and parameters described
below.
Interrupt Enable. D7 enables the interrupt, so
that an interrupt output (INT) is generated at
zero count. Interrupts may be programmed in
either mode and may be enabled or disabled
at any time.
Operating Mode. D6 selects either tiI11:er or
counter mode.
Prescaler Factor. (Timer Mode Only). D5
selects factor-either 16 or 256.
Trigger Slope. D4 selects the active edge or
slope of the CLK/TRG input pulses. Note that
reprogramming the CLK/TRG slope during
operation is equivalent to issuing an active
edge. If the trigger slope is changed by a control word update while a channel is pending
operation in timer mode, the result is the same
as a CLK/TRG pulse and the timer starts.
Similarly, if the channel is in counter mode,
the counter decrements.
I0, Ioslo, I0.1 OJ I0, I0, 1'0 I
0
.
INTERRUPT
1 ENABLES INTERRUPT
jJ
o DISABLES INTERRUPT
MODE
o SELECTS TIMER MODE
1 SELECTS COUNTER MODE
PRESCAlER VALUE'
1 = VALUE OF 256
o = VALUE OF 16
ClK/TRG EDGE SELECTION _ _----I
o SELECTS FALLING EDGE
1 SELECTS RISING EDGE
t
Lo
.
L - -_ _
CONTROL OR VECTOR
= VECTOR
= CONTROL WORD
1
RESET
0
CONTINUED OPERATION
1
SOFTWARE RESET
=
=
TIME CONSTANT
o = NO TIME CONSTANT FOLLOWS
1 = TIME CONSTANT FOLLOWS
TIMER TRIGGER'
o = AUTOMATIC TRIGGER WHEN
TIME CONSTANT IS LOADED
CLK/TRG PULSE STARTS TIMER
1
=
'TIMER MODE ONLY
Figure S. Channel Control Word
62
2041·0159
Programming Trigger Mode (Timer Mode Only). D3 selects
(Continued)
the trigger mode for timer operation. When D3
is reset to 0, the timer is triggered automatically. The time constant word is programmed
during an 1/0 write operation, which takes one
machine cycle. At the end of the write operation there is a setup delay of one clock period.
The timer starts automatically (decrements) on
the rising edge of the second clock pulse (T 2)
of the machine cycle following the write operation. Once started, the timer runs continuously. At zero count the timer reloads
automatically and continues counting without
interruption or delay, until stopped by a reset.
When D3 is set to I, the timer is triggered
externally through the CLK/TRG input. The
time constant word is programmed during an
1/0 write operation, which takes one machine
cycle. The timer is ready for operation on the
rising edge of the second clock pulse (T 2) of
the follOWing machine cycle. Note that the first
timer decrement follows the active edge of the
CLK/TRG pulse by a delay time of one clock
cycle if a minimum setup time to the rising
edge of clock .is met. If this minimum is not
met, the delay is extended by another clock
period. Consequently, for immediate triggering, the CLK/TRG input must precede T2 by
one clock cycle plus its minimum setup time. 1£
the minimum time is not met, the timer. will
start on the third clock cycle (T 3).
Once started the timer operates continuously, without interruption or delay, until
stopped by a reset.
Time Constant to Follow. A 1 in D2 indicates
that the next word addressed to the selected
channel is a time constant data word for the
time constant register. The time constant word
may be written at any time.
A 0 in D2 indicates no time constant word is
to follow. This is ordinarily used when the
channel is already in operation and the new
channel control word is an update. A channel
will not operate without a time constant value.
The only way to write a time constant value is
to write a control word with D2 set.
:~:~
II ~~~~~
TC5~
LTC2
TC.
TC3
Figure 6. Time Constant Word
2041·0160.0161
Software Reset. Setting D1 to 1 causes a software reset, which is described in the Reset
section.
Control Word. Setting Do to 1 identifies the
word as a control word.
Time Constant Programming. Before a channel can start counting it must receive a time
constant word from the CPU. During programming or reprogramming, a channel control
word in which bit 2 is set must precede the
time constant word to indicate that the next
word is a time constant. The time constant
word can be any value from 1 to 256 (Figure
6). Note that 0016 is interpreted as 256.
In timer mode, the time interval is controlled
by three factors:
m The system clock period (cp)
Ell
The prescaler factor (P), which multiplies
the interval by either 16 or 256
EJ
The time constant (T), which is programmed
into the time constant register
Consequently, the time interval is the product of cp X P X T. The minimum timer resolution is 16 X cp (4 p.s with a 4 MHz clock). The
maximum timer interval is 256 x cp x 256 (16.4 ms
with a 4 MHz clock) . For longer intervals
timers may be cascaded.
Interrupt Vector Programming. 1£ the 2-80
CTC has one or more interrupts enabled, it
can supply interrupt vectors to the 2-80 CPU.
To do so, the 2-80 CTC must be pre-programmed with the most-significant five bits of
the interrupt vector. Programming consists of
writing a vector word to the 1/0 port corresponding to the 2-80 CTC Channel O. Note
that Do of the vector word is always zero, to
distinguish the vector from a channel control
word. D1 and D2 are not used in programming
the vector word. These bits are supplied by
the interrupt logic to identify the channel
requesting interrupt service with a unique
interrupt vector (Figure 7). Channel 0 has the
highest priority.
V7- V3
SUPPLIED
BY USER
=:=J
L
L
0 = INTERRUPT VECTOR WORD
1 = CONTROL WORD
CHANNEL IDENTIFIER
(AUTOMATICALLY INSERTED
BY CTC)
o 0 CHANNEL 0
o 1 = CHANNEL 1
1 0 = CHANNEL 2
1 1 = CHANNEL 3
=
Figure 7. Interrupt Vector Word
63
Pin
Description
CEo Chip Enable (input, active Low). When
enabled the CTC accepts control words, interrupt vectors, or time constant data words from
the data bus during an I/O write cycle; or:
transmits the contents of the down-counter to
the CPU during an 1/0 read cycle. In most
applications this signal is decoded from the
eight least significant bits of the address bus
for any of the four 1/0 port addresses that are
mapped to the four counter-timer channels.
lEI. Interrupt Enable In (input, active High).
A High indicates that no other interrupting
devices of higher priority in the daisy chain
are being serviced by the 2-80 CPU.
CLK. System Clock (input). Standard singlephase 2-80 system clock.
INT. Interrupt Request (output, open drain,
active Low). Low when any 2-80 CTC channel
that has been programmed to enable interrupts
has a zero-count condition in its down-counter.
CLK/TRGo-CLK/TRG3. External Clock/Timer
Trigger (input, user-selectable active High or
Low). Four pins corresponding to the four 2-80
eTC channels. In counter mode, every active
edge on this pin decrements the down-counter.
In timer mode, an active edge starts the timer.
CSO-CSI. Channel Select (inputs active High).
Two-bit binary address code selects one of the
four CTC channels for an 1/0 write or read
(usually connected to Ao and AI).
00-07. System Data Bus (bidirectional,
3-state). Transfers all data and commands
between the 2-80 CPU and the 2-80 CTC.
SYSTEM
BUSES
CPU _
r
lJL---l\
ry
l'
PIO
INT..l
iNr
lEI
+5V
T
lEI
ZC/TO,
CTC
-<
lEO
lEI
RxCA
iNr
TxCA
lEO
RxCB
hlB
510
lEO
vA
iNr
lEI
ROY
DMA
\
['r--r'
lEO. Interrupt Enable Out (output, active
High). High only if IEI is High and the 2-80
CPU is not servicing an interrupt from any
2-80 CTC channel. IEO blocks lower priority
devices from interrupting while a higher
priority interrupting device is being serviced.
10RQ. Input/Output Request (input from CPU,
active Low). Used with CE and RD to transfer
data and channel control words between the
2-80· CPU and the 2-80 CTC. During a write
cycle, IORQ and CE are active and RD
inactive. The 2-80 CTC does not receive a
speCific write Signal; rather, it internally
generates its own from the inverse of an active
RD signal. In a read cycle, IORQ, CE and RD
are active; the contents of the down-counter
are read by the 2-80 CPU. If IORQ and Ml are
both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on
the 2-80 data bus.
Ml. Machine Cycle One (input from CPU,
active Low). When Ml and IORQ are active,
the 2-80 CPU is acknowledging an interrupt.
The 2-80 CTC then places an interrupt vector
on the data bus if it has highest priority, and if
a channel has requested an interrupt (INT).
RD. Read Cycle Status (input, active Low).
Used in conjunction with IORQ and CE to
transfer data and channel control words
between the 2-80 CPU and the 2-80 CTC.
RESET. Reset (input active Lov/). Terminates
all down-counts and disables all interrupts by
resetting the interrupt bits in all control
registers; the 2C/TO and the Interrupt outpi..tts
go inactive; IEO reflects IEI; Do-D7 go to the
high-impedance state.
ZC/TOo-ZC/T02. Zero Count/Timeout (output,
active High). Three 2C/TO pins corresponding
to 2-80 CTC" channels 2 through 0 (Channel 3
has no 2C/TO pin). In both counter and timer
modes the output is an active High pulse when
the down-counter decrements to zero.
Figure S. A Typical Z-SO Environment
64
2041-0156
Timing
Read Cycle Timing. Figure 9 shows read
cycle timing. This cycle reads the contents of a
down-counter without disturbing the count.
During clock cycle T2, the Z-80 CPU initiates a
read cycle by driving the following inputs
Low: RD, IORQ, and CEo A 2-bit binary code
at inputs CS) and CSo selects the channel to
be read. Ml must be High to distinguish this
cycle from an interrupt acknowledge. No additional wait states are allowed.
latched into the appropriate register with the
rising edge of clock cycle T3.
CLltlTRG
INTERNAL
TlfAE'R
---------'
START TIMING
Figure 11. Timer Modo Timing
CLK
CSo. CS1.
CE
X
_ _- J
CHANNEL ADDRESS
I
\
\
RO
X
r-
_--r--------------
",1
I
_.I
OATA------'c
~
Figure 9. Read Cycle Timing
Write Cycle Timing. Figure 10 shows write
cycle timing for loading control, time constant
or vector words.
The CTC does not have a write signal input,
so it generates one internally when the read
(RD) input is High during T). During T2
IORQ and CE inputs are Low. Ml must be
High to distinguish a write cycle from an interrupt acknowledge. A 2-bit binary code at
.
inputs CS) and CSo selects the channel to be
addressed, and the word being written is
placed on the Z-80 data bus. The data word is
CSo. CS1.
CE
-=--x
IORQ
CHANNEL ADDRESS
r=
I
\
--7---------------------
no _JI
-
M1
--..,.-----------------I
--'
OATA _______
-JX~
__I_N_~X~
_ _ _ _ _ _ ___
Figuro 10. Write Cycle Timing
2041-0162, 0163, 0164, 0165
Timer Operation. In the timer mode, a
CLKITRG pulse input starts the timer (Figure
11) on the second succe~ding rising edge of
CLK. The trigger pulse is asynchronous, and it
must have a minimum width. A minimum lead
time (210 ns) is required between the active
edge of the CLK/TRG and the next. rising edge
of CLK to enable the prescaler on the following clock edge. If the CLK/TRG edge occurs
closer than this, the initiation of the timer
function is delayed one clock cycle. This corresponds to the startup timing discussed in the
programming section. The timer can also be
started automatically if SO programmed by the
channel control word.
CLKITRG
mTERUAL
COUNTER - - - - " , /
ZC/TO _ _ _ _- - . I
Figure 12. Counter Modo Timing
Counter Operation. In the counter mode, the
CLK/TRG pulse input decrements the downcounter. The trigger is asynchronous, but the
count is synchronized with CLK. For the
decrement to occur on the next rising ed<;16 of
CLK, the trigger edge must precede CLK by a
minimum lead time as shown in Figure 12. If
the lead time is less than specified, the count
is delayed by one clock cycle. The trigger
pulse must have a minimum width, and the
trigger period must be at least twice the clock
period.
The ZC/TO output occurs immediately after
zero count, and follows the rising CLK edge.
65
Interrupt
Operation
The Z-80 CTC follows the Z-80 system interrupt protocol for nested priority interrupts and
return fron: interrupt, wherein the interrupt
priority of a peripheral is determined by its
location in a daisy chain. Two lines-lEI and
lEO-in the CTC connect it to the system daisy
chain. The device closest to the + 5 V supply
has the highest priority (Figure 13). For additional information on the Z-80 interrupt structure, refer to the Z-BO CPU Product Specification and the Z-BO CPU Technical Manual.
HIGHEST PRIORITY
DEVICE
LOWEST PRIORITY
DEVICE
Figure 13. Daisy-Chain Interrupt Priorities
Within the Z-80 CTC, interrupt priority is
predetermined by channel number: Channel 0
has the highest priority, and Channel 3 the
lowest. If a device or channel is being serviced
with an interrupt routine, it cannot be interrupted by a device or channel with lower
priority until service is complete. Higher'
priority devices or channels may interrupt the
servicing of lower priority devices or channels.
A Z-80 CTC channel may be programmed to
request an interrupt every time its downcounter reaches zero. Note that the CPU must
be programmed for interrupt mode 2. Some
time after the interrupt request, the CPU sends
an interrupt acknowledge. The CTC interrupt
control logic determines the highest priority
channel that is requesting an interrupt. Then,
if the CTC lEI input is High (indicating that it
has priority within the system daisy chain) it
places an 8-bit interrupt vector on the .system
data bus. The high-order five bits of this vector
were written to the CTC during the programming process; the next two bits are provided
by the CTC interrupt control logic as a binary
code that identifies the highest priority channel requesting an interrupt; the low-order bit
is always zero.
Interrupt Acknowledge Timing. Figure 14
shows interrupt acknowledge timing. After an
interrupt request, the Z-80 CPU sends an interrupt acknowledge (Ml and IORQ). All channels are inhibited from changing their interrupt request status when Ml is active-about
two clock cycles earlier than IORQ. RD is
High to distinguish this cycle from an instruction fetch.
The CTC interrupt logic determines the
highest priority channel requesting an interrupt. If the CTC interrupt enable input (lEI) is
High, the highest priority interrupting channel
within the CTC places its interrupt vector on
the data bus when IORQ goes Low. Two wait
states (TWA) are automatically inserted at this
time to allow the daisy chain to stabilize. Additional. wait states may be added.
Return from Interrupt Timing. At the end of
an interrupt service routine the RET! (Return
From Interrupt) instruction initializes the daisy
chain enable lines for proper control of nested
priority interrupt handiing. The CTC decodes
the 2-byte RET! code internally and determines
whether it is intended for a channel being serviced. Figure 15 shows RETI timing.
If several Z-80 peripherals are in the daisy
chain, lEI settles active (High) on the chip
currently being serviced when the opcode
ED16 is decoded. If the folloWing opcode is
4D16, the peripheral being serviced is released
and its IEO becomes active. Additional wait
states are allowed.
Tl
CLK
M1
\
\
IORO
I
M1\
I
no
Do-D7
IEI=======7
DATA
\.====
----------~~>---Figure 14. Interrupt Acknowledge Timing
66
T2
T3
Tl
T4
T2
T3
T4
eLK
I
\
I
ED
IEI- _
- _
____
J ,
lEO
r
------------------~
Figure 15. Roturn From Interrupt Timing
2041-0166, 0167, 0168
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Test
Conditions
The characteristics below apply for the
folloWing test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
C S* = O°C to + 70°C,
+4.75 V!5 Vee!5 +5.25 V
c E* = - 40°C to + 85°C,
+4.75V!5Vee!5 +5.25V
tJ M* = -55°C to + 125°C,
+ 4.5 V !5 Vee !5 + 5.5 V
·See Ordering Information section for PSlckage
temperature range and product number.
DC
Characteristics
Symbol
2.1K
Parameter
Min
Max
Unit
VILe
VIHe
Clock Input Low Voltage
-0.3
+0.45
V
VIL
VlH
Input Low Voltage
Clock Input High Voltage
Vee -·6 Vee +.3
-0.3
+0.8
Input High Voltage
+2.0
Output Low Voltage
VOL
VOH
Output High Voltage
+2.4
V
=
V
IoL
V
IoH = -250 p.A
2 rnA
+20
p.A
VIN = 0 to Vee'
3-State Output Leakage Current in Float
±10
p.A
VO UT
rnA
VO H
REXT
Parameter
-1.5
Max
Unit
CLK
Clock Capacitance
20
pF
C IN
Input Capacitance
5
pF
COUT
Output CapaCitance
10
pF
25°C, f
V
± 10
Darlington Drive Current
=
V
Input Leakage Current
IoHD
TA
Vee
+0.4
Test Condition
Power Supply Current
Ice
III
ILO
Symbol
8085-0239
+5V
=
rnA
= 0.4 to Vee
= 1.5 V
= 390n
Condition
U nrneasured pins
returned to ground
1 MHz
67
-0-CLOCK
J
~
1r----1
~
.'
~
(D.-
~: ~ ~~_jnul\
IX
CSO, CS1
1-0-----
~I
CE
I~
READ
~I
10RQ
I~
<:5=-:'1
AD
I~
~I
-I-
DATA
~
f---®-I"
~
){
CSo. CS1
--I
1(
'~~I
I
CE
WRITE
I~
~I
I~
~I
-I
10RQ
DATA
I-{!D-~I
M1
\-
l:r
~I
15
INTERRUPT
ACKNOWLEDGE
\
10RQ
~I
*
DATA
lEI
--®-r""*
\.
I-®-
)
-
\l-
lEO
~I
-®--
-®-
=4
INT
CLK/TRGO_3
(COUNTER
MODE)
CLK/TRQo_3
(TIMER"
MODE)
ZC/TOo_2
68
®-1
21
-®-
@--
211
II
,
J
I:..--..w-I'--@--~}
J
-@-
~
-%-1
2041-0169
Z-80ACTC
Z-80B CTC
Min
Max
Min
Max
Min
Max
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)·
400
170
170
[ I]
250
105
105
[ I]
2000
2000
2000
2000
165
65
Z-80 CTC
Number Symbol
1
2
3
4
56
7
8
9
10 11
12
13
14
15 16
17
18
19
20 -
21
22
23
24
25 26
27
28
29
TcC
TwCH
TwCl
TfC
TrC
Th
TsCS(C)
Parameter
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
Clock Fall Time
Clock Rise Time
All Hold Times
CS to Clock , Setup Time
30
30
0
250
TsCE(C)
200
CE to Clock' Setup Time
TsIO(C)
IORQ 1 to Clock , Setup Time 250
TsRD(C) - - RD 1 to Clock' Setup Time - - 240
TdC(DO)
Clock , to Data Out Delay
TdC(DOz)
Clock 1 to Data Out Float Delay
TsDI(C)
Data In to Clock t Setup Time
60
TsMl(C)
Ml to Clock' Setup Time
TdMl(1EO)- Ml I to lEO I Delay (Interrupt
immediately preceding Ml)
TdIO(DOI)
IORQ I to Data Out Delay
(lN~ A Cycle)
TdlEl(lEOf)
lEI I to lEO I Delay
lEI , to lEO t Delay
TdIEI(lEOr)
(After ED Decode)
TdC(lNT)
Clock t to INT I Delay
TdCLK(INT) -
CLK/TRG , to INT 1
tsCTR(C) satisfied
tsCTR(C) not satisfied
0
160
150
240
230
50
90
NOTES:
[1] TcC = TwCh + TwCl + TrC + TfC.
[2J Increase delay by 10 ns for each 50 pF increase in loading,
200 pF maximum for data lines, and 100 pF for control lines.
130
90
[2]
N
CO
40
70
0
300
340
190
160
130
110
[3]
[2]
190
130
100
[3]
160
(TcC+ 140)
(2TcC)
50
50
"
[3]
[4]
[5]
[5]
40
40
200
200
120
120
210
150
[5]
[4]
150
190
190
tI
[5]
2TcC
50
50
210
260
190
110
TcC+ 120
(19) + (26)
(19) + (26)
(1) + (19) + (26) (1) + (19) + (26)
(19) + (26)
(1) + (19) + (26)
TcCTR
[A] 2.5 TcC > (n-2) TdIEI(IEOf) + TdMl(IEO) + TsIEI(lO)
+ TTL buffer delay, if any.
[B] RESET must be active for a minimum of 3 clock cycles.
100
70
70
200
110
220
(TcC+200)
(2TcC)
CLK/TRG Cycle Time
TrCTR
CLK/TRG Rise Time
TfCTR
CLK/TRG Fall Time
CLK/TRG Width (Low)
TwCTRI
200
TwCTRh - - CLK/TRG Width (High)
200
TsCTR(Cs)
CLK/TRG t to Clock t Setup
Time for Immediate Count
300
TsCTR(Ct)
CLK/TRG , to Clock t Setup
Time for enabling of Prescaler
210
on following clock t
TdC(ZC/TOr) Clock t to ZC/TO t Delay
TdC(ZC/TOf) Clock I to ZC/TO I Delay
[ I]
2000
2000
20
20
0
100
115
115
210
65
30
30
Notes·
140
140
[3J Increase delay by 2 ns for each 10 pF increase in loading,
100 pF maximum.
[4] Timer mode.
[5J Counter mode.
[6J RESET must be active for a minimum of 3 clock cycles.
• All timings are preliminary and subject to change.
69
..
':
Product
Number
Package/
Temp
Speed
Description
Product
Number
Description
28430
CE
2.5 MHz
280 CTC (28-pin)
28430A
CMB
4.0 MHz
280A CTC (28-pin)
28430
CM
2.5.MHz
Same as above
28530A
CS
4.0 MHz
Same as above
28430
CMB
2.5 MHz
Same as above
28430A
DE
4.0 MHz
Same as above
28430
CS
2.5 MHz
Same as above
28430A
DS
4.0 MHz
Same as above
28430
DE
2.5 MHz
Same as above
28430A
PE
4.0 MHz
Same as above
28430
DS
2.5 MHz
Same as above
28430A
PS
4.0 MHz
Same as above
28430
PE
2.5 MHz
Same as above
28430B
CS
6.0 MHz
Same as above
28430
PS
2.5 MHz
Same as above
28430B
DS
6.0 MHz
Same as' above
28430A
CE
4.0 MHz
280A CTC (28-pin)
28430B
PS
6.0 MHz
Same as above
28430A
CM
4.0 MHz
Same as above
"NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -40°C to +85°C, M
MIL·STD·883 Class B processing, S = O°C to + 70°C.
70
Package/
Speed
Temp
= -55°C to
+ 125°C, MB
= -55°C to
+ 125°C with
00-2022-02
Z8440
Z80® SIO Serial
l!lmptmft/(J)ulpul Controller
Product
Specification
September 1983
Features
General
Description
[J
Two independent full-duplex channels, with
separate control arid status lines for modems
or other devices.
[J
Data rates of 0 to 500K bits/second in
the xl clock mode with a 2.5 MHz clock
(Z-BO SIO), or 0 to BOOK bits/second with a
4.0 MHz clock (Z-BOA SIO).
[J
Asynchr.onous protocols: everything
necessary for complete messages in 5, 6, 7
or B bits/character. Includes variable stop
bits and several clock-rate multipliers;
break generation and detection; parity;
overrun and framing error detection.
[J
The Z-BO SIO Serial Input/Output Control'
ler is a dual-channel data communication
interface with extraordinary versatility and
capability. Its basic functions as a serial-toparallel, parallel-to-serial converter/controller
can be programmed by a CPU for a broad
range of serial communication applications.
The device supports all common asynchronous and synchronous protocols, byte- or
D~~~[ ~ ~ ~
BUS
~
Highly sophisticated and flexible daisychain interrupt vectoring for interrupts
without external logic.
bit-oriented,' and performs all of the functions
traditionally done by UARTs, USARTs and
. synchronous communication controllers combined, plus additional functions traditionally
performed by the CPU. Moreover, it does this
on two fully-independent channels, with an
exceptionally sophIsticated interrupt structure
that allows very fast transfers.
Full interfaCing is provided for CPU or DMA·
RxDA . - -
TxOA
°4
CHANNEL A
-Os
_0,
~
Synchronous protocols: everything
necessary for complete bit- or byte-oriented
messages in 5, 6, 7 or B bits/character,
including IBM Bisync, SDLC, HDLC,
CCITT-X.25 and others. Automatic CRC
generation/checking, sync character and
zero insertion/deletion, abort generation/detection and flag insertion.
[] Receiver data registers quadruply buffered,
transmitter registers doubly buffered.
IJ
07
RTSA
CTSA - -
lmi1i
MODEM
CONTROL
0,
40
DO
0,
39
0,
Os
3&
O.
0,
37
o.
iNf
36
lEI
35
CE
lEO
34
S/A
6
33
CIO
+5 V :: 9
32
Mf
_
RESET
~M1
CONTROL
_
lORa
R,OS _ _
F~~~
_
AD
RxCB _ _
- . . c/o
------...-
DAISY {
CHAIN
INTERRUPT
CONTROL
BIA
TxDA :: 15
26
TxCA
DTRA
DCDB
-4---
16
CISA ~ 18
19
OCOA
eLK
RO
g
g~
W/ROYB
EJ R,OS
R,CS
TXci
hOS
DTRS
Rffij
Rffi
_ } MODEM
OTRS
.
CONTROL
lEO
28
lxes ....-.
:~::
lEI
29
13
R,CA
CHANNEL D
~
12
R,OA
hOS
W/ROYS
10 %.80510/2 31
11
30
WIRDYA
SYNCA
lORa
23
CTSS ,
22
OCOS
RESET
L.....-,1""'--'1""'--'1----'
+5V
Figura 1.
2042·0111, 0120
GNO
CLK
z-ao 510/2 Pin Functions
Figure 2.
z-ao 510/2 Pin Assigrments
71
N
00
C
'"...o
General
Description
(Continued)
control. In addition to data communication, the
circuit can handle virtually all types of serial
I/O with fast (or slow) peripheral devices.
While designed primarily as a member of the
Z-80 family, its versatility makes it well suited
to many other CPUs.
The Z-80 S10 is an n-channel silicon-gate
depletion-load device packaged in a 40-pin
plastic or ceramic DIP. It uses a single + 5 V
power supply and the standard Z-80 family
single-phase clock.
Pin
Description
Figures 1 through 6 illustrate the three pin
configurations (bonding options) available in
the S10. The constraints of a 40-pin package
make it impossible to bring out the Receive
Clock (RxC), Transmit Clock (TxC)' Data Terminal Ready (DTR) and Sync (SYNC) signals
for both channels. Therefore, either Chan~el B
lacks a signal or two signals are bonded
together in the three bonding options offered:
CEo Chip Enable (input, active Low). A Low
• Z-80 S10/2 lacks SYNCB
• Z-80 SIO/1 lacks DTRB
• Z-80 S1010 has all four signals, but TxCB
and RxCB are bonded together
The first bonding option above (SI0/2) is the
preferred version for most applications. The
pin descriptions are as follows:
B/A. Channel A Or B Select (input, High
selects Channel B). This input defines which
channel is accessed during a data transfer
between the CPU and the S10. Address bit Ao
from the CPU is often used for the selection
function.
C/D. Control Or Data Select (input, High
selects Control). This input defines the type of
information transfer performed between the
CPU and the S10. A High at this input during
a CPU write to the S10 causes the information
on the data bus to be interpreted as a command for the channel selected by BilL A Low
at c/B means that the information on the data
bus is data. Address bit Al is often used for
this function.
D~~~l:: ~
BUS
~
level at this input enables the 810 to accept
command or data input from the CPU during a
write cycle or to transmit data to the CPU
during a read cycle.
CLK. System Clock (input). The S10 uses the
standard Z-80 System Clock to synchronize
internal signals. This is a single-phase clock.
CTSA, CTSB. Clear To Send (inputs, active
Low). When programmed as Auto Enables, a
Low on these inputs enables the respective
transmitter. If not programmed as Auto
Enables, these inputs may be programmed as
general-purpose inputs. Both inputs are
Schmitt-trigger buffered to accommodate slowrisetime signals. The S10 detects pulses on
these inputs and interrupts the CPU on both
logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noiselevel margin.
00-07. System Data Bus (bidirectional,
3-state). The system data bus transfers data
and commands between the CPU and the Z-80
S10. Do is the least significant bit.
DCDA, DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if the S10 is programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slowrisetime signals. The S10 detects pulses on
these pins and interrupts the CPU on both
logic level transitions. Schmitt-trigger buffer-
hDA
04
CHANNEL A
--05
-0,
-
rnA
CTSA - -
0,
DfRJI
MODEM
CONTROL
F~~~
- - + - Mi
_
lORa
_
_
_
0,
05
0,
38
O.
37
0,
iNf
36
lORa
R5
C/O
_
:
35
34
B/A
33
C/O
W/ROYA
SYNCA
hOB
RxDA
TxC8~
AxCA
SYNCB.W/ROYB
TxCA
lEa
CE
lEI
Mt
RxCB _ _
R T S B } MODEM
CTSB - CONTROL
DC DB - -
lEI
DO
lEa
AxDS . - -
32
Z·80 SIOI1
R5
31
GNO
30
W/ROYB
29
13
TxDA
CHANNEL B
DAISY {
CHAIN
INTERRUPT
CONTROL
40
39
+5 V
- + - RESET
CONTROL
0,
OJ
SYNCs
28
RxOB
27
RxCS
26
hCB
OTRA
16
25
TxOB
RTSA
17
24
Rffij
23
em
22
iiCiiB
CTSA
OCOA
ClK
20
RESET
L......:.-..,t"""--t"'-'-"t,...-.J
+5 v
GNO
ClK
Figure 3. Z-80 510/1 Pin Functions
72
Figure 4. Z-80 510/1 Pin Assignments
2042-011 L 0120
Pin
Description
ing does not guarantee a specific noise-level
margin.
(Continued)
DTRA, DTRB. Data Terminal Ready (outputs,
active Low). These outputs follow the state programmed into 2-80 SIO. They can also be programmed as general-purpose outputs.
In the 2-80 SIO/l bonding option, DTRB is
omitted.
lEI. Interrupt Enable In (input, active High).
This signal is used with lEO to form a priority
daisy chain when there is more than one
interrupt-driven device. A High on this line
indicates that no other device of higher priority is being serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is· High only if lEI is High and the
CPU is not servicing an interrupt from this
SIO. Thus, this signal blocks lower priority
devices from interrupting while a higher
priority device is being serviced by its CPU
interrupt service routine.
INT. Interrupt Request (output, open drain,
active Low). When the SIO is requesting an
interrupt, it pulls INT Low.
10RQ. Input/OutPllt Request (input from CPU,
active Low). 10RQ is used in conjunction with
BIA, C/D, CE and RD to transfer commands
and data between the CPU and the SIO. When
CE, RD and 10RQ are all active, the channel
selected by BIA transfers data to the CPU (a
read operation). When CE and 10RQ are
active but RD is inactive, the channel selected
by BIA is written to by the CPU with either
data or control information as speCified by
C/f). If 10RQ and Ml are active simultane-
D~~~!- ~
BUS
hCA - -
~
04
SYNCA
~
OS
WIRDYA
==~:
CONTROL!
F~~~
'
~
RTSA
CISA
DIRli
~::'
" . ".,. :::
AD
~
h.OB
SYNCB
INTE;:~!~ f _
CONTROL
1
RxCA, RxCB. Receiver Clocks (inputs).
Receive data is sampled on the rising edge of
RxC. The Receive Clocks may be I, 16, 32 or
64 times the data rate in asynchronous modes.
These clocks may be driven by the 2-80 CTC
Counter Timer Circuit for programmable baud
rate generation. Both inputs are Schmitttrigger buffered (no noise level margin is
speCified) .
In the 2-80 SIO/O bonding option, RxCB is
bonded together with TxCB.
RD. Read Cycle Status (input from CPU,
active Low). If RD is active, a memory or 1/0
read operation is in progress. RD is used with
BIA, CE and 10RQ to transfer data from the
SIO to the CPU.
RxDA, RxDB. Receive Data (inputs, active
High). Serial data at TTL levels.
RESET. Reset (input, active Low). A Low
RESET disables both receivers and transmitters, forces TxDA and TxDB marking, forces
the modem controls High and disables all
interrupts. The control registers must be
0,
0,
CHANNEL A
0,
lEO
M1
+5V
WlRDVA
SYNCA
GNO
WIROYB
RKOA
~CA
~
TxCA
RxTxCB
TlOA
CHANNEL B
BIA
:~,I
~;:! -_ ~g~i:OL
lEO
DCDS
RTSB
0,
iNf
MODEM
CONTROL
W7ADYB
}
DTM
RTSA
CISA
OCDA
RESET
'--t'---'t~t~
+5V
GND
eLK
Figure 5. Z-80 510/0 Pin Functions
2042-0111. 0120
MI. Machine Cycle (input from 2-80 CPU,
active Low). When Ml is active and RD is also
active, the 2-80 CPU is fetching an instruction
from memory; when Ml is active while 10RQ is
active, the SIO accepts Ml and 10RQ as an
interrupt acknowledge if the SIO is the highest
priority device that has interrupted the 2-80
CPU.
RifiCB . -
------.. c/o
-----..
l
=
-
ously, the CPU is acknowledging an interrupt
and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest
priority device requesting an interrupt.
Figure 6. Z-80 510/0 Pin Assignments
73
Pin
Description
(Continued)
rewritten after the SIO is reset and before data
is transmitted or received.
RTSA. RTSB. Request To Send (outputs,
active Low). When the RTS bit in Write
Register 5 (Figure 14) is set, the RTS output
goes Low. When the RTS bit is reset in the
Asynchronous mode, the output goes High
after the transmitter is empty. In Synchronous
modes, the RTS pin strictly follows the state of
the RTS bit. Both pins can be used as generalpurpose outputs.
SYNCA. SYNCB. Synchronization (inputs/outputs, active Low). These pins can act either as
inputs or outputs. In the asynchronous receive
mode, they are inputs similar to CTS and
DCD. In this mode, the transitions on these
lines affect the state of the Sync/Hunt status
bits in Read Register 0 (Figure 13)' but have
no other function. In the External Sync mode,
these lines also act as inputs. When external
synchronization is achieved, SYNC must be
driven Low on the second rising edge of RxC
after that rising edge of RxC on which the last
bit of the sync character was received. In
other words, after the sync pattern is detected,
the external logic must wait for two full
Receive Clock cycles to activate the SYNC
input. Once SYNC is forced Low, it should be
kept Low until the CPU informs the external
synchronization detect logic that synchronization has been lost or a new message is about to
start. Character assembly begins on the rising
edge of RxC that immediately precedes the
falling edge of SYNC in the External Sync
mode.
In the internal synchronization mode
(Monosync and Bisync), these pins act as outputs that are active during the part of the
receive clock (RxC) cycle in which sync
characters are recognized. The sync condition
is not latched, so these outputs are active each
time a sync pattern is recognized, regardless
of character boundaries.
In the 2-80 SIO/2 bonding option, SYNCB
is omitted.
TxCA. TxCB. Transmitter Clocks (inputs). In
asynchronous modes, the Transmitter Clocks
may be 1, 16, 32 or 64 times the data rate;
however, the clock multiplier for the transmitter and the receiver must be the same. The
Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements (no noise level margin is specified).
Transmitter Clocks may be'driven by the 2-80
CTC Counter Timer Circuit for programmable
baud rate generation.
In the 2-80 S10/O bonding option, TxCB is
bonded together with RxCB.
TxDA. TxDB. Transmit Data (outputs, active
High). Serial data at TTL levels. TxD changes
from the falling edge of TxC.
W/RDYA. W/RDYB. Waif/Ready A, Waif/
Ready B (outputs, open drain when pro- .
grammed for Wait function, driven High and
Low when programmed for Ready function).
These dual-purpose outputs may be programmed as Ready lines for a DMA controller
or as Wait lines that synchronize the CPU to
the S10 data rate. The reset state is open
drain.
_ } SERIAL DATA
CHANNEL A
:::=}
_
CHANNEL CLOCKS
SYNC
WAIT/READY
INTERNAL
CONTROL
LOGIC
CHANNEL A
CONTROL
AND
STATUS
DATA
-}
-
MODEMOR
OTHER CONTROLS
-}
MODEM OR
CPU
BUS 110
CONTROL
CHANNEL B
CONTROL
AND
STATUS
INTERRUPT
CONTROL _
LINES
INTERRUPT
CONTROL
LOGIC
_
::=}
}
CHANNEL B
OTHER CONTROLS
SERIAL DATA
CHANNEL CLOCKS
SYNC
WAIT/READY
Figure 1. Block Diagram
74
2042-0106
Functional
Description
the SIO offers valuable features such as nonvectored interrupts, polling and simple handshake capability.
Figure 8 illustrates the conventional devices
that the SIO replaces.
The first part of the following discussion
covers SIO data-communication capabilities;
the second part describes interactions between
the CPU and the SIO.
The functional capabilities of the 2-80 SIO
can be described from two different points of
view: as a data communications device, it
transmits and receives serial data in a wide
variety of data-communication protocols; as a
2-80 family peripheral, it interacts with the
2-80 CPU and other peripheral circuits, sharing the data, address and control buses, as
well as being a part of the 2-80 interrupt structure. As a peripheral to other microprocessors,
CHANNEL
A
lSI
CO
MICROPROCESSOR {
INTERFACE
C
...
(Ii
o
CHANNEL
B
MICROPROCESSOR
INTERFACE
-
B
Z.80
SIO
-
CHANNEL
A
CHANNEL
B
Figure 8. Conventional Devices Replaced by the Z-80 SIO
Data
Communi.cation
Capabili ties
The SIO provides two independent fullduplex channels that can be programmed for.
use in an:y common asynchronous or synchronous data-communication protocol. Figure 9
illustrates some of these protocols. The following is a short description of them. A more
detailed explanation of these modes can be
found in the Z-80 510 Technical Manual.
Asynchronous Modes. Transmission and
reception can be done independently on each
channel with five to eight bits per character, .
plus optional even or odd parity. The transmitters can supply one, one-and-a-half or two stop
bits per character and can provide a break
output at any time. The receiver breakdetection logic interrupts the CPU both at the
start and end of a received break. Reception is
protected from spikes by a transient spikerejection mechanism that checks the signal
one-half a bit time after a Low level is detected
on the receive data input (RxDA or RxDB in
Figure 5). If the Low does not persist-as in
the case of a transient-the character assembly
process is not started.
Framing i.errors and overrun errors are
detected and buffered together with the partial
character on which they occurred. Vectored
2042·0107
interrupts allow fast servicing of error conditions using dedicated routines. Furthermore, a
built-in checking process avoids interpreting a
framing error as a new start bit: a framing
error results in the addition of one-half a bit
time to the point at which the search for the
next start bit is begun.
The SIO does not require symmetric transmit
and receive clock signals-a feature that
allows it to be used with a 2-80 CTC or many
other clock sources. The transmitter and
receiver can handle data at a rate of I, 1116,
1132 or 1164 of the clock rate supplied to the'
receive and transmit clock inputs.
In asynchronous modes, the SYNC pin may
be programmed as an input that can be used
for functions such as monitoring a ring
indicator.
Synchronous Modes. The SIO supports both
byte-oriented and bit-oriented synchronous
communication.
Synchronous byte-oriented protocols can be
handled in several modes that allow character
synchronization with an 8-bit sync character
(Monosync), any 16-bit sync pattern (Bisync),
or with an external sync signal. Leading sync
75
Data
Communication
Capabilities
(Continued)
underrun occurs in the middle of a message,
an external/status interrupt warns the CPU of
this status change so that an abort may be
issued. One to eight bits per character can be
sent, which allows reception of a message with
no prior information about the character structure in the information field of a frame.
The receiver automatically synchronizes on
the leading flag of a frame in SDLC or HDLC,
and provides a synchronization signal on the
SYNC pin; an interrupt can also be programmed. The receiver can be programmed to
search for frames addressed by a single byte to
only a specified user-selected address or to a
global broadcast address. In this mode, frames
that do not match either the user-selected or
broadcast address are ignored. The number of
address bytes can be extended under software
control. For transmitting data, an interrupt on
the first received character or on every
character can be selected. The receiver
automatically deletes all zeroes inserted by the
transmitter during character assembly. It also
calculates and automatically checks the CRC
to validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers.
The SIO can be conveniently used under
DMA control to provide high-speed reception
or transmission. In reception, for example, the
SIO can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The SIO then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received.
characters can be removed without interrupting the CPU.
Five-, six- or seven-bit sync characters are
detected with 8- or 16-bit patterns in the SIO
by overlapping the larger pattern across multiple in-coming sync characters, as shown in
Figure 10.
CRC checking for synchronous byteoriented modes is delayed by one character
time so the CPU may disable CRC checking on
specific characters. This permits implementation of protocols such as IBM Bisync.
Both CRC-16 (X 16 + XI5 + X2 + 1) and
CCITT (X16 + XI2 + X5 + 1) error checki~g
polynomials are supported. In all non-SDLC
modes, the CRC generator is initialized to O's;
in SDLC modes, it is initialized to l's. The SIO
can be used for interfacing to peripherals such
as hard-sectored floppy disk, but it cannot
generate or check CRC for IBM-compatible
soft-sectored disks. The SIO also provides a
feature that automatically transmits CRC data
when no other data is available for transmission. This allows very high -speed transmissions
under DMA control with no need for CPU
intervention at the end of a message. When
there is no data or CRC to send in synchronous modes, the transmitter inserts 8- or.
16-bit sync characters regardless of the programmed character length.
The SIO supports synchronous bit-oriented
protocols such as SDLC and HDLC by performing automatic flag sending, zero insertion
and CRC generation. A special command can
be used to abort a frame in transmission. At
. the end of a message the SIO automatically
transmits the CRC and trailing flag when the
transmit buffer becomes empty. If a transmit
rr
II '
PARITY
T
STr
-MA-R-KI-NG-lIN-E---1I
DATA
p
,r-,-D-AT-A-',-'I-"""'"
DATA
I I I I MARKING LINE
ASYNCHRONOUS
::
::
DATA
SYNC
I
DATA
CRC,
CRC,
DATA
CRC,
CRC2
DATA
CRC,
CRC 2
CRC,
CRC2
MONOSYNC
SYNC
SYNC
DATA
SIGNAL
FLAG
I
ADDRESS
I
I
::
+
DATA
BISYNC
EXTERNAL SYNC
INFO{M;TION
FLAG
SDLC/HDLC/X.25
Figure 9. Some Z-80 SIO Protocols
6 BITS
~
. SYNq
I
SYNC
DATA
DATA
DATA
DATA
'-----..,-----8
~-----v~------~
16
Figure 10. Six-Bit Sync Character Recognition
76
2042-0lO8, OlO9
II 0 Interface
Capabilities
The SIO offers the choice of polling, interrupt (vectored or non-vectored) and blocktransfer modes to transfer data, status and control information to and from the CPU. The
block-transfer mode can also be implemented
under DMA control.
CPU is interrupted by the transmit buffer
becoming empty. (This implies that the
transmitter must have had a data character
written into it so it can become empty.) The
receiver can interrupt the CPU in one of two
ways:
Polling. Two status registers are updated at
appropriate times for each function being performed (for example, CRC error-status valid at
the end of a message). When the CPU is
operated in a polling fashion, one of the SIO's
two status registers is used to indicate whether
the SIO has some data or needs some data.
Depending on the contents of this register, the
CPU will either write data, read data, or just
go on. Two bits in the register indicate that a
data transfer is needed. In addition, error and
other conditions are indicated. The second
status register (special receive conditions) does
not have to be read in a polling sequence,
until a character has been received. All interrupt modes are disabled when operating the
device in a polled environment.
• Interrupt on first received character
I
Interrupts. The SIO has an elaborate interrupt
scheme to provide fast interrupt service in
real-time applications. A control register and a
status register in Channel B contain the interrupt vector. When programmed to do so, the
SIO can modify three bits of the interrupt vector in the status register so that it points directly to one of eight interrupt service routines in
memory, thereby servicing conditions in both
channels and eliminating most of the needs for
a status-analysis routine.
Transmit interrupts, receive interrupts and
external/status interrupts are the main sources
of interrupts. Each interrupt source is enabled
under- program control, with Channel A having a higher priority than Channel B, and with
receive, transmit and external/status interrupts
prioritized in that order within each channel.
When the transmit interrupt is enabled, the
• Interrupt on all received characters
Interrupt-on-first-received-character is
typically used with the block-transfer mode.
Interrupt-on-all-received-characters has the
option of modifying the interrupt vector in the
event of a parity error. Both of these interrupt
modes will also interrupt under special receive
conditions on a character or message basis
(end-of-frame interrupt in SDLC, for example).
This means that the special-receive condition
can cause an interrupt only if the interrupt-onfirst- recei ved-character or in terru pt -on -allreceived-characters mode is selected. In
interrupt-on-first-received-character, an interrupt can occur from special-receive conditions
(except parity error) after the first-receivedcharacter interrupt (example: receive-overrun
interrupt) .
The main function of the external/status
interrupt is to monitor the Signal transitions of
the Clear To Send (CTS), Data Carrier Detect
(DCD) and Synchronization (SYNC) pins
(Figures 1 through 6). In addition, an external/status interrupt is also caused by a CRCsending condition or by the detection of a
break sequence (asynchronous mode) or abort
sequence (SDLC mode) in the data stream.
The interrupt caused by the break/abort
sequence allows the SIO to interrupt when the
break/abort sequence is detected or terminated; This feature facilitates the proper termination of the current message,- correct
initialization of the next message, and the
accurate timing of the break/abort condition in
external logic.
77
N
00
C
~
C
I/O Interface
Capabilities
(Continued)
In a 2-80 CPU environment (Figure 11), SIO
interrupt vectoring is "automatic": the SIO
passes its internally-modifiable 8-bit interrupt
vector to the CPU, which adds an additional 8
bits from its interrupt-vector (I) register to form
the memory address of the interrupt-routine
table. This table contains the address of the
beginning of the interrupt routine itself. The
process entails an indirect transfer of CPU
control to the interrupt routine, so that the
next instruction executed after an interrupt
acknowledge by the CPU is the first instruction
of the interrupt routine itself.
SYSTEM
BUSES
Vt----\
~
I
DMA
CPU
-
INT
INT-
,-..
ROY
lEI
+5V
T
CPU/DMA Block Transfer. The SIO's block-
lEI
transfer mode accommodates both CPU block
transfers and DMA controllers (Z-80 DMA or
other designs). The block -transfer mode uses
the Wait/Ready output signal, which is .
selected with three bits in an internal control
register. The Wait/Ready output signal can be
programmed as a WAIT line in the CPU blocktransfer mode or as a READY line in the DMA
block-transfer mode.
To a DMA controller, the SIO READY output
indicates that the SIO is ready to transfer data
to or from memory. To the CPU, the WAIT output indicates that the SIO is not ready to
transfer data, thereby requesting the CPU to
extend the I/O cycle.
ZCITO,
CTC
iNT
ZCIT02
--<
lEO
lEI
RxCA
iNT
TxCA
lEO
RxCS
TxCS
WIROYA
WIROYB
SIO
lEO
-
INT
~
JA
lEI
ROY
DMA
1\
.y--y
Figure II. Typical Z-80 Environment
Internal
Structure
The internal structure of the device includes
a Z-80 CPU interface, internal control and
interrupt logic, and two full-duplex channels.
Each channel contains its own set of control
and status (write and read) registers, and control and status logic that provides the interface
to modems or other external devices.
The registers for each channel are desig-·
nated as follows:
WRO-\"1R7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The register group includes five 8-bit control
registers, two sync-character registers and two
status registers. The interrupt vector is written
into an additional 8-bit register (Write Register
2) in Channel B that may be read through
another 8-bit register (Read Register 2) in
Channel B. The bit assignment and functional
grouping of each register is configured to
simplify and organize the programming process. Table 1 lists the functions assigned to
each read or write register.
78
Read Register Functions
RRO
Transmit/Receive buffer status, interrupt
status and external status
RRI
Special Receive Condition status
RR2
Modified interrupt vector '(Channel B only)
Write Register Functions
WRO
Register pointArs, CRC initialize, initialization commands for the various modes, etc.
WRI
Transmit/Receive interrupt and data transfer
mode definition.
WR2
Interrupt vector (Channel B only)
WR3
Receive parameters,and control
WR4
Transmit/Receive miscellaneous parameters
and modes
WR5
Transmit parameters and controls
WR6
Sync character or SDLC address field
WR7
Sync character or SDLC flag
2032-0127
Internal
Structure
(Continued)
The logic for both channels provides formats, synchronization and validation for data
transferred to and from the channel interface.
The modem control inputs, Clear To Send
(CTS) and Data Carrier Detect (DCD), are
monitored by the external control and status
logic under program control. All external
control-and-status-logic signals are generalpurpose in nature and can be used for functions other than modem control.
Data Path. The transmit and receive data path
illustrated for Channel A in Figure 12 is identical for both channels. The receiver has three
8-bit buffer registers in a FIFO arrangement,
in addition to the 8-bit receive shift register.
This scheme creates additional time for the
CPU to service an interrupt at the beginning of
a block of high-speed data. Incoming data is
routed through one of several paths (data or
CRC) depending on the selected mode
and-in asynchronous modes-the character
length.
The transmitter has an 8-bit transmit data
buffer register that is loaded from the internal
data bus, and a 20-bit transmit shift register
that can be loaded from the sync-character
buffers or from the transmit data register.
Depending on the operational mode, outgoing
data is routed through one of four main paths
before it is transmitted from the Transmit Data
output (TxD).
N
00
CPU I/O
"O~'"
C
...
o
(I)
TOCHANNELB.----------------------------------~~-----------------------------------
EXT~~~~~~IALT~51~~~~g:
_______________.""..-__________....,.,...__
IN_TE_R_N_AL_D_A_TA_B_U--,S
TxDA
Figure 12. Transmit and Receive Data Path (Channel A)
2042-0112
79
Programming
The system program first issues a series of
commands that initialize the basic mode of
operation and then other commands that
qualify conditions within the selected mode.
For example, the asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first; then
the interrupt mode; and finally, receiver or
transmitter enable.
Both channels contain registers that must be
programmed via the system program prior to
operation. The channel-select input (BfA) and
the control/data input (c/iS) are the commandstructure addressing controls, and are normally controlled by the CPU address bus. Figures
15 and 16 illustrate the timing relationships for
programming the write registers and transferring data and status.
WRO is a special case in that all of the basic
commands can be written to it with a single
byte. Reset (internal or external) initializes the
pointer bits Do-D2 to point to WRO. This
implies that a channel reset must not be combined with the pointing to any register.
READ REGISTER 0
III
~I
I LL.::=
Rx
AVAILABLE
INTCHARACTER
PENDING (CH,
A ONLY)
~~gUFFER
EMPTY
}
SYNC/HUNT
CTS
Tx UNDERRUN/EOM
BREAK/ABORT
•
·Used With "ExternaliStatus
InterrUPt" Mode
READ REGISTER It
Read Registers. The S10 contains three read
registers for Channel B and two read registers
for Channel A (RRO-RR2 in Figure 13) that can
be read to obtain the status information; RR2
contains the internally-modifiable interrupt
vector and is only in the Channel B register
set. The status information includes error conditions, interrupt vector and standard
communications-interface signals.
To read the contents of a selected read
register other than RRO, the system program
must first write the pointer byte to WRO in
exactly the same way as a write register operation. Then, by executing a read instruction,
the contents of the addressed read register can
be read by the CPU.
The status bits of RRO and RRI are carefully
grouped to Simplify status monitoring. For
example, when the interrupt vector indicates
that a Special Receive Condition interrupt has
occurred, all the appropriate error bits can be
read from a single register (RRl).
Write Registers. The S10 contains eight v/rite
registers for Channel B and seven write
registers for Channel A (WRO-WR7 in Figure
14) that are programmed separately to configure the function'al personality of the channels; WR2 contains the interrupt vector for
both channels and is only in the Channel B
register set. With the exception of WRO, programming the write registers requires two
bytes. The first byte is to WRO and contains
three bits (Do-D2) that point to the selected
register; the second byte is the actual control
word that is written into the register to configure the S10.
80
L-ALL SENT
III
1
o
1
o
1
o
1
o
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
I FIELD BITS IN
I FIELD BITS
IN PREVIOUS SECOND PREVIOUS )
BYTE
BYTE
0
3
0
4
0
5
0
6
0
7
0
1
•
8
8
8
2
PARITY ERROR
Rx OVERRUN ERROR
L...---CRC/FRAMING ERROR
END OF FRAME (SDLC)
·ReSldue Data For Eight
Rx Bits/Character Programmed
~---
tUsed With SpeCial Receive Condition Mode
READ REGISTER 2*
III111
~~:t}
,
~;~
V4
V5
INTERRUPT
VECTOR
V6
V7,
tVariable If "Status Affects
Vector" is Programmed
(·CHANNEL B ONLY)
Figure 13. Read Register Bit Functions
2042-0114
Programming
WRITE REGISTER 0
WRITE REGISTER 4
(Continued)
I0 10,1 Os I0.1 0 10,1 0, IDo I
I0 10,1 0;1 0.1 0, I0,1 0, IDo I
7
7
3
1 1 1
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
II
0
1
2
3
4
5
6
7
1
1
'
PARITY ENABLE
PARITY EVEN/ODD
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1 'I, STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE
NULL CODE
SEND ABORT (SDLC)
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INT ON NEXT R. CHARACTER
RESET Tx INT PENDING
ERROR RESET
RETURN FROM INT (CH·A ONLY)
Xl CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNDERRUN/EOM LATCH
WRITE REGISTER 5
WRITE REGISTER I
I0 10,1 Os I0.1 0 10,1 0, IDo I
7
[~I~I~I~I~I~I~I~1
3
I
1
EXT INT ENABLE
Tx INT ENABLE
'-----STATUS AFFECTS VECTOR
(CH. B ONLY)
III
II
Rx INT DISABLE
}
Rx INT ON FIRST CHARACTER
INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR)
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)
,
WAIT/READY ON R/T
WAIT/READY FUNCTION
'-----WAIT/READy ENABLE
1_1_I__ ~~;RC
T. 5 BITS (OR LESS)/CHARACTER
Tx 7 BITS/CHARACTER
•
T. 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER
DTR
·Or On
SpecIal
Condition
WRITE REGISTER 2 (CHANNEL B ONLY)
WRITE REGISTER 6
I0 10,1 Os I0.1 0 10,1 0, IDo I
I0 10,1 Os I0.1 0, I0,1 0, IDo I
7
7
3
II ~, ~~
~V4
IIII
1
}INTERRUPT
VECTOR
II'
V5
V6
,
ENABLE
1.
SDLC/CRC·16
' - - - - - - T x ENABLE
' - - - - - - - S E N D BREAK
11,1
~!jmil!}.
SYNC BIT 5
SYNC BIT.6
SYNC BIT 7
V7
-AlSO SOLe Address Field
WRITE REGISTER 3
WRITE REGISTER 7
I0 10,1 Os I0.1 0 10,1 0, IDo I
1~1~1~1~1~1~1~1~1
7
3
IIII ' L-,,,,,,,,
~SYNC
CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT PHASE
.
AUTO ENABLES
1
o
1
0
1
Rx
Rx
Rx
Rx
5
7
6
8
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
1II111
~!~~g::Ho}
SYNC
SYNC
SYNC
SYNC
SYNC
BIT
BIT
BIT
BIT
BIT
11
12
13
14
15
•
·For SOLe 11 Musl Be Programmed
to "011111 to" For Flag Recognition
Figure 14. Write Register Bit Functions
2042·0113
81
Timing
The SIO must have the same clock as the
CPU (same phase and frequency relationship,
not necessarily the same driver).
Read Cycle. The timing signals generated by
a 2-80 CPU input instruction to read a data or
status byte from the SIO are illustrated in
Figure 15.
Write Cycle. Figure 16 illustrates the timing
and data signals generated by a 2-80 CPU output instruction to write a data or control byte
into the SIO.
Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an 310
(INT pulled Low), the 2-80 CPU sends an
interrupt-acknowledge sequence (Ml Low, and
IORQ Low a few cycles later) as in Figure 17.
The SIO contains an internal daisy-chained
interrupt structure for prioritizing nested interrupts for the various functions of its two channels, and this structure can be used within
an external user-defined daisy chain that
prioritizes several peripheral circuits.
The IEI of the highest-priority device is
terminated High. A device that has an interrupt pending or under service forces its IEO
Low. For devices with no interrupt pending or
under service, IEO = IEI.
To insure stable conditions in the daisy
chain, all interrupt status signals are prevented from changing while Ml is Low. When
IORQ is Low, the highest priority interrupt
requestor (the one with IEI High) places its
interrupt vector on the data bus and sets its
internal interrupt-under-service latch.
Return From Interrupt Cycle. Figure 18
illustrates the return from interrupt cycle.
Normally, the 2-80 CPU issues a RET! (Return
From Interrupt) instruction at the end of an
interrupt service routine. RET! is a 2-byte
opcode (EO-40) that resets the interruptunder-service latch in the SIO to terminate the
interrupt that has just been processed. This is
accomplished by manipulating the daisy chain
in the following way.
The normal daisy-chain operation can be
used to detect a pending interrupt; however, it
cannot distinguish between an interrupt under'
service and a pending unacknowledged interrupt of a higher priority. Whenever "EO" is
decoded, the daisy chain is modified by forcing High the IEO of any interrupt that has not
yet been acknowledged. Thus the daisy chain
identifies the device presently under service as
the only one with an IEI High and an IEO Low.
If the next opcode byte is "40," the interruptunder-service latch is reset.
The ripple time of the interrupt daisy chain
(both the High-to-Low and the Low-to-High
transitions) limits the number of devices that
can be placed in the daisy chain. Ripple time
can be improved with carry-Iook-ahead, or by
extending the interrupt-acknowledge cycle.
For further information about techniques for
increasing the number of daisy-chained
devices, refer to the Z-80 CPU Product
Specification.
CLOCK
CLOCK
~ \\...--------4:..11
CE, CtO, BtA _ _---I
I
LV
AD----------------~----~I--------
--------_~~_ _~I~
~------------------~------------DATA -------------------~~l----
lEI _ _ _ _ _ _ _ _ _
~
~
~
:
\====:
DATA-------------~~~---Figure 17. Interrupt Acknowledge Cycle
Figure 15. Read Cycle
~
1
~
CLOCK
.CO.K
....' ••
~A~~
IORQ
M1
I
.
AD -----------------......j.--------~ -------------------~I---------
>G:x_____
-,r------------.,--------
lEI -______
- - - - - .1
DATA _ _ _ _ _ _ _ _ _ _ _
Figure 16. Write Cycle
82
lEO
- -_ _ _ _-----:.-..11r--Figure 18. Return from Interrupt Cycle
2044-008, 009, 010, 011
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150°C
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
III S* = O°C to + 70°C,
+4.75 V ~ Vee ~ +5.25 V
m E* = - 40°C to + 85°C,
+4.75 V ~ Vee ~ +5.25 V
II M* = - 55°C to' + 125°C,
+4.5 V ~ Vee ~ +5.5 V
·See Ordering Information section for package
temperature range and product number.
DC
Characteristics
Symbol
Parameter
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
+5V
2.1K
The product number for each operating
temperature range can be found in the
ordering information included in the product speCification (see 1982/83 Zilog Data
Book, document number 00-2034-02).
Min
Max
Unit
-0.3
+0.45
V
V
VILe
Clock Input Low Voltage
VIHe
VIL
Clock Input High Voltage
Vee- 0 . 6
Vee+ 0 . 3
Input Low Voltage
-0.3
+0.8
V
VIH
Input High Voltage
+2.0
Vee
V
VOL
Output Low VC?ltage
VOH
Output High Voltage
ILl
Input Leakage Current
IOL
3-State Output Leakage Current in Float
IL(SYl
SYNC Pin Leakage Current
lee
Power Supply Current
lSI
00
o
...
(I)
o
Test Condition
p.A
= 2.0 rnA
IoH = -250 p.A
VIN = 0 to Vee
VOUI = 0.4 V to Vee
+ 10/ -40
p.A
O and control
WR4
Transmit/Receive'miscellaneous parameters
and modes
WR5
Transmit parameters and controls
The status bits of RRO and RRI are carefully
grouped to Simplify status monitoring. For
example, when the interrupt vector indicates
that a Special Receive Condition interrupt has
occurred, all the appropriate error bits can be
read from a single register (RRl).
Read Register Functions
RRO
Transmit/Receive buffer status, interrupt
status and external status
RRI
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only)
93
Z-80 DART
READ REGISTER 0
Read and Write
Registers
ID71 D61 D51 D, ID31 D,I D, IDo I
READ REGISTER 2
READ REGISTER 1 *
I~I~I~I~I~I~I~I~I
~ LALLSENT
§l§
L-NOTUSED
PARITY ERROR
Rx OVERRUN ERROR'
INTERRUPT
VECTOR
FRAMING ERROR
NOT USED
• Used With Special Receive Condition Mode
' - - - - - - - - - - V7
"Variable If "Status Affects
Vector" Is Programmed
WRITE REGISTER 0
WRITE REGISTER 1
I~I~I~I~I~I~I~I~I
I~I~\~I~I~\~\~\~I
T~l
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
T~
0
1
2
3
4
5
L
oo
0
0
NULL CODE
0
1
NOT USED
1
0
RESET EXT/STATUS INTERRUPTS
1
1
CHANNEL RESET
1
0
0
ENABLE INT ON NEXT Rx CHARACTER
1
0 I 1
RESET TxlNT PENDING
1
1
0
ERROR RESET
1
1, 1
RETURN FROM INT (CH·A ONLY)
'----------NOTUSED
o
' - - - - - - - WAIT/READY ON R/T
' - - - , - - - - - WAIT/READY FUNCTION
L..--,-_--:-_ _ _ WAIT/READY ENABLE
WRITE REGISTER 2 (CHANNEL B ONLY)
WRITE REGISTER 3
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
m~
EXT INT ENABLE
Tx INT ENABLE
STATUS AFFECTS VECTOR
(CH. B ONLY)
0
Rx INT DISABLE
'}
1
Rx INT ON FIRST CHARACTER
OR ON
OINT ON ALL Rx CHARACTERS (PARITY
SPECIAL
AFFECTS VECTOR)
RECEIVE
INT ON ALL Rx CHARACTERS (PARITY
CONDITION
DOES NOT AFFECT VECTOR)
1
o
o
o
L
T
I
I
L
RxENABLE
L - NOT USED (MUST BE PROGRAMMED 0)
....- - - - - - AUTO ENABLES
'--------- 0
INTERRUPT
VECTOR
o
1
1
0
1
0
1
Rx
Rx
Rx
Rx
5 BITS/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER
' - - - - - - - - - - V7
WRITE REGISTER 4
WRITE REGISTER 5
I~\~\~\~I~\~\~\~I
liIt
~
o
o
PARITY EVEN/ODD
.
0
1
NOT USED
1 STOP BIT/CHARACTER
~
~
~ ~T~TpO~I:~Jg~cAHRA,.RC~~~ER
o
o
0
1
0
1
1
1
94
ID7\D6\D51 D.\ D3\D,\ D, IDo I
PARITY ENABLE
NOT USED
Xl
X16
X32
X64
CLOCK
CLOCK
CLOCK
CLOCK
I
T~
o
o
MODE
MODE
MODE
MODE
L= :~:USED
~
1
1
Tx
Tx
Tx
Tx
NOTUSED
Tx ENABLE
SEND BREAK
5 BITS (OR LESS)/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER
' - - - - - - DTR
2044-004, 005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0, V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
[J S* = O°C to + 70°C,
+4.75V:$ Vee:$ +5.25 V
c E* = -40°C to +85°C,
+ 4.75 V:$ Vee:$ + 5.25 V
c M* = - 55°C to + 125°C,
+ 4.5 V :$ Vee:$ + 5.5 V
·See Ordering Information section for package
temperature range and product number.
DC
Characteristics
2.1K
Parameter
Min
VILe
Clock Input Low Voltage
-0.3
VIHe
VIL
Clock Input High Voltage
Symbol
VOH
IL
Inputl3-State Output Leakage Current
-10
IL(Rl)
HI Pin Leakage Current
-40
lee
Power Supply Current
VOL
Max
+0.45
Vee -0.6 +5.5
-0.3
+0.8
Inpllt Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIH
8085-0006
+5V
+2.0
+5.5
Unit
Test Condition
V
V
V
+10
+ 10
V
V
V
p.A
IOH = -250 p.A
O.4 .
e - 2 In the opcodt:' provides an. eflectlve address 01 pc + e doS PC 15 lncrerr.ented
by 2 prior to the additIOn at e
NOTES
Call and
Return Group
If B * O.
CALL nn
(SP-l) - PCH
(SP-2) - PCL
PC - nn
X
X
11 001 101 CD
17
CALL cc, nn
If condition
cc is false
X
X
11
10
If cc is false.
17
If cc is true.
cc 100
continue,
otherwise same as
CALL nn
RET
PCL - (SP)
PCH - (SP+ I)
X
X
11 001 001 C9
RET cc
If condItion
cc is false
X
X
11
10
N
11
continue,
otherwise
RET
RET!
RETNI
RST p
NOTE:
Input and
Output Group
X
X
X
X
(SP-I)
(SP-2)
PCH PCL -
X
- PCH
- PCL
0
p
101
001
101
000
101
101
101
101
11
t
III
ED
14
4D
ED
14
45
·11
cc
000
001
010
011
100
101
110
III
NZ
Z
NC
C
PO
PE
P
M
n
Condition
non-zero
zero
non· carry
carry
parity odd
parity even
sign positive
sign negative
ir6
d
~
000 DOH
001 OSH
010 IOH
011 ISH
100 20H
101 2SH
110 30H
III 3SH
IN A, (n)
A - (n)
IN r, (C)
r - (C)
if r = 110 only the
flags will be affected
I.
INI
(HL) - (C)
B - B-1
HL - HL +
(HL) - (C)
B - B-1
HL - HL + I
Repeat unhl
B = 0
X
IND
X
(C) -
OUT!
(HL)
B - B-1
HL - HL + I
(C) - (HL)
B - B-1
HL - HL +
Repedt untd
B = 0
X
(HL)
B - B-1
HL - HL-I
X
OT!R
OUID
CD 11 tht· fl'sul! 01 B-1
o
IS
P
11 011 011 DB
n
! 1 101 101 ED
01 r 000
-
11
-
X
X
X
X
X
11 101 101 ED
10 100 010 A2
X
X
X
X
X
11 101 101 ED
10 110 010 B2
X
X
X
X
X
11 101 101 ED
10 101 010 AA
X
X
X
X
X
11 101 101 ED
10 III 010 BA
@
X
r
(C) -
X
12
n to AD - ·A7
Acc. to AS - AI5
C to AO - A7
B to AS - AI5
5
(If B*O)
4
(If B =0)
16
C to AO - A7
B to AS - AI5
21
C to AO - A7
B to AS - AI5
16
CD
X
OUT (C), r
(C) -
X
X
@
OUT (n), A
INDR
X
CD
(HL) - (C)
B - B -1
HL - HL-I
(HL) - (C)
B - B-1
HL - HL-l
Repeat unhl
B = 0
(n) - A
NOTE·
X
11
01
11
01
C
t"'
If cc is true.
'RETN loads IFF2 - IFFI
INlR
2001·001
Return from
interrupt
Return from
non· maskable
interrupt
eo
If cc is false.
cc 000
CD
X
X
X
X
11 010011 D3
n
11 101 101 ED
01 r 001
-
,X
X
X
X
II 101 101 ED
10 100011 A3
X
X
X
X
X
II 101 101 ED
10 110 011 B3
C to AD - A7
B to AS - AI5
21
C to AD - A7
B to AS - A15
16
11
-
X
@
X
5
(If B*O)
4
(If B =0)
16
12
4 -
5
(If B*O)
4
(If B=O)
n to AO - A7
Acc. to AS - AI5
C to AO - A7
B to AS - A15
16
C to AO - A7
B to AS - A15
21
C to AO - A7
B to AS - A15
16
CD
zp.ro Ihp Z flaq
IS Sf't,
X
otherWise
X
It lS
X
X
11 101 101 ED
10 101 011 AB
16
C to AO - A7
B to AS - AI5
reset.
Z fldq IS 51'! upon instruction compiptlOn only.
111
Input and
Output Group
MnemonIc
(Continued)
OTDR
Summary of
Flag
Operation
Symbolic
Notation
X
X
X
X
X
X
lOA, I. lOA, R
BIT b, s
X
S
Z
H
N
H&N
C
X
0,
S
ADD A, s; ADC A, s
SUB s; SBC A, s; CP s; NEG
ANDs
OR s, XOR s
INC 5
DEC 5
ADD DD, ss
ADC HL, 55
sac HL, S9
RLA, RLCA,RRA; RRCA
RL m; RLC m; RR m;
RRC m; SLA m;
SRA m; SRL m
RLD; RRD
DAA
CPL
SCF
CCF
IN riC)
IN!. IND, OUT!; OUTD
INIR; INDR; OT!R; OTDR
LDI; lOD
lOIR; lODR
CPI; CPIR; CPD; CPDR
Symbol
Flags
H
P/V N
S
(C) - (HL)
B - B-1
HL - HL-I
Repeat until
B = 0
Instruction
P/V
112
Symbolic
Operation
X
X
X
Opcode
76 543 210 Hex
No.of No.of M No.of T
Bytes Cycles States
II 101 101 ED
10 III Oil
5
(If B*O)
4
(If B=O)
21
Comments
. C to Ao - A7
B to Aa - AI5
16
Do
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
X
X
X
0
0
X
X
X
X
X
I
I
X
C
I
I
X
X
X
X
X
X
X
X
I
I
0
X
0
X
X
0
0
X
X
X
X
X
X
·X
X
X
X
X
X
X
X
X
X
X
P/V
N
V
V
P
P
V
V
0
I
0
0
0
I
0
0
I
0
0
V
V
P
C
Comments
t
a·bit add or add with carry.
a·blt subtract, subtract with carry, compare and negate accumulator.
~}
P
P
X
X
I
0
0
0
I
I
0
0
I
X IFF
X X
0
0
P
X
X
X
Logical operations.
a·bit Increment.
a·bit decrement.
16·bit add.
16·bit add with carry.
16·bit subtract with carry.
Rotate accumulator.
Rotate and shilt locatIOns.
:}
:}
Rotate digit left and right.
Decimal adjust accumulator.
Complement accumulator.
Set carry.
Complement carry.
Input register indirect.
Block input and output. Z = 0 if B * 0 otherwise Z = O.
Block transfer instructions. P/V = I if BC * 0, otherwise PIV = O.
Block search instructions. Z = I if A = (HL). otherwise Z = O. P/V =
iI BC * 0, otherwise P/V = O.
The content of the interrupt enable flip· flop (IFF) is copied into the PIV flag.
The state of bit b of location s is copied into the Z flag.
Operation
Sign flag. S = 1 if the MSB of the result is I.
Zero flag. Z = 1 if the result of the operation is O.
Parity or overflow flag. Parity (P) and overflow
(V) share the same flag. Logical operations affect
this flag with the parity of the result while
arithmetic operations affect this flag with the
overflow of the result. If P/V holds parity, PlY
1 if the result of the operation is even, P/V = 0 if
result is odd. If PlY holds overflow, PlY = 1 if
the result of the 'operation produced an overflow.
Half-carry flag. H = 1 if the add or subtract
operation produced a carry into or borrow from
bit 4 of the accumulator.
Add/Subtract flag. N = 1 if the previous operation was a subtract.
Hand N flags are used in conjunction with the
decimal adjust instruction (DAA) to properly corfeC! the result into packeJ BCD format foHowing
addition or subtraction using operands with
packed BCD format.
Carry/Link flag. C = 1 if the operation produced
a carry from the MSB of the operand or result.
Symbol
I
o
1
X
V
P
ss
ii
R
n
nn
Operation
The flag is affected according to the result of the
operation.
The flag is unchanged by the operation.
The flag is reset by the operation.
The flag is set by the operation.
The flag is a "don't care."
P/V flag affected according to the overflow result
of the operation.
PlY flag affected according to the parity result of
the operation.
Anyone of the CPU registers A, B, C, D, E, H, L.
Any 8-bit location for all the addressing modes
allowed for the particular instruction.
Any 16-bit location for all the addreSSing modes
allowed for that instruction.
Anyone of the two index registers IX or IY.
Refresh counter.
8·bit value in range < 0, 255 >.
16-bit value in range < 0, 65535 >.
2001·001
Pin
Descriptions
Ao-AlS. Address Bus (output, active High,
3-state). Ao-A15 form a 16-bit address bus. The
Address Bus provides the aqdress for memory
data bus exchanges (up to 64K bytes) and for
I/O device exchanges.
BUSACK. Bus Acknowledge (output, active
Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus,
data bus, and control signals MREQ, IORQ,
RO, and WR have entered their highimpedance states. The external circuitry
can now control these lines.
BUSREQ. Bus Request (input, active Low).
Bus Request has a higher priority than NMI
and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, IORQ, RO, and WR to go to a highimpedance state so that other devices can
control these lines. BUSREQ is normally wireORed and requires an external pullup for
these applications. Extended BUSREQ
periods due to extensive OMA operations can
prevent the CPU from properly refreshing
dynamic RAMs.
00-07. Data Bus (input/output, active High,
3-state). 00-07 constitute an 8-bit bidirectional
data bus, used for data exchanges with
memory and I/O.
HALT. Halt State (output, active Low). HALT
indicates that the CPU has executed a Halt
instruction and is awaiting either a nonmaskable or a maskable interrupt (with the
mask enabled) before operation can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.
INT. Interrupt Request (input, active Low).
Interrupt Request is generated by I/O deVices.
The CPU honors a request at the end of the
'current instruction if the internal sbftwarecontrolled interrupt enable flip-flop (IFF) is
enabled. INT is normally wire-ORed and
requires an external pullup for these
applicatiops.
IORQ. Input/Output Request (output, active
Low, ~-state). IORQ indicates that the lower
half of the' address bus holds a valid I/O ,
address for an I/O read or write operation.
IORQ is also generated concurrently with MI
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be
placed on the data bus.
MI. Machine Cycle One (output, active Low).
MI, together with MREQ, indicates that the
current machine cycle is the opcode fetch
cycle of an instruction execution. MI, together
with IORQ, indicates an interrupt acknowledge
cycle.
MREQ. Memory Request (output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory wri,te operation.
NMI. Non-Maskable Interrupt (input, negative
edge-triggered). NMI has a higher priority
than INT. NMI is always recognized at the end
of the current instruction, independent of the
status of the interrupt enable flip-flop,' and
automatically forces the CPU to restart at
location 0066H.
RD. Read (output, active Low, 3-state). RD indicates that the CPU wants to read data from
memory or an I/O device. The addressed I/O
device or memory should use this signal to
gate data onto the CPU data bus.,
RESET. Reset (input, active Low). RESET
initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the interrupt status
to Mode O. During reset time, the address and
data bus go to a high-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minimum
of three full clock cycles before the reset
operation is complete~
RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bits of the system's address bus can be
used as a refresh address to the system's
dynamic memories.
WAIT. Wait (input, active Low). WAIT
indicates to the CPU that the addressed memory or I/O devices are not ready for a data
transfer. The CPU continues to enter aWait
state as long as this signal is active. Extended
WAIT periods can prevent the CPU from
refreshing dynamiC memory properly.
WH. Write (output, active Low, 3-state). WR
indicates that the CPU data bus holds valid
data to be stored at the addressed memory or
I/O location.
113
CPU Timing
The CPU executes instructions by proceeding through a specific sequence of operations:
II Interrupt ackpowledge
The basic clock period is referred to as a
T time or cycle, and three or more T cycles
make up a machine cycle (Ml, M2 or M3 for
instance). Machine cycles can be extended
either by the CPU automatically inserting one
or more Wait states or by the insertion of one
or more Wait states by the user.
Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). Approximately one-half clock cycle later,
MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the
CPU data bus.
The CPU samples the WAIT input with the
falling edge of clock state 1.'2 . During clock
states T3 and T4 of an Ml cycle dynamic RAM
refresh can occur while the CPU starts
decoding and executing the instruction. When
the Refresh Control signal becomes active,
refreshing of dynamic memory can take place.
• Memory read or write
Ell
I/O device read or write
T,
T,
Tw
CLOCK
WAIT
--~----------~--~-fJ~J
-II-®
;'
Do-D7 --}-----f('-~z~....;+Z~.lo.7__:(.f_---Jl'---_=f . . . _ _ _ _ _ _ _+-___
~
'-'"
I
-
r
I-
_ _ _ _OI/_ _
RFSH
21
~22
--------'r--
NOTE: Tw-Wait cycle added when necessary for slow ancilliary devices.
Figure 5. Instruction Opcode Fetch
114
2005·882
CPU
Timing
(Continued)
Memory Read or Write Cycles. Figure 6
shows the timing of memory read or write
cycles other than an opcode fetch (Ml) cycle.
The MREQ and RD signals function exactly as
in the fetch cycle. In a memory write cycle,
MREQ also becomes active when the address
bus is stable. The WR line is active when the'
data bus is stable, so that it can be used
directly as an R/W pulse to most semiconductor memories.
T,
CLOCK
RD
OPERA~~~~
{
00- 0 7
\'iR
OPER~:IIJ~
{
0
00-
7
--------------~--------~~--------------------~
Figure 6. Memory Read or Write Cycles
2005-883
115
CPU
Timing
(Continued)
Input or Output Cycles. Figure 7 shows the
timing for an I/O read or I/O write operation.
During I/O operations, the CPU automatically
inserts a single Wait state (Tw). This extra Wait
state allows sufficient time for an I/O port to
decode the address from the port address lines.
CLOCK
Ao-A7 __+-J1Y-__~____________~~~__-H________H-+-~~''-_
WAIT __~__4-__~__________~__L-~~_'
110
READ
OPIRATION
{
I~
WR
WRI~~
OPERATION {
_____________I):"-_________.....J
....
®.-
~
00- 0 7
---------~r---------------~{~------~~;_----__\
~
DATA OUT
NOTE: Tw· = One Wait cycle automatically inserted by CPU.
Figure 7. Input or Output Cycles
Interrupt Request/Acknowledge Cycle. The
CPU samples the interrupt signal :with .the rising edge of the last clock cycle at the' end of
any instruction (Figure 8). When an interrupt
is accepted, a special Ml cycle is generated.
During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. The CPU automatically adds two
Wait states to this cycle.
Tw'
Tw'
Tw
CLOCK
-----I----\.I----+----+H:~~-~
Ao-A15 ____________~~r1--------------p~c~~------_H_{.~--~+_~+_-'.~---
WAIT
____________
~--------------------------~--~~J
00-07
NOTE: I) TL = Last state 01 previous instruction.
2) Two Wait cycles automatically inserted by CPU(·).
Figure 8. Interrupt Request/Acknowledge Cycle
116
2005-884, 885
CPU
Timing
(Continued)
Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the
maskable interrupt input INT but has higher
priority and cannot be disabled under software
control. The subsequent timing is similar to
that of a normal memory read operation except
that data put on the bus by the memory is
ignored. The CPU instead executes a restart
(RST) operation and jumps to the NMI service
routine located at address 0066H (Figure 9).
CLOCK
IlMl - - - -
-
-
~®
Ir - - -
-------+-1----.la-AU
-
-------------1-' -l-4---...;..;;""..---+-"+o-----+---+-----4J
• Although NMI is an asynchronous input. to ~antee its being
recognized on the following machine cycle, NMI's falling edge
must occur no later than the rising edge of the clock cycle
preceding TLAST.
Figure 9. Non-Maskable Interrupt Request Operation
Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock period of any machine cycle (Figure
10). If BUSREQ is active, the CPU sets its
address, data, and MREQ, IORQ, RD, and WR
lines to a high-impedance state with the rising
edge of the next clock pulse. At that time, any
external device can take control of these lines,
usually to transfer data between memory and
I/O devices.
CLOCK
BUSREQ
BUSACK
--®
FLOAT
Ao-A15
-@
FLOAT
00-07
--@
MREQ
AD ,ViR
IORQ
Ml
-®--
UNCHANGED
NOTE' TL = Last state of any M cycle.
TX = An arbitrary clock cycle used by requesting device.
Figure 10. Z-BUS Request/Acknowledge Cycle
2005-0218, 886
117
CPU
Timing
(Continued)
Halt Acknowledge Cycle. When the CPU
receives a HALT instruction, it executes NOP
states until either an INT or NMI input· is .
Ml
received. When in the Halt state, the HALT
output is active and remains so until an interrupt is processed (Figure 11).
----.I••--------Ml-------~.I ••- - - - - - Ml
T4
Tl
T2
T3
T4
Tl
T2
CLOCK
NMI
--------------------------UI--~_·--------------------• See note, Figure Q.
NOTE: lNT will also force a Halt exit.
Figure 11. Halt Acknowledge Cycle
Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept it. As long as RESET remains active, the
address and data buses float, and the control
outputs are inactive. Once RESET goes
inactive, two internal T cycles are consumed
before the C'PU resumes normal processing
operation. RESET clears the PC register, so the
first opcode fetch' will be to location 0000
(Figure 12).
I.._---Ml--- -
- -
CLOCK
-®-
-0FLOAT
-----------------------®J~~------------------------~-------------------FLOAT
0
0-07
:
M1
-®-
/
----------------------~
~R~
R~~------------~/Z~/~/~/~/~/~-----~'~)-----------------------\
--------------
BU~~~~
HALT
~---------------
------
Figure 12. Reset Cycle
118
2005-887, 888
AC
Characteristicst
Number Symbol
Parameter
Z8300-1
(1.0 MHz)
Min Max
(ns)
(ns)
Z8300-3
(2.5 MHz)
Min Max
(ns)
(ns)
400*
TcC
Clock Cycle Time
1000*
2
TwCh
Clock Pulse Width (High)
470*
3
TwCl
Clock Pulse Width (Low)
470
4
TfC
Clock Fall Time
30
5-TrC
Clock Rise Time
30
30
380
145
6
TdCr(A)
Clock' to Address Valid Delay
7
TdA(MREQf)
Address Valid to MREQ
I Delay
8
TdCf(MREQf)
9
TdCr(MREQr)
Clock I to MREQ I Delay
Clock , to MREQ " Delay
lO-TwMREQh--MREQ Pulse Width (High)
180*
2000
180
2000
30
125*
370*
260
260
100
410*
100
170*---
890*
360*
tl
11
TwMREQl
MREQ Pulse Width (Low)
12
TdCf(MREQr)
Clock I to MREQ , Delay
260
13
TdCf(RDf)
Clock I to RD I Delay
340
130
14
TdCr(RDr)
. Clock , to RD , Delay
260
100
15-TsD(Cr)---Data Setup Time to Clock'
16
ThD(RDr)
Data Hold Time to RD ,
17
TsWAIT(Cf)
WAIT Setup Time to Clock I
18
ThWAIT(Cf)
WAIT Hold Time after Clock I
140
100
50
0
190
0
70
0
TdCr(Mlf)
19
Clock' to MI I Delay
20- TdCr(Mlr)--Clock , to Ml , Delay
0
340
130
340
130
21
TdCr(RFSHf)
Clock , to RFSH I Delay
460
180
22
TdCr(RFSHr)
Clock 1 to RFSH , Delay
390
150
23
TdCf(RDr)
Clock I to RD , Delay
290
110
24
TdCr(RDf)
Clock' to RD I Delay
260
100
25-TsD(Cf)
Data Setup to Clock I during
M21 M31 M4 or M5 Cycles
160
790*
60
26
TdA(IORQf)
Address Stable prior to lORQ
27
TdCr(lORQf)
Clock , to lORQ I Delay
240
90
28
TdCf(IORQr)
Clock I to lORQ , Delay
290
110
29
TdD(WRf)
Data Stable prior to WR I
TwWR
WR Pulse Width
32
TdCf(WRr)
Cloyk I to WR , Delay
33
TdD(WRf)
Data Stable prior to WR I
34
35 -
TdCr(WRf)
Clock , to WR I Delay
36
TdCf(HALT)
Clock I to HALT' or I
37
TwNMl
NMI Pulse Width
38
TsBUSREQ(Cr) BUSREQ Setup Time to Clock'
TdWRr(D) - - Data Stable from WR ,
190*
470*
30-TdCf(WRf)--Clock I to WR I Delay
31
320*
240
90
360*
890*
100
260
30*
-30*
210
290*
80
130*--300
760
210
80
210
80
• For clock periods other than the minimums shown in the table, calculate parameters
using the expressions in the table on the following page.
tAIl timings assume equal loading on pins within 50 pF.
Timings are preliminary and subject to change.
119
0
t'II
..,
~
CI
AC
Characteristicst
(Continued)
Number Symbol
Z8300-1
Min Max
(ns)
(ns)
Parameter
ThBUSREQ(Cr) BUSREQ Hold Time after Clock I
39
40 -TdCr(BUSACKf)- Clock I to BUSACK 1 Delay
TdCf(BUSACKr) Clock 1 to BUSACK I Delay
41
TdCr(Dz)
42
Clock I to Data Float Delay
TdCr(CTz)
43
Clock I to Control Outputs Float
Delay (MREQ, IORQ, RD,
and WR)
TdCr(Az)
44
Clock I to Address Float Delay
45-TdCTr(A)--MREQ I, IORQ I, RD I, and
WR I to Address Hold Time
TsRESET(Cr)
RESET to Clock I Setup Time
46
47
ThRESET(Cr)
RESET to Clock I Hold Time
TsINTf(Cr)
INT to Clock I Setup Time
48
ThINTr(Cr)
49
INT to Clock I Hold Time
50 -TdMlf(IORQf) - M1 1 to IORQ 1 Delay
TdCf(IORQf)
51
Clock 1 to IORQ 1 Delay
TdCf(IORQr)
52
Clock I to IORQ I Delay
TdCf(D)
53
Clock 1 to Data Valid D~lay
Z8300-3
Min Max
(ns)
(ns)
0
0
310
120
290
240
110
90
110
290
290
400*
240
110
160*-90
0
210
0
80
0
0
920*--
290
260
110
100
230
2300*
290
'For clock periods other than the minimums shown in the table, calculate parameters
using the following expressions. Calculated values above assumed TrC = TIC = 20 ns.
t All timings assume equal loading on pins with 50 pF.
Timings are preliminary and subject to cha·nge.
Footnotes to AC Characteristics
Number Symbol
Z8300-1
Z8300-3
1
TeC
TwCh + TwCl + TrC + TfC
TwCh + TwCl + TrC + TfC
2
TwCh
Although static by design,
TwCh of greater than 200 J1.s
is not guaranteed
Although static by design,
TwCh of greater than 200 J1.S
is not guaranteed
7 - . TdA(MREQf) - - - - TwCh + TfC - 200 - - - - - - TwCh + TfC - 75 - - - - - - - 10
TwMREQh
TwCh + TfC - 90
TwCh + TfC - 30
11
TwMREQl
TeC - 110
TeC - 30
26
TdA(IORQf)
TeC - 210
TeC - 80
29
TdD(WRf)
TeC - 540
TeC - 210
3 1 - TwWR - - - - - - - TeC - 110
TdD(WRf)
TwCl + TrC - 470
TwCl + TrC - 180
35
TdWRr(D)
TwCl + TrC - 210
TwCl + TrC - 80
45
TdCTr(A)
TwCl + TrC - 110
TwCl + TrC - 40
50
TdM1f(IORQf)
2TeC + TwCh + TfC - 210
2TeC + TwCh + TfC - 80
AC Test Conditions:
VIH = 2.0 V
VIL = 0.8 V
VIHC = VCC -0.6 V
VILC = 0.45 V
VOH = 2.0 V
VOL = 0.8 V
FLOAT = ±0.5 V
120
TeC - 40 - - - - - - - - - - - -
33
Absolute
Maximum
Ratings
Storage Temperature ........ -65°C to + 150 °e
Temperature
under Bias ........ See Ordering Information
Voltages on all inputs and
<;mtputs with respect to ground. -0.3 V to + 7 V
Power Dissipation .................... 1.5 W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
folloWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND (0 V). Positive current flows into the
referenced pin. Available operating
temperature ranges are:
m S* = ooe to + 70°C,
+4.75 V ::5 Vee::5 +5.25 V
All ac parameters assume a load capacitance
of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for
the data bus and 100 pF for address and control·
lines.
+5V
'See Ordering Information section for package
temperature range and product number.
DC
Characteristics
Parameter
Min
VILe
Clock Input Low Voltage
-0.3
VIHe
VIL
Clock Input High Voltage
Vee-· 6
Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
III
Output High Voltage
Input Leakage Current
lLO
3-State Output Leakage
lee
Power Supply Current
Symbol
Frequency
Capacitance
Symbol
Max
0.45
V
Vee
0.4
V
V
V
IoH = -250 p.A
10
J.l.A
VIN = 0 to Vee
± 10 1
J.l.A
VOUT = 0.4 to Vee
Temperature
70°C
25°C
Max Typical Max
Unit
30
26
15
20
rnA
28300-3 (2.5 MHz)
45
42
25
35
rnA
Min
IoL= 1.8 rnA
V
28300-1 (1.0 MHz)
Parameter
Test Condition
V
Vee+ .3
0.8
2.4
OOC
Max
Unit
Max
Unit
Note
------------------~-----------------------------------------------------------
C eLOeK
CIN
COUT
TA
8085-0221
Clock Capacitance
35
pF
Input Capacitance
Output Capacitance
5
pF
10
pF
U nrneasured pins
returned to ground
= 25°e. f = 1 MHz.
121
Ordering
Information
Product
Number
Package/
Speed
Temp
Description
Product
Number
Package/
Temp
Speed
28300-1
PS
1.0 MHz
280L CPU (40-pin)
28300-3
PS
28300-1
CS
1.0 MHz
Same as above
28300-3
CS
• 2.5 MHz
2.5 MHz
Description
280L CPU (40-pin)
Same as above
NOTES: C = Ceramic, P = Plastic; S = O°C to + 70°C.
122
00-2189~4
2:8320 )Low Power
ZaOL ® PIO Parallel
Kmlpu~/@uRpui
Ziiog
1I.e and DC Characteristics
Preliminary
September 1983
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
As Specified in
Operating Ambient
Ordering Information
Temperature ........ in Product Specifications
Storage Tempera ture ........ -65°C to + 150 °C
Test
Conditions
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
range is:
[J
+5V
2.1K
S * = O°C to + 70°C,
+4.75Vs;Vee s; +5.25 V
·See Ordering Information section in· product specifications
for package temperature range and product number.
DC
Characteristics
Parameter
Symbol
VILe
VIHe
VIL
VIH
VOL
VOH
ILl
ILO
IL(Sy)l
lee
IOHD2
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Output Leakage
Current in Float
SYNC Pin Leakage Current
Power Supply Current:
SIO
PIO
CTC
Darlington Drive Current
Min
Max
-0.3
Vee- 0 .6
-0.3
+2.0
+0.45
Vee+ 0 .3
+0.8
Typical
Condition
±1O
V
V
V
V
V
V
/lA
loL = 2.0 rnA
IOH = -250/lA
VIN = 0 to Vee
±1O
+10/ -40
/lA
/lA
VOUT = 0.4 to Vee
VIN = 0 to Vee
Vee
+0.4
+2.4
30
20
20
-1.5
Unit
20
13
13
rnA
rnA
rnA
rnA
VOH = 1.5V
REXT = 390n
Over specified temperature and voltage range.
NOTES:
[1] SIO only
[2] eTe and PIa only
123
Z8320-1 and
Z8320-3
Z80L PIO
AC
Characteristics
CLOCK
CE
B/A,C/D
DO-D7
{OUT _ _ _
-+-~
Ir-----+-----"""""II ,.-++--_ _+--_ __
IN
------~----~--~.~---+---------------~
lEI
lEO
READY
IARDY OR BRDY)
I.-------~QD~------~~I
STROBE
IASTB OR BSTB)
MODE 0
MODE 1
Ao-A7
Bo-B7
MODE2
MODE 3
124
r---~-----------------------
Z8320-1 and
Z8320-3
Number Symbol
Z80L PIO
AC
TcC
Characteristics
TwCH
2
(Continued)
3
TwCl
4
TfC
5-TrC
TsCS(RI)
6
7
8
9-
Parameter
Z8320-l
(1.0 MHz)
Min Max
Z8320-3
(2.5 MHz)
Min Max
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
1000
470
470
400
170
170
Clock Fall Time
Clock Rise Time
CE, BIA, C/iS to RD,
IORQ 1 Setup Time
Any Hold Times for Specified
Th
Setup Time
RD,
IORQ to Clock I Setup
TsRI(C)
Time
TdRI(DO) - - RD, lORQ 1 to Data Out Delay
10
TdRI(DOs)
11
TsDI(C)
17 18
TdlEl(lEOr)
13 14
15
16
19
TcIO(C)
lEI I to lEO I Delay (after ED
Decode)
IORQ I to Clock 1 Setup Time
(To Activate READY on Next
Clock Cycle)
20
TdC(RDYr)
Clock 1 to READY I Delay
[ 1)
2000
2000
30
30
140
50
0
0
[6)
115
300
430--- [ 2 ) - -
1090
RD, IORQ I to Data Out Float
Delay
Data In to Clock I Setup Time
TdIO(DOl)
IORQ 1 to Data Out Delay
(lNTACK Cycle)
TsMl(Cr) - - Ml 1 to Clock I Setup Time
TsMl(Cf)
Ml I to Clock 1 Setup Time
(Ml Cycle)
Ml 1 to lEO 1 Delay (Interrupt
TdMl(lEO)
Immediately Preceding Ml I)
lEI to IORQ 1 Setup Time
TslEI(lO)
(lNTACK Cycle)
TdlEI(lEOf) -lEI 1 to lEO 1 Delay
12
2000
2000
30
30
Notes*
160
410
140
50
CL
(3)
340
860
540
210
0
0
[5,7)
(7)
190--(5)-CL = 50 pF
540
210
140
(5)
220
560
(5)
200
510
CL
21- TdC(RDYf) -
Clock 1 to READY 1 Delay
STROBE Pulse Width
STROBE I to Clock 1 Setup
Time (To Activate READY on
Next Clock Cycle)
TdIO(PD)
lORQ I to PORT DATA Stable
24
Delay (Mode 0)
25- TsPD(STB) -PORT DATA to STROBE I
Setup Time (Mode 1)
TdSTB(PD)
STROBE 1 to PORT DATA
26
Stable (Mode 2)
TdSTB(PDr)
STROBE I to PORT DATA Float
27
Delay (Mode 2)
22
23
TwSTB
TsSTB(C)
28
TdPD(I~T)
29
TdSTB(lNT)
PORT DATA Match to INT 1
Delay (Mode 3)
STROBE I to INT I Delay
NOTES:
[II TcC = TwCh + TwCI + TrC + TIC.
[21 Increase TdRI(DO)by 10 ns for each 50 pF increase in load
up to 200 pF max.
[3J Increase TdIO(DOl) by 10 ns for each 50 pF, increase in
loading up to 200 pF max.
14J For Mode 2: TwSTB > TsPD(STB).
15J Increase these values by 2 ns for each 10 pF increase in
loading up to 100pF max.
()()'2330{) 1
\
560
= 50 pF
150
[5)-(4)
220
[5)
150
390
390
200
(5)
590
230
(5)
510
200
1360
1240
540
490
510
260
660
CL
til
IllS
480
360
I
•
0
[8)
. 300
760
= 50 pF
= 50 pF
[61 TsCS(RI) may be reduced. However, the time subtracted
from TsCS(Rl) will be added to TdRI(DO).
[7J 2.5 TcC > (N-2)TdIEI(IEOf) + TdMI(!EO) + TsIEI(IO)
. ± TTL Buffer Delay, if any.
18J MI must be active for a minimum of two clock cycles to
reset the PI~.
• Timings are preliminary and subject to change.
125
18330 Low Power
Z80L® eTC Counlerl
'lrimme~ CCfir«:uniift
Zilog
AC and DC Characteristics
Preliminary
September 1983
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... .:...0.3 V to +7.0 V
As Specified in
Operating Ambient
Ordering Information
Temperature ........ in Product Specifications
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Storage Temperature ........ -65°C to + 150°C
Test
Conditions
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
range is:
EI S* = O°C to + 70°C,
+4.75 V ~ Vee ~ +5.25 V
+5V
2.1K
'See Ordering Information section in product specifications
for package temperature range and product number.
DC
Characteristics
Parameter
Symbol
VILe
VIHe
VIL
VIH
VOL
VOH
ILl
ILO
IL(Sy)l
ICC
IOH02
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
3 c State Output Leakage
Current in Float
SYNC Pin Leakage Current
Power Supply Current:
SIO
PIO
CTC
Darlington Drive Current
Min
Max
-0.3
Vee- 0 . 6
-0.3
+2.0
+0.45
Vee+ 0 .3
+0.8
Typical
Condition
±10
V
V
V
V
V
V
p.A
10L = 2.0 rnA
10H == -250 p.A
VIN == 0 to Vee
±10
+10/ -40
p.A
p.A
VOUT == 0.4 to Vee
VIN == 0 to Vee
Vee
+0.4
+2.4
30
20
20
-1.5
Unit
20
13
13
rnA
rnA
rnA
rnA
VOH == 1.5V
REXT == 390n
Over speCified temperature and voltage range.
l;'l"OTES:
[1] SIO only
[2] eTC and PIO only
127
Z8330-1 and
Z8330-3
Z80L CTC
AC
Characteristics
~
~-0CLOCK
~
r-L ~
n01\
L-J
IX
CSo. CS1
,
,
I--ra
... CI:fiilfi«:;runil ®nn
September 1983
Features
[J
Regular, easy-to-use architecture
[J
[J
Instruction set more powerful than many
minicomputers
Resource-sharing capabilities for multiprocessing systems
[J
Multi-programming support
[J
Directly addresses 8M bytes
[J
Compiler support
[J
Eight user-selectable addressing modes
D
[J
Seven data types that range from bits to
32-bit long words and byte and word strings
Memory management and protection provided by Z8010 Memory Management Unit
[J
[J
System and Normal operating modes
32-bit operations, including signed multiply
and divide
[J
Separate code, data and stack spaces
D Z-BUS compatible
Sophisticated interrupt structure
o 4, 6 and 10 MHz clock rate
[J
General
Description
The Z8000 is an advanced high-e~d 16-bit
microprocessor that spans a wide variety of applications ranging from simple stand-alone
computers to complex parallel-processing
systems. Essentially a monolithic minicomputer
central processing unit, the Z8000 CPU is
characterized by an instruction set more
powerful than many minicomputers; abundant.
resources in registers, data types, addressing
modes and addressing range; and a regular
architecture that enhances throughouput by
avoiding critical bottlenecks such as implied or
dedicated registers.
CPU resources include sixteen 16-bit
general-purpose registers, seven data types
that range from bits to 32-bit long words and
byte and word strings, and eight userselectable addressing modes. The 110 distinct
instruction types can be combined with the
various data types and addressing modes to
form a powerful set of 414 instructions.
Moreover, the instruction set is regular; most
instructions can use any of the five main addressing modes and can operate on byte, word
and long-word data types.
The CPU can operate in either the system or
normal modes. The distinction between these
two modes permits privileged operations,
thereby improving operating system organization and implementation. Multiprogramming is
supported by the "atomic" Test and Set in-
struction; multiprocessing by a combination of
instruction and hardware features; and compilers by multiple stacks, special instructions
and addressing modes.
DUS{
TIMmG
AS
AD1S
os
AD14
MREQ
AD1'
READIWRITE
ADll
NORMAUSYSTEM
AD 10
AD12
S~ATusl
BYTE/WORD
AD.
ADs
ST,
AD,
ST2
ADs
ST1
STo
ADs
ADDRESSI
DATA BUS
AD.
AD,
CPu{
CO'.TROL
WAIT
zaOO1
zaOO2
CPU
AD2
AD1
,-ADD
BUS{
. CONTROL
,."•• UPTS{
MUL TI·MICRO {
CONTROL
=
NMI
Vi
NVi
I
SNs
I
SNs
I
I
I
I
I
SN4
I
-rz.;';:~~
SEGMENT:
NUMBER I
SN,
SN2
I
SN1
I
I
SNo
SEGMENT
SEGT
L __
_
~R~ _ _
Figure 1. ZaDOO CPU Pin Functions
2001-0089
I
-1
139
The 28000 CPU is offered in two versions:
the 28001 48-pin segmented CPU and the
28002 40-pin non-segmented CPU. The main
difference between the two is in addressing
range. The 28001 can directly address 8 megabytes of memory; the 28002 directly addresses
64 kilobytes. The two operating modes-system
and normal-and the distinction between code,
data and stack spc;lces within each mode allows
memory extension up to 48 megabytes for the
28001 and 384 kilobytes for the 28002.
To meet the requirements of complex,
memory-intensive applications, a companion
memory-management device is offered for the
28001. The 28010 Memory Management Unit
manages the large address space by providing
features such as segment relocation and
memory protection. The 28001 can be used
with or without the 28010. If used by itself, the
28001 still provides an 8 megabyte direct
addressing range, extendable to 48 megabytes.
The 28001, 28002 and 28010 are fabricated
with high-density, high-performance scaled
n-channel silicon-gate depletion-load technology, and are housed in dual in-line
packages.
Register
The 28000 CPU is a register-oriented
Organization machine that offers sixteen 16-bit generalpurpose registers and a set of special system
registers. All general-purpose registers can be
used as accumulators and all but one as index
registers or memory pointers.
Register flexibility is created by grouping
and overlapping multiple registers (Figures 2
and 3). For byte operations, the first eight
16-bit registers (RO ... R7) are treated as sixteen
8-bit registers (RLO, RHO, ... , RL7, RH7). The
sixteen 16-bit registers are grouped in pairs
(RRO ... RRl4) to form 32-bit long-word
registers. Similarly, the register set is grouped
in quadruples (RQO ... RQI2) to form 64-bit
registers.
General
Description
(Continued)
RO 17
RHO
Rl 115
RHl
01 7
RLO
01
RRO {
ROO
RH2
R21
R31
RH3
RL3
R41
RH4
RL4
RSC=:
RHS
RTI
RHT
RLO
R21
RH2
RL2
R31
RH3
RL3
R41
RH4
RL4
Rsl
RHS
RLS
Rsl
RHS
RLB
RTt
RH7
RL7
o
I
RR2 {
RR4 {
RLS
R04
R04
RL6
RRS {
RS
RLl
i7
ROO
RR4 {
RHS
RHO
RHl
RL2
RR2 {
Rsl
RO 17
Rl11S
RRO {
RLl
RRS {
RLT
15
RsilS
RRS {
RR8 {
R9
R91
ROS
ROS
Rl0
R101
RR10 {
RR10 {
Rll
Rlll
R12
R12t
RR12 {
RR12 {
R13
R131
SYSTEM STACK POINTER (SEG. NO.)
,,,·1
Stacks
140
R14
NORMAL STACK POINTER (SEG. NO.)
R1S
NORMAL STACK POINTER (OFFSEn
R012
SYSTEM STACK POINTER (OFFSET)
RQ1:<:
R141
" .. I
R1S'
R1S
SYSTEM STACK POINTER
NORMAL STACK POINTER
Figure 2. Z8001 General-Purpose Registers
Figure 3. Z8002 General-Purpose Registers
The 28001 and 28002 can use stacks located
anywhere in memory. Call and Return instructions as well as interrupts and trqps use implied stacks. The· distinction between normal
and system stacks separates system information
from the application program information. Two
stack pointers are available: the system stack
pointer and the normal stack pointer. Because
they are part of the general-pu:pose register
group, the user can manipulate the stack
pointers with any instruction available for
register operations.
In the 28001, register pair RR 14 is the
implied stack pointer. Register R14 contains
the 7-bit segment number and R15 contains the
16-bit offset. In the 28002, register R15 is the
implied 16-bit stack pointer.
2001-0090,0091
Refresh
Program
Status
Information
The 28000 CPU contains a counter that can
be used to automatically refresh dynamic
memory. The refresh counter register consists
of a 9-bit row counter, a 6-bit rate counter and
an enable bit (Figure 4). The 9-bit row counter
can address up to 256 rows and is incremented
by two each time the rate counter reaches endof-count. The rate counter determines the time
between successive refreshes. It consists of a
programmable 6-bit modulo-n prescaler
(n = 1 to 64), driven at one-fourth the CPU
clock rate. The refresh period can be programmed by 1 to 64 p.s with a 4 MHz clock. Refresh
can be disabled by programming the refresh
enable/disable bit.
This group of status registers contains the
program counter, flags and control bits. When
an interrupt or trap occurs, the entire group is
saved and a new program status group is
loaded.
Figure 5 illustrates how the program status
groups of the 28001 and 28002 differ. In the
non-segmented 28002, the program status
group consists of two words: the program
counter (PC), and the flag and control word
(FCW). In the segmented 28001, the program
status group consists of four words: a two-word
program counter, the flag and control word,
and an unused word reserved for future use.
Seven bits of the first PC word designate one
of the 128 memory segments. The second word
supplies the 16-bit offset that designates a
"
memory location within the segment.
With the exception of the segment enable bit
in the 28001 program status group, the flags
and control bits are the same for both CPUs.
10,0
I 0
I
o!o!
o!
o!
o!
0
t o ! o!
0
I o!·o!
o!
0
I
RESEAVED
WORD
,ROW ,
,
RATE
Figure 4. Refresh Counter
i,-'°--,-15_'N....
1E_PA..J..I_VIE...J.IN_V....IIEI_o_,,--o
.J..I_O...J.!_°-lll&~~v~~
J..1_C.J.I_Z...J.I_S....JII-Pl_VL ID_AJ..I_H
J...!_ '
ADDRESS
II
L..-.l.--..L-....I.-....I.---1-.....J...-....I...'-.J..'----l.'--l_L...-L-..L-...L-1'---.J
PROGRAM
COUNTER
Z8002 Program Status Registers
28001 Program Status Registers
, ,
j'
,
SEGMENT NUMBER
UPPER POINTER
,
!
,
Z8002 Program Status Area Pointer
, , ,
UPPER OFFSET
Z8001 Program Status Area Pointer
Figure 5.
Interrupt
and Trap
Structure
2045-0282, 0283
zaooo CPU Special Registers
The 28000 provides a very flexible and
powerful interrupt and trap structure. Interrupts are external asynchronous events requiring CPU attention, and are generally triggered
by peripherals needing service. Traps are synchronous events resulting from the execution
of certain instructions. Both are processes in a
similar manner by the CPU.
The CPU supports three types of interrupts
(non-maskable, vectored and non-vectored)
and four traps (system call, Extended Process
Architecture instruction, privileged instructions and segmentation trap). The vectored
and non-vectored interrupts are maskable. Of
the four traps, the only external one is the
segmentation trap, which is generated by the
28010.
The remaining traps occur when instructions
limited to the system mode are used in the normal mode, or as a result of the System Call instruction, or for an EPA instruction. The
descending order of priority for traps and in-"
terrupts is: internal traps, non-maskable interrupt, segmentation trap, vectored interrupt
and non-vectored interrupt.
When an interrupt or trap occurs, the current program status is automatically pushed on
the system stack. The program status consists
of the processor status (PC and FCW) plus a
16-bit identifier. The identifier contains the
reason or source of the trap or interrupt. For
internal traps, the identifier is the first word of
the trapped instruction. For external traps or
interrupts, the identifier is the vector on the
data bus read by the CPU during the
interrupt-acknowledge or trap-acknowledge
cycle.
After saving the current program status, the
new program status is automatically loaded
from the program status area in system
memory. This area is designated by the program status area pointer (PSAP).
141
Data
Types
28000 instructions can operate on bits, BCD
digits (4 bits), bytes (8 bits), words (16 bits),
long words (32 bits) and byte strings and word
strings (up to 64 kilobytes long), and word strings (up to 64 kilobytes long). Bits can be set,
reset and tested; digits are used in BCD
arithmetic operations; bytes are used for
characters or small integer values; words are
used for integer values, instructions and nonsegmented addresses; long words are used for
Segmentation
High-level languages, sophisticated operatand Memory ing systems, large programs and data bases,
Management and decreasing memory prices are all acceleratingthe trend toward larger memory requirements in microcomputer systems. The
28001 meets this requirement with an eight
Segmented
Addressing .
A segmented addressing space - compared
with linear addressing - is closer to the way a
programmer uses memory because each procedure and data space resides in its own segment. The 8 megabytes of 28001 addressing
space is divided into 128 relocatable segments
up to 64 kilobytes each. A 23-bit segmented
address uses a 7-bit segment address to point
to the segment, and a 16-bit offset to address
any location relative to the beginning of the
segment. The two parts of the segmented address may be manipulated separately. The
segmented 28001 can run any code written for
the non-segmented 28002 in anyone of its 128
segments, provided it is set to the nonsegmented mode.
Memory
The addresses manipulated by the programManagement mer, used by instructions and output by the
28001 are called logical addresses. The,
Memory Management Unit tkes the logical
addresses and transforms them into the
physical addresses required for accessing the
memory (Figure 6). This address transformation process is called relocation. Segment
relocation makes user software addresses independent of the physical memory so the user is
freed from specifying where information is
actually located in the physical memory.
The relocation process is transparent to user
software. A translation table in the Memory
Management Unit associates the 7-bit segment
number with the base address of the physical
memory segment. The 16-bit offset is added to
the physical base address to obtain the actual
physical address. The system may dynamically
reload translation tables as tasks are created,
suspended or changed.
In addition to supporting dynamiC segment
relocation, the Memory Management Unit also
provides segment protection and other segment management features. The protection
features prevent illegal uses of segments, such
as writing into a write-protected zone.
Each Memory Management Unit stores 64
segment entries that consist of the segment
142
long integer values and segmented addresses.
All data elements except strings can reside
either in registers or memory. Strings are
stored in memory only.
The basic data element is the byte. The
number of bytes us~d when manipulating a
data element is either implied by the operation
or - for strings and multiple register operations - explicitly specified in the' instruction.
megabyte addressing space. This large address
space is directly accessed by the CPU using a
segmented addressing scheme and can be
managed by the 28010 Memory Management
Unit.
In hardware, segmented addresses are contained in a register pair or long-word memory
location. The segment number and offset can
be manipulated separately or together by all
the available word and long-word operations.
When contained in an instruction, a
segmented address has two different representations: long offset and short offset. The long
offset occupies two words, whereas the short
offset requires only one and combines in one
word the 7-bit segment number with an 8-bit
offset (range 0-256). The short offset mode
allows very dense encoding of addresses and
minimizes the need for long addresses required by direct accessing of this large address space.
base address, its attributes, size and status.
Segments are variable in size from 256 bytes to
64 kilobytes in increments of 256 bytes. Pairs
of Management Units support the 128 segment
numbers available for each of the six CPU
address spaces. Within an address space,
several Management Units can be used to
create multiple translation tables.
LOGICAL ADDRESS
L..---r--r--...li
r---------
I MEMORY
MANAGMENT
UNIT
BASE
ADDRESS
REGISTER
FILE
I
I
I
I
23
L-_--I~
24·BIT PHYSICAL ADDRESS ......- - - '
L ______ __
~
Figure 6.
__-.1
Logical-to~Physical
Address
Transformation
2045-0284
The 2ilog Extended Processing Architecture
(EPA) provides an extremely flexible and
modular approach to expanding both the hardware and software capabilities of the 28000
CPU. Features of the EPA include:
Extended
Processing
Architecture
IJ
SpeCialized instructions for external processors or software traps may be added to
CPU instruction set.
&1
Increases throughput of the system by using
up to four speCialized external processors in
parallel with the CPU.
[] Permits modular design of 28000-based
systems.
I
IJ
Provides easy management of multiple
microprocessor configurations via "single
instruction stream" communication.
IJ
Simple interconnection between extended
processing units and 28000 CPU requires no
additional external supporting logic.
[J
Supports debugging of suspect hardware
against proven software.
C
Standard feature on all 2ilog 28000 CPUs ..
Specific benefits include:
[J
EPU s can be added· as the system grows and
as EPU s with specialized functions are
developed.
t:l
Control of EPUs is accomplished via a
"single instruction stream" in the 28000
CPU, eliminating many significant system
software and bus contention management
obstacles that occur in other multiprocessor
(e.g., master-slave) organization schemes.
The processing power of the 2ilog 28000
16-bit microprocessor can be boosted beyond
its intrinsic capability by Extended Processing
Architectur~. Simply stated, EPA allows the
28000 CPU to accommodate up to four Extended Processing Units (EPUs), which perform
speCialized functions in parallel with the CPU's
main instruction execution stream.
The. use of extended processors to boost the
main CPU's performance capability has been
proven with large mainframe computers and
minicomputers. In these systems, speCialized
functions such as array processing, special
inpuVoutput processing, and data communications processing are typically assigned to
extended processor hardware. These extended
processors are complex computers in their own
right.
The 2ilog Extended Processing Architecture
combines the best concepts of these proven
performance boosters with the latest in highdensity MOS integrated-circuit design. The
result is an elegant expansion of design
capability-a powerful microprocessor
architecture capable of connecting single-chip
EPUs that permits very effective parallel
processing and makes for a smoothly integrated instruction stream from the 28000 programmer's point of view. A typical addition to
the current 28000 instruction set might be
Floating Point Instructions.
The Extended Processing Uni ts connect
directly to the 28000 BUS (2-BUS) and continuously monitor the CPU instruction stream.
When an extended instruction is detected, the
appropriate EPU responds, obtaining or
placing data or status information on the
2-BUS using the 28000-generated control
signals and performing its function as directed.
The 28000 CPU is responsible for instructing
the EPU and delivering operands and data to
it. The EPU recognizes instructions intended
for it and executes them, using data supplied
MEMORY
Figure 7. Typical Extended Processor Configuration
2007-001
143
Extended
Processing
Architecture
(Continued)
with the instruction and/or data within its internal registers. There are four classes of EPU
instru ctions:
Z8000 CPU.
This software trap mechanism facilitates the
design of systems for later addition of EPUs:
initially, the extended function is executed as a
trap subroutine; when the EPU is finally
attached, the trap subroutine is eliminated and
the EPA control bit is set. Application software
is unaware of the change.
Extended Processing Architecture also offers
protection against extended instruction overlapping. Each EPU connects to the Z8000 CPU
via the STOP line so that if an EPU is
requested to perform a second extended
instruction function before it has completed the
previous one, it can put the CPU into the
Stop/Refresh state until execution of the
previous extended instruction is complete.
EPA and CPU instruction execution are
shown in Figure 8. The CPU begins operation
by fetching an instruction and determining
whether it is a CPU or an EPU command. The
EPU meanwhile monitors the Z-BUS for its own
instructions. If the CPU encounters an EPU
command, it checks to see whether an EPU is
present; if not, the EPU may be simulated by
an EPU instruction trap software routine; if an
EPU is present, the necessary data and/or
'address is placed on the Z-BUS. If the EPU is
free when the instruction and data for it
appear, the extended instruction is executed.
If the EPU is still processing a previous
instruction, it activates the CPU's STOP line to
lock the CPU off at the Z-BUS until execution
is complete. After the instruction is finished,
the EPU deactivates the STOP line and CPU
transactions continue.
• Data transfers between main memory and
EPU registers
• Data transfers between CPU registers and
EPU registers
• EPU internal operations
• Status transfers between the EPUs and the
Z8000 CPU Flag and Control Word register'
(FCW)
Four Z8000 addressing modes may be utilized
with transfers between EPU registers and the
CPU and main memory:
• Register
• Indirect Register
• Direct Address
• Indexed
In addition to the hardware-implemented ,
capabilities of the Extended Processing
Architecture, there is an extended instruction
trap mechanism to permit software simulation
of EPU functions. A control bit in the Z8000
FCW register indicates whether actual EPUs
are present or not. If not, when an extended
instruction is detected, the Z8000 traps on the
instruction, so that a software "trap handler"
can emulate the desired EPU function-a very
useful development tool. The EPA software
trap routine supports the debugging of suspect
hardware against proven software. This feature
will increase in significance as designers
become familiar with the EPA capability of the
'~
'" -EPU')
,---------------,
I
I
I
I
I
IL
_ _ _ _&.
___________
~
&. DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE EXECUTION OF AN INSTRUCTION,
Figure
144
a.
EPA and
zaooo CPU Instruction Execution
2007-002
Addressing
Modes
The information included in 28000 instructions consists of the function to be performed,
the type and size of data elements to be
manipulated and the location of the data
elements. Locations are designated by register
addresses, memory addresses or I/O
addresses. The addressing mode of a given
instruction defines the address space it references and the method used to compute the
address itself. Addressing modes are explicitly
speCified or implied by the instruction.
Mode
Immediate
Operand Value
Operand Addressing
In the Instruction
Register
Figure 4 illustrates the eight addressing
modes: Register (R), Immediate OM), Indirect
Register OR), Direct Address (DA), Indexed
(X), Relative Address (RA), Base Address (BA)
and Base Indexed (BX). In general, an addressing mode explicitly specifies either
register address space or memory address
space. Program memory address space and
I/O addrE;'!ss space are usually implied by the
instruction.
I
REGISTER ADDRESS
In Memory
In a Register
H
OPERAND
The content of the
register
1
1 OPERAND
Indirect
Register
1
Direct
Address
I
In the instruction
ADDRESS
H
t--------OI'~11
OPERAND
~--------------I'-tl
OPERAND
REG.ISTER ADDRESS
ADDRESS
Base
Address
The content of the location
w hose address is in the
register.
The content of the location
whose address is in the
instruction
The content of the location
whose address is the
address in the instruction.
offset by the content of
the register
Index
Relative
Address
1
PC VALUE
DISPLACEMENT
I--r
""'----=--.0---1
OPERAND
The content of the location
whose address is the
content of the program
count or • offset by the
displacement in the
instruction
The content of the location
whose address is the
address in the register.
offset by the displacement
in the instruction
REGISTER ADDRESS
DISPLACEMENT
The content of the location
whose address is the
address in the register.
offset by the displacement in the register
Base
hldex
Figure 9. Addressing Modes
2045-0285
145
Input/
Output
A set of I/O instructions performs 8-bit or
16-bit transfers betwen the CPU and I/O
devices. I/O devices are addressed with a
16-bi t I/O port address. The I/O port address
is similar to a memory address; however, I/O
address space need not be part of the memory
address space. I/O port and memory addresses
coexist on the same bus lines and they are
distinguished by the status outputs.
Two types of I/O instructions are available:
standard and special. Each has its own address
space. The I/O instructions include a comprehensive set of In, Out and Block I/O instructions for both bytes and words. Special I/O instructions are used for loading and unloading
the Memory Management Unit. The status information distinguishes between standard and
special I/O references.
Multi-MicroProcessor
Support
Multi-microprocessor systems are supported
in hardware and software. A pair of CPU pins
is used in conjunction with certain instructions
to coordinate multiple microprocessors. The
Multi-Micro Out pin issues a request for the
resource, while the Multi-Micro In pin is used
to recognize the state of the resource. Thus,
any CPU in a multiple microprocessor system
can exclude all other asynchronous CPUs from
a critical shared resource.
Multi-microprocessor systems are supported
in software by the instructions Multi-Micro Request, Test Multi-Micro In, Set Multi-Micro
Out and Reset Multi-Micro Out. In addition,
the eight megabyte CPU address space is
beneficial in multiple microprocessor systems
that have large memory requirements.
Instruction.
Set
Summary
The 28000 provides the following types of
instructions:
t:J Bit Manipulation
[] Load and Exchange
[] Arithmetic
IJ
Cl
Rotate and Shift
[l
Block Transfer and String Manipulation
D Input/Output
Logical
[] CPU Control
[] Program Control
Load
and
Exchange
Clock Cycles'Mnemonics
CLR
CLRB
Operands
dst
Addr.
Modes
R
IR
DA
X
EX
EXB
R.src
R
IR
DA
X
LO
LOB
LOL
R, src
R
1M
1M
1R
DA
X
BA
BX
LO
LOB
LOL
dst,R
IR
DA
X
BA
BX
LO
LOB
dst, 1M
IR
DA
X
* NS
146
= Non-Segmented
SS
Word. Byte
N5
7
8
11
12
55
5L
Long Word
N5
Operation
5L
Clear'
dst -
12
12
a
14
15
Exchange
6
12 .
15
16
16
16
R - src
18
19
3
7
5 (byte only)
7
9
10
12
10
10
13
14
14
11
12
13
17
17
8
11
12
14
14
II
14 .
15
17
17
11
14
15
55
12
12
14
15
15
15
17
18
Load into Register
5
11
R -
13
13
15
16
15
15
17
18
src
Load into Memory (Store)
dst -
R
Load Immediato into Memory
= Segmented Short Offset
SL
= Segmented Long Offset
dst - 1M
Load and
EJcchange
(Continued)
Clock Cycles
Mnemonics
Addr.
Modes
Word. By to
N5
55
8L
13
13
15
16
Long Word
N5
55
Operation
5L
LDA
R. src
DA
X
BA
BX
12
13
15
15
LOAR
R. src
RA
15
LOK
R, src
1M
5
LOM
R, src, n
IR
DA
X
11
14
15
15
15
;7 } +3n
18
Load Multiple
R - src (n consecutive words)
(n = 1 .. , 16)
IR
DA
X
11
14
15
15
15
;7 } +3n
18
Load Multiple (Store Multiple)
dst - R (n consecutive words)
(n = 1 .. , 16)
eo
C')
RA
14
Load Relative
R - src
(range -32768 ... + 32767)
n
LOM
dst,R,n
Load Address
R - source address
Load Address Relative
R - source address
Load Constant
R - n (n = 0 ... 15)
LOR
LORB
LORL
R, src
LOR
LORB
LORL
dst,R
RA
14
17
LoadRelative (Store Relative)
dst - R
(range -32768 ... +32767)
POP
POPL
dst.1R
R
1R
DA
X
8
12
16
16
12
19
23
23
Pop
dst - IR
Autoincrement contents of R
R
1M
1R
DA
X
9
12
13
14
14
PUSH
PUSHL
Arithmetic
Operands
IR, src
AOC
ADCB
R, src
R
5
AOO
ADDB
ADDL
R, src
R
1M
IR
DA
X
4
7
7
9
10
R
1M
IR
DA
X
4
7
7
9
10
IR
DA
X
11
14
15
CP
CPB
CPL
R, src
17
16
16
18
19
23
23
25
26
16
17
20
21
21
21
21
N
'G
eJ
23
24
Add with Carry
R - R + src + carry
12
13
8
14
14
15
16
10
10
12
13
8
14
14
15
16
15
15
17
18
10
10
Add
R - R + src
16
16
18
19
Compare with Register
R - src
16
16
18
19
Compare with Immediato
dst - 1M
CP
CPB
dst, 1M
DAB
dst
R
5
Docimal Adjust
dst,n
R
IR
DA
X
4
11
13
14
Decrement by n
dst - dst - n
(n = 1 ... 16)
DEC
OECB
0
lid
Push
Autodecrement contents of R
IR - src
12
14
14
00
14
14
16
17
147
Arithmetic
(Continued)
Clock Cycles
Mnemonics
DlV
DlVL
Operands
R,src
Addr.
Modes
INC
INCB
MULT
MULTL
NEG
NEGB
Logical
dst
dst.n
R, src
dst
SUB
SUBB
SUBL
R. src
OR
ORB
55
Operation
SL
Divide (signed)
X
R
11
11
Extend Sign
R
lR
DA
X
4
11
13
14
R
IR
DA
X
70
70
70
71
72
R
IR
DA
X
7
12
15
16
R
5
R
1M
IR
DA
X
R, src
dst
R, src
lR
DA
X
R
lR
DA
X
7
12
15
16
R
IR
DA
X
4
7
7
9
10
R
5
1M
cc,dst
TEST
TESTB
TESTL
dst
4
7
7
9
10
4
7
7
9
10
R
1M
Word: Rn+ 1 - Rn, n+ 1 + src
Rn - remainder
Long Word: Rn +2.n+3 - Rn ... n+3 + src
Rn, n + 1 - remainder
Increment by n
14
14
72
72
dst -- dst + n
(n = 1 ... 16)
16
17
74
75
282* 282* 282* 283* 284* 286*
284 * 284* 287*
Multiply (signed)
Word: Rn,n+ 1 -- Rn+ 1 • src
Long Word: Rn ... n+ 3 --:-.Rn+2. n+3
* Plus seven cycles for each 1 in the
multiplicand
Negate
dst -- 0 - dst
16
16
18
19
Subtract with Carry
10
10
12
13
8
14
14
15
16
R - src - carry
Subtract
R -- R - src
16
16
18
19
AND
R -- RAND src
10
10
12
13
Complement
dst -- NOT dst
16
16
18
19
OR
R - R OR src
10
10
12
13
Test Condition Code
Set LSB if cc is true
R, src
R
IR
DA-
11
X
12
R
4
7
7
9
10
1M
lR
DA
X
148
Long Word
NS
R -
TCC
TCCB
XOR
XORB
SL
744 744 744 744 744
745 746 748
746 746 749
1M
R, src
COM
COMB
55
Extend sign of low order half of dst
through high order half of dst
SBC
SBCB
AND
ANDB
NS
107
107
107 107 107
108 109 111
109 109 112
R
1M
IR
DA
EXTS
EXTSB
EXTSL
Word. Byte
7
8
12
12
14
15
13
13
16
17
Test
dst OR 0
17
17
19
20
Exclusive OR
R -- R XOR src
10
10
12
13
Program
Control
Clock Cycles
Mnemonics
CALL
Operands
d3t
Addr.
Modes
Word. Byte
X
10
12
13
18
18
15
20
21
Call Subroutine
Autodecrement SP
@ SP - PC
PC- dst
15
Call Relative
Autodecrement SP
@ SP - PC
PC - PC + dst (range -4094 to + 4096)
CA1R
dst
RA
10
DJNZ
DBJNZ
R,dst
RA
11
SS
Operation
SL
IR
NS
SL
SS
DA
Decrement and Jump if Non-Zero
R - R- 1
If R 0: PC - PC + dst (range -254 to 0)
"*
IRET'"
JP
Long Word
NS
13
. cc, dst
IR
IR
X
10
7
7
8
RA
6
DA
16
8
8
15
7
10
11
Interrupt Return
PS - @ SP
Autoincrement SP
(taken)
(not taken)
N
CO
e
<=;)
....
Jump Conditional
If cc is true: PC - dst
N
n
eu
d
JR
Bit
Manipulation
cc,dst
RET
cc
SC
src
dst,b
BIT
BITB
Jump Conditional Relative
If cc is true: PC - PC + dst
(range -256 to + 254)
10
7
13
7
1M
33
39
R
1R
DA
X
4
8
10
11
(taken)
(not taken)
Return Conditional
If cc is true: PC - @ SP
Autoincrement SP
System Call
Autodecrement SP
@ SP - old PS
Push instruction
PS - System Call PS
Test Bit Static
Z flag - NOT dst bit specified by b
11
11
13
14
BIT
BlTB
dst,R
R
10
Test Bit Dynamic
Z flag - NOT dst bit specified by
contents of R
RES
RESB
dst,b
R
1R
DA
Reset Bit Static
Reset dst bit specified by b
X
4
11
13
14
R
10
Reset Bit Dynamic
Resetdst bit speCified by contents R
R
Set Bit Static
Set dst bit specified by b
X
4
11
13
14
RES
RESB
dst,R
SET
SETB
dst,b
IR
DA
14
14
14
14
16
17
16
17
SET
SETB
dst,R
R
10
Set Bit Dynamic
Set dst bit specified by contents of R
TSET
TSETB
dst
R
1R
DA
7
11
14
15
Test and Set
S flag - MSB of dst
dst - allIs
X
15
15
17
18
'Privileged instruction. Executed in system mode only.
149
Rotate
and
Shift
Block
Transfer
and String
Manipulation
Clock Cycles
Mnemonics
Addr.
Modes
Word. Byte
NS
SS
SL
Long Word
NS
SS
Operation
SL
R
R
6forn = I
7 forn = 2
Rotato Loft
R
R
6forn = 1
7 forn :;: 2
Rotate Left through Carry
R,src
R
9
Rotato Digit Left
RR
RRB
dst,n
R
R
6 for n = 1
7forn = 2
Rotate Right
RRC
RRCB
dst.n
R
R
6forn= 1
7forn = 2
Rotate Right through Carry
RRDB
R,src
R
9
Rotato Digit Right
SDA
SDAB
SDAL
dst,R
R
SDL
SDLB
SDLL
dst,R
SLA
SLAB
SLAL
dst,n
SLL
SLLB
SLLL
dst,n
SRA
SRAB
SRAL
dst,n
SRL
SRLB
SRLL
dst,n
CPD
CPDB
Rx, src, Ry, cc
CPDR
CPDRB
Rx, src, Ry, ce
CPI
CPIB
RX' sre,Ry, cc
CPIR
CPIRB'
RX' sre, Ry, ee
RL
RLB
dst.n
RLC
RLCB
dst.n
RLDB
CPSD
CPSDB
150
Operands
(IS + 3 n)
by n bits (n = 1. 2)
by nbits (n = 1,2)
by n bits (n = 1,2)
by n bits (n
(IS + 3 n)
= 1. 2)
Shift Dynamic Arithmetic
Shift dst left or right
by contents of R
R
(15 + 3 n)
(15 + 3 n)
Shift Dynamic Logical
Shift dstleft or right
by contents of R
R
(13 + 3 n)
(13 +3 n)
Shift Left Arithmetic
by n bits
R
(13 + 3 n)
(13 + 3 n)
Shift Left Logical
by n bits
R
(13 + 3 n)
(13 + 3 n)
Shift Right Arithmetic
by n bits
R
(13 + 3 n)
(13 + 3 n)
ShUt Right Logical
by n bits
IR
20
Compare and Decrement
Rx - sre
Aulodecrement sre address
Ry - Ry - 1
IR
(11 + 9 n)
Compare. Decrement and Repeat
RX - sre
Autodeerement sre address
Ry - Ry - 1
Repeat until ee is true or Ry = 0
IR
~O
Compare and Increment
RX - src
Autoinerement sre address
Ry - Ry - 1
·IR
(II + 9 n)
Compare. Increment and Repeat
HX - src
Autoincrement src address
Ry - Ry - 1
Repeat until ec is true or Ry
dst, src, H, ec
IR
25
=0
Compare String and Decrement
dst - sre
Autodecrement dst and sre
H - R-I
~ddresses
Block Transfer
and String
Mnemonics
Manipulation
Clock Cycles
Operands
Addr.
Modes
(Continued)
CPSDR
CPSDRB
dst, src, R, cc
IR
CPSI
CPSIB
dst, src, R. cc
IR
CPSIR
CPSIRB
dst, src, R, cc
IR
Word. Byte
NS
SS
SL
(11 + 14 n)
25
(11 + 14 n)
Long Word
NS
SS
Operation
SL
Compare String. Deer. and Repeat
dst - src
Au todecrement dst and src addresses
R - R- 1
Repeat until cc is true or R = 0
Compare String and Increment
dst - src
Autoincrement dst and src addresses
R - R-l
Compare String. Incr. and Repeat
dst - src
Autoincrement dst and src addresses
R- R- 1
Repeat until cc is true or R = 0
00
~
LDD
LDDB
dst, src, R
IR
LDDR
LDDRB
dst, src, R
IR
LDI
LDIB
dst, src, R
IR
LDIR
LDIRB
dst, src, R
IR
TRDB
dst, src, R
IR
TRDRB
dst, src, R
IR
TRIB
dst, src, R
IR
TRIRB
dst, src, R
IR
TRTDB
src I, src2, R
IR
20
(11 + 9 n)
20
(11 + 9 n)
25
(11 + 14 n)
25
(11 + 14 n)
25
e
e....
Load and Decrement
dst - src
Autodecrement dst and src addresses
R - R- 1
N
fi
tV
el
Load. Decrement and Repeat
dst - src
Autodecrement dst and src addresses
R - R-l
Repeat until R = 0
Load and Increment
dst - src
Autoincrement dst and src addresses
R - R-l
Load. Increment and Repeat
dst - src
Autoincrement dst and src addresses
R - R-l
Repeat until R = 0
Translate and Decrement
dst - src (dst)
Autodecrement dst address
R - R-l
Translate. Decrement and Repeat
dst - src (dst)
Autodecrement dst address
R - R-l
Repeat until R = 0
Translate and Increment
dst - src (dst)
Autoincrement dst address
R - R-l
Translate. Increment and Repeat
dst - src (dst)
Autoincrement dst address
R - R-l
Repeat until R = 0
Translate and Test. Decrement
RHI - src 2 (src 1)
Autodecrement src 1 address
R - R-l
151
Block Transfer
and String
Mnemonics
Manipulation
(Continued)
Input/
Output
Clock Cycles
Operands
Addr.
Modes
Word. Byte
NS
SS
(11 + 14 n)
Long Word
NS
SS
Operation
SL
TRTDRB
src 1, src2, R
IR
TRTIB
src 1, src2, R
IR
TRTIRB
src 1, src2, R
IR
R, src
IR
DA
10
12
Input
R - src
IND*
INDB*
dst, src, R
IR
21
Input and Decrement
dst - src
Autodecrement dst address
R - R-l
INDR*
INDRB*
dst, src, R
IR
INI*
INIB*
dst, src, R
IR
INIR*
INIRB*
dst, src, R
IR
OUT'"
OUTB*
dst,H
IR
DA
10
12
Output
dst.- R
OUTD*
OUTDB*
dst, src, R
IR
21
Output and Decrement
dst - src
Autodecrement src address
R - R-l
OTDR*
OTDRB*
dst, src, R
IR
OUTI*
OUTIB*
dst, src, R
IR
OTIW
OTIRB*
dst, src, R
IR
IN*
INB*
25
(11 + 14 n)
(11 + 10 n)
21
(11 + 10 n)
(11 + 10 n)
21
(11 + 10 n)
'Privileged instructions. Executed in system mode only.
152
SL
Translate and Test. Decr. and Repeat
RHI - src 2 (src 1)
Autodecrement src 1 address
R - R-l
Repeat until R = a or RHI = a
Translate and Test. Increment
RHI - src 2 (src 1)
Autoincrement src 1 address
R- R- 1
Translate and Test. Incr. and Repeat
RHI - src 2 (src 1)
Autoincrement src 1 address
R - R...: 1
Repeat until R = a o~ RHl = a
Input. Decrement and Repeat
dst - src
Autodecrement dst address
R - R- 1
Repeat until R = a
Input and Increment
dst - src
Autoincrement dst address
R - R- 1
Input. Increment and Repeat
dst - src
Autoincrement dst address
R - R-l
Repeat until R = a
Output. Decrement and Repeat
dst - src
Autodecrement src address
R - R-l
Repeat until R = a
Output and Increment
dst - src
Autoincrement src address
R - R- 1
Output. Increment and Repeat
dst - src
Autoincrement src address
R - R- 1
Repeat until R = a
Input/Output
(Continued)
Clock Cycles
Mnemonics
SIN*
SINB*
Addr.
Modes
Word. Byte
NS
SS
SL
Long Word
NS
SS
Operation
SL
R, src
DA
12
Special Input
R - src
SIND*
SINDB*
dst, src, R
IR
21
Special Input and Decrement
dst - src
Autodecrement dst address
R - R- 1
SINDR*
SINDRB*
dst, src, R
IR
SINI*
SINIB*
dst, src, R
IR
SINIR*
SINIRB*
CPU
Control
Operands
dst,src,R
IR
(11 + 10 n)
21
(11 + 10 n)
Special Input. Decrement and Repeat
dst - src
Autodecrement dst address
R - R- 1
Repeat until R = 0
Special Input and Increment
dst - src
Autoincrement dst address
R - R-l
dst, src
DA
12
Special Output
dst - src
SOUTD*
SOUTDB*
dst, src, R
IR
21
Special Output and Decroment
dst - src
Autodecrement src address
R - R-l
SOTDR*
SOTDRB*
dst, src, R
IR
SOUTI*
SOUTIB*
dst, src, R
IR
SOTIR*
SOTIRB*
dst, src, R
R
COMFLG
flags
Special Output. Decr. and Repeat
dst - src
Autodecrement src address
R - R-l
Repeat until R = 0
Special Output and Increment
dst - src
Autoincrement src address
R - R-l
21
(11 + 10 n)
Special Output. Incr. and Repeat
dst - src
Autoincrement src address
R - R- 1
Repeat until R = 0
7
Complement Flag
(Any combination of C, Z,
s,
01*
int
7
Disable Interrupt
(Any combination of NVI, VI)
EI*
int
7
Enable Interrupt
(Any combination of NVI, VI)
(8 + 3 n)
HALT*
0
Special Input. Increment and Repeat
dst - src
Autoincrement dst address
R - R-l
Repeat until R = 0
SOUT*
SOUTB*
(11 + 10 n)
N
CO
PIV)
HALT
LDCTL*
CTLR,src
R
7
Load into Control Register
CTLR - src
LDCTL*
dst,CTLR
R
7
Load from Control Register
dst - CTLR
'Privileged instructions. Executed in system mode only.
153
etool
N
n
IV
c:=
CPU
Control
(Continued)
Clock Cycles
Mnemonics
Operands
Addr.
Modes
Word. Byte
NS
SS
SL
Long Word
NS
SS
Operation
SL
LDCTLB
FLGR,src
R
7
Load into Flag Byte Register
FLGR - src
LDCTLB
dst,FLGR
R
7
Load from Flag Byte Register
dst - FLGR
IR
12
16
17
LDPS*
src
DA
X
MlII,(*
MREQ*
20
20
16
22
23
Load Program Status
PS - src
7
dst
R
Test Multi-Micro Bit
Set S if Mj is Low; reset S if
(12 + 7 n)
Mi is High.
Multi-Micro Request
MRES*
5
Multi-Micro Reset
MSET*
5
Multi-Micro Set
NOP
7
No Operation
RESFLG
flag
7
Reset Flag
(Any combination of C, Z, S, PIV)
SETFLG
flag
7
Set Flag
(Any combination of C, Z, S, PIV)
• Privileged instructions. Executed in system mode only.
Condition
Codes
Code
Z
NZ
C
NC
PL
MI
NE
EQ
OV
NOV
PE
PO
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Meaning
Flag Settings
Always false
Always true
Zero
Not zero
Carry
No Carry
Plus
Minus
Not equal
Equal
Overflow
No overflow
Parity is even
Parity is odd
Greater than or equal (signed)
Less than (signed)
Greater than (signed)
Less than or equal (signed)
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
CC Field
0000
1000
0110
1110
0111
1111
1101
OlGl
1110
0110
0100
1100
0100
1100
1001
0001
1010
0010
1111
0111
1011
0011
Z = 1
Z = 0
C = 1
C=O
S = a
S = 1
Z = 0
Z = 1
PIV = 1
PIV = 0
PIV = 1
PIV = 0
(S XOR PI'l) = 0
(S XOR PIV) = 1
[Z OR (S XOR PIV)l = 0
[Z OR (S XOR PIV)l = 1
C=O
C = 1
[(C = 0) AND (Z = 0)1 = 1
(C OR Z) = 1
Note that some condition codes have identical flag settings and binary fields in the instruction:
Z = EQ, NZ = NE, C = ULT, NC = UGE, OV = PE, NOV = PO
Status
Code
Lines
154
ST3- STO
0000
000 1
0010
001 1
0100
0101
0110
01 1 1
Definition
Internal operation
Memory refresh
1/0 reference
Special 1/0 reference (e.g., to an MMU)
Segment trap acknowledge
Non-maskable interrupt acknowledge
Non-vectored interrupt acknowledge
Vectored interrupt acknowledge
ST3- STO
100 a
1001
1010
101 1
1 100
1 101
1 1 10
1111
Definition
Data memory request
Stack memory request
Data memory request (EPU)
Stack memory request (EPU)
Program reference, nth word
Instruction fetch, first word
Extension processor transfer
Reserved
Pin
Description
ADo-ADlS. Address/Data (inputs/outputs,
active High, 3-state). These multiplexed
address and data lines are used both for I/O
and to address memory.
AS. Address Strobe (output, active Low,
3-state). The rising edge of AS indicates
addresses are valid.
BUSACK. Bus Acknowledge (output, active
Low). A Low on this line indicates the CPU has
relinquished control of the bus.
BUSREQ. Bus Request (input, active Low).
This line must be driven Low to request the
bus from the CPU.
B/W. Byte/Word (output, Low = Word,
3-state). This signal defines the type of memory
reference on the 16-bit address/data bus.
CLK. System Clock (input). CLK is a 5V
single-phase time-base input.
DS. Data Strobe (output, active Low, 3-state).
This line times the data in and out of the CPU.
MREQ. Memory Request (output,. active Low,
3-state). A Low on this line indicates that the
address/data bus holds a memory address.
MI. Mo. Multi-Micro In,
Multi-Micro Out
(input and output, active Low). These two lines
form a resource-request daisy chain that allows
one CPU in a multi-microprocessor system to
access a shared resource.
NMI. Non~Maskable Interrupt (edge triggered,
input, active Low). Ahigh-to-low transition on
NMI requests a non-maskable interrupt. The
ADo
48
ADs
ADg
47
SNs
AD 10
46
SN5
AD11
45
AD7
N/S. Normal/System Mode (output, Low
NVI. Non- Vectored Interrupt (input, active
Low). A Low on this line requests a nonvectored interrupt.
RESET. Reset (input, active Low). A Low on
this line resets the CPU.
= Write,
3-state). R/W indicates that the CPU is reading
from or writing to memory or I/O.
R/W. Read/Write (output, Low
SEGT. Segment Trap (input, active Low). The
Memory Management Unit interrupts the CPU
with a Low on this line when the MMU detects
a segmentation trap. Input on Z8001 only.
SNo-SNs. Segment Number (outputs, active
High, 3-state). These lines provide the 7-bit
segment number used to address one of 128
segments by the Z80 10 Memory Management
Unit. Output by the Z8001 only.
STo-STa. Status (outputs, active High, 3-state).
These lines specify the CPU status (see table).
STOP. Stop (input, active Low). This input can
be used to single-step instruction execution.
VI. Vectored Interrupt (input, activ~ Low). A
Low on this line requests a vectored interrupt.
WAIT. Wait (input, active Low). This line
indicates to the CPU that the memory or I/O
device is not ready for data transfer.
Reserved. Do not connect.
AD12
44
ADs
ADg
ADo
43
AD4
AD10
ADs
STOP
42
SN4
AD11
AD7
MI
41
AD5
AD12
ADs
AD15
40
AD3
AD13
AD4
AD14
10
39
AD2
STOP
AD5
+5V
11
38
AD1
MI
AD3
37
SN2
AD15
AD2
36
GND
AD14
35
CLOCK
+5V
Vi
12
NVI
13
SEGT
14
ZOOO1
AD1
10
Z8002
31
GND
NMI
15
34
AS
Vi
11
RESET
16
33
RESERVED
NVI
12
Mo
17
32
BiVi
NMI
13
28
RESERVED
MREQ
18
31
N/S
RESET
14
27
Bm
os
19
30
R/W
ST3
20
29
BUSACK
ST2
21
28
WAIT
ST1
22
27
BUSREQ
STo
23
26
SNo
SN3
24
25
SN1
=
System Mode, 3-state). Nis indicates the CPU
is in the normal or system mode.
AD13
Figure 10. Z8001 Pin Assignments
2045-0286. 0287
NMI interrupt has the highest priority of the
three types of interrupts.
CLOCK
AS
Mo
15
26
N/S
MREQ
16
25
Rm
os
17
24
BUSACK
ST3
18
23
WAif
ST2
19
22
BUSREQ
ST1
20
21
STo
Figure 11. Z8002 Pin Assignments
155
zaooo
CPU
Timing
Memory
Read and
Write
The Z8000 CPU executes instructions by
stepping through sequences of basic machine
cycles, such as memory read or write, 1/0
device read or write, interrupt acknowledge,
and internal execution. Each of these basic
cycles requires three to ten clock cycles to
execute. Instructions that require more clock
cycles to execute are broken up into several
machine cycles. Thus no machine cycle is
longer than ten clock cycles and fast response
to a Bus Request is guaranteed.
The instruction opcode is fetched by a
normal memory read operation. A memory
refresh cycle can be inserted just after the
completion of any first instruction fetch (IFl)
cycle and can also be inserted while the
following instructions are being executed:
MULT, MULTL, DIV, DIVL, HALT, all Shift
instructions, all Block Move instructions, and
the Multi-Micro Request instruction (MREQ).
The following timing diagrams show the
relative timing relationships of all CPU signals
during each of the basic operations. When a
machine cycle requires additional clock cycles
for CPU internal operation, one to five clock
cycles are added. Memory and I/O read and
write, as well as interrupt acknowledge cycles,
can be extended by activating the WAIT input.
For exad timing information, refer to the composite timing diagram.
Note that the WAIT input is not synchronized
in the Z8000 and that the setup and hold times
for WAIT relative to the clock must be met. If
asynchronous WAIT signals are generated,
they must be synchronized with the CPU clock
before entering the Z8000"
Memory read and instruc~ion fetch cycles
are identical, except for the status information
on the STo-ST3 outputs. During a memory
read cycle, a 16-bit address is placed on the
ADo-ADl5 outputs early in the first clock
period, as shown in Figure 12. (In the Z8001,
T,
..
CLOCt(
T,
-I-
~
I
-
\'/AIT
STATlISI!r.
T,
--
-
l
_INSERTS WAIT STATE
(BIW. NIS.
STo-ST,)
SlIo- ml 6
SEGMENT NUMBER
AS
MRcQ
AD
MEMORY ADDRE!;S
READ
'>---
I'
(
DATA IN
')
-
05
READ
niw
READ
~
/
AD
MEMORY ADDRESS
WRITE
DATA OUT
os
WRITE
R1W
WRITE
r
\
Figuro 12. Momory Read and Writo Timing
156
2045·0288
Memory
Read and
Write
(Continued)
Input/
Output
the 7-bit segment number is output on
SNo-SN6 one clock period earlier than the
16-bit address offset to compensate for the
delay in the memory management circuitry.)
A valid address is indicated by the rising
edge of Address Strobe. Status and mode
information become valid early in the memory
access cycle and remain stable throughout.
The state of the WAIT input is sampled in the
middle of the second clock cycle by the falling
edge of Clock. If WAIT is Low, an additional
clock period is added between T2 and T3.
WAIT is sampled again in the middle of this
wait cycle, and additional wait states can be
inserted. This allows interfacing slow
memories. No control outputs change during
wait states.
Although Z8000 memory is word organized,
memory is addressed as bytes. All instructions
are word-aligned, using even addresses.
Within a 16-bit word, the most significant byte
(Ds-DI5) is addressed by the low-order address
(Ao = Low), and the least significant byte
(Do-D7) is addressed by the high-order
address
-I
WAIT
-
TWA
...... INSERT WAIT STATE
HIS
LOW
is
-
rLJ
HIGH
MREQ
AD
INPUT
-
-
ex
PORT ADDRESS
(
~)-------
i
DATA IN
> C
os
INPUT
RlW
INPUT
AD
OUTPUT
- LI
-
ex
"PORT ADDRESS
DATA OUT
os
OUTPUT
R/W
OUTPUT
2045-0289
-
"
~
Figure 13. Input/Output Timing
157
Interrupt and
Segment
Trap Request
and
Acknow ledge
The 28000 CPU recognizes three interrupt
inputs (non-maskable, vectored and nonvectored) and a segmentation trap input. Any
High-to-Low transition on the NMI input is
asynchronously edge detected and sets the
internal NMI latch. The VI, NVI and
SEGT inputs as well as the state of the internal
NMI latch are sampled at the beginning of T3
in the last machine cycle of any instruction.
In response to an interrupt or trap, the subsequent IFr cycle is exercised, but ignored.
The internal state of the CPU is not altered and
the instruction will be refetched and executed
after the return from the interrupt routine. The
program counter is not updated, but and the
system stack pointer is decremented in
preparation for pushing starting information
onto the system stack.
The next machine cycle is the interrupt
1
CLOCK
Vi, iiVi,
acknowledge cycle. This cycle has five
automatic wait states, with additional wait
states possible, as shown in Figure 14.
After the last wait state, the CPU reads the
information on ADo-AD15 and stores it temporarily, to be saved on the stack later in the
acknowledge sequence. This word identifies
the source of the interrupt or trap. For the
non-vectored and non-maskable interrupts, all
16 bits can represent peripheral device status
information. For the vectored interrupt, the
low byte is the jump vector, and the high byte
can be extra user status. For the segmentation
trap, the high byte is the Memory Management
U nit identifier and the low byte is undefined.
After the acknowledge cycle, the N/S output
indicates the automatic change to system
mode.
I
I
LAST
MACHINE
INSTRUCTIONj
ACKNCOyWCLLEEDGE -----------~. STATUS
CYClEOFANY~"-FETCHIF 1
....-----------SAVING
INSTRUCTION
(ABORTED)
AUTOMATIC .!AIT STATES
rtJ-LJiJ
I
ru= . .
T,
T,
SEaT
INTERNAL
NMl
R/W
ofw
STo- ST 3
~--~~-------------------------
,IDENTIFIER
( '-- _
_ _--J)
Figure 14. Interrupt and Segment Trap Request/ Acknowlodge Timing
Status
Saving
Sequence
The machine cycles following the interrupt
acknowledge or segmentation trap acknowledge cycle push the old status information on
the system stack (Figure 12) in the following
order: the 16-bit program counter; the 7-bit
segment number (28001 only); the flag control
Bus Request
A Low on the BUSREQ input indicates to the
Aclmowledge CPU that another device is requesting the
Timing
Address/Data and Control buses. The asynchronous BUSREQ input is synchronized at the
beginning of any machine cycle (Figure 15). If
158
word; and finally the interrupt/trap identifier.
Subsequent machine cycles fetch the new program status from the program status area, and
then branch to the interrupt/trap service
routine.
BUSREQ is Low, an internal synchronous
BUSREQ signal is generated, which-after completion of the current machine cycle-causes
the BUSACK output to go Low and all bus outputs to go into the high-impedance state. The
2045-0290
Bus Request! requesting device-typically a DMA-can then
Aclmow ledge control the bus.
When BUSREQ is released, it is synchron(Continued)
ized with the rising clock edge and the
BUSACK output goes High one clock period
later, indicating that the CPU will again take
control of the bus.
_ - - - B U S AVAILABLE-_
iiUSREQ
--~------------~----+---~~
INTERNAL
SUSRE-a
________________
~--
----
--- ----
~--
----
---- ---
----
----
~J
>--MREQ.~,----------------~~
o- 5T 31
)---
B/W, 5T
Riw,
HIS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~J
---
Figure 15. Bus Request/Acknowledge Timing
Stop
The STOP input is sampled by the last falling
clock edge immediately preceeding any IFl
cycle (Figure 16) and before the second word
of an EPA instruction is fetched. If STOP is
found Low between the IF 1 cycle, a stream of
memory refresh cycles is inserted after T3,
again sampling the STOP input on each falling
clock edge in the middle of the,T3 states. During the EPA instruction, both EPA instruction
, words are fetched but any data transfer or
subsequent instruction fetch is postponed' until
STOP is sampled High. This refresh operation
does not use the refresh p~escaler or its divideby-four clock prescaler; rather, it doubleincrements the refresh counter every three
clock cycles. When STOP is found High again,
the next refresh cycle is completed, any
remaining T states of the IFl cycle are then
executed and the CPU continues its operation.
'F,--_'1
I'
1--- - T,
T,
T3
T"
R~::ESH~I
~REF;,:SH-----:-1
T.
T,
CLOCK
DC
STOP\~!
_ _ _ _ _~\~/_ _ _ _
J\~
_____________
v
\~---I/
\ ____--J/
STO-ST3
==:><_____
'F_,_ _
---JX~
/
________
___________________
MEMORY REFRESH
____
\~
~A
_ _ _ _ _ _ _L
ruW
Figuro 16. Stop Timing
2045-0291, 0292
159
clock cycles long (Figure 17). This allows fast
response to Bus Request and Refresh Request,
because bus request or refresh cycles can be
inserted at the end of any internal machine
cycle.
Certain extended instructions, such as
Multiply and Divide, and some special instructions need additional time for the execution of
internal operations. In these cases, the CPU
goes through a sequence of internal operation
machine cycles, each of which is three to eight
T,
T,
T,
B/W
UNDEFINED
HIS
SAME AS PREVIOUS CYCLE
Figure 17. Internal Operation Timing
Memory
Refresh
When the 6-bit prescaler in the refresh
counter has been decremented to zero, a
refresh cycle consisting of three T-states is
started as soon as possible (that is, after the
next IF} cycle or Internal Operation cycle).
The 9-bit refresh counter value is put on the
low-order side of the address bus (ADo-ADa);
ADg-ADIS are undefined (Figure 18). Since
the memory is word-organized, Ao is always
Low during refresh and the refresh counter is
always incremented by two, thus stepping
through 256 consecutive refresh addresses on
ADI-ADa. Unless disabled, the presettable
prescaler runs continuously and the delay in
starting a refresh cycle is therefore not
cumulative:
While the STOP input is Low, a continuous
stream of memory refresh cycles, each three
T-states long, is executed without using the
refresh pres caler .
#
CLOCK
REFRESH
AD
lVii. BlW. Hrs
REFRESH ADDRESS
>------- --------
}_-+____-+__
-C
----t----
S_AM_EA_S_PR_EV_'OU_St-CY_CL_E
FigurQ 18. Memory Refresh Timing
160
2045·0293, 0294
Halt
A HALT instruction executes an unlimited
number of 3-cycle internal operations,
inter-spersed with memory refresh cycles
whenever requested. An interrupt, segmentation trap or reset are the only exits from a
HALT instruction.
The CPU samples the VI, NVI, NMI and
SEGT inputs at the beginning of every T3
cycle. If an input is found active during two
consecutive samples, the subsequent IF 1 cycle
is exercised, but ignored, and the normal
interrupt acknowledge cycle is started.
Reset
A Low on the RESET input causes the following results within five clock cycles (Figure 19):
are executed in the system mode. In the 28001,
the first cycle reads the flag and control word
from location 0002, the next reads the 7-bit
program counter segment number from location 0004, the next reads the 16-bit PC offset
from location 0006, and the followingIFl cycle
starts the program. In the 28002, the first cycle
reads the flag and control word from location
0002, the next reads the PC from location
0004, and the following IFI cycle starts the
program.
'm ADo-AD15 are 3-stated
II
AS, ISS, MREQ, STo-ST3,
BUSACK and MO are forced High
II
SNo-SN6 are forced Low
CI
Refresh is disabled
&I
R/W, B/W and Nis are not affected
When RESET has been High for three clock
periods, two consecutive memory read cycles
EX,
EX,
\~-------------------~>----u
l
/
----------------~
-J/
~ _____________________________J/
MREQ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-J/
IF,
STo-ST3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
BiVi
BUSACK
/
-------~
-J/
Mo _______________________
Figuro 19. Rosot Timing
2045·0295
161
Composite
AC Timing
Diagram
1
1_
~
~
~~
51
Vi,
-
1-==~
~ ...
NVI
,~
~
r-®-
~<=.
---.Y ...
r-®I""
~
~I""
:J=~
MO
This composite timing dia·
gram does not show actual
timing sequences. Refer to
this diagram only for the
detailed timing relationships
of individual edges. Use the
preceding illustrations as an
explanation of the various
timing sequences.
~
c:
59
I~:
stop
~C
~~
~~:C
WAIT
I. ~J®-
-®-j ~
"~
BUSREQ
f-
65
Timing measurements are
made at the following
voltages:
High
Low
Clock
Output
Input
Float
4.0V
2.0V
2.0V
f:::,V
0.8V
0.8V
0.8V
±0.5V
_C~
II
'I,
67
!.,
C--
~
11
)
DATA IN
~i~~
----[@
-®- -I-f®
®
~
~
MEMORY READ
r®
tf6'
...
,31
-®-V ~
H' -~
-
--
('
~
l - -®-
-®- -.-.:~
..../
-®--Ii'
~
~
rr
..../!"'
I((
S~rf:~'
REA~,
NORMAUSYSTEM,
BYTE/WORD
162
-@-
r-®-
X",
-
~
~
46
({
~I
J_
~
-
t'"
.1
~
-@-
.J)
---
/
""'---
------
~'"
~
MEMORY WRITE . . . . /
.
INTERRUPT ~
ACKNOWLEDGE
_ K:
-®rL V1""( ____
...... ""-
-®-'
INPUT/OUTPUT
I- -~ ~D
22
-®
1
-if
~
r--
I>
!@-
'-
~
1
~~
- - @ - - l-
DATA OUT
~--
~Ki.D
--0-
ADO-AD15
/-@-
t=t0
I.-
ADDRESS
,..
-l~
~
£~
~~
.,k/!"' --:tr>
",--__
-~
'"
I
2045-0296
Numbor
Symbol
Z8001/Z8002
Min
Max
Paramotor
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
Clock Fall Time
Clock Rise Time
Clock I to Segment Number Valid
(SO pF load)
TdC(SNn)
Clock I to Segment Number Not Valid
7
TdC(Bz)
Clock I to Bus Float
8
TdC(A)
Clock I to Address Valid
9
10--TdC(Az)--- Clock I to Address Float
TdA(DR)
Address Valid to Read Data Required Valid
11
TsDR(C)
Read Data to Clock I Setup Time
12
TdDS(A)
DS I to Address Active
13
14
TdC(DW)
Clock I to Write Data Valid
15--ThDR(DS)-- Read Data to DS I Hold Time
16
TdDW(DS)
Write Data Valid to DS I Delay
17
TdA(MR)
Address Valid to MREQ I Delay
18
TdC(MR)
Clock I to MREQ I Delay
19
TwMRh
MREQ Width (High)
20 - - TdMR(A)--- MREQ I to Address Not Active
Write Data Valid to DS I (Write) Delay
TdDW(DSW)
21
TdMR(DR)
MREQ I to Read Data Required Valid
22
TdC(MR)
Clock I MR~Q I Delay
23
TdC(ASf)
Clock I to AS I Delay
24
25 - - TdA(AS) - - - Address Valid to AS I Delay
TdC(ASr)
Clock I to AS I Delay
26
TdAS(DR)
AS I to ~ad Data Required Valid
27
28
TdDS(AS)
DS I to AS I Delay
29
TwAS'
AS Width (Low)
30 - - TdAS(A) - - - AS I to Address Not Active Delay
31
TdAz(DSR)
Address Float to DS (Read) I Delay
32
TdAS(DSR)
AS I to DS (Read) I Delay
33
TdDSR(DR)
DS (Read) I to Read Data Required Valid
34
TdC(DSr)
Clock I to DS I Delay
35--TdDS(DW)-- DS I to Write Data Not Valid
TdA(DSR)
Address Valid to DS (Read) I Delay
36
37
TdC(DSR)
Clock I to DS (Read) I Delay
38
TwDSR
DS (Read) Width (Low)
39
TdC(DSW)
Clock I to DS (Write) I Delay
40--TwDSW--- DS (Write) Width (Low)
41
TdDSI(DR)
DS (I/O) I to Read Data Required Valid
42
TdC(DSf)
Clock I to DS (I/O) I Delay
43
TwDS
DS (I/O) Width (Low)
44
TdAS(DSA)
AS I to DS (Acknowledge) I Delay
4S--TdC(DSA)--Clock I to DS (Acknowledge) I Delay
TdDSA(DR)
DS (Acknowledge) I to Read Data
46
Required Delay
TdC(S)
Clock I to Status Valid Delay
47
TdS(AS)
Status Valid to AS I Delay
48
TsR(C)
RESET to Clock I Setup Time
49
50--ThR(C)
RESET to Clock I Hold Time
NMI Width (Low)
TwNMI
51
TsNMl(C)
NM~ Clock I Setup Time
52
TsVI(C)
VI, NVI to Clock I Setup Time
53
54
Th Vl(C)
VI, NVI to Clock I Hold Time
55--TsSGT(C)--SEGT to Clock I Setup Time
ThSGT(C)
SEGT to Clock I Hold Time
56
TsMl(C)
MI to Clock I Setup Time
57
ThMI(C)
MI to Clock I Hold Time
58
TdC(MO)
Clock I to MO Delay
59
60--TsSTP(C)---STOP to Clock I Setup Time
ThSTP(C)
STOP to Clock I Hold Time
61
TsW(C)
WAIT to Clock I Setup Time
62
63
ThW(C)
WAIT to Clock I Hold Time
BUSREQ to Clock I Setup Time
64
TsBRQ(C)
65-- ThBRQ(C)-- BUSREQ to Clock I Hold Time
TdC(BAKr)
Clock I to BUSACK I Delay
66
, Clock I to BUSACK I Delay
TdC(BAKf)
67
Address Valid Width
TwA
68
TdDS(S)
DS I to STATUS Not Valid
69
TcC
TwCh
TwCl
4
TfC
5--TrC
TdC(SNv)
6
1
2
3
·Clock-cycle-time-dependent characteristics. See table on following page.
2S0
lOS
lOS
2000
2000
2000
20
20
130
Z8001AlZ8002A Z800lBIZ8002Bt
Min
Max
Min
Max
16S
70
70
10
20
6S
100
6S
47S*
100
0
295*
S5
60
60
90
80
45*
110*
120
85
95
80
255*
690*
120
60
85
120
10*
SO
0
SO
SO
40
10
40
0
80
0
70
8S
100
0
30
10
80
10
100
100
r Units in nanoseconds (ns).
165*
30*
70
0
70
70
SO
20
55
0
140
0
140
0
SO
10
90
10
65-
85
110
20
60
160*
410*
295*
70
0
180
0
60
75·
120*
90
120
50*
180
0
100
140
110
60
110*
110*
210*
45S*
45
25*
6S*
185*
410*
106S*
40
140*
15*
30*
20*
0
30*
70*
65
70
18S*
330*
45
40
20*
220*
35*
55*
45*
0
5S*
130*
275*
40
80*
20*
15*
140*
35*
75*
180*
SO
0
110*
20*
70
80
80
360*
70*
85*
70* .
0
80*
205*
40
SO
40180*
10
20*
135*
3S*
35*
230·
55*
10
1070
7S
80
2000
S
0
195*
35*
210*
70*
S5*
375*
100
40
40
SS
7S
SS
30S*
20
4S*
30
80*
lS0*
80*
·2000
2000
2000
10
IS
110
50
0
20
S
60
S
75
75
95*
SS*
All timings are preliminary:
60
60
SO*
30*
163
N
00
e
e....
N
n
~
c::
Number
Symbol
Z8001/Z8002
Equation
TdA(DR)
11
2TeC + TwCh - 130 ns
TdDS(A)
TwCl- 25 ns
13
TdDW(DS)
16
TeC + TwCh - 60 ns
TdA(MR)
17
TwCh - 50 ns
19--TwMRh
TeC - 40 ns
TdMR(A)
20
TwCl- 35 ns
21
TdDW(DSW)
TwCh - 50 ns
TdMR(DR)
22
2TeC - 130 ns
TdA(AS)
25
TwCh - 50 ns
27-- TdAS(DR)-- 2TeC - 140 ns
TdDS(AS)
28
TwCl- 35 ns
29
TwAS
TwCh - 20 ns
TdAS(A)
30
TwCl- 35 ns
TdAS(DSR)
32
TwCl - 25 ns
33--TdDSR(DR)-- TeC + TwCh - 150 ns
\
TdDS(DW)
35
TwCl- 30 ns
TdA(DSR)
TeC - 70 ns
36
TwDSR
TeC + TwCh - 80 ns
38
40
TwDSW
TeC - 65 ns
41--TdDSI(DR)-- 2TeC - 170 ns
43
TwDS
TdAS(DSA)
44
TdDSA(DR)
46
TdS(AS)
48
68--TwA
'69
TdDS(s)
164
2TeC - 90 ns
4TeC + TwCl - 40 ns
2TeC + TwCh - 150 ns
TwCh - 55 ns
TeC - 90 ns
TwCl- 25 ns
Z8001A/Z8002A
Equation
2TeC + TwCh - 95 ns
TWCl- 25 ns
TeC + TwCh - 40
TwCh - 35 ns
TeC - 30 ns
TwCl- .35 ns
TwCh - 35 ns
2TeC - 100 ns
TwCh - 35 ns
2TeC - 110 ns
TwCl- 35 ns
TwCh - 15 ns
TwCl- 25 ns
TwCl- 15 ns
TeC + TwCh - 105 ns
TwCl- 25 ns
TeC - 55 ns
TeC + TwCh - 50 ns
TeC - 55 ns
2TeC - 120 ns
2TeC - 75 ns
4TeC + TwCl - 40 ns
2TeC + TwCh - 105 ns
TwCh - 40 ns
TeC - 70 ns
TwCl - 15 ns
Z8001B/Z8002B
Equation
2TeC + TwCh - 60 ns
TwCl- 20 ns
TeC + TwCh - 30 ns
TwCh - 20 ns
TeC - 20 ns
TwCl - 20 ns
TwCh - 25 ns
2TeC - 60 ns
TwCh - 20 ns
2TeC - 60 ns
TwCl- 25 ns
TwCh - 10 ns
TwCl - 20 ns
TwCl - 10 ns
TeC + TwCh - 70 ns - - TwCl - 15 ns
TeC - 35 ns
TeC + TwCh - 30 ns
TeC - 25 ns
2TeC - 80 ns
2TeC - 40 ns
4TeC + TwCl - 30 ns
2TeC + TwCh - 75 ns
TwCh - 30 ns
TeC - 50 ns
TwCl- 10 ns
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Test
Conditions
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
+5V
2.1K
[] S* = O°C to + 70°C,
+4.75V!5Vee !5 +5.25V
IJ
E* = - 40°C to + 85°C,
All ac parameters assume a total load
capacitance (including parasitic capacitances)
of 100 pF max, except for parameter 6 (50 pF
max). Timing references between two output
signals assume a load difference of 50 pF max.
+4.75 V !5 Vee !5 +5.25 V
IJ
= -55°C to + 125°C,
+ 4.5 V !5 Vee !5 + 5.5 V
M*
'See Ordering Information section for package
temperature range and product number.
DC
Characteristics
8085-0006
Symbol
Parameter
Min
Max
Unit
Condition
VeH
Clock Input High Voltage
Vee- O.4
Vee+ 0 .3
V
Driven by External Clock
Generator
VeL
Clock Input Low Voltage
-0.3
0.45
V
Driven by External Clock
Generator
VIH
Input High Voltage
2.0
Vee+ 0 .3
V
VIH RESET
Input High Voltage on RESET
pin
2.4
Vee to .3
V
-0.3
0.8
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output La';'; Voltage .
2.4
0.4
V
V
IOH = -250 p.A
V
IOL = +2.0 rnA
±10
pA
100
pA
IlL
Input Leakage
IlL SEGT
Input Leakage on SEGT pin
IOL
Output Leakage
±10
p.A
ICC
Vee Supply Current
300
rnA
-100
0.4
:5
VIN
:5
+ 2.4 V
0.4 :5 VIN :5 + 2.4 V
165
Ordering
Information
Product
Number
Package/
Temp
Speed
Z8001
CE
4.0 MHz
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001A
Z8001A
Z8001A
Z8001A
Z8001A
. Z8001A
Z8002
CM
CMB
CS
DE
DS
PE
PS
CE
CS
DE
DS
PE
PS
CE
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
4.0 MHz
Z8002
Z8002
Z8002
Z8002
CM
CMB
CS
DE
4.0
4.0
4.0
4.0
MHz
MHz
MHz
MHz
Description
CPU (segmented,
48-pin)
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
CPU (nonsegmented, 40-pin)
Same as above
Same as above
Same as above
Same as above
Product
Number
Z8002
z8062
Z8002
Z8002A
Z8002A
Z8002A
za002A
Z8002A
Z8002A
Z8002A
Z8002A
Z8002B
Z8002B
Z8002B
Z8002B
Z8002B
Z8002B
Z8002B
Z8002B
Package/
Temp
Speed
DS
4.0 MHz
PE
PS
CE
CM
CMB
CS
DE
DS
PE
PS
CE
CM
CMB
CS
DE
DS
PE
PS
4.0 MHz
. 4.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
"NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -;-40°C to +85°C, M = -55°C to + 125°C, MB
MIL-STD-883 with Class B processing, S = O°C to + 70°C.
166
= -55°C to
Description
CPU (nonsegmented, 40-pin)
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
+ 125°C with
DO-2045'()3
-18003/4 Z8000™ Z·VMPU
Virtual Memory
ProcessIng Unil
Product
Specification
2:ilo9'
September 1983
FEATURES
IJ
Regular, easy-to-use architecture.
1.1
Separate System and Normal operating modes.
[J
Instruction set more powerful than many minicomputers.
a
Sophisticated interrupt structure.
El
[J
Direct addressing capability of up to 8M bytes in
each address space.
Resource-sharing capabilities for multiprocessing
systems.
c
Multi-programming support.
[J
Supports
systems.
['J
32-bit operations, including signed multiply and
divide.
D
Z_BUSTM compatible.
r.:J
Multiple clock- rates: 4, 8, or 10 MHz.
implementation
of
virtual
memory
D
Eight user-selected addressing modes.
D
Wide range of data types including bits, bytes,
words, 32-bit long words, and byte and word strings.
B
Binary-compatible with Z8001/2 CPUs.
GENERAL DESCRIPTION
The Virtual Memory Microprocessor Units (Z8003 and
Z8004 Z-VMPUs) accommodate applications that range
from the simplest to the most complex.'
The Z8003 Z-VMPU uses both segmented and
nonsegmented address spaces. It also provides facilities
for the implementation of demand segment swapping or
a demand paged virtual memory system.
The Z8004 Z-VMPU uses only nonsegmented address
spaces. It also provides facilities for the implementation
of a demand paged virtual memory system.
Both Z-VMPUs interface with the entire Z8000 Family of
support components. Used alone or with Z8000 Family
components, the advanced architecture of these LSI
Z-VMPUs permits the implementation of systems that
have the flexibility and the sophisticated features usually
associated with minicomputers or mainframe computers.
The Z8003/4 microprocessors are binary compatible
with other Z8000 Family microprocessors. The features
that distinguish these microprocessors from the Z8001
and Z8002 microproce~sors are the abort capability and
the Test anp Set status.
An abort request function aids in the implementation of
virtual memory systems. The abort function is initiated
by memory management circuitry external to the
Z-VMPU when an address issued by the Z-VMPU
references information (data or instructions) that is not in
main memory. After the abort interrupt function, a service routine must bring the page or segment containing
the addressed data into main memory. The mainstream
program is then restarted at the point of interruption. An
abort interrupt differs from a standard interrupt in that
the executing instruction is stopped immediately upon
. detection of the interrupt; this prevents the loss of information needed for a successful restart.
167
The Test and Set instruction (TSET), in addition to its
semaphore test and set function, causes status code
1111 to be placed onto output lines STo-ST3 during the
data read bus transaction. It can be used by external circuitry to lock memory to prevent it from being accessed
by any other device during the execution of the current
TSET instruction.
The Z-VMPU is designed so that a powerful memory
management system can be used to improve the utilization of the main memory either as a standard memory or
as a virtual memory configuration. Zilog produces
Memory Management Units (Z-MMUs) designed for use
with the Z8003 Z-VMPU to implement both virtual and
nonvirtual memory systems.
The architectural features of the Z-VMPU combine to
produce a powerful and versatile microprocessor. These
features result in the following benefits:
The architectural resources of the Z-VMPUs include sixteen 16-bit registers, seven data types (ranging from bits
to 32-bit words, and byte and word strings), eight addressing modes, and a powerful instruction set.
•
High-density code
•
Efficient compilation of programs
III
Support for typical operating system operations
•
Complex data structures
•
Large-scale virtual memory systems
. A general mechanism has been provided for extending
the basic instruction set through the use of external
devices called Extended Processing Units (EPUs). In
general, an EPU is dedicated to performing complex and
time-consuming tasks (such as floating-point arithmetic)
so as to unburden the Z-VMPU. FigL!re 1 shows a
simplified block diagram of the Z-VMPU. _
1--------------·
GENERAL
PURPOSE
REGISTERS
------~
I
I
I
I
I
ARITHMETIC
LOGIC
UNIT
Z·BUS
INTERFACE
INTERNAL DATA BUS
PROGRAM
STATUS
REGISTERS
INSTRUCTION
EXECUTION
CONTROL
L
EXCEPTION
HANDLING
CONTROL
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ---.JI
Z8000CPU
Figure 1. Block Diagram
168
2084-001
ARCHITECTURE
General·Purpose Registers
Special·Purpose Registers
The Z-VMPU is a register-oriented machine that contains
sixteen 16-bit general-purpose registers. All generalpurpose registers can be used as accumulators and all
but one can be used as index registers or. memory
pointers.
The Z-VMPUs also provide 16-bit special-purpose
registers. These registers include Program Status
registers, Program Status Area Pointer register(s), and a
Refresh Counter. The configurations of the specialpurpose registers for the Z8003 and Z8004 Z-VMPUs are
shown in Figure 3.
Register flexibility is created by grouping and overlapping multiple registers (Figure 2). For byte operations,
the first eight 16-bit registers can be treated as sixteen
8-bit registers. The sixteen 16-bit registers can also be
grouped in pairs to form eight 32-bit long-word registers.
Similarly, the register set can be grouped in quadruples
to form four 64-bit registers.
Stacks. Z-VMPUs can use stacks located anywhere in
main memory. Call and Return instructions, as well as interrupts and traps, use an implied stack. Two stack
pointers are available, the System Stack Pointer and the
Normal Stack Pointer. The two stacks separate
operating system (System mode) information from application program (Normal mode) information. The user
can manipulate the Stack Pointer with any instruction
available for register operations because the Stack
Pointer is part of the general-purpose register group.
In the Z8003 Z-VMPU, register pair RR14 is the implied
Stack Pointer for segmented operation. Register R14
contains the 7-bit segment number and R15 contains the
16-bit offset. Register R15 is used as the Stack Pointer
during nonsegmented operation. Since the Z8004 runs
only in the nonsegmented mode, register R15 is used as
the Stack Pointer.
R~O
{
01 7
RLO
RO 17
RHO
Rl
RHl
RLl
RH2
RL2
Program Status Registers. This group of registers consists of the Program Counter (PC) register and the Flag
and Control Word (FCW) register. The PC register contains the address of the next instruction to be loaded into
the CPU. The low-order byte of the FCW register contains the following flags:
C, Carry flag, is used to indicate that a carry was made
out of the high-order bit position of a register used as an
accumulator.
Z, Zero flag, is generally used to indicate that the result
of an operation was zero.
S, Sign flag, is generally used to indicate that the result
of an operation was negative.
P/V, Parity/Overflow flag, is generally used to indicate
either even parity (after logical operations on byte
operands) or an overflow condition (after arithmetic
operations).
D, Decimal·Adjust flag, is used in BCD arithmetic to indicate the type of instruction that was executed (addition
or subtraction).
oI
RO
RHO
Rl
RHl
RLl
R2
RH2
RL2
RL3
i7
RLO
ROO
R2
ROO
RR2 {
.RR2 {
R3
RH3
RL3
R3
RH3
R4
RH4
RL4
R4
RH4
RL4
R5
RH5
RL5
RS
RHS
RLS
R6
RH6
RL6
R6
RH6
RL6
RH7
RL7
RR4 {
RR4 {
R04
R04
RR6 {
RR6 {
R7
R8
RL7
RH7
R7
oI
15
GENERAL
PURPOSE
REGISTERS
RR8 {
R8
15
RR8 {
R9
R9
R08
RR10
{
Rl0
R08
RR10
{
Rl1
RR12
I
{
R12
RR12
{
R12
R13
'W(NSPSEG) NORMAL
'''". """'0'"''
"". "'.,
STACK POINTER (SEG. NO.)
R012
R14
RR14
R15'
R1S
Rl0
Rll
R13
• RR14
aI
RRO {
15
(NSPOFF)
SYSTEM STACK POINTER (OFFSET)
NORMAL STACK POINTER (OFFSET)
,
I'"
R1S'
R15
Z8003
R012
SYSTEM STACK POINTER (OFFSET)
NORMAL STACK POINTER (OFFSET)
Z8004
Figure 2. Z·VMPU General·Purpose Registers
2084·002
169
H, Half Carry flag, is used to convert the binary result of
a previous addition or subtraction into the correct
decimal (BCD) result.
The high-order byte of the FCW register contains control
bits which are used to control the Z-VMPU operating
modes and to enable various types of interrupts. The
following control bits are contained in the FCW:
NVIE, Nonvectored Interrupt Enable bit. This bit must
be 1 to enable the Z-VM'PU to accept non-vectored interrupts.
VIE, Vectored Interrupt Enable bit. This bit must be 1
to enable the Z-VMPU to accept vectored interrupts.
SIN, System/Normal bit. This bit indicates the current
Z-VMPU operating mode. When 0, SIN specifies Normal
mode; When 1, SIN specifies System mode. The Z-VMPU
output N/S represents the complement of this bit.
EPA, Extended Processor Architecture mode bit.
This bit, when 1, indicates that the system contains an
Extended Processing Unit (EPU) and extended instructions are to be executed by the appropriate EPU. When
0, this bit specifies that extended instructions will be
trapped for software emulation.
SEG, Segmentation mode bit (Z8003 only). When 1,
this bit specifies that the Z-VMPU is in segmented addressing mode; when 0 it specifies that the Z-VMPU is in'
the non segmented addressing mode.
15
I
Program Status Area Pointer (PSAP) Register. A Program Status Area (PSA) array in main memory is used to
store new program status information (i.e., sets of FCW
and PC values). Each time an interrupt or trap occurs,
the current program status is saved and a new program
status is loaded into the status registers from the Program Status Area. The address of the table that contains
new program status values is contained in a Program
Status Area Pointer (PSAP) register (Figure 4). The loworder byte of the offset address is assumed to be all
zeros; therefore, the Program Status Area must start on
a 256-byte boundary.
Refresh Register. The Z-VMPU contains a programmable counter that automatically refreshes dynamic
memory. The Refresh Counter register consists of a 9-bit
row counter, a 6-bit rate counter, and an Enable bit
(Figure 5). The 9-bit row counter can address up to 256
rows and is incremented by two each time the rate
counter reaches end-of-count. The rate counter determines the time between successive refreshes. It consists of a programmable, 6-bit modulo-n prescaler (n =
,1-64), driven at one-fourth the Z-VMPU clock rate.
Refresh can be disabled by programming the refresh
Enable/Disable bit. If this register is not needed for
memory refresh, it can function as an on-board internal
timer.
.
15
0
•
0
!
0
I
0'
I
0
I
0
I
0
I
0
I
0
I
0
0
I
!
0
I
0
I
0
!
0
0
} RESERVED
I
WORD
FLAG AND
CONTROL
} WORD
I°I
I
SEGMENT NUMBER
I
I
I
UPPER OFFSET
I
I
I
SEGMENT NUMBER
I
I
,
I
0
0
I
0
I
0
I
°I
0
I
°I
0
I
°I °I
0,
I
°I
0
I
0 1
°
I
°I °I
l8003
PROGRAM
COUNTER
, , ,
I
I
SEGMENT OFFSET
0
15
I
l8003
UPPER POINTER
I
I
I
I
° ! ° I ° I ° I ° I ° I ° ! °I
l8004
15
I
0
0
I SIN I EPA I VIE INVIEI 0
,
0
I
0
I C I
z
I S
I PIV I
D I H I
0 I
ADDRESS
0
I }t~~V~~
I}
L-....L..-..L.--'--~~-L---'-,--,-I---,-I--L---I.--'_'L-...L..'--,-I---I.
l8004
Figure 4. Z8003 Program Status Area
Pointer (PSAP) Registers
PROGRAM
COUNTER
RATE
I
ROW
I
I
I
I
Figure 3. Program Status Registers
Figure 5. Refresh Register/Counter
170
2084·003. 004. 005
SYSTEM AND NORMAL MODES
The Z-VMPUs can run in either System or Normal mode.
In System mode, all instructions can be executed and all
Z-VMPU control registers can be accessed. This mode is
useful in programs that perform operating system functions.
In Normal mode, some instructions, such as the 1/0 instructions, cannot be executed. In addition, the Z-VMPU
control registers cannot be accessed. This mode is intended for use by application (user) programs.
The use of separate Z-VMPU System and Normal modes
promotes the integrity of the system by preventing user
programs from having access to the operating system
and the control registers. The current operating mode is
specified by the SIN bi,t of the FCW register. The complement of the state of this bit is output by the Z-VMPU on
line N/S. Output NIS can be used to separate System and
Normal address spaces.
ADDRESS SPACES
Programs and data can be located in the main memory
of the computer system or in peripheral devices. In
either case, the location of the information must be
specified by an address before that information can be
accessed. A set of these addresses is called an address
space.
The Z-VMPUs support two different types of addresses
and thus two categories of address space:
[J
Memory addresses, which specify locations in main
memory.
o
1/0 addresses, which specify the ports through
which peripheral devices are accessed.
Within the two general types of address spaces (memory
and 1/0), there are several subcategories. Figure 6
shows the address spaces that are available on both
types of Z-VMPUs.
The difference between the Z8003 and the Z8004
Z-VMPUs lies not in the number and type' of address
spaces, but rather in the organization and size of each
space. For the Z8003, the memory address space contains 8M byte§:) of addresses grouped into 128 separate
segments. For the Z8004, the memory space is a
homogeneous collection of 64K_ bytes of addresses. In
both the Z8003 and the Z8004, each 1/0 address space
contains 32K byte port addresses and 64K word port addresses.
When an address is used to access data, the address
spaces can be distinguished by the state of the status
lines (STo-ST3) and by the value of the NormallSystem
line (N/S). The states of the four status lines are determined by the way the address was generated. The value
of the NIS output line is the complement of the SIN control bit in the FCW register.
The 23-bit segmented addresses are divided into 7-bit
segment identifiers (segment numbers) and 16-bit offsets to address locations rerative to the beginning of the
specified segment. In hardware, segmented addresses
are contained in a register pair or in a long-word memory
location. The segment number and offset of an address
can be manipulated separately or together by all
available word and long word operations.
In an instruction, a segmented address can have one or
two representations; long-offset or short-offset. A longoffset address occupies two words, with the first word
containing the 7-bit segment number and the second
word containing the 16-bit offset. A short-offset address
requires only one word, which combines the 7-bit segment number with an 8-bit offset (range 0-256). The
short-offset mode allows very dense encoding of addresses and minimizes the need for long addresses to
directly access each 8M byte address space.
Nonsegmented addresses are 16 bits and permit access
of up to 64K of contiguous byte locations.
The Z8004 operates only in the nonsegmented address
mode. The Z8003 can operate in either the segemented
or nonsegmented address mode. When the Z8003 is in
nonsegmented mode, all address representations
assume implicitly the segment number contained in the
7-bit segment number field of the PC.
110 Addresses
There is a set of 1/0 instructions that perform 8- or 16-bit
transfers between a Z-VMPU and its 1/0 devices. 1/0
devices are addressed with 16-bit 1/0 port addresses. An
1/0 port address is similar to a memory address;
however, the 1/0 address space is not part of the
memory address space. Memory-mapped 1/0 can be implemented by dedicating memory locations to 1/0 device
registers. Two types of 1/0 instruction are available:
Standard and Special, Each type has its own address
space. Special 1/0 instructions are used for loading and
unloading memory management units.
MEMORY ADDRESS SPACES
SYSTEM MODE
NORMAL MODE
INSTRUCTIONS
DATA
STACK
INSTRUCTIONS
DATA
STACK
I/O ADDRESS SPACES
SYSTEM MODE
STANDARD I/O
SPECIAL 1/0
Figure 6. Address Spaces on,the Z8003 and Z8004
2084-006
171
INSTRUCTION ADDRESSING MODES
The information included in Z-VMPU instructions consists of the function to be performed, the type and size of
data elements to be manipulated, and the locations of
the data elements. Locations are designated by register
addresses, memory addresses, or I/O addresses. The
addressing mode of a given instruction defines the
method used to compute the address. Addressing
modes are explicitly specified or implied by the instruction. Locations are designated using one of the following
addressing modes:
BI
Register Mode (R). The data element is located in
one of the 16 general-purpose registers or a control
register.
fI
Immediate Mode (1M). The data element is located
in the instruction.
II
Indirect Register Mode (IR). The data element can
be found in the location whose address is given in a
specified register.
13
Direct Address Mode (DA). The data element can
be found in the location whose address is given in
the instruction.
Gil
Index Mode (X). The data element can be found in
the location whose address is the sum of the contents of an index value in a specified register and an
address in the instruction.
f1J
Relative Address Mode (RA). The data element
can be found in the location whose address is the
sum of the contents of the Program Counter and a
displacement given in the instruction.
E!!
Base Address Mode (BA).The data element can be
found in the location whose address is the sum of a
base address in a specified register and a displacement given in the instruction.
Il]
Base Index Mode (BX). The data element can be
found in the location whose address is the sum of a
base address in one specified register and an index
value in a second specified register.
INSTRUCTION SET
Major Groups
The major groups of instructions provided by the
Z-VMPU are described in the following paragraphs. A
detailed summary of the instructions is presented in
Table 3 (located at the back of this document).
Load and Exchange. These instructions move data
among registers or between registers and main memory.
Arithmetic. These instructions perform integer
arithmetic. The basic instructions (e.g., add, subtract,
multiply and divide) in this group use standard two's
complement binary format. Support is also provided for
implementing BCD arithmetic.
Logical. These instructions perform logical operations
(i.e., AND, OR, XOR, and complementation) on the bits of
specified operands. The operands can be bytes or
words. The Test Long (TESTL) instruction, however, permits logical operations to be performed on 32-bit quantities.
. Program Control. These instructions affect the Program Counter, thereby controlling program flow.
Bit Manipulation. These instructions manipulate individual bits in registers or main memory.
Rotate and Shift. These instructions shift and rotate the
contents of registers.
Block Transfer and String Manipulation. These instructions perform string comparisons, string translations, and block transfer functions.
172
Input/Output. These instructions transfer bytes, words,
or blocks of data between peripheral devices and the
Z-VMPU registers or main memory.
Z·VMPU Control. These instructions modify Z-VMPU
control and status registers or perform those functions
that do not fit into any of the preceding. instruction
groups.
Extended. These instructions perform Extended Processor Unit (EPU) internal operations, data transfers between memory and EPU, data transfers between EPU
and the Z-VMPU, and data transfers between EPU flag
registers and the Z-VMPU Flag And Control Word (FCW).
Processor Flags
The processor flags contained by the program status
registers provide a link between sequentially executed
instructions. The link is provided in the sense that the
result of executing one instruction may alter one or more
flags. The new flag values (states) can then be used to
determine the operation of a subsequent instruction
(typically a conditional jump instruction). The following
six flags are available for use by the programmer and the
processor:
EI
Carry (C)
D " Zero (Z)
m Sign (S)
II
Parity/Overflow (PIV)
II
Decimal-Adjust (D)
III
Half Carry (H)
Table 1. Condition Codes
Code Meaning
F
Always false
T
Z
Always true
Zero
NZ
C
NC
Not zero
Carry
Z = 1
Z = 0
C = 1
No carry
C=O
PL
Plus
MI
NE
EQ
Minus
Not equal
Equal
8 = 0
8 = 1
OV
Overflow
NOV No overflow
PE
Parity is even
PO
GE
Parity is odd
Greater than or equal (signed)
LT
Less than (signed)
GT
LE
UGE
ULT
Greater than (signed)
Less than or equal (signed)
Unsigned greater than or equal
Unsigned less than
UGT Unsigned greater than
ULE Unsigned less than or equal
CC Field
Binary
Hex
Flag Settings
0000
1000
0110
1110
0111
1111
1101
Z = 0
Z = 1
PN = 1
PN = 0
PN = 1
PN = 0
(8 XOR PN) = 0
(8 XOR PN) = 1
[Z OR (8 XOR PN)] = 0
[Z OR (8 XOR PN)] = 1
C=O
C = 1
[(C = 0) AN 0 (Z = 0)] = 1
(C OR Z) = 1
Noto: Some condition codes have identical flag settings and binary fields in the instruction, i.e., Z
NOV
PO.
=
Condition Codes
Flags C, Z, S, and PIV are used to control the operation
of conditional instructions (such as Conditional Jump).
The operations performed by this type of instruction de·
pend on whether or not a specified Boolean condition ex-
0
8
6
E
7
F
0
0101
5
1110
0110
E
6
4
0100
1100
0100 .
C
1100
1001
0001
C
9
1
1010
0010
1111
0111
A
1011
0011
00
g=
4
•
W
~
CI
~
•
2
F
7
B
3
c:I
= EO, NZ = NE, C = ULT, NC = UGE, OV = PE,
ists on the four flags. Sixteen functions of the flag settings found to be frequently used are encoded in a 4-bit
condition code (CC) field, which forms a part of all conditional instructions. These 16 codes are described in
Table 1.
MULTI·MICROPROCESSOR RESOURCE
CONTROL
The Z8003 and Z8004 Z-VMPUs include both hardware
and software support for controlling access to shared
resources in multi-microprocessor systems. Z-VMPU
pins MT (Multi-Micro In) and MO (Multi-Micro Out) and instructions MSET (Set MO), MREQ (access request),
MBIT (Test MI), and MRES (reset MO) can be used to
form a prioritized resource access control system. Such
a system WOUld, for a Z-VMPU, 1), issue requests for access to a shared resource, 2) test the access status for
,the resource (available/not available) and 3) when access is granted, exclude all other Z-VMPUs in the system
from the resource until use of the resource is complete.
173
TEST AND SET
~NSTRUCTION
(TSEn
The TSET instruction implements synchronization
mechanisms in multiprogramming and multiprocessing
. environments. TSET tests and sets semaphores that
control access to shared resources. The testing and setting of a semaphore requires the semaphore to be read
from memory, modified, then written back into the same
memory location. To prevent other processors from re. questing access to a resource during a test and set process, status code 1111 is placed onto status lines
STo-ST3 during the data read transaction to specify that
an uninterruptable memory operation is taking place.
Status code 1111 is particularly useful in a multiple
microprocessor environment to permit external circuitry
to preclude memory access by another device between
the read transaction and the write transaction of the test
and set operation. Request input BUSREQ is also disabled during a test and set operation to ensure that the
test and set operation is not interrupted; this action is
useful in a single-processor system.
EXTENDED PROCESSING ARCHITECTURE
The Z-VMPU has an Extended Processing Architecture
(EPA) facility which extends the basic functions of the
Z-VMPU by using external devices called Extended Processing Units (EPUs). A special set of extended instructions controls the operations to be performed by each
EPU. When a Z-VMPU encounters an extended instruc-
tion, it either traps the instruction, or it performs the data
transfer portion of the instruction. The data manipulation
portion of the instruction is executed by the involved
EPU. Whether the Z-VMPU traps or transfers data
depends on the setting of an EPA bit in its Flag and Control Word (FCW) status register.
EXCEPTIONS
The"Z8003 and Z8004 Z-VMPUs support four types of exceptions (conditions that alter the normal flow of program execution): interrupts, traps, instruction aborts,
and reset.
Interrupt and Trap Structure
The Z8003 and Z8004 Z-VMPUs have a flexible and
powerful interrupt and trap structure. Interrupts are external events requiring Z-VMPU attention and are
generally triggered by peripherals needing service.
Traps are synchronous events resulting from the execution of certain instructions.
Both Z8003 and Z8004 Z-VMPUs support three interrupts: nonmaskable (NMI), vectored (VI), and nonvectored (NVI). .
Both Z-VMPUs support several types of traps: System
Call, EPU instruction, and privileged instruction. In addi.tion, the Z8003 supports a Segment! Address Translation
(SAn trap. Of the above traps, only the last is initiated by
external events. Such events are normally generated by
a memory management system. The remaining traps occur when instructions limited to the System mode are
used in the Normal'mode, when a System Call instruction is executed, or when an EPA instruction is encountered.
The descending order of priority for traps and interrupts
is: internal traps, nonmaskable interrupts, segment!ad-
174
dress translation traps, vectored interrupts, and nonvectored interrupts.
When an interrupt or trap occurs, the current program
status information is automatically pushed onto the
System stack. The new program status is then
automatically loaded into the Program Status registers
from the Program Status Area in System program
memory; This area of memory is identified by the Program Status Area Pointer (PSAP).
Instruction Abort Function
The Z-VMPU monitors its ABORT input during each bus
transaction it generates. The timing for ;:in Instruction
Abort operation is shown in Figure 7. If the ABORT input
is asserted during clock cycle T2 of a memory access,
the currently executing instruction is automatically
aborted. If no abort is indicated but input WAIT is
asserted, input ABORT is also tested during each wait
cycle (Tw). When an Instruction Abort condition is indicated (ABORT is asserted) the WAIT input must also be
asserted for five cycles to permit the Z-VMPU internal
control mechanism to abort the current instruction.
When the WAIT input is deasserted, the Z-VMPU
acknowledges any pending interrupt request. Therefore,
the memory management circuitry that caused the interrupt to be aborted should also request an interrupt to the
software routine that restores the Z-VMPU registers and
the main memory s6 that the aborted instruction can be
reissued;
AS
OS
SAT
ABORT
VIRTUAL ADDRESS
ABORT
ACKNOWLEDGE
CYCLE
(lid
NOTE: •
= Clock Sample Points
Figure 7. Instruction Abort Timing
VIRTUAL MEMORY SYSTEMS
Virtual memory systems permit programs to reference
an address space that exceeds the main (physical)
memory. In virtual memory systems, high-speed main
memory is supported by medium- and low-speed storage
devices (secondary memory) such as hard disks or floppy disks. When a Z-VMPU in a virtual system issues an
address that references information not in main
memory, a software swap operation must be initiated.
This swap retrieves the block containing the referenced
location, loads it into main memory, and restarts the
aborted mainstream program at the pOint of interruption.
, The swap operation is transparent to the user and to the
executing program; therefore, the system appears to
have a memory that is not constrained by physical size.
The maximum size of a virtual memory is determined by
the address structure used and by the capabilities of the
system memory management hardware and software.
Segmented and' Paged Virtual Memories
External circuitry can be used to implement either a
segmented virtual memory or a paged virtual memory. In
a segmented virtual memory, information is transferred
between main memory and secondary storage devices
on a segment-by-segment basis. The Z8003 Z-VMPU
permits use of variable-length segments of up to 64K
bytes.
In a paged virtual memory system, each segment is
divided into fixed-size pages (standard size is 2048
bytes). Main memory is divided into page ','frames." Information is then transferred between main memory and
the secondary storage devices on a page-by-page basis.
The Z8003 Z-VMPU can support both segmented or
paged virtual memory systems. The Z8004 supports,only
the paged virtual memory approach.
2084-007
External Hardware Support
The detection of a logical address that references a location outside main memory (Le., an addressing fault) and
the initiation of the required swap operation must be performed by memory management circuitry external to the
Z-VMPU.
A swap operation is started by the initiation of a
Segment/Address Translation (SAT) trap request function in the Z-VMPU. Since the Z8004 does not have a
SAT input, one of the NMI, VI or NVI inputs must be used
instead. Low levels on Z-VMPU inputs ABORT, SAT and
WAIT initiate SAT requests.
These inputs are sampled at the falling clock of the second clock cycle of a bus transaction. Input WAIT must be
asserted for at least five clock cycles. Input ABORT must
be deasserted on or before the riSing edge of the WAIT
Signal. The same timing can be used for both WAIT and
ABORT. Input SAT should be asserted until the trap~
acknowledge bus transaction is indicated by Z8003
Z-VMPU status code 0100.
External circuitry is needed to record the information for
instruction restart. The following assumptions about the
operating system must also be true:
II
The fault handler does not generate a fault until all
critical di:lta is saved.
II
Accessing the System stack never causes a fault.
(Either the segment is in memory or a memory
management mechanism warns of a potential stack
overflow.)
II
I/O buffers are always in main memory, so I/O instructions never cause a fault.
175 '
m The Program Status Area is always in main memory.
The following information must be saved by external circuitry to restart the instruction interrupted by the addressing fault:
•
The value of the Program Counter during the initial
instruction fetch cycle (cycle identified by status
code 1101).
1'1
The address that caused the fault.
II
The code that was on the status lines during the
aborted cycle.
•
For paged memories, the numb.er of successful data
accesses made by the instruction.
Software Support
The software required for virtual memory operation normally consists of a fault handler and a restart routine.
The fault handler is started during each Z-VMPU abort
request operation. The fault handler is responsible for
saving information about the aborted instruction and for
the initiation of a request which brings the segment (or
page) containing the referenced location in main
memory. The state of the aborted program (Flag and
Control Word (FCW), Program Counter (PC), and the
register file must be saved and another process dispatched while the misSing segment (or page) is being
fetched from secondary memory.
When the page or segment containing the referenced
location is loaded into main memory, an instruction
restart routine must be executed. This instruction restart
routine must restore the.operatin,g environment that existed when the instruction/program abort was initiated.
This routine must establish the PC value that points to
the aborted instruction. It must also decode the instruction's opcode to determine whether or not any of the
Z-VMPU's registers were modified before the instruction
execution cycle in which the abort occurred. If registers
were modified, the instru~tion restart routine must return
these registers to a state in which the restarted instruction behaves as if no abort had occurred. The flow chart
in Figure 8 illustrates a possible control sequence for a
software restart routine. The instructions requiring
remodification of system registers and the manner in
which these registers must be modified depend upon the
type (segmented or paged) of virtual memory system implemented.
BUS TRANSACTIONS
Status Outputs
The Z-VMPUs provide output that specifies the type of
transaction on the Address/Data bus. Output line R/W
specifies whether a read or write operation is involved.
Output line B/W specifies whether the transaction involves byte or word data. Output lineNi§" specifies the
mode of operation, Normal or System. In addition to
these lines, output lines STo-ST3 encode additional
characteristics of the current bus transaction. These
lines can present any of sixteen 4-bit status codes which
define specific characteristics of the current bus transaction. The available status codes are listed and defined
in Table 2.
Table 2. Status Codes
ST3-STO
Binary
0000
0001
0010
001 1
0100
01 01
01 1 0
o1 1 1
1000
1 001
101 0
10 11
1 100
110 1
1110
1111
Definition
Internal Operation
Memory Refresh
I/O Reference
Special I/O Reference (e.g., to an MMU)
Segment/Address Translation Trap
Acknowledge
Nonmaskable Interrupt Acknowledge
Nonvectored Interrupt Acknowledge
Vectored Interrupt Acknowledge
Data Memory Request
Stack Memory Request
Data Memory Request (Extended Processing Architecture)
Stack Memory Request, (Extended Processing Architecture)
Instruction Space Access
Instruction Fetch, First Word
Extended Processing Unit-Z-VMPU
Transfer
Bus Lock, Data Memory Request
Figure 8. Flow Chart of an Instruction Restart Routine
176
2084-008
Memory Read and Write
~emory read and instruction fetch cycles are identical,
except for the status code on the STo-ST3 outputs;'
Memory write is similar to memory read except for the
RIW status and the timing of DS and data valid true. During a memory cycle, a 16-bit offset address is placed on
the ADo-AD15 outputs early in the first clock period
(Figure 9). In the Z8003, a 7-bit segment number is also
output on SNo-SNs one clock period earlier than the
16-bit address offset. Issuing the segment number early
minimizes address translation overhead by enabling the
memory management circuitry to overlap its operations
with the Z-VMPU instruction execution cycle.
l
-
WAIT
STATU!>
The ReadlWrite line (RIW) indicates the direction of the
data transfer. R/W is High for transfers to the Z-VMPU.
RIW is Low for transfers from the Z-VMPU.
Word data (BIW is Low) to or from the Z-VMPU is
transmitted on lines ADo-AD15. Byte data to the Z-VMPU
is transmitted in AD10-AD7, from odd addresses
(ADo = 1) and in ADa-AD15 from even addresses
(ADo = 0). Byte data from the Z-VMPU is replicated in
ADo-AD7 and ADa-AD15, regardless of address.
T3
T2
1
CLOCK
A valid address is indicated by the rising edge of Address
Strobe (AS). Status and mode information becomes valid
early in the memory access cycle and remains stable
throughout it. The access cycle can be extended in
length by the addition of wait cycles.
xt
I
...--
INSERT WAIT STATE(S) AT THIS TIME
(B/W, N/S,
STo-ST3)
SNo-SNs
SEGMENT NUMBER
-
As
MREQ
READ
AD
MEMORY ADDRESS
'>--,.
(
DATAIN
>
Os
I
RIW
L
/
WRITE
AD
MEM0I:lY ADDRESS
DATA OUT
Os
RIW
r
\
Figure 9. Memory Read and Write Timing
2084-009
177
1/0 Transactions
ADo-AD15. Since the 1/0 address is always 16 bits long,
the segment number lines in Z8003 are undefined.
1/0 transactions, which are generated by the execution
of 1/0 instructions, move data to or from peripherals or
Z-VMPU support devices. As shown in the timing
diagram presented in Figure 10, 1/0 transactions have a
minimum length of four clock cycles; wait cycles can be
added to lengthen transaction periods to meet the needs
of slow peripherals. Status line outputs indicate whether
access is to the Standard 1/0 (0010) or Special 1/0 (0011)
address spaces.
For byte transfers (BIW = High) in Standard 1/0 space,
addresses must be odd; for byte transfers in Special I/O
space, addresses must be even.
Word data (BIW = Low) to or from the CPU is transmitted on ADo-AD15' Byte data (BIW = High) is transmitted
on ADo-AD15 for Special I/O. This allows peripheral
devices or CPU support devices to attach to only eight of
the 16 ADo-AD16 lines. The Read/Write line (R/W) indicates the direction of the data transfer: peripheral-toCPU (Read: R/W = High) or CPU-to-peripheral (Write:
RIW = Low).
1/0 transactions are always performed with the Z-VMPU
in System mode (NiS = Low). The rising edge of AS indicates that a valid address is present on lines
CLOCK
-
T1
T2
I
I
STATUS
-
.
Ta
I
It
XQS
ex
NIS
AS
TWA
r---
I
WAIT
(B/W. ST.-STa)
.
A"" INSERT WAIT STATE(SJ AT THIS TIME
LOW
-
~
HIGH
MREQ
INPUT
AD
-
ex
-
J
-
:x
-
r\
-
PORT ADDRESS
c=0
~>------I-
C
Ds
R/W
~
OUTPUT
AD
PORT ADDRESS
DATA OUT
Ds
I
R/W
r
Figure 10. Input/Output Transaction
178
2084-010
Wait Add·On Cycles
As shown in Figures 9 and 10, the WAIT input"line is
sampled on a falling edge of ClK one cycle before data
is sampled (DS is low for a read or write operation). If
the WAIT input line is low when sampled, another cycle
is added to the transaction before data is sampled or DS
is deasserted (goes High). During an added wait cycle,
input WAIT is sampled again on the falling clock edge; if
it is low, another wait cycle is added to the transaction.
This use of the WAIT input permits transactions to be extended arbitrarily to accommodate, for example, slow
memories or 1/0 devices that are not yet ready for data
transfer.
Memory Refresh Timing
When the 6-bit prescaler in the refresh counter has been
decremented to zero, a refresh cycle is started (Figure
11). The 9-bit refresh counter value is put on ADo-ADa;
lines ADg-AD15 are undefined. Unless disabled, the
presettable prescaler runs continuously, therefore any
delay in starting a refresh cycle is not cumulative.
While the STOP input is low, a continous stream of
memory refresh cycles is executed without using the
refresh prescaler. The refresh count, however, is incremented.
Internal Operation Timing
Certain instructions, such as multiply and divide, need
additional time to execute internal operations. In these
cases, the Z-VMPU goes through a sequence of internal
operation machine cycles, each three to eight clock
cycles long (Figure 12). This allows fast response to bus
and refresh requests because a bus request or a refresh
cycle can be inserted at the end of any internal machine
cycle.
Although the address outputs during clock cycle T1 are
undefined, Address Strobe (AS) is generated to satisfy
the requirements of Z-BUS-compatible peripherals and
self-refresh dynamic memories.
Reset Function
A low on the RESET input causes the following results
within five clock cycles (Figure 13):
1. ADo-AD15 are 3-stated. _
2. AS, DS, MREQ, BUSACK, MO, and STo-ST3 are forced
High.
3. SNo-SN6 are forced low.
4. Refresh is dis6.::Jicd.
5. RIW, BIW and Nis are undefined.
When RESET is again High, the Z8003 Z-VMPU executes
three memory read cycles in a System mode of operation. During these three word read cycles, the Z-VMPU
reads, in sequence, the following information from segment 0:
1. The flag and control word (FCW) from offset location
0002.
2. The Program Counter segment number from location
0004 and offset from location 0006.
In the Z8004 Z-VMPU, only two read cycles are performed. During the first cycle, the FCW is read from
location 0002. During the second cycle, the 16-bit PC
value is read from location 0004. The program is started
during the following machine cycle.
T,
T,
T.
CLOCK
CLOCK
STo-ST.
INTERNAL OPERATION
STo-ST.
AD
REFRESH ADDRESS
>------- --------
-C
MREQ,
Os,
R/W
)--
'--_ _+-J
HIGH
B/W
RlW. B/W. Mis
}_-+-___
Figure 11. Memory Refresh Timing
2084-011.012
-+-__
-+_S_,AM_EA_SP_RE_VIO_US+-CY_CLE_ _ _
MIS
SAME AS PREVIOUS CYCLE
Figure 12. Internal Operating Timing
179
EX,
EX,
IF,
\1.-..-.__---:--____
_ _ _ _ _ _ _--J)----M
/
--------~
MREQ
/
------------------~
M
/
-----------------~
-JI
IF,
STO-ST3 _ _ _ _ _ _ _ _ _ _
NIS
RIW
BIW
euSA« _ _ _ _ _ _ _-~1
~------_____~I
Figure 13. Reset Timing
BUS REQUEST, INTERRUPT AND
ACKNOWLEDGE
A Low on the BUSREO input indicates to the Z·VMPU
that another device is requesting the address/data and
control lines. The asynchronous BUSREQ input is synchronized at the beginning of any machine cycle (Figure
14). If BUSREO is Low, an internal synchronous
BUSREO signal is generated, which, after completion of
the current machine cycle, causes the BUSACK output
to go Low and all bus outputs to go into the highimpedance state. The requesting device (typically a
DMA) can then control the bus.
When BUSREQ is released, it is synchronized with the
rising clock edge. The BUSACK output goes High one
clock period later to indicate that the Z-VMPU will take
control of the bus.
Interrupt and Segment/Address Translation Trap
Request and Acknowledge
Any High-to-Low transition on the Z-VMPU's NMI input
(Figure 15) is asynchronously edge-detected and sets
the internal NMI latch. The VI, NVI, and SAT inputs, as
well as the state of the internal NMllatch, are sampled at
the beginning of T 3.
In response to an interrupt ortrap, the subsequent IF1
cycle is exercised. The Program Counter, however, is
180
not updated, but the System Stack Pointer is
decremented in preparation for storing status information on the System stack.
The next machine cycle is the interrupt acknowledge
cycle. This cycle has five automatic wait states, and additional wait states are possible.
After the last wait state, the Z-VMPU reads the information on ADo-AD15 and stores it temporarilY,to be saved
on the stack later in the acknowledge sequence. This
word identifies the source of the interrupt or trap. For internal traps, the identifior is the first word of the trapped
instruction. For external events, the identifier is the contents of the Data bus as sampled during T3 of the
acknowledge cycle. During nonvectored and nonmaskable interrupts, all 16 bits can represent peripheral
device status information. For the vectored interrupt, the
low byte is the jump vector, and the high byte can be
used for extra status. Fora SAT trap (assuming that a
Zilog Z8010 Z-MMU Memory Management Unit is used)
the high byte is the memory management unit identifier
and the low byte is undefined.
After the acknowledge cycle, the N/S output indicates
the automatic change to System mode.
2084·013
I....I-----ANY M
I
T,
CYCLE---~
T,
....- - - - - B U S AVAILABLE-----,.
T,
Tx
Tx
Tx
Tx
Tx
Tx
CLOCK
INTERNAL
DUSREQ
BUSACK
'---
SN
)---
AD
}---
MREQ,DS,----------------------------~
STo-ST3,
}-__
D/W, R/W, NIS __________________________+_'
I..
----
i
_ __ _
Figure 14. Bus Request/Acknowledge Timing
1
~~~l~~~~~~
INSTRUCTION
----1-
CLOCK~
IN~:;~~~~~N - j .
(IGNORED)
rtr= . .
T,
I
ACKNOWLEDGE
CYCLE
1STATUS
- - - - - - - - - - - - -.... SAVING
AUTOMATIC WAIT STATES
T,
INTERNAL
HM!
ACKNOWLEOGE
AD
(
IDENTIFIER
)
'--------'
Figure 15. Interrupt and Segment/Address translation Trap, Request/Acknowledge Timing
2084-014,015
181
PIN DESCRIPTIONS
The Z8003 Z-VMPU is produced in a 48-pin package; the
Z8004 Z-VMPU is produced in a 40-pin package. The pin
functions of both the Z8003 and Z8004 are illustrated in
Figure 16;" the pin assignments are illustrated in Fig~re
17. The signal names assigned to the Z-VMPU I/O PinS
are listed alphabetically and are described in the following paragraphs.
ABORT. Abort Request (input, active Low). This input is
used to implement virtual memory. It is asserted by external circuitry when an address does not correspond to
a location'in main memory.
When ABORT is asserted with input SAT in the Z8003, or
with input NMI, VI, or NVI in the Z8004, it initiates an
Abort Interrupt in the Z-VMPU.
ADo-AD15. Address/Data (inputs/outputs, active High,
3-state). These multiplexed address and data lines are
used both for I/O and memory.
AS. Address Strobe (output, active Low, 3-state). The rising edge of AS indicates that addresses are valid.
BUSACtC Bus Acknowledge (output, active Low). A low
on this line indicates that the Z-VMPU has relinquished
control of the bus.
BUSREQ. Bus Request (input, active Low). This line
must be driven low to request the bus from the Z-VMPU.
BUS{
TIMING
AS
. AD,s
os
AD,.
MREC:i
AD,.
=
BIW. Byte/Word (output, Low
Word, 3-state). This line
defines the size of the data being transferred.
ClK. System Clock (input). elK is a
time-base input.
DS. Data Strobe (output, active Low, 3-state). This line
strobes data in and out of the Z-VMPU.
MI,
MO. Multi-Micro In, Multi-Micro Out (input and output, active Low). These two lines form a resourcerequest daisy chain that allows only one Z-VMPU in a
multi-microprocessor system to access a shared
resource at the same time.
MREQ. Memory Request (output, active Low, 3-state). A
low on this line indicates that a memory reference is in
progress.
NMI. Nonmaskable Interrupt (edge-triggered, input, active Low). A High-to-low transition on NMI requests a
nonmaskable interrupt.
N/S. Normal/System Mode (output, Low = System
mode, 3-state). N/'S indicates the current Z-VMPU
operating mode (System or Normal).
NVI. Nonvectored Interrupt (input, active Low). A low on
this line requests a nonvectored interrupt.
RESET. Reset (input, active Low). A low on this line
resets the Z-VMPU.
As
BUS{
TIMING
AD,s
os
AD,.
MRRi
AD,.
AD,2
AD'2
REA DIWRlil:
AD"
READIWRlTE
AD"
NORMAL/S'i'S'FEM
AD,o
NORMALlsvsrrM
AD,o
BYTE/WORD
AD,
ADa
STATU{
ST.
BYTE/WORD
ST.
ST,
STo
STo
ABORT
,
BUS{
• CONTROL
-
ADDRESSI
DATA
ST2
ST,
WAiT
{~
-_
AD,
ADa
ADDRESSI
DATA
ST,
CPU
CONTROL
+ 5 V single-phase,
-
ZaOO3
_
ABORT
WAIT
STOP
BUS{ -
RESET
CPU
CONTROL {
VMPU
STOP
za004
VMPU
RESET
COUTROL
SN6
SNs
NMI
SN4
I.TERRUPTS{ :::::: Vi
SN.
NVi
SN2
lOEG"E",
NUMBER
ItITERRUPTS{
=: ~
NVI
SN,
MUL TI·MICRO {
CONTROL
SNo
MI
MULTI.MICRO{
CONTROL
Me
SAT
+5 V GND
Mi
Me
SEGMEtH·PAGE
or TRANSLATION
TRAP
t
CLK
+5 V GND
CLK
Figure 16. Pin Functions
182
2084·016
AD.
ADa
AD.
AD.
AD.
SNa
AD,.
ADa
AD,.
SNs
AD"
AD,
AD"
AD,
AD"
AD,
AD,
AD"
AD,
AD"
AD,
STOP
ADs
STOP
SN,
Mi
AD,
AD,
MI
ADs
AD"
AD"
AD,
AD"
AD,
AD"
AD,
+5V
GND
+5V
AD,
Vi
Vi
SN,
NVi
AS
NVi
GND
NMI
RESERVE;D
SAT
CLOCK
NMI
AS
RESET
RESET
ABORT
Mo
CLOCK
BtW
MO
N/S
MREQ
R/W
B/W
OS
N/S
ST,
WAIT
RiW
ST,
BUSREQ
ST,
BUSACK
ST,
ST.
ST,
WAIT
MREQ
OS
ST,
BUSREQ
ST.
SN.
SN,
SN,
BUSACK
Figure 17. Pin Assignments
INSTRUCTION SET SUMMARY
The Z8003/04 instruction set is presented in the instruction set summary. This summary lists the .mnemonics,
operands, addressing modes, timing, and operation for
each instruction.
Timing is given as the number of CPU clock cycles required for instruction execution. Timing requirements
are given for the three possible addressing representations used in word, byte and long word operations:
is contained within the instruction itself. The only instructions of this type are those using the DA and X addressing modes.
With few exceptions, timing requirements are the same
for all instructions in either segmented or nonsegmented
mode, except for those instructions that employ the SS
and SL addresses. Th.e timing for these instructions will
differ since the number of fetches needed to load the address, one word or two words, will vary.
IJ
NS
nonsegmented addresses
[J
SS
segmented short-offset addresses
NOTE
segmented long-offset addresses
Timing values are given in the SS and SLcolumns of the instruction set summary
for all addressing modes, even where the address representation does not apply.
These values are given to indicate that the time requirements .are the same for
both segmented and nonsegmented modes.
IJ
SL
The SS and SL address representations apply only to
those instructions for which the address of the operand
INSTRUCTION SET SUMMARY
The Z8003/4 provides the following types of instructions:
IJ
Bit Manipulation
[J
Load and Exchange
IJ
Rotate and Shift
IJ
Arithmetic
[J
Block Transfer and String Manipulation
EJ
Logical
[iJ
Input/Output
[J
Prog ram Control
[]
CPU Control
2084-017
183
Load and Exchange
Clock Cycles
Word, Byte
NS
SS
SL
Long Word
SS
SL
Mnemonics
Operands
CLR
CLRB
dst
R
IR
DA
X
7
8
11
12
EX
EXB
R,src
R
IR
DA
X
6
6
6
12
15
16
12
16
16
12
18
19
LO
LOB
LOL
R,src
R
1M
1M
IR
DA
X
BA
BX
3
7
5(byte
7
9
10
14
14
3
7
only)
7
10
10
14
14
3
7
5
11
5
11
5
11
7
12
13
14
14
11
12
13
17
17
11
13
13
17
17
11
15
16
17
17
11
14
15
17
17
11
15
15
17
17
11
17
18
17
17
7
8
12
12
NS
Operation
Clear
dst - 0
7
8
14
15
Exchange
R - src
Load Into Register
R - src
LO
LOB
LOL
dst,R
IR
DA
X
BA
BX
8
11
12
14
14
8
12
12
14
14
8
14
15
14
14
LO
LOB
dst, 1M
IR
DA
X
11
14
15
11
15
15
11
17
18
Load Immediate Into Memory
dst - 1M
LOA
R,src
DA
X
BA
BX
12
13
15
15
13
13
15
15
15
16
15
15
Load Address
R - source address
LOAR
R,src
RA
15
15
15
Load Address Relative
R - source address
LOK
R,src
1M
5
5
5
LOM
R,src,n
IR
DA
X
11
14
15
11
15
15
11
17
18
+3n
IR
DA
X
11
14
15
11
15
15
11
17
18
+3n
LOM
184
Addr.
Modos
dst,R,n
Load Into Memory (Store)
dst - R
Load .Constant
R - n (n = 0 ... 15)
Load Multlp!e
R - src (n consecutive words)
(n = 1 ... 16)
Load Multiple (Store Multiple)
dst ~ R (n consecutive words)
(n = 1 ... 16)
LOR
LORB
LORL
R,src
RA
14
14
14
17
17
17
Load Relative
R - src
(range -32768 ... + 32767)
LOR
LORB
LORL
dst,R
RA
14
14
14
17
17
17
Load Relative (Store Relative)
dst - R
(range -32768 ... + 32767)
POP
POPL
dst,IR
R
IR
DA
X
8
8
12
·16
16
12
16
16
8
12
18
19
12
19
23
23
12
19
23
23
12
19
25
26
Pop
dst - IR
Autoincrement contents of R
PUSH
PUSHL
IR,src
R
1M
IR
DA
X
9
12
13
13
14
9
12
13
14
14
9
12
13
16
17
12
12
12
20
21
21
20
21
21
20
23
24
Push
Autodecrement contents of R
IR - src
Arithmetic
Clock Cycles
Mnemonics
Operands
Addr.
Modes
Word, Byte
NS
SL
SS
NS
Long Word
SL
SS
Operation
ADC
ADCB
. R,src
R
5
5
5
ADD
ADDB
ADDL
R,src
R
1M
IR
4
7
7
9
10
4
7
7
10
10
4
7
7
12
13
8
14
14
15
16
8
14
14
16
16
8
14
14
18
19
4
7
7
9
10
4
7
7
10
10
4
7
7
12
13
8
14
14
15
16
8
14
14
16
16
8
14
14
18
19
11
14
15
11
15
15
11
Compare with Immediate
17
dst -1M
W
18
~
ft1
DA
X
CP
CPB
CPL
R,src
R
1M
IR
DA
X
CP
CPB
dst,IM
IR
DA
X
Add with Carry
R - R + carry + src
Add
R -
R + src
Compare with Register
R - src
DAB
dst
R
5
5
5
Decimal Adjust
DEC
DECB
dst,n
R
IR
4
11
13
14
4
11
14
14
4
11
16
Decrement by n
X
107
107
107
108
109
107
107
107
109
109
107
107
107
111
112
744
744
744
745
746
744
744
744
746
746
744
744
744
748
749
R
11
11
11
11
11
11
DA
X
DIV
DIVL
R,src
R
1M
IR
DA
EXTS
EXTSB
EXTSL
dst
INC
INCB
dst,n
ct1
~
~
e3
dst - n
= 1 ... 16)
17
4
11
13
14
4
11
14
14
4
11
16
17
70
70
70
71
72
70
70
70
72
70
70
70
74
75
X
7
12
15
16
7
12
16
16
7
12
18
19
R
5
5
5
R
IR
DA
R,src
R
1M
IR
DA
X
NEG
NEGB
e
Dlvldo (signed)
Word: Rn+ 1 - Rn,n+ 1 + src
Rn - remainder
Long Word: Rn +2,n+3 - Rn ... n +3 + src
Rn, n + 1 - remaind~r
Extend Sign
Extend sign of low order half of dst
through high order half of dst
X
MULT
MULTL
dst (n
~
~
~
dst
R
IR
DA
SBC
SBCB
R,src
SUB
SUBB
SUBL
R,src
72
Increment by n
dst + n
dst (n
= 1 ... 16)
282*
282*
282*
283*
284*
282*
282*
282*
284*
284*
282*
282*
282*
286*
287*
Multiply (signed)
Word: Rn,n+ 1 - Rn + 1 • src
Long Word: Rn ... n +3 - Rn +2,n+3 • src
* Plus seven cycles for each 1 in the
absolute value of the low order word of
the multiplicand
Negate
dst -
Subtract with Carry
R-
R
1M
IR
DA
X
4
7
7
9
10
4
7
7
10
10
4
7
7
12
13
-dst
8
14
14
15
16
8
14
14 .
16
16
8
14
14
18
19
R - src - carry
Subtract
R-
R - src
185
Logical
Clock Cycles
Word, Byte
NS
SS
SL
Mnemonics
Operands
Addr.
Modes
AND
ANDB
R,src
R
4
4
4
1M
IR
DA
X
7
7
7
7
7
7
9
10
10
10
12
13
R
IR
DA
X
7
7
7
12
15
16
12
16
16
12
18
19
R
4
4
4
1M
IR
DA
X
7
7
7
7
7
7
9
10
10
10
12
13
R
IR
DA
X
7
7
7
8
11
12
8
12
12
8
14
,15
COM
COMB
dst
OR
ORB
R,src
TEST
TESTB
TESTL
dst
NS
Long Word
SS
SL
Operation
And
R - RAND src
Complement
dst - NOT dst
OR
R-
13
13
16
17
13
13
17
17
13
13
19
20
R OR src
Test
dst OR 0
TCC
TCCB
cC,dst
R
5
5
5
Test Condition Code
Set LSB if cc is true
XOR
XORB
R,src
R
4
4
4
1M
7
7
7
7
exclusive OR
R - R XOR src
IR
DA
X
7
7
9
10
10
10
12
13
Addr.
Modes
Word, Byte
S'L
NS
SS
Program Control
Clock Cycles
Operands
CALL
dst
IR
DA
X
10
12
13
15
18
18
15
20
21
Call Subroutine
Autodecrement SP
@ SP - PC
PC - dst
CALR
dst
RA
10
15
15
Call Relatlvo
Autodecrement SP
@ SP - PC
PC - PC + dst
(range -4094 to + 4096)
DJNZ
DBJNZ
R,dst
RA
11
11
11
Decremont and Jump If Non·Zero
R - R-1
If R *- 0: PC - PC + dst
(range -254 to 0)
13
16
16
Interrupt Return
PS - @ SP
Autoincrement SP
10
15
15
7
7
7
7
8
8
10
11
IRET*
JP
186
Long Word
SL
SS
Mnemonics
cC,dst
IR
IR
DA
X
8
NS
(taken)
(not taken)
Operation
Jump Conditional
If cc is true: PC - dst
Program Control (Continued)
Clock Cyclos
Mnomonics
Operands
RET
cc
SC
src
Addr.
Modes
1M
Long Word
SL
SS
Word, Byte
NS
SS
SL
NS
10
7
13
7
13
7
(taken)
(not taken)
33
39
39
Oporation
Roturn Conditional
If cc is true: PC - @SP
Autoincrement SP
Systom Call
Autoincrement SP
@ SP - Old PS
Push Instruction
PS - System Call PS
BIT
BITB
BIT
BITB
dst,b
dst,R
4
8
11
11
4
8
13
14
Tost Bit Static
X
4
,8
10
11
R
10
10
10
Tost Bit Dynamic
R
IR
DA
Z flag -
NOT dst bit specified by b
N
00
0
C
·Privileged instructions. Executed in system mode only.
•
Bit Manipulation
c::I
(:)
Z flag - NOT dst bit specified by
contents of R
1M
•
CI
•..,
Clock Cycles
Mnemonics
Oporands
RES
RESB
dst,b
RES
RESB
dst,R
SET
SETB
dst,b
SET
dst,R
Addr.
Modos
Word, Byto
NS
SS
SL
R
IR
DA
X
4
11
13
14
4
11
1ll
14
4
11
16
17
R
10
10
10
NS
Long Word
S5
SL
Rosot Bit Static
Reset dst bit specified by b
Resot Bit Dynamic
Reset dst bit specified by contents R
R
IR
4
11
4
11
4
11
R
10
10
10
-SETB
TSET
TSETB
Oporatlon
Sot Bit Static
Set dst bit specified by b
Sot Bit Dynamic
Set dst bit specified by contents of R
dst
X
7
11
14
15
Clock Cyclos
Word, By to
Long Word
SL
NS
SS
SL NS
SS
R
IR
DA
7
11
15
15
7
11
17
18
Tost and Sot
S flag - MSB of dst
dst - all 1s
Rotate and Shift
Mnemonics
Operands
Addr.
Modos
RLDB
R,src
R
9
9
9
Rotato Loft Digit
RRDB
R,src
R
9
9
9
Rotato Right Digit
RL
RLB
dst,n
R
R
6 for n = 1
7 for n=2
Rotato Loft
RLC
RLCB
dst,n
R
R
6 fO'r n = 1
7 for n=2
Rotato Loft through Carry
RR
RRB
dst,n
R
R
6 for n = 1
7 for n=2
Rotato Right
Oporatlon
Rotate dst by n bits (n = 1,2)
Rotate dst by n bits (n = 1,2)
Rotate dst by n bits (n = 1,2)
187
Rotate and Shift (Continued)
Mnemonics
Operands
RRC
RRCB
dst,n
SDA
SDAB
SDAL
dst,R
SDL
SDLB
SDLL
dst,R
SLA
SLAB
SLAL
dst,n
SLL
SLLB
SLLL
dst,n
SRA
SRAB
SRAL
dst,n
SRL
SRLB
SRLL
dst,n
Addr.
Modes
Clock Cycles
Word, Byte
Long Word
SL NS
SL
NS
SS
SS
R
R
6 for n= 1
7 for n=2
R
(15
+
Operation
Rotate Right through Carry
Rotate dst by n bits (n = 1,2)
3n)
(15
+
3n)
Shift Dynamic Arithmetic
Shift dst left or right by contents of R
R
(15
+
3n)
(15
+
3n)
Shift Dynamic Logical
Shift dst left or right by contents of R
R
(13
+
3n)
(13
+
3n)
Shift Left Arithmetic
Shift dst left by n bits
R
(13
+
3n)
(13
+
3n)
Shift Left Logical
Shift dst left by n bits
R
(13
+
3n)
(13
+
3n)
Shift Right Arithmetic
Shift dst right by n bits
/R
(13
+
3n)
(13
+
3n)
Shift Right Logical
Shift dst right by n bits
Block Transfer and String Manipulation
Addr.
Modes
Clock Cycles
Word, Byte
Long Word
SL NS
NS
SS
SS
SL
Operation
20
Compare and Decrement
Mnemonics
Operands
CPD
CPDB
Rx,sre,
Ry,ee
IR
CPDR
CPDRB
Rx,src,
Ry,ce
IR
CPI
CPDRB
Rx,src,
Ry,ee
IR
CPIR
CPIRB
Rx,sre,
Ry,ce
IR
CPSD
CPSDB
dst,sre,
R,ee
IR
CPSDR
CPSDRB
dst,sre,
R,ee
IR
188
20
20
Rx - sre
Autodeerement sre address
Ry - Ry - 1
(11
+
Compare, Decrement and Repeat
9n)
Rx - sre
Autodeerement sre address
Ry-Ry-1
Repeat until ec is true or Ry = 0
20
20
20
Compare, Decrement and Repeat
Rx - sre
Autodeerement sre address
Ry - Ry-1
(11
+
Compare, Increment and Repeat
9n)
Rx - sre
Autoinerement src address
Ry - Ry-1
Repeat until ec is true or Ry = 0
25
25
25
Compare String and Decrement
dst - src
Autodeerement dst and sre addresses
R - R-1
(11
+
14n)
Compare String, Decrement and Repeat
dst - src
Autodeerement dst and src addresses
R - R-1
Repeat until ee is true or R = 0
Block Transfer and String Manipulation (Continued)
Clock Cycles
Addr.
Modes
Word, Byte
SL
NS
SS
25
Mnemonics
Operands
CPSI
CPSIB
dst,src,
R,cc
IR
CPSIR
CPSIRB
dst,src,
R,cc
IR'
25
25
NS
Long Word
SL
SS
Operation
Compare String and Incremont
dst - src
Autoincrement dst and src addresses
R +- R-1
(11
+
Comparo String,
14n)
Incromon~
and Ropeat
dst - src
Autoincrement dst and src addresses
R +- R-1
Repeat until cc is true or R
0
=
LDD
LDDB
dst,src, R
LDDR
LDDRB
dst,src, R
IR
20
20
20
Load and Docromont
dst +- src
Autodecrement dst and src addresses
R +- R-1
IR
(11
+
N
03
8W
;;;
Load, Decromont and Ropoat
9n)
dst +- src
Autodecrement dst and src addresses
R +- R-1
Repeat until R
0
't'i
IItI
•
=
LDI
LDIB
dst,src, R
LDIR
LDIRB
dst,src, R
IR
20
20
20
l1iJ
C1
Load and Incromont
dst +- src
Autoincremerit dst and src addresses
R - R-1
IR
(11
+
Load, Incromont and Ropoat
9n)
dst +- src
Autoincrement dst and src addresses
R +- R-1
Repeat until R
0
=
TRDB
dst,src, R
IR
25
25
25
Translate and Docremont
dst +- src (dst)
Autodecrement dst address
R +- R-1
TRDRB
dst,src, R
IR
(11
+
Translate, Decromont and Ropeat
14n)
dst +- src (dst)
Autodecrement dst address
R +- R-1
Repeat until R
0
=
TRIB
dst,src, R
IR
25
25
25
Translate and Increment
dst +- src (dst)
Autoincrement dst address
R - R-1
TRIRB
dst,src, R
IR
(11
+ 14~)
Translate, Increment and Ropoat
dst +- src (dst)
Autoincrement dst address
R +- R-1
Repeat until R
0
=
TRTDB
src1, src2, R
IR
25
25
25
Translate and Test, Docrement
RH1 +- src 2 (src1)
Autodecrement src1 address
R - R-1
TRTDRB
src1 ,src2, R
IR
(11
+
14n)
Translate and Tost, Decroment
and Repeat
RH1 +- src2 (src1)
Autodecrement src1 address
R - R-1
Repeat until R
0 or RH1
0
=
=
189
Block Transfer and String Manipulation (Continued)
Clock Cycles
Mnemonics
Operands
Addr.
Modes
Word, Byte
NS
SS
SL
TRTIB
src1, src2, R
IR
25
TRTIRB
src1 ,src2, R
IR
(11
25
+
NS
Long Word'
SS
SL
Operation
Translate and Test, Increment
RH1 - src2 (src1)
Autoincrement src1 address
R - R-1
25
Translate and Test, Increment
and Repeat
RH1 - src2 (src1)
Autoincrement src1 address
R - R-1
Repeat until R = 0 or RH1 = 0
14n)
Input/Output
Clock Cycles
Addr.
Modes
Word, Byte
NS
SL
SS
Long Word
SS
SL
Operation
Mnemonics
Operands
IN·
INB·
R,src
IR
DA
10
12
10
12
10
12
Input
R - src
IND·
INDB·
dst,src,R
IR
21
21
21
Input and Decrement
dst - src
Autodecrement dst address
R - R-1
IN DR·
INDRB·
dst,src, R
IR
(11
INI·
INIB·
dst,src, R
IR (
21
INIR·
INIRB·
dst,src,R
IR
(11
OUT·
OUTB·
dst,R
IR
DA
10
12
10
12
10
12
Output
dst - R
OUTD·
OUTDB·
dst,src, R
IR
21
21
21
Output and Decrement
dst - src
Autodecrement src address
R - R-1
OTDR·
OTDRB·
dst,src,R
IR
(11
OUTI·
OUTIB·
dst,src,R
IR
21
190
+
+
+
Input, Decrement and Repeat
dst - src
Autodecrement dst address
R - R-1
Repeat until R = 0
10n)
21
21
Input and Increment
dst - src
Autoincrement dst address
R - R-1
Input, Increment and Repeat
dst - src
Autoincrement dst address
R - R-1
Repeat until R = 0
10n)
Output, Decrement and Repeat
dst - src
Autodecrement src address
R - R-1
Repeat until R = 0
10n)
21
NS
21
Output and Increment
dst - src
Autoincrement src address
R - R-1
Input/Output (Continued)
Clock Cycles
Mnemonics
Operands
Addr.
Modes
OTIR*
OTIRB*
dst,src, R
IR
Word, Byte
NS
SS
SL
(11
+
NS
Long Word
SS
SL
Operation
Output, Increment and Repeat
dst - src
Autoincrement src address
R - R-1
Repeat until R
0
10n)
=
SIN*
SINB*
R,src
SIND*
SINB*
dst,src, R
IR
21
SINDR*
SINDRB*
dst,src, R
IR
(11
DA
12
12
12
Special Input
R-
21
+
21
src
Special Input and Decrement
dst - src
Autodecrement dst address
R - R-1
N
CD
Special Input, Decrement and Repeat
dst - src
Autodecrement dst address
R - R-1
Repeat until R
0
10n)
§
•
"•..
=
CI
SINI*
SINIB*
dst,src,R
SINIR*
SINIRB*
dst,src, R
IR
21
21
21
Special Input and Increment
dst - src
Autoincrement dst address
R - R-1
IR
(11
+
CI
Special Input, Increment and Repeat
dst - src
Autoincrement dst address
R - R-1
Repeat until R
0
10n)
=
SOUT*
SOUTe*
dst,src
DA
12
12
12
Special Output
dst - src
SOUTD*
SOUTDB*
dst,src, R
IR
21
21
21
Special Output and Decrement
dst - src
Autodecrement src address
R - R-1
SOTDR*
SOTDRB*
dst,src, R
IR
(11
+
Special Output, Decrement and Repeat
dst - src
Autodecrement src address
R - R-1
Repeat until R
0
10n)
=
SOUTI*
SOUTIB*
dst,src,R
IR
21
SOTIR*
SOTIRB*
dst,src, R
R
(11
21
+
10n)
21
Special Output and Increment
dst - src
Autoincrement src address
R - R-1
Special Output, Increment and Repeat
dst - src
Autoincrement src address
R - R~ 1
0
Repeat until R
=
*Privileged instructions. Executed in system mode only.
191
CPU Control
Mnemonics
Operands
COMFLG
flags
Addr.
Modes
Clock Cycles
Word, Byte
Long Word
NS
SS
SL NS
SS
SL
7
7
7
Operation
Complement Flag
(Any combination of C,Z,S,PIV)
01*
int
7
7
7
Olsable Interrupt
(Any combination of NVI, VI)
EI*
int
7
7
7
Enable Interrupt
(Any combination of NVI, VI)
HALT*
LOCTL*
(8
CTLR,src
R
+
HALT
3n)
7
7
7
Load Into Control Register
CTLR -
LOCTL*
dst,CTLR
R
7
7
7
Load from Control Register
dst -
LOCTLB
FLGR,src \
R
7
7
7
src
CTLR
Load Into Flag Byte Register
FLGR -
LOCTLB
dstFLGR
R
7
7
7
Load from Flag Byte Register
dst -
LOPS*
src
IR
DA
X
MBIT*
12
16
17
16
20
20
16
22
23
7
7
7
src
FLGR
Load Program Status
PS -
src
Test Multl·Mlcro Bit
Set S if MI is Low;
clear S if MI is High
MREQ*
dst
R
(12
+
Multl·Mlcro Request
7n)
MRES*
5
5
5
Multl·Mlcro Reset
MSET*
5
5
5
Multl·Mlcro Set
NOP
7
7
7
No Operation
7
7
7
RESFLG
flag
Reset Flag
(Any combination of C,Z,S,PIV)
SETFLG
flag
7
7
7
Set Flag
(Any combination of C,Z,S,PIV)
·Prlvlleged Instructions. Executed In system mode only.
192.
Extended Instructions
Clock Cycles
Addr.
Modes
Function
Memory -
EPU
IR
X
DA
EPU -
Memory
IR
X
DA
N5
5L
55
Operation
(11
(15
(14
+
+
+
3n)
3n)
3n)
(11
(15
(15
+ 3n)
+ 3n)
+ 3n)
(11
(18
(17
+ 3n)
+ 3n)
+ 3n)
Load Memory from EPU
Write n words from EPU into memory
(11
(15
(14
+ 3n)
+ 3n)
+ 3n)
(11
(15
(15
+ 3n)
+ 3n)
+ 3n)
(11
(18
(17
+ 3n)
+ 3n)
+ 3n)
Load EPU from Memory
Read n words from memory into EPU
CPU -
EPU Registers
(11
+
4n)
(11
+ 4n)
(11
+ 4n)
Load VMPU from EPU
Transfer n words from EPU to Z-VMPU registers
EPU -
CPU Registers
(11
+
4n)
(11
+ 4n)
(11
+ 4n)
Load EPU from VMPU
Transfer n words from Z-VMPU registers to EPU
Flags
EPU
+-
+-
EPU
15
15
15
Load FCW from EPU
Load information from EPU into flags of the
Z-VMPU's Flag and Control Word
Flags
15
15
15
Load EPU from FCW
Transfer information from Z-VMPU's Flag and
Control Word to EPU
EPU Internal Operations
(11
+
4n)
(11
+ 4n)
(11
+
4n)
Internal EPU Operations
Z-VMPU treats this template. as a "no-operations";
it is typically used to initiate an internal EPU
operation. The character is a field in the
instruction.
193
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs
with respect to GND ............... -0.3 V to
Operating Ambient Temperature ....... ooe to
+ 7.0 V
+ 70°C
Storage Temperature.' ............ -65°C to + 150 °e
Stresses greater than those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; operation of the device at any condition beyond those indicated in
the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
STANDARD TEST CONDITIONS
Standard test temperature/operating voltage ranges are
presented below. All voltages are referenced to GND.
Positive current flows into the referenced pin.
+ 70°C, + 4.75 V ~
!II -40°C to + 85°C, + 4.75 V
a -55°C to + 125°C, + 4.5 V
•
ooe to
Vee ~
~
Vee
~
Vee
+5V
+ 5.25 V
~ + 5.25V
~ + 5.5V
All ac parameters assume a load capacitance of 100 pF
max, except for parameter 6, which has a load
capacitance of 50 pF max. Timing references between
two output signals assume a load difference of 50 pF
max.
Figure 18. Standard Test Load
DC CHARACTERISTICS
Symbol
VCH
VCl
VIH
Vil
VOH
VOL
III
IOl
lee
Parameter
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Min
Max
Unit
Vcc- O.4
-0.3
2.0
Vcc+ 0 .3
0.45
V
V
-0.3
2.4
Vce+ 0 .3
0.8
Output Low Voltage
Input Leakage
Output Leakage
0.4
± 10
±10
Vee Supply Current
300
Condition
Driven by External Clock Generator
Driven by External Clock Generator
V
V
V
V
A
A
mA
IOH
= -250 A
=
+2.0 mA
IOl
0.4 VIN + 2.4 V
0.4 VOUT + 2.4 V
AC CHARACTERISTICSt
Number
Symbol
Parameter
1
2
3
4
5
6
TcC
TwCh
TwCI
TfC
TrC.
TdC(SNv)
7
8
9
10
11
12
13
14
15
16
TdC(SNn)
TdC(Bz)
TdC(A)
TdC(Az)
TdA(DR)
TsDR(C)
TdDS(A)
TdC(DW)
ThDR(DS)
TdDW(DS)
Clock Cycle Time
Clock Width (High)
Clock Width (Low)
Clock Fall Time
Clock Rise Time
Clock t to Segment Number Valid
(50 pF load)
Clock t to Segment Number Not Valid
Clock t to Bus Float
Clock t to Address Valid
Clock t to Address Float
Address Valid to Read Data Required Valid
Read Data to Clock I Setup Time
DS t to Add ress Active
Clock t to Write Data Valid
Read Data-to DS t Hold Time
Write Data Valid to DS t Delay
194
Z80031Z8004
(4 MHz)
Min
Max
250
105
105
2000
2000
2000
20
20
130
20
Z8003A1Z8004A Z80038/Z80048
(6 MHz)
(10 MHz)
Min
Max
Min
Max
165
70
70
10
65
100
65
475*
30
80*
100
40
40
5
20
45*
40
50
40
180*
10
20*
75
0
195*
2000
10
10
70
55
75
55
305*
100
0
295*
2000
2000
2000
10
15
110
50
0
110*
2084-018
AC CHARACTERISTICSt (Continued)
Z8003/Z8004
Number
Symbol
Parameter
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
TdA(MR)
TdC(MR)
TwMRh
Td'MR(A)
TdDW(DSW)
TdMR(DR)
TdC(MR)
TdC(ASf)
TdA(AS)
TdC(ASr)
TdAS(DR)
TdDS(AS)
TwAS
TdAS(A)
TdAz(DSR)
TdAS(DSR)
TdDSR(DR)
TdC(DSr)
TdDS(DW)
TdA(DSR)
TdC(DSR)
TwDSR
TdC(DSW)
TwDSW
TdDSI(DR)
TdC(DSf)
TwOS
TdAS(DSA)
TdC(DSA)
TdDSA(DR)
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
TdC(S)
TdS(AS)
TsR(C)
ThR(C)
TwNMI
TsNMI(C)
TsVI(C)
ThVI(C)
TsSGT(C)
ThSGT(C) .
TsMI(C) \
ThMI(C)
TdC(MO)
TsSTP(C)
ThSTP(C)
TsW(C)
ThW(C)
TsBRQ(C)
ThBRQ(C)
TdC(BAKr)
TdC(BAKf)
TwA
TdDS(S)
TsABT(C)
ThABT(C)
Address Valid to MREQ 1 Delay
Clock 1 to MREQ 1 Delay
MREQ Width (High)
MREQ 1 to Address Not Active
Write Data Valid to OS 1 (Write) Delay
MREQ 1 to Read Data Required Valid
Clock 1 MREQ t Delay
Clock t to AS 1 Delay
Address Valid to AS t Delay
Clock 1 to AS t Delay
AS t to Read Data Required Valid
OS t to AS 1 Delay
AS Width (Low)
AS t to Address Not Active Delay
AddresUJoat to OS (Read) 1 Delay
AS t to OS (Read) 1 Delay
OS (Read)JJ.o Read Data Required Valid
Clock 1 to OS t Delay
OS t to Write Data Not Valid
Address Valid to OS (Read) 1 Delay
Clock t to OS (Read) 1 Delay
OS (Read) Width (Low)
Clock 1 to OS (Write) 1 Delay
OS (Write) Width (Low)
OS (I/O) 1 !Q.Bead Data Required Valid
Clock 1 to OS (I/O) 1 Delay
OS (I/O) Width (Low)
AS t to OS j6cknowledge) 1 Delay
Clock t to OS (Acknowledge) 1 Delay
OS (Acknowledge) 1 to Read Data
Required Delay
Clock t to Statu.§...Valid Delay
Status Valid to AS t Delay
RESET to Clock t Setup Time
RESET to Clock t Hold Time
NMI Width (Low)
N.Ml...!Q.. Clock t Setup Time
VI, NVI to Clock t Setup Time
VI, NVI to Clock t Hold Time
SAT to Clock t Setup Time
SAT to Clock t Hold Time
MI to Clock t Setup Time
MI to Clock t Hold Time
Clock t to MO Delay
STOP to Clock 1 Setup Time
STOP to Clock 1 Hold Time
WAIT to Clock 1 Setup Time
WAIT to Clock 1 Hold Time
BUSREQ to Clock t Setup Time
BUSREQ to Clock t Hold Time
Clock t to BUSACK t Delay
Clock t to BUSACK 1 Delay
Address Valid Width
OS t to STATUS Not Valid
ABORT l'to Clock t Setup Time
ABORT 1 to Clock 1 Hold Time
(4 MHz)
Max
Min
Z8003A1Z8004A Z8003 B/Z8004 B
(10 MHz)
(6 MHz)
Min
Max
Min
Max
35*
55
80
210*
70*
55*
375*
20*
140*
15*
30*
20*
0
30*
70*
220*
35*
55*
45*
0
55*
130*
70
80
95
185*
330*
90
120
110
65
60
85
10*
50
0
50
50
40
10
40
0
80
0
30*
70
0
70
70
50
20
55
0
110
0
120
70
85
50
0
20
5
60
5
80
0
30
10
80
10
140
0
50
10
90
10
60
60
75
75
100
100
95*
55*
30
0
d
165*
295*
50*
180
0
100
140
110
20
70
0
180
0
60
60
85
120
455*
~
~
160*
410*
255*
690*
410*
1065*
~
tta
75*
120*
110*
210*
W
60
110*
185*
275*
§
25*
65*
85
120
00
45
65
45*
110*
75*
180*
40
80
90
360*
70*
85* .
70*
0
80*
205*
45
40
60
60.
35*
55*
40
80*
20*
15*
140*
135*
35*
35*
230*
80
80
150*
80*
50
0
20'"
70
50*
30*
25
0
*Clock·cycle·time·dependent characteristics. See table on
following page.
tTimings are preliminary and subject to change. Units in
nanoseconds(ns).
195
~
COMPOSITE AC TIMING DIAGRAM
Vi,
w
~
-Y
NVI
~
~
--®--
~
~
~
~~
~
-Y
SAT
~
MO
..
~
~
K=
5~
Y-
STOP
~~.
.(jD- ~
./-~
WAIT
C
;@-- ~
~
Xr-
~
r@J:_ _
~~~
r~
),
C(
_r-w-
iiiORT
~
)
~
F
I1\.
!.-
----
X""
/
~~
DATA IN
® --~
DATA OUT
1=~
~
~
-.@
MEMORY READ
~
f®
.~~
1-i-f--I - ..
®
liS'
"
H' -~ ~
36
NY--
r-w
V
21
(
-@
~~
-
~
rw .. -®J
~
,)t!
i'
-®-i:= ~
INPUT/OUTP~T
INTERRUPT - . /
ACKNOWLEDGE
.
REA~/~~~i~:
NORMAUSYSTEM,
BYTE/WORD
196
"
i+
~
I:X~.
f--®--1
----@---rr~
-®-I
JJ
K:
/
_---
1:" ___
-
---
.k I - ~~ -®-l
--®.cc
~
«
~
l"'"
i'~
38'
MEMORY WRITE ~
~
r-® t}- ~~ ...
/
~
11
I---
,I> ~1
I®- I- -:; ~1)
2Il
~
~/ -.@ ~-
~--
~
~
11
"ADO-AD15
\
~
~---
v--::t't>--.'---
'"
CLOCK·CYCLE·TIME·DEPENDENT CHARACTERISTICS
Numbor
Symbol
TdA(DR)
TdDS(A)
TdDW(DS)
TdA(MR)
TwMRh
TdMR(A)
TdDW(DSW)
TdMR(DR)
TdA(AS)
TdAS(DR)
TdDS(AS)
TwAS
TdAS(A)
TdAS(DSR)
TdDSR(DR)
TdDS(DW)
TdA(DSR)
TwDSR
TwDSW·
TdDSI(DR)
TwDS
TdAS(DSA)
TdDSA(DR)
TdS(AS)
TwA
TdDS(S)
11
13
16
17
19
20
21
22
25
27
28
29
30
32
33
35
36
38
40
41
43
44
46
48
68
69
Z8003
Z8003A
Z8003B
Equation
Equation
Equation
2TcC + TwCh -130 ns
TwCI- 25 ns
TcC + TwCh - 60 ns
TwCh - 50 ns
TcC - 40 ns
TwCI- 35 ns
TwCh - 50 ns
2TcC -130 ns
TwCh - 50 ns
2TcC - 140 ns
TwCI- 35 ns
TwCh - 20 ns
TwCI- 35 ns
TwCI- 25 ns
2TcC + TwCh - 95 ns
TwCI- 25 ns
TcC + TwCh - 40 ns
TwCh - 35 ns
TcC - 30 ns
TwCI- 35 ns
TwCh - 35 ns
2TcC - 100 ns
TwCh - 35 ns
2TcC -110 ns
TwCI- 35 ns
TwCh -15 ns
TwCI- 25 ns
TwCI- 15 ns
TcC + TwCh -150 ns
TwCI- 30 ns
TcC -70 ns
TcC + TwCh - 80 ns
TcC- 65 ns
2TcC -170 ns
2TcC - 90 ns
4TcC + TwCI - 40 ns
2TcC + TwCh -150 ns
TwCh - 55 ns
TcC + TwCh - 105 ns
TwCI·- 25 ns
TcC - 90 ns
TwCI- 25 ns
2TcC + TwCh - 60 ns
TwCI- 20 ns
TcC + TwCh - 30 ns
TwCh- 20 ns
TcC-20 ns
TwCI- 20 ns
TwCh - 25 ns
2TcC - 60 ns
TwCh- 20 ns
2TcC - 60 ns
TwCI- 25 ns
TwCh -10 ns
TwCl- 20 ns
TwCI-10 ns
TcC + TwCh - 70 ns
TwCI- 15 ns
TcC-35 ns
TcC + TwCh - 30 ns
TcC - 25 ns
2TcC- 80 ns
2TcC- 40 ns
TcC-55 ns
TcC + TwCh - 50 ns
TcC - 55 ns
2TcC-120 ns
2TcC -75 ns
4TcC + TwCI- 40 ns
2TcC + TwCh - 105 ns
TwCh - 40 ns
TcC -70 ns
TwCI- 15 ns
N
00
8W
•
It'
-S
:I
•
CI
4TcC + TwCI - 30 ns
2TcC + TwCh - 75 ns
TwCh - 30 ns
TcC - 50 ns
TwCI- 10 ns
ORDERING INFORMATION
Product
Number
Packagel
Temp
Speed
Z8003
Z8003A
Z8003B
CS
CS
CS
4.0 MHz
6.0 MHz
10.0 MHz
NOTES: e
00-2084-02
Description
Z-VMPU (48-pin)
(same as above)
(same as above) .
Product
Number
Z8004
Z8004A
Z8004B
Packagel
Temp
CS
CS
CS
Speed
Description
4.0 MHz
6.0 MHz
10.0 MHz
Z-VMPU (40-pin)
(same as above)
(same as above)
= Ceramic; S = o·e to 70·e
197
18010
!8000™ ~·MWA'f1i Al'iIemm(tl)!,.
Management Unnt
Product
Specifica lion
Zilog·
September 1983
Features
II
Dynamic segment relocation makes software
addresses independent of physical memory
addresses.
t.'l 64 variable-sized segments from 256 to
65,536 bytes can be mapped into a total
physical address space of 16M bytes; all 64
segments are randomly accessible.
a Sophisticated memory-management features
General
Description
include access validation that protects
memory areas from unauthorized or
unintentional access, and a write-warning
indicator that predicts stack overflow.
II For use with both 28001 and 28003 CPU.
13 Multiple MMUs can support several transla-
The 28010 Memory Management Unit (MMU)
manages the large 8M byte addressing spaces
of the 28001 CPU. The MMU provides dynamic
segment relocation as well as numerous
memory protection features.
DynamiC segment relocation makes user software addresses independent of .the physical
memory addresses, thereby freeing the user
from specifying where information is actually
located in the physical memory. It also provides a flexible, efficient method for supporting multi-programming systems. The MMU
uses a translation table to transform the 23-bit
logical address output from the 28001 CPU
into a 24-bit address for the physical memory.
(Only logical memory addresses go to an MMU
for translation; 110 addresses and data, in
general, must by pass this component.)
tion tables for each 28001/3 address space.
Ii!
MMU architecture supports multi-programming systems and virtual memory implementations.
A23
A22
CS
A21
DMASYNC
A20
SEGT.
AI9
AI8
A17
AlB
PHYSICAL
ADDRESS
AI5
SEGMENT
NUMBER
I
_
SNB
Au
SN5
A13
SN.
SN3
AI2
ZOOiD
MMU
SN2
All
Alo
-SNI
A9
SNo
Aa
SEGMENT
TRAP
DMA/SEGMENT
SUP
DMASYNC
SUPPRESS
RiW
N /_
S _)
ST3 _
ST2 _
STI _
CHIP SELECT _
CS
STo _
STATUS
N/S
Riw
AS
sUP
os
RESET
STo
A23
STI
A22
ST2
A21
ST3
A20
ADa
AI9
AD9
Vee
ADlo
Ala
ADII
A17
CLK
AI6
GND
AI5
ADI2
AI.
AD13
A13
ADI.
AI2
A11
ADI5
SNo
Alo
SNI
Ag
SN2
Aa
SN3
RESERVED
SN.
SN6
SN5
+5V GND CLK RESET
Figure 1. Pin Functions
2046-051, 033
Figure 2. Pin Assignments
199
General
Description
(Continued)
Memory segments are variable in size from
256 bytes to 64K bytes, in increments of 256
bytes. Pairs of MMUs support the 128 segment
numbers available for the various Z8001 CPU
address spaces. Within an address space, any
number of MMUs can be used to accommodate
multiple translation tables for System and Normal operating modes, or to support more
sophisticated memory-management systems.
MMU memory-protection features safeguard
memory areas from unauthorized or unintended access by associating special access
restrictions with each segment. A segment is
assigned a number of attributes when its
descriptor is entered into the MMU. When a
memory reference is made, these attributes are
checked against the status information supplied by the Z8001/3 CPU. If a mismatch oc-
STo-ST 3
RiW.
NJ~
curs, a trap is generated and the CPU is interrupted. The CPU can then check the status
registers of the MMU to determine the cause.
Segments are protected by modes of permitted use, such as read only, system only,
execute only and CPU-access only. Other segment management features include a writewarning zone useful for stack operations and
status flags that rec~rd read or write accesses
to each segment.
The MMU is controlled via 22 Special 1/0
instructions from the Z8000 CPU in System
mode. With these instructions, system software
can assign program segments to arbitrary
memory locations, restrict the use of segments
and monitor whether segments have been read
or written.
SEGMENT NUMBER
OFFSET/DATA
SEGMENT NUMBER
OFFSET/DATA
SNo-SNe
ADa-AD15
SNo-SNa
ADa-AD,s
SEGf
SUP
STATUS
SEGMENT SUPPRESS PHYSICAL
INFORMATION
TRAP
ADDRESS
REGUEST
STo-ST,
RiW,NJ~
!miT
SUP
STATUS
SEGMENT SUPPRESS PHYSICAL
INFORMATION
TRAP
ADDRESS
REQUEST
Figure 3. The shaded areas in these block diagrams illustrate the resources used in the two modes of MMUoperation. In
the Address Translation Mode shown on the left. addresses are translated automatically. In the Command Mode shown
on the right. specific registers are accessed using Special 1/0 commands.
200
2046-028
Segmented
Addressing
Memory
Protection
2046·029
A segmented addressing space-compared
with linear addressing-is closer to the way a
programmer uses memory because each procedure and data set can reside in its own
segment.
The 8M byte Z8001 addressing spaces are
divided into 128 relocatable segments of up to
64K bytes each. A 23-bit segmented address
uses a 7-bit segment address to point to the
segment, and a 16-bit offset to address any
byte relative to the beginning of the segment.
The two parts of the segmented address may.
be manipulated separately.
The MMU divides the physical memory into
256-byte blocks. Segments consist of physically
contiguous blocks. Certain segments may be
designated so that writes into the last block
generate a warning trap. If such a segment is
used as a stack, this warning can be used to
increase the segment size and prevent a stack
overflow· error.
The addresses manipulated by the programmer, used by instructions and output by the
Z8001 are called logical addresses. The MMU
takes the logical addresses and transforms
them into the physical addresses required for
accessing the memory (Figure 4). This address
transformation process is called relocation.
The relocation process is transparent to user
software. A translation table in the MMU
associates the 7-bit segment number with the
base address of the physical memory segment.
The 16-bit logical address offset is added to the
physical base address to obtain the actual
physical memory location. Because a base
address always has a low byte equal to zero,
only the high-order 16 bits are stored in the
MMU .and used in the addition. Thus the loworder byte of the physical memory location is
the same as the low-order byte of the logical
address offset. This low-order byte therefore
bypasses the MMU, thus reducing the number
of pins required.
Each memory segment is assigned several
attributes that are used to provide memory
access protection. A memory request from the
Z8001/3 CPU is accompanied by status information that indicates the attributes of the
memory request. The MMU compares the
memory request attributes with the segment
attributes and generates a Trap Request
whenever it detects an attribute violation. Trap
Request informs the Z8001/3 CPU and the
system control program of the violation so that
appropriate action can be taken to recover.
The MMU also generates the Suppress signal
SUP in the event of an access violation. Suppress can be used by a memory system to inhibit stores into the memory and thus protect the
contents of the memory from erroneous
changes.
. Five attributes can be associated with each
segment. When an attempted access violates
anyone of the attributes associated with a segment, a Trap Request and a Suppress signal
are generated by the MMU. These attributes
are read only, execute only, system access
only, inhibit CPU accesses and inhibit DMA
accesses.
Segments are specified by a base address
and a range of legal offsets to this base
address. On each access to a segment, the offset is checked against this range to insure that
the access falls within the allowed range. If an
access that lies outside the segment is attempted, Trap·Request and Suppress are generated.
Normally the legal range of offsets within a
segment is from 0 to 256N + 255 bytes, where
0:::;N:::;255. However, a segment may be
speCified so that legal offsets range from 256N
to 65,535 bytes, where 0:::; N:::; 255. The later
type of segment is useful for stacks since the
Z8000 stack manipulation instructions cause
stacks to grow toward lower memory locations.
Thus when a stack grows to the limit of its·
allocated segment, additional memory can be
allocated on the correct end of the segment.
As an aid in maintaining stacks, the MMU
detects when a write is performed to the lowest
allocated 256 bytes of these segments and
generates a Trap Request. No Suppress signal.
is generated so the write is allowed to proceed.
This write warning can then be used to indicate that more memory should be allocated to
the seqment.
23·DIT LOGICAL ADDRESS
8 5
o
15
8
7
~--~S~EG~.NO~. ~--O~FFS-~--~
r----------
-""1
rSEaNo:l
_ _ _ _ _ _~::;....,I ~R~ ~Rf I
I"'
o 84 I
•
I
I
•
1
85
TA8~E OF 84
SEGMENT DESCRIPTOR
REGISTERS
.2
• I
1
"
"+1
~
o....
"+841
•
I
•
1
I
c
I
i
1
I
_ _ _ _ _ _-+--+.... _83_ .2.2~
V'
24·DIT PHYSICAL ADDRESS
Figure 4. Logical-to-Physical Address Translation
201
MMU
The MMU contains three types of registers:
Register
Segment Descriptor, Control and Status. A
Organization set of 64 Segment Descriptor Registers supplies
the information needed to map logical memory
addresses to physical memory locations. The
segment number of a logical address determines which Segment Descriptor Register is
used in address translation. Each Descriptor
Register also contains the necessary information for checking that the segment location
referenced is within the bounds of the segment
and that the type of reference is permitted. It
also indicates whether the segment has been
read or written.
In addition to the Segment Descriptor
Registers, the 28010 MMU contains' three 8-bit
control registers for programming the device
and six 8-bit status registers that record information in the event of an access violation.
Segment Descriptor Registers. Each of the 64·
Descriptor Registers contains a 16-bit base
address field, an 8-bit limit field and an 8-bit
attribute field (Figure 5). The base address
field is subdivided into high- and low-order
bytes that are loaded one byte at a time when
the descriptor is initialized. The limit field contains a value N that indicates N + 1 blocks of
256 bytes have been allocated to the segment. *
The attribute field contains eight flags
(Figure 6). Five are related to protecting the
segment against certain types of access, one
indicates the special structure of the segment,
and two encode the types of accesses that have
been made to the segment. A flag is set when
its value is 1. The following brief descriptions
indicate how these flags are used.
Read-Only (RD). When this flag is set, the segment is read
only and is protected against any write access.
System-Only (SYS). When this flag is set, the segment can
be accessed only in System mode, and is protected against
any access in Normal mode.
CPU-Inhibit (CPUI): When this flag is set, the segment is
not accessible to the currently executing process, and is
protected against any memory access by the CPU. The
segment is, however, accessable under DMA.
Execute-Only (EXC). When this flag is set, the segment
can be accessed only during an instruction fetch or access
by the relative addreSSing mode cycle, and thus is protected against any access during other cycles.
DMA-Inhibit (DMAI). When this flag is set, the segment
can be accessed only by the CPU, and thus is protected
against any access under DMA.
Direction and Warning (DIRW). When this flag is set, the
segment memory locations are considered to be organized
in descending order and each write to the segment is
checked for access to the last 256·byte block. Such an
access generates a trap to warn of potential segment
overflow, but no Suppress signal is generated.
Changed (CHG); When this flag is set, the segment has
been changed (written). This bit is set automatically during
any write access to this segment if the write access does not
cause any violation.
Referenced (REF). When this flag is set, the segment has
been referenced (either read or written). This bit is set
automatically during any access to the segment if the
access does not cause a violation.
BASE ADDRESS LIMIT ATIRIBUTE
FIELD
FIELD
FIELD
~
15
87
07
07
SDRO BAHO I BALO
LO
AO
SDR1
L1
A1
SDR2
L2
A2
:~~~ I:~~~
I
I
I
I
I
I
I
I
SDR63 BAH63 I BAL63
L63
A63
Figure 5. Segment Descriptor Registers
7
0
I
REF I CHG IDIRWIDMAII EXC I CPUII SYS I RD
I
Figure 6. Attribute Field in Segment Descriptor Register
Control Registers~ The three user-accessible
8-bit control registers in the MMU direct the
functioning of the MMU (Figure 7). The Mode
Register provides a sophisticated method for
selectively enabling MMUs in multiple-MMU
configurations. The ?egment Address Register
(SAR) selects a particular Segment Descriptor
Register to be accessed during a control
operation. The Descriptor Selection Counter
Register points to a byte within the Segment
Descriptor Register to be accessed during a
control operation.
7
6
5
4
32
10
7
I
65
0
0
MODE
0
ISEG~ENTIDESC~IPTOIR NU~BER I !~~~~~i
21
I
0
I
DESCRIPTOR
_°--LI_O--'-I_O--'-I_°--L_D....I~_C---I ~~~~Ci~~N
......-L.._.l..1
Figure 7. Control Registers
The Mode Register contains a 3-bit identification field (ID) that distinguishes among
eight enabled MMUs in a multiple-MMU configuration. This field is used during the segment trap acknowledge sequence (refer to the
section on Segment Trap and Acknowledge).
In addition, the Mode Register contains five
flags.
Multiple Segment Table (MST). This flag indicates whether
multiple segment tables are present in the hardware configuration. When this flag is set, more than one table is
present and the N/S line must be used to determine
whether the MMU contains the appropriate table.
Normal Mode Select (NMS). This flag indicates whether
the MMU is to translate addresses when the N/S line is
High or Low. If the MST flag is set, the N/S line must
match the NMS flag for the MMU to translate segment
addresses, otherwise the MMU Address lines remain
3-stated.
°In the stack mode, segment size is 64K-256N.
202
2046-030, 031
MMU
Register
Organization
(Continued)
Upper Range Select (URS). This flag is used to indicate
whether the MMU contains the lower-numbered segment
descriptors or the higher-numbered segment descriptors.
The most significant bit of the segment number must match
the URS flag for the MMU to translate segment addresses,
otherwise the MMU Address lines remain 3-stated.
Translate (TRNS). This flag indicates whether the MMU is
to translate logiCal program addresses to physical memory
locations or is to pass the logical addresses unchanged to
the memory and without protection checking. In the nontranslation mode, the most significant byte of the output is
the 7-bit segment number and the most significant bit is O.
When this flag is set, the MMU performs address translation and attribute checking.
Master Enable (MSEN). This flag enables or disables the
MMU from performing its address translation and memory
protection functions. When this flag is set, the MMU performs these tasks; when the flag is clear the Address lines
of the MMU remain 3-stated.
The Segment Address Register (SAR) points
to one of the 64 segment descriptors. Control
commands to the MMU that access segment
descriptors implicitly use this pointer to select
one of the descriptors. This register has an
auto-incrementing capability so that multiple
descriptors can be accessed in a block
read/write fashion.
The Descriptor Selection Counter Register
holds a 2-bit counter that indicates which byte
in the descriptor is being accessed during the
reading or writing operation. A value of zero
in this counter indicates the high-order byte of
the base address field is to be accessed, one
indicates the low-order byte of the base
address, two indicates the limit field and three
indicates the attribute field.
Status Registers. Six 8-bit registers contain
information useful in recovering from memory
access violations (Figure 8). The Violation
Type Register describes the conditions that
generated the trap. The Violation Segment
Number and Violation Offset Registers record
the most-significant 15 bits of the logical
address that causes a trap. The Instruction
Segrp.ent Number and Offset Registers record
the most-significant 15 bits of the logical
address of the last instruction fetched before
the first accessing violation. These two
registers can be used in conjunction with
external circuitry that records the low-order
offset byte. At the time of the addressing'violation, the Bus Cycle Status Register records the
bus cycle status (status code, read/write mode
and normal/system mode).
The MMU generates a Trap Request for two
general reasons: either it detects an access
2046-032
violation, such as an attempt to write into a
read-only segment, or it detects a warning
condition, which is a write into the lowest 256
bytes of a segment with the DIRW flag set.
When a Violation or warning condition is
detected, the MMU generates a Trap Request
and automatically sets the appropriate flags.
The eight flags in the Violation Type Register
describe the cause of a trap.
Read-Only Violation (RDV). Set when the CPU attempts to
access a read-only segment and the R/W line is Low.
System Violation (SYSV). Set when the CPU accesses a
system-only segment and the N/S line is High.
CPU-Inhibit Violation (CPUIV). Set when the CPU
attempts to access a segment with the CPU-inhibit flag set.
Execute-Only Violation (EXCV). Set when the CPU
attempts to access an execute-only segment in other than
an instruction fetch or load relative instructions cycle.
Segment Length Violation (SLV). Set when an offset falls
outside of the legal range of a segment.
Primary Write Warning (PWW). Set when an access is
made to the lowest 256 bytes of a segment with the DIRW
flag set.
Secondary Write Warning (SWW). Set when the CPU
pushes data into the last 256 bytes of the system stack and
EXCV, CPUIV, SLY, SYSV, RDV or PWW is set. Once this
flag is set, 'subsequent write warnings for accessing the
system stack do not generate a Segment Trap request.
Fatal Condition (FATL). Set when any other flag in the
Violation Type Register is set and either a violation is
detected or a write warning condition occurs in Normal
mode. This flag is not set during a stack push in System
mode that results in a warning condition. This flag
indicates a memory access error has occurred in the trap
processing routine. Once set, no Trap Request signals are
generated on subsequent violations. However, Suppress
signals are generated on this and subsequent CPU violations until the FA TL flag has been reset.
7
0
IFATLISWWlpwwlExcvfpUlvl SLV ISYSVI ROV
7
I
0
I
SEGMENT NUMBER
I
I
I ~~~ATION
0
I VIOLATION
SEGMENT
NUMBER
0
UPPER OFFSET
I
I
I VIOLATION
OFFSET
I
0
7
INJ~lruwl
0
CPU STATUS
I
I
7
0
I
BUS
CYCLE
STATUS
INSTRUCTION
SEGMENT
NUMBER
SEGMENT NUMBER
I
I
0
UPPER OFFSET
I
I
I
INSTRUCTION
OFFSET
Figure 8. Status Registors
203
Segment
The Z8010 MMU generates a'Segment Trap
when it detects an access violation or a
Acknow,ledge write warning cOndition. In the case of an
access violation, the MMU also activates Suppress, whk:h can be used to inhibit memory
writes and to flag special data to be returned
'on a read access. Segment Trap remains Low
until a Trap Acknowledge signal is received. If
a CPU-generated violation occurs, Suppress is
asserted for that cycle and all subsequent CPU
instruction execution cycles until the end of
the instruction. Intervening DMA cycles are
not suppressed, however, unless they generate
a violation. Violations detected during DMA
cycles cause Suppress to be asserted during
that cycle only-no Segment Trap Requests are
ever generated during DMA cycles.
Segment traps to the Z8001l3 CPU are handled Similarly to other types of interrupts. To
service a segment trap, the CPU issues a segment trap acknowledge cycle. The acknowledge cycle is always preceded by an instruction fetch cycle that is ignored (the MMU has
been designed so that this dummy cycle is
ignored). During the a'cknowledge cycle all
enabled MMU s use the AddresslData lines to
indicate their status. An MMU that has
generated a Segment Trap Request outputs a 1
on the AID line associated with the number in
its ID field; an MMU that has not generated a
segment trap request outputs a 0 on its
associated 'AID line. AID lines for which no
MMU is associated remain 3"stated. During a
segment trap acknowledge cycle, an MMU
uses AID line 8 + i if its ID field is i.
Following the acknowledge cycle the CPU
automatically pushes the Program Status onto
the system stack and loads another Program
Status from the Program Status Area. The Segment Trap line is reset during the segment trap
acknowledge cycle. Suppress is not generated
during the stack push. If the store creates a
write warning condition; a Segment Trap
Request is generated and is serviced at the
end of the Program Status swap. The SWW
flag is also set. Servicing this second Segment
Trap Request also creates a write warning condition, but because the SWW flag is set, no
Segment Trap Request is generated. If a violation rather than a write warning occurs during
the Program Status swap, the FATL flag is set
rather than the SWW flag. Subsequent violations cause Suppress to be asserted but not
Segment Trap Request. Without the SWW and
FATL flags, trap processing routines that
generate memory violations would repeatedly
be interrupted and called to process the trap
they created.
The CPU routine to process a trap request
should first check the FATL flag to determ\ne
if a fatal system error has occurred. If not, the
SWW flag should be checked to determine if
more memory is required for the system stack.
Finally, the trap itself should be processed and
the Violation Type Register reset.
Virtual
Memory
Several features of the MMU can be used in
conjunction with external circuitry to support
virtual memory for the Z8001l3. Segment Trap
Request can be used to signal the CPU in the
event that a segment is not in primary memory.
The CPU-Inhibit Flag can be used to indicate
'whether a segment is in the memory or in
secondary storage. The Changed and Altered
Flags in the attribute field for each segment
can aid in implementing efficient segment
management policies. The Status Registers can
be used in recovering from virtual memory
access faults.
Multiple
MMUs
MMU architecture directly supports two
methods for multiple MMU configurations. The
first approach extends single-MMU capability ,
for handling 64 segments to a dual-MMU configuration that manages the 128 different
segments the Z8001l3 can address. This
scheme uses the URS flag in the Mode Register
in connection with the high-order bit of the
segment number (SN6).
The 'second approach uses several MMUs to
implement multiple translation tables. Multiple
tables can be used to reduce the time required
to switch tasks by assigning separate tables to
each task. Multiple translation tables for multi-
task environments can use the Master Enable
Flag to enable the appropriate MMUs through
software. Multiple translation tables may also
be used to extend the physical memory size
beyond 16 megabytes by separating system
from normal memory and!or program from
data memory. The MST and NMS flags in the
Mode Register can be used in conjunction with
the Nis line to select the MMU that contains
the appropriate table. Special external circuitry that monitors the CPU Status lines can
manipulate the MMU Nis line to perform this
selection.
Trap and
204
DMA
Operation
MMU
Commands
Direct memory access operations may occur
between Z800 1 instruction cycles and can be
handled through the MMU. The MMU permits
DMA in either the System or Normal mode of
operation. For each memory access, the segment attributes are checked and if a violation
is detected, Suppress is activated. Unlike a
CPU violation that automatically causes Suppress signals to be generated on subsequent
memory accesses until the next instruction,
DMA violations generate a Suppress only on a
per memory access basis.·
The DMA device should note the Suppress
signal and record sufficient information to
enable the system to recover from the access
violation. No Segment Trap Request is ever
generated during DMA, hence warning
conditions are not signaled. Trap Requests are
not issued because the CPU cannot
acknowledge such a request.
The various registers in the MMU can be
read and written using Z800 1 CPU special 1/0
commands. These commands have machine
cycles that cause the Status lines to indicate an
SIO operation is in progress. During these
machine cycles the MMU enters command
mode. In this mode, the rising edge of the
Address Strobe indicates a command is pres"
ent on the ADa-ADIs. If Chip Select is
asserted and if this command indicates that
data is to be written into one of the MMU
registers, the data is read from ADa-ADIs
while Data Strobe is Low. If the command indicates that data is'to be read from one of the
MMU registers, the data is placed on
ADa-ADIs while Data Strobe is Low.
There are ten commands that read or write
various fields in the Segment Descriptor
Register. The status of the Read/Write line
indicates whether the command is a read or a
write.
The auto-incrementing ·feature of the Segment Address Register (SAR) can be used to
block load segment descriptors using the
repeat forms of the Special I/O instructions.
The SAR is autoincremented at the end of the
field. In accessing the base field, first the
high-order byte is selected and then the loworder byte. The command accessing the entire
Descriptor Register references the fields in the
order of base address, limit and attribute.
At the start of a DMA cycle, DMASYNC
must go Low for at least two cldck cycles,
indicating to the MMU the beginning of a
DMA ,cycle. A Low DMASYNC inhibits the
MMU from using an indeterminate segment
number on lines SNo-SN6. When the DMA
logical memory address is valid, the
DMASYNC line must be High before a rising
edge of Clock and the MMU then performs its
address translation and access protection fu'nctions. Upon the release of the bus at the termination of the DMA cycle the DMASYNC line
must again be High. After two clock cycles ~f
DMASYNC High, the MMU assumes that the
CPU has control of the bus and that subsequent memory references are CPU accesses.
The first instruction fetch occurs at least two
cycles after the CPU regains control of the
bus. During CPU cycles, DMASYNC should
always be High.
Opcode (Hex)
oa
09
OA
OB
OC
OD
OE
OF
IS
16
Instruction
Read/Write Base Field
Read/Write Limit Field
ReadlWrite Attribute Field
Read/Write Descriptor (all fields)
Read/Write Base Field; Increment SAR
ReadlWrite Limit Field; Increment SAR
ReadlWrite Attribute Field; Increment
SAR
ReadIWrite Descriptor; Increment SAR
Set All CPU-Inhibit Attribute Flags
Set All DMA-Inhibit Attribute Flags
Three commands are used to read and write
the control registers.
.
Opcode (Hex)
00
01
20
Instruction
ReadIW rite Mode Register
Read/Write. Segment Address Register
Read/Write Descriptor Selector Counter
Register
The Status Registers are read-only registers,
although the Violation Type Register (VTR)
can be reset. Nine instructions access these
registers.
Opcode (Hex)
Instruction
Read Violation Type Register
02
Read Violation Segment Number Register
03
Read Violation Offset (High-byte) Register
04
Read Bus Status Register
OS
Read Instruction Segment Number
06
Register
Read Instruction Offset (High-byte)
07
Register
II
Reset Violation Type Register
13
Reset SWW Flag in VTR
14
Reset FATL Flag in VTR
205
MMU
Timing
Memory Read and Write. Memory read and
instruction fetch cycles are identical, except
for the status information on the STo-ST 3
inputs. During a memory read cycle (Figure 9)
the 7-bit segment number is input on SNo-SN6
one clock period earlier than the address offset; a High on DMASYNC during T3 indicates
that the segment offset data is valid. The most
Significant eight bits of the address offset are
placed on the ADo-AD15 inputs early in the
The 28010 translates addresses and checks
for access violations by stepping through
sequences of basic clock cycles corresponding
to the cycle structure of the 28001 CPU. The
following timing diagrams show the relative
timing relationships of MMU signals during the
basic operations of memory read/write and
MMU control commands. For exact timing
information, refer to the composite timing
diagram.
T,
CLOCK
I
-
2
3
I
I
NIS,
STo-ST3
SNo-SHe
DON'T CARE
SEGMENT NUMBER
,
/
ADa-ADu
RlW
MEMORY ADDRESS
ADDRESS VALID
~>-
J
--
(
DATA IN
>
L
/
Figure 9. Memory Read Timing
206
2046·034
MMU
Timing
(Continued)
first clock period. Valid address offset data is
indicated by the rising edge of Address
Strobe. Status and mode information become
valid early in the memory access cycle and
remain stable throughout. The most significant
16-bits of the address (physical memory location) remain valid until the end of T3. Segment
Trap Request and Suppress are asserted in T2 .
Segment Trap Request remains Low hnUl Segment Trap Acknowledge is received. Suppress
is asserted during the current machine cycle
and terminates during T3. Suppress is
repeatedly asse.rted during CPU instruction
execution cycles until the current instruction
has terminated.
~Tl _ _.I~.-T2_~T3~·1
CLOCK
I
~
1..----
I
filS,
STo-ST3
SEGMENT NUMBER
DMASYNC
DON'T CARE
./ \
~
/
I
\
Aa-A 23
"
PHYSICAL ADDRESS
I
I
ADa-AD15
OFFSET
DATA OUT
/
\
Figure 10. Memory Write Timing'
2046-198
207
MMU
Timing
(Continued)
MMU Command Cycle. During the command
cycle of the MMU (Figure 11), commands are
placed on the Address/Data lines during T1.
The Status lines indicate that a Special I/O
instruction is in progress, and the Chip Select
line enables the appropriate MMU for that
command. Data to be written to a register in
the MMU must be valid on the Address/Data
lines late in T2. Data read from the MMU is
placed on the Address/Data lines late in the
TWA cycle.
Input/Output and Refresh. Input/Output and
Refresh operations are indicated by the status
lines STo-ST3.During these operations, the
MMU refrains from any address translation or
protection checking. The address lines As-A23
remain 3-stated.
I_Tl~r-T2-r-TWA-~T3-1
CLOCK
J
I
I
I
I
I
I
I
Ir----
cs
STo-ST3
- [X
-
0011
LOW
HIS
AS
-
r\-
~
ADs-ADu
INPUT
~
ADs- AD 15
-
ex
READ COMMAND
VALID
-----
(
DATA INTO CPU
c
L
-U
-
ex
WRITE COMMAND
VALID
DATA OUT OF CPU TO MMU
os
RlW
208
-
os
RIW
OUTPUT
HIGH
-
"
/
Figure II. 1/0 Command Timing
2046-199
MMU
Timing
(Continued)
Reset. The MMU can be reset by either hard
ware or software mechanisms. A hardware
reset occurs on the falling edge of the Reset
signal; a software reset is performed by a
28000 Special I/O command. A hardware reset
clears the Mode Register, Violation Type
Register and Descriptor Selection Counter. If
the Chip Select line is Low, the Master Enable
Flag in the Mode Register is set to 1. All other
registers are undefined. After reset, the
ADs-AD15 and As-A23 lines are 3-stated. The
SUP and SEGT open-drain outputs are not
driven. If the Master Enable flag is not set during reset, the MMU does not respond to subsequent addresses on its AID lines. To enable an
MMU after a hardware reset, an MMU command must be used in conjunction with the
Chip Select line.
A software reset' occurs when the Reset
'Violation Type Register command is issued.
This command clears the Violation Type
Register and returns the MMU to its initial
state (as if no violations or warnings had
occurred). Note that the hardware and software
resets have different effects.
Segment Trap and Acknowledge. The 28010
MMU generates a segment trap whenever it
detects an access violation or a write into the
lowest block of a segment with the DIRW flag
set. In the case of an access violation, the
MMU also activates Suppress. This Suppress
signal can be used to inhibit memory writes.
The Segment Trap remains Low until a Trap
Acknowledge signal is received. If a violation
occurs, Suppress is asserted for that cycle and
all subsequent CPU cycles until the end of the
instruction; intervening DMA cycles are not
suppressed, however, unless they generate a
violation. Violations detected during DMA
cycles cause Suppress to be asserted during
that cycle only, but no Trap Request is
generated.
When the MMU issues a Segment Trap
Request it awaits a Segment Trap Acknowledge. Subsequent violations occurring before
the Trap Acknowledge is received are still
detected and handled appropriately. During
the Segment Trap Acknowledge cycle, the
MMU drives one of its Address/Data lines
High; the particular line selected is a function
of the identification field of the mode register.
After the Segment Trap has been acknowledged by the 2800113 CPU, the Violation
Status Register should be read via the Special
I/O commands in order to determine the cause
of the trap. The Trap Type Register should also
be reset so that subsequent traps will be
recorded correctly.
...- - - - - - - - - - - - - - A C K N O W L E D G E
CYCLE----------------·I~l~i~~
__------__A,--------------_
AUTOMATIC WAIT CYCLES
~----
I
~
~
~
~
~
~
~
~
~
~
CLOCK
R/W
HIGH
SEGMENT TRAP ACKNOWLEDGE
(
IDENTIFIER
)
\..--_--J
Figure 12. Segment Trap and Acknowledge Timing
2046-123
209
Pin
Description
between MMU s during different phases of an
instruction.
Aa-A23. Address Bus (outputs, active High,
3-state). These address lines are the 16 mostsignificant bits of the physical memory
location.
Reserved. Do not connect.
RESET. Reset (input, active Low). A Low on
ADa-ADls. Address/Data Bus (inputs/outputs,
this line resets the MMU.
active High, 3-state). These multiplexed
address and data lines are used both for commands and for logical addresses intended for
translation.
R/W. Read/Write (input, Low=write). R/W
indicates the 2800113 CPU or 28016 DTC is
reading from or writing to memory or the
MMU.
AS. Address Strobe (input, active Low). The
SEGT. Segment Trap Request (output, active
rising edge of AS indicates that ADo-ADlS,
STo-ST3, R/W and Nis are valid.
Low, open drain). The MMU interrupts the
2800113 CPU with a Low on this line when the
MMU detects an 'access violation or write
warning.
CLK. System Clock (input). CLK is the 5 V
single-phase time-base input used for both the
CPU and MMU.
SNo-SNs. Segment Number (inputs, active
CS. Chip Select (input, active Low). This line
High). The SNo-SNs lines are used to address
one of 64 segments in the MMU; SN6 is used to
selectively enable the MMU.
selects an MMU for a control command.
OMASYNC. DMA/Segment Number Synchronization Strobe (input, active High). A
STo-ST3. Status (inputs, active High). These
Low on this line indicates that the segment
number lines are 3-state; a High indicates that
the segment number is valid. It must always be
High during CPU cycles. If a DMA device
does not use the MMU for address translation,
the BUSACK signal from the CPU may be
used as an input to "DMASYNC.
lines specify the 2800113 CPU status.
5T3-5TO
0000
a a 01
aa 1a
a 01 1
a1aa
a1a1
01 10
OS. Data Strobe (input, active Low). This line
a1 1 1
10 a a
provides timing for the data transfer between
the MMU and the 2800113 CPU.
100 I"
10 1 a
101 1
1 100
1 101
1 1 10
1111
Nis. Normal/System Mode (input, Low =
System Mode). Nis indicates the 28001/3 CPU
or 28016 DMA is in the Normal or System
Mode. The signal can also be used to switch
Definition
Internal operation
Memory refresh
I/O reference
Special I/O reference (e.g., to an MMU)
Segment trap acknowledge
Nonmaskable interrupt acknowledge
Nonvectored interrupt acknowledge
Vectored interrupt acknowledge
Data memory request
Stack memory request
Data memory request (EPU)
Stack mem.ory request (EPU)
Instruction space access
Instruction fetch, first word
Extension processor transfer
Bus Lock, Data Memory Request (28003 only)
~I
00- 0 ,
~
Os-D,s
.A-ADo-AD,
1
1
Z8001
CPu
~
ADs-AD,s
Ao-A,
.~
A,-A23
JilMU
d
STO-ST3J;
AS~
---
RIW
, NIS
MEMORY
CONTROL
Z8010
f--
OS
~
sUP
~
AS
)
V
~
SEGT
)
r
V
~cs
SNo-SNs
STo-ST3 '
~
~
8~
r--
J...--,!!.tW
Figure
210
I
13.
The MMU in a
zaool
System
2046-052
Pin
Description
( Continued)
SUP. Suppress (output, active Low, open
drain). This signal is asserted during the cur-
rent bus cycle when any access violation
except write warning occurs.
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
,
Temperature ........ See ordering information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
C +4.75 V :::; Vcc :::; +5.25 V
c GND = 0 V
c O°C :::; TA :::; +70°C
DC
Characteristics
Symbol
+5V
2.2K
FROM OUTPUT 0 - - -__UNDER TEST
.....-1<
Parameter
Min
Max
Unit
VCH
Clock Input High Voltage
VCC-O.4
VCC+0.3
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
-0.3
0.45
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
VCC+0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
0.4
V
IOL = +2.0 rnA
IlL
Input" Leakage
±10
p.A
0.4 :::; VIN :::; +2.4 V
IOL
Output Leakage
±10
p.A
0.4 :5 VIN :5 + 2.4 V
ICC
VCC Supply Current
300
rnA
2.4
Condition
V
IOH = -250 p.A
NOTE: The on-chip back-bias voltage generator takes approximately 20 ms to pump the back-bias voltage to -2.5 V after the power has
been turned on. The performance of the 28010 2-MMU is not guaranteed during this period.
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Speed
Description
Z8010
CE
4.0 MHz
Z-MMU (48-pin)
Z8010A
CE
6.0 MHz
Z-MMU (48-pin)
Z8010
CM
4.0 MHz
Same as above
Z8010A
CM
6.0 MHz
Same as above
Z8010
CMB
4.0 MHz
Same as above
Z8010A
CMB
6.0 MHz
Same as above
Z8010
CS
4.0 MHz
Same as above
Z8010A
CS
6.0 MHz
Same as above
Z8010
PE
4.0 MHz
Same as above
Z8010A
PE
6.0 MHz
Same as above
Z8010
PS
4.0 MHz
Same as above
Z8010A
PS
6.0 MHz
Same as above
NOTES: C = Ceramic, P = Plastic; E = -40°C to +85°C, M
MIL-STD-883 Class B processing, S = O°C to + 70°C.
8085-0209
Package/
Temp
=
-55°C to + 125°C, MB
=
-55°C to + 125°C with
211
AC Characteristics .
No.
Symbol
Z8010
4 MHz
Parameter
TcC
1
2
TwCh
3
TwCI
4
TfC
5-TrC
TdDSA(RDv)
6
Min
Clock Cycle Time
250
Clock Width (High)
105
Clock Width (Low)
105
Clock Fall Time
Clock Rise Time
DS I (Acknowledge) to Read Data
Valid Delay
TdDSA(RDf)
DS I (Acknowledge) to Read Data
7
Float Delay
TdDSR(RDv)
DS I (Read) to AD Output Driven Delay
8
TdDSR(RDf)
DS I (Read) to Read Data Float Delay
9
10- TdC(WDv)-- CLK I to Write Data Valid Delay
ThC(WDn)
11
CLK I to Write Data Not Valid
30
Hold Time
12
TwAS
Address Strobe Width
60
TsOFF(AS)
13
Offset Valid to AS' I Setup Time
45
14
ThAS(OFFn)
AS I to Offset Not Valid Hold Time
60
15 - TdAS(C)--- AS I to CLK I Delay
110
TdDS(AS)
16
DS I to AS I Delay
50
TdAS(DS)
17
AS I to DS I Delay
50
TsSN(C)
18
SN Data Valid to CLK I Setup Time
100
ThC(SNn)
19
CLK I to SN Data not Valid Hold Time
a
20 - TdDMAS(C) DMASYNC Valid to CLK I Delay
120
TdSTNR(AS)
21
Status (STo-ST3 , NIS, R/W) Valid to
50
AS I Delay
TdC(DMA)
22
CLK I to DMASYNC I Delay
20
TdST(C)
23
Status (STo-ST3 ) Valid to CLK I Delay
100
TdDS(STn)
24
DS I to Status Not Valid Delay
a
25 - TdOFF(Av)-- Offset Valid to Address Output
Valid Delay
TdST(Ad)
Status Valid to Address Output
26
Driven Delay
TdDS(Af)
27
DS I to Address Output Float Delay
TdAS(Ad)
28
AS I to Addres Output Driven Delay
29
TdC(Av)
CLK I to Address Output Valid Delay·
30 - TdAS(SEGT)- AS I to SEGT I Delay
TdC(SEGT)31
CLK I to SEGT I Delay
TdAS(SUP)
AS I to SUP I Delay
32
TdDS(SUP
33
DS I to SUP I Delay
TsCS(AS)
34
Chip Select Input Valid to AS I Setup
10
Time
35 - ThAS(CSn) - - AS I to Chip Select Input ~ot Valid---60
Hold Time
TdAS(C)
AS I to CLK I Delay
36
a
TsCS(RST)
37
Chip Select Input Valid to RESET I
150
Setup Time
ThRST(CSn)
38
RESET I to Chip Select Input Not
a
Valid Hold Time
TwRST
RESET Width (Low)
2TcC
39
40 - TdC(RDv) - - CLK I to Read Da'ta Valid Delay
TdDS(C)
41
DS I to CLK I Delay
30
TdC(DS)
42
CLK I to DS I Delay
0
NOTES:
1. 50 pF Load.
2. 2.2K Pull-up.
• All 6 MHz timings are preliminary.
t Units in nanoseconds (ns).
212
Z8010
Max
Z8010
6MHz
Min
Max
IOMHz
Max
Min
165
70
70
100
40
40
20
20
100
10
15
80
10
10
60
75
60
45
80
60
80
60
45
50
100
75
125
60
20
10
50
35
40
90
30
40
40
30
20
20
'50
15
30
20
a
a
80
30
60
10
15
60
10
30
a
Notes*.t
a
175
90
60---1-
155
75
45
160
145
255
160
300
150
155
130
70
155
100
200
90
100
100
40
100
60--1,2100
1.2
1,2
55
1,2
60
10
10
40
20
a
a
100
60
a
a
2TcC
2TcC
300
460
190
20
10
a
a
Timing measurements are made at the following voltages:
High
Low
0.8 V
4.0 V
0.8 V
2.0 V
2.0 V
0.8 V
±0.5 V
b.V
Clock
Output
Input
Float
CLOCK
p-~
f..®.
~======================================
~t f-®
00-2046-02
2046-122
213
Z8015 Z8000™ PMMU
ll»Qg~a!
Mannery
Management Unit
Produ.ct
Specification
September 1983
iie:»
FEATURES
[] 'PMMU architecture supports multiprogramming
systems and virtual memory implementations.
[J
IJ
Dynamic page relocation makes software addresses
independent of physical memory addresses.
Sophisticated memory management features include
access validation that protects memory areas from
unauthorized or unintentional access, and a writewarning indicator that predicts stack overflow.
[J
[J
64 pages, each 2048 bytes in length, can be mapped
into a total physical address space of 16 megabytes;
all 64 pages are randomly accessible.
Pages larger or smaller than 2048 bytes can be easily
implemented.
[] The number of accessible pages can be increased by
using multiple PMMUs.
GENERAL DESCRIPTION
The l8015 Paged Memory Management Unit (PMMU), a
new member of lilog's l8000 Family, is designed to support a paged virtual memory system for the l8003 Virtual
Memory Processor Unit (VMPU). Although designed
primarily for the l8003, the PMMU can also be used to
support other CPUs in the Z8000 Family. The sophisticated memory management features of the PMMU include access validation for memory protection, a writewarning that gives advance warning of possible stack
overflow, and the generation of instruction aborts for accesses to pages not in main memory. Each PMMU can
manage a basic memory area of sixty-four 2048-byte,
fixed-size pages. The VMPU's 8M byte logical address
space is translated by the PMMU into a 16M byte
physical address space. Page size can be easily
changed and multiple PMMUs can be combined to support more pages.
FUNCTIONAL DESCRIPTION
The l8015 Paged Memory Management Unit (PMMU)
manages the 8M byte addressing spaces of the l8003
VMPU. The PMMU provides dynamic page relocation as
well as numerous memory protection features.
Dynamic page relocation makes user software addresses independent of the physical memory addresses,
thereby freeing the user from specifying where information is located in the physical memory. It also provides a
flexible, efficient method for supporting multiprogramming systems.
, The PMMU uses a content-addressable translation table
to transform each 23-bit logical address output from the
VMPU into a 24-bit address for the physical memory.
(Only logical memory addresses go to a PMMU for
translation; I/O addresses and data bypass this component.) The translation table consists of 64 page descriptors; each descriptor contains address translation,
status, and access information for one memory page.
Each PMMU can then manage up to 64 pages of
memory.
Multiple PMMUs can be used to support more than 64
pages within a given address space. In addition, PMMUs
can be used to accommodate separate translation
tables for System and Normal operating modes.
The PMMU is designed to support a memory page 2048
bytes in length. This basic page length can be increased
or decreased using a minimal amount of external circuitry.
The PMMU is specially designed to operate with a l8003
VMPU to implement a paged virtual memory system. If
the current PMMU instruction addresses a page not in
main memory (a page fault), the PMMU initiates an Instruction Abort operation in the VMPU. During an abort,
215
tool
en
;
:I
CI
the PMMU aborts the execution of the current instruction, then saves the information needed to restart the
aborted instruction. On completion of the abort, the
PMMU initiates a trap in the VMPU to a routine that
brings the addressed page into main memory, updates
the descriptor table of the PMMU to allow address
translation to the new page, and restarts the execution
of the interrupted instruction.
The logical address that caused the page fault is
available in three violation address registers of the
PMMU. This information can be used to fetch the required instruction or data page into main memory and/or
to create a page descriptor entry so that the executing
program can access those instructions or data. The
logical address of the instruction generating the page
fault is available in three instruction address registers of
the PMMU. This information can be used to reset the
Program Counter' to restart the instruction. The instruction to be restarted must also be examined to determine
if adjustments must be made to any VMPU registers to
ensure correct execution. Finally, the Read/Write Data
Count register can be accessed so that certain instructions, such as Load Multiple, can be restarted correctly.
As an aid in implementing efficient paging algorithms,
the PM M U provides Changed and Referenced flags for
each page descriptor register. The Changed flag indicates that a page has been altered and hence must be
copied to secondary storage before that physical
memory can be overwritten by another page. The
Referenced flag can be used to determine which pages
have not been accessed by an executing program-these are the pages that should first be removed
from memory when room must be made to bring another
page into memory.
PMMU memory protection features safeguard memory
areas from unauthorized or unintended access by associating special access restrictions with each page. A
page is assigned a number of attributes when its descriptor is initially entered into the PMMU. When a memory
reference is made, these attributes are checked against
the status information supplied by the VMPU. If a mismatch occurs, the instruction is aborted, a Trap Request
Signal is generated, and the VMPU is interrupted. The
VMPU then checks the status registers of the PMMU to
determine the cause of the abort.
Pages are protected by modes of permitted use, such as
read only, system only, and execute only. A Valid flag indicates whether or not a descriptor has been initialized.
Other page management features include a Write Warning flag useful for stack operations.
The PMMU is controlled by 20 Special I/O instructions,
which can be issued from the VMPU in System mode
only. With these instructions, system software can
assign program pages to arbitrary memory locations,
restrict the use of pages, and monitor'whether pages
have been read or written.
The PMMU has two operating modes: an Address Translation mode in which addresses are translated
automatically as they are received, and a Command
mode, during which specific registers in the PMMU are
accessed using Special I/O commands. Figure 1 shows
two simplified block diagrams that illustrate the internal
organization and data/Signal flow within the PMMU. The
resources used in the Translation and the Command
modes are shown, separately, in Figures 1a and 1b.
SEGMENTED ADDRESSING AND
ADDRESS TRANSLATION
Compared with linear addressing, a segmented addressing space is closer to the way a programmer uses
memory because each procedure and data set can
reside in its own segment.
The 23-bit addresses output by the VMPU divide an 8M
byte addressing space into 128 segments of up to 64K
bytes each. A 23-bit segmented address consists of a
7-bit segment number and a 16-bit offset used to address
any byte relative to the beginning of the segment. The
two parts of the segmented address (segment number
and offset) can be manipulated separately.
The PMMU divides physical 'memory into 2048-byte
pages. Pages are assumed to be allocated in memory on
2048-byte boundaries so that the 11 low-order bits of the
starting location of each page are always equal to zero.
216
Segments in a virtual memory system can consist of
pages that need not be in physical storage. Those segment pages in main memory need not be contiguous.
Segments can have a variable number of pages. Certain
pages can be designated so that writes into the last 128
bytes generate a warning trap without causing an instruction abort. If such a page is used as the last page of
the system stack, the warning trap can be used to initiate
the allocation of another page to the stack segment to
prevent a stack overflow error.
The addresses manipulated by the programmer, used by
instructions, and output by the VMPU are called logical
addresses. The PMMU translates logical addresses into
the phYSical addresses required for acceSSing memory,
this process is called relocation.
INTERNAL DATA BUS
OFFS(T nus
IOPF
LOW
VOFF
LOW
OAR
ADS-AD1O
ViOUUiOU
CHf.CKING
¢={f
r....--..I.
STJL-ST~
R/W N/S
Figure 1a. Address Translation Mode PMMU Operating Modes, Simplified Flow Diagram
The translation activity in the PMMU that provides address relocation is controlled by four internal control
flags and six input lines. The four flags are:
Mastor Enable (MSEN) Flag. This flag controls when the PMMU outputs physical addresses on its Address bus (A) lines. When this bit is
clear, the A lines remain 3-stated and no checking is performed.
Translate (TRNS) Flag. This flag determines whether the output on
the A lines is the logical address as input (with most significant bit at 0)
or a translated address. When translation is not performed, no checking is done.
Multiple Page Table (MPT) Flag. This flag indicates whether or not
separate PMMUs are to be used for System and Normal pages.
Normal Mode Select (NMS) Flag. When the Multiple Page Table flag
is set, this flag indicates whether the PMMU contains System or Normal page descriptors.
2081-001
The six input lines used in the control of the PMMU are:
NIS Line. This line is used by the PMMU to distinguish
System mode accesses from Normal mode accesses.
When the Multiple Page Table flag is set, the NtS line
acts as a chip-select mechanism.
Chip Enable (CE) Line. This line acts as a master
enable control line: it must be asserted for any address
translation to occur or for any address to be output by
the PMMU.
Status Lines (STo-ST3)' These four lines are used by
the PMMU to determine the type of transaction in progress.
217
INTERNAL DATA BUS
OFFSET BUS
IOFF
lOW
VOFF
lOW
ADa-AD10
VIOLATION
CHECKING
Figure 1b. Command Mode PMMU Operating Modes, Simplified Flow Diagram
Access violation checking, write warning checking, and
page fault monitoring functions occ'ur only when the
PMMU is enabled for address translation. For example,
if Chip Enable is not asserted, the PMMU does not
generate an Abort Request even if none of its descriptors
match the logical address.
The address translation process is transparent to user
software; a simplified flow diagram of this process is
shown in Figure 2. A content-addressable translation
table in the PMMU compares the 7-bit segment number
and five most-significant bits of the offset with the logical
218
address field of each descriptor. If a match occurs and
that descriptor's Valid flag is set, the physical address
field of that descriptor is accessed. The 11-bit logical address within the page is concatenated to this 13-bit
physical base address to obtain the actual physical
memory location. Because the base address of a page
always has the low-order 11 bits equal to zero,. only the
high-order 13 bits are stored in the PMMU and used in
the translation. The PMMU outputs the 16 mostsignificant bits of the translated address.
2081-002
11 10
15
8 7
LOGICAL
r------t----t-------1 ADDRESS
L
__
PHYSICAL
ADDRESS
23
~,----------
__
11 10
8 7
v~------------J
OUTPUT BY PMMU
Figure 2. Logical·to·Physical Address Translation
MEMORY PROTECTION
Each memory page is assigned several attributes that
are used to provide memory access protection. A
memory request from the VMPU is accompanied by
status information that indicates the attributes of the
memory request. The PMMU compares the memory request attributes with the page attributes and generates
Instruction Abort Request, Suppress, and Trap Request
Signals whenever it detects an attribute violation.
An Abort Request is used to generate the Abort and Wait
inputs to the VMPU that cause the current instruction to
be aborted. The Suppress input is used by the VMPU to
inhibit stores into the memory and thus protect the contents of the memory from erroneous changes. A Trap Request informs the VMPU and the system control program
of the violation so that appropriate action can be taken
for recovery.
Three attributes: read only, execute only, and system access only, can be associated with each page. When an
attempted access violates anyone of the page attributes, Abort Request, Trap Request, and Suppress
Signals are generated by the PMMU.
Each descriptor register has a Valid flag in the attribute
field. When set to 1, this flag indicates that the descriptor
2081-003
contains valid translation information and its logical ad·
dress field is to be used in the associative match pro·
cess. If Chip Enable is asserted and no match is found,
the PMMU, if enabled, generates Abort Request, Trap
Request, and Suppress signals. The PMMU is enabled
under either of the following conditions: the MSEN and
TRNS flags are both 1 and the MPT flag is 0; or the MSEN
and TRNS flags are both 1, the MPT flag is 1, and both in·
put N/S and the NMS flag have the same value.
Normally, the legal range of offsets within a segment
goes from 0 to 65,535 bytes. A stack segment, however,
has legal word offsets ranging downward from 65,534 to
o bytes; the stack manipulation instructions cause
stacks to grow toward lower memory locations. When a
stack grows to the limit of its allocated segment, addi·
tional memory can be added to the segment. As an aid in
maintaining stacks, the PMMU detects when a write is .
performed to the lowest-allocated 128 bytes of a stack
page and generates a Trap Request if the DIRW attribute
flag is set in the page descriptor. Since neither a Suppress nor Abort Request signal is generated, the write is
allowed to proceed. This write warning can then be used
to indicate that more memory (that is, another page)
needs to be allocated to the segment.
219
PMMU REGISTER ORGANIZAtiON
The PMMU contains a set of 64 page descriptor
registers that supply the information needed to' map
logical memory addresses to physical memory locations. The PMMU also contains three' 8-bit control
registers for programming the PMMU, and nine 8-bit
status registers to record information in the event of an
access violation.
Page Descriptor Registers
The segment number and five most-significant bits of a
logical address determine, by associative lookup, which
page descriptor register is used in address translation.
Each register also contains the necessary information to
enable checking to ensure that the type of reference
made is permitted. An indication that the segment has
been previously read or written is also contained in the
register.
Each of the 64 page descriptor registers contains a
12-bit logical address field, a 13-bit physical address
field, and a 7-bit attribute field (Figure 3).
Figure 3. Page Descriptor Register Format
. The logical address field is used during the associative
search phase of address translation; a match of this field
with the most-significant bits of the logical address indicates that the descriptor is to be used during physical
address generation. The physical address field supplies
the most-significant bits of the generated physical address.
The attribute field contains seven flags (Figure 4). Three
flags protect the page against certain types of access,
one indicates the special structure of the page, and two
6
IVALIDI
REF
I CHG
I I
DIRW
0
EXC
I SYS
I RD 1
Figure 4. Attribute Field of Page Descriptor Register
220
encode the types of accesses that have been made to
the page. The seventh flag is used to indicate whether or
not the information in the descriptor is valid. A flag is set
when its value is 1. During a write to only the attribute
field, bit 7 of the byte is ignored. When an attribute field
is read, bit 7 is undefined. When an entire descriptor is
accessed, bit 7 will be part of the physical address field.
The following descriptions explain how these flags are
used.
Valid (VALID). When this flag is set, the descriptor contains valid
page information for the currently executing process. When this bit is
clear, the logical address generated by the VMPU is not compared
against the contents of the logical address field, so the descriptor is
not used for address translation. Only descriptors that have this flag
set are used during the associative search.
Read·Only (RD). When this flag is set, the page is read·only and is
protected against any write access.
System·Only (SYS). When this flag is set, the page can be accessed
only in System mode, and is protected against any access in Normal
mode.
Execute·Only (EX C). When this flag is set, the page can be accessed
only during an Instruction Fetch cycle and is thus protected against ac·
cess during other cycles.
Direction and Warning (DIRW). When this flag is set, the page's
memory locations are considered to be organized in descending order
and each write to the page is checked for access to the lowest 128
bytes. Such an access generates a Trap Request signal to warn of
potential stack overflow, but neither an Abort Request nor a Suppress
signal is generated .
Changed (CHG). When this flag is set, the page has been changed
(written into). This bit is set automatically during any write access to
this page if the write access does not cause a violation.
Referenced (REF). When this flag is set, the page has been referenced (either read or written). This bit is set automatically during any access to the page if the access does not caus,e a violation.
The byte format that is requIred to write into or read from
an attribute field is shown in Figure 5.
IVALIDI
REF
I I I I I I
CHG
DIRW
EXC
SYS
RD
Figure 5. Format of Byte for Reading or Writing
a Descriptor's Attribute
2081'()()4, 005, 006
Control Registers
The three user-accessible, 8-bit control registers in the
PMMU direct the functioning of the PMMU (Figure 6).
The Mode register provides a sophisticated method for
selectively enabling PMMUs in multiple-PMMU configurations. The Descriptor Address (DAR) register
selects the particular page descriptor register to be accessed during a control operation. The Descriptor Selection Count (OSC) register pOints to the byte in the Page
Descriptor register to be accessed during a control
operation.
highest-order byte of the descriptor is to be accessed
(most-significant byte of the logical address field), a one
indicates the next byte of the descriptor, a two indicates
the third byte, and a three indicates the least-significant
byte (containing the attribute field).
Status Registers
The following nine 8-bit status registers contain information useful in recovering from memory access violations
(Figure 7):
TRAP
TYPE
32
I MPT I NMS I
MODE
10
65
SEGMENT NUMBER
DESCRIPTOR
ADDRESS
DESCRIPTOR NUMBER
!
!
,
21
o
I
DSC
~~--~--~--~--~--~.--~I--~
UPPER OFFSET BYTE
DESCRIPTOR
SELECTION
COUNT
LOWER OFFSET BYTE
Figure 6. Control Registers
SEGMENT NUMBER
Mode Register
The Mode register contains a 3-bit identification (10) field
that can distinguish up to eight enabled PMMUs in a
multiple-PMMU configuration. This field is used during
the Trap Request acknowledge sequence. In addition,
the Mode register contains the following four flags:
Multiple Page Table (MPT). This flag indicates whether more than
one page table is present in the hardware configuration. When this flag
is set, more than one table is present and the N/S line is used to determine whether the PMMU contains the appropriate table.
Normal Mode Select (NMS). This flag indicates whether the PMMU is
to translate addresses when the N/S line is High or Low. If the MPT flag
is set, the N/S line must match the NMS flag for the PMMU to translate
addresses; otherwise, the PMMU address lines remain 3-stated.
Translate (TRNS). This flag indicates whether the PMMU is to
translate logical program addresses to physical memory locations or is
to pass the logical addresses unchanged to the memory without protection checking. In the Non-Translation mode, the most-significant
output byte is the 7-bit segment number and the most-significant bit is
O. When TRNS is set, the PMMU performs address translation and attribute checking.
VIOLATION
ADDRESS
UPPER OFFSET BYTE
INSTRUCTION
ADDRESS
LOWER OFFSET BYTE
7
6
I
0
I
0
0
3
I I I
N/S
R/W
0
I
, cPU STATUS
,
,
COUNT
BUS CYCLE
STATUS
READ/WRITE
DATA COUNT
Figure 7. Status Registers
Trap Type Register. This register describes the conditions that generate a Trap Request signal.
Violation Segment Number and Violation Offset
Registers. These three registers record the logical address that caused a Trap Request.
Master Enable (MSEN). This flag enables or disables the PMMU from
performing its address translation and memory protection functions.
When this flag is set, the PMMU performs these tasks; when the flag is
clear the address lines of the PMMU remain 3-stated.
Instruction Address Registers. These three registers
Descriptor Address Register (DAR)
Bus Cycle Status Register. This register records the
bus cycle status (status code, Read/Write operation and
Normal/System mode).
This register pOints to one of the 64 page descriptor
registers. Control commands to the PMM'U that access
page descriptors implicitly use this pointer to select one
of the page descriptor registers. The DAR has autoincrementing capability so that multiple descriptors can
be accessed in a block read/write fashion.
Descriptor Selection Count (DSC) Register
This register holds a 2-bit counter that indicates which
byte in the descriptor is being accessed during Read or
Write operations. A zero·in this counter indicates that the
2081-007, 008
record the logical address of the last instruction fetched
before the first warning, access violation, or page fault.
Read/Write Data Count Register. This register contains a 4-bit counter that counts the number of read and
write data transactions whose addresses have been
translated by the PMMU since the last instruction fetch
. cycle. This ·count is locked when an Abort Request is
generated, and indicates the number of successful data
transactions performed by the aborted instruction.
221
Violation Type Register (VTR) Flags
The VTR is used by the PMMU to determine the cause of
a Trap Request. The PMMU generates a Trap Request
when: it detects an access violation, such as an attempt
to write into a read-only page; it detects a warning condition, which is a write into the lowest 128 bytes of a page
with the DIRW flag set; or no entry matches the logical
address (a page fault). The .following seven flags are contained by the Violation Type register (VTR):
Read-Only Violation (RDV). This flag is set when the VMPU attempts
to access a read-only page and the RtW line is Low.
System Violation (S YS V). This flag is set when the VMPU accesses a
system-only page and the N/S line is High.
Execute·Only Violation (EXCV). This flag is set when the VMPU attempts to access an execute-only page other than during an instruction fetch cycle.
Page Fault (PGFT). This flag is set when no logical address field of
the valid descriptors in the PMMU matches the upper 12 bits of the
logical address.
Primary Write Warning (PWW). This flag is set when an access is
made to the lowest 128 bytes of a page with the DIRW flag set.
Secondary Write Warning (SWW). This flag is set when the VMPU
writes data into the last 128 bytes of the system stack and EXCV,
SYSV, PGFT, RDV, or PWW is set. With SWW set, subsequent write
warnings for accessing the system stack do not generate a Trap Request.
Fatal Condition (FATL). This flag is set when any other flag in the
Trap Type register is set and either a violation is detected or a write
warning condition occurs in Normal mode. FATL is not set during a
stack push in System mode that results in a warning condition. This
flag indicates that a memory access error has occurred in the trap processing routine. Once set, no Trap Request or Abort Request signals
are generated on subsequent violations. However, as long as the
PMMU is enabled, Suppress signals are generated on this and subsequent VMPU violations until the FATL flag is reset. .
ABORT, TRAP REQUEST, AND
ACKNOWLEDGE·
The PMMU generates a four-clock-cycle Abort Request
(ABORT) when it detects an access violation or a page
fault. This Signal on the ABORT (pin 33) and WAIT (pin 20)
inputs of the VMPU inserts a five-cycle abort sequence
that causes the VMPU to terminate instruction execution. A Trap Request is generated when the PMMU
detects an access violation, page fault, or write warning.
This signal on the translation trap line of the VMPU (line
14) causes the VMPU to generate a trap acknowledge
after the instruction abortion (for an access violation or
page fault) or after the execution of the instruction (for a
write warning). In the case of an access violation or page
fault, the PMMU also activates Suppress (SUP), which
can be used by the memory to inhibit memory writes.
Trap Request remains Low until a trap acknowledge is
received (status = 0100). If a VMPU-generated violation
occurs, Suppress is asserted for that memory reference.
(If a Z8001 or Z8002 CPU generates the violation, any
subsequent CPU memory reference also causes Suppress.to be asserted until the end of the instruction.) Intervening DMA accesses are not suppressed, however,
unless they generate a violation. Violations detected during DMA accesses cause Suppress to be asserted for
that access only; no Trap or Abort Requests are
generated'during DMA accesses.
Trap Requests to the VMPU are handled similarly to interrupts. To service a PMMU trap, the VMPU issues a
trap acknowledge. The acknowledge is usually preceded
by a dummy instruction fetch that is not used by the
VMPU (the PMMU has been designed to ignore this dummy fetch). During the identifier fetch of the acknowledge
cycle, all enabled PMMUs use the Address/Data (AD)
222
lines to indicate their status. A PMMU that has
generated a Trap Request outputs a 1 on the AD line
associated with the number in its 10 field; a PMMU that
has not generated a trap request outputs a 0 on its
associated AD line. AD lines with no associated PMMU
remain 3-stated. During.a trap acknowledge, a PMMU
uses AD line 8 + i if its ID field is i.
Following the Acknowledge cycle, the VMPUautomatically pushes the program status onto the system stack
and loads another program status from the trap vector at
location 20H in the program status area. The PMMU's
trap line is reset during the trap acknowledge. Suppress
is not generated during the stack push. If the push operation creates a write warning condition, a Trap Request is
generated and serviced at the end of the context swap.
The SWW flag is also set. Servicing this second Trap Request also creates a write warning condition, but
because the SWW flag is set, no Trap Request is
generated. If a violation or page fault rather than a write
warning occurs during the context swap, the FATL flag is
set rather than the SWW flag. Subsequent violations or
faults cause Suppress but not Trap Request to be
asserted. Without the SWW and FATL flags, trap processing routines that generate memory violations or
faults would repeatedly be interrupted and called to process the trap they created.
The VMPU routine to process a Trap Request should first
check the FATL flag to determine if a fatal system error
has occurred. If not, the SWW flag should be checked to
. determine· if more memory is required for the system
stack. Finally, the trap itself should be processed and the
Trap Type register reset.
MULTIPLE PMMUs
Although only one PMMU should be actively translating
addresses at a given time, PMMU architecture directly
supports various methods for multiple PMMU configurations. The following four examples illustrate different
ways that PMMUs can be used to implement memory
management systems capable of handling more than 64
pages.
Example 1. The first approach extends the capability of
one PMMU for handling 64 pages to a multiple-PMMU
configuration that manages more than 64 pages. The
Chip Enable line is used to select a particular PMMU to
translate a page address. For example, if one PMMU is
assigned only pages for logical addresses whose bit
number 11 is a 0 and another PMMU is assigned those
whose bit number 11 is a 1, then the state of output line
AD11 can be used to select the appropriate PMMU to
translate a logical address.
associated with translating addresses generated during
instruction fetches (status codes 1100 and 1101) and the
other with addresses generated during data fetches
(status codes 1000, 1001, 1010, 1011, and 1111). Chip
Enable for each PMMU is obtained from the status code
(Le., status lines STo-ST3).
Example 3. Several PMMUs can be used to implement
multiple translation tables. Multiple tables reduce the
time required to switch tasks by assigning separate
tables to each task. Multiple translation tables for multitask environments can use the Master Enable flag to
enable the appropriate PMMUs through software.
Example 4. A final method uses two translation tables
to separate system from normal memory. The MPT and
NMS flags in the Mode register can be used in conjunction with the N/S line to select the PMMU that contains
the appropriate table.
Example 2. Another way of using Chip Enable sepa~
rates program pages from data pages. One PMMU is
CHANGING PAGE SIZE
The PMMU directly supports pages of 2048 bytes in
length. However, the addition of external circuitry
enables the PMMU to support systems with larger or
smaller pages. The following examples illustrate the
technique for changing the supported page size.
Example 1. To implement 4096-byte pages, address bit
AD11 is not used in the translation process but is used
directly as the most significant bit of the address location within a selected 4096-byte page. This can be
achieved by doing the following: (1) set the AD11 input to
be equal to the logical OR of the ST3 and AD11 output
lines of the VMPU, (2) require that the least significant bit
in the logical address field of each descriptor register be
set to 1, and (3) use the logical address bit AD11 output
by the VMPU instead of the physical address A11 output
by the PMMU. The AD11 input must be 1 during address
translation but must equal the AD11 output by the CPU
during command cycles to the PMMU; ST3 is used to
distinguish the two types of transactions.
Example 2. To implement 1024-byte pages an additional address bit' must be translated. Two PMMUs are
used. The CE input is driven by AD10 for one PMMU and
its complement, AD1O, for the other.
DMA OPERATION
At the start of a DMA cycle, DMASYNC must go Low
whether or not the PMMU is used to translate DMA addresses, to indicate the beginning of a DMA cycle. When
DMASYNC has been Low for two cycles, the PMMU·
assumes that a DMA device has control of the bus. A
Low on DMASYNC inhibits the PMMU from using an indeterminate segment number on lines SNo-SNs. When
the DMA logical memory address is valid, the DMASYNC
line must be High on a rising edge of the, clock and then
be Low by the next falling clock edge. The PMMU then
performs its address translation and access protection
functions during the clock period begun in this
DMASYNC pulse. Upon the release of the bus at the termination of the DMA cycle, the DMASYNC line must go
High. After two clock cycles of DMASYNC High, the
PMMU assumes that the VMPU has control of the bus
and that subsequent memory references are VMPU accesses. The first memory reference occurs at least two
cycles after the VMPU regains control of the bus. During
VMPU cycles, DMASYNC should remain High. Refer to
the paragraph "Memory Read and Write" and Figure 8
for further information.
Direct memory access (DMA) operations can occur between instruction cycles and can be handled through the
PMMU. The PMMU permits DMA in either the System or
Normal mode of operation. For each memory access,
the page attributes are checked, and if a violation is
detected, Suppress is activated. DMA violations
generate a Suppress only on a per-memory-access
basis.
I
The DMA device should note the Suppress signal and
record sufficient information to enable the system to
recover from the access violation. Neither a Trap Request nor an Abort Request is ever generated during a
DMA operation, therefore warning conditions are not
signaled.
223
PMMU COMMANDS
The various registers in the PMMU can be read and written using VMPU Special I/O commands. The machine
cycles of these commands cause the status lines to indicate that a special input/output operation is in progress. During these machine cycles, the PMMU enters
the command mode. In this mode, the rising edge of AS
indicates that a command is present on lines ADa-AD15'
If this command indicates that data is to be written into
one of the PMMU registers, the data is read from lines
ADa-AD15 while DS is Low. If the command indicates
that data is to be read from one of the PMM!:!..!egisters,
the data is placed on lines ADa-AD15 while DS is Low.
Table 2 gives the three commands that are used to read
and write the control registers.
There are five commands that read or write various
fields in the page descriptor register. The status of the
read/write line indicates whether the command is a read
or a write.
The status registers are read-only registers, although the
Trap Type Register (ITR) can be reset. Twelve instructions, shown in Table 3, access these registers.
The autoincrementing feature of the Descriptor Address
Register (DAR) can be used to block load page descriptors using the repeat forms of the Special I/O instru~
tions. The DAR is autoincremented at the end of the
field. The command acc~ssing the entire page descriptor register references the fields in the order of logical
address, physical address, and attribute; four bytes are
written in succession.
Table 2. Control Registers' Read/Write Commands
Opcode
(Hex)
Instruction
00
ReadlWrite Mode register
01
ReadlWrite Descriptor Address register
20
ReadlWrite Descriptor Selector Count register
Table 3. 'Status Registers' Access Instructions
Opcode
(Hex)
02
Instruction
Read Trap Type register
03
Read Violation Segment Number register
04
Read Violation Offset (high-byte) register
Table 1 gives the five commands that are used to write
data into descriptor fields.
05
Read Bus Status register
06
Read Instruction Segment Number register
Table 1. Descriptor Field Write Commands
07
Read Instruction Offset (high-byte) register
11
Reset Trap Type register
13
Reset SWW flag in VTR
14
Reset FATL flag in VTR
Read Violation, Offset (low-byte) register
Opcode
(Hex)
Instruction
OA
ReadlWrite Attribute field
21
OB
ReadlWrite Descriptor (all fields)
22
Read ReadlWrite Data Counter register
OE
ReadlWrite Attribute field; increment DAR
23
Read Instruction Offset (low-byte) register
OF
ReadlWrite Descriptor (all fields); increment
DAR
15
Reset all Valid Attribute flags
USE OF THE PMMU WITH OTHER
Z8000 CPUs
The PMMU is designed to operate in conjunction with
the Z8003 VMPU; however, it can also be used with
other CPUs in the Z8000 Family. The following examples
suggest simple system configurations; more sophisticated arrangements are possible.
The Z8004 VMPU generates nonsegmented 16-bit addresses only. The PMMU can be used to implement a
paged virtual memory by tying the segment number inputs of the PMMU to 0 and requiring the most'significant
224
seven bits of the logical address field to be O. Since the
Z8004 VMPU lacks a translation trap request input pin,
the nonmaskable (or other interrupt request) pin should
be used instead.
The PMMU extends the physical addressing capability of
the Z8004 without using the segmentation mechanism of
the Z8003. This use is similar to the way in which 16-bit
minicomputers extend their addressing capability.
The Z8001 and Z8002 CPUs do not support the instructionabort mechanism. A page fault for one of these
CPUs is, in general, non-recoverable, since during an interrupt, the current instruction runs to completion,
possibly overwriting CPU registers. For the nonsegmented Z8002, this means that all pages that the CPU
can access must be in physical memory and appropriate
information must be in the PMMU page descriptor
registers. For the segmented Z8001 , this means that programs must explicitly request segments before accessing them and must free segments after use. It also
means that segments are allocated in units of the page
size and that limit protection is performed with this
granularity. Use of the PMMU with the Z8001 and Z8002
CPUs permits a paged allocation of main memory and
extends the physical address capability of the Z8002.
PMMU TIMING
The PMMU translates addresses and checks for access
violations by stepping through sequences of basic clock
cycles corresponding to the cycle structure of the
VMPU. Timing diagrams that show the relative timing
relationships of PMMU signals during the basic operations of memory read/write and PMMU control commands are given in this section.
Memory Read and Write
Memory read and instruction fetch cycles are identical,
except for the status information on the STo-ST3 inputs.
During a memory read cycle (Figure 8), the 7-bit segment number is input on SNo-SNs one clock period
before the address offset; a High on DMASYNC during
T3 indicates that the segment offset data is valid. The addr'ess offsets are placed on the ADo-AD15 inputs early in
the first clock period. Valid address offset data is indicated by the rising edge of AS. Status, mode, and chip
enable information becomes valid early in the memory
access cycle and must remain stable throughout. The
most significant 16 bits of the address (physical memory
location) remain valid until the end of T3. Abort Request,
Trap Request, and Suppress are asserted in T2 (Figure
9). Abort Request is asserted for four clock cycles. Trap
Request remains Low until trap acknowledge
(status = 0100) is received. Suppress is asserted during
the current machine cycle and terminates during T3.
PMMU Command Cycle
During the command cycle of the PMMU (Figure 11),
commands are placed on lines ADs':'AD15 during T1. The
status lines indicate that a Special I/O instruction is in
progress, and the CS line enables the appropriate PMMU
for that command. Data to be written to a register in the
PMMU must be valid on lines ADs-AD15 late in T2. Data
read from the PMMU is placed on lines ADs-AD15 late in
the TWA cycle.
Input/Output and Refresh
Input/output and refresh operations are indicated by
codes on status lines STo-ST3' During these operations,
the PMMU refrains from any address translation or protection checking. Lines Aa-A23 remain 3-stated during
these operations.
Reset
edge of the Reset signal; a software reset is performed
by a VMPU special I/O command. A hardware reset
clears the Mode register, Trap Type Register, and
Descriptor Selection Count register. If the CS line is Low,
the Master Enable flag in the Mode register is set to 1. All
other registers are undefined. After reset, lines
ADo-AD15 and Aa-A23 are 3-stated. The SUP and
ABORT open-drain outputs are not driven. If the Master
Enable flag is not set during reset, the PMMU does not
respond to subsequent addresses on its AD lines. To
enable a PMMU after a hardware reset, a PMMU command must be used in conjunction with CS.
A software res!3t occurs when the Reset Violation Type
Register command is issue~:L This command clears the
Trap Type Register and returns the PMMU to its initial
state (as if no violations or warnings had occurred). Note
that the hardware and software resets have different effects.
Abort, Trap Request, and Aclmowledge
The PMMU generates a Trap Request whenever it fails to
find a page entry corresponding to the logical address
(that is, a page fault), detects an access violation, or
detects a write into the lowest 128-byte block of a page
. with the DIRW flag set (Figure 12). In the case of an access violation or page fault, the PMMU also activates
Suppress and Abort Request. The Suppress Signal is used by memory to inhibit memory writes. The Trap Request remains Low until a trap acknowledge signal
(status = 0100) is received. Violations detected during
DMA cycles cause Suppress to be asserted during that
cycle only, but no Trap Request is generated.
When the PMMU issues a Trap Request, it awaits the indication of' a trap acknowledge. Subsequent violations
occurring before the trap acknowledge indication is
received are detected and appropriately processed. During a Trap Acknowledge cycle, the PMMU drives one of
its Address/Data lines; the selection of the line is a function of the identification field of the Mode register. After
the Trap Request has been acknowledged by the VMPU,
the Violation Status register should be read by a special
I/O command in order to determine the cause of the trap.
The Trap Type register should be reset so that subsequent traps are recorded correctly.
The PMMU can be reset by either hardware or software
mechanisms. A hardware reset occurs on the falling
225
CLK
-
TN
T1
T2
T3
I
I
I
I
NIS,
STo-ST3
SNo-SN6
SEGMENT NUMBER
DON'T CARE
\
/
,
J
DMASYNC
/
ADDRESS VALID
\
,
ADa-AD15
)---
MEMORY ADDRESS
I
(
DATA IN
>
/
RIW
/
L
Figure 8. Memory Read Timing
226
2081-009
T1
T2
TWA
TWA
TWA
TWA
AD
ALLOW MORE WAIT STATES
T3
T1
flJL
eLK
AS
'ir
TWA
,f~
.
\J
=>DC
~XJOC
"'~----------------------------~--------~/)'
DEASSERTED
f i N TRAPACK
"'~--------------------------------------~'f
\____
~r/
Figure 9. Abort and Trap Request Timing
2081-010
227
eLK
-
TN
T1
T2
T3
I
I
I
I
NIS,
STO-ST3
SEGMENT NUMBER
SNo-SN6
DON'T CARE
\
/
,
J
DMASYHC
ADa- AD 15
/
ADDRESS VALID
\
DATA OUT
MEMORY ADDRESS
L
R/W
Figure 10. Memory Write
228
)-
Ti~lng
2081-011
Tj
T2
TWA
II
CLOCK
I
-
I
T3
•
I
I
CS
STO-ST3
HIS
-
=x
- ---------
~-------
-------- -------- .. ---LOW
AS
ADa-AD15
INPUT
-
1\
-
ex
-
J
'COMMAND VALID
}- -
-
-
-
DATA IN
--
I
c
DS
~
R/v.;
,
L
,
ADa-AD15
OUTPUT
<
-
=x
-
r\
COMMAND VALID
DATA OUT
OS
R/v.;
r
Figure 11. 1/0 Command Timing
2081-012
229
I~.~
___________________________
ACK~~~C:DGE
____________________________~.~I~~~~~
AUTOMATIC WAIT STATES
r_-----------TWA
TWA
TWA
A
------------_
TWA
TWA
Ts
CLOCK
RIW
HIGH
SEGMENT TRAP ACKNOWLEDGE
<
IDENTIFIER
)
'--------'
ADO-A D15
Figure 12_ Trap Request and Acknowledge Timing
SIGNAL DESCRIPTIONS
The 28015 is produced in a 64-pin package; the functions performed by the device's input and/or output pins
are shown in Figure 13. Pin/signal name assignments
are shown in Figure 14. The device sig'nal names
together with a brief description of the function(s) performed by each are given in the foJlowing paragraphs.
Aa-A23. Address
Bus
(out'puts,
active
High,
3-state). These address lines are.the16 most significant
bits of the physical memory location.
ABORT. Abort Request (output, active low, open
drain). A low on this line indicates MMU requests for an
instruction abort. This line is enabled when a page fault
or access violation is detected.
AOO-A015. Address/Data Bus (inputs/outputs, active
High, 3-state). ADo-AD? are used for addresses and inputs only. They carry the low-order byte in the offset of
logical addresses intended for translation. ADa-AD15
are multiplexed address and data lines that are used
both for the eight most significant bits of the logical address and for commands.
230
. AS. Address Strobe (input, active low). The rising edge
of A8 indicates that lines ADo-AD15, 8To-8T3, R/W, CE,
and Nis are valid.
CEo Chip Enable (input, active low). This line selects a
PiviiviU to translate a logical address.
+ 5 V singlephase, time-base input used for both the VMPU and
PMMU.
ClK. System Clock (input). ClK is a
CS. Chip Select (input, active low). This line selects a
PMMU for a control command.
OMASYNC. DMA/Segment Number Synchronization
Strobe (input, active High). A low on this line indicates a
DMA access is occurring; a High indicates the segment
number is valid. It must be High during VMPU cycles and
low when 8N lines are 3-stated.
OS. Data Strobe (input, active low). This line provides
timing for the data transfer between the PMMU and the
28003 VMPU.
2081-013
Table 4. Status Lines
N/S. Normal/System Mode (input, Low = System
mode). N/S indicates to the PMMU that the VMPU or
DMA is in the Normal or System mode.
RESET. Reset (input,- active Low). A Low on this line
resets the PMMU.
R/W. Read/Write (input, Low = write). R/Windicates
whether the VMPU is reading from or writing to either
memory or the PMMU.
SNo-SNs. Segment Number (inputs, active High).
These lines provide the 7~bit segment number of a logical address.
STo-ST3. Status (inputs, active High). These lines
(Table 4) specify the status of the associated VMPU.
SUP. Suppress (output, active Low, open-drain). This
signal is asserted during the current bus cycle when a
page fault or any access violation, except write warning,
occurs.
TRAP. Trap Request (output, active Low, opendrain). The PMMU interrupts the VMPU with a Low on
this line when the PMMU detects a page fault, access
violation, or write warning.
Definition
0000
Internal operation
0001
Memory refresh
0010
1/0 reference
001 1
Special 1/0 reference (for example, to a
PMMU)
0100
Translation trap acknowledge
01 01
Nonmaskable interrupt acknowledge
01 1 0
Nonvectored interrupt acknowledge
o1 1 1
Vectored interrupt acknowledge
1000
Data memory request
1 001
Stack memory request
10 10
Data memory request (External Processing
Architectu re)
10 1 1
Stack memory request (External Processing
Architecture)
1 1 00
Instruction space access
110 1
Instruction fetch, first word
11 10
External Processing Unit-CPU transfer
1111
Bus lock, data memory request
AD1S
ADa
A D13
ADDRESSI
DATA BUS
AD12
N/S
ADll
R/W
A23
A22
ADs
A2l
RESERVED
AD7
A20
STo
ADs
An
RESERVED
ADs
A1S
RESERVED
AD4
An
AD3
A16
1
AD2
,A1S
Au
ADs
ADo
A13
ADg
ZOO15
ABORT REQUEST
DMAISEGMENT
A12
ClK
All
GND
SNs
Al0
AD10
SN4
Ag
ADll
SN3
As
AD12
SN2
AD13
SUP
AD14
A12
All
AD7
TRAP
Al0
Vee
GND
ADs
ABORT
DMASYNC
R/W
AS
ST3
OS
ST2
STl
cs
STo
CE
Figure 13. Pin Functions
2081-014,015
SUPPRESS
SNo
N/S
CHIP SELECT
CHIP ENABLE
ST3
SNs
SNl
TRAP REQUEST
STl
ST2
PHYSICAL
ADDRESS
ADl
PMMU
SEaMENT
NUMBER
AS
OS
AD10
AD9
)
STATUS
AD15
Ag
ADs
As
AD4
RESERVED
AD3
SNs
AD2
SNs
ADl
,SN4
ADo
SN3
SNo
SN2
Figure 14. Pin ASSignments
231
AC CHARACTERISTICS
The following composite timing diagram shows the AC
timing relationships of the PMMU's control, address, and
data signals. The ac characteristics of these signal relationships are described in the AC Characteristics Table.
AC CHARACTERISTICS TABLE'
No_ Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Clock Cycle Time
TcC
CJock Width (High)
TwCh
TwCI
Clock Width (low)
Clock Fall Time
TfC
Clock Rise Time
TrC
TdDSA(RDv) - - OS ! (Acknowledge) to Read Data Valid Delay
TdDSA(RDD
OS t (Acknowledge) to Read Data Float Delay
TdDSR(RDv)
OS I (Read) to AD Output Driven Delay
OS t (Read) to Read Data Float Delay
TdDSR(RDf)
TdC(WDv)
ClK t to Write Data Valid Delay
ThC(WDn)
ClK.! to Write Data Not Valid Hold Time
TwAS'
Address Strobe Width
TsOFF(AS)
Offset Valid to AS t Setup Time
ThAS(OFFn)
AS t to Offset Not Valid Hold Time
AS I to ClK t Delay
TdAS(C)
TdDS(AS)
OS t to AS ! Delay
TdAS(DS)
AS t to OS I Delay
TsSN(C) - - - SN Data Valid to ClK t Setup Time
ThC(SNn)
ClK t to SN Data Not Valid Hold Time
DMASYNC Valid to ClK t Delay
TdDMAS(C)
TdSTNR(AS)
Status (STo-ST3 , NiS, R/W) Valid to 'AS t Delay
TdC(DMA)
ClK t to DMASYNC ! Delay
TdST(C)
Status (STo-ST3 ) Valid to ClK t Setup Time
TdDS(STn)--DS t to Status Not Valid Delay
TdOFF(Av)
Offset Valid to Address Output Valid Delay
TdST(Ad)
Status Valid to Address Output Driven Delay
TdDS(Af)
OS t to Address Output Float Delay
TdAS(Ad)
AS ! to Address Output Driven Delay
TdC(Av)
ClK ! to Address Output Valid Delay
TdAS(TRAP) --AS t to TRAP I Delay
TdC(TRAP)
ClK t to TRAP t Delay
TdAS(SUP)
AS t to SUP! Delay
TdDS(SUP)
OS t to SUP t Delay
TsCS(AS)
Chip Select Input Valid to AS t Setup Time
ThAS(CSn)
AS t to Chip Select Input Not Valid Hold Time
TdAS(C)
AS t to ClK t Delay
TsCS(RST)
Chip Select Input Valid to RESET t Setup Time
ThRST(CSn)
RESET t to Chip Select Input Not Valid Hold Time
TwRSTI
RESET Width (low)
TdC(RDv)
ClK t to Read Data Valid Delay
TdDS(C)
OS t to ClK t Delay
TdC(DS)--- ClK I to OS t Delay
TdAS(ABORT)
AS t to ABORT I Delay
ClK ! to ABORT t Delay
TdC(ABORT)
TdCE(Av)
CEI to Address Output Valid Delay
TsCE(AS)
CE ! to AS t Setup Time
ThAS(CEn)
AS t to Chip Enable Input Not Valid Hold Time
NOTES:
1. 50 pF load.
2. 2.2K pull·up.
3. All times given in nanoseconds (ns).
232
Parameters
Min
(4 MHz)
Max
(4 MHz)
Notes
250
105
105
20
20
20
20
100
75
100
75
160
1--
30
60
45
60
110
50
50
120
0
120
60
20
140
0
30
30
10
80
0
150
0
2TcC
200
180
160
170
155
110
300
115
155
460
30
0
30
0
60
110
110
155
235
1,2-1,2
1,2
1,2
CLOCK
TRAP
ACKNOWLEDGE
~
AOa-A 0 15
READ
MMU----+-+----+--~f-+-----+-~-8-<1.=~
=--{~1n-
____r-~~
__9~'1
~I>+--+--
___________ ~~----~----~-~10----+-------~--~-----+-®--11~~rWRITE MMU
_ __________
~~.
~--
_
J
-----------~~'"
OFFSET
:~
AOO-A015
..ll'.
){
~--_+_---__+---~--+__+..,_
>------ ----------------- --- -- ---- i--
.-®~
--------+~
-®
~~
}\r-~r_'l~
,y®-r-f--
--
~
/
--------~~~
OS
@--j
\~~______~____+-_____. . ~.Jt
~
MEMORY ACCESS
"1\.
/~
\,
~-~------.....;-r
----~)
,f
,~;J
MMUSYNC"
7"
,
1/
(
DTC
,.I-
>C
DTC
}--,-~
c;
DTC
>-a
~,,
,'I
"For logical addressing only.
""For physical addressing only.
Figure 12. Bus Request and Acknowledge Timing
2129-012
253
CLOCK
I
STo-ST3, B/W
(SN O- SN 7)* *
~
--A
LOW
N/S
MMUSYNC*
\
-~
X
(SNo-SNu) * __~______________~__________________________________- J
AD
~_________________
PORT ADDRESS
READ
IN
R/W
AD
WRITE
OUT
X
PORT ADDRESS
X
DATA OUT
OS
R/W
r
\
* For logical addressing only.
* * For physical addressing only.
Figure 13. Flowthrough I/O Transaction Timing
254
2129-013
I~T3~I~T1---'I~T2~I~T3-'1
CLOCK
INSERT WAIT STATE
STO-ST3,B/W ------------------~
N/S
(SN o- SN 7) * *
--.....------------....",
(SNO-SNO)*
I...
•
i
MMUSYNC*
MEMORY
ADDRESS
AD
READ
R/W
MEMORY
ADDRESS
AD
DATA OUT
WRITE
R/W
* For logical addressing only.
* * For physical addressing only.
Figure 14. Flowthrough Memory Transaction Timing
2129-014
255
· Flyby Transactions
A Flyby operation is performed during three T-states. AS
is pulsed during T1 to signal the output of address information. R/W is High if the current ARA specifies source,
and Low if the current ARB specifies destination. OS and
OACK are driven active during T2 to initiate the transfer,
and driven inactive during T3 to conclude the transfer.
Wait states can be inserted between T2 and T3 to extend
the active time to OS and OACK. Flyby transaction timing is shown in Figure 15.
CLOCK
STe-ST3
BiW, HIS***
(sNo-sN7)··
MMUSYHC*
(SHe-SHe)*
AD
TO FLYBY
PERIPHERAL
ADDRESS (B)
FROM FLYBY
PERIPHERAL
*Toggles for memory access in logical address space only.
*:: For p~ysical addressing only.
N/S Will be low for 110 transactions.
(A) Address is current ARA
(B) Address is current ARB
Figure 15. Flyby Transaction Timing
256
2129-015
DREQ Timing
DACK Timing
The following section describes DREQ timing for various
operations.
A High-to-Low transition of DREQ causes a single iteration of a DMA operation. A new transition can occur after
the Low-to-High AS transition on the first memory or I/O
access of the DMA iteration. Figure 16 shows the timing
for a new transition to be applied and recognized to
avoid giving up the bus at the end of the current iteration.
In Bus Hold mode, DREQ is sampled when a channel
gains bus control. If DREQ is Low, an iteration of a DMA
operation is performed. If DREQ is High, the channel retains bus control and continues to drive all bus control
signals active or inactive, but performs no DMA
operation.
In Demand mode during DMA operation, DREQ is sampled to determine whether the channel should perform
another cycle or release the bus (Figure 17).
DREQ is sampled after each Ene:! qf Chaining or Base-toCurrent Reloading operation. If UREQ is active, the
channel begins performing DMA operations immediately, without releasing the bus.
. During I/O and memory transactions, WAIT is sampled in
the middle of T2. If WAIT is High, and no programmable
Wait states are selected, the DTC proceeds to T3. Otherwise, one or more Wait states are inserted. WAIT is also
sampled during TWA. If WAIT is High the DTC proceeds
to T3, otherwise, additional Wait states are inserted.
When both hardware and software Wait states are inserted, each WAIT time is sampled. A Low causes a
hardware Wait state to be inserted in the next cycle.
Software Wait state insertion is suspended until WAIT is
High. Hardware Wait states can be inserted any time
during the software Wait state sequence. DACK timing is
shown in Figure 18.
EOP Timing
EOP is driven Low when a TC, MC, or EOP termination
occurs. When a DMA operation has terminated, EOP is
sampled on the falling edge of T3 to determine if EOP has
been driven Low. The generation of internal EOPs and
sampling of external EOPs for Transfers-and-Searches
follows the same timing used for Transfers. EOP timing
is shown in Figure 19.
1:'R8T ACCESS OF DMA ITERATION
LAST. ACC. ESS OF DMA ITERA.TION.. I
T14<1---T2~.r--TWA or T2--l>~T3
CLOCI(
\'----I:r-:_\~-r.-/__
Figure 16. Sample DREQ During Single Transfer DMA Operations
2129·016
257
1"-
THLO-----.j...--
THLO-----.I~ THLO-----'r--- TS--"~I"''''~-T1__1
CLOCK
\~--\~/_-------------(A) Sampling of DREO While in Bus Hold Mode
I
LAST ACCESS OF DMA ITERATION
r---T2 or
I
FIRST ACCESS OF NEXT DMA ITERATION
T1-----1~TwA or T2~r----T3---''--T1---''~T2~1
CLOCK
\
/
(B) DREO Sampling in Demand Mode During DMA Operations
j..--T2 or
T1~I""-TWA or T2 --.1"--T3---'1~ T1P--.I~Ts---..l..-- T 1 - -
CLOCK
\
/
(C) Sampling DREO at the End of Chaining
I~TAU2-------..I~TAU3----"I~TAU4-------"I~TCO----ilo--I~Ts~I~T1-CLOCK
\
/
(D) Sampling DREO at End of Base-to-Current Reloading
Figure 17_ DREQ Sampling in Demand Mode
258
2129-017
I~T1--"I~T2~I""'--T3---..I~T1P~I~TSCLOClt
\~
LEVEL
DACK
_ _ _ _ _.....JI
PULSED
DACK (FLYBY)
\
I
f
TO
FROM
""_ _ _F_L_YB_Y_........_____ . - FLYBY
110-1/0
I/O-MEM
Y/""""'--Figure 18. DACK Timing
I~THLD~I-.--THLD-..I.-TIDLE-CLOCK
EXTERNAL
EOP
I~TWA orT2--.I~T3---I~~I~T1P---.I~TAU1CLOCK
EOP ________________
~T~NM
\ __ /_____________________________________
~
~
INTERNAL
EOP
Figure 19. EOP Timing
2129-018,019
259
ACTIVE STATE TIMING
CD
I----
A D o- AD15
~
11
)
r
:X:
DATA IN
~~ ~=f.
DATA OUT
~
~ -@-
C
-
-®
~
-®-
1
~
MEMORY READ
MEMORY WRITE
INPUT/OUTPUT
-@-/ +@
-N----®--
0
-®- ~\l
-® 1
/
STo-ST3,
, READIWRITE,
NORMALISYSTEM,
BYTEIWORD,
260
.f2a\----
7J3'=
-®-
/"
L.-
((
}J
r-®-
:X~
K=
-@H
~I
-®--I
((
7J
-®
(r - -
-®-I
..--®i>
,.....
7J
/
....
I
,..v ~
HJH
H9-
~
V
-®-
~
/
/rc-
I>--
®-1-
(
-- --®i
'-~
~
1>~i
22
~
1INTERRUPT
ACKNOWLEDGE
JiG\-
1
~
I--
~
~
"
.... ~
~r-
~
Y -
-
~
~
'"
I
2129-020
AC CHARACTERISTICS
No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Description
Clock Cycle Time
TcC
Clock Width (High)
TwCh
TwCI
Clock Width (low)
Clock Fall Time
TfC
Clock Rise Time
TrC
ClK I to Segment Number Valid (50pF load) Delay
TdC(SNv)
ClK I to Segment Number Not Valid Delay
TdC(SNn)
TdC(Bz)
ClK I to Bus Float Delay
ClK I to Address Valid Delay
TdC(A)
TdC(Az)
ClK I to Address Float Delay
TdA(DI)
Address Valid to Data in Required Valid Delay
TsDI(C)
Data In to ClK I Setup Time
TdDS(A)
OS I to Address Active Delay
TdC(DO)
ClK I to Data Out Valid Delay
ThDI(DS)-'--Data In to OS I Hold Time
TdDO(DS)
Data Out Valid to OS I Delay
TdDO(SW)
Data out Valid to OS I (Write) Delay
TdC(ASf)
ClK I to AS I Delay
TdA(AS)
Address Valid to AS I Delay
TdC(ASr)---ClK I to AS I,Delay
TdAS(DI)
AS I to Data In Required Valid Delay
TdDS(AS)
OS I to AS I Delay
TwAS
AS Width (low)
TdAS(A)
AS I to Address Not Valid Delay
TdAz(DSR) - - Address Float to OS (Read) I Delay
TdAS(DSR)
AS t to OS I (Read) Delay
TdDSR(DI)
OS (Read) I to Data In Required Valid Delay
TdC(DSr)
ClK I to OS I Delay
TdDS(DO)
OS I to Data Out (Write only) and Status Not Valid
(Read and Write) Delay
TdA(DSR)
Address Valid to OS (Read) I Delay
TdC(DSR)
ClK I to OS (Read) I Delay
TwDSR
OS (Read) width (low)
TdC(DSW)
ClK I to OS (Write) I Delay
TwDSW
OS (Write) Width (low)
TdDSI(DI)
OS (Input) I to Data in Required Valid Delay
TdC(DSf)
ClK I to OS (I/O) I Delay
TwOS
OS (I/O) Width (low)
TdAS(DS)
AS t to OS I (ACK) Delay
TdC(DS) - - - ClK I to OS I (ACK) Delay
TdSA(DI)
OS I (ACK) to Data in Delay
TdC(S)
ClK I to Status Valid Delay
TdS(AS)
Status Valid to AS I Delay
TsWT(C)
WAIT to ClK I Setup Time
ThWT(C)
WAIT to ClK I Hold Time
Min (ns)
(4 MHz)
250
105
105
Max (ns)
(4 MHz)
2000
20
20-110
20
65
90
65-400
20
80
00
CO
C
90
...
0
230
55
Ol
~
70
'n"
~
50
70-300
75
80
60
0
75
165
60
85
120
60
275
60
160
325
60
160*
100
100-150
110
60
20
10
*Insert Wait states via software or hardware when accessing slow peripherals,
261
INACTIVE STATE TIMING
ADDRESS
ADo-AD15
lOR ------1-1------0(
lOW -----+-~-O(I
1/0
INTERRUPT
ACKNOWLEDGE
STO-ST3,R/W, B/W
BUS EXCHANGE TIMING
,
~-----------~~----~~~------~ ~--7?-----~~~----~~
,
II
"For logical addressing only.
··For physical addressing only.
Note 1: The OTC will begin driving t.he bus on the clock cycle following the clock cycle In which the set·up parameters are met.
262
2129·021,022
AC CHARACTERISTICS (Continued)
No. Symbol
Description
TdDSA(RDZ)
DS I Acknowledge) to Read Data Float Delay
TdDSR(DOD)
DS I (IOR)to Data Output Driven Delay
TdDSR(RDZ)
DS I (lOR) to Read Data Float Delay
TwAS 1
AS low Width
TsA(AS)
Address Valid to AS I Setup Time
ThAS(A)
AS I to Address Not Valid Hold Time
TsCS(AS)
CS Valid to AS I Setup Time
ThCS(AS)
AS I to CS Not Valid Hold Time
TdDS(Dn)
DS I (lOW) to Data Not Valid Delay
TdA(DRV)--'-Address Valid to Data (lOR) Required Valid Delay
TdA(DS)
Address Float to DS I (lOR) Delay
TwDS(IO)
DS (10) low Width
Data Valid to DS I Setup Time (lOW)
TsD(DS)
DS I (lOW) to DS I (lOW) (Write Recover Time applies only for
TrDsh(DSR)
issuing command)
AS I to DS I (ACK) Delay
62 TdASh(DSe)
DS (ACK) Width low
63 TwDS(AK1)
64 TsS(AS)
Status Valid to AS I Setup Time
DS I (lOR) to Data Not Valid Delay
65 TdDSW(Dn)
66 TdASh(DSI)--AS I to DS I Delay (10)
DREO Valid to ClK I Setup Time
67 TsDRO(c)
ClK I to DREO Valid Hold Time
68 ThDRO(C)
ClK I to BUSREO I Delay
69 TdC(BROf)
ClK I to BUSREO I Delay
70 TdC(BROr)
71 TdBRO(BAI)-- BUSREO I to BAI I Required Delay
72 TsBAK(C)
BAI Valid to ClK I Setup Time
ClK I to Segment No. Valid (50pF load) Delay
73 TdC(SNv)
74 TdC(ASf)
ClK I to AS I Delay
ClK I to Status Valid Delay
75 TdC(S)
76 TdBRO(BUSc)-BUSREO I to Control Bus Float Delay
ClK I to Address Valid Delay
77 TdC(A)
78 TdBRO(BUSd)
BUSREO I to AID Bus Float Delay
79 TdQ(SNr)
ClK I to SN7/MMUSYNC I Delay**
ClK I to SN7/MMUSYNC I Delay**
80 TdC(SNf)
48
. 49
50
51
52
53
54
55
56
57
58
59
60
61
Min (ns)
(4 MHz)
Max (ns)
(4 MHz)
60
135
60
70
30
40
0
40
25
540-0
150
40
N
00
0
...
4tcC
100
150
20
25
100
50
20
•ItI
"fI
150
150
0
50
20
110
70
110
140-90
140
110
110
**Logical Addressing Only.
263
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs
with respect to GND ............... ~0.3 V to
Stresses greater than those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only: operation of the device at any condition above those indicated in
the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
, may affect device reliability.
+ 7.0 V
Operating Ambient
Temperature ............... See ordering information
Storage Temperature ............. -65°C to
+ 150 °C
STANDARD TEST CONDITIONS
+5V
The characteristics below apply for the following standard test conditions, unless otherwise noted. AII,voltages
are referenced to GND. Positive current flows into the
referenced pin. Standard conditions are as follows:
E1
+ 4.75 V
c
GND =
:5 Vcc:5
+5V
2.2K
FROM OUTPUT
UNDER TEST
+ 5.25 V
aV
D TA as specified in Ordering Information
~I
2'2K
50PF
.
All ac parameters assume a load capacitance of 50 pF
max.
Open-Drain Test Load
Standard Test Load
DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Unit
VCH
Clock Input High Voltage
Vcc-O.4
Vcc+ 0.3
V
Driven by External Clock Generator
VCl
Clock Input Low Voltage
-0.3
0.45
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
VCC+ 0.3
V
Vil
Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
0.4
III
Input Leakage
±10
IOL
Output Leakage
±10
Icc
Vcc Supply Current
350
NOTE: Vce = 5 V ± 5% unless otherwise specified.
264
Condition
2.4
V
10H
VIOL
p.A
0.4
= -250 p.A
= +2.0 mA
:5
VIN
:5
+ Vcc
ORDERING INFORMATION
Product
Number
Package/
Temp
Speed.
Description
Product
Number
Paclmge/
Temp
Speed
Description
Z8016
CS
4.0 MHz
OTC (48-pin)
Z8016A
CS
6.0 MHz
OTC (48-pin)
Z8016
PS
4.0 MHz
Same as above
Z8016A
PS
6.0 MHz
Same as above
M B =' -55°C to
+ 125 °C with
=
=
=
= -55°C to + 125 °C,
NOTES: C
Ceramic, P
Plastic; E
-40°C to + 85°C, M
MIL-STD-883 Class B processing, S = O°C to + 70°C.
00-2129-01
265
~$(Q)33@ ~8(O)(O)(Q)TM !aSCtr;
meJrnan (C«1>WUllWlnImnccalnoJms
CC@UUftil@nn]lDfJ«:fiUii«:aftii@Im
September 1983
Features
[J
[J
[J
Genoral
Description
Two independent, 0 to 1M bit/second, fullduplex channels, ea~h with a separate
crystal oscillator, baud rate generator, and
Digital Phase-Locked Loop for clock
recovery.
Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
ADDRESS'
DATA BUS
--
--
BUS{_
TIMING
ANDRESET CONTROL
INTERRUPT
{=:
1=
ADT
TxDA
ADs
RxDA
ADs
TRxCA
_
[J
AD3
SYNCA
AD2
W/RECA
AD,
DTR/RECA
ADo
RTSA
As
Os
CTSA
} SERIAL
DATA
AD,
CH·A
CHANNEL
CONTROLS
FOR MODEM,
DMA,OR
OTHER
CS,
RxDB
CSo
TRxCB
iNT
_
W/RECB
lEO
DTR/RECB
RTSB
Z8030
Z·SCC
t t
CTSB
DCoii
AD.
ADT
ADs
iNT
os
lEO
As
lEI
R/W
INTACK
CSo
--
CHANNEL
CONTROLS
FOR MODEM,
DMA,OR
OTHER
W/RECB
RTxCA
SYNCB
RxDA
CH·B
CS,
GND
SYNCA
TRxCA
SYNCB
lEI
+5 V
} SERIAL
DATA
} CHANNEL
CLOCKS
RTxCB
INTACK
AD2
ADs
W/RECA
TxDB
ADo
AD3
+5V
DCDA
R/W
Local Loopback and Auto Echo modes.
communications applications. The device contains a variety of neW, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
-}CHANNEL
CLOCKS
RTxCA _
AD,
Synchronous mode with internal or external
character synchronization on one or two
synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
[] SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial converter/controller. The Z-SCC can be softwareconfigured to satisfy a wide variety of serial
--
TxDA
DTR/RECA
RTxCB
R~DB
TRxCB
TxDB
RTSA
DTR/RECB
CTSA
RTSB
DCDA
CTSB
PCLK
DCDB
GND PCLK
Figuro 1. Pin FunctloD1J
2016-039, 041
IJ
Figuro 2. Pin Asalgnmonta
267
General
Description
(Continued)
The Z-SCC handles asynchronous formats,
synchronous byte-oriented protocols such as
IBM Bisync, and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
The device can generate and check CRC
codes in any Synchronous mode and can be
programmed to check data integrity in various
modes. The Z-SCC also has facilities for
modem controls in both channels. In applications where these controls are not needed,
the modem controls can be used for
general-purpose I/O.
The i-Bus daisy-chain interrupt hierarchy
is also supported-as is standard for Zilog
peripheral components.
The Z8030 Z-SCC 'is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.
Pin
Description
The following section describes the pin
functions of the Z-SCC. Figures 1 and 2 detail
the respective pin functions and pin
assignments.
lEI. Interrupt Enable In (input, active High).
IEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
ADo-AD7' Address/Data Bus (bidirectional,
active High, 3-state). These multiplexed lines
carry register addresses to the Z-SCC as well
as data or control information to and from
the Z-SCC.
AS. Address Strobe (input, active Low).
Addresses on ADo-AD7 are latched by the rising edge of this signal.
CSo. Chip Select 0 (input, active Low). This
signal is latched concurrently with the
addresses on ADo-AD7 and must be active for
the intended bus transaction to occur.
CSI. Chip Select 1 (input, active High). This
second select signal must also be active before
the intended bus transaction can occur. CSI
must remain active throughout the transaction.
CTSA. CTSB. Clear to Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables their
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The Z-SCC detects pulses on these inputs and
can interrupt the CPU on both logic level
transitions.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input 'pins. Both pins are
Schmitt-trjgger buffered to accommodate slow
rise-time signals. The Z-SCC detects pulses on
these pins and can interrupt the CPU on both
logic level traI'lsitions.
DS. Data Strobe (input, active Low). This
signal provides timing for the transfer of data
into and out of the Z-SCC. If AS and DS coincide, this is interpreted as a reset.
DTR/REQA. DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
268
lEO. Interrupt Enable Out (output, active
High). IEO is, High only if lEI is High and the
CPU is not servicing a Z-SCC interrupt or the
Z-SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). IEO is connected to
the next lower priority device's lEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
Z-SCC requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
Z-SCC interrupt daisy chain settles. When DS
becomes active, the Z-SCC places an interrupt
vector on the data bus (if lEI is High).
IN TACK is latched by the rising edge of AS.
PCLK. Clock (input). This is the master Z-SCC
clock used to synchronize internal signals.
PCLK is not required to have any phase relationship with the master system clock, although
the frequency of this clock must be at least
90% of the CPU clock frequency for a Z8000.
P.CLK is a TTL level signal.
RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock of the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be 1, 16, 32, or 64 times the
data rate in Asynchronous modes.
RTSA. RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 11) is set, the
Pin
Doscription
(Continued)
RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto
'Enable is on, the signal goes High after the
transmitter is empty. In Synchronous mode or
in Asynchronous mode with Auto Enable off,
the RTS pin strictly follows the state of the RTS
bit. Both pins can be used as general-purpose
outputs.
R/W. Read/Write (input). This signal specifies
whether the operation to be performed is a
read or a write.
TxDA, TxDB. Transmit Data (outputs, active
High) .. These output signals transmit serial data
at standard TTL levels.
SYNCA, SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either
as inputs, outputs, or part of the crystal
oscillator circuit.
In the Asynchronous Receive mode (crystal
oscillator option not selected), these pins are
inputs similar to CTS and DCD. In this mode,_
transitions on these lines affect the state of the
Synchronous/Hunt status bits in Read Register
a (Figure 10) but have no other function.
In External Synchronization mode with the
crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be
driven Low two receive clock cycles after
the last bit in the synchronous character is
received. Character assembly begins on the
rising edge of the receive clock immediately
preceding the. activation of SYNC.
In the internal Synchronizatlon mode
Functional
Description
TRxCA, TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the output of the Digital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or 'the transmit clock in the output
mode.
W/REQA, W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to
synchronize the CPU to the Z-SCC data rate.
The reset state is Wait.'
following description briefly detail these
protocols.
The functional capabilities of the Z-SCC
can be described from two different points
of view: as a data communications device,
. it transmits and receives data in a wide
variety of data communications protocols;
as a Z8000 Family peripheral, it interacts
with the Z8000 CPU and other peripheral
circuits and is part of the Z-Bus interrupt
stru8ture.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optiorial even or odd parity.
The transmitters can supply one, one-anQ-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the. start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
mechanism that checks the signal one-half a
Data Communications Capabilities. Th~
Z-SCC provides two independent full-duplex
channels programmable for use in any common Asynchronous or Synchronous datacommunication protocol. Figure 3 and the
tr
(Monosync and Bisync) with the crystal
oscillator not selected, these pins act as outputs and are active only during the part of the
receive clock cycle in which synchronous
characters are recognized. The synchronous
condition is not latched, so these outputs are
. active each time a synchronization pattern is
recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag.
PARITY
T
STr
-MA-R-KI-NG-L-IN-E----,I I
DATA
I I I IIr-- T-A ""11""11""11""111
DA
,
DATA
SYNC
p
DATA
II I I MARKING LINE
ASYNCHRONOUS
::
1
DATA
CRC1
CRC2
DATA
CRC1
CRC2
DATA
CRC1
CRC2
CRC1
CRC2
MONOSYNC
SYNC
SYNC
DATA
SIGNAL
+
1
DATA
::
BISYNC
:;
EXTERNAL SYNC
FLAG
1 ADDRESS 1
INFO{MtTlON
'I
FLAG
SDLC/HDLC/X.25
Figure 3. Some Z-SCC Protocols
2042-108
269
Functional
Description
(Continued)
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure 1). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored inter.rupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process aVQ.ids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The Z-SCC does not require symmetric
transmit and receive clock signals-a feature
allOWing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of 1, 1/16, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
Synchronous Modes. The Z-SCC supports both
byte-oriented and bit-oriented synchronous
communication. Synchronous byte-oriented
protocols can be handled in several modes,
allowing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync),
any I2-bit synchronization pattern (Bisync), or
with an external synchronization signal.
Leading synchronous characters can be
removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or I6-bit patterns in the
Z-SCC by overlapping the larger pattern
across multiple incoming synchronous
characters as shown in Figure 4.
CRC checking for Synchronous byteoriented modes is delayed by one character
time so that the CPU may disable CRC checking on specifiC characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-I6 (X16 + XIS + X2 + 1) and
CCITT (X16 + XI2 + XS + 1) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all Os. The Z-SCC also
provides a feature th~t automatically transmits
CRC data when no other data is available for
transmission. This allows for high speed
transmissions under DMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in Synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous
characters, regardless of the programmed
character length .
The Z-SCC supports Synchronous bitoriented protocols, such as SDLC and HDLC,
by performing automatic flag sending, zero in":
sertion, and CRC generation. A special command can be used to abort a frame iri transmission. At the end of a message, the Z-SCC
automatically transmits the CRC and trailing
flag when the transmitter underruns. The
.
transmitter may also be programmed to send
an idle line consisting of continuous flag
characters or a steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The Z-SCC may also be
programmed to send an abort itself in case of
an underrun, relieVing the CPU of this task.
One to eight bits per character can be sent,
allowing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver Can be
programmed to search for frames addressed by
a single byte (or four bits within a byte) of a
user-selected address or to a global broadcast .
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (endof-frame) can be selected. The receiver
automatically deletes all Os inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SDLC
mode, the Z-SCC must be programmed to use
the SDLC CRC polynomial, but the generator
. and checker may be preset to all Is or all Os.
5 BITS
,..--"----..
~YNC
SYNq
I
SYNC
I
DATA
DATA
DATA
DATA
--- ..,-----.....16
Figure 4. Detecting 5- or 7-Bit Synchronous Characters
270
2042·109
Functional
Description
(Continued)
The CRC is inverted before transmission and
the receiver checks a.gainst the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any
lx mode. The parity options available in Asynchronous modes are available in Synchronous
modes.
The Z-SCC can be conveniently used under
DMA control to provide high-speed reception
or transmission. In reception, for example, the
Z-SCC can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The Z-SCC then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received. The CPU may also enable the
DMA first and have the Z-SCC interrupt only
on end-of-frame.This procedure allows all
data to be transferred via the DMA.
SOLe Loop Mode. The Z-SCC supports SDLC
Loop mode in addition to normal SDLC. In an
SDLC Loop, there is a primary controller
station that manages the message traffic flow
on the loop and any number of secondary
stations. In SDLC Loop mode, the Z-SCC performs the functions of a secondary station
while a Z-SCC operating in regular SDLC
mode can act as a controller (Figure 5).
A secondary station in an SDLC Loop is
always listening to the messages being sent
around the loop, and in fact must pass these
messages to the rest of the loop by retransmitting them with a one-bit-time delay. The
secondary station can place its own message
on the loop only at speCific times. The controller signals that secondary stations may
transmit messages by sending a special
character, called an EOP (End Of Poll),
around the loop. The EOP character is the bit
pattern 11111110. Because of zero insertion
during messages, this bit pattern is unique and
~asily recognized.
. When a secondary station has a message to
transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0
before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop
and terminates the message with an EOP. Any.
secondary stations further down the loop with
messages to transmit can then append their
messages to the message of the first secondary
station by the same process. Any secondary
stations without messages to send merely echo
the incoming messages and are prohibited
from placing messages on the loop (except
upon recognizing an EOP).
SDLC Loop mode is a programmable option
in the Z-SCC. NRZ, NRZI, and FM coding may
all be used in SDLC Loop mode.
Baud Rate Generator. Each channel in the
Z-SCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The follOWing formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
baud rate =
2 (time constant + 2) X (BR clock period)
Digital Phase-Locked Loop. The Z-SCC con-.
tains a Digital Phase-Locked Loop (DPLL) to
recover clock information from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this
clock, along with the data stream, to construct
a clock for the data. This clock may then be
used as the Z-SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
Figure S. An SDLe Loop
2016·001
271
Functional
. Description
(Continued)
incoming data stream for edges (either 1 to a
or a to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
a to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the Z-SCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding The Z-SCC may be programmed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encodi~g, a 1 is represented by a High level
and a a is represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a a is represented by a change in
level. In FMl (more properly, bi-phase mark)
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a a is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transition occurs at the beginning of every
bit cell. A a is represented by an additional
transition at the center of the bit cell, and a 1
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the Z-SCC can be used to
decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is a to I,
the bit is a O. If the transition is 1 to a the
bit is a 1.
Auto Echo and Local Loopback. The Z-SCC
is capable of automatically echoing everything
it receives. This feature is useful mainly in
Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto
Echo mode, TxD is RxD. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The Z-SCC is also capable of Local Loopback. In this mode TxD is RxD, just as in Auto
Echo mode. However, in Local Loopback
mode, the internal transmit data is tied to the
internal receive data and RxD is ignored
(except to be echoed out via TxD). The CTS
and DCD inputs are also ignored as transmit
and receive enables. However, transitions on
these inputs can still cause interrupts. Local
Loopback works in Asynchronous, Syn- .
chronous and SDLC modes with' NRZ, NRZIor
FM coding of the data stream.
1/0 Interface Capabilities. The Z-SCC offers
the choice of Polling, Interrupt (vectored or
nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the Z-SCC are automatically
updated whenever any function is performed.
For example, end-of-frame in SDLC mode
sets a bit in one of these status registers. The
idea behind polling is for the CPU to periodically read a status register until the register
contents indicate the need for data to be
transferred. Only one register needs to be
DATA
NRZ
\
NRZI
\
/
I
\
\
FM1
FMO
MANCHESTER
Figure 6. Data Encoding MethQds
272
2016-002
Functional
Doscription
(Continued)
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
.
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the Z-SCC and
external to the Z-SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the lEO output of the Z-SCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
. interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transrnitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of
three ways:
Interrupts. The Z-SCC interrupt scheme conforms to the Z-Bus specification. When a:
Z-SCC responds to' an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt
vector may be placed on the AID bus. This
vector is written in WR2 and may be read in
RR2A or RR2B (Figures 10 and 11).
To speed interrupt response time, the Z-SCC
. can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
Z-SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: ,Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
e Interrupt on First Receive Character or
given interrupt source, then that source can
Special Receive Condition.
request interrupts. The exception is when the
e Interrupt on All Receive Characters or
MIE (Master Interrupt Enable) bit in WR9 is
Special Receive Condition.
reset and no interrupts may be requested. The
e Interrupt on Special Receive Condition
IE bits are write only.
Only.
The other two bits are related to the Z-Bus
interrupt priority chain (Figure 7). As a Z-Bus
Interrupt on First Character or Special Conperipheral, the Z-SCC may request an '
dition and Interrupt on SpeCial Condition Only
interrupt only when no higher priority device
are typically used with the Block Transfer
is requesting one, e.g., when IEI is High. If
mode. A Special Receive Condition is one of
the device in question requests an interrupt, it , the following: receiver overrun, framing error
pulls down INT. The CPU then responds with
in Asynchronous mode, end-of-frame in SDLC
INTACK, and the interrupting device places
mode and, optionally, a parity error. The
the vector on the AID bus.
Special Receive Condition interrupt is different
In the Z-SCC, the IP bit signals a need for
from an ordinary receive character available
interrupt servicing. When an IP bit is 1 and
interrupt only in the status placed in the vector
the IEI input is High, the INT output is pulled
during the Interrupt Acknowledge cycle. In
Low, requesting an interrupt. In the Z-SCC, if
Interrupt on First Receive Character, an interthe IE bit is not set by enabling interrupts,
rupt can occur from Special Receive Condithen the IP for that source can never be set.
tions any time after the first receive character
The If> is set two or three AS cycles after the
interrupt.
interrupt condition occurs. Two or three AS
The main function of the External/Status
rising edges are required from the time an ininterrupt is to monitor the signal transitions of
terrupt condition occurs until INT is activated.
the CTS, DCD, and SYNC pins; however, an
The IP bits are readable in RR3A.
External/Status interrupt is also caused by a
The IUS bits signal that an interrupt request
Transmit Under run condition, or a zero count
Z·BUG
PERIPHERAL
lEI ADo-AD7
iNf INTACK lEO
Z·DUS
PERIPHERAL
lEI ADo-AD7
iNf INTACK lEO
Z·BUS
PIZRIPHERAL
lEI ADo-AD7
iNf INTACK
+5V
,+5V
ADO-AD7\,______________________________________________
~
INT.-------------~~--------------~~~--------------~~~
INTACK~--------------~----------------~~----------------~
Figure 7. Z-BUS Interrupt Schedule
2016-003
273
Functional
Description
(Continued)
in the baud rate generator, or by the detection
of a Break (Asynchronous mode), Abort (SDLC
mode) or EOP (SDLC Loop mode) sequence in
the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing
the Z-SCC to interrupt when the Abort or EOP
sequence is detected or te~minated. This
feature facilitates the proper termination of the
current message, correct initialization of the
next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature, allows
secondary stations to recognize the wishes of
the primary station to regain control of the
loop during a poll sequence.
CPU/DMA Block Transfer. The Z-SCG provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Transfer mode uses the
WAIT/REQUEST output in conjunction with the
Wait/Request bits in WRI. The WAIT/
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the Z-SCC REQUEST
output indicates that the Z-SCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the Z-SCC is not
ready to transfer data, thereby requesting that
the CPU extend the I/O cycle. The DTRI
REQUEST line allows full-duplex operation
under DMA control.
Architecture
The Z-SCC internal structure includes two
full-duplex channels, two baud rate
generators, internal control and interrupt
logic, and a bus interface to the Zilog Z-Bus.
Associated with each channel are a number of
read and write registers for mode control and
status information, as well as logic necessary to
interface to modems or other external devices
(Figure 8).
The logic for both channels provides
-I
-I
SERIAL DATA
CHANNEL CLOCKS
-SYNC
=WA"""IT....
/R=EQ"'U""ES=T
INTERNAL
CONTROL
LOGIC
_
}
MODEM, DMA, OR
OTHER CONTROLS
ADDRESS/~
DATA~
CPU
BUS I/O
CONTROL
INTERNAL BUS
WL--__
-}
...I
INTERRUPT
CONTROL
LINES
INTERRUPT
CONTROL
LOGIC
MODEM, DMA, OR •
OTHER CONTROLS
I
SERIAL DATA
-I
tt t
CHANNEL CLOCKS
SYNC
WAIT/REQUEST
+5 V GND PCLK
Figure 8. Block Diagram of Z-SCC Architecture
274
2016-040
->
0 ...
10
o
a;
o n
ae=
S" S'
6
~
s::: n
CD -
o..~
-;
CPU 1/0
.------.....,,j
BR GENERATOR
INPUT
BR GE.NERATOR
OUTPUT
HUNT MODE (BISYNC)
,----------,
TRANSMIT
CLOCK
RID
DPLL
SOLc-eRC
DPLL OUTPUT
•
I
I
BR GENERATOR OUTPUT
CRC RESULT
~.
RECEIVE CLOCK
DPLL OUTPUT
TRIC
CLOCK
MUX
RTxC
TRANSMIT CLOCK
DPLL CLOCK
BR GENERATOR CLOCK
SYNC
(OSCILLATOR)
I\)
-....J
()l
Figuro 9. Data Path
OOa-20£GOE
TO OTHER CHANNEL
I
Architecture
(Continued)
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two sync
character (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that d6cermines the
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write-only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRl5 - Write Registers 0 through 15.
RRO-RR3, RRlO, RR12, RR13, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The Z-SCC contains
only one WR2 and WR9, but they can be
accessed by either channel. All other registers
are paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Figure 9 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive'shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths (data or CRC)
depending on the selected mode (the character
length in Asynchronous modes also determines
the data path).
The transmitter has an 8-bit Transmit Data
Programming
276
The Z-SCC contains 13 write registers in
each channel that are programmed by the
'system separately to configure the functional
personality of the channels. All of the registers
in the Z-SCC are directly addressable. How
the Z-SCC decodes the address placed on the
address/data bus at the beginning of a Read or
W rite cycle is controlled by a command issued
'in WROB. In the Shift Right mode the channel
select AlB is taken from ADo and the state of
ADs is ignored. In the Shift Left mode A/B is
taken from Aps and the state of ADo is
buffer register loaded from the internal data
bus and a 20-bit Transmit Shift register that
can be loaded either from the synchronous
character registers or from the Transmit Data
register. Depending on the operational mode,
outgoing data is routed through one of four
main paths before it is transmitted from the
Transmit Data output (TxD)
Read Register Functions
RRO
Transmit/Receive buffer status and External status
RRI
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only) ,
Unmodified interrupt vector (Channel A only)
RR3
Interrupt Pending bits (Channel A only)
RR8
Receive buffer
RRIO
Miscellaneous status
RR12
Lower byte of baud rate generator time constant
RR13
Upper byte of baud rate generator time constant
RRlS
External/Status interrupt information
Write Register Functions
WRO
CRC initialize, initialization commands for the
various modes, shift right/shift left command
WRI
Transmit/Receive interrupt and data transfer mode
definition
WR2
Interrupt vector (accessed through either channel)
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and
modes
WRS
Transmit parameters and controls
WR6
Sync characters or SOLC address field
WR7
Sync character or SOLC flag
WR8
Transmit buffer
WR9
Master interrupt control and reset (accessed
through either channel)
WRIO
Miscellaneous transmitter/receiver control bits
WRll
Clock mode control
WR12
Lower byte of baud rate generator time constant
WR13
Upper byte ~f baud rate generator time constant
WR14 . Miscellaneous control bits
WRlS
External/Status interrupt control
Table I. Read and Write Register Functions
ignored. AD7 and AD6 are always ignored as
address bits and the register address itself
occupies AD4-ADl.
The system program first issues a series of
commands to initialize the basic mode of
operation. This is followed by other commands
to qualify conditions within the selected mode.
For example, the Asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first.
Then the Interrupt mode would be set, and
finally, receiver or transmitter enable.
Programming Read Registers. The Z-SCC contains eight
(Continued)
read registers (actually nine, counting the
receive buffer [RR8]) in each channel. Four of
these may be read to obtain status information
(RRO, RRl, RRlO, and RR15). Two registers
(RR12 and RR13) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the
Read Register 0
Interrupt Pending (IP) bits (Channel A).
Figure 10 shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e:g.,
when the interrupt vector indicates a Special
. Receive Condition interrupt, all the appropriate error bits can be read from a Single
register (RRl).,
Read Register 10
I ~ ~~~~:.~::::"u'"
~
~SYNC/HUNT
CTS
Tx UNDERRUN/EOM
L...-_ _ _ _ _ _ _ _ _ _ _
' - - - - - - - - BREAK/ABORT
Read Register 1
ONE CLOCK MISSING
Read Register 12
I0, I0,1 Os I0.1 0,1 0 10, IDo I
2
~~
I ~ :~~I:~:TCODE.2
LS
RESIDUE CODE 1
RESIDUE CODE 0
LOWER BYTE OF
TIME CONSTANT
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
' - - - - - - - - TC7
' - - - - - - - - - END OF FRAME (SOLC)
Read Register 2
Read Register 13
10, I0,1 Os 10.10,1 0 10, IDo I
2
INTERRUPT VECTOR'
'-------------V7
~:~:~
UPPER BYTE OF
TIME CONSTANT
' - - - - - - - - TC'5
'MODIFIED IN B CHANNEL
Read Register 3
Read Register 15
I~I~I~I~I~I~I~I~I
I ~ ~:::::~:~::~S.TATIP'
~~
L
CHANNEL B Rx IP'
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'
o
'--------------- 0
~~'O'O"""
~~
CDCDIE
SYNC/HUNT IE
CTS IE
Tx UNDERRUN/EOM IE
' - - - - - - - - BREAK/ABORT IE
'ALWAYS 0 IN B CHANNEL
Figure 10. Read Register Bit Functions
2016-005
277
Programming Write Registers. The Z-SCC contains 13 write
(Continued)
registers (14 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels, In
addition, there are two registers (WR2 and
Write Register 0
Write Register 3
0
1
NULL CODE
o
0
NULL CODE
1
NULL CODE
1
0
SELECT SHIFT LEFT MODE'
1
1
. :ELECT SHIFT RIGHT MODE'
0
o
o
o
0
1
NULL CODE
1
0
RESET EXT/STATUS INTERRUPTS
1
1
SEND ABORT
1
0
0
ENABLE INT ON NEXT Rx CHARACTER
1
0
1
1
1
0
Rx 5 BITS/CHARACTER
o
1
Rx 7 BITS/CHARACTER
1
0
Rx 6 BITS/CHARACTER
1
1
Rx 8 BITS/CHARACTER
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES
RESET Tx INT PENDING
Write Register 4
ERROR RESET
1
RESET HIGHEST IUS
o
o
1
RESET Rx CRC CHECKER
1
0
RESET Tx CRC GENERATOR
1
1
RESET Tx UNDERRUN/EOM LATCH
0
~~
L-.: Rx ENABLE
0
o
o
1
WR9) shared by the two channels that may be
accessed through either of them, WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits, Figure
11 shows the format of each write register,
I0,1 0: I0,1 0.1 OJ ID,I 0, IDo I
NULL CODE
~
o
o
'B CHANNEL ONLY
Write Register 1
I~I~I~I~I~I~I~I~I
I IL L "" '"",,'"
I L PARITY ENABLE
L PARITY EVEN/ODD
0
SYNC MODES ENABLE
1
1 S70P BIT/CHARACTER
1
0
1 '12 STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
o
o
1
16 BIT SYNC CHARACTER
o
SDLC MODE (01111110 FLAG)
1
1
EXTERNAL SYNC MODE
0
8 BIT SYNC CHARACTER
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
o
0
Rx INT DISABLE
o
1
Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION
1
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
1
o
o
0
X 1 CLOCK MODE
1
X16 CLOCK MODE
1
0
X32 CLOCK MODE
1
1
X64 CLOCK MODE
Rx INT ON SPECIAL CONDITION ONLY
Write Register 5
' - - - - - - WAIT/DMA REQUEST ON RECEIVE/TRANSMIT
1-------1---------
WAIT/DMA REQUEST FUNCTION
WAIT/DMA REQUEST ENABLE
,~I
L-.:
Write Register 2
L
I0,1 0.1 0,1 0.1 0,1 0,1 0, IDo I
SOLC/CRC.16
Tx ENABLE
mi:
1---------
:;SCRC ENABLE
SEND BREAK
INTERRUPT VECTOR
o
0
Tx 5 BITS (OR LESS)/CHARACTER
o
1
Tx 7 BITS/CHARACTER
1
0
Tx 6 BITS/CHARACTER
1
1
Tx 8 BITS/CHARACTER
' - - - - - - - - DTR
V7
Write Register 6
I0,1 0 10,1 0.1 OJ I0,1 0, IDo I
6
IFP)~~
SYN C7
SYNC,
SYNC7
SYNC3
ADR7
ADR7
SYNCs
SYNCo
SYNCs
SYNC2
ADRa
ADRs
SYNC,
SYNCs
SYNCs
SYNC,
ADRs
ADRs
SYNC,
SYNC,
SYNC,
SYNCo
ADR,
ADR,
SYNC3
SYNC3
SYNC3
1
ADR3
SYNC2
SYNC2
SYNC2
1
ADR2
SYNC,
SYNC,
SYNC,
1
ADR,
SYNCo
SYNCo
SYNCo
1
ADRo
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC (ADDRESS RANGE)
Figure 11. Write Register Bit Functions
278
2016-006
Programming
(Continued)
Write Register 1
SYNC,
SYNCs
SYNC1S
S YNC 11
o
SYNCS
SYNC4
SYNC14
SYNC 10
1
SYNCs
SYNC3
SYNC13
SYNC9
1
SYNC4
SYNC2
SYNC12
SYNCa
1
SYNC3
SYNC1
SYNC11
SYNC,
1
SYNC2
SYNCo
SYNC10
SYNCs
x
SYNC9
SYNCs
1
1
X
SYNCa
SYNC4
o
MONOSYNC, a BITS
MONOSYNC, 6 BITS
[lISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
Write Register 12
Write Register 9
I0,1 0,1 0 10.1 0 10,1 0, IDo I
5
3
~~~
~~
L
o
o
DLC
MIE
LOWER BYTE OF
TIME CONSTANT
:TATUS HIGHISTATUS LOW
IN
eo
ow
1..-_ _ _ _ _ _ _ _ TC,
0
NO RESET
1
CHANNEL RESET B
1
0
CHANNEL RESET A
C
1
1
FORCE HARDWARE RESET
N
•
fAD
n
n
Write Register 13
Write Register 10
I0 10,1 0 10.1 0 10,1 0, IDo I
I ~ 6 BIT/a BIT SYNC
7
5
3
~
UPPER BYTE OF
TIME CONSTANT
LLOOPMODE
o
0
ABORT/FLAG ON UNDERRUN
MARK/FLAG IDLE
GO ACTIVE ON POLL
1..-_ _ _ _ _ _ _ TC1S
NRZ
o
1
NRZI
1
0
FM1 (TRANSITION
=
1
1
FMO (TRANSITION
= 0)
1)
Write Register 14
1..-_ _ _ _ _ _ _ CRC PRESET
110
~~
L DR GENERATOR ENABLE
L. BR GENERATOR SOURCE
Write Register 11
I 0 7 D,I D51 D.I D31 D,I D,
1
IDol
~
o
0
TRxC OUT = XTAL OUTPUT
o
1
TRxC OUT
1
0
1
1
DTR/REQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK
0
0
0
NULL COMMAND
0
0
1
ENTER SEARCH MODE
TRxC OUT = BR GENERATOR OUTPUT
0
1
0
RESET MISSING CLOCK
TRxC OUT = DPLL OUTPUT
0
1
1
DISABLE DPLL
TRxC 011
1
0
0
SET SOURCE
1
0
1
SET SOURCE
TRANSMIT CLOCK = RTxC PIN
1
1
0
SET FM MODE
TRANSMIT CLOCK = TRxC PIN
1
1
1
SET NRZI MODE
= TRANSMIT CLOCK
o
0
o
1
1
0
TRANSMIT CLOCK = BR GENERATOR OUTPUT
1
1
TRANSMIT CLOCK = DPLL OUTPUT
= BR GENERATOR
= RTxC
Write Register 15
RECEIVE CLOCK = RTxC PIN
o
0
o
1
RECEIVE CLOCK
1
0
RECEIVE CLOCK = BR GENERATOR OUTPUT
1
1
RECEIVE CLOCK = DPLL OUTPUT
I~I~I~I~I~I~I~I~I
= TRxC PIN
~--------RTxCXTAUNOXTAL
~~;;:::::'
Tx UNDERRUN/EOM IE
1..-_ _ _ _ _ _ _ _ BREAK/ABORT IE
Figure 11. Write Rogister Bit FUDctions (Continued)
2016-006
279
Timing
The Z-SCC generates internal control signals
from AS and DS that are related to PCLK.
Since PCLK has no phase relationship with
AS and DS, the circuitry generating these
internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the Z-SCC. The recovery
time required for proper operation is specified
from the rising edge of DS in the first transaction involving the Z-SCC to the falling edge of
DS in the second transaction involving the
Z-SCC. This time must be at least 6 PCLK
cycles plus 200 ns.
Read Cycle Timing. Figure 12 illustrates read
cycle timing. The address on ADo-AD7 and·
the state of CSo and INTACK are latched by
the rising edge of AS. R/W must be High to
indicate a Read cycle. CSI must also be High
for the Read cycle to occur. The data bus
drivers in the Z-SCC are then enabled while
DS is Low.
I
INTACK
ADO-AD 7
--/
X
ADDRESS
R1W
\_--------~----------)
(
------X
7
7
c
DATA VALID
\~
____
}--
~r-
Flguro 12. Road Cyclo Timing
Write Cycle Timing. Figure 13 illustrates
Write cycle timing. The address on ADo-AD7
and the state of CSo and INTACK are latched
by the rising edge of AS. R!W must be Low to
CSo
ADO-AD7
,
\
I
7
\
X
ADDRESS
indicate a Write cycle. CSI must be High for
the Write cycle to occur. DS Low strobes the
data into the Z-SCC.
,
XJ(~______X=
DATA
...&r_
C
\~ _ _ _ _ _ _ _ _ _ _ _
RIW _ _ _ _ _ _ _
7
cs1 _ _ _ _ _ _
\_______....Jr-'
Figure 13. Write Cycle Timing
Interrupt Acknowledge Cycle Timing.
Figure 14 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD 7 and
the state of CSo and INTACK are latched by
280
the rising edge of AS. However, if INTACK is
Low, the address and CSo are ignored. The
state of the R/W and CSI are also ignored for
the duration of the Interrupt Acknowledge
2016-007, 008
Timing
(Continued)
intended for the Z-SCC. In this case, the
Z-SCC may be programmed to respond to DS
Low by placing its interrupt vector on
ADo-AD7. It then sets the appropriate
Interrupt- Under-Service latch internally.
::ycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
lEI/lEO daisy chains settle. If there is an interrupt pending in the Z-SCC and lEI is High
when DS falls, the Acknowledge cycle was
CSo
INTACK
ADo-AD7
X
(IGNORED)
.I'
~
X
X ;
L ~,
(IGNORED)
)
CJ<
I)
>-
VECTOR
'I
os
Figuro 14. Intorrupt Aclcnowlodgo Cyclo Timing
Absolute
Maximum
Ratings
Standard
Test
Conditions
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150 °C
The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
+4.75 V ::5 Vee ::5 +5.25 V
fJ GND = 0 V
[J TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
[J
+5V
2.1K
,
+5V
2'2K
FROM OUTPUT
UNDER TEST
~r
50pF
Figure 15. Standard Test Load
DC
Characteristics
Symbol
VIH
VIL
VO H
VOL
IlL
IOL
Icc
Figure 16. Open-Drain Test Load
Parameter
Min
Max
Unit
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
2.0
-0.3
2.4
Vee+ 0 .3
0.8
V
V
V
V
p.A
p.A
rnA
0.4
± 10.0
± 10.0
250
Condition
IOH =
1oL =
0.4 =::;
0.4 =::;
-250 p.A
+2.0 rnA
VIN =::; + 2.4V
Your =::; +2.4V
Vee = 5 V ± 5% unless otherwise specified, over speCified temperature range.
Capacitance
Symbol
C IN
COUT
Cvo
f
20 \6-009
8085-006, 00 I
=
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
U nrneasured Pins
Returned to Ground
I MHz, over speCified temperature range.
281
Read and
Write
Timing
CSo
RlW
-++-_.1
READ _ _ _ _
RIW
WRITE
----~H_---_+_-+----------__+---"Ij_----------
ADo-AD7
WRITE _ _ _
1'--+-!---1
ADo-AD7
READ _ _- - '
1'--Hf----"rr
WIREQ
WAIT
WIREQ
-+-_____-+___--'
REQUEST _ _ _ _ _
DTRlREQ
-+-______________________
REQUEST _ _ _ _ _
~---~~~----~~-------------------------~
4 MHz
No.
Symbol
Parameter
Min
1
TwAS
AS Low Width
70
2
TdDS(AS)
DS t to AS • Delay
50
3
TsCSO(AS)
CSo to AS t Setup Time
a
4
ThCSO(AS)
CSo to AS t Hold Time
60
5 -TsCSl(DS) --CS1 to DS l Setup T i m e - - - - - - - - - - 100
6
ThCSl(DS)
CS] to iSS tJiold Time
55
TsIA(AS)
INTACK to AS t Setup Time
7
a
8
ThIA(AS)
INTACK to AS t Hold Time
250
9
TsRWR(DS)
RiW (Read) to DS • Setup Time
100
lO-ThRW(DS)--RiWto DS t Hold Time - - - - - - - - - - 55
11
TsRWW(DS)
RiW (Write) to DS l Setup Time
a
12
TdAS(DS)
AS t to DS • Delay
60
13
TwDSl
DS Low.Width
390
14
TrC
Valid Access Recovery Time
6TcPC
+200
15 - TsA(AS)
Address to AS t Setup Time - - - - - - - - - 30
50'
16
ThA(AS)
Address to AS t Hold Time
17
TsDW(DS)
Write Data to DS , Setup Time
30
18
ThDW(DS)
Write Data to DS t Hold Time
30
19
TdDS(DA)
DS , to Data Active Delay
a
20-TdDSr(DR)--DS t to Read Data Not Valid D e l a y - - - - - - - a
21
TdDSf(DR)
DS , to Read Data Valid Delay
22
TdAS(DR)
AS t to Read Data Valid Delay
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
transactions.
282
Max
6 MHz
Min
Max
Notes*t·
50
25
a
1
40
1
80 ------,,....----140
1
a
250
80
40
a
40
250
6TcPC
2
+ 130
10 - - - , . . . . - - - - 1 30
1
20
20
a
a
250
520
180
335
2. Parameter applies only between transactions involving the sec.
'Timings are preliminary and subject to change.
,
tUnits in nanoseconds (ns).
2016-010
y
Interrupt
Acknowledge
Timing
----------------~
ADo-AD7 ----------------------I---------------++--~
lEI
lEO
t-----{36}---l~
}---------------
Reset
Timing
Cycle
Timing
No.
PCLf(
Symbol
Parameter
Min
4MHz
Max
6 MHz
Min
Max
45
23
TdDS(DRz)
DS t to Read Data Float Delay
70
24
TdA(DR)
Address Required Valid to Read Data Valid Delay
570
420
240
200
25
TdDS(W)
DS l to Wait Valid Delay
200
26
TdDSf(REQ)
DS l to W/REQ Not Valid Delay
240
5TcPC
27-TdDSr(REQ)-DS t to DTRlREQ Not Valid D e l a y - - - - - - - - - 5TcPC
+300
+250
28
TdAS(INT)
AS t to INT Valid Delay
500
500
29
TdAS(DSA)
AS t to DS l (Acknowledge) Delay
250
250
250
DS (Acknowledge) Low Width
390
30
TwDSA
180
31
TdDSA(DR)
DS l (Acknowledge) to Read Data Valid Delay
250
100
32 - TsIEI(DSA) - - lEI to DSl (Acknowledge) Setup Time - - - - - 120
33
ThIEI(DSA)
lEI to DS t (Acknowledge) Hold Time
0
0
34
TdIEI(lEO)
lEI to lEO Delay
120
100
250
35
TdAS(lEO)
AS t to lEO Delay
250
36
TdDSA(INT)
DS·l (Acknowledge) to INT Inactive Delay
500
500
15
37 - TdDS(ASQ) - - DS t to AS l Delay for No Reset - - - - - - - - 30
30
38
TdASQ(DS)
AS t to DS l Delay for No Reset
30
250
39
TwRES
AS and DS Coincident Low for Reset
250
105
2000
70
1000
40
TwPCl
PCLK Low Width
70
1000
41
TwPCh
PCLK High Width
105
2000
42-TcPC
PCLK Cycle Time - - - - - - - - - - - - 250 -4000--165- 2000
15
20
43
TrPC
PCLK Rise Time
20
10
44
TfPC
PCLK Fall Time
NOTES:
3. Float delay is defined as the time required for a ±0.5 V change
in the output with a maximum dc load and minimum ac load.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system dependent. For any Z-SCC in the daisy
chain, TdAS(DSA) must be greater than the sum of TdAS(IEO)
for the highest priority device in the daisy chain, TsIEI(DSA)
for the Z-SCC, and TdIEIf(IEO) for each device separating them
in the daisy chain.
2016-011, 012, 013
Notes*t
3
4
4
5
6
4
7
6. Parameter applies only to a Z-SCC pulling INT Low at the
beginning of the Interrupt Acknowledge transaction.
7. Internal circuitry allo;""s for the reset provided by the Z8 to be
recognized as a reset by the Z-SCC .
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "I" and 0.8 V for a logic "0".
t Units in nanoseconds (ns).
283
General
Timing
PCLK
WIRE::Q
REQUEST
+-____________________________--'
WIREQ
WAIT ________________________
RTxC, TRxC
RECEIVE ____________..;...____~ I
RxD
SYNC
EXTERNAL __________J~~__________+_------------~'~------------------------------------------
TRxC,RTxC
TRANSMIT
TxD
---CI-:
___~:~. ,. .--" _______~ '______
___
'~
___®_'3~_-_-__
TRxC ___________________________~
OUTPUT
~--------------------------------------------------____________________________________________________
~
\----D7Jg
TRXC-----\~_ _~~-----\~-----'rm,DCD
SYNC
INPUT
~
I
~
.
/'--------------------------------
- - - , ~r.:==®==J .
-----------------
284
22·
F=®===i
2016-014
6 MHz
Min
Max
Parameter
1
TdPC(REQ)
PCLK l to WIREQ Valid
250
250
2
TdPC(W)
PCLK l to Wait Inactive Delay
350
350
3
TsRXC(PC)
RxC t to PCLK t Setup Time (PCLK
4
TsRXD(RXCr)
RxD to RxC t Setup Time (Xl Mode)
5-ThRXD(RXCr)-RxD to RxC t Hold Time (Xl Mode)
6
TsRXD(RXCf)
RxD to RxC l Setup Time (Xl Mode)
Min
4MHz
Max
Symbol
No.
4 case only)
dO
TwPCL
70
TwPCL
Notes*t
1,4
0
0
150
150
0
0
I,S
I-
7
ThRXD(RXCf)
RxD to RxC l Hold Time (Xl Mode)
150
150
1,5
8
TsSY(RXC)
SYNC to RxC t Setup Time
-200
-200
1
9
ThSY(RXC)
SYNC to RxC t Hold Time
3TcPC
+200
3TcPC
+200
10 -TsTXC(PC)--TxC l to PCLK t Setup Time
0
2,4-
0
11
TdTXCf(TXD)
TxC I to TxD Delay (Xl Mode)
300
300
2
12
TdTXCr(TXD)
TxC t to TxD Delay (Xl Mode)
300
300
2,5
13
TdTXD(TRX)
TxD to TRxC Delay (Send Clock Echo)
200
200
14
TwRTXh
RTxC High Width
180
180
RTxC Low Width
180
180
15-TwRTXl
16
TcRTX
RTxC Cycle Time
400
17
TcRTXX
Crystal Oscillator Period
250
18
TwTRXh
19
TwTRXl
20-TcTRX
250.
Oft
6
66
400
1000
1000
3
TRxC High Width
180
180
6
TRxC Low Width
180
180
TRxC Cycle Time
400
400
6
6-
200
21
TwEXT
DCD or CTS Pulse Width
200
22
TwSY
SYNC Pulse Width
200
NOTES:
1. RxC is RTxC or TRxC, whichever is supplying the receive
clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit
clock.
3. Both RTxC and SYNC have 30 pf capacitors to the ground
connected to them.
4. Parameter applies only if the data rate is one-fourth the PCLK
rate. In
other cases, no phase relationship between RxC and
PCLK or TxC and PCLK is required.
lSI
5. Parameter applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and
baud rate generator timing requirements are ideniical to chip
PCLK requirements.
* Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
all
285
eW
0
~
~
8
System
Timing
RfiC, TiiiC
RECEIVE
W/REQ
REQUEST
W/REQ
WAIT
SYNC
OUTPUT
RTJlC, TRJlC
TRANSMIT
W/REQ
REQUEST
W/REQ
WAIT,
DTRlREQ
REQUEST
CTS, DCD
V
------------~~~~-------------------------
SYNC--------------------~----~J(~------------------------------------INPUT
----------------~--~~~~9----~--------------------
INT--------------~~-----------\
~--____(IO)_---'i~
-------,------------------------------------------------------------------------------------4 MHz
No.
Symbol
Parameter
TdRXC(REQ)
RxC t to VI/REQ Valid Delay
TdRXC(W)
RxC t to Wait Inactive Delay
Min
Max
12
8
12
8
4
TdRXC(SY)
RxC t to SYNC Valid Delay
7
3
TdRXC(INT)
12
4
RxC t INT Valid Delay
8
+2
+3
5 -TdTXC(REQ) -TxC I to WIREQ Valid Delay - - - - - - - - 5 - - 8
8
6
TdTXC(W)
TxC I to Wait Inactive Delay
5
4
TxCI tb DTR/REQ Valid Delay
7
7
TdTXC(DRQ)
8
TdTXC(INT)
TxC I to INT Valid Delay
4
6
+2
+3
3
TdSY(INT)
SYNC Transition to INT Valid Delay
2
9
TdEXT(INT)
2
3
10
DCD or CTS Transition to INT Valid Delay
2
NOTES:
1. Open·drain output, measured with open-drain test load.
2. RxC is RTxC or TRxC, whichever is supplying the receive
clock.
3. TxC is TRxC or RTxC, whichever Is supplying the transmit
clock.
286
6 MHz
Min
Max
8
12
8
12
4
7
8
12
+2
+3
5--8
5
4
4
+2
2
2
8
7
6
+3
3
3
Notes*
2,4
1,2,4
2,4
1,2,4
5
3,41,3,4
3,4
1,3,4
5
1,5
1,5
4. Units equal to TcPC.
5. Units equal to AS.
·'Timings are preliminary and subject to change.
2016-015
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Temp
Speed
CE
6.0 MHz
Description
Z8030
CE
4.0 MHz
Z-SCC (40-pin)
Z8030A
Z8030
CM
4.0 MHz
Same as above
Z8030A
CM
6.0 MHz
Same as above
Z8030
CMB
4.0 MHz
Same as above
Z8030A
CMB
6.0 MHz
Same as above
Z8030
CS
4.0 MHz
Same as above
Z8030A
CS
6.0 MHz
Same as above
Z8030
DE
4.0 MHz
Same as above
Z8030A
DE
6.0 MHz
Same as above
Z8030
DS
4.0 MHz
Same as above
Z8030A
DS
6.0 MHz
Same· as above
Z8030
PE
4.0 MHz
Same as above
Z8030A
PE
6.0 MHz
Same as above
Z8030
PS
4.0 MHz
Same as above
Z8030A
PS
6.0 MHz
Same as above
Z-SCC (40-pin)
. NOTES: C = Ceramic, D = Cerciip, P = Plastic; E = -40°C to +85°C, M = -55°C to 125°C, MB = -55°C to 125°C with MIL-STD-883
with Class B processing, S = O°C to.+70°C.
00·2016-02
287
Z8Q31 Z8000™ Z-ASec
Asynchronous Serial
Communications Controller
Product
Zilo
Specification
September 1983
Features
Two independent, 0 to 1M biVsecond, fullduplex channels, each with a separate
crystal oscillator and baud rate generator.
iii Programmable for NRZ, NRZI, or FM data
encoding.
II Asynchronous communications with five to
Ell
eight bits per character and one, one and
one-half, or two stop bits per character; programmable clock factor; break·detection
and generation; parity, overrun, and framing error detection.
m Local Loopback and Auto Echo modes.
General
Description
The 28031 Z-ASCC Asynchronous Serial
Communications Controller is a dual-channel
data communications peripheral designed for
use with the Zilog Z-BUS. The Z-ASCC functions as a serial-to-parallel, parallel-to-serial
converter/controller. The device contains a
variety of new, sophisticated internal functions
including on-chip baud rate generators and
crystal oscillators that dramatically reduce the
need for external logic.
The Z-ASCC has facilities for modem con-
_
7
_
AD6
TxDA
AD
RxDA
ADs
TRxCA
RTxCA
ADDRESS'
DATA BUS
} SERIAL
DATA
} CHANNEL
CLOCKS
·CH·A
AD,
ADo
BUS { _ As
TIMING
-
A::::::: {- ::
cso
INTERRUPT
troIs in both channels. In applications where.
these controls are not needed, the modem controls can be used for general-purpose I/O.
The Z-BUS daisy-chain interrupt hierarchy
is also supported-as is standard for Zilog
peripheral components.
The Z8031 Z-ASCC is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.
I
iNr
INTACK
lEI
lEO
Z0031
Z·ASCC
CHANNEL
CONTROLS
FOR MODEM,
DMA,OR
OTHER
AD,
ADo
AD3
AD2
ADs
AD4
AD7
AD6
iNr
os
lEO
As
lEI
RIW
INTACK
CSo
+5V
CS,
W/REQA
} SERIAL
DATA
RIA
RTxCA
} CHANNEL
CLOCKS
RxDA
TRxCA
CHAtlNEL
CONTROLS
FOR MODEM,
DMA,OR
OTHER
CH·U
TxDA
DTR/REQA
GND
W/REQB
RiB
RTxCB
RxDB
TRxCB
TxDB
RTSA
DTR/REQB
CTSA
RTSB
DCDA
CTSB
PCLK
DCDB
t t t
+5 V GND PCLK
Figure 1. Pin Functions
2245-001, 002
Figure 2. Pin Assignments
289
Pin
Description
The following section describes the pin
functions of the Z-ASCC.Figures 1 and 2
detail the respective pin functions and pin
assignments.
ADo-AD7' Address/Data Bus (bidirectional,
active High, 3-state). These multiplexed lines
carry register addresses to the Z-ASCC as well
as data or control information to and from
the Z-ASCC.
AS. Address Strobe (input, active Low).
Addresses on ADo-AD7 are latched by the rising edge of this signal.
CSo. Chip Select 0 (input, active Low). This
signal is latched concurrently with the
addresses on ADo-AD7 and must be active for
the intended bus transaction to occur.
CSI. Chip Select 1 (input, active High). This
second select signal must also be active before
the intended bus transaction can occur. CSI
must remain active throughout the transaction.
CTSA, CTSB. Clear to Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables their
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The Z-ASCC detects pulses on these inputs
and can interrupt the CPU on both logic level
transitions.
DCDA, DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger, buffered to accommodate slow
rise-time signals. The Z-ASCC detects pulses
on these pins and can interrupt the CPU on
both logic level transitions.
DS. Data Strobe (input, active Low). This
signal provides timing for the transfer of data
into and out of the Z-ASCC. If AS and DS
coincide, this is interpreted as a reset.
DTR/REQA, DTR/REQB. Data. Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
IEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). IEO is High only if IEI is High and the
CPU is not servicing a Z-ASCC interrupt or
the Z-ASCC is not requesting an interrupt
(Interrupt Acknowledge cycle only). IEO is
290
connected to the next lower priority device's
IEI input and thus inhibits interrupts from
lower priority devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
Z-ASCC requests an interrupt. '
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
Z-ASCC interrupt daisy chain settles. When
DS becomes active, the Z-ASCC places an
interrupt vector on the data bus (if IEI is
, High). INTACK is latched by the rising edge
of AS.
PCLK. Clock (input). This is the master
ZcASCC clock used to synchronize internal
signals. PCLK is not required to have any
phase relationship with the master system
clock, !=llthough the frequency of this clock
must be at least 90% of the CPU clock frequencyfor a Z8000. PCLK is a TTL level
signal.
RxDA, RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
RIA, RIB. Ring Indicator (inputs, active Low).
These pins can act either as inputs or as part
of the crystal oscillator circuit.
In normal operation (crystal oscillator option
not selected), these pins are inputs similar to
CTS and DCD. In this mode, transitions on
these lines affect the state of the Ring Indicator
status bits in Read Register 0 (Figure 8) but
have no other function.
RTxCA, RTxCB. Receive/Transmit Clocks
-(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock of the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective HI pins as a crystal oscillator. The receive
clock jila y be 1, 16, 32, or 64 times the data
rate in Asynchronous modes.
RTSA, RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 9) is set, the
RTS Signal goes Low~ When the RTS bit is
reset and Auto Enable is on, the signal goes
High after the transmitter is empty. With Auto
Enable off, the RTS pin strictly follows the state
of the RTS b~t. Both pins can be used as
general-purpose outputs.
R/W. Read/Write (input). This signal specifies
whether the operation to be performed is a
read or a write.
TxDA, TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.
Pin
Description
(Continued)
TRxCA~ TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the output of the Digital Phase-Locked
Loop, the crystal oscillator, the baud rate
. generator, or the transmit clock in the output
mode.
Functional
Description
The functional capabilities of the Z-ASCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols;
as a Z8000 peripheral, it interacts with the
CPU and other peripheral circuits and is part
of the system interrupt structure.
handle data at a rate of 1116, 1132, or 1164 of
the clock rate supplied to the receive and
transmit clock inputs.
Data Communications Capabilities. The
Z-ASCC provides two independent full-duplex
channels programmable for use in any common Asynchronous data communication protocol. Figure 3 and the following description
briefly detail this protocol.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
mechanism that checks the signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDBin
Figure 1). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors, and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored iIiterrupts allow fast servicing of error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The Z-ASCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
STrT
~MA-R-KI-NG-L-IN--E---"II
DATA
W/REQA. W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to
synchronize the CPU to the Z-ASCC data rate ..
The reset state is Wait.
Baud Rate Generator. Each channel in the
Z-ASCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may b~
echoed out via the TRxC pin.
The following formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
.
time constant
PCLK
= 2 (clock factor)
(baud) - 2
Digital Phase-Locked Loop. The Z-ASCC
contains a Digital Phase-Locked Loop (DPLL)
to recover clock information from a data
stream with NRZI or FM encoding. The DPLL is
driven by a clock that is nominally 32 (NRZI)
or 16 (FM) times the data rate. The DPLL uses
this clock, along with the data stream, to construct a clock for the data. This clock may then
be used as the Z-ASCC receive clock, the
transmit clock, or both.
PARITY
llOP
III
IIr--DA-T-A"'I"'I~I~11
DATA
I I I I MARKING LINE
ASYNCHRONOUS
Figure 3. Z-ASCC Protocol
2042-108
291
Functional
Description·
( Continued)
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is .locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the Z-ASCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding The Z-ASCC may be programmed to encode and decode the serial data
in four different ways (Figure 4). In NRZ
encoding, a 1 is represented by a High· level
and a 0 is represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a 0 is represented by a change in
level. In FMI (more properly, bi-phase mark)
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a 1
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the Z-ASCC can be used to
decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to I,
the bit is a O. If the transition is 1 to 0 the
bit is a 1.
Auto Echo and Local Loopback~ The Z-ASCC
is capable of automatically echoing everything
it receives. In Auto Echo mode, RxD is connected to TxD internally. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS inpuUs ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The Z-ASCC is also capable of Local Loopback. In this mode TxD is connected to RxD
internally, just as in Auto Echo mode.
However, in Local Loopback mode, the internal transmit data is tied to the internal receive
data and RxD is ignored (except to be echoed
out via TxD). The CTS and DCD inputs are
also ignored as transmit and receive enables.
However; transitions on thes!3 inputs can still
cause interrupts. Local Loopback works with
NRZ, NRZI or FM coding of the data stream.
I/O Interface Capabilities. The Z-ASCC
offers the choice of Polling, Interrupt (vectored
or nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the Z-ASCC are automatically updated when~ver any function is performed. The idea behind polling is for the
CPU to periodically read a status register until
the register contents indicate the need for data
to be transferred. Only one register needs to
be read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
DATA
NRZ
NRZI
\
\
I
I
\
\
FM1
FMIf
MANCHESTER'
Figure 4. Data Encoding Methods
292
2016-002
Functional
Description
(Continued)
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. The Z-ASCC interrupt scheme
conforms to the Z-.BUS specification. When a
Z-ASCC responds to an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt
vector may be placed on the A/D bus. This
vector is written in WR2 and may be read in
RR2A or RR2B (Figures 8 and 9).
To speed interrupt response time, the
Z-ASCC can modify three bits in this vector to
indicate status. If the vector is read in Channel
A, status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
Z-ASCC (Transmit, Receive, and External/Status interrupts in both channels) has
three bits associated with the interrupt source:
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bit is straightforward. If the IE bit
is set for a given interrupt source, then that
source can request interrupts. The exception is
when the MIE (Master Interrupt Enable) bit in
WR9 is reset and no interrupts may be
requested. The IE bits are write only.
The other two bits are related to the Z-BUS
interrupt priority chain (Figure 5). The
Z-ASCC may request an interrupt only when
no higher priority device is requesting one,
e.g., when IEI is High. If the device in question requests an interrupt, it pulls down INT.
The CPU then responds with INTACK, and the
interrupting device places the vector on the
AID bus.
In the Z-ASCC, the IP bit signals a need for
interrupt servicing. When an IP bit is 1 and
the IEI input is High, the INT output is pulled
Low, requesting an interrupt. In the Z-ASCC,
if the IE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP is set two or three AS cycles after the
interrupt condition occurs. Two or three AS
rising edges are required from the time an
interrupt condition occurs until INT is activated. The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the Z-ASCC and
external to the Z-ASCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the IEO output of theZ-ASCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled; the
receiver can interrupt the CPU in one of
three ways:
Interrupt on First Receive Character or
Special Receive Condition.
IJ
11 Interrupt on All Receive Characters or
Special Receive Condition.
e Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is receiver
overrun, and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receive character available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First Receive Character, an interrupt can occur from Special Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and RI pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection
of a Break.
Z·BUS
Z·BUS
PERIPHERAL
lEI ADo-AD7 INT INTACK lEO
Z·BUS
PERIPHERAL
PERIPHERAL
iNT
lEI ADo-AD7 iNf INTACK
lEI ADo-AD7
INTACK lEO
+5V
+5V
ADo-AD7V-______________________________
~
______________
~
INT.-------------~;_--------------~~r_--------------~~~
INTACK~--------------~~--------------~~----------------~
Figure 5. Z-BUS Interrupt Schedule
2016·003
293
Functional
Description:
(Continued)
CPU/DMA Block Transfer. TheZ-ASCC provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Trarisfer mode uses the
WAIT/REQUEST output in conjunction with the
Wait/Request bits in WRl. The WAIT/
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the Z-ASCC REQUEST
output indicates that the Z-ASCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the Z-ASCC is not
ready to transfer data, thereby requesting that
the CPU extend the I/O cycle. The DTR/
REQUEST line allows full-duplex operation
under DMA control.
Architecture
The Z-ASCC internal structure includes
two full-duplex channels, two baud rate
generators, intern9-1 control and interrupt
logic, and a bus interface to the Zilog Z-BUS.
Associated with each channel are a number of
read and write registers for mode control and
status information, as well as logic necessary to
interface to modems or other external devices
(Figure 6).
The logic for both channels provides
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the
BAUD RATE
GENERATOR
A
WAIT/REQUEST
INTERNAL
CONTROL
LOGIC
CHANNEL A
REGISTERS
_
}
ADDRESS/~
MODEM, DMA, OR
OTHER CONTROLS
DATA~
CPU
BUS I/O
INTERNAL BUS
-}
CONTROL
..
INTERRUPT
CONTROL
LINES
,I I I
+SVGND PCLK
INTERRUPT
CONTROL
LOGIC
B
CHANNEL 5
MODEM, DMA, OR
OTHER CONTROLS
ISERIALDATA
}.':HANNEL CLOCKS
RI
WAIT/REQUEST
Figure 6. Block Diagram of Z-ASCC Architecture
294
2245-003
10
10
->
0 ...
""6
o
. ""
(JJ
o n
ae:
s· it
n
CD ....
o..S::
s::
---(;
CPU 110
BR GENERATOR
INPUT
BR GENERATOR
OUTPUT
RECEIVE
RECEIVE
DATA
ERROR
FIFO
FIFO
TRANSMIT
CLOCK
RxD
DPLL
DPLL OUTPUT
BR GENERATOR OUTPUT
DPLL OUTPUT
3
TRxC
RECEIVE CLOCK
CLOCK
MUX
RTxC
TRANSMIT CLOCK
DPLL CLOCK
BR GENERATOR CLOCK
(OSCILLATO~ --J...--J
f\)
<0
01
Figure 1. Data Path
33SV-Z 1£081
Architecture
(Continued)
baud rate. Finally, associated with' the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write-only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WR 15 -
Write Registers 0-5, 8-15.
Read Register Functions
RRO
TransmiVReceive buffer status and External status
RRI
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only)
Unmodified interrupt vector (Channel A only)
RR3
Interrupt Pending bits (Channel A only)
RR8
Receive buffer,
RRIO
Miscellaneous status
RR12
Lower byte of baud rate generator time constant
RR13
Upper byte of baud rate generator time constant
RR15
External/Status interrupt information
RRO-RR3, RRIO, RRI2, RRI3, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The Z-ASCC contains
only one WR2 and WR9, but they can be
accessed by either channel. All other registers
are paired (one for each channel).
Programming.
296
Write Register Functions
WRO
CRC initialize, initialization commands for the
various modes, shift righVshift left command
WRI
TransmiVReceive interrupt and data transfer mode
definition
WR2
WR3
WR4
Interrupt vector (accessed through either channel)
Receive parameters and control
Data Path. The transmit and receive data path
illustrated in Figure 7 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths depending on the
selected mode (the character length determines the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
bus and an 11-bit Transmit Shift register that is
loaded from the Transmit Data register.
WRlO
Miscellaneous transmitter/receiver control bits
WRll
Clock mode control
WRl2
WR13
WR14
WRl5
Lower byte of baud rate generator time constant
The Z-ASCC contains 11 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels. All of the registers
in the Z-ASCC are directly addressable. How
the Z-ASCC decodes the address placed on
the address/data bus at the beginning of a
Read or Write cycle is controlled by a command issued in WROB. In the shift right mode,
the channel select NB is taken from ADo and
the state of AD5 is ignored. In the shift left
mode, NB is taken from AD5 and the state of
ADo is ignored. AD7 and AD6 are always
ignored as address bits and the register
address itself occupies AD4 - ADl.
The system program first issues a series of
commands to initialize the basic mode of -,
operation. For example, the character length,
clock rate, 'number of stop bits, even or odd
parity might be set first. Then the Interrupt
mode would be set, and finally, receiver or
transmitter enable.
WR5
TransmiVReceive miscellaneous parameters and
modes
Transmit parameters and controls
WR8
Transmit buffer
WR9
Master interrupt control and reset (accessed
through either channel)
Upper byte of baud rate generator time constant
Miscellaneous control bits
External/Status interrupt control
Table 1. Read and Write Register Functions
Programming Read Registers. The Z-ASCC contains eight
(Continued)
read registers (actually nine, counting the
receive buffer [RR8]) in each channel. Four of
these may be read to obtain status information
(RRO, RRl, RRlO, and RRlS). Two registers
(RR12 and RR13) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the
Read Register 10
Read Register 0
I
Interrupt Pending OP) bits (Channel A).
Figure 8 shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a single
register (RRl).
llli ~i~~:::::"~'"
~
~
RING INDICATOR
N
CTS
00
C
1.
W
' - - - - - - - - ONE CLOCK MISSING
' - - - - - - - - BREAK
tool
Read Register 1
Read Rogister 12
.
I~I~I~I~I~I~I~I~I
~1~
LOWER BYTE OF
TIME CONSTANT
' - - - - - - - - TC7'
Read Register 2
Read Register 13
UPPER BYTE OF'
TIME CONSTANT
INTERRUPT VECTOR'
' - -_ _ _ _ _ _ TC15
' - - - - - - - - V7
'MODIFIED IN B CHANNEL
Read Register 3
L~
~~illt1,
.
Read Register 15
CHANNELBEXT/STATIP'
CHANNEL B Tx IP'
CHANNEL B Rx IP'
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'
o
II
illt1 ~~::'"~"
2="
1
' - - - - - - - - BREAK IE
'ALWAYS 0 IN B CHANNEL
Figure 8. Read Register Bit Functions
2245-005
297
Programming Write Registers. The Z-ASCC contains 11
(Continued)
write registers (12 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the chami.els. In
addition, there are two registers (WR2 and
Write Register 0
WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits. Figure
9 shows the format of each write register.
Write Register 3
i~I~I~I~I~I~I~I~1
~t:::~~,,~
0
0
0
1
NULL CODE
o
0
Rx 5 BITS/CHARACTER
0
0
1
NULL CODE
o
1
Rx 7 BITS/CHARACTER
0
1
0
RESET EXT/STATUS INTERRUPTS
1
0
Rx 6 BITS/CHARACTER
0
1
1
NULL CODE
1
1
Rx 8 BITS/CHARACTER
1
0
0
ENABLE INT ON NEXT Rx CHARACTER
1
0
1
RESET Tx INT PENDING
1
1
0
ERROR RESET
1
1
1
RESET HIGHEST IUS
0
0
o
1
NULL CODE
NULL CODE
1
0
SELECT SHIFT LEFT MODE'
1
1
:ELECTSHIFT RIGHT MODE'
Write Register 4
~
Write Register 1
o
I~I~I~I~I~I~I~I~I
II
L
L ,no",..",
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
o
Rx INT DISABLE
1
Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION
I L PARITY ENABLE
L PARITY EVEN/ODD
o
0
1
1
0
DO NOT PROGRAM
1 STOP BITICHARACTER
1 'Iz STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
'X 1 CLOCK MODE
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
o
o
0
1
1
X16 CLOCK MODE
1
1
1
0
X32 CLOCK MODE
1
1
X64 CLOCK MODE
Rx INT ON SPECIAL CONDITION ONLY
1...-_ _ _ _ _ WAITIDMA REQUEST ON RECEIVEITRANSMIT
' - - - - - - - - WAITIDMA REQUEST FUNCTION
' - - - - - - - - - WAIT/DMA REQUEST ENABLE
Write Register 5
Write Register 2
INTERRUPT VECTOR
o
0
o
1
Tx 7 BITS/CHARACTER
1
0
Tx 6 BITS/CHARACTER
1
1
Tx 8 BITS/CHARACTER
Tx 5 BITS (OR LESS)/CHARACTER
' - - - - - - - - - - V7
' - - - - - - - - - - DTR
Figure 9, Write Register Bit Functions
2245-006
Programming Write Register 9
Write Register 12
(Continued)
I~I~I~I~I~I~I~I~I
~~
~~
L ~~~
DLC
MIE
:TATUS HIGHISTATUS LOW
o
NO RESET
1
CHANNEL RESET B
1
0
CHANNEL RESET A
1
'1
FORCE HARDWARE RESET
LOWER BYTE OF
TIME CONSTANT
' - - - - - - - - - - TC7
Write Register 13
Writer Register 10
UPPER BYTE OF
TIME CONSTANT
' - - - - - - - - - - TC15
o
o
0
1
NRZI
1
0
FM1 (TRANSITION
= 1)
1
1
FMO (TRANSITION
= 0)
NRZ
Write Register 14
L BR GENERATOR ENABLE
~~
L
Write Register 11
BR GENERATOR SOURCE
D'fRIREQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK
0
0
0
NULL COMMAND
0
0
TRxC OUT = XTAL OUTPUT
0
0
1
ENTER SEARCH MODE
o
1
TRxC OUT = TRANSMIT CLOCK
0
1
RESET MISSING CLOCK
1
O. TRxC OUT = BR GENERATOR OUTPUT
0
1
DISABLE DPLL
1
1
1
0
0
SET SOURCE
1
0
1
SET SOURCE
1
1
0
SET FM MODE
1
1
1
SET NRZI MODE
[1
TRxC OUT
TRxC
= DPLL OUTPUT
oli
-
o
o
0
1
TRANSMIT CLOCK = TRxC PIN
1
0
TRANSMIT CLOCK
1
1
TRANSMIT CLOCK = DPLL OUTPUT
TRANSMIT CLOCK = RTxC PIN
=BR GENERATOR
= RTxC
= BR GENERATOR OUTPUT
Write Register 15
RECEIVE CLOCK
= RTxC PIN
1
RECEIVE CLOCK
= TRxC PIN
0
RECEIVE CLOCK = BR GENERATOR OUTPUT
o
o
0
1
1
1
RECEIVE CLOCK = DPLL OUTPUT
" - - - - - - - - - ffTxC
I~I~I~I~I~I~I~I~I
XTAUNO XTAL
~~~:ro"m"
' - - - - - - - - - - BREAK IE
Figure 9. Write Register Bit Functions (Continued)
2245-006
299
Timing
The Z-ASCC generates internal control
signals from AS and DS that are related to
PCLK. Since PCLK has no phase relationship
with AS and DS, the circuitry generating these
internal control signals must provide time for
metastable conditio~s to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the Z-ASCC. The recovery
time required for proper operation is specified
from the rising edge of DS in the first transaction involving the Z-ASCC to the falling edge
CSo
ADo-AD7
\
I
/
\
X
ADDRESS
of DSin the second transaction involving the
Z-ASCC. This time must be at'least 6 PCLK
cycles plus 200 ns.
Read Cycle Timing. Figure 10 illustrates
Read cycle timing. The address on ADo-AD 7
and the state of CSo and INTACK are latched
by the rising edge of AS. R!W must be High to
indicate a Read cycle. CSI must also be High
for the Read cycle to occur. The data bus
drivers in the Z-ASCC are then enabled while
DS is Low~
('--____.."x
)
DATA VALID
}--
/
- R/Vi
c
/
\\-.____----J;Figure 10. Read Cycle T~ming
Write Cycle Timing. Figure II illustrates
Write cycle timing. The address on ADo-AD7
and the state of CSo and INTACK are latched
by the rising edge of AS. R/W must be Low to
CSo
ADo-AD7
R/Vi
\
I
/
\
X
ADDRESS
x:x
indicate a Write cycle. CSI must be High for
the Write cycle to occur. DS Low strobes the
data into the Z-ASCC.
~
_ _ _ _X=
DATA
\
r=
/
'C
\~----------~;-
Figure 11. Write Cycle Timing
Interrupt Acknowledge Cycle Timing.
Figure 12 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD7 and
the state of CSo and INTACK are latched by
300
the rising edge of AS. However, if INTACK is
Low, the address and CSo are ignored. The
state of the R/W and CSI are also ignored for
the duration of the Interrupt Acknowledge
2016-007,008,005
Timing
(Continued)
intended for the Z-ASCC. In this case, the
cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
IEl/IEO daisy chains settle. If there is an interrupt pending in the Z-ASCC and IEI is High
when DS falls, the Acknowledge cycle was
CSo
_ _ _J
X
(IGNORED)
~
ADO-AD7
X
(IGNORED)
Z-A,SCC may be programmed to respond to
DS Low by placing its interrupt vector on
ADo-AD7. It then sets the appropriate
Interrupt-Under-Service latch internally.
~,
X
I
:,':'
)
/f
ex
}-
VECTOR
I
I....w
Figure 12. Interrupt Acknowledge Cycle Timing
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150 °C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
+4.75 V ~ Vee ~ +5.25 V
iJ GND = 0 V
IJ TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
[J
+5V
+5V
2.1K
2.2K
FROM OUTPUT
UNDER TEST
~r
50PF
Figure 13. Standard Test Load
DC
Symbol
Characteristics
Figure 14. Open-Drain Test Load
Parameter
Min
Max
Unit
Condition
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
2.0
-0.3
2.4
Vcc +0.3
0.8
V
V
V
V
pA
pA
rnA
IOH =
IOL =
0.4 :S
0.4 :S
0.4
± 10.0
±1O.0
250
-250 pA
+2.0 rnA
VIN :S + 2.4V
Your :S + 2.4V
Vee = 5 V ± 5% unless otherwise specified, over speCified temperature range.
Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
Unmeasured Pins
Returned to Ground
f = I MHz, over specified temperature range.
2016·009 8085·006,001
301
Read and
Write
Timing
Cio
Riw
READ _ _ _ _
-++-_,.,1
R/W
WRITE
-----1-+----++-+-------------1-4-----------
ADo-ADr
WRITE _ _ _,
1'o-+-+--"'l
·ADo-ADr
READ _ _- - '
l-++--'I
W/REQ
WAIT
W/REQ
-+-_____-+___--'
REQUEST _ _ _ _ _
DTR/REQ
-+-______________________
REQUEST _ _ _ _ _
14-~--__{28l_---_t------------------
4 MHz
No.
Symbol
Parameter
Min
AS Lov; Width
70
DS I to AS I Delay
50
CSo to AS I Setup Time
0
CSo to AS I Hold Time
60
CS I to DS I Setup T i m e - - - - - - - - - - 100
CS] to DS IJioid Time
55
INTACK to AS I Setup Time
0
INTACK to AS I Hold Time
250
R/W (Read) to DS I Setup Time
100
RIW to DS I Hold Time - - - - - - - - - - 55
RIW (Write) to DS I Setup Time
0
AS I to DS I Delay
60
DS Low Width
390
Valid Access Recovery Time
6TcPC
+200
15 - TsA(AS) - - - Address to AS I Setup Time - - - - - - - - - 30
16
ThA(AS)
Address to AS I Hold Time
50
17
TsDW(DS)
Write Data to DS I Setup Time
30
18
ThDW(DS)
Write Data to DS I Hold Time
30
19
TdDS(DA)
DS I to Data Active Delay
0
20 -TdDSr(DR)-- DS I to Read Data Not Valid D e l a y - - - - - - - 0
21
TdDSf(DR)
DS I to Read Data Valid Delay
22
TdAS(DR)
AS I to Read Data Valid Delay
Max
1
TwAS
2
TdDS(AS)
3
TsCSO(AS)
4
ThCSO(AS)
5-:-TsCS1(DS)-6
ThCS1(DS)
TsIA(AS)
7
8
ThIA(AS)
9
TsRWR(DS)
10 - ThRW(DS)-11
TsRWW(DS)
12
TdAS(DS)
13
TwDSl
14
TrC
NOTES:
1. Parameter does not apply to Interrupt Acknowledge
transactions.
2. Parameter applies only between transactions involving
302
250
520
6 MHz
Min
Max
Notes*t
50
25
0
1
40
1
80 - - - - - - - 1 40
1
0
250
80
40
0
40
250
6TcPC
2
+ 130
10 - - - - - - - 1 30
1
20
20
0
0
180
335
the Z-ASCC.
"Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
2016-010
Interrupt
Acknow ledge
Timing
Ai
ADO-AD7----------------------+---------------~--_r
IIlI
1110
N
CO
C
W
....
Reset
Timing
N
•
III
til
n
n
/.
Cycle
Timing
PCLK
4 MHz
No.
Symbol
Parameter
23
TdDS(DRz)
24
TdA(DR)
25
TdDS(W)
26
TdDSf(REQ)
27-TdDSr(REQ)-
Min
Max
6MHz
Min
Max
DSt to Read Data Float Delay
70
45
Address Required Valid to Read Data Valid Delay
570
420
DS , to Wait Valid Delay
240
200
DS , to W/REQ Not Valid Delay
240
200
DS i to DTRlREQ Not Valid D e l a y - - - - - - - - - 5TcPC
5TcPC
+300
+250
28
TdAS(INT)
AS t to INT Valid Delay
500
500
29
TdAS(DSA)
AS t to DS , (Acknowledge) Delay
30
TwDSA
DS (Acknowledge) Low Width
390
250
31
TdDSA(DR)
DS , (Acknowledge) to Read Data Valid Delay
180
250
32 - TsIEI(DSA) - - IEI to DS , (Acknowledge) Setup Time - - - - - 120
100
33
ThIEI(DSA)
lEI to DS t (Acknowledge) Hold Time
0
0
100
34
TdIEI(IEO)
IEI to IEO Delay
120
TdAS(IEO)
AS t to IEO Delay
250
35
250
36
TdDSA(INT)
DS , (Acknowledge) to INT Inactive Delay
500
500
37 - TdDS(ASQ) - - DS t to AS , Delay for No Reset - - - - - - - - 30
15
38
TdASQ(DS)
AS t to DS , Delay for No Reset
30
30
39
TwRES
AS and DS Coincident Low for Reset
250
250
40
TwPCl
PCLK Low Width
70
105
2000
1000
41
TwPCh
PCLK High Width
105
2000
70
1000
4000 - - 1 6 5 - 2000
42-TcPC
PCLK Cycle Time - - - - - - - - - - - - 250 43
TrPC
PCLK Rise Time
20
15
TfPC
PCLK Fall Time
20
44
10
NOTES:
3. Float delay is defined as the time required for a ± 0.5 V change
in the output with a maximum dc load and minimum ac load.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system dependent. For any Z-ASCC in the daisy
chain, TdAS(DSA) must be greater than the sum of TdAS(IEO)
for the highest priority device in the daisy chain, TsIEI(DSA)
for the Z·ASCC, and TdIEIf(IEO) for each device separating
them in tll') daisy chain.
2016·011. 012, 013
Notes*t
3
4
4
5
6
4
7
6. Parameter applies only to a Z·ASCC pulling INT Low at the
beginning of the Interrupt Acknowledge transaction.
7. Internal circuitry allows for the reset provided by the Z8 to be
recognized as a reset by the Z-ASCC .
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
t Units in nanoseconds (ns).
303
General
Timing
PeLf(
WIREQ
REQUEST
WIREQ
WAIT ______________________~------------------------------I
RTaC,TRaC
RECEIVE
----------------....;1[""
RaD
TRaC,RTaC
TRANSMIT
_~
TaD_Cl-:
--------'-~-------_-_®_II~---~~~:~~-------------------------------------------------
OUTPUT
TRaC __________________________~
~
_________________________________________________
''------1~~"
.i==3~
TRaC-----\~______~--------'--~r---CTa, DCD, iii
304
_ _ _
1ft.
/
r~~
2245-007
4 MHz
No.
2
Symbol
Parameter
TdPC(REQ)
PCLK 1 to W IREQ Valid
PCLK 1 to Wait Inactive Delay
TdPC(W)
Min
Max
6MHz
Min
Max
250
Notes*t
250
350
350
3
TsRXC(PC)
RxC t to PCLK t Setup Time (PCLK -;- 4 case only)
4
TsRXD(RXCr)
RxD to RxC t Setup Time (Xl Mode)
RxD to RxC t Hold Time (Xl Mode)
0
150
150 - - - - - - - 1 -
0
150
0
150
1,5
1,5
0
2,4
5 - ThRXD(RXCr) -
80
TwPCl
70
0_
6
7
TsRXD(RXCf)
RxD to RxC 1 Setup Time (Xl Mode)
ThRXD(RXCf)
RxD to RxC 1 Hold Time(Xl Mode)
8
TsTXC(PC)
TxC 1 to PCLK t Setup Time
9
TdTXCf(TXD)
TxC 1 to TxD Delay (Xl Mode)
10 -
TdTXCr(TXD) -
TxC t to TxD Delay (Xl Mode)
11
12
TdTXD(TRX)
TwRTXh
TxD to TRicC Delay (Send Clock Echo)
RTxC High Width
180
180
13
TwRTX1
RTxC Low Width
180
180
14
. TcRTX
0
1,4
300
300
2
300 - - - - - 300 - - - 2,5-
RTxC Cycle Time
15 16
400
400
TcRTXX - - - Crystal Oscillator Period - - - - - - - - - - 250 -1000 - - 250 TwTRXh
TRxC High Width
180
180
17
TwTRXl
TRxC Low Width
18
TcTRX
19
TwEXT
180
180
TRxC Cycle Time
400
400
DCD or CTS or RI Pulse Width
200
200
NOTES:
I. RxC is RTxC or TRxC, whichever is supplying the receive
clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit
clock.
3. Both RTxC and ill have 30 pF capacitors to the ground
connected to them.
4. Parameter applies only if the data rate is one-fourth the PCLK
rate. In all other cases, no phase relationship between RxC and
TwPCI
6
6
6
1000 - - - 3 6
6
6
PCLK or TxC and PCLK is required.
5. Paramet~r applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and
baud rate generator timing requirements are identical to chip
PCLK requirements .
• Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
305
N
00
0
W
....
N
•
;J:II
(I)
n
n
System
Timing
RTJlC,TRJlC
RECEIVE
W/REQ
REQUEST
W/REQ
WAIT
RTJlC, TRJlC
TRANSMIT
W/REQ
REQUEST
W/REQ
WAIT
DTRlREQ
REQUEST
CTS, DCD,RI
INT
No.
2
3
45
6
7
8
Symbol
. Parameter
TdRXC(REQ)
RxC t to W/REQ Valid Delay
TdRXC(W)
RxC t to Wait Inactive Delay
TdRXC(INT)
RxC t INT Valid Delay
TdTXC(REQ)-TxC l to W/REQ Valid Delay
TdTXC(W)
TxC l to Wait Inactive Delay
TdTXC(DRQ)
TxC l to DTRlREQ Valid Delay
TdTXC(INT)
TxC l to INT Valid Delay
TdEXT(INT)
DCD,
ru or CTS Transition to INT Valid Delay
NOTES:
1. ~n-drain output, measured with open-drain test load.
2. RxC Is RTxC or TRxC, whichever is supplying the receive
clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit
clock.
306
t
~
CD
Min
4 MHz
Max
12
8
12
8
12
8
+2
+3
5--8
5
8
7
4
4
6
+2
+3
2
3
6 MHz
Min
Max
Notes*
2,4
8
12
1,2,4
8
12
1,2,4
8
12
5
+2
+3
5--8--·-3,41,3,4
5
8
3,4
4
7
1,3,4
4
6
5
+2
+3
1,5
2
3
4. Units equal to Tcpe.
5. Units equal to AS.
• Timings are preliminary and subject to change.
2245-008
Ordering
Information
Product
Number
Package/
Speed
Temp
Description
Product
Number
Z8031A
Z8031
CE
4.0 MHz
Z-ASCC (40-pin)
Z8031
CM
4.0 MHz
Same as above
Z8031
CMB
4.0 MHz
Z8031
CS
4.0 MHz
Z8031
DE
4.0 MHz
Z8031
DS
Z8031
PE
. Z8031
PS
Package/
Speed
Temp
Description
CE
6.0 MHz
Z-ASCC (40-pin)
Z8031A
CM
6.0 MHz
Same as above
Same as above
Z8031A
CMB
6.0 MHz
Same as above
Same as above
Z8031A
CS
6.0 MHz
Same as above
Same as above
Z8031A
DE
6.0 MHz
Same as above
4.0 MHz
Same as above
Z8031A
DS
6.0 MHz
Same as above
4.0 MHz
Same as above
Z8031A
PE
6.0 MHz
Same as above
4.0 MHz
Same as above
Z8031A
PS
6.0 MHz
Same as above
NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -40°C to +85°C, M = -55°C to 125°C, MB = -55°C to + 125°C with
MIL-STD-883 with Class B processing, S = O°C to + 70°C.
Iw...
307
18036 Z8000™ z-elo
Counler/Timer and
~allai1Rei i/O iJ'niil
Product
Specification
Zilog
September 1983
Features
Ell
Two independent 8-bit, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode), "pulse
catchers," and programmable opendrain outputs.
EI Flexible pattern-recognition logic, program-
mable as a 16-vector interrupt controller.
m Three independent 16-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave),
programmable as retriggerable or
nonretriggerable.
c Four handshake modes, including 3-Wire
(like the IEEE-488).
EJ REQUEST/WAIT signal for high-speed data
transfer.
General
Description
The Z8036 Z-CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most
counter/timer and parallel I/O needs
encountered in system designs. This versatile
device contains three I/O ports and three
counter/timers. Many programmable options
tailor its configuration to specific applications.
-
AD6
AD7
_ADs
_ 7_)
PA A
P
6
PA _
s
_
_
AD,
AD3
AD2
_
_
ADl
ADo
PA, PA3 _
PA
2
PAl
PA _
o
_
_
AS
Os
-
CSo
_
.
ADDRESS/DATA
BUS
1
BUS TIMING {
AND RESET
CONTROL
RtW
za036
Z.CIO
PC3 PC2 _
pC _
l
_
ADl
PORT A
INTERRUPT {
-
lEI
PB
lEO
PB 3 _
ADo
CsO
PAo
}
PBl
PORT C
PAl
PA2
PA3
PA,
PAs
P
PB6B
_ 7_)
PBs _
The use of the device is simplified by making
all internal registers (command, status, and
data) readable and (except for status bits)
writable. In addition, each register is given its
own unique address so that it can be
accessed directly-no special sequential
operations are required. The Z-CIO is directly
Z-Bus compatible.
AD2
PCo -
INTACK
Easy to use since all registers are read/write
and directly addressable.
AD3
{
_CS
iNTl
C
PA6
PA7
4
-
PB 2 PB _
PB l _
o
PORTB
INTACK
iNT
+5V
PC3
PC2
PCLK + 5 V GND
Figuro 1. Pin Functions
2014-0035, 00,36
Figure 2. Pin Assignments
309
Pin
Description
ADo-AD7. Z-Bus Address/Data lines
(bidirectional/3-state). These multiplexed
Address/Data lines are used for transfers
between the CPU and Z-CIO.
AS*. Address Strobe (input, active Low).
Addresses,INTACK, and CSa are sampled
while AS is Low.
CSo and CSI. Chip Select 0 (input, active
Low) and Chip Select 1 (input, active High).
CSa and CSl must be Low and High, respectively, in order to select a device. CSa is
latched by AS.
DS*. Data Strobe (input, active Low). DS provides timing for the transfer of data into or out
of the Z-CIO.
lEI. Interrupt Enable In (input, active High).
lEI is used with IEO to form an 'interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). IEO is High only if IEI is High and the
CPU is not servicing an interrupt from the
requesting Z-CIO or is not requesting an interrupt (Interrupt Acknowledge cycle only). lEO
is connected to the next lower priority device's
IEI input and thus inhibits interrupts from
lower priority devices.
'When As and iSS are detected Low at the same time (normally
an illegal condition). the Z-CIO is reset.
Architecture
The Z8036 Z-CIO CounterlTimer and
Parallel I/O element (Figure 3) consists of a
INTERRUPT
CONTROL
LOGIC
<
,
INTE:RUPT >
CONTROL
INT. Interrupt Request (output, open-drain,
active Low). This signal is pulled Low when
the Z-CIO requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates to the Z-CIO that
an Interrupt Acknowledge cycle is in progress.
INTACK is sampled while AS is Low.
PAo-PA7. Port A I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the Z-CIO's Port
A and external devices.
PBo-PB7. Port B I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the Z-CIO's Port
B and external devices. May also be used to .
'provide external access to Counter/Timers
1 and 2.
PCc-PC3. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports.A and B or to provide
external access to Counter/Timer 3 or access
to the Z-CIO's Port C.
PCLK. (input, TTL-compatible). This is a
peripheral dock that may be, but is not
necessarily, the CPU clock. It is used with
. timers and REQUEST/WAIT logic.
R/W. Read/Write (input). R/W indicates that
the CPU is reading from (High) or writing to
(Lo~) the Z-CIO.
Z-Bus interface, threeI/O ports (two generalpurpose 8-bit ports and one special-purpose
I
11
V
ADDRESSI
OAT: BUS>
CON~ROL
PORTA>
1/0
---------..
<
I'
I / L - - - - - - - ' DART
INTERNAL BUS
A
I~
I'
Z.BUS
DCRT
O
~
INTERFACE
PORTC
it'
>1-_ _---1
INPUTS
INTERNAL
CONTROL
LOGIC
,
PORT
B
>
1/0
<
PORTB
va
>
Figure 3. Z-CIO Block Diagram
310
2014-001
Architecture
(Continued)
4-bit port), three 16-bit counter/timers, an
interrupt control logic block, and the internal
control logic block. An extensive number of
programmable options allow the user to tailor
the configuration to best suit the specific
application.
The two general-purpose 8-bit I/O ports
(Figure 4) are identical, except that Port B can
be specified to provide external access to
Counter/Timers 1 and 2. Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit individually programmable. Each
port includes pattern-recognition logic, allowing interrupt generation when a specific pattern is detected. The pattern-recognition logic
can be programmed so the port functions like
a priority-interrupt controller. Ports A and B
can also be linked to form a 16-bit I/O port.
To control these capabilities, both ports contain 12 registers. Thre~ of these registers, the
Input, Output, and Buffer registers, comprise
the data path registers. Two registers, the
Mode Specification and Handshake Specification registers, are used to define the mode of
the port and to specify which handshake, if
any, is to be used. The reference pattern for
the pattern-recognition logic is defined via
three registers: the Pattern Polarity, Pattern
Transition, and Pattern Mask registers. The
detailed characteristics of each bit path (for
example, the direction of data flow or whether
a path is inverting or noninverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initially configured, only this register must be
accessed frequently. To facilitate initialization,
the port logic is designed so that registers
associated with an unrequired capability are
ignored and do not have to be programmed.
INTERNAL
INPUT
BUFFERI
INVERTERS
AND
l's
CATCHER
OUTPUT
DATA
REGISTER
PATIERN
RECOGNITION
LOGIC
PORT
110
"
INPUT
DATA
REGISTER
OUTPUT
BUFFERI
INVERTERS
PORT
CONTROL
LOGIC
TO PORT C
Figure 4. Ports A and B Block Diagram
2014-002
311
Architecture
(Continued)
The function of the special-purpose 4-bit
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
I/O lines or to provide external access for the
third counter/timer.
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The three counter/timers (Figure 6) are all
identical. Each is comprised of a 16-bit downcounter, a 16-bit Time Constant register
(which holds the value loaded into the downcounter), a 16-bit Current Counter register
(used to read the contents of the downcounter), and two 8-bit registers for control
and status (the Mode Specification and the
Command and Status registers).
The capabilities of the counter/timer are
numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.
The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
The interrupt control logic provides standard
Z-Bus interrupt capabilities. There are five
registers (Master Interrupt Control register,
three Interrupt Vector registers, and the Current Vector register) associated with the interrupt logic. In addition, the ports' Command
and Status registers and the counter/timers'
Command and Status registers include bits
associated with the interrupt logic. Each of
these registers contains three bits for interrupt
control and status: Interrupt Pending (IP),
Interrupt Under Service (IUS), and Interrupt
Enable (IE).
TO COUNTERI
TIMER 3
INPUT
BUFFERI
INVERTERS
AND
l's
CATCHER
INTERNAL
BUS
OUTPUT
DATA
REGISTER
~PORT
0
r-i"
INPUT
DATA
REGISTER
OUTPUT
BUFFERI
INVERTERS
PORT
CONTROL
LOGIC
I~ONTROL
.'-----4'rINTERNAL PORT
.
...J
LINES
<- - - - _
.....
Figure 5. Port C Block Diagram
312
2014·003
Archi tecture
(Continued)
INTERNAL
BUS
CURRENT
COUNT
REGISTER
(MSB's)
CURRENT
COUNT
R~~~~~R I - - - - . . . J
I
eft
i
Figure 6. Counter/Timer Block Diagram
Functional
Description
The following describes the functions
of the ports, pattern-recognition logic,
counter/timers, and interrupt logic,
I
I/O Port Operations. Of the Z-CIO's three
I/O ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also
provides access for Counter/Timers 1 and 2. In
all configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUESTIWAIT line can also be provided
so that Z-CIO transfers can be synchronized
with DMAs or CPUs. Any Port C bits not used
for handshake or REQUEST/WAIT can be used
as input or output bits (indiVidually data direction programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any' combination of bits can be set
and/or cleared while the other bits
remain undisturbed without first reading the
register.
port's Data Direction register specifies the
direction of data flow for each bit. A 1
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the input just prior to
the read. A l's catcher can be inserted into the
input data path by programming a 1 to the
corresponding bit position of the port's Special
I/O Control register. When a 1 is detected at
'the 1's catcher input, its output is set to a 1
until it is cleared. The l's catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be specified as opendrain by writing a 1 to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with aI, the state of the corresponding output
bit is not changed.
Bit Port Operations. In bit port operations, the
2014-004
313
Functional
Description
(Continued)
Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The Z-CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake' logic. Port C provides the
handshake lines as shown in Table 1. Any Port
C lines not used for handshake can be used as
simple I/O lines or as access lines for Counter/
Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (IP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (ITB) control
bit is set to I, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read or
written.
When the Single Buffer (SB) bit is set to I,
the port acts as if it is only single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
Port AlB Configuration.
Ports A and B:
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the Z-CIO must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
output port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the previous byte of the data is no longer available,
thereby acknowledging the input port's acceptance of the last byte. This allows the Z-CIO to
interface directly to the port of a Z8 microcomputer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAV) output for output po~ts.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles speCified by the
deskew timer ti~e constant plus one, DAV is
PCa
P~
PCI
PCO
Bit I/O
Bit I/O
Bit I/O
Bit I/O
Port A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)·
~FD or DAV
ACKIN
REQUESTIW AIT
or Bit I/O
Bit I/O
Port B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)·
REQUESTIWAIT
or Bit I/O
Bit I/O
RFD or DAV
ACKIN
Port A or B: Input Port (3-Wire
Handshake)
RFD (Output)
DAV (Input)
REQUESTIW AIT
or Bit I/O
DAC (Output)
DA V (Output)
DAC (Input)
REQUESTIW AIT
or Bit I/O
RFD (Input)
RFD or DAV
ACKIN
REQUESTIW AIT
or Bit I/O
IN/OUT
Port A or B:
Bit Ports
A has pattern-match capability. Port B's
pattern-match capability must be disabled.
Also, when the ports are linked, Port B's Data
register must be read or written before
Port A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port G (Tabie 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have l's catchers; therefore, those bits in the
Special I/O Control register are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Output Port (3-Wire
H~ndshake)
Port A or B: Bidirectional Port
(Interlocked or Strobed Handshake)
"Both Ports A and B can be specified input or output with Interlocked, Strobed, or Pulsed Handshake at the same time if neither
uses REQUESTIWAIT.
Table 1. Port C Bit Utilization
314
Functional
Description
(Continued)
allowed to go Low. The deskew timer therefore
guarantees that the output'data is valid for a
specified minimum amount of time before DA V
goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is "strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked Handshake, the signal
indicating the port is ready for another data
transfer operates independently of the ACKIN
input. It is up to the external logic.to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate if an input port is ready
for new data or if it has accepted the present
data. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake,
the output lines of many input ports can be
bussed together with open-drain drivers; the
Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devices that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logic is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the. ACKIN path.
The external ACKIN input trigg-ars the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintains all of its normal
capabilities. This handshake is not available to
bidirectional ports.
OUTPUT HANDSHAKE
INPUT HANDSHAKE
DATA:J<
output port knows when all the ports have
accepted the data and are ready. This is the
same handshake as is used on the IEEE-488
bus. Because this handshake requires three
lines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be
changed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.
VALID
X'-_________
DATA
NEXT BYTE
RFD
)----
DATA LATCHED
IN BUFFER REGISTER
BUFFER REGISTER
"EMPTIED"
INTERLOCKED
¥HANDSHAKE
STROBED
HANDSHAKE'
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Figuro 7. Intorlockod and Strobod Handshakes
OUTPUT HANDSHAKE
INPUT HANDSHAKE
DATA:J<
VALID
X'-_________
NEXT BYTE
DATA
nfD
DAY
INPUT
INPUT
nfD
OUTPUT
DAC
INPUT
DAC
OUTPUT
DAY
OUTPUT
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Figuro 8. 3-Wiro Handshako
2014-005, 006
315
Functional
Description
(Continued)
REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a data transfer via the Z-Bus. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUEST/WAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a. handshake and a
REQUEST/WAIT line. The other port must be
a bit port ..
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (ITB) control bit. When ITB is 0, the
REQUEST line goes active as soon as the
Z-CIO is ready for a data transfer. If ITB is I,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is availabre to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allOWing the port to recognize patterns in all of
its configurations. The pattern can be
independently ·specified for each bit as I, 0,
rising edge, falling edge, or any transition.
Individual bits may be masked off. A patternmatch is defined as the simultane.ous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT
ACKIN
(EXTERNAL)
ACKIN
(INTERNAL)
D-t>
OUTPUT PORT
Figure 9. Pulsed Handshake
316
r-.,
'------' ....~~
I
The pattern specified in the Pattern Definition register assumes that the data path is programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
speCified. Output bits used in the patternmatch logic are internally sampled before the
invertlnoninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as I/O for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the invertlnoninvert
logic) in all cases except for simple inputs with
l's catchers. In this case, the output of the l's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports speCified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transition from a no-match to a match state is
not required.
The pattern-recognition logic of bit ports
operates in two basic modes: Transparent and
Latched. When the Latch on Pattern Match
(LPM) bit is set to 0 (Transparent mode), the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = 1), the state of all the
port inputs at the time the interrupt was generated is latched in the input register and held
until IP is cleared. In all cases, the PMF indicates the state of the port at the time it is read.
If a match occurs while IP is already set, an
error condition exists. If the Interrupt On Error
bit (IOE) is 0, the match is ignored. However,
if IOE is I, after the first IP is cleared, it is
automatically set to 1 along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP is cleared.
When a pattern-match is present in the
OR-Priority Encoded Vector mode, IP is set to
1. The IP cannot be cleared until a match is no
longer present. If the interrupt vector is
allowed to include status, the vector returned
during Interrupt Acknowledge indicates the
highest priority bit matching its speCification at
the time of the Acknowledge cycle. Bit 7 is the
highest priority and bit 0 is the lowest. The bit
initially causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the
Acknowledge cycle is initiated, the vector is
2014-007
Functional
Description
(Continued)
. frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the l's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection is
performed in this mode and the Interrupt On
Error bit should be set to O.
Function
CounterlTimer Output
Counter Input
Trigger Input
Gate Input
C/Tl
C/T2
C/T3
PB
PB
PB
PB
PB
4
5
6
7
a
pca
PB 1
PB 2
PC 1
PC2
PB 3
PC3
Table 2. Counter/Timer External Access
The flexibility of the counter/timers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate 'input,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer lis external I/O lines are provided by
the four most significant bits of Port B.
Counter/Timer 2' s are provided by the four
least significant bits of Port B. Counter/Timer
3' s external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode Specification
registers.
When external counter/timer I/O lines are to
be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as simple input
lines. They can be specified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the l's catcher input.
Counter/Timers 1 and 2 can be linked internally in three different ways. Counter/Timer
l's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer 1
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/
Ports with Handshake Pattern::Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the Pattern
Match Flag (PMF). The data is compared with
the match pattern when it is shifted from the
Buffer register to the Input register (input port)
or when it is shifted from the Output register to
the Buffer register (output port). The patternmatch logic can override the handshake logic
in certain situations. If the port is programmed
to interrupt when two bytes of data are
available to be read or written, but the first
byte matches the specified pattern, the
pattern-recognition logic sets IP and generates
an interrupt. While PMF is set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emptied while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit is
set, IP is set only when the data matches the
pattern. This is useful in DMA-type applications when interrupts are required only after a
block of data is transferred.
CounterITimer. Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode SpeCification register,
an 8-bit Command and Status register, and the
associated control logic that links these
registers.
PCLK/2 OR
COUNTER INPUT
TRIGGER
--1
Ie
GATE
I
PULSE OUTPUT
ONE SHOT
OUTPUT
TC
I
LJ
TC-l
I
TC-l
I
TC-2
I· · · I
I
~t
I
II
-------1~
L---
If
---""
SQUARE WAVE
OUTPUT
FIRSTHALF _ _ _ _ _ _ _ _ _ _ _ _......,(.10"_ _ _-1
SQUARE WAVE OUTPUT
-
-
-
-
------------I'~'----,
SECONO HALF
Figure 10. Counter/Timer Waveforms
2014-008
317
Functional
Description
(Continued)
318
timer waveforms. When the Pulse mode is
specified, the output goes High for one clock
cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode;
the output goes High when the counter/timer is
triggered and goes Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/timer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter· to be loaded and the normal countdown sequence to begin. If ,a 1 count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value is reloaded. On the clocking edge, when
both the down-counter and the output are l's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode Specification register controls operation of the down~counter when it reaches terminal count. If C/SC is 0 when a terminal
count is reached, the countdown sequence
'stops. If the C/SC bit is 1 each time the countdown counter reaches 1, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register c;md initiating the countdown sequence
by loading the down-counter with the time
constant value. The Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter is loaded in one of
three ways: by writing a 1 to the Trigger
Command Bit (TCB) of the Command and
Status register, on the rising edge of the external trigger input, or, for Counter/Timer 2 only,
on the rising edge of Counter/Timer l's internal output if the counters are linked via the
trigger input. The TCB is write-only, and read
always returns O.
'
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are 1
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
Specification register. If REB is 0, retriggers
are ignored and the countdown continues normally. If REB is I, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output
is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECE] bit is 0), the down-counter is clocked
internally by a signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is I), the down-counter is
decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to 1,
and if interrupts are enabled (IE = 1), an interrupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to a 1
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(CIP) status bit in the Command and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16-bit register, accessible as two
8-bit registers, which mirrors the contents of
the down-counter. This register can be read
anytime. 'However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a 1 .to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.
Interrupt Logic Operation. The interrupts
generated by the Z-CIO follow the Z-Bus
operation as described more fully in the Zilog
Z-Bus Summary. The Z-CIO has five potential
sources of interrupts: the three counter/timers
and Ports A and B. The priorities of these
.
sources are fixed in the following order:
Counter/Timer 3, Port A, Counter/Timer 2,
Port B, and Counter/Timer 1. Since the
counter/timers all have equal capabilities and
Ports A and B have equal capabilities, there is
no adverse impact from the relative priorities.
The Z-CIO interrupt priority, relative to
other components within the system, is determined by an interrupt daisy chain. Two pins,
Interrupt Enable In (IEI) and Interrupt Enable
Out (lEO), provide the input and output
necessary to implement the daisy chain. When
IEI is pulled Low by a higher priority device,
Functional
Description
(Continued)
the Z-CIO cannot request an interrupt of the
CPU. The following discussion assumes that
the IEI line is High.
Each source of interrupt in the Z-CIO contains three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bit, an Interrupt Unde.r Service (IUS)
status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is 1.
The IUS status bit is set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge commences. It
can also be set directly by the CPU. Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do not request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off individual SQurces of interrupts.
When IE is set to I, an interrupt is generated
normally. When IE is set to a, the IP bit is set
when an event occurs that would normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the Z-CIO to be
disabled without having to individually set '
each IE to O. If MIE is set to a, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain
(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to I, the Z-CIO's lEO is forced Low,
independent of the state of the Z-CIO or its IEI
input, and all lower priority devices' interrupts
are disabled.
As part of the Interrupt Acknowledge cycle,
the Z-CIO is capable of responding with an
8-bit interrupt vector that specifies the source
of the interrupt. The Z-CIO contains three vector registers: one for Port A, one for Port B,
and one shared by the three counter/timers.
The vector output is inhibited by setting the No
Vector (NV) control bit to 1. The vector output
can be modified to include status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = I, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this way, all the information obtained by the vector, including
status, can be obtained with one additional
instruction when VIS is set to o. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the Z-CIO in a polled
environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.
Programming
Programming the Z-CIO entails loading control registers with bits to implement the desired
operation. Individual enable bits are prOVided
for the various major blocks so that erroneous
operations do not occur while the part is being
initialized. Before the ports are enabled, IPs
cannot be set, REQUEST and WAIT cannot be
asserted, and all outputs remain high-impedance. The handshake lines are ignored until
Port C is enabled. The counter/timers cannot
be triggered until their enable bits are set.
The Z-CIO is reset by forcing AS and DS
Low Simultaneously or by writing a 1 to the
Reset bit. Once reset, the only thing that can
be done is to read and write the Reset bit.
Writes to all other bits are ignored and all
reads return as. In this state, all control bits
are forced to O. Only after clearing the Reset
bit (by writing to it) can the other command
bits be programmed.
Register Addressing. The Z-CIO allows two
schemes for register addressing. Both schemes
use only six of the eight bits of the address/
data bus. The scheme used is determined by
the Right Justify Address (RJA) bit in the
Master Interrupt Control register. When RJA
equals 0, address bus bits a and 7 are ignored,
and bits 1 through 6 are decoded for the
register address (Ao from ADl). When RJA
equals I, bits a through 5 are decoded for the
register address (Ao from ADo). In the following register descriptions, only six bits are
shown for addresses and represent address/
data bus bits a through 5 or 1 through 6,
depending on the state of the RJA bit.
319
Registers
Master Interrupt Control Regi~ter
Address: 000000
(ReadlWrite)
MAST~R
INTERRUPT
ENABLE (MIE)
~~
DISABLE LOWER CHAIN (DLC)
NO VECTOR (NV)
PORT A VECTOR INCLUDES
STATUS (PA VIS)
\
~
Master Configuration Control Register
Address: 000001
(ReadlWrite)
PORTB~
JJ
~RESET
I L 'O"",'M'.""",
CONTROLS (LC)
ENABLE (PBE)
RIGHT JUSTIFIED ADDRESSES
0= SHIFT LEFT (Ao from AD,)
1 = RIGHT JUSTIFY (Ao from ADo)
COUNTERITIMER 1
ENABLE (CT1E)
COUNTERITIMERS VECTOR
INCLUDES STATUS (CT VIS)
COUNTERITIMER 2
ENABLE (CT2E)
PORT B VECTOR INCLUDES
STATUS (PB VIS)
PORT C AND COUNTERI
TIMER 3 ENABLE
(PCE AND CT3E)
LCl
LCO
o
1
1
1
·0
1
--0 -0
COUNTERITIMERS INDEPENDENT
CIT 1'5 OUTPUT GATES CIT 2
CIT l's OUTPUT TRIGGERS CIT 2
CIT 1'5 OUTPUT IS CIT 2's
.COUNT INPUT
PORT A ENABLE (PAE)
L-_ _ _ PORT LINK CONTROL (PLC)
0= PORTS A AND B OPERATE INDEPENDENTLY
1 = PORTS A AND B ARE LINKED
Figure 11. Master Control Registers
Port Handshake Specification Registers
Addresses: 100001 Port A
101001 Port B
(ReadlWrite)
Port Mode Specification Registers
Addresses: 100000 Port A
10 1000 Port B
(ReadIW rite)
I~I~I~I~I~I~I~I~I
PORTTYPE~
SELECTS (PTS)
PTSl PTSO.
[ ) [ ) BIT PORT
o
1 INPUT PORT
1
0 OUTPUT PORT
1
1 BIDIRECTIONAL
PORT
INTERRUPT ON TWO
BYTES (IT B)
SINGLE BUFFERED
MODE (SB)
L
LATCH ON PATIERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (DTE)
(HANDSHAKE MODES)
HANDSHAKE TYPE SPECIFICAT.
ION:J
BITS (HSn
.
I ---c ""'" n."",,,,,,,,o,
BITS
~~~~~~~I~~~ ~~:~sC~NSTANT.
HSTl HSTO
o
0 INTERLOCKED HANDSHAKE
o
1 STROBED HANDSHAKE
1
0 PULSED HANDSHAKE
1
1 THREE·WIRE HANDSHAKE
PATIERN MODE SPECIFICATION
BITS (PMS)
PMSl PMSO
o
0 DISABLE PATIERN MATCH
o
1 "AND"MODE
1
0 "OR" MODE
1
1 "OR·PRIORITY ENCODED
VECTOR" MODE
REQUESTIWAIT SPECIFICATION BITS
(RWS)
RWS2 RWS1 RWSO FUNCTION
o
- 0 - REQUESTIWAIT DISABLED
o
1
OUTPUT WAIT
1
1
INPUT WAIT
o
0
SPECIAL REQUEST
o
1
OUTPUT REQUEST
1
1
INPUT REQUEST
' - - - - - INTERRUPT ON MATCH ONLY (IMO)
LSB IS FORCED 1.
.
.
Port Command and Status Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
.
INTERRUPT PENDING (IP)
IUS, IE, AND IP ARE WRITIEN USING
THE FOLLOWING CODE:
0
CLEAR IUS
o
o
o
o
1
1
SET IP
1
0
0
CLEAR·IP
1
0
1
SET IE
1
1
0
CLEAR IE
1
1
1
NULL CODE
CLEAR IP & IUS
SET IUS
~
.I L
INTERRUPT UNDER
SERVICE (IUS)
INTERRUPT ENABLE (IE)
0
0
1
1
0
L
INTERRUPT ON ERROR (IOE)
PATIERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (lRF)
(READ ONLy)
OUTPU'T REGISTER EMPTY (ORE)
(READ ONLy)
INTERRUPT ERROR (ERR) - - - - '
(READ ONLy)
Figure 12. Port Specification Registers
320
2014-009, 010
Registers
(Continued)
Data Direction Registers
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(ReadlWrite)
Data Path Polarity Registers
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(ReadlWrite)
' - - - - - DATA DIRECTION (DO)
O=OUTPUT BIT
1 =INPUT BIT
' - - - - - DATA PATH POLARITY (DPP)
0" NON·INVERTING
1 = INVERTING
Special I/O Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port·C (4 LSBs only)
(ReadlWrite)
' - - - - - SPECIAL INPUT/OUTPUT (SIO)
0= NORMAL INPUT OR OUTPUT
1 =OUTPUT WITH OPEN DRAIN OR
INPUT WITH l's CATCHER
Figure 13. Bit Path Definition Registers
Port· Data Registers
Addresses: 001101 Port A
001110 Port B
(ReadlWrite)
Port C Data Register
Address: 001111
(ReadlWrite)
4 MSBs
O. WRITING OF CORRESPONDING LSB ENABLED
1 _ WRITING OF CORRESPONDING LSB INHIBITED
(READ RETURNS 1)
Figure 14. Port Data Registers
Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(ReadlWrite)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Porf B
(ReadlWrite)
PM PT PP PATIERN SPECIFICATION
BIT MASKED OFF
o 1 X ANY TRANSITION
1 0 0 ZERO
1 0 lONE
1 1 0 ONE·TO·ZERO TRANSITION (\)
1 1 1 ZERO·TO·ONE TRANSITION (I)
0" 0" X
Pattern Mask Registers (PM)
Addresses: 100111 Port A
101111 Port B
(ReadlWrite)
Figure 15. Pattern Definition Registers
2014-011, 012, 013
321
Registers
(Continued)
Counter/Timer Command and Status Registers
Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2
001100 Counter/Timer 3
(Read/Partial Write)
'""''"' "'"'" ",." """ l
INTERRUPT ENABLE (IE)
INTERRUPT PENDING (lP)
II
I
I
I
I
IUS, IE, AND IP ARE WRITIEN USING
THE FOLLOWING CODE:
E~
NULL CODE
COUNT IN PROGRESS (CIP)
(READ ONLy)
TRIGGER COMMAND BIT (TCB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (GCB)
READ COUNTER CONTROl: (RCC)
(READISET ONLYCLEARED BY READING CCR LSB)
CLEAR IP & IUS
SET IUS
CLEAR IUS
SET IP
CLEAR IP
1
0
1
SET IE
1
1
0
CLEAR IE
1
1
1
INTERRUPT ERROR (ERR) _ _ _---1
(READ ONLy)
Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/Timer 1
011101 Counter/Timer 2
011110 Counter/Timer 3
(Read/Write)
S.lli.~
J~
IL
CONTINUOUS
GLE CYCLE (CISC)
EXTERNAL OUTPUT
ENABLE (EOE)
EXTERNAL COUNT
ENABLE (ECE)
EXTERNAL TRIGGER
ENABLE (ETE)
SELECTS (DCS)'"''
,""mon
•
DCS1DCSO
----0- ----0- PULSE OUTPUT
o
1
1
1
0
1
ONE·SHOT OUTPUT
SQUARE·WAVE OUTPUT
DO NOT SPECIFY
RETRIGGER ENABLE BIT (REB)
L..-._ _ _ EXTERNAL GATE ENABLE (EGE)
Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer l's MSB
010001.Counter/Timer l's LSB
010010 Counter/Timer 2's MSB
010011 Counter/Timer 2's LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)
MOST - - - - - '
SIGNIFICANT
BYTE
' - - - - - - LEAST
SIGNIFICANT
BYTE
Counter/Timer Time Constant Registers
Addresses: 010110 Counter/Timer l's MSB
010111 Counter/Timer l's LSB
011000 Counter/Timer 2's MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 C'ounter/Timer 3's LSB
(Read/Write)
MOST-------'
SIGNIFICANT
BYTE
' - - - - - - LEAST
SIGNIFICANT
BYTE
Figure 16. Conter/Timer Registers
322
2014-014
Registers
Current Vector Register
Address: 011111
(Read Only)
Interrupt Vector Register
Addresses: 000010 Port A
000011 Port B
000100 Counter/Timers
(ReacllWrite)
(Continued)
L..-_ _ _ INTERRUPT VECTOR BASED
ON HIGHEST PRIORITY
UNMASKED IP.
IF NO INTERRUPT PENDING
ALL 1's OUTPUT.
L..-_ _ _ INTERRUPT VECTOR
PORT VECTOR STATUS
PRIORITY ENCODED VECTOR MODE:
NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH
ALL OTHER MODES:
03
02
01
ORE iRF PMF NORMAL
0
0
ERROR
o
COUNTERfTlMER STATUS
02 01
0' 0'
1
1
0
CfT3
CfT 2
CfT 1
1
1
ERROR
o
Figure 17. Interrupt Vector Registers
Register
Address
Summary
Address'
000000
000001
000010
000011
000100
000101
000110
000111
Main Control Registers
Register Name
Master Interrupt Control
Master Configuration Control
Port A's Interrupt Vector
Port B's Interrupt Vector
CounterlTimer's Interrupt Vector
Port C's Data Path Polarity
Port C's Data Direction
Port C's Special I/O Control
Address·"
100000
100001
100010
100011
100100
100101
100110
100111
Port A Specification Registers
Register Name
Port A's Mode Specification
Port A's Handshake Specification
Port A's Data Path Polarity
Port A's Data Direction
Port A's Special I/O Control
Port A's Pattern Polarity
Port A's Pattern Transition
Port A's Pattern Mask
Address·
001000
001001
001010
001011
001100
001101
001110
001111
Most Often Accessed Registers
Register Name
Port A's Command and Status
Port B's Command and Status
CounterlTimer l's Command and Status
Counter/Timer 2's Command and Status
Counter/Timer 3's Command and Status
Port A's Data
Port B's Data
Port C's Data
Address·
101000
101001
101010
101011
101100
101101
101110
101111
Port B Specification Registers
Register Name
Port B's Mode Specification
Port B's Handshake Specification
Port B's Data Path Polarity
Port B's Data Direction
Port B's Special I/O Control
Port B's Pattern Polarity
Port B's Pattern Transition
Port B's Pattern Mask
Address·
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Counter/Timer Related Registers
Register Name
Counter/Timer 1's Current Count-MSBs
Counter/Timer l's Current Count-LSBs
Counter/Timer 2's Current Count-MSBs
CounterlTimer 2's Current Count-LSBs
Counter/Timer 3's Current Count-MSBs
Counter/Timer 3's Current Count-LSBs
Counter/Timer 1's Time Constant-MSBs
Counter/Timer l's Time Constant-LSBs
Counter/Timer 2's Time Constant-MSBs
Counter/Timer 2's Time Constant-LSBs
Counter/Timer 3's Time Constant-MSBs
Counter/Timer 3's Time Constant-LSBs
Counter/Timer l's Mode SpeCification
Counter/Timer 2's Mode Specification
CounterlTimer 3's Mode Specification
Current Vector
'When RIA = 0, AO from AD1; when RIA = 1, AO from ADO
2014·015
323
Timing
Read Cycle. The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSa and CSl). Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The data from the register specified is
strobed onto the address/data bus when the
CPU issues a Data Strobe (DS). If the register
indicated by the address does not exist, the
Z-CIO remains high-impedance.
1
CS1
RIW
I
\
Os
ADo-AD7
~
VALID
(
Write Cycle. The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external'logic to provide two Chip
Selects (CSa and CSd. Six bits of the least
significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The CPU places the data on the
address/data,bus and strobes it into the Z-CIO
register by issuing a Data Strobe (DS).
~
CS1
~
RlW
r-
Os
READ DATA ) - -
~
I
c=
r-
\
\
ADAD~
07
VALID
x=
WRITE DATA
Figure 19. Write Cycle Timing
Figure 18. Read Cycle Timing
Interrupt Acknowledge Cycle. When one of
the IP bits in the Z-CIO goes High and interrupts are enabled, the Z-CIO pulls its INT
output line Low, requesting an interrupt. The
CPU responds with an Interrupt Acknowledge
cycle. When INTACK goes Low with IP set, the
Z-CIO pulls its Interrupt Enable Out (lEO)
Low, disabling all lower priority devices on the
daisy chain. The CPU reads the Z-CIO interrupt vector by issuing a Low DS, thereby
strobing the interrupt vector onto the address/
data bus. The IUS that corresponds to the IP is
also set, which causes lEO to remain Low.
1
INT ______________________
lEI
lEO
\--------------\'--_---J/
ADo-AD7
,
°INTACK is decoded from 28000 status.
Figure 20. Interrupt Acknowledge Timing
(
324
2014·016,017,018
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these speCifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows -into the referenced pin. Standard conditions are as follows:
• +4;75 V ::s; Vee ::s; +5.25 V
• GND = 0 V
TA as speCified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
II
+5V
+5V
dr
2.2K
FROM OUTPUT
UNDER TEST
50 PF
Figure 21. . Standard Test Load
DC
Characteristics
Symbol
Parameter
Figure 22. Open-Drain Test Load
Min
Max
Unit
Vee+ 0.3
V
VIH
Input High Voltage
2.0
VIL
VOH
Input Low Voltage
-0.3
Output High Voltage
VOL
Output Low Voltage
0.8
Condition
V
V
IOH = -250 p,A
0.4
V
IOL = +2.0 rnA
V
pA
IOL = +3.2 rnA
0.4 :S VIN:s + 2.4 V
O.4:sVOUT
2.4
ILL
Input Leakage
0.5
± 10.0
IOL
Output Leakage
± 10.0
p,A
Icc
Vee Supply Current
200
rnA
:S
+2.4V
Vee= 5 V ± 5% unless otherwise specified, over speCified temperature range.
Capacitance
Symbol
Parameter
Min
Max
Unit
C IN
Input Capacitance
Output Capacitance
10
15
pF
C OUT
C vo
Bidirectional Capacitance
20
pF
pF
Test Condition
Unrneasured Pins
Returned to Ground
f = 1 MHz, over speCified temperature range.
8085·0209, 0001
325
CPU
Interface
Timing
Interrupt
Timing
~TCH
PAT'TEM
INPUT(S)
BIT PORT
=1:.==========:-=@n-;::::::::::•..7,--------PATTERN MATCHES
ACKIN
NOTE4
COUNTER
INPUT
PCLK
Interrupt
Acknowledge
Timing
lEI
lEO
326
2014-019, 020, 021
\
No.
Symbol
Parameter
TwAS
AS Low Width
Address to AS I Setup Time
Address to AS I Hold Time
Address to DS , Setup Time
TsA(AS)
2
ThA(AS)
3
4-TsA(DS)
TsCSO(AS)
5
Min
4MHz
Max
70
30
50
130
CSo to AS I Setup Time
ThCSO(AS)
CSo to AS I Hold Time
6
TdAS(DS)
AS t to DS 1 Delay
7
S-TsCSl(DS)-- CS 1 to DS 1 Setup Time
TsRWR(DS)
R/W (Read) to DS 1 Setup Time
9
R/W (Write) to DS 1 Setup Time
TsRWW(DS)
10
DS Low Width
TwDS
11
12-TsDW(DSf)--Write Data to DS I' Setup Time
TdDS(DRV)
DS (Read) 1 to Address Data Bus Driven
13
TdDSf(DR)
DS I to Read Data Valid Delay
14
ThDW(DS)
Write Data to DS I Hold Time
15
16- TdDSr(DR) - - DS I to Read Data Not Valid Delay
TdDS(DRz)
DS I to Read Data Float Delay
17
ThRW(DS)
R/W to DS I Hold Tirpe
IS
ThCSl(DS)
CS 1 to DS I Hold Time
19
20-TdDS(AS)--DS t to AS I Delay
Trc
Valid Access Recovery Time
21
TslA(AS)
0
40
40
100
100
SO
SO
a
0
250
20
0
a
250
30
0
1-
Bel
ISO
C
W
en
20
0
45
70
lNTACK to AS I Setup Time
Notes*t
2000
10
30
100
390
30
ThlA(AS)
INTACK to AS t Hold Time
2S
TsAS(DSA)
AS I to DS (Acknowledge) I Setup Time
29
30-TdDSA(DR)--DS (Acknowledge) I to Read Data Valid Delay
DS (Acknowledge) Low Width
31
TwDSA
TdAS(IEO)
AS t to IEO I Delay (lNTACK Cycle)
32
33-TdIEI(IEO) --IEI to IEO Delay
TslEI(DSA)
lEO to DS (Acknowledge) I Setup Time
34
ThIEl(DSA)
lEI to DS (Acknowledge) I Hold Time
35
TdDSA(lNT)
DS
(Acknowledge) 1 to INT I Delay
36
NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is measured to the time when the output has
changed 0.5 V from steady state with minimum ac load and
maximum dc load.
3. This is the delay from iSS, r of one CIO access to OS j of
another CIO access.
4. The delay is from DAV j for 3-Wire Input Handshake. The
delay is from DAC r for 3-Wire Output Handshake. One
additional AS cycle is required for ports in the Single Buffere'd mode:
50
0
60
60
55
40
55
50
1000
40
25
650
TdPM(INT)
Pattern Match to INT Delay (Bit Port)
22
TdACK(INT)
ACKIN to INT Delay (Port with Handshake)
23
24-TdCI(INT)--Counter Input to INT Delay (Counter Mode)
TdPC(lNT)
PCLK to INT Delay (Timer Mode)
25
TdAS(lNT)
AS to INT Delay
26
27
2000
6 MHz
Min
Max
1 +SOO
3
1 +SOO
6
4,6
4+600
1+700---6-
4+600
1 +700
1 +700
300
1 +700
a
a
250
350
250
250
6
5
180
250
390
...0~
2
250
250
100
350
150
100
100
5
70
70
600
5
5-
600
S. The parameters for the devices in any particular daisy
chain must meet the following constraint: the delay from
AS r to f5S j must be greater than the sum of TdAS(lEO)
for the highest priority peripheral. TsIEI(DSA) for the
lowest priority peripheral, and TdIEI(IEO) for each
peripheral separating them in the chain.
6. Units equal to AS cycle + ns.
• Timings are preliminary and subject to change.
t Units in nanoseconds(nsl. except as noted.
327
Strobed
Handshake
INPUT
OUTPUT
==x ~ATAVALID X\..-_ __
0i=\ !:Joe:: ----:...FF:l-3-it:b:}.....--'
. . :. . __
Interlocked
Handshake
DATA
DATA
OU'rPUT
ACKiii
DAY
a-Wire
Handshake
DATA
DAY
INPUT
INPUT
RFD
OUTPUT
DAC
OUTPUT
DATA
DAC
INPUT
OUTPUT
RFD
INPUT
DAY
OUTPUT
328
2014-022, 023, 024
No.
Symbol
Parameter
TsDI(ACK)
ThDI(ACK)
Data Input to ACKIN I Setup Time
Data Input to ACKIN I Hold Time - Strobed
Handshake
TdACKf(RFD)
ACKIN I to RFD I Delay
3
4-TwACKl---ACKIN Low Width - Strobed Handshake
5
TwACKh
ACKIN High Width - Strobed Handshake
1
2
Min
4MHz
Max
6 MHz
Max
Min
0
500
o
0
250
250
o
Notes*t
0
o
TdRFDr(ACK)
RFD I to ACKIN ,I Delqy
6
25'
TsDO(DAV)
20
·7
Data Out to DAV I Setup Time
TdDAVf(ACK) DAV I to ACKIN I Delay
o
8
0
-------29-ThDO(ACK)-- Data Out to ACKIN I Hold Time - - - - - - - 10
TdACK(DAV)
ACKIN I to DAV I Delay
1
1
2
11
ThDI(RFD)
Data Input to RFD I Hold Time - Interlocked
0
o
Handshake
12
TdRFDf(ACK)
RFD I to ACKIN I Delay - Interlocked Handshake
0
0
13-TdACKr(RFD)-ACKIN I (DAV I) to RFD I Delay - I n t e r l o c k e d - - O - - - - - - O - - - - - - - and 3-Wire Handshake
14
TdDAVr(ACK) DAV I to ACKIN I (RFD I ) - Interlocked and
0
o
3-Wire Handshake
15
TdACK(DAV)
ACKIN I (RFD I )to DAV I Delay - Interlocked and
0
o
3-Wire Handshake
16-TdDAVIf(DAC)-DAV I to DAC I Delay - Input 3-Wire H a n d s h a k e - - O - - - - - - O - - - - - - - 17
ThDI(DAC)
Data Input to DAC I Hold Time - 3-Wire
0
0
Handshake
18
TdDACOr(DAV) DAC I to DAV I Delay - Input 3-Wire Handshake
0
0
19
TdDAVIr(DAC) DAV I to DAC I Delay - Input 3-Wire Handshake
0
0
20-TdDAVOf(DAC)-DAV I to DAC I Delay - Output 3-Wire Handshake - 0 - - - - - - 0 - - - - - - - 21
ThDO(DAC)
Data Output to DAC I Hold Time - 3-Wire
1
2
Handshake
22
TdDACIr(DAV) DAC I to DAV I Delay - Output 3-Wire Handshake
1
1
2
23
TdDAVOr(DAC) DAV I to DAC I Delay - Output 3-Wire Handshake
0
o
NOTES:
1. This time can be extended through the use of the d8skew
timers.
Units equal to AS cycle.
2.
• Timings are preliminary and subject to change. All timing
references assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
r Units in nanoseconds (ns), except as noted.
329
Counter/
Timer
Timing
PCLK
PCLKI2
INTERNAL
_ _ _ _ _.J
COUNTER
INPUT
TRIGGER
INPUT
GATE
INPUT
COUNTER
OUTPUT
No.
Symbol
Parameter
Min
4MHz
Max
6 MHz
Min
Max
Notes*t
165
4000
2S0
4000
TePC
PCLK Cycle Time
1
70
2000
PCLK High Width
105
2000
TwPCh
2
70
2000
PCLK Low Width
105
2000
TwPCl
3
20
10
PCLK Fall Time
4
TfPC
15
20
TrPC
PCLK Rise Time
5
330
Counter Input Cycle Time
500
6-TeCI
150
230
Counter Input High Width
7
TCIh
150
Low
Width
230
Counter
Input
8
TwCIl
15
20
Counter Input Fall Time
9
TfCI
15
10
TrCI
Counter Input Rise Time
20
Il-TsTI(PC)---Trigger Input to PCLK 1 Setup Time--lS0 - - - - - - - - - - - - - - - 2
(Timer Mode)
2
Trigger Input to Counter Input 1 Setup
TsTI(CI)
150
12
Time (Counter Mode)
13
TwTI
Trigger Input Pulse Vlidth (High or Low) 200
14 -TsGI(PC)---Gate Input to PCLK 1 Setup Time - - - ' 100 - - - - - - - - - - - - - - - 2
(Timer Mode)
2
Gate Input to Counter Input 1 Setup
100
TsGI(CI)
IS
Time (Counter Mode)
2
Gate Input to PCLK 1 Hold Time (Timer 100
ThGI(PC)
16
Mode)
17 - ThGI(CI)---Gate Input to Counter Input 1 Hold --100 - - - - - - - - - - - - - - - 2
Time (Counter Mode)
18
TdPC(CO)
PCLK to Counter Output Delay (Timer
475
Mode)
TdCI(CO)
475
Counter Input to Counter Output Delay
19
(Counter Mode)
NOTES:
1. PCLK is only used with the counter/timers (in Timer mode), the
deskew timers, and the REQUESTIW AIT logic. If these functions are not used, the PCLK input can be held low.
2. These parameters must be met to guarantee that trigger or gate
330
are valid for the next counter/timer cycle.
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "I" and 0.8 V for a logic "0".
t Units in nanoseconds (ns).
2014-025
REQUEST/
PCLK
WAIT
Timing
ACKIN
NOTE 1
REQ
No.
2
Min
Symbol
Parameter
TdDS(REQ)
TIS I to REQ I Delay
TdDS(WAIT)
TISI to WAIT I Delay
3
TdPC(REQ)
PCLK I to REQ t Delay
4
TdPC(WAIT)
PCLK I to WAIT t Delay
5
TdACK(REQ)
ACKIN I to REQ t Delay
6
TdACK(WAIT)
ACKIN I to WAIT t Delay
NOTES:
I. The Delay is from DAV J for the 3-Wire Input Handshake. The
delay is from DAC 1 for the 3-Wire Output Handshake.
2. UnIts equal to AS cycles + PCLK cycles + ns.
Reset
6MHz
Min
Max
500
500
300
300
3+2
+ 1000
10 +600
Notes*t
w
eft
...0J:
1,2
3
f~
',--------,.r~
RESET
INTERNAL
No.
2
3
----------------------~;-
Symbol
Parameter
Min
TdDSQ(AS)
Delay from DS t to AS I for No Reset
TdASQ(DS)
Delay from AS t to DS I for No Reset
TwRES
Minimum Width of AS and DS both Low ·for Reset
40
50
250
NOTES:
1. Internal circutry allows for the reset proVided by the Z8 (DS
held Low whJle AS pulses) to be sufficient.
2014-026, 027
4 MHz
Max
a
0
3. Units equal to PCLK cycles + ns .
• Timings are preliminary and subject to change. All timing refer"
ences assume 2.0 V for a logic "I" and 0.8 V for a l'ogic "0".
t Units in nanoseconds (ns), except as noted.
_DASSJ~
Timing
4MHz
Max
6 MHz
Max
Min
Notes*t
15
30
170
• Timings are prehminary and subject to change. All timing references assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
t Units in nanoseconds (ns).
331
Miscellaneous
Port
Timing
r
------~
1'. CATCHER
INPUT
=iL
0-
ANY INPUT
~~----------------
________I
\_~
___________
PATTERN
MATCH
INPUTeS) - - - - - - - - - 1 ' - - - - - - - ' 1 -~------DATATOBE ------~ ~---------~ , - - - - - - - - - - LATCHED TO
PATTERN MATCH - - - - - - - I ' - - - - - - - - - - J \ ~---------
4 MHz
6 MHz
Min
Symbol
Parameter·
2
Trl
TfI
Any Input Rise Time
Any Input Fall Time
3
Twl's
l's Catcher High Width
250
170
4
TwPM
Pattern Match Input Valid (Bit Port)
750
500
5
TsPMD
. ThPMD
Data Latched on Pattern Match Setup Time (Bit Port)
a
Data Latched on Pattern Match Hold Time (Bit Port) 1000
650
No.
6
Min
INIOUT
Max
Notes*t
100
100
100
NOTES:
1. If the input Is programmed inverting, a Low·going pulse of the
same width will be detected.
Bidirectional
Port
Timing
Max
100
a
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "1" and 0.8 V for a logic "0",
t Units in nanoseconds (ns).
/
I
-0--
J
RFD/DAV
.J.,
DATA
INIOUT
RFD/DAV
.
1;1
.,
CD
CD
CD
i
't
DATA _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
No.
Symbol
Parameter
TdIOr(DAV)
110
110
6 MHz
Min
Max
500
500
500
500
500
500
3
4
TdIOf(RFD)
I/O I to RFD/DAV High Delay
5
6
TdIOf(DAV)
110
TdDO(IO)
I/O I to Data Bus Driven
I to RFD/DAV I Delay
NOTES:
I. Units equal to AS cycle~
_.
2. Minimum delay is four AS cycles or one AS cycle after the corresponding IP is cleared, whichever is longer.
332
4MHz
Max
I to Data Float Delay
I/O I to ACKIN I Delay
I to RFD/DA V High Delay
TdIOr(DRZ)
TdIOr(ACK)
2
Min
Notes*t
2
3
2
3
2
• Timings are preliminary and subjecHo change. All timing
references assume 2.0 V for a logic "I" and 0.8 V for a logic "0".
t Units in nanoseconds (ns).
2014'028
00-2014-A
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Temp
Speed
Description
28036
CE
4.0 MHz
2-CIO (40-pin)
28036A
CE
6.0 MHz
2-CIO (40-pin)
28036
CM
4.0 MHz
Same as above
28036A
CM
6.0 MHz
Same as above
28036
CMB
4.0 MHz
Same as above
28036A
CMB
6.0 MHz
Same as above
28036
CS
4.0 MHz
Same as above
28036A
CS
6.0 MHz
Same as above
28036
DE
4.0 MHz
Same as above
28036A
DE
6.0 MHz
Same as above
28036
DS
4.0 MHz
Same as above
28036A
DS
6.0 MHz
Same as above
28036
PE
4.0 MHz
Same as above
28036A
PE
6.0 MHz
Same as above
28036
PS
4.0 MHz
Same as above
28036A
PS
6.0 MHz
Same as above
NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -40°C to +85°C, MB = -55°C to 125°C with MIL-STD-883 with Class B processing,
S = O°C to +70°C.
00-2014-02
333
18038 Z8000™
Z-FIO FIFO Inputl
ClU1Rpu~ ~iiRei'fa(Ce Uoii
Product
Specification
September 1983
Features
[J
[J
[J
General
Description
128-byte FIFO buffer provides asynchronous
bidirectional CPU/CPU or CPU/peripheral
interface, expandable to any width in byte
increments by use of multiple FIOs.
Interlocked 2-Wire or 3-Wire Handshake
logic port mode; Z-BUS or hon-Z-BUS
interface.
Pattern-recognition logic stops DMA
transfers and/or interrupts CPU; preset byte
count can initiate variable-length DMA
transfers.
The Z8038 FlO provides an asynchronous
128-byte FIFO buffer between two CPUs or
between a CPU and a peripheral device. This
buffer interface expands to a 16-bit or wider
data path and expands in depth to add as
many Z8060 FIFOs (and an additional FlO) as
are needed.
The FlO manages data transfers by assuming
Z-BUS, non-Z-BUS microprocessor (a generalized microprocessor interface), Interlocked
~:
{
-
I
O2
1
2
I
z.1..
-0
FI,O
~
Ml
-Mo
+5V
I
DATA
BUS
5
I
37
36
6 PORT: PORT35
2 34
7 1
8 SIDE I SIDE 33
I
10
I
za038
FlO
CONTROL
12
13
14
15
16
INTERRUPT
17
18
Ml
19
GND
20
I
I
I
02
I
03
I
I
I
06
I
I
Mo
GND
Figure 1. Pin Functions
2020-096, 097
+5V
I
I
0-
CONFIGURATION { -
lSI
•
til
2-Wire Handshake, and 3-Wire Handshake
operating modes. These modes interface
dissimilar CPUs or CPUs and peripherals
running under differing speeds or protocols,
allowing asynchronous data transactions and
improving I/O overhead by as much as two
orders of magnitude. Figures 1 and 2 show
how the signals controlling these operating
modes are mapped to the FlO pins.
-
!~)
{= I I==}
~!
00
directly addressable read/write registers.
02
00
eo
w
C)
m All functions are software controlled via
0 1 SIDE: SIDE 0 1
l-~
INTERRUPT
I
-
lSI
REQUEST/WAIT lines control high-speed
data transfers.
Ds-
04
:
04
0 3 PORT I PORT 0 3
_Do
CONT.J
I:'l
Seven sources of vectoredlnonvectored
interrupt which include pattern-match,
byte count, empty or full buffer status;
a dedicated "mailbox" register with
interrupt capability provides CPU/CPU
communication.
:' ~:_)
-os
DATA
BUS
II
Figure 2. Pin Assignments
335
....
o
General
Description
(Continued)
The FlO supports the Z-BUS interrupt protocols, generating seven sources of interrupts
upon any of the following events: a write to a
message register, change in data direction,
pattern match, status match, over/underflow
error, buffer full and buffer empty status. Each
interrupt source can be enabled or disabled,
and can also place an interrupt vector on the
port address/data lines.
The data transfer logic of the FlO has been
specially designed to work with DMA (Direct
Memory Access) devices for high-speed
transfers. It provides for data transfers to or
from memory each machine cycle, while the
DMA device generates memory address and
control signals. The FlO also supports the
variably sized block length, improving system
throughput when multiple variable length
messages are transferred amongst several
sources.
CPU
INTERFACE
OR
I/O PORT
CPU
INTERFACE
128 X 8
DATA
BUS \r--,f---t
FIFO BUFFER
r--""\.--"
DATA
BUS
PORT 1 SIDE : PORT 2 SIDE
Figure 3. FlO Block Diagram
Functional
Description
Operating Modes. Ports 1 and'2 operate in
any of twelve combinations of operating
modes, listed in Table 2. Port 1 functions in
either the Z-BUS or non-Z-BUS microprocessor
modes, ...;hile Port 2 functions in Z-BUS, nonZ-BUS, Interlocked 2-Wire Handshake, and
3-Wire Handshake modes. Table 1 describes
the signals and their corresponding pins in
each of these modes.
The pin diagrams of the FlO are identical,
except for two pins on the Port 1 side, which
select that port's operating mode. Port 2's
operating mode is programmed by two bits in
Port l's Control register O. Table 2 describes
the combinations of operating modes; Table 3
describes the control signals mapped to pins
A-J in the five possible operating modes.
3-Wire
HS Port'"
Signal
Pins
Z-BUS
Low Byte
Z-BUS
High Byte
Non-Z-BUS
[KJ
[!]
@J
[Q]
REQIWT
REQIWT
REQIWT
RFD/DAV
RFD/DAV
DMASTB
DMASTB
DACK
ACKIN
DAV/DAC
Interlocked
HS Port'"
DS
DS
RD
FULL
DAC/RFD
R!W
PJW
WR
EMPTY
EMPTY
~
[TI
@]
[ill
INTACK
Aa
INTACK
INa
INa
lEO
Al
lEO
OUTI
OUTI
OJ
W
lEI
A2
lEI
OE
OE
INT
A3
INT
OUT3
OUT3
CS
CS
CE
CLEAR
CLEAR
AS
AS
C/D
DATA DIR
DATA DIR
*2 side only.
Table 1. Pin Assignments
336
2020·001
Functional
Description
(Continued)
Modo
0
MI
MO
BI
0
0
0
0
0
0
BO
0
2
3
0
0
0
0
4
5
6
7
0
0
0
0
0
1
0
0
0
0
8
0
0
0
9
0
0
1
10
0
11
0
0
Port I
Port 2
Z-BUS
Z-BUS
Z-BUS
Z-BUS
Low
Low
Low
Low
Byte
Byte
Byte
Byte
Z-BUS Low Byte
Non-Z-BUS
3-Wire Handshake
2-Wire Handshake
Z-BUS
Z-BUS
Z-BUS
Z-BUS
High
High
High
High
Byte
Byte
Byte
Byte
Z-BUS High Byte
Non-Z-BUS
3-Wire Handshake
2-Wire Handshake
Non-Z-BUS
Non-Z-BUS
Non-Z-BUS
Non-Z-BUS
Z-BUS Low Byte
Non-Z-BUS
3-Wire Handshake
2-Wire Handshake
Tablo 2. Operating Modes
Z·BUS
N
CHANNEL A
CQ
e
W
00
CHANNEL B
N
...o•
DIJ
PORT 2
<8>
Z8002
PORT 3
<8>
SYSTEM
MEMORY
Z80 BUS
[]
Z80
SYSTEM
MEMORY
MEMORY
110
_
}
HANDSHAKE
SIGNALS
Z·FIO
Z·BUS
Z80 BUS
Figuro 4. CPU to CPU Configuration
2020-002. 003
Figure 5. CPU to 1/0 Configuration
337
Pins Common
To Both Sides
Pin
Signals
Signal
Description
MO
21
19
40
DC power source
GND
20
DC power ground
Pin
Signals
Pin
Names
Pin Numbers
Port
2
ADO-AD7
(Address/Data)
DO-D7
11-18
REQ/WAIT
(RequestIWait)
A
DMASTB
(Direct Memory
Access Strobe)
B
DS
(Data Strobe)
Ml
+5 Vdc
GND
Z-BUS
High Byte
Mode
Pin
Numbers
M1
+5 Vdc
MO
Z-BUS
Low Byte
Mode
Pin
Names
M1 and MO program Port 1
side CPU interface
Signal
Description
29-22
Multiplexed bidirectional address/data lines, Z-BUS
compatible.
39
Output, active Low, REQUEST (ready) line for DMA
transfer; WAIT line (open-drain) output for synchronized CPU and FlO data transfers.
2
38
Input, active Low. Strobes DMA data to and from
the FIFO buffer.
C
3
37
Input, active Low. Provides timing for data transfer to or from FlO.
R/W
(Read/W rite)
D
4
36
Input; active High signals CPU read from FlO;
active Low signals CPU write to FlO.
CS
(Chip Select)
E
5
35
Input, active Low. Enables FlO. Latched on the
rising edge of AS.
AS
(Address Strobe)
F
6
34
Input, active Low. Addresses, CS and INTACK
sampled while AS Low.
INTACK
(Interrupt
Acknowledge)
G
7
33
Input, active Low. Acknowled~ an interrupt.
Latched on the rising edge of AS.
lEO
(Interrupt
Enable Out)
H
8
32
Output, active High. Sends interrupt enable to
lower priority device lEI pin.
lEI
(Interrupt
Enable In)
9
31
Input, active High. Receives interrupt enable from
higher priority device lEO signal.
INT
(Interrupt)
10
30
Output, open drain, active Low. Signals FlO interrupt request to CPU.
Pin
Signals
Pin
Names
Pin Numbers
Port
2
ADO-AD7
(l\.ddress/Data)
Do-D7
11-18
REQ/WAIT
(RequestlWait)
A
DMASTB
(Direct Memory
Access Strobe)
B
DS
(Data Strobe)
Signal
Description
29-22
Multiplexed bidirectional address/data lines, Z-BUS
compatible.
39
Output, active Low, REOUEST (ready) line for DMA
transfer; WAIT line (open-drain) output for synchronized CPU and FlO data transfers.
2
38
Input, active Low. Strobes DMA data to and from the
FIFO buffer.
C
3
37
Input, active Low. Provides timing for transfer of data
to or from FlO.
RIW
(Read/Write)
D
4
36
Input, active High. Signals CPU read from FlO; active
Low signals CPU write to FlO.
CS
(Chip Select)
E
5
35
Input, active Low. Enables FlO. Latched on the
rising edge of AS.
AS
(Address Strobe)
F
6
34
Input, active Lo~ Addresses, CS and INT ACK are
sampled while AS is Low.
AO
(Address Bit 0)
G
7
33
Input, active High. With AI, A2, and A3, addresses
FlO internal registers.
Al
(Address Bit 1)
H
8
32
Input, active High. With AO, A2, and A3, addresses
FlO internal registers.
A2
(Address B,it 2)
9
31
Input, active High. With AO' AI, and A3, addresses
FlO internal registers.
A3
(Address Bit 3)
10
30
Input, active High. With AO' AI, and A2, addresses
FlO internal registers.
Table 3. Signal/Pin Descriptions
338
Non-Z-BUS
Mode
Pin
Signals
Pin
Names
Pin Numbers
Port
4
DO-D7
(Data)
DO-D7
11-18
REQIWT
(RequestlWait)
A
DACK
(DMA Acknowledge)
B
RD
(Read)
Signal
Description
29-22
Bidirectional data bus.
39
Output. active Low. REQUEST (ready) line for DMA
transfer; WAIT line (open-drain) output for synchronized CPU and FlO data transfer.
2
38
Input. active Low. DMA acknowledge.
C
3
37
Input. active Low. Signals CPU read from FlO.
WR
(Write)
D
4
36
Input. active Low. Signals CPU write to FlO.
CE
(Chip Select)
E
5
35
Input. active Low. Used to select FlO.
c/15
F
6
34
Input. active High. Identifies control byte on DO-D7;
active Low identifies data byte on DO-D7.
INTACK
(Interrupt
Acknowledge)
G
7
33
Input. active Low. Acknowledges an interrupt.
lEO·
(Interrupt
Enable Out)
H
(ControVData)
Port 2-1/0
Port Mode
N
00
0
8·
32
Output. active High. Sends interrupt enable to
lower priority device lEI pin.
lEI
(Interrupt
Enable In)
9
31
Input. active High. Receives interrupt enable from
higher priority device lEO signal.
INT
(Interrupt)
10
W
00
N
•
-:I
....
0
Output, open drain. active Low. Signals FlO interrupt
to CPU.
30
Signal
Description
Pin
Signals
Pin
Names
Pin
Numbers
DO-D7
(Data)
DO-D7
29-22
RFD/DAV
(Ready for Data/Data
Available)
A
39
'2-Wire HS
3-Wire HS
ACKIN
(Acknowledge Input)
B
38
2-Wire HS
Input. active Low. Signals FlO that output data is
received by peripherals or that input data is valid.
DAV/DAC
(Data Available/Data
Accepted)
B
38
3-Wire HS
Input; DAV (active Low) signals that data is valid on
bus. DAC (active High) signals that output data is
accepted by peripherals.
FULL
C
37
2-Wire HS
Output. open drain. active High. Signals that FlO
buffer is full.
DAC/RFD
(Data Accepted/Ready
for Data)
C
37
3-Wire HS
Direction controlled by internal programming. Both
active High. DAC (an output) signals that FlO has
received data from peripheral; RFD (an input) signals
that the listeners are ready for data.
EMPTY
D
36
2-Wire HS
3-Wire HS
Output. open drain. active High. Signals that FIFO
buffer is empty.
CLEAR
E
35
2-Wire HS
3-WireHS
Programmable input or output. active Low. Clears all
data from FIFO buffer.
DATA DIR
(Data Direction)
F
34
2-Wire HS
3-Wire HS
Programmable input or output. Active High signals
data input to Port 2; Low signals data output from
Port 2.
INO
G
33
2-Wire HS
3-Wire HS
Input line to DO of Control Register 3.
OUTl
H
32
2-Wire HS
3-Wire HS
Output line from Dl of Control Register 3.
OE
(Output Enable)
31
2-Wire HS
3-Wire HS
Input. active Low. When Low. enables bus drivers.
Whim High. floats bus drivers at high impedance.
OUT3
30
2-Wire HS
3-Wire HS
Output line from D3 of Control register 3.
Mode
2-Wire HS"
3-Wire HS
Bidirectional data bus.
Output. RFD active High2!gnals peripherals that FlO
is ready to receive data. DA V active Low 'signals
that FlO is ready to send data to peripherals.
"Handshake
Table 3. Signal/Pin Descriptions (Continued)
339
Reset
The FlO can be reset under either hardware
or software control by one of the following
methods:
• By forcing both AS and DS Low simultaneously in Z-BUS mode (normally illegal).
• By forcing RD and WR Low Simultaneously
in non-Z-BUS mode.
• By writing a 1 to the Reset bit in Control
register 0 for software reset.
In the Reset state, all contl'ol bits are cleared
to O. Only after clearing the Reset bit (by
CPU
Interfaces
The FlO is designed to work with both
Z-BUS- and non-Z-BUS-type CPUs on both Port
1 and Port 2. The Z-BUS configuration interfaces CPUs with time-multiplexed address and
data information on the same pins. The Z8001,
Z8002, and Z8 are examples of this type of
CPU. The AS (Address Strobe) pin is used to
latch the address and chip select information
sent out by the CPU. The RlW (ReadlWrite)
pin and the DS (Data Strobe) pin are used
for timing reads and writes from the CPU to
ADO-AD7 - - (
A~~~rosS
writing a 0 to it) can the other command bits
be programmed. This action is true for both
sides of the FlO when programmed as a CPU
interface.
For proper system control, when Port 1 is
reset, Port 2 is also reset. In addition, all Port
2's outputs are floating and all inputs are
-ignored. To initiate the data transfer, Port 2
must be enabled by Port 1. The Port 2 CPU
can determine when it is enabled by reading
Control register 0, which reads "floating" data
bus if not enabled and "01 H" if enabled.
the FlO (Figures 6 and 7).
The non-Z-BUS configuration is used for
CPUs where the address and data buses are
separate. Examples of this type of CPU are the
Z80 and 8080. The RD (Read) and WR (Write)
pins are used to time reads and writes from the
CPU to the FlO (Figures 9 and 10); The c/iS
(Control/Data) pin is used to.directly access
the FIFO buffer (C/I5 =0) and to access the
other registers (C/D = 1). Read and write to all
)>--------(
TO CPU
)>------
ruw=:/
\ _____
\I...... _ _--J!
Figure 6. Z-BUS Read Cycle Timing
ADo-AD7
----c(
A~~~FosS H~·
___
-.J»)----
D_A_TA_F_RO_M_C_PU_ _
V
\J
ruw
\
\~-_/
Figure 7. Z-BUS Writo Cycle Timing
340
2020-004, 005
CPU
Interfaces
(Continued)
registers except the FIFO buffer l are two-step
operations, described as follows (Figure 8).
First, write the address (c/iS = 1) of the register
to be accessed into the Pointer Register (State
0); second, read or write (C/D = 1) to the
register pointed at previously (State 1). Continuous status monitoring can be performed in
State 1 by continuous Control· Read operations
(C/D = 1).
RD OR WR
WRTO PTR
(C/O = 1)
(CtO = 0)
RESET = 0
Figure 8. Register Access in Non-Z-BUS Mode
1The FIFO buffer can also be accessed by this two-step operation.
CID_...-JX____________>C:
~----------------------------~( ro~ } - \~
____________~r_
\ _____~I
=
C
W
00
N
Figure 9. Non-Z-BUS Read Cycle Timing
cm
X
X
Do-D7
CE
WR
...C~
FROM CPU
<
}
I
\
\
I
Figure 10. Non-Z-BUS Write Cycle Timing
WAIT
Operation
When data is output by the CPU, the
REQ/WT (WAIT) pin is active (Low) only when
the FIFO buffer is full, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not full.
When data is input by the CPU, the
REQ/WT pin becomes active (Low) only when
the FIFO buffer is empty, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not empty.
Interrupt
Operation
The FlO supports Zilog's prioritized daisy
chain interrupt protocol for both Z-BUS and
non-Z-BUS operating modes (for more details
refer to the Zilog Z-EUS Summary).
Each side of the FlO has seven sources of
interrupt. The priorities of these devices are
fixed in the following order (highest to lowest):
Mailbox Message, Change in Data Direction,
Pattern Match, Status Match, Overflow/
Underflow Error, Buffer Full, and Buffer
Empty. Each interrupt source has three bits
that control how it generates the interrupt.
These bits are Interrupt Pending (IP),
Interrupt Enable (IE), and Interrupt Under
Service (IUS).
In addition, each side of the FlO has an
interrupt vector and four bits controlling the
FlO interrupt logic. These bits are Vector
2020-006, 007, 008
341
Interrupt
Operation
(Continued)
Includes Status (VIS), Master Interrupt Enable
(MIE), Disable Lower Chain (DLC), and No
Vector (NV).
A typical Interrupt Acknowledge cycle for
Z-BUS oPElration is shown in Figure 11 and for
non-Z-BUS operation in Figure 12. The only
difference is that in Z-BUS mode, INTACK is
latched by AS, and in non-Z-BUS mode
INTACK is not latched.
When MIE = 1, reading the vector always
includes status, independent of the state of the
ADO-AD7
VIS bit. In this way, when VIS = 0, all information can be obtained with one additional
read, thus conserving vector space. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified.
In non-Z-BUS mode, the IPs do not get set
while in State 1. Therefore, to minimize interrupt latency, the FlO should be left in State O.
In Z-BUS mode IPS are set by an AS following
the event.
~~------«
VECTOR
»)----
\_____rlEI _ _...J/
INT
/
--------------~
Figure 11. Z-BUS Interrupt Acknowledge Cycle
DO-D7
------------<~)----
\~__---JI
lEI
INT
/
_ _ _.-oJ
/
---------'
Figure 12. Non-Z-BUS Interrupt Acknowledge Cycle
CPU to CPU
Operation
342
DMA Operation. The FlO is particularly well
suited to work with a DMA in both Z-BUS and
non-Z-BUS modes. A data transfer between the
FlO and system memory can take place during
every machine cycle on both sides of the FlO
simultaneously.
In Z-BUS mode, the DMASTB pin (DMA
Strobe) is used to read or write into the FIFO
buffer. The R/W (Read/Write) and DS (Data
Strobe) signals are ignored by the FlO;
however, the CS (Chip Select) signal is not
ignored and therefore must be kept invalid.
Figures 13 and 14 show typical timing.
In Non-Z-BUS mode, the DACK pin (DMA
Acknowledge) is used to tell the FlO that its
DMA request is granted. After DACK goes
Low, every read or write to the FlO goes into
the FIFO buffer. Figures 15 and 16 show
typical timing.
2020-009,010
CPU
to
CPU
Operation
(Continued)
AID BUS
DATA FROM FlO TO MEMORY
1
\ \ - -_ _- - J
RlW
\ ______1
Figure 13. Z-BUS flO to Memory Data Transaction
AID BUS
DATA FROM MEMORY TO FlO
DS
\ ' - -_ _ _- - - - - - ' ,
RlW
\ ___1
DMASTB
Figure 14. Z-BUS Memory to flO Data Transaction
ADDRESSES
===><_____
M_E_M_O_RY_A_D_D_R_ES_S_O_F_W_R_IT_E____
-J)(~______________________
---I>--
D:~: --------C(DATA FROM FlO TO MEMORY}----(,,_____________
MEMORY
WRITE
110
READ
DACK ~~____________________________________________________
Figure 15. Non-Z-BUS FlO to Memory Transaction
ADDRESSES
===><
MEMORY ADDRESS OF READ
DATA _______~(
BUS
MEMORY~
READ
DATA FROM
MEMORY TO FlO
x~
________________________
»)--~(------I>-
/
\".__________--J.
\_-----1
DACK ~~_ _ _ _ _ _ _ _ _ _~____________________
Figure 16. Non-Z-BUS Memory to FlO Data Transaction
2020-011, 012, 013, 014
343
CPU to CPU
Operation
(Continued)
The FlO provides a special mode to enhance
its DMA transfer capability. When data is
written into the FIFO buffer, the REQ/WT
(REQUEST) pin is active (Low) until the FIFO
buffer is full. It then goes inactive and stays
inactive until the number of bytes in the FIFO
buffer is equal to the value programmed into
the Byte Count Comparison register. Then the
REQUEST signal goes active and the sequence
starts over again (Figure 17).
When data is read from the FlO, the
REQIWT pin (REQUEST) is inactive until the
number of bytes in the FIFO buffer is equal to
the value programmed in the Byte Count Comparison register. The REQUEST signal then
goes active and stays active until the FIFO buffer is empty. When empty, REQUEST goes
inactive and the sequence starts over again
(Figure 18).
REO
(]
--"""0
ACTIVE .......;4~....- - r - -.....
CD
CD
ACTIVE
....
INACTIVE ---::~--""""";"'-"'--.....J-
--\----_1-----...-04-
INACTIVE
NUMBER OF BYTES IN FIFO
FULL
EMPTY
CD
(]
CD
.....:::+---___----+=--.,---FJLL
EMPTY
NUMBER IN BYTE COUNT COMPARISON REGISTER
NUMBER IN BYTE COUNT COMPARISON REGISTER
NOTES:
1. FIFO empty.
2. REQUEST enabled, FlO requests DMA transfer.
3. DMA transfers data into the FlO.
4. FIFO fun, REQUEST inactive.
5. The FIFO empties from the opposite port until the number
of bytes in the FIFO buffer is the same as the number programmed in the Byte Count Comparison register.
NOTES:
1. FIFO empty.
2. CPU/DMA fills FIFO buffer from the opposite port.
3. Number of bytes in FIFO buffer is the same as the number
of bytes programmed in the Byte Count Comparison register.
4. REQUEST goes active.
5. DMA transfers data out of FIFO until it is empty.
Figure 17. Byte Count Control: Write to flO
Figure 18. Byte Count Control: Read from FlO
interrupted. Port 2' s message IP status is
readable from the Port 1 side. When Port 2's
CPU reads the data from its Message In register, the Port 2 IP is cleared. Thus, Port l's
CPU can read when the message has been
read and can now send another message or
follow whatever protocol that is set up between
the two CPU's. The same transfer can also be
made from Port 2' s CPU to Port l' s CPU.
Message Registers. Two CPUs can communicate through a dedicated "mailbox" register
without involving the 128 X 8 bit FIFO buffer
(Figure 19). This mailbox approach is useful
for transferring control parameters between
the interfacing devices on either side of the
FlO without using the FIFO buffer. For
example, when Port l's CPU writes to the
Message Out register, Port 2's message IP is
set. If interrupts are enabled, Port 2's CPU is
PORT 1
MESSAGE OUT
REGISTER
<
REGISTER
ADDRESS
"C"
..t!
\
vi
::..
PO RT 1
MESS AGEIN
REG ISTER
MESSAGE
REGISTER
PORT 1
TO
PORT 2
-
REGISTER
ADDRESS
"B"
PORT 2
MESSAGE IN
REGISTER
MESSAGE
REGISTER
REGISTER
ADDRESS
"B"
PORT 2
TO
PORT 1
-
NOTE: Usable only for CPU/CPU interface.
Figure 19. Message Register Operation
344
2020-015,016.017
CPU to CPU
Operation
(Continued)
CLEAR (Empty) FIFO Operation. The CLEAR
FIFO bit (active Low) clears the FIFO buffer of
data. Writing a 0 to this bit empties the FIFO
buffer, inactivates the REQUEST line, and
disables the handshake (if programmed). The
CLEAR bit does not affect any control or data
register. To remove the CLEAR state, write a 1
to the CLEAR bit.
In CPU/CPU mode, under program control,
only one of the ports can empty the FIFO by
writing to its Control Register 3, bit 6. The
Port 1 CPU must program bit 7 in Control .
Register 3 to determine which port controls the
CLEAR FIFO operation (0 = Port 1 control;
1 = Port 2 control).
Direction of Data Transfer Operation. The
Data Direction bit controls the direction of data
transfer in the FIFO buffer. The Data Direction
bit is defined as 0 = output from CPU and
1 = input to CPU. This bit reads correctly
when read by either port's CPU. For example,
if Port l's CPU reads a 0 (CPU output) in its
Data Direction bit, then Port 2's CPU reads a 1
(input to CPU) in its Data Direction bit.
In CPU/CPU mode, under program control,
only one of the ports can control the direction
of data transfer. The Port 1 CPU must program
bit 5 in Control Register 3 to determine which
port controls the data direction (0 = Port 1
control; 1 = Port 2 control). Figure 20 shows
FlO data transfer options.
ESI
eo
o
w
00
N
....o~
(PROGRAM REGISTERS FOR OPERATING MODE,
PORT 2 CONFIGURATION, DATA TRANSFER CONTROL, ETC.)
PORT 1 (CPU)
PORT 2 (CPU)
PORT 2 (110)
(DMA OR INTERRUPT·
DRIVEN TRANSFERS, AS
FOR PORT 1)
TRANSFERS DATA BYTE·
AT·A·TIME UNTIL
FIFO BUFFER IS
Full OR Empty
EXCHANGE BYTES
VIA MESSAGE REGISTER
I
I
I
t
TERMINATES ON ANY
OF THESE CONDITIONS:
·DMA BLOCK LENGTH REGISTER = 0
·FIO PATTERN MATCH INTERRUPT
·BYTE COUNT DISABLES REO
TERMINATES ON ANY
OF THESE CONDITIONS:
·CPU COMPLETES BUFFER DUMP
·FIO PATTERN MATCH INTERRUPT
·FIO BYTE COUNT INTERRUPT
·FIO Full I Empty INTERRUPT
I
I
I
l,
........
......
,,
.......-
I
I
I
I
.......-
y
I
I
I
.... )
.......-~
I
I
I
I
I
EXCHANGE BYTES
VIA MESSAGE REGISTERS
-----------
\
/
Y
t
I
I
1
1
I
1
I
I
·1
I
1
1
1
1
CONTINUE OR REPROGRAM PORT REGISTERS WITH NEW BLOCKS OF CONTROL BYTES.
Figure 20. flO Data Transfer Options
2020·018
345
CPU to I/O
Operation
, When Port 2 is programmed in the Interlocked 2-Wire Handshake mode or the 3-Wire
Handshake mode, and Port A is programmed
in 2-BUS or non-2-BUS Microprocessor mode,
the FlO interfaces a CPU and a peripheral
device. In the Interlocked 2-Wire Handshake
mode, RFD/DA V and ACKIN strobe data to
and from Port 2. In the 3-Wire Handshake
mode, RFD/DAV, DAVlDAC, and DAC/RFD
signals control data flow.
Interlocked 2-Wire Handshake. In the Interlocked Handshake, the action of the FlO must
be acknowledged by the other half of the
handshake before the next action can take
place. In output mode, Port 2 does not indicate
that new data is available until the external
device indicates it is ready for the data.
Similarly, in input mode, Port 2 does not indi~
cate that it is ready for new data until the data
source indicates that the previous byte of the
data is no longer available, therebyacknowledging Port 2's acceptance of the last byte.
This allows the FlO to directly interface to a
28's port, a CIO's port, a UPC's port, another
FlO port, or another FIFO 28060, with no
external logic (Figures 21 and 22).
3-Wire Handshake. The 3-Wire Handshake is
designed for applications in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate that an input port is ready
for new data or that it has accepted the present
data. In the 3-Wire Handshake, the rising
edge of the RFD status line indicates that the
port is ready for data, and the rising edge of
the DAC status line indicates that the data has
been accepted. With 3-Wire Handshake, the
lines of many input ports can be bussed
together with open-drain drivers and the out-
346
put port knows when all of the ports are ready
and have accepted the data. This handshake is
the same handshake used in the IEEE-488
Instruments. Since the port's direction can be
changed under software control, bidirectional
IEEE-488-type transfers can be performed.
Figures 23 and 24 show the timings associated
with 3-Wire Handshake communications.
CLEAR FIFO Operation. In CPU-to-I/O
operation, the CLEAR FIFO operation can be
performed by the CPU side (Port 1) under software control as previously explained. The
CLEAR FIFO operation can also be performed
under hardware control by defining the
CLEAR pin of Port 2 as an input (Control
Register 3, bit 7 = 1).
__
For cascading purposes, the CLEAR pin can
also be defined as an output (Control Register
3, bit 7 = 0)' which reflects the current state
of the CLEAR FIFO bit. It can then empty
other FIOs or initialize other devices in the
system.
Data Direction Control. In CPU-to-I/O mode,
the direction of data transfer can be controlled
by the CPU side (Port 1) under software control as preViously explained. The data direction can also be determined by hardware control by defining the Data Direction pin
of Port 2 as an input (Control Register 3,
bit 5 = 1).
For cascading purposes, the Data Direction
pin can also be defined as an output (Control
Register 3, bit 5 = 0) pin which reflects the
current state of the Data Direction bit. It can
then be used to control the direction of data
transfer for other FIOs or for external logic.
On the Port 2 side, when data direction is 0,
Port 2 is in Output Handshake mode. When
data direction is I, Port 2 is in Input Handshake mode.
CPU to I/O
Operation
(Continued)
DATA IN
=:x
VALID DATA
,
\
ACKIN
RFD
X
1
X
X
'-----I
'-----I
VALID DATA
/
Figure 21. Interlocked Handshake Timing (Input) Port 2 Side Only
=:x
DATA OUT
VALID DATA
x'-___..JX
VALID DATA
X'-____
' ___I
,------'/
Figure 22. Interlocked Handshake Timing (Output) Port 2 Side Only
DATA IN
~~
:=:x:
X
VALID DATA
J'
D~~
X
/
1
\
VALID DATA
X'-____
,'-_____
'----I
DAC
OUT _ _ _ _ _ _ _- - '
Figure 23. Input (Acceptor) Timing IEEE-488 HS Port: Port 2 Side Only
DATA OUT
:=:x:
Dtu~
X",___X
VALID DATA
\
VALID DATA
X'-_____
/
DAC
IN _ _ _ _ _ _ _- - '
RFD
IN
--f
' ____---'1
,'------
Figure 24. Output (Source) Timing IEEE-488 HS Port: Port 2 Side Only
2020-019,020,021,022
347
Programming
The programming of the FlO is greatly
simplified by the efficient grouping of the
various operation modes in the control
registers. Since all of the control registers are
read/write, the need for maintaining their
image in system memory is eliminated. Also,
the read/write feature of the registers aids in
system debugging.
Each side of the FlO has 16 registers. All 16
registers are used by the Port 1 side; Control
register 2 is not used on the Port 2 side. All
registers are addressable OH through FH.
In the Z-BUS Low Byte mode, the FlO allows
two methods for register addressing under control of the Right Justify Address (RJA) bit in
Control register O. When RJA = a, address
bus bits 1-4 are used for register addressing
and bits I, 5, 6, and 7 are ignored (Table 4).
When RJA = I, bits 0-3 are used for the
register addresses, and bits 4-7 are ignored.
Control Registers. These four registers specify
FlO operation. The Port 2 side control
Non Z-iJUS
D7- D4
Z-BUS High
Z-BUS Low
AD7-ADS
{ RJA=O
RJA= 1
A~-AD4
registers operate only if the Port 2 device is a
CPU. The Port 2 CPU can control interface
operations, including data direction, only
when enabled by the setting of bit a in the Port
1 side of Control Register 2. A 1 in bit 1 of the
same register enables the handshake logic.
Interrupt Status Registers. These four
registers control and monitor the priority
interrupt functions for the FlO.
Interrupt Vector Register. This register stores
the interrupt service routine address. This vector is placed on Do-D7 when IUS is set by the
Interrupt Acknowledge Signal from the CPU.
When bit 4 (Vector Includes Status) is set in
Control Register a, the reason for the interrupt
is encoded within the vector address in bits I,
2, and 3. If bit 5 is set in Control register a, no
vector is output by the FlO during an Interrupt
Acknowledge cycle. However, IUS is set as
usual.
Da
D2
Dl
DO
Aa
A2
Al
Ao
AD4
ADa
ADa
AD2
AD2
ADI
ADI
ADo
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
ADo
Description
Contr9l Register
a
Control Register 1
Interrupt Status Register
x
a
x
x
Interrupt Status Register 1
x
Interrupt Status Register 2
x
Interrupt Status Register 3
x
Interrupt Vector Register
x
Byte Count Register
x
a
a
x
a
x
1
x
a
x
a
x
x
x
Byte Count Comparison
Register
x
a
Control Register 2"
x
0
Control Register 3
x
Message Out Register
x
a
a
1
1
x
Message In Register
x
0
a
x
Pattern Match Register
x
a
Pattern Mask Register
x
Data Buffer Register
x
x =Don't Care
"Register is only on Port I side
Table 4. FlO Register Address Summary
348
x
a
a
a
x
1
x
a
x
x
0
x
x
Programming Byte Count Compare Register. This register
(Continued)
contains a value compared with the byte count
in the Byte Count register. If the Byte Count
Compare interrupt is enabled, an interrupt will
occur upon compare.
Message Out Register. Either CPU can place
a message in its Message Out register. If the
opposite side Message register interrupt is
enabled, the receiving side CPU will receive
an interrupt request, advising that a message
is present in its Message In register. Bit 5 in
Control Register 1 on the initiating side is set
when a message is written. It is cleared when
the message is read by the receiving CPU.
Message In Register. This register receiv~s a
message placed in the Message Out register by
the opposite side CPU.
Pattern Match Register. This register contains
a bit pattern matched against the byte in the
Data Buffer register. When these patterns
match, a Pattern Match interrupt will be
generated, if previously enabled.
Pattorn Mask Registor. The Pattern Mask
register may be programmed with a bit pattern
mask that limits comparable bits in the Pattern
Match register to non-masked bits (l = mask).
Data Buffer Register. This register contains
the data to be read from or written to the
FIFO buffer.
Byte Count Register. This is a read-only
register, containing the byte count for the
FIFO buffer. The byte count is derived by subtracting the number of bytes read from the buffer from the number of bytes written into the
buffer. The count is "frozen" for an accurate
reading by setting bit 6 (Freeze Status register)
in Control Register 1. This bit is cleared when
the Byte Count register read is completed.
e
w
00
N
•
tIS
...o
Z·BUS
1/ ....--"'--' '\ TO
COMM.
I ' \ r - - , / LINE
Z·BUS
MASTER
CPU
NOTES:
1. Data from master CPU - Z-FIO Port 2.
2. Z-FIO Port 1 -DCP.
3. DCP -RAM.
4. RAM -Z-SCC.
5. Z-SCC - data comm. line loop.
Figure 25. Typical Application: Node Controller
2020-033
N
00
349
E
Control Register 0
Address: 0000
(ReadlWrite)
Control Register 2*
Address: 1001
(ReadlWrite)
ID,ID,I~ c4~1"'I"'I"~,="",
51D
I~I~I~I~I~I~I~I~I
.
~
g
~
1 _
0
1
.
= Z·BUS CPU
= NON Z U
.
= 3.WIR/H ; CPU }
=
HS
INTERLOC~'i'D
~ ;: 'a'" """.."'"
I
1 = RT . J UST. ADDRESS (
(Bll (Bol"
RJA)
- PORT 2 SIDE ENABLE
FRO~I~~ERRTREADS
"THIS RE
O'S
PROGRAMS
PORT 2 MODE
PROGRA~MED
BITS 2-7 NOT USE
ALL
MUST BE
2 SIDE
HANDSHAKE
0
- VECTOR INCLUDES
1 = NO VECTQjl
STATUS (VIS)
1 = DISABLE LO;N INTERRUPT (NV)
1 = INTERRU
ER DAISY CHAIN (DLC)
PTS ENABLED (MIE)
Control Register 3
Address: 10 10
(ReadlWrite)
Control Register 1
Address: 0001
(ReadIW rite)
0
1
00
1 ,1
0 0
,1 lli§51
~41D
~31D
~21~IID~
L PORT
2 SIDE-INPUT
PORT 2 SIDE
LINE" (PIN 33)""
~'IO
~~ID
~410
ll;31"~'
111: ="a""""",..,,,"
NOT USED
0
,1
DATA
1 = START DMA
1 = STOP OM
ON BYTE COUNT
-
:=
.
A ON PATTERN MATCH
GE MAILBOX
: MESSAGE MAILBOX
UNDER SERVICE"
"~~AD.ONLY
"
ER FULL"
NOT USED (MUST B E
S PROGRAMMED
REGISTER COUNT
0)
O=PORT 1 SIDE
BITS
1 =PORT 2 SIDE ggNTROLS CLEAR
NTROLS
NLY WHEN PO
RT 2 IS AN ItO PORT
Control Registers
Interrupt
.
0
AddStatus RegIster·
ress: 0010
(ReadlWrite)
Irl'II""""""~
I
I
CPU
cg~~:g~~ DATA DIRECTION
- CLEAR FIFO BUFFER
:::::~ER
_ FREEZE STATU
"READ.ONLY BITS
TPUT LINE (PIN 30)""
F~6~
O=OUTPUT
0= PORT 1 SIDE C
PORT 2 SIDE
1 = MESSA
~
O~T BE PROGRAMMED 0)
DIREC~IO
1 = INPUT TO N BIT
= WAIT
1 = REQUEST
,
(~~UTPUT LINE (PIN 32)""
PORT 2 SIDE
I
NOT USED
~:UST BEPROGRAMMED 0)
SSAGE INTERRUPT
MESSAGE INTER
PENDING (lP)
RUPT EN
~OWRITTEN USING
IUS, IE, AND IP A
THE FOLLOWING
NULL CODE
MESSAGE INTERRUPT UNABLE (IE)
DER SERVICE (IUS)
MMAND:
CLEAR IP & IUS
SET IUS
1
CLEAR IUS
o
SET IP
Figure 27" Interrupt Status Registers
Registers
(Continued)
Interrupt Status Register 1
Address: 00 11
(Read/Write)
ID, I D,I Ds
DATA DIRECTION CHANGE INTERRUPT
UNDER SERVICE (IUS)
iJ I
III~L, - •.,.,,," .,"" "".
I
DATA DIRECTION CHANGE INTERRUPT
ENABLE (IE)
I
I
I
,
I
I
! D41 D31 D, I D, I Do
PATTERN MATCH INTERRUPT PENDING (IP)
I
PATTERN MATCH INTERRUPT ENABLED (IE)
I
PATTERN MATCH INTERRUPT
UNDER SERVICE (IUS)
DATA DIRECTION CHANGE INTERRUPT
PENDING (IP)
' - - - - - - NOT USED
(MUST BE PROGRAMMED 0)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE
0
CLEAR IP & IUS
0
0
SET IUS
0
1
CLEAR IUS
0
1
1
0
SET IP
1
0
CLEAR IP
1
0
SET IE
1
1
CLEAR IE
1
1
o
o
o
o
0
0
NULL CODE
0
1
CLEAR IP & IUS
1
0
SET IUS
1
1
CLEAR IUS
1
0
0
1
0
1
1
1
1
1
SET IP
CLEAR IP
SET IE
1
CLEAR IE
'RE"D·ONLY BITS
Interrupt Status Register 2
Address: 0100
(Read/W rite)
I0, I0,
BYTE COUNT COMPARE INTERRUPT
UNDER SERVICE (IUS)
iJ I
t
I
I
BYTE COUNT COMPARE INTERRUPT
ENABLE (IE)
I
BYTE COUNT COMPARE INTERRUPT
PENDING (IP)
lblli~
L
I
I
I
I
L UNDERFLO~ ERROR'
0,1 0 4 t D3l 0, I D, I Do
I
I
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
ERROR INTERRUPT PENDING (10)
ERROR INTERRUPT ENABLED (IE)
I
I
ERROR INTERRUPT UNDER SERVICE (IUS)
I
I
OVERFLOW ERROR'
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
NULL CODE
0
0
CLEAR IP & IUS
0
0
SET IUS
0
1
CLEAR IUS
0
1
1
SET IP
1
0
0
CLEAR IP
1
0
SET IE
1
1
CLEAR IE
1
1
0
1
o
0
0
NULL CODE
o
0
1
CLEAR IP & IUS
o
o
1
0
SET IUS
1
1
CLEAR IUS
1
0
0
1
0
1
1
1
1
SET IP
CLEAR IP
SET IE
1
CLEAR IE
'READ·ONLY BITS
Interrupt Status Register 3
Address: 0101
(Read/Write)
I0, I0, i Ds
'"" ,",,","no"," "'''''''"''
FULL INTERRUPT ENABLE (IE)
~~I I
I
I
FULL INTERRUPT PENDING (IP)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
I 0 4 i 0 3 1 0, I D, I Do
lblli~
~
I
NULL CODE
0
CLEAR IP & IUS
0
0
0
I
' L BUFFER EMPTY'
I
I
I
I
EMPTY INTERRUPT PENDING (IP)
EMPTY INTERRUPT ENABLE (IE)
EMPTY INTERRUPT UNDER SERVICE (IUS)
BUFFER FULL'
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:
0
1
SET IUS
1
0
0
1
1
o
o
0
CLEAR IUS
0
1
NULL CODE
CLEAR IP & IUS
SET IP
1
0
0
o
1
0
SET IUS
CLEAR IP
1
0
1
o
1
1
CLEAR IUS
1
0
0
SET IP
CLEAR IP
SET IE
1
1
0
CLEAR IE
1
1
1
1
0
1
1
1
0
SET !E
1
1
1
CLEAR IE
• READ·ONL Y BITS
Figure 27. Interrupt Status Registers (Continued)
2020·024
351
Registers
( Continued)
Byte Count Register
Address: 0111
(Read Only)
Interrupt Vector Register
Address: 0110
(ReadJW rite)
10710.1 0 10.1 0 10,1 0, I0.1
5
3
I I I I
I I I I I I I I
REFLECTS NUMBER OF BYTES IN BUFFER
NO INTERRUPTS PENDING
BUFFER EMPTY
Figure 28. Byte Count Register
BUFFER FULL
VECTOR STATUS
OVER/UNDERFLOW ERROR
BYTE COUNT MATCH
1
PATTERN MATCH
1
0
1
DATA DIRECTION CHANGE
1
1
0
MAILBOX MESSAGE
1
1
1
Figure 29. Interrupt Vector Register
Pattern Match Register
Address: II 0 1
(ReadJWrite)
Pattern Mask Register
Address: 1110
(ReadJWrite)
I~I~I~I~I~I~I~I~I
10710.1 0,1 0.\ 0 0,\ 0, \0.1
II I I I I I I
II I I I I I I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER
3 \
IF SET, BITS 0·7 MASK BITS 0-7
IN PATTERN MATCH REGISTER.
MATCH OCCURS WHEN ALL
NON·MASKED BITS AGREE.
Figure 30. Pattern Match Register
Figure 31. Pattern Mask Register
Data Buffer Register
Address: 1111
(ReadJWrite)
Byte Count Comparison Register
Address: 1000
(ReadJWrite)
107\ 0.\ 0 0.\ 0 0,\ 0, 1.0.1
I I I I I I I I
I~I~I~\~\~I~I~I~I
CONTAINS THE BYTE TRANSFERRED
TO OR FROM FIFO BUFFER RAM
CONTAINS VALUE COMPARED TO BYTE COUNT
REGISTER TO ISSUE INTERRUPTS ON MATCH
.
(BIT 7 ALWAYS 0.)
5 \
I I I I I I I I
Figure 32. Data Buffer Register
Figure 33. Byte Count Comparison Register
Message Out Register
Address: 10 11
(ReadJWrite)
Message In Register
Address: 1100
(Read Only)
I~I~I~I~I~I~I~I~I
I~!~!~!~I~I~I~I~I
I I I I
352
3\
II I I
II I I I I I I
STORES MESSAGE SENT TO MESSAGE
IN REGISTER ON OPPOSITE PORT OF FlO
STORES MESSAGE RECEIVED FROM MESSAGE
OUT REGISTER ON OPPOSITE PORT OF CPU
Figure 34. Message Out Register
Figure 35. Message In Register
2020·025,026,027,028,029,030,031,032
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. ooe to + 70°C
Storage Temperature ........ -65°C to + 150 °e
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
c +4.75 V ~ Vee ~ +5.25 V
GND = 0 V
Ell TA as specified in Ordering Information
Ii
+5V
+5V
2.2K
dr
2.2K
FROM OUTPUT
UNDER TEST
50 PF
Open.Drain Test Load
Standard Test Load
DC
Characteristics
Symbol
Parameter
Min
Max
Unit
2.0
Vcc +0.3
0.8
V
Condition
VIH
Input High Voltage
V1L
VOH
Input Low Voltage
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
-10.0
IaL
ILM
Output Leakage
-10.0
+ 10.0
p,A
IOL = +3.2 rnA
0.4 ::; VIN ::; + 2.4V
0.4 ::; VOUT ::; +2.4V
Mode Pins Input Leakage
(Pins 19 and 21)
-100
+ 10.0
p,A
O
W
CO
N
...o•
~
RD/WR
READ/WRITE OF DATA
BUFFER REGISTER
I~--~CD)-----I
WR,/RD1
WRITE/READ OF DATA
BUFFER REGISTER
BY OTHER SIDE
ACKIN
INPUT/OUTPUT PORT
DATA FROM FlO
FlO WRITE TO DATA
BUFFER REGISTER
--)t~-:- - - Figure 45. Non-Z-BUS Request/Wait Timing
2020-043
361
AC Characteristics
No.
Symbol
Parameter
Min
100
100
500
TdWR(RD)
Delay from WR f to RD !
2
TdRD(WR)
Delay from RD f to WR !
3
TwRD + WR
Width of RD and WR, both Low for Reset
4MHz
Max
6 MHz
Min
Max
Notes*t
70
70
350
NOTES:
• Timings are preliminary and subject to change.
r Units in nanoseconds (ns).
Figure 46. Non-Z-BUS Reset Timing
AC Characteristics
No.
4MHz
Max
6MHz
Min
Max
Symbol
Parameter
Min
700
700
a
a
TwCLR
Width of Clear to Reset FIFO
2
TdOE(DO)
OE ! to Data Bus Driven
3
TdOE(DRZ)
OE f to Data Bus Float
Notes*t
NOTES:
• Timings are preliminary and subject to change.
r Units in nanoseconds (ns).
CLEAR~~¥
INPUT
/
DATA OUT
Figure 47. Port 2 Side Operation
I
/
362
2020·044, 045
AC Characteristics
No.
2
Symbol
Min
Parameter
.TsDI(ACK)
Data Input to ACKIN I to Setup Time
TdACKf(RFD)
ACKIN I to RFD I Delay
RFD 1 to ACKIN I Delay
TdRFDr(ACK)
3
4-TsDO(DAV)--Data Out to DAV I Setup Time
4MHz
Max
500
50
a
a
500
25
5
TdDAVf(ACK)
DA V I to ACKIN I Delay
a
a
6
ThDO(ACK)
Data Out to ACKIN Hold Time
50
50
TdACK(DAV)
ACKIN I to DA V 1 Delay
7
8-ThDI(RFD)--Data Input to RFD I Hold Time
a
a
a
500
a
a
a
500
a
a
400
a
a
400
9
TdRFDf(ACK)
RFD I to ACKIN 1 Delay
10
TdACKr(RFD)
ACKIN 1 (DAV I) to RFD 1 Delay-Interlocked and
3-W ire Handshake
11
TdDAVr(ACK)
DAV 1 to ACKIN 1 (RFD I)
12-TdACKr(DAV)-ACKIN 1 to DAV I
13
TdACKf(Empty) ACKIN I to Empty
14
TdACKf(Full)
ACKIN I to Full
15
TcACK
ACKIN Cycle Time
Notes*t
50
50
a
a
6 MHz
Max
Min
0--800
0--800
N
CO
a
a
a
a
W
CO
C
lSI
....IIa:IC•
NOTES:
• Timings are preliminary and subject to change.
t Units in nanoseconds (ns), except as noted.
1. Units in microseconds.
DATA
EMPTY
~\'------
FULL
Figure 48. 2-Wire Handshake (Port 2 Side Only) Output
DATA
=>t
VALID DATA
-cD-
RFD
I~.r---------~®~--------~~I
EMPTY
FULL
~I~k---_Figure 49. 2-Wire Handshake (Port 2 Side Only) Input
2020-046, 047
363
I
AC Characteristics
No.
Symbol
Parameter
Min
1
TsDI(DAV)
Data Input to DA V f Setup Time
50
2
TdDAVIf(RFD)
DA V f to RFD f Delay
3
TdDAVf(DAC)
DAV f to DAC t Delay
a
a
a
a
a
a
a
4-ThDI(DAC)--Data In to DAC t Hold Time
5
TdDACIr(DAV)
DAC t to DA V t Delay
6
TdDAVIr(DAC)
DAV t to DAC f Delay
7
TdDAVIr(RFD)
DA V t to RFD t Delay
8-TdRFDI(DAV)-RFD t to DAV f Delay
9
TsDO(DAC)
4 MHz
Max
6 MHz
Min
Max
Notes*t
50
500
a
a
a
a
a
500
0
500
500
500
500
500
500
a
Data Out to DAV f
10
TdDAVOf(RFD) DA V f to RFD f Delay
11
TdDAVOf(DAC) DAV f to DAC t Delay
a
a
a
a
12-ThDO(DAC)--Data Out to DAC t Hold Time - - - - - - - - - - - - - - - - - - - - - - - 13
TdDACOr(DAV) DAC t to DAV t Delay
14
TdDAVOr(DAC) DAV t to DAC f Delay
15
TdDAVOr(RFD) DAV t to RFD t Delay
a
a
16
TdRFDO(DAV)
RFD t to DAV f Delay
a
400
800
400
a
a
a
800
NOTES:
• Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
(
PIN)
38
DAV
INPUT
PIN)
( 39
OUTPUT
PIN)
( 37
OUTPUT _ _ _ _ _ _ _~
RFD
DAC
Figure 50. 3-Wire Handshake Input
C:''r:'
~----DA-TA-V-AL-ID----il
DAC
, INPUT
RI'D
INPUT
( PIN)
39
DiY
OUTPUT
Figure 51. 3-Wire Handshake Output
364
2020-049
Ordering
Information
Product
Number
Z8038
Z8038
Package/
Temp
Speed
Description
Product
Number
Description
CE
4.0 MHz
Z-FIO (40-pin)
Z8038A
CM
6.0 MHz
Z-FIO (40-pin)
CM
4.0 MHz
Same as above
Z8038A
CMB
6.0 MHz
Same as above
Same as above
Z8038
CMB
4.0 MHz
Same as above
Z8038A
CS
6.0 MHz
Z8038
CS
4.0 MHz
Same as above
Z8038A
DE
6.0 MHz
Same as above
Z8038
DE
4.0 MHz
Same as above
Z8038A
DS
6.0 MHz
Same as above
Z8038
DS
4.0 MHz
Same as above
Z8038A
PE
6.0 MHz
Same as above
Z8038
PE
4.0 MHz
Same as above
Z8038A
PS
6.0 MHz
Same as above
Z8038
PS
4.0 MHz
Same as above
NOTES: C = Ceramic, D = Cerdip, P = Plastic; E
with Class B processing, S = O°C to +70°C.
00-202()'()2
Package/
Temp
Speed
= -40°C to
+85°C, M
= 55°C to
+ 125°C, MB
= -55°C to
l25°C with MIL-STD-883
365
~$«l)~@
~~t!D@«DTM ~~j§1ll1r(Q)
Qi'ffi1fifi amwll
lmtmffer
~ujjrTJlI@ ~i!R»aBider
Ir>R'«D«il \Ul~R
~peccllgfi(.CtWiln@llLl
September 1983
Features
lJ
Bidirectional, asynchronous data transfer
capability
El
Large 128-bit-by-8-bit buffer memory
[J
Two-wire, interlocked handshake protocol
c Wire-ORing of empty and full outputs for
[] 3-state data outputs
[J
Connects any number of FIFOs in series to
form buffer of any desired length
C
Connects any number of FIFOs in parallel
to form buffer of any desired width
sensing of multiple-unit buffers
General
Description
The Z8060 First-In First-Out (Z-FIFO) Buffer
Unit consists of a 128-bit-by-8-bit memory,
bidirectional data transfer and handshake
logic. The structure of the Z-FIFO unit is
similar to that of other available buffer units.
Z-FIFO is a general-purpose unit; its handshake logic is compatible with that of other
members of Zilog's Z8 and Z8000 Families.
Z-FIFOs can be cascaded end-to-end without
limit to form a parallel 8-bit buffer of any
7
0
-0
6
III
"
_05
AlB
DATA
BUS
-
1
_
_
CONTROL
:
o. -
03
I
O
2
Z8060
03 _
O2 -
0,
0,_
-Do
I
00-
~
ACKIN
I
_
RFOIDAV : RFOIDAV _
OUTPUT
I
ACKIN _
-
E~~~.L ~~~E
OIRAIB
}
CONTROL
"
-
EMPTY
CLEAR
FULL
+5V
RFOIDAVB
ACKINB
CLEAR
DEA
OIRA/B
OOA
DEB
D'A
Dos
D2A
018
D3A
D2S
D4A
D3B
DSA
DOB
D6A
DSB
D7A
D6S
GND
D7B
GNO
Figure 1. FIFO Pin Functions
2123-001,002
ACKINA
EMPTY
FULL
+5V
RFO/OAVA
DATA
BUS
OUTPUT
_
_
"
00
Flr O
{
COMMON
CONTROL {
o.
7
__ )
6
05 _
desired length (in 128-byte increments). Any
number of single- or multiple-unit Z-FIFO
serial buffers can be connected in parallel to
form buffers of any desired width (in 8-bit
increments) .
The Z-FIFO buffer units are available d~
28-pin packages. Figures 1 and 2 show the pin
functions and pin assignments, respectively, of
the Z-FIFO"device. A block diagram is shown
in Figure 3.
Figure 2. FIFO Pin Assignments
367
General
Description
(Continued)
DATA , ' - - _..... ,
BUS
A
DATA
BUS
I
'_-_II
CONTROL , ......._
AND
STATUS
..on
B
, , - - - , CONTROL
AND
STATUS
I
Figure 3. Functional Block Diagram
Pin
Descriptions
Functional
Description
ACKIN. Acknowledge Input (input, active
Low). This line signals the FIFO that output
data has been received by peripherals or that
input data is valid.
CLEAR. Clear Buffer (input, active Low).
When set to Low, this line causes all data to be
cleared from the FIFO buffer.
Do-I>,. Data Bus (inputs/outputs, bidirec ..
tional). These bidirectional lines are used by
the FIFO to receive and to transmit data.
DIR AlB. Direction Input AlB (input, two con ..
trol states). A High on tHis line signals that
input data is to be received at Port B. A Low
on this line signals that input data is to be
received at Port A.
EMPTY. Buffer Status (output, active High,
open .. drain). A High on this line indicates that
the FIFO buffer is empty.
FULL. Buffer Status (output, active High,
open .. drain). A High on this line indicates that
the FIFO buffer is full.
OEA" OEB. Output Enable A, Output Enable
B (inputs, active Low). When Low, OEA
enables the bus drivers for Port A;' when High,
OEA causes the bus drivers to float to a high ..
impedance level. Input OEB controls the bus
drivers for Port B in the same manner as OEA
controls those for Port A.
RFD/DAV. Ready.. /or..DataIData Available
(outputs RFD, active High; DAV active Low).
RFD, when High, signals to the peripherals
involved that the FIFO is ready to receive
data. DAV, when Low, signals to the
peripherals involved that FIFO has data
available to send.
cates that the previous byte of the data is no
longer available, thereby acknowledging the
acceptance of the last byte. This control
feature allows the FIFO, with no external
logiC, to directly interface wi'th the port of any
CPU in the 28 Family-a CIO, a UPC, an FlO,
or another FIFO. The timing for the input and
output handshake operations is shown in
Figures 4 and 5, respectively.
Interlocked 2-Wire Handshake. In inter ..
locked 2 .. wire handshake operation, the action
of FIFO must be acknowledged by the other
half of the handshake before the next action
can occur. In an Output Handshake mode, the
FIFO indicates that new data is available only
after the external device has indicated that it is
ready for the data. In an Input Handshake
mode, the FIFO does not indicate that it is
ready for new data until the data source indi ..
DATA IN = : x
ACKIN
RFD
X
VALID DATA
X
I
\
I
\
X
'--I
'--I
VALID DATA
Figure 4. Two.. Wire 'Interlocked Handshake Timing (input)
-JX
DATAOUT=:x_______
VA_L_ID_D_AT_A____
'\-_----JI
\~__~I
VALID DATA
C
~
\----'1
Figure 5. Two.. Wire Interlocked Handshake Timing (output)
368
2123-003, 004, 005
Functional
Description
(Continued)
Resetting or Clearing the FIFO. The CLEAR
input is used to initialize Cind clear the FIFO.
A Low level on this input clears all data from
the FIFO, allows the EMPTY output to go High
and forces both outputs RFD/DAVA and
RFD/DAVB High. A High level on CLEAR
allows the data to transfer through the FIFO.
Bidirectional Transfer Control. The FIFO has
bidirectional data transfer capability under
control of the DIR AlB input. When DIR AlB is
set Low, Port A becomes input handshake and
Port B becomes output handshake; data
transfers are then made from Port A t() Port B.
Setting DIR AlB High reverses the handshake
assignments and the direction of transfer. This
bidirectional control is illustrated in Table 1.
tion change is to be made, the recommended
procedure is:
( 1) Force and hold CLEAR Low.
(2) Set DIR AlB to the level required for the
desired direction.
(3) Force CLEAR High.
Empty and Full Operation. The EMPTY and
FULL output lines can be wire-ORed with the
EMPTY and FULL lines of other FIFOs and
FIOs. This capability enables the user to
determine the empty/full status of a buffer consisting of multiple FIFOs, FIOs, or a combination of both. Table 2 shows the various states of
EMPTY and FULL.
Number of
Bytes in FIFO
EMPTY
0
High
Low
1-127
Low
Low
Low
Higl}
DIR AlB
Port A
Handshake
Port B
Handshake
Transfer
0
Input
Output
A to B
Output
Input
B to A
128
Table 1. Bidirectional Control Function Tablo
The FIFO buffer must be empty before the
direction of transfer is changed; otherwise, the
results of the change will be unpredictable. If
FIFO status is unknown when a transfer direc+5V
FULL
Table 2. Signals EMPTY and FULL Opo·ration Table
Interconnection Example. Figure 6 illustrates
a simplified block diagram showing the manner in which FIFOs can be interconnected to
extend a FlO buffer.
+5V
FULL J-,_-----4--_--------l----1~---_.. SYSTEM FULL
EMPTY ~------1~--+_-----_--+---I'----_.. SYSTEM EMPTY
,, _ _ _ I
DATA
BUS
PORT 2
of
za03a
zaooo
zaooo
RFD/DAYa J . . - - _ }
~~~ASL~KE
ACKINa _
OEa . - - - OUTPUT CONTROL
crEAR
t-l---~-----+_-----.-...----I-----.. SYSTEM
crEAR
DATA DIR 1---l_------4--------------..I~---_.. SYSTEM DIRECTION
Figure 6. Typical Interconnection (Simplified Diagram)
2123-006
369
Functional
Description
(Continued)
Output Enable Operation. The FIFO provides
a separate Out~ut Enable (OE) signal for each
port of the buffer. An OE output is valid only
when its port is in the Output Handshake
mode. The control of this output function is
shown in Table 3. Signal OE operates with
lines DIR AlB. A High on a valid OE line
3-states its port's data bus but does not affect
the handshake operation. A Low level on a
valid OE enables the data bus outputs if its
. port is in the Output Handshake mode. Note
that the handshake operation is unaffected by
the Output Enable pin.
DIR AlB
Function
OEA OEB
o
x
o
x
o
Disable Port A Output
Enable Port B Output
Disable Port A Output
Disable Port B Output
o
X
Enable Port A Output
Disable Port B Output
X
Disable Port A Output
Disable Port B Output
NOTE: X = Don't care.
Table 3. Output Control Function Table
Absolute
Maximum
Ratings
Voltages on all inputs and outputs with respect
to GND ................... -0.3 V to +7.0 V
Operating
Ambient Temperature ......... As speCified in
Ordering Information
Storage Temperature ......... -65° to + 150°C
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; operation of the device at any condition above
those indicated in the operational sections of these specifications is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Standard
Test
Conditions
The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
• +4.75V:5Vcc :5 +5.25 V
• GND = 0 V
• TA as speCified in Ordering Information. All
ac parameters assume a load capacitance of
50 pF max.
+5V
+5V
2.2K
dr
2•2K
FRO~ OUTPUT
UNDER TEST
50 P F
Figure 7. Standard Test Load
370
Figure 8. Open-Drain Test Load
8085-0239, 001
DC
Characteristics
Min
Max
Unit
Input High Voltage
2.0
Vcc+0.3
V
VIH
Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
V
10H = -250 A
VOL
Output Low Voltage
0.4
0.5
V
V
IoL = +2.0 rnA
IOL = +3.2 rnA
IlL
Input Leakage
±10
p.A
0.4 :S VIN :S + 2.4 V
10L
Output Leakage
±10
p.A
0.4 :S VOUT :S +2.4 V
Icc
Vcc Supply Current
200
rnA
Symbol
VIH
Parameter
2.4
Condition
NOTE: VCC = +5 V ±5% unless otherwise specified over specified temperature range.
Capacitance
Symbol
Min
Parameter
Max
Unit
Test Condition
C IN
Input Capacitance
10
pF
Unmeasured pins
C OUT
Output Capacitance
15
pF
returned to ground
Cvo
Bidirectional Capacitance
20
pF
II
0
!
Input
tr
Any input rise time
100
ns
tf
Any input fall time
100
ns
~
:I
IIJ
0
NOTE: f = I MHz over specified temperature range.
Ordering
Information
Product
Number
Package/
Speed
Temp
4.0 MHz
FIFO (28-pin)
CS
4.0 MHz
Same as above
DE
4.0 MHz
Same as above
28060
CE
28060
28060
NOTES: C
Description
= Ceramic, D = Cerdip, P = Plastic;
Product
Number
28060
Package/
Temp
Speed
Description
DS
4.0 MHz
FIFO (28-pln)
28060
PE
4.0 MHz
Same as abovo
28060
PS
4.0 MHz
Same as above
E = -40°C to +85°C, S
= O°C to 70°C
371
2-Wire
Interlocked
Handshake
Timing
INPUT TIMING
DATA
RFD
EMPTY
~_.
FULL ___________
-J
W
OUTPUT TIMING
ACKNOWLEDGE INPUT TO DATA AVAILABLE TIME (BUBBLE TIME)
\~---------------
bp;...-----
OUTPUT ENABLE AND CLEAR
CLEAR~-W-¥
INPUT
DATA OUT
Figure 9. Timing Diagrams
372
2123-007
FIFO 2-Wire Handshake Timing. Timing for
2-wire interlocked handshake operation is
shown in Figure 9. The symbol, description
AC
Characteristics
No.
Symbol
TsDI(ACK)
and values for the numbered parameters
(Figure 9) are given in AC Characteristics.
Parameter
2
TdACKf(RFD)
Data Input to ACKIN 1 to Setup Time
ACKIN 1 to RFD 1 Delay
3
4
TdRFDr(ACK)
TsDO(DAV)
RFD I to ACKIN 1 Delay
Data Out to DAV 1 Setup Time
Min
50
o
o
50
Max
Units·
ns
ns
ns
ns
5-TdDAVf(ACK)--DAV 1 to ACKIN 1 Delay - - - - - - - - - - - 0 - - - - - ns6
ThDO(ACK)
Data Out to ACKIN I Hold Time
50
ns
7
TdACK(DAV)
ACKIN 1 to DAV I Delay
0
ns
8
ThDI(RFD)
Data Input to RFD 1 Hold Time
0
ns
9
TdRFDf(ACK)
RFD 1 to ACKIN I Delay
0
10 -- TdACKr(RFD) - - ACKIN I to RFD I Delay
11
TdDAVr(ACK)
DAV I to ACKIN I
ns
0 - - - - - ns0
ns
TdACKr(DAV)
ACKIN I to DAV 1
ns
o
TdACKINf(EMPTY) (Input) ACKIN 1 to EMPTY 1 Delay
(Output) ACKIN 1 to EMPTY I Delay
TdACKINf(FULL) (Input) ACKIN 1 to FULL I Delay
14
(Output) ACKIN 1 to FULL 1 Delay
15 -- ACKIN Clock Rate (Input or Output) - - - - - - - - - - - - - - - - 1 . 0 - - - - - - - - - MHzTdACKINf(DAVf) . (Bubble Time)
16
ns
12
13
17
18
19
TwCLR
TdOE(DO)
TdOE(DRZ)
Width of Clear to Reset FIFO
OE 1 to Data Bus Driven
OE I to Data Bus Float
700
ns
o
n3
ns
NOTES:
• All timing references assume 2.0 V for a logic 1 and 0.8 V for a
logic O. Timings are preliminary and subject to change.
00-2123-03
373
II
IIti
:3
III
0
•
Z8065
Z8000™ZalBJ£P
BUllSI Elru'017 ~Il@CeSS@lf
ProduceR
Specificaiionu
Zilog
September 1983
Features
1!!1
Detects errors in serial data up to 585,442
bi ts in length
II
Implements correction of a detected error
burst of up to 12 bits in length
1I
m Provides three correction algorithms:
o Full-period clock-around method for conformance to current practices
o Chinese remainder theorem, which
Handles effective data rates of up to 20M
bits per second
reduces correction time by orders of
magnitude
o Reciprocal polynomial, which allows cor-
B Provides four industry-standard polynomials
rection with 48-bit code
for error detection
II
General
Description
Designed for use in both microprocessor
and microprogrammed disk-controlled
systems
The 28065 Burst Error Processor (BEP) provides error detection and correction facilities
for high-performance, high-density disk
systems and any other system in which highspeed serial data transfers occur.
For error detection, the BEP provides a
selection of four standard polynomials,
including the more popular 56-bit and 4~-bit
INPUT
DATA
1
Do
00
01
01
02
02
03
03
04
04
05
as
Os
as
07
07
I
DATA
CHECKDUTBITS
Z8065
BEP
LPI
Po
PI
}
ER
ERROR
AE
ALIGNMENT EXCEPTION
P2
EP
ERROR PATTERN
P3
C2
REP
PM2
Po
POL YNOM'AL {
LDCATED ERRDR
PATTERN
LP2
LP3
FUNCTION {
SELECT
SHIFT CONTROL
07
REP
LPo
POL YNOMIAL {
SELECT
READ ERROR
PATTERN
versions, to satisfy a broad range of applications. During write operations, the BEP
,generates check-bit words, which are appended to the record being written onto the disk.
These check-bit words are then used in subsequent reads and, if necessary, in correction
operations.
PI
PM3
P2
PM4
}
PATTERN MATCH
Do
01
02
+5 V GNO
CP
MR
Figure 1. Pin Functions
2019-001
2019-002
Some of the material used herein is used by permission of Advanced Micro DeVices, Inc,
Figure 2. Pin Assignments
375
General
Description
(Continued)
When a stored record is read, the BEP computes the syndrome for data validation. This
syndrome is then used to determine' if an error
burst is present in the retrieved data stream. If
an error is detected, the BEP can be used to
locate its actual bit pattern. The information
obtained is then made available to the host
system where it is used to correct the data
read. Any of the three algorithms can be
selected for this process.
The BEP is fabricated using silicon-gate,
N-MOS technology and is supplied in a 40-pin
dual in-line package (DIP). Figures 1
and 2 illustrate the pin functions and pin
assignments, respectively, of the Z8065. Z8065
operation requires a + 5 V dc power supply
and a single-phase clock.
Pin
Descriptions
AE. Alignment Exception (output, active
data stream. If the register array contains a
zero syndrome, ER is set Low to indicate that
no error was detected. If the array contains a
non-zero syndrome, ER is set High to indicate
that an error was detected. The output is valid
only after the BEP receives the last check byte
during a normal read or a read high-speed
function. The resulting syndrome is contained
by the register array. ER is set Low each time
the BEP is initialized.
High). This output goes High when a misalignment condition occurs during an error-pattern
search operation.
Co-~.
Function Select (inputs, active High).
These three lines carry the binary code used to
select the BEP functions. The codes and the
functions initiated by each are listed in
Table 1.
~
Cl
Co
Function
L
L
L
Compute Check Bits
L
L
H
Write Check Bits
L
H
L
Read Normal
Read High Speed
L
H
H
H
L
L
Load
H
L
H
Reserved
H
H
L
Correct Normal (Full Period
Clock Around)
H
H
H
Correct High Speed (Chinese
Remainder Theorem Method)
H = High, L = Low
Table 1. Function
Sel~ct
Codes
CPo Clock (input, active High). All BEP
operations are timed by this external clock
input. Any input changes must be made to the
BEP v:hen CP is High. Data is strobed into the
BEP only during the Low-to-High transition of
CP. BEP outputs are valid only after a subsequent Low-to-High transition occurs on CP.
Do-D7. Data In (input, active High). These
eight lines are used to enter data into the BEP.
Do is the least-significant bit (LSB) position of
the input; D7 is the most-significant bit (MSB)
position of the input. Data entry occurs on the
Low-to-High transition of the input clock pulse.
Any change on Do-D7 must take place when
the clock pulse (CP) input is High.
EP. Error Pattern (output, active High). During an error correction process, EP is set High
to indicate that the bit pattern of the detected
error has been found. EP is set Low each time
the BEP is initialized. EP is valid only during
the performance of a correction function; it
must be ignored at all other times.
ER. Error (output, active High). ER indicates
that the BEP has detected an error in the input
376
LPO-LP3. Located Error Pattern (outputs,
3-state). These four lines, together with QO-Q7
provide a 12-bit error pattern that is output
when REP is High. Q7 is the MSB of the pattern; LPO is the LSB of the pattern. A High
level on any output line represents a logical 1;
a Low level a logical O. When no error pattern
is available (REP is Low), output lines LPO-LP3
and QO-Q7 are maintained in a highimpedance state.
MR. Master Reset (input, active Low). This
input controls the initialization of the BEP. Setting MR Low for a minimum period of 800 ns
initialized the BEP. The BEP must be initialized
prior to performing compute check bits, read
normal, read high-speed, and load functions.
PO-P3. Polynomial Shift Control (inputs, active
High). During correction procedures using the
Chinese remainder theorem, each syndrome
obtained by the high-speed read function is
shifted individually. The PO-P3 inputs provide
this capability: Po enables the shifting of the
first syndrome, PI shifts the second syndrome
and so on. A High on an input allows the corresponding register to shift; a Low causes it to
hold. These inputs are effective only during
the correct high-speed function. Changes on
these inputs occur only when the CP input is
High.
PM2-PM4. Pattern Match (outputs, active
High). These lines are used during a Chinese
remainder theorem error-correction operation
to indicate error-pattern match conditions for
each syndrome involved. When High, an output speCifies that the corresponding syndrome
register has achieved a match.
QO-Q7. Data Out (outputs, 3-state). These
eight lines are active only during write check
bit and error correction functions. At all other
times, QO-Q7 are maintained at a highimpedance level. During the write check bit
Pin
Descriptions
(Continued)
function, check bits are presented to these
lines one byte at a time. Qo is the LSB and Q7
is the MSB of the output. During the errorcorrection function, REP enables these lines to
carry the detected error bit pattern.
REP. Read Error Pattern (input, 3-state). REP
when High, enables lines LPO-LP3 and QO-Q7.
This error pattern information is valid only
after a High is indicated on the EP output during correction operations.
SO-SI. Polynomial Select (inputs, active High).
These two pins carry the binary codes required
to select which polynomial the BEP will implement. The select codes (logic levels) are given
in Table 2.
Number of
Check Bits
Polynomial
L L
(X22 + l)(XlI +X7 +X6-i-X+ 1)(X12+XlI +XlO+X9+X8+X7 +X6+X5+X4+X3+X2+X+ 1)
(XlI +X9+X7 +X6+X5+X+ 1)
L H
(X21 + l)(XlI + X2 + 1)
32
H L
(X23 + 1)(X12+XlI +X8+X7 +X3+X+ 1)
35
H H
(X13+ 1)(X35+X23+X8+X2+ 1)
48
56
H = High, L = Low
Table 2. Polynomial Select Codes
Architecture
The BEP consists of four major circuit
groups: control logic, polynomial divide
matrix, register array, and status logic. Figure
3 shows a block diagram of the BEP.
Control Logic. The control logic circuits provide timing, reset, polynoinialselection, and
read error-pattern control inputs for the
remaining BEP circuits.
Basic timing is provided to the control logic
by clock input CPo The control logic generates
and distributes appropriate timing and control
signals to the remaining BEP circuits.
Enabling the Master Reset (MR) causes the
control logic to initialize all device circuits.
This operation is usually performed before the
execution of a selected device function.
Function select and polynomial select inputs
are decoded by the control logic. The outputs
of the decoder are then used to generate the
control and timing signals needed to perform
the encoded function or to select the encoded
pol ynomial.
The Read Error Pattern (REP) and
Polynomial Shift Control signals enable the
control logic to strobe valid error bit pattern
outputs onto the register array output lines.
During high-speed corrections, the polynomial·
shift inputs are used for register array, error
burst-pattern bit-matching operations.
Polynomial Divide Matrix. This matrix connects the register array circuits so that each
data byte presented on lines Do-D7 is suitably
divided by the user-selected polynomial. The
connections to be made are determined by
STATUS LOGIC
RESET (MA) - - - - - - - - - ,
ZERO DETECTION
t---.
ERROR (ERI
ALIGNMENT MONITOR
t---.
ALIGNMENT EXCEPTION (AE)
t---.
ERROR PATTERN (EP)
CLOCK (CP) - - - - - ,
ERROR PATTERN DETECTOR
FUNCTION
SELECT (C2-CO)
L.-_ _ _~o::------....Jr-----v
1-_ _ _ _ _,\
1-_ _ _ _ _,/
POLYNOMIAL SHIFT
CONTROL (P3-PO) ' - -_ _ "
PATTERN MATCH (PM.·PM2)
DATA OUT
(07-00)
REGISTER
ARRAY
POLYNOMIAL
SELECT (5,-50)
POLYNOMIAL
DIVIDE MATRIX
Figure 3. Simplified Block Diagram
2019-003
377
Archi tecture
(Continued)
gating the signals supplied by the control logic
after decoding the select code on inputs So
andSl.
Register Array. This array consists of 56 flipflop circuits used for: (1) check-bit computation during write operations, (2) syndrome
computation during read operations, and (3)
error pattern extraction during errorcorrection operations.
The bit patterns required for array functions
are provided by the polynomial divide matrix.
The array and matrix circuits, together,
simulate a serial, polynomial, feedback-shift
Condition
Detected
register arrangement in an 8-bit parallel form.
At the end of each write operation, the computed check-bit bytes are available on lines
00-07. On completion of a correction operation, the bit pattern of the detected error is
available on lines LPO-LP3 and 00-07. Input
REP determines when a valid error bit pattern
is on the register output lines.
Status Logic. These circuits monitor the
register array to detect the conditions listed in
Table 3 and to enable the generation of the
corresponding control signals.
Signal
Result of Polynominal Division
ER (error) High when error found; Low when no error.
Alignment during H-S and normal correction
AE (alignment error) High when error pattern is incorrectly aligned.
Location of an error bit pattern
EP (error pattern) High when an error-bit pattern is detected.
Pattern matching during H-S correction
PM 2 , PM3, PM4 (pattern match). Each signal goes High when its
corresponding register matches the proper section of a located burst·bit
pattern.
Table 3. Status Logic. Detected Condition and Resulting Output
Functional
Description
The BEP detects and corrects data errors
using write, read, and correct operations. The
BEP operates in conjunction with external
logic: either a microprocessor or microprogrammed control circuitry. Master clock
inputs, the selection of polynomials and functions, and the output of check bytes and error
bit patterns are initiated and controlled by
inputs from external circuits. External logic is
also used to collect data, perform calculations,
and carry out the actual modification of stored
data during error-correction operations.
The BEP contains code for four standard
polynomials (sometimes referred to as Fire
codes). This code forms the basis fo the unit's
error detection and correction functions. The
polynomial to be used is selected by a coded
input from the host system*. Table 2 lists the
polynomial select codes, the equations implemented, and the number of check bits
generated by each polynomial during a write
operation. The same polynomial must be
selected for the write, read, and correction
operations performed for a given data stream.
It is the responsibility of the host system to
keep track of which polynomial is selected for
use with each data stream.
The BEP also contains the cod~ required to
implement each of seven functions that can be
executed during data stream write, read, and
correction operations. The function to be performed is selected by a coded input from the
host system. * The functions and their required
input code are listed in Table 1.
'NOTE: In the remainder of this specification, external circuitry
and software is referred to as the host system.
378
Write Operation. Before data is written onto a
disk or similar storage device, the BEP must
generate and add check-bit bytes to the data to
be stored. These bytes are required for the
detection and correction of errors that may
occur during write and during subsequent
read operations.
Immediately before a write operation, the
host system must output codes to the BEP to
select the polynomial to be used and to initiate
the compute check-bit function.
The data stream to be written is entered, onthe-fly, into the BEP as it is written onto the
disk. Data is presented to the BEP as a series
of 8-bit bytes in parallel form. Check bits are
generated by dividing each input byte by the
selected polynomial using the rules of algebra
in polynomial fields. The check bits are stored
as they are generated. Check bits are
generated in sets of 56, 48, 35, or 32 bits,
depending on the selected polynomial. When
the last input byte has been processed, the
write check-bit function is initiated by the host
system. During a check-bit write, the
generated check bits are organized into 8-bit
bytes (check-bit bytes), which are output byte
by byte in 8-bit parallel form on lines 00-07.
The host system adds these check-bit bytes to
the end of the newly written file.
The polynomial selected for data write
operations must also be used in subsequent
reads of the written data. Therefore, in selecting a polynomial for a write operation, the
user should consider the type of read and correction functions desired for future data
retrieval operations. The relationships between
Functional
Description
(Continued)
the polynomials and the read and corrections
functions are:
II
A read normal function must be followed by
a correct normal function. All four
polynomials can be used with this set of
read/correction functions.
II
A read high-speed function must be followed by the Chinese remainder theorem
correction function. All but the 48-bit
polynomial can be used with this set of
read/ correction functions.
Read Operations. When data is read from a
disk, the BEP checks the retrieved data and
check-bit bytes for read and write errors. If
errors are detected, the host system initiates
correction functions, retrieving from the BEP
the information needed to locate and correct
the erroneous data. Immediately before starting the read operation, the host system selects
the desired polynomial and either a read normal or a read high-speed function. Data and
associated check-bit bytes are then loaded,
byte-by-byte, into the BEP as they are read
from the disk. A divide operation results in
one or more syndromes (depending on the
polynomial used), which are stored in the
register arr-ay. The binary values of these syndromes indicate whether or not an error was
present in the scanned data stream. If an error
was detected, ER is set High.
When an error condition is indicated and
correction is desired, the host system must
initiate a correct normal, a A8-bit correct normal, or a correct high-speed function. The
function selected depends on which
polynomial and which read function were
selected for the initial read operation. When
executed, the selected correction function supplies the host system with the information
needed to calculate the location of the error
pattern in the data stream and to correct the
erroneous data stream bits.
Read Normal Function. When this function is
selected, the polynomial matrix is configured
to 'establish the selected polynomial in its
expanded form. The input stream, data and
check bit bytes, are divided byte by byte by
the expanded polynomial. The results form a
syndrome whose binary value is detected by
the status logic. If the syndrome is nonzero, ER
goes High, to indicate an error condition; if
the syndrome is zero, ER remains Low, to
indicate a no-error state.
Read High-Speed Function. This function is
selected when the correct high-speed function
is used. All but the 48-bit polynomial can be
used with this function.
When selected, this function configures the
polyncmial matrix to simultaneously divide
each byte of the input data/check-bit stream by
all factors .of the selected polynomial. The
result of each factor division forms a separate
syndrome. Thus, the number of syndromes
developed depends upon the number of factors
in the selected polynomial. The status logic
monitors all syndromes and uses their combined binary values to determine if an error
condition is present. If all syndromes are zero
after the last byte of the input stream is read, a
no-error state is indicated and ER remains
Low. If any syndrome has a non-zero value, an
error condition is indicated and ER is set High.
48-Bit Polynomial. Only read normal and correct normal functions can be used when this
polynomial is .selected. The read normal function for the 48-bit polynomial is performed in
the same manner as for the other polynomials.
The resulting syndrome, however, will be too
long and cannot be used directly in subsequent correct normal functions; instead, the
reciprocal of the syndrome must be established
in the BEP before the correct normal function
is selected. The host system initiates this
operation by selecting the write check-bit
function immediately after the syndrome is
formed and error is indicated. Clock pulses
are then applied to the BEP during the write
bit function to strobe the syndrome onto lines
QO-Q7 as six sequential 8-bit bytes. The host
system must then reverse the order of the syndrome bits (that is, the original LSB becomes
the new MSB and the original MSB becomes
the new LSB) to form the reciprocal. The host
system then reloads this new syndrome into the
BEP by selecting the load function.
Load Function. This function is used only during read normal and correct normal operations
when the 48-bit polynomial is selected. The
host system selects the load function to prepare
the BEP to receive an externally-formed
reciprocal syndrome and to control the loading
of the syndrome bytes into the BEP. The load
function causes the register array to be configured into an 8-bit wide, 7-bit deep shift
register connected to lines Do-D7. The host
system then presents the six syndrome bytes on
lines Do-D7. Clock pulses are then generated
to strobe the bytes into the Shift register one at
a time.
When all six bytes of the syndrome are
loaded, the host system causes the input lines
to be pulled Low, then generates a seventh
clock pulse. The seventh clock pulse strobes
these Lows into the Shift register as a zero
dummy fill byte. On completion of the load
operation, the BEP is ready for the cor!ect normal function.
379
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Correction
Operations
The detection of an error in a retrieved data
stream causes the following corrective functions to be performed:
1. The error burst containing the erroneous
data bits is located by the BEP.
2. Using data supplied by the BEP, the host
system calculates the exact position of the
error burst in the retrieved data stream.
3. The bit pattern of the error burst is strobed
out of the BEP and used by the host system
to perform bit correction.
Location of an Error Pattern. An error pattern is characterized by the appearance of a
known number of consecutive Os in specific
registers of the register array. The exact
number of Os and their locations in the register
array is unique to each polynomial. When a
polynomial is selected for read and errordetect/correction operations, the pattern
associated with that polynomial is loaded into
the status logic. The status logic uses this pattern to identify an error burst during the error
pattern location operations.
When only one syndrome is developed during the read error-detection function, the
error-bit pattern is located by repeatedly
dividing the syndrome by the polynomial. Division is accomplished by the repeated application of clock pulses (CP), while ignoring the
states of lines Do-D7. This operation results in
a serial bit-by-bit reconstruction of the
retrieved data stream. The generated data bits
are shifted at a rate of one per clock cycle
through the register array. The BEP status
logic performs the actual error bit pattern
detection as the data stream is reconstructed.
The status logic monitors specific registers of
the register array, and it detects a pattern of Os
that matches the zero error pattern unique to
the selected polynomial, it sets EP High to indicate that an error burst was found.
When more than one syndrome is developed
during the read error-detection function, each
syndrome is divided by its associated factor
until a match condition is found for each. Each
time a match is found, the status logic enables
one of outputs PM2, PM3 or PMt. When the
total error bit pattern is found, the status logic
ou tpu ts associated with the syndromes of a
polynomial (2 or 4) are all enabled. The clock
pulses required for each factor syndrome
divide operation are supplied by lines PO-P3.
A major factor in calculating the exact location of error-burst patterns in the retrieved
data stream is the number of clock pulses used
by the BEP to detect the error-burst pattern.
The host system must record the total number
of clock pulses generated from the start of BEP
pattern-location operations to the enabling of
output EP. If necessary, this total must include
the clock pulses needed for alignment
operations.
Bit Alignment. During syndromE;l division, the
register array is configured into a matrix
representing an 8-bit, parallel mechanization
of a serial, polynomial division scheme. Under
certain conditions the error pattern bits
~eveloped do not line up automatically. When
the status logic detects such a misalignment,
AE is set High. When AE is High, the BEP
switches internally into One-Bit Shift mode
during which each input clock pulse shifts the
data stream one cell through the register
array. When alignment is achieved, the status
logic sets AE Low and the BEP is switched out
of the One-Bit Shift mode. The number of shift
pulses needed to achieve alignment is an additional factor in calculating the position of the
error-bit pattern.
Uncorrectable Errors. If the total clock cycle
time needed to locate the error burst pattern is
greater than the natural period of the selected
polynomial (Table 4), an uncorrectable error
condition is indicated and the host system must
abort the correction operation.
No. of
Check Bits
Period
(Bits)
Correctable
Burst Error
Length (Bits)
(X 22 + 1)(Xll +X7 +X6+X+ I)(XI2+Xll +XlO+ ...
+X+ 1)(Xll +X9+X7 +X6+X5+X+ 1)
56
585,442
11
(X21 + 1)(Xll +X2+ 1)
32
42,987
11
(X23 + I)(XI2 +Xll + X8+ X7 + X3 + X + 1)
35
94,185
12
(XI3+ 1)(X35+X23+x8+X2+ 1)
48
13(235 _1)
7
Polynomial
Table 4. Polynomials, Checkbits. Natural Period. and Length of Error Burst
380
Correction
Operations
(Continued)
Correct Normal Function. This function must
be preceded by a read normal function. With
the exception of 4S-bit polynomial operations,
this function performs all operations needed to
construct a serial form of the retrieved data
stream and to locate the detected error burst.
The operations performed are the same as
those described previously for a singlesyndrome situation.
Correct Normal Function, 48-Bit Polynomial. The functions performed by the correct normal function when a 4S-bIt polynomial
is selected are essentially the same as those
described for the other polynomials. The major
exception is that the location 'of the first bit in
the error-bit pattern is calculated using the
formula:
Computing Error Bit Pattern Locations. If no
alignment exception state is indicated (AE is
Low), the locations of the error-bit pattern
within the data stream (except when the 35-bit
polynomial is used) can be calculated by the
formula:
L = NK - SRI
Where:
L
= (SRI +
R2) - 4S
L = The number of bit positions from the last
check bit to the nearest error burst bit.
!--L __I
-1r--E-R-RO-R-B-UR-ST--'~
_
r-----,
Where:
L = The location (number) of the first bit in
the error burst, counting from the last check
bit in the scanned record.
.
N = The natural period of the selected polynomial.
K = The smallest integer needed to make this
expression positive.
RI = The total number of clock pulses input
by the BEP from the start of the find operation
until EP goes High.
If an alignment exception state is indicated
(AE is High), the location of the error-bit pattern within the data stream (except when the
35-bit polynomial is used) can be calculated
using the formula:
L = NK - SRI - R2
Where:
L,N,K, and RI are the same as described
above.
R2 = The number of clock pulses input by the
BEP between the time that AE goes High and
EP goes High.
If the 35-bit polynomial is selected, the
quantity 5 must be added in the following manner to the formulas used to calculate the location of the error-bit pattern:
L = NK - SRI + 5
and L
= NK
- SR I - R2 + 5
RI = If alignment is needed, RI is the number
of clock pulses from the start of the find operation until AE goes High. If no alignment is
needed, R I is the total number of clock pulses
from the start of the find operation until EP
goes High.
R2 = Variable used only when an alignment is
needed; it represents the number of clock
pulses from the time AE goes High until EP
goes High.
Correct High Speed Function. This function
uses a Chinese remainder theorem to locate a
detected error-burst bit pattern. This theorem
minimizes the number of clock pulses required
for the location process, thus making it appreciably faster than the correct normal method.
The correct high-speed function must be
preceded by the read high-speed function. The
multiple syndromes developed during the read
operation are located in consecutive sets'of
flip-flops in the register array. The set of flipflops containing syndromes is treated as an'
individual shift register. Each syndrome shift
register is associated with the factor of the
polynomial used to develop the syndrome. For
example, the 56-bit polynomial has four factors
(see Table 2), and when selected for read and
correction operations it causes four corresponding syndromes to be developed, each housed
in an individual shift register in the register
. array.
3S1
Correction
Operations
(Continued)
The actual location of an error-bit pattern
can be computed by the host system using the
following elements:
1. The number of clock pulses required (per
factor/syndrome register) to find the error
pattern.
2. The natural period of each factor of the
selected polynomial.
3. A predetermined constant per factor.
The formulas used to calculate error-pattern
locations for high-speed operations are
described in Table 5. Table 6 lists the pre~
determined constants for each factor of the
polynomials. Table 7 lists the natural period of
each factor of each polynomial.
L
=
(NK) - (AIMI + A2M2 +
A3M3 + A4M4)
·32-Bit L
=
(NK) - (AIMI + A2M2)
56-Bit
35-Bit
L = (NK) -(AIMI + A2M2 + 5)
Table 5. Correct High-Speed. Error-Burst
Location Formulas
Legend:
L = Beginning (first bit) of detected error
burst counting from the last check bit in the
processed record.
-1
K
ERROR BURST
~-
= Smallest integer required to make right
side of equation positive.
AI-Al.
= Natural period of selected polynomial.
= Number of clock pulses required to
achieve a match in each factor/syndrome
register.
A detected error-bit pattern can be strobed
from the BEP in 12-bit, parallel form by forcing REP High when EP goes High. The 12-bit
output is then matched bit for bit with the corresponding bits in the stored data. The errorbit pattern is then XORedwith the matching
data stream bits to effect the required bit-bybit correction.
Figure 4 illustrates the format for strobing
the error bit pattern (11 or 12 bits) out of the
BEP in all but the 48-bit polynomial correction
operation and shows how the pattern must be
oriented to the data stream bits. Figure 5 illustrates the format for strobing the error-bit pattern (7 bits) out of the BEP in the 48-bit
polynomial correction operation and shows
how the pattern must be oriented to the data
stream bits.
Data Stream Correction Function. Each
detected error pattern consists of 12 consecutive bits not all of which represent errors.
If the data and check-bit stream scanned during the preceding read operation was stored in
accessible memory, the error-bit pattern can
be used directly to correct the data stream.
Polynomial
Al
Predetermined Constants
A2
Aa
56 Bit
452,387
2,521,404
32 Bit
311,144
32,760
35 Bit
32,760
720,728
578,864
A.
2,647,216
= Predetermined constants for each
factor of the selected polynomial.
382
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Table 6. Chinese Romainder Theorem Coefficients
Correction
Operations
(Continued)
Tablo 7. Natural Periods for Polynomials and Polynomial Factors
Polynomial
Period
Factor I
Period
Factor 2
Period
Factor 3
Period
Factor 4
Composite
Period (n)
56 Bit
32 Bit
35 Bit
22
21
23
13
2047
4095
89
23
585442
42987
94185
L (COMPUTED ERROR LOCATION)
RECORD
DATA
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Figure 4. Error Pattern Fo.mat for 56-Bit. 35-Bit. and 32-Bit Polynomials
P.I
loG
Figure 5. Error Pattern Format for 48-Bit Polynomial
2078-003
2078-004
383
Timing
The overall timing requirements for BEP
operations are illustrated in Figures 6 through
13. Individual timing parameters are identified
numerically in each timing diagram and are
described in the AC Characteristics section.
Figure 6. Clock Waveform For All Functions Except
Correct Normal Or Correct High-Speed
AC
Characteristics""
No.
Symbol
Parameter
Clock Pulse (CP) Width (Low)
TwCPl
1
TcCP
Clock Pulse Cycle Time
2
Clock Pulse Width (High)
TwCPh
3
4
TwMRI
MR Pulse Width (Low)
5 - TdMR(CP) - - MR t to CP l Time Delay-Recovery
TsDI(CP)
DI (Do-~) to CP t Setup Time
6
ThCP(DI)
CP t to DI (Do-~) Hold Time
7
TsC(CP) or
C(Co-C2) or S(SO-S1) to CP t 8etup Time
8
Ts8(CP)
ThCP(C) or
CP t to C(CO-C2) or 8(80-8 1) Hold Time
9
ThCP(8)
lO-TsC(CP) o r - - C(CO-C2) or 8(So-8 1) to CP l 8etup Time
Ts8(CP)
TdC(Q) or
C(CO-C2) or S(80-82) to Q(Qo-~) Valid Time Delay
11
Td8(Q)
TdCP(Q)
12
CP t to Q(Qo-~) Invalid Time Delay
TdCP(Q)
CP t to Q(Qo-~) Valid Time Delay (write)
13
TdC(Q)
C(CO-C2) to Q(QO-Q7) Time Delay-3-state
14
15 - TdMR(ER) - - MR l to ER l Time Delay
TdCP(ER)
16
CP t to ER t Valid Time Delay
TwCPCl .
CP Pulse Width (Low) for Correct Functions
17
TwCPCh
CP Pulse Width (High) for Correct Functions
18
TcCPC
CP Cycle Time for Correct Functions
19
20- TdC(EP) 9 r - - C(CO-C2) to EP or to AE Valid Time Delay
TdC(AE)
TdCP(EP) or
21
CP l to EP, to AE or to PM(PM2-PM4) Valid Time Delay
TdCP(AE)
TsP(CP)
22
P(PO-P3) to CP l Setup Time
23
TdPo(EP) or
Po t to EP or to AE Time Delay
TdPo(AE)
TsC(CPC) or
24
C(CO-C2) or 8(80-8 1) to CP l 8etup Time for Correct Functions
Ts8(CPC}
25 - TdP(PM) - - - P1 or P2 or P3 to Corresponding PM Output, Time Delay
TdCP(EP) or
CP l to EP, to AE, or to PM (PM2, PM3, P~) Invalid Time Delay
26
TdCP(AE) or
TdCP(PM)
27
TdPo(EP) or
Po l to EP or to AE Invalid Time Delay
TdPo(AE)
TwREPh
REP Pulse Width (High)
28
TdREP(Q) or
29
REP t to Q(Qo-~) or to LP(LPo-LP3) Time Delay
TdREP(LP)
30- TdREP(QT) or- REP l to Q(Qo-~) or to LP(LPo-LP3) Time Delay 3-state
TdREP(LPT)
TdP(PM)
31
P(P 1-P3) l to PM(PM2-P~) Invalid Time Delay
TdC(EP) or
C(CO-C2) to EP, or to AE, PM(PM2-P~) Invalid Time Delay
32
TdC(AE) or
TdC(PM)
Min
(ns)
Max
(ns)
180
400
180
800
250
350
0
400
0
180
200
0
200
100
200200
450
450
1000
250400
400
250
400
2500
0
250
150
1000
0
* All timings are preliminary and subject to change.
384
2078-005
AC
Character·
istics
(Continued)
Figure 7. Compute Check Bits or Load Function
CP
f-----@---~
Notes: 1. REP input assumed low.
2. 0 0.0 7 outputs will be high impedance if CO-C2 inputs do not specify write check bits function.
Figure 8. Write Check Bits Function
I--t---@
ER
Note: ER output is a function of the contents in the register array flip·f1ops.
Figure 9. Read Normal or Read High-Speed Function
2078·006 2078·007 2078-008
385
AC
Characteristics
(Continued)
~---------------~--------------~~
Figure 10. Clock Waveform for Correct Normal or Correct High-Speed Functions
\~~
E.,AE
~® /....----K
__I
'tI!JY:n
Note 1: Assumes AE or EP output becomes active without any clocking.
Figure II. Correct Normal Function
_I
CP
Po
~----+---~--------~.~
Note 2
~----------~~~~--------~~
EP,AE
Note 3
Note 2: Assumes EP, AE becomes active without clocking.
Note 3: Assumes corresponding PM output becomes active without clocking.
Figure 12. Correct High-Speed Function
1-1.-'------@---ll
REP_A
r-@)~
\_
@+~
QO-Q7/LP_O_-_L_P_3________________~~--------------------~~
Figure 13. Read Error Pattern Timing
386
2078-009 2078-010
2078-011
2078-012
Absolute
Maximum
Ratings
Voltages on all inputs and outputs with respect
to GND ................... -0.3 V to +7.0 V
Operating
Ambient
Temperature ........ See Ordering Information
Storage Temperature ......... -65° to + 150°C
Standard
Test
Conditions
The characteristics below apply for the following standard test conditions unless otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
DC
Characteristics
Electrical
Characteristics
~
[J
+4.75 V
[J
GND = 0 V
[J
O°C
~
TA
Vee
~
~
2.2K
+5.25 V
+70°C
. Parameter
Symbol
Min
Max
Unit
Condition
VeH
Clock Input High Voltage
Vee- O.4
Vee+ 0 .3
v
Driven by external clock
generator
VeL
Clock Input Low Voltage
-0.3
0.45
V
Driven by external clock
generator
V
V
V
V
VlH
Input High Voltage
2.0
Vee+ 0 .3
VIL
Input Low Voltage
-0.3
0.8
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
± 10
10L
Output Leakage
± 10
Icc
Vee Supply Current
300
p.A
p.A
rnA
Min
Max
Unit
V
V
V
V
2.4
0.4
Parameter
Symbol
VIL
Input Low Voltage
-0.5
+.8
VlH
Input High Voltage
2.0
VOL
Output Low Voltage
Vee
0.4
VOH
Output High Voltage
10L
Output Leakage Current
10
IWH
Output Leakage Current
10
CIN
Input Capacitance
15
CliO
I/O Capacitance
25
ILL
Input Leakage Current
± 10
Icc
Vee Power Supply Current
NOTES: D
8085'{)209
=
eerdip, P
=
Plastic, S
and Vee
= 5.0
Description
4.0 MHz
DS
2.4
= 25°C
Paclcage/
Temp
Speed
Product
Number
Z8065
00-2078-02
+5V
I
NOTE: Typical values apply at TA
Ordering
Information
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition aDove those indicated in the ~perational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Burst Error
Processor
(40-pin)
=
p.A
p.A
pF
pF
p.A
10H
= -250 A
10L
=
0.4
:S
VIN
:S
+ 2.4 V
0.4
:S
VIN
:S
+ 2.4 V
+2.0
rnA
Condition
10H = 3.2
10H
=
400
rnA
p.A
VO UT
0.4 V
VO UT
Vee
V. See table above for operating range.
Product
Number
Z8065
Package/
Temp
Speed
PS
4.0 MHz
Description
Burst Error
Processor
(40-pin)
ooe to 70°C
387
Z8068
Z8000™ Z-DCP Data
(cApllue~ilillg nnllOCeSSOi'
lProduct
Specification
Zilog
September 1983
Features
El
Encrypts and decrypts data using the
National Bureau of Standards encryption
algorithm.
security and throughput by eliminating frequent reloading of keys.
B Three separate programmable ports (master,
c Supports three standard ciphering modes:
slave, and key data) provide hardware
separation of encrypted data, clear data,
and keys.
Electronic Code Book, Chain Block and
Cipher Feedback.
lJ
General
Description
Three separate registers for encryption,
decryption, and master keys improve system
The Z8068 Data Ciphering Processor (DCP)
is an n-channel, silicon-gate LSI device, which
contains the circuitry to encrypt and decrypt
data using National Bureau of Standards
encryption algorithms. It is designed to be
used in a variety of environments, including
dedicated controllers, communication concentrators, terminals, and peripheral task processors in general processor systems.
The DCP provides a high throughput rate
using Cipher Feedback, Electronic Code
Book, or Cipher Block Chain operating modes.
The provision of separate ports for key input,
clear data, and enciphered data enhances
security.
t:I
Key parity check.
The host system communicates with the DCP
using commands entered in the master port or
through auxiliary control lines. Once set up,
data can flow through the DCP at high speeds
because input, output and ciphering activities
can be performed concurrently. External DMA
control can easily be used to enhance
throughput in some system configurations.
The 28068 DCP is designed to interface
directly to Zilog's Z-BUS® . Device signal/pin
functions are shown in Figure 1; actual pin
number assignments are shown in Figure 2.
MASTER
PORT
(ADDRESSI
DATAl
)
SLAVE PORT {
CONTROL
AUXILIARY {
CONTROL
SLAVE
PORT
(DATAl
I
~Ml
)
,""um
CONTROL/KEY
PARITY
+5V
GND
'-'
40
+5V
39
SP,
SP,
SP, = 3
4
SP,
38
37
SP,
SP,
5
36
SP,
AUXo = 8
7
AUX1
35
AUX,
34
AUX,
AUX, = 8
33
AUX.
~UX,
9
32
AUX,
AFlG
10
ASTB
11
PAR
12
CIK
13
Z8068
DCP
31
SFlG
30
29
SDS
28
scs
MRiW
elK
14
27
MAS
MFLG
15
26
MDS
MPo
16
25
MCS
MP,
17
24
MP,
MP,
18
23
MP,
MP,
n
22
MP,
GND
20
21
MP,
elK
Figure 1. Pin Functions
2080-001,002
•
Data rates greater than 1M bytes per second
can be handled.
.
Some of the material used herein is used by permission of Advanced Micro Devices, Inc.
I
N
IJ
GND= 1
2
SPo
N
Figure 2. Pin Assignments
389
Q
Pin
Descriptions
AFLG. Auxiliary Port Flag (output, active
Low). This output signal indicates that the DCP
is expecting key data to be entered on pins
AUXo-AUX7. This can occur only when C/K is
Low and a \\Load Key Through AUX Port"
command has been entered. AFLG remains
active (Low) during the input of all eight bytes
and will go inactive with the leading edge of
the eighth strobe (ASTB).
ASTB. Auxiliary Port Strobe (input, active
Low). In Multiplexed Control mode (C/K Low),
the rising (trailing) edge of ASTB strobes the
key data on pins AUXo-AUX7 into the
appropriate internal key register. This input is
ignored unless AFLG and C/K are both Low.
One byte of key data is entered on each ASTB
with the most significant byte entered first.
AUXo-AUX7' Auxiliary Port Bus (bidirectional,
active High). When the DCP is operated in
Multiplexed Control mode (C/K Low), these
eight lines form a key-byte input port, which
can be used to enter the master and session
keys. This port is the only path available for
entering the master key. (Session keys can also
be entered via the master port.) A UXo is the
low-order bit and is considered to be the parity
bit in key bytes. The most significant byte is
entered first.
When the DCP is operated in Direct Control
mode (C/K High), the auxiliary port's keyentry function is disabled and five of the eight
lines become direct control/status lines for
interfacing to high-speed microprogrammed
controllers. In this case, AUXo, AUXI and
AUXt have no function, and the other pins are
defined as follows:
AUX2-BSY. Busy (output, active Low). This
status output gives a hardware indication that
the ciphering algorithm is in operation.
AUX2-BSY is driven by the BSY bit in the
Status register such that when the BSY bit is 1
(active), AUX2-BSY is Low.
AUX3-CP, CommandPending (output, active
Low). This status output gives a hardware
indication that the DCP is ready to accept the
input of key bytes following a Low-to-High
transition on AUX7-K/D. AUX;3-CP is driven
by the CP bit in the Status register such that
yrhen the CP bit is 1 (active), AUX3-CP is
Low.
AUXs-S/S. Start/Stop (input, Low = Stop).
When this pin goes Low (Stop), the DCP
follows the normal Stop command sequence.
When this pin goes High, a sequence
equivalent to a Start Encryption· or Start
Decryption command is followed. When
Auxs-sis goes High, the level on AU%-E/D
selects either the start encryption or start
decryption operation.
AUXs-E/O. Encrypt/Decrypt (input,
Low
390
= Decrypt).
When AUXs-S/S goes High,
it initiates a normal data ciphering operation
whose input specifies whether the ciphering.
algorithm is to encrypt (E/D High) or decrypt
(E/D Low).
When AUX7-K/15 goes High, initiating the
entry of key bytes, the level on AU%-E/D
specifies whether the bytes are to be written
into the E ·Key register (E/D High) or the D key
Register (E/D Low).
The AU%-E/D input is not latched internally
and must be held constant whenever one or
more of Auxs-S/s, AUX7-K/D, AUX2-BSY, or
AUX3-CP are active. Failure to maintain the
proper level on A U%- E/D during loading or
ciphering operations results in scrambled data
in the internal registers.
AUX7-K/D. Key/Data (input, Low = Data).
When this signal goes High, the DCP initiates
a key-data input sequence as ifa Load Clear E
0r D Key Through Master Port command had
been entered. The level on AU%-E/D determines whether the subsequently entered clearkey bytes are written into the E key register
(E/D High) or the D key register (E/D Low)
AUX7-K/D and AUXs-S/S are mut~ally
exclusive control lines; when one goes active
(High), the other must remain inactive (Low)
until the first returns to an inactive state. In
addition, both lines must be inactive (Low)
whenever a transition occurs on C/K (entering
or exiting Direct Control mode).
C/K. Control/Key Mode Control. {input,
Low = Key}. This input determines the
operating characteristics of the DCP. A Low
input on C/K puts the DCP into the Multiplex. ed Control mode, enabling programmed
access to internal registers through the master
port and enabling input of keys through the
master or auxiliary port. A High input on C/K
specifies operation in Direct Control mode. In
this mode, several of the aUXiliary porL pins
become direct control status signals which can
be driven/sensed by high-speed controller
logiC, and access to internal registers through
the master port is limited to the Input or Output register.
CLK. Clock {input, TTL compatible}. An external timing source is input via the CLK pin.
The Data Strobe signals (MDS, SDS) must
change synchronously with this clock input, as
must Master Port Address Strobe (MAS) in
Multiplexed Control mode (CiK Low), and also
AUX7-K/D and Auxs-sis in Direct Control
mode (CiK High). In addition, the Auxiliary,
Master and Slave Port Flag outputs (AFLG,
MFLG, and SFLG) change synchronously with
the clock. When using the DCP with the Z8000
CPU in Multiplexed Control mode, the clock
input must agree in frequency and phase with
the processor clock; however, the DCP does
not require the high voltage levels of the processor clock.
Pin
Descriptions
(Continued)
MAs.
Master Port Address Strobe (input,
active Low). In Multiplexed Control mode
(C/K Low), an active (Low) signal on this pin
indicates the presence of valid address and
chip select information at the master port. This
information is latched internally on the rising
edge of Master Port Address Strobe (MAS).
When C/K is High (Direct Control mode),
MAS can be High or Low without affecting
DCP operation, except that, regardless of the
state of CIK, if both Master Port Address
Strobe (MAS) and Data Strobe (MDS) are Low
simultaneously, the DCP Mode register will be
reset to ECB mode. The master port is
assigned to clear data, the slave port is
assigned to enable data, and all flags remain
inactive.
MCS. Master Port Chip Select (input, active
High). This signal is used to select the master
port. In Multiplexed Control mode (C/K Low),
the level on MCS is latched internally on the
rising edge of Master Port Address Strobe
(MAS). This latched level is retained as long
as MAS is High; when MAS is Low, the latch
becomes invisible and the internal signal
follows the MCS input. In Direct Control mode
(C/K High), no latching of Master Port Chip
Select occurs; the level on MCS is passed
directly to the internal select circuitry,
regardless of the state of Address Strobe
(MAS).
MDS. Master Port Data Strobe (input, active
Low). When MDS is active and Master Port
Chip Select (MCS) is valid, it indicates that
valid data is present on MPa-MP7 during output. MDS and Master Port Address Strobe
(MAS) are normally mutually exclusive; if both
go Low simultaneously, the DCP is reset to
ECB mode and all flag~ remain inactive.
MFLG. Master Port Flag (output, active Low).
This flag is used to indicate the need for a data
transfer into or out of the master port during
normal ciphering operation. Depending upon
the control bits written to the Mode register,
the master port is associated with either the
Input register or the Output register.
If data is to be transferred through the
master port to the Input register, the MFLG
.reflects the contents of the Input register; after
any start command is entered, MFLG goes active (Low) whenever the Input register is not
full. MFLG is forced High by any command
other than a start. Conversely, if the master
port is associated with the Output register,
MFLG reflects the contents of the Output
register (exc~pt in single-port configuration).
MFLG goes active (Low) whenever the Output
register is not empty. In single-port configuration, MFLG reflects the contents of the Input
register, while the Slave Port Flag (SFLG) is
associated with the Output register.
MPO-MP7. Master Port Bus (input/output,
active High). These eight bidirectional lines
are used to specify internal register addresses
in Multiplexed Control mode (see C/K) and to
input and output data. The master port provides software access to the Status, Command
and Mode registers as well as the Input and
Output registers. The 3-state master port outputs are enabled only when the master port is
selected by Master Port Chip Select CMCS) .
being Low, with Master Port Read/Write
(MR/W) High, and strobed by a Low on the
Master Port Data Strobe (MDS). MPa is the
low-order bit. Data and key information is
entered into this port with most significant byte
input first.
MR/W. Master Port Read/Write (input,
Low = Write). This signal indicates to the
DCP whether the current master port operation
is a read (MR/W is High) or a write (MR/W is
Low), thereby indicating whether data is to be
transferred from or to an internal register.
MR/W is not latched internally and must be
held stable while Master Port Data Strobe
(MDS) is Low.
PAR. Parity (output, active Low). The DCP
checks all key bytes for correct (odd) pari ty as
they are entered through either the master port
(Multiplexed or Direct Control mode) or the
auxiliary port (Multiplexed Control mode
only). If any key byte contains even parity, the
PAR bit in the Status register is set to 1 and
PAR goes Low. The least significant bit of key
bytes is the parity.
SCS. Slave Pori Chip Select (input, active
Low). This signal is logically combined with
Slave Port Data Strobe (SDS) to facilitate slave
port data transfers in a bus environment. SCS
is not latched internally and can be permanently tied to Low without impairing slave
port operation.
SDS. Slave Pori Data Strobe (input, active
Low). When both SDS and SCS are Low, it
indicates to the DCP either that valid data is
on the SPa-SP7 lines for an input operation, or
that data is to be driven onto the SPa-SP7 lines
for output. The direction of data flow is determined by the control bits in the Mode register .
SFLG. Slave Pori Flag (output, active Low).
This output indicates the status of either the
Input'register or the Output register, depending on the control bits in the Mode register.
In single-port configuration, -SFLG goes active
during normal processing whenever the Output register is not empty. In dual-port configuration, SFLG reflects the content of
whichever register is associated with the slave
port. If the input register is assigned to the
slave port, SFLG goes active w4enever the
Input register is not full, once any of the start
commands has been entered; SFLG is forced
391
Pin
Descriptions
(Continued)
inactive if any other command is entered. If
the slave port is assigned to the Output
register, SFLG goes active whenever the Output register is not empty. In this case, SFLG
goes inactive if any command is aborted.
SPO-SP7. Slave Port Bus (bidirectional). The
slave port provides a second data inpuVoutput
interface to the DCP, allowing overlapped
Functional
Description
The overall design of the DCP, as shown
in Figure 3', is optimized to achieve high data
throughput. Data bytes can be transferred
through both the master and slave ports, and
key bytes can be written through both the auxiliary and master ports. Three 8-bit buses
(input, output and C bus) carry data and key
bytes between the ports and the internal
registers. Three 56-bit, write-only key registers
are provided for the Master (M) Key, the
Encryption (E) Key and the Decryption (D)
Key. Parity checking is provided on incoming
key bytes. Two 64-bit registers are provided
for initializing vectors (lVE and IVD) that are
required for chained (feedback) ciphering
modes. Three 8-bit registers (Mode, Command
and Status) are accessible through the master
port.
Algorithm Processing.
The algorithm processing unit of the DCP (Figure 3) is designed
to encrypt and decrypt data according to the
National Bureau of Standards' Data Encryption
Standard (DES), as specified in Federal Information Processing Standards Publication 46.
The DES specifies a method for encrypting
64-bit blocks of clear data ("plain text") into
corresponding 64-bit blocks of "cipher text."
input, output, and ciphering operations. The
3-state slave port outputs are driven only when
Slave Port Chip Select (SCS) and Slave Port
Data Strobe (SDS) are both Low, SFLG isO,
and the internal port control configuration
allows output to the slave port. SPa is the low
order bit. The most significant byte of data
blocks is entered or retrieved through this port
first.
The DCP offers three ciphering methods,
selected by the cipher type field of the Mode
register: Electrqnic Code Book (ECB), Cipher
Block Chain (CBC) and Cipher Feedback
(CFB). These niethods are implemented in
accordance with Federal Information Processing Standards, Publication 46.
Electronic Code Book (ECB) is a straightforward implementation of the DES: 64 bits of
clear data in, 64 bits of cipher text out, with no
cryptographic dependence between blocks.
Cipher Block Chain (CBC) also operates on
blocks of 64 bits, but it includes a feedback
step which chains consecutive blocks so that
repetitive data in the plain text (such as ASCII
blanks) does not yield repetitive cipher text.
CBC also provides an error extension
characteristic which protects against
fraudulent data insertions and deletions.
Cipher Feedback (CFB) is an additive
stream cipher method in which the DES
algorithm generates a pseudorandom binary
stream, which is then exclusive-ORed with the
clear data to form the Cipher text. The cipher
text is then fed back to form a portion of the
next DES input block. The DCP implements
8-bit cipher feedback, with data input, output,
PARITY BIT
MUX/DIRECT
CONTROL
I
CLOCK
==.;:.;.:,...--+-----If-+-f-P-I
~
MASTER {
PORT
CONTROL
INPUTS
MASTER PORT
FLAG
MAS
-
MD~ •
MRIW
MFTIi
C BUS
KEY
8
OR~
DATA MPo-MP,
OUTPUT BUS
INPUT BUS
Figure 3. Z8068 Block Diagram
392
2080-003
Functional
Description
(Continued)
figuration bits are set to master port only
(Figure 4). In this operating configuration, the
encrypt/decrypt bit (~) controls the processing of data. Data to be encrypted or decrypted
is written to the master port Input register
address. To facilitate monitoring of the Input
register status, the MFLG signal goes Low
when the Input register is not full. Data is read
by the master CPU through the master port
Output register address. Pin SFLGgoes Low
when the Output register is not empty. MFLG
is then redefined as a master input flag and
SFLG is redefined as a master output flag.
and feedback paths of one byte wide. This
method is useful for low speed, character-at-atime, serial communications.
Multiple Key Registers. The DCP provides
the necessary registers to implement a
multiple-key or master-key system. In such an
arrangement, a single master key, stored in
the DCP M key register, is used to encrypt sessionkeys for transmission to remote DES
equipment and to decrypt session keys
received from such equipment. The M Key
register may be loaded (with plain text) only
through the auxiliary port, using the Load
Clear Master Key command. In addition to the
M Key register, the DCP contains two session
key registers: the E key register, used to encrypt clear text, and the D key register, used
to decrypt cipher text. All three registers are
loaded by writing commands such as Load
Clear E Key, through master port, into the
Command. register, and then writing the eight
bytes of key data to the port when the Command Pending bit in the Status register is 1.
Operating Modes: Multiplexed Control vs.
Direct Control. The DCP can be operated in
either of two basic interfacing modes, determined by the logic level on the C/K input pin.
In Multiplexed Control mode (C/K Low), the
DCF is configured internally to allow a master
CPU to address five of the internal control/status/data registers directly, thereby controlling the· device via mode and command
values written to these registers. Also, in this
mode, the auxiliary port is enabled for keybyte input.
If the logic level on C/K is brought High,
the DCP enters Direct Control mode, and the
auxiliary port pins are converted into direct
hardware status or control signals capable of
instructing the DCP to perform cf functionally
complete subset of its Cipher processing at
very high throughputs. This operating mode is
particularly well suited for Ciphering data for
high-speed peripheral devices such as
magnetic disk or tape.
AUXILIARY
PORT
CPU BUS
MASTER
PORT
Figuro 4. Single-Port Configuration. Mu'ltiplexed Control
AUXILIARY
PORT
CPU BUS
MASTER
\ . - - - - - - - . / 1 PORT
COMMANDS
ENCRYPT AND DECRYPT
KEYS CLEAR TEXT
IJL-----l\
Dual Port, Master Port Clear
Configuration. In the dual-port configurations, both the master and slave ports are used
for data entry and removal (Figures 5a and
5b). In the master port clear configuration,
clear text for encryption can be entered only
through the master port, and clear text
resulting from decryption can be read only
through the master port. Cipher text can be
handled only through the slave port. The
actual direction of data flow is controlled
either by the encrypt/decrypt bit (M4) in the
Mode register or by the Start Encryption or
Start Decryption commands. If encryption is
specified, clear data will flow through the
master port to the Input register, and cipher
data will be available at the slave port when it
is ready to be read from the Output register.
F or decryption, the process is reversed, with
Cipher data written to the Input register
STATUS
K
~COMMANDS'"
r
HOST
SYSTEM
SLAVE
Figure Sa. Dual-Port Configuration. Multiplexed Control
Single-Port Configuration. The simplest configuration occurs when the Mode register conA
DCP
PORT I\':~=':"":"::':":"'/I
......_-----1
Data Flow. Bits M2 and M3 of the Mode
register control the flow of data into and out of
the DCP through the master and slave ports.
Three basic configurations are prOVided: one
single-port and two dual-port.
HIGH·SPEED
MICROPROGRAMMED
DEVICE
DCP
COMMANDS
ENCRYPT AND DECRYPT
KEYS, CLEAR TEXT
CIPHER TEXT
<
COMMANDS
ENCRYPT AND DECRYPT
KEYS CLEAR TEXT
}'"""'"
PORT
>
MASTER
PORT
DCP
S~~~~
A
~.I
CIPHER TEXT)I
'f
YI
PERIPHERAL
DEVICE OR
BUFFER
I
Figure 5b. Dual-Port Configuration. Direct Control
2080-004,005,006
393
Functional
Description
(Continued)
through the master port. Slave port and clear
text read from the Master port.
In both dual-port configurations, the Master
Port Flag (MFLG) and the Slave Port Flag
(SFLG) are used to indicate the status of the
data register associated with the master port
and slave port, respectively. For example, during encryption in the master port clear configuration, MFLG goes Low (active) when the
Input register is not full; SFLG goes Low
(active) when the Output register is not empty.
If cyphering operation changes direction,
MFLG and SFLG switch their register association (see Table 1).
Mode Register Bits
Encryptl
Port
Decrypt Configuration.
Bit M4 Bit M3 Bit M2
a
a
a
a
a
1
1
1
a
a
1
1
a
1
a
a
1
a
Input
Register
Flag
Output
Register
Flag
SFLG
MFLG
SFLG
MFLG
SFLG
SFLG
Table 1. Association of Master Port Flag (MFLG)
and Slave Port Flag (SFLG)
with Input and Output Registers
Dual Port, Slave Port Clear Configuration.
This configuration is identical to the previously
described dual-port, master port clear configuration except that the direction of ciphering is reversed. That is, all data flOWing in or
out of the master port is cipher text, and all
data at the slave port is clear text.
Master Port Read/Write Timing. The master
port of the DCP is designed to operate directly
with a multiplexed address/data bus such as
the Zilog Z-BUS. Several features of the master
port logic are:
[J
II]
The level on Master Port Chip Select (MCS)
is latched internally on the rising (trailing)
edge of Master Port Address Strobe (MAS).
This action relieves external address decode
circuitry of the responsibility for latching
chip select at address time.
The levels on MPI and MP2 are also latched
internally on the rising edge of MAS and
are subsequently decoded to enable reading
and writing of the DCP's internal registers
(Mode, Command, Status, Input and Output). This action also eliminates the need for
external address latching and decoding.
c Data transfers through the master port are
controlled by the levels and transitions on
Master Port Data Strobe (MDS) and Master
Port Reac:l/Write (MR/W). The former controls the timing and the latter controls the
transfer direction. Data transfers disturb
neither the chip-select nor address latches,
394
so once the DCP and a particular register
have been selected, any number of reads or
writes of that register can be accomplished
without intervening address cycles. This
feature greatly speeds up the loading of
keys and data, given the necessary transfer
control external to the DCP.
Loading Keys and Initializing Vector (IV)
Registers. Because the key and InitialiZing
Vector (IV) registers are not directly
addressable through any of the DCP's ports,
keys and vector data must be loaded (and in
the case of vectors, read) via \\command data
sequences." Most of the commands recognized
by the DCP are of this type. A load or read
command is written to the Command register
·through the master port. The command processor responds by asserting the Command
Pending output. The user then either writes
eight bytes of key or vector data through the
master or auxiliary port, as appropriate to the
speCific command, or reads eight bytes of vector data from the master port.
In Direct Control mode, only the E Key and
D Key registers can be loaded; the M Key and
IV registers are inaccessible. Loading the E
and D Key registers is accomplished by placing the proper state on the AU%-E/D input
(High for E Key, Low for D Key) and then raising the AUX7-K/D input-indicating that key
loading is required. The command processor
attaches the proper key register to the master
port and asserts the AUX3-CP (Command
Pending) signal (active Low). The eight key
bytes can then be written to the master port. In
the Multiplexed Control mode, all key and
vector registers can be written to and all but
the Master (M) Key register can be loaded with
encrypted, as well as clear, data. If the operation is a Load Encrypt command, the subsequent data written to the master or auxiliary
port (as appropriate) is routed first to the Input
register and decrypted before it is written into
the speCified key or InitialiZing Vector
register.
Parity Checking of Keys. Key bytes contain
seven bits of key information and one parity
bit. By DES deSignation, the low-order bit is
the parity bit. The parity-check circuit is
enabled whenever a byte is written to one of
three key registers. The output of the paritycheck circuit is connected to PAR and the
state of this Signal is reflected in Status register
'bit PAR (S3)' Status register bit PAR goes to 1
whenever a byte with even parity (an even
number of 1s) is detected. In addition to the
PAR bit, the Status register has a Latched Parity bit (LP AR, S4) that is set to 1 whemever the
Status register PAR bit goes to 1. Once set, the
LPAR bit is not cleared until a reset occurs or
a new Load Key command is issued.
Functional
Description
(Continued)
When an encrypted key is entered, the
parity-check logic operates only after the
decrypted key is available. The encrypted data
is not checked for parity. The PAR signal
reflects the state of the decrypted bytes on a
byte-to-byte basis as they are clocked through
the parity-check logic on their way to the key
register. Thus, the time during which PAR
indicates the status of a byte of decrypted key
data may be as short as four clock cycles. The
LPAR bit in the Status register indicates if any
erroneous bytes of key data were entered.
Programming
Initialization. The DCP can be reset in
several ways:
Hex
Code
[J
By the "Software Reset" command.
[J
By a hardware reset, which occurs
whenever both MAS and MDS go Low
simultaneously.
lJ
By writing to the Mode register.
[J
By aborting any command.
These sequences initiate the same internal
operations, except that loading the Mode
register or aborting any command does not
subsequently reset the Mode register. Once a
reset process starts, the DCP is unable to
respond to further commands for approximately five clock cycles. If a power-up hardware
reset is used, the leading edge of the reset
signal should not occur until approximately 1
ms after Vee has reached normal operating
voltage. This delay time is needed for internal
signals to stabilize.
Registers. The registers in the DCP that can
be addressed directly through the master port
are shown with their addresses in Table 2. A
brief description of these registers and those
not directly accessible follows.
X
X
0
0
1
X
X
X
0
0
1
1
1
X
X
X
0
1
0
1
X
X
0
1
0
0
0
0
0
1
0
0
Input Register
Output Register
Command Register
Status Register
Mode Register
No Register Accessed
Input Register
Output Register
AUX7 -K/O
Pins
AUXs-E/D
H
H
H
H
H
H
H
L
L
L
L
t
t
1
H
Data
L
H
X
L
H
X
X
Data
Load
Load
Load
Load
Load
Clear
Clear
Clear
Clear
Clear
M Key Through AUXiliary Port
E Key Through AUXiliary Port
D Key Through Auxiliary Port
E Key Through Master Port
D Key Through Master Port
B1
B2
31
32
Load
Load
Load
Load
Encrypted
Encrypted
Encrypted
Encrypted
85
84
A5
A4
Load
Load
Load
Load
Clear rVE Through Master Port
Clear IVD Through Master Port
Encrypted IVE Through Master Port
Encrypted IVD Through Master Port
8D
8C
A9
A8
Read
Read
Read
Read
Clear IVE Through Master Port
Clear rVD Through Master Port
Encrypted IVE Through Master Port
Encrypted IVD Through Master Port
39
41
40
CO
Encrypt With Master Key
Start Encryption
Start Decryption
Start
EO
00
Stop
Software Reset
E Key Through Auxiliary Port
D Key Through AUXiliary Port
E Key Through Master Port
D Key Through Master Port
N
•
t'J
n
•
AUXs-S/S Command Initiated
t
t
1
L
L
L
H
Data
=
N
0
=
Command Register. Data written to the 8-bit,
write-only Command register through the
master port is interpreted as an instruction. A
detailed description of each command is given
in the Commands section; the commands
and their hexadecimal representations are
summarized in Table 3. A subset of these
commands can be entered implicitly in Direct
Control mode (elK High)-even though the
Command register cannot be addressed in that
mode-by transitions on auxiliary lines
AUX5-S/S, AU~-E/D, and AUX7-K/D. These
implicit commands are summarized in Table 4.
Table 2. Master Port Register Addresses
C/K
90
91
92
11
12
Table 3. Command Codes in Multiplexed Control Mode
C/K MP2 MPI MR/W MCS Register Addressed
0
0
0
0
0
X
1
1
Command
Start Decryption
Start Encryption
Stop
Load D Key Clear through master port
Load E Key Clear through master port
End Load Key command
Not allowed
AUX, pins become Key-Byte inputs
Table 4. Implicit Command Sequences in Direct Control Mode
395
Programming
(Continued)
396
Status Register. The bit assignments in the
read-only Status register are shown in Figure
6. The PAR, AFLG, SFLG and MFLG bits
indicate the status of the corresponding output
pins, as do the busy and command pending
bits when the DCP is in a Direct Control mode
(C/K High). In each case, the output signal
will be active Low when the corresponding
status bit is a 1. The parity bit indicates the
parity of the most recently entered key byte.
The LPAR bit indicates whether any key byte
with even parity has been encountered since
the last Reset or Load Key command.
The Busybit is 1 whenever the ciphering
algorithm unit is actively encrypting or
decrypting data, either as a response to a command such as Load Encrypted Key (in which
case the Command Pending bit is 1) or in the
ciphering of regular text (indicated by the
Start/Stop bit being 1). If the ciphered data
cannot be transferred to the Output register
because that register still contains output from
a previous ciphering cycle, the Busy bit
remains 1 even after the ciphering is complete.
Busy is a at all other times, even when Ciphering is not possible because data has not been
written to the Input register.
The Command Pending bit is set to 1 by any
command whose execution requires the
transfer of data, to or from a nonaddressable
internal register, such as when writing key
bytes to the E key register or reading bytes
from the IVE register. Thus, the Command
Pending bit is set follOWing all commands ex-
cept the three start commands, the Stop command and the Software Reset command. The
Command Pending bit returns to a after all
eight bytes have been transferred following
Load Clear, Read Clear, or Read Encrypted
commands; and after data has been transferred, decrypted, and loaded into the desired
register follOWing Load Encrypt commands.
The Start/Stop bit is set to 1 when one of the
start commands is entered and it is reset to a
whenever a reset occurs or when a new command other than a Start is entered.
Mode Register. Bit assignments in this 5-bit
read/write register are shown in Figure 7. The
Cipher type bits (Ml and Mo) indicate to the
DCP which ciphering algorithm is to be used.
On reset, the Cipher Type mode defaults to
Electronic Code Book mode.
Configuration bits (M3 and M2) indicate
which data ports are to be associated with the
Input and Output registers and flags. When
these bits are set to the single-port, masteronly configuration (M3 M2 = 10), the slave
port is disabled and no manipulation of Slave
Port Chip Select (SCS) or Slave Data Strobe
(SOS) can result in data movement through the
slave port; all data transfers are accomplished
thtough the master port, as previously
described in the Functional Description. Both
MFLG and SFLG are used in this configuration; MFLG gives the status of the Input
register and SFLG gives the status of the Output register.
When the configuration bits are set to one of
the dual-port configurations (M3 M2 = 00 or
01), both the master and slave ports are
available for input and output. When M3,
M2 = 01 (the default configuration), the
master port handles clear data while the slave
port handles encrypted data. Configuration
M3, M2 = 00 reverses this assignment. Actual
data direction at any particular moment is controlled by the Encrypt/Decrypt bit.
The Encrypt/Decrypt bit (~) instructs the
DCP algorithm processor to encrypt or decrypt
the data from the Input register using the
Ciphering method specified by the Cipher
Type bits. The Encrypt/Decrypt bit also controls data flow within the DCP. For example,
when the configuration bits are 0,1 (dual-port,
master clear, slave encrypted) and the
Encrypt/Decrypt bit is 1 (encrypt), clear data
will flow into the DCP through the master port
and encrypted data will flow out through the
slave port. When the Encrypt/Decrypt bit is set
to a (decrypt), data flow is reversed.
L MASTER PORT FLAG
~
o
= INACTIVE
1 = ACTIVE
SLAVE PORT FLAG
INACTIVE
1
ACTIVE
o=
=
AUXILIARY PORT FLAG
INACTIVE
1 = ACTIVE
o=
~--- PARITY (PAR)
o = ODD PARITY
1
= EVEN PARITY
' - - - - - - LPAR
o = ALL
BYTES HAD
ODD PARITY
1
= ONE OR MORE BYTES
HAD EVEN PARITY
' - - - - - - - BUSY
o = NOT BUSY
1
= BUSY
' - - - - - - - - COMMAND PENDING
INACTIVE
l'
ACTIVE
o=
=
~------ START/STOP
STOP ENTERED
START ENTERED
1
o=
=
Figure 6. Status Register Bit Assignments
RESERVED
I
L """ ""
00
01
10
11
= ELECTRONIC CODE BOOK (DEFAULT)
= CIPHER FEEDBACK
= CIPHER BLOCK CHAIN
= RESERVED
PORT CONFIGURATION
00 = DUAL PORT, MASTER
ENCRYPTED, SLAVE CLEAR
01 = DUAL PORT, MASTER CLEAR,
SLAVE ENCRYPTED (DEFAULT)
10 = SINGLE PORT, MASTER ONLY
11 = RESERVED
' - - - - - - ENCRYPTIDECRYPT
1 = ENCRYPT
o = DECRYPT
Figure 7. Mode Register Bit ASSignments
2080-007, 008
Programming
(Continued)
Input Register. The 64-bit, write-only Input
register is organized to appear to the user as
eight bytes of pushdown storage. A status circuit monitors the number of bytes that have
been stored. The register is considered empty
when the data stored in it has been or is being
processed; it is considered full when one byte
of data has been entered in Cipher Feedback
mode or when eight bytes of data have been
entered in Electronic Code Book or Cipher
Block Chain mode. If the user attempts to write
data into the Input register when it is full, the
Input register disregards the attempt; no data
in the register is destroyed.
Output Register. The 64-bit, read-only Output
register is organized to appear to the user as
eight bytes of pop-up storage. A status circuit
detects the number of bytes stored in the Output register. The register is considered e~pty
when all the data stored in it has been read by
the master CPU and is considered full if it still
contains one or more bytes of output data. If a
user attempts to read data from the Output
register when it is empty, the buffers driving
the output bus remain in a 3-state condition.
M, E, D Key Registers. The following
multibyte key registers cannot be addressed
directly, but are loaded in response to commands written to the Command register.
Commands
There are three 64-bit, write-only key
registers in the DCP: the Master (M) Key
register, the Encrypt (E) key register, and the
Decrypt (D) key register. The Master key
register can be loaded only with clear data
through the auxiliary port. The Encrypt and
Decrypt Key registers can be loaded in any of
four ways: (l) as clear data through the auxiliary port, (2) as clear data through the master
port, (3) as encrypted data through the auxiliary port, or (4) as encrypted data through
the master port. In the last two cases, the
encrypted data is first routed to the Input
register, decrypted using the M Key, and finally written to the target key register from the
Output register.
Initializing Vector Registers (IVE and
IVD). Two 64-bit registers are provided to
store feedback values for cipher feedback and
chained block ciphering methods. One initializing vector register (lVE) is used during
encryption, the other (lVD) is used during
decryption. Both registers can be loaded with
either clear or encrypted data through the
master port (in the latter case, the data IS
decrypted before being loaded into the IV
register), and both may be read out either
clear or encrypted through the master port.
(91H).
Each byte is written to its respective key
register by placing an active Low signal on the
Auxiliary Port Strobe (ASTB) once data has
been set up on the aUXiliary port pins. The
actual write process occurs on the rising (trailing) edge of ASTB. (See Switching Characteristics section for exact setup, strobe width, and
hold times.)
The Auxiliary Port Flag (AFLG) goes inactive immediately after the eighth strobe goes
active (Low). However, the Command Pending
bit (S6) remains 1 for several more clock
cycles, until the key loading process is completed. All key bytes are checked for correct
(odd) parity as they are entered.
Load Clear D Key Through Auxiliary Port
Load Clear E Key Through Master Port
All operations of the DCP result from command inputs, which are entered in Multiplexed
Control mode by writing a command byte to
the Command register. Command inputs are
entered in Direct Control mode by raiSing and
lowering the logic levels on the AUX7-K/D,
AUX6-E/15, and AUX5-S/S pins. Table 3 shows
all commands that can be given in Multiplexed
Control mode. Table 4 shows a subset of the
impliCit commands that can be executed in the
Direct Control mode.
Load Clear M I{ey Through Auxiliary Port
(90H).
Load Clear E Key Through Auxiliary Port
(92H).
These commands may be used only for
multiplexed operations; they override the data
flow specifications set in the Mode register and
cause the Master (M) Key, Encrypt (E) Key, or
Decrypt (D) Key register to be loaded with
eight bytes written to the auxiliary port. After
the Load command is written to the Command
register, the Auxiliary Port Flag (AFLG) goes
active (Low) and the corresponding bit in the
Status register (S2) becomes I, indicating that
the device is able to accept key bytes at the
auxiliary port pins. Additionally, the Command Pending bit (S6) becomes 1 duri;ng the
entire loading process.
(llH).
Load Clear D Key Through Master Port
(12H).
These 'commands are available in both
Multiplexed Control and Direct Control
modes. They override the data flow specifications set in the Mode register and attach the
master port inputs to the Encrypt (E) Key or
Decrypt (D) Key register, as appropriate, until
eight key bytes have been written. In
Multiplexed Control mode, the command is
initiated by writing the Load command to the
Command register. In Direct Control mode,
the command is initiated by raising the
AUX7-K/D control input while the AUX5-S/S
397
Commands
(Continued)
input is Low. In this latter case, the level on
AU%-E/D determines which key register is
written (High = E register).
Once the command has been recognized,
the Command Pending bit (S6 in the Status·
register) becomes 1. In Direct Control mode,
AUX3-CP goes active (Low), indicating that
key entry may proceed. The host system then
"writes exactly eight bytes to the master port (at
the Input register address in Multiplexed Control mode). When the key register has been
loaded, the Command Pending bit returns to
'0. In Direct Control mode, the AUX3-CP output goes inactive, indicating that the DCP can
accept the next command.
Load Encrypted E Key Through Auxiliary
Port (BIH).
Load Encrypted D Key Through Auxiliary
Port (B2H).
These commands are used in Multiplexed
Control mode only. Their execution is similar
to that of the Load Clear E (D) Key Through
Auxiliary Port command, except that key bytes
are first decrypted using the electronic code
book algorithm and the Master (M) Key
register. The key bytes are then loaded into
the appropriate key register, after having
passed through the parity-check logic.
The Command Pending bit (S6) is 1 during
the entire decrypt-and-load operation. In addition, the Busy bit (S5) is 1 during the actual
decryption process.
Load Encrypted E Key Through Master Port
(3IH).
Load Encrypted D Key Through Master Port
(32H).
These commands are used in Multiplexed
Control mode only. Their execution is similar
in effect to that of the Load Clear E (D) Key
Through Master Port command. The commands
differ in that key bytes are initially decrypted
using the electronic code book algorithm and
the Master (M) Key register. Once decrypted,
they are loaded byte-by-byte into the target
key register, after having passed through the
parity-check logic.
The command pending bit (S6) is 1 during
the entire decrypt-and-load operation. In addition, the busy bit (S5) is 1 during the actual
decryption process.
Load Clear IVE Register Through
Master Port (8SH)
Load Clear IVD Register Through
Master Port (84H)
These commands are used in Multiplexed
Control mode only. Their execution is virtually
identicalto that of the Load Clear E (or D) Key
Through Master Port command. The commands
differ in that the data written to the input
register address is routed to either the Encryption Initializing Vector (lVE) or DecryptIon'
Initializing Vector (IVD) register instead of a
key register. No parity checking occurs. The
398
Commtlnd Pending bit (S6) is 1 during the
entire loading process.
Load Encrypted IVE Register Through
Master Port (ASH).
Load Encrypted IVD Register Through
Master Port (A4H).
These commands are analogous to the Load
Encrypted E (or D) Key Through Master Port
command. The data flow specifications set in
the Mode register are overridden and the eight
vector bytes are decrypted using the Decryption (D) Key register and the electronic code
book algorithm. The resulting clear vector
bytes are loaded into the target Initializing
Vector register. No parity checking occurs.
The Busy bit (S5) does not become 1 during
the decryption process, but the Command
Pending bit (S6) is 1 during the entire
decryption-and-load operation.
Read Clear IVE Register Through
Master Port (8DH).
Read Clear IVD Register Through
Master Port (8CH).
In the Multiplexed Control mode, these commands override the data flow specifications
set in the Mode register and connect the
appropriate Initializing Vector register to the
master port at the Output register address. In
this state, each IV register appears as eight
bytes of FIFO storage. The first byte of data is
available six clocks after loading the Command register. The Command Pending bit in
the Status register remains a 1 until sometime
after the eighth byte is read out. The host
system is responsible for reading exactly eight
bytes.
Read Encrypted IVE Register Through
Master Port (A9H).
Read Encrypted IVD Register Through
Master Port (A8H).
In the Multiplexed Control mode only, these
commands override the specifications set in
the Mode register and encrypt the contents of
the specified Initializing Vector register using
the electronic code book algorithm and the
. Encrypt (E) key. The resulting cipher text is
placed in the output register, where it can be
read as eight bytes through the master port.
During the actual encryption process, the Busy
bit (S5) is 1. When the Busy bit becomes 0, the
encrypted vector bytes are ready to be read
out. The Command Pending bit (S6) is 1
during the entire encryption and output process; it becomes 0 when the eighth byte is read
out. The host system is responsible for reading
exactly eight bytes.
Encrypt with Master (M) Key (39H).
In the Multiplexed Control mode; this command overrides the data flow specifications set
in the Mode register and causes the DCP to
accept eight bytes from the master port, which
are written to the Input register. When eight
bytes ha~e been received, the DCP encrypts
Commands
(Continued)
the input using the Master (M) Key register.
The encrypted data is loaded into the Output
register, where it can be read out through the
master port. The Command Pending bit (S6)
and the Busy (Ss) bit are used as status
indicators in the three phases of this operation.
The Command Pending bit becomes 1 as
soon as the Input register can accept data.
When exactly eight bytes have been entered,
the Busy bit becomes and remains 1 until the
encryption process is complete. When 'Busy
becomes 0, the encrypted data is available to
be read out. The Command Pending bit
returns to 0 when the eighth byte has been
read.
Start Encryption (41H)
Start Decryption (40H)
Start (COH) . .
The three start commands begin normal data
ciphering by setting the Status register's
Start/Stop bit (S7) to 1. The Start Encryption
and Start Decryption commands explicitly
specify the ciphering direction by forCing the
Encrypt or Decrypt bit (M4) in the Mode
register to 1 or 0, respectively. The Start command, however, uses the current state of the
Encrypt/Decrypt bit, as speCified in a previous
Mode register load.
When a start command has been entered,
the port status flag (MFLG or SFLG) associated with the Input register becomes active
(Low), indicating that data may be written to
The control and/or data signals and the
Timing
Requirements timing requirements for clock/reset, Direct
Control mode, Multiplexed Control mode
(master port)' master (slave) port read/write,
and auxiliary port key' entry functions are
illustrated in Figures 8 through 12. The ac
switching characteristics of the signals
involved in the above functions are described
in the AC Characteristics. The specific timing
periods described are identified by numerics
(1 through 48), which are referenced in both
the timing diagrams and in the AC
Characteristics.
A two-to-seven character symbol is listed in
AC Characteristics for each period described.
The symbol speCifies the signal(s) involved, the
state of each signal, and optionally, the port
associated with a signal. Symbols are encoded
as follows:
General Form: Ta Ab (Cb)
Where:
(1) T is a constant.
(2) a represents anyone of the following sym-
bols:
Symbol
c
d
f
Meaning
Clock
Delay
Fall Time
the Input register to begin ciphering.
In Direct Control mode, the Start command
is issued by raising the level on the AUXs-S/S
input (Table 4). The ciphering direction is
specified by the level on AU~-E/D. If
AU~-E/D is High when AUXs-S/S goes High,
the command is Start Encryption; if A U%- E/D
is Low, it is Start Decryption.
Stop (EOH).
The Stop command clears the Start/Stop bit
(S7) in the Status register. This action causes
the input flag (MFLG or SFLG) to become
inactive and inhibits the loading of any further
input into the algorithm unit. If ciphering is in
progress [Busy bit (Ss) is 1 or AUX2-BSY is
active], it is allowed to finish, and any data in
the Output register remains accessible.
In Direct Control mode, the Stop command
is implied when the signal level on the
Auxs-s/s input goes from High to Low
(Table 4).
Software Reset (00).
This command has the same effect as a hardware reset (MAS and MDS Low): it forces the
DCP back to its default configuration, and all
processing flags go into Inactive mode. The
default configuration includes setting the Mode
register to Electronic Code Book ciphering
mode and establishes a dual-port configuration
. with master port clear and slave port
encrypted.
Hold Time
Rise Time
Setup Time
Width
w
(3) A,C represent any of the following signal
names:
h
r
s
Symbol
A
B
C
D*
E
F*
G*
K
M
N
P
Q*
R
S*
W
Signal Name
Address Strobe
BSY, Busy
Clock
Data In or the address
at the master port.
E/D, EnablelDisable
Flag (MFLG, SFLG, or
(AFLG)
Data Strobe (MDS',
SDS, or ASTB)
KID, KeylData
CIK, Control/Key
Mode
SIS, Start/Stop
PAR, Parity
Data Out (master or
slave port)
CP, Clock Pulse
Chip Select (master or
slave port)
MRIW, Master Port
read/write
399
(4)
Timing
Requirements
(Continued)
b represents anyone of the
following signal state descriptors (symbol).
.
Symbol
h
I
For example: Dl specifies data
in at Master Port; F2 specifies
Slave Port flag-SFLG.
State Indicated
High
Low
Valid
Invalid
High Impedance
* These signal names may be
tnbdified by the folloWing optional numeric port identifiers:
Identifier Port
I
Master Port
2
Slave Port
3
AUX (Key) Port
v
x
z
Figure 8. Clock and Reset
II
AC
Switching
Characteristics
Number
Parameter
Syhlbol
Min
Max
Notes*t
Clock
1
2
3
nvCh
TwCl
Tbc
Clock Width (High)
Clock Width (Low)
Clock Cycle Time
105
105
250
Reset
4TdGhl(Glh) MDS*MAS Low to MDS*MAS High - - TC - - - - - - - - - (Reset Pulse Width)
TdC(Glh)
Clock High to MDS*MAS High
0
50
5
Direct Control Mode
T~Ni? Data Bus (bidirectional, 3-state). These
lines carry data and commands to and from
the SCC.
DTR/REQA. DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
IEI is used with IEO to form an interrupt daisy
chain when there i~ more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
410
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
SCC requests an interrupt.
IN TACK. Interrupt AckrlOwledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
SCC interrupt daisy chain settles. When RD
becomes active, the SOC places an interrupt
vector on the data bus (if IEI is High).
INTACK is latched by the rising edge
of PCLK.
.
PCLK. Clock (input). This is the master SCC
clock used to synchronize internal signals
PCLK is a TTL level signal.
RD. Read (input, active Low). ni.is signal indicates a read operation and when the SCC is
selected, enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus
if the SCC is the highest priority device
requesting an interrupt.
RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock for the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be I, 16, 32, or 64 times the
data rate in. Asynchronous modes.
RTSA. RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 11) is set, the
RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto
Pin
Description
(Continued)
Functional
Description
Enable is on, the signal goes High after the
transmitter is empty. In Synchronous mode or
in Asynchronous mode with Auto Enable off,
the RTS pin strictly follows the state of the RTS
bit. Both pins can be used as general-purpose
outputs.
SYNCA. SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either
as inputs, outputs, or part of the crystal
oscillator circuit. In the Asynchronous Receive
mode (crystal oscillator option not selected),
these pins are inputs similar to CTS and DCD.
In this mode, transitions on these lines affect
the state of the Synchronous/Hunt status bits in
Read Register 0 (Figure 10) but have no other
function.
In External Synchronization mode with the
crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be
driven Low two receive clock cycles after the
last bit in the synchronous character is
received. Character assembly begins on the
rising edge of the receive clock immediately
preceding the activation of SYNC.
In the Internal Synchronization mode
(Monosync and Bisync) with the crystal
oscillator not selected, these pins act as outputs and are active only during the part of the
receive clock cycle in which synchronous
characters are recognized. The synchronous
condition is not latched, so these outputs are
active each time a synchronization pattern is
recognized (regardless of character boundaries). In SDLC mode, these pins act as
outputs and are valid on receipt ofa flag.
TxDA. TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.
--- --TRxCJ.'I\. TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply the output of the Digital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output
mode.
WR. Write (input, active Low). When the SCC
is selected, this signal indicates a write
operation. The coincidence of RD and WR is
interpreted as a reset.
W IREQA. W IREQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low 'when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The
reset state is Wait.
The functional capabilities of the SCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols; as a
microprocessor peripheral, the SCC offers
valuable features such as vectored interrupts,
polling, and simple handshake capability.
follOWing description briefly detail these
protocols.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
Data Communications Capabilities. The
SCC provides two independent full-duplex
channels programmable for use in' any common Asynchronous or Synchronous datacommunication protocol. Figure 3 and the
!sr
PARITY
STfT
-MA-R-KI-NG-L-IN-E---'II
DATA
II
p
I I
""1-DA-T-A"""""'1""'1-'11
DATA
III
I MARKING LINE
ASYNCHRONOUS
DATA
SYNC
::
I
DATA
CRCl
CRC2
DATA
CRCl
CRC2
DATA
CRCl
CRC2
CRCl
CRC2
MONOSYNC
SYNC
,
SYNC
DATA
SIGNAL
I
DATA
::
BISYNC
::
EXTERNAL SYNC
FLAG
I
ADDRESS
I
INFO{M;TlON
FLAG
SDLC/HDLC/X.25
Figure 3. Some
2042-108
see Protocols
411
Functional
Description
( Continued)
mechanism that checks the signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure 1). If the Low does not persist (as in the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The SCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of I, 1/16, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
Synchronous Modes. The SCC supports both
byte-oriented and bit-oriented synchronous
communica tion. Synchronous byte-oriented
protocols can be handled in several modes,
allowing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync),
any 12-bit synchronization pattern (Bisync), or
with an external synchronous signal. Leading
sync characters can be removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the SCC
by overlapping the larger pattern across multiple incoming synchronous characters as shown
in Figure 4.
CRC checking for Synchronous byteoriented modes is delayed by one character
time so that the CPU may disable CRC checking on specific characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-16 (X 16 + XI5 + X2 +. 1) and
CCITT (X16 + XI2 + X5 + 1) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all Os. The SCC also provides a feature that automatically transmits
CRC data when no other data is available for
transmission. This allows for high speed
transmissions under DMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in. Synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous
characters, regardless of the programmed
character length.
The SCC supports Synchronous bit-oriented
protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion,
and CRC generation. A special command can
be used to abort a frame in transmission. At
the end of a message, the SCC automatically
transmits the CRC and trailing flag when the
transmitter underruns. The transmitter may
also be programmed to send an idle line consisting of continuous flag characters or a
steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The SCC may also be
programmed to send an abort itself in case of
an underrun, relieVing the CPU of this task.
One to eight bits per character can be sent,
allowing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be
programmed to search for frames addressed by
a single byte (or four bits within a byte) of a
user-selected address or to a global broadcast
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (endof-frame) can be selected. The receiver
automatically deletes all Os inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SDLC
mode, the SCC must be programmed to use
the SDLC CRC polynomial, but the generator
and checker may be preset to all Is or all Os.
5 BITS
~
SYNq
I
SYNC
I
DATA
DATA
DATA
DATA
'---v-----'
8
~------v-------16
Figure 4. Detecting 5- or 7-Bit Synchronous Characters
412
2042-109
Functional
Description
(Continued)
The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any
Ix mode. The parity options available in Asynchronous modes are available in Synchronous
modes.
The SCC can be conveniently used under
DMA control to provide high speed reception
or transmission. In reception, for example, the
SCC can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The SCC then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received. The CPU may also enable the
DMA first and have the SCC interrupt only on
end-of-frame. This procedure allows all data to
be transferred via the DMA.
SOLe Loop Mode. The SCC supports SDLC
Loop mode in addition to normal SDLC. In an
SDLC Loop, there is a primary controller
station that manages the message traffic flow
on the loop and any number of secondary
stations. In SDLC Loop mode, the SCC performs the functions of a secondary station
while an SCC operating in regular SDLC
mode can act as a controller (Figure 5).
A secondary station in an SDLC Loop is
always listening to the messages' being sent
around the loop, and in fact must pass these
messages to the rest of the loop by retransmitting them with a one-bit-time delay. The
secondary station can place its own message
on the loop only at specific times. The controller signals that secondary stations may
transmit messages by sending a special
character, called an EOP (End Of Poll),
around the loop. The EOP character is the bit
pattern 11111110. Because of zero insertion
during messages, this bit pattern is unique and
easily recognized.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0
before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop
and terminates the message with an EOP. Any
secondary stations further down the loop with
messages to transmit can then append their
messages to the message of the first secondary
station by the same process. Any secondary
stations without messages to send merely echo
the: incoming messages and are prohibited
from placing messages on the loop (except
upon recognizing an EOP).
SDLC Loop mode is a programmable option
in the SCC. NRZ, NRZI, and FM coding may
all be used in SDLC Loop mode.
Baud Rate Generator. Each channel in the
SCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The following formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
baud rate =
2 (time constant
+ 2)
x (BR dock period)
Digital Phase-Locked Loop. The SCC contains a Digital Phase-Locked-Loop (DPLL) to
recover clock information from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this
clock, along with the data stream, to construct
a clock for the data. This clock may then be
used as the SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
Figure 5. An SDLe Loop
2016-001
413
Functional
Description
(Continued)
incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxe input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the see via the TRxe pin (if
this pin is not being used as an input).
Data Encoding. The see may be programmed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a 0 is represented by a change in
level. In FMl (more properly, bi-phase mark),
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a 1
is represented by no additional transition at
the center 'of the bit cell. In addition to these
four methods, the sec can be used to decode
Manchester (bi-phase level) data by using the
DPLL in the FM mode and programming the
receiver for NRZ data. Manchester encoding
always produces a transition at the center of
the bit cell. If the transition is 0 to I, the bit is
a O. If the transition is 1 to 0, the bit is a 1.
Auto Echo and Local Loopback. The see is
capable of automatically echoing everything it
receives. This feature is useful mainly in
Asynchronous modes, but works in Synchronous and SDLe modes as well. In Auto
Echo mode, TxD is RxD. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The see is also capable of local loopback.
In this mode TxD is RxD, just as in Auto Echo
mode. However, in Local Loopback mode, the
internal transmit data is tied to the internal
receive data and RxD is ignored (except to be
echoed out via 'TxD). The eTS and DeD
inputs are also ignored as transmit and receive
enables. However, transitions on these inputs
can still cause interrupts. Local Loopback
works in Asynchronous, Synchronous and
SDLe modes with NRZ, NRZI or FM coding of
the data stream.
I/O Interface Capabilities. The see offers
the choice of Polling, Interrupt (vectored or
non vectored) , and Block Transfer modes to
transfer data, status, and control information to
and from the epu. The Block Transfer mode
can be implemented under epu or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the sec are automatically
updated whenever any function is performed.
For example, end-of-frame in SDLe mode
sets a bit in one of these status registers. The
idea behind polling is for the epu to
periodically read a status register until the'
register contents indicate the need for data to
be transferred. Only one register needs to be
DATA
NRZ
NRZI
\
\
I
I
'\
\
FM1
FMO
MANCHESTER
Figure 6. Data Encoding Methods
414
2016-002
Functional
Description
(Continued)
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. When an SCC responds to an
Interrupt Acknowledge signal (INTACK) from
the CPU, an interrupt vector may be placed on
the data bus. This vector is written in WR2 and
may be read in RR2A or RR2B (Figures 10
and 11).
To speed interrupt response time, the SCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the interrupt priority chain (Figure 7). As a
microprocessor peripheral, the SCC may
request an interrupt only when no higher
priority device is requesting one, e. g . , when
IEI is High. If the device in question requests
an interrupt, it pulls down INT. The CPU then
responds with INTACK, and the interrupting
device places the vector on the data bus.
In the SCC, the IP bit signals a need for
interrupt servicing. When an IP bit is 1 and
the IEI input is High, the INT output is pulled
Low, requesting an interrupt. In the SCC, if
. the IE bit is nOt set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the SCC and
PERIPHERAL
lEI 00-07
iNT
external to the SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the IEO output of the SCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of three
ways:
• Interrupt on First Receive Character or
Special Receive Condition.
II Interrupt on All Receive Characters or
Special Receive Condition.
II Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is one of
the following: receiver overrun, framing -error
in Asynchronous mode, end-of-frame inSDLC
mode and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receive character available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First Receive Character, an interrupt can occur from Special Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins; however, an
PERIPHERAL
INTACK lEO
lEI 00-07
iNT
INTACK lEO
PERIPHERAL
lEI 00"07
iNT
INTACK
+5V
+5V
DO-D7~
______________________________________________
~
INT.-------------~1---------------~_1----------------~4_~
INTACK~--------------~
_________________4----------------~
Figure 7. Interrupt Schedule
2023-003
415
Functional
Description
(Continued)
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection
of a Break (Asynchronous mode), Abort (SDLC
mode) or EOP (SDLC Loop mode) sequence in
the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing
the SCC to interrupt when the Abort or EOP
sequence is detected or terminated. This
feature facilitates the proper termination of the
current message, correct initialization of the
next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature allows
secondary stations to recognize the wishes of
the primary station to regain control of the
loop during a poll sequence.
CPU/DMA Block Transfer. The SCC provides
a Block Transfer mode to accommodate CPU
block transfer functions and DMA controllers.
The Block Transfer mode uses the WAITI
REQUEST output in conjunction with the
WaiVRequest bits in WRI. The WAITI
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the SCC REQUEST
output indicates that the SCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the SCC is not
ready to transfer data, thereby requesting that
the CPU extend the IIO cycle. The DTRI
REQUEST line allows full-duplex operation
under DMA control.
Architecture
The SCC internal structure includes two fullduplex channels, two baud rate generators,
internal control and interrupt logic, and a bus
interface to a nonmultiplexed bus. Associated
with each channel are a number of read and
write registers for mode control and status
information, as well as logiC necessary to interface to modems or other external devices
(Figure 8).
The logiC for both channels provides
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two synccharacter (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
WAIT/REQUEST
INTERNAL
CONTROL
LOGIC
_
}
MODEM, DMA, OR
OTHER CONTROLS
DATAW
CPU
BUS 1/0
INTERNAL BUS
-}
CONTROL W I . . . . -_ _.....
INTERRUPT
CONTROL
LINES
INTERRUP-T
CONTROL
LOGIC
MODEM, DMA, OR
OTHER CONTROLS
I
SERIAL DATA
-I
ttt
Figure 8. Block Diagram of
416
CHANNEL CLOCKS
SYNC
WAIT/REQUEST
+5 V GND PCLK
see Architecture
2016·040
.......
>
0 ...
N
a
0;
o n
~
a=.
5' CD
c n
(l)
o..S::
--~
CPU 110
TO OTHER CHANNEL
BR GENERATOR
INPUT
BR GENERATOR
OUTPUT
TRANSMIT
CLOCK
RxO
OPLL
SOLC·CRC
OPLL OUTPUT
"
I
I
BR GENERATOR OUTPUT
OPLL OUTPUT
TRxC
CRC RESULT
3"
RECEIVE CLOCK
CLOCK
MUX
iITxc
TRANSMIT CLOCK
OPLL CLOCK
BR GENERATOR CLOCK
SYNC
(OSCILLATOR)
.j::>.
......
-..,j
Figure 9. Data Path
33801SSI
Archi tecture
(Continued)
Programming
418
write only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WR15 - Write Registers 0 through 15.
RRO-RR3, RRlO, RRI2, RR13, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The SCC contains only
one WR2 and WR9, but they can be accessed
by either channel. All other registers are
paired (one for each channel).
Data Path. The transmit and receive data path
'illustrated in Figure 9 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths (data or CRC)
depending on the selected mode (the character
length in Asynchronous modes also determines
the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
bus and a 20-bit Transmit Shift register that
can be loaded either from the synchronous
character registers or from the Transmit Data
register. Depending on the operational mode,
outgoing data is routed through one of four
main paths before it is transmitted from the
Transmit Data output (TxD)
The SCC contains 13 write registers in each
channel that are programmed by the system
separately to configure the functional per":
sonality ofthe channels.
In the SCC, register addressing is direct for
the data registers only, which are selected by
a High on the Die pin. In all other cases (with
the exception of WRO and RHO), programming
the write registers requires two write operations and reading the read registers requires
both a write and a read operation. The first
write is to WRO and contains three bits that
point to the selected register. The second write
is the actual control word for the selected
register, and if the second operation is read,
Read Register Functions
RRO
Transmit/Receive buffer status and External status
RRI
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only)
Unmodified interrupt vector (Channel A only)
RR3
Interrupt Pending bits (Channel A only)
RR8
Receive buffer
RRIO
Miscellaneous status
RR12
Lower byte of baud rate generator time constant
RR13
Upper byte of baud rate generator time constant
RR 15
External/Status interrupt information
Write Register Functions
WRO
CRC initialize. initialization commands for the
various modes, Register Pointers
WRI
Transmit/Receive interrupt and data transfer mode
definition
WR2
Interrupt vector (accessed through either channel)
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and
modes
Transmit parameters and controls
WR5
WR6
Sync characters or SDLC address field
WR7
Sync character or SDLC flag
WR8
Transmit buffer
WR9
Master interrupt control and reset (accessed
through either channel)
WRIO
Miscellaneous transmitter/receiver control bits
WR 11
Clock mode control
WR12
Lower byte of baud rate generator time constant
WR13
Upper byte of baud rate generator time constant
WR14
Miscellaneous control bits
WR15
External/Status interrupt control
Table 1. Read and Write Register Functions
the selected read register is accessed. All of
the registers in the SCC, including the data
registers, may be accessed in this fashion. The
pointer bits are automatically cleared after the
read or write operation so that WHO (or RRO) is
addressed again.
The system program first issues a series of
commands to initialize the basic mode of
operation. This is followed by other commands
to qualify conditions within the selected mode.
F or example, the Asynchronous mode,
character length, clock rate, number of 'stop
bits, even or odd parity might be set first.
Then the interrupt mode would be set, and
finally, receiver or transmitter enable.
Programming Read Registers. The SCC contains eight read
(Continued)
registers (actually nine, counting the receive
buffer (RR8) in each channel). Four of these
may be read to obtain status information (RRO,
RRl, RRlO, and RR15). Two registers (RR12
and RR13) may be read to learn the baud rate
generator time constant. RR2 contains either
the unmodified interrupt vector (Channel A) or
the vector modified by status information
Read Register 0
(Channel B). RR3 contains the Interrupt Pending (IP) bits (Channel A). Figure 10 shows
the formats for each read register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a single
register (RR 1) .
Read Register 10
I0,1 0 10 10.1 OJ I0,1 0, IDo I
6
5
llli
~~~~;;,~~;:::.,~'"
LS
I
~
SYNC/HUNT
CTS
Tx UNDERRUN/EOM
' - - - - - - - - - - - ONE CLOCK MISSING
' - - - - - - - - BREAK/ABORT
Read Register 1
Read Register 12
10,1 06 \ 05 10.\ OJ I0,1 0, I Do I
I0, \0 10 0.\ OJ \ 0,\ 0, IDo I
~~
6
~:j
I~
~:::':::''''''
RESIDUE CODE 1
RESIDUE CODE 0
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
' - - - - - - - - END OF FRAME (SD~C)
6
5 \
LOWER BYTE OF
TIME CONSTANT
' - - - - - - - - - TC7
Read Register 2
10, I0 10
5 \
Read Register 13
0.\ OJ 10,1 0, IDo I
~i:
UPPER BYTE OF
TIME CONSTANT
INTERRUPT VECTOR'
~------------V7
~------------- TC'5
'MODIFIED IN B CHANNEL
Read Register 3
Read Register 15
I~I~I~I~I~I~I~I~I
I ~ ~::~~:~:~:~~~TATIP'
~~
L
CHANNEL B Rx IP'
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'
o
'--------0
II ~ ~; ~: : :'
~"'''
Tx UNDERRUN/EOM IE
' - - - - - - - - BREAK/ABORT IE
'ALWAYS 0 IN B CHANNEL
Figure 10. Read Rogister Bit FUDctions
2016-005
419
Programming Write Registers. The SCC contains 13 write
(Continued)
registers (14 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits. Figure
11 shows the format of each write register.
Write Register 3
Write Register 0
10, IOs I0 10.1 0 10,1 0, IDo I
5
0
3
~~
I
L
REGISTER 0
LRXENABLE
0
0
0
0
REGISTER 1
0
1
REGISTER 2
0
1
REGISTER 3
1
0
1
0
1
1
1
0
REGISTER 8
1
REGISTER 7
o
o
1
Rx 7 BITS/CHARACTER
REGISTER 8
1
0
Rx 6 BITS/CHARACTER
1
1
Rx 8 BITS/CHARACTER
REGISTER 4
0
REGISTER 5
0
0
1
REGISTER 9
0
1
0
REGISTER 10
0
1
1
0
1
0
1
1
REGISTER 14
1
1
REGISTER 15
REGISTER 11
REGISTER 12
1
REGISTER 13
).
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES
Rx 5 BITS/CHARACTER
0
Write Register 4
I 0,1 Os I0 10,1 0 10,1 0, IDo I
5
3
I
I L
L
PARITY ENABLE
o
o
o
o
0
0
NULL CODE
0
1
POINT HIGH
1
0
RESET EXT/STAT INTERRUPTS
1
1
1
0
ENABLE INT ON NEXT Rx CHARACTER
1
0
RESET TxlNT PENDING
1
1
0
ERROR RESET
o
0
1
1
1
RESET HIGHEST IUS
o
1
16 BIT SYNC CHARACTER
o
SDLC MODE (01111110 FLAG)
1
EXTERNAL SYNC MODE
SEND ABORT (SDLC)
o
o
0
NULL CODE
1
RESET Rx CRC CHECKER
1
0
RESET Tx CRC GENERATOR
1
1
RESET Tx UNDERRUN/EOM LATCH
1
'WITH POINT HIGH COMMAND
PARITY EVEN/tfOD
o
o
0
SYNC MODES ENABLE
1
1 STOP BIT/CHARACTER
1
0
1 y, STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
8 BIT SYNC CHARACTER
o
0
X1 CLOCK MODE
o
1
X16 CLOCK MODE
1
0
X32 CLOCK MODE
1
1
X64 CLOCK MODE
Write Register 1
Write Register 5
I 0,1 Os I0 10.1 0 10,1 0, IDo I
5
3
I L!: '" '" '"""
o
o
0
Rx INT DISABLE
1
Rx INT ON FIF1ST CHARACTER OR SPECIAL CONDITION
1
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
1
L!: :~SCRC
L
~
I
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
.
Rx INT ON SPECIAL CONDITION ONLY
' - - - - - - - WAITIDMA REQUEST ON RECEIVE/TRANSMIT
' - - - - - - - - WAITIDMA REQUEST FUNCTION
' - - - - - - - - - WAIT/DMA REQUEST ENABLE
ENABLE
SDLC/CRC.16
Tx ENABLE
SEND BREAK
o
0
o
1
Tx 7 BITS/CHARACTER
1
0
Tx 6 BITS/CHARACTER
1
1
Tx 8 BITS/CHARACTER
Tx 5 BITS (OR LESS)/CHARACTER
' - - - - - - - - - DTR
Write Register 2
Write Register 6
I 0,1 I0 10.1 0 10,1 0, IDo I
Os
5
10, IOs I0 10.1 03 10,1 0, IDo I
3
5
INTERRUPT
VECTOR
L -_ _ _ _ _ _ _
V,
~)~~
SYNC,
SYNC1
SYNC,
SYNC3
ADR,
ADR,
SYNCs
SYNCo
SYNCs
SYNC2
ADRs
ADRs
SYNCs
SYNCs
SYNCs
SY NC1
ADRs
ADRs
SYNC,
SYNC,
SYNC,
SYNCo
ADR,
ADR,
SYNCo
SYNCo
SYNCo
1
ADRo
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC
(ADDRESS RANGE)
Figure 11. Write Register Bit Functions
420
2016-006 2023-010
t-
Programming
Write Register 7
(Continued)
I
SYNC7
SYNCs
SYNC,s
SYNC"
SYNCe
SYNC4
SYNC14
SYNClO
1
o
0, I 0 1Os I 0.1 0,1 0,1 0, I Do I
SYNCs
SYNC 3
SYNC13
SYNCg
1
6
SYNC.
SYNC2
SYNC'2
SYNCe
1
SY~Co
SYNC,
SYNC2
SYNCo
SYNC,o
SYNC,
1
MONOSYNC, 8 BITS
MONOSYNC, 6 BIT;'>
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
X
SYNCg
SYNCs
1
SYNCs
SYNC~
o
Write Register l~
Write Register 9
0,I 0,1 051D. i 0 10,1 0, I Do I
1
SYNC3
SYNC,
SYNC"
SYNC7
1
I0, I0 105 i 0.1 0,1 0,1 0, 10 I
6
3
~
~:~
lJ£::
~MIE
~TATUS HIGH/STATUSJ:OW
o
o
0
NO RESET
1
CHANNEL RESET B
1
0
CHANNEL RESET A
1
1
FORCE HARDWARE RESET
0
LOWER BYTE OF
TIME CONSTANT
Write Register 13
Write Register 10
~lJ£
L 6 BIT/8BTf SYNC
UPPER BYTE OF
TIME CONSTANT
LOOP MODE
ABORT/FLAG ON UNDERRUN
MARK/FLAG IDLE
GO ACTIVE ON POLL
o
o
0
1
NRZI
1
0
FMl (TRANSITION
= 1)
1
1
FMO (TRANSITION
= 0)
L-_ _ _ _ _ _ _ TC,s
NRZ
Write Register
H
I0, I0.1 0510.1 0,1 0 10, IDo I
' - - - - - - - - - - CRC PRESET I/O
2
L BR. GENfRATOR ENABLE
~@.
L
Write Register 11
I
1
0
DTRIREQUEST FUNCTION
•
,
AUTO ECHQ
I
LOCAL LOOPBACK
0
0
TRxC OUT
0
0
NULL CQM¥A~P
1
TRxC OUT
= XTAL OUTPUT
= TRANSMIT CLOCK
0
o
0
0
1
ENTER St;:ARGH MODE
1
0
TRxC OUT
= BA GENERATOR OUTPUT
0
1
0
RESET MISSING CI.OCK
1
1
TRxC OUT
= DPLL OUTPUT
0
1
1
DISAB~E DPI.!.
1
0
0
SET $)lllflC;E l' ~R GENI'RATqR
'rRxC
o
IlR GENERATOR SOURCE
o/i
TRANSMIT CLOCK
= RTxC
1
0
1
SET SPURI;E
= RTxC PIN
1
1
0
SET
1
1
1
SET NR;!:I ~ODE
o
1
TRANSMIT CLOCK = TRxC PIN
1
0
TRANSMIT CLOCK
= BR GENERATOR OUTPUT
1
1
TRANSMIT CLOCK
= DPLL OUTPUT
fM
IJIOD~
Write Registe~
o
0
RECEIVE CLOCK
= Rtxc PIN
o
1
RECEIVE CLOCK
= TRxC PIN
1
D
RECEIVE CLOCK
1
1
RECEIVE CLOCK
= BR GENERATOR OUTPUT
= DPLL OUTPUT
L---------R~XTAUNOXTAL
l&
ID'IDm·ID~SID~'II'I[~
:"''''''''
CDCDI~
SYNC/HUNT IE
CTS IE
T~
\JNDEflRj.lN/EOM IE
L-_ _ _ _.........,...,...-_ BREAK/ABORT IE
Figure ll. Write Register Bit Functions (Continued)
2016·006
421
Timing
The SCC generates internal control signals
from WR and RD that are related to PCLK.
Since PCLK has no phase relationship with
WR and RD, the circuitry generating these
internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the SCC. The recovery time
required for proper operation is speCified from
the rising edge of WR or RD in the first trans-
action involving the SCC to the falling edge of
WR or RD in the second transaction involving
the SCC. This time must be at least 6 PCLK
cycles plus 200 ns.
Read Cycle Timing. Figure 12 illustrates
Read cycle timing . Addresses on AlB and Die
and the status on INT ACK must remain stable
throughout the cycle. If CE falls after RD falls
or if it rises before RD rises, the effective RD is
shortened.
X
AlB, ole _ - - - - J
V--
ADDRESS
VALID
_ _ _
_
_ _ _" - - - - -
\'---1
\
\\0.----_--11
00-07
-'x
------------«\..____
DATA VALID
»)------
Figure 12. Read Cycle Timing
Write Cycle Timing. Figure 13 illustrates
Write cycle timing. Addresses on AlB and Die
and the status on INTACK must remain stable
AlB,
ole
X
_----J
throughout the cycle. If CE falls after WR falls
or if it rises before WR rises, the effective WR
is shortened.
V--
ADDRESS VALID
_ _ _ _ _ _. - " - - - - -
\_-I
\
\\.-____-..JI
00-07------------~(\.._ _ _ _ _ _D_AT_A_VA_L_ID_ _ _ _ ____')~--------Figure 13. Write Cycle Timing
Interrupt Acknowledge Cycle Timing. Figure
14 illustrates Interrupt Acknowledge cycle
timing. Between the time INTACK goes Low
and the falling edge of RD, the internal and
external IEI/IEO daisy chains settle. If there is
an interrupt pending in the SCC and lEI is
High when RD falls, the Acknowledge cycle is
intended for the SCC. In this case, the SCC
may be programmed to respond to RD Low by
placing its interrupt vector on Do-D7 and it
then sets the appropriate Interrupt- UnderService latch internally.
~'-------~>O'l~--------------------'J'
~----------~£~'--~\~_____________'J'
INTACK
00-07
-'X
- - - - - - - - - I / , F - '--------«'-___
VECTOR
»)------
Figure 14. Interrupt Acknowledge Cycle Timing
422
2023-003, 004, 005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .. : ....... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Tempera ture ........ -65°C to + 150 °C
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these speCifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
[J
III
+4.75 V ::5 Vee ::5 +5.25 V
GND = 0 V
II TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+5V
+5V
~r
2'2K
FROM OUTPUT
UNDER TEST
.
50PF
Figure 15. Standard Test Load
DC
Characteristics
Symbol
VIH
VIL
VOH
VOL
IlL
IOL
Icc
Figure 16. Open-Drain Test Load
Parameter
Min
Max
Unit
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
2.0
-0.3
2.4
Vee+ 0 .3
0.8
V
V
V
V
p.A
p.A
0.4
± 10.0
± 10.0
250
Condition
IOH =
IOL=
0.4 S
0.4 S
-250 p.A
+2.0 rnA
VIN S + 2.4V
VOUT S +2.4V
rnA
Vee = 5 V ± 5% unless otherwise specified, over speCified temperature range.
Capacitance
Symbol
C IN
C OUT
CIIO
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
Unmeasured Pins
Returned to Ground
f = 1 MHz, over specified temperature range.
8085-006, 001
423
Read and
Write
Timing
PCLK
AlB,
ole
-'I\.~
'"
I----
CPU
BUS I/O
INTERNAL BUS
-}
CONTROL
INTERRUPT
CONTROL
LINES
ti i
+ 5 V GND
PCLK
INTERRUPT
CONTROL
LOGIC
8
CHANNEL B
}
MODEM, DMA, OR
OTHER CONTROLS
SERIAL DATA
I
CHANNEL CLOCKS
Ai
WAIT/REQUEST
, Figure 6. Block Diagram of ASee Architecture
436
2244-003
..-..>
IV
IV
:t
:i2
o0""
n
6
~e:
S· ;-
-
C n
(])
Q...~
-~
CPU 110
TO OTHER CHANNEL
BR GENERATOR
INPUT
BR GENERATOR
OUTPUT
RECEIVE
RECEIVE
DATA
ERROR
FIFO
FIFO
TRANSMIT
CLOCK
R,D
OPLL
OPLL OUTPUT
BR GENERATOR OUTPUT
~
RECEIVE CLOCK
OPLL OUTPUT
TRxC
CLOCK
MUX
RTxC
TRANSMIT CLOCK
OPLL CLOCK
BR GENERATOR CLOCK
(OSCILLATO~ ~
~
w
......,
Figure 7. Data Path
33STf I£SSZ
Architecture
(Continued)
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pending bits (ChannelA only).
The registers for each channel are
designated as follows:
WRO-WR 15 -
Write Registers 0-5, 8-15.
RRO-RR3, RRlO, RRI2, RRI3, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The ASCC contains only one WR2 and WR9, but they can be accessed by either channel. All other registers are
paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in Figure 7 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of. seve~al paths depending on the
selected mode (the character length also determines the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
bus and an ll-bit Transmit Shift register that
can be loaded from the Transmit Data register.
Programming
438
The ASCC contains 11 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels.
In the ASCC, register addressing is direct
for the data registers only, which are selected
by a High on the DIe pin. In all other cases
(with the exception of WRO andRRO), programming the write registers requires two
write operations and reading the read registers
requires both a write and a read operation.
The first write is to WRO and contains three
bits that point to the selected register. The second write is the actual control word for the
Read Register Functions
RRO
Transmit/Receive buffer status and External status
RRI
Special Receive Condition status
RR2
Modified interrupt vector (Channel B only)
Unmodified interrupt vector (Channel A only)
RR3
Interrupt Pending bits (Channel A only)
RR8
Receive buffer
'RRlO
Miscellaneous status
RR12
Lower byte of baud rate generator time constant
RR13
Upper byte of baud rate generator time constant
RR15
ExternaVStatus interrupt information
Write Register Functions
WRO
CRC initialize, initialization commands for the
various modes, Register Pointers.
WRI
Transmit/Receive interrupt and data transfer mode
definition
WR2
Interrupt vector (accessed through either channel)
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and
modes
WR5
Transmit parameters and controls
WR8
Transmit buffer
WR9
Master interrupt control and reset (accessed
through either channel)
WRlO
Miscellaneous transmitter/receiver control bits
WRII
Clock mode control
WR12
Lower byte of baud rate generator time constant
WR13
Upper byteof baud rate generator time constant
WRl4
Miscellaneous control bits
WR15
ExternaVStatus interrupt control
Table I. Read and Write Register Functions
selected register, and if the second operation
is read, the selected read register is accessed.
All of the registers in the ASCC, including the
data registers, may be accessed in this fashion.
The pointer bits are automatically cleared after
the read or write operation so that WRO (or
RRO) is addressed again.
The system program first issues a series of
commands to initialize the basic :mode of
operation. For example, the character length,
clock rate, number of stop bits, even or odd
parity might be set first. Then the interrupt
mode would be set, and finally, receiver or
transmitter enable.
Programming Read Registers. The ASCC contains eight
(Continued)
read registers (actually nine, counting the
receive buffer (RR8) in each channel). Four of
these may be read to obtain status information
(RRO, RRl, RRIO, and RR15). Two registers
(RR12 and RR13) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the
Interrupt Pending OP) bits (Channel A).
Figure 8 shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a single
register (RRl).
Read Register 0
Read Register 10
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
~
I ~ ~~~~;~~::'~:""'"
~
RING INDICATOR
.
~j
~WO CLOCKS MISSING
CTS
1
' - - - - - - - - ONE CLOCK MISSING
' - - - - - - - - BREAK
Read Register 1
Read Register 12
I0 10 10 10.1 OJ I0 10, IDo I
I~I~I~I~I~I~I~I~I
7
6
5
2
~
[
;
:
~
:
'
"
o
,
L§ ' '"'"'
~:i:
I
',"0'
LOWER BYTE OF
TIME CONSTANT
' - - - - - - - - TCT
Read Register 2
Read Register 13
I~I~I~I~I~I~I~I~I
INTERRUPT VECTOR·
'--------------VT
~:~:~
UPPER BYTE OF
TIME CONSTANT
' - -_ _ _ _ _ _ TC15
·MODIFIED IN B CHANNEL
Read Register 3
Read Register 15
I~I~I~I~I~I~I~I~I
~~
I ~ CHANNELB EXT/STATlp·
L
CHANNEL B Tx Ip·
CHANNEL B Rx Ip·
CHANNEL A EXT/STAT Ip·
CHANNEL A Tx Ip·
CHANNEL A Rx Ip·
o
~:'"o,o""'''
~~
CDCDIE
Ai
IE
CTS IE
1
' - - - - - - - - BREAK IE
·ALWAYS 0 IN B CHANNEL
Figure 8. Read Register Bit Functions
2244-005
439
Programming Write Registers. The ASCC contains 11 write
(Continued)
registers (12 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits.
Ffgure 9 shows the format of each write
register.
Write Register 3
Write Register 0
I~I~I~I~I~I~I~I~I
0
0
0
0
0
1
REGISTER 0
REGISTER 1
0
1
o
REGISTER 2
~c~~'~""
0
1
1
REGISTER 3
1
0
0
REGISTER 4
1
0
1
REGISTER 5
1
1
o
NULL CODE
o
0
Rx 5 BITS/CHARACTER
1
1
1
NULL CODE
o
1
Rx 7 BITS/CHARACTER
0
0
0
REGISTER 8
1
0
Rx 6 BITS/CHARACTER
0
0
1
REGISTER 9
1
1
Rx 8 BITS/CHARACTER
0
1
0
REGISTER 10
0
1
1
REGISTER 11
1
0
0
REGISTER 12
1
0
1
REGISTER 13
1
1
0
REGISTER 14
1
1
1
REGISTER 15
I·
o
0
0
NULL CODE
o
0
1
POINT HIGH
o
RESET EXT/STAT INTERRUPTS
Write Register 4
I~I~I~I~I~I~I~I~I
1
NULL CODE
o
ENABLE INT ON NEXT Rx CHARACTER
~
RESET TxlNT PENDING
1
0
ERROR RESET
1
RESET HIGHEST IUS
o
0
ror;-
'WITH POINT HIGH COMMAND
~ro
!~
I L PARITY ENABLE
L PARITY EVEN/ODD
o
0
o
1
1 STOP BIT/CHARACTER
1
0
1'1. STOP BITS/CHARACTER
1
1
2 STOP BITS/CHARACTER
DO NOT PROGRAM
X 1 CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
Write Register 1
I~I~I~I~I~I~I~I~I
Write Register 5
L L ''''''' 'NAO"
II
I~I~I~I~I~I~I~I~I
Tx INT ENABLE
PARITY IS SPECIAL CONDITION
o
o
0
Rx I~JT C~SA5t.[
1
Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION
1
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
1
Rx INT ON SPECIAL CONDITION ONLY
' - - - - - - - WAIT/DMA REQUEST ON RECEIVEI'I'fiAfiSMJT
' - - - - - - - - WAif/DMA REQUEST FUNCTION
' - - - - - - - - - WAITIDMA REQUEST ENABLE
o
o
0
Tx 5 BITS (OR LESS)lCHARACTER
Tx 7 BITS/CHARACTER
1
1
~~;:::~.
Tx 6 BITS/CHARACTER
1
Tx 8 BITS/CHARACTER
L--_ _ _ _ _ _ _ _
DTR
Write Register 2
I~I~I~I~I~I~I~I~I
~li
L--_ _ _ _ _ _ _ _
INTERRUPT VECTOR
V7
Figure 9. Write Register Bit Functions
440
2244-006
Write Register 12
Programming Write Register 9
(Continued)
I~I~I~I~I~I~I~I~I
~~
I~I~I~I~I~I~I~I~I
~1l
~~~
~DLC
o
o
MIE
:TATUS HIGH/STATUS LOW
L -_ _ _ _ _ _ _ _
0
NO RESET
1
CHANNEL RESET B
o
CHANNEL RESET A
'1
FORCE HARDWARE RESET
LOWER BYTE OF
TIME CONSTANT
T l
C
Write Register 13
I~I~I~I~I~I~I~I~I
Write Register 10
~1j:~
I~I~I~I~I~I~I~I~I
~;
o
o
0
1
NRZI
1
0
FM1 (TRANSITION = 1)
1
1
FMO (TRANSITION = 0)
UPPER BYTE OF
TIME CONSTANT
L..-_ _ _ _ _ _ _ _ TC15
NRZ
Write Register 14
I~I~I~I~I~I~I~I~I
I
~
I
L BR GENERATOR ENABLE
~ BR GENERATOR SOURCE
Write Register 11
I~I~I~I~I~I~I~I~I
1
0
AUTO ECHO
LOCAL LOOPBACK
0
0
0
NULL COMMAND
0
0
TRxC OUT = XTAL OUTPUT
0
0
1
ENTER SEARCH MODE
o
1
TRxC OUT = TRANSMIT CLOCK
0
1
1
0
TRxC OUT = BR GENERATOR OUTPUT
0
1
1
1
TRxC OUT = DPLL OUTPUT
TRxC
o
o
DfR/REQUEST FUNCTION
o/i
TRANSMIT CLOCK = RTxC PIN
1
TRANSMIT CLOCK = TRxC PIN
1
0
TRANSMIT CLOCK = BR GENERATOR OUTPUT
1
1
TRANSMIT CLOCK
RESET MISSING CLOCK
DISABLE DPLL
0
0
SET SOURCE = BR GENERATOR
0
1
SET SOURCE =
1
1
0
SET FM MODE
1
1
1
SET NRZI MODE
RTxC
= DPLL OUTPUT
Write Register 15
o
o
0
RECEIVE CLOCK = RTxC PIN
1
RECEIVE CLOCK = TRXC PIN
1
0
RECEIVE CLOCK = BR GENERATOR OUTPUT
1
1
RECEIVE CLOCK
I~I~I~I~I~I~I~I~I
= DPLL OUTPUT
L..-_ _ _ _ _ _ _ _ RTxC XTAUNO XTAL
I ~:,""ro"",,,
~~
CDCDIE
iii
IE
CTS IE
1
L-_ _ _ _ _ _ _ _ BREAK IE
Figure 9. Writo Register Bit Functions (Continued)
2244-006
441
Timing
The ASCC generates internal control signals
from WR and RD that are related to PCLK.
Since PLCK has no phase relationship with
WR and RD, the circuitry generating these internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the ASCC. The recovery
time required for proper operation is specified
from the rising edge of WR or RD in the first
AlB, DIC
X
transaction involVing the ASCC to the falling
edge of WR or RD in the second transaction
involving the ASCC. This time must be at least
6 PLCK cycles plus 200 ns.
Read Cycle Timing. Figure 10 illustrates read
cycle timing, Addresses on NB and Die and
the status on INTACK must remain stable
throughout the cycle. If CE falls after RD
falls,or rises before RD rises, the effective RD
is shortened.
V--
ADDRESS VALID
_ _--J ' - -_ _ _ _ _ _ _ _ _......~
\_--
1
\
\ ____--1
Do-D7
------------«\.____.JX
DATA VALID
»)------
Figure 10. Read Cycle Timing
Write Cycle Timing. Figure 11 illustrates
write cycle timing. Addresses on NB and Die
and the status on INTACK must remain stable
throughout the cycle. If CE falls after WR falls
or rises before WR rises, the effective WR is
shortened.
X
AlB, DIC _ - - J
V--
ADDRESS_
VALID _ _ _~
_ _ _ _
\_-I
\
\ ,\._______________J'I
DO-D7--------~(\._ _ _ _ _D_AT_A_V_AL_ID_ _ _ ___J)~----Figure 11. Write Cycle Timing
Interrupt Acknowledge Cycle Timing. Figure
12 illustrates interrupt acknowledge cycle timing. Between the time INTACK goes low and
the falling edge of RD,. the internal and external lEI/lEO daisy chains settle. If there is an
interrupt pending the ASCC and lEI is High
when RD falls, the acknowledge cycle was intended for the ASCC. In this case, the ASCC
may be programmed to respond to RD Low by
placing its interrupt vector on Do-D7 and sets
the appropriate Interrupt- Under-Service latch
internally.
INTACK~~_ _ _ _ _~;~'l~_______________-'1'
I:
Do-D7
\_------1'
--------II,-,..'-----«\-___.JX
VECTOR
»)-------
Figure 12. Interrupt Acknowledge Cycle Timing
442
2023-003, 004, 005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ......... -65°C to + 150 °C
Stresses greater than those listed under Absolute Maxi·
mum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
IJ +4.75 V =:;; Vee =:;; +5.25 V
GND
TA as
All ac
of 50 pF
[J
[J
= 0V
specified in Ordering Information
parameters assume a load capacitance
max.
+5V
+5 V
2.1K
FROM OUTPUT
UNDER TEST
Figure 13. Standard Test Load
DC
Characteristics
Symbol
Parameter
VIH
Input High Voltage
VIL
VOH
VOL
IlL
IOL
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Icc
Vee Supply Current
~I
2'2K
.
50PF
Figure 14. Open-Drain Test Load
Min
Max
Unit
2.0
Vee +0.3
0.8
V
V
V
V
pA
pA
-0.3
2.4
0.4
± 10.0
± 10.0
250
Condition
IoH = -250 pA
IoL= +2.0 rnA
0.4 s VIN S + 2.4V
0.4
S
VOUT
S
+2.4V
rnA
Vee = 5 V ± 5% unless otherwise specified, over specified temperature range.
Capacitance
Symbol
C 1N
COUT
Cvo
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
10
15
20
pF
pF
pF
Test Condition
U nrneasured Pins
Returned to Ground
f = 1 MHz, over specified temperature range.
8085-006, 001
443
Read and
Write
Timing
_in-~
PCLK
AlB, Die
:=J<
~
f--? Data Bus (bidirectional 3-state). These
eight data lines are used for transfers between
the CPU and the CIa.
lEI. Interrupt Enable In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI is High and the
CPU is' not servicing an interrupt from the
requesting CIO or is not requesting an interrupt (Interrupt Acknowledge cycle only). lEO
is connected to the next lower priority device's
IEI input and thus inhibits interrupts from
lower priority devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is pulled Low when
the CIa requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This input indicates to the CIO that an
Interrupt Acknowledge cycle is in progress.
INTACK must be synchronized to PCLK, and
The CIa Counter/Timer and Parallel I/O
element (Figure 3) consists of a CPU interface,
it must be stable throughout the Interrupt
Acknowledge cycle.
PAo-PA7. Port A I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIO's Port A
and external devices.
PBo-PB,. Port B I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIO's Port B
and external devices. May also be used to
provide external access to Counter/Timers
1 and 2.
PCo-PCa. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the CIO's Port C.
PCLK. Peripheral Clock (input, TTLcompatible). This is the clock used by the
internal control logic and the counter/timers
in timer mode. It does not have to be the
CPU clock.
RD*. Read (input, active Low). This signal
indicates that a CPU is reading from the CIa.
During an Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the data
bus if the CIO is the highest priority device
requesting an interrupt.
WR*. Write (input, active Low). This signal
indicates a CPU write to the CIa.
·When RD and WR are detected Low at the same time (normally
an illegal condition), the CIa is reset.
three I/O ports (two general-purpose 8-bit
ports and one special-purpose 4-bit port),
INTERNAL BUS
INTERNAL
CONTROL
LOGIC
Figure 3. CIO Block Diagram
452
2021-001
Architecture
(Continued)
INTERNAL
INPUT
BUFFERI
INVERTERS
AND
l's
CATCHER
PORT
110
OUTPUT
BUFFERI
INVERTERS
Figure 4. Porta A and B Block Diagram
three 16-bit counter/timers, an interruptcontrol logic block, and the internal-control
logic block. An extensive number of programmable options allow the user to tailor the configuration to best suit the specific application.
The two general-purpose a-bit I/O ports
(Figure 4) are identical, except that Port B can
be specified to provide external access to
Counter/Timers 1 and 2. Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit individually programmable. Each
port includes pattern-recognition logic, allowing interrupt generation when a specific pattern is detected. The pattern-recognition logic
can be programmed so the port function's like
a priority-interrupt controller. Ports A and B
can also be linked to form a 16-bit I/O port.
To control these capabilities, both ports contain 12 registers. Three of these registers, the
Input, Output, and Buffer registers, comprise
the data path registers. Two registers, the
Mode Specification and Handshake Specification registers, are used to define the mode of
the port and to specify which handshake, if
any, is to be used. The reference pattern for
the pattern-recognition logic is defined via
2014-002
three registers: the Pattern Polarity, Pattern
Transition, and Pattern Mask registers. The
detailed characteristics of each bit path (for
example, the direction of data flow or whether
a path is inverting or noninverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initially configured, only this register must be accessed frequently. To facilitate initialization,'
the port logic is designed so that registers
associated with an unrequired capability are
ignored and do not have to be programmed.
The function of the special-purpose 4-bit
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
I/O lines or to provide external access for the
third counter/timer.
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special 1/0 Control registers.
453
Archi tecture
(Continued)
TOCOUNTERI
TIMER 3
INPUT
BUFFERI
INVERTERS
AND
INTERNAL
BUS
l's
CATCHER
OUTPUT
DATA
REGISTER
~PORT
r-v'I/O
INPUT
DATA
REGISTER
OUTPUT
BUFFERI
INVERTERS
PORT
CONTROL
LOGIC
.-----_......I~ONTROL
' - - - - - 0 I N T E R N A L PORT
..J
LINES
<
Figure 5. Port C Block Diagram
The three counter/timers (Figure 6) are all
identical. Each is comprised of a 16-bit downcounter, a 16-bit Time Constant register
(which holds the value loaded into the downcounter), a 16-bit Current Count register (used
to read the contents of the down-counter), and
two 8-bit registers for control and status (the
Mode Specification and the Command and
Status registers).
The capabilities of the counter/timer are
numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.
454
The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
There are five registers (Master Interrupt
Control register, three Interrupt Vector
registers, and the Current Vector register)
associated with the interrupt logic. In addition,
the ports' Command and Status registers and
the counter/timers' Command and Status
registers include bits associated with the interrupt logic. Each of these registers contains
three bits for interrupt control and status:
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE).
2014-003
Architecture
(Continued)
INTERNAL
BUS
CURRENT
COUNT
REGISTER
(MSBs)
CURRENT
COUNT
R~Ei~!fR t - - - - - I
Figure 6. Counter/Timer Block Diagram
Functional
Description
The following describes the functions
of the ports, pattern-recognition logiC,
counter/timers, and interrupt logiC.
I/O Port Operations. Of the CIO's three I/O
ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also provides access for Counter/Timers 1 and 2. In all
configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUEST/WAIT line can also be provided
so that CIO transfers can be synchronized with
DMAs or CPUs. Any Port C bits not used for
handshake or REQUESTIWAIT can be used as
input or output bits (indiVidually data-direction
programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits remain
undisturbed without first reading the register.
Bit Port Operations. In bit port operations, the
2014-004
port's Data Direction register specifies the
direction of data flow for each bit. A 1
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the input just prior to
the read. A l's catcher can be inserteid into the
input data path by programming a 1 to the
corresponding bit position of the port's Special
I/O Control register. When a 1 is detected at
the l's catcher input, its output is set to 1 until
it is cleared. The l's catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of.Port C return the state
of the pin. Outputs can be specified as opendrain by writing a 1 to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with a I, the state of the corresponding output
bit is not changed.
.
455
Functional
Description
(Continued)
Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logic. Port C provides the
handshake lines as shown in Table 1. Any Port
C lines not used for handshake can be used as
simple 1/0 lines or as access lines for
CounterlTimer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (IP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. Inbidirectional ports, IP is cleared only by command.
When the Interrupt on "Two Bytes (ITB) control
bit is set to 1, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
-information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read
or written.
When the Single Buffer (SB) bit is set to 1,
the port acts as if it is only single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
A has pattern-match capability. Port B's
Port AlB Configuration
PC3
pattern-match capability must be disabled.
Also, when the ports are linked, Port B'sData
register must be read or written before
Port A's.
When a port is speCified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special 1/0 Control register apply only to output bits (3-state or open-drain). Inputs may not
have l's catchers; therefore, those bits in the
Special 1/0 Control registe~ are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the CIa must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
o~tput port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the
previous byte of the data is no longer
available, thereby acknowledging the input
port's acceptance of the last byte. This allows
the CIa to interface directly to the port of a 28
microcomputer, a UPC, an FlO, an FIFO, or
to another CIa port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAV) output for output ports.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles specified by the
deskew timer time constant plus one, DAV is
allowed to go Low. The deskew timer therefore
guarantees that the output data is valid for a
specified minimum amount of time before DAV
P~
PCI
PCO
Bit I/O
Bit I/O
Bit I/O
Bit I/O
Port A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)·
RFD or DAV
ACKIN
REQUEST/WAIT
or Bit I/O
Bit I/O
Port B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)·
REQUESTIW AIT
or Bit I/O
Bit I/O
RFD or DAV
ACKIN
Port A or B: Input Port (3-Wire
Handshake)
RFD (Output)
DAV (Input)
REQUESTIW AIT
or Bit I/O
DAC (Output)
Port A or B: Output Port (3-Wire
Handshake)
DA V (Output)
DAC (Input)
REQUESTIWAIT
or Bit I/O
RFD (Input)
Port A or B: Bidirectional Port
(Interlocked or Strobed Handshake)
RFD or DAV
ACKIN
REQUESTIWAIT
or Bit I/O
IN/OUT
Ports A and B:
Bit Ports
·Both Ports A and B can be specified Input or output with Interlocked, Strobed. or Pulsed Handshake at the same time if neither uses
REQUESTIW AlT.
Table 1. Port C Bll Utilization
456
Functional
Description
(Continued)
goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is \\strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked handshake, the signal
indicating the port is ready for anoth~r data
transfer operates independently of the ACKIN
input. It is up to the external logic to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate if an input port is ready
for new data or if it has accepted the present
da ta. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake
the output lines of many input ports can be '
bussed together with open-drain drivers; the
output port knows when all the ports have
accepted the data and are ready. This is the
INPUT HANDSHAKE
DATA:::)(
same handshake as is used on the IEEE-488
bus. Because this handshake requires three
lines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be
changed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.
Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devices that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logic is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the ACKIN path.
The external ACKIN input triggers the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintains all of its normal
capabilities. This handshake is not available to
bidirechon"al ports.
OUTPUT HANDSHAKE
X'-_________
VALID
DATA
NEXT BYTE
RFD
DATA LATCHED
}N BUFFER REGISTER
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Flguro 7. Interlockod and Strobod Handshakos
OUTPUT HANDSHAKE
INPUT HANDSHAKE
DATA:::)(
X'-_________
VALID
nPD
DAV
INPUT
INPUT
'------+---1
DAC
OUTPUT
NEXT BYTE
_ _ _ _ _ _J
DAC
RPD
OUTPUT
DATA
'DATA SHIFTED
TO INPUT REGISTER
INPUT
DAV
----l,---'
OUTPUT
BUFFER REGISTER
"EMPTIED"
NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER
Figure 8. 3-Wiro Handshako
2014-005, 006
457
Functional
Description
(Continued)
REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST ~r WAIT signal. The REQUEST
signal indicates'when a port is ready to perform a data transfer via the CPU interface. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUEST/WAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a handshake and a
REQUEST/WAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (ITB) control bit. When ITB is a, the
REQUEST line goes active as soon as the CIO
is ready for a data transfer. If ITB is I,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allowing the port to recognize patterns in all of
its configurations. The pattern can be independently specified for each bit as I, a, rising
edge, falling edge, or any transition. Individual bits may be masked off. A patternmatch is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT
ACKIN'
OUTPUT PORT
Figure 9. Pulsed Handshake
458
The pattern specified in the Pattern Definition register assumes that the data path is programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
specified. Output bits used in the patternmatch logic are internally sampled before the
invert/noninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as I/O for the counter/timers. The input
to the pattern-recognition logiC follows the
value at the pins (through the invert/noninvert
logic) in all cases except for simple inputs with
l's catchers. In this case, the output of the l's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match'
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports specified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transition from a no-match to a match state is
not required.
The pattern-recognition logiC of bit ports
operates in two basic modes: transparent and
latched. When the Latch on Pattern Match
(LPM) bit is set to a (Transparent mode), the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = I), the state of all the
port inputs at the time the interrupt was
generated is latched in the input register and
held until IP is cleared. In all cases, the PMF
indicates the state of the port at the time it is
read.
If a match occurs while IP is already set, an
error condition exists. If the Interrupt On Error
bit (IOE) is a, the match is ignored. However,
if IOE is 1 after tne first IP is cleared, it is
automatically set to 1 along, with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP is cleared.
When a pattern-match is present in the OR-'
Priority Encoded Vector mode, IP is set to l.
The IP cannot be cleared until a match is no
longer present. If the 'interrupt vector is allowed to include status, the vector returned during Interrupt Acknowledge indicates the
highest priority bit matching its specification at
the time of the Acknowledge cycle. Bit 7is the
highest priority and bit a is the lowest.' The bit
initially causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the
2014-007
Functional
Description
(Continued)
Acknowledge cycle is initiated, the vector is
frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the l's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection is
performed in this mode, and the Interrupt On
Error bit should be set to O.
Function
C/Tl
C/T2
C/T3
Counter/Timer Output
PB 4
PB 0
PCO
Counter Input
PB 5
PB 1
PC 1
Trigger Input
PB 6
PB 2
PC2
Gate Input
PB 7
PB 3
PC 3
Tablo 2. Counter/Timor External Access
The flexibility of the counter/timers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate input,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer l's external I/O lines are prOVided by
the four most significant bits of Port B.
Counter/Timer 2' s are prOVided by the four
least significant bits of Port B. Counter/Timer
3' s external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode Specification
registers.
When external counter/timer I/O lines are
to be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as simple input
lines. They can be specified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the l's catcher input.
Counter/Timers 1 and 2 can be linked internally in three different ways. Counter/Timer
l's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer 1
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the cOl,Jnter/
timer waveforms. When the Pulse mode
Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the PatternMatch Flag (PMF). The data is compared with
the match pattern when it is shifted from the
Buffer register to the Input register (input port)
or when it is shifted from the Output register to
the Buffer register (output port). The pattern
match logic can override the handshake logiC
in certain situations. If the port is programmed
to interrupt when two bytes of data are
available to be read or written, but the first
byte matches the specified pattern, the
pattern-recognition logic sets IP and generates
an interrupt. While PMF is set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emptied while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit is
set, IP is set only when the data matches the
pattern. This is useful in DMA-type application
when interrupts are required only after a block
of data is transferred.
Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode SpeCification register,
an 8-bit Command and Status register, and the
associated control logic that links these registers.
PCLK/2 OR
COUNTER INPUT
TRIOO.,R
-.J
OATE
I
PULSE OUTPUT
TC
I
LJ
TC-l
I
TC-l
/1
I
TC-2
I· · •I
1
I' 6t I
II
-------I.~
L-
,c
ONE SHOT
OUTPUT _ _ _....
SQUARE WAVE
OUTPUT
FIRST HALF
------------......,'r;.'---....I
SQUARE WAVE -
-
-
-
-
---------.."r;.,----,
OUTPUT
SECOND HALF
Figura 10. Counter/Timer Waveforms
2014-008
459
Functional
Description
(Continued)
460
is specified, the output goes High for one
clock cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode,
the output goes High when the counter/timer is
triggered and goes 'Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/timer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a 1 count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value is reloaded. On the clocking edge, when
both the down-counter and the output are l's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode Specification register controls operation of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count is reached, the countdown sequence
stops. If the CISC bit is 1 each time the countdown counter reaches I, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register and initiating the countdown sequence
by loading the down-counter with the time
constant value. The Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter is loaded in one of
three ways: by writing a' 1 to the Trigger Command Bit (TCB) of the Command and Status
register, on the rising edge of the external
trigger input, or, for Counter/Timer 2 only, on
the rising edge of Counter/Timer l's internal
output if the counters are linked via the trigger
input. The TCB is write-only, and read always
returns O..
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are 1
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
Specification register. If REB is 0, retriggers
are ignored and the countdown continues normally. If REB is I, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output
is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECE] bit is 0), the down-counter is clocked
internally by a Signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is 1), the down-counter is decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to I,
and if interrupts are enabled (IE = 1), an inter~
rupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to 1
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(CIP) status bit in the Gommand and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16-bit register, accessible as two
8-bit registers, which mirrors the contents of
the down-counter. This register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a 1 to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.
Interrupt Logic Operation. The CIa has five
potential sources of interrupts: the three
counter/timers and Ports A and B. The
priorities of these sources are fixed in the
following order: Counter/Timer 3, Port A,
Counter/Timer 2, Port B, and Counter/Timer
1. Since the counter/timers all have equal
capabilities and Ports A and B have equal
capabilities, there is no adverse impact from
the relative priorities.
The CIa interrupt priority, relative to other
components within the system, is determined
by an interrupt daisy chain. Two pins, Interrupt Enable In (IEI) and Interrupt Enable Out
(lEO), provide the input and output necessary
to implement the daisy chain. When lEI is
pulled Low by a higher priority device, the
CIa cannot request an interrupt of the CPU.
The following discussion assumes that the IEI
line is High.
Each source of interrupt in the CIa contains
three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bi\, an Interrupt Under Service (IUS)
Functional
Description
(Continued)
Programming
status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is 1.
The IUS status bit is set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge" commences.
It can also be set directly by the CPU . Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do not request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off individual sources of interrupts.
When IE is set to 1, interrupt is generated normally. When IE is set to 0, the IP bit is set
when an event occurs that wouid normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the CIO to be
disabled without having to individually set
each IE to O. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain
(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to 1, the CIO's IEO is forced Low,
independent of the state of the CIO or its lEI
input, and all lower priority devices' interrupts
are disabled.
As part of the Interrupt Acknowledge cycle,
the CIO is capable of responding with an 8-bit
interrupt vector that specifies the source of the
interrupt. The CIO contains three vector
registers: one for Port A, one for Port B, and
one shared by the three counter/timers. The
vector output is inhibited by setting the No
Vector (NV) control bit to 1. The vector output
can be modified to include status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = 1, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this ,way, all the information obtained by the vector, including
statu's, can be obtained with one additional
instruction when VIS is set to O. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the CIO in a polled environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.
The data registers within the CIO are
directly accessed by address lines Ao and Al
(Table 3). All other internal registers are
accessed by the following two-step sequence,
with the address lines specifying a control
operation. First, write the address of the target
register to an internal 6-bit Pointer Register;
then read from or write to the target register.
The Data registers can also be accessed by
this method.
An internal state machine determines if
accesses with Ao and Al equalling 1 are to the
Pointer Register or to an internal control
register (Figure 11). Following any control
read operation, the state machine is in State b
(the next control access is to the Pointer
Register). This can be used to force the state
machine into a known state. Control reads in
State 0 return the contents of the last register
pOinted to. Therefore, a register can be read
continuously without writing to the Pointer.
While the CIO is in State 1 (next control
access is to the register pOinted to), many
internal operations are suspended-no IPs are
set and internal status is frozen. Therefore, to
minimize interrupt latency and to allow continuous status updates, the CIO should not be
left in State 1.
The CIO is reset by forcing RD and WR Low
simultaneously (normally an illegal condition)
or by writing a 1 to the Reset bit. Reset
disables all functions except a read from or
write to the Reset bit; writes to all other bits
are ignored, and all reads return 01 H. In this
state, all control bits are forced to 0 and may
be programmed only after clearing the Reset
bit (by writing a a to it).
Register
a
a
Port C's Data Register
SOF~:ARE
RESET
Port B's Data R~gister
a
a
WR TO REG.O
(BITO = 1)
Port A's Data Register
Control Registers
Tablo 3. Registor Seloction
2021-002
HARDWARE
NOTE:
State changes occur only when AO = Al = 1. No other
accesses have effect.
Figuro 11. Stato Machino Oporation
461
N
CO
en
W
en
fl
o
Registers
Master Interrupt Control Register
Address: 000000
(ReadIWrite)
Master Configuration Control Register
Address: 000001
(ReadIWrite)
I0 10.1 0 10.1 0 10,1 0, IDo I ,
7
5
3
INTERRUPT~
JJ
~I
LL
MASTER
ENABLE (MIE)
.
DISABLE LOWER CHAIN (DLC)
NO VECTOR (Ny)
•
PORT A VECTOR INCLUDES
STATUS (PA VIS)
PORTB~~ IL 'O"~'M'." ''''
RESET
CONTROLS (LC)
ENABLE (PBE)
RIGHT JUSTIFIED ADDRESSES
0 = SHIFT LEFT (Ao from AD,)
1 = RIGHT JUSTIFY (Ao !rpm ADo)
COUNTERfTlMER 1
ENABLE (CT1E)
COUNTERfTlMERS VECTOR
INCLUDES STATUS (CT VIS)
COUNTERfTlMER 2
ENABLE (CT2E)
PORT B VECTOR INCLUDES
STATUS (PB VIS)
PORT C AND COUNTERI
TIMER 3 ENABLE
(PCE AND CT3E)
LC1
LCO
1
1
0
1
.
. T T g~U1~:~~~~~~Ri,.'~~i~~TN~ENT
CIT 1'8 OUTPUT TRIGGERS CIT 2
CIT 1'8 00fPUf IS CIT 2'.
COUNT INPUT
PORT A ENABLE (PAE)
' - - - - - PORT LINK CONTROL (PLC)
0= PORTS A AND B OPERATE INDEPENDENTLY
1 = PORTS A AND B ARE LINKED
Figure 12. Master Control Registers
Port Handshake Specification Registers
Addresses: 100001 Port A
101001 Port B
(ReadIWrite)
Port Mode Specification Registers
Addresses: 100000 Port A
10 1000 Port B
(ReadlWrite)
I~I~I~I~I~I~I~I~I
PORTTYPE~
.SELECTS (PTS)
PTS1 PTSO.
OBIT PORT
o 1 INPUT PORT
0 OUTPUT PORT
1
1
1 BIDIRECTIONAL
PORT
o
INTERRUPT ON TWO
BYTES (ITB)
SINGLE BUFFERED
MODE (SB)
L
LATCH ON PATIERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (DTE)
(HANDSHAKE MODES) ,
HANDSHAKE TY. PE SPECIFICATION
BITS (HTS)
-.J.
I ---c '''''''''.''''''"''"0'
HTS1 HTSO
o 0 INTERLOCKED HANDSHAKE
o 1 STROBED HANDSHAKE
0 PULSED HANDSHAKE
1
1
1 THREE·WIRE HANDSHAKE
PATIERN MODE SPECIFICATION
BITS (PMS)
PMS1 PMSO
- - --0- DISABLE PATIERN MATCH
1 "AND"MODE
o "OR" MODE
1 "OR·PRIORITY ENCODED
VECTOR" MODE
BITS
~~~~~~~I~H~ ~~~.C°o"NSTANT.
LSB IS FORCED 1.
REQUESTIWAIT SPECIFICATION BITS
(RWS)
RWS2 RWS1 RWSO FUNCTION
o
- - REQUESTIWAIT DISABLED
o
OUTPUT WAIT
o
INPUT WAIT
1
SPECIAL REQUEST
1
OUTPUT REQUEST
1
INPUT REQUEST
' - - - - - INTERRUPT ON MATCH ONLY (IMO)
Port Command and Status Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
I
INTERRUPT UNDER
SERVICE (IUS)
INTERRUPT PENDING (IP)
IUS, IE, AND IP ARE WRITIEN USING
THE FOLLOWING CODE:
CLEAR IUS
o
o
o
o
SET IP
1
0
CLEAR IP
1
0
NULL CODE
CLEAR IP & IUS
SET IUS
SET IE
CLEAR IE
~
L
L
INTERRUPT ENABLE (IE)
0
0
0
INTERRUPT ON ERROR (IOE)
PATIERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (IRF)
(READ ONLy)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLy)
1
1
1
1 0
1
1
INTERRUPT ERROR (ERR) - - - - - - '
(READ ONLy)
Figure 13. Port Specifications Registers
462
2014·009, 010
f
Registers
(Continued)
Data Path Polarity Registers
Addresses: 100010 Port A
10 10 10 Port B
000101 Port C (4 LSBs only)
(Read/Write)
Data Direction Registers
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(Read/W rite)
' - - - - - DATA DIRECTION (DD)
0 .. OUTPUT BIT
1 =INPUT BIT
' - - - - - DATA PATH POLARITY (DPP)
o~ NON·INVERTING
1 ~ INVERTING
Special II 0 Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(Read/Write)
' - - - - - - SPECIAL INPUT/OUTPUT (SIO)
0= NORMAL INPUT OR OUTPUT
1 = OUTPUT WITH OPEN DRAIN OR
INPUT WITH 1'9 CATCHER
Figure 14. Bit Path Deflnltlon Registers
Port Data Registers
Addresses: 001101 Port A *
001110 Port B*
(Read/Write)
Port C Data Register
Address: 001111 *
(Read/Write)
4 MSBs
O. WRITING OF CORRESPONDING LSD ENABLED
1- WRITING OF CORRESPONDING LSD INHIBITED
(READ RETURNS 1)
"These registers can be
addressed directly.
Figure IS •. Port Data Registers
Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(Read/Write)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Port B
(Read/Write)
PM PT PP
- - X
X
o
1
o
1
PATTERN SPECIFICATION
BIT MASKED OFF
ANY TRANSITION
ZERO
ONE
ONE TO'ZERO TRANSITION (\)
ZERO·TO·ONE TRANSITION (f)
Pattern Mask Registers (PM)
Addresses: 100111 Port A
10 1111 Port B
(Read/Write)
Figure 16. Pattern Deflnltlon Registera
2014-011. 012. 013
463
Registers
(Continued)
Counter/Timer Command and StClt1!S Registers
Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2
001100 Counter/Timer 3
(ReadIPartial Write)
"""";. ""'.."'''''"~ -1 I I
INTERRUPT ENABLE (IE)
I
I
INTERRUPT PENDING (IP)
.I
I
NULL CODE
0
0
CLEAR IP • IUS
0
0
SET IUS
0
1
CLEAR IUS
0
1
1
SET IP
1
0
0
CLEAR IP
1
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE:
0
0
1
SET IE
1
0
CLEAR IE
1
1
L COUNT IN PROGRESS (CIP)
ug~
(READ ONLy)
TRIGGER COMMAND BIT (TCB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (OCB)
READ COUNTER CONTROL (RCC)
(READ/SET ONLYCLEARED BY READING CCR LSB)
INTERRUPT ERROR (ERR) - - - - - '
(READ ONLy)
Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/Timer 1
011101 Counter/Timer 2
011110 Counter/Timer 3
(Read/Write)
sm.
CONTINUOUS
GLE CYCLE (C/SC)
JJ~
EXTERNAL OUTPUT
ENABLE (EOE)
EXTERNAL COUNT
ENABLE (ECE)
EXTERNAL TRIGGER
ENABLE (ETE)
ILom'mo=~m
SELECTS (DCS)
DCS1DCSO
( ) ( ) PULSE OUTPUT
1 ONE·SHOT OUTPUT
1
0 SQUARE·WAVE OUTPUT
1
1 DO NOT SPECIFY
o
RETRI3GER ENABLE BIT (REB)
' - - - - - EXTERNAL GAT!: ENABLE (EGE)
Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer l's MSB
010001 Counter/Timer l's LSB
010010 Counter/Timer 2's MSB
010011 Counter/Timer 2'8 LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)
MOST - - - - - '
SIGNIFICANT
BYTE
' - - - - - LEAST
SIGNIFICANT
BYTE
Counter/Timer Time Constant Registers
Addresses: 010110 Counter/Timer l's MSB
010111 Counter/Timer l's LSB
011000 Counter/Timer 2's MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/Timer 3's LSB
(Read/Write)
MOST - - - - - '
SIGNIFICANT
BYTE
' - - - - - LEAST
SIGNIFICANT
BYTE
Figure 17. Counter/Timer Registers
464
2014-014
Registers
Current Vector Register
Address: 011111
(Read only)
Interrupt Vector Register
Addresses: 000010 Port A
000011 Port B
000100 Counter/Timers
(Read/Write)
(Continued)
L -_ _ _ INTERRUPT VECTOR BASED
ON HIGHEST PRIORITY
UNMASKED IP.
IF NO INTERRUPT PENDiNG
ALL l's OUTPUT.
' - - - - - INTERRUPT VECTOR
PORT VECTOR STATUS
PRIORITY ENCODED VECTOR MODE:
03
X
~
X
01
X
NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH
ALL OTHER MODES:
03 02 01
ORE iRF PMF NORMAL
o 0 0 ERROR
COUNTERITIMER STATUS
02
o
o
1
1
01
0
1
0
crr3
crr 2
crr 1
1
ERROR
Figure 18. Interrupt Vector Registera
Register
Address
Summary
Address
000000
000001
000010
000011
000100
000101
000110
000111
Address
001000
001001
001010
001011
001100
001101
001110
001111
Address
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
2014-015
Main Control Registers
Register Name
Master Interrupt Control
Master Configuration Control
Port A's Interrupt Vector
Port B's Interrupt Vector
CounterlTimer's Interrupt Vector
Port C's Data Path Polarity
Port C's Data Direction
Port C's Special 1/0 Control
Most Often Accessed Registers
Register Name
Port A's Command and Status
Port B's Command and Status
CounterlTimer l's Command and Status
CounterlTimer 2's Command and Status
CounterlTimer 3's Command and Status
Port A's Data (can be accessed directly)
Port B's Data (can be acces.sed directly)
Port C's Data (can be accessed directly)
Address
100000
100001
100010
100011
100100
100101
100110
100111
Address
101000
101001
101010
101011
lCI100
101101
101110
101111
Port A Specification Registers
Register Name
Port A's Mode Specification
Port A's Handshake Specification
Port A's Data Path Polarity
Port A's Data Direction
Port A's Special I/O Control
Port A's Pattern Polarity
Port A's Pattern Transition
Port A's Pattern Mask
Port B Specification Registers
Register Name
Port B's Mode Specification
Port B's Handshake Specification
Port B's Data Path Polarity
Port B's Data Direction
Port B's Special 1/0 Control
Port B's Pattern Polarity
Port B's Pattern transition
Port B's Pattern Mask
Counter/Timer Related Registers
Register Name
CounterlTimer l's Current Count-MSBs
CounterlTimer l's Current Count-LSBs
CounterlTimer 2's Current Count-MSBs
CounterlTimer 2's Current Count-LSBs
CounterlTimer 3's Current Count-MSBs
CounterlTimer 3's Current Count-LSBs
CounterlTimer I's Time Constant-MSBs
CounterlTimer l's Time Constant-LSBs
Counter/Timer 2's Time Constant-MSBs
CounterlTimer 2's Time Constant-LSBs
CounterlTimer 3's Time Constant-MSBs
CounterlTimer 3's Time Constant-LSBs
CounterlTimer l's Mode Specification
CounterlTimer 2's Mode Specification
CounterlTimer 3's Mope Specification
Current Vector
465
Timing
Read Cycle. At the beginning of a read cycle,
the CPU places an address on the address bus.
Bits Ao and Al specify a CIO register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIO. When
Read (RD) goes Low, data from the specified
register is gated onto the data bus.
Ao-Ai
CE
iffi
Do·D7
==x
Write Cycle. At the beginning of a write
cycle, the- CPU places an address on the data
bus. Bits Ao and Al specify a CIO register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIO. When
WR goes Low, data placed on the bus by the
CPU is strobed into the specified CIO register.
C
ADDRESS VALID
~
Ao-Ai
/
(
READ DATA
lEI
lEO
(
-r--
WRITE DATA
Figure 20. Write Cycle Timing
Interrupt Acknowl~e. The CIO pulls its
Interrupt Request (INT) line Low, requesting
interrupt service from the CPU, if an Interrupt
Pending (IP) bit is set and interrupts are
enabled. The CPU responds with an Interrupt
Acknowledge cycle. When Interrupt Acknowledge (lNTACK) goes true and the IP is set, the
INTACK
I
\
Do-D7
Figure 19. Read Cycle Timing
INT
/
VIii
}--
C
ADDRESS VALID
~
Ci
I
\
==x
CIO forces Interrupt Enable Out (lEO) Low,
disabling all lower priority devices in the interrupt daisy chain. If the CIO is the highest
priority device requesting service (IEI is
High), it places its interrupt vector on the data
bus and sets the Interrupt Under Service (IUS)
bit when Read (RD) goes Low.
------------~£F<-------JI
~F-'____________..1
1
J)
"
'-nf-'- - - - /~
Do-D7
-----------...,£',,'-------«
VECTOR
}--
Figure 21. Interrupt Acknowledge Timing
466
2021-003, 004, 005
Absolute
Maximum
Ratings
Voltages on all inputs and outputs
with respectto GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maxi:
mum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
folloWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:
+4.75 V ~ Vee ~ +5.25 V
GND = a V
r! TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
111
II
+5V
+5V
2.2K
dr
2•2K
FROM OUTPUT
UNDER TEST
50 PF
Figure 23. Open-Drain Test Load
Figure 22. Standard Test Load
DC
Characteristics
Symbol
Parameter
Min
Max
Unit
Vee+ 0 .3
0.8
V
VIH
Input High Voltage
2.0
VIL
VOH
Input Low Voltage
-0.3
Output High Voltage
VOL
Output Low Voltage
2.4
Condition
V
V
IoH = - 250 p.A
V
V
p.A
IOL = +2.0 rnA
IoL = +3.2 rnA
0.4 :S VIN :S + 2.4 V
0.4 :S VOUT :S +2.4 V
IlL
Input Leakage
0.4
0.5
±1O.0
IOL
Output Leakage
± 10.0
p.A
Icc
Vee Supply Current
200
rnA
Vee = 5 V ± 5% unless otherwise specified, over speCified temperature range.
Capacitance
Symbol
C IN
C OUT
Cvo
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
Test Condition
10
15
20
pF
pF
pF
Unmeasured Pins
Returned to Ground
f = 1 MHz, over specified temperature range.
8085-0209, 0001
467
CPU
Interface
Timing
PCLK
AO-Ai
Do-Dr
WRITE _ _ _ _ _ _
DATA VALID
~
----~/~
1--/------,@rr'L
"MWR~'
CE
Interrupt
Timing
PATTERNINPUTIS)
MATCH
BIT PORT
\ \ - ._ __
~___p~A~n~E~R~N~M~~~C~H:ES~__________~____________
-,@I-_ _ _ _--._I
t.._ _ _ _ _ _ _ _
COUI4TER
I"PUT _ _ _ _ __
PCLK
Interrupt
Acknow ledge
Timing
Do-Dr
lEI
lEO
468
2021-006, 007, 008
No.
Min
Symbol
Parameter
TcPC
PCLK Cycle time
4 MHz
Max
250
4000
6MHz
Min
Max
165
4000
2
TwPCh
PCLK Width (High)
105
2000
70
2000
3
TwPCI
PCLK Width (Low)
105
2000
70
2000
4
TrPC
PCLK Rise Time
20
5 -TfPC
PCLK Fall Time
20
7
ThIA(PC)
t Setup Time
IN TACK to PCLK t Hold Time
8
TsIA(RD)
IN TACK to RD 1 Setup Time
9
ThIA(RD)
INTACK to RD
10 -
TsIA(WR) - - INTACK to WR 1 Setup Time
6
TsIA(PC)
10
15
INTACK to PCLK
100
0
0
200
200
t Hold Time
100
0
0
200
200
11
ThIA(WR)
INTACK to WR
t Hold Time
0
0
12
TsA(RD)
Address to RD 1 Setup Time
80
80
13
ThA(RD)
Address to RD
14
TsA(WR)
Address to WR 1 Setup Time
15 -
ThA(WR) - - Address to WR
t Hold Time
0
16
TsCEl(RD)
CE Low to RD 1 Setup Time
0
17
TsCEh(RD)
CE
18
ThCE(RD)
CE to RD
19
TsCEl(WR)
CE Low to WR 1 Setup Time
20 -
TsCEh(WR) - - CE High to WR 1 Setup Time
21
ThCE(WR)
CE to WR
22
TwRDl
RD Low Width
23
TdRD(DRA)
RD
24
TdRDf(DR)
RD 1 to Read Data Valid Delay
H~gh
t Hold Time
to RD 1 Setup Time
t Hold Time
t Hold Time
1 to Read Data Active Delay
Notes*t
0
0
~
80
80
(JI
100
0
CO
W
0
('i)
0
6
70
0
till
0
0
0
100
70
0
0
390
250
0
0
180
255
26
TdRD(DRz)
t to Read Data Not Valid Delay
RD t to Read Data Float Delay
27
TwWRl
WR Low Width
28
TsDW(WR)
Write Data to WR 1 Setup Time
29
ThDW(WR)
Write Data to WR
30
Trc
Valid Access Recovery Time
31
TdPM(INT)
Pattern Match to INT Delay (Bit Port)
2+800
2
6
32
TdACK(lNT)
ACKIN to INT Delay (Port with Handshake)
10+600
10
4,6
33
TdCI(lNT)
Counter Input to INT Delay (Counter Mode)
2+700
2
6
34
TdPC(lNT)
PCLK to INT Delay (Timer Mode)
3+700
3
6
25- TdRDr(DR)-- RD
t Hold Time
0
0
45
70
390
250
0
0
0
1000*
650
0
3
35
TsIA(RDA)
INTACK to RD 1 (Acknowledge) Setup Time
350
250
36
TwRDA
RD (Acknowledge) Width
350
250
37
TdRDA(DR)
RD! (Acknowledge) to Read Data Valid Delay
250
180
38
TdIA(lEO)
INTACK! to lEO ! Delay
350
250
150
100
39-TdIEI(IEO)--IEI to lEO Delay
40
TsIEI(RDA)
lEI to RD! (Acknowledge) Setup Time
100
70
41
ThIEI(RDA)
100
70
42
TdRDA(lNT)
t (Acknowledge) Hold Time
RD ! (Acknowledge) to INT t Delay
lEI to RD
NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is measured to the time when the output has
changed 0.5 V with minimum ac load and maximum dc load.
3. Trc is the specified number or 3 TcPC, whichever is longer.
4. The delay is from DAV I for 3-Wire Input Handshake. The
delay is from DAC r for 3-Wire Output Handshake.
5. The parameters for the devices in any particular daisy chain
. must meet the following constraint: The delay from INTACK I
2
600
5
5
55
600
to RD I must be greater than the sum of TdIA(1EO) for the
highest priority peripheral, TsIEI(RDA) for the lowest priority
peripheral, and TdLEI(1EO) for each peripheral separating them
in the chain.
6. Units are equal to TcPC plus ns.
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "I" and 0.8 V for a logic "a".
t Units in nanoseconds (ns), except as noted .
469
Strobed
Handshake
INPUT
OUTPUT
Interlocked
Handshake
DATA
INPUT
RFD
==x
'k' ---_____
~~
DATA VALID
_~y~J-
DATA
OUTPUT
ACKIN
DAY
3-Wire
Handshake
DATA
DAY
INPUT
INPUT
RFD
OUTPUT
DAC
OUTPUT
DATA
DAC
INPUT
OUTPUT
RFD
INPUT
DiY
OUTPUT
470
2014-022, 023, 024
No.
Symbol
Parameter
Min
TsDI(ACK)
ThDI(ACK)
Data Input to ACKIN I Setup Time
0
Data Input to ACKIN I Hold TimeStrobed Handshake
TdACKf(RFD)
ACKIN I to RFD I Delay
0
3
4
TwACKl
ACKIN Low Width-Strobed Handshake
5 - TwACKh--- ACKIN High Width-Strobed Handshake
RFD I to ACKIN I Delay
TdRFDr(ACK)
0
6
TsDO(DAV)
Data Out to DA V I Setup Time
7
25
TdDAVf(ACK) DA V I to ACKIN I Delay
8
0
ThDO(ACK)
Data Out to ACKIN I Hold Time
9
2
10 - TdACK(DAV) - ACKIN I to DAV I Delay
2
THDI(RFD)
11
Data Input to RFD I Hold Time-Interlocked
Handshake
TdR'FDf(ACK)
12
RFD I to ACKIN I Delay Interlocked Handshake
0
TdACKr(RFD)
13
ACKIN I (DA V I) to RFD I Delay-Interlocked and
3-Wire Handwshake
0
TdDAVr(ACK) DAV I to ACKIN I (RFD I)-Interlocked and 3-Wire
14
Handshake
0
15 - TdACK(DAV)- ACKIN I (RFD I) to DAV I Delay-Interlocked and
3-Wire Handshake
0
TdDAVIf(DAC) DAV I to DAC I Delay-Input 3-Wire Handshake
16
0
ThDI(DAC)
17
Data Input to DAC I Hold Tizpe-3-Wire Handshake
0
TdDACOr(DAV) DAC I to DAV I Delay-Input 3-Wire Handshake
18
0
TdDAVIr(DAC) DAV I to DAC I Delay-Input 3-Wire Handshake
19
0
20 - TdDAVOf(DAC) DAV I to DAC I Delay-Output 3-Wire Handshake - 0
ThDO(DAC)
21
Data Output to DAC I Hold Time-3-Wire
,Handshake
2
TdDACIr(DAV) DAC I to DA V I Delay-Output 3-Wire Handshake
22
2
23
TdDAVOr(DAC) DAV I to DAC I Delay-Output 3-Wire Handshake
0
2
4MHz
Max
6MHz
Min
Max
Notes*t
0
0
0
20
0
2
2
2
2-
IIen
0
0
W
0
n
....
0
~
0
0
0
0
0
0
2
2
0
2
2
NOTES:
1. This time can be extended through the use of deskew timers.
2. Units equal to Tcpe.
• Timings are preliminary and subject to change. All timing refer-'
ences assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
Units in nanoseconds (ns), except as noted.
t
471
Counter/
Timer
Timing
PCLK
PCLK'2
(INTERNAL) _ _ _ _ _...1
COUNTER
INPUT
TRIGG~R
INPUT
GATE
INPUT
COUNTER
OUTPUT
No.
1
2
3
4MHz
Max
6MHz
Min
Max
Symbol
Parameter
Min
TeCI
TClh
Counter Input Cycle Time
Counter Input High Width
500
230
330
150
TWCIl
Counter Input Low Width
230
150
Notes*t
15
20
Counter Input Fall Time
4
TfCI
5-TrCI - - - - - Counter Input Rise Time - - - - - - - - - - - - - - - 20 ------------15----------Trigger Input to PCLK I Setup Time (Timer Mode)
TsTI(PC)
6
7
TsTI(CI)
Trigger Input to Counter Input I Setup Time
(Counter Mode)
8
9
10 -
TwTI
TsGI(PC)
Trigger Input Pulse Width (High or Low)
Gate Input to PCLK I Setup Time (Timer Mode)
TsGI(CI) - - - Gate Input to Counter Input I Setup Time - - - - - - - - - - - - - - - - - - - - - - - (Counter Mode)
11
12
ThGI(PC)
ThGI(CI)
Gate Input to PCLK I Hold Time (Timer Mode)
13
1<1.
TdPC(CO)
TdCI(CO)
PCLK to Counter Output Delay (Timer Mode)
Gate Input to Counter Input I Hold Time
(Counter Mode)
Counter Input to Counter Output Delay
(Counter Mode)
NOTES:
1. These parameters must be met to guarantee trigger or gate
are valid for the next counter/timer cycle.
472
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "I" and 0.8 V for a logic "0".
i Units in nanoseconds (ns).
2021-009
REQUEST/
WAIT
Timing
No.
Symbol
Parameter
Min
4MHz
Max
6 MHz
Min
Max
Notes*t
RD j to REQ j Delay
TdRD(REQ)
500
RD j to WAIT j Delay
2
TdRD(WAIT)
500
WR j to REQ j Delay
3
TdWR(REQ)
500
WR j to WAIT j Delay
4
TdWR(WAIT)
500
5-TdPC(REQ)--PCLK I to REQ I D e l a y - - - - - - - - - - - - 300
6
7
8
TdPC(WAIT)
TdACK(REQ)
TdACK(WAIT)
PCLK j to WAIT I Delay
ACKIN j to REQ I Delay
ACKIN I to WAIT I Delay'
NOTES:
1. The delay is fronm DAV I for 3-Wire Input Handshake. The
delay is from DAC t for 3-Wire Output Handshake.
2. Units equal to TcPC + ns.
300
8+ 100
10 + 600
1,2
1,2
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
t Units in nanoseconds (ns). except as noted.
Reset
Timing
RESET
INTERNAL
No.
----------------------~j'
Symbol
Parameter
Min
2
TdRD(WR)
TdWR(RD)
3
TwRES
Delay from RD I to WR I for No Reset
Delay from WR I to RD I for No Reset
Minimum Width of RD and WR both Low for Reset
50
50
250
1
• Timings are preliminary and subject to change. All timing references assume 2.0 V for a logic "1" and 0.8 V for a logic "0".
2021-010,011
t
4MHz
Max
6MHz
Min
Max
Notes*t
50
50
250
Unites in nanoseconds (ns).
473
Miscellaneous
Port
Timing
ANY INPUT
1'. CATCHER
INPUT
-----+r
~1'--:
- - -
~
------~I
\~
___________
~;.;;. ------~~,f2521< 1.. .------
PATTERN MATCH
No.
2
3
4
5
6
------..I~
4MHz
Max
SMHz
Min
Max
100
100
100
100
Symbol
Parameter
TrI
T£1
Tw1's
Any Input Rise Time
Any Input Fall Time
l's Catcher High Width
TwPM
Pattern Match Input Valid (Bit Port)
Data Latched on Pattern Match Setup Time (Bit Port)
250
750
0
500
Data Latched on Pattern Match Hold Time (Bit Port)
1000
650
TsPMD
ThPMD
Min
NOTES:
1. If the input is programmed inverting, a Low-going pulse of the
same width will b~ detected.
Ordering
Information
Product
Number
Package/
Temp
Speed
Notes*t
170
o
• Timings are preliminary and subject to change. All timing
references assume 2.0 V for a logic "I" and 0.8 V for a logig "0"
t Units in nanoseconds (ns).
Description
Product
Number
Package/
Speed
Temp
Description
28536
CE
4.0 MHz
CIO (40-pin)
Z8536A
CE
6.0 MHz
CIO (40-pin)
28536
CM
4.0 MHz
Same as above
Z8536A
CM
6.0 MHz
Same as above
28536
CMB
4.0 MHz
Same as above
Z8536A
CMB
6.0 MHz
Same as above
28536
CS
4.0 MHz
Same as above
Z8536A
CS
6.0 MHz
Same as above
Z8536
DE
4.0 MHz
Same as above
Z8536A
DE
6.0 MHz
Same
28536
DS
4.0 MHz
Same as above
28536A
DS
6.0 MHz
Same as above
28536
PE
4.0 MHz
Same as above
Z8536A
PE
6.0 MHz
Same as above
PS
4.0 MHz
Same as above
Z8536A
PS
6.0 MHz
Same as above
28536
NOTES: C = Ceramic, D = Cerdip, P = Plastic; E
with Class B processing, S = O°C to + 70°C.
474
~
= -40°C to
+85°C, M
= -55°C to
125°C, MB
= -55°C
3.S
above
to 125°C with MIL-STD-883
2014-028 OO·2021'()3
!8$$ n (cRotCn" (GentleraRo~
annuail ll(UHdl lief
Spea:iiiiicali@l1l1
Zilog
September 1983
28601 Single-Chip Microcomputer with 2K ROM
28603 Prototyping Device with EPROM Interface
Features
m Complete microcomputer, 2K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
62K bytes addressable external space each
for program and data memory.
El
(J
R~gister Pointer so that short, fast instructions can access any of nine working
register groups in 1 JLS.
lJ
On-chip oscillator that accepts crystal or external clock drive.
a 144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.
General
Description
Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-,bit programmable prescaler.
lJ
Average instruction execution time of
1.5 JLs, maximum of 3 JLS.
C
Low-power standby option which retains
contents of general-purpose registers.
[]
Vectored, priority interrupts for I/O,
counter/timers, and UART.
[J
Single + 5 V power supply-all pins TTLcompatible.
The Z8601 microcomputer introduces a new
level of sophistication to single-chip architecture. Compared to earlier Single-chip microcomputers, the Z8601 offers faster execution;
more efficient use of memory; more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8601 can be
tailored to the needs of its user. It can' be con-
figured as a stand-alone microcomputer with
2K bytes of internal ROM, a traditional microprocessor that manages up to 124K bytes of
external memory, or a parallel-processing element in a system with other processors and '
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.
+5V
PORT 2
(BIT PRO·
GRAMMABLE)
PORT 0
(NIBBLE
PROGRAMMABLE)
110
110 OR A,-A"
PORT 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL 110
AND CONTROL
PORT 1
(BYTE
PROGRAMMABLE)
110 OR ADo-AD,
Figure 1. Pin Functions
2037 -00 I. 002
40
P3,
XTAL2
P3,
XTALl
P2,
P3,
P2,
P3 0
P2,
RESET
P2.
RIW
P2,
os
P2,
AS
P2,
P3,
P2 0
GND
P3,
P3,
P3.
POo
Pl,
PO,
Pl,
PO,
Pl,
PO,
Pl.
PO.
Pl,
PO,
Pl,
PO,
Pl,
PO,
Pl o
Figure 2. Pin Assignments
487
lSI
GO
I...
t I)
••
n
c:I,
.,
Architecture
Z8601 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
.
Microcomputer applications demand powerful I/O capabilities. The Z8601 fulfills this with
32 pins dedicated to input and output. These
lines are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status signals, serial or
parallel I/O with or without haridshake, and an
address/data bus for interfacing external
memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the Z8601
can assume many different memory and I/O
configurations. These configurations range
from a self-contained microcomputer to a
OUTPUT
Vee
microprocessor that can address 124K bytes of
_external memory.
Three basic address spaces are available to
support thi's wide range of configurations: program memory (internal and external), data
memory (external) and the register file (Internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers.
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized
because one of the on-chip timers supplies the
bit rate.
GND
!!
IlllUl1
1/0
(BIT PROGRAMMABLE)
ADDRESS OR 1/0
(NIBBLE PROGRAMMABLE)
ADDRESSIDATA OR 1/0
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
Pin
Description
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for. all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Port,s 0 and 1, Data Strobe and Read/Write.
DS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
POO-P07' P1o-PI7' P20-P27' P30-P37. 1/0 Port·
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports
that can be configured under program control
488
for I/O or external memory interface.
RESET. Reset {input, active Low); RESET initializes the 28601. When RESET is deactivated,
program execution begins from internal program location OOOCH.
R/W. Read/Write (output). R/W is Low when
the 28601 is writing to external program or
data memory.
XTALl, XTAL2. Crystall, Crystal 2 (time-base
input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz maximum) or an external single-phase clock (8 or
12 MHz maximum) to the on-chip clock
oscillator and buffer.
2037-003
Address
Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 2048 bytes
consist of on-chip mask-programmed ROM. At
addresses 2048 and greater, the 28601
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The 28601 can address 62K
bytes of external data memory beginning at
location 2048 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-R127) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure 6.
28601 instructions can access registers
655351"'""----------,
5535
EXTERNAL
ROM OR RAM
2048
2047
ON·CHIP
ROM
Location of
flrstbyteot
Instruction
executed
aHarrese'
~ ~-----------11
lRa5
10
IRaS
9
IRa4
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
8
IRa4
7
IRa3
6
IRa3
51"
IRa2
4~
IRa2
3
IRal
2
IRal
1
IRaO
0
IRaO
EXTERNAL
DATA
MEMORY
~~:~ 1 - - - - - - - - - - - 1
NOT ADDRESSABLE
Figure 4. Program Memory Map
LOCATION
IDENTIFIERS
255
STACK POINTER (BITS 7-0)
SPL
254
STACK POINTER (BITS 15-8)
SPH
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
RP
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT' REaUEST REGISTER
IRa
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
P01M
P3M
247
PORT 3 MODE
246
PORT 2 MODE
P2M
245
TO PRESCALER
PREO
244
TIMER/COUNTER 0
Figure 5. Data Memory Map
1-~;:::=+------......,255
-
-{
~'-------I
~
.....- - - - - - - - -... 240
The upper n!bble 01 the reglsterflle address
provided by the register pointer speCifies
the actlveworking·reglstergroup.
12
TO
243
T1 PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
240
SERIAL I/O
SIO
PREl
T1
NOT
IMPLEMENTED
The lower
nibble 01
the-register
SPECIFIED WORKING·
REGISTER GROUP
127
file address
...-- the Instruction
provided by
points to the
specilied
register.
GENERAL·PURPOSE
REGISTERS
15
PORT 3
P3
PORT 2
P2
PORT 1
Pl
PORT 0
PO
1-------------3
I/O PORTS
Figure 7. The Register Pointer
2037·004, 005, 006, 007
489
Address
Spaces
(Continued)
directly or indirectly with an 8-bit address
field. The 28601 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.
Stacks. Either the internal register file or the
external data memory can be usedfor the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-R127).
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second for 8
MHz and 94.8K bits/second for 12 MHz.
The 28601 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity is also available as an option. Eight
data bits are always transmitted, regardless of
parity selection. If parity is enabled, the eighth
bit is the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.
Transmitted Data
Received Data
(No Parity)
(No Parity)
I~I~I~I~I~I~I~I~I~I~I
LSTART BIT
LSTART BIT
' - - - - - - E I G H r DATA BITS
' - - - - - - E I G H T DATA BITS
1' - - - - - - - - - - O N E STOP BIT
TWO STOP BITS
Transmitted Data
Received Data
(With Parity)
(With Parity)
ISP ISP I P I0 10 10,1 0 10,1 0, Ido IST I
1~lpl~I~I~I~I~I~I~I~1
'1'1
6
5
3
II,-
_LSTARTBIT
' - - - - - S E V E N DATA BITS
LSTARTBIT
' - - - - - S E V E N DATA BITS
L - - - - - - - - - O O O PARITY
TWO STOP BITS
PARITY ERROR FLAG
' - - - - - - - - - - O N E STOP BIT
Figure 8. Serial Data Formats
Counter/
Timers
490
Ths'28601 contains two 8-bit programmable
counter/timers (To and Tl), each driven by its
own 6-bit programmable prescaler. The Tl
prescaler can be driven by internal or external
clock sources; however, the To pres caler is
driven by the internal clock only.
The 6-bit prescalers can divide the ipput frequency of the clock source by any number
from 1 to 64. Each pres caler drives its counter,
which decrements the value (1 to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (Tl)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (singlepass mode) or to automat'ically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
, The clock source for T 1 is user-definable and
can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and 6
MHz maximum for the 12 MHz device.) divided by four, or an external signal input via Port
3. The Timer Mode regi~ter configures the external timer input as an external clock (1 MHz
maximum), a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. The counter/timers
can be programmably cascaded by connecting
the To output to the input of Tl. Port 3 line P36
also serves as a timer output (TOUT) through
which To, Tl or the internal clock can be output.
2037-009
I/O Ports
The 28601'has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to
provide address outputs, timing, status signals,
serial 1/0, and parallel 1/0 with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 1 can be programmed as a byte 1/0
port or as an addressldata port for interfacing
external memory. When used as an 1/0 port,
Port 1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY 1
and DAVI (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port 0 must output the additional lines.
Port 1 can be placed in the high-impedance
state along with Port 0, AS, DS and RIW, allow-
ing the 28601 to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33
as a Bus Acknowledge input and P34 as a Bus
Request output.
Port 0 can be programmed as a nibble 1/0
port, or as an address port for interfacing
external memory. When used as an 1/0 port,
Port 0 may be placed under handshake control. In this configuration, Port 3 lines P32 and
P3s are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the 1/0 direction of the upper
nibble P04-P07.
For external memory references, Port 0 can
provide address bits As-All (lower nibble) or
As-AIS (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as
1/0 while the lower nibble is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the highimpedance state along with Port 1 and the control signals AS, DS and RIW.
Port 2 bits can be programmed independently as input or output. The port is
always available for I/O operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as
the handshake controls lines DAV2 and RDY 2.
The handshake signal assignment for Port 3
lines P31 and P36 is dictated by the direction
(input or output) assigned to bit 7 of Port 2.
Port 3 lines can be configured as I/O or control lines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37)' For serial I/O, lines P30
and P37 are programmed as serial in and serial .
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt
request signals (IRQo-IRQ3); timer input and
output signals (TIN and Tour) and Data
Memory Select (DM).
2037-008
PORT 1
(1/0 OR ADo-AD7)
Figure 9a. Port 1
PORT 0
} (110 OR As-A,.!
Figure 9b. Port 0
PORT 2(110)
HANDSHAKE CONTROLS
} DAV2 AND RDY2
(P3, AND P3sl
Figure 9c. Port 2
-
PORT 3
(110 OR CONTROL)
Figure 9d. Port 3
491
Interrupts
The 28601 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In,. Serial Out, and the two counter/
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
All 28601 interrupts are vectored. When an
interrupt request is granted, an interrupt
machine cycle is entered. This disables all
subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that· interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitors (Cl ::5 15 pF) from each pin to
ground. The specifications for the crystal are
as follows:
Power Down
Standby
.. Option
492
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user asa bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input. This
necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power; 'whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. Figure 10 shows
• AT cut, parallel resonant
• Fundamental type, 8/12 MHz maximum
• Series resistance, Rs ::5 100 n
'the recommended circuit for a battery back-up
supply system.
+5V
o - - - -_ _
-~
Voo
Z8801
J
Figure 10. Recommended Driver Circuit
for Power Oown Operation
2037-010
Z8603
Protopack
Emulator
The Z8603 MPE (Protopack) is used tor
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROMless version of the standard Z8601,
housed in a pin-compatible 40-pin package
(Figure 11).
To provide pin compatibility and interchangeability with the standard maskprogrammed device, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure 1). The
24-pin socket is equipped with 11 ROM
address lines, 8 ROM data lines and necessary
control lines for interface to 2716 EPROM for
the first 2K bytes of program memory.
Pin compatibility allows the user to design
the pc board for a final 40-pin maskprogrammed Z8601, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot production units. When the
final program is established, the user can then
switch over to the 40-pin mask-programmed
Z8601 for large volume production. The Protopack is also useful in small volume applica
tions where masked ROM setup time, mask
charges, etc., are prohibitive and program
flexibility is desired.
Compared to the conventional EPROM
versions of the single-chip microcomputers,
the Protopack approach offers two main
advantages:
L1 Ease of developing various programs during
the prototyping stage. For instance, in
applications where the same hardware
configuration is used with more than one
program, the Z8603 Protopack allows
economical program storage in separate
EPROMs (or PROMs), whereas the use of
separate EPROM-based single-chip
microcomputers is more costly.
C
Figure 11. The Z8603 Microcomputer Protopack Emulator
Instruction
Set
Notation
Addressing Modes. The follOWing notation is used
to describe the addreSSing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Flags. Control Register R252 contains the following
six flags:
Symbols. The following symbols are used in
describing the instruction set.
dst
src
cc
o
Ir
RR
Destination location or contents
Source location or contents
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
Register pointer (control register 253)
RP
Interrupt mask register (control register 251)
IMR
2037-012
Assignment of a value is indicated by the symbol
"-". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
C
Z
S
V
D
H
IR
Elimination of long lead time in procuring
EPROM-based microcomputers.
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Ha.lf-carry flag
Affected flags are indicated by:
11
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
493
Condition
Codes
Value
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Meaning
Flags Set
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Instruction
Formats
OPC
dSI
C
C
1
a
=1
=a
s =a
S =1
V =1
V =a
Z =1
Z =a
Z
Z
a
(8 XOR V) =
(8 XOR V) = 1
[Z OR (8 XOR V)]
[Z OR (8 XOR V)]
=a
C =1
(C = a AND Z = 0)
(C OR Z) = 1
a
1
C
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
OPC
INCr
One-Byte Instructions
ADC, ADD, AND, cp,
LD, OR, SBC, SUB,
TCM, TM, XOR
I
OPC
1--:::';dS"'::t:'-~
OR
11 1 1 01
JP, CALL (Indirect)
dst
1--_"::":":_-01 OR
OPC
VALUE
111 1 01
dst
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD
LD, LDE, LDEI,
LDC, LDCI
'--.....;...;.;..;:.~--'
dst 1 OPC
VALUE
IdStlCCR~
OPC
LD
OR
JP
11 1 1 01
LD
CALL
DJNZ, JR
Two-Byte Instructions
Three-Byte Instructions
Figure
494
12~
Instruction Formats
2037·013
Instruction
Summary
Instruction
and Operation
ADC dst,src
Addr Modo
dst
arc
(Note 1)
Opcodo Flags Affocted
Byte
(Hox) CZSVDH
10
o•
dst - dst + arc + C
ADD dst,src
(Note 1)
00
(Note 1)
50
• 0 •
dst - dst + src
AND dst,src
dst - dst AND src
0
DA
SP - SP - 2
IRR
@SP - PC; PC - dst
D6
D4
------
CCF
EF
* - - - - -
BO
Bl
dst - NOT dst
R
IR
60
61
CP dst,src
dst - src
(Note 1)
DA dst
R
IR
40
41
• X
R
IR
00
01
- * * *- -
dst - DA dst
DEC dst
dst - dst - 1
DECW dst
dst - dst·- 1
RR
IR
RA
-
..
0--
I
80
81
- * *
8F
------
rA
r=O-F
------
*--
FF
------
(Note 1)
40
- • • 0 - -
POP dst
dst - @SP
SP - SP + 1
R
IR
50
51
------
R
IR
RCF
RL dst
. 70
71
CF
o- - - - -
AF
------
RLC dst
R
IR
90
91
R
lR
10
.~ 1~
EO
El
~
lIiJ=E:i)J
c
,
0
RR dst
lQ] l),
lIiJ=E:i)J
c
,
SBC dst,src
dst - dst - src - C
11
R
lR
CO
Cl
(Note 1)
30
SCF
------***--
R
lR
rE
r=O-F
20
21
RR
IR
AO
Al
-***--
BF
* * * * * *
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR(7) - 1
DA
if cc is true
PC - dst
IRR
JR cc,dst
RA
if cc is true,
PC - PC + dst
Range: + 127, -128
8085-00~
OR dst,src
lQ]~~
SRP src
1m
1m
r
R
R
r
X
r
lr
R
R
R
IR
IR
X
r
lr
r
R
IR
1m
1m
R
SUB dst,src
.. .
•
.. - W
f'!a
eI
• • 1
.
DF
1 - - -
DO
D1
• • • 0
31
------
20
R
IR
FO
F1
X • • X - -
TCM· dst,src
(NOT dst) AND src
(Note 1)
60
- • • 0
TM dst, src
(Note 1)
70
- • • 0
(Note 1)
Bo
@
dst AND src
cD
c=O-F
30
------
cB
c=O-F
------
rC
r8
r9
r=O-F
C7
------
• • 1
XOR dst,src
dst - dst XOR src
D7
E3
F3
E4
E5
E6
E7
F5
.
(Note 1)
dst - dst - src
SWAP dst
• 0 - -
Nole 1
These instructions have an identical set of addressing
modes, which ar~ encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in tho follOWing table to the
left of the applicable addreSSing mode pair.
For example, to determine the opcode of an ADC
instruction use the addreSSing modes r (destination) and
Ir (source). The result is 13.
Addr Modo
dst
src
R
R
R
IR
lr
R
1R
1M
1M
Lower
Opcode Nibble
[l]
r
lrr
lrr
C2
D2
------
lr
1rr
dst - src
r - r + 1; rr - rr + 1
lrr
lr
C3
D3
------
N
CO
m
....
RP - src
IRET
dst - src
------
RET
AD
9F
dst - dst + 1
LDCI dst,src
83
93
SRA dst
INC dst
LDC dst,src
lrr
lr
C-O
IMR (7) - 1
LD dst,src
dst - src
lr
lrr
dst - src
r - r + 1; rr - rr + 1
LDEI dst,src
C-1
EI
JP cc,dst
------
0
'*
dst - dst +
82
92
RRC dst
r - r- 1
if r
0
PC - PC + dst
Range: + 127, -128
INCW dst
lrr
dst - src
PC - @ SP; SP - SP + 2
DI
IMR (7) - 0
DJNZ r,dst
r
lrr
LDE dst,src
PUSH src
SP - SP-l; @SP - src
R
IR
COM dst
src
dst - dst OR src
C - NOT C
dst - 0
Opcodo Flags Affected
Byte
(Hex) CZSVDH
dst
NOP
CALL dst
CLR dst
Addr Modo
Instruction
and Operation
@]
[i]
lID
lID
[1]
495
Registers
R240SI0
R244 TO
Counter/Timer 0 Register
(F4H; ReadlWrite)
Serial 110 Register
(FOH; ReadlWrite)
I 0,\ 0.\ 0,\ 0.\ 0 O 0, \Do I
3\
2 \
'------SERIAL DATA (Do = LSB)
R241 TMR
Timer Mode Register
(FIH; ReadlWrite)
=
NOT TOUT
USEDMODES
00
~~ g~~
:
~~
INTERNAL CLOCK OUT = 11
T MODES
EXTERNAL CLOCK INP'OT
00
GATE INPUT
01
(NON.R~~~~g~~~~:~i) 10
TRIGGER INPUT = 11
(RETRIGGERABLE)
j
~
To INITIAL VALUE (WHEN WRITTEN)
'------(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
R245 PREO
Prescaler 0 Register
(F5H; Write Only)
llli~o =
l
FUNCTION
1 = NO
LOAD
To
.
0 = DISABLE To COUNT
1 = ENABLE To COUNT
0
NO FUNCTION
1
LOAD T,
0
DISABLE T, COUNT
1
ENABLE T, COUNT
=
=
=
=
=
=
=
R242 Tl
Counter Timer 1 Register
(F2H ; ReadlWrite)
COUNTMODE
o = To SINGLE·PASS
1 = To MODULO·N
RESERVED
PRESCALER MODULO
'-------(RANGE: 1-64 DECIMAL
01-00 HEX)
R246 P2M
Port 2 Mode Rogister
(F6H ; Write Only)
I 0,\ 0.\ 0,\ 0.\ 0 O 0, \Do I
3\
P2o-P2, 110 DEFINITION
L-_ _ _ _ 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
T, INITIAL VALUE (WHEN WRITTEN)
L-----(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VAlliE (WHEN READ)
R243 PREI
Prescaler.l Register
(F3H; Write Only)
[
2 \
R247 P3M
Port 3 Modo Register
(F7H ; Write Only)
~~
C~~NJ,
~~DGELE.PASS
=
1
T, MDDULO·N
CLOCK SOURCE
1 = T, INTERNAL
o T, EXTERNAL TIMING INPUT
(T'N) MODE·
=
PRESCALER MODULO
'-------(RANGE: 1-64 DECIMAL
01-00 HEX)
496
RESERVED
o P32 = INPUT
1 P32 = MVO/RDYO
P35
P3S
= OUTPUT
= INPUT
= INPUT
= DAVl/RDYl
P34
= OUTPUT
= IlM
= RDYl/DAVl
00 P33
~ ~} P33
1 1 P33
'--------~ ~~~ : ~J!Jfo'~~
'--------- ~ ~~g : ~N~~IL IN
'--________
Figure13. Control
O1 PORT
2 PULL·UPS OPEN DRAIN
PORT 2 PULL·UPS ACTIVE
P34
P34
= RDYO/DAVli
~;: ~ ~~~~~~~2UT)
~~~ ~ ~~~~~TOUT
~ ~!=:~~ g~F
Regist~rs
2037-014
Registers
(Continued)
R248 POIM
Port 0 and I Mode Rogistor
R252 FLAGS
Flag Rogistor
(F8H; Write Only)
(FCH; Read/Write)
I0,1 0.1 0.1 0.1 0 1021 0, IDo I
3
PO.-PO, =M
OUTPUT
00O D
. E:]
INPUT
01
A'2-A"
lX
EXTERNAL MEMORY TIMING
NORMAL .. 0
EXTENDED
1
=
~-r
L
~~~
LUSERFLAGF1
O
3
PO00
-P0
MODE
= OUTPUT
01
INPUT
lX
A.-A"
STACK SELECTION
0 = EXTERNAL
1
INTERNAL
LUSER FLAG F2
=
=
=
=
=
Pl o-Pl, MODE
00
BYTE OUTPUT
01
BYTE INPUT
10 = ADo-AD,
11 .. HIGH·IMPEDANCE ADo-AD,.
AS. OS. RtW. As-A". A'2-A15
IF SELECTED
=
=
R253 RP
Register Pointer
(F9H; Write Only)
(FDH; ReadlWrite)
I~I~I~I~I~I~I~I~I
I
:J
RESERVED
T 1
IRQ1, IRQ4 PRIORITY (GROUP C)
o IRQ1 > IRQ4
1 = IRQ4 > IRQ1
=
I
INTERRUPT GROUP PRIORITY
RESERVED = 000
C > A > B
001
A > B> C
010
A > C > B
011
B > C > A
100
C> B > A = 101
B > A > C = 110
RESERV~D
111
=
=
IRQO. IRQ2 PRIORITY (GROUP B)
o = IRQ2 > IRQO _ _ _ _ _- J
1 = IRQO > IRQ2
=
=
=
=
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
I..------..:.---CARRY FLAG
R2491PR
Interrupt Priority Roglster
IRQ3. IRQS PRIORITY (GROUP A)
o IRQS > IRQ3
1
IRQ3 > IRQS
HALF CARRY FLAG
REGISTER
POINTER
0,1 0.1 0.1 0.1 0 1021 0, I Do I
3
{:~gJJ
C=DON'T CARE
=
---------1
R250 IRQ
Intorrupt Request Reglstor
R254 SPH
Stack Pointor
(FAH; ReadlWrite)
(FEH; ReadIWrite)
I0,1 0.1 0.1 0.1 0 1021 0, IDo I
3
RESERVED
==r-
c=
IRQO
IRQ1
IRQ2
IRQ3
IRQ4
IRQS
..
..
..
..
P32 INPUT (Do .. IRQO)
P33 INPUT
P3, INPUT
P30 INPUT. SERIAL INPUT
To. SERIAL OUTPUT
= T,
R2511MR
Interrupt Mask Register
R255 SPt
Stack Pointer
(FBH; ReadlWrite)
(FFH; ReadIWrite)
I0,1 0.1 0.1 0.1 0 1021 0, IDo I
3
I.
c=
I
1..-------
I 0,1 De I0.1 0.1 0 10 210, IDo I
3
1 ENABLES IRQO-IRQS
(Do = IRQO)
RESERVED
1 - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 13. Control Registers
497
Z8601
Opcode
Lower Nibble (Hex)
Map
o
o
2
3
"
5
-;c
6
GI
!S
:a
7
.
GI
Po
Po
8
~
9
A
B
C
D
E
F
5
6
7
8
9
A
B
C
D
E
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
DEC
ADD
ADD
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
Il,Rz
12,Rl
II,RA
cc,RA
Il,IM
cc,DA
II
Rl
IRI
II, IZ
II, lIZ
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
Rl
IRl
II, IZ
Il,IIZ
Rz,Rl
IRz,Rl
RI,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
Rl
IRI
n,IZ
II,IIZ
Rz,Rl
IR2,Rl
RI,IM
IRl,IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
IP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRRI
1M'
II, IZ
II, lIZ
R2,Rl
IR2,Rl
RI,IM
IRI,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
Rl
IRl
II, 12
II, lIZ
R2,RI
IRZ,Rl
Rl,IM
IRl,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
Rl
IRI
n,IZ
II, lIZ
R2,Rl
IRZ,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
RI
IRl
n,IZ
II,Il2
Rz,Rl
IRz,Rl
Rl,IM
IRI,IM
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
Rz
IR2
II, 12
Il,Il2
R2,RI
IRz,RI
Rl,IM
IRI,IM
10,5
10,5
12,0
18,0
LDE
LDEI
DECW DECW
RRI
IRI
II,III2
In,lrl2
6,5
6,5
12,0
18,0
LDE
LDEI
RL
RL
Rl
IRI
10,'5
10,5
6,5
I----
I----
I----
EI
10,5
6,5
10,5
10,5
CP
CP
CP
CP
CP
Rz,RI
IRz,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
Rl
IRI
II, rz
Il,Irz
Rz,Rl
IRZ,Rl
Rl,IM
IRl,IM
6,5
10,5
10,5
10,5
6,5
6,5
12,0
18,0
10,5
RRC
LDC
LDCI
LD
Rl
IRl
6,5
6,5
12,0
18,0
20,0
20,0
10,5
SRA
LDC
LDCI
CALL·
CALL
LD
DA
IZ, x, Rl
10,5
10,5
Iz,IIIl Irz, lIn
6,5
JRRI
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
Rl
IRI
II, Irz
Rz,Rl
IRz,Rl
Rl,IM
IRl,IM
8,5
8.5
6,5
IRI
V'
2
-
LD
LD
R2,IRl
"
"-
V"
3
- 6,5
-
SCF
6,5
CCF
!t
..I
16,0
IRET
6,5
10,5
Ill, r2
RET
RCF
II, x, Rz
SRA
SWAP SWAP
-
10,5
RRC
n,Irlz IIl,IIl2
- 14,0
10,5
II,Irz
\..
f---
6,1
CP
IRl
f---
DI
n,IZ
6,5
f---
I----
IRI
Rl
f---
6,1
RRI
6,5
F
~
Iz,IIII IIz,IIIl
INCW INCW
Rl
Bytes per
Instruction
"
3
DEC
10/12,1 12/14,1
GI
:9
:z;
2
,
,
~
t--6,0
NOP
\..
~--------~~~----------,# ~ ~
2
3
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode
Nibble
~A
First
Operand
t
Pipeline
Cycles
Mnemonic
Second
Operand
Legend:
R = 8-Bit Address
r = 4-Blt Address
HI or rl = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
*2-byte instruction; fetch cycle appears as a 3-byte instruction
498
8085-002
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 1·50 °C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
o +4.75 V ~ Vee ~ +5.25 V
o GND = 0 V
o O°C =:;; TA =:;; +70°C*
+5V
'See Ordering Information section for package
temperature range and product number.
+5V
2.1K
+5V
+5V
18K
Uk
74 LS04
1.Sk
74 LS04
CLI~CK --i.><>--..--D>O---.-.----1,~-
t
XTAL2
I
CL = 15pF MAX
' - - - - - - - - . - - XTAL1
1
I
I
CL = 15pF MAX
Figure 14. Test Load I
Figure 15. Test Load 2
Figure 16. TTL External Clock Interface Circuit
(Both the clock and Its complement are required)
DC
Characteristics
Parameter
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
Symbol
,VIH
Input High Voltage
2.0
Vee
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
, VOH
8085-0313, 0312
Output High Voltage
Condition
V
IoH
= -250 /LA
0.4
V
IoL
=
2.4
rnA
VOL
Output Low Voltage
IlL
Input Leakage
-10
10
/LA
o V::5
VIN S +5.25 V
IoL
Output Leakage
-10
10
/LA
o V::5
VIN S +5.25 V
IIR
Reset Input Current
-50
/LA
Vee'
lec
Vee Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
3
Vee
V
+2.0
=
+5.25 V, VRL
=0V
Power Down Mode
Power Down
499
· External I/O
or Memory
Read and
Write Timing
RlW
PORT 0,
DM
PORT 1
As
os
(READ)
PORT 1
Afl-AT
58
(WRITE)
Figure 17. External I/O or Memory Read/Write
Z8601/3
No.
Parameter
1
TdA(AS)
Address Valid to AS t Delay
50
35
2
TdAS(A)
AS t to Address Float Delay
70
45
TdAS(DR)
AS t to Read Data Required Valid
TwAS
TdAz(DS)
AS Low Width
3
4
, 5
Min
Max
Z8601-12
Symbol
Min
360
Max
Notes*t
1,2,3
1,2,3
220
1,2,3,4
80
55
1,2,3·
Address Float to DS I
0
0
6-TwDSR
DS (Read) Low Width
250
185
1
·1,2,3,4
7
DS (Write) Low Width
160
8
9
10
11
12 13
14
15
TwDSW
TdDSR(DR)
ThDR(DS)
DS I to Read Data Required Valid
Read Data to DS t Hold Time
TdDS(A)
DS t to Address Active Delay
TdDS(AS)
DS t to AS I Delay
TdRIW(AS) - - R/W Valid to AS t Delay
TdDS(R/W)
DS I to RlW Not Valid
TdDW(DSW)
Write Data Valid to DS (Write) I Delay
TdDS(DW)
DS t to Write Data Not Valid Delay
16
TdA(DR)
Address Valid to Read Data Required Valid
17
TdAS(DS)
AS t to DS I Delay
NOTES:
1. Test Load 1
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.
4. When using extended memory timing add 2 TpC.
500
1,2,3,4
110
200
130
0
0
70
45
1,2,3,4
1,2,3
70
55
1,2,3
50
30
60
35
1,2,3
1,2,3
50
35
1,2,3
70
45
410
80
1,2,3
255
55
1,2,3,4
1,2,3
5. All timing references use 2.0 V for a logic "1" and 0.8 V for a logic "0".
* All units in nanoseconds (ns).
t Timings are preliminary and subject to change.
2194-011
Additional
Timing
Table
Figure 18. Additional Timing
No.
Symbol
Parameter
Z860l!3
Min
Max
125
1
TpC
Input Clock Period
2
TrC/TfC
Clock Input Rise And Fall Times
3
TwC
Input Clock Width
4
TwTinL
5-TwTinH
1000
Z8601-12
Min
Max
83
Notes*t
1000
25
15
lSI
37
26
Timer Input Low Width
100
70
3TpC
3TpC
2
8TpC
8TpC
2
00
!...
2
-
6
TpTin
Timer Input High Width
Timer Input p'eriod
7
TrTin, TfTin
Timer Input Rise And Fall Times
8a
TwIL
Interrupt Request Input Low Time
100
70
8b
TwIL
Interrupt Request Input Low Time
3TpC
3TpC
2/3
2,4
9
TwIH
Interrupt Request Input High Time
3TpC
3TpC
2/3
100
W
:I
2
100
NOTES:
3. Interrupt request via Port 3 (P31-P33)'
4. Interrupt request via Port 3 (P30)'
• Units in nanoseconds (ns).
i Timings are preliminary and subject to change.
1. Clock timing references uses 3.8 V for a logic" 1" and 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "1" and 0,8 V for
a logic "0".
Z8603
Memory Port
Timing
Ao-A10
Do-D7
~_______________________________________A_D_D_RE_S_S_VA_L_ID________________________________________~t<
----..J_r.-.
_CD----Jj
_
~
DON'T CARE
T~~
~
DATA IN VALID
Figure 19. Memory Port Timing
Parameter
No.
Symbol
TdA(DI)
Address Valid to Data Input Delay
2
ThDI(A)
Data In Hold Time
Min
Z8601
Max
Min
460
a
Z8601
Max
Notes*
320
1/2
a
NOTES:
1. Test Load 2
2. This is a Clock-Cycle-Dependent parameter. For clock frequencies other than the maximum, use the following formula:
28601/3 = 5 TpC - 165
'
28601/3-12 = 5 TpC - 95
2194-012
2037-019
• Units are nanoseconds unless otherwise speCified; timings are
preliminary and subject to change.
501
"
c:I
Handshake
Timing
DATA IN
DAY
(INPUT)
ROY
(OUTPUTI
Figure 20a. Input Handshake
x---
DATA OUT
DATA OUT VALID
-~-----
)f-----(~®>-----I-~-E1!=
DAY
(OUTPUTI
ROY
(INPUTI
Figure 20b. Output Handshake
No.
Symbol
Parameter
1
TsDI(DAV)
Data In Setup Time
2
ThDI(DAV)
Data In Hold Time
Z8601/3
Min
Max
Z8601!3-12
Min
Max
0
230
160
0
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY) DAV I Input to RDY I Delay
5-TdDAVOf(RDY)-DAV I Output to RDY I D e l a y - - - - - - - - - 0
6
TdDAVIr(RDY) DAV 1 Input to RDY 1 Delay
7
TdDAVOrRDY)
DAV 1 Output to RDY 1 Delay
8
9
TdDO(DAV)
TdRDY(DAV)
Data Out to DAV I Delay
Rdy I Input to DAV 1 Delay
NOTES:
I. Test load I
2 .. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for
a logic "0".
ClockNumber
Cycle-TimeDependent
Characteristics
2
3
4
6
7
8
10
11
12
13
14
15
16
17
120
175
175
120
1,2
0 ------1,3
1,2
120
0
0
50
30
0
200
0
1,3
1
140
• Units in nanoseconds (ns).
t Timings are preliminary and subject to change.
Z8601!3
Equation
Z8601!3-12
Equation
TdA(AS)
TpC-75
TpC-50
TdAS(A)
TdAS(DR)
TpC-55
4TpC-140*
TpC-40
4TpC-llO*
TwAS
TwDSR
TpC-45
3TpC-125*
TpC-30
3TpC-65*
TwDSW
TdDSR(DR)
Td(DS)A
2TpC-90*
2TpC-55*
3TpC-175*
3TpC-120*
TpC-55
TpC-40
Symbol
Notes*t
TdDS(AS)
TpC-55
TpC-30
TdRlW(AS)
TpC-75
TpC-55
TdDS(RIW)
TpC-65
TpC-50
TdDW(DSW)
TdDS(DW)
TpC-75
TpC-50
TdA(DR)
TpC-55
5TpC-215*
TpC-40
5TpC-160*
TdAS(DS)
TpC-45
TpC-30
• Add 2TpC when using extended memory timing
502
2194·013
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Speed
Temp
Description
28601
CE
8.0 MHz
28MCU
(2K ROM, 40-pin)
28601-12
PE
12.0 MHz
28MCU
(2K ROM, 40-pin)
28601
CS
8.0 MHz
Same as above
28601-12
PS
12.0 MHz
Same as above
28603
RS
8.0 MHz
28603-12
RS
12.0 MHz
28601
PE
8.0 MHz
Same as above
28601
PS
8.0 MHz
Same as above
28601-12
CE
12.0 MHz
ZSMCU
(2K ROM,40-pin)
28601-12
CS
12.0 MHz
Same as above
NOTES: C = Ceramic, P = Plastic, R
= Protopack; E =
ZSMCU
(2K XROM,
Prototyping Device,
40-pin)
Same as above
40° to 85°C, S = O°C to +70°C.
II
!...
W
•n
c:I
503
Z8® Family of
Microcomputers
Z8611 CD Z8612 • Z8613
I
Product
Specification
Zilog
September 1983
28611 Single-Chip Microcomputer with 4K ROM
28612 Development Device with Memory Interface
28613 Prototyping Device with EPROM Interface
Features
II
Complete microcomputer, 4K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
60K bytes addressable external space each
for program and data memory.
III
144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.
rI
Average instruction execution time of
1.5 fJ-S, maximum of 3 fJ-S.
a Vectored, priority interrupts for I/O,
counter/timers, and UART.
General
Description
The Z8611 microcomputer introduces a new
level of sophistication to single-chip architecture. Compared to earlier single-chip microcomputers, the Z8611 offers faster execution;
more efficient use of memory; more sophisti-'
cated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8611 can be
tailored to the needs of its user. It can be con-
II
Full-duplex UART and two programmable
8-bit counter/tirpers, each with a 6-bit
programmable prescaler.
a Register Pointer so that short, fast instructions can access any of nine workingregister groups in 1 fJ-S.
IJ
On-chip oscillator which accepts crystal or
external clock drive.
Ii1
Low-power standby option that retains contents of general-purpose registers.
Ii
Single + 5 V power supply-all pins TTLcompatible.
figured as a stand-alone microcomputer with
4K bytes of internal ROM, a traditional microprocessor that manages up to 120K bytes of
external memory, or a parallel-processing element in a system with other processors and
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.
+5V
PORTO
(NIBBLE
PROGRAMMABLE)
1/0 OR As-A"
PORT 2
(BYTE
PROGRAMMABLE)
1/0 OR ADD-AD,
P2 7
P3,
P2.
P3,
P2.
REID
P2.
R/W
P23
os
1/0
AS
P2.
P2,
P3.
P2,
GND
P3 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL 1/0
AND CONTROL
Figure 1. Z8BU MCU Pin Functions
2038·001, 002
P3,
XTALl
(BIT PRO·
GRAMMABLE)
PORT 3
PORT 1
P3.
XTAL2
P3.
P3.
po,
po,
po.
Pl,
Pl.
Pl.
P0 3
Pl.
po.
po.
po.
po,
P1 3
Pl.
Pl,
Pl 0
Figure 2. Z8BU MCU Pin Assignments
505
Architecture
28611 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O capabilities. The 28611 fulfills this with
32 pins dedicated to input and output. These
lines are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status signals, serial or
parallel I/O with or without handshake, and an
address/data bus for interfacing external
memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the 28611
can assume many different memory and I/O
configurations. These configurations range
from a self-contained microcomputer to a
OUTPUT
Vee
microprocessor that can address 120K bytes of
external memory (Figure 3).
Three basic address spaces are available to
support this wide range of configurations: program memory (internal and external), data
memory (external) and the register file (internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers.
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized
because qne of the on-chip timers supplies the
bit rate.
'GND
!!
FLAGS
REG. POINTER
I/O
(BIT PROGRAMMABLE)
ADDRESS OR 110
(NIBBLE PROGRAMMABLE)
ADDRESSIDATA OR 110
(BYTE PROGRAMMABLE)
Figure 3. Functional Block Diagram
Pin
Description
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid 'at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, active Low). Data
Strobe is ~ctivated once for each external
memory transfer.
POO-P01' P1o-P11. P20-P21' P30-P31. I/O Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports
that can be configured under program control
506
for I/O or external memory interface.
RESET. Reset (input, active Low). RESET initializes the 28611. When RESET is deactivated,
program execution begins from internal program location,OOOCH.
R/W. Read/Write (output). R/W is Low when
the 28611 is writing to external pr'ogram or
data memory.
XTALI. XTAL2. Crystall, Crystal 2 (time-base
input and output). These pins connect a
parallel-resonant crystal (8 or 12 MHz maximum) or an externalsingle-phase clock (8 or
12 MHz maximum) to the on-chip clock
oscillator and buffer.
2037-003
Address
Spaces
Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 4096 bytes
consist of on-chip mask-programmed ROM. At
addresses 4096 and greater, the Z8611
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The Z8611 can address 60K
bytes of external data memory beginning at
5535
location 4096 (Figure 5). External data memory
may be included with or sepa.rated from the
external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used
to distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-RI27) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure .6.
Z8611 instructions can access registers
65535
_---------""1
EXTERNAL
ROM OR RAM
4096
4095
ON·CHIP
ROM
Location 0 I
first byte 0 I
Instruction
!~ ~------------
executed
efterrese
Interrup I
Vecta
(Lower Byte
;
11
IR05
10
IR05
9
IR04
8
IR04
7
IR03
6
IR03
5"'-
IR02
4j..Interrup I
Vectc r
(Upper Byte)
EXTERNAL
DATA
MEMORY
IR02
3
IROI
2
IROI
1
IROO
0
IROO
:~~~ ~----------I
NOT ADDRESSABLE
Figure 5. Data 'Memory Map
Figure ,4. Program Memory Map
LOCATION
255
254
253
IDENTIFIERS
STACK POINTER (BITS 7-0)
SPL
STACK POINTER (BITS 15-8)
SPH
REGISTER POINTER
RP
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
249
INTERRUPT REQUEST REGISTER
IRQ
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
252
~
1--~"':-;;"""';_..L..-_ _ _ _-I253
1----------..1240
The upper nibble of the register file address
provided by the register poinler specifies
the active working·reglster group.
127
POIM
PORT 3 MODE
P3M
248
PORT 2 MODE
P2M
245
TO PRESCALER
PREO
244
TIMER/COUNTER 0
243
Tl PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
240
SERIAL I/O
SIO
247
r-_~---;-;:{~----.255
TO
PREI
T1
The lower
nibble of
the register
NOT
IMPLEMENTED
SPECIFIED WORKING,
REGISTER GROUP
127
til. address
by
'-1- provided
the Instruction
pOints to the
specified
register.
GENERAL·PURPOSE
REGISTERS
1
PORT 3
P2
PORT 1
PI
PORT 0
PO
Figure 6. The Register File
2038·004, 005 2037·006. 007
P3
PORT 2
1--------------3
110 PORTS
Figure 7. The
Regist~r
Pointer
507
Address
Spaces
(Continued)
directly or indirectly with an 8-bit address
field. The Z8611 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
4096 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-RI27).
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asyn~
chronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second for 8
MHz and 94.8K bits/second for 12 MHz.
The Z8611 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity is also available as an option. Eight
data bits are always transmitted, regardless of
parity selection. If parity is enabled, the eighth
bit'is the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.
Transmitted Data
(No Parity)
Received Data
(No Parity)
ISP I0, I 0.1 0 10.1 0 10,1 0, I Do I ST I
5
3
LSTART BIT
LSTART BIT
I
' - - - - - - E I G H T DATA BITS
TWO STOP BITS
L . . - - - - - E I G H T DATA BITS
L . . - - - - - - - - - O N E STOP BIT
Received Data
(With Parity)
Transmitted Data
(With Parity)
ISP I SP 1P I 0.1 0 10.1 0 10,1 0, 1Do 1sTI
5
TL
IDlpl~I~I~I~I~I~I~I~1
3
_LsTARTBIT
' - - - - - - S E V E N DATA BITS
II
LSTART BIT
'-_ _ _ _ _-'--_ _ SEVEN DATA BITS
PARITY ERROR FLAG
ODD PARITY
TWO STOP BITS
' - - - - - - - - - - O N E STOP BIT
Figure 8. Serial Data Formats
Counter/
Timers
508
The Z8611 contains two 8-bit programmable
counter/timers (To and TIL each driven by its
own 6-bit programmable prescaler. The TI
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each prescaler drives its counter,
which decrements the value (1 to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (TI)is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (singlepass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for TI is user-definable and
can be the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and a
6 MHz maximum fd'r the 12 MHz device.)
divided by four, or an external signal input via
Port 3. The Timer Mode register configures the
external timer input as an external clock
(1 MHz maximum), a trigger input that can be
retriggerable or non-retriggerable, or as a gate input for the internal clock. The
counter/timers can be programmably cascaded
by connecting the To output to the input of TI.
Port 3 lineP36 also serves as a timer output
(TOUT) through which To, TI or the internal
clock can be output.
2047-009
I/O Ports
The 28611 has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to
provide address outputs, timing, status signals,
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 1 can be programmed as a byte I/O
port or as an address/data port for interfacing
external memory. When used as an I/O port,
Port 1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY 1
and DAVl (Ready and Data Available).
Memory locations greater than 4096 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port a must output the additional lines.,
Port 1 can be placed in the high-impedance
state along with Port 0, AS, DS and R/W,
allowing the 28611 to share common resources
in multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33 as
a Bus Acknowledge input, and P34 as a Bus
Request output.
Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port a may be placed under handshake control. In this configuration, Port 3 lines P32 and
P3s are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the I/O direction of the upper
nibble P04 - P07. '
For external memory references, Port a can
provide address bits Aa-All (lower nibble) or
As-AlS (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port a can be programmed independently as
I/O while the lower nibble is used for addressing. When Port a nibbles are defined as
address bits, they can.be set to the highimpedance state along with Port 1 and the control signals AS, DS and R/W.
Port 2 bits can be programmed independently as input or output. This port is
always available for I/O operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Ports a and I, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P3l and P36 are used as
the handshake controls lines DAV2and RDY2.
The handshake signal assignment for Port 3
lines P3l and P36 is dictated by the direction
(input or output) assigned to bit 7 of Port 2.
Port 3 lines can be configured as I/O or controllines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
. four output (P34-P37)' For serial I/O, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the follOWing control
functions: handshake for Ports a, 1 and 2
(DAV and RDY); four external interrupt
request signals (IRQO-IRQ3); timer input and
output signals (TIN and TOUT) and Data
Memory Select (DM).
2037-008
PORT 1
(1/0 OR ADo-AD,)
HANDSHAKE CONTROLS
} DAV, AND RDY,
(P33 AND P3.)
a
......
-......
w
eft
Figure 9a. Port 1
PORT 0
} (1/0 OR As-A,.>
_
} HANDSHAKE CONTROLS
DAVo AND RDYo
(P3. AND P3S>
Figure 9b. Port 0
PORT 2(1/0)
HANDSHAKE CONTROLS
} DAV. AND RDY2
(P3, AN D P3 s)
Figure 9c. Port 2
PORT 3
(1/0 OR CONTROL)
Figure 9d. Port 3
509
N
I
Interrupts
Clock
Power Down
Standby
Option
The ·Z8611 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counterl
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
. All Z8611 interrupts are vectored. When an
interrupt request is granted, an interrupt
. machine cycle is entered. This disables all
subsequent interrU:pts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
'interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service .
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALI = Input, XTAL2 = Output).
The crystal source is connected across
XTALI and XTAL2, using the recommended
capacitors (Cl ~ 15 pF) from each pin to
ground. The specifications for the crystal are
as follows:
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input. This
necessitates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. Figure 10 shows
the recommended circuit for a battery back-up
supply system.
This 64-pin development version of the
Z8612
Development 40-pin mask-programmed Z8611 (Figure 11)
allows the user to prototype the system in hardDevice
ware with an actual device and to develop the
code that is eventually mask-programmed into
the on-chip ROM of the Z861l.
The Z8612 is identical to the Z8611 with the
. following exceptions:
• The internal ROM has been removed.
II The ROM address. lines and data lines are
buffered and brought out to external pins.
• Control lines for the new memory have
been added.
Pin Description. The functions of· the Z8612
1/0 lines, AS, DS-, R/W, XTALl, XTAL2 and
RESET are identical to those of their Z8611
counterparts. The functions of the remaining
24 pins are as follows:
Ao-Au. Program Memory Address (outputs).
Ao-All access the first 4K bytes of program
memory.
• AT cut, parallel resonant
.. Fundamental type, 8/12 MHz maximum
II Series resistance, Rs ~ 100 n
+5 V O----~~-__1 Voo
Z8611
J
Figure 10. Recommended Driver Circuit
for Power Down Operation
P2s
Vee
P31
XTAL2
P27
XTALl
P2s
P37
P2s
P30
P24
R~$ET
P23
P22
RIW
OS
P21
AS
P20
P3s
P33
P33
P34
poo
P17
POl
PIs
P02
PIs
P03
P14
P04
P13
GND
P12
POs
P11
POs
P10
P07
07
lACK
Ds
SYNC
Ds
SCLK
04
MOS
Ao
Do
Al
01
A2
D2
A3
D3
A4
All
As
Al0
As
As
A7
As
Figure 11. Z8612 Pin Assignments
510
2038-010, 011
Z8612
Do-D,. Program Data (inputs). Program data
Development from the first 4K bytes of program memory is
Device
input through pins Do-D7.
(Continued)
lACK. Interrupt Acknowledge (output, active
High). lACK is driven High in response to an
interrupt during the interrupt machine cycle.
MOS. Program Memory Data Strobe (output,
active Low). MDS is Low during an instruction
fetch cycle when the first 4K bytes of program
memory are being accessed.
Z8613
Protopaclc
Emulator
The 28613 MPE (Protopack) is used for
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROMless version of the standard 28611,
housed in a pin-compatible 40-pin package
(Figure 12).
To provide pin compatibility and interchangeability with the standard maskprogrammed device, the Protopack carries
(piggy-back) a 24-pin socket for a direct interface to program memory (Figure 1). The
24-pin socket is equipped with 12 ROM
SCLK. System Clock (output). SCLK is the
internal clock output through a buffer. The
clock rate is equal to one-half the crystal
frequency.
SYNC. Instruction Sync (output, active Low).
This strobe output is forced Low during the
internal clock period preceding an opcode
fetch.
address lines, 8 ROM data lines and necessary
control lines for interface to 2732 EPROM for
the first 4K bytes of program memory.
Pin compatibility allows the user to
design the pc board for a final 40-pin maskprogrammed 28611, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot production units. When the
final program is established, the user can then
switch over to the 40-pin mask-programmed
28611 for large volume production. The Protopack is also useful in small volume applications where masked ROM setup time, mask
charges, etc., are prohibitive and program
flexibility is desired.
Compared to the conventional EPROM
versions of the Single-chip microcomputers,
the Protopack approach offers two main
advantages:
(J
Ease of developing various programs during
the prototyping stage: For instance, in
applications where the same hardware
configuration is used with more than one
program, the 28613 Protopack allows
economical program storage in separate
EPROMs (or PROMs), whereas the use of
separate EPROM-based Single-chip
microcomputers is more costly.
c
Elimination of long lead time in procuring
EPROM-based microcomputers.
Figure 12. Tho Z6613 Microcomputer Protopack Emulator
Instruction
Set
Notation
Addressing Modes. The follOWing notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
IR
Ir
RR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Symbols. The follOWing symbols are used in
describing the instruction set.
dst
src
cc
@
SP
PC
FLAGS
RP
IMR
Destination location or contents
Source location or contents
Condition code (see list)
Indirect address prefix
Stack pointer (control registers 254-255)
Program counter
Flag register (control register 252)
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol
\1-". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation \laddr(n}" is used
to refer to bit \In" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
511
Instruction
Set
Notation
(Continued)
Flags. Control Register R252 contains the following
six flags:
C
Z
S
V
H
*
X
Mnemonic
Value
Condition
Codes
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
Meaning
1011
0011
0000
Flags Set
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned. less than
Unsigned greater than
Unsigned less than or equal
Never true
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
aIII
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
1
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
D
Affected flags are indicated by:
o
Instruction
Formats
OPC
dst
C
1
C = a
Z =1
Z =0
S = a
S = 1
V = 1
V = a
Z = 1
Z = a
(S XOR V) = a
(S XOR V) = 1
[Z OR (S XOR V)]
[Z OR (S XOR V)]
a
1
C=O
C =1
(C = a AND Z
(C OR Z) = 1
= 0)
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
INCr
OPC
One-Byte Instructions
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
CLR, CPL, DA, DEC,
L-""::":'=_-' OR
I
OPC
t---"d'--'st"----I OR
h 1 1 01 dsllsrc 1 ~~~~'~~~Rt~~:R."OP,
RRC, SRA, SWAP
11 1 1 01
JP, CALL (Indirect)
dst
1-_"::::":'_--1 OR
111101
dst
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
OPC
VALUE
LD
LD, LDE, LDEI,
LDC, LDCI
LD
L..-....:.:..:=_.J. OR
dst 1 OPC
VALUE
I
dsllCCR~ OPC
11 1 1 01
JP
LD
CALL
DJNZ, JR
Two-Byte Instructions
512
LD
Three-Byte Instructions
2037-013
Instruction
Summary
Opcode Flags Affected
Byte
(Hox)
CZSVDH
Instruction
and Oporation
Addr Mode
ADC dst,src
dst - dst + src + C
(Note 1)
10
ADD dst,src
dst - dst + src
(Note 1)
00
AND dst,src
dst - dst AND src
(Note 1)
50
- * * 0
CALL dst
DA
IRR
SP - SP - 2
@SP - PC; PC - dst
D6
D4
------
CCF
C - NOT C
EF
* - - - - -
dst
src
Opcode Flags Affected
Byto
(Hex)
CZSVDH
dst
src
* 0 *
LDE dst,src
dst - src
r
Irr
Irr
82
92
------
* 0 *
LDEI dst,src
Ir
Irr
dst - src
r - r + 1; rr-rr+l
Irr
Ir
83
93
------
FF
------
OR dst,src
dst - dst OR src
(Note 1)
40
0--
POP dst
dst - @SP
SP - SP + 1
R
IR
50
51
NOP
------
CLR dst
dst - 0
R
IR
BO
Bl
------
PUSH src
SP - SP-l; @SP - src
COM dst
dst - NOT dst
R
IR
60
61
- * * 0
RCF
C-O
CF
o- - - - -
CP dst,src
dst - src
(Note 1)
RET
PC - @ SP; SP - SP + 2
AF
------
DA dst
dst - DA dst
R
IR
40
41
* * *
DEC dst
dst - dst - 1
R
IR
00
01
-***--
DECW dst
dst - dst - 1
RR
IR
80
81
-***--
DI
IMR (7) - 0
rA
r=O-F
*
x- -
-----------
------
rE
r=O-F
20
21
-***--
R
IR
RR
IR
AO
Al
-***--
IRET
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP +2; IMR(7) - 1
JP cc,dst
if cc is true
PC - dst
JR cc,dst
if cc is true,
PC - PC + dst
Range: + 127, -128
LD dst,src
dst - src
LDC dst,src
dst - src
DA
IRR
RA
1m
r
R
R
r
X
r
Ir
R
R
R
IR
IR
X
r
Ir
r
R
IR
1m
1m
R
r
Irr
Irr
LDCI dst,src
Ir
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Ir
70
71
a
~I~
.......
RLC dst
~, '~I~
10
11
N
RR dst
L[ri L{6)J I~
EO
El
RRC· dst
LE1=ciJ IRR
CO
Cl
c
,
SBC dst,src
dst - dst - src - C
,
(Note 1)
SCF
C-l
9F
INC dst
dst - dst + 1
R
IR
90
91
RL dst
SRA dst
EI
IMR (7) - 1
INCW dst
dst - dst +
AD
8F
DJNZ r,dst
RA
r - r- 1
if r
0
PC - PC + dst
Range: + 127, -128
ru ,rJ I~
~
1m
SRP src
RP - src
SUB dst,src
dst - dst - src
(Note 1)
G)
* * - -
* *
* * 1 *
DF
1 - - -
DO
Dl
* * * 0
31
20
* * 1 *
TCM dst,src
(NOT dst) AND src
(Note 1)
60
-
* * 0 - -
TM dst, src
dst AND src
(Note 1)
70
-
* * 0
(Note 1)
BO
-**0--
XOR dst,src
dst - dst XOR src
cB
c=O-F
------
Note 1
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
------
C2
D2
------
C3
D3
------
These instructions have an identical set of addressing
modes, which are encoded for brev:ity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a D in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction use the addressing modes r (destination) and
Ir (source). The result is 13.
AddrMode
dst
src
Lower
Opcode Nibble
[l)
R
R
R
Ir
R
rn
IR
lID
1M
1M
@]
W
~
~
3D
X * *X - -
------
Id
n
'Ii
FO
Fl
cD
c=O-F
30
-£WI
SWAPdstr@ R
IR
IR
8085-003
Addr Mode
Instruction
and Operation
[!l
(2)
513
Registers
R240 SIO
Serial I/O Register
R244 TO
Counter/Timer 0 Register
(FOH ; Read/Write)
(F4H; Read/Write)
' - - - - - - SERIAL DATA (Do
= LSB)
(FIH; Read/Write)
R245 PREO
Prescaler 0 Register
(F5H; Write Only)
I 0,1 0,1 Os I0,1 0 10,1 0, IDo I
I~I~I~I~I~I~I~I~I
R241 TMR
Timer Mode Register
=
NOT TOUT
USEDMODES
00
~: g~~ ~ ~~
=
11
INTERNAL CLOCK. OUT
T MODES
EXTERNAL CLOCK IN~~T
00
01
GATE INPUT
10
TRIGGER INPUT
(NON·RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
To INITIAL VALUE (WHEN WRITTEN)
'------(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
J
.-J
3
lS~O =
FUNCTION
1 = NO
LOAD
To
0 = DISABLE To COUNT
1
ENABLE To COUNT
0 = NO FUNCTION
1
LOAD T,
0
DISABLE T, COUNT
1
ENABLE T, COUNT
=
=
=
=
=
=
=
COUNT
MODE
o = To SINGLE·PASS
~L
1 = To MODULO·N
• RESERVED
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
(F2H; Read/Write)
R246 P2M
Port 2 Mode Register
(F6H; Write Only)
I 0,\ 0.\ Os \ 0.\ 0 0,\ 0, \Do I
I~I~I~I~I~I~I~I~I
R242 Tl
Counter Timer 1 Register
3\
P20 -P2,1I0 DEFINITION
' - - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
T, INITIAL VALUE (WHEN WRITTEN)
'------(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)
R243 PREI
Prescaler 1 Register
(F3H; Write Only)
R247 P3M
Port 3 Mode Register
(F7H ; Write Only)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
~
E~
COO~N;, ~~G~E'PA.SS
1 = T, MODULO·N
CLOCK SOURCE
1 = T, INTERNAL
o T, EXTERNAL TIMING INPUT
(T,N) MODE
O
PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
RESERVED
o P32
= INPUT
= DAVOfRDYO
o 0 P33 = INPUT
~~}P33 = INPUT
=
1 P32
P35 = OUTPUT
P35 = RDYOfDAVO
P34
= OUTPUT
P34 = Ii1II
1 1 P33 = DAVlfRDYl P34 = RDYlfDAV1
PRESCALER MODULO
L...------(RANGE: 1-64 DECIMAL
01-00 HEX)
'--------~ ~~1 ~ ~N:vUJ~b'~~ :~~ ~ ~~~~~UT)
L...-_ _ _ _ _ _ _
'--________
~ ~~~ ~ ~N:R~rL
IN
~~~ ~ ~~~~ULTOUT
~ ~~~:~~ g~F
Figure 14. Control Registers
514
2037-014
Registers
(Continued)
R248 POIM
Port 0 and 1 Mode Register
R252 FLAGS
Flag Rogister
(F8H; Write Only)
(FCH ; Read/Write)
I 0, I0,1 0 10.1 0 10 10, IDo I
5
MODE~.
.-J .
PO.-PO,
OUTPUT = 00
INPUT = 01
A'2-A'5 = lX
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1
,
~
~POO_P03MODE
L
.
3
2
~~~
LUSERFLAGFl
00 = OUTPUT
01
INPUT
lX = A.-An
LUSER FLAG F2
=
STACK SELECTION
o = EXTERNAL
1 = INTERNAL
Pl o-Pl, MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD,
11 = HIGH-IMPEDANCE ADo-AD"
As, OS, Rm, AS-All. A12-A15
IF SELECTED
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
I - . - - - - - - - C A R R Y FLAG
R249IPR
Interrupt Priority Register
R253 RP
Register Pointer
(F9H; Write Only)
(FDH ; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED
I
=oJ
IR03, IROS PRIORITY (GROUP A)
o = IROS > IR03
1 = IR03 > IROS
IROO, IR02 PRIORITY (GROUP B)
o = IR02 > IROO _ _ _ _ _--1
1 = IROO > IR02
INTERRUPT GROUP PRIORITY
RESERVED = 000
C > A > B = 001
A> B > C = 010
A> C > B = 011
B > C > A = 100
C> B > A = 101
B > A > C = 110
RESERVED = 111
C=DON'T CARE
REGISTER
POINTER
IR01, IR04 PRIORITY (GROUP C)
o = IROl > IR04 - - - - - - - - '
1 = IR04 > IROl
R250 IRQ
Interrupt Request Register
.
R254 SPH
Stack Pointer
(FAH ; Read/Write)
(FEH; Read/Write)
1~1~1~1~1~1~1~1~1
RESERVED
~
c=
I~I~I~I~I~I~I~I~I
IROO
IROl
IR02
IR03
IR04
IROS
P32 INPUT (Do = IROO)
P331NPUT
P3, INPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
Tl
R2511MR
Interrupt Mask Register
R255 SPL
Stack Pointer
(FBH; Read/Write)
(FFH ; Read/Write)
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
c=
1 ENABLES IROO-IROS
(Do = IROO)
1-._ _ _ _ _ _ _ RESERVED
:
I
L I_ _ _ _
~~~~~S~~~~~~R
LOWER
' - - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 14. Control Registers
515
Opcode
Lower Nibble (Hex)
Map
o
6,5
o
2
5
)(
6
CD
=.
:Q
:9
7
.
z
CD
0.
0.
8·
0
9
A
C
D
E
F
6
7
8
9
A
B
C
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
12110,5
12/10,0
6,5
12/10,0
6,5
LD
LD
DJNZ
JR
LD
JP
INC
Il,R2
12,Rl
fl,RA
cc,RA
Il,lM
cc,DA
II
IRI
II, I2
Il,II2
R2,Rl
IR2,Rl
Rl,lM
IRl,lM
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
R2,Rl -IRz,Rl
Rl
IRI
II, 12
II, Irz
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
Rl,lM
E
IRl,lM
IRl,lM
Rl
IRI
n, 12
II, lIZ
R2,Rl
IRz,Rl
Rl,lM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
SBC
IRRI
1M
II, IZ
II, lIZ
R2,Rl
IRz,Rl
Rl,lM
IRl,lM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
RI
IRI
II, IZ
II, lIZ
R:z,RI
IR:z,RI
RI,IM
IRI,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
Rl
IRI
II, IZ
II, lIZ
Rz,Rl
IRz,Rl
Rl,lM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
Rl
IRI
II, IZ
Il,Irz
Rz,Rl
IRz,Rl
Rl,lM
IRl,lM
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
Rz
IRz
II, IZ
Il,lIZ
Rz,Rl
IR2,Rl
Rl,lM
IR1,IM
10,5
10,5
12,0
18,0
LDE
LDEI
Il,lIIZ
II1,IIIZ
DECW DECW
RRI
IRI
6,5
6,5
12,0
18,0
RL
RL
LDE
LDEI
Rl
IRI
10,5
10,5
F
r---
r---
r---
r---
r---
r---
r---
I-6,1
DI
r--6,1
El
IZ, IIIl 1I2,IIIl
6,5
INCW INCW
IRI
6,5
10,5
10,5
10,5
CP
CP
CP
CP
CP
CP
II, 12
II, lIZ
R2,Rl
IRZ,Rl
Rl,lM
IRl,lM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
XOR
XOR
XOR
XOR
XOR
XOR
Rl
IRI
fl, IZ
n, lIZ
Rz,Rl
IRZ,Rl
Rl,lM
IR1,IM
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LDC
LDCI
LD
Rl
IRI
Il,lIIZ II1,IIIZ
6,5
6,5
12,0
18,0
SRA
I.DC
LDCI CALL·
'Rl
IRI
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RR
RR
tD
tD
tD
tD
LD
Rl
IRI
Il,II2
R2,Rl
IR2,Rl
Rl,lM
IR1,IM
8,5
8,5
6,5
SWAP SWAP
IRI
'-r'
20,0
20,0
10,5
CALL
LD
IRRI
DA
16,0
IRET
i---
6,5
12,
X,
-
LD
LD
Rz,IRl
"-
6,5
~
6,5
CCF
fW
'-r'
2
RCF
SCF
Rl
10,5
Ill, IZ
~
RET
,-
II, x, Rz
SRA
Iz,lIIl IIZ,lIIl
I-14,0
10,5
CLR
\,
D
ADC ADC ADC ADC ADC ADC
6,5
Rl
Bytes per
Instruction
5
Rl
RRI
B
4
DEC ADD ADD ADD ADD ADD ADD
10/12,1 12/14,1
CD
3
6,5
3
4
6;5
DEC
2
3
ttl
,
It
1
6,0
NOP
\,
'---------~~~----------~# ~ ~
2
3
Lower
Opcode
Nibble
Execution
Cycles
+
Pipeline
Cycles
Upper
Opcode~A
Mnemonic
Legend:
R = 8-Bit Address
r = 4-Bit Address
RI or rl = Dst Address'
R2 or r2 = Src Address
Nibble
First
Operand
S,econd
Operand
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
*2-byte instruction; fetch cycle appears as a 3-byte instruction
516
8085-002
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambi'ent
Temperature ........ See Ordering Information
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rdting only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
o +4.75 V
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
~ Vee ~
+5.25 V
o GND = a V
o O°C ~ TA ~ +70°C*
·See Ordering Information section for package
temperature range and product number.
+SV
+5V
+SV
+SV
18K
1.Sk
74LS04
CLOCK
1.Sk
74LS04
>O---.--t.:»-<~...-- XTAL2
!
IN
I
CL
= lSpF MAX
L . . . - - - - - t ' - - XTAL1
I
I
Figure 15. Test Load 1
CL
= lSpF MAX
(Both the clock and its complement are required)
DC
, Characteristics
Parameter
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vec
V
Driven by External Clock Generator
VCL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
V
VlL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vce
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL,
Output Low Voltage
IlL
Input Leakage
IOL
Output Leakage
IIR
Reset Input Current
-50
p,A
Icc
VCG Supply Current
180
rnA
IMM
VMM Supply Current.
10
rnA
VMM
Backup Supply Voltage
Symbol
V
IOH
= -250 p.A
0.4
V
IoL
=
-10
10
p,A
-10
10
2.4
3
o V::s;
p,A o V::s;
Vec
1. For AO-All' MDS, SYNC, SCLK and lACK on the Z8612 version, lOH
8085-0313, 0312
2037-015
Condition
V
Vcc
+2.0
Notes
rnA
VIN ::s; +5.25 V
VIN ::s; +5.25 V
=
+5.25 V, VRL
0')
N
w
Figure 17. TTL External Clock ~ llterface Circuit
Figure 16. Test Load 2
=
.........
-.-..
=0V
Power Down Mode
Power Down
= -100 p.A and lOL = 1.0 rnA.
517
I
External 110
or Memory
Read and
Write Timing
RlW
PORT 0,
DM
PORT 1
. 0l----.a~1
os
------------4---------~'~~--------~CDr---------~'z_----r_----
(READ)
PORT 1
Ao-A7
00-07 OUT
1~------4CDr-----~~1
os
(WRITE)
Figure 18. External I/O or Memory Read/Write
Z8611/2/3
No.
Min
Max
Z8611/2/3-12
Min
Symbol
Parameter
TdA(AS)
Address Valid to AS I Delay
50
35
2
TdAS(A)
AS I to Address Float Delay
70
45
3
TdAS(DR)
AS I to Read Data Required Valid
4
TwAS
AS Low Width
5
TdAz(DS)
Address Float to DSI
0
0
DS (Read) Low Width
250
185
160
110
6-TwDSR
Max
1,2,3
1,2,3
220
360
1,2,3,4
1,2,3
55
80
Notes*t
1,2,3,4
1,2,3,4
7
TwDSW
DS (Write) Low Width
8
TdDSR(DR)
DS I to Read Data Required Valid
9
ThDR(DS)
Read Data to DS I Hold Time
0
0
1
10
TdDS(A)
DS I to Address Active Delay
70
45
1,2,3
DS I to AS I Delay
200
130
1,2,3,4
11
TdDS(AS)
70
55
1,2,3
12 -
TdRlW(AS) - - ' R/W Valid to AS I Delay
50
30
1,2,3
13
TdDS(R/W)
DS I to R/W Not Valid
60
35
1,2,3
14
TdDW(DSW)
Write Data Valid to DS (Write) I Delay
35
1,2,3
15
TdDS(DW)
DS I to Write Data Not Valid Delay
50
70 .
16
TdA(DR)
Address Valid to Read Data Required Valid
17
TdAS(DS)
AS I to DS I Delay
NOTES:
1. Test Load 1
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.
4. When using extended memory timing add 2 TpC.
518
255
410
80
1,2,3
45
55
1,2,3,4
1,2,3
5. All timing references use 2.0 V for a logic "I" and 0.8 V for a logic "0".
• All units in nanoseconds (ns).
t Timings are preliminary and subject to change.
2194-011
Additional
Timing
Table
Figure 19. Additional Timing
Symbol
Parameter
Z8611/2/3
Min
Max
TpC
Input Clock Period
125
2
TrC,TfC
Clock Input Rise And Fall Times
3
TwC
Input Clock Width
Timer Input Low Width
No.
TwTinL
5-TwTinH
4
6
7
TpTin
TrTin, TfTin
Timer Input High Width
Timer Input Period
Timer Input Rise And Fall Times
TwIL
Interrupt Request Input Low Time
TwIL
9
TwIH
Interrupt Request Input Low Time
Interrupt Request Input High Time
NOTES:
1. Clock timing references uses 3.8 V for a logic "1" and 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "I" and 0.8 V for
a logic "0"
Timing
1000
15
37
26
1
70
3TpC
2
2
2
8TpC
100
3TpC
70
2
2,3
3TpC
2,4
3TpC
3TpC
2,3
100
100
8a
AO-A10
83
Notes*t
100
3TpC
8TpC
8b
Z8612. Z8613
Memory Port
1000
25
Z861112/3·12
Min
Max
3. Interrupt request via Port 3 (P31-P33)'
4. Interrupt request via Port 3 (P30)'
• Units in nanoseconds (ns).
t Timings are preliminary and subject to change.
~
t(
ADDRESS VALID
T-_=.~-_==-_==~-0=r=-_==--~~~-------------------~T~1~
__-_
-_J_
,Xl;
DON'T CARE
~
DATA IN VALID
Figure 20. Memory Port Timing
No.
Symbol
Parameter
Address Valid to Data Input Delay
2
TdA(DI)
ThDI(A)
Data In Hold Time
NOTES:
1. Test Load 2
2. This is a Clock-Cycle-Dependent parameter. For clock frequencies other than the maximum, use the following formula:
28611/2/3 = 5 TpC - 165
28611/2/3-12 = 5 TpC - 95
2194-012 2037-019
Z861112/3
Min
Max
Z861112/3·12
Min
Max
460
o
320
Notes*
1,2
o
• Units are nanoseconds unless otherwise specified; timings are.
preliminary and subject to change.
519
II
en
.........
.-..
~
W
I
Handshake
Timing
DATA IN
DAY
(INPUT)
RDY
(OUTPUT)
Figure 21a. Input Handshake
r-
DATA OUT
~ATA OUT VALID
-~----
1~:-®>----~-Er=
DAY
(OUTPUT)
RDY
(INPUT)
Figure 21b. Output Handshake
Z8611/2/3
No.
Z8611/2/3-12
Symbol
Parameter
TsDI(DAV)
Data In Setup Time
0
0
2
ThDI(DA V)
Data In Hold Time
230
160
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY)
DAV 1 Input to RDY 1 Delay
Min
TdDAVOrRDY)
DAV t Output to RDY t Delay
8
TdDO(DAV)
Data Out to DAV 1 Delay
9
TdRDY(DAV)
Rdy 1 Input to DAV t Delay
NOTES:
I. Test load I
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for
a logic "0"
ClockCycle-TimeDependent
Characteristics
Min
175
0
50
30
200
0
1,3
140
• Units in nanoseconds (ns).
r Timings are preliminary and subject to change.
Z8611/2/3
Z8611/2/3-12
Symbol
Equation
Equation
TdA(AS)
TpC-75
TpC-50
2
TdAS(A)
TpC-55
TpC-40
3
4
TdAS(DR)
4TpC-140*
.4TpC-llO*
TwAS
TpC-45
3TpC-125*
TpC-30
3TpC-65*
Number
6
TwDSR
7
2TpC-90*
2TpC-55*
3TpC-175*
3TpC-120*
10
TwDSW
TdDSR(DR)
Td(DS)A
TpC-55
TpC-40
11
TdDS(AS)
TpC-55
TpC-30
12
TdR/W(AS)
TpC-75
TpC-55
13
TdDS(R/W)
TpC-65
TpC-50
14
TdDW(DSW)
TdDS(DW)
TpC-50
TdA(DR)
TpC-75
TpC-55
5TpC-215*
TpC-40
5TpC-160*
TdAS(DS)
TpC-45
TpC-30
8
15
16
17'
Notes*t
120
1,2
0 -------1,3
1,2
120
0
0
Max
120
175
5-TdDAVOf(RDY)-DAV 1 OutputtoRDY 1 Delay - - - - - - - - 0
6
TdDAVIr(RDY) DAV t Input to RDY t Delay
7
Max
• Add 2TpC when using extended memory timing
520
2194-013
Ordering
Information
Product
Number
Package/
Temp
Speed
Description
28611
CE
8.0 MHz
28MCU
(4K ROM, 40-pin)
28611
CS
8.0 MHz
Same as above
28611
PE
8.0 MHz
Same as above
28611
PS
8.0 MHz
28611-12
CE
12.0 MHz
28611-12
CS
12.0 MHz
Product
Number
28612
Package/
Speed
Temp
PE
8.0 MHz
28612
28612-12
PS
8.0 MHz
Same as above
12.0 MHz
Same as above
CS
12.0 MHz
Same as above
Same as above
Same as above
28612-12
28612-12
PE
12.0 MHz
28612-12
PS
12.0 MHz
28613
RS
8.0 MHz
28613-12
RS
12.0 MHz
28611-12
PE
12.0 MHz
Same as above-
28611-12
PS
12.0 MHz
Same as above
28612
CE
8.0 MHz
Z8MCU
(4K XROM, 64-pin)
28612
CS
8.0 MHz
Same as above
28MCU
(4K XROM, 64-pin)
CE
28MCU
(4K ROM, 40-pin)
Same as above
Description
Same as above
28 MCU (4K XROM,
Prototyping Device,
40-pin)
Same as above
NOTES: C = Ceramic, P = Plastic, R = Prototyping Device; E = -40° to +85°C, S = O°C to +70°C.
521
Irammiiny
~3~ 7 n r~(CUJ wiinlhl
~8®
rnll!X§ll[(
Figure lOco Port 2
PORT 3
(1/0 OR CONTROL)
Figure 10d. Port 3
529
Counter/
Timers
The Z8671 contains two 8-bit programmable
counter/timers (To and Tl), each driven by its
own 6-bit programmable prescaler. The Tl
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each prescaler drives its counter,
which decrements the value (1 to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQs (Tl)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (singlepass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for Tl is user-definable; it
can be either the internal microprocessor clock
(4 MHz maximum for the 8 MHz device and 6
MHz maximum for the 12 MHz device) divided
by four, or an external signal input via Port 3.
The Timer Mode register configures the external timer input as an external clock, a trigger
input that can be retriggerable or nonretriggerable, or as a gate input for the internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of Tl. Port 3 line P36 also
serves as a timer output (TOUT) through which
To, TI or the internal clock can be output.
Interrupts
The Z8671 allows six different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or individually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are 'resolved by a
programmable priority encoder that is controlled by the Interrupt Priority register.
All Z8671 interrupts are vectored; however,
the internal UART operates in a polling
fashion. To accommodate a polled structure,
any or all of the interrupt inputs can be masked and the Interrupt Request register polled to
determine which of the interrupt requests
needs service.
The BASIC/Debug Interpreter does not process interrupts. Interrupts are vectored
\
through locations in internal ROM which point
to addresses 1000-1011 (hex). To process interrupts, jump instructions can be entered to the
interrupt handling routines at the appropriate
addresses as shown in Table l.
530
(hex)
Contains Jump Instruction and
Subroutine Address for:
1000-1002
1003-100S
1006-1008
1009-100B
100C-lOOE
100F-I011
IRQO
IRQl
IRQ2
IRQ3
IRQ4
IRQS
Address
Table 1. Interrupt Jump Instructions
Clock
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTAL1 = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitance (CL = 15 pF maximum) from each
pin to ground. The specifications for the
crystal are as follows:
Il AT cut, parallel resonant
CJ Fundamental type, 8/12 MHz maximum
III Series resistance, Rs ::5 100 n
IJ 8 MHz maximum for 28671
lllI 12 MHz maximum for 28671-12
Instruction
Set
Notation
Addressing Modes. The following notation is used
IMR
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
IR
Ir
RR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Symbols. The folloWing symbols are used in
describing the instruction set.
dst
Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol
"-". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
Flags. Control Register R252 contains the folloWing
six flags:
C
Z
S
V
D
H
Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag
Affected flags are indicated by:
0
."
X
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
531
Condition
Codes
Value
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000
Meaning
Flags Set
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE'
LT
GT
LE
UGE
ULT
UGT
ULE
Instruction
Formats
S
a
S
= 1
V = 1
V =
a
Z = 1
Z = a
(S XOR V) = a
(S XOR V) = 1
[Z OR (S XOR V)) = a
[Z OR (S XOR V)) = 1
C=O
C = 1
(C = AND Z
(C OR Z) = I
a
= 0)
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dst
C
1
C = a
Z = 1
Z =a
OPC
INC r
One-Byte Instruction
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
CLR, CPL, DA, DEC,
'--......;;;=~--'
OR
11 1 1 01 dst/src 1 ~~~~'~~:R~~~~R,POP,
RRC, SRA, SWAP
I
OPC
I--'-ds-'t---I OR
11 1 101
JP, CALL (Indirect)
dst
1---=':---1 OR
OPC
VALUE
11 1 1 01
dst
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD
LD, LDE, LDEI,
LDC, LOCI
LD
dst 1 OPC
VALUE
JP
LD
CALL
CJNZ. In
Two-Byte Instruction
Three-Byte Instruction
Figure II. Instruction Formats
532
2037-013
Instruction
Summary
Opcode Flags Affected
Byte
(Hex)
CZSVDH
Instruction
and Operation
Addr Mode
AOC dst,src
dst - dst + src + C
(Note 1)
ADO dst,src
dst - dst + src
(Note 1)
00
ANO dst,src
dst - dst AND src
(Note 1)
50
dst
src
10
* 0 *
src
r
Irr
Irr
82
92
------
LOEI dst,src
Ir
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Ir
83
93
------
dst - src
* * 0 *
0
NOP
FF
DA
IRR
@SP - PC; PC - dst
06
04
------
CCF
EF
* - - - - -
POP dst
dst - @SP
SP - SP + 1
R
IR
BO
Bl
------
PUSH src
R
IR
60
61
-**0--
dst - NOT dst
CP dst,src
(Note 1)
COM dst
dst - OA dst
DEC dst
dst - dst - 1
DECW dst
dst - dst - 1
* * * X - -
RL dst
R
IR
00
01
-***--
RLC dst
RR
IR
80
81
-***--
70
71
------
CF
o- - - - -
AF
------
EJLDJ I~
90
91
****--
~I~
10
11
R
IR
RA
* 0 - -
L{i}:E3J
------
rA
r=O-F
------
,
SBC dst,src
0
EO
El
R
IR
CO
Cl
(Note 1)
3D
SCF
9F
------
****--
* 1 *
DF
1 - - - - -
DO
Dl
***0--
31
------
20
* * * * 1 *
FO
Fl
X * * X - -
IR
(Note 1)
60
-
* * 0
(Note 1)
70
-
* * 0
(Note 1)
BO
-
* * 0 - -
SRP src
1m
RP - src
- * *
R
IR
rE
r=O-F
20
21
RR
IR
AO
Al
- * * * - -
BF
******
IRET
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR(7) -1
DA
if cc is true
PC - dst
IRR
JR cc,dst
RA
if cc is true,
PC - PC + dst
Range: + 127, -128
* - -
SWAPdst~ R
cD
c=O-F
30
------
cB
c=O-F
------
r
Irr
Irr
C2
------
LOCI dst,src
Ir.
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Ir
X
r
Ir
r
R
IR
1m
1m
R
R
IR
IR
TM dst, src
XOR dst,src
Note 1
These instructions have an identical set of adaressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the following table to the
left of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using
the addressing modes r (destination) and Ir (source) is 13.
Addr Mode
D2
C3
03
(NOT dst) AND src
dst - dst XOR src
R
r
X
r
Ir
R
TCM dst,src
dst AND src
------
1m
R
(Note 1)
dst - dst - src
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
r
r
R
SUB dst,src
------
dst
src
R
R
R
IR
Ir
R
IR
1M
1M
...
3
C-l
4TI~I~
en
...:I
~
dst - dst - src - C
SRA dst
N
CO
4=3--J I~
4TI
C
INC dst
dst - dst + 1
LDC dst,src
dst - src
RR dst
RRC dst
8F
IMR (7) - 1
LO dst,src
dst - src
------
RET
AD
40
41
EI
JP cc,dst
50
51
RCF
R
IR
r - r - 1
if r *- 0
PC - PC + dst
Range: + 127, -128
dst - dst +
R
IR
C-O
DI
INCW dst
40
PC - @ SP; SP - SP + 2
IMR (7) - 0
DJNZ r,dst
(Note 1)
SP - SP-1; @SP- src
dst - src
DA dst
OR dst,src
dst - dst OR src
C - NOT C
dst - 0
Opcode Flags Affected
Byte
(Hex)
CZSVDH
dst
LOE dst,src
CALL dst
Sp - SP - 2
CLR dst
Addr Mode
Instruction
and Operation
Lower
Opcode Nibble
rn
rn
m
~
ffil
(l]
533
CI
Registers
R240 SIO
Serial I/O Register
(FOH ; Read/Write)
R244 TO
Counter/Timer 0 Register
(F4H; Read/Write)
I 0,1 0.1 0 10.1 0,1 0, I0, IDo I
I 0,1 0.1 0 10.1 0,1 0, I0, IDo I
5
5
'------SERIAL DATA (Do
= LSB)
R241 TMR
Timer Mode Register
(FI H ; Read/Write)
R245 PREO
Prescaler 0 Register
(F5H ; Write Only)
I 0,1 0,1 0 10.1 0,1 0, I0, IDo I
I~I~I~I~I~I~I~I~I
~~O
~
J
5
NOT Tou,MODES
USED = 00
i~ g~i ~ ~~
INTERNAL CLOCK OUT
= 11
.-J
FUNCTION
1 = NO
LOAD
To
0 = DISABLE To COUNT
1
ENABLE To COUNT
=
0 = NO FUNCTION
1
LOAD T, .
0 = DISABLE T, COUNT
T MODES
EXTERNAL CLOCK IN~OT
00
GATE INPUT = 01
=
(NON.R~~~~g~~~~:~~) =
To INITIAL VALUE (WHEN WRITTEN)
'------(RANGE: 1-256 DECIMAL 01-00 HEX)
To CURRENT VALUE (WHEN READ)
=
1 = To MODULO·N
RESERVED (MUST BE 0)
PRESCALER MODULO
' - - - - - - - ( R A N G E : 1-64 DECIMAL
01-00 HEX)
1 = ENABLE T, COUNT
10
COUNTMODE
o = To SINGLE·PASS
TRIGGER INPUT = 11
(RETRIGGERABLE)
R242 TI
Counter Timer I Register
(F2H ; Read/Write)
R246 P2M
Port 2 Mode Register
(F6H; Write Only)
I 0,1 0,1 0 10.1 0,1 0, I0, IDo I
I 0,1 0,1 0 10.1 0,1 0, I 0, I Do I
5
5
P2o-P2, 110 DEFINITION
' - - - - - - 0 DEFINES BIT AS OUTPUT
T, INITIAL VALUE (WHEN WRITTEN)
'------(RANGE 1 256 DECIMAL 01 00 HEX)
T, CURRENT VALUE (WHEN READ)
1 DEFINES BIT AS INPUT
R243 PREI
Pres caler I Register
(F3 H ; Write Only)
R247 P3M
Port 3 Mode Register
(F7H ; Write Only)
I0,10,1 0 10.1 0,1 0, I0, IDo I
I~I~I~I~I~I~I~I~I
5
l
COO~Ni' ~~~ELE.PASS
1 = T, MODULO.N
CLOCK SOURCE
1
T, INTERNAL
o T, EXTERNAL TIMING INPUT
(T'N) MODE
PRESCALER MODULO
'-------(RANGE: 1·64 DECIMAL
01·00 HEX)
~~~
O1 PORT
2 PULL·UPS OPEN DRAIN
PORT 2 PULL·UPS ACTIVE
RESERVED (MUST BE 0)
o P32 = INPUT
=
P3s
OUTPUT
1 P32'; DAVO/RDYO P3s = RDYO/1lAVO
o 0 P3, = INPUT
~ ~} P3, = INPUT
'---------
P3,
= DAV1/RDYI
P34
= OUTPUT
P34 = OM
P34
RDY1/DAVl
=
'--------~ ~~: ~ ~~vU~~6~1 ~~: ~ ~g~~/~~~r)
11
~ ~~~ ~ kN~~IL IN ~~~ ~ ~~~:;'~TOUT
'----------~ ~~=:i~ g~F
Figure 12. Co~trol Registers
534
2037-013
Registers
(Continued)
R248 POIM
Port 0 and I Mode Register
!a2S2 fLAGS
FICl:g'
Rcgi.Gt~T
(F8H ; Write Only)
(FCH ; Read/Write)
I0,1 0,1 0 10, I0,1 D,TD,lO:J
I D,I D,I D51 D, I0,1 D,I 0, IDo I
5
MODE~
PO,-PO,
OUTPUT; 00
INPUT; 01
A,rA15 ; IX
EXTERNAL MEMORY TIMING
NORMAL; 0 EXTENDED; 1
-rMODE
L POo-PO,
00; OUTPUT
~
.
~~~
LUSERFLAGFI
LUSER FLAG F2
01 ; INPIJT
IX; A,-A"
STACK SELECTION
o ; EXTERNAL
1 ; INTEf>NAL
PIa-PI, MODE
00 = BYTE OUTPUT
01 ; BYTE INPUT
10 ; ADo-AD,
11 ; HIGH·IMPEDANCE ADo-Ail7,
AS, OS, R/W, As-A", A'2-A'5
IF SELECTED
RGgiztcr Pointer
(F9H ; Write Only)
(FDH; Read/Write)
IR03, IROS PRIORITY (GROUP A)
o = IROS > IR03
1 = IR03 > IROS
IROO, IR02 PRIORITY (GROUP B)
o = IR02 > IROO _ _ _ _ _---1
1 = IROO > IR02
ZERO FLAG
R253 RP
I 0,1 0,1 0 10, I0,1 0,1 0, IDo I
I~I~I~I~I~I~I~I~I
I
OVERFLOW FLAG
SIGN FLAG
L . . . . - - - - - - - C A R R y FLAG
R2491PR
Interrupt Priority Register
RESERVED (MUST BE 0):J
HALF CARRY FLAG
DECIMAL ADJUST FLAG
5
INTERRUPT GROUP PRIORITY
RESERVED = 000
C > A > B = 001
A> C > C = 010
A> C > 8 = 011
B > C > A = 100
C> B > A = 101
B > A > C = 110
RESERVED = 111
REGISTER
FO!NTCR
{:~g)J
C=DON'T CARE
IR01, IR04 PRIORITY (GROUP C)
o = IROI > IR04 - - - - - - - - '
1 = IR04 > IROI
R250 IRQ
Interrupt Reque!::t Register
R254 SPH
Stc.:c!: Pointer
(FAH; Read/Write)
(FEH ; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST'BE O)=:r-
c==
I~I~I~I~I~I~I~I~I
IROO
IROI
IR02
IR03
IR04
IROS
P32 INPUT (Do = IROO)
P33 INPUT
P3, IN?LiT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT
T,
L--_ _ _ _ STACK POINTER UPPER
BYTE (SP.-SP 15)
R2511MR
Interrupt Mask Register
R2558PL
Stack Point~r
(FBH ; Read/Write)
(FFH ; Read/Write)
I~I~I~I~I~I~I~I~I
l!d 061 0 10.1 0 10,1 0, I I
5
c==
1 ENABLES IRaQ-lAOS
(Do = IROC)
L--_ _ _ _ _ _ _ RESERVED (MUST BE 0)
II
3
Do
LI_ _ _ _
~~~~~s~~~~J~R
LOWER
' - - - - - - - - - - 1 ENADLES INTERRUPTS
Figure 12. Control Registers (Continued)
2037-013
535
Z8671
Lower Nibble (Hex)
Opcode
Map
o
o
2
3
"
5
M
III
a
GI
:a
:9
:z;
6
7
..
III
0.
0.
8
C
0
E
F
per
Instruction
7
8
9
A
B
10,5
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
LO
LO
OJNZ
JR
LO
JP
INC
fl,R2
r2, Rl
fl,RA
cc,RA
ll,IM
cc,DA
fl
6,5
IRl
rl, r2
fl,Ir2
R2,Rl
IR2,Rl
Rl,lM
IRl,lM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
10,5
ADD ADD ADD ADD ADD ADD
Rl
IRl
rl, r2
r 1, Ir2
R2,Rl
IR2,Rl
Rl,lM
6,5
6,5
6,5
10,5
10,5
INC
INC
10,5
10,5
SUB
SUB
SUB
SUB
SUB
SUB
IRl,lM
Rl
IRl
rl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,lM
6,1
6,5
6,5
10,5
10,5
10,5
SRP
10,5
IP
SBC
SBC
SBC
SBC
IRRl
1M
SBC
SBC
rl, r2
rl,lr:z
R2,Rl
IR:z,Rl
Rl,lM
IR1,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
OA
OA
OR
OR
OR
OR
OR
OR
IR1,IM
Rl
IRl
rl, r:z
rl,lr:z
R2,Rl
IR2,Rl
Rl,lM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
ANO
ANO
ANO
ANO
ANO
ANO
IR1,IM
Rl
IRl
rl, r:z
rl,lr:z
R:z,Rl
IR:z,Rl
Rl,lM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
Rl
IRl
rl, r:z
fl,lr:z
R:z,Rl
IR2,Rl
Rl,lM
IRl,lM
10/12,1 12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH PUSH
TM
TM
TM
TM
TM
TM
R2,Rl
IR2,Rl
Rl,lM
IRl,lM
R:z
IR:z
rl, r2
rl,lr:z
10,5
10,5
12,0
18,0
LOE
LOEI
rl,Irr2
Ir 1, Irr2
12,0
18,0
LOE
LOEI
OECW OECW
IRl
6,5
RL
Rl
IRl
r---
r---
r--r---
r---
r---
r---
r--6,1
DI
r--6,1
EI
10,5
IRl
6,5
6,5
10,5
10,5
10,5
CP
CP
CP
CP
CP
CP
rl, r2
rl, Ir2
R2,Rl
IR2,Rl
Rl,lM
IRl,lM
10,5
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
Rl
IRl
rl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,lM
IR1,IM
6,5
6,5
12,0
18,0
10,5
RRC
RRC
LOC
LOCI
LO
Rl
IRl
rl, Irr2 Irl,Irr2
6,5
6,5
12,0
18,0
SRA
LOC
LOCI CALL*
Rl
IRl
6,5
6,5
6,5
10,5
RR
RR
LO
LO
Rl
IRl
rl,IR2
R2,Rl
8,5
8,5
6,5
10,5
to
to
Irl, r2
R2,IRl
SWAP SWAP
IRl
vP
~
2
14,0
RET
~
16,0
IRET
---6,5
fl, x, R2
SRA
r2,Irrl Ir2,Irrl
r---
20,0
20,0
10,5
CALL
LO
DA
r2, x, Rl
10,5
10,5
10,5
LO
LD
LD
IR2,Rl
Rl,lM
IRl,lM
IRRl
'"
-
Execution
Cycles
Upper
Opcode - - . A
Nibble
First
Operand
+
6,5
r--6,5
CCF
r--6,0
1
vP
3
Pipeline
Cycles.
Mnemonic
Second
Operand
·2-byte instruction; fetch cycle appears as a 3-byte instruction
RCF
SCF
"I
\..
NOP
~--------~~~.-----------'~ ~ ~
2
3
Lower
Opcode
Nibble
536
F
r2,Irfl Ir2,Irrl
INCW INCW
"
E
IR1,IM
8,0
RL
C
ADC ADC ADC ADC ADC ADC
6,5
Rl
By~es
6
DEC
RRl
B
6,5
o
5
Rl
10,5
A
6,5
"
6,5
6,5
9
3
DEC
RRl
=-
2
Legend:
R = a-Bit Address
r = 4-Bit Address
RI or n = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
The characteristics below apply for the
following standard. test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
+5V
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
[J +4.75 V :::; Vee:::; +5.25 V
[] GND = 0 V
IJ
O°C :::; TA :::; +70°C
+5V
+5V
+5V
1.5k
1.Sk
2.1K
18K
74LS04
74LS04
CLI~CK ---I>·o---+~>-l~I><>--+--'I--
I
XTAL2
I
CL = lSpF MAX
' - - - - - - . - - XTAL 1
1
I
I
CL
Figure 13. Test Load 1
Figure 14. Test Load 2
= lSpF MAX
Figure 15. TTL External Clock Interface Circuit
(Both the clock and its complement <:Ire required)
DC
Characteristics
8085-0313,2194-010
Symbol
Parameter
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
v
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
ILL
Input Leakage
IOL
Output Leakage
1m
2.4
Condition
=
-250 p.A
V
IOH
0.4
V
IOL ;", +2.0
-10
10
itA
o V~
VIN
~
+5.25 V
-10
10
itA
o V~
VIN
~
+5.25 V
Reset Input Current
-50
itA
Vee = +5.25 V, VRL = 0 V
Icc
Vee Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
3
Vee
V
rnA
Power Down Mode
Power Down
537
External 110
or Memory
Read/Write
R1W
PORT 0,
DM
16
PORT 1
is
CD
CD
os
(READ)
PORT 1
Ao-A7
00-07 OUT
os
(WRITE)
Figure 15. External I/O or Memory Read/Write
Z8671
Parameter
Min
Max
Z8671-12
Min
No.
Symbol
TdA(AS)
Address Valid to AS t Delay
50
35
2
TdAS(A)
AS I to Address Float Delay
70
45
Max
Notes*t
1,2,3
1,2,3
TdAS(DR)
3
4
TwAS
TdAz(DS)
5
6-TwDSR
AS I to Read Data Required Valid
AS Low Width
Address Float to DS I
DS (Read) Low Width
80
55
1,2,3,4
1,2,3
0
250
0
185
1,2,3,4
7
DS (Write) Low Width
160
110
8
9
10
TwDSW
TdDSR(DR)
ThDR(DS)
DS I to Read Data Required Valid
Read Data to DS t Hold Time
TdDS(A)
DS t to Address Active Delay
TdDS(AS)
11
DS t to AS I Delay
12-TdR/W(AS)--R/W Valid to AS I Delay
TdDS(R/W)
13
DS I to R/W Not Valid
TdDW(DSW)
Write Data Valid to DS (Write) I Delay
14
TdDS(DW)
15
DS t to Write Data Not Valid Delay
16
17
TdA(DR)
TdAS(DS)
Address Valid to Read Data Required Valid
AS I to DS I Delay
NOTES:
1. Test Load 1
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.
4. When using extended memory timing add 2 TpC.
538
360
220
130
200
50
60
50
70
55
1,2,3
30
35
35
1,2,3
1,2,3
1,2,3
1,2,3
45
255
410
80
1
1,2,3
0
45
0
70
70
1,2,3,4
1,2,3,4
55
1,2,3,4
1,2,3
5. All timing references use 2.0 V'for a logic "1" and 0.8 V for a logic "0".
• All units in nanoseconds (ns).
t All timings are preliminary and subject to change.
2194·011
Additional
Timing
Figure 16. Additional Timing
No.
Symbol
Parameter
Min
Z8671
Max
125
1000
1
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise And Fall Times
3
TwC
Input Clock Width
TwTinL
4
5-TwTinH
Timer Input High Width
TpTin
Timer Input Period
7
TrTin, TfTin
Timer Input Rise And Fall Times
8a
TwIL
Interrupt Request Input Low Time
8b
TwIL
TwIH'
Interrupt Request Input Low Time
Interrupt Request Input High Time
9
AO-A10
~~
100
3TpC
8TpC
70
3TpC
1000
8TpC
100
100
2
IIen
2
2
n
...--:a
ac
70
2
2,3
3TpC
3TpC
2,4
2,3
3. Interrupt request via Port 3 (P31-P33)'
4. Interrupt request via Port 3 (P30)'
• Units in nanoseconds (ns).
t All timings are preliminary and subject to change.
.JJU
_ _ _ _- : :_ _ _ _-:-_A_DD_R_ES_S_V_A_LlD
__________
1--- _ C D----"'~l
X
_-----J_
Do-D7
26
3TpC
Notes*t
15
37
100
3TpC
NOTES:
1. Clock timing references uses 3.8 V for a logic "1" and 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "I" and 0.8 V for
a logic "0".
Memory Port
Timing
83
25
Timer Input Low Width
6
Z8671-12
Min
Max
DON'T CARE
T~l~
K-
DATA IN VALID
Figure 17. Memory Port Timing
No.
Symbol
Parameter
2
TdA(DI)
ThDI(A)
Address Valid to Data Input Delay
Data In Hold Time
NOTES:
1. Test Load 2
2. This is a Clock-Cycle-Dependent parameter. For clock frequencies other than the maximum, use the following formula:
Z8671 = 5 TpC - 165
Z8671-12 = 5 TpC - 95
2194-012, 2037-019
Min
Z8671
Max
Z8671-12
Min
Max
460
o
320
o
Notes*t
1,2
1
• Units are nanoseconds unless otherwise specified; timings are
preliminary and subject to change.
539
==
Handshake
Timing
DA: ~:, ______~
___ .:"""":_ ~
....._-----
RDY
(OUTPUT)
Figure 17a. InputHandshake
r-
DATA OUT
DATA OUT VALID
--~~------------------
1~-CD}----~-~
DAV
(OUTPUT)
RDY
(INPUT)
Figure 17b. Output Handshake
Z8671
No.
Symbol
Parameter
Min
Max
Z8671-12
Min
TsDI(DAV)
Data In Setup Time
0
0
2
ThDI(DAV)
Data In Hold Time
230
160
3
TwDAV
Data Available Width
175
120
4
TdDAVIf(RDY)
DAV I Input to RDY I Delay
175
5-TdDAVOf(RDY)-DAV I Output to RDY I D e l a y - - - - - - - - - 0
6
TdDAVIr(RDY)
DAV I Input to RDY I Delay
7
TdDAVOrRDY)
DA V I Output to RDY t Delay.
8
TdDO(DAV)
Data Out to DA V I Delay
9
TdRDY(DAV)
Rdy I Input to DA V 1 Delay
175
NOTES:
I. Test load 1
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for
a logic "0".
ClockNumber
Cycle-TimeDependent
Characteristics
Symbol
120
0
50
30
200
Notes*t
120 .
1,2
1
,
3
0
0
0
Max
0
1,2
1,3
140
• Units in nanoseconds (ns).
t All timings are preliminary and subject to change.
Z8671
Z8671-12
Equation
Equation
TdA(AS)
TpC-75
TpC-50
TpC-40
2
TdAS(A)
TpC-55
3
TdAS(DR)
4TpC-140*
4TpC-II0*
4
TwAS
TpC-45
TpC-30
6
TwDSR
3TpC-125*
3TpC-65*
7
TwDSW
2TpC-90*
2TpC-55*.
8
TdDSR(DR)
3TpC-175*
3TpC-120*
10
Td(DS)A
TpC-55
TpC-40
11
TdDS(AS)
TpC-55
TpC~30
12
TdR/W(AS)
TpC-75
TpC-55
13
TdDS(R/W)
TpC-65
TpC-50
14
TdDW(DSW)
TpC-75
TpC-50
15
TdDS(DW)
TpC-55
TpC-40
16
TdA(DR)
5TpC-215*
5TpC-160*
17
TdAS(DS)
TpC-45
TpC-30
• Add 2TpC when using extended memory timing
540
2194-013
Ordering
Information
Product
Number
P~ckagc/
Temp
Speed
Z8671
PE
8.0 MHz
Z8671
PS
Z8671
CE
Z8671
CS
Description
Product
Number
Package/
Temp
Speed
Description
' PE
12.0 MHZ
Z8 MCU with
BASIC/Debug
Interpreter
(40-pin)
Z8671-12
PS
12.0 MHz
Same as above
Z8671-12
CE
12.0 MHz
Same as above
Z8671-12
CS
12.0 MHz
Same as above
Z8 MCU with
BASIC/Debug
Interpreter
(40-pin)
Z8671-12
8.0 MHz
Same as above
8.0 MHz
Same as above
8.0 MHz
Same as above
NOTES: C = Ceramic; P = Plastic; E = -40°C to +85°C, S = O°C to +70°C.
541
Z8® 18681/82
ROMless
Microcomputer
Product
Specification
Zilog
September 1983
Features
III Complete microcomputer, 24 I/O lines, and
II
up to 64K bytes of addressable external
space each for program and data memory.
El
143-byte register file, including 124
general-pwpose registers, three I/O port
registers, and 16 status and control
registers.
II
Vectored, priority interrupts for I/O,
counter/timers, and UART.
II
On-chip oscillator that accepts crystal or
external clock drive.
contents of general-purpose registers.
Single + 5 V power supply-all I/O pins
TTL compatible.
Ell
Available in 8 and 12 MHz versions.
13
General
. Description
The 28681and 28682 are ROMless versions of
the 28 single-chip microcomputer. The 28682
is usually more cost effective. These products
differ only slightly and can be used interchangeably with proper system design to provide maximum flexibility in meeting price and
delivery needs .. The 28681182 offers all the
outstanding features of the '28 family architecture except an on-chip program ROM. Use
of external memory rather than a preprogrammed ROM enables this 28 microcomputer
_
TlM~=g
CONTROL
.
PRO~/~A~RMAA8~;~:
RESET
R/W
1
+5V
XTALl
AS
PO.
XTAL2
P20
PO,
P2,
_
PO.
P2.
PORT 1
(BYTE
PROGRAMMABLE)
ADo-AD,
PO,
Pl 0
P30
Pl,
P3,
P1 2
P32
Pl 3
P3 3
. Pl.
P3,
Pl s
P3 s
P1 6
P36
Pl,
P3,
Figure 1. Pin Functions
m Low-power standby option that retains
to be used in low volume applications or where
code flexibility is required.
The 28681182 «:an provide up to 16 output
address lines, thus permitting an address
space of up to 64K by tea of data or program
memory. Eight address outputs (ADo-AD7) are
provided by a multiplexed, 8-bit, Address/Data
bus. The remaining 8 bits can be provided by
the software configuration of Port 0 to output
address bits Aa-AIS.
XTAL2
PORT 2
(BIT PRO·
GRAMMABLE)
I/O
PO s Z8681/82 P2 s
POa
MCU
P2a
P2,
CI
+5V
GND
os
P0 2
PORTO
(NIBBLE
2194-001, 002
Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit programmable prescaler.
Register Pointer so that short, fast instructions can access anyone of the nine
working-register groups.
PORT 3
(FOUR INPUT;
FOUR OUTPUT)
SERIAL AND
PARALLEL I/O
AND CONTROL
P3 a
P3, .
XTALl
P2,
P3,
P2 a
P30
P2 s
RESET
P2.
R/W
P2 3
os
P2 2
~
P2,
P3 s
P20
GND
P3 3
P3 2
P3.
POo
Pl,
po,
P1 6
P0 2
Pl s
P0 3
Pl.
PO.
P1 3
PO s
P1 2
PO a
Pl,
PO,
Pl.
Figure 2. Pin Assignments
543
General
Description
(Continued)
Available address space can be doubled (up
to 128K bytes for the 28681 and 124K bytes for
the 28682) by programming bit 4 of Port 3
(P34) to act as a data memory select output
(DM). The two states of DM together with the
16 address outputs can define separate data
and memory address spaces of up to
64K/62Kbytes each.
There are 143 bytes of RAM located on-chip
and organized as a register file of 124 generalpurpose registers, 16 control and status
registers, and three I/O port registers. This
register file can be divided into nine groups of
16 working registers each. Configuring the
register file in this manner allows the use of
short format instructions; in addition, any of
the individual registers may be accessed
directly.
The pin functions and the pin assignments of
the 28681182 40-pin package are illustrated in
Figures 1 and 2, respectively.
Architecture
28681182 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O capabilities. The 28681182 fulfills,this
with 24 pins available for input and output.
These lines are grouped into three ports of
eight lines each and are configurable under
software control to provide timing, status
signals, serial or parallel I/O with or without
handshake, and an Address bus for interfacing
external memory.
Three basic address spaces are available:
program memory, data memory and the
register file (internal). The 143-byte randomaccess register file is composed of 124 generalpurpose registers, three I/O port registers, and
16 control and status registers.
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized'
b~cause one of the on-chip timers supplies the
bit rate. Figure 3 shows the 28681182 block
diagram.
OUTPUT
INPUT
Vee
GND
M/L.---!-! _\~--'---1
UART
[
lllllltl
110
(BIT PROGRAMMABLE)
PORTO
ADDRESS OR 110
(NIBBLE PROGRAMMABLE)
,
ADDRESSIDATA OR 110
(BYTE PROGRAMMABLE)
#
Z·BUS WHEN USED AS
ADDRESSIOATA BUS
Figure 3. Functional Block Diagram
Pin
Description
544
AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the -beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.
POo-P~.
P2o-P27. P30-P37' I/O Port Lines
(inpuVoutputs, TTL-compatible). These 24
lines are divided into three 8-bit I/O ports that
can be configured under program control for
I/O or external memory interfpce (Figure 3).
P1o-PI7. Address/Data Port (bidirectional).
Multiplexed address (Ao-A7) and data (Do-D7)
lines used to interface with program and data
memory.
2194-003
Pin
Description
(Continued)
RESET.* Reset (input, active Low). RESET initializes the 28681182. When RESET is deactivated, program execution begins from program location OOOCH for the 28681 and 0812H
for the 28682.
the 28681182 is writing to external program or
data memory.
XTALL XTAL2. Crystall, Crystal 2 (time-base
input and output). These pins connect a
parallel-resonant crystal to the on-chip clock
oscillator and buffer.
R/W. Read/Write (output). RlW is Low when
Summary of
Z8681 and
Z8682
Differences
Feature
Z8681
Z8682
Address' of first instruction executed after Reset
12
2066
Addressable memory
space
0-64K
2K-64K
Address of interrupt
vectors
0-11
2048-2065
Reset input high voltage
TTL levels'
7.35-8.0 V
Port 0 configuration
after Reset
Input, float after reset.
Can be programmed as
Address bits.
Output, configured as
Address bits A8-A15'
External memory timing
start-up configurations
Extended Timing
Normal Timing
J~'errupt
2 byte vectors point
directly to service
routines.
2 byte vectors in internal
N
ROM point to 3 byte Jump
instructions, which point
to service routines.
n
26JLsec
36JLsec
vectors
Interrupt response time
N
CO
...emo
CO
~
C
'8.0 V VIN max
Address
Spaces
For the 28681, the first 12 bytes of program
memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that
Program Memory.* The 28681182 addresses
64K/62K bytes of external program memory
space (Figure 4).
Z8681
Z8682
6553
5536
PROGRAM
MEMORY
PROGRAM
MEMORY
r----- /
,#
f=
f=
f=
-
IR04
IR03
=
=
=
-
IR02
~
IROl
-
IROO
=
r-----
(812H ) 2066
(811 H) 2065
= ..,.-
f=
=
LOCATION OF FIRST
BYTE OF INSTRUCTION
EXECUTED AFTER
RESET (Za681)
IROS
LOCATION OF FIRST'
BYTE OF INSTRUCTION
EXECUTED AFTER
RESET (Z8682)
3 BYTE INTERRUPT
JUMP INSTRUCTIONS
(800H ) 2048
2047
NOT
ADDRESSABLE
r...
I-
IR04
INTERRUPT
VECTOR
(LOWER BYTE)
I-
IR03
INTERRUPT
VECTOR
(UPPER BYTE)
~
IR02
I-
IROl
-
I-
IROO
-
I-
IR05
12
11
10
9
8
7
2 BYTE
6 ..,.-INTERRUPT
5
VECTORS
4
3
2
1
0
Figure 4. Z8681/82 Program Memory Map
'This feature differs in the Z8681 and Z8682
2194-004
545
Address
Spaces
(Continued)
correspond to the six available interrupts. Program execution begins at location OOOCH after
a reset.
The 28682 has six 24-bit interrupt vectors
beginning at address 0800H. The vectors consist of Jump Absolute instructions. After a
reset, program execution begins at location
0812H 'for the 28682.
Data Memory. * The 28681182 can address
64K/62K bytes of external data memory. External data memory may be included with or
separated from the external program. memory
space. DM, an optional I/O function that can
be programmed to appear on pin P34, is used
to distinguish between data and program
memory space.
Register File. The 143-byte register file
includes three I/O port registers (RO, R2, R3),
124 general-purpose registers (R4-RI27) and
16 control and status registers (R240-R255).
LOCATION
255
254
These registers are assigned the address locations shown in Figure 5.
28681182 instructions can access registers
directly or indirectly with an 8-bit address
field. This also allows short 4-bit register addressing using the Register Pointer (one of the
control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 5). The Register Pointer
addresses the starting location of the active
working-register group (Figure 6).
Stacks. Either the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory. An 8-bit Stack
Pointer (R255) is used for the internal stack
that resides within the 124 general-purpose
registers (R4-R127).
IDENTIFIERS
STACK POINTER (BITS 7-0)
SPL
STACK POINTER (BITS 15-8)
SPH
253
REGISTER POINTER
252
PROGRAM CONTROL FLAGS
FLAGS
251
INTERRUPT MASK REGISTER
IMR
250
INTERRUPT REOUEST REGISTER
IRO
249
INTERRUPT PRIORITY REGISTER
IPR
248
PORTS 0-1 MODE
P01M
247
PORT 3 MODE
P3M
246
PORT 2 MODE
P2M
245
TO PRESCALER
r--_~-;-;:(= = 1 - - - - - - . 2 5 5
RP
PREO
244
TIMER/COUNTER 0
243
Tl PRESCALER
242
TIMER/COUNTER 1
241
TIMER MODE
TMR
240
SERIAL I/O
SIO
TO
PREl
T1
NOT
IMPLEMENTED
~
1--_~:""';'_L-~~--:---I253
......- - - - - - - - - - ' 2 4 0
The upper nibble of the register ilia address
provided by the register pointer specifies
the active working-register group.
127
...
- ...
- ...
- ... (
-
The lower
nibble of
the register
127
SPECIFIED WORKING·
REGISTER GROUP
{
GENERAL·PURPOSE
REGISTERS
-
PORT 3
P3
PORT 2
P2
PORT 0
Figure 5. The Register File
PO
file address
~I- provided by
the Instruction
points
the
to
... {
specified
register.
- ... {
-
... {
1
-------------.- 3
I/O PORTS
0
Figure 6. The Register Pointer
"This feature differs in the 28681 and 28682
546
2194- 005, 006
Serial
Input/
Output
Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second at 8 MHz
and 93.75K bits/second at 12 MHz.
The 28681182 automatically adds a start bit
and two stop bits to transmitted data (Figure
7). Odd parity is also available as an option.
Eight data bits are always transmitted,
Isp ISP I0 1Dsl 0510.1 0 10 10, IDo IST I
7
1
3
regardless of parity selection. If parity is
enabled, the eighth data bit is used as the odd
parity bit. An interrupt request (IRQ4) is
generated on all transmitted characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data' is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.
I0
I SP
2
7 ,
De ,
0
5'
D. ,
0 0 10, IDo' ST I
3'
2
LSTART BIT
LSTART BIT
' - - - - - - E I G H T DATA BITS
TWO STOP BITS
Received Data
(No Parity)
(No Parity)
3
T
' - - - - - - - - - - O N E STOP BIT
Transmitted Data
ISP IP I0.1 010.1 0 10 10, IDo IST I
I I P , Dsl 05' 0.1 0 10 10, IDo ISTI
, I SP SP
L - . . - - - - E I G H T DATA BITS
5
2
' - - - - - - S E V E N DATA BITS
ODD PARITY
TWO STOP BITS
2
LSTART BIT
_ _
LSTARTBIT
I,
3
II
' - - - - - - S E V E N DATA BITS
L..._ _ _ _ _ _ _ _ PARITY ERROR FLAG
- - - - - - - - - O N E STOP BIT
L-,
Transmitted Data
Received Data
(With Parity)
(With Parity)
Figure 7. Serial Data Formats
Counter/
Timers
The 28681182 contains two 8-bit programmable counter/timers (To and TIL each driven
by its own 6-bit programmable prescaler. The
T1 prescaler can be driven by internal or external clock sources; however, the To prescaler
is driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each prescaler drives its counter,
which decrements the value (1 to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQs (Tl)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-
pass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for T1 is user-definable; it
can be either the internal microprocessor clock
divided by four, or an external signal input via
Port 3. The Timer Mode register configures the
external timer input as an external clock, a
trigger input that can be retriggerable or nonretriggerable, or as a gate input for the internal clock. The counter/timers can be programmably cascaded by connecting the To' output to the input of Tl. Port 3 line P36 also
serves as a timer output (TOUT) through which
To, T1 or the internal clock can be output.
I/O Ports
The 28681182 has 24 lines available for input
and output. These lines are grouped into three
ports of eight lines each and are configurable
as input, output or address. Under software
control, the ports can be programmed to pro-
vide address outputs, timing, status sig~als,
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.
Port 1 is a dedicated 2-BUS compatible'
memory interface. ThG operations of Port 1 are
supported by the Address Strobe (AS) and
Data Strobe (DS) lines, and by the Read/Write
(R/W) and Data Memory (DM) control lines.
The low-order program and data memory
addresses (Ao-A7) are output through Port 1
(Figure 8) and are multiplexed with data in/out
(Do-D7). Instruction fetch and data memory
read/write operations are done through this
port.
Port 1 cannot be used as a register nor can a
handshake mode be used with this port.
2037·009
547
I/O Ports
(Continued)
Both the 28681 and 28682 wake up with the 8
bits of Port 1 configured as address outputs for
external memory. If more than eight address
line are required with the 28681, additioni,'il
lines can be obtained by programming Port 0
bits as address bits. The least-significant four
bits of Port 0 can be configured to supply address bits Aa-All for 4K byte addressing or
both nibbles of Port 0 can be configured to
supply address bits Aa-AIS for 64K byte addressing.
Port 0* can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory (Figure 9). When used as an
I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3
lines P32 and P35 are used as the handshake
controls DAVo and RDYo. Handshake signal
assignment is dictated by the I/O direction of
the upper nibble P04-P07.
For external memory references, Port 0 can
provide address bits As-All (lower nibble) or
As-AIS (lower and upper nibbles) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as
I/O while the lower nibble is used for
addressing.
.
In the Z8681 *, Port 0 lines float after reset;
their logic state is unknown until the execution of ap initialization routine that configures
Port O.
Such an initialization routine must reside
within the first 256 bytes of executable code
and must be physically mapped into memory
by forcing the Port 0 address lines to a known
state. See Figure 10. The proper Port initialization sequence is:
PORT 1
(1/0 OR ADo-AD1
TO EXTERNAL
MEMORY
Figure 8. Port 1
eliminate this extended timing mode.
The following example illustrates the manner
in which an initialization routine can be
mapped in a 28681 system with 4K of memory.
Example. In Figure 10, the initialization
routine is mapped to the first 256 bytes of program memory. Pull-down resistors maintain the
address lines at a logic 0 level when these
lines are floating. The leakage current caused
by fanout must be taken into consideration
when selecting the value of the pulldown
resistors: The resistor value must be large
enough to allow the Port 0 output driver to pull
the line to a logic one. Generally, pulldown
resistors are incompatible with TTL loads. If
PortO drives into TTL input loads (ILOW = 1.6
ma) the external resistors should be tied to
Vee and the initialization routine put in address space FFOOH-FFFFH.
In the Z8682 *, Port 0 lines are configured as
address lines Aa-:-A15 after a Reset. If one or
both nibbles are needed for I/O operation,
they must be configured by writing to the Port
o Mode register. The 28682 is in the fast
memory timing mode after Reset, so the initialization routine must be in fast memory.
1. Write initial address (As-AlS) of initialization routine to Port 0 address lines.
~}P04-P01
2. Configure Port 0 Mode Register to oufput
POO-P03
Aa-Als (or Aa-All)·
Z8681182
}PORTO
(1/0 OR AS-A15
4
MCU
To permit the use of slow memory, an'
automatic wait mode of two oscillator clock
cycles is configured for the bus timing of the
28681 after each reset. The initialization
routine could include reconfiguration to
PORT1
<
_
} HANDSHAKE CONTROLS
DAVo AND RDYo
(P32 AND P3S>
Figure 9. Port 0
ADo-AD7
As,
os, R/W
>
~
Z8681/82
MCU
112 PORT 0
PROGRAM
MEMORY
(4K BYTES)
I
fFigure 10. Port 0 Address Lines Tied to Logic 0
'This feature differs in the 28681 and 28682
548
2194-007,008,009
I/O Ports
(Continued)
Port 2 bits can be programmed independently as input or output (Figure 11). This port
is always available for I/O operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Port 0, Port 2 may also be placed under
handshake control. In this configuration, Port
3 lines P31 and P36 are used as the handshake
controls lines DAV2 and RDY2. The handshake
signal assignment for Port 3 lines P31 and P36
is dictated by the direction (input or output)
assigned to bit 7 of Port 2.
--
Clock
The Z8681182 allows six different interrupts
from eight sources: the four Port 3 lines
P30-P33, Serial In, Serial Out, and the two
counter/timers. These interrupts are both
maskable and prioritized. The Interrupt Mask
register globally or indiVidually enables or
disables the six interrupt requests. When more
than one interrupt is pending, priorities are
resolved by a programmable priority encoder
that is controlled by the Interrupt Priority
register.
All Z8681 and Z8682 interrupts are vectored
through locations in program memory. When
an interrupt request is granted, an interrupt
machine cycle is entered. This disables all
subsequent interrupts, saves the Program
Counter and status flags, and accesses the program memory vector location reserved for that
interrupt. In the Z8681, this memory location
and the next byte contain the 16-bit address of
the interrupt service routine for that particular
interrupt request. The Z8681 takes 26 system
clock cycles to enter an interrupt subroutine.
The Z8682 has a small internal ROM that
contains six 2-byte interrupt vectors pointing to
The on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALI and XTAL2, using the recommended
capacitance (CL = 15 pF maximum) from each
pin to ground. The speCifications for the
crystal are as follows:
ponT 2(1/0)
Z8681/82 : : : :
MCU
_
-
P27
HANDSHAKE CONTROLS
} DAV2 AND RDY2
(P3 1 AND P3sl
Figure 11. Port 2
Port 3 lines can be configured as I/O or control lines (Figure 12). In either case, the direction of the eight lines is fixed as four input
(P30-P33) and four output (P34-P37)' For serial
I/O, lines P30 and P37 are programmed as
serial in and serial out, respectively.
Port 3 can also provide the follOWing control
functions: handshake for Ports 0 and 2 (DAV
and RDY); four external interrupt
request signals (IRQo-IRQ3); timer input and
output signals (T.lli....9nd TOUT) and Data
Memory Select (DM).
Interrupts*
2
P 0
PORT 3
(1/0 OR CONTROL)
Figure 12. Port 3
addresses 2048-2065, where 3-byte jump absolute instructions are located (See Figure 4).
These jump instructions each contain a I-byte
opcode and a 2-byte starting address for the
interrupf service routine. The Z8682 takes 36
system clock cycles to enter an interrupt
subroutine.
Table 1. Z8682 Interrupt Processing
Address
(Hex)
Contains Jump Instruction and
Subroutine Addr.ess For
SOO-S02
S03-S05
S06-S0S
S09-SOB
SOC-SOE
BOF-Sll
IRQO
IRQl
IRQ2
IRQ3
IRQ4
IRQS
Polled interrupt systems are also supported.
To accommodat~ a polled structure, any or all
of the interrupt inputs can be masked and. the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Iii
AT cut, parallel-resonant
III
Fundamental type
II
Series resistance, Rs ::s; lOOn
• For Z8681/Z8682, 8 MHz maximum
.. For Z8681/Z8682-12, 12 MHz maximum
"This feature differs in the 28681 and 28682
2194-010, 011
549
Power Down
Standby
Option
The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available only to the user as a bonding
option whereby pin 2 (normally XTAL2) is
replaced by the VMM (standby) power supply
input. This necessitates the use of an external
clock generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. Figure 13 shows
the recommended circuit for a battery back-up
supply system.
Z8681/Z8682
Although the 28681 and 28682 have minor
Interdifferences, a system can be designed for comchangeability patibility with both ROMless versions. To
achieve interchangeability, the design must
take into account the special requirements of
each device in the external interface, initialization, and memory mapping.
External Interface. The 28682 requires a
7.5 V positive logic level on the RESET pin for
at least 6 clock periods immediately following
reset, as shown in Figure 14. The 28681 requires a 3.8 V or higher positive logic level,
but is compatible with the 28682 RESET
waveform. Figure 15 shows a simple circuit for
generating the 7.5 V level.
7.35 TO 8.0 V
,----"""TX- - - - -
VRH
+5 V o------..--~ Vee
Z8661/62
MCU
Figure 13. Recommended Driver Circuit for
Power-Down Operation
Initialization. The 28681 wakes up after reset
with Port 0 configured as an input, which
means Port 0 lines·are floating in a highimpedance state. Because of this pullup or
pulldown, resistors must be attached to Port 0
lines to force them to a valid logic level until
Port 0 is configured as an address port.
Port 0 initialization is discussed in the section on ports. An example of an initialization
routine for 28681128682 compatibility is shown
in Table 2. Only the 28681 need execute this
program.
Table 2. Initialization Routine
Address Opcodes Instruction
OOOC
E6 00 00
LD PO #%00
OOOF
E6 F8 96
LD POlM #%96 Configure Port 0 as
AS-AI5. Eliminate extended memory timing.
0012
8D 0812
IP START
ADDRESS
\
'- -- -
3.8V MIN
Comments
Set AS-AI5 to O.
-VRH
Execute application
program.
/
VRL----'
65536
4
6
MAX
MIN
APPLICATION
PROGRAM
.. ~r~~" -- ~r~~.Figure 14. Z8682 RESET Pin Input Waveform
+V
2066
A.P. PROG START ADDRESS
2063
JP IR05
2060
JP IR04
2057
JP IR03
2054
JP IR02
2051
JP IROl
2048
JP IROO
Z8682 VECTORS
JUMP INSTRUCTIONS
2047
NOT USED
21
18
15
15H
JP %0812
LD P01M
~%96
12
LD PO #%00
10
IROS
I
Z8681
INITIALIZATION
IR04
Z8681
)---~---I RESET
7.35 - 8.0 V
OR
Z8682
OPEN
COLLECTOR
TTL GATE
Figure 15. RESET Circuit
550
IR03
IR02
Z8681
VECTORS
IROl
IROO
Figure 16. Z8681/82 Logical Program Memory Mapping
2194-012, 013, 014, 015
Z86811Z8682
Interchangeability
(Continued)
Memory Mapping. The 28681 and 28682
lower memory boundaries are located at 0 and
2048, respectively. A single program ROM can
be used with either product if the logical program memory map shown in Figure 16 is
followed. The 28681 vectors and initialization
17FF
routine must be starting at address 0 and the
28682 3-byte vectors (jump instructions) must
beat address 2048 and higher. Addresses in
the range 21-2047 are not used. Figure 17
shows practical schemes. for implementing this
memory map using 4K and 2K ROMs.
6K
APPLICATION
PROGRAM
-
1015
1014
CHIP SELECT =
NOT USED
1000
(.\12 + Ali) • Al3 • A4' Als
FFF
4K
FFF
APPLICATION
PROGRAM
812
811
812
811
Z8682 VECTORS
800
800
2K
7fF
7FF
~
NOT USED
15
14
N
15
14
za681 VECTORS
AND INITIALIZATION
00
en
...
00
0
LOGICAL
MEMORY
PHYSICAL
MEMORY
00
N
a. Logical to Physical Memory Mapping for 4K ROM
:I
6
d
FFF
APPLICATION
PROGRAM
CHIP SELECT =
835
834
NOT USED
A10
As
820
81F
APPLICATION
PROGRAM
812
811
Z8682 VECTORS
r--
Ali • Ai2 • A13 • ~ .A;5
:0--
A TO ROM
s
-
7FF
35
34
800
7FF
20
IF
NOT USED
~
12
15
14
Z8681 VECTORS
AND INITIALIZATION
11
rPHYSICAL
MEMORY
LOGICAL
MEMORY
b. Logical to Physical Memory Mapping for 2K ROM
Figure 17. Practical Schemes for Implementing Z8681 and Z8682 Compatible Memory Map
Instruction
Set
Notation
Addressing Modes. The following notation is used
to describe the addressing modes and instruction
operations as shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
IR
Ir
RR
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working register pair address
Symbols. The following symbols are used in
describing the instruction set.
dst
Destination location or contents
2194-016
src
cc
Source location or contents
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
FLAGS Flag register (control register 252)
RP
Register pointer (control register 253)
IMR
Interrupt mask register (control register 251)
Assignment of a value is indicated by the symbol
\\-". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation \\addr(n)" is used
to refer to bit \\n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
551
Instruction
Set
Notation
(Continued)
Flags. Control Register R252 contains the following
six flags:
C
Z
S
V
D
H
Condition
Codes
Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
*
X
Mnemonic
Value
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
Flags Set
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or 'equal
Never true
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
1111
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
Meaning
C
NC
Z
NZ
PL
0111
1011
0011
0000
Affected flags are indicated by:
o
Instruction
Formats
S = a
S = 1
V
V
= 1
=
a
Z = 1
Z = a
(S,XOR V) = a
(S XOR V) = 1
[Z OR (S XOR V)] = a
[Z OR(S XOR V)] = 1
c=o
C = 1
(C = a AND Z = 0)
,(C OR Z) = 1
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dst
C
1
C = a
Z =1
Z = 0
INCr
OPC
One-Byte Instruction
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
CLR, CPL, DA, DEC,
OR
DECW, tNC, INCW, POP,
11 1 1 01 dsl/src 1 PUSH,
RL, RLC, RR,
RRC, SRA, SWAP
OPC
dst
I
OR
11 1 101
JP, CALL (Indirect)
dst
OPC
VALUE
I-~~:=--l
OR j11 1 0
I
dst
ADC, ADD, AND, CP,
LD, OR, sec, SUB,
TCM, TM, XOR
SRP
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD
LD, LDE, LDEI,
LDC, LOCI
OR
I
dst
OPC
VALUE
Id.tlCC~~
OPC
It 1 1 01
LO
JP
arc
LO
CALL
DJNZ, JR
Two-Byte Instruction
Three-Byte Instruction
Figure 18. Instruction Formats
552
2037-013
Instruction
Summary
Addr Mode
ADC dst,src
dst - dst + src + C
(Note 1)
10
* * * * 0 *
ADD dst,src
dst - dst + src
(Note 1)
00
* 0 *
AND dst,src
dst - dst AND src
(Note 1)
50
-**0--
CALL dst
DA
IRR
SP - SP - 2
@SP - PC; PC - dst
D6
D4
------
CCF
C - NOT C
EF
* - - - - -
clst
arc
Addr Mode
Instruction
and Operation
Opcode Flags Affected
Byte
(Hex) CZSVDH
dst
src
r
Irr
Irr
82
92
------
LDE! dst,src
Ir
dst - src
Irr
r - r + 1; rr - rr + 1
Irr
Ir
83
93
------
LDE dst,src
dst - src
NOP
FF
------
OR dst,src
dst - dst OR src
(Note 1)
40
-**0--
POP dst
dst - @SP
SP - SP + 1
R
IR
50
51
------
70
71
------
CLR dst
dst - 0
R
IR
BO
Bl
------
PUSH src
SP - SP -1; @SP- src
COM dst
dst - NOT dst
R
IR
60
61
- * * 0 - -
RCF
C-O
CF
0-- - - -
CP dst,src
dst - src
(Note 1)
RET
PC - @SP; SP - SP + 2
AF
------
DA dst
dst - DA dst
R
IR
40
41
* X- -
RL dst
~I~
90
91"
DEC dst
dst - dst - 1
R
IR
00
**--
RLC dst
l&-i, .~ I~
10
RR dst
~y,
'~I~
EO
El
RRC dst
LE1=ciJ IRR
CO
Cl
DECW dst
dst - dst - 1
AD
01
RR
IR
80
81
DI
IMR (7) - 0
DINZ r,dst
RA
r - r- 1
if r
0
PC - PC + dst
Range: + 127, -128
*"
- *
-***--
8F
------
rA
r=O-F
------
c
,
SBC dst,src
dst - dst - src - C
20
* * * * 1 *
FO
Fl
X * *X- -
IR
TCM dst,src
(NOT dst) AND src
(Note 1)
60
-**0--
TM dst, src
dst AND src
(Note 1)
70
-**0--
(Note 1)
BO
-**0--
IRET
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP+ 2; IMR(7) -1
* * * * * *
IP cc,dst
if cc is true
PC - dst
cD
c=O-F
30
------
IRR
XOR dst,src
dst - dst XOR src
JR cc,dst
RA
cB
c=O-F
------
Noto 1
r
X
X
r
Ir
r
R
IR
1M
1M
R
r
Ir
R
R
R
IR
IR
LDC dst,src
r
Irr
dst - src
LDCI dst,src
Ir
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Irr
Ir
SWAPdst~ R
------
C2
D2
------
C3
D3
------
* * 1 *
(Note 1)
- * * *- -
rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
3D
------
AO
Al
1m
R
(Note 1)
CI
31
RR
IR
r
r
R
•
1m
SUB dst,src
dst - dst - src
LD dst,src
dst - src
~
ac
n
***0--
- * * *- -
if cc is true,
PC - PC + dst
Range: + 127, -128
CO
11
DO
Dl
rE
r=O-F
20
21
DA
CO
~
SRA dst L{ri~R
IR
R
IR
INCW dst
dst - dst +
ro
1 - - - - -
SRP src
RP - src
These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode
nibble is found in the instruction set table above. The
second nibble is express~d symbolically by a 0 in this
table, and its value is found in the follOWing table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction using the addreSSing modes r (destination) and
Ir (source) is 13.
Addr Mode
dst
src
R
R
R
IR
Ir
R
IR
1M
1M
N
."
DF
9F
INC dst
dst - dst + 1
R
IR
SCF
C-l
------
EI
IMR (7) - 1
8085-003
Opcodo Flags Affected
Byte
(Hex) CZSVDH
Instruction
and Operation
Lower
Opcode Nibble
[l]
rn
[i]
@]
@)
rn
553
Registers
R244 TO
Counter/Timer 0 Register
(F4H ; ReadIWrite)
R240 SIO
Serial 1/0 Register
(FOH ; ReadlWrite)
L-----SERIAL DATA (Do
= LSB)
'R241 TMR
Time Mode Register
(FI H ; ReadlWrite)
NOT TouJMODES
USED .. 00
~o g~~
: ~~
R245 PREO
Pres caler 0 Register
(F5H ; Write Only)
Ij~~O=NOFUNCTION
-.J,
l
1 .. LOAD To
0
1
0
1
0
1
INTERNAL CLOCK OUT .. 11
T MODES
EXTERNAL CLOCK IN~OT .. 00
GATE INPUT· 01
(NON.~~k~g~:~~:~~ • 10
TRIGGER INPUT. 11
(RETRIGGERABLE)
..
..
..
..
..
..
DISABLE To COUNT
ENABLE To COUNT
NO FUNCTION
LOAD Tt
DISAIILE Tt COUNT
ENABLE Tt COUNT
R242 TI
Counter Timer 1 Register
(F2H; ReadlWrite)
COUNTMODE
o .. To SINGLE·PASS
1 .. To MODULO·N
RESERVED (MUST BE 0)
PRESCALER MODULO
L------(RANGE: 1-64 DECIMAL
01-00 HEX)
R246 P2M
Port 2 Mode Register
(F6 H ; Write Only)
P20-P2, I/O DEFINITION
L-_ _ _ _ 0 DEFINES BIT AS OUTPUT
1 DEFINES'BIT AS INPUT
T t INITIAL VALUE (WHEN WRITTEN)
L-----(RANGE 1-256 DECIMAL 01-00 HEX)
T t CURRENT VALUE (WHEN READ)
R243 PREl
Prescaler 1 Register
(F3H; Write Only)
R247 P3M
Port 3 Mode Register
(F7 H ; Write Only)
I~I~I~I~I~I~I~I~I
~
COUNTMODE
1 = T MODULO·N
o ..
t
Tt SINGLE·PASS
CLOCK SOURCE
1 = Tt INTERNAL
o = Tt EXTERNAL
TIMING INPUT
(T,N) MODE
PRESCALER MODULO
L-------(RANGE: 1-64 DECIMAL
01-00 HEX)
~~
O1 PORT
2 PULL,UPS OPEN DRAIN
PORT 2 PULL·UPS ACTIVE
RESERVED (MUST BE 0)
o P32 = IN PUT
=
P3s
OUTPUT
1 P32 = IlAVO/RDYO P3s = RDYO/1lAVO
o0
P33
~ ~}
= INPUT
P34
= OUTPUT
P33 = INPUT
P34 = D'M
P33
DAVl/RDY1 P34
RDY1/DAV1
11
=
=
'--------~ ~~: ~ ~N:VUJto~~ ~~: ~ ~~~~~UT)
L.-_~-----~ ~~~ ~ kN~~lL IN ~~~ ~ ~~~i'AULTOUT
'--________
~ ~~=:~~ g~F
Figure 19. Control Registers
554
2037-014
R248 POIM
'Port 0 Register
(F8 H ; Write Only)
Registers
(Continued)
-.J
PO.-PO, =M
OUTPUT
00O D E : ]
INPUT = 01
A12 -A,s .. IX
R252 FLAGS
Flag Register
(FC H ; Read/Write)
~~
'
L
_
EXTERNAL
MEMORY TIMING
NORMAL = 0
'EXTENDED = 1
LUSERFLAGFl
~~~
PO.-PO.
MODE
00 = OUTPUT
01 = INPUT
IX = A.-A"
LUSER FLAG F2
.
STACK SELECTION
0 = EXTERNAL
1 = INTERNAL
RESERVED (MUST BE 0)
HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
L . . . - - - - - - - - C A R R Y FLAG
'ALWAYS EXTENDED TIMING AFTER RESET
R2491PR
Interrupt Priority Register
(F9H ; Write Only)
R253 RP
Register Pointer
(FDH ; Read/Write)
0,1 0.1 0 0.1 D. \ O 0, ID. I
INTERRUPT GROUP PRIORITY
RESERVED :OJ
RESERVED = 000
1
51
2\
I
IR03. IROS PRIORITY (GROUP A)
o = IROS > IR03
1 = IR03 > IROS
'---+-+--
IROO. IR02 PRIORITY (GROUP B)
o
IR02 > IROO - - - - - - - - '
1 = IROO > IR02
=
C > A> B
A > B> C
A> C > B
B> C > A
C> B > A
B> A> C
RESERVED
=
=
=
=
=
=
=
001
010
011
100
101
110
111
REGISTER
POINTER
IROI. IR04 PRIORITY (GROUP C)
o = IROI > IR04 - - - - - - - - '
1
IR04 > IROI
=
R250 IRQ
Interrupt Request Register
R254 SPH
Stack Pointer
(FAH ; Read/Write)
(FEH; Read/Write)
I~I~I~I~I~I~I~I~I
RESERVED (MUST BE o ) : : r -
c-=
IROO IROl ..
IR02 ..
IR03 ..
IR04 ..
IROS"
P32 INPUT (Do .. IROO)
P33 INPUT
P31 INPUT
P30 INPUT. SERIAL INPUT
To. SERIAL OUTPUT
Tl
R251lMR
Interrupt Mask Register
R255 SPL
Stack Pointer
(FBH ; Read/Write)
(FFH; Read/Write)
I~I~I~I~I~I~I~I~I
II
c-=
1 ENABLES IROO-IROS
IROO)
(00 =
L.....-------RESERVED (MUST BE 0)
' - - - - - - - - - 1 ENABLES INTERRUPTS
Figure 19, Control Registers (Continued)
2037-014
555
Z8681/82
Opcode
Lower Nibble (Hex)
Map
o
o
2
5
)(
6
III
;.
III
:Q
:9
1
.
z
III
C.
c.
8
~
9
A
B
C
D
E
F
6
5
1
8
9
A
B
C
D
E
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
DEC
ADD
ADD
ADD
ADD
ADD
ADD
LD
LD
DJNZ
JR
LD
JP
INC
Rl
IRl
fl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
rl,R2
r2, Rl
fl,RA
cc,RA
rl,IM
cc,DA
fl
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
RLC
RLC
ADC
ADC
ADC
ADC
ADC
ADC
Rl
IRl
rl, r2
r l,Ir2
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
Rl
IRI
rl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
8,0
6,1
6,5
6,5
10,5
10,5
10,5
10,5
JP
SRP
SBC
SBC
SBC
SBC
SBC
IRRI
1M
SBC
rl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
DA
DA
OR
OR
OR
OR
OR
OR
Rl
IRl
rl, r2
rl,Ir2
R2,Rl
IR2,Rl
Rl,IM
IR1,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
POP
POP
AND
AND
AND
AND
AND
AND
Rl
IRI
rl, r2
rl,Irz
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
Rl
IRI
fl, fZ
rl,lrz
Rz,Rl
IR2,Rl
Rl,IM
IR1,IM
10/12,1 12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH PUSH
TM
TM
TM
TM
TM
TM
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
R2
IR2
rl, r2
rl,lrz
10,5
10,5
12,0
18,0
DECW DECW LDE
IRl
fl,Irr2
Ir I, Irr2
6,5
6,5
12,0
18,0
LDE
LDEI
RL
RL
Rl
IRl
10,5
10,5
r---
-
-
r---
r---
r--6,1
DI
r--6,1
EI
r2,Irrl Ir2, Irfl
6,5
INCW INCW
6,5
10,5
10,5
10,5
CP
CP
CP
CP
CP
IRl
rl, r2
rl,Irz
R2,Rl
IRZ,Rl
Rl,IM
IRl,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
CLR
XOR
XOR
XOR
XOR
XOR
XOR
Rl
IRl
rl, r2
rl,Irz
R2,Rl
IR2,Rl
Rl,IM
IRl,IM
6,5
6,5
12,0
18,0
RRC
RRC
LDC
LDCI
Rl
IRI
6,5
12,0
18,0
SRA
LDC
LDCI CALL·
Rl
IRl
6,5
6,5
20,0
20,0
10,5
CALL
LD
DA
rz, x, Rl
10,5
10,5
IRRI
10,5
10,5
RR
RR
LD
LD
LD
LD
LD
Rl
IRI
rl,IRz
R2,Rl
IRz,Rl
Rl,IM
IR1,IM
8,5
8,5
6,5
IRl
V'
LD
R2,IRl
2
-
RCF
6,5
SCF
t--6,5
CCF
r--6,0
LD
'"
IRET
6,5
10,5
Irl, r2
,.I
-
LD
6,5
SWAP SWAP
RET
- 16,0
rl, x, Rz
SRA
6,5
14,0
10,5
rl,lrrz Irl,lrrz
rz,Irrl Irz,lrrl
>----
10,5
CP
RRI
'"
F
r---
LDEI
RRI
Rl
Bytes per
Instruction
4
3
DEC
3
4
2
V'
3
1
,/
NOP
'"~--------~~~----------~~ ~ ~
2
3
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode-' A
~
Pipeline
Cycles
Mnemonic
Legend:
R = 8-Bit Address
r = 4-Bit Address
HI or rl = Dst Address
Hz or rz = Src Address
~Ibble
First
Operand
Second
Operand
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined_
*2-byte instruction; fetch cycle appears as a 3-byte instruction
556
8085-002
Absolute
Maximum
Ratings
Voltages on all pins*
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C
Standard
Test
Conditions
• GND = 0 V
• O°C :s; TA :s; +70°C for S (Standard
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
m +4.75 V
:s; Vee ~
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indiCated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
temperature)
g -40°C :s; TA S + 85°C for E (Extended
temperature)
+5.25 V
+SV
+SV
2.1K
+sv
1.Sk
14LS04
1.Sk
14LS04
N
CO
en
...
-=
CO
XTAL1
Figure 20. Test Load 1
DC
Characteristics
Symbol
iI
"CI
Figure 21. External Clock Interface Circuit
Parameter
Min
Max
Unit
VeH
Clock Input High Voltage
3.8
Vee
V
Driven by External Clock Generator
VeL
Clock Input Low Voltage
-0.3
0.8
V
Driven by External Clock Generator
VIH
Input High Voltage
2.0
Vee
V
VIL
Input Low Voltage
-0.3
0.8
V
VRH
Reset Input High Voltage
3.8
Vee
V
VRL
Reset Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
IlL
Input Leakage
10L
Output Leakage
1m
2.4
Condition
See Note
= -250 p.A
V
IoH
0.4
V
-10
10
p,A
= +2.0 rnA
o v's VIN S +5.25 V
-10
10
p.A
o Vs
Reset Input Current
-50
p.A
Vee
lee
Vee Supply Current
180
rnA
IMM
VMM Supply Current
10
rnA
VMM
Backup Supply Voltage
3
Vee
V
IoL
VIN s +5.25 V
= .+5.25 VI
VRL
=0V
Power Down Mode
Power Down
NOTE:
The Reset line (pin 6) is used to place the 28682 in external memory mode. This is accomplished as shown in Figure
14 .
•Except RESET Pin 6
8085-0313, 2037-015
557
External 1/0
or Memory
Read and
Write Timing
RlW
PORT 0,
DM
PORT 1
As
os
(READ)
PORT 1
AfJ-A7
os
(WRITE)
Figure 22. External I/O or Memory Read/Write Timing
No.
Symbol
TdA(AS)
1
TdAS(A)
2
TdAS(DR)
3
4
TwAS
TdAz(DS)
5
6-TwDSR
Parameter
Address Valid to AS t Delay
AS t to Address Float Delay
AS t to Read Data Required Valid
AS Low Width
Address Float to DS ,
DS (Read) Low Width
DS (Write) Low Width
DS , to Read Data Required Valid
NOTES:
1. Test Load 1
2. Timing numbers given are for minimum TpC.
3. Also see clock cycle time dependent characteristics table.
4. When using extended memory timing add 2 TpC.
558
Z8681/82
8 MHz
Min
Max
12MHz
Min
Max
50
70
35
45
220
360
TwDSW
TdDSR(DR)
ThDR(DS)
Read Data to DS t Hold Time
TdDS(A)
10
DS t to Address Active Delay
TdDS(AS)
DS t to AS , Delay
11
12-TdRlW(AS)--RlW Valid to AS t Delay
TdDS(R/W)
13
DS t to R/W Not Valid
TdDW(DSW)
14
Write Data Valid to DS (Write) , Delay
TdDS(DW)
15
DS t to Write Data Not Valid Delay
TdA(DR)
16
Address Valid to Read Data Required Valid'
TdAS(DS)
AS t to DS , Delay
17
7
8
9
Z8681/82
55
0
185
80
0
250
160
110
200
130
0
45
55
30
35
35
45
0
70
·70
50
60
50
70
255
410
80
55
Notes*t
1,2,3
1,2,3
1,2;3,4
"1,2,3
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3,4
1,2,3
5. All timing references use 2.0 V for a logic "1" and 0.8 V for a logic "0".
• All units in nanoseconds (ns).
t Timings are preliminary and subject to change.
2194-017
Additional
Timing
Table
CLOCK
Till
Figure 23. Additional Timing
Z8681/82
No.
2
Parameter
8MHz
Min
Max
TpC
Input Clock Period
125
TrC,TfC
Clock Input Rise And Fall Times
Symbol
3
TwC
TwTinL
4
5--TwTinH
Input Clock Width
1000
Z8681182
12MHz
Min
Max
83
25
Timer Input Low Width
Timer Input High Width
37
100
3TpC
TpC
26
70
3TpC
TpC
S-
S-
6
TpTin
Timer Input Period
7
TrTin, TfTin
Timer Input Rise And Fall Times
8
9
TwIL
TwIH
Interrupt Request Input Low Time
Interrupt Request Input High Time·
100
100
3TpC
Notes*;
1000
15
N
00
2
2
2
100
70
3TpC
2
2,3
2,3
NOTES:
1. Clock timing references uses 3.8 V for a logic "1" and 0.8 V for
a logic "0".
2. Timing reference uses 2.0 V for a logic "1" and.o.8 V for
a logic "0".
2194-018
3. Interrupt request via Port 3.
* Units in nanoseconds (ns).
t Timings are preliminary and subject to change.
559
'"
...CO
00
~
ac
n
d
Handshake
Timing
DATA IN
DAV
(INPUT)
RDY
(OUTPUT)
Figure 24a. Input Handshake Timing
r-
DATA OUT
DATA OUT VALID
7.
------'~-----
\)\O--~C:9
~
0)---~ ~
DAV
(OUTPUT)
RDY
(INPUT)
Figure 24b. Output Handshake Timing
No.
Symbol
Z8681182
8 MHz
Min
Max
Parameter
Z8681/82
12MHz
Min
Max
TsDI(DAV)
Data In Setup Time
0
0
2
ThDI(DA V)
Data In Hold Time
230
160
3
TwDAV
Data Available Width
175
4
TdDAVIf(RDY)
DAV I Input to RDY I Delay
6
TdDAVIr(RDY)
DAV I Input to RDY I Delay
7
TdDAVOrRDY)
DAV I Output to RDY I Delay
8
TdDO(DAV)
Data Out to DAV I Delay
9
TdRDY(DAV)
Rdy I Input to DA V I Delay
NOTES:
1. Test load I
2. Input handshake
3. Output handshake
4. All timing regerences use 2.0 V for a logic "I" and 0.8 V for
a logic "0".
ClockCycle-TimeDependent
Characteristics
120
175
5-TdDAVOf(RDY)-DAV I Output to RDY I Delay
120
175
0
120
50
1,2
1,3
0
30
200
0
140
• Units in nanoseconds (ns).
r Timings are preliminary and subject to change.
Z8681/82
12 MHz
Equation
TpC-50
Symbol
Z8681182
8 MHz
Equation
1
TdA(AS)
TpC-75
2
TdAS(A)
TpC-55
TpC-40
3
TdAS(DR)
4TpC-140*
4TpC-110*
Number
1,2
0 ------1,3
0
0
Notes*t
4
TwAS
TpC-45
TpC-30
6
TwDSR
3TpC-125*
3TpC-65*
7
TwDSW
2TpC-90*
2TpC-55*
8
TdDSR(DR)
3TpC-175*
3TpC-120*
10
Td(DS)A
TpC-55
TpC-40
11
TdDS(AS)
TpC-55
TpC-30
12
TdR/W(AS)
TpC-75
TpC-55
13
TdDS(R/W)
TpC-65
TpC-50
14
TdDW(DSW)
TpC-75
TpC-50
15
TdDS(DW)
TpC-55
TpC-40
16
TdA(DR)
5TpC-215*
5TpC-160*
17
TdAS(DS)
TpC-45
TpC-30
• Add 2TpC when using extended memory timing
560
2194-019
Ordering
Information
Product
Number
Package/
Speed
Temp
Z8681
CE
8.0 MHz
Description
Z8MCU
(ROMless, 40-pin)
Product
Number
Package/
Speed
Temp
Z8681
CE
12.0 MHz
Description
Z8MCU
(ROMless, 40-pin)
Z8681
CS
8.0 MHz
Same as above
Z8681
CS
12.0 MHz
Same as above
Z8681
DE
8.0 MHz
Same as above
Z8681
DE
12.0 MHz
Same as above
Z8681
DS
8.0 MHz
Same as above
Z8681
DS
12.0 MHz
Same as above
Z8681
PE
8.0 MHz
Same as above
Z8681
PE ,
12.0 MHz
Same as above
Z8681
PS
8.0 MHz
Same as above
Z8681
PS
12.0 MHz
Same as above
Z8682
PE
8.0 MHz
Same as above
Z8682
PS
8.0 MHz
Same as above
Z8682
Z8682
PE
PS
12.0 MHz
12.0 MHz
Same as above
Same as above
NOTES: C = Ceramic, D = Cerdip, P = Plastic; E = -40°C to +85°C, S = O°C to +70°C.
NOTE: The Z8681 is available in the low power standby option. If this option is desired, a 28685 part number should be specified. All other data
remains the same for ordering purposes.
561
Z8@ Family of
Universal Peripheral
«:cnll'laDBlam
Zilog
Product
Specification
September 1983
Non-Multiplexed Bus
Z8590-2K HOM
Z8594-PROM/RAM Protopack
Z-BUS
Z8090-2K ROM
Z8094-PROMIRAM Potopack
Features
Ell Complete slave 28 microcomputer, for
each with a 6-bit prescaler. Counter/Timer
TO is driven by an internal source, and
Counter/Timer Tl can be driven by internal
or external sources. Both counter/timers are
independent of program execution.
distributed processing use.
S Unmatched power of 28 architecture and
instruction set.
II
C
I!IJ
General
Description
Three programmable I/O ports, two with
optional 2-Wire Handshake.
Six levels of priority interrupts from eight
sources: six from external sources and two
from internal sources.
Two programmable 8-bit counter/timers
The Universal Peripheral Controller
(UPC) is an intelligent peripheral controller
for distributed processing applications (Figure
1). The upe unburdens the host processor by
assuming tasks traditionally done by the host
(or by added hardwarE!) , such as performing
arithmetic, translating or formatting data, and
controlling I/O devices. Based on tbe 28
microcomputer architecture and instruction
set, the UPC contains 2K bytes of internal program ROM, a 256-byte register file, three 8-bit
I/O ports, and two counter/timers.
The UPC is offered in two basic configurations:the 28090/4, which interfaces to
multiplexe~ address/data CPUs such as the
[J
[J
256-byte register file, accessible by both the
master CPU and UPC, as allocated in the
UPC program.
2K bytes Of on-chip ROM for efficiency and
versatility.
28000, and the 28590/4, which interfaces with
non-multiplexed CPUs such as the 280. Both
devices have the same instruction set and I/O
port configuration. The difference in the
devices is in the UPC-to-host interface pins
and the sequence of data transfer between the
units.
The UPC offers fast execution time, an
effective use of memory, and sophisticated
interrupt, I/O, and bit manipulation. Using
a powerful and extensive instruction set
combined with an efficient internal
addressing scheme, the UPC speeds
program execution and efficiently packs
program code into the on-chip ROM.
563
General
Description
(Continued)
An important feature of the UPC is an internal register file containing I/O port and control registers accessed both by the UPC program and indirectly by its associated master
CPU. This architecture results in both byte
and programming 'efficiency, because UPC
instructions can operate directly on I/O data
without moving it to and from an accumulator.
Such a structure allows the user to allocate as
many general-purpose registers as the applica,tion requires for data buffers between the CPU
and peripheral devices. All general-purpose
registers can be used as address pointers,
index registers, data buffers, or stack space.
The register file is logically divided into 16
groups, each consisting of 16 working
registers. A Register Pointer is used in conjunction with short format instructions,
resulting in tight, fast code and easy task
sWitching.
Communication between the master CPU
and the register file takes place via one group
of 19 interface registers addressed directly by
both the master CPU and the UPC, or via a
block transfer mechanism. Access by the
master CPU is controlled by the UPC to allow
HOST CPU
INTERFACE
Z8D90
Z8590
ADo-AD,
DBo-DB,
As
BUS TO
MASTER
CPU
independence between the master CPU and
UPC software.
The UPC has 24 pins that can be dedicated
to I/O functions. Grouped logically into three
8-line ports, they can be programmed in many
combinations of input or output lines, with or
without handshake, and with push-pull or
open-drain outputs. Ports 1 and 2 are bitprogrammable; Port 3 has four fixed inputs
and four outputs ..
To relieve software from coping with realtime counting and timing problems, the UPC
has two 8-bit hardware counter/timers, each
.with a fixed'divide-by-four, and ~ 6-bit programmable prescaler . Various counting modes
may be selected.
In addition to the 40-pin standard ROM configuration, the UPC is available in a Protopack
RAM/ROM version with a socket for up to 2K
bytes of RAM or ROM and with 36 bytes of internal ROM permitting downloading from the
master CPU.
This range of versions and configurations
makes the UPC compatible with most system
peripheral device control considerations.
Z8.UPC MICROCOMPUTER
AID
os
AD
Riw
Cs
ViR
WAIT
WAIT
110
Cs
iNT
iNT
INTACK
INTACK
lEI
lIil
lEO
lEO
Figure I. Functional Block Diagram
564
2017-087
Pin
Description
Z8090
Z-UPC
ADo-AD1' Z-Bus Address/Data Lines (bidirectional). These multiplexed address and data
lines are used to transfer information between
the master CPU and the slave Z- UPC.
AS. Address Strobe (input, active Low). The
rising edge of AS initiates the beginning of a
transaction and indicates that the Address,
Status, R/W, and CS signals must be valid.
P1o-PI1' Port 1 (input/output-as output it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
PCLK. Clock (input). TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.
P2o-P21' Port 2 (input/output-as output, it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
CS. ChipSelecf (input, active Low). A Low on
this line during the rising edge of AS enables
the Z- UPC to accept address or data information from the bus during a master CPU write
cycle or to transmit data to the bus during a
read cycle.
P30-P31' Port 3 (four inputs, four outputs).
Parallel I/O, handshake control, timer I/O, or
interrupt control.
DS. Data Strobe (input, active Low). DS
provides timing for data movement to the bus
master. A simultaneous Low on AS and DS
resets the Z- UPC. It is held in reset as long as
DS is Low.
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the Z- UPC register
file, this signal requests the master CPU to
wait until the Z- UPC can complete its part of
the transaction.
~ ~l~
Pls-
AD
2
AD
l
-ADo
Pll
ADDRESS,j
DATA BUS
_
TIM~~~
{
AND RESET
AD3
CONTROL {
os
=: ~
INTERR~~~ {
_
P21
P26
P2s
P24
Plo-
P23
3
Z8090
P3
P34
_}
P3l_
Z·UPC
P36
iNfOR P3s
INTACK OR P32
lEI OR P30
lEO OR P37
-
P3l
PORT 1
P12-
WAiT
MASTER
indicates that the master CPU is executing a
Read cycle if High, and a Write cycle if Low.
P36
P14
P13 -
AS
-
R/W. Read/Write (input). This status signal
1
Pl
_
P1
6 -)
-
+sv_
PCLK_
GND_
Figure 2. Pin Functions
2017-069, 095
P1o-PI1. P2o-P21' P30-P31' I/O Port Lines
(inputs/outputs, TTL-compatible). These 24
lines are divided into three 8-bit I/O ports and
may be configured in the following ways under
program control:
P22
PORT 3
P2l
P20
P33
P34
Pl1
P16
Pls
P14
P13
Ph
Pll
Pl0
Figure 3. Pin Assignments
565
Pin
Description
Z8590
UPC
AID. Address/Data (input). A Low on this pin
defines information on the data bus as an
address. A High defines the information
as data.
CS. Chip Select (input, active Low). A Low
enables the UPC to accept address or data
information from the master CPU during a
write cycle or to transmit data to the master
CPU during a read cycle. This line is usually
generated from higher bits of the address
,lines.
DBo-DB.,. Data Bus (bidirectional). This bus is
used to transfer address and data information
between the master CPU and the UPC.
Plo-PI7. P2o-P27. P30-P37' I/O Port Lines
(bidirectional, TTL-compatible). These 24 lines
are divided into three 8-bit I/O ports and may
be configured in the following ways under program control:
Plo-PI7' Port 1 (input/output-as output it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
~ ~1~
TI:'~: {
AND RI!SI!T
P12-
-OBI
Pl1
-OBo
P10-
PORT 1
40
1
Z~:~O
39
P3s
lEO OR P3l
38
P2l
37
P2a
P2s
as
P3 _ }
P34
P31_
PORT 3
P3s
_
INTACK OR P32
-
,lEI OR P30
lEO OR P3l
P31
PCLK
3
iNT OR P3s
MASTER
WH. Write (input, active Low). A Low on this
pin enables the master CPU to write information to the UPC. A simultaneous Low on RD
and WR resets the UPC. It is held in reset as
long as WR is Low.
38
35
WAIT
INTERR~:~ {
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the UPC register file,
this signal requests the master CPU to wait
until the UPC can complete its part of the
transaction.
+5V
P1e-
-OB2
CONTROL { -
active Low). A Low enables
the master, CPU to read information from the
UPC. Raising the voltage on this pin above
VDD will force the UPC into test mode.
7
P14
P13-
AID
~ Rli
-Wli
RD. Read (input,
P1
P l_
e _)
OB3
DATAl
BUS
_
P2o-P27' Port 2 (input/output-as output, it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P30-P37' Port 3 (four inputs, four outputs).
Parallel I/O, handshake control, tiqler I/O, or
interrupt control.
PCLK. Clock (input). TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.
Z8590
UPC
P24
34
P23
33
P22
32
P21
31
P20
30
P33
P34
Pll
PIa
PIS
+5V_
PCLK_
GNO_
~igure
566
4. Z8590 UPC Pin Functions
Pl0
Figure 5. Z8590 UPC Pin Assignments
2017-068, 095
Functional
Description
Address Space. On the 40-pin UPC, all
address space is committed to on-chip
memory. There are 2048 bytes of maskprogrammed ROM and 256 bytes of register
file. I/O is memory-mapped to three registers
in the register file. Only the Protopack version
of the UPC can access external program
memory. See the section entitled "Special
Configurations" for a complete description of
the Protopack version.
Program Memory. Figure 6 is a map of the 2K
on-chip program ROM. Even though the architecture allows addresses from 0 to 4K, behavior of the device above program address 2047
(7FFH) is not defined. The first 12 bytes of program memory are reserved for the UPC
interrupt vectors. In the RAM version, addresses OCH through 2FH are reserved for onchip ROM.
20 47
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED AFTER
RESET
USER
ROM
'I'-..
12
11
"
Register File. This 256-byte file includes three
I/O port registers (1-3H), 234 general-purpose
registers (6-EFH), and 19 control, status and
special I/O registers (OH, 4H, 5H, and
FO-FFH). The functions and mnemonics
assigned to these register address locations
are shown in Figure 7. Of the 256 UPC
registers, 19 can be directly accessed by the
master CPU; the others are accessed indirectly
via the block transfer mechanism.
IDENTIFIER
(UPC Side)
LOCATION
FFH
STACK POINTER
SP
FEH
MASTER CPU INTERRUPT CONTROL
MIC
FDH
REGISTER POINTER
RP
FCH
PROGRAM CONTROL FLAGS
FLAGS
FBH
UPC INTERRUPT MASK REGISTER
IMR
FAH
UPC INTERRUPT REQUEST REGISTER
F9H
UPC INTERRUPT PRIORITY REGISTER
IPR
F8H
PORT 1 MODE
P1M
F7H
PORT 3 MODE
P3M
F6H
PORT 2 MODE
P2M
IRQ
F5H
To PRESCALER
F4H
TIMER/COUNTER 0
To
F3H
Tl PRESCALER
PRE1
F2H
TIMER/COUNTER 1
Tl
F1H
TIMER MODE
TMR
FOH
MASTER CPU INTERRUPT VECTOR REG.
MIV
00
m
~
to
~
PREO
~
CJ
tJ
r.lr
00
00
EFH
IRQ5 LOWER BYTE
10
IRQ5 UPPER BYTE
9
IRQ4 LOWER BYTE
8
IRQ4 UPPER BYTE
7
IRQ3 LOWER BYTE
6
IRQ3 UPPER BYTE
5
IRQ2 LOWER BYTE
4
IRQ2 UPPER BYTE
3
IRQ1 LOWER BYTE
2
(II
=
to
GENERAL-PURPOSE REGISTERS
~
eJ
6H
5H
DATA INDIRECTION REGISTER
4H
LIMIT COUNT REGISTER
LC
3H
PORT 3
P3
PORT 2
P2
2H
ro
DIND
IRQ1 UPPER BYTE
lH
PORT 1
P1
1
IRQO LOWER BYTE
OH
DATA TRANSFER CONTROL REGISTER
DTC
0
IRQO UPPER BYTE
6
Figure 7. Rogistor File Organization
Figure 6. Program Memory Map
2017-001, 002
567
Functional
Description
(Continued)
The 1/0 port and control registers are
included in the register file without differentiation. This allows any UPC instr~ction to
process 1/0 or control information, thereby
eliminating the need for special 1/0 and control instructions. All general-purpose registers
can function as accumulators, address
pOinters, or index registers. In instruction execution, the registers are read when they are
defined as sources and written when defined as
destinations.
UPC instructions may access registers
directly or indirectly using an 8-bit address
mode or a 4-bit address mode and a Register
Pointer. For the 4-bit addressing mode, the file
is divided into 16 working register groups,
each occupying 16 contiguous locations
(Figure 8). The Register Pointer (RP) addresses
the starting point of the active working-register
group, and the 4-bit register designator supplied by the instruction specifies the register
within the group. Any instruction altering the
contents of the register file can also alter the
Register Pointer .. The UPC instruction set has a
special Set Register Pointer (SRP) instruction
for initializing or altering the pointer contents.
Stacks. An 8-bit Stack Pointer (SP), register
R255, is used for addressin'g the stack,
residing within the 234 general-purpose
registers, address location 6H through EFH.
PUSH and POP instructions can save and
restore any register in the register file on the
stack. During CALL instructions, .the Program
Counter is automatically saved on the stack.
During UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the stack. The RET and IRET
instructions pop- the saved values of the Program Counter and Flag register.
-
THE 4·BIT REGISTER}
POINTER PROVIDES THE
UPPER NIBBLE OF THE
REGISTER FILE. ADDRESS
FOR THE 4·BIT ADDRESS
MODE.
(j
1 I
1
o
7SH 01110101
0 0 0
FFH
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
9FH
90H
8FH
80H
~
70H
6FH
60H
SFH
SOH
4FH
40H
3FH
30H
2FH
20H
1FH
10H
OFH
0
Figure 8. Register Pointer Mechanism
568
Ports. The UPC has 24 lines dedicated to
input and output. These are grouped into three
ports of eight lines each and can be configured under software control as inputs, outputs, or speCial control signals. They can be
programmed to provide Parallel 1/0 with or
without handshake and timing signals. All outputs can have active pullups and pulldowns,
compatible with TTL loads. In addition, Port 1
and 2 may be configured as open-drain outputs.
Port 1. Individual bits of Port 1 can be configured as input or output by programming
Port I Mode register (PIM) F8H. This port is
accessed by the UPC program as general
register IH. It is written by specifying address
IH as the destination of any instruction used to
store data in the output register. The port is
read by specifying address 1H as the source of
an instruction.
Port 1 may be placed under handshake control by programming Port 3 Mode register
(P3M) F7H. This configures Port 3 pins P33
and P34 as handshake control lines DA V} and
RDYI for input handshake, or RDY} and DAV}
for output handshake, as determined by the
direction (input or output) assigned to bit 7 of
Port 1. The Port 3 Mode register also has a bit
that programs Port 1 for open-drain output.
Port 2. Individual bits of Port 2 can be configured as inputs or outputs by programming
Port 2 Mode register (P2M) F6H. This port is
accessed by the UPC program as general
register 2H, and its functions and methods of
programming are the same as those of Port 1.
Port 3 pins P31 and P36 are the handshak~
lines DA V2 and RDY 2, with the direction (input
or output) determined by the state of bit 7 of
the port. The Port 3 Mode register also has a
bit used to program Port 2 for open-drain
output.
Function
{ '"'
cow,"
"""FILE
OF THE
REGISTER
ADDRESS (0101) IS
PROVIDED BY THE
INSTRUCTION.
Line Direction
Signal
P3l
P33
P34
P36
In
In
Out
Out
DAV2/RDY2
DAVI/RDYI
RDYl/DAVl
RDY2/DAV2
{
P30
P3l
P33
In
In
In
IRQ3
IRQ2
IRQl
Counter/Timer
{ P31
P36
In
Out
Master CPU
P3S
P32
P30
P37
Out
In
In
Out
T7N
TOUT
INT
INTACK
lEI
lEO
P3S
Out
AID
Handshake
{
UPC Interrupt
Request·
Test Mode
{
·P30. P3l. and P33 can always be used as UPC interrupt
request inputs. regardless of the configuration
programmed.
Table 1. Port 3 Control Functions
2017-003
Functional
Description
(Continued)
Port 3. This port can be configured as I/O or
II
control lines by programming the Port 3 Mode
register. Port 3 is accessed as general register
3H. The directions of the eight data lines are
fixed. Four lines, P30 through P33, are inputs,
and the other four, P34 through P37, are outputs. The control functions performed by Port
3 are listed in Table]
I!I External gate input for the UPC internal
clock divided by four.
TO is driven by the UPC internal clock
divided by four.
Interrupts. The UPC allows six interrupts from
eight different sources as follows:
Counter/Timers. The UPC contains two 8-bit
programmable counter/timers, each driven by
an internal 6-bit programmable prescaler.
The Tl prescaler can be driven by internal
or external clock sources. The TO prescaler is
driven by an internal clock source. Both
counter/timers operate independently of the
processor instruction sequence to relieve the
program from time-critical operations like
event counting or elapsed-time calculation. TO
Prescaler register (PREO) F5H and Tl Prescaler register (PREl) F3H can be programmed
to divide the input frequency of the source
being counted by any number from 1 to 64. A
Counter register (F2H or F4H) is loaded with a
number from 1 to 256. The corresponding
counter is decremented from this number each
time the prescaler reaches end-of-count. When
the count is complete, the counter issues a
timer interrupt request; IRQ4 for TO or IRQs
for Tl. Loading either counter with a number
(n) results in the interruption of the UPC at the
nth count.
The counters can be started, stopped,
restarted to continue, or restarted from the initial value. They can be programmed to stop
upon reaching end-of-count (Single-Pass
mode) or to automatically reload the initial
value and continue counting (Modulo-n Continuous mode). The counters and prescalers
can be read at any time without disturbing
their values or changing their counts. The
clock source for timer T 1 can be defined as
anyone of the following:
[J
Port 3 lines P30, P32, and P33.
II
The master CPU(3).
These interrupts can be masked and globally
enabled or disabled using Interrupt Mask
Register (IMR) FBH. Interrupt Priority Register
(IPR) F9H specifies the order of their priority.
All UPC interrupts are vectored.
Table 2 lists the UPC's interrupt sources,
their types, and their vector locations in program ROM. Interrupt Request IRQo is
dedicated to master CPU communications.
Interrupt Requests IRQl, IRQ2, and IRQ3 are
generated on the falling transitions of external
inputs P33, P3l, and P30. Interrupt Requests
IRQ4 and IRQs are generated upon the timeout
of the UPC's two counter/timers. When an
interrupt request is granted, the UPC enters an
interrupt machine cycle. This cycle disables all
subsequent interrupts, saves the Program
Counter and Status Flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
The UPC also supports polled" systems. To,
accommodate a polled structure, any or all of
the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Following any hardware reset operation, an
EI instruction must be executed to enable the
setting of any interrupt request bit in the
IRQ register. Interrupts must be disabled prior
to changing the content of either the IPR
(F9H) or the IMR (FBH). DI is the only instruction that should be used to globally disable
interrupts.
[] External clock input to Counter/Timer Tl
via P3l (l MHz maximum).
1:1 Retriggerable trigger input for the UPC
internal clock divided by four.
Source
II
iii The two counter/timers.
UPC internal clock (4 MHz maximum)
divided by four.
Name
Nonretriggerable trigger input for the UPC
internal clock divided by fqur.
Vector
Location
Comments
IRQo
EOM, XERR, LERR
IRQI
DAV I , IRQI
IRQ2
DAV2 , IRQ2' TIN
IRQ3
IRQ3' lEI
0,1
2,3
4,S
6,7
IRQ4
TO
8,9
Internal
IRQ5
Tl
10,11
Internal
Internal (RO Bits
(P33)
External (P31)
External (P30)
External
0, 1,
2)
I Edge Triggered
I Edge Triggered
I Edge Triggered
Table 2. Interrupt Types, Sources, and Vector Locations
569
\
Functional
Description
( Continued)
Master CPU Register File Access. There are
two ways in which the master CPU can access
the UPC register file: direct access and block
access.
Direct Access. Three UPC registers-the Data
Transfer Control (OH), the Master Interrupt
Vector (FOH), and the Master Interrupt Control
(FEH)-are mapped directly into the master
CPU address space. The master CPU accesses
these registers via the addresses shown in
Table 3.
The master CPU also has direct access to 16
registers known as the DSC (Data, Status,
Command) registers. The DSC registers are
numbered 0 through F (DSCO-DSCF). These
registers can be any 16 contiguous register file
registers beginning on a 16-byte boundary.
The base address of the DSC register group is
designated by the IRP (I/O Register Pointer),
which is bits D4-D7 of the Data Transfer Control register (OH). Figure 9 shows how the
register address is made up of the 4-bit IRP
field, concatenated with the low order 4-bits of
the address from the master CPU.
Block Access. The master CPU may transmit
or receive blocks of data via address xxxlO101.
When the master CPU accesses this address,
the UPC register pointed to by the Data
Indirection register is read or written. The
DTC REGISTER (OHI
lAP
Data Indirection register is incremented, and
the Limit Count register is decremented, for
example, when the master CPU issues a read
or write to address xxx10101 while the Data
Indirection register contains the value 33H.
The operation causes register 33H to be read
or written and the Data Indirection register to
be incremented to 34H. This scheme is well
suited to Block I/O Instructions and allows the
master CPU to efficiently read or write a block
of data to or from the UPC.
The Limit Count register (04H) is
decremented and is used to control the
number of bytes to be transferred by master
CPU block accesses. If the master CPU
attempts a read or write to the UPC after the
Limit Count register reaches 6, the access is
not completed, the LERR bit (D1) of the Data
Transfer Control register is set (ihdicating a
limit error), and the LERR error causes an
IROo interrupt request.
The IRP field of the Data Transfer Control
register, the Data Indirection register, and the
Limit Count register are not directly accessible
to the master CPU and therefore must be set
by the UPC. This allows the UPC to protect
itself from master CPU errors and frees the
master CPU from tracking the UPC's internal
data layout.
UPC Address
Decimal
Hex
~
0
OH
DIC
5H
DIND
@5H**
240
FOH
MIV
254
*n
FEH
MIC
xxxllllO
xxIII lOx
DSCO
xxxOOOOO
xxOOOOOx
n+l
DSCI
xxxOOOOI
xxOOOOlx
n+2
DSC2
xxxOO010
xxOOOlOx
n+3
DSC3
xxxOOO11
xxOOOllx
n+4
DSC4
xxxOOlOO
xxOOlOOx
n+5
DSC5
xxxOO 10 1
xxOO 10 1x
n+6
DSC6
xxxOOllO
xxOOllOx
xx00111x
IATI A61 A51 A41 A31 A21 A, IAo I
IRTI R61 R51 R41 R31 R21 R, IRo I
REGISTER
FILE
J.-
"The shift or no·shift state is set during a hardware reset. If the
Wait line is held High during the hardware reset, the 8090/4 is in
the shift state after the reset. If WAIT is held Low, it is in the no·
shift state. The shift state is maintained until the next hardware
reset. Figure 7 shows one way to interface the 8090/4 for the use
of no·shift.
Figure 9. DCS Register Addressing Scheme
570
xxx 11000
8090/4
Shift
Address
5
@5**
ADDRESS FROM CPU
I~~~'"'~'"
8090/4
8590/4
No-Shift
Identifier Address
xx11000x
xxx 10 10 1
xxlOlOlx
xxx 10000
xxlOOOOx
n+7
DSC7
xxx0011 1
n+B
DSCB
xxxOlOOO
xxOlOOOx
n+9
DSC9
xxx01001
xxOlO01x
n+ 10
DSCA xxxO 10 10
xxOl 0 lOx
n+ 11
DSCB
xxx01011
xxOlOl1x
n+ 12
DSCC xxx01100
xx01100x
n+ 13
DSCD
xxx01101
xxOl101x
n+ 14
DSCE
xxx011 10
xx01 1lOx
n+ 15
DSCF
xxx01111
xx01111x
x
= don't care
On is the value in the IRP x 16
""Master CPU accesses the register address in Register 5.
Table 3. Master CPU/UPC Register Map
2017-004
Special
Configura-'
tions
The Protopack version of the UPC is identical to the 40-pin ROM-based UPC with the
following exceptions:
c All but 36 bytes of internal ROM are omitted
from the Protopack RAM/ROM version.
• The memory address and data lines are buffered and brought out to the socket on the
Protopack. This socket uses a 2Kx8 RAM or
ROM.
The Protopack version of the UPC allows the
user to prototype the system in hardware with
an actual UPC device and to develop the code
intended to be mask programmed into the
on-chip ROM of the 40-pin UPC for the production system. The Protopack version of the
UPC is an extremely versatile part. RAM program memory can be used on the 40-pin Protopack with RAM/ROM for all but 36 bytes of
the UPC's memory space. This memory can
then be downloaded from the master CPU
using a bootstrap program stored in the 36
bytes (C-2F). Figure 10 is a memory map for
the RAM version. This package will also accept a ROM, provided that the area from C to
2F is not used for programming.
Using the Z8094/Z8594 with EPROM or
RAM. The 28094 2- UPC and the 28594 UPC
can be used with an EPROM or RAM plugged
into the socket on top of the 40-pin package.
Instructions for using a RAM are provided in
. Chapter 8 of the UPG Technical Manual
(document #00-2055-01). If an EPROM is used,
the follOWing design considerations must be
observed for proper operation:
1. The pin-out for the EPROM is 2716 compatible.
2. Programs in the EPROM must begin at 30
(hex). The RAM bootstrap ROM resides in
locations OC (hex) to 2F (hex).
FFFH . . . - - - - - - - - - - -.......
(7FFH
3. The LDE instructions that would attempt a
write to the EPROM cannot be used.
4. The UPC must be taken out of the Download
mode by the host CPU after a reset: This is
accomplished by having the host CPU write
two bytes to the UPC. The first byte must
reset the Interrupt Pending bit (05) in the
Master CPU Interrupt Control (MIC)
register. The second byte must set the End
of Message bit (DO) in the same register.
Any static RAM that can be interchangeably
used with a 2716 EPROM can be plugged into
the Protopack socket.
Protopaclc: Pin Functions. Forty of the pins on
the Protopack versions have functions identical
to those of the 40-pin version. The remaining
24 pins have additional functions described
below. (Figure 11 shows the Protopack versions' pin functions and pin assignments.)
Ao-Alo. Program Memory Address Lines (output). These lines are identical in all RAM/ROM
versions in the Protopack. They are used to ad. dress 2K bytes of external UPC memory.
00-07. Program Data (input/output). Data is
read in from the external memory on these'.
lines. The RAM version also writes external
memory through this bus.
MOS. Memory Data Strobe (output, active
Low). This signal is Low during an instruction
fetch or memory write .
MR/W. Memory Read/Write (output RAM versions only). This signal is High when the UPC
is fetching an instruction and Low when it is
loading external memory.
Z8094
+5V 1
PCLK
PCLK 2
P37/1EO
P37/1EO 3
P3011EI
P3011EI 4
P3s1iNf
P3s1iNf 5
P32/1NTACK
P32/1NTACK 6
os
R/W
AS
EXTERNAL
RAM
PROGRAM MEMORY
~~~~--------------------~
}
BOOTSTRAP ROM
INTERNAL
ROM
CH
cs
CS 10
GND
GND 11
WAIT
WAIT 12
AD7
DB7 13
ADs
DBs 14
ADs
DBs 15
AD4
DB4 16
AD3
DB3 17
AD2
ADI
DBI 19
ADo
DBo 20
Socket Pin Definition:
UPC INTERRUPT
EXTERNAL RAM
Figure 10. UPC RAM Version Memory Map
2017·005, 008
RD7
WR 8
A/o 9
'SOCKET FOR 2716 EPROM (2K )( 8) OR RAM
BH~----I}
~_ _ _ _V_E_~_O_R_S_____
Z8594
+5V
pin
pin
pin
pin
pin
pin
pin
pin
1 A7
2 As
3 As
4 A4
5 A3
6 A2 '
7 Al
8 Ao
pin
pin
pin
pin
pin
pin
pin
pin
9 Do
10 Dl
11 D2
12 GND
13 D3
14 D4
15 Ds
16 Ds
pin
pin
Pin
pin
pin
pin
pin
pin
17 D7
18 MDS
19 Al0
20 GND
21 MR/W
22 Ag
23 As
24 +5 V
Figure II. Z80941Z8594 UPC Protopack Pin Assignments
571
Addressing
Modes
The following notation is used to describe the
addressing modes and instruction operations as
shoyvn in the instruction summary.
IRR
Irr
X,
DA
Additional
Symbols
Flags
dst
src
cc
Destination location or contents
Source location or contents
Condition code (see list)
@
Indirect address prefix
SP
Stack Pointer (control register FFH)
PC
Program Counter
, FLAGS Flag register (control register FCH)
RP
Register Pointer (control register FDH)
IMR
Interrupt Mask register (control register FBH)
Control Register FCH contains the folloWing six
flags:
C
Z
S
V
D
H
Condition
Codes
572
Indirect register pair or indirect working-register
pair address
Indirect working-register pair only
Indexed address
Direct address
Carry flag
Zero flag
Sign flag
Overflow flag
DeCimal-adjust flag
Half-carry flag
RA
1M
R
IR
Ir
RR
Assignment of a value is 'inqicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" ,is used
to refer ~o bit "nil of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
Affected flags are indicated by:
o
*
X
Value
Mnemonic
1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
aIII
1011
0011
0000
C
NC
Z
NZ
PL
MI
OV
NOV
EO
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register
address
Indirect working-register address only
Register pair or working-register pair address
Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined
Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Never true
Flags Set
C = 1
C = a
Z = 1
Z = a
S = a
S = 1
V = 1
V =0
Z = 1
Z = a
(S XOR V) = a
(S XOR V) = 1
[ZOR (S XOR V)] = 0
[ZOR (S XOR V)] = 1
C=O
C = 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
Instruction
Formats
CCF, 01, EI, IRET, NOP,
RCF, RET, SCF
OPC
dst
OPC
INCr
One-Byte Instructions
CLR, CPL, DA, DEC,
'----=-="'------' OR
I
OPC
i---""ds"";t---I OR
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
11 1 1 01 dsllsrc 1 ~~~~'~~~Rt~~:R:OP'
RRC, SRA, SWAP
11 1 1 01
JP, CALL (Indirect)
dst
I---";;';":---i OR
OPC
VALUE
11 1 101
dst
ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TCM, TM, XOR
SRP
LD
ADC, ADD, AND,
CP, OR, SBC, SUB,
TCM, TM, XOR
LD, LDE, LDEI,
LDC, LOCI
LD
1-.---':'=:":""----'
dst 1 OPC
VALUE
IdSIlCCR~
OPC
OR
11 1 1 01
JP
LD
CALL
DJNZ, JR
Two-Byte Instructions
2037-013
LD
Three-Byte Instructions
573
Opcode
Lower Nibble (Hex)
Map
o
6,5
o
6,5
10,5
10,5
7
8
9
A
B
10,5
10,5
6,5
6,5
12/10,5
12/10,0
6,5
12/10,0
6,5
LO
LO
OJNZ
JR
LO
JP
INC
n,R2
r2,RI
n,RA
cc,RA
rl,IM
cc,DA
rl
DEC ADD ADD ADD ADD ADD ADD
RI
IRI
rl, rz
rl,lrz
Rz,RI
6,5
6,5
6,5
6,5
10,5
RLC
RLC
IRz,RI
RI,IM
IRI,IM
10,5
10,5
10,5
RI
IRI
rl, rz
rl,Irz
R2,RI
IRz,RI
RI,IM
IRI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
INC
INC
SUB
SUB
SUB
SUB
SUB
SUB
RI
IRI
rl, rz
rl,lrz
Rz,RI
IRz,RI
RI,IM
IRI,IM
6,5
6,5
10,5
10,5
10,5
10,5
SBC
SBC
SBC
SBC
SBC
IRRI
1M
rl, fZ
rl,lrz
Rz,RI
IRz,RI
RI,IM
IRI,IM
8,5
8,5
6,5
6,5
10,5
10,5
10,5
10,5
"
OA
OA
OR
OR
OR
OR
OR
OR
RI
IRI
rl, rz
rl,lrz
Rz,RI
IR2,RI
RI,IM
IRI,IM
10,5
10,5
6,5
6,5
10,5
10,5
10,5
10,5
5
POP
POP
ANO
ANO
ANO
ANO
ANO
ANO
7
.
:z:
RI
IRI
rl, rz
rl,lrz
Rz,RI
IRz,RI
RI,IM
IRI,IM
6,5
6,5
6,5
6,5
10,5
10,5
10,5
10,5
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
RI
IRI
rl, rz
rl,lrz
Rz,RI
IRz,RI
RI,IM
IRI,IM
10112,1 12/14,1
6,5
6,5
10,5
10,5
10,5
10,5
PUSH
PUSH
TM
TM
TM
TM
TM
TM
Rz
IRz
rl, rz
rl,lrz
R2,RI
IRz,RI
RI,IM
IRI,IM
10,5
10,5
12,0
18,0
PECW OECW
8
~
9
A
LOE
LOEI
RRI
IRI
rl, Irrz
IrI,lrrz
6,5
6,5
.12,0
18,0
LOE
LDEI
RL
RL
RI
IRI
10,5
10,5
B
C
0
E
F
6,5
IRI
f---
f---
f---
I----
f---
f---
DI
6,1
EI
6,5
10,5
10,5
10,5
CP
CP
CP
CP
CP
rl,lrz
R2,RI
IRz,RI
RI,IM
IRI,IM
6,5
6,5
6,5
10,5
10,5
10,5
10,5
CLR
XOR
XOR
XOR
XOR
XOR
XOR
RI
IRI
rl, rz
rl, Irz
Rz,RI
IRz,RI
RI,IM
IRI,IM
6,5
6,5
12,0
18,0
RRC
RRC
LOC
LOCI
RI
IRI
----16,0
-
6,5
6,5
12,0
18,0
20,0
20,0
10,5
SRA
LOC
LOCI
CALL*
CALL
LO
RI
IRI
IRRI
DA
rz, x, RI
6,5
6,5
10,5
10,5
rz,lrrl Irz, Irrl
6,5
10,5
10,5
RR
RR
LO
LO
LO
LO
LO
RI
IRI
rl,lr 2
R2,RI
1R2,RI
RI,IM
IRI,IM
8,5
8,5
6,5
10,5
LO
LO
Irl, rz
Rz,IRI
.;
\..
-
RCF
6,5
. SCF
f---
6,5
CCF
I----
6,0
r
""
2
IRET
6,5
LO
rl, x, Rz
SRA
V"
14,0
RET
10,5
rl, Irrz Irl,lrrz
IRI
f---
10,5
CP
6,5
\..
f---
f---
rl, rz
'SWAP SWAP
Bytes perInstruction
f---
6,1
CLR
RI
F
E
rz,lrrl Irz, Irrl
INCW INCW
RRI
C
ADC ADC ADC ADC ADC ADC
SBC
6
o
6
6,1
II
Il.
Il.
5
SRP
II
II
"
IP
e
:9
6,5
3
8,0
3
:Q
6,5
DEC
2
M
2
3
..I
NOP
\..
~--------~~~----------~~ ~ ~
2
3
Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode --.. A
Nibble
First
Operand
•
Pipeline
Cycles
Mnemonic
Second
Operand
Legend:
R = 8-Bit Address
r = 4-Bit Address
RI or rl = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.
*2-byte instruction; fetch cycle appears as a 3-byte instruction.
574
8085-002
Instruction
Summary,
Opcode Flags Affected
Byte
(Hex)
CZSVDH
Instruction
and Oporatlon
Addr Mode
ADC dst,src
dst - dst -+ src + C
(Note 1)
10
* * * * 0 *
LDE dst,src
dst - src
ADD dst,src
dst - dst + src
(Note 1)
00
* * * * 0 *
AND dst,src
dst - dst AND src
(Note 1)
50
* 0 - -
CALL dst
DA
IRR
SP - SP - 2
@SP - PC; PC - dst
D6
D4
CCF
C - NOTC
dst
src
Addr Modo
Instruction
and Operation
Opcode Flags Affected
Byte
(Hex)
CZSVDH
dst
src
r
Irr
Irr
82
92
------
LDEI dst,src
.Ir
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Ir
83
93
------
FF
------
------
OR dst,src
dst - dst OR src
(Note 1)
40
- * * 0 - -
* - - - - -
POP dst
dst - @SP
SP - SP + 1
R
IR
50
51
------
EF
70
71
------
NOP
CLR dst
dst - 0
R
IR
BO
Bl
------
PUSH src
SP - SP-l; @SP - src
COM dst
dst - NOT dst
R
IR
60
61
- * * 0 - -
RCF
C-O
CF
0- - - - -
CP dst,src
dst - src
(Note 1)
AD
* * * * - -
RET
PC - @ SP; SP - SP + 2
AF
------
DA dst
dst - DA dst
R
IR
40
41
* X- -
RL dst
DEC dst
dst-dst-1
R
IR
00
01
- * * * --
RLC dst
DECW dst
'dst - dst - 1
RR
IR
80
81
- * * *--
8F
DI
IMR (7) - 0
DJNZ r,dst
r - r- 1
if r :;t: 0
PC - PC + dst
Range: + 127, -128
RA
rA
r=O-F
~
R
IR
90
91
Lri'l=E:i}J
R'
IR
11
RR dst
lElLJ, .tJ I~
EO
El
------
RRC dst
Lri'l=E:i}J
R
IR
CO
Cl
------
SBC dst,src
dst - dst - src - C
(Note 1)
3D
------***--
R
IR
rE
r=O-F
20
21
RR
IR
AO
Al
-***--
IRET
BF
FLAGS - @SP; SP - SP + 1
PC - @SP; SP - SP + 2; IMR(7) -1
* * * * * *
JP cc,dst
if cc is true
PC - dst
------
IRR'
cD
c=O-F
30
m cc,dst
RA
cB
c=O-F
------
rC
r8
r9
r=O-F
C7
------
INC dst
dst - dst + 1
INCW dst
dst - dst +
DA
if cc is true,
PC - PC + dst
RaQge: + 127, -128
LD dst,src
dst - src
r
R
1M
R
r
X
r
Ir
,R
R
R
IR
IR
X
r
Ir
r
R
1R
1M
1M
R
r
Irr
Irr
LOCI dst,src
Ir
Irr
dst - src
r - r + 1; rr - rr + 1
Irr
Ir
LDC dst,src
dst - src
c
,
c
,
•
•
D7
E3
F3
E4
E5
E6
E7
F5
SRA dst
CD
~
~
Ia.
a
en
* * *
DF
1 - - - - -
..-
DO
Dl
***0--
n
31
-----* * 1 *
* 1 *
SRP src
RP - src
1m
SUB dst,src
dst - dst - src
(Note 1)
20
SWAP dst
R
IR
FO
Fl
X * * X - -
TCM dst,src
(NOT dst) AND src
(Note 1)
60
-
* * 0 - -
TM dst,src
dst AND src
(Note 1)
70
-
* * 0 - -
XOR dst,src
dst - dst XOR src
(Note 1)
BO
-**0--
®
Note 1
These instructions have an identical set of addressing
modes, which ate encoded for brevity. The first opcode
nibble is found' in lhe instruction set table above. The
second nibble is expressed symbolically by a 0 in this
table, and its value is found in the folloWing table to the
left of the applicable addressing mode pair.
For example, to determine the opcode of an ADC
instruction using the addressing modes r (destination) and
Ir (source) is 13.
dst
src
R
R
R
IR
Ir
R
IR
1M
1M
Lower
Opcode Nibble
[lJ
------
C3
D3
------
U)
C
c:I
IU
lEl C2J .tJ I~
Addr Mode
C2
D2
N
00
"
10
SCF
C-1
9F
EI
1MR (7) - 1
R
IR
[I]
rn
@]
@]
[l]
575
Registers
R248 PIM
Port 1 Mode Register
UPC register address (Hex): Fa
R247 P3M
Port 3 Mode Register
UPC register address (Hex): F7
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
III ~ ::::: ::~~::: ::~:::
P10-P1r 1/0 DEFINITION
' - - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
1 PORT 1 PULL·UPS ACTIVE
o P35
R246 P2M
Port 2 Mode Register
UPC register address (Hex): F6
= OUTPUT
1 P35 = [NT
RESERVED
o P33
= INPUT
1 P33 .. DAV1/R,DY1
I~I~I~I~I~I~I~I~I
P34 = OUTPUT
P34 = RDY1/DAV1
'-------- ~ ~!: ~ ~:~R~~~
P2o-P27 1/0 DEFINITION
' - - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT
~!:: ~~~~~OUT)
'---_ _ _ _ _ _ ~ ~: ~ :~tUT
~!~
: ~~TPUT
'---------- ~ ~!~ : :~~~~K
Figure 12. Port Mode Registers
R251lMR
Interrupt Mask Register
UPC register address (Hex); FB
R250 IRQ
Interrupt Request Register
UPC register address (Hex); FA
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
~~~
L
L.1ENABLESIRQO
III'.~
1 ENABLES IRQ1
1 ENABLES IRQ2
:::
;~~:::~'"
OOMM"'CA"O"
IRQ2 = P31 INPUT
IRQ3 = P30 INPUT
1 ENABLES IRQ3
IRQ4 = To
1 ENABLES IRQ4
-
1 ENABLES IRQS
L -_ _ _ _ _ _ _
RESERVED
IROS = TI
RESERVED
' - - - - - - - - - 1 ENABLES INTERRUPTS
R2491PR
Interrupt Priority Register
UPC register address (Hex): F9 (Write Only)
I~I~I~I~I~I~I~I~I
.","m
INTERRUPT GROUP PRIORITY
RESERVED .. 000
C>A> B = 001
A>B>C - 010
A>C>B = 011
B>C>A = 100
C>B>A = 101
B>A>C
110
RESERVED = 111
:::J
II I 4'"".
'"0"""'''' (••0""1
o = IRQ1
> IRQ4
1 = IRQ4 > IRQ1
IRQO, IRQ2 PRIORITY (GROUP B)
0 = IRQ2 > IROO
1 = IRQO>IRQ2
IRQ3, IRQS PRIORITY (GROUP A)
0
IRQS > IRQ3
1 .. IRQ3>IRQS
=
=
Figure 13. Interrupt Control Registers
R254 MIC
Master CPU Interrupt Control Register
UPC register address (Hex); FE
R240 MIV
Master CPU Interrupt Vector Register
OPC register address (Hex); FO
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
~~
LO-
'--------
'---------'--..,------
1 END OF MESSAGE
L - I-
_ _
VECTOR DATA (Do
= LSB)
o WAIT ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE
o ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN
o DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
o VECTOR OUTPUT
1 NO VECTOR OUTPUT
~ ~~S~~~T~:u~~~~~1~~~U:iN~~~gING
~ ~~~~1~~~U~~DUE~D::R~~~~ICE
~ :~~~==~~~ =~g~m ~~:BBLL:g
Figure 14. Master CPU Interrupt Registers'
576
20l7 c009, OlD, all
Registers
(Continued)
R253 RP
Register Pointer
UPC register address (Hex); FD
R252 FLAGS
Flag Regi!;ter
UPC register address (Hex); FC
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
L USER FLAG Fl
~~llli
L
USER FLAG F2
REGISTER POINTER
('4-'7)
c=
=:=J
DON'T CARE
HALF CARRY FLAG
DECIMAL ADJUST FLAG
R255 SP
StacIe Pointer
UPC register address (Hex); FF
OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
' - - - - - - - - - - CARRY FLAG
I~I~I~I~I~I~I~I~I
I
STACK POINTER
(SPO-SP7)
Figura 15. UPC Control Rogistors
RODTC
Data Transfer Control Register
UPC register address (Hex); 00
R4LC
Limit Count Register
UPC register address (Hex); 04
I~I~I~I~I~I~I~I~I
I~I~I~I~I~I~I~I~I
(EOM)~
~
(LERR)
L-._____
END OF MESSAGE
0 NO LIMIT ERROR
1 LIMIT ERROR
(XERR)
R5 DIHD
Data Indirection Register
UPC register address (Hex): 05
NO TRANSFER ERROR
TRANSFER ERROR
(EDX)
LIMIT COUNT VALUE
(RANGE: 0-255 DECIMAL
OO-FF HEX)
DISABLE DATA TRANSFER
ENABLE DATA TRANSFER
I~I~I~I~I~I~I~I~I
,",(I.;.;;RP~)_ _ _ _ _ _ _ 1 1/0 REGISTER POINTER
IL-._____ :~~':~~~)ON
ADDRESS
Figuro 16. Mastor CPU-UPC Data Transfer Rogistors
R241 TMR
Timer Mode Register
UPC register address (Hex): F 1
I~I~I~I~I~I~I~'~I
RESERVED = 00
T
U=T
To O
OUT
01M O D E S J
Tl OUT = 10
INTERNAL CLOCK OUT = 11
.
ug~
R243 PREI
Prescaler I Register
UPC register address (Hex): F3
-
1~'~'~'~'~'~f~'~1
l
0 = NO FUNCTION
1 = LOAD To
0 = DISABLE To COUNT
1 = ENABLE To COUNT
~~g~~
0 = NO FUNCTION
1 = LOAD Tl
EXTERJJ..1
INPUT = 00
TRI~~i~ :~~~~ ~ ~~
1
PASS
Tl MODULO. N
PRESCALER MODULO
' - - - - - - - (RANGE: 1-64 DECIMAL·
01-00 HEX)
0 = DISABLE T 1 COUNT
1 = ENABLE Tl COUNT
(NON.RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)
g~U~I\~N°J>L~
=
CLOCK SOURCE
o = EXTERNAL TIMING INPUT
(TIN) MODE
1 = Tl INTERNAL
R244 TO
Counter/Timer 0 Register
UPC register address (Hex): F4
R242 TI
Counter/Timer I Register
UPC register address (Hex); F2
I~I~I~I~I~I~I~I~I
L-.____
I'------l~~~~~~~-~~~~~CIMAL
Tl INITIAL VALUE
(RANGE: 1-256 DECIMAL
01-00 HEX)
01-00 HEX)
R245 PREO
Prescaler 0 Register
UPC register address (Hex): F5
I~I~I~I~I~I~I~I~I
~L:
.
COUNT MODE
0 = To SINGLE·PASS
1 = To MODULO· N
RESERVED
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)
FigurQ 17. UPC CountorlTimor Rogistors
2017-012, 014, 013
577
Registers
(Continued)
Control Register
0,
Ds
DS
D"
D3
D2
Dl
DO
Comments
DOH
Data Transfer Control Register
X
X
X
X
0
0
0
0
Disable data transfer
from master CPU
0
0
0
Stops TO and T 1
X
0
0
Single-Pass mode
X
0
0
Single-Pass mode
External clock source
04H
Limit Count Register
Not Defined
05H
Data Indirection Register
Not Defined
FOH
Interrupt Vector Register
Not Defined
FIH
Timer Mode
0
0
0
X
X
X
X
X
Not Defined
F4H
Tl Register
F5H
Tl Prescale~
0
Not Defined
F2H
TO Register
F3H
TO Prescaler
0
X
X
X
X
X
Port 2 llnes defined as
inputs
F6H
Port 2 Mode
F7H
Port 3 Mode
0
0
0
0
X
0
0
'1
F8H
Port 1 Mode
Port 1 lines defined as
inputs
Not Defined
F9H
Interrupt Priority
FAH
Interrupt Request
X
X
0
0
0
0
0
0
Reset Interrupt Request
FBH
Interrupt Mask
0
X
X
X
X
X
X
X
Interrupts disabled
0
0
0
Master CPU interrupt disabled; wait enable when
write; lower chain enabled
FCH
Flag Register
Not Defined
FDH
Register Pointer
Not Defined
FEH
Master CPU Interrupt
Control Register
FFH
Stack Pointer
0
0
0
0
0
Not Defined
NOTE: X means not defined.
Tablo 4. Control Register Reset Conditions
578
Port 1. 2 open drain;
P3S = INT; P30. P3!. P32.
P33 defined as input; P34.
P36. P37 defined as output.
Absolute
Maximum
Ratings
Voltages on all pins
with respect to GND .......... -0.5 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Standard
Test
Conditions
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:
4.75 V:s; Vee:S; +5.25 V
= GND = a V
D O°C :s; TA :s; +70°C*
D
o VSS
'See Ordering Information section for package
temperature range and product number.
+5V
+5V
18K
2.2K
-=
Figuro lB. Tost Load 1
DC
Characteristics
Symbol
Parameter
VeH
Clock Input High Voltage
VeL
Clock Input Low Voltage
V IH
Input High Voltage
V IL
Input Low Voltage
V OH
Output High Voltage
VOL
Output Low Voltage
Figuro 19. Tost Load 2
Min
Max
Unit
2.4
Vee
V
-0.3
0.8
V
2.0
Vee
V
-0.3
0.8
V
2.4
Condition
V
IOH
0.4
V
loL
IlL
Input Leakage
-10
10
/LA
IOL
Output Leakage
-10
10
/LA
lee
Vee Supply Current
180
rnA
o :5
o :5
Notes
= -250/LA
= +2.0 rnA
VIN :5 +5.25 V
VIN :5 +5.25V
2
1. For AO-All' DO-D7, and MRlW on the Protopack versions, IOH = 100 "A and IOL = 1.0 rnA.
2. For Protopack versions, lee = 180 rnA plus the current for the memory Ie used.
8085-006, 312
579
Master CPU
Interface
Timing
Z8590/94
PCLK
AID
cs
DBa-DD7
WRITE CASE
WR
DBo-DD7
READ CASE
iii)
WAIT
Interrupt
Acknow ledge
Timing
DBa-DD7
Z8590/94
mTACr.:
iiD
lEI
lEO
580
2022-015, 016
No.
Symbol"
Parameter
Min
4MHz
Max
105
1855
1
TrC
Clock Rise Time
2
TwCH
Clock High Width
3
TfC
Clock Fall Time
4
TwCl
Clock Low Width
105
5
TpC
Clock Period
250
6MHz**
Min
Max
20
15
70
1855
1855
70
1855
2000
165
2000
20
6-TsND(WR) - - AID to WR I Setup Time
10
80
80
7
TsND(RD)
AID to RD I Setup Time
80
80
8
ThND(WR)
AID to WR
25
ThND(RD)
AID to RD
t Hold Time
t Hold Time
30
9
30
25
10
TsCSf(WR)
CS I to WR I Setup Time
0
0
ll-TsCSf(RD) - - CS I to RD I Setup Time
12
TsCSr(WR)
CS t to WR I Setup Time
0
60
0
60
t to RD I Setup Time
60
60
0
0
13
TsCSr(RD)
CS
14
ThCS(WR)
CS to WR I Hold Time
15
ThCS(RD)
CS to RD I Hold Time
16-TsDI(WR) - - Data in to WR I Setup Time
0
0
0
0
17
Tw(WR)
WR Low Width
390
250
18
Tw(RD)
RD Low Width
390
250
19
ThWR(DI)
Data in to WR
0
0
20
TdRD(DI)
Data Valid from RD I Delay
t Hold Time
21 -ThRD(DI) - - Data Valid to RD
t Hold Time
23
TdRD(DBA )
RD I to Read Data Active Delay
24
TdWR(W)
WR I to WAIT I Delay
25
TdRD(W)
RD I to WAIT I Delay
t Delay
t
D-
t.1
CoO
0
c:I
0
150
150
150
150
0
0
TsAC~(RD)
INTACK I to RD I Setup Time
28
TdRD(DI)
RD I to" Vector Valid Delay
29
ThRD(ACK)
RD
0
ThIEI(RD)
t to INTACK t Hold Time
t Hold Time
0
30
IEI to RD
100
100
RD (Acknowledge) Low Width
255
2
80
90
255
180
250
32
TdIEI(IEO)
IEI to IEO Delay
33
TsIEI(RD)
IEI to RD I Setup Time
34
TdACKf(IEO)
IN TACK I to IEO I Delay
250
250
35
TdADKr(IEO)
INTACK
t to IEO t Delay
250
250
NOTES:
1. This parameter Is dependent on the state of the UPC at the time
of master CPU access.
2. In case where daisy chain is not used.
3. The timing characteristics given reference 2.0 V as High and
0.8 V as Low.
•52
•"
45
70
27
31- TwRDl
..g
CI)
~
0
0
TdRD(DIz)
26-TdDI(W) ---Data Valid to WAIT
N
00
0
en
22
Data Bus Float Delay from RD
Notes*t
100
120
120
150
4. All output ac parameters use test load 1.
*Timlngs are preliminary and subject to change.
tUnits In nanoseconds (ns).
**Z8590 only.
581
Handshake
Timing
DATA IN
DAV
INPUT
RDY
OUTPUT
PORT
READ
Input Handshake
DATA OUT
DATA OUT VALID
DAV
I
I
OUTPUT
~
RDY
INPUT
Output Handshake
Reset
Timing
RAM Version
Program
Memory
Timing
MAS·
MNW ----------~r_+_----------------------~--~
(RAM VERSION
ONLy)
,------------
MDS
WRITE CASE
DO-D7
WRITE CASE
MDS
READ CASE
DO-D7
SYNC.=S:Jj
READ CASE
IRQN
®>---....,..~I
~~--~~--~-----------------------------------
'This signal is not available externally.
582
2017·017,018 2014·024 2017.019.
No.
Symbol
Parameter
Min
TsDI(DA)
ThDA(DI)
Data in Setup Time
4MHz
Max
6MHz**
Min
Max
TdDAH(RY)
Data Available High to Ready
Delay Time
6
TdDO(DA)
7
TdRY(DA)
Data O~t to Data Available Delay Time
Ready to Data Available Delay Time
0
0
230
230
175
175
20-'-175---20--175
0
0
150
150
0
0
50
50
205
0
205
0
Symbol
Parameter
Min
2
Data in Hold Time
TwDA
Data Available Width
3
4-TdDAL(RY)--Data Available Low to Ready
Delay Time
5
4 MHz
No.
Max
6MHz**
Max
Min
1
TdRDQ(WR)
Delay from RD t to WR 1 for No Reset
40
35
2
TdWRQ(RD)
Delay from WR t to RD 1 for No Reset
50
35
3
TwRES
Minimum Width of WR and RD both Low for Reset
250
250
Symbol
Parameter
4MHz
Min
Max
6MHz**
Min
Max
Memory Address Strobe Width
2
TwMAS
TdA(MAS)
3
TdMRIW(MAS)
Notes*t
1,2
1,22,3
1,2
2,3
2
2
Notes*t
4
N
C»
0
CG
No.
1
Address Valid to Memory Address Strobe t Delay
Memory ReadlWrite to Memory Address Strobe t
Delay
TdMDS(A)
Memory Data Strobe t to Address Change Delay
4
5 -TdMDS(MRIW)- Memory Data Strobe t to Memory ReadlWrite Not
Valid Delay
Tw(MDS)
Memory Data Strobe Width (Write Case)
6
TdDO(MDS)
Data Out Valid to Memory Data Strobe I Delay
7
TdMDS(DO)
Memory Data Strobe t to Data Out Change Delay
8
Tw(MDS)
Memory Data Strobe Width (Read Case)
9
lO-TdMDS(DI)--Memory Data Strobe I to Data In Valid Delay
11
12
TdMAS(DI)
ThMDS(DI)
13
14
TwSY
TdSY(MDS)
15
TwI
60
30
...
5
1:1
D.
5
DJ
II
en
30
30
60
60
5
....
t.D
S!
d
75
80
160
110
30
30
230
30
30
230
160
280
Memory Address Strobe t to Data In Valid Delay
Memory Data Strobe t to Data In Hold Time
Instruction Sync Out Width'
0
160
Instruction Sync Out to Memory Data Strobe Delay
Interrupt Request via Port 3 Input' Width
200
100
NOTES:
1. Input Handshake.
2. Test Load 1.
3. Output Handshake.
4. Internal reset signal is Y2 to 2 clock delays from external reset
condition.
S. Delay times are specified for an input clock frequency of 4
MHz. When operating at a lower frequency, the increase in in·
put clock period must be added to the specified delay time,
6. Data strobe width is specified for an input clock frequency of 4
MHz. When operating at a lower frequency. the increase in
55
30
Notes*t
@
6
5
5
130
220
6
77
0
100
160
100
three input clock periods must be added to the specified width.
Data strobe width varies according to the instruction being executed.
7. Address strobe and data strobe to data in valid delay times
represent memory system access times and are given for a 4
MHz input frequency.
* All timing references assume 2.0 V for a logic "1" and 0.8 V for a
logic "0". All output ae parameters use test load 2. Timings are
preliminary and subject to change.
tUnits in nanoseconds (ns).
* *Z8090 only.
583
8
Master CPU
Interface
Timing
Z8090/94
peLK
ADo-AD?
MASTER CPU
READ
Ai
RlW
(WRITE)
....:.------~rl------~~+-----T--T----i-
ruW
(READ)
-------~H_----
ADO-AD?
MASTE~~I~~
Interrupt
Acknow ledge
Timing
_ _ _ _ _ _01
"_+-~';';;;"_"'I ~_______-+:::-:-______
ADO-AD?
Z8090/94
61
lEI
lEO
INT
---------------------
584
2017-015,016
4 MHz
No.
2
Symbol
Parameter
Min
Max
6MHz**
Min
Max
TrC
TwCh
TfC
Clock Rise Time
20
1855
20
105
1855
250-2000
15
1855
10
70
1855
165 -2000
3
4
TwCl
5-TpC
TsCS(AS)
6
ThCS(AS)
7
TsA(AS)
8
ThA(AS)
9
lO-TwAS
11
TdDS(DR)
TdDS(DRz)
Clock High Width
Clock Fall Time
Clock Low Width
Clock Period
CS to AS t Setup Time
CS to AS t Hold Time
Address to AS t Setup Time
Address to AS t Hold Time
AS Low Width
DS t to Read Data Not Valid
DS t to Read Data Float Delay
12
TdAS(DS)
13
AS t to DS 1 Delay
TdDS(AS)
14
DS t to AS 1 Delay
15-ThDW(DS)-- Write Data to 158t Hold Time
TdDS(DR)
DS 1 to Read Data Valid Delay
16
TdAz(DS)
17
Address Float to DS De~ay
18
TwDS
DS Low Width
TsRWR(DS)
R!W (Read) to DS 1 Setup Time
19
20-TsRWW(DS)-- RlW (Write) to DS 1 Setup Time
TsDW(DSf)
Write Data to DS 1 Setup Time
21
TdAS(W)
AS t to WAIT 1· Valid Delay
22
ThRW(DS)
R!W to DS t Hold Time
23
TsDR(W)
24
Read Data Valid to WAIT t
25
26
27
TsIA(AS)
ThIA(AS)
TdAS(DSA)
TdDSA(DR)
IN TACK to AS t Setup Time
INTACK to AS t Hold Time
AS t to DSI (lAcknowledge) Delay
DS 1 (Acknowledge) to Read Data Valid
28
Delay
TwDSA
DS 1 (Acknowledge) Low Width
29
30-TdAS(IEO)-- AS t to lEO Delay
31
32
33
34
105
0
60
30
50
0
70
2095
30
40
35
20
45
2095
2
N
CO
1--3
0
390
40
0
250
0
250
200
360
475
ThIEI(DS)
lEI to DS t Hold Time
100
to
~
~
d
~
6
180
250
250
290
120
150
aen
0
940
lEI to lEO Delay
IEI to DS 1 (Acknowledge) Setup Time
DS 1 to INT Delay
D-
160
60
0
100
120
500
500
~
0
20
195
C
U)
C
g
0
250
80
100
0
30
TdIEIf(IEO)
TsIEI(DSA)
TdDS(lNT)
NOTES:
l. Parameter does not apply to Interrupt Acknowledge transactions.
2. The maximum value for TdAS(DS) does not apply to Interrupt
Acknowledge transactions.
3. This parameter is dependent on the state of UPC at the time of
master CPU access.
70
0
40
10
30
50
70
0
60
50
No~es*t
100
* Timings are preliminary and pubject change.
t Units)n nanoseconds (ns).
**Z8090 only.
The timing characteristics given reference 2.0 V as High and
0.8 V as Low.
All output ac parameters use test load I.
585
Product
Number
Package/
Temp
Speed
Description
Product
Number
Package/
Speed
Temp
Description
Z8590
CS
4.0 MHz
UPC (40- pin)
28090
PS
4.0 MHz
UPC (40-pin)
Z8090
CS
4.0 MHz
Same as above
28590-6
PS
6.0 MHz
Same as above
Z8590-6
CS
6.0 MHz
Same as above
28090-6
PS
6.0 MHz
Same as above
RS
4.0 MHz
UPC Protopack
RS
4.0 MHz
Same as above
Z8090-6
CS
6.0 MHz
Same as above
28594
Z8590
PS
4.0 MHz
Same as above
28094
NOTES: C = Ceramic, P = Plastic, R = Protopack; S = O°C to +70°C.
586
00-2022-02
Zili©g
Pioneering the
Micro world
",.
September 1983
The advancing demands of the
marketplace have caught many
design projects between the need
for new features and the desire to
preserve existing software. The
l800 family provides the most
desired new features without compromise. It is totally software- (object code) compatible with the
l80®.
Memory Management. The demand for memory expanded
beyond 64K is satisfied by the
memory management of the l800,
which also provides protection and
dynamic relocation. Two alternatives, 512K bytes and 16M bytes
of physical address space, are
available with MPUs in 40- and
64-pin packages, respectively. The
implementation deals with 4K or
8K pages, which can be individually mapped and protected. Virtual
memory is also supported, via an
instruction abort mechanism.
The utility of the larger spaces is
enhanced by the optional separation of program and data and the
implementation of System and
User modes. System program,
system data, user program, and
user data can now each occupy
64K physical spaces without
operating system intervention.
Much larger spaces can be made
available by reloading the on-Chip
control registers.
Performance. To fully benefit from
longer programs operating on
larger blo,cks of data, increas~d
performance is essential. This is
provided by the l800 in several
ways. First, a range of clock
speeds will be available starting
with 10 MHz. To achieve full
benefit from the higher CPU
speeds without making inordinate
demands on memory access, onchip cache memory featuring
automatic update has been implemented.
Furthermore, a 16-bit bus option
doubles the bandwidth to memory.
For CPU-intensive applications, the
system can be further tailored for
cost-effective use of memory with
the programmable bus-clock scaler
and the four programmable waitstate generators. These devices
operate directly off the on-Chip
clock oscillator, which runs at half
the frequency of the crystal. Additional performance enhancement
results from new addressing
modes and new instructions. For
example, hardware multiply and
divide are standard in both Signed
and unsigned modes for both 8 and
16 bits.
Savings. System cost has been
reduced through the integration of
peripheral functions on-chip. Both
board space and development time
are saved by the use of the four
DMAs, four counter/timers, and
one UART available on the l800
chip, These features-along with
the refresh generator, memory
manager, cache memory, and
clock oscillator with the CPUresult in a virtual mainframe onchip.
Support. MPU features can be
converted to system benefits only
with appropriate development
suport tools. lilog support starts
with the UN IX* envi ronment on the
DEC-VAX or the lilog System
8000. Cross-software is provided
that includes an assembler,
instruction-level simulator, C compiler, linker, loader, and library.
This software is compatible with
DEC-VMS and CP/M.
The l-SCAN 800 is provided for
debugging hardware and software.
It features real-time emulation with
menu-driven, screen-oriented software, Early system prototyping can
be done with the single-board computer/development module
(SBCIDM). This multibus board has
128K bytes of random access
memory, four sockets for read-only
memory, three serial ports, one
parallel port, and an interface to
floppy disks. Software for the
SBC/DM will include CP/M and all
the cross-software packages.
·UNIX is a trademark of Bell Laboratories.
589
Z800™ IIPU
ramAly
Zilog
Preliminary
Product
Specification
September 1983
FEATURES
High performance 16-bit Z-BUS interface or 8-bit
Z80-compatible bus interface.
II
Enhanced Z80® instruction set that maintains
object-code compatibility with Z80 microprocessor_
II
Ell
On-chip paged Memory Management Unit (MMU)_
m Four on-chip 16-bit counter/timers.
II
Large memory address space: 512K byte and 16M
byte versions.
[J
IllI
On-chip, high-speed local or cache memory.
Four on-chip DMA channels.
m On-chip full duplex UART.
a
,10-25 MHz CPU processor clock.
GENERAL DESCRIPTION
Zilog's newZ800 family of 8- ano 16-bit microprocessors
features high-performance microprocessors designed to
give the end-user a powerful and cost effective solution
to application requirements. The family consists of the
8-bit Z80-Bus microprocessors that are packaged in 40and 64-pin dual i'n-line packages, and 16-bit Z-BUS
microprocessors in 40- and 64-pin packages. The Z800
family incorporates advanced ,architectural features that
allow fast and efficient throughput and increased
memory addressing while maintaining Z80 object code
compatibility. Z800 microprocessors offer both a C2ontinuing growth path for present Z80-based designs and a
high-performance microprocessor for future designs.
Central to the Z800 microprocessors is an enhanced version of the Z80 Central Processing Unit (CPU). To assure
system integrity, the Z800 microprocessors can operate
in either user or system mode, allowing protection of
system resources from user tasks and programs.
System mode operation is supported by the addition of
the system Stack Pointer to the working register set. The
IX and IY registers have been modified so that in addition
to their regular function as index registers, each register
can be accessed as a 16-bit general purpose register or
as two single-byte registers.
The Z80 CPU instruction set has been retained, meaning
that the Z800 microprocessors are completely binarycode compatible with present Z80 code. The basic addressing modes of the Z80 microprocessor have been
augmented with the addition of Indexed mode with full
16-bit displacement, Program Counter Relative with
16-bit displacement, Stack Pointer Relative with 16-bit
displacement, and Base Index mode. The new addressing modes are incorporated into many of the old Z80
CPU instructions, resulting in greater flexibility and
power. Some additions to the instruction set include
8-and 16-bit signed and unsigned multiply and divide,
8-and 16-bit sign extension, and a test and set instruction
to support multiprocessing. The 16-bit instructions have
been expanded to include 16-bit compare, memory increment, memory decrement, negate, add, and subtract,
, in addition to the previously mentioned multiply and
divide.
A requirement of many of today's microprocessor-based
system designs is to increase the memory address
space beyond the 64K byte range of typical 8-bit
microprocessors. The Z800 microprocessors have an
on-chip Memory Management Unit (MMU) that enables
the microprocessors to address either 512K bytes or
16M bytes, depending on the device package. In addition
to enabling the address space to be expanded, the MMU
performs other memory management functions
previously handled by dedicated off-chip memory
management devices.
I/O address space has been expanded by the addition of
an I/O Page register used to select pages of I/O addresses. The 8-bit I/O Page register can select one of
591
256 possible pages of I/O addresses to be active at one
time, allowing a. total of 64K I/O addresses to be accessed.
There are 256 bytes of on-chip memory present on all
members of the Z800 family. This memory can be configured as a high-speed cache or as a fixed address local
memory. When configured as a cache, the memory can
be programmed to be instruction onlY,data only, or both
data and instruction. The cache memory allows programs to run significantly faster by reducing the number
of external bus accesses. Operation and update of the
cache is performed automatically and is completely
transparent to the user. When used as a local memory,
the addresses are programmable, allowing "RAMless"
systems to be used.
Many features' that have traditionally been handled by
external peripheral devices have been incorporated in
the deSign of the Z800 microprocessors. The "on-chip
peripherals" reduce system chip count and reduce interconnection on the external bus. All members of the Z800
family contain an·on-chip clock oscillator. Also present is
a refresh controller that provides 10-bit refresh addresses for dynamic memories.
The 64-pin versions of the Z800 MPU contain additional
on-chip peripherals to provide system deSign flexibility.
To support high·bandwidth data transmission four
Direct Memory Access (DMA) channels are incorp~rated
on-Chip. Each DMA channel operates using full 24-bit
source and destination addresses with a 16-bit count.
The channels can be. programmed to operate in single
transaction, burst, or continuous mode. System event
counting and timing. requirements are met with the help
of the four 16-bit counter/timers. The counter/timer func~ions can be externally controlled with gate and trigger
Inputs, and can be programmed as retriggerable or
nonretriggerable. Also, a full duplex UART, capable of
handling a variety of data and character formats, is present to facilitate asynchronous serial communication.
Regardless of whether the 8- or 16-bit bus is used, all
members of the Z800 family feature programmable bus
timing, allowing the user to tailor timing to the individual
system. Upon reset the Z800 microprocessors can be
programmed to have system timing that is one-fourth,
one-half, or equal to the speed of the CPU, with one-half
being the default. In addition to clock scaling, programmable wait states can be inserted during various bus
transactions. Without the use of external· hardware, one
to th~ee wait states can be inserted into memory, I/O,
and Interrupt acknowledge transactions. Furthermore,
separate memory wait states can be specified for upper
and lower memory areas, facilitating the use of different
speeds of ROMs and RAMs in the same system.
An additional featu re of the 16-bit bus interface is the
ability to support "nibble-mode" dynamic RAMs. Using
this feature (known as burst mode), the bus bandwidth of
memory read transactions is essentially doubled. Burst
mode transactions have the further benefit of allowing
the cache to operate more efficiently by guaranteeing a
high probability that the contents of the accessed
memory will be present in the cache.
The Z800 family supports Zilog's ExtendedProcessor Architecture (EPA) in a number of ways. All members are
capable of trapping Extended Processor Unit (EPU) instructions in order to perform software emulation of the
EPU. The Z8216 directly interfaces with an EPU such as
the Z8070 Floating Point Unit and operates in a manner
that is completely transparent to the user and the program. The other members of the Z800 family can interface easily with EPUs with the aid of support software.
The pin functions of four versions of the Z800 MPU,
Z8108, Z8208, Z8116, and Z8216, are shown in Figures
1-4, respectively. A block diagram of the Z800 M PU is
shown in Figure 5.
zaoo CPU
User and System Modes of Operation
The Z800 CPU can operate in either user or system
mode. In user mode, some instructions cannot be executed and some registers of the CPU are inaccessible.
In general, this mode of operation is intended for use by
application programs. In system mode, all of the instructions can be executed and all of the CPU registers can
be accessed. This mode is intended for use with programs that perform operating system functions. This
separation of CPU resources promotes the integrity of
the system, since programs op~rating in user mode cannot access those aspects of the CPU that deal with
system interface events.
592
To further support the dual user/system mode, there are
two copies of the Stack Pointer-one for the user stack
and another for the system stack. These two stacks
facilitate the task switching involved when interrupts or
traps occur. To ensure that the user stack is free of
system information, the information saved on the occurrence of interrupts or traps is always pushed onto the
sy.stem stack before the new program status is loaded.
ADO
ADI
AD2
BUS
TIMmO
AND
STATUS
AD3 : : )
AD4
ADs
AD7
As
BUS!
TIMINO
AND
STATUS
IORQ
ADI
Mi
AD2
MREQ
AD3
RD
ViR
ADs
RFSH
ADs
As
AD4
CPU CONTROL
{
,
_
WAIT
HALT
PAUSE
All
Z8208
MPU
Au
BUS CONTROL
A15
WAIT
HALT
-
Z8108
A17
As
As
Au
INTERRUPTS
BUSREQ
Ala
Au
BUSACK
All
A20
A21
A12
A13
A22
ADDRESS
A23
A14
AIS
ClK
-
Au
ClK
A17
XTALI
AIS
XTAlO
+5V
+5V
GND
GND
Figure 1. Z8108 Pin Functions
Figure 2. Z8208 Pin Functions
BUS
TIMINO
AND
STATUS
BUS
TIMINQ
AND
STATUS
1
ADDRESS
AIS
MPU
BUS CONTROL {
A12
A13
AD7
_
-
Ala
RESET
CPU CONTROL {
As
ADo
os
B/Vi
DATA
Ag
RESET
ADDRESS'
DATA
ADDRESSI
ADs
-
AS
ADo
Os
ADI
B/Vi
AD2
RiW
AD3
STo
AD4
STI
ADs
ST2
ADs
----
ST3
ADDRESS'
DATA
iE
Oe
RiW
RESET
STo
WAIT
STI
PAUSE
AD12
Z8216
MPU
AD13
ST2
ST3
ADDRESS'
DATA
Z8116
MPU
BUS CONTROL {
BUSREQ
I
BUSACK
ADll
BUSREQ
AD12
iiiiSAci<
AD13
ADDRES.
AD14
NMI
INTERRUPTS {
ClK
-
XTAll
AIS
A17
XTAlO
AIS
+5V
GND
GND
Figure 3. Z8116 Pin Functions
225~1,OO2,003,OO4
XTAlO
+5V
Figure 4. Z8216 Pin Functions
593
INTERNAL
ADDRESS/DATA
BUS
¢=>
ADDRESS
BUS
¢=
CONTROL
BUS
¢=>
~
BUS
K
~
)
I
Ii.
BUS
INTERFACE
~
\
CLOCK
OSCILLATOR
)
~
\.
~
r
~
~
RDYO * - - .
MEMORY
* --
REFRESH
ADDRESS
GENERATOR
~
)
UART
I~
-
,....
,
r--
DMA
CHANNEL
t~
~
J
r
COUNTER·
TIMER
0
1
I
2
--
3
CTh*
CTI01 *
CTI2*
CTI02*
I
2
3
~
CTIO*
CTIOo*
I
1
I
....
....
0
I
--
~
* -* --
Rx*
--. Tx*
l'
I-
DMASTB1
INTc"
256 BYTE
~
'i
DMASTBo * - * --
iiiTB*
~
MEMORY
MANAGEMENT
UNIT
RDY1
~
~
V
~
=c...-
--
CPU
l'
NMI
INTA
I
·Z8216 only
Figure 5.
zaoo MPU Block Diagram
Address Spaces
The Z8aa CPU architecture supports four distinct address spaces corresponding to the different types of
locations that can be accessed by the CPU. These four
address spaces are:
III
CPU register space
II
CPU control and status register space
•
Memory address space
•
I/O address space
CPU Register Space. The CPU register space consists
of all of the registers in the CPU register file. The CPU
registers are used for data and address manipulation ..
Access to these registers is specified in the instruction.
The CPU registers are labeled F, A, B, C, D, E, H, L, F',
A', B', C', D /, E', H', L', IX, IY, SSP, USP, PC, I, and R.
594
CPU Control and Status Register Space. The CPU
control register space consists of all of the control and
status registers found in the CPU control register file.
These registers govern the operation of the CPU and are
accessible only by the privileged Load Control instruction. The registers in the CPU control file consist of the
Master Status register, Bus Timing and Initialization
register, Bus Timing and Control register, InterruptlTrap
Vector Table Pointer, I/O Page register, System Stack
Limit register, Trap Control register, Interrupt Status
register, Cache Control register, and Local Address
register.
Memory Address Space. Two memory address spaces
are supported by the Z8aa CPU; onefor user and one for
system mode of operation. They are selected by the
User/System Mode (U/S) bit in the Master Status
register, which governs the selection of page descriptor
registers during address translation.
2259-005
Each address space can be viewed as a string of 64K
bytes numbered consecutively in ascending order. The
8-bit byte is the basic addressable element in the
memory address spaces. However, there are other addressable data elements: bits, 2-byte words, byte strings
and multiple-byte EPU operands.
The address of a multiple-byte entity is the address of the
byte with the lowest address. Multiple-byte entities can
be stored beginning at either even or odd memory addresses.
I/O Address Space. I/O addresses are generated only
by the I/O instructions IN, OUT, and the I/O block move
instructions. Logical I/O addresses are eight bits in
le.ngth, augmented by the A register on lines Aa-A15 in
Direct Address addressing mode and by the B register
on lines Aa-A15 in Indirect Register addressing mode
Clnd for block I/O instructions. The 16-L.. t logical I/O address is always extended by appending the contents of
the 8-bit page register to the augmented I/O address.
Thus the complete address generated to address an 1/0
port consists of an I/O page number on A23-A16, the contents of the A or B register on Aa-A15, and the 8-bit I/O
address on A7-AQ.
Unlike memory references, in which a 16-bit word store
or fetch can generate two memory references, an 1/0
word store or fetch is always one 1/0 bus transaction
regardless of bus size or I/O port address. Note:
however, that on-chip peripherals with word registers
are accessed via word I/O instructions for those 16-bit
registers, regardless of the external bus size.
Data Types
The CPU can operate on bits, binary-coded decimal
(BCD) digits (4 bits), bytes (8 bits), words (16 bits), byte
strings, and word strings. Bits in registers or memory
can be set, cleared, and tested. BCD digits, packed two
to the byte, can be manipulated with the Decimal Adjust
Accumulator instruction in conjunction with binary addition and subtraction. Bytes" are operated on by 8-bit load,
arithmetic, logical, and shift and rotate instructions.
Words are operated on in a similar manner by the 16-bit
load and 16-bit arithmetic instructions. Block move and
search operations can manipulate byte strings up to 64K
bytes long. Block I/O word instructions can manipulate
word strings up to 32K words long. To support EPU
operations, byte strings up to 16 bytes in length can be
transferred by the CPU.
CPU Registers
The Z8aa MPU contains 23 programmable registers in
the CPU register address space. These registers are
illustrated in Figure 6.
Primary and Working Register Set. The working
register set is divided into the two 8-bit register
files-the primary fil€ and alternate (designated by ,
[prime]) file. Each file contains an 8-bit accumulator (A),
a Flag register (F), and six general-purpose registers (B,
C, 0, E, "H, and L). Only one file can be active at any
given time. Upon reset, the primary register file is active.
Exchange instructions allow the programmer to exchange the active file with the inactive file.
PRIMARY FILE
A
AUXILIARY FILE
F
ACCUMULATOR
FLAG REGISTER
A'
ACCUMULATOR
F'
FLAG REGISTER
B
GENERAL PURPOSE
C
GENERAL PURPOSE
B'
GENERAL PURPOSE
C' .GENERALPURPOSE
D
GENERAL PURPOSE
E
GENERAL PURPOSE
D'
GENERAL PURPOSE
E'
GENERAL PURPOSE
H
GENERAL PURPOSE
L
GENERAL PURPOSE
H'
GENERAL PURPOSE
L'
GENERAL PURPOSE
, ..
..
8 BITS
I
R
INTERRUPT VECTOR
IX INDEX REGISTER
I
I
IY INDEX REGISTER
I
PC PROGRAM COUNTER
SP STACK POINTER
USER
I
:J
SYSTEM
, .......- - - - - - - 1 6 BITS----~--.. I
Figure 6. CPU Register Configuration
2259..()()6
595
The accumulator is the destination register for 8-bit
arithmetic and logical operations. The six generalpurpose registers can be paired (BC, DE, and HL) to form
three 16-bit general-purpose registers. The HL register
pair serves as a 16-bit accumulator for 16-bit arithmetic
operations.
CPU Flag Register. The Flag register contains six flags
that are set or reset by various CPU operations. This
register is illustrated in Figure 7.
7
0
Is Iz I I I I I Ic I
0
H
0
PIV
N
Figure 7. CPU Flag Register
The flags in this register are:
Carry (C). This flag is set when an add instruction
generates a carry or a subtract instruction generates a
borrow. Certain logical and rotate and shift instructions
affect the Carry,flag.
Add/Subtract (N). This flag is used by the Decimal Adjust
Accumulator instruction to distinguish between add and
subtract operations. The flag is set for subtract operations and cleared for addition operations.
Parity/Overflow (PIV). This flag is set or cleared depending on the operation being performed. During arithmetic
operations it is set to indicate a twos complement
overflow. During logical and rotate operations, this flag
is set to indicate even parity of the result, or cleared to
indicate odd parity.
Half Carry (H). This flag is set if an 8-bit arithmetic operation generates a carry or borrow between bits 3 and 4, or
if a 16-bit operation generates a carry or borrow between
bits 11 and 12. This bit is used to correct the result of a
packed BCD addition or subtract operation.
Zero (Z). This flag is set if the result of an arithmetic or
logical operation is a zero.
Sign (S). This flag stores the state of the most significant
bit of the accumulator. The Sign flag is also used to indicate the res'ults of a test and set instruction.
Dedicated CPU Registers
Index Registers. The two Index registers, IX and IY,
each hold a 16-bit base address that is used in the Index
addressing mode. The Index registers can also function
as general-purpose registers with the upper and lower
bytes capable of being accessed individually. The high
and low bytes of the IX register are called IXH and IXL.
The high and low bytes of the IY register are called IYH
and IYL.
Interrupt Register. The Interrupt register (I) is used in interrupt mode 2 to 'generate a 16-blt indirect logical address to an interrupt service routine. The Interrupt
register supplies the upper eight bits of the indirect address and the interrupting peripheral supplies the lower
eight bits.
596
Program Counter. The Program Counter (PC) is used to
sequence through instructions in the currently-executing
program and to generate relative addresses. The Program Counter contains the 16-bit logical address of the
currerit instruction being fetched from memory.
R Register. The R register can be used as a generalpurpose 8-bit read/write register. The R register is not
associated with the refresh address and its contents are
changed only by the user.'
Stack Pointers. Two hardware Stack Pointers, the user
Stack Pointer (USP) and the system Stack Pointer (SSP),
support the dual mode of operation of the
microprocessor. The SSP is used for saving information
when an interrupt or trap occurs, and for supporting
subroutine calls and returns in system mode. The USP is
used for supporting subroutine calls and returns in user
mode.
'
Status and Control Registers. There are ten status and
control registers available to the programmer in the
Z800 MPU. Table 1 shows the addresses occupied by
the registers in the status and control register addressing space.
Table 1. Status and Control Register Addressing Space
Address
(Hexadecimal)
Control Register Name
Bus Timing and Control
Bus Timing and Initialization
Cache, ControP'
Interrupt Status
InterruptfTrap Vector Table
1/0 Page Register
Local Address Register2
Master Status (MSR)
Stack Limit
Trap Control
Control
Control
Control
Contro!
Control
Control
Control
Control
Control
Control
02
FF
12
16
06
08
14
00
04
10
NOTES:
1. See section on on-chip memory for register description.
2. See section on multiprocessing mode of operation for register description.
Bus Timing and Control Register. This 8-bit register
(Figure 8) governs the timing of transactions to high
memory addresses and the daisy-chain timing for interrupt requests, as well as the functionality of requests on
the various Z800 MPU interrupt request lines. On reset,
this register is cleared to aliOs.
7
I
o:c
I I I+
0
0
0
lIP
I
Figure 8. Bus Timing and Control Register
2259'()()7,008
The fields in this register are:
I/O Wait Insertion (I/O). This 2-bit field specifies the
number of additional wait states (in addition to the one
automatically inserted for I/O) to be inserted by the CPU
in both I/O transactions and vector response timing (00
none, 01
one, 10
two, 11
three).
=
=
=
=
High Memory Wait Insertion (HM). This 2-bit field
specifies the number of automatic wait states (00 =
none, 01
one, 10
two, 11
three) for the CPU to
insert in memory transactions when the MMU is enabled
and there is a 1 in bit 15 of the selected page descriptor
register.
=
=
=
Daisy Chain Timing (DC). This 2-bit field determines the
number of additional automatic wait states the CPU inserts while the interrupt acknowledge daisy chain is settling (00
none, 01
one, 10
two, 11
three). A
value of 01 in the DC field indicates that one additional
cycle will be added to the four cycles that normally
elapse between interrupt acknowledge, AS and OS
assertions.
=
=
=
Multiprocessor Configuration Enable (MP). This ·1-bit field
enables the multiprocessor mode of operation (0
disabled, 1 = enabled). (See the multiprocessor mode
section).
=
Bootstrap Mode Enable (BS). This 1-bit field enables the
bootstrap mode of operation (0 = disabled,1 = enabled). (See the UART section for details about bootstrap
mode.)
Interrupt Status Register. This 16-bit register (Figure
10) indicates which interrupt mode is in effect and which
interrupt sources have interrupt requests pending. It also
contains the bits that specify whether the interrupt inputs are to be vectored. Only the interrupt vector enable
bits are writeable; all other bits are read-only.
=
Figure 10. Interrupt Status Register
Bus Timing· and Initialization Register. This 8-bit
The fields in this register are:
register (Figure 9) is used to specify the duration of control signals for the external bus when the MMU is disabled or when the MMU is enabled and there is a in bit
15 of the selected page descriptor register. It also controls the relationship between internal processor clock
rates and bus timing. It can be programmed by external
hardware upon reset.
Interrupt Request Pending (lP). When bit IPn is set to 1,
an interrupt request from sources at level n is pending.
(See the Interrupt and Trap Structure section.)
During reset this register is initialized to one of two settings, depending on the state of the Wait input line on the
rising edge of reset: if the Wait line is not asserted, the
register is set to OOH. If the Wait line is asser.ted during
reset, then this register is set to the contents of the AD
lines.
Interrupt Vector Enable (I). These four bits indicate
whether each of the four interrupt inputs are to be vectored. When In is set to 1, interrupts on the Interrupt n
line are vectored when the CPU is in interrupt mode 3;
when cleared to 0, all interrupts on this line use the same
entry in the InterruptlTrap Vector Table. These bits are
ignored except in interrupt mode 3.
a
Interrupt Mode (1M). A value of n in .this 2-bit. field indicates that interrupt mode n is in effect. This field can
be changed by executing the 1M instruction.
Interrupt/Trap
Vector Table Pointer. This 16-bit
register (Figure 11) contains the most Significant 12 bits
of the physical address at the beginning of the InterruptlTrap Vector Table; the lower 12 bits of the phYSical
address are assumed to be O. The four least significant
bits of this register must be O.
Figure 9. Bus Timing and Initialization Register
The fields in this register are:
Clock Scaling (CS). This 2-bit field specifies the scaling of
the CPU clock for all bus transactions (00 = one bus
clock cycle is equal to two internal processor clock
cycles, 01 = bus clock cycle is equal to the internal
processor clock cycle, 10 = one bus clock cycle is
equal to four internal processor clock cycles, 11 =
reserved). This field cannot be modified by software.
110 Page Register. This 8-bit register (Figu re 12) in-
Low Memory Wait Insertion (LM). This 2-bit field
specifies the number of automatic wait states (00
none, 01
one, 10
two, 11
three) for the CPU to
insert in memory transactions when the MMU is disabled
or when the MMU is enabled and there is a in bit 15 of
the selected page descriptor register.
IA231 A221 A2l1 A20 IAlgi Alai A171 A161
=
=
=
=
a
Figure 11. Interrupt/Trap Vector Table Pointer
dicates the bits to be appended to the 16 bits that are
output during I/O transactions during the I/O address
phase.
7
0
Figure 12. 1/0 Page Register
2259-009,010,011,012
597
Master Status Register. The Master Status register
(Figure 13) is a 16-bit register containing status information about the currently-executing program. This register
is cleared to 0 during reset.
Trap Control Register. This 8-bit register (Figure 15)
enables the maskable traps.
7
0
lolololololllElsl
15
I I
0
Uffi
0
I 0 IBH I 0 I 0 Isspl ss I 0 I E61 Esl q I E31 E21 El IEo I
Figure 13. Master Status Register
The bits in this register are:-
The fields in this register are:
Interrupt Request Enable (En). There are seven Interrupt
Enable bits, one for each type of maskable interrupt
source (both external and internal). When bit En is set to
1, interrupt requests from sources at level n are accepted by the CPU; when this bit iscleared to 0, interrupt
requests at level n are not accepted.
Single-Step (SS). While this bit is set to 1, the CPU is in
single-stepping mode; while this bit is cleared to 0,
automatic single-stepping i.s disabled. This bit is
automatically cleared when a trap or interrupt is taken.
Single-Step Pending (SSP). While this bit is set to 1, the
CPU generates a trap prior to executing an instruction.
The SS bit is a'utomatically copied into this field at the
completion of each instruction. This bit is. automatically
cleared to 0 when a Single-Step, Page Fault, Privileged
Instruction, Break-on-Halt or Division trap is taken so
that the SSP bit in the saved Master Status register is
cleared to O.
Breakpoint-on-Halt Enable (BH). While this bit is set to 1,
the CPU generates a Breakpoint trap whenever a halt instruction is encountered; while this bit is cleared to 0, the
halt instruction is executed normally.
User/System Mode (U/S). While this bit is cleared to 0,
the CPU is in the system mode of operation; while it is
set to 1 the CPU is in the user mode of operation.
System Stack Limit Register. This 16-bit register
(Figure 14) indicates when a System Stack Overflow
Warning trap is to be generated. If enabled by setting a
control bit in the Trap Status register, pushes onto the
system stack cause the 12 most significant bits in this
register to be compared to the upper 12 bits of the
system Stack Pointer and a trap is generated if they
match. The low-order four bits of this register must be O.
15
IA1SI A14\ A13\A12\ All! Al0! A9! As IA7' As' As' A4'
0
0 , 0 , 0 , 0
Figure 14. System Stack Limit Register
598
Figure 15. Trap Control Register
I
System Stack Overflow Warning (S). While this bit is set
to 1 the CPU generates a Stack Overflow Warning trap
when the system stack enters the specified region of
memory. Upon reset this register is, initialized to all Os.
EPU Enable (E). While this bit is cleared to 0, the CPU
generates a trap whenever an EPA instruction. is encountered.
Inhibit User I/O (/). While this bit is set to 1, the CPU
generates a Privileged Instruction trap when an 1/0 instruction is encountered in user mode.
Cache Control and Local Address Registers. See the
. on-chip memory section for information about the Cache
Control register, and the multiprocessor mode section
for information about the Local Address register.
Interrupt and Trap Structure
The l800 MPU provides a very flexible and powerful interrupt and trap structure. Interrupts are external asynchronous events requiring CPU attention, and are
generally triggered by peripherals needing service.
Traps are synchronous events resulting from the execution of certain instructions.
Interrupts. Two types of interrupt, nonmaskable and
maskable, are supported by the l800 MPU. The nonmaskable interrupt (NMI) cannot be disabled (masked)
by software and is generally reserved for highest priority
external events that require immediate attention.
Maskable interrupts, however, can be selectively disabled by software. Both nonmaskable and maskable interrupts can be programmed to be vectored or nonvec- tored. The CPU accepts interrupts between instructions
with the exception of the block move, search, and I/O instructions, which can be safely interrupted after any
iteration and restarted after the interrupt is serviced.
Interrupt Sources. The l800 MPU accepts nonmaskable interrupts on the NMI pin only. The l800 MPU
accepts maskable interrupts on the INT pins, and from
the on-chip counter/timers, DMA channels, and the
UART receiver and transmitter. The 40-pin members of
the l800 family accept maskable interrupts on INTA
only.
2259'()13, 014, 015
Interrupt Lines A, B, and C can be selectively programmed to support. vectored interrupts by setting the appropriate bits in the Interrupt Status register. The external interrupts can be programmed to be vectored or
nonvectored in interrupt mode 3.
Interrupt Modes of Operation. The CPU has fou r
modes of interrupt handling. The first three modes extend the l80 interrupt modes to accommodate additional interrupt input lines in a compatible fashion. The
fourth mode provides more flexibility in handling the interrupts. On-chip peripherals use the fourth mode
regardless of which mode is selected for externally
generated interrupt requests. The interrupt mode is
selected by using the privileged instructions 1M 0, 1M 1,
1M 2, or 1M 3. On reset, the l800 MPU is automatically
set to interrupt mode O. The current interrupt mode in effect can be read from the Interrupt Status register.
Mode O. This mode is identical to the 8080 interrupt
response mode. With this mode, the interrupting device
on any of the maskable interrupt lines can place a call or
restart instruction on the data bus and the CPU will execute it. As a result, the interrupting device, instead of
the memory, provides the next instruction to be executed.
Mode 1. When this mode is selected, the CPU responds
to a maskable external interrupt by executing a restart to
the logical address 0038H in the system program address space.
Mode 2. This mode is a vectored interrupt response
mode. With a single 8-bit byte from the interrupting
device, an indirect call can be made to any memory
location. With this mode the system maintains a table of
16-bit starting addresses for every interrupt service
routine. This table can be located anywhere in the
system mode logical data address space on a 256-byte
boundary. When an interrupt is accepted, a 16-bit pointer
is formed to obtain the desired interrupt service routine
starting address from the table. The upper eight bits of
this pOinter are formed from the contents of the I
register. The lower eight bits of the pointer must be supplied by the interrupting device. The 16-bit pOinter so
formed is treated as a logical address in the system data
address space, which can be translated by the MMU to a
physical address.
Mode 3. This is the intended mode of operation for
systems that take advantage of the enhancements of the
l800 microprocessor family (such as single-step and
user/system mode) since the Master Status register is
automatically saved and another loaded for the interrupts. Also, vector tables can be used for the external interrupt sources to provide more interrupt vectors for the
l8000™ family, l80 family, and l8500 Universal
Peripherals.
When an interrupt _request (either maskable or nonmqskable) is accepted, the Master Status register, the
address of the next instruction to be executed, and a
16·bit •• reason code" are pushed onto the system stack.
A new Master Status register and Program Counter are
then fetched from the InterruptlTrap Vector Table. The
"reason code" for externally generated interrupts is the
contents of the bus during the interrupt acknowledge sequence; for 8-bit data buses, the most significant byte of
the reason code is zero. For interrupts generated by onchip peripherals, the reason code identifies which
peripheral generated the interrupt and is identical to the
vector address in the Interrupt/Trap Vector Table. The Interrupt/Trap Vector Table Pointer is used to reference
the table.
Traps. The l800 CPU supports eight traps that are
generated internally. The following traps can be disabled: the EPA trap, which allows software to emulate an
EPU; the Stack Warning trap, which is taken at the end of
an instruction causing the trap; the Breakpoint-on-Halt
trap, which is taken when a halt instruction is encountered; and the Single-Step trap, which is taken for
each instruction. In addition, I/O instructions can be
specified as privileged instructions. Traps cause the in~
struction to be terminated without altering CPU registers
(except for the system Stack Pointer, which is modified
when the program status is pushed onto the system
stack).
The saving of the program status on the system stack
and the fetching of a- new program status from the Interrupt/Trap Vector Table is the same in any interrupt mode
of operation;
Traps can only occur if the trap generating features of
the l800 CPU (such as System Stack Overflow warning)
have been explicitly enabled. Traps cannot occur on in~
structions of the l80 instruction set unless explicitly
enabled by the operating system using l800 CPU extensions.
Extended Instruction. This trap occurs when the CPU encounters an extended instruction while the Extended
Processing Architecture (EPA) bit in the Trap Control
register is O. Four trap vectors are used by the EPA
trap-one for each type of EPA instruction. This greatly
simplifies trap handlers that use I/O instructions to access an EPU or software to emulate an EPU.
Privileged Instructfon. This trap occurs whenever an attempt is made to execute a privileged instruction while
the CPU is in user mode (User/System Mode control bit
in the Master Status register is 1).
System Call. This trap occurs whenever a System Call
(SC) instruction is executed.
Access Violation. This trap occurs whenever the MMU's
translation mode is enabled and an address to be
translated is invalid or (for writes) is write-protected.
System Stack Overflow Warning. This trap occurs only
while the Stack Overflow Warning bit in the Trap Control
register is set to 1. For each system stack push operation, the most significant bits in the Stack Pointer
register are compared with the contents of the Stack
Limit register and a trap is signaled if they match. The
Stack Overflow Warning bit is then automatically cleared
in order to prevent repeated traps.
599
N
CO
8
II
a
Division Exception. This trap occurs whenever the
divisor is zero (divide-by-zero case) or the true quotient
cannot be represented in the destination precision
(overflow); the CPU flags are set to distinguish these two
cases.
Single-Step. This trap occurs before executing an instruction if the Single-Step Pending control bit in the'
Master Status register is set to 1. Two control bits in the
Master Status register are used for the Single-Step trap.
The Single-Step bit (bit 8), on being set when previously
clear, causes a trap to occur after the execution of the
next instruction. While this bit is set to 1, if an instruction
execution causes a trap, the Single-Step trap occurs
after the execution of the trap-handling routine. The
Single-Step Pending bit (bit 9), is used by the processor
to ensure that only one Single-Step trap occurs for each
instruction executed while the Single-Step bit is set to 1.
Breakpoint-on-Halt. This trap occurs whenever the
Breakpoint-on-Halt control bit in the Master Status
register is·1 and a halt instruction' is encountered.
Interrupt and Trap Disabling. Maskable interrupts can
be enabled or disabled independently via software by
setting or clearing the appropriate control bits in the
Master Status register.
A 7-bit mask field in the Master Status register indicates
which of the requested interrupts will be accepted. Interrupt requests are grouped as follows, with each group
controlled by a separate Interrupt Enable control bit. The
list is presented in order of decreasing priority, with
sources within a group listed in order of descending
priority.
•
Maskable Interrupt A line (bit 0)
•
Counter/Timer 0, DMAO (bit 1)
•
Maskable Interrupt B line (bit 2)
•
Counter/Timer 1, UART receiver, DMA 1 (bit 3)
•
Maskable Interrupt C line (bit 4)
•
Counter/Timer 2, UART transmitter, DMA2 (bit 5)
•
Counter/Timer 3, DMA3 (bit 6)
When a source of interrupts has been disabled, the CPU
ignores any interrupt request from that source.
The System Stack Overflow Warning trap, I/O instructions in user mode trap (Privileged Instruction trap), or
Extended Instruction trap can be enabled by setting control bits in the Trap Control register, and the Single-Step
and Breakpoint-on-Halt trap can be enabled by setting
control bits in the Master Status register; these are the
only traps that can be disabled.
Interrupt/Trap Vector Table. The, format of the Interrupt/Trap Vector Table consists of pairs of Master Status
register and Program Counter words, one pair for each
600
separate on-Chip interrupt or trap source. For each external interrupt, there is a separate Master Status
register word and Program Counter word (for use if the
input is not vectored). If the external interrupt is vectored, a vector table consisting of one Program Counter
word for each of the 128 possible vectors that can be
returned for each input line is used instead of the
dedicated Program Counter word; thus for vectored interrupts, there is only one Master Status register for
each interrupt type.
The format of the Interrupt/Trap Vector Table is shown in
Table 2.
Table 2. InterruptiTrap Vector Table
Address
(Hexadecimal)
Contents
00
Unused
04
08
OC
10
NMI Vector
Interrupt Line A Vector (End of Process)
14
18
1C
20
24
C-TO
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68-6C
70-16E
170-26E
270-36E
Interrupt Line B Vector
Interrupt Line C Vector
C-T1
C-T2
C-T3
DMAO Vector
DMA1 Vector
DMA2 Vector
DMA3 Vector
UART Receiver Vector
UART Transmitter Vector
Single-Step Trap Vector
Breakpoint-on-Halt Trap Vector
Division Exception Trap Vector
Stack Overflow Warning Trap Vector
Page Fault Trap Vector
System Call Trap Vector
Privileged Instruction Trap Vector
EPU .... Memory Trap Vector
Memory .... EPU Trap Vector
A .... EPU Trap Vector
EPU Internal Operation Trap Vector
Reserved
128 Program Counters for NMI and Interrupt line A Vectors (MSR from 04 and
08, respectively)
128 Program Counters for Interrupt Line
B Vectors (MSR from OC)
128 Program Counters for Interrupt Line
C Vectors (MSR from 10)
Addressing Modes
Addressing modes (Figure 16) are used by the CPU to
calculate the effective address of an operand needed for
execution of an instruction. Nine addressing modes are
supported by the Z800 CPU. Of these nine, four are additions to the Z80 addressing modes (Indexed with 16-bit
displacement, Stack Pointer Relative, Program Counter
Relative, and Base Index) and the remaining five modes
are either existing or extensions to the existing Z80 addressing modes.
Register. The operand is one of the 8-bit registers (A, B,
C, D, E, H, L, IXH, IHL, IYH or IYL); or one of the 16-bit
registers (BC, DE, HL, IX, IY, or SP), or one of the special
byte registers (I or R).
Immediate. The operand is in the instruction itself and
has no effective address.
Register Indirect. The contents of a register specify the
effective address of an operand. The HL register is the
register most often used for memory accesses. The C
register is used for I/O and control register space accesses.
Direct Address. The effective address of the operand is
the location whose address is contained in the instruc-
tion. Depending on the instruction, the specified operand
is either in I/O or data memory space.
Index. The effective address of the operand is the location specified by adding the 16-bit address contained in
the instruction to a twos complement "index" contained
in the HL, IX, or IY register.
Short Index. The effective address of the operand is the
location computed by adding the 8-bit twos complement
signed displacement contained in the instruction to the
contents of the IX or IY register. This addressing mode is
equivalent to the Z80 CPU indexed mode.
Relative. An 8- or 16-bit displacement contained in the
instruction is added to the Program Counter to generate
the effective address of the operand.
Stack Pointer Relative. The effective address of the
operand is the location computed by adding a 16-bit twos
complement displacement contained in the instruction
to the contents of the Stack Pointer.
Base Index. The effective address of the operand is the
location whose address is computed by adding the contents of HL, IX, or IY to the contents of another of these
three registers.
Instruction Set
Notation
Addressing Modes. The following notation is used to
describe the addressing modes and instruction operations as shown in the instruction set.
BX
DA
1M
IR
X
R
RA
RX
SP
SR
SX
n
nn
Base Index
Direct Address
Immediate constant
Indirect Register
Index
Single register of the set (A, B, C, D, E, H, L)
Relative address f
A byte in the IX or IY register
Current Stack Pointer '
Stack Relative
Short Index
8-bit constant
16-bit constant
Symbols. The following symbols are used to describe
the instruction set.
dst
src
n
nn
SP
p
(C)
SSP
USP
(Destination location or contents)
(Source location or contents)
(An 8-bit constant)
(A 16-bit constant)
(Current Stack Pointer)
(Interrupt mode)
(I/O port pOinted to by C register)
(System Stack Pointer)
(User Stack POinter)
Assignment of a value is indicated by the symbol" -".
For example,
• Abbreviated set
dst - dst
+
src
indicates that the source data is added to the destination
data and the result is stored in the destination location.
The notation "addr(n)" is used to refer to bit "n" of a
given location. For example,
dst(?)
specifies bit? of the destination.
Flags. The F register contains the following six flags.
C
H
N
P/v
S
Z
Carry flag
Half carry flag
Add/Subtract flag
Parity/Overflow flag
Sign flag
Zero flag
Condition Codes. The following symbols describe the
condition codes.
Z*
NZ*
C*
NC*
S
NS
V
PE
PO
P
M
Zero
Not zero
Carry
No carry
Sign
No sign
Overflow
Parity even
Parity odd
Positive
Minus
601
Mode
Operand Addressing
In the Instruction
Register
ESTER ADDRESS
Immediate
Register
Indirect
Direct
Address
In a Register
J-.I
Operand Value
In Memory or I/O
The content of the
register
OPERAND
In the instruction
OPERAND
1 REGISTER ADDRESS
J-.I
ADDRESS
.-------
....._ _
A_D_DR_E_S_S_...... - - - - - - - - - - -...
REGISTER ADDRESS
*Index
I
The content of the location
whose address is in the
register
OPERAND
The content of the location
whose address is in the
instruction
The content of the location
whose address is the 16·bit
address in the instruction,
offset by the content of
the 16·bit register
INDEX
_B_A_SE_AD_D_R_E_SS_.r--------I~·0__1
.....
OPERAND
REGISTER ADDRESS
Short Index
DISPLACEMENT
OPERAND
PCVALUE
*Relative
DISPLACEMENT
DISPLACEMENT
~
•
1
.....---:...-0--I~O-PE-R-A-N-D.,
SPVALUE
*Stack Pointer
Relative
*8ase Index
OPERAND
t------t
.....---~I
OPERAND
The content of the location
whose address is in the 16·bit
register, offset by the 8·bit
displacement in the
instruction
Tile content of the location
whose address is the
content of the Program
Counter, offset by the
displacement in the
instruction
The content of the location
whose address is the
content of the Stack
Pointer, offset by the
displacement in the
instruction
The content of the location
whose address is the
content of a register,
offset by the displacement
in'a register
REGISTER ADDRESS 1
REGISTER ADDRESS 2
-New Z800 Family addreSSing modes
Figure 16. Addressing Modes
602
2259·016
a·Bit Load Group
Instruction
Addressing Modes
EX A,src
src = R,RX,IR,DA,X,SX,
RA,SR,BX
EX H,L
S
Z
0
0
Flags
H. PN
0
0
N
C
Operation
0
0
Exchange Accumulator
A- src
0
0
•
•
•
•
Exchange H,L
H-L
LD dst,src
src=A
dst = R,RX,IR,DA,X,
SX,RA,SR,BX,
(BC),(DE)
0
0
0
0
0
0
Load Accumulator
dst - src
=
t-J
or
C)
src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX,
(BC),(DE)
dst=A
LD dst,src
dst= R
src = R,RXt,IM,IR,SX
C
~
I(J
=
0
0
0
0
0
0
Load Register (Byte)
dst - src
or
dst = R,RXt,IR,SX
src= R
LD dst,n
* LDUD dst,src
dst = R,RX,IR,DA,X,
SX,RA,SR,BX
0
dst=A
src = IR or SX in user
space
0
0
0
0
0
0
Load Immediate (Byte)
dst - nn
~
0
~
0
~
Load in User Data
Space (Byte)
dst - src
or '
dst = IR or SX in user
space
src=A
* LDUP dst,src
dst=A
src = IR or SX in user
space
0
~
0
~
•
~
Load in User Program
Space (Byte)
dst - src
or
dst = IR or SX in user
space
src=A
16·Bit Load Group
Flags
Instruction
Addressing Modes
EX src,HL
src = DE,IX,IY
S
Z
0
0
H PN N
0
0
0
C
0
Operation
Exchange HL with
Addressing Register
src -
HL
* Privileged instruction.
t
Accessing bytes of IX or IY precludes use of H or l.
603
16·Bit Load Group (Continued)
Flags
Instruction
Addressing Modes
S
Z
H PN N
C
Operation
EX (SP),dst
dst = HL,IX,IY
•
•
•
•
•
Exchange Addressing
Register with Top
of Stack
•
(SP) - dst
t
EX AF,AF'
t
t
t
t
Exchange Accumulatorl
Flag with
Alternate Bank
AF-AF'
•
EXX
•
•
•
•
•
Exchange Byte/Word
Registers with Alternate
Bank
BC- BC'
DE - DE'
HL - HL'
LO[W] dst,src
dst = HL,IX,IY
src = IM,DA,X,RA,SR,BX
•
•
•
•
•
•
or
Load Addressing
Register
dst - src
dst = DA,X,RA,SR,BX
src = HL,IX,IY
LO[W] dst,src
LOW dst,nn
dst = BC,DE,HL,SP
src = IM,IR,DA,SX
or
dst = IR,DA,SX
src = BC, DE, H L,SP
•
dst = RR,IR,DA,RA
•
•
•
•
•
•
Load Register Word
dst - src
•
•
•
•
•
Load Immediate Word
dst - nn
LO[W] dst,nn
dst= RR
•
•
•
•
•
•
Load immediate V'v'ord
dst - nn
LO[W] dst,src
LOAdst,src
POP dst
dst=SP
src = HL,IX,IY,IM,IR,
DA,SX
or
dst= IR,DA,SX
src=SP
•
dst= HL,IX,IY
src = X,RA,SR,BX
0
dst = RR*,IR,DA,RA
•
•
•
•
0
•
Load Stack Pointer
dst - src
•
•
•
•
•
Load Address
dst - address (src)
0
•
•
0
0
POP
dst - (SP)
SP - SP + 2
PUSH src
604
src = RR*,IM,IR,DA,
RA
•
•
•
0
0
0
PUSH
SP - SP - 2
(SP) - src
'AF Instead of SP.
Block Transfer and Search Group
Flags
Instruction
CPO
Addressing Modes
S
Z
H
~
~
~
PN N
C
•
~
Operation
Compare and. Decrement
A - (HL)
HL -'HL - 1
Be - Be - 1
CPDR
~
~
~
~
•
Compare, Decrement
and Repeat
Repeat until Be
match:
A - (HL)
HL - HL - 1
Be - Be - 1
CPI
~
~
~
•
~
=0 or
1.\1
@I)
Compare and Increment
A - (HL)
HL - HL + 1
Be - Be - 1
CPIR
~
~
~
•
~
•
•
0
~
0
•
Compare, Increment
and Repeat
=0 or
Load and Decrement
(DE) - (HL)
DE - DE - 1
HL - HL - 1
Be - Be - 1
LDDR
LDI
LDIR
•
•
•
•
0
0
0
•
Load, Decrement and
Repeat
Repeat until Be
(DE),- (HL)
DE - DE - 1
HL - HL - 1
Be - Be - 1
.'
0
•
0
~
0
•
=0:
Load and Increment
(DE) - (HL)
DE - DE + 1
HL - HL + 1
Be - Be - 1
0
0
•
iii
c:I
Repeat until Be
match:
A - (HL)
HL - HL + 1
Be - Be - 1
LDD
8
Load, Increment and
Repeat
=
Repeat until Be 0:
(DE) - (HL)
DE - DE + 1
HL - HL + 1
Be - Be - 1 '
605
a·Bit Arithmetic
~nd
Logic Group
Instruction
Addressing Modes
S
Z
Flags
H PN
N,
C
Operation
ADC [A,]src
src = R,RX,IM,IR,
DA,X,SX,RA,
SR,BX
~
~
~
0
~
Add With Carry (Byte)
src = R,RX,IM,IR,
DA,X,SX,RA,
SR,BX
~
src = R,RX,IM,IR,
DA,X,SX,RA,
SR,BX
~
src = R,RX,IM,IR,
DA,X,SX, RA,
SR,BX
~
ADD [A,]src
AND [A,]src
CP [A,]src
A-A
~
~
V
0
~
p
~
0
0
+
+
src
C
Add (Byte)
A -A
+
src
And
A -AAND src
~
~
~
V
Compare (Byte)
A- src
•
C?PL [A]
V
•
•
•
Complement
Accumulator
A- NOTA
~
DAA [A]
~
~
p
•
~
Decimal Adjust
Accumulator
A - Decimal Adjust A
DEC dst
DIV [HL,]src
DIVU [HL,]src
dst = R,RX,IR,DA,X,
SX,RA,SR,BX
~
src = R,RX,IM,DA,X,
SX,RA,SR,BX
~
src = R,RX,IM,DA,X,
SX,RA,SR,BX
0
~
~
•
V
Decrement (Byte)
dst - dst - 1
~
•
~
•
•
Divide (Byte)
A - HL+src
L - remainder
~
•
~
•
•
Divide Unsigned (Byte)
A~HL+src
L - remainder
•
EXTS [A]
•
•
•
•
•
Extend Sign (Byte)
L-A
If A(7) = 0, then H - 00
else H - FF
INC dst
MULT [A,]src
MULTU [A,]src
NEG [A]
dst = R,RX,IR,DA,X,
SX,RA,SR,BX
~
src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX
~
src= R,RX,IM,IR,DA,
X,SX,RA,SR,BX
0
~
~
V
0
•
Increment (Byte)
dst - dst
~
•
0
•
~
1
Multiply (Byte)
HL - A x src
~
•
0
•
~
Multiply Unsigned (Byte)
HL-A x src
~
~
~
V
~
Negate Accumulator
A- -A
606
+
a·Bit Arithmetic and Logic Group (Continued)
Instruction
Addressing Modes
S
Z
Flags
H PN
OR [A,]src
src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX
t
t
0
src = R,RX,IM,IR,DA,
X,SX,RA,SR ,BX
t
SBC [A,]src
P
N
C
Operation
0
0
OR
A - A OR src
t
t
v
t
Subtract With Carry
(Byte)
A -A - src - c
SUB [A,]src
XOR [A,]src
src = R,RX,IM,IR,DA,
X,SX,RA,SR ,BX
t
src = R,RX,IM,IR,DA,
X,SX,RA,SR,BX
t
t
t
t
V
Subtract
A -A - src
t
0
P
0
0
Exclusive OR
N
A -AXOR src
8
eo
IId
16·Bit Arithmetic. Operations
Instruction
Addressing Modes
S
Z
Flags
H PN
ADC dst,src
dst= HL
src = BC,DE,HL,SP
or
dst= IX
src = BC,DE,IX,SP
or
t
t
t
v
N
C
Operation
0
t
Add With Carry (Word)
dst - dst
+ src + c
dst= IY
src = BC,DE,IY,SP,
ADD dst,src
dst= HL
src = BC,DE,HL,SP
•
•
t
•
0
t
Add (Word)
dst - dst
or
+ src
dst= IX
src = BC,DE,IX,SP
or
dst= IY
src = BC,DE,IY,SP
ADD dst,A
dst = HL,IX,IY
t
t
t
V
0
t
Add Accumulator to
Addressing Register
dst - dst
ADDW [HL,]src
src = RR*,IM,DA,X,RA
t
t
t
V
0
t
Add Word
HL - HL
CPW [HL,]src
src = RR*,IM,DA,X,RA
t
t
t
t
V
+A
+ src
Compare (Word)
HL - src
DECW dst
dst= RR*,IR,DA,X,RA
•
•
•
•
•
•
Decrement (Word)
dst - dst - 1
'In X addressing mode, (HL
+ nn) is precluded.
607
16·Bit Arithmetic Operations (Continued)
Flags
Instruction
Addressing Modes
S
Z
H
DEC[W] dst
dst= RR
•
•
•
PN N
•
•
C
Operation
•
Decrement (Word)
dst - dst - 1
DIVUW
[DEHL,]src
src = RR,IM,DA,X,RA
DIVW [DEHL,]src
src = RR,IM,DA,X,RA
0
t
•
t
•
•
Divide Unsigned (Word)
HL - DEHL+ src
DE - remainder
t
t
•
t
•
•
Divide (Word)
HL - DEHL+ src
DE - remainder
•
EXTS HL
•
•
•
•
•
Extend Sign (Word)
If H(7)= 0, then DE - 0000
else' DE - FFFF
INCW dst
dst = RR,IR,DA,X*,RA
•
•
•
•
•
•
Increment (Word)
dst - dst
INC[W] dst
dst= RR
•
•
•
•
•
•
src = RR,IM,DA,X,RA
0
t
•
0
•
t
1
Increment (Word)
dst - dst
MULTUW [HL,]src
+
+
1
Multiply Unsigned
(Word)
DEHL - HL x src
MULTW [HL,]src
src = RR,IM,DA,X,RA
t
t
•
0
•
t
Multiply (Word)
DEHL - HL x src
t
NEG HL
t
t
V
t
Negate HL
HL SBC dst,src
SUBW [HL,]src
dst= HL
src = BC,DE,HL,SP
or
dst= IX
src = BC,DE,IX,SP
or
dst= IY
src = BC,DE,IY,SP
t
src = RR,IM,DA,X*,RA
t
t
t
V
t
-HL
Subtract With Carry
(Word)
dst - dst - s rc - C
t
t
V
t
Subtract (Word)
HL - HL - src
·In X addressing mode, (HL + nn) is precluded.
608
Bit Manipulation, Rotate and Shift Group
Instruction
Addressing Modes
S
Z
BIT b,dst
dst =R,IR,SX
•
~
Flags
H PN
•
N
C
Operation
0
0
Bit Test
Z - NOT dst(b)
RES b,dst
dst = R,IR,SX
•
•
•
•
•
•
Reset bit
dst(b) - 0
RL dst
dst =R,IR,SX
~
~
0
p
0
~
Rotate Left
tmp - dst
dst(O) - C
C - dst(7)
dst(n + 1) - tmp(n) for
n = 0 to 6
L&EJJ
•
•
0
•
0
Rotate Left Accumulator
tmp-A
A(O) - C
C - A(7)
A(n + 1) - tmp(n) for
n = 0 to 6
L&EJJ
A
RLC dst
dst = R,IR,SX
~
~
0
p
0
Rotate Left Circular
tmp - dst
C - dst(7)
dst(O) - tmp(7)
dst(n + 1) - tmp(n) for
n = 0 to 6
~
dst
RLCA
•
0
0
•
0
GO
8
d
dst
RLA
N
Rotate Left Circular
(Accumulator)
tmp-A
C - A(7)
A(O) - tmp(7)
A(n + 1) - tmp(n) for
n = 0 to 6
~
A
609
Bit Manipulation, Rotate and Shift Group (Continued)
Instruction
Addressing Modes
RLD
S
Z
~
~
Flags
H PN
·0
p
N
C
Operation
0
•
Rotate Left Digit
tmp(0:3) - A(0:3)
A(0:3) - src(4:7} .
src(4:7) - src(0:3)
src(0:3) - tmp(O:3)
432J 801
17 1
A
RR dst
dst = R,IR,SX
~
~
0
p
0
~
dst
Rotate Right
tmp - dst
dst(7) - C
C - dst(O)
dst(n) - tmp(n
n = 0 to 6
+
1} for
L[GJ-.@]J
dst
•
RRA
•
0
•
0
~
Rotate Right
(Accumulator)
tmp - dst
A(7) - C
C - A(O)
A(n) - tmp(n
n = 0 to 6
+
1) for
Lo-liJ
A
RRC dst
dst= R,IR,SX
~
~
0
p
0
~
Rotate Right Circular
tmp - dst
C - dst(O)
dst(7) - tmp(O}
dst(n) - tmp(n
n = 0 to 6
+
1) for
L[G}l0
.dst
610
Bit Manipulation, Rotate and Shift Group (Continued)'
Flags
Instruction
Addressing Modes
RRCA
S
Z
H PN N
•
•
0
•
C
Operation
Rotate Right Circular
(Accumulator)
0
tmp -A
C - A(O)
A(7) - tm p(O)
A(n) - tmp(n
n = 0 to 6
+
1) for
LG4J
dst
RRD dst
dst=IR
t
t
0
p
0
•
N
8
tmp(O:3) - A(O:3)
A(O:3) - src(O:3)
src(O:3) - src(4:7)
src(4:7) - tmp(O:3)
E{
17
dst = R,IR,SX
•
0
0
0
•
•
tg
c=
<13B gol
A
SET b,dst
=
Rotate Right Digit
dst
Set Bit
dst(b) - 1
SLA dst
dst = R,IR,SX
t
t
0
p
0
t
Shift Left Arithmetic
tmp - dst
C - dst(7) .
dst(O) - 0
dst(n + 1) - tmp(n) for
n = 0 to 6
0~~o
dst
SRA dst
dst = R,IR,SX
t
t
0
p
0
t
Shift Right Arithmetic
tmp - dst
C - dst(O)
dst(7) - tmp(7)
dst(n) - tmp(n
n = 0 to 6
+
1) for
~
dst
611
Bit Manipulation, Rotate and Shift Group (Continued)
Flags,
Instruction
Addressing Modes
SRL dst
dst
=R,IR,SX
S
Z
H PN N
C
Operation
0
~
0
p
~
Shift Right Logical
0
tmp - dst
C - dst(O)
dst(7) - 0
dst(n) - tmp(n
n 0 to 6
=
+ 1) for
O~~
dst
TSET dst
dst
=R,IR,SX
~
•
•
•
•
•
Test and Set
s - dst(7)
dst - FF
Program Control Group
Flags
Instruction
Addressing Modes
S
Z
H PN N
C
Operation
CALL cC,dst
dst = IR,DA,RA
•
•
·
•
CALL
.
•
•
If cc is satisfied then:
SP - SP - 2
(SP) - PC
PC - dst
CALL dst
dst = IR,DA,RA
•
•
•
•
•
•
CALL
SP - SP - 2
(SP) - PC
PC - dst
•
CCF
•
~
•
0
~
Complement Carry Flag
C - NOTC
DJNZ dst
dst= RA
•
•
•
•
•
•
Decrement and Jump if
Non·Zero
8-8-1
If 8=#=0 then PC - dst
JAF dst
dst= RA
•
•
•
•
•
•
Jump on Auxiliary
Accumulator/Flag
If Auxiliary AF then:
PC - dst
JAR dst
dst= RA
•
•
•
•
•
•
Jump on Auxiliary
Register File in Use
If Auxiliary File then:
PC - dst
JP cC,dst
dst = IR,DA,RA
•
•
•
•
•
•
Jump
If cc is satisfied then:
PC - dst
612
Program Control Group (Continued)
Flags
Instruction
Addressing Modes
S
Z
JP dst
dst = IR,DA,RA
•
•
H PM N
C
Operation
•
•
Jump
0
•
PC - dst
JR ee,dst
dst= RA
•
•
•
•
0
0
Jump Relative
If ee* is satisfied then:
PC - PC + dst
JR dst
dst= RA
•
0
0
0
0
0
Jump Relative
PC - PC
RET
0
0
0
0
0
•
+
dst
N
00
Return
8
PC - (SP)
SP - SP - 2
•
RET ee
0
0
0
•
0
aiI
Return
If ee is satisfied then:
PC - (SP)
SP - SP + 2
RST dstt
dst= DA
•
0
0
0
0
•
Restart
SP - SP - 2
(SP) - PC
PC - dst
SC nn
0
•
•
0
0
•
System Call
SP -SP - 4
(SP) - PS
SP - SP - 2
(SP) - nn
PS - System Call
Program Status
•
SCF
0
0
•
Set Carry Flag
0
C-1
Input/Output Instruction Group
*
*
Instruction
Addressing Modes
IN dst,(C)
dst= R,RX,DA,X,RA,
SR,BX
IN A,(n)
S
Z
Flags
H PM
0
P
N
C
Operation
0
0
Input
dst - (C)
•
•
•
•
•
•
Input Accumulator
A - (n)
• Uses abbreviated set of condition codes.
t dst mustbe 0, 8, 16, 24, 32, 40, or 56.
:j: Programmable as privileged.
613
Input/Output Instruction Group (Continued)
Flags
Instruction
t
IN[W] HL,(C)
Addressing Modes
S
Z
H PN N
C
Operation
•
•
•
•
•
Input HL
•
HL - (C)
t
IND
•
•
•
•
Input and Decrement
(Byte)
(HL) - (C)
8-8-1
HL-HL-'1
t
INDW
•
•
•
•
Input and Decrement
(Word)
(HL) - (C)
8-8-1
HL - HL - 2
t
INDR
•
1
•
•
•
Input, Decrement and
Repeat (Byte)
Repeat until 8 = 0:
HL - (C)
8-8-1
HL - HL - 1
t
INDRW
•
1
•
•
•
Input, Decrement and
Repeat (Word)
Repeat until 8 = 0:
HL - (C)
8-8-1
HL - HL - 2
t
INI
•
t
•
•
•
Input and Increment
(Byte)
(HL) - (C)
8-8-1
HL - HL + 1
t
INIW
•
t
•
•
•
Input and Increment
(Word)
(HL) - (C)
8-8-1
HL - HL + 2
t
INIR
•
•
•
•
Input, Increment and
Repeat (Byte)
Repeat until 8 = 0:
(HL) - (C)
HL - HL + 1
8-8-1
t Programmable as privileged.
614
Input/Output Instruction Group (Continued)
Flags
Instruction
t
Addressing Modes
INIRW
S
Z
0
H PN N
0
0
C
0
Operation
Input, Increment and
Repeat (Word)
Repeat until B = 0:
(HL) - (C)
HL - HL - 2
B-B-1
tOUT (C),src
tOUT (n),A
src= R,RX,DA,X,RA,
SR,BX
0
0
0
0
0
0
Output
(C) - src
0
0
0
0
0
0
~-J
~
~
~
Output Accumulator
(n) - A
t OUT[W] (C),HL
~
0
0
0
0
0
0
t-J
Output HL
'U
e;I
(C) - HL
t OUTD
0
t
0
0
•
Output and Decrement
(Byte)
B-B-1
(C) - (HL)
HL - HL - 1
t.OUTDW
0
t
0
0
0
Output and Decrement
(Word)
B-B-1
(C) - (HL)
HL - HL - 2
t OUTDR
0
0
•
0
Output, Decrement and
Repeat ,(Byte)
Repeat until B = 0:
B - B-1 '
(C) - (HL)
HL - HL - 1
t OUTDRW
0
0
0
0
Output, Decrement and
Repeat (Word)
Repeat until B = 0:
B-B-1
(C) - (HL)
HL- HL- 2
t OUTI
•
t
0
0
0
Output and Increment
(Byte)
B-B-1
(C) - (HL)
HL - HL + 1
t
Programmable as privileged.
615
Input/Output Instruction Group (Continued)
Flags
Instruction
t
Addressing Modes
OUTIW
S
Z
H PN
•
~
•
N
•
C
Operation
•
Output and Increment
(Word)
B-B-1
(C) - (HL)
HL - HL + 2
t
•
•
OUTIR
•
•
Output, Increment and
Repeat (Byte)
Repeat until B = 0:
B-8-1
(C) - (HL)
HL - HL + 1
t
•
•
OUTIRW
•
•
Output, Increment and·
Repeat (Word)
Repeat until B = 0:
B-B -- 1
(C) - (HL)
HL - HL + 2
t
~
~
TSTI (C)
0
P
0
•
Test Input
F - test (C)
CPU Control Group
Flags
Instruction
* Dllnt
* Ellnt
Addressing Modes
S .Z
Int = E6,E5,E4,E3,E2,
E1,EO
•
Int = E6,E5,E4,E3,E2,
E1,EO
•
* HALT
•
H PN
•
•
N
C
Operation
•
•
Disable Interrupt
If Ei then:
MSR(i) - 0;
Otherwise
MSRO _ 6 - 0
•
•
•
•
•
Enable Interrupt
If Ei then:
MSR(i) ;,.... 1;
Otherwise
MSRO _ 6 - 1
0
\
0
•
•
•
•
Halt
CPU Halts
* 1M p
p=0,1,2,3
0
0
0
0
0
0
Interrupt Mode Sel~ct
Interrupt Mode - p
* LD dst,src
dst=A
src = I,R
0
0
•
Load Accumulator from
I or R Register
A - src
t
Programmable as privileged.
• Privileged Instruction.
616
CPU Control Group (Continued)
Flags
Instruction
* LO dst,src
Addressing Modes
S
Z
H
dst= I,R
src=A
0
•
0
PN N
0
•
C
Operation
0
Load I or R Register
from Accumulator
dst - A
* LOCTL dst,src
dst = (C), USP
src = HL,IX,IY
or
dst = HL,IX,IY
src = (C),USP
•
•
•
•
•
•
Load Control
dst - src
NOP
•
0
•
•
•
•
No Operation
PCACHE
•
•
•
•
•
•
Purge Cache
e-.:l
m
~
S
~
All cache entries
invalidated
* RETI
0
•
•
0
0
•
~
eJ
Return from Interrupt
PC - (SP)
SP - SP + 2
•
* RETIL
0
•
0
•
0
Return from Interrupt
Long
PS - (SP)
SP - SP + 4
•
* RETN
•
•
0
•
0
Return from
Nonmaskable Interrupt
PC - (SP)
SP - SP + 2
MSR(O-7) - IFF(O-7)
Extended Instruction Group1
Flags
Instruction
Addressing Modes
S
Z
EPUM src
src = IR,DA,X,RA,SR,BX
•
•
H PM N
C
Operation
•
•
Load EPU from Memory
0
•
EPU - template
EPU - src
MEPU dst
dst = IR,DA,X,RA,SR,BX
0
0
0
•
•
•
Load Memory from EPU
EPU - template
dst - EPU
EPUF
~
~
0
P
0
•
Load Accumulator
from EPU
EPU - template
A-EPU
EPUI
•
•
•
•
•
•
EPU Internal Operation
EPU - template
1Refer
to the Z8070 Z8000™ Floating-Point Product Specification (document number 00-2235-01) for the floating-point
extended instructions.
• Privileged instruction.
617
EXTENDED PROCESSING
ARCHITECTURE
Features,
The Zilog Extended Processing Architecture (EPA) provides an extremely flexible and modular approach to expanding both the hardware and software capabilities of
the Z800 CPU. Features of the EPA includ~:
II
Direct Address
II
Indirect Register
Allows Z800 CPU instruction set to be extended by
external devices.
•
Indexed
•
Stack Pointer Relative
Increases throughput of the system by using up to
-four specialized external processors in parallel with
the CPU.
II
Relative
•
Base Index
II
III
Six addressing modes can be utilized with transfers between EPU registers and the CPU and main memory:
EI
Used by Z8070 floating-point EPU.
II
Permits modular
systems.
II
Provides
easy
management
of
multiple
microprocessor configurations via "single instruction stream" communication.
D
Simple interconnection between EPUs and Z800
MPU requires no additional external supporting
logic.
II
Supports debugging of suspect hardware against
proven software.
design
of
Z800
CPU-based
m EPUs can be added as the system grows and as
EPUs with specialized functions are developed.
General Description
The processing power of the Zilog Z-BUS Z800
microprocessor can be boosted beyond its intrinsic
capability by the Extended Processing Architecture
(EPA). The EPA allows the Z800 CPU to accommodate
up to four Extended Processing Units (EPUs), which perform specialized functions in parallel with the CPU's
main instruction execution stream.
The EPUs connect directly to the Z-BUS and continuously monitor the CPU instruction stream for an instruction
intended for the EPU (template). When a template is
detected, the appropriate EPU responds, obtaining or
placing data or status information on the Z-BUS by using
the Z800 CPU-generated control signals and performing
its function as directed.
The CPU is responsible for instructing the EPU and
delivering operands and data to it. The EPU recognizes
templates intended for it and executes them, using data
supplied with the template and/or data within its internal
registers. There are three classes of EPU instructions:
m Data transfers between main memory and EPU
registers
11
Data transfers between CPU registers and EPU
status registers
II
EPU internal operations
618
In addition to the hardware-implemented capabilities of
the EPA, there is an extended instruction trap
mechanism to permit software simulation of EPU functions. An EPU present bit in the Z800 MPU T"rap Controlregister indicates whether actual EPUs are present or
not. If not, when the CPU traps when an extended instruction is detected, a software "trap -handler" can
emulate the desired EPU function. Thus, the EPA software trap routine supports systems not. containing an
EPU.
EPA and CPU instruction execution are shown in Figure
17. The CPU begins operation by fetching an instruction
and determining whether or not it is an EPU instruction.
If the instruction is an EPU instruction, the state of the
EPU Enable bit in the Trap Control register is examined.
If the EPU Enable bit is reset (E = 0), the CPU generates
a trap and the EPU instruction can be simulated by an
EPU instruction trap software routine. However, if the
EPU Enable bit is set (E = 1), indicating that an EPU is
present in the system, then the 4-byte EPU template is
fetched from memory. The fetching of the EPU template
is indicated by the status lines STo-ST3. The EPU meanwhile continuously monitors the Z-BUS and the status
lines for its own templates. After fetching the EPU
template, the CPU, if necessary, transfers appropriate
data between the CPU and memory or between the CPU
and the EPU. These transactions are indicated by unique
encodings of the status lines. If the EPU is free when the
template and the data appear, the EPU template is executed. If the EPU is still processing a previous instruction, it activates the PAUSE line (Z8216 only) to halt further execution of CPU instructions until execution is
complete. After the execution of the template is complete, the EPU deactivates the PAUSE line and CPU instruction. execution continues.
r-----------'
I
YES
I
I
I
,I
NO
CPU FETCHES
EPU TEMPLATE
FROM MEMORY
I
I
I
I
1M
00
CPU GENERATES
DATA/ADDRESS
AND PLACES
ON Z·BUS
8
...c:I
::I
I1-. _ _ _ _ _ _ _ _ _ _ _
~------------~--------2---------~
SET PAUSE
LINE AT CPU
UNTIL EPU
FREE
Figure 17. EPA and Z8216 CPU Instruction Execution
MEMORY MANAGEMENT
Features
•
On-chip dynamic address translation
•
Permits addressing of large physical memory
o
o
512K bytes-40-pin devices
16M bytes-64-pin devices
•
Separate translation facilities for user and system
modes
•
Permits instructions and data to reside in separate
memory areas.
•
Write prote'ction for individual pages of memory
•
Aborts CPU on access violation to support virtual
memory
General Description
Th.e Z800 microprocessor contains an on-chip Memory
Management Unit (MMU), which translates logical addresses into physical addresses. This allows access to
more than 64K bytes of physical memory and provides
memory protection features typical of those found on
large systems. With the MMU, the CPU can access up to
16M bytes of physical memory, depending on package
size (the 40-pin package devices output only 19 address
bits). The MMU features a sophisticated trapping
mechanism that generates page fault$ on error condi-
2259'()17
tions. Instructions that are aborted by a page fault can
be restarted in a manner compatible with virtual memory
system requirements. On reset, the MMU features are
not enabled, thus permitting logical addresses to pass to,
the physical memory untranslated.
The physical address space is expanded by dividing the
64K byte logical address space (the space manipulated
by the program) into pages. The pages are then mapped
(translated) into the larger physical address space of the
Z800 microprocessor. The mapping process makes the
user software addresses independent of the physical
memory, so the user is freed from specifying where information is actually stored in physical memory. The actual size of the page depends on whether the program/data separation mode is enabled-if it is enabled,
each page is 8K bytes in length, and if it is not enabled,
the page length is 4K bytes. With the page mapping
technique, 16-bit logica'i addresses can be translated into 24-bit physical addresses (only the lower 19 bits are
externally available on 40-pin devices). Address translation can occur both in system arid in user mode, with
separate translation facilities available to each mode.
The MMU further allows instruction references to be
separated from data references, which enables programs of up to 64K bytes in length to manipulate up to
64Kbytes of data without operating system intervention.
619
MMU Architecture
The Z800 MMU consists of two sets of sixteen page
descriptor registers (Figure 18) that are used to translate
addresses, a 16-bit control register that governs the
translati.on facilities, a Page Descriptor Register Pointer,
an I/O write-only port that can be used to invalidate sets
of page descriptors, and two I/O ports for accesses to
the page descriptor registers. One set of page descriptor
registers is dedicated to the system mode of operation
and the other set is dedicated to the user mode of operation.
While an address is being translated, attributes
associated with the logical page containing that location
are checked. The correct logical page is determined by
the CPU mode (user or system), address space (program/data), and the four most significant bits of the
logical address. Pages can be write-protected to prevent
them from being modified by the executing task and can
also be marked as non-cacheable to prevent information
from being copied into the cache for later reference. The.
latter capability is useful in multiprocessor systems, to
ensure that the processor always accesses the most
current version of information being shared among multiple devices. The MMU also maintains a bit for each page
that indicates if the page has been modified.
Each page descriptor register contains a Valid bit, which
indicates that the descriptor contains valid information.
Any attempt by the MMU to translate an address using
an invalid descriptor generates a page fault. Valid bits for
groups of page descriptor registers can be reset- by
writing to an MMU control port.
o
15
Figure 18. Page Descriptor Register
For each mode of CPU operation, the MMU can be configured to separate instruction fetches from data
fetches, and thus separate the program address space
from the data address space. When the program/data
separation mode is in effect, the·sixteen page descriptor
registers for the current CPU mode of operation (user or
system) are partitioned into two sets, one for instruction
fetches and one for data fetches. A instruction fetch or
data access using the Program Counter Relative addressing mode is translated by the MMU registers
associated with the program address space; data accesses using ,other addressing modes .and accesses to
the Interrupt Vector Table in interrupt mode 2 use the
MMU registers associated with the data address space.
In this mode of MMU operation, the page size is 8192
bytes. There are two control bits in the MMU Master
Control register that independently specify whether the
user and system modes of CPU operation have separate
program and data address spaces.
620
Each 16-bit page descriptor register consists of a 4-bit
attribute field and a 12-bit page frame address field. The
attribute field consists of the least Significant bits of the
descriptor and contains four control and status bits,
listed below.
Modified (M). This bit is automatically set whenever a
write is successfully performed to a logical address in
this page; it can be cleared to
only by a software
routine that loads the descriptor register. If the Valid bit
is 0, the contents of this bit are undefined.
°
Cacheable (C). While this bit is set to 1, information
fetched from this page can be placed in the cache. While
this bit is cleared to 0, the cache control mechanism is
inhibited from retaining a copy of the information.
Write-Protect (WP). While this bit is set to 1, CPU writes
to logical addresses in this page cause a page fault to be
gener?ted and prevent a write operation from occurring.
While this bit is cleared to 0, all valid accesses are permitted.
Valid (V). While this bit is set to 1, the descriptor contains
valid information. While this bit is cleared to 0, all CPU
accesses to logical addresses in this page cause a page
fault to be generated.
'
MMU Control Registers and 110 Ports
MMU operation is controlled by one control register and
four dedicated I/O ports. The MMU Master Control
register (Figure 19) determines the program/data address space separation in effect in both user and system
modes and whether logical addresses generated in user
and system mode will be translated by the MMU. Page
descriptor registers are accessed indirectly through the
register address contained in the Page Descriptor
Register Pointer. The descriptor select port is used to access the page descriptor register that is pOinted to by the
Page Descriptor Register Pointer. After this access the
Page Descriptor Register Pointer is left unchanged. The
block move I/O port is used to move blocks of words be~
tween the page descriptor registers and memory; reads
or writes to this I/O port access data pointed to by the
Page Descriptor Register Pointer, then increment the
pointer by one. The Invalidation I/O Port is used to invalidate blocks of page descriptor registers; writes to
this port cause the Valid bits in selected blocks of page
descriptor registers to be cleared to 0, which indicates
that the descriptors no longer contain valid information.
15
IUTEIUpol
0
I 0 ISTElsPol
0
I0 I0
I I I
0
0
Figure 19. MMU Master Control Register
MMU Master Control Register. The MMU Master Control register controls the operation of the MMU. This
register contains four control bits; all other pits in this
2259'()18,019
register must be cleared to O. The four control bits of the
MMU Master Control register are described below.
Page Fault Identifier (PFI). This 5-bit field latches information that indicates which page descriptor register was
being accessed when the access violation was
detected.
System Mode Program/Data Separation Enable (SPD).
While this bit is set to 1, instruction fetches and data accesses via the PC Relative addressing mode use the
system mode page descriptor registers 8-15, and data
references that do not use the PC Relative addressing
mode use the system mode page descriptor registers
0-7. While this bit is cleared to 0, system mode page
descriptor registers 0-15 are used to translate instruction and data references.
o
System Mode Translate Enable (STE). While this bit is set
to 1, logical addresses generated in the system mode of
operation are translated. While this bit is cleared to 0,
addresses are passed through the MMU extended with
zeros in the most significant bits and no attribute checking or modified bit setting is performed.
User Mode Program/Data Space Separation Enable
(UPD). While this bit is set to 1, instruction fetches and
data accesses via the PC Relative addressing mode use
user mode page descriptor registers 8-15, and data
references that do not use the PC Relatiye addressing
mode use user mode page descriptor registers 0-7.
While this bit is cleared to 0, user mode page descriptor
registers 0-15 are used to translate instruction and data
references.
Block Move I/O Port. Block moves of data into and out
of the page descriptor registers are accomplished by
writing and reading words to or from this dedicated 110
port at location FFxxF4. Any word I/O instruction can be
used to access page descriptor registers via this port,
provided that the Page Descriptor Register Pointer is
properly initialized.
Invalidation I/O Port. Valid bits can be cleared (i.e., the
page descriptor registers invalidated) by writing to this
dedicated 8-bit port {Table 3). Individual Valid bits can
subsequently be set by software writing to the page
descriptor registers. Reading this I/O port returns unpredictable data.
Table 3. Invalidation Port Table
Encoding
Registers Invalid
System Page Descriptor Registers 0-7
System Page Descriptor Registers 8-15
System Page Descriptor Registers 0-15
User Page Descriptor Registers 0-7
User Page Descriptor Registers 8-15
User Page Descriptor Registers 8-15
User Page Descriptor Registers 0-15
Translation Mechanism
Page Descriptor Register Pointer. Moves of data into
Address Translation. Address translation is illustrated
in Figure 20. While the Program/Data Space Separation
bit is cleared to 0, the 16-bit logical address is divided into two fields, a 4-bit index field used to select one of 16
page descripto~ registers, and a 12-bit offset field that
forms the lower 12 bits of the physical address. The
physical address is composed of the 12-bit page frame
address supplied by the selected page descriptor
register and the 12-bit offset supplied by the logical address.
and out of the MMU page descriptor registers use the
Page Descriptor Register Pointer. This 8-bit register contains the address of one of the page descriptor registers.
When a word 110 instruction accesses 110 address
FFxxF5 (descriptor select port), this register is used to
access a page descriptor register. When a word 110 instruction accesses 110 address FFxxF4 (block move 110
port), this register is also used to access a page descriptor register, but after the access, this register is
automatically incremented by one.
While the ProgramlData Space Separation bit is set to 1,
the logical address is divided into a 3-bit index field and a
13-bit offset field. The page descriptor register consists
of an 11-bit Page Frame Address field. The physical address is a result of concatenating the page frame address and the logical offset. The page descriptor register
. is chosen by a 4-bit index field, which consists of a Pro. gram/Data Address bit from the CPU and the three Index
bits from the logical address.
User Mode Translated Enable (UTE). While this bit is set
to 1, logical addresses generated in the user mode of
operation are translated. While this bit is cleared to 0
addresses are passed through the MMU extended with
. zeros in the most significant bits and no attribute checking or modified bit setting is performed.
0
Descriptor Select Port. Moves of on'e word of data into
and out of a page descriptor register are accomplished
by writing and reading words to or from this dedicated
110 port at location FFxxF5. Any word 110 instruction can
be used to access a page descriptor register via this
port, provided that the Page Descriptor Register Pointer
is properly initialized.
621
15
I
INDEX
L:15
J
I
J
OFFSET
4
}
LOGICAL
ADDRESS
0
3
0
15
"-
PAGE FRAME
ADDRESS
PAGE DESCRIPTOR
REGISTERS
ATTRIBUTE
~USER
~
V
/ " " SYSTEM
I¥
0
oI
I
~
23
I
0
I}
~____P_AG_E_F_R_A_M_E_AD_D_R_ES_S____~_________
O_FF_S_ET________~_
PHYSICAL
ADDRESS
Figure 20. Address Translation
ON-CHIP MEMORY
Features
the system or used as a cache for instructions or data.
Its. mode of use (dedicated memory or a cache) is programmable; on reset it is automatically enabled for use
as a cache for instructions only.
•
256-byte local memory
•
Configurable as high-speed cache
•
Programmable to cache instructions, data or both
On·Chip Memory Architecture
•
Permits faster execution by minimizing external bus
accesses
•
Operation is transparent to user
•
Configurable as local RAM with user-definable addresses
The on-chip memory is organized as 16 lines of 16 bytes
each. Each line can hold a copy of 16 consecutive bytes
in physical memory locations whose 20 most significant
bits of physical address are identical. Each byte in the
cache has an associated Valid bit that indicates whether
the cache holds a valid copy of the memory contents at
the associated physical memory location. Figure 21 illustrates the cache organization_
The Z800 MPU has 256 bytes of on-chip memory, which
can be dedicated to memory locations programmed by
20 BITS
16 BITS
16 x 8 BITS
~~r~------------------A------------------~,
LINE 0
LINE 1
LINE 2
TAG 0
VALID
BITS
CACHE DATA
TAG 1
VALID
BITS
CACHE DATA
TAG 2
VALID
BITS
CACHE DATA
•
•
•
•
•
•
•
•
TAG 15
VALID
BITS
•
•
LINE 15
CACHE DATA
Tag n = the 20 Address bits associated with line n
Valid bits = 16 bits that Indicate which bytes In the cache contain valid data
Cache data
16 bytes
=
Figure 21. Cache Organization
622
2259-020, 021
The on-chip memory has two modes of operation. If the
Memory/Cache bit in the Cache Control register is set to
1, then the 256 bytes of on-chip memory are treated as
physical memory locations. Memory accesses to addresses covered by the on-chip memory do not generate
bus transactions on the external bus and hence the accesses are faster. In this mode, the valid bits are ignored.
If the Memory/Cache bit is cleared to 0, then the 256
bytes of on-chip memory are treated as a cache
memory. The lines are allocated using a least-recently
used (LRU) algorithm. When a cache "miss" on a read
occurs (and the MMU does not assert cache inhibit), the
line in the cache that has been least recently accessed
is selected to hold the newly read data. All bytes in the
selected line are marked invalid except for the bytes
containing the newly accessed data. On a cache miss,
one or two bytes, depending on the bus size, are fetched
from main memory. Except for burst mode instruction
fetches, the cache does not pre-fetch beyond the
currently-requested address. A cache miss on a data
write does not cause a line to be allocated to the
memory location accessed.
wdte is to a valid location in the cache but the LRU
mechanism is unaffected. Also, for the EPU to memory
transfer, if the cache contains valid locations that are updated by an EPU transaction, the on-chip cache is also
updated.
Cache Control Register. The operation of the on-chip
memory is controlled by an 8-bit Cache Control register
(Figure 22) that is accessed using a load control instruction. This register contains five control bits; all other bits
must be cleared to o.
7
0
IM/cl I I 0 ILMBEBI 0 I 0 I 0 I
Figure 22. Cache Control Register
The bits in this register are:
High Memory Burst Capability (HMB). This 1-bit field
specifies whether a memory burst transaction occurs
when the MMU is enabled and there is a 1 in bit 15 of the
selected page descriptor register (0 = burst mode not
supported, 1 = burst mode supported).
The cache can hold both instructions and data. Two control bits in the Cache Control register can be separately
set to enable the cache to hold instructions and to hold
data. If the cache contains data, writes to data at locations contained in the cache also cause external bus
transactions to update the appropriate memory location.
Low Memory Burst' Capability (LMB). This 1-bit field
specifies whether' a memory burst transaction occurs
when the MMU is disabled or when the MMU is enabled
and there is a zero in bit 15 of the selected page descriptor register (0
burst mode not supported, 1
burst
'
mode supported).
Both the CPU and the on-chip DMAs access the cache.
For the CPU, if the MMU is enabled, the access can be
either cacheable or non-cacheable, depending on the
value of the Cacheable bit in the page descriptor register
used to translate the logical address. If the MMU is not
enabled, all memory transactions are considered to be
cacheable. Two bits in the Cache Control register, the
Cache Instruc.tions Disable bit and the Cach~ Data
Disable bit, further determine the operation of the cache_
for various situations. These bits enable the cache for instructions and for data.
Cache Data Dis~b/e (D) . .While this bit is cleared to 0,
data fetches are copied into the cache if the M/C bit = 0
(cache mode). If M/C = 1, the state of this bit is ignored.
When the on-chip memory is used as fixed memory locations, neither the Cache Instruction Disable or Cache
Data Disable bits are used, and no distinction is made as
to whether the CPU is accessing data or instructions.
In general, when devices such as on-chip DMAs transfer
data to the memory, the cache data is modified if the
=
=
Cache Instructions.Disable (/). While this bit is cleared to
0, instruction fetches are copied into the cache when the
M/C bit = 0 (cache mode). When M/C = 1, the state of
this bit is ignored.
Memory/Cache (M/C). While this bit is set to 1, the onchip memory is to be accessed as phYSical memory;
while it is cleared to 0, the memory is accessed \
associatively as a cache.
If the on-chip memory is to be used as fixed memory
locations, the user can programmably select the ranges
of memory addresses for which the on-Chip memory
responds.
CLOCK OSCILLATOR
The Z800 MPU has an on-chip clock oscillator/generator
that can be connected to a crystal or any suitable clock
source. The bus timing clock generated from the on-Chip
2259-022
oscillator is output for use by the rest of the system. The
f~eql.Jency of the processor clock is one-half that of the
fundamental frequency of the crystal.
623
REFRESH
The Z8aa MPU has an internal mechanism for refreshing
dynamic memory. This mechanism can be activated by
setting ·the Refresh Enable bit in the Refresh Rate
register to 1. Memory refresh is performed periodically
at a rate specified by the Refresh Rate register. Refresh
transactions are identical to memory transactions except that different status signals are used and no data is
transferred. They can be inserted immediately after the
last clock cycle of any bus transaction, including an internal operation.
A 1a-bit refresh address is generated for each refresh
operation with the refresh address being incremented by
two between refreshes for 16-bit bus versions, and by
one for 8-bit bus versions.
While the Refresh Enable bit is set to 1, the value of the
6-bit Rate field in the Refresh Rate register determines
the time between successive refreshes (the refresh
period). When ·Rate = a, the refresh period is 256 processor clock cycles; when Rate = n (n > a) the refresh
period is 4n. The Rate and Refresh Enable control bits
are programmed via an I/O instruction.
enables the refresh mechanism and specifies the frequency of refresh transactions.
The refresh transaction is generated as soon as possible
after the refresh period has elapsed (generally after the
last clock cycle of the current bus transaction). If the
CPU receives an interrupt request, the refresh operation
is performed first. When the Z8aa CPU does not have
control of the bus or is in the wait state, internal circuitry
records the number of refresh periods that have elapsed
and refresh cycles cannot be generated. When the CPU
regains control of the bus or the Wait input signal is
deactivated and the bus transaction completes, the
refresh mechanism immediately issues the skipped
refresh cycles. The internal circuitry can record up to
256 such skipped refresh operations.
On reset, refresh is enabled, the rate is 32 processor
clock cycles, and the refresh address is not affected.
The Refresh mechanism is controlled by an 8-bit control
register, described below.
Refresh Rate Register. This 8-bit register (Figure 23)
Figure 23. Refresh Rate Register
The fields in this register are:
Refresh (Rate). This field indicates in processor clock
cycles the rate at which refresh transactions are to be
generated; a value of n in this field indicates a refresh
period of 4n, with Rate = a indicating 256 clock cycles.
Refresh Enab/e (E). When this 1-bit field is set to 1, the
refresh mechanism is enabled.
UART
The Z8aa UART transmits and receives serial data using
any common asynchronous data-commun,ication protocol.
Transmission and reception can be performed independently with five, six, seven, or eight bits per
character, plus optional even or odd parity. The transmitter can supply one or two stop bits and can provide a
break output at any time. Reception is protected from
spikes by a "transient spike-rejection" mechanism that
checks the ·signal one-half a bit time after a Low level is
detected on the receiver data input; if the Low does not
persist-as in the case of a transient-the character
assembly process is not started. Framing errors and
overruns are detected and buffered with the partial
character on which they occur. Furthermore, a built-in
checking process avoids interpreting a framing error as
a new start bit: a framing error results in the addition of
one-half a bit time to the point at which the search for the
next start bit is begun.
The UART uses the same clock frequency for both the
transmitter and the' receiver. The input for the UART
clocking circuitry is derived from counter/timer a, either
624
from its external input line for an external clock or from
the counter/timer output for a bit rate generatec,j from the
internal processor clock. The UART input clock is further
scaled by 1, 16, 32, or 64 for clocking the transmitter and
receiver.
Two of the DMA channels can be used independently to
move characters between memory and the transmitter
or receiver without CPU intervention. Both the transmitter and receiver can interrupt the CPU for processor
assistance.
The UART uses two external pins, Transmit and Receive.
Data that is to be transmitted is placed serially on the
Transmit pin and data that is to be received is read in
from the Receive pin.
Asynchronous Transmission
_ The Transmitter Data Output line is held marking (High)
when the transmitter has no data to send. Under program control, the Send Break command can be issued to
hold the Data Output line Low (spacing) until the command is cleared.
2259-023
The- UART automatically adds the start bit, the programmed parity bit (odd, even, or no parity), and the programmed -number of stop bits to the data character to be
transmitted. When the character is five, six, or seven
bits, the unused most significant bits in the Transmitter
Data register are automatically ignored by the UART.
Serial data is shifted from the transmitter at a rate equal
to 1, 1/16th, 1/32nd or 1/64th of the clock rate supplied to
the transmitter clock input (as determined by the clock
scale field in the UART Configuration register). Serial
data is shifted out on the falling edge of the clock input.
Asynchronous Reception
An asynchronous receive operation begins when the
Receive Enable bit in the Receiver Control/Status
register is set to 1. A Low (spacing) condition on the
Receive input line indicates a start bit. If this Low persists for at least one-half of a bit time, the start bit is
assumed to be valid and the data input is then sampled
at mid-bit time until the entire character is assembled.
This method of detecting a start bit improves error rejection when noise spikes exist on an otherwise marking
line. If the x 1 clock mode is selected, bit synchronization must be accomplished externally; received data is
sampled on the rising edge of the clock.
A received character can be read from the 8-bit Receiver
Data register. The receiver inserts 1s when a character
length of other than eight bits is used. Ifparity is enabled,
the parity bit is not stripped from the assembled
character for character lengths other than eight bits. For
lengths other than eight bits, the receiver assembles a
character length of the required number of data bits,
plus a parity bit and 1s for any unused bits.
Since the receiver is buffered by one 8-bit register in addition to the receiver shift register, the CPU has enough
time to service an interrupt and to accept the data
character assembled by the UART. The receiver also
has a buffer that stores error flags for each data
character in the receive buffer. These error flags' are
loaded at the same time as the data character.
After a character is received, it is checked for the follow-ing error conditions:
I!l
Parity Error: when the parity bit of the character
does not match the programmed parity.
c
Framing Error: if the character is assembled without
any stop bits (i.e., a Low level is detected for a stop
bit).
fJ
Receiver Overrun Error: if the CPU fails to read a
data character when more than one character has
been received.
The Parity Error, Framing Error, and Receiver Overrun
Error cause an interrupt request if the interrupt request
capability is enabled. Since the Parity Error and Receiver
Overrun Error flags are latched, the error status that is
2259-024
read reflects an error in the current character in the
Receiver Data register plus any Parity or Overrun Errors
detected since the last write to the Receiver Control/Status register. To keep correspondence between
the state of the error buffers and the contents of the
receiver data buffers, the Receiver Control/Status
register must be read before the data.
Polled Operation
In a polled environment, the Receive Character
Available bit in the Receiver Control/Status register must
be monitored so the CPU can know when to read a
character. This bit is automatically cleared when the
Receiv~r Data register is read. To prevent overwriting
data in polled operations, the transmitter buffer status
must be checked before writing into the transmitter. The
Transmit Buffer Empty bit in the Transmitter Control/Status register is set to 1 whenever the transmit buffer is empty.
UART Control and Status Registers
The UART operation is controlled by three control and
status registers. The UART configuration register
specifies the character size and parity, the clock source
and scaling and loop-back enable. Both the transmitter
. and the receiver have their own control/status register.
UART Configuration Register. This 8-bit register
(Figure 24) contains control information for both the
transmitter and receiver.
7
,aIC
I I I I
p
ElO cs
0
CR
I I'
LB
Figure 24. UART Configuration Register
The control fields for this register are:
Loop Back Enable (LB). The UART is capable of local
loopback. In this mode the internal transmit data line is
tied to the internal receiver line and the external receiver
input is ignored. If this bit is set to 1, loop mode is enabled.
Clock Rate (CR). These two bits specify the multiplier
between the clock and data rates (00 = data rate x 1,
01 = data rate x 16, 10 = data rate X 32, 11 = data
rate X 64). The same rate is used for both the receiver
and transmitter. If the X 1 clock rate is selected, bit synchronization must be accomplished externally.
Clock Select (CS). This bit specifies the clock input for
, the UART. If the bit is set to 1, the counter/timer 0 output
pulse is used for bit-rate generation; if the bit is cleared
to 0, the input line to counter/timer 0 provides the clock
from an external source.
Parity Even/Odd (E/O). If parity is specified, this bit determines whether it is sent and checked as even or odd (1
= even).
625
Parity (P). If this bit is set to 1, an additional bit position
(in addition to those specified in the bits/character control field) is added to transmitted data and is expected in
received data. In the Receiver, the parity bit received is
transferred to the CPU as a part of the character, unless
eight bits/character is selected.
Bits/Character (B/C). Together, these two bits determine
the number of bits to form a character. If these bits are
changed during the time that a character is being
assembled, the results are unpredictable (00 = 5
bits/character, 01 = 6 bits/character, 10 = 7 bits/
character, 11 = 8 bits/character).
Transmitter Control/Status Register. This 8-bit
register (Figure 25) specifies the operation of the
transmitter.
7
I
EN liE
0
I 0 IS6 16RKIFRCIVALI BE
Transmitter Enable (EN). While this bit is cleared to 0,
data is not transmitted and the transmitter output is held
marking. Data characters in the process of being
transmitted are completely sent if this bit is cleared to 0
after transmission has started.
Receivor Control/Status Register. This 8-bit register
(Figure 26) specifies the operation of the receiver. The
control bits are described below.
7
I
EN liE
0
I 0 ICA IOVEI PE I FE IERRI
Figure 26. Recolver Control/Status Register
I
Receiver Error (ERR). This bit iS'the logical OR of the PE,
aVE, and FE bits.
Figure 25. Transmitter Control/Status Register
The control bits for this register are:
Transmitter Buffer Empty (BE). This bit is automatically
set to 1 whenever the transmitter buffer becomes empty,
and cleared to 0 when a character is loaded into the
transmit buffer. This bit is in the set condition after
reset. This bit is controlled by the UART control circuitry,
it can be read by an I/O read but cannot be set to 1 or
cleared to 0 by an I/O write.
a
Value (VAL); This bit determines the value of the bits
transmitted while the FRC bit is 1 and dummy characters
are loaded into the transmitter buffer. When this bit is 1,
a mark character (all 1s) is sent; when this bitis 0, a
break character (aliOs) is sent.
Force Character (FRC). When this bit is set to 1, any
character loaded into the transmitter buffer causes the
transmitter output to be held High or Lo'v'v' (as indicated
by the VAL bit) for the length of time required to transmit
a char)cter; the character itself is not sent until after the
current character is transmitted. This allows a program
to generate a marking signal or a break of multiplecharacter duration simply by setting this bit to 1, setting
the VAL bit to 1 or 0, and loading the appropriate number
of dummy characters into the transmitter buffer.
Send Break (BRK). When set to 1, this bit immediately
forces the transmitter output to the spacing condition,
regardless of any data being transmitted. When this bit is
cleared to 0, the transmitter returns to marking.
Stop Bits (SB). Jhis bit determines the number of stop
bits added to each asynchronous character sent. The
receiver always checks for one stop bit. If this bit is set
to 1, two stop bits are automatically appended to the
character (and parity) sent; if this bit is cleared to 0, only
one stop bit is appended.
626
Transmitter Interrupt Enable (IE). When this bit is set to
1, interrupt requests are generated whenever the
transmitter buffer becomes empty; when this bit is
cleared to 0, no requests are made.
Framing Error (FE). This bit is automatically set to 1 for
the received character in which the framing error occurred. Detection of a framing error adds an additional onehalf of a bit time to the character time so the framing error is not interpreted as a new start bit. The bit is latched,
so once an error occurs it remains set until the bit is
cleared by software writing to this register.
Parity Error (PE). When parity is enabled, this bit is
automatically set to 1 for those characters whose parity
does not match the programmed sense (even/odd). This
bit is latched, so once an error occurs, it remains set until it is cleared by software writing to this register.
Receiver 'Overrun Error (OVE). This bit is automatically
set to 1 to indicate that more than two characters have
been received without a read from the CPU (or. DMA).
Only the most recently received character is flagged
with this error, but when this character is read, the error
condition is latched until cleared by software writing to
this register.
,Receiver Character Available (CA). This bit is
automatically set to 1 when at least one character is
available in the receive buffer; it is automatically cleared
to 0 when the Receiver Data register is read. This bit is
controlled by the UART control circuitry; it can be read
by an I/O read but cannot be set or cleared by an I/O
write.
Receiver Interrupt Enable (IE). While this bit is set to 1,
interrupt requests are generated whenever the receiver
detects an error or the receiver has a character
available.
Receiver Enable (EN). When this bit is set to 1, receiver
operations begin. This bit should be set only after, the
parameters in the UART Configuration register are set.
2259-025, 026
UART Bootstrapping Option
DMA Master Control register-DOR and EOP set
The Z800 CPU supports an automatic initialization of
memory via the UART after a reset operation. This
system bootstrapping capability permits ROMless
system configurations: the memory can be initialized by
a serial link before the Z800 CPU fetches information
from memory after the reset.
Count register-01 00 (256 bytes to be transferred)
Destination Address register-OOOOOO (starting memory
address = 0)
Source Address register-undefined (not used when
DMAO is linked to UART)
On the rising 'edge of reset, the AD lines are sensed; if
AD6 is being driven High, the Z800 CPU automatically
enters a Halt state. The UART is also automatically initialized to receive 8-bit character data with odd parity at
a X 16 clock rate. An external clock source is assumed.
A minimum of 15 processor clock cycles must elapse
before the transmission can begin.
Characters received are placed in memory starting at
physical memory location zero. If an error occurs, the
Z800 CPU drives the Transmitter Output line Low. External circuitry monitoring this line can use this Signal to
cause the transmitting device to begin the initialization
procedure again, starting with a reset and AD6 asserted
on the rising edge of RESET.
During the bootstrapping operation, DMA Channel 0 is
used to transfer received characters into the memory.
This channel is initialized as follows:
After 256 bytes of data have been transferred,the Z800
CPU automatically begins execution by fetching the first
instruction from memory location O.
Transfer Descriptor register-IE, EPS, and "'(C cleared,
ST-byte transfer, BRP-continuous, TYPE-flowthrough,
DAD-Auto-increment memorx address
DMA CHANNELS
The Z800 MPU has four on-Chip Direct Memory Access
(DMA) channels to provide high bandwidth data
transmission capabilities. There are two types of DMA
channels; two support flyby transactions and the other
two do not. The two types of DMA channels otherwise
have identical capabilities, although they have different
priorities with respect to interrupt requests and bus requests.
Each DMA channel is a powerful and versatile device for
controlling and processing transfers of data. Its basic
function of managing CPU-independent transfers between two ports Is augmented by an array of features requiring little or no external logic in systems using an 8- or
16-bit data bus.
Transfers can be performed between any two ports
(source and destination), including memory-to-I/O, I/O-tomemory, memory-to-memory, and I/O-to-I/O. Except for
flyby, two port addresses are automatically generated
for each transaction and can be either fixed or incrementing/decrementing.
During a transfer, a DMA channel assumes control of
the system address and data bus. Data is read from one
addressable port and written to the other addressable
port, byte-by-byte or word-by-word. The ports can be programmed to be either system main memory or
peripheral I/O devices.
.
For both flyby and flowthrough DMA transactions, if the
destination is a memory location that corresponds to an
entry in the on-chip memory (either cache or fixed
memory location), the on-Chip memory is updated to
reflect the new contents of the memory location.
Except in flyby mode, two 24-bit addresses are
generated by the DMA for every transfer operation, one
address for the source port and another for the destination port. Two readable address counters (three bytes
each) keep the current address of each port.
The DMA devices use the same memory and I/O timing
as the CPU for bus transactions, as indicated by the appropriate bus timing register.
Modes of Transfer Operation
Each DMA can be programmed to operate in one of
three transfer modes: '
o
Single Transaction. Data operations are performed
one byte or word at a time.
o
Burst. Data operations continue until a port's Ready
line to the DMA goes inactive.
o
Continuous. Data operations continue until the end
of the programmed block of data is reached or if an
end of process has been signaled before the SYSt(;;:T1
bus is released.
In all modes, once a byte or word of data is read by the
DMA channel, the operation is completed in an orderly
fashion, regardless of the state of other signals (including a port's Ready line).
Pin Descriptions
Each DMA channel has a Ready input line. In addition,
two DMA channels have a flyby output line to support
high speed data transfers between I/O devices and
memory.
627
The flyby output is asserted by the DMA channel to
signal a peripheral device associated with the DMA
channel that it should participate in the data transmission during the current flyby bus transaction.
The Ready line is sampled on the rising edge of each processor clock cycle. If Ready is active, the DMA channel
requests control of the external system bus to perform
the DMA transaction. When the external system bus is
available for DMA transfers, the DMA channel with a request pending and the highest priority assumes bus
mastership. The priority of DMA channels from highest
to lowest is: DMAO, DMA 1, DMA2, and DMA3. A DMA
channel in burst mode relinquishes bus mastership to a
higher priority DMA channel only when its Ready line is
deasserted (or Eap is signaled or terminal count is
reached). A DMA channel in continuous mode relinquishes bus mastership only when Eap is signaled or
terminal count is reached.
Priority of On·Chip DMA Channels and External
Bus Requesters
The on-chip DMA channels are arranged in a daisy chain
with the external Bus Request input line being the "next
lower bus requester" on this chain. The on-chip DMAs
behave as if they were external bus requestors with
respect to acquiring the bus, relinquishing the bus, and
priority access to the bus.
End·of·Process
If the end-of-process (Eap) capability is enabled,
transfers by DMA channels can be prematurely terminated by a Low on Interrupt A line during the transfer.
This capability is programmed by a control bit in the
DMA Master Control register. Eap occurs regardless of
the setting of the Interrupt A Enable bit in the Master
Status register. ,When an Eap is signaled, the EOP
Signaled (EPS) bit in the Transaction Descriptor register
of the active DMA channel is set to 1 and the Enable bit
is cleared to O. If interrupt requests are enabled (IE = 1
in the Transaction Descriptor register), an interrupt request is generated by the channel that was active when
the Eap was signaled. After an Eap has been Signaled,
the DMA relinquishes the bus within 16 cycles of the last
DMA bus transaction.
If the End-Of-Process signal on Interrupt A line is still
asserted when the CPU is bus master, the Signal is interp,reted as an interrupt request; thus both the DMA channel and the external EOP generating device can request
interrupts simultaneously. Separate mask bits in the
Master Status register enable the CPU to accept interrupts from these two sources.
On a flowthrough transaction, if the Eap signal is received while the information is being read into the Z800
MPU, the transfer is aborted and the data is not written
out from the Z800 MPU.
628
DMA Linking
The DMA devices can be linked together to achieve
DMA transfers to non-contiguous memory locations
(linked operation). Bits in the DMA Master Control
register allow DMA3 to be linked to DMA 1 and DMA2 to
be linked to DMAO, when DMAO and DMA1 have flyby
capabilities. If the appropriate bit is set to 1 in the DMA
Master Control register, the master DMA (0 or 1) signals
its linked DMA each time its transfer is complete (count
= 0). This acts a? an internal ready input to the linked
DMA that reloads the master DMA control' registers.
Words are loaded into the master DMA control registers
in the following order: Destination Address register (two
words), Source Address register (two words), Count (one
word), Transfer Descriptor register (one word). After six
words have been transferred, the master DMA deasserts its internal ready line and begins the transfer of
the next block of data. The linked DMA can be programmed to interrupt the CPU on "count equal 0" (to notify
software that the last block is being transferred) or the
master DMA can be programmed to interrupt the CPU on
"count equals 0" when the last block move is programmed into the master DMA (to notify software that the entire sequence of transfers is completed). When linking is
enabled, the external Ready line is not asserted by the
master DMA when count equals zero; also, both master
and linked DMAs generate interrupts whenever the programmed condition arises.
When programming linked DMAs, the last word to be
programmed must be the master DMA's Transaction
Descriptor register. Also, the linked DMA must be programmed before the master DMA's status register is
programmed.
DMA Master Control Register. This 16-bit register
(Figure 27) specifies the general configuration of the four
on-chip DMA channels: the linking of the DMA channels,
the software ready enables, edge detection enables for
the Ready lines, and EOP enable.
15
Figure 27_ DMA Master Control Register
The fields in this register are:
OMAO to Receiver Link (0 OR). When this bit is set to 1,
DMA channel 0 is linked to the UART receiver.
OMA 1 to Transmitter Link (01 T). When this bit is set to 1,
DMA channel 1 is linked to the UART transmitter.
OMA2 Link (02L). When this bit is set to 1, DMA channel
2 is linked to DMA channel O.
2259-027
DMA3 Link (D3L). When this bit is set to 1, DMA channel
3 is linked to DMA channel 1.
End-of-Process (EOP). When this bit is set to 1, the INTA
line is used as an end-of-process signal for the active'
DMA channel.
Software Ready for DMAO (SRO). When this bit is set to 1,
DMA channel 0 requests service if enabled.
Software Ready for DMA 1 (SR1). When this bit is set to 1,
DMA channel 1 requests service if enabled.
Enable Count n (fen). When bit ECn is set to 1, edge
detection circuitry is enabled on Ready line n.
DMA Channel Control Registers
Transaction Descriptor Registers. These four 16-bit
registers, one for each channel, (Figure 28) describe the
type of DMA transfer to be performed and contain control and status information.
15
I I
EN
SAD
liE
I
ST
BRP
TYPE
I I
TC
DAD
I
EPsl
Figure 28. Transaction Descriptor Register
The fields in this register are:
Transaction Type (Type). This 2-bit field specifies flyby or
flowthrough type of operation or count option (00 =
flowthrough, 01 = count option, 10 = flyby write, 11 =
flyby read). In flowthrough mode of operation, two bus
transactions occur for each DMA operation-a read
from the source followed by a write to the destination. In
a flyby operation, only one bus transaction occurs for
each DMA operation. In flyby write to memory, the flyby
output pin is pulsed instead of an I/O transaction being
performed and the contents of the Destination Address
register are output to specify the memory location. In
flyby read from memory, the flyby output pin is pulsed instead of an I/O transaction being performed and the contents of the Source Address register are output to
specify the memory location. Only two DMAs have flyby
capability. In the count option type of operation, the DMA
acts as a counter and the BRP field governs the counting
frequency; the "count each" option decrements the
count register once for each High-to-Low transition on
the Ready line while the DMA enable bit is set to 1; the
gate option decrements the count register once for eactl
eight internal processor clock cycles while the Ready
line is Low and the DMA enable bit is set to 1.
Bus Request Protocol (BRP). The setting of these two
bits indicates the mode of DMA operation (Table 5); their
interpretation depends on whether the channel is programmed for DMA operations or with' the count option.
End-of-Process Signaled (EPS). This bit is set to 1
automatically when the channel is active and an end-ofprocess is signaled on the Interrupt A input line, thus
prematurely terminating the transfer.
Destination Address Descriptor (DAD). The setting of
this 3-bit field indicates the type of location (memory or
I/O) and how the address is to be manipulated (incremented, decremented or left unchanged), as shown
in Table 4.
Table 4. SAD and DAD Encodlngs
Encoding
Address Modification Operation
o0 0
Auto-increment memory location
Auto-decrement memory location
Memory address unmodified by transaction
Reserved
Auto-increment (by 1) 1/0 location
Auto-decrement (by 1) I/O location
I/O address unmodified by transaction
Reserved
o0 1
o1 0
01 1
100
1 01
110
111
Table 5. Bus Request Protocol (BRP)
0
0
when the count register has reached zero.
2259-028
Single Transaction
Burst
Continuous
Reserved
0
1
0
CounteriTimer
Count each
Gated count
Continuous gated count
Reserved
Size of Transfer (ST). This 2-bit field specifies the size of
the entity to be transferred by the DMA channel (Table
6). For word transfers to or from memory locations, the
memory address must be even (least significant bit is 0).
Long word (32-bit) transfers are supported only in flyby
mode, with the cache disabled.
Table 6. Size of Transaction (S1)
Encoding
ST1 STO
0
0
Transfer Complete (TC). This bit is set to 1 automatically
DMA
Encoding
0
1
0
Size of
Transfer
Byte
16-bit word
32-bit longword
Reserved
Number to Increment!
Decrement By
2
4
629
Interrupt Enab/e (/E). When this bit is set to 1, the DMA
generates an interrupt request at end of count or end of
process. When this bit is 0, no interrupt request is
generated.
Source Address Descriptor (SAD). The setting of this
3-bit field indicates the type of location (memory or 110)
and how the address is to be manipulated (incremented,
decremented or left unchanged), as shown in Table 4.
for the bus transaction as indicated in the Mode field in
the Transfer Descriptor register. The format for these
registers is shown in Figure 29.
15
I
I
0
Count Register. This 16-bit register is programmed to
contain the number of DMA transfers to be performed.
When the contents of the count register reach zero, further requests on the RDY input line are ignored. The
DMA channel can be programmed to generate an interrupt when the count register reaches zero.
Source Address Register and Destination Address
Register. These 24-bit registers contain the 24-bit
physical addresses to be used during the DMA transaction. They are not translated by the MMU. In flyby mode,
only one of these registers is used to supply the address
0
o
I
A11
0
• • • • • • • • • • Aol
15
A23
DMA Enab/e (EN). While this bit is 1, the DMA transfer is
enabled.
0
0
• • • • • • • • • •
A121 0
0
0
o
I
Figure 29. Source and Destination Address
Registers Format
Flyby Transaction Timing
The Transaction Type field in the Transaction Descriptor
register indicates whether the transaction is a read or a
write. For flyby read transactions, the Source Address
Descriptor indicates the transaction is a read from
memory; for write flyby transactions the Destination Address Descriptor indicates the transaction is a write to
memory. Additional wait states can be automatically inserted if programmed in the appropriate timing register.
COUNTER/TIMERS
The l800 MPU's four counter/timers can be programmed by system software for a broad range of counting
and timing applications. The four independently programmable channels satisfy common microcomputer
system requirements for event counting, interrupt and interval timing, and general clock generation.
Three of the four Gounter/timers can have external input;
the fourth can be used only in the timing mode.
Programming the counter/timers is straightforward:
each channel is programmed with four bytes. Once
started, the channel counts down, and optionally reloads
its time constant automatically and resumes counting.
. Software timing loops are completely eliminated. Interrupt processing is simplified because each channel uses
,a unique vector from the InterruptlTrap Vector Table.
Each channel is individually programmed with three
registers: a configuration byte, a control byte, and a
time-constant word. The configuration byte selects the
operating mode (counter or timer), enables or disables
the channel interrupt, and selects certain other
operating parameters. In the timing mode, the CPU processor clock is divided by four for input to the
counter/timers. The time-constant word contains a value
from a to 65,535.
During operation, the individual counter channel counts
down from the present time-constant value. In counter
mode operation, the counter decrements on each of the
input pulses until the count/time output condition is met.
Each decrement is synchronized by the scaled internal
processor clock. For counts greater, than 65,536, two of
630
the counters can be programmably cascaded. When the
count/time output condition is reached, the downcounter
is automatically reset with the time constant value, if so
programmed.
The timer mode determines time intervals without additional logic or software timing loops. Time intervals are
generated by dividing the internal processor clock by
four and decrementing a presettable downcounter.
Thus, the time interval is an integral multiple of the processor clock period, the prescaler value four, and the
time constant that is preset in the downcounter. A timer
is triggered by setting the software trigger control bit in
the Control/Status register or by an external input.
Three channels can generate an external output when
the count/time output condition is met. The output is high
when the internal presettable downcounter contains all
zeros.
Each channel can be programmed to generate an Interrupt Request, which occurs only if the channel has its Interrupt Enable control bit set to 1 by software programming. When the l800 CPU accepts the interrupt request
it automatically vectors through the Interrupt Vector
Table.
The four channels of the l800 MPU are fully prioritized
and fit into four different slots in the l800 internal
peripheral daisy-chain interrupt structure. Channel a has
the highest priority and Channel 3 has the lowest. The.
channels have separate interrupt enables and the CPU's
Master Status register has individual control bits that'
selectively inhibit interrupts from each channel.
2259-029
Gate Operation. A counter/timer can be programmed to
count or time only when a gating condition is met. While
the counterltimer is enabled and the external gate
capability is selected, an external input line is monitored;
only while this line is High are the counting or timing
operations performed. The software gate facility filters
the state of the input line; while the software gate bit in
the Command and Status register is cleared to 0, the
gating condition is not met regardless of the signals on
the gating line. The gate facility is illustrated in Figure 30.
Modes of Operation
Three of the counter/timer channels have two basic
modes of operation: ,as counters or as timers. As
counters they monitor external input lines and record
Low to High transitions on these lines. In the timer mode,
the processor clock, scaled by.tour, is used instead of
the external input line. The duration of this counting or
timing can be either continuous from initial enabling (trigger operation) or only during intervals specified by
signals on an input line (gate and gate/trigger operation).
The count can be automatically 'restarted by programming the Retrigger Enable control bit in the
counter/timer's Configuration register. Channel number
2 has no external inputs, and thus operates only as a
timer.
Trigger Operation. A counter/timer can be programmed
to count or time only after a triggering condition occurs.
While the counter/timer is enabled and the external trigger capability is programmed, an external input line is
monitored; only after this line makes a Low-to-High transition is a counting or timing operation performed. The
software trigger facility causes the triggering condition
to be met regardless of the activity of this line. The trigger operation is illustrated in Figu re 31.
Each of the four counter/timers has a software gate and
trigger facility that extends the hardware capabilities of
the counter/timers.
Counting Operation. While the appropriate enabling
conditions are met, the counter/timer monitors its input,
line for Low-to-High transitions. When sLich a transition
occurs, the CountlTime register is decremented by 1.
Timing Operation. While the appropriate enabling conditions are met, the counter/timer monitors the internal
processor clock scaled by four for Low-to-High transitions. When such a transition occurs the Count/Time
register is decremented by 1.
Gate/Trigger Operation. One input line can be used for
both the gating and the triggering functions. A Low-toHigh transition on this line acts as a trigger and subsequent High signals on this line function as gate signals. If
non-retriggerable mode is programmed, subsequent
Low-to-High transactions do not cause a trigger.
Gate/Trigger Operation is shown in Figure 32.
GATE
INPUT _ _ _ _ __
Lfl_____......Ir-u-l__
COUNTER
OR TIMER _ _ _...
COUNTITIME
REGISTER
DECREMENTED
*
*
*
Figure 30_ Gate Facility
TRIGGER
INPUT _ _ _ _ _ _ _ _ __
n
COUNTER
LINE _ _ _ _...
COUNTITII'.'IE
REGISTER
DECREF.'ENTED
_ __n___
_ _ _ _ _...
*
Figure 31. Tr'igger Operation
2259-030, 031
631
GATE
~TRIGGER
OATEITRIOOER
INPUT
-.1l
COUNTER
LINE
n
COUNTITIME
REOISTER
DECREMENTED
GATE
LJ
LJ
n
n
*
*
Figure 32. GateITrigger Operation
The software gate and trigger mechanism can also be
used in this mode of operation. A software gate before a
trigger (hardware or software) has no effect on the
counter/timer. After a hardware or software trigger, the
software gate must be set to 1 for the Count/Time
register to be decremented. A software trigger after a
hardware or software trigger has no effect unless the
Retrigger Enable control bit is set to 1.
CounterlTimer Control and Status Registers
Each counter/timer has two 8-bit control registers and
two '16-bit count registers. The Configuration register
and Command and Status register determine the
counter/timers's operation, the Counter/Timer Com~
mand/Status register provides information about the current operation, the Time Constant register contains the
initialization value for the counter/timer, and the
Count/Time register contains the current value ot the
count in progress.
Counter/Timer Configuration Register. This 8-bit
register (Figure 33) specifies the counter/timer's mode
of operation: the pin configuration, whether an interrupt
request is generated, and whether the countdown sequence is automatically restarted when the count
reaches zero or when a trigger occurs.
ICIS I
RE
liE ICTc·1
IPA
'CTC Is present on counter/timers
o and 2 only.
Figure 33. CounterlTimer Configuration Register
The fields in this register are:
Input Pin Assignments (IPA). This 4-bit field specifies the
functionality of the input lines associated with the'
counterltimer and whether the counter/timer monitors
an external input (counting operation) or uses the scaled
internal processor clock (timing operation). The four bits
in this field can be associated with enabling output
generation (EO), selecting the external signal or internal
clock (C/T) , enabling the gating facility (G), and enabling
the triggering facility (T). The selected options determine
the functions associated with each input line associated
with the counter/timer, as illustrated in Table 7.
Counter/Timer Cascade (CTC). When this bit is set to 1,
counter/timers 0 and 1 and/or counter/timers 2 and 3
form a 32-bit counter. When used as 32-bit counter/
timers, the control and status registers corresponding to
counter/timers 0 and 2 are not used, with the exception
Table 7. Input Pin Functionality
EO
0
0
0
0
0
0
0
0
IPA Field
CIT G
0
0
0
0
0
0
T
0
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0
O·
0
0
1
0
1
1
0
0
0
1
0
632
Pin Functionality
CounterlTlmer Input
CounterlTlmer 1/0
Unused
Unused
Gate
Gate
Unused
Trigger
Gate
GatelTrigger
Output
Output
Output
Output
Output
Unused
Unused
Unused
Unused
Trigger
Unused
Trigger
Input
Input
Input
Input
Unused
Trigger
Gate
GatelTrigger
Input
Unused
Unused
Unused
Notes
Timer
Timer
Timer
Timer
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
Counter
Reserved
Reserved
Reserved
2259-032, 033
of the CTC bits in the counter/timer configuration
registers. The CTC bits in the counter/timer configuration
registers of counter/timers 1 and 3 are never used.
interrupt Enab/e (IE). While this bit is set to 1 the
counter/timer generates an interrupt request when the
count/time output condition is met. While this bit is no
interrupt request is generated.
°
Retrigger Enab/e (RE). While this bit is set to 1, the time
constant value is automatically loaded into the
·Count/Time register when· a trigger input is received
while the counter/timer is counting down. While this bit is
0, no reloading occurs.
Continuous/Single Cycle (C/S). While this bit is set to 1,
the countdown sequence is automatically restarted .
when the count reaches zero by loading the time constant value into the CountlTime register. While this bit is
0, no reloading occurs.
Counter/timer channel 2 can be programmed as a
counter. However, since it has no external inputs to
count, this is not a useful mode of operation.
Counter/Timer Command/Status Register. This 8-bit
register (Figure 34) provides software control over the
operation of the counter/timer and reflects the current
status of the counter/timer's operation. Control bits in
this register enable the counter/timer's operation and
provide software gate and trigger capabilities. Status
bits indicate whether a count is in progress, the
count/time output condition has been reached, or the
condition has been reached a second time.
7
I
EN I GT I TG
0
I 0 I 0 ICIP I cc ICORI
Figure 34_ CounteriTimer Command/Status Register
The fields of this register are:
Count Overrun (COR). When this bit is set to 1 the
count/time output condition has been reached and the
CC bit is set to 1, thus indicating a count overrun condition. While this bit is cleared to 0, the count/time output
condition has not been reached with the CC bit set since
the time the CC bit was cleared by software. This bit can
be read or written (set or cleared) by software I/O instructions.
CounVTime Output Condition has been Met (CC). When
this bit is set to 1 the CountlTime register has been
decremented to zero by the counter/timer control circuitry in single cycle mode, or the CountlTime register
has been reloaded in continuous mode. When this bit is
cleared to the count has not reached the count/time
output condition since the bit was cleared by software.
This bit can be read or written (set or cleared) by software I/O instructions.
°
2259-034
Count in Progress (C/P). While this bit is set to 1 the
counter/timer is operating and the CountlTime register is
non-zero; while this bit is cleared to the counter/timer
is not operating. This bit is controlled by the
counter/timer control circuitry; it can be read by an 110
read but cannot be set or cleared by an I/O write instruction.
°
Software Trigger (TG). When this bit is set to 1. (and the
trigger operation of the counter/timer is enabled), if the
Enable bit is also set to.1, the trigger operation is enabled on the rising edge of the first processor clock
period following the setting of this bit from a previously
cleared value. That is, if a hardware trigger has not
already occurred, the contents of the Time Constant
register are loaded into the CountlTime register and the
countdown sequence begins. If a hardware trigger has
already occurred, then if Retrigger Enable is set to 1, the
counter/timer is retriggered; otherwise, setting this bit
has no effect. Writing a 1 in this field when the previous
value was 1 has no effect on the operation of the
counter/timer. When this bit is cleared to zero, this bit
has no effect on the operation of the counter/timer.
Software Gate (GT). When this bit is set to 1 (and the gate
operation of the counter/timer is enabled), if the Enable
. bit is also set to 1, operation begins on the rising edge of
the first processor clock period following the setting of
this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the
operation of the counter/timer. When this bit is cleared to
0, the countdown sequence is halted.
Enab/e (EN). While this bit is set to 1, the counter/timer is
enabled; operation begins on the rising edge of the first
processor clock period following the setting of this bit
from a previously cleared value. Reset clears this bit.
While this bit is cleared to 0, the value in the Time Constant register is. constantly transferred to the Count/Time
register. If the Time Constant register is all zeros, the
output of the counter/timer is one. Thus, when the
counter/timer is not enabled, the counter/timer output in
conjunction with the Time Constant register can be used
as an I/O port. Writing a 1 in this field when the previous
value was 1 has no effect on the operation of the
counter/timer. While this bit is 0, the counter/timer performs no operation during the next (and subsequent)
processor clock periods.
Time-Constant Register. This 16-bit register holds the
value that is automatically loaded into the Count/Time
register when the counter/timer is enabled, or in the continuous or retrigger mode when the count reaches zero
or the trigger is asserted, respectively. This register can
be read or written by I/O instructions.
Count/Time Register. This 16-bit register holds the current value of the count or timing in progress. It is automatically loaded from the Time-Constant register, and
can be read by software using the I/O read instructions.
633
Pin Descriptions
Counter/timers 0, 1, and 3 have two external input lines
associated with them. The I/O lines transfer signals between the counter/timers and external devices. The input lines receive signals from external devices for the
counter/timers. The interpretations of the signals on
these lines is determined by the Input Pin Assignment
field in the Configuration register.
MULTIPROCESSOR MODE OF
OPERATION
Features
•
Allows global memory areas for shared resources
•
Global memory addresses are user-specified
•
Separate requests for local and global buses
•
Requesting mechanism is transparent to user
•
Easily interfaces to external arbiters
One mode of operation for the l800 MPU is as an I/O
Processor (lOP); while in this mode, the l800 MPU also
supports multiprocessor conf!gurations. While operating
as an lOP, the l800 MPU is able to support both a local
bus (of which the l800 MPU is the default bus master)
and a global bus (for which the l800 MPU must request
the bus and receive a bus grant signal before issuing a
bus transaction.)
To accomplish this functionality, two pins previously
used for the counter/timer 0 peripheral are dedicated to
be global bus request and global bus grant lines; thus
this feature is available only in the 64-pin devices. A
register in the l800 MPU bus interface unit is accessed
for each bus transaction to determine whether the
physical address must be accessed via the global or
local bus.
Architecture
Pin Functionality. Two pins are used by the lOP for obtaining the global bus: the Global Request line is used to
request the global bus, one which the CPU does not control by default (counter/timer 0 input/output), and the
Global Acknowledge line receives an acknowledge of a
global bus request (counter/timer 0 input).
Local Address Register. The bus interface unit
distinguishes whether a bus transaction uses the local or
global bus by comparing the four most significant bits of
the physical address of memory (address bits 20 through
23) with a 4-bit Base field in the local Address register
(Figure 35). A mask field in this register specifies which
bits are to be used. If all the corresponding address bits
match the Base field bits (for those bit positions
specified by the mask field), then the bus transaction can
proceed on the local bus without requesting the global
bus; if there is a mismatch in at least one specified bit
position, then the global bus is be requested and the bus
transaction does not proceed until the global bus
acknowledge Signal is asserted.
634
7
IME2~ME22IME21IME201 B231 B221 B21 1 B20
0
I
Figure 35. Local Address Register
The bits in the local Address register are:
Base (Bn). When Bn is 1, address bit An must be 1 for a
local bus transaction to be performed (unless Match
Enable bit MEn is 0); when bit Bn is 0, address bit An must
be 0 for a local bus transaction to be performed.
Match Enable (MEn). When MEn is 1, address bit An is
compared to base bit Bn to determine if the address requires the use of the global bus. When MEn is 0, then any
values for An and Bn will produce a match. If each MEn is
. 0, then all bus transactions are performed on the local
bus.
CPU Accesses on the Global Bus
The control of the local bus uses BUSREQ and BUSACK
in the same way as in the non~multiprocessor mode of
operation. The input Signal BUSREQ is. asynchronous to
the processor clock; the CPU synchronizes BUSREQ internally. When the CPU acknowledges a local bus request by driving BUSACK active, then the CPU places all
other output signals, including GREQ, in 3-state. After
reset the CPU acknowledges a request for the local bus
before performing any transactions.
When the CPU has not granted the local bus then it can
request a global bus. A timing diagram for global bus request is shown in Figure 36. First, on a rising edge of
ClK, the CPU drives the address and status lines valid.
AS is not asserted, however; GREQ serves the function
of indicating that a valid address is on the local bus. On
the next falling edge of ClK the CPU drives GREQ active.
The CPU samples GACK on each falling edge of ClK until the arbiter drives GACK active and leaves BUSREQ inactive, indicating that the addressed global bus is
available to tne CPU. The BUSREQline is used by the arbiter to remove all of the devices that are simultaneously
requesting the global bus, except the one device that is
granted the global bus. The devices that are not granted
the global bus make their GREQ inactive. The input
Signal GACK is asynchronous to the processor clock; the
CPU synchronizes GACK internally. The CPU that was
granted the bus performs one or more transactions on
the global bus until the CPU no longer needs the global
2259-035
DMA Accesses on the Global Bus
bus or the CPU is prepared to acknowledge a local bus
request. The CPU then drives GREQ inactive and wa~ts
for the arbiter to drive GACK inactive. The CPU relInquishes the global bus upon receipt of a local bus, DMA,
or refresh request or after any transaction except for a
test and set instruction (both data read and write are performed before relinquishing the bus) and for burst
transfers (the entire sequence of data reads are made).
Each on-chip DMA device can use the global bus to perform data transfers. The address generated during each
DMA initiated transfer is compared with the contents of
the Local Address register to determine whether the
global bus is requested; this operation is the same as for
CPU-generated requests.
I_T_I-T_I-T1-1
~J
I I I I
ADDRESSI
DATA
HIGH
STo-ST3
R/W
B/W
Figure 36. Multiprocessor Mode Timing
EXTERNAL INTERFACE (ZaO·BUS)
Features
BUSACK. Bus Acknowledge (output, active LOW). A Low
on this line indicates that the CPU has relinquished control of the bus in response to a bus request.
Ell
8-bit data bus
a
Multiplexed address/data lines
BUSREQ. Bus Request(input, active LOW}. A Low on this
EJ
Supports Z80 Family peripherals
line indicates that an external bus requester has obtained or is trying to obtain control of the bus.
Pin Descriptions
A. Address (output, active High, 3-state). These address
lines carry I/O addresses and memory addresses during
bus transactions. Of the 16 lines, only 11 are available
on the 40-pin version.
AD. A"ddresslData (bidirectional, active High, 3-state).
These eight multiplexed Data and Address lines carry I/O
addresses, memory addresses, and data during bus
transactions.
AS. Address Strobe (output, active Low, 3-state). The rising edge of AS indicates the beginning of a transaction
and shows that the address is valid.
2259·036
ClK. Clock Output (output). The frequency of the processor timing clock is derived from the oscillator input
(external oscillator) or crystal frequency (internal
oscillator) by dividing the crystal or external oscillator input by two. This clock is further divided by one, two, or
four (as programmed), and then output on this line.
HALT. Halt (output, active Low, 3-state). This Signal indicates that the CPU has executed a Halt instruction and
is awaiting an interrupt before operation can resume.
INT. Maskable Interrupts (input, active Low). A Low on
one is available on the 40-pin version.
635
lORa. InpuVOutput Request (output, active Low,
3-state). This signal indicates that ADo-AD7 and A16-A23
of the address bus hold a valid 1/0 address for a 1/0 read
or write operation. An 10RO signal is also generated with
an M1 signal when an interrupt is being acknowledged,
to indicate that an interrupt response vector can be
placed on the data bus. Interrupt acknowledge operations occur during M1 time and 1/0 operations never occur during M1 time.
M1. Machine Cycle One (output, active Low, 3-state).
This signal indicates that the current transaction is the
opcode fetch cycle of a RETI instruction execution. M1
also occurs with lORa to indicate an interrupt
acknowledge cycle.
MREa. Memory Request (output, active Low, 3-state).
This signal indicates that the address bus holds a valid
address for a memory read or write operation.
NMI. Nonmaskable Interrupt (input, falling-edge activated). A High-to-Low transition on this line requests a
nonmaskable interrupt.
RD. Read (output, active Low, 3-state). This signal indicates that the CPU or DMA peripheral is reading data
from memory 9r an 1/0 device.
RESET. Reset (input, active LOw). A Low on this line
resets the CPU and on-chip peripherals.
RFSH. Refresh (output, active Low, 3-state). This signal
indicates that the lower ten bits of the Address bus contain a refresh address for dynamic memories and the
current MREO signal should be used to perform a
refresh read to all dynamic memories.
WAIT. Wait (input, active LOw). A Low on this line indicates that the responding device needs more time to
complete a transaction.
WR. Write (output, active Low, 3-state). This signal indicates that the bus holds valid data to be stored at the
addressed memory or I/O location.
>.u (or on-chip DMA channel in nonFlyby transactions) places the same byte on both halves
of the bus, and the proper byte must be selected by
testing Ao. For word transfers, (R/W = Low), all 16 bits
are captured by the CPU or DMA channel (Read: RIW =
High) or stored by the memory (Write: RIW = Low). For
these transactions (either memory or I/O) the bytes of
data appear swapped on the bus with the most significant byte on ADrADo and the least significant byte on
AD15-ADa·
Memory transaction timings are shown in Figures 46-50.
647
3-1
I-
Tl - I - T 2 - I -T
.J
I
ADO-AD 15
ADDRESS
STATUS
STATUS VALID
B/W
R/W = 1
IE*
·Z8216 only.
m = 18 lor Z8116, 23 lor Z8216.
Figure 46. Memory Read Timing
1 I
ADDRESS
I
r
;x
+VAUD
ADDRESS
STATUS
RIW
B/W
0
=
IE·
STATUS VALID
HIGH
'Z8216 only.
m = 18 lor Z8116, 23 for Z8216.
Figure 47. Memory Write Timing
648
2259-046, 047
!-T1-j_T2_I_Tw_!-T3_1
I
---1
ADo-AD15
ADDRESS
STATUS
DIW
RIW = 1
STATUS VALID
oe*
IE*
·Z8216 only.
m = 18 for Z8116, 23
for Z8216.
Figure 48. Memory Read Timing with External Wait Cycle
!-T1--_. . . .---T2_!-TW--_. +I··---
---1
_ I__
I
ADo-AD15
DATA VALID
STATUS
DIW
RIW = 0
STATUS VALID
oe*
IE*
HIGH
·Z8216 only.
m = 18 for Z8116, 23
for Z8216.
I
Figure 49. Memory Write Timing with External Wait Cycle
2259-048, 049
649
ADO-AD15
ADDRESS
STATUS
R/W
STATUS VALID
B/W
1
=
OE*
IE*
'Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 50. Memory Read Timing with Internal Wait Cycle
Burst Memory Transactions. Burst memory transac·
tions use multiple Data Strobes associated with a single
Address Strobe. The CPU uses burst transactions to
read four consecutive words in four data transactions~
The address of the first word read during a burst transaction has zeros in the three least significant bits. Control
bits in the Cache Control register indicate whether or not
portions of-the memory system can support burst transactions.
The CPU uses burst mode reads only for fetching instructions. If an instruction is to be fetched from a location within a half of physical memory that supports burst
transactions, the CPU reads the eight bytes that contain
the first byte of the instruction. (EPA template fetches
and the RETI instruction do not use the burst
transaction.)
Timing for the first data transfer during a burst transaction is identical to that for a single memory read, including the automatic insertion of wait states, except
there are four T3 states. Subsequent data transfers do
not include automatic wait states. On the first data
transfer, if WAIT is sampled active then it is sampled
again every bus clock cycle until it is inactive, at which
time the data is read from the bus. Burst memory read
timing is shown in Figure 51,
650
Internal Operation and Halt Transactions. Two types
of bus transactions made by the CPU do not transfer
data: Internal Operations and Halt transactions. These
transactions look like a memory transaction, except that
DS remains High and no data is transferred.
For tile Internal Operation transaction (Figure 52), the
Address lines contain arbitrary data when AS goes High.
The R/W line indicates Read (High) and the Status lines
indicate Internal Operation (0000).
A Halt transaction (Figure 53) is generated when the
CPU executes a Halt instruction or when a fatal sequence of traps and bus errors. occurs. The address
placed on the AD lines is the location of the Halt instruction or the instruction that initiated the fatal sequence of
traps and errors. The Status lines indicate a Halt transaction (0011).
WAIT is not sampled during the Internal Operation or
Halt transaction.
2259'()50
I_Tl-j_T2-1-'r3-I-T4-I_Ts_I_T6_1·
~
I
ADo-AD15
ADDRESS
STATUS
STATUS VALID
D/Vi
R/Vi = 1
D5
WAIT
IE·
·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 51. Burst Me~ory Read Timing
I _ T l - I -T2 - I -T3 - 1
~
I
ADo-AD15
UNDEFINED
STATUS
= 0
R/W = 1
B/VI
STATUS VALID
HIGH
IE·
·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figura 52. Internal Operation Timing
2259'{)51, 052
651
3-1
I _ T l - I -T2 - I -T
ADO-AD15
ADDRESS
STATUS
BIW
RIW
=0
=1
STATUS VALID
HIGH
OE**
iE* *
• Address of Halt Instruction.
• ·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 53. Halt Timing
1/0 Transactions. I/O transactions (Figures 54 and 55)
move data to or from peripherals and are generated during the execution of 1/0 instructions. 1/0 transactions to
on-chip peripheral devices do not generate external bus
transactions.
1/0 transactions are four bus cycles long at a minimum,
and they can be lengthened by the addition of wait
cycles either automatically generated as indicated in the
Bus Timing and Control register or generated by an external device. The extra clock cycles allow for slower
peripheral operation.
The status lines indicate that the access is an 1/0 transaction (0010). The 1/0 address is found on ADo-AD15 and
A16- A23'
Interrupt Acknowledge Transactions. These transactions (Figure 56) acknowledge an interrupt and read an
identifier from the device that generated the interrupt. Interrupt Acknowledge transactions are generated
automatically by the hardware when an interrupt is
detected.
These transactions are five cycles long at a minimum,
with at least two automatic wait cycles, although others
can be added by programming the Bus Timing and Control register. The wait cycles are used to give the interrupt priority daisy chain (or other priority resolution
device) time to settle before the identifier is read.
Byte data (BIW = High) is transmitted on ADo-AD? This
allows peripheral devices to attach to only eight of the
AD lines. The ReadlWrite line (RIW) indicates the direction of the data transfer: peripheral-to-CPU (Read: RIW
High) or CPU-to-peripheral (Write: RIW = Low).
=
652
2259-053
DATA VALID
ADO-AD15.
STATUS
STATUS VALID
B/W
R/W
=0
IE·
'Z8216 only.
m = 18 for Z8116, 23 for Z8216.
HIGH
I
Figure 54. I/O Write Timing
-i
I -Tl - I -T2 - I - T w - - - I -T3
--1
ADO-AD15
-K
I
ADDRESS
-
-
STATUS
B/W
R/W
= 1
-
,
,"-
"-
DATA
"-
f
ADDRESS
rLJ
STATUS VALID
/
WAIT
~
IE·
\
'Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 55. 110 Read Timing
2259'()54, 055
653
3_1
I _ T L A S T - I - T 1 - I _T2 _ I _Tw _ I _ Tw - I _ T
---1
/
I
J
I
UNDEFINED·
ADO-A D 15
."
/
I
"-
DATA
r
>-
~
UNDEFINED
STATUS
B/W
0
R/W
1
=
=
STATUS VALID
/ \
I \
OE**
\
/
* AD, and AD2 Indicate the type 01 interrupt being acknowledged.
** Z8216 only.
m
= 18 lor Z8116, 23 lor Z8216.
Figure 56. Interrupt Acknowledge Timing
The Status lines identify the type of interrupt that is being
acknowledged. The possibilities are nonmaskable interrupt (0101) and the three external interrupt
acknowledges (0100, 0101 and 0111). No address is
generated; the contents of the bus are undefined when
AS rises. The RIW line indicates Read (High), and the
BIW line indicates Word (Low). .
The only item of data transferred is the identifier that is
captured from the AO lines on the falling clock edge just
before OS is raised High. The length of time that OS is
asserted is identical with 1/0 timing programmed in the
Bus Timing and Control register.
There are two places where WAIT is sampled and thus a
wait cycle can be inserted by external devices. The first
place serves to delay the falling edge of OS to allow the
daisy chain a longer time to settle, and the second place
serves to delay the point at which data is read.
Refresh Transactions. A memory Refresh transaction
(Figure 57) is generated by the refresh mechanism and .
654
can come immediately after the final clock cycle of any
other transaction. The memory refresh counter's 10-bit
address is output on the low order 10 bits of the bus during the first cycle of the transaction. The contents of the
rest of the bus are undefined. The Status lines indicate
Refresh (0001). This transaction can be used to generate
refreshes for dynamic RAMs. Refreshes may occur
while the CPU is in the Halt or Fatal state.
CPU· Extended Processing Unit Interaction
The l800 CPU with a loBUS interface and PAUSE input
line (Le., the l8216) and one or more Extended Processing Units (EPUs) work together like a single CPU component, with the CPU providing address, status, and timing
signals and the EPU supplying and capturing data. The
EPU monitors the status and timing Signals output by the
CPU so that it knows when to participate in a memory
transaction; for EPU to memory transfers, the CPU puts
its AO lines in 3-state while OS is Low, so that the EPU
can use them.
2259-056
I - l - I - 2 - I - 3-1
T
T
T
r
.J
ADO-AD15
UNDEFINED
STATUS
=
BIW
0
RIW = 1
STATUS VALID
II
GO
HIGH
8
II
d
IE··
'10 least·significant bits are Refresh address.
"Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 57, Memory Refresh Timing
In order to know which transaction it is to participate in,
the EPU must track the following sequence of events:
•
•
When the CPU fetches the first word of an EPA instruction template from memory (ST3-STO = 1101),
the EPU must also capture the instruction returned
by the memory. The template has an 10 field that indicates whether or not the EPU is to execute the instruction. Because there is no alignment restriction
on EPA templates, the 10 field can not be in the first
word fetched.
The next non-refresh transaction by the CPU is the
fetching the second word of the instruction (ST3-STO
= 1100). The EPU must also capture this word. If
the template is not aligned, a third fetch is made
(ST3-STO = 1100).
m If the instruction involves a read or write to memory,
then transfers of data between memory and the EPU
(ST3-STO = 1010) are the next non-refresh transactions performed by the CPU. The EPU must supply
the data (Write: R/W = Low) or ·capture the data
(Read: R/W = High) for each transaction, just as if it
were part of the CPU. In both cases, the CPU
3-states its AD lines while data is being transferred
(OS Low).
2259-057
D
If the instruction involves a transfer from the EPU to
the Z800 MPU, the next non-refresh transaction is
the CPU transferring data between the EPU and CPU
(ST3-STO = 1110).
In order to follow this sequence, an EPU has to monitor
the status lines to verify that the transaction it is monitoring on the bus was generated by the CPU. In a multiple
EPU· system, there is no indication on the bus as to
which EPU is cooperating with the CPU at any given
time. This must be determined by the EPU.s from the EPA
templates they capture.
When an EPU begins to execute an extended instruction,
the CPU can continue fetching and executing instructions. If the EPU wishes to halt the CPU from executing
another instruction or bus transaction, the EPU must activate the PAUSE line to stop the CPU until the EPU is
ready for subsequent CPU activity. This mechanism is
used to sy.nchronize CPU-EPU activity.
EPU Transfer Transactions. These transactions
(Figures 58-60) move data between the CPU and an EPU,
thus allowing the CPU to transfer data to or from an EPU
or to read or write an EPU's status registers. They are
generated during the execution of the EPA instruction.
655
When a request is m~de, it is. answered according to its
type: for interrupt requests, an Interrupt Acknowledge
transaction is initiated by the CPU; for bus requests, an
acknowledge signal is sent; for global bus request, an
acknowledge signal is received.
EPU-to-Memory transfers are five cycles unless extended by Wait. Memory to EPU transfers are three cycles
unless extended by WAIT.
EPU-CPU transfer transactions have the same form as
I/O transactions and thus are four clock cycles long,
unless extended by WAIT. Although AS is asserted, no
address is generated and the contents of the bus are
undefined; only one status code is used (1110).
Interrupt Requests. The Z800 MPU supports two types
of external interrupt, maskable and nonmaskable (NMI).
The Interrupt Request line of a device that is capable of
generating an interrupt may be tied to any of the interrupt pins. Several d~vices can be connected to one pin,
with the devices arranged in a priority daisy chain. The
CPU uses the same protocol for handling requests on
these pins. The sequence of events is given below:
In a multiple EPU system, the EPU that is to participate
in a transaction is selected implicitly by the ID code in
the EPU template, rather than by an address. The
Read/Write line (R/W = High) indicates the direction of
the data transfer into the CPU.
Any High-to-Low transition on the NMI input is asynchronously edge-detected, and the internal NMI latch is
set. At the beginning of the last processor clock cycle of
any instruction, the interrupt inputs are sampled along
with the state of the internal NMI latch.
Requests
The Z800 MPU supports three types of request signal.
These are:
•
Interrupt requests, which another device initiates
and the CPU accepts an'd acknowledges.
•
Bus requests, which an external potential bus
master initiates and the CPU accepts and
acknowledges.
•
Global bus requests, which the CPU or on-chip DMA
initiates to acquire a global system bus.
If a maskable interrupt is requested and the Master
Status register indicates that requests on that line are to
be accepted, or if the NMI latch is set, the next possible
bus transaction is an interrupt acknowledge transaction
that results in an identifier from the highest-priority interrupting device being read off the AD lines. ThiS data is
3-1
l-i-
I -T
A D o-AD15
- K
-
UNDEFINED
=
STATUS
BIW
RIW = 1
T2 - I - T w - I -T
~
f
/
'\.
\.
DATA
f
UNDEFINED
L.I
-
STATUS VALID
/
\
---\
IE·
·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 58. EPU to CPU Timing
656
2259-058
I_Tl-I-Tw-I-T2-I-T3-I-Tw-1
r--
~I
ADO- AD 15
-
STATUS
B/W
R/W:;:: 0
-(
ADDRESS
\.
f
f
\.
\.
f
EPU DATA VALID
ADDRESS
~
-
STATUS VALID = 1010
.....:...
/
~
iE*
HIGH
·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
Figure 59. EPU Write to Memory
I -Tl - I -T2 _ I -T3 - 1
~
I
ADo- AD 15
ADDRESS
STATUS
B/W
R/W
STATUS VALID
=1
·Z8216 only.
m = 18 for Z8116, 23 for Z8216.
IE*
Figure 60. Memory to EPU Timing
2259-059, 060
657
used to initiate the interrupt service routine. For a nonmaskable interrupt request in interrupt mode 0, 1, or 2,
an interrupt acknowledge transaction is not generated;
the hexidecimal constant 0066 is used to initiate the interrupt service routine.
Bus Requests. To generate transactions on the bus, a
potential external bus master (such as a DMA Controller)
must gain control of the bus by making a bus request. A
bus request is initiated by pulling BUSREQ Low. Several
bus requesters can be wire ORed to the BUSREQ pin;
priorities are resolved externally to the CPU, usually by a
priority daisy chain.
The asynchronous BUSREQ signal generates an internal
BUSREQ, which is synchronous. If the external BUSREQ
is Low at the beginning of any processor clock cycle, the
internal BUSR6Q will cause the bus acknowledge line
(BUSACK) to be asserted after the cu rrent bus transaction is completed or after the write transaction of a TSET
instruction. The CPU then enters Bus Disconnect state
and gives up control of the bus. All l800 Output pins except BUSACK are 3-stated.
The on-chip DMA channels have higher priority than the
off-chip devices requesting the external bus via
BUSREQ.
(de-asserted), the state of th~ Wait line is also noted: if
WAIT is asserted, then the contents of the AD lines on
the falling edge of the clock are usedto program the content of the Bus Timing and Initialization register, otherwise the constant 00 hexadecimal is used. If the hardware programming option is used, AD6 is used to enable
the bootstrap via UART option.
After reset, the following control registers are initialized
as follows:
E!I
Program Counter, System Stack Pointer, I, and R
registers initialized to a
D
Master Status register-initialized to 0, e.g., system
mode of operation; single-step mode, Breakpoint-onHalt and all maskable interrupts disabled
It
1/0 Page register-I/O page
..
Stack Limit register cleared
EI
Refresh register-initialized to 88, e.g., refresh
enabled, rate = 32 clock cycles
II
Cache Control register-initialized to 00, e.g. cache
enabled for program only (associative rather than
fixed location); also, all lines invalid
CJ
Memory Management Unit Master Control
register-initialized to 0, e.g., translation disabled
[]
Trap Control register-initialized to 0, e.g., Stack
Warning disabled, EPA disabled, 1/0 not privileged
!ill
All peripheral control registers-peripheral disabled
(but see UART bootstrap option)
D
-Interrupt Status register-Interrupt Mode
RESET
A hardware reset puts the l800 MPU into a known state
and optionally initializes the Bus Timing and Initialization
control register of the l800 MPU to a system specifiable
value. A reset begins at the end of any processor clock
cycle if the RESET line is Low. However, if abus transaction is in progress it is allowed to be completed. A
system reset overrides all other operations of the chip,
including interrupts, traps and bus requests. A reset
should be used to initialize a system as part of the powerup sequence.
VJithin 128 processor clock cycles of the RESET line
becoming Low, the l800 lines assume their reset values.
For either bus, the AD lines are 3-stated, and all control
outputs are forced High. While RESET is asserted, the
clock output is the processor clock frequency scaled by
fou r. RESET must be held low at least 128 processor
clock cycles.
The Reset line is sampled on the rising edge of the clock
output during ·reset. When the Reset line is sampled High
658
a in use
a
The following registers are unaffected:
G
CPU register file, including user Stack Pointer
Ii]
Page Descriptor registers
r::l
Interrupt/Trap Vector Table Pointer register
On the rising edge of RESET, if Bus Request is asserted
the l800 MPU will grant the bus before fetching the first
instruction from location O.
After RESET has returned to High, the CPU begins to
operate unless the Bootstrap UART feature is utilized.
PIN ASSIGNMENTS
The pin assignments of four versions of the 2800 MPU,
the 28108, 28208, 28116 and 28216 are shown in
Figures 61-64 respectively.
+5V
A21
AlO
A22
Ala
All
Aa
Aa
A23
AI2
RDY3
AI3
All
Au
AI7
Als
AI!
DMASTBo
RDY2
Hill
AD7
DMASTBI
RDYI
WR
iiFSH
ADe
IORQ
AD.
AIO
+5V
All
Aa
Au
Aa
A13
AI8
OE
RDYo
AI.
A17
aND
OND
A15
Au
IE
RX
HALT
AD7
M1
AD3
\VA
ADe
MREQ
A~
RFSH
ADs
CTIOo
TX
IORQ
AD.
AD
aND
aND
AD3
AS
MREQ
AD2
XTAlI
AD
ADI
XTALo
AS
ADo
ClK
XTAlI
ClK
WAIT
RESET
CTIN3
INTc
ADa
ADu
ADa
AD13
ADI.
All
AI7
ADIS
BIW
AD7
Ale
ADe
ADs
A22
Ala
ADa
A23
ADa
ADu
RDV3
ADI3
Ala
ADI.
A17
ADI5
Ala
ADs
ST1
AD4
be
ROVo
aND
aND
IE
ST2
ST3
CTIOo
os
CTINo
ST2
ST3
AD3
AD2
XTAll
os
ADI
XTAlo
AS
ADo
ClK
AD2
TX
ADI
CTINI
ADo
OOA
NMI
BUS-REO
lNfB
NM1
BUSREQ
CTIN3
lNfc
lNfA
XTALo
RESET
+5V
Z811~
AS
RX
AD3
CTI0 3
WAIT
XTAlI
225~1,062,063,064
STo
AD.
Figure 63.
ROYI
ADa
aND
WAIT
RDY2
AD7
RIW
STI
BUSACK
+5V
ADII
OND
ClK
+5V
A20
DMASTBI
ADII
33
ADIO
BNi
+5V
PAUSE
32
Figure 62. Z8208 Pin Assignments
DMASTBo
ADlo
INTB
BUSACK
A21
RNi
STo
NMI
BUSREQ
BUSREQ
Figure 61. Z8108 Pin Assignments
Pin Assignments
CI
OOA
WAIT
CTIOI
:c
DId
CTINI
CTI03
+5V
0
0
ADo
OOA
NMI
RESET
BUSACK
N
CO
ADI
CTINo
M1
XTALo
ADs
BUSACK
CTiOI
RESET
pAUSE
+5V
Flguro 64. Z8216 Pin Assignments
659
,000
Family
Zilog
Pioneering the
Microworld
,I
iPrt®wfiailes II @::. affil@
~~cj]JfiR
~Jii~l?a.DllD l?@a!(EH39(fl)l? ~aDll unUllcn)llLlS
September. 1983
Zilog continues its tradition of
state-of-the-art microprocessor
components with the introduction
of the 32-bit Z80,OOO CPU and the
Z8070 floating-point Arithmetic Processing Unit (APU). These two
devices bring the performance of
super minicomputers and mainframe computers into the realm of
microprocessor-based systems.
The advances in VLSI technology
used in these integrated circuits
herald a major breakthrough in the
range of options available to the
systems designer.
The Z80,000. The Z80,OOO CPU
provides the flexibility of a 16-bit or
32-bit system configuration with
the performance of a 32-bit CPU.
Oriented to applications in which
high throughput is required, its file
of 16 general-purpose registers
handles bytes, words, and long
words with equal facility. The rich
instruction set combines powerful
addressing modes and operations
in a manner that aids assemblylanguage coding of time-critical applications, and still provides the
completeness desirable for efficient compiler-generated code.
The Z80,OOO CPU can be configured under software control to
use 16-bit logical addresses (ideally suited for high-speed controller
applications) or 32-bit addresses
(for large-system tasks). The 32-bit
address modes support both a
linear addressing space and an
alternative segmented addressing
space, which are selected by the
user according to the application's
requ i rements.
Other system features include
System and Normal modes of
operation, a sophisticated trapping
mechanism, a high-performance
bus structure, and built-in
multiprocessor support. Finally, the
device has a high-performance
interface to the Z8070 Arithmetic
Processing Unit so that the two
devices can operate in tandem to
execute floating-point instructions
in the CPU's instruction stream.
An on-chip cache and a memory
management unit (MMU), coupled
with a sophisticated instruction
pipeline, enable the Z80,OOO to execute instructions at a rate of up to
. one instruction per processor cycle. The 256-byte cache provides
an automatic buffering mechanism
to hold the most recently fetched
instructions and data on the chip
itself. Thus, subsequent references
to these items do not require
lengthy memory transactions but
instead can be fetched in a single
processor cycle. The memory
management unit on the chip contains all the information needed to
translate the most recently used
logical addresses generated by the·
CPU into the phYSical addresses
used by the memory system. With
each address translation, access
attributes are automatically
checked to determine whether or
not the access is permitted. The
MMU can be used to implement a
virtual memory or can be disabled
entirely for applications that do not
need memory management.
Peripheral Support. The Z80,OOO
uses Zilog's Z-BUSTM, so the entire
Z8000 family of circuits are
available for use with it. Multifunction Z-BUS peripherals are ex. tensively programmable, so each
can be precisely tailored to an application. Counting, timing, and.
parallel I/O are tasks handled by
the Z8036 Z-CIO CounterlTimer
and Parallel I/O Unit, which has
three 16-bit counter/timers and
three I/O ports.
Data communications are the
domain of the Z8030 Z-SCC Serial
~ommunications Controller and the
Z8031 Z-ASCC Asynchronous
Serial Communications Controller,
both dual-channel multiprotocol
components that between them
support all popular communication
formats.
663
Direct melTlory access components are supplied by the Z8016
Z-DTC DMA Transfer Controller, a
fast, dual-channel device that supports I/O-to-memory data tran$fers
without CPU intervention. In addition, the Z-BUS versions of the
Z800 can be used as I/O processors, with their on-chip DMA
channels programmed to transfer
data in a Z80,OOO-based system.
General-purpose control and
data-manipulation problems are
solved by the Z8090 Z-UPC Universal Peripheral Controller, a complete microcomputer-on-a-chip that
uses the Z8 instruction set and
features three I/O ports and two
8-bit counter/timers. The Z8038
Z-FIO FIFO Input/Output Interface
Unit can be interconnected with
asynchronous subsystems of a
multiprocessor system to interface
any major microproc'essor to the
Z-BUS. Its buffer depth can be expanded using the Z8060 Z-FIFO
Buffer Unit. Other support
peripheral circuits that can be
used with the Z80,OOO are the
Z8065 Z-BEP Burst Error Processor
and the Z8068 Z-DCP Data Ciphering Processor.
664'
The Z8581 CGC,Clock Generator
Controller can be used to generate
the clock timing required by the
Z80,OOO. This device uses the
same technology as the Z80,OOO
and provides a power-on reset
signal and auxilary clocking
signals.
Finally, the Z8070 APU
Arithmetic Processing Unit provides the' floating-point processing
power for the Z80,OOO CPU.
Z8070 Arithmetic Processing
Unit. The Z8070 Arithmetic Processing Unit (APU) provides highperformance binary floating-point
capability for the Z800, Z8000, and
Z80,OOO CPUs. These processors
have built-in Extended Processor
Architecture, which enables the
CPU and APU to function together
to execute floating-point instructions. In each case, the CPU
fetches the instruction and controls
the data movement in the bus,
while the APU interprets the
instruction and performs the indicated operation. Thus, the programmer generates one stream of
instructions and is unconcerned
with the mechanism for sharing the
task .of executing the floating-point
instructions ,in that stream.
The Z8070 can also be used as
an I/O device for other popular
microprocessors. In this mode, the
device is accessed using I/O instructions to write the instruction
command to the Z8070 and to
move data to and from the APU.
This mode of operation is also
useful when the Z8070 is used in a
bit-sliced CPU implementation to
provide floating-point capability.
The Z8070 follows the proposed
IEEE P754 standard in respect to
data formats, arithmetic operations, and trap handling. In addition
to single, double, and double, extended floating-point formats, the
Z8070 handles 32- and 64-bit integers and byte strings of BCD
digits. Add, subtract, multiply, and
divide operations are supplemented with square root, remainder, and a rich array of ,comparison instructions. Finally, eight
trapping conditions are monitored
and trigger the device to either
generate an interrupt request to
the CPU or handle the trap with
the pre-programmed, default trap
handler on the chip.
~®@~® ~IIA~UJ
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September 1983
FEATURES
[J
o
Cl
Fast and complete implementation of proposed IEEE
Standard P754 Draft 10.0 for Binary Floating-Point
Arithmetic. Performs a single-precision multiplication in under three microseconds (with a 10 MHz
clock).
[J
Interfaces as coprocessor to Z800™, Z8000™, and
Z80,000TM CPUs.
D
Speed versions offered from 10 MHz to 25 MHz.
o
Data types supported are: Single, Double, and Double Extended floating-point; 16- and 32-bit integer;
BCD strings.
Provides for conversion of binary integer and Binary
Coded Decimal formats to and from floating-point
format.
.
IJ
Operations supported include add, subtract, mUltiply, divide, square root, remainder, and compare.
Can be interfaced through Zilog's Extended Processing Architecture or a general-purpose interface.
D
Frees CPU for performance of other tasks.
GENERAL DESCRIPTION
The Z8070 Arithmetic Processing Unit (APU) is an Extended Processing Unit (EPU) designed to perform
floating-point arithmetic functions while operating in
parallel with a CPU. By monitoring the same instruction
stream as the CPU, it is able to identify and execute
those instructions intended for it, thereby freeing the
CPU to perform other activities (Figure 1).
The APU supports several data formats, enabling it to
handle a wide range of business and scientific applications. These include three binary floating-point formats
and four integer formats, including one for variable
length Binary Coded Decimal (BCD) strings. All of the
APU's internal numeric manipulations use an 80-bit
floating-point format; however, transfers of data between the APU's data registers and CPU registers or
memory can use any of the formats desired, as specified
in the floating-point instruction.
The APU can use Zilog's Extended Processing Architecture (EPA) for the Z800, Z8000, and Z80000, or it can be
integrated into systems based on other popular
microprocessors, using a general-purpose interface.
APU
EXECUTION OF
FLOATING·POINT
INSTRUCTIONS
CPU
EXECUTION OF
CPU INSTRUCTIONS;
BUS CONTROL
Ii
K
~
IT
SYSTEM BUS
MEMORY
~
)
V
CPU AND APU
INSTRUCTIONS
AND DATA
Figure 1_ The APU Environment
2235-001
665
Floating-point arithmetic operations are perfmmed according to the requirements of the proposed IEEE Standard for floating-point arithmetic. The l807a. supports:
L!I
Single (32-bit), Double (64-bit), and Extended (80-bit)
Precision floating-point number formats.
II
Additior), subtraction,
multiplication, division,
square-root, remainder, and compare operations.
PI
Conversions between binary integers and floatingpoint numbers.
II
Conversions between decimal integers and floatingpoint numbers.
•
Non-numbers (NaNs) and infinity arithmetic.
II
Floating-point exceptions and their handling.
m Conversions between different floating-paint formats.
ARCHITECTURE
Overview
The l8070's contribution to a system is best understood
by examining its structure. Internally, the l8070 is
organized as two processors: an Interface Processor
and a Data Processor. The two processors have
separate clocks, freeing the Data Processor from interface speed constraints. Figure 2 is a block diagram of
the l8070 APU.
The Interface Processor fetches and aligns instructions
and data, maintains the internal instruction queue, and
executes certain control and data movement instructions independently of the Data Processor. By monitoring CPU status and control signals; the Interface Processor knows when an instruction fetch is to occur and
will watch for an Extended Instruction template. It will
read and align the instruction and data when the Extended Instruction template has the correct ID number. The
user may access the status and control registers of the
Interface Processor.
The Data Processor, which operates independently of
the Interface Processor, contains eight 80-bit data
registers accessible to the user. It also contains the
multiplier array, ALU, accumulator, shifter, and temporary registers required for floating-point processing.
The only parts of the Data Processor visible to the user
are the eight 80-bit data registers, specified in floatingpaint instructions as source and/or destination registers,
and the two operand registers.
Register Organization
There are eight 80-bit data registers, two 80-bit operand
registers, three 32-bit status registers, and one 32-bit
and one 16-bit control register in the l8070. All are accessible to users with the exception of the System Configuration register, which is reserved for privileged
users. Figure 3. illustrates the l8070 register set.
STATUS AND CONTROL REGISTERS
CPU ADDRESSIDATA LINES
USER
INTERFACE PROCESSOR
ID~~~TD~nCr'i~~ TRnEA~~~I~~~n
~·~~!~~U~~~~~?~'-..e~~
... ll;nn
t
,..,
nI;UlI.;Jll:.n~
1
INTERFACE CONTROL
I
I
J
SYSTEM
PC1
PC2
FLAGS
FOP1
FOP2
J
J
DATA PROCESSOR
l
DATA AND OPERAND
REGISTERS
DATA REGISTER FILE
J
J
I
MULTIPLIER
+
I
ALU
t
J
ACCUMULATOR
J
SHIFTER
I
I
Figure 2. Z8070 Block Diagram
I
I
I
I
Figure 3. Z8070 Registers
2235-002, 003, 004
Data Registers. The Z8070 has a data register file of
eight 80-bit registers labeled FRO to FR7 (Figure 4).
Program Counter Registers. PC1 holds the address of
the instruction being executed in the Data Processor or
the address of any control instruction being executed.
PC2 holds the address of any queued instruction (Figure
5).
Status Registers. There are three 32-bit status
registers: the Program Counter registers (PC1 and PC2)
and the Flag register.
79
78
64
Flags Register. The Flags register (Figure 6) contains
historical information on Z8070 operations as described
below.
63
FR7
FR6
31
FRS
FR4
PC1
31
FR3
FR2
PC2
FR1
FRO
SIGN
EXPONENT
SIGNIFICAND
Figure 5. Program Counter Registers
Figure 4. Z8070 Data Register File
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
UN FOV INV
7
6
5
4
3
2
IX NAN DE INX DZ
1
UN FOV INV
~~-------~_------~/~_------~~-------~;
COMPARE AND REMAINDER FLAGS
PREVIOUS O.PERATION FLAGS
STICKY FLAGS
Figure 6. Flags Register
Sticky Flags (0·7). Eight flags are set when the corresponding aritti"metic exception occurs, and remain set
until they are cleared by the programmer. These flags
are:
Previous Operation Flags (8·15). The same as the
sticky flags described above, but they reflect the exceptions of the previous arithmetic operation.
NIS1, N1S2 (16·17). Set to indicate Normal mode, and
INV (Invalid Operation)-Indicates an invalid operation
or result has occurred (e.g., ...[3).
cleared to indicate System mode for PC1 and PC2,
respectively.
FOV (Overflow)-Indicates that the absolute value of a
floating-point number is too large to be accommodated
by the destination format.
Compare and" Remainder Flags (18·23). Set with comparisons as shown in Table 1.
UN (Underflow)-Occurs when the absolute value of a
number is too small for the destination format, and further denormalization would cause a loss of accuracy.
DZ (Divide by Zero)-Indicates the division of a non-zero
finite number by zero.
INX (Inexact Result)-Indicates when the result is inexact due to rounding or an untrapped overflow.
DE (Denormalized number)-Indicates that an operation
was performed on a denormalized number.
NAN (Signaling NaN)-Occurs when a Signaling NaN is
encountered. (NaN stands for "Not-a-Number", and
may be used to force a trap or hold other information.)
IX (Integer Exception)-Occurs when the floating-point
number is too large in magnitude to convert to an integer
or BCD string, or when an attempt is made to convert a
NaN to an integer.
2235-005, 004, 006
Table 1. Comparison Results
> Unordered
<
Fe
FZ
FS
FV
FD
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
FOP2E (24·25). Contains the two most significant bits of
the exponent of operand register FOP2 for use in an
overflow exception.
FOP1 E (26·27). Contains the two most significant bits of
the exponent of operand register FOP1 for I-lse in an
overflow exception.
R (28). Rounding bit; 1 if most recent result was rounded
up.
667
Invalid Op (29·31). Contains a code describing the
reason for an invalid operation result as follows:
000
·001
010
011
100
101 Square root of a negative number
110 Non-decimal digit on BCD convert
Magnitude subtraction of infinities
Zero multiplied by infinity
Zero divided by zero, or infinity divided by infinity
All invalid remainders
.
Unordered compare
20
19
18
17
System Configuration Register. The System Configuration register is a 32-bit control register (Figure 7).
In systems that distinguish between System and User
modes of operation, it is restricted to privileged users.
16
15
1.4
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Figure 7. System Configuration Register
DLC (12). Set to disable' interrupts from lower priority
devices on the interrupt daisy chain.
IUS (13). Set when 'the interrupt is under service.
IP (14). Set to indicate a pending interrupt.
MIE (15).. Set to enable interrupts.
INTACK (16·17). Set to indicate which type of interrupt
acknowledge to respond to as follows:
Ox = Nonmaskable
10 = Nonvectored
11 = Vectored
OVRLP (18·19). Indicates the Overlap mode as follows:
Ox = No Overlap
10 = Intermediate Overlap
11 = Maximum Overlap
AC (20). Set to synchronize processors if ClK.1 (interface' clock) and ClK.D (data processor clock) are running at different speeds.
F (21). Set if an interrupt service routine will be unable to
successfully return to the interrupted program. This happens when two or more floating-point instructions have
been fetched after the EPU instruction qausing the inter~
rupt, but before the interrupt acknowledge.
RPC (22). Set if an interrupt service routine will need to
alter its return address to successfully continue the interrupted program.
U (23). Set when the Z8070 is used.
IR (24·25). Set to indicate the reason for an interrupt as
follows: '
668
in binary form and are set on power-up with the ID pins.
Instructions are executed only if the ID in the opcode
matches these bits.
EPUID (28·31). This field contains four bits, one for each
possible EPU ID. An instruction specifying an ID whose
corresponding bit is a 1 will cause an Invalid EPU ID interrupt.
User Control Register. The User Control register
(Figure 8) is a 16-bit register, accessible to all users. The
user controls rounding modes and enables and disables
traps with this register.
15
I
14
'NV! 0 : 0 : 0
______
~
NV (11). Set when there is no interrupt vector (leaves
'lines 3-stated).
ID (26·27). These bits hold the I D of the Z8070 expressed
~
VIS (10). Set when the interrupt vector is to include
status information.
00 = Arithmetic
01 = Invalid opcode
10 ;:: Invalid EPU ID
11 = Privileged mode violation
'
SV (9). Set to shift the interrupt vector left one bit, and
set the lSB to zero.
I
t
~
Interrupt· Vector (0.7). This field identifies the source
and cause of an interrupt.
4
3
2
: 0 : 0 : o!
_ _ _ _ _ _ _J#
1
0
~M
I
TRAP ENABLES
Figure 8. User Control Register
RM (0·1). Sets the rounding modes as follows:
00 = Round to Nearest
01 = Round toward Zero
10 = Round toward Positive Infinity
11 ~ Round toward Negative Infinity
Trap Enables (8·15). The setting of these bits enables
the trap associated with each exception listed below.
INV (Invalid)
FOV (Overflow)
UN (Underflow)
DZ (Divide-by-Zero)
INX (Inexact result)
DE (Denormalized number)
NAN (Signaling NaN)
IX (Integer Exception)
2235-006
Floating Operand Registers. The ZS070 contains two
SO-bit Floating Operand registers (Figure 9), labeled
79 78
FOP1 and FOP2, which contain the input operand (FOP1)
and the default result (FOP2) for use by trap handlers.
64 63
I
EXPONENT
L
SIGNIFICAND
15 LEAST SIGNIFICANT BITS OF
EXPONENT (2 MSBs IN FLAGS REGISTER)
t=OP1 (INPUT OPERAND)
79 78
64
I I
S
6~
SIGNIFICAND
EXPONENT
L
15 LEAST SIGINFICANT BITS OF
EXPONENT (2 MSBs IN FLAGS REGISTER)
.
i
)
FOP2 (RESUL T1
Figure 9. Floating Operand Registers
PROGRAMMING
Floating-point instructions are contained in the same
program as standard CPU instructions. To the programmer, instruction execution appears linear, as if a single
processor is executing all the instructions. In many
cases however, CPU and Z8070 processing can occur in
parallel, greatly increasing system throughput.
Parallel processing depends upon the type of APU instruction being executed and the Overlap mode in effect.
APU
T1
•
•
•
•
•
•
•
•
•
•
•
•
Tn
OPCODE
FETCH
OPERAND
FETCH
- ---
cpu
--------OPCODE
FETCH
EXECUTION
. OPERAND
FETCH
EXECUTION
OPCODE
FETCH
OPERAND
FETCH
EXECUTION
- - - --
APU
•
•
•
•
•
•
•
•
----. - - - - OPCODE
FETCH
t----01- -
OPCODE
FETCH
OPERAND
FETCH
EXfCUTION
APU/CPU PROCESSING IN AN OVERLAP MODE
1-------1 -
CPU
-
-
- 1-------1
-
-
-
- 1-------1
OPCODE
FETCH
•
•• CPU STOPPED
•
•
EXECUTION
OPERAND
FETCH
EXECUTION
•
----"1- - - --
•
t-----I- -
OPCODE
FETCH
EXECUTION
Tn
-
-OPCODE
FETCH
APU/CPU PROCESSING IN NO OVERLAP MODE
Figure 10. Instruction Processing
2235-007,008
-----
OPERAND
FETCH
•
•
•
•
----
-----
If the APU receives an instruction involving a data
transfer out of the APU, it halts the CPU (asserts BSY)
regardless of the Overlap mode in effect. When NoOverlap mode is in effect, the APU asserts BSY
whenever any floating-point instruction is received.
Figure 10 illustrates instruction processing with and
without overlap.
In general, the interaction of CPU and APU is
transparent to the user. It is possible, however, to arrange programs to· take advantage of the parallel processing capabilities inherent in the system.
An interleaving of CPU and l8070 instructions enhances
the ability of a system to process in parallel. Without interleaving, floating-point instructions .might be received
faster than they can be processed, forcing the l8070 to
halt further CPU processing until the current extended
instruction is completed. Also, some instructions take a
relatively long time to process (e.g., FSQR, FDIV); interleaving allows the CPU to process instructions while
these extended instructions are being processed by the
APU.
Parallel processing is facilitated by interleaving instructions as in
FADD
INC
FLD
F1 @92
R24
@R4 F1.
!APU instruction!
!CPU instruction!
!APU instruction!
The significand portion contains the fraction and the integer bit (in Single and Double Precision binary, the integer bit is implicit). The significandthen, is the integer
bit followed by the binary point and the fraction. The exponent locates the actual binary point, and the sign bit
specifies a positive or negative number.
In the following description of the binary floating-point
formats, "s" is the sign, "e" is the exponent, "f" is the
fractional part of the significand, and "j" is the integer
part (possibly implicit) of the significand.
The value (v) of the 32-bit Single Precision Binary format
is determined as follows:
= 255 and f =1= 0, then v = NaN.
= 255 and f = 0, then v = (- 1)S(infinity).
•
If e
II
If e
•
If 0 < e < 255, thEm v = (-1)S2 e-127(1.f).
•
If e = 0 and f
•
If e
=1=
0, then v = (-1)s2e-126(0.f).
= 0 and f = 0, then v = (- 1)SO,(zero).
since the incremen't of R2 can occur while the floating
point add is finishing.
The value of the 64-bit Double Precision binary format is
determined as follows:
Programming constructions like the following
.If e
FADD
FLD
F1 @R2
@R4 F1
cause the l8070 to halt the CPU to ensure that valid
results are read from F1 during the subsequent store
operation.
•
If e
= 2047 and f =1= 0, then v = NaN.
= 2047 and f = 0, then v = (-1)S(infinity).
•
If 0
<
m If e
•
If e
e
<
2047 then v = (- 1)S2e-1023(1.f).
= 0 and f =1= 0, then v = (-1)s2e-1022(0.f).
= 0 and f = 0, then v = (- 1)SO,(zero).
Data Types and Formats
For the 80-bit Double Extended Precision Binary format,
the value is determined as follows:
This section describes the different data types and formats that the APU is able to manipulate. These data
types include binary· floating-point and binary and
decimal integers, and can be represented in 32-, 64-, and
80:bit formats.
•
If e
II
If e
11
If 0 < e < 32,767 then v = (-1)s2(e-16,383) U.f).
•
If e
0 andj
zero).
Binary Floating·Point. All binary floating-point numbers
assume the followin·g format:
Is I e
where the ·S .bit is the Sign bit and specifies a positive
(cleared to 0) or negative (set to 1) number. The negative
or positive floating-point number is equal to:
Significand x 2(exponent-bias)
670
•
= 32,767 and f =1= 0, then v = NaN.
= 32,767 and f = 0, then v = (-1)S(infinity).
=
= f = 0, then v = (-1)sO, (normal
'
If e = 0 and j or f is nonzero, then v =
( - 1)s2 e-16,383U.f).
The exponent is always biased to ensure a positive value
for the purpose of comparisons. Numbers of the same
format may then be compared bit by bit from left to right,
the first difference determining the ordering. The biases
for the floating-point formats are shown in Table 2.
2235.p09
Integers. Integer formats are automatically converted to
the aO-bit binary floating-point format when they are
loaded into the APU (instructions FLDIL, FLDIQ, and
FLO BCD).
Tabla 2. Exponent Biases
Format
Exponont Bins
Single
127
Double
1023
Extended
16,383
An exponent of all ones indicates an infinity if the fraction equals zero, or a NaN if the significand is not'zero. A
Signaling NaN is indicated by the most significant bit
(MSB) of the fraction field being zero, and a Quiet (nontrapping) NaN is indicated by the MSB of the fraction being one (in Extended format, Quiet vs. Signaling is determined by bit 62). Single, Double, and Extended formats
are shown in Figure 11.
31 30
Decima/Integers. The Decimal Integer format is one to
ten bytes,' which includes up to 19 Binary Coded Decimal
(BCD) digits and a Sign bit. The Decimal Integer format is
illustrated in Figure 12.
Binary Integers. The Long Word and Quad Word Integer
formats are shown in Figure 13. These are the only formats which express negative numbers in two's complement form.
23 22
SINGLE PRECISION BINARY (32 BITS)
63 62
52 51
DOUBLE PRECISION BINARY (64 BITS)
79 78
64 63 62
e
EXTENDED PRECISION BINARY (80 BITS)
Figure 11. Binary Floatlng·Polnt
79
/S
Format~
75
I I Ix I
X
X
UP TO 19 BCD' DIGITS
BINARY CODED DECIMAL INTEGER
s = sign bit
e
exponent lIeld
f = fraction lIeld
J Integer bit.
=
=
Figure 12. Binary Coded Decimal (BCD) Integer Format
31
o
63
BINARY INTEGER (32 AND 64 BIT TWO'S COMPLEMENT INTEGERS)
Figure 13. Long·Word and Quad·Word Integer Formats
2235-009, 2146-001
671
Addressing Modes
Assembler Syntax
Operands are specified in a floating-point instruction
with the addressing modes for each CPU option as
shown in Table 3.
Floating-point instructions are of the form:
Table 3. Addressing Modes
Addressing Mode
Z8070 Register
CPU Register
Indirect Register
Direct Address
Index
Immediate
Relative
Stack Pointer
Relative
Base Index
=
Universal
zaoo
F
CPU
M
M
M
M
M
F
R
IR
DA
X
M
M
S
BX
zaooo zao,ooo
F
R
IR
DA
X
1M
F
R
IR
DA
X
RA
FXXX[S,D] rnd dst,src
The opcode suffix [Single (S), Double (D), or Extended
(no suffix)], refers to the size of the source operand.
"rnd" refers to the precision to which the result of the
operation is rounded. SGL is single precision, DBL is
double precision, and no suffix is extended precision.
Instruction Set
, The floating-point instruction set provides the following
types of instructions:
.
•
Primary arithmetic operations
II
Load and store operations
iii
Compare operations
Ii]
Secondary arithmetic operations
E1
Control operations
F APU register
CPU
CPU register
M
memory
=
=
Primary Arithmetic Operations
Mnemonic
Operands
Addressing Modes
Operation
FADD
FADDS
FADDD
dst, src
src: F,CPU,M
Floating Add
dst: F
dst -
FDIV
FDIVS
FDIVD
dst,src
src: F,CPU,M
Floating Divide
dst: F
dst -
FMUL
FMULS
FMULD
dst, src
src: F,CPU,M
Floating Multiply
dst: F
dst -
FREMSTEP
dst, src
src: F,CPU,M
dst: F
Floating Remainder Step
FREMSTEPF
dst, src
src: F
dst: F
dst -
dst
+
src
dst/src
dst*src
dst REM src
Floating Remainder Step and
Transfer Flags to CPU
dst - dst REM src
CPU - Flags
672
FSQR
FSQRS
FS9RD
dst,src
FSUB
FSUBS
FSUBD
dst, src
src: F,CPU,M
Floating Square .Root
dst: F
dst -
src: F,CPU,M
Floating Subtract
dst: F
dst -
SQR (src)
dst - src
Load and Store Operations
Mnemonic
Oporands
Addressing Modes
Operation
FLO
FLDS
FLDD
dst, src
src: F,CPU,M
dst: F
or
src: F
dst: CPU,M
Floating Load
FLO BCD
dst, src
FLDIL
dst, src
dst: F
src: CPU,M
or
dst: CPU,M
src: F
dst: F
src: CPU,M
or
dst: CPU,M
src: F
FLDIL
dst, src
dst: F
src: CPU,M
·or
dst: CPU,M
src: F
FLDIQ
dst,src
dst: F
src: CPU,M
or
dst: CPU,M
sdc: F
(note: CPU = 64-bit
register)
FLDM
FLDTL
FLOTO
dst, src, n'
(n = 1,2)
dst, src
dst, src
dst: F
src: CPU,M
or
dst: CPU,M
src: F
(note: F,CPU,M = 80or 160-bit location)
dst: CPU,M
src: F
(note: dst is 32 bits)
dst: CPU,M
src: F
(note: dst is 64 bits)
dst - src
Floating Load BCD Integer
dst dst -
Float (BCD-src)
BCD (float-src)
Floating Load Binary Integer
Long Word
dst dst -
~
I
Float (src)
Fix (src)
~
tg
e=
Floating Load Binary Integer
Long Word
dst dst -
Float (src)
Fix (src)
Floating Load Binary Integer
Quad Word
dst dst -
Float (src)
Fix (src)
Floating Load Multiplo
dst - src
Floating Load and Truncate to
Integer Long Word
dst -
Int (src)·
Floating Load and Truncate to
Integer Quad Word
dst -
Int (src)
673
Compare Operations
Mnemonic
Operands
Addressing Modes
Operation
FCP
FCPS
FCPD
dst, src
dst: F
Floating Compare
src:F,CPU,M
dst - src, set APU flags
FCPF
dst, src
dst: F
src: F
Floating Compare and Transfer
Flags to CPU
dst - src
CPU - flags
FCPFX
dst, src
dst: F
src: F
Floating Compare, Transfer Flags to
CPU, and Raiso Exception if
Unordered
dst - src
CPU - flags
FCPX
FCPXS
FCPXD
dst, src
dst: F
Floating Compare and Raise
Exception if, Unordered
src: F,CPU,M
dst - src, set APU flags
FCPZ
FCPZS
FCPZD
dst, src
FCPZF
dst
dst: F,CPU,M
Floating Compare with Zero
dst - 0, set APU flags
dst: F
Floating Compare with 0, and
Transfer Flags to CPU
dst - 0
CPU - flags
FCPZFX
dst
dst: F
Floating Compare with 0, Transfer
Flags to CPU, and Raise Exception
if Unordered
dst - 0
CPU - flags
FCPZX
FCPZXS
FCPZXD
674
dst
dst: F,CPU,M
Floating Compare with Zero and
Raise Exception if Unordered
dst ,- 0
set APU flags
Secondary Ari~hr(.eiic Opera~ions
iv1nemonic
Operands
Addressing Modes
Operation
FABS
FABSS
FABSD
dst, src
dst: F
Floating Absolute Value
src: F,CPU,M
dst -
FCLR
dst
dst: F
Floating Clear
dst -
FINT
FINTS
FINTD
dst, src
FNEG
FNEGS
FNEGD
dst, src
Conirol
I src I
+0
dst: F
Floating Round to Floatin_g Integer
src: F,CPU,M
dst -
dst: F
Floating Negation
src: F,CPU,M
dst -
Float [Int (src)]
00
~
(-src)
Opera~ions
00
•
~
ra
Mnomonic
Operands
Addressing Modes
Operation
FLDCTL
dst, src
dst: FCTL
src: CPU,M
Floating Load Control
or
dst -
d
src
dst: CPU,M
src: FCTL
FLDCTLB
dst
dst: Fsel
Floating Load Control Byte
CPU -
FRESFLG
FRESTRAP
FSETFLG
FSETMODE
FSETTRAP
src
src
src
src
src
dst: FFLAGS
src: flaglist
dst: USER
src: traplist
dst: FFLAGS
src: flaglist
dst: FMODE
src: modelist
dst: USER
src: traplist
flags
Floating Reset Flag
FFLAGS (flaglist) -
0
Floating Reset Trap
USER (traplist) -
0
Floating Sot Flag
FFLAGS (flaglist) -
1
Floating Set Mode
FMODE -
modelist
Floating Sot Trap
USER (traplist) -
1
675
SIGNAL DESCRIPTIONS
The following section describes each pin function of the
Z8070 APU. Depending on which CPU option is chosen
(pins OPTo and OPT1), some of these functions do not apply. Figure 14 shows a Z8070 pin-out with pin
assignments, and Figure 15 gives the functional pin-out
for each of the four possible interface options.
ABORT. Abort (input, active Low). ABORT is asserted to
cause an instruction abort.
ADo-AD31. Address/Data (inputs/outputs, active High,
3-state). Multiplexed address .and data lines.
AS. Address Strobe (input, active Low). The rising edge
of AS indicates the beginning of a transaction and show's
that the address, status, and control signals are valid.
BLIW and BWiL. Byte, Word, and Long Word (inputs).
These signals specify the data transfer size as follows:
BUW
Bwi[
1
1
1
o
a
1
Size In bits
8
16
32
BRST. (Burst, input, active Low). BRST active indicates
that the CPU may generate burst transfers.
-BRSTA. Burst Acknowledge (input,
active Low). A Low
on BRSTA indicates that the memory can support burst
transfers.
BSY. Busy (output, active Low). The BSY signal is used
by the Z8070 to halt the CPU during stores, and also to
implement overlap functions. It is associated with the
following CPU signals:
100-101' 10 Select· (inputs, active High). These signals
establish the EPU ID during reset.
lEI. Interrupt Enable In (input, active High). lEI is used
with lEO to form an interrupt daisy chain when there is
more than one interrupt-driven device sharing a common
interrupt request line to the CPU. A High lEI indicates
that no other higher priority device has an interrupt
under service.
lEO. Interrupt Enable Out (output, active High). lEO is
High only if lEI is High and the CPU is not servicing a
Z8070 interrupt and the Z8070 is not requesting an interrupt (Interrupt Acknowledge cycle only). lEO is connected to the next lower priority device's lEI input and
thus inhibits interrupts from lower priority devices. lEO is
tied high for the last device on the chain.
INT. Interrupt Request (output, open-drain, active Low).
This signal is activated when the Z8070 requests an interrupt.
NtS'. Normal/System mode (input). High for Normal
mode, Low for System mode.
OPTo-OPT1. CPU Option (input, active High). These
signals establish the CPU option during reset as follows:
OPTo
OPT1
a
1
a
1.
1
a
CPU Interface
Universal
Z80,000
Z800
Z8000
a
1
RESET. Reset (input, active Low). When asserted,
RESET forces a hardware reset to power-on condition.
CPU
Z800
Z8000
Z80,000
Signal
PAUSE
STOP
EPUBSY
BUSACK. Bus Acknowledge (input, active Low). When
BUSACK goes Low, the EPU 3-states the AD lines until it
goes High again and an EPU-to-memory or CPU transfer
is required.
RSPo-RSP1. Response (input, active High). These lines
encode the response monitored by the APU to transactions initiated by the Z80,000 CPU as follows:
RSPo
RSP 1
1
a
a
a
1
1.
a
1
Bus Error
Bus Retry
Wait
Ready
ClK.D. Data Processor Clock (input). CLK.D is provided
by the system and runs the data processor portion of the
Z8070.
RIW. Read/Write (input, Low = Write). Indicates whether
the CPU is performing a read or write operation.
ClK.I. Interface Processor Clock (input). Interface Pro-
SIP. Sequence in Progress (output, active Low). This
cessor clock of the Z8070.
signal is asserted by the APU and held Low until the instruction and any associated data transfer is completed.
CS. Chip Select (input, active Low). CS signals the beginning of a Z8070 transaction and is valid only for the
length of a single transaction or machine cycle.
SNo-SNs. Segment Number (input, active High). These
DBo-DBn. Data Bus (input/outputs, active High, 3-state).
These are the data lines for the Universal interface,
where n=7, 15 or 31.
STo-ST3. Status (input, active High). These lines specify
OS. Data Strobe (input, active Low). DS provides timing
for data transfers on the bus.
676
lines contain the segment number portion of a memory
address.
the type of bus transaction as described in the appropriate CPU Technical Manual.
BUSACK
AD27 (SN21
BRSTA
AD28 (SNal
+5V
SIP/BRST/ABORT
Riw
A029 (SN4l
GNO
AOao (SNsl
Cs/As
AD31 (SNsl
Nis
101
Z8070 APU
RESERVED
10 0
INT
lEI
GND
lEO
RESET
OPT1
OPTO
Figure 14. Pin Assignments
EXTERNAL INTERFACE
The four different interfaces for the Z8070 are the Z800,
Z8000, Z80000, and Universal interface. The Z800,
Z8000, and Z80000 are Z-BUS® type interfaces with the
CPU and APU fully interlocked in hardware. No software
polling or wait instructions are required to prevent overrunning of the Z8070's instruction queue with the Z-BUS
interfaces. Depending on the type of system, the Universal interface may require additional logic to implement
the interface. In general, APU-memory transactions are
performed with the same bus cycles as CPU-memory
transactions. The following sections describe interface
specific features of the Z8070.
Interface Types
Z·BUS Interface. An important feature of the Z-BUS
CPUs (Z800, Z8000, and Z80000) is their Extended Processing Architecture (EPA). This facility provides a
mechanism by which the basic instruction set can be extended via external EPUs such as the Z8070 APU.
The execution of floating-point instructions is controlled
by an extended processor enable bit in the CPU. When
this bit is zero, it indicates that there is no EPU con-
2235·010
nected to the CPU, causing the CPU to trap to a software
trap handler whenever an extended instruction is encountered. This allows the operation of the extended instruction to be performed by software, and provides the
ideal tool for emulating an EPU during development of
systems intended to later contain an EPU.
If the extended instruction indicates a transfer of data
between the Z8070's internal registers and the main
memory, the CPU will calculate the memory address and
generate the appropriate timing signals (AS, OS, MREQ,
etc.), but the data transfer itself is between the Z8070
and memory (over the AD lines). If a transfer of data between the CPU and APU is indicated, the sender places
the data on the AD bus while DS is active.
If the extended instruction indicates an internal operation to be performed by the Z8070, the Z8070 begins execution of the task and the CPU is free to continue on to
the next instruction. Processing then proceeds
simultaneously in both the CPU and the Z8070 until a second extended instruction is encountered that is destined for the Z8070.
677
fJ
RESET _
BUS ACKNOWLEDGE _
.........
------
ADDRESSI
DATA BUS
iiESET
iiliSA'CK
RNi
~
10,
~
100
0
AD,s
OPT,
AD,.
OPTO" 1
AD!3
aSy
AD,z
ClK.!
ClK.D
Z8070
APU
ADg
I
I
A D7
iNT
ADa
lEI
ADs
lEO
AD4
ST3
AD3
STz
ADz
ST,
AD,
STo
ADo
Nis
CLOCKS
BUS TIMING
OS
aNi
CPU OPTION
CPU PAUSE
AS
ADa
liD SELECT
I
a
AD"
AD,O
READ/WRITE
DATA SIZE
--
jlNTERRUPT
CONTROL
I
} STATUS
~
POWER
AND
GROUND
Figure 15a. Z80701Z800 Interface
ID SELECT
CPU OPTION
CLOCKS
I
I
I
--
SNs
SNs
OPT, .. 1
SN4
OPTo" 1
SN3
ClK.1
SNz
ClK.D
---
ADDRESSI
DATA BUS
r--
10,
100
-.......
--
AD,s
I
SN,
-I
SNo
AD,.
~A.!.O~
AD!3
ST3
AD,z
AD"
AD,o
_
SEGMENT
NUMBER
...!N.!T.!!U~T!.O!! ~~R!...!
ST,
}
STo
STATU'
Nt'S
ADa
RiW
AD7
TNT
ADs
lEI
ADs
lEO
AD.
OS
AD3
AS
AD,
-
ONLY
STz
Z80.70
APU
ADg
~ ADz
-----------,
_ )
Z"''''I
I
BUS
TIMINO
REsET
RESET
aUSACK
-
BUS ACKNOWLEDGE
BYTE/WORD
atVi
Vss BSY
~
POWER
AND
GROUND
j'NTERRUPT
CONTROL
_
ADo
Vee Vss Vee
-
CPU
STOP
Figure 15b. Z8070/Z80001nt'erface
678
2235-011,012
-
-
AD31/SNS
AD301SNs
AD29/SN4
AS
AD2s1SN3
OS
AD27/SN2
INT
AD2s1SNl
lEI
AD2s1SNo
lEO
AD24
BSY
AD23
BUSACK
AD22
OPTl = 1
AD21
OPTa = 0
AD20
10 1
100
AD19
ZB070
AD18
ADDRESS/
DATA BUS
---
APU
AD17
RESET
BLiVl
BW/L
AD16
AD15
) BUS
TIMING
} INTERRUPT
CONTROL
EPU BUSY
BUS ACKNOWLEDGE
) CPU OPTION
) 10 SELECT
RESET
) DATA SIZE
RSPl
AD14
RSPo
AD1J
BRSTA
AD12
BRST
ADll
ST3
AD10
ST2
AD9
STl
AD8
STo
AD7
N/S
ADs
Vee
ADs
Vss
A04
Vee
AD3
Vss
AD2
ClK.1
AOl
ClK.D
lSI
~
~
IV
CI
ADo
Figure 15c. Z80,OOOlZ8070 Functional Interface
DB23
-DATA BUS
(0-23)
---
---
--
DB31
DB22
DB30
OB21
DB29
DB20
DB28
DB19
DB27
DBn
DB26
DB17
DB25
DB16
DB24
DB15
!NT
DB14
DB13
lEI
ZB070
APU
DBn
DB10
OPTl = 0 ---'-
OB9
OPTo = 0
os _
DB8
DB7
SiP
DB6
cs
N/S _
DBs
DB4
)
INTERRUPT
} CONTROL
lEO
BUW
BwiL
DBll
DATA BUS
(24-31)
) DATA SIZE
I
CPU OPTION
DATA STROBE
SEQUENCE IN PROGRESS
NORMAL/SYSTEM MODE
D~3
R/W
RESET _
READ/WRITE
RESET
DB2
ABORT
INSTRUCTION ABORT
DBl
ClK.I
ClK.D
DBa
) CLOCKS
Vee
tt
'-----v-----' BUSY
POWER
AND
GROUND
Figure 15d. Z8070 Universal Interface
2235-013,014
679
The Extended Processing Architecture also offers a provision to preclude extended instruction overlapping. The
APU connects to the CPU via the BSY line so that if the
APU is requested to perform a second extended instruction before it has completed the previous one, it can halt
the CPU until execution of the previous instruction is
complete. BSY is also asserted when a store opcode is
received by the APU, ,and it is held active until the requested data is ready for the CPU to transfer.
With the Z800 interface, the CPU indicates an instruction
fetch to the APU whenever it places a floating-point iRstruction on the bus. The Z8070 then translates the instruction and performs the operation, asserting BSY if
the opcode indicates a store.
For the Z8000 interface, if the EPA bit is set it indicates
that an EPU is connected to the CPU. The CPU begins
operation by fetching an instruction and determining
whether it is a CPU or an EPU command. The EPU
monitors the Z-BUS at the same time, looking for an extended instruction template. The CPU performs any address calculations required by the extended instruction
and, if the instruction specifies the transfer of data, the
CPU generates the timing signals for the transfer.
The Z8070 monitors the activity on the Address/Data
(AD) bus. If the instruction fetched is an extended instruction, all EPUs and the CPU latch the instructiort If
the Z8070 is not busy when the instruction and data intended for it appear, the floating-point instruction is executed. If the Z8070 is busy, the CPU is stopped until the
Z8070 is no longer busy.
The Z80,OOO CPU differs slightly from the Z800 and
Z8000 CPUs described above. When the Z80,OOO CPU
detects an extended instruction, it first samples BSY. If
BSY is inactive, the CPU signals an EPU transaction
(status 0100) and places the extended instruction on the
AD bus. If BSY is active, the CPU samples BSY every
bus clock cycle until it is inactive. The CPU may
acknowledge bus requests or interrupt requests during
this period, and if this should happen before all
associated data transfers are complete, the CPU saves
the address of ,the extended instruction.
Universal Interface. With the Universal interface, the
Z8070 does not monitor the bus but, rather, waits until its
CS line becomes active, indicating that the instruction on
the bus is intended for it. The APU then reads data from
the bus during each Data Strobe until it has collected the
full instruction and associated data. The decoded instruction informs the Z8070 of the type of operation it is
to perform. When CS goes Low, it forces the Sequence
in Progress Signal (SIP) Low, and SIP stays Low until the
last bus transaction associated with the instruction is
complete.
The Universal interface can be set for a data bus width of
8-, 16-, or 32-bits with the BLlW and Bwi[ pins. A set of
interrupt control signals (INT, lEI, lEO) permit the integration of the Z8070 in a daisy-chain priority interrupt
scheme.
680
Bus Transactions
The following section describes bus transactions for the
Z800, Z8000, Z80,OOO,and Universal interfaces.
2800/Z8070 Bus Transactions. The 16-bit Z800 MPUs,
Z8116 and Z8216, incorporate Zilog's Extended' Processing Architecture (EPA) for Extended Processing
Units. The Z8116 is a 40-pin device that contains an
MMU, clock oscillator, and refresh controller on-Chip. It
does not have a PAUSE input. The Z8216 is a 64-pin
device which additionally contains four DMA channels,
four counter/timers, and a UART, and does have a
PAUSE input. When the Z800 encounters an EPU instruction, it fetches the following EPU template from
memory with instruction fetch status. (The opcode and
addressing mode portion of the instruction may be executed from cache, but the template will always be fetched from memory with status 1101 or 1100). When an
EPA template with the appropriate ID number is
detected, the Z8070 obtains or places data or status information on the bus using the Z800generated control
signals and performs its function as directed.
The Z800,MPU is responsible for instructing the APU and
delivering operands and data to it. The Z8070 recognizes
templates intended for it and executes them, using data
supplied with the template and/or data within its, internal
registers. There are three classes of APU instructions:
•
Data transfers between main memory and APU
registers.
r.!
Data transfers from APU registers to the CPU's accumulator.
•
APU internal operations.
Six Z800 addressing modes may be utilized with
transfers between APU registers and the CPU and main
memory:
..
Direct Address
•
Indirect Register
•
Indexed
II
Relative
II
Stack Pointer Relative
II
Base Index
The Z8070 connects to the Z800 via the BSY (PAUSE)
Signal, so that if the APU is requested to perform a second floating-point instruction before it has completed the
previous one, it can stop the CPU until execution of the
previous floating-point instruction is complete. BSY will
also be asserted if the instruction is a store.
Z8070/Z800 instruction execution is illustrated in Figure
16. The Z800 begins operation by fetching an instruction
and determining whether or not it is an extended instruction. If it is, the state of the EPU Enable bit in the Trap
Control register is examined. If the EPU Enable bit is
zero, The CPU generates a trap and may simulate the
APU in software. If the EPU Enable bit is set to 1, the four
byte EPA template is fetched from memory, with 1 1 a. a
indicated on status lines 8To-8T3. After fetching the
template, the l800 will; if necessary, transfer appropriate data between the CPU and memory or between the CPU and the APU. If the APU is not busy when
the data and template for it appear, the template is executed. If the APU is still processing a previous instruc:
tion, it asserts B8Y to halt further execution of CPU instructions until execution is complete. After the execu-
CLOCK _
Tn
T,
I
I
tion of the template is complete, the APU releases the
B8Y line and CPU instruction execution continues.
APU to CPU transfer transactions (Figure 16) have the
same form as 1/0 transactions, and thus are four clock
cycles long (unless extended by WAIT). 8T3-8To
1110, and the CPU output R/W indicates the direction of
data transfer. A l8070-memory read· is illustrated in
Figure 17 and a l8070-memory write is illustrated in
Figure 18.
=
T2
T3
~
,l
(~
WAIT
SAMPLED
DATA SAMPLED
FOR READ
r
WAIT CYCLES ADDED
WAIT
STATUS
(BNi, Nis,
5 To-5T3)
SNo-SNo
SEGMENT NUMBER
AS
MREQ
/
READ
(
~.
AD
MEMORY ADDRESS
READ
>---
~-
DATA IN
)
DS
~
READ
-
RIW
"
READ
L
/
AD
MEMORY ADDRESS
WRITE
APU DATA OUT
\
,
-
DS
WRITE~
\
WRITE
RIW
WRITE
~
\
L
MEMORY READ AND WRITE
Figure 16. Z8070·Z800 Transfer Transaction
2235-015
681
I_T1_I_T2_I_T3~1
~
I
ADo-AD15
RIW
STATUS
STATUS VALID
BIW = 1
Figure 17. Z8070·Memory Read Transaction (Z800)
I_T1-I-Tw-'I_T2_I_T3_I_TW~1
~
ADo-AD15
RIW
- K
STATUS
=1
I
ADDRESS
\
I
/
\
I
I \.
EPU DATA VALID
I
/
-
-
BIW
l
-
rL..I
STATUS VALID
= 1010
/
I
I
I
\
I
1
1
Figure 18. Z8070·Memory Write Transaction (Z800)
682
2235-016,017
Z8000/Z8070 Bus Transactions. l8000/l8070 transfer
transactions move data between the APU and CPU or
·between the APU and memory. The CPU can transfer
data to or from the APU, and provides address and bus
control signals for transfers between the APU and
memory.
When the l8070 is to participate in a memory transaction, the l8000 places its AD (Address/Data) lines into
the high impedance state while OS is Low, so that the
l8070 can use them. APU-memory transfer transactions
are the same as CPU-memory transactions (Figure 19).
The CPU generates the address, and status codes 1010
and 1011 are used. APU-CPU transactions have the
same timing relationship as I/O transactions (Figure 20).
In order to know which transaction it is to participate in,
the l8070 tracks the following sequence of events:
1.
2.
3.
the data (R/W Low) or captures the data (R/W High)
for each transaction. In both cases the CPU 3-states
its AD lines while data is being transferred (OS Low).
APU memory transfers are always word oriented
(B/W Low).
4.
If the instruction involves a transfer between the
CPU and APU, the next 1 to 16 non-refresh transactions by the CPU transfer data between the APU
. and CPU (ST3-STO = 1110).
To follow the above sequence, the l8070 has to monitor
the BUSACK line to verify that the transaction on the bus
is generated by the CPU. There is no indication on the
bus as to which EPU in a multiple EPU system is
coopcrrating with the CPU-this must be determined
from the opcodes and 10 fields of the extended instruction the APU captures.
When the CPU fetches the first word of an instruction (ST3-STO = 1101), the APU must also capture
the instruction returned by memory. If the instruction
is an extended instruction, it will have an 10 field
which indicates whether or not the APU is to execute
it.
With the first two instruction words, the l8070 determines:
If the instruction is to be executed by the APU, the
next non-refresh transaction by the CPU fetches the
second word of the instruction (ST3-STO = 1100).
The APU also captures this word.
If the instruction involves a read or write to memory,
there will b~ zero or more program fetches by the
CPU (ST3-STO = 1100) to obtain the address portion
of the extended instruction. The next 1 to 16 nonrefresh transactions by the CPU will transfer data
between memory and the APU. The APU supplies
[J
Whether or not a memory access will be made.
CJ
The number of words of data to be transferred for
APU-memory or APU-CPU transfers.
[J
The operation to be performed on the data.
A final aspect of l8000/Z8070 interaction is the use of
the BSY (STOP) signal If the system is in Non-Overlap
mode, the APU asserts BSY to stop the CPU whenever it
receives a floating-point instruction and its associated
data. If overlapping is allowed, when the l8070 begins to
execute a floating-point instruction the CPU can continue fetching and executing instructions. If the CPU
fetches another floating-point instruction before the first
one has completed execution, the APU asserts BSY until
I - l_I_ 2_I_ w_I_ 3_1
~
I
T
T
AOo-A015
- K
STATUS
B/W = 1
-
I
UNDEFINED
T
T
"
/
"
/
DATA
"
/
rL!
STATUS VALID
-
os
/
I
I
I
I
\
I
Figure 19. Z8070·Memory Transfer Transaction (Z8000)
2235-018
683
execution of the previous floating-point instruction is
complete. (In Intermediate Overlap mode BSY is not
asserted until a third APU instruction is fetched;) BSY is
always asserted if an instruction involves a store.
tion. The Z80,000 also transfers the PC value for the instruction, which the APU saves for use in exception
handling. If data transfers are required to complete the
instruction, the Z80,000 controls the data transfer transactions while the Z8070 drives or receives the data.
Z80,OOO/Z8070 Bus Transactions. When the Z80,000
CPU encounters an EPA instruction and the EPA bit in
the FCW is set to 1, the CPU broadcasts the first two
words of the instruction to the EPUs in the system using
the CPU-EPU instruction transfer transaction. All EPUs
in the system recognize the transaction, but the APU is
chosen specifically in bits 16 and 17 of the EPU instruc:
T1
II
CLOCK
. ..
TWA
T2
..
I
-
The signal BSY, output from the APU and wired to the
CPU's EPUBSY pin, is used to synchronize the CPU and
APU in executing floating-point instructions. The CPU
must sample BSY inactive before initiating an APU instruction transfer. If data transfers are required, the CPU
must sample BSY inactive before initiating the transfer.
'II
I
R
.
,t
(~
WAli
SAMPLED
..
T3
..
DATA SAMPLED
FOR READ
r
WAIT CYCLES ADDED
WAIT
_STATUS
(B/W, STo-ST3)
-
ex
"'S
AS
LOW
-
r\
HIGH
MREQ
AD
INPUT
(
)---'----
'.
J
DATA IN
> C
INPUT
RIW
INPUT
,~
AD
OUTPUT
L
-U
-
-
D<
CPU DATA OUT
DS
~
WRITE
R/Vi
OUTPUT
"
684
PORT ADDRESS
DS
TO <
CPU
TO
APU
- D<
-
"
r
Figure 20. Z8070·Z8000 Transfer Transaction
2235-019
status 0100, is shown in Figure 21. The transaction
begins with Address Strobe to indicate the AD lines and
status are valid. During T1 the AD lines are used to
transfer the opcode, which is the first two words of the
EPA instruction. At the beginning of T2 the CPU stops
driving the opcode, asserts OS, and starts driving the PC
on the AD lines.
BSY is also used to control the degree of overlap between CPU and APU instruction processing. Ordinarily
the CPU can continue processing other instructions after
performing the data transfers associated with a floatin-g
point instruction, and before the APU has completed executing the instruction. To simplify debugging and
recovery from exceptions, a Non-Overlap mode is provided, controlled by the EPU.O bit in the Z80,000 Hardware Interface Control Register. In Non-Overlap mode,
the CPU samples BSY in the middle of the bus cycle in
which the last data transfer for an extended instruction
occurs. If BSY is asserted, the Z80,000 ceases processing instructions or interrupts until BSY is sampled inactive in ttie middle of a bus cycle.
CPU·APU Data Transfer Transactions. Transactions
to transfer data between the CPU and APU use status
0001. The number of words transferred is known to the
CPU and EPU from the EPA instruction opcode (n-1
field). The transactions transfer one or more longwords
of data until all words have been transferred. If the last
transfer contains only a word, the data is replicated on
ADo-AD15 and AD16-AD31. The CPU does not assert
BRST and ignores RSPo-RSP1 and BRSTA.
CPU·APU Instruction Transfer Transactions. Timing
for a CPU-APU instruction transfer transaction, with
eLK
~
r
1--*_I
--'X
AD _ _ _ _ _ _ _
- I - 2-1
1 1 1+ I
T
T1
OPCODE
X
PC
)C
*EPUBSY sampled.
+ EPUBSY sampled II EPU Internal operation.
Figure 21. Z8070·Z80,OOO Instruction Transfer
2235-020
685
CPU·APU Da'ta Read. Timing for a CPU-APU -data read
transaction is shown in Figure 22. This example has two
data transfers; any. number of data transfers between 1
and 4 is possible. The transaction begins with Address
Strobe to indicate that the status and control signals are
valid. The CPU stops driving the AD lines at the end of T1,
and the APU begins driving the AD lines ,in the middle of
T2. At the beginning of T3 the CPU asserts DS. In the middle of T3 the CPU samples the data and negates DS. The
second longword of data is transferred during T4. After
the last data transfer the CPU inserts an idle bus cycle
(T5 in the example) during which neither the CPU nor
APU drive the AD lines.
1~-T1_I-T2-I-T3-1_-T4_I_T5_1
elK
J
I 1 I I I 1* I I I
---IX UNDEFINED >- - - -<'-___D_AT_A_IN__-JX. . .__DA_TA_I_N_.. I>- - - - - -C
1---*______I
I
AD _ _ _ _ _ _
LJ
AS
7
05 _ _ _---1
\~_ _ _ _~/
OE ______________
!
IE _ _ _ _ _
-J'!
~
R/W _ _ _ _ _ _ _
STo-ST3
BW/L, BLlW
His
BRST
BRSTA
*EPUBSY
X
_ _ _ _ _ _ _ '-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
)(
--/
-/
sampled.
Figure 22. Z8070·Z80,OOO Data Read Transaction
686
2235-021
CPU·APU Data Write. Timing for a CPU·APU data write
transaction is shown 'in Figure 23. This example has
three data transfers; any number of data transfers be·
tween 1 and 4 is possible. Timing for, the first transfer is
identical to the CPU·APU instruction transfer transac·
tion. A second longword of data is transferred during T3,
and the third longword is transferred during T4.
2 - i - I - 4-1
I I I I 1* I
T
,_T1-I-
CLK
.-J
I~*---II
I
x
AD _ _ _ _ _ _ _- - J
UNDEFINED
I
X
DATA OUT
T3
X
DATA OUT
T
X
DATA OUT
>C
\.
DS
/
E...:l
-~
(1,
~
e
\
OE
00
•
~
~
~
1
IE _ _ _ _.....J
\
Riw
STO-ST3 -------~X
BWIL, BLIW
tHS
. \..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
BRST
>C
~
/
----I
BRSTA
r
/
-----I
'EPUBSY sampled.
Figure 23. Z8070·Z80,OOO Data Write Transaction
2235-O:l2
687
APU·Memory Transactions. The CPU uses status
1010 or 1011 for the APU to read from and write to
memory. The timing for an APU-memory read is identical
to a CPU-memory read. The APU passively monitors the
CPU timing on the bus, and uses the two least-significant
address bits, the data transfer size, and the length of the
operand from the instruction to select the bytes it needs
from the AD line.
The timing for an APU-memory write differs slightly from
a CPU-memory write. Two extra bus cycles are included
to pass the AD lines from CPU to APU after the address
transfer and from APU back to CPU after the last data
transfer. An example is shown (Figure 24) for a single
APU-memory data transaction with no wait states. The
CPU stops driving the AD lines at the end of T1, and the
APU begins driving the AD lines in the middle of T2. OS is
asserted in the middle of T3, one bus cycle later than for
CPU-memory write timing. The CPU negates OS in the
middle of T4. The CPU can insert wait states in the middle of T4. The APU continues to drive the AD lines until
the end of T4. After the last data transfer the CPU inserts
an idle bus cycle (T5 in the example) during which neither
the CPU nor APU drive the AD lines. APU-memory burst
write transactions are similarly extended by two bus
cycles compared with CPU-memory burst write timing.
One cycle is inserted before· the first data transfer, and
another cycle after the last data transfer.
I
I
'--_ _ _ _ _
A_PU_D_A_TA_O_U_T_ _ _ _ _...,)- -
-
-
-
-c
\'-------JI
L
~
___________________K
*EPUBSY sampled.
+ RSPo-RSPl
__
sampled; EPUBSY sampled" last transaction.
Figure 24. Z8070·Memory Single Write Timing (Z80,000)
688
2235-023
Universal Bus Transactions. The Universal interface is
designed to accommodate a wide variety of CPUs. It can
be tailored for data bus sizes of 8 bits, 16 bits and 32 bits.
In transfers of data strings between the Z8070 and
memory or the CPU, the MSB is presented first, and the
data is left-justified, starting on pin DBo, when odd
numbers of strings are being presented. For example, a
Z8070/memory transaction involving the double extended number 123456789ABCDEF02468 would be sent on a
long-word (32 bit) bus as follows:
first longword 12345678
second longword 9ABCDEFO
third longword 2468xxxx
(where x = don't care)
The CPU samples SIP and BSY before initiating an instruction transfer to the APU. If both signals are inactive,
the CPU asserts CS and controls the bus to transfer the
floating-point instruction and any associated data. The
APU recognizes that an instruction is for it when both CS
and OS are asserted. The APU then asserts SIP to signal
that an APU sequence is in progress.-SIP stays Low
throughout the bus transaction portion of instruction processing. This prohibits the CPU from initiating another
floating-point instruction transfer until the APU's Inter-
DB
face Processor is empty. If an instruction is executing in
the Data Processor and another instruction is queued in
the Interface Processor, the APU asserts BSY until the
Interface Processor is empty. As with other CPU options,
the APU asserts BSY on receiving any instruction involving a store. Figure 25 illustrates Universal Interface bus
transactions.
Exception Processing
When the Z8070 detects an exception (and the particular
interrupt mask and master interrupt enable are enabled)
it asserts INT. If there is an instruction in the instruction
queue that was queued or being queued when the interrupt occurred, this queued instruction will be invalidated
("flushed" without being executed). If the Z8070 has
BSY asserted, (e.g., the queued instruction is a store)
then BSY will be negated so that the store instruction
can have the Z8070-memory transaction completed.
This stores undefined data in memory, and the store instruction is effectively invalidated. If an instruction has
been invalidated, the RPC bit in the System Configuration register is set, indicating that the instruction was invalidated and must be re-executed. If an interrupt occurs
and the queue is empty, RPC is not modified.
----«'-___VA_L_ID_ _ _) > - - - - - - - - - - - - - «
VALID
»)----C(
VALID
»)----
Typical Z8070 Universal Interlace Transaction
\------1/
CS
SIP
DS
I
.r-c _ _ _
\\.-----J1
~~---------------------------------------------/
,F-r- - - - - , . \
DATA
I
BSY Function During Universal Interlace Store
Flguro 25. Unlvorsal Intorfaco Transfor Transaction
00-2235-01
2235-024
689
~annmnImary
rf'Ircdmcl
~l1De(CnfneaftRoJm
September 1983
FEATURES
c
Full 32-bit architecture and implementation
[J
EJ,
4 gigabytes (billion bytes) of directly addressable
memory
Extended Processing Architecture supports floating
point operations
[J
Regular use of operations, addressing modes, and
data types in instruction set
[J
System and Normal modes of operation with
separate stacks
[J
Sophisticated interrupt and trap handling
[J
Software is a binary-compatible
Z8000™ software
[J
Hardware is compatible with other Z_BUSTM components
E1
Linear or segmented address space
a
Virtual memory management integrated with CPU
[]
On-chip cache memory
I£]
General-purpose register file with 16 32-bit registers
[J
9 general addressing modes
[;J
Numerous data types include bit, bit field, logical
value, signed integer, and string
extension
of
m Mainframe performance
GENERAL DESCRIPTION
The Z80,OOO CPU is an advanced, high-end 32-bit
microprocessor that integrates the architecture of a
mainframe computer into a single chip. While maintaining full compatibility with Z8000 family software and
hardware, the Z80,OOO CPU offers greater power and
flexibility in both its architecture and interface capability.
Operating systems and compilers are easily developed
in the Z80,OOO CPU's high-quality environment, and the
hardware interface provides for connection to a wide
variety of system configurations.
Addresses in the Z80,OOO CPU are 32 bits. This allows
direct addressing of 4G bytes in each of four address
spaces: System"mode data, System-mode instruction,
Normal-mode data, and Normal-mode instruction. The
CPU supports three modes of address representation.
The 16-bit compact addresses are compatible with
Z8000 nonsegmented mode. The 32-bit segmented addresses include both 16-bit offset, which is compatible
with Z8000 segmented mode, and 24-bit offset. In,addition a full 32-bit linear address space is provided.
The CPU features a general-purpose register file with
sixteen 32-bit registers, and nine operand addressing
modes. The various addressing modes allow encoding
choices for compact representation or for full 32-bit addressing. The instruction set can operate on bit, bit field,
logical value, Signed integer, unsigned integer, address,
string, stack, and packed decimal byte data types.
Logical and arithmetic instructions operate on bytes (8
bits), words (16 bits) and longwords (32 bits). The Extended Processing Architecture (EPA) supports floating point
operations. In addition, the instruction set is highly
regular in combining operations, data types, and addressing modes. High-level language compilation is supported with instructions for procedure linkage, array index calculation, and bounds checking. Other instructions provide operating system functions such as system
call and control of memory management.
There are two main operating modes, System and Normal, supported by separate stacks. User programs
operate in Normal mode, while sensitive operating
691
, I
system functions are performed in System mode. This
protects critical parts of the operating system from user
access. In addition, some instructions are privileged,
and execute only in System mode. Memory management
functions protect both system memory from user programs, and user memory from other users. Vectored,
nonvectored, and nonmaskable interrupts support realtime operating systems.
Memory management is fully integrated with, the CPU;
no external support circuitry is necessary. A paging address translation mechanism is implemented. Registers
in the CPU point to address translation tables located in
memory; the most recently used table entries are kept in
a Translation Lookaside Buffer in the CPU. The CPU performs logical to physical address translation and access
protection for each memory reference. When a logical
memory reference causes a translation or protection
violation, the state of the CPU is automatically restored
to restart the instruction. 1/0 ports can be referenced
either by. dedicated instructions or by the memory
management m~chanism mapping logical memory addresses to 1/0 port addresses.
Extensive trapping facilities, such as integer overflow,
subrange out of bounds, and subscript out of bounds,
catch common run-time errors. Software debuggers can
use trace and breakpoint traps. Privileged instruction
traps and memory protection violation traps secure the
operating system from user programming errors or
mischief. The Overflow Stack allows recovery from
otherwise fatal errors.
The CPU has full 32-bit internal address and data paths.
Externally, 32 pins time-multiplex the address and data.
The interface is compatible with the complete line of
Z-BUS peripherals. The hardware interface features
16-bit or 32-bit memory data path and programmable
Wait states. Burst transfers and an on-chip cache for instructions and data help develop high-performance
systems. The interface supports multiprocessing configurations with interlocked memory references and two
typ.es of bus reque$t protocols. The system designer can
.tailor the Z80,000-based system to cost and performance needs.
In summary, the Z80,000 CPU meets and surpasses the
requirements of medium and high-end microprocessor
systems for the 1980s. Software program development
is easily accomplished with the CPU's sophisticated architecture. The highly pipelined design, on-Chip cache,
and external interface support systems ranging from
dedicated controllers to mainframe computers. While
Zilog continues to develop support for the Z80,000 CPU,
Z8000 peripherals and development software are fully
compatible with this latest in Zilog's line of highperformance microprocessors.
REGISTERS
The Z80,000 CPU is a register-oriented processor offering sixteen 32-bit general-purpose registers, a 32-bit Program Counter (PC), a 16-bit Flag and Control Word
(FCW), and nine other special-purpose registers.
The general-purpose register file (Figure 1) contains 64 bytes. of storage. The first 16 bytes
(RLO,RHO, ... ,RL7,RH7) can be used as accumulators for
byte data. The first 16 words (RO,R1 ,... ,R15) can be used
as accumulators for word data, as index registers (except RO), or for memory addresses in compact mode (except RO). Any longword register (RRO,RR2, ... ,RR30) can
be used as an accumulator for longword data, an index
register (except RRO), or for memory addresses in linear
or segmented modes (except RRG). Quadword registers
(RQO,R04, ... ,R028) can be used as accumulators for
Multiply, Divide, and Extend Sign instructions. This
unique register organization allows bytes and words of
data to be manipulated conveniently while leaving most
of the register file free to hold addresses, counters, and
any other data.
·Two registers are dedicated to the Stack Pointer (SP) and
Frame Pointer (FP) used by Call, Enter, Exit, and Return
692
instructions. In compact mode, R15 is the Stack Pointer
and R14 the Frame Pointer. In linear or segmented
mode, RR14 is the Stack Pointer and RR12 is the Frame
Pointer.
RQO {
RQ4 {
RQ8 {
RRO
7 RHO
RR2
7 RH2
RR4
7 RH4
RR6
7 RH6
o
o
o
o
RR8
15
R8
RR10
15
R10
15
R12
15
R14
RQ12{ RR12
RR14
31
7 RLO
7 RL2
7 RL4
7 RL6
o
o
o
o
o
o
o
o
7 RH1
o
7 RL1
0
RO, R1
7 RH3
0
7 RL3 0
R2, R3
7 RH5
0
7 RL5 0
R4, R5
7 RH7 0
7 RL7 0
R6, R7
15
R9
0
15
R11
0
15
R13
0
15
R15
0
0
RQ16 {RR16
RR18
31
0
RR20
31
0
RR22
31
0
RR24
31
0
RR26
31
0
RR28
31
0
{ RR30
31
0
RQ20 {
RQ24 {
RQ28
Figure 1. General·Purpose Register File
2071'()()1
The PC and FCW form the Program Status (Figure 2),
which is automatically saved for traps and interrupts.
The bits in FCW indicate operating modes, masks for
traps and interrupts, and flags set according to the result
15
8
IEJC'S/N'EPA'VIE'NVI~ US, TPI
T i C , Z I S IPNI
of instructions. The remaining special registers are used
for memory management, system configuration, and
other CPU control (Figure 3).
7
0
0I
H 'IV
1
I
0
I~
INTEGER OVERFLOW ENABLE (IV)
HALF CARRY (H)
DECIMAL-ADJUST (D)
PARITY/OVERFLOW (PIV)
SIGN (S)
ZERO(Z)
CARRY (C)
TRACE (T)
TRACE PENDING (TP)
LINEAR/SEGMENTED MODE (US)
NONVECTORED INTERRUPT ENABLE (NVIE)
VECTORED INTERRUPT ENABLE (VIE)
EXTENDED PROCESSOR ARCHITECTURE (EPA)
SYSTEMINORMAL MODE (S/N)
EXTENDED/COMPACT MODE (EJe)
FLAG AND CONTROL WORD (FCW)
o
31
PROGRAM COUNTER (PC)
Figure 2. Program Status Registers
ADDRESS SPACES
As shown in Figure 4, the CPU has three modes of address representation: compact, segmented, and linear.
The mode is selected by two control bits in the Flag and
Control Word register (see Table 1). The Extended/Compact (E/C) bit selects whether compact addresses (16
bits) or extended addresses (32 bits) are used. For extended addresses the Linear/Segmented (US) bit selects
whether linear or segmented addresses are used.
The Load Address instruction can be used to manipulate
addresses in any mode of representation.
In compact mode, addresses are 16 bits. Address
calculations using compact addresses involve all 16 bits.
Compact mode is more efficient and less programconsuming for applications requiring less than 64K bytes
of program and less than64K bytes of data. This efficien-
2071'()()2
cy is due to shorter instructions in· compact mode, and
the fact that addresses in the register file use word
rather than longword registers. Applications requiring
more than 64K bytes of either program or data should
use segmented or linear modes.
Table 1. Address Representation
Control Bits in FCW
Representation
E/e
US
o
o
Compact
o
1
Reserved
Segmented
Linear
o
693
31
PROGRAM STATUS AREA POINTER (PSAP)
31
NORr.,AL STACK POINTER (NSP)
0
31
SITTD
II
II
II
NLTB
PROT
G
SIZ
TF
NDTTD
G
NLTB
PROT
SIZ
TF
NLTB
PROT
SIZ
TF
NLTB
PROT
SIZ
TF
0
31
NITTD
G
0
31
SDTTD
I
I
I
0
31
II
G
I
TRANSLATION TABLE DESCRIPTOR REGISTERS
31
OVERFLOW STACK POINTER (OSP)
HARDWARE INTERFACE CONTROL REGISTER (HICR)
31
o
0
0
0
00000000
o
0
0
0
0
SYSTEM CONFIGURATION CONTROL LONGWORD (SCCL)
Figure 3. Speclal·Purpose Control Registers
694
2071-003
15
(A) COMPACT ADDRESSES
31
30
16 15
,
SEGMENT
I
,
,
"
I
I
.0
I
I
,
I
I
OFFSET
,
,
(I) 64K BYTE SEGMEtlT SIZE,
31
30
2423
SEGMENT
I
I
I
I
I ,
I
,
,
,
,
,
I
OFFSET
,
,
(II) 16M BYTE SEGr.. ENT SIZE
(B) SEGMENTED ADDRESSES
o
31
, , , , ,
"
0' .
(C) LINEAR ADDRESSES
Figure 4. Address Representations
In segmented mode, addresses are 32 bits. Segmented
addresses are composed of either a 15-bit segment
number and a 16-bit segment offset or a 7-bit segment
number and a 24-bit segment offset. Bit 31 of the address selects either of the two types of segmented addresses. Address ,calculations using segmented addresses involve only the segment offset; the segment
number is unaffected. In segmented mode, the address
space allows up to 32,768 segments of 64K.byte maximumsize and up to 128 segments of 16M byte maximum size. Many applications benefit from the logical
structure of segmentation by allocating individual" objects, such as a program modUle, stack, or large data.
structure, to separate segments:
In linear mode, addresses are 32-bits. Address calculations using linear addresses involve all 32 bits. In linear
mode, the address space of 4G bytes is uniform and
unstructured. Many applications benefit from the flexibility of linear addressing. by allocating objects at arbitrary positions in the address space. .,
Memory ,is byte addressable by .the CPU. Th,eaddress
used for·. multiple-byte. data. is tre' address' 6f the most
significant byte. Multiple-byte data can be located at any
byte address with nb alignment restrictions.
110 ports can be addressed by either dedicated 'instructions or by the memory management. mechanism mapping logical memory addresses to I/O ports. 110 ports
can be byte, word, or longword in size.
NORMAL AND SYSTEM MODES
The CPU has two modes of operation, Normal and
System, selected by the SiN bit in the Flag and Control
, Word register. These modes impact on CPU operation in
three areas:privilegedins!fuctions, stack painters, and
memory manage,ment. ."
Since the most' sensitive portions of the operating
system usually execute in System mode, separate stack"
pointers are used to isol~lte. the two operating modes.
2071-004
Some instructions, such as those performing I/O operations or accessing control registers, can only be. executed in System mode; in addition,themernOry
management. mechanism .' allowsacces~tosome
memory. locations in System mode only .. Prograrns,e~~
ecuting,in Normal mode can re·q4estS.ervic~s from 'the
operating system using theSysteni Calf instruction and
trap.
. .
.
695
MEMORY MANAGEMENT
The CPU and the operating system cooperate in
translating logical to physical addresses and protecting
memory for execute, read, and write accesses. The CPU
implements a paging translation mechanism similar to
that in most mainframe and super-minicomputers. The
operating system creates translation tables in memory,
then initializes pointers to the tables in control registers.
The CPU automatically references the tables to perform
address translation and access protection. The CPU
enables the operating system to implement efficient virtual memory by marking pages that have been referenced or modified and by automatically recovering from
address translation faults to allow instruction restart.
The paging translation scheme implemented by the CPU
divides the logical address spaces into pages and the
physical address space into frames. The logical pages
and physical frames are each 1K bytes. A logical page,
which is specified by the 22 most significant bits of the
logical address, ,can be mapped into any physical frame,
which is specified by the 22 most significant bits of the
physical address. The 10 least significant bits, which
specify the byte within a page or frame, are not
translated. For each memory reference, the CPU
translates the logical address to the corresponding
physical address and also tests whether access to the
memory location is permitted. For most references the
information needed to perform the translation is stored
in the CPU Translation Lookaside Buffer (TLB). The TLB
(Figu re 5) stores the translation information for the 16
most recently referenced pages in a fully associative
memory. Only when information to translate the page is
missing from the TLB does the CPU reference translation tables in memory. In the case of a TLB miss, the
CPU translates the logical address using the procedure
described below and the translation information is loaded into the TLB entry of the le,ast recently referenced
page.
31
10 9
PAGE ADDRESS
TRANSLATION
LOOKASIDE
BUFFER
P~~!I~:L
LOGICAL PAGE
ADDRESS TAGS
ADDRESSES
PHYSICAL ADDRESS
Figure 5. Address Translation USing the TLB
-0-
-0-
TA BLE DESCRIPTOR
REGISTORS
+
31
LOGICAL ADDRESS
I
J
L1·NO
PAGE TABLE
LEVEL 2
TABLE
LEVEL 1
TABLE
24 23
I
16 lS /10 9
L2·NO
I
P·NO
I
0
31
109
PAGE TABLE,
ENTRY
P,OFFSET
T
TRANSLATION
LOOKASIDE
BUFFER
LOGICAL PAGE
ADDRESS TAGS
PHYSICAL
FRAME
ADDRESSES
Figure 6. Automatic Loading of the TLB Using Tables in Memory
696
2071'()05,006
The address translation mechanism is a three-level paging scheme. A logical address is partitioned into an 8-bit
level-1 field (L 1-NO), an 8-bit level-2 field (L2-NO), a 6-bit
page number field (P-NO), and a 10-bit page offset field
(P-OFFSET). During translation, the L1-NO, L2-NO, and
P-NO fields are used as indexes into tables in physical
memory. The TF field of the Segment Table Descriptor
registers can be programmed to select!vely skip the first
and second-level tables to reduce both the storage
space needed for tables and the number of references
necessary to perform translation when the information to
translate a page is missing from the on-chip TLB.
To load the TLB (Figure 6), the CPU selects one of four
table descriptor registers according to the address
space for the reference: system instruction, system
data, normal instruction, or normal data. The table
descriptor register points to the beginning of the level-1
table in memory; the L1-NO field of the logical address is
used as an index into this table to select the level-' table
entry. Next, the level-1 table entry points to the beginning of the level-2 table; the L2-NO field of the logical address is used as an index into this table to select the
level-2 table entry. After this, the level-2 table entry
points to the beginning of the page table in memory; the
PAGE-NO field of the logical address is used as an index
into this table to select the page table entry. The page
table entry contains the physical address of the frame
corresponding to the logiCal address. The CPU then
loads the logical page address and physical frame address into the TLB.
31
TABLE FORMAT (TF)
L..-_ _ _ _
L..-_ _ _ _ _ _ _ _ _ ~ffi t:~TE~
L..-_ _ _ _ _ _ _ _ _ _ _ _
Access protection information (Table 2) is encoded in the
4-bit PROT field contained in the Translation Table
Descriptor, level-' table entry, level-2 table entry, or
page table entry. During the translation process, a PROT
field is encountered at each level. The first PROT field
with value other than' 000 is selected; the other PROT
fields are ignored. The protection code specifies the
types of access (execute, read, and write) permitted in
Normal and System modes.
TABLE
GROWTH DIRECTION (G)
Table Format
(TF)
00
01
10
11
THREE LEVELS
SKIP LEVEL 2 TABLES
SKIP LEVEL 1 TABLES
SKIP LEVEL 1 AND LEVEL 2 TABLES
TADL[; SIZE
(SIZ)
VALID TABLE ENTRIES
0=0
0=1
00
OTO 63
o TO 255
01
o TO 127
64 TO 255
10
OTO 191
. 128 TO 255
11
o TO 255
192 TO 255
Figure 7. Translation Table Descriptor
31
3
2
1
0
VALID (V)
' - - - - TABLE SIZE (SIZ)
L....-_ _ _ _ PROTECTION (PROT)
1...-_ _ _ _ _ _ _ _ _
L..-_ _ _ _ _ _ _ _ _ _ _ _ _
~:~ t:~i~ TABLE
GROWTH DIRECTION (G)
LEVEL 1 TABLE EUTRY
31
When bit 31 in the page table entry is " the frame is in
physical I/O space. The CPU uses I/O status and timing
for the reference .. Thus, the address translation process
allows protected access to memory-mapped I/O
devices.
Figures 7 and 8 show the translation and table entry formats.
TABLE SIZE (SIZ)
PROTECTION (PROT)
1
0
L....-_ _ _ _
1...-_ _ _ _ _ _ _ _ _
VALID (V)
PROTECTION (PROT)
NEXT LEVEL TABLE
BASE (NLTB)
LEVEL 2 TABLE EUTRY
31
r-r-------.,.--r---r..,....,.....,.....
REFERENCED (R)
VALID (V)
MODIFIED (M)
1...--_ _
NONCACHEABLE (NC)
' - - - - - - PROTECTION (PROT)
L....-_ _ _ _ _ _ UNUSED
L..-_ _ _ _ _ _ _ _ _
L....-_ _ _ _ _ _ _ _ _ _ _ _ _
FRAME ADDRESS (FA)
1/0
PAGE TABLE EUTRY
Figure 8. Table Entry Formats
2071-007,008
697
Table 2. Protection Field Encoding
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
.1010
1011
1100
1101
1110
1111
System
Normal
NA
RE
RE
RE
E
E
R
R
Note
RW
RW
RW
RWE
RWE
RWE
RWE
NA
NA
E
RE
NA
E
NA
R
Note
NA
R
RW
NA
E
RE
RWE
NA-no access is permitted
R-read access is permitted
W-write access is permitted
E-execute access is permitted
Note-use the protection field of the next level translation table or NA
(for page tables)
There are several optional features that allow the
number of levels and the size of tables to be reduced.
When memory address spaces are not separated, two or
more of the· translation table descriptor registers can be
loaded with the same value so that tables are held in
common. The table descriptor register can specify that
either or both of the level-1 and level-2 tables should be
skipped during the translation process. Level-1 tables
can be skipped when a 24-bit logical address space is
sufficient, both level-1 and level-2 segment tables can be
skipped for compact addresses, and level-2 tables can
be skipped for compatibility with Z8000 segmented addresses. The table size can be reduced by allocating
only 256, 512, or 768 bytes for the tables; the remaining
table entries are assumed invalid. The tables can be
allocated efficiently for downward growing stacks by setting the G bit of the translation table descriptor or level-1
table entry.
During execL:tion of an instruction, if an invalid translation table entry is encountered or a protection violation is
detected, the CPU traps to the operating system. The
CPU automatically saves the state of registers and
memory so the instruction can simply be restarted.
Several instructions are provided to help the operating
system control memory management. The Purge TLB instructions are used to purge the Translation Lookaside
Buffer of a single entry, Normal mode entries, or all en(tries. The Load Physical Address instructions translate
logical addresses into physical addresses, and set the
flags to verify access permission for system call
parameters. The instructions, Load Normal Data and
Load Normal Instruction allow System mode programs
to reference Normal memory spaces.
The memory management mechanism can be selectively enabled for normal and system space references by
using the SX and NX bits of the System Configuration
Control Longword register.
EXCEPTIONS
The CPU supports four types of exceptions: Reset, Bus
Error, interrupts, and traps. A reset exception occurs
when the RESET line is activated; this causes the CPU to
be reset to an initialized state. A bus error exception occurs when externalrhardware indicates an error on a bus
transaction. An interrupt is an asynchronous event that
typically occurs when a peripheral device needs attention. A trap is a synchronous event that occurs when a
particular condition is detected during execution of an instruction.
698
In responding to a reset exception, the CPU fetches the
program status (FCW and PC) from physical address 2.
In responding to other exceptions, the CPU pushes the
old program status onto the system stack along with information specific to the type of exception. The CPU
then fetches a new program status from the table
designated by the Program Status Area Pointer control
register.
During exception processing, the mode of address
representation for the system Stack Pointer and Program Status Area Pointer is either linear or segmented,
selected by the XLIS bit in the System Contfguration Control Longword register. Three types of interrupts are supported: vectored, nonvectored, and nonmaskable. The
vectored and nonvectored interrupts have mask bits in
the FCW. All interrupts read an identifier word from the
bus during an Interrupt Acknowledge transaction and
save the word on the system stack. Vectored interrupts
use the lower byte of this word to select a unique PC
value from the Program Status Area.
when tracing is enabled by setting the T bit in the
FCW.
o
Breakpoint Trap occurs when the Breakpoint instruction is executed, usually to invoke a debugging or
monitoring program.
o
Conditional Trap occurs when the Conditional Trap
instruction is executed and the specified condition
code is satisfied. This trap can allow detection of
user-defined exceptions.
o
Integer Overflow Trap occurs when overflow is
detected during execution of an integer arithmetic
instruction and the IV bit in the FCW is set.
The CPU recognizes twelve trap conditions.
o
Extended Instruction Trap occurs when an Extended
Processing Architecture instruction is executed and
the EPA bit in the FCW is clear.
o
Bounds Check Trap occurswhen the Check instruction is executed and the source operand is out of
bounds.
o
Privileged Instruction Trap occurs when an attempt
is made to execute a privileged instruction in Normal
mode.
,0
Subscript Error Trap occurs when the Index instruction is executed and the subscript operand is out of
bounds.
o
System Call Trap occurs when the System Call instruction is executed to request service from the
operating system.
o
Address Translation Trap occurs when an address
translation or access protection violation is
detected.
o
Reserved Instruction Trap occurs when an attempt
is made to execute 'an instruction' with a reserved bit
pattern.
o
Odd PC Trap occurs when an odd-byte address is
loaded into the PC.
o
Trace Trap occurs after execution of an instruction
In descending order, the priority of exceptions is: reset,
bus error, trap (other than trace), nonmaskable interrupt,
vectored interrupt, and nonvectored interrupt. Trace
Trap uses two control bits, T and TP, so that when tracing is enabled, exactly one trace trap occurs after each
instruction is executed.
When an address translation trap occurs for the system
stack, the CPU cannot save the program status and
other exception information on the system stack. The
system can still recover from this otherwise fatal error .
because the CPU saves the information on the Overflow
Stack designated in physical memory by the Overflow
Stack Pointer control register.
ADDRESSING MODES
The CPU locates operands (the data manipulated by instructions) in registers, memory, I/O ports, or in the instruction. The location of an operand is specified by one
of nine addressing modes (Figure 9): Register (R), Immediate (1M), Indirect Register (IR), Direct Address (DA),
Index (X), Base Address (BA), Base Index (BX), Relative
Address (RA), and Relative Index (RX). Most operations
can be used with any addressing mode; however, some
operations are restricted. Instruction encoding provides
compact representation for the most frequently used addressing modes.
The term Extended Addressing Modes (EAM) refers to
the following addressing modes that require one or more
extra words to be added to the opcode.
o
o
In compact mode: DA and X (X is equivalent to BA)
In linear or segmented modes: DA, X, BA, BX, RA,
and RX
699
Addressing Mode
Operand Value
Operand Addressing
In tho Instruction
In a Register
In Memory
R
Register
1
REGISTER ADDRESS
H
OPERAND
1
Tho content of the
register
1M
Immediate
1 OPERAND
In tho Instruction
*IR
Indirect
Register
~GISTER ADDRESS
H
ADDRESS
-I
OPERAND
The content of the
location whoso
address Is In the
reglstor
-I
OPERAND
The content of the
location whose address
Is In the Instruction
DA
Direct
Address
ADDRESS
*X
The content of the
location whose
address is the address
In the Instruction. plus
the content of tho
Index register
REGISTER ADDRESS
Index
BASE ADDRESS
RA
PC VALUE
Relative
Address
DISPLACEMENT
~I
OPERAND
*BA
Base
Address
REGISTER ADDRESS
DISPLACEMENT
OPERAND
*BX
Base
Index
OPERAND]
OPERAND
The content of the
location whoso
addreso Is tho content
of the Program
Counter. plun the contont of the Index
reglotor. plus tho
dlsplacoment In the
Instructlon.
DISPLACEMENT
*RX
PC VALUE
Relativo
Index
INDEX
1='0--1
The contont of tho
location whose
address Is the content
of the Baso reglstor.
plus the displacGmGnt
In the Instruction
The content of the
location whoso
addross Is the content
of the Base register.
plus the content of
the Indox register.
plus the displacement
In the Instruction
REGISTER ADDRESS
REGISTER ADDRESS
The contont of the
location whose
address Is tho address
In tho Instructlon. plus
tho content of the
Index register
*RO and RRO cannot bo used for Indirect. Baso. or Index registors
Figuro 9. Addressing Modes
700
2071.()()9
DATA TYPES
The CPU supports operations on the following data
types.
EJ
Bit
c
Logical value-byte, word, and longword
EI
Bit field-1 to 32 contiguous bits within a longword
[]
Address
rEI
Signed integer-byte, word, longword, and quadword
[]
Packed BCD integer-byte
[]
Stack-word and longword
[]
String-dynamic length byte, word, and longword
m Unsigned integer-byte, word, longword, and quadword
FLAGS AND CONDITION CODES
Arithmetic, logical, and many other instructions affect
the six flag bits (C, Z, S, PN, D, and H) in the FCW to provide information about an operation's result. Generally,
C indicates carry or borrow from the result, Z indicates
the result is zero, S indicates whether the result is
negative or positive, and PN indicates parity or overflow.
D and H are used for decimal arithmetic.
Jump, Test Condition Code, and several other instructions test the state of the flags. The conditions that can
be tested are shown in Table 3.
Table 3. Flags and Condition Codes
Code
F
T
Z
NZ
C
NC
PL
MI
NE
EQ
OV
NOV
PE
PO
GE
LT
GT
LE
UGE
ULT
UGT
ULE
Meaning
Always false
Always true
Zero
Not zero
Carry
No carry
Plus
Minus
Not equal
Equal
Overflow
' No overflow
Parity even
Parity odd
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
Flag Setting
Z = 1
Z=O
C=1
C=O
5=0
5 = 1
Z=O
Z = 1
V = 1
V=O
P = 1
P=O
(5 XOR V) = 0
(5 XOR V) = 1
(Z OR (5 XOR V») = 0
(Z OR (5 XOR V») = 1
C=O
C = 1
((C = 0) AN D (Z = 0) = 1
(C OR Z) = 1
Binary
0000
1000
0110
1110
0111
1111
1101
0101
1110
0110
0100
1100
0100
1100
1001
0001
1010
0010
1111
0111
1011
0011
Some of the condition codes correspond to identical flag settings: i.e .• Z-EQ. NZ-NE. NC-UGE. PE-OV, PO-NOV.
701
INSTRUCTION SeT SUMMARY
The CPU provides 11 types of
in~tructions:
•
Block Transfer and String Manipulation
•
Load and Exchange
•
Input/Output
•
Arithmetic
•
CPU Control
•
Logical
•
Bit Field
•
Program Control
•
Extended Instructions
•
Bit Mcmipulation
•
Rotate and Shift
Instructions are encoded in one or more words, located
in memory at even addresses.
Load and Exchange
Mnemonic
Operands
Addressing Modes
Operation
CLR
CLRB
CLRL
dst
dst: R,IR,EAM
Clear
CVTBW
CVTBL
CVTWB
CVTWL
CVTLB
CVTLW
dst,src
CVTUBW
CVTUBL
. CVTUWB
CVTUWL
CVTULB
CVTULW
dst,src
dst -
EX
EXB
dst,src
LO
LOB
dst,src
dst: R
src: R,IR,EAM
or
dst: IR,EAM
src: R
Convert
dst: R
src:R,IR,EAM
or
dst: IR,EAM
src:R
Convert Unsigned
dst: R
src: R,IR,EAM
EXC
LDL
LPA
LOA~
.. LOK
dst,src .
dst;src
dst,n
LPKL
~c~mpact rTl~~ allows BX with ~a disPlaceme~t for EAM.
702
0
dst: R
src: R,IM,IR,EAM*
or
dst: IR,EAM*
src: R,IM
dst: R
. sra: EAM*
dst: R
src.:RA
dst -
dst -
convert (src)
convert (src)
Exchange
dst -
src
Load
dst -
src
Load Address
dst.· - Address (src)
.Load Address Relative
dst - Address (src)
dstR
Load Constant
n: 1M·
dst - n .
(n = 0 .. 15)
Load and Exchange (Continued)
Mnemonic
Operands
Addressing Modes
Operation
LDM
dst,src,n
dst: R
src: IM,IR,EAM
n: 1M
Load Multiple
dst -
src (n words)
or
dst: IR,EAM
src: R
n: 1M
LDML
mask,src
or
dst,mask
mask: 1M
src: IM;IR,EAM
or
dst: IR,EAM
src: 1M
Load Multiple Long
dst (register mask) - src
or
dst - src (register mask)
N
CO
LDR
LDRB
LDRL
POP
POPL
PUSH
PUSHL
dst,src
dst,src
. dst,src
dst: R
src: RA
or
dst: RA
src: R
dst: R,IR,EAM
src: IR
dst: IR
src: R,IM,IR,EAM
p
Load Relative
dst -
0
g
src
...c:I
6
Pop
dst - src
Autoincrement src address
Push
Autodecrement dst address
dst - src
Arithmetic
Mnemonic
Operands
Addressing Modes
Operation
ADC
ADCB
ADCL
dst,src
dst:' R
src: R
Add with Carry
ADD
ADDB
ADDL
dst,src
dst: R
src: R,IM,IR,EAM
Add
CHK
CHKB
CHKL
dst,src
CP
CPB
CPL
dst,src
DAB
dst
dst: R
Decimal Adjust
DEC
DECB
DECL
dst,n
dst: R,IR,EAM
n: 1M
Decrement
. dst: R
src: IM,IR,EAM
dst: R
src: R,IM,IR,EAM
or
dst: IR,EAM
src: 1M
dst -
dst -
dst
+ src +
dst
+ src
C
Check
compare dst with src bounds
if out of bounds then trap
Compare
dst - src
dst - dst - n
(n = 1..16)
703
Arithmetic (Continued)
Mnemonic
Operands
Addressing Modes
Operation
DECI
DECIB
dst,n
dst: IR,EAM
n: 1M
Decrement Interlocked
dst - dst - n
(n
1..16)
=
/: ,.
\\ ~
\-,'
,.~~"\
~
..
DIV
DIVL
dst,src
DIVU
DIVUL
dst,src
EXTS
EXTSB
EXTSL
dst
INC
INCB
INCL
dst,n
INCI
INCIB
dst,n
dst: R
src: R,IM,IR,EAM
dst: R
src: R,IM,IR,EAM
dst: R
Divide
dst (low) - dst DIV src
dst (high) - dst REM src
Divide Unsigned
dst (low) - dst DIV src
dst (high) - dst REM src
Extend Sign
dst -
dst: R,IR,EAM
n: 1M
sign_extend (dst (low))
Increment
dst - dsl + n
(n
1.. 16)
=
dst: IR,EAM
n: 1M
Increment Interlocked
dst - dst + n
(n
1..16)
=
704
INDEX
INDEXL
dst,sub,src
MULT
MULTL
dst,src
MULT,U
MULTUL
dst,src
NEG
NEGB
NEGL
dst
SBC
SBCB
SBCL
dst,src
SUB
SUBB
SUBL
dst,src
TESTA
TESTAB
TESTAL
dst
dst: R
sub: R
src: IM,IR,EAM
dst: R
src: R,IM,IR,EAM
dst: R
src: R,IM,IR,EAM
dst: R,IR,EAM .
Index
calculate array index:
check, scale, and accumulate
Multiply
dst -
. Multiply Unsigned
dst -
dst (low) * src
Negate
dst -
dst: R
src: R
dst (low) * src
dst
Subtract with Carry
dst -
dst - src - C
dst: R
src: R,IM,IR,EAM
Subtract
dst: R,IR,EAM
Test Arithmetic
dst -
dst -
dst ~ src
0
Logical
Mnemonic
Operands
Addressing Modes
Operation
AND
ANDB
ANDl
dst,sre
dst: R.
sre: R,IM,IR,EAM
And
COM
COMB
COMl
dst
dst: R,IR,EAM
Complement
OR
ORB
ORl
dst,sre
TCC
TCCB
TCCl
ee,dst
TEST
TESTB
TESTl
dst
XOR
XORB
XORl
dst,sre
dst -
dst dst: R
sre: R.,IM,IR,EAM
dst: R
dst: R,IR,EAM
dst AND sre
NOT dst
Or
dst -
dst OR sre
Test Condition Code
N
if ee then
dst - dst OR 1
...0
Test
8
~
§
-a
dst OR 0
dst: R
sre: R,IM,IR,EAM
CI
Xor
dst -
dst XOR sre
Program Control
Mnemonic
Operands
Addressing Modes
BRKPT
Operation
Breakpoint
(breakpoint trap)
Push PS onto System Stack
Push instruction
PS - Breakpoint PS
CAll
dst
dst: IR,EAM
Call
Autodeerement SP
@SP - PC
PC - Address (dst)
CAlR
dst
dst: RA
Call Relative
Autodeerement SP
@SP - PC
PC - Address (dst)
DJNZ
DBJNZ
DlJNZ
ent,dst
ent: R
dst: RA
Decrement and Jump If Not Zero
ent - ent - 1
if ent
0 then
PC - Address (dst)
*
705
Program
Con~rol
(Continued)
Mnemonic
Operands
Addressing Modes
Operation
ENTER
mask,siz
mask:'IM
siz: 1M
Enter Procedure
EXIT
Push registers (mask)
Push FP
Push mask
Push 0 (exception handler)
FP - SP + siz
update integer overflow mask
Exit Procedure
SP - FP
Pope'xception handler
POpl mask
Pop FP
Pop registers (mask)
restore integer overflow mask
JP
cC,dst
dst: IR,EAM
Jump
if cc then
PC - Address (dst)
JR
cC,dst
dst: RA
Jump Relative
if cc'then
PC - Address (dst)
RET
Return
cc
if cc then
PC - @SP
Autoincrement SP
SC
src
src: 1M
System Call
(system call trap)
Push PS onto System Stack
Push instruction
PS - System Call PS
TRAP
cC,src,
src: 1M
Trap Conditional
if cc then
(condition trap)
Push PS onto System Stack
Push instruction
PS - Conditional Trap PS
706,
Bit Manipulation
Mnemonic
Operands
Addressing Modes
Operation
BIT
BITB
BITL
dst,src
dst: R,IR,EAM
src: 1M
or
dst: R
src: R
Test Bit
RES
RESB
RESL
dst,src
dst: R,IR,EAM
src: 1M
or
dst: R
src: R
Reset Bit
SET
SETB
SETL
dst,src
Z -
NOT dst (src)
dst (src) -
0
dst: R,IR,EAM
src: 1M
or
dst: R
src: R
Set Bit
dst: R,IR,EAM
Test and Set
dst (src) -
N
Q
1
0
g
.
0
fI-'
TSET
TSETB
TSETL
dst
a
s - dst (MSB)
dst - -1
Rotate and Shift
Mnemonic
Operands
Addressing Modes
Operation
RL
RLB
RLL
dst,n
dst: R
n: 1M
Rotate Left
RLC
RLCB
RLCL
dst,n
RLDB
Iink,dst
RR
RRB
RRL
dst,n
RRC
RRCB
RRCL
dst,n
dst: R
n: 1M
link: R
dst: R
dst: R
n: 1M
dst: R
n: 1M
dst - dst rotate left
n.bits
(n = 1 or 2)
Rotate Left through Carry
dst,C - dst,C rotate left
n bits
(n = 1 or 2)
Rotate Left Digit
dst,link(0:3) - dst,link (0:3)
rotate left 1 digit
Rotate Right
dst - dst rotate right
n bits
(n = 1 or 2)
Rotate Right through Carry
dst,C - dst,C rotate right
n bits
(n = 1 or 2)
707
r
Roiate and Shift (Continued)
Mnemonic
Operands
Addressing Modes
RRDB
link,dst
link: R
dst: R
SOA
SDAB
SDAL
dst,src
SOL
SDLB
SDLL
dst,src
SLA
SLAB
SLAL
dst,n
SLL
SLLB
SLLL
dst,n
SRA
SRAB
SRAL
dst,n
SRL
SRLB
SRLL
dst,n
dst: R
src: R
. Operation
Rotate Right Digit
dst,link (0:3) - dst,link (0:3)
rotate right 1 digit
Shift Dynamic Arithmetic
dst - dst arithmetic shift
src bits·
dst: R
src: R
Shift Dynamic Logical
dst: R
n: 1M
Shift Left Arithmetic
dst: R
n: 1M
Shift Left Logical
dst: R
n: 1M
Shift Right Arithmetic
dst: R
n: 1M
Shift Right Logical
dst - dst logical shift
src bits
dst - dst arithmetic shift
left n bits
dst - dst logical shift
left n bits
dst - dst arithmetic shift
right n bits
dst - dst logical shift .
right n bits
Block Transfer and String Manipulation
Mnemonic
Operands
Addressing Modes
Operation
CPO
CPOB
CPDL
dst,src,
cnt,cc
dst: R
src: IR
cnt: R
Compare and Decrement
CPOR
CPDRB
CPDRL
dst,src,
cnt,cc
dst: R
src: IR
cnt: R
dst - src
Autodecrement src address
cnt - cnt - 1
Compare, Decrement, and Repeat
Repeat
dst - scr
Autodecrement src address
cnt - cnt - 1
Until cc is true or cnt 0
=
CPI
CPIB
CPIL
708
dst,src,
cnt,cc
dst: RO
src: IR
cnt: R
Compare and Increment
dst - src
Autoincrement src address
cnt - cnt - 1
Blocle Transfer and String Manipulation (Continued)
Mnemonic
Oporands
Addressing Modes
Operation
CPIR
CPIRB
CPIRL
dst,sre,
ent,ee
dst: R
sre: IR
ent: R
Compare, Increment, and Repeat
CPSD
CPSDB
CPSDL
dst,sre,
ent,ee
dst: IR
sre: IR
ent: R
CPSDR
CPSDRB
CPSDRL
dst,sre,
ent,ee
dst: IR
sre: IR
ent: R
CPSI
CPSIB
CPSIL
dst,sre,
ent,ee
dst: IR
sre: SR
ent: R
CPSIR
CPSIRS
CPSIRL
dst,sre,
ent,ee
dst: IR
sre: IR
ent: R
LDD
LDDB
LDDL
dst,sre,ent .
dst: IR
sre: IR
ent: R
LDDR
LDDRB
LDDRL
dst,sre,ent
LDI
LOIB
LOlL
dst,sre,ent
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
Repeat
dst - src
Autoinerement sre address
ent - ent - 1
Unit ee is true or ent =' 0
Compare String and Decrement
dst - sre
Autodeerement dst and sre addresses
ent - ent - 1
N
Compare String, Decrement, Repeat
J
Repeat
dst - src
Autodeerement dst and sre
addresses
ent - ent - 1
!Jntil ee is true or ent=O
0
8
":=
Compare String and Increment
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1
Compare String, Increment, Repeat
Repeat
dst - sre
Autoinerement dst and sre
addresses
ent - ent - 1
Until ee is true or ent = 0
Load and Decrement
dst - sre
Autodeerement dst and sre addresses
ent - ent - 1
Load, Decrement, and Repeat
Repeat
dst - sre
Autodeerement dst and sre
addresses
ent - ent - 1
Unitl ent= 0
Load and Increment
dst - sre
Autoinerement dst and sre addresses
ent - ent - 1
709
r
· Block Transfer and String Manipulation (Continued)
Mnemonic
Operands
Addressing Modes
Operation
LDIR
LDIRB
LDIRL
dst,src,cnt
d~t: IR
src: IR
cnt: R
Load, Increment, and Repeat
TRDB
dst,src,cnt
TRDRB
TRIB
TRIRB
TRTDB
TRTDRB
TRTIB
710
dst: IR
src: IR
cnt: R
Repeat
dst - src
Autoincrement dst and src
addresses
cnt - cnt - 1
Until cnt= 0
Translate and Decrement
dst - src [dst]
Autodecrement dst address
cnt - cnt - 1
dst: IR
src: IR
cnt: R
Translate, Decrement, and Repeat
dst: IR
src: IR
cnt: R
Translate and Increment
dst: IR
src: IR
cnt: R
Translate, Increment, and Repeat
src1,src2,
cnt
src1: IR
src2: IR
cnt: R
Translate, Test, and Decrement
src1,src2,
cnt
src1: IR
src2: IR
cnt: R
Translate, Test, Decrement, Repeat
src1,src2,
cnt
src1 :IR
src2: IR
cnt: R
Translate, Test, and Increment
dst,src,cnt
dst,src,cnt
dst,src,cnt
Repeat
dst - src [dst]
Autodecrement dst address
cnt - cnt - 1
Until cnt= 0
dst - src [dst]
Autoincrement dst address
cnt - cnt - 1
Repeat
dst - src [dst]
Autoincrement dst address
cnt - cnt - 1
Until'cnt = 0
RH 1 - src2 [src1]
Autodecrement src1 address
cnt - cnt - 1
Repeat
RH1 - src2 [src1]
Autodecrement src1 address
cnt - cnt - 1
Until RH1 *0 or cnt=O
RH 1 - src2 [src1]
Autoincrement src1 address
cnt - cnt - 1
Blo~f(
Transfer and String Manipulation (Con~inued)
Mnemonic
Operands
Addressing Modes
Operation
TRTIRB
sre1,sre2,
ent
sre1: IR
sre2: IR
ent: R
Translate, Test, Increment, Repeat
Mnemonic
Operands
Addressing Modes
Operation
IN*
INB*
INl*
dst,sre
dst: R
sre: IR,DA
Input
IND*
INDB*
INDl*
dst,sre,ent
INDR*
INDRB*
INDRl*
dst,sre,ent
INI*
INIB*
INll*
dst,sre,ent
INIR*
INIRB*
INIRl*
dst,sre,ent
OTDR*
OTDRB*
OTDRl*
dst,sre,ent
OTIR*
OTIRB*
OTIRl *
dst,sre,ent
Repeat
RH1 - 'sre2 [sre1]
Autoinerement sre1 .address
ent - ent - 1
Until RH1 *0 or ent=O
Input/Output
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
dst: IR
sre: IR
ent: R
dst -
00
..eo
Q
~
C:)
t;)
sre
6
Input and Decrement
t{J
=
dst - sre
Autodeerement dst address
ent - ent - 1
Input, Decrement, and Repeat
Repeat
dst - sre
Autodeerement dst address
ent - ent'- 1
Until ent=O
Input and Increment
dst - sre
Autoinerement dst address
ent - ent - 1
Input, Increment, and Repeat
Repeat
dst - sre
Autoinerement dst address
ent - ent - 1
Until ent =0
Output, Decrement, and R'epeat
Repeat
dst - sre
Autodeerement sre address
ent - ent - 1
Until ent=O
Output, Increment, and Repeat
Repeat
dst - sre
Autoinerement sre address
ent - ent - 1
Until ent= 0
71,1
Input/Output (Continued)
Mnemonic
Operands
Addressing Modes
Operation
OUT*
OUTB*
OUTL*
dst,src
dst: IR,DA
src: R
Output
OUTD*
OUTDB*
OUTDL*
dst,src,cnt
OUTI*
OUTIB*
OUTIL*
dst,src,cnt
dst: IR
src: IR
cnt: R
pst: IR
src: IR
cnt: R
dst -
src
Output and Decrement
dst - src
Autodecrement src address
cnt - cnt - 1
Output and Increment
dst - src
Autoincrement src address
cnt - cnt - 1
CPU Control
Mnemonic
Operands
Addressing Modes
Operation
COMFLG
flags
flags: 1M
Complement Flag
DI*
ints
ints: 1M
Disable Interrupt
EI*
ints
ints: 1M
Enable Interrupt
HALT*
Halt
IRET*
Interrupt Return
PS - @SP
Autoincrement SP
LDCTL*
LDCTLB
LDCTLL*
LDND*
LDNDB*
LDNDL*
'Privileged instruction
712
dst,src
dst,src
dst,src
dst,src
dst: CTLR
src: R
or
dst: R
dst: FLGR
src: R
or
dst: R
src: FLGR
dst: CTLRL
src: R
or
dst: R
src: CTLRL
dst: R
src: IR,EAM
or
dst: IR,EAM
src: R
Load Control Register
dst -
src
Load Flag Byte Register
dst -
src
Load Control Register Long
dst -
src
Load Normal Data Address Space
dst -
src
CPU Con~rol (Con~inued)
Mnemonic
Operands
Addressing Modes
Operation
LDNI*
LONIS*
LONIL*
dst,src
dst: R
src: IR,EAM
Load Normal Instruction Address
Space
or
dst: IR,EAM
src: R
dst -
LOPS*
src
src: IR,EAM
Load Program Status
PS -
LONO*
LONI*
LOSO*
LOSI*
dst,src
dst: R
src: IR,EAM
src
src
Load Physical Address
dst -
PhysicalJddress (src)
E.\1
CO
e
NOP
No Operation
PCACHE*
Purge Cache
PTLB*
Purge TLB
PTLBENO*
PTLBENI
PTLBESO*
PTLBESI*
src
src: IR,EAM
~
6
£U
Cl
Purge TLB Entry
Purge TLB Normal
PTLBN*
RESFLG
flag
flag: 1M
Reset Flag
SETFLG
flag
flag: 1M
Set Flag
Mnemonic
Operands
Addressing Modes
Operation
EXTR
dst,src,
pos,siz
dst: R
src: R,IR,EAM
pos: IM,R
siz: IM,R
Extract Field
dst,src,
pos,siz
dst: R
src: R,IR,EAM
pos: IM,R
siz: IM,R
dst,src,
pos,siz
dst: R,IR,EAM
src: R
pos: IM,R
siz: IM,R
Bit Field
EXTRU
INSRT
dst -
src (pos,siz)
Extract Unsigned Field
dst -
src (pos,siz)
Insert Field
dst -
(pos,siz) -
src
• Privileged instruction.
713
EXTENDED INSTRUCTIONS
The Z80,OOO CPU .supports extended instructions
through the Zilog Extended Processing Architecture
(EPA). The EPA facility allows the operations defined in
the Z80,OOO architecture to be extended' by software or
hardware. In particular, floating-point operations are
supported by the Z8070 Arithmetic Processing Unit
(APU) or by a software package that emulates the APU.
Up to four Extended Processing Units (EPUs) can be included in a Z80,OOO CPU system. The CPU and EPU
cooperate in execution· of EPA instructions. When the
CPU encounters an EPA instruction, the instruction is
transmitted across the external bus to the appropriate
EPU. The CPU then performs transactions on the external bus to transfer data between the EPU and memory or
the EPU and CPU. Transfers between the EPU and CPU
can involve the CPU general-purpose registers or FCW
flag byte. EPU internal operations do not require any
data transfers. After the data transfers for the EPU instruction are completed, the CPU can continue processing while the EPU performs the operation. While the EPU
is processing an instruction, it can drive the EPUBSY
signal to stop the CPU.
The data processing operations performed by the EPU
are transparent to the CPU. The EPU can execute
floating point operations, decimal arithmetic, specialized
operating system functions, signal processing operations, or any other that the system designer chooses. For
this reason, no mnemonic is listed for the extended instructions, as the mnemonic will depend on the type of
EPU. EPUs designed to speed execution of special purpose operations can provide significant performance improvements. The operation of the EPU can be overlapped with operation of the CPU and other EPUs.
The EPA bit in the Flag and Control Word register indicates whether an EPU is present. If no EPU is present,
the CPU traps EPA instructions for software simulation.
Thus, the EPA facility can be used even with no external
support circuitry. This allows software compatibility between systems, whether or not an EPU is present. The
system designer can choose to include an EPU in highperformance systems but not in low-cost systems, and
software can be developed using the EPA instructions
before an EPU is available.
Extended Instructions
Operation
Operands
Addressing Modes
Load EPU from memory
dst - src
(n bytes or words)
dst,src, n
dst: EPU
src: IM,IR,EAM*
Load memory from EPU
dst - src
(n bytes or words)
dst,src,n
Load EPU from CPU
dst - src
(n words or longwords)
dst,src, n
Load CPU from EPU
dst - src
(n words or longwords)
dst,src,n
Load EPU from Flags
dst - src
dst,src
dst: EPU
src: FLGR
Load Flags from EPU
dst - src
dst,src
dst: FLGR
src: EPU
EPU Internal Operation
·Compact mode allows BX with no displacement for EAM.
714
n: 1M
dst: IR,EAM*
src: EPU
n: 1M
dst: EPU
src: R
n: 1M
dst: R
src: EPU
n: 1M
CACHE
The CPU implements a Cache mechanism to keep onchip copies of the most recently referenced memory
locations (Figure 10). The CPU examines the cache on
memory fetches to determine if the addressed data are
located in the cache. If the information is in the cache (a
hit), then the CPU fetches from the cache, and no transaction is necessary on the external interface. If the information is not in the cache (a miss), then the CPU performs a Memory Read transaction to fetch the missing
information.
The cache stores data in blocks of 16 bytes. Each data
word in the cache has an associated validity bit to indicate whether or not the word is a valid copy of the corresponding main memory location. The cache contains
16 blocks, providing 256 bytes of storage.
The cache is fully associative, so that a block currently
needed and missing in the cache can replace any block
MATCH
ADDRESS TAG
ASSOCIATIVE
MEMORY
(16 x 28)
r----..,.-----.
LINES
J-=o1=r6- , -. . . .
CACHE DATA VALIDITY
MEMORY
BITS
(16 x 128)
(16 x 8)
BLOCK
HIT
32
PHYSICAL
ADDRESS
DATA
CACHE
HIT
Figure 10. Cache Organization
in the cache. Moreover, when a block miss occurs, the
least recently used (LRU) block in the cache is replaced.
When a cache miss occurs on an instruction fetch, the
CPU fetches the missing instruction from memory and
prefetches the following words in the block using a Burst
transaction. When a cache miss occurs on an operand
fetch, the CPU fetches the missing data from memory.
(The CPU uses Burst transactions only for fetching
operands when more than one data transfer is
necessary: longword operands on a 16-bit bus, unaligned operands, string instructions, Load Multiple instructions, and loading Program Status.)
On store references, the data is written to memory (store
through), and if the reference hits in the cache, the data
is also written to the cache. If the store reference misses
in the cache, the cache is unaffected.
Software has some control ,over the cache. The cache
can be selectively enabled for instruction and data
references by bits CI and CD in the SCCL control
register. The memory management mechanism allows
cacheing to be inhibited for individual pages. The
Pcache instruction can be used to invalidate all information in the cache.
The cache has an option, controlled by bit CR in SCCL, to
inhibit block replacement on a miss. This option can be
used to lock fixed locations into the cache for fast, onchip access. To do this, the cache is first enabled for
block replacement of data references only. Selected
blocks are read into the cache. The block replacement
algorithm is then disabled, while the cache is enabled for
instruction and data references.
PIN DESCRIPTIONS
The CPU .has 58 signal lines. Pin functions are'shown in
Figure 11.
ADo-AD31. Address/Data (Bidirectional, active High,
3-state). These 32 lines are time-multiplexed to transfer
address and data. At the beginning of each transaction
the lines are driven with the 32-bit address. After the address has been driven, the lines are used to transfer one
or more bytes, words, or longwords of data.
AS. Address Strobe (Output, active Low, 3-state). The rising edge of AS indicates the beginning of a transaction
and shows that the address, STo-ST3, R/W, BUW, BwiC,
NIS, and BRST are valid.
2071.()10
BUSREQ. Bus Request (Input, active LOW). A Low on this
line indicates that a bus requestor has obtained or is trying to obtain control of the local bus. .
BUSACK. Bus Acknowledge (Output, active LOW). A Low
on this line indicates that the CPU has relinquished control of the local bus in response to a bus request.
BRST. Burst (Output, active Low, 3-state). A Low on this
line indicates that the CPU is performing a burst transfer;
i.e, multiple Data Strobes following a single Address
Strobe.
715
BRSTA. Burst Acknowledge (Input, active Low). A Low
on this line indicates that the responding device can support burst transfers.
BUW; ,BW/L Byte, Longword/Word; Byte,
Word/
Longword (Output, 3-state). These two lines specify the
data transfer size.
NVI. Non-Vectored Interrupt (Input, active Low). A Low
on this line requests a non-vectored interrupt.
Nis.
Normal/System Mode (Output, Low = System
Mode, 3-state). This line indicates whether the CPU is in
Normal or System mode.
OE. Output Enable (Output, active Low, 3-state). A Low
on this line can be used. to enable buffers on the AD lines
to drive away from the CPU.
BuW
BW/L
Size
High
Low
High
Low
High
High
Low
Low
Byte
Word
Longword
Reserved
ClK. Clock (Input). This line is the clock used to
generate all CPU timing.
RIW. Read/Write (Output, Low = 'Write, 3-state). This
signal indicates the direction of data transfer.
RESET. Reset (Input, active Low). A Low on this line
OS. Data Strobe (Output, active Low, 3-state). DSis used
, for timing data transfers.
EPUBSY. EPU Busy (Input, active Low). A Low on this
line indicates that an EPU is busy. This line is used to
synchronize the operation of the CPU with an EPU during
execution of an EPA instruction.
resets the CPU.
RSPO-RSP1. Response (Input). These lines encode the
response to transactions initiated by the CPU. Note that
RSPo and RSP1 can be connected together for ZeBUS
WAIT timing.
GREQ. Global Request (Output, active Low, 3-state). A
Low on this line indicates the CPU has obtained or is trying to obtain control of a global bus.
GACK. Global Acknowledge (Input, active Low). A Low
on this line indicates the CPU has been granted control
of a global bus.
'
IE. Input Enable (Output, active Low, 3-state). A Low on
this line can be used to enable buffers on the AD lines to
drive toward the CPU.
'
RSPo
RSP1
Response
High
Low
High
Low
High
High
Low
Low
Ready
Bus Error
Bus Retry'
Wait
STO-ST3' Status (Output, active High, 3-state). These
lines specify the kind of transaction occurring on the
bus. (See Table 4.)
NMI. Non-Maskable Interrupt (Input, Edge activated). A
VI. Vectored Interrupt (Input, active Low). A Low on this
line requests a vectored interrupt.
High-to-Low transition on this line' requests a nonmaskable interrupt.
RESET
AD
EXTENDED
PROCESSOR
CONTROL
ADDRESSIDATA
BUS
AS
EPii'iiSv
-
4-
os
RiW
INTERRUPT
REQUESTS
l
BuW
-NM'
~
.
BW/[
NVI
BUS STATUS
AND TIMING
STATUS
LOCAL BUS {
CONTROL
GLOBAL BUS
CONTROL
_
BUFFER
} CONTROL
GREQ
GACK
BURST TRANSFER
} CONTROL
ClK
+5 V
GND
CLOCK
,Figure 11. Pin Functions
716
2071-011
MULTIPROCESSOR CONFIGURATIONS
The CPU provides support for interconnection in four
types of multiprocessor configurations (Figure 12):
coprocessor, slave processor, tightly-coupled multiple
CPUs, and loosely-coupled multiple CPUs.
Coprocessors, such as the Z8070 Arithmetic Processing
Unit, work synchronously with the CPU to execute a
single instruction stream using the Extended Processing
Architecture facility. The signal EPUBSY is dedicated for
connection with qoprocessors.
Slave processors, such as the Z8016 DMA Transfer Controller, perform dedicated functions asynchronously to
the CPU. The CPU and slave processor share a local
bus, of which the CPU is the default master, using the
CPU's BUSREQ and BUSACK lines.
Tightly-coupled, multiple CPUs execute independent instruction streams and generally communicate through'
shared memory located on a common (global) bus using
the CPU's GREQ and GACK lines. Each CPU .!s default
master of its local bus, but the global bus master is
chosen by an external arbiter. The CPU also provides
status information about interlocked memory references
(for Test and Set, Increment Interlocked, and Decrement
Interlocked instructions), which can be used with multiported memories.
Loosely-coupled, multiple CPUs generally communicate
through a muftiple·ported peripheral, such as the Z8038
FlO. The Z80,000 CPU's 110 and interrupt facilities can
support loosely·coupled multiprocessing.
LOCAL BUS
(D) LOOSELY·COUPLED
MULTIPLE CPU
(C) TIGHTLY·COUPLED MULTIPLE CPU
(8) SLAVE PROCESSOR
(A) COPROCESSOR
Figure 12. Multiprocessor Configurations
HARDWARE INTERFACE CONTROL
REGISTER
The Hardware Interface Control register (HICR) specifies
certain characteristics of the hardware configuration
surrounding the CPU, including bus speed, memory data
path width, and number of automatic Wait states. The
physical memory address space is divided into two sections, Mo and M1, selected by bit 30 of the address. A
typical system would locate slow, 16-bit wide bootstrap
ROM in Mo and faster 32-bit wide dynamic RAM in M1.
The physical 110 address space is similarly divided into
two sections, 1100 and 1101, selected by bit 30 of the address.
Fields in H1CR specify the
characteristics (see Figure 3):
2071'()12
following
interface
Bus speed (S)- The bus clock frequency is either 112 or
114 the clock frequency.
Memory data path (Mo.DP, M1.DPJ- The data path width
for Mo and M1 are each specified as 16 or 32 bits.
Automatic Wait states (Mo. W, M1. W, 1/00. W, 1/01. W,
lACK. W1, lACK. W2)- The number of Wait states
automatically inserted by the CPU for references to Mo,
Ml, 1100, 1101, and Interrupt Acknowledge, are separate- ,
Iy specified.
Global bus protocol control (LAO, GE)-The CPU can access a global bus (a bus shared with other CPUs). On
references to the global bus, the CPU must use a re-
717
quest/acknowledge handshake with an external arbiter.
The GE field enables the use of the global bus; the LAD
field selects the portion of the address space used for
references to the global bus.
is'useful for refreshing pseudostatic RAMS.
EPU overlap (EPUO)-This bit, along with another bit in
an EPU control register, controls the degree of overlap
for CPU and EPU operations. The degree qf overlap can
be limited to simplify debugging and recovery from exceptions, although to do so reduces overall execution
speed.
Minimum Address Strobe rate (MASR)-This optional
feature ensures that an Address Strobe will be
generated at least once every 16 bus clock cycles. This
CPU TIMING
The CPU performs transactions on the external interface
to transfer data for fetching instructions, fetching and
storing operands, processing exceptions, and performing memory management. In addition, the CPU performs
Internal Operation and Halt transactions, which do not
transfer data. Each transaction occurs during a sequence of bus clock cycles, named T1, T2, etc.
and output delays are specified with respect to a rising
edge of ClK. When CPU output transitions "occu"r on different clock edges, the time between the transitions is
specified in terms of a constant delay and a variable
number of ClK cycles. The number of ClK" cycles
depends on the bus timing scale factor, type of" transaction, and number of Wait states.
The CPU has a single clock line, ClK, used to generate
all timing. Internally, the CPU derives another clock for
bus timing by dividing ClK by 2 or 4. The scale factor for
bus timing (2 ot 4) is selected at Reset. In the AC timing
characteristics for the CPU, input setup and hold times
In the logical timing diagrams that follow, the signal transitions on the bus are shown in relation to the bus clock,
BClK. The beginning of a transaction, signified by a failing edge of AS, always occurs on a rising edge of BClK.
The BClK signal is derived internally to the CPU as
CLK
BCLK
~
AD~
AS
~
}-------<
ADDRESS
(A) BCLK = CLK
-7
DATAIN}--"
2
CLK
BLCK
AD
~
J~
___
A_DD_R_ES_S_ _ _
~)- -
-
-
-
-
-
-
-
-
-
-
-
-('\",_ _
DA_TA_IN_-.Jr -
-
-
-
-
~
\~--------------~I
(B) BCLK
= CLK +
4 '
-Figure 13. Memory Read Timing for Different Bus Scale Factors
718
2071-013
described above, but is not available on the pins. BClK
can also be derived externally to the CPU by dividing
ClK by the selected bus timing. scale factor. (The Reset
section discusses synchronization of the internal and external bus clocks). The timing diagrams in Figure 13
show example memory read transactions using. the different scale factors.
In the description of bus transactions that follow, the
term "asserted" means an active signal and "negated"
means an inactive signal. A signal is either active when
High or when low, as specified in the pin functions.
BUS TRANSACTIONS
All bus transactions begin with Address Strobe (AS)
asserted and then negated. On the rising edge of AS the
lines for status (STo-ST3), Read/Write (R/W), data
transfer size (BW/L, BUW), and Normal/System (NiS) are
valid. The status lines indicate the type of transaction being initiated (Table 4). The R/W line indicates the direction of data transfer. The data transfer size indicates
whether a byte, word, or longword of data is being
transferred. The N/S line indicates the CPU's operating
mode. The following sections describe timing for the different transactions.
Tablo 4. Status Codes
data, and thus do not assert DS.) For Write operations
(R/W = low) the CPU asserts DS when valid data is on
the AD lines. For Reaq operations (R/W = High) the CPU
makes the AD lines 3-state before asserting DS, so the
addressed device can put its data on the bus. The CPU
samples the data in the middle of a bus cycle, while
negating DS.
The AD lines can be used to transfer bytes, words, or
longwords. For Read transactions, the three cases are
handled as follows:
m Byte transfers use ADo-AD7; ADa-AD31 are ignored.
m Word transfers use ADo-AD15; AD16-AD31 are
ST3-STo
Definition
0000
0001
0010
a 01 1
0100
1 01
01 1 a
01 1 1
1000
100 1
1010
1 01 1
1 100
1 1 01
111
1111
internal operation
CPU-EPU (data)
a
a
1/0
halt
CPU-EPU (instruction)
N M I acknowledge
NVI acknowledge
Vi acknowledge
cacheable CPU-memory (data)
non·cacheable CPU-memory (data)
cacheable EPU-memory
non-cacheable EPU-memory
cacheable CPU-memory (instruction)
non-cacheable CPU-memory (instruction)
reserved
interlocked CPU-memory (data)
On the rising edge of AS, the address on the AD lines is
also valid. Addresses are not required and therefore are
undefined for Internal Operation, Halt, Interrupt
Acknowledge, and CPU-EPU data transactions.
The CPU uses Data Strobe (DS) to time the data transfer.
(Internal Operation and Halt transactions do not transfer
ignored.
CI
longword transfers use ADo-AD31.
For Write transactions, the three cases are handled as
follows:
II
Byte transfers replicate the data on ADo-AD7,
ADa-AD15, AD16-AD23, and AD24-AD31.
•
Word transfers replicate the data on ADo-AD15 and
AD16-AD31·
1'1
longword transfers use ADo-AD31.
The signals Input Enable (iE) and Output Enable (OE) can
be used to enable buffers on the bidirectional AD lines.
IE is asserted when the buffers drive toward the CPU; OE .
is asserted when the buffers drive away from the CPU.
Whenever the direction for the AD lines changes, neither
iE nor OE is asserted for at least one ClK cycle.
To transfer more than one data item, the CPU can perform Burst transactions. The data items are transferred
in the same direction, and must be equal in size. Data
Strobe is used to time each transfer. The CPU asserts
Burst (BRST) to indicate a burst transfer. The responding
device asserts Burst Acknowledge (BRSTA) if it is
capable of supporting burst transfers. If BRSTA is not
asserted, the CPU transfers only a single data item.
719
RESPONSE
Any time data is transferred, the responding device
returns a code on the Response lines (RSPo-RSP1) to indicate Ready, Wait, Bus Error, or Bus Retry. The
response is sampled at a time specific to each type of
transaction, generally before the AD lines are sampled
or OS is negated.
Ready indicates the completion of a successful transfer.
Wait indicates that the responding device· needs more
time to complete the transaction. The CPU waits one bus
cycle before sampling the response again to accommodate slow memory or peripherals.
Bus Error indicates that a fatal error has occurred during
the transaction; for example, bus timeout for a nonexistent device. Bus Error is treated as an exception by the
CPU.
Bus Retry indicates that the transaction should be tried
again; for example, a transient parity error is detected.
The CPU tries the transaction again.
The CPU can insert Wait states automatically under control of several fields in the Hardware Interface Control
Register. If an automatic Wait state is programmed for a
bus cycle, the CPU ignores the response and Wait is
assumed. Thus, Wait states can be inserted automatically by the CPU or upon request of the responding
device.
It must be emphasized that the RSPo-RSP 1 lines are synchronous. Thus, they must meet the specified setup and
hold times for correct operation. A simple system using
only Z~BUS WAIT can be implemented by connecting
WAIT to RSPo and RSP1.
CPU-MEMORY TRANSACTIONS
The CPU uses status 1000, 1001, .1100, 1101, or 1111 to
read from and write to memory. The transactions involve
a single data transfer or multiple, burst data transfers.
i
BCLK
Single Memory Read
Figure 14 shows timing for a single memory read transaction with no Wait states. AS is asserted during the first
half of T1. The rising edge of AS indicates that the address on AD and control signals SIo-ST3, R/W, BW/L,
BLlW, and N/S are valid. The control signals remain valid
for the duration of the transaction. BRST is negated during the transaction because only a single data item is being transferred. At the beginning of T2 the CPU stops
driving the address, asserts OS, and prepares to receive
data from memory. In the middle of T2 RSPo-RSP1 are
sampled Ready, the input data is latched, and OS is
negated. The signal DE is asserted during T1; however,
for this two-cycle read transaction, IE is not asserted.
The CPU can insert Wait states in the middle of T2 if
RSPo-RSP1 are sampled Wait or if automatic Wait states
are programmed in the appropriate field of HICR. The
duration of a Wait state is one BCLK cycle.
The timing for a single memory Read transaction with
one Wait state is shown in Figure 15. This is not a true
Wait state because IE is asserted in the middle of T2 and
continues until the middle of T3. For memory Read transactions longer than two bus cycles, either because of
Wait states or Burst transfers, IE is asserted from the
middle of T2 until the end of data transfer. The signals OE
and IE can be used to control buffers on the AD lines.
For memory Read transactions, the data transfer size is
equal to the data path width specified in H ICA. The
memory should transfer the aligned longword addressed
by AD2-AD31 (ignoring ADo-AD1) for a 32-bit data path
or the aligned word addressed by AD1-AD31 (ignoring
ADo) for a 16-bit data path. The CPU selects the required
bytes from the transferred word or longword.
720
AD
T1
--.J
i - ·-1
T2
I
>- -®- -C
1
=x
ADDRESS
1*
I
R/W.-J
T
T
S o-S 3
BW/i:, BLlW
HIS
=x
._ _ _ _ _ _ _ _ _ __
~.
)(
\
*RSPo-RSPl and data sampled.
Figure 14. Single Memory Read Timing
2071-014
r-Tl~I~T2~I-T31
DCLK
AD
STO-ST3
HIS
BwiL, BL/\!
.-J
J
ADDRESS
=x
.~___________________________________
*RSPo-RSPl and data sampled.
Figure 15. Single Memory Read Timing (1 Wait State)
2071-015 00-2071-01
721
Single Memory Write
A single memory Write transaction (Figure 16) begins
with AS to indicate that address and control signals are
valid. At the beginning of T2, the CPU stops driving the
address and starts driving the data. In the middle of T2,
OS is asserted. The CPU negates OS in the middle of T3.
OEis asserted beginning at T1 and continues for the
duration of the transaction. The CPU samples
RSPo-RSP1 in the middle of T3.
For memory Write transactions, the data transfer size is
less than or equal to the data path width specified in
H ICA. Bytes and words can be written to a 16-bit
memory; bytes, words, and longwords can be written to
a 32-bit memory. The CPU writes bytes to any address,
but words and longwords are always written to an
aligned address (i.e., words are always written to an
even address and longwords are always written to an ad-
dress that is a multiple of four). When a program writes a
word or longword to an unaligned address, the CPU performs two or more write transactions to aligned addresses. For example, if the program writes a word to an
odd address, the CPU first writes the more Significant
byte to the odd address, then it writes the less Significant
byte to the successive even address.
Single memory read and write timing differ slightly from
loBUS specificatiOns. The minimum Read transaction is
two bus cycles, and the slave response is sampled at the
end of the data transfer. For the loBUS, the minimum
Read transaction is three cycles, and the slave response
is sampled one cycle before the end of the data transfer.
For strict loBUS compatibility, it is possible to program
one automatic Wait state for memory read and to delay
the slave response with an external flipflop.
I~T1~IT2~IT31
BCLK~
AD
I
J
ADDRESS
I
I
I
I
1*
X'-____
,X
D_AT_A_O_UT_ _ _ _
\.
\,------,1
IE
)L
STC-ST:OLl\!
tllS - - - -V
"_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.
ow/i:",
RiW~
;=
• RSPo- RSP1 sampled.
Figure 16_ Single Memory Write Timing
722
2071'()16
Burst Memory Transactiomj
Burst memory transactions use multiple Oata Strobes
following a single Address Strobe to transfer data at consecutive memory addresses. The signals BRST and
BRSTA control the Burst transaction. The CPU uses
Burst transactions to prefetch a cache block on an instruction fetch cache miss. The CPU also uses Burst·
transactions to fetch or store operands when more than
one transfer is necessary, as with unaligned operands,
string instructions, Load Multiple instructions, and
loading of program status.
If the memory does not support Burst transfers, the
Burst transfer protocol described below (Figure 17)
allows BRSTA to be tied High. The CPU then separates
the Burst transaction into a sequence of single transfers.
At the beginning of a Burst transaction, the CPU asserts
BRST along with other control signals. When the CPU
continues to assert BRST at 1he falling edge of OS, this
indicates to memory that the CPU· can support another
data transfer following the one in process. When the
CPU negates BRST before the falling edge of OS, this indicates to memory that the current transfer is the last in
the transaction.
When BRSTA is asserted at the time the RSPo-RSP1
lines are sampled Ready, this indicates to the CPU that
memory can support another data transfer following the
one in process. When BRSTA is negated at the time the
RSPo-RSP1 lines are sampled Ready, this indicates to
the CPU that the current data transfer is the last in the
transaction.
The Burst transaction can be terminated by either the
CPU or memory. If memory terminates the transfer by
negating BRSTA, the CPU responds by negating BRST
when OS is negated. (See the e~ample for Burst Memory
Read.) If the CPU terminates the transfer by negating
BRST before the falling edge of OS, memoryresponds by
negating BRSTA. (See the example for Burst Memory
Write.) The CPU terminates the burst transaction when
all the required data items have been transferred or after
reaching the end of an aligned, 16-byte block.
2071-017
Figure 17. CPU Burst Transfer Protocol
723
Burst Memory Read
Figure 18 shows timing for a Burst Memory Read transaction with one Wait state. In this example, three data
items are transferred, after which memory terminates
the burst. BRST is asserted at the beginning of T 1; otherwise, the timing for the first transfer is identical to a
single memory read. In the middle of T3 the CPU
samples RSPo-RSP1 Ready, latches the data, and
samples BRSTA active. During T4 the second data item
is transferred, accompanied by OS. The time for the
second and subsequent transfers can be extended with
wait states if· RSPo-RSP1 are sampled Wait; the CPU
does not insert automatic Wait states after the first
transfer.
During T5 the third data item is transferred. At the same
time the RSPo-RSP1 lines are sampled Ready, the data
is latched and BRSTA is sampled inactive. Memory terminates the Burst transfer, and the CPU responds by
negating BRST.
3 DATA TRANSFERS, MEMORY TERMINATES BURST
'~T11~T2---"~T3
BCLK
I.
~
I.
~WAIT STATE-.J
AD =X"",-A_D_D_RE_SS_..J)- -
-
-
-
-(
DATA IN
-,..
T4-.'-TS----...'
1 I.
X
X
DATA IN
I.
DATA IN
)-
I
--C
\.
\~_--JI
OE _ _ _
\~-------------------------------~
RiWJ
STo-ST3
BwlL, BLlW
N~
BRST
X
•
~,------------------------------~----------------------
~~______________________________________________--..J
°RSPo- RSP1, BRSTA, and data sampled;
Figure 18. Burst Memory Read Timing (1 Wait State)
724
2071'()18
Burst Memory Write
Figure 19 shows timing for a Burst Memory Write transaction with no Wait states. In this example, two data
items are transferred, and the CPU terminates the burst.
BRST is asserted at the beginning of T1; otherwise, the
timing for the first transfer is identical to a single
memory write. In the middle of T3 the CPU samples
RSPo-RSP1 Ready and BRSTA active. At the beginning
of T4 the CPU n~gates BRST indicating that one more
data transfer will follow. During T4 the second data item
is transferred, accompanied by OS. The time for the second and subsequent transfers can be extended with
Wait states if RSPo-RSP1 are sampled Wait; the CPU
does not insert automatic Wait states after the first
transfer. Memory recognizes that the CPU has terminated the burst transfer and responds by negating
BRSTA before the end of T4.
2 DATA TRANSFERS, CPU TERMINATES BURST
~T1----"I""'---T2----'I"-T3----'I""'--T4~1
I.
DCLK~
AD
J
ADDRESS
X
DATA OUT
I
>C
I.
X
DATA OUT
IE
RiW~
STo-5T3
DW/L, BUW
HIS
DRST
=x
.~
>C
________________________________________~.
---J/
~"- _ _ _ _ _ _ _ _ _ _
\ _ _ _ _\.a.......-~/_
___J7
*RSPO-RSP1, BRSTA sampled.
Figure 19. Burst Memory Writo Timing
Interlocked Memory Transactions
In some multiprocessing configurations, the CPU must
inhibit other bus masters from referencing shared
memory while the CPU performs two or more transactions. The CPU does this by using status 1111 with any of
the memory transactions described above. A status of
1111 indicates a non-cacheable data reference with in-
2071-019
terlock protection. The CPU uses interlock protection for
data references associated with Test and Set, Decrement Interlocked, and Increment Interlocked instructions. The CPU also uses interlock protection for
references to address translation table entries when
loading the Translation Lookaside Buffer.
725
INPUT/OUTPUT TRANSACTIONS
The CPU uses status 0010 to read from and write to 1/0
ports. 1/0 transactions are generated by I/O instructions
and, when address translation is enabled, by data
references to pages with bit 31 of the page table entry
set to 1.
The timing for 1/0 and memory transactions is very
similar. The major difference is that DS falls in the middle of T2 for 1/0 read timing, compared to the beginning
of T2 for memory read timing. This allows peripheral
AD
~
ADDRESS
}- -
devices more time for address decoding~ Another difference is that the data transfer size (byte, word, or
longword) for I/O transactions is specified by the instruction, not by HICR. The final difference is that the CPU
does not support Burst I/O transactions. Figure 20 shows
timing for an 110 Read transaction. Single 110 Write timing is the sam~ as that shown for a single memory write
(Figure 16).
-
-
-
--(
DATAIN
>- --C
\_-
I
\~----'
RiW.--J
STo-ST3
BWIL, BLlYI
HIS
X
. '-.- - - - - - - - - - - - - - -
°RSPo-RSP1 and data sampled.
Figure 20. 1/0 Read Timing
726
2071"()20
EPU TRANSACTIONS
The CPU and EPU cooperate in the execution of EPA instructions (Figure 21). When the CPU encounters an EPA
instruction and the EPA bit in the FCW is 1, the CPU
broadcasts the first two words of the instruction to the
EPUs in the system using the CPU-EPU instruction
transfer transaction. All EPUs in the system recognize
the transaction, but only one of four possible EPUs is
selected by bits 16 and 17 of the EPU instruction. The
CPU also transfers the PC value for the instruction,
which the selected EPU saves for use in exception
handling. If data transfers are required to complete the
instruction, the CPU controls the data transfer transactions while the EPU drives or receives the data.
The signal EPUBUSY, output from the EPU, is used to
synchronize the CPU and EPU in executing EPA instructions. The CPU must sample EPUBSY inactive before initiating an EPU instruction transfer. If data transfers are
required, the CPU must sample EPUBSY inactive before
initiating the first transfer. EPUBSY is also used to control the degree of overlap between CPU and EPU instruction execution. Ordinarily, the CPU can continue processing other instructions after performing the data
transfers associated with an EPA instruction and before
the EPU has completed executing the instruction. To
simplify debugging and recovery from exceptions, a
Non-Overlap mode is provided, controlled by the EPU 0
bit in HICR. In Non-Overlap mode, the CPU samples
EPUBSY in the middle of the bus cycle during which the
last data transfer for an EPA instruction occurs. If
EPUBSY is asserted, the CPU ceases processing instructions or interrupts until EPUBSY is sampled inactive
in the middle of a bus cycle.
NO
YES
NO
YES
Figure 21. EPA Instruction Processing
To simplify system hardware, the AD lines for CPU and
EPU should be wired together with no buffers between
them. If the AD lines are separated by buffers, external
circuitry must generate iE and OE timing for CPU-to-EPU
Data Read and EPU-to-Memory Write transactions.
2071.021
727
CPU·to·EPU Instruction Transfer
Figure 22 shows timing for a CPU-to-EPU Instruction
Transfer transaction with status 0100. The rising edge of
AS indicates that AD lines and status are valid. During
T1, the AD lines are used to transfer the opcode, i.e., the
first two words of the EPA instruction. At the beginning of
T2 the CPU stops'driving the opcode, asserts DS, and
starts driving PC on the AD lines. The CPU negates DS in
the middle of T2. The data transfer size for the transaction is longword. The CPU ignores RSPo-RSP1.
*EPUBSY sampled.
+ EPUBSY sampled If EPU Internal operation.
Figure 22. CPU·to-EPU Instruction Transfer Timing
728
2071-022
CPU·to·EPU Data Transfer Transactions
Transactions to transfer data between the CPU and EPU
use status 0001. The EPA instructiOn opcode indicates
the number of words to be transferred. One or more
longwords of data are transferred until all words have
been transferred. If the last transfer contains a single
word, the data is replicated on ADo-AD1S and
AD1S-AD31. The CPU does not assert BRST and ignores
RSPo-RSP1 and BRSTA.
Figure 23 shows timing for a CPU-to-EPU Data Read
transaction. This example has two data'transfers; any
number of data transfers between one and eight is possible. The rising edge of AS indicates that status and control signals are valid. The CPU stops driving the AD lines
at the end of T1, and the EPU begins driving the AD lines
in the middle of T2. At the beginning of T3, the CPU
asserts DS. In the middle of T3, the CPU samples the
data and negates DS. The second longword of data is
transferred during T4. After the last data transfer, the
CPU inserts an idle bus cycle (Ts in the example) during
which neither the CPU nor EPU drive the AD lines.
I-T1-I-T2-I-T3-I-T4-I-T5-1
BCLK
J
AD
As
DS
OE
IE
I. I 1 I I I I I I· I I r)------C
>- ---(
X
X
'----I
\.I
'-----f\J
\.
/
\.
UNDEFINED
S.!o-S'D!
BW/L, BUW
His
BRSTA
DATA IN
7
R1W
BRST
DATA IN
7
~
X
)(
7
7
\..
·EPUBSY sampled.
Figure 23., CPU·to-EPU Data Read Timing
2071-023
729
OO
Cl
...e
e
8
~
IIfJ
c:I
Figure 24 shows timing for a CPU-to-EPU data write
transaction. This example has three data transfers; any
number of data transfers between one and eight is possible. Timing for the first transfer is identical to the CPU-to-
EPU instruction transfer transaction. A second longword
of data is transferred during T3. and the third longword is
transferred during T4.
I--Tl-iT2-iT3-I--T41
BCLK
--.J
11.. -*_____I
I
X
AD _ _ _ _ _ _ _......I
UNDEFINED
I
I
X
DATA OUT
I
I
X
DATA OUT
'---I
os
I
1*
X
DATA OUT
I
~
'-
/
_ _....J
\
7
Riw
\
r
X
>C
STo-ST3 - - - - - - - - - - .
BW/L, BLiYi
His _ _ _ _ _ _ _.....J
~
7
7
*EPUBSY'Sampled.
Figure 24. CPU·to·EPU Data Write Timing
730
2071-024
EPU·to·Memory
Trans~ction5
The CPU uses status 1010 or 1011 for the EPU to read
from and write to memory. The timing is identical for
EPU-to-memory read and CPU-to-memory read. The EPU
monitors the CPU timing on the bus, and uses the two
least significant address bits, the data transfer size, and
the length of the operand from the instruction to select
the bytes it needs from the AD lines.
The timing for an EPU-to-memory write transaction differs slightly from a CPU-to-memory write transaction.
Two extra bus cycles are included to pass the AD lines
from the CPU to EPU after the address transfer and from
EPU back to CPU after the last data transfer. Figure 25
shows an example for a single EPU-to-memory write
transaction with no Wait states. The CPU stops driving
the AD lines 'at the end of T1; the EPU begins driving
them in the middle of T2. DS is asserted in the middle of
T3, one bus cycle later than for CPU-to-memory write
timing. The CPU negates D~ in the middle of T4. The CPU
can insert Wait states in the middle of T4. The EPU contin!Jes to drive the AD lines until the end of T4. After the
last data transfer the CPU inserts an idle bus cycle (T5 in
this example) during which neither the CPU nor EPU
drive the AD lines. EPU-to-memory burst write transactions are similarly extended by two bus cycles more than
with CPU-to-memory burst write timing. One cycle is inserted before the first data transfer, and another after
the last data. transfer.
~_ _ _ _ _E_PU_D_A_TA_O_U_T_ _ _ _ _.J>- - - - -
-c
[
[
~
______________________________K
*EPUBSY sampled.
__
+ RSPo-RSPl sampled; EPUBSY sampled if last tran!!action.
Figure 25. EPU·to-Memory Single Write Timing
2071-025
731
INTERRUPT REQUEST AND
ACKNOWLEDGE
The CPU recognizes vectored, nonvectored, and nonmaskable interrupt requests. The decreasing order of
priority for interrupts is nonmaskable, vectored, and
nonvectored. NMI is edge sensitive; when NMI is
asserted, an internal latch is loaded. Vi and NVI are level
sensitive.
The CPU samples VI, NVI, and the internal NMI latch on
the rising edge of ClK. The interrupt request signals can'
be asynchronous to ClK; the CPU synchronizes them internally.
Figure 26 shows timing for an Interrupt Acknowledge
transaction, indicated by status 0101,0110, or 0111. The
timing is similar to a single 1/0 read. Wait states (either
programmed for automatic insertion or externally
generated) can be inserted before OS falls in the middle
of T2 and before OS rises in the middle of T3. Inserting
Wait states before OS falls allows for delay in the interrupt priority daisy chain. A word of data is transferred. All
of the interrupts save the transferred word on the system
stack for processing the interrupt. Vectored interrupts
use the low-order byte of the word to select a unique PC
value from the Program Status Area.
I~Tl---..r-T2-I~T3~1
BCLI(
LJ
~
1
1
I.
1
1+
I
VI, Nvi \ " "_ _ _ _ _ _ _ __
NMI
\'---'&1______
INTERNAL
NMI LATCH
\-------1I.fAD
~
UNDEFINED )- - -<,-__D_AT_A_IN_.->- --C
\
\--__1
\.
\ ___1
Riiv
OJ
STO-S~=X
BwiL,
BLlvt
N/S
'=
>C
.~--------------
*RSPo-RSPl sampled.
+ RSPo-RSPl arid data sampled.
Figure 26_ Interrupt Response/Acknowledge Timing
732
2071-026
INTERNAL OPERATION AND HALT
TRANSACTIONS
Figure 27 shows timing for Internal Operation (status =
0000) and Halt (status = 0011) transactions. Unlike
other bus transactions, data is not transferred in these
operations.
Nevertheless, the transfer size for these transactions is
longword. The minimum duration for the transaction is
two bus cycles.
The CPU generates an Internal Operation transaction
after a sequence of interlocked memory transactions to
free the memory system lock when no other transactions
need to be performed. The CPU generates a Halt transaction upon entering Halt State-when the Halt instruction is' executed, or when memory indicates Bus Error
during a fetch or store of Program Status for exception
processing. The CPU leaves Halt state when an interrupt
or reset occurs. When the minimum Address Strobe rate
option is enabled (controlled by bit MASR in HICR), the
CPU maintains a miniril'um rate for Address Strobes by
generating Halt transactions in Halt state or Internal
Operation transactions otherwise.
rT1-I~T2-1
I
BCLK~
AD
==:><
I
I
I
K
UNDEFINED
IE
'C
STo-ST3
BwiL", BU\1.
1!15
J(
>C
."---------..;.....--
BRSTA
Figure 27. Internal Operation and Halt Timing
BUS RETRY,
During any transaction in which data is transferred, the
responding device can indicate Bus Retry on
RSPo-RSP,. When Bus Retry is indicated, the CPU terminates the transaction in progress, negating DS and
BRST. If Bus Retry is indicated during a Burst transfer,
the Retry transaction begins with the address for the
data transfer where Bus Retry is indicated.
BUS ERROR
During any transaction in which data is transferred, the
responding device can indicate a bus error exception on
RSPo-RSP,. When Bus Error is indicated, the CPU terminates the transaction in progress, negating DS and
BRST. A bus error exception also causes termination of
2071'()27
the instruction in execution. In processing a bus error exception, the CPU saves the Program Status, phYSical address for the transaction, and a word identifying the
status and control signals used for the transaction.
733
BUS REQUEST AND ACKNOWLEDGE
The CPU supports two types of bus request!
acknowledge sequences, local and global. Other bus
masters request the local bus from the CPU using a
handshake of BUSREQ and BUSACK. The CPU requests
a global bus from an external arbiter using a handshake
of GREQ and GACK.
To generate transactions on the local bus, a potential
bus master (such as a DMA controller) must gain control
of the bus by making a bus request (Figure 28). A local
bus request is initiated by asserting BUSREQ. Several
bus requestors can be wired to the BUSREO signal;
priorities are resolved externally to the CPU, usually by a
prioritized daisy chain.
The CPU samples BUSREO on the rising edge of ClK.
BUSREO can be asynchronous to ClK;the CPU synchronizes it internally. After BUSREQ is asserted, the
CPU completes any transaction or sequence of interlocked transactions in progress, including possible
retries. Next the CPU responds by asserting BUSACK
and placing all other output signals in 3-state. When
BUSREQ is negated, the CPU negates BUSACK and
begins driving all other output signals.
The CPU can initiate transactions with devices located
on a global bus shared with other CPUs. At any time, only
one of the CPUs can initiate transactions on the global
bus. Control of the global bus is arbitrated by external
circuitry. Before initiating transactions on the global bus,
the CPU requests control of the global bus from the arbiter using the protocol described below. The CPU uses
two fields of HICR to distinguish between local and
global bus transactions. The GE bit enables use of the
global bus. The 4-bit lA field, which is compared with
bits 26 to 29 of the physical address, specifies one of sixteen. sections of the physical address space to use for
local references; other references use the global request protocol.
.BCLK~j
~
BUSREQ
~----~/,~'-----
~'~'--------------------~/rJ'
....
,
I)
BUSACK
AD
---.!\s, DS,
BRST,GREQ
STo-ST3
BW!~fuD~~YJ
n'~... ~
OE, IE
:;,
,
,
'7
(
~------~r-----~~
f'
'J
r,
\...- -
J.J1------1'
-
- - -..(1- --
- -
-
-..(~
-- '--
Figure 28. Local Bus Request/Acknowledge Timing
734
2071'()28
Figure 29 shows timing for the global bus request/acknowledge protocol. Before initiating a transaction on the global bus, the CPU drives the address,
8To-8T3, BR8T, R/W, N/S, BUW, and BW/L valid at the
beginning of a bus cycle. Then'i in the middle of the bus
cycle, the CPU asserts GREQ. When the global bus
selected by the address is available to the CPU, the ar-
DCLK..lL"j
~f---'
biter asserts GACK. The CPU samples GACK on the rising edge of ClK. GACK can be asynchronous to ClK; the
CPU synchronizes it internally. The CPU performs one or
more transactions on the global bus, then negates
GREQ. The arbiter responds by negating GACK, and the
CPU can then initiate more transactions.
LJl,,~
-----J/~I
_ _
1\--------------~h
r-
u '
AD ) ( :
;;
------1'1/
,'!
,,
,~
If-y-
/~
----------~h~'--------------------~h~'------~iJ~'----I~
\.
\~______~/~/--------------------~~~,------~:~
OE
-------1.1:=><=
s..!o-s!1. J<,......------I:r.'~',-----------------I/,~'
DW/L, DLlW
HIS
,
------I,~--------------_:'r'lJ-----1)
----------~h~'---------------------:,~'l~------~h~'----
DRST
\
~
,
:'J
"
JJ
------~,,~---------------------:f
I,"
"
I,
...
,
C
iJ
Figure 29. Global Bus Request/Acknowledge Timing
2071-029
735
Figure 30 shows a state diagram for the local and global
bus request protocols. To prevent deadlock between
CPUs referencing each other's local memories, a CPU
can be preempted while it is waiting for GACK in State 2.
If BUSREQ is asserted before GACK, the CPU relinquishes the global bus without performing any transactions.
STATE 0 - - - " - - - ,
...-----1
(BUSREa = L).
(GACK = H)
GREa = H
BUSACK = H 1 - - - - - ,
BUS = 2ST
A
=
= H)'
C
B+ GACK = L
__--:i...-....,
ERROR
STATE 1
STATE 2
=
GREa = L
r------1 BUSACK = H 1 - - - - - ,
3ST
GREa
BUSACK = L
BUS = 3ST
BUS
D
Bi:iSREQ = H
=
(BUSREa
H).(GACK
(NEED_G BUS
Hi
= 2ST
(G'Ac'K = L).(BU~REa
E
= H)
STATE 3
F
(GACK = L).
(BUSREa = L)
STATE 4
GREa = L
BUSACK = H
BUS
2ST
=
I--~=-_H_ _--I~I
(GACK
= L)'
[(EiUsREa =
+ (NEED_G
GREa = H
BUSACK = H
BUS
2ST
=
L)
BUS = L))
I
G !GACK = H
GACK = H
ERROR
NOTES: Interface signals are High (H). Low (L). High or Low (251). or 3·slaled (3sl).
Need_G BUS Is an aclive High signal Inlernal 10 Ihe CPU.
Figure 30. State Diagram for CPU Bus Request Protocol
State Legend
Transition Legend
A
A local bus request occurs.
State 0
B
The global bus arbiter grants control of the
global bus when no global bus request is
pending. This is an error. The CPU remains in
State 0.
The CPU controls the local bus and is neither
requesting nor controlling the global bus.
The CPU can perform transactions on the
local bus.
State 1
c
The CPU requests the global bus in response
to the internally generated signal
NEED_GBUS.
The CPU has granted the local bus.
The CPU cannot perform transactions.
State 2
The CPU controls the local bus and is reo
questing the global bus.
The CPU cannot perform transactions.
State 3
The CPU controls the local and global busses.
The CPU can perform transactions on the
global bus.
State 4
The CPU controls the local bus and is relinquishing control of the global bus.
The CPU cannot perform transactions.
o
The local bus master relinquishes the bus.
E
_The global bus arbiter grants the global bus to
the CPU while no local bus request is pending.
F
The global bus arbiter grants the global bus to
the CPU while no local bus request is pending.
The arbiter has preempted the CPU.
G
The global bus arbiter reclaims the global bus
before the CPU relinquishes the global bus.
This is an error. The CPU's response to this
error is undefined.
H
The CPU relinquishes control of the global bus
when it no longer needs the global bus or in
response to a local bus request.
The global bus arbiter reclaims the global bus.
736
2071-030
Reset
Figure 31 shows reset timing. After RESET is asserted,
the CPU responds as follows.
[J
AD lines are turned to input direction
o
AS, BRST, BUSACK, DS, GREQ,
negated
o
STo-ST3 are driven to 1111
o
BW/[ and BUW are driven low
o N/S
iE,'
and OE are
and R/W are undefined
At power on, RESET should be asserted until power has
stabilized.
During reset, bits SX, NX, CI, and CD of the SCCl control
register are cleared, disabling the address translation
and cache mechanisms. Bit GE of H ICR is also cleared,
disabling the global bus request protocol. At the rising
edge of RESET, the relationship between bus timing,
memory data path, and number of automatic Wait states
is determined. If RSPo is High at the rising edge of
RESET, HICR is initialized to a default configuration of
bus clock scale factor 2, word memory data path, and
seven automatic Wait s'tates: If RSPo is low at the rising
edge of RESET, HICR is initialized by latching data from
the AD lines. RESET need not be synchronous with ClK;
however, the CPU assumes that the last rising edge of
ClK on which RESET is asserted corresponds to a rising
edge of BClK. If RESET is synchronized with the rising
edge of the external bus clock, the internal and external
bus clocks will be in phase with respect to ClK. After
RESET is negated, the CPU fetches FCW from address 2
and PC from address 4.
Lj
RESET
~
,
~~
______________________________
~~
_ _ _ _ _ _• __- J
II
':
»"
)~
RSPo
;
----------~h~'------------------------------~f~------~
DATA
;
J,
"
IN
:~:
'-----J;f-----
- - -7;-(
ADDRESS
=2
;'~'----.Ir..
,':
r(
"
'f
);
"
iJ
""
"
)J
::\
»"
----------~J~------------------------------~~------------------~;~~~-ALL HIGH
{;'
If
\STATUS = 1101
~---\~-------------~£~(--------------Jn~
/,1-'
---------------------J;r
c=
Figura 31. Resot Timing
2071-031
737
Addilional
/'
HITrliormalion
Zilog
Pioneering the
Microworld
Z·liiJS®
tCommponermft Hrmiar«:cmIlUtms«:ft
Zilog
Summa.r,.
September 1983
Features
Il
General
Description
The Z-BUS isa high-speed parallel shared
bus that iinks components of the Z8000 Family.
It provides family members with a common
communication interface that supports the
following kinds of interactions:
Multiplexed addressldata bus shared by
memory and 1/0 transfers.
Il 16 or more memory address bits; 16-bit 1/0
addresses; 8 or 16 data bits.
IJ Supports polling and vectored or nonvectored interrupts.
e Daisy-chain interrupt structure services
interrupts without a separate priority
controller.
Data Transfer. Data can be moved between
bus controllers (such as a CPU) and memories or peripherals.
g Interrupts. Interrupts can be generated by
peripherals and serviced by CPU saver
the bus.
e Resource Control. Distributed management
of shared resources (including'the bus itself)
is supported by a daisy-chain priority
mechanism.
The· heart of the Z-BUS is a set of multiplexed addressldata lines and the signals that
control these lines. Multiplexing data and
addresses onto the same lines makes more efficient use of pins and facilitates expansion of
the number of data and address bits. Multiplexing also allows straightforward addressing
of a peripheral's internal registers, which
greatly simplifies 1/0 programming.
A daisy-chained priority mechanism resolves
interrupt and resource requests, thus allowing
distributed control of th~ bus and eliminating
the need for separate priority controllers. The
resource-control daisy chain allows wide
physical separation of components,
The Z-BUS is asynchronous in the sense that
peripherals do not need to be synchronized
with the CPU clock. All timing information is
provided by Z-BUS signals.
Direct addressing of registers within a
peripheral facilitates 1/0 programming.
a Bus signals allow asynchronous CPU and
peripheral clocks.
El Daisy-chain bus-request structure supports
distributed control of the bus.
e Shared resources can be managed by a
general-purpose, distributed resourcerequest mechanism.
13
------PRIMARy SIGNALS------
<
ADo-AD,.
>
EXTENDED ADDRESS
C
2031-0045
STATUS>
BUS
MASTER
--AS_
--os_
PERIPHERAL
AND MEMORY
--R/W_
--B/W _
_
WAIT--
_RESET_
- - - - - B U S REQUEST S I G N A L S - - - - _BUSREQ_
. CPU
--BUSACK_
REQUESTER
r---iiAiL-_
BAO
-----INTERRUPT S I G N A L S - - - - -
_00--
PERIPHERAL
r---IEIL
-_
1EO
----RESOURCE REQUEST SIGNALS-----MMRQ_
Z·BUS
COMPONENT
-MMSf-_MMAI----,
MULTI·MICRO
REQUEST
NETWORK
_MMAO---1
Figure 1. Z-BUS Signals
741
Z-BUS
,Components
Peripherals. A Z-BUS peripheral is a component capable of responding to 1/0 transactions and generating interrupt requests. The
Z8036 Counter Input/Output Circuit (Z-CIO),
Z8038 FIFO Input/Output, Interface Unit
(Z-FIO), the Z8030 Serial Communication
ControJler (Z-SCC), the Z8090 Universal
Peripheral Controller (Z-UPC), and the
Z8052 CRT Controller (Z-CRT) are 'all
Z-BUS peripherals.
Requesters. A Z-BUS requester is any component capable of requesting control of the
bus and initiating transactions on the bus. A
Z-BUS requester is usually also a peripheral.
The Z8016 DMA Transfer Controller (Z-DTC) is
a Z-BUS requester and a peripheral.
Memories. A Z-BUS memory is one that interfaces directly to the Z-BUS and is capable of
fetching and storing data in response to Z-BUS
memory transactions. The Z6132 Quasi-Static
RAM is a Z-BUS memory.
The Z8 Microcomputer-in its microprocessor configuration-conforms to Z-BUS
timing (which allows it to use Z-BUS
peripherals and memories), but is miSSing a
wait input and certain status outputs.
The Z8010 Memory Management Unit
(Z-MMU) is a za900 CPU support component
that interfaces with part of the Z-BUS on the
CPU side and provides demultiplexed
addresses on the memory side.
The "28060 First-In-First-Out Buffer (Z-FIFO)
is not a Z-BUS component; rather, it is used to
expand the buffer depth of the Z-FIO or to
interface the 1/0 ports of the Z-UPC, Z-CIO,
or Z-FIO to user equipment.
Z-80 Family components, while not
Z-BUS compatible, are easily interfaced to
Z-BUS CPUs.
'Two kinds of operations can occur on the
Z-BUS: transactions and requests. At any given
time, one device (either the CPU or a bus
requester) has control of the Z-BUS and is
known as the bus master. A transaction is
initiated by a bus master and is responded to
by some other device on the bus. Four kinds of
transactions occur in Z-BUS systems:
at a time, and it must be initiated by the bus
master. A request, however, may be initiated by a component that does not have control of the bus. There are three kinds of
requests:
A Z-BUS component is one that uses Z-BUS
signals and protocols, and meets the specified
ac and dc characteristics. Most components in
the Z8000 Family are Z-BUS components. The
four categories of Z-BUS components are as,
follows:
CPUs. A Z-BUS system contains one CPU, and
this CPU has default control of the bus and
typically initiates most bus transactions.
Besides generating bus transactions, it handles
interrupt and bus-control requests. The Z8001
Segmented CPU and Z8002 Non-Segmented
CPU are Z-BUS CPUs.
'
Other
'. Components
Operation
• Memory. Transfers 8 or 16 bits of data to or
from a memory location.
• 1/0., Transfers 8 or 16 bits of data to or from
a peripheral.
• Interrupt Acknowledge. Acknowledges
an interrupt and transfers an identification/status vector from the interrupting.
peripheraL
• Null. Does not transfer data. Typically used
for refreshing memory.
Only one transaction can proceed on the bus
742
• Interrupt. Requests the attention of the
Z-BUS CPU.
• Bus. Requests control of the Z-BUS to initiate transactions.
• Resource. Requests control of a particular
resource.
When a request is made, it is answered
according to its type: for interrupt requests an
interrupt-acknowledge transaction is initiated;
for bus and resource requests an acknowledge
signal is sent. In all cases a daisy-chain priority mechanism provides arbitration between
simultaneous requests.
Signal
Lines
The Z-BUS consists of a set of common signal
lines that interconnect bus components (Figure
1). The signals on these lines can be grouped
into four catagories, depending on how they
are used in transactions and requests.
Primary Signals. These signals provide
timing, control, and data transfer for Z-BUS
transactions.
ADo-AD1S. Address/Data (acfiveHigh). These
multiplexed data and address lines carry 1/0
addresses, memory addresses, and data during
Z-BUS transactions. A Z-BUS may have 8 or 16
bits of data depending on the type of CPU. In
the case of an 8-bit Z-BUS, data is transferred
on ADo-AD7.
Extended Address. (active High). These
lines extend ADo-AD15 to support memory,
addresses greater than 16 bits. The number of
lines and the type of address information
carried is dependent on the CPU.
Status. (active High). These lines designate
the kind of transaction occurring on the bus
and certain additional information about the
transaction (such as program or data memory
access or System versus Normal Mode).
AS. Address Strobe (active Low). The rising
edge of AS indicates the beginning of a transaction and that the Address, Status, R/W, and
B/W signals are valid.
DS. Data Strobe (active Low). DS provides
timing for data movement to or from the bus
master.
R/W. Read/Write (Low = write). This signal
determines the direction of data transfer for
memory or I/O transactions.
B/W. Byte/Word (Low = word}. This signal
indicates whether a byte or word of data is to
be transmitted on a 16-bit bus. This signal is
not present on an 8-bitbus.
.
WAIT. (active Low). A Low on this line indicates that the responding device needsmore
time to complete a transaction.
RESET. (active Low). A Low on this line resets
the CPU and bus users. PeripherC\ls may be
reset by
RESET or by holding AS a~d DS Low
simultaneously.
CS. Chip Select (active Low). Each perjpheI'al
or memory component has CS line that is
decoded from the address and status lines. A
Low on this line indicates that the peripheral
or memory component is being addressed by a
transaction. The Chip Select information is
latched on the rising edge of 'AS.
a
Bus Request Signals. These signals make
bus requests and establish. which component
should obtain control of the bus.
.
BUSREQ. Bus Request (active Low). This line.
is driven by all bus requesters. A Low indicates that a bus requester has or is trying to
obtain control of the bus.
BUSACK. Bus Acknowledge (active Low). A
Low on this line indicates that the Z-BUS CPU
has relinquished control of the bus in response
to a bus request.
BAI, BAD. Bus Acknowledge In, Bus
Acknowledge Out (active Low). These signals
form the bus-request daisy chain.
743
Z-BUS
Connections
Signal
CPU
Requester
Peripheral
Memory
ADo-ADI5
Bidirectional2
3-state
Bidirectiona12
3-state
Bidirectional l
3-state
Bidirectional2
3-state
Extended
Address8
Output
3-state
Output
3-state
0
Input
Status
Output
3-state
Output
3-state
InputlO
0
R/W
Output
3-state
Output
3-state
Input
Input
B/W9
Output
Output
Input3
Input--
Input
Output8
WAIT
Input
Output8
Open Drain
Output
3-state
Input
Input
AS
Output
3-state
DS
Output
3-state
Output
3-state
Input
Input
CS4
0
0
Input
Input
Input
Input l3
InputS
BUSREQ
Input
Bidirectional
Open Drain
0
0
BUSACK
0
RESET
!
0--
Output
0
0
BAfl
0
Input
0
0
BA07
0
Output
0
0--
Input
0
Output
'Open Drain
0
INTACK6
0
0
Input ll
0
IEI7
0
0
Input
0
0
OutQut
Open Drain
0
Output
0
INT
IE07,
MMRQ12
MMST12
Input
MMAI7,12
Input
MMA07,12
Output
1.
2.
3.
4.
Only ADO-AD7' unless peripheral is 16-Bit.
For an 8-bit bus, only ADO':AD7 are bidirectional.
Only for a 16-bit peripheral.
Derived signal, one for each peripheral or memory; decoded
from status and address lines.
5. Optional-peripherals are typically reset by AS and i5S being
Low simultaneously; however, they 'can have a reset input.
6. Derived signal; decoded from status lines.
7. Daisy-chain lines.
8. Optional signal(s).
9. For 16-bit data bus only.
10. Optional-usually only input on peripherals that are also
requesters.
II. May be omitted if peripheral inputs status lines.
12. Optional signal; any component may attach to the resource
request lines.
13. Optional signal; a bus~requestor may also be reset by As and
OS going Low and BAl being High simultaneously.
o No Connection
Table I. Z-BUS Component Connections to
Signal Lines. This table shows how the
requester and a peripheral, the attributes in
both columns of the table should be combined
(e.g., input combined with output and 3-state
becomes bidirectional and 3-state.)
various Z-BUS components attach to each
signal line. When a device is both a bus
744
Open Drain
Signal
Lines
(Continued)
Interrupt Signals. These signals are used for
interrupt requests and for determining which
interrupting component is to respond to an
acknowledge. To support more than one type
of interrupt, the lines carrying these signals
can be replicated. (The Z8000 CPU supports
three types of interrupts: non-maskable, vectored, and non-vectored.)
INT. Interrupt (active Low). This signal can
be driven by any peripheral capable of generating an interrupt. A Low on INT indicates that
an interrupt request is being made.
INTACK. Interrupt Acknowledge (active
Low). This signal is decoded from the status
lines. A Low indicates an interrupt acknowledge transaction is in progress. This signal
is latched by the peripheral on the rising
edge of AS.
lEI, lEO. Interrupt Enable In, Interrupt Enable
Out (active High). These signals form the
interrupt daisy chain.
Resource Request Signals. These signals are
used for resource requests. To manage more
than one resource, the lines carrying these
signals can be replicated. (The Z8000 supports
one set of resource request lines.)
MMRQ. Multi-Micro Request (active
Low). This line is driven by any device that
can use the shared resource. A Low indicates
that a request for the resource has been made
or granted.
MMST. Multi-Micro Status (active Low). This
pin allows a device to observe the value of the
MMRQ line. An input pin other than MMRQ
facilitates the use of line drivers for MMRQ.
MMAI, MMAO. Multi-Micro Acknowledge In, .
Multi-Micro Acknowledge Out (active
Low). These lines form the resource-request
daisy chain.
Transactions
All transactions start with Address Strobe
being driven Low and then raised High by the
bus master (Figure 2). The Status lines are
valid on the rising edge of Address Strobe and
indicate the type of transactions being initiated. If the transaction requires an address,
it must also be valid on the rising edge
of Address Strobe.
For all transactions except null transactions
(which do nothing beyond this point), data is
then transferred to or from the bus master. The
bus master uses Data Strobe to time the movement of data. For a read (R/W = High), the
bus master makes ADo-AD15 inactive before
.driving Data Strobe Low so that the
addressed memory or peripheral can put its
data on the bus. The bus master samples this
data just before raising Data Strobe High. For
a write (R/W = Low), the bus master puts the
data to be written on ADo-AD15 before forcing
Data Strobe Low.
For an 8-bit Z-BUS, data is transferred on
ADo-AD7. Address bits may remain on
ADs-AD15 while DS is Low.
CLOCK
/
' - - - - - 7 BUS MASTER/
BUS MASTER
SAMPLES WAIT
STO-ST3
-+-_
R/W, D/W _ _ _
ADo-AD15
ADO-AD15
2031-0181
"'---
SAMPLES
INPUT DATA
'"------+--------f .f~-----__t-- '-___
ADDRESS FROM
BUS MASTER
DATA TO
BUS MASTER
DATA FROM BUS MASTER
745
Memory
Transactions
For a memory transaction, the Status lines
distinguish among various address spaces,
such as program and data or system and normal, as well as indicating the type of transaction. The memory address is put on
ADo-AD15 and on the extended address lines.
For aZ-BUS with 16-bit data, the .memory is
organized as two banks of eight bits each
(Figure 3) .. One bank contains all the upper
bytes of all the addressable 16-bit words. The
other bank contains all the lower bytes. When
a single byte is written (R/W = Low,
B/W = High), only the bank indicated by
address bit Ao is enabled for writing.
For a Z-BUS with 8-bit data, the memory is
organized as one bank which contains a'll
bytes. This bank always inputs and outputs its
data on ADo-AD7.
1C1·DIT Z·I:lUS DATA PATH
D
Ao-A15
EXTEtlDED
ADDRESS
LOWER
BANK
--t:==:::!::==L./----------' ENABLE
Figuro 3. By to/Word Momory Organization
1/0
Transactions
I/O transactions are similar to memory
transactions with two important differences.
The first is that I/O transactions take an extra
clock cycle to allow for slow peripheral operation. The second is that byte data (indicated
by B/W High on a 16-bit bus) is always trans-
mitted on ADo-AD7, regardless of the I/O
address. (ADB-AD15 contain arbitrary data in
this case.) For an I/O transaction, the address
indicates a peripheral and a particular register
or function within that peripheral.
Null
Transactions
The two kinds of null transactions are distinguished by the Status lines: internal operation and memory refresh. Both tranflar.tions
look like a memory read transaction except
that Data Strobe remains High and nodata is
transferred.
For an internal operation transaction, the
Address lines contain arbitrary data when
Address Strobe goes High. This transaction is
initiated to maintain a minimum transaction
rate when a bus master is doing a long internal
operation (to support memories which generate
refresh cycles from Address Strobe).
746
For a memor}T refresh trannaction, the
. Address lines contain a refresh address when
Address Strobe goes High. This transaction is
used to refresh a row of a dynamic memory.
Any memory or I/O transaction can be suppressed (effectively turning it into a null transaction) by keeping Data Strobe High throughout the transaction.
2031·0182
Interrupts
and Interrupt Enable bit (IE), and an Interrupt
Under Service bit (IUS).
. A peripheral may also have one or more
vectors for identifying the source of an interrupt during an interrupt-acknowledge transaction. Each interrupt source is associated with
one interrupt vector and each interrupt vector
can have one or more interrupt sources associated with it. Each vector has a Vector Includes
Status bit (VIS) controlling its use.
Finally, each peripheral has three bits for
controlling interrupt behavior for the whole
device. These are a Master Interrupt Enable
bit (MIE), a Disable Lower Chain bit (DLC),
and a No Vector bit (NV).
A complete interrupt cycle consists of an
interrupt request followed by an interruptacknowledge transaction. The request, which
consists of INT pulled Low by a peripheral,
notifies the CPU that an interrupt is pending.
The interrupt-acknowledge transaction, which
is i~itiated by the CPU as a result of the
request, performs two functions: it selects the
peripheral whose interrupt is to be acknowledged, and it obtains a vector that identifies
the selected device and cause of interrupt.
A peripheral can have one or more sources
of interrupt. Each interrupt source has three
bits that control how it generates interrupts.
These bits are an Interrupt Pending bit (IP),
INTERRUPT
VECTOR
IIlTERRUPT
VECTOR
~
~
... ~
~
,--I- - - i f ,f-~_---'I
I
I\r~~~--------~,r------~
HIGHEST PRIORITY
IIlTERRUPT SOURCE
...
lEI
HIGIIE~~
PRIORI~~
LOWEST
PRIORITY
Z·DUS
PERIPHERAL
A+L:j
Arr
tti
lEO
INTACK
ACo-AC,
AS
Z·DUS
CPU
os
iNr
WAIT
STATUS
ACa-AC"
1 , ,
1 I
~.
I
===>t
p
STATUS
DECODER
Z·DUS
PERIPHERAL
lEI ACo-AC,
L--J
Z·DUS
PERIPHERAL
AS . os iNf INTACK lEO
I Itt I
I
1 J
1 I
1
rI.
r----1
"
.,
',',
',',
, ,,
II
os
I
lEI ACo-AC, AS
+
iNf iNfACi< lEO
•
>;
,,
' ,
fROIo! 16·I:IT PERIPIfERALI
Figure 4. Interrupt Connections
2031·0189
747
Interrupts
(Continued)
748
Peripherals are connected together via an
interrupt daisy chain formed with their lEI and
IEO pins (Figure 4). The interrupt sources .
within a device are similarly connected into
this chain with the overall effect being a daisy
chain connecting the interrupt sources. The
daisy chain has two functions: during an
interrupt-acknowledge transaction, it determines which interrupt source is being
acknowledged; at all other times it determines
which interrupt sources can initiate an interrupt request.
Figure 5 is a state diagram for interrupt
processing for an interrupt source (assuming
its IE bit is 1). An interrupt source with an
interrupt pending (IP = 1) makes an interrupt
request (by pulling INT Low) if, and only if, it
is enabled (IE = 1, MIE = 1), it does not have
an interrupt under service (IUS = 0), no
higher priority interrupt is being serviced
(IEI = High), and no interrupt-acknowledge
transaction is in progress (as indicated by
INTACK at the last rising edge of AS). IEO is
not pulled down by the interrupt source at this
time; lEO continues to follow IEI until an
interrupt-acknowledge transaction occurs.
S~me time after INT has been pulled Low,
the CPU initiates an interrupt-acknowledge
transaction (indicated by INTACK Low).
Between the rising edge of AS and the falling
edge of DS, the IEIIIEO daisy chain settles.
Any interrupt source with an interrupt pending
(IP = 1, IE = 1, MIE = 1) or under service
(IUS = 1) holds its IEO line Low; all other
interrupt sources make IEO follow IEI. When
DS falls, only the highest priority interrupt
source with a pending interrupt (IP = 1) has
its IEI input High, its IE bit set to 1, and its
IUS bit set to O. This is the interrupt source
being acknowledged, and at this point it sets
its IUS bit to 1, and, if the peripheral's NV bit
is 0, identifies itself by placing the vector on
ADo-AD7. If the NV bit is 1, then the peripheral's ADo-AD7 pins remain floating, thus
allowing external circuitry to supply the vector. (All interrupts, including the Z8000's nonvectored interrupt, need a vector for identifying the source of an interrupt.) If the ,vector's
VIS bit is 1, the vector will also contain status
information further identifying the source of
the interrupt. If the VIS bit is 0, the vector
held in the peripheral will be output without
modification.
While an int~rrupt source has an interrupt
under service (IUS = 1), it prevents all lower
priority interrupt sources from requesting
interrupts by forCing IEO Low. When interrupt
servicing is complete, the CPU must reset the
IUS bit and, in most cases, the IP bit (by
means of an I/O transaction).
A peripheral's Master Interrupt Enable bit
(MIE) and Disable Lower Chain bit (DLC) can
modify the behavior of the peripheral's interrupt sources in the following way: if the MIE
bit is 0, the effect is as if every Interrupt
Enable bit (IE) in the peripheral were 0; thus
all interrupts from the periphera.l are disabled.
If the DLC bit is 1, the effect is to force the
peripheral's lEO output Low, thus disa'bling all
, lower priority devices from initiating interrupt
requests.
Polling can be done by disabling interrupts
(using MIE and DLC) and by reading peripherals to detect pending interrupts. Each
Z-BUS peripheral has a single directly
addressable register that can be read to determine if there is an interrupt pending in the
device and, if so, what interrupt source
it is from.
Interrupts
(Continued)
HIGH
STATE'll
HIGH
LOW
N
LOW
IP
IUS
IE
IP
11 10 11 1
IUS
=•
IE
d
11 10 11 1
STATE'll
(Ii
STATE 4
ANY
ANY
IP
IUS
I
IE
1 0 11 11
G
STATE 5
ANY
IP
>
IUS
IE
STATE 8
ANY
E4
IP
1111111
IUS
IANyl 0 I
IE
0I
c¢
STATE 7
ANY
C¢
IP
IUS
~N~
IE
1 101
C¢
STATE 8
Figure 5. State Diagram for an Interrupt Source
Transition Legend
State Legend
fA\. The peripheral detects an interrupt condition and sets
t::/' Interrupt Pending.
FB'All higher priority peripherals finish interrupt se'rvice,
t.::/' thus allowing lEI to go High.
rc"'An interrupt-acknowledge transaction starts, and the
~ IEIIIEO daisy chain settles.
[£> The interrupt-acknowledge transaction terminates with
the peripheral selected. Interrupt Under Service (IUS)
is set to 1, and Interrupt Pending (IP) mayor may not
be reset.
rE'The interrupt-acknowledge transaction terminates with a
~ higher priority device having been selected.
rf'. The Interrupt Pending bit in the peripheral is reset by
l!:,/ an I/O operation.
[Q> A new interrupt condition is detected by the peripheral,
causing IP to be set again.
,
fH'.. Interrupt service is terminated for the peripheral by
LV'resetting IUS.
lE> IE is reset to zero, causing interrupts to be disabled.
IE> IE is set to one, re-enabling interrupts.
1. This diagram assumes MIE = 1. The effect of MIE = 0 is the
same as that of setting IE = O.
2. The DLC bit does not affect the states of individual interrupt
sources. Its only effect is on the IEO output of a whole peripheral.
2031-0185
No interrupts are pending or under service for this
peripheral.
An interrupt is pending, and an interrupt request has
been made by pulling INT Low.
An interrupt is pending, but no interrupt request has
been made because a higher priority peripheral has an
interrupt under service, and this has forced IEI Low.
An interrupt-acknowledge sequence is in progress, and
no higher priorify peripheral has a pending interrupt.
An interrupt-acknowledge sequence is in progress, but
a higher priority peripheral has a pending interrupt,
forcing lEI Low.
IIJ the peripheral has an interrupt under service. Service
may be temporarily suspended (indicated by lEI going
Low) if a higher priority device generates an interrupt.
This is the same as State 5 except that an interrupt is
also pending in the peripheral.
Interrupts are disabled from this source because IE
o.
Interrupts are disabled from this source and lower
priority sources because IE = 0 and IUS = 1.
3. Transition I to state 6 or 7 can occur from any state except 3 or
4 {which only occur during interrupt acknowledge}.
4. TranSition J from state 6 c;>r 7 can be to any state except 3 or 4,
depending on the value of IEI, IP, and IUS.
749
Interrupts
(Continued)
STATE 1
HIGH~
~+BAo~
BUS REQUESTERS
I-~==~--------------------------~--------~
~~==~~~
~_:_IH--.~ ~.B
______________- r______________
BAi
~
~
~
w
STATE 6
~
STATE 7
Figure 6. Bus Request Mechanism States
High, it may request the bus when its BAI input
rises; otherwise if it wants the bus, it must wait for
BUSREQ to rise.
Bus Requester Legend
[DRequester does not want bus and is not pulling
BUSREQ Low.
.
r2'>Requester mayor may not want bus; it is pulling
BUSREQ Low in either case.
a..=,;'
rp.Requester is not pulling BUSREQ Low; it it wants
~control of the bus, it must wait for BUSREQ and
BAI to rise before requesting the bus.
'4'Requester is either using the bus or propagating .
U/"the Low on its BAI input. It will stop driving
BUSREQ when its BAO output goes Low. If it
wants to use the bus, but did not want to at the
time BUSREQ arid BAI were last High or BUSREQ
went from Low to High, then it must wait for
BUSREQ and BAI to rise before requesting and
using the bus ..
IS'Requester is not pulling BUSREQ Low. If it wants
t:!.I"to use the bus, it must wait for its BAI to become
High before requesting the bus.
. f6'Requester is propagating the High on its BAY _
~iriput. If it wants the bus it will pull BUSREQ Low.
~equester
. input..
is propagating the High on its BAI
.
rtJtequester is not· pulling BUSREQ Low. If it ~anted
o/the bus at the time BUSREQ went from Low to
750
Bus State Legend
mThe CPU owns the bus and no one is ;equesting it.
rn
A bus requester has requested the bus by pulling
BUSREQ Low, but the CPU has nor responded.
[]] A Low from the CPU's BUSACK is propagating
down the BAIIBAO daisy chain. Bus requesters are
using the bus. .
------mThe
Low from BUSACK has propagated to the end
of the daisy chain causing all bus requesters to
release BUSREQ, which floats High. The CPU has
not yet acknowledged return of the bus.
[[] The CPU acknowledges the High on ===
BUSREQ with
a High on BUSACK, which has propagated down
the BAIIBAO daisy chain.
[§] Some device whose BAi input is High requests the
bus by pulling BUSREQ Low. The CPU has not yet
. responded with a Low on BUSACK.
m
The CPU has responded to a Low on BUSREQ with
. a Low on BUSACK. The previous High state on
BUSACK is still propagating. down the BAIIBAO
daisy chain.
Interrupts
(Continued)
Transition Legend
A A bus requester requests the bus by pulling down
on BUSREQ.
D The CPU responds to BUSREQ High by driving
BUSACK High.
B The CPU reponds to BUSREQ by pulling down
BUSACK.
E The High fromB--.....
U--SR--E-Q-- propagates to the end of
the BAIIBAO daisy chain.
C The Low from BUSACK propagates to the end of
the BAIIBAO daisy chain, causing all the bus requesters to let BUSREQ rise.
Bus
Requests
Figure 7 shows how the bus request lines
connect bus requesters and the CPU on a
Z-BUS. Figure 8 shows the states of the bus
request mechanism as the Z-BUS is acquired,
used, and released.
To generate transactions on the bus, a bus
requester must gain control of the bus by
making a bus request. This is done by pulling
down BUSREQ . A bus request can be made in
either of two cases:
II
BUSREQ is initially High and BAI is High,
indicating that the bus is controlled by the
CPU and no other requester is requesting
the bus.
iii
BAI is High and the requester had wanted
to request the bus at the time of the last
Low-to-High transition of BUSREQ . This
insures that a module will not be locked out
indefinitely by a higher priority bus
requester.
After BUSREQ is pulled Low, the Z-BUS
CPU relinquishes the bus and indicates this
condition by making BUSACK Low. The Low
on BUSACK is propagated through the
BAIIBAO daisy chain (Figure 7). BAI follows
BAO for components not requesting the bus,
and any component requesting the bus holds
its BAO High, thereby locking out all lower
priority requesters. A bus requester gains con-
Z·BUS CPU
BUS
REQUESTORS
trol of the bus when its BAI input goes Low.
When it is ready to relinquish ,the bus, it stops
pulling BUSREQ Low and allows BAO to
follow BAI. This permits lower priority devices
that made simultaneous requests to gain control of the bus. When all Simultaneously
requesting devices have relinquished the bus,
and the Low on BAIIBAO has propagated to
the lowest priority requester, BUSREQ goes
High, returning control of the bus to the CPU.
The CPU responds to the High on
BUSREQ' by driving BUSACK High. The High
on BUSACK is propagated down the BAIIBAO
daisy chain, thus allowing bus requesters to
make new bus requests. Because high priority
bus requesters can pull BUSREQ Low before
low priority devices have a High on BAI, a
way is needed for low priority devices to
request the bus when BUSREQ is Low. That is
prOVided by the rule that a requester may
request the bus if BAI is High and it had
wanted the bus at the time the last Low-to-High
transition on BUSREQ .
As soon as BUSREQ is pulled Low by any
requester, each of the other requesters on the
bus drives BUSREQ Low and continues to do
so until it drives its BAO output Low. This provides a handshake between the CPU and the
bus requesters by ensuring that BUSREQ will
not go High until the CPU's acknowledgement
of BUSACKhas reached ever'{ requester. Bus
requesters can therefore run asynchronously to
the CPU. This rule also allows the bidirectional
BUSREQ line to be buffered using the logic
shown in Figure 8. Thi~ logic is similar to the
logic inside a bus requester ,that keeps
BUSREQ Low when it has initially been
pulled Low by a different requester.
+5V
+ 5 V --"N\r--..-....
COMMON
iiUSREQ
Figure 8.. Bus Request Line Buffering
Figure 7. Bus Request Connections
751
Resource
Requests
Resource requests are used to obtain control
of a resource that is 'shared between several
users. The resource can be a common bus, a
common memory or any other resource .. The
requestor can be any component capable of
implementing the request protocol.
Unlike the Z-BUS itself, no component has
control of a general resource by default; every
device must acquire the resource before using
it. All devices sharing the general resource
drive the MMRQ line (Figure 9). When Low,
the MMRQ line indicates that the resource is
being acquired or used by some device. The
MMST pin allows each device to observe the
state of the MMRQ line.
When MMRQ is High, a device may initiate
a resource request by pulling MMRQ Low
(Figure 10). The resulting Low on MMRQ is
propagated through the MMAI/MMAO daisy
chain. If a device is not requesting the
resource, its MMAO output follows its MMAI
input. Any device making a resource
request forces its MMAO output High to deny
lise of the resource to lower priority devices.
A device gains control of the resource if its
MMAI input is Low (and its MMAO output is
High) after a sufficient delay to let the daisy
chain settle. If the device does not obtain the
resource after this short delay, it must stop
pulling MMRQ Low and make another request
at some later time when MMRQ is again High.
When a device that has gained cont~ol of a
resource is finished, it releases the resource by
allowing MMRQ to go High.
Th~ four unidirectional lines of the resource
request chain allow the use of line drivers,
thus facilitating connection of components
separated by some distance. In the case of the
Z8000 CPU, the four resource request lines
may be mapped into the cpuMf and MO pins
using the logic shown in Figure 11. With this
configuration, the Multi-Micro Request Instruction (MREQ) performs a resource request.
YES
+5V
MMAI \ - . - - - - - - - - - - 4
MMST
MMRO
I...-------~
1-_------4
MMAO
Figure 10. Resource Request Protocol
MMAI
MMST
I...-------~
MMRO I-_------~
MMAO
1. For any resource requested, this wait time must be less than the
minimum wait time plus resource usage time 01 all other
requesters.
~--------------~MMST
MMAI
MMST ....- - - - - - - - - - 4
MMRO
MMRO
MMAoi
I
I
I
I
I
Figure 9. Resource Request Connections
752
Mi----«
Hf--t.>--------
MMRQ
MO~----------------~
---L-yl------- MMAO
Figure 11. Bus Request Logic for Z8000
Test
Conditions
The timing characteristics given in this
document reference 2.0 V as High and 0.8 V
as Low. The following test load circuit is
assumed. The effect of larger capacitive
loadings can be calculated by delaying output
signal transitions by 10 ns for each additional
50 pF of load up toa maximum 200 pF.
+5V DC
+5VDC
2.2K
'"." ."""'1.T'"
UNDER TEST
r
50pF
Open-Drain Tost Load
DC
Characteristics
The following table states the dc character~
istics for the input and output pins of Z-BUS
Symbol
Parameter
VIL
VIH
VIHRESET
Input Low Voltage
Input High Voltage
Input High Voltage on RESET pin
VOL
VOH
IlL
10L
Capacitance
Timing
Diagramll
8085·004, 005
Output Low Voltage
Output High Voltage
Input "Leakage Current
3-State Output Leakage Current in Float
Standard Tost Load
components. All voltages are relative to
ground.
Min
Max
Unit
-0.3
2.0
2.4
0.8
Vee +0.3
Vee to
0.3
0.4
V
V
V
+10
+10
/LA
2.4
-10
-10
V
V
/LA
Test Condition
~
10L = 2.0mA
10H = 250/LA
VIN = 0.4 to 2.4 V
VOUT = 0.4 to 2.4 V
The following table gives maximum pin
capacitance for Z-BUS components. Capacitance is specified -at a frequency of 1 MHz
over the temperature range of the component.
Unused pins are returned to ground.
Symbol
The folloWing diagrams and tables give the
timing for each kind of transaction (except null
transactions). Timings are given separately for
bus masters and for peripherals and memories
and are intended to give the minimum timing
requirements which a Z-BUS component must
meet. An individual component will have more
detailed and sometimes more stringent timing
specifications. The differences between bus
master timing and peripheral and memory timing allow for buffer and decoding circuit
delays and for signal skew. The timing given
for memories is a constraint on bus-compatible
memories (like the Z6132 Quasi-Static RAM)
and is not intended to constrain memory subsystems constructed from conventional components.
Besides these timings, there is a requirement
that at least 128 transactions be initiated in any
2 ms period. This accommodates IJ1emories that
generate refresh cycles from Address Strobe.
CIN
COUT
·Cvo
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Max (pF)
10
15
15
753
t':3
eJ
(il
)
Bus Master
Timing
~l
------(i)-CLOCK
---.I
CD-- --
~
STo-ST3
R/W,B/W
)
J
N-
-~(i}--I-{j)---~I
-
--~
t~
--®--I )
r---'-.
WAIT CYCLES
ADDEO
SAMPLED
-+---~:------------+--------~
1-----------4GD~------~~1
_____________®_52=====:~----~
754
T
2031·0240,0187, 0191
No.
Symbol
Parameter
Min
4 MHz
Max
6 MHz
Min
Max
Notes*t
All Transactions
250
2000
1
TpC
Clock Period
2000
165
105
70
2
TwCh
Clock High Width
70
3
TwC1
Clock Low Width
105
4
TfC
Clock Fall Time
20
10
5 - TrC
Clock Rise Time - - - - - - - - - - - - - - - - - 20 - - - - - - 1 5 - - - - - 6
TdC(S)
Clock t to Status Valid Delay
110
85
Clock' to AS t Delay
90
80
7
TdC(ASr)
8
TdC(ASf)
Clock t to AS , Delay
80
60
9
TdS(AS)
Status Valid to AS t Delay
50
30
10-TwAS
AS Low Width - - - - - - - - - - - - - - 80 - - - - - - 5 5 - - - - - - - - 11
TdDS(S)
DS t to Status Not Valid Delay
75
55
12
TdAS(DS)
AS t to DS , Delay
80
2095
55
3
13
TsDR(C)
Read Data !2.-Clock' Setup Time
30
20
14
TdC(DS)
Clock' to DS t Delay
70
65
15-TdDS(AS)--DS t to AS , Delay
70
35-------16
TdC(Az)
Clock t to Address Float Delay
65
55
17
TdC(A)
Clock t to Address Valid Delay
100
75
18
TdA(AS)
Address Valid to AS t Delay
50
35
19
TdAS(A)
AS t to Address Not Valid Delay
70
45
20- TwA
Address Valid Width - - - - - - - - - - - - 150 - - - - - - 8 5 - - - - - - - - 21
ThDR(DS)
Read Data to DS t Hold Time
0
0
22
TdDS(A)
DS t to Address Active Delay
80
45
23
TdDS(DW)
DS t to Write Data Not Valid Delay
50
45
24
TsW(C)
WAIT to Clock' Setup Time
50
30
2,4
25-ThW(C)
WAIT,to Clock' Hold Time
10
10------2,4_
_ _ Memory Transactions
26
TdAS(W)
AS t to WAIT Required Valid
90
45
85
27
TdC(DSR)
Clock' to DS (Read) , Delay
120
28
TdDSR(DR)
DS (Read) , to Read Data Required Valid
200
130
29
TwDSR
DS (Read) Low Width
250
185
30-TdA(DS)-'--Address Valid to DS , Delay---------180 - - - - - - 1 1 0 - - - - - - - - 31
TdAz(DSR)
Address Float to DS (Read) , Delay
0
0
32
TdAS(DR)
AS t to Read Data Required Valid
360
220
33
TdA(DR)
Address Valid to Read Data Required Valid
305
410
Clock! to DS (Write) , Delay
34
TdC(DSW)
80
95
35-TwDSW
DS (Write) Low W i d t h - - - - - - - - - - - 1 6 0 - - - - - - 1 1 0 - - - - - - - - 36
TdDW(DSWf)
Write Data Valid to DS (Write) , Delay
50
35
230
195
37
TdDW(DSWr)
Write Data Valid to DS (Write) t Delay.
I/O Transactions
38
TdAS(DR)
AS t to Read Data Required Valid
610
385
470
39
TdA(DR)
Address Valid to Read Data Required Valid
660
40-TdAz(DSl)--Address Float to DS (VO) , - - - - - - - - - - 0 - - - - - - 0 - - - - - - - - 41
TdC(DSI)
Clock' to DS (VO) ,
120
90
210
42
TdDSI(DR)
DS (VO) , to Read Data Required Valid
330
43
TwDSI
DS (VO) Low Width
400
255
180
110
44
TdA(DSl)
Address Valid to DS (VO) , Delay
45-TdDW(DSIf)--Write Data to DS (I/O) , D e l a y - - - - - - - - 5 0 - - - - - - 3 5 - - - - - - - 46
TdDW(DSlr)
Write Data to DS (VO) t Delay
480
320
210
47
TdAS(W)
AS to WAIT Required Valid
340
Interrupt-Acknowledge Transactions
690
48
TdAS(DSA)
AS t to DS (Acknowledge) , Delay
960
49
TdC(DSA)
Clock t to DS (Acknowledge) , Delay
120
85
50-TdDSA(DR)--DS (Acknowledge) , to Read Data Required Valid - - - - - 455 - - - - - - 2 9 5 - - - - - 51
TwDSA
DS (Acknowledge) Low Width
485
315
52
TdAS(W)
AS t to Wait Required Valid
840
540
53
TdDSA(W)
DS (Acknowledge) , to Wait Required Valid
185
120
NOTES:
1. Timing for extended addresses is CPU dependent; however,
extended addresses must be valid at least as soon as addresses
are valid on ADO-ADlS and must remain valid at least as
long as addresses are valid on ADO-ADlS.
2. The exact clock cycle that wait is sampled on depends on the
type of transaction; however, wait always has the given setup
and hold times to the clock.
3. The maximum value for TdAS(DS) does not apply to InterruptAcknowledge Transactions.
4. The setup and hold times for WAIT to the clock must be met.
If WAIT is generated asychronously to the clock, it must be
synchronized before input to a bus master.
• Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
Except where otherwise stated, maximum rise and fall times for
inputs are 200 ns.
755
/
Memory and
Peripheral
Timing
STo-ST3,
O/W,ruW __________
J~++
EXTENDED
ADDRESS _ _ _ _ _- - '
________________________________________________
~'~----
-+______________
HH--------'l ' -__________________________
ADo-AD15
os
(READ)
os
(WRITE)
1.---------~GDr----------~1
Parameters 1-12 are common to all transactions.
110 Transaction
Timing
Cs ___~~~___~~~__________________________________
-'X'-________________--'X'-____
oiw _ _ _
ADO-AD15
.
)
.
®
13
DATA TO
BUS MASTER
ADDRESS FROM
BUS MASTER
-®j
f.-®-...
~
.
®
>---<
.j;
----®--
~®.-
ruW
/
(WRITE)
ruW
(READ)
J
t-®-I
I'
ADo-AD15
X
®
.1
\
DATA FROM BUS MASTER
k-----®---j
X
Interrupt
Aclmowledge
Timing
756
C8014-0183
C8014-0188
C8014-0192
No.
Symbol
Parameter
Min
All Transactions
TsCS(AS)
CS to AS I Setup Time
1
ThCS(AS)
CS to AS I Hold Time
2
TsS(AS)
Status to AS I Setup Time
3
4
ThS(DS)
Status to DS I Hold Time
5-TsA(AS) - - - Address to AS I Setup Time
ThA(AS)
Address to AS I Hold Time
6
7
TwAS
AS Low Width
TdDS(DR)
DS I to Read Data Not Valid Delay
8
TdDS(DRz)
DS I to Read Data Float Delay
9
lO-TdAS(DS)-- AS I to DS 1 Delay
TdDS(AS)
DS I to AS 1 Delay
11
ThDW(DS)
12
Write Data to DS I Hold Time
Memory Transactions
TdA(DR)
Address Required Valid to Read Data Valid Delay
13
TdAS(DR)
AS I to Read Valid Delay
14
15-TdAz(DSR) - - Address Float to DS (Read) 1 Delay
TdDSR(DR)
DS (Read) 1 to Read Data Valid Delay
16
DS (Read) Low Width
17
TwDSR
TdA(DS)
Address to DS 1 Setup
18
TwDSW
DS (Write) Low Width
19
TsDW(DSWf)
Write Data to DS (Write) 1 Setup Time
20
21-TsDW(DSWr)-Write Data to DS (Write) I Setup Time
1/0 Transactions
TdA(DR)
Address Required Valid to Read Data Valid Delay
22
TdAS(DR)
23
AS I to Read Data Valid Delay
DS (Va) 1 to Read Data Valid Delay
24
TdDSI(DR)
25
TdAz(DSI)
Address Float to DS (Va) 1 Delay
26-TdA(DSI)--Address to DS (Va) 1 Setup
27
TwDSI
DS (Va) Low Width
TsRWR(DSI)
28
RlYJ.. (Read) to DS (Va) 1 Setup Time
TsRWW(DSI)
RIW (Write) to DS (I/O) 'I Setup Time
29
TsDW(DSIf)
Write Data to DS (Va) 1 Setup Time
30
TsDW(DSlr)
31
Write Data to DS (I/O) I Setup Time
32-TdAS(W)--AS I to WAIT Valid Delay
TsIA(AS)
33
ThIA(AS)
34
TdAS(DSA)
35
TdDSA(DR)
36
37-TwDSA
TdAS(IEO)
38
TdIEIf(IEO)
39
TsIEI(DSA)
40
00·2031-02
0
60
20
55
30
50
70
0
6 MHz
Max
Min
Notes*t
0
40
0
40
10
30
50
1
1
2
1' 1
0
70
45
60 - 2 0 9 5 , - - 40
50
25
30
20
320
270
0
0
240
160
150
30
210
N
•
t'J
80
180
100
105
20
180
570
520
250
0
160
390
100
0
30
460
195
5-
255
170
110
Interrupt-Acknow ledge Transactions
INTACK to AS I Setup Time
0
INTACK to AS I Hold Time
250
AS I to DS (Acknowledge) 1 Delay
940
DS (Acknowledge) 1 to Read Delay Valid Delay
365
DS (Acknowledge) Low Width
475
AS 1 to IEO 1 Delay
IEI to lEO Delay
lEI to DS (Acknowledge) 1 Setup Time
NOTES:
I. Parameter does not apply to Interrupt Acknowledge Transactions.
2. Does not cover R/W for I/O Transactions.
3. Applies only to a peripheral which is pulling INT Low at the
beginning of the Interrupt Acknowledge Transaction.
4. These parameters are device dependent. The parameters for the
devices in any particular daisy chain must meet the following
constraint: for any two peripherals in the daisy chain,
TdAS(DSA) must be greater than the sum of TdAS(IEO) for the
4MHz
Max
c=
(ft
420
335
180
0
100
250
100
0
20
305
160
0
250
675
245
310
3,4
4
4
higher priority peripheral, and TdIEIf(IEO) for each peripheral
separating them in the daisy chain.
'
5. The maximum value for TdAS(DS) does not apply to Interrupt
Acknowledge Transactions .
• Timings are preliminary and subject to change.
t Units in nanoseconds (ns).
Except where otherwise stated, maximum rise and fall times for
inputs are 200 ns.
757
!18JI
~lIIlmU~ l!a«:n~plaD1l12
ilmlftC2)f(cc@numl~3::ft ~~sl~mm
Ji>ro annIlea
lIDes«!lriipftiicml
September 19S3
Features
[J
The bus structure for the SO's
[] Compatible with the Z-BUS Component
Interconnect system '
[] Designed for the powerful Zilog Family of
Microprocessors
o
o
o
o
Z8 CPU
Z80 CPU
[J
Designed-in reliability
o Byte-oriented parity and parity error line
o High reliability pin and socket connectors
o Distributed ground lines
o
High-current power distribution
o Terminated bus lines
r.----'
Z8000 CPU
I
8-, 16- or 32-bit operations
EXTENDED
I
Future microprocessors
o Flexibility in application
o
o
[J
PROCESSORS
za
zao
zaooo
Unsegmented, segmented, or memory
mapped systems
I
I
86
Future growth
o Allows 32-bit operations
o 5-bit status field
EXPANSION
MEMORY
PERIPHERAL
CONTROLLERS
I/O
ACCESSORIES
Description
The Z-BUS Backplane Interconnect (ZBI)
system is a high performance, applicationoriented system bus designed to utilize the full
capabilities of all Zilog. microprocessors-the
Z8, Z80 and Z8000.
Thirty-two address/data lines coupled with
twenty-eight control lines provide the
resources needed for growth paths to future,
more complex 32-bit microprocessors.
A member of the Z-BUS family of microcom-
puter bus structures, the ZEI bus is compatible
with the Z-BUS Component Interconnect (ZCI)
system used for communications at the chip
level between Zilog processors and their
peripheral support modules.
Reliability has been designed into the ZBI
structure: parity lines have been included;
ground lines are distributed between signals to
reduce noise; and all bus lines are terminated.
Functional
Description
Mechanical Configuration. The ZBI bus is
defined for three sizes of modular boards. The
single size modules measure 6.3" x 3.9" (160
mm x 100 mm). The double size boards are
6.3" x 9.2" (160 mm x 233.4 mm), and the
double extended size measure 11.0" x 9.2"
(280 mm x 233.4 mm). All ZBI boards are
consistent with the standard European form
factor.
The single size boards have a single bus
connector while the double boards have two
connectors.
The connector has a matrix of 96 pins on
.100" (2.54 mm) centers which are aligned in 3
rows of 32 pins each. A molded plastic housing
surrounds the pin array, providing mechanical
rigidity and protecting the pins from'
mechanical damage.
The backplanes use a similar style of mating
connector. These connectors are highly
reliable because connection surfaGes are completely enclosed and shielded from dirt and
dust when the connectors are mated. Another
advantage of this connector is its high density
which permits the design of compact boards.
In addition, the connectors are self-aligning
1003-001
759
Functional
Description
(Continued)
and keyed to prevent improper insertion.
All of the signals on the double boards are
assigned to one connector so that single
boards can be used in the same backplane
SINGLE
h
I/O SIGNALS
U.
1_ _ 3;~~7_1
1
6.300
160
1
with double boards. The second connector on
the double boards is unspecified and available
for use by the designer.
UNSPECiFIED .... ---/
I
DOUBLE
11.023
280
BI
EXTENDED
I/O SIGNALS
9.187
233.400
l0..
-=
1/0 SIGNALS
/1
~
9.187
233.400
Figure 2. The ZBI backplane accepts two sizes of boards: both are compatible with
European standards. The dimensions are in inches (upper) and millimeters (lower).
Signal
Description
The ZBI consists of 96 lines: 32 bidirectional
address/data lines with four parity lines, nine
interrupt lines, 28 control lines, 21 powersupply lines for ± 12 V, ±5 V and ground and
two reserve lines. The pin layout was defined
to provide the most convenient connection
from the board and the backplane, with signals
collected into logical groups for placement on
the connector.
Address and Data. The address/data group is
laid out to enable the lines to enter the board
in order on both two-layer and four-layer
boards. Low-order lines are placed next to the
power pins for easier routing through buffers.
The high-order address/data pins are positioned near the control pins to facilitate
decodjng of the state of the bus. Address and
data information is transmitted over 32 bidirectional lines with separate address and data
strobe lines arbitrating the informati9n flow.
The use of shared address/data lines enables a
compact connection while still allowing 32-bit
word sizes.
Word size is controlled by two lines that
indicate the data width of the current operation on the bus, making possible 8-bit, 16-bit
and 32-bit word transfers in the same system.
Data is aligned in the lower byte (ADo-AD7) of
the data field for 8-bit transfers, and the lower
word (ADo-AD15) for 16-bit transfers.
The ZBI includes four parity lines and an
error-indication line to detect errors in
memory devices and transmissions on the bus.
One parity bit is provided for each byte 6f the
32-bit address/data field, enabling paritychecking at· both the byte and word levels.
Control Signals. The ZBI bus has 28 lines that
are used for bus control and status, grouped
into the following categories:
•
760
Clocking. Two lines provide a master clock and a bus
clock. The master clock supplies a constant frequency
and is used as a master timing reference; the bus clock
is derived from the master.
• Extended processor architectures. Two lines enable the
CPU to interact with an Extended Processor Unit.
• Resource sharing. Three lines enable processors to
lock other processors off the bus. This is a software
implementation, and all processors must be aware of
these signals for the lockout to be effective.
• Direct memory access. Three lines provide the control
signals required for data to be transmitted in burst
mode across the bus. When a DMA device wants to
transmit information, it issues a request that causes the
processor to get off the bus. Once off the bus, the processor issues an acknowledge signal indicating that the
bus is free. The DMA device then begins transferring
data to the specified address. When the transfer is complete, the processor regains use of the bus.
• Muiltiprocessor. Four lines enable multiple processors
to share a common bus. (Arbitration logic to prevent
contention errors must be included on each module.)
• Data/Address Strobe. Two lines indicate whether
address or data information is on the address/data lines.
•
Status. Five lines designate the kind of transaction
occurring on the bus.
•
Word-size select. Two lines determine the word size of
the transaction on the bu~.
Interrupts. The ZBI bus has three independent
interrupt groups. Each group has an interrupt
request line and an interrupt enable input and
output daisy chain. A different priority level is'
assigned to each of the three interrupt groups
and position-dependent priority is assigned to
each device within the groups.
The treatment of the interrupt signal is
processor-dependent and can be maskable,
non-maskable, vectored, or non-vectored
depending upon the configuration of the.
system CPU.
Bus Conditioning. All bus lines are terminated in resistor pairs to provide the highest
integrity and best noise immunity for the
system. This forces all undriven lines to
approximately + 3 V.
1003,-002
Signal
Definition
Table 1 defines the signals necessary to the
2EI structure.
All signals, with the exception of the data
and address lines, are negative true signals,
where logical 1 = < 0.5 V and logical
o = > + 2.4 V. Any exceptioI1 to this standard is noted in the table. Naming conventions
are as follows:
NAME: a single line, n~gative-true logic level
NAMElINAME2: a doubly named line,
High/Low logic levels
The abbreviations used to describe signal
types are:
BD: Bidirectional data lines
TS: 3-state, undirectional lines
OC: Open collector
He; High-current driver line, not 3-state
NAME: a single line, positive.true logic level
NAME < 0.3>: 4 lines, positive-true logic level
DC: Daisy-chained Signal-OUT on one board
connects to IN of the next board
j"
Signal
Number
Signal
Name
of Lines
Type
Function
Address and Data Group - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BD
AD
32
Address and Data Lines. Address and data information is time-multiplexed onto
these lines. The times they are valid are defined by address strobe (AS) and data
strobe (DS). Additional information can be derived from the BCLK signal for syn"
chronous operation.
Parity Group
P
4
BD
PE
OC
Interrupt Group
INTI
OC
INT2
OC
INT3
OC
IEIl
IEOI
IEI2
IE02
IEI3
IE03
DC
DC
DC
DC
DC
DC
Control Group
PWRBAD
OC
Clocking
MCLK
BCLK
Parity-Check Bits. For bus transfer integrity, one parity bit is provided for each
byte of the 32-bit adqre~s/data bus. Even parity ensures that a read from a nonexistent resource will generate a parity fault.
Parity Error. Indicates to the Bus Master that a parity error in a data transfer on
the bus has been caught by the parity check logic.
Levell Interrupts. Highest priority interrupt in the system. If a non-maskable
interrupt is present, it must be here.
Level 2 Interrupt. Second highest priority interrupt in the system. If a vectored
interrupt is present, it must be here.
Level 3 Interrupt. Lowest priority interrupt in the system. If a non-vectored interrupt is present, it must be here.
Level'l Interrupt Enable In
Level 1 Interrupt Enabl Out
Level 2 Interrupt Enable In
Level 2 Interrupt Enable Out
Level 3 Interrupt Enable In
Level 3 Interrupt Enable Out
r
Power Bad, An early warning signal that the dc power for the system will soon
disappear. This signal is generated by the power supply to give the processor
enough t~me to store the machine state (if appropriate storage is available) before
power drops below critical levels.
----------------------~----------------------
HC
HC
Master ~fpfi:~' Sy:;tem plqster clock-16 to 32 MHz. Frequency is a 4 X multiple of
the desited1bus clock frequency.
Bus Clock. Bus transQcttl=))1 cloc~, derived from Master Clock and used by all synchronous elements in the system.
Extended Processing Architecture ------.,.-----r-r-----.,--------------------N/S
1
TS
Normal/;;y~.em. Indicates the mode of the CPU controlling the bus-Normal user
mad~.
Systepl mode (able to execute privileged instructions).
OC
Stop pne. Stop the processor in control of the bus for synchronization of activities
with the C:;PU,
or
Address/Data Strobes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AS
1
TS
Address Stj:'obe. Indicates that the AD lines contain a valid address. The AS line is
pulsed ~0':'f by a board controlling the transaction for program or data memory
acce~~! AQ~n~ss'fl1 pre vql~p at ~he trailing (rising) edge of AS.
Data Strobe, Data is placed on or accepted from the AD bus lines whe"n DS is low.
TS
Table 1. SignalO,pniHons
i
ipi
II'
761
Signal
Name
Status
ST<0:4>
Number
of Lines
Signal
Type
5
TS
Status Lines. These lines designate the type of transaction occurring on the bus.
S,
0
0
0
0
S3
0
0
0
0
~ SI
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
Function
So
0 0 0
0 0 1
0 1 0
0 1 1
0
0
1
1
0
0 0
0
1
0
1
0
Transaction
Internal Operation
Memory Refresh
VO Reference
Special VO
Reference
Segment Trap Ack
Intl Interrupt Ack
Int2 Interrupt Ack
Int3 Interrupt Ack
Data Memory
Request
Stack Memory
Request
0
0
0
0
0
0
0
0
0 0
0 1
1 0
0 1 1 1 1
1 X X X X
Data Mem < > EPU
transfer
Stack Mem < > EPU
transfer
Prog Ref - nth cycle
Prog Ref - 1st cycle
EPU <> CPU
transfer
Reserved
Reserved
~ord
Size Select----------------------------------------------------------------------------------1
TS
Byte/~ord Select. Used in conjunction with W/LW to define data access width.
~ord/Long ~ord Select. Used in conjunction with BIW to define the data access
TS
W/LW
width. (A logical 1 is a high voltage level.)
B/W W/LW
Access Width
1
1
Byte (8-bit}-Data on AD < 0:7>
o
1
Word (l6-bit}-Data on AD < 0: 15>
1
0
Double Word (32-bit}-Data on AD <0:31>
o
0
Reserved
BM
Resource Sharing
MMREQ
1
OC
MMAI
DC
MMAO
DC
Direct Memory Access
BAI
1
DC
BAO
DC
BUSREQ
OC
Multiprocessor
CAl
CAc5
CPUREQ
CAVAIL
Multimicro Request. This is a software request to another processor for software
synchronization.
Multimicro Acknowledge In. Forms the logical chain among processors to perform software arbitration, in conjunction with the MMAO signal. The effect of this
line is dependent on the software present on the processor board.
Multimicro Acknowledge Out. Completes the logical chain to the next processor's
MMAI pin.
Bus Acknowledge In From Priority Chain. This signal and BAO form the bus
priority chain.
Bus Acknowledge Out to Priority Chain. Completes the circuit to the next device
.
in the bus priority chain.
Bus Request. Used to request access to the bus. A request to a processor to relinquish the bus at the end of the current instruction cycle. This signal is used with
the BAI and BAO signals to control bus sharing by DMA devices not able to
become bus masters.
Control ---------------------------------------------------------------------1
DC
CPU Acknowledge In.
DC
CPU Acknowledge Out.
DC
CPU Request. A request to the processor currently in control of the bus to relin~h control at the end of the current instruction cycle. This signal is used with
CAl, CAO, and CAYAIL to control sharing of the bus by devices able to become
•
bus masters.
TS
CPU Available. Used in conjunction with CAl and CAO to transfer bus control
from one bus master to another.
Miscellaneous Control Lines - - - - - - - - - - - : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESET
1
OC
Reset. Connected to the master reset switch and power-up reset circuit.
WAIT
OC
Wait. Causes a processor or peripheral to wait for the response to a request for
data. Such a wait could be caused by slow memory or by refresh contention
problems.
RIW
TS
Read/~rite. 1£ this line is high, the current operation is a read; if low, a write.
Table 1. Signal Definitions (continued)
762
00·1003-01
BighaReliabilily
MAciOciii'CWliiQs
Military Specification
Standards·
Zilog
June 1982
General
Description
Zilog offers high-reliability versions of the
entire family of Z8, Z80, and Z8000 logic circuits, processed in accordance with the
requirements of MIL-STD-833 (Test Methods
and Procedures for Microelectronics). TheZ80
and Z8000 CPUs are currently Qualified Products, Level II MIL-M-3851O.
General Considerations. Zilog high-reliability
microcircuits are designed to meet the full
military temperature range of -55°C to
+ 125°C and are packaged in hermetic dualin-line packages. These packages can reliably
withstand the thermal shock requirements of
Test
Condition
Precap Visual
MIL-STD-833, method 1011, Condition C
(-65°C to + 150°C). For industrial users, Zilog
offers an extended operating temperature
range of-40°C to +85°C. All of Zilog's highreliability microcircuits receive 5004 processing in accordance with the requirements of
MIL-STD-833. Table 1 lists the screening tests
performed on the two levels. An X indicates
that the test is performed 100% of the time.
Additional screening options are available
upon request. Table 2 lists the Zilog products
available with the 100% testing process shown
with X's in Table 1.
MIL-STD-883
Method Condition
2010
B
Seal and Lot I.D.
Stabilization Bake
48 hrs.
@
150°C
1008
C
Class
B
C
X
X
X
X
X
X
Temperature Cycling
10 cycles
1010
C
X
X
Centrifuge
Yl Plane
2001
X
X
X
X
X
X
X
X
Fine Leak
1014
E
A
Gross Leak
1014
C
Electrical Test
Per Zilog Data Sheets
Burn-In
160 hr. + 8 - 0
Final Electrical
-55°C,
and + 125°C
External Visual
NOTES: S
= Sample testing only,
1015
160 hrs.
2009
X
X
X
X
X
X
X
X
= 100% testing.
Table 1. Total Lot Screening
763
III
G
~
II
=
CD
II
cr
J
, General
Description
(Continued)
Speed
883 Temp
Range
Extended
Temp Range
za611
8.0 MHz
Yes
Yes
za681
8.0 MHz
Yes
Yes
zao CPU
2.5 MHz
Yes
Yes
zaOA CPU
4.0 MHz
Yes
Yes
zao PIO
2.5 MHz
Yes
Yes
~OA
4.0 MHz
Yes
Yes
Yes
Product·
PIO
zao SIO
2.5 MHz
Yes
zaOA SIO
4.0 MHz
Yes
Yes
zao CTC
2.5 MHz
Yes
Yes
zaOA CTC
4.0 MHz
Yes
Yes
zaOOl CPU
4.0 MHz
Yes
Yes
zaOOlA CPU
6.0 MHz
Yes
Yes
za002 CPU
4.0 MHz
Yes
Yes
. za002A CPU
6.0 MHz
Yes
Yes
za030 Z-SCC
4.0 MHz
Yes
Yes
za030A Z-SCC
6.0 MHz
Yes
Yes
za036 CIO
4.0 MHz
Yes
Yes
za036A CIO
6.0 MHz
Yes
Yes
za038 Z-FIO
4.0 MHz
Yes
Yes
za038A Z-FIO
6.0 MHz
Yes
Yes
za530 SCC
4.0 MHz
Yes
Yes
za530A SCC
6.0 MHz
Yes
Yes
za536 CIO
4.0 MHz
Yes
Yes
za536A CIO
6.0 MHz
Yes
Yes
·;NOTE: See Ordering Information for package and temperature designators ..
Table 2. High.Rellablllty Products Available
Manufac- •
turing and
Process
Controls
Zilog high-reliability microcircuits will be
processed and assembled in accordance with
the, requirements of Appendix A of MILM-38510 or MIL STD 883, as specified by
.customer purchase order. The following are .
~ome of the items contained in the Zilog Product Assurance Program Plan:
• A clear, concise procedure for converting a
customer specification to a Zilog internal
specification,. assuring the customer that
parts received meet or exceed specified
requirements.
• A formalized training and testing program
for operators and inspection personnel to
ensure that each operation is performed
correctly.
II An inspection system that includes a com-
plete Incoming InspE/ctioI')., Laboratory and a
Chemical Analysis ,I:aboratory ensure' that
~/f"".r
764
all materials, utilities, and work-in-progress
meet Zilog requirements and specifications.
• Rigid requirements for the cleanliness of
work areas and the maintenance of a Class
100 environment at all stations where
critical operations are performed.
• ·A document control system to control
changes in deSign, materials, and processes.
• An instrument maintenance and calibration
program complying to the requirements of
MIL-STD-45662 (Calibration System
Requirements) .
• A quality audit system in accordance.
with MIL-I-45208 (Quality Program
Requirements) .
Zilog offers '1 number of standard flows,
which include both military and commercial
temperature ranges (see Table 3).
A
B
Bl
G
H
K
Q
S,E
M
M
S,E
S,E
S,E
M
C,D,L
C,D,L
C,D,L
D,P
C,D,L,P
P
C,L
Pre-Cap Visual
Method 2010,
Condition B
X
X
X
X
X
X
X
Stabilization Bake
Method 1008,
Condition C
X
X
X
X
X
X
X
Temperature Cycle
Method 1010,
Condition C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Environmental Flow
Temperature Range
Package
Centrifuge Method
2001, Condition E
(y, axis only)
Fine and Gross Leak
Method 1014,
Condition Fine A2
Gross C
100% Electrical Test
9-II
11:1
X
X
X
Burn-In Method 1015,
Condition D
X
X
X
X
X
100% Electrical Test
X
X
X
X
X
X
X
QA Test at Temperature
X
X
X
X
X
X
X
100% Electrical Test
X
X
X
X
X
X
X
Group B/C/D Generic
Data
X
=
=r
CD
X
III
X
e
q
X
Note: All test methods are per MIL-STD-883.
Table 3. Standard Flows
00-2027-03
765
Packaging·
information
Zilog
Pioneering the
Micro world
Zil©g'
September 1983
m:r::
Paclcage
Information
This table summarizes the microprocessor
components available from Zilog by number of
pins and package type. Following the table are
detailed drawings for each package type. For
further information on specific components,
see the Ordering Information section of each
product specification.
Pins
Pins
IQ
tlJ
~
IZJ
G
ii
Packago
Componont
18
Ceramic, Cerdip, Plastic
28581 CGC
28
Ceramic, Cerdip, Plastic
28430 280 CTC
28
Leadless Carrier, Ceramic
28430 280 CTC
40
Ceramic, Cerdip, Plastic
28002 28000 CPU
28030 28000 Z-SCC
28036 28000 Z-CIO
28038 28000 Z-FIO
28090 28000 Z-UPC
28400 280 CPU
28410 280 DMA
28420 280 PIO
28440 280 SIO/O
28441 280 SIO/l
28442 280 SIO/2
28449 280 SIO/9
28470 280 DART
28530 SCC
28536 CIO
28538 FlO
28590 UPC
2860128 MCU
2861128 MCU
2867128 MCU
2868128 MCU
40
Protopack
44
Packago
Leadless Carrier, Ceramic
G
Component
28002
28030
28036
28038
28400
28410
28420
28444
28530
28536
28000 CPU
28000 Z-SCC
28000 Z-CIO
28000 Z-FIO
280 CPU
280 DMA
280 PIO
280 SIO·
SCC
CIO
48
Ceramic, Plastic
2800128000 CPU
28010 28000 Z-MMU
52
Leadless Carrier, Ceramic
28010 28000 Z-MMU
2800128000 CPU
64
Ceramic, Plastic
28015 28000 Z-PMMU
281162800 MCU
28216 2800 MCU
2861228 DM
68
Leadless Carrier, Ceramic
2801528000 Z-PMMU
28070 APU
281162800 MCU
28216 2800 MCU
28612 Z8 DM
28093 28000 Z-UPC
28094 28000 Z-UPC
28593 UPC
28594 UPC
2860328 MCU
2861328 MCU
• NOTE: As a result of size of package, all three SIO versions are
Included In one version, the 28444.
769
[
...
0
-e
0
t1
Package
Information
(Continued)
18
10
IS-Pin Ceramic Package
0.320 __
MAX
"I
G~~+~ :~ :~:w: :~
A
MiL~
V
0.220
~
V
SEALING GLASS
~35
l.ooo MAX
0.125 - ::!: .015
MIN
BOTH ENDS
0.100
::!:.010
TYP
IS-Pin Cerdip Package
£~i~~A2i¥S~
o 300
r-0:320-1
B'
I-~:~~~--l
-.015
0.025
0.030
0.065~
:
:
:: :
:1
:
~0.920~
MAX
~ -11-- 0•040
0.130
Tr~J::£"'4''''
~
O.OO!!
0
. 0 1 5 ,I
0.050
::!:.015
t-
II
~r--
g:g~~
0.100--j
TYP
I
I Jj
r
0.125
MIN
IS-Pin Plastic Package
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
770
Paclcago
Information
28
15
(Continued)
PIN 1
IDENTIFICATION
14
0.185
lO.110
0.090
-
0.021
II'-0.015
20-Pln Coramlc Packago
G~!~~2_8LL~~-LLL~~ULLLLl~-ULL~~1~5-.
0.550
l'---r-T-r-T-r-r~~
.
r
AXL~
14
1,1.':1
o 230
'0.056
t1-1
.
'I
•
o
"'IN
'"
:J
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ENDS~I
0100 "AX
t+- B'OTH
0.040
:.020
I
0.100
t+-:.010
TYP
"
. .18
-+It+-:!:.003
TYP
20-Pln Cordlp Packago
28
15
14
0.100
TYP
0.018
0.050
: .003 TYP TYP
20-Pln Plastic Packago
771
Package
Information
40
21
(Continued)
PIN 1
IDENTIFICATION
20
~
~~
1~~:--1
,
".t'
LJ •.
1---0.600
REF
=.002
TYP
----l
5:
I'
MAX
2.02'
M
I
II
I
l
0.125
MIN
0.060
0.020
I
I
-l l
0.050
=.015 BOTH ENDS
0.100
=.010 TYP
--J L
0.018
=.003 TYP
40·Pin Ceramic Package
G~gt
21
40
0.550
l~~~~,.........,.,..
20
·
~o:~------------
om
....11.'
M~
lj ~ b~H'!~' bs
0.040
=.020
-I
~:f~ -I~±"Tgr,
40·Pin Cerdlp Packago
NOTE: Package dimensions are given In Inches. To convert to millimeters, multiply by 25.4.
772
Package
Information
40
21
T
(Continued)
0.555
:r:~~~=rrT~~n=rrTT~=nrr~~~n=rrTT,,=rrr~~
20
'~--------------------~~----------------------~"I
IJi:-=------H-------I~~O
r--------1
,~0.600~,
0.620
at~ =
)~
~
+0.009
I.
0.150
MAX
I
.1
0.650
r----0.610~
0
40-Pln Plastic Package
1. or
40
00
~~o 0
o
)to
0
MUMU
000000000 0
PIN1
J
1
-F
D~
o~
-
-
-
-
-
!o
~
-
I
~
- - - -
--~
2.020 MU
IDENTI FICATION
0.050:!: .020 ,
1.220MU
r
004gJ~~~g~~
0.300
MAX
-
0.010
-:!:.002
TYP
~OR~9t----.\
"'
..-.
r-0.5~~Q'--J
±.O~~
: 0.050:t.015 BOTH ENDS
~0.100:!:.010TYP
-I1-~'~J~3
TYP
1--------------------1~Ot
.
0.040+.007TYP
-.002
0.125
MIN
40-Pin Protopack Package
773
Package
Information
(Continued)
48
25
PIN 1
IDENTIFICATION
24
f
DO.O..
:!:.010
TYP
~~
~3! I'
r-~~I
tM
! !
!
1---0.600~
REF
I.-
0.125
MIN
0.060
0.020
0.050
:!:.025
'I
0.040
-J L
' BOTH ENDS
0.100
:!:.010 TYP
j
L
11.018
:!:.003 TYP
48-Pln Ceramic' Package
48
25
0.062
RADIUS
~___________________________ ~~~ ___________________________24~11
0.620
15°
0.01810.015
~o:SoO-----j
RA~P~~.Elk
~
= ~
0.015~
0.00, . I
r----0.610~
I.
0.650
0.155
'
,
:rrC'::::r---------:,----------------------'-----------------------.
o.tkE~:REF
MIN.
0....
0.060
·.
0.100
TYP.
Ilf
~0.040
0.060
48-Pin Plastic Package
NOTE: Package dimensions are given In Inches. To convert to millimeters, multiply by 25.4.
774
33
Package
Information
(Continued)
0.050R
.760
'~~I;:::==============~II
I'"
LL..L..-.T1
'9 -=-==-=-=~-=-=-=-==~~~~
.~
32
PIN 1
IDENTIFICATION
-~~ITP
~
-rt-~II-=':::::::::::::=2'42=5M=AX:::~~~~~::;:~~'I~
It-
.185 MAX ~
t
.125r'N
.095 MAX
060
t·])20
1-.750 REF-I
-:~~g
BOTH ENDS
64-Pin Ceramic Packago
64
1----------1.437----------+1
33
.062R
.1968 DIA X.003 DEEP
TOP EJECT PINS
.236 DIA X.003 DEEP
BOTTOM EJECT PINS
0.009
0.015
!--0.790:t:.010-!
1-------------2.170-------------J
64-Pin Plastic Package
775
Package
Information
(Continued)
-t -:1
~::~: !~: ~I-
0.399 SQ.
0.013
MAX.
1- ~~~
1_ O.~~:Q. -I
~ 11~19
O
METALIZATION~
ONE CORNER ONLY
~~~~ -
~
I
'.09' MAX.
~.02{
I~
x 45"
-
1 28
~
0.025 TYP.
28-Pin Leadless Package
_0.662 S Q . _
0.640 SQ.
lo.s~SQ_1
0.492 SQ.
1_
0.475 SQ.
0.469 SQ.
--I
FD=
-II
ij'
18
23
28
JL
_ _ 0.025
TYP
_
I
0.040 x 45"
TYP.3 REF.
0.058
0.042
~
44-Pin Leadless Package
NOTE: Package dimensions are given In Inches. To convert to millimeters. multiply by 25.4.
776
Package
Information
.750 :t .011 SO
(19.05 :t 0.28)
.
(Continued)
-------1...1
.075 :t .008
(1.91 :t 0.2)
~(1~~~Sa.
.015
(0.38)
Ir-(1!,:~ SQ·----·~I
I
I
.060
r--(1.27)
I
.050 TYP
'-(1.27)
•
.020 x 45°
III.- (0.51).
~
--'1
r-
(;~~) 45° TYP. 3
-eE---r--
;~~
TYP.
-~-
.050
_ _ _ (1.27) TYP. REF.
J
52-Pin Leadless Ceramic Package
777
/
Package
Information
(Continued)
~
.094
. (2.39)
.088
(1.88)
.800
(20.32)
.960
(24.38)
18
~
_ _ _ _ _ _ _ _ _ _ .960 _ _ _ _ _ _ _ _
..
(24.38)
I
__..1
.130
1(3.30)
~
JEDEC Type A Package
I....---------(~O~~~)
SQ.-------_~I
GUIDE BOSS
3 PLCS
¢
FRONT
1-'
-'-SOCKET
ORIENTATION PIN
Textool Carrier Socket
S8-Pin Leadless Ceramic Package
NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4.
778
Package
Information
(Continued)
STOP
ADs
M1
AD3
AD1S
AD2
AD14
AD1
+5V
Z8002
Z8004
NC
CPU
Vi
ClK
AS
RESERVED/ABORT"
NVI
NC
GND
NMI
BNi
RESET
Nis
Mo
RiW
= Z8004 Version
= No connection
Z8002/4 Leadless Package
CHAMFERED
CORNER
SN4
ADs
AD3
AD2
AD1
SN2
GND
elK
AS
RESERVED AlWRT"
BiW
N/S
RiW
NC
= Z8003 only
= No connection
Z8001/3 Loadless Package
779
Package
Information
(Continued)
BUSACK
AD27 (SNv
AD28 (SN3)
BRSTA.
+5V
SIP/BRST/ABORT
RiW
AD29 (SN4)
GND
AD30 (SNs)
Cs/AS
AD31 (SNs)
os
N/S
BUw
Bwi[
101
Z80~O APU
RESERVED
STo
1D0
ST1
INT
lEI
ST2
GND
·ST3
lEO
BSY
+5V
RESET
AD14
OPT 1
A D13
OPTo
ze070 APU LecuHe~. Package
As
A4
A3
A2
A1
Ao
GND
RFSH
M1
RESET
BUSREQ
NC .. No connection
ze400 zeo CPU Leadless Package
780
Package
Information
CHAMFERED
CORNER
~
(Continued)
~~
() () () ()
oS'
,;>
;
0
~
() () 'O~
'9" ~
r
6'
lEI
B/A
lEO
CID
AD
M1
+5V
GND
W/RDYA
Z8444
SYNCA
SIO
W/RDYB
SYNCB
RxDA
RxDB
RxCA
RxCB
TxCA
TxCB
TxDA
TxDB
()~~~~
~~~ ~1- ~~~~~()~
%()~Il'~~~~
NC
•
LV
= No connection
ft
W
W
G
Z8444 SIO Leadless Package
Ei
Q
~
-10
&:0
~~
'\
~ <'Il" ~
CHAMFERED
CORNER
e-...
~~~l,1-1-~~\<'o
0
Ao
00
ClK
0,
WR
02
AD
03
IORQ
04
Z8410
NC
GND
DMA
+5V
05
MREQ
Os
BAO
07
BAI
M1
BUSREQ
NC
~~~~~~1
r
v ., ; 0
~oS'
tt
~ ~()~ -10
~.1'
NC
= No connection
Z8410 DMA Leadless Package
781
Package
Information
CHAMFERED
CORNER
(Continued)
lID
[fJ
[ID
(ffi
Z8038
Z·F10
OJ
QJ
Do
01
02
03
04
NC
= No connection
Z8038 Z·FIO Leadless Packago
NC
ST2
ST3
ADa
ADs
Z8010
ZMMU
AD10
AD11
ClK
GND
AD12
AD13
AD14
AD15
NC
= No connection
Z8010 Z·MMU Leadless Package
782
Paclcago
Information
(Continued)
CHAMFERED
CORNER
~ 10 and the
first letter of the scre~n name. Table 1 explains the
screens and their functions.
Table 1. EMS Screen Descriptions
Screen
Function
Command (Menu·Driven) Screens
Allocation
Assigns EMS resources to specific tasks such as tracing and breakpOints.
Configuration
Allows various hardware controls to configure global features of EMS.
Pattern
Allows entry of recognized patterns.
Mapping
Substitutes EMS mappable memory for target memory.
Debug
, Examines and edits memory/registers, I/O, displays trace results, begins emulation, sets
software breakpoints, turns watch area on and off, uploads and downloads files to and
from the host computer, single/multiple steps through program execution.
Support Screens
Help
Lists global command controls and helpful reminders not listed in the above menu
screens. It can be displayed on all other screens by typing a .
Change
This is the intermediate step between two command screens and is entered by typing a
.
·UNIX is a trademark of Bell Laboratories,
792
HARDWARE DESCRIPTION
The EMS is a full-featured emulation peripheral. The
heart of the EMS is a Central Controller Unit (CCU) with a
4 MHz Z80, 256K of dynamic memory, and 16K of ROM.
The CCU contains the monitor program that provides a
screen-oriented user interface, and operates continuously to allow the user to monitor the progress of
emulation and breakpoints in real-time. The other EMS
modules include a two-board Trigger module, a real-time.
Trace module, an External Probe interface module, a
Mappable Memory module, and a microprocessor Personality module with a CPU Pod (Figure 2).
Figure 3 shows a fully configured EMS syster:n with the
following units:
II
EMS 8000
B
CPU Pod/cable assembly. The CPU Pod contains the
processor chip to be emulated plus the required interface circuitry. Pods are available for the Z8001 /3 and
Z8002.
EI ·64K mappable memory (standard).
62K mappable memory addition (optional).
c Host computer and user CRT terminal (required).
GI
The EMS uses dual-processor architecture to unburden
the emulating processor from the configuration chores
of the emulation system. (The Z80 CPU is used for EMS
configuration and monitor functions and the Z8000 CPU
for actual emulation.) This independence allows for improved debugging when unreliable target operation
occurs.
A 10 MHz Z8000 CPU is used to emulate the 6 MHz
maximum clock rate of the EMS to compensate for timing delays caused by buffering. The buffering p.rovides
better emulation control in problem targets and allows
mappable m~mory to override existing target memory.
Fast (90 ns) mapped memory allows emulation at 6 MHz
with no Wait states. (Wait states can be forced if desired
for compatibility with target memory.) Multilevel pattern
recognition resources can be allocated in complex sequential, logical, and enable/disable combinations to the
functions of trace qualifying and triggering, event counting, and timer modes. The counter/timer modes support
a long count of 48 bits (40 when time is displayed in
microseconds). This ensures adequate count capability
for analysis of human-related events in real time.
External probes (optional).
[] Target (the system being emulated).
TARGET SYSTEM
GENERATES CLOCK
(EMULATED PROCESSOR ENVIRONMENT)
TO
TERMINAL
CENTRAL CONTROLLER
SERIAL
TO HOST
COMPUTER
)
u."
COMMUNICATIONS
CHANNELS
INTERRUPT
TO BREAK
GROUP EMS's
DATA/ADDRESS READ·WRITE CONTROL
TRIGGER MODULE
TRACE BOARD 64X1 K
EMULATOR BOARD
RESOURCE A
RESOURCE B
RESOURCE C
MAPPABLE
MEMORY BOARDS
63 BLOCKS OF
2K BYTES
GENERAL PURPOSE
COUNTER
TIMING STROBES
SYNCHRONIZED TO EMULATED
Figure 2. EMS 8000 System Block Diagram
8216-006
793
SOFTWARE DESCRIPTION
The EMS can use ZEUS when the System 8000 is the
host computer. This total system provides a complex
hierarchical file structure that includes C, PLZ/SYS, a
Z8000 assembler, a compiler writing system, and a
general-purpose microprocessor. Because the EMS interfaces with Zilog computer systems, the user has access to powerful development tools for speeding up the
product development cycle. Software downloads to
either the ZEUS (UNIX) or RIO operating systems.
The EMS operating system is downloaded from a host
computer, allowing easy implementation of future upgrades to improve its effectiveness and applicability. The
hosts that can be configured with the EMS are:
EMS software is friendly and easy to use. The menu
prompt for each EMS screen reminds the user about the
type of data that is available or the options that are permitted. Error checking prevents the user from entering illegal states and allows graceful recovery from emulation
target problems (e.g., bad clock or power failure). Global
command keys allow the user to control the starting and
stopping of emulation, execution of command scripts,
and entering Transparent mode independently of the
command screens. A Help screen, which summarizes
global commands and command entry, is available to
help the user gain familiarity with EMS.
The terminals that can be configured with EMS 8000 are:
[J
Zilog System 8000
[] Vax UNIX
EJ PDP 11 UNIX
[] Zilog MCZ 1, MCZ 2, and ZDS 1/40
I:l ADM 31
IJ CITOH
[] Televideo 920
[] VT 100
IJ VTZ 2/10
TERMINAL
(ADM 31, CITOH,
Tel evideo 920, VT 100,
VTZ 2/10)
HOST
(MCZ·1, MCZ·2, PDP 11,
UNIX, Vax UNIX, ZDS
1140, Zilog System 8000)
EMS 8000
LOGIC ANALYZER
Do
o
CPU POD
'--r
EXTERNAL PROBE
TARGET SYSTEM
Figure 3. EMS 8000 System Configuration
794
00-2224'()1
8fZ3(ill@@TM
[ij)CY\70ilQ)~jjtIllGEUU ~vJ@uJ'ill!n@
VL?®@IJIl@n
ill)CDDQ;l1finnnil@[m
September 1983
Cl ZBOOI/Z8002 CPU Evaluation and
Debug Support
[;!
16K Words Dynamic RAM
(Expandable to 32K for User Code
Execution and Debug
, 0 32 Programmable I/O Lines
Cl EPROM Monitor and Debugger
o Transparent Operation Allows
Software Development without
Disconnection from CRT and Host
System
D RS-232C St~ndard Serial Interfaces
Compatible with Most CRT Terminals and Development Hosts
o Wire-wrap Area for Prototyping
OVERVIEW
The 28000 Development Module is a
complete, single-board microcomputer
that is used as a tool for the evaluation
and debug of 28000-based microprocessor systems. The Development
Module is used in the first stages of the
design and development process, not
only as a tool for evaluating 28000
microprocessor capabilities, but also as
an environment in which code can be
executed and debugged.
Evaluation. The Development Module
provides a ready-made environment in
which the user can execute software
unique to his 28000-based application,
evaluate the CPU's performance, and
then reach a realistic decision about its
suitability for a specific application.
Software Debug. In addition to use as
an evaluation,tool, the 28000 Development Module can be used to debug
and modify user code. For the software
designer, the Development Module is a
real 28000 environment in which he
can execute code and qarry out fairly
extensive debugging. For the hardware
designer; the Development Module is
an example of 28000 hardware design
which provides special hooks and wirewrap facilities to strap on additional
logic.
795
FUNCTIONAL DESCRIPTION
Z8000 code developed on a software
host may be downloaded serially to the
Development Module RAM area via a
serial port, and executed and debugged under EPROM monitor control.
Once the system is connected, no further disconnection is necessary as the
module has two serial ports (one connected to a host and the other connected to a CRT terminal). A simple
software command makes the development process transparent in the serial
path, thereby allowing direct communication between the host and terminal.
The serial RS-232C interfaces allow virtually any software development host
and CRT terminal to be used . .For
PROM-based code testing, the development module is self-contained and
can operate stand-alone with a CRT
terminal, since the host is only
required for storage of user code
on disk.
A variety of jumper areas and
switches permit the selection of clock
rates ranging from 2.5 to 3.9 MHz; the
use of 2708, 2716, or 2732 EPROMs;
the use of 4K or 16K RAMS; serial
interface to modem, terminal, or teletype; VO port addressing; and baudrate selection from 110 to 19200 baud.
Hardware. The 28000 Development
Module is available in two versions:
one supports the segmented 28001
microprocessor; the other supports the
non-segmented Z8002 microprocessor.
Z8001 Development Module. The
Z8001 Development Module consists of
a Z8001 CPU, 16K words of dynamic
RAM (expandable to 32K words), 4K
words of EPROM monitor (userexpandable to 8K words), a 280A SIO
providing dual serial ports, a 280A
CTC peripheral chip providing four
counter/timer channels, two Z80A PIO
devices providing 32 programmable
VO lines, and wire-wrap area for prototyping hardware.
za002 Development Module. The
28002 Development Module consists of
a 28002 CPU, 16K words of dynamic
RAM (expandable to 24K words), 2K
words of EPROM monitor (userexpandable to 8K words), a Z80A SIO
device providing dual serial ports, a
Z80A CTC peripheral device providing
four counter/timer channels, two 280A
PIO devices providing 32 programmable I/O lines, and wire-wrap area
for prototyping.
'
796
COMMAND
INTERPRETER
UPLOADI
DOWNLOAD
TERMINAL
HANDLER
DEBUGGER
Figure 1. Monitor Block Diagram
Software. The monitor software
(Figure 1) contained in EPROM (4K
words for the 28001 and 2K words for
the 28002) provides debugging commands, VO control and host interface.
It consIsts of a terminal handler, command interpreter, debugger and
upload!download handler.
ensures command validity and passes
to other software modules in the
monitor.
Terminal Handler. A Terminal Handler
provides interface to the console
device to facilitate output to a display
or printing mechanism and input from
a standard ASCII keyboard.
Upload/Download Handler. The
UploadIDownload Handler provides an
interface between the serial connection
and the host computer, the command
interpreter and the memory resources
of the 28002 Development Module. It
formats and interprets asynchronous
data streams to and from the host and
provides error checking and recovery
for the serial interface (see Figure 2).
Debugger. The Debugger provides a
basic set of debug commands to allow
the user to start and stop program execution, display and alter CPU
registers, flags or memory, and trap
instruction sequences.
Memory Organization. Tables 1 and 2
show the memory maps for tIte two versions of the Development Module. The
organization of ROM and RAM in.both
the segmented and nonsegmented
modes is indicated.
Command Interpreter. The Command
Interpreter scans console inputs,
,
/
ADDRESS
I I I
BYTE CHECK
COUNT SUM
I
I
CHECK C
SUM
R
DATA
I I I I
I I I I
I
Figure 2. Serial Data Format
1047-001,002
Segment 1
Segment 0
Address (Hex)
Memory
Address (Hex)
Memory
Address (Hex)
Memory
0000
Monitor
EPROM
0000
Monitor
EPROM
0000
3FFF
Expansion RAM
(User Installed)
4000
Unused
OFFF
1000
3FFF
4000
BFFF
COOO
FFFF
User EPROM
(User Installed)
IFFF
2000
User EPROM
(User Installed)
3FFFF
Standard
RAM
4000
49FF
Monitor RAM
(Scratchpad Area)
Expansion RAM
(User Installed)
4AOO
Standard RAM
BFFF
COOO
FFFF
Expansion RAM
(User Installed)
Table 1. ZaDD2 Development Module Memory Map
FFFF
Table 2. ZaDDl Development Module Memory Map
MONITOR COMMAND SUMMARY
The folloWing notation is used in the
command description:
< > Enclose descriptive names for the
quantities to be entered, and are
not actually entered as part of the
command.
[]
Denote optional entries in the command syntax.
Denotes "OR", ego WIB denotes that
either W or B may be used but not
simultaneously.
<
GO
IOPORT < address>
[WIB]
The following commands apply when
the 28001 monitor is used. All commands listed remain the same except
those that pe~it reference to segmented addresses as follows:
=
[ < segment number>] < offset
address>
< segment number> =
"<" < hex number in
7-bit range>">"
BREAK < address>
[]
Sets and clears a breakpoint at a
given memory address. The option
< n > allows specification of the
number of occurrences, where n is
from 1 to 128. The default is one.
COMPARE
Compares two blocks of memory
data beginning with the addresses
speCified for < n > bytes, where n
is from 1 to 128. Errors are
reported on the console device.
DISPLAY < address>
[LIWIB]
Displays and modifies memory for
< n > number of words or bytes.
The optionaf entry allows data to
be handled as bytes, words, or
long words. The default is words.
FILL < address 1 >
< address 2> < word>
Stores the < word> from memory
address i to and including
address 2.
Allows direct communications from
the console to a select~d I/O port.
A word (W) or a byte (B) may be
read from the selected port and a
word or byte. may be sent to the
selected port; default is byte.
JUMP < address>
Unconditional branch to the specified address. All registers are
restored prior to execution.
MOVE < address 1 >
Moves contents of a memory block
from source address < address 1 >
to destination address
for bytes.
NEXT[]
Executes the next < n > machine
instructions. may be from
1 to 128. ILn is omitted, 1 is
assumed.
PUNCH < address 1>
Punches a copy of memory from
address 1 to address 2 on paper
tape on the console device. Automatically turns on punch and a
null leader is created.
Upload/Download section
describes the tape format used.
QUIT
Places serial channels into transparent mode. The 28000 Development Module must be connected to
both the 2ilog host and the console
device, and the Development
Module acts as a message
switcher.
REGISTER
[ < register name> ]
Allows examination and modification of 28000 registers. 8-bit, 16-bit
or 32-bit quantities may be
selected by the appropriate
register-naming conventions.
TAPE
Loads memory from paper tape via
the console device. The
Upload/Download section
describes the tape format used.
Prompt sign for the nonsegmented
28002 monitor.
Prompt sign for the segmented
28001 monitor.
Begins program execution at the
address contained in the current
PC; execution is resumed where it
was last interrupted. All registers
are restored prior to execution.
797
t5
C
e."
Q
t;J
Q)
:=
ag
8.
e.e»
SPECIFICATIONS
Microprocessor
ZSOOI or ZS002 CPU
Clock Rate: 2.5 MHZ or 3.9 MHz
Memory
ROM: 2K or 4K Words (Expandable
to 8K Words)
RAM: 16K Words (Expandable
to 32K Words)
Input/Output
Parallel: 32 Lines (Two Z80A-PIOs)
Serial: Dua! RS-232C or RS-232C and
Current Loop (ZSOA-SIO)
Power
+5 V/ 3 A
+12 V/ 1 A
-12 V/ 0.2 A
Note
The user has access to all bus signals to allow
custom system expansion into the wire-wrap area
off·board.
Physical
Height
Interrupts
Maskable Vectored (256) / Maskable
Non-vectored, Non-maskable,
Segmentation Trap
ORDERIN~
Width
Depth
Weight
1.75 in. (4.5 em) Inclusive of
Standoffs
14.0 in. (35.6 em)
11.0 in. (27.9 em)
Approx. 30 oz. (850 gm)
INFORMATION.
Part No.
D&scription
05-6168-01
05-6101-01
05-6171-01
28001 Development Module
28002 Development Module
28001 Conversion Kit (converts 28002 Development Module into
28001 Development Module)
Systems recommended for use with the above:
Description
Prerequisi te
2DS-l Series Development Systems
28000 Software Development Package
PDS 8000 Series Development
Systems
28000 Software Development Package
System 8000 Family
28000 Software Development Package
798
OQ·1047'()2
18$ Developmemlft
Mo«BMXS
Zilog
Product
Description
September 1983
II Two 4K zas are used on the board:'
one as board manager and one fdr
emulation (without real-time trace)
or other user-defined configuration.
EI
4096 bytes of static RAM allow convenient creation and debugging of
user code .
I
.. On-board socket tests user code in a
2716 or 2732 EPROM.
CD
II Up to 4096 hardware breakpoints on
address compare cover the entire
internal ROM space.
13 Versatile monitor software allows
debugging, with- register/mET,mory
examination and manipulation, and
file upload and download. I
II ·"Transparent" operation allows
terminal- to-host communication
without disconnecting the'Development Module .
• Wire-wrap area for prototyping .
• za board management is operated at
7.3728 MHz for baud rate purposes.
The User za has switch-selectable 8
or liMHz crystals.
OVERVIEW
The za Development Module is a
Single-board microcomputer system
specifically designed to assist in the
development and evaluation of hardware and software designs based on the
28 microcomputer family. It allows the
user to build a prototype using the ~
prototyping deVice, thereby developing
code that will eventually be maskprogrammed into the 28 on-chip ROM.
Two 28 devices exist on the za
Development Module: the Monitor za
serves as a board controller, while the
User 28 is user-definable. All user
ports on the User za are uncommitted
and can be configured to suit any application.
Up to 4096 bytes of high-speed static
RAM are available to simulate internal
ROM. Also, an on-board EPROM
socket allows the user to substitute
EPROM for the ROM. This enables the
user to store the software without
building special hardware.
The EPROM-resident monitor software offers register and memory
manipulation, as well as a convenient
means to upload and download software between the host and user RAM
space. '
The Development Module connects
to the CRT terminal and host system
via two on-board RS-232-C serial ports;
this places the Development Module
between the CRT and host. A simple
command makes the Development
Module transparent in the serial path,
which allows software to be developed
on the host-resident assembler without
disconnecting the Development Module
from the CRT and host.
. The Development Module can
operate stand-alone for simple debugging operations, or it can interface
directly to a host system such as the
2ilog System 8000 for software development and file storage.
Fourteen square inches of wire-wrap
area with 5 V and ground points are
provided near the User 28 for prototyping.
799
FUNCTIONAL DESCRIPTION
Hardware. The two Z8 microcomputer
units (Monitor MCU and User MCU)
are at the heart of the Z8 Development
Module. The Monitor MCU controls
operation of the User MCU using the
monitor/debug software, which resides
in 4K bytes of EPROM. Hardware
breakpoint logic provides a maximum
of 4096 breakpoints. Single-stepping
with software trace capabilities is also
available.
The User MCU is controlled by the
Monitor MCU via internal address/data
and control lines brought out to exter-
nal pins. This effectively leaves all
ports on the User MCU unconfigured
and available for the user. The 4K
bytes of static RAM on the inte~nal bus
are reserved for code that is executed
by the User MCU. Execution is done in
real time at full processor speed.
In addition to the wire-wrap area, a
40-pin header (3M type 2395-1002) for
the User Z8 can connect to a ribbon
cable with a 40-pin plug, which will
then plug into a target system. Two
switches, Mode and Reset, provide a
means to re-enter the Monitor and to
reinitialize the system, respectively.
-The baud rate, from 110 to 19200, is
the same baud rate used for the terminal and host and is selected with an
on-board, four-element DIP switch.
Software. The monitor/debug program
includes debug, disassembly, input!
output, control, and host interface Cjommands. These commands are grouped
into four major functional blocks:
'
monitor, debug, manipulation, and file
commands (see the following command
list).
.
Z8 Development Module
Monitor Commands. This group of commands controls
execution of the User MCU, monitors user interrupts and
transfers control from the monitor to the host system.
GO
Causes User MCU to execute its
program and disallows further
debugging until a BREAK or
HALT command is encountered.
HALT
Halts program execution of the
User MCU.
QUIT
Returns control to the host system
and enters the "transparent" mode.
INTERRUPTS [E/D]
Enables or disables all usergenerated interrupts. Note: All
user interrupts are automatically
disabled when a breakpoint is
encountered. It is necessary to
reenable such interrupts with this
command.
800
Debug Commands. This group of commands allow~ the user
to debug code by tracing through code and setting breakpoints and jumps to specified locations within the "internal"
ROM space, which is simulated in 4K bytes of RAM.
BREAK < ADDRESS>
Sets a breakpoint at the specified .
address.
KILL [ < ADDRESS> ]
Clears the breakpoint at the
specified address.
JUMP
Allows the User MCU to jump to a
specified address anywhere within
the internal ROM space by changing the value of the Program
. Counter.
NEXT []
Causes execution of n instructions
of the ·User MCU and then halts
the User MCU.
TRACE
Causes single-step execution of the
User MCU. Every instruction
executed is output to the console.
~
'\r-
TRACE
STOP/GO
MONITOR
EPROM
I-CODE
REGISTERS
l~
2"':::...
USER
.............. ~
t-.
\
MONITOR DATA BUS
I
MONITOR
MCU
MONITOR
EPROM
BREAK
POINT
...::~
~
PROGRAM
COUNTER
ir
I
V
DATA
MUX
H
r:i
BUS
USER
MCU
RAM
ir
n
t-.
MONITOR ADDR BUS
V
ADDR
MUX
@
;L-
"k.
BUS
(
A
~
...
r
)
RS232C
PORTS
JJ.JJ.
TO CRT
TO HOST
Z8 Development Module Block Diagram
Manipulation Commands. The manipulation commands
display and alter registers and memory. This group can be
subdivided into two categories: register manipulation and
memory manipulation.
COMPARE
[ ]
Compares two blocks of user
memory data, one beginning at
ADDRESS 1 and the other at
ADDRESS 2 for n bytes.
Register Manipulation
ZAP[ < STARTING
ADDRESS> [ < n> 11
Disassembles' and displays code at
a specified starting address for a
specified number of bytes.
REGISTER [] [< NEW
REG VALUE>]
WORKING REGISTERS
Allows examination and modification of the Z8 internal registers.
Displays contents of the current 16
working registers.
File Commands. The file group enables the user to upload
and download programs to and from the host system.
PHILL < NUMBER
OF REGISTERS>
[]
Stores the sequence of DATA
BYTES into User MCU registers
beginning at the STARTING
REGISTER and continues for the
NUMBER OF REGISTERS
specified.
LOAD
Downloads a file to user memory
starting at the low address of the
file and continuing until the entire
file is transferred.
UPLOAD
< NUMBER OF BYTES>
[ < ENTRY ADDRESS>]
Creates a RIO file image of user
memory, beginning at ADDRESS
I, creating default length records,
and imaging memory for the
specified number of bytes.
Memory Manipulation
DISPLAY [ < STARTING Allows display and modification of
ADDRESS> [ 11
user memory contents for n
number of bytes.
SET
[]
Allows a sequence of data bytes
beginning at the ADDRESS specified to be written into user
memory.
FILL < STARTING
ADDRESS>
[]
Stores the sequence of DATA
BYTES into user memory beginning at the starting ADDRESS and
continues for the LENGTH
specified.
MOVE < SOURCE
ADDRESS>
< DESTINATION
ADDRESS> []
Moves contents of a user memory
block from a source address to a
destination address for a length
of n bytes.
1007-001
Note: The follOWing notation is used in the command description.
< > Enclose descriptive names for the
quantities to be entered, and are not
actually entered as part of the
command.
[]
Denote optional entries in the command syntax.
.
Denotes "or."
801
SPECIFICATIONS
Processor:
Two 64-pin DIP zas
Pin spacing Is 0,070
Row spacing Is 0.75
CPU Clock Frequency:
7.37 MHz for Monitor
8/12 MHz for User
Memory:
Monitor Z8
Scratch Pad RAM
RAM memory size: 1K bytes
RAM addressing: %2000 to %23FF
Minimum speed: 300 ns
EPROM
Word size: 8 bits
Memory size: 8K bytes'
Addressing: 0 to %FFF Internal
% 1000 to % IFFF external
Minimum speed: 350 ns
ORDERING INFORMATION
Part No.
05-6158-01
Description
Z8 Development Module
(2K). Includes one serial
interface ribbon cable
and reference manual.
05-6222-01
Z8 Development Module
(4K). Includes one serial
interface ribbon cable
and reference manual.
Systems recommended for use with above:
Description
System 8000
802
Prerequisites
Z8 Assembler
User Z8
RAM (EPROM equivalent)
Word size: 8 bits
Memory size: 4K bytes
Addressing: 0 to %FFF (relative to
User)
%9000 to %9FFF (relative'
to Monitor)
Minimum speed: 350 ns
Baud rate: Programmable to 110, 150,
300, 600, 1200, 2400, 4800,
19200 bps
Emulator cable length: 12 inches max.
Input/Output:
Monitor Z8
Baud rates: Programmable to 110, 150,
300, 600, 1200, 2400, 4800,
9600, 19200 bps
Connector type: Two 25-pin DB-25S
connectors
User Z8
Parallel interface: 32 110 lines undefined
Connector type: 40-pin PC edge
connector
Dimensions (LxW):
29.94 cm (11 in.) x 35.56 cm (l4Vl in.)
Power Requirements:
I.4Aat +5Vdc ±5%
Environmental:
o to 50°C (+ 32° to + 122°F)
Up to 90% humidity without condensation
Zilog
i>llo8iuacl
Brief
September 1983
FEATURES
CJ
[]
Portable, stand-alone, in-circuit
emulator (ICE) for lilog's
Universal Peripheral Controller
(UPC).
Emulates six versions of the
UPC: l8093, l8090, l8094,
l8590, l8593 and l8594.
[J
[]
Connects to the host and terminal via standard RS-232-C
interface.
Emulates loBUS and nonloBUS UPCs with either masked ROM or proto RAM/EPROM.
g
Single-step trace capability.
II
Monitor software allows file
upload and download, register
and memory manipulation.
OVERVIEW
The l-SCAN UPC is a simple and
cost-effective development tool
that emulates four versions of
'lilog's Universal Peripheral Controller (UPC)' As a portable incircuit emulator (ICE), the l-SCAN
U PC is an ideal tool for system
development from design through
manufacturing.
Both loBUS compatible and nonloBUS compatible types of UPC
are emulated by the l-SCAN UPC.
The loBUS compatible l-UPCs that
are emulated are the l8090 and
l8094. The non-loBUS compatible
UPCs that are emulated are the
l8590 and the l8594. Connection
with the host and a terminal is
accomplished via two RS-232-C interfaces.
By supporting eight popular terminal types and a wide variety of
hosts, the Z-SCAN UPC is easily integrated into most operating
environments.
803
FUNCTIONAL DESCRIPTION
The Z-SCAN UPC is physically
located between the host system
and the user's terminal, connected
via the RS-232-C interface. The
target cable connects directly to
the front of the Z·SCAN for safety
and convenience. The Z-SCAN
UPC can operate in stand~alone
mode for simple debugging opera, tions, or it can be placed in
transparent mode to allow software
development with the host.
Hardware
cluding three 1/0 port registers,
234 general-purpose registers, and
19 control, status, and special 110
registers.
..
Monitor commands control the
Z8 MCU to monitor interrupts
and transfer control from the
monitor to the host system.
Twenty-four pins can be dedicated
to 110 functions. These pins are
grouped logically into three eightline ports, which, can be configured
in various combinations as input or
output, with or without handshake,
and with push-pull or open-drain
outputs.
•
Debug commands allow tracing and jumps to user-specified
PROM locations.
III
Manipulation commands permit
display and alteration of
registers and memory.
II
File commands enable the user
to upload and download to and
from the host system.
Software
The Z-SCAN UPC contains both a
Z8 MCU and a UPC. The Z8 MCU
controls monitor functioning, including operational commands and
debug software. The UPC itself
features a 256-byte register file in-
The monitorldebug program
resides in 4096 bytes of PROM and
contains debug, 1/0, control, and
host interface commands. This
software is divided into four functional groups:
In addition, Z~SCAN UPC software
supports eight popular terminal
types and easily interfaces to a
wide variety of host systems.
Z·SCAN UPC
. . . . . - - - - - - - IN·CIRCUIT EMULATOR
(ICE)
TARGET BOARD
Figure 1. Stand·Alone Development System
804
00-2322-01
2322-001
ZmSCAN $
!!1® li:lmUuBsn@U'
Zilog
i¥'lrc«ilun ten
lJJ)esa:riipftu@DU
September 1983
II
Provides real-time emulation
capability for the family of Z8
Microcomputers.
f.'!I
Operates with Zilog systems
and other hosts; Z-SCAN 8
uses standard RS-232 links and
is compatible with many standard CRTs and software hosts.
This includes Zilog's S8000
systems, and others with user-
supplied load/save routines and
cross-software support.
(J
Hardware/software debugging
is fast and convenient. Two
screens display the status of
the Z-SCAN 8 monitor and Z8
target resources. Target m,emory can be displayed and modified in a scrollable window.
a
Fulfills the user's essential
real-time debugging needs with
its real-time trace, two complex breakpoints, single-step
capability, and four blocks of
mappable memory.
g
Interactive and easy to use.
Commands are selected from
menus; command arguments
are self-prompting.
OVERVIEW
The Z-SCAN 8 Emulator is a combination of hardware and software
that allows efficient,' interactive
emulation of the Z8 Microcomputer. By the Simple exchange of
target devices, the selected Z8
MCU can be emulated in a realistic
mode that allows user inspection
and control over the environment
being tested. Real-time trace, two
breakpoints, single-step capability,
and extensive mappable memory
ensure the user a tool that accurately simulates the anticipated
Z8 operating environment.
Z-SCAN 8 is an in-circuit emulator
deSigned specifically for Zilog's
Z8601 (2K), Z8611 (4K), and
Z8681182 (ROMless) Microcomputers. Z-SCAN 8 works with
Zilog's family of development·
hosts, interfacing via two RS-232
serial ports to the host and a CRT
terminal. A list of compatible CRT
terminals is provided in Table 1.
805
Table 1. Terminals Supported by the
Z·SCAN 8 Monitor
Table 2. Recommended Sources for Cross·Software
Manufacturer
Model
Source
Description
Zilog
System 8000*. Cross-assembler for Z8 and
Z8-UPC microcomputers.
Lear Siegler
ADM31
Televideo
TVI 912
TVI 920
Zentec
Zephyr
So roc
10120
10135
Beehive
Bee 100
Bee 107
Micro-B 1
DEC (any)
VT52
VT100
ANSI A3.64 or
ISO DP 6429
compatible
General Terminals,
Inc.
1-200
1-400
Hazeltine
1420
1500
Exec 80
Hewlett Packard
2620
2640
IBM
3101
Because it uses a standard serial
interface, Z-SCAN 8 can also be
use,d with virtually any software
host system that runs a crossassembler o'r cross-compiler
capable of generating Z8 code (see
Table 2). This means software can
be developed on many general-
1315 Dell Avenue
Campbell, CA 95008
(408) 370-8000
Third Party
Allen Ashley
395 Sierra Madre Villa
Pasadena, CA 91107
(213) 793-5748
ASMB-Z8*. Cross-assembler; operates with any
standard CP/M-based system.
System-Z8*. Cross-assembler; includes ASMBZ8 and text editor"operates with any standard
CP/M-Z80-based system.
Avocet Systems, Inc.
804 South State St.
Dover, DE 19901
(302) 734-0151
Z8 Cross-assembler (XASMZ8); operates with
CP/M-80, CP/M-86, and MOOS.
Microtec
P.O. Box 60337
Sunnyvale, CA 94088
(408) 733-2919
ASM Z8. Cross-assembler; operates with any
general-purpose mainframe (DEC, IBM, DG,
etc.) in FORTRAN ..
Relational Memory
Systems, Inc.
P.O. Box 6719
San Jose, CA 95150
ASM Z8*. Relocatable macro cross-assembler;
operates with Intel Intellec 800 and Series \I
microcomputer development systems.
·These Include the upload and download software for communicating.
, purpose computers. Only a simple
upload and download utility is
needed for operation since communication between the host
system and Z-SCAN 8 is through a
standard serial port using Tektronix
hex format. Once software has
been downloaded into the target,
Z-SCAN 8 can be disconnected
from the host and operated stand
alone. Transparent operation
allows the terminal to be used with
the host in such a way that
Z-SCAN 8 effectively disappears
from the terminal-to-host link,
without any physical re-cabling.
The Z-SCAN 8 can be substituted
for a Z8 microprocessor in any of
its configurations or operational
modes and can perform all the
functions of the processor. Additionally, the Z-SCAN 8 allows the
user to
m Inspect and display the condi-
FUNCTIONAl..
DESCRIPTION
The Z-SCAN 8 emulator is a compact, portable device that can be
used in,a wide variety of functional
configurations and applications. It
has been designed to ease debugging of both hardware and software, to integrate hardware and
software in Z8-based systems, and
to provide the user with a powerful
and versatile tool for the development of new systems and new applications for old systems.
806
II
Control any function or operation of the processor and its internal (and in some cases, external) hardware.
tion or status of internal
registers and CPU pins for up
to 1,024 machine cycles
preceding the breakpoint.
II
Execute a program or any
number of instructions in single
step mode.
a
Substitute up to 8K bytes of
RAM for external program or
data memory.
Z·SCAN a
I za BOARD
zaooo BOARD
n
~
L.::.:-I'
TERMINAL
t
DEBUG
SCREEN
RS·232
_r
MONITOR
PROGRAM
(EPROM)
L
t
r::l
L.:J
MONITOR
DATA
MEMORY
RS·232
HOST
W
BREAK·
POINT
LOGIC
TRACE
MEMORY
.1K x48
MAPPABLE
MEMORY
4x2K
BLOCK
CONFIGURATION
SCREEN
-I _l
I- t
I I I I I I I .J 4a BITS
EMULATOR
CABLE
I
I
ADDRESS
,
TEST
SYSTEM
;1;;
CONTROL 2
3
Flguro 1. Z·SCAN 8 Systom Block Diagram
Usor Interface, Z·SCAN 8 Com·
mand Screens
All communication between the
user and Z-SCAN 8 takes place
through the terminal. The format
consists of two selectable screen
menus: the Configuration menu
and the Debug menu. The operator
can manipulate each of these
primary menus to enable variations
for which the user can select a
particular set of conditions, such
as parameters and other variables,
for.user control during ~mulation.
Z-SCAN 8 executes two types of
commands: screen commands and
manipulation commands. The latter
are used to control the display on
the monitor and are normally executed by a control character or an
arrow key. Screen commands are
those used to define and control
the conditions of an emulation.
used for a specific emulation. It is
comprised of five submenus:
[J
Host
[J
Load
[J
Save
[J
Map
[J
Target
These submenus allow the user to
[J
Set the host serial-link baud
rate.
[J
Connect the user directly to
the host system, in effect, making the Z-SCAN 8 transparent.
[J
Download programs or data
from a host file.
[J
Allocate mappable memory in
the Z-SCAN 8.
[J
Inform the Z-SCAN 8 of target
configuration.
The Configuration Screen
The Configuration screen is primarily used to inform the Z-SCAN
80fcertain default values to be
8200·001
In practice, the Configuration
screen is seldom changed after Initial setup until some other type of
test or exercise is contemplated.
The Debug Screen
Because it controls those conditions most often changed, .the
Debug screen is the scr.een most
frequently entered during a series
of tests or emulations. The Debug
screen is comprised of five
submenus:
[J
Watch
13
Memory
'J!
Break
eXecute
&I
Display
The Watch command allows the
user to deSignate up to twelve
16-byte lines of memory for
display. This display is automat-
807
WE
1..-48 BITS~I
-1
MDS SYNC
I IIIII
HIG~~
6K BYTES
4 BITS
4 BITS
(NOT USED)
U'
1K
_
Os
~\(~
1
(I-===-::--~I--='~I--==--=
ADDRESS
I..-_ _ _...a
I CONTROL I
PORT
DATA
P~RT
3
Figure 2. Bit Significance, Trace Memory Word
ically updated to show any change
occurring in the section of memory
specified.
Breakpoints
Two complex breakpoints are
available in the Z-SCAN 8. Each
The Memory command is used to. , breakpQint can be pr.ogrammed independently to stop all processor
compare two blocks of memory, fill
a block of memory with a hexaactivity at some arbitrarily selected
point and save the state of the
decimal string, or move a block of
system in the trace memory for
memory to another range of adlater analysis. The breakpoints may
dresses.
specify a stop on address, on data,
The Break command is used to
or on a status such as an interrupt
define two complex breakpoints,
acknowledge. Or the breakpoint
which operate independently.
may specify that a pulse be
The Display command allows the
generated and sent to the BNC
user to specify what portion or
connector at the back of the
machine rather than stopping ,the
range of program, data, or register
memory is to be displayed on the
emulation.
screen.
Trace Memory
-The trace memory of the Z-SCAN 8
consists of a 48-bit by 1K block of
RAM that can be used by the
operator to record the condition
and status of certain elements of
the processor's environment for up·
to 1,024 machine cycles. The trace
memory can then be displayed and
the display used' to analyze an entire series of steps in a routine.
The bit significance of the 48-bit
trace memory word is shown in
Figure 2.
Mappable Memory
Mappable memory in the Z-SCAN 8
consists of four 2K blocks of highspeed static RAM. Each of the
blocks can be aSSigned independently to replace a section or
block of the target system's
memory. The block can be a~
signed anywhere in the Z8's
memory space and can be
specified to respond to program or
data memory or both. Mapping
must be done on 2K word boundaries only, and the entire block can
be write-protected. When a break
results from a write-protect violation, an error message appears on
the CRT.
SOFTWARE DESCRIPTION
The basic design of the Z-SCAN 8
software divides the emulator func_tions into two main tasks, the Net
Task and the Command Task. The
third major program module is the
Kernel, which performs the functions of an operating system.
The two systel'Jl tasks are written
in the C programming language. To
take advantage of the system of
pointers available in this language,
the system sofhA/are has made extensive use of tables that define
the collection of system commands.
INTERFACE TO NON·
ZILOG HOSTS
Load/save communication between
a Zilog (or other) host system and
the Z-SCAN 8 monitor is accomplished by exchanging
messages containing printable
ASCII characters. Message types
are:
11
808
•
Error text
•
Data block
All messages exchanged during a
Load or Save command are text
lines, each ending in RETURN (carriage return}. Memory and other
data are converted into hexadecimal numerals for transmission,
and the resultant message is
readable left-to-right, high-order
digit first, as it is transmitted over
the RS-232 link.
Single-character, data-block
acknowledgment
8200-002
Z-SCAN 8 SPECIFICATIONS
Processor:
Mappable Memory:
40-pin, 2K and 4K Z8 CPU
Clock Rate:
Internal to Z8000 board: 2.4 MHz
Emulation Frequency:
Up to 12 MHz
8K high-speed, static RAM assignable in 2K blocks
Broakpolnts:
Two com pies' breakpoint&: breakable
on data, address, or !nt~rruPt
acknowle~ge
I/O:
Two RS-232-C serial ports for ter, minal and host
Emulator Cable;
24 inches
Front Panel:
CRT Terinlnal:
Any standard CRT system, including
Zilog'8 S8000 systems.
Baud Rato:
Terminal:
TARGET RESET and ~ONITOR RESET switches, POWER O~ indicator,
40-pin connec;:tor type,
Rear Panel:
9600
Host:
Determined by user selection from
300 to 38,000
BNC connector for pulse output,
standard LS-TTL level 2 x 25 pin connectors, 3M type '3483 (terminal and
host), 3-pin power connector,
1 ~ in., fuseholder (screwdriver release type), POWER ON switch
rocker type), 115/220 voltage selection switch (sliding type)
Power:
180-264 volts ac or 90-130 volts ac,
switch selectable; 47-63 Hz; 2 amp
maximum
Dlmen~lons:
4 inch!3s x 17.5 inches x 14.5 inches
(HWD); 10.2 centimeters x 44.5 centimeters x 36.8 centimeters
Environment:
1Qoe to 50 e (operating)
0
Unit Weight:
25 pounds
.-a .. ,¢.... ''''o,,''''-. .... ·.·...
ORDERING INFORMATION
Part No.
Description
05-0144-00
Z-SCAN 8 Emulator
809
Z-SCAN 800
Z80C™ :;:iiiiila~oi
Product
Description
Zilog
'iSeptember 1983
INTRODUCTION
The Z-SCAN 800 is a low-cost
Z800™ M PU development system
designed to facilitate the integrated
hardware and software development of Z800-based systems. The
Z-SCAN 800 represents the logical
choice for Z800 development, and
offers Z80~ CPU system developersthe ideal window to the
future.
Based on Zilog's 16-bit Z8000™
CPU and connected via two RS232-C compatible ports, the
Z-SCAN 800 (Figure 1) offers incircuit emulation (ICE) in a standalone mode or in a hosted multiuser configuration, using any of
several common terminals and
various host development systems.
The stand-alone mode is especially
useful in manufacturing environments as it provides simple
testing and debugging for PROMbased target systems. Configured
with a host, the Z-SCAN 800
becomes transparent, lending itself
to the development of high-level
software.
H {'P!.~
....,
'1<
;
j;)%t
"
; ~
l
'
~
~
Figure 1. Z·SCAN 800
811
Z·SCAN software offers similar
flexibility. The user at a terminal
has a choice of screens to view,
and each screen offers a variety of
options to enable the user to focus
on specific needs. Real·time
emulation, extensive trace capabil·
ity, user·defined breakpoints, and a
MULTI·USER DEVELOPMENT
SYSTEM WITH HOST
RS 232
INTERFACE
STAND·ALONE DEVELOPMENT
SYSTEM
I·SCAN 800
IN CIRCUIT
EMULATOR
(ICE)
TARGET
BOARD
Figure 2. Z·SCAN 800 Environment
812
large mappable memory help main·
tain the Zilog tradition of advanced,
friendly development systems.
Figure 2 illustrates the Z·SCAN 800
environment.
Z800 EMULATION
The Z-SCAN 800 emulates all four
versions of the Z800 MpU. These
four versions are the Z8108,
Z8208, Z8116, and Z8216. All
Z800s are binary-code compatible
with the Z80, and incorporate advanced architectural features such
as dual mode (User/System) operation, on-chip peripherals, and
memory management.
The Z8108/8208 MPUs are
characterized by an 8-bit, Z80-type
bus. The Z8108, a 40-pin package,
includes on-chip the Z800-standard
Memory Management Unit (MMU),
clock oscillator, and refresh controller. The Z8208, a 64-pin
package, additionally includes four
24-bit Direct Memory Access
(DMA) channels, four 16-bit
counter/timers, and a full-duplex
UART to facilitate asynchronous
serial communication.
The Z8116/8216 MPUs operate on
the 16-bit Z-BUS@ . As with the
Z8108/8208 CPUs, the Z8116 contains the advanced features standard to the Z800s and the Z8216
includes the additional on-chip
peripherals.
Regardless of the package type,
the Z-SCAN 800 traces all address,
data, status, and control signals on
Z800 pins for development with
any Z800 MPU.
MAPPABLE MEMORY
N
In addition to providing MPU
emulation during system development, the Z-SCAN 800 also
emulates user-board ROM by providing 64K bytes of static RAM.
This RAM may be divided in up to
eight blocks of 8K bytes each and
is mappable on any 4K byte bound-
ary. A special write-protection
feature can be individually applied
to any combination of the eight
blocks, providing a safe and accurate representation of system
ROM.
The system developer can use the
mappable memory as a complete
substitute for eventual on-board
ROM, or as a partial supplement to
existing ROM. This supplement
may represent additional ROM
under development or even "throw
away" ROM to be used only during
debugging.
SCREEN·ORIENTED
DISPLAY
The screen-oriented display is one
example of the user-friendly software of the Z-SCAN 800. The
screen-oriented approach frees the
user from the need to remember
all the possible commands
because the options are listed, and
it eliminates time-consuming and
error-producing keystrokes by requiring only cursor placement for
selection. A first-time user can effectively learn the Z-SCAN 800 ina
few hours by-interacting with the
terminal display. The user chooses
between two screens: the· Debug
Screen and the Configuration
Screen.
Debug Screen
The Debug screen acts as a "window" into the target. The user can
configure the screen to display
preformatted presentations of
target resources such as special-
Configuration Screen
The Configuration screen provides
multiple options regarding the setup of mappable memory. This
screen contains information less
frequently used during the debugging phase, such as baud rates
and target characteristics.
Table 1. Z·SCAN aoo Interface
Protocols
INTERFACE PROTOCOLS
Z-SCAN 800 is provided with protocols to permit uploading and
downloading with many host computer systems. Protocols are provided for the Z800 family running
under several operating systems
as shown in Table 1. These standard protocols allow system
purpose and general-purpose
registers; target memory can be
displayed in scrollable fashion.
developers to use their current
hardware configuration as a host
for Z-SCAN development work. In
addition, protocols are provided to
allow Z-SCAN 800 to interface with
such popular terminals as
ADM-31 s, Hazeltine, HP and many
more.
Host Operating
System
zaoo Mode
Apple
CP/M
Intel MDS
System 8000, ZEUS
Vf\)(, UNIX*
Special
ELOAD-binary
ELOAD-binary
ELOAD·binary
ELOAD·binary
Protocol
·UNIX is a registered trademark of Western Electric
813
•
QPl
n
~
=flO
8
BREAKPOINTS
The Z-SCAN 800 provides two
complex hardware breakpoints and
fifteen software breakpoints. The
two hardware breakpoints permit
the user to break on address, data,
and control signals, and can cause
breaks on specific combinations of
conditions. The additional software
breakpoints contribute to making
debugging a relatively simple task.
Additionally, the Z-SCAN 800 incorporates a break-in/break-out
feature, extremely useful in a Local
Area Network (LAN) debugging
situation. Break-in and break-out
pulses allow simultaneous breaking
within a multiple Z-SCAN environment. The break-in signal may
come from an external source or it
may originate in a previously set
hardware breakpoint within a
Z-SCAN 800.
TRACE
Another invaluable tool for debugging is the trace feature. Trace
records up to 64-bits of data on up
to 1000 events, creating clear
histories. of Z800 signal states.
Finally, a disassembler provides
the user with easily recognizable
mnemonics to interpret results.
And the Z-SCAN 800 is an exceptional value. It comes at a very low
cost and includes a pod to ensure
reliable results even with high frequencies and long cables. The
Z-SCAN 800 is fully UUCSA approved.
·UNIX is a trademark of Bell Laboratories. Zilog is
licensed by AT&T.
814
00-2261.()1
Z8000™ Emulator
!gSCAtJ 8000
Zilog
Product
Description
September 1983
iii Provides Real Time Emulation up
II Transparent Operation Permits
to" MHz of tho Z8DDI and Z8002
CPUs.
iii Two RS-232C Serial Ports Make It
a Peripheral Usable with MQst
Standard CRTs and Software
Hosts.
Direct Communication Between
CRT and Host without Physical
Disconnect.
C Highly Interactive. ScreenOrientod User Interface Makos
Z-SCAN Easy To Use.
II Shadow Monltor Removes All
Restrictions on Targot Syntom
Memory Space. Makin!} It Fully
Available To the User.
m High-Speed Mappable Memory
(no wait states) Is Avallablo to
,Simulate Target System
RAM/ROM.
'OVERVIEW
The Z-SCAN 8000 Emulator is an incircuit emulator that has been designed
as a peripheral unit for Zilog's Z8001
and Z8002 16-bit microprocessors.
InterfaCing via two RS-232C Serial
ports to host and CRT terminal,
Z-SCAN 8000 can work with Zilog's
family of development hosts.
Because it employs a standard serial
interface, Z-SCAN 8000 can also be
used with Virtually any software host
system that runs a cross assembler or
cross compiler capable of generating
Z8000 code. Communication between
the host system and Z-SCAN 8000 is
with a standard serial format requiring
only a simple upload and download
utility to operate. For PROM-based
target systems, Z-SCAN can operate
stand-alone with' a CRT terminal
because the monitor and debug software is EPROM-resident:
In keeping with Zilog's design
philosophy of separating a development system into two identifiable units
(the software host and an emulation
peripheral), Z-SCAN 8000 fits into
three scenarios, making it a highly versatile unit:
II As a periph~ral to Zilog's PDS 8000,
ZDS-1, or System 8000, Z-SCAN
8000 completes the development
support package for the' Z8001 and
Z8002 microprocessors available
from Zilog.
II As a peripheral to any development
host with the capability of compiling
or assembling Z8000 code, Z-SCAN
8000 allows a low-cost emulation
capability which precludes substantial reinvestment in a software host
system.
I! As a stand-alone in-circuit emulator
that can operate with ~ost CRT
terminals, Z-SCAN 8000 provides
simple testing and debugging
capability for PROM-based target'
systems.
815
SYSTEM FEATURES
User Interface. Z-SCAN SOOO incorporates the use of a two-dimensional
screen-oriented user interface which
'makes it easy to use. Because it is
general-purpose in nature, the user
interface does not require a customized
CRT terminal to operate. The only
requirements are that the CRT terminal
have screen erase, line erase, and cursor addressing capability.
The objective of the user interface is
to provide a screen format with a
menu-like approach, which directs the
user through the operation of the emulator. The user is aware at all times of
where he/she is in the debug process
because Z-SCAN 8000 provides the
CRT information about system parameters, system resources, current
execution, and error messages. When
the system is turned on, a bootstrap
routine produces a display informing
the user of the unit's configuration and
requesting the user to define set-up
parameters. A menu of display choices
shows the user the different capabilities
of the system:
• The Memory/I/O command display
shows the various memory and I/O
manipulation commands which
access the target system.
• The Resources display presents the
user with the full complement of
arguments applicable to emulation
of the target system~
• The Execution display shows all the
commands and parameters necessary to cause emulation to take
place.
At all times, execution of specific
Monitor commands is possible, and
information on other relevant system
parameters and resources is always displayed. This highly interactive user
interface makes it possible to usa
Z-SCAN 8000 without frequent
reference to the operating manual.
Shadow Memory. Z-SCAN 8000 is a
single, CPU-based systepl that can be
configured to emulate either the 28001
or Z8002 by simply exchanging the
CPU, monitor EPROM, and the
emulator cable.
Although the system uses a single
CPU for both monitor and emulation
functions, no restrictions are placed on
the target system memory size. This is
because the entire monitor resides in
shadow memory and, therefore, does
not appear in the target system memory
space. This feature also provides the
benefit of making future system expansion possible without any hardware
redesign. '
816
ADDRESS/DATA
BUS
ADDRESS/DATA
COMPARATORS
SEGMENT
COMPARATORS
STATUS
COMPARATORS
DON'T
CARE
INSTRUCTION
FETCH
DETECT
COUNTER
MATCH
COUNTER
Figure 1. Hardware Trigger Implementation
Hardware Trigger. Z-SCAN 8000
offers the capability of setting breakpoints in three different fields or in a
combination of these fields. These are
the Address/Data Field, the Segme.nt
Field, and the ControVStatus Field. A
Pass Counter can be set up to a maximum of 255 counts to allow multiple
pass triggering. In addition, Z-SCAN
8000 may also be set to break on
instruction fetches only (single-step
execution), or, by using a Pass
Counter, may be set up to a maximum
of 247 counts to allqw triggering on
multiple instruction 'fetches (multi-step
execution) .
With these two capabilities, a breakpoint argument can be set up which is
on ORed condition allowing for either
a break-on-field (or combination of
fields) argument or for "n" instruction
fetches, whichever occurs first. This
ORed situation is convenient when
tracing through a program in search of
a'specific occurrence. A pulse output,
providing a trigger pulse on breakpoint match condition is available on
the rear panel to trigger auxiliary test
instrumentation.
Mappable Memory. Z-SCAN 8000
offers a 4K work block of high-speed
static RAM. This block is available to
the user to simulate a target system
memory block which would typically
be ROM. No Wait states are required
at 4 MHz. This block is mappable
anywhere in the 28001 and 28002
address space and can be speCified to
be Normal Code, Normal Data, Normal
Stack, System Code, System Data,
System Stack, -or Space Independent.
Mapping must be done on 4K word
boundaries only, and the entire block
can be write protected against illegal
writes to cause system emulation either
to break on such occurrences or continue emulation. An error message
appears on the CRT display informing
the user of an illegal write.
Software Trace. Z-SCAN 8000 bffers a
software trace feature which provides
insight into target system activity and
CPU resources. In the Trace Mode, the
system displays the address of the
instruction being executed and the
contents of the CPU registers (both
general-purpose and control) consecutively, covering one full screen
format.
For example, displaying the CPU
registers associated with every instruction executed just prior to executing a
Break is tremendously useful to the
user during debug of target system
activity.
1041-001
SPECIFICATIONS
CPU
28001 or 28002 per configuration
Clock Rato
500 kHz-4.0 MHz (external)
110
Two RS-232C Serial Ports for CRT and
host
Baud Rato
Automatically selected from 50 to 19.2K
Breakpoint
Address, Data, Segment and Address,
Control, Address and Control, Data and
Control, Segment and Address and
Control, Instruction Fetch, OR combination of Instruction Fetch and any Field
argument
Mappablo Momory
4096 X 16 Static RAM (no Wait states at
4 MHz while operating off User clock)
Front Panol
Target/Monitor, Reset, and NMI toggle
switches
Inputs
One standard LS-TTL load plus 30 pF
maximum
Power
Outputs
Capable of driving one standard LS-TTL
load plus 30 pF preload
Dimensions
4 in. (10.2 cm) (H) X 14Y2 in. (36.8 cm)
(W) X 18 in. (45.7 cm) (D)
Rear Panol Output
ENC connector for pulse output, standard
LS-TTL
Emulator Cablo
12 inches
110/220 Vac, 50/60 Hz switch selectable,
60 VA maximum
~
AC CHARACTERISTICS
m
Numb:::
Symbol
ZCOO1l2
Paramoter
Min{nu)
Max{ns)
n
Z-SC1Ui
Min{ns)
1 TcC
Clock Cycle Time
250
2000
250
2 TwCh
Clock Width (High)
105
2000
105
3 TwCl
Clock Width (Low)
105
2000
105
4 TfC
Clock Fall Time
20
5- TrC
Clock Rise T i m e - - - - - - - - - - - - - - - - - - - 20
6 TdC(SNv)
Clock t to Segment Number Valid (50 pF load)
130
. Clock t to Segment Number Not Valid
7 TdC(SNn)
20
35
8 TdC(Bz)
Clock t to Bus Float
65
9 TdC(A)
Clock t to Address Valid
100
10- TdC(Az)---Clock t to Address Float - - - - - - - - - - - - - - - 65
11
TdA(DI)
Address Valid to Data In Required Valid
455
383
12 TsDI(C)
Data In to Clock , Setup Time
50
76
13 TdDS(A)
DS t to Address Active
80
-4
14 TdC(DO)
Clock t to Data Out Valid
100
15- ThDI(DS)--- Data In to DS t Hold Time - - - - - - - - - - - 0
-20
16 TdDO(DS)
Data Out Valid to DS t Delay
295
269
17 TdA(MR)
Address Valid to MREQ , Delay
55
29
18 TdC(MR)
Clock' to MREQ , Delay
80
MREQ Width (High)
210
19a TwMRh
193
19b-TwMRh
MREQ Width (High) During Monitor O p e r a t i o n - - - - - - - - - - - - - 184
20 TdMR(A)
MREQ , to Address Not Active
70
53
21
TdDO(DSW)
Data Out Valid to DS , (Write) Delay
55
59
MREQ' to Data In Required Valid
350
22 TdMR(DI)
287
Clock' MREQ t Delay
23 TdC(MR)
80
24-TdC(ASf)--Clock t to AS J D e l a y - - - - - - - - - - - - - - - - 80
25 TdA(AS)
Address Valid to AS t Delay
55
29
Clock' to AS t Delay
26 TdC(ASr)
90
AS t to Data In Required Valid
27 TdAS(DI)
340
277
DS t to AS , Delay
28 TdDS(A~)
70
53
29-TwAS
AS Width ( L o w ) - - - - - - - - - - - - - 70
53
30 TdAS(A)
AS t to Address Not Active Delay
60
43
31
TdAz(DSR)
Address Float to DS (Read) , Delay
0
-41
Max{ns)
2000
2000
2000
20
20175
165
163
154-
163
143
134
134144
4
--------------------------------CONTINUED ON NEXT PAGE-----------------------------
817
~
Z
00
"e
C
AC CHARACTERISTICS
Number
Symbol
Z8001/2
Max (ns)
Min(ns)
Parameter
32 TdAS(DSR)
AS t to DS (Read) 1 Delay
70
33 TdDSR(DI)
DS (Read) .!...!.O Data In Required Valid
185
34 TdC(DSr)
Clock 1 to DS t Delay
35 TdDS(DO)
DS t to Data Out and STATUS Not Valid
75
36-TdA(DSR) - - Address Valid to DS (Read) 1 Delay
180
37 TdC(DSR)
Clock t to DS (Read) 1 Delay
38 TwDSR
DS (Read) Width (Low)
275
Clock 1 to DS (Write) 1 Delay
39 TdC(DSW)
40 TwDSW
DS (Write) Width (Low)
185
41-TdDSI(DI)-- DS (lnput)..!J.o Data In Required Valid
320
42 TdC(DSf)
Clock 1 to DS (I/O) 1 ,Delay
43 TwDS
DS (I/O) Width (Low)
410
AS t to DS (Acknowledge) 1 Delay
44 TdAS(DSA)
1065
45 TdC(DSA)
Clock t to DS (Acknowledge) 1 Delay
46-TdDSA(DI)-- DS (Acknowledge) 1 to Data In Required Delay---435
TdC(S)
47
Clock t to Status Valid Delay
48 TdS(AS)
Status Valid fa AS t Delay
60
49
TsR(C)
RESET to Clock t Setup Time
180
ThR(C)
50
RESET to Clock t Hold Time
0
51-TwNMI
NMI Width (Low)
100
52 TsNMI(C)
NMI~Clock t Setup Time
140
53 TsVI(C)
VI, NVI to Clock t Setup Time
110
54 ThVI(C)
VI, NVI to Clock t Hold Time
0
55 TsSGT(C)
SEGT to Clock t Setup Time
70
56-ThSGT(C)-- SEGT to Clock t Hold Time
0
TsMI(C)
57
MI to Clock t Setup Time
180
58 ThMI(C)
MI to Clock t Hold Time
0
59 TdC(MO)
Clock t to MO Delay
60 TsSTP(C)
STOP to Clock 1 Setup Time
140
61-ThSTP(C)--.STOP to Clock 1 Hold Time
0
62 TsWT(C)
WAIT to Clock 1 Setup Time
50
ThWT(C)
63
WAIT to Clock 1 Hold Time
10
TsBRQ(C)
64
BUSREQ to Clock t Setup Time
90
ThBRQ(C)
65
BUSREQ to Clock t Hold Time
10
66-TdC(BAKr)--Clock t to BUSACK t Delay
67
TdC(BAKf)
Clock t to BUSACK 1 Delay
Z-SCAN
Max (ns)
Mln(ns)
53
122
65
70
58
154
174
120
258
149
95
168
266
, 120
174
393
1048
174
120
381
162
110
45
208
15
116
154
118
22
78
22
188
22
165
120
148
22·
78
25
98
32
100
100
145-145
ORDERING INFORMATION
Part No.
Description
05-0100-00
Z-SCAN 8000/1 Emulator
Description
Prerequh;i tes
(Supports Z8001 Emulation and Control)
ZDS-l Series Development Systems
zaooo SDP
PDS 8000 Series Development
Systems
Z8000 SDP
System BOOO Family
zaooo SDP
05-0100-01
Z-SCANBOOO/2 Emulator
(Supports Z8002 Emulation and Control)
05-0101-00
Z8001 Field Support Kit
(Converts Z-SCAN
BOOO/2 into Z-SCAN
BOOO/1)
05-0102-00
Z8002 Field Support Kit
(Converts Z-SCAN
BOOOIl into Z-SCAN
BOOO/2)
05-0103-01
Z-SCAN BOOO Emulator
Includes Z8001 and
Z8002 CPU's, emulator
cables and serial interface cables;
818
Systems ,recommended:
I
00-1041'()3
~ysRemm $@@@
Eva@all~llo ~ II itlInlcdl $lt
September 1983
Features
IJ
o
[J
VLSI components include the 6
MHz Z8001A CPU and 6 MHz
Z8010A Memory Management
Units (MMUs), as well as 6
MHz Z80B CPUs. The Z8000 is
a 16-bit CPU that has 16
general-purpose registers, an
8M byte address space, and
capability to perform 8-bit,
16-bit, and 32-bit operations.
ZEUS, Zilog's enhanced UNIX*
operating system, is a complete, real UNIX, not a lookalike. Enhancements include
additional utilities from Zilog
and the University of California
at Berkeley.
System 8000 uses a powerful
screen-oriented text editor to
increase editing spe'ed.
[J
A selection of high-level
languages is offered for the
Z8000: BASIC, COBOL, C,
FORTRAN 77, Pascal and
PLZ/SYS.
[]
Up to 4M bytes of ECCcontrolled memory increases
system reliability, and a large
physical memory size improves
system performance.
IJ
[]
Up to 24 users can be supported.
Optional industry-standard
9-track, half-inch, magnetic
tape is available for information interchange. Streamer
mode is used for disk backup.
...
Co\)
H igh·Performance,
Time.Sharing
Computer Systems
The System 8000 Models 21 and
31 are general-purpose, multiuser,
time-sharing computer systems.
They offer versatile and economic
solutions for the commercial user,
since many users can be added to
the same system, all performing
different tasks simultaneously.
Sharing of files and transmission of
messages between users is easy.
The multiuser programming environment allows both
sophisticated and untrained users
to operate the computer.
State·of·the·Art Technology Plus
Future Expansion
Z8000TM CPU, ECC (Error Checking
and Correction controlled memory,
Winchester disks, cartridge tape
and low power consumption
devices. System growth is made
possible by the addition of more
boards and more peripheral
modules.
As a supplier of both components
and systems, Zilog incorporates
the latest microprocessor
technology into system-level'
products.
The System 8000 family offers
high-performance systems at
reasonable' cost.
For optimal performance, the
System 8000 utilizes many advanced components such as
'UNIX is a trademark of Bell Laboratories, Zilog is licensed by Western ElectriC, Inc. for the Seventh Editon and System III.
819
All of the software needed to make
system programmers, application
programmers, and technical
writers more productive is
available on the system. Commercial users can choose from COBOL
and BASIC business languages;
system programmers have C,
Z8000 assembler, and PLZ/SYS for
their needs. Technical users can
select FORTRAN 77 or Pascal.
Left to Right: Model 11, Model 31 with Optional
Expansion Chassis. Model 31 with Optional
g·Track Tape Drive. Model 21.
Software
For the operating system, Zilog
chose to implement UNIX, the optimum environment for application
software development and programmer productivity. The Zilog
"port" of UNIX is named ZEUS, for
Zilog Enhanced Unix System. It
contains many additional features
and utilities designed by Zilog and
the University of California at
Berkeley.
Unlike some other implementations
of the popular UNIX operating
system, ZEUS, in conjunction with
the Z8001 CPU and the specialized
memory management hardware in
the System 8000; is able to support
extremely large user programs.
This can be especially important
for large FORTRAN and C applications.
ZEUS is a general-purpose,
multiuser, multitasking operating
system designed for software
development. Productivity increases with ZEUS because with
it, the necessary software tools are
available. Documentation quality .
and availability also improve
because tedious jobs are
automated.
820
Programs for business such as Accounts Receivable, Payroll, and
Order Entry can be quickly ported
and customized. In the technical
environment, special software and
test programs can be developed to
fit the needs of the task. The major
operating system features are:
•
Hierarchical file system
•
Compatible file, device, and
interprocess input/output
•
Separate code and data
address space
•
Multiple processes per user
•
User configurability
•
User programs address space
of up to 8M bytes (C,
FORTRAN 77, assembler)
System Utilities
The system utilities include the
command interpreter and file
maintenance, status inquiry,
system accounting programs, and
data communications. The command interpreter is selected on a
per-user basis, enabling the system
to be tailored to the needs of different users. Data communications
utilities are included for networking
over a serial link to other local or
remote ZEUS- or UNIX-based computer systems.
The ZEUS programming tools consist of languages, libraries, a symbolic debugger, text processing
software, and more than 180 other
utilities.
Hardware
The System 8000 hardware is
designed to support ZEUS software. The memory management
architecture allows ZEUS to support, with minimal changes, programs that run under the UNIX
operating system. The memory architecture also makes it possible
for user programs to have an address space of up to 8M bytes.
DeSigned for performance, reliability, and future growth, System
8000 is based on Zilog's 6 MHz
Z8001A CPU, with highperformance, high-reliability Winchester and Storage Module Disks
(SMD). Intelligent I/O controllers
aid performance. The large ECCcontrolled memory reduces swapping. The ZeBUS Backplane Interconnect (ZBITM) and modular
system packaging allow for system
growth. Serial RS-232-C and
parallel interfaces allow attachment of I/O devices such as CRTs
and printers.
The modular design makes System
8000 easy to service. As many as
five modules can be stacked. Each
module is self-contained so that
modules can be unstacked without
tools. The unit can also be
mounted in a standard 19" rack.
Zilog is committed to the long-term
development of the System 8000
product family. A recent addition is
an industry-standard, half-inch
magnetic tape peripheral option.
This peripheral supports interchange of information on tape with
other systems and can also be
used in a "streaming" mode for
fast·, high-capacity backup of the
on-line disks.
System 8000 Model 21 and 31 Characteristics
Storage Module Disk (SMD) Performance
Physical
Height
Width
Depth
Weight
84 cm (33 in.)
48 cm (19 in.)
61 cm (24 in.)
105 kg. (250 pounds)
approximate
Winchester Disk Performance
Rotation Speed
Power ON to Ready ,
Time
Average Positioning
Time (Typical)
Number of Surfaces
Tracks per Surface
,Sectors per Track
Bytes per Sector'
Data Transfer Rate
Capacity Unformatted
3,600 RPM
60 seconds
45 ms
Rotation Speed
Power ON to Ready Time
Average Positioning Time
(Typical)
Number of Surfaces
Tracks per Surface
Sectors per Track
Bytes per Sector
Data Transfer Rate
Capacity Unformatted
Cartridge Tape Drive Performance
3,600 RPM .
60 seconds
Speed Read/Write
(rewind/search)
Tracks
Recordi[Jg Density
20 ms
7
589
32
512
1.2M bytes/sec
84M bytes
30 ips (90 ips)
4
6,400 BPI
Memory
1M bytes ECC (minimum)
Electrical
.
Phase
Frequency
Single
47-63 Hz
Environmental
4
600
24
512
801 K bytes/sec
32M bytes
Operating Temperature
Relative Humidity
10° C
(50 0 F) min.
40° C
(104° F) max.
20-80%
(noncondensing)
Nominal
Selectable
Voltages ( ±,1 0 %)
100
117
220
240
V ac/60
V ac/60
V ac/50
V ac/50
Hz
Hz
Hz
Hz
Current
Sustained
(max)
Current
Surge
(max)
5.0 A
5.0A
2.5 A
2.5 A
8.0 A
8.0A
4.0 A
4.0 A
w
~
OO-1105'()3
821
System 8000
Moden I!
Zilog
Product Brie!
September 1983
Features
•
Economical, time-sharing
system supports up to eight
users.
•
Powerful ZEUS operating
system, Zilog's implementation
of UNIX*.
•
ZEUS includes a screenoriented text editor and com·
prehensive text processing
software for fast and easy
editing applications.
•
Model 11 supports such highlevel languages as COBOL,
BASIC, C, PLZ/SYS, FORTRAN
77, and Pascal.
•
Up to 1M bytes of parity
memory or optional 1M byte of
ECC-controlled memory.
•
Up to 36M bytes of disk
storage capacity.
•
17M byte cartridge tape for
backup and archiving.
A Compact Computer Powerful
Enough to Support Eight Users
The Zilog System 8000 Model 11
has been specifically designed for
business and office environments.
The system is small enough to fit
under a desk, yet can provide computing power for up to eight users
simultaneously. This generalpurpose, time-sharing system is
ideally suited for commercial
needs.
State-of-the-Art Components
The Model 11 features reliable,
field-proven VLSI components such
as the Z8001A CPU (which supports separate code and data address spaces) and three Z801 OA
Memory Management Units.
The basic Model 11 has 256K
bytes of parity random-access
memory (RAM). A 51A -inch. Winchester disk provides IBM bytes of
storage. The sealed, highperformance Winchester disk drive
protects data from contaminants
. and provides economical, fast, and
highly reliable on-line storage of
data.
A 17M byte cartridge tape drive is
used for hard disk backup. This
tape drive offers virtually unlimited
off-line storage of data.
Powerful ZEUS Operating
System
For the operating system, Zilog
chose to implement UNIX, the optimum environment for application
software' development and pro-'
grammer productivity. The Zilog
"port" of UNIX is named ZEUS, for
Zilog Enhanced Unix System.
Unlike some other implementations
of the popular UNIX operating
system, ZEUS, 'in conjunction with
the Z8001 CPU a'nd the specialized
memory management hardware in
the System 8000, is able to support
extremely large user programs.
This can be especially important
for large FORTRAN and C applications.
·UNIX is a trademark of 8ell Laboratories, Zilog is licensed by Western Electric. Inc, for the Seventh Edition and System III.
823
developed on other units in the
System 8000 family are completely
transferrable to the Model 11.
Intelligent Winchester disk and
tape drive controllers free the
operating system from routine
device-handling functions.
The system's 32-bit Z-BUS
Backplane 'Interconnect (ZBITM)
provides flexibility in system configuration and allows for future expansion.
Serial RS-232-C and parallel interfaces allow the system to communicate with input/output devices
such as CRTs and printers.
ZEUS includes features and additional software developed by Zilog
and the University of California at
Berkeley. Major features of the
ZEUS operating system are its
hierarchical file structure and compatible file, device, and interprocess input/output functions.
ZEUS includes an impressive array
of programs that comprise its
system utilities and development
tools. These software tools make it
easy for both OEMs and end-users
to develop new applications
quickly.
Reliable Hardware
The system's hardware has been
designed to complement its powerful software. Also, programs
Flexible Hardware
Expansion
ZEUS features a command interpreter as an interface between the
user and the system. It is selected
on a per-user basis, allowing the
system to be tailored to meet the
needs of different users.
The ZEUS development tools include programming languages,
libraries, a symbolic debugger, text
processing and formatting software, and more than 180 other
utilities. ZEUS also includes a twodimensional, screen-oriented text
editor to increase editing speed.
The system supports several highlevel programming languages for
business, scientific, and industrial
applications. Choose from COBOL,
BASIC, C, PLZ/SYS, FORTRAN 77,
and Pascal.
To accommodate system growth,
the basic Model 11 System 8000
can be expanded to include up to
1M bytes of parity or ECC- (Error
Checking and Correction) controlled memory. A second 51A -inch,
IBM byte Winchester disk drive
can be added to the system to provide dual drives with a total of 36M
bytes of on-line data storage
capacity.
System Utilities
The ZEUS system utilities provide
programs for user access, command processing, file management, status information, communication with other devices or
systems, and system maintenance.
Left to Right: Model 11, Model 31 with Optional
Expansion Chassis. Model 31 with Optional
g-Track Tape Drive. Model 21.
System 8000 Model 11 Characteristics
Physical
Height
Width
Depth
Weight
Environmental
66 cm (26 in.)
20 cm (8 in.)
46 cm (18 in.)
43 kg. (95 pounds)
approximate
Operating Temperature
Relative Humidity
Winchester Disk Performance
Rotation Speed
Power ON to Ready Time
Average POSitioning Time
(Typical)
Bytes per Sector
Data Transfer Rate
Capacity Unformatted
824
3,600 RPM
60 seconds
75 ms
512
5M bits/sec
IBM bytes
Electrical
10° C
(50° F) min.
40° C
(104° F) max.
20·80%
(noncondensing)
Cartridge Tape Drive Performance
Speed Read/Write
(rewind/search)
Tracks
Recording Density
30 ips (90 ips)
4
6,400 BPI
Single
47·63 Hz
Phase
Frequency
Nominal
Selectable
Voltages (± 10%)
100
117
220
240
V ac/60
V ac/60
V ac/50
V ac/50
Hz
Hz
Hz
Hz
Current
Sustained
(max)
2.5 A
2.5 A
1.25 A
1.25 A
Current
Surge
(max)
4.0
4.0
2.0
2.0
A
A
A
A
Memory
256K-byte parity (minimum)
00-11~2
Software
Development
Products
. Zilog
Pioneering the
Micro world
Development Systems
ao~iware ~or
All lilog Microprocessors
Zilog OTTers full support for all
its microprocessors and microcomputers with the System SOOO.
The System SOOO computer
system uses ZEUS, the UNIX*based operating system specifically designed for software
development and text processing.
Numerous development tools are
available, including the programming languages PLZ/SYS, C,
FORTRAN 77, Ada, and Pascal;
various libraries; and a symbolic
debugger.
Cross-software packages run
under ZEUS on the SSOOO enable
complete code development for
all Zilog microprocessors and
microcomputers. This includes C
compilers for the ZSOOO and ZSO
and assemblers for the ZSOOO,
ZSOO, ZSO, and ZS.
Emulators designed for the
complete range of Zilog products
are detailed in the Development
Section of this data book.
Because ZEUS treats emulators
as System SOOO peripherals,
System SOOO can be combined
with EMS SOOO, Z-SCAN SOOO, or
with non-Zilog emulators to provide total product development
support for multiple microprocessors.
The ZRTS Kernel is a small executive program that provides the
core of a real-time multitasking
operating system in PROM able
form. In addition to development
languages, ZRTS SOOO and ZCL
are available to assist the user in
implementing a real-time target
operating system. ZCL is a highlevel configuration language that
permits the designer to c'onfigure
the target system in easy-to-use
statements.
More software products for
Zilog components and systems
are described in the Zilog Software Catalog.
·UNIX is a trademark of Bell Laboratories.
S27
zaOOO™
PL~/SYS
Zilog
Product
Brief
June 1982
Features
I!I
• Structured format for fast and easy-tocompile programs.
Allows direct or interpretive execution of
program modules.
&1
Supports both segmented and nonsegmented
Z8000 processors.
• Produces efficient code for economical
memory usage and processing time.
Description
• Simplifies software production and
maintenance.
• High-level procedure-oriented language
permits efficient writing of machineindependent modules and programs.
28000 PLZ is a family of different programming languages designed to satisfy a wide
range of microcomputer software development
requirements. The two members of the PLZ
family, PLZlSYS and PLZlASM, produce object
code-compatible modules and share common
control structures and data definition facilities.
Thus, selective portions of programs can be
written in the most appropriate language for
the speCific application and still maintain a
consistent structure between modules.
PLZlSYS is a high-level, procedure-oriented
language that is syntactically similar to Pascal.
It provides a medium for writing structured,
machine-independent programs with a
minimum of programming effort.
PLZIASM, on the other hand, is a structured
assembly language that permits access to the
low-level capabilities of the processor by mixing assembly language and high-level control
structures.
Compiler. The Z8000 PLZlSYS Compiler
translates source code modules into an
intermediate stage called Z-code. The Z-code
modules can then be executed interpretively or
processed by the code generator to produce a
machine-code object module.
The compiler provides support for both the
segmented and non-segmented 28000 processors.
Code Generator. The Z8000 PLZCG Code
Generator accepts a file of intermediate Z-code
generated by PLZlSYS and produces the cor-
responding Z8000 machine code as a relocatable object module. This file can be linked
with other modules to form a complete
executable load module.
Interpreter. The intermediate Z-code modules
produced by the Z8000 PLZlSYS Compiler can
be executed interpretively by ZINTERP. Linking ZINTERP with the other modules generated
by the compiler produces an executable load
-module.
Linker. The Linker, ZLINK, links Z-code,
ZINTERP and/or machine code modules into a
single relocatable load module, allOWing the
user to control the overall size and speed of
the program.
Although interpretive Z-code runs more
slowly than machine code, the space savings
over machine code is usually substantial for
larger programs where the 3K bytes of
ZINTERP is a small percentage of the entire
program. By balancing the number of Z-code
and machine code modules, the user can maximize the efficiency of a particular program.
ZLINK resolves any external references
between separately assembled modules, so that
the load module produced is relocatable-. It
also allows the reordering and combining of
named sections between modules and supports
incremental linking.
Operating Environment. Z8000 PLZlSYS is
supported on Zilog's S8000 Development
System.
829
~1«J)7(l)
IrloalilmgmlPoinl
S)@«fiwarre I£muialion
i})a~E,!al17duncc~
Zilog
lJj)esccTlipftnolm
Preliminary
September 1983
The ZRTS package consists of a
small real-time, multi-tasking executive
program, the Kernel, and a System.
Configurator. The Kernel prOVides
sychronization and control of multiple
events occurring in a real-time environment. All major real-time functions are available-task synchronization, interru'pt-driven priority sdheduling, intertask communication, real-time
response, and dynamic memory allocation. The System Configura tor is a
language processor that allows the
target operating system to be defined
in high-level terms using the ZRTS
Configuration Language (ZCL).
[J
II Real-time Multi-Tasking Software
Components
o Synchronization of multiple tasks
• Interrupt-driven priority scheduling
• Real-time response
• Dynamic memory allocation
• Modular and Flexible Design
• Efficient memory utilization
• 6K byte PROMable kern~l
Q
Support for 28001 and 28002
16-bit microprocessors
• Configurable via linkable
modules
iii Versatile Base for Z8000™ System
Designs
• Segmented/non-segmented tasks
• System/normal mode tasks
• Uses standard Zilog calling conventions
Easy-To-Use System Generator
o High-level configuration
language
o Supports a wide variety of hardware configurations
o Easily changed control
parameters allow system
optimization
. 0
Eliminates the requirement for
intimate knowledge of system internal structure
OVERVIEW
Zilog's Real Time Software (ZRTS)
provides of a set of 'modular software
components that allows quick and easy
implementation of customized
operating systems for all members of
the 28000 16-bit microprocessor family.
In effect, ZRTS extends the instruction
set of the Z8000, adding easy-to-use
commands that give the Z8000 the
capability for managing real-time,
multi-tasking applications.
These functions greatly simplify the
tasks of the designer, allowing
development efforts to be concentrated
on the application, instead of on realtime coordination, task management
problems, and complicated system
generations. ZRTS provides a modular
and flexible development tool that
serves as a versatile base for 28000
system designs. The Kernel requires
only 6K bytes of either PROM or RAM
memory, thus allOWing configurations
for a wide variety of target systems,
while producing a memory-efficient.
cost-effective end product
839
.TABLE I.
CONCEPTS
ZRTS is both easy-to-Iearn and easyto-use. Oniy a few simple concepts
need to be understood before designing begins.
'TASK MANAGEMENT
Tasks. Tasks are the components comprising a real-time application. Each
task is an independent program that
shares the processor with the other
tasks in the system. Tasks provide a
mechanism that allows a complicated
application to be subdivided into
several independent, understandable,
and manageable units.
T_Destroy
Removes a dynamically created task.
T_Lock
Allows a task to take exclusive control
of the-CPU.
T_Reschedule
Changes the priority of a task.
T_Resume
Activates a suspended task.
T_Suspend
Suspends another task.
T_Unlock
Releases exclusive control of the CPU
for other tasks.
T_Wait
Suspends task execution.
T_Whoami
Returns the name (address) of the task
making the request.
Semaphores. Semaphores provide a
low overhead facility for allowing O1)e
task to signal another. Semaphores can
be used for indicating the availability
of a shared resource, timing pulses or
event notification.
Exchanges and Messages. Exchanges
and Messages provide the mechanism
for one task to send data to another. A
Message is a buffer of data, while an
Exchange serves as a mailbox at which
tasks can wait for Messages and to
which Messages are sent and held.
Two components make up the heart
of ZRTS-the ZRTS Kernel and the
ZRTS Configuration Language (ZCL).
An va subsystem and a debugger are
also provided in ZRTS.
The ZRTS Kernel. The Kernel is the
basic building block of ZRTS and performs the management functions for
tasks, semaphores, the real-time clock,
memory and interrupts. The Kernel
also provides for task-to-task communications via Exchanges and
Messages. All requests for Kernel
operations are made via system call
instructions with parameters' in
registers, according to the standard
Zilog calling conventions.
Task Management. One of the main
activities of the Kernel is to arbitrate
the competition that results when
several tasks each want to use the processor. Each task has a unique task
descriptor that is managed by the
Kernel. The data contained in the
descriptor includes priority, status and
other pertinent information. ZRTS supports any number of tasks, limited only
by the memory available to accommodate the task descriptors and stacks.
The Kernel maintains a queue of all
active tasks on the system. Each .laskis
scheduled for processor time based on
its priority. The highest-priority task
that's ready to run gains control of the
CPU; other tasks are queued. Tasks
can be prioritized up to 32767 levels,
with round-robin scheduling among
tasks with the same priority.
Tasks can run either segmented or
non-segmented code, in either normal
840
Provides the status of tasks in the
system.
T_Create
Creates a task dynamically.
SEMAPHORE MANAGEMENT
Se11'L-.Clear
Clears semaphore queue and
reinitializes a semaphore.
Se11'L-.Create
Creates a semaphore dynamically.
Se11'L-.Destroy
Removes a dynamically created
semaphore.
Se11'L-.Signal
Signals a s,emaphore, increments the
counter.
Tests a semaphore for a signal.
Causes a task to wait until a semaphore
is signaled, decrements the counter.
CLOCK MANAGEMENT
Clk_Delay_Absolu te
Places a task on the clock queue
waiting for absolute time.
Places a task on the clock queue
waiting for passage of an interval of
time.
CILSet
Sets the 'real-time clock.
Clk_Time
Reads the clock.
MEMORY MANAGEMENT
Me11'L-.Census
PrOVides status of the memory
resource.
Alloc
Dynamically allocates memory.
Release
Releases allocated memory.
INTER-TASK COMMUNICATION
Gets a messa.ge from an exchange pool
and assigns a destination or a reply
exchange to it.
~Assign
Assigns a new source and destination
to an existing message.
M_Create
Creates a message dynamically.
M_Destroy
Removes a dynamically created
message.
M_GeLDescriptor
Gets message's descriptor informfltion
~Read
Reads the message data.
M_Receive
Receives a message from an exchange.
~Receive_Wait
Waits to receive a message from an
exchange.
Returns a message to the exchange
pool.
~Reply
Sends a message back to destination
exchange.
~Send
Sends a message to an exchange.
~Write
Changes message data.
LCreate
Dynamically creates an exchange with
a pool of messages.
LDestroy
Removes a dynamically created
exchange.
or system mode. The numerous operations that may be performed on tasks
are listed in Table l.
Semaphore Management. The Kernel
provides semaphore management for
synchronizing interacting tasks. A
typical use of semaphores is to provide
mutual exclusion of a shared resource.
When a resource is to be used by only
one task at a time, a semaphore with a
counter of 1 controls the resource.
Every task requiring the resource must
first wait on that semaphore. Since the
counter is I, only one task will acquire
the resource. The others will be
queued on the semaphore and
suspended until the semaphore is
signaled that the resource is once
again available. At that time, the first
task on the semaphore queue will be
made ready to run and can use the
resource. After all tasks have ,?cquired
the resource and signaled the completion of their use, the semaphore returns
to its original state with a counter of 1.
Counters greater than one are useful
when there are a number of similar
resources, (Le., three tape drives, four
I/O buffers, etc.).
In ZRTS, a semaphore can count up
to 32767 signals. The commands provided by the Kernel to manage
semaphores are listed in Table l.
Clock Management. ZRTS operates
with a real-time clock that generates
interrupts at a hardware-dependent
rate. It is use? for timed waits,
timeouts, and round-robin scheduling.
All times are given in number of ticks.
The clock may be manipulated by the
set of commands provided by the
Kernel that are listed in Table l.
Memory Management. Storage for
ZRTS data structures is allocated either
statically at system generation time, or
dynamically at run time. Dynamic
allocation occurs via a system call that
specifies the attributes of the structure
to be created and returns a name that
can be used to refer to the structure.
Memory is allocated in 256-byte
increments, and can be released using
a system call.
The storage allocator can also be
called directly to obtain blocks of
memory up to 64K bytes long, which
can be used by the task for any
purpose.
Interrupt Management. Interrupthandling routines are provided for
system calls, non-vectored interrupts
and a hardware clock. The user must
provide interrupt routines for whatever
other vectored interrupts are included
in the target system.
ZRTS can switch control to a task
waiting for an external event within
600-microseconds after the occurrence
TABLE 2.
CONSTANTS
Specifies system constants.
EXCHANGES
Defines the characteristics of application exchanges.
INiTIALIZATION
Specifies routines that are to execute
prior to beginning execution of the first
task.
INTERRUPT
Associates an interrupt routine with an
interrupt vector or trap and system
call-handlers. Provides the facilities to
specify a NVI interrupt-handler that
will be called from the system NVIhandler routine.
MEMORY
Defines sections or segments that contain code, initialized data, or
uninitialized data and speCifies the
location in memory where it will be
placed. The files to be included in the
configuratfon are also defined in this
section in conjunction with the section/segment definitions.
SEMAPHORES
Defines the characteristics of application semaphores.
SWITCHES
Allows flags that control the system
generation operation to be set.
TASKS
Defines the characteristics of application tasks.
of the event. This is a worst-case time
for a system using a 4 MHz Z8001 CPU
and is based on a SeID-Signal system
call awakening a higher priority task
that is waiting on a semaphore; this
causes a task switch to occur.
ZRTS provides several commands for
inter-task communications. These are
listed in Table l.
Inter-Task Communication. The
Kernel provides the capability for tasks
to exchange information. This communication process occurs when one
task sends a Message to an Exchange
and another task receives the Message.
A Message contains a length indicator, a buffer with a variable amount
of data, and a code that identifies the
Message type. The Exchange is a
system data structure that consists of a
queue for Messages sent but not yet
received, a semaphore on which a task
can wait for a Message, and an
optional "pool" list from which
Messages can be obtained quickly.
Logical 1/0. ZRTS includes an optionalmodule which provides a deviceindependent mechanism for interfacing
between tasks and customer-written I/O
device drivers. Sample device drivers
are included for terminal and disk-type
devices.
ZRTS Configuration Language (ZCL).
Since ZRTS's modular design leads to
so many different configurations, a
simple facility for generating the target
operating system is a critical part of
the ZRTS package. The ZRTS Configuration Language (ZCL) provides an
easy-to-use means for generating the
target system. Using ZCL, the designer
can specify hardware information, software parameters, linkage information,
and system data structures in highlevel terms.
GULE
zaooo
USER
APPLICATION
SYSTEM
· l - - - -.... CONFIGURATION
DEVELOPMENT
Development Environment
841
ZCL unburdens the user of the
necessity to learn the details of the
ZRTS internal structures. System data
structures can be generated simply by
specifying the appropriate parameters.
The ZCL syntax is free-format with
comments allowed to make the configuration commands more readable
and maintainable.
ZCL input is comprised of a number
of descriptive sections, each containing
the details of the target operating
system. The functions of these sections
are described in Table 2. A sample
system generation using ZCL is illustrated in Figure l.
DEVELOPMENT ENVIRONMENT.
Application modules for ZRTS are
developed on a Zilog System 8000. The
application or system generated can
then be downloaded into a Zilog S8000
Development Module or a customized
target system.
An interface package is provided for
making ZRTS system calls from programs written in C, Pascal, or FORTRAN. Register usage by the system
calls is compatible with Zilog's calling
conventions.
A debugger is provided with ZRTS
for use in testing and debugging applications. After the application is
debugged, the system can be easily
reconfigured (without the debugger)
into its final form.
5.' ICHf S:
IlppIIC"~t. f~"
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'llessaoes
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Figuro I. ZeL Samplo Input.
ORDERING INFORMATION
Description
Prerequsites
ZRTS Zilog Real-Time Software for the Z8000
System 8000 (Requires Software License)
842
00-1097.()3
. J.PI?@aalill@U
LIDsolI:I?il[0UUCU>llu
June 1982
lJ High-Lovol Procoduro-Oriented
Languago Permits Efficiont
Writing of Machine-Independent
Modules and Programs.
[J
Structured Format for Fast and
Easy-to-Compilo Programs.
[J
Prod\1ces Efficient Codo for
Economical Momory Usago and
Processing Timo.
[J
Simplifies Softwaro Production
and Maintenance.
[J
Allows Direct or Interprotivo
Execution of Program Modules.
FEATURES
Compiler. The 280 PLZlSYS Compiler
translates source code modules into an
intermediate stage called Z-code. The
Z-code modules may then be executed
interpretively or processed by the code
generator to produce a machine-code
object module.
Codo Gonerator. The 280 PLZCG
Code Generator accepts a file of intermediate Z-code generated by PLZlSYS
and produces the corresponding 280
machine code as a relocatable object
module. This file may be linked with
other modules to form the complete executable load module.
Intorprotor. The intermediate Z-code
modules produced by the Z80 PLZlSYS
OVERVIEW
Z80 PLZ is a family of different programming languages designed to
. satisfy a wide range of microcomputer
software development requirements.
The two members of the PLZ family,
PLZlSYS and PLZIASM, produce object
code-compatible modules and share
common control structures and data
definition facilities. Thus, selective por, tions of programs may be written in the
most appropriate language for the
specific application and still maintain a
consistent structure between modules.
PLZlSYS is a high-level, procedureoriented language that is syntactically
similar to PASCAL. It provides a
medium for writing structured,
machine-independent programs with a
minimum of programming effort.
PLZIASM, on the other hand, is a
structured assembly language that per'±nits access to the low-level capabilities
of the processor by mixing assembly
language and high-level control
structures.
Compiler can be executed interpretively by ZINTERP. Linking ZINTERF>
with the other modules generated by
the compiler produces an executable
load module.
Although interpretive Z-code runs
more slowly than machine code, the
, space savings over machine code is
usually substantial for larger programs
'where the 3K bytes of ZINTERP is a
~mall percentage of the entire program. By balanCing the number of
Z-code and machine code modules, the
user can maximize the efficiency of a
particular program.
PLINK resolves any external references between separately assembled
modules, so that the load module produced is relocatable. It also allows the
reordering and combining of named
section~ between modules and supports
incremental linking.
PLZ/ ASM Translator. The PLZ FILTER
translates a PLZIASM source module
into a file of the corresponding Z80
Assembler source. This gives the .
Assembler the benefit of logical data
structure, program flow control, and
modular program design, in addition to
its existing features.
PLZ Linl:er. The PLZ Linker, PLINK,
links Z-code, ZINTERP and/or machine
code modules into a single relocatable
load module, allowing the user to control the overall size and speed of the
program.
ORDERING INFORMATION
Part No.
Description
07-3301-01
Z80 PLZ
Object Diskette for use
with PDS 8000105 and
PDS 8000/15
07-3302-01
Z80 PLZ
Object Diskette for use
with ZDS-l Series
07-3303-01
Z80 PLZ
Object Cartridge Disk
for use with PDS 8000/20
and PDS 8000/30
843
PLZlSYS
FILTER
PLZCQ
ASM
PLINK
Figure 1. Z8D PLZ Language Modules.
844
00-1043-01
~800!M
(Cl1@&lO ~@ai1t7~rlO ~Q@rlCJ@O
lProdlunci
.DescripftnoBU
September 1983
OVERVIEW
The Z800 Cross-Software Package is a complete
development environment that provides all the tools
necessary to both generate and debug programs for the
Z800 MPU. The package-a comprehensive collection
of software routines and utilities-allows programmers
to prepare, modify, test, and debug their software prior
to release of the Z800 chip. The result of this comprehensive software testing and evaluation is a highquality design that will be ready for end use by the time
the hardware has been perfected.
The user interface for each of the program. tools is
similar to the standard UN IX* interface. Code testing
and debugging can be done either with the Instruction
Level Simulator (ILS) on the host system or'by downloading to a Z800-based target system; mload and msend
utilities are included to manage the host-to-target
system communication. Use of the ILS facility allows
program ~ebugging well in advance of prototype hardware availability.
All the software tools in the Cross-Software Package are
designed to run on either the DEC-VAX or the Zilog ZEUS
S8000, both with a UNIX operating system. The programmer can choose either the C programming language or
Z800 (Z80-compatible) assembly language to develop,
load, test, debug and run programs for the Z800 MPU.
DEVELOPMEtn
BOARD
Z800 Cross-Software Package
·UNIX is a trademark of Bell Laboratories.
2311-001
845
FEATURES
The l800 Cross-Software Package consists of the
followif")g tools:
•
Object File Utilities. Standard UNIX object utilities
for MUFOM files, plus upload/download to target.
•
C Cross Compiler. Produces efficient assemblylanguage code. Standard run-time library included.
•
•
Cross Assembler. Relocatable assembler with
macros, conditional assembly, and floating-point
support.
.
Portable Debugger. Written in C language, the
debugger facilitates the use of different hosts. It not
only runs on l800 target systems, but is also the
user interface to the ILS.
II
Linker. Handles full address range of the l800
MPU using proposed IEEE-standard MUFOM format.
Test cases. Included with each tool for product
testing.
II
Documentation for each tool in the package.
•
•
Instruction Level Simulator. Debugging environment for l800 code on cross-software host.
DESCRIPTION
code as output to allow easy debugging of the compiled
code, or to allow hand optimization for critical code sections. A listing file can be generated that shows the
assembly language interspersed with ,the C code that
produced it.
C Cross Compiler
\
The l800 C Cross Compiler is a UNIX-license-free C
compiler, designed to run on either lilog's UNIX S8000
or the DEC-VAX. The l800 Compiler includes a Bell
System V-compatible front end, and a back end
generated by an automatic code-generator. Running at
speeds similar to the Portable C Compiler, the l800
Compiler features a variety of optimizations, some
machine-independent, others machine-dependent.
Options include:
The compiler supports the latest version of the C pro-.
gramming language, and thus includes longword and
floating-point support, enumerations, structure assignment, and full "define" capability. The compiler can
automatically invoke the C optimizer to produce more efficient code. The compiler produces assembly language
0
E1
s compiles the source files but suppresses the
assembly and link steps.
GJ
c compiles and assembles the source files but suppresses linking.
Without the use of these options, the C Cross Compiler
by default compiles, assembles, and links l800 code.
LrUJ ~if:E
DISK
DRIVE
/
9
DD"'---'-""""",,-rn··----:>'I·
C
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•
D
Z800
/
DEVELOPMENT~.
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UNI):,V5.\
Z800
CROSS SIW
PACKAGE
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j~j{i.~'~'
.
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invokes the C optimizer.
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Z800
DEVELOPMENT
MODULE
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,Typical Z800 Cross-Software Package Installation
846
2311-002
Cross Assembler
The Z800 Cross Assembler utilizes expanded Z80
mnemonics and addressing modes to assemble and
generate MUFOM object modules (IEEE proposed standard #P695). The Z800 Cross Assembler is both
fast-assembling at least 1,000 lines per minute-and
efficient-consuming no more than 64K bytes of
code/data space., Written in theC programming
language, the assembler is designed to be easily
retargetted. Additional features include macros, condi~
tiona I assembly, and relocation. The Z800 assembler is
upwardly compatible with Zilog's Z80 gssembler and
Microsoft's Macro-80 assembler.
The assembler supports a full set of pseudo-ops including conditional pseudo-ops and a powerful macro
capability as well as pseudo-ops to support floating-point
opera~ions. A cross-reference listing can be generated
to show the use and definition of all the symbols in the
program.
The assembler supports the complete list of opcodes in
the Z800 MPU Preliminary Product Specification (document # 00-2259-01), plus the instruction set of the Z8070
Floating-Point Unit. All Z80 opcodes,pseudo-ops, and
commands supported by the Z80-RIO assembler are
also supported. Constants supported by the assembler
include integers, floating-point numbers, characters, and
character strings. In addition, the assembler supports
expressions using up to 80 bits of precision.
Addressing modes for the assembler are also derived
from the Z80 assembler:
•
Registar
•
Immediate
III ' Indirect Register
II
Direct Address
..
Indexed
II
Short Index
•
Based Indexed
•
Stack Relative
IJ
PC Relative
Three kinds of macros are included in the Z800
assembler:
MACROs are compatible with the Z80 assembler.
Parameters are separated by blanks or commas and are
substituted into the macro body as strings.
PROCs are call-by-value macros. Parameters are expreSSions, separated by blanks or, commas, and are
substituted into the macro body as values.
FUNCs are function macros. They are similar to PROC
macros, except that they are recognized within expressions as operators or op.erands.
Additional pseudo-ops are provided to extend macros,
conditional assembly, data definition, and object code
generation. A command-line option specifies a third pass,
for generating a cross reference.
Linker
The Z800 linker is a processor-independent linker that
combines MUFOM format-relocatable object modules
generated by the cross assembler and resolves external
refer..ences from within the modules or by searching object code libraries. The result is an executable, program
that can be sent to a target syptem for execution or
simulated on the ILS. The linker also provides many advanced features such as complex expression evaluation
with up to 80 bits of precision, multiple program/data
segments of any length, and memory protection attributes for any portion of the memory space. '
Object File Utilities
Z800 Cross Software Package includes a number of
machine-independent utilities' for processing object
modules created in MUFOM format. Because these
utilities can be used for different computef systems
without modification, the programmer is freed from such
constraints as variations in address and data size; these
potential snags are resolved by the MUFOM utilities
themselves.
MUFOM allows for up to 256 independently relocatable
sections per module. This gives the programmer flexibility and control over how the program is mapped in
memory. Program size is approximately 96K bytes, with
64K bytes for code and 32K for data.
Object modules can be stored in either ASCII or binary
format. While ASCII is useful fO[ downloading across
serial links, binary modules require less file space and
allow faster processing.
'
For linking and loading object modules, two utilities are
provided:mlink and mload. mlink resolves external
references among modules, relocates addresses, and
combines the object modules into a single module called
a load module. mload downloads an object file from the
host system to the target system. mload and mlink can
send or receive object files in either Tektronix hex for- ,
mat, Intel hex format, or ASCII MUFOM format.
In addition to mlink and mload, there are several other
functions performed by the MUFOM utilities: mnm,
msend, mdump, mcb, and mbc. These facilities allow inspection of object code files and the creation and
maintenance of object libraries for use by the linker.
mnm
prints the name list (symbol table) of an object
module.
m'send
uploads the contents of memory from a target
system and creates an absolute MUFOM object module on the host system.
847
mdump
dumps a hex object file along with relocation
information; object header information is also
displayed.
mcb
converts an ASCII object module into a binary
module.
mbc
converts a binary object module into ASCII.
Portable Debugger
The l800 Portable Debugger is a versatile debugging
system, able to run on either l800 (8-bit) or l8000
(16-bit) microprocessor systems. The debugger is written in C language, using the standard C library as well as
a library for stand-alone I/O and memory utilities appropriate to the target system. To facilitate the use of different hosts (e.g., other UNIX systems, other operating
systems such as CP/M, or development module environments), the processor descriptor parameters, such
as state structure/display, memory and I/O access, Mini
Assembly and. Disassembly library routines (MAD) and
the ILS, are contained in separate, easily modified
modules.
Instruction Level Simulator (ILS)
The Z800 ILS is a powerful software tool that simulates
execution of l800 instructions. These instructions can
then be displayed and manipulated by the portable
848
debugger. The ILS facility executes l800 instructions at
slower than real-time rates and allows access to the
simulated processor registers and to the full range of
simulated memory. The ILS supports both symbolic and
mnemonic l800 opcode assembly, disassembly, and
emulation. Additional features of the ILS include simulation of the on-chip MMU to provide a large (24M byte) addressing space; multiple breakpoints; single-stepping;
I/O simulation; full memory, register and flag access;
and friendly error ~eporting.
The ILS software, program accepts as input l800
machine code generated by the l800 assembler; it then
simulates changes in processor state. Each simulation is .
a single-step routine that works in conjunction with the
debugger.
A typical process for using the ILS to generate, ~assem
ble, and debug l800 software is as follows:
1. A conventional editor is used to create a l800
assembly language source file.
2. The source file is then assembled and tested for syntax errors.
3. The default MUFOM object file produced by the
assembler, named m.out, is then loaded into the
debugger/l LS and run.
00-2227.Q1
Z8® Software
BDe'Ue!opmenl !iackage
Zilog
Product
Description
September 1983
II Structured Assembly Language
with High-Level Constructs.
• Relocatable and Absolute Object
Code Format.
iii Free Format Statements Allow
Indentation and Spacing for
Readability.
m External Symbol References.
II Global Symbol Definitions.
OVERVIEW
The Z8 Software Development
Package consists of five utility programs which aid and simplify software
development for Z8-based systems. Z8
PLYASM, par1' of Zilog's PLZ family,
brings all the advantages of modular
programming to Z8 software develop"ment: The programming task can be
broken into easily managed modules,
giving more work assignment options to
the engineering manager and a clearcut structure to the individual programmer. The Z8 linker completes the task
by combining the modules and resolving any external references.
FEATURES
Assembler. The Z8 PLYASM
Assembler translates easy-to-read, freeformat PLYASM source programs to
object code. Because the user may
specify that either absolute or
relocatable object code be produced,
he may choose a memory location for
the program or leave that responsibility
to the Linker. The Z8 PLYASM
Assembler produces a listing file containing both the source and assembled
code.
Z8 PLYASM allows an efficient mix
of powerful assembly language
mnemonics with high-level control
structures such as IF . . . THEN . . .
ELSE ... FI and DO ... aD loops.
The PLYASM programmer may map
instructions and information into the
Z8's register, program and data
memory spaces, and organize the data
space with such data declarations as
RECORDS and ARRAYS. The
PLYASM Assembler supports external
symbol references and global symbol
definitions and is fully supported by
. the RIOTM operating system.
ZLINK. ZLINK links assembled modules
into a single relocatable module and
resolves any external references among
ORDERING INFORMATION
Prerequisites:
PDS 8000,Series
ZDS 1146 or 1125
MCZ~l Series
RIO
Part No.
Description
07-0086-01
28 Software Development Package
Object Cartridge Disk
for Use with PDS
8000/20A
07-3361-01
00-1042'()1
Z8 Software Development Package
Object Diskette for Use
with PDS .8000/5 and
PDS 8000/15
separately assembled modules. It can
also reorder and combine named sections found in the input assembly
language modules. ZLINK accepts a
symbolic specification of
the program entry point in the command line and, on request, produces a
detailed link map which gives the locations of global references and relocated
modules and sections. Errors in the
'
linking process are reported in the
optional link map and at the system
console.
Imager. IMAGER accepts multiple""
linked-object files from the linker and
translates them into absolute code.
IMAGER can then either store the
absolute code in a disk file or leave it
in system memory. Named sections
found in the input object modules may
be reordered and loaded anywhere in
system memory.
Program Transfer. LOAD/SEND
downloads an absolute program file
into the Z8 Development Module for
debugging, then sends it back to the
disk for back-up and storage .
Prom Programming. Z-PROG stores
the perfected load module in PROM.
Pent No.
07-3362-01
Description
Z8 Software Development Package
Object Diskette for Use
with ZDS-1 Series
07-3363-01
Z8 Software Development Package
Object Cartridge Disk
for Use with PDS
8000/20 and PDS
8000/30
849
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Notes
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