1983_8 Bit_Microprocessor_and_Peripheral_Data 1983 8 Bit Microprocessor And Peripheral Data

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Motorola's Microprocessor Families

I

Reliability

I

Data Sheets

II

Mechanical Data

I

Technical Training

•

Memory Products

•

Logic and Special Function Products

•

Development Systems and
Board-Level Products

II.

MOTOROLA
MICROPROCESSORS
Prepared by
Technical Information Center

This book is intended to provide the design engineer with the technical data
needed to completely and successfully design a microprocessor based
system. The data sheets for Motorola's microprocessor and peripheral components are included.
The information in this book has been carefully checked; no responsibility,
however, is assumed for inaccuracies. Furthermore, this information does
not convey to the purchaser of microelectronic devices any license under
the patent rights of the manufacturer.
Additional information about memory products, technical training, and
system development products is also provided. For further marketing and
applications information, please contact:

Motorola Inc.
MOS Integrated Circuits Group
Microprocessor Division
Austin, Texas
(512)928-6800

Printed in U.S.A.

Series C
©MOTOROLA INC., 1983
Previous Edition © 1981
"All Rights Reserved"

Product Preview data sheets herein contain information on a product under
development. Motorola reserves the right to change or discontinue these
products without notice.
Advance Information data sheets herein contain information on new products. Specifications and information are subject to change without
notice.

EXORciser and EXORmacs are registered trademarks of Motorola Inc.
BASIC-M, EXORbug, EXORbus, EXORdisk, EXORset, EXORterm, HDS-200,
1I0module, L1Lbug, MOOS, MICRObug, Micromodule, PRObug, RMS09,
RMS68K, SUPERbug, UNICORN, UNIDOS, VERSAbug, VERSAbus,
VERSAdos, VERSAmodule, VMC 68/2, VMEbus, VMEmodule, and VME/10
are trademarks of Motorola Inc.
DEC and VAX are trademarks of Digital Equipment Corporation
LARK is a trademark of Control Data Corporation
Sentry is a registered trademark of Fairchild
Silent 700 Cassette is a trademark of Texas Instruments Incorporated
UNIX is a trademark of Bell Labs

ii

TABLE OF CONTENTS
Title

Page No.

Chapter 1 -

Motorola's Microprocessor and
Microcomputer Families
8-Bit Microprocessors (M PUs) - MC6800, MC6802,
MC6803, MC6808, MC6809, MC6809E, MC146805E2. . .
8-Bit Microprocessors' Features Matrix. . . . . . . . . . . . . . .
Peripheral and Interface Components. . . . . . . . . . . . . . . .

1-2
1-6
1-7

Chapter 2 - Reliability
Reliability and Quality Monitor Report. . . . . . . . . . . . . . . .

2-2

Chapter 3 - Data Sheets
(See Master Index for sequence)
Chapter 4 - Mechanical Data
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Dimensions ..............................

4-3
4-3

Chapter 5 - Technical Training
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Course Offerings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-3
5-3

Chapter 6 - Memory Products
Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2

Chapter 7 - Logic and Special Function Products
High-Speed CMOS Selector Guide. . . . . . . . . . . . . . . . . . .

7-3

Chapter 8 - Development Systems and Board-Level Products
Development Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Guide: Selection by MPU/MCU Supported. . . .
Microcomputer Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-3
8-15
8-19

iii

iv

MASTER INDEX
This index includes all devices in Motorola 8-Bit
Microcomputer and Microprocessor/Peripheral
product lines. Devices with MCU in the page
number column are fully characterized in the
separate Microcomputer Data Book.
Device No.
MC1372
MC2670
MC2671

MC2672
MC2673
MC2674
MC2675
MC3440A
MC3441A
MC3443A
MC3446A
MC3447
MC3448A
MC3870
MC6800
MC6801
MC6801U4
MC6802
MC6802NS
MC6803
MC6803E
MC6803U4
MC6804J2
MC6804P2
MC68HC04P2
MC68HC04P3
MC6805K2
MC6805K3
MC6805P2
MC6805P4

Description
Page No.
Color Television Modulator .................. .
3-2
Display Character and Graphics Generator ..... .
3-10
Programmable Keyboard and Communications
Controller ............................... .
3-24
Programmable Video Timing Controller ........ .
3-47
Video Attributes Controller .................. .
3-74
Advanced Video Display Controller ............ .
3-87
Color/Monochrome Attributes Controller ....... . 3-119
Quad Interface Bus Transceiver .............. . 3-131
Quad Interface Bus Transceiver .............. . 3-131
Quad Interface Bus Transceiver .............. . 3-131
Quad Bidirectional Bus Transceiver ........... . 3-135
Octal Bidirectional Instrumentation Bus (GPIB)
Transceiver .............................. . 3-138
Quad Bidirectional Instrumentation Bus (GPIB)
Transceiver .............................. . 3-144
8-Bit Single-Chip Microcontroller ............. . MCU
8-Bit Microprocessor Unit .................... . 3-149
8-Bit Microcomputer Unit .................... . MCU
8-Bit Microcomputer Unit .................... . MCU
8-Bit Microprocessor with Clock and
Optional RAM ............................ . 3-179
8-Bit Microprocessor with Clock and
Optional RAM ............................ . 3-179
8-Bit Microprocessor Unit .................... . MCU
8-Bit Microprocessor ........................ . 3-200
8-Bit Microprocessor Unit .................... . MCU
8-Bit Microcomputer ........................ . MCU
8-Bit Microcomputer ........................ . MCU
8-Bit HCMOS Microcomputer Unit ............. . MCU
8-Bit HCMOS Microcomputer Unit ............. . MCU
8-Bit Microcomputer Unit with Serial Peripheral
Interface and Two Timers .................. . MCU
8-Bit Microcomputer Unit with A/D Converter,
Serial Peripheral Interface, and Two Timers ... . MCU
8-Bit HMOS 1K Microcomputer ............... . MCU
8-Bit HMOS 2K Microcomputer ............... . MCU

v

Device No.
MC6805P6
M C68(7)05R/U
Series
MC6805R2
MC6805R3
MC6805S2
MC6805T2
MC6805U2
MC6805U3
MC68HC05C4
MC6808
MC6809
MC6809E
MC68HC09E
MCM6810
MC68HC11A4
MC6821
MC6822
MC6829
MCM68HC34
MC6835
MCM6836E16
MCM6836R16
MC6839
MC6840
MC6844
MC6845
MC6846
MC6847
MC6847Y
MC6850
MC68HC51
MC6852
MC68HC53
MC6854
MC6859
MC68HC68A1
MC68HC68R1
MC68HC68R2
MC68HC68T1

Page No.
Description
8-Bit Microcomputer ........................ . MCU
8-Bit Microcomputers ....................... .
8-Bit Microcomputer ........................ .
8-Bit Microcomputer ........................ .
8-Bit Microcomputer Unit with A/D Converter,
Serial Peripheral Interface, and Three Timers .,
8-Bit HMOS 2K Microcomputer with PLL ....... .
8-Bit Microcomputer ........................ .
8-Bit Microcomputer ........................ .
8-Bit HCMOS Microcomputer ................. .
8-Bit Microprocessor with Clock and
Optional RAM ............................ .
8-Bit Microprocessing Unit ................... .
8-Bit Microprocessor Unit .................... .
8-Bit HCMOS Microprocessing Unit ........... .
128 x 8-Bit Static Random Access Memory ..... .
8-Bit Microcomputer ........................ .
Peripheral Interface Adapter ................. .
Industrial Interface Adapter .................. .
Memory Management Unit ................... .
Dual-Port Memory Unit ...................... .
Mask Programmed CRTC Controller ........... .
128K Combination ROM/EEPROM Memory ..... .
128K Combination ROM/EEPROM Memory ..... .
Floating-Point ROM ......................... .
Programmable Timer ........................ .
Direct Memory Access Controller ............. .
CRT Controller (CRTC) ...................... .
ROM-I/O-Timer ............................. .
Video Display Generator ..................... .
Video Display Generator ..................... .
Asynchronous Communications Interface
Adapter ................................. .
Asynchronous Communications Interface
. Adapter ................................. .
Synchronous Serial Data Adapter ............. .
Asynchronous Communication Interface Adapter
Advanced Data-Link Controller ............... .
Data Security Device ........................ .
Serial 1O-Bit A/D Converter ................... .
8-Bit Serial Static RAM ...................... .
8-Bit Serial Static RAM ...................... .
Real-Time Clock plus RAM and Power
Sense/Control ........................... .
vi

MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
3-179
3-233
3-266
3-300
3-302
MCU
3-307
3-317
3-326
3-342
3-350
3-371
3-371
3-382
3-397
3-410
3-427
3-450
3-469
3-469
3-494
3-503
3-506
3~520

3-524
3-546
MCU
MCU
MCU
MCU

Device No.
MC6875
MC6875A
MC6880A/MC8T26A
MC6882A, B/MC3482A, B
MC6883/SN74LS783
MC6885/M C8T95
MC6886/M C8T96
MC6887/MC8T97
MC6888/M C8T98
MC6889/M C8T28
MC6890
MC68120
MC68121
MC68701
MC68701U4
MC68705P3
MC68705P5
MC68705R3
MC68705R5
MC68705U3
MC68705U5
MC146805E2
MC146805E3
MC146805F2
MC146805G2
MC146805H2
MC146818
MC146823
MC1468705F2
MC1468705G2
TCA5600
TCF5600

Description

Page No.

Two-Phase Clock Generator .................. .
Two-Phase Clock Generator .................. .
Quad Bus Transceiver ....................... .
Octal Buffer/Latch .......................... .
Synchronous Address Multiplier .............. .
Hex Address Buffer ......................... .
Hex Address Buffer ......................... .
Hex Address Buffer ......................... .
Hex Address Buffer ......................... .
Quad Bus Transceiver ....................... .
8-Bit M PU D/A Converter ..................... .
Intelligent Peripheral Interface ............... .
Intelligent Peripheral Interface ............... .
EPROM Microcomputer ..................... .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit EPROM Microcomputer ................. .
8-Bit CMOS Microprocessor .................. .
8-Bit CMOS Microprocessor .................. .
8-Bit CMOS Microcomputer .................. .
8-Bit CMOS Microcomputer .................. .
8-Bit CMOS Microcomputer .................. .
CMOS Real-Time Clock plus RAM ............. .
CMOS Parallel Interface ..................... .
8-Bit CMOS Microcomputer with EPROM ....... .
8-Bit CMOS Microcomputer with EPROM ....... .
Universal Microprocessor Power Supply
Controller ............................... .
Universal Microprocessor Power Supply
Controller ............................... .

3-555
3-555
3-566
3-571
3-576
3-601
3-601
3-601
3-601
3-606
3-611
3-618
3-618
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
3-662
3-696
MCU
MCU
MCU
3-697
3-719
MCU
MCU

vii

MCU
MCU

viii

Motorola's Microprocessor Families

1-1

I

MOTOROLA'S
MICROPROCESSOR AND MICROCOMPUTER FAMILIES

I

Serving as the "heart" of every microcomputer system is a microprocessor. Motorola
manufactures the industry's most complete selection of solid-state microcomputer components to provide the performance you need and the design flexibility you want.
The family concept has been extremely popular in the microprocessor industry. Motorola
pioneered this family concept with the introduction of the M6800 Family in 1974. Since
then the MPU/MCU Family has evolved in several directions, as shown in Figure 1-1, in
order to fill expanding use concepts. In addition, the basic M6800 Family has been enhanced. A large number of peripheral devices have been developed to support the expanding family of microprocessors and microcomputers.

FIGURE 1-1. GENEALOGY OF THE COHESIVE
M6800 MICROPROCESSOR/MICROCOMPUTER FAMILY
6.0
5.0
4.0
3.0
2.5

2.0
1.5
1.2

1.0
0.75
0.6
0.5
0.4

1975

1976

1977

1978

1979

1980

1981

1984

INTRODUCTION YEAR

8-BIT MICROPROCESSORS (MPUs)
MC6800 - MC6802 - MC6803 - MC6808 MC6809 - MC6809E - MC146805E2
The MC6800 MPU was the first of the M6800 MPU Family and still remains a highly
cost-effective processor for a great many process-control and data-communications applications. Seventy-two instructions and six different addressing modes give it powerful
capability, and a full range of compatible peripheral chips offer the widest possible latitude
in system implementation. After years of field experience, the MC6800 has earned an
enviable reputation as one of the easiest-to-use processors available.

1-2

Moreover, to tailor the system to your specific needs at the lowest cost, the MC68DD (and
its peripherals) is available in three different packages, three different temperature ranges,
and three speed ranges, as follows:

The MC6802 MPU has all the attributes of the basic MC68DD, but it reduces the component count of a minimum microcomputer system to only two.
The MC68D2 adds an on-chip clock oscillator and 128 bytes of RAM to the capability of
an MC68DD. Data in the first 32 bytes of the built-in RAM can be retained in a lower-power
mode by an external power source, allowing memory retention during a power-down
situation.
Using this microprocessor, a minimum microcomputer system consists of:
11-

MC68D2 Microprocessing Unit
MC6846 ROM-I/O-Timer Unit

Of course, the system is expandable to any requirement with the adapters, expanders,
and other peripheral chips that are a part of the M68DO Family.

The MC6803 MPU is the microprocessor version of the MC6801 single-chip microcomputer. The MC6803 accommodates applications where external ROM is present. With 13
parallel input/output lines, a 16-bit timer, and a serial communications interface the MC6803
offers a great deal of freedom in system needs. One of the most desirable attributes of
the multigeneration MC6803 is its compatibility with existing software and hardware. The
MC68D3 easily meets this goal by being thoroughly integrated into the total M68DD family
of components. In addition, since the MC6803 is an HMOS device, it requires only a single
+ 5 volt power supply and interfaces with both TTL and MOS peripherals. The concept
of an integrated family of devices is predicated on continuity in both design and development. As a member of the M680D family, the MC6803 shares many of the attributes of
the basic MC68DO MPU. For example, the MC6803 encompasses the full MC68DO instruction set, yet new instructions have been incorporated for even greater system capability
and ease of programming. Many MC6803 instructions execute in fewer cycles than on the
MC68DO. More and faster instructions increase throughput and reduce software conversion
and development time. Some of the features of the MC6803 are:
•
•
•
•
•
•
•
•
•
•

Expanded MC6800 Instruction Set
Full Duplex Serial Communications Interface
Upward MC680D Source and Object Code Compatibility
16-Bit Timer with Three Modes
16-Bit Multiplexed Address Bus Providing 64K-Byte Memory Space
128 Bytes of On-Chip RAM (64 Bytes Retainable with Battery Backup)
13 Parallel 1/0 Lines
Internal Clock (Divide-by-Four)
TTL-Compatible Inputs and Outputs
Interrupt Capability (Maskable and Non-Maskable)

The MC6803E was designed for uses in which the internal clock needs to be synchronized
with system, peripherals, or other MPUs. The MC6803E also supports DMA and dynamic
RAM refresh with its halt (HALT) and bus available (BA) pins. Other features include:
1-3

I

I

•
•
•
•
•
•
•
•
•
•
•
•

Enhanced MC6800 Instruction Set
Upward Source and Object Code Compatible with the MC6800
Bus Compatible with the M6800 Family
Direct Source and Object Code Compatible with the MC6801
8 x 8 Multiply Instruction
64K Memory Map (Unused High Order Address Lines Can Be Used as Input Lines)
External Clock Inputs (E and AS) Allow Synchronization
Serial Communications Interface (SCI)
16-Bit, Three-Function Programmable Timer
128 Bytes of RAM
64 Bytes of RAM Retainable During Power Down
Pin-for-Pin Compatible with MC6801 Except for HALT and BA Pins

The MC6808 low-cost version of the MC6802 microprocessor has an on-chip clock
oscillator and driver, but no on-chip memory. The MC6808 can use up to 64K of external
RAM, ROM, or peripherals.

The MC6809 microprocessor, with five internal 16-bit registers, offers up to five times
higher performance than the MC6800, yet, due to the 8-bit bus is fully compatible with all
M6800 bus-oriented supplementary circuits and peripherals. Here's how the MC6809
stacks up:
Architectural Improvements:
• Additional 16-Bit Index and Stack Registers
• Direct Page Register
• Increased Addressing Modes
• 16-Bit Operations and 16-Bit Accumulator
.8 x 8 Multiplier
• Fast Interrupt
Software Improvements:
• Designed for efficient handling of high-level languages, including Pascal, Basic,
MPL, Cobol, and Fortran.
• Position-independent coding and reentrant-programming capability encourage development of "canned software," with modular program interchangeability.
• Structural, high subroutined code enhanced by two 16-bit index registers and program counter usable for indexing.
• Multi-task and multi-processor organization.
• Stack-oriented compiler instructions with both user and hardware stack registers
available.
Although the MC6809 is compatible with the extensive existing M6800 Family, Motorola
is designing even more peripherals to enhance systems designed with the MC6809. These
new peripherals (e.g., the MC6829 Memory Management Unit, the MC6839 Floating Point
ROM, and the MC6855 Serial DMA Processor) allow an MC6809 user to realize the full
potential of the processor.
1-4

The MC6809 is a logical step for applications that crowd the capacity limits of today's
conventional 8-bit processor - yet, hardware and software (upward) compatibility with
existing M6800 processors protects previous software investment.
The MeSSOgE includes all the features of the MC6809 plus external clocking to provide
the flexibility required in a mUlti-processor system.

The MC146805E2 initiates the CMOS side of Motorola's microprocessor family. Batteryoriented and noise sensitive applications have long sought an M6800 MPU implemented
in CMOS. The MC146805E2 includes an 8-bitoptimized processor the equal of the MC6800
in speed and performance, plus on-chip RAM, timer, parallel 1/0 ports, and clock oscillator.
Complete CMOS systems are assembled using the MC146823 Parallel Interface,
MC146818 Real-Time Clock plus RAM, MCM65516 CMOS 2K ROM, and many MSI and
SSI support parts. The MC146805E2 also serves as a ROMless prototype device for the
CMOS and HMOS M6805 Family single-chip MCUs.
The processor has sixty-one basic instructions that are similar to those of the popular
MC6800 microprocessor, plus some unique enhancements. A complete set of bitmanipulation and test instructions allow any bit in RAM or any 1/0 pin to be individually
set or cleared or tested as a conditional branch, all with a single instruction. The table
look-up indexing modes have also been enhanced and made more ROM efficient.
The very low power requirement of static CMOS make the MC146804E2 family of processors and peripherals extremely attractive for those applications where power is a major
consideration (portable instruments, telecommunications, point-of-sale terminals, remote
instrumentation, industrial control, applicance controllers, etc.). The operating voltage
range is from 3 to 6 volts, while current usage ranges from microamps upward depending
upon frequency, voltage, standby modes, and operating duty cycle. Other MC146805E2
features include:
•
•
•
•
•

•
•
•
•
•

Expansion Bus Addressing 8K Bytes of Memory
112 Bytes of RAM
16 Bidirectional 1/0 Lines in Addition to the Bus
2 Program Initiated Low-Power Standby Modes
Timer/Counter:
- 8-Bit Programmable Counter
- 7-Bit Software-Selectable Prescaler
- External Timer Input
- Maskable Timer Interrupt
Maskable External Interrupt
40-Pin Package
Fully Static Operation for Lower Power Needs
Oscillator Frequency to 5 MHz at 5 V
Compatible ROM Available - MCM65516 (2K x 8)

The MC146805E3 is an expanded version of the MC146805E2 that includes a 64K
memory addressing capability.

1-5

I

8-BIT MICROPROCESSORS FEATURES MATRIX
RAM

I

Device
MC6800
MC6802
MC6802NS
MC6803
MC6803NR
MC6803E
MC6808
MC6809
MC6809E
MC146805E2
MC146805E3

Tech

Pins

NMOS
NMOS
NMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
CMOS
CMOS

40
40
40
40
40
40
40
40
40
40
40

ax
128
128
128

128

1/0
Lines

Special
1/0

-

-

-

-

13
13
13

-

-

112
112

16
16

Serial
Serial
Serial

-

-

-

-

Mnem Ext Data
Inst1 Addr Size
72
72
72
82
82
82
72
59
59
61
61

64K
64K
64K
64K
64K
64K
64K
64K2
64K2
8K
64K

8
8
8
8
8
8
8
8
8
8
8

Clock
No
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes

Timer

16-Bit
16-Bit
16-Bit
-

} 8-Bit +
. Prescaler

NOTES:
1. Some Mnemonic Instructions can have many Opcode Instructions. As a result a Microprocessor normally has many
more Opcode Instructions than Mnemonic Instructions. For instance the MC6809 has 59 Mnemonic Instructions and
1464 Opcode Instructions.
2. Two megabytes when used with the MC6829 Memory Management Unit.

1-6

PERIPHERAL AND INTERFACE COMPONENTS
Motorola manufactures and is continuing in new design efforts to provide you with an
extensive selection of efficient, cost effective peripheral and interface components.

I
PERIPHERAL AND INTERFACE COMPONENTS SELECTOR GUIDE
FOR NMOS/HMOS MICROPROCESSOR SYSTEMS
Page
For MC6800 Two-Phase Clock Generation
MC6875 - Two-Phase Clock Generator .............................................................. 3-555
For Parallel-Oriented Applications
MC6821 - Peripheral Interface Adapter ............................................................... 3-307
MC6822 - Industrial Interface Adapter ................................................................. 3-317
MC6840 - Programmable Timer .......................................................................... 3-397
For Serial Applications
MC6850 - Asynchronous Interface Adapter ........................................................
MC68HC51 - Asynchronous Communications Interface Adapter ......................
MC6852 - Synchronous Serial Data Adapter .....................................................
MC68HC53 - Asynchronous Communications Interface Adapter ......................
MC6854 - Advanced Data Link Controller ..........................................................

3-494
3-503
3-506
3-520
3-524

For Complex Peripheral Control
MC6829 - Memory Management Unit ................................................................
MC68HC34 - Dual-Port RAM Memory Unit ........................................................
MC6835 - CRT Controller ...................................................................................
MC6839 - Floating Point ROM ............................................................................
MC6844 - Direct Memory Access .......................................................................
MC6846 - ROM - I/O - Timer .........................................................................
MC6859 - Data Security Device .........................................................................
MC68120/MC68121 - Intelligent Peripheral Controller .......................................

3-326
3-342
3-350
3-382
3-410
3-450
3-546
3-618

For Display
MC1372 MC6845 MC6847 MC2670 MC2671 MC2672 MC2673 MC2674 MC2675 -

Color TV Video Modulator ................................................................. 3-2
CRT Controller ................................................................................... 3-427
Video Display Generator .................................................................... 3-469
Display Character and Graphics Generator (DCGG) ......... ....... ... ..... 3-10
Programmable Keyboard and Communications Controller (PKCC) .. 3-24
Programmable Video Timer Controller (PVTC) ................................. 3-47
Video Attributes Controller (VAC) ...................................................... 3-74
Advanced Video Display Controller (AVDC) ...................................... 3-87
Color/Monochrome Attribute Controller (CMAC) ............................... 3-119

1-7

PERIPHERAL AND INTERFACE COMPONENTS
SELECTOR GUIDE (CONTINUED)

I

For Memory

Page

MCM6810 - 128 x 8-Bit Static Random Access Memory ............... 3-302
MCM6836E16/MCM6836R16 - 128K-Bit Combination
ROM/EEPROM Memory ......................................... 3-371
For System Expansion
MC3440A, 3441A, 3443A - Quad Interface Bus Transceivers ............
MC3446 - Quad Bidirectional Bus Transceiver .......................
MC3447 - Octal Bidirectionallnst. Bus (GPIA) Transceiver .............
MC3448 - Quad Bidirectionallnst. Bus (GPIB) Transceiver .............
MC3482/MC6882 - Octal Buffer/Latch ..............................
MC6880A/MC68T26 - Quad Bus Transceiver .........................
MC6889/MC8T28 - Quad Bus Transceiver ...........................
MC6885/MC8T95, MC6886/MC8T96, MC6887/MC8T97, MC6888/MC8T98 Hex Three-State Buffer/lnverters ..................................
MC6890 - 8-Bit MPU D/A Converter .................................

3-131
3-135
3-138
3-144
3-571
3-566
3-606
3-601
3-611

For CMOS Systems
MC146818 - Real-Time Clock plus RAM ............................. 3-697
MC146823 - Parallel Interface .................................... " 3-719

1-8

Reliability

2-1

I

RELIABILITY AND QUALITY
MONITOR REPORT
OCTOBER 1983

I
Introduction
Motorola conducts extensive reliability tests to qualify devices, to evaluate process and material
changes and to accumulate generic performance data. The results of these tests provide the basis
for production decisions and the generation of reliability reports for customer use. The following
report provides an overview of reliability testing on Motorola's MOS Microprocessor Components
conducted during 1982. Included in the report are summary results of dynamic life testing and thermal
performance testing for plastic and ceramic packaged devices, and moisture performance testing
for plastic parts. Results of the tests are detailed below.

Dynamic Life
Dynamic life, or high temperature operating life, is performed to accelerate failures resulting
from thermally activated defects. Failure mechanisms detected during life test include die related
defects which occur during wafer processing and both die and package related defects which occur
during assembly.
Stress is generated through the application of a 5 volt dynamic bias and an ambient temperature
of 125°C. A dynamic bias is considered more effective than static bias for LSI Microprocessor devices
because a large percentage of the chip can be continuously exercised. During life test, devices are
exercised using a ,common mid-range frequency clock signal which is typically 500KHz or 1MHz.
Devices are electrically tested after 168, 504, and 1008 hours using computer controlled testers
which employ functional patterns under worst-case supply and clock conditions. Pass/fail criteria are
established for each circuit type based on functionality and data sheet limits for AC and DC parameters. Devices which fail to meet a test criterion are segregated by failure mode and data logged,
and failure analysis is performed, when appropriate, to establish associated failure mechanisms.
Life test failure rates are calculated using the Chi-Square distribution and a 90% confidence level
(see Appendix A). This 90% confidence level is more stringent than the 60% level used in the 1981
report. The accompanying increase in failure rates for individual device types is a result of tightening
the confidence level and does not indicate a reduction in the reliability of the devices. Tables 1 and
2 summarize the 1982 dynamiC life test data for MOS Microprocessors.

Test results contained herein are for information only. This report does not alter
Motorola'S standard warranty or product specifications.

2-2

TABLE 1.
SUMMARY OF DYNAMIC LIFE TEST RESULTS

Device
Type

Technology
NMOS

MC6800
MC681 0
MC6821
MC6822
MC6840
MC6844
MC6845
MC68652
MC68653
MC68661

TOTAL
HMOS

MC6801
MC6805P2
MC6805R2
MC6805U2
MC6809
MC68000
MC68008
MC68230
MC68451
MC68705P3

TOTAL
CMOS

MC141200
MC146805E2
MC146805G2
MC146818

TOTAL
GRAND TOTAL
111 90%

Test
Devices

125°C
Device Hours

70°C
Equivalent
Device Hours

Failures

Failure
Rate*
FITs

45
90
448
83
45
45
346
45
134
45

45,360
89,040
451,584
83,664
45,360
45,360
346,752
45,360
135,072
45,360

2.2 x 106
4.6 x 106
24.1 x 106
4.9 x 106
2.5 x 106
2.7 x 106
19.5 x 106
1.9 x 106
5.3 x 106
2.5x106

0
2
0
0
0
0
2
0

0
0

1050
1150
100
470
920
860
270
1200
440
920

1,326

1,332,912

70.2 x 106

4

110

704
224
171
86
225
262
168
126
88
268

702,672
212,352
170,520
80,808
225,960
262,080
169,344
120,456
88,704
265,248

106
106
106
106
106
106
106
106
106
106

3
0
1
0
1
2
0
3
0
2

250
240
370
770
580
350
340
960
480
340

2,322

2,298,144

105.1 x 106

12

170

135
89
178
89

135,576
83,352
171,192
88,872

14.1 x 106
8.8 x 106
17.2x106
7.4 x 106

1

0
3
0

270
260
390
310

491

478,992

47.5 x 106

4

170

4,139

4,110,048

222.8 x 106

20

120

Confidence Level

2-3

27.1
9.7
10.1
3.0
6.3
15.0
6.8
7.0
4.8
15.3

x
x
x

x
x
x
x

x
x
x

I

TABLE 2.
MICROPROCESSOR FAMILY DYNAMIC LIFE TEST RESULTS

Total
Devices

125°C
Device Hours

70°C
Equivalent
Device Hours

Failures

Failure Rate
FITs

*

WAFER PROCESS TECHNOLOGY
1,326

1,332,912

HMOS

2,322

2,298,144

CMOS

491

478,992

NMOS

I

x 106
x 106
47.5 x 106
70.2

4

110

105.1

12

170

4

170

PACKAGING SYSTEM TECHNOLOGY
Ceramic

1,875

1,858,176

Plastic

2,264

2,251,872

TOTAL

4,139

4,110,048

*90% Confidence

x 106
118.5 x 106
222.8 x 106
104.3

12

170

8

110

20

120

Level

SUMMARY:
The overall life test results for 1982 show a very significant improvement over our 1981 data base
(Reliability Report 8238). For 1982 we tightened our confidence level from 60% to 90%. The failure
rate for 1982 was 120 FITs at a 90% confidence level as compared with 250 FITs at 90% confidence
level for 1981. The major effect of tightening the confidence level from 60% to 90% is to increase
the predicted failure rate of individual devices with limited device hours. For example, the predicted
failure rate for the MC6800 using 60% confidence is 420 FITs. The predicted failure rate for this
same device using the 90% confidence is 1050 FITs, or more than double. This makes a statistically
significant comparison of the individual device failure rates very difficult. It is more beneficial to
examine the failure rate of the process technologies (NMOS, HMOS, CMOS) or the packaging
technologies (plastic and ceramic) in which there are a considerable number of device hours which
reduce the impact of the confidence level change. Even with the statistical tightening for 1982, the
process and package technologies have achieved a reliability improvement as measured by dynamic
life test when compared with the 1981 data base.

Plastic Package Environmental Performance
The use of plastic encapsulation for packaging of integrated circuits has met with widespread
customer acceptance throughout the semiconductor industry because it is lighter, less expensive,
and more resistant to physical damage than ceramic packaging. However, there are several reliability
concerns in plastic packages: contamination, moisture resistance, wirebond integrity, and thermal
performance. Dynamic life test results show no significant difference between plastic and ceramic
device performance; this demonstrates that Motorola's careful selection of materials and rigid control
of processes has eliminated any plastic-related performance degradation. The following section
addresses the other reliability concerns of plastic parts: corrosion, wirebond integrity, and thermal
performance.

2-4

Moisture Related Performance
In plastic integrated circuits, moisture present in the package can cause an increase in the corrosion
rate of the die metallization, if ionic contaminants are present, resulting in failures when the device
is in use. Moisture may reach the interconnect metallization along the leadframe-molding compound
interface or through the bulk of the plastic. The combination of moisture, ionic contaminants carried
in with the moisture or present in the plastic, and an electric field creates an electrolytic cell which
becomes a corrosion site.
To help prevent corrosion problems, Motorola uses a molding compound which forms a compressive bond around the leadframe which, when cured, produces a tight seal to minimize microgaps.
Tighter control of contamination sources throughout the manufacturing process, improvements in
passivation and improved metallization techniques have resulted in lower defect density and more
complete passivation coverage, keeping moisture from penetrating to the-die surface.
Two accelerated tests are used by Motorola to assess the level of performance achieved by the
combined application of these corrosion-prev'9ntion measures: Autoclave and Temperature Humidity
Bias (T.H.B.). 1982 moisture performance test results are detailed below.

Autoclave
Autoclave testing uses a combination of temperature, humidity, and pressure to accelerate moisture
ingress along the leadframe-molding compound interface path. The absence of a bias keeps device
power dissipation from acting as a moisture barrier, increasing the probability that moisture will reach
the die if a part is defective.
Autoclave test conditions include 121°C, 100% relative humidity and 15 psig. Each test sample
is selected from a separate assembly lot and subjected to a minimum of 96 hours of stress; complete
parametric and functional tests are performed on all devices at each readpoint. In addition, some
devices are stressed for an additional 48 hours. All electrical failures are included in the data base,
not only those associated with corrosion on the die. Autoclave test results for ~ 982 are summarized
in Table 3.

TABLE 3.
AUTOCLAVE TEST RESULTS

121°C

100% R.H.

15 psig
48

96

144

6/3083

1/3076

2/1399

Percent Defective

0.1'9

0.03

0.14

Cumulative Percent Defective

0.19

0.22

0.36

Hours
Failures/Sample

Temperature Humidity Bias
Temperature Humidity Bias (T.H.B.) testing is used to evaluate the moisture resistance of plastiC
devices by employing the severe conditions of 85°C, 85% relative humidity, and 5 volts to accelerate
corrosion of the metallization. The biasing circuits used in T.H.B. testing create static electric fields
between adjacent pins and metallization stripes, maximizing the effect of electrolytic cells while
minimizing the power diSSipation. A typical T.H.B. biasing scheme would include: all I/O or output
pins either open or with resistive terminations; enable pins are disabled; and all other pins have
alternate VDD and VSS on adjacent pins. As with autoclave, the expected failure mode is corrosion
of the die metallization.

2-5

I

Each T,H.B. sample is sourced from a separate assembly lot and tested for a period of 1008
hours. Complete parametric and functional test programs are typically performed at the 168, 504,
and 1008 hour read pOints using computer controlled testers. The pass/fail criteria used for life test
are also employed with T.H.B. samples. A worst-case analysis is presented since all electrical failures
are considered instead of only those associated with corrosion mechanisms. Results for 1982 are
summarized in Table 4.

I

TABLE 4.
TEMPERATURE HUMIDITY BIAS TEST RESULTS
85°C
85% R.H.
5.0 VOLTS
Hours

168

504

1008

2/1456

4/1796

5/1781

Percent Defective

0.14

0.22

0.28

Cumulative Percent Defective

0.14

0.36

0.64

Failures/Sample

A Weibull plot (Figure 1) shows the continued improvement in TH.B. performance as measured
in 1979, 1980, 1981 and 1982.

50.0

10.0

-

5.0
1979

Q)

.2

'ro

u.
E
Q)

C,)

1.0 ~
0.5

Q;

-

""......-

0.1

-""'"

-

1980
1981

irroo"""""

_i-""""""

-- -.,,-- _.....

-"""

-

-'"

........... -"" ----,

~

-- -----~

CL

..-

l--" ~

-

-'" ~ ...

.,..-"""

....-

,,-

-....-,

...

-

--

. .. -~

--

.,.. ....

......

...... -~
1982

0.05

0.01

I

I

168

336

504

1008
Test Time in Hours

10 K

FIGURE 1. WEIBULL PLOT OF TEMPERATURE HUMIDITY BIAS TEST RESULTS

2-6

Thermal Cycling Performance
Thermal cycling accelerates the stressing effects of thermal expan~ion mismatch between the
various components of the plastic and ceramic packaging systems through rapid successive ex~
cursions to high and low temperature extremes. Temperature cycle and thermal shock are two tests
which are used to determine the effects of these stresses on package integrity, especially wire bond
and die bond integrity. These types of failure modes follow the classical wearout mechanism pattern
(Le. an increasing failure rate with increased cycles of exposure.)

Temperature Cycle
The integrity of wire bonds and die bonds in plastic packages can be accurately evaluated through
temperature cycle testing. Military Standard 8838, Method 1010.4, Condition C is employed to
permit easy comparison of results with other industry sources.
Devices are inserted into the cycling system and held at - 6SoC for at least ten minutes. Following
the cold dwell, devices are heated to 1S0°C during a transition time of five minutes maximum, after
which devices dwell at 1S0°C for a minimum of ten minutes. They are then cooled during a similar
transition period to - 6SoC after which the cycle is repeated. The system employs a circulating air
environment to assure rapid stabilization at the specified temperature. The dwell at each extreme,
plus the two transition times, constitutes one test cycle (approximately 30 minutes).
Electrical measurements and high temperature continuity tests are typically performed after 100,
sao and 1000 cycles. The predominant failure mechanism in the ceramic packaged product is wire
bond breakage above the ball near the die where the heat and stress of the bonding process reduce
the strength of the wire. The predominant temperature cycle activated failure mechanisms in plastic
encapsulated circuits are die lift and die crazing/cracking due to inadequate die wetting/curing and
mold compound stresses on the die, respectively. Results of the test are shown in Table S.

TABLE 5.
TEMPERATURE CYCLE TEST RESULTS
- 65°C to + 150°C
AIR TO AIR

Cycles

100

500

1000

7/3103

5/3081

8/3050

Percent Defective

0.23

0.16

0.26

Cumulative Percent Defective

0.23

0.39

0.65

Failures/Sample

Thermal Shock
Thermal shock is an environmental test performed in accordance with Military Standard 8838,
Method 1011.3, Condition C. The objective of this test is the same as that for temperature cycle
- to emphasize differences in expansion coefficients for components of the packaging system.
However, thermal shock provides a more severe stress than temperature cycle in that the devices
are exposed to a more sudden change in temperature due to the higher thermal conductivity and
heat capacity of the liquid ambient.
Devices are placed in a fluorocarbon bath cooled to - 6SoC. After being held in the cold chamber
for at least five minutes, the sample is transferred in less than ten seconds to an adjacent chamber
filled with fluorocarbon at 1S0°C and held for an equivalent time. The dwell time at each endpoint,
plus the total transition time, constitutes one test cycle (approximately ten minutes). Thermal shock
endpoint electrical measurements and high temperature continuity tests are typically performed
at 100, SOO, and 1000 cycles. Results of thermal shock tests performed in 1982 are shown in
Table 6.

2-7

I

TABLE 6.
THERMAL SHOCK TESTS RESULTS
- 65°C TO + 150°C
LIQUID TO LIQUID
100

500

1000

Failures/Sample

1/941

1/967

9/955

Percent Defective

0.11

0.10

0.94

Cumulative Percent Defective

0.11

0.21

1.15

Cycles

I

Conclusions
Reliability testing performed by Motorola MaS Microprocessor Division during 1982 has produced
excellent results. The specific test results included in this report are representative of Motorola MaS
Microprocessor components expected field performance. Failure rate estimates have been based
on the outcome of tests and data analyses which are widely accepted. Life test failure rates on both
ceramic and plastic packaged devices are significantly reduced over those reported previously.
Moisture resistance testing indicates extremely high performance of Motorola MaS Microprocessor
plastic encapsulated circuits. Thermal integrity testing shows that there are few failures, which
typically occur only after extensive exposure to temperature extremes greater than those seen in
field applications. The level of performance predicted by these test results is among the best available
in the industry and far exceeds the requirements of most applications. Comparison to previous
reports (Reliability Report 8238) verifies a history of continuous improvement which has made
Motorola MaS Microprocessor components the optimum choice for reliable performance.
Copies of this and other reliability reports may be obtained from your local Motorola representative.
For additional information contact Microprocessor Reliability Engineering 512-928-6640 or write to:
MOS Microprocessor Reliability Engineering
Motorola Incorporated
3501 Ed Bluestein Blvd.
Austin, Texas 78721

2-8

APPENDIX A.
QUALITY AND RELIABILITY SYSTEM
A complete Reliability and Quality Assurance system is in place to monitor and control the performance of Motorola's MOS Microprocessor Components. Incoming Quality Control inspects starting
wafers, masks, chemicals, package piece parts and molding compounds. Process Engineering and
In-Process Quality Control perform step-by-step monitoring of the wafer process to check oxidation,
diffusion. photolithography, ion implantation, polysilicon deposition, metallization, passivation, and
other process operations. Final visual, class probe, and capacitance-voltage plots complete the wafer
area inspections. Environmental monitors are also performed for air cleanliness, water quality, temperature and humidity.
In the assembly area, In-Process Quality Control performs monitors on- equipment performance
and gate inspections at the major process steps on all lots. The Outgoing Quality Control group
continues this philosophy in the final test area by performing electrical and visual-mechanical gates
on every lot. The electrical inspection, which consists of AC, DC and functional tests, is performed
to a 0.1 % (maximum) Acceptable Quality Level (AQL) sampling plan. The visual/mechanical inspection is also performed to a 0.1 % AQL sampling plan. Any lot which fails either of these gates
is returned to production for 100% rescreen. A Quality Engineering organization exists to approve
final test programs and support the Outgoing Quality Control organization. Test programs are tailored
to assure all required speCifications are met or the devices are rejected.
The Reliability Engineering organization is responsible for performing qualifications of new deSigns
and process changes prior to introduction. In addition, Reliability Engineering establishes and maintains monitor programs to assure processes stay in control once they are qualified. Results from
these programs provide rapid feedback to correct problems as they occur.
Supporting these efforts is the Metrology Laboratory which includes both a Standards and a
Calibration Laboratory to provide National Bureau of Standards traceability to all production
measurements.
Also offering required support are a Chemical Laboratory with such equipment as a gas chromatograph/mass spectrograph and X-ray fluorescent systems for detailed incoming chemical analyses; a Surface AnalysiS Laboratory whose equipment includes a Scanning Electron Microscope
(S.E.M.) and a Scanning Auger Microprobe (S.A.M.); and a Product Analysis Laborabory for detailed
analyses of failure modes and mechanisms for Microprocessor devices.

2-9

I

I

MOS Reliability & Quality Assurance Operations

I

I

I

I

Microprocessor
Division
R&QA
Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Burn-In

Memory
Operation
R&QA
Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Burn-In

I

Logic and Special Functions
Operation
R&QA

1
I

I

I

Reliability Engineering
QA Engineering
QC Gate
Lot Processing
Environmental Laboratory

~
~

o

I

R&QA
Technical
Services

I

I

R&QA
Business
Services

Wafer
Operation
R&QA

I

!

I

I

Product Analysis
Laboratory
Technical Writing
Statistical Training
Assembly R&QA
Engineering
Data Base Computer
System

Specifications
Metrology Laboratory
Warehouse Final
Inspection
Customer Notification
Returned Material

Wafer In Proce~s QA
Wafer R&QA Engineering
Analytical Services

FIGURE A. RELIABILITY AND QUALITY ASSURANCE ORGANIZATION

APPENDIX B.
PACKAGING SYSTEMS
Motorola Microprocessor devices are produced in plastic, CERDIP and sidebraze packages. The
ceramic package types are hermetically sealed to protect the integrated circuit from environmental
factors and permit operation over extreme temperature ranges. Although plastic devices are not
hermetic, modern epoxies exhibit extremely high moisture resistance, and long lifetimes may therefore be expected from these devices in typical environments.

Plastic
In recent years, plastiC encapsulated devices have gained widespread acceptance throughout the
electronics industry. Improvements in materials and process controls have resulted in significant
improvements in reliability performance. In addition, plastic packages have the advantage of low
cost and physical strength. Through careful selection of molding compound, leadframe material, and
assembly methods, Motorola produces plastic packaged ICs with reliability suitable for nearly all
applications.
Encapsulated integrated circuits incorporate the simplest processing and package construction
of the various systems available. The die is attached to a leadframe, wire bonded and encapsulated
using an epoxy novolac molding compound. The die may be attached to the leadframe by epoxy
or by any of a variety of eutectic forming metal preforms. Wire bonding may be thermocompression
or thermosonic, but the wire is always gold. This system has evolved from early industry experiments
with aluminum ultrasonic wire bonding which experienced high rates of opens and intermittents. The
encapsulant is the most critical component of the system since it controls contamination, moisture
resistance, and stress effects. Epoxy novolacs have become the industry standard molding compound since they combine excellent characteristics in all these areas.
The plastic package is, by far, the most resistant to physical damage since the die is completely
encapsulated and 'cavity hermeticity is not a concern. Since the package is light in weight and the
plastiC is less brittle than ceramic, chipping and cosmetic damage are not problems, The leadframe
and plating are equivalent to CERDIP, and modern epoxies pose no danger from contamination,
In comparing plastiC to ceramic packages, there are two characteristics to be considered: moisture
resistance and thermal characteristics. Microprocessor plastiC products perform very well on moisture
resistance related tests. This is due to advances in molding compounds, and the characteristic low
voltages and moderate power dissipation of Microprocessor products. In most instances, plastic
devices will provide excellent performance, essentially equivalent to hermetic performance. Thermal
resistance has been improved dramatically through the introduction of copper leadframes and heatspreaders. During 1982 and 1983, a large number of Microprocessor devices will be converted from
Alloy 42 to copper leadframes to take advantage of the better thermal conductivity of copper. This
results in lower junction temperatures, and subsequent improvements in electrical characteristics
and reliability performance.
Another approach to lower thermal resistance for devices with high power dissipation is plastic
assembly using a heatspreader. The heatspreader is an anodized aluminum piece part that sits
below the plan~ of the leadframe. During the encapsulation process, the heatspreader is surrounded
by plastic and becomes part of the package structure. Heatspreaders, when used in combination
with Alloy 42 leadframes, yield a thermal resistance roughly equivalent to a copper leadframe plastic
device, or to a ceramic device. Devices which contain a heatspreader employ the suffix "G" to
designate this package type. The MC6801 Microprocessor Family has been offered in this package,
and the 64-pin MC68000 16-bit Microprocessor is being offered in a heatspreader package.

2-11

I

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The sidebraze, or solder seal, package is composed of three layers of alumina which are screened
with refractory metal such as tungsten or moly manganese and fired together to form the package
body with a cavity for the die. The refractory metal is then plated and Alloy 42 leadframes are brazed
to the bottom, sides or top of the package, depending on the vendor, The advantage of the sidebraze
version is accurate lead alignment without the need for forming. The final piece part operation is
plating which may be gold, or tin with a selective gold plate in the cavity. Although epoxy die bonding
is feasible in this package - due to the higher sealing temperature, most manufacturers, including
Motorola, employ a eutectic bond. Both aluminum ultrasonic wire bonding and gold thermocompression bonding are used.

2-13

I

I

Some tradeoffs exist in the performance characteristics of the two hermetic packages as they are
offered by Motorola. Both typically are ceramic, hermetic, employ a eutectic die bond, use ultrasonic
aluminum wire bonding, and have tin plating. The thermal resistance of the packages is very similar,
with the sidebraze having a slight advantage. Both packages perform well on the standard thermal
and mechanical environmental tests, but each is susceptible to handling damage. Loose shipping
rail packaging or high velocity impacts during testing can chip the sidebraze package and sever the
interlayer metallization. This type of handling will not affect the 1O-mil-thick leadframe of the CERDIP
package, but hermeticity failures can occur. The CERDIP package is slightly thicker and heavier, but
no conductive surfaces are exposed so the shorting potential in dense packaging is reduced. Extensive testing of 24, 28, and 40 lead CERDIP and sidebraze devices has indicated no significant
differences in reliability.
Some Microprocessor devices are now being offered in Leadless Chip Carriers (LCC). The primary
advantage of LCes is increased device density at the board or substrate level. Motorola currently
uses a 40-pin Lee that is essentially identical to the side braze dual-in-line in construction characteristics and assembly methods. Some MC68000 16-bit family devices will be offered in higher
terminal count LCCs, up to 68 terminals. Future plans include LCCs with single layer construction
and other package types offering higher packing density at the system level.

APPENDIX C.
FAILURE RATE CALCULATIONS
Environmental tests are designed to measure device resistance to unusual and severe stress, not
expected under normal operating conditions. Device performance under these conditions is eX
pressed as a percent of devices defective and compared to previous results. Life tests, on the other
hand, accelerate the use conditions of the device with temperature and voltage in a manner which
is more quantitatively correlatable to system operation. Life test failure rates are expressed as failures
per unit time and are calculated using established principles of probability and statistics.
The principles of reliability engineering have indicated that failure rates for semiconductor devices
will take the form of the "bathtub" curve (Figure C1).
n

2

o

l\-_____~___3_ __
)

t-I

FIGURE C1. OEVICE FAILURE RATE AS A FUNCTION OF TIME.

The following three regions are represented in the curve:
1. Infant Mortality - a region of high but rapidly declining failure rates, usually associated with
manufacturing defects.
2. Random Failures - a region of low, random failures caused by more subtle defects. This
area of the curve represents the useful part of device life ..
3. Wearout - a region of rapidly rising failure rates related to device wearout. Most semiconductors will not reach this stage before they are replaced because of changes in technology.
Techniques for calculating life test failure rates assume that the devices being tested have passed
infant mortality and entered the stable random failure portion of the life curve. Failures which occur
in this area are few and are known to approximate specific probability distributions. These probability
distributions are used to calculate sample failure rates which can be projected to the population in
general through the application of confidence limits. Techniques used to calculate life test failure
rates for microprocessors are discussed below.
A failure rate for any sample of life tested devices can be determined by dividing the number of
failures by the number of device hours. However. this rate will apply to that sample only. If you are
interested in projecting from the sample to the populations in general, you must establish confidence
limits. The application of confidence limits is a statement of how "confident" you are that the sample
failure rate approximates that for the population in general. To obtain rates with different confidence
levels it is necessary to make use of specific probability distributions which take the same form as
the actual failure distribution.

2-16

I

It has been determined that failures in semiconductors that have entered the middle portion of the
bathtub curve will approximate a Poisson distribution; this distribution applies when one has a large
sample with an extremely small number of events of interest, such as device failures. Given a
POisson failure process, a Chi-Square distribution can be used to establish confidence limits for
failure rates. Reliability Engineering has determined that the following general formula, which utilizes
values from a Chi-Square table, can be used to calculate failure rates for semiconductors:
1 x 10 5
A. =

I

X2 (0:, d.f.)

MTTF =

2t

(1 )

where:
A. = Failure Rate, %/1000 Hours
MTTF = Mean Time To Failure (Hours)
x2 = Chi-Square Function
100 - Confidence Limit
0: =
100

d.f. = Degrees of Freedom = 2r + 2
r = Number of Failures
t = Device Hours
To calculate the failure rate, first determine the level of confidence you require and calculate
degrees of freedom. Select the Chi-Square value from a Chi-Square distribution table with the
appropriate degrees of freedom and confidence level. Divide that value by twice the actual device
hours, at the temperature of interest.
The above formula applies for calculating a device failure rate, provided that the test is conducted
at system temperature. However, since we are unable to observe long-term effects which develop
over time, the test is accelerated through the application of a high temperature. In order to calculate
a failure rate at the ambient temperature of a system, a factor must be supplied to compensate for
the acceleration. The factor (Fa) which equates test temperature with rated temperature is derived
from the Arrhenius relationship:
Fa = exp ((elk) .

(.!. - .!.))
Tr

Tt

(2)

where:
Fa

Acceleration Factor
Activation Energy, eV
k = Soltzman's constant, 8.62 x 10 - 5 eV;oK
Tr = Junction Temperature, oK at the Rated Ambient of 70°C
Tt = Junction Temperature, oK at the Life Test Ambient of 125°C
=

e=

Motorola uses 70°C for the system temperature (To) to more closely approximate the actual temperature of the device during system operation and to supply a degree of conservatism to the failure
rate calculation.

2-16

Motorola uses an activation energy (8) value of 1.0 electron-volt. A 1.0 eV was selected as an
average value because a variety of different failure mechanisms exist for microprocessor and other
VLSI devices, with activation energies ranging from 0.40 eV for oxide related failures to 1.0 eV or
greater for contamination and metal related failures. Tr and Tt of the equation are the average
junction temperatures present at the rated and test ambients. Motorola uses junction, rather than
ambient temperature, because they produce acceleration factors that are more conservative and
representative of actual conditions. These temperatures are calculated as follows:

TJ = T A

+ PD' 8JA

(3)

where:
TJ = Junction Temperature, °C
TA = Ambient Temperature, °C
PD = Average Power Dissipation, Watts
6JA = Thermal Resistance - Junction to Ambient, °C Per Watt
Once this step has been completed, the acceleration factor can be calculated and applied as a
multiplier to the number of device test hours under accelerated test conditions to determine the
equivalent number of hours at rated operating conditions. To determine the failure rate at the operating
temperature, use equation (1) substituting the equivalent device hours at rated temperature for t in
the equation ..
Formula 1 provides a failure rate expressed in percent per thousand hours. This number, stated
as a percentage per each thousand hours of operation, is one way Motorola Reliability Engineering
expresses failure rates for Microprocessors. One other way of expressing failure rates is Failures
In Time (FITs) which refers to failed units per 109 device hours (1 FIT = A x 104).
Mean Time To Failure (MTTF) is another parameter frequently used to express failure rates. MTTF
is the average time to a failure of a non-repairable item such as a semiconductor and is expressed
as the reciprocal of the failure rate:
MTTF

=

2-17

.!.

A

(4)

I

APPENDIX D.
ELECTRICAL TESTING AND FAILURE CHARACTERISTICS

fI

The electrical measurements performed on reliability test samples were obtained using computer
controlled testers and programs employing exhaustive functional routines under worst-case supply
and clock conditions. Devices which do not meet a test criterion, including those failing for parametric
reasons, are first segregated into "bin outs" defined by the test program. A data log is obtained from
which each failing device is then assigned to one of six failure mode categories. An analysiS to
determine specific failure mechanisms is performed when the level or pattern of failure indicates
that it is appropriate. T.H.B. rejects are routinely decapsulated and inspected for corrosion of the
metallization.
The electrical test programs are typically constructed in the following manner:
1.
2.
3.
4.
5.

"Opens" test
"Shorts" test
Input Leakage
Functionality using nominal supply and input voltage levels and low frequency clock conditions
Functionality to data sheet parametric limits using worst-case combinations of VDO level and
clock frequency
6. Three-state leakage
7. Output buffer current drive capability
8. Power dissipation test
Failure modes categorized according to these tests do not always indicate a specific problem
and individual test programs may deviate from the sequence shown above as required for complete
testing of the specific device type. Microprocessors and other LSI logiC circuits do not readily lend
themselves to the identification of failure modes since their complexity creates an astronomical
number of possible combination, some of which are very subtle. Attempts to categorize these
modes by the test sequence invariably result in groupings which are not mutually exclusive or
related to phYSical mechanisms.
The distribution of failure modes and mechanisms observed during life testing appears to be
the result of random manufacturing anomalies and does not, therefore, indicate trends correlatable
to specific process or design deficiencies. These results are consistent with careful attention to
process controls and reflect Motorola's high priority for quality and reliability.

2-18

TABLE 01.
FAILURE MODE CLASSIFICATION

A.

OPENS - No electrical connection between an external terminal and corresponding die
circuitry (possible intermitent). MOS inputs are normally high impedance parts and opens are
detected by forward-biasing the substrate diode.

8.

SHORTS - An unintended resistive path of relatively low value between one terminal and
any other terminal.

C.

FUNCTIONAL - A failure of one or more output terminals to respond with a correct logical
state under nominal supply, clock, and VIH/VIL levels; a violation of the internal Boolean
relationship defined by the circuit design.

D.

INPUT LEAKAGE - A current of either polarity which exceeds data sheet limits for input
terminals. Large values of leakage are classified as shorts.

E.

THREE-STATE LEAKAGE - A current of either polarity which exceeds data sheet limits for
I/O terminals when under three-stated conditions. This parameter is also timing dependent
and, when catastrophic, is classified as a functional failure mode.

F.

PARAMETRIC - A broad classification of non-catastrophic failure modes which excludes
leakages but includes:
1, Failure to respond at one or more output terminals with a correct logical state under worst-

case supply, clock, and VIH/VIL conditions; usually the result of excessive propagation
delays, improper VOHNOL levels, or a dynamic logic state which should be static, etc.
Must be 100% functional under nominal conditions and may be associated with leakage
currents not previously detected.
2. Excessive power dissipation. For CMOS Microprocessors, leakage currents can be a significant contributing factor for this failure mode. Device is 100% functional.
3. Incorrect output analog voltage or current level not resulting in a functional failure.

2-19

I

APPENDIX E.
MICROPROCESSOR AVERAGE JUNCTION TEMPERATURES
AND GATE COUNTS
Average Junction
Temperature @T A = 70°C

MOS
Technology
NMOS

I

HMOS

CMOS

NOTES:

Device
Type
MC6800
MC6802/08
MC6810
MC6821
MC6844
MC6845
MC6846
MC6847
MC6850
MC6852
MC6854
MC68488
MC68652
MC68653
MC68661
MC68701

Ceramic

Plastic
A42
Cu

83
91
83
79
85
89
89
83
81
83
89
85
86

92
116
92
92
103
105
109
94
92
91
101
98
106

81
88
90
91
84
85
84
91
86
88

85
99

102

91

MC6801
MC6805P2
MC6805R2IU2
MC6809/E
MC6829
MC68000
MC68008
MC68120
MC68451
MC68705P3
MC68705R3

95
88
82
92
92
97
107
96

96*
106
108
117
117
95*

97
95
87
96
96

MC141000
MC141200
MC146805E2
MC146805F2
MC146805G2
MC146823

71
71
71
71
71
71

88
89

* Plastic package with molded-in heatspreader.
A42 Plastic package with Alloy 42 leadframe.
Cu Plastic package with copper leadframe.

2-20

72
72
72
72
72
72

Equivalent
Number of
Gates
1,367
3,633
1,083
450
1,000
750
3,755
833
580
907
1,400
893
6,442
3,200
4,200
11,267
8,533
4,833
6,430
3,000
3,293
12,667
12,667
9,644
12,233
8,833
14,433
2,425
2,425
4,333
5,633
5,800
867

APPENDIX F.
RELIABILITY AND QUALITY MONITOR PROGRAM
The Motorola MOS Microprocessor Reliability and Quality Monitor Program is designed to generate
an ongoing data base of reliability and quality performance for various categories of Microprocessor
products. The primary purpose of the program is to identify negative trends in the data so that
immediate corrective action can be taken. The program also allows Motorola to develop a large data
base of reliability and quality results that can be reported quarterly to customers,
For the reliability monitor tests, each quarter sample group is pulled from major categories of
product representing a matrix of processing and packaging technologies (see Sample Group chart).
Product mix, sample availability and equipment capacity may cause the specific sample group pulled
for a given quarter to vary from the chart shown. Each sample group has a specific set of reliability
tests associated with it that are appropriate for that product type based on our history for that
classification. At the end of each quarter, results are reported for all sample groups that have
completed testing.
The quality results that are reported are the electrical and visual/mechanical AOQ (Average
Outgoing Quality, given in parts per million defective) for the Microprocessor Division. This data
represents the summary of results from the QC gate operation performed on every lot during the
quarter. Electrical AOQ represents any AC, DC, or functional failure at any temperature (each lot
is typically gated at two temperatures: hot and either room or cold). Visual/mechanical AOQ represents failures such as bent leads, incorrect marking, marking permanency problems, and cracked
packages. The AOQ reported is the product of the process average (ratio of defective devices to
largest sample size) and the lot acceptance rate.
Following are brief descriptions of the various reliability tests included in this program:

High Temperature Operating Life
High temperature operating life (HoT.O.L.) testing is performed to accelerate failure mechanisms
which are thermally activated through the application of extreme temperatures and the use of dynamic
operating conditions. The temperature and voltage conditions used in the stress are typically 125°C
with a bias level at the maximum data sheet specification limit of 5.5 volts. All devices used in HTOL
test are sampled directly after final electrical test with no prior burn-in or other pre-screening. Testing
is performed per Mil Std 883B, Method 1005, with all streSSing dynamic and minimum test duration
1008 hours. Some sample groups will be extended beyond 1008 hours, some run at temperatures
higher than 125°C, and some at voltages higher than maximum rated voltage to look for the effects
of these variations.
Device equivalent hours assume the Arrhenius relationship using an activation energy of 1.0 eV
to extrapolate from the device junction temperature at 125°C to the junction temperature at 70°C.
Failure rates given in FITs are derived using the Chi-Square distribution to a 90% confidence limit.
A FIT is 1 failure per 109 device hours or 0.0001 %/1 000 Hours.

Temperature Humidity Bias
Temperature Humidity Bias (T.H.B.) is an environmental test performed at a temperature of 85°C
and a relative humidity of 85%. The test is designed to measure the moisture resistance of plastic
encapsulated circuits. A nominal voltage of 5 volts static bias is applied to the device to create the
electrolytic cells necessary to accelerate corrosion of the metallization. Testing is performed per
JEDEC Standard 22, Method A 101. Most groups are tested to 100 hours with some groups extended
beyond to look for longer term effects.

2-21

I

Autoclave
Autoclave, like T.H.8., is an environmental test which measures device resistance to moisture
penetration along the leadframe-plastic interface. Conditions employed during the test include 121°C,
100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism. Autoclave
is a highly accelerated and destructive test performed per JEDEC Standard 22, method A102. Testing
is routinely performed for 144 hours.

Temperature Cycle

I

Temperature cycle testing accelerates the effects of thermal expansion mismatch among the
different components within a specific packaging system. This test is typically performed per Mil
Std 8838, Method 1010, Condition C (-65°C to + 150°C), or JEDEC Standard 22, Method A104,
Condition 8 (-40°C to + 125°C). During temperature cycle testing, devices are inserted into a
cycling system and held at the cold dwell temperature for at least ten minutes. Following this cold
dwell, the devices are heated to the hot dwell where they remain for another ten minute minimum
time period. The system employs a circulating air environment to assure rapid stabilization a.t the
specified temperature. The .dwell at each extreme, plus the two transition times of five minutes each
(one up to the hot dwell temperature, another down to the cold dwell temperature), constitute one
cycle. Test duration is for 1000 cycles with some tests extended to look for longer term effects.

Thermal Shock
The objective of thermal shock testing is the same as that for temperature cycle testing - to
emphasize differences in expansion coefficients for components of the packaging systems. However,
thermal shock provides additional stress in that the device is exposed to a sudden change in
temperature due to the transfer time of ten seconds maximum as well as the increased thermal
conductivity of a liquid ambient. This test is performed per Mil Std 8838, Method 1011, Condition
C (- 65°C to + 150°C). Devices are placed in a fluorocarbon bath and cooled to - 65°C. After being
held in the cold chamber for five minutes minimum, the devices are transferred to an adjacent
chamber filled with fluorocarbon at + 150°C for an equivalent time. Two five-minute dwells plus two
ten-second transitions constitute one cycle. Test duration is normally for 1000 cycles with some tests
being extended to look for longerterm effects.

Data Retention
Data retention testing or high temperature storage is performed to measure the stability of programmed EPROM and EEPROM devices during storage at elevated temperatures with no electrical
stress applied. The devices are exposed to an ambient environment of 150°C per Mil Std 8838,
Method 1008, Condition C. An acceleration of charge loss from the storage cell is the expected
result. All groups are typically tested to 1008 hours.

RELIABILITY AND QUALITY MONITOR PROGRAM
SAMPLE GROUPS

Category
Name

Typical
Product
Types

Minimum Number of
Sample Groups/Qtr

NMOS
Plastic

6800 Family
3870, 6800, 6810
6821. 6845, Custom

8

HMOS
Plastic

6801 Family
6805 Family
6809 Family

4

CMOS
Plastic

CMOS Family
146805E2
146805G2

4

68000
Family
Plastic
(HMOS)

68000

CERDIP
(NMOS or
HMOS)

6800 Family
3870,6800,6810,
6821, 6845, 6801,
6805, 6809

Side
Braze

6800 Family
3870, 6800, 6810
6821, 6845, 6810,
6805, 6809

Leadless
Chip
Carrier

146805E2
146805G2
CMOS Family

68000
Family
Ceramic
(HMOS)

68000

EPROM MCU
(NMOS, HMOS
or CMOS)

68701
68705
1468705G2

2

2

Test Performed
No. Samples

(Typ.)

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
34
22
38

Pes
Pes
Pes
Pes

HTOL
THB
Autoclave
TCITS

45
36
38
38

Pes
Pes
Pes
Pes

HTOL
TCITS

45 Pes
38 Pes

TCITS

52 Pes

HTOL
TCITS

30 Pes
38 Pes

HTOL

45 Pes

HTOL
TCITS
Data
Retention

45 Pes
38 Pes

2

3

2

2

2-23

45 Pes

I

APPENDIX G.
QUALITY PERFORMANCE

I

The chart below gives the goals and actuals for the Microprocessor Division Electrical and Visual!
Mechanical AOQ (Average Outgoing Quality, given in parts per million defective). This data represents
the summary of results from the QC gate operations performed on every lot. Electrical AOQ represents any AC, DC, or functional failure at any temperature (each lot is typically gated at two
temperatures: hot, and either room or cold). Visual/Mechanical AOQ represents failures such as bent
leads, incorrect marking, marking permanency problems, and cracked packages. The AOQ reported
is the product of the process average (ratio of defective devices to largest sample size) and the lot
acceptance rate.
AVERAGE OUTGOING QUALITY

Goal

Electrical
AOQ (PPM)
Actual

(-)
(-)

(-)
(-)

Total 1979
Total 1980
Total 1981

3000
2500
1500

1st Qtr 1982
2nd Qtr 1982
3rd Qtr 1982
4th Qtr 1982

1200
1000
800
600

1045
868
492
636

1408
1934
1062
651

1st Qtr 1983
2nd Qtr 1983
3rd Qtr 1983
4th Qtr 1983

500
450
400
350

326
341
313

405
267
251

1st Half 1984
2nd Half 1984

275
275

1st Half 1985
2nd Half 1985

175
125

1986

100

2-24

4000
2000
1725

Visual/Mechanical
AOQ (PPM)
Actual

4500
2500
1920

Data Sheets

3-1

I

®

MC1372

MOTOROLA

COLOR TV
VIDEO
MODU LATOR C I RCU IT

COLOR TV VIDEO MODULATOR

SI LICON MONOLITH IC
INTEGRATED CIRCUIT

· .. an integrated circuit used to generate an R F TV signal from
baseband color·difference and luminance signals.
The MC1372 contains a chroma subcarrier oscillator, a lead and
lag network, a quasi·quadrature suppressed carrier DSB chroma
modulator, an RF oscillator and modulator, and an LSTTL com·
patible clock driver with adjustable duty cycle.

I

The MC1372 is a companion part to the MC6847 Video Display
Generator, providing and accepting the correct dc interconnection
levels. This device may also be used as a general-purpose modulator
with a variety of video signal generating devices such as video games,
test equipment, video tape recorders, etc.
•

Single 5.0 Vdc Supply Operation for NMOS
and TTL Compatibility

•

Minimal External Components

'_.SUFFIX

PLASTIC PACKAGE
CASE 646-05

Pin Connections

•

Compatible with MC6847 Video Display Generator

•

Sound Carrier Addition Capability

•

Modulates Channel 3 or 4 Carrier with Encoded Video Signal

•

Low Power Dissipation

Clock
Output
Oscillator
Input
Duty Cycle
Adj

•

Linear Chroma Modulators for High Versatility

•

Composite Video Signal Generation Capability

•

Ground-Referenced Video Prevents Overmodulation

VCC
Color B
Input

Chromlnance
Input

Color Ref

Luminance

Input

Input

Color A
Input

Chroma
Modulator
Output

FIGURE 1 - BLOCK DIAGRAM

RF
Color B

Luminance
Input

Input

VCC

Modulator
Output

11

Oscillator

Chrominance

Input

Input

Chrominance
Oscillator
and

.----t----H:J

Clock

Output

Driver
Clock
Output

Ground

Modulator

Color A
Input

Duty Cycle
Adjust

Color
Reference
Input

3-2

R F Tank

MC1372

MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)
Rating

Supply Voltage

Value

Unit

8.0

Vdc

o to

Operating Ambient Temperature Range
Storage Temperature Range

°c

+70

-65 to +150

°c

Junction Temperature

150

°c

Power Dissipation, Package

1.25

Watts
mW/oC

Derate above 25°C

13

RECOMMENDED OPERATING CONDITIONS
Supply Voltage

5.0

Vdc

Luma Input Voltage - Sync Tip

1.0

Vdc

Peak White

0.35

Color Reference Voltage
Color A, B Input Voltage Range

ELECTRICAL CHARACTERISTICS

1.5

Vdc

1.0 to 2.0

Vdc

II

(VCC = +5 Vdc, TA = 25 0 C, Test CirCUit 1 unless otherwise noted)

Characteristic
Operating Supply Voltage
Supply Current
CHROMA OSCILLATOR/CLOCK DRIVER (Measured at Pin 1 unless otherwise noted)
0.4

Vdc

Rise Time (Vl = 0.4 to 2.4 Vdc)

50

ns

Fall Time (Vl = 2.4 to 0.4 Vdc)

50

Output Voltage
2.4

70

Duty Cycle Adlustment Range (V3 = 5.0 Vdc)
(Measured at Vl

=

30

%

1.4 V)

Inherent Duty Cycle (No connection to Pin 3)

50

°'0

CHROMA MODULATOR IV5 = V6 = V7 = 1 5 Vdc unless otherwise noted)
Input Common Mode Voltage Range (Pins 5, 6,7)

2.3

Vdc

15

31

mV(p-p)

100

115

0.8

Oscillator Feedthrough (Measured at Pin 8)
S5

Modulation Angle (nS(V7 = 2.0 Vdc) - n8(V5 = 2.0 Vdc)]
ConverSion Gain (VS/(V7 - V6); VS/(V5 - V6)]

-20

Input Current (Pins 5, 6,7)
Input ReSistance (Pins 5, 6,7)

100

j.J.A
kU

Input Capacitance (Pins 5, 6,7)

5.0

Chroma MOdulator Linearity

degrees
V(p-p)/Vdc

0.6

4.0

pF
%

(V5=10t02.0V;V7=1.0t02.0V)
RF MODULATOR

o

Luma Input DynamiC Range (Pin 9, Test CirCUit 2)
R F Output Voltage (f = 67.25 MHz, V9 = 1.0 V)

1.5

Volts

15

mVrms

0.8

V/V

Luma Conversion Gain
(c,V12/c,V9; V9 = 0.1 to 1.0 Vdc) Test Circuit 2
Chroma Conversion Gain

V/V

(..'.V12ic,Vl0; Vl0 = 1.5 Vp-p; V9 = 1.0 Vdc) Test Circuit 2

0.95

Chroma Linearity (Pin 12, Vl0 = 1.5 Vp-p).Test Circuit 2

1.0

%

Luma Linearity (Pin 12, V9 = 0 to 1.5 Vdc) Test Circuit 2

2.0

%

-20

Input Current (Pin 9)
800

Input Resistance (Pin 10)
Input Resistance (Pin 9)

j.J.A

12
kl2

100

Input Capacitance (Pins 9,10)

5.0

pF

Residual 920 kHz IMeasured at Pin 12) See Note 1

50

dB

Output Current (Pin 12, V9 = 0 V) Test Circuit 2

1.0

mA

TEMPERATURE CHARACTERISTICS IV C

= 5 Vdc, T A = 0 to 70°C, IC only)

Chroma Oscillator Deviation Ifo = 3.579545 MHz)
RF Oscillator Deviation (fo = 67.25 MHz)
Clock Drive Duty Cycle Stability
NOTE 1. V9
Vs

= 1.0 Vdc, Vc = 300 mV(p-p) @ 3.58 MHz,
= 250 mV(p-p) @ 4.5 MHz, Source Impedance = 75 n.

3-3

MC1372

FIGURE 2 - TEST CIRCUIT 1

+5 V

+

10ILF

1

240

75
u.
:l.

~::rO

0

N

~

O.l/iH

-=

0

V12
RF Output

II

3.579545 MHz

11

14

13

12
Chroma Modulator
Output

9-35
pF

MC1372

5.6 k

Vo

10

Clock
Output

l,.--,--"""T"-.....--,--,Jr--o-!.0~.\1-,~3~0~0:1'>-() V C
:J;30PF

/iF

90

10k

V5

V6

V7

300

V9

~

Duty Cycle
Adiust

FIGURE 3 - TEST CIRCUIT 2

+5 V

+7 V

360

10 fJ.F

2 k

lN4001

14

12
Chroma Modulator
Output

56 k

9-35
pF

MC1372

Vo
10
OutPuto-~------~~~_-r_-r_'-_~_~

Clock

(--0 Vl0
0.1 IlF

V5

V6

V7

V9

s:

FIGURE 4 - SCHEMATIC DIAGRAM
Duty Cycle

Oscillator

Clock

Adjust

Input

Driver

Luma

11
VCC

(")

Chrominance

RF MOdulator

I nrlJt

Input

90

10

Output
12 (

...a

RF

Co\)

Tank

139 9

"

14

N

o-,-t-,-------,-----------~----------t_~~------~--~~--~~----~~~--~~------_.~----~~~~--~
R1

R3

R5

R13

R14

25 k

2.5 k

4.7 k

600

1.6 k

~I I

R19

R20
300

~ :~~

~R12
04
20 k
R8

~

R6
11 k

, 20 k

01

K

~05
R9

02

R2
25 k i D 1

R7
3.6 k

R10

R25

l!l

:>

R26:>

R27

a:

4

~--~--------------~~~~--------~--------~_4--~--~----~~-----'--------~----------~----~--~~-O Ground

w
cJ,

-4----------

YD2

R50

\

7f
C4

R51

"C3

;:r:M
R31

R28

R32

~t
C2

~44

...J....

C1

8 Chroma

l

~MOdulator

I

Output

030

1M

O~

R43
R37

'R44 ~ R48
13.4 k 3.4 k

032
M

C5

..L

o~t

'T'

Or
1:

036

2

R33

R34

R46

R35

R47

Rl'

56
Color 8
Input

Color Reference
Input

Color A
Input

III

MC1372

OPERATIONAL DESCRIPTION

Pin 11 - VCC
Positive supply voltage

Pin 1 - Clock Output
Pin 12 - R F Modulator Output

Provides a rectangular pulse output waveform with

Common collector of output modulator stage. Output

frequency equal to the chrominance subcarrier oscillator.

impedance and stage gain may be selected by choice of

This output is capable of driving one LS-TT L load.

resistor connected between this pin and dc supply.

Pin 2 - Oscillator Input

Pins 13 and 14 - RF Tank

Color subcarrier oscillator feedback input. Signal from

A tuned circuit connected between these pins determines the R F oscillator frequency. The tuned circuit must

the clock output is externally phase shifted and ac coupled to this pin.

provide a low dc resistance shunt. Applying a dc offset

Pin 3 - Duty Cycle Adjust

voltage between these pins results in baseband composite

A dc voltage applied to this pin adjusts the duty cycle

video at the R F Modulator Output.

of the clock output signal. If the pin is left unconnected,
the duty cycle is approx imately 50%.

I

MC1372 CIRCUIT DESCRIPTION
Pin 4 - Ground
The chrominance oscillator and clock driver consist of
emitter follower Q4 and inverting amplifier Q5. Signal

Pin 5 - Color B Input
Dc coupled input to Chroma Modulator B, whose
phase leads modulator A by approximately 100° The

presented at clock driver output pin

1 is coupled to

osci:lator input pin 2 through an external RC and crystal

modulator output amplitude and polarity correspond to

network, which provides 180 0 phase shift at the resonant

the voltage difference between this pin and the Color
Reference Voltage at Pin 6.

frequency. The duty cycle of the output waveform is
determined by the dc component at pin 1 internally

Pin 6 - Color Reference Input

coupled through R 12 to the base of Q4. As pin 1 dc

The

dc voltage applied to this pin establishes the

voltage

reference voltage to which Color A and Color B inputs
are compared.

longer percentage of the cycle. Transistors QO, Q1,
Q2 and diode 01 provide the biasing network which
determines the dc operating level of the oscillator. The

Dc coupled input to Chroma Modulator A, whose
100° The

modulator output amplitude and polarity correspond to
the voltage difference between this pin and the Color
Reference Voltage at Pin 6.

transistor Q2 and resistors R5, R6, and R7 form a voltage
reference of four times VBE at the collector of Q2. The
dc voltage at pin 1 is determined by the values of R4,
R8, and R12 and the applied duty cycle adjust voltage

Pin 8 - Chroma Modulator Output
Low
provides

impedance
the

(emitter

vectorial

sum

a smaller portion of the sinusoidal

two times VBE required for conduction. As the dc level
is reduced, device Q4 and thus Q5 is turned on for a

Pin 7 - Color A Input
phase lags modulator B by approximately

increases,

feedback signal at pin 2 exceeds the Q4 base voltage of

which

at pin 3. Since these resistors are nominally equal, the

of chroma modulators A

voltage at pin 1 will always approximate the dc voltage

follower)

output

at pin 3.

and B.

The oscillator signal at pin 1 is internally coupled to

Pin 9 - Luminance Input

active filter Q44. This filter reduces the frequency content

Input to RF modulator. This pin accepts a dc coupled

above 4 M Hz. The output of the filter at the emitter of

luminance and sync signal. The amplitude of the RF signal
output increases with positive voltage applied to the pin,

Q44 is ac coupled th rough C3 to the input of the lead/lag
network. R32 and Cl provide approximately 50 0 of phase

and ground potential results in zero output (i.e., 100%

lag, while C2 and R29 provide approximately 50 0 of

modulation). A signal with positive-going sync should
be used.

phase lead. These two quasi-quadrature waveforms are
used to switch chroma modulators B and A. respectively.
The transistors Q22 through Q25 and Q32-Q33 form

Pin 10 - Chrominance Input

a doubly balanced modulator. The input signal applied
at pin 5 is compared to the color dc reference voltage

Input to the R F modulator. This pin accepts ac coupled
chrominance provided by the Chroma Modulator Output
(pin 8). The signal is reduced by an internal resistor divider

applied at pin 6 in differential amplifier Q32-Q33. The
source current provided by transistor 034 is partitioned

before being applied to the RF modulator. The resistor
divider consists of a 300 ohm series resistor and a 500

in transistors 032 and Q33 according to the differential

ohm shunt resistor. Additional gain reduction may be
obtained by the addition of external series resistance

input signal. The bases of transistors 023 and Q24 are
connected to the dc reference voltage at the emitter of

to pin 10.

030. The bases of transistors Q22 and 025 are connected

3-6

MC1372

associated equipment. The duty cycle may be adjusted
by varying the dc voltage applied to pin 3. This adjustment may be made with the use of a potentiometer
(10 kst) between supply and ground. With no connection
to pin 3, the duty cycle is approximately 50%.

to the phase delayed oscillator signal at the emitter of
buffer transistor 021. The differential signal currents
provided by 032 and 033 are switched in transistors
022 through 025 and the resultant signal voltage is
developed across R49. This signal has the phase and
frequency of the oscillator signal at the emitter of 021.
The amplitude is proportional to the differential input
signal applied between pins 5 and 6. Transistors 026
through 029 and 038-039 form chroma modulator B.
This modulator develops a signal voltage which is propor·
tional to the differential vqltage appl ied between pins
7 and 6. The phase and frequency of the output is equal
to the phase advanced chroma oscillator at the emitter
of buffer transistor 020. Both chroma modulators A and
B share the same output resistor, R49, so the output
signal presented at the emitter of 042 (pin 8) is the
algebraic sum of modulators A and B.

Chroma Modulator
The chrominance oscillator is internally phase shifted
and appl ied to chroma modulators A and B. No external
lead/lag networks are necessary. The phase relationship
between the modulators is approximately 100 0 , which
was chosen to provide the best rendition of colors using
equal amplitude color-difference signals. The voltage
applied to pin 5, 6, or 7 must always be within the Input
Common Mode Voltage Range. Since the amplitude of
chrominance output is proportional to the voltage difference between pins 5 and 6 or 7 and 6, it is desirable
to select the Color Reference Voltage applied to pin 6 to
be midway between V5 max and V5 m in (which should

The R F osci lIator consists of differential ampl ifier
018 and 019 cross-coupled through emitter followers
016 and 017. The oscillator 'will operate at the parallel
resonant frequency of the network connected between
pins 13 and 14. The oscillator output is used to switch
the doubly balanced RF modulator, 09 through 015.
Transistors 07 and 08 provide level shifting and a high
input impedance to the luminance input pin 9. The
bases of transistors 09 and 010 are both biased through
resistors R 17 and R 18, respectively, to the same dc
reference voltage at 06 emitter. The base voltage at 010
may only be offset in a negative direction by luminance
signal current source 08. This design insures that overmodulation due to the luminance signal will never occur.
The chrominance signal developed at pin 8 is externally
ac coupled to pin 10 where it is reduced by resistor
dividers R 20 and R 17, and added to the lum inance
signal in 09. The resultant differential composite video
currents are switched at the appropriate R F frequency
in 012 through 015. The output signal current is presented
at pin 12.
Transistors 036, 041 and resistors R44, R47 provide
a highly stable voltage reference for biasing current sources
043,034,035, and 011.

be V7 max and V7 m in)' The Chroma B Modulator will be
defined as a (B-Y) modulatol' if a burst flag signal is
applied to the Color B Input (pin 5) at the appropriate
time. This voltage should be negative with respect to the
Color Reference Voltage, and typically has an amplitude
equal to 1/2[V6-V5 m in J. Since the phase of burst is
always defined as -(B·Y), the Chroma A Modulator
approximates an (R-Y) modulator; however, the phase
is offset by 10 0 from the nominal 90 0 , to provide the
100 0 phase shift as discussed previously.
R F Modulator and Oscillator
The coil and capacitor connected between pins 13 and
14 should be selected to have a parallel resonance at the
carrier frequency of the desired TV channel. The values
of 56 pF and 0.1 pH shown in Figure 5 were chosen
for a Channel 4 carrier frequency of 67.25 MHz. For
Channel 3 operation, the resonant frequency should
be 61.25 MHz (C = 75 pF, L = 0.1 pH). Resistors R4 and
R5 are chosen to provide an adequate amplitude of
switching Voltage, whereas R6 is used to lower the maximum dc level of switching voltage below VCC, thus
preventing saturation within the IC.
Composite Luminance and Sync should be dc coupled
to Luminance Input, pin 9. This signal must be within
the Luma I nput Dynamic Range to insure linearity.
Since an increase in dc voltage applied to pin 9 results
in an increase in R F output, the input signal should
have positive-going sync to generate an NTSC compatible
signal. As long as the input signal is positive, overmodulation is prevented by the integrated circuit.
Chrominance information should be ac coupled to
Chrominance Input, pin 10. This pin is internally connected to a resistor divider consisting of a series 300
ohms and a shunt 500 ohms resistor. The input impedance
is thus 800 ohms, and a coupling capacitor should be
appropriately chosen.

MC1372 APPLICATION INFORMATION
Chrominance Oscillator
The oscillator is used as a clock signal for driving
associated external circuitry, in addition to providing a
switching signal for the chroma modulators. The IC uses
an external crystal in a Colpitts configuration, as shown
in Figure 5. Resistor Rl provides current limiting to
reduce the signal swing. Capacitor C2 is adjusted for
the exact frequency desired (3.579545 MHz).
In some applications, the duty cycle of the clock signal
at pin 1 must be modified to overcome gate delays in

3-7

I

MC1372

FIGURE 5 - TYPICAL APPLICATION CIRCUIT

.5 Vdc
C5

'T'

a 001.-1.....

RF
Output

I
R5
240

R2
750

The Luminance to Chrominance ratio (L:C) may be
modified with the addition of an external resistor in series
with pin 10 (as shown in Figure 5). The unmodified L:C

tage at pi n 12 is high enough to prevent the output
devices from reaching saturation (approximately 4.5 V
with components in Figure 5). The peak current out of
pin 12 is typically 2 mAo Hence, a load resistance of up

(Ao) is determined by the ratio of the respective Conversion Gain for equal amplitude signals (typically, 0.883 =
-1.6 dB). The modified L:C will be governed by the
equation Ao(l + Rext /800) for equal amplitude input
signals.

to 250 ohms may be safely used with a 5 \. supply.
Composite Video Signal Generation
The RF modulator may be easily used as a composite
video generator by replacing the RF oscillator tank
circuit with a diode as shown in Figure 3. This results in

The internal chrominance modulators are not internally connected to the RF modulator; therefore, the user
has the option of connecting an externally generated
chrominance signal to the RF modulator. In addition,
the RF modulator is wideband, and a 4.5 MHz FM audio
signal may be added to the chrominance input at pin 10.
This may be accomplished by selecting an appropriate series
input resistor to provide the correct Luminance:Sound
ratio.

the output modulator being biased so the summation of
luminance and chrominance appears unswitched at
pin 12. The polarity of the output waveform is controlled by the direction of the diode. Inverted video:
Anode to pin 14, cathode to pin 13. Non-inverted
video: Anode to pin 13, cathode to pin 14. Note that the
supply resistor must always be connected to the anode
of the diode.
The amplitude of signal may be increased by increasing
the load resistor on pin 12 and returning it to a higher
supply voltage. Any voltage up to the Absolute Maximum

The modulated R F signal is presented as a current
at RF Modulator Output, pin 12. Since this pin represents
a current source, any load impedance may be selected for
matching purposes and gain selection, as long as the vol·

Rating may be used.

3-8

MC1372

RECOMMENDED CHROMA·LUMA SIGNALS

Applications with MC6847 Video Display Generator
The MC1372 may be easily interfaced to the MC6847
as shown in Figure 5. The dc levels generated and required
by the VDG are compatible with the MC1372, so that
pins 1, 5, 6, 7, and 9 may be directly coupled to the
appropriate MC6847 pins. Both integrated circuits as
well as any associated NMOS MPU may be driven from
a common 5 Vdc supply.

3-9

Pin ;.7

Pin #6

Pin #5

ColorA
(Vdc)

Color Ref.
(Vdc)

Color B
(Vdc)

1.0

1.5

1.5

1.5

Blanking

0.75

1.5

1.5

1.5
1.25

Sync

Recommended Chroma·Luma Signals
A chroma modulation angle of 1000 was chosen to
facilitate a desirable selection of colors with a minimum
number of input signal levels. The following table demonstrates applicable signal levels for a variety of colors.

Pin ;09
Luminance
Input
(Vdc)

Burst

0.75

1.5

1.5

Black

0.70

1.5

1.5

1.5

Green

0.50

1.0

1.5

1.0

Yellow

0.38

1.5

1.5

1.0

Blue

0.62

1.5

1.5

Red

0.62

2.0

2.0
1.5

Cyan

0.50

1.0

1.5
1.5

Magenta

0.50

2.0

1.5

Orange

0.50

2.0

1.5

1.0

Buff

0.38

1.5

1.5

1.5

1.5
2.0

I

®

MC2670

MOTOROLA

Advance Information
HMOS
(HIGH DENSITY N-CHANNEL, SILICON-GATE
DEPLETION LOAD)

DISPLAY CHARACTER AND
GRAPHICS GENERATOR (DCGG)
DISPLAY CHARACTER AND GRAPHICS GENERATOR
(DCGG)

I

The MC2670 display character and graphics generator (DCGG) is a
mask-programmable 11 ,648-bit line-select character generator. It contains 128 10 x 9 characters placed in a 10 x 16 matrix, and has the
capability of shifting certain characters such as L y, g, p, and q that normally extend below the baseline. Character shifting, previously requiring additional external circuitry, is now accomplished internally by the
DCGG; effectively, the nine'active lines are lowered within the matrix to
compensate for the character's position.
Seven bits of an 8-bit address code are used to select one of 128 available characters. The eighth bit functions as a chip-enable signal. Each
character is defined by a pattern of logic ones and zeros stored in a
10 x 9 matrix. When a specific 4-bit binary line address code is applied, a
word of 10 parallel bits appears at the output. The lines can be sequentially selected, providing a 9-word sequence of 10 parallel bits per word
for each character selected by the address inputs. As the line address
inputs are sequentially addressed, the device will automatically place
the 10 x 9 character in one of two pre-programmed positions on the
16-line matrix with the positions defined by the 4-line address inputs.
One or more of the 10 parallel outputs can be used as control signals to
selectively enable functions such as half-dot shift, color selection, etc.
The MC2670 includes latches to store the character address and line
address data. A control input to inhibit character data output for certain
groups of characters is also provided. The MC2670 also includes a
graphics capability, wherein the 8-bit character code is translated directly into 256 possible user-programmable graphic patterns. Thus, data
can be generated for 384 distinct patterns, of which 128 are defined by
the mask-programmable ROM. Features include:
LAO

• 128 lOx 9 Matrix Characters
• 256 Graphic Characters
• Optional Thin Graphics for Forms

VCC
27

LSTROBE

• Internal Descent Logic
• 200 Nanosecond and 300 Nanosecond Character Select Access Time
Versions

CAl

25

LA3

CA2

24

DO

CA3

23

[11
D2

CSTROBE

• Control Character Output Inhibit Logic
No Clocks Required

L.Al
LA2

CAD

• Character and Line Address Latches

• Static Operation -

PIN ASSIGNMENT

CA4

21

D3

• Single 5-Volt Power Supply

CA5

D4

• TTL Compatible Inputs and Outputs

CA6

D5

CA7

D6

GM

This document contains information on a new product. Specifications and information herein
are subject to change without notice

3·10

07

SCD

13

DB

VSS

14

D9

MC2670

BLOCK DIAGRAM

sco----------------------------------,
G M --------------------...,

~vcc

...---GNO

CAO-CA 7 '--__________-,

CSTROBE

00-09

LAO-LA3

LSTROBE--------~

POWER CONSIDERATIONS
The average chip-juncton temperature, T j, in °c can be obtained from:
(1)
Tj = TA + (PD-OjA)
Where:
TA""Ambient Temperature, °c
OJA "" Package Thermal Resistance, Junction-to-Ambient, °C/W
PD""PINT+ PPORT
PINT""ICCxVCc, Watts - Chip Internal Power
PPORT"" Port Power Dissipation, Watts - User Determined
For most applications PPORT 0 PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and TJ (if PPORT is neglected) is:
PD= K + (T J + 273°C)
(2)
Solving equations 1 and 2 for K gives:
K= PD-(TA +273°C) +OJNPD 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 bV measuring PD (at equilibrium)
for a known T A Using this value of K the values of PD and TJ can be obtained by salving equations (1) and (2) iteratively for any
value of T A.

3-11

I

MC2670

MAXIMUM RATINGS
Parameter

Symbol

Value

Supply Voltage

VCC

-0.3 to 7.0

V

Input Voltage with Respect to Ground

Yin

-0.3t07.0

V

TA

o to 70

°c

Tstg

- 55 to + 150

°c

Operating Temperature Range
Storage Temperature Range

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any
voltage higher than maximum-rated
voltages to the high-impedance circuit.

Unit

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

I

Symbol

Value

Unit

IIJA

115
60
65

°C/W

DC ELECTRICAL CHARACTERISTICS ITA = O°C to 70°C V CC = 50 V +
- 5% See Notes 1 2 and 3)
Symbol

Min

Typ

Max

Input Low Voltage

Parameter

VIL

-0.3

-

0.8

V

Input High Voltage

VIH

2.0

-

VCC

V

VOL

-

0.3

0.4

V

VOH

2A

3

-

V

Output Low Voltage
ILoad = 1.6 mA
Output High Voltage
ILoad= -100 p.A
Input Leakage Current
Vin=Ot04.25V

IlL

Hi-Z 10ff-State) Leakage Current
VCC=5.25 V, Vin=OA to 2A V

ITSL

Internal Power Dissipation
VCC=5.25 V, TA=O°C Minimum
Input Capacitance IAII Other Pins Grounded)
Output Capacitance

-

-10

PINT

-

Cin

-

Cout

-

Unit

-

10

p.A

-

10

p.A

200

420

mW

10

pF

15

pF

-

NOTES:
1. Parameters are valid over operi'ting temperature range unless otherwise specified.
2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and outputs Input
levels are 0 V to 2A V.
3. Typical values are at + 25°C, typical supply voltages, and typical processing parameters.

AC ELECTRICAL CHARACTERISTICS ITA = O°C to 70°C, V CC = 5 V +
- 5%, See Notes 1, 2, 3, and 4)
MC2670*3
Symbol

Min

Strobe Pulse Width

tws

100

Line Address Setup Time

tLAS

Line Address Hold Time

Max

Unit

-

100

-

ns

50

-

50

-

ns

tLAH

25

-

25

-

ns

Character Address Setup Time

tCAS

25

-

15

-

ns

Character Address Hold Time

tCAH

25

-

15

-

ns

Character Select Access Time

tCA

-

300

'-

200

ns

Line Select Access Time

tLA

-

500

-

350

ns

Chip Select Delay Time

tSEL

-

250

-

150

ns

Chip Deselect Delay Time

tDES

-

200

-

125

ns

tsc

-

300

-

200

ns

Special Character Blank/Unblank Time

Max

MC2670*2
Min

Parameter

* Substitute letter corresponding to standard font for 1*) In part number for standard parts. Refer to ORDERING INFORMAnON for additional
information.
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2 All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and outputs. Input
levels are 0 V and 2A V.
3. Typical values are at + 25°C, typical supply voltages, and typical processing parameters
4. Test conditions: CL = 100 pF and 1 TTL load.

3-12

MC2670

TIMING DIAGRAMS

LSTROBE

LAO-LA3

00-09

SCO*

~

~--

CA5, CA6

00-09

* When GM = 1 SCO input is inactive

CSTROBE

tCAH
CAO-CA7, GM

00-09

~~~~~~~~_tC_A_-_-_-_-_-~---lX=~

_______

CSTROBE

CA7*

00-09

*CA7 operates as output enable only in character mode IGM=O)

3-13

I

MC2670

SIGNAL DESCRIPTION

character latch outputs are presented to the three sources of
data; the ROM through an address decoder, the graphics
logic, and the output inhibit control. The output inhibit control (together with the SCD input) suppresses the ROM data
for selected character codes. The outputs from the line latch
drive the line address translation ROM which maps the
character ROM data onto 9 of 16 line positions. Finally, the
line select multiplexers route the ROM or graphics data to
the output drivers on DO through D9.

The input and output signals for the DCGG are described
in the following paragraphs.
VCC AND VSS
Power is supplied to the DCGG using these two pins. VCC
is the + 5-volt power supply and VSS is the ground connection

I

CHARACTER LATCH
The character latch is a 9-bit edge-triggered latch used to
store the character address (CAO through CA7) and graphics
mode (GM) inputs. The data is stored on the falling edge of
CSTROBE. Seven latched addresses (CAO through CA6) are
inputs to the ROM character address decoder. In character
mode (GM = 0), CAl operates as a chip enable. The output
drivers are enabled when CA7 = 1 and are in the highimpedance state when CAl = O. In graphics mode (GM = 1),
the output drivers are always enabled and the CAO through
CA7 outputs of the latch are used to generate graphic
symbols.

CHARACTER ADDRESS (CAO-CA7)
This 8-bit input code specifies the character or graphic
pattern for which matrix data is to be supplied. In character
mode (GM=Q), CAO through CA6 select one of the 128
ROM-defined characters and CA7 is a chip enable. The outputs are active when CAl = 1 and are in the high-impedance
state when CAl = O. In graphics mode (GM = 1), the outputs
are active and CAO through CA7 select one of 256 possible
graphic patterns to be output.
CHARACTER STROBE (CSTROBE)
This input pin is used to store the character address (CAO
through CAl) and graphics mode (GM) inputs into the
character latch. Data is latched on the negative going edge
of CSTROBE.
GRAPHICS MODE (GM)

CHARACTER ADDRESS DECODER
This circuit decodes the l-bit character address from the
character latch to select one of the 128 character fonts
stored in the ROM section of the DCGG.

This input pin when low (G M = 0) selects the character
mode and when high (GM = 1) selects graphics mode.

READ-ONLY MEMORY
The 11 ,648-bit ROM stores the fonts for the 128 matrixdefined characters. The data for each character consists of
91 bits. Ninety bits represent the 10 x 9 matrix and one bit
specifies whether the character data is output at the normal
(unshifted) lines or at the descended (shifted) lines. The 90
data bit outputs are supplied to the line select multiplexers.
The descend control bit is an input to the line address
translation ROM.

LINE ADDRESS (LAO-LA3)
When operating in the character mode, these input pins
select one of the 16 lines of matrix data for the selected
character to appear at the 10 outputs. LAO is the least-significant bit and LA3 is the most-significant bit. The input codes
which cause each of the nine lines of character data to be
output are specified as part of the programming data for
both non-shifted and shifted fonts. Cycling through the nine
specified counts at the LAO through LA3 inputs causes successive lines of data to be output on DO through D9. The
seven non-specified codes for both non-shifted and shifted
characters cause blanks (logic zeros) to be output. In
graphics mode, the line address gates the latched graphics
data directly to the outputs.

GRAPHICS LOGIC
When the GM input is zero (low), the DCGG operates in
the character mode. When it is one (high), it operates in the
graphics mode. In graphics mode, output data is generated
by the graphics logic instead of the ROM. The graphics logic
maps the latched character address (CAO through CA7) to
the outputs (00 through 09) as a function of line address
(LAO through LA3). For any particular line address value,
two of the CA bits are output: CAO, CA2, CA4, or CA6 is
output on DO through 04 and CA 1, CA3, CA5, or CAl is output on 05 through 09. The outputs are paired: when CAO is
output on DO through 04, CA 1 is output on 05 through 09
and likewise for CA2-CA3, CA4-CA5, and CA6-CA7.
A ROM within the graphics logic allows the specific line
numbers for which each pair of bits is output to be specified
by the customer. Figure 1 illustrates the general format for
graphics symbols and an example where (CA7 through
CAO) = H'65'. The outputs from the graphics logic go to the
line select multiplexers. The multiplexers route the graphic
symbol data to the outputs when GM = 1.
As a customer specified option, 16 of the possible graphic
codes (H'80' to H'8F') may be used to generate the special
graphic characters illustrated in Figure 2. For each of these
characters, the vertical component appears on the 04 output. The horizontal components occur on LH which is
specified by the customer. The vertical components
specified by CAO and CA2 are output for line addresses zero
through LH and LH through 15, respectively.

LINE STROBE (LSTROBE)
This input pin is used to store the line address data (LAO
through LA3) in the line address latch. Data is latched on the
negative going edge of LSTROBE.
SELECTED CHARACTER DISABLE (SCD)
In character mode, a high level at this input causes all outputs (regardless of line address) to be blanks (zeros) for
characters for which CA6 and CA5 are both zero. A low level
input selects normal operation. SCD is inoperative in the
graphics mode.
DATA OUTPUTS (DO-D9)
These outputs provide data for the specified character and
line.

FUNCTIONAL DESCRIPTION
The DCGG consists of nine major sections which are
described in the following paragraphs. Line and character
codes are strobed into the line and character latches. The

3-14

MC2670

FIGURE 1 -

GENERAL FORMAT GRAPHIC SYMBOLS

Line Address

Line

LF=O1-

CAO

CAl

234-

CA2

CA3

CA4

CA5

5678-

910 -

CA6

CA7

LL = 11-

)
)
)
)

0-

Group 1

1-

Group 2

23456-

Group3

Group4

78-

9lOll-

I

k-00-04~0509--.j
o

Group line addresses are specified by the customer

FIGURE 2 -

":?2 042 082

002

OE2

082 OC~ OB8
082

08 N 022 022 022 nl'+ 008 orB 020

020 020

48 N 082 042 022

oc N 01[

010

'C N 002 002 002 n02 002 002 J02 002 07E

002

ODE n02

QF2 010 070

010

012

00 N Ole 002 002 002 07C 090 L70 050 090

40 N 082

OC6 OAA n92 092

082 082 082 082

DE N Ole

082 086 08A

OA2

002 DOC

nl0

06E

090

090

090

060

4E N 082

OF N Ole 002 DOC

010

OEE

0'+0

0'+0

040

0[0

4F N 038

0'+'+ 082 082 082

ODE 010

010

010

oro

50 N 07E

082 082 082 07E 002 002 002 (J02

11 NODE 012 012 012

OItE 060 040 040

oro

51 N 03~

044 082 082 082 092 1)A2 044

12 NODE

012 012

!'l12

ObE

1)40 020

Oro

52 N 07E

082 082 082

13 NODE

012 012

n12

06E

QBO

060

oeo

070

53 N 078

084

14 NODE

012 012

n12

04E

060

050

OFS

040

54 N OF[

010 010 010

10 NODE

012 012 n12

15 N 012 016 01A

n12

092

090

050

002 004

092

07E

oe2 082

082 OA2 0'+'+

012

u2.2

082
038

088

LJ,+2 DB.?

036 040

!JAO

O~2

03C

010

LID

c10

ClO

010

082 082 oB2 082 082

030

050

090

55 N 082

16 N Ole

U02

Doe

[)10

USE

050

U2()

U20

020

56 N 082

OB2 OB2 n44

044

17 N DIE

002 ODE

n02

07E

090

C70

(lqO

070

57 N

08~

082 OB2 n82

082 092

{I

0132 044

03~

028 U?8

Olu

lila

')g~

OAI\

1)'+4

18 N Ole

002

002

n 02

Ole

090

CP (l

[I[~

19 N DIE

002

ODE

n02

OlE

OSr.

(JDB

OA!j LJ!j!j

59 N 082 082 0" n28 010 010 010 010 010

lA N OlC 002 DOC nlO

on

090 010 090 070

5A N OFE 080 0.0 n20 010 008 00. 002 OFE

1I

ap

58 N 082 082 044 n28 010 028 u'+l+

082 082

18 N OlE 002 ODE 002 OlE OED 010 010 OED

56 N 01C

lC N OlE 002 ODE n02 OE2 010 0'0 080 070

5C N 000 002 00. nOB 010 020 0.0 080 000

10 N Ole

50 N 01C

002 alA

012

OEe

DIU

LJ~O

OeD 070

001+ 001+ n04 00'+ 004 001+ 001+ 07e

040 040 n40

040 040

040 040

07C

lE NODE 012 ODE oOA OF2 010 060 080 070

5E NOlO 038 05. nlO 010 010 010 010 010

IF N 012 012 012 n12

DEC 010 060 080 070

5F N 000 000 008 nO. OFE 00. 008 000 000

20 N 000 000 000 nOD 000 000 000 000 000

60 N 018 018 010 020 000 000 000 000 000

21 NOlO 010 010 nlO 010 000 uOO 010 010

61 N 000 000 000 n3C 0.0 07C 0'2 0.2 ORC

22 N 028 028 028 n28 UOO 000 000 000 000

62 N 002 002 002 n3A 0'6 0_2 0'2 0.6 03A
63 N 000 000 000 03C C.2 002 002 0.2 03C

23 N 028 028 OFE n28 028 U2a UFE 028 028
2. N 028 OFC 02A n2A 07C OA8 OA8 07E 028

64 N 040

OltO 040 o5C

0(.2 042

U42 062 05(

020

010

OOB

044

OA2 0'+0

65 N 000 000 000 n3C 0'2 07E 002 002 03C

012 noe

DOC

012 OA2

042 ORe

66 N 030 0'8 008 n08 03E 008 008 008 008

01B DaB 00,+ 000 000 000 000 000

67 5 000 05C 062 n.2 062 OSC 0"0 0.2 03C

28 N 020 010 008 n08 008 008 CCO 010 020

68 N 002 002 002 n3A 0.6 0'2 0'2 0.2 0.2

25 N 004

08A 044

26 NoDe

012

27 N 018

69 N 000 010 000 n18 010 010 OlD 010 038

29 N 008 010 020 n20 020 020 020 010 008
2A N 000 010 05. n38 OF£ 038 05' 010 000

6A 5 000 060 0'0 n'O 0'0 0'0 0'0 0" 038

28 N 000 010 010 nlO OFE 010 010 010 000

68 N 002 002 002 n22 012 OOA 016 022 0.2

01B OlB OOB 00'+

6C N 018 010 010 010 010 010 010 010 038

2e soDa

000

000 000 000

60 N 000 000 000 n6A 096 092 092 092 092

20 N 000 000 000 nOD OFE 000 000 000 000
2[ NOaa

000 000 nOD

000

6[ N 000 000 000

000 000 01B (118

n3A 046 042 0'+2 042 042

6F N 000 000 000 03c 0'2 0'2 0'2 0.2 03C

2F N 000 080 0.0 n20 010 008 UO' 002 000
038

70 5 000 03A 0'6 0'2 0'6 03A 002 002 002

31 NOlO 018 01. nlO 010 010 010 010 07C

11 ·5 000 05C 062 n.2 062 05C 0'0 0.0 0'0

32 N 07c 082 080 0.0 038 00. 002 002 OFE

72 N 000 000 000 03A 0'6 002 002 002 002

30 N 038 044 OC2 oA2

092 08A 086 044

33 N 07C 082 080 n80 070 080 080 082 07C

73 N 000 000 000 03C 0'2 DOC 030 0.2 03C

34 N altO

H

060

050 04B Olt4

35 N OFE 002 002 002

on

OFE

040 0'+0 040

080 OBO 082 07C

36 N 078 08' 002 n02 07A 086 082 082

N 000 008 008 nlC 008 008 008 0.8 030

75 N 000 000 000 n'2 0'2 0.2 0'2 062 05C

on

76 N 000 000 000

n44 01+1+ 01+4 041+ 028 010

37 N OF( 080 080 n.O 020 010 008 DO' 002

71 N 000 000 000 082 062 092 092 092 06C

38 N 07C 082 082 n . . 038 0" 082 082 07C

7B N 000 000 000 n.2 02' 018 018 02' 0'2

39 N 07C 082 082 nC2 08C 080 080 0.2 03C

79 5 000 0.2 0'2 0.2 062 OSC 0'0 0.2 03C

on

3A N 000 000 000 n18 018 000 000 OlB 018

7A N 000 000 000 n7E 020 010 008 00.

38 5 000 01B 018 nOD 000 018 018 008 00.

78 N 030 008 008 n08 00. 008 008 ooa 030

3C N 020 010 008 nO. 002 00. 008 010 020

7C NOlO 010 010 000 ·000 DOG 010 010 010

3D N 000 000 000 nFE 000 000 O'E 000 000

70 N 018 020 020

n20 O'+G 020

020 02G

018

3E N OOB 010 020 n.O 080 0.0 020 010 008

7E N 000 000 000 noc 092 060 000 000 000

3F N 07C 082 082 n80 060 010 010 000 010

7F NOAA 051+ OAA 054 OAA 054

3-19

OAA 054 OAA

I

MC2670

FIGURE 5 -

10x 16 MATRIX FONT DRAWING (Sheet 1 of 4)

I

3-20

MC2670

FIGURE 5 - 10 x 16 MATRIX FONT DRAWING (Sheet 2 of 4)

I

3-21

MC2670

FIGURE 5 - 10 x 16 MATRIX FONT DRAWING (Sheet 3 of 4)

I

MC2670

FIGURE 5 - 10x 16 MATRIX FONT DRAWING (Sheet 4 of 4)

I

3·23

®

MC2671

MOTOROLA

Advance Information
HMOS
PROGRAMMABLE KEYBOARD AND
COMMUNICATIONS CONTROLLER (PKCCI

I

The MC2671 programmable keyboard and communications controller iPKCC) is an MOS/LSI device which provides a versatile
keyboard encoder and an independent full-duplex asynchronous communications controller. It is intended for use in microprocessor-based
systems and provides an 8-bit data bus interface.
Applications for the MC2671 include: CRT terminals, hard-copy
terminals, word-processing systems, data-entry terminals, and small
business computers.
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Keyboard Interface
Contact or Capacitive Keyboard
Up to 128 Keys on an 8 x 16 Matrix
Encoded or Unencoded Operation
Four Code Levels Per Key
Latched Key Option - Separate Depress and Release Codes
Programmable Scan Rate and Debounce Time
Programmable Rollover Modes
Programmable Auto-Repeat for Selected Keys
Tone Output - Two Frequencies
Asynchronous Communication Interface
Internal Baud-Rate Generator - 16 Rates
Full-Duplex Operation
Detection of Start and End of Break
Programmable Break Generation
Programmable Character Parameters
Auto-Echo and Maintenance Loopback Modes
Polled or Interrupt Operation
Interrupt Priority Controller and Vector Generator
Opel'a!es Directly from Crystal or External Clocks
TTL Compatible
Single + 5 Volt Power Supply

ORDERING INFORMAnON
Package .Type
Ceramic
L Suffix
Cerdip
S Suffix
Plastic
P Suffix

Frequency
1.0 MHz
1.0 MHz
1.0 MHz

Temperature
ooC to 70°C
ooC to 70°C
ooC to 70°C

Order Number
MC2671AL
MC2671AS
MC2671AP

(HIGH-DENSITY
N-CHANNEL, SILCON-GATE)

PROGRAMMABLE KEYBOARD
AND COMMUNICATIONS
CONTROLLER

L SUFFIX
CERAMIC PACKAGE
CASE 715

~
~:T':-.Ui:~AG'
.!

. !'

, '

3·24

.'

I!'.

S SUFFIX

CERDIP PACKAGE
CASE 734

CASE 711

PIN ASSIGNMENT
HYS

VCC

KORES

RxD

KCLK

TxO

KC3

XT AL2/BRCLK

KC2

XTAL1

KC1

Rxe

KeO

TxC

KR2

A2

KR1

A1

KRO

AO

REPEAT

CE

SHIFT

R

CONTROL

IN

TONE

INTA

KRET

07

DO

06

01

05

02

04

03

INTR

VSS

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

I

XINTR

MC2671

BLOCK DIAGRAM

IL

L

00-07 (

Bus Buffer

Data

(

Keyboard Encoder

REPEAT
KClK

t

Mode & Timing
Control

I

1

Operation Control

Vi

~

CMR

R

KMR

CE

L

~

L

I

Command Decoder

I

....-

A

Interrupt Control
and
Vector Generator

L----=l

XTA l2

Key Holding
Register

t

I

Tone Generator

I

Baud-Rate
Generator

~

Baud-Rate
Control
Register

TONE

-.~

~I--

...-.XTAl1/BRC lK

I

I

-.

Timing

Rx C

} KRO-KR2

Keyboard Data
Register

VC C GN D -

Tx C

4 x 128 x8
Read-Only
Memory

I
I
I
I

~

G

R

KRET

r--------i

I
R

} KCO-KC3

Keyboard
Scanner and
Encoder/
Decoder

CSR
KSR

AO-A2

KDRES
HVS

Transmitter

"T

Transmit
Holding Register
Transmit
Shift Register

Tx o

1
Receiver

Int;;;;:u~ts
Timing
Controls
I

3·25

Receive Holding
Register
Receive
Shift Register

RxD

MC2671

MAXIMUM RATINGS
Characteristics
Supply Voltage

Symbol

Rating

VCC

-0.3to +7.0

Input Voltage

Vin

-0.3 to -+ 7.0

Operating Temperature Range

TA
Tstg

- 55 to + 150

Symbol

Rating

Storage Temperature

o to

Unit
V
V

70

°C
°C

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage hiRher than maximum-rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Plastic
Cerdip
Ceramic

Unit
°C/W

()JA
100
60
50

I

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °c can be obtained from:
T J =TA + (PO-iJJA)
Where:
T A == Ambient Temperature, °C
iJJA == Package Thermal Resistance, Junction-to-Ambient, °C/W

(1)

Po == PINT + PPORT
PINT == ICC x VCC, Watts-Chip Internal Power
PPORT =: Port Power Oissipation, Watts- User Oetermined
For most applications PPORT~PINT and can be neglected. PPORT may become significant if the device is configured
to drive Oarlington bases or sink LEO loads.
An approximate relationship between Po and T J (if PPORT is neglected) is:
PO=K+(TJ+273 0 C)
(2)
Solving equations 1 and 2 fOT K gives:
K = PO-(T A + 273°C) +iJJA _P02
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at
equilibrium) for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1)
and (2) iteratively for any value of T A.

DC ELECTRICAL CHARACTERISTICS (T A = O°C to 70°C, VCC = 5 V ± 5%)
Parameter
Input Low Voltage
Input High Voltage

XTAL 1, XTAL2
All Other Inputs

Output Low Voltage
(lOL = 1.6 mAl
Output High Voltage (Except INTR)
(lOH = -100/LA)
Input Leakage Current
Win = 0 to VCC)

Symbol

Min

Typ

Max

Unit

VIL

-

-

0.8

V

VIH

4.0
2,0

-

-

V

-

-

0.4

V

-

-

V

10

/LA

-

10

/LA

-

150

mA

VOL

XT AL2/BRCLK
All Other Inputs

Data Bus Hi-Z Leakage Current
(VO = 0 to VCC)
Power Supply Current

3-26

-

VOH

2.4

IlL

-10

ILL

-10

ICC

-

-100
-

MC2671

AC ELECTRICAL SPECIFICATIONS -

READ CYCLE (TA

=

ooc to 70°C, VCC

=

±5%) (See Figure 1)
Symbol

Parameter

Min

Typ

Max

Unit

Address Setup Time to R

tAS

50

-

-

ns

CE Setup Time to R

tcs

50

-

-

ns

Read Cycle Pulse Width

tpw

250

-

-

ns

Address Hold Time from R

tAH

20

-

-

ns

CE Hold Time from R

tCH

0

-

-

ns

Data Delay Time for Read Cycle
(Cl = 150 pF)

too

-

-

200

ns

Data Bus Floating Time for Read Cycle
(Cl = 150 pF)

tDF

10

-

100

ns

Access Delay Time from any Read to Next Read or Write

tAD

250

-

ns

-

I

FIGURE 1 - READ CYCLE TIMING DIAGRAM

CE
tCH
AO-A2

~--------tAD---------+~'

AC ELECTRICAL SPECIFICATIONS -

WRITE CYCLE (TA

=

OOC to 70°C, VCC

Parameter

± 5%) (See Figure 2)
Symbol

Min

Typ

Max

Unit

Address Setup Time to W

tAS

50

-

-

ns

CE Setup Time to W

tcs

50

-

-

ns

Write Cycle Pulse Width

tpw

250

-

-

ns

Address Hold Time from W

tAH

20

-

-

ns

CE Hold Time from W

tCH

0

-

-

ns

Data Setup Time

tDS

100

-

-

ns

Data Hold time

tDH

10

-

-

ns

Access Delay Time from any Write to Next Read or Write

tAD

250

-

-

ns

Access Delay Time from Reset Command to Next Read or Write

tAD

1.0

-

-

p's

FIGURE 2 - WRITE CYCLE TIMING DIAGRAM
CE
AO-A2

w
DO-D7------------------~

3-27

MC2671

AC ELECTRICAL SPECIFICATIONS -

± 5%) (See Figure 3)

INTERRUPT KNOWLEDGE (T A = OOC to 70°C, VCC
Symbol

Min

Typ

Max

Unit

INTA Pulse Width

tpWI

300

-

-

ns

Oata Oelay Time for Interrupt Vector
(CL = 150 pF)

tOOl

-

-

250

ns

Oata Bus Floating Time after INT A
(CL = 150 pF)

tOFI

10

-

100

ns

INTA to INTA ACcess Oelay Time

tAOI

300

-

Parameter

-

ns

FIGURE 3 - INTERRUPT KNOWLEDGE TIMING

II

V I H t = t P W I - - i t_ _ _ _ tAOI _ _ _ _---<~

r-

POI={~tDFI
Valid
)>-_________

VIL
00-07 _ _ _ _ _ _ _ _ _--<
_
(Interrupt Vector)

,

AC ELECTRICAL SPECIFICATIONS -

± 5%) (See Figure 4)

INTERRUPT RESET (T A = OOC to 70°C, VCC

Parameter

Symbol

INTR Delay Time from:
Read RxHR (RxRDY)
Read KHR (KROY)
Reset Commands (KOVR, KERR, BREAK)
Load TxHR (TxEMT, TxROY)
Mask Bit Reset

Typ

Max

-

-

-

-

400
400
450
400
300

Min
-

FIGURE 4 -

-

-

-

-

INTERRUPT RESET TIMING DIAGRAM

VIH1f4____ tRI _ _ __
INTR ____________________________________

3..28

Unit
ns

tRI

-J~----------

MC2671

AC ELECTRICAL SPECIFICATIONS - KEYBOARD (TA

= ODC to

70 DC, VCC

=

±5%) (See Figures 5 and 6)

Parameter

Symbol

KClK Frequency

fKClK

KRi, KCi, to KRET Sample Delay Time:
Fast Scan
Slow Scan

tKSD

Scan Time per Matrix Position:
Fast Scan
Slow Scan

tpos

KDRES Delay Time from KClK
(Cl = 150 pF)

tKRD

KDRES Hold Time from KClK
(Cl = 150 pF)

tKRH

HYS Delay Time from KClK
(Cl = 150 pF)

Min

409

-

12.0
55.0

-

-

-

20
80

-

-

-

400

-

-

400

-

-

600

-

-

400

-

Unit
kHz
/ls

/ls

ns
ns
ns

tHYSD

KRi, KCi Delay Time from KCLK
(Cl = 150 pF)

Max

Typ

-

ns

tRCD

I

FIGURE 5 - KEYBOARD SCAN TIMING DIAGRAM
~

___________ tpos ____________

~

KClK 400 kHz

l

Ji

tKRD
KDRES
HYS
KRO-KR2
KCO-KC3

-j I-

l/fKClK

~ tKRH
__~__________________~r--l~

_____________

~_tH~Y~S~D~__________________~)(~______________

:::::1r-_t:..:;RC~D,,--_ _ _ _ _ _ _ _ _----. ~--------

===:x

X'---_________

~I- - - t K B D - - - _ I
KRET, Shift Control, and
Repeat Sample Time _ _ _ _ _ _ _ _ _ _ _ _ _
NOTE: Scan timing shown is for fast scan (KMR1
run at 14 the shown rates.

n

~

L._ _ _ _ _ _ _ _ _ _ _ _ _ __

1). For slow scan (KMR1

=

0). All signals except KlCK

FIGURE 6 - KEYBOARD TIMING

KRO~~JlI1J1J1fLI1~~~J111flf1J1_ 1 Scan Cycle

Key 1
KRET

I

I

~~~l
I~
I

KC3!

Key 1

Key 2

Key 1

Key 2

Key 1

~,~t---fL~·t-l----fG~'-------~nl~----'rL

I

n
,...

It
I
N·Key Rollover U
Modes Only

KRDY
(KSRO)-----------------------------~

2 Key Rollover
2 Key Inhibit

Read KHR (K 1)
KERR
(KSR1)----------------__------------------------------------------~
INTR

3-29

r-

MC2671

AC ELECTRICAL SPECIFICATIONS -

UART (TA

=

OOC to 70°C, VCC

=

±5%) (See Figures 7, 8, and 9)

Parameter

Symbol

Min

Typ

Max

Unit

RxD Setup Time

tRxS

200

-

-

ns

RxD Hold Time

tRxH

200

-

-

ns

TxD Delay Time from Falling Edge of TxC
(Cl = 150 pF)

tTxD

-

-

300

ns

Skew Between TxD Transition and Falling Edge of TxC Output (Cl

=

tTCS

-

0

-

ns

XTAl1 Clock High (see Figures 10 and 11)

150 pF)

tBRH

70

-

-

ns

XT Al 1 Clock low (see Figures 10 and 11)

tBRl

70

-

-

ns

BRG Input Frequency

fBRG

1.0

4.915

5.075

MHz

-

-

1.3
1.0

TxC or RxC Input Frequency
Clock Rate Factor = 16X, 32X, 64X
Clock Rate Factor = 1 X

MHz

fR/T

TxC or RxC Clock High

tR/TH

350

-

-

ns

TxC or Rxe Clock low

tR/Tl

350

-

-

ns

I
FIGURE 7 -

CLOCK, TRANSMIT, AND RECEIVE TIMING DIAGRAMS
CLOCK

XT Al 1, TxC, RxC

TRANSMIT

TxC
(Input)

TxD

TxC
(Output)

RECEIVE

MC2671

FIGURE 8 - TRANSMITTER TIMING DIAGRAM
(5-Bit Characters, No Parity, 2 Stop Bits)

TxC
Data 2

TxD

Data 3

TxEN
CEfor __~____- ,
Write of
THR
TxRDY
(CSR1)

r---~----~ r--------~~----------------------~ ~----------------------~----

TxEMT
(CSR2)----------------------------------------------~

__________--iA
TxD

B CAB C

~f===~Br~e~ak~1====:::::..!B~r~ea~k~2~==__=1l==::::1

I
I

A

E

B
Data

C -D

3--=i

TxEN

CEfor~~__~ r---~-------, ~----~------------------------------------~---------------

Break
Command
TxRDY
(CSR1)

Transmit Break
CSR3-------I
TxEMT

(CSR2)-------------------------------------------r--~----~~------~

Write of-----------------------------------------.
THR

A
B
C
D

=
=
=
=

Start Bit
First Stop Bit
Second Stop Bit
Mark

3-31

r-""7''--------------~.__---------------------

MC2671

FIGURE 9 - RECEIVER TIMING DIAGRAM
(5-Bit Characters, No Parity, 2 Stop Bits)

RxC
RxD
RxEN

IT

for
Ready of
RHR
RxRDY
(CSRO)
ROVRUN
(CSR5)

I

RxD

_ _ _-, A r--_ _ _ _-rB;;...,..C,;:;-, A

I I

Datal

I

I

B

A

~

B

_Data3_

RxEN
Framing
Error (CSR6)
Received
Break (CSR4~
CE for Reset
Command
with 04= 1
ISR5
(Break Detect
Change)

A = Start Bit
B = First Stop Bit
C = Second Stop Bit

FIGURE 10 - CRYSTAL CONNECTIONS BRG CLOCK
MC2671
XTAL1
4.9152 MHz CJ
XTAL2

FIGURE 11 - CONNECTION FOR EXTERNAL BRG CLOCK SOURCE
MC2671

;-------1 XTAL 1

4.9152 MHz

XTAL2

3·32

MC2671

SIGNAL DESCRIPTION

RECEIVER CLOCK (RxC)
The function of this input/output pin depends on BRR6.
If the external receiver clock is selected (BRR6 = 0), this
pin is an input for the receiver clock. If internal receiver
clock is selected (BRR6 = 1), this pin is an output which
is a multiple of the actual baud rate (1 X, 16X) as selected
by BRR4. The received data is sampled on the rising edge
of RxC. This pin is an input after power on and after master
reset or communications reset commands.

The input and output signals for the PKCC are described
in the following paragraphs.

VCC AND VSS
Power is supplied to the PKCC using these two pins.
VCC is the + 5 volt power supply and VSS is the ground
connection.

TRANSMITTER DATA (TxD)
This output is the transmitted serial data; the least
significant bit is transmitted first. This pin is high after
power-on reset or a reset command that affects the
transmitter.

DATA BUS (DO-D7)
This 8-bit three-state bidirectional data bus makes all
data, command, and status transfers. DO is the least
significant bit and 07 is the most signficant bit.
ADDRESS BUS (AO-A2)
These input lines are used to select internal PKCC
registers or commands.

RECEIVER DATA (RxD)
This input is the serial data input to the receiver. The
least significant bit is received first.

READ STROBE (R)
This input, when low, gates the selected PKCC register
onto the data bus if chip enable is also low.

CONNECTIONS FOR CRYSTAL (XTAL 1, XTAL2/BRCLK)
The crystal connections provide an on-chip clock
generator for the internal baud-rate generator and the
keyboard interface logiC. If an external clock is provided,
use XT AL2 as the clock input. See Figures 10 and 11.
All timing parameters such as keyboard scan times, tone
frequency, and baud rate assume a clock input at the
specified BRG input frequency. If this frequency is different, the timing parameters will vary proportionately.

WRITE STROBE (W)
This input, when low, gates the contents of the data
bus into the selected PKCC register if chip enable is also
low.
.
CHIP ENABLE (CE)
This input, when high, places the data bus output drivers
in a high-impedance condition. If chip enable is low, data
transfers are enabled in conjunction with the read and write
inputs.

KEYBOARD ROW SCAN (KRO-KR2)
This output is decoded externally and selects one of
eight rows.
KEYBOARD COLUMN SCAN (KCO-KC3)
This output is decoded externally and selects one of 1 6
columns.

INTERRUPT REQUEST (lNTRj
Using this active low open-drafn output, several conditions may be programmed to request an interrupt to the
CPU. This pin will be inactive after power-on reset or a
master reset command.

KEY RETURN (KRET)
This input, when active high, indicates that the key being
scanned is closed.

INTERRUPT ACKNOWLEDGE (lNT A)
This input is used to indicate that an interrupt request
has been accepted by the CPU. When INTA goes low, the
PKCC outputs an. 8-bit address vector on 00-07 corresponding to the highest priority interrupt currently active.

SHIFT KEY (SHIFT)
This is the active low input from the shift key. The combination of SHIFT and CONTROL inputs selects one of four
possible codes from the internal key encoding ROM.

EXTERNAL INTERRUPT (XINTR)
This is an active low external interrupt input to the PKCC
interrupt priority receiver.

CONTROL KEY (CONTROL)
This is the active low input from the CONTROL key. The
combination of SHIFT and CONTROL inputs selects one
of four possible codes from the internal key encoding ROM.

TRANSMITTER CLOCK (TxC)
The function of this input/output pin depends on bit 7
of the baud-rate control register (BRR7). If the external
transmitter clock is selected (BRR7 = 0), this pin is an input for the transmitter clock. If the internal transmitter
clock is selected (BRR7 = 1)' this pin is an output which
is a multiple of the actual baud rate (1 X, 16X) as selected
by BRR5. The data is transmitted on the falling edge of
TxC. This pin is an input after power on and after master
reset or communications reset commands.

REPEAT KEY (REPEAT)
This is the active low input from the REPEAT key which
causes the key depression currently active to be repeated
at a rate of approximately 15 times per second.
KEYBOARD CLOCK (KCLK)
This high frequency (approximately 400 kHz) output is
used to scan capacitive keyboards.

3·33

I

MC2671

TIMING

KEY DETECT RESET (KDRES)
This output resets the analog detector before scanning
a key. It is used for capacitive keyboards.

The PKCC contains a baUd-rate generator (BRG) which
is programmable to accept external transmit or receive
clocks or to divide an external clock to perform data communications. The unit can generate 16 baud rates, any of
which can be selected for full-duplex operation. The external clock to the baud-rate generator can be applied
directly to the XTAL2 input (see Figure 11) or can be
generated internally by connecting a crystal across the
XTAL 1, XTAL2 input pins. The clock input is also utilized
by the keyboard en .·der section. Thus, a clock must be
provided even if external transmitter and receiver clocks
are used.

HYSTERESIS OUTPUT (HYS)
This output is sent to the analog detector for capacitive
keyboard applications. A low indicates the key currently
scanned has been recognized on previous scan cycles.
SQUARE WAVE OUTPUT (TONE)
This output is used for tone generation.

FUNCTIONAL DESCRIPTION

I

RECEIVER
The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for break
conditions, framing and parity errors, and loads an
"assembled" character in the receive holding register for
access by the CPU.

The programmable keyboard and communications controller (PKCC) consists of six major sections. These are the
transmitter, receiver, timing, operation control, keyboard
encoder, and a priority encoded interrupt control unit.
These sections communicate with each other via an internal data bus and an internal control bus. The internal
bus interfaces to the microprocessor data bus via a bidirectional data bus buffer.

TRANSMITTER
The transmitter accepts parallel data loaded by the CPU
into the transmit holding register and converts it to a serial
bit stream framed by the start bit, calculated parity bit (if
specified). and stop bit(s). The composite serial stream of
data is transmitted on the TxD output pin.

OPERATION CONTROL
This functional block stores configuration and operation
commands from the CPU and generates appropriate signals
to various internal sections to control the overall device
operation. It contains read and write circuits to permit communications with the microprocessor via the data bus and
contains mode registers KMR and CMR, the command
decoder, and status registers KSR and CSR. Details of
operating modes and status information are presented in
OPERATION. The register addressing is specified in
Table 1.

TABLE 1 CE

A2

Al

AO

1
0
0
0
0

X
0
0
0
0
0
0
0
1
1
1
1
1

X
0
0
0
1
1
1
1
0
0
1
1
1

X
0
0
1
0
0
1
1
0
1
0
1
1

0
0
0
0
0
0
0
0

KEYBOARD ENCODER
The keyboard encoder provides encoded scanning
signals for a matrix keyboard. Key depressions are
detected on the KRET input. The debounced and verified
key codes (or matrix addresses) are loaded into the key
holding register for access by the CPU. Figures 12 and 13
illustrate the PKCC interface to contact and capacitive
keyboards, respectively.

REGISTER ADDRESSING

R,W

X

Function
Three-State Data Bus

W

Reset Command

R

Read Interrupt Status Register (lSR)

R,W

Read/Write Communications Mode Register (CMR)

W

Write Transmit Holding Register (TxHR)

W

Write Baud-Rate Mode Register (BRR)

R

Read Receiver Holding Register (RxHR)

ff

Read Communications Status Register (CSR)

R,W

Read/Write Interrupt Mask Register (lMR)

R, W

Read/Write Keyboard Mode Register (KMR)

R

Read Keyboard Holding Register (KHR)

R

Read Keyboard Status Register (KSR)
W

Miscellaneous Commands

X = Don't Care

3-34

MC2671

FIGURE 12 - CONTACT KEYBOARD INTERFACE
KRET

~

KRO-KR2

Digital Multiplexer
8 Rows

I

PKCC
roo---

4

1-of-16
16
Decode Columns

KCO-KC3

------.

Contact
Keyboard
Matrix

FIGURE 13 -

I

CAPACITIVE KEYBOARD INTERFACE

Analog
Detector
KRET
HYS
KDRES

1'f
~

KRO-KR2

Analog Multiplexer

J

8 Rows
PKCC

-

KCLK
KCO-KC3

1-of-16
Decode

16 Columns

-

~
Capacitive
Keyboard
Matrix

INTERRUPT CONTROL
The interrupt controller unit contains a software programmable interrupt mask register which selectively
enables status conditions from the keyboard encoder and
communication controller to generate interrupts. The interrupts are priority encoded and individually generate an
8-bit vector which is output on the data bus in response
to a CPU interrupt acknowledge on the INTA input pin.

data register (KDR). If the keyboard holding register is
empty, the contents of the KDR will be transferred to the
KHR immediately; if the KHR is full (i.e., the CPU has not
read the previous key code), the transfer will be held off
until the KHR is read. The data transfer to the KHR causes
keyboard data (KRDY) to be set in the keyboard status
register.
For capacitive keyboards, the high frequency output
KCLK can be used to gate the column scan to the keyboard
(see Figure 13). The key detector reset (KDRES) output
resets the analog detector prior to scanning each keylocation. The output from the analog multiplexer is sensed and
then latched in the analog detector. The HYS output controls the sense level. A zero will lower the sense level causing hysteresis, and a one will raise the sense level with
no hysteresis.
The REPEAT input enables the keyboard logic to
recognize any key repeatedly, 15 times per second. Additionally, certain keys can be programmed to repeat
automatically if depressed for more than one-half second.
A square wave is output on the TO('JE pin when the CPU
issues a ring tone command to the PKCC.

OPERATION
KEYBOARD ENCODER
The keyboard is continuously scanned by KCO-KC3 and
KRO-KR2 which are decoded externally to handle 1 28
possible keys (see Figures 12 and 13). KCO-KC3 select
one of 16 columns and KRO-KR2 multiplex the eight row
return lines into the KRET pin. Debouncing is accomplished
by remembering a one state at the KRET pin when a key
is being addressed and verifying it one scan later. Once
the key is verified a key code is loaded into the keyboard

3·35

MC2671

KEYBOARD MODE REGISTER

matrix (KR2-KRO = 000) produce a code both
when depressed and when released. The codes
are independent of the states of the inputs as
"SRTFT and CONTROL. If one or more of the
latched keys are depressed when the keyboard
is enabled (after a keyboard reset). the
corresponding codes will be sent out as the keys
are scanned and debounced. Note that
simultaneous latched keys will not set KERR
(KSR1) and that latched keys will not be autorepeat and will not be affected by the REPEAT
input.
Two-Key Rollover. The first key code is loaded into
the KDR immediately and the second code is
loaded only after the first key is released.
Simultaneous keys will set KERR (KSR1). If three
or more keys remain closed at any given time,
the KERR bit will also be set. All keys must then
be released before the next KRET will be
processed.
Two-Key Inhibit. All keys must be released between
keystrokes; otherwise, KERR (KSR1) will be set.

Operating modes are selected by programming the
keyboard mode register (KMR), whose format is illustrated
in Figure 14.
Bit KMR7 is used for testing the device. For normal
operation, this bit should always be written to a zero.
Bits KMR6-KMR5 select the rollover modes for keyboard
processing:

I

N-Key Rollover. In this mode, the code corresponding
to each key depression is loaded into the KDR as
soon as that key is debounced, independent of
the release of other keys. Two or more closures
occurring within one scan cycle are considered
to be simultaneous which will set keyboard error in the keyboard status register (KSR1). As
soon as the keyboard holding register is empty
the code in the KDR is transferred to the KHR and
the KRDY status bit is set (KSRO).
N-Key Rollover with Latched Keys. This mode is the
same as regular N-key rollover, except that the
keys which are assigned to row of the keyboard

a

FIGURE 14 - KEYBOARD MODE REGISTER FORMAT

Test Mode _ _ _ _ _---',

L T o n e Select
o = 1 kHz
1 = 2 kHz

1 = Enable
Disable

o=

Rollover Modes - _ _ _ _ _ _ _ _-'
00 = N-Key with
Latched Keys
01 = N-Key
10 = Two Key
11 = Two-Key
Inhibit

o=

Encoded - - - - - - - - - - - -.....
Keyboard
= Non-Encoded
Keyboard

KM R2

KMR1

Key
Matrix
Size

0
0
1
1

0
1
0
1

128
128
80
80

. L - - - - - - - - - A u t o Repeat
o = Disable
1 = Enable

3-36

Scan
Time
10 ms
2.5 ms
6.4 ms
1.6 ms

MC2671

Bit KMR4 specifies the key encoding mode. Each key
is assigned four a-bit codes, corresponding to the states
of the SHIFT and CONTROL inputs. If the encoded mode
is programmed, the row/column address of the detected
key is used to load one of the four key codes into the KDR.
See Table 2 for key code assignments. If the non-encoded
mode is programmed, the row/column address is loaded
directly into the KDR with the following format:

KDR
7

6

l. mom,",~Kk~:;
o.. :"

o

2

3

4

KC:' K:,. KCO [KR2.

"1" for latched keys release
"0" for latched keys depress

TABLE 2 -

K~"

KRO

I

STANDARD KEY CODES (HEX)

Row (KR3-KRO)
Column
(KC3-KCO)
0

1

2

3

4

5

6

0
EO
FO
EO
FO
El
Fl
El
Fl
E2
F2
E2
F2
E3
F3
E3
F3
E4
F4
E4
F4
E5
F5
E5
F5
E6
F6
E6
F6

1
CO
DO
CO
DO
Cl
Dl
Cl
Dl
C2
D2
C2
D2
C3
D3
C3
D3
C4
D4
C4
D4
C5
D5
C5
D5
C6
D6
C6
D6

2

lB
lB
lB
lB
21
31
21
31
22
32
22
32
23
33
23
33
24
34
24
34
25
35
25
35
26
36
26
36

ESC
ESC
ESC
ESC
!
1
!
1

..

2

..

2
#

3
#

3
$

4
$

4
%

5
%

5
&

6
&

6

3
09
HT
HT
09
09 • HT
09 • HT
DCl
11
11
DCl
Q
51
71
q
17
ETB
17
ETB
57
W
w
77
ENQ
05
ENQ
05
45
E
65
e
12
DC2
12
DC2
52
R
72
r
14
DC4
14
DC4
54
T
74
t
19
19
59
79

EM
EM
Y
y

4
IF
IF
IF
IF
01
01
41
61
13
13
53
73
04
04
44
64
06
06
46
66
07
07
47
67
08
08
48
68

US
US
US
US
SOH
SOH
A
a
DC3
DC3
S
s
EOT
EOT
D
d

ACK
ACK
F
f

BEL
BEL
G
9

BS
BS
H
h

lA
lA
5A
7A
18
18
58
78
03
03
43
63
16
16
56
76
02
02
42
62
OE
OE
4E
6E
OD
OD
4D
6D

5
SUB
SUB
Z
z
CAN
CAN
X
x

ETX
ETX
C
c
SYN
SYN
V
v

STX
STX
B
b

SO
SO
N
n

CR
CR
M
m

6
30
0
30
0
30
0
30
0
3D
=
2D
3D • =
2D • lE
RS
RS
lE
7E
5E

t

lC
FS
lC
FS
I
7C
I
5C
'-....
08
BS
BS
08
08 • BS
08 • BS
10
DLE
10
DLE
50
P
70
p
00
00
60
40

NUL
NUL
@

7
2B
3B
2B
3B
2A
3A
2A
3A
IF
IF
7F
5F
lB
lB
7B
5B
lD
lD
7D
5D
08
08
08
08
09
09
09
09

+
;

+

.
;

.
:
:

US
US
• DEL
• ESC
ESC

{

[
GS
GS

}

]
BS
BS
BS
• BS
HT
HT
• HT
• HT
Continued

3-37

MC2671

TABLE 2 -

STANDARD KEY CODES (HEX) (Continued)
Row (KR3-KRO)

Column
(KC3-KCO)

2

E7
F7
E7
F7

C7
D7
C7
D7

27
37
27
37

E8
F8
E8
F8

C8
D8
C8
D8

28
38
28
38

9

E9
F9
E9
F9

C9
D9
C9
D9

29
39
29
39

A

EA
FA
EA
FA

CA
DA
CA
DA

37
37
37
37

B

EB
FB
EB
FB

CB
DB
CB
DB

C

EC
FC
EC
FC

D

3

<

j

3C
2C
3C
2C

OB
OB
4B
6B

VT
VT
K
k

3E
2E
3E
2E

>

0
a

OC
OC
4C
6C

FF
FF
L
I

3F
2F
3F
2F

34
34
34
34

4
4
4
4

31
31
31
31

1
1
1
1

30
30
30
30

8
8
8
8

35
35
35
35

5
5
5
5

32
32
32
32

2
2
2
2

9
9
9
9

36
36
36
36

6
6
6
6

33
33
33
33

3
3
3
3

NAK
NAK
U
u

OA
OA
4A
6A

09
09
49
69

HT
HT
I
i
SI
SI

9

OF
OF
4F
6F

7
7
7
7

38
38
38
38

CC
DC
CC
DC

39
39
39
39

ED
FD
ED
FD

CD
DD
CD
DD

90
90
90
90

93
93
93
93

E

EE
FE
EE
FE

CE
DE
CE
DE

91
91
91
91

80
80

F

EF
FF
EF
FF

CF
DF
CF
DF

92
92
92
92

8

I

6

5

4

15
15
55
75

7

I

1

0

7
7
(

8
(

8
)

9
)

80 •
80 •
94
94
94
94

82
82
82 •
82 •
84
84
84
84
83
83
83 •
83 •

LF
LF

J

DEL
DEL
DEL
DEL

OA
OA
OA
OA

LF
LF
LF
LF

I

OD
OD
OD
OD

CR
CR
CR
CR

0
0
0
0

AO
BO
AO
BO

LF
LF
LF
OA •
OA • LF
A6
B6
A6
B6

2E
2E
2E
2E

A1
B1
A1
B1

A7
B7
A7
B7

BF
AF
9F
8F

A2
B2
A2
B2

A8
B8
A8
B8

95
95
95
95

A3
B3

A9
B9

A3 •
B3 •
A4
B4
A4·

A9 •
B9 •
AA
BA

<

>
?
I

?

81
81
81 •
81 •
96
96
96
96

CONTROL
(Pin 13 = 0)

This row contains the
latched keys when that
mode is selected (KMR6,
KMR5 = 00).

7

7F
7F
7F
7F

20
20

SP
SP
20 • SP
20 • SP
OB
VT
OB
VT
OB • VT
OB • VT
OA
OA

B4 •
A5
B5

AA •
BA •
AB
BB

A5 •
B5 •

AB •
BB •
= 0)

~

Latched key code for release
Latched key code for depress

' - - - - - ASCII equivalent (if any)
• Indicates Auto-Repeat keys

Bit KMR3 enables the auto-repeat mode. In this mode,
if a key that is programmed for auto-repeat is depressed
for longer than one-half second, the key code will be loaded
into the KDR approximately 1 5 times per second until that
key is released. Only the non-control codes will autorepeat, i.e., CONTROL = 1. Table 2 specifies the autorepeat keys.
KMR2 and KMR 1 select the key matrix size and
debounce time (scan rate). The keyboard row outputs
(KR2, KR1, KRO) always scan from 0 to 7. The column

outputs (KC3, KC2, KC1, KCO) scan from 0 to 15 for a
128-key matrix and from 0 to 9 for an 80-key matrix.
KMRO selects between a 1 kHz and 2 kHz frequency to
be output on the TONE pin in response to a ring tone
command.

KEYBOARD STATUS REGISTER
The keyboard status register (KSR) provides operational
feedback to the CPU. Its format is illustrated in Figure 15.

3-38

MC2671

FIGURE 15 -

KEYBOARD STATUS REGISTER FORMAT

KSR

:::0'

4

I

o

2

~
I

I
ShiftLOCk~
_I

3

LKRDY

~KERR

Repeat --------------------~

KSR7, KSR6, and KSR4 reflect the state of the inputs
at the corresponding pins. CONTROL and SHIFT are
latched at the time the key is accepted. As the verified
codes are loaded into the KDR, the corresponding states
of CONTROL and SHIFT are loaded into the KSR. REPEAT
is updated on every matrix example. The status bits are
the complements of the input levels.
KSR5 reflects the state of the internal shift lock flag
which is controlled by the set/reset shift lock commands.
KSR3 indicates that the keyboard controller is enabled.
It is controlled by the set/clear keyboard enable command.
Keyboard overrun (KSR2) is set when both the KHR and
KDR are full and a third key is validated. The original content of the KHR is preserved and the content of the KDR
is overwritten with the new key code. This bit can be
specified (by IMR1) to generate an interrupt and is cleared
by the reset command with D2 = 1 .
Keyboard error (KR1) is set when the operator depresses
more keys than are allowed in the selected rollover mode,
or when keys are depressed simultaneously (within one
scan cycle). This bit can be specified (by IMR3) to generate
an interrupt and is cleared by the reset command with
D1 = 1.
Keyboard data ready (KSRO) is set when the key code
or address is transferred from the KDR to the KHR. This
bit can be specified (by IMR2) to generate an interrupt.
It is cleared when the CPU reads the KHR.

KOVR
Keyboard Enabled

receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper
number of data bits and the parity bit (if any) have been
assembled, and one stop bit has been detected. The least
significant bit is received first. The data is then transferred
to the receive holding register (RxHR) and the RxRDY bit
in the CSR is set to a one. If the character length is less
than eight bits, the most significant unused bits in the
RxHR are set to zero.
After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero
character was received without a stop bit (i.e .. framing
error) and RxD remains low for one half of the bit period
after the stop bit was sampled, then the space is interpreted as a start bit.
The parity error, framing error, and overrun error (if any)
are strobed into the CSR at the received character boundary. If a break condition is detected (RxD is low for the
entire character including the stop bit) only one character
consisting of all zeros will be transferred to the RxHR and
the received break bit in the CSR is set to one (RxRDY is
not set when a break is received). The RxD input must
return to a high condition for one bit time before a search
for the next start bit begins.

TRANSMITTER
The transmitter accepts parallel data from the CPU and
converts it to a serial bit stream on the TxD output pin.
It automatically sends a start bit followed by the data bits,
an optional parity bit, and the programmed number of stop
bits. The least significant bit is sent first. Following the
transmission of the stop bits, if a new character i5 not available in the transmit holding register (TxHR), the TxD output remains high and the TxEMT bit in the CSR will be set
to one. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the TxHR. The
transmitter can be forced to send a continuous low condition by a transmit break command.
If the transmitter is disabled, it continues operating until the character currently being transmitted is completely
sent out.

COMMUNICATIONS CONTROLLER
The communications controller section of the PKCC
comprises a full duplex asynchronous receiver/transmitter
(UART) with a baud-rate generator. Registers associated
with these elements are the communications mode register
(CMR), the baud-rate control register (BRR), and the communications status register (CSR).
RECEIVER
The receiver accepts serial data on the RxD pin, converts the serial input to parallel format, checks for start
bit, stop bit, parity bit (if any), or break condition, and
presents the assembled character to the CPU. The receiver
looks for a high-to-Iow (mark-to-space) transition of the
start bit on the RxD input pin. If a transition is detected,
the state of the RxD pin is sampled again after a delay of
one half of the bit time. If RxD is then high, the start bit
is invalid and the search for a valid start bit begins again.
If RxD is still low, a valid start bit is assumed and the

COMMUNICATION MODE REGISTER
Figure 16 illustrates the bit format of the CMR, which
controls the operational mode of the communications controller and the character parameters.

3-39

I

MC2671

FIGURE

16- COMMUNICATIONS MODE REGISTER FORMAT

CMR

Operating Mode
00 = Normal
01 = Auto Echo
10 = Local Loopback
11 = Remote Loopback

T

LCh."""

00 = 8 Longth
01 = 5
10 = 6
11 = 7

Parity _ _ _ _ _ _ _ _ _ _ _ _- '

'---_ _ _ _ _ 0 = Two Stop Bits
1 = One Stop Bit

o=

Odd/Force 0
1 = Even/Force 1

'--_ _ _ _ _ _ _ _ _ _ Parity Mode
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Not Allowed

I
Bits CMR1-CMRO select a character length of five, six,
seven, or eight bits. The character length does not include
the parity, start, or stop bits.
CMR2 selects the transmitted character framing as one
or two stop bits. The receiver always checks for one stop
bit.
The parity format is selected by bits CMR4 and CMR3.
If parity or force parity is selected, a parity bit is added
to the transmitted character and the receiver performs a
parity check on incoming data. CMR5 selects odd or even
parity and determines the polarity of the parity bit in the
force parity mode.
The bits in the mode register affecting character
assembly and disassembly ICMR5-CMRO) can be changed
dynamically and affect the characters currently being
assembled in RxSR and transmitted by TxSR. To affect
assembly of a received character, the CMR must be updated within n-1 bit times of the receipt of that character's
start bit. To affect a transmitted character, the CMR must
be updated within n-1 bit times of transmitting that
character's start bit In = the smaller of the new and old
character lengths).
The UART can operate in one of four modes, as illustrated in Figure 17. The operating modes are selected by

bits CMR7 and CMR6, which should only be changed
when b.oth the transmitter and receiver are operating independently. CMR7 - CMR6 = 01 places the UART in the
automatic-echo mode, which automatically retransmits the
received data. The following conditions me true while in
automatic-echo mode:

1. Data assembled by the receiver is automatically
placed in the transmit holding register and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter
need not be enabled.
4. Status bit TxRDY is not set. TxEMT operates
normally.
5. The received parity is checked, but is not
regenerated for transmission, i.e., transmitted parity bit is as received.
6. Only the first character of a break condition is
echoed; the TxD output will go high until the next
received character is assembled.
7. CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled.

3-40

MC2671

FIGURE 17 - OPERATING MODES OF THE MC2671 UART

(a) Normal Operating Mode

I
(b) Automatic Echo Mode

(c) Local Loopback Mode

(d) Remote Loopback Mode

3·41

MC2671

I

Two diagnostic modes can also be configured. In local
loop back mode (CMR7 - CMR6 = 10):
1. The transmitter output is internally connected to
the receiver input.
2. The transmit clock is used for the receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver
need not be enabled.
6. CPU-to-transmitter and receiver communications
continue normally.
The second diagnostic mode is the remote loopback
mode (CMR7 - CMR6 = 11). In this mode:
1. Data assembled by the receiver is automatically
placed in the transmit holding register and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. No data is sent to the local CPU, but the error status
conditions (parity and framing) are set if required.

4. The received parity is checked, but is not regenerated for transmission, i.e., transmitted parity bit
is as received.
5. The receiver must be enabled, but the transmitter
need not be enabled.

BAUD-RATE CONTROL REGISTER
The baud-rate control register (BRR) controls the frequency generated by the baud-rate generator (BRG) and
the clock source used by the receiver and transmitter. Its
format is illustrated in Figure 18.
BRR3-BRRO select one of sixteen frequencies to be
generated by the BRG. See Table 3.
BRR7 and BRR6 select the source of the transmit and
receive clocks. If external clocks are chosen (BRR7 = 0 or
BRR6 = 0). then the clock rate factor is determined by
BRR5 and BRR4. The external clock input(s) should be the
desired baud rate multiplied by the clock rate factor.

FIGURE 18 - BAUD-RATE CONTROL REGISTER FORMAT

BRR

T, Clo,k

o=
1

=

sou,re~

External
Internal (BRG)

Rx Clock Source
o = External
1 = Internal (BRG)

IT

- [ B a U d Rate Select -

~

See Table 3

Clock Rate Factor for External
Clocks

00 = 16X
01 = 32X
10 = 64X
11 = lX
For internal clocks these
bits specify the output
frequency on pin 34 and
pin 35. See Table 4.

TABLE 3 - BAUD RATE GENERATOR CHARACTERISTICS
(BRCLK = 4.9152 MHz)

BRR3-0

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Baud
Rate

50
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
38400

Actual
Frequency

16X Clock
0.8
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4

Percent
Error

kHz

-

-0.01

-

+0.20
-

-0.20
-0.26
-

-

Divisor

6144
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
8

MC2671

set when the transmitter is enabled, provided that no data
was loaded into the TxHR during the time the transmitter
was disabled. This bit can be specified (by IMR7) to generate an interrupt.
Transmitter empty (CSR2) indicates that the transmitter
has underrun, i.e., both the TxHR and TxSR are empty.
This bit can only be set after transmission of at least one
character, and is cleared when the TxHR is loaded by the
CPU. TxEMT is reset when the transmitter is disabled. This
bit can be specified (by IMR6) to generate an interrupt.
CSR3 will be set when the PKCC receives a command
to transmit a break. This bit will be cleared after the break
is completed.
Received break (CSR4) indicates that an all zero character of the programmed length has been received without
a stop bit. Breaks originating in the middle of a received
character can be detected. This bit is cleared when RxO
returns to a high state for at least one bit time.
Receiver overrun (CSR5) indicates that the previous
character in the RxHR has not been "read by the CPU and
that a new character has been loaded into the RxHR. This
bit is cleared by a reset command with 03 = 1.

If internal clock(s) are specified, (BRR7 = 1 or BRR6 = 1),
the clock is supplied by the internal baud-rate generator
at the selected baud rate. The clock rate factor for internally generated clocks is always 16. Pins 35 and 34
become outputs for transmit or receive clocks, respectively. See Table 4 for the description and selection of these
outputs.

COMMUNICATIONS STATUS REGISTER
Figure 19 illustrates the bit format of the communications status register (CSR), which provides UART status
to the CPU.
Receiver ready (CSRO) indicates that a received character is assembled and transferred to the RxHR and is ready
to be read by the CPU. This bit can be specified (by IMRO)
to generate an interrupt and is reset by reading the RxHR.
Transmitter ready (CSR1) indicates that the TxHR is
empty and ready to be loaded with character. This bit will
be cleared when the TxHR is loaded and has not yet transferred the character to the transmit shift register (TxSR).
TxROY is reset when the transmitter is disabled. It will be

TABLE 4 -

BAUD-RATE CONTROL REGISTER

Clock Source

Pin Functions

BRR7BRR4

TxC

RxC

00**
01**
10**
1100
1101
1110
1111

E
E
I
I
I
I
I

E
I
E
I
I
I
I

Pin
34

Pin
35

BRR3-BRRO
Baud Rate Selection

TxC
TxC
16X
1X
1X

RxC
1X
RxC
1X

The baud rates are
listed in Table 3.

16X

16X
16X

NOTES
1. * * = Clock rate factor for external clocks:

00
01
10
11

1X

16X

= 16X
=32X
= 64X
= 1X

2. E = External clock.

3. I = Internal clock (BRG).
4. 1X and 16X are clock outputs at 1 or 16 times the actual baud rate. For receive. the 1 X output is the actual data sample
clock.
5. BRR7-BRR6 = 01 or 10 not permitted in automatic echo or remote loop back modes unless BRR5-BRR4 = 00.

FIGURE 19 -

COMMUNICATIONS STATUS REGISTER FORMAT

CSR

Parity

ErrorJ~

Framing Error

~

LRXRDY

~

LTXRDY

Overrun Error
Received Break _ _ _ _ _ _- - J

TxEMT
Transmit Break

3-43

I

MC2671

The bit assignments of the ISR and IMR and corresponding vectors and priorities are listed in Table 5.

Framing error (CSR6) indicates that the stop bit has not
been detected. The stop bit check is made in the middle
of the first stop bit position. This bit is cleared by a reset
command with D3 = 1 .
Parity error (CSR7) indicates that a character was received with incorrect parity when 'with parity' is enabled. This bit is cleared by a reset command with D3 = 1.

I

COMMANDS
In addition to the control exercised by programming of
the PKCC control registers, several functions can be performed by executing command operations. There are two
classes of commands which are initiated by writing to the
MC2671 at address A2 - AO = 000 (reset command) and
address A2 - AO = 111 (miscellaneous commands). Individual commands are specified by the bit pattern of the
data bus (D7 - DO).

INTERRUPT CONTROLLER
The MC2671 contains a maskable interrupt status
register (lSR) which can be enabled to generate an active
low interrupt request on the INTR output. The eight interrupt conditions in the ISR are individually enabled by
writing a one into the corresponding bit of the interrupt
mask register (lMR).
Each of the interrupt conditions is assigned a priority and
a vector. When an enabled ISR bit is set, the MC2671
asserts the INTR output. If the CPU activates the INTA input, the MC2671 responds by placing the corresponding
8-bit on the data bus (D7-DO). If multiple interrupts are
pending, the vector corresponds to the condition with the
highest priority. The interrupt will persist until all pending
interrupt conditions are cleared.
The ISR can also be polled by reading at address
A2 - AO = 000. All pending interrupt conditions which are
enabled by the IMR will be read independent of priority.

RESET COMMANDS
The reset command bit format is illustrated in Figure 20
and the detailed command descriptions are given in
Table 6.
A reset command with D7 - DO = 111 XXXX 1 is a master
reset for the MC2671. This command must be given
following a power-on condition to release the internal
power-on reset latch which deactivates the MC2671 on
power up.
MISCELLANEOUS COMMANDS
The miscellaneous command format is illustrated in
Figure 21.

TABLE 5 - INTERRUPT MASK REGISTER (lMR) AND INTERRUPT STATUS REGISTER (lSR)
Bit in
IMR/ISR
IMRO!lSRO
IMR1!1SR1
IMR2/1SR2
IMR3/1SR3
IMR4!1SR4
IMR5!1SR5
IMR6/1SR6
IMR7/1SR7

Interrupt
Condition
RxRDY
KOVR
KRDY
KERR
XINT1
.:lBREAK2
TxEMT
TxRDY

Vector on 07-00
I
Binary
Hex

Priority
1
2
3
4
5
6
7
8

11001111
11010111
11011111
11100111
11101111
11110111
11000111
11000111

I

I
I

I

I
I
I

I
I
I

:

CF
D7
DF
E7
EF
F7
C7
C7

Condition Reset by:
Read RxHR
Reset CMD (D2 = 1)
Read KHR
Reset CMD (D1 = 1)
External
Reset CMD (D4 = 1)
Load TxHR
Load TxHR

NOTES:
1. XI NT is an input from an external interrupt source, active low (pin 21).
2 . .:lBREAK refers to the change of a received break condition.

FIGURE 20 - RESET COMMAND FORMAT

7

6

5

4

~

~

OOX No Effect _ _ _ _ _ _--J
010
011
100
101
110
111

Set RxE
Reset RxE
Set TxE
ResetTxE
Set TxE and RxE
Communications Reset

Break Detect Change Reset

-------~

K"booed R...,
KERR Reset

KOVR Reset

' - - - - - - - - - Communications Error Reset

3-44

MC2671

TABLE 6 -

Command

RESET COMMAND DESCRIPTION

Resets

Keyboard Reset

Comments
The keyboard controller is reset. ignoring the input at KRET.

KMR7-KMRO
KSR5. KSR2-KSRO
IMR3-IMR1

KERR Reset

KSR1

Keyboard error status bit reset.

KOVR Reset

KSR2

Keyboard overrun status bit reset.

Communications
Error Reset

CSR7-CSR5

Resets the receiver overrun. parity. and framing error status bits.

Break Detect
Change Reset

ISR5

Resets the break detect change bit in the interrupt status register.

Set RxE

See note

Enables receiver operation.

Reset RxE

CSR7-CSR4. CSRO
See note

Disables the receiver.

Set TxE

See note

Enables transmitter operation

Reset TxE

CSR3-CSR1
See note

Disables the transmitter. Sets the TxD output to a one after
transmitting the character in TxSR.

Communications Reset

CMR. CSR. BRR. TxE. RxE.
IMR7 -IMR5. IMRO

Resets the communication controller. The RxD input is ignored and
the TxD output is set to a one.

Master Reset

CMR. CSR. BRR. TxE. RxE. KMR.
KSR5. KSR3-KSRO. IMR7-IMRO.
Releases the internally latched
power-on reset.

Resets the keyboard and communication controllers. Inputs at
KRET and RxD are ignored and the TxD output is set to a one.

I

NOTE: Command does not affect the CMR or the BRR.

FIGURE 21 -

MISCELLANEOUS COMMANDS FORMAT

Clear Keyboard Enable

Transmit Character Break

Set Keyboard Enable----......I
Clear Shih Lock

'-----Transmit Timed Break

--------......1

Set Shift L o c k - - - - - - -_ _ _ _---I

' - - - - - - - - - - Ring Tone Short
' - - - - - - - - - - - - Ring Tone Long

3-45

I

MC2671

I

The transmit break commands force a break (steady low
output) on the TxD pin immediately or after the character
in the TxSR (if any) is transmitted. A timed break lasts for
approximately 200 milliseconds, and a character break
lasts for one character time including parity and stop bit
time. In either case, TxRDY (CSR1) will be set at the beginning of the break which can be extended indefinitely (by
200 milliseconds or one character time increments) by
reasserting the command in response to TxRDY. Note that
these commands reset TxRDY. When a transmit break
command is asserted, CSR3 will be set. This bit will be
cleared after the break is completed.

The set keyboard enable command enables the keyboard
controller and sets KSR3 in the keyboard status register.
The clear keyboard enable command resets KSR3 and
disables key processing at the KRET input. The keyboard
controller is not reset by this command, and the current
state of the keyboard (key depressions and latched key
states) is preserved internally. When the keyboard is subsequently enabled, key processing. resumes, old and new
keys are debounced, and latched keys are encoded if there
has been a change in their state.

The ring tone commands cause the tone generator to
output a square wave on the TONE output. The tone durations are specified by the commands.

Characteristics of certain portions of the PKCC are internally programmed by means of a ready-only memory.

MASK PROGRAMMABLE OPTIONS

The items which can be programmed are:
• Key codes
• Auto-repeat keys
• Scan times, tone frequency, and tone duration
• Baud rates
• Interrupt vectors
Consult your local Motorola representative for costs,
minimum quantities, and data submission requirements for
customized versions of the PKCC.

Ring tone short = 25 milliseconds
Ring tone long = 1 00 milliseconds
The tone frequency is either 1 kHz or 2 kHz, as specified
by KMRO.
The set/clear shift lock commands control the state of
the internal shift lock flip flop. When shift lock is set the
keyboard controller encodes all key depressions as if the
SHIFT input was asserted. The state of the shift lock flip
flop is reflected in KSR5.

3-46

®

MOTOROLA

MC2672

Advance Information
HMOS
(HIGH-DENSITY N-CHANNEL, SILICON-GATE)

PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
The MC2672 programmable video timing controller (PVTC) is a programmable device designed for use in CRT terminals and display
systems that employ raster scan techniques. The PVTC generates the
vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT monitor. It provides consecutive addressing to a user specified display buffer memory domain
and controls the CPU-display buffer interface for various buffer configuration modes. A variety of operating modes, display formats, and
timing profiles can be implemented by programming the control
registers in the PVTC. Applications include CRT terminals, wordprocessing systems, small business computers, and home computers.

PROGRAMMABLE VIDEO TIMING
CONTROLLER (PVTC)

•
•
•
•
•
•
•
•
•
•
•

4 M Hz Character Rate
Up to 256 Characters Per Row
1 to 16 Raster Lines Per Character Row
Up to 128 Character Rows Per Frame
Programmable Horizontal and Vertical Sync Generators
Interlaced or Non-Interlaced Operation
Up to 16K RAM Addressing for Multiple Page Operation
Automatic Wraparound of RAM
Addressable, Incrementable, and Readable Cursor
Programmable Cursor Size, POSition, and Blink
Split Screen and Horizontal Scroll Capability

~

•
•
•
•
•
•

Light Pen Register
Selectable Buffer Interface Modes
Dynamic RAM Refresh
Completely TTL Compatible
Single + 5-Volt Power Supply
Power-On Reset Circuit

I
SSUFFIX

CERDIP PACKAGE
CASE 734

~

PSUFFIX

PLASTIC PACKAGE
CASE711

~

PIN ASSIGNMENT

R
CE
W

A1

CTRLl

AO

CTRL2

LPS

CTRL3

iNTt\"

CURSOR

ORDERING INFORMATION (TA=O°C to 70°C)

VCC
A2

DADDO

DO

DADD1

01

DADD2

D2

DADD3/L1

D3

DADD4/LAO

Fraq,:,ency

Order Number

Plastic
P Suffix

2.7 MHz
4.0 MHz

MC2672A3P
MC2672A4P

D4

DADD5/LA1

05

DADD6/LA2

Ceramic
L Suffix

2.7 MHz
4.0 MHz

MC2672A3L
MC2672A4L

D6

DADD7/LA3

2.7 MHz
4.0 MHz

MC2672A3S
MC2672A4S

DADDS/LNZ

Cerdip
S Suffix

D7
CCLK

DADD9/LPL

BLANK
VSYNCI
CSYNC
HSYNC

DADD10/UL
DADD11
IBLINK
rDADD121
ODD
DADD13/LL

Package Type

GND
This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3·47

MC2672

BLOCK DIAGRAM

CE

Interface

Control

R
Vii

CTRL1
Display
Memory
Handshake
Logic

Initialization
and Display
Registers

Read/Write
Control Logic

Command
Decode
Logic

CTRL2
CTRL3

Display
Address
Timing
Multiplexers

Interrupt
Logic and
Status
Register

Address
Decoder

I

Cursor,
Pointer, and
Light Pen
Registers

Cursor and
Compare
Logic

Light Pen Strobe

CURSOR

~
HSYNC

~

Timing Chain
and
Decode Logic

CCLK

BLANK

Timing

ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range ,
Storage Temperature Range

THERMAL CHARACTERISTICS
Characteriatic
Thermal Resistance
Plastic Package
Ceramic Package
Cerdip Package

Symbol

Value

VCC
Yin

-0.3 to + 7.0
-0.3 to + 7.0

Unit
V
V

TA

o to 70

°c

Tstg

-55 to +150

°c

Symbol

Value

Ratina

8JA

100
50
60

°C/W

3·48

VSYNC/ CSYNC

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum-rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Vin and
Vout be constrained to the range
VSS~(Vin or Vout)~Vce· Reliability of
operation is enhanced if unused inputs
are tied to an appropriate logic voltage
level (e.g., either VSS or Vee!.

MC2672

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)
TJ=TA+(PO·OJA)
Where:
TA==Ambient Temperature, °c
OJA == Package Thermal Resistance, Junction-to-Ambient, °C/W
Po == PINT+ PPORT
PINT==ICC x VCC, Watts - Chip Internal Power
PPORT == Port Power ~issipation, Watts - User Determined
For most applications PPORT<1Ii PINT and can be neglected, PPORT may become significant if the device is configured to
drive Oarlington bases or sink LEO loads.
An approximate relationship between Po and TJ (if PPORT is neglected) is:
PO=K+(TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
K = PO.(T A + 273°C) +OJA·PD 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at equilibrium)
for a known TA Using this value of K the values of Po and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA

DC ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, VCC=5.0 V +5%)
Symbol

Min

Max

Unit

Input Low Voltage

VIL

-0.3

0.8

V

Input High Voltage

VIH

2.0

VCC

V

Output Low Voltage (ILoad= 1.6 mAl

VOL

-

OA

V

Output High Voltage (Except INTR Output) ILoad= -100 p.A

VOH

2A

lin

10

p.A

Parameter

V

Hi-Z (Ollstate) Input Current Vin-OA to 2A V

ITSI

-10
-10

10

p.A

INTR Open-Drain Output Leakage Current VOH = 2A VCC

ILOH

-

10

p.A

Internal Power Dissipation

PINT

-

800

mW

Input Leakage Current Vin = 0 to V CC

3·49

I

MC2672

AC ELECTRICAL CHARACTERISTICS -

BUS TIMING (T A = 0° to 70°C V CC = 50 V +
- 5% See Note 1)
MC2672A3
Min

Max

Min

Max

Unit

tAS

30

30

-

ns

AO-A2 Hold Time from W, R High

tAH

0

0

-

ns

IT Setup Time to W, R Low
IT Hold Time from W, R High

tcs

0

-

0

tCH

0

-

0

-

ns

W, R Pulse Width

tRW

250

-

250

-

ns

tDO

-

200

200

ns

Data Bus Floating after R High

tOF

-

100

-

100

ns

Oata Setup Time to W High

tDS

150

-

150

-

ns

Data Hold Time from W High

tOH

10

-

5

-

ns

tcc

600
300

-

600
300

-

ns
ns

AO-A2 Setup Time to W,

Data Valid after

High Time from

I

MC2672A4

Symbol

Parameter

Fl Low

Fl Low

IT to CE (see Note 2)

Consecutive Commands
Other Commands

-

-

ns

NOTES:
1. Timing is illustrated and specified referenced to Wand Rinputs. Oevice may also be operated with CE as the "strobing" input. In this case,
all timing specifications apply referenced to falling and rising edges of
2. This specification requires that the
input be negated (high) between read and/ or write cycles.

cr.

cr

BUS TIMING DIAGRAM

00-07 (Read)

Float

Float

r-

00-07 (Write) _ _ _ _ _ _ _ _ _

~~

3-50

tos
Valid

MC2672

AC ELECTRICAL CHARACTERISTICS -

CHARACTER CLOCK TIMING (TA=O°C to 70°C, VCC=5.0 V ±50/0, See Note
MC2672A3

Parameter

1)

MC2672A4

Symbol

Min

Max

Min

Max

CClK Period

tccp

370

ns

tCCH

125

250
100

-

CClK High Time

tCCl

125

100

-

ns

CClK low Time

-

Output Delay Time from CClK Edge
DADDO-DADD13, BCE, WDB, RDB, MBC
BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREQ, BACK*

tCCD
40
40

175
225

40
40

150
200

ns

Unit

ns

* BCE, WDB, and RDB delays track each other within 10 nanoseconds. Also, these output delays will tend to follow the direction (minimum/
maximum) of DADDO-DADD13 delays.

CHARACTER CLOCK TIMING DIAGRAM
~------tccp'------~

Outputs
(See Note 1)

________________- J

tCCD .........t----.t
Outputs
WDB, RDB, BCE

NOTES:
1. DADDO-DADD13, BLANK, HSYNC, CSYNC/vSYNC, CURSOR, BEXT, BREG, BCE, MBC, BACK.
2. BCE changes state on both CClK edges.

3·51

I

MC2672

AC ELECTRICAL CHARACTERISTICS -

OTHER TIMINGS (T A = O°C to 70°C V CC = 50 V +
- 5%)
MC2672A3

MC2672A4

Symbol

Min

Max

Min

Max

Unit

READY/RDFlG low fromW HIGH*

tRDl
tBAK

tCCp+30
225

-

BACK High from PGREO low

-

tcCp+30
200

ns

BEXT High from PBREO High

tBXT

-

225

-

200

ns

Light Pen Strobe Setup Time to CClK low

tlPS

120

-

-

ns

Light Pen Strobe Hold Time. from CClK low

tlPH

-10

-

120
-10

-

ns

fiiJfii low from

tlRl

-

225
600

-

200
600

ns

Parameter

CClK low

ns

ns
tlRH
* Timing is illustrated and specified referenced to Wand R inputs. Device may also be operated with CE as the "strobing" input. In this case, all
timing specifications apply referenced to falling and rising edges of CE.
INTR High from W, R High*

OTHER TIMING DIAGRAMS

I

Vertical Blanking
Interval

BLANK

First HSYNC
of VBlANK

HSYNC

VBlANK
Status Bit

BLANK

DADD3DADD13

Multiplexed
Signals Valid

line Zero and
Split Screen
Status Bit _ _ _ _ _ _ _ _ _ _ _ _ _-+-__

tIRL~

----\1
~

INTR

~---------------------

3·52

MC2672

OTHER TIMING DIAGRAMS (Continued)

LPS

Light Pen
Status Bit

tiRL~

~-----

DADDODADD13

Character
Address n

Vi for a
Delayed
Command

~tRDLr

W or RWhich

\

Resets
Interrupt

PBREQ

~I

\

~
BACK

tBAK

~

/

BEXT

Ready or
RDFLG Status
Bits

INTR

~

\

j

tlRH

r/

3-53

1Vr-

tBXT

I

MC2672

COMPOSITE SYNC TIMING DIAGRAM

Even Field
~
Last Displayed Scan
of Previous Field
Vertical Front
CSYNC

I

Porch--....,.~.~Vertical SYNC

~

Pulse

+-

Vertical Back

First Displayed Scan

Porch~

of Even Field
HOrizontal Sync

Interval---------~-~LSL

Odd Field
LtD· I d S can
as f ElspaYFe Id
!.-Vertical FrontPorch - Y, H+vertical SYNC~Vertical Back Porch oven Ie
Pulse
~y,Hk-

I

I

Pulses

BLANKLP04-------------Vertical Blanking

~

CSYNC

I

I-

I-

~-----------Vertical Blanking Interval

~ First Displayed Scan
y, H
of Odd Field

I

_ _________
~~I~

.~HP~d

~/' L...J

L

Horizontal Blanking Interval
NOTES:
1. In non-interlaced operation the even field is repeated continuously, and the odd field is not.
2. In interlaced operation the even field alternates with the odd field.

SIGNAL DESCRIPTION

WRITE STROBE (W)

The input and output signals for the PVTC are described in
the following paragraphs.

This pin is an active low input. A low on this pin while chip
enable is also low causes the contents of the data bus to be
transferred to the register selected by AO-A2. The transfer
occurs on the rising edge of W.

VCC AND GND
Power is supplied to the PVTC using these two pins. VCC
is the + 5 volts ± 5% power input and GNO is the ground
connection.

CHIP ENABLE (CE)

ADDRESS LINES (AO-A2)

These lines are used to select PVTC internal registers for
read/write operations and for commands.
DATA BUS (DO-D7)
These lines comprise the 8-bit bidirectional three-state
data bus. Bit 0 is the least significant bit and bit 7 is the most
significant bit. All data, command, and status transfers between the CPU and the PVTC take place over this bus. The
direction of the transfer is controlled by the read and write inputs when the chip enable input is low. When the chip
enable input is high the data bus is in the high-impedance
state.
READ STROBE (R)

This
enable
AO-A2
on the

pin is an active low input. A low on this pin while chip
is low causes the contents of the register selected by
to be placed on the data bus. The read cycle begins
falling edge of R.

This pin is an active low input. When low, data transfers
between the CPU and the PVTC are enabled on 00-07 as
controlled by the IN, R, and AO-A2 inputs. When
is high,
the PVTC is effectively isolated from the data bus and DO
through 07 are placed in the high-impedance state.

cr

CHARACTER CLOCK (CCLK)
This pin is the timing signal derived from the video dot
clock which is used to synchronize the PVTe's timing functions.
HORIZONTAL SYNC (HSYNC)
This pin is an active high output which provides video
horizontal sync pulses. The timing parameters are programmable.
VERTICAL SYNC/COMPOSITE SYNC (VSYNC/CSYNC)
A control bit selects either vertical or composite sync
pulses on this active high output. When CSYNC is selected,
equalization pulses are included. The timing parameters are
programmable.

MC2672

BLANK (BLANK)

DISPLAY ADDRESS (DADDO-DADD13)

This active high output defines the horizontal and vertical
borders of the display. Display control signals which are output on DADD3 through DADD13 are valid on the trailing
edge of BLANK.

The display address is used by the PVTC to address up to
16K of display memory. These outputs are floated at various
times depending on the buffer mode. Various control signals
are multiplexed on DADD3 through DADD13 and are valid at
the trailing edge of BLANK. The following paragraphs
describe these control signals.

CURSOR GATE (CURSOR)
LINE INTERLACE (DADD3/L1) - Replaces DADD4/LAO
as the least significant line address for interlaced sync and
video applications. A low indicates an even row of an even
field or an odd row of an odd field.

This active high output becomes active for a specified
number of scan lines when the address contained in the cursor registers matches the address output on the display address (DADDO through DADD13). The first and last lines of
the cursor and a blink option are programmable.

LINE ADDRESS (DADD4-DADD7/LAO-LA3) - Provides
the number of the current scan line within each character
row.

INTERRUPT REQUEST (lNTR)

This pin is an open-drain output which supplies an active
low interrupt request from any of five maskable sources.
This pin is inactive after power-on reset or a master reset
command.

LINE ZERO (DADDS/LNZ)
scan line in each character row.

Asserted before the first

LIGHT PEN LINE (DADD9/LPL) - Asserted before the
scan line which matches the programmed light pen line position (line three, five, seven, or nine).

LIGHT PEN STROBE (LPS)

This positive edge triggered input indicates a light pen 'hit'
causing the current value of the display address to be
strobed into the light pen register.

UNDERLINE (DADD10/UL) - Asserted before the scan
line which matches the programmed underline position (line
o through 15).

HANDSHAKE CONTROL 1 (CTRL1)
In independent mode, this pin provides an active low write
data buffer (WDB) output which strobes data from the interface latch into the display memory. In transparent and
shared modes, this is an active low processor bus request
(PBREO) input which indicates that the CPU desires to access the display memory. This pin must be tied high when
operating in row-buffer mode.

BLINK FREQUENCY (DADDll/BLlNK) - Provides an
output divided down from the vertical sync rate.
ODD FIELD (DADD12/0DD) - Active high signal which
is asserted before each scan line of the odd field when interlace is specified.

HANDSHAKE CONTROL 2 (CTRL2)

LAST LINE (DADD13/LL) - Asserted before the last scan
line of character row.

In independent mode, this pin provides an active low read
data buffer (RDB) output which strobes data from the
display memory into the interface latch. In transparent and
shared modes, CTRL2 is an active low bus external enable
(BEXT) output which indicates that the PVTC has relinquished control of the display memory (DADDO-DADD13 are
in the high-impedance state) in response to a CPU bus request. BEXT also goes low in response to a "display off and
float DADD" command. In row-buffer mode, CTRL2 is an
active low bus request (BREO) output which halts the CPU
during a line DMA.

FUNCTIONAL DESCRIPTION
The following paragraphs describe the major blocks (databus buffer, interface logic, operation control, timing, display
control, and buffer control) which comprise the PVTC.
DATA-BUS BUFFER
The data-bus buffer provides the interface between the external and internal data buses. It is controlled by the operation control block to allow read and write operations to take
place between the controlling CPU and the PVTC.

HANDSHAKE CONTROL 3 (CTRL3)

In independent mode, this pin provides the active low buffer chip enable (BCE) signal to the display memory. In
transparent and shared modes, CTRL3 provides an active
low bus acknowledge (BACK) output which serves as a
ready signal to the CPU in response to a processor bus request. In row buffer mode, CTRL3 is an active high memory
bus control (MBC) output which configures the system for
the DMA transfer of one row of character codes from system
memory to the row display buffer.

INTERFACE LOGIC
The interface logic contains address decoding and read
and write circuits to permit communications with the microprocessor via the data-bus buffer. The functions performed
by the CPU read and write operations are as shown in
Table 1.

3-55

MC2672

TABLE 1 - PVTC ADDRESSING
A2

0
0
0
0
1
1
1
1

A1
0
0
1
1
0
0
1
1

AO
0
1
0
1
0
1
0
1

...

Read (R=O)
Interrupt Register
Status Register
Screen Start Address Lower Register
Screen Start Address Upper Register
Cursor Address Lower Register
Cursor Address Upper Register
Light Pen Address Lower Register
Light Pen Address Upper Register

Write (W=O)
Initialization Registers*
Command Register
Screen Start Address Lower Register
Screen Start Address Upper Register
Cursor Address Lower Register
Cursor Address Upper Register
Display Pointer Address Lower Register
Display Pointer Address Upper Register

* There are 11 Inttlallzatlon registers which are accessed sequentially via a simple address. The PVTC
maintains an internal pointer to these registers which is incremented after each write at this address
until the last register (lR1O, the split-screen register) is accessed. The pointer then continues to point
to the split-screen register. Upon power-up or a master reset command, the internal pointer is reset to
point to the first register (lRO) of the initialization register group. The internal pointer can also be preset
to any register of the group via the "load m address pointer" command.

I

OPERATION CONTROL
The operation control section decodes configuration and
operation commands from the CPU and generates appropriate signals to other internal sections to control the overall
device operation. It contains the timing and display registers
which configure the display format and operating modes,
the interrupt logic, and the status register which provides
operational feedback to the CPU.

modes utilize a single or multiple page RAM and differ
primarily in the means used to transfer display data between
the RAM and the CPU. The row-buffer mode makes use of a
single row buffer (which can be shift register or a small
RAM) that is updated in real time to contain the appropriate
display data.
The user program bits 0 and 1 of IRO to select the mode
best suited for the system environment. The CNTRL1CNTRL3 outputs perform different functions for each mode
and are named accordingly in the description of each mode
given in the following paragraphs.

TIMING
The timing section contains the cursors and decoding
logic necessary to generate and monitor timing outputs and
to control the display format. These timing parameters are
selected by programming of the initialization registers.

INDEPENDENT MODE
The CPU-to-RAM interface configuration for this mode is
illustrated in Figure 2. Transfer of data between the CPU and
display memory is accomplished via a bidirectional latched
port and is controlled by the signals read data buffer (RDB),
write data buffer (WDB), and buffer chip enable (BCE). This
mode provides a non-contention type of operation that does
not address the memory directly. The read or write operation
is performed at the address contained in the cursor address
register or the pointer address register as specified by the
CPU. The PVTC enacts the data transfers during blanking
intervals in order to prevent visual disturbances of the
displayed data.
The CPU manages the data transfers by supply commands
to the PVTC. The commands used are:

DISPLAY CONTROL
The display control section generates linear addreSSing of
up to 16K bytes of display memory. Internal comparators
limit the portion of the memory which is displayed to programmed values. Additional functions performed in this section include cursor positioning, storage of light pen "hit"
locations, and address comparisons required for generation
of timing signals and the split-screen interrupt.
BUFFER CONTROL
The buffer control section generates three Signals which
control the transfer of data between the CPU and the display
buffer memory. Four system configurations requiring four
different handshaking schemes are supported. These are
described in SYSTEM CONFIGURATIONS.

1. Read/write at pOinter address.
2. Read/write at cursor address (with optional increment of address).
3. Write from cursor address to pointer address.
The operational sequence for a write operation is:
1. CPU checks RDFLG status bit to assure that any
previous operation has been completed.
2. CPU loads data to be written to display memory into
the interface latch.
3. CPU writes address into cursor or pointer registers.
4. CPU issues "write at cursor with/without increment"
or "write at pointer" command.
5. PVTC generates control Signals and outputs specified
address to perform requested operation. Data is
copied from the interface latch into the memory.

SYSTEM CONFIGURATIONS
A typical display terminal using the MC2670, MC2671,
MC2672, and MC2673 CRT terminal devices is shown in
Figure 1. In this system, the CPU examines inputs from the
data communications line and the keyboard and places the
data to be displayed in the display buffer memory. This buffer is typically a RAM which holds the data for a single or
multiple screen load (page) or for a single character row.
The PVTC supports four common system configurations
of display buffer memory, designated the independent,
transparent, shared, and row-buffer modes. The first three

3-56

MC2672

5. PVTC generates control signals and outputs block
addresses to copy data from the interface latch into
the specified block of memory.

6. PVTC sets RDFLG status to indicate that the write is
completed.
Similarly, a read operation proceeds as follows:

6. PVTC sets RDFLG status to indicate that the block
write is completed.

1. Steps 1. and 3. as above
2. CPU issues "read at cursor with/without increment"
or "read at pointer" command.

Similar sequences can be implemented on an interrupt
driven basis using the READY interrupt output to advise the
CPU that a previously requested command has been completed.
Two timing sequences are possible for the "read/write at
cursor/pointer" commands. If the command is given during
the active display window (defined as first scan line of the
first character row to the last scan line of the last character
row), the operation takes place during the next horizontal
blanking interval, as illustrated in Figure 3. If the command is
given during the vertical blanking interval, or while the
display has been commanded blanked, the operation takes
place immediately. In the latter case, the execution time for
the command is approximately one microsecond plus six
character clocks (see Figure 4).
Timing for the "write from cursor-to-pointer" operation is
shown in Figure 5. The BLANK output is asserted automatically and remains asserted until the vertical retrace interval following completion of the command. The memory is
filed at a rate of one location per two character times, plus a
small amount of overhead.

3. PVTC generates control signals and outputs specified
address to perform requested operation. Data is
copied from memory to the interface latch and PVTC
sets RDFLG status to indicate that the read is complete.
4. CPU checks RDFLG status to see if operation is completed.
5. CPU reads data from interface latch.
Loading the same data into a block of display memory is
accomplished via the "write from cursor-to-pointer" command:
1. CPU checks RDFLG status bit to assure that any
previous operation has been completed.
2. CPU loads data to be written to display memory into
the interface latch.
3. CPU writes beginning address of memory block into
cursor address register and ending address of block
into pointer address register.
4. CPU issues "write from cursor-to-pointer" command.

FIGURE 1 -

CRT TERMINAL BLOCK DIAGRAM

MC2673

MC2672

MO~

CPU

Keyboard

3·57

II

MC2672

FIGURE 2 - INDEPENDENT BUFFER-MODE CONFIGURATION

MC2672
PVTC

Refresh
RAM
Display Address

DADD

BCE

CTRl3

CE

WDB

CTRll
CRTl2

ADR

iN

Data I/O

RDB

I

To
Video
logic

iN

System Data Bus

FIGURE 3 -

READ/WRITE AT CURSOR/POINTER COMMAND TIMING DIAGRAM
(Command Received During Active Display Window)

CClK

eE
iN
BLANK

DADD

RDB

WDB

..

'l

BCE

'"

NOTE: Write waveforms shown in dotted lines.

3-58

MC2672

FIGURE 4 -

READ/WRITE AT CURSOR/POINTER COMMAND TIMING DIAGRAM
(Command Received While Display is Blanked)

BLANK

DADD

\----:----1~

------------~~----~~
1

FIGURE 5 - WRITE FROM CURSOR-TO-POINTER COMMAND TIMING

BLANK is Set Until First VBLANK After Last Write

BLANK

DADD

--------------------------~~------------------------

3·59

I

MC2672

cesses. BACK, which can be used as a "hold" input to the
CPU, is then lowered to indicate that the CPU can access the
buffer.
In transparent mode, the PVTC delays the granting of the
buffer to the CPU until a vertical or horizontal blanking interval, thereby causing minimum disturbance of the display. In
shared mode, the PVTC will blank the display and grant immediate access to the CPU. Timing for these modes is illustrated in Figures 7, 8, and 9.

SHARED AND TRANSPARENT BUFFER MODES
In these modes the display buffer RAM is a part of the
CPU memory domain and is addressed directly by the CPU.
Both modes use the same hardware configuration with the
CPU accessing the display buffer via three-state drivers (see
Figure 6). The processor bus request (PBREQ) control signal
informs the PVTC that the CPU is requesting access to the
display buffer. In response to this request, the PVTC raises
bus acknowledge (BACK) until its bus external (B8('i") output has freed the display address and data buses for CPU ac-

FIGURE 6 -

I

PVTe SHARED OR TRANSPARENT BUFFER MODES

MC2672
PVTC

Refresh
RAM
Display Address

CPU

{ PBREO
BACK
BEXT

CTRLl

ADR

EE
W

CTRL3
CTRL2

Select
Decode

Upper
System Address Bus

System Data Bus

3-60

MC2672

FIGURE 7 - TRANSPARENT-BUFFER MODE TIMING

~I

I

____

1~~

~

fS;N~;;-------~---------------

~ ----j-----"------~--------------.

. 1~~""'1-)----\..--______(.se,~~0~e3.:.
. ______J\.r----\

BLANK

~

Horizontal Blanking Interval

\

\ _________ •

DADO
NOTES:

1. PBREO must be asserted prior to the rising edge of BLANK in order for sequence to begin during that blanking period.
2. If PBREO is negated after the next to last CClK of the horizontal blanking interval, the next scan line will also be blanked.

FIGURE 8 -

'--__-+-__-+-__

SHARED-BUFFER MODE TIMING

-I-_J'\,~--J

______ __ I

' - -_ _ _- ' ' \ , - -_ _...,j _ _ _ _ _ _ _

T1~;~;~-----~-------------

r--------~------------

.J

BLANK

DADO
NOTE:

1. If PBREO is negated after the next to last CClK of the horizontal blanking interval, the next scan line will also be blanked.

3-61

I

MC2672

FIGURE 9 -

SHARED AND TRANSPARENT MODE TIMING

(a) During Vertical Blank or after 'display off' command

(b) After 'display off and three-state' command
CClK

t1~

~I

BACK __________~I

I

- - - - - -......
VBlANK
or DBlANK

I

DADD

----------------------~~---------­

-----------\------------

PBREO ______________ ~---------------.

BACK

~

BEXT

\
\

BLANK

DADD

__---",'--_..J\._~
. . Refresh Addresses ...

Sys Add.

ROW-BUFFER MODE

ROW-BUFFER MODE CONFIGURATION
2x 2111
Row
Refresh
RAM

MC2672
PVTC
BREO
To CPU

Continuous Bus Control

programmed number of scan lines. The bus-request control
(BREO) signal informs the CPU that character addresses and
the memory bus control (MBC) signal will start at the next
falling edge of BLANK. The CPU must release the address
and data buses before this time to prevent bus contention.
After the row of character data is transferred to the CPU,
BREO returns high to grant memory control back to the
CPU.

Figures 10 and 11 show the timing and a typical hardware
implementation for the row-buffer mode. During the first
scan line (line 0) of each character row, the PVTC halts the
CPU and DMA's the next row of character data from the
system memory to row-buffer memory. The PVTC then
releases the CPU and displays the row-buffer data for the

FIGURE 10 -

System Processor has

...... Refresh ..
Addresses

~----.....- - - - - - . . . I

OD

CTRl2

w
CTRl3

System Address Bus

vv-----'
System Data Bus

MC2672

FIGURE 11 -

CClK

BLANK

--r

ROW-BUFFER MODE TIMING

i ~1~__

(l_ine_o_o_nl_Y)_.....I\r--_ _- - J

BREQ - - - - , \

to

~~

1.-----

~

~_----il

MBC __________~~

\~_________

OPERATION

the data on the CRT. The user effects changes to the display
by modifying the contents of the display memory, the PVTC
display control and command registers, and the initialization
registers, if required. Interrupts and status conditions
generated by the PVTC supply the "handshaking" information necessary for the CPU to effect the display changes in
the proper time frame.

After power is applied, the PVTC will be in an inactive
state. Two consecutive "master reset" commands are
necessary to release this circuitry and ready the PVTC for
operation. Two register groups exist within the PVTC: the
initialization registers and the display control registers. The
initialization registers select the system configuration,
monitor timing, cursor shape, display memory domain, and
screen format. These are loaded first and normally require no
modification except for certain special visual effects. The
display control registers specify the memory address of the
base character (upper left corner of screen), the cursor position, and the pointer address for independent memory
access mode. These usually require modification during
operation.
After initial loading of the two register groups, the PVTC is
ready to control the monitor screen. Prior to executing the
PVTC commands which turn on the display and cursor, the
user should load the display memory with the first data to be
displayed. During operation, the PVTC will sequentially address the display memory within the limits programmed into
its registers. The memory outputs character codes to the
system character and graphics generation logic, where they
are converted to the serial video stream necessary to display

FIGURE 12 -

IRO

II

INITIALIZATION REGISTERS
There are 11 initialization registers (I RQ-IR 10) which are accessed sequentially via a single address. The PVTC maintains
an internal pointer to these registers which is incremented
after each write at this address until the last register (IRlO,
the split-screen register) is accessed. The pointer then continues to point to the split-screen register. Upon power-up or
a master reset command, the internal pointer is reset to point
to the first register (IRQ) of the initialization register group.
The internal pointer can also be preset to any register of the
group via the "load IR address pointer" command. These
registers are write only and are used to specify parameters
such as the system configuration, display format, cursor
shape, and monitor timing. Register formats are shown in
Figure 12 and described in the following paragraphs.

INITIALIZATION REGISTER FORMATS (Page 1 of 3)

Scan Lines Per Character Row
Not Used

Non-I nterlaced

Interlaced

Sync Select

0000= 1 line
0001 = 2 lines
0010=3 lines

0000= Undefined
0001 = 5 lines
0010= 7 lines

0= VSYNC
1 = CSYNC

1110= 15 lines
1111 = 16 lines

1110=31 Lines
1111 = Undefined

..

..

3·63

Buffer-Mode Select
00 = Independent
01 = Transparent
10= Shared
11=Row

I

MC2672

FIGURE 12 - INITIALIZATION REGISTER FORMATS (Page 2 of 3)

4
IRl

Interlace
Enable

Equalizing Constant

0= Non0000000= 1 CClK
Interlace 0000001 = 2 CClK
1 = Interlace

··
·

Calculated from:
EC=0.5 (HACT+ HFP+ HSYNC+ HBP) - 2(HSYNC)

1111110=127 CClK
1111111 = 128 CClK

4
IR2

Not Used

3

Horizontal Sync Width

I

Horizontal Back Porch

0000= 2 CClK
0001 =4 CClK

000= 1 CClK
001 =5 CClK

1110=30 CClK
1111 =32 CClK

110=25 CClK
111 =29 CClK

..

6
IR3

..

--

o

4

Vertical Front Porch

Vertical Back Porch

000=4 Scan lines
001 = 8 Scan Lines

00000=4 Scan Lines
00001 = 6 Scan Lines

110= 28 Scan lines
111 = 32 Scan Lines

11110= 64 Scan Lines
11111 =66 Scan Lines

..
6

IR4

Character
Blink Rate

..

o

4
Active Character Rows Per Screen*

00000oo = 1 Row
0000001 = 2 Rows

0=1/16
VSYNC
1 = 1/32
VSYNC

···

1111110= 127 Rows
1111111 = 128 Rows
* In interlace mode with odd total character rows per screen the last character row will be the programmed scan lines per
character row minus one.

4
IR5

Active Characters Per Row
00000010= 2 Characters
00000011 = 4 Characters

11111110= 255 Characters
11111111 = 256 Characters

3·64

MC2672

FIGURE 12 -

INITIALIZATION REGISTER FORMATS (Page 3 of 3)

o
IR6

First Line of Cursor

Last Line of Cursor

0000= Scan Line 0
0001 = Scan Line 1

0000= Scan Line 0
0001 = Scan Line 1

1110 = Scan Line 14
1111=Scan Line 15

1110=Scan Line 14
1111 = Scan Line 15

..

··

°

4
IR7
Cursor
Blink

Double
Height
Char.

Underline Position

0= No
1 = Yes

0= No
1 = Yes

0000= Scan Line 0
0001 = Scan Line 1

Light Pen Line
00=
01 =
lOt
11 t

Scan
Scan
Scan
Scan

Line
Line
Line
Line

3
5
7
9

I

··

1110= Scan Line 14
1111=Scan Line 15

°

4
IR8

Display Buffer First Address LS Bs

H"OOO" =0
H"001" = 1
NOTE

MSBs are in IR9[301

H"FFE"=4,094
H"FFF"=4,095

IR9

Display Buffer Last Address

Display Buffer First Address MSBs

0000= 1,023
0001 =2,047

..

See IR8

1110= 15,359
1111=16,383

IR10

Cursor
Blink
Rate
0= 1/16
VSYNC
1 = 1/32
VSYNC

Split-Screen Interrupt Row
0000000= Row 0
0000001 = Row 1

..

1111110= Row 126
1111111 = Row 127

3-65

MC2672

SCAN LINES PER CHARACTER ROW (IRO[6:3]1 - Both
interlaced and non-interlaced scanning are supported by the
PVTC. For interlaced mode, two different formats can be implemented, depending on the interconnection between the
PVTC and the character generator (see IR1[7]). This field
defines the number of scan lines used to compose a character row for each technique. As scanning occurs, the scan
line count is output on the LAO-LA3 and LI pins.

non-interlaced timing operation. Two modes of interlaced
operation are available, depending on whether LO-L3 or LI,
LO-L2 are used as the line address for the character
generator. The resulting displays are shown in Figure 13.
For "interlaced sync" operation, the same information is
displayed in both odd and even fields, resulting in enhanced
readability. The PVTC outputs successive line numbers in
ascending order on the LAO-LA3 lines, one per scan line for
each field.
The "interlaced sync and video" format doubles the
character density on the screen. The PVTC outputs successive line numbers in ascending order on the LI, LAO-LA2
lines, one per scan line for each field, but alternates beginning the count with even and odd line numbers. This
displays the odd field with even scan lines in even character
rows and odd scan lines in odd character rows, and the even
field with odd scan lines in even character rows and even
scan lines on odd character rows. This provides balanced
beam currents in the odd and even fields, thus minimizing
character variations due to different loading of the CRT
anode supply between fields.

VS/CS ENABLE (lRO[2]) - This bit selects either vertical
sync pulses or composite sync pulses on the VSYNC/
CSYNC output (pin 181. The composite sync waveform conforms to EIA RS170 standards, with the vertical interval composed of six equalizing pulses, six vertical sync pulses, and
six more equalizing pulses.

I

BUFFER MODE SELECT (lRO[1 :0]) - Four buffer memory
modes may be selectively enabled to accommodate the
desired system configuration. See SYSTEM CONFIGURATION.
INTERLACE ENABLE (lR1[7]) -

Specifies interlaced or

FIGURE 13 -

INTERLACED DISPLAY MODES

.- ~~=:l1
l
. - L1 ---.

----------T.----- . - L2 ---.

t

Line Address
To Char. Gen.

Line Address
To Char. Gen.

L3

Line Address
To Char. Gen.

~

"0

6

.-

Jj
C

"0

o

1 -.-.-.-.-.--

3 - . ---------4 -.-.-.-------

5 - .--------6 -.-------

7 -.-.-.-.-.-0-------1 --.-.-.-.-.---

2 --. - - - - - - - 3 -- . - - - - - - 4 --.-.-.-------

5-·------6-·------7 --.-.-.-.-.--

-.-.-.-.-.-0------------1 -0-0-0-0-0--

2 -.------9 Scan
Lines/
Row

~ ~

7 8-----------

o ------------

2 -

17 Scan
Lines/
Row

.---------

2-0------3 -.------3-0------4 .--0
.-0
-----4.-0
--

5 -.-------5-0-----

--.-----------6-0-------

--.-.-.-.-.---.-.-.-.-.--.---------7

-0-0-0-0-0---

o -1-------0-0-0-0-0--2-0----------

3-0---------3 -4
.----------0-0-0----

4 .-.-.----5-0---------5 -.----------6·0
6 -.--------7 -0-0-0-0-0-7 --.-.-.-.-.---

8-------

!
0

9Scan
Llnes/
Row

1-00000----

2 3-~-4 - ••• - - - - - - 5 -0 - - - - - - -

6-·------7 -00 0 0 0 - - - - - 80
-----------1 - ••••• -----2 -0 - - - - - - - - -

34--·0-0-0-------

56-~--------••••• - - - - 8--------

7 -

0----------1-00000----2-·------3 -0 - - - - - - - -

4 -

•••- - - - -

5-0-------

67--0·0-0-0-0-- --8

_ _ _ _ _ __
0
1 - ••••• -----

2-0-------

3-·------4 -0 0 0 - - - - - - - 5-·------6-0------

7 -

••••• - - - -

8------0------Non-Interlaced
IRO= 1000; Total Lines/Row=9

Interlaced Sync
IRO=01111; Total Lines/Row= 17

3-66

Interlaced Sync and Video
IRO=0011; Total Lines/Row=9

MC2672

VERTICAL BACK PORCH (lR3[4:0]1 - This field determines the number of scan line periods between the falling
edges of the VSYNC and BLANK outputs.

EQUALIZING CONSTANT (lR1[6:0]) - This field indirectly defines the horizontal front porch and is used internally to
generate the equalizing pulses for the RS170 compatible
CSYNC. The value for this field is the total number of character clocks (CClK) during a horizontal line period divided by
two, minus two times the number of character clocks in the
horizontal sync pulse:
EC

HACT+ HFP+ HSYNC+ HBP
2

CHARACTER BLINK RATE (lR4[7]) - Specifies the frequency for the character blink attribute timing. The blink rate
can be specified as 1/16 or 1/32 of the vertical field rate. The
timing signal has a duty cycle of 75% and is multiplexed onto
the DADD11/BLINK output at the falling edge of each
BLANK.

2(HSYNC)

The definition of the individual parameters is illustrated in
Figure 14. The minimum value of HFP is two character
clocks.
Note that when using the MC2673 video attributes controller (VAC), the blank pulse is delayed three CClKs relative
to the HSYNC pulse.

CHARACTER ROWS PER SCREEN (lR4[6:0]) - This field
defines the number of character rows to be displayed. This
value multiplied by the scan lines per character row, plus the
vertical front and back porch values, and the vertical sync
pulse width (three scan lines) is the vertical scan period in
scan lines.

HORIZONTAL SYNC PULSE WIDTH (IR2[6:3]) - This
field specifies the width of the HSYNC pulse in CClK
periods.

ACTIVE CHARACTERS PER ROW (lR5[7:0]) - This field
determines the number of characters to be displayed on each
row of the CRT screen. The sum of this value, the horizontal
front porch, the horizontal sync width, and the horizontal
back porch is the horizontal scan period is CClKs.

HORIZONTAL BACK PORCH (lR2[2:0]) - This field
defines the number of CClKs between the trailing edge of
HSYNC and the trailing edge of BLANK.

FIRST AND lAST SCAN LINE OF CURSOR (IR6[7:4]
AND IR6[3:0]) - These two fields specify the height and
position of the cursor on the character block. The "first" line
is the topmost line when scanning from the top to the bottom of the screen.

VERTICAL FRONT PORCH (lR3[7:5]) - Programs the
number of scan line periods between the rising edges of
BLANK and VSYNC during a vertical retrace interval. The
width of the VSYNC pulse is fixed at three scan lines.

FIGURE 14 -

HORIZONTAL AND VERTICAL TIMING

4:---- Char/Row
- - - - - - - "..
~I
(IR5)

1--

HBLANK~~----~I____________________~I----~~

~

1'+ Front Porch (IR1)

Back Porch (lR2)~

HSYNC~~______________________~r--l~

~HSYNC(lR2)
~Char Rows/Screen (IR4)~
-., ~ Scan Lines Per Row (IRQ)

-+j

I

VB LANK

j.-

_____

-------.L

----1.-----~11i~

f4:- Front Porch (IR3)

~

nL._____

I -VSYNC (Fixed at3)

Equalizing
Constant

Lines/Row
~

IRa

I I I I I I I I
HSYNC
Width

IR1

HBACK
Porch

VBACK
Porch

~

I I I I I I II

IR3

I I I I I I I I I
Characters Per Row

Char. Rows/Screen
IR4

I I I I I I I I I
VFRONT
Porch

~

IR2

~

Back Porch (IR3)·-.j

VSYNC ~

I I I I I I I I

IR5

3-67

I I I I I I

I I I

I

MC2672

If "last address" is the end of a character row and a new
screen start address has been loaded into the screen start
register, or if "last address" is the last character position of
the screen, the next data is obtained from the address contained in the screen start register.
Note that there is no restriction in displaying data from
other areas of the addressable memory. Normally, the area
between these two bounds is used for data which can be
overwritten (e.g., as a result of scrolling), while data that is
not to be overwritten would be contained outside these
bounds and accessed by means of the split-screen interrupt
feature of the PVTC.

LIGHT PEN LINE POSITION (lR7[7:6]) - This field
defines which of four scan lines of the character row will be
used for the light pen strike - through attribute by the
MC2673 VAC. The timing signal is multiplexed onto the
DADD9/LPL output during the falling edge of BLANK.
CURSOR BLINK ENABLE (lR7[5]) - This bit controls
whether or not the cursor output pin will be blinked at the
selected rate (lRl0[7]). The blink duty cycle for the cursor is
50%.

I

DOUBLE HEIGHT CHARACTER ROW ENABLE (lR7[4])
- If enabled, the number of each scan line will be repeated
twice in succession, causing the height of the character row
to double. This bit can be changed at any time but will only
become effective at the beginning of the character row following the time it is changed. This allows selected character
rows to be of double height. The split-screen interrupt can
be used to notify the CPU when the effectuate changes to
this bit. For each double height row which replaces a normal
row, one row count should be subtracted from the "character rows per screen" field (IR4) to maintain the same total
number of scan lines per field.

CURSOR BLINK RATE (lRl0[7]) - The cursor blink rate
can be specified at 1/16 or 1/32 of the vertical scan frequency. Blink is effective only if blink is enabled by IR7[5J.
SPLIT-SCREEN INTERRUPT (lR10[6:0]) - The splitscreen interrupt can be used to provide special screen effects
such as a row of double height characters or to change the
normal addressing sequence of the display memory. The
contents of this field is comparel~, in real time, to the current
character row number. Upon a match, the PVTC sets the
split-screen status bit, and issues an interrupt request if so
programmed. The status change/interrupt request is made
at the beginning of scan line zero of the split-screen character row.

UNDERLINE POSITION (lR7(3:0]) - This field defines
which scan line of the character row will be used for the
underline attribute by the MC2673 VAC. The timing signal is
multiplexed onto the DADD10/UL output during the falling
edge of BLANK.

TIMING CONSIDERATIONS
Normally, the contents of the initialization registers are not
changed during operation. However, this may be necessary
to implement special display features such as multiple cursors, smooth scrolling, horizontal scrolling, and double
height character rows. Table 2 describes the timing details
for these registers which should be considered when implementing these features.

DISPLAY BUFFER FIRST ADDRESS (lR9[3:0] AND
IR8[7:0]1 AND DISPLAY BUFFER LAST ADDRESS
(lR9[7:4]) - These two fields define the area within the buffer memory where the display data will reside. When the data
at the "display buffer last address" is displayed, the PVTC
will wrap-around and obtain the data to be displayed at the
next screen position from the" display buffer first address".

TABLE 2 - TIMING CONSIDERATIONS

Parameter

Timing Considerations

Field Line of Cursor
Last Line of Cursor
Light Pen Line
Underline

These parameters must be established at a minimum of two characters times
prior to their occurrence.

Double Height Characters

Set/reset during the character row prior to the row which is to be/not to be
double height.

Cursor Blink
Cursor Blink Rate
Character Blink Rate

New values become effective within one field after values are changed.

Split-Screen Interrupt Row

Change anytime prior to line zero of desired row.

Character Rows Per Screen

Change only during vertical blanking period.

Vertical Front Porch

Change prior to first line of VFP.

Vertical Back Porch

Change prior to fourth line after VSYNC.

Screen-Start Register

Change prior to the horizontal blanking interval of the last line of character
row before row where new value is to be used.

3·68

MC2672

DISPLAY CONTROL REGISTERS

ing registers in the group store address values which specify
the cursor and buffer pointer locations, the location of the
first character to be displayed on the screen, and the location
of a light pen "hit". With the exception of the light pen
register, the user initializes these registers after powering on
the system and changes their values to control the data
which is displayed.

There are nine registers in this group, each with an individual address. Their formats are illustrated in Figure 15.
The command register is used to invoke one of 16 possible
PVTC commands as described in COMMANDS. The remain-

FIGURE 15 -

DISPLAY CONTROL REGISTER FORMATS

(a) Command Register (Write Only)

o

4
Command Code

I

Refer to COMMANDS for Command Codes

(b) Screen Start Registers (Read and Write).
Cursor Address Registers (Read and Write),
Pointer Address Register (Write Only), and
Light Pen Address Register (Read Only)

o
Upper Register

MSBs

Not Used

o
Lower Register ILSBs)

H"OOOO" =0
H"OOOl" = 1
NOTE: MSBs are in Upper Register [5:0J
H"3FFE" = 16,382
H"3FFF" = 16,383

the programmed number of rows per screen. Thus, the data
in the display memory is displayed sequentially starting from
the address contained in the screen start register. After the
ensuing vertical retrace interval, the entire process repeats
again.
The sequential operation described above will be modified
upon the occurrence of either of two events. First, if during
the incrementing of the memory address counter the
"display buffer last address" (IR9[7:4J) is reached, the MAC
will be loaded from the "display buffer first address" register
(IR9[3:0J), (IR8[7:0J) at the next character clock. Sequential
operation will then resume starting form this address. This
wraparound operation allows portions of the display buffer
to be used for purposes other than storage of displayable
data and is completely automatic without any CPU intervention (see Figure 16a).

SCREEN-START REGISTERS

The screen-start registers contain the address of the first
character of the first row (upper left corner of the active
display). At the beginning of the first scan line of the first
row, this address is transferred to the row-start register
(RSR) and into the memory-address counter (MAC). The
counter is then advanced sequentially at the character rate
the number of times programmed into the active charactersper-row register (I R5) thus reaching the address of the last
character of the row plus one. At the beginning of each subsequent scan line of the first row, the MAC is reloaded from
the RSR and the above sequence is repeated. At the end of
the last scan line of the first row, the contents of the MAC is
loaded into the RSR to serve as the starting memory address
for the second character row. This process is repeated for

3·69

MC2672

FIGURE 16 -

DISPLAY ADDRESSING OPERATION

or---------.

Bottom of Screen...

rrmf~rrrmff~f

..

Display Buffer Start

Screen Start+ ........~.,....,........................,....,.....~
Monitor
Display

I

16KL-----------~

Memory

(a) Display Memory Wraparound

..............,........:...l...::...:....l...i........:..lj .-Display

Buffer End

II
Monitor
Display

16KL------.....
Memory

(b) Display Memory Split Screen With Wraparound

The sequential row-to-row addressing can also be
modified under CPU control. If the contents of the screenstart register (upper, lower, or both) are changed during any
character row (say row "n"), the starting address of the next
character row (row "n+ 1") will be the next value of the
screen-start register and addressing will continue sequentially from there. This allows features such as split-screen
operation, partial scroll, or status line display to be implemented. The split-screen interrupt feature of the PVTC is
useful in controlling this type of operation. Note that in order
to obtain the correct screen display, the screen-start register
must be reloaded with the original value prior to the end of
the vertical retrace. See Figure 16b.
During vertical blanking the address counter operation is
modified by stopping the automatic load of the contents of
the RSR into the counter, thereby allowing the address outputs to free-run. This allows dynamic memory refresh to occur during the vertical retrace interval. The refresh addressing starts at the last address displayed on the screen and increments by one for each character clock during the retrace
interval. If the display buffer last address is encountered
refreshing continues from the display buffer first address.

CURSOR ADDRESS REGISTERS
The contents of these registers define the buffer memory
address of the cursor. If enabled, the cursor output will be
asserted when the memory address counter matches the
value of the cursor address registers. The cursor address
registers may be read or written by the CPU or incremented
via the "increment cursor address" command. In independent buffer mode, these registers define a buffer memory address for PVTC controlled access in response to "read/write
at cursor with/without increment" commands, or the first
address to be used in executing the "write for cursor to
pointer" command.
DISPLAY POINTER ADDRESS REGISTERS
These registers define a buffer memory address for PVTC
controlled accesses in response to "read/write at pointer"
commands. They also define the last buffer memory address
to be written for the "write from cursor to pointer" command.
LIGHT PEN ADDRESS REGISTERS
If the light pen input is enabled, these registers are used to

3-70

MC2672

VB LANK (I/SR[4]) - Indicates the beginning of a vertical
blanking interval, is set to a one at the beginning of the first
scan line of the vertical front porch.

store the current character address upon receipt of a light
pen strobe input. Several sources of delay between the
display of a character upon the screen and the receipt of a
light pen hit can be expected to exist in a system environment. These delays include address pipelining in the character generation circuits, delays in the video generation circuits, and delays in the light detection circuitry itself. These
delays cause the value stored in the light pen register to differ from the actual address of the character at which the light
pen hit actually was detected. Software must be used to correct this condition.

LINE ZERO (I/SR[3]) - Is set to a one at the beginning of
the first scan line (line zero) of each active character row.
SPLIT SCREEN (IISR[2]) - This bit is set when a match
occurs between the current character row number and the
value contained in the split-screen interrupt register,
IR10[6:0J. The equality condition is only checked at the
beginning of line zero of each character row. This bit is reset
when either of the screen-start registers is loaded by the
CPU.

INTERRUPT/STATUS REGISTERS
The interrupt and status registers provide information to
the CPU to allow it to interface with the PVTC to effect
desired changes to implement various display operations.
The interrupt register provides information on five possible
interrupting conditions, as shown in Figure 17. These conditions may be selectively enabled or disabled (masked) from
causing interrupts by certain PVTC commands. An interrupt
condition which is enabled (mask bit equal to one) will cause
the INTR output to be asserted and will cause the corresponding bit in the interrupt register to be set upon occurrence of interrupt condition. An interrupt condition which is
disabled (mask bit equal to zero) has no effect on either the
INTR output or the interrupt register.
The status register provides six bits of status information;
the five possible interrupting conditions plus the NOT BUSY
bit. For this register, however, the contents are not effected
by the state of the mask bits.
Descriptions of each interrupti status register bit follows.
Unless otherwise indicated, a bit, once set, will remain set
until reset by the CPU by issuing a "reset interrupt/status
bits" command. The bits are also reset by a "master reset"
command and upon power-up.
RDFLG (SR[5]) - This bit is present in the status register
only. A zero indicates that the PVTC is currently executing
the previously issued command. A one indicates that the
PVTC is ready to accept a new command.
FIGURE 17 -

READY (I/SR[1]) - Certain PVTC commands affect the
display and may require the PVTC to wait for a blanking
interval before enacting the command. This bit is set to one
when execution of the command has been completed. No
command should be invoked until the prior command is
completed.
LIGHT PEN (I/SR[O]) - A one indicates that a light pen
hit has occurred and that the contents of the light pen
register have been updated. This bit will be reset when either
of the light pen registers is read.

COMMANDS
The PVTC commands are divided into two classes: the instantaneous commands, which are executed immediately
after they are invoked, and the delayed commands which
may need to wait for a blanking interval prior to their execution. Command formats are shown in Table 3. The commands are asserted by performing a write operation to the
command register with the appropriate bit pattern as the
data byte.

INTERRUPT AND STATUS REGISTER FORMAT

o
Not Used
Always Read
as Zero

RDFLG

VBLANK

Line
Zero

0= Busy
1 = Ready

0= No
1 =Yes

O=No
1 =Yes

3-71

Split
Screen

Ready

Light
Pen

O=No
1 =Yes

0= Busy
1 = Ready

0= No
1 = Yes

I

MC2672

TABLE 3 D7

D6

D5

D4

D3

D2

D1

DO

PVTC COMMAND FORMATS

Hex

Command

Instantaneous Commands

0

a

a

a
a
a

0
0
0
1
0

I

0

0
0
0
0

0
0

0

1
0
1

0
0
1
1
1
1
1
1

a
a
1

0
1
d
d
d
d
1
1
N
N
N

0
V
d
d
1
1
d
d
N
N
N

0
V
d
d
N
N
d
d
N
N
N

0
V
1
1
d
d
d
d .
N
N
N

V

L

B

Z

S
S

0

L
P

0
0
0
0
0
0

a

1

0
1
0

0
0
1

a

a

1
0
1
1

0
1
1
1

R

~

0
V
0*
1*
0*
1*
0*
1*
N
N
N

Master Reset
Load IR Pointer with Value V (V = 0 to 10)
Disable Light Pen
Enable Light Pen
Display Off - Float DADO Bus If N = 1
Display On - Next Field (N= 1) or Scan Line (N=O)
Cursor Off
Cursor On
ResetlotSlrrupt/Status - Bit Reset where N= 1
Disable Interrupt.:... Disable where N = 1
Enable Interrupt - Enables Interrupts and Resets the Corresponding
Interrupti Status Bits where N = 1

Delayed Commands
1
1
1
1
1
1
1
1

0
0
0

a
a
a
a
0

1
1
1
1
1
1
1

a

1

1

0
1
1
1
1
1
1

a
0
1
0
1

a
0

A4
A2
A9
AC
AA
AD
AS

BB

Reset at Pointer Address
Write at Pointer Address
Increment Cursor Address
Read at Cursor Address
Write at Cursor Address
Read at Cursor Address and Increment Address
Write at Cursor Address and Increment Address
Write from Cursor Address to Pointer Address

* Any combination of these three commands is valid.
d = Don't Care

INSTANTANEOUS COMMANDS

ENABLE LIGHT PEN

The instantaneous commands are executed immediately
after the trailing edge of the write pulse during which the
command is issued. These commands do not affect the state
of the RDFLG or READY interrupt/status bits. However, a
command should not be invoked if the RDFLG bit is low.

After invoking this command, receipt of a light pen strobe
input will cause the light pen register to be loaded with the
current buffer memory address and the corresponding interrupt and status flag to be set. Once loaded, further loads are
inhibited until either one of the light pen registers are read or
a reset function is performed.

MASTER RESET
DISABLE LIGHT PEN

This command initializes the PVTC and may be invoked at
any time to return the PVTC to its initial state. Upon powerup, two successive master reset commands must be applied
to release the PVTe's internal power on circuits. In transparent and shared buffer modes, the CNTR L1 input must be
high when the command is issued. The command causes the
following:

Light pen hits will not be recognized.
DISPLAY OFF

Asserts the BLANK output. The DADDO through DADD13
display address bus outputs may be optionally placed in the
high-impedance state by setting bit 2 to a one when invoking
the command.

1. VSYNC and HSYNC are driven low for the duration of
reset and BLANK goes high. BLANK remains high until
a "display on" command is received.
2. The interrupt and status bits and masks are set to zero,
except for the RDFLG flag which is set to a one.
3. The transparent mode, cursor off, display off, and light
pen disable states are set.

DISPLAY ON

Restores normal blanking operation either at the beginning
of the next field (bit 2 = 1) or at the beginning of the next
scan line (bit 2=0). Also returns the DADDO-DADD13
drivers to their active state.

4. The initialization register pointer is set to address I RO.

CURSOR OFF

Disables cursor operation. Cursor output is placed in the
low state.

LOAD IR ADDRESS

This command is used to preset the initialization register
pointer with the value "V" defined by D3-DO. Allowable
values are 0 to 10.

CURSOR ON

Enables normal cursor operation.

3·72

MC2672

RESET INTERRUPT/STATUS BITS

ENABLE INTERRUPTS

This command resets the designated bits in the interrupt
and status registers. The bit positions correspond to the bit
positions in the registers:

Resets the selected interrupt and status register bits and
writes the associated interrupt mask bits to a one. This
enables the corresponding conditions to assert the INTR output. Bit position correspondence is as above.

Bit
Bit
Bit
Bit
Bit

0
1
2
3
4

DELAYED COMMANDS
This group of commands is utilized for the independent
buffer mode of operation, although the "increment cursor"
command can also be used in other modes. With the exception of the "write from cursor to pointer" and "increment
cursor" commands, all the commands of this type will be
executed immediately or will be delayed depending on when
the command is invoked. If invoked during the active screen
time, the command is executed at the next horizontal blanking blanking interval. If invoked during a vertical retrace interval or a "display off" state, the command is executed immediately.

- Light Pen
- Ready
- Split Screen
- Line Zero
- Vertical Blank

DISABLE INTERRUPTS
Sets the interrupt mask to zeros for the designated conditions, thus disabling these conditions from asserting the
INTR output. Bit position correspondence is as above.

3-73

I

®

MOTOROLA

MC2673

Advance Information
HMOS
(HIGH-DENSITY N-CHANNEL, SILICON-GATE)

VIDEO ATTRIBUTES CONTROLLER (VAC)

I

VIDEO ATTRIBUTES
CONTROLLER (VAC)

The MC2673A and MC2673B video attributes controllers (VAC) are
bipolar LSI devices designed for CRT terminals and display systems that
employ raster scan techniques. Each contains a high-speed video shift
register, field and character attributes logic, attribute latch, cursor format logic, and half-dot shift control.
The VAC provides control of visual attributes on a field or character
by character. Internal logic preserves field attribute data from character
row to character row so that an attribute byte is not required at the
beginning of each row. The MC2673B provides for reverse video, blank
(non-display), blink, underline, and highlight attributes and a graphics
mode attribute to work in conjunction with the MC2670 display
character and graphics generator (DCGGl. The MC2673A substitutes a
light pen (strike-thru) attribute for the graphics attribute.
The horizontal dot frequency is the basic timing input to the VAC.
Internally, this clock is divided down to provide a character clock output
for system asynchronization. Up to ten bits of video dot data are parallel
loaded into the video shift register on each character boundary. The
video data is shifted out on three outputs at the dot frequency. On the
VIDEO output, the data is presented as a three-level Signal representing
low, medium, and high intensities. The three intensities are also en. coded ontwoTTCcompatlt.>le video outputs. Light or dark screen background can be selected.
VSS

•
•
•
•

25 MHz Video Dot Rate
Three-Level Current Driven (75 Ohms) Video Output
Three-Level Encoded TTL Video Outputs
Character/Field Attribute Logic:
Reverse Video
Character Blank
Character Blink
Underline
Highlight
Light Pen Strike- Thru or Graphics Control
• Field Attributes Extend from Row to Row

•
•
•
•
•
•
•

PIN ASSIGNMENT

D2

D4

Dl

D5

DO

D6

CCLK

D7

ceo

D8

CCl

D9

CC2

RESET

Light or Dark Field
Cursor Reverse Video Logic
Up to Ten Dots Per Character
CompOSite Blanking for Light Field Retrace
Optional Field Graphics Control Output
High-Speed Bipolar DeSign
4O-Pin Dual-in-Line Package

CBLANK

ACD

TTLVIDl

AMODE

TTLVID2

CURSOR
BLANK

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3·74

DCLK

BKGND

AFLG

• TT L Compatible
• Compatible with the MC2672 PVTC and MC2670 DCGG
• Applications Include:
- CRT Terminals
- Word Processing Systems
- Small Business Computers

VCC

D3

UL
BLINK
LL
LPLlGMD
GND

VIDEO
HDOT
ABLANK
ABLINK
AUL
AHILT
ARVID
ALTPEN/
AGM

MC2673

ORDERING INFORMATION
(VCC=5 V±5%, TA=Oc to 70 C C)

Package Type
Ceramic
L Suffix
Plastic
P Suffix

light-Pen Attribute
Graphics Attribute
Frequency Order Number Frequency Order Number
18
25
18
25

MHz
MHz
MHz
MHz

MC2673A8L
MC2673A5L
MC2673A8P
MC2673A5P

18
25
18
25

MHz
MHz
MHz
MHz

MC2673B8L
MC2673B5L
MC2673B8P
MC2673B5P

VIDEO ATTRIBUTES CONTROLLER BLOCK DIAGRAM

CCO
CC1

CCLK

CC2
DCLK

Dot
Data

DO-D9

VIDEO

Video
and
Attribute
Hierarchy
Logic

HDOT

CURSOR
ARVID -----l~

TTLVID1
TTLVID2

BKGND

ABLANK

CBLANK

ABLINK - - -.....
AHILT
AUL
o,ALTPEN/AGM
AFLG
AMODE
ACD
BLINK - - - + I

Attribute and
Cursor Control
Logic and
Pipeline

..
.

...

UL

LL - - -.....
LPLlGMD

3·75

BLANK
RESET
VCC
VSS
GND

I

MC2673

ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.5 to +6.0

V

Input Voltage

Vin

-0.5 to +6.0

V

Operating Temperature Range

TA

o to 70

°c

Tstg

-65 to + 150

°c

Rating

Storage Temperature Range

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum-rated voltages to
this high-impedance circuit. For proper
operation it is recommended that Yin and
V out be constrained to the range
VSSs(Vin or Vout)sVCc. Reliability of
operation is enhanced if unused inputs
are tied to an appropriate logic voltage
level (e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic Package
Ceramic Package

I

Symbol

Value

Rating

(JJA

50
50

°C/W

" ·POWER CQNSIDERATIONS
The average chip-junction temperature, TJ, in °C can be obtained from:
T J= T A+ (PD e 9JA)
Where:
TA ""Ambient Temperature, °c
9JA"" Package Thermal Resistant, Junction-to-Ambient, °C/W
PD"" PINT+ PpORT
PINT""ICCxVCC, Watts - Chip Internal Power
PPORT"" Port Power Dissipation, Watts - User Determined
For most applications PPORT4i PPINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and TJ (if PPORT is neglected) is:
PD = K -;- (T J + 273°C)
(2)
Solving equations 1 and 2 for K gives:
2
e
e
K=PD (TA+273°C)+9JA PD
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA

DC ELECTRICAL CHARACTERISTICS ITA=O°C to 70°C, VCC=5.0 V +5%,
see Figure
-

1)

Symbol

Milll

Typ

Max

Unit

Input Low Voltage

VIL

-

-

O.S

V

Input High Voltage

VIH

2.0

-

V

Output Low Voltage (Except VIDEO) IOL = 4 mA

VOL

-

-

Output High Voltage (Except VI DEO) IOH = - 400 p.A

VOH

2.4

-

Parameter

0.4

V

-

V

VIDEO Black Level RL = 150 Ohms to GND

VB

-

0

-

V

VIDEO Gray Level RL = 150 Ohms to GND

VG

-

0.45

-

V

VIDEO White Level RL = 150 Ohms to GND

Vw

-

0.90

-

V

Input Low Current Vin=O.4 V

IlL

-

-

-400/
-SOO*

p.A

Input High Current Vin=2.4 V

IIH

-

-

20/
40*

p.A

Power Supply Current Vin=O V, VCC= Max, VSS= Max

ICC

-

-

SO

mA

Bias Supply Current Vin=O V, VCC= Max, VSS= Max

ISS

-

-

120

mA

* For DCLK Input

3-76

MC2673

FIGURE 1 - TEST DIAGRAM
VCC

37.4 ohms,
1%, 'h W

VAC

0.11'F

AC ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, VCC=5 V +5%,
see Figure 1)
18 MHz

25 MHz
Parameter

Symbol

Dot Clock Frequency (see Figure 2)

fD

Min
-

Max

Min

Max

Unit

25

-

18

MHz

Dot Clock High (see Figure 2)

tDH

15

-

22

-

ns

Dot Clock low (see Figure 2)

tDl

15

-

22

-

ns

BLANK to CClK Setup Time (see Figures 2, 3, 4, and 5)

tBS

50

-

50

-

ns

BLINK, Ul, lPl, II IRef. to BLANK) to CClK Setup Time
(see Figures 2, 3, 4, and 5)

tsc

20

-

20

-

ns

Attributes to CClK Setup Time (see Figures 2, 3, 4, and 5)

tSA

45

-

55

-

ns

Dot Data 00-09 to CClK Setup Time (see Figures 2, 3, 4, and 5)

tSD

70

-

70

-

ns

CURSOR to CClK Setup Time (see Figures 2, 3, 4, and 5)

tSK

50

-

50

-

ns

AFlG to CClK Setup Time (see Figures 2, 3, 4, and 5)

tFS

50

-

65

-

ns

tSH

45

-

55

-

ns

HOOT to CClK Setup Time (see Figures 2, 3, 4, and 5)
BLINK, Ul, lPl, II (Ref. to BLANK) Hold Time from
(see Figures 2, 3, 4, and 5)

arK
tHC

20

-

20

-

ns

Attributes Hold Time from CCLX (see Figures 2, 3, 4, and 5)

tHA

20

-

20

-

ns

Dot Data 00-09 Hold Time from CClK (see Figures 2, 3, 4, and 5)

tHD

30

-

ns

tHK

20

-

30
20

-

CURSOR Hold Time from CClK (see Figures 2, 3, 4, and 5)

-

ns

AFlG Hold Time from CClK (see Figures 2, 3, 4, and 5)

tFH

ns

tHH

BKGND to DClK Setup Time (see Figure 6)

tSG

30
20
15

-

HOOT Hold Time from CClK (see Figures 2,3,4, and 5)

-

-

30
20
15

-

ns

-

ns

CBlANK to DClK Setup Time (see Figure 6)

tSB

15

-

15

-

ns

BKGND Hold Time from DClK (see Figure 6)

tHG

15

-

15

-

ns

CBlANK Hold Time from DClK (see Figure 6)

tHB

15

-

15

-

ns

tDGM

-

65

-

65

ns

CClK from DClK Delay Time* Cl = 150 pF (see Figures 5 and 7)

tDC

-

65

-

65

ns

TTlVID1 and TTlVID2 from DClK Delay Time Cl = 150 pF
(see Figures 5 and 7)

tDV

45

75

45

80

ns

VIDEO from DClK Delay Time Cl = 150 pF (see Figures 5 and 7)

tDV

-

240

-

240

ns

GMD from DClK Delay Time Cl = 150 pF (see Figures 5 and 7)

* Cl less than 150 picofarads could be faster.

3-77

I

MC2673

FIGURE 2 -

HALF-DOT SHIFT TIMING DIAGRAM

DCLK

r
I.. -I" -I

CClK ---V-O-H'"'I

Val ___
~

tSH

~

___________________

tHH

VIH-r-T

HOOT

--.J

L-

VIDEO

I

Char N+ 1
NOTE: Half-dot shift feature 18 MHz maximum.

FIGURE 3 - VAC PIPELINE TIMING DIAGRAM

BLANK

~
~

Attributes 1

~

~
~

~

VIDE03

BKGND4

2nd
Char

1st
Char

NOTES
1. Attributes include: ABLlNK, ABlANK, ARVID, AUl, AHllT, and AlTPEN.
2. One CClK delay for dot data (obtained from delay through character generator).
3. See Figure 7 for detail timing of VIDEO, TTlVID1, TTlVID2.
4. Non-active scan time. VIDEO reverts to polarity selected by the BKGND input.

3-78

BKGND4

MC2673

FIGURE 4 - CURSOR PIPELINE TIMING DIAGRAM

1_

Cursor

Video

Character
jI
with Cursor -----./

FIGURE 5 - CHARACTER (AMODE=O), FIELD (AMODE= 1), AND GMD ATIRIBUTE TIMING DIAGRAM

AFLG

VIDEO
(AMODE=OI

I.
VIDEO
(AMODE= 11

{

Blank Characters If

•

AeM

}

~

GMD1
(AMODE= 11
NOTE
1. GMD output in MC2673B version only. See Figure 7 for detail timing.

FIGURE 6 -

BKGND AND CBLANK TIMING DURING INACTIVE SCAN TIME (BLANK = 1)

DCLK

~
SG

BKGND

~

---.J

r-

tHG

V~OIfI

~

VOL ',_-___________ (

VIDEO - - - - - W - h - i t - e - - = v BI"k

CBLANK

/

White

I

MC2673

FIGURE 7 - VIDEO AND GMD PIPELINE TIMING DIAGRAM

r

1/tD

-1

DCLK

~~tDcl
vO~~~.

_________________________________________________

I
VIDEO
TTLVID1,2

I

GMD1
(AMODE=l)
NOTE

1. GMD output in MC2673B version only.

SIGNAL DESCRIPTION

attributes. Cursor position, shape, and blink rate are controlled by this input.

The input and output signals for the VAC are described in
the following paragraphs.

BACKGROUND INTENSITY (BKGNO)
This input specifies light or dark video during BLANK and
character fields. Affects the intensities of all attributes.

DOT CLOCK (OCLK)

This input controls the dot frequency and video shift rate.
SCREEN BLANK (BLANK)
CHARACTER CLOCK (CCLK)
This output is a submultiple of DCLK. The frequency
ranges from one sixth to one twelfth of DCLK, as determined
by the state of the CCO-CC2 inputs.

When high, this input forces the video outputs to the level
specified by the BKGND input (either high or low intensity).
However, BLANK is riot effective when composite blank
(CBLANK) is high.

CHARACTER CLOCK CONTROL (CC2-CCO)
The logic state of these three static inputs determine the
internal divide factor for the CCLK output rate. Character
clock rates of 6 through 12 dots per character may be
specified.

COMPOSITE BLANK (CBLANK)

This input is used with the TTL video outputs only. When
high, CBLANK forces the video outputs to a low intensity
state for retrace blanking. When BKGND input is low, or
when usin.g video outputs, this input may be tied low.
REVERSE VIDEO ATTRIBUTE (ARVID)

DOT DATA INPUT (DO-09)

This input causes the intensity of the associated character
or field video to be reversed. All other attributes are effectively .reversed.

These are parallel inputs corresponding to the character/
graphic symbol dot data for a given scan line. These inputs
are strobed into the video shift register on the falling edge of
each characte'r clock.
'
HALF-~OT

HIGHLIGHT ATTRIBUTE (AHIL Tl
This input causes al.l dot video (including underline) of the
associated character or field to be highlighted with respect to
the BKGND input and the reverse video attribute.

SHIFT (HOOT)

When this input is high, the serial video output is delayed
by one-half dot time. This input is latched on the falling edge
of each character clock.

BLANK ATTRIBUTE (ABLANK)
This input generates a blank space in the associated character or field. The blank space intensity is determined by the
BKGND input,the reverse video attribute, and the CURSOR
input.

CURSOR TIMING (CURSOR)
This input provides the timing for the cursor video. When
high, it effectively reverses the intensities of the video and

3-80

MC2673

BLINK ATTRIBUTE (ABLlNK)

LAST LINE (LL)

This input causes the associated character or field video to
be driven to the intensity determined by BKGND and the
reverse video attribute when the BLINK input is high.

This input indicates the last scan line of each character
row and is used internally to extend field attributes across
row boundaries. Latched on the falling edge of BLANK. This
input has no effect in character mode (AMODE=O).

UNDERLINE ATTRIBUTE (AUL)

VIDEO (VIDEO)

This input specifies a line to be displayed on the character
or field. The line is specified by the underline (ULl input. All
other attributes apply to the underline video.

This is a three-level serial video output which corresponds
to the composite dot pattern of characters, attributes, and
cursor.

LIGHT PEN ATTRIBUTE (ALTPEN)

TTL VIDEO 1 (TTLVID1)

This input of the MC2673A specifies a highlighted line to
be displayed on the character or field. The line is specified by
the LPL input.

This output corresponds to the serial, non-highlighted
video dot pattern.

This input of the MC2673B is latched and synchronized to
provide a field graphics mode output for the MC2670 DCGG.

TTL VIDEO 2 (TTLVID2)
This output corresponds to the highlighted serial video dot
pattern. Should be used with TTLVID1 to decode a composite video of three intensities.

ATTRIBUTE MODE (AMODE)

MANUAL RESET (RESET)

ATTRIBUTE GRAPHICS MODE (AGM)

This input specifies character (AMODE= Q)
(AM ODE = 1) attributes mode.

This active high input initializes the internal logic and
resets the attribute latches. Normally used for testing.

or field

ATTRIBUTES FLAG (AFLG)

VCC, VSS, AND GND

This input, when high, causes the VAC to sample and
latch the attributes inputs. If field attributes are specified
(AMODE = 1), the attributes are double buffered on a row
basis. Thus, each scan line of every character row will start
with the attributes that were valid at the end of the previous
row.

Power is supplied to the VAC using these three pins. V CC
is the + 5 volts ± 5% power input, VBB is the bias supply
(see Figure 1), and GND is the ground connection.

FUNCTIONAL DESCRIPTION
The VAC consists of four major sections. The high speed
dot clock input is divided internally to provide a character
clock for system timing. The parallel dot data is loaded into
the video shift register on each character boundary and
shifted into the video logic block at the dot rate. The six attribute inputs are latched internally and combined with the
serial dot data to. provide a three-level video source for the
monitor.
A separate BLANK input defines the active screen area.
When BLANK = 0, the video levels are derived internally by
the combinations of dot data, attributes, cursor, and the
state of the BKGND input. Either black or white background
can be selected. Symbols (dot data) are normally gray and
can be highlighted to white or black as shown in Figure 8.
Note that the VIDEO output is inverted as referenced to the
TTL video outputs. The video output stages of the MC2673
are illustrated in Figure 9.
During the inactive screen area (BLANK= 1), the video
level produced by the TTL outputs in either white
(BKGND= 1) or black (BKGND=Q). A separate composite
blank (CBLANK) input is provided to suppress raster retrace
video when white background is specified. DUring the inactive screen area (BLANK= 1), the video level produced by
the VIDEO output is either black (BKGND= 1) or white
(BKGND=Q). For the latter case, raster retrace video suppression is accomplished by raising the BKGND input during
horizontal and vertical retrace intervals. For black
background, tie BKGND high. Tie CBLANK input low for
both cases.

ATTRIBUTE CONTROL DISPLAY (ACo)

In field attributes mode (AMODE= 1), if ACD=O, the first
character in each new attribute field (the attribute control
character) will be suppressed and only the attributes will be
displayed. If ACD = 1, the first character and the attributes
are displayed. This input has no effect in character mode
(AMODE=O).
BLINK (BLINK)

This input is sampled on the falling edge of BLANK to provide the blink rate for the character blink attribute. It should
be a submultiple of the frame rate.
UNDERLINE (UL)

This input indicates the scan line(s) for the underline attribute. Latched on the falling edge of BLANK.
LIGHT-PEN LINE (LPL)

For the MC2673A, this input indicates the scan line(s) for
the light pen strike-thru attribute. Latched on the falling edge
of BLANK.
GRAPHICS MODE (GMD)

For the MC2673B, this output provides a synchronized,
latched, field graphics mode corresponding to the AGM input. This output can be used to control the GM input on the
MC2670 DCGG.

3-81

11

..
3:

o
I\)

en
.....
w

FIGURE 8 - ENCODED VIDEO OUTPUTS

DCLK

CCLK

I
W
G

VIDE01
U)

B

6:>
I\)
TTLVID1

TTLVID2

Normal
Gray on Black
NOTE
1. W=White
G= Gray
B= Black

Highlighted
White on Black

Reverse
Gray on White

Reverse,
Highlighted
Black on White

MC2673

FIGURE 9 -

VIDEO OUTPUT STAGES OF THE MC2673

Part of Me2673

750

Vee

750

Vee

Vee

Vee

I
TTL

TTL

Driver

Driver

N

8o

:>

o

o

~

lI-

Zo= 750

~
l-

I-

750

CHARACTER CLOCK COUNTER
The character clock counter divides the frequency on the
DCLK input to generate the character clock (CClK). The
divide factor is specified by the clock control inputs (CCOCC2) as follows:

VIDEO SHIFT REGISTER
On each character boundary, the parallel data (DO-D9J is
loaded into the video shift register. The data is shifted out
least significant bit first (DO) by the DClK. If 11 or 12 dots/
character are specified (CC2-CCO = 110 or 111), a zero
(blan'k dot) is always shifted out before DO. For 12 dots/
character, a zero is also shifted out after D9. The serial dot
data is shifted into the video logic where it is combined
with the cursor and attributes to encode three levels of
video.

Character Clock (CCLK)
CC2

CCl

CCO

Dots/ Character

Duty Cycle

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

6
6
7

3/3
3/3
4/3
4/4
5/4
5/5
6/5
6/6

8
9

10
11
12

ATIRIBUTE AND CURSOR CONTROL
The VAC visual attributes capabilities include: reverse
video, character blank, blink, underline, highlight, and light
pen strike-thru. The six attributes and the three attribute
control inputs (AMOD, AFlG, and ACD) are clocked into

3·83

MC2673

the VAC on the falling edge of CClK. If AFlG is high, the
attributes are latched internally and are effective for either
one character time (AMODE= Q) or until another set of
attributes is latched IAMODE = 1). The attributes set is
double buffered on a row-by-row basis internally. Using
this technique, field attributes can extend across character
row boundaries thereby eliminating the necessity of starting each row with an attribute set.
When field attribute mode is selected, (AMODE = 1), the
V AC will accomodate two attribute storage configurations.
In one configuration, the attribute control data is stored in
the refresh RAM, taking the place of the first character
code in the field to be affected. For this mode, the ACD input is tied low and blank characters will be displayed in the

I

FIGURE 10 -

screen positions occupied by the attribute data (see Figure
10). In the second configuration, (ACD = 1), the character
codes and attribute data are presented to the VAC in
parallel. In this mode, dot data is displayed at each character position (see Figure 11).
The CURSOR and the attribute input signals are pipelined internally to allow for system propagations (one CClK
for refresh RAM, one CClK for dot generator). The attribute timing Signals BLINK, UL lPl, and II are clocked
into the VAC at the beginning of each scan line by the failing edge of the BLANK input. Thus, these Signals must be
in their proper state at the falling edge of BLANK preceding
the scan line at which they are to be active (see Figure 3).

SYSTEM BLOCK DIAGRAM OF THE MC2673 IN FIELD ATTRIBUTE MODE USING THE NARROW RAM
(8 WIDE) CONFIGURATION
To CRT Controller

~------C-CL-K~~
BLANK
BLINK
UL
LL
MC2673

r - - - ...,
Page N

I
Refresh
RAM
2K x8
Page 1

MC2670

.J

0:0 t----f--~

D~

0·9

D9

Video

GMD ....- - - - - - - I G M D
AGM
ARVID
AHILT

VCC

AUL
ABLINK

RAM Byte Format:

ABLANK
AFLG

AMODE J1KD
ACD

Causes
-.;.
Attribute Byte
To Be Displayed
As A Blank Character

-=-

AfLG
NotUsed
ABLINK - - - - - '
ABLANK - - - - - - - '

AGM
L--_ _ _

ARVID
AHIL T

L------AUL

3·84

MC2673

b

FIGURE 11 - SYSTEM BLOCK DIAGRAM OF THE MC2673 IN FIELD OR CHARACTER ATIRIBUTE MODE USING THE
WIDE RAM CONFIGURATION

.,

r

NotUsed

Ch",,'" Cod,

jCh"",,, B~' g

[

r
en
en

~

rp;;:geN

I


~

BCE

0

~

,.

~

RDB

BLANK
HSYNC

~
~

HFP=Even

I

\~

\~---_____________________

DADD

BLANK

~---

- -

-

---

-

HSYNC
DADD
NOTE:
If. co'nmand execution occurs just prior to the first scan line of a character row and row table addressing fTlode is enabled, execution of the
command is delayed by two character clocks from the timing illustrated.

-

\""""'--

MC2674

FIGURE 6 -

AVDC SHARED OR TRANSPARENT BUFFER MODES

Refresh
RAM

MC2674
AVDC

ADR
PBREa ----~~ CTRL1
CPU

{

BACK

+ - -....-~

BEXT

~-+----I

I

~-----,~a

w

CTRL3

Data I/O

CTRL2

Select
Decode

FIGURE 7 - TRANSPARENT BUFFER MODE TIMING

__......

~'--_-+

__-+____""'__,.. ___

r-------~---

.JI (2)

------

__ -1r-----~--BLANK

I,...--------.....~--------~)- - - - -~ --"\\

"-------

-----'-"'"

DADD
NOTES:
1. PBREa must be asserted prior to the rising edge of BLANK in order for sequence to begin during that blanking period.
2. If PBREa is negated after the next to last CCLK of the horizontal blanking interval. the next scan line will also be blanked.
3. Accesses during vertical blank or "display off" are granted only at the beginning of the horizontal front porch.
4. If row table addressing is enabled, CPU access is delayed by two character clocks prior to the first scan line of each character row
5. Measurement points shown at 0.8 V to 2.0 V, unless otherwise noted.

3·102

MC2674

FIGURE 8 -

___+-__

+-_~,""",...I\

SHARED BUFFER MODE TIMING

____ -

-

-

-

,.------- -+---- -------

-II (1)

1r-____~r__-----...,.!.12.. ____
BLANK

+ ___,,

~-------

DADD
NOTES:
1. )f PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked.
2. Measurement points shown at 0.8 V to 2.0 V, unless otherwise noted.

FIGURE 9 -

SHARED AND TRANSPARENT MODE TIMING
(b)

(a)

PBREQ

BACK

----------~\. .____~L~--J}----VBLANK or
DBLANK
DADO

,•

~
Refresh Addresses

Refresh
Addresses

L

---------~~.-----------

..•
BLANK

Sys. ADD

------- ........If --------

•

System Processor Has Continuous Bus Control

t:~:

DADO - {_ _ _ _....

_____}-

b) After 'display off and 3-state' command

a) During Vertical Blank or after 'display off' command in shared
mode only. See Figure 7 for transparent timing
NOTE: Measurment pOints shown at 0.8 V to 2.0 V, unless otherwise noted.

OPERATION

the other modes, but circuitry must be added to route the
data from the display memory to the data bus inputs of the
AVDC. Additionally, when not operating in row buffer
mode, care must be taken to assure that the CPU does not
attempt to access the A VDC while it is reading the row table.
One way of preventing this is to latch prior to reading or
writing the AVDC. The AVDC should only be accessed if the
latch is low, indicating that the last line of the row is not
active.
Figure 13 illustrates a typical hardware implementation for
use in conjunction with independent and transparent modes,
and Figure 14 shows the timing for row table operation.

After power is applied, the AVDC will be in an inactive
state. Two consecutive "master reset" commands are
necessary to release this circuitry and ready the AVDC for
operation. Two register groups exist within the ADC; the
initialization registers and the display control registers. The
initialization registers select the system configuration,
monitor timing, cursor shape, display memory domain,
pointer address, scrolling region, double height and width
condition, and screen format. These are loaded first and normally require no modification except for certain special visual

3·103

I

MC2674

FIGURE 10 - ROW BUFFER MODE CONFIGURATION
2x2111
Row
Refresh

RAM
~------~----~~OD

w

I

System
RAM

System
Decode

'R
W---~

System Data Bus

FIGURE 11 - ROW BUFFER MODE TIMING

NOTES:
1. If row table addressing is enabled, BREQ will be asserted at the middle of the last scan line of the prior row, and MBC will be asserted at the
beginning of BLANK.
2. Measurement points shown at 0.8 V to 2.0 V, unless otherwise noted.

3·104

MC2674

FIGURE 12 -

ROW TABLE ADDRESS FORMAT

r
Row Table {
in Memory

A
B
C
D

E
F

1st Char
2nd Char
Third
{
Data Row

SSR2

~~
I+-

0
0
0
last Char

1st Char
2nd Char
First
{
Data Row

I

r.--

0
0
0
last Char

1st Char
2nd Char
Second {
Data Row

""-

0
0
0
last Char

FIGURE 13 -

ROW TABLE MODE CONFIGURATION (NON-ROW BUFFER MODES)

CClK - - - - - - ,
RAM

MC2674
AVDC

DADD

ADD

Display Address

Data I/O

DBlNK

CClK
BLANK

R
W

CURSOR

IT
DO-D7

N ....---...J
8
Display Data Bus
Select
Decode

w

3·105

MC2674

FIGURE 14 - ROW TABLE MODE TIMING

CCLK

BLANK

lIlllf1IlIlflI1

lllIl
First Line of Row

Last Line of Row

HSYNC
EC+2HSWCCLKs
BREQ

I

Row Buffer
Mode

MBC

DADD

Last Line Addresses

,..------CURSOR

I

Possible Cursors

First Line Addresses

-

Refresh

------

Possible Cursors

DADD

First Line Addresses

DADD

First Line Addresses

3-State

Transparent
Buffer Mode

Independent
Buffer Mode

WDB

BCE

-----u-- ~ --u~_______________________________

= Multiplexed Control Signals
EC = Equalizing Constant
HSW= Horizontal SYNC Width

3·106

MC2674

effects. The display control registers specify the memory address of the base character (upper left corner of screen), the
cursor position, and the split screen addresses associated
with the scrolling area or an alternate memory. These may
require modification during operation.
After initial loading of the two register groups, the ADC is
ready to control the monitor screen. Prior to executing the
AVDC commands which turn on the display and cursor, the
user should load the display memory with the first data to be
displayed. During operation, the AVDC will sequentially address the display memory within the limits programmed into
its registers. The mem'ory outputs character codes to the
system character and graphics generation logic, where they
are converted to the serial video stream necessary to display
the data on the CRT. The user effects changes to the display
by modifying the contents of the display memory, the AVDC
display control and command registers, and the initialization
registers, if required. Interrupts and status conditions
generated by the AVDC supply the "handshaking" informa-

tion necessary for the CPU to effect real time display
changes in the proper time frame if required.

INITIALIZATION REGISTERS
There are 15 initialization registers (IRO-IR14) which are accessed sequentially via a single address. The AVDC maintains an internal pointer to these registers which is incremented after each write at this address until the last register
(lR14) is accessed. The pointer then continues to point to
IR14 for further accesses. Upon a power-on or a master reset
command, the internal pointer is reset to point to the first
register (IRQ) of the initialization register group. The internal
pointer can also be preset to any register of the group via the
"load IR address pointer" command. These registers are
write only and are used to specify parameters such as the
system configuration, display format, cursor shape, and
mOllitor timing. Register formats are shown in Figure 15.

FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 1 of 4)
4

IRO

Double
Height/
Width

Scan Lines Per Character Row
Non-Interlaced
Interlaced
0000= 1 Line
0000=2 Lines
0001 =2 Lines
OJOI =4 Lines
0010=3 Lines
0010=6 Lines

..

..

1110= 15 Lines
1111=16 Lines

Sync
Select
O=VSYNC
1= CSYNC

Buffer-Mode
Select
00= Independent
01 Transparent
10= Shared
II=Row

1110=30 Lines
1111 = Undefined

4

IRI

Interlace
Enable
0= NonBit
1= Interrupt

Equalizing Constant

00000oo = 1 CITR
0000001 = 2 ITIT

..

Calculated from:
EC= 0.5 (HACT+ HFP+ HSYNC+ HBP) -2(HSYNC)

1111110= 127 CCIK
1111111 = 128 ITIT

4
IR2

Row
Table
O=Off
1=On

o

3

Horizontal Sync Width
0000= 2 CClK
0001 =4 CClK

Horizontal Back Porch
000= Not Allowed
001 =3 CClK

1110=30 CClK
1111 = 32 CITR

110=23 CClK
111=27CITK

..

3·107

..

--

I

MC2674

FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 2 of 4)

Vertical Front Porch

Vertical Back Porch

000=4 Scan Lines
001 = B Scan Lines

00000=4 Scan Lines
00001 = 6 Scan Lines

110 = 28 Scan Lines
111 = 32 Scan Lines

11110=64 Scan Lines
11111 = 66 Scan Lines

..

..

6
IR4

I

o

3

4
IR3

o

4

Character
Blink Rate

Active Character Rows Per Screen

00000oo = 1 Row

0= 1/64
VSYNC
1 = 1/128
VSYNC

0000001 = 2 Rows

·
··

1111110=127 Rows
1111111=128 Rows

4

3

Active Characters Per Row

IR5

00000010= 3 Characters
00000011 =4 Characters

11111110 = 255 Characters
11111111 =256 Characters

4
IR6

First Line of Cursor

Last Line of Cursor

0000= Scan Line 0
0001 = Scan Line 1

0000= Scan Line 0
0001 = Scan Line 1

1110= Scan Line 14
1111=Scan Line 15

1110=Scan Line 14
1111=Scan Line 15

..

6
IR7
Light Pen Line
00= Scan
01 = Scan
10= Scan
11 = Scan

Line
Line
Line
Line

3
1
5
7

··

4
Cursor
Blink

Cursor
Rate

Underline Position

0= Off
1=On

0= 1/32
1= 1/64

0000= Scan Line 0
0001 = Scan Line 1

··

1110=Scan Line 14
1111 = Scan Line 15

3·108

MC2674

FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 3 of 4)
4
IRS

Display Buffer First Address LSBs
H'ooo'=O
H'OO1'=1
NOTE: MSBs are in IR9[3:0]
H'FFE' =4,094
H'FFF'=4,095

4
IR9

Display Buffer Last Address

Display Buffer First Address MSBs

0000= 1,023
0001 =2,047

..

See IRS

1110=15,359
1111 = 16,383

6
IRlO

4
Display Pointer Address Lower

See IR11

4
IR11

LZ Down

LZ Up

O~Off

O~OfI

1=On

1=On

Display Pointer Address Upper
H'oooo' -0
H'0001'= 1

..

H'3FFF' = 16,,383

4
IR12

Scroll End
0=011
1=On

3
Split Register 1
0000000= Row 1
0000001 = Row 2

..

1111111=Row 12S

3·109

I

MC2674

FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 4 of 4)

6
IR13

o

4

Scroll End
O=Off
l=On

Split Register 2
0000000= Row 1
0000001 =Row 2

..

1111111=Row 128

6
IR14

I

Double 1
00- Normal
01 = Double Width
10= Double Width
and Tops
11 = Double Width
and Bottoms

o

4
Double 2
00- Normal
01 = Double Width
10= Double Width
and Tops
11 = Double Width
and Bottoms

DOUBLE HEIGHT/WIDTH ENABLE (lRO[7]) - When this
bit is set, the value in IR14[7:6] is used to control the double
height and width conditions of each character row. Assertion of this bit also allows IR14[7:6] to be programmed in two
ways:
1. By the CP writing to IR14 directly.
2. When the contents of screen start register 1 (SSR1)
upper are changed, either by the CPU writing to this
register or by the automatic loading of SSR1 when
operating in row table mode, the two most significant
bits of SSR1 upper are copied into IR14[7:61. Thus, the
most significant bits of each row table entry can be used to control double height and double width attributes
on a row-by-row basis.
IR14[5:4] are not active when this bit is set. When this bit
is reset, the double height and width attributes operate as
described in IR[141.
SCAN LINES PER CHARACTER ROW liRO[6:3]) - Both
interlaced and non-interlaced scanning are supported by 'the
AVDC. For interlaced mode, two different formats can be
implemented, depending on the interconnection between
the AVDC and the character generator (see IR1[7])' This field
defines the number of scan lines used to compose a character row for each technique. As scanning occurs, the scan
line count is output on the LAO-LA3 and ODD pins.
VSYNC/CSYNC (lR0[2]) - This bit selects either vertical
sync pulses or composite sync pulses on the VSYNC/
CSYNC output (pin 18), The composite sync waveform conforms to EIA RS170 standards, with the vertical interval composed of six equalizing pulses, six vertical sync pulses, and
six more equalizing pulses.
BUFFER MODE SELECT liR0[1 :0]) - Four buffer memory
modes may be selectively enabled to accommodate the
desired system configuration. See SYSTEM CONFIGURATIONS.
INTERLACE ENABLE (lR1[7]) - Specifies interlaced or
non-interlaced timing operation. Two modes of interlaced
operation are available, depending on whether LO-L3 or

3·110

Lines to Scroll
0000= 1
0001 =2

..

1110= 15
1111=16

ODD, LO-L2 are used as the line address for the character
generator. The resulting displays are shown in Figure 16.
For "interlaced sync" operation, the same information is
displayed in both odd and even fields, resulting in enhanced
readability. The AVDC outputs successive line numbers in
ascending order on the LAO-LA3 lines, one per scan line for
each field.
The "interlaced sync and video" format doubles the character density on the screen. The AVDC outputs successive
line numbers in ascending order on the odd and LAO-LA2
lines, one per scan line for each field.
EQUALIZING CONSTANT (lR1[6:0]) - This field indirectly defines the horizontal front porch and is used internally to
generate the equalizing pulses for the RS170 compatible
CSYNC. The value. for this field is the total number of
character clocks (CCLKs) during a horizontal line period
divided by two, minus two times the number of character
clocks in the horizontal sync pulse:

The definition of the individual parameters is illustrated in
Figure 17.
Note that when using the MC2675 CMAC, it will delay the
bl~nk pulse three CCLKs relative to the HSYNC pulse.
ROW TABLE MODE ENABLE (IR2[7]) - Ass..ertion/negation of this bit causes the AVDC to begin/terminate
operating in row table mode starting at the 'next character
row. See ROW TABLE ADDRESS MODE. By using the split.
interrupt capability of the AVDC, this mode can be enabled
and disabled on a particular character row. This allows a
combination of row table and sequential addressing to be
utilized to provide maximum flexibility in generating the
display.
HORIZONTAL SYNC PULSE WIDTH (lR2[6:3]) - This
field specifies the width of the HSYNC pulse in CCLK
periods.

MC2674

FIGURE 16 - INTERLACED DISPLAY MODES

t~-----! {~O~~}l
Line Address
To Character Generator

Line Address
To Character Generator
"0
"0

0

Line Address
To Character Generator

C
Q)

JJ

c:

7

-0

]18

0

c

~
0

<1lCl:
0---

UJ gJ
OJ

c:
:.:J

4

-e-e-e-e-e--e
-e
-e-e-e
-e
-e
-e-e-e-e-e--

8

0

fii ~

(.lCC

UJ'U;
CX)

Q)

~:§

-e-e-e-e-e-1 -0-0-0-0-0--e
2-0
3 -e
3-0
4 -e-e-e
4-0-0-0
-e
5-0
6 -e
6-0
-e-e-e-e-e--

4

8

8

Non-Interlaced
IRO= 1000; Total Lines/Row=9

o

<\ :
4

Q)

-:§

6

7-00000----

1-00000----

4

0

8
1-00000----

4
6

8

7-00000----

1-00000----

4

Interlaced SYNC
IRO= 1000; Total Lines/Row= 16

CHARACTER BLINK RATE (lR4[7]) - Specifies the frequencyior the character blink attribute timing. The blink rate
can be specified as 1/64 or 1/128 of the vertical field rate.
The timing signal has a duty cycle of 50% and is multiplexed
onto the DADD11/BLINK output at the falling edge of each
BLANK.

3-111

-e
3-0
-eee
5-0
-e

8

7-0-0:-0-0-0--

VERTICAL FRONT PORCH (lR3[7:311 - Specifies the
number of scan line periods between the rising edges of
BLANK and VSYNC during the vertical retrace interval. The
vertical front porch will be extended in increments of scan
lines if the AClL input is low at the end of the programmed
value.

-e
3-0
-eee
5-0
-e

7-00000----

-e-e-e-e-e-1 -0-0-0-0-0--e
2-0
-e
3-0
-e-e-e
4-0-0-0
-e
5-0
-e
6-0
-e-e-e-e-e--

HORIZONTAL BACK PORCH (IR2[2:0]) - This field
defines the number of CClKs between the trailing edge of
HSYNC and the trailing edge of BLANK.

-e
3-0
-eee
5-0
-e

8

7 -0-0-0-0-0--

8

-e-e-e-e-e--e
-e
4 -e-e-e
5 -e
6 -e
-e-e-e-e-e--

1-00000----

~~
c
UJ'U;

-e
3-0
-eee
5-0
-e

Interlaced SYNC and Video
IRO=Ol00; Total Lines/Row= 10

CHARACTER ROWS PER SCREEN (lR4[6:0]) - This field
defines the number of character rows to be displayed. The
value multiplied by the scan lines peg character row, plus the
vertical frc.nt porch, the vertical back porch values, and the
vertical sync pulse width is the vertical scan period in scan
lines.
ACTIVE CHARACTERS PER ROW (lR5[7:0]) - This field
determines the number of characters to be displayed on each
row of the CRT screen. The sum of this value, the horizontal
front porch, the horizontal sync width, and the horizontal
back porch is the horizontal scan period in CClKs.
FIRST AND LAST SCAN LINE OF CURSOR (lR6[7:4),
IR6[3:0)) - These two field specify the height and position
of the cursor on the character block. The "first" line is the
topmost line when scanning from the top to the bottom of
the screen.

I

MC2674

FIGURE 17 - HORIZONTAL AND VERTICAL TIMING
character ROw _ _ _--I·~1
(lR5)

HBLANK

toI.r-_ _ _
--..J----iI..I __________.:1--~L-

~ ~FrontPorCh(IR1)
HSYNC

--.j

~HSYNC (lR2)

~Character Rows/ Screen (IR4)-+-j

---1r------i1

I

n ..___

~ VSYNC (lR7)
Equalizing
Constant

11111I
HSYNC
Width

IR21

..

HBACK
Porch

I

IRll

,

I I I 1I I I I

I

,
II

II III I I

VFRONT
Porch

VBACK
Porch

I...
IR31

Character Rowsl Screen
IR4

j.-

Back Porch (lR3)--.j

Lines/Row
IRO

I

'i----...L

--fl
~

I

I-r Scan Lines Per Row (lRO)

~ Front Porch (lR3)

-.j

VSYNC

~

r-l",,-__
-.j

VBLANK

BackPOrCh(lR2)--1

-rI

I I I

VSYNC
Width

,

1

I

I 1

I

~

IR71

I I

I I

Characters per Row
I R5

~I....-.. . . . . --'1'--'-1___..........
between these two bounds is used for data which can be
overwritten (e.g., as a result of scrolling), while data that is
not to be overwritten would be contained outside these
bounds and accessed by means of the automatic split screen
or split screen interrupt features of the AVDC.

VERTICAL SYNC PULSE WIDTH (JR7[7:6]) - This field
specifies the width of the VSYNC pulse in scan line periods.
CURSOR BLINK ENABLE (IR7[5]) - This bit controls
whether or not the cursor output pin will be blinked at the
selected rate (IR7[4]). The blink duty cycle for the cursor is
50%.
CURSOR BLINK RATE (JR7[4]) - The cursor blink rate
can be specified at 1/32 or 1/64 of the vertical scan frequency. Blink is effective only if blink is enabled by IR7[51.
UNDERLINE POSITION (JR7[3:0]) - This field defines
which scan line of the character row will be used for the
underline attribute by the MC2675 CMAC. The timing signal
is multiplexed onto the DADD10/UL output during the failing edge of BLANK.
DISPLAY BUFFER FIRST ADDRESS (JR9[3:0]), IR8[7:0]
I-\ND DISPLAY BUFFER LAST ADDRESS (JR9[7:4]) These two fields define the area within the buffer memory
where the display data will reside. When the data at the
"display buffer last address" is displayed, the AVDC will
wraparound and obtain the data to be displayed at the next
screen position from the "display buffer first address". If
"last address" is the end of a character row and a new
screen start address has been loaded into the screen start
register, or if "last address" is the last character position of
the screen, the next data is obtained from the address contained in the screen start register.
Note that there is no restriction in displaying data from
other .areas of the addressable memory. Normally, the area

DISPLAY POINTER ADDRESS LOWER (lRl0[7:0] AND
DISPLAY POINTER ADDRESS UPPER (JR11[5:0]) - These
two fields define a buffer memory address for AVDC controlled accesses in response to "read/write at pointer" commands. They also define the last buffer memory address to
be written for the "write from cursor to pointer" command.
SCAN LINE ZERO DURING SCROLL DOWN (JRZ11[7]) This field specifies normal scan line count or all scan line zero
counts for the new character row that occurs at the top of
the scrolling area during soft scroll down operation. If the
character generator provides blanks during scan line zero,
this will cause the new row to be automatically blanked on
the display. This feature can be used, if necessary, to blank
the. new row until the CPU places "blank data" into the
display buffer.
SCAN LINE ZERO DURING SCROLL UP (lRl1[6]) - This
field specifies normal scan linecourrt or all scan line counts
for the new character row that occurs at the bottom of the
scrolling area during soH scroll up operation.
SCROLL START (IR12[7]) - This bit is asserted when
soft scroll is to take place. The scrolling area begins at the
row specified in split register 1 (I R12[6:0]). If set, the first

3·112

MC2674

row to scroll scan line count will be reduced by the value in
the lines to scroll register (lR14[3:0]). The scan line count of
this row will start at the programmed offset value. When this
bit is asserted, scroll end IR13[7] must be set before split
register 2.
SPLIT REGISTER 1 (lR12[6:0]) - Split register 1 can be
used to provide special screen effects such as soft (scan line
by scan line) scrolling, double height/width rows, or to
change the normal addressing sequence of the display
memory. The contents of this field is compared, in real time,
to the current row number. Upon a match, the AVDC sets
the split screen 1 status bit, and issues an interrupt request if
so programmed. The status change/interrupt request is
made at the beginning of the scan line zero of the split screen
character row. If enabled by the SPL1 bit of screen start
register 2, an automatic split screen to the address specified
in screen start register 2 will be made for the designated
character row. During a scroll operation, this field defines
the first character row of the scrolling area.
SCROLL END (IR13[7]) - This field specifies that the row
programmed in split register 2 (IR13[6:0]) is to be the last
scrolling row of the scrolling area. Note that this bit must be
asserted for a valid row only when the scroll start bit IR12[7]
is also asserted.
SPLIT REGISTER 2 (lR13[6:0]) -: This field is similar to
the split register 1 field except for the following:
1. Split screen 2 status bit is set.
2. During a scroll operation, this field defines the last
character row of the scrolling area. This row will be
followed by a partial row. The LTSR (IR14) value
replaces the normal scan lines/ row value for the partial
row, thus keeping the total scan lines/screen the same.
3. If enabled by the S PL2 bit of screen start register 2, an
automatic split to the address contained in screen start
register 2 will occur in one of two ways:
a) If not scrolling an automatic split will occur for the
next character row.
b) If scrolling, the automatic split will occur after the
partial row being scrolled onto or off the screen.

4. The specified double width and height conditions (IR14)
are also asserted in two possible ways:
a) Automatic split will assert the programmed condition
for the current row.
b) During soft scroll operation the programmed conditions are asserted for the partial row scrolling onto or
off the screen.
DOUBLE 1 (lR14[7:6]) - This field specifies the conditions (double width/height or normal) of the row deSignated
in split register 1 (IR12[6:0J). When double height tops or
bottoms has been specified, the AVDC will automatically
toggle between tops and bottoms until another split 1 or 2
occurs which changes the double height/width condition. If
a double height top row is specified, the scan line count will
start at zero and increment the scan line every other scan
line. If a double height bottom row is specified, the AVDC
will start a one half the normal scan line total. If double width
is specified, the AVDC will assert the DADD9/DW output at
the falling edge of blank. This condition will also remain active until the next split 1 or 2. When IRO[7] = 1, the values
written into bits 7 and 6 of screen start 1 upper will also be
written into IR14[7:6] and the automatic toggling between
tops and bottoms is disabled.
DOUBLE 2 (lR14[5:4]) - This field specifies the conditions (double width/height or normal) of the row designated
in split register 2 (IR13[6:0]). Not used with IRO[7] = 1.
LINES TO SCROLL (lR14[3:0]) - This field defines the
scan line increment to be used during a soft scroll operation.
This value will only be used when scroll start (lR12[7]) and
scroll end (lR13[7]) are enabled.
TIMING CONSIDERATIONS

Normally, the contents of the initialization registers are not
changed during normal operation. However, this may be
necessary to implement special display features such as
multiple cursors and horizontal scrolling. Tpble 2 describes
timing details for these registers which should be considered
when implementing these features.

TABLE 2 - TIMING CONSIDERATIONS

Parameter

Timing Considerations

First Line of Cursor
Last Line of Cursor
Underline Line

These parameters must be established at a minimum of two character times prior to their
occurrence.

Double Height Character Rows
Double Width Character Rows
Rows to Scroll

Set! reset prior to the row specified in split 1 or 2 registers.

Cursor Blink
Cursor Blink Rate
Character Blink Rate

New values become effective within one field after values are changed.

Split Register 1
Split Register 2

Change anytime prior to line zero of desired row.

Character Rows Per Screen

Change only during vertical blanking period.

Vertical Front Porch

Change prior to first line of VFP.

Vertical Back Porch

Change prior to four line after VSYNC.

Screen Start Register 1
Row Table Mode Enable

Change prior to the horizontal blanking interval of the last line of character row before row where
new value is to be used.

3·113

I

MC2674

DISPLAY CONTROL REGISTERS
There are seven registers in this group, each with an individual address. Their formats are illustrated in Figure 18.
The command register is used to invoke one of 19 possible
AVDC commands as described in COMMANDS. The remaining registers in the group store address values which
specify the cursor location, the location of the first character
to be be displayed on the screen, and any split screen address locations. The user initializes these registers after
powering on the system and changes their values to control
the data which is displayed.

I

SCREEN START REGISTERS 1 AND 2
The screen start 1 registers contain the address of the first
character of the first row (upper left corner of the active
display). At the beginning of the first scan line of the first
row, this address is transferred to the row start register
(RSR) and into the memory address counter (MAC). The
counter is then advanced sequentially at the character clock
rate for the number of times programmed into the active
characters per row register (lR5), thus reaching the address
of the last character of the row plus one. At the beginning of
each subsequent scan line of the first row, the MAC is
reloaded from the RSR and the above sequence is repeated.
At the end of the last scan line of the first row, the contents
of the MAC is loaded into the RSR to serve as the starting
memory address for the second character row. This process
is repeated for the programmed number of rows per screen.
Thus, the data in the display memory is displayed sequentially starting from the address contained in the screen start
register. After the ensuing vertical retrace interval, the entire
process repeats again.
During vertical blanking, the address counter operation is
modified by stopping the automatic load of the contents of
the RSR into the counter, thereby allowing the address outputs to free-run. This allows dynamic memory refresh to occur during the vertical retrace interval. The refresh addressc

FIGURE 18 -

ing starts at the last address displayed on the screen and increments by one for each character clock during the retrace
interval. If the display buffer last address is encountered,
refreshing continues from the display buffer first address.
The sequential operation described above will be modified
upon the occurrence of any of three events. First, if during
the incrementing of the memory address counter the
"display buffer last address" (lR9[7:4)) is reached, the MAC
will be loaded from the "display buffer first address" register
. (IR9[3:0) and IR8[7:0]) at the next character clock. Sequential operation will then resume starting from this address.
This wraparound operation allows portions of the display
buffer to be used for purposes other than storage of displayable data and is completely automatic without any CPU
intervention (see Figure 19a).
The sequential row to row addressing can also be modified
via split register 1 (lR12) and split register 2 (lR13), under
CPU control, or by enabling the row table addressing mode.
If bit 6 of screen start register 2 upper (SPL 1) is set, the
screen start register 2 contents will be loaded automatically
into the RSR at the beginning of the first scan line of the row
designated by split register 1 (lR12[6:0))' If bit 7 of screen
start 2 upper (SPL2) is set, the screen start register 2 contents is automatically loaded into the RSR at the end of the
last scan line of the row designated by split register 2
(lR13[6:0)). SPL1 and SPL2 are write only bits and will read
as zero when reading screen start register 2.
If the contents of screen start register 1 (upper, lower, or
both) are changed during any character row (e.g., row'n'),
the starting address of the next character row (row 'n+ 1')
will be the new value of the screen start register and addressing will continue sequentially from there. This allows features such as split screen operation, partial scroll, or status
line display to be implemented. The split screen interrupt feature of the AVDC is useful in controlling the CPU initiated
operations. Note that in order to obtain the correct screen
display, screen start register 1 must be reloaded with the
original (origin of display) value prior to the end of the vertical retrace. See Figure 19b.

DISPLAY CONTROL REGISTER FORMATS (Sheet 1 of 2)

4

6

3

o

Command Code

See COMMANDS for Command Codes

Command Registers (Wnte Only)

6

5

o

4
Upper Register

DADD15

DADD14

Most Significant Bits

3·114

MC2674

FIGURE 18 -

DISPLAY CONTROL REGISTER FORMATS (Sheet 2 of 2)

4
Lower Register (Least Significant Bit)
H'OOOO' -0
H'OOOl'= 1
Through
H'3FFE' = 16,382
H'3FFF' = 16,383

NOTE: Most significant bits are in upper register [5:0]

NOTES:
1. Bits 7 and 6 of upper register are not used in the cursor address register.
2. Bits 7 and 6 of upper register are always zero when read by the CPU.
3. When IRO[7] = 1, the values written into bits 7 and 6 of screen start 1 upper will also be written into
IR14[7:6] to control the double width and double height attributes of the display as follows:

2

~

Attribute
None
Double Width Only
Double Width and Double Height Tops
Double Width and Double Height Bottoms

o

o
1
1

1
0
1

Screen Start 1 Register (Read and Write) and
Cursor Address Registers (Read and Write)

4
Upper Register
SPL2
O=Off
l=On

SPL1
0= Off
l=On

6

Most Significant Bits

4

3

Lower Register (Least Significant Bit)
H'OOOO'=O
H'OOOl'=l
Through
H'3FFE' = 16,382
H'3FFF' = 16,383

NOTE: Most significant bits are in upper register [5:0]

NOTE:
Bit 7 and bit 6 are always zero when read by the CPU.
Screen Start 2 Registers (Read and Write)

When row table addressing mode is enabled, the first address of the row table is designated in SSR2. The AVDC
fetches the next row's starting address from the table during
the blanking interval prior to the first scan line of each character row and loads it into SSRl for use as the starting address of the next row. Since the contents of SSR2 changes
as the table entries are fetched, it must be re-initialized to
point to the first table entry during each vertical retrace interval.
The values of the two most significant bits of SSRl upper
are multiplexed onto the DADD1!DADD14 and DADD2!
DADD15 outputs during the falling edge of BLANK. If
I RO[7] = 0, these two bits act as memory page select bits
which may be used to extend the display memory addressing

3-115

range of the AVDC up to 64K. In that case, these two bits
act as a two-bit counter which is incremented each time that
"wraparound" occurs (see above). Note that the counter is
incremented at the falling edge of BLANK and that for proper display operation the wraparound address should be programmed to occur at the last character position of a row.
Also, the first address accessed in the new page will be the
address contained in the display buffer first address register
(lR9[3:0] and IR8[7:0J).
CURSOR ADDRESS REGISTERS

The contents of these registers define the buffer memory
address of the cursor. The cursor output will be asserted
when the memory address counter matches the value of the

I

MC2674

FIGURE 19 -

DISPLAY ADDRESSING OPERATION

Bottom of Screen-

Screen Start -

r-.~~~..--.:~:-I

I-"'""""'~~~~"

I

-

Display Buffer End

Monitor
Display

16K ' - - - - - - - - - '

Memory
(a) Display Memory Wraparound

0.----------,

Screen Start 1 -

..,..,....,..,...,...,..,...,....,....,..,...,...,..,.-,1

Screen Start 2 -

~...........--....--....--..~:-I

~-::.~~~~....:f-

Display Buffer End

Monitor
Display

16K ' - - - - - - - - - '

Memory
(b) Display Memory Split Screen With Wraparound

cursor address registers for the scan lines specified in IR6.
The cursor address registers can be read or written by the
CPU or incremented via the "increment cursor address"
command. In independent buffer mode, these registers
define a buffer memory address for AVDC controlled access
in response to "read/write at cursor with/without increment" commands, or the first address to be used in
executing the "write from cursor to pointer" command.

(masked) from causing interrupts by certain AVDC commands. An interrupt condition which is enabled (masked bit
equal to one) will cause the INTR output to be asserted and
will cause the corresponding bit in the interrupt register to be
set upon the occurrence of the interrupting condition. An
interrupt condition which is disabled (mask bit equal to zero)
has no effect on either the INTR output or the interrupt
register.
The status register provides six bits of status information:
the five possible interrupt conditions plus the RDFLG bit. For
this register, however, the contents are not affected by the
state of the mask bits.
Descriptions of. each interrupt/status register bit fOllow.
Unless otherwise indicated, a bit, once set, will remain set
until reset by the CPU by issuing a "reset interrupt/status
bits" command. The bits are also reset by a "master reset"
command and upon power-up.

INTERRUPT/STATUS REGISTERS

The interrupt and status registers provide information to
the CPU to allow it to interact with the AVDC to effect
desired changes that implement various display operations.
The interrupt register provides information on five display
operations. The interrupt register provides information on
five possible interrupt conditions, as shown in Figure 20.
These conditions can be selectively enabled or disabled

3-116

MC2674

FIGURE 20 -

INTERRUPT ANO STATUS REGISTER FORMAT

4
RDFLG
Not Used
Always Read as 0

0= Busy
1 = Ready

Line
Zero

VBLANK
O=No
1 =Yes

O=No
1 = Yes

RDFlG (lfSR[5J) - This bit is present in the status
register only. A zero indicates that the AVDC is currently
executing the previously issued delayed command. A one
indicates that the AVDC is ready to accept a new delayed
command.
VBLANK (l/SR[4J) - Indicates the beginning of a vertical
blanking interval. Set to one at the beginning of the first scan
line of the vertical front porch.
LINE ZERO (l/SR[31) - Set to one at the beginning of the
first scan line (line 0) of each active character row.
SPLIT SCREEN 1 (IISR[2J) - This bit is set when a match
occurs between the current character row number and the
value contained in split register 1, IR12[6:0). The equality
condition is only checked at the beginning of line zero of
each character row.
READY (l/SR[1J) - The delayed commands affect the
display and may require the AVDC to wait for a blanking
interval before enacting the command. This bit is set to one

TABLE 3 -

07

06

05

D4

03

02

01

DO

Split 1
O=No
1 =Yes

Ready
0= Busy
1 = Ready

Split2
O=No
1 = Yes

when execution of a delayed command has been completed.
No other delayed command should be invoked until the prior
delayed command is completed.
SPLIT SCREEN 2 (l/SR[OJ) - This bit is set when a match
occurs between the current character row number and the
value contained in split register 2 (IR13[6:01l.

COMMANDS
The AVDC commands are divided into two classes: the instantaneous commands which are executed immediately
after they are invoked, and the delayed commands which
may need to wait for a blanking interval prior to their execution. Command formats are shown in Table 3. The commands are asserted by performing a write operation to the
command register with the appropriate bit pattern as the
data byte.

AVOC COMMANO FORMATS

Hex

Command
Instantaneous Commands

0
0
0
0
0
0
0
0
0
1
0

- -

0
0
0
0
0
0
0
0
1
0
1

f--

0
0
1
1
1
1
1
1
0
0
1

0
1
d
d
d
d
1
1
N
N
N

- - -V- -

0

0

0

0

V

V

V

V

d
d
1
1
d
d
N
N
N

d
d
N
N
d
d
N
N
N

1

0*
1*
0*
1*
0*
1*
N
N
N

-

-S

B

L
Z

0

0

1

0
0

0
1
1
1
1
1
1
1

0
0

P
1

-

Master Reset
Load IR Pointer with Value V (V=O to 14)
Disable Graphics
Enable Graphics
Disable Off - Float DADD Bus if N = 1
Disable On - Next Field (N = 1) or Scan Line (N = 0)
Cursor Off
Cursor On
Reset Interrupt/Status: Bit Reset where N = 1
Disable Interrupt: Disable where N = 1

- - -S -

R
D
Y

P
2

~n~l~n~r~p..!: ~aE.le~ I~e:..r:ue!s ~~r~ N~ ~ _
Interrupt Bit
Assignments

Delayed Commands
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0

0
0

1
1
1
1
1
1
1
1
1

0
0
0
0
1
1

1

0
1

0
0

0

1

1
0
0
1

0
1
1
0

0

A4

0
1

A2
A9
AC
AA
AD
AB
BB
BD

0
0
1
1
1
1

Read at Pointer Address
Write at Pointer Address
Increment Cursor Address
Read at Cursor Address
Write at Cursor Address
Read at Cursor Address and Increment Address
Write at Cursor Address and Increment Address
Write from Cursor Address to Pointer Address
Read from Cursor Address to Pointer Address

NOTES:
* Any combination of these three commands is valid.
d= Don't care.

3·117

---------

I

MC2674

I

INSTANTANEOUS COMMANDS
The instantaneous commands are executed immediately
after the trailing edge of the write pulse during which the
command is issued. These commands do not affect the state
of the RDFLG or READY interrupt/status bits and can be invoked at any time.

Restores normal blanking operation either at the beginning
of the next field (bit 2= 1) or at the beginning of the next
scan line (bit 2=0), Also returns the DADDO-DADD13
drivers to their active state.

MASTER RESET

CURSOR OFF
Disables cursor operation. Cursor output is placed in the
low state.

This command initializes the AVDC and can be invoked at
any time to return the AVDC to its initial state. Upon powerup, two successive master reset commands must be applied
to release the AVDC's internal power-on circuits. In
transparent and shared buffer modes, the CTRL 1 input must
be high when the command is issued. The command causes
the following:
1. VSYNC and HSYNC are driven low for the duration of
the command and BLANK goes high. After command
completion, HSYNC and VSYNC will begin operation
and BLANK will remain high until a "display on" command is received.
2. The interrupt and status bits and masks are set to zero,
except for the RDFLG flag which is set to a one.
3. The row buffer mode, cursor-off, display-off, and line
graphics disable states are set.
4. The initialization register pOinter is set to address IRO.
5. IR2[7] is reset.
LOAD IR ADDRESS

This command is used to preset the initialization register
pointer with the value "V" defined by D3-DO. Allowable
values are 0 to 14.
ENABLE GRAPHICS

After invoking this command, the AVDC will increment
the MAC to the next consecutive memory address for each
scan line even if more than one scan line per row is programmed. This mode can be used for bit-mapped graphics where
each location in the display buffer within the defined area
contains the bit pattern to be displayed. This command is
row buffered and should be asserted during the character
row prior to the row where this feature is required. This
allows the user to enter and exit graphics mode on character
row boundaries.
To perform split screen operations while in graphics mode
use SSR2 only.
DADDO/LG is asserted during the trailing edge of BLANK
for each scan line while this mode is active.
DISABLE GRAPHICS

Normal addressing resumes at the next row boundary.
DISPLAY OFF

Asserts the BLANK output. The DADDO through DADD13
display address bus outputs can be optionally placed in the
three-state condition by setting bit 2 to a one when invoking
the command.

3·118

DISPLAY ON

CURSOR ON
Enables normal cursor operation.
RESET INTERRUPT/STATUS BITS
This command resets the designated bits in the interrupt
and status registers. The bit positions correspond to the bit
positions in the registers:
Bit 0 - Split 2
Bit 1 - Ready
Bit 2 - Split 1
Bit 3 - Line Zero
Bit 4 - Vertical Blank
DISABLE INTERRUPTS
Sets the interrupt mask to zeros for the designated conditions, thus disabling these conditions from being set in the
interrupt register and asserting the INTR output. Bit position
correspondence is as above.
ENABLE INTERRUPTS
This command writes the associated interrupt mask bit to
a one. This enables the corresponding conditions to be set in
the interrupt register and asserts the INTR output. Bit position correspondence is as above.
DELAYED COMMANDS

This group of commands is utilized for the independent
buffer mode of operation, although the "increment cursor"
command can also be used in other modes. With the exception of the "write from cursor to pointer" and "increment
cursor" commands, all the commands of this type will be
executed immediately or will be delayed depending on when
the command is invoked. If invoked during the active screen
time, the command is executed at the next horizontal blanking interval. If invoked during a vertical retrace interval or a
"display off" state, the command is executed immediately.
The "increment cursor" command is executed immediately after it is issued and requires approximately three CCLK
periods for completion. The "write from cursor to pointer"
command executes during blanking intervals. The AVDC will
execute as many writes as possible during each blanking
interval. If the command is not completed during the current
blanking interval, the command will be held in suspension
during the next active portion of the screen and continues
?uring the next blanking interval until the command is
completed.

®

MC2675

MOTOROLA

HMOS

Advance Information

(HIGH-DENSITY N-CHANNEL, SILICON-GATE)

COLOR/MONOCHROME ATTRIBUTES CONTROLLER
(CMAC)
The MC2675 color/monochrome attributes controller (CMAC) IS a
bipolar LSI device designed for CRT terminals and display systems that
employ raster scan techniques. It contains a programmable dot clock
divider to generate a character clock, a high speed shift register to
serialize input dot data into a video stream, latches, logic to apply visual
attributes to the resulting display, and logic to display a cursor on the
display.
The CMAC provides control of visual attributes on a character-bycharacter basis for two operating modes: monochrome and color. The
monochrome mode provides reverse video, blank, highlight, and two
general purpose user definable attributes. In this mode, the display
characters can be specified to appear on either a light or dark screen
background. Retrace video supression can be automatically or externally controlled. The color mode provides eight colors for foreground
(character) video and eight colors for background video together with a
luminance output for external color set selection or to simultaneously
drive a monochrome monitor. Additionally, both modes provide double
width, underline, blink, dot stretching, and dot width attributes. In
monochrome mode, the MC2675 emulates the attributes characteristics
of Digital Equipment Corporation VT100 terminal.
The horizontal dot frequency is the basic timing input to the CMAC.
This clock is divided internally to provide a character clock output for
system synchronization. Up to ten bits of dot data are parallel loaded into the video shift register on each character boundary. The two TTL
video data outputs in monochrome mode are encoded to provide four
video intensities (black, gray, white, and highlight). The video data in
color mode is encoded to provide eight foreground colors and shifted
out on three TTL outputs, together with the luminance output.
Applications include CRT terminals, word processing systems, small
business computers.
• 25 MHz and 18 MHz Video Dot Rate Versions*
• Four Video Intensities Encoded on Two TTL Outputs (Monochrome
Mode)
• Eight Foreground and Background Colors Encoded on Three TTL
Outputs (Color Mode)
• Internally Latched
Reverse Video
Blank
Blink
Underline
Highlight

Character Atrributes:
Two General Purpose
Eight Foreground Colors
Eight Background Colors
Dot Width Control
Double Width Characters

• Up to Ten Dots Per Character
Light or Dark Background in Monochrome Mode Retrace Blanking

I
S SUFFIX
CERDIP PACKAGF
CASE 734

PIN ASSIGNJI4ENT
VBB

DO

D3

D2

D5

D4

D7

D6

D8

C1

R8LANK

CO

CURSOR

CCLK

CMODE

DCLK

DOTS

DOTM

BLINK

UL

M!C
BLUE!
TTLV2
RED!TTLV1

ADOUBLE

GREEN!GP1

RESET

Automatic
ABLINK
AGREENF!
SKGND
AGREENB!
ARVID
AUL

• Programmable Dot Stretching
• TTL Compatible
• 40-Pin Dual-in-Line Package

GND

* For faster versions consult factory.
This document contains information on a new product Specifications and information herein
are subject to change without notice

3.. 119

VCC

D1

BLANK

• VT100 Compatible Attributes
• Reverse Video Cursor with Optional White Cursor in Color Mode
•

COLOR/MONOCHROME
ATTRIBUTES CONTROLLER
(CMAC)

LUM!GP2
AREDF!
AHILT
ADOTM
ASLUEF!
ASLANK
ASLUEB!
AGP2
AREDS!
AGP1

MC2675

ORDERING INFORMATION (VCC=5 V ±5%, ODC to 70 DC)
Dots Per
Character

Frequency
(MHz)

Order Number

Ceramic
L Suffix

7,8,9,10
7,8,9, 10
6,8,9,10
6,8,9,10

18
25
18
25

MC2675B8L
MC2675B5L
MC2675C8L
MC2675C5L

Plastic
P Suffix

7,8,9, 10
7,8,9, 10
6,8,9,10
6, 8, 9, 10

18
25
18
25

MC2675B8P
MC2675B5P
MC2675C8P
MC2675C5P

Cerdip
S Suffix

7,8,9,10
7,8,9, 10
6,8,9,10
6,8,9,10

18
25
18
25

MC2675B8S
MC2675B5S
MC2675C8S
MC2675C5S

Package Type

I

BLOCK DIAGRAM
DCLK
C1

Double
Width
Logic

co

ADOUBLE

DOTM

Dot
Modulation
Logic

00-08

DOTS
ADOTM

RBLANK

UL
BLINK
CURSOR
CMODE
ABLINK
AUL

M/C
ABLUEFI ABLANK
AGREENF/BKGND

Monochrome
and Color
Attribute
and
Cursor
Logic

Video
and
Attribute
Hierarchy
Logic

RED/TTLV1
TTL
Drivers

BLUE/TTLV2
GREEN/GP1
LUM/GP2
BLANK

AREDF/AHILT

RESET

ABLUEBI AGP2

. . - - VCC

AGREENBI ARVID

. . - - VSS

AREDB/AGP1

. . - - GND

3·120

MC2675

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit
V

Supply Voltage

VCC

-0.3 to + 7.0

Input Voltage

Yin

-0.3 to + 7.0

V

Operating Temperature Range

TA
Tstg

o to 70

°c

- 55 to + 150

°c

Storage Temperature Range

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic Package
Ceramic Package

Symbol

Value

Rating

f)JA

50
50

°C/W

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum-rated voltages to this highimpedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range V SS s (Vin or
Vout) s V Cc. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS
or VCC).

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)
TJ = TA + (PO-OJA)
Where:
TA == Ambient Temperature, °c
OJA == Pack-age Thermal Resistance, Junction-to-Ambient, °C/W
PO==PINT+ PPORT
PINT==ICCxVCc, Watts - Chip Internal Power
PPORT == Port Power Dissipation, Watts - User Determined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J (if PPORT is neglected) is:
PO=K+(TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
K = PO-(T A + 273°C) + OJNP 0 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known T A. Using this value of K the values of Po and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA-

DC ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C VCC=5 0 V +5%)
Parameter

Symbol

Min

Max

Unit

Input low Voltage

Vil

-0.3

0.8

V

Input High Voltage

VIH

2.0

V

Output low Voltage (IOl =4 mAl

Val

-

VCC
0.4

Output High Voltage (lOH = - 400 p.A)

VOH

2.4

-

Input low Current (Vin = 0.4 V)

DClK
All Other Inputs

Input High Current (Vin = 2.4 V)

DClK
All Other Inputs

-

III

-

-800
-400

V
V
p.A

lin

-

40
20

p.A

VCC Supply Current (Vin=O V, VCC= Max)

ICC

-

80

mA

VSS Supply Current (See Figure 1)

ISS

-

120

mA

3-121

-

I

MC2675

FIGURE 1 -

RECOMMENDED VSS TEST CIRCUIT
VCC
40
VCC

?

31.6

<>
(>

1%,

n

y, W

1
VBB
_L-

I--

I

AC ELECTRICAL CHARACTERISTICS -

0.1/LF

DOT CLOCK TIMING (TA=O°C to 70°C, VCC=5.0 V ±5%)
25 MHz

18 MHz

Symbol

Min

Max

Min

Max

Unit

Dot Clock High Time

tOH

15

-

22

-

ns

Dot Clock low Time

tDl

15

-

22

-

ns

BLANK to CClK Setup Time

tSB

40

-

50

-

ns

Attributes to CClK Setup Time

tSA

40

-

50

-

ns

00-09 to CClK Setup Time

tso

60

-

70

-

ns

CURSOR to CClK Setup Time

tSK

40

50

-

ns

CO and C1 to OClK Setup Time

tsc

20

-

20

-

ns

RBlANK to OClK Setup Time

tSR

20

-

20

-

ns

BLINK, Ul, DOTS, to BLANK Setup Time

tSM

20

-

20

-

ns

BLANK from CClK Hold Time

tHB

20

-

20

-

ns

Attributes from CClK Hold Time

tHA

20

-

20

-

ns

00-08 from CClK Hold Time

tHO

30

-

30

-

ns

CURSOR from CClK Hold Time

tHK

20

-

20

-

ns

CO and C1 from OClK Hold Time

tHC

20

-

20

-

ns

RBlANK from OClK Hold Time

tHR

20

-

20

-

ns

BLINK, Ul, DOTS, from BLANK Hold Time

tHM

20

-

20

-

ns

CClK from OClK Delay Time (Cl = 50 pF)

toc

-

55

-

70

ns

Other Outputs from OClK Delay Time (CL = 50 pF)

tov

30

60

35

70

ns

Parameter

NOTE: All voltage measurements are referenced to ground. For testing, all input signals swing between 0.4 volts and 2.4 volts with a transition
time of 3 nanoseconds maximum. All time measurements are referenced at input voltages of 0.8 volts and 2.0 volts and at output
voltages of 0.8 volts and 2.0 volts as appropriate.

3-122

MC2675

CMAC PIPELINE TIMING DIAGRAM

BLANK

BLINK,
Ul,
DOTS

---v-c;;tV

Attributes 1

~

~

~
~

Dot Data 2

00-08

~

Vide03

~

---_,------_r------,------

----------r---~_,------_r----1st
2nd
BKGND4
__
_ _ _...L-_
___'_ _
___________
Char
Char

I

......._ _ _ _ _......~_

BKGND4

__L_ __

NOTES:
1. Attributes include: ABLlNK, ABlANK, ARVID, AUl, AHllT, ADOUBlE, ADOTM, two general purpose, and foreground/background
colors.
2 One CClK delay for dot data (obtained from delay through character generator!.
3. For detail timing of video outputs, see Output Pipeline Timing Diagram.
4. Non-active scan time. Video reverts to polarity selected by the BKGND input in monochrome mode.

OUTPUT PIPELINE TIMING DIAGRAM

CURSOR PIPELINE TIMING DIAGRAM

~l/tD-+l

CClK

CURSOR

VIDEO

~
~
I

I

Character
with CURSOR

tDHM

tDlM

OClK

\tIDe
CClK

~

Other
Outputs

~

Character N - 1

3·123

Character N

II

MC2675

BKGND AND RBLANK TIMING DIAGRAM DURING INACTIVE SCAN TIME (BLANK= 1) -

DClK

MONOCHROME MODE

r-pHA

BKGND

Video

I

Gray

:\
\

/

Black

Gray

Black

I

CLOCK DIVIDER TIMING DIAGRAM

DClK

ffi

CClK1

CO, C1

~ ~I ----~

~~~~~~~~D~o~n~'t~c~a~re~~~~~~~~~_

'.---SC

_~

____________D_o_n_'t_c_a_re____________

~ ~tHC

-r:>C~_________

NOTE:
1. The high and low times of CClK may be controlled independently.

SIGNAL DESCRIPTION

RED/TTL VIDEO 1 (RED/TTLV1)
In color mode, this output provides the red gun serial
video. In monochrome mode, it should be used with the
bluelTTL video 2 output to decode four video intensities.

The input and output signals for the CMAC are described
in the following paragraphs.

BLUE/TTL VIDEO 2 (BLUE/TTLV2)
In color mode, this output provides the blue gun serial
video. In monochrome mode, it should be used with the
readlTTL video 1 output to decode four video intensities.

VCC. VBB. AND GND
Power is supplied to the CMAC using these three pins.
VCC is the +5 volts ±5% power input, VBB is the bias
supply current (refer to Figure 1), and GND is the ground
connection.

GENERAL/GENERAL PURPOSE 1 (GREEN/GP1)
In color mode, this output provides the green gun serial
video. In monochrome mode, it is a general purpose TTL
output which is asserted if the AREDB/ AGP1 input is
asserted when the corresponding character dot data is
loaded into the video shift register.

DOT CLOCK (DCLK)
This dot frequency input controls the video output shift
rate.
CHARACTER CLOCK (CCIi()
This output is a submultiple of DCLK. The period ranges
from seven to ten DCLK periods per cycle and is determined
by the state of the character clock control (CO-C1) inputs.

LUMINANCE/GENERAL PURPOSE 2 (LUM/GP2)
In color mode, this output is the logical OR of the RGB

3-124

MC2675

CURSOR MODE (CMODE)

foreground video. It is low during a blanking interval and during the foreground portion of the cursor display. In monochrome mode, it is a general purpose TTL output which is
asserted if the ABlUEB/ AGP2 input is asserted when the
corresponding character dot data is loaded into the video
shift register.

Used in color mode only. When CURSOR and CMODE are
high, the RGB outputs are driven high (white cursor). When
CURSOR is high and CMODE is low, the RGB outputs are
logically inverted (reverse video cursor).
UNDERLINE ATTRIBUTE (AUl)

UNDERLINE TIMING (Ul)

Indicates the scan line(s) for the underline attribute.
Latched on the falling edge of BLANK.

Specifies a line to be displayed in the character block. The
specific line(s) are specified by the U l input. All other attributes apply to the underline video.

BLINK TIMING (BLINK)

BLINK ATTRIBUTE (ABLlNK)

This input is sampled on the falling edge of BLANK to provide the blink rate for the blink attribute. Should be a submultiple of the frame rate.

In color mode, this active high input will drive the foreground RGB combination to the background RGB combination. In monochrome mode, the associated character or
background is driven to the intensity determined by BKGND,
reverse video attribute, and the cursor input.

SCREEN BLANK (BLANK)

When high, this input forces the video outputs to the
specified background color in color mode and to the level
specified by the BKGND input (either black or gray) in monochrome mode.

DOUBLE WIDTH ATTRIBUTE (ADOUBLE)

This active high input causes the associated character
video to be shifted out of the serial shift register at one-half
the dot frequency (DCLK). The CClK output is not affected.

RETRACE BLANK (RBLANK)

This input is used to force the video outputs to a low during retrace periods. If pulled high, it will automatically suppress video during the retrace periods when BLANK is high.
The user may also pulse this input while BLANK is high to
selectively suppress raster video.

RED BACKGROUND/GENERAL PURPOSE ATTRIBUTE 1
(AREDB/ AGP1)

In color mode, this input activates the RED/TTlVl output
during the background portion of the associated character
block. In monochrome mode, it activates the GREEN/GPl
output for the associated character block

GREEN FOREGROUND/BACKGROUND INTENSITY
(AGREENF/ BKGND)

BLUE BACKGROUND/GENERAL PURPOSE ATTRIBUTE 2
(ABLUEB/ AGP2)

In color mode, this input activates the GREEN/GPl output
during the foreground (character video) portion of the associated character block. In monochrome mode, this input
specifies gray or black screen background.

In color mode, this input activates the BlUEITTLV2 output during the background portion of the associated character block. In monochrome mode, it activates the
lUM/GP2 output for the associated character block.

BLUE FOREGROUND/BLANK ATTRIBUTE
(ABLUEF/ ABLANK)

GREEN BACKGROUND/REVERSE VIDEO ATTRIBUTE
(AGREENB/ ARVID)

In color mode, this input activates the BlUEITTlV2 output during the foreground (character video) portion of the
associated character block. In monochrome mode, this input
generates a blank space for the associated character. The
blank space intensity is controlled by the AG REEN F/ B K GN D
input, the reverse video attribute and cursor input.

In color mode, this input activates the GREEN/GPl output
during the background portion of the associated character
block. In monochrome mode, it causes the associated character block video intensities to be reversed.

RED FOREGROUND/HIGHLIGHT ATTRIBUTE
(AREDF/ AHIL T)

DOT DATA INPUT (00-08)

These are parallel inputs corresponding to the character/
graphic symbol dot data for a given scan line. These inputs
are strobed into the video shift register on the trailing (falling)
edge of each character clock (CClK).

In color mode, this input activates the REDITTlVl output
during the foreground (character video) portion of the associated character block. In monochrome mode, this input
highlights the associated character (including underline).

CHARACTER CLOCK CONTROL (CO-Cl)

CURSOR TIMING (CURSOR)

The states of these two static inputs determine the internal
divide factor for the CClK output rate.

This input provides the timing for the cursor video. In color
mode, with CURSOR and CMODE high, the RGB outputs
are driven high (white cursor). If CMODE is low, or in monochrome mode, this input reverses the intensities of the video
and attributes. Cursor position, shape, and blink rate are
controlled by this input.

RESET (RESET)

This active high input initializes the internal logic and
resets the attribute latches.

3-125

I

MC2675

MONOCHROME/COLOR MODE (M/C)
This input selects whether the CMAC operates in monochrome or color mode. A low selects color mode and a high
selects monochrome mode.
DOT MODULATION ATTRIBUTE (ADOTM)
When DOTM and this input are high, the active dot width
of the associated character video is one DCLK. When DOTM
is high and this input is low, the active dot width of the
associated character video is two DCLKs.
DOT WIDTH MODULATION (DOTM)
When this input is high, two DCLKs are used for each dot
shifted through the shift register. When this input is low, one
DCLK is used.

I

DOT STRETCHING (DOTS)
This input is sampled at the falling edge of BLANK. When
this input is high, one extra dot is appended to individual
dots or groups of dots of the input parallel data and then
transferred through the shift register. When this input is low,
normal transfer of input parallel data results.

FIGURE 2 -

FUNCTIONAL DESCRIPTION
The CMAC consists of seven major sections (refer to the
block diagram). The high speed dot clock input is applied to
a programmable divider to provide a character clock output
for system timing. Parallel dot data is loaded into the video
shift register on character boundaries and shifted into the
video logic block at the dot rate specified by the dot modulation section. The appropriate attribute control inputs are
selected by the mode select logic, latched internally on character boundaries, and combined with the serial dot data to
provide monochrome or color video outputs. System block
diagrams of the MC2675 in color mode and monochrome
mode are provided in Figures 2 and 3.
The BLANK input defines the active screen area. In color
mode, the video outputs are forced to the specified background color when this signal is asserted; in monochrome
mode the video outputs are forced to the states defined by
the BKGND input, i.e., black if dark background is selected
and gray if light background is selected. A separate RBLANK
input allows the user to select the amount of border around
the active area when operating in color mode or in
monochrome mode with light background. This input can be

SYSTEM BLOCK DIAGRAM OF MC2675 IN COLOR MODE

R
Character
RAM

G

B }Mom,m

LUM
(/)

~

"0
"0
<{

>co

~
£5

Attribute
RAM

MC2675

FIGURE 3 -

SYSTEM BLOCK DIAGRAM OF MC2675 IN MONOCHROME MODE

TTLV1}
Monitor
TTLV2

MC2670
Character
Generator

Character
RAM
(f)
(f)

(J)

:g

}

MC2675
CMAC

<{

General
Purpose
Outputs

>co

~

0

I

Attribute
RAM

tied high, in which case the area outside the active area will
be dark, or it may be pulsed during BLANK periods to externally control the border widths.
In color mode, eight colors for the character (foreground)
and eight colors for the background (area other than
character) can be selected by the attribute inputs. In monochrome mode, the intensities of foreground and background
are a function of the attribute and BKGND inputs, i.e., characters may be black, gray, white, or highlight (very white)
while background may be black, gray, or white (see Table 1).

TABLE 1 -

REV*
0
0
0
0
1
1
1
1

CHARACTER CLOCK COUNTER
The character clock counter divides the DClK input to
generate the character clock (CClK). The divide factor is
specified by the clock control inputs (Cl-Co) as follows:

MONOCHROME MODE ATTRIBUTE
CHARACTERISTICS

AHllT ABLlNK**
0
0
1
1
0
0
1
1

CClK
Duty
Character Cycle*

Dotsl

C1

CO

0
0
1
1

0
1
0
1

10
7

8
9

5/5
4/3
4/4
5/4

Background
Video

W
WIG

B
B
B
B
G
G/B
W
W/B

0
1
0
1
0
1
0
1

H
H/W
B
B/W
B
B/H

*REV=(BKGNO) XOR (AVRIO):
BKGND

ARVID

.fIDl

000
1
o

o

MC2675B

Foreground
Video

1

o

MC2675C

* * For blinking, the video outputs are shown as zerolone, where
zero and one are the blink timing input states.

CClK
Duty
Character Cycle*
10
5/5
6
313
8
4/4
9
5/4

Dotsl

NOTES:
1. Foreground includes underline when underlining is specified by
AUL=l.
2. When ABLANK = 1, foreground component becomes same as
background component.
3. Codes for video outputs are as follows:

*Hlgh/low

Code

TTL V2

B

0

G

0

W
H

3-127

TTlVl

o

Beam Intensity
Black
Gray
White
Highlight

MC2675

The number of dot clocks/character is normally the
number of dots/character as listed above. However, when
dot width control is specified, the OCLK input is divided by
two before it is applied to the character clock counter
resulting in the number of dot clocks/ character being double
those listed above, although the number of displayed dots/
character remains the same. See DOT MODULATION
LOGIC.

I

intensities (black, gray, white, and highlight) which are encoded on the TTLV1 and TTLV2 outputs as follows:
TTLV2
0
0

VIDEO SHIFT REGISTER
On each character boundary, the parallel input dot data
(D0-08) is loaded into the video shift register. The data is
shifted out least significant bit first (DO) at the OCLK rate. If
ten dots/character are specified (C1-CO=00), the tenth dot
will be the same as 08. The serial dot data from the video
shift register is routed to the video logic where it is combined
with the cursor and attribute control bits to produce the
video data outputs.

FIGURE 4 -

TTLVl
0
1
0
1

Video Intensity
Black
Gray
White
Highlight

CHARACTER BLOCK DEFINITION

Symbol
Video
Background
Video

MODE SELECT, ATTRIBUTE, AND CURSOR CONTROL
The mode select logic multiplexes the monochrome and
color attribute inputs and outputs as specified by the M/ C input. The monochrome mode provides blank, reverse video,
highlight, and two general purpose attributes. The latter may
be used, with external logic, to combine other attributes
(e.g., overscore) into the video stream. The color mode provides RGB foreground and background color attributes.
Both modes provide double width characters, blink, underline, dot width control, and dot stretching.
The cursor and attribute inputs are pipelined internally to
allow for system pipeline propagations. The cursor input
Signal is delayed internally by two CCLKs (one for RAM and
one for the character generator), while the attribute inputs
are delayed for one CCLK to account for the delay of the
character data through the character generator latches. The
attribute timing inputs (BLINK, UL, and DOTS) are clocked
into the MC2675 at the beginning of each scan line time by
the falling edge of BLANK. Thus, these inputs must be their
proper state at the falling edge of BLANK preceding the scan
line where they are required to be active. The BLANK signal
itself is also delayed internally to provide for the RAM and
character generator delays. Internal delays cause the video
outputs to be delayed relative to CCLK.

Underline
Video

Table 1 describes the relationship between attributes and
video intensity of the foreground and background components of the character block in monochrome mode.
In color mode, the colors of the foreground and background components are specified by the corresponding attribute inputs; AREDF, AGREENF, and ABLUEF dictate the
color of the foreground components while AREOB,
AGREENB, and ABLUEB do the same for the background
component. In this mode, the serial dot data and pipelined
cursor and attributes are combined to generate four video
outputs. The RED, GREEN, and BLUE outputs separately
contain the corresponding foreground and background components. The LUM output is the logical OR of the foreground colors and can be used to drive a separate monochrome monitor or to select a different set of colors for the
foreground.
DOT MODULATION LOGIC
The dot modulation logic controls the video shift register
to supply dot stretching and dot width control.
Dot stretching is controlled by the DOTS input which is
sampled each scan line at the trailing (falling) edge of
BLANK. If DOTS is asserted at that time, all characters on
the following scan line will have dot stretching applied. Dot
stretching causes an extra dot to be added to individual dots
or groups of dots as shown in Figures 5 and 6. Dot stretching
can be used to:
1. Compensate for low video backwidth monitors (since
the minimum active displayed segment with dot
stretching is two OCLKs).

VIDEO LOGIC
Each character block consists of the three components
shown in Figure 4. Symbol video is generated from the dot
data inputs 00-08. Underline video is enabled by the AUL
attribute and is generated during the scan lines for which the
UL input is active. Underline and symbol video are always
the same intensity or color, and other attributes (e.g.,
ABLlNK) apply to them equally. The combination of underline and symbol video is also referred to as foreground video.
Background video is the area of the character block corresponding to the absence of foreground video. The assertion
of the non-display attribute (ABLANK) causes the entire
character block to be displayed as background.
In monochrome mode, the serial dot data and pipelined
cursor and attributes are combined to generate four video

2. Assure crisp black characters when operating in white
background mode.
3. Provide thick characters as a means of distinguishing
areas of the display.

3-128

MC2675

FIGURE 5 -

DOT MODULATION TIMING

Dot Stretching
Dot Clock
Normal
Stretched

Normal
Stretched

Dot Clock
Width
ADOTM=O
Width
ADOTM=1

Width
ADOTM=O
Width
ADOTM= 1

---II
---.-..J

•

•-

Displayed on Monitor

Dot Width Control

II

---.-..J

Displayed on Monitor

•

-

FIGURE 6 -

• • •

DOT STRETCHING

Character as Stored
in Character Generator

Actual Character Displayed
with Dot Stretching Employed

A
Dot width is controlled by the DOTM and ADOTM inputs.
DOTM is tied either high, which enables the features on the
entire display, or low, which disables the feature. With
ADOTM high, the dot width of characters can be selectively
controlled by assertion of the ADOTM attribute input. When
operating in this mode, the dot clock input is divided by two
before being applied to other circuits in the CMAC. This affects the CClK output.
When dot width control is enabled as above, two DClKs
are used for each video dot period. Asserting ADOTM for a
particular character will cause each active video dot of the
displayed character to be turned on for one DClK and off for
the other DClK, while if ADOTM is negated for that character, the active video dot for that character will be turned on

(black background) or off (white background) for both DClK
times (see Figures 5 and 7). Only the character video components of the character block are modulated. Underline
video and background are not affected by on-time modulation. Width control can be used to:
1. Make horizontal lines and vertical lines appear the same
brightness on the display.
2. Provide two different brightness levels for characters
without requiring a monitor with analog brightness
inputs.
However, note that the effects produced by this feature are
highly dependent on the video amplifier characteristics of the
monitor used.

3·129

MC2675

FIGURE 7 ~ DOT WIDTH CONTROL

I

Normal Character Display
Without Width Control

Actual Character Display
with Width Control

E

E

DOUBLE WIDTH LOGIC
The double width logic controls the rate at which dots are
shifted through the video shift register. When the ADOUBLE
input is asserted, the associated character video will be
shifted at one half the DClK rate, and the dot information

for the next character will be loaded into the shift register
two CClKs later. The CClK output is not affected. If a
double width character is specified at the last location of a
character row, the second half of the double width character
(one CClK) will extent into the horizontal front porch.

3·130

i

®

MC3440A
MC3441A
MC3443A

MOTOROLA

QUAD INTERFACE
BUS TRANSCEIVERS

QUAD GENERAL-PURPOSE INTERFACE
BUS (GPIB) TRANSCEIVERS

SILICON MONOLITHIC
INTEGRATED CIRCUITS

The MC3440A, MC3441 A, MC3443A are quad bus transceivers
intended for usage in instruments and programmable calculators
equipped for interconnection into complete measurement systems.

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

These transceivers allow the bidirectional flow of digital data and
commands between the various instruments. Each of the transceiver
versions provides four open-collector drivers and four receivers
featuring input hysteresis.
The MC3440A version consists of three drivers controlled by
a common Enable input and a single driver without an Enable input.

Output and
Termination ....
Gnd

Receiver
Output A

The MC3443A is identical to the MC3441 A except that the terminations have been omitted. As such it is pin compatible, and
functionally equivalent to the SN75138. It does offer the advantage
of receiver input hysteresis.
•

Receiver Input Hysteresis Provides Excellent Noise Rejection

•

Open-Collector Driver Outputs Permit Wire-OR Connection

•

Tailored to Meet the Standards Set by the IEEE and IEC
Committees on Instrument Interface (488-1978)

•

Terminations provided (except MC3443A version)

•

Provides Electrical Compatibility with General-Purpose
Interface Bus

Bus C

Bus A

Terminations are provided in the device.
The MC3441A differs in that all four drivers are controlled by
the common Enable input_ Again, the terminations are provided.

Receiver
Output C

Driver
Input A

Driver
Input C

Driver
Input B

Enable E
Driver
Input D

Receiver
Output B

Receiver
Output D

Bus B
Logic Gnd

Bus D

~

Output and
Termination ....
Gnd
Bus C

Bus A

MAXIMUM RATINGS

iT A = 25°C unless otherwise noted)

Ratong

Symbol

Power Supply Voltage
Input Voltage
Oliver Output Current
Power DiSSipation (Package Limitation)

Value

Unit

VCC

7.0

Vdc

VI

5.5

Vdc

10(0)

150

mA

Po

830

mW

6.7

mW/oC

Derate above 25°C
Operating Ambient Temperature Range

TA

Storage Temperature Range

T stg

o to

+ 70

°c

-65 to +150

Receiver
Output A

Receiver
Output e

Driver
Input A

Driver
Input e

Driver
Input B

Enable E
Driver
Input D

Receiver
Output B

Receiver
Output D

Bus B

°c
Logic Gnd

Bus D

~

TYPICAL APPLICATION - GPIB MEASUREMENT SY·STEM

Vce

Output Gnd

BusC

Bus A

Instrument

A

Receiver
Output A

(with GPIB)

Programmable
Calculator
(with GPIB)

Receiver
Output C

Driver
Input A

Driver
Input C

Driver
Input B

Enable E
Driver
Input D

Receiver
Output B

Instrument

B
(with GPIB)

Bus B

~

Logic Gnd

..

Receiver
Output D

- T - = Bus
Termination
16 Lines Total

3·131

~

Bus D

I

MC3440A, MC3441A, MC3443A

ELECTRICAL CHARACTERISTICS (Unless otherwise noted, 4.5 v,;; VCC';; 5.5 V and 0,,;; T A";; 70 0 C, lYpical values are at
T A = 25 0 C, VCC = 5.0 VI
Char acter istic

Symbol

Min

Typ

Max

Input Voltage - High Logic State

VIHIDI

2.0

V

VILIDI

-

-

-

Input Voltage - Low Logic State

O.B

V

IIHIDI

-

40

JJA

IILIDI

-

-

-1.6
-0.25

mA

VIK(DI

-

-

-1.5

V

VOHIDI

2.5

-

-

V

-

-

-

0.5
O.BO

-

250

JJA

mV

Unit

DRIVER PORTION

Input Current
IVIH

High Logic State
2.4 VI

Input Current .- Low Logic Stdte
IVIL O.4V.VCC
I nput Clamp Voltage
(11K = -12 mAl

MC3443A

5.0 V. TA

25 0 CI

M C3440A, 3441 A

Output Voltage -- High Logic State 111
(VIH(E) = 2.4 V or VIL(O) = 0.8 V)

(MC3440A, 3441

A onlyl

Output Voltage - Low Logic State

(VIH(O)
(VIH(O)

I

=
=

2.0 V, VIL(E)
2.0 V, VIL(E)

=
=

0.8 V, IOL(O)
0.8 V, IOL(O)

48 mAl
100 mAl

Output Leakage Current - MC3443A Only
IVIHIEI

2.0 V or VILIDI

V

VOLIDI

=
=

IOHIOI

DB \II

RECEIVER PORTION
I npu t HysteresIS
Input ThreshOld Voitage _. Low to High Output Logic S,ate
IVCC

5.0 V, T A

580

0.8

0.98

-

VI HLIRI

-

1.56

2.0

V

VOHIRI

2.4

-

-

V

-

0.5

V

-

-55

mA

V

0

25 CI

Input Threshold Voltage - High to Low Output Logic State
IVCC ~ 5.0 V. T A 25 0 CI
Output Voltage _. High Logic State
IVILIRI

400
VILHIRI

OBV.IOHIRI

-400jJAI

O"tpu t Voltage - Low Logic State
(VIHIRI. 20 V. IOLIRI

VOLIRI

16 mAl

Output Short·Crrcult Current
(VILIRI c O.B VI IOnly one output may be shorted at a tlmel

-20

IOSIRI

BUS TERMINATION PORTION (Does not apply to MC3443A)
Bus Voltage (VILIDI = 0.8 VI

-1.5
2.50

Bus Current
(VILIDI = O.B
(VIL(DI = O.B
(VIL(DI = 0.8
(VCC = 0,0';

V

VBUS

IIBUS = -12 mAl
(No Loadl

3.70
mA

IBUS
V, VBUS? 5.0 VI
V. VBUS ~ 5.5 VI
V, VBUS = 0.5 VI
VBUS";; 2.75 VI

0.7
2.5
-3.2
+0.04

-1.3
(MC3440A, 3441 A only)

TOTAL DEVICE POWER CONSUMPTION
Power Supply Current
iVIH(DI ~ 2.4 V. VILIEI

0 VI

SWITCHING CHARACTERISTICS (VCC = 5.0 V. TA

25 0 CI

Characteristic
DRIVER PORTION
Propagation Delay Time from Driver I nput to Low Logic State Bus Output

tPHLIDI

-

13

30

-

13

25

ns

Propagation Delay Time from Driver Input to H'9h Logic State Bus Output

tPLHlD1

-

17

30

-

17

25

ns

Propagation Delay Time from Enable Input to Low Logic State Bus Output

tPHLIEI

-

25

40

--

25

32

ns

Propagation Delay Time from EnabJ-e I nput to High Logic State Bus Output

tPLHJJ~l

-

25

40

-

25

32

ns

RECEIVER PORTION
Propagation Delay Time from Bus I nput to High Logic State Receiver Output
Propagation Delay Time from Bus Input to Low Logic State Receiver Output
(1) 12 k resistor from the bus terminal to V CC required on the MC3443A version.

3-132

MC3440A, MC3441 A, MC3443A

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER INPUT (BUS) TO OUTPUT
To Scope
(Output) +5.0 V
Input

50%

To Scope
(Input)

OV

VOH
Output

~

tPLH(R)

1.5 V

15 pF

vOL--------~-----------------~

or equiv
Input

Pulse

I

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)
3.0V - - -

tv

OV
To Scope
(Input)

3.0 V

+5.0 V

VOH
Output
VOL

50%

50%

Pulse
OV

F

150 pF

Input

_____________CtPHL(E)

VO H
Output
VOL

FIGURE 3 - TYPICAL RECEIVER HYSTERESIS
CHARACTER ISTICS
50

I
~I- Vee ~ 5.0 V ---t----+------t----+--------t-------1

~a

TA

4.0

~

25 0 e

I==+==+=~==:j::::;i=+~:::::j:=,r__I

>

~

30 r-----+----t------t-----i-t---t----f---±----t-----I

~

2.0 r-----+----t------t-----t-"I''---t-----f---+----t-----I

>a

::>

~ 1.0 r-------t----+----+----t--f-----t-----t---t---t--------1

OL-__

o

~

____

~

0.5

__

~

____'--__

~

___'--__

1.0
VI. INPUT VOLTAGE (VOLTS)

3·133

1.5

~

__

~

2.0

1.5 V

MC3440A, MC3441A, MC3443A

GENERAL PURPOSE JNTERFACE BUS APPLICATION
INSTRUMENT B

INSTRUMENT A

-l

----

I
I

MC3441A

-- -0101

:

0102

0102

I

0103

0103

I

I

0104

REN

I

MC3441A

(Always

I

Enabled)

I
I

I

MC3441A

\.

\.

E

---

SRO

0108 ~
\.

(Always
Enabled)

I
REN J

0107

J

0108

I

ATN J

DAV

I

IFC )

I
1
I
I
I

-...

EOI

-...
-...

EOI

\.

(Always
Enabled)
(Always
(Always

Enabled)

Enabled)

I

SRO ~

ATN

,-1

DAV)

IFC

I
I
I
I

I

I
I

~

t4I
I
I

I

Instruments
Lo gic (Typical)

To

I

I

I

44-

MC3440A

I

I

I

,

1

MC3440A

0106

0107 )

1

I

0105

0106 )

I
I
I

I
MC3440A

I

I

I

0104

01051

I
I

I"

I

I

I

----

I

0101

T

I

1-

-...

NRFD

NRFD

NDAC

NDAC

I

!

~
I

MC3440A

2tI
I

I

+
2-fI

MC3440A

I
I

I
- - -.J

---If 16 Lines
Total

I
L

I
-- ---

GPIB SIGNA LS:
8 Line Data Bus:

0101 -

0108

5 General Interrupt Transfer Control Bus:
REN - Remote Enable
SRO -' Service Request
EOI - End or Identify
ATN - Attention
I FC - Interface Clear

3-134

3 Data Byte Transfer Control Bus
DAV - Data Valid
NRFO - Not Ready for Data
NOAC - Not Data Accepted
16 Total Signal Lines

E

®

MC3446A

MOTOROLA

QUAD GENERAL-PURPOSE INTERFACE
BUS (GPIB) TRANSCEIVER

QUAD INTERFACE
BUS TRANSCEIVER
SI LICON MONOLITH IC
INTEGRATED CIRCUIT

The MC3446A is a quad bus transceiver intended for usage in
instruments and programmable calculators equipped for interconnection into complete measurement systems. This transceiver allows the
bidirectional flow of digital data and commands between the various
instruments. The transceiver provides four open-collector drivers and
four receivers featuring hysteresis.
•

Tailored to Meet the IEEE Standard 488-1978 (Digital Interface
for Programmable Instrumentation) and the Proposed IEC

•

Provides Electrical Compatibil ity with General-Purpose Interface
Bus (GPIB)

•

MOS Compatible with High Impedance Inputs

•

Driver Output Guaranteed Off During Power Up/Power Down

I

Standard on Instrument Interface

•

Low Power - Average Power Supply Current

•

Terminations Provided

~

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

12 mA

l

PIN CONNECTIONS
TYPICAL MEASUREMENT SYSTEM APPLICATION
Receiver

....

Output A
Receiver
Output 0

Bus A

-

I

Instrument
A
(with GPIB)

I

Bus 0

w

Driver

Enable
ABC

I

Driver
Input B

~.

Instrument
B
(with GPIB)

Driver
Input A

- --

J

Programmable
Calculator
(with GPIB)

I

Input 0

Driver
Input C

Bus B

I

Receiver
Output B

~

---- T - = Bus Term ination

3·135

Bus C

....

Gnd

16 Lines Total

Enable 0

(.II

Receiver
Output C

MC3446A
MAXIMUM RATINGS

(T A= 25°C unless otherwise noted )

Rating

Symbol

V .. ue

Unit

VCC

7.0

Vdc

VI

5.5

Vdc

Driver Output Current

10(0)

150

mA

Junction Temperature

TJ

150

°c

Operating Ambient Temperature Range

TA

o to +70

°c

Power Supply Voltage
Input Voltage

Storage Temperature Range

~5

T stg

to +15Q

°c

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, 4.5 V,;; VCC'; 5.5 V and 0.; T A'; 70°C, typical values are at TA = 25 0 C, Vee = 5.0 V)
Symbol

Min

Typ

Input Voltage - High Logic State

VIHIDI

2.0

-

-

V

Input Voltage - Low Logic State

VILlD)

-

-

0.8

V

Input Current - High LOijic State
(VIH=2.4V)

IIH(D)

-

5.0

40

IJA

IILlD)

-

-0.2

-0.25

mA

VIK(D)

-

-

VOHID)

2.5

VOLlD)
IIB(D)

Character istic

Max

Unit

DRIVER PORTION

I

Input Current - Low Logic State
(VIL = 0.4 V, VCC

= 5.0

V, TA

= 25 0 CI

Input Clamp Voltage
(11K = -12 mAl
Output Voltage - High Logic State (11
(VIH(S) = 2.4 V or VIH(D)

= 0.8

V

3.3

3.7

V

-

-

0.5

-

-

1.0

mA

= 2.0 V)

Output Voltage - Low Logic State
(VILISI

-1.5

V, VILlD) = 0.8 V, IOLlD) ~ 48 mAl

Input Breakdown Current
(VI(D) = 5.5 V)
RECEIVER PORTION

-

400

625

-

mV

Input Threshold Voltage - Low to High Output Logic State

VILH(R)

-

1.66

2.0

V

Input Threshold Voltage - High to Low Output Logic State

VIHLlR)

0.8

1.03

-

V

Output Voltage - High Logic State

VOH(R)

2.4

-

-

V

Output Voltage - Low Logic State
(VILlR) = 0.8 V, IOLlRI = 8.0 mAl

VOLlR)

-

-

0.5

V

Output Short·Circuit Current
(VIH(RI = 2.0 V) (Only one output may be shorted at a timel

IOS(RI

4.0

-

14

mA

(VIH(E) = 24 V)
(IBUS=-12mAI

V(BUSI

25

3.3
-

3.7
-1.5

V

-

(VIH(OI= 2.4 V, VBUS;",5.0 V)
(VIH(DI = 2.4 V, VBUS = 0.5V)
(VBUS'; 5.5 VI
(Vec = 0, 0 V.; VBUS'; 2.75 V)

I(BUS)

0.7
-1.3

-

-

mA

-

-

-

-3.2
2.5

-

-

0.04

Input Hysteresis

(VIH(R) = 2.0 V, IOH(R) = -4001JAI

BUS LOAD CHARACTERISTICS
Bus Voltage
Bus Current

TOTAL DEVICE POWER CONSUMPTION
Power Supply Current
(All Drivers OFF)
(All Drivers ONI

SWITCHING CHARACTERISTICS

(VCC = 5.0 V, TA

=

25 0 CI

Characteristic
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic State Bus Output

tPHLlD)

-

-

50

ns

Propagation Delay Time from Driver Input to High Logic State Bus Output

tPLHID)

-

40

ns

Propagation Delay Time from Enable Input to Low Logic State BusOutput

tPHL(E)

-

-

50

ns

Propagation Delay Time from Enable Input to High Logic State BusOutput

tPLH(E)

-

-

50

ns

RECEIVER PORTION
Propagation Delay Time from Bus Input to High Logic State Receiver Output
Propagation Delay Time from Bus I nput to Low Logic State Receiver Output

3·136

MC3446A

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER INPUT (BUS) TO OUTPUT
To Scope
(Output)
Input

+5.0 V

To Scope

ov

(Input)

Output

VOL

Input

Pulse

I

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)

To Scope

+5.0 V

(Input)

Pulse

VOH
Output

-----J'r--,..------1.5 V

VOL----·
Input

.. Includes Probe and Jig Capacitance

FIGURE 4 - TYPICAL BUS LOAD LINE

FIGURE 3 - TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS
5.0

~

40

I
- - Vee ~ 5.0 V
TA ~ 25 0 e

60

-+--+----+--[----+---1

40

1---t--!-T-~==::j::::;o;jjjH==::j::=~

20

~

I
-

f----- I - -

-_._(---

5

~

:z
a:

30 r----+--t-----t--:i:-1--+----t----t-------j

S; 2.0 \----+--1----+--+--1--+---+---+----1

{

=> -40
=>

~

l-

=>

~

20

10 r - - - - + - - t - - - - 1lc --+---t---t--+----t-----I

I
I
I
I
II

-60
-80
10
12

O~

o

__

_ L_ _ _ _~ _ _~ _ _~ _ _ _ _~ _ _~ _ _ _ _~ _ _~

0.5

10

15

14
-4.0

2.0

-2.0

--

I

I

~

3·137

I

J

Non-Shaded Area

-

eont~r~~ ~Ot ~~r~raph _
Standard 4881978

I I
20

VBUS, BUS VOLTAGE (VOLTS)

VI. INPUT VOLTAGE (VOLTS)

..... ~ ~

I
40

_

I
6.0

®

MC3447

MOTOROLA

OCTAL BIDIRECTIONAL
BUS TRANSCEIVER

BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER

WITH

This bidirectional bus transceiver is intended as t~e interface
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus (488-1978, often referred to as GPIB). The required bus termination is internally provided.

TERMINATION NETWORKS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

Low power consumption has been achieved by trading a minimum
of speed for low current drain on non-critical channels. A fast

I

channel is provided for critical ATN and EOI paths.
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of each
channel is enabled by a Send/Receive input with the disabled output
of the pair forced to a high impedance state. The receivers have
input hysteresis to improve noise margin, and their input loading

L SUFFIX
CERAMIC PACKAGE
CASE 623-05

follows the bus standard specifications.
Low Power - Average Power Supply Current

•
•
•
•
•

Eight Driver/Receiver Pairs
Three-State Outputs
High Impedance Inputs
Receiver Hysteresis - 600 mV (Typ)
Fast Propagation Times - 15-20 ns (Typ)

•
•
•
•

TTL Compatible Receiver Outputs
Single +5 Volt Supply
Open Collector Driver Output with Terminations
Power Up/Power Down Protection (No Invalid
Information Transmitted to Bus)
No Bus Loading When Power is Removed From Device
Required Termination Characteristics Provided

•
•

MAXIMUM RATINGS

P3 SUFFIX
PLASTIC PACKAGE
CASE 724-02

= 30

•

mA Listening
75 mA Talking

PIN ASSIGNMENTS

IT A = 25 0 C unless otherwise noted)
Symbol

Value

Unit

VCC

7.0

Vdc

VI

5.5

Vdc

Driver Output Current

1010)

150

mA

Junction Temperature

TJ

150

Operating Ambient Temperature Range

TA

o to +70

Storage Temperature Range

[stg

-65 to +150

°c
°c
°c

Rating
Power Supply Voltage
Input Voltage

I

-

Instrument

A

--

-

---

I

(With GPIB)

----

l

Instrument

B
(With GPIB)

I

TYPICAL MEASUREM ENT
SYSTEM APPLICATI ON

r "o,,,mm,""

1
1

Calculator
(With GPIB)

I

----

41

Vee

~Bus -Indicates~us
~

- --

16 Lines Total

Gnd

3-138

~ Terminatwns

MC3447
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted 4.50 V..;, Vcc ..;, 5.50 V and 0 ..;, T A";' 70 0 C; typical values are at T A

Characteristic - Note 2

= 25 0 C,

VCC

= 5.0 V)

Symbol

Min

Typ

Max

V(Bus)

2.5

VIC(Bus)

-

-

3.7
-1.5

-

Bus Voltage

Unit
V

(Bus Pin Open)(VI(S/A) = 0.8 V)
(I(Bus) = -12 rnA)
Bus Current
(5.0 V";' V(Bus) ..;, 5.5 V)

rnA

I(Bus)

0.7
-1.3
-

-

2.5
-3.2
+0.04

-

400

600

-

VILH(R)
VIHL(R)

-

1.6
1.0

2.0

(V(Bus) = 0.5 V)
(VCC = 0 V, 0 V..;, V(Bus)";' 2.75 V)
Receiver Input Hysteresis

-

mV

(VI(S/R) = 0.8 V)
Receiver Input Threshold

V

(VI(S/A) = 0.8 V)

Low.to High
High to Low

Receiver Output Voltage - High Logic State

VOH(R)

0.8
2.4

-

-

-

V

-

0.5

V

-20

rnA

(VI(S/A) = 0.8 V, 10H(R) = -200 !J.A, V(Bus) = 2.0 V)
Receiver Output Voltage - Low Logic State

VOL(R)

-

(V I(S/A) = 0.8 V, 10L(R) = 4.0 rnA, (V (Bus) = 0.8 V
Receiver Output Short Circuit Current

10S(R)

-4.0

-

VIH(O)

2.0

-

(VI(SIR) = 0.8 V, V(Bus) = 2.0 V)
Driver Input Voltage - High Logic State

-

V

(VI(S/A) = 2.0 V)
Driver Input Voltage - Low Logic State

VIL(D)

-

-

0.8

11(0)

-100

-

IIB(D)

-

-

40
200

II(S/R)
IIB(S/A)

-250
-

-

20
100

VIC(D)

-

-

-1.5

2.5

-

V

(VI(S/R) = 2.0 V)
Driver Input Current - Data Pins

IJA

(VI(S/A) = 2.0 V)
(0.5";' VI(O)";' 2.7 V)
(VI(D) = 5.5 V)
Input Current - Send/Receive

IJA

(0.5";' VI(S/R) ..;, 2.7 V)
(VI(S/R) = 5.5 V)
Driver Input Clamp Voltage

V

(VI(S/R) = 2.0 V,IIC(D) = -18 rnA)
Driver Output Voltage - High Logic State

VOH(D)

-

V

(VISIR) = 2.0 V, VIH(D) = 2.0 V)
Driver Output Voltage - Low Logic State (Note 1 )

VOL(D)

-

-

0.5

ICCL
ICCH

-

30
75

45
95

7.0
16

15
30

28
15

50
30

17
12

30
22

V

(VI(S/R) = 2.0 V, VIL(D) = 0.8 V, 10L(D) = 48 rnA)
Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)

SWITCHING CHARACTERISTICS

rnA

-

(VCC = 5.0 V, T A = 25 0 C unless otherwise noted)

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)

tPLH(D)
tPHL(D)

-

Propagation Delay of Receiver (Channels 0 to 5, 7)
(Output Low to High)
(Output High to Low)

tPLH(R)
tpHL(R)

-

Propagation Delay of Receiver (Channel 6, Note 3)
(Output Low to High)
(Output High to Low)

tpLH(R)
tpHL(R)

-

NOTES:

ns
-

ns
-

ns
-

1. The IEEE 488-1978 Bus Standard changes VOL(D) from 0.4 to 0.5 V maximum to permit the use of Schottky technology.
2. Specified test conditions for V I(S/A) are 0.8 V (Low) and 2.0 V (H igh). Where V I (S/A) is specified as a test condition, V I (S/R)
uses the opposite logic levels.

3. In order to ,neet the IEEE 488-1978 standard for total system delay on the ATN and EOI channels, a fast receiver has been
provided on Channel 6 (pins 9 and 16).

3-139

I

MC3447

SWITCHING CHARACTERISTICS (continued) (Vee = 5 0 V T A = 25 0 e unless otherwise noted)
Symbol

Min

Typ

Max

Propagation Delay Time - Send/Receiver to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low

tpHZ(R)
tpZH(R)
tpLZ(R)
tPZL(R)

--

15
15
15
10

30
30
25
25

Propagation Delay Time - Send/Receiver to Bus
Logic Low to Third State
Third State to Logic Low

tpLZ(D)
tpZL(D)

-

13
30

25
50

Characteristic

Unit
ns

ns

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

To Scope
(Output)

+ 5.0 V

3.0 V

~':RV

Input

I

1.5 V

To Scope

1 k
)ata

( input)

Output

lN916
or Equiv.
tTLH = tTHL '" 5.0 ns (10-90)
Duty Cycle

~

50%
Pulse

Send/

Generator

Rec

'Includes Jig
and Probe Capac Ita nee

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)
3.0 V

To Scope
( Input)

To Scope
(Output) 3.0 V
Sendl
51
Bus

Pulse

f = 1.0 MHz
'Includes Jig

tTLH = tTHL';; 5.0 ns (10 ·90)

and Probe Capdc itance

Duty Cycle = 50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
To Scope
(Output)

Data
Send/Rec

To Scope
( Input)
Pulse
Generator

51

il"
-

Input
Output
Low to Open

3.0 V

f=1.0MHz

CL = 30 pF (Includes Jig and

tTLH = tTHL = .;; 5.0 ns (10-90)

Probe Capacitance

Duty Cycle = 50%

3·140

MC3447
FIGURE 4 - SEND/REcEiVe INPUT TO DATA OUTPUT (RECEIVER)

r-------_.----

3.0 V

Input

5.0 V

OV

To Scope
(Output)

1.2 k

zl

Output
High to Open
Output
Low to Open

600

2.0 V
51

CL = 15 pF (Includes Jig

f=1.0MHz

and Probe Capacitance)

tTLH = tTHL = .;; 5.0 ns (10-90)
Duty Cycle = 50%

FIGURE 5 - TYPICAL RECEIVER HYSTERESIS
CHARACTER ISTICS

FIGURE 6 - TYPICAL BUS LOAD LINE

5.0

6.0
4.0

~

4.0

r--- -

Vee! 5.0 V
TA = 25 0 e

2.0
.§.
>-

UJ

;'"

i3

o

>

~

~

~ -2.0

3.0

~

-4.0

Non·Shaded Area
Conforms to
Paragraph 3·5.3 of
IEEE Standard

-10

488·1978
Vee = 5.0 V

-12

o

o

0.5

1.5

1.0

I

-14
-4.0

2.0

2.0

-2.0

FIGURE 7 - SUGGESTED PRINTED CIRCUIT BOARD LAYOUT USING MC3447s AND MC68488
10

0

MC68488

o

0

2 MC3447s
A

7~~~J.,vgy

0
0
0
0
0

I

~

0

:~~

0

I

0

0.' !

: a

0
0

m7

0

VRl

0
0

OAV
OAC
RFD 0 - - - - - - '

i

0
0

~_

0---/1'

0

1~
0------/~

4

0

a

./,

,vI~:c i 'Dvcc

D"

O---SRQ
0101

~:

0---

:

/,-------0------0108

o-----~~;

I'

SIR(5)o-S/R(1-4)~

::~j ~_S/:_(6)~OI--S_/R-(_7)~~~--o---~~-~~
W I
SRQo-J.

Gnd

Gnd

Gnd

0

REN

o---~

0

iFC

Jumper or second
level metal

3·141

Gnd

-

-

I
4.0

VBUS, BUS VOLTAGE (VOLTS)

VI, INPUT VOLTAGE (VOLTS)

r-

I

~-8.0

~ 1.0

f..--

I

/~

~ -6.0

2.0

--

I

~

o
~

I

I

6.0

I

MC3447
FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
tS

v

DB0

T/R 1

r-------,

Data
T/R 2

I
2 MC3447s
DAV

D0

DB7

I
I
I

DAV

D7

R/IN

R/W

RS0

A0

MC6802
DI01

IB0
RS2

I

DI03

IB2

DIOS

IB4

DI07

IB6

MC6800
MPU

Address

A15

IRQ

IRO

NDAC

DAC

Vl

::l

In

EOI

EOT

~
cO

IFC

IFC

,..co
CO

""w

MC68488
GPIA

w

~
SRO

SRO

DI02

1s1

DI04

IB3

DI06

iB5

DI08

iB7

NRFD

NOTE 1: Although

RFD

the

MC3447

transceivers

are non·inverting, the 488·1978 bus call outs
appear inverted with. respect to the MC68488
ATN

ATN

REN

REN

L ______ ...JI

pin designations. This is because the 488-1978
Standard is defined for negative logic, while all
M6800 MPU components make use of positive
logic format.

Trig

-=

3·142

MC3447

FIGURE 9 - SUGGESTED PIN DESIGNATIONS FOR USE WITH MC68488
MC68488
Connections

MC68488
Connections

MC3447 Pin Designations

A

B

T/R 2

vcc

SIR (0)

~

A

B

VCC

VCC

vCC

oAV

SRO

Data 00

2

23

Bus 0

OAV

SRO

iB0

iB1

Data 1

3

22

Bus 1

0101

0102

iB2

183

Data 2

4

21

Bus 2

0103

0104

IB4

IB5

Data 3

5

-IB6

IB7

Data 4

6

Octal
GPIB

20

Bus 3

0105

0106

19

Bus 4

0107

0108

oAC

RFO

Data 5

7

Transceiver 18

Bus 5

NoAC

NRFo

TIR 2

TlR2

SIR (5)

8

17

SIR (1-4)

T/R 2

T/R 2

EOT

ATN

Data 6

9

16

Bus 6

EOI

ATN

iFC

REN

Data 7

10

15

Bus 7

IFC

REN

T/R 1

Gnd

SIR (6)

11

14

SIR (7)

Gnd

Gnd

Gnd

Gnd

Logic Gnd

12

13

Bus Gnd

Gnd

Gnd

I

GPIB
GPIA

Bus

MC3447
(2)

Instrument

®

MC3448A

MOTOROLA
BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER

QUAD THREE-STATE
BUS TRANSCEIVER WITH
TERMINATION NETWORKS

This bidirectional bus transceiver is intended as the interface
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus 1488-1978, often referred to as GPIB)_ The required bus
termination is internally provided_
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of each
channel is enabled by its corresponding Send/Receive input with
the disabled output of the pair forced to a high impedance state_ An
additional option allows the driver outputs to be operated in an
open collector(1} or active pull-up configuration. The receivers have
input hysteresis to improve noise margin, and their input loading
follows the bus standard specifications.

I

•
•
•
•
•
•
•
•
•
•
•

SILICON MONOLITHIC
INTEGRATED CIRCUIT

...

Four Independent Driver/Receiver Pairs
Three-State Outputs
High Impedance Inputs
Receiver Hysteresis - 600 mV (Typ)
Fast Propagation Times - 15-20 ns (Typ)
TTL Compatible Receiver Outputs
Single +5 Volt Supply
Open Collector Driver Output Option(1}
Power Up/Power Down Protection
(No Invalid Information Transmitted to Bus)
No Bus Loading When Power Is Removed From Device
Required Termination Characteristics Provided

LSUFFIX
CERAMIC PACKAGE
CASE 620-02

Send/Rec.
Input A

Value

Unit

VCC

7.0

Vdc

VI

5.5

Vdc

10(o}

150

mA

°c
°c
°c

Input Voltage
Driver Output Current
Junction Temperature

TJ

150

Operating Ambient Temperature Range

TA

o to +70

T stg

-65to +150

Storage Temperature Range

Vcc
Send/Rec,
Input D

Data A

Symbol

Power Supply Voltage

~

1

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

(T A; 25 0 C unless otherwise noted)

Rating

I!
16

(1) Selection of the "Open Collector" configuration, in fact, selects an open collector device
with a passive pull-up load/termination which conforms to Figure 7, IEEE 488-1978
Bus Standard.

MAXIMUM RATINGS

_

Bus A
Pull-Up
Enable
Input A-B

Data D
Bus D

~

Pull-Up
Enable
Input CoD

Bus B
Data B

Bus C

Send/Rec,
Input B

-

--, , ,

Instrument

A

I

(With GPIB)

- --

I

Data C

TYPICAL MEASUREME NT

'"

Send/Rac_
Input C

SYSTEM APPLICATIO N

- T- = Bus Termination
Instrument

,.",..,,,,,,,,

Programmable
Calculator
(With GPIB)

I

I

,
I

1

B
(With GPIB)

I

TRUTH TABLE

... , ...

Send/Rec.

----

x

16 Lines Total

3·144

~

Don't Care

Enable

Info. Flow
BUI 4 Data

Comments

Data'" Bus

Active Pull· Up

Data .....",. Bus

Open Col.

MC3448A

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted 4.75

v.;;

VCC';; 5.25 V and 0';; TA';; 70 o C; typical values are at TA = 25 0 C, VCC = 5.0 V)

Characteristic

Typ

Max

2.75

-

-

-

3.7
-1.5

Symbol

Min

V(BUS)
VIC(BUS)

Unit
V

Bus Voltage
(Bus Pin Open)(VI(S/R) = 0.8 V)
(I(BUs)=-12mA)
Bus Current
(5.0 v.;; V(BUS) .;; 5.5 V)
(V(BUS) = 0.5 V)
(VCC = 0 V,O v.;; V(BUS)';; 2.75 V)

mA

I(BUS)
2.5
-3.2

0.7

-

-1.3

+0.04

-

-

-

400

600

-

VILH(R)
VIHL(R)

-

1.6
1.0

1.8

0.8

Receiver Output Voltage - High Logic State
(V I (SIR) = 0.8 V, IOH (R) = -800 !J.A, V (BUS) = 2.0 V)

VOH(R)

2.7

-

-

\/

Receiver Output Voltage - Low Logic State

VOL(R)

-

-

0.5

V

IOS(R)

-15

-

-75

mA

Driver Input Voltage - High Logic State
(VI(S/R) = 2.0 V)

VIH(D)

2.0

-

-

V

Driver Input Voltage - Low Logic State

VIL(D)

-

-

0.8

V

Receiver Input Hysteresis

mV

(VI(S/R) = 0.8 V)
V

Receiver Input Threshold
(VI(S/R) = 0.8 V, Low to High)
(VI(S/R) = 0.8 V, High to Low)

-

(VI(S/R) = 0.8 V, IOL(R) = 16 mA, V(BUS) = 0.8 V)
Receiver Output Short Circuit Current
(VI(S/R) = 0.8 V, V(BUS) = 2.0 V)

(VI(S/R) = 2.0 V)
!J.A

Driver Input Current - Data Pins
(VI(S/R) = VI(E) = 2.0 V)
(0.5';; VI(D) .;; 2.7 V)
(VI(D) = 5.5 V)

-

40
200

-100

-

-

-

20
100

-

20
100

11(0)

-200

IIB(D)

-

II(S/R)
IIB(S/R)

!J.A

Input Current - Send/Receive
(0.5';; VI(S/R)';; 2.7 V)
(VI(S/R) = 5.5 V)

!J.A

Input Current - Enable
(0.5';; VI(E) .;; 2.7 V)
(VI(E) = 5.5 V)

II(E)

-200

IIB(E)

Driver Input Clamp Voltage

VIC (D)

-

-

-1.5

V

VOH(D)

2.5

-

-

V

VOL(D)

-

-

0.5

V

IOS(D)

-30

-

-120

mA

ICCL
ICCH

-

63
106

85
125

(VI(S/R) = 2.0 V, IIC(D) = -18 mAl
Driver Output Voltage - High Logic State
(VI(S/R) = 2.0 V, VIH(D) = 2.0 V, VIH(E) = 2.0 V, IOH = -5.2 mAl
Driver Output Voltage - Low Logic State (Note 1)
(VI(SIR) = 2.0 V, lOUD) = 48 mAl
Output Short Circuit Current
(VI(S/R) = 2.0 V, VIH(D) = 2.0 V, VIH(E) = 2.0 V)
mA

Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)

SWITCHING CHARACTERISTICS

(VCC

= 5.0

V, TA

= 25 0 C unless

otherwise noted)
ns

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)

tPLH(D)
tpHL(D)

-

-

-

15
17

Propagation Delay of Receiver
(Output Low to High)
(Output High to Low)

tpLH(R)
tpHL(R)

-

-

-

25
23

ns

NOTE 1. A modification of the IEEE 488-1978 Bus Standard changes VOL(D) from 0.4 to 0.5 V maximum to permit the use of
Schottky technology.

3-145

I

MC3448A
SWITCHING CHARACTERISTICS (continued)

(VCC; 5.0 V, T A; 25 0 C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Propagation Delay Time - Send/Receive to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low

tPHZ(R)
tpZH(R)
tPLZ(R)
tpZL(R)

-

-

-

30
30
30
30

Propagation Delay Time - Send/Receive to Bus
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low

tPHZ(D)
tpZH(D)
tPLZ(D)
tpZL(D)

-

-

30
30
30
30

tPOFF(E)
tpON(E)

-

-

-

-

30
20

Unit
ns

ns

Turn-On Time - Enable to Bus
Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable

-

ns

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

I

To Scope
(Output)

Input

+ 5.0 V

To Scope

240

(Input)

Output

1N916
f

~

or Equiv

1.0 MHz

tTLH ~ tTHL';; 5.0 ns (10 90)
DutV Cycle

~

50%
Pulse

.. Includes Jig and

Send/

Generator

Probe Cap~citance

Rec

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)
3.0 V

To Scope

L

(Input)

L -.......-i----o-~

To Scope
(Output)

2.3 V

Send/

Driver Input

Rec

or Enable

1.5 V

38.3
Bus

Pulse

Output

CL'130 pF
f~1.0MHz

• Includes Jig

tTLH ~ tTHL';; 5.0 ns (10· 90)

Pull·Up Enable

and Probe Capacitance

DutV Cycle

3.0 V

~

50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
3.0 V

To Scope
(OUI"ut)

Input

ZL
Data
Output

~L

Send/Rec

High to Open

To Scope

Output

(Input)

Low to Open
51
CL

~

15 pF (Includes Jig and

f~1.0MHz

Probe Capacitance

tTLH ; tTHL ~ ,;; 5.0 ns (10-90)
DutV Cycle

3-146

~

50%

MC3448A

FIGURE 4 - SEND/RECEIVE INPUT TO DATA OUTPUT (RECEIVER)
_ - - - - - - _ - - - - - 3.0 V
Input

5.0 V

OV

To Scope
(Output)

3.0 V

Output
High to Open
Output
Low to Open

CL ~ 15 pF (Includes Jig

Pulse

f

and Probe Capacitance)

~

1.0 MHz

I

tTLH = tTHL =,;;: 5.0 ns (10-90)
Duty Cycle

=

50%

FIGURE 5 - ENABLE INPUT TO BUS OUTPUT (DRIVER)
To Scope
(Output)

3.0 V

,.---------,.-----3.0 V
1.5 V

Data

1.5 V

Send/Rec
To Scope
(Input)

480

Pulse

51

Generator

CL

~

------------90%

Output

f~1.0MHz

15 pF (Includes Jig

Duty Cycle

FIGURE 6 - TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS

~o

r------ -

Vcc

50%

I

4.0

~ 5.0 V

I

2.0

TA = 25 0 C

-

~ -2.0

3.0

G -4.0

>

~

~

6.0

~
w

'"

VOC

FIGURE 7 - TYPICAL BUS LOAD LINE

5.0

4.0

VOH

tTLH ~ tTHL ~.;; 5.0ns (10-90)

and Probe Capacitance

~

c

OV

tPOFF(E)

~ -6.0

2.0

~

~ 1.0

~

V

I

488·1978
Vec =5.0 V

I

-14
1.0

1.5

2.0

-4.0

-2.0

2.0
VBUS. BUS VOLTAGE (VOLTS)

VI. INPUT VOLTAGE (VOLTS)

3-147

---I

r

--

-B.O

-10

0.5

~

Non·Shaded Area
Conforms to
Paragraph 3-5.3 of lEE E Standard

-12

o
o

I

-

-

I
4.0

6.0

MC3448A

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
+5 V

0.0

DBfI

T/A 1

Data
T/A 2

EOI

DB7

07

A/W

R/W

AS~

Al1

MC6802
OA

SAQ
AS2

MC6800
MPU

Address

AEN
A15
IFC
IAQ

IRQ

ATN

OAC

AFO

OAV
MC68488
GPIA
IBP

IB1

iB2
IB3

'"

o
IB4

IB5

IB6

IB7

NOTE 1: Although the MC3448A transceivers
are non-inverting, the 488-1978 bus callouts
appear inverted with respect to the MC68488
pin designations. This is because the 488-1978
Standard is defined for negative logic, wh ile
all M6800 MPU components
positive logic format.
NOTE

2:

Unless

proper

make

use

of

considerations

provided, it is recommended that the pull-up
enable pins on the MC3448As be grounded,

Trig

selecting the open-collector mode.

3·148

®

MOTOROLA

MC6800

8-BIT MICROPROCESSING UNIT (MPU)

MOS

The MC6800 is a monolithic 8-bit microprocessor forming the central
control function for Motorola's M6800 family. Compatible with TTL, the
MC6800, as with all M6800 system parts, requires only one + 5.0-volt
power supply, and no external TTL devices for bus interface.
The MC6800 is capable of addressing 64K bytes of memory with its
16-bit address lines. The 8-bit data bus is bidirectional as well as threestate, making direct memory addressing and multiprocessing applications realizable.

IN-CHANNEL, SILICON-GATE,
DEPLETION LOAD)

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

8-Bit Parallel Processing
Bidirectional Data Bus
16-Bit Address Bus - 64K Bytes of Addressing
72 Instructions - Variable Length
Seven Addressing Modes - Direct, Relative, Immediate, Indexed,
Extended, Implied and Accumulator
Variable Length Stack
Vectored Restart
Maskable Interrupt Vector
Separate Non-Maskable Interrupt - Internal Registers Saved in
Stack
Six Internal Registers - Two Accumulators, Index Register,
Program Counter, Stack Pointer and Condition Code Register
Direct Memory Addressing (DMA) and Multiple Processor
Capability
Simplified Clocking Characteristics
Clock Rates as High as 2.0 MHz
Simple Bus Interface Without TTL
Halt and Single Instruction Execution Capability

MICROPROCESSOR

~
'

...... I

.'

•

..' L

. ' ••

~
~

Y
.Y

S SUFFIX

CERDIP PACKAGE
CASE734

,

I

~I

P SUFFIX

PLASTIC PACKAGE
CASE 711

L SUFFIX
CERAMIC PACKAGE
CASE 715

PIN ASSIGNMENT
VSS
HALT
1

RESET
TSC
N,C.
2

ORDERING INFORMATION
Package Type
Ceramic
L Suffix

Cerdip
S Suffix

Plastic
P Suffix

Temperature

1.0
1.0
1.5
1.5
20

O°C to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6800L
MC6800CL
MC68AOOL
MC68AOOCL
MC68BOOL

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6800S
MC6800CS
MC68AOOS
MC68AOOCS
MC68BOOS

O°C to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C

OBE

NMI

N,C.

BA
Order Number

Frequency (MHz)

1.0
1.0
1.5
1.5
2.0

VMA

MC6800P
MC6800CP
MC68AOOP
MC68AOOCP
MC68BOOP

3-149

VCC

R/W
00

AO

01

Al

02

A2

03

A3

04

A4

05

A5

06

A6

07

A7

A15

A8

A14

A9

A13

A10

A12

All

VSS

I

MC6800

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range

Symbol
VCC
Yin
TA

MC~C, MC~AOOC

Tstg

Storage Temperature Range

I

Unit
V
V

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum-rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage le.g., either VSS or
VCC)·

h

MCffiOO,MCffiAOO,MC~BOO

THERMAL RESISTANCE
Rating
Plastic Package
Cerdip Package
Ceramic Package

Value
-0.3 to +7.0
-0.3to+7.0

Symbol
fJJA

toTH
o to + 70
-40 to +85
-55to +150

Value
100
60

°c
°c

Unit
°C/W

50

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °C can be obtained from:
(1)

TJ =TA+ (PD· OJA)
Where:
TAEAmbient Temperature, °C
0JA!& Package Thermal Resistance, Junction-to-Ambient, °C/W
PD!Ii PINT + PPORT
PI NT -ICC x V CC, Watts -

Chip Internal Power

PPORT - Port Power Dissipation, Watts -

User Determined

For most applications PPORT1,<1>2 - MC6800
<1>1, <1>2 - MC68Aoo
<1>1, <1>2 - MC68Boo

Total <1>1 and <1>2 Up Time

230
180

PWH

-

tr,tf

-

-

100

ns

td

0
0

-

9100
9100

ns

tut

Rise and Fall Time (Measured between VSS +0.4 and VCC-0.6)

-

900
600
440

-

MC6800
MC68Aoo
MC68Boo

Delay Time or Clock Separation (Figure 1)
(Measured at VOV = VSS + 0.6 V@tr=tf:S 100 ns)
(Measured at VOV = VSS + 1.0 V@tr=tf:s35 ns)

FIGURE 1 -

-

CLOCK TIMING WAVEFORM

~-----------------tcyc----------------~
r-----------------tut------------~

tr

tf

--1

f--

<1>1

td

r

~IHC


VILC

~

-V-O-V------t-r=T L p W < I > H - J ttf

NOTES:
1. Voltage levels shown are VL:SO.4,

VH~2.4

V, unless otherwise specified.

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted.

READ/WRITE TIMING (Reference Figures 2 through 6, 8, 9, 11, 12 and 13)

Characteristic

Symbol

MC68AOO

MC6800

MC68BOO

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

-

-

150
135

Unit

Address Delay
C=90 pF
C=30 pF

tAD

-

-

270
250

-

-

180
165

Peripheral Read Access Time
tacc= tut- (tAD+ tDSR)

tacc

605

-

-

400

-

-

290

-

-

tDSR

100

-

-

60

-

-

40

-

ns

tH

10

-

-

10

-

-

10

-

-

ns

Data Setup Time (Read)
Input Data Hold Time

ns

ns

tH

10

25

-

10

25

-

10

25

-

ns

Address Hold Time (Address, R/W, VMA)

tAH

30

50

-

30

50

-

30

50

-

ns

Enable High Time for DBE Input

tEH

450

-

-

280

-

-

220

-

ns

tDDW

-

-

225

-

-

200

-

-

160

ns

tpcs
tPCr, tPCf
tBA
tTSE
tTSD
tDBE
tDBEr, tDBEf

200

-

-

-

100
135

Output Data Hold Time

Data Delay Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
Bus Available Delay
Hi-Z Enable
Hi-Z Delay
Data Bus Enable Down Time During <1>1 Up Time
Data Bus Enable Rise and Fall Times

3-151

-

-

140

-

-

110

-

-

-

-

40

0

-

-

270

-

150

-

-

120

-

100
165

0

-

100
250

-

-

-

-

25

-

-

40

-

-

0

-

-

40
220
25

-

75

-

25

-

-

270

-

ns

I

MC6800

FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS
,..,.. Start of Cycle

<1>1

<1>2

R/Vii

Address
From MPtJ

I

- _ - t - - - - - - - t a c c - - - - - - - t -__
Data
2.0 V ---::=~I-""""===+-t..
From Memory - - - - - - - - - - - - - - - - - -.....s::::t:l~
or Peripherals
0.8 V _=""'-ll'-=:;;;:;;;;;:;~~~.

~~ Data Not Valid
FIGURE 3 - WRITE IN MEMORY OR PERIPHERALS
, . - Start of CYcle

~--------------------tCYC---------------------~

R/iii

Addr...

FromMPU~~~~~~~~~~---------------------------~~~
VMA _____~~

t---------tEH

--------1

OBE

Data
From MPU -----------------+---::s::;;:~

t\\\\\%'i Data Not Valid
NOTES:
1. Voltage levels shown are VLSO.4, VH 

~0

400

UJ

UJ

::E

;::

10 H =-145 pA max @2.4 V
10 L = 1.6 mA max @0.4 V
VCC = 5.0 V
TA = 25°C

200

100

Vi-"""

........

-~

--

;::

_V

>

g

200

100
CL includes stray capacitance

100

300

200

300

400

500

600

--

I-- ..... I--

V

........ ~
l-- ~

VMA
I
Address,

V

100

CL, LOAD CAPACITANCE (pF)

200

CL includes stray capacitance
300

400

CL, LOAD CAPACITANCE (pF)

FIGURE 6 - BUS TIMING TEST LOADS

Vee
RL

= 2.2

k.l!
TE.ST CONDITIONS

Test Point

o-_~_--+4

__---4

MMD6150

The dynamic test load for the Data Bus is
130 pF and one standard TTL load as shown.
The Address, R/W, and VMA outputs are tested
under two conditions to allow optimum operation in both buffered and unbuffered systems.
The resistor (R) is chosen to insure specified
load currents during VOH measurement.
Notice that the Data Bus lines, the Address
lines, the Interrupt Request line, and the DBE
I ine are all specified and tested to guarantee
0.4 V of dynamic noise immunity at both
"1" and "0" logic levels.

or Equiv.
C

R
MMD 7000
or Equiv.

e = 130 pF for 00-07,
= 90 pF for AO-A15,

E
R/iN, and VMA

(Except tAD2)

= 30

pF for AO-A 15, R/Vii, and VMA

(tAD2 only)

= 30 pF for BA
R = 11.7 k.l! for 00-07
= 16.5 k.l! for AO-A 15,

R/iN, and VMA

= 24 k.l! for BA

3·153

RIW- I---

500

600

I

MC6800

FIGURE 7 - EXPANDED BLOCK DIAGRAM

A15
25

A14
24

A13
23

A12
22

A11
20

A10
19

A9
18

A8
17

29
D4

30
D3

31
D2

32
D1

33
DO

Clock, cP1
Clock, cP2

37

RESET

40

Non-Maskable Interrupt

I

HALT
Interrupt Request

Instruction
Decode
and
Control

4

Three-State Control

39

Data Bus Enable

36

Bus Available
Valid Memory Address
Read/Write, R/W

VCC= Pin 8
Vss=Pins 1, 21

34

26
D7

27
D6

28
D5

3-154

A7
16

A6
15

A5
14

A4
13

A3
12

A2
11

A1
10

AO

9

MC6800

MPU SIGNAL DESCRIPTION
Proper operation of the MPU requires that certain control
and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine
the state of the processor.

Read (high) or Write (low) state. The normal standby state of
this Signal is Read (high), Three-State Control going high will
turn Read/Write to the off (high impedance) state. Also,
when the processor is halted, it will be in the off state. This
output is capable of driving one standard TTL load and
90 pF.

Clocks. Phase One and Phase Two (cjl1, cjl2) - Two pins
are used for a two-phase non-overlapping clock that runs at
the V CC voltage level.
Figure 1 shows the microprocessor clocks. The high level
is specified at VIHC and the low level is specified at VILC.
The allowable clock frequency is specified by f (frequency).
The minimum cjl1 and cjl2 high level pulse widths are specified
by PWcjlH (pulse width high time). To guarantee the required
access time for the peripherals, the clock up time, tut, is
specified. Clock separation, td, is measured at a maximum
voltage of VOV (overlap voltage). This allows for a multitude
of clock variations at the system frequency rate.

RESET - The RESET input is used to reset and start the
MPU from a power down condition resulting from a power
failure or initial start-up of the processor. This level sensitive
input can also be used to reinitialize the machine at any time
after start-up.
If a high level is detected in this input, this will signal the
MPU to begin the reset sequence. During the reset sequence, the contents of the last two locations (FFFE, FFFF)
in memory will be loaded into the Program Counter to point
to the .beginning of the reset routine. During the reset
routine, the interrupt mask bit is set and must be cleared
under program control before the MPU can be interrupted by
IRQ. While RESET is low (assuming a minimum of 8 clock
cycles have occurred) the MPU output signals will be in the
following states: VMA=low, BA=low, Data Bus=high impedance, R/W = high (read state), and the Address Bus will
contain the reset address FFFE. Figure 8 illustrates a power
up sequence using the RESET control line. After the power
supply reaches 4.75 V, a minimum of eight clock cycles are
required for the processor to stabilize in preparation for
restarting. During these eight cycles, VMA will be in an indeterminate state so any devices that are enabled by VMA
which could accept a false write during this time (such as
battery-backed RAM) must be disabled until VMA is forced
low after eight cycles. RESET can go high asynchronously
with the system clock any time after the eighth cycle.

Address Bus (AO-A15) - Sixteen pins are used for the address bus. The outputs are three-state bus drivers capable of
driving one standard TTL load and 90 pF. When the output is
turned off, it is essentially an open circuit. This permits the
MPU to be used in DMA applications. Putting TSC in its high
state forces the Address bus to go into the three-state mode.
Data Bus (00-07) - Eight pins are used for the data bus.
It is bidirectional, transferring data to and from the memory
and peripheral devices. It also has three-state output buffers
capable of driving one standard TTL load and 130 pF. Data
Bus is placed in the three-state mode when DBE is low.
Data Bus Enable (OBE) - This level sensitive input is the
three-state control signal for the MPU data bus and will
enable the bus drivers when in the high state. This input is
TTL compatible; however in normal operation, it would be
driven by the phase two clock. During an MPU read cycle,
the data bus drivers will be disabled internally. When it is
desired that another device control the data bus, such as in
Direct Memory Access IDMA) applications, DBE should be
held low.
If additional data setup or hold time is required on an MPU
write, the DBE down time can be decreased, as shown in
Figure 3 (DBE:;!:cjl2). The minimum down time for DBE is
tDBE as shown. By skewing DBE with respect to E, data
setup or hold time can be increased.

RESET timing is shown in Figure 8. The maximum rise and
fall transition times are specified by tPCr and tPCf. If RESET
is high at tpcs (processor control setup time), as shown in
Figure 8, in any given cycle then the restart sequence will
begin on the next cycle as shown. The RESET control line
may also be used to reinitialize the MPU system at any time
during its operation. This is accomplished by pulsing RESET
low for the duration of a minimum of three complete cjl2
cycles. The RESET pulse can be completely asynchronous
with the MPU system clock and will be recognized during cjl2
if setup time tpcs is met.
Interrupt Request (IRQ) - This level sensitive input requests that an interrupt sequence be generated within the
machine. The processor will wait until it completes the current instruction that is being executed before it recognizes
the request. At that time, if the interrupt mask bit in the Condition Code Register is not set. the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on
the stack. Next, the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which
is located in memory locations FFF8 and FFF9. An address
loaded at these locations causes the MPU to branch to an interrupt routine in memory. Interrupt timing is shown in
Figure 9.

Bus Available (BA) - The Bus Available signal will normally be in the low state; when activated, it will go to the
high state indicating that the microprocessor has stopped
and that the address bus is available. This will occur if the
HALT line is in the low state or the processor is in the WAIT
state as a result of the execution of a WAIT instruction. At
such time, all three-state output drivers will go to their off
state and other outputs to their normally inactive level. The
processor is removed from the WAIT state by the occurrence
of a maskable (mask bit I =0) or nonmaskable interrupt. This
output is capable of driving one standard TTL load and
30 pF. If TSC is in the high state, Bus Available wiJl be low.
Read/Write (R/W) - This TTL compatible output signals
the peripherals and memory devices wether the MPU is in a

3·155

I

..
~

FIGURE 8 -

I Cycle
I

I

#1

CO

1#5

#2

#6

#7

#9

#8

In + 11n + 21n + 31 n+41 n+51

~2JULf1,
~:7::w:rn _J_-_

11__

,25 V

-

5

~;

-

-

n

0)

RESET TIMING

-

-

-

--

-

-

-'~

-

--

----l

If---------li

If

RESET

~

-1-

Supply - / 4 , 7 5 V

1m + 11m + 21m + 31

II

I

~~

I

~ tpcs

--l

tpcs

-f~,:-I_ _ _ _ __

---i ~ tPCr
--1 I-- tpCf
:~:ress I\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\f~\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~~=-" "'-,,-.. . . . . . '-~--""""'"""'-_"'-_~'_-..J''--_~_---A_--''--_
,J

Rmm'\\\~~~~~ H"

VMA

Data
ct>

~~N\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\

,,""
II

I

Bus

\\\\\\\\\\\\\\\\\\\\\\\\\\\\f.\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~I--1'---.1 '--_..J'-_--" ...._ - - ' ''--_,'----/

BA

\\\\\\\\\\\\\\\\\\\\\\\\\\\\~~\\\\\\\\\\\\\\\\\\\\\\\\\\\\

PC 8-15 PC 0-7
((

First

ff

Instruction

~

~

~ = Indeterminate
FIGURE 9 Cycle
#1

#2

#3

#4

#5

#6

INTERRUPT TIMING
#7

#8

#9

#10

#11

#12

#13

#14

#15

~2

Address ""~
Bus
IRQ
NMI
Mask

Interrupt

-....::=:~:=-:~-----------===:-:===~==~~==~==~-;t===:~~

Data BUS====~K:==~~======~==~<=====~=====:K:=====x======~====:)c=====)(=t====~~~~~====:x======x=====~

New PC 8-15 New PC 0-7, First Inst of
Address
Address
Interrupt Routine

R!W
VMA

o
o

MC6800

The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while HALT
is low.
The IRO has a high-impedance pullup device internal to
the chip; however, a 3 kO external resistor to VCC should be
used for wire-OR and optimum control of interrupts.
Non-Maskable Interrupt (NMII and Wait for Interrupt
(WAil - The MC6800 is capable of handling two types of interrupts: maskable (lRO) as described earlier, and nonmaskable (NMI) which is an edge sensitive input. IRO is
maskable by the interrupt mask in the condition code register
while NMI is not maskable. The handling of these interrupts
by the MPU is the same except that each has its own vector
address. The behavior of the MPU when interrupted is
shown in Figure 9 which details the MPU response to an interrupt while the MPU is executing the control program. The
interrupt shown could be either i'RQ or NMI and can be asynchronous with respect to q,2. The interrupt is shown going
low at time tpcs in cycle #1 which precedes the first cycle of
an instruction (OP code fetch). This instruction is not executed but instead the Program Counter (PC), Index
Register (IX), Accumulators (ACCX), and the Condition
Code Register (CCR) are pushed onto the stack.
The Interrupt Mask bit is set to prevent further interrupts.
The address of the interrupt service routine is then fetched
from FFFC, FFFD for an NMI interrupt and from FFF8, FFF9
for an IRO interrupt. Upon completion of the interrupt service routine, the execution of RTI will pull the PC, IX, ACCX,
and CCR off the stack; the Interrupt Mask bit is restored to
its condition prior to Interrupts (see Figure 10).
Figure 11 is a similar interrupt sequence, except in this
case, a WAIT instruction has been executed in preparation
for the interrupt. This technique speeds up the MPU's
response to the interrupt because the stacking of the PC, IX,
ACCX, and the CCR is already done. While the MPU is
waiting for the interrupt, Bus Available will go high indicating the following states of the control lines: VMA is low,
and the Address Bus, R/W and Data Bus are all in the high
impedance state. After the interrupt occurs, it is serviced as
previously described.
A 3-10 kO external resistor to VCC should be used for wireOR and optimum control of interrupts.
MEMORY MAP FOR INTERRUPT VECTORS
Vector
MS
LS
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
FFF8
FFF9

Description
Reset
Non-Maskable Interrupt
Software Interrupt
Interrupt Request

Refer to Figure 10 for program flow for Interrupts.
Three-State Control (TSC) - When the level sensitive
Three-State Control (TSC) line is a logic "1", the Address
Bus and the R/iN line are placed in a high-impedance state.
VMA and BA are forced low when TSC= "'" to prevent
false reads or writes on any device enabled by VMA. It is
necessary to delay program execution while TSC is held
high. This is done by insuring that no transitions of q,1 (or q,2)
occur during this period. (Logic levels of the clocks are irrelevant so long as they do not change). Since the MPU is a
dynamic device, the q, 1 clock can be stopped for a maximum

3·157

time PWq,H without destroying data within the MPU. TSC
then can be used in a short Direct Memory Access IDMA)
application.
Figure 12 shows the effect of TSC on the MPU. TSC must
have its transitions at tTSE (three-state enable) while holding
q,1 high and q,2 low as shown. The Address Bus and R/W
line will reach the high-impedance state at tTSD (three-state
delay), with VMA being forced low. In this example, the
Data Bus is also in the high-impedance state while q,2 is being held low since DBE=q,2. At this point in time, a DMA
transfer could occur on cycles #3 and #4. When TSC is
returned low, the MPU Address and R/W lines return to the
bus. Because it is too late in cycle #5 to access memory, this
cycle is dead and used for synchronization. Program execution resumes in cycle #6.
Valid Memory Address (VMA) - This output indicates to
peripheral devices that there is a valid address on the address
bus. In normal operation, this Signal should be utilized for
enabling peripheral interfaces such as the PIA and ACIA.
This signal is not three-state. One standard TTL load and
90 pF may be directly driven by this active high Signal.
HALT - When this level sensitive input is in the low state,
all activity in the machine will be halted. This input is level
sensitive.
The HALT line provides an input to the MPU to allow control of program execution by an outside source. If HALT is
high, the MPU will execute the instructions; if it is low, the
MPU will go to a halted or idle mode. A response Signal, Bus
Available IBA) provides an indication of the current MPU
status. When BA is low, the MPU is in the process of executing the control program; if BA is high, the MPU has
halted and all internal activity has stopped.
When BA is high, the Address Bus, Data Bus, and R/iN
line will be in a high-impedance state, effectively removing
the MPU from the system bus. VMA is forced low so that the
floating system bus will not activate any device on the bus
that is enabled by VMA.
While the MPU is halted, all program activity is stopped,
and if either an NMI or IRO interrupt occurs, it will be latched
into the MPU and acted on as soon as the MPU is taken out
of the halted mode. If a RESET command occurs while the
MPU is halted, the following states occur: VMA = low,
BA=low, Data Bus=high impedance, R/W=high (read
state), and the Address Bus will contain address FFFE as
long as RESET is low. As soon as the RESET line goes high,
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.
Figure 13 shows the timing relationships involved when
halting the MPU. The instruction illustrated is a one byte, 2
cycle instruction such as CLRA. When HALT goes low, the
MPU will halt after completing execution of the current instruction. The transition of HALT must occur tpcs before
the trailing edge of q,1 of the last cycle of an instruction
(point A of Figure 13). HAIT must not go low any time later
than the min mum tpcs specified.
The fetch of the OP code by the MPU is the first cycle of
the instruction. If HALT had not been low at Point A but
went low during q,2 of that cycle, the MPU would have
halted after completion of the following instruction. BA will
go high by time tBA (bus available delay time) after the last
instruction cycle. At this point in time, VMA is low and R/W,
Address Bus, and the Data Bus are in the high-impedance
state.

I

MC6800

To debug programs it is advantageous to step through
programs instruction by instruction. To do this, HALT must
be brought high for one MPU cycle and then returned low as
shown at point B of Figure 13. Again, the transitions of
RAIT must occur tpcs before the trailing edge of 411. BA
will go low at tBA after the leading edge of the next 41 1, indicating that the Address Bus, Data Bus, VMA and R/W

FIGURE 10 -

lines are back on the bus. A single byte, 2 cycle instruction
such as LSR is used for this example also. During the first cycle, the instruction Y is fetched from address M + 1. BA
returns high at tBA on the last cycle of the instruction indicating the MPU is off the bus. If instruction Y had been
three cycles, the width of the BA low time would have been
increased by one cycle.

MPU FLOWCHART

I

Condition Code Register

Notes:
1. Reset is recognized at any position in the flowchart.
2. Instructions which affect the I-Bit act upon a one-bit buffer register,
"ITMP." This has the effect of delaying any CLEARING of the I-Bit one
clock time. Setting the I-Bit, however, is not delayed.
3. See Tables 6-11 for details of Instruction Execution.

3·158

FIGURE 11 Cycle
#1

.--,

#3

#2

.--,

#6

#5

#4

3:

o

WAIT INSTRUCTION TIMING

#8

#7

#9

I

#10

n+l

I

n+2

I

n+3

I

n+4

I

n+5

Address
Bus
RM
VMA
Interrupt
Mask

First Inst
of Interrupt
Routine

IRQor

NMi
Data Bus
Inst

Address

BA
Note: Midrange waveform indicates
high impedance stats.

CfJ
~

0'1

CO

FIGURE 12 -

THREE-STATE CONTROL TIMING

Cycle

""2

""1

""3

=4

=5

=6

=7

=8

=9

System

'/11

MPU '/>1

~~~ress)(

II

~

Riw"

II
II

.--

-- II

~

~

"

~

'I

II

Data
Bus
';>2

=

=
~~--v--~
,

'------.J'----

DBE

TSC

0)
Q)

o

o

r

2

VMA

I

--=::;::(f4-- tT S E

tTSE

~

-

Address

MC6800

FIGURE 13 - HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG

VMA

I

R/W

~______\~__________~

~~--------------~(f
Fetch

V

/

(I

\

>-

'<

/'

Execute

Address
Bus
Data
Bus

r

\

BA

r



INDEX

MNEMONIC

OP

-

==

OP

-

==

OP

-

CPX
OEX
DES
INX
INS
LOX
LOS
STX
STS
TXS
TSX

BC

3

3

9C

4

2

AC

6

CE
BE

3
3

3
3

DE
9E
OF
9F

4
4
5

5

2 EE
2 AE
2 EF
2 AF

6
6
7
7

EXTNO

==
2

OP

-

==

BC

5

3

FE
BE
FF

2
2
2

2 I BF

5

5
6
6

i

(Bit NI Test: Sign bit of most significant (MSI byte of result = 17
(Bit VI Test: 2's complement overflow from subtraction of ms bytes?
(Bit NI Test: Result less than zero? (Bit 15 = 1 I

3·163

5 4 J 2 1 0

IMPLIED
OP

-

==

09
34
08
31

4
4
4
4

I
1
1
1

BOO LEAN/ARITHMETIC OPE RATIO N
XH - M. XL - (M + I)

3
3
3
3

X-1~X

SP - 1 ~SP
X + 1~ X
SP + 1 ~ SP
M ~ XH. (M + 1)-- XL
M --SPH. 1M + 11 ~SPL
XH~M.XL~IM+ll

35
30

4
4

1
1

SPH ~M. SPL
X - 1 ~ SP
SP + 1 ~ X

~(M

+ 11

···....·.··..
···....·.···..
····..... ...···
·.·.·.
H I N Z V C

CD! 14.
!
!

@!

0:

@:
@:

R
R
R
R

•

I

MC6800

FIGURE 15 - STACK OPERATION, PUSH INSTRUCTION
MPU

MPU

ACCA

ACCA

~
m - 2

m - 2

m -1

I

SP_m-1

"co

SP_m

Previously
Stacked
Data

New Data

III

{:::

7F

o

Previously
Stacked
Data

63

m +3

F3

co

7F

FD

m++21
63

m
{
m

+3

FD

3C

PC_

3C

PSHA

PSHA

Next Instr.

PC-

(a) Before PSHA

Next Instr.

(b) After PSHA

FIGURE 16 - STACK OPERATION, PULL INSTRUCTION
MPU

MPU

ACCA

ACCA

m - 2

m - 2

m -1

m -1

SP~m

PreviouslY
Stacked
Data

{:: ~ I---:-:--~
m + 3

m + 1

SP _

+2

3C

m +3

05

m

Previously
Stacked
Data

05

EC

1A

{

PULA
PC_

(a) Before PULA

Next Instr.

(b) After PULA

3·164

MC6800

TABLE 4 - JUMP AND BRANCH INSTRUCTIONS
CONO. CODE REG.
RELATIVE
OPERATIONS
Branch Always
Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If ;;. Zero
Branch If > Zero
Branch If Higher
Branch If ';;Zero
Branch If lower Gr Same
Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt"

MNEMONIC

OP

BRA
BCC
BCS
BEG
BGE
BGT
BHI
BlE
BlS
BlT
BMI
BNE
BVC
BVS
BPl
BSR
JMP
JSR
NOP
RTI
RTS
SWI
WAI

20
24
25
27
2C
2E
22
2F
23
20
2B
26
28
29
2A
80

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8

INDEX

#

OP

-

EXTNO

#

OP

-

IMPLIED

#

OP

-

BRANCH TEST

#

6E
AD

4
8

3
9

7E
BD

2
2

}

3
3
01
3B
39
3F
3E

2
10
5
12
9

1
1
1
1
1

See Special Operations
Advances Prog. Cntr. Only

}

4

3

2

1

0

H

I

N

Z

V

C

·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·:1 ·· ·· ·· ·· ··
·· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
·- ·-- ·- ·· ·· ·-- .· .·· .·· ··..··
·--CD-·-1·)1·1·'·'. . . ..

None
C=O
C= 1
Z= 1
N  V) = 1
C+Z = 1
N  m - 7

m -3
m - 2

Condition Code
Acmltr. B
Acmltr. A
Index Register (X H)
Index Register (Xl)

m -1

PC(n + 1)H

m - 6

c::::>

m - 5
m -4

PC(n+1)L

HOWR
INT

SWI

NMI

NMI

No

FFFC
FFFO

FFF8
FFF9

Interrupt Memory Assignment 1
FFF8
FFF9
FFFA

IRO

MS

IRO
SWI

lS
MS

FFFB
FFFC
FFFO
FFFE
FFFF

SWI

lS ~
MS L.-..y'

NMI
NMI
Reset
Reset

lS
MS
lS

First InSlr.
Addr. Formed
By Fetching
2·Bytes From
Per. Mem.
Assign.

NOTE: MS = Most Significant Address Byte;
lS = least Significant Address Byte;

3·168

FFFE
FFFF

MC6800

FIGURE 24 -

CONDITIONAL BRANCH INSTRUCTIONS

BMI

N=1

BEQ

Z=1

BPL

N=q,

BNE

Z=q,

BVC

V=q,

BCC

C=q,

BVS

V=l

BCS

C=l

BHI

C+Z=q,

BLT

BLS

C+Z=l

BGE

NEIlV= 1
NEIlV=q,

BLE

Z+(NEIlV)-l

BGT

Z + (NEIlV) = q,

The conditional branch instructions, Figure 24, consists of
seven pairs of complementary instructions. They are used to
test the results of the preceding operation and either continue with the next instruction in sequence (test fails) or
cause a branch to another point in the program (test succeeds).
Four of the pairs are used for simple tests of status bits N,
Z, V, and C:
1. Branch on Minus (BMI) and Branch On Plus (BPU tests
the sign bit, N, to determine if the previous result was
negative or positive, respectively.
2. Branch On Equal (BEQ) and Branch On Not Equal
(BNE) are used to test the zero status bit, Z, to determine
whether or not the result of the previous operation was equal
to zero. These two instructions are useful following a Compare (CMP) instruction to test for equality between an accumulator and the operand. They are also used following the
Bit Test (BIT) to determine whether or not the same bit positions are set in an accumulator and the operand.
3. Branch On Overflow Clear (BVC) and Branch On
Overflow Set (BVS) tests the state of the V bit to determine
if the previous operation caused an arithmetic overflow.
4. Branch On Carry Clear (BCC) and Branch On Carry Set
(BCS) tests the state of the C bit to determine if the previous
operation caused a carry to occur. BCC and BCS are useful

for testing relative magnitude when the values being tested
are regarded as unsigned binary numbers, that is, the values
are in the range 00 (lowest) to FF (highest). BCC following a
comparison (CMP) will cause a branch if the (unsigned)
value in the accumulator is higher than or the same as the
value of the operand. Conversely, BCS will cause a branch if
the accumulator value is lower than the operand.
The fifth complementary pair, Branch On Higher (BHI) and
Branch On Lower or Same (BLS) are, in a sense, complements to BCC and BCS. BHI tests for both C and Z=O; if
used following a CMP, it will cause a branch if the value in
the accumulator is higher than the operand. Conversely,
BLS will cause a branch if the unsigned binary value in the
accumulator is lower than or the same as the operand.
The remaining two pairs are useful in testing results of
operations in which the values are regarded as signed two's
complement numbers. This differs from the unsigned binary
case in the following sense: in unsigned, the orientation is
higher or lower; in signed two's complement, the comparison is between larger or smaller where the range of
values is between -128 and + 127.
Branch On Less Than Zero (BL T) and Branch On Greater
Than Or Equal Zero (BGE) test the status bits for N e V = 1
and N e V = 0, respectively. BL T will always cause a branch
following an operation in which two negative numbers were
added. In addition, it will cause a branch following a CMP in
which the value in the accumulator was negative and the
operand was positive. BL T will never cause a branch following a CMP in which the accumulator value was positive and
the operand negative. BGE, the complement to BL T, will
cause a branch following operations in which two positive
values were added or in which the result was zero.
The last pair, Branch On Less Than Or Equal Zero (BLE)
and Branch On Greater Than Zero (BGT) test the status bits
for Z e (N + V) = 1 and Z e (N + V) = 0, respectively. The action of B LE is identical to that for B LT except that a branch
will also occur if the result of the previous result was zero.
Conversely, BGT is similar to BGE except that no branch will
occur following a zero result.

CONDITION CODE REGISTER
OPERATIONS
The Condition Code Register (CCR) is a 6-bit register
within the MPU that" is useful in controlling program flow
during system operation. The bits are defined in Figure 25.
The instructions shown in Table 5 are available to the user
for direct manipulation of the CCR.
A CLI-WAI instruction sequence operated properly, with
early MC6800 processors, only if the preceding instruction
was odd (Least Significant Bit = 1). Similarly it was advisable

to precede any SEI instruction with an odd opcode - such
as NOP. These precautions are not necessary for MC6800
processors indicating manufacture in November 1977 or
later.
Systems which require an interrupt window to be opened
under program control should use a CLI-NOP-SEI sequence
rather than CLI-SEI.

3-169

I

MC6800

FIGURE 25 - CONDITION CODE REGISTER BIT DEFINITION

v

IC I

H = Half-carry; set whenever a carry from b3 to b4 of the result is generated
by ADD, ABA, ADC; cleared if no b3 to b4 carry; not affected by other
instructions.
Interrupt Mask; set by hardware or software interrupt or SEI instruction;
cleared by CLI instruction. (Normally not used in arithmetic operations.)
Restored to a zero as a result of an RTl instruction if 1m stored on the
stacked is low.
N = Negative; set if high order bit (b7) of result is set; cleared otherwise.

I

Z

= Zero; set if result = 0; cleared otherwise.

v=

Overlow; set if there was arithmetic overflow as a result of the operation;
cleared otherwise.

C = Carry; set if there was a carry from the most significant bit (b7) of the
result; cleared otherwise.

TABLE 5 - CONDITION CODE REGISTER INSTRUCTIONS
CONO. COOE REG.
5

4

3

2

1

0

= BOOLEAN OPERATION H

I

N

Z

V

C

IMPLIED
OPERATIONS

MNEMONIC

OP

-

OC 2 1
0~ C
••••• R
Clear Carry
ClC
OE 2 1
0~ I
•
R •
•
•
•
Clear Interrupt Mask
CLI
OA 2
1
O~V
•••• R •
Clear Overflow
ClV
00 2 1
1~ C
•
•
•
•
•
S
Set Carry
SEC
OF 2
1
1~ I
•
S •
•
•
•
Set Interrupt Mask
SEI
Set Overflow
SEV
08 2 1
1~ V
•••• S •
Acmltr A ~ CCR
TAP
06 2 1
A ~ GGR
--~CC~R_~~A~c~m~ltr~A~__~__~T~PA~~~07-L~2~1~__~C~CR_~_A __~~._~1.~I_._~I.~I_._~I.

CD - - -

R = Reset
S = Set
• = Not affec ted

CD

(ALL) Set according to the contents of Accumulator A.

ADDRESSING MODES
The MPU operates on 8-bit binary numbers presented to it
via the Data Bus. A given number (byte) may represent
either data or an instruction to be executed, depending on
where it is encountered in the control program. The M6800
has 72 unique instructions, however, it recognizes and takes
action on 197 of the 256 possibilitis that can occur using an
8-bit word length. This larger number of instructions results
from the fact that many of the executive instructions have
more than one addressing mode.
These addressing modes refer to the manner in which the
program causes the MPU to obtain its instructions and data.
The programmer must have a method for addressing the
M PU's internal registers and all of the external memory locations.
Selection of the desired addressing mode is made by the
-user as the source statements are written. Translation into

3-170

appropriate opcode then depends on the method used. If
manual translation is used, the addressing mode is inherent
in the opcode. For example, the Immediate, Direct, Indexed,
and Extended modes may all be used with the ADD instruction. The proper mode is determined by selecting (hexadecimal notation) 8B, 9B, AB, or BB, respectively.
The source statement format includes adequate information for the selection if an assembler program is used to
generate the opcode. For instance, the Immediate mode is
selected by the Assembler whenever it encounters the "t"
symbol in the operand field. Similarly, an "X" in the operand
field causes the Indexed mode to be selected. Only the
Relative mode applies to the branch instructions, therefore,
the mnemonic instruction itself is enough for the Assembler
to determine addressing mode.

MC6800

For the instructions that use both Direct and Extended
modes, the Assembler selects the Direct mode if the operand
value is in the range 0-255 and Extended otherwise. There
are a number of instructions for which the Extended mode is
valid but the Direct is not. For these instructions, the
Assembler automatically selects the Extended mode even if
the operand is in the 0-255 range. The addressing modes are
summarized in Figure 26.

"operands" but the space between them and the operator
may be omitted. This is commonly done, resulting in apparent four character mnemonics for those instructions.
The addition instruction, ADD, provides an example of
dual addressing in the operand field:
Operator Operand

Comment

ADDA

MEM12 ADD CONTENTS OF MEM12 TO ACCA

ADDB

MEM12 ADD CONTENTS OF MEM12 TO ACCB

or

Inherent (Includes" Accumulator Addressing" Model
The successive fields in a statement are normally
separated by one or more spaces. An exception to this rule
occurs for instructions that use dual addressing in the
operand field and for instructions that must distinguish between the two accumulators. In these cases, A and Bare
FIGURE 26 Direct:

DO

Example: SUBB Z
Addr. Range ~ 0-255

&

(K = One-Byte Oprnd)

ADDRESSING MODE SUMMARY

Instruction

n + 1

Z = Oprnd Address

n + 2

Next Instr.

Z

~1

The example used earlier for the test instruction, TST, also
applies to the accumulators and uses the "accumulator addressing mode" to designate which of the two accumulators
is being tested:

•
•
•
____K
__
=_o_p_e_ra_n_d__

Instruction

Immediate:
Example: LOAA #K
(K = One-Byte Oprnd)

n + 1
n+2

Z

KH = Operand

Z + 1

KL = Operand

Instruction

~

n + 1

KH = Operand

n+2

KL

n + 3

Relative:

&

If Z
If Z

Next Inst_
OR

(K = Two-Byte Oprnd)
(CPX, LOX, and LOS)

OR
(K = Two-Byte Oprnd)

= Operand

K

Example: BNE

>,.;; 255,

Assembler Select Direct Mode
255, Extended Mode is selected

= Operand

Next Instr.

Instruction
n

K

(K = Signed 7-Bit Value)

+1

n + 2

±K = Brnch Offset
Next Instr.

•
•
•

Addr. Range:
-125 to +129
Relative to n.

FO

Extended:
Example: CMPA Z
Addr_ Range:

&

Instruction

(n + 2) ±K 1
..._ _
N_e_xt_ln_st_r_._&_3_----1

n + 1

ZH = Oprnd Address

n + 2

ZL = Oprnd Address

n + 3

Next Instr.

256-65535

(K = One-Byte Oprnd)

Z

1~

___

&

•
•
•

If Brnch Tst False,

&

If Brnch Tst True.

Indexed:

Instruction
n + 1

Z

Addr. Range:
0-255 Relative to
Index Register, X

n+2

Next Instr_

(Z = a-Bit Unsigned
Value)

X+Z

•
•

K_=_o_p_er_a_nd
____......

Z

KH = Operand

Z + 1

KL = Operand

3-171

= Offset

Example: ADDA Z, X

OR
(K = Two-Byte Oprnd)

&

K = Operand

I

MC6800

Operator

Comment

TSTB

TEST CONTENTS OF ACCB

TSTA

TEST CONTENTS OF ACCA

mode, the "address" of the operand is effectively the
memory location immediately following the instruction itself.
Table 7 shows the cycle-by-cycle operation for the immediate addressing mode.

or

I

Direct and Extended Addressing Modes - In the Direct
and Extended modes of addressing, the operand field of the
source statement is the address of the value that is to be
operated on. The Direct and Extended modes differ only in
the range of memory locations to which they can direct the
MPU. Direct addressing generates a single 8-bit operand
and, hence, can address only memory locations 0 through
255; a two byte operand is generated for Extended addressing, enabling the MPU to reach the remaining memory locations, 256 through 65535. An example of Direct addressing
and its effect on program flow is illustrated in Figure 30.
The MPU, after encountering the opcode for the instruction LDAA (Direct) at memory location 5004 (Program
Counter=5004), looks in the next location, 5005, for the address of the operand. It then sets the program counter equal
to the value found there (100 in the example) and fetches the
operand, in this case a value to be loaded into accumulator
A, from that location. For instructions requiring a two-byte
operand such as LOX (Load the Index Register), the operand
bytes would be retrieved from locations 100 and 101. Table 8
shows the cycle-by-cycle operation for the direct mode of
addressing.
Extended addressing, Figure 31, is similar except that a
two-byte address is obtained from locations 5007 and 5008
after the LDAB (Extended) opcode shows up in location
5006. Extended addressing can be thought of as the "standard" addressing mode, that is, it is a method of reaching
any place in memory. Direct addressing, since only one address byte is required, provides a faster method of processing data and generates fewer bytes of control code. In most
applications, the direct addressing range, memory locations
0-255, are reserved for RAM. They are used for data buffering and temporary storage of system variables, the area in
which faster addressing is of most value. Cycle-by-cycle
operation is shown in Table 9 for Extended Addressing.

A number of the instructions either alone or together with
an accumulator operand contain all of the address information that is required, that is, "inherent" in the instruction
itself. For instance, the instruction ABA causes the MPU to
add the contents of accmulators A and B together and place
the result in accumulator A. The instruction INCB, another
example of "accumulator addressing," causes the contents
of accumulator B to be increased by one. Similarly, INX, increment the Index Register, causes the contents of the Index
Register to be increased by one.
Program flow for instructions of this type is illustrated in
Figures 27 and 28. In these figures, the general case is shown
on the left and a specific example is shown on the right.
Numerical examples are in decimal notation. Instructions of
this type require only one byte of opcode. Cycle-by-cycle
operation of the inherent mode is shown in Table 6.

Immediate Addressing Mode - In the Immediate addressing mode, the operand is the value that is to be operated on.
For instance, the instruction
Operator

Operand

Comment

LDAA

125

LOAD 25 INTO ACCA

causes the MPU to "immediately load accumulator A with
the value 25"; no further address reference is required. The
Immediate mode is selected by preceding the operand value
with the "#" symbol. Program flow for this addressing mode
is illustrated in Figure 29.
The operand format allows either properly defined symbols or numerical values. Except for the instructions CPX,
LOX, and LOS, the operand may be any value in the range 0
to 255. Since Compare Index Register (CPX), Load Index
Register (LOX), and Load Stack Pointer (LOS), require 16-bit
values, the immediate mode for these three instructions require two-byte operands. In the Immediate addressing

FIGURE 28 - ACCUMULATOR ADDRESSING

FIGURE 27 - INHERENT ADDRESSING
MPU

MPU

MPU

RAM

PROGRAM
MEMORY

PC

0

5000 ~""'-"_-I"
PC

GENERAL FLOW
GENERAL FLOW

EXAMPLE

3·172

0

5001 '--~"'--_".

EXAMPLE

MC6800

Relative Address Mode - In both the Direct and Extended
modes, the address obtained by the MPU is an absolute
numerical address. The Relative addressing mode, implemented for the MPU's branch instructions, specifies a
memory location relative to the Program Counter's current
location. Branch instructions generate two bytes of machine
code, one for the instruction opcode and one for the
"relative" address (see Figure 32). Since it is desirable to be
able to branch in either direction, the 8-bit address byte is interpreted as a signed 7-bit value; the 8th bit of the operand is
treated as a sign bit, "0" = plus and "1" = minus. The remaining seven bits represent the numerical value. This
results in a relative addressing range of ± 127 with respect to
the location of the branch instruction itself. However, the
branch range is computed with respect to the next instruction that would'be executed if the branch conditions are not
satisfied. Since two bytes are generated, the next instruction
is located at PC + 2. If D is defined as the address of the
branch destination, the range is then:
(PC + 2) -127s Ds (PC+ 2) + 127
or
PC-125sDsPC+ 129
that is, the destination of the branch instruction must be
within - 125 to + 129 memory locations of the branch instruction itself. For transferring control beyond this range,
TABLE 6 Address Mode
and Instructions

ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

the unconditional jump (JMP), jump to subroutine (JSR),
and return from subroutine (RTS) are used.
In Figure 32, when the MPU encounters the opcode for
BEQ (Branch if result of last instruction was zero), it tests the
Zero bit in the Condition Code Register. If that bit is "0," indicating a non-zero result, the MPU continues execution
with the next instruction (in location 5010 in Figure 32). If the
previous result was zero, the branch condition is satisfied
and the M PU adds the offset, 15 in this case, to PC + 2 and
branches to location 5025 for the next instruction.
The branch instructions allow the programmer to efficiently direct the MPU to one point or another in the control program depending on the outcome of test results. Since the
control program is normally in read-only memory and cannot
be changed, the relative address used in execution of branch
instructions is a constant numerical value. Cycle-by-cycle
operation is shown in Table 10 for relative addressing.
Indexed Addressing Mode - With Indexed addressing,
the numerical address is variable and depends on the current
contents of the Index Register. A source statement such as
Operator
STAA

Operand

X

Comment
PUT A IN INDEXED LOCATION

causes the MPU to store the contents of accumulator A in

INHERENT MODE CYCLE-BY-CYCLE OPERATION

R/W
Address Bus

2

4

PSH

4

PUL

4

TSX

4

TXS

4

RTS

5

Line

Data Bus

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

OpCode of Next Instruction

3
4

0

Previous Register Contents

1

Irrelevant Data (Note 1)

0

New Register Contents

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code

2
3
4

1

Op Code Address + 1

1

Op Code of Next Instruction

1

Stack Pointer

0

Accumulator Data

0

Stack Pointer - 1

1

Accumulator Data

1

1

Op Code Address

1

Op Code
Op Code of Next Instruction

2

1

Op Code Address + 1

1

3
4

0

Stack Pointer

1

Irrelevant Data (Note 1)

1

Stack Pointer + 1

1

Operand Data from Stack

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3
4

0

Stack Pointer

1

Irrelevant Data (Note 1)

0

New Index Register

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3
4

0
0

Index Register

1

Irrelevant Data

New Stack Pointer

1

Irrelevant Data

1

1

Op Code Address

1

OpCode
Irrelevant Data (Note 2)

2

1

Op Code Address + 1

1

3
4

0

Stack Pointer

1

Irrelevant Data (Note 1)

1

Stack Pointer + 1

1

Address of Next Instruction (High
Order Byte)

5

1

Stack Pointer + 2

1

Address of Next Instruction (Low
Order Byte)

3·173

I

MC6800

TABLE 6 - INHERENT MODE CYCLE-BY-CYCLE OPERATION (CONTINUED)
Address Mode
and Instructions

Address Bus

WAI

9

RTI

I

10

SWI

12

Note 2.
Note 3.

Data Bus

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

1

Stack Pointer

0

Return Address (Low Order Byte)

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1
1

Stack Pointer - 3

7

1

Stack Pointer - 4

0
0

Contents of Accumulator A

8
9
1
2
3
4

1

Stack Pointer - 5
Stack Pointer - 6 (Note 3)

0
1

Contents of Accumulator B

1
1

Op Code Address

1

Op Code

1

Op Code Address + 1

1

Irrelevant Data (Note 2)

0
1

Stack Pointer
Stack Pointer + 1

1
1

Index Register (High Order Byte)

Contents of Condo Code Register

Irrelevant Data (Note 1)
Contents of Condo Code Register from
Stack

5

1

Stack Pointer + 2

1

Contents of Accumulator B from Stack

6
7

1

Stack Pointer + 3

1

Contents of Accumulator A from Stack

1

Stack Pointer + 4

1

Index Register from Stack (High Order
Byte)

8

1

Stack Pointer + 5

1

Index Register from Stack (Low Order
Byte)

9

1

Stack Pointer + 6

1

Next Instruction Address from Stack
(High Order Byte)

10

1

Stack Pointer + 7

1

Next Instruction Address from Stack
(Low Order Byte)

1

1

Op Code Address

1

2

1

1

Irrelevant Data (Note 1 )

3

1

Op Code Address + 1
Stack Pointer

0

Return Address (Low Order Byte)

.Op Code

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

1

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1

Stack Pointer - 3

0

Index Register (High Order Byte)

7

1

Stack Pointer - 4

0

Contents of Accumulator A

8
9
10
11

1

Stack Pointer - 5
Stack Pointer - 6

0

Contents of Accumulator B

1
0

Stack Pointer - 7

0
1

Contents of Condo Code Register
Irrelevant Data (Note 1)

1

Vector Address FFFA (Hex)

1

Address of Subroutine (High Order
Byte)

1

Vector Address FFFB (Hex)

1

Address of Subroutine (Low Order
Byte)

12

Note 1.

R/W
Line

If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
Data is ignored by the MPU.
While the MPU is waULng for the interrupt, Bus Available will go high indicating the following states of the control lines: VMA is
low; Address Bus, R/W, and Data Bus are all in the high impedance state.

the memory location specified by the contents of the Index
Register (recall that the label "X" is reserved to designate the
Index Register). Since there are instructions for manipulating
X during program execution (LOX, INX, DEC, etc.), the Indexed addressing mode provides a dynamiC "on the fly" way
to modify program activity.
The operand field can also contain a numerical value that
will be automatically added to X during execution. This format is illustrated in Figure 33.
When the MPU encounters the LDAB (Indexed) opcode in

location 5006, it looks in the next memory location for the
value to be added to X (5 in the example) and calculates the
required address by adding 5 to the present Index Register
value of 400. In the operand format, the offset may be
represented by a label or a numerical value in the range 0-255
as in the example. In the earlier example, ST AA X, the
operand is equivalent to 0, X, that is, the 0 may be omitted
when the desired address is equal to X. Table 11 shows the
cycle-by-cycle operation for the Indexed Mode of Addressing.

3-174

MC6800

FIGURE 29 -

FIGURE 30 -

IMMEDIATE ADDRESSING MODE

MPU

DIRECT ADDRESSING MODE

MPU

MPU

MPU

ADDR I--~:';';';'_"""'"

PC

ADDR

I--~;.;.;.;.-L...

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

RIW

2

3

1

1

Op Code Address

2

1

Op Code Address

CPX
LOS
LOX

+1

Line

Olt. Bus

1

Op Code

1

Operand Data

1

1

Op Code Address

1

Op Code

2

1

1

Operand Data (High Order Byte)

3

1

+1
Op Code Address + 2

1

Operand Data (Low Order Byte)

Op Code Address

TABLE 8 -

EOR
LOA
ORA
SBC
SUB

EXAMPLE

IMMEDIATE MODE CYCLE-BY-CYCLE OPERATION

Address Bus

DIRECT MODE CYCLE-BY-CYCLE OPERATION

RIW

Address Mode
and Instructions

ADC
ADD
AND
BIT
CMP

t--~-L....

GENERAL FLOW

Address Mode
and Instructions
ADC
ADD
AND
BIT
CMP

t--"''"---i .....

ADDR = 0~255

EXAMPLE

TABLE 7 -

100

PC = 5004
5005

PC+ 11-~;;...,;.,......j

GENERAL FLOW

=

Address Bus

3

4

STA

4

5

Oltl Bus

1

Op Code

1

Address of Operand

Address of Operand

1

Operand Data

1

Op Code Address

1

Op Code

2

1

Op Code Address

3
4

1

Address of Operand

1

Operand Address

1

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Destination Address

3

0
1

Destination Address

1

Irrelevant Data (Note 1)

Destination Address

0
1

Data from Accumulator
Op Code

1

Address of Operand
Irrelevant Data (Note 1)

1

1

Op Code Address

2

1

Op Code Address

3

1

1

4
1
2

STS
STX

Line

+1

+1
+1

1

Address of Operand

1

Operand Data (High Order Byte)

1

Op Code Address

1

Op Code Address

3

0

Address of Operand

1

4
5

1

Address of Operand

0

Register Data (High Order Byte)

1

Address of Operand

0

Register Data (Low Order Byte)

+1

+1

Note 1. If device which is address during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.

3·175

I

MC6800

FIGURE 31 -

EXTENDED ADDRESSING MODE

MPU

ADDR

MPU

ADDR = 300 ..........;.;:;_-{"-...

......;;.;..;.;.;..;...-r......

PC = 5006
PC

1--";""-4
5009

I

ADDR

<'

256

EXAMPLE

GENERAL flOW

TABLE 9 Address Mode
and Instructions

Cycle
Cycles

STS
STX

6

JSR

9

"

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

CPX
LOS
LOX

5

STA A
STA B

5

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

6

Line

Data Bus

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

0

Address of Operand

1

Irrelevant Data (Note 1)

5
6

1

Address of Operand

Operand Data (High Order Byte)

1

Address of Operand + 1

0
0

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Subroutine (High Order Byte)

3

1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

4

1

Subroutine Starting Address

1

Op Code of Next Instruction

5
6

1

Stack Pointer
Stack Pointer - 1

0
0

Return Address (Low Order Byte)

1

7

0
0
1

Stack Pointer - 2

1

I rrelevant Data (Note 1 )

Op Code Address + 2

1

Irrelevant Data (Note 1)

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

9
3

R/VV
Address Bus

1

B

JMP

EXTENDED MODE CYCLE-BY-CYCLE

VMA
Line

Operand Data (Low Order Byte)

Return Address (High Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Jump Address (High Order Byte)

3

1

Op Code Address + 2

1

Jump Address (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Operand Data
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Operand Data (High Order Byte)

5

1

Address of Operand + 1

1

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Destination Address (High Order Byte)

3

1

Op Code Address + 2

1

Destination Address (Low Order Byte)

4

0

Operand Destination Address

1

Irrelevant Data (Note 1)

5

1

Operand Destination Address

0

Data from Accumulator

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Current Operand Data

0

Address of Operand

1

Irrelevant Data (Note 1 )

110
(Note
2)

Address of Operand

0

New Operand Data (Note 2)

5
6

Note 1. If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
Note 2. For TST, VMA = 0 and Operand data does not change.

3-176

MC6800

FIGURE 32 -

RELATIVE ADDRESSING MODE

MPU

Program
Memory
PC
(PC +

1-----1,
-t

2)~_ _ _

I
PC

FIGURE 33 -

INDEXED ADDRESSING MODE
MPU

MPU

ADDR = INDX .....~~-V
+ OFFSET ~";;';';';';;:"_I'

PC

ADDR = 405 ~""";;;;""---il""""

PC = 5006

I-----~/

.....---1.'"

OFFSET <; 255
GENERAL FLOW

TABLE

1a -

EXAMPLE

RELATIVE MODE CYClE-BY-CYClE OPERATION

Address Mode
and Instructions

BCC
BCS
BEQ
BGE
BGT

BHI
BlE
BLS
BlT
BMI

BNE
BPl
BRA
BVC
BVS

Address Bus

4

BSR

8

Note 1.

Rffl

Oeta Bus

Line

1

1

Op Code Address

1

OpCode

2

1

1

Branch Offset

3
4

0

+1
Op Code Address + 2

1

Irrelevant Data (Note 1)

0

Branch Address

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address

1

Branch Offset

3
4

0
1

Return Address of Main Program

1

Irrelevant Data (Note 1)

Stack Pointer

a

Return Address (Low Order Byte)

5
6

1

Stack Pointer - 1

0

Return Address (High Order Byte)

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

0

Return Address of Main Program

1

Irrelevant Data (Note 1)

8

a

Subroutine Address

1

Irrelevent Data (Note 1)

Op Code Address

+1

If device which is addressed during this cycle uses VMA, then the Date Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.

3·177

MC6800

TABLE 11 -

INDEXED MODE CYCLE-BY-CYCLE

RfW

Addrell Mode
and Instructions

AddreuBul

Line

INDEXED
JMP
4

AOC
ADD
AND
BIT
CMP

I

EOR
LOA
ORA
SBC
SUB

5

CPX
LOS
LOX

6

STA

6

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

7

STS
STX
7

JSR

8

Note 1.
Note 2.

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1 )

4

0

Index Register Plus Offset (w/o Carry)

1

1

Op Code Address

1
1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5

1

Index Register Plus Offset

1

Operand Data

Irrelevant Data (Note 1 )

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1)

3

0

Index Register

1

4

0

Index Register Plus Offset (wio Carry)

1

Irrelevant Data (Note 1)

5
6

1

Index Register Plus Offset

1

Operand Data (High Order Byte)

1

Index Register Plus Offset + 1

1

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

6

1

Index Register PI us Offset

0

Operand Data

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6

1

Index Register Plus Offset

1

Current Operand Data

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

7

1/0
(Note
2)

Index Register Plus Offset

0

New Operand Data (Note 2)

1

1
l-

Op Code Address

1

Op Code

2

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

1

Index Register Plus Offset

0

Operand Data (High Order Byte)

7

1

Index Register Plus Offset + 1

0

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code
Offset

2

1

Op Code Address + 1

1

3

0

Index Register

1

Irrelevant Data (Note 1 )

4

1

Stack Pointer

0

Return Address (Low Order Byte)

5
6

1

Stack Pointer - 1

0

Return Address (High Order Byte)

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

0

Index Register

1

Irrelevant Data (Note 1)

8

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
For TST, VMA = 0 and Operand data does not change.

3-178

®

MC6802
MC6808
MC6802NS

MOTOROLA

MICROPROCESSOR WITH CLOCK AND OPTIONAL RAM
The MC6802 is a monolithic 8-bit microprocessor that contains all the
registers and accumulators of the present MC6800 plus an internal clock
oscillator and driver on the same chip. In addition, the MC6802 has 128
bytes of on-board RAM located at hex addresses $0000 to $007F. The
first 32 bytes of RAM, at hex addresses $0000 to $001 F, may be retained
in a low power mode by utilizing VCC standby; thus, facilitating
memory retention during a power-down situation.
The MC6802 is completely software compatible with the MC6800 as
well as the entire M6800 family of parts. Hence, the MC6802 is expandable to 64K words.
The MC6802NS is identical to the MC6802 without standby RAM
feature. The MC6808 is identical to the MC6802 without on-board
RAM.
•

On-Chip Clock Circuit

•

128 x 8 Bit On-Chip RAM

MOS
(N-CHANNEL, SILICON-GATE,
DEPLETION LOAD)

MICROPROCESSOR
WITH CLOCK AND OPTIONAL RAM

L SUFFIX

• 32 Bytes of RAM are Retainable

CASE 715

•

Software-Compatible with the MC6800

•

Expandable to 64K Words

•

Standard TTL-Compatible Inputs and Outputs

~

• 8-Bit Word Size
•

16-Bit Memory Addressing

•

Interrupt Capability

~

PSUFFIX

PLASTIC PACKAGE
CASEn1

PIN ASSIGNMENT

VSS

RESET

HALT

EXTAL

'v1R

XTAL

ORDERING INFORMATION
Package Type
Ceramic
L Suffix

Plastic
P Suffix

Frequency (MHz)
1.0
1.0
1.0
1.0
1.5
1.5
1.5
2.0
2.0
1.0
1.0
1.0
1.0
1.5
1.5

1.'5
2.v
2.0

Temperature
O°C to 70°C
-40°C to 85°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
-40°C to 85°C
OOC to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
-40°C to 85°C
OOC to 70 0 e
OOC to 70°C
O°C to 70°C
.. 40 oC to 85°C
OOC to 70 0 e
O°C to 70°C
O°C to 70°C

Order Number
MC6802L
MC6802CL
MC6802NSL
MC6800L
MC68A02L
MC68A02CL
MC68A08L
MC68B02L
MC68B08L
MC6802P
MC6802CP
MC6802NSP
MC6800P
MC68A02P
MC68A02CP
MC68A08P
MC68B02P
MC68B08P

VMA

RE""

NMI

Vce Standby"

vee

DO

Riw

AO

Dl

Al

D2

A2

D3

A3

D4

A4

D5

A5

D6

A6

D7

A7

A15

AS

A14

A9

A13

Al0

A12

All

VSS

* Pin 35 must be tied to 5 V on the
* * Pin 36 must be tied to ground for

3·179

MC6802NS
the MC6808

I

MC6802

e

MC6808

e

MC6802NS

TYPICAL MICROCOMPUTER

Vcc

Vcc

Vcc

VCC

I----+----~ iRQ

Counter/ \
Timer I/O

I

This block diagram shows a typical cost effective microcomputer. The MPU is the
center of the microcomputer system and is
shown in a minimum system interfacing with
a ROM combination chip. It is not intended
that this system be limited to this function
but that it be expandable with other parts in
the MOOOO Microcomputer family.

' - - - -...... MR
CSO I4--'-V:..;.M;.;..A:....-_ _ _-f VM A

RESET

....C;:::I"::o=Ck,..--_ _ _-I E

RE

Riw

....~.:..-----IRlw MC6802 NMI
Parallel
I/O

MPU
DO-D7
EXTAL

CJ
AO-A15

I

AO-A15

XTAL

MAXIMUM RATINGS
Rating
Supply Voltage

Symbol

Value

Unit

VCC

-0.3 to +7.0

V

-0.3 to +7.0

V

Input Voltage

Vin

Operating Temperature Range
MC6802, MC680A02, MC680B02
MC6802C, MC680A02C
MC6802NS
MC6808,MCOOAOO,MCOOBOO

TA

Storage Temperature Range

Tstg

-55 to + 150

Symbol

Value

Unit

(JJA

100
50

°C/W

Oto+70
-40 to +85
Oto+70
Oto+70

°c

°c

This input contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logiC voltage level (e.g., either VSS
or VCC).

THERMAL CHARACTERISTICS
Characteristic
Average Thermal Resistance (Junction to Ambient)
Plastic
Ceramic

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can be obtained from:
T J= T A + (POe6JA)
Where:
TA-Ambient Temperature, °C
6JA-Package Thermal Resistance, Junction-to-Ambient, °C/W

(1)

Po - PINT + PPORT
PINT -ICC x V CC, Watts - Chip Internal Power
PPORT-Port Power Oissipation, Watts - User Oetermined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Oarlington bases or sink LEO loads.
An approximate relationship between Po and T J (if PPORT is neglected) is:
(2)
PO= K+ (TJ + 273°C)
Solving equations 1 and 2 for K gives:
K= POe(TA+273°C) +6JAeP 0 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at equilibrium)
for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1) and (2) iteratively for any
value of TA.

3·180

MC6802 • MC6808 • MC6802NS

DC ELECTRICAL CHARACTERISTICS (VCC=5 0 Vdc ±5% VSS=o TA=O to 70°C unless otherwise noted)
Typ
Characteristic
Symbol
Min
VSS+2.0
Logic, EXT AL

Max

Unit
V

VSS+4.0

-

VIL

VSS-0.3

-

lin

-

1.0

VCC
VCC
VSS+0.8
2.5

VOH

VSS+2.4
VSS+2.4
VSS+2.4

-

-

Output Low Voltage (ILoad = 1.6 mA, VCC = min)

VOL

-

-

VSS+O.4

V

Internal Power Dissipation (Measured at T A = OOC)

PINT

-

1.0

W

VSBB
V!=:B

4.0
4.75

·0.750
-

5.25
5.25

V

ISBB

-

-

8.0

mA

10
6.5

12.5
10

pF

-

12

pF

Input High Voltage

VIH

R'ESE'f

Input Low Voltage

Logic, EXT AL, ~
Logic

Input Leakage Current (Vin-Oto 5.25 V, VCC- max)
Output High Voltage
OLoad= -205p.A, Vcc=min)
Load = -l45p.A, Vcc=min)
(ILoad= -l00p.A, VCC= min)

00-07
AO-A 15, R/W, VMA, E
BA

o

Power Down
Power Up

VccStandby
Standby Current
Capacitance I
(Vin =0, TA=25°C, f= 1.0 MHz)

00-07
Logic Inputs, EXT AL

Cin

AO-A15, R/W, VMA

Cout

I

-

I

-

-

V
p.A

V

"In power-down mode, maximum power dissipation is less than 42 mW.
ICapacitances are periodically sampled rather than 100% tested.

CONTROL TIMING (VCC=5.0 V ±5%, VSS=O, TA=TL to TH, unless otherwise noted)
Symbol

Characteristics
Frequency of Operation
Crystal Frequency
External Oscillator Frequency
Crystal Oscillator Start Up Time

MC6Im
MC6ImNS
MC6808
Min Max

3·181

Min

MC68B02
MC68~

Unit

Max

fo

0.1

1.0

0.1

1.5

0.1

2.0

fXTAL
4xfo

1.0

4.0

1.0

6.0

1.0

8.0

MHz

0.4

4.0

0.4

6.0

0.4

8.0

MHz

trc

100

-

100

-

100

-

ms

tpcs
tPCr,
tPCf

200

-

140

-

110

-

ns

-

100

-

100

-

100

ns

rnn, TIm m:J])

Processor Controls (HALT, MR, RE,
Processor Control Setup Time
Processor Control Rise and Fall Time
(Does Not Apply to RESET)

MC68A02
MC68A08
Min Max

MHz

I

MC6802 • MC6808 • MC6802NS

BUS TIMING CHARACTERISTICS
Ident.
Number

I

Symbol

Characteristic

MC6eJ2
MC6ImNS
MC680B
Min Max

MC68A02
MC68AOB
Min

Max

MC68B02
MC68BOB
Min

Unit

Max

1

Cycle Time

leye

1.0

10

0.667

10

0.5

10

P.s

2

Pulse Widlh, E Low

PWEL

450

5000

280

5000

210

5000

ns

3

Pui,se Widlh, E High

PWEH

450

9500

280

9700

220

9700

ns

4

Clock Rise and Fall Time

Ir,lf

-

25

-

25

-

25

ns

-

ns

9

Address Hold Time*

IAH

20

-

20

-

20

12

Non-Muxed Address Valid Time 10 E (See NOle 51

IAVl
IAV2

160

-

100

50

-

270

-

-

17

Read Dala Selup Time

IDSR

100

70

-

60

18

Read Dala Hold Time

IDHR

10

-

10

-

10

19

Wrile Dala Delay Time

IDDW

-

225

-

170

-

21

Wrile Data Hold Time*

IDHW

30

-

20

20

-

ns

29

Usable Access Time (See NOle 41

IACC

535

-

335

-

235

-

ns

-

160

ns
ns
ns
ns

* Address and dala hold times are periodically lesled ralher than 100% tested.

FIGURE 2 - BUS TIMING

o
R/W, Address
iNon-Muxedl

---_r~~~-L~~~~--------~_r-------------------------------~~~~

Read Dala
Non-Muxed ---+-'''''';If"

MPU Read Dala Non-Muxed

Write Data
Non-Muxed _ _ _ _~

NOTES:
1. Voltage levels shown are VLSO.4 V, VHi!:2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V. unless otherwise noted.
3. All eleetricals shown for the MC6802 apply to the MC6802NS and MC6808. unless otherwise noted.
4. Usable access time is computed by: 12+3+4-17.
5. If programs are not executed from on-board RAM. TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be executed from on-board
RAM when using A and B parts (MC68A02. MC68AOB. MC68B02. MC68BOB). On-board RAM can be used for data storage with all parts.
6. All electrical and control characteristics are referenced from: T L = O°C minimum and T H = 70°C maximum.

3-182

MC6802 • MC6808 • MC6802NS

FIGURE 3 -

BUS TIMING TEST LOAD
4.75 V

RL =2.2 kO

c= 130 pF

MM06150
or Equiv.

Test Pointo-......---

300

~
>-

UJ

:.

R

g

1.---

100~__+-1_-~_+-_t_--~__+--_t_-~_+--_t_~

200

m~x 2.~

1
10 H1= _145 pA
@ V
10L = 1.6 mA max@0.4 V
VCC = 5.0 V
TA = 25°C

----

-~

L..-- ~
~ !--

f-- ~

Rm

100

I

CL includes stray capacitance

CL includes stray capacitance

°0~~-1~00--L-2~00-~-30~0-~-4~0-0-~-5~00-~~600

100

FIGURE 6 -

AID
19

A9
18

A8
17

31
02

32
D1

33
DO

3

RESET 40
Non-Maskable Interrupt iN'MiI 6

2
4

EXTAL 39
XTAL 38
Bus Available

7

Valid Memory Address

5

Read/Write IR/WI 34

Vcc=Pin B
Vcc=Pin 35 for MC6802NS
Vss=Pins 1, 21
Vss=Pin 36 for MC6BOO
26
D7

27
06

500

EXPANDED BLOCK DIAGRAM

Enable 37

HALT

400

CL LOAD CAPACITANCE ipF)

A15 A14 A13 A12 All
25
24
23
22
20

Interrupt Request I IRQI

300

200

CL LOAD CAPACITANCE ipF)

Memory Ready

I

Address, VMA

28
05

29
D4

30
03

3-183

A7
16

A6
15

A5
14

A4
13

A3
12

A2
11

Al
10

AD

9

600

MC6802 • MC6808 • MC6802NS

MPU REGISTERS

I

A general block diagram of the MC6802 is shown in Figure
6. As shown, the number and configuration of the registers
are the same as for the MC6800. The 128 x 8-bit RAM· has
been added to the basic MPU. The first 32 bytes can be retained during power-up and power-down conditions via the
RE signal.
The MC6802NS is identical to the MC6802 except for the
standby feature on the first 32 bytes of RAM. The standby
feature does not exist on the MC6802NS and thus pin 35
must be tied to 5 V.
The MC6808 is identical to the MC6802 except for onboard RAM. Since the MC6808 does not have on-board
RAM pin 36 must be tied to ground allowing the processor to
utilize up to 64K bytes of external memory.
The MPU has three 16-bit registers and three 8-bit
registers available for use by the programmer (Figure 7).

read/write memory that may have any location (address)
that is convenient. In those applications that require storage
of information in the stack when power is lost, the stack
must be non-volatile.
INDEX REGISTER

The index register is a two byte register that is used to
store data or a 16-bit memory address for the indexed mode
of memory addressing.
ACCUMULATORS

The MPU contains two 8-bit accumulators that are used to
hold operands and results from an arithmetic logic unit
(ALU).
CONDITION CODE REGISTER

The condition code register indicates the results of an
Arithmetic Logic Unit operation: Negative (N), Zero (Z),
Overflow (V), Carry from bit 7 (C), and Half Carry from bit 3
(HI. These bits of the Condition Code Register are used as
testable conditions for the conditional branch instructions.
Bit 4 is the interrupt mask bit (I). The unused bits of the Condition Code Register (b6 and b7) are ones.
Figure 8 shows the order of saving the microprocessor
status within the stack.

PROGRAM COUNTER

The program counter is a two byte (16-bit) register that
points to the current program address.
STACK POINTER
The stack pointer is a two byte register that contains the
address of the next available location in an external pushdown/pop-up stack. This stack is normally a random access

'If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be executed from on-board RAM
when using A and B parts (MC68A02, MC68A08, MC68B02, and MC68B08l. On-board RAM can be used for data storage with all parts.

FIGURE 7 -

PROGRAMMING MODEL OF THE MICROPROCESSING UNIT

~

_____~I

Accumulator A

o

1.. 1_ _ _ _ _ _ _ _ _ _ _ _--11 Stack Pointer
Condition Codes

..L..,-y.,..........

L.....I--I..........

Register

Carry (From Bit 7)
Overflow
Zero
Negative
Interrupt
' - - - - - - Half Carry (From Bit 3)

3-184

· MC6802 • MC680S • MC6802NS

FIGURE 8 -

SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK

m-9
m-8
SP

~

SP

m - 7

Stack Pointer

CC ~ Condition Codes (Also called the Processor Status Byte)
ACCB ~ Accumulator B
ACCA ~ Accumulator A
IXH ~ Index Register, Higher Order 8 Bits
IXl ~ Index Register, lower Order 8 Bits
PCH ~ Program Counter, Higher Order 8 Bits
PC l ~ Program Counter, lower Order 8 Bits

m - 6

CC

m - 5

ACCB

m - 4

ACCA

m - 3

IXH

m - 2

m - 2

IXl

m -1

m - 1

PCH

~SP

-~l

m + 1
m + 2

.>(.
t)

'"

Ul

PCl
m + 1
m + 2

I
Before

After

MPU SIGNAL DESCRIPTION
tion, bus available will be at a high state, valid memory address will be at a low state. The address bus will display the
address of the next instruction.
To ensure single instruction operation, transition of the
HALT line must occur tpcs before the falling edge of E and
the HALT line must go high for one clock cycle.
HALT should be tied high if not used. This is good
engineering design practice in general and necessary to ensure proper operation of the part.

Proper operation of the MPU requires that certain control
and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine
the state of the processor. These control and timing signals
are similar to those of the MC6800 except that TSC, DBE,
cP1, cP2 input, and two unused pins have been eliminated,
and the following signal and timing lines have been added:
RAM Enable (RE)
Crystal Connections EXT AL and XT AL
Memory Ready (MR)
VCC Standby
Enable cP2 Output (E)
The following is a summary of the MPU signals:

READ/WRITE (RiW)
This TTL-compatible output signals the peripherals and
memory devices whether the MPU is in a read (high) or write
(low) state. The normal standby state of this signal is read
(high). When the processor is halted, it will be in the read
state. This output is capable of driving one standard TTL
load and 90 pF.

ADDRESS BUS (AO-A15)
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90 pF. These
lines do not have three-state capability.

VALID MEMORY ADDRESS (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this
signal should be utilized for enabling peripheral interfaces
such as the PIA and ACIA. This signal is not three-state. One
standard TTL load and 90 pF may be directly driven by this
active high Signal.

DATA BUS (00-07)
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of
driving one standard TTL load and 130 pF.
Data bus will be in the output mode when the internal
RAM is accessed and RE will be high. This prohibits external
data entering the MPU, It should be noted that the internal
RAM is fully decoded from $0000 to $OO7F. External RAM at
$0000 to $OO7F must be disabled when internal RAM is accessed.

BUS AVAILABLE (BA) - The bus available signal will normally be in the low state; when activated, it will go to the
high state indicating that the microprocessor has stopped
and that the address bus is available (but not in a three-state
condition), This will occur if the HALT line is in the low state
or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers will go to their off-state and other outputs to their
normally inactive level. The processor is removed from the

HALT
When this input is in the low state, all activity in the
machine will be halted. This input is level sensitive. In the
HALT mode, the machine will stop at the end of an instruc-

3-185

I

MC6802 • MC6808 • MC6802NS

WAIT state by the occurrence of a maskable (mask bit I = OJ
or nonmaskable interrupt. This output is capable of driving
one standard TTL load and 30 pF.

I

tion of a routine to initialize the processor from its reset condition. All the higher order address lines will be forced high.
For the restart, the last two ($FFFE, $FFFF) locations in
memory will be used to load the program that is addressed
by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the MPU can be
interrupted by IRO. Power-up and reset timing and powerdown sequences are shown in Figures 9 and 10, respectively.
RESET, when brought low, must be held low at least three
clock cycles. This allows adequate time to respond internally
to the reset. This is independent of the trc power-up reset
that is required.
When RESET is released it must go through the low-tohigh threshold without bouncing, oscillating, or otherwise
causing an erroneous reset (less than three clock cycles).
This may cause improper MPU operation until the next valid
reset.

INTERRUPT REQUEST (IRQ)
A low level on this input requests that an interrupt sequence be generated within the machine. The processor will
wait until it completes the current instruction that is being
excuted before it recognizes the request. At that time, if the
interrupt mask bit in the condition code register is not set,
the machine will begin an interrupt sequence. The index
register, program counter, accumulators, and condition
code register are stored away on the stack. Next the MPU
will respond to the interrupt request by setting the interrupt
mask bit high so that no further interrupts may occur. At the
end of the cycle, a 16-bit vectoring address which is located
in memory locations $FFF8 and $FFF9 is loaded which
causes the MPU to branch to an interrupt routine in memory.
The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while HALT
is low.
A nominal 3 kD pullup resistor to Vee should be used for
wire-OR and optimum control of interrupts. IRO may be tied
directly to Vee if not used.

NON-MASKABLE INTERRUPT (NMI)
A low-going edge on this input requests that a nonmaskable interrupt sequence be generated within the processor. As with the interrupt request signal, the processor
will complete the current instruction that is being executed
before it recognizes the NMI signal. The interrupt mask bit in
the condition code register has no effect on 1'JMi.
The index register, program counter, accumulators, and
condition code registers are stored away on the stack. At the
end of the cycle, a 16-bit vectoring address which is located
in memory locations $FFFe and $FFFD is loaded causing the
MPU to branch to an interrupt service routine in memory.
A nominal 3 kD pullup resistor to Vee should be used for
wire-OR and optimum control of interrupts. NMI may be tied

RESET
This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is low, the
MPU is inactive and the information in the registers will be
lost. If a high level is detected on the input, this will signal
the MPU to begin the restart sequence. This will start execuFIGURE 9 -

POWER-UP AND RESET TIMING

VCC

d

trc

~------------------------~I~----------V~IHVIL

trc
RESET

/. -

tPCS

' -_ _ _ _ _ _ _ _ _ __
Option 1
(See Note Below)

-------------

-----1r

Option 2
(See Figure 10 for
Power-down Condition)

II
RE
A - - - t P - C f- - - - -

NOTE: If option 1 is chosen, RESET and RE pins can be tied together.

3-186

MC6S02 • MC6S0S • MC6802NS

directly to Vee if not used.
Inputs IRQ and NMI are hardware interrupt lines that are
sampled when E is high and will start the interrupt routine on
a low E following the completion of an instruction.
Figure 11 is a flowchart describing the major decision
paths and interrupt vectors of the microprocessor. Table 1
gives the memory map for interrupt vectors.

FIGURE 10 -

POWER-DOWN SEQUENCE

Vcc

TABLE 1 - MEMORY MAP FOR
INTERRUPT VECTORS
Vector

Description

MS

LS

$FFFE

$FFFF

Restart

$FFFC

$FFFD

Non-Maskable Interrupt

$FFFA

$FFFB

Software Interrupt

$FFF8

$FFF9

Interrupt Request

RE

FIGURE 11 -

MPU FLOWCHART

3-187

I

MC6802 • MC6S08 • MC6802NS

FIGURE 12 - CRYSTAL SPECIFICATIONS
Y1

Cin

Cout

3.58 MHz

27 pF

27 pF

4 MHz

27 pF

27 pF

6 MHz

20 pF

20 pF

8 MHz

18 pF

18 pF

Crystal Loading

-----II oIt--- - Y1

I
Nominal Crystal Parameters*
3.58 MHz

4.0 MHz

6.0 MHz

8.0 MHz

RS
CO

600
3.5 pF

500
6.5 pF

30-50 0
4-6 pF

20-40 0
4-6 pF

C1

0.015 pF

0.025 pF

0.01-0.02 pF

0.01-0.02 pF

Q

>4OK

>30K

>20K

>20K

'These are representative AT -cut parallel resonance crystal parameters only.
Crystals of other types of cuts may also be used.

Figure 13 - SUGGESTED PC BOARD LAYOUT
Example of Board Design Using the Crystal Oscillator

~Other Signals are Not Wired in this Area

E Signal is Wired Apart from 38 Pin
and 39 Pin

------038
37

/

3-188

MC6802 • MC680S • MC6802NS

FIGURE 14 - MEMORY READY SYNCHRONIZATION

4xfo
Oscillator

EXTAL~~~----------------------------t
XTAL 38
MC6802
MR~------------------4

Memory Ready
Generated from
CS Logic

II

SN74LS74

FIGURE 15 - MR NEGATIVE SETUP TIME REQUIREMENT

E Clock Stretch

9'PCS
\L.o_.8_v__

~1

~"CS

r

\~O.8v___

The E clock will be stretched at end of E high of the cycle during which MR negative meets the tpcs setup time. The tpcs setup time is
referenced to the fall of E. If the tpcs setup time is not met, E will be stretched at the end of the next E-high Y, cycle. E will be stretched in integral multiples of Y2 cycles.

Resuming E Clocking

~'PCS 9'PCS i'PCS \
Stretched E

MR

...,p_C_S_ _..J/

L

Ifllll

The E clock will resume normal operation at the end of the 11, cycle during which MR assertion meets the tpcs setup time. The tpcs setup time
is referenced to transitions of E were it not stretched. If tpcs setup time is not met, E will fall at the second possible transition time after MR is
asserted. There is no direct means of determining when the tpcs references occur, unless the synchronizing circuit of Figure 14 is used.

3-189

MC6802 • MC6808 • MC6802NS

MC6802 + MC6802NS ONLY)
A TTL-compatible RAM enable input controls the on-chip
RAM of the MC6802. When placed in the high state, the onchip memory is enabled to respond to the MPU controls. In
the low state, RAM is disabled. This pin may also be utilized
to disable reading and writing the on-chip RAM during a
power-down situation. RAM Enable must be low three
cycles before VCC goes below 4.75 V during power-down.
RAM enable must be tied low on the MC6808. RE should be
tied to the correct high or low state if not used.
RAM ENABLE (RE -

MPU INSTRUCTION SET
The instruction set has 72 different instructions. Included
are binary and decimal arithmetic, logical, shift, rotate, load,
store, conditional or unconditional branch, interrupt and
stack manipulation instructions (Tables 2 through 6), The instruction set is the same as that for the MC6800.

MPU ADDRESSING MODES

EXTAL AND XTAL

I

These inputs are used for the internal oscillator that may
be crystal controlled. These connections are for a parallel
resonant fundamental crystal (see Figure 12), (AT-cut.) A
divide-by-four circuit has been added so a 4 MHz crystal may
be used in lieu of a 1 MHz crystal for a more cost-effective
system. An example of the crystal circuit layout is shown in
Figure 13. Pin 39 may be driven externally by a TTL input
signal four times the required E clock frequency. Pin 38 is to
be grounded.
An RC network is not directly usable as a frequency
source on pins 38 and 39. An RC network type TTL or CMOS
oscillator will work well as long as the TTL or CMOS output
drives the on-chip oscillator.
LC networks are not recommended to be used in place of
the crystal.
If an external clock is used, it may not be halted for more
than tPW4>L. The MC6802, MC6808 and MC6802NS are
dynamic parts except for the internal RAM, and require the
external clock to retain information.
MEMORY READY (MR)

MR is a TTL-compatible input signal controlling the stretching of E. Use of M R requires synchronization with the 4xf 0
signal, as shown in Figure 14. When MR is high, E will be in
normal operation. When M R is low, E will be stretched integral numbers of half periods, thus allowing interface to
slow memories. Memory Ready timing is shown in Figure 15.
MR should be tied high (connected directly to VCC) if not
used. This is necessary to ensure proper operation of the
part. A maximum stretch is tcyc.
ENABLE (E)

This pin supplies the clock for the MPU and the rest of the
system. This is a Single-phase, TTL-compatible clock. This
clock may be conditioned by a memory read Signal. This is
equivalent to 4>2 on the MC6800. This output is capable of
driving one standard TTL load and 130 pF.
VCC STANDBY (MC6802 ONLY)
This pin supplies the dc voltage to the first 32 bytes of
RAM as well as the RAM Enable (RE) control logic. Thus,
retention of data in this portion of the RAM on a power-up,
power-down, or standby condition is guaranteed. Maximum
current drain at VSB maximum is ISBB. For the MC6802NS
this pin must be connected to V CC.

There are seven address modes that can be used by a programmer, with the addressing mode a function of both the
type of instruction and the coding within the instruction. A
summary of the addressing modes for a particular instruction
can be found in Table 7 along with the associated instruction
execution time that is given in machine cycles. With a bus
frequency of 1 MHz, these times would be microseconds.
ACCUMULATOR (ACCX) ADDRESSING

In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions.
IMMEDIATE ADDRESSING
In immediate addressing, the operand is contained in the
second byte of the instruction except LOS and LOX which
have the operand in the second and third bytes of the instruction. The MPU addresses this location when it fetches
the immediate instruction for execution. These are two- or
three-byte instructions.
DIRECT ADDRESSING
In direct addressing, the address of the operand is contained in the second byte of the instruction. Direct addressing
allows the user to directly address the lowest 256 bytes in the
machine, i.e., locations zero through 255. Enhanced execution times are aChieved by storing data in these locations. In
most configurations, it Should be a random-access memory.
These are two-byte instructions.
EXTENDED ADDRESSING

In extended addressing, the address contained in the second byte of the instruction is used as the higher eight bits of
the address of the operand. The third byte of the instruction
is used as the lower eight bits of the address for the operand.
This is an absolute address in memory. These are three-byte
instructions.
INDEXED ADDRESSING
In indexed addressing, the address contained in the second byte of the instruction is added to the index register's
lowest eight bits in the MPU. The carry is then added to the
higher order eight bits of the index register. This result is
then used to address memory. The modified address is held
in a temporary address register so there is no change to the
index register. These are two-byte instructions.

MC6S02 • MC6S0S • MC6802NS

IMPLIED ADDRESSING
In the implied addressing mode, the instruction gives the
address (i.e., stack pointer, index register, etc.!. These are
one-byte instructions.

byte of the instruction is added to the program counter's
lowest eight bits plus two. The carry or borrow is then added
to the high eight bits. This allows the user to address data
within a range of -125 to + 129 bytes of the present instruction. These are two-byte instructions.

RELATIVE ADDRESSING
In relative addressing, the address contained in the second

TABLE 2 -

MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE

ABA
ADC
ADD
AND
ASL
ASR

Add Accumulators
Add with Carry
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right

BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BSR
BVC
BVS

Branch if Carry Clear
Branch if Carry Set
Branch if Equal to Zero
Branch if Greater or Equal Zero
Branch if Greater than Zero
Branch if Higher
Bit Test
Branch if Less or Equal
Branch if Lower or Same
Branch if Less than Zero
Branch if Minus
Branch if Not Equal to Zero
Branch if Plus
Branch Always
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set

CBA
CLC
CLI

Compare Accumulators
Clear Carry
Clear Interrupt Mask

CLR
CLV
CMP
COM
CPX

Clear
Clear Overflow
Compare
Complement
Compare Index Register

DM
DEC
DES
DEX

Decimal Adjust
Decrement
Decrement Stack Pointer
Decrement Index Register

EOR

Exclusive OR

INC
INS
INX

Increment
Increment Stack Pointer
Increment Index Register

JMP
JSR

Jump
Jump to Subroutine

LDA
LDS
LDX
LSR

Load Accumulator
Load Stack POinter
Load Index Register
Logical Shift Right

NEG
NOP

Negate
No Operation

ORA

Inclusive OR Accumulator

PSH

Push Data

3-191

PUL

Pull Data

ROL
ROR
RTI
RTS

Rotate
Rotate
Return
Return

SBA
SBC
SEC
SEI
SEV
STA
STS
STX
SUB
SWI

Subtract Accumulators
Subtract with Carry
Set Carry
Set Interrupt Mask
Set Overflow
Store Accumulator
Store Stack Register
Store Index Register
Subtract
Software Interrupt

TAB
TAP
TBA
TPA
TST
TSX
TXS

Transfer Accumulators
Transfer Accumulators to Condition Code Reg.
Transfer Accumulators
Transfer Condition Code Reg. to Accumulator
Test
Transfer Stack Pointer to Index Register
Transfer Index Register to Stack Pointer

WAI

Wait for Interrupt

Left
Right
from Interrupt
from Subroutine

I

MC6802 • MC6808 • MC6802NS

TABLE 3 - ACCUMULATOR AND MEMORY INSTRUCTIONS
ADDRESSING MODES
IMMED
OPERATIONS
Add

Add Acmltrs
Addwlth Carry
And

Clear

Compare
Compare Acmltrs
Complement,l's

II

Complement.2's
(Negatel

Oeclmal Adjust, A

Decrement

Increment

Load Acmltr
Or, Inclusive
Push Data

Pull Data
Rotateleh

Shih Left, ArithmetiC

Store Acrnllr
Subtract
Subtract Acmltrs
Subtr.wlthCarry
Transfer Acmllrs

Test, Zeraor MlIlus

DIRECT

INDEX

OP

,

OP

,

DP

-

AOOA
AD DB
ABA
AOCA
AOCB
ANOA
ANOB
BITA
BITB
CLR
CLRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
OAA

3B
CB

2
2

9B
DB

3
3

AB
EB

5

2

5

2

DEC
OECA
OECB
EORA
EORB
INC
INCA
INCB
LOAA
LOAB
ORAA
ORAB
PSHA
PSHB
PULA
PUlB
ROl
ROlA
ROlB
ROR
RORA
RORB
ASl
ASlA
ASlB
ASR
ASRA
ASR8
lSR
lSRA
lSRB
STAA
STAB
SUBA
SUBB
SBA
S8CA
SBCB
TAB
TBA
TST
TSTA
TST8

BOOLEAN/ARITHMETIC OPERATIDN CDND CDDE REG

EXTND

MNEMONIC

IMPLIED
OP

DP

-

BB
fB

4

3

4

3

81
CI

2

2

2

2

2
2

2
2
2
2

2
2

2
2

99
09
94
04
95
05

3

2

3

A9
E9

2
3

3

91
01

2
2

E4
A5
E5
6f

Al
El
63

60

88
CB

86
C6

2
2

2
2

8A
CA

2
2

98
08

5

A4

3

2
2

3

5

7

5
5
7

7

2
2
2

2

B9
f9
84
f4
B5
f5
7f

BI

fl
73

70

4
4
4
4
4
4
6

6

3

A8
E8
6C

5

2
2
2

B8
f8
7C

4

3

4

3

6

3

2
2
2

9A
OA

3
3

2
2

AA
EA

5
5

2

2

2

5f

2

11

2

I

43
53

2

1

A·A

2

1

B

3

3

5
5

B6
f6

4
4

3
3

BA
fA

4
4

3
3

80
CO

2
2

2
2

82
C2

2
2

2
2

92
02

4

3
3

6

7

2

76

6

3

68

7

2

78

6

3

7

2

77

2

1
1
1

4A
5A

2
2

1
1

4C
5C

2

1

A

2

I

Btl

7

2

74

6

3

6
6

2
2

3
3

5
5

2
2

B7
f7
BO
fO

5
5

2
2

A7
E7
AD
EO

2
2

A2
E2

5
5

2
2

B2
F2

4
4

3
3

60

7

2

70

6

3

2
2

R S

R S
IRS

_.!

•

Converts Billary Add of BCO Characters
Into BCD Format
M - 1 ·M
A I·A
B-1 ·B
A0M -A
B0M -B

•

• •

I

!

4

M + 1 ·M
.0.

+, .

'8

2

1

2

1

~}
8

46
56

2
2

1
1

8

48
58

2
2

1
1

47
57

2
2

1
1

44
54

2

I

2

1

·SP
·SP
·A

C

~} CO
C

b7 -

-

bO

ITIIIIJI}::J
b7

-

~}~-D
b7

bO

C

0-=rrITI b7

bO

0
C

B ·M

4
10

2

1

16
17

2
2

1
1

40
50

•
•
•
•

•
•
•
•

R.

I I:~ I
I II~ I
! 'I~ I
\ 'I~!

'I~
'I~

bO

n ~-~-O
~}

R.

·.....

·8

A •M

4

!~

I R •
• .!
• • 1

L{] - crn:rr:;:o:J

:

;~:

I R •

1
1

49
59

! (J)

liCK •

A+ M • A
B +M ·8
A ·MSp. SP 1
B ·MSp.SP 1
SP.l -SP. Msp
SP'1 ·SP. MSp

4
4

I

•
! R •
I R •
I~ •
II~ •

M ·B

4

I
I

CDei)
CD CV
CD CV

I

M ·A

6

64

R S R R
R S R R
R S R R

I! I I
I I I I
I I

00 M -M
00 - A - A
00 - B • B

2
2

3

66

6/

97
07
90
DO

79

•
•
•

-B

19

33
2

•
•
•

A M
B- M
A B
M -M

40
50

36
37
32
69

I
I I
R •
R •
R •
R •

00 -M
00 ·A
OO·B

4,

3

6

A6
E6

•
•

8· M

7A

2
2

• I
• I
• I

B· M ·8
A·M

4
4
6

I
I
I
I
I

8. M ·8
A. B ·A
A'" M .. C 'A
B + M .. C 'B

3

2

3
3

1

A· M -A

7

5
7

2

3

6A

96
06

2

2
2
2
2
2
2
2

refertocontenu)
A'M -A

lB
89
C9
84
C4
85
C5

543210
H I N Z V C

(All register labels

,

A M·A
B M·B
A B·A
A M C· A
B M - C ·B
A-8
8-A
M - 00
- DO
- 00

• •

I

:I~
II~

I

:I
!

II~I

• • I II~ I
• • I II~!
• • R 'I~ I

: : : :I~ :
•
•
•
•
•

• I 1 R •
• 1 I R •
.!
I I
• I
I!
• I
I I
I
!!
I
I I
I
R.
t
R.
I
I

R R
R R
R R

H I N Z V C
LEGEND-

QP

CONOITION COOE SYMBDLS

Operallon Code (HexadeCimal!.

o

Number 01 MPU Cycles;

Number of Program Bytes,
ArithmetiC Plus;
ArithmetiC MinUS,
Boolean AND;
MSp Contents of memory locatIOn pOinted to be Stack POinter,
Note - Accumulator addreSSing mode instructions are Included

In

iii

00

Boolean InclUSive OR,
Boolean hcluslve OR;
Complemental M;
Transfer Into,
Bit: Zero:
Byte = Zero:

the column tor IMPLIED addreSSing

3-192

Half-carry from bit 3,
Interrupt mask
Negative (sign bit)
Zero (byte)
Overllow,2'scomplement
Carry from bit 7
Reset Always
Set Always
Testandset If true, cleared otherWise
Not Affected

MC6S02 • MC6S0S • MC6802NS

TABLE 4 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
CONO COOE REG
IMMEO
POINTER OPERATIONS
Compare Index lIeg
Decrement Index Reg
Decrement Stack Pntr
Increment Index Reg
Increment Stack Pntr
Load Index Aeg
load Stack Pntr
Store Index Reg
Store Stack Pntr
Indx Reg -Stack Pntr
Stack Pntr 'Indx Aeg

INOEX

DIRECT

MNEMONIC

OP

-

=

OP

-

=

OP

-

=

OP

-

=

CPX
DEX
DES
INX
INS
LOX
lOS
STX
STS
TXS
TSX

BC

3

3

9C

4

2

AC

6

2

BC

5

3

CE
BE

3
3

3
3

DE
9E
OF
9F

4
4
5
5

2
2
2
2

EE
AE
EF
AF

6
6
7
7

FE
BE
FF

"6

2 I BF

6

2
2
2

5

5 4 3 2 1 0

IMPLIED

EXTND

OP

-

=

09
34
08
31

4
4
4
4

I
I
I
I

BOOLEAN/ARITHMETIC OPERATION

4
4

35
30

----....®.
....--··.····
·(J);

XH-M,XL-IM+II
X- I - X
SP I- SP
X + 1- X
SP + I- SP
M '-XH,IM + II -XL
M -SPH,IM+II -SPL
XH -M, XL -1M + II
SPH -M,SPL -IM+II
X I - SP
SP + I • X

3
3
3
3

I

H I N Z V C

I
I

I
I

-® I
-® :
-®!
-® :

A
A
A
A

--- ---- :J-I
-- ---I

I

TABLE 5 - JUMP AND BRANCH INSTRUCTIONS
C!lND CODE REG
RELATIVE
OPERATIONS
Branch Always
Branch II Corry Clear
Branch II Carry Set
Branch II Zero
Branch II;;' Zero
Branch II >Zero
Branch II Higher
Branch II ';;Zero
Branch II lower Or Same
Branch II < Zero
Branch II Minus
Branch II Not Equal Zero
Branch If Overflow Clear
Branch II Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutme
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait lor Interrupt
0

MNEMONIC

OP

BAA
BCC
BCS
BEQ
BGE
BGT
BHI
BlE
BlS
BlT
BMI
BNE
BVC
BVS
BPl
BSA
JMP
JSA
NOP
ATI
RTS
SWI
WAI

20
24
25
27
2C
2E
22
2F
23
20
2B
26
28
29
2A
80

-

INDEX

4

= OP - "'
2

4
4
4
4
4
4
4
4
4
4
4
4
4
4
8

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

OP

5

IMPLIED

EXTND

- = OP

-

::

BRANCH TEST
None
CoO
Col
Z I
N (j) V 0
Z + IN (j) VI 0
C+

fn

INOXO

n +2

EXTNO

~

II

SP-2
SP-l
SP

INX + K

OK = 8·Bit Unsigned Value

PC

Main Program

n
n+1
n+2

BO = JSR
SH = Subr. Addr.
SL= Subr. Addr

n +3

Next Main Instr.

I

In+21 Hand In+21 L Form n+2

Sf'

~

SP-2
SP-l

S

SP L..:.;.:........;;.:.....;;._---J
.... =

(S Formed From SH and SLI

Stack POinter Alter Execution

BSR, BRANCH TO SUBROUTINE:

~,.......=.;..;.;;.~.:.......,

I

n+l
n+ 2

Sp~ ,.......--.:=----.:.......,

c:::>

.--==':':"""....,

II

n+2±K ~~:.:::.;..=~

SP- 1 t--'-----'-'-----t
SP L...;..--'_ _

L...;..:.c..;.......:...____",--,

~

OK = 7·Bit Signed Value;

n+2 Formed From In+21 Hand In+21 L

JMP, JUMP:

INDXD

n~

EXTENDED

n+2

L...!;._-:-_...J

{

I

K r-nst-ru-ct-,o....,n
N-ex -t I....
RlS, RETURN FROM SUBROUTINE:

PC

S

Subroutine

1 39 = RTS

I

~

c:::>

SP
SP + 1
SP + 2

RTI, RETURN FROM INTERRUPT:

II

Interrupt Program

S 1 3B = RTI

I

c:::>

B
NL

Stack

.sf

PC

SP
SP + 1
SP
SP
SP
SP
SP

Condition Code
Acmltr B

+2
+3
+4
+5
+6

AcmltrA
Index Register (XHI
Index Register (XLI
PCH
peL

SP + 7

TABLE 6 -

Stack

CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
CONDo CODE REG.
IMPLIED

OPERATIONS
Clear Carry
Clear Interrupt Mask
Clear Overllow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A - CCR
CCR ~Acmltr A

MNEMONIC

OP

CLC
Cli
CLV
SEC
SEI
SEV
TAP
TPA

OC
OE
OA
00
OF
OB

4

3

2

1

0

-

= BOOLEAN OPERATION

H

I

N

Z

V

C

•

•

•

•

•

R

•

R

•

•

•

•

•
•
•

•
•
S

•
•
•

•
•
•

R
•
•

•
S
•

•

•

•

•

S

2

1

0> C

2
2

1
1

O~V

2
2
2

1
1
1

06

2

1

07

2

1

CONDITION CODE REGISTER NOTES:
(Bit V)
(Bit CI
(Bit C)
(Bit VI
(Bit V)
(Bit V)

Test:
Test:
Test:
(Not
Test:
Test:
Test:

o -I
1 -> C
1--1
1- V

A ~ CCR
CCR -A

5

•

--@-.1-1.1-11

-

(Bit set It test IS true and cleared otherwisel

Result = 10000000?
Result I 000000001
Decimal value of most signilicant BCD Character greater than nine?
cleared if previously set.)
Operand = 10000000 prior to execution?
Operand = 01111111 prior to execution?
Set equal to result 01 N0C after shllt has occurred

3-194

10
11

(Bit N)
(Bit V)
(Bit N)
(AlII
(Bit I)

12

(Alii

Test: Sign bit of most significant (MSI byte = f?
Test: 2's complement overflow from subtraction of MS bytes?
Test: Result less than zero? (Bit 15 = 1)
Load Condition Code RegISter from Stack. (See Special Operations)
Set when interrupt occurs. II previously set, a Non·Maskable
Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.

MC6802 • MC6808 • MC6802NS

TABLE 7 -

~

;

~

0

~

0

ABA
ADC
ADD
AND
ASL
ASR
BCC
BCS
BEA
BGE
BGT
BHI
81T
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR

NOTE

INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES
(Times in Machine Cycle)

x

u
u

<{

~

.g

E .,u

!

0

~

w

]
"'C

1

.,>
a. ;
9!

.= !

~

e

Qj

II:

INC
INS
INX
JMP
JSR
LDA
LDS
LDX
LSR
NEG
NOP
ORA
PSH
PUL
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STS
STX
SUB
SWI
TAB
TAP
TBA
TPA
TST
TSX
TSX
WAI

4

6
6

4
4

8

4

6
5

.,

c-

0

"'C

7

6

6

4

I nterrupt time IS 12 cycles from the end of
the Instruction being executed, except following
a WAI Instruction. Then It IS 4 cycles

3-195

11

eo

X

u
U

<{

ii

E .,u

!

0

~ ].::

"'C

w

]

a.
!

2

3
9
2

3

3
3'

4

8
5
6
6

I
10

5
2

4

5
5
3

5
6
6

.

12
2
2
2
2

MC6802 • MC6808 • MC6802NS

SUMMARY OF CYCLE-BY-CYCLE OPERATION
as the control program is executed. The information is
categorized in groups according to addressing modes and
number of cycles per instruction. (In general, instructions
with the same addressing mode and number of cycles execute in the same manner; exceptions are indicated in the
table.)

Table 8 provides a detailed description of the information
present on the address bus, data bus, valid memory address
line (VMA), and the read/write line (R/W) during each cycle
for each instruction.
This information is useful in comparing actual with expected results during debug of both software and hardware

TABLE 8 - OPERATIONS SUMMARY
Address Mode
and Instructions

Address Bus

R/W
Line

Data Bus

IMMEDIATE

I

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

1

1

Op Code Address

1

Op Code

2

2

1

Op Code Address + 1

1

Operand Data

1

1

Op Code Address

1

Op Code

3

2

1

Op Code Address + 1

1

Operand Data (High Order Byte)

3

1

Op Code Address + 2

1

Operand Data (Low Order Byte)
Op Code

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

3

4

STA
4

STS
STX
5

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand

3

1

Address of Operand

1

Operand Data
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand

3
4

1

Address of Operand

1

Operand Data (High Order Byte)

1

Operand Address + 1

1

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Destination Address

3

0

Destination Address

1

Irrelevant Data (Note 1)

4

1

Destination Address

Data from Accumulator
Op Code

1

1

Op Code Address

0
1

2

1

Op Code Address + 1

1

Address of Operand

3

0

Address of Operand

1

Irrelevant Data (Note 1)

4

1

Address of Operand

0

Register Data (High Order Byte)

5

1

Address of Operand + 1

0

Register Data (Low Order Byte)

INDEXED
JMP
4

ADC'
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

5

CPX
LOS
LOX
6

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

Irrelevant Data (Note 1)
Op Code

1

1

Op Code Address

1
1

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5

1

Index Register Plus Offset

1

Operand Data

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1)

3

0

Index Register

1

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1 )

5
6

1

Index Register Plus Offset

1

Operand Data (High Order Byte)

1

Index Register Plus Offset + 1

1

Operand Data (Low Order Byte)

3-196

MC6802 • MC680S • MC6802NS

TABLE 8 - OPERATIONS SUMMARY (CONTINUED)

R/W

Address Mode
and Instructions

Address Bus

INDEXED (Continued)
STA

6

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

7

STS
STX
7

JSR

8

Data Bus

Line

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1)

3

0

Index Register

1

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6
1

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

1

Index Register Plus Offset

0

Operand Data

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1 )

3

0

Index Register

1

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6
7

1

Index Register Plus Offset

1

Current Operand Data

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

110
(Note
3)

Index Register Plus Offset

0

New Operand Data (Note 3)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5

0

Index Register Plus Offset

1

Irrelevant Data (Note 1 )

6

1

Index Register Plus Offset

0

Operand Data (High Order Byte)

7

1

Index Register PIllS Offset + 1

0

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

1

Stack Pointer

0

Return Address (Low Order Byte)

5
6

1

Stack Pointer - 1

0

Return Address (High Order Byte)

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

0

Index Register

1

Irrelevant Data (Note 1)

8

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1 )

EXTENDED
JMP
3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

CPX
LOS
LOX

5

STA A
STA B

5

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

6

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Jump Address (High Order Byte)

3

1

Op Code Address + 2

1

Jump Address (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Operand Data
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Operand Data (H igh Order Byte)

5
1
2

1

Address of Operand + 1

1

Operand Data (Low Order Byte)

1

Op Code Address

1

Op Code

1

Op Code Address + 1

1

Destination Address (High Order Byte)

3

1

Op Code Address + 2

1

Destination Address (Low Order Byte)

4

0

Operand Destination Address

1

Irrelevant Data (Note 1)

5
1

1

Operand Destination Address

0

Data from Accumulator

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order E!yte)

4

1

Address of Operand

1

Current Operand Data

0

Address of Operand

1

Irrelevant Data (Note 1 )

1/0
(Note
3)

Address of Operand

0

New Operand Data (Note 3)

5
6

3-197

I

MC6802 • MC6808 • MC6802NS

TABLE 8 - OPERATIONS SUMMARY (CONTINUED)

R/W

Address Mode
Bnd Instructions
EXTENDED (Continued)
STS
STX

Address BUI

6

9

I

DatB Bus

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

0
1
1

Address of Operand

1

Irrelevant Data (Note 1)

Address of Operand

Operand Data (High Order Byte)

1

Op Code Address

0
0
1

2

1

Op Code Address + 1

1

Address of Subroutine (High Order Byte)

3

1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

4

1

Subroutine Starting Address

1

Op Code of Next Instruction

5
6

1

Stack Pointer

1

Stack Pointer - 1

0
0

Return Address (Low Order Byte)
Return Address (High Order Byte)

5
6
1

JSR

Line

Address of Operand + 1

Op Code

Operand Data (Low Order Byte)
Op Code

7

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

8
9

0
1

Op Code Address + 2

1

Irrelevant Data (Note 1)

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

2

4

PSH
4

PUL

1

1

Op Code Address

2

1

Op Code Address + 1

1
1

Op Code
Op Code of Next Instruction

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

0

Previous Register Contents

1

Irrelevant Data (Note 1 )

4

New Register Contents

1

Irrelevant Data (Note 1)

1

0
1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3
4

1

Stack Pointer

Accumulator Data

0
1

Stack Pointer - 1
Op Code Address

0
1
1

Op Code
Op Code of Next Instruction

1
4

TSX
4

TXS
4

RTS

2

1

Op Code Address + 1

1

3

0

Stack Pointer

1

Irrelevant Data (Note 1)

4

1

Stack Pointer + 1

1

Operand Data from Stack

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

3

0

Stack Pointer

1

Op Code of Next Instruction
Irrelevant Data (Note 1)

4

0

New Index Register

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

0

Index Register

1

Irrelevant Data

4

0
1

New Stack Pointer

1

Irrelevant Data

Op Code Address

1

Op Code

1

5

Accumulator Data

2

1

Op Code Address + 1

1

Irrelevant Data (Note 21

3

Stack Pointer

1

Irrelevant Data (Note 1)

4

0
1

Stack Pointer + 1

1

Address of Next Instruction (High
Order Byte)

5

1

Stack Pointer + 2

1

Address of Next Instruction (Low
Order Byte)

3-198

MC6802 • MC6808 • MC6802NS

TABLE 8 Address Mode
and Instructions
INHERENT (Continued)
WAI

OPERATIONS SUMMARY (CONCLUDED)

Address Bus

9

RTI

10

SWI

12

R/W
line

Data Bus

1

Op Code

1

1

Op Code Address

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

1

Stack Pointer

0

Return Address (Low Order Byte)

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

1

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1

Stack Pointer - 3

0

Index Register (High Order Byte)

7

1

Stack Pointer - 4

0

Contents of Accumulator A

8
9

1

Stack Pointer - 5

0

Contents of Accumulator B

1

Stack Pointer - 6

1

Contents of Condo Code Register

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Irrelevant Data (Note 2)

3

0

Stack Pointer

1

Irrelevant Data (Note 1)

4

1

Stack Pointer + 1

1

Contems of Condo Coda Ragister from
Stack

5

1

Stack Pointer + 2

1

Contents of Accumulator B from Stack

6

1

Stack Pointer + 3

1

Contents of Accumulator A from Stack

7

1

Stack Pointer + 4

1

Index Register from Stack (High Order
Byte)

8

1

Stack Pointer + 5

1

I ndex Register from Stack (Low Order
Byte)

9

1

Stack Pointer + 6

1

Next Instruction Address from Stack
(High Order Byte)

10

1

Stack Pointer + 7

1

Next Instruction Address from Stack
(Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Irrelevant Data (Note 1)

3

1

Stack Pointer

0

Return Address (Low Order Byte)

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

1

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1

Stack Pointer - 3

0

Index Register (High Order Byte)

7

1

Stack Pointer - 4

0

Contents of Accumulator A

8
9

1

Stack Pointer - 5

0

Contents of Accumulator B

1

Stack Pointer - 6

0

Contents of Condo Code Register

10

0

Stack Pointer - 7

1

Irrelevant Data (Note 1)

11

1

Vector Address FFFA (Hex)

1

Address of Subroutine (High Order
Byte)

12

1

Vector Address FFFB (Hex)

1

Address of Subroutine (Low Order
Byte)

1

RELATIVE
BCC
BCS
BEQ
BGE
BGT

BHI
BLE
BLS
BLT
BMI

BNE
BPL
BRA
BVC
BVS

4

BSR

8

1

1

Op Code Address

1

Op Code Address + 1

,.

Op Code

2

3

0

Op Code Address + 2

1

Irrelevant Data (Note 1)

4

0

Branch Address

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code
Branch Offset

Branch Offset

2

1

Op Code Address + 1

1

3

0

Return Address of Main Program

1

Irrelevant Data (Note 1)

4

1

Stack Pointer

0

Return Address (Low Order Byte)

5

1

Stack Pointer - 1

0

Return Address (High Order Byte)

6

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

0

Return Address of Main Program

1

Irrelevant Data (Note 1)

8

0

Subroutine Address (Note 4)

1

Irrelevant Data (Note 1)

NOTES:
1. If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high-impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
2. Data is ignored by the MPU.
3. For TST, VMA=Q and Operand data does not change.
4. MS Byte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address.

3-199

I

®

MC6803E

MOTOROLA

Advance Information
HMOS
(HIGH-DENSITY N-CHANNEL, SILICON-GATE)

8-BIT
MICROPROCESSOR

8-BIT MICROPROCESSOR

I

The MC6803E is an 8-bit microprocessing unit (MPU) designed for
uses in which the internal clock needs to be synchronized with systems,
peripherals, or other MPUs. The MC6803E also supports DMA and
dynamic RAM refresh with its halt (HALT) and bus available (BA) pins.
The MC6803E has all the features of the MC6801 microcomputer unit
except on-chip ROM and an on-chip oscillator. These on-chip features
include 128 bytes of RAM, a serial communications interface (SCI),
parallel 1/0, and a three-function programmable timer. The MC6803E
has the same enhanced MC6800 features as the MC6801, which include
64K addresss space, two 8-bit accumulators (which can be concatenated into one 16-bit accumulator), and the enhanced instruction
set, as well as extra internal interrupts.

•
•

Enhanced MC6800 Instruction Set
Upward Source and Object Code Compatible with the MC6800

•
•
•
•

Bus Compatible with the M6800 Family
Direct Source and Object Code Compatible with the MC6801
8 x 8 Multiply Instruction
64K Memory Map (Unused High Order Address Lines Can Be Used
as Input Lines)

•
•
•
•

External Clock Inputs (E and AS) Allow Synchronization
DMA Capability (Clock Stretching) with HALT and BA Pins
Serial Communications Interface (SCI)
16-Bit, Three-Function Programmable Timer

•
•
•

128 Bytes of RAM
64 Bytes of RAM Retainable During Power Down
Pin-for-Pin Compatible with MC6801 Except for HALT and BA Pins

ORDERING INFORMATION
Package Type

PIN ASSIGNMENT

VSS
HALT

AS

BA

R/W

NMi

P30

TAOl

P31

RESET

P32

VCC

P33

P20

P34

P21

P35

P22

P36

P23

P37

P24

P40

Pl0

P41

Pll

P42

P12

P43

P13

P44

(T A = O°C to 70°C)

Frequency

Order Number

Plastic
P Suffix

1.0 MHz
1.25 MHz

MC6803EP
MC6803EP-l

Ceramic
L Suffix

1.0 MHz
1.25 MHz

MC6803EL
MC6803EL-l

P14

P45

P15

P46

P16
P17

This document contains Information on a new product. Specifications and information herein
are subject to change without notice

3-200

P47
21

VCC
Standby

MC6803E

BLOCK DIAGRAM

P37
P36
P35
P34
P33
P32
P31
P30

A7/D7
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
Al/Dl
AO/DO
R/W
AS

P47
P46
P45
P44
P43
P42
P41
P40

I/O
1/0*
I/O
I/O
I/O

Port
3

TIN
TOUT
SeLK
RDATA
TDATA

P20
P21
P22
P23
P24

I

A15
A14
A13
A12
All
Al0
A9
AS

Port
4
Port
1

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

P10
Pll
P12
P13
P14
P15
P16
P17

*The output at this pin (P21) comes from the timer and not a data register.

MAXIMUM RATINGS
Rating
Supply Voltage

Symbol

Unit
V

-0.3 to + 7.0

V

o to 70

°e

-55 to + 150

°e

Symbol

Value

Rating

IiJA

50
50

°C/W

Input Voltage

Yin

Operating Temperature Range

TA
T stg

Storage Temperature Range

Value
-0.3 to + 7.0

• Vee

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic

3-201

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS oS (Vin or Voutl oS Vee.
Input protection is enhanced by connecting
unused inputs to either VDD or VSS.

MC6803E

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in DC can be obtained from:
(1)

TJ=TA+(PO-OJA)
Where:
T A = Ambient Temperature, DC

oJA = Package Thermal

Resistance, Junction-to-Ambient, DC/W

Po = PINT + PPORT
PINT= ICC x VCC, Watts -

Chip Internal Power

PPORT= Port Power Dissipation, Watts -

User Determined

For most applications PPORT~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.

I

An approximate relationship between Po and T J (if PPORT is neglected) is:
PO=K+(TJ+273 DC)

(2)

Solving equations 1 and 2 for K gives:
K = PO-n A + 273 DC) + OJNP 2

(3)

0

Where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at equilibrium)
for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1) ar,d (2) iteratively for any
value of T A.

D
DC ELECTRICAL CHARACTERISTICS IV CC = 5.0 Vdc +
- 5% V SS = 0, TA = ODC to 70 C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

E

VEIH

VCC-0.75

-

E

VEIL
VIH

VSS-O.3
VSS+4.0
VSS+20
VSS -03

-

VCC
VSS+0.6

V
V

VCC
VCC
VSS+08

V

Characteristic
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
IVin= 0 to 5.25 V)
Hi-Z Input Current
IVin=0.5to2.4V)
Output High Voltage
Ilload= -loop.A, VCC= min)
Output Low Voltage
IIload=2.0mA, VCC=min)
Darlington Drive Current
(VO= 1.5 V)

RESEJ
Other Inputs
All Inputs *

VIL

HALT, AS, NMI, IRQ1, RESET

lin

-

1.5

2.5

p.A

Pl0-P17, P20-P24, P30-P37

ITSI

-

2.0

10

p.A

All Outputs

VOH

VSS+2.4

-

VOL

-

-

All Outputs

Pl0-P17
Internal Power Dissipation (Measured at T A = ODC in Steady-State Operation)
Input Capacitance
P30-P37, AS
(Vin=O, TA=25 DC, fo= 1.0 MHz)
Other Inputs (Except E)

VCC Standby
Standby Current

-

Power Down
Power Up
Power Down

* Except mode programming levels; see Figure 8.

3-202

-

VSS+0.5

V

V
V

1.5

5.0

mA

PINT

-

-

1200

mW

Cin

-

-

4.0
4.75

-

12.5
10.0
5.25
5.25

pF

-

-

6.0

mA

IOH

VSBB
VSB
ISBB

1.0

-

-

V

MC6803E

PERIPHERAL PORT TIMING (Refer to Figures 1 and 21
Characteristics
Peripheral Data Setup Time
Peripheral Data Hold Time
Delay Time, Enable Negative Transition to Peripheral Data Valid
Ports 1, 2
Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid

FIGURE 1 -

Symbol

Min

Typ

Max

Unit

tpDSU

200

-

-

ns

tpDH

200

-

-

ns

tpWD

-

-

350

ns

tCMOS

-

-

2.0

/ls

FIGURE 2 - DATA SETUP AND HOLD TIMES
(MPU WRITE)

DATA SETUP AND HOLD TIMES
(MPU READ)

I
P10-P17
P20-P24
Inputs

PlO-P17 - - - - - - - - ~---Data Valid
P20-P24
Outputs - - - - - - - - - '
NOTES:
1. 10 k pullup resistor required for port 2 to reach 0.7 V Cc.
2. Not applicable to P21.

NOTE· Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted

FIGURE 3 -

CMOS LOAD

FIGURE 4 - TIMING TEST LOAD PORTS 1, 2, 3, 4

Vee

Test POint
Test POint

1Ii

C

R

-=

C=90 pF for
= 30 pF for
R = 24 kG for
P30-P3l,

3-203

P30-P37,
P10-P17,
P10-P17,
P40-P47,

RL=1.8kG
MMD6150
or Equlv
MMD7000
or Equlv

-=

P40-P47, R/W
P20-P24, SA
P20-P24,
R/W, SA

MC6803E

BUS TIMING (See Notes 1 and 2)
Ident.
Number

I

Characteristics

MC6803E

MC6803E-l

Symbol

Min

Max

Min

Max

Unit

tcyc

1.0

2.0

O.S

2.0

p's

1

Cycle Time

2

Pulse Width, E Low

PWEL

430

1000

360

1000

ns

3

Pulse Width, E High

PWEH

450

1000

360

1000

ns

4

Clock Rise and Fall Time

tr,tf

-

25

-

25

ns

9

Non-Muxed Address Hold Time

tAH

20

-

20

-

ns

11

Address Delay From E Low

tAD

-

260

-

220

ns

17

Read Data Setup Time

tDSR

SO

-

70

-

ns

lS

Read Data Hold Time

tDHR

10

-

10

-

ns

19

Write Data Delay Time

tDDW

-

-

200

ns

21

Write Data Hold Time

tDHW

20

-

20

-

ns

23

Muxed Address Delay from AS

tADM

-

90

-

70

ns

25

Muxed Address Hold Time

tAHL

20

-

20

-

ns

26

Delay Time E to AS Rise

tASD

100

-

SO

-

ns

27

Pulse Width, AS High

PWASH

220

-

170

-

ns

2S

Delay Time AS to E Rise

tASED

100

-

SO

-

ns

29

Usable Access Time (See Note 4)

tACC

635

-

485

-

ns

Enable Rise Time Extended

tERE

SO

-

SO

ns

Processor Control Setup Time

tpcs

200

-

200

-

ns

Processor Control Hold Time

tpCH

20

40

20

40

ns

tBA

0

300

0

300

ns

tPCPPCr

0

100

0

100

ns

Bus Available Delay Time from Enable Low
HALT Rise and Fall Time

FIGURE 5 -

BUS TIMING DIAGRAM

R/W, Address
Non Muxed

Read Data Muxed

Addr/Data
Muxed

~----~19'-----~~

Write Data Muxed

Addr/Data
Muxed

Address
Strobe (AS) _____---\

NOTES:
1. Voltage levels shown are VL~0.5 V, VH~2.4 V, unless otherwise specified.
2. Measurement points shown are O.S V and 2.0 V, unless otherwise specified.
3. Address valid on the occurrence of the latter of 11 or 23.
4 Usable access time is computed by smaller of 1 - (4 + 11 + 17) or 1 - (4+ 17 + 23 + 261.

3-204

-

225

MC6803E

The term "port," by itself, refers to all of the hardware
associated with the port. When the port is used as a "data
port" or an "I/O port" it is controlled by the port data direction register and the programmer has direct access to the
port pins using the port data register. Port 3 functions as a
time multiplexed address/data bus and does not contain
either a data direction register or a data register. Port 4 functions as a non-multiplexed high order address bus and does
not contain either a data direction register or a data register.
Port pins are labeled as Pij, where i identifies one of four
ports and j indicates the particular bit.
The MC6803E is an enhanced MC6800 MPU with additional capabilities and greater throughput. It is directly
source and object code compatible with the MC6801 and upward source and object code compatible with the MC6800.
The programming model is shown in Figure 6. A list of the
new instructions available on the MC6803E, in addition to
the M6800 instruction set, are qiven in Table 1.

INTRODUCTION
The MC6803E is an MC6801 microcomputer unit without
the internal oscillator or the on-chip ROM. The MC6803E is
used in the applications in which synchronization to another
device or system is needed, or in which clock stretching is a
requirement (i.e., direct memory access or dynamic RAM
refresh). At reset, the MC6803E is configured into one of two
operating modes to control the various functions associated
with the memory map. These operating modes are the
expanded multiplexed modes of the MC6801 (2 and 3).
The MC6803E has three 8-bit ports and one 5-bit port.
Each port except port 3 a nd port 4 consists of at least a writeonly data direction register and.a data register. The data
direction register is used to define whether corresponding
bits in the data register are configured as an input (clear) or
output (set).
FIGURE 6 -

PROGRAMMING MODEL

~

~

A
0U 7
B
B-Bit Accumulators A and B
15 - - - - - - - - - D - - - - - - - - - ~ Or 16-BltDoubleAccumulatorD

..
ll_5_ _ _ _ _ _ _ _ _
X_ _ _ _ _ _ _ _:---'0llndex Register (XI

..
ll_5_ _ _ _ _ _ _ _ _S_P_ _ _ _ _ _ _ _......
OI Stack Pointer (SPI

I..

I

1_5_ _ _ _ _ _ _ _ _P_C_ _ _ _ _ _ _ _......
O Program Counter (PCI

Condition Code Register (CCRI
I.--IL-.lY~-r'-r-r-'-:~

Carry/Borrow from MSB
Overflow
Zero
Negative
' - - - - - - - Interrupt
' - - - - - - - - Half Carry (From Bit 31

TABLE 1 Instruction
ABX
ADDD
ASLD or LSLD

NEW INSTRUCTIONS
Description

Unsigned addition of accumulator B to index register
Adds (without carryl the double accumulator to memory and leaves the sum in the double accumulator
Shifts the double accumulator left (towards MSBI one bit; the LSB is cleared and the MSB is shifted into the C bit

BHS

Branch if higher or same; unsigned conditional branch (same as BCCI

BLO

Branch if lower; unsigned conditional branch (same as BCSI

BRN

Branch never

JSR

Additional addressing mode: direct

LDD

Loads double accumulator from memory

LSL

Shifts memory or accumulator left (towards MSBI one bit; the LSB is cleared and the MSB is shifted into the C bit
(same as ASLI

LSRD

Shifts the double accumulator right (towards LSBI one bit; the MSB is cleared and the LSB is shifted into the C bit

MUL

Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator

PSHX

Pushes the index register to stack

PULX

Pulls the index register from stack

STD

Stores the double accumulator to memory

SUBD
CPX

Subtracts memory from the double accumulator and leaves the difference in the double accumulator
Internal processing modified to permit its use with any conditional branch instruction

3-205

I

MC6803E

PC1 and PCO bit locations of the program control register on
the positive edge of RESET. The operating mode may be
read from the port 2 data register as shown below, and programming levels and timing must be met as shown in Figure
9. Characteristics and a brief outline of the operating modes
are shown in Tables 2 and 3.

OPERATING MODES

I

The MC6803E has two operating modes (modes 2 and 3),
The operating modes are hardware selectable, determining
the device memory map. The mode numbers are referred to
as 2 and 3 for consistency with the MC6801 and because that
is the binary value applied to the mode programming pins
during reset. (See PROGRAMMING THE MODE.)
A 64K byte memory space is available in both operating
modes. In modes 2 and 3, port 4 provides address lines A8 to
A15.
Port 3 functions as a time multiplexed address/ data bus
with address valid on the negative edge of address strobe
(AS) and data valid while E is high. Address strobe can be
used to control a transparent D-type latch to capture
addresses AO-A7, as shown in Figure 7. This allows port 3 to
function as a data bus when E is high.
Figure 8 depicts a typical operating configuration.

PORT 2 DATA REGISTER

7

o

5

4

3

2

The operating mode is determined at reset by the levels
asserted on P20 and P21. These levels are lached into the

TYPICAL LATCH ARRANGEMENT

GNO

AS

I I

G

,.
Pmt3

Add",,/O",

1J .

1

0

Circuitry to provide the programming levels is dependent
primarily on the normal system usage of P20 and P21. If configured as outputs, the circuit shown in Figure 10 may be
used; otherwise, three-state buffers can be used to provide
isolation while programming the mode.

PROGRAMMING THE MODE

FIGURE 7 -

6

I PC1 I PCO I P24 I P23 I P22 I P21 I P20 I $03

OC

01

"".

Q1

74LS373
(Typical)

08

) Add""

Q8
"".

) 0,,,
-"

3-206

A~AJ

O~OJ

MC6803E

FIGURE 8 - EXPANDED MULTIPLEXED CONFIGURATION

VCC

Port 3
8 Lines
Port 1
8 I/O Lines
Port 2
51/0 Lines • • •~
Serial 110
16-Bit Timer

Port 4
8 Lines
Address Bus

VSS

I

VCC

I
Port3

VCC

ESE~----'"

Port 1
8 I/O
Port 2

51/0
SCI
Timer

MC6803E

.

..

Data Bus
roO-07)
Port4

16

RiW

...

E

...

'\

,..

Address Bus
(AO-A15)
R/W

"
AS

~

8

rt$

Sta ndby~
R-NMi~
IRQi~

8
Latch

EI

Clock
Circuit

f

VSS

8

I
~

ROM

8

8
8

8

8

I~

II

RAM

PIA

I

NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory should be enabled only during E high time.

FIGURE 9 -

MODE PROGRAMMING TIMING

See Figure 10
for Diode Arrangement
".- __ GVMPDD

_ ___ ....~;
" ~
-r

IP"'. P21. "21
Mode Inputs
(P20, P21)

----CI

MODE PROGRAMMING

trESTI

MPL
Mode Latch

'"

Level

(Refer to Figure 9)

Symbol

Min

Max

Mode Programming Input Voltage Low

VMPL

-

1.8

V

Mode Programming Input Voltage High

VMPH

4.0

-

Mode Programming Diode Differential (If Diodes are Used)

VMPDD

0.6

-

V
V

RESET Low Pulse Width

PWRSTL

3.0

tMPS

2.0

-

E Cycles

Mode Programming Setup Time
Mode Programming Hold Time
RESET Rise Time~ 1 P.s
RESET Rise Time< 1 P.s

tMPH

0
100

-

ns

-

Characteristic

3·207

Unit

E Cycles

MC6803E

TABLE 2 -

SUMMARY OF MC68Q3E OPERATING MODES

Memory Space Options (64K Address Space)
Mode 2 - Internal RAM
Mode 3 - No Internal RAM

TABLE 3 -

Mode

P21
PCl

P20
PCO

3
2

H
H

H

0

L
L

,

I

Legend:
I - Internal
E - External

MODE SELECTION SUMMARY

RAM

Interrupt
Vectors

Bus
Mode

E
I

E
E

MUX
MUX

L
H
L

Operating Mode

Multiplexed/No RAM
Multiplexe~/ RAM
Undefined
Undefined*

L - Logic 0
MUX - Multiplexed

H - Logic 1

*These modes are undefined for the MC6803E; device should not be operated in these modes.

FIGURE 10 -

TYPICAL MODE PROGRAMMING CIRCUIT

VCC

R2

.~ R1~ R1 ~

: '>

~

MC6803E
6

RESET>--------.---r--~------------; RESET

8

P20~------+_--.-~~----------_i P20

9

P2l~------+_--+-~~---------_i

Mode
Control
Switches

NOTES:
1. Mode 3 as shown
2. R2.C = reset time constant
3. R1 = 10 k (typical!
4. D = 1N914, 1N4001 (typical!
5. Diode Vf should not exceed VMPDD min.

3·208

(PCG)

P2l (PC1)

MC6803E

MEMORY MAPS

Figure 11. The first 32 locations of each map are reserved for
the internal register area, as shown in Table 4, with exceptions as indicated.

The MC6803E can provide up to 64K bytes of address
space. A memory map for each operating mode is shown in

FIGURE 11 -

MC6803E
Mode

MC6803E MEMORY MAPS

2

MC6803E
Mode

3

Multiplexed/ No RAM

Multiplexed/RAM

Internal Registers

Internal Registers
External Memory Space
Internal RAM

External Memory Space
External Memory Space

$FF FO ~----;:,
External Interrupt Vectors

External Interrupt Vectors

$FFFF'-----...Y

NOTE:
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and

NOTE:
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and

$OF.

$OF.

3·209

II

MC6803E

TABLE 4 - INTERNAL REGISTER AREA
Address
(Hex)

Register
Port
Port
Port
Port

1
2
1
2

Data
Data
Data
Data

External
External
External
External

I

Direction Register *
Direction Register *
Register
Register

00
01
02
03

04

Memory
Memory
Memory
Memory

05
06
07

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)

08
09
OA
OB

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
External Memory

OC
OD
OE
OF

Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register

10
11
12
13

RAM Control Register
Reserved

14
15-1F

* 1 = Output, 0= Input

MC6803E INTERRUPTS
The Me6803E supports two types of interrupt requests:
maskable and non-maskable. A non-maskable interrupt
(NMI) is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are controlled by the condition code register I bit and by individual
enable bits. The I bit controls all maskable interrupts. Of the
maskable interrupts, there are two types: IRQ1 and IRQ2.
The programmable timer and serial communications interface use an internal IRQ2 interrupt line, as shown in the
block diagram. External devices use IRQ1. An TROl interrupt
is serviced before IRQ2 if both are pending.
All IRQ2 interrupts use hardware prioritized vectors. The
single sel interrupt and three timer interrupts are serviced in
a prioritized order and each is vectored to a separate location. All interrupt vector locations are shown in Table 5.
The interrupt flowch?rt is depicted in Figure 12 and is
common to every interrupt excluding reset. DurinQ interrupt
servicing, the program counter, A accumulator, B accumulator, and condition code register are pushed onto the stack.
The I bit is set to inhibit maskable interrupts and a vector is
TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS
MSB

LSB

FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFFO

FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFF1

* IRQ2

Interrupt

Interrupt

REET
NMI
Software Interrupt (SWI)

fetched corresponding to the current highest priority interrupt. The vector is transferred to the program counter and
instruction execution is resumed. Interrupt and RESET
timing are illustrated in Figures 13 and 14.

FUNCTIONAL PIN DESCRIPTIONS
Vee AND VSS
Vee and VSS provide power to a large portion of
the MPU. The power supply should provide + 5 volts
(± 5%) to Vee. and VSS should be tied to ground. Total
power dissipation (including Vee standby) will not exceed
Po milliwatts.
Vee STANDBY
Vee standby provides power to the standby portion ($80
through $BF) of the RAM and the STBY PWR and RAME
bits of the RAM control register. Voltage requirements de-.
pend on whether the device is in a power-up or power-down
state. In the power-up state, the power supply should provide + 5 volts (± 5%) and must reach VSB volts before
RESET reaches 4.0 volts. During power down, Vee standby
must remain above VSBB (minimum) to sustain the standby
RAM and STBY PWR bit. While in power-down operation,
the standby current will not exceed ISBB.
It is typical to power both Vee and Vee standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
power-down operation. Vee standby should be tied to
ground in mode 3.

iROi
ICF (Input Capture) *
OCF (Output Compare) *
TOF (Timer Overflow) *
SCI (RDRF + ORFE + TDRE)*

AS (ADDRESS STROBE)
Address strobe is an input strobe used to strobe out the
least significant byte of an address on the 8-bit multiplexed
bus. The AS line is used to demultiplex the eight least significant bits from the data bus.

3·210

FIGURE 12 -

3:

INTERRUPT FLOWCHART

o

0)
Q)

o
w

m

w

~

...L
...L

SCI

~

TIE-TORE + RIE-IRORF + ORFEI

Cundltlon Code Register
,,'

i

,

,

Vector-PC
Modes 2-3
NMI

FFFC-FFFD Non-Maskable Interrupt

SWI

FFFA-FFFB Software Interrupt

IRQl

FFF8-FFF9

Maskable Interrupt Request 1

ICF

FFF6-FFF7

Input Capture Interrupt

OCF

FFF4-FFF5

Output Compare Interrupt

TOF

FFF2-FFF3

Timer Overflow Interrupt

SCI

FFFO-FFFl

SCI Interrupt (TORE + RORF + ORFEI

A

..

iii
3:
(")
FIGURE 13 -

Last Instruction

~

en

INTERRUPT SEQUENCE

CO
0

w

Cycle
#1

#3

#2

#4

I

#5

I

#7

#8

ACCA

ACCB

#6

#9

I

#10

I

#11

I

#12

m

I

Internal
Address Bus

IRQ1

~ I-+-tpcs

NMI or IRQ2

\

~ !+-tpcs

Internal
Data Bus _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Op Code Op Code

w
N

PC 0-7

PC8-15

X 0-7

X 8-15

Irrelevant
Data

Vector
LSB

Vector
MSB

First Ins! of
Interrupt Routine

~

\

Internal R/Vil

CCR

~

I\,)

FIGURE 14 - RESET TIMING

%\\\%\\\\~~ ~~~'0. LJUl,
Vcc
RESET

InternaB,
Address us
Internal R/W
Internal
Data Bus

~:~~~
I..

II

I
'RC

_ _ _-----.,/ I

I

,~

(:;3'~'pcs
_I
0.8 V

.~''I---,pcs
1 _

08 V ~-_ _

4.0 V

\\\\\\~\\\\\\\\\\~ h\\\\~\\\\\\\\\\\\\\\\\\\\\~ /FFFE

SillTh\\\\\\\\\\'{ (b\\\\\\\\\\\\\\\\\\\\\\\\\\?

FFFE

~~

I I

&\\\\\\\\S\\\\\\\S 1\\\\\\\\\\\\\\\\\\S\\\\\\\\\wcj
PC 8-15 PC 0-7

~ r~otValid

First
Inst ruction

'=

MC6803E

HALT

BA (BUS AVAILABLE)

This level sensitive active low input causes the MPU to halt
all activity when a low is applied to it. When the HALT input
is low, the machine stops at the end of an instruction and
bus available (BA) goes to a high state. During this time
read/write (R/W) is high and the address bus displays the
address of the next instruction. See Figure 15 for timing
requirements.
To debug programs, it is advantageous to step through
programs one instruction at a time. To do this, HALT must
be brought high for one clock cycle and then returned low as
shown in Figure 15. The instruction illustrated is a one byte,
two cycle instruction, such as CLRA. When the HALT line
goes low, the MC6803E is halted after completing execution
of the current instruction.

This active high output is used to indicate when the
MC6803E is halted. Other devices may then use the address
and data buses, providing care is taken to prevent contention. Alternatives include three-state buffers on the address
and data buses, or three-state buffers on the address bus
and holding AS low during BA high. Note that the BA line
will also go high when a wait instruction is executed.

FIGURE 15 -

Last Cycle
of Instr.

R/W (READ/WRITE)

The R/W output is used to indicate the direction of data
transfer on the data bus. A logic low indicates that the MPU
is writing data onto the bus and a logic high indicates that
the M PU is reading data from the bus.

HA'i:T AND

I

BA TIMING

I

Instruction
Fetch

I

Instruction
Execution

HAL T-----1"'\

BA ____~---------~

R/W

MUX
Addressl Data

~~~~~sx_Addr---i\°"lx

Add,

O"k

dd

'

°"1

°'1

Add,

Add,

°"1

Add,

°"1

Add,

°l

Add,

O"~

RESET

E (ENABLE)

This input is used to reset the inte(nal state of the device
and provide an orderly start-up procedure. During power up,
RESET must be held below 0.8 volts until 1) VCC reaches
4.75 volts and E is stable, and 2) until VCC standby reaches
4.75 volts. RESET must be held low at least three E cycles if
asserted during power-up operation. During the rising edge
of RESET, the MC6803E also latches in its operating mode.
RESET timing is shown in Figure 14.

This is an input clock used primarily for address and data
bus synchronization. This input should have some provision
to obtain the specified logical high level which is greater than
standard TTL levels. Two examples of clock generating circuits are presented in Figures 16 and 17.
Enable is the primary MC6803E system timing signal and
all timing data specified as. cycles is assumed to be
referenced to this clock unless otherwise noted.

3-213

I

MC6803E

FIGURE 16 -

CLOCK CIRCUIT EXAMPLE 1

VCC
Schematic

AS

Ul SN74LS175
U2 SN75LS08

I

tRC= 10 P.s
Timing
8 MHz

DA

OA

J

OB

r-

OC
OD

AS

J

L

NMI (NON-MASKABLE INTERRUPT)

An NMI negative edge requests an MPU interrupt sequence, but the current instruction will be completed before
it responds to the request. The MPU will then begin an interrupt sequence. Finally, a vector is fetched from $FFFC and
$FFFD, transferred to the program counter, and instruction
execution is resumed. NMI typically requires a 3.3 kilohm
(nomina\) resistor to VCe. There. is no internal NMI pullup
resistor. NMI must be held low for at least one E cycle to be
recognized under all conditions.
IRQ1 (MASKABLE INTERRUPT REQUEST 1)

IRQ1 is a level-sensitive input which can be used to request an interrupt sequence. The MPU will complete the current instruction before it responds to the request. If the interrupt mask bit (I bit) in the condition code register is clear, the

3-214

M PU will begin an interrupt sequence. A vector is fetched
from $FFF8 and $FFF9, transferred to the program counter,
and instruction execution is resumed.
IRQ1 typically requires an external 3.3 kilohm (nomina\)
resistor to VCC for wire-OR applications. IRQ1 has no internal pullup resistors.

P10-P17 (PORT 1)

Port 1 is a mode independent 8-bit 1/0 port with each line
an input or output as defined by the port 1 data direction
register. The TTL compatible three-state output buffers can
drive one Schottky TTL load and 30 picofarads, Darlington
transistors, or CMOS devices using external pullup resistors.
It is configured as a data input port during reset. Unused
lines can remain unconnected.

MC6803E

FIGURE 17 - CLOCK CIRCUIT EXAMPLE 2
Schematic

Vec

Vce
150
3.3 k

U3c )()----AS

o

PRE
Q

NC

U2

}-----tCLK

CLR

a~.,.,.,.....,..,.".~

Ul, U2-SN74LS74
U3-SN74LS02

Timing

JlSUL

4f o

Q (Ula)

Q(U2)

'---__~I
....IIl'--____---IIlL.--_

AS _ _ _ _ _

3-215

I

MC6803E

P20-P24 (PORT 2)

I

RAM CONTROL REGISTER

Port 2 is a mode-independent, 5-bit, mUltipurpose I/O
port. The voltage levels present on P20 and P21 on the rising
edge of RESET determine the operating mode of the MPU.
The entire port is then configured as a data input port. The
port 2 lines can be selectively configured as data output lines
by setting the appropriate bits in the port 2 data direction
register. The port 2 data register is used to move data
through the port. However, if P21 is configured as an output, it will be tied to the timer output compare function and
cannot be used to provide output from the port 2 data
register.
Port 2 can also be used to provide an interface -for the
serial communications interface and one of the timer input
edge functions. These configurations are described in PROGRAMMABLE TIMER and SERIAL COMMUNICATIONS
INTERFACE.
The port 2 three-state TTL-compatible output buffers are
capable of driving one Schottky TTL load and 30 picofarads,
or CMOS devices using external pullup resistors.

PORT 2 DATA REGISTER

7

6

5

4

3

2

x

x

x

x

x

o
x

Bit 0-5 Not used.
Bit 6 RAM Enable (RAME) - This read/write bit can be
used to remove the entire RAM from the internal
memory map. RAME is set (enabled) during reset provided standby power is available on the positive edge
of RESET. If RAME is clear, any access to a RAM address is external. If RAM E is set and not in mode 3, the
RAM is included in the internal map.
Bit 7 Standby Power (STBY PWR) - This bit is a read/
write status bit which, when cleared, indicates that
VCC standby has decreased sufficiently below VSBB
(minimum) to make data in the standby RAM suspect.
It can be set only by software and is not affected during reset.

76543210

o

I PCl I PCO I P24 I P23 I P22 I P21 I P20 I $03

PROGRAMMABLE TIMER

P30-P37 (PORT 3)
Port 3 consists of a time multiplexed address (A7-AO) and
data bus (D7-DO) where address strobe (AS) can be used to
demultiplex the two buses. The port is held in a highimpedance state between valid address and data to prevent
bus conflicts. The TTL-compatible three-state output buffers
can drive one Schottky TTL load and 90 picofarads.
P4Q-P47 (PORT 4)
Port 4 functions as half of the address bus and provides A8
to A 15. Port 4 can drive one Schottky TTL load and 90
picofarads and is the only port with internal pullup resistors.
Unused lines can remain unconnected.

RESIDENT MEMORY
The MC6803E provides 128 bytes of on-board RAM. One
half of the RAM is powered through the VCC standby pin
and is maintainable during VCC power down. This standby
portion of the RAM consists of 64 bytes located from $80
through $BF.
Power must be supplied to VCC standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM control register.
RAM CONTROL REGISTER ($14)
The RAM control register includes two bits which can be
used to control RAM accesses and determine the adequacy
of the standby power source during power-down operation.
It is intended that RAME be cleared and STBY PWR be set
as part of a power-down procedure.

3-216

The programmable timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths c·an vary from several microseconds to many seconds. A block diagram of the timer is
shown in Figure 18.
COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all ones.
OUTPUT COMPARE REGISTER ($OB:OC)
The output compare register is a 16-bit read/write register
used to control an output waveform or to provide an arbitrary timeout flag. It is compared with the free-running
counter on each E cycle. When a match occurs, OCF is set
and OLVL is clocked to an output level register. If port 2, bit
1 is configured as an output, OLVL will appear at P21 and the
output compare register and OLVL can then be changed for
the next compare. The function is inhibited for one cycle
after a write to its high byte ($OB) to ensure a valid compare.
The output compare register is set to $FFFF at RESET.
INPUT CAPTURE REGISTER ($QD:OE)
The input capture register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always
senses P20 even when configured as an output. An input
capture can occur independently of ICF: the register always

MC6803E

FIGURE 18 -

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

MC6803E Internal Bus

I
Status
Register
$08

Register
Bit 1
Port 2

DDR

I
Output Compare Pulse

___ J

Output Input
Level
Edge
Bit 1
Bit 0
Port 2 Port 2

Bit 1 Input Edge (IEDG) - IEDG is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register:
IEDG = 0 transfer on a negative edge
IEDG = 1 transfer on a positive edge

contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU
read. The input pulse width must be at least two E cycles to
ensure an input capture under all conditions.
TIMER CONTROL AND STATUS REGISTERS ($08)

Bit 2 Enable Timer Overflow Interrupt (ETO!) - When set,
an IR02 interrupt will be generated when the timer
overflow flag is set; when clear, the interrupt is inhibited. ETOI is cleared during reset.

The timer control and status register (TCSR) is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. The three most significant bits provide the timer
status and indicate if:
1. a proper level transition has been detected,
2. a match has occurred between the free-running
counter and the output compare register, and
3. the free-running counter has overflowed.
Each of the three events can generate an I R02 interrupt and
is controlled by an individual enable bit in the TCSR.

Bit 3 Enable Output Compare Interrupt (EOC!) - When set,
an IRQ2 interrupt will be generated when output compare flag is set; when clear, the interrupt is inhibited.
EOCI is cleared during reset.
Bit 4 Enable Input Capture Interrupt (EICI) - When set, an
IR02 interrupt will be generated when input capture
flag is set; when clear, the interrupt is inhibited. EICI is
cleared during reset.

TIMER CONTROL AND STATUS REGISTER (TCSR)

7

654

3

2

1

0

Bit 5 Timer Overflow Flag (TOF) - The TOF is set when the
counter contains all ones ($FFFF). It is cleared by
reading TCSR (with TOF set) then reading the counter
high byte ($09), or during reset.
Bit 6 Output Compare Flag (OCF) - OCF is set when the
output compare register matches the free-running
counter. OCF is cleared by reading the TCSR (with
OCF set) and then writing to output compare register
($OB or $OC), or during reset.

Bit 0 Output Level (OLVL) - OLVL is clocked to the output
level register by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set. OLVL is cleared during reset.

3-217

MC6803E

Bit 7 Input Capture Flag (ICF) - When ICF is set, it indicates a proper level transition; it is cleared by reading
TCSR (with ICF set) and then the input capture
register high byte ($OD), or during reset.

PROGRAMMABLE OPTIONS
The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or bi-phase
• clock: external or internal bit rate clock
• baud: one of 4 per E clock frequency, or external clock
(8x desired baud)
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver
• clock output: internal bit rate clock enabled or disabled
to P22

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

I

SERIAL COMMUNICATIONS REGISTERS
The serial communications interface includes four
addressable registers as depicted in Figure 19. It is controlled
by the rate and mode control register and the transmit/
receive control and status register. Data is transmitted and
received utilizing a write-only transmit register and a readonly receive register. The shift registers are not accessible to
software.

WAKE-UP FEATURE
In a typical serial loop mUltiprocessor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPUs to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
consecutive ones or during reset. Software must provide for
the required idle string between consecutive messages and
prevent it within messages.

RATE AND MODE CONTROL REGISTER (RMCR) ($10)The rate and mode control register controls the SCI bit rate,
format, clock source, and under certain conditions the configuration of P22. The register consists of four write-only bits
which are cleared during reset. The two least Significant bits
control the bit rate of the internal clock and the remaining
two bits control the format and clock source.

FIGURE 19 -

Bit 7

SCI REGISTERS

Rate and Mode Control Register
CCl

I

Bit 0

I Icco I Isso 1$10
SSl

T ransmit/ Receive Control and Status Register

RDRF IORFE/TDRE! RIE!

RE

I TIE I TE

I

WU

1$11

Receive Data Register

$12

(Not Addressable)

10

12

Transmit Data Register

3-218

MC6803E

RATE AND MODE CONTROL REGiSTER

7

6

5

43210

x

x

x

x

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER
76543210

I CC1 I cco I SS1 I sso I $10

!RDRFloRFE!TDRE! RIE ! RE ! TIE! TE ! WU 1$11

Bit 1: Bit 0 SS1 :SSO Speed Select - These two bits select
the baud when using the internal clock. Four
rates may be selected which are a function of the
MPU input frequency. Table 6 lists bit time and
rates for three selected M PU frequencies.

Bit 0 Wake-up on Idle line (WU) - When set, WU enables
the wake-up function; it is cleared by ten consecutive
ones or during reset. WU will not set if the line is idle.
Bit 1 Transmit Enable (TE) - When set, the P24 DDR bit is
set and cannot be changed. P24 DDR will remain set if
TE is subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P24 and a
preamble of nine consecutive ones is transmitted. TE is
cleared during reset.

Bit 3: Bit 2 CC1 :CCO Clock Control and Format Select
These two bits control the format and select the
serial clock source. If CC1 is set, the DDR value
for P22 is forced to the complement of CCO and
cannot be altered until CC1 is cleared. If CC1 is
cleared after having been set, its DDR value is
unchanged. Table 7 defines the formats, clock
source, and use of P22.

When set, an IR02
Bit 2 Transmit Interrupt Enable (TIE)
is enabled when TDRE is set; when clear, the interrupt
is inhibited. TIE is cleared during reset.

If both CC1 and CCO are set, an external TTL compatible
clock must be connected to P22 at eight times (8 x) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%), If CC1 :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

Bit 3 Receive Enable (RE) - When set, the P23 DDR bit is
cleared and cannot be changed. P23 DDR will remain
clear if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared during reset.

NOTE
The source of SCI internal bit rate clock is the timer
free-running counter. An MPU write to the counter can
disturb serial operations.

Bit 4 Receiver Interrupt Enable (RIE) - When set, an IR02
interrupt is enabled when RDRF and/or ORFE is set;
when clear, the interrupt is inhibited. RIE is cleared
during reset.

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR) ($11) - The transmit! receive control
and status register controls the transr:nitter, receiver, wakeup feature, and two individual interrupts, and monitors the
status of serial operations. All eight bits are readable while
bits 0 to 4 are also writable. The register is initialized to $20
by RESET.
TABLE 6 -

Bit 5 Transmit Data Register Empty (TDRE) - TDRE is set
when the transmit data register is transferred to the
output serial shift register, or during reset. It is cleared
by reading the TRCSR (with TDRE set) and then
writing to the transmit data register. Additional data
will be transmitted only if TDRE has been cleared.

SCI BIT TIMES AND RATES

614.4 kHz
SS1:SS0

E

0

0

0

1

1
1

1.0 MHz

1.2288 MHz

Baud

Time

Baud

+16

38400.0

62500.0

16.0 JLs

76800.0

13.0 JLs

+ 128

4800.0

26 JLS
208.3 JLs

7812.5

128.0 JLs

9600.0

104.2 JLs

0

+ 1024

600.0

1.67 ms

976.6

1.024 ms

1200.0

833.3 JLs

1

+4096

150.0

6.67 ms

244.1

4.096 ms

300.0

·3.33 ms

76800.0

13.0 JLs

125000.0

8.0 JLs

153600.0

6.5 JLs

External (P22)·

Time

Baud

• USing maximum clock rate

TABLE 7 -

SCI FORMAT AND CLOCK SOURCE CONTROL

CC1:CCO

Format

Clock
Source

Port 2
Bit 2

00

Bi-Phase

Internal

Not Used

01

NRZ

Internal

Not Used

10

NRZ

Internal

Output

11

NRZ

External

Input

3-219

Time

I

MC6803E

INSTRUCTION SET

Bit 6 Overrun Framing Error (OR FE) - If set, OR FE indicates either an overrun or framing error. An overrun is
a new byte ready to transfer to the receive data register
with RDRF still set. A receiver framing error has occurred when the byte boundaries of the bit stream are not
synchronized to the bit counter. An overrun can be
distinguished from a framing error by the state of
RDRF: if RDRF is set, then an overrun has occurred;
otherwise, a framing error has been detected. Data is
not transferred to the receive data register in an overrun condition. Unframed data causing a framing error
is transferred to the receive data register; however,
subsequent data transfer is blocked until the framing
error flag is cleared. ORFE is cleared by reading the
TRCSR (with ORFE set) then the receive data register,
or during reset.

I

As stated earlier, the MC6803E is upward source and object code compatible with the MC6800. Execution times of
key instructions have been reduced and several new instructions have been added, including a hardware multiply.
In addition, two new special opcodes, 4E and 5E, are provided for test purposes. These opcodes force the program
counter to increment like a 16-bit counter, causing address
lines to increment until the device is reset. These opcodes
have no mnemonics.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addreSSing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and two codes reserved for test purposes.

Bit 7 Receive Data Register Full (RDRF) - RDRF is set
when the input serial shift register is transferred to the
receive datil register, or during reset.

PROGRAMMING MODEL

A programming model for the MC6803E is shown in Figure
6. The registers are defined in the following paragraphs.

SERIAL OPERATIONS

The SCI is initialized by writing control bytes first to the
rate and mode control register and then to the transmit/
receive control and status register. When TE is set, the output of the transmit serial shift register is connected to P24
and serial output is initiated by transmitting a 9-bit preamble
of ones.
A t this point, one of two situations exists: 1) if the transmit
data register is empty (TDRE= 1), a continuous string of
ones will be sent indicating an idle line, or 2) if a byte has
been written to the transmit-data register (TDRE=O), it will
be transferred to the output serial shift register (synchronized with the bit rate clock), TDRE will be set, and transmission will begin.
The start bit (0), eight data bits (beginning with bit 0), and
a stop bit (1) will be transmitted. If TDRE is still set when the
next byte transfer should occur, ones will be sent until more
data is provided. In bi-phase format, the output toggles at
the start of each bit and at half-bit time when a one is sent.
Receive operation is controlled by RE which configures P23
as an input and enables the receiver. SCI data formats are illustrated in Figure 20.

FIGURE 20 -

ACCUMULATORS - The MPU contains two 8-bit
accumulators, A and B, which are used to store operands
and results from the arithmetic logic unit (ALU). They can be
concatenated and referred to as the D (double) accumulator.
Any operation which modifies the D accumulator
automatically modifies the A and B accumulators.
INDEX REGISTER - The index register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.
STACK POINTER - The stack pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/ pullup (LI FO) queue. The stack resides in
random-access memory at a location defined by the programmer.

PROGRAM COUNTER - The program counter is a 16-bit
register which always points to the next instruction.

SCI DATA FORMATS

Output
Clock

NRZ

Format

1,

Bi-Phase
Format
Idle State

Bit

Bit
4

Data: 01001101 ($40)

3-220

7

Stop

MC6803E

TABLE 8 OP

MNEM

MOOE

-

#

Nap

INHER

2

I

()()

01
02

-

#

OP

MNEM

MOOE

34

DES

'NHER

3

I

35

TXS

3

I

36

PSHA

3

I

OP

CPU INSTRUCTION MAP
OP

MNEM

MODE

ASL

INDXD

6

2

9C

CPx

DIR

ROL

6

2

9D

JSR

DEC

6

2

9E

LDS
STS

DIR

4

D3

ADDD

5

SUBA

INDXD

4

2

D4

ANDB

3

2

4

2

05

BITB

3

2

3

2

A2

SBCA

4

2

D6

LDAB

3

INDXD

6

2

A3

SUBD

6

2

D7

STAB

3

2
2

EXTND

6

3

A4

ANDA

4

2

D8

EORB

3

2

A5

BITA

4

2

D9

ADCB

3

2

A6

LDAA

4

aRAB

3

6

3

A7

STAA

4

2
2

DA

COM

DB

AD DB

3

2
2

LSR

6

3

A8

EORA

4

2

DC

LDD

4

2

A9

ADCA

4

2

DD

STD

2

ROR

6

3

AA

ORAA

4

4

2

6

3

AB

ADDA

4

DE
OF

LDX

ASR

2
2

It

4

76

77

STX

DIR

4

2

78

SUBB

INDXD

4

6C

I

6D

INC
TST

06

TAP

2

I

3A

ABX

6E

JMP

07

TPA

2

I

3B

RTI

3
IU

I
I

6F

CLR

3

I

3C

PSHX

4

I

70

NEG

D,X

3
2

I

3D

MUL

10

I

I

3,

WAI

72

3F

SWI

9
12

1

I

I

73

I

40

NEGA

2

I

74

COMA

2

I

OD

SEC

2

I

41

DE

eLI

2

I

42

OF

SEI

2

I

43

10

SBA

2

I

44

II

CBA

2

I

45

2
1

CMPA

I

5

CLC

SBCB

#

3

3
3

AI

5

RTS

OC

D2

-

AO

6B

PULX

39

2
2

DIR

2

I

38

I

SEV

SUBB
CMPB

2

3

I

3

08

MODE

DO
DI

OP

6

PSHB

3

CLV

MNEM

2

6

37
LSRD

08

#

5
5

2
2

ASLD

09
OA

~

-

2
2
2

05

INX

#

MODE

68
69
6A

04

03

-

MNEM

1

9F

71

75

4

LSRA

2

I

ASL

6

3

AC

CPX

6

2

[0

79

ROL

6

3

AD

JSR

6

2

EI

CMPB

4

2
2

12

46

RORA

2

I

7A

DEC

6

3

AE

LDS

5

2

E2

SBCB

4

2

13

47

ASRA

2

I

7B

STS

INDXD

AS LA

2

I

7C

INC

6

3

BO

SUBA

EXTND

4

3

,4l3

AD DO

48

"

2

14

ANDB

6
4

2
2

15

49

ROLA

2

I

7D

TST

6

3

BI

CMPA

4

3

C5

RITB

1

2

DECA

2

I

7E

JMP

3

3

B2

SBCA

4

3

E6

LDAB

4

2

7F

CLR

EXTND

6

3

B3

SUBD

6

3

E7

STAB

4

2

INCA

2
2

I

80

SUBA

IMMED

2

2

B4

ANDA

4

3

E8

fORB

4

2

I

81

CMPA

2

2

B5

BITA

4

3

E9

ADCB

4

2

82

SBCA

2

2

B6

LDAA

4

3

EA

ORAB

4

2

EB

ADDB

16

TAB

2

I

4A

17

TBA

2

I

4B

18
19

4C
DAA

INHER

2

I

IA

4D

TSTA

4E

T

4F

CLRA

2

1

1C

50

NEGB

2

I

10

51

IB

ABA

INHER

2

I

IE

52

IF
20
21

BRA

REL

AF

4

3

STAA

4

84

ANDA

2

2

B8

EORA

85

BITA

2

2

B9

ADCA

4
4

lOAA

2

2

BA
BB

ADDA

EORA

2

2

BC

CPX

2

2

BD

JSR

83

86

53

COMB

2

1

87

3

2

54

LSRB

2

1

88

55

SUBD

ADCA

B7

ORAA

3

4

2

3

EC

lOD

5

2

3
3

ED

STD

5

2

4

3

EF

STX

INDXD

5

2

6

3

FO

SUBB

EXTND

4

3

4

EE

LDX

3

FI

2

2

BE

LDS

5

3

F2

SBCB

2

2

BF

STS

EXTND

5

3

F3

ADDD

4

3

CO

SUBB

IMMED

2

2

F4

AN DB

6

CMPB

5

4

2

3

3

2

22

BHI

3

2

56

RDRB

2

I

8A

ORAA

23

BLS

3

2

57

ASRB

2

1

8B

ADDA

24

Bce

3

2

58

ASLB

2

1

8C

CPX

25

BCS
BNE

3

2

2

I

8D

BSR

REL

6

2

CI

CMPB

2

2

F5

BITB

3

2

59
5A

ROLB

26

DECB

2

I

IMMED

3

3

C2

SBCB

4

3

2

5B

C3

ADDD

3

F6
F7

LDAB

3

2
4

2

BEO

8E
8F

LDS

27

STAB

4

3

28

BVC

3

2

5C

ANDB

2

2

F8

EORB

4

3

29

BVS

3

2

5D

2A

BPL

3

2

5E

T

2B

BMI

3

2

5F

CLRB

INHER

2C

BGE

3

2

60

NEG

INDXD

2D

BLT

3

2

61

BRN

2E

BGT

,

2F

30

BLE
TSX

31

INS

32

PULA

33

PULB

89

INCB
TSTB

3

2

62

REL
INHcR

3

2
I

63

COM

64

LSR

t

3
4

1

65

I

66

ROR

4

1

67

ASR

3

1

INDXD

I;
IMMED

"

1

90

SUBA

2

1

91

CMPA

92

SBCA

2

1

93

SUBD

6

2

94

ANDA

3

2

C8

EORB

2

2

FC

LDD

95

BITA

3

2

C9

ADCB

2

2

FD

STD

2

2

FE

LOX

W

2

2

FF

STX

EXTND

3

3

~

3

2

C5

BITB

2

2

F9

ADCB

4

3

3

2

C6

LDAB

2

2

FA

ORAB

4

3

5

2

C7

FB

ADDB

4

3

5

3

5

3

5

3

5

3

3

2

CA

6

2

97

STAA

3

2

CB

ADDB

6

2

EORA

3

2

CC

LOO

ADCA

3

2

CD

ORAA

3

2

CE

ADDA

3

2

CF

2
2

9B

3

C4

LDAA

6

3

2

96

6

4

3

ORAB

98
99
9A

3
3

4

2

DIR

4
6

LDX

,
IMMED

3

* UNDEFINED OP

CODE

3

NOTES:
Addressing Modes
INHER .. Inherent
INDXD .. Indexed
IMMED .. Immediate
REL .. Relative
EXTND .. Extended DIR .. Direct
Unassigned opcodes are indicated by ..... and should not be executed
Codes marked by "T" force the PC to function as a 16-bit counter.

CONDITION CODE REGISTER - The condition code
register indicates the results of an instruction and includes
the following five condition bits: negative IN), zero IZ),
overflow IV), carry/borrow from MSB Ie), and half carry
from bit 3 (H) These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask I I bit) and inhibits all maskable interrupts when set. The two unused bits,
B6 and B7, are read as ones.
ADDRESSING MODES
Six addressing modes can be used to reference memory.
A summary of the addressing modes for all instructions is
presented in Tables 9 through 12, where execution times are
provided in E cycles. Instruction execution times are summarized in Table 13. With an input frequency of 4 megahertz,
one E cycle is equivalent to one microsecond. A description
of selected instructions is shown in Figure 21.

IMMEDIATE ADDRESSING - The operand or immediate
bytels) is contained in the following bytels) of the instruction
where the number of bytes matches the size of the register.
These are two or three byte instructions.
DIRECT ADDRESSING - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access. In most applications, the 256-byte area is reserved for frequently referenced
data.
EXTENDED ADDRESSING - The second and third bytes
of the instruction contain the absolute address of the
operand. These are three byte instructions.

3-221

I

MC6803E

INDEXED ADDRESSING - The unsigned offset contained in the second byte of the instruction is added with carry to
the index register and 'used to reference memory without
changing the index register. These are two byte instructions.

RELATIVE ADDRESSING - Relative addressing is used
only for branch instructions. If the branch condition is true,
the program counter is overwritten with the sum of a signed
single byte displacement in the second byte of the instruction and the current program counter. This provides a
branch range of - 126 to + 129 bytes from the first byte of
the instruction. These are two byte instructions.

INHERENT ADDRESSING - The operand(s) is a register
and no memory reference is required. These are single byte
instructions.

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed

Pointer Operations

I

Compare Index Register

CPX
DEX

8C

4

Index

Extnd

# Op -

# Op

3 9C

2 AC 6

2 8C 6

5

Inherent

-

# Op -

MNEM Op -

Decrement Index Register

Direct

Boolean/
Arithmetic Operation

-

#

09

3

1 X-l--X

3

1 SP-l--SP

# Op

Decrement Stack Pointer

DES

34

Increment Index Register

INX

08 3

1 X+ l--X

Increment Stack POinter

INS

31

1 1 SP+l--SP

Load Index Register

LDX

CE

3

3 DE 4

2 EE

5

2

5

3

M--XH.IM+lI--X~

Load S tack POinter

LDS

8E

3

3 9E

2 AE

5

2 BE 5

3

M -- SPH.IM + 11 -- SPL

Store Index Register

STX

DF 4

2

EF

5

2

FF

5

3

XH--M,XL --IM+lI

Store S tack Pointer

STS

9F

2 AF

5

2 BF 5

3

SPH--M.SPL --IM+lI

Index Reg -- Stack Pointer

TXS

4
4

FE

3

35

3

3

Stack Pntr --Index Register

TSX

30

Add

ABX

3A 3

4

3

2

H

I

N

Z

1 0
V C

·· ·· · t · ·
·· · ·· · · ·
··· ··· tf .·tt · ···
·· ·· t f ··
··· ·· ·· ·· ·· ···
·····
· · ·
I I I I

X- MM+ 1

3

5

I

R

1 SP+l--X
1 B+X--X

PSHX

3C

4

1 XL --MSp.SP-l-SP
XH -- MSp.SP-l -- SP

Pull Data

PULX

38

5

1 SP+ l--SP.MSP--XH
SP+ l--SP.MSP--XL

R
R

1 X-l--SP

Push Data

R

I I

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)

,
Accumulator and
Memory Operations

Immed
MNEM Op

-

Condition Codes
Direct

# Op -

Index

# Op -

# Op -

Inher

Extend

# Op -

Boolean
Expression

#

Add Accumulators

ABA

1B 2

1 A+B--A

Add B to X

ABX

3A

1 oo:B+ X -- X

Add with Carry
Add

3

2

2 99

2 A9 4

2 B9 4

3

ADCB C9

2

2 D9 3

2

2

F9

4

3

B+ M+ C--B

ADDA 8B

2

2 9B

2 AB 4

2 BB 4

3

A+M--A
B+M--A

3

E9

4

A+M+C--A

ADDB CB 2

2 DB 3

2 EB 4

2 FB 4

3

Add Double

ADDD C3 4

3 D3 5

2

2

6

3

D+M:M+l--D

And

ANDA 84

2

2 94

2 A4 4

3

A.M--A

ANDB C4

2

2 D4 3

3

B.M -- B

78

3

Shift Left. Arithmetic

3

2

ASL

E3

6

F3

E4

4

2 B4 4
2 F4 4

68

6

2

6

ASLA
ASLB
Shift Left Dou ble
Shift Right. Arithmetic

Bit Test

ASLD
ASR

Clear

Compare
l's Complement

6

2 77 6

1

05

1

3

1

3

ASRA

47

2

1

ASRB

57

2

1

BITA 85
BITB

Compare Accumulators

67

48 2
58 2

b7

2 B5 4

3

A·M

C5 2

2 D5 3

2

2

3

B·M

E5

4

F5

4

11

2

1 A- B

CLRA

4F

2

1 oo-A

CLRB

5F

2

1 oo-B

CBA
CLR

6F

6

2

7F

6

oo-M

3

CMPA 81

2

2 91

3

2 Al 4

2 Bl

4

3

A-M

CMPB Cl

2

2

3

2 E1

4

2

Fl

4

3

B-M

63

6

2 73 6

3

COM

D1

M-M

COMA

43

2

1 A-A

COMB

53 2

1 B-B

3-222

--

-- a

qilli IIII-@]

2 A5 4

2

1

N

Z

V C

0

· ·· · · · ·
··
·· ··
··
·
·· ··
··· ···
t t t t
··· ·· tf tf t ·t
It
··· ·· f If f ·f
·· ··
t t t t
··· ··· tit
··t t
1 J f 1

R

b7

2 95 3

3

I

R

@J--l11I11111bO

2

4

H

f

ADCA 89

3

5

bO

R

R

··

R

R

S

R

R

S

R

R

R

S

R

R

I It I

I

R

S

t t

R

S

R

S

MC6803E

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed
MNEM Op

Decimal Adjust, A

DAA

Decrement

DEC

Exclusive OR

Increment

Load Accumulators

-

Direct
# Op -

Index

Extend

Inher

# Op -

# Op -

# Op -

6A 6

2 7A 6

3

19

2

1 A-1-A

5A

2

1 B-1-B

EORA 88

2

2

98

3

2 A8 4

2

B8 4

3

AEBM-A

EORS C8

2

2 08

3

2

E8

4

2

F8

4

3

BEBM-B

6C

6

2 7C

6

3

INC

4C

2

1 A+1-A

INCB

5C

2

1 B+1-B

2 A6 4

2

B6 4

3

M-A

E6

4

2

F6

4

3

M-B

2 EC

5

2 FC 5

3

MM+1-D

68

6

2

3

LDAA 86

2

2 96

LDAS C6

2

2 06 3

2

CC 3

3 DC 4

3

78

6

LSLA

48

2

1

LSLB

58

2

1

05

3

2

LSLD
LSR

64

6

2

74

6

3

LSRA

44

2

1

LSRB

54

2

1

LSRD

04

3

1

1 oo-A~A

NEGB

50

2

1 00- B-B

NOP

01

2

1 PC+ 1-PC

6

2

70

6

ORAA 8A 2

2 9A

3

2 AA 4

2 SA 4

3

A+M-A

ORAB CA 2

2 DA 3

2 EA 4

2 FA 4

3

B+M-S

Subtract Accumulator

ROL

1 B-

4

1 Stack-A

69

6

2

79

6

33

4

1 Stack-S

@].-111111111---0

49

2

1

59

2

1

RORA

46

2

1

RORS

56

2

1

SSA

10

2

1 A-B-A

66

2

SBCB C2 2

2

92

3

2 02 3
97

3

2 A2

6

4

2

2

76

6

B2 4

b7

@]-11111111r-@]
b7

A-M-C-A

2 E2 4

2

F2

4

3

B-M-C-B

4

2

B7 4

3

A-M

F7

2 A7

STAB

07 3

2 E7 4

2

4

3

B-M

STD

DO 4

2 ED 5

2 FD 5

3

D-M:M+1

SUBA 80

2

BO 4

3

A-M-A

4

2

FO

4

3

B-M-B

2 A3 6

2

B3 6

3

2

90

2

DO 3

2

SUBO 83

3

93

4

3

2 AO 4

2

SUBB CO 2

5

EO

TAB
TBA
TST

60 6

2 70

6

D-M:M+1-D
16

2

1 A-B

17

2

1 B-A
M-oo

3

TSTA

40

2

1 A-oo

TSTB

5D 2

1 B-oo

The condition code register notes are listed after Table 12,

3-223

bO

3

3

2

1

0

N

Z

V

C

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

t t
t
t
t

· tt

···
t
t ·
t
···
t t

R
R

·· t
·· tt
t
· tt
· tt tt tt
t t
t
·· tt tt
· tt tt
t
· ·tt ·tt ·tt tt
· ·t ·t ·t ·t
· tt tt ·
· ·· · ·· ·
· · · ·· ··
· tt tt tt tt
· tt tt tt tt
· tt tt tt tt
R
R
R

R
R
R

R

3

ROLB
ROR

3

I

R

Stack

ROLA

STAA

Test, Zero or Minus

3

32

PULA

Store Accumulators

Subtract Double

37

PSHB

SBCA 82

Transfer Accumulator

1 A-Stack

36

Subtract with Carry

Subtract

3

PSHA

PULB

bO

00- M-M

3

4

H

R

2

60

NEGA

Rotate Right

r,7

40

NEG

-0

bO

-IIIIIIIII-@]

1 AxB-D

MUL

Rotate Left

o

3D 10

Multiply
2's Complement INegateJ

Pull Data

@]-111111111
h7

5

· tt
·· tt
t

M+1-M

INCA

LSL

Push Data

M-1-M
4A

Logical Shift, Lelt

InclUSive OR

1 AdJ binary sum to BCD

DECB

LDD

No Operation

#

DECA

Load Double

Shilt Right, Logical

2

Boolean
Expression

bO

·
··
. ··
·
·
. ··
·

t t t
t t t
t t t
t t R
t t R
t t R
t t t
t t t
t t t
t t R
t t R
t t R
t t R
t t R

t
t

t

··
·t
t
t

··
R

R
R

I

MC6803E

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg"
Operations

I

Direct
Extend
Inherent
Relative
Index
# Op
# Op
MNEM Op
# Op
# Op
#

-

-

-

-

-

Branch Test

B ranch Always

BRA

20

3

2

Branch Never

BRN

21

3

2

None

Branch If Carry Clear

BCC

24

3

2

C=O

Branch If Carry Set

BCS

25

3

2

C=l

Branch If = Zero

BEQ

27

3

2

Z=l

Branch If ",Zero

BGE

2C

3

2

NEBV=O

Branch If >Zero

BGT

2E

3

2

Z+INEBVI=O

BHI

22

3

2

C+Z=O

Branch If Higher or Same

BHS

24

3

2

C=O

Branch If :5 Zero

BLE

2F

3

2

Z+INEBVI=l

Branch If Carry Set

BLO

25

3

2

C=l

Branch If Lower Or Same

BLS

23

3

2

C+Z=l

Branch If < Zero

BLT

20

3

2

NEBV=l

Branch If Minus

BMI

2B

3

2

N=l

Branch If Not Equal Zero

BNE

26

3

2

Z=O

Branch If Overflow Clear

BVC

28

3

2

v=o

Branch If Overflow Set

BVS

29

3

2

V=l
N=O

Branch If Plus

BPL

2A 3

2

Branch To Subroutine

BSR

80 6

2

Jump

JMP

6E

2 7E

3

3

3

2 BO 6

3

JSR

No Operation

NOP

01

2

1

Return From Interrupt

RTI

3B 10

1

Return From Subroutine

RTS

39

1

Software Interrupt

SWI

3F 12

1

Wait For Interrupt

WAI

3E

9

1

9D 5

2

AO 6

5

} Soo

3

2

I

N

Z V

1

0
C

··· ··· · · ·· ···
·· ·· ··· ··· · ··
·· ·· · · ·· ··
· ·· · ·· ·· ··
·· · · · ·
· · · · ··
·· ·· ·· · ·· ·
1
!
1
·· · ·· ·· ·
··· ·

} See Special
Operations Figure 21

Jump To Subroutine

4

··· ··· · ·· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· · ·· ··

None

Branch If Higher

5
H

Spec'"~

I I

Operations Figure 21

I

S

TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Condition Code Register
Operations

Inherent
MNEM Op

-

#

Boolean Operation

1

O-C

1

0-1

Clear Carry

CLC

OC

Clear Interrupt Mask

CLI

OE

2
2

Clear Overflow

CLV

OA

2

1

O-V

Set Carry

SEC

00

2

1

1-C

Set Interrupt Mask

SEI

OF

2

1

1-1

Set Overflow

SEV

OB

2

1

1-V

Accumulator A- CCR

TAP

06

2

1

A-CCR

CCR"- Accumulator A

TPA

07

2

1

CCR-A

LEGEND
Op Operation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
I Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OR
• Boolean Exclusive OR
M Complement of M
Transfer Into
o Bit=Zero
00 Byte=Zero

3-224

CONDITION CODE SYMBOLS
H Half-carry from bit 3
1 Interrupt mask
N Negative (Sign bit)
Z Zero (byte)
V Overflow, 2's complement
C Carry/Borrow from MSB
R Reset"Always
S Set Always
t Affected
• Not Affected

5

4

3

H

I

N

2
Z

1

0

V

C

··· ·· ··· ··· ·· ··
·· · ·· ·· ·· ·
·t ·t ·t ·t t ·t
······
R

R

R

S

S

S

MC6803E

TABLE 13 -

INSTRUCTION EXECUTION TIMES IN E CYCLES
ADDRESSING MODE

ADDRESSING MODE

!1\1

~

Q)

E

ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

!

"0
Q)

u
~

"0

c:

!)(

"0

C

"0

Q)
~

Q)
)(
Q)

~

.§

is

w

.E

.E

•
•2

•
•3

••

••

2
3

2

3
5
3

6

6

4

4

4

2

••
••
••
••
••2
•
••

2

•
4

••
••
2
•
•

••
••
••
•
•••
•
••
••

4
4

6

3

•6
•••
•
•••
••
••
••
•••
••
•
•••
6
•

5

6
6

3

•
•••
•3

••

4

4

•6
••
6
•
4

4
4

6

•
••
•
2
3
2

'"

Q)

...>

~
Q)

E
.§

1\1

'i

a:

••
••
••
••
•3

INX
JMP
JSR
LDA
LDD
LDS
LDX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

•
•• •••
••• ••
•• ••
• •
•
•••
••
•
••
••
•
•
••
•
• •
• •
6

3
3
3
3
3
3

4

3
3
3
3
3
3
3
3
3
6
3
3

6

2
2
2
2
2

4

6
6

6

•
•
4

6

•

2

2
2
3
3

••3

3-225

•
••
2
3
3
3

••
••
•••
2
••
••
••
•••
2

•

••
•
••
•2
••
•
•••
••
•
4

u
~

is

"0
GI
"0

"0
GI

!IC

GI
"0

c:

IC

W

.E

••5

•3

•3

6

6

3

4

4

4
4
4

5
5
5
6

5
5
5
6

••
••
••
•3
••
•

•••
•
•
••
3

•6
••
6
•
••
••6
6
••
•
•
••
4

•6
•
•6
•
••
••6
6
••
•
•
••

4
4
4

5
5
5

5
5
5

3
5

4

4

•
•
3

•
•••
•
••
••

4

4

6

••
••
•6
••
•

4

4

4

6

••
••
•6

•••

C

GI

GI

.~
.!!

.E

a:

~

~

3

••
••
•

GI

•
••

•
2
3
2
3

10

2
2

•
3

4
4

•

5
2
2
10

5
2

•
2
2
2

•
•••
••
12
2
2
2
2
2
3
3
9

•

II

•

s:o
m

00

FIGURE 24 -

o
w
m

SPECIAL OPERATIONS

SWI, Software Interrupt

JSR,.Jump to Subroutine
~

~

$9D = JSR

D"oc'

SP

Main Program

Main Program

$3F= SWI

I~-+
~

RTN

I

AcmltrB

SP-4

AcmltrA

SP-3

Index Register (XH)

SP-2

Index Register (XL)

I¢

SP-l

RTNH

SP

RTN

Iy

~

Stack

Next Main Instr
K = Direct Address

~

Main Program

~I
INDXD

{

¢

$AD= JSR
K= Offset

RTN

I

~

WAI, Wait for Interrupt

5'-2 E § E I
SP-l
RTNH
SP

Next Main Instr

Stack

RTNL
RTI Return from Interrupt

U)

N
N

0)

EXTND

I

Main Program

~

.

SP
Condition Code

SP+ 1

AcmltrB

SL = Subr. Addr

SP+3

AcmltrA

Next Main Inst

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+ 7

RTNL

~

± K = Offset
Next Main Instr

E

Subroutine
$39=RTS

Stack

¢~ SP-2~

$8D= BSR

RTN I

~

SP+2

Mam Program
~

~

"'0 '"

SH = Subr. Addr

BSR, Branch To Subroutine

RTS, Return from Subroutine

Interrupt Program

IT

$BD = JSR

RTN I

Condition Co'de

SP-6
SP-5

{
RTN

Stack

SP-7

I

SP-l

RTNH

SP

RTNL

~

¢

Stack

---..

JMP, Jump

INDXD

ES;

I

X+ K

§EI
SP+S
1 PE
RTNH

---..

SP+ 2

RTNL

Legend
RTN = Address of next Instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
- = Stack Pointer After Execution
K = 8-bit Unsigned Value

Main Program

PC

I

Next Instruction

'''m~d

$7E=JMP
K H = Next Address
KL = Next Address

{
K

I

Next Instruction

1\t1C6803E

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the address bus, data bus, and the read/write
(R/iN) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in

TABLE 14 -

Address Mode and
Instructions

groups according to addressing mode and number of cycles
per instruction. In general, instructions with the same
addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appear on the external data bus. High
order byte refers to the most significant byte of a 16-bit
value.

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 6)

R/W
Line

Address Bus

Data Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

2

LDS
LDX
LDD

3

CPX
SUBD
ADDD

4

1
2

Opcode Address
Opcode Address+ 1

1
1

Opcode
Operand Data

1
2

Opcode Address
Opcode Address+ 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Upcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcode Address
Opcode Address + 1
Destination Address

1
1

Opcode
Destination Address
Data from Accumulator

3
1
2

3
4

DIRECT
ADC
ADD
AND
BIT
CMP
STA

EOR
LDA
ORA
SBC
SUB

3

1

2
3

3

1

2
3
LDS
LDX
LDD

4

STS
STX
STD

4

1
2

3
4

1
2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

5
JSR

5

1
2

3
4

5

0

Opcode Address
Opcode Address+ 1
Address of Operand
Operand Address+ 1

1

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1
1

0
0

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Subroutine Address
Stack Pointer
Stack Pointer-l

1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

1

1
1

1
1

0
0

3-227

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

I

MC6803E

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 2 of 6)

R/W

Address Mode and
Instructions

Address Bus

Data Bus

Line

EXTENDED

3

JMP

1

2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

STA

4

1

2

3
4
4

1

2

3
4

I

5

LDS
LUX
LDD

1

2

3
4

5
STS
STX
STD

5

1

2

3
4

5
ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

LSR
NEG
ROL
ROR
TST*

6

1

2

3
4

5
6
6

1

2

3
4

5
6
JSR

6

1
2

3
4

5
6

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order By tel
Jump Address (Low Order By tel

Opcode
Opcode
Opcode
Address

Address
Address + 1
Address + 2
of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order By tel
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1

0

Opcode
Destination Address (High Order By tel
Destination Address (Low Order By tel
Data from Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Opcode
Address
Address
Operand
Operand

of Operand
of Operand
Data (High
Data (Low

(High Order By tel
(Low Order By tel
Order By tel
Order By tel

Opcode Address
Opcode Address+ 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Opcode
Address
Address
Operand
Operand

of Operand
of Operand
Data (High
Data (Low

(High Order By tel
(Low Order By tel
Order By tel
Order By tel

Opcode
Opcode
Opcode
Address
Address
Address

0
0

Address
Address+ 1
Address + 2
of Operand
Bus FFFF
of Operand

1
1
1
1
1

0

Opcode
Address of Operand (High Order By tel
Address of Operand (Low Order By tel
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address (High Order By tel
Operand Address (Low Order By tel
Operand Data (High Order By tel
Operand Data (Low Order By tel
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
S tack Pointer
Stack Pointer- 1

1
1
1
1

Opcode
Address of Subroutine (High Order By tel
Address of Subroutine (Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF

3-228

MC6803E

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 61
R/W
Line

Address Bus

Data Bus

INDEXED

3

JMP

1

2
3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

4

STA

1

2
3
4
1

2
3
4
LOS
LDX
LDD

5

STS
STX
STD

5

1

2
3
4

5

ASL
ASR
CLR
COM
DEC
INC

1

2
3
4
5
LSR
NEG
ROL
ROR
TST*

6

1

2
3
4

5
6

CPX
SUBD
ADDD

6

JSR

6

1

2
3
4
5
6
1

2
3
4

5
6

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Address Bus FFFF
I ndex Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF
I ndex Register Plus Offset
I ndex Register Plus Offset + 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order By tel
Operand Data (Low Order By tel

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register Plus Offset
I ndex Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order By tel
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
I ndex Register Plus Offset

0
0
1
1
1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Index Register + Offset
Index Register+ Offset + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
I ndex Register + Offset
Stack Pointer
Stack Pointer - 1

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (H igh Order Byte)

0
0

*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

3-229

I

MC6803E

TABLE 14 -

CYCLE-BY-CYCLE OPERATION (Sheet 4 of 6)

R/W

Address Mode and
Instructions

Line

Address Bus

Data Bus

INHERENT
2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

Opcode Address
Opcqde Address + 1
Stack Pointer

1
1

0

Opcode
Opcode of Next Instruction
Accumulator Data

Opcode Address
Opcode Address+ 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

Opcode Address
Opcode Address+ 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order By tel
Index Register (High Order By tel

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2

1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order By tel
Index Register (Low Order By tel

ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

3

I

1
2

3
1
2

3
1
2

3
PSHA
PSHB

3

1
2

3
TSX

3

TXS

3

PULA
PULB

4

1
2

3
1
2

3
1
2

3
4
PSHX

4

1
2

3
4
PULX

5

1
2

3
4

5

2-230

MC6803E

TABLE 14 Address Mode and
Instructions

CYClE-BY-CYClE OPERATION (Sheet 5 of 6)
R/W
Line

Address Bus

1

Data Bus

INHERENT
RTS

5

1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Poi nter + 2

1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order By tel
Address of Next Instruction (Low Order By tel

WAI

9

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer-6

1
1
0
0
0
0
0
0
0

Opcode
Opcode of Next Instruction
Return Address (Low Order By tel
Return Address (High Order By tel
Index Register (Low Order By tel
Index Register (High Order By tel
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2
Stack Poi nter + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer+ 6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order By tel
Index Register from Stack (Low Order By tel
Next Instruction Address from Stack (High Order By tel
Next Instruction Address from Stack (Low Order By tel

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1
Stack Pointer- 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Stack Pointer- 7
Vector Address FFFA (Hexl
Vector Address FFFB (Hexl

1
1
0
0
0
0
0
0
0
1
1
1

Opcode
Irrelevant Data
Return Address (Low Order By tel
Return Address (High Order By tel
Index Register (Low Order By tel
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order By tel
Address of Subroutine (Low Order By tel

Opcode Address
Opcode Address+'
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address+ 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer-l

1
1
1
1
0
0

Opcode
Branch Offset
low Byte of Restart Vector
Opcode of Next Instruction
Return Address (low Order Byte)
Return Address (High Order By tel

8
9
MUL

10

1
2
3
4
5
6
7

8
9
10
RTI

10

1
2
3
4
5
6
7

8
9
10
SWI

12

1
2
3
4
5
6
7

8
9
10
11
12

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR

BHT BNE BLO
BlE BPl BHS
BlS BRA BRN
BlT BVC
BMI BVS

3

1
2

3

6

1
2

3
4
5

6

3-231

I

MC6803E

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 6 of 6)

R/W
Line

Address Bus

Data Bus

RELATIVE

Bee
BeS
BEQ
BGE
BGT
BSR

BHT
BLE
BLS
BLT
BMI

BNE BLO
BPL BHS
BRA BRN
BVe
BVS

3

1

2

3

6

1

2

3
4
5
6

Opcode Address
Opcode Address+ 1
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
S tack Pointer - 1

1

Opcode
Branch Offset
Low Byte of Restart Vector
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

I

3-232

1

1
1

0
0

®

MC6809

MOTOROLA

a-BIT MICROPROCESSING UNIT
The MC6809 is a revolutionary high-performance 8-bit microprocessor
which supports modern programming techniques such as position independence, reentrancy, and modular programming.
This third-generation addition to the M6800 Family has major architectural
improvements which include additional registers, instructions, and addressing
modes.
The basic instructions of any computer are greatly enhanced by the
presence of powerful addressing modes. The MC6809 has the most complete
set of addressing modes available on any 8-bit microprocessor today.
The MC6809 has hardware and software features which make it an ideal
processor for higher level language execution or standard controller applications.

HMOS
(HIGH DENSITY N-CHANNEL, SILICON-GATE)

8-BIT
MICROPROCESSING
UNIT

MC6800 COMPATIBLE
• Hardware - Interfaces with All M6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set and
Addressing Modes

L SUFFIX
CERAMIC PACKAGE
CASE 715

P SUFFIX

ARCHITECTURAL FEATURES
• Two 16-Bit Index R€gisters
• Two 16-Bit Indexable Stack Pointers
• Two 8-Bit Accumulators can be Concatenated to Form One
16-Bit Accumulator
• Direct Page Register Allows Direct Addressing Throughout Memory
HARDWARE FEATURES
• On-Chip Oscillator (Crystal Frequency = 4 x E)
• DMA/BREQ Allows DMA Operation on Memory Refresh
• Fast Interrupt Request Input Stacks Only Condition Code Register
and Program Counter
• MRDY Input Extends Data Access Times for Use with Slow
Memory
• Interrupt Acknowledge Output Allows Vectoring by Devices
• Sync Acknowledge Output Allows for Synchronization to External
Event
• Single Bus-Cycle RESET
• ~Ie 5-Volt Supply Operation
• NMI Inhibited After RESET Until After First Load of Stack Pointer
• Early Address Valid Allows Use with Slower Memories
• Early Write Data for Dynamic Memories
SOFTWARE FEATURES
• 10 Addressing Modes
• 6800 Upward Compatible Addressing Modes
• Direct Addressing Anywhere in Memory Map
• Long Relative Branches
• Program Counter Relative
• True Indirect ,A.ddressing
• Expanded Indexed Addressing:
0-,5-,8-, or 16-Bit Constant Offsets
8- or 16-Bit Accumulator Offsets
Auto Increment/Decrement by 1 or 2
• Improved Stack Manipulation
• 1464 Instructions with Unique Addressing Modes
• 8 x 8 Unsigned Multiply
• 16-Bit Arithmetic
• Transfer/Exchange All Registers
• Push/ Pull Any Registers or Any Set of Registers
• Load Effective Address

3-233

PLASTIC PACKAGE
CASE 711

S SUFFIX
CERDIP PACKAGE
CASE 734

PIN ASSIGNMENT

VSS

HALT

NMI

39

XTAL

i'RQ

38

EXTAL

FiRQ

37

R'ESEi

BS

36

MROY

BA

35

0

Vee

34

AO

33

OMA/BREO

Al

32

R/W
00

A2

31

A3

30

01

A4

29

02

A5

28

03

A6

27

04

A7

26

05

A8

25

06

A9

24

07

Al0

23

A15

A11

22

A14

A12

21

A13

I

MC6809

MAXIMUM RATINGS
Unit

Symbol

Value

Supply Voltage

Vcc

-0.3to+7.0

V

Input Voltage

Yin

-0.3 to + 7.0

V

Operating Temperature Range
MC6809. MC68A09. MC68B09
MC6809C. MC68A09C. MC68B09C

TA

TL to TH
+ 70
-40 to +B5

°c

Tstg

-55 to + 150

°c

Rating

Storage Temperature Range

o to

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however. it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage levels (e.g .• either
VSS or VCC!.

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Ceramic
Cerdip
Plastic

II

Symbol

Value

8JA

50
60
100

Unit
°C/W

POWER CONSIDERATIONS

The average chip-junction temperature. T J. in °c can be obtained from:
(1)

TJ=TA+(PO·8JA)
Where:
TA"" Ambient Temperature. °c
8JA"" Package Thermal Resistance. Junction-to-Ambient. °C/W

PO"" PINT + PPORT
PINT"" ICC x VCC. Watts - Chip Internal Power
PPORT"" Port Power Oissipation. Watts - User Oetermined
For most applications PPORT
co

c..>

~L~tpCf
Wtpcs
~ ~tPcs
1M
f7T}'TT7"7'7'TCr7T7"T77"T"TT-l~------------------

SVIHR
tRC

c..>

~

LJ~

~tPcs

A~d~:SS;\\\\\\~~

VIHR
New PC+ 1

'L,:=<:=X

FFFE
Rlw
Data

',,+

!!a/'&'lKWIHR

i [.tPCr

New PC+ 1

~

See Note 3

New PC

\\\'(\\\\\';~

FFFF

~=-

New PC

FFFF New PC

C

New PC

r

VMA , - - , , - - - . r

Bus~~~~~~~~~_J~-~~-~'_-J~--''--~

BA

\\\\\\\\\:\~~

BS~~

Low Byte
/

\

Instruction

()
Sf

NOTES: 1. Parts with date codes prefixed by 7F or 5A will come out of RESET one cycle sooner than shown.
2. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
3. FFFE appears on the bus during RESET low time. Following the active transition of the RESET line, three more FFFE cycles will appear followed
by the vector fetch

La Byte

I

Instruction

\'-----

MC6809

FIGURE 7 -

CRYSTAL CONNECTIONS AND OSCILLATOR START UP

VCC

-----+--~
I

VIL

NOTE: Waveform measurements for all inputs and outputs are specified at logic high 2.0 V and logic low 0.8 V unless otherwise specified

I

MC6809

Y1
8 MHz

Cin
18 pF

6 MHz

20 pF

20 pF

4 MHz

24 pF

24 pF

---11

39

D
ln

C

38 _ _ _ _

Y1

38

Cnllt
18 pF

D

1::

I

Cout

Nominal Crystal Parameters

----39

1-1

~ctJ-~
CO

3.58 MHz

4.00 MHz

6.0 MHz

8.0 MHz

RS

6O{}

50 {}

30-50 {}

20-40 {}

CO
C1

3.5 pF

6.5 pF

4-6 pF

4-6 pF

0.015 pF

0.025 pF

0.01-0.02 pF

001-002 pF

Q

>40 k

>30 k

>20 k

>20 k

All parameters are 10%
NOTE: These are representative AT-cut crystal parameters only. Crystals of other
types of cut may also be used.

38

3-240

Other Signals
Not Wired In
This Area.

Me6809

FIGURE 8 - HALT AND SINGLE INSTRUCTION
EXECUTION FOR SYSTEM DEBUG
2nd To
Last
Cycle
Last
Cycle Of
Of
Current Current
1. .

Dead

Dead

Inst

Instruction Dead

I..~§~_ _ _ _~H.:.:a::.:lt:::::ed~_ _ _ _ _...+f.{.C:.c.y~C~le..~.,..-=e..::tc::.-h~-+1••Ex_e_c_ut_:+~f-C-.CY_C---,le-*I.~H~al~te:...:d_

lnsl. _1.lnst . •

o

HALT

~
Fetch
Execute

Address
Bus

S

R/W
~

/

BA ____________________- J

s

\

H

I

BS ____________________- J

\

I
!

~----~~-------------------------------~~-------­

Data
Bus

Instruction
Opcode
NOTE: Waveform measurements for all inputs and outputs are specified at logic high 2.0 V and logic low 0.8 V unless otherwise specified.

INTERRUPT ACKNOWLEDGE is indicated during both
cycles of a hardware-vector-fetch (RESET, NMI, FIRQ, IRQ,
SWI, SWI2, SWI3). This signal, plus decoding of the lower
four address lines, can provide the user with an indication of
which interrupt level is being serviced and allow vectoring by
device. See Table 1.

interrupt cannot be inhibited by the program, and also has a
higher priority than FIRQ, IRQ, or software interrupts. During recognition of an NMI, the entire machine state is saved
on the hardware stack. After reset, an NMI will not be recognized until the first program load of the hardware stack
pointer (S). The pulse width of NMIIow must be at least one
E cycle. If the NMI input does not meet the minimum set up
with respect to Q, the interrupt will not be recognized until
the next cycle. See Figure 9.

SYNC ACKNOWLEDGE is indicated while the MPU is
waiting for external synchronization on an interrupt line.
HALT/BUS GRANT is true when the MC6809 is in a halt
or bus grant condition.
TABLE 1 -

FAST-INTERRUPT REOUEST (FIRQ)"

MEMORY MAP FOR INTERRUPT VECTORS

Memory Map For
Vector Locations

A low level on this input pin will initiate a fast interrupt sequence, provided its mask bit (F) in the CC is clear. This sequence has priority over the standard interrupt request
(IRQ), and is fast in the sense that it stacks only the contents
of the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 10.

Interrupt Vector
Description

MS

LS

FFFE

FFFF

RESET

FFFC

FFFD

N'Mi

FFFA

FFFB

SWI

FFF8

FFF9

iRa

FFF6

FFF7

FIRO

INTERRUPT REQUEST (IRQ)"

FFF4

FFF5

SWI2

FFF2

FFF3

SWI3

FFFO

FFFl

Reserved

A low level input on this pin will initiate an interrupt request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state it provides a
slower response to interrupts than FIRQ. IRQ also has a
lower priority than FIRQ. Again, the interrupt service routine
should clear the source of the interrupt before doing an RTI.
See Figure 9.

NON MASKABLE INTERRUPT (NMI)"
A negative transition on this input requests that a nonmaskable interrupt sequence be generated. A non-maskable

*NMI, FIRO, and'iRO requests are sampled on the falling edge of O. One cycle is required for synchronization before these interrupts are recognized. The pending interrupt(s) will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRO
and FIRO do not remain low until completion of the current instruction they may not be recognized. However, NMI is latched and need only remain low for one cycle. No interrupts are recognized or latched between the falling edge of RESET and the rising edge of BS indicating
RESET acknowledge.

3-241

I

-

~

o

CD

Q)

o

CD

FIGURE 9 -

rna AND NMI INTERRUPT TIMING

Last cycle
of Current
Instruction

Instruction
Fetch

I. -I.
I m-2 I m- 1 1 m

Interrupt Stacking and Vector Fetch Sequence
Im+l

I m+21

.1... -I

m+31 m+41 m+51 m+61 m+71 m+81 m+9Im+l0Im+lllm+12Im+13Im+14Im+15Im+16Im+17Im+181

n

n+ 1

I

E*
Q

Address

-.~~~~~~r---,r---.r---~r--~,r---~r----\r---~'----'r--~,r---~r---.r---,r---..r---~ r----'r-

B~

(,.)

N

~
I\)

TRQ or
NMI
Data~L---.JL---.JL---.J~~~~~~~~\___..J\.____1\

R/W~

\

~------------------------------------~

E*

NOTE: Waveform measurements for all inputs and outputs are specified at logic high=2.0 V and logic low=O.8 V unless otherwise specified.

* E clock shown for reference only.

3:

o
0)
00

o
FIGURE 10 -

Last Cycle
of Current
Instruction

I.
1

m-2

I

Instruction
Fetch

Interrupt Stacking and Vector Fetch Sequence

.1.

m-l

CO

FIRQ INTERRUPT TIMING

m

I

m+l

I

m+2

I

m+3

I

m+4

I

m+5

I

m+6

.1.
I

m+7

I

m+8

I

m+9

.1

n+ 1

n+

E*

o
Address
Bus

--=i r-

tpcs

PC

PC

FIRO

w
N

~

w

Data

R/W=

\

; , - - - - - - - - - -

B A = ' - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

BS=

/

\'--_ _ __

E*
NOTE: ~aveform measurements for all inputs and outputs are specified at logic high = 2.0 V and logic low = 0.8 V unless otherwise specified.
E clock shown for reference only.

MC6809

XTAl, EXTAl

registers onto the stack and then awaits an interrupt.
During this waiting period, it is possible to place the
MPU into a halt mode to three-state the machine, but
MRDY will not stretch the clocks.
The mask set for a particular part may be determined by
examining the markings on top of the part. Below the part
number is a string of characters. The first two characters are
the last two characters of the mask set code. If there are only
four digits the part is the G7F mask set. The last four digits,
the date code, show when the part was manufactured.
These four digits represent year and week. For example a
ceramic part marked:

These inputs are used to connect the on-chip oscillator to
an external parallel-resonant crystal. Alternately, the pin
EXT Al may be used as a TTL level input for external timing
by grounding XT Al. The crystal or external frequency is four
times the bus frequency. See Figure 7. Proper RF layout
techniques should be observed in the layout of printed circuit
boards.
E,O
E is similar to the MC6800 bus timing signal phase 2; 0 is a
quadrature clock signal which leads E. 0 has no parrallel on
the MC6800. Addresses from the MPU will be valid with the
leading edge ·of O. Data is latched on the falling edge of E.
Timing for E and 0 is shown in Figure 11.

II

MRDY*
This input control signal allows stretching of E and 0 to
extend data-access time. E and 0 operate normally while
MRDY is high. When MRDY is low, E and 0 may be stretched in integral multiples of quarter (y.,) bus cycles, thus allowing interface to slow memories, as shown in Figure 12(a).
During non-valid memory access (VMA cycles), MRDY has
no effect on stretching E and 0; this inhibits slowing the processor during "don't care" bus accesses. MRDY may also be
used to stretch clocks (for slow memory) when bus control
has been transferred to an external device (through the use
of HALT and DMA/BREO).
NOTE
Four of the early production mask sets (G7F, T5A,
P6F, T6M) require synchronization of the MRDY input
with the 4f clock. The synchronization necessitates an
external oscillator as shown in Figure 12(b). The
negative transition of the MRDY signal, normally
derived from the chip select decoding, must meet the
tpcs timing. With these four mask sets, MRDY's
po~itive transition must occur with the riSing edge of
4f.
In addition, on these same mask sets, MRDY will
not stretch the E and 0 signals if the machine is executing either a TFR or EXG instruction during the
Fl"A[j high-to-Iow transition. If the MPU executes a
CWAI instruction, the machine pushes the internal

is a T5A mask set made the twelfth week of 1980.
DMA/BREO*
The DMA/BREO input provides a method of suspending
execution and acquiring the MPU bus for another use, as
shown in Figure 13. Typical uses include DMA and dynamic
memory refresh.
A low level on this pin will stop instruction execution at the
end of the current cycle unless pre-empted by self-refresh.
The MPU will acknowledge DMA/BREO by setting BA and
BS to a one. The requesting device will now have up to 15
bus cycles before the MPU retrieves the bus for self-refresh.
Self-refresh requires one bus cycle with a leading and trailing
dead cycle. See Figure 14. The self-refresh counter is only
cleared if DMA/BREO is inactive for two or more MPU
cycles.
Typically, the DMA controller will request to use the bus
by asserting DMA/BREO pin low on the leading edge of E.
When the MPU replies by setting BA and BS to a one, that
cycle will be a dead cycle used to transfer bus mastership to
the DMA controller.
False memory accesses may be prevented during any dead
cycles by developing a system DMAVMA Signal which is
LOW in any cycle when BA has changed.

FIGURE 11 - E/Q RELATIONSHIP
End of Cycle (Latch Datal

Start of Cycle
I

I

E~~0~.5~V~
I
Q

______

:'AVHy
I

~;'

I

'{,'---I

\'-_----1.-1__
I

Address Valid

NOTE: Waveform measurements for all inputs and outputs are specified at logic high 2.0 V and logic low 0.8 V unless otherwise specified.

* The on-board clock generator furnishes E and 0

to both the system and the MPU. When MRDY is pulled low, both the system clocks and the
internal MPU clocks are stretched. Assertion of DMA/'BREQ input stops the internal MPU clocks while allowing the external system clocks to
RUN O.e., release the bus to a DMA controller). The internal MPU clocks resume operation after DMA/BREO is released or after 16 bus cycles
(14 DMA, two dead), whichever occurs first. While DMA/BRE
AUTO-REFRESH DMA TIMING (> 14 CYCLES)
(REVERSE CYCLE STEALING)

IDead ""1.1f---------14 DMA Cycles ----------;.~IDeadIMPuloeadI.--DMA-----.
I

I

I

I

I

I

1

I

I

I

1

I

1

I
I

o
1

I

DMA/BREO'I
SA, BS

I
1

I

1

1

I

I

I

1

1

1

,!o------

I

1 _~----------¥Ir-~------------------------------------~I
I
W--r
I
I

I

I

I

DMAVMA*~

~

* DMAVMA is a signal which is developed externally, but is a system requirement for DMA. Refer to Application Note AN-820

NOTE: Waveform measurements for all inputs and outputs are specified at logic high 2.0 V and logic low 0.8 V unless otherwise specified.

3·246

FIGURE 15 -

:s:

FLOWCHART FOR MC6809 INSTRUCTIONS

o

CD

FiRQ.F

0)

o

CO

(..)

r\)
~

.......

Bus State

BA

BS I

0

Running

0

Interrupt or Reset Acknowledge

0

1

Sync Acknowledge

1

0

1

1

~alt

or Bus Grant Acknowledge

CWAI

Note: Asserting RESET will result in entering the reset sequence from any point in the flowchart.

Me6S09

ADDRESSING MODES

I

EXTENDED INDIRECT - As in the special case of indexed
addressing (discussed below), one level of indirection may
be added to extended addressing. In extended indirect, the
two bytes following the postbyte of an indexed instruction
contain the address of the data.
LDA
[CAT]
LDX
[$FFFE]
STU
[DOG]

The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The
MC6809 has the most complete set of addressing modes
available on any microcomputer today. For example, the
MC6809 has 59 basic instructions; however, it recognizes
1464 different variations of instructions and addressing
modes. The addressing modes support modern programming techniques. The following addressing modes are available on the MC6809:
Inherent (includes accumulator)
Immediate
Extended
Extended Indirect
Direct
Register
Indexed
Zero-Offset
Constant Offset
Accumulator Offset
Auto Increment/ Decrement
Indexed Indirect
Relative
Short/ Long Relative Branching
Program Counter Relative Addressing

DIRECT ADDRESSING

Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower eight bits of the address to be used. The
upper eight bits of the address are supplied by the direct
page register. Since only one byte of address is required in
direct addressing, this mode requires less memory and
executes faster than extended addressing. Of course, only
256 locations (one page) can be accessed without redefining
the contents of the DP register. Since the DP register is set
to $00 on reset direct addressing on the MC6809 is compatible with direct addressing on the M6800. Indirection is not
allowed in direct addressing. Some examples of direct
addressing are:
LDA
$30
SETDP $10 (assembler directive)
LDB
$1030
LDD
< CAT

INHERENT (INCLUDES ACCUMULATOR)

In this addressing mode, the opcode of the instruction
contains all the address information necessary. Examples of
inherent addressing are: ABX, DAA, SWI, ASRA, and
CLRB.

NOTE
is an assembler directive which forces direct
addressing.

<

IMMEDIATE ADDRESSING

In immediate addressing, the effective address of the data
is the location immediately following the opcode (i.e., the
data to be used in the instruction immediately following the
opcode of the instruction). The M C6809 uses both 8- and
16-bit immediate values depending on the size of argument
specified by the opcode. Examples of instructions with immediate addressing are:
LDA #$20
LDX #$FOOO
LDY #CAT
NOTE
# signifies Immediate addressing; $ signifies hexadecimal value.

REGISTER ADDRESSING

Some opcodes are followed by a byte that defines a
register or set of registers to be used by the instruction. This
is called a postbyte. Some examples of register addressing
are:
x, Y
TFR
Transfers X into Y
A, B
Exchanges A with B
EXG
PSHS
A, B, X, Y Push Y, X, B and A onto S
X, Y, D
PULU
Pull D, X, and Y from U
INDEXED ADDRESSING

In all indexed addressing, one of the pointer registers (X,
Y, U, S, and sometimes PC) is used in a calculation of the effective address of the operand to be used by the instruction.
Five basic types of indexing are available and are discussed
below. The postbyte of an indexed instruction specifies the
basic type and variation of the addressing mode as well as
the pointer register to be used. Figure 16 lists the legal formats for the postbyte. Table 2 gives the assembler form and
the number of cycles and bytes added to the basic values for
indexed addressing for each variation.

EXTENDED ADDRESSING

In extended addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address
generated by an extended instruction defines an absolute
address and is not position independent. Examples of extended addressing include:
lOA
CAT
STX
MOUSE
LDD
$2000

3-248

MC6809

ZERO-OFFSET INDEXED - In this mode, the selected
pointer register contains the effective address of the data to
be used by the instruction. This is the fastest indexing mode.
Examples are:

FIGURE 16 - INDEXED ADDRESSING POSTBYTE
REGISTER 'BIT ASSIGNMENTS
Postbyte Register Bit

7

6

5

4

3

2

1

0

0
1
1
1
1
1
1
1
1

R
R
R
R
R
R
R
R
R
R
R
x
x
R

R
R
R
R
R
R
R
R
R
R
R
x
x
R

d
0
i
0

d
0
0
0
0
0
0
0
1
1
1
1
1
1

d

d
0
0
1
1
0
0
1
0
0
1
0
0
1

d
0
1
0
1
0
1
0
0
1
1
0
1
1

1
1
1
1
1

I

i
I
I
I
I
I

i
i
i

- ---

0
0
0
0
1
1
1
0
0
0
1
1
1

Indexed
Addressing
Mode
EA = ,R + 5 Bit Offset
,R+
,R+ +
,-R

LOO
LOA

,- - R

EA = ,R +0 Offset
EA = ,R + ACCB Offset
EA = ,R + ACCA Offset
EA = ,R +8 Bit Offset
EA = ,R + 16 Bit Offset
EA = ,R + D Offset
EA = ,PC +8 Bit Offset
EA = ,PC + 16 Bit Offset
EA = [,Address]

'-----Addressing Mode Field

'---------Indirect Field
(Sign bit when b7 = 0)

S

CONSTANT OFFSET INDEXED - In this mode, a twoscomplement offset and the contents of one of the pointer
registers are added to form the effective address of the
operand. The pointer register's initial content is unchanged
by the addition.
Three sizes of offsets are available:
5 bit (- 16 to + 15)
8 bit (-128 to + 127)
16 bit ( - 32768 to + 32767)
The twos complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and
cycles. The twos complement 8-bit offset is contained in a
single byte following the postbyte. The twos complement
16-bit offset is in the two bytes following the postbyte. In
most cases the programmer need not be concerned with the
size of this offset since the assembler will select the optimal
size automatically.
Examples of constant-offset indexing are:

LOA
LOX
LOY
LOU

' - - - - - - - - - - - - - R e g i s t e r Field: RR
00 = X
x = Don't Care
01 = Y
d = Offset Bit
10 = U
11 = S
i = ~: ~~~r~c~irect:

a,x

23,X
-2,S
300,X

CAT,Y

TABLE 2 - INDEXED ADDRESSING MODE
Type

Forms

Constant Offset From R
(2s Complement Offsets)

No Offset
5-Bit Offset
8-Bit Offset
16-Bit Offset

Accumulator Offset From R
(2s Complement Offsets)
Auto Increment/Decrement R

Constant Offset From PC
(2s Complement Offsets)
Extended Indirect
R=X, y, U, or S
x = Don't Care

A Register Offset
B Register Offset
D Register Offset
Increment By 1
Increment By 2
Decrement By 1
Decrement By 2
8-Bit Offset
16-Bit Offset
16-Bit Address

Non Indirect
Postbyte
Assembler
Opcode
Form
,R
1RROO100
n, R
ORRnnnnn
n, R
1RR01000
n, R
1RR01001
A, R
1RROO110
B, R
1RR00101
D, R
1RR01011
,R+
1RROOOOO
1RROOOO1
,R+ +
,-R
1RROOO10
,- -R
1RROOO11
n, PCR
1xx01100
n, PCR
1xx01101
-

RR:
OO=X
01=Y
10=U
11 =s

-:'and +# indicate the number of additional cycles and bytes for the particular variation.

3-249

+ +
#
0 0
1 0
1 1

-

4 2
1 0
1 0
4 0
2 0
3 0
2 0
3 0
1 1
5 2
- -

Indirect
Assembler
Postbyte
Form
Opcode
[,Rl
1RR101oo
defaults to 8-bit
[n, Rl
1RR11000
[n, Rl
1RR11oo1
[A, Rl
1RR10110
[B, Rl
1RR10101
[0, Rl
1RR11011
not allowed
1RR10001
[,R+ +l
not allowed
[,- -R]
1RR1oo11
[n, PCRl
1xx111oo
[n, PCRl
1xx11101
[nl
10011111

+ +
#
3 0

4

1
2
4 0
4 0
7 0

7

6 0

6 0
4 1
8 2
5 2

I

MC6809

ACCUMULATOR-OFFSET INDEXED - This mode is
similar to constant offset indexed except that the twoscomplement value in one of the accumulators (A, B, or D)
and the contents of one of the pointer registers are added to
form the effective address of the operand. The contents of
both the accumulator and the pointer register are unchanged
by the addition. The postbyte specifies which accumulator
to use as an offset and no additional bytes are required. The
advantage of an accumulator offset is that the value of the
offset can be calculated by a program at run-time.
Some examples are:
LDA
B,Y
LDX
D,Y
LEAX
B,X

I

Before Execution
A= XX (don't care)
X= $FOoo
LDA [$1O,Xl
EA is now $F01O

$0100
$F010
$F011

$F1
$50

$F150

$F150 is now the
new EA

$AA
After Execution
A = $AA Actual Data Loaded
X= $ FOOO

All modes of indexed indirect are included except those
which are meaningless (e.g., auto increment/decrement by
one indirect!. Some examples of indexed indirect are:
LDA
[,X]
LDD
[10,8]
LDA
[B,Y]
LDD
[,X+ +]

AUTO INCREMENT/DECREMENT INDEXED - In the
auto increment addressing mode, the pointer register contains the address of the operand. Then, after the pointer
register is used it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data,
or for the creation of software stacks. In auto decrement, the
pointer register is decremented prior to use as the address of
the data. The use of auto decrement is similar to that of auto
increment; but the tables, etc., are scanned from the high to
low addresses. The size of the increment/ decrement can be
either one or two to allow for tables of either 8- or 16-bit data
to be accessed and is selectable by the programmer. The
pre-decrement, post-increment nature of these modes
allows them to be used to create additional software stacks
that behave identically to the U and S stacks.
Some examples of the auto increment/ decrement addressing modes are:
LDA
,X+
STD
,Y+ +
,- Y
LDB
LDX
,- - S

RELATIVE ADDRESSING
The byte(s) following the branch opcode is (are) treated as
a Signed offset which may be added to the program counter.
If the branch condition is true, then the calculated address
(PC + signed offset) is loaded into the program counter.
Program execution continues at the new location as indicated by the PC; short (one byte offset) and long (two
bytes offset) relative addressing modes are available. All of
memory can be reached in long relative addressing as an effective address is interpreted modulo 216. Some examples of
relative addressing are:

Care should be taken in performing operations on 16-bit
pointer registers (X, Y, U, S) where the same register is used
to calculate the effective address.
Consider the following instruction:
STX O,X + + (X initialized to Q)
The desired result is to store zero in locations $0000 and
$0001 then increment X to point to $0002. In reality, the
following occurs:
O-temp
calculate the EA; temp is a holding register
perform auto increment
X + 2-X
X-(temp)
do store operation

CAT
DOG

BEQ
BGT
LBEQ
LBGT

RAT
RABBIT

NOP
NOP

CAT
DOG
RAT
RABBIT

(short)
(short)
(long)
(long)

PROGRAM COUNTER RELATIVE - The PC can be used
as the pointer register with 8- or 16-bit Signed offsets. As in
relative addressing, the offset is added to the current PC to
create the effective address. The effective address is then
used as the address of the operand or data. Program counter
relative addressing is used for· writing position independent
programs. Tables related to a particular routine will maintain
the same relationship after the routine is moved, if
referenced relative to the program counter. Examples are:
LDA
CAT, PCR
LEAX
TABLE, PCR
Since program counter relative is a type of indexing, an
additional level of indirection is available.
LDA
[CAT, PCR]
LDU
[DOG, PCR]

INDEXED INDIRECT - All of the indexing modes, with
the exception of auto increment/decrement by one or a
± 4-bit offset, may have an additional level of indirection
specified. In indirect addressing, the effective address is contained at the location specified by the contents of the index
register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address
calculated from the index register and an offset.

3-250

MC6809

INSTRUCTION SET
The instruction set of the MC6809E is similar to that of the
MC6800 and is upward compatible at the source code level.
The number of opcodes has been reduced from 72 to 59, but
because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464.
Some of the new instructions are described in detail
below.

Transfer / Exchange Post byte
:Sou:rce :

0000= D (A:B)
1000= A
0001 = X
1001 = B
1010= CCR
0010= Y
0011 = U
1011=DPR
0100= S
0101 = PC
NOTE
All other combinations are undefined and INVALID.

PSHU/PSHS

The push instructions have the capability of pushing onto
either the hardware stack (S) or user stack (U) any single
register or set of registers with a single instruction.

LEAX/ LEA Y / LEAU / LEAS
The LEA (load effective address) works by calculating the
effective address used in an indexed instruction and stores
that address value, rather than the data at that address, in a
pointer register. This makes all the features of the internal
addressing hardware available to the programmer. Some of
the implications of this instruction are illustrated in Table 3.
The LEA instruction also allows the user to access data
and tables in a position independent manner. For example:

PULU/PULS

The pull instructions have the same capability of the push
instruction, in reverse order. The byte immediately following
the push or pull opcode determines which register or
registers are to be pushed or pulled. The actual push/ pull sequence is fixed; each bit defines a unique register to push or
pull, as shown below.

Push/ Pull Postbyte

Stacking Order
Pull Order

I I I I I I I I I

Il

MSG1

CC
A
B

DP
X Hi
X Lo
Y Hi
Y Lo
U/S Hi
U/S Lo
PC Hi
PC Lo

t

MSG1, PCR
PDATA (print message routine)

FCC

'MESSAGE'

LEAa ,b+

Push Order
Increasing
Memory

+
TFR/EXG

Within the MC6809E, any register may be transferred to or
exchanged with another of like size, i.e., 8 bit to 8 bit or 16
bit to 16 bit. Bits 4-7 of postbye define the source register,
while bits 0-3 represent the destination register. These are
denoted as follows:

Instruction
LEAX 10, X
LEAX 500, X
LEAY
A,Y
LEAY
D,Y
LEAU -10, U
LEAS -10, S
LEAS 10, S
LEAX
5, S

LEAX
LBS R

This sample program prints: 'MESSAGE'. By writing
MSG1, PCR, the assembler computes the distance between
the present address and M SG 1. This result is placed as a
constant into the LEAX instruction which will be indexed
from the PC value at the time of execution. No matter where
the code is located when it is executed, the computed offset
from the PC will put the absolute address of MSG1 into the X
pointer register. This code is totally position independent.
The LEA instructions are very powerful and use an internal
holding register (temp). Care must be exercised when using
the LEA instructions with the auto increment and auto
decrement addressing modes due to the sequence of internal
operations. The LEA internal sequence is outlined as follows:

+

CCR
A
B
DPR
X
Y
S/U
PC

I D~sti~atio:n

Register Field

(any of the 16-bit pointer registers X, Y,
U, or S may be substituted for a and b)

1. b-temp

(calculate the EA)

2. b+1-b

(modify b, postincrement)

3. temp- a

(load a)

LEAa ,- b
1. b-1-temp

(calculate EA with predecrement)

2. b-1-b

(modify b, predecrement)
(load a)

3. temp- a

TABLE 3 - LEA EXAMPLES
Operation
Comment
Adds 5-Bit Constant 10 to X
X + 10 - X
X+500-X
Adds 16-Bit Constant 500 to X
Adds 8-Bit A Accumulator to Y
Y+A - Y
Y+D - y
Adds 16-Bit D Accumulator to Y
U - 10 -U
Substracts 10 from U
S - 10 - S
Used to Reserve Area on Stack
S + 10 - S
Used to 'Clean Up' Stack
S + 5 -X
Transfers As Well As Adds

3-251

I

MC6809

Auto increment-by-two and auto decrement-by-two instructions work similarly. Note that LEAX ,X + does not change
X; however, LEAX, - X does decrement; LEAX 1, X should
be used to increment X by one.
MUL
Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D
accumulator. The unsigned multiply also allows multipleprecision multiplications.

Example 1: LBSR (Branch Taken)
Before Execution SP = FOOO

$8000

LBSR

MOOO

CAT

CAT

LONG AND SHORT RELATIVE BRANCHES

I

The MC6809 has the capability of program counter relative
branching throughout the entire memory map. In this mode,
if the branch is to be taken, the 8- or 16-bit signed offset is
added to the value of the program counter to be used as the
effective address. This allows the program to branch
anywhere in the 64K memory map. Position-independent
code can be easily generated through the use of relative
branching. Both short (8-bit) and long (16-bit) branches are
available.
SYNC
After encountering a sync instruction, the MPU enters a
sync state, stops processing instructions, and waits for an
interrupt. If the pending interrupt is non-maskable (NMI) or
maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the processor will clear the sync state and perform the normal interrupt stacking and service routine. Since FIRQ and IRQ are
not edge-triggered, a low level with a minimum duration of
three bus cycles is required to assure that the interrupt will
be taken. If the pending interrupt is maskable (FIRQ, IRQ)
with its mask bit (F or I) set, the processor will clear the sync
state and continue processing by executing the next in-line
instruction. Figure 18 depicts sync timing.
SOFTVVAREINTERRUPTS
A software interrupt is an instruction which will cause an
interrupt and its associated vector fetch. These software interrupts are useful in operating system calls, software
debugging, trace operations, memory mapping, and software development systems. Three levels of SWI are available
on the MC6809, and are prioritized in the following order:
SWI, SWI2, SWI3.
l6-BIT OPERATION
The MC6809 has the capability of processing 16-bit data.
These instructions include loads, stores, compares, adds,
subtracts, transfers, exchanges, pushes, and pulls.

CYCLE-BY-CYCLE OPERATION
The address bus cycle-by-cycle performance chart (Figure
18) illustrates the memory-access sequence corresponding
to each possible instruction and addressing mode in the
MC6809. Each instruction begins with an opcode fetch.
While that opcode is being internally decoded, the next program byte is always fetched. (Most instructions will use the
next byte, so this technique considerably speeds throughput.) Next, the operation of each opcode will follow the
flowchart. VMA is an indication of FFFF16 on the address
bus, R/W = 1 and BS = O. The following examples illustrate
the use of the chart.

3-252

CYCLE-BY-CYCLE FLOW
Cycle #

Address

Data

1
2

17
20

7
8

8000
8001
8002
FFFF
FFFF
AOOO
FFFF
EFFF

9

EFFE

3
4

5
6

R/W Description

*
*
*
*
80

1
1
1
1
1
1
1
0

03

0

00

Opcode Fetch
Offset High Byte
Offset Low Byte
VMA Cycle
VMA Cycle
Computed Branch Address
VMA Cycle
Stack High Order Byte of
Return Address
Stack Low Order Byte of
Return Address

Example 2: DEC (Extended)
$8000

DEC

$AOOO

$A8000 $80
CYCLE-BY-CYCLE FLOW
Cycle #

Address

Data

1
2
3
4

8000
8001
8002
FFFF
AOOO
FFFF
AOOO

7A
AD
00
*

5
6
7

80
*
7F

R/W Description
1
1
1
1
1
1
0

Opcode Fetch
Operand Address, High Byte
Operand Address, Low Byte
VMA Cycle
Read the Data
VMA Cycle
Store the Decremented Data

*The data bus has the data at that particular address.

INSTRUCTION SET TABLES
The instructions of the MC6809 have been broken down
into five different categories. They are as follows:
8-bit operation (Table 4)
16-bit operation (Table 5)
Index register/stack pointer instructions (Table 6)
Relative branches (long or short) (Table 7)
Miscellaneous instructions (Table 8)
Hexadecimal values for the instructions are given in
Table 9.

PROGRAMMING AID
Figure 19 contains a compilation of data that will assist in
programming the MC6809.

3:

o

0)

CO

o

CO

FIGURE 17 -

SYNC TIMING
Last Cycle

Sync

Q

Address
See Note 1

c.u

r\:>
(11

c.u

Data

R/W

BA
BS
IRQ{
FIRQ
NMI

See Note 2

tpcs

NOTES:
1. If the associated mask bit is set when the interrupt is requested, this cycle will be an instruction fetch from address location PC + 1. However, if the interrupt is accepted (NMI or an unmasked FIRQ or IRQ) interrupt processing continues with this cycle as m on Figures 9 and 10 (Interrupt Timing)
2. If mask bits are clear, IRQ and FIRQ must be held low for three cycles to guarantee interrupt to be taken, although only one cycle is necessary to bring
the processor out of SYNC.
3. Waveform measurements for all inputs and outputs are specified at logic high 2.0 V and logic low 0.8 V unless otherwise specified.

III

MC6809

FIGURE 18 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 1 of 5)

I
NOTES
1. Each state shows
Data Bus

.---------,

Address Bus L -_ _ _---l

2 Address NNNN is location of opcode
3

If opcode is a two byte opcode subsequent
addresses are in parenthesis (-)

4 Two-byte opcodes are hIghlighted

No

Yes

No

3-254

Me6809

FIGURE 18 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 2 of 5)

I

3-255

MC6809

FIGURE 18 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 3 of 5)

I

3-256

MC6809

FIGURE 18 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 4 of 5)

I
+ Offset Byte
+ Offset High Byte Offset Low Byte
Accumulator
A Register
B Register
D Register

Offset from A
Offset
Offset
Offset

+ A Register
+ B Register
+ 0 Register

Auto Increment/Decrement R
Incrementby2
Decrement by 2
Constant Offset from PC
8-Bit Offset
16-blt Offset

Program Counter + Offset Byte
Program Counter + Offset High Byte" Offset Low Byte

ExtendedlndlreCl

16-811 Address

Address High Byte Addres Low Byte

*Themdex reglsler IS Incremented followmg the mdexed access

3-257

MC6809

FIGURE 18 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 5 of 5)

Effective Address

ANDCC.

JMP

ORCe
(Immediate

(All Except
Immediate)

LEAS

Only)

I

Effective Address (EAI
Constant Offset from R
No Offset
5-Bit Offset
8-Blt Offset

+ Post Byte
+ Post Byte High Post Byte Low

16·811 Offset
Accumulator
A Register
B Register
o Register

Offset from A
Offset
Offset
Offset

Index Register + A
Index Register + B
Index Register + 0

Auto Increment/Decrement R
Incrementbyl
Incrementby2
Decrement by 1
Decrement by2
Constant Offset from PC
8-Blt Offset

Program Counter + Offset Byte
Program Counter + Offset High Byte Offset Lo~ B"te

16-811 Offset

Direct Page Register Address Low
Address High" Address Low
NNNN+ 1
The Index register IS Incremented following the mdexed access

3-258

MC6809

TABLE 4 - 8-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS
Mnemonic(s)

Operation

ADCA, ADCB

Add memory to accumulator with carry

ADDA,ADDB

Add memory to accumulator

ANDA,ANDB

And memory with accumulator

ASL, ASLA, ASLB

Arithmetic shift of accumulator or memory left
Arithmetic shift of accumulator or memory right

ASR, ASRA, ASRB
BITA, BITB

Bit test memory with accumulator

CLR, CLRA, CLRB

Clear accumulator or memory location

CMPA, CMPB

Compare memory from accumulator

COM, COMA, COMB

Complement accumulator or memory location

DAA

Decimal adjust A accumulator

DEC, DECA, DECB

Decrement accumulator or memory location

EORA, EORB

Exclusive or memory with accumulator

EXG Rl, R2

Exchange Rl with R2 (Rl, R2 = A, B, CC, DP)

INC, INCA, INCB

Increment accumulator or memory location

LOA, LOB

Load accumulator from memory

LSL, LSLA, LSLB

Logical shift left accumulator or memory location

LSR, LSRA, LSRB

Logical shift right accumulator or memory location

MUL

Unsigned multiply (A x B -

D)

NEG, NEGA, NEGB

Negate accumulator or memory

ORA,ORB

Or memory with accumulator

ROL, ROLA, ROLB

Rotate accumulator or memory left

ROR, RORA, RORB

Rotate accumulator or memory right

SBCA, SBCB

Subtract memory from accumulator with borrow

STA, STB

Store accumulator to memory

SUBA, SUBB

Subtract memory from accumulator

TST, TSTA, TSTB

Test accumulator or memory location

TFR Rl, R2

Transfer Rl to R2 (Rl, R2 = A, B, CC, DP)

NOTE: A, B, CC, or DP may be pushed to (pulled from) stack with either PSHS, PSHU
(PULS, PULU) instructions.

TABLE 5 Mnemonic(s)

16-81T ACCUMULATOR AND MEMORY INSTRUCTIONS
Operation

ADDD

Add memory to 0 accumulator

CMPD
EXG 0, R

Compare memory from 0 accumulator
Exchange 0 with X, y, S, U, or PC

LDD

Load 0 accumulator from memory

SEX

Sign Extend B accumulator into A accumulator

STD

Store 0 accumulator to memory

SUBD

Subtract memory from 0 accumulator

TFR 0, R

Transfer 0 to X, Y, S, U, or PC

TFR R, 0

Transfer X, Y, S, U, or PC to 0

NOTE: 0 may be pushed (pulled) to stack with either PSHS, PSHU (PULS,
PULU) instructions.

3-259

I

MC6809

TABLE 6 - INDEX REGISTER/STACK POINTER INSTRUCTIONS
Instruction
. CMPS, CMPU
CMPX, CMPY

Compare memory from index register

EXG Rl, R2

Exchange D, X, Y, X, U, or PC with D, X Y, S, U, or PC

LEAS, LEAU
LEAX, LEAY

Load effective address into stack pointer

LDS, LDU
LDX, LDY

Load
Load
Push
Push

PSHS
PSHU
PULS
PULU
S,S, STU
S,X, STY
TFR Rl, R2

Load effective address into index register
stack
index
A, B,
A, B,

pointer from memory
register from memory
CC, DP, D, X, Y, U, or PC onto hardware stack
CC, DP, D, X, Y, S, or PC onto user stack

Pull A, B, CC, DP, D, X, Y, U, or PC from hardware stack
Pull A, B, CC, DP, D, X, Y, S, or PC from hardware stack
Store stack pointer to memory
Store index register to memory
Transfer D, X, Y, S, U or PC to D, X, Y, S, U, or PC
Add B accumulator to X (unsigned)

ABX

I

Description
Compare memory from stack pointer

TABLE 7 -

BRANCH INSTRUCTIONS
Description

Instruction

SIMPLE BRANCHES
BEQ, LBEQ

Branch if equal

BNE, LBNE
BMI, LBMI

Branch if not equal
Branch if minus

BPL, LBPL
BCS, LBCS

Branch if plus
Branch if carry set

BCC, LBCC

Branch if carry clear
Branch if overflow set

BVS, LBVS
BVC, LBVC
BGT,
BVS,
BGE,
BEQ,
BNE,

LBGT
LBVS
LBGE
LBEQ
LBNE

BLE, LBLE
BVC, LBVC
BLT, LBLT
BHI. LBHI
BCC, LBCC
BHS, LBHS
BEQ, LBEQ
BNE, LBNE
BLS, LBLS
BCS, LBCS
BLO, LBLO
.BSR, LBSR
BRA, LBRA
BRN, LBRN

Branch if overflow clear
SIGNED BRANCHES
Branch if greater (signed)
Branch if invalid 2s complement result I
Branch if greater than or equal Isigned)
Branch if equal
Branch if not equal
Branch if less than or equal (signed)
Branch if valid 2s compiement result
Branch if less than (signed)
UNSIGNED BRANCHES
Branch if higher (unsigned)
Branch if higher or same (unsigned)
Branch if higher or same (unsigned)
Branch if equal
Branch if not equal
Branch if lower or same (unsigned)
Branch if lower (unsigned)
Branch if lower (unsigned)
OTHER BRANCHES
Branch to subroutine
Branch always
Branch never

TABLE 8 Instruction
ANDCC
CWAI
NOP
ORCC
JMP
JSR
RTI
RTS
SWI, SWI2, SWI3
SYNC

MISCELLANEOUS INSTRUCTIONS
Description

AND condition code register
AND condition code register, then wait for interrupt
No operation
OR condition code register
Jump
Jump to subroutine
Return from interrupt
Return from subroutine
Software interrupt (absolute indirect)
Synchronize with interrupt line

3-260

MC6809

TABLE 9 -

HEXADECIMAL VALUES OF MACHINE CODES

OP

Mnem

Mode

-

#

OP

Mnem

Mode

00

NEG

Direct

6

2

*
*

LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU

Indexed

01
02
03

30
31
32
33
34
35
36
37

38

*

39
3A
3B
3C
3D
3E
3F

RTS
ABX
RTI
CWAI
MUL

04

COM
LSR

05

*

06

ROR
ASR
ASL, LSL
ROL
DEC

07
08

09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
lC

10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F

6
6

2
2

6
6
6
6
6

2
2
2
2
2

6
6

*
INC
TST
JMP
CLR

Direct

6

2
2
2
2

-

-

-

-

-

-

3

Page 2
Page 3
NOP
SYNC

Inherent 2
Inherent ;::4

1
1

Relative
Relative

5
9

3
3

Inherent
Immed

2
3

1
2

3
2
8
6

2
1
2
2

*
*
LBRA
LBSR

40
41
42
43
44
45
46
47

48

*
DAA
ORCC

*

-

ANDCC
SEX
EXG
TFR
BRA
BRN
BHI
BLS
BHS, BCC
BLO, BCS
BNE
BEG
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE

Immed
Inherent
Immed
Immed
Relative

Relative

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57

58
59
5A
5B
5C
5D
5E
5F

t

Indexed
Immed
Immed
Immed
Immed

#

OP

Mnem

Mode

4+
4+
4+
4+
5+
5+
5+
5+

2+
2+
2+
2+
2
2
2
2

60

NEG

Indexed

61
62
63

*
*

5
3

1
1
1
2
1

t

Inherent

6/15
;::20
11

-

*
SWI

Inherent

19

1

NEGA

Inherent

2

1

*
*
2
2

1
1

2
2
2
2
2

1
1
1
1
1

2
2

1
1

*
RORA
ASRA
ASLA, LSLA
ROLA
DECA

*
INCA
TSTA

*
CLRA

Inherent

2

1

NEGB

Inherent

2

1

2
2

1
1

2
2
2
2
2

1
1
1
1
1

2
2

1

2

1

*
*
COMB
LSRB

*
RORB
ASRB
ASLB, LSLB
ROLB
DECB

*
INCB
TSTB

1

*
Inherent

- Number of MPU cycles (less possible push pull or indexed-mode cycles)

# Number of program bytes
Denotes unused opcode

3-261

COM
LSR

65

*

66

ROR
ASR
ASL, LSL
ROL
DEC

67
69
6A
6B
6C
6D
6E
6F
70
71

72

COMA
LSRA

CLR8

64

68

-

Inherent

LEGEND:

*

-

73
74
75
76

77
78
79
7A

NEG

6+
6+

2+
2+

6+
6+
6+
6+
6+

2+
2+
2+
2+
2+

6+
6+
3+
6+

2+
2+
2+
2+

Indexed

Extended 7

3

7
7

3
3

7
7
7
7
7

3
3
3
3
3

7
7
4
Extended 7

3
3
3
3

*
ROR
ASR
ASL, LSL
ROL
DEC

*

80
81
82
83

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA

89
8A
8B
8C
8D
8E
8F

It

COM
LSR

INC
TST
JMP
CLR

88

2+

*
*

7C
7D
7E
7F

85
86
87

#

6+

*
INC
TST
JMP
CLR

78

84

-

Immed

2
2
2

2
2
2

4

3

2
2
2

2
2
2

2
2
2
2
4
7
3

2
2
2
2
3
2
3

*
EORA
ADCA
ORA
ADDA
CMPX
BSR
LDX

*

Immed
Relative
Immed

I

MC6809

TABLE 9 OP

Mode
Direct

99
9A
9B
9C
90
9E
9F

Mnem
SUBA
CMPA
SBCA
SUBD
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
AODA
CMPX
JSR
LOX
STX

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LOX
STX

Indexed

90
91
92
93
94
95

96
97

98

I

BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LOX
STX

I

Direct

Indexed

-

OP

Mnem

Mode

4
4
4
6
4
4
4
4
4
4
4
4
6
7
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LOB

Immed

"

4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
OF
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC

Extended 5
5
5
7
5
5
5
5
5
5
5
5
7
8
6
Extended 6

,

HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED)

#

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

NOTE: All unused opcodes are both undefined
and illegal

r

Immed
Immed

*

-

#

2
2
2
4
2
2
2

2
2
2
3
2
2
2

I

2
2
2
2
3

2
2
2
2
3

Immed

3

3

SUBB
CMPB
SBCB
AODO
ANDB
BITB
LOB
STB
EORB
ADCB
ORB
AOOB
LDO
STD
LOU
STU

Direct

4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

Indexed

EE
EF

SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
ADDB
LOO
STO
LOU
STU

4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

SUBB
CMPB
SBCB
AOOD
ANDB
BITB
LOB
STB
EORB
AOCB
ORB
AD DB
LOO
STD
LOU
STU

Extended 5
5
5
7
5
5
5
5
5
5
5
Extended 5
Extended 6
6
6
Extended 6

ED

EORB
AOCB
ORB
ADDB
LDD

*
LOU

I

Direct
j

W

Indexed

t

3-262

3

3
3
3
3

3
3
3
3
3
3

3
3
3
3

3

OP

IMnem

T

Mode

I- I #

Page 2 and 3 Machine
Codes
1021
1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
1020
102E
102F
103F
1083
lOBC
lOBE
1093
l09C
l09E
l09F
10A3
lOAC
10AE
lOAF
10B3
10BC
lOBE
10BF
10CE
lODE
100F
lOEE
10EF
lOFE
10FF
113F
1183
118C
1193
119C
llA3
llAC
llB3
llBC

LBRN
LBHI
LBLS
LBHS. LBCC
LBCS. LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
SWI2
CMPD
CMPY
LOY
CMPO
CMPY
LOY
STY
CMPD
CMPY
LOY
STY
CMPD
CMPY
LOY
STY
LOS
LOS
STS
LOS
STS
LOS
STS
SWI3
CMPU
CMPS
CMPU
CMPS
CMPU
CMPS
CMPU
CMPS

Relative

t
Relative
Inherent
Immed

I

Immed
Direct

t

Direct
Indexed

~

Indexed
Extended

t

Extended
Immed
Direct
Direct
Indexed
Indexed
Extended
Extended
Inherent
Immed
Immed
Direct
Direct
Indexed
Indexed
Extended
Extended

5
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
20
5
5
4
7
7
6
6
7+
7+
6+
6+
8
8
7
7
4
6
6
6+
6+
7
7
20
5
5
7
7
7+
7+
8
8

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
4
4
4
3
3
3
3
3+
3+
3+
3+
4
4
4
4
4
3
3
3+
3+
4
4
2
4
4
3
3
3+
3+
4
4

MC6809

FIGURE 19 - PROGRAMMING AID

,

Addressing Modes
Instruction

Forms

Immediate
Op
#

Op

-

#

Indexed
Op
#

Extended
Op
#

99
09

4
4

2
2

A9
E9

4+
4+

2+
2+

B9
F9

5
5

3
3

A+M+C-A
B+M+C-B

2
2
2

AB 4+
EB 4+
E3 6+

2+
2+
2+

BB
FB
F3

5
5
7

3
3
3

A+M-A
B+M-B
D+M:M+1-D

2
2

A4 4+

2+
2+

B4
F4

5
5

3
3

AA M-A
B A M-B
CC A IMM-CC

-

Direct

-

-

ABX
ADCA
ADCB

89
C9

2
2

ADD

ADDA
ADDB
ADDD

8B
CB
C3

2
2
4

2
2
3

9B
DB
03

4
4
6

AND

ANDA
ANDB
ANDCC

84

2
2
3

2
2
2

94

C4
1C

4
4

ASL

ASR

E4

4+

~}[H
I lim I ~O
c
b7
bO

6+

2+

78

7

3

ASRA
ASRB
ASR

07

6

2

67

6+

2+

77

7

3

95
05

4
4

2
2

A5 4+
E5 4+

2+
2+

B5
F5

5
5

3
3

OF

6

2

6F

6+

2+

7F

7

3

91
D1
10
93
11
9C
11
93
9C
10
9C

4
4
7

2
2
3

4+
4+
7+

2+
2+
3+

3
3
4

Compare M from A
Compare M from B
Compare M:M + 1 from 0

3

7+

3+

7

3

7+

3+

6
7

2
3

6+
7+

2+
3+

B1
F1
10
B3
11
BC
11
B3
BC
10
BC

5
5
8

7

A1
E1
10
A3
11
AC
11
A3
AC
10
AC

CMPS
CMPU
CMPX
CMPY

48

58

2
2

2
2

5

2
2

2
2
4

5

4

5

4

4
5

3
4

COMA
COMB
COM

CWAI

03
3C

~2(

6

2

63

6+

2+

73

DECA
DECB
DEC

EOR

EORA
EORB

EXG

R1, R2

JNC

INCA
INCB
JNC

88
C8

2
2

1E

8

Compare M: M + 1 from S

4

Compare M:M + 1 from U

7

3
4

Compare M:M + 1 from X
Compare M:M + 1 from Y

8

7

OA

6

2

6A

6+

2+

7A

7

3

98
D8

4

2
2

A8
E8

4+
4+

2+
2+

B8
F8

5
5

3
3

4

2
2

1 A-A
1 B-B
M-M

19

2

1 DeCimal Adjust A

4A
5A

2
2

1 A-1-A
1 B-1-B
M-1-M
A"';-M-A
B¥M-B
R1-R22

6

2

JMP

OE

3

JSR

90

7

96
D6
DC
10
DE
DE
9E
10
9E

LDU
LDX
LDY

43
53
3

2
2
3
4

3
3
4

3
3
4

3

2+

7E

4

3

2+

BD

8

3

Jump to Subroutine

A6 4+
E6 4+
EC 5+
10 6+
EE
EE 5+
AE 5+
10 6+
AE

2+
2+
2+
3+

B6
F6
FC
10
FE
FE
BE
10
BE

5
5
6
7

3
3
3
4

M-A
M-B
M:M+1-D
MM+ 1-3

6
6
7

3
3
4

M:M+1-U
MM+1-X
MM+1-Y

32

2+
2+
2+
2+

2+

2

6E

3+

2

AD 7+

4
4
5
6

2
2
2

5
5
6

2
2
3

4+

33 4+
30 4+
31

4+

2+
2+
3+

EA3_S
EA3_U
EA3_X
EA3_y

M

Complement of M
Transfer Into

Number of MPU Cycles

H

Half-carry (from bit 3)

Number of Program Bytes

N

Negative (sign bit)

Arithmetic Plus

Z

Arithmetic Minus

V

Zero result
Overflow, 2's complement

Multiply

C

Carry from ALU

Operation Code I Hexadecimal)

1 A+ 1--A
1 B+ 1-B
M+1-M
EA3_PC

7

6+

3

2
2

7C

6C

LEAS
LEAU
LEAX
LEAY

LEGEND:

C

1 O-A
1 O-B
O-M

4

2

2
2
3
4

50

8

4C
5C

86
C6
CC
10
CE
CE
8E
10
8E

~}ql mTil HJ

CC A IMM-CC Walt for Interrupt

OC

LOA
LOB
LDD
LDS

2
2

2

2
2

1
1

8

DAA
DEC

2
2

b7
Bit Test A 1M A A)
Bit Test B 1M A Bt
4F
5F

81
C1
10
83
11
8C
11
83
8C
10
8C

1
1

M
47
57

85
C5

2
2

3-263

I
I

I
I

I
I

I
I

I
I

I
I

I
I
I

I
I
I
0
0

I
I
I

I
I

I
I
I
I
I

8
8
8

I
I
I

I
I
I

I
I
I

8
8
8

I
I
I

I
I
I

I
I

I
I

0
0

0
0
0

1
1
1

0
0
0

0
0
0

I
I
I

I
I
I

I
I
I

I
I
I

I

I

I

I

I

I

I

I

I
I

I
I

I
I

I
I

··
·

68

CMPA
CMPB
CMPD

LEA

·· ·· ·

B + X- X IUnsigned)

2

CLRA
CLRB
CLR

LD

1

6

CLR

COM

04

3

08

BITA
BITB

CMP

2
2

0
5 3 2
H N Z V C

Description

ASLA
ASLB
ASL

BIT

+

-

3A

ADC

OP

Inherent
Op
#

··
7
I
I
I

··
·
··· ··
··
·
·
8
8

·
··

I
I
I

··
·
··· ··
·· ··
··· · · · ···
·· ··
·· ·· ·· ·· ··
··· ···
· ·
··· ···
·· ·· ·· ·· ··
·· ·· ·· ··
I
I
I

I
I
I

0
0
0

I

I

0

I
I
I

I
I
I

I
I
I

I
I

I
I

0
0

I
I
I

I
I
I

I
I
I

I
I
I
I

I
I
I
I

0
0
0
0

I
I
I

I
I
I

0
0
0

1
1
1

7
I

I
I

Test and set if true, cleared otherwise
Not Affected
CC

Condition Code Register
Concatenation

V

Logical or

A
¥

Logical and
Logical Exclusive or

I

MC6809

FIGURE 19 -

Instruction
LSL

LSR

Forms

Immediate
Op
#

-

Direct
Op

PROGRAMMING AID (CONTINUED)

Addressing Modes
Indexed1
Extended
# Op
# Op
#

-

LSLA
LSLB
LSL

08

6

2

68

6+

2+

78

7

3

LSRA
LSRB
LSR

04

6

2

64

G+

2+

74

7

3

48

NEGA
NEGB
NEG

00

6

2

60

6+

2+

70

7

3

9A
DA

4
4

2
2

AA 4+
EA 4+

2+
2+

BA
FA

5
5

3
3

OR

ORA
ORB
ORCC

8A
CA
1A

PSH

PSHS
PSHU

PUL

PULS
PULU

34 5+ 4
36 5+ 4
35 5+ 4
37 5+ 4

ROL

ROLA
ROLB
ROL

09

6

2

69

6+

2+

79

7

3

RORA
RORB
ROR

06

6

2

66

6+

2+

76

7

3

ROR

2
2
3

2
2
2

1
1

2
2

1
1

~}[J.-1liTllll ~O
b7

b7

3D

11

1 Ax B-O (Unsigned;

40

50

2
2

1 A+ 1-A
1 B+ 1-B
M+1-M

12

2

1 No Operation

Push Registers on S Stack
Push Registers on U Stack

2
2

Pull Registers from S Stack
Pull Registers from U Stack
2
2
2
2

1
1
1
1

t

I
I

2+
2+

B2
F2

5
5

3
3

97
D7
OD

4
4
5
6

2
2
2
3

A7
E7

4+
4+
5+
6+

2+
2+
2+
3+

67
F7

[)

5
6
7

3
3
3
4

A-M
B-M
D-MM+1
S-MM+1

STU
STX
STY

5
5
6

2
2
3

5+
5+

2+
2+

6
6
7

3
3
4

U-MM+1
X-M.M+1
Y-M.M+1

SUB

SWI

SUBA
SUBB
SUBO
SWI6
SWI2 6

80
CO
83

2
2
4

2
2
3

4
4
6

2
2
2

5
5
7

3
3
3

A-M-A
B-M-B
0-M:M+1-0

90
DO
93

10
EF
EF
AF
10
AF

FD

6+

3+

10
FF
FF
BF
10
BF

AO 4+
EO 4+
A3 6+

2+
2+
2+

BO
FO
B3

SWI3 6
SYNC
TFR

R1, R2

TST

TSTA
TSTB
TST

1F

6

A-M-C-A
B-M-C-B

19
20

1 Software Interrupt 1
2 Software Interrupt 2

20

1 Software Interrupt 3

13

>4

1 SynchrOnize to Interrupt

40
50

2
2

R1-R2L

00

6

2

6D

6+

2+

70

7

3

bO

1 Test A
1 Test B
Test M

I
I
I

7

8
8

1 Sign Extend B Into A

3F
10
3F
11
3F
2

I
I
I

I
I
I

t

4+
4+

ED

0
0
7

9

I
I

A2
E2

10

I
I

I
I
I

I
I
I

2
2

DF
OF
9F
10
9F

I
I

I

b7

4
4

2

I
I
I

I
I
I

c

92
D2

10
STA
STB
STD
STS

I
I
I

··
··

I
I
I

1 Return from Subroutine

ST

I
I
I

I
I
I

I
I
I

1 Return From Interrupt

SEX

0
0
0

···
··

I
I
I

1111111
b7
bO

39
2
2

I
I
I

c

3B 6/15
5

I
I
I

·····
·· ··
·· · ·· ·· ··
··· ·· ·· · ··
~lL[H
P ·
· ·
~}4HIIIIIIIP ··
· ··
·····
··· ···
·· ··
·· ··
· ·

2
2

46
56

2
2

c

A V M-A
B V M-B
CC V IMM-CC

49
E·9

82
C2

bO

···
8
8
8

RTS
SBCA
SBCB

bO

~} 0 ~ III III I HJ

RTI
SBC

5 3 2 1 0
H N Z V C

Description

c

44
54

NOP

I

2
2

58

MUL
NEG

Inherent
Op
#

8
8

I
I

I
I

I

t

0

I
I
I
I

I '0
I 0
I 0
I 0

I
I
I

I
I
I

0
0
0

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

0
0
0

I
I

I
I

I
I
I

·· · · · ·
·····
·····
·· ·· ·· ·· ··
· ·
·· ··

NOTES:
1. This column gives a base cycle and byte count. To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table,
Table 2.
2. R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, 0, PC
3. EA is the effective address.
4. The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte pushed or pulled.
5. 5(6) means: 5 cycles if branch not taken, 6 cycles if taken (Branch instructions).
6. SWI sets I and F bits. SWI2 and SWI3 do not affect I and F.
7. Conditions Codes set as a direct result of the instruction.
8. Vaue of half-carry flag is undefined.
9. Special Case - Carry set if b7 is SET.

3-264

MC6809

FIGURE 19 -

PROGRAMMING AID (CONTINUED)
Branch Instructions

Addressing
Mode
Relative
Instruction
BCC

Forms
BCC
I LBCC

OP -5

#

Description

24
3
10 5161
24

Branch C~ 0
Long Branch

BCS
LBCS

25
3
10 5161
25

2 Branch C ~ 1
4 Long Branch

BEQ

BEQ
LBEQ

27
3
10 5161
27

Branch Z = 1
Long Branch

2C
3
10 5161
2C

2 Branch ~ Zero
4 Long Branch ~ Zero

BGT

BGT
LBGT

2E
3
10 5161
2E

2
4

BHI
LBHI

22
10
22

3
5161

BHS

24

3

LBHS

10 5161
24
2F
3
10 .5161
2F

BLE
LBLE

BLO

BLO
LBLO

.

Branch> Zero
Long Branch> Zero
Branch Higher
Long Branch Higher

2
4

Branch Higher
or Same
Long Branch Higher
or Same
Branch!5 Zero

Long Branch s Zero
Branch lower
Long Branch Lower

25
3
10 5161
25

·
.

.·

. . ·
.

SIMPLE BRANCHES

r>m
r~m

r=m
r:sm
rm

BGT
BGE
BEQ
BlE
BlT

2E
2C
27
2F
2D

BlE
BLT
BNE
BGT
BGE

2F
2D
26
2E
2C

r~m

r=m
r:sm
r<>OOQ.
'---___
AVMA~===~n~~I============================================~~~~~~:=~~~~~~
BUSY
LlC

~

1\

/

* E clock shown for reference only.
NOTE: Timing measurements are refererlced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted .

\

III
3:

FIGURE 9 -

last Cycle
of Current
1Instruction

1 m-2

1 m-l

Instruction
Fetch

Interrupt Stacking and Vector Fetch Sequence

.1..:

I(

m

1

m+ 1

1 m+2

1 m+3

n
en
CO
o
U)

FIRQ INTERRUPT TIMING

1 m+4

1

m+5

1

m+6

)11(
1 m+ 7

1 m+8

1

m

.1

m+9

n+l

$FFFF

New PC New PC+l

n+

E*
Q

Address
Bus

-4

r-

- - - --P-C- --PC--

F'F"F'F

~ ~

SP-3

$FFFF

$FFF6

$FFF7

PC S

FIRQ

~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Data
~

VMA

N
......

PCl

PCH

CCR

VMA

New PCH

New PCl

VMA

0)

R/W=

\

1'-----------

BA=
B S = ' - - - - - - - - - - - - I - - - - \-~-AVMA

BUSY

LlC

r--\

==:)

1

* E clock shown for reference only.

•
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

~

\'---___

Me6S0gE

FIGURE 10 -

CLOCK GENERATOR

,- - - - - - - - - - - - - - - - - - - ,
,I

I
I
I

+5V

I
I

I

I

STRETCH

I

Optional
MRDY ICircuit

IMRDY

I
I

I

I

I

I
___ ..J

'-------

. - - - + - - - - - - - - - - - r..... Q to

System and Processor

~_---------r-" E to System

+5 V

NOTE: If optional circuit is not included the CLR and PRE
inputs of U2 and U3 must be tied high.

FIGURE 11 -

READ-MODIFY-WRITE INSTRUCTION EXAMPLE (ASL EXTENDED INDIRECT)

Memory
Location

Memory
Contents

PC-$02oo

$68

$0201

$9F

Extended Indirect Post byte

$0202

$63

Indirect Address Hi-Byte

$0203

$00

$0204

L--

-

Contents Description

ASL Indexed Opcode

Indirect Address Lo-Byte

-

$6300~
$6301~

Next Main Instruction

Effective Address Hi-Byte
Effective Address Lo-Byte

Target Data

3-277

I

•
Last Cycle of
Current Instr.

FIGURE 12 -

m

m-1

m+1

m+3

m+2

3:
en
00
o
(')

BUSY TIMING

m+4

m+6

m+5

m+7

m+B

m+9

I

m+10

CD

m

o

Data

~

X

$68

X
$63

X

X
VMA

$00

X

X

$E3

X
V"f\lA

$06

X
$5C

X
Wl1A

Y

R/W-=:J..
BUSY

X
$9F

\

A

/,

/

X
$BB

I~---

,'--_ _ _ __

LlC _ _ _-....J
AVMA _ _ _-"

E
~

N
......

Q)

FIGURE 13 - TSC TIMING

a\

TSC

AlW,

Add~

MPUD",

tPcs~ 'k

!l7Y~ tt

TSD

.

----~

)

\

1

1

pcs
f_t
_

t: r
I

C'l_

t -1' ~SA~ i r;......-~-sv-T SV

---I

-.j ;. . .-~t- '-"TS_V
L:J' J
(. . . . . ,. __
!--tDDW

__

"-See Note 1
NOTES:
1. Data will be asserted by the MPU only during the interval while R/IN is low and (E or 0) is high. A composite bus cycle is shown to give most cases of
timing.
2. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

FIGURE 14 -

3:
n
~

FLOWCHART FOR MC6809E INSTRUCTIONS

CO

o

CD

m

U)

N

.......

CO

Bus State

NOTES: 1. Asserting RESET will result in entering the reset
sequence from any point in the flowchart.
2. BUSY is high during first vector fetch cycle.

BA I BS

Running

010

Interrupt or Reset Acknowledge I

0

Sync Acknowledge
Halt Acknowledge

o

Me6S0gE

ADDRESSING MODES

I

The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The
MC6809E has the most complete set of addressing modes
available on any microcomputer today. For example, the
MC6809E has 59 basic instructions; however, it recognizes
1464 different variations of instructions and addressing
modes. The addressing modes support modern programming techniques. The following addressing modes are available on the MC6809E:
Inherent (Includes Accumulator)
Immediate
Extended
Extended Indirect
Direct
Register
Indexed
Zero-Offset
Constant Offset
Accumulator Offset
Auto Increment/ Decrement
Indexed Indirect
Relative
Short/Long Relative Branching
Program Counter Relative Addressing

EXTENDED INDIRECT
As a special case of indexed addressing (discussed
below), one level of indirection may be added to extended
addressing. In extended indirect, the two bytes following the
post byte of an indexed instruction contain the address of the
data.
LOA [CAT)
LDX
[$FFFEl
STU
[DOG)
DIRECT ADDRESSING
Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower eight bits of the address to be used. The
upper eight bits of the address are supplied by the direct
page register. Since only one byte of address is required in
direct addressing, this mode requires less memory and executes faster than extended addressing. Of course, only 256
locations (one page) can be accessed without redefining the
contents of the DP register. Since the DP register is set to
$00 on reset, direct addressing on the MC6809E is upward
compatible with direct addressing on the M6800. Indirection
is not allowed in direct addressing. Some examples of direct
addressing are:
LOA where DP = $00
LOB
where DP= $10
LDD


U'I

,

I

BA ~

\~

BS~

,
i

AVMA~
LIC
IRQ,
NMI
FIRQ

_________

~

\

I

~

l·
,

~tiltPCf

~

See Note 1

~
See Note 2
__ _________________________________________
__
~tPcs

VIL~~

NOTES: 1. If the associated mask bit is set when the interrupt is requested, LlC will go low and this cycle will be an instruction fetch from address
location PC + 1. However, if the interrupt is accepted (NMI or an unmasked FIRQ or IRQ) Lie will remain high and interrupt processing
will start with this cycle as m on Figures 8 and 9 (Interrupt Timing).
2. If mask bits are clear, IRQ and"FiRTI' must be held low for three cycles to guarantee that interrupt will be taken, although only one cycle
is necessary to bring the processor out of SYNC.
3. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted .

..

MC6809E

FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 1 of 5)

I
NOTES
1. Each state shows'
Data Bus .----:::-::----:-::-:----,
Address Bus '--~~"";';:::.......J
2. Address NNNN is location of opcode
3. If opcode is a two byte opcode subsequent
addresses are in parenthesis (-)
4. Two-byte opcodes are highlighted

No

Me6S0gE

FIGURE 17 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 2 of 5)

I

3-287

Me6S0gE

FIGURE 17 -

CYCLE-BY-CYLE PERFORMANCE (Sheet 3 of 5)

I

3-288

Me6S0gE

FIGURE 17 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet4of5)

II
Constant Offset from A
No Offset

8·8,10ffsRt
Offset Low Byte

Auto Increment/Decrement A

Incrementby2
Decrement by2

Index
Index

Constant Offsellrom PC
~--

15-blt Offset

Offset Low Byte

ExtendedlndlreCl
16 BI1 Address
*Themdex register

Address High Byte Addres low Bvte
IS

mcremenled following the Indexed access

3-289

Me6S0gE

FIGURE 17 -

CYCLE-BY-CYCLE PERFORMANCE (Sheet 5 of 5)

Effective Address

ANDCC,
ORCC
(Immediate
Only)

II

JMP
(All Except

Immediate)

Effective Address (EAI
Constant Offset from A

No Offset
5·811 Offset
8-81\ Offset
16·81\ Offsp.!

+ Post Byte
+ Po", Rytp. High- Post Rylp. low

Index Register + 0

Index

-1

Index

-2

Constant Offset from PC
8-Blt Offset
16-811 Offset

Offset Low Byte

Direct Page Register Address Low
Address High Address Low

The rndex register

IS

Incremented following themde'xed access

3-290

Me6S0gE

TABLE 4 - 8-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS
Operation

Mnemonic(s)

ADCA,ADCB

Add memory to accumulator with carry

ADDA,ADDB

Add memory to accumulator

ANDA,ANDB

And memory with accumulator

ASL, ASLA, ASLB

Arithmetic shift of accumulator or memory left

ASR, ASRA, ASRB

Arithmetic shift of accumulator or memory right

BITA, BITB

Bit test memory with accumulator

CLR, CLRA, CLRB
CMPA,CMPB

Clear accumulator or memory location
Compare memory from accumulator

COM, COMA, COMB

Complement accumulator or memory location

DAA

Decimal adjust A accumulator

DEC, DECA, DECB

Decrement accumulator or memory location

EORA, EORB

Exclusive or memory with accumulator

EXG Rl, R2
INC, INCA, INCB

Exchange Rl with R2 (Rl, R2 = A, B, CC, DP)
Increment accumulator or memory location

LDA, LDB

Load accumulator from memory

LSL, LSLA, LSLB

Logical shift left accumulator or memory location

LSR, LSRA, LSRB

Logical shift right accumulator or memory location

MUL

Unsigned multiply (A x B -

NEG, NEGA, NEGB

Negate accumulator or memory

D)

ORA, ORB

Or memory with accumulator

ROL, ROLA, ROLB

Rotate accumulator or memory left

ROR, RORA, RORB

Rotate accumulator or memory right

SBCA, SBCB

Subtract memory from accumulator with borrow

STA, STB

Store accumulator to memory

SUBA, SUBB

Subtract memory from accumulator

TST, TSTA, TSTB
Test accumulator or memory location
TFR Rl, R2
Transfer Rl to R2 (Rl, R2 = A, B, CC, DP)
NOTE: A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS,
PULU) instructions.
TABLE 5 Mnemonic(s)

16-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS
Operation

ADDD

Add memory to D accumulator

CMPD
EXG D, R

Compare memory from D accumulator
Exchange D with X, Y, S, U or PC

LDD

Load D accumulator from memory

SEX

Sign Extend B accumulator into A accumulator

STD

Store D accumulator to memory

SUBD

Subtract memory from D accumulator

TFR D, R

Transfer D to X, Y, S, U or PC

TFR R, D

Transfer X, Y, S, U or PC to D

NOTE: D may be pushed (pulled) to either stack with PSHS., PSHU (PULS,
PULU) instructions.
TABLE 6 Instruction

INDEX REGISTER/STACK POINTER INSTRUCTIONS
Description

CMPS, CMPU

Compare memory from stack pointer

CMPX, CMPY

Compare memory from index register

EXG Rl, R2

Exchange D, X, Y, S, U or PC with D, X, Y, S, U or PC

LEAS, LEAU

Load effective address into stack pointer

LEAX, LEAY

Load effective address into index register

LDS, LDU

Load stack pOinter from memory

LDX, LDY

Load index register from memory

PSHS

Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack

PSHU

Push A, B, CC, DP, D, X, Y, S, or PC onto user stack

PULS

Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack

PULU

Pull A, B, CC, DP, D, X, Y, S or PC from hardware stack

STS, STU

Store stack pointer to memory

STX, STY

Store index register to memory

TFRR1,R2

Transfer D, X, Y, S, U or PC to D, X, Y, S, U or PC

ABX

Add B accumulator to X (unsigned)

3-291

I

Me680gE

TABLE 7 -

BRANCH INSTRUCTIONS
Description

Instruction

SIMPLE BRANCHES

BEQ, LBEQ

Branch if equal

BNE, LBNE

Branch if not equal

BMI, LBMI

Branch if minus

BPL, LBPL

Branch if plus

BCS, LBCS

Branch if carry set

BCC, LBCC

Branch if carry clear

BVS, LBVS

Branch if overflow set

BVC, LBVC

Branch if overflow clear

BGT, LBGT

Branch if greater (signed)

SIGNED BRANCHES

I

BVS, LBVS

Branch if invalid 2's complement result

BGE, LBGE

Branch if greater than or equal (signed)

BEQ, LBEQ

Branch if equal

BNE, LBNE

Branch if not equal

BLE, LBLE

Branch if less than or equal (signed)

BVC, LBVC

Branch if valid 2's complement result

BLT,LBLT

Branch if less than (signed)

BHI, LBHI

Branch if higher (unSigned)

BCC, LBCC

Branch if higher or same (unSigned)

UNSIGNED BRANCHES

BHS, LBHS

Branch if higher or same (unSigned)

BEQ, LBEQ

Branch if equal

BNE, LBNE

Branch if not equal

BLS, LBLS

Branch if lower or same (unsigned)

BCS, LBCS

Branch if lower (unsigned)

BLO, LBLO

Branch if lower (unsigned)

BSR, LBSR

Branch to subroutine

OTHER BRANCHES

BRA, LBRA

Branch always

BRN, LBRN

Branch never

TABLE 8 -

MISCELLANEOUS INSTRUCTIONS
Description

Instruction

ANDCC

AND condition code register

CWAI

AND condition code register, then wait for interrupt

NOP

No operation

ORCC

OR condition code register

JMP

Jump

JSR

Jump to subroutine

RTI

Return from interrupt

RTS

Return from subroutine

SWI, SWI2, SWI3

Software interrupt (absolute indirect)

SYNC

Synchronize with interrupt line

3-292

Me6S09E

TABLE 9 -

HEXADECIMAL VALUES OF MACHINE CODES

OP

Mnem

Mode

-

#

OP

Mnem

Mode

00

NEG

Direct

6

2

*
*

35
36
37

LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU

Indexed

01
02
03

30
31
32
33

38

*

39
3A
3B
3C
3D
3E
3F

RTS
ABX
RTI
CWAI
MUL

)

04

COM
LSR

05

*

06

ROR
ASR
ASL, LSL
ROL
DEC

07

08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C

6
6

2
2

6
6
6
6
6

2
2
2
2
2

6
6
3
6

2
2
2

-

-

-

-

-

-

*
INC
TST
JMP
CLR

Direct

Page 2
Page 3
NOP
SYNC

Inherent 2
Inherent 2:4

2

1
1

*
*
LBRA
LBSR

Relative
Relative

5
9

3
3

Inherent 2
Immed 3

1

40
41
42
43
44
45
46
47

48

*
DAA
ORCC

*

2

-

1E
1F

ANDCC
SEX
EXG
TFR

Immed
Inherent
Immed
Immed

3
2
8
6

2
1
2

20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F

BRA
BRN
BHI
BLS
BHS, BCC
BLO, BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE

Relative

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

2
2
2
2
2
2
2
2
2
2
2

10

34

Relative

2

2
2
2
2
2

49
4A
4B
4C
4D
4E
4F
50
51
52
53

54
55
56
57

58
59
5A
5B
5C
5D
5E
5F

t

Indexed
Immed
Immed
Immed
Immed

#

OP

Mnem

Mode

4+
4+
4+
4+
5+
5+
5+
5+

2+
2+
2+
2+
2
2
2
2

60

NEG

Indexed

61
62
63

*
*

Inherent 5
3
6/15
2:20
Inherent 11

t

*

1
1
1
2
1

-

19

SWI

Inherent

NEGA

Inherent 2

1
1

*
*
2

1
1

*
2
2
2
2

1
1
1
1
1

2
2

1
1

CLRA

Inherent 2

1

NEGB

Inherent 2

1

RORA
ASRA
ASLA, LSLA
ROLA
DECA

2

*
INCA
TSTA

*

*
*
2

COMB
LSRB

2

1
1

*
2
2

RORB
ASRB
ASLB, LSLB
ROLB
DECB

2
2

1
1
1
1
1

2
2

1
1

2

*
INCB
TSTB
CLRB

Inherent 2

- Number of MPU cycles (less possible push pull or indexed-mode cycles)

# Number of program bytes
Denotes unused opcode

3-293

1

COM
LSR

65

*

66

ROR
ASR
ASL, LSL
ROL
DEC

67
69
6A
6B
6C
6D
6E
6F
70
71

72

2

COMA
LSRA

*

64

68

-

LEGEND:

*

-

73
74
75
76

77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83

84
85
86
87

88
89
8A
8B
8C
8D
8E
8F

-

#

6+

2+

6+
6+

2+
2+

6+
6+
6+
6+
6+

2+
2+
2+
2+
2+

6+
6+
3+
6+

2+
2+
2+
2+

*
INC
TST
JMP
CLR
NEG

If
Indexed

Extended 7

3

7
7

3
3

7
7
7
7
7

3
3
3
3
3

7
7
4
It'
Extended 7

3
3
3
3

*
*
COM
LSR

*
ROR
ASR
ASL, LSL
ROL
DEC

*
INC
TST
JMP
CLR
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA

Immed

2
2
2
4
2
2
2

2
2
2
3
2

2
2

*
EORA
ADCA
ORA
ADDA
CMPX
BSR
LDX

*

2

It
Immed
Relative
Immed

2

2

2

2
2
4
7
3

2
2
3

2
3

II

Me680gE

TABLE 9 OP
90
91
92
93

97
98
99
9A
9B
9C
9D
9E
9F

Mnem
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX

BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX

94
95

96

I

Mode
Direct
~

4
4
4

Indexed
I

Indexed

HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED)
OP

Mnem

Mode

-

#

CO
Cl
C2
C3
C4
C5
C6

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB

Immed

2
2
2
4
2
2
2

2
2
2
3
2
2
2

C7

*

C8
C9
CA
CB
CC
CD
CE
CF

EORB
ADCB
ORB
ADDB
LDD

4
4
4
4
4
4
4
4
6
7
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

*

4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC

6

Direct

#

Extended 5
5
5
7
5
5
5
5
5
5
5
5
7
8
6
~
Extende d 6

3
3
3
3
3
3
3
3
3
3
3
3
3

3.
3
3

NOTE: All unused opcodes are both undefined
and illegal

I

Immed
Immed

I

2
2
2
2
3

2
2
2
2
3

Immed

3

3

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU

Direct

4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

Indexed
J

EE
EF

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU

4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+

2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+

FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU

Extended 5
5
J
5
7
5
5
5
5
5
5
5
Extended 5
Extended 6
6
6
Extended 6

ED

*
LDU

I

Direct

Indexed

t

3-294

3
3
3
3
3
3
3
3
3
3
3

3
3
3
3
3

OP

IMnem

I

Mode

1- 1#

Page 2 and 3 Machine
Codes
1021
1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
102D
102E
102F
103F
1083
108C
108E
1093
109C
109E
109F
10A3
lOAC
10AE
lOAF
10B3
10BC
lOBE
10BF
10CE
lODE
10DF
lOEE
10EF
10FE
10FF
113F
1183
118C
1193
119C
llA3
llAC
llB3
llBC

LBRN
LBHI
LBLS
LBHS, LBCC
LBCS, LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
SWI2
CMPD
CMPY
LDY
CMPD
CMPY
LDY
STY
CMPD
CMPY
LDY
STY
CMPD
CMPY
LDY
STY
LDS
LDS
STS
LDS
STS
LDS
STS
SWI3
CMPU
CMPS
CMPU
CMPS
CMPU
CMPS
CMPU
CMPS

Relative

Relative
Inherent
Immed

I

Immed
Direct

t

Direct
Indexed

~

Indexed
Extended

t

Extended
Immed
Direct
Direct
Indexed
Indexed
Extended
Extended
Inherent
Immed
Immed
Direct
Direct
Indexed
Indexed
Extended
Extended

5
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
20
5
5
4
7
7
6
6
7+
7+
6+
6+
8
8
7
7
4
6
6
6+
6+
7
7
20
5
5
7
7
7+
7+
8
8

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
4
4
4
3
3
3
3
3+
3+
3+
3+
4
4
4
4
4
3
3
3+
3+
4
4
2
4
4
3
3
3+
3+
4
4

Me6S0gE

FIGURE 18 -

PROGRAMMING AID

Addressing Modes
Instruction

Forms

Immediate
Op
#

Op

-

#

Indexed
Op
#

Extended
Op #

-

Direct

-

ABX

5 3 2

Inherent
Op
#

-

3A

3

ADCA
ADCB

89
C9

2
2

2
2

99
D9

4
4

2
2

A9
E9

4+
4+

2+
2+

B9
F9

5
5

3
3

A+M+C-A
B+M+C-B

ADD

ADDA
ADDB
ADDD

8B
CB
C3

2
2
4

2
2
3

9B
DB
D3

4
4
6

2
2
2

2+
2+
2+

BB
FB
F3

5
5
7

3
3
3

A+M-A
B+M-B
D+M:M+1-D

AND

ANDA
ANDB
ANDCC

84

C4
1C

2
2
3

2
2
2

94
D4

4
4

2
2

AB 4+
EB 4+
E3 6+
A4 4+
E4 4+

2+
2+

B4
F4

5
5

3
3

A A M-A
B A M-B
CC A IMM-CC

ASL

ASR

ASLA
ASLB
ASL

08

6

2

68

6+

2+

78

7

3

ASRA
ASRB
ASR

07

6
4
4

2

67

6+

2+

77

7

3

2
2

A5
E5

4+
4+

2+
2+

B5
F5

5
5

3
3

BIT

BITA
BITB

CLR

CLRA
CLRB
CLR

CMP

CMPA
CMPB
CMPD
CMPS
CMPU
CMPX
CMPY

COM

85
C5

2
2

2
2

95
D5

81
C1
10
83
11
8C
11
83
8C
10
8C

5

2
2

2
2
4

5

4

5

4

4
5

3
4

DECA
DECB
DEC

EaR

EORA
EORB

88
C8

2
2

2
2

EXG

R1, R2

1E

8

2

INC

INCA
INCB
INC

I
I
I

2
2

1
1

~}qlmnIHJ

8
8
8

I
I
I

I
I
I

I
I
0
0
0

I
I
1
1
1

2
2

0
0
0

I
I
I

I
I
I

I
I
I

I
I
I

I

I

I

I

I

I

I

I

I
I

I
I

I
I

I
I

I
I
I

I
I
I

0
0
0

1
1
1

I

I

0

I
I
I

I
I
I

I
I
I

I
I

I
I

0
0

I
I
I

I
I
I

I
I
I

I
I
I
I

I
I
I
I

0
0
0
0

I
I
I

I
I
I

0
0
0

60

4
4
7

2
2
3

4+
4+
7+

2+
2+
3+

3
4

3

7+

3+

8

4

Compare M: M + 1 from S

7

3

7+

3+

8

4

Compare M:M + 1 from U

6
7

2
3

6+
7+

2+
3+

B1
F1
10
B3
11
BC
11
B3
BC
10
BC

5
5
8

7

A1
E1
10
A3
11
AC
11
A3
AC
10
AC

7
8

3
4

Compare M:M + 1 from X
Compare M:M + 1 from Y

6

2

63

6+

2+

73

7

C

1 O-A
1 O-B
O-M

91
D1
10
93
11
9C
11
93
9C
10
9C

Compare M from A
Compare M from B
Compare M M + 1 from D

3

43
53

2
2

1 A-A
1 B-B
M-M

19

2

1 DeCimal Adjust A

4A
5A

2
2

1 A-1-A
1 B-1-B
M-1-M

3

CC A IMM-CC Walt for Interrupt

OA

6

2

6A

6+

2+

7A

7

3

98
D8

d

4

2
2

A8
E8

4+
4+

2+
2+

B8
F8

5
5

3
3

OC

6

2

6C

6+

2+

7

3

6E 3+
AD 7+

2+

7E

4

3

2+

BD

8

3

Jump to Subroutine

A6 4+
E6 4+
EC 5+
10 6-1
EE
EE 5+
AE 5+
10 6+
AE

2+
2+
2+
3+

B6
F6
FC
10
FE
FE
BE
10
BE

5
5
6
7

3
3
3
4

M-A
M-B
MM+1-D
M:M+1-S

6
6
7

3
3
4

MM+1-U
MM+1-X
MM+1-Y

32
33

2+
2+
2+
2+

96
D6
DC
10
DE
DE
9E
10
9E

4
4
5
6

2
2
2
3

5
5
6

2
2
3

+

I
I
I

3

2

LEAS
LEAU
LEA X
LEAY

LEGEND:

I
I
I

7

2

OP

~l[H
I iiTn I ~O
C
b7
bO

8
8
8

7F

3

LEA

I
I

2+

7

3
3
4

I
I

··
·

6+

OE

3
3
4

I
I
I

6F

9D

LDU
LDX
LDY

I
I

I
I
I
0
0

2

JMP
2
2
3
4

I
I

I
I
I

6

JSR
2
2
3
4

I
I

I
I
I

b7
Bit Test A (M A AI
Bit Test B (M A Bi

A-'oI-M-A
B-¥-M-B
f11-R2 2
4C
5C

86
C6
CC
10
CE
CE
8E
10
8E

I
I

I
I

M

2

DEC

1
1

I
I

OF

03
3C 2:r2C

LDA
LDB
LDD
LDS

2

4f5F

DAA

LD

2

58
47
57

COMA
COMB
COM

CWAI

48

·····

1 B + X- X (Unsignedl

ADC

30
31

M

Operation Code (Hexadecimal)

4+
4+
4+
4+

2+
2+
3+

7C

2
2

1 A+ 1--A
1 B+ 1-B
M+1-M
EA3_PC

EA3_S
EA3_ u
EA3_
EA3_ y

x

Complement of M
Half-carry (from bit 3)

Number of Program Bytes

N

Negative (sign bit)

Arithmetic Plus

Z

Zero result

Arithmetic Minus

V

Multiply

C

CC

Condition Code Register
Concatenation

V

Logical or

Overflow, 2's complement

A

Logical and

Carry from ALU

¥

Logical Exclusive or

3-295

·
·
·
·
··
··
·
···
··
8
8

7

··
·
0
0

I
I
I
I
I
I

··
0
0
0

7
I

··
·
·
·· · · · ··
·· ··
·· · · · ··
·· · · · ··
·· ··
· ·
·
·
·· ··
·· ·· ·· ·· ··
·· ·· ·· ··
I
I

Not Affected

H

·
···

··

Test and set if true, cleared otherwise

Transfer Into

Number of MPU Cycles

1 0

H N Z V C

Description

I

Me6S0gE

FIGURE 18 --'- PROGRAMMING AID (CONTINUED)
Addressing Modes
Instruction
LSL

L.SR

Op

-

#

Indexed1
Op
#

Extended
Op
#

LSLA
LSLB
LSL

08

6

2

68

6+

2+

78

7

3

LSRA
LSRB
LSR

04

6

2

64

6+

2+

74

7

3

Forms

Immediate
Op
#

-

Direct

-

-

2
2

54

00

6

2

60

6+

2+

70

7

3

9A
DA

4
4

2
2

AA 4+
EA 4+

2+
2+

BA
FA

5
5

3
3

OR

ORA
ORB
ORCC

8A
CA
1A

PSH

PSHS
PSHU

34 5+ 4

PUL

PULS
PULU

ROL

ROLA
ROLB
ROL

09

6

2

69

6+

2+

79

7

3

RORA
RORB
ROR

06

6

2

66

6+

2+

76

7

3

2
2
3

36 5+ 4
35 5+ 4
37 5+ 4

2
2
2

1
1
1
1

~}D4liTm I
b7

bO

b7

3D

11

1 Ax B-D (Unsigned)

40

50

2
2

1 A+ l-A
1 B+ 1-B
M+1-M

12

2

1 No Operation

Push Registers on S Stack
Push Registers on U Stack

2
2

Pull Registers from S Stack
Pull Registers from U Stack

46
56

2

2

1
1
1
1

STA
STB
STD
STS

I
I
I

2+
2+

B2
F2

5
5

3
3

97
D7
DD
10
DF
DF
9F
10
9F

4
4
5
6

2
2
2
3

A7
E7

4+
4+
5+
6+

2+
2+
2+
3+

B7
F7

5
5
6
7

3
3
3
4

STU
STX
STY

5
5
6

2
2
3

5+
5+

2+
2+

6
6
7

3
3
4

U-MM+1
X-M:M+1
Y-M:M+1

SUB

SUBA
SUBB
SUBD
SW I6
SWI2 6

SWI

80
CO
83

2
2
4

2
2
3

4
4
6

2
2
2

5
5
7

3
3
3

A-M-A
B-M-B
D-M:M+1-D

90
DO
93

FD

6+

3+

10
FF
FF
BF
10
BF

AO 4+
EO 4+
A3 6+

2+
2+
2+

BO
FO
B3

A-M-C-A
B - M - C- B

3F
10
3F
11
3F

SWI36
SYNC
TFR

R1, R2

TST

TSTA
TSTB
TST

1F

6

6

2

6D

6+

2+

7D

7

I
I
I
9
I
I
I

8
8

Sign Extend B into A

I

I

0

I
I
I
I

I
I
I
I

0
0
0
0

I
I
I

I
I
I

0
0
0

I
I
I

I
I
I

I
I
I

20

1

Software Interrupt 3

13

~4

1

Synchronize to Interrupt

4D
5D

2
2

1 Test A
1 Test B
Test M

NOTES:

I
I
I

7

A-M
B-M
D-M:M+1
S-M:M+1

1 Software Interrupt 1
2 Software Interrupt 2

3

I
I
I

I
I
I

I
I

R1-R2L

OD

I
I
I

I
I

19
20

2

I
I
I

I
I
I

4+
4+

10
EF
EF
AF
10
AF

0
0
7

bO

A2
E2

ED

I
I

b7

2
2

1

I
I

c

4
4

2

I
I
I

I
I
I

92
D2

10

ST

I
I
I

I
I
I

1 Return from Subroutine

SEX

I
I
I

bO

1 Return From Interrupt

2
2

I
I
I

b7

39
2
2

0
0
0

c

3B 6/15
5

I
I
I

··· · · · ···
·· ·· ·· ·· ··
·· ·· ·· ·· ··
~}L{H 1111111 P ··
· ·
~} qj:j 1111111 P ··
· ··
·····
··· ···
·· ··
·· ··
· ·

2
2

2
2

I
I
I

I

AV M-A
B V M-B
CC V IMM-CC

49
59

82
C2

c

··
·· ·
··· · ···
8
8
8

RTS
SBCA
SBCB

f.-O
bO

~} 0 ~ III 1111 HJ

RTI
SBC

5 3 2 1 0
H N Z V C

Description

c

44

NEGA
NEGB
NEG

ROR

2
2

58

NOP

I

-

48

MUL
NEG

Inherent
Op
#

8
8

I
I

I
I

I
I
I

·· · · · ·
·····

·····
·· ·· ·· ·· ··
··· ···
I
I
I

I
I
I

0
0
0

1.

This column gives a base cycle and byte count. To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table,
Table 2.

2.

R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, D, PC

3.

EA is the effective address.

4.

The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte pushed or pulled.

5.

5(6) means: 5 cycles if branch not taken, 6 cycles if taken (Branch instructions).

6.

SWI sets I and F bits. SWI2 and SWI3 do not affect I and F.

7.

Conditions Codes set as a direct result of the instruction.

8.

Vaue of half-carry flag is undefined.

9.

Special Case -

Carry set if b7 is SET.

3-296

Me6S09E

FIGURE 1B -

PROGRAMMING AID (CONTINUED)

Branch Instructions

Instruction

Forms

BCC

BCC
lBCC

BCS

BCS
lBCS

Addressing
Mode
Relative
OP -5 I
24
3
10 516)
24
25
3
10 516)
25
27
3
10 5161
27

Description
Branch C=O
long Branch
C=O
2 Branch C= 1
4 long Branch
C=1

5 3

1

H N

V

..

Instruction

23

3

lBlS

10 5161
23

BlT

BLT
lBLT

2D
3
10 5i61
2D

2 Branch Zero
long Branch> Zero

BPl

BPl
lBPl

BHI
lBHI

22
3
10 516)
22
24
3

Branch Higher
long Branch Higher

2A
3
10 516)
2A

BAA

BAA
lBAA
BAN
lBAN

20
16

BHS

2 Branch Higher
or Same
4 long Branch Higher
or Same

lBHS

10 5161
24

BlE

BlE
lBlE

2F
3
10 516)
2F

Branch S Zero
long Branch s Zero

BlO

BlO
lBlO

25
3
10 516)
25

Branch lower
long Branch lower

BAN

...

Description

Branch Z=O
long Branch
Z=O
Branch Plus
long Branch Plus
Branch Always
long Branch Always
Branch Never
long Branch Never

21
10
21

3

1

N

V

2 Branch lower
or Same
4 long Branch Lower
or Same

BlS

BEQ
lBEQ

BHS

!

BlS

BEQ

BHI

Branch Z= 1
long Branch
Z=1
Branch 2: Zero
long Branch 2: Zero

Forms

Addressing
Mode
Relativ
OP -5 #

· ·
.· .

BSA

BSA
lBSA

8D
17

Branch to Subroutine •
long Branch to
Subruutine

BVC

BVC
lBVC

28
3
10 516)
28

Branch V - 0
long Branch
V=O

BVS

BVS
lBVS

29
3
10 5161
29

Branch V= 1
Long Branch
V=1

· · ..
· ·
• i•

i

SIMPLE BRANCHES
OP

SIMPLE CONDITIONAL BRANCHES (Notes 1-4)

BRA
LBRA

20
16

3
5

BRN
LBRN

21
1021

3
5

BSR
LBSR

80
17

7
9

2
4

True

OP

False

OP

r>m

BGT
BGE
BEQ
BLE
BLT

2E
2C
27
2F
20

BLE
BLT
BNE
BGT
BGE

2F
20
26
2E
2C

r~m

r=m
rsm
rm
r~m

r=m
rsm
r---1<111---.
VI

MMD7000
or EQuiv.

C

MMD6150
or Equiv.

R
MMD7000
or Equiv.

C=30pF,R=12k

FIGURE 5 - NMOS EQUIVALENT
TEST LOAD

FIGURE 4 - CMOS EQUIVALENT
TEST LOAD

1

dI

(IRQ Only)

(PAO-PA7, CA2)

Test Point

3, 11
3,11

tlR

-

"The

3,10

tRS3
PWI

tRS2

RESET Low Time"

/los
ns

-

tr,tf

Delay Time, CBl Active Transition to CB2 Positive Transition

Interrupt Input Pulse Time

4,9
3, 11, 12

-

Rise and Fall Time for CBl and CB2 Input Signals

Interrupt Response Time

6

-

0

Control Output Pulse Width, CA2/CB2

Reference
Fig. No.

0

200

tpDH

Delay Time, Enable Positive Transition to CB2 Positive Transition

Unit

100

135

tpDS

Data Hold Time

Delay Time, Data Valid to CB2 Negative Transition

MC68B21
Min Max

-

-

Data Setup Time

Delay Time, Enable Positive Transition to CB2 Negative Transition

I

MC6821
Min Max

5.0 V

r"

T'"

eo;",

"0''

3·310

1.5,.

13

MC6821

FIGURE 6 -

FIGURE 7 - CA2 DELAY TIME
(Read Mode; CRA-5=CRA3=1, CRA-4=0)

PERIPHERAL DATA SETUP AND HOLD TIMES
(Read Mode)

• Assumes part was deselected during
the previous E pulse.

FIGURE 9 - PERIPHERAL CMOS DATA DELAY TIMES
,(Write Mode; CRA-5=CRA-3=1, CRA-4=0)

FIGURE 8 - CA2 DELAY TIME
(Read Mode; CRA-5 = 1, CRA-3 = CRA-4 = 0)

I

Enable

CA1_.~.,~ ~'.~

PAO-PA7,
CA2

~r----I

CA2

FIGURE 11 - CB2 DELAY TIME
(Write Mode; CRB-5= CRB-3= 1, CRB-4= 0)

FIGURE 10 - PERIPHERAL DATA AND CB2 DELAY TIMES
(Write Mode; CRB-5= CRB-3= 1, CRB-4=0)

Enable~

/

Enable

~tPDW
PBO~PB7-----·- - ) { [ - '-1'-------I- tDC--j

J\EtCG2
------CB2

CB2*

-----PWCT

~~I
~tRS1'

• Assumes part was deselected during the
previous E pu IS8

*CB2 goes low as a result of the
positive transition of Enable.

FIGURE 12 - CB2 DELAY TIME
(Write Mode; CRB-5=1, CRB-3=CRB-4=0)

FIGURE 13 -

-'L3-

:::----t

INTERRUPT PULSE WIDTH AND IRQ RESPONSE

c

'Assumes Interrupt Enable Bits are set.

* Assumes part was deselected during

any previous E pulse.

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

3-311

MC6821

RESET LOW TIME

FIGURE 15 -

FIGURE 14 - IRQ RELEASE TIME

t---

~-J

tRL--~1

r-

RES~~______________~~

Enable--1
___
• _tl_'

"The RESET line must be a VIH for a minimum of
1.0 ILs before addressing the PIA.

~I

IRQ

Note: Timing measuremems are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

FIGURE 16 - EXPANDED BLOCK DIAGRAM

I

IROA

38

DO

33

01

32

02

31

I nterrupt Status
Control A

39 CA2

03

30

04

29

05

28

06

27

2

PAO

07

26

3

PAl

4

PA2

5

PA3

6

PA4

A

7 PA5

::l

In

Pin 20

VSS

CAl

Data Direction
Register A
(DORA)

Bus Input
Register
(BIR)

VCC

40

8

PA6

9

PA7

10 PBO

Pin 1

11

PBl

12 PB2
CSO
CS1

24

13

PB3

14

PB4

CS2

23

15 PB5

RSO

36

16 PB6

17 PB7

RS1

35

Riw

21

Enable

25

RESET 34
Data Direction
Register B
(OORB)

Interrupt Status
Control B

IROB 37

3-312

18 CBl
19 CB2

MC6821

PIA INTERFACE SIGNALS FOR MPU
for the duration of the E pulse. The device is deselected
when any of the chip selects are in the inactive state.

The PIA interfaces to the M6800 bus with an 8-bit bidirectional data bus, three chip select lines, two register select
lines, two interrupt request lines, a read/write line, an enable
line and a reset line. To ensure proper operation with the
MC6800, MC6802, or MC6808 microprocessors, VMA
should be used as an active part of the address decoding.

Bidirectional Data (00-07) - The bidirectional data lines
mO-D7) allow the transfer of data between the MPU and the
PIA. The data bus output drivers are three-state devices that
remain in the high-impedance (off) state except when the
MPU performs a PIA read operation. The read/write line is in
the read (high) state when the PIA is selected for a read
operation.
Enable (E) - The enable pulse, E, is the only timing
signal that is supplied to the PIA. Timing of all other signals
is referenced to the leading and trailing edges of the E pulse.
Read/Write (RiW) - This signal is generated by the
MPU to control the direction of data transfers on the data
bus. A low state on the PIA read/write line enables the input
buffers and data is transferred from the MPU to the PIA on
the E signal if the device has been selected. A high on the
read/write line sets up the PIA for a transfer of data to the
bus. The PIA output buffers are enabled when the proper address and the enable pulse E are present.
RESET - The active low RESET line is used to reset all
register bits in the PIA to a logical zero (low). This line can be
used as a power-on reset and as a master reset during
system operation.
Chip Selects (CSO, CS1, and CS2) - These three input
signals are used to select the PIA. CSO and CS1 must be
high and CS2 must be low for selection of the device. Data
transfers are then performed under the control of the enable
and read/write signals. The chip select lines must be stable

Register Selects (RSO and RS1) - The two register
select lines are used to select the various registers inside the
PIA. These two lines are used in conjunction with internal
Control Registers to select a particular register that is to be
written or read.
The register and chip select lines should be stable for the
duration of the E pulse while in the read or write cycle.
Interrupt Request (lROA and IRQB) - The active low Interrupt Request lines IIROA and IROB) act to interrupt the
MPU either directly or through interrupt priority circuitry.
These lines are "open drain" (no load device on the chip).
This permits all interrupt request lines to be tied together in a
wire-OR configuration.
Each Interrupt Request line has two internal interrupt flag
bits that can cause the Interrupt Request line to go low. Each
flag bit is associated with a particular peripheral interrupt
line. Also, four interrupt enable bits are provided in the PIA
which may be used to inhibit a particular interrupt from a
peripheral device.
Servicing an interrupt by the MPU may be accomplished
by a software routine that, on a prioritized basis, sequentially
reads and tests the two control registers in each PIA for interrupt flag bits that are set.
The interrupt flags are cleared (zeroed) as a result of an
MPU Read Peripheral Data Operation of the corresponding
data register. After being cleared, the interrupt flag bit cannot be enabled to be set until the PIA is deselected during an
E pulse. The E pulse is used to condition the interrupt control
lines (CA1, CA2, CB1, CB2)' When these lines are used as
interrupt inputs, at least One E pulse must occur from the inactive edge to the active edge of the interrupt input signal to
condition the edge sense network. If the interrupt flag has
been enabled and the edge sense circuit has been properly
conditioned, the interrupt flag will be set on the next active
transition of the interrupt input pin.

PIA PERIPHERAL INTERFACE LINES
The PIA provides two 8-bit bidirectional data buses and
four interrupti control lines for interfacing to peripheral
devices.

line while a "0" results in a "low." Data in Output Register A
may be read by an MPU "Read Peripheral Data A" operation
when the corresponding lines are programmed as outputs.
This data will be read properly if the voltage on the
peripheral data lines is greater than 2.0 volts for a logic "1"
output-and less than 0.8 volt for a logic "0" output. Loading
the output lines such that the voltage on these lines does not
reach full voltage causes the data transferred into the M PU
on a Read operation to differ from that contained in the
respective bit of Output Register A.

Section A Peripheral Data (PAO-PA7) - Each of the
peripheral data lines can be programmed to act as an input or
output. This is accomplished by setting a ''1'' in the corresponding Data Direction Register bit for those lines which
are to be outputs. A "0" in a bit of the Data Direction
Register causes the corresponding peripheral data line to act
as an input. During an MPU Read Peripheral Data Operation,
the data on peripheral lines programmed to act as inputs appears directly on the corresponding MPU Data Bus lines. In
the input mode, the internal pullup resistor on these lines
represents a maximum of 1.5 standard TTL loads.
The data in Output Register A will appear on the data lines
that are programmed to be outputs. A logical "1" written into the register will cause a "high" on the corresponding data

Section B Peripheral Data (PBO-PB7) - The peripheral
data lines in the B Section of the PIA can be programmed to
act as either inputs or outputs in a similar manner to PAOPA7. They have three-state capabiity, allowing them to enter
a high-impedance state when the peripheral data line is used
as an input. In addition, data on the peripheral data lines

3-313

I

MC6821

PBO-PB7 will be read properly from those lines programmed
as outputs even if the voltages are below 2.0 volts for a
"high" or above 0.8 V for a "low". As outputs, these lines
are compatible with standard TTL and may also be used as a
source of at least 1 milliampere at 1.5 volts to directly drive
the base of a transistor switch.

peripheral control output. As an output, this line is compatible with standard TTL; as an input the internal pullup resistor
on this line represents 1.5 standard TTL loads. The function
of this signal line is programmed with Control Register A.
Peripheral Control (CB2) - Peripheral Control line CB2
may also be programmed to act as an interrupt input or
peripheral control output. As an input, this line has high input impedance and is compatible with standard TTL. As an
output it is compatible with standard TTL and may also be
used as a source of up to 1 milliampere at 1.5 volts to directly
drive the base of a transistor switch. This line is programmed
by Control Register B.

Interrupt Input (CA1 and CB1) - Peripheral input lines
CA 1 and CB 1 are input only lines that set the interrupt flags
of the control registers. The active transition for these
signals is also programmed by the two control registers.
Peripheral Control (CA2) - The peripheral control line
CA2 can be programmed to act as an interrupt input or as a

I

INTERNAL CONTROLS
Notice the differences between a Port A and Port Bread
operation when in the output mode. When reading Port A,
the actual pin is read, whereas the B side read comes from an
output latch, ahead of the actual pin.

IN ITIALIZATION

A RESET has the effect of zeroing all PIA registers. This
will set PAO-PA7, PBO-PB7, CA2 and CB2 as inputs, and all
interrupts disabled. The PIA must be configured during the
restart program which follows the reset.
There are six locations within the PIA accessible to the
MPU data bus: two Peripheral Registers, two Data Direction
Registers, and two Control Registers. Selection of these
locations is controlled by the RSO and RSl inputs together
with bit 2 in the Control Register, as shown in Table 1.
Details of possible configurations of the Data Direction
and Control Register are as follows:

CONTROL REGISTERS (CRA and CRB)

The two Control Registers (CRA and CRB) allow the MPU
to control the operation of the four peripheral control lines
CA 1, CA2, CB 1, and CB2. In addition they allow the MPU to
enable the interrupt lines and monitor the status of the interrupt flags. Bits 0 through 5 of the two registers may be written or read by the MPU when the proper chip select and
register select signals are applied. Bits 6 and 7 of the two
registers are read only and are modified by external interrupts
occurring on control lines CA 1, CA2, CB 1, or CB2. The format of the control words is shown in Figure 18.

TABLE 1 - INTERNAL ADDRESSING
Control
Register Bit
RSO

CRA·2

CRB-2

0

0

1

X

0

0

0

X

Data Direction Register A

Peripheral Register A

0

1

X

X

Control Register A

1

0

X

1

Peripheral Register B

1

0

X

0

Data Direction Register B

1

1

X

X

Control Register B

x~

DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and
CRB-2)

Location Selected

RSl

Bit 2, in each Control Register (CRA and CRB), determines selection of either a Peripheral Output Register or the
corresponding Data Direction E Register when the proper
register select signals are applied to RSO and RS1. A "1" in
bit 2 allows access of the Peripheral Interface Register, while
a "0" causes the Data Direction Register to be addressed.
Interrupt Flags (CRA-6, CRA-7, CRB-6, and CRB-7) The four interrupt flag bits are set by active transitions of
signals on the four Interrupt and Peripheral Control lines
when those lines are programmed to be inputs. These bits
cannot be set directly from the MPU Data Bus and are reset
indirectly by a Read Peripheral Data Operation on the appropriate section.

Don't Care

PORT A-B HARDWARE CHARACTERISTICS

As shown in Figure 17, the MC6821 has a pair of I/O ports
whose characteristics differ greatly. The A side is designed
to drive CMOS logic to normal 30% to 70% levels, and incorporates an internal pullup device that remains connected
even in the input mode. Because of this, the A side requires
more drive current in the input mode than Port B. In contrast, the B side uses a normal three-state NMOS buffer
which cannot pullup to CMOS levels without external
resistors. The B side can drive extra loads such as Darlingtons without problem. When the PIA comes out of reset,
the A port represents inputs with pullup resistors, whereas
the B side (input mode also) will float high or low, depending
upon the load connected to it.

Control of CA2 and CB2 Peripheral Control Lines (CRA-3,
CRA-4, CRA-5, CRB-3, CRB-4, and CRB-5) - Bits 3,4, and
5 of the two control registers are used to control the CA2 and
CB2 Peripheral Control lines. These bits determine if the control lines will be an interrupt input or an output control
signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) is an interrupt
input line similar to CAl (CB1). When CRA-5 (CRB-5) is
high, CA2 (CB2) becomes an output signal that may be used
to control peripheral data transfers. When in the output
mode, CA2 and CB2 have slightly different loading
characteristics.

3-314

MC6821

Control of CAl and CBl Interrupt Input Lines (CRA-O,
CRB-O, CRA-l, and CRB-l1 - The two lowest-order bits of
the control registers are used to control the interrupt input
lines CA 1 and CB 1. Bits CRA-O and CR B-O are used to
FIGURE 17 -

enable the MPU interrupt signals IROA and IROB, respectively. Bits CRA-1 and CRB-1 determine the active transition
of the interrupt input signals CA 1 and CB 1.

PORT A AND PORT B EQUIVALENT CIRCUITS

Port A

Port B

VCC

VCC

Port Pin
Port Pin

Data -------.._ _

I

Direction
(l-+-Output Pin)
(O--lnput Pin)

in Output
Mode

To External

Read of B
Data when
in Input Mode

Read A Data
in Input or
Output Mode
Internal PIA Bus

ORDERING INFORMATION

r

MC68A21CP

--r T ~

Mota.
In.tegra."d Ci,,",,
M6800rala
Family
Blanks= 1.0 MHz
A=1.5MHz
B=2.0 MHz
Device Designation
In M6800 Family
Temperature Range - - - - - - - - - '
Blank = 0°_ + 70°C
C= - 40°- + 85°C
Package
P = Plastic
S = Cerdip
L = Ceraf"1lc
BETTER PROGRAM

Better program process·ing is available on all types listed. Add
suffix letters to part number.
Levell add "S"

Level 2 add "D"

Level 3 add "OS"

Levell "S" = 10 Temp Cycles - (- 25 to 150°C);
Hi Temp testing at T A max
Level 2 "0" = 168 Hour Burn-In at 125°C
Level 3 "OS" = Combination of Levelland 2

3-315

MC6821

FIGURE 18 - CONTR OL WORD FORMAT

Determine Active CA1 (CB1) Transition for Setting
Interrupt Flag IROA(B)1 - Ibit 7)
b1 =0: IROAIB)l set by high-to-Iow transition on CAl
ICB1)
bl =1:

IROAIB)l set by low-to-high transition on CAl
ICBll.

CA1 ICB1) Interrupt Requ est Enable/Disable
bO=O: Disables IROAIB) MPU Interrupt by CAl
(CB1) active transit ion. 1
bO=l: Enable IROA(B) M PU Interrupt by CAl (CB1)
active transition.
1. IROAIB) will occur on ne xt (MPU generated) positive
transition of bO if CAl (CB1) active transition occurred while interrupt wa s disabled.

I
IROAIB) 1 Interrupt Flag (bit 7)
Goes hig h on active transition of CAl (CB1); Automatically cle ared by MPU Read of Output Register A(B).
May also be cleared by hardware Reset.

~

I

----L-

Control Register

IROAIB)2 Interrupt Flag Ibit 6)
When CA2 ICB2) is an input, IROAIB) goes high on active transition CA2 ICB2); Automatically cleared by
MPU Read of Output Register AlB). May also be
cleared by hardware Reset.
CA2 ICB2) Established as Output Ib5= 1): IROAIB)
2= 0, not affected by CA2 ICB2) transitions.

Determines Whether Data Direction Register Or Output
Register is Addressed
b2=0: Data Direction Register selected.
b2 = 1: Output Register selected.

I

I

CA2 ICB2) Established as Output by b5= 1
INote that operation of CA2 and CB2 output
b5 b4 b3
functions are not identical)

CA2 ICB2) Established as Input by b5=O

Q§ .124 b3

--~CA2
1

0

o

b3 = 0:

Read Strobe with CA 1 Restore
CA2 goes low on first high-to-Iow
E transition following an MPU read
of Output Register A; returned high
by next active CAl transition, as
specified by bit 1.
b3 = 1: Read Strobe with E Restore
CA2 goes low on first high-to-Iow
E transition following an MPU read
of Output Register A; returned high
by next high-to-Iow E transition during a deselect.
~CB2
b3=0: Write Strobe with CB1 Restore
CB2 goes low on first low-to-high
E transition following an MPU write
into Output Register B; returned
high by the next active CB 1 transition as specified by bit 1. CRB-b7
must first be cleared by a read of
data.
b3 = 1: Write Strobe with E Restore
CB2 goes low on first low-to-high
E transition following an MPU write
into Output Register B; returned
b5 b4 b3
high by the next low-to-high E transltlon follOWing an E pulse which
occurred while the part was deselected
1 1
Set/Reset CA2 ICB2)
CA2 ICB2) goes low as MPU writes
b3=0 into Control Register.
CA2 ICB2) goes high as MPU writes
b3= 1 into Control Register.

--L

3-316

L

CA2 (CB2) Interrupt Request Enable/Disable
b3=0: Disables IROAIB) MPU Interrupt by
CA2 (CB2) active transition."
b3= 1: Enables IROA(B) MPU Interrupt by
CA2 (CB2) active transition.
"IROAIB) will occur on next (MPU gene ratted) positive transition of b3 if CA2 (CB2)
active transition occurred while interrupt
was disabled.
~Determines Active CA2 (CB2) Transition for
Setting Interrupt Flag IROAIB)2 - IBit bS)
b4=0: IROAIB)2 set by high-to-Iow transition on CA2 (CB2).
b4= 1: IROA(B)2 set by low-to-high transition on CA2 (CB2).

®

MC6822

MOTOROLA
Advance Information

MOS

INDUSTRIAL INTERFACE ADAPTER (IIA)
The MC6822 Industrial Interface Adapter (IIA) provides a universal
means of interfacing peripheral equipment to the M6800 Family of
microprocessors. This device is capable of interfacing the MPU to
peripherals through two 8-bit bidirectional peripheral data buses and
four control lines. No external logic is required for interfacing to most
peripheral devices.
The functional configuration of the IIA is programmed by the MPU
during system initialization. Each of the peripheral data lines can be programmed to act as an input or an output, and each of the four control I
interrupt lines may be programmed for one of several control modes.
This allows a high degree of flexibility in the overall operation of the
interface.
•
•

8-Bit Bidirectional Data Bus for Communication with the MPU
Two Bidirectional 8-Bit Buses for Interface to Peripherals

•
•
•

Two Programmable Control Registers
Two Programmable Data Direction Registers
Four Individually-Controlled Interrupt Input Lines, Two Usable as
Peripheral Control Outputs

•
•
•
•
•

Handshake Control Logic for Input and Output Peripheral Operation
Open-Drain Port Circuits
High Voltage Capability up to 18 Volts
Program Controlled Interrupt and Interrupt Disable Capability
Ports Output Compatible with CMOS at 15 Volts

•
•
•

TTL Compatible
Static Operation
Pin Compatible with MC6821 PIA

Ceramic
L Suffix

Cerdip
S Suffix

Plastic
P Suffix

Frequency
1.0
1.0
1.5
1.5
2.0
2.0

MHz
MHz
MHz
MHz
MHz
MHz

1.0
1.0
1.5
1.5
2.0
2.0

MHz
MHz
MHz
MHz
MHz
MHz

1.0
1.0
1.5
1.5
2.0
2.0

MHz
MHz
MHz
MHz
MHz
MHz

Operating
Temperature
ODC to 70 DC
-40 DC to 85 DC
ODC to 70 DC
- 40 DC to 85 DC
ODC to 70 DC
-40 DC to 85 DC
ODC to 70 DC
- 40DC to 85 DC
ODC to 70 DC
- 40 DC to 85 DC
ODC to 70 DC
- 40DC to 85 DC
ODC to 70 DC
- 40 DC to 85 DC
ODC to 70 DC
- 40DC to 85 DC
ODC to 70 DC
-40 DC to 85 DC

INDUSTRIAL INTERFACE
ADAPTER

I

PIN ASSIGNMENT
VSS

ORDERING INFORMATION

Package Type

IN-CHANNEL, SILICON-GATE
DEPLETION LOAD)

CAl

PAO

CA2

PAl

IROA

PA2

IROB

PA3

RSO

PA4

RSl

Part Number

PA5

RESET

MC6822L
MC6822CL
MC68A22L
MC68A22CL
MC68B22L
MC68B22CL

PA6

DO

PA7

Dl

MC6822S
MC6822CS
MC68A22S
MC68A22CS
MC68B22S
MC68B22CS
MC6822P
MC6822CP
MC68A22P
MC68A22CP
MC68B22P
MC68B22CP

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-317

PBO

02

PBl

03

PB2

04

PB3

05

PB4

06

PB5

07

PB6
PB7

CSl

CBl

CS2

CB2

CSO

VCC

R/W

MC6822

MAXIMUM RATINGS
Symbol

Value

Unit

VCC

-0.3 to 7.0

V

Input Voltage
PAO-PA7, CAl, CA2, PBO-PB7, CB1, CB2
All Others

Yin

-0.3 to 18.0
-0.3 to 7.0

V

Operating Temperature Range
MC6822, MC68A22, MC68B22
MC6822C, MC68A22C, MC68B22C

TA

TL to TH
o to 70
-40 to 85

°c

Tstg

-55 to 150

°c

Symbol

Value

Unit

OJA

50
100
60

°C/W

Characteristic
Supply Voltage

Storage Temperature Range

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage (i.e., either VSS or
VCC)·

THERMAL CHARACTERISTICS
Characteristic

I

Thermal Resistance
Ceramic
Plastic
Cerdip

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in DC can be obtained from:
TJ=TA+(PDeOJA)
Where:
TA==Ambient Temperature, DC
OJA == Package Thermal Resistance, Junction-to-Ambient, DC/W

(1)

PD==PINT+ PPORT
PINT==ICCxVCC, Watts - Chip Internal Power
PPORT == Port Power Dissipation, Watts - User Determined
For most applications PPORT----toII..----. MMD6150
or Equiv.

0

C
130 pF

MMD7000
or Equiv.

FIGURE 4 - PERIPHERAL DATA
SETUP AND HOLD TIMES
(READ MODE)

FIGURE 3 - NMOS EQUIVALENT
TEST LOAD

(IRQ Only)

5.0 V

t
T~"O;"':i

3kO

100pF

I

R

R is such that
1=1.0 mA with
Vtestpoint=OA V

PAO-PA7~
PBO-PB7

~

_
tpDS

Enable

!

Ir--r-_ - - ,

~tPDH

~

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise noted.

3-320

MC6822

FIGURE 5 - CA2 DELAY TIME
(READ MODE: CRA-5= CRA-3= 1,
CRA-4=0)

FIGURE 6 - CA2 DELAY TIME
(READ MODE: CRA-5= 1,
CRA-3 = CRA-4 = 0)
Enable

t_C_A_2~ ~~~-'.-~----

CA1 _________

* Assumes part was deselected durir,g
the previous E pulse.

~

CA2
FIGURE 7 -

PERIPHERAL CMOS DATA
DELAY TIMES
(WRITE MODE: CRA-5 = CRA-3 = 1,
CRA-4=0)

FIGURE 8 - PERIPHERAL DATA AND
CB2 DELAY TIMES
(WRITE MODE: CRB-5= CRB-3= 1,
CRB-4=0)

Enable~

/

_----,k-.t

PBO-PBl

tpDW

~,._ _ _ _ _ __
j...tDC~
~

CB2*
*CB2 goes low as a result of the
positive transition of enable.
FIGURE 9 - CB2 DELAY TIME
(WRITE MODE: CRB-5 = CRB-3 = 1,
CRB-4=0)

FIGURE 10 - CB2 DELAY TIME
(WRITE MODE: CRB-5= 1.
CRB-3= CRB-4=0)

Enable

~tr'tf

CB1----+--C-B-2~-----,~~-/-~---

CB2

CB2

"Assumes part was deselected during the
previous E pulse.

*Assumes part was deselected during
any previous E pulse.
FIGURE 11 - INTERRUPT PULSE WIDTH
AND iRQ RESPONSE

FIGURE 12 -

Enable

IRQ

IRQ RELEASE TIME

--.It

tlR4----J
~I
_ ___

"Assumes interrupt enable bits are set.
FIGURE 13 -

RESET LOW TIME

::---\ r--

RESET

1.;
"-

tRL
~~
____________~~

*The RESET line must be a VIH for a minimum of
1.0 p's before addressing the IIA.
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.

3-321

I

MC6822

FIGURE 14 IROA

EXPANDED BLOCK DIAGRAM

38

Interrupt Status
Control A
'---------'

DO

~40

CAl

~39

CA2

33

D1

32

D2

31

D3

30

D4

29

Data Direction
Register A
(DDRA)

Data Bus
Buffers
(DBB)

05

28

D6

27

~2

PAO

07

26

.......... 3

PAl

.......... 4

PA2

Peripheral
Interface
A

I

............ 5

PA3

6

PA4

9

PA6
PA7

10

PBO

11

PB1

Bus Input
Register
(BIR)

VCC= Pin 20
Vss=Pin 1

CSO

22

CSl

PA5

12

PB2
PB3
PB4

24

13
14

CS2

23

15

PB5

RSO
RSl

36
35

16

PB6

17

PB7

R/W

21

Enable
RESET

34

18

CBl

19

CB2

25
Data Direction
Register B
(DDRB)

Interrupt Status
IROB

Control B
37~---------------------------------------L____________
~

IIA INTERFACE SIGNALS FOR MPU
The IIA interfaces to the M6800 bus with an 8-bit bidirectional data bus, three chip select lines, two register select
lines, two interrupt request lines, a read/write line, an enable
line, and a reset line. To ensure proper operation with the
MC6800, MC6802, or MC6808 microprocessors, VMA
should be used as an active part of the address decoding.
BIDIRECTIONAL DATA (00-07)
The bidirectional data .Iines !D0-D7) allow the transfer of
data between the MPU and the IIA. The data bus output
drivers are three-state devices that remain in the highimpedance (off) state except when the MPU performs an IIA
read operation. The read/write line is in the read (high) state
when the IIA is selected for a read operation.

ENABLE (E)
The enable pulse, E, is the only timing signal that is supplred to the IIA. Timing of all other signals is referenced to
the leading and trailing edges of the E pulse.
READ/WRITE (R/W)
This signal is generated by the MPU to control the direction of data transfers on the data bus. A low state on the IIA
read/write line enables the input buffers and data is transferred from the MPU to the IIA on the E Signal if the device has
been selected. A high on the read/write line sets up the IIA
for a transfer of data to the M PU data bus. The IIA output
buffers are enabled when the proper address and the enable
pulse, E, are present.

3·322

MC6822

RESET (RESET)

setting a one in the corresponding data direction register bit
for those lines which are to be outputs. A zero in a bit of the
data direction register causes the corresponding peripheral
data line to act as an input. During an MPU read peripheral
data operation, the data on peripheral lines programmed to
act as inputs appears directly on the corresponding MPU
data bus lines.
The data in output register A will appear on the data lines
that are programmed to be outputs. A logical one written
into the register will cause the corresponding data line to go
into a high-impedance state, and may be pulled up externally
to a maximum of 18 volts. A logical zero written into the
register results in a low on the corresponding data line. Data
in output register A may be read by an MPU "Read
Peripheral Data A" operation when the corresponding lines
are programmed as outputs. This data will be read properly if
the voltage on the peripheral data lines is greater than 2.0
volts for a logic one output and less than 0.8 volts for a logic
zero output.

The active low RESET line is used to reset all register bits
in the IIA to a logical zero (low). This line can be used as a
power-on reset and as a master reset during system operation.
CHIP SELECTS (CSO, CS1, AND'CS2)

These three input signals are used to select the IIA. CSO
and CS1 must be high and CS2 must be low for selection of
the device. Data transfers are then performed under the control of the enable and read/write Signals. The chip-select
lines must be stable for the duration of the E pulse. The
device is deselected when any of the chip selects are in the
inactive state.
REGISTER SELECTS (RSO AND RS1)
The two register select lines are used to select the various
registers inside the IIA. These two lines are used in conjunction with internal control registers to select a particular
register that is to be written or read.
The register and chip-select lines should be stable for the
duration of the E pulse while in the read or write cycle.

SECTION B PERIPHERAL DATA (PBO-PB7)

The peripheral data lines in the B section of the IIA can be
programmed to act as either inputs or outputs in a manner
similar to PAO-PA7. Data on the peripheral data lines PBOPB7 will be read properly from those lines programmed as
outputs even if the voltages are below 2.0 volts for a "high"
or above 0.8 volts for a "low."

INTERRUPT REOUEST (lROA AND IROB)

The active low interrupt request lines (fRQA and IROB) act
to interrupt the M PU either directly or through interrupt
priority circuitry. These lines are "open drain" (no load
device on the chip). This permits all interrupt request lines to
be tied together in a wire-OR configuration.
Each interrupt request line has two internal interrupt flag
bits that can cause the interrupt request line to go low. Each
flag bit is associated with a particular peripheral interrupt
line. Also, four interrupt enable bits are provided in the IIA
which may be used to inhibit a particular interrupt from a
peripheral device.
Servicing an interrupt by the MPU may be accomplished
by a software routine that, on a prioritized basis, sequentially
reads and tests the two control registers in each IIA for interrupt flag bits that are set.
The interrupt flags are cleared (zeroed) as a result of an
MPU read peripheral data operation of the corresponding
data register. After being cleared, the interrupt flag bit cannot be enabled to be set until the IIA is deselected during an
E pulse. The E pulse is used to condition the interrupt control
lines (CAl, CA2, CB1, CB2). When these lines are used as
interrupt inputs, at least one E pulse must occur from the inactive edge to the active edge of the interrupt input signal to
condition the edge sense network. If the interrupt flag has
been enabled and the edge sense circuit has been properly
conditioned, the interrupt flag will be set on the next active
transition of the interrupt input pin.

INTERRUPT INPUT (CAl AND CB1)

Peripheral input lines CAl and CBl are input-only lines
that set the interrupt flags of the control registers. The active
transition for these signals is also programmed by the two
control registers.
PERIPHERAL CONTROL (CA2)

The peripheral coritrolline CA2 can be programmed to act
as an interrupt input or as an open-drain output. The function of this signal line is programmed with control register A.
PERIPHERAL CONTROL (CB2)

Peripheral control line CB2 may also be programmed to act
as an interrupt input or peripheral control output. As an
input, this line has high input impedance and is compatible
with standard TTL. This line is programmed by control
register B.

INTERNAL CONTROLS
INITIALIZATION
A RESET has the effect of zeroing all IIA registers. This
will set PAO-PA7, PBO-PB7, CA2, and CB2 as inputs, and
disable all interrupts. The IIA must be configured during the
restart program which follows the reset.
There are six locations within the IIA accessible to the
MPU data bus: two peripheral registers, two data direction
registers, and two control registers. Selection of these locations is controlled by the RSO and RSl inputs together with
bit 2 in the control registers, as shown in Table 1.

IIA PERIPHERAL INTERFACE LINES
The IIA provides two 8-bit bidirectional data buses and
four interrupt control lines for interfacing to peripheral
devices.
SECTION A PERIPHERAL DATA (PAO-PA7)

Each of the peripheral data lines can be programmed to act
as an input or an open-drain output. This is accomplished by

3-323

I

MC6822

TABLE 1 - INTERNAL ADDRESSING

RSl
0
0
0
1
1
1

Control Register Bit
RSO CRA-2
CRB-2
1
X
0
0
0
X
1
X
X
0
X
1
0
X
0
1
X
X

DATA DIRECTION ACCESS CONTROL BIT
(CRA-2 AND CRB-21
Bit 2 of each control register (CRA and CRB) determines
selection of either a peripheral output register or the corresponding data direction registers when the proper register
select signals are applied to RSO and RS1. A one in bit 2
allows access of the peripheral data register, while a zero
causes the data direction register to be addressed.

Location Selected
Peripheral Register A
Data Direction Register A
Control Register A
Peripheral Register B
Data Direction Register B
Control Register B

CONTROL OF CA2. AND CB2 PERIPHERAL CONTROL
L1N~S (CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, AND
CRB-51
Bits 3, 4, and 5 of the two control registers are used to
control the CA2 and CB2 peripheral control lines. These bits
determine if the control lines will be an interrupt input or an
output control signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2)
is an interrupt input line similar to CAl (CB1). When CRA-5
(CRB-5) is high, CA2 (CB2) becomes an output signal that
may be used to control peripheral data transfers. When in
the output mode, CA2 and CB2 have slightly different
loading characteristics.

X= Don't Care

Details of possible configurations of the data direction and
control register are given in the following paragraphs.

I

PORT A-B HARDWARE CHARACTERISTICS
As shown in Figure 15, the MC6822 has a pair of I/O ports
whose characteristics differ slightly.
Notice the differences between a port A and port Bread
operation when in the output mode. When reading port A,
the actual pin is read, whereas the B side read comes from an
output latch, ahead of the actual pin.

CONTROL OF CAl AND CBl INTERRUPT INPUT LINES
(CRA-O, CRA-l, CRB-O, AND CRB-ll
The two lowest-order bits of the control registers are used
to control the interrupt input lines CA 1 and CB 1. Bits CRA-O
and CRB-O are used to enable the MPU interrupt Signals
IROA and IROB, respectively. Bits CRA-1 and CRB-l determine the active transition of the interrupt input Signals CAl
and CB1.

CONTROL REGISTERS (CRA AND CRBI
The two control registers (CRA and CRB) allow the MPU
to control the operation of the four peripheral control lines
CAl, CA2, CB1, and CB2. In addition, they allow the MPU
to enable the interrupt lines and monitor the status of the
interrupt flags. Bits 0 through 5 of the two registers may be
written or read by the MPU when the proper chip select and
register select signals are applied. Bits 6 and 7 of the two
registers are read only and are modified by external interrupts
occurring on control lines CA 1, CA2, CB1, or CB2. The format of the control words is shown in Figure 16.

INTERRUPT FLAGS (CRA-6, CRA-7, CRB-6, AND CRB-71
The four interrupt flag bits are set by active transitions of
signals on the four interrupt and peripheral control lines
when those lines are programmed to be inputs. These bits
cannot be set directly from the MPU data bus and are reset
indirectly by a read peripheral data operation on the appropriate section.

FIGURE 15 - PORT A AND PORT B EQUIVALENT CIRCUITS
Port B

Port A

DATA

Port Pin*
Port Pin*

Data----" _~
Direction
(l--.0utput Pin)
(O--'Input Pin)

in Output
Mode

To External

Read of B
Data when
in Input Mode

Read A Data
in Input or
Output Mode

Internal IIA Bus
*Port pins are open drain and must be pulled up externally.

3-324

MC6822

FIGURE 16 -

Determine Active CAl (CB1) Transition for Setting
Interrupt Flag IROA(B)l - (bit 7)
bl =0: IRGA(B)l set by high-to-Iow transition on CAl
ICB1)
bl=l: IRGAIB)l set by low-to-high transition on CAl
ICBll.

CONTR OL WORD FORMAT

CAl (CB1) Interrupt Requ est Enable/Disable
Disables IRGAIB) MPU interrupt by CAl ICB1)
active transition. l
bO= 1: Enable IRGAIB) M PU interrupt by CAl ICB1)
active transition.
1. IRGAIB) will occur on ne xt IMPU generated) positive
transition of bO if CA 1 ICB1) active transition occurred while interrupt wa s disabled.

bO=O:

t
IROA(B) 1 Interrupt Flag (bit 7)
Goes hig h on active transition of CAli CB 1); automatically cleared by MPU read of output register AlB).
May also be cleared by hardware reset.

~

----L-

Control Register

I

IROA(B)2 Interrupt Flag (bit 6)
When CA2 ICB2) is an input, IRGA(B) goes high on active transition CA2 I CB2); automatically cleared by
MPU read of output register AlB). May also be cleared
by hardware reset.
CA2 ICB2) Established as output Ib5= 1): IRGAIB)
2 = 0, not affected by CA2 I CB2) transitions.

Determines Whether Data Direction Register Or Output
Register is Addressed
b2= 0: Data direction register selected.
b2 = 1: Output register selected.

I

I
CA2 (CB2) Established as Input by b5=O

CA2 (CB2) Established as Output by b5= 1
INote that operation of CA2 and CB2 output
functions are not identical)
~~ b3
~CA2
1

0

b3 = 0:

Read Strobe with CAl Restore
CA2 goes low on first high-to-Iow E
transition following an MPU read of
output register A; returned high by
next active CAl transition, as
specified by bit 1.

b3 = 1:

Read Strobe with E Restore
CA2 goes low on first high-to-Iow E
transition following an MPU read of
output register A; returned high by
next high-to-Iow E transition during
a deselect.

~CB2
b3= 0:

b3 = 1:

--L
b5 b4 b3

1

1

Q§

o

1.>4

b3

L

CA2 (CB2) Interrupt Request Enable/Disable
b3=0: Disables IRGAIB) MPU Interrupt by
CA2 ICB2) active transition.*
b3= 1: Enables IRGAIB) MPU Interrupt by
CA2 ICB2) active transition.

*IRGA(B) will occur on next IMPU generatted) positive transition of b3 if CA2 ICB2)
active transition occurred while interrupt
was disabled.
~Determines Active CA2 (CB2) Transition for
Setting Interrupt Flag IROA(B)2 - (Bit b6)
b4=O: IRGAIB)2 set by high-to-Iow transition on CA2 ICB2)'

Write Strobe with CBl Restore
CB2 goes low on first low-to-high E
transition following an MPU write
into output register B; returned high
by the next active CBl transition as
specified by bit 1. CRB-b7 must first
be cleared by a read of data.
Write Strobe with E Restore
CB2 goes low on first low-to-high E
transition following an MPU write
into output register B; returned high
by the next low-to-high E transition
following an E pulse which occurred
while the part was deselected

b4= 1:

Set/Reset CA2 (CB2)
CA2 ICB2) goes low as MPU writes
b3 = 0 into control register.
CA2 ICB2) goes high as MPU writes
b3= 1 into control register.

3-325

IRGAIB)2 set by low-to-high transition on CA2 ICB2)'

I

®

MOTOROLA

MC6829

Advance InforIllation
HMOS

MEMORY MANAGEMENT UNIT

I

(HIGH DENSITY N-CHANNEL, SILICON-GATE)

The principle function of the MC6829 Memory Management Unit
(MMU) is to expand the address space of the MC6809 from 64K bytes to
a maximum of 2 Megabytes. Each MMU is capable of handling four different concurrent tasks including DMA. The MMU can also protect the
address space of one task from modification by another task. Memory
address space expansion is accomplished by applying the upper five address lines of the processor (A 11-A 15) along with the contents of a 5-bit
task register to an internal high-speed mapping RAM. The MMU output
consists of ten physical address lines (PA 11-PA20l which, when combined with the eleven lower address lines of the processor (AO-A 10),
forms a physical address space of 2 Megabytes. Each task is assigned
memory in increments of 2K bytes up to a total of 64K bytes. In this
manner, the address spaces of different tasks can be kept separate from
one another. The resulting simplification of the address space programming model will increase the software reliability of a complex multiprocess system.
• Expands Memory Address Space from 64K to 2 Megabytes
• Each MMU is Capable of Handling Four Separate Tasks
• Up to Eight MMUs can be Used in a System
• Provides Task Isolation and Write Protection
• Provides Efficient Memory Allocation; 1024 Pages of 2K Bytes Each
• Designed for Efficient Use with DMA
• Fast, Automatic On-Chip Task Switching
• Allows Inter-Process Communication Through Shared Resources

MEMORY MANAGEMENT UNIT
(MMU)

~

[!!

~
~

LSUFFIX
CERAMIC PACKAGE
CASE 715

SSUFFIX
CERDIP PACKAGE
CASE 734

'I

~
" " "i

.

.

• Simplifies Programming Model of Address Space
• Increases System Software Reliability

P SUFFIX

PLASTIC PACKAGE
CASE 711

PIN ASSIGNMENT
VSS

• MC6809/MC6800 Bus Compatible
• Single 5-VoltPower Supply

PAll

A15

PA12

A14

PA13

A12

PA15

All

PA16

BLOCK DIAGRAM

PA14

Mapping RAM
Task 0 Registers
Task 1 Registers

All-A15

PAll-PA20

RA

PA17

RS6

PA18

RS5
RS4

II)

~

PA19

10

31

PA20

SA

RS3

SS

RS2

RESET

RSl

05

RSO

04

07
12

KVA
Q

06

03
16

02
01

BA

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-326

DO

BS

19

Vee

RESET

20

R/W

MC6829

MAXIMUM RATINGS
Symbol

Value

Unit

Vcc
Yin

-0.3 to +7.0
-0.3 to + 7.0

V
V

Operating Temperature Range
MC6829, MC68A29, MC68B29
MC6829C, MC68A29C, MC68B29C

TA

TL to TH
o to 70
-40 to +85

°c

Storage Temperature Range

Tsta

- 55 to + 150

°c

Symbol

Value

Rating

Characteristics
Supply Voltage
Input Voltage

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either
VSS or VCC!.

THERMAL CHARACTERISTICS
Thermal Resistance
Plastic
Cerdip
Ceramic

(JJA

100

60

°C/W

50

I

POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °c can be obtained from:
(11

TJ=TA+(PO-8JAI
Where:
T A E Ambient Temperature, °C
8JAE Package Th'ermal Resistance, Junction-to-Ambient, °C/W

POE PINT+ PPORT
PINTE ICC x VCe. Watts - Chip Internal Power
PPORT!= Port Power Oissipation, Watts - User Oetermined
For most applications PPORT
~
w

-

Ea
R/Wa
RSa

Address
Decode

-"

-

~

[\----

IV'

•

M
r----v

----

;t-

\r-

Semaphore
Register

-

-

r--

n
~

r-----

r---

~

,....--Address
Decode

""'-

~

~

w
0

"---

MCM68HC34

SIGNAL DESCRIPTION

TABLE 2 -

The following paragraphs contain a brief description of
the input and output signals.
VCC AND VSS
These pins supply power to the DPM. Vee is + 5 volts
and VSS is 0 volts or ground.

± 5%

E CLOCK INPUTS (Ea AND Eb)
These are the input clocks from the respective processors
and are positive during the latter portion of the bus cycle.
REGISTER SELECT INPUTS (RSa AND RSb)
These inputs function as register select inputs. A high on
the RSa for side A or RSb for side B input allows selection of
the semaphore and interrupt registers respectively for side A
and side B by the lower three address bits. A low on RSa or
RSb selects 256 bytes of RAM from side A or side B respectively.
CHIP SELECT INPUTS (CS1a AND CS1b)
These inputs function as chip select inputs for their
respective sides. eSla must be low...!£... select side A and
eSlb must be low to select side B. If eSla is high, side A is
deselected. If eSlb is high, Side B is deselected.
MODE SELECT (MODE)
In normal operation, this pin should always be connected
to Vee (MODE= 1l. Each side has three states controlled by
RSa and eSla for side A and RSb and eSlb for side B.
If eSla is high, side A cannot be accessed. If eSla is low,
side A accesses either 256 bytes of RAM or the six
semaphore registers and the two interrupt registers depending on the level of RSa. If RSa is low, 256 bytes of RAM are
accessed and if RSa is high, the six semaphores and two interrupt registers are accessed.
The six semaphore and two interrupt registers are redundantly mapped in the 256 byte mode. That is, only the low
order three bits select one of eight registers and the upper
five bits of address are not decoded. Refer to Table 1.

SIDE B CONTROL SIGNAL OPERATION
Operation

Mode

CSlb

RSb

1

0
1

Access 256 Byte RAM Side B

1

0
0

1

1

X

Side B Not Selected

Access Semaphore! I RQ Side B
on Lower Three Bits of Address

INTERRUPT REQUEST OUTPUTS (lROa AND IRQb)
These pins are active low open-drain outputs. A write to
address F9 from one side asserts an interrupt, if not masked.
On the other side, a write to address F9 sets this pin low.
B SIDE ADDRESS BUS INPUTS (AO-All AND
B SIDE BIDIRECTIONAL DATA BUS (OO-D7)
When the B side is run from a multiplexed bus processor,
the B side address pins are connected to the B side data
pins, respectively (AO to DO, Al to D1, etc.).
SYSTEM RESET INPUT (RESET)
A low level on this input causes the semaphore registers to
be set to the states shown in Table 5 under SEMAPHORE
REGISTERS and clears both bits of both IRQ registers to
zeros. The RAM data is unaffected by RESET.
ADDRESS STROBE INPUTS (ASa AND ASb)
The ASa input demultiplexes the eight low order address
lines from the data lines on the A side The falling edge of
ASa latches the A side address within the DPM. The ASb input is used in the same manner when the B side is connected
to a multiplexed bus. It must be connected to a high level
when the B side is connected to a non-multiplexed bus.
A SIDE MULTIPLEXED ADDRESS/
BIDIRECTIONAL DATA BUS (ADO-AD7)
The A side can only be used with a multiplexed address/ data bus. The A side addresses are on these lines during the time ASa is high. The lines are used as bidirectional
data lines during the time Ea is high.

DUAL-PORT RAM
TABLE 1 -

SIDE A CONTROL SIGNAL OPERATION

Mode

CSla

RSa

1

0
1

Access 256 Byte RAM Side A

1

0
0

Operation

1

1

X

Side A Not Selected

Access Semaphore! iRQ Side A
on Lower Three Bits of Address

The three states for side B in the 256 byte mode are controlled in the manner as side A using RSb and eSlb except
that side Buses sep'arated address and data inputs. Refer to
Table 2.

The dual-port memory unit contains 256 bytes of dual-port
RAM that is accessed from either processor. It is selected in
either case by eight address lines, register select, and chip
select inputs. The direction of data transfer is controlled by
the respective read/write (R/VVa or R/Wb) line. The dualport RAM enables the processors to exchange data without
interfering with devices on the other bus.
Simultaneous accesses by both sides of different locations
of dual-port RAM will cause no ambiguities. Simultaneous
reads by both sides of the same dual-port RAM location
gives the proper data to both sides. On a simultaneous write
and read of the same location, the data written is put into
RAM but the data read is undefined. Simultaneous writes to

3-347

I

MCM68HC34

the same RAM location result in undefined data being
stored. Thus, simultaneous writes and simultaneous write
and read to the same location should be avoided. The
semaphore registers provide a tool for determining when the
shared RAM is available.

except the second' semaphore register which is owned by the
B processor.
TABLE 5 - RESET STATE OF SEMAPHORE REGISTERS
Semaphore
Register
Number

SEMAPHORE REGISTERS

1
2

I

The dual-port memory unit contains six read/write
semaphore registers. Only two bits of each register are used
Bit 7 is the semaphore (SEM) bit and bit 6 is the ownership
(OWN) bit. The remaining six bits will read all zeros.
Each semaphore register is able to arbitrate simultaneous
accesses to it. The semaphore register bits provide a
mechanism for controlling accesses to the shared RAM but
there are no hardware controls of the dual-port RAM by the
semaphore registers.
Table 3 is the truth table for when a semaphore register is
accessed by one of the processors. When a semaphore
register is written, the actual data written is disregarded but
the SEM bit is set to zero. When the register is read, the
resulting SEM bit is one (for the next read). The data obtained from the read is interpreted as: SEM bit equals
zero - resource available, SEM bit equals one - resource
not available.

3
4

5
6

A Processor
SEM Bit
OWN Bit
1
1
1
0
1
1
1
1
1
1
1
1

B Processor
SEM Bit
OWN Bit
1
0
1
1
1
0
1
0
1
0
1
0

A state diagram for a semaphore register is shown in
Figure 3.
FIGURE 3 - STATE DIAGRAM FOR SEMAPHORE REGISTER

A Reads 0, 1

TABLE 3 - ONE PROCESSOR SEMAPHORE BIT TRUTH TABLE
Original
SEM Bit

Data
Read
0*
1*

R/W

R
R

0
1
0
1

W
W

Resulting
SEM Bit
1
1
0
0

-

* 0= Resource
1=

Available
Resource Not Available

Table 4 shows the truth table if both processors read or
read and write the same semaphore register at the same
time. The A processor always reads the actual SEM bit. The
B processor reads the SEM bit except during the
simultaneous read of a clear SEM bit. This insures that
during a simultaneous read, only the A processor reads a
clear S EM bit and therefore has priority to the shared RAM.

B Writes
I
I

TABLE 4 - SIMULTANEOUS ACCESS OF OF SEMAPHORE
REGISTER TRUTH TABLE
Original
SEM Bit
0
1
1
1

A Processor
R/W Data Read
R
R

0:
1

W

-

R

1*

B Processor
R/W Data Read
1*
R

W

-

R
R

1*
1*

I

I

I
I

Resulting
SEM Bit

Available

1
0
0
1

In Use

NOTES:
1. Writes to a semaphore register are valid only if SEM = 1
and OWN=1.
2. When A and B simultaneously read a semaphore register,
the hardware handles it as a read by A followed by a read
by B.

*0= Resource Available

1 = Resource Not Available
The ownership bit is a read-only bit that indicates which
processor last set the SEM bit. The OWN bit is set to a one
whenever the SEM bit is set from zero to one. The OWN bit
as read by one processor is the complement of the bit read
by the other processor.
The reset state of the semaphore registers is defined In
Table 5. The A processor owns all of the semaphore registers

I
I

INTERRUPT REGISTERS
The dual-port memory unit contains two addressable
locations at F8 and F9 on both sides that control the interrupt
(IRQ) operation between the processors. Although there is
only one hardware register for each side, for purposes of
explanation the register accessed at location F8 is referred to

3-348

MCM68HC34

as the IROX status register and the register accessed at
location F9 is referred to as the IROX control register (refer to
Table 6). The registers each consisting of two bits have
identical bit arrangements. Bit 6 is the enable bit and bit 7 is
the flag bit. The other six bits are not used and always read
as zero. When RESET is asserted, both bits are cleared to
zero.
Table 7 summarizes the bits involved when reading or
writing to the status or control registers at F8 or F9. The
enable bits on either side (A or B) track the data that is
written into the status register from that side. Writes to the
control register do not alter data. The actual data written is
disregarded but the action sets the flag bit in the other side's
register and asserts an interrupt signal if enabled.
The following describes how the B .side interrupt is
asserted from the A side. The A side interrupt is controlled in
a similar manner.
When the enable bit in the IROb status register is set (bit
6 = 1), a write to I ROa control register sets the flag bit in the
IROb status register (bit 7 = 1) and causes an interrupt on the
B side by setting the IROb pin low. Reading the IROb status

register reads the state of the B side enable and flag bits.
Reading the I ROb control register also reads the enable and
flag bits but in addition, clears the B side flag bit (bit 7 = 0)
and clears the B side interrupt by removing the low condition
on the IROb pin.
The enable bit in the IROb status register (bit 6) is changed
by writing the proper data to bit 6 of the IROb status register.
If the B side enable bit is zero, interrupts are prevented on
the B side. However, a write to the IROa control register still
sets the B side flag bit.

INTERNAL REGISTER ADDRESSES
Table 8 shows the address of the RAM, TRQ, and
semaphore registers. The addresses to these registers are the
same whether accessed from the A or B side. The address
and data buses are multiplexed on the A side. The B side has
separate address and data buses. The B side can be used on
a multiplexed bus by connecting the corresponding address
and data bit pins together (AO to DO, A 1 to D1, etc.) and
using the B side address strobe input pin.

TABLE 6 Location
A
A
B
B

Side
Side
Side
Side

FS
F9
FS
F9

IRQ REGISTERS

Register Name

Bit 7

Bit 6

IRQa Status
IRQa Control
IRQb Status
IRQb Control

Flag
Flag
Flag
Flag

Enable
Enable
Enable
Enable

TABLE 7 -

Bits 5 to 0
Used
Used
Used
Used

INTERRUPT OPERATION
Action Taken

Operation
A
A
A
A

Not
Not
Not
Not

Reads IRQa Status at FS
Writes IRQa Status at FS
Reads IRQa Control at F9
Writes IRQa Control at F9

Read EA and FA
Writes to EA
Read EA and FA; Clear FA
Set FB; Assert IRQB if Enabled

BReads IRQb Status at FS
B Writes IRQb Status at FS
B Reads I Rb Control at F9
B Writes IRQb Control at F9

Read EB and FB
Writes to EB
Read EB and FB; Clear FB
Set FA; Assert IRQA if Enabled

FS and F9 are Address Locations
EA and FA are A Side Enable and Flag Bits
EB and FB are B Side Enable and Flag Bits

TABLE 8 -

REGISTER LOCATIONS

RS

Address

Register Name

0
1
1
1
1

OO-FF
00-07
OS-OF
10-17
lS-lF

Dual Ported RAM
IRQ and Semaphore
IRQ and Semaphore
IRQ and Semaphore
IRQ and Semaphore

1
1
1
1
1

··
·

EO-E7
ES-EF
FO-F7
FS-FF

IRQ and Semaphore
IRQ
IRQ
IRQ
IRQ

and
and
and
and

Semaphore
Semaphore
Semaphore
Semaphore

3-349

Where:
X is 0 through F of the upper four bits
of the address (note that only the lower
three bits of the address are decoded):
XO and XS IRQa or IRQb Status
Xl and X9 IRQa or IRQb Control
X2 and XA Semaphore 1
X3 and XB Semaphore 2
X4 and XC Semaphore 3
X5 and XD Semaphore 4
X6 and XE Semaphore 5
X7 and XF Semaphore 6

I

®

MC6835

ItIIOTOROLA

Advance Information
MOS
(HIGH-DENSITY, N-CHANNEL,
SILICON-GATE DEPLETION LOAD)

CRT CONTROLLER (CRTC)

I

MASK PROGRAMMED
CRT CONTROLLER
(CRTC)

The MC6835 is a ROM based CRT Controller which interfaces an
MPU system to a raster scan CRT display. It is intended for use in MPU
based controllers for CRT terminals in stand-alone or cluster configurations. The MC6835 supports two selectable mask programmed screen
formats using the program select input (PROG).
The CRTC is optimized for the hardware/software balance required
for maximum flexibility. All keyboard functions, reads, writes, cursor
movements, scrolling, and editing are under processor control. The
mask programmed registers of the CRTC are programmed to control
the video format and timing.

'

.. '

'

.,.'

In ~f!·

lSUFFIX

CERAMIC PACKAGE

~

• Cost Effective ROM Based CRTC Which Supports Two Screen
Formats
• Useful in Monochrome or Color CRT Applications
• Applications Include "Glass-Teletype," Smart, Programmable, Intelligent CRT Terminals; Video Games; Information Displays

•

I

• Alphanumeric, Semigraphic, and Full Graphic Capability
• Timing May Be Generated for Almost Any Alphanumeric Screen
Format, e.g., 80x24, 72x64, 132x20
•
•
•
•

~

,

/

(I'; ( • .

CERDIP PACK,AGE
CASE 734

,

';

~
~,

Single + 5 Volt Supply
M6800 Compatible Bus Interface
TTL-Compatible Inputs and Outputs
Start Address Register Provides Hardware Scroll (By Page, Line, or
Character)

sC:~~:,:

I

~

, ., ' I '

P SUFFIX

... PLASTIC PACKAGE

• Programmable Cursor Register Allows Control of Cursor Position
• Refresh (Screen) Memory May Be Multiplexed Between the CRTC
and the MPU Thus Removing the Requirements for Line Buffers or
External DMA Devices
• Mask Prbgrammable Interlace or Non-Interlace Scan Modes
• 14-Bit Refresh Address Allows Up to 16K of Refresh Memory
for Use in Character or Semigraphic Displays

CASE 711

PIN ASSIGNMENT
VS

HS

RESET
PROG

RAO
RA1

• 5-Bit Row Address Allows up to 32 Scan-Line Character Blocks
• By Utilizing Both the Refresh Addresses and the Row Addresses,
a 512K Address Space is Available for Use in Graphics Systems
• Refresh Addresses are Provided During Retrace, Allowing the CRTC
to provide Row Addresses to Refresh Dynamic RAMs
• Pin Compatible with the MC6845. The MC6845 May Be Used as a
Prototype Part to Emulate the MC6835.

MA1

RA2

MA2

RA3
RA4

MA4

33

DO

MA5

32

01

MA6

31

02

MA7

30

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage

Value

Unit

MAg

28

05

+ 7.0
-0.3 to + 7.0

V

MA10

'27

06

V

MA11

07

MA12

CS

Symbol
VCC"
Vin"

03
04

MA8

-0.3 to

Operating Temperature Range
MC6835, MC68A35, MC68B35
MC6835C, MC68A35C, MC68B35C

TA

to + 70
-50 to + 85

°c

Storage Temperature Range

Tstg

-55 to

+ 150

°c

o

MA13

24

RS

21

ClK

OE
CURSOR

"With respect to GNO (VSSl.
VCC

This document contains information on a new product Specifications and Information herein
are subject to change without notice.

MC6835

FIGURE 1 - TYPICAL CRT CONTROLLER APPLICATION
r--.-----------~~------------------------------------~AB

...... DB

L--_ _ _-..Jt--+----~~-+-----------------.,....--

Primary Bus

Cursor,
Display
Enable

I
HS

VS

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Cerdip
Ceramic

Symbol

Rating

Value

100

9JA

°C/W

60
50

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage

Characteristic

VCC
VIL

5.25
0.8

Input High Voltage

VIH

5.0
-

V

Input Low Voltage

4.75
-0.3
2.0

VCC

V

V

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS( s Yin or Vout) S VCC.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., either VSS or VCC)·

POWER CONSIDERATIONS
The average chip-junction temperature, T j, in °C can be obtained from:

(1)

Tj=TA+(PO-OjA)
Where:
TA=Ambient Temperature, °C
OjA= Package Thermal Resistance, junction-to-Ambient, °C/W

PO= PINT+ PPORT
PINT= ICC x VCe. Watts - Chip Internal Power
PPORT= Port Power ~issipation, Watts - User Determined
For most applications PPORT .0

"6

}Line

(J)

'>"0

~

A B= C

Display Period

E

1L
::J

L:

Vertical Retrace Period

Total Scan Line Adjust (Nadj)

NOTE1: Timing values are described in Table 8.

3-359

I

..
3:
n
0)
00

w

en

FIGURE 11 - CRTC HORIZONTAL TIMING
Horizontal Total (ROI
1"'~~----------------tSI= (Nht+ 11x tc
HOrizontal Display (R11N hd x tc

~tc
1

ClK,

I

~

II
0)
o

MAO-MA13'~

0

i
1

Ch",,'" ,

III(
HSYNCI

I,

r
1

,

I

,

I

I

I

I

_ I

~

*=i~:fhd 1. Nhd

1

,

I

I

j

I

1

I

2

I

I

: i ~ IN",

r

101(
Dispen I

1

Horizontal Sync Position (R21
""

I

* *

'I

:

h
'I

I

~

,

f
I

hSP

I

1

-, NhSP,

I

1

r

I

~

i ~ i"h"r'"j i ~ I
I

.

I

I

I

,

I
..

I

,Nht.

I

I

I~ :

I

Nh, ~

_ HS Pulse Wldth~

~

I

~

'\.

""'

"'-

* Timing is shown for first displayed scan row only. See Chart in Figure 15 for other rows. The initial MA is determined by the contents of Start
Address Register, R12/R13. Timing is shown for R12/R13=O.
NOTE 1: Timing values are described in Table 5.

I

~,

~Front Porch (Sync Delay)~Nhswxtc ~.aack P~h (Scan Delay~

-~

I

HOrizontal Retrace

~~~"'l--Jt-Il

* *I ,
I

0

I

-III(

'
j

s:

n
0)
01)

W
U1
FIGURE 12 -

RAO-RA4

I

)

is Interlace
Sync and
Video Mode
Odd Field
MAO-MA13"

* * ._, ..

I

I

..'"

I

I

..~
I
...
I
'--I----oTf)j-..---1 Nsf

.

~,. II
I
I

VSYNC

a>
~

Ii

I

I

i
I
I Nvd-1

I

I '

I

I

~_----'r--_-+I'_ _--i-_ _ Vertical

Sync
P?sltlon IR7)

VSYNC

Display
Enable

:x ...

1NI-1)1

1Nsl-1l

FldAd

T

1

~

I

Nvsp 1 I
Vertical
Sync Delay
I
_,

Nvsp

::

1

~16xtSI~

Nvt

Nvt+ 1

Vertical Scan Delay
Vertical Sync
Pulse
...

I

I

I
.
."
i
~
I
..
. ..
,
. . . ,I
~~------~~-----------------------------------i
,
1
~1~~!§!1

(Even Field)
VSYNC
(Odd Field)

...---x= __

~Q~~*=~~~~~~~=*I5d~V~~~:h~(S~~I~2ZZZZZsZZ~22222222A~d~dr~e~ss~c~o~n~tln~u~e~s~to~l~n~cr~em~e~n~t~~~~~~IZZZZZZlezzziluzsztZI2m~e~

~

INvd-1)xNhd+Nht

W

ji

.1

Vertical Retrace

I
..
I
~'_::I __ ~~ __
~v ~
II-V-~I-O-,-1 ----I.----V-i~-,.
Nsl
j...QlJlTadj=NadjX.tSI-+

IINd-1lxNdIINe-1l

Character
Row #

U)

CRTC VERTICAL TIMING

tF= IN vt + 1) x trc+ NadJx tsl
Field Time
~------------------Vertlcal Total IR4) + Vertical Total Adjust (R5)
Vertical Display = Nvd x trclR6)
_1111(
I~
~I
trc..
r-TSI'?"J

I

1

I

I

I

I

1

•

I

1 2

I

..

I

I... I "
1
1
I

2

...._______________---:
'"

~~~~----~~~~--~.~~------------~

'Nht must be an odd number for both interlace modes.
"Initial MA is determined by R12/R13 (Start Address Register), which is zero in this timing example.
"'Nsl must be an odd nU:llber for Interlace Sync and Video Mode.
NOTES:
1. Refer to Figure 6 - The Odd Field is offset Y, horizontal scan time.
2. Timing values are described in Table 5.

III

MC6835

TABLE 2 -

Bit 1

Bit 0

0
1

0
0

0

1

1

1

INTERLACE MODE REGISTER

TABLE 3 -

Bit 5

Normal Sync Mode (Non-Interlace)

0
0

0

Non-Blink

1

Cursor Non-Display

Interlace Sync Mode

1

0

Blink, 1116 Field Rate

Interlace Sync and Video Mode

1

1

Blink, 1/32 Field Rate

FIGURE 13 -

Scan Line Address

0-------------------- - - -0

I

0

0

1

0

0

2

0

0

3

0

0 0 0
0
0

0

0

Cursor Display Mode

INTERLACE CONTROL

Scan Line Address

0

0 0
0

CURSOR START REGISTER

Bit 6

Mode

o
&-1

0
-9
0

~

-&0

Scan Line Address

0-------------------1
2-

3 - -3

-9

---9
00000
-9
- &
6
0
0

-3

4

-2

(':I

-&

--a

-5
-7

0-------------------

--1

--3

-- -5
- - -7
Even
Field

a) Normal Sync

Odd
Field
b) Interlace Sync

Vertical Total Register (R4) and Vertical Total Adjust
Register (R5) - The frequency of VS is determined by both
R4 and R5. The calculated number of character line times is
usually an integer plus a fraction to get exactly a 50 or 60 Hz
vertical refresh rate. The integer number of character line
times minus one is programmed in the 7-bit Vertical Total
Register (R4l. The fraction of character line times is programmed in the 5-bit Vertical Total Adjust Register (R5) as a
number of scan line times.

Odd
Field

Even
Field
c) Interlace Sync and Video

Table 4 describes operation of the Cursor and DE skew
bits. Cursor skew is controlled by bits 6 and 7 of R8 while DE
skew is controlled by bits 4 and 5.
In the normal sync mode (non-interlace) only one field is
available as shown in Figure 5 and 13a. Each scan line is
refreshed at the VS frequency (e.g., 50 or 60 Hzl.
Two interlace modes are available as shown in Figures 6,
13b, and 13c. The frame time is divided between even and
odd alternating fields. The horizontal and vertical timing relationship (VS delayed by 112 scan line time) results in the
displacement of scan lines in the odd field with respect to the
even field.
In the Interlace Sync mode the same information is painted
in both fields as shown in Figure 13b. This is a useful mode
for filling in a character to enhance readability.
In the Interlace Sync and Video mode alternating lines of
the character are displayed in the even field and the odd
field. This effectively doubles the number of characters that
may be displayed on a CRT monitor of a given bandwidth.
Care must be taken when using either interlace mode to
avoid an apparent flicker effect. This flicker effect is due to
the doubling of the refresh period for all scan lines since each
field is displayed alternately. Flicker may be minimized with
proper monitor design (e.g., longer persistence phosphorsl.
In addition, there are restrictions on the programming of
the CRTC registers for interlace operation:

Vertical Displayed Register (R6) - This 7-bit register
specifies the number of displayed character rows on the CRT
screen, and is programmed in character row times. Any
number smaller than the contents of R4 may be programmed
into R6.
Vertical Sync Position (R7) - This 7-bit register controls
the position of vertical sync with respect to the reference. It
is programmed in character row times. The value programmed in the register is one less than the number of computed
character line times. When the programmed value of this
register is increased, the display position of the CRT screen
is shifted up. When the programmed value is decreased the
display position is shifted down. Any number equal to or less
than the vertical total (R4) may be used.

a. The Horizontal Total Register value, RO, must be odd
(i.e., an even number of character timesl.

Interlace Mode and Skew Register (RB) - This 6-bit
register controls the. interlace modes and allows a programmable delay of zero to two character clock times for the DE
(display enable) and Cursor outputs. Table 2 shows the interlace modes available to the user. These modes are
selected using the two low order bits of this 6-bit register.

b. For the Interlace Sync and Video mode only, the Vertical Displayed Register (R6) must be even. The programmed number, Nvd, must be 1h the actual number
required.

3-362

MC6835

TABLE 4 - CURSOR AND DE SKEW CONTROL
Value
00

01
10
11

tion the cursor anywhere on the screen and allow the start
address to be modified.
The Address Register is a five-bit write-only register used
as an "indirect" or "pointer" register. Its contents are the ~
dress of one of the other 18 registers. When both R~and CS
are low, the Address Register is selected. When CS is low
and RS is high, the register pointed to by the Address
Register is selected.

Skew
No Character Skew
One Character Skew
Two Character Skew
Not Available

Maximum Scan Line Address Register (R9) - This 5-bit
register determines the number of scan lines per character
row including the spacing thus controlling operation of the
Row Address counter. The programmed value is a maximum
address and is one less than the number of scan lines.

Start Address Register (R12-H. R13-LI - This 14-bit
write-only register pair controls the first address output by
the CRTC after vertical blanking. It consists of an 8-bit low
order (MAO-MA7l register and a 6-bit high order (MA8MA 13) register. The start address register determines which
portion of the refresh RAM is displayed on the CRT screen.
Hardware scrolling by character, line or page may be accomplished by modifying the contents of this register.

Cursor Start Register (R10) and Cursor End Register (R11)
- These registers allow a cursor of up to 32 scan lines in
height to be placed on any scan line of the character block as
shown in Figure 14. R10 is a 7-bit register used to define the
start scan line and blink rate for the cursor. Bits 5 and 6 of
the Cursor Start Address Register control the cursor operation as shown in Table 4. Non-display, display and two blink
modes (16 times or 32 times the field period) are available.
R11 is a 5-bit register which defines the last scan line of the
cursor.
When an external blink feature on characters is required, it
may be necessary to perform cursor blink externally so that
both blink rates are synchronized. Note that an invert/noninvert cursor is easily implemented by programming the
CRTC for a blinking cursor and externally inverting the video
signal with an exclusive-OR gate.

Cursor Register (R14-H. R15-L) - This 14-bit write-only
register pair is programmed to position the cursor anywhere
in the refresh RAM area thus allowing hardware paging and
scrolling through memory without loss of the original cursor
position. It consists of an 8-bit low order (MAO-MA7) register
and a 6-bit high order (MA8-MA13) register.
CRTC INITIALIZATION
Registers R12-R15 must be initialized after the system is
powered up. The processor will normally load the CRTC
register file from a firmware table. Figure 15 shows an M6800
program which could be used to program the CRT Controller.

PROGRAMMABLE REGISTERS
The four programmable registers allow the MPU to pas i-

FIGURE 14 - CURSOR CONTROL

I
I

I

~

I

On

I
I

Off

On

-+

: . - Blink Period =
I
16 or 32 Times
Field Period
Example of Cursor Display Mode

o-+-+-+-+---t--t-+-

o-+-+-++-+-t-t-

1-+-+-+-+-+-+-+-

1-+-+-~-+-++2-+-++-+-+-+-+3-+-+-+-H-+--t-

2 -+-+-+-IH-++3 -+-++-H-+-+4 -+-+-+-+-+-t-t5 -+-+-+-IH-+-+-

6-+-++-H-++7-1-+-++-H-+-

4 -f-+-+-+-t--ir-+5 -+-++-+-+-++-

6-+-++-+-+-++7-+-++-+-+-++8 --I--+-+-+-+-t-t-

O-+-+-+--+-+--f--+l-$eG~M.

2~eEI)e!BEl3.

;~~It&:

5-eEEM~Kr
6 -+-++-+-+-++7 -I-+-+-+H-+-

8:--I-+-+-+-t-I'""""+91-$"1$EI~!r
10-lH--++-HH-11-+-+-+-+-t-t-+-

1~~~:a~~~~
11--+-+-+--+-..-...t'""""+-

10 -+-+-+-+-+-+-+11 --+--+-+--+-+--f-+-

Cursor Start Adr. = 9
Cursor End Adr. = 9

Cursor Start Adr. = 9
Cursor End Adr. = 10

Cursor Start Adr. = 1
Cursor End Adr. =5

3·363

8 --I-+-+--+-+--f-+-

9 -+-++-f-+-+-+-

I

MC6835

ADDITIONAL CRTC APPLICATIONS

quired to meet system specifications. The worksheet of
Table 5 is extremely useful in computing proper register
values for the MC6835. The program shown in Figure 15 may
be expanded to properly load the calculated register values in
the MC6845. Once the two sets of regi~ter values have been
developed, fill out the ROM program worksheet of Figure 18.
To order a custom programmed MC6835, contact your
local field service office, local sales person or your local
Motorola representative. A manufacturing mask will be
developed for the data entered in Figure 18.

The foremost system function which may be performed by
the CRTC controller is the refreshing of dynamic RAM. This
is quite simple as the refresh addresses continually run.
Both the VS and the HS outputs may be used as a real
time clock. Once programmed, the CRTC will provide a
stable reference frequency.
SELECTING MASK PROGRAMMED REGISTER VALUES
A prototype system may be developed using the MC6845
CRTC. This will allow register values to be modified as re-

FIGURE 15 -

I

PAGE

001

CRTCINIT.SA:l

MC6835 CRTC initialization program
NAM
TTL
OPT

(IJ(IJ0(IJ1
(IJ(IJ0(IJ2
(IJ(IJ0(IJ3
(IJ(IJ0(IJ4
(IJ(IJ0(IJ5
(IJ(IJ0(IJ6
(IJ(IJ0(IJ7
(IJ(IJ0(IJ8
(IJ(IJ0(IJ9
(IJ(IJ01(IJ
(IJ(IJ011

(IJ(IJ012A
(IJ(IJ013A
(IJ(IJ014A
(IJ(IJ015A
(IJ(IJ016A
00017A
(lJ0018A
00U9A
(lJ002(IJA
00021A
0(IJ022A

M6800 PROGRAM FOR CRTC INITIALIZATION

MC6835
CRTC initialization program
G,S,LLE=85 print FCB'x, FDB's & XREF table

********************************************************

9(IJ0(IJ

9(IJ(lJl

* Assign CRTC
*
CRTCAD EQU

address

A
A CRTCRG EQU

$90(IJ(IJ
Address Register
CRTCAD+l Data Register

********************************************************
(IJ(IJ(IJ(IJ
(IJ(IJ(IJ(IJ
(IJ(IJ(IJ2
(IJ(IJ(IJ5
(IJ(IJ08

(IJ(IJ0A
(IJ(IJ(IJD

(IJ(IJ(IJE
(lJ0(IJF
0011
(IJ(IJ13

*
*

C6
CE
F7
A6
B7
(lJ8
5C
Dl
26
3F

(lJC
1(IJ20
9(IJ(IJ(IJ

0(IJ
9(IJ(lJl

1(IJ
F2

Initialization Program

A
A
A CRTCl
A
A
A

(lJ0(IJ5

ORG
LDAB
LDX
STAB
LDAA
STAA
INX
INCB
CMPB
BNE
SWI

(IJ
$C
38RTTAB
CRTCAD
(IJ,X
CRTCRG

a place to start
initialize pointer
table pointer
load address register
get register value from table
program register
increment counter

$1(IJ

finished?
no: take branch
yes: call monitor

CRTCl

********************************************************

(IJ(IJ023
(IJ(IJ024
(lJ0025

0(IJ026A 1020
(IJ(IJ027A 1(IJ20
(lJ0(IJ28A 1(IJ22
(lJ0029

*
*

CRTC register initialization table

ORG
A CRTTAB FDB
A
FDB
END

$102(IJ

$0080
$0080

start of table
R12, R13 - Start Address
R14, R15 - Cursor Address

TOTAL ERRORS

CRTCl

0(IJ05

CRTCAD 9000 . CRTCRG 9001

CRTTAB 1020

3·364

3:

n
en
CO

w
en

TABLE 5 - CRTC FORMAT WORKSHEET
CRTC Registers

Display Format Worksheet

1.

Displayed Characters per Row

Char

2.

Displayed Character Rows per Screen

Rows

3.

Character Matrix

4. Character Block

U)

II
0)
0'1

a. Columns

Columns

b. Rows

Rows

a. Columns

Columns

b. Rows

Rows

5.

Frame Refresh Rate

Hz

6.

Horizontal Oscillator Frequency

Hz

7. Active Scan Lines (Line 2x Line 4b)

Lines

8. Total Scan Lines (Line 6+ Line 5)

Lines

9. Total Rows Per Screen (Line 8+ Line 4b)

_ _ Rows

and _ _ Lines

10. Vertical Sync Delay (Char. Rows)

Rows

11. Vertical Sync Width (Scan lines (16))

Lines

Decimal

RO Horizontal Total (Line 15 - 1)
R1 Horizontal Displayed (Line 1)
R2 Horizontal Sync Position (Line 1 + Line 12)
R3 Horizontal Sync Width (Line 13)
R4 Vertical Total (Line 9-1)
R5 Vertical Adjust (Line 9 Lines)
R6 Vertical Displayed (Line 2)
R7 Vertical Sync Position (Line 2+ Line 10)
R8 Interlace (00 Normal, 01 Interlace,
03 Interlace, and Video)
R9 Max Scan Line Add (Line 4b - 1)
Rl0 Cursor Start

Horizontal Sync Delay (Character Times)

Char. Times

13. Horizontal Sync Width (Character Times)

Char. Times

R12, R13 Start Address (H and l)

Horizontal Scan Delay (Character Times)

Char Times

R14, R15 Cursor (H and L)

12.

14.

15. Total Character Times (Line 1 + 12+ 13+ 14)

Char Times

16. Character Rate (Line 6 x 15)

Hz

17.

Dot Clock Rate (Line 4a x 16)

Rll

Cursor End

Hz

III

Hex

-

3:
(")
0)
OC)

W

(II

TABLE 6 -

WORKSHEET FOR

SOx 24 FORMAT

Display Format Worksheet

1.

Displayed Characters per Row

80

Char.

2.

Displayed Character Rows per Screen

24

Rows

3. Character Matrix

a. Columns

4.

Character Block

b. Rows
a. Columns

5.

Frame Refresh Rate

b. Rows

U)

l>

0)
0)

CRTC Registers

6.

Horizontal Oscillator Frequency

7.

Active Scan Lines (Line 2 x Line 4b)

8. Total Scan L.ines (Line 6+ L.ine 5)
9. Total Rows Per Screen (Line 8+ Line 4b)

9
__
9 ___

50

86

__
56_ _

27

_ _1_8_ _

11

Rows

R3 Horizontal Sync Width (Line 13)

60

Hz

R4 Vertical Total (Line 9 minus 1)

18,600

~

Hz

R5 Vertical Adjust (Line 9 Lines)

264

Lines

R6 Vertical Displayed (Line 2)

24

__
18

310

L.ines

R7 Vertical Sync Position (Line 2+ Line 101

24

18

28

Rows and

2

Lines

Rows _ _ _
_ _1_6_ _

Char. Times

1.8972 M
rL07~_

10

- -B

R10 Cursor Start

0

- -0

R11

11

- -B

R12, R13 Start Address (H and LI

128

00
---

R14, R15 Cursor (H and LI

128

00
---

R9 Max Scan L.ine Add (Line 4b minus 1)

14. Horizontal Scan Delay (Character Times)
102

R8 Interlace (00 Normal, 01 Interlace,
03 Interlace, and Video)

Lines

Char. Times

17. Dot Clock Rate (Lllie 4a times 16)

80

R2 Horizontal Sync Position (Line 1 + Line 12)

Horizontal Sync Width (Character Times)

16. Character Rate (Line 6 times 151

65
---_.-

Horizontal Displayed (Line 11

Rows
Columns

Char. Times

15. Total Character Times (Line 1 + 12+ 13+ 14)

RO Horizontal Total (Line 15 minus 11
R1

12. Horizontal Sync Delay (Character Times)
13.

Hex

101

Columns

10. Vertical Sync Delay (Char Rowsl
11. Vertical Sync Width (Scan L.ines (1611

Decimal

Char. Times
MHz
MHz

Cursor End

80
--80

MC6835

OPERATION OF THE CRTC
Timing of the CRT Interface Signals - Timing charts of
CRT interface signals are illustrated in this section with the
aid of programmed example of the CRTC. When values
listed in Table 7 are programmed into CRTC control
registers, the device provides the outputs as shown in the
Timing Diagrams (Figures 11, 12, 16, and 17). The screen

TABLE 7 Register
Number

format of this example is shown in Figure 10. Figure 17 is an
illustration of the relation between Refresh Memory Address
(MAO-MA13), Raster Address (RAO-RA4) and the position
on the screen. In this example, the start address is assumed
to be "0".

VALUES PROGRAMMED INTO CRTC REGISTERS
Register Name

Value

Programmed
Value

Nht+ 1

Nht

Nhd

Nhd

RO

H. Total

Rl

H. Displayed

R2
R3

H. Sync Position

Nhsp

Nhsp

H. Sync Width

Nhsw

Nhsw

R4

V. Total

Nvt + 1

Nvt

R5

V. Scan Line Adjust

Nadi

Nadj

R6

V. Displayed

R7

V. Sync Position

Nvd
Nvsp

Nvd
Nvsp

R8

Interlace Mode

R9

Max. Scan Line Address

Nsl

Nsl

Rl0

Cursor Start

Rll

Cursor End

R12

Start Address (H)

0

R13

Start Address (U

0

R14

Cursor (H)

R15

Cursor (U

I

iii
3:

n
en

tI

(II

FIGURE 16 -

RAO-RA4"

MAO-MA13"

Character Row #
(,)

~

0)

CO

Character #

Cursor

CURSOR TIMING

F

f

f

I

I

I

4.

,

,

i

I

I

I

T NhdNhd+1

~I

I
I

:

Nhd+21

:

:

\

\

I

I

\
I

I
I

l
2'

I

,
Nhd+
Nht

I

•
Nhd

:

'"

i\;

Nht

r---1

0

•

dr-I

INhd+1INghd+2\
I
I

I

I

I

I

:

:

I

I

I

I

I

I

I

r-----I

Nhd+
Nht

•I
I
:

\

~:

I

I
Nht

f
Nhd

•

-q

I

\

I

I Nhd+ I
Nht I

I

:

\ Nhd+1INhd+2r-'

:

I
I
I

I
I

\

k
f
I

~
I

I
Nht

r---i'--____

"Timing is shown for non-interlace and interlace sync modes.
Example shown has cursor programmed as:
Cursor Register= Nhd+ 2
Cursor Start = 1
Cursor End = 3
""The initial MA is determined by the contents of Start Address Register, R12/R13. Timing is shown for R12/R13=O.
NOTE1: Timing values are described in Table 8.

I

•

3:

FIGURE 17 -

n
en

REFRESH MEMORY ADDRESSING (MAG-MA131 STATE CHART

CO

w

(J)

..§

(J)

o

ro

ro

~

.<= 0

Urr:

Horizontal Display

~I~
I

0t:

{:

~I
>

I
0

I
I

Nrd

Nh~+ 1

I

I

Nhd

Nhd+ 1

2XNhd

2XN~d+ 1

I

I

2XNhd

2XNh'd+ 1

2
{

~

1

I

0I

I

Ns

1/

0
I

~Q;

>

1

w

~

m

co

(Nvd-1) x Nhd

NV d- 1{

i

0
(Nvd -

Ns

0

1) x Nhd

Nvd x Nhd

1
(Nvd-1) x Nhd+ 1

I
I

(Nvd-lI x Nhd+ 1
Nvd x Nhd+ 1
I

Nvd

%

{
Ns I

~

U1

Horizontal Retrace (Non-Display)

I

I

Nvd x Nhd

Nvd x Nhd+ 1

Nvt x Nhd

Nvt x Nhd+ 1

I

I

•
•.
•
•
•

..
..•
•

Nhd- 1

N~d

I

I

I

Nhd- 1

Nhd

2XNhd -1

2X~hd

i

I

2XNhd -1

2XNhd

3XNh.d -1

3X~hd

I

I

3XNhd -1

3XNhd

1
Nvd x Nhd+ 1
I

1
Nvd ~ Nhd

I

I

Nvd x Nhd-1

Nvd x Nhd

(Nvd+ 1) x Nhd-1

(Nvd+ 1) x Nhd

I

I

.
I

•
•
•

..

•

.
..
..
.

Nht
I

I
I

Nht
Nhd+ Nht
I

I

•
Nhd+ Nht
2Nhd+ Nht
I
I

2Nhd'+ Nht

1
(Nvd -1 )xNhd+Nht

I

I

(Nvd-1)xNhd+Nht
Nvd x Nhd + Nht

I

I

(Nvd+ 1) x Nhd-1

(Nvt+ 1) x Nhd

(Nvt+ 1) x Nhd-1

(N vt + 1) x Nhd

Nvt x Nhd + Nht

I

I

Nvd + Nhd + Nht

~o

~
(J)

o

ro
(J)

rr:

N

Vt

{

ro

Ns

o

~

(J)

>

0

I

Nvt + 1 {

0
Nad I

-;

I

Nvt~ Nhd

I

(Nvt+ 1) x Nhd

(N vt + 1) ~ Nhd+ 1

t
(Nvt+ 11• x Nhd

i
(N vt + 1) x Nhd-1

(Nvt+ 1) x Nhd

Nvt x Nhd + Nht

IN",+2I(Nhd- 1 1 (Nvt +:) x Nhd

(N v + 1)~hd+ Nht

I
(N vt + 1) x Nd+ 1

I

(Nvt+ 2) x Nhd-1

I

t

(Nvt + 2) x Nhd

(Nvt + 1)Nhd + Nht

NOTE 1: The initial MA is determined by the contents of start address register, R12/R13. Timing is shown for R12/R13=O. Only NonInterlace and Interlace Sync Modes are shown.

MC6835

FIGURE 18 -

ROM PROGRAM WORKSHEET

The value in each register of the MC6845 should be entered without any modifications. Motorola will take care of translating into the appropriate
format.

o

All numbers are in decimal.

o

All numbers are in hex.

ROM
Program
Zero
(PROG=O)

ROM
Program
One
(PROG=l)

RO
Rl
R2
R3

I

R4

R5
R6

R7
R8

R9
Rl0
Rl1

ORDERING INFORMATION
Frequency (MHz)

Temperature*

Ceramic
L Suffix

1.0
1.0
1.5
1.5
2.0
2.0

O°C to 70°C
- 50°C to 85°C
O°C to 70°C
- 50°C to 85°C
O°C to 70°C
-50°C to 85°C

MC6835L
MC6835CL
MC68A35L
MC68A35CL
MC68835L
MC68B35CL

Cerdip
S Suffix

1.0
1.0
1.5
1.5
2.0
2.0

O°C to 70°C
- 50°C to 85°C
O°C to 70°C
- 50°C to 85°C
O°C to 70°C
- 50°C to 85°C

MC6835S
MC6835CS
MC68A35S
MC68A35CS
MC68B35S
MC68B35CS

Plastic
P Suffix

1.0
1.0
1.5
1.5
2.0
2.0

O°C to 70°C
- 50°C to 85°C
O°C to 70°C
- 50°C to 85°C
O°C to 70°C
- 50°C to 85°C

MC6835P
MC6835CP
MC68A35P
MC68A35CP
MC68B35P
MC68B35CP

Package Type

3-370

Order Number

®

MCM6836E16
MCM6836R16

MOTOROLA

Advance Information
HMOS
128K-BIT COMBINATION ROM/EEPROM MEMORY UNIT

HIGH-DENSITY N-CHANNEL PROCESS

The MCM6836E16/MCM6836R16 Combination ROM/EEPROM
Memory (CREEM) is a 16K byte combination memory device with 14K
bytes of mask programmable ROM and 2K bytes of electrically erasable
programmable ROM (EEPROM). It is designed for handling data in
applications requiring nonvolatile memory and in-system reprogramming to a portion of the memory. The MCM6836 saves time and money
because of the in-system erase and reprogram capability of its 2K bytes
of EEPROM. The industry standard pinout in a 28-pin dual-in-line
package makes the MCM6836( ) 16 compatible with 128K-bit ROMs and
EPROMs.
For easy use, the MCM6836( )16 device operates in the read mode
from a single power supply and has a static power·down mode. The
MCM6836R16 version has a 256 byte user programmable redundancy
EEPROM on chip. It can be programmed by the user to replace any
page of 256 bytes of memory in the mask ROM or EEPROM sections.
The following are some of the major features of the MCM6836( )16.

128K-BIT COMBINATION
ROM/EEPROM MEMORY

S SUFFIX
CERDIP PACKAGE
CASE 733

P SUFFIX
PLASTIC PACKAGE
CASE 710

• 128K-Bit ROM/EEPROM Combination Memory Organized as
16,384 x 8 Bytes
•
•
•
•
•

Lowest Order 2K Bytes are Bulk Erasable EEPROM
Remaining 14K Bytes are Mask Programmed ROM
Packaged in Standard 28-Pin DIP
Pin Compatible with 128K-Bit ROMs and EEPROMs
In the Read Operating Mode Only + 5 V Power Supply is Required

PIN ASSIGNMENT

• + 21 Vdc Programming Power Supply
• Bulk Erase
• 256 Bytes of Spare Memory are Included on Chip (MCM6836R16
Only)
• Seven Operating Modes: Read, Standby, Program, Erase, Verify,
Replace (MCM6836R16 Only), and Erase-of-Replace (MCM6836R16
Only)

Vpp

VCC

A12

W

A7

A13

A6

AS

A5

A9

A4

All

A3

G

A2

Al0

Al

E

AO

D07

DOO

D06

DOl

D05

D02

D04

VSS

ID03

ORDERING INFORMATION (T A = O°C to 70°C)

Package Type

Order Number

Cerdip
S Suffix

MCM6836E16S
MCM6836R16S

Plastic
P Suffix

MCM6836E16P
MCM6836R16P

Pin Names
AO-A13

E.
G.

W
DOO-DOl
Vpp.
VCC
VSS
This document contains Information on a new product. Specifications and information herein
are subject to change without notice

3-371

... Address
. Chip Enable
. Output Enable
... Write
....... Data
. Program Voltage
. . + 5 V Power Supply
Ground

I

MCM6836E/R16

FIGURE 1 -

MCM6836( )16 EEPROM MEMORY UNIT BLOCK DIAGRAM
Data Input/Output DOD-D07

E
G
Vii

A~A5

I

A~A13

{

Y
Decoder

V-Gating

{

114.688-Bit
ROM

X
Decoder

16.384-Bit
EEPROM

2048-Bit
Spare EEPROM

Spare
Decoder

FIGURE 2 - AC TEST LOAD
VDD=5V

Test Point

.....

o-----4t--~t--_I--

100 pF

MMD7000
or Equiv.

3·372

MCM6836E/R16

MAXIMUM RATINGS (Voltages Referenced to Vss)
Ratings

Symbol

Supply Voltage

VCC

Value
-0.3 to + 7.0

Unit
V

Programming Voltage

VPP

-0.3 to +22

V

Input Voltage
Mode Programming Pin
All Other Inputs

V,HH
Vin

-0.3 to + 19
-0.3 to + 7

V
V

TA
Tstg

o to 70

°c

-55 to + 150

°c

Operating Temperature Range
Storage Temperature Range

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Cerdip
Plastic

Symbol

Value

Unit

8JA

60
100

°C/W

This device contains circuitry to protect
the inputs against damage due to high
static voltages of electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin and
V out be constrained to the range
VSS::s(Vin or Vout)::SVCc. Reliability of
operation is enhanced if unused inputs
are connected to an appropriate logic
voltage level (e.g., either VSS or VCC'-

I

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
TJ = TA + (POeOJA)
(1)
Where:
TA ==Ambient Temperature, °c
OJA == Package Thermal Resistance, Junction-to-Ambient, °C/W
PO==P,NT+ PPORT
P'NT==ICCx VCC, Watts - Chip Internal Power
PPORT == Port Power Oissipation, Watts - User Oetermined
For most applications PPORT-

5.0 V
RL = 12k
MMD5150
or Equiv.

Test Point
100 pF *

10.9 k
MMD7000
or Equiv

* Includes Jig Capacitance

HIGH
IMPEDANCE

3-384

MC6839

FIGURE 2 - TIMING DIAGRAM
f4..---------tELEL

CHiP ENABLE.

----------.-j

E
f4..---------tELEH-----~

ADDRESS. A

~----H-tELQV~.~_

VOH-_ _

IlrZ--------

DATA OUTPUT. Q

VALID

__-------HIZ-------__

VOL-

NOTES:
1. Voltage levels shown are VL:50A, VH",2A V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted

INTRODUCTION
Since the earliest days of computers it has been obvious
that no computer was capable of doing all desirable
mathematical operations in binary integer arithmetic. To
meet the needs of those applications requiring the manipulation of real numbers, floating point (FP) evolved and became
widely used. Unfortunately, each computer manufacturer
created his own floating point (FP) representation and the
ensuing wide variation in formats, accuracy, and exception
handling almost guarantees that a program executed on one
computer will get different results if executed on another
computer.
Meanwhile, research has been completed which formulates an optional binary floating point representation. Unfortunately, the existing manufacturers have far too much
money invested in software and hardware to incur the costs
of conversion to a new standard. Powerful microprocessors,
on the other hand, were in their infancy and the floating
point experts saw the opportunity to standardize a floating
point format for microprocessors. The IEEE appointed a
committee to address the standard and their work resulted in
the IEEE Proposed Standard for Binary Floating Point
Arithmetic Draft B.D.
The MC6839 represents a complete implementation of the
IEEE proposed standard. Since hardware implementations of
floating point (FP) are always several orders of magnitude
faster (and more expensive) than software implementations,
the MC6839 substitutes increased functionality for speed.
Therefore, the MC6839 supports all precisions, modes, and

3-385

operations required or suggested by the IEEE proposed standard.
From its very inception, the M6809 microprocessor was
designed to support a concept of ROMabie software by an
improved instruction set and addressing modes. It was felt
that the only way to reduce the escalating cost of software
was for the silicon manufacturer to supply software on
silicon. Since the manufacturer can amortize the cost of
developing the software over a very large volume, the cost of
this software, above normal masked ROM costs, will be low.
Also, to be useful in many diverse systems, the ROM must
be pOSition-independent and re-entrant.
The intent of this Advance Information (data) Sheet is to
provide the reader with enough information to make an intelligent decision as to whether the MC6839 is applicable to
his system. The intent is not to provide all the details
necessary to interface or program the MC6839. A familiarity
with the MC6809 instruction set is assumed in this document.

PHYSICAL CHARACTERISTICS
The MC6839 is housed in one 24-pin 8K-by-8 mask programmable ROM: the MCM68364. This ROM uses a single
5 V power supply and is available with access times of 250 or
350 ns. The MC6839 is designed to be used in MC6809 or
MC6809E systems with up to 2 MHz internal clocks. Full
device characteristics can be found at the front of this data
sheet.

I

MC6839

FLOATING POINT FORMATS
The MC6839 supports the three precisions suggested by the IEEE Proposed Floating Point Standard: single, double, and extended. The values occupy 32,64, and 80 bits (4, 8, and 10 bytes) respectively in the users memory. The formats of the three precisions
are described in the following paragraphs.

SINGLE FORMAT
All single precision numbers are represented in four bytes as:
11 f.--8-~.*"1o({-----23 bits--~.I

Is I

exponent

I

significand

I

The exponent is biased by + 127. That is exponent of: 20 is 127, 22 is 129, and 2-2 is 125. The significand is stored in sign
magnitude rather than twos complement form. The equation for the single form representation is:
x = (- 1)S x 2(exp - 127) x (1. significand)

I

s
exp
significand

= sign of the slgniflcand
= biased exponent
= bit string of length 23 encoding the significant bits of the number that follow the binary point, yielding a 24-bit significant digit field for the number that always begins "1 ___ ."

Examples:
+1.0= 1.0x20=$3F
+3.0= 1.5x21=$40
-1.0= -1.0x20=$BF

80
40
80

00
00
00

00
00
00

DOUBLE FORMAT
All double precision numbers are represented by an 8-byte string as:
11 f..:--11 bits;~.*IO(O(----52 bits;--~.I

Is I

exponent

I

significand

I

For double formats the exponent is biased by + 1023. The rest of the interpretation is the same as for single format. The equation for double format is:
x = (- 1)S x 2(exp - 1023) x (1. significand)
Examples:
7.0= 1.75 =22= $40
- 30.0= -1.875x 24 = $CO
0.25= 1.0x2- 2 = $3F

1C
3E
DO

00
00
00

00
00
00

00
00
00

00
00
00

00
00
00

00
00
00

EXTENDED FORMAT
Single- and double-formats should be used to represent the bulk of floating point (FP) numbers in the user's system (e.g.,
storage of arrays). Extended should only be used for intermediate calculations such as occur in the evaluation of a complex expression. In fact, extended may not be used at all by most users, bl" since it is required internally, it is optionally provided. Extended
numbers are represented in 10 bytes as:
11 k--15 bits-..+oI!IIlf----64
I s 1

exponent

11.

3-386

bits-----:~~I

significand

I

MC6839

A notable difference between this format and single and double is the 1.0 is explicitly present in the significand and the exponent
contains no bias and is in twos complement form. The equation for double extended is:
x = ( - 1)s x 2exp x significand
where the significand contains the explicit 1.0.
Examples:
0.5= 1.0x2- 1 =
-1.0= -1.0x 20
384.0= 1.5x 28

$7F
$80
$00

FF
00
08

80
80
CO

00
00
00

00
00
00

00
00
00

00
00
00

00
00
00

00
00
00

00
00
00

BCD STRINGS
A BCD string is the input to the BCD-to-Floating-Point conversion operation and the output of the Floating-Point-to-BCD conversion operation. All BCD strings have the following format:

o
se

5 6

1
4 digit BCD exponent

sf

24 25
19 digit BCD fraction

p

se=sign of the exponent. $00= plus, $OF=minus. (one byte)
sf = sign of the fraction. $00 = plus, $OF = minus. (one byte)
p = number of fraction digits to the right of the decimal point. (one byte)
All BCD digits are unpacked and right Justified in each byte:

7

0
_0_0_0_0--1._ _0_-9_ _1

LI

The byte ordering of the fraction and exponent is consistent with all Motorola processors in that the most-significant BCD digit is
in the lowest memory address.
Examples:
2.0=2.0x 100 (p=O)
Address
0000
0001
0005
0006
ooOB
0010
0015
0019

Data
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
or 2.0= 20,000 x 1O- 4 (p=0)
Address
Data
0000
OF
0001
00
00
00
0005
00
0006
00
00
00
OooB
00
00
00
0010
00
00
00
0015
00
00
00
0019
00
(The above might be the output of a

00
00
00
00
02

Ise= + I
1exponent = 01
Isf= +1
00 !fraction = 21
00
00
Ip=OI

04

00
00
00
00

!se= -I
lexponent = 41
Isf= + I
00 Ifraction = 200001
00
02

!p=OI
Floating-Point-to-BCD with k = 5)

or 2.0= 2.0 x 100 (p = 10)
Address
0000
0001
0005
0006
oooB
0010
0015
0019

Data
00
00
00
00
00
00
00
OA

00

00

00

00
00
00
00

00
00
00
00

00
02
00
00

Ise= + I
1exponent = 01
Isf= + I
00 Ifraction = 200000000001
00
00
Ip= 101

3-387

I

MC6839

INTEGERS

I

ASCII
Mnemonic
Description
FADD
Add arg1 to arg2 and store the result.

Two sizes of integers are supported; short and double.
Short integers are 16 bits long and double integers are 32 bits
long. The byte ordering is consistent with all Motorola processors in that the most-significant bits are in the lowest address.

FSUB

Subtract arg2 from arg1 and store the result.

FMUL

Multiply arg1 times arg2 and store the result.

FDIV

Divide arg1 by arg2 and store the result.

SPECIAL VALUES

FREM

Take the remainder of arg1 divided by arg2 and
store the result. The remainder is biased to lie in
the range - arg2/2 < remainder< + arg2/2, instead of the usual range of O~ remainder< arg2.
This bias makes the function more useful in the
implementation of trigonometric and other functions.

FCMP

Compare arg1 with arg2 and set the condition
codes to the result of the compare. Arg1 and arg2
can be of different precisions.
Compare arg1 with arg2 and set the condition
codes to the result of the compare. In addition,
trap if an unordered exception occurs regardless
of the state of the UNOR (unordered) bit in the
trap enable byte of the fpcb.

No derivable floating point format can represent the infinite number of possible real numbers, so it is very useful if
some special numbers are recognized by a floating point
package. These numbers are: + 0, - 0, + infinity, - infinity, very small (almost zero) numbers, and in some cases unnormalized numbers. Also, it is convenient to have a special
format which indicates that the contents of memory do not
contain a valid floating point number. This "not a number"
might occur if a variable is defined in a HLL and is used
before it is initialized with a value. The most positive and
negative exponents of each format are reserved to represent
these special vaues.
The detailed description of these special values is given in
a later section.

FTCMP

FPCMP

ARCHITECTURE

FTPCMP A trapping predicate compare; same as the
predicate compare except trap on an unordered
exception regardless of the state of the UNOR
(unordered) bit in the trap enable byte of the fpcb

All floating point operations are of the "two address" or
"three address" variety; all the user need supply are the addresses of the operand(s) and the result. The package looks
for operands at the specified location(s) and delivers the
result to the specified destination. For example,
Arg1
+
Arg2
< source>
< source>

A predicate compare; this means compare arg1
with arg2 and affirm or disaffirm the input
predicate (e.g., 'is arg 1 = arg2' or 'is arg1 < arg2').

FSQRT
FINT

Result
< destination>

Intermediate results are never presented to the user;
therefore, there are no internal "registers" to be concerned
about, keeping the interface as simple as possible. The end
result is ease of use.
There is a user defined floating point control block (fpcb)
that defines the mode of the package. This control block is
much like the control blocks frequently used to define I/O or
operating system operations. The fpcb is discussed in detail
in a later section.

FFIXS

Convert arg2 to a short (16-bit) binary integer.

FFIXD

Convert arg2 to a long (32-bit) binary integer.

FFLTS

Convert a short binary integer to a floating point
result.

FFLTD

Convert a long binary integer to a floating point
result.

BINDEC

Convert a binary floating point value to a BCD
decimal string.

DECBIN

Convert a BCD decimal string to a binary floating
point result.
Return the absolute value of arg2 in the result.

FABS

SUPPORTED OPERATIONS

FNEG
FMOV

The MC6839 supports the following operations. On any
particular call to the floating point ROM a 1-byte opcode
which immediately follows the LBSR instruction chooses the
desired operation. Below are short descriptions of the functions implemented in the MC6839 along with suggested
men manics. A table containing the opcodes and calling sequences for these functions is presented at the end of this
data sheet.

Returns the square root of arg2 in the result.
Returns the interger part of arg2 in the result. The
result is still a floating point number. For example,
the integer part of 3.14159 is 3.00000.

Return the negative of arg2 in the result.
Move (or convert) arg1-arg2. This function IS
useful for changing precisions (e.g., single to
double) with full exception checking for possible
overflow or underflow.

All routines, except FMOV and the compares, accept
arguments of the same precision and generate a result with
the same precision. For moves and compares the sizes of the
arguments are passed to the package in a parameter word.

3-388

MC6839

MODES OF OPERATION
In addition to supporting a wide range of precisions and
operations, the MC6839 supports all modes required or suggested by the IEEE Proposed Floating Point Standard. These
include rounding modes, infinity closure modes, and exception handling modes. The various modes are selected by bits
in the floating point control block (fpcb) that resides in user
memory. Thus, each user or task can have a unique set of
modes in effect for his calculations. The selection bits are
defined in a later section on the fpcb.
ROUNDING MODES
Four rounding modes are suggested by the IEEE Proposed
Floating Point Standard. They are:
(RN)
1. Round to nearest
(RZl
2. Round toward zero
(RP)
3. Round toward plus infinity
(RN)
4. Round toward minus infinity
Round nearest will be used by most users because it provides the most accurate answers for most calculations.
Round towards zero (truncate) is useful when the MC6839
implements real numbers in some high level languages that
require truncation (i .e., FORTRAN). Round towards plus
and minus infinity are used in interval arithmetic.
Normally a result is rounded to the precision of its destination. However, when the destination is Extended, the user
can specify that the result significand be rounded to the
precision of the basic format - single, double, or extended - of his choice, although the exponent range remains extended.
NO DOUBLE ROUNDING - The MC6839 is implemented
such that no result will undergo more than one rounding error.
INFINITY CLOSURE MODES
The way in which infinity is handled in a floating point
package may limit the number of applications in which the
package can be used. To solve this problem, the proposed
I EEE standard requires two types of infinity closures. A bit in
the control byte of the Floating Point Control Block (fpcb)
will select the type of closure that is in effect at any time.
AFFINE CLOSURE -

In affine closure:

minus infinity< levery finite numberl < plus infinity
Thus, infinity takes part in the real number system in the
same manner as any other Signed quantity.
PROJECTIVE CLOSURE -

In prOjective closure:

infinity = minus infinity = plus infinity
and all comparisons between infinity and a floating pOint
number involving order relations other than equal (= ) or not
equal (*-) are invalid operations. In projective closure the real
number system can be thought of as a circle with zero at the
top and infinity at the bottom.
NORMALIZE MODE
The purpose of the normalize mode is to prevent unnormalized results from being generated, which can otherwise
happen. Such an unnormalized result arises when a denor-

3-389

malized operand is operated on such that its fraction remains
not normalized but its exponent is no longer at its original
minimum value. By transforming denormalized operands to
normalized, internal form upon entering each operation, unnormalized results are guaranteed not to occur.
Thus, when operating in this mode the user can be
assured that no attempt will be made to return an unnormalized value to a single or double destination. A bit in the
control byte of the fpcb selects whether or not this mode is
in effect. This mode is forced whenever the round mode is
either round toward plus or minus infinity. Unnormalized
numbers entering an operation are not affected by this
mode, only denormalized ones are. Unnormalized and
denormalized operands are discussed in a later section.

EXCEPTIONS
One of the greatest strengths of the IEEE Proposed
Floating Point Standard is the regular and consistant handling of exceptions. Existing floating point implementations
are quite varied in the way they handle exceptions, so the
proposed IEEE standard has very carefully prescribed how
exceptions must be handled and what constitutes an exception. Seven types of exceptions will be recognized by the
MC6839. Only the first 5 are required by the proposed IEEE
standard. They are:
1. Invalid Operation - a general exception that arises
when an operation has gone so wrong that the program cannot return any reasonable result or fit the exception into any of the other more specific classes.
2. Underflow - arises when an operation generates a
result that is too small to fit into the desired result
precision.
3. Overflow - arises when an operation generates a
result that is too large to fit into the desired result
precision.
4. Division by Zero - arises when division by zero is attempted.
5. Inexact Result - arises when the result of an operation was not exact and therefore was rounded to the
desired precision before being returned to the user.
6. Integer Overflow - arises when the binary integer
result of a FIXS(O) operation cannot fit into 16(32)
bits.
7. Comparison of Unordered Values - arises when one
of the arguments to a compare operation is a "NAN"
or an infinity in the projective closure mode. (See the
Infinity and Not a Number paragraphs for further explanation of NANs and infinity.)
For each exception the caller will be given the option of
specifying whether the package should: (1) trap to a user
supplied trap routine to process the exception, or (2) deliver
a default result specified by the proposed standard and proceed with execution. For most users the default result is adequate and the user need not write any trap handlers.
Regardless of whether a trap is specified or not, a status bit
will be set in the status byte of the fpcb and will remain set
until cleared by the caller's program. Selection of whether to
trap or to continue will be made by setting bits in the trap
enable byte of the fpcb. For more details on the fpcb see the
section on the Floating Point Control Block (fpcb).

I

MC6839

If a trap is taken, the floating point package supplies a
pointer that points to an area on the stack containing the
following diagnostic information:
1. Event that caused the trap (overflow, etc.)
2. Where in the caller's program
3. Opcode
4. The input operands
5. The default result in internal format
In the event more than one exception occurs during the
same operation, only one trap is invoked according to the
following precedence.
1. Invalid Operation

I

2. Overflow
3. Underflow
4. Division by Zero
5. Unordered
6. Integer Overflow
7. Inexact Result
The user supplied trap routine (if any) will usually do 1 of 3
things:
1. Fix the result
2. Do nothing to the result and allow the floating point
package to deliver the aefault value to the result.
3. Abort execution.

USER INTERFACE
There are two types of calls to the floating point package: register calls and stack calls. For register calls the user loads the
machine registers with pointers (addresses) to the operand(s) and to the result; the call to the package is then performed. For stack
calls the operand(s) is pushed on the stack and the call to the package is performed with the result replacing the operands on the
stack after completion. The operand(s) must be pushed least-significant bytes first; this is consistent with the other Motorola architectures in that the most-significant byte resides in the lowest address. The two types of calls look like:
General form of a register call:
load registers
LBSR fpreg register call
FeB opcode
Example of a pOSition-independent call to the add routine:
LEAU
LEA Y
LEAX
TFR
LEAX
LBSR
FeB

arg1, pcr
arg2, pcr
fpcbptr, pcr
x, d
result, pcr
fpreg
fadd

pointer to fpcb

General form of a stack call:
push arguments
LBSR
fpstak
FeB
opcode
pull
result

stack call

Example of a stack call to the add routine:
push argument 1
push argument 2
push
fpcbptr
LBSR
fpstak
FeB
fadd
pull
result

pointer to fpcb

A reference table of calling sequences and opcodes can be found at the end of this data sheet.

3-390

MC6839

STACK REQUIREMENTS
When the MC6839 is called by the user, the package reserves local storage on the hardware stack. It then moves the input
arguments from user memory to the local storage area and expands them into a convenient internal format. The operations use
these "internal" numbers to arrive at an "internal" result which is then converted to the memory format of the result and returned
to the user. For this reason, the user must insure that adequate memory exists on the hardware stack before calling the MC6839.
The maximum stack sizes that any particular function will ever find necessary are:
register calls
stack calls

150 bytes
185 bytes

FLOATING POINT CONTROL BLOCK (fpcb)
The fpcb is a user-defined block that contains information needed by the floating point package. The fpcb is also used to pass
status back to the caller or to Invoke the trap routine. The fpcb must reside in the user RAM space to insure that the package can remain re-entrant. The caller of the floating pOint package must pass the address of the fpcb on each call. The format of the fpcb is:

0

control byte
trap enable byte
status byte

2

secondary status byte

3

I

4

address of trap routine

5

The meaning of the various bit fields Within the fpcb are discussed in detail in the following paragraphs
CONTROL BYTE - The control byte configures the floating point package for the caller's operation and is written by the user.
Various fields in the byte set the precision, round, infinity closure, and normalize modes.

7

Bit 0

Closure (AlP) Bit
0= projective closure
1 = affine closure

Bits 1-2

Round Mode
00= round to
01 = round to
10= round to
11 = round to

Bit 3

6

5

4

3

x

NRM

2

Roun~ Mode

o
AlP

nearest (RN)
zero (RZ)
plus infinity (RP)
minus infinity (RM)

Normalize (NRM) Bit
1 = normalize denormalized numbers while in internal format before using. Precludes the creation of unnormalized
numbers.
0= do not normalize denormalized numbers (warning mode)
NOTE
If the rounding mode is RM or RP then normalize mode is forced. Unnormalized numbers are not affected by bit 3.

Bit 4

Undefined, reserved

Bits 5-7

Precision Mode
000= Single
001 = Double
010= Extended with no forced rounding of result
011 = Extended - force round result to single
100= Extended - force round result to double
101 = Undefined, reserved
110= Undefined, reserved
111 = Undefined, reserved

Note that if the control byte is set to zero by the user, all defaults in the IEEE Proposed Floating Point Standard will be selected.

3-391

MC6839

STATUS BYTE

7

6

5

4

3

2

INX

IOV

UN

DZ

UNF

a
OVF

lOP

The bits in the status byte are set if any errors have occurred. Each bit of the status byte is a "sticky" bit in that it must be manually reset by the user. The FP package writes bits into the status byte but never clears existing bits. This is done so that a long calculation can be completed and the status need only be checked once at the end.
Invalid opertion (see secondary status)
Bit
Bit 1
Overflow
Bit 2
Underflow

a

I

Bit 3

Division by zero

Bit 4

Unordered

Bit 5

Integer overflow
Inexact result
Undefined, reserved

Bit 6
Bit 7

TRAP ENABLE BYTE

7

6

5

4

INX

IOV

UNOR

I

3

2

DZ

UNF

a
OVF

lOP

A "1" in any bit of the trap enable byte enables the FP package to trap if that error occurs. The bit definitions are the same as for
the status byte. Note that if a trapping compare is executed and the result is unordered, then the unordered trap will be taken
regardless of the state of the UNOR bit in the trap enable byte.
SECONDARY STATUS (SS)

6

5

4

3

2

a

Invalid: operatio:n Type

The FP package will write a status into this byte any time a new lOP occurs. As is the case with the status bytes, it is up to the
caller to reset the "lOP type" field.
Invalid Operation Type Field
Bits 0-4
0= no lOP error
1 = square root of a negative number, infinity in projective mode, or a not normalized number
2 = (+ infinity) + ( - infinity) in affine mode
3= tried to convert NAN to binary integer
4= in division: 0/0, infinity/infinity or divisor is not normalized and the dividend is not zero and is finite
5= one of the input arguments was a trapping NAN
6= unordered values compared via predicate other than = or :j::
7= k out of range for BINDEC or p out of range for DECBIN
8= projective closure use of + / - infinity
9 = x infinity
10= in REM arg2 is zero or not normalized or arg1 is infinite
11 = unused, reserved
12= unused, reserved
13= BINDEC integer too big to convert
14= DECBIN cannot represent input string
15= tried to MOV a single denormalized number to a double destination
16= tried to return an unnormalized number to single or double (invalid result)
17 = division by zero with divide by zero trap disabled

a

3·392

MC6839

TRAP VECTOR - If any of the traps occur, the FP package will jump indirectly through the trap address in the fpcb with an index in the A accumulator indicating the trap type:
0= Invalid Operation
1= Overflow
2= Underflow
3= Divide by Zero
4= Un normalized
5= Integer Overflow
6= Inexact Result
If more than 1 enabled trap occurs, the MC6839 will return the index of the highest priorty enabled error. Index= 0= invalid
operation is the highest priority, and, index=6 is the lowest.

SPECIAL VALUES (SINGLE- AND DOUBLE-FORMAT)
The encoding of the special values are given below. Generally, when used as operands, the special values flow through an operation creating a predictable result. Note that as with normalized numbers the extended format differs slightly from the single- and
double-formats.
ZERO

Zero is represented by a number with both a zero exponent and a zero significand. The sign is significant and differentiates between plus or minus zero.

o

o

INFINITY
The infinities are represented by a number with the maximum exponent and a zero significand. The sign differentiates plus or
minus infinity.

Is 11111 .. 11111

o

DENORMALIZED (SMALL NUMBERS)

When a number is so small that its exponent is the smallest allowable normal biased value (1), and it is impossible to normalize
the number without further decrementing the exponent, then the number will be allowed to become denormalized. The format for
denormalized numbers has a zero exponent and a non-zero significand. Note that in this form the impliCit bit is no longer 1 but is
zero. The interpretation for denormalized numbers is:
Single: X = (-1)s x 2 -126 x (0. significand)
Double: X = ( - 1)S x 2 - 1022 x (0. significand)
Note that the exponent is always interpreted as 2 - 126 for single and 2 - 1022 for double instead of 2 - 127 and 2 - 1023 as might
be expected. This is necessary since the only way to insure the implicit bit becomes zero is to right shift the significand (divide by 2)
and increment the exponent (multiply by 2). Thus, the exponent ends up with the interpretation of 2-126 or 2- 1022 .
The format for denormalized numbers is:

o

non-zero

Note that zero may be considered a special case of denormalized numbers where the number is so small that the significand has
been reduced to zero.
Examples:
Single:
1.0x2- 128 =0.25x 2- 126 =$00 20 00 00
Double:
1.0x2-1025=0.125x2-1022= $00 02 00 00

00

00

3·393

00

00

I

MC6839

NOT A NUMBER (NAN)
A number containing a NAN indicates that the number is not a valid floating number. NANs can be used to initialize areas in
memory to indicate they have not had a valid floating point number stored in them. They are also created by the MC6839 to indicate
that an operation could not return a valid result.
The format for a NAN has the largest allowable exponent, a non-zero significand, and an undefined sign. As an implementation
feature (not required by the IEEE Proposed Floating Point Standard), the non-zero fraction and undefined sign are further defined:

I d 11111 .... 1111 I t I
d:

t:

I

0=
1=
0=
1=

This
This
This
This

NAN
NAN
NAN
NAN

has
has
will
will

operation address

00 ... 0000

never entered into an operation with another NAN.
entered into an operation with other NANs.
not necessarily cause an invalid operation trap when operated upon.
cause an invalid operation trap when operated upon (trapping NAN).

Operation address:
The 16 bits, immediately to the right of the t bit, contain the address of the instruction immediately following the call to the FP
package of the operation that caused the NAN to be created. If d (double NAN) is also set, the address is arbitrarily one of the
addresses in the two or more offending NANs.

SPECIAL VALUES (EXTENDED FORMAT)
ZERO
Zero is represented by a number with the smallest unbiased exponent and a zero significand:

I s 1 100.... 0000 I

o

INFINITY
Infinity has the maximum unbiased exponent and a zero significand:

I s 1011111 .... 111

o

DENORMALIZED NUMBERS
Denormalized numbers have the smallest unbiased exponent and a non-zero significand:

I s 1 100..... 000 10 .

non-zero

The exponent of denormalized extended and internal numbers is interpreted as having the exponent value 1 greater than the
smallest unbiased exponent value. Thus, a denormalized number has the exponent - 16384, but has the value:
(-1)sx2-16383xO.f
Example:
10x2-16387=0625x2- 16383=$40

00

08

00

00

00

00

00

00

00

NANs
NANs have the largest unbiased exponent and a non-zero significand. The operation addresses "t" and "d" are implementation
features and are the same as for single- and double-formats.

I I
d

011 .... 1111

I I I
0

t

operation addr.

I 00000000

The operation address always appears in the 16 bits immediately to the right of the t bit.

3-394

MC6839

UNNORMALZIED NUMBERS
Unnormalized numbers occur only in extended or internal format, Unnormalized numbers have an exponent greater than the
minimum in the extended format (i,e., they are not denormalized or normal zero) but the explicit leading bit is a zero. If the significand is zero, this is an un normalized zero, Even though un normalized numbers and denormalized numbers are handled similarly in
most cases, they should not be confused, Denormalized numbers are numbers that are very small - have minimum exponent and hence have lost some bits of significance, Unnormalized numbers are not necessarily small (the exponent may be large or small)
but the significand has lost some bits of significance, hence, the explicit bit and possibly some of the bits to the right of the explicit
bit are zero,
I

s

I

significand

> 100",000 10

Note that unnormalized numbers cannot be represented - and hence cannot exist - for single- and double-formats, Unnormalized numbers can only be created when denormalized numbers in single- or double-format are represented in extended or internal formats,
E~ample:

0625x2 2 (unnorm,)=$00

02

08

00

00

00

00

00

00

00

MC6839 CALLING SEQUENCE AND OPCODE REFERENCE TABLE
Function

Opcode

Register Calling Sequence

Stack Calling Sequence 1

FADD
FSUB
FMUL
FDIV

$00
$02
$04
$06

U-Addr of Argument #1
Y-Addr of Argument #2
D-Addr of FPCB
X - Addr of Result
LBSR FPREG
FCB 

Push Argument #1
Push Argument #2
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull Result

FREM
FSQRT
FINT
FFIXS
FFIXD
FAB
FNEG
FFLTS
FFLTD

$08
$12
$14
$16
$18
$1 E
$20
$24
$26

Y - Addr. of Argument
0 - Addr, of FPCB
X - Addr. of Result
LBSR FPREG
FCB 

Push Argument
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull Result

FCMP
FTCMP
FPCMP
FTPCMP

$8A
$CC
$8E
$00

U - Addr. of Argument #1
Y - Addr. of Argument #2
D-Addr, of FPCB
X - Parameter Word
LBSR FPREG
FCB 

Push Argument #1
Push Argument #2
Push Parameter Word
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull Result lif predicate compare)

NOTE Result returned In the CC register, For
predicate compares the Z-Bit is set if predicate
is affirmed cleared If disaffirmed

NOTE: Result returned in the CC register for
regular compares. For predicate compares a one
byte result is returned on the top of the stack,
The result is zero if affirmed and - 1($FF) if
disaffirmed,

FMOV

$9A

U - Precision Parameter Word
Y-Addr. of Argument
D-Addr, of FPCB
X-Addr. of Result
LBSR FPREG
FCB 

Push Argument
Push PreciSion Parameter Word
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull Result

BIN DEC

$lC

U - k 1# of digits in result)
Y-Addr, of Argument
D-Addr. of FPCB
X - Addr, of Decimal Result
LBSR FPREG
FCB 

Push Argument
Push k
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull BCD String

DECBIN

$22

U - Addr. of BCD Input String
D-Addr, of FPCB
X - Addr, of Binary Result
LBSR FPREG
FCB 

Push Addr, of BCD Input String
Push Addr, of FPCB
LBSR FPSTAK
FCB 
Pull Binary Result

1All arguments are pushed on the stack least-significant bytes first so that the high-order byte is always pushed last and resides in the
lowest address,
Entry points to the MC6839 are defined as follows:
FPREG = ROM start + $30
FPST AK = ROM start + $3F

3-395

I

MC6839

MC6839 EXECUTION TIMES
Time in JLs Using 2 MHz 6809

Function
FADD

FSUB
FMUL
FDIV

I

FABS
DECBIN
(time depe~ds on magnitude
of input)
BINDEC
(time depends on # significant
digits requested)

Single
Precision
1200-3300
t= 12oo+40(A)+50(N)
where:
A = # shifts to align operands
N = # shifts to normalize result
ADD+11
1400-1600
t= 2700+60(0)
where:
0=# of quotient bits which are
are a"540
8500-14,000

35,000 - 48,000

3·396

Double
Precision
1500-3700
t= 15OO+40(A) + 5O(N)

Extended
Precision
1100-3800
t= 11oo+40(A) + 50(N)

ADD+11
4100-4300
t = 5000+ 60(0)

ADD + 11
4600-4800
5= 6500+ 60(0)

750

650

8500 - 23,000

-

('7,000-85,000

-

®

MOTOROLA

MC6840

PROGRAMMABLE TIMER MODULE (PTM)
The MC6840 is a programmable subsystem component of the M6800
family designed to provide variable system time intervals.
The MC6840 has three 16-bit binary counters, three corresponding
control registers, and a status register. These counters are under software control and may be used to cause system interrupts and/ or
generate output signals. The MC6840 may be utilized for such tasks as
frequency measurements, event counting, interval measuring, and
similar tasks. The device may be used for square wave generation,
gated delay signals, single pulses of controlled duration, and pulse
width modulation as well as system interrupts.

MOS
(N-CHANNEL, SILICON-GATE
DEPLETION LOAD)

PROGRAMMABLE TIMER

•
•
•
•

Operates from a Single 5 Volt Power Supply
Fully TTL Compatible
Single System Clock Required (Enable)
Selectable Prescaler on Timer 3 Capable of 4 MHz for the MC6840,
6 MHz for the MC68A40 and 8 MHz for the MC68B40
• Programmable Interrupts (IRO) Output to MPU
• Readable Down Counter Indicates Counts to Go Until Time-Out
• Selectable Gating for Frequency or Pulse-Width Comparison
• RESET Input
• Three Asynchronous External Clock and Gate/Trigger Inputs
Internally Synchronized
• Three Maskable Outputs

L SUFFIX
CERAMIC PACKAGE
CASE 719

PSUFFIX
PLASTIC PACKAGE
CASE 710

. -

~

SSUFFIX

CERDIP PACKAGE
CASE 733

PIN ASSIGNMENT

ORDERING INFORMATION
Package
Type
Ceramic
Side Brazed
L Suffix

Plastic
P Suffix

Cerdip
S Suffix

Frequency
1.0
1.0
1.5
1.5
2.0

MHz
MHz
MHz
MHz
MHz

1.0
1.0
1.5
1.5
2.0

MHz
MHz
MHz
MHz
MHz

1.0
1.0
1.5
1.5
2.0

MHz
MHz
MHz
MHz
MHz

Temperature
Range

Order
Number

O°C to 70°C
-40°C to +85°C
O°C to 70°C
-40°C to +85°C
O°C to 70°C

MC6840L
MC6840CL
MC68A40L
MC68A40CL
MC68B40L

O°C to 70°C
-40°C to +85°C
O°C to 70°C
-40°C to +85°C
O°C to 70°C
O°C to 70°C
-40°C to +85°C
O°C to 70°C
- 40°C to + 85°C
O°C to 70°C

MC6840P
MC6840CP
MC68A40P
MC68A40CP
MC68B40P
MC6840S
MC6840CS
MC68A40S
MC68A40CS
MC68B40S

VSS

Ci

G2

01

02

Gi

C2
G3

Dl

DO

03

D2

C3

D3

RESET

D4

IRQ

D5

RSO

10

D6

RSl

11

D7

RS2

12

R/W

Vce

3-397

CS1
14

CSO

I

MC6840

BLOCK DIAGRAM
E (Enable)

I

G3

E3

03

G2

E2

02

Gi

Ei

01

POWER CONSIDERATIONS

The average chip-junction temperature, T J, in DC can be obtained from:
TJ=TA+(POeOJA)
Where:
T A=- Ambient Temperature, DC
OJA=- Package Thermal Resistance, Junction-to-Ambient, DC/W

(1)

Po =- PINT + PPORT
PINT=- ICC x VCC, Watts - Chip Internal Power
PPORT=- Port Power Dissipation, Watts - User Determined
For most applications PPORT ~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J (if PPORT is neglected) is:
Po = K -;- (T J + 273 D C)
(2)
Solving equations 1 and 2 for K gives:
K = POe(T A + 273 DC) + OJA e Po 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at equilibrium)
for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1) and (2) iteratively for any
value of T A.

3-398

MC6840

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

V

Input Voltage

Yin

-03to+7.0

V

Operating Temperature Range - TL to TH
MC6840, MC68A40, MC68B40
M C6840C, M C68A40C

TA

o to + 70
-40 to +85

°c

Storage Temperature Range

T stg

- 55 to + 150

°c

Symbol

Value

Unit

()JA

65
115

°C/W

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields, however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this hlghImpedance circuit. For proper operation it is
recommended that Yin and V out be constrained to the range VSS:5(Vin or Voutl
:5VCC Reliability of operation IS enhanced If
unused Inputs are tied to an appropriate logiC
voltage level (e.g., either VSS or VCCI

THERMAL CHARACTERISTICS
Characteristic

Thermal Resistance
Cerdip
Plastic
Ceramic

60

DC ELECTRICAL CHARACTERISTICS (VCC=5.0 Vdc +5%,
VSS=O, TA=TL to TH unless otherwise noted I
Symbol

Min

Typ

Max

Unit

Input High Voltage

VIH

-

VIL

-

lin

-

1.0

VCC
VSS+0.8
2.5

V

Input Low Voltage

VSS + 20
VSS-0.3

p.A

DO-D7

ITSI

-

2.0

10

p.A

DO-D7
Other Outputs

VOH

VSS + 2.4
VSS + 2.4

-

-

V

TAO, DO-D7

VOL

V
p.A

Characteristic

Input Leakage Current (Vin = 0 to 5.25 VI
Hi-Z (Off Statel Input Current (Vin = 0.5 to 2.4 VI
Output High Voltage
"Load = - 205 p.AI
II Load = - 200 p.AI
Output Low Voltage
"Load = 1.6 mAl
II Load = 3.2 mAl
Output Leakage Current (Off Statel (VOH = 2.4 VI

-

-

01-03

-

-

IRQ

ILOH

-

1.0

VSS+O.4
VSS+O.4
10

PINT

-

470

700

mW

Cin

-

-

12.5
7.5

pF

Cout

-

-

5.0
10

pF

-

Internal Power Dissipation (Measured at T A = TLI
Input Capacitance
(Vin = 0, T A = 25°C, f= 1.0 MHzl

DO-D7
All Others

Output Capacitance
(Vin = 0, T A = 25°C, f = 1.0 MHzl

V

-

IRQ
01 02 03

AC OPERATING CHARACTERISTICS (See Figures 2-71
Characteristic

Symbol

MC68A40

MC6840

MC68B40

Min

Max

Min

Max

Min

Max

Unit

Input Rise and Fall Times
(Figures 4 and 51 C, G, and RESET

tr,tf

-

10'

-

0.666'

-

0.500'

P.s

Input Pulse Width Low (Figure 41
(Asynchronous Inputl
C, G, and RESET

PWL

tcycE + tsu + thd

-

tcycE + tsu + thd

-

tcycE: + tsu + thd

-

ns

Input Pulse Width High (Figure 51
(Asynchronous Inputl C, G

PWH

IcycE + lsu + thd

-

tcycE + tsu + lhd

-

tcycE + tsu + thd

-

ns

Input Setup Time (Figure 61
(Synchronous Inputl
C, G, and RESET

tsu

200

-

120

-

75

-

ns

Input Hold Time (Figure 61
(Synchronous Input I
C, G, and RESET

thd

50

-

50

-

50

-

ns

t sync

250

-

200

-

175

-

ns

PWL, PWH

120

-

80

-

60

-

ns

tco
tcm
tcmos

700
450
2.0

-

460
450
1.35

-

-

-

-

340
340
1.0

ns
ns
p's

-

1.2

-

0.9

-

0.7

p'S

Input Synchronization Time (Figure 91
C3 (+ 8 Prescaler Mode Onlyl
Input Pulse Width
C3 (+ 8 Prescaler Mode Onlyl
Output Delay, 01-03 (Figure 71
TTL
(VOH=2.4 V, Load BI
(VOH = 2.4 V, Load DI
MOS
CMOS
(VOH = 0.7 VDD, Load DI
Interrupt Release Time
't r and tf:5 tcycE

lJR

-

-

-

I

MC6840

BUS TIMING CHARACTERISTICS ISee Notes 1 2 and 3)
Ident.
Number
1

Characteristic

Symbol

Cycle Time

2

Pulse Width, E Low
Pulse Width, E High

3
4
9
13

MC6840
Min Max

MC68A40
Min Max

MC68B40
Min Max

Unit

tCYC
PWEL

1.0

10

0.67

10

0.5

430

9500

2S0

9500

210

10
9500

9500
25

2S0

9500

220

9500

ns

-

25

-

ns

-

10

-

60
60
10

-

20
-

40
40

-

ns
ns

10

-

ns

20
10

50"

20

50"

ns

-

10

ns

290

-

lS0

-

150

-

SO

60

-

PWEH

450

Clock Rise and Fall Time
Address Hold Time

tr,tf

Address Setup Time Before E

tAS
tcs

10
SO
SO
10
20
10

tAH

14
15

Chip Select Setup Time Before E
Chip Select Hold Time

lS

Read Data Hold Time

tDHR

21

Write Data Hold Time

30
31

Peripheral Output Data Delay Time
Peripheral Input Data Setup Time

tDHW
tDDR
tDSW

tCH

-

165

50"
-

-

10

"'s
ns

ns

ns
ns

"The data bus output buffers are no longer sourcing or sinking current by tDHR max IHigh Impedance).

I

NOTES:
1. Not all Signals are applicable to every part.
2. Voltage levels shown are VLsO.4 V, VH2:2.4 V, unless otherwise specified.
3. Measurement points shown are O.S V and 2.0 V, unless otherwise specified.

FIGURE 1 - BUS TIMING

E
~------------~3l-----------~~

R/VV,Address--~~~~~~~~~--------~,-rd~--~~--------------------------------~~~~~

(Non-Muxed) ____~~~LX~~~~--------~~~~--~~--------------------------------~_r~~~

cs----+--.,.------------~

Read Data
Non-Muxed

----+-':IL
D----------------------------------------------~~~---------<~I~--~--_i~--~

Write Data -----'---.....
MPU Wrrte Data Non-Muxed
Muxed
D------------------------------------------------1~~---~---~~I----------~--~

FIGURE2 - INPUT PULSE WIDTH LOW

FIGURE 3 - INPUT PULSE WIDTH HIGH

C,-C3

C1-C3

Gl-G3

01-<33
RESET

3·400

MC6840

FIGURE 4 - INPUT SETUP AND HOLD TIMES

FIGURE5 - OUTPUT DELAY

, if iL'~ ::~'---C"1T3,

~>t~

G 1-G3,

01-03

RESET

-----

* tcmos

= 0.7 X Vee

FIGURE 6 - IRQ RELEASE TIME

E~~_ _ _ __

~"RJFIGURE 7 -

a INPUT SYNCHRONIZATION TIME (+8 PRESCALER MODE ONLY)

~ 14

Cycle N

'"' "J

I

;=

Cycle N+ 1

;-

~

jt'y,,~

C3
I
Transitions Processed During N

FIGURE 8 -

Transitions Processed During N + 1 TX

BUS TIMING TEST LOADS
Load B

Load A
(00-07)

Load C

(01.02.03)

(IRQ Only)

(TTL Load)
5.0 V

Vee of device under test
RL

MMD6150

T est Po in t

o--......._~---1<___--+

=

1.25 k

MMD6150
or Equiv.

or Equiv.

11.7 k

40 pF
MMD 7000

MMD7000
or Equiv.

or Equiv.

5.0 V

T." 0"0'

=-iI"
I

'00

0'

Load 0

(01.02.03)
(CMOS Load)
(MOS)
Testpo;nt

1

1""

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.

3-401

MC6840

DEVICE OPERATION

I

The MC6840 is part of the M6800 microprocessor family
and is fully bus compatible with M6800 systems. The three
timers in the MC6840 operate independently and in several
distinct modes to fit a wide variety of measurement and synthesis applications.
The MC6840 is an integrated set of three distinct
counter/timers. It consists of three 16-bit data latches,
three 16-bit counters (clocked independently), and the
comparison and enable circuitry necessary to implement
various measurement and synthesis functions. In addition, it
contains interrupt drivers to alert the processor that a particular function has been completed.
In a typical application, a timer will be loaded by first storing two bytes of data into an associated Counter Latch. This
data is then transferred into the counter via a Counter Initialization cycle. If the counter is enabled, the counter
decrements on each subsequent clock period which may be
an external clock, or Enable (E) until one of several predetermined conditions causes it to halt or recycle. The timers are
thus programmable, cyclic in nature, controllable by external
inputs or the MPU program, and accessible by the MPU at
any time.
BUS INTERFACE
The Programmable Timer Module (PTM) interfaces to the
M6800 Bus with an 8-bit bidirectional data bus, two Chip
Select lines, a Read/Write line, a clock (Enable) line, and Interrupt Request line, an external Reset line, and three
Register select lines. VMA should be utilized in conjunction
with an MPU address line into a Chip Select of the PTM
when using the MC6800/6802/6808.
BIDIRECTIONAL DATA (00-07) - The bidirectional data
lines (00-07) allow the transfer of data between the MPU
and PTM. The data bus output drivers are three-state
devices which remain in the high-impedance (off) state except when the MPU performs a PTM read operation
(Read/Write and Enable lines high and PTM Chip Selects activated).
CHIP SELECT (CSO, CS1) - These two Signals are used
to activate the Data Bus interface and allow transfer of data
from the PTM. With CSO = 0 and CS 1 = 1, the device is
selected and data transfer will occur.
READ/WRITE (R/W) - This signal is generated by the
MPU to control the direction of data transfer on the Data
Bus. With the PTM selected, a low state on the PTM R/W
line enables the input buffers and data is transferred from the
MPU to the PTM on the trailing edge of the E (Enable) clock.
Alternately, (under the same conditions) R/W.= 1 and
Enable high allows data in the PTM to be read by the MPU.
ENABLE (E CLOCK) - The E clock signal synchronizes
data transfer between the MPU and the PTM. It also performs an equivalent synchronization function on the external
clock, reset, and gate inputs of the PTM.
INTERRUPT REQUEST (IRQ) - The active low Interrupt
Request signal is normally tied directly (or through priority interrupt circuitry) to the IRQ input of the MPU. This is an

"open drain" output (no load device on the chip) which permits other similar interrupt request lines to be tied together in
a wire-OR configuration.
The IRQ line is activated if, and only if, the Composite Interrupt Flag (Bit 7 of the Internal Status Register) is asserted.
The conditions under which the"'iRO line is activated are
discussed in conjunction with the Status Register.
RESET - A low level at this input is clocked into the PTM
by the E (Enable) input. Two Enable pulses are required to
synchronize and process the signal. The PTM then
recognizes the active "low" or inactive "high" on the third
Enable pulse. If the RESET signal is asynchronous, an additional Enable period is required if setup times are not met.
The RESET input must be stable High/Low for the minimum
time stated in the AC Operating Characteristics.
Recognition of a low level at this input by the PTM causes
the following action to occur:
a. All counter latches are preset to their maximum count
values.
b. All Control Register bits are cleared with the exception
of CR10 (internal reset bit) which is set.
c. All counters are preset to the contents of the latches.
d. All counter outputs are reset and all counter clocks are
disabled.
e. All Status Register bits (interrupt flags) are cleared.
REGISTER SELECT LINES (RSO, RS1, RS2) - These inputs are used in conjunction with the R/W line to select the
internal registers, counters and latches as shown in Table 1.
NOTE
The PTM is accessed via MPU Load and Store operations
in much the same manner as a memory device. The instructions available with the M6800 family of MPUs which perform read-modify-write operations on memory should not be
used when the PTM is accessed. These instructions actually
fetch a byte from memory, perform an operation, then
restore it to the same address location. Since the PTM uses
the R/W line as an additional register select input, the
modified data will not be restored to the same register if
these instructions are used.
CONTROL REGISTER
Each timer in the MC6840 has a corresponding write-only
Control Register. Control Register #2 has a unique address
space (R SO = 1, RS = 0, RS2 = 0) and therefore may be written into at any time. The remaining Control Registers (#1 and
#3) share the Address Space selected by a logiC zero on all
Register Select inputs.
CR20 - The least significant bit of Control Register #2
(CR20) is used as an additional addressing bit for Control
Registers #1 and #3. Thus, with all Register selects and R/W
inputs at logic zero, Control Register #1 will be written into if
CR20 is a logic one. Under the same conditions, Control
Register #3 can also be written into after a RESET low condition has occurred, since all control register bits (except
CR10) are cleared. Therefore, one may write in the sequence
CR3, CR2, CR1.

3-402

MC6840

TABLE 1 - REGISTER SELECTION
Register
Select Inputs

Operations

RS2

RS1

RSO

0

0

0

0

0

1

Write Control Register #2

0

1

0

Write MSB Buffer Register

Read Timer #1 Counter

0

1

1

Write Timer #1 Latches

Read LSB Buffer Register

1

0

0

Write MSB Buffer Register

Read Timer #2 Counter

1

0

1

Write Timer #2 Latches

Read LSB Buffer Register

1

1

0

Write MSB Buffer Register

Read Timer #3 Counter

1

1

1

Write Timer #3 Latches

Read LSB Buffer Register

R/W = 0
Write Control Register #3

CR20

Write Control Register #1

=

1

CR10 - The least significant bit of Control Register #1 is
used as an Internal Reset bit. When this bit is a logic zero, all
timers are allowed to operate in the modes prescribed by the
remaining bits of the control registers. Writing a "one" into
CR10 causes all counters to be preset with the contents of
the corresponding counter latches, all counter clocks to be
disabled, and the timer outputs and interrupt flags (Status
Register) to be reset. Counter Latches and Control Registers
are undisturbed by an Internal Reset and may be written into
regardless of the state of CR 10.
The least signifcant bit of Control Register #3 is used as a
selector for a-+-8 prescaler which is available with Timer #3
only. The prescaler, if selected, is effectively placed between
TABLE 2 -

CRX7*

o

R/W=l

CR20 = 0

No Operation
Read Status Register

the clock input circuitry and the input to Counter #3. It can
therefore be used with either the internal Clock (Enable) or an
external clock source.

NOTE
When initializing Timer 3 into the divide-by-eight mode on
consecutive E-cycles (i.e., with DMAI. Control Register 3
must be initialized before Timer Latch #3 to insure proper
timer initialization.
CR30 - The functions depicted in the foregoing discussions are tabulated in Table 2 for ease of reference.

CONTROL REGISTER BITS

Timer #X Counter Output Enable
TX Output masked on output OX
TX Output enabled on output OX

CRX6

o

Timer #X Interrupt Enable
Interrupt Flag masked on IRQ
Interrupt Flag enabled to IRQ

Control Register X

Timer #X Counting Mode Control
TX configured for normal (16-blt) counting mode
TX configured for dual 8-bit counting mode

CRX1

o

CR 10 Internal Reset Bit
All timers allowed to operate
All timers held in reset state
X=l

Timer #X Clock Source
TX uses external Clock source on CX input
TX uses Enable clock

CR20 Control Register Address Bit
CR#3 may be written
1 CR#l may be written
X=2

o

3-403

CR30 Timer #3 Clock Control
T3 Clock is not prescaled
T3 Clock is prescaled b + 8
X=3

o

I

MC6840

An interrupt flag is cleared by a Timer Reset condition,
i.e., External RESET=O or Internal Reset Bit (CR1Q)=1. It
will also be cleared by a Read Timer Counter Command provided that the Status Register has previously been read while
the interrupt flag was set. This condition on the Read Status
Register-Read Timer Counter (RS-RT) sequence is designed
to prevent missing interrupts which might occur after the
status register is read, but prior to reading the Timer
Counter.
An Individual Interrupt Flag is also cleared by a Write
Timer Latches (W) command or a Counter Initialization (CI)
sequence, provided that W or CI affects the Timer corresponding to the individual Interrupt Flag.

Control Register Bits CR10, CR20, and CR30 are unique in
that each selects a different function. The remaining bits (1
through 7) of each Control Register select common functions, with a particular Control Register affecting only its corresponding timer.

CRX1 - Bit 1 of Control Register #1 (CR11) selects
whether an internal or external clock source is to be used
with Timer #1. Similarly, CR21 selects the clock source for
Timer #2, and CR31 performs this function for Timer #3. The
function of each bit of Control Register "X" can therefore be
defined as shown in the remaining section of Table 2.

I

CRX2 - Control Register Bit 2 selects whether the binary
information contained in the Counter Latches (and subsequently loaded into the counter) is to be treated as a single
16-bit word or two 8-bit bytes. In the single 16-bit Counter
Mode (CRX2=Q) the counter will decrement to zero after
N + 1 enabled (G = Q) clock periods, where N is defined as the
16-bit number in the Counter Latches. With CRX2= 1, a
similar Time Out will occur after (L+·1).(M+1) enabled
clock periods, where Land M, respectively, refer to the LSB
and MSB bytes iOl the Counter Latches.

COUNTER LATCH INITIALIZATION

Each of the three independent timers consists of a 16-bit
addressable counter and a 16-bit addressable latch. The
counters are preset to the binary numbers stored in the latches. Counter initialization results in the transfer of the latch
contents to the counter. See notes in Figure 10 regarding the
binary number L or M placed into the Latches and their relationship to the output waveforms and counter Time-Outs.
Since the PTM data bus is 8-bits wide and the counters are
16-bits wide, a temporary register (MSB Buffer Register) is
provided. This "write only" register is for the MostSignificant Byte of the desired latch data. Three addresses
are provided for the MSB Buffer Register (as indicated in
Table 1), but they all lead to the same Buffer. Data from the
MSB Buffer will automatically be transferred into the MostSignificant Byte of Timer #X when a Write Timer #X Latches
Command is performed. So it can be seen that the MC6840
has been designed to allow transfer of two bytes of data into
the counter latches provided that the M SB is transferred
first. The storage order must be observed to ensure proper
latch operation.
In many applications, the source of the data will be an
M6800 Family MPU. It should be noted that the 16-bit store
operations of the M6800 family microprocessors (STS and
STX) transfer data in the order required by the PTM. A Store
Index Register Instruction, for example, results in the MSB
of the X register being transferred to the selected address,
then the LSB of the X register being written into the next
higher location. Thus, either the index register or stack
pointer may be transferred directly into a selected counter
latch with a single instruction.
A logic zero at the RESET input also initializes the counter
latches. In this case, all latches will assume a maximum
count of 65,53510. It is important to note that an Internal

CRX3-CRX7 - Control Register Bits 3, 4, and 5 are explained in detail in the Timer Operating Mode section. Bit 6 is
an interrupt mask bit which will be explained more fully in
conjunction with the Status Register, and bit 7 is used to
enable the corresponding Timer Output. A summary of the
control register programming modes is shown in Table 3.

STATUS REGISTER/INTERRUPT FLAGS

The MC6840 has an internal Read-Only Status Register
which contains four Interrupt Flags. (The remaining four bits
of the register are not used, and defaults to zeros when being read.) Bits 0, 1, and 2 are assigned to Timers 1,2, and 3,
respectively, as individual flag bits, while Bit 7 is a Composite
Interrupt Flag. This flag bit will be asserted if any of the individual flag bits is set while Bit 6 of the corresponding Control Register is at a logic one. The conditions for asserting
the composite Interrupt Flag bit can therefore be expressed
as:
INT= 11.CR16+ 12.CR26+ 13.CR36
where INT= Composite Interrupt Flag (Bit 7)
11 = Timer #1 Interrupt Flag (Bit Q)
12 = Timer #2 Interrupt Flag (Bit 1)
13= Timer #3 Interrupt Flag (Bit 2)

CRX4
CRX3

CRX5

o

0

o

TABLE 3 -

PTM OPERATING MODE SELECTION

0 Continuous Operating Mode: Gate I or Write to Latches or Reset Causes Counter Initialization
0 Frequency Comparison Mode: Interrupt If Gate

LJt is< Counter Time Out

o Continuous Operating Mode: Gate I or Reset Causes Counter Initialization
o Pulse Width Comparison Mode: Interrupt if Gate L--.J is< Counter Time Out
o
1 0

o

1 Single Shot Mode: Gate I or Write to Latches or Reset Causes Counter Initialization

Ln'

Frequency Comparison Mode: Interrupt If Gate
is> Counter Time Out
Single Shot Mode: Gate I or Reset Causes Counter Initialization
Pulse Width Comparison Mode: Interrupt If Gate ~ is> Counter Time Out

3-404

MC6840

CLOCK INPUT C3 (+ 8 PRESCALER MODE) - External
clock input C3 represents a special case when Timer #3 is
programmed to utilize its optional +8 prescaler mode.
The divide-by-8 prescaler contains an asynchronous ripple
counter; thus, input setup (ts u ) and hold times (thd) do not
apply. As long as minimum input pulse widths are maintained, the counter will recognize and process all input clock
(0) transitions. However, in order to guarantee that a clock
transition is processed during the current E cycle, a certain
amount of synchronization time (t sync ) is required between
the C3 transition and the falling edge of Enable (see Figure
9). If the synchronization time requirement is not met, it is
possible that the C3 transition will not be processed until the
following E cycle.
The maximum input frequency and allowable duty cycles
for the + 8 prescaler mode are specified under the AC
Operating Characteristics. Internally, the + 8 prescaler output is treated in the same manner as the previously discussed
clock inputs.

Reset (Bit zero of Control Register 1 Set) has no effect on
the counter latches.
COUNTER INITIALIZATION
Counter Initialization is defined as the transfer of data from
the latches to the counter with subsequent clearing of the Individual Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition
(RESET=O or CR1O= 1) is recognized. It can also occur depending on Timer Mode - with a Write Timer Latches
command or recognition of a negative transition of the Gate
input.
Counter recycling or re-initialization occurs when a
negative transition of the clock input is recognized after the
counter has reached an all-zero state. In this case, data is
transferred from the Latches to the Counter.
ASYNCHRONOUS INPUT/OUTPUT LINES
Each of the three timers within the PTM has external clock
and gate inputs as well asa counter output line. The inputs
are high-impedance, TTL-compatible lines and ouputs are
capable of driving two standard TTL loads.

GATE INPUTS (G1, G2, G3) - Input pins G1, G2, and G3
accept asynchronous TTL-compatible signals which are used
as triggers or clock gating functions to Timers 1, 2, and 3,
respectively. The gating inputs are clocked into the PTM by
the E (enable) clock in the same manner as the previously
discussed clock inputs. That is, a Gate transition is recognized by the PTM on the fourth Enable pulse (provided setup
and hold time requirements are met), and the high or low
levels of the Gate input must be stable for at least one system
clock period plus the sum of setup and hold times. All
references to G transition in this document relate to internal
recognition of the input transition.
The Gate inputs of all timers directly affect the internal
16-bit counter. The operation of G3 is therefore independent
of the + 8 prescaler selection.

CLOCK INPUTS (C1, C2, and C3) - Input pins C1, C2,
and C3 will accept asynchronous TTL voltage level signals to
decrement Timers 1, 2, and 3, respectively. The high and low
levels of the external clocks must each be stable for at least
one system clock period plus the sum of the setup and hold
times for the clock inputs. The asynchronous clock rate can
vary from dc to the limit imposed by the Enable Clock Setup,
and Hold times.
The external clock inputs are clocked in by Enable pulses.
Three Enable periods are used to synchronize and process
the external clock. The fourth Enable pulse decrements the
internal counter. This does not affect the input frequency, it
merely creates a delay between a clock input transition and
internal recognition of that transition by the PTM. All
references to C inputs in this document relate to internal
recognition of the input transition. Note that a clock high or
low level which does not meet setup and hold time specifications may require an additional Enable pulse for recognition.
When observing recurring events, a lack of synchronization
will result in "jitter" being observed on the output of the
PTM when using asynchronous Clocks and gate input
signals. There are two types of jitter. "System jitter" is the
result of the input signals being out of synchronization with
Enable, permitting signals with marginal setup and hold time
to be recognized by either the bit time nearest the input transition or the subsequent bit time.
"Input jitter" can be as great as the time between input
signal negative going transitions plus the system jitter, if the
first transition is recognized during one system cycle, and
not recognized the next cycle, or vice versa. See Figure 9.
FIGURE 9 -

INPUT JITIER

Enable~~
Input~i--

ReCOg~__ \ -

Input
Either Here

or Here

---j

r-- System

TIMER OUTPUTS (01, 02, 03) - Timer outputs 01, 02,
and 03 are capable of driving up to two TTL loads and produce a defined output waveform for either Continuous or
Single-Shot Timer modes. Output waveform definition is accomplished by selecting either Single 16-bit or Dual 8-bit
operating modes. The Single 16-bit mode will produce a
square-wave output in the continuous mode and a single
pulse in the single-shot mode. The Dual 8-bit mode will produce a variable duty cycle pulse in both the continuous and
single-shot timer modes. One bit of each Control Register
(CRX7) is used to enable the corresponding output. If this bit
is cleared, the output will remain low (VOL) regardless of the
operating mode. If it is cleared while the output is high the
output will go low during the first enable cycle following a
write to the Control Register.
The Continuous and Single-Shot Timer Modes are the
only ones for which output response is defined in this data
sheet. Refer to the Programmable Timer Fundamentals and
Applications manual for a discussion of the output signals in
other modes. Signals appear at the outputs (unless
CRX7 = 0) during Frequency and Pulse Width comparison
modes, but the actual waveform is not predictable in typical
applications.

I~~J~ Bit Time

Output _ _ _ _ _ _ _ _ _ _ _~\~- - -

Jitter

3-405

I

MC6840

TIMER OPERATING MODES

that the timer output is enabled (CRX7= 1), either a square
wave or a variable duty cycle waveform will be generated at
the Timer Output, OX. The type of output is selected via
Control Register Bit 2.
Either a Timer Reset (CRlO= 1 or External Reset=Q) condition or internal recognition of negative transition of the
Gate input results in Counter Initialization. A Write Timer
latches command can be selected as a Counter Initialization
signal by clearing CRX4.
The counter is enabled by an absence of a Timer Reset
condition and a logic zero at the Gate input. In the 16-bit
mode, the counter will decrement on the first clock cycle
during or after the counter initialization cycle. It continues to
decrement on each clock signal so long as G remains low and
no reset condition exists. A Counter Time Out (the first clock
after all counter bits = 0) results in the Individual Interrupt
Flag being set and reinitialization of the counter .
In the Dual8-bit mode (CRX2= 1) [refer to the example in
Figure 10 and Tables 5 and 6] the MSB decrements once for
every full countdown of the LS B + 1. When the LS B = 0, the
MSB is unchanged; on the next clock pulse the LSB is reset
to the count in the LSB Latches, and the MSB is
decremented by 1 (one). The output, if enabled, remains low
during and after initialization and will remain low until the
counter MSB is all zeroes. The output will go high at the
beginning of the next clock pulse. The output remains high
until both the LSB and MSB of the counter are all zeroes. At
the beginning of the next clock pulse the defined Time Out
(TO) will occur and the output will go low. In the Dual 8-bit
mode the period of the output of the example in Figure 12
would span 20 clock pulses as opposed to 1546 clock pulses
using the normal 16-bit mode.
A special time-out condition exists for the dual 8-bit mode
(CRX2= 1) if L=O. In this case, the counter will revert to a
mode similar to the single 16-bit mode, except Time Out occurs after M + 1* clock pulses. The output, if enabled, goes
low during the Counter Initialization cycle and reverses state
at each Time Out. The counter remains cyclical (is reinitialized at each Time Out) and the Individual Interrupt Flag
is set when Time Out occurs. If M = L = 0, the internal
counters do not change, but the output toggles at a rate of
Yz the clock frequency.

The MC6840 has been designed to operate effectively in a
wide variety of applications. This is accomplished by using
three bits of each control register (CRX3, CRX4, and CRX5)
to define different operating modes of the Timers. These
modes are divided into WAVE SYNTHESIS and WAVE
MEASUREMENT modes, and are outlined in Table 4.
TABLE 4 Control Register
CRX3

CRX4

0
0
1
1

I

CRX5

a

OPERATING MODES
Timer Operating Mode

- 0

Continuous

1

Single-Shot

Synthesizer

0

Frequency Comparison

1

Pulse Width Comparison

Measurement

• Defines Additional Timer Function Selection.

One of the WAVE SYNTHESIS modes is the Continuous
Operating mode, which is useful for cyclic wave generation.
Either symmetrical or variable duty-cycle waves can be
generated in this mode. The other wave synthesis mode, the
Single-Shot mode, is similar in use to the Continuous
operating mode, however, a single pulse is generated, with a
programmable preset width.
The WAVE MEASUREMENT modes include the Frequency Comparison and Pulse Width Comparison modes which
are used to measure cyclic and singular pulse widths, respectively.
In addition to the four timer modes in Table 4, the remaining control register bit is used to modify counter initialization
and enabling or interrupt conditions.
WAVE SYNTHESIS MODES
CONTINUOUS OPERATING MODE (TABLE 5) - The
continuous mode will synthesize a continuous wave with a
period proportional to the preset number in the particular
timer latches. Any of the timers in the PTM may be programmed to operate in a continuous mode by writing zeroes into
bits 3 and 5 of the corresponding control register. Assuming

TABLE 5 - CONTINUOUS OPERATING MODES
Synthesis Modes

CONTINUOUS MODE
(CRX3 = 0, CRX5 = 0)

Control Register
CRX2

CRX4

Initialization/Output Waveforms
*Timer Output (OX) (CRX7

Counter Initialization

-

0

0

GI+W+R

0

1

GI+R

-

1

0

GI+W+R

1

1

GI+R

= 1)

rIN+lI1TITIN+lI1TITIN+lllTl--j

I

I

I

'0

TO

TO

I

I-VOH
I

VOL

TO

I--IL+lI1M+ll(T)--t-IL+lIIM+lI1TI---i

~-VOH

I
'0

---i ILlIT)

t--

TO

---i

I--vo L

ILiITI
TO

MC6840

FIGURE 10 - TIMER OUTPUT WAVEFORM EXAMPLE
(Continuous Dual 8-Bit Mode Using Internal Enable)
·Time
Out

Example: Contents of MSB = 03 = M
Contents of LSB = 04 = L

1--------

t

M(L + 1) + 1 ---------o-r-o--Algebraic Expression
03(04 + 1) + 1 =
16 Enables
- - - - - - 1 - - - - 2.4 V
- - - - - j \ - - - - 0.4 V

Counter Output

Enable
(System 2)
I

-_-,-1.'--1 + L - .....I ....- - 1 + L~
5 Enable
I
5 Enable
Pulses
I
Pulses
Pulses

I
I
:

1----1 + L

I
I

k - - + - - - - - - - ' - . . . : . I - - - ( M + 11)(

I:

~

I
I 5 Enable
I
I Pulses
I
I
+ 1) - - - - t-+- - - - - - ;

~

I

I

I

I

~~l7,l

V

H

I
I
:

I

Algebraic Expression
(M + 1)(L + 1) = Period
(04 + 1 )(03 + 1) = 20 Enable or
M (L + 1) + 1 = Low portion of period
External Clock Pulses
L = Pulse width
• Preset LSB and MSB to Respective Latches on the negative transition of the Enable
•• Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the Enable

The discussion of the Continuous Mode has assumed that
the application requires an output signal. It should be noted
that the Timer operates in the same manner with the output
disabled (CRX7 = Q). A Read Timer Counter command is
valid regardless of the state of CRX7.

the counter results in the setting of an Individual Interrupt
Flag and re-initialization of the counter.
The second major difference between the Single-Shot and
Continuous modes is that the internal counter enable is not
dependent on the Gate input level remaining in the low state
for the Single-Shot mode.
Another special condition is introduced in the Single-Shot
mode. If L = M = 0 (Dual 8-bitl or N = 0 (Single 16-bitl, the
output goes low on the first clock received during or after
Counter Initialization. The output remains low until the
Operating Mode is changed or nonzero data is written into
the Counter Latches. Time Outs continue to occur at the end
of each clock period.

SINGLE-SHOT TIMER MODE - This mode is identical to
the Continuous Mode with three exceptions. The first of
these is obvious from the name - the output returns to a
low level after the initial Time Out and remains low until
another Counter Initialization cycle occurs.
As indicated in Table 6, the internal counting mechanism
remains cyclical in the Single-Shot Mode. Each Time Out of

TABLE 6 - SINGLE-SHOT OPERATING MODES
Synthesis Modes

I

SINGLE-SHOT MODE
(CRX3 = 0, CRX7 = 1, CRX5 = 1)

Control Register

Initialization/Output Waveforms

CRX2

CRX4

Counter Initialization

0

0

GI+W+R

0

1
1

1
0

1

GI+R
-

GI+W+R

-

Timer Output (OX)

r-J::IN+lIITI~IN+lllT1l
\--INIITI

L.J

r"

GI+R
to

Symbols are as defined in Table 5.

I

TO

to

TO

--j
.'''M.''''';;j:=''.'''M·'''''l
ILiITI

!l

TO

TO

I

MC6840

The three differences between Single-Shot and Continous
Timer Mode can be summarized as attributes of the SingleShot mode:
1. Output is enabled for only one pulse until it is reinitialized.

generation until a new Counter Initialization cycle has been
completed. When this internal bit is set, a negative transition
of the Gate input starts a new Counter Initialization cycle.
(The condition ofGI~TO is satisfied, since a Time Out
has occurred and no individual Interrupt has been
generated.)
Any of the timers within the PTM may be programmed to
compare the period of a pulse (giving the frequency after
calculations) at the Gate input with the time period requested for Counter Time Out. A negative transition of the
Gate Input enables the counter and starts a Counter Initialization cycle - provided that other conditions, as noted
in Table 8, are satisfied. The counter decrements on each
clock signal recognized during or after Counter Initialization
until an Interrupt is generated, a Write Timer Latches command is issued, or a Timer Reset condition occurs. It can be
seen from Table 8 that an interrupt condition will be
generated if CRX5= 0 and the period of the pulse (single
pulse or measured separately repetitive pulses) at the Gate
input is less than the Counter Time Out period. If CRX5 = 1,
an interrupt is generated if the reverse is true.
Assume now with CRX5= 1 that a Counter Initialization
has occurred and that the Gate input has returned low prior
to Counter Time Out. Since there is no Individual Interrupt
Flag generated, this automatically starts a new Counter Initialization Cycle. The process will continue with frequency
comparison being performed on each Gate input cycle until
the mode is changed, or a cycle is determined to be above
the predetermined limit.

2. Counter Enable is independent of Gate.
3. L = M = 0 or N = 0 disables output.
Aside from these differences, the two modes are identical.

I

WAVE MEASUREMENT MODES
TIME INTERVAL MODES - The Time Interval Modes are
the Frequency (period) Measurement and Pulse Width Comparison Modes, and are provided for those applications
which require more flexibility of interrupt generation and
Counter Initialization. Individual Interrupt Flags are set in
these modes as a function of both Counter Time Out and
transitions of the Gate input. Counter Initialization is also affected by Interrupt Flag status.
A timer's output is normally not used in a Wave Measurement mode, but it is defined. If the output is enabled, it will
operate as follows. During the period between reinitialization
of the timer and the first Time Out, the output will be a
logical zero. If the first Time Out is completed (regardless of
its method of generation), the output will go high. If further
TO's occur, the output will change state at each completion
of a Time-Out.
The counter does operate in either Single 16-bit or Dual
8-bit modes as programmed by CRX2. Other features of the
Wave Measurement Modes are outlined in Table 7.

Pulse Width Comparison Mode (CRX3= 1, CRX4= 1)
This mode is similar to the Frequency Comparison Mode except for a positive, rather than negative, transition of the
Gate input terminates the count. With CRX5= 0, an Individual Interrupt Flag will be generated if the zero level pulse
applied to the Gate input is less than the time period required
for Counter Time Out. With CRX5 = 1, the interrupt is generated when the reverse condition is true.
As can be seen in Table 8, a positive transition of the Gate
input disables the counter. With CRX5= 0, it is therefore
possible to directly obtain the width of any pulse causing an
interrupt. Similar data for other Time Interval Modes and
conditions can be obtained, if two sections of the PTM are
dedicated to the purpose.

Frequency Comparison Or Period Measurement Mode
(CRX3= 1, CRX4=O) - The Frequency Comparison Mode
with CRX5= 1 is straightforward. If Time Out occurs prior to
the first negative transition of the Gate input after a Counter
Initialization cycle, an Individual Interrupt Flag is set. The
counter is disabled, and a Counter Initialization cycle cannot
begin until the interrupt flag is cleared and a negative transition on G is detected.
If CRX5= 0, as shown in Tables 7 and 8, an interrupt is
generated if Gate input returns low prior to a Time Out. If a
Counter Time Out occurs first, the counter is recycled and
continues to decrement. A bit is set within the timer on the
initial Time Out which precludes further individual interrupt

FIGURE 7 -

OUTPUT DELAY

CRX3 = 1
CRX4

CRX5

Application

0

0

Frequency Comparison

Interrupt Generated if Gate Input Period (1fF) is less
than Counter Time Out (TO)

Condition for Setting Individual Interrupt Flag

0

1

Frequency Comparison

Interrupt Generated if Gate Input Period (1fF) is greater
than Counter Time Out (TO)

1

0

Pulse Width Comparison

I nterrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TO)

1

1

Pulse Width Comparison

Interrupt Generated if Gate Input "Down Time" is greater
than Counter Time Out (TO)

3·408

MC6840

TABLE 8 Mode

Bit 3

Bit 4

Frequency

1

0

Comparison

1

0

Pulse Width

1
1

1

Comparison

GI
W
R
N
TO
I

1

Control Reg.
Bit 5
0
1
0
1

FREQUENCY COMPARISON MODE

Counter
Initialization
'Q.I±!'C1:+TO)+R

Counter Enable
Flip-Flop Set (CE)
Gl.W."fj.1

Counter Enable
Flip-Flop Reset (CE)

Interrupt Flag
Set (I)

W+R+I

GI Before TO

GI.I+ R

GI.W·R·I

W+R+I

TO Before GI

GI·I+ R
GI.I+ R

GIW·R·I

W+R+I+G

Gt Before TO

GI·W.R·I

W+R+I+G

TO Before Gt

= Negative transition of Gate input.
= Write Timer Latches Command.
=Timer Reset (CR10=1 or External RESET=Q)
= 16-Bit Number in Counter LatCh.
= Counter Time Out (All Zero Condition)
= Interrupt for a given timer .

• All time intervals shown above assume the Gate (G) and Clock (C) signals are sycnhronlzed to the system clock
(E) with the specified setup and hold time requirements.

3-409

•

®

MOTOROLA

MC6844

MOS

DIRECT MEMORY ACCESS CONTROLLER (DMAC)

•

The MC6844 Direct Memory Access Controller (DMAC) performs the
function of transferring data directly between memory and peripheral
device controllers. It directly transfers the data by controlling the address and data bus in place of an MPU in a bus organized system.
The bus interface of the MC6844 includes select, read/write, interrupt. transfer request/grant, a data port, and an address port which
allow data transfer over an 8-bit bidirectional data bus. The funtional
configuration of the DMAC is programmed via the data bus. The internal structure provides for control and handling of four individual channels, each of which is separately configured. Programmable control
registers provide control for data transfer location and data block
length, individual channel control and transfer mode configuration,
priority of channel servicing, data chaining, and interrupt control.
Status and control lines provide control to peripheral controllers.
The mode of transfer for each channel can be programmed as one of
two single-byte transfer modes or a burst transfer mode.
Typical MC6844 applications are a Floppy Disk Controller (FDC) and
an Advanced Data Link Controller (ADLC) DMA interface.
MC6844 features include:
• Four DMA Channels, Each Having a 16-Bit Address Register and
a 16-Bit Byte Count Register
• 2 M Byte/Sec Maximum Data Transfer Rate
• Selection of Fixed or Rotating Priority Service Control

(N-CHANNEL, SILICON-GATE)

DIRECT MEMORY
ACCESS CONTROLLER
(DMAC)

L SUFFIX
CERAMIC PACKAGE
CASE 715

;mMhfrlh

i4ffM

S SUFFIX

CERD" ""AGE

~
~VVU"'.

CASE 734

PSUFFIX

PLASTIC PACKAGE
CASE 711

• Separate Control Bits for Each Channel
• Data Chain Function
• Address Increment or Decrement Update

PIN ASSIGNMENT

• Programmable Interrupts and DMA End to Peripheral Controllers
VSS
CS/Tx AKB
R/W
FIGURE 1 - M6800 MICROCOMPUTER FAMtL Y
BLOCK DIAGRAM

Address
Bus

Data
Bus

3-410

DGRNT

AO

DROl

Al

DR02

A2

Tx AKA

A3

Tx STB

A4

IRO/DEND

A5

Tx ROO

A6

Tx ROl

A7

Tx R02

A8

Tx R03

A9

DO

Al0

Dl

All

D2

A12

D3

A13

D4

A14

D5

A15

D6

Vee

D7

3:

(')
FIGURE 2 -

R/W

AO-A4

CO

t

DO-D7

A5- A15

"'-

--~

en

BLOCK DIAGRAM OF DMAC

~

Bus
Control

Address
Bus
Buffer

'r

Address
Bus
Bulter

Data Bus
Buller

J
~

~

CSIT ( AKB
~

MPX

.....

-

-4-

Register
Select

t ••

c.u

0

~

DROl

#0 H
:
L
I- - - - - --1-- ----#1 H
1
L
I- - - - - - -~ - - - - - - 1
#2 H
L

DRO
Control

DGRNT

Byte Count
Decrementer

U

~

DR02

1-- - - -

#3 H

~

A

Address
Register
116x 4)

fi

L

L

#0 H

1------.1-----A
'"V

--+-- ---1

~I RO/DEND

L

Address Latch

Address
Incrementl Decremellter

J:.
......
......

IRQI
DMA END
Co"trol

#1 H
#2-H- -

#0
-------#1
------ ...
#2

L

1

L

+- - L- 1-------+-----I- -

#3 H

Channel
Control
Register
18x 4)

I

Byte Count Register 116 x 4)

Tx ROO

A

ModelTir'1lng
Control

E DMA

r- - - --#3

PCR 15)
-----ICR 15)

A

...
------DCR (4)

RESET

VCC

---...

---...

VSS ---+-

Tx ROl
Tx ROI
Tx AK
Control

General
Control
Register

Priority
Control

tI

..

~

l+-

Tx R02
Tx R03

~
f-+~

~

TxAK
Encoder

----

~ Tx AKA
Tx STB

--+

(Tx AKB)

MC6844

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range
MC6844, MC68A44, MC68B44
MC6844C, MC68A44C
Storage Temperature Range

Symbol

Value

Unit

VCC·

-0.3 to + 7.0
-0.3 to + 7.0

V

Yin·

V

TA

TL to TH
to + 70
-40 to +85

°c

T stg

-55 to + 150

°c

Symbol

Value

Unit

fJJA

100
50

°C/W

o

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS
orVcc).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

60

I

POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °c can be obtained from:
TJ=TA+(PDeOJA)
Where:
TA = Ambient Temperature, °c
OJA = Package Thermal Resistance, Junction-to-Ambient, °C/W

(1)

PD=PINT+PPORT
PINT= ICC x VCC, Watts - Chip Internal Power
PPORT= Port Power Dissipation, Watts - User Determined
For most applications PPORT--_---_

DEND 1

Tx AK 0

1-4--f--------. . Tx AK 0

TxAKA

f--~----~~TxAKl

N.C.

CS/Tx AKB

IRQ (Open Collector)

DGRNT

TxSTB~--------+----'

TxAKA~----~~

~--~--_4----_+----_r--TxAKO

~------_+----~----~--TxAKl
~------------~----~--TxAK2

(Open
Collector)

~------------------~--TxAK3

CS

3-423

I

MC6844

MC68000 BUS ARBITRATION INTERFACE

I

Figure 11 shows an MC6844/ MC68000 interface for
DMAC mode 2 or mode 3 operation. The MC68000 Advanced Information Data Sheet should be consulted for complete
understanding of the circuit.
The MC6844 must be initialized for transfer mode, byte
count, DMA starting address, etc.
Initially DGRNT is low, BGACK output is high, and Tx
STB is high. The MC6844 responds to a Tx RO by asserting
DROH. Assertion of Tx RO also asserts MC68000 BR. For
DMA transfer, two conditions must be met: 1l DMAC DROH
must be asserted and 2l all bus masters must relinquish the
system bus. Once DROH is asserted it remains asserted low
until DMA byte transfer in the halt-steal mode or until the last
byte of a DMA memory block is being transferred in the haltburst mode. A relinquishing of the bus by all bus masters is
indicated by negated BGACK, AS, and DTACK after the
MC68000 asserts BG in response to a bus request.
When both condition~re met, the NAND flip-flop is set
by assertion of LS138 03, asserting DGRNT and BGACK.
The DMAC then performs a byte transfer in the halt-steal
mode or a block of byte transfers in the halt-burst mode.
The NAND flip-flop is cleared on the rising edge of Tx STB
after asserting during each DMA cycle in the halt-steal
mode, and during the last DMA cycle of a DMA block in the
halt-burst mode (see MC6844 timing diagramsl.
Note that BR to the MC68000 is negated when BGACK is
asserted, satisfying an MC68000 requirement.
MC6800 BUS ARBITRATION INTERFACE
A typical system design,using the MC6800/MC6844, is
shown in Figure 12. A clock generator/driver is used which
will stretch the MPU clock during DMA operation while
generating a non-stretched clock for system memory. Priority logic is used to give highest priority to refresh request,
since memory refresh and DMA transfers must not occur
during the same E cycles.

During mode 2 or 3 DMA operation, the clock generator
has no control over DMA Grant. To prevent DMA operation
in mode 1 during a memory refresh cycle, system E
must be gated with refresh grant. DGRNT must be the
ORed output of bus available (BAl and DMA grant from
the clock generator in order to support all 3 DMA modes of
operation.
During the DMA cycle, a system VMA Signal must be
generated by the DMAC. This is done by ORing Tx STB and
the MPU VMA line.
MC6844/MC6809 BUS ARBITRATION INTERFACE
An MC6844/MC6809 interface is presented in Figure 13.
This circuit ensures that MC6809 DMA/BREO is asserted
only during 0 high, an MC6809 requirement. The circuit will
also generate a system VMA (valid memory addressl, often
referred to as DMA VMA.
The MC6809 does not generate a VMA output since the
only invalid address asserted by the MPU is $FFFF with R/W
asserted high. Therefore, an MC6809 system does not normally need a VMA circuit. When using the MC6844 for DMA
in an MC6809 system, however, a VMA circuit is required
since the address lines are floating during dead cycles between the MPU and DMA modes. Devices on the bus must
be deselected during this time.
Initially, in the MPU mode, DR01/2 is negated (high
levell, and the 0 output of U3 is high. The output of the exclusive OR gate U4 is therefore a low, inhibiting clocking of
U3 by forcing the output of U5 to remain a low. When
DR01 /2 is asserted low, the output of U4 changes to a high.
If the MC6809 0 output is high at this time, the output of U5
changes to a high, clocking U3. If the MC6809 0 output is
low at this time, the output of U5 will be driven high on the
next riSing edge of 0, clocking U3. When U3 is clocked, the
o output of U3 changes to a low asserting MC6809
DMA/BREO. The output of U4 at this time is a low, since
both of the U4 inputs are low.

FIGURE" - MC68000/MC6844 INTERFACE

1 - _ - - - - - - - - - 1 ORQ2 Tx RO

BR~----Cj

MC68000
BG~-+---I

AS f---+---I

MC6844

OT ACK f---+---I
BGACK I---

U

I~

~

~

IZ

a:

0Cll

c.9

a:

Cll

"iii

a: a:

Address Bus
Data Bus

1------'

R/W 1 - - - - - - - - - - '

DMAC
Signals

VMAI-----\
MC6800

Tx STB
IRQ
HALTI------~-------f_4__+----4r­

BA f - - - - - - - - - \

DGRNT

TSC 1 - - - - - - _ - 1

MEM

DRQ2

CLKI--------f_--~~4__+~

E DMA
DMA/Ref Gr
Clock
Generatorl
Driver

RefRQI--r-----~

DMA GNT

DMA/Ref Req

DMA

RQI-------------~~r_

DRQ1

Priority
Logic

FIGURE 13 -

MC6844/MC6809 INTERFACE

BS

System VMA

BA

DGRNT

System E
System RESET
RESET

RESET

DMAiREO

DRQ1/2

Q

MC6809

MC6844

3-425

I

MC6844

high, indicating that the address on the system address bus
is invalid during this dead cycle between MPU and OMA
modes. On the next falling edge of E, U1 is clocked high
forcing the output of U2 low during this OMA cycle. When
BA is negated after OMA, the output of U2 is forced high until the next falling edge of E, indicating invalid address during
this dead cycle.

After the OMA transfer, OR01/2 is negated by the
MC6844, forcing the output of U4 to a high. Once again, U3
will be clocked only when the MC6809 0 output is high.
VMA is generated by U1 and U2. Initially, in the MPU
mode, U1 is clear, with a low 0 output. The BA (bus
available) output of the MC6809 is also a low. Therefore, the
output of U2 (VMA) is low (VMA asserted). When the
MC6809 asserts BA for OMA, the output of U2 becomes

I

ORDERING INFORMATION
Order Number

Frequency (MHz)

Temperature

Ceramic
L Suffix

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
-40°C to 85°C
O°C to 70°C
- 40 c C to 85 c C
OCC to 70 c C

MC6844L
MC6844CL
MC68A44L
MC68A44CL
MC68B44L

Cerdip
S Suffix

1.0
1.0
1.5
1.5
2.0

OCC to 70 c C
-40 c C to 85 c C
OCC to 70 c C
-40°C to 85°C
OCC to 70°C

MC6844S
MC6844CS
MC68A44S
MC68A44CS
MC68B44S

Plastic
P Suffix

1.0
1.0
1.5
1.5
2.0

OCC to 70°C
-40°C to 85°C
OCC to 70°C
-40°C to 85°C
O°C to 70°C

MC6844P
MC6844CP
MC68A44P
MC68A44CP
MC68B44P

Package Type

3-426

®

MOTOROLA

MC6845

CRT CONTROLLER (CRTC)
The MC6845 CRT controller performs the interface between an MPU
and a raster-scan CRT display. It is intended for use in MPU-based controllers for CRT terminals in stand-alone or cluster configurations.
The CRTC is optimized for the hardware/software balance required
for maximum flexibility. All keyboard functions, reads, writes, cursor
movements, and editing are under processor control. The CRTC provides video timing and refresh memory addressing.

MOS

(N-CHANNEL, SILICON-GATE)

CRT CONTROLLER
(CRTC)

• Useful in Monochrome or Color CRT Applications
• Applications Include "Glass-Teletype," Smart, Programmable, Intelligent CRT Terminals; Video Games; Information Displays
• Alphanumeric, Semi-Graphic, and Full-Graphic Capability

I

• Fully Programmable Via Processor Data Bus. Timing May Be Generated for Almost Any Alphanumeric Screen Format, e.g., 80 x 24,
72 x 64, 132 x 20
•

Single + 5 V Supply

•

M6800 Compatible Bus Interface

• TTL-Compatible Inputs and Outputs
•

Start Address Register Provides Hardware Scroll (by Page or
Character)

• Programmable Cursor Register Allows Control of Cursor Format
and Blink Rate
• Light Pen Register
• Refresh (Screen) Memory May be Multiplexed Between the CRTC
and the MPU Thus Removing the Requirements for Line Buffers or
External DMA Devices
• Programmable Interlace or Non-Interlace Scan Modes
• 14-Bit Refresh Address Allows Up to 16K of Refresh Memory for
Use in Character or Semi-Graphic Displays
• 5-Bit Row Address Allows Up to 32 Scan-Line Character Blocks
•

By Utilizing Both the Refresh Addresses and the Row Addresses,
a 512K Address Space is Available for Use in Graphics Systems

• Refresh Addresses are Provided During Retrace, Allowing the CRTC
to Provide Row Addresses to Refresh Dynamic RAMs
• Pin Compatible with the MC6835

PIN ASSIGNMENT
GND

VS

RESET

HS

lPSTB

RAO
RAl

MAl
MA2

RA2
RA3
RA4

ORDERING INFORMATION

DO
MA5

Package Type
Ceramic
l Suffix

Cerdip
S Suffix

Plastic
P Suffix

Frequency (MHz)

Temperature

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6845l
MC6845Cl
MC68A45l
MC68A45Cl
MC68B45l

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6845S
MC6845CS
MC68A45S
MC68A45CS
MC68B45S

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
-40°C to 85°C
O°C to 70°C
- 40°C to 85°C
O°C to 70°C

MC6845P
MC6845CP
MC68A45P
MC68A45CP
MC68B45P

Order Number

3-427

01

MA6

02

MA7

03

MA8

04

MA9

05

MAlO

06

MAll

07

MA12

CS

MA13

RS

OE

CURSOR
VCC

R/W
ClK

MC6845

FIGURE 1 - TYPICAL CRT CONTROLLER APPLICATION

~--e-----------~------------------------------------~AB

L-_ _ _--I~-+-----'r---+-------------------r------'DB

Primary Bus

Cursor,
Display
Enable

I
HS

VS

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range
MC6845, MC68A45, MC68B45
MC6845C, MC68A45C
Storage Temperature Range

Symbol

Value

Unit

VCC

-0.3to +7.0

V

Vln

-0.3 to + 7.0

V

TA

TL to TH
o to 70
-40 to +85

DC

Tstq

- 55 to + 150

DC

Symbol

Value

Rating

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic Package
Cerdip Package
Ceramic Package

{JJA

100
60
50

The device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS s (Vin or
VoutlsVCc.

DC/W

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage

Characteristics

VCC

4.75

5.0

5.25

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Input High Voltage

VIH

2.0

-

VCC

V

3·428

MC6845

POWER CONSIDERATIONS

The average chip-Junction temperature, TJ, in °c can be obtained from:
(1)

T J = TA + (PO-liJA)
Where:
T A == Ambient Temperature, °c
liJA== Package Thermal Resistance, Junction-to-Ambient. °C/W
Po == PINT + PPORT
PINT==lccxVCc. Watts - Chip Internal Power
PPORT == Port Power Dissipation, Watts - User Oetermined

For most applications PPORT~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Oarlington bases or sink LEO loads.
An approximate relationship between Po and T J (if PPORT is neglected) is:
PO=K-+-(TJ+273°C)

(2)

Solving equations 1 and 2 for K gives:
(31
K = PO-(T A + 273°C) + liJNP02
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at equilibrium)
for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1) and (2) iteratively for any
value of T A.

0
DC ELECTRICAL CHARACTERISTICS (Vee = 5.0 Vdc +
- 5%, VSS = 0, T A = 0 to 70 e unless otherwise noted, see Figures 2-41

Symbol

Min

Typ

Max

Unit

Input High Voltage

VIH

2.0

-

V

Input Low Voltage

VIL

-0.3

-

Vee
0.8

Input Leakage Current

lin

0.1

2.5

p.A

Characteristic

Hi-Z State Input Current (V CC = 5.25 VI (Vin = 0.4 to 2.4 VI
Output High Voltage
(ILoad= -205p.AI
II Load = -l00p.AI

00-07
Other Outputs

-

V

ITSI

-10

-

10

p.A

VOH

2.4
2.4

3.0
3.0

-

V

-

Output Low Voltage (ILoad = 1.6 mAl

VOL

-

0.3

0.4

V

Internal Power uissipation (Measured at T A = ooel

PINT

-

600

750

mW

Input Capacitance

00-07
All Others

Output Capacitance

All OUtputs

3·429

-

-

Cin

-

-

12.5
10

pF

Cout

-

-

10

p~

I

MC6845

BUS TIMING CHARACTERISTICS (See Notes 1 and 2) (Reference Figures 2 and 3)
Ident.
Number

I

Characteristic

Symbol

MC68A45

MC68B45

Min

MC6845
Max

Min

Min

Max

Max

Unit

1

Cycle Time

tcyc

1.0

-

0.67

-

0.5

-

p's

2

Pulse Width, E Low

PWEL

430

-

280

-

210

3

Pulse Width, E High

PWEH

450

-

280

-

220

-

ns

ns

4

Clock Rise and Fall Time

tr,tf

-

25

-

25

-

20

ns

9

Address Hold Time (RS)

tAH

10

-

10

-

10

-

ns

13

RS Setup Time Before E

tAS

80

-

60

-

40

-

ns

14

tcs

80

-

60

-

40

-

ns

15

R/W and
R/W and

tCH

10

-

10

-

10

-

ns

18

Read Data Hold Time

tOHR

20

50*

20

50*

20

50*

ns

21

Write Data Hold Time

tOHW

10

-

10

30

Peripheral Output Data Delay Time

tOOR

-

CS Setup Time
CS Hold Time

Before E

290

-

31
Peripheral Input Data Setup Time
165
80
tosw
* The data bus output buffers are no longer sourcing or sinking current by tOHR maximum (high Impedance)

FIGURE 2 -

-

10

180

0

150

ns

-

60

-

ns

-

MC6845 BUS TIMING

~---------------'(E)---------~
RS

R/w' Cs

Read Data

Write Data
NOTES:
1. Voltage levels shown are VL:SOo4 V, VH~204 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified.

FIGURE 3 -

BUS TIMING TEST LOAD
5.0 V

Test Point Q - - - _ e - - _ e - - - i. .- - . RL = 204 kG

C

MM06150
or Equiv.

=

3-430

C = 130 pF for 00-07
=30 pF for MAO-MA13, RAO-RA4,
DE, HS, VS, and CURSOR
R = 11 kG for 00-07
= 24 kG for All Other Outputs

ns

MC6845

CRTC TIMING CHARACTERISTICS (Reference Figures 4 and 5)
Symbol

Min

Max

Unit

Minimum Clock Pulse Width, Low

PWCL

150

-

ns

Minimum Clock Pulse Width, High

PWCH

150

-

ns

fe

-

3.0

MHz

Characteristic

Clock Frequency
Rise and Fall Time for Clock Input

t cr , tcf

-

20

ns

Memory Address Delay Time

tMAD

-

160

ns

Raster Address Delay Time

tRAD

-

160

ns

Display Timing Delay Time

tDTO

-

250

ns

Horizontal Sync Delay Time

tHSD

-

250

ns

Vertical Sync Delay Time

tVSD

-

250

ns

Cursor Display Timing Delay Time

tCDD

-

250

ns

PWLPH

80

-

ns

tLPD1

-

80

ns

tLPD2

-

10

ns

Light Pen Strobe Minimum Pulse Width
Light Pen Strobe Disable Time

NOTE: The light ptm strobe must fall to low level before VS pulse rises.

FIGURE4 - CRTCTIMING CHART

MAO-MA13

RAO-RA4

DE

HS

VS

CURSOR

NOTE: Timing measurements are referenced to and from a low voltage at 0.8 volts and a high voltaoe of 2.0 volts unless otherwise noted.

3·431

I

MC6845

FIGURE 5 -

CRTC-ClK, MAO-MA13, AND lPSTB TIMING DIAGRAM

. .-----l/fc-------'l~

elK

MAO-MA13

lPSTB

I

l

NOTE Timing measurements are referenced to and
from a low voltage of 0.8 volts and a high
voltage of 2.0 volts, unless otherwise noted

~---~---PWlPH--------~

Wh,e

::~::TC d"""


qj

~

} Line INSLI

E
x

~

Display Period

Vertical Retrace Period

Total Scan Line Adjust INadji
NOTE 1: Timing values are described in Table 5

3-437

I

MC6845

Horizontal Displayed Register (R1) - This 8-bit write-only
register determines the number of displayed characters per
line. Any 8-bit number may be programmed as long as the
contents of RO are greater than the contents of R1.
Horizontal Sync Position Register (R2) - This 8-bit writeonly register controls the HS position. The horizontal sync
position defines the horizontal sync delay (front porch) and
the horizontal scan delay (back porch). When the programmed value of this register is increased, the display on the
CRT screen is Shifted to the left. When the programmed
value is decreased the display is shifted to the right. Any
8-bit number may be programmed as long as the sum of the
contents of R2 and R3 are less than the contents of RO. R2
must be greater than R1.

I

Sync Width Register (R3) - This 8-bit write-only register
determines the width of the horizontal sync (HS) pulse. The
vertical sync pulse width is fixed at 16 scan-line times.
The HS pulse width may be programmed from 1-to-15
character clock periods thus allowing compatibility with the
HS pulse width specifications of many different monitors. If
zero is written into this register then no HS is provided.
Horizontal Timing Summary (Figure 12) - The difference
between RO and R1 is the horizontal blanking interval. This
interval in the horizontal scan period allows the beam to
return (retrace) to the left side of the screen. The retrace time
is determined by the monitor's horizontal scan components.
Retrace time is less than the horizontal blanking interval. A
good rule of thumb is to make the horizontal blanking about
20% of the total horizontal scanning period for a CRT. In inexpensive TV receivers, the beam overscans the display
screen so that aging of parts does not result in underscanning. Because of this, the retrace time should be about one
third the horizontal scanning period. The horizontal sync
delay, HS pulse width, and horizontal scan delay are typically
programmed with a 1:2:2 ratio.
Vertical Total Register (R4) and Vertical Total Adjust
Register (R5) - The frequency of VS is determined by both
R4 and R5. The calculated number of character row times is
usually an integer plus a fraction to get exactly a 50 or 60 Hz
vertical refresh rate. The integer number of character row
times minus one is programmed in the 7-bit write-only vertical total register (R4). The fraction of character line times is
programmed in the 5-bit write-only vertical total adjust
register (R5) as the number of scan lines required.
Vertical Displayed Register (R6) - This 7-bit write-only
register specifies the number of displayed character rows on
the CRT screen, and is programmed in character row times.
Any number smaller than the contents of R4 may be programmed into R6.
Vertical Sync Position (R7) - This 7-bit write-only register
controls the pOSition of vertical sync with respect to the
reference. It is programmed in character row times. When
the programmed value of this register is increased, the
display pOSition of the CRT screen is shifted up. When the
programmed value is decreased the display position is
shifted down. Any number equal to or less than the vertical
total (R4) and greater than or equal to the vertical displayed
(R6) may be used.

Interlace Mode and Skew Register (R8) - The MC6845
only allows control of the interlace modes as programmed by
the low order two bits of this write-only register. Table 3
shows the interlace modes available to the user. These
modes are selected using the two low order bits of this 6-bit
write-only register.

TABLE 3 - INTERLACE MODE REGISTER

Bit 1

Bit 0

0
1
0
1

0
0
1

1

Mode
Normal Sync Mode (Non-Interlace)
Interlace Sync Mode
Interlace Sync and Video Mode

In the normal sync mode (non-interlace) only one field is
available as shown in Figures 6 and 14a. Each scan line is
refreshed at the VS frequency (e.g., 50 or 60 Hz).
Two interlace modes are available as shown in Figures 7,
14b, and 14c. The frame time is divided between even and
odd alternating fields. The horizontal and vertical timing relationship (VS delayed by one half scan line time) results in the
displacement of scan lines in the odd field with respect to the
even field.
In the interlace sync mode the same information is painted
in both fields as shown in Figure 14b. This is a useful mode
for filling in a character to enhance readability.
In the interlace sync and video mode, shown in Figure 14c,
alternating lines of the character are displayed in the even
field and the odd field. This effectively doubles the given
bandwidth of the CRT monitor.
Care must be taken when using either interlace mode to
avoid an apparent flicker effect. This flicker effect is due to
the doubling of the refresh time for all scan lines since each
field is displayed alternately and may be minimized with proper monitor design (e.g., longer persistence phosphors).
In addition, there are restrictions on the programming of
the CRTC registers for interlace operation:
1. The horizontal total register value, RO, must be odd
(i.e., an even number of character times).
2. For interlace sync and video mode only, the maximum
scan-line address, R9, must be odd (i.e., an even
number of scan lines).
3. For interlace sync and video mode only, the number
(Nvd) programmed into the vertical display register (R6)
must be one half the actual number required. The even
numbered scan lines are displayed in the even field and
the odd numbered scan lines are displayed in the odd
field.
4. For interlace sync and video mode only, the cursor start
register (R10) and cursor end register (R11) must both
be even or both odd depending on which field the cursor is to be displayed in. A full block cursor will be
displayed in both the even and the odd field when the
cursor end register (R 11) is programmed to a value
greater than the value in the maximum scan line address
register (R9).

3:

o

Q)

CO
~

U1

FIGURE 12 - CRTC HORIZONTAL TIMING

~

~tc
ClK

I
,

*

MAO-MA13*."

J:,..

I

U)

Character # I

CO

,

)0,0(

Horizontal Display IR1)Nhd x tc

I
r
I'
J.'

J
U)

Horizontal Total I ROl
IN
1
tsl=
ht+ )xt c

~

I

I-

•

~

,I
1
~

I

!

I

I

,

~

~
I

d

~~"\IL-->~""I""L_rLJI
I
,
r
I,-,ffi-rl-lii

'"

I

:'1

Horizontal Retrace

I

I

II

I

-

~

"\i

,

I

Dlspen i

I

I

I

-

'"

101(

,

I
'I

I

I

~

I

-j'
I

I

*'

I

I

I

~ INh5~.-1

"J

I

..
..
Horizontal Sync Position IR2)
Front Porch ISync Delay)

Nhsp

I
I HS

I

I

If

I
I

I

I

I

I

I

~
I
'I

-

I

f'. !
"\i I

Pulse Width IR3) I
~N
x t ~
I~
hsw
c ~

~

,
j

~

! "J
Back

'
,

,
I Nht

I

P~h IScan Delay)

I

I
I
I
1
,
1

)01

~

,

~NhSP-1NhSP.L~

IN hd- 1 Nhd I
I
I

HSYNC!

,

I

'"

* Timing is shown

~

'\.jr---------'

for first displayed scan row only. See chart in Figure 15 for other rows. The initial MA is determined by the contents of start
address register, R12/R13. Timing is shown for R12/R13=O

NOTE: Timing values are described in Table 5.

III

FIGURE 13 Non-Interlace
Mode :...
I

Lini:

Frame 1

~~~~~ ! I ' I

.,...

~

0

:I

Nvsp

Ito I ' I

I
I
'..

Y,tsl~~

:
I
*TR~

:..

:

I

I

:

~

I

I

DE_~
RAO-RA4

II

_.

~

~

r___

L..J

~

n_.

!

3:

oC»
Frame4

I'

0

,

II

I

... !

Frame2

o

'6 tsl - . 1

n:

Y,tsl~~

:!n
~

i4I(-

I

rL..L
:

I

I

Linex'

I

'--f

L...I

_;

:..

I

I

I

I

Line x Nvsp

r---- .... . ,'--'r__-- :
..
I

L...I

I

.:

:..

LinexNvl

:

I

I

:

:

k=='6°'s1=::;:j

Interlace
Sync Mode

.,1.
:

I

Linexl

_,

:....

Line x Nvsp

I

I

I

Linex(AdjustRasterl~

. ; ...

:
:I
I

I

I

:I

I

I

I

I

I

I
I
I

I

I

I

I

: :

:

i

:x:::EJ(----XIJC:DC----:x::E::X---- ~ :x::::D:IX---~

I

LinexO

~

c.n

.:

I

'....

I

I

I

I

o

Nvsp

h ______

I

C'

CO

.:

I

r-'1 .---, I I

...

I

Nvsp

I

....

_rri~-tsl

.1"

LinexO

.. :...
I

I I

I'

0

!I

Odd Field

~----~ - - -

VSYNC

n

~

I

' I

1---------......:.II:n
:~y,tsl
:: :

(,.)

Nvsp

Frame 1

Even Field

Line Number
is VSYNC

Non-Interlace
Mode

,

I

.1.

I

Interlace : .
Mode I

Frame 3

I

'60tsl~H!.--

I

CRTC VERTICAL TIMING

.i...

Frame 2

•

I'll(

I

~Y, Trfoll(-

I

.... 1

LinexNvl

I

I

i

.i...

I

LineX(AdjUstRasterl~

I

I

~v,

I

I

I

~

I'

RAO-RA4~=
:
~r
I:
I
I
I
VSYNC ~-Nr
0
,
---~---~---~---XIJC::J:)C----~---~

~
;'>

l

Even Field

~

'

.... Y,Tr)4l(-

l'

...

"
'\

\

,.",.....:=16.Tr=::::;:j
~

:

:

:

l" >
l
,

l,
"

:"

'I

I

'I

I

:

I

Re~~~~ ~--- ~---JQ:X---~--::x::!:X----~---JQ!:XIX---~
I

:

:

Odd Field

:

k"='60tsl~

I

I

I

I

I
Interlace Sync
and Video Mode

'..
:

Line x 0

:

)I

I ...

Line xl

I iii(

I

.,
I

I

:

:

:

Line x Nvsp

I_

~1

Line x Nvl

I
I

I

:

...

Line x (Adjust Raster) ~
I

1111(
I

~

I

I

I
Y,Trr-

Re~~~~x:J:JCIX----~---~----x:::pc:::Q(--~----:x:::IX::IX----~----~
:
. ""
l'
l " Ia::;=:16.Tr~"
:
l
~,
I,
I
Even Field
"
'>
!

I y, Tr;

i

~

I

:

J

'I

I

'I

:

:

:

1

'.J

Re~-~~~ BCOCJ:X----~----~----~----~---~--~--~
:

:

:

Odd Field

I
NOTES: 1. In interlace sync and video mode, maximum raster address (Nrl shall be odd

2. In interlace mode, Nht shall be odd

:

l

k=='60Tr=::;jL-_ _ _ _ _ _ _ _
' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....

MC6845

FIGURE 14 - INTERLACE CONTROL
Scan Line Address

Scan Line Address

Scan Line Address

0

0
-

0

0

1

0

0

0

2

0

0

0

0 0
0
0
0

0

0 0
0
0
0

--0

0

-9

&-1

-e-

-2

0

-&4 0 0 0

~

0
-0
0 0

7-8
--9-

(7 -6

0
-9

Even
Field
(a) Normal Sync

(b) Interlace Sync

Non-Blink

1
0
1

Cursor Non-Display

-1
t
---9

-3

0 0 0 0 0
--6
- &
6
0
0
-&
--9
0

-5

-7

--1

-----

--:;
-

-5

- - - --7
Even
Odd
Field
Field
(c) Interlace Sync and Video

OTHER REGISTERS
Start Address Register (R12-H, R13-l) - This 14-bit
write-only register pair controls the first address output by
the CRTC after vertical blanking. It consists of an S-bit low
order (MAO-MA7) register and a 6-bit high order (MASMA 13) register. The start address register determines which
portion of the refresh RAM is displayed on the CRT screen.
Hardware scrolling by character or page may be accomplished by modifying the contents of this register.

TABLE4 - CURSOR START REGISTER

0

-9

4

- -

Cursor Register (R14-H, R15-L) - This 14-bit read/write
register pair is programmed to position the cursor anywhere
in the refresh RAM area; thus, allowing hardware paging and
scrolling through memory without loss of the original cursor
position. It consists of an S-bit low order (MAO-MA7) register
and a 6-bit high order (MAS-MA13) register.

Cursor Start Register (Rl0) and Cursor End Reigster
(Rll) - These registers allow a cursor of up to 32 scan lines
in height to be placed on any scan line of the character block
as shown in Figure 15. RlO is a 7-bit write-only register used
to define the start scan line and the cursor blink rate. Bits 5
and 6 of the cursor start address register control the cursor
operation as shown in Table 4. Non-display, display, and two
blink modes (16 times or 32 times the field period) are
available. R11 is a 5-bit write-only register which defines the
last scan line of the cursor.

Bit 5

8

invert cursor is easily implemented by programming the
CRTC for a blinking cursor and externally inverting the video
signal with an exclusive-OR gate.

CURSOR CONTROL

0
0
1
1

-7

Odd
Field

Maximum Scan Line Address Register (RS) - This 5-bit
write-only register determines the number of scan lines per
character row including the spacing; thus, controlling operation of the row address counter. The programmed value is a
maximum address and is one less than the number of scan
lines.

Bit 6

-3

5-~ -9-0 &"8 -4
e- - 5
--9
6
0
0

2-

Light Pen Register (R16-H, R17-L) - This 14-bit read-only
register pair captures the refresh address output by the
CRTC on the positive edge of a pulse input to the LPSTB
pin. It consists of an S-bit low order (MAO-MA7) register and
a 6-bit high order (MAS-MA 13) register. Since the light pen
pulse is asynchronous with respect to refresh address timing
an internal synchronizer is designed into the CRTC. Due to
delays (Figure 5) in this circuit, the value of R16 and R17 will
need to be corrected in software. Figure 16 shows an interrupt driven approach although a polling routine could be
used.

Cursor Display Mode

Blink, 1/16 Field Rate

Blink, 1/32 Field Rate
Example of cursor display mode

When an external blink feature on characters is required, it
may be necessary to perform cursor blink externally so that
both blink rates are synchronized. Note that an invert/ non-

3·441

I

MC6845

FIGURE 15 -

CURSOR CONTROL

Ir--o-n---Ir--o-ff--~--o-n--+-----+
I

I

-....l

~

I

I

Blink Period =
16 or 32 Times
Field Period

O-+-+-+-+-t--t-+-

1....,.-+--+-+-H-+--

II

~.

1-+-+-+-H-+-+-

2 -+-+-++--I-l-l,....

2 -+-+--t-IH-++3 -+-+-+-iH-++4 -+-+--+-+-~I-+-

3-+++-H++4-+-+-+-+-t-ir-+-

5-+-+--t-IH-+-+6 -+-+--+-i--I-+-+-

5 -+-++-H-+--I-

7--+-+--+-+-+-+-+-8-+-+-++-+-1--1-

7 -+-+-++-+-l-l8--+-+-++--I-l-l-

9-e~~oo;!e-

10 -+-+--+-+-H-+-11-+-+--+-+-H-+--

1~~~3~~~~
11-+-+--+-t-1H-+-

8-+-t-+--t-H-t9-+-t-+--t-H-t10 -+-+-+--t-H-+11 -+-+--+-+-H-+--

Cursor Start Adr.=9
Cursor End Adr. = 9

Cursor Start Adr. = 9
Cursor End Adr. = 10

Cursor Start Adr. = 1
Cursor End Adr. = 5

6-+-+--+--HH-+-

FIGURE 16 -

6 -t--+-hH-+--+-

7 -+-+-+-+-t--t-+-

INTERFACING OF LIGHT PEN

Light Pen

OPERATION OF THE CRTC
TIMING CHART OF THE CRT INTERFACE SIGNALS

TABLE 5 -

Timing charts of CRT interface signals are illustrated in
this section. When values listed in Table 5 are programmed
into CRTC control registers, the device provides the outputs
as shown in the timing diagrams (Figures 12, 13, 17, and 18).
The screen format is shown in Figure 11 which illustrates the
relation between refresh memory address (MAO-MA 13),
raster address (RAO-RA4), and the position on the screen. In
this example, the start address is assumed to be zero.

Reg. #

3-442

VALUES PROGRAMMED INTO CRTC REGISTERS

Register Name

RO

H Total

R1

H. Displayed

R2

H. Sync Position

R3

H. Sync Width

R4

V. Total

R5
R6
R7

V. Sync Position

R8

Interlace Mode

R9

Max. Scan Line Address

Value

Programmed
Value

Nht+ 1

Nht

Nhd

Nhd

Nhsp

NhSp

Nhsw
Nvt + 1

Nhsw
Nvt

V. Scan Line Adjust

Nadj

Nadj

V. Displayed

Nvd
Nvsp

Nvd
Nvsp

Nsl

Nsl

3:

(')
0)
Q)
~
(J1

FIGURE 17 - CURSOR TIMING

RAO-RA4*:X

T

I

MAO-MA13**

Character Row #

I
I
I

(..)

~

*I

Character #

I

f

f

I

:
I
I
I
I
I

~
(..)

Cursor

I

I

I

I

I

I

I

I

I

~I Nhd+ *
=x==x
~
I Nhd INhd+lINhd+21
I Nhd+ I

I

INhd+lINghd+21
I
I
I

I

:

:

:

:

I

~I Nhd+ •I

NhdNhd+l Nhd+ 21
I
I
I

;

I

Nht

:

Nhd

I

I~

Nht

I

t----1

X

I

I
I
I

Nht

I

I ~
I

I

I

I

: :

I
I
Nht

t----1

I

I

I
I

I
I

: ~

0

I
I

I

Nht

' :

I
Nht

r-----i'-_____

* Timing is shown for non-interlace and interlace sync modes
Example shown has cursor programmed as
Cursor Register = Nhd + 2
Cursor Start = 1
Cursor End = 3
**The initial MA is determined by the contents of start address register, R12/R13. Timing is shown for R12/R13=O
NOTE 1: Timing values are described in Table 5.

..

•
FIGURE 18 -

:.5

~

Ua:

I

{,

I

'C

0I

II

Horizontal Display

~I~

Co i!
.c 0

>

REFRESH MEMORY ADDRESSING (MAO-MA13) STAGE CHART

Cf)
~

0

1

I
I

0

I
I

Nhd

Nh

1

U>

J:.

~
~

I

....

Nvd x Nhd + 1

NVd- 1{

(Nvd-1) x Nhd+ 1

i

,i

0
Ns I

0

1

(N v d- 1) xN hd
(Nvd -

i) x Nhd

Nvd x Nhd

(Nvd-1) x Nhd+ 1
Nvd x Nhd+ 1
I

Nvd

I

{

Ns I

~

I

Nvd x Nhd

Nvd x Nhd+ 1

Nvt x Nhd

Nvt x Nhd + 1

1
...

.

..

I

1
Nvd ~ Nhd

I

I

Nvd x Nhd-1

Nvd x Nhd

(Nvd+ 1) x Nhd-1

(Nvd+ 1) x Nhd

I

I

(Nvd + 1) x Nhd-1

(Nvt + 1) x Nhd

(Nvt+1)xNhd-1

(Nvt +;) x Nhd

I

I
I

Nht
Nhd + Nht
I

I
I

Nhd+ Nht

...

2Nhd+ Nht

•

2Nhdo+ Nht

...

(Nvd-1)xNhd+Nht

..

I

I

Nht

•

.~
."
Q;

%

en

OJ

OJ

~

3:

oen

I
I

1
I
I

..

(Nvd-1)xNhd+Nht

...

I

Nvd x Nhd + Nht

I

Nvd + Nhd + Nht

~o

~

~

Q)

a:

ro

Ns

()

."

Q;

I

I

>

Nvt+ 1 {

0

-;

Nvt x Nhd + Nht
I

i

I

I

Nvtx Nhd

{N vt + l)'x Nhd-1

(Nvt+ 1) x Nhd

Nvt x Nhd + Nht

{N vt +1) xN hd

{N vt +1):Nhd+ 1

{N vt +2) xN hd-1

(N vt +:) x Nhd

I

I

i

(N +liNhd+Nht
v
I

(N vt + 1) x Nd+ 1

(N vt +2) x Nhd-1

I

Nad j

I

I
I

I

0

Nvt{

(N vt + 11 x Nhd

I

{N vt +2) xN hd

-----

{N vt
- - - -

-

I

I

I~
+1)Nhd+ Nht

------~---

NOTE 1: The initial MA is determined by the contents of start address register, R12/R13. Timing is shown for R12/R13=O. Only noninterlace and interlace sync modes are shown.

I

MC6845

DETERMINING REGISTER CONTENTS

The remaining register contents must be determined from
some basic data related to the CRT monitor and from the
user-desired display format. The CRTC reference sheet (see
Figure 191 gives a set of formulas for calculating the register
contents as well as other useful characteristics of the
display. This type of data is summarized under basic
parameters in Figures 20 and 21; most or all of this data must
be supplied by the user before he can determine the contents
for registers RO-R7 and R9. All variables 81-810 are equal to
basic parameters 1 through 10.

Some of the register contents are determined rather easily.
They are:
Contents

Register

Name

RS

I nterlace Mode Register

See Table 3

RlO

Cursor Start

See Figure 15 and
Table 4
See Figure 15

R11

Cursor End

R12
R13

Start Address I HI
Start Address III

User programs first
memory location
to be displayed

R14
R15

Cursor IHI
Cursor III

User programs desired
cursor location

R16
R17

Light Pen IHI
Light Pen III

Can be loaded via
light-pen strobe
only

FIGURE 19 - CRTC REFERENCE SHEET
Register Function
RO

Horizontal Total

R1

Horizontal Displayed

R2

Horizontal Sync Position

R3

Horizontal Sync Width

Register Calculations

Intermediate Calculations
Symbol

Description

Calculation

Register

f'

Dot frequency
11 st approx.1

85-187+ 8g1
11/811- 83

RO

tc

Character Time

Calculation

81- 18 7+ 8g1

R1

85

R2

IR11 + IR31

R3

IROI- IR1)
--3--

R4

N-1

[IROI + 1j-81
R4

Vertical Total

R5

Vertical Total Adjust

R6

Vertical Displayed

R7

Vertical Sync Position

RS

Interlace Mode

R9

Maximum Scan Line Address

Dot frequency

tsl

N

87+ 8g
- tc

Scan line time

[IROI+1j-t c

Total # of
scan lines

82- t sl

Integer
and

n = N+ R
8S+81O
8S+81O

RlO

Cursor Start

R11

Cursor End

R12

Start Address IHI

tcr

Character
row time

18S+ 8101-tsl

R13

Start Address III

thr

Horizontal
retrace time

:s [IROI+1-85J-187+8gl

R14

Cursor IHI

R15

Cursor III

R16

Light Pen IHI

R17

Light Pen III

R

tvr

R5

Integer remainder

Vertical
retrace time

R6

86

R7

[IR4,+ 1J- 16- IR5) ~IR7)~IR6)
8S+ 810

R9

18S+ 8101-1

f

:s lU - 8618S+ 8101-t sl
82

3-445

I

MC6845

®

In Figures 20 and 21, worksheet example calculations are
shown for 32 x 16 and 80 x 24 display formats respectively.
The following items are keyed to the figures. Basic parameters ~throU9h @ have been provided; items
through 4 are data about the CRT monitor and items
through 1 are data about the user's desired display.

@
@
@
@
@

CD

®

Calculate the approximate dot frequency. The user
should verify that the bandwidth of his CRT
monitor will accomodate this frequency.
Calculate RO. The resultant answer will usually be
an integer plus a fraction. Assume the next high
integer.

@
@

Fill in value for R1.

I
(j)

®

@
@

Calculate R3. Use the next highest integer. In these
examples the sync width was chosen to be one
third of the horizontal blanking interval.
Calculate R2. Again, use the next highest integer.
Calculate t c , character tie. This is the time required
for one scan line of one character block to be
written.
Calculate the exact dot frequency.
Calculate tsl, scan line time. This is the time required for one scan line of one character row to be
written including retrace time.

FIGURE 20 -

Calculate R4.
Fill in R5.
Fill in R6.
Calculate R7. If there is no possible value for R7,
then the display demands for the CRT monitor exceed its capability. A compromise adjustment must
be made in basic parameter 6, 8, or 10.
Calculate R9.
Calculate t cr . This the time required for one character row to be written.
Calculate thr· thr> B3·
Calculate t vr . t vr > B4·

®

In Figure 20, calculation
verifies that the vertical period is
16.667 milliseconds or 60 hertz. The expression used is:
tcr x [(R4) + 1J+ [tsl x (R5)J = Vp

Another check is calculation of horizontal sync pulse width
R3.
tc = PWHS (typically approximately equals 4
microseconds) .
For convenience, a blank worksheet is provided in Figure
22.

CRTC WORKSHEET EXAMPLE CALCULATION (32x 16)

Basic Parameters (Bl-Bl0)

Register Calculations

Intermediate Calculations
Symbol

Value

1. Horizontal frequency

= 15750±500

CD

f'

32x(5+2)
1 -11xlO- 6
15750

2. Vertical frequency

=--..m_®

tc

1
39x 15750

f

5+2
1.63x 10-6

CD

3. Minimum Horizontal
retrace time

= llxlO- 6

4. Minimum vertical
retrace time

=~®tSI

5. # of displayed
characters per row

= __
32_ _

6. # of displayed
charactor rows

= __
16_ _

®
@

n

39x 1.63x 10- 6

1
60x63.6x 10- 6

--R-

®R2

32+ ].
2

~_2_1_

@R3

38- 32 =
--3

@R4

17-1=

@R5

R=7

@)R6

B6= 16

_1_6_ _1_0_

@R7

®

_1_6_ _1_0_

4.29x 106

=63.6xlO- 6

262

262

(7+8) x63.6x 10- 6

= 954 x 10- 6 @)R9

10. Number of scan lines
between vertical
adjacents

= __
8 _ _ @tvr[15750-16(7+8)JX63.6xlO-6-1.431xlO-3
60

f'i016+1-l2..::.l >(R7»16
\:y
7+8 17 -

.6~

(R7)

~

16

- 11 .42 x 10- 6

® 954xlO- 6 x17=16.218xlO- 3
+ 63.6xlO- 6 x7=.445xlO- 3 _.l
16.663 ms
- f
f",,60 Hz

3·446

Rll
R12
R13
R14
R15

_2_0_

__
2_ _ _
2_

_ 1_6_ _1_0_
_7_ _ _ _
7_

------

R8

Rl0
(38+ 1 - 32)-(5+ 2)
4.29x 106

26

85=32

actor - matrix column
2 _ _ @thr
9. Number of dots between = _ _
horizontal adjacents

4.27 x 106
~
15,750 x (5+2)
-1=

Hex

= 1.63x 10-6 @Rl

7+8
= __
7 _ _ @t cr

Decimal

Register

4.27x 106 (DRO

17

N

_ _5
__

7. # of dots in character
dot matrix row'

8. # of scan lines in char-

Calculate n. This is the total number of scan lines
for each frame. Discard any fraction.
Calculate Nand R.

7+8-1=

_14_~

------

MC6845

FIGURE 21 -

CRTC WORKSHEET EXAMPLE CALCULATION (80 x 24)

Basic Parameters (Bl-Bl0)

1. Horizontal frequency

~

__
60_ _

2. Vertical frequency

Minimum Horizontal
retrace time

11 x 10- 6

Minimum vertical
retrace time

1xlO- 3

# of displayed
characters per row

__
80_ _

Value

CDI'

16-836 x 106

®
(2)

80-17 + 21

18~00

-11 x 10- 6

1100+ 11-18600
7+2
532.31 x 10- 9

16.907 x 106

1100+ 111532.31 x 10- 9 1

53.76 x 10- 6

f

@tSI

1
(60)153.76x 10- 6 1

®n

# of dots in character
dot matrix row

_ _7_ _

# of scan lines in charactor - matrix column

_ _9_ _ @tcr

0

>R7>24
-

26.722:R72:24

~_5_0_

@R1

B5=80

@R2

80+7

G)R3

RO- R1

__
7 _ _0_7_

@R4

28-1

~ _1_B_

310

@R5

R=2

~_0_2_

@R6

B6=24

@R7

®

~

__
18_
__
19_

_0_ _ _
0_

R8

310

__

~_54

2"

~

28

11
19+2)153.76x 10- 6 )

Number of dots between = __2_ _ @thr
horizontal adjacents

® 127+11-116-21
11

Hex

RO 16836x106_1 --..l.QL ~
118,600)(9)

@)R9

10 Number of scan lines
between vertical
adjacents

Decimal

Register

532.31 x 10- 9

tc

__
24_ _ @)N

6. # of displayed
charactor rows

Register Calculations

Intermediate Calculations
Symbol

__2_ _

@)

:5

tvr :5

® B2 =

~8600
60

1101-80)(7+21
16.907 x 106

11.17x 10- 6

3
_ 241 11J53 76 x 10- 6 2.47 x 10.

1/[ltcr IIR4+ 11+ It sl)(R511
1I [1591.39 x 106 )(281 + 153.76 x 10 - 611211
1/16.667 x 10- 3
60

3-447

19+21-1

_1_0_~

591.39x 10- 6
R10

~_O_O_

R11

_11_

--.illL

R12

_0_0_

R13

~ ~

R14

~ ~

R15

_8_0_

I

MC6845

FIGURE 22 - CRTC WORKSHEET
Basic Parameters

Intermediate Calculations
Symbol

Register Calculations
Value

Register

1. Horizontal frequency

f'

RO

2. Vertical frequency

tc

Rl
R2

3. Minimum Horizontal

R3

retrace time

R4
4. Minimum vertical

tsl

R5

retrace time

R6
5. # of displayed

characters per row

I

6. # of displayed

N

8. # of scan lines in char-

R12

tcr

R13

actor • matrix column
9. Number of dots between =

R14

thr

R15

tvr

R17

horizontal adjacents
10. Number of scan lines

------------- ------------------------- - - -------- -------------

Rll

dot matrix row

R16

between vertical
adjacents

R18
R19

CRTC INITIALIZATION
Register RO-R15 must be initialized after the system is
powered up. The processor will normally load the CRTC
register file from a firmware table. The program required to
initialize the CRTC for a 80 x 24 format (example calculation
#2) is shown in Figure 23.
The CRTC registers will have an initial value at power up.
When using a direct drive monitor (sans horizontal oscillator)
these initial values may result in out-of-tolerance operation.
CRTC programming should be done immediately after power
up especially in this type of system.

------------------------------------

R8

Rl0

7. # of dots in character

Hex

R7

R9

charactor rows

Decimal

------

is quite simple as the refresh addresses continually run.
Note that the LPSTB input may be used to support additional system functions other than a light pen. A digital-toanalog converter (DAC) and comparator could be configured
to use the refresh addresses as a reference to a DAC composed of a resistive adder network connected to a comparator. The output of the comparator would generate the
LPSTB input signifying a match between the refresh address
analog level and the unknown voltage.
The light-pen strobe input could also be used as a
character strobe to allow the CRTC refresh addresses to
decode a keyboard matrix. Debouncing would need to be
done in software.
Both the VS and HS outputs may be used as a real-time
clock. Once programmed, the CRTC will provide a stable
reference frequency.

ADDITIONAL CRTC APPLICATIONS
The foremost system function which may be performed by
the CRTC controller is the refreshing of dynamic RAM. This

3·448

MC6845

FIGURE 23 -

PAGE 001

CRTCINIT.SA:O

MC6800 PROGRAM FOR CRTC INITIALIZATION

MC6845 CRTC Initialization Program

NAM
MC6845
00001
TTL
/ MC6845-1 CRTC initialization program
00002
OPT
G,S,LLE=85 print FCB's, FDB's & XREF table
00003
********************************************************
00004
00005
* Assign CRTC addresses
00006
*
9000 A CRTCAD EQU
$9000
Address Register
00007
9001 A CRTCRG EQU
CRTCAD+l Data Register
00008
********************************************************
00009
00010
* Initialization program
00011
*
00012A 0000
ORG
o
a place to start
0001 3A 0000 5F
CLRB
cl ear counter
00014A 0001 CB 1020 A
LOX
#CRTTAB table pointer
00015A 0004 F7 9000 A CRTCl STAB CRTCAD
load address register
00016A 0007 A6 00
A
LOAA O,X
get register value from table
00017A 0009 B7 9001 A
STAA CRTCRG
program regi ster
00018A OOOC 08
INX
increment counters
00019A OOOD 5C
INCB
00020A OOOE Cl 10
A
CMPB $10
finished?
00021A 0010 26 F2 0004
BNE
CRTCl
no: take branch
00022A 0012 3F
SWI
yes: call monitor
00023
********************************************************
00024
* CRTC register initialization table
00025
* 80 x 24 non-interlaced format
00026A 1020
ORG
$1020
start of table
00027A 1020
65
A CRTTAB FCB
$64,$50 RO, Rl - H total & H di spl ayed
A 1021
50
A
A
00028A 1022
$54,$07 R2, R3 - HS pOSe & HS width
56
FCB
A 1023
A
09
00029A 1024
$lB,$02 R4, R5 - V total & V total adj.
A
18
FCB
A 1025
OA
A
00030A 1026
18
A
FCB
$18,$19 R6, R7 - V displayed $ VS pOSe
A 1027
A
18
FCB
00031 A 1028
00
A
$OO,$OA R8, R9 - Interlace &Max scan line
A 1029
OB
A
00032A 102A
00
A
FCB
$OO,$OB R10,Rll- Cursor start &end
A 102B
OB
A
00033A 102C
0080 A
FDB
$0080
R12,R13- Start Address
00034A 102E
0080 A
FDB
$0080
R14,R15- Cursor Address
00035
END
TOTAL ERRORS 00000--00000
CRTCl

0004

CRTCAD 9000

CRTCRG 9001

3-449

CRTTAB 1020

I

®

MC6846

MOTOROLA

MOS

ROM - I/O - TIMER
The MC6846 combination chip provides the means, in conjunction
with the MC6802, to develop a basic 2-chip microcomputer system. The
MC6846 consists of 2048 bytes of mask-programmable ROM, an 8-bit
bidirectional data port with control lines, and a 16-bit programmable
timer-counter.
This device is capable of interfacing with the MC6802 (basic MC6800,
clock, and 128 bytes of RAM) as well as the entire M6800 family if
desired. No external logic is required to interface with most peripheral
devices.

I

(N-CHANNEL, SILICON-GATE,
DEPLETION LOAD)

ROM-I/O- TIMER

• 2048 8-Bit Bytes of Mask-Programmable ROM
• 8-Bit Bidirectional Data Port for Parallel Interface plus Two Control
Lines
• Programmable Interval Timer-Counter Functions
• Programmable I/O Peripheral Data, Control, and Direction Registers

• TTL-Compatible Data and Peripheral Lines
• Single 5-Volt Power Supply

Frequency (MHz)

Temperature

Ceramic
L Suffix

1.0
1.0
1.5

O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6846L
MC6846CL
MC68A46L

Cerdip
S Suffix

1.0
1.0
1.5

O°C to 70°C
-40°C to 85°C
O°C to 70°C

MC6846S
MC6846CS
MC68A46S

1.0
1.0
1.5

O°C to 70°C
- 40°C to 85°C
O°C to 70°C

MC6846P
MC6846CP
MC68A46P

Plastic
P Suffix

Order Number

VSS

Symbol

Value

VCC

-0.3 to +7.0

V

Input Voltage

Vin
TA

-0.3 to + 7.0

V

TL toTH
o to + 70
-40 to +85

°c

-55 to + 150

°C

Storage Temperature Range

Tstg

A8

39

A7

Supply Voltage
Operating Temperature Range
M C6846, MC68A46
MC6846C

Unit

THERMAL CHARACTERISTICS

Al0

A5

RESET

A4

IRQ

CSO

CP2

R/iN

CPl

DO

8

33

AO

9

32

Al

02

31

A2

D3

30

A3

28

P7

D4

VCC

Thermal Resistance
Ceramic
Plastic
Cerdip

D6
Symbol

Value

8JA

50
100

Unit

°C/W

60

This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages
to this high-impedance circuit. Reliabiity of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VCC).

3·450

A9

A6

D5
Characteristic

PSUFFIX

PIN ASSIGNMENT

MAXIMUM RATINGS
Rating

~

SSUFFIX
CERDIP PACKAGE
CASE 734

PLASTIC PACKAGE
CASE 711

~

ORDERING INFORMATION
Package Type

~
\

• Compatible with the Complete M6800 Microcomputer Product
Family

P6

D7

P5

CSI

P4

CTG

P3

CTC

P2

CTO

Pl
20

PO

MC6846

MC6846 BLOCK DIAGRAM

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)

TJ =TA + (PDe(JJA)
Where:
T A !IE Ambient Temperature, °c
(JJA - Package Thermal Resistance, Junction-to-Ambient, °C/W

PD· PINT + PPORT
PINT-ICC x Vce, Watts - Chip Internal Power
PPORT- Port Power Dissipation, Watts - User Determined
For most applications PPORTA), and B-Y (I/>B) Interface

001

FS
RP

• Compatible with the MC6883 (74LS783) Synchronous-Address Multiplexer
• Available in Either an Interlace (NTSC Standard) or Non-interlace
Version

002
003

A/G

004

A/S

005

ClK

CHB
A

21

DA12

I

MC6847. MC6847Y

FIGURE 1 -

BLOCK DIAGRAM OF A TV GAME USING THE VDG AND THE MC6809E MPU
4X Color
Burst Freq.
1438 MHz

rlDh

t3
SO-52
E
MC6809E
MPU

E
Q

Q

Synchronous
Address
Multiplexer

MC6883

AO-A15

ZO-Z7 WE CAS

/

~

00-07

I

B'

AO-A15

"RAS

OAO

RS

HS

Ht-

l
A
T
C
H

B

A
MC6847 y
Video
Display
Generator

t t

Dynamic
RAM
Array
(MCM4027,
MCM4116, MCM6633
or MCM6665)

L

ClK

OAO

I

B

If 16

1

ClK

~

~
~

RF Signa
to TV

M
C
1
3
7
2

r---+ RF
Mod

IU
~

"----

00-07

L..-

r-B
U
F
F
E
R

Mode
/1, 5

~

AO-A15

-

Game
Paddle s

"'

r--

....

00-07

CS

MC6846
ROM
lia Timer

CS

l
A
T
C
H
i..-

2

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristics

Symbol

Value

V
°e

T stg

+ 70
-65 to + 150

Symbol

Value

Unit

()JA

50
100

°C/W

Vee

-0.3 to

Input Voltage Any Pin

Vin

-0.3 to

Operating Temperature

TA

o to

Storage Temperature

Unit

+ 7.0
+ 7.0

Supply Voltage

V
°C

Vec!.

THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Ceramic
Plastic
Cerdip

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to
an appropriate logic voltage (e.g., either VSS or

60

3-470

MC6847. MC6847V

DC (STATIC) CHARACTERISTICS (VCC=5.0 V ±5%, VSS=o.O v, TA=O°C to 70°C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

Input High Voltage
ClK
Other Inputs

VIH

VSS+2.4
VSS+2.0

-

VCC
VCC

V

-

Input low Voltage
ClK
Other Inputs

Vil

VSS-0.3
VSS-0.3

-

VSS+0.6
VSS+0.8

V

Input leakage Current, Force 5.25 V on Pin Under Test,
VCC=55 V ClK, GMO-GM2, INV, INT/EXT, MS, VSS,
000-007, "$../S, "$../G

lin

-

-

2.5

p.A

-

±10

p.A

Characteristic

Three-State (Off State) Input Current OAO-OA 12
Force 2.4 V and 0.4 V on Pin Under Test

IOl

-

Output High Voltage (Cload = 30 pF, Iload = -100 p.A

RP, HS, FS

VOH

2.4

-

-

V

Output High Voltage (Cload = 55 pF, Iload = -100 p.A)

OAO-OA12

VOH

2.4

-

-

V

Output low Voltage (Cload- 30 pF, Iload = 1.6 mAl

RP, HS, FS

VOL

-

-

VSS+O.4

V

Output Low Voltage (CLoad= 55 pF, ILoad = 1.6 mAl

OAO-OA12

VOL

-

-

VSS+O.4

V

Output High Current (Sourcing)
(VOH = 2.4 V)

All Outputs (Except
cPA, cPB, Y, and CHB)

IOH

-100

-

-

p.A

Output Low Current (Sinking)
(VOL =0.4 V)

All Outputs (Except
cPA, cPB, Y, and CHB)

IOL

1.6

-

-

mA

Cin

-

-

7.5

pF

Internal Power Dissipation (Measured at T A = 0 to 70°C)

PINT

-

-

600

mW

Chroma cPA Voltage (Figure 3)
(CLoad = 20 pF, RLoad = 100 k!l)
(Note 1)

VIH
VR
VOL

1.8
1.34
0.8

2.0
1.5
1.0

2.2
1.66
1.2

V

Chroma cPB Voltage (Figure 3)
(CLoad = 20 pF, RLoad = 100 k!l)
(Note 1)

VIH
VR
VOL

2.0
1.5
1.0
1.25

2.2
1.66
1.2
1.43

V

VBurst

1.8
1.34
0.80
1.07

Vs
VBlank
VBlack
VWL
VWM
VWH

0.9
0.63
0.58
0.51
0.40
0.27

1.0
0.77
0.72
0.65
0.54
0.42

1.1
0.9
0.83
0.75
0.65
0.53

Chroma Bias Voltage (Cload = 20 pF, RLoad = 100 k!l)

VR

0.27 VCC

0.3 VCC

0.33 VCC

V

Resistor % of VSS Tracking (Analog Outputs Linearity Error)

RT

-

1.0

3.0

%

Input Capacitance (Vin = 0, T A = 25°C, f = 1.0 MHz)

Luminance Y Voltage (Figure 3)
(CLoad = 20 pF, RLoad = 100 k!l)
(Voltage Synchronization)
(Voltage Blank)
(Voltage Black)
(Voltage White Low)
(Voltage White Medium)
(Voltage White High) (Note 1)

All Inputs

V

NOTE 1: The specified minimum and maximum number reflect performance of the VOG of the specified temperature range. Overlapping voltage levels will not occur. Refer to Figure 2.

I

MC6847 • MC6847V

POWER CONSIDERATIONS
The average chip-junction temperature. T J. in °C can be obtained from:
TJ=TA+(PO-8JA)
Where:
T A & Ambient Temperature. °C
8JA!Ii Package Thermal Resistance. Junction-to-Ambient. °C/W

I

(1)

PO- PINT+ PPORT
PINT- ICC x VCC. Watts - Chip Internal Power
PPORT- Port Power Oissipation. Watts - User Oetermined
For most applications PPORTA
trA
tfCA
tfA

-

100
100
100
12

-

100
100
100
100
100

ns

trCB
trB
tfCB
tfB

Color Burst Rise Time on B Output

tCBr

-

Color Burst Fall Time on B Output

tCBf

-

100
100

ns
ns

12
12

Chroma Phase Delay (Measured with Respect to "Y" Output)
 A
B

tYA
tYB

140
140

ns

11

Field Sync (FS) Delay

Fall
Rise

Chroma Rise and Fall Times
(A Rise Time)
(A Fall Time)
(B Rise Time)
(B Fall Time)

-

-

-

-50
-50

Luminance Rise Time

try

-

100

ns

12

Luminance Fall Time

tfy

-

100

ns

12

Horizontal Sync Rise Time on Y Output

tHr

-

100

ns

12

Horizontal Sync Fall Time on Y Output

tHf

-

100

ns

12

Horizontal Blanking Rise Time on Y Output

tHBr

-

100

ns

12

Horizontal Blanking Fall Time on Y Output

tHBf

-

100

ns

12

Front Porch Duaration Time (7 x lit)

tFP

1.8

24

p's

12

Back Porch Duration Time (17.5x l/f)

tBP

4.5

5.1

p's

12

Left Border Duration Time (29.5x lit)

tLB

7.5

8.3

p's

12

Right Border Duration Time (28 x l/f)

tRB

7.5

8.3

p's

12

Color Burst Duration Time (10.5x l/f)

tCB

2.7

3.2

p's

12

FIGURE 3 -

AO-A12,

FS, RP, HS

24 k

A,B, Y, CHB

4.75 V
MMD6150
or Equiv.

Test
Point

TEST LOADS

2.50 kl1

TestPoint~

r

100 k

MMD7000
or Equiv.

3-473

I

MC6847. MC6847V

FIGURE 4 -

CLOCK AND LONG CYCLE HORIZONTAL ACCESS TIMING

tCLKf ---l~I"'-tCLKr

elKlN,te 11

r--

DAO-DA3

I

DDO-DD7, CSS

NOTES:
1. The VDG may power-up using either the rising or falling edge of the clock (dotted line).
2. Transitions of DA4-DA 12 occur outside the display area. DAO-DA3 access the 16 bytes of data displayed during each scan line in the display area.
3. Long cycle timing applies to CG1, RG 1, RG2, and RG3 modes (see Table 31. AI G is high; AS, INT I EXT, and I NV input levels do not affect
the VDG in long cycle modes.
4. Usable RAM access time for the long cycle may be calculated using the following equation:
tRACl =8e 1/f max - tHDAD max - tDDSmin - tClKr
If address and data buffers are used, the access time must be adjusted accordingly.
5. All timing is measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise specified.

FIGURE 5 -

SHORT CYCLE HORIZONTAL ACCESS TIMING

tClKr~~""'-

ClK

DAO-DA3

DA4

DDO-DD7
CSS, A/G, A/S,
INT/EXT
NOTES:
1. The VDG may power-up using either the rising or falling edge of the clock as shown in Figure 4.
2. Transitions of DA5-DA 12 occur outside the display area. DAO-DA4 access the 32 bytes of data displayed during each scan line in the display area.
3. Short cycle timing applies to the four alphanumeric modes, two semigraphic modes, and to the CG2, CG3, CG6, RG6 modes (see Table 3).
For the four graphic modes, A/G is high and the A/S, INT/EXT, and INV input levels do not affect the VDG.
4. Usable RAM access time for the short cycle may be calculated using the following equation:
tRACS=4 e 1/fmax - tHDA4D max - tDDSmin - tClKr
If address and data buffers are used, the access time must be adjusted accordingly.
5. All timing is measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise specified.

3-474

FIGURE 6 -

3:

n

HORIZONTAL ADDRESS AND VALID DATA SETUP AND HOLD TIMING
(Timing Relationships Shown From Beginning of Line)

0)

00

~
.....

•

DAO~DA3~ ....

Valid Address

Valid Address

I.

DDO~DD7

n
0)
CO

Valid Address

_I

tRACL

I(

II

II

tCHARL

II

teA

II~

II

DA4

II

..1'

A..~:-X~_-:'-:'-=-

.,.

Valid Address
Valid Address

II

~~_X:-~=_.A

:_-:.x=.:.=-:_")(

:~/J/)lmI/llJ)lim;jJj;uii/M~i§~~jJ/7///////JII/)I//;(I/IJ!!IIXZ~~ii.a~

11111111111111111111111111((1111111111111111111111111111 'C

CSS. INV. A/S. INT/EXT
DDO~DD7

~

-Long element/access modes: CG1, RG1, RG2, RG3
··Short element/access mode: CG2, CG3, CG6, RG6, Alphanumerics, Semi graphics

(J'I

FIGURE 7 -

VERTICAL ADDRESS, ROW PRESET AND HORIZONTAL SYNCHRONIZATION TIMING

RP
I.

tWHS
N~2

DA5~DA12'

Valid Address

~

~

Valid Address

U)

~

~
.....
-<

~I

(First Character on Screen After Border)

DAO~DA3

DDO~DD7

3:

Valid Address

_I.

_I.

tHSRP
N~3

I 22ons~fffffffflll)wffh'$I.X
Begin Ripple Through Vertical Address Counter

NOTES
1. All timing IS measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise specified
2. HS pulse width may be determined by tWHS ~ 16.5.1/f- tDHSF + tDHSr
3. HS to RP may be determined by tHSRP~3.5.1/f-tDHSr+tDRPf
4. RP pulse width may be determined by tWRP ~ 3.5.1 If - tDRPf + tDRPr
5. DA5~DA 12 will change dUring the Inactive portion of the display
6. tpHS=227.5.1/f
7 tDOT = y, f

..

Valid Address

C

MC6847- MC6847V

FIGURE 8 -

FIELD SYNC (FS) TIMING

ClK

I
~-----------------tPFS------------------~

Note 2
NOTES:
1. tWFS=32.tPHST= 32.(277.5.1/f)
2. tPFS=262.tPHST=262.(227.5.1/f) for MC6847
tpFS=262.5.tPHST=262.5.(227.5.1/f) for MC6847Y

FIGURE 9 -

MEMORY SELECT (MS) TIMING

MS
Note 1
tDMSV

MAO-MA12

Valid Address

Valid Address

Valid Address

NOTES:
1. MS is asserted asynchronously with respect to ClK.

3·476

MC6847. MC6847Y

FIGURE 10 - VIDEO AND CHROMINANCE OUTPUT WAVEFORM RELATIONSHIPS

TFP

tHST
Note 4 - - - - - - - - - - - - - - - + 1
~
-------tAVB - - - - - - - - - .-1
I - Left Border
Note 3
Right Border I
tBP ~
-"'-1

1

~I~~~~~~I]Q~
~~:·I
Y

WL

BlaCH

N':;~2

.

~~

·~I·tRB1
tHBNK--.!

I

Note 5

----~
End of
Horizontal
Sync

t

I
I

tCB

I

A/G + A/GeCSS

cpB

VBurst
VOL
(Burst is removed
for
A/GeCSSeGMOl

~--r---

A/GCSS

I

I
I

I
I
I

I
I

I
A/G + A/GeCSS

= 0

I I
I
I
I I

I

---ir-~~D1

I I

r iiA./G

l

I

A/GeCSS
A/GeCSS

I Yellow II

Red
Blue

A/GeCSSIL._ _.L.-..;G::.;r.;;.;ee;.;.;n---ill
NOTES:
1. tHCD=3.5.1/f
2. tAV= 128.1/f
3. tAVB = 185.5.1/f
4. Refer to Figure 7
5. tHBNK=42.1/f

FIGURE 11 - CHROMA PHASE DELAY

Y _ _ _ _ _. J

cpA __________

~-'

cpB ____________¥

3-477

I

b

Magenta Orange

......B_U_ff_...,kJ

I

I

1

I

MC6847. MC6847Y

FIGURE 12 - TIMING DIAGRAMS
VIDEO RISE AND FALL TIMES (Illustrates Seginning of One Horizontal Line)

Vsync

VSlank

I

y

VSlack
VWL
VWM
VWH

tCSr
~S------------~l~O~%~

VSurst
VOL

tCSf

tfC~A

~A----------------------------------~~
VOL

MC6847. MC6847V

FIGURE 13 -

DISPLAY AREA TIMING

Vertical Blanking 13 H Lines

.~

Top Border 25 H Lines

--

~-

"a;

u::

.r:
u
co

w

(f)

Active Display Area 192 H Lines

(f)

~
::;

~
::;

N

N

~

C"!i

~

~

c
.2 10
Ql

g

~
(f)

Z
(f)

Ql
C

::;
N

~ ~
::;
~

N

Falling Edge of

A and cJ>B).
POWER INPUTS - VCC requires + 5 volts ± 5%. VSS
requires zero volts and is normally ground. The tolerance and
current requirements of the VDG are specified in the Electrical Characteristics.
VIDEO OUTPUTS (cJ>A, cJ>B, Y, CHB) - These four analog
outputs are used to transfer luminance and color information
to a standard NTSC color television receiver, either via the
MC1372 RF modulator or via drivers directly into Y, cJ>A, cJ>B
television video inputs (see Figures 10,11, and 12).

NOTE
A system with the MC6847 VDG and the MC1372
video modulator forms a transmitter, transmitting at
61.2 MHz (channel 3) or 67.25 MHz (channel 4) depending on component values chosen. This being a Class I
TV device, care must be taken to meet FCC requirements Part 15, Subpart H. However, if the composite video output from the MC1372 were to drive the
television directly, Section 15.7 of the FCC specification must be adhered to.

Luminance (Y) - This six level analog output contains
composite sync, blanking and four levels of video luminance.

cJ>A - This three level analog output is used in combination with cJ>B and Y outputs to specify one of eight colors.
cJ>B - This four level output is used in combination with
cJ>A and Y outputs to specify one of eight colors. Additionally, one analog level is used to specify the time of the color
burst reference signal.

SIGNAL DESCRIPTION
DISPLAY ADDRESS OUTPUT LINES (DAO-DA12)

Thirteen address lines are used by the VDG to scan the
display memory as shown in Figures 4-7. The starting address of the display memory is located at the upper left corner of the display screen. As the television sweeps from the
left to right and top to bottom, the VDG increments the
RAM display address. The timing for two accesses starting
at the beginning of the line is shown in Figure 6. These lines
are TTL compatible and may be forced into a highimpedance state whenever MS (pin 12) goes low. AO-A3

FIGURE 15 -

Chroma Bias (CHB) - This pin is an analog output and
provides a DC reference corresponding to the quiescent
value of cJ>A and 4>B. CHB is used to guarantee good thermal
tracking and minimize the variation between the MC1372 and
MC6847. This pin, when pulled low, resets certain registers
within the chip. In a user's system, this pin should not normally be used as an input. It is used mainly to enhance test
capabilities within the factory.

COLOR COMPOSITE VIDEO TO COLOR MONITOR

+5V
560

360

Adjust for
de Output

14

... 0.4 mA pp Typ

12

4.3V

1---1~----£

2N4401

MC1372

750

Color

,....._--"IM...--~ Composite

10
750

8
Adjust for
ae Output

Ratio: Color to Video Trim

470
3.9k*
......- - - - - - - - '

3-480

"" 2.0 V:r
'='

Video
Out

*3.9 kll is MC1372 effective load,
pin 12 voltage doesn't move and is virtual ground.

MC6847 • MC6847Y

SYNCHRONIZING INPUTS (MS, CLK)
THREE-STATE CONTROL - (MS) is a TTL compatible
input which, when low, forces the VDG address lines into a
high-impedance state, as shown in Figure 9. This may be
done to allow other devices (such as an MPU) to address the
display memory (RAM),

The HS pulse coincides
HORIZONTAL SYNC (HS)
with the horizontal synchronization pulse furnished to the
television receiver by the VDG (see Figure 7). The high-tolow transition of the HS output coincides with the leading
edge of the horizontal synchronization pulse and the low-tohigh transition coincides with the trailing edge.

CLOCK (CLK) - The VDG clock input (ClK) requires a
3.579545 MHz (standard color burst) TV crystal frequency
square wave. The duty cycle of this clock must be between
45 and 55% since it controls the width of alternate dots on
the television screen. 'The MC1372 RF modulator may be
used to supply the 3.579545 MHz clock and has provisions
for a duty cycle adjustment. The VDG will power-up using
either the rising or falling edge of the clock. The dotted line
on the ClK signal in Figure 4 indicates this characteristic of
latching in data on either clock edge.

ROW PRESET (RP) - If desired, an external character
generator ROM may be used with the VDG. However, an external four bit counter must be added to supply row addresses. The counter is clocked by the HS signal and is
cleared by the AP signal. RP pulses occur in all alphanumeric
and semigraphics modes; no pulses are output in the full
graphic modes. AP occurs after the first valid 12 lines.
Therefore, use an FS clocked preloadable counter such as a
74lS161 as shown in Figures 7, 14, and 23.
MODE CONTROL LINES INPUT (A/G, A/S, INT/EXT,
GMO, GM1, GM2, CSS, INV)
Eight TTL compatible inputs are used to control the
operating mode of the VDG. A/S INT/EXT, CSS, and INV
may be changed on a character-by-character basis. The CSS
pin is used to select between two possible alphanumeric colors when the VDG is in the alphanumeric mode and between
two color sets when the VDG is in the Semigraphics 6 or full
graphic modes. Table 1 illustrates the various modes that can
be obtained using the mode control lines. There are two different types of memory access concerning these modes,
they are a short and a long access cycle, which differ by a

SYNCHRONIZING OUTPUTS (FS, AS, AP)
Three TTL compatible outputs provide circuits, exterior to
the VDG, with timing references to the following internal
VDG states:
FIELD SYNC (FS) - The high-to-Iow transition of the FS
output coincides with the end of active display area (see
Figure 8). During this time interval, an MPU may have total
access to the display RAM without causing undesired flicker
on the screen. The low-to-high transition of fS coincides
with the trailing edge of the vertical synchronization pulse.

FIGURE 16 - EXTERNAL CHARACTER GENERATOR ROW COUNTER FOR MC6847

+5V

6
PO

RP

P1

P2

+5V

P3
VCC

MR

CEP

From
MC6847

FS
AS

9

PE

CET

74LS161

2

GND

CP~
00

01

02

03
11

Row Address
(Zero Through Eleven)

3-481

16

I

MC6847- MC6847V

TABLE 1 -

A/G

I

A/S INT/EXT

INV

0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1

0

1
1
1
1
1
1
1
1

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X

1

GM2 GMl

1
1

MODE CONTROL LINES (INPUTS)
GMO

X
X
X
X
X
X
0
0
0
0

X
X
X
X
X
X
0
0
1
1

0

1
1
1
1

0
0

0

1
1

0

Alpha/Graphic Mode Select

X Internal Alphanumerics
X Internal Alphanumerics Inverted
X External Alphanumerics
X External Alphanumerics Inverted
X Semigraphics 4 (SG4)
X Semigraphics 6 (SG6)
0 64x64 Color Graphics One (CG1)
1
1
1
1

shift of one full 3.58 MHz cycle. One of the differences between these access times, in the short access time frame, is
a shift of one full 3.58 MHz cycle from the corresponding
normal long access time frame, as shown in Figure 6. The
modes us'lng short access times read memory twice as often
as the long access modes.

OPERATION OF THE VDG
A simplified block diagram of the VDG is shown in Figure
17a and a detailed block diagram is shown in Figure 17b.
The externally generated 3.58 MHz color burst clock drives
the VDG. Referring to Figures 11 and 12, note that the
horizontal screen span from blanking to blanking is 193.1
clock periods (,.; 53.95 its). The display window is offset from
the left-hand edge by 283 periods and lasts for 128 periods
(35.75 its). Of the 242 lines on the vertical screen from blanking to blanking, 192 lines are used for the display. The
display window is offset from the top by 25 lines. Under the
constraint of the master clock, the smallest display element
possible for the VDG is half period of the 3.58 MHz clock
wide by one scan line high. All other display elements are
multiples of this basic size.
DISPLAY MEMORY ADDRESS DRIVERS
The address drivers normally drive the video refresh address into the display memory so characters may be
displayed on the CRT. When the memory select pin (MS) is
pulled low by an external decoder, the driver outputs go to a
high-impedance state so external three-state drivers may
switch the MPU produced address onto the display memory
address bus; the MPU may directly manipulate data in the
display memory.
VIDEO TIMING AND CONTROL

This subsystem of the VDG includes the mode decoding,
timing generation, and associated row counter logic, and
uses the 3.58 MHz color frequency to generate horizontal
and vertical timing information (via linear shift register
counters), which the video and chroma encoder uses to
generate color video information. The horizontal timing for
the VDG is summarized in Figure 7. Ten and one-half cycles
of the 3.58 MHz subcarrier are transmitted on the back porch

128x64 Resolution Graphics One (RG1)
128 x 64 Color Graphics Two (CG2)
128 x 96 Resolution Graphics Two (RG2)
128 x 96 Color Graphics Three (CG3)
128x 192 Resolution Graphics Three (RG3)
128 x 192 Color Graphics Six (CG6)
256 x 192 Resolution Graphics Six (RG6)

# of Colors
2

8
8
4
2
4
2
4
2
4
2

of every horizontal blanking period. This color burst is suppressed during vertical sync and equalizing intervals. Color
burst is also suppressed in the most dense two color graphic
modes. This leads to some interesting rainbow effects on the
d'isplay which is frequency ana pattern dependent. The vertical timing for the VDG is given in Figure 18. Vertical retrace
is initiated by the luminance Signal being brought to the
blanking level. The vertical blanking period begins with three
lines of equalizing pulses followed by three lines of serrated
vertical sync pulses followed by three more lines of equalizing pulses. The remaining vertical blanking period contains
the normal horizontal sync pulses. The equalizing and serration pulses are at half line frequency. Notice the difference in
spacing between the last horizontal sync pulse and the first
equalizing pulse in even and odd fields. It is the half line difference between fields that produces the interlaced picture in
a frame. Vertical timing between fields for the non-interlaced
VDG, on the other hand, is identical. The equalizing and serration pulses are, however, at the horizontal frequency.
The 3.58 MHz color frequency is also used to clock the
video shift register load counter. This counter and the video
shift clock inhibit circuitry derive the dot-clock for the output
of the video shift registers and the load signals for the video
shift registers' input latches. The vertical and horizontal address counters generate the addresses for the external
display memory.
INTERNAL CHARACTER GENERATOR ROM
Since many uses of the VDG will involve the display of
alphanumeric data, a character-generator ROM is included
on the chip. This ROM will generate 64 standard 5x 7 dot
matrix characters from standard 6-bit ASCII input. A standard character set is included in the MC6847 although the
ROM is custom programmable.
INTERNAL/EXTERNAL CHARACTER GENERATOR
MULTIPLEXER
The internal/external multiplexer allows the use of either
the internal ROM or an external character generator. This
multiplexer may be switched on a character-by-character
basis to allow mixed internal and external characters on the
CRT. The external character may be any desired dot-pattern
in the standard 8 x 12 one-character display matrix, thus
allowing the maximum 256 x 192 screen density.

3-482

MC6847. MC6847V

FIGURE 17a -

SIMPLIFIED VDG BLOCK DIAGRAM

MPU Address Bus

+5

MPU Data Bus

OV

VDD VSS
VDG
Refresh
RAM
512 Bytes to
6K Bytes
CC

Timing
and
Control

INT/EXT

8
'A/S

'A/G
GM2
GM1
GMO
CSS

6,7 or 8

Character
Generator
ROM

y
Parallel To
Serial Shift Register,
Video Chroma Encoder

Luminance

cpA

VIDEO AND COLOR SUBSYSTEM

called Y. The luminance signal, Y, and the two chrominance
outputs, cpA (R- Y) and cpB (B- Y), can be combined
(modulated) by an MC1372 into a composite video signal
with color. Figures 8,9, 10, and 16 show the relationship between the luminance and chrominance Signals and the resultant color.

The 8-bit output of the internal/external multiplexer is
serialized in an 8-bit shift register clocked at the dot-clock
frequency.
The luminance information from the shift register is summed with the horizontal and vertical sync signals to produce
a composite video signal less the chrominance information,

3·483

iii
3:

(")

m

00
~

FIGURE 17b - DETAILED VDG BLOCK DIAGRAM

"'-I

•

Display Address Bus

3:
n
m

Display Data Bus

00
~

"'-I

-<

A/G

RP

A/S

iNTI
EXT

U)

~

(X)
~

I
jI

INV

GM2
GMl

GMO

I
I
I
I
'Horizontal Tlmlngl

II

+5V

l.S.R.C

,

,

II

Non-Interlaced

63rd and 64th ns Counted
VDD

VSS

I

VDG

3.58 MHz

ClK

CHS

.. A

.. S

IR-YI

IS-YI

3:
n
0)

FIGURE 18 - NON-INTERLACE VERTICAL TIMING
(For Interlace Vertical Timing Use Inserts)

CO

~
......

+l

-+I !PHS!+-

!-05tPHS

~tPHSI+-

---.j

-...jtPHSk-

•

k - 0.5tPHS

3:

,nnr

n0)

:......

_t:=

3 tPHS

--+l- 3 tpHS

~

-.j--

3 tPHS

3 tPHS ~ 3 tPHS

--.j
~

19tPHS

-

10:

Odd Fleldlnlerlaced

---.!-

3 tpHS

-.j

19H

<

-I

Even Field Interlaced·

"Y"

Sync
Blank

y

~I

Black

WL
WM
WH

~

~

(X)

c.n

~

VIH .:!.
VOL

~

~/Gj!c;S G/~;;.css

Gii'iocss

V,H
VR

~

FS

_

~

~---

-

~

U

"~A"

- --

tWFS-~~---~

J I of 31.468 kHz clocks
11131.4$8 kHz) = 31.7783.5

1. [

Non-Parentheses=1 of 3.58 MHz Clocks

;

~

"418"

G/AoCSS

DO
GiAoCSS

RP

~

-

G/A+G/AoCSS

VOL

NOTES

~

-o'GU

~B VBU:S~
~A

G/A·CSS

'

r-n

~ G(A~CSS ~

''';'''"1''1 ~i:r'·"',"
GI AoCSS

1 AoCSS

G/A+G/A-CSS
0

-Note: No Row!'resetOccurs Here
..

-tHBNK could actually be considered as part of the border especially for purposes of writing to the screen. The same holds

GIAoCSS

I
First Row Preset to Occur
Comes After the First Active
Row of Characters

true for the upper border

113.58 MHz=279.366 ns
Time marks 455 and 0 are the same points In time

tHST ~ 1227.5-01 x 279.366 ns= 83.5.5
= 1455-227.5) x 279.366 ns=83.5.s
tWHS = 1455-4381 x 279.366 ns~ 4. 75.5
Lower Border= 1524-472) x 31.7783 "s-tHBNK
= 1.6525 ms-l1.6 ns= 1.fA ms
Upper Border= 188- 38) x 31.7783I-1s- tHBNK =

= 1.5889"5-11.6,,s= 1.58 ms
2. tRP= 12 hOrizontal scan lines
~

"~A"

"""""
----Jv---uO

l~_-----------------

U_tRP_U'
-+ll+-tHSRP
Note 2
~~tWRP

Example TIming CalculatIons

3 tVBNK

~

20.tPHS = 20.1227.5.1/0

4. IF = 262.tPHS = 262.1227.5.1/f) for Non-Interlace
tF = 262.5. TpHS = 262.5.(227.5.1/t) for Interlace

..

MC6847. MC6847V

DISPLAY MODES

The 5 x 7 character font is positioned two columns to the
right and three rows down within the 8 x 12 character element. Six bits of the 8-bit data word are typically used for the
internal ASCII character generator. The remaining two bits
may be used to implement inverse video, color switching, or
external character generator ROM selection on a characterby-character basis. For those who wish to display lower case
letters, special characters, or even limited-graphics, an external ROM may be used. If such external ROM is used, all of
the 8 x 12 picture elements, or pixels, in the character element can be utilized. Characters may be either green on a
dark green background or orange on "a dark orange
background, depending on the state of the CSS pin. The invert pin can be used to display dark characters on a bright
background.

There are two major display modes in the VDG. Major
mode 1 contains four alphanumeric and two limited graphic
modes. Major mode 2 contains eight graphic modes. Of
these, four are full color graphic and four restricted color
graphic modes. The mode selection for the VDG is summarized in Table 2. The mnemonics of these fourteen modes
are explained in the following sections.
In major mode 1 the display window is divided into 32 columns by 16 character element rows thus requiring 512 bytes
of memory. Each character element is 8 half periods by 12
scan lines in size as shown in Figure 19. The area outside the
display window is black.
The VDG has a built-in character generator ROM containing the 64 ASCII characters in a 5x 7 format (see Figure 20).

II
TABLE 2 - SUMMARY OF MAJOR MODES
Major Mode 1 - Alpha Modes

Title

Memory

Alphanumerics
Iinternal)

512x 8

Display Elements

;-T

Colors

Title

Memory

2

Semigraphic 4

512x8

Display Elements

2-1 H 5

T

7

~
2

-t

0.
: •••

:

~EI,m'",

12
~

1==1
..

.. ·· -t
. ·· ~

~
Alphanumerics
IExternal)

Colors

512x8

0

12

Semigraphic 6

2

512x8

~

Major Mode 2 Title
64 x 64 Color Graphic

128 x 64 Graphics"
128 x 64 Color Graphic
128 x 96 Graphics"
128x96 Color Graphic
128 x 192 Graphics"
128 x 192 Color Graphic
256 x 192 GraphiCS

Graphics Modes

Memory

Colors

1 kx8
1 kx8
2kx8
1.5 kx8
3kx8
3kx8
6kx8
6kx8

4
2
4
2
4
2
4
2

Comments
Matrix 64 x 64 Elements
Matrix 128 Elements Wide by
64 Elements High
Matr'lx 128 Elements Wide by
96 Elements High
Matrix 128 Elements Wide by
192 Elements High
Matrix 256 Elements Wide by
192 Elements High

"Graphics mode turns on or off each element. The color may be one of two.

3·486

~E"m'c'

8

4

MC6847. MC6847Y

FIGURE 19 -

ALPHANUMERIC MODE (INTERNAL)

FIGURE 20 -

512 Characters (32x 16)
Typical Character
00000000
00000000
oooo~ooo
00• • • 00
• - Dot Off ii0801~~~
00.0 0.0
o - Dot Lit
11(:)1
00.000.0
00. . . .00
••gj~
00.000.0

MD4= INV=D4
MD7= AS= 07

........
11111111

88"~~~8

00000000
00000000
Inverted
Black Character
Orange or Green
Background (Selectable)

AVAILABLE ALPHANUMERICS

o = Inverted Character 0_

..ae..o.

HiE

Illuminated Background,
Dark Character

_ 0

_1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ 9 _ A _ B

(ii>

ABC

0

E

F

G

H

I

J

K

_c _ 0
L

M

_ E _ F

N

0

PQRSTUVWXYZI

Normal
Black Background
Orange or Green
Character (Selectable)

J_

0

1

2

#

$

0'0

3

4

5

6

7

8

9

L@OOGeooeOOOOGGoe
L00000C!)OOOOO • • • • •

Character Source:

Internal - 6 Bit ASCII Generator ROM On Chip or User Definable
External - Users ROM

L

•••

COOO • • • • • • • • •

8008000800 • • • • • •
THE 128x 64 COLOR GRAPHICS TWO (CG2) MODE The 128 x 64 color graphics mode generates a display matrix
128 elements wide by 64 elements high. Each element may
be one of four colors. A 2k x 8 display memory is required.
The display RAM is accessed 32 times per horizontal line.
Each pixel equals two half-clocks by three scan lines,

The two limited graphic modes are Semigraphics 4 and
Semigraphics 6. In Semigraphics 4, the 8 x 12 dot character
block is divided into four pixels (each pixel is four half-clocks
by six scan lines!. The four low-order bits lDDO-DD3) of each
incoming byte of data select one of sixteen possible illumination patterns while the next three bits lDD4-DD6) determine
the color of the illuminated elements. The most significant
bit is unused. Figure 21 shows the color and pattern selections. In Semigraphics 6 the 8 x 12 dot character block is
divided into six pixels, each four half-clocks by four scan
lines. The six low-order bits of each byte of incoming data
select one of 64 possible illumination patterns while the CSS
input and the high-order data bits lDD6-DD7) determine the
color of the illuminated elements.
The display window in major mode 2 (full graphics) has a
less rigorous format than in major mode 1. The display
elements vary from one scan line to three scan lines in
height. The length of the display element is either eight or
sixteen half-periods wide. Each display element is divided into four or eight pixels. The former corresponds to a full color
mode while the latter a restricted color mode, like the
semigraphics modes, represents illumination data. When it is
high the pixel is illuminated with the color chosen by the color set select (CSS) pin. When it is low the pixel is black. In
the full color modes, pairs of data bits choose one of four
colors in one of two color sets defined by the CSS pin.
Depending on the state of the CSS pin, the area outside the
display window is either green or buff. The display formats
and color selection for this major mode are summarized in
Figure 19.

THE 128 x 192 RESOLUTION GRAPHICS THREE (RG3)
MODE - The 128x 192 graphics mode generates a display
matrix 128 elements wide by 192 elements high. Each element may be either ON or OFF, but the ON element may be
one of two colors selected with the color set select pin. A
3k x 8 display memory is required. The display RAM is accessed 16 times per horizontal line. Each pixel equals two
half-clocks by one scan line.

THE 64x64 COLOR GRAPHICS ONE (CG1) MODE The 64 x 64 color graphics mode generates a display matrix
of 64 elements wide by 64 elements high. Each element may
be one of four colors. A 1kx8 display memory is required.
The display RAM is accessed 16 times per horizontal line.
Each pixel equals four half-clocks by three scan lines.

THE 128 x 192 COLOR GRAPHICS SIX (CG6) MODE The 128 x 192 color graphics mode generates a display 128
elements wide by 192 elements high, Each element may be
one of four colors. A 6k x 8 display memory is required. The
display RAM is accessed 32 times per horizontal line, Each
pixel equals two half-clocks by one scan line.

THE 128x64 RESOLUTION GRAPHICS ONE (RG1)
MODE - The 128 x 64 graphics mOde generates a matrix
128 elements wide by 64 elements high. Each element may
be either ON or OFF. However, the entire display may be one
of two colors, selected by using the color set select pin. A
1k x 8 display memory is required. The display RAM is accessed 16 times per horizontal line. Each pixel equals two
half-clocks by three scan lines.

THE 256 x 192 RESOLUTION GRAPHICS SIX (RG6)
MODE - The 256 x 193 graphics mode generates a display
256 elements wide by 192 elements high. Each element may
be either ON or OFF, but the ON element may be one of two
colors selected with the color set select pin. A. 6k x 8 display
memory is required, The display RAM is accessed 32 times
per horizontal line. Each pixel--equals one half-clock by one
scan line.

3-487

THE 128 x 96 RESOLUTION GRAPHICS TWO (RG2)
MODE - The 128 x 96 graphics mode generates a display
matrix 128 elements wide by 96 elements high, Each element
may be either ON or OFF. However, the entire display may
be one of two colors selected by using the color set select
pin. A 1.5k x 8 display memory is required. The display RAM
is accessed 16 times per horizontal line, Each pixel equals
two half-clocks by two scan lines.
THE 128 x 96 COLOR GRAPHICS THREE (CG3) MODE The 128 x 96 color graphics mode generates a display 128
elements wide by 96 elements high. Each element may be
one of four colors. A 3k x 8 display memory is required. The
display RAM is accessed 32 times per horizontal line. Each
pixel equals two half-clocks by two scan lines.

I

MC6847. MC6847V
TABLE 3 -

DETAILED DESCRIPTION OF VDG MODES

Color

VDG Pins
MS

I

G/A

SiA

EXTIINT GM2

GMI

GMO

CSS

INV

Character Color

Background

Green
Black
Orange
Black

Black
Green
Black
Orange

Green
Black
Orange
Black

Black
Green
Black
Orange

Lx

C2

Cl

CO

0

X

X

I

0
0

0

1

I

0

Lx

Cl

0

X

CO

0
0

1
Ci

CO

0

0

Lx

Same color as
Color Graphics
One

Black

Black
Black

Color
Black
Green

Yellow
Blue
Red
Buff
Cyan
Magenta
Orange
Color
Black
Green
Yellow
Blue

Display Mode

Border
Black

32 Characters

per row
16 Characters

32 Characters
per row
16 Characters

64 Display elements
per row
Black

Black

Red
Black
Buff
Cyan
Magenta
Orange

32 Display elements

64 Display elements
per row
48 Display elements

I Color
Green
Yellow
Blue
Red
Buff
Cyan
Magenta
Orange
Color
Black
Green
Black
Buff

1

Green

64 Display elements

per row
Buff

64 Display elements

Green

per row

128 Display elenlents

\

64 Display elemehts
Buff

:
128 Display elements

Green

per row
64 Display elements

Buff
Same color as
Resolution
Graphics One

Green

Buff
Same color as
Color Graphics
One

Green

Same color as
Resolution
Graphics One

Green

128 Display element~
per row

~ r~:~lay

elements \,

128 Display elements

per row
96 Display elements

Buff

rows
128 Display elements
per row

In

192 Display elements
Buff

Same color as
Color Graphics
One

Green

Buff
Same color as
Resolution
Graphics One

Green

Buff

3·488

128 Display elements

per row
192 Display Elements
256 Display elements

per row
192 Display elements

MC6847- MC6847V
TABLE 3 -

DETAILED DESCRIPTION OF VDG MODES
(Continued)

TV ScrMn

Comments

VDG D.t. Bus
D8IIIiI

4~s.:i.1

1

r1!oJ ..-1

I I I I I I I II

~~

-.exIra

......

-.-

ASCII Code

-

The ALPHANUMERIC INTERNAL mode uses an Internal character
generator (which coptains the following five dot by seven dot
characters
,@ABCDEFGHIJKLMNOPORSTUVWXYZ
I\JlI_SP !"I$%&'( 1·+,-,0123456789:;< = >'. The SIX bit
ASCII code leaves two bits free and these may be externally con·
nected to the mode pins IG/A, S/A, EXT liNT, GM2, GM1, GMO,
CSS or INVI.

Internal Alphanumerics

..... 8--1

The ALPHANUMERIC EXTERNAL mode uses an external character
generator as well as a row counter. Thus, custom character fonts or

I'"::::'

I I I I I I I II

~:::
~

1
12

One Row of
Custom Character~

The SEMIGRAPHICS FOUR mode uses an internal "course graphics"

~4"'4"
fr--;...-..;.
6

L3

generator in which a rectangle (eight dots by twelve dots) is divided
into four equal parts. The luminance of each part IS determined by a

L2

tr--tLo
t6 __ __
L1

graphic symbol sets with up to 256 different 8x 12 dot "characters"
may be displayed.

LIC21C11colL31 L21L11 Loi
One
} Element

corresponding bit on the VDG data bus. The color of Illuminated parts
is determined by three bits.

extra

The SEMIGRAPHIC SIX mode is similar to the SEMIGRAPHIC FOUR
mode with the following differences. The eight dot by twelve dot rectangle is divided into six equal parts. Color IS determined by the two
remaining bits

4

L3

L2

•

L1

LO}

~I::enl
The COLOR GRAPHICS ONE mode uses a maximum of 1024 bytes of
display RAM in which one pair of bits specifies one picture element

13~

i

L71 L61

The RESOLUTION GRAPHICS ONE mode uses a maximum of 1024
bytes of display RAM In which one bit specifies one picture element

L51l41 L31 L21 L 11 La , 3
l

The COLOR GRAPHICS TWO mode uses a maximum of 2048 bytes
of display R AM in which one pair of bits specifies one picture element

The RESOLUTION GRAPHICS TWO mode uses a maximum of 1536
bytes of display RAM in which one bit specifies one picture element

The COLOR GRAPHICS THREE mode uses a maximum of ':!IJ72 bytes
of display RAM in which one pair of bytes specifies one picture element

""2~

iii

L7

i

The RESOLUTION GRAPHICS THREE mode uses a maximum of

i

':!IJ72 bytes of display RAM in which one bit specifies one picture ele-

i~f

ment

The COLOR GRAPHICS SIX mode uses a maximum of 6144 bytes of
display RAM in which one pair of bits specifies one picture element

The RESOLUTION GRAPHICS SIX mode uses a maximum of 6144

4ti:am i
L7

bytes of display RAM In which one bit specifies one picture element

Lot

3-489

I

MC6847. MC6847V

FIGURE 21 -

SEMIGRAPHIC MODE ENCODING

(a) Data and Display Formats

GEJ

rn!

I I I I I I I I I
D7

D6

D5

D4

~ Chroma

D3

D2

-10(

D1

Luma

DO

----.I

~

+I

Semigraphics 4

4 (PWCLK)

1CSS

I

1 D7

I Os

~ Chroma

1 D5

I

D4 1 D3 1 D2

10(

I

I

I

D1

DO

I

-I

Luma
Semigraphics 6

D5

D4

D3

D2

-L

D1

DO

4L

(b) Color Selection

0

D6
X

SG4
D5
X

D4
X

CSS
X

SG6
D7
X

1
1

0
0

0
0

0
1

0
0

0
0

1

0

1

0

0

1

1

0

1

1

0

1

1

1

0

0

1

0

1

1

0

1

1

0

1
1

1

1

1

1

1

1

0
1

1

1

Luma
DN

FIGURE 22 -

Color

Os
X
0
1
0
1
0
1
0
1

Black
Green
Yellow
Blue
Red
Buff
Cyan
Magenta
Orange

GRAPHIC MODE ENCODING

(a) Data Format

1 D7

D61 0 5

04

,....

I D71
I.

I

(b) Display Format

I...1..
03

021 01

Chroma

D61 D5

I

I

3L CG1

00 IColor Graphic

4 (T 12)

_,

I D,

D41 D31 D2
Luma

IDo I~~:;~~:J
_I

T

L...---'------.J...-----''-----'L

r-~

...J

I I I I I I I I;-'G'
+-I

2 (T/2)

~

...--T----r----r----rl---r-I""TI----r-I-"
I

I

2 (T/2)

0

Border
Green

Resolution
Color Mode
Color
ON
Black
0

Color Mode
Color

ON
0

Green

0
1

1

Yellow

0

Blue

1

1

Red

0

Buff

Green

1

Green

0

Green

1

0

Green

1

Green
Green

1

Buff

0

Black

0

1

Buff

1

Buff

0

1

Cyan

1

Buff

1

Buff

1

0

Magenta

1

Buff

1

Buff

1

1

Orange

3-490

..1..

I
I--..;L.....--L--....J~IL.......-....jLT

2L CG3

2(1/2)-]

r-

L-~_-L_~~I ~G6
2(T/2)~

Short Element Modes

DN+1
0

0

3L CG2

L-~-2-(-TL/2-)~~--~~~

~

I I ~G3
L--...L--L-~-....JI ~G6
...j ~T
1 (T/2)---\
~

Long Element Modes

(c) Color Selection
CSS

2 L RG2

+\ ~T

2 (T/2)

I

..l...

l

MC6847. MC6847Y

TYPICAL SYSTEM IMPLEMENTATION
The block diagram in Figure 23 shows how the VDG is
related to other functional blocks in a typical system
(non-6883). A negative row preset signal (iifS) generated by
the VDG initializes the row scan counter for the external
character generator once every twelve scan lines, while the
negative horizontal sync (RS) acts as clock to this counter.
The negative field sync (FS) generates an interrupt to the
MPU, signifying that the display memory can be updated
without interference with the VDG display function. This
signal must not be confused with the system vertical sync
signal. Field sync is activated by the end of the vertical
display window and deactivated by the trailing edge of vertical sync. This gives the MPU a total of thirty-two scan lines
or 2.03 ms to update the display memory. The MPU
acknowledges the interrupt request from the VDG by bringing the negative memory select input (MS) to the VDG low.
This puts the address bus output from the VDG into highimpedance state, thus relinquishing bus control to the MPU.
The timing relationship of horizontal sync, row preset, and
field sync are shown in Figures 7, 8, and 13.
The display memory is an element-by-element map of the
display window on the screen. The VDG addresses the
display memory storage locations in succession and
translates their contents into luminance and chrominance
levels. The frequency of address update is dependent on the
length of the display element. Recall that display elements in
major mode 1 are four periods and major mode 2 are either
four or eight periods of the master clock. Data from the
display memory is latched on every address transition.
Hence, the data for the first display element must be stable
four or eight periods before the horizontal display window
depending on the display mode selected. This timing requirement is illustrated in Figure 6.
Examination of Figures 21 and 22 reveal that all display
elements within major mode 1 are similar while those within
major mode 2 are largely dissimilar. Therefore, mode switching between alphanumeric modes and semigraphic modes
can be carried out freely. Care must be taken, however,
when performing mode switching in major mode 2. The only
compatible modes are between CG 1 and RG 1, and between
CG6 and RG6. Minor mode switching within the same major
mode in a given ei'ement row can be achieved as long as it is
between compatible modes. It should be quite apparent that
major mode switching on an element-by-element basis is impractical. It can be achieved, however, at the expense of
added component count. The element formats in the VDG
lend themselves to major mode switching between element

rows. The presence of row preset in major mode 1 serves as
a flag for the beginning of a new element row. Detection of
this signal can initiate a major mode switch from 1 to 2.
Display memory size is a function of the display density.
Quite often a graphic display contains shapes that are several
times larger than that of the display elements in the VDG.
This is part'lcularly true of certain video games. Much of the
display consists of a fixed background. The vertical size of a
display element can be doubled or quadrupled by simply ignoring the lowest order or the first two low order vertical addresses, respectively, from the VDG. Reduction of address
lines naturally leads to reduction in memory size. Another
method of memory reduction is to store objects or object
fragments in ROM and store their display addresses in the
RAM portion of display memory. Here, the larger the object
fragment, the greater the memory saving.

ASSOCIATED DEVICES
MC6883 -

SYNCHRONOUS ADDRESS MULTIPLEXER
(SAM)

This device, a linear bipolar companion to the MC6800 or
MC6809E (external clock inputs), is primarily a VDG
transparent-access controller. It allows the microprocessor
to load and store to VDG display memory ("screen RAM")
without waiting for a blank screen interval. Figure 1 shows a
typical system using the SAM and the MC6809E. The inherent interleaved direct memory accesses (IDMA) which
occur, continuously keep the VDG updated with the proper
data (independently of mode), as well as keeping the
dynamic memory (used as system memory with the MC6833)
refreshed. This is done through a IDMA process as well, during the time the VDG does not need display data (horizontal
and vertical sync times).
In addition to being a transparent memory access and
dynamic memory controller, the SAM also functions as an
external clock generator for the MC6800/6809E (slight additional circuitry is required for the MC6800).
MC1372/1373 CHROMA/RF MODULATOR
The MC1372 is a chrominance phase-shift modulator with
built in RF up-converter. The part may be used without the
RF modulator for chroma only, or the RF oscillator may be
defeated and composite chrominance and luminance can be
obtained.
The MC1373 is an RF modulator only (similar to the second half of the MC1372) and can be used to up-modulate
separate luma and chroma signals at the receiver for high
quality video reception.

3-491

I

MC6847 • MC6847V

FIGURE 23 - TYPICAL VDG SYSTEM

Game
Paddles
D~7-------~~-r---------------'---------------------------'-------'

A~+-~~~----~+-----------------+-~

8

M68XX
MPU

latch

o
8

IRQb-------------------------~

ClK

I

ClK

FS Mode

Display
Memory

MS

Control

ToTV Set

A
Y
R-Y
MC1372

B-Y

MC6847
VDG

CHB
D
RF
Tank
3.58 MHz
XTAl

HS

FS RP

INT/EXT
"A/S

External
Character
~----I'--__________-.lRow Generator 0
A
ROM
Row Counter

.---f----.tChar. Add
8

FIGURE 24 -

APPENDIX A
CUSTOM MC6847 ORDERING INFORMATION

PROM MARKING

The following information is required when ordering a
custom M CU. This information may be transmitted to
Motorola in the following media:
PROM(s) MCM2716s or MCM2708s
MOOS disk file
To initiate a ROM pattern for the MCU it is necessary to
first contact your local field service office, local sales person,
or your local Motorola representative.

000

400

xxx = Customer 10

PROMs - The MCM2708 or MCM2716 type PROMs, programmed with the customer program (positive logic sense.
for address and data), may be submitted for pattern generation. The PROMs must be clearly marked to indicate which
PROM corresponds to which address space (OOO-3FF HEX),
(400-7FF) or (OOO-7FFl. See Figure 24 for recommended
marking procedure.
After the PROM(s) are marked they should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.

VERIFICATION MEDIA
All original pattern media (PROMs or Floppy Disk) are filed
for contractual purposes and are not returned. A computer
listing of the ROM code will be generated and returned along
with a listing verification form. The listing should be
thoroughly checked and the verification form completed,
signed, and returned to Motorola. The signed verification
form constitutes the contractual agreement for creation of
the customer mask. If desired, Motorola will program a blank

3-492

MC6847- MC6847V

2716 EPROM Isupplled by the customer) from the data file
used to create the custom mask to aid in the verification process.
ROM VERIFICATION UNITS

Ten MC6847s containing the customer's ROM pattern will
be sent for program verification. These units will have been
made using the custom mask but are for the purpose of
ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room
temperature and 5 volts. These RVUs are included in the
mask charge and are not production parts.
FLEXIBLE DISKS

The disk media submitted must be single-sided, slngledensity, 8-lnch, MOOS compatible floppies. The customer
must write the binary file name and company name on the

disk with a felt-tip pen The floppies are not to be returned by
Motorola as they are used for archival storage. The minimum
MOOS system flies must be on the disk as well as the absolute binary object file Ifilename.LO type of file). An object
file made from a memory dump using the ROLLOUT command is also admissable. Consider submitting a source
listing as well as the following files: filename .LX IEXORciser® loadable format) and filename .SA IASCII Source
Code). These files will of course be kept confidential and are
used 1) to speed up the process in house if any problems
arise, and 2) to speed up our customer to factory interface if
a user finds any software errors and needs assistance quickly
from the factory representatives.
MOOS IS Motorola's Oisk Operating System available on
development systems such as EXORcisers, or EXORsets,
etc.

FIGURE A-2
Customer Name ________________________________________________________________________________
Address ____________________________________________________________________________
CitY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Phone (_________________ State _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.J..7ip _ _ _ _ _ _ _ _ _ _ __
Contact Ms/Mr _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Pattern Media
2708 PROM
2716 PROM
MOOS Disk
(Note 21 ____________________________________________________
Other (NOTE: Other media requires pr'lor factory approval)
Signature
Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

3-493

I

®

MOTOROLA

MC6850

ASYNCHRONOUS COMMUNICATIONS INTERFACE
ADAPTER (ACIA)

MOS
IN-CHANNEL, SILICON-GATE)

I

The MC6850 Asynchronous Communications Interface Adapter provides the data formatting and control to interface serial asynchronous
data communications information to bus organized systems such as the
MC6800 Microprocessing Unit.
The bus interface of the MC6850 includes select, enaole, read/write,
interrupt and bus interface logic to allow data transfer over an 8-bit
bidirectional data bus. The parallel data of the bus system is serially
transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of the
ACIA is programmed via the data bus during system initialization. A
programmable Control Register provides variable word lengths, clock
division ratios, transmit control, receive control, and interrupt control.
For peripheral or modem operation, three control lines are provided.
These lines allow the ACIA to interface directly with the MC6860L
0-600 bps digital modem.
• 8- and 9-Bit Transmission
• Optional Even and Odd Parity
• Parity, Overrun and Framing Error Checking
• Programmable Control Register
• Optional + 1, + 16, and + 64 Clock Modes
• Up to 1.0 Mbps Transmission
• False Start Bit Deletion
• Peripheral/Modem Control Functions
• Double Buffered
• One- or Two-Stop Bit Operation

ASYNCHRONOUS
COMMUNICATIONS INTERFACE
ADAPTER

S SUFFIX
CERDIP PACKAGE
CASE 623

P SUFFIX
PLASTIC PACKAGE
CASE 709

L SUFFIX
CERAMIC PACKAGE
CASE 716

PIN ASSIGNMENT
MC6860 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
BLOCK DIAGRAM

VSS

eTS
OCO

Rx ClK

Data.Bus

Data
Bus
Buffers

Transmit
Data

00

Tx ClK

01

RTS

02

Tx Data

03
04

Receive
Data

Address
Control
and
Interrupt

Selection
and
Control

CSO

05

CS2

06

CSl

07

RS
Peripheral/
Modem
Control

VCC

3-494

R/Vii

MC6850

MAXIMUM RATINGS
Characteristics
Supply Voltage
Input Voltage
Operating Temperature Range
MC6850, MC68A50, MC68B50
MC6850C, MC68A50C
Storage Temperature Range

Symbol
VCC
Vin

Value
-0.3 to + 7.0
-0.3 to + 7.0

Tstg

TL to TH
0 to 70
-40 to +85
-55 to + 150

Symbol

Value

(JJA

120
60
65

TA

Unit
V
V

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS
or VCC!.

°c
°c

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

Unit
°C/W

I

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °c can be obtained from:
(1)

T J = TA + (PO-IJJA)
Where:
T A - Ambient Temperature, °C
IJJA-Package Thermal Resistance, Junction-to-Ambient, °C/W

Po - PINT + PPORT
PINT-ICC x VCC, Watts - Chip Internal Power
PPORT- Port Power Oissipation, Watts - User Oetermined
For most applications PPORT2

CS1

IRQ

RESET
CTS

TxD

DCD
DSR
RxC
XTL1
XTLO

R/W

CSO
CS1

06

XTL1

05

XTLO

D4

RTS

03

CTS

02

TxO

01

OTR

DO

RxO

OSR

DTR
RTS

RS1

RxD

This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.

3-503

OCO

RSO
RS1

RSO

07

RxC

15

VCC

MC68HC51

DATA CARRIER DETECT (DCD)

FIGURE 2 - M6800 SERIES
INTERFACE REQUIREMENTS

R/W~---~R/W
<1>2 I-----~ <1>2

The DCD input pin is used to indicate to the ACIA the
status of the carrier-detect output of the modem. A low indicates that the modem carrier signal is present and a high that
it is not. Like DSR, DCD is a high-impedance input and must
be connected.

Proper connection of
CSO, CS 1, address and
data lines is assumed.

REQUEST TO SEND (RTS)

The RTS output pin is used to control the modem from the
processor. The state of the RTS pin is determined by the
contents of the command register.
R/W 1 - - - - - - - 1 R/W
DS 1-------1 <1>2

I

CLEAR TO SEND (CTS)
Same as above, except an
external latch is required when
interfacing with MC6805

The CTS input pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter is
automatically disabled if CTS is high.
DATA TERMINAL READY (DTR)

This output pin is used to indicate the status of the ACIA
to the modem. A Iowan DTR indicates the ACIA is enabled
and a high indicates it is disabled. The processor controls
this pin via bit 0 of the command register.

SIGNAL DESCRIPTIONS
The following paragraphs provide a brief description of the
input and output signals for the MC68HC51.

CHIP SELECTS (CSO, CS1)

During system initialization, a low on the RESET input
causes the internal registers to be cleared.

The two chip-select inputs are normally connected to the
processor address lines either directly or through decoders.
The ACIA is selected when CSO is high and CS1 is low.

INPUT CLOCK (2), The Receiver Data
Available status bit (RDA) indicates when data is available to
be read from the last FIFO location (#3) when in the 1-byte
transfer mode. The 2-byte transfer mode causes the RDA
status bit to indicate data is available when the last two FIFO

register locations are full. Data being available in the Receive
Data FIFO causes an interrupt request if the Receiver Interrupt Enable (RIE) bit is set. The MPU will then read the
SSDA Status Register which will indicate that data is
available for the MPU read from the Receive Data FIFO
register. The IRO and RDA status bits are reset by a read
from the FIFO. If more than one character has been received
and is resident in the Receive Data FI FO, subsequent E
clocks will cause the FIFO to update and the RDA and IRO
status bits will again be set. The read data operation for the
2-byte transfer mode requires an intervening E clock between reads to allow the FIFO data to shift. Optional parity is
automatically checked as data is received, and the parity
status condition is maintained with each character until the
data is read from the Receive Data FIFO. Parity errors will
cause an interrupt request if the Error Interrupt Enable (EIE)
has been set. The parity bit is not transferred to the data bus
but must be checked in the Status Register. NOTE: In the
2-byte transfer mode, parity should be checked prior to
reading the second byte, since a FIFO read clears the error
bit.
Other status bits which pertain to the receiver section are
Receiver Overrun and Data Carrier Detect (oCD)' The Overrun status bit is automatically set when a transfer of a
character to the Receive Data FIFO occurs and the first
register of the Receive Data FIFO is full. Overrun causes an
interrupt if Error Interrupt Enable (EIE) has been set. The
transfer of the overrunning character into the FIFO causes
the previous character in the FIFO input register location to
be lost. The Overrun status bit is cleared by reading the
Status Register (when the overrun condition is present),
followed by a Receive data FIFO Register read. Overrun cannot occur and be cleared without providing an opportunity to
detect its occurrence via the Status Register.
A positive transition on the DCD input causes an interrupt
if the EIE control bit has been set. The interrupt caused by
DCD is cleared by reading the Status Register when the
status bit is high, followed by a Receive data FIFO read. The
DCD status bit will subsequently follow the state of the DCD
input when it goes low.

om

INPUT/OUTPUT FUNCTIONS
SSDA INTERFACE SIGNALS FOR MPU
The SSDA interfaces to the MC6800 MPU with an 8-bit bidirectional data bus, a chip-select line, a register-select line,
an interrupt-request line, read/write line, an enable line, and
a reset line. These signals, in conjunction with the MC6800
VMA output, permit the MPU to have complete control over
the SSDA.
SSDA Bi-Directional Data (00-07) - The bi-directional
data lines (oO-D7) allow for data transfer between the SSDA
and the MPU. The data bus output drivers are three-state
devices that remain in the high-impedance (off) state except
when the MPU performs an SSDA read operation.
SSDA Enable (E) - The Enable signal, E, is a highimpedance TTL-compatible input that enables the bus input/output data buffers, clocks data to and from the SSDA,
and moves data through the FIFO Registers.

3·513

I

MC6852

Read/Write (R/W) - The Read/Write line is a highimpedance input that is TTL compatible and is used to control the direction of data flow through the SSDA's input/ output data bus interface. When Read/Write is high
(MPU read cycle), SSDA output drivers are turned on if the
chip is selected and a selected register is read. When it is
low, the SSDA output drivers are turned off and the MPU
writes into a selected register. The Read/Write Signal is also
used to select read-only or write-only registers within the
SSDA.

I

Chip Select (CS) - This high-impedance TTL-compatible
input line is used to address the SSDA. The SSDA is
selected when CS is low. VMA should be used in generating
the CS input to insure that false selects will not occur.
Transfers of data to and from the SSDA are then performed
under the control of the Enable signal, Read/Write, and
Register Select.
Register Select (RS) - The Register Select line is a highimpedance input that is TTL compatible. A high level is used
to select Control Registers C2 and C3, the Sync Code
Register, and the Transmit/Receive Data Registers. A low
level selects the Control 1 and Status Registers (see Table 1).
Interrupt Request (IRQ) - Interrupt Request is a TTL
compatible, open-drain (no internal pullup), active low output that is used to interrupt the MPU. The Interrupt Request
remains low until cleared by the MPU.
RESET Input - The RESET input provides a means of
resetting the SSDA from an external source. In the low
state, the RESET input causes the following:
1. Receiver Reset (Rx Rs) and Transmitter Reset (Tx Rs)
bits are set causing both the receiver and transmitter
sections to be held in a reset condition.
2. Peripheral Control bits PCl and PC2 are reset to zero,
causing the SM/DTR output to be high.
3. The Error Interrupt Enable (EIE) bit is reset.
4. An internal synchronization mode is selected.
5. The Transmitter Data Register Available (TDRA)
status bit is cleared and inhibited.
6. The Receiver Shift Register is set to l's.
When RESET returns high (the inactive state), the
transmitter and receiver sections will remain in the reset state
until the Receiver Reset and Transmitter Reset bits are
cleared via the data bus under software control. The control
Register bits affected by RESET (Rx Rs, Tx Rs, PC1, PC2,
EIE, and Ell Sync) cannot be changed when RESET is low.

SERIAL INPUT/OUTPUT LINES
Receive Data (Rx Data) - The Receive Data line is a highimpedance TTL-compatible input through which data is
received in a serial format.
Transmit Data (Tx Data) - The Transmit Data output line
transfers serial data to a modem or other peripheral.
PERIPHERAL/MODEM CONTROL
The SSDA includes several functions that permit limited
control of a peripheral or modem. The functions included are
Clear-to-Send, Sync Match/Data Terminal Ready, Data Carrier Detect, and Transmitter Underflow.
Clear-to-Send (CTS) - The CTS input provides a realtime inhibit to the transmitter section (the Tx Data FIFO is
not disturbed). A positive CTS transition resets the Tx Shift
Register and inhibits the TDRA status bit and its associated
interrupt in both the one-sync-character and two-synccharacter modes of operation. TDRA is not affected by the
CTS input in the external sync mode.
The positive transition of CTS is stored within the SSDA
to insure that its occurrence will be acknowledged by the
system. The stored CTS information and its associated IRQ
(if enabled) are cleared by writing a "1" in the Clear CTS bit
in Control Register 3 or in the Transmitter Reset bit. The CTS
status bit subsequently follows the CTS input when it goes
low.
The CTS input provides character timing for transmitter
data when in the external sync mode. Transmission is initiated on the negative transition of the first full positive clock
pulse of the transmitter clock (Tx ClK) after the release of
CTS (see Figure 6),
Data Carrier Detect (DCD) - The DCD input provides a
real-time inhbit to the receiver section (the Rx FIFO is not
disturbed). A positive DCD transition resets and inhibts the
receiver section except for the Receive FIFO and the RDRA
status bit and its associated IRO.
The positive transition of DCD is stored within the SSDA
to insure that its occurrence will be acknowledged by the
system. The stored DCD information and its associated IRO
(if enabled) are cleared by reading the Status Register and
then the Receiver FIFO, or by writing a "1" into the Receiver
Reset bit. The DCD status bit subsequently follows the DCD
input when it goes low. The DCD input provides character
synchronization timing for the receiver during the external
sync mode of operation. The receiver will be initialized and
data will be sampled on the positive transition of the first full
Receive Clock cycle after release of DCD (see Figure 7).

CLOCK INPUTS
Separate high-impedance TTL-compatible inputs are provided for clocking of transmitted and received data.

Sync Match/Data Terminal Ready (SM/DTR) - The
SM/ DTR output provides four functions (see Table 1)
depending on the state of the PCl and PC2 control bits.
When the Sync Match mode is selected (PC="l",
PC2= "0"), the output provides a one-bit-wide pulse when a
sync' code is detected. This pulse occurs for each sync code
match even if the receiver has already attained synchronization. The SM output is inhibited when PC2="1". The DTR
mode (PCl = "0") provides an output level corresponding to
the complement of PC2 IDTR="O" when PC2="1"). (See
Table 1.)

Transmit Clock (Tx CLK) - The Transmit Clock input is
used for the clocking of transmitted data. The- transmitter
shifts data on the negative transition of the clock.
Receive Clock (Rx CLK) - The Receive Clock input is used for clocking in received data. The clock and data must be
synchronized externally. The receiver samples the data on
the positive transition of the clock.

3-514

MC6852

TABLE 1 - SSDA PROGRAMMING MODEL
Control Address
In uts
Control
RS R!W AC2 ACl
1
X

Register

Register Content
Bit 7
Interrupt
Request
(lRO)

Bit 6
Receiver
Parity
Error
(PE)

Bit 5
Bit 4
Receiver Transmitter
Overrun Underflow
(TUF)
(Rx Ovrn)

Bit 3
Clear-toSend
(CTS)

Bit 2
Data Carrier
Detect
(OCD)

Receiver Transmitter
Interrupt
Interrupt
Enable
Enable
(RIE)
(TIE)

Clear
Sync

Strip Sync
Characters
(S trip Sy nc)

Bit 1
Transmitter
Data
Register
Available
(TDRA)
Transmitter
Reset
(Tx Rs)

Bit 0

a

x

Cantrall
{Cn

a a

x

X

Address
Control 2
(AC2)

Address
Cantrall
(AC1)

Receive
Data FIFO
Control 2

1

1

X

X

D7

D6

05

D4

D3

02

01

DO

1

0

a

a

Error
Interrupt
Enable
(EIE)

Transmit
Sync Code
on
Underflow
(Tx Sync)

Word
Length
Select 3
(WS3)

Word
Length
Select 2
(WS2)

Word
Length
Select 1
(WS1)

1-Byte/2-By te
Transfer
(l-By le/2- By tel

Peripheral
Control 2
(PC2)

Peripheral
Cantrall
(PC1)

1

a

a

1

Not Used

Not Used

Not Used

Not Used

Clear
Transmitter
Underflow
Status
(CTUF)

Clear CTS
Status
(Clear CTS)

One-SyncCharacterl
Two-Sync
Character
Mode Control
(1 Sync!
2 Sync)

Externall
Internal
Sync Mode
Control
(Ell Sync)

Status (S)

(C2)

Control 3
(C3)

Receiver
Data
Available
(RDA)
Receiver
Reset
(Rx Rs)

Sync Code

1

0

1

0

D7

06

05

D4

D3

D2

Dl

DO

Transmit
Data FIFO

1

a

1

1

D7

D6

D5

04

03

D2

D1

00

X

~

Don't care

STATUS REGISTER
IRO

Bit 7

The IRO flag is cleared when the source of the IRO is
cle'ned. The source is determined by the enables in the
Control Registers: TIE, RIE, EIE.

Bits 6--0
PE
Rx Ovrn
TUF
CTS
DCD
TDRA
RDA

indicate the SSDA status at a point in time, and can be

reset as follows:
Bit 6 Read Rx Data FIFO, Or a "1" into Rx Rs (Cl Bit 0).
Bit 5

Read Status and then Rx Data FIFO, or a "1" into
Rx Rs (Cl Bit 0).
A "1" into CTUF (C3 Bit 3) or into Tx Rs (Cl Bit 1).
A "1" into Clear CTS (C3 Bit 2) or a "1" into Tx Rs
(Cl Bitl)
Bit 2 Read Status and then R x Data FIFO or a "1" into
Rx Rs (Cl Bit 0)
Bit 1 Write into Tx Data FIFO.
Bit 0 Read Rx Data FIFO.
Bit 4
Bit 3

CONTROL REGISTER 1
AC2, ACl
RIE
TIE
Clear Sync
Strip Sync
Tx Rs
Rx Rs

Bits 7, 6
Bit 5
Bit4
Bit 3
Bit 2

Used to access other registers, as shown above.
When "1", enables interrupt on RDA (S Bit 0).
When"l",enablesinterruptonTDRA(SBitl).
When "1", clears receiver character synchronization.
When" 1", strips all sync codes from the received
data stream_
Bit 1 When "1", resets and inhibits the transmitter section_
Bit
When" 1", resets and inhibits the receiver section.

Ell Sync

Bit 5
WS3

Bit 4
WS2

Bit 3
WSl

a

0
0

0
1

0
0
0
1
1
1
1

1
1

0

0
0

0

1
1

0

1
1
1

1-Byte/2-Byte

Bit 2

a

CONTROL REGISTER 3
CTUF
Clear CTS
1 Sync/2 Sync

CONTROL REGISTER 2
Bit 7 When "1", enables the PE, Rx Dvm,
EIE
TUF, CTS, and DCD interrupt flags
(S Bits 6 through 2),
Tx Sync
Bit 6 When "1", allows sync code contents
to be transferred on underflow, and
enables the TUF Status bit and output. When "0", an all mark character
is transmitted on underflow.
WS3, 2,1
Bits 5-3 Word Length Select

PC2, PCl

Bit 3 When "1", clears TUF (S Bit 4)' and IRO if enabled.
Bit 2 When "1", clears CTS (S Bit 3), and IRO if enabled.
Bit 1 When "1", selects the one-sync-character mode; when
"0", selects the two-sync-character mode.
Bit
When "1", selects the external sync mode; when "0",
selects the internal sync mode.

a

Bits 1--0

Bit 1
PC2

Bit 0
PCl

0
0

0

1
1

0

1
1

Word Length
6 Bits 1 Even Parity
6 Bits + Odd Parity
7 Bits
8 Bits
7 Bits + Even Parity
7 Bits + Odd Parity
8 Bits + Even Parity
8 Bits + Odd Parity
When "1", enables the TDRA and
RDA bits to indicate when a 1-byte
transfer can occur; when "0", the
TDRA and RDA bits indicate when
a 2·byte tra nsfer can occur.
SM/DTR Output Control
SM/DTR Output at Pin 5
Pulse ..r-L.,1 1-Bit Wide on SM

0
SM Inhibited, 0

NOTE: When the SSDA is used in applications requiring the MSB of data to
be received and transmitted first, the data bus inputs to the SSDA may be
reversed (DO to D7, etc.!' Caution must be used when this is done since the
bit positions in this table will be reversed, and the parity should not be selected.

3·515

I

MC6852

Transmitter Interrupt Enable (TIE), Cl Bit 4 - TIE enables
both the Interrupt Request output (TAO) and Interrupt Request status bit to indicate a transmitter service request.
When TIE is set and the TDRA status bit is high, the IRQ output will go low (the active state) and the IRQ status bit will
go high.

Transmitter Underflow (TUF) - The Underflow output indicates the occurrence of a transfer of a "fill character" to
the Transmitter Shift Register when the last location (#3) in
the Transmit Data FIFO is emtpy. The Underflow output
pulse is approximately one Tx CLK high period wide and occurs during the last half of the last bit of the character
preceding the "Underflow" (see Figure 4). The Underflow
output pulse does not occur when the Tx Sync bit is in the
reset state.

I

Receiver Interrupt Enable (RIE), C1 Bit 5 - RIE enables
both the Interrupt Request output ('iRQ) and the Interrupt
Request status bit to indicate a receiver service request.
When RIE is set and the RDA status bit is high, the'ii1Q output will go low (the active state) and the IRQ status bit will
go high.

SSDA REGISTERS
Seven registers in the SSDA can be accessed by means of
the data bus. The registers are defined as read-only or writeonly according to the direction of information flow. The
Register Select input (R S) selects two registers in each state,
one being read-only and the other write-only. The
Read/Write input (A/W) defines which of the two selected
registers will actually be accessed. Four registers (two readonly and two write-only) can be accessed via the bus at any
particular time. These registers and the required addressing
are defined in Table 1.

Address Control 1 (AC1) and Address Control 2 (AC2), Cl
Bits 6 and 7 - AC1 and AC2 select one of the write-only
registers - Control 2, Control 3, Sync Code, or Tx Data
FIFO - as shown in Table 1, when RS="'" and
R/W="O".
CONTROL REGISTER 2 (C2)
Control Register 2 is an 8-bit write-only register which can
be programmed from the data bus when the Address Control
bits in Control Register 1 (AC1 and AC2) are reset, RS = "1"
and R/W="O".

CONTROL ~EGISTER 1 (C1)
Control Register' is an 8-bit write-only register that can be
directly addressed from the data bus. Control Register' is
accessed when RS = "0" and R/W = "0".

Peripheral Control (PC1) and Peripheral Control 2 (PC2),
C2 Bits 0 and 1 - Two control bits, PCl and PC2, determine
the operating characteristics of the Sync Match/DTR output. PC1, when high, selects the Sync Match mode. PC2
provides the inhibit/enable control for the SM/DTR output
in the Sync Match mode. A one-bit-wide pulse is generated
at the output when PC2 is "0", and a match occurs between
the contents of the Sync Code Register and the incoming
data even if sync is inhibited (Clear Sync bit= "1"). The
Sync Match pulse is referenced to the negative edge of Rx CLK pulse causing the match (see Figure 3).
The Data Terminal Ready (i5'i'R) mode is selected when
PC1 is low. When PC2= "'" the SM/DTR output= "0" and
vice versa. The operation of PC2 and PCl is summarized in
Table ,.

Receiver Reset (Rx Rs), C1 Bit 0 - The Receiver Reset
control bit provides both a reset and inhibit function to the
receiver section. When Rx Rs is set, it clears the receiver
control logic, sync logic, error logic, Rx Data FIFO Control.
Parity Error status bit, and DCD interrupt. The Receiver Shift
Register is set to ones. The Rx Rs bit must be cleared after
the occurrence of a low level on RESET in order to enable
the receiver section of the SSDA.
Transmitter Reset (Tx Rs), C1 Bit 1 - The Transmitter
Reset control bit provides both reset and inhibit to the
transmitter section. When Tx Rs is set, it clears the transmitter control section, Transmitter Shift Register, Tx Data FIFO
Control (the Tx Data FIFO can be reloaded after one E clock
pulse), the Transmitter Underflow status bit, and the CTS interrupt, and inhibits the TDRA status bit lin the one-synccharacter and two-sync-character modes). The Tx Rs bit
must be cleared after the occurrence of a low level on RESET
in order to enable the transmitter section of the SSDA. If the
Tx FIFO is not preloaded, it must be loaded immediately after
the Tx Rs release to prevent a transmitter underflow condition.

l-Byte/2-Byte Transfer (1-Byte/2-Byte), C2, Bit 2 When '-8yte/2-8yte is set, the TDRA and RDA status bits
will indicate the availabitliy of their respective data FIFO
registers for a single-byte data transfer. Alternately, if
'-Byte/2-8yte is reset, the TDRA and RDA status bits indicate when two bytes of data can be moved without a second status read. An intervening Enable pulse must occur
between data transfers.

Strip Synchronization Characters (Strip Sync), C1 Bit 2 If the Strip Sync bit is set, the SSDA will automatically strip
all received characters which match the contents of the Sync
Code Register. The characters used for synchronization (one
or two characters of sync) are always stripped from the
received data stream.

Word Length Selects (WS1, WS2, WS3), C2 Bits 3, 4, 5
- Word Length Select bits WS1, WS2, and WS3 select
word lengths of 7, 8, or 9 bits including parity as shown in
Table 1.
Transmit Sync Code on Underflow (Tx Sync), C2 Bit 6 When Tx Sync is set, the transmitter will automatically send
a sync character when data is not available for transmission.
If Tx Sync is reset, the transmitter will transmit a Mark
character lincluding the parity bit position) on underflow.
When the underflow is detected, a pulse approximately one
Tx CLK high period wide will occur on the underflow output

Clear Synchronization (Clear Sync), C1 Bit 3 - The Clear
Sync control bit provides the capability of dropping receiver
character synchronization and inhibiting resynchronization.
The Clear Sync bit is set to clear and inhibit receiver synchronization in al/ modes and is reset to zero to enable resynchronization.

3·516

MC6852

if the Tx Sync bit is set. Internal parity generation is inhibited
during underflow except for sync code fill character
transmission in 8-bit plus parity word lengths.
Error Interrupt Enable (EIE), C2 Bit 7 - When EIE is set,
the IRQ status bit will go high and the IRQ output will go low
if:
1. A receiver overrun occurs. The interrupt is cleared by
reading the Status Register and reading the Rx Data
FIFO.
2. DCD input has gone to a "1". The interrupt is cleared
by reading the Status Register and reading the Rx
Data FIFO.
3. A parity error exists for the character in the last location (#3) of the Rx Data FIFO. The interrupt is cleared
by reading the Rx Data FIFO.
4. The CTS input has gone to a "1". The interrupt is
cleared by writing a "1" in the Clear CTS bit, C3 bit 2,
or by a Tx Reset.
5. The transmitter has underflowed (in the Tx Sync on
Underflow mode). The interrupt is cleared by writing a
"1" into the Clear Underflow, C3 bit 3, or Tx Reset.
When EIE is a "0", the IRQ status bit and the IRQ output
are disabled for the above error conditions. A low level on
the RESET input resets EIE to "0".
CONTROL REGISTER 3 (C3)
Control Register 3 is a 4-bit write-only register which can
be programmed from the data bus whe RS = "1" and
R/W="O" and Address Control bit AC1="1"and
AC2="0".
External/internal Sync Mode Conrol (Ell Sync), C3, Bit 0
- When the E/I Sync Mode bit is high, the SSDA is in the
external sync mode and the receiver synchronization logic is
disabled. Synchronization can be achieved by means of the
"i'5"CD input or by starting Rx ClK at the midpoint of data bit 0
of a cahracter with DCD low. Both the transmitter and
receiver sections operate as parallel - serial converters in
the External Sync mode. The Clear Sync bit in Control
Register 1 acts as a receiver sync inhibit when high to provide a bus controllable inhibit. The Sync Code Register can
serve as a transmitter fill character register and a receiver
match register in this mode. A "low" on the RESET input
resets the Ell Sync Mode bit placing the SSDA in the internal sync mode.
One-Sync-Character ITwo-Sync-Character Mode Control
(1-Sync/2-Sync), C3 Bit 1 - When the l-Sync/2-Sync bit is
set, the SSDA will synchronize on a single match between
the received data and the contents of the Sync Code
Register. When the l-Syncl2-Sync bit is reset, two successive sync charaCters must be received prior to receiver
synhnchronization. If the second sync character is not
detected, the bit-by-bit search resumes from the first bit in
the second character. See the description of the Sync Code
Register for· more details.
Clear CTS Status (Clear CTS), C3 Bit 2 - When a "1" is
written into the Clear CTS bit, the stored status and interrupt
are cleared. Subsequently, the CTS status bit reflects the

state of the CTS input. The Clear CTS control bit does not
affect the CTS input nor its inhibit of the transmitter section.
The Clear CTS command bit is self-clearing, and writing a
"0" into this bit is a nonfunctional operation.
Clear Transmit Underflow Status (CTUF), C3 Bit 3 When a "1" is written into the CTU F status bit, the CTU F bit
and its associated interrupt are reset. The CTUF command
bit is self-clearing and writing a "0" into this bit is a nonfunctional operation.
SYNC CODE REGISTER
The Sync Code Register is an 8-bit register for storing the
programmable sync code required for received data character
synchronization in the one-sync-character and two-synccharacter modes. The Sync Code Register also provides for
stripping the sync/fill characters from the received data (a
programmable option) as well as automatic insertion of fill
characters in the transmitted data stream. The Sync Code
Register is not utilized for receiver character synchronization
in the external sync mode; however, it provides storage of
receiver match and transmit fill characters.
The Sync Code Register can be loaded when AC2 and
ACl are a "1" and "0", respectively, and R/W="O" and
RS="l".
The Sync Code Register may be changed after the detection of a match with the received data (the first sync code
having been detected) to synchronize with a double-word
sync pattern. (This sync code change must occur prior to the
completion of the second character.) The sync match (S M)
output can be used to interrupt the MPU system to indicate
that the first eight bits have matched. The service routine
would then change the sync match register to the second
half of the pattern. Alternately, the one-sync-character mode
can be used for sync codes for 16 or more bits by using software to check the second and subsequent bytes after
reading them from the FIFO.
The detection of the sync code can be programmed to appear on the Sync Match/i"Jrn output by writing a "1" in PCl
(C2 bit 0) and a "0" in PC2 (C2 bit 11. The Sync Match output will go high for one bit time beginning at the character interface between the sync code and the next character (see
Figure 3).

PARITY FOR SYNC CHARACTER
Transmitter
Transmitter does not generate parity for the sync
character except 9-bit mode.
9-bit (8-bit + parity) ... 8-bit sync character + parity
8-bit (7-bit + parity) ... 8-bit sync character (no parity)
7-bit (6-bit+ parity) ... 7-bit sync character (no parity)
Receiver

At Synchronization
Receiver automatically strips the sync character(s) (two
sync characters if '2 sync' mode is selected) which is used to
establish synchronization. Parity is not checked for these
sync characters.

3-517

I

MC6852

After Synchronization Is Established
When 'strip sync' bit is selected, the sync characters (fill
characters) are stripped and parity is not checked for the
stripped sync (fill) characters. When "strip sync" bit is not
selected (low), the sync character is assumed to be normal
data and it is transferred into FIFO after parity checking.
(When non-parity format is selected parity is not checked)

I

Strip Sync
(C1, Bit 2)

WSO-WS2
(Data Format)
(C2, Bits 3-5)

1

X

0

With Parity

0

Without Parity

No transfer of sync code
No parity Check of sync code
"Transfer data and sync codes
Parity check
"Transfer data and sync codes
No paritv check

"Subsequent to synchronization.
It is necessary to consider parity in the selected sync
character in the following cases. Data Format is (6+ parity),
(7 + parity), strip sync is not selected (low), and when sync
code is used as a fill character after synchronization.
The transmitter sends a sync character without parity, but
the receiver checks the parity as if it is normal data.
Therefore, the sync character should be chosen to match the
parity check selected for the receiver in this special case. See
the following section for unused bit assignment in shortword length.
RECEIVE DATA FIRST-IN FIRST-OUT REGISTER (Rx Data
FIFO)
The Receive Data FIFO Register consists of three 8-bit
registers which are used for buffer storage of received data.
Each 8-bit register has an internal status bit which monitors
its full or empty condition. Data is always transferred from a
full register to an adjacent empty register. The transfer from
register to register occurs on E pulses. The RDA status bit
will be high when data is available in the last location of the
Rx Data FIFO.
In an Overrun condition, the overrunning character will be
transferred into the full first stage of the FIFO register and
will cause the loss of that data character. Successive overruns continue to overwrite the first register of the FIFO. This
destruction of data is indicated by means of the Overrun
status bit. The Overrun bit will be set when the overrun occurs and remains set until the Status Register is read, followed by a read of the Rx Data FIFO.
Unused data bits for short word lengths (including the
parity bit) will appear as "a's" on the data bus when the Rx
Data FI FO is read.
TRANSMIT DATA FIRST-IN FIRST-OUT REGISTER (Tx
Data FIFO)
The Transmit Data FIFO Register consists of thee 8-bit
registers which are used for buffer storage of data to be
transmitted. Each 8-bit register has an internal status bit
which monitors its full or empty condition. Data is always
transferred from a full register to an adjacent empty register.
The transfer is clocked by E pulses.
The TDRA status bit will be high if the Tx Data FIFO is
available for data.

Unused data bits for short word lengths will be handled as
"don't cares." The parity bit is not transferred over the data
bus since the SSDA generates parity at transmission.
When an Underflow occurs, the Underflow character will
be either the contents of the Sync Code Register or an all
"1's" character. The underflow will be stored in the Status
Register until cleared and will appear on the Underflow output as a pulse approximatley one Tx ClK high period wide.
STATUS REGISTER (S)
The Status Register is an 8-bit read-only register which
provides the real-time status of the SSDA and the associated
serial data channel. Reading the Status Register is a nondestructive process. The method of clearing status bits
depends upon the function each bit represents and is
discussed for each bit in the register.
Receiver Data Available (RDA), S Bit 0 - The Receiver
Data Available status bit indicates when receiver data can be
read from the Rx Data FIFO. The receiver data being present
in the last register (#3) of the FIFO causes RDA to be high for
the 1-byte transfer mode. The RDA bit being high indicates
that the last two registers (#2 and #3) are full when in the
2-byte transfer mode. The second character can be read
without a second status read (to determine that the
character is availablel. An E pulse must occur between reads
of the Rx Data FIFO to allow the FIFO to shift. Status must
be read on a word-by-word basis if receiver data error checking is important. The RDA status bit is reset automatically
when data is not available.
Transmitter Data Register Available (TDRA), S Bit 1
The TDRA status bit indicates that data can be loaded into
the Tx Data FIFO Register. The first register (#1) of the Tx
Data IFFO being empty will be indicated by a high level in the
TDRA status bit in the 1-byte transfer mode. The first two
registers (#1 and #2) must be empty for TDRA to be high
when in the 2-byte transfer mode. The Tx Data FIFO can be
loaded with two bytes without an intervening status read;
however, one E pulse must occur between loads. TDRA is
inhibited by the Tx Reset or RESET. When Tx Reset is set,
the Tx Data FIFO is cleared and then released on the next E
clock pulse. The Tx Data FIFO can then be loaded with up to
three characters of data, even though TDRA is inhibited.
This feature allows preloading data prior to the release of Tx
Reset. A high level on the CTS input inhibits the TDRA
status bit in either sync mode of operation (one-synccharacter or two-sync-character). CTS does not affect
TDRA in the external sync mode. This enables the SSDA to
operate under the control of the CTS input with TDRA indicating the status of the Tx Data FIFO. The CTS input does
not clear the Tx Data FIFO in any operating mode.
Data Carrier Detect (DCD), S Bit 2 - A positive transition
on the DCD input is stored in the SSDA until cleared by
reading both Status and Rx Data FIFO. A "1" written into Rx
Rs also clears the stored DCD status. The DCD status bit,
when set, indicates that the DCD input has gone high. The
reading of Status followed by reading of the Receive Data
FIFO allows Bit 2 of subsequent Status reads to indicate the
state of the DCD input until the next positive transition.

3-518

MC6852

Clear-to-Send (CTS), S Bit 3 - A positive transition on
the CTS input is stored in the SSDA until cleared by writing
a "1" into the Clear CTS control bit or the Tx Rs bit. The
CTS status bit, when set, indicates that the CTS input has
gone high. The Clear CTS command (a "i" into C3 Bit 2)
allows Bit 3 of subsequent Status reads to indicate the state
of the CTS input until the next positive transition.
Transmitter Underflow (TUF), S Bit 4 - When data is not
available for the transmitter, an underflow occurs and is so
indicated in the Status Register lin the Tx Sync on underflow
mode}. The underflow status bit is cleared by writing a "1"
into the Clear Underflow (CTUF) control bit or the Tx Rs bit.
TUF indicates that a sync character will be transmitted as the
next character. A TUF is indicated on the output only when
the contents of the Sync Code Register is to be transferred
(transmit sync code on underflow="1").
Receiver Overrun (Rx Dvm), S Bit 5 - Overrun indicates
data has been received when the Rx Data FIFO is full,

resulting in data loss. The Rx Ovrn status bit is set when
overrun occurs. The Rx Ovrn status bit is cleared by reading
Status followed by reading the Rx Data FIFO or by setting
the Rx Rs control bit.
Receiver Parity Error (PE), S Bit 6 - The parity error
status bit indicates that parity for the character in the last
register of the Rx Data FIFO did not agree with selected parity. The parity error is cleared when the character to which it
pertains is read from the Rx Data FIFO or when Rx Rs occurs. The DCD input does not clear the Parity Error or Rx
Data FIFO status bits.
Interrupt Request IIRQ), S Bit 7 - The Interrupt Request
status bit indicates when the IRO output is in the active state
(IRO output= "a"). The IRO status bit is subject to the same
interrupt enables (RIE, TIE, and EIE) as the TAO output. The
1RO status bit simplifies status inquiries for polling systems
by providing single bit indication of service requests.

3-519

I

®

MOTOROLA

MC68HC53

Product Preview

HCMOS
(HIGH DENSITY CMOS SILICON-GATE)

ASYNCHRONOUS COMMUNICATIONS INTERFACE
ADAPTER (ACIA)
The MC68HC53 ACIA provides a program-controlled interface
between 8-bit, microprocessor-based systems, serial communication
data sets, and modems. An on-chip crystal oscillator and a baud-rate
generator allow the ACIA to transmit at 15 different program-selected
rates, ranging from 50 to 19,200 baud. The MC68HC53 can receive at
either the transmit rate or at 16 times an external clock rate. A MOTEL
(MOTorola - IntEL) bus compatible circuit, is incorporated in the
MC68HC53. This circuit allows the device to directly interface with
many types of microprocessors.

I

• Compatible With 8-Bit Microprocessors
• Full-Duplex or Half-Duplex Operation With Buffered Receiver and
Transmitter

ASYNCHRONOUS
COMMUNICATIONS
INTERFACE ADAPTER
(ACIA)

.,.

• Fifteen Progiammable Baud Rates 150 to 19,200)
• Receiver Data Rate May Be Identical to Baud Rate or May Be 16
Times the External Clock Input

P SUFFIX
PLASTIC PACKAGE
CASE 710

• Data Set/Modem Control Functions
• Programmable Word Lengths, Number of Stop Bits, and Parity Bit
Generation and Detection
• Programmable Interrupt Control
• Software Reset
• Program-Selectable Serial Echo Mode
•
•
•
•
•

PIN ASSIGNMENT

Two Chip Selects
2 MHz or 1 MHz Clock Rate
Single + 5 Volt ± 5% Power Supply
Full TTL Compatibility
MOTEL Read/Write Control Circuit

FIGURE 1 -

VSS

BLOCK DIAGRAM

CTS

DO-D7

TxD

R/W

CSO
CSl
CS2
RSO

DS
RESET
AS

3·520

IRQ

RESET

A/D7

RxC

A/D6

XTL1

A/D5

XTLO

A/D4

RTS

A/D3
A/D2

TxD

A/D1/RS1

DCD
DSR

DTR

A/DO/RSO

RxD

DSR

RxC
XTLl
XTLO

CS2

DCD

AS

VCC

RxD

This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice

DS

CS1

CTS

DTR
RTS

RSl

R/W

CSO

MC68HC53

FIGURE 2 -

R/W

01/RSl OO/RSO

R/W

E (OS)

OS

AS

AS

MC6801
or
M146805

Proper connection of CSO,
CS 1, address and data bus
lines is assumed

Write

Read

0

0

Transmit Data Register Received Data Register

0

0

Programmed Reset
(Data is "Don't Care")

1

0

Command Register

1

1

Control Register

Status Register

MC68HC53

ALE

AS

RD

OS

WR

RD/WR

8085
or
NSC800

cycles when the ACIA is selected. DO and 01 are dualpurpose register selects and data lines. They are demultiplexed by AS as follows:

INTERFACE REQUIREMENTS OIAGRAM

DATA SET READY ([)Sti)
The DSR input pin is used to indicate to the ACIA the
status of the modem. A low indicates the "ready" state and
a high "not-ready". DSR is a high-impedance input, and
must be connected. If unused, it should be driven high or
low but not switched.

(Same as above)

DATA CARRIER DETECT (DCD)
The DCD input pin is used to indicate to the ACIA the
status of the carrier-detect output of the modem. A low indicates that the modem carrier Signal is present and a high that
it is not. Like DSR, DCD is a high-impedance input and must
be connected.

MC68HC53

SIGNAL DESCRIPTIONS
The following paragraphs provide a brief description of the
input and output signals for the MC68HC53.

REQUEST TO SEND (RTS)
The RTS output pin is used to control the modem from the
processor. The state of the RTS pin is determined by the
contents of the command register.

RESET (RESET)
During system initialization, a low on the RESET input
clears the internal registers.

CLEAR TO SEND (CTS)
The EfS input pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter is
automatically disabled if CTS is high.

ADDRESS STROBE (AS)
Address strobe indicates the presence of an address on
the multiplexed bus. The negative edge latches address/ data
lines 0-1 and chip select 2.

DATA TERMINAL READY (DTR)
This output pin is used to indicate the status of the ACIA
to the modem. A low on DTR indicates the ACIA is enabled
and a high indicates it is disabled. The processor controls
this pin via bit 0 of the command register.

DATA STROBE (DS)
This input is used to transfer data to or from the microprocessor.
READ/WRITE (R/W)
The R/W is generated by the microprocessor and is used
to control the direction of data transfers. A high on the R/W
pin allows the processor to read the data supplied by the
ACIA. A low on the R/W pin allows a write to the ACIA.

CHIP SELECTS 0,1, AND 2 (CSO, CS1, AND CS2)
These three chip-select inputs are normally connected to
the processor address lines either directly or through
decoders. The ACIA is selected when CSO is high, CS1 is
low, and CS2 is high. CS2 is latched by AS.

INTERRUPT REQUEST (IRQ)
The IRQ pin is an interrupt output from the interrupt control logic. It permits several devices to be connected to the
common IRQ microprocessor input. Normally a high level,
IRQ goes low when an interrupt occurs.

CRYSTAL PINS (XTL1, XTLO)
These pins are normally directly connnected to the external crystal (1.8432 megahertz) used to derive the various
baud rates. Alternatively, an externally generated clock may
be used to drive the XTL 1 pin in which case the XTLO pin
must float. XTL 1 is the input pin for the transmit clock.

ADDRESS/DATA BUS (A/DO-A/D7)
The AIDO-A/D7 pins are the eight data lines used to
transfer data and addresses. These lines are bidirectional and
are normally in the high-impedance state, except during read

TRANSMIT DATA (TxD)
The TxD output line is used to transfer serial non-returnto-zero (NRZ) data to the modem. The least significant bit

3·521

I

MC68HC53

microprocessors. No external logic is needed to adapt to the
differences in bus control signals from common multiplexed
bus microprocessors.
Practically all microprocessors interface with one of two
synchronous bus structures. One bus was originated for the
Motorola MC6800 and the other for the Intel 8080 and its
companion part, the 8228.
The MOTEL circuit (for MOTorola and intEL bus compatibility) is built into a peripheral or memory IC to permit
direct connection to either type of bus. An industry standard
bus structure is now available. The MOTEL concept is
shown logicaliy in Figure 3.
MOTEL selects one of the two interpretations of two pins.
In the Motorola case, DS and R/W are gated together to
produce the internal read enable. The internal write enable is
a similar gating of the inverse of R/W. With competitor
buses, the inversion of R1S and WR create functionally identical internal read and write enable signals.
The MC68HC53 automatically selects the processor type
by using ASI ALE to latch the state of the DSI RD pin. Since
DS is always low and RD is always high during AS and ALE,
the latch automatically indicates which processor type is
connected.

(LSB) of the transmit data register is the first data bit
transmitted and the rate of data transmission is determined
by the baud rate selected, or under control of an external
clock (as selected by the control register).
RECEIVE DATA (RxD)

The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, LSB first. The receiver data rate
is either the programmed baud rate or the rate of an externally generated receiver clock (as selected by the control
register).
RECEIVE CLOCK (RxC)

The RxC is a bidirectional pin which serves as either the
receiver 16x clock input or the receiver 16x clock output. The
latter mode results if the internal baud-rate generator is
selected for receiver data clocking.

I

MOTEL CIRCUIT
The MOTEL circuit is a new concept that permits the
MC68HC53 to be directly interfaced with many types of

FIGURE 3 -

Motorola Type
Intel Type
MPU Signals MPU Signals

MOTEL CIRCUIT-LOGIC DIAGRAM

MC68HC53
Pin Signals

Intel Bus

0
AS

ALE

AS

Q

C

Internal
Signals

Motorola
Bus

Q

OS, E, or tj>2

OS

R/W

R/W

Read Enable

Write Enable

3-522

MC68HC53

MAIN DATA/CONTROL REGISTERS

A brief description of the main MC68HC53 data and control registers follows.

specifies the specific modes and functions the MC68HC53 is
to assume. Included are data terminal ready, transmitter interrupt disabled, receiver echo mode, and parity disabled.

TRANSMIT DATA REGISTER

This 8-bit register provides temporary storage for the data
to be transmitted. Bit 0 is the leading bit to be transmitted.
Unused bits are the high-order bits and are "don't care" for
transmission.
RECEIVE DATA REGISTER

This 8-bit register provides temporary storage for the data
being received. Bit 0 is the leading bit received. Unused bits
are the high-order bits and are "zeros" for the receiver.
Parity bits are not contained in the receive data register but
are stripped off after being used for parity checking. Thus,
former parity bits become unused "zero" bits in the receive
data register.

CONTROL REGISTER
This 8-bit register contains, message format information
received from the microprocessor, and includes: baud rate,
clock source, word length, and number of stop bits. This information is used by the MC68HC53 for synchronization and
proper processing of message data.

STATUS REGISTER
This 8-bit register contains the current status of the
MC68HC53 and the related modem. This register is continuously accessed by the controlling microprocessor during
operation to determine if data processing is being performed
properly or if errors have occurred. Status indications include: parity error, framing error, overrun, clear to send,
transmit register empty, receive register full, data carrier
detect, and interrupt request.

COMMAND REGISTER

This 8-bit register contains the command word received
from the controlling microprocessor. The command word

3-523

I

®

MOTOROLA

MC6854

ADVANCED DATA-LINK CONTROLLER (ADLC)

MOS

The MC6854 /([)LC performs the complex MPU/data communication
link function for the "Advanced Data Communication Control Procedure" (ADCCP), High-Level Data-Link Control (HDLC) and Synchronous Data-Link Control (SDLC) standards. The ADLC provides key
interface requirements with improved software efficiency. The ADLC is
designed to provide the data communications interface for both primary
and secondary stations in stand-alone, polling, and loop configurations.

I

• M6800 Compatible
• Protocol Features
• Automatic Flag Detection and Synchronization
• Zero Insertion and Deletion
• Extendable Address, Control and Logical Control Fields (Optional)
• Variable Word Length Information Field - 5-, 6-, 7-, or 8-Bits
• Automatic Frame Check Sequence Generation and Check
• Abort Detection and Transmision
• Idle Detection and Transmission
• Loop Mode Operation
• Loop Back Self-Test Mode
•
•
•
•

NRZ/NRZI Modes
Quad Data Buffers for Each Rx and Tx
Prioritized Status Register (Optional)
MODEM/DMA/Loop Interface

(N-CHANNEL, SILICON GATE)

ADVANCED DATA-LINK
CONTROLLER

~

LSUFFIX
CERAMIC PACKAGE
CASE 719

PSUFFIX
.

PLASTIC PACKAGE
CASE 710
.

.

.

~
iii\!

SSUFFIX

CERDIP PACKAGE
CASE 733

PIN ASSIGNMENT
ORDERING INFORMATION
Package Type

Frequency (MHz)

Temperature

Order Number

Ceramic
L Suffix

1.0
1.0
1.5
1.5
2.0

ooC to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
ooc to 70°C

MC6854L
MC6854CL
MC68A54L
MC68A54CL
MC68B54L

1.0
1.0
1.5
1.5
2.0

ooC to 70°C
- 40°C to 85°C
ooC to 70°C
-40°C to 85°C
ooC to 70°C

MC6854S
MC6854CS
MC68A54S
MC68A54CS
MC68B54S

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
-40°C to 85°C
O°C to 70°C
-40°C to 85°C
ooC to 70°C

MC6854P
MC6854CP
MC68A54P
MC68A54CP
MC68B54P

Cerdip
S Suffix

Plastic
P Suffix

CTS
OCO
26

LOC/Oi'R

25

FLAG5E'f

TxC

24

TDSR

TxO

23

ROSR

22
RESET

8

00
01

CS

02

RSO

03

RSl

04
05
06

VCC

3-524

07

MC6854

MAXIMUM RATINGS
Symbol

Rating
Supply Voltage

VCC

Input Voltage

Vin

Operating Temperature Range
MC~.MC~A~.MC~B~

Unit
V
V

TA

(TL to TH)
o to 70
-40 to 85

°c

Tstg

-55 to + 150

°c

Symbol

Value

Unit

MC~C. MC~A54C

Storage Temperature Range

Value
-0.3 to + 7.0
-0.3 to + 7.0

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however. it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g .• either VSS
or Vee).

THERMAL CHRACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic
Cerdip

8JA

115
60
65

°C/W

I
FIGURE 1 -

Control

ADLC GENERAL BLOCK DIAGRAM

Control

oco
RxC

Data
Bus
00-07

RESET
Vss PI" 1
Vee Pin 14

3-525

MC6854

POWER CONSIDERATIONS
The average chip-junction temperature, T J, in °c can be obtained from:
T J = TA + (PD e8JA)
Where:
T A - Ambient Temperature, °c
8JA - Package Thermal Resistance, Junction-to-Ambient, °C/W
PD- PINT+ PPORT
PINT-ICC x VCC, Watts -

Chip Internal Power

PPORT - Port Power Dissipation, Watts -

User Determined

For most applications PPORT

Status Register #1

RS1 RSO = 01

RS1 RSO = 10

Status Register #2

Receiver Data
Register

0

RDA

Address Present

Bit 0

1

Status #2
Read Request

Frame Valid

Bit 1

2

Loop

Inactive Idle Received

Bit 2

3

Flag Detected
(When Enabled)

Abort Received

Bit 3

4

CTS

FCS Error

Bit 4

5

Tx Underrun

DCD

Bit 5

6

TDRA/Frame
Complete

Rx Overrun

Bit 6

7

IRQ Present

RDA (Receiver Data Available)

Bit 7

Control Register #1

Control Register #2
(C1bO = 0)

0

Address Control (AC)

Prioritized Status
Enable

1

Receiver Interrupt
Enable (RIE)

>
C

2

.~

:

a:

II

RS1 RSO = 11

Same as RS1, RSO

--

Transmitter ~
Data
I
(Last Data)
(C1bO = 0)

Logical Control
Field Select

Bit 0

Bit 0

Double Flag/Single
Flag Interframe
Control

2 Byte/1 Byte
Transfer

Extended Control
Field Select

Bit 1

Bit 1

Word Length Select
Transmit #1

Transmitter Interrupt
Enable (TI E)

Flag/Mark Idle

Auto, Address
Extension Mode

Bit 2

Bit 2

Word Length Select
Transmit #2

3

RDSR Mode (DMA)

Frame Complete/
TDRA Select

01/11 Idle

Bit 3

Bit 3

Word Length Select
Receive #1

4

TDSR Mode (DMA)

Transmit Last Data

Flag Detected
Status Enable

Bit 4

Bit 4

Word Length Select
Receive #2

5

Rx Frame
Discontinue

CLR Rx Status

Loop/Non-Loop Mode

Bit 5

Bit 5

Transmit Abort

6

Rx RESET

CLR Tx Status

Go Active on Poll/Test

Bit 6

Bit 6

Abort Extend

7

Tx RESET

RTS Control

Loop On-Line
Control DTR

Bit 7

Bit 7

NRZI/NRZ

Control Register #3
(C1 bO=1)

~

~

IX

0

~

10

Transmitter
Data
(Continue Data)

Bit #

'i»

~

3-538

Control Register #4
(C1bO = 1)

MC6854

CONTROL REGISTERS

CONTROL REGISTER 1 (CR1)

RS1

RSO

o

0

R/W AC

0

7

6

5

4

3

2

1

0

TxRS

RxRS

Discontinue

TDSR

RDSR

TIE

RIE

AC

Mode

Mode

X

bO - Address Control (AC) - AC provides another RS
(Register Select) signal internally. The AC bit is used in conjunction with RSO, RS1, and R/W inputs to select particular
registers, as shown in Table 2.
b1 Receiver Interrupt Enable (RIE) RIE
enables/disables the interrupt request caused by the receiver
section. 1... enable, 0 ... disable.
b2 Transmitter Interrupt Eanble (TIE)
TIE
enables/ disables the interrupt request caused by the
transmitter. 1... enable, 0 ... disable.
b3 - Receiver Data Service Request Mode (RDSR
MODE) - The RDSR MODE bit provides the capability of
operation with a bus system in the DMA mode when used in
conjunction with the prioritized status mode. When RDSR
MODE is set, an interrupt request caused by RDA status is
inhibited, and the ADLC does not request data transfer via
the IRQ output.
b4 - Transmitter Data Service Request Mode (TDSR
MODE) - The TDSR MODE bit provides the capability of
operation with a bus system in the DMA mode when used in
conjunction with the prioritized status mode. When TDSR
MODE is set, an interrupt request caused by TDRA status is
inhibited, and the ADLC does not request a data transfer via
the iRQ output.

b5 - Rx Frame Discontinue (DISCONTINUE) - When
the DISCONTINUE bit is set, the currently received frame is
ignored and the ADLC discards the data of the current
frame. The DISCONTINUE bit only discontinues the currently received frame and has no affect on subsequent frames,
even if a following frame has entered the receiver section.
The DISCONTINUE bit is automatically reset when the last
byte of the frame is discarded. When the ignored frame is
aborted by receiving an Abort or DCD failure, the DISCONTINUE bit is also reset.
b6 - Receiver Reset (Rx RS) - When the Rx RS bit is
"1", the receiver section stays in the reset condition. All
reciever sections, including the Rx FIFO register and the
receiver status bits in both status registers, are reset. (During
reset, the stored DCD status is reset but the DCD status bit
follows the DCD input.) Rx RS is set by forcing a low level on
the RESET input or by writing a "1" into the bit from the
data bus. Rx RS must be reset by writing a "0" from the data
bus after I1ES'ET has gone high.
b7 - Transmitter Reset (Tx RS) - When the Tx RS bit is
"1", the transmitter section stays in the reset condition and
transmits marks ("1's"l. All transmitter sections, including
the Tx FIFO and the transmitter status bits, are reset (FIFO
cannot be loaded!. During reset, the stored CTS status is
reset but the CTS status bit follows the CTS input. Tx RS is
set by forcing a low level on the R'ESETinput or by writing a
"1" from the data bus. It must be reset by writing a "0" after
RESET has gone high.

3-539

I

MC6854

CONTROL REGISTER 2 (CR2)

RS1

a

I

RSO

R/W

AC

a

a

7

6

5

4

3

2

1

6

RTS

CLR

CLR

Tx

FC/TORA

F/M

2/1

PSE

TxST

RxST

Last

Select

Idle

Byte

bO - Prioritized Status Enable (PSE) - When the PSE bit
is SET, the status bits in both status registers are prioritized
as defined in the Status Register section. When PSE is low,
the status bits indicate current status without bit suppression
by other status bits. The exception to this rule is the CTS
status bit which always supresses the TORA status.

after loading the last data byte and before the Tx FIFO empties. When the Tx Last bit is set, the AOLC assumes the byte
is the last byte and terminates the frame by appending CRCC
and a clOSing Flag. This control bit is useful for OMA operation. Tx Last bit automatically returns to the "0" state.

b1 - 2-Byte/1-Byte Transfer (2/1 Byte) - When the 2/1
Byte bit is RESET the TORA and ROA status bits then will indicate the availability of their respective data FIFO registers
for a single-byte data transfer. Similarly, if 2/1 Byte is set,
the TORA and ROA status bit indicate when two bytes of
data can be moved without a second status read.

b5 - Clear Receiver Status (ClR Rx ST) - When a "1" is
written into the CLR Rx ST bit, a reset signal is generated for
the receiver status bits in status registers 11 and 12 (except
AP and ROA bits). The reset Signal is enabled only for the
bits which have been present during the last "read status"
operation. The CLR Rx ST bit automatically returns to the
"0" state.

b2 - Flag/Mark Idle Select (F/M Idle) - The F/M Idle bit
selects Flag characters or bit-by-bit Mark Idle for the time fill
or the idle state of the transmitter. When Mark Idle is
selected, Go-Ahead code can be generated for loop operation in conjunction with the 01/11 Idle control bit (C3b3).
1...Flag time fill, Ooo.Mark Idle.

b6 - Clear Transmitter Status (ClR Tx ST) - When a
"1" is written into CLR Tx ST bit, a reset signal is generated
for the transmitter status bits in status register 11 (except
TORA). The reset signal is enabled for the bits which have
been present during the last "read status" operation. The
CLR Tx ST bit automatically returns to the "0" state.

b3 Frame Complete/TORA Select (FC/TORA
Select) - The FC/TORA Select bit selects TORA status or
FC status for the TORA/FC status bit indication. 1...FC
status, 0 ... TORA status.

b7 - Request-to-Send Control (RTS) - The RTS bit,
when high, causes the RTS output to be low (the active
state). When the RTS bit returns low and data is being
transmitted, the RTS output remains low until the last
character of the frame (the closing Flag or Abort) has been
completed and the Tx FIFO is empty. If the transmitter is idling when. the RTS bit returns low, the RTS output will go
high (the inactive state) within two bit times.
.

b4 - Transmit Last Data (Tx Last) - Tx Last bit provides
another method to terminate a frame. This bit should be set

3·540

MC6854

CONTROL REGISTER 3 (CR3)

RS1

o

RSO

R/W

o

AC

7

6

5

4

3

2

1

0

LOC/

GAP/

Loop

FDSE

01/11

AEX

CEX

LCF

DTR

TST

Idle

detection will cause the Flag Detect output to go low for 1 bit
time regardless of the state of FDSE.

bO - Logical Control Reid Select (LCF) - The LCF select
bit causes the first byte(s) of data belonging to the information field to remain 8-bit characters until the logical control
field is complete. The logical control field (when selected) is
an automatically extendable field which is extended when bit
7 of a logical control character is a "1." When the LCF Select
bit is reset the ADLC assumes no logical control field is present for either the transmit or received data channels. When
the logical control field is terminated, the word length of the
information data is then defined by WLS1 and WLS2.

b5 - LOOP/NON-LOOP Mode (LOOP) - When the
LOOP bit is set, loop mode operation is selected and the
GAP/TST control bit, LOC/DTR control bit and ·LOC/DTR
output are selected to perform the loop control functions.
When LOOP is reset, the ADLC operates in the point-topoint data communications mode.
b6 - Go Active On Poll/Test (GAP/TST) - In the Loop
Mode - The GAP/TST bit is used to respond to the poll sequence and to begin transmission. When GAPITST is set,
the receiver searches for the "Go Ahead" (or End of Poll,
EOP). The receiver "Go ahead" is converted to an opening
Flag and the ADLC starts its own transmission. When
GAP/TST is reset during the transmission, the end of the
frame (the completion of Flag or Abort) causes the termination of the "go-active-on-poll" operation and the Rx Data to
Tx Data link is re-established. The ADLC then returns to the
"Ioop-on-line" state.
In the Non-Loop Mode - The GAPITST bit is used for
self-test purposes. If GAP/TST bit is set, the TxD output is
connected to the RxD input internally, and provides a "Ioopback" feature. For normal operation, the GAP/TST bit
should be reset.

b1 - Extended Control Field Select (Cex) - When the
CEX bit is a "1", the control field is extended and asusmed to
be 16 bits. When CEX is "0", the control field is assumed to
be 8 bits.
b2 - Auto/ Address Extend Mode (Aex) - The AEX bit
when "low" allows full 8 bits of the address octet to be utilized for addressing because address extension is inhibited.
When the AEX bit is "high," bit a of address octet equal to
"0" causes the Address field to be extended by one octet.
The exception to this automatic address field extension is
when the first address octet is all "a's" (the Null Address!.
b3 - 01/11 Idle (01/11 Idle) - The 01/11 Idle Control bit
determines whether the inactive (Mark) idle condition begins
with a "0" or not. If the 01/11 Idle Control is SET, the closing
flag (or Abort) will be followed by a 011111 ... pattern. This is
required of the controller for the "Go Ahead" character in
the Loop Mode. When 01/11 is RESET, the idling condition
will be all "l's".

b7 - Loop On-Line Control/OTR Control (LOC/OTR) In the Loop Mode - The LOC/ DTR bit is used to go on-line
or to go off-line. When LOC/DTR is set, the ADLC goes to
the on-line state after 7 consecutive "1's" occur at the RxD
input. When LOC/DTR is reset, the ADLC goes to the "offline" state after eight consecutive "l's" occur at the RxD input.
In the Non-Loop Mode - The LOC/DTR bit directly controls the Loop On-Line/ DTR output state. 1... DTR output
goes to low level, O...DTR output goes to high level.

b4 - Rag Oetect Status Enable (FOSE) - The FDSE bit
enables the FD status bit in Status Register #1 to indicate the
occurrence of a received Flag character. The status indication will be accompanied by an interrupt if RIE is SET. Flag

3-541

I

MC6854

CONTROL REGISTER 4 (CR4)

RS1

RSO

R/W AC

7

6

5

NRZI/NRZ

ABTEX

ABT

3

2

Rx

o

I

I

4

WLS2

WLS1

I

1

0
"FF"/F

Tx
WL S2

WLS1

bO Double Flag/Single Flag Interframe Control
("FF" /"F") - The "FF" /"F" Control bit determines
whether the transmitter will transmit separate closing and
opening Flags when frames are transmitted successively.
When the "FF" I"F" control bit is low, the closing flag of the
first frame will serve as the opening flag of the second frame.
When the bit is high, independent opening and closing flags
will be transmitted.

1-bit delay is added to the transmitted data (TxDl to allow for
NRZI encoding. 1.. .NRZI, 0 ... NRZ.

b1, b2 - Transmitter Word Length Select (Tx WLS1 and
WLS2) - Tx WLS1 and WlS2 are used to select the word
length of the transmitter information field. The encoding format is shown in Table 3.

STATUS REGISTER
The Status Register #1 is the main status register. The IRO
bit indicates whether the ADLC requests service or not. The
S2RO bit indicates whether any bits in status register #2 request any service. TDRA and RDA, because they are most
often used, are located in bit pOSitions that are more convenient to test. RDA reflects the state of the RDA bit in status
register #2.
The Status Register #2 provides the detailed status information contained in the S2RO bit and these bits reflect
receiver status. The FD bit is the only receiver status which is
not indicated in status register #2.
The prioritized status mode provides maximum efficiency
in searching the status bits and indicates only the most important action required to service the ADLC. The priority
trees of both status registers are provided in Figure 10.
Reading the status register is a non-destructive process.
The method of clearing status depends upon the bit's function and is discussed for each bit in the register.

b3, b4 - Receiver Word Length Select (Rx WLS1 and
WLS2) - Rx WLS 1 and WLS2 are used to select the word
length of the receiver information field. The encoding format
is shown in Table 3.

TABLE 3 - I-FIELD CHARACTER LENGTH SELECT
WLS,
0
1

0
1

WLS2
0
0
1
1

I·Field Character Length
5 bits
6 bits
7 bits
8 bits

NOTE
NRZI coding - The serial data remains in the same
state to send a binary "1" and switches to the opposite state to send a binary "0".

b6 - Transmit Abort (ABT) - The ABT bit causes an
Abort (at least 8 bits of "1" in succession) to be transmitted.
The Abort is initiated and the Tx FIFO is cleared when the
control bit goes high. Once Abort begins, the Tx Abort control bit assumes the low state.

FIGURE 10 - STATUS REGISTER PRIORITY TREE IPSE= 11
SA #1
Decreasing
Priority

b6 - Abort Extend (ABTex) - If ABTEX is set. the abort
code initiated by ABT is extended up to at least 16 bits of
consecutive "1's", the mark Idle State.

1

b7 NRZI (Zero Complement)/NRZ Select
(NRZI/NRZ) - NRZI/NRZ bit selects the transmit/receive
data format to be NRZI or NRZ in both Loop Mode or NonLoop mode operation. When the NRZI Mode is selected, a

(Tx)
,,,- CIS
"'\

TXU
.j.

'l.I TDAA/FC

(Ax)

SA#2 (Ax)

FD
.j.
S2AQ
.j.
ADA

EAA, FV, DCD,
OVAN'.j.AX ABT

'Prioritlzed evan when PSE = 0
NOTE: Status bit above will inhibit one below it.

3..542

Ax Idle
.j.
AP
.j.
ADA

MC6854

STATUS REGISTER 1 (SR1)

RS 1

RSO

o

0

R/W

AC

7

6

5

4

3

2

1

0

IRQ

TDRA/FC

TXU

CTS

FD

LOOP

S2RQ

RDA

X

bO - Receiver Data Available (RDA) - The RDA status
bit reflects the state of the RDA status bit in status register
#2. It provides the means of achieving data transfers of
received data in the full Duplex Mode without having to read
both status registers.

b5 - Transmitter Underrun (TxU) - When the transmitter runs out of data during a frame transmission, an underrun
occurs and the frame is automatically terminated by
transmitting an Abort. The underrun condition is indicated
by the TxU status bit. TxU can be cleared by means of the
Clear Tx Status Control bit or by Tx Reset.

b1 - Status Register #2 Read Request (S2RQ) - All the
status bits (stored conditions) of status register #2 (except
RDA bit) are logically ORed and indicated by the S2RQ
status bit. Therefore, S2RQ indicates that status register #2
needs to be read. When S2RQ is "0", it is not necessary to
read status register #2. The bit is cleared when the appropriate bits in status register #2 are cleared or when Rx
Reset is used.

b6 - Transmitter Data Register Available/Frame Complate (TDRA/FC) - The TDRA Status bit serves two purposes depending upon the state of the Frame Complete/TDRA Select control bit. When this bit serves as a
TDRA status bit, it indicates that data (to be transmitted)
can be loaded into the Tx Data FIFO register. The first
register (Register '1) of the Tx Data FIFO being empty
(TDRA= "1") will be indicated by the TDRA Status bit in the
"1-Byte Transfer Mode." The first two registers (Registers
#1 and '2) must be empty for TDRA to be high when in the
"2-Byte Transfer Mode." TDRA is inhibited by Tx Reset, or
CTS being high.
When the Frame Complete Mode of operation is selected,
the TDRA/FC status bit goes high when an abort is transmitted or when a flag is transmitted with no data in the Tx FIFO.
The bit remains high until cleared by resetting the TDRA/FC
control bit or setting the Tx Reset bit.

b2 - Loop Status (LOOP) - The LOOP status bit is used
to monitor the loop operation of the ADLC. This bit does not
cause an IRQ. When Non-Loop Mode is selected, LOOP bit
stays "0". When Loop Mode is selected, the LOOP status bit
goes to "1" during "On-Loop" condition. When ADLC is in
an "Off-Loop" condition or "Go-Active-On-PolI" condition,
the LOOP status bit is a "0".
b3 - Flag Datected (FD) - The FD Status bit indicates
that a flag has been received if the Flag Detect Enable control
bit has been set. The bit goes high at the last bit of the Flag
Character received (when the Flag Detect Output goes low)
and is stored until cleared by Clear Rx Status or Rx Reset.

b7 - Interrpt Request (IRQ) - The Interrupt Request
status bit indicates when the IRQ output is in the active state
(IRQ Output= "0"1. The IRQ status bit is subject to the same
interrupt enables (RIE, TIE) as the IRQ output, i.e., with both
transmitter and receiver interrupts enabled, the IRQ status
bit is a logical ORed indication of Status Register 1 status
bits. The IRQ bit only reflects the set status bits which have
interrupts enabled. The IRQ status bit simplifies status inquiries for polling systems by providing single bit indication
of service requests.

b4 - Clear-to-Send (CTS) - The CTS input positive transition is stored in the status register and causes an IRQ (if
Enabledl. The stored CTS condition and its IRQ are cleared
by Clear Tx Status control bit or Tx Reset bit. After the
stored status is reset, the CTS status bit reflects the state of
the i l l input.

3-543

I

MC6854

STATUS REGISTER 2 (SR2)

RS1

o

I

RSO

RiW AC

7

6

5

4

3

2

1

0

RDA

OVRN

DCD

ERR

Rx

Rx

FV

AP

ABT

Idle

x

bO - Address Present (AP) - The AP status bit provides
the frame boundary and indicates an Address octet is
available in the Rx Data FIFO register. In the Extended Addressing Mode, the AP bit continues to indicate addresses
until the Address field is complete. The Address present
status bit is cleared by reading data or by Rx Reset.

b1 - Frame Valid (FV) - The FV status bit provides the
frame boundary indication to the MPU and also indicates
that a frame is complete with no error. The FV status bit is
set when the last data byte of a frame is transferred into the
last location of the Rx FIFO (available to be read by MPU).
Once FV status is set, the ADLC stops further data transfer
into the last location of the Rx FI FO (in order to prevent the
mixing of two frames) until the status bit is cleared by the
Clear Rx Status bit or Rx Reset.

Abort condition is cleared by the Clear Rx Status Control bit
or Rx Reset.
b4 Frame Check Sequence/ Invalid Frame Error
(ERR) - When a frame is complete with a cyclic redundancy
check (CRC) error or a short frame error (the frame does not
have complete Address and Control fields), the ERR status
bit is set instead of the Frame Valid status bit. Other functions, frame boundry indication and control function, are exactly the same as for the Frame Valid status bit. Refer to the
FV status bit.
b6 - Data Carrier Detect (DCD) - A positive transition
on the DCD input is stored in the status register and causes
an IRO (if enabled), The stored DCD condition and its IRO
are cleared by the Clear Rx Status Control bit or RX Reset.
After stored status is reset, the DCD status bit follows the
state of the input. Both the stored DCD condition and the
DCD input cause the reset of the receiver section when they
are high.

b2 - Inactive Idle Received (Rx Idle) - The Rx Idle status
bit indicates that a minimum of 15 consecutive "1's" have
been received. The event is stored within the status register
and car) cause an interrupt. The interrupt and stored condition are cleared by the Clear Rx Status Control bit. The
Status bit is the Logical OR of the receiver idling detector
(which continues to reflect idling until a "0" is received) and
the stored inactive idle condition.

b6 - Receiver Overrun (OVRN) - OVRN status indicates
that receiver data has been transferred into the Rx FI FO
when it is full, resulting in data loss. The OVRN status is
cleared by the Clear Rx Status bit or Rx Reset. Continued
overrunning only destroys data in the first FIFO Register.
b7 - Receiver Data Available (RDA) - The Receiver Data
Available status bit indicates when receiver data can be read
from the Rx Data FIFO. When the prioritized status mode is
used, the RDA bit indicates that non-address and non-last
data are available in the Rx FIFO. The receiver data being
present in the last register of the FIFO causes RDA to be high
for the "1-Byte Transfer Mode." The RDA bit being high indicates that the last two registers are full when in the "2-Byte
Transfer Mode." The RDA status bit is reset automatically
when data is not available.

b3 - Abort Received (RxABT) - The RxABT status bit
indicates that seven or more consecutive "1's" have been
received. Abort has no meaning under out-of-frame conditions; therefore, no interrupt nor storing of the status will occur unless a Flag has been detected prior to the Abort. An
Abort Received when "in frame" is stored in the status
register and causes an IRO. The status bit is the logical OR of
the stored conditions and the Rx Abort detect logic, which is
cleared after 15 consecutive "1 's" have occurred. The stored

3-544

MC6854

PROGRAMMING CONSIDERATIONS
1. Status Priority - When the prioritized status mode is used, it is best to test for the lowest priority conditions first.
The lowest priority conditions typically occur more frequently and are the most likely conditions to exist when
the processor is interrupted.
2. Stored va Present Status - Certain status bits (DCD,
CTS, Rx Abort, and Rx Idle) indicate a status which is the
logical OR of a stored and a present condition. It is the
stored status that causes an interrupt and which is
cleared by a Status Clear control bit. After being cleared,
the status register will reflect the present condition of an
input or a receiver input sequence.
3. Clearing Status Registers - In order to clear an interrupt
with the two Status Clear control bits, a particular status
condition must be read before it can be cleared. In the
prioritized mode, clearing a higher priority condition
might result in another iRO caused by a lower priority
condition whose status was suppressed when a status
register was first read. This guarantees that a status condition is never inadvertently cleared.
4. Clearing the Rx FIFO - An Rx Reset will effectively clear
the contents of all three Rx FIFO bytes. However, the
FIFO may contain data from two different frames when
abort or DCD failure occurs. When this happens, the data
from a previously closed frame (a frame whose closing
flag has been received) will not be destroyed.
5. Servicing the Rx FIFO in a 2-Byte Mode - The procedure
for reading the last bytes of data is the same, regardless of
whether the frame contains an even or an odd number of
bytes. Continue to read 2 bytes until an interrupt cocurs
that is caused by an end-of-frame status (FV or ERR).
When this occurs, indicating the last byte either has been
read or is ready to ~e read, switch temporarily to the
1-byte mode with no prioritized status (control register 2).

Test RDA to indicate whether a 1-byte read should be
performed. Then clear the frame end status.
6. Frame Complete Status and R'fS Release - In many
cases, a MODEM will require a delay for releasing RTS.
An 8-bit or 16-bit delay can be added to the ADlC RTS
output by using an Abort. At the end of a transmission,
frame complete status will indicate the frame completion.
After frame complete status goes high, write "1" into the
Abt control bit (and Abt Extend bit if a 16-bit delay is required), After the Abt control bit is set, write "0" into the
RTS control bit. The transmitter will transmit eight or sixteen "1's" and the RTS output will then go high
(inactive).
7. Note to users not using the MC6800 - (a) Care should be
taken when performing a write followed by a read on successive E pulses at a high frequency rate. Time must be
allowed for status changes to occur. If this is done, the
time that E is low between successive write/ read E pulses
should be at least 500 ns. (b) The ADlC is a completely
static part. However, the E frequency should be high
enough to move data through the FIFOs and to service
the peripheral requirements. Also, the period between
successive E pulses should be less than the period of RxC
or TxC in order to maintain synchronization between the
data bus and the peripherals.
8. Clear-to-Send (CTS) - The CTS input, when high, provides a real-time inhibit to the TDRA status bit and its
associated interrupt. All other status bits will be operational. Since it inhibits TDRA, CTS also inhibts the TDSR
DMA request. The CTS input being high does not affect
any other part of the transmitter. Information in the Tx
FIFO and Tx Shift Register will, therefore, continue to be
transmitted as long as the Tx ClK is running.

3·545

I

®

MOTOROLA

Me68S9

Advance Information
MOS
DEPLETION LOAD
(N-CHANNEL, SILICON-GATE)

DATA SECURITY DEVICE

DATA SECURITY DEVICE

I

The MC6859 Data Security Device (DSD) is a monolithic MOS integrated circuit designed to be integrated into a wide range of equipment requiring protection of data by the employment of cryptographic
measures.
The cryptographic algorithm utilized by the device is the Data Encryption Standard (DES) as adopted by the U.S. Department of Commerce,
National Bureau of Standards (NBS), in publication FIPS PUB 46
(1-15-1977).
Through the use of flexible on-chip control and status circuitry and
external control lines, the DSD provides direct capability of adapting the
functional implementation of the DES algorithm for various specific
system requirements for data protection.
• Direct Compatibility with the M6800 Microprocessor Family
• Data Encryption Standard Algorithm
• Two Separate Interrupt Output Lines for Program Controlled
Interrupt Capability
• Up to 400 KBPS Throughput Rate of 64-Bit Block Cipher (Exclusive
of Software Overhead)

L SUFFIX
CERAMIC PACKAGE
CASE 716

• TTL Compatible
• Single + 5 V Power Supply
PIN ASSIGNMENT

IROPE

06

07
DATA SECURITY DEVICE BLOCK DIAGRAM
MPU

AO

05

A1

04

A2

03

Vee

02

R/W

00

01

2XE
eS4

VSS

eS3

CS1

eso

eS2

NOTICE

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3·546

•

This product may not be exported
without prior approval from the U.S.
Department of State, Office of Munitions Control.

MC6859

MAXIMUM RATINGS
Characteristics
Supply Voltage
Input Voltage
Operating Temperature Range
MC6859

VCC
Yin

Value
-0.3 to +7.0
-0.3 to + 7.0

TA

TL to TH
o to 70

°c

T stg

-55 to + 150

°c

Symbol

Storage Temperature Range

Unit
V
V

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precuations be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either
VSS or VCC!.

THERMAL CHARACTERISTICS

POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °C can be obtained from:
T J = T A + (PD e8JA)

I

(1)

Where:
T A - Ambient Temperature, °C
8JA- Package Thermal Resistance, Junction-to-Ambient, °C/W
PD - PINT + PPORT
PINT-ICC x VCC, Watts - Chip Internal Power
PPORT- Port Power DisSipation, Watts - User Determined
For most applications PPORT. PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and T J (if PPORT is neglected) is:
PD=K+(TJ+273°C)
(2)
Solving equations 1 and 2 for K gives:
K= PDe(T A + 273°C) +8JAePD 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known T A. Using this value of K the values of PD and T J can be obtained by solving equations (1) and (2) iteratively for any
value of TA.

DC ELECTRICAL CHARACTERISTICS (VCC=5 0 Vdc ±5% '¥SS=O TA=TL to TH unless otherwise noted)
Symbol

Min

Typ

Max

Unit

Input High Voltage

VIH

VSS+2.0

-

V

Input Low Voltage

VIL

-

Input Leakage Current (Vin = 0 to 5.25 V)

lin

VSS-0.3
-

1.0

VCC
VSS+0.8
2.5

p.A

Characteristic

V

Three-State (Off State) Input Current (Vin = 0 to 5.25 V)

00-07

liZ

-

2.0

10

p.A

Output High Voltage (ILoad= -205 p.A) (See Figure 2)

00-07

VOH

VSS+2.4

-

-

V

00-07
IROPE,IROR
IROPE,IROR

VOL

-

-

-

-

1.0

-

-

VSS+0.4
VSS+0.6
10
1000

V

-

Output Low Voltage
OLoad=1.6mA)
OLoad=3.2 mAl (See Figure 2)
Output Leakage Current (Off State) (VOH = 2.4 V)
Internal Power Dissipation (Measured at T A = OOC)
Input Capacitance (Vin=O, TA=25°C, f= 1.0 MHz)
Output Capacitance (Vin=O, TA=25°C, f= 1.0 MHz)

00-07
All Others
IROPE,IROR

3-547

IOZ
PINT
, Cin
Cout

-

-

-

-

p.A
mW

12.5
7.5

pF

50

pF

MC6859

BUS TIMING CHARACTERISTICS

I

Ident.
Number
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17

Symbol

Characteristic
Cycle Time
Pulse Width, E Low
Pulse Width, E High
Clock Rise and Fall Time
2XE to E High Delay Time
2XE to E Low Delay Time
Pulse Width 2XE Low
Pulse Width 2XE High
Address Hold Time
Address Setup Time Before E
Chip Select Setup Time Before E
Chip Select Hold Time
Read Data Hold Time
Output Data Delay Time
Write Data Hold Time
Input Data Setup Time* *
Interrupt Release Time

Min

Max

Unit

1.0
10
/los
tCYC
ns
430
PWEL
450
ns
PWEH
25
ns
tr,tf
0
ns
tDH
ns
0
tDL
210
ns
PW2l
220
ns
PW2H
10
ns
tAH
ns
80
tAS
80
ns
tcs
10
ns
tCH
20
ns
50*
tDHR
290
ns
tDHW
10
ns
tDDR
165
ns
tDSW
1200
ns
tlR
*The data bus output buffers are no longer sourcing or sinking current by tDHR maximum (high Impedance).
* * Data is latched into the internal registers on the falling edge of 2XE and while enable is high. Therefore, for system considerations,
tDSW=tDSW1 +tD+2X tf· Minimize tD to ensure operation at 1 MHz. tDSWl is the data setup time for the "AK6" mask set.

-

FIGURE 1 -

BUS TIMING

2XE

R/W, ADD
(Non-Muxedl

-----+~~~~--------------~~~~--+_----------------------------_1~~~~~-

Read Data
Non-Muxed _ _

MPU Read Data Non-Muxed

Write Data
Non-Muxed

MPU Write Data Non-Muxed

+ ......

---+....iiIf

NOTES:
1. Voltage levels shown are VLsO.4 V, VH~2.4 V, unless otherwise specified.
2. Measurement points shown are O.B V and 2.0 V, unless otherwise specified.

3-548

MC6859

FIGURE 2 -

BUS TIMING TEST LOADS

(00-07)

IROPE.IROR

Vee

Vee
RL=2.5 kO

....._I~-......

Test Point n----.-~

e
130 pF

MMD6150

or Equiv.

3 kO

Test Point

R
11.7 k
MM072) line, a 2XEnabie
(2XE) clock line, and two interrupt request lines. These
signals permit the M6800 MPU to control the DSD and perform data transfers between the two.

Modes - Operational and control modes are invoked by
addressing DSD registers at the addresses in Tables 1 and 2.
TABLE 1 - OPERATIONAL MODES
Control Address
Operational Mode
AO, A1, A2 R/W
0 0 0
W Write Data/"C" Key Operation (1st 7 bytes)

'1
'0
0
0

Bidirectional Data Bus (OO-D7) - The bidirectional data
lines (DO-D7) allow the transfer of information between the
MPU and DSD. The data bus input/output drivers are threestate devices which remain in the high-impedance (off) state
except when the MPU performs a DSD read or write operation.

I

0
0
0
1·

1

W

Encipher Data

1
1

W

Decipher Data

R

Read Data

0

R

Read Status

TABLE 2 - CONTROL MODES

Chip Select (CSO, CS1, CS2, CS3, and CS4) - These five
signals are used to activate the data bus interface and allow
DSD data transfers. When CSO= CS3= CS4= 1 and
CS1=CS2=O, the device is selected.

Control Address
AO, A1, A2 R/W

1

0
1
'0
'1

Read/Write (R/W) - With the DSD selected, this input
controls the direction of data transfer on the data bus. When
R/Wis high, data in the DSD is read by the MPU on the'trailing edge of E. A low state on the R/W line enables data
transfer from the MPU on the trailing edge of the 2XE signal.

1

Control Mode

0
1
1
1

0
0
0
1

1

1

W

Encipher Secondary Key

0

0

R

Transfer Major Key

W

Reset/Initialize

W

Enter Major Key

W

Enter Plain Secondary Key

W

Decipher Secondary Key

* Instruction initiated after eighth byte of Key Block entry.
Enable (E) and 2XEnable (2XE) - The rising edge of the
Enable input initiates data transfer from the DSD to the MPU
during a read cycle. The falling edge of the Enable input latches MPU data into the DSD during a write cycle. The 2XE
input is used in processing the encryption/decryption
algorithm for all mask sets. E and 2XE are completely asynchronous. See section on Mask Sets for exceptions on prior
revision of the DSD.
Reset (RESET) - This input signal is used to initialize the
internal control logic, status flags, and counters of the DSD.
The contents of the active key register and major key register
remain unchanged. The RESET function should be coupled
with the system power-on reset to provide orderly system
initialization. It may also be used as a master reset to the chip
during system operation.
To abort the encryption algorithm before the required 320
clock cycles (2XE) have occurred, it is necessary to provide a
RESET signal or a software reset command to the DSD.
When this occurs, information in the data register and active
key register is no longer valid. The contents of the major key
register are unaffected.
Address Lines (AO, Al, A2) - These inputs are used in
conjunction with the RiW line to select one of eleven possible DSD operations, as shown in Tables 1 and 2. The DSD is
accessed via MPU read and write operations in much the
same manner as a memory device.
NOTE:
Instructions performing operations directly on memory
should not be used when the DSD is accessed. Since the
DSD uses the R/W'line as an additional reg.ister select input,
read-modify-write type instructions will conflict with normal
operation of the Data Security Device.

Interrupt Requests - These open drain outputs are used
to convey internal DSD status information to the MPU.
Ready Interrupt Request (lROR) - This active low output signals the MPU that the DSD is
ready to initiate another operation. The IROR
signal will be inactive during encryption/decryption or key transfer.
Parity Error Interrupt Request (lROPE) - This
active low output is used t·,) Signal the MPU that
the DSD has detected a parity error. The IROPE
signal will remain low until a hardware or software reset is received.
DSD FUNCTIONAL DESCRIPTION
The MC6859 Data Security Device appears to an MPU
system as an interface adapter device. An example of a
system with the encryption function is shown in Figure 4.
Internal construction of the DSD is illustrated by the block
diagram. The device consists of a Single 8-bit data bus buffer
with three-state operation, through which data may be
ent~red into:
1) the 56-bit active key register
2) the 54-bit major key register
3) the 64-bit data register
Output data from the status register or the data register is
also switched through the data bus buffers.
At the bus interface, the DSD data register appears as
eight addressable memory locations to the MPU, through
which the operational mode of the chip may be selected,
chip status monitored, key or data written into. the device,
and data read from the device.

3-550

MC6859

OPERATING MODES
As shown in Table 1, the operation of the DSD is split into
five major modes:
1) status readout
2) loading of data or encrypted key
3) data encryption
4) data decryption
5) data readout
These and additional control modes are activated by three
address input lines and a read/write input line.

Read Status - Only two bits are used in the status
readout, D7= Parity Error (PE) and D6= READY. The remaining six bits are always read as logic zeros. A read of the
status register does not change these bits.
The PE flag is set when a parity error is detected while
loading either a major or secondary key or when the active
key is checked during algorithm operation. The PE flag remains set and the IROPE signal will remain low until a hardware/software reset is received.
The READY flag is set and the IROR output goes high
whenever the device is processing a block of data. The flag is
cleared, pulling the IROR output low, whenever the DSD is
not encoding/decoding data or transferring major key. IROR
may be tied to IRO of a M6800 family processor for interruptdriven encryption if no other peripherals share the IRO line.
Encipher Data - To encipher an 8 byte block of data, the
first seven bytes are written to the Write Data/"C" Key
register. The eighth byte is written to the Encipher Data
register. This automatically initiates the encryption process.

Data is always processed using the current Active Key. During algorithm operation, the DSD constantly performs parity
checking on the contents of the active key register. The busy
flag will be set during encryption and then reset when the
algorithm has finished. Completion requires 320 cycles of
2XE. During this time the DSD will ignore all external commands except status read, hardware reset and software
reset.
Decipher Data - This process is identical to encipher data
except that the eighth byte is written to the Decipher Data
register. During decipher Or encipher only a read status
register, hardware reset, or software reset will be recognized. All other commands will be ignored.
Read Data - This command is normally executed upon
completion of the encipher/decipher algorithm (indicated by
READY = Q). A read prior to completion of busy will result in
all zeros being read from DO-D7. As each byte of data is read,
zeros are automatically shifted into the data register to ensure data security.
CONTROL MODES
Shown in Table 2 are the control modes which facilitate
programming of the primary and secondary keys.
Reset/Initialize - The DSD may be software reset by
writing the reset/initialize command at any time the data bus
is ignored. Like the hardware reset, this command initializes
the internal control logic, status flags, and counters without
altering the contents of the active key register or the major
key register. If a hardware or software reset is issued during
the algorithm processing, the information in the data register
and active key register will no longer be valid. However, the
contents of the major key register are not affected.

FIGURE 4 - M6800 MICROCOMPUTER FAMILY BLOCK-DIAGRAM

M600J
Microprocessor

t------T""------y------~------....._-___l~ Data
Bus

t--+---...,.--t----"""T-+----,--+-----T"""-t--. Address
Bus

3-551

I

MC6859

Load Major Key - An unencrypted key will be entered into both the active key register and the major key register
when eight consecutive bytes are written into the Enter Major Key Register. Parity error checking is automatically performed.

more receivers, the following typical sequence might be used
to transmit confidential data:
1) A software reset is issued to each DS D by its M PU.
2) The sending MPU loads a major key (eight bytes) into
its DSD. This will serve as the active key if a secondary
key is not entered.
3) The receiving station must also load this same major
key before data transmission can begin. If the current
major (or secondary) key is not known in advance, it
can be transmitted by the sending MPU, but may not
be encoded as the receiving M PU system has no key
to decode it by. The MPU at the receiving station must
be programmed with the mode and format being used
for data transmission so its DSD can process the data
correctly. At this point both the transmitting and
receiving stations are ready for data transfer.
4) The sending MPU writes eight bytes of data into its
DSD which enciphers them.
5) The sending MPU retrieves eight bytes of encrypted
data from its DSD and transmits them to the receiving
MPU.
6) The receiving MPU writes these eight bytes of data into its DSD to be deciphered.
7) The receiving MPU retrieves eight bytes of data from
its DSD in the original plain text form.
Steps four through seven are repeated for each 8-byte
block of data to be transmitted. If the major key or secondary
key is to be changed, steps two and three must also be carried out.

Load Plain Secondary Key - An unencrypted key may be
loaded into the active key register and simultaneously
checked for parity errors by writing eight consecutive bytes
into the Enter Plain Secondary Key Register. The Major Key
Register is unaffected.

I

Encipher Secondary Key - After a secondary key is loaded, it can be enciphered or deciphered (the source of an encrypted key is usually another DSD). A secondary key may
be enciphered by loading the first seven bytes of plain text to
the Write Data/"C" Key register. The eighth byte is entered
to the Encipher Secondary Key register. This causes the
secondary key to be enciphered using the current major key
and automatically loaded into the Active Key register and
checked for parity. This operation requires 328 cycles of 2XE.
Decipher Secondary Key - This function is similar to the
Encipher Secondary Key operation. The first seven bytes of
the key are loaded into the Write Datal"C" Key register. The
eighth byte is entered by addressing the Decipher Secondary
Key register. The secondary key is then deciphered using the
current major key and automatically loaded into the Active
Key register and checked for parity. This operation requires
328 cycles of 2XE.
Transfer Major Key - The contents of the Major Key
register will be transferred to the Active Key register by a
read of the Transfer Major Key register. The data bus is ignored. The Major Key register remains unchanged. This
operation requires eight cycles of 2XE.
KEY CONVENTIONS
The key used for coding is a 56-bit data word plus eight
bits of odd parity. In the DSD seven bits of key and the parity
bit make up a key character. Eight key characters make up
the total key information required by the DSD if parity errors
are to be checked via the PE signal. If parity is not needed for
some reason, then the parity bit need not be calculated and
can be left as a zero. An example key with parity is shown in
Table 3.
TABLE 3 - EXAMPLE KEY

Binary Value

Key Character
Byte 1

Hex Value

7C

0

Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
BytsS

A1

1 0 o 0 0
0 0 0 1 0 0 0

OataUnes

10

45
4A
1A

6E
57

1 1 1 1 1 0

Parity
0

1 0

1

0

0
1

1
0 1
0 0
0 1

0 0 0 1 0
0 0 1 0 1
0 1 1 0 1

0
0

1 0 1 1 1
1 0 1 0 1 1

0
1

07 D6 05 D4 03 02 01

DO

0

TYPICAL SYSTEM OPERATION
For a communications link between a sender and one or

SECURITY CONSIDERATIONS
The security of a system employing the NBS Data Encryption Standard (DES) depends only upon the key used, not
the availability of the algorithm or of equipment used to implement the algorithm. The key is the most critical piece of
information in the system and security of the key itself must
be maintained both inside and outside the system.
Guidelines to be used in selecting a key are:
• Consider the key to be a single 56-bit number
• Avoid bias in selecting the key
• Change key as frequently as practical
One way to help ensure the security of the key is to make
frequent use of secondary keys. Secondary keys can be
generated by the sender and distributed selectively to one or
more receivers. Since the MC6859 can encipher or decipher
secondary keys using the major key, the sender can transmit
the secondary key in encrypted form to further ensure
system security. However, the receiver must be aware that a
secondary key is being transmitted and must decrypt the key
if it was sent in encrypted form.
AssumiAg that secrecy of the key is maintained, it is nearly
impossible for an unauthorized user to decode an intercepted message into its original form. Since the DES
algorithm utilizes a 56-bit active key, there are 256 (or about
7 x 1016) possible encrypted messages which must be
searched to retrieve the original message. In addition, if the
key were changed regularly only a small portion of the
message would be retrieved for each successful exhaustive
search. Therefore, the basic "block cipher" technique
described in the Typical System Operation section is adequate for today's data security applications.

3·552

MC6859

If additional security is required for some reason, several
techniques can be used to increase data security. These include:

CFB DECIPHER
The baSic flow of the decipher CFB operation is shown in
Figure 6.
The same initial fill as used for enCiphering must be used
to initialize the decipher RAM buffer. The same key used to
encipher must also be used to load the DSD active key
register prior to receiving cipher text bytes. When a cipher
text byte is received it is exclusive ORed with the key byte
generated by the DSD and the result is the plain text data
byte. The received cipher text byte is shifted into the RAM
buffer and becomes the newest RAM buffer byte. The oldest
RAM buffer byte is discarded and the eight byte RAM buffer
is loaded into the DSD for block deciphering. One byte of the
DSD data register is read out and this byte becomes the key
byte for the next cipher text byte received.

• Perform multiple encryption and/or decryption using
the same key or different keys
• Reverse the algorithm (decipher-transmit-encipher)
• Utilize cipher feedback or other feedback techniques
The process of multiple encryption or decryption is an
easy way to effectively increase the size of the key to any
desired length. For example, the sender might successively
encipher, decipher, and encipher a block of data using one
key for the encipher operations and another for the decipher
operation. The receiver would then have to decipher, encipher, and decipher the data using the same pair of keys.
This technique would greatly increase data security while
reducing throughput by a factor of three. Many such multiple encryption combinations are possible.
An easy way to increase security without reducing
throughput is to perform the DES algorithm "in reverse." In
other words, data or keys can be deciphered by the sender
and then enciphered by the receiver to yield the original
message. This technique works because the enciphering and
deciphering algorithms are "mirror images" of each other.
Many different feedback techniques are available as alternatives to the basic 64-bit block cipher. One of these, known
as cipherfeedback (CFB), is described below. CFB is a byteoriented implementation in that only one byte is transmitted
at a time. Thus, throughput is reduced by a factor of eight
(excluding software overhead). Implementation of the CFB
technique is more dependent upon the system configuration
than is the block cipher.

FIGURE 5 - CFB ENCIPHER DATA FLOW
(TRANSMITTING)

I

Ct-7
RAM
Buffer

DES
Algorithm

Ct+1

Pt+1

CFB ENCIPHER
The basic flow of the CFB encipher procedure is shown in
Figure 5.
An initial eight byte fill of the RAM buffer must be done
prior to accepting plain text bytes for enCiphering. This information can be considered to be a data subset of the key, but
may be any combination of eight-bit bytes as long as the
deciphering device uses the same initial fill.
After the block of data in the RAM buffer is enciphered,
one byte of enCiphered data is read from the DSD. This byte
is the key byte (Kt+ 1). The plain text byte (Pt+ 1) is exclusive ORed with the key byte and the result is the cipher
text byte (Ct + 1). The cipher text byte is shifted into the bottom of the RAM buffer and now is the newest byte in the
block. The oldest previous byte is discarded. The cipher text
byte is now available for use. The new RAM buffer block is
loaded into the DSD for enciphering and yields the next key
for further processing.

FIGURE 6 - CFB ENCIPHER DATA FLOW
(RECEIVING)

RAM
Buffer

DES
Algorithm

Ct-7

Ct+1------~----------~~

To purchase a copy of the NBS Data Encryption Standard ask for the Federal Information
Processing Standards (FIPS) Publication, FIPSP 46 at the following address:
National Technical Information Service
U.S. Department of Commerce
5285 Port Royal Road
Springfield, VA 22161

3-553

Pt+1

MC6859

Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked
and is believed to be reliable, Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the
purchaser any license under the patent rights of Motorola or others.
The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves
the right to make any changes to the information and the product(s) to which the information applies and to discontinue
manufacture of the product(s) at any time.

ORDERING INFORMATION

MC68A5~frl:

=rTf

I

Levell "S" = 10 Temp Cycles - (- 25 to 150°C);
Hi Temp testing at T A max.
Level 2 "0" = 168 Hour Burn-in at 125°C
Level 3 "OS" = Combination of Levelland 2.

Motorola Inte.,,,,,. c;,,",,
M6800 Family
Blanks= 1.0 MHz
A=1.5MHz
B=2.0 MHz
Device Designation
In M6800 Family
Temperature Range - - - - - - - - - - '
Blank=Oo- + 70°C
C= _40°_ +85°C
Package ------------~
L= Ceramic

BETTER PROGRAM

Better program processing is available on all types listed. Add
suffix letters to part number.
Levell add "S"

Level 2 add "0"

Level 3 add "OS"

3-554

Device

Temperature Range

MC6859L

o to 70°C

®

MC6875
MC6875A

MOTOROI.A
Specifications and Applications
Information

M6800 TWO·PHASE
CLOCK GENERATOR/DRIVER

M6800 CLOCK GENERATOR

SCHOTTKY MONOLITHIC
INTEGRATED CIRCUIT

Intended to supply the non-overlapping <1>1 and <1>2 clock signals
required by the microprocessor, this clock generator is compatible
with 1.0, 1.5, and 2.0 MHz versions of the MC6800. Both the
oscillator and high capacitance driver elements are included along
with numerous other logic accessory functions for easy system
expansion.
Schottky technology is employed for high speed and PNP-buffered
inputs are employed for NMOS compatibility. A single +5 V power
supply, and a crystal or RC network for frequency determination
are required.

I

Typical MPU System with Bus Extenders
L SUFFIX
CERAMIC PACKAGE
CASE 620-02
GND +5 V

c::::J

-r-

4 x fo MPU

PIN CONNECTIONS

ADDRESS
AND
CONTROL
BUS

DATA
BUS

Xl

VCC

X2

MPU 1

Ext In

Reset Output

4 x fo

MPU 2

2 x fo
Memory
Ready
Bus 2

Power-On Reset

Ground

Mamory Clock

DMA/Ref Grant
DMA/Raf Req

ORDERING INFORMATION
Device
MC6875L
MC6875AL

3-555

I
I
I

Temperature Range
to +700C

o

-55 to

+125 0

C

I

Pack. .e

I Ceramic

Dip
/Ceramic Dip

MC6875, MC6875A
ABSOLUTE MAXIMUM RATI NGS

(Unless otherwise noted T A

= 25 0 e.)

Symbol

Value

Unit

Vee

+7.0

Vdc

Input Voltage

VI

+5.5

Vdc

Operating Ambient Temperature Range
MC6875L
MC6875AL

TA

Storage Temperature Range

T stg

-65 to +150

°c

TJ

175

°c

Ratinll
Power Supply Voltage

Operating Junction Temperature

°c

o

to +70
-55 to +125

NOTE:
Operation of the MC6875AL over the full military
temperature range (to maximum TA) will result in
excessive operating junction temperature.
The use of a clip on 16 pin heat sink similar to AAVID
Engi~eering, Inc., Model 5007 (RoCA = 18°CIW) is
recommended above TA = 95°C.

RECOMMENDED OPERATING CONDITIONS

Contact AAVID Engineering, Inc.
30 Cook Court
Laconia, New Hampshire 03246
Tel. (603) 524-4443

Rating
Power Supply Voltage
Operating Ambient Temperature Range

I

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted specifications apply over recommended power supply and temperature ranges.
Typical values measured at V CC = 5.0 V and T A = 25 0 C.)
Typ

Max

Symbol

Min

VOHM
VOHMK

VCC - 0.6

-

-

-

VOHB
VOHBK

2.4

-

-

-

-

Vec + 1.0

VOH4X

-

-

VOH

2.4
2.4

-

-

V

VOHR

2.4

-

-

V

VOLM
VOLMK

-

-

-

-

0.4
-1.0

VOLB
VOLBK

.-

-

0.5

-

-

-1.0

VOL4X

-

-

VOL

-

-

0.5
0.5

V

VOLR

-

-

0.5

V

Input Voltage - High Logic State
Ext. In, Memory Ready and DMA/Refresh Request Inputs

VIH

2.0

Input Voltage - Low Logic State
Ext. In. Memory Ready and DMA/Refresh Request Inputs

VIL

-

-

0.8

VILH
VIHL

-

2.8
1.4

3.6

-1.0
-1.5

V

-

-

IIH

-

-

25

!lA

IIHA

-

-

50

!lA

IlL

-

-

-250

!lA

liLA

-

-

-250

!lA

Characteristic
Output Voltage - High Logic State
MPU ¢1 and ",2 Outputs
(Vce = 4.75 V, IOHM = -200 !lA)
(Vee = 5.25 V,IOHMK = +5.0 mAl
Bus ",2 Output
(Vee = 4.75 V, IOHB = -10 mAl
(Vee = 5.25 V,IOHBK = +5.0 mAl
4 x fa Output
(Vee = 4.75 V, VIH = 2.0 V, IOH4X = -500 !lA)
2 x fa, DMA/Refresh Grant and Memory Clock Outputs
(Vee = 4.75 V, IOH = -500 !lA)
Reset Output
(Vee = 4.75 V, VIH = 3.3 V, IOHR = -100 !lA)

V

V

V

V

V
-

V

MC6875L

VIK

MC6875AL

Input Current - High Logic State
Ext. In, Memory Ready and DMA/Refresh Request Inputs
(Vee = 4.75 V, VIH = 5.0 V)

= 5.0

.-

V

Input Thresholds - Power-On Reset Input (See Figure 2)
Output Low to High
Output High to Low

Power-On Reset
(Vee = 5.0 V, VIHR

VCC+l.0

V

(Vee = 4.75 V, VIL = 0.8 V,IOL4X = 16 mAl
2 x fa, DMA/Refresh Grant and Memory Clock Outputs
(Vee = 4.75 V, IOL = 16 rnA)
Reset Output
(Vce = 4.75 V, VIL = 0.8 V,IOLR = 3.2 mAl

= -5.0 rnA)

-

V

Output Voltage - Low Logic State
MPU "'1 and ",2 Outputs
(Vee = 4.75 V,IOLM = +200 !lA)
(Vee = 4.75 V,IOLMK = -5.0 mAl
Bus ",2 Output
(Vee = 4.75 V. IOLB = +48 mAl
(Vee = 4.75 V, IOLBK = -5.0 mAl
4 x fa Output

Input Clamp Voltage
(Vee = 4.75 V, lie

Unit

0.8
-

-

V)

Input Current - Low Logic State
Ext. In, Memory Ready and DMA/Refresh Request Inputs
(Vee = 5.25 V, VIL = 0.5 V)
Power-On Reset Input 1
(Vee = 5.25 V, VIL = 0.5 V)

3-556

MC6875, MC6875A
OPERATING DYNAMIC POWER SUPPLY CURRENT
Characteristic

Symbol

Min

Typ

Max

Unit

ICCN

-

-

150

mA

ICCMR

-

-

135

mA

ICCDR

-

-

135

mA

Power Supply Currents
(VCC = 5.25 V, fosc = 8.0 MHz, VIL = 0 V, VIH = 3.0 V)
Normal Operation
(Memory Ready and DMA/Refresh Request Inputs at
High Logic State)
Memory Ready Stretch Operation
(Memory Ready Input at Low Logic State;
DMA/Refresh Request Input at High Logic State)
DMA/Refresh Request Stretch Operation
(Memory Ready Input at High Logic State;
DMA/Refresh Request Input at Low Logic State)

SWITCHING CHARACTERISTICS
(These specifications apply whether the Internal Oscillator (see Figure 9) or an External Oscillator is used (see Figure 10).
Typical values measured at V CC = 5.0 V, T A = 25 0 C, fo = 1.0 MHz (see Figure 8).
Characteristic

Symbol

Min

Typ

Max

Unit

to

500

-

-

ns
ns

400
230
180

-

-

-

-

-

MPU <1>1 AND <1>2 CHARACTERISTICS
Output Period (Figure 3)
Pulse Width (Figure 3)
(to = 1.0 MHz)
(fo = 1.5 MHz)
(fo = 2.0 MHz)

tPWM

Total Up Time (Figure 3)
(fo = 1.0 MHz)
(fo = 1.5 MHz)
(fo = 2.0 MHz)

tUPM

ns
900
600
440

-

-

-

-

-

-

Delay Time Referenced to Output Complement (Figure 3)
Output High to Low State (Clock Overlap at 1.0 V)

tpLHM

0

-

-

ns

Delay Times Referenced to 2 x fo (Figure 4 MPU <1>2 only)
Output Low to High Logic State
Output High to Low Logic State

tPLHM2X
tpHLM2X

-

-

-

-

85
70

ns
ns

tTLHM
tTHLM

-

-

-

-

25
25

ns
ns

Transition Times (Figure 3)
Output Low to High Logic State
Output High to Low Logic State
BUS <1>2 CHARACTERISTICS
Pulse Width
(fo = 1.0
(fo = 1.5
(fo = 2.0

- Low Logic State (Figure 4)
MHz)
MHz)
MHz)

ns

tPWLB

Pulse Width - High Logic State
(fo = 1.0 MHz)
(fo = 1.5 MHz)
(fo = 2.0 MHz)

430
280
210

-

-

-

-

-

-

450
295
235

-

-

480
320
240

-

-

-

-

-

-

25

-

20

-30
0

-

+25
+40

ns
ns

20
20

ns
ns

ns

tpWHB

Delay Times - (Referenced to MPU <1>1) (Figure 4)
Output Low to High Logic State
(fo = 1.0 MHz)
(fo = 1.5 MHz)
(fo = 2.0 MHz)
Output High to Low Logic State
(CL = 300 pF)
(CL = 100 pF)

ns

tpLHBMl
-

tPHLBMl

Delay Times (Referenced to MPU <1>2) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLHBM2
tPHLBM2

Transition Times (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tTLHB
tTHLB

3-557

-

-

-

-

-

I

MC6875, MC6875A
SWITCHING CHARACTERISTICS (continued)
Characteristic

Typ

Symbol

Min

Delay Times (Referenced to MPU 4>2) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLHCM
tpHLCM

-50
0

Delay Times (Referenced to 2 x fo) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tpLHC2X
tpHLC2X

-

-

tTLHC
tTHLC

-

-

Max

Unit

MEMORY CLOCK CHARACTERISTICS

Transition Times (Figure 4)
Output Low to High State
Output High to Low State

-

-

-

-

+25
+40

ns
ns

65
85

ns
ns

25
25

ns
ns

ns
ns

2 x fo CHARACTERISTICS
Delay Times (Referenced to 4 x fa) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLH2X
tpHL2X

Delay Time (Referenced to MPU 4>1) (Figure 4)
Output High to Low Logic State
(fo = 1.0 MHz)
(fa = 1.5 MHz)

I

-

-

-

-

50
65

365
220

-

-

-

-

.-

-

-

-

25
25

ns
ns

50
30

ns
ns

ns

tPHL2XMl

Transition Times (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tTLH2X
tTHL2X

4 x fo CHARACTERISTICS
Delay Times (Referenced to Ext. In) (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tPLH4X
tPHL4X

-

-

-

-

Transition Time (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

tTLH4X
tTHL4X

-

-

25
25

ns
ns

Set-Up Times (Figure 5)
Low Input Logic State
High Input Logic State

tSMRL
tSMRH

55
75

-

-

-

-

ns
ns

Hold Time (Figure 5)
Low I nput Logic State

tHMRL

10

-

-

ns

Set-Up Times (Figure 6)
Low Input Logic State
High Input Logic State

tSDRL
tSDRH

65
75

-

-

-

ns
ns

Hold Time (Figure 6)
Low Input Logic State

tHDRL

10

-

-

ns

Delay Time Referenced to Memory Clock (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tPLHG
tpHLG

-15
-25

-

+25
+15

ns
ns

Transition Times (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tTLHG
tTHLG

-

-

-

-

25
25

ns
ns

tPLHR
tPHLR

-

-

1000
250

ns
ns

tTLHR
tTHLR

-

-

100

-

-

50

ns
ns

MEMORY READY CHARACTERISTICS

DMA/REFRESH REQUEST CHARACTERISTICS

DMA/REFRESH GRANT CHARACTERISTICS

RESET CHARACTERISTICS
Delay Time Referenced to Power-On Reset (Figure 7)
Output Low to High Logic State
Output High to Low Logic State
Transition Times (Figure 7)
Output Low to High Logic State
Output High to Low Logic State

DESCRIPTION OF PIN FUNCTIONS
-

A free running oscillator .t four times the MPU clock rite useful for a system sync signal

-

BUS.2

•
•

MEMORY CLOCK - An output nominitlly In phase With MPU .2 which tree runs during a refresh request cycle
POWER·ON RESET
A Schmitt trigger input which controls Reset A capacitor to ground is required 10 set the
desired time constant. Internal 50 k resIStor to Vec. See General Design Suggestions for
Manual Reset Operation

•

2 II fa

-

A fre. running oscillator It two times the MPU clock rate

•

OMA/REF REa

-

An lSynchronous input used to freeze the MPU clocks in th~ 4> 1 high, 4>2 low state for
dynamic memory r.frnh or cycl, steal DMA (Direct Memory Access)

•
•

REF GRANT
- A synchronous output used to synchronize the refresh or OMA operation to the MPU
MEMORY READY - An .synchronous input used to freeze the MPU clocks In the .110w.• 2 high state for slow
memoryinterflCe.

• MPU.l

MPU¢2

- Capable of driVing the.1 and

.2

inputs on two MC6800s

•

RESET

•
•

Xl,X2
EXT IN

3-558

-

An output nominally

In

phase with MPU 4>2 havmg MCBT26A type drive capability

- An output to the MPU and I/O devices
- Provision to attach a series resonant crystal or RC network
- Allows driving by an external TTL signal to synchronize the MPU to an eMtern.1 system

MC6875, MC6875A

FIGURE 1 - BLOCK DIAGRAM

Xl

X2

In

BUS 1 AND 2

FIGURE 2 - TYPICAL HYSTERESIS CHARACTERISTIC
OF RESET FUNCTION
5.0

- Gnd

I
l
= 5.0 V _
TA = 25 0 e

I-- Vee

~

4. 0

Cl

2:

;'"

3. 0

Cl

>

I-

2. 0

::;)

I::;)

Cl

i>

1. 0

o

o

1.0

2.0

3.0

4.0

VI, INPUT VOLTAGE (VOLTS), POWER-ON RESET PIN

5.0

Vov

=

1.0 V

= Clock

Overlap
measurement point

I

MC6875, MC6875A

FIGURE 4 - TIMING DIAGRAM FOR NON-STRETCHED OPERATION
(Memory Ready and DMA/Refresh Request held high continuously)
Ext_ In Input Voltage: 0 V to 3.0 V, f = 8.0 MHz, Duty Cycle = 50%, tTLHEX =tTHLEX

I

DMA/Refresh Grant

(Low)

3-560

= 5.0 ns

MC6875, MC6875A
FIGURE 5 - TIMING DIAGRAM FOR MEMORY READY STRETCH OPERATION
(Minimum Stretch Shown I
Input Voltage: 3.0 to 0 V. tTHLMR = tTLHMR = 5.0 ns

Memory Ready

0.8 V

~

DMA/Refresh Request

MPU 1

DMA/Aefresh Grant

(Low)

3-561

Irrelevant

I

MC6875, MC6875A
FIGURE 6 - TIMING DIAGRAM FOR DMA/REFRESH REQUEST STRETCH OPERATION
(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V. tTHLDR =tTLHDR = 5.0 ns

Memory Ready

~

I
-+----tPWDMA =

1.5

!;:;-----+-

OMA/Refresh Grant
0.8 V

0.8 V

3-562

Irrelevant

MC6875, MC6875A

FIGURE 7 - POWER ON RESET
Input Voltage: 0 to 5.0 V, f = 100 kHz - Pulse Width = 1.0

~S,

tTLH = tTHL = 25 ns

5.0 V ------+--+r----------------~

Power·On Reset

OV-----"

I

Reset
0.8 V

0.8 V

FIGURE 8 - LOAD CIRCUITS
For Bus r~2

For MPU (,1 and MPU 1,2

+5.0 V

RI.L

~

RLL
68

18 k

CL
All diodes are 1 N916

°

300 pF

I

RLH

240

or equivalent

MPU 1 CL

~

35 pF, RD = 20

MPU 2 C L

=

70 pF, RD

=

15

All diodes are 1 N916
or equ iva lent

n.
n.

For 4 x fo, 2 x fo, Memory Clock and DMA/Refresh Grant

For Reset Output

+5.0 Volts

RLL

CLO
100 pF

I

240

RLL=1.2k

CLO

RLH
4.7 k
All diodes are 1N916
or equivalent

100

PFI

All diodes are 1 N916
or equivalent

• Load capacitance includes fixture and probe capacitance

NOTE:
Operation of the MC6875AL over the full military temperature range (to maximum T A) will result in excessive
operating junction temperature.
The use of a clip on 16 pin heat sink similar to AAV ID
Engineering, Inc., Model 5007 (ReCA = 18o C/W) is
recommended above T A ~ 95 0 C.

3·563

Contact AAVID Engineering, Inc.
30 Cook Court
Laconia, New Hampshire 03246
Tel. (603) 524-4443

MC6875, MC6875A
APPLICATIONS INFORMATION
FIGURE 9 - TYPICAL RC FREQUENCY versus VOLTAGE
+8.0

V
~ +6.0
w

'"z
~

+4.0

i

+2.0

~

10-'"

...V
V

..,../

~

I

fo=1.0MHz _
@VCC=5.0V
TA =25'C -

./

_V
-2.0
4.5

/'

V

5.0

I

t-t--

I

5.5
6.0
VCC. SUPPLY VOLTAGE (VOL TS)

7.0

6.5

FIGURE 10 - TYPICAL RC FREQUENCY
versus TEMPERATURE
/

+1.0

/

~ +0.8

/

w

5'"z +0.6

/

>

~

/

/
/

+0.4

1/

a

~ +0.2

/'

/

to= 1.0 MHz _
@VCC = 5.0 V
TA =25'C -

./

~

GENERAL
The MC6875 Clock Generator/Driver should be located
on the same board and within two inches of the MC6800
MPU. Series damping resistors of 10-30 ohms may be
utilized between the MC6875 and the MC6800 on the <1>1
and <1>2 clocks to suppress overshoot and reflections.
The VCC pin (pin 16) of the MC6875 should be
bypassed to the ground pin (pin 8) at the package with a
0.1 /-IF capacitor. Because of the high peak currents
associated with driving highly capacitive loads, an ade. quately large ground strip to pin 8 should be used on the
MC6875. Grounds should be carefully routed to minimize
coupling of noise to the sensitive oscillator inputs. Unnecessary grounds or ground planes should be avoided near
pin 2 or the frequency determining components. These
components should be located as near as possible to the
respective pins of the MC6875. Stray capacitance near
pin 2 or the crystal, can affect the frequency. The can of
the crystal should not be grounded. The ground side
of the crystal or the C of the R-C oscillator should be connected as directly as possible to pin 8.
Unused inputs should be connected to VCC or ground.
Memory Ready, DMA/Refresh Request and Power-On
Reset should be connected to VCC when not used.
The External Input should be connected to ground
when not used.

f----f-----

V
~0.2

V

V

-10

20

10

70

30
40
50
60
TA. TEMPERATURE (1:)

80

90

FIGURE 11 - TYPICAL FREQUENCY versus
RESISTANCE FOR C VARIABLE
200

100
80

w
u

60

U

40

z
<
.....

:

'"

,

'
"
"'

~ .....
I'..

""-

.......

1"'-..'" r--..... .......
~'" t'-..'
.....

~

.....

u'

~"

'" ~
.....

""- .......

I I I I I

I

" "'-

"",,-"~ '\.

."'-"

"-

~

"~ ~"

~" "-"

I' "
5k
Ri

HI

10

r------.----.-------

3k

T

MC6875

'Vc~ = 5.'0 v'-

(2)

TA = 25°C -

[\

(3)

\

1\

~

2k

lk

7

1

Ext In

I\.

"-,

X1

I

1,\ f\

'" ""

20

(1)

-

I

'"

...........

FIGURE 12 - OSCILLATOR-CRYSTAL OPERATION

NOTE: RC Operation not recommended above
4, to = 2.0 MHz
1

OSCILLATOR
A tank circuit tuned to the desired crystal frequency
connected between terminals X 1 and X2 as shown in
Figure 12, is recommended to prevent the oscillator from
starting at other than the desired frequency. The 1 kn
resistor reduces the Q sufficiently to maintain stable
crystal control. Crystal manufacturers may recommend a
capacitance (ell to be used in series with the crystal for
optimum performance at series resonance.
See Figures 9 and 10 for typical oscillator temperature
and VCC supply dependence for R - C operation.

_

\

-

or,-

8 9 10

4 x fo. FREQUENCY (MHz)

3·564

4 X fo

= Crystal

frequency

4 X fo =1 _ _
1 __

21TJLTCT

• Required by some
Crystal manufacturers

2.5 /lH .;;; LT';;; 22 /lH
75 pF .;;; CT " 200 pF

RT

= 1kil

MC6875, MC6875A

TABLE 1 - OSCILLATOR COMPONENTS

TANK CIRCUIT
PARAMETERS

APPROXIMATE
CRYSTAL PARAMETERS

CTS KNIGHTS
400 REIMANN AVE.
SANDWICH.IL
60548
(8151786-8411

McCOY ELECT. CO.
WATTS & CHESTNUTS STS.
MT. HOLLY SPRING. PA
17065
(7171486-3411

"H

CT
pF

RS
Ohms

Co
pF

C1
mpF

fo
MHz

10

150

15-75

3-6

12

4.0

MP..()4A
·390 pF

113-31

4.7

82

8-45

4-7

23

8.0

MP'()80
·47 pF

113-32

LT

Inductors may be obtained from: Coilereft, Cery, IL 60013

FIGURE

13

RC OPERATION
(1) r - - - - - - ,
r------j X 1

EXTERNAL INPUT

R

(1)

(2)

X2
MC6875

X1
Open
(2)
X2

(3)

Ext In

MC6875
(3)

Ext In
51
External Pulse
Generator

To precisely time a crystal to desired frequency, a
variable trimmer capacitor in the range of 7 to 40 pF
would typically be used. Note it is not a recommended
practice to tune the crystal with a parallel load capacitance.
The table above shows typical values for CT and LT,
typical crystal characteristics, and manufacturers' part
numbers for 4.0 and 8.0 megahertz operation.
The MC6875 will function as an R-C oscillator when
connected as shown in Figure 13. The desired output
frequency (M¢1) is approximately:
Formula

320

4 x fo "" C (R+ .27) + 23

TyeO CRYSTAL PRODUCTS
3940 W. MONTECITO
PHOENIX. AZ
85019
(6021 272-7945
150-3260
150-3270

(312) 639·2361

a solid VOL output level until VCC has reached 3.5 to
4.0 V. During this time transients may appear on the
clock outputs as the oscillator begins to start. This
happens at approximately VCC = 3 V. At some VCC level
above that, where Reset Output goes low, all the clock
outputs will begin functioning normally. This phenomenon of the start-up sequence should not cause any
problems except possibly in systems with battery back-up
memory. The transients on the clock Iines during the
time the Reset Output is high impedance could initiate
the system in some unknown mode and possibly write
into the backup memory system. Therefore in battery
backup systems, more elaborate reset circuitry will
be required.
Please note that the Power-On Reset input pin of the
MC6875 is not suitable for use with a manual MPU reset
switch if the DMA/Ref Req or Memory Ready inputs are
going to be used. The power on reset circuitry is used to
initialize the internal control logic and whenever the
input is switched low, the MC6875 is irresponsive to
the DMA/Ref Req or Memory Ready inputs. This may
result in the loss of dynamic memory and/or possibly
a byte of slow static memory. The circuit of Figure 14
is recommended for applications which do not utilize the
DMA/Ref Req or Memory Ready inputs. The circuit of
Figure 15 is recommended for those applications that do.
FIGURE 14 - MANUAL RESET FOR APPLICATIONS NOT USING
DMA/REFRESH REQUEST OR MEMORY READY INPUTS

Vcc

C in picofarads
R in K ohms
4 x fo in Megahertz

10

6

Reset

(See Figure 11)
It would be desirable to select a capacitor greater than
15 pF to minimize the effects of stray capacitance. It is
also desirable to keep the resistor in the 1 to 5 k
range. There is a nominal 270 n resistor internally at
X1 which is in series with the external R. By keeping
the external R as large as possible, the effects due to
process variations of the internal resistor on the frequency
will be reduced. There will, however, still be some
variation in frequency in a production lot both from
the resistance variations, external and internal, and
process variations of the input switching thresholds.
Therefore, in a production system, it is recommended
a potentiometer be placed in series with a fixed R
between X 1 and X2.
POWER-ON RESET
As the power to the MC6875 comes up, the Reset
Output will be in a high impedance state and will not give

C

n

12

4\
-=-

~

14

IX)

40

0
0

IX)

<0

<0
U

u

:2

:2

Manual Reset SWitch

FIGURE 15 - MANUAL RESET FOR SYSTEMS USING
DYNAMIC RAM OR SLOW STATIC RAM IN CONJUNCTION
WITH MEMORY READY OR DMA/REFRESH REQUEST INPUTS

Vec
1/474LS08
47 k

.r

~

3-565

Manual Reset
Switch

I

®

MC8T26A
MC6880A

MOTOROLA

QUAD THREE-STATE BUS TRANSCEIVER

I

QUAD THREE-STATE
BUS TRANSCEIVER

This quad three-state bus transceiver features both excellent MOS
or MPU compatibility, due to its high impedance PNP transistor
input, and high-speed operation made possible by the use of Schottky
diode clamping_ Both the -48 mA driver and -20 mA receiver outputs are short-circuit protected and employ three-state enabling inputs_
The device is useful as a bus extender in systems employing the
M6800 family or other comparable MPU devices. The maximum
input current of 200 J.J.A at any of the device input pins assures
proper operation despite the limited dri.ve capability of the MPU
chip. The inputs are also protected with Schottky-barrier diode
clamps to suppress excessive undershoot voltages.
The MC8T26A is identical to the N E8T26A and it opel ates from
a single +5 V supply.
•

High Impedance Inputs

•

Single Power Supply

•

High Speed Schottky Technology

•

Three-State Drivers and Receivers

•

Compatible with M6800 Family Microprocessor

MONOLITHIC SCHOTTKY
INTEGRATED CIRCUITS

LSUFFIX

CERt:~ ::OC~GE

~

ryrrm ~ ~

..

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

MICROPROCESSOR BUS EXTENDER APPLICATION

PIN CONNECTIONS -

GND +5 V,.,

MC8T26A
MC6880A

(Clock)
(>2
Receiver
E:nable

VCC

Input
Receiver
Output

,

Driver
Enable
Input

2

Receiver
Output
4
Bus 4
Driver
Input
4
Receiver
Output

3
Driver
Input

Bus3

7

2
Gnd

ORDERING INFORMATION

Alternate

Temperature
Range

Package

MC6880AL

MC8T26AL

0 to +75°C

Ceramic DIP

MC6880AP

MC8T26AP 0 to +75 C

Device

Plastic DIP

MC8T26A, MC6880A

MAXIMUM RATINGS

(TA = 250 C unless otherwise noted.)
Symbol

Value

Unit

VCC

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Junction Temperature
Ceramic Package
Plastic Package

TJ

Rating
Power Supply Voltage

°c
175
150

Operating Ambient Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS

TA

o to +75

T stg

-65 to+150

°c
vc

(4.75 V.;; VCC';; 5.25 V and OOC ... TA'" 75 0 C unless otherwise noted.)

Characteristic
I nput Current - Low Logic State
(Receiver Enable Input, VIL(RE) = 0.4 V)
(Driver Enable Input, VIL(DE) = 0.4 V)
(Driver I nput, VI U D) = 0.4 V)
(Bus (Received Input, VI UB) = 0.4 V)
Input Disabled Current - Low Logic State
(Driver Input, VIL(D) = 0.4 V)

Symbol

Min

IILlRE)
IIL(DE)
IIUD)
IIUB)

-

Typ

~

Max

Unit

~200

IJA

~200

-

-

-

-

~200

-

-

~200

-

-

~25

/lA

25
25
25

IJA

IIL(D) DIS

Input Current· High Logic State
(Receiver Enable Input, VIH(RE) = 5.25 V)
(Driver Enable Input, VIHIDE).= 5.25 V)
(Driver Input, VIH(D) = 5.25 V)

IIH(RE)
IIH(DE)
IIH(D)
IIH(B)

(Receiver Input, VIH(B) = 5.25 V)
I nput Voltage - Low Logic State
(Receiver Enable Input)
(Driver Enable Input
(Driver Input)

-

-

I nput Voltage - High Logic State
(Receiver Enable Input)
(Driver Enable Input)
(Driver Input)
(Receiver Input)

-

100

-

VILIDE)
VIUD)

-

-

0.85
0.85
0.85

VILlB)

-

-

0.85

-

VIURE)

(Receiver Input)

~

~

V

VIH(RE)
VIH(DE)
VIH(D)

2.0
2.0
2.0

-

VIH(B)

2.0

-

-

0.5
0.5

V

3.1
3.1

-

V

-

-

100
100

IJA

V

-

Output Voltage - Low Logic State
(Bus Driver) Output, 10L(B) = 48 mAl
(Receiver Output, 10L(R) = 20 mAl
Output Voltage - High Logic State
(Bus (Driver) Output, 10H(B) = -~10 mAl
(Receiver Output, 10H(R) = -2.0 mAl
(Receiver Output, IOH(R)

= -100

/lA, VCC

= 5.0

VOUB)
VOLlR)

-

-

-

-

VOH(B)
VOH(R)

2.4

V)

2.4
3.5

-

Output Disabled Leakage Current - High Logic State
(Bus Driver) Output, VOH(B) = 2.4 V)
(Receiver Output, VOH(R) = 2.4 V)
Output Disabled Leakage Current - Low Logic State
(Bus Output, VOL(B) = 0.5 V)
(Receiver Output, VOL(R) = 0.5 V)

IOHL(B)
10HLlR)

-

-

-

-

10LL(B)
10LL(R)

-

-

-100
-100

/lA

-

VIC(DE)
VIC(RE)
VIC(D)

-

-

-1.0
-1.0
-1.0

V

10S(B)
10S(R)

-50
-30

-

-150
-75

mA

-

lee

-

-

87

rnA

Input Clamp Voltage
(Driver Enable Input IIO(DE) = -12 mAl
(Receiver Enable Input IIC(RE) = +12 mAl
(Driver Input IIC(D) = ·-12 mAl
Output Short-Circuit Current, Vee = 5.25 V III
(Bus (Driver) Output)
(Receiver Output)
Power Supply Current
(Vee = 5.25 V)
(1) Only one output may be short-circuited at a time.

3·567

-

I

MC8T26A, MC6880A

SWITCHING CHARACTERISTICS (Unless otherwise noted, specifications apply at T A

I

=

250 C and VCC

=

5.0 V)

Symbol

Figure

Min

Max

Unit

Propagation Delay Time from Receiver (Bus) Input to
High Logic State Receiver Output

tPLH(R)

1

-

14

ns

Propagation Delay Time from Receiver (Bus) I nput to
Low Logic State Receiver Output

tPHL(R)

1

-

14

ns

Propagation Delay Time from Driver "Input to
High Logic State Driver (Bus) Output

tpLH(D)

2

-

14

ns

Propagation Delay Time from Driver I nput to
Low Logic State Driver (Bus) Output

tPHL(D)

2

-

14

ns

Propagation Delay Time from Receiver Enable I nput to
High Impedance (Open) Logic State Receiver Output

tPLZ(RE)

3

-

15

ns

Propagation Delay Time from Receiver Enable Input to
Low Logic Level Receiver Output

tpZL(RE)

3

-

20

ns

Propagation Delay Time from Driver Enable I nput to
High Impedance Logic State Driver (Bus) Output

tPLZ(DE)

4

-

20

ns

Propagation Delay Time from Driver Enable Input to
Low Logic State Driver (Bus) Output

tPZL(DE)

4

-

25

ns

Characteri stic

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM
BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tpLH(R) AND tPHL(R)

tTHL" 5.0 ns

Input

OV

Input Pulse Frequency = 10 MHz
Duty Cycle = 50%

VOH------,
OUtput
VOL----~-----~----------------J

To Scope
(Input)

2.6 V

To Scope
( Input)

Receiver

En;bi';
Input

92
Receiver

1N916

Output

or Equiv.

Driver
Input
Pulse
Generator

51

1.3 k
Driver
Enable
Input

3-568

30 pF

MC8T26A, MC6880A
FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVERI OUTPUT, tpLH(DI AND tPHL(DI

tTHL C; 5.0 ns

2.6V----Input

OV---";;"";..:7l

Input Pulse Frequency = 10 MHz
Duty' Cycle = 50%

tpHL(D)

vOH-----Output
VOL--------~-------J

2.6 V

2.6 V

To Scope
(Input)

To Scope
(Output)

Driver
Enable
Input

r

Driver
Driver
Input

(Bus)

I

30
lN916
or EQuiv.

Output

Receiver
Output
51

300 pF

260

~

EniibiS
Input

FIGURE 3:- TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT, tPLZ(REI AND tpZL(REI

tTHL" 5.0 ns

tTLH .. 5.0 ns

2.6 V ----+-~-------"L
Input

OV
"'3.5 V

1.5 V

Output
VOL----...I.

To Scope
(Input)

r

tPZL(RE)

-----+---:_-----~.

2.6 V
To Scope
(Output)

Receiver 'Enable
Input

Input Pulse Frequency ~ 5.0 MHz
Duty Cycle = 50%

.

5.0 V

2.4 k

Receiver
Output

Pulse
Generator

240

51

lN916
5.0 k

3-569

30 pF

or EQuiv.

MC8T26A, MC6880A

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER (BUS) OUTPUT, tPLZ(DE) AND tpZL(DE)

tTHL';;;5.0ns

2.6 V ----+----~-------"L
Input

<::'Z~IDEI ---1.1-Output

Input Pulse Frequency = 5.0 MHz
Duty Cycle = 50%

\1.5V

VOL------L--------J

I

+2.6 V
To Scope
(Output)

Driver Enable
Input

5.0 V

70

2.4 k

Driver
Input

Driver (Busl
Pulse

51

Generator

Output

Receiver
Output

1N916
5.0 k

Receiver
Enable
Input

300 pF

0;'"

Equiv.

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs

Receiver
Outputs

Driver
Inputs

Driver
Inputs

Receiver
Enable

To Other
Drivers/ Receivers

Driver
Enable

3-570

Receiver
Enable

®

MC3482A1MC6882A
MC3482BIMC6882B

MOTOROLA

OCTAL THREE-STATE BUFFER/LATCH
This series of devices combines four features usually found

OCTAL THREE-STATE
BUFFER/LATCH

desirable in bus-oriented systems: 1) High impedance logic inputs
insure
that
these devices do not seriously
load the
bus; 2) Three-state logic configuration allows buffers not being
utilized to be effectively removed from the bus; 3) Schottky
technology allows for high-speed operation; 4) 48 mA drive
capability.
•

Inverting and Non-Inverting Options of Data

•

SN74S373 Function Pinouts

•

Eight Transparent Latches/Buffers in a Single Package

•

Full Parallel-Access for Loading and Reloading

•

Buffered Control Inputs

•

All Inputs Have Hysteresis to Improve Noise Rejection

L SUFFIX
CASE 732-03

•

High Speed - 8.0 ns (Typ)

•

Three-State Logic Configuration

•

Single +5 V Power Supply Requirement

•

Compatible with 74S Logic or M6800 Microprocessor Systems

•

High Impedance PNP Inputs Assure Minimal Loading of the Bus

MICROPROCESSOR BUS EXTENDER

INPUT EQUIVALENT
CIRCUIT

~PPLICATION

(Clock)

Gnd +5 V <1>1

<1>2

OUTPUT EQUIVALENT
CIRCUIT

Vee

ORDERING INFORMATION
(Temperature Range for the following
devices ~ 0 to + 75 0 C.1

Package
Ceramic DIP
Ceramic DIP

3-571

II

MC6882A, MC6882B, MC3482A, MC3482B

MAXIMUM RATINGS

(T A = 25°C unless otherwise noted)

Reting
Power Supply Voltage
Input Voltage
Operating Ambient Temperature Range
Storage Temperature Range
Operating Junction Temperature

Symbol

Velue

Unit

VCC
VI
TA
T stg

8.0
5.5
to +75
-65 to +150

Vdc
Vdc
uc

o

175

Ceramic Package

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, OOC ~T A ~ 75°C and 4.75 V ~ VCC ~ 5.25 V)

Chareet... istic

I

°c
°c

TJ

Symbol

Min

Typ

Max

Unit

Input Voltage - High Logic State
(VCC = 4.75 V, T A = 25°C)

VIH

2.0

-

-

V

Input Voltage - Low Logic State
(Vec = 4.75 V, TA = 25°C)

VIL

-

-

0.8

V

Input Current - High Logic State
(VCC = 5.25 V, VIH = 2.4 V)

IIH

-

-

40

!J.A

Input Current - Low Logic State
(VCC = 5.25 V, VIL = 0.5 V, VIL(OE) = 0.5 V)

IlL

-

-

-250

!J.A

Output Voltage - High Logic State
(VCC = 4.75 V,IOH = -20 mAl

VOH

2.4

-

-

V

Output Voltage - Low Logic State
(lOL =48mA)

VOL

-

-

0.5

V

Output Current - High Impedance State
(VCC = 5.25 V, VOH = 2.4 V)
(VCC = 5.25 V, VOL = 0.5 V)

102

-

-

Output Short·Circuit Current
(VCC = 5.25 V, Vo = 0) (only one output can be shorted at a time)
Power Supply Current
(VCC = 5.25 V)

MC3482A/MC6882A
MC3482B/MC6882B

Input Clamp Voltage
(VCC = 4.75 V,IIK = -12 mAl

3-572

!J.A

-

-

100
-100

lOS

-30

-80

-130

mA

ICC

-

130
150

mA

V IK

-

-1.2

V

-

MC6882A, MC6882B, MC3482A, MC3482B

SWITCHING CHARACTERISTICS (V CC ~ 5.0 V, O°C,,;; T A";; +75°C, unless otherwise noted, typical
Characteristics

MC3482A1
MC6882A

Symbol
Min

Propagation Delay Times
Data to Output
Low to High
CL = 50 pF
CL ~ 250 pF
CL ~ 375 pF
CL=500pF
High to Low
CL = 50 pF
CL = 250 pF
CL=375pF
CL = 500 pF
Propagation Delay Times
Latch Disable (Low to High)
to Output
Low to High
CL = 50 pF
High to Low
CL=50pF
Propagation Delay Times
(CL = 20 pF)
High Output Level to High Impedance
Low Output to High Impedance
High Impedance to High Output
High Impedance to Low Output

Typ

Max

Min

Unit

Typ

Max
ns

tPLH(D)
4.0
-

10

9.0
12
14
16

16
20
22
24

4.0

8.0
15
18
21

16
22
25
28

4.0

-

10

9.0
12
14
16

16
20

8.0
15

16
22
24
27

22
24

tPHL(D)
4.0
-

16

-

17
18

14

II

ns

tPLH(L)

-

22

30

-

18

30

-

23

30

-

14

25

-

8.0
20
9.0
13

15
27
16
20

-

6.0
15
11
9.0

13
23
18
16

tpHL(L)
ns
tpHZ(OE)
tPLZ(QE)
tpZH(OE)
tPZL(QE)

-

-

AC SETUP CHARACTERISTICS (V CC = 5.0 V, O°c ,,;; T A";; +75°C, unless otherwise noted, typical
Characteristic

T A ~ 25°C.)

@

MC3482BI
MC6882B

@

Symbol

T A = 25°C.)

MC3482BI
MC6882B

MC3482A1
MC6882A

Unit

Min

Typ

Max

Min

Typ

Max

Setup Time
(Data to Negative Going Latch Enable)

tsu(D)

10

0

-

7.0

0

-

ns

Hold Time
(Data to Negative Going Latch Enable)

th(D)

10

-

-

8.0

-

-

ns

Minimum Latch Enable Pulse Width
(High or Low)

tWILl

-

15

-

-

15

-

ns

3·573

MC6882A, MC68828, MC3482A, MC34828

PIN CONNECTIONS AND TRUTH TABLES

MC3482B/MC6882B

MC3482A/MC6882A

Output
Enable

Vee

1

Out 8

In 8

I

In 7

Out 5

Output
Enable

Latch

Input

Output

Output
Enable

Latch

Input

Output

0

1

0

1

0

1

0

0

0

1

1

0

0

1

1

1

0

0

X

0

0

X

1

X

X

°0

1

X

X

°0

Z

3·574

Z

MC6882A, MC6882B, MC3482A, MC3482B

FIGURE 2 - WAVEFORMS FOR PROPAGATION OELAY
TIMES DATA TO OUTPUT

FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS

,..----"""'------ 3 V

To Scope
Output

To Scope (Input)

Closed for
tPLZ(OE), tPZL(OE) only

Input or

Enable

+5 V

1 k

..n..

Pulse
Generator

1 N3064
or Equivalent

50

Output

MC3482A/MC6882A

Output

1.0 k
CL Includes Probe and
Jig Capacitance

1

MC3482B/MC6882B _ _ _..J
Closed for
tPHZ(OE),tPZH(OE) only

FIGURE 3 - WAVE FORMS FOR AC SETUP AND
LATCH DISABLE TO OUTPUT DELAY

Latch

Input
(Data) "::"';'''::''';:'':::''':'''T'-;,.;::.::o.:r

Output

FIGURE 4 - WAVEFORMS FOR PROPAGATION DELAY
TIMES - OUTPUT ENABLE TO OUTPUT

3·575

Input Pulse Conditions

tTHL
tTLH<5ns
f
1.0 MHI

I

®

SN74LS783
MC6883

MOTOROLA
Advance InforIDation

SYNCHRONOUS
ADDRESS
MUL TIPLEXER

SYNCHRONOUS ADDRESS MULTIPLEXER
The SN74LS783/MC6883 brings together the MC6809E
(MPU), the MC6847 (Color Video Display Generator) and dynamic RAM to form a highly effective, compact and cost effective computer and display system.

LOW POWER SCHOTTKY

• MC6809E, MC6800, MC6801E, MC68000 and MC6847 (VDG)
Compatible
• Transparent MPUIVDG/Refresh

II

• RAM size Static)

4K, 8K, 16K, 32K or 64K Bytes (Dynamic or

• Addressing Range -

96K Bytes

N SUFFIX
PLASTIC PACKAGE
CASE 711

• Single Crystal Provides All Timing
• Register Programmable:
VDG Addressing Modes
VDG Offset (0 to 64K)
RAM Size
Page Switch
MPU Rate (Crystal .;- 16 or .;- 8)
MPU Rate (Address Dependent or Independent)

J SUFFIX
CERAMIC PACKAGE
CASE 734

• System "Device Selects" Decoded 'On Chip'
• Timing is Optimized for Standard Dynamic RAMs

• + 5.0 V Only Operation
• Easy Synchronization of Multiple SAM Systems

PIN ASSIGNMENT

• DMA Mode

40

SYSTEM BLOCK DIAGRAM

39
38

TV Display Section
is Optional

Address

AO-A15

36

6

35 (RAS1)

7

34

8

33

9

32
31

11

30

Ef..-----4

12

29

Qf..-----4

13

28

14

27

15

26

16

25

MC6809E
MPU

Data

37

5

10

R wl------I~

To
ROMs
and
10

SN74LS783
MC6883
SAM

4

DYNAMIC
RAM
4K. 8K, 16K
32K or 64K
BYTES

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-576

17

24

18

23

19

22

20

21

SN74LS783, MC6883
MAXIMUM RATINGS (TA

= 25°C unless otherwise noted.)

Symbol

Value

Unit

VCC

-0.5 to + 7.0

Vdc

Input Voltage (Except OSCln)

VI

-0.5 to 10

Vdc

Input Current (Except OSCln)

II

-30 to + 5.0

mA

Vo

-0.5to +7.0

Vdc

Rating
Power Supply Voltage

Output Voltage
Operating Ambient Temperature Range

o to

TA

+70

°c

TstQ

-65 to + 150

°c

Input Voltage OSCln

VIOSCln

-0.5 to VCC

Vdc

Input Current OSCln

II0sCIn

-0.5 to +5.0

rnA

Storage Temperature Range

GUARANTEED OPERATING RANGES
Symbol

Min

Typ

Max

Supply Voltage

Parameter

VCC

4.75

5.0

5.25

V

Operating Ambient Temperature Range

TA

0

25

75

°c

Output Current High
RASO, RAS1, CAS, WE
All Other Outputs

10H

-

-

-1.0

Output Current Low
MSO, RAS1, CAS, WE
VClk
All Other Outputs

10L

-

Unit

rnA
-0.2
rnA

-

8.0

-

4.0

0.8

DC CHARACTERISTICS (Unless otherwise noted specifications apply over recommended power supply and
temperature ranges)
Characteristic

Symbol

Min

Typ

Input Voltage -

High Logic State

VIH

2.0

-

Input Voltage -

Low Logic State

VIL

-

-

0.8

V

Input Clamp Voltage
(VCC = Min, lin = -18 rnA) All Inputs Except OSCln

VIK

-

-

-1.5

V

Input Current - High Logic State at Max Input Voltage
(VCC = Max, Vin = 5.25 V) VClk Input
(VCC = Max, Vin = 5.25 V) DAO Input
(VCC = Max, Vin = 5.25 V OSCln = Gnd) OSCOut Input
(VCC = Max, Vin = 7.0 V) All Other Inputs Except OScin

II

-

-

-

200
100
250
100

-

-

20

-

-1.2
-60
-8
-.4

Input Current High Logic State
(VCC = Max, Vin = 2.7 V)
Input Current (VCC = Max,
(VCC = Max,
(VCC = Max,
(VCC = Max,

All Inputs Except VClk,
DAO OSCln' OSCOut

IIH

Low Logic State
Vin = 0.4 V) DAO Input
Vin = 0.4 V) VClk Input
Vin = 0.4 V, OSCln = Gnd) OSCOut Input
Vin = 0.4 V) All Other Inputs Except OSCln

IlL

-

-30

-

-

Max

Units
V

JLA

JLA
rnA

Output Voltage - High Logic Sta~ _ _
(VCC = Min,lOH = -1.0 rnA) RASO, RAS1, CAS, WE
(VCC = Min, 10H = - 0.2 rnA) E,
(VCC = Min, 10H = - 0.2 rnA) All Other Outputs

VOH(C)
VOH(E)
VOH

3.0
VCC - 0.75
2.7

-

Output Voltage - Low Logic State_
(VCC = Min, 10L = 8.0 rnA) RASO, RAS1, CAS, WE
Outputs
(VCC = Min, 10L = 4.0 rnA) E,
(VCC = Min, 10L = 0.8 rnA) VClk Output
(VCC = Min, 10L = 4.0 rnA) All Other Outputs

VOL(C)
VOLlE)
VOL(V)
VOL

-

-

-

-

0.5
0.5
0.6
0.5

Power Supply Current

ICC

-

180

230

rnA

Output Short-Circuit Current

lOS

30

-

225

rnA

a

a

V

-

V

3-577

I

SN74LS783, MC6883
AC CHARACTERISTICS (4.75 V""VCC""5.25 V and 0""TA""70°C, unless otherwise noted).
Characteristic

Symbol

Propagation Delay Times
(See Circuit in Figure 9) Oscillator-In "'- to Oscillator-Oulf td(OL-OH)
Oscillator-In f
to Oscillator-Out4,... td(OH-OL)
(CL = 195 pF) AO thru A15 to ZO, Z1, Z2 thru Z7
(CL = 30 pF) AO thru A15, R/W to SO, 51, 53

I

Typ

Min

Max

Units
ns

-

-

3.0
20

-

28
18

-

td(A-Z)
td(A-S)

-

(CL = 95 pF) Oscillator-Out "'-- to RASO f
(CL = 95 pF) Oscillator-Out "'- to RASO "'--

td(OL-ROH)
td(OL-ROL)

-

20
18

-

(CL = 95 pF) Oscillator-Out "'--to RAS1 f
(CL = 95 pF) Oscillator-Out "'-to RAS1 "'--

td(OL-R1H)
td(OL-R1L)

-

22
20

-

(CL = 195 pF) Oscillator-Out "'-- to CAS f
(CL = 195 pF) Oscillator-Out "'- to CAS "'--

td (OL-CH)
td(OL-CL)

-

-

-

20
20

(CL = 195 pF) Oscillator-Out "'-- to WE f
(CL = 195 pF) Oscillator-Out "'-to WE "'--

td(OL-WH)
td(OL-WL)

-

22
40

-

(CL = 100 pF) Oscillator-Out "'-- to E f
(CL = 100 pF) Oscillator-Out "'- to E "'-

td(OL-EH)
td(OL-EL)

55
25

-

(CL = 100 pF) Oscillator-Out"'-- to O f
(CL = 100 pF) Oscillator-Out "'- to 0 " -

td(OL-OH)
td(OL-OL)

-

55
25

-

td(OH-VH)
td(OH-VL)

-

50
65

(CL = 195 pF) Oscillator-Out "'-- to Row Address
(CL = 195 pF) Oscillator-Out "'- to Column Address

td(OL-AR)
td(OL-AC)

-

36
33

-

(CL = 15 pF) Oscillator-Out "'- to DAO f
(CL = 15 pF) Oscillator-Ou.t "'-- to DAO f

td(OL-DH)
td(OL-DH)

-

-15
+15

-

(CL = 95 pF on RAS, CL = 195 pF on CAS) CAS "'- to RASf td(CL-RH)

-

208

-

28
28

-

ns

30
30

-

ns

2.0

5.0

6.0

(CL = 30 pF) Oscillator-Out f
(CL = 30 pF) Oscillator-Out f

to VClk f
to VClk "'--

Earliest! 1)
Latest!1)

Setup Time for AO thru A15, R/W
Hold Time for AO thru A15, R/W

Rate = +16
Rate = + 8

tsu(A)

Rate = +16
Rate = + 8

th(A)

Width of HS Low 2

-

-

twL(HS)

-

-

-

-

-

fLs

Notes: 1. When using the SAM with an MC6847, the rising edge of DAO is confined within the range shown in the timing diagrams (unless the
synchronizing process is incomplete.) The synchronization process requires a maximum of 32 cycles of OSCOut for completion.
2. tWL(HS) wider than 6.0 ~s may yield more than 8 sequential refresh addresses.

FIGURE 1 -

PROPAGATION DELAY TIMES
VERSUS LOAD CAPACITANCE

40

~ 30

td (OL-R1L)

~

~

;:::
>- 20

~
0

z
0
;:::

«
<.::>
;t

-

~~ p-r
td (OL-ROL)
~
10

... td (OL-CLI

~
50

100

200

300

CL, LOAD CAPACITANCE (pFI

3-578

400

500

SN74LS783, MC6883
PIN DESCRIPTION TABLE

Gi
~

0

a..

]c
0

<.J
"C

c

III

::
III

c

.t;

ii:

"C
c:(

:::I

:::l

II)

..
Q.

-=

a..
:::!:

(!J"§
c ..
> ~

Name

No.

VCC
Gnd

40
20

Apply + 5 volts ± 5%. SAM draws less than 230 mAo
Return Ground for + 5 volts.

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AO

36
37
38
39
1
2
3
4
24
23
22
21
19
18
17
16

Most Significant Bit.

R/W

15

MPU READ or WRITE. This signal comes directly from the MPU and is used to enable writing
to the SAM control register, dynamic RAM (via WE)' and to enable device select #0.

III

II)

>

III

Apply 14.31818* MHz crystal and 2.5-30 pF trimmer to ground. See page 12.

DAO

8

HS

9

VClk

7

Display Address DAO. The primary function of this pin is to input the least significant bit of a
16-bit video display address. The more significant 15-bits are outputs from an internal 15-bit
counter which is clocked by DAO. The secondary function of this pin is to indirectly input the
logic level of the VDG "FS" (field synchronization pulse) for vertical video address updating.
Horizontal Synchronization. The primary function of this pin is to detect the falling edge of
VDG "HS" pulse in order to initiate eight dynamic RAM refresh cycles. The secondary function
is to reset up to 4 least significant bits of the internal video address counter.
VDG Clock. The primary function of this pin is to output a 3.579545 MHz square wave** to the
VDG "Clk" pin. The secondary function resets the SAM when this VClk pin is pulled to logic
"0" level, acti ng as an input.

6

S2
S1

25
26

SO

27

E

14

~~

II)

:::l..ll:

a..

II)

c

<.J

..
:::I

S:::I
0

II)

:::!: ~

c:( ...

a:::g

c:(

:::!:"§

c:(c

a:

0

<.J

Apply 1.5 kfl resistor to 14.31818* MHz crystal and 33 pF capacitor to ground. See page 12.
Most Significant Bit (Device Select Bits). The binary value of S2, S1, SO selects one of eight
"chunks" of MPU address space (numbers 0 through 7). Varying in length, these "chunks"
provide efficient memory mapping for ROMs, RAMs, Input/Output devices, and MPU Vectors.
(Requires 74LS 138-type demultiplexer).
Least Significant Bit.

Q

13

E (Enable Clock) "E" and "Q" are 90° out of phase and are both used as MPU clocks for the
MC6809E. For the MC6800 and MC6801 E, only "E" is used. "E" is also used for many MC6800
peripheral chips.
Q (Quadrature Clock).

Z7t
Z6t
Z5t
Z4t
Z3t
Z2t
Z1t
Zot

35
34
33
32
31
30
29
28

Most Significant Bit
First, the least significant address bits from the MPU or "VDG" are presented to ZO-Z5 (4K
x 1 RAMs) or ZO-Z6 (16K x 1 RAMs) or ZO-Z7 (64K x 1 RAMs). Next, the most significant
address bits from the MPU or "VDG" are presented to ZO -Z5 (4K x 1 RAMs) or ZO -Z6
(16K x 1 RAMs) or ZO -Z7 (64K x 1 RAMs). Note that for 4K x 1 and 16K x 1 RAMs, Z7 (Pin
35) is not needed for address information. Therefore, Pin 35 is used for a second row
address select which is labeled (RAS1).
Least Significant Bit.
Row Address Strobe One. This pulse strobes the least significant 6,7 or 8 address bits into
dynamic RAMs in Bank #1.
Row Address Strobe Zero. This pulse strobes the least significant 6,7 or 8 address bits into
dynamic RAMs in Bank #0.
Column Address Strobe. This pulse strobes the most significant 6,7 or 8 address bits into
dynamic RAMs.
Write Enable. When low, this pulse enables the MPU to write into dynamic RAM.

U

:::!:~

ii:

Least Significant Bit.

5

OS C Out
.~ 't)

MPU address bits AO-A15. These 16 signals come directly from the MPU and are used to
directly address up to 64K memory locations or to indirectly address up to 96K memory
locations. (See pages 17 and 18 for memory maps). Each input is approximately equivalent
to one low power Schottky load.

OS C ln

<.J

I--

Function

RAS1t

35

RASOt

12

CASt

11

WEt

10

*14.31818 MHz is 4 times 3.579545 MHz television color subcarrier. Other frequencies may be used. (See page 12.)
**When VDG and SAM are not yet synchronized the "square wave" will stretch (see page 10.)
t Due to fast transitions, ferrite beads in series with these outputs may be necessary to avoid high frequency (~ 60 MHz) resonances.

3-579

I

..
en
z

......
ren
......

•

FIGURE 2 -

TIMING WAVEFORMS for MPU RATE = SLOW

C»

~
i ...

ONE MACHINE CYCLE

., ,

3:

oen
OSCln

~

CHANGE FROM H TO l

Will CHANGE FROM H TO l

~

CHANGE FROM L TO H

Will CHANGE FROM L TO H

~

ANY CHANGE PERMITTED

C»
C»

(,.)

OSCQUI

Reference POtnlS tn Ttme_1

tdIOL.EU-+II~

..... j.... 'dlOl.EHI

1

.

~

~

M'''.'''~

1

I

I I.....

VOHIE)

~ll"--ld(Ol.QHI

I

I

j

I·

.....

VaHlE I

....

I'~I~~,~~~~~#VIL/

l..... td{OH.Vl!
VALID VOG ADDRESS {COLUMN}

In'

'dIOLARI_I;O~1:-~0~1

VOL

vL

MPU AOORl

'dleL.RH)

WE··

I I:~l

\Vll

VOlIC)

::~o~,Acl_I;~1-

VOH

VALID MPliAOORESS (COLUMN)

'V'

~.-~,
",-,
I

---+-II-+- 'dIOL·Rll!

~ ~td(Ol.CHI I'

VOlle)

------I f-4---'dtOl.WLl

VaHle)

-~s

VOL

-is

--:J~Lt(~~l.ROll

IdIOl.ROH1-"ISOHICI

..

--I

VOL

~I r:- _~~:~~~lHI

RiSi .•
RAS1i
~

I -L~;';'·· 0 H

t

'"' ' '-1:t~':·

VOllV)

~1;O~I4-ldlOl.ACI

_.

.-if

./~::::::
Id""'"1
1 1 1 1 1

I I

VOH

_

VOUEI

VOltE)

!dIOH·VHI.....

~

M.~i

/-+--- 'd(Ql·QU

--4S
1r.-ldIOL.ell

.-s~

VOllel

Vouel

'dlOl·WHI-.. ,.......
~--4~

OHIC

'Timing points marked with "." are defined elsewhere (specifically. 8 cycles of "OSCOut" to the left or right.1
Note 1: The period of "VClk" is four times that of "OSCOut" unless the synchronization process is incomplete. Also.
VClk may rise within td(OH.VHI nanoseconds of TO. Tl, T2 ... or TF.

en

:z

~.

~

r-

FIGURE 3- TIMING WAVEFORMS for MPU RATE

en
--...

= FAST

CD
..W
,4

ONE MACHINE CYCLE

3:

.. ,

oen
~

CHANGE FROM H TO l

WILL CHANGE FROM H TO l

~

CHANGE FROM L TO H

Will CHANGE FROM l TO H

CD
CD
W

OSCln,

'-oooofS

OSCOut,

ReferencePOII'lSlnTlme~1

I

U)

~

...

" I

..j~Ol.qHI

-I r'd(OloQlI
~.

VOH(EI

-r-:'~I"r--'-H,"IA81

VOUEI

VIHJ"_

VI~

VOLlE I

I' -

t--'d(A.SI

I

1·...,5

")t,."

-~s

_I

1_.

_

VI><=bf':lhIA81
Vil - ";:1~.J~
'--ldIA_51

l-... I

AO·A15. RVi - .l--

1 ""

-

1

_

I

I

I

I

1

_-If

--41

J-4I

- J

_-jf

~~~~~~~ld~IO~HV~HI==F=3=~~~~~~~~~=F====f=====t===~~~~~i:~~~~~~~::::1:::::[:]

.

vo/

VOH

VOH

~

~td(OH.Vll

VOH~/OH

VALI"'"O=MP~U=AO=OR='5""5""'IR=OW"'"1~No=-"""'I---'\I

VOL'

'",",/

VOL

I'VOL

RAS1--E-----:-"'--------------------:--J~~

--1t:.ldIOL'RiHI
--rVOH(CI

14K' 16K mOde".

-

VOLICI

•

VOH

'd(Ql·AC I

VOH>gvc~H

"",-ffi--

--If
- -11

VOUVI

IdlOLROHI
VOLICI/-f'VOHICI
" ' ' ' " " , ".../_

VOl!

1

1

-.::1. VOI~~L'RIlI

~t:.ldIOLCHI
-IOO"'"

vouz,"

ldiOl-ROU

I

~:~S

- -11

['VOL

VOl

1

1....,----

I

-.::jt-ldIOL.CLI
-J VOLICI

-.J;::'~W<' '

-

'Timing poinls marked wilh ..... are defined elsewhere (specifically, B cycles of "OscOUI" 10 Ihe lefl or Ihe righl.)
NOles 1: In Ihe "fasl MPU rale" mode, the time sial olherwise used for a VDG address is used for a second MPU address_
2: The period of "VClk-' is four times thaI of "OscOUI" unless Ihe synchronizalion process is incomplete.
Also, VClk may rise within Id(OH-VH) nanoseconds of TO, Tl, T2, . _ . or TF.

III

.....

~dIOL'WHI

~OO"'"

~I

--41
--;1--11

SN74LS783, MC6883

FIGURE 4 - SAM BLOCK DIAGRAM
S2

Sl

SO

VCC

Gnd

$ FFCO - $ FFDF
Refresh
Grant

A

Refresh Counter

TY

Refresh
Clock
Logic

12

A15

I

HS
Control Register
Write Strobe

B15

F6

A14

A14

B14

F5

A13

A13

B13

F4

A12

A12

B12

F3

A11

Al1

B11

F2

A10

A10

A9

A9

A8

A8

A7

A7

B7

AS

A6

86

V2

A5

A5

85

Vl

A4

A4

84

VO

A3

A3

B3

DAO

F1

FO

B9

Address
Multiplexer
(See page 9 for signal
routing and timing)

B8

VClk

M1
Ml

A2

A2

B2

Al

A1

B1

AO

AO
Z7

MO

80
Z6

Z5

Z4

Z3

Z2

Z1

RiW
E

Os c ln

Q

OS C Out

"Reset
Destinations:
RAS1/Z7

Z6

Z5

Z4

Z3

Z2

Z1

ZO

Dots indicate which internal signals reset logic blocks

3-582

SN74LS783, MC6883

SAM BLOCK DIAGRAM DESCRIPTION
MPU Addresses (AO - A 15):
These 16 signals come directly from the MPU and are used to directly address up to 64K memory locations
(K= 1024) or to indirectly address up to 96K memory locations, by using a paging bit "P" (see pages 17 and
18 for memory maps.) Each input is approximately equivalent to one low power Schottky load.

VDG Address Counter (80 - 815):
These 16 signals are derived from one input (DAO) which is the least significant bit of the VDG address. Most
of the counter is simply binary. However, to duplicate the various addressing modes of the MC6847 VDG,
ADDRESS MODIFIER logic is used. Selected by three VDG mode bits (V2, V1, and YO) from the SAM CONTROL
REGISTER, eight address modifications are obtained as shown in Figure 5.
Also, notice that bits 89-815 may be loaded from bits FO-F6 from the CONTROL REGISTER. This allows the
starting address of the VDG display to be offset (in V2K increments) from $0000 to $FFFFt. 89-815 are loaded
when a VERTICAL PRE-LOAD(VP) pulse is generated. VP goes active (high) when HS from the VDG rises if DAO
is high (or a high impedance.) This condition should occur only' while the TV electron beam is in vertical
blanking and is simply implemented by connecting FS and MS together on the MC6847. The VP pulse also
clears bits 81 - 88.
Finally, a HORIZONTAL RESET (HR) pulse may also affect the counter by clearing bits 81 - 83 or 81 - 84
when HS from the VDG is LOW (see Figure 5.) The HR pulse should occur only while the TV electron beam is
in horizontal blanking.
In summary, DAO clocks the VDG ADDRESS COUNTER; HR initializes the horizontal portion and VP initializes
the vertical portion of the VDG ADDRESS COUNTER.

REFresh Address Counter (CO - C6):
A seven bit binary counter with outputs labeled CO - C6 supplies bursts of eight* sequential addresses
triggered by a HS high to low transition. Thus, while the TV electron beam is in horizontal blanking, eight
sequential addresses are accessed. Likewise, the next eight addresses are accessed during the next horizontal
blanking period, etc. In this manner, all 128 addresses are refreshed in less than 1.1 milliseconds.

Address Multiplexer:
Occupying a large portion of the block diagram in Figure 4, is the address multiplexer which outputs bits
ZO-Z7 (as addresses to dynam'ic RAM's.) Inputs to the address multiplexer include the VDG address (80 - 815)
the REFresh address (CO- C6) and the MPU address (AO - A15) or (AO - A14 p~us one paging bit "P".) The paging
bit "P" is one bit in the SAM CONTROL REGISTER that is used in place of A 15 when memory map TYpe #0 is
selected (via the SAM CONTROL REGISTER "TY" bit.)
Figure 6 shows which inputs are routed to ZO - Z7 and when the routing occurs relative to one SAM machine
cycle. Notice that Z7 and RASr share the same pin. Z7 is selected if "Ml" in the SAM CONTROL REGISTER IS
HIGH (Memory size = 64K.)

Address Decode:
At the top left of Figure 4, is the Address Decode block. Outputs 52, 51, and SO form a three bit encoded
binary word(S). Thus 5 may be one of eight values (0 through 7) with each value representing a different range
of MPU addresses. (To enable peripheral ROM's or 1/0, decode the 52, 51, and SO bits into eight seperate
signals by using a 74LS138, 74LS155 or 74LS156. Notice that 52, 51, and SO are not gated with any timing
signals such as E or 0.)
Along with the A5 - A15 inputs is the MEMORY MAP TYpe bit (TY.) This bit is soft-programmable (as are all
16 bits in the SAM CONTROL REGISTER,) and selects one of two memory maps. Memory map #0 is intended
to be used in systems that are primarily ROM based. Whereas, memory map #1 is intended for a primarily
RAM based system with 64K contiguous RAM locations (minus 256 locations.) The various meanings of 52,51,
SO are tabulated in Figure 16 (page 19) and again on pages 17 and 18.
In addition to 52, 51, and SO outputs is a decode of $FFCO through $FFDF which, when gated with E and
R/W, results in the write strobe for the SAM CONTROL REGISTER.

SAM Control Register
As shown in Figure 4, the CONTROL REGISTER has 16 "outputs":
~DG Addressing Modes:
V2, Vl, VO
MPU Rate:
VDG Address OFFset:

F6, F5, F4, F3, F2, Fl, FO

~emory

32K fage Switch:

P

Memory Map TYpe:

Size (RAM):

R1, RO
Ml, MO
TV

When the SAM is reset (see page 10,) all 16 bits are cleared. To set anyone of these 16 bits, the MPU simply
writes to a unique** odd address (within $FFC1 through $FFDF.) To clear anyone of these 16 bits, the MPU
* If HS is held low longer than 8
during which

HS

fLS, then the number of sequential addresses in one refresh "BURST" is proportional to the time interval

is low,

** See pages 17 or 18 for specific addresses,
t In this document, the "S" symbol always preceeds hexidecimal characters.

3-583

I

SN74LS783, MC6883
simply writes to a unique** even address (within $FFCO through $FFDE.) Note that the data on the MPU data
bus is irrelevant.
Inputs to the control register include A4, A3, A2, A1 (which are used to select which one of 16 bits is to be
cleared or set), AD (which determines the polarity ... clear or set,) and R/W, E and $FFCO - $FFDF (which
restrict the method, timing and addresses for changing one of the 16 bits.) For more detailed descriptions of
the purposes of the 16 control bits, refer to related sections in the BLOCK DIAGRAM DESCRIPTION (pages 8
through 12) and the PROGRAMMING GUIDE (pages 14 through 18).
** See

pages H or 18 for specific addresses.

FIGURE 5 -

VDG ADDRESS MODIFIER

Mode

I

Division Variables

Bits Cleared by HS (low)

V2

V1

VO

X

Y

0
0

0
0

0
1

1
3

12
1

Bl-B4
Bl-B3

0
0

1
1

0
1

1
2

3
1

Bl-B4
Bl-B3

1
1

0
0

0
1

1
1

2
1

Bl-B4
Bl-B3

1
1

1
1

0
1

1
1

1
1

Bl-B4
None (OMA MODE)

FIGURE 6 -

SIGNAL ROUTING for ADDRESS MULTIPLEXER

Memory Size

4K

M1

MO

Signal
Source

0

0

MPU

VDG

REF

0

16K

1

MPU

VOG

REF

MPU

64K (dynamic)
1

0
VOG

REF

64K (static)

MPU
1

1

Row/Column

REF

Z5

Z4

Z3

AS

A4

A3

A2

Al

AO

T7-TA

All

Al0

A9

A8

A7

A6

TA-TF

Z2

Z1

ZO

Timing
(Figure 2)

Z6

ROW

*

A6

COL

*

L

ROW

*

B6

BS

B4

B3

82

Bl

BO

TF-T2

COL

*

L

Bll

Bl0

89

B8

B7

.B6

T2-T7

ROW

*

C6

CS

C4.

C3

C2

Cl

CO

TF-T2

COL

*

L

L

L

L

L

L

L

T2-T7

ROW

*

A6

AS

A4

A3

A2

Al

AO

T7-TA

COL

*

A13

A12

All

Al0

A9

A8

A7

TA-TF

ROW

*

B6

BS

B4

B3

B2

Bl

BO

TF-T2

COL

*

B13

B12

Bll

810

B9

B8

B7

T2-T7

ROW

*

C6

CS

C4

C3

C2

Cl

CO

TF-T2

COL

*

L

L

L

L

L

L

L

T2-T7

ROW

A7

A6

AS

A4

A3

A2

Al

AO

T7-TA

COL

PIA lS***

A14

A13

A12

All

Al0

A9

A8

TA-TF
TF-T2

ROW

B7

B6

BS

B4

B3

B2

Bl

BO

COL

B1S

B14

B13

B12

B11

Bl0

B9

B8

T2-T7

ROW

L

C6

CS

C4

C3

C2

Cl

CO

TF-T2

COL

L

L

L

L

L

L

L

L

T2-T7

A7

A6

AS

A4

A3

A2

Al

AO

T7-T9

A14

A13

A12

All

Al0

A9

AS

T9-TF

ROW
COL

VOG

Signals Routed to ZO-Z7
Z7

PIA lS***

ROW

B7

B6

BS

B4

B3

B2

Bl

BO

TF-T1

COL

B1S

B14

B13

B12

Bll

Bl0

B9

BS

T1-T7

ROW

L

C6

CS

C4

C3

C2

Cl

CO

TF-T1

COL

L

L

L

L

L

L

L

L

T1-T7

.

Notes. "'"
L Implies logICal LOW level.
'1:7 functions as RAS1 and its level is address dependent For example. when using two banks 01 16K x 1 RAMs, RASO is active lor addresses
$0000 to $3FFF and RAS1 is active lor addresses $4000 to $7FFF.
"'11 Map TYpe = 0, then page bit 'p' is the output (otherwise A15).

3·584

SN74LS783, MC6883

Internal Reset
By lowering VCC below 0.6 volts for at least one millisecond, a complete SAM reset is initiated and is
completed within 500 nanoseconds after VCC rises above 4.25 volts.
NOTE: In some applications, (for example, multiple "VDG-RAM" systems controlled by a single MPU)
multiple SAM ICs can be synchronized as follows:
• Drive all SAM's from one external oscillator.
• Stop external oscillator.
• Lower VCC below 0.6 volts for at least 1.0 millisecond.
• Raise VCC to 5.0 volts.
• Start external oscillator.
• Wait at least 500 nanoseconds.
Now, the "E" clocks from all SAM's should be in-phase.

External Reset
When the VClk pin on SAM is forced below 0.8 volts for at least eight cycles of "oscillator-out", the SAM
becomes partially reset. That is, all bits in the SAM control register are cleared. However, signals such as RAS,
CAS, WE, E or Q are not stopped (as they are with an internal reset). since the SAM must maintain dynamic
RAM refresh even during this external reset period.
Figure 7 shows how VClk can be pulled low through diode 01 when node "A" is low.* When node "A" is
high, only the backbiased capacitance of diode 01 loads the 3.58 MHz on VClk. Diode 02 helps discharge C1
(Power-on-Reset capacitor) when power is turned off. Diode 03 allows the MPU reset time constant R2C2 to
be greater than the SAM reset time constant. Thereby, ensuring release of the SAM reset prior to attempting
to program the SAM control register.

FIGURE 7 -

EXTERNAL RESET CIRCUITRY

+5.0 V

+5.0 V

100 kfl
R2

100 kfl
03

Manual
System
Reset
Switch'

1

/1

l~"'F
MC6883

MC6847

MC6809E

VDG Synchronization
In order for the VDG and MPU to share the same dynamic RAM (see page 13,) the VDG clock must be stopped
until the VDG data fetch and MPU data fetch are synchronized as shown in Figure 12. Once synchronized, the
VDG clock resumes its 3.579545 MHz rate and is not stopped again unless an extreme temperature change (or
SAM reset) occurs. When stopped, the VDG clock remains stopped for no more than 32 OSCOut cycles (approximately 2 microseconds.)
In the block diagram in Figure 4, DAO enters a block labeled VDG Timing Error Detector. If DAO rises between
time reference points** TA and TC, then Error is high and VClk is the result of dividing BOSC (Buffered OSCOut
= 14 MHz) by four. However, if DAO rises outside the time Window TA to TC, then Error goes LOW and the VDG
stops. A START pulse at time reference point TB (center of Window) restarts the VDG ... properly synchronized.
·Use a diode with sufficiently low forward voltage drop to meet VIL requirement at VClk.
··See timing diagrams on page 5 and 6.

3·585

I

SN74LS783, MC6883

Changing the MPU Rate (by changing SAM control register bits RO, R1).
Two bits in the SAM control register determine the period of both "E" and
are implemented as follows:
RATE MODE R1

RO
0

The frequency of "E" (and "0") is f crystal -;- 16. This rate mode is automatically selected when
the SAM is reset. Note that system timing is least critical in this "SLOW" rate mode.

A.D.
0
1
(Address Dependent)

The frequency of "E" (and "0") is either f crystal -;- 16 or f crystal -;- 8. depending on the address
the MPU is presenting.

FAST

The frequency of "E" (and "0") is f crystal -;- 8. This is accomplished by stealing the time that
is normally used for VDG/REFRESH. and using this time for the MPU. Note: Neither VDG display
nor dynamic RAM refresh are available in the "FAST" rate mode. (Both are available in SLOW
and A.D. rate modes).

SLOW

I

"a" MPU clocks. Three rate modes

0

1

X

When changing between any two of the three rate modes, the following procedures must be followed to
ensure that MPU timing specifications are met:

RATE MODE

-- ----1"5"'"'
---Z-t
~"'"O

SLOW
A.D.
FAST

poth "

~q","~#1_

-\

Set RD. then CLEAR R1

•

(See Below)

S

t

Thl' dl,,,'
-""'-'"ow,d 'm~b'---I_
et

R1

.

hardware reset.-A
•

May be ANY address from $0000 to $7FFF.
SEQUENCE #1:
,-A-..
7D 00 00 TST #$0000 ... Synchronizes STA instruction to write during T2·TG (See Figure #8).*
21 00
BRN 00
87 FF 06 STA #$FFD6 ... Clears bit RO
*Note: "TST" instruction affects MeS809E condition code register.

Changing the MPU Rate (In Address Dependent Mode)
When the SAM control register bits "R1", and "RO" are programmed to "0" and "1", respectively, the
Address Dependent Rate Mode is selected. In this mode, the -;- 16 MPU rate is automatically used when
addressing within $0000 to $7FFF* or $FFOO to $FF1 F ranges. Otherwise the -;- 8 MPU rate is automatically
used. (Refer to Figure 8 for sample "E" and "a" waveforms yielding -;- 8 to -;- 16 and -;- 16 to -;- 8 rate
changes). This mode often nearly doubles the MPU throughput while still providing transparent VDG and
dynamic. RAM refresh functions. For example, since much ofthe MPU's time may be spent performing
internal MPU functions (address = $FFFF)**, accessing ROM (address = $8000 to $FEFF) or accessing I/O
(address = $FF20 - $FF5F), the faster f crystal -;- 8 MPU rate may be used much of the time.
Note: The VDG operates normally when using the SLOW or A.D. rate modes. However. in the FAST rate mode, the VDG is not allowed access to
the dynamic RAM.

FIGURE 8 fast
( r - - - -__~A

RATE CHANGE E AND Q WAVEFORMS
slow

~

( r____________________-JA~

______________________~~

E:~

I
I

0: I
. .L.....Jr-----lL-..Jr-----lI--:--L-r--~-I
"slow" address detected herte

t
"fast" address detected here

*When using Memory Map O. addresses $0000 to $7FFF may access Dynamic RAM.
*"The MC6809 outputs $FFFF on AD-A 15 when no other valid addresses are being presented.

3·586

fast
~

!l....-ru---JLj

SN74LS783, MC6883
Oscillator
In Figure 4, an amplifier between Oscln and OSCOut provides the gain for oscillation (using a crystal as shown
in Figure 9.) Alternately, Pin 5 (Oscln) may be grounded while Pin 6 (OSCOut) may be driven at low-power
Schottky levels as shown in Figure 10. Also, see VIH, VIL on page 2.

AC Specifications"
OseOut

Typ

Min

Units

tpH(Ose)

-

30

22

ns

tpL(Ose)

-

30

22

ns

teye(Ose)

-

70

62.4

ns

Max

FIGURE 9 -

CRYSTAL OSCILLATOR

I

Suggested Component Values
Freq.
MHz

CV

CV*

CF"

R1"

~~:~ *

X1

14.31818

2.5-30
pF

33
pF

1.5
kO

~

100K

10K

*

16.0000

2.5-30
pF

33
pF

1.5
k!l

~

100K

10K

*

~

\"

\

",\

~~:: *

\ \
\ \

I

RS

14.31818 MHz**

16.0000 MHz**

100 ± 2.00

100 ± 2.00

CO

5.0 pF ± 1.5 pF

6.0 pF ± 1.0 pF

C1

0.0245 pF ± 15%

0.0319 pF ± 15%

L1

5.05 mH

3.1 mH

50k ± 10K

40K ± 10K

Q

\

1\
I
"-

Recommended Crystal Parameters

\

"-

- A

\

101

8

\

\

"-

, .....

A-8~B
CO

Calibration Tolerance: 0.002% at 26°C
Temperature Tolerance: 0.001% O°C to 70°C

FIGURE 10 -

TTL CLOCK INPUT

(R4 = 2000 Typ, 500 Min)
~

R4
' - - - - - - - - - - -..... OseOut
6

~

74LSOO
(Used as an input)

Typical input capacitances are 3.0 pF for Pin 5 and 5.5 pF for Pin 6.
"Optimum values depend on characteristics of the crystal (Xl). For many applications, VClk must be 3.579545 MHz:!: 50 Hz! Hence,
OSCOut must be made similarly "drift resistant" (by balancing temperature coefficients of Xl, CV, CF, Rl, R2 and R3).
""Specifically cut for MC6883 are International Crystal Manufacturing, Inc. Crystals (#167568 for 14.31818 MHz or #167569 for 16.0 MHz).
However, other crystals may be used.

3·587

SN74LS783, MC6883
THEORY OF OPERATION
Video or No Video
Although the MC6883 may be used as a dynamic RAM controller without a video display*, most applications
are likely to include a MC6847 video display generator (VDG). Therefore, this document emphasizes MC6883
with MC6847 systems.

Shared RAM (with interleaved DMA)
To minimize the number of RAM and interface chips, both the MPU and VDG share common dynamic RAM.
Yet, the use of common RAM creates an apparent difficulty. That is, the MPU and VDG must both access the
RAM without contention. This difficulty is overcome by taking advantage i.lf the timing and architecture of
Motorola MPU's (MC6800, MC6801E, MC6809E, MC68000). Specifically, all MPU accesses of external memory
always occur in the latter half of the machine cycle, as shown below:

FIGURE 11 -

MOTOROLA MPU TIMING

One Machine Cycle

r - - -______~A~________~\

I

'E' Clock'l
(Approx. 1 MHz)

I

I-. _ _ _ _ _ _ _ _ y

__

I

I

r

'--____...

-.-Jy... _______ '.,------.Jy

MPU Address

MPU Data
Window

MPU Address

MPU Data
Window

Similarly, the MC6847 (non-interlaced) VDG transfers a data byte in a half machine cycle (E or <1>2). Thus,
when properly positioned, VDG and MPU RAM accesses interleave without contention as shown below:

FIGURE 12 -

MOTOROLA MPU WITH VDG TIMING
VDG Address

V~~~oa~a

VDG Address

( ________ ~J,., ____ ____..~,.- _______ A___

'E' Clock:
(Approx. 1 MHz)

l

I

I

MPU Half

v~~~:~a

~~

I

VDG Half

r

', ________ y-----.J\.."/',-------,,,---------'y
MPU Address

MPU Data
Window

MPU Address

MPU Data
Window

This Interleaved Direct Memory Access (lDMA) is synchronized via the MC6883 by centering the VDG data
window half-way between MPU data windows. **
The result is a shared RAM system without MPUIVDG RAM access contention, with both MPU and VDG
running uninterrupted at normal operating speed, each transparent to the other.

RAM Refresh
Dynamic RAM refresh is accomplished by accessing eight*** sequential addresses every 64*** microseconds
until 128 consecutive addresses have been accessed. To avoid RAM access contention between REFRESH and
MPU, each of the 128 refresh accesses occupies the "VDG half" of the interleaved DMA (lDMA). Furthermore,
refresh accesses occur only during the television retrace period (at which time the VDG doesn't need to access
RAM).
In summary, the VDG, MPU and MC6883's Refresh Counter all transparently access the common dynamic
RAM without contention or interruption.

Why IDMA?
Use of the interleaved direct memory access results in fast modification to variable portions of display RAM,
by the MPU, without any distracting flashes on the screen (due to RAM access contention.) In addition, the
MPU is not slowed down nor stopped.by the MC6883; thereby, assuring accurate software timing loops without
costly additional hardware timers. Furthermore, additional hardware and software to give "access permission"
to the MPU is eliminated since the MPU may access RAM at any time.
* Only 1 pin, (OAO) out of 40 pins is dedicated to the video display.

** See VOG synchronization (p~e 10) for more detail.
*** When not using a MC6847, HS may be wired low for continuous transparent refresh.

3·588

SN74LS783, MC6883
"Systems On Silicon" Concept
Total Timing
For most applications, the SAM can supply completesystem timing from its on-chip precision 14.31818 MHz
oscillator. This includes buffered MPU clocks (E and Q). VDG clock, color subcarrier (3.58 MHz). row address
select (RAS). column address select (CAS) and write enable (WE).
Total Address Decode
For most applications, the SAM plus a "1 of 8 decoder" chip completely decodes 1/0, ROM and RAM chip
selects without wasting memory address space and without needlessly chopping-up contiguous address space.
Chip selects are positioned in address space to allow three types of memory (RAM, local ROM and cartridge
ROM) independent room for growth. For example, RAM may grow from address $OOOO-up, cartridge ROM may
grow from address $FEFF-down and local ROM may grow from $FBFF-down. Alternately, if the application
requires minimum ROM and maximum contiguous RAM, a second choice of two memory maps places RAM
from $0000 to $FEFF. (See pages 17 and 18.)
In both memory maps all 1/0, MPU vectors, SAM control registers, and some reserved address spaces are
efficiently contained between addresses $FFOO and $FFFF.

How Much RAM7
Using nine SAM pins (ZO - Z7 and RASO) the following combinations require no additional address logic.
FIGURE 13 Address:
MSB

RAM CONFIGURATIONS

Chip Select:
LSB

Z5Z4Z3Z2Z1Z0 ..................................... RASO

t

Z5Z4Z3Z2Z1 ZO ..................................... RAS 1 (= Z7) \- - - - - - One or two banks of 4K x 8 (like MCM4027's)
Z6Z5Z4Z3Z2Z1 ZO ..................................... RASO

t

Z6Z5Z4Z3Z2Z1Z0 ..................................... RAS1 (= Z7) \ - - - - - - One or two banks of 16K x 8 (like MCM4116's)
Z7Z6Z5Z4Z3Z2Z1 ZO ..................................... RASO - - - - - - - - - - - One bank of 64K x 8 (like MCM6665's)

PROGRAMMING GUIDE
SAM -

Programmability

The SAM contains a 16-bit control register which allows the MC6809E to program the SAM for the following
options:
VDG Addressing Mode .......... 3-bits
VDG Address Offset ............... 7-bits
32K Page Switch ...... ...... ......... l-bit
MPU Rate ............................... 2-bits
Memory Size .......................... 2-bits
Map Type ................................ l-bit
Note that when the SAM is reset by first applying power or by manual hardware reset,t all control register
bits are cleared (to a logic "0").

VDG Addressing Mode
Three bits (V2, Vl, VO) control the sequence of DISPLAY ADDRESSES generated by the SAM (which are used
to scan dynamic RAM for video information). For example, if you wish to display Dynamic RAM data as
INTERNAL ALPHANUMERICS VIDEO, you should program:\: the MC6847 for the INTERNAL ALPHANUMERICS
MODE and CLEAR BITS V2, Vl and VO in the SAM. The table on the following page summarizes the available
modes:
t See Figure 7 for manual reset circuit.
; Typically, part of a PIA (MC6821) at location $FF22 is used to control MC6847 modes. (See MC6847 Data Sheet.)

3-589

I

SN74LS783, MC6883

MC6847 Mode

G/A

GM2

GM1

CSS

V2

V1

Internal Alphanumerics

0

X

X

0

X

0

0

0

External Alphanumerics

0

X

X

1

X

0

0

0

Mode Type

OSemigraphics -

I

SAM Mode
GMt
EXTii

4

VO

0

X

X

0

X

0

0

0

Semigraphics -

6

0

X

X

1

X

0

0

0

Semigraphics -

8*

0

X

X

0

X

0

1

0

Semigraphics -

12*

0

X

X

0

X

1

0

0

Semigraphics -

24*

0

X

X

0

X

1

1

0

Full Graphics -

1C

1

0

0

0

X

0

0

1

Full Graphics -

1R

1

0

0

1

X

0

0

1

Full Graphics -

2C

1

0

1

0

X

0

1

0

Full Graphics -

2R

1

0

1

1

X

0

1

1

Full Graphics -

3C

1

1

0

0

X

1

0

0

Full Graphics -

3R

1

1

0

1

X

1

0

1

Full Graphics -

6C

1

1

1

0

X

1

1

0

Full Graphics -

6R

Direct Memory Accesst

1

1

1

1

X

1

1

0

X

X

X

X

X

1

1

1

*S8, S12, & S24 modes are not described in the MC6847 Data Sheet. See appendix "A".
tDMA is identical to SR except as shown in Figure 5 on page 9.

VDG Address Offset
Seven bits (F6, F5, F4, F3, F2, F1 and FO) determine the Starting Address for the video display. The
"Starting Address" is defined as "the address corresponding to data displayed in the Upper Left corner of
the TV screen". The "Starting Address" is shown below in binary:

Note that the "Starting Address" may be placed anywhere within the 64K address space with a resolution of
%K (the size of one alphanumeric page).
The F6-FO bits take effect during the TV vertical synchronization pulse (i.e., when FS from MC6847 is low).

Page Switch
One bit (P1) is used "in place of" A15 from the MC6809E in order to refer access within $OOOO-$7FFF to one
of two 32K byte pages of RAM. If the system does not use more than 32K bytes of RAM, P1 can be ignored. **
**When using 4K x , RAMS, two banks of eight IC's are allowed. This accounts for Addresses $0000·' FFF. Also, this same RAM can be
addressed at $2000·$3FFF, $4000·$5FFF and $SOOO-$7FFF.

3-590

SN74LS783, MC6883
MPU Rate
Two bits (R1, RO) control the clock rate to the MC6809E MPU. The options are:
RATE (FREQUENCY OF "E" CLOCK)

R1

RO

0
0
1

0
1
X

0.9 MHz (Crystal Frequency -7 16) Slow
0.9/1.8 MHz (Address Dependent Rate)
1.8 MHz (Crystal Frequency -7 8) Fast
(Typical Crystal Frequency

=

14.31818 MHz)

In the "address dependent rate" mode, accesses to $0000-$7FFF and $FFOO-$FF1 F are slowed to 0.9 MHz
(crystal frequency .;- 16) and all other addresses are accessed at 1.8 MHz (crystal frequency .;- 8.)
Note: "Slow" (0.9 MHz) operation can be accomplished using 1.0 MHz MC6809E and MC6821 devices. For "Fast"
(1.8 MHz) operation, 2.0 MHz MC68B09E and MC68B21 devices must be used.

Memory Size
Two bits (M1 and MO) determine RAM memory size. The options are:
SIZE

I

M1 MO

One or two banks of 4K x 1 dynamic RAMs
One or two banks of 16K x 1 dynamic RAMs
One bank of 64K x 1 dynamic RAMs
Up to 64K static RAM*

0
0
1
1

0
1
0
1

*Requires a latch for demultlplexmg the RAM address.

IMPORTANT!
Note: Be sure to program the SAM for the correct memory size before using RAM (i.e., for a subroutine
stack).

Map Type
One bit (TV) is used to select between two memory map configurations.
Refer to pages 17, 18 and 19 for details. Early versions of the SAM did not allow the "Fast" MPU rate to be
used in conjunction with Map Type "TV = 1". Devices manufactured after January 1, 1983 allow both "Fast"
and "Slow" MPU rates to be used with Map Type "TV = 1." (Date of manufacture is marked on devices as
VVWW where VV is the year and WW is the week of manufacture.)

Writing To The SAM Control Register
Any bit in the control register (CR) may be set by writing to a specific unique address. Each bit has two unique
addresses ... writing to the even # address clears the bit and writing to the odd # address sets the bit. (Data
on the data bus is irrelevant in this procedure.) The specific addresses are tabulated on pages 17 and 18.
If desired, a short routine may be written to program the SAM CR "a word at a time". For example, the
following routine copies "B" bits from "A" register to SAM CR addresses beginning with address "X".
SAM1

46
24
30
A7
20

06
01
80
02

ROR
BCC
INX
STA
BRA

A
SAM2
(LEAX1,X)
O,X+
SAM3

SAM2

A7

81

STA

O,X++

SAM3

5A
26
39

F2

DEC
BNE
RTS

B
SAM1

7

6

543

o c

(I~---'----'-~_'____.I.......I-+D )

3·591

SN74LS783, MC6883

FIGURE 14 - MEMORY MAP (TYPE #0)
COURSE

FINE
MC6809E
Address

Me6809E
___ 8 _
Vectors,
Bits
SAM ~
Control,
1/0

52,
51, SO MC6809E
Value Address

+

t

/$FFFF

1" $FFOO

t

~~~

I~
~~~

ROM2**

Definitions

Label
~

~---

SWI

..

(S=3)

~~---+-""'-"....L--_SWI13-----l
(S

I

r- - -- -r<$COOO

~~
~\f----!,!,f-~"--~f- ~

I:

ROM1**
(S=2)

Do not use!

~~~

- - - - ---<$AOOO

~-J--CL>!L-+-SL..-..jS'

ROMO**

1",\---..!L.ll.liL-+-"-----l

(S= 1)

16~:::tic t
IT

MO

:-:::

011

I

M~~~ry

1

l'I

0

1

16K

0

~ F,::';,mio

I

I Fpr~·SLOW ~ ~~~:::rent

I

I~~~~~RO~~_~~--~O~

I
I

~~t=ii~t=1=t~+-F-61-------l'

r - - - - I - - - - - - -k$8000

~

I

(S

RAM
(5=0 if R/W = 1)
(5=7 if Rf'W = 0)

I

I
I

r

~--

I

",'

~~:---e~-+~--I

:

t

'-v-" '-v-"

"IBi'''VI

D~~6R, G6C

~GI3RGI3CG2R
IG~G~,G1R

~
~
~

(S

16K

4K

r--

~:\j--=:L!~::L...-::~::1-:--+:-~-~-~e-~~"--!-,,--!-,,--!-,,--!-,,,-'!'-"'-I'!'-"'-:!-:
l'.~

I

D~~~:i

Address of "Upper-Left-Most
Display Element = $0000 + (V,K· Offset)

~

-k$4000

:-- -r

F4

MPU Addresses from $0000 to $7FFF
Apply to page #1 if P1 = '1

}

'>

F5

"

I
I

I
I
I

Page

~

I
I

Page 1

Reserved
for future
MPU
enhancements.

I---

~
FF60

VO

AI, AE, S4, S6

(SAM)

Reserved
Do not use!

Reserved for Future
Control Registers or Special 1/0

~~
FF43

~*
k$1000

""$0000

I/00(Slow)

Page 0

'Note:
M.S. == Most Significant
L.S. == Least Significant

S == Set Bit · f (All bits
. are cleared when SAM is reset.)
C == CI ear BIt
S = Device Select value = 4 x S2 + 2 x S1 + 1 x SO

3-592

"May also be RAM

SN74LS783, MC6883
FIGURE 15 -

MEMORY MAP (TYPE #1)
FINE

COURSE
MC6809E;
~ 8 ___ Address I
MC6809E
Vectors,
Bits
5AM ~
$FFFF
Control, ~'\.
I/O, Boot
"$FFOO'
ROM

t

52,
51,50 MC6809E
e Address

vat
~

(S = 0
if
R/W = 1)
RAM

if
(S = 0

if

---....;. r<$8000
R/W = 1)

..J
..J

(S=O

if
R/W=1)
(S

(S=7

if

S'
('

MI

I

RO

~

F5

I

~

(S

(S
'-----""""-« $0000

F4
F3
F2

VO
FF60

Display
Offset
(Binary)

,-"

~ Dynamic

rl'F~AST

1

0

1

rA~.SLOW

0

0

l Transparent
\ Refresh

0

} (No effect in this map type)

rrrGf:fGFG~G~

G1R
AI, AE, S4, S6

VDG
Mode
(SAM)

I

1

1

0

0

o

0

o 1

0

1

0

1

ROM Boot Load**
& MC6S09 Vectors

...EE~

FF

64KD
1,16K

AddresE of "Upper-Left-Most
Display Element" = $0000 + (1

FO

V1

'55"'0

MPU
Rate

Fl

~

~
~

Memory
Size

F6

~
~ ~~
~
~

rv~

Page

I
I

I

(S

TV

MO

I

R/W=O)

1
64

I

R/W =0)

=

Do not use!

~
~

---K$AQOO
(S = 1

I

Reserved
for future
MPU
enhancements.

II

if
R/W =0)

SWI3

..

~

is=-2 ';"*. K$COOO

*Note:
M.S.
Most Significant
L.S. '" Least Significant

IRQ

FiRci

~

if
R/W =1)

«

SWI

~
(S

(S = 0

«
cr::

NMf

I

if

~

REsff

I~

(S = 3
R/W =0)

a

L b eI
Def In!'fIons
/~;~---

1/02

~lE

FI ~3
....E!:2..
FI
FI
....E!_

1/01

FFo3

I/OO(Slow)

**Decode S2, S1, and SO wit h an open
collector SN74LS156 and' wire-or' state 7
with state 2. (See Append ix B for
suggested decode circuit. )
***To avoid ROM enable duri ng R/W = LOW,
the ROM at S = 2 must b e gated with R/W.
(See Appendix B for sugg ested decode circuit.)

~

FF01
FFoO

S '" Set Bit 't ~ (All bits
. are cleared when SAM .
)
IS reset.
C '" CI ear B I
S = Device Select value = 4 x S2 + 2 x S1 + 1 x SO

3·593

SN74LS783, MC6883
FIGURE 16 - MEMORY ALLOCATION TABLE
(Also, see the memory MAPs on pages 17 and 18.)
Type # 0:

(Primarily for ROM based systems)

Address Range

5=4(52)+2
(51) +50
5 Value

$FFF2 to FFFF
FFEO to FFF1
FFCO to FFDF
FF60 to FFBF
FF40 to FF5F
FF20 to FF3F
FFOO to FF1F
COCO to FEFF
AOOO to BFFF

I

8000 to 9FFF
0000 to 7FFF

2
2
7
7
6
5
4
3
2

1..o if R/W =
7 if

1

Intended Use
MC6809E Vectors: Reset, NMI, SWI, IRQ, FIRQ, SWI2, SWI3.
Reserved for future MPU enhancements.
SAM Control Register: VO, - V2, FO - F6, P, RO, R1, MO, M1, TV.
Reserved for future control register enhancements.
1/02: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
1/01: Input/Output (PIAs, ACIAs,etc.) To subdivide, use AO - A4.
1/00: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
ROM2: 16K addresses. External cartridge ROM*.
ROM1: 8K addresses. Internal ROM*. Note that MC6809E vector addresses select this
ROM*.
ROMO: 8K addresses. Internal ROM*.
RAM: 32K addresses. RAM shared by MPU and VDG.

Riw =0

*Not restricted to ROM. For example, RAM or 1/0 may be used here.

Type # 1:

(Primarily for RAM based systems)

Address Range
$FFF2 to FFFF
FFEO to FFF1
FFCO to FFDF
FF60 to FFBF
FF40 to FF5F
FF20 to FF3F
FFOO to FF1 F
0000 to FEFF

5=4(52)+2
(51)+50
5 Value
2
2
7
7
6
5
4
o if R/W

=

1

Intended Use
MC6809E Vectors: Reset, NMI, SWI, IRQ, FIRQ, SWI2, SWI3.
Reserved for future MPU enhancements.
SAM Control Register: VO - V2, FO - F6, P, RO, R1, MO, M1, TV.
Small ROM: Boot load program and initial MC6809 vectors.
1/02: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
1/01: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
1/00: Input/Output (PIAs, ACIAs, etc.) To subdivide, use A2 - A4.
RAM: 64K( - 256) addresses, shared by MPU and VDG.
(If R/W = 0 then S = 3 for $COOO-$FEFF; S = 2 for $AOOO-$BFFF; S
$8000-$9FFF and S = 7 for $0000-$7FFF.)

3·594

=

1 for

SN74LS783, MC6883
APPENDIX A
VDG/SAM Video Display System Offers 3 New Modes
by
Paul Fletcher
There are three new modes created when the VDG
and 5AM are used together in a video display system. These modes offer alphanumeric compatibility
with 8 color low-to-high resolution graphics,
64Hx64V, 64Hx96V, 64Hx192V. The new modes 58,
512, and 524 are created by placing the VDG in the
Alpha Internal mode and having the 5AM in a 2K,
3K or 6K full color graphics mode. In all modes the
VDG's 5lA. and Inv. pins are connected to data bits
DD7 and DD6 to allow switching on the fly between
Alpha and 5emigraphics and between inverted
and non-inverted alpha. This method is used in
most VDG systems to obtain maximum flexibility.
The three modes divide the standard 8*12 dot box
used by the VDG for the standard alpha and semigraphics modes into eight 4*3 dot boxes for the 58
mode, twelve 4*2 dot boxes for the 512 mode, and
twenty-four 4*1 dot boxes for the 524 mode. Figure
17 shows the arrangement of these boxes. One byte
is needed to control two horizontally consecutive
boxes. It therefore takes four bytes for the 58, six
bytes for the 512, and 12 bytes for the 524 mode to
control the entire 8*12 dot box. These two horizontally consecutive boxes have four combinations of
luminance controlled by bits 80 - 83. For conven-

ience 82 should be made equal to 80 and 83 should
be made equal to 81. This eliminates a screen placement problem which would cause other codes to
change patterns when moved vertically on the
screen. The illuminated boxes can be one of eight
colors which are controlled by 84- 86 (see Figure
18). The bytes needed to control all the boxes in the
8*12 dot box must be spaced 32 address spaces
apart in the display RAM because of the addressing
scheme orginally used in the VDG and duplicated
by the 5AM. This means to place an alphanumeric
character on the TV screen it requires 4, 6, or 12
bytes depending on the mode used. These bytes are
placed 32 memory locations apart in the display
RAM (see Figure 18). This multiple byte format allows the mixing of character rows of different characters in the same 8*12 dot box creating new characters and symbols. It also allows overlining and
underlining in eight colors by switching to semigraphics at the correct time.
These new modes optimize the memory versus
screen density tradeoffs for RF performance on
color TVs. This could make them the most versatile
of all the modes depending on the users creativity
and the software sophistication.

APPENDIX B
Memory Decode for "MAP TYPE

= 1"
MPU Vectors and
Boot Load ROM
128 X 8 (or 256 X 8)

EN
Vcc = 16
Gnd = 8

"7 (03a)
Ea

-=

+5.0
V

4

+5.0
V
6'(02a) 5

Ea

5
4

EN

110 2

+5.0
V
(01a)
6
+5.0
V
(OOa)

1/0 1
1100

SN74LS156

S2
14

fmm

SAM!

Eb
Eb

-=

12

2 (02b)

11

1(01b)

S1
So

"3 (03b)

A1
13

AO

o(OOb)

10

NC

NC
+5.0 V
RAM READ

3·595

I

SN74LS783, MC6883

FIGURE 17 -

DISPLAY MODES S8, S12, S24
BitIVisible Dot Correlation

~8Rightl

~~~ress Byte

1

Scan
Lines

58

•
• •
•
•
•
•
• • • ••
•
•
•
•

12

1

I

$XXOO ($01)

~8--'1

1

Scan
Lines

512

$XX40 ($01)

$01 is the
VDG "ASCII"
code for 'A',

$XX60 ($01)

• Alphanumeric Compatible

***

Left

Right

Red

Red

$XXOO ($BF)

Blue

Off

$XX20 ($AA)

Green

$XX40 ($85)

Off

12

1

1

Orange

Orange $XX60 ($FF)

Off

Off

$XX80 ($80)

Yellow

Yellow

$XXAO ($9F)

• Options: One of 8 colors for
L or R or both, Off = Black

1'-8-1
Scan
Li
nes t - - - - - i - - - - i

r------+-------

524

$XX20 ($01)

Blue
Black
Black

Blue
Black
Black

**

• • • ••
•

~-----!J

•
•

• •
•
• •

Black
Green

•

•
•

Black
Green

$XXOO
$XX20
$XX40
$XX60
$XX80

$XXAO ($18)!
$XXCO ($18)
VDG
$XXEO ($18)
Code
$X100 ($18)
for X
$X120 ($18)
$X140 ($80)
$X160 ($8F)

• Underline, Overline
• Mix Character Dot Rows

***

Characters will always remain in standard VDG positions.

3-596

($AF)
($80)
($80)
VDG
($14) _Code
($18)
for T

FIGURE 18 -

58 DISPLAY FORMAT EXAMPLES

r-(1~*~
LO

L1
L1

LO

L1

LO
LO

L1

(,.)

~
.......

~

(l1 Column

I,~

X

Black

0

0

0

Green

0

1

Yellow

1

0

Blue

0

1

1

Red

1

1

0

0

Buff

1

1

0

1

Cyan

1

1

1

0

Magenta

1

1

1

1

Orange

0

X

X

1

0

0

1

0

1

0

1
(b)

1

J

Alpha

~
Extra

y~----~
ASCII Code

C)

(d)

I

4
Off

Off

CD

0

Off

0

Color

Color

I

Off

co!or

..

1st row of 4 x 3
dot boxes

..3,'

32 Columns - - - - - - - - - - _

(a)1
(a)2
(a)3
(a)4
(a)5

+

I

1111 rowt

(d)

~

2nd row of 4 x 3
dot boxes

One

F

ROWOf+

8 x 12

TV Screen
Resolution
Semi = 64 x 64
Alpha = 32 Char. H. x 16 Rows V

16 Rows
of 58 Blocks

$0000

(a)32
(b)1
(b)2
(b)3
(b)4
(b)5

3rd row of 4 x
dot boxes

+

4th row of 4 x
dot boxes

,

0020

;

(b)32
(c)1
(c)2
(c)3
(c)4
(c)5

$0040

~

(c)32
(d)1
(d)2
(d)3
(d)4
(d)5

$0060

;

(d)32

•

JIl

3:

0

S8 Screen Memory Map

.f 58 8'.,k.

234.

B2,BO

CO

Semi

a )**

l~~1Ii1111111111
..

B3,B1

C1

BO

12

S8

Color

LX C2

en
z
.....
.,..
ren
.....

$0080

0)

CD
CD
W

SN74LS783, MC6883

FIGURE 19 - EXAMPLE of MC6809E. MC6883 and MC6847 COMPUTER

) ENOC

,

-

-

r---

A15
A14
A13

A9

AS

23

A7

1

1

A6

2

2

3

3

A11
A10

I

A5

A11
A10

19
22
23

A4

CS1

24

CS1

24

4

4

A3

CSO

22

CSO

22

5

5

6

6

35

7

7

RSO 36

8

8

A2
A1

35

RS1

AO

RSO
CS2

Rm

~~~~~~~~~

_ 21
S
18

- 21
S
_ 18
S
19
A10
22

A12

RS1

36

~KiO

CS2

~101

E~ROM1

S~ROM2

21

21

BA

<

BS
BUSY
LlC

::II

::II

3:
3:
(')
3:
en
00

3:
3:
(')
3:
en

3:

~

Co)
Co)

::II

J!

:!

3:
(')
en
00

~

E

(')

.

en

25

00

~

0

0

0

»

»

TSC

25

~

»

00
»

en

N

0

s::

(')

!:

en

00

»
Co)

171
U1

FIRO
IRO

IRDA,B

38,37

IROA,B

38,37

HALT
NMI

34

34

+5 V

20

20

24

24

GNO

1

1

12

12

RESET

~+12V

~-12V
07

07

26

07

26

07

17

07

17

D6

27

27

16

16

05

28

28

15

15

D4

29

29

14

14

03

30

30

13

13

02

31

31

11

11

01

32

32

10

10

33

DO 33

DO

DO

DO

9

DO

9

OSPB

-

'-

I

PB~
4 3
2 1
7 6 5
0

17116115114113112\11\10\

,

PA7

6

5

4

3

91817\ 6151

2

1

,
0

41 3\21

CB-

CA-

~
2

1

2

1

19118'1391401

64 KEY
KEYBOARD
CONNECTS
HERE

::.-J

PB~
4 3
2 1 0
7 6 5
171161151141131121111101

~

~I

9\ 81

19118139\401

PA-

7\

61

51

41

31

21

'2

1

2

1

MC6847 Mode Control & Misc 1/0 connects here.

3-598

J

SN74LS783, MC6883

VIDEO
ENCODER
MODULATOR
CONNECTS

4.7 k
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -______~~~+5V

+

~--------------------2__13

36

A15
f--____________________
2-l2 A14

~-----IA15

21
~--------------------__I A13
21
20
A12 I--=-----------------------j A12
18
19
~1

Al0

19

18

22

17

23

16

I

15

2

14

f--_ _....:3--j7 A14

6~ii02

~---3~8 A13

5~1iQ, ..,

~-----IAII

Al0

~-----IA10

23

o

4

~-----IA7

~--------------------~A6

1-------1 A6
22
1--------I A5
21
1--------IA4
19
1-------1 A3
18
f - - - - - - - l A2

10
9

1.l1..-..
d>A,-----.

15 ) MRD

16

CHB~

Gnd~8

EN EN
5 4

f--------IAI
16
f------'-'-j AO

~8~---------------------I8 AO
f--____________________3~2

VCC~

20
Gndh

1

17

f------------------------jAI

E~ROMO

AOM2"

24

~-----IA8

~--------~----------~A2

4P ilOO

A2 ~ _ 12

iii _

~-----I3 A9

~--------------------~A3

3

r----

26
2
~ 3
S I C - - Al
13 - - To
27
I
;;: 2 ~ ROM I Chip
SOt-='-- AO CD _ 14 _ _ Selects
I ~ROMC!J

3
13
f------------------------jA5
12
4
f------------------------jA4

7

S2

2

~--------------------__IA7

6

25

I

Ml

~--------------------__IA8

II

'00

39

1----~A12

~--------------------__IA9

5

~lII

r2- NC

7

RW

6 1.5 k
OSCOut I--'Wor---.---

cb-

50 PF1::
.".

f--_ _--'-1=-j5 R/W

t

14.31818
MHz

OSCin 1-'50--__- . - _
6

f------------------------jBA

9-35 pF

~:
TO PIA

5

f-----------------------BS

HSI-9"---______________+-_t~ HS

33

f - - - - - - - - - - - - - - - - - - - - - - - BUSY
f--__________________----'-3.:...8 lIC 3:

38

+-__--=2""2 DAO
VClk 1--7________--.-_______+-___3---<3 Clk
DAO 1--8________________

39
"V
f------------------------'-.:... TSC C

3:

34- l E
f--__________________----=35

g
3:

14
~ 1-------lE
~
13
f-----'--lo

C')

!

o ~

4_

f - - - - - - - - - - _ - - - - - - - - - - - l FIRO
3 __
~--------+-_+--------__IIRO

40 _
f - - - - - - - - - - + - - + - - _ - - - - - l HALT
f--________+--+__+-__- -2-l NMI
37
f----------+--+--+--1
f--.:...-lRESET

~2~4--------~~-~~S-L-S-~~L---7__1VCC

~1~2---------------------l1
17

Gnd

24

Z7 Z6 Z5 Z4 Z3 Z2 Z1 ZO
35 34 33 32 31 30 29 28

f----<>+5 V

CAS
RASO
WE
12 II 10

13' la' 11'12' 6' 7' 5' 4'

As A5 A4 A3 A~ Al
RAM's MCM4116B-20
2 07

3

~1.:...6____________________
25__1D6

2 D6

5

III

2 D5

7

5

26 05

14

27 D4

2 D4

9

13

28 03

2 03

12

~
t

07 14

~
3 0

1--1.:.5__0.:.6+--14______---14
13

05 14

[34 NS

~

7

II

04 14

8

8

03 14

13

0

1-"-2_--+-~1~0
5

III

007

2 006

r.:.6_ _ _~8 005

Z

"'w~

7
1-'-9_ _ _-1
1--12"---_ _

004

29 02

f--______2+-D_2____________---I14 VCC=20 6

Q2

14

14 VCC=20 15

5 002

10

30 01

16 Gnd = 10 4
f--____----.:2=-t=-D_l____________---1

01 14

17 Gnd = 10 16

4 DOl

18
f--____----.:2=-t=-D.:...0____________---1

-,

1>2

OUTPUT eaUIVALENT
CIRCUIT

AND
CONTROL
BUS

ORDERING INFORMATION
(Temperature Range for the following devices =
o to +75 0 C)

3·601

DEVICE

ALTERNATE

PACKAGE

MC8T95L
MC8T96L
MC8T97L
MC8T98L
MC8T95P
MC8T96P
MC8T97P
MC8T98P

MC6885L
MC6886L
MC6887L
MC6888L
MC6885P
MC6886P
MC6887P
MC6888P

Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP

MC8T95-98/MC6885-88
PIN CONNECTIONS AND TRUTH TABLES
MC8T96/MC6886

MC8T95/MC6885

II

Enable 2

Enable 1

Input

Output

Enable 2

Enable 1

Input

Output

L
L

L

L

L
L

H

H

H

X
X
X

Z
Z
Z

L
L
L

L

H

L
Z
Z
Z

L
L
L

H

H
H

L

H

H

H
H

X
X
X

L

H

MC8T97/MC6887

MC8T98/MC6888

Enable

Input

Output

L
L

L

H

H

X

L
H
Z

L = Low Logic State
H = High Logic State
Z = Third (High Impedance) State
X = Irrelevant

MAXIMUM RATINGS

Enable
L
L

H

Input

Output

L

H
L

H
X

(TA = 25°C unless otherwise noted.)

Rating
Power Supply Voltage

Symbol

Value

Unit

V~

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Operating Ambient Temperature Range

TA

o to +75

°c

T stg

-65 to +150

°c

Storage Temperature Range
Operating Junction Temperature
Plastic Package
Ceramic Package

°c

TJ
150
175

3-602

Z

MC8T95-98/MC6885-88
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, OoC ";;TA";; 75°C and 4.75 V ";;VCC";;5 25 VI
Symbol

Min

Input Voltage - High Logic State
(VCC ~ 4.75 V, T A ~ 25 0 CI

VIH

2.0

-

-

V

Input Voltage - Low Logic State
(VCC ~ 4.75 V, T A ~ 25 0 CI

VIL

-

-

0.8

V

Input Current - High Logic State
(VCC ~ 5.25 V, VIH = 2.4 VI

IIH

-

-

40

!J.A

Input Current - Low Logic State
(VCC ~ 5.25 V, VIL ~ 0.5 V, Vll.:(E) ~ 0.5 VI

IlL

-

-

--400

!J.A

IIH(EI

-

-

--40

!J.A

Output Voltage - High Logic State
(VCC ~ 4.75 V, 10H ~ -5.2 mAl

VOH

2.4

-

-

V

Output Voltage - Low Logic State
(lOL ~ 48 mAl

VOL

-

-

0.5

V

-

-

Cha racteristic

Input Current - High Impedance State
(VCC ~ 5.25 V, VIUII = 0.5 V, VIH(EI~ 2.0 VI

Output Current - High Impedance State
(VCC = 5.25 V, VOH = 2.4 VI
(VCC = 5.25 V, VOL = 0.5 VI

10Z

Output Short·Circuit Current
(VCC = 5.25 V, Va = 01
(only one output can be shorted at a timel

lOS

Power Supply Current
(VCC ~ 5.25 VI

ICC

Typ

Max

Unit

!J.A
-

-

40
--40

--40

-80

-115

-

98
89

mA

mA

MC8T95, MC8T97, MC6885, MC6887
MC8T96, MC8T98, MC6886, MC6888

-

65
59

Input Clamp Voltage
(VCC = 4.75 V, IIC = -12 mAl

VIC

-

-

-1.5

V

Output VCC Clamp Voltage
(VCC = 0, lac = 12 mAl

VOC

-

-

1.5

V

Output Gnd Clamp Voltage
(VCC = 0, IOC = -12 mAl

VOC

-

-

-1.5

V

Input Voltage
(II = 1.0mA)

SWITCHING CHARACTER ISTICS (VCC

Characteristic

=

-

5.5

VI

50 V T A ~ 25°C unless otherwise noted)
MC8T95/97
MC6885/87
Symbol

Propagation Delay Time - High to Low State
(CL ~ 50 pFI
(CL ~ 250 pFI
(CL ~ 375 pFI
(CL ~ 500 pF)

tpHL

Propagation Delay Time - Low to High State
(CL ~ 50 pFI
(CL ~ 250 pFI
(CL ~ 375 pFI
(CL ~ 500 pFI

tPLH

Transition Time - High to Low State
(CL ~ 250 pF)
(CL ~ 375 pF)
(CL ~ 500 pF)

tTHL

Transition Time - Low to High State
(CL ~ 250 pF)
(CL ~ 375 pF)
(CL ~ 500 pF)

tTLH

Min

MC8T96/98
MC6886/88
Max

Min

Typ

Max

-

12

4.0

-

11

16
20
23

-

-

-

-

-

-

-

15
18
22

3.0

-

10

22
28
35

-

10
13
15

-

-

28
38
53

-

Typ

Unit
ns

3.0

-

-

-

ns
3.0

-

13

-

25
33
42

-

-

-

-

10
11
14

-

-

-

-

-

-

-

ns
-

-

-

ns

-

3·603

V

-

32
42
60

-

-

-

-

-

-

I

MC8T95-98/MC6885-88
SWITCHING CHARACTERISTICS (Vee = 5.0 v, T A = 25 C unless otherwise noted.)
MC8T96/98
MC6886/88

MC8T95/97
MC6885/87
Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Propagation Delay Time - High State to Third State
(Cl = 5.0 pF)

tPHZ(E)

-

-

10

-

-

10

ns

Propagation Delay Time - low State to Third State
(Cl = 5.0 pF)

tPlZ(E)

-

-

12

-

-

16

ns

Propagation Delay Time - Third State to High State
(Cl = 50 pF)

tPZH(E)

-

-

25

-

-

22

ns

Propagation Delay Time - Third State to low State
(Cl = 50 pF)

tpZl(E)

-

-

25

-

-

24

ns

Characteristic

FIGURE 2 - WAVEFORMS FOR PROPAGATION DELAY
TIMES INPUT TO OUTPUT

FIGURE 1 - TeST CIRCUIT FOR SWITCHING CHARACTERISTICS

I

,..----""'\..----- 3 V

To Scope
Output

To Scope (I nput)

Open for tPZH(E) Test Only

Input or
Enable

~---OV

+5 V
~

200
50

Output
MC8T96, MC6886
MC8T98 or MC6888

Output

'.0 k

CL Includes Probe and
Jig Capacitance

1

MC8T95"MC6885
MC8T97 or MC6887

--I. _ _- J

Open for
tPZL(E) Test Only

Input Pulse Conditions
tTHL ~ tTLH '" '0 ns
f
1.0 MHz
c

FIGURE 3 - WAVEFORMS FOR PROPAGATION DELAY TIMES -

VOH--------~~
"-~V
~t

\15

Output

.

tPHZ(E)

,'-....:..---,;;'.5V

----ll---

I ,.------ 3.0 V

_____-Jf__

£iiii'A'BU TO OUTPUT

"ZC",-J

r_ :::

VOL-------~
JPLZ(E)

I

Output
VOL

,_._5~l

Output

Enable
0

\,.5V

'·_5_V_ _ _ _ _ 0

Enabl: _ _ _ _ _

3.0 V

V

3.0 V
V

tpZH(E)

i

I--

H = High-Logic State, L = Low-Logic State, Z

3-604

Enable

\,.5V

~

Ii==

1,.5

V

= High Impedance State

0

VOH
Output

MC8T95-98/MC6885-88

FIGURE 4 - ADDRESS MULTIPLEXER FOR 16-PIN 4K NMOS MEMORV
Row Enable

-

1
MC8T97
or
Other

Row Address From MPU

Column Address
From MPU

--=:;

::

Column Enable

E

AO

1

MCM6604A
NMOS
Memory
Array
AS

I--

MC8T97
or
Other

1

~

t---

E

I

3-605

®

MC8T28
MC6889

MOTOROLA

NONINVERTING
QUAD THREE-STATE BUS TRANSCEIVER

I

NONINVERTING
BUS TRANSCEIVER

This quad three-state bus transceiver features both excellent MOS
or MPU compatibility, due to its high impedance PNP transistor
input, and high-speed operation made possible by the use of Schottky
diode clamping. Both the -48 mA driver and -20 rnA receiver outputs
are short-circuit protected and employ three-state enabling inputs.
The device is useful as a bus extender in systems employing the
M6800 family or other comparable MPU devices. The maximum
input current of 200 /JA at any of the device input pins assures
proper operation despite the limited drive capability of the MPU
chip. The inputs are also protected with Schottky·barrier diode
clamps to suppress excessive undershoot voltages.
Propagation delay times for the driver portion are 17 ns maximum
while the receiver portion runs 17 ns. The MC8T28 is identical to
the N E8T28 and it operates from a single +5 V supply.
•

High Impedance Inputs

•

Single Power Supply

MONOLITHIC SCHOTTKY
INTEGRATED CIRCUITS

LSUFFIX
CERAMIC PACKAGE
CASE 620-02

_
!
16

•

High Speed Schottky Technology

•

Three·State Drivers and Receivers

•

Compatible with M6800 Family Microprocessor

•

Non-Inverting

1

.

(I··

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

MICROPROCESSOR BUS EXTENDER APPLICATION

PIN CONNECTIONS -

(Clock)

GND+5V C"

•

MC8T28
MC6889

,,2
Receiver
Enable
Input

Receiver

,

Output

Driver
Enable

2

Input
Receiver
Output
4
Bus 4

Receiver
Output

Driver
Input
4
Receiver

5

2

Output

3
Driver
Input

Bus3

7

2
Gnd

ORDERING INFORMATION

3-606

Device

Alternate

MC8T28L

MC6889L

MC8T28P

MC6889P

Temperature
Range

o to
o to

Package

+75°C

Ceramic DIP

+ 75°C

Plastic DIP

MC8T28, MC6889

MAXIMUM RATINGS

(T A = 250 C unless otherwise noted.)

Symbol

Value

Unit

VCC

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Junction Temperature
Ceramic Package
Plastic Package

TJ

Operating Ambient Temperature Range

TA

o to + 75

T stg

-65 to+150

Rating
Power Supply Voltage

150

Storage Temperature Range

ELECTRICAL CHARACTERISTICS

°c
175

°c
vc

(4.75 V';; VCC" 5.25 V and OoC .. T A';; 75 0 C unless otherwise noted.)

Characteristic

Symbol

Input Current - Low Logic State
IRecelver Enable Input. VILIREI = 0.4 VI
IDriver Enable Input. VILlDE) - 0.4 VI
IDrlver Input. VILIDI = 0.4 V)
(Bus I Receiveri Input. VILIBI -- 0.4 VI

Min

Typ

IILlREI
II LlDEI
IILIDI
IILIBI

Input Disabled Current - Low Logic State
(Driver Input, VILlD) = 0.4 V)

Max

Unit

-200
-200
-200

)1A

11

-200

IILlD) DIS
-25

)1A

IIHlREI
II HIDEI
IIHIDI

25
25
25

)1A

VILlREI
VILIDEI
VILIDI

0.85
0.85
0.85

-

Input Current-High Logic State
(Receiver Enable Input, VIHIREI - 5.25 VI
IDrlver Enable Input, VIHIDEI
525 VI
IDrlver Input, VIHIDI = 5.25 VI
Input Voltage - Low Logic State
I Receiver Enable I nputl
I Driver Enable Input
I Dflver Inputl
IReceiver Input)

VILIB)

Input Voltage - High Logic State
IRecelver Enable Inputl
I Dflver Enable Inputl
IDrlver Inputl
IReceiver Input)

-

VIHlREI
VIHIDEI
VIHIDI

2.0
2.0
20

VIHIB)

2.0

-

0.85

-

-

V

~

_.

Output Voltage - Low Logic State
(Bus Driver) Output, IOLlB) = 48 mAl
(Receiver Output, 10LlR) = 20 mAl

VOLIBI
VOLIRI

-

-

-

0.5
0.5

V

Output Voltage - High Logic State
(Bus IDriver) Output, 10HIB) = 10 mAl
IReceiver Output, 10H(R) = -2.0 mAl

VOHIBI
VOHIRI

IReceiver Output, IOH(R) = -100jIlA, VCC = 5.0 V)

2.4
2.4
3.5

3.1
3.1

V
-

-

-

100
100

)1A

-100
-100

)1A

Output Disabled Leakage Current - High Logic State
IBus Driveri Output, VOH(B) = 2.4 V)
(Receiver Output, VOH(R) = 2.4 V)
Output Disabled Leakage Current - Low Logic State
(Sus Output, VOLlS) = 0.5 V)
(Receiver Output, VOLlR) = 0.5 V)

IOHLIB)

-

-

10HLIRI

-

-

10LLlS)
10LLlR)

--

-

-

-

-

Input Clamp Voltage
IDriver Enable Input IIDIDE) = -12 mAl
(Receiver Enable Input IIC(R E) = +12 mAl
(Driver Input IICm) = -12 rnA)
Output Short-Circuit Current, VCC
I Bus I Driver) Output)
(Receiver Output)

= 5.25

-1.0
-1.0
-1.0

V

-150
-75

mA

-

110

mA

-

VICIDE)
VICIRE)
VICID)

-

-

-

-

10SIB)
10SIR)

-50
-30

-

ICC

-

V 111

Power SUPP'iy Current
(VCC = 5.25 V)
(1) Only one output may be short-circuited at a time.

3-607

I

MC8T28, MC6889

SWITCHING CHARACTERISTICS (Unless otherwise noted VCC = 5.0 V and TA = 25 0 C)
Characteristic
Propagation Delay Time-Receiver (CL

= 30 pF)

Symbol

Min

Max

Unit

tPLH(R)

-

17

ns

17

tpHL(R)

= 300 pF)

Propagation Delay Time-Driver (CL

-

tPLH(O)

17

Propagation Delay Time-Enable (CL
- Receiver

= 30 pF)

- Driver Enable (CL 300 pF)

ns

17

tPHL(D)
tpZL(R)

-

tPLZ(R)

-

tpZL(D)

-

tPLZ(D)

23
18

ns

28
23

I
FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM
BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tpLH(R) AND tpHL(R)

tTHL<;;5.0ns

2.6 V
Input

o V----I
tPHlIRJ---j

1'-'-';;.;.;..-------'
Input Pulse Frequency = 10 MHz
Duty Cycle = 50%

~
I

VOH
Output

1.5 V ' \
VOL------'·~------------J

To Scope
(Input)

2.6 V

To Scope
(Input)

Receiver

En;;'bi;

T

Input

92
Receiver
Input

1N916
or Equiv.

Output

Driver
Input
Pulse

Generator

51

1.3 k

Driver
Enable
Input

3-608

30 pF

MC8T28, MC6889

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVER) OUTPUT, tpLH(D) AND tpHLlD)

tTLH

2.6 V
Input

OV----Input Pulse Frequency = 10 MHz
Duty Cycle = 50%
VOH-------,
Output
VOL----

2.6 V

2.6 V

To Scope
(I nput I

To Scope
(Output)

DrIver

Enable
Input

Dr1ver

I

30

Driver

(Bus)

1N916

Input

Output

or Equiv.

Receiver
300 pF

260

51

Input

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT, tpLZ(RE) AND tpZL(RE)

tTLH .; 5.0

ns

2.6 V ---+-j,,-~-----

___1.

Input

tPLZ(RE)
~ 3.5 V - ----+---,

r10%

OV

---1

tPZL{RE)

_--------,.

Input Pulse Frequency
Duty Cycle

c

5.0 MHz
50%

1.5 V

Output

V O L - - - -....

To Scope

OV
To Scope
(Output)

( Input)

5.0 V

240

2.4 k

Receiver

Output

Pulse

51

Generator

5.0 k

3-609

30 pF

1N916
or Equiv.

MC8T28, MC6889

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER IBUSI OUTPUT, tPLZIDEI AND tPZLIDEI

tTHL';; 5.0 ns

-----+-±-:=--------,i-

2.6 V
Input

Input Pulse Frequency = 5.0 MHz
Duty Cycle
50%

0\1

0:0

~3.5V---~

Output
VOL-----------~---------~

I

OV

To Scope
(Outputl

Driver Enable

5.0 V

Input

70

2.4 k

Driver
Input

Driver (Bus)
Pulse

51

Output

Receiver
Output

1N916

5.0 k

Receiver
Enable

300 pF

or Equ iv

Input

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs

Receiver
Outputs

Driver
Inputs

Driver
Inputs

Receiver
Enable

To Other
Drivers! Receivers

Driver
Enable

3-610

Receiver
Enable

®

MC6890

MOTOROLA
Advance InforIDation

8-BIT
MPU-BUS-COMPATIBLE
DAC

MPU-BUS-COMPATIBlE
B-BIT O-TO-A CONVERTER
The MC6890 is a self-contained, bus-compatible, 8 bit (±0.19%
accuracy) D-to-A converter system capable of interfacing directly
with 8-bit microprocessors.
Available in both commercial and military temperature ranges, this
monolithic converter contains master/slave registers to prevent
transparency to data transitions during active enable; a lasertrimmed, low-TC, 2.5 V precision bandgap reference; and high
stability, laser-trimmed, thin-film resistors for both reference input
and output span and bipolar offset control.
A reset pin provides for overriding stored data and forcing lout
to zero.
•

Direct Data Bus Link with All Popular TIL Level MPU's

•

±1 /2 LSB Nonlinearity Over Temperature

•

Fast Settling Time: 200 ns Typ

•

Internal 2.5-V Precision Laser-Trimmed Voltage Reference (May
Also Be Used Externally)

•

Minimum Enable Pulse Width: 70 ns

•

Fast Enable: 10 ns Maximum Data Hold Time
Reset Pin to Override Data

•

Output Voltage Ranges: +5, +10, +20, or ±2.5, ±5, ±1 0 Volts
Low Power: 90 mW Typ

•

+5 V and -5 V to -15 V Supplies

I
L SUFFIX
CASE 732-03

•
•

SILICON MONOLITHIC
INTEGRATED CIRCUIT

OPERATION WITH AN MPU
PIN CONNECTIONS

(LSB) DO

I

Microprocessor
19

REFOUT

Data Bus
Clock,
Control,
and
Address
Bus

Data
Bus

17

Analog Gnd

16

20 V Span

15

10 V Span

(MSB) 07

Bipolar
Offset
12

Digital Gnd

REFIN

Enable

10

MC6890

~-----i Enable

ORDERING INFORMATION
Temperature Range

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

3-611

MC6890
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Power Supply Voltage

VCC
VEE

+7.0
-18

Vdc

Digital Input Voltage, Pins 1-8, 12
Pin 9

Yin

-3.0 to +7.0
Oto +7.0

Vdc

Applied Output Voltage

V14

VEE +2.0 to
VEE +24

Vdc

Reference Amplifier Input

V18

±7.5

Vdc

Operating Temperature Range
MC6890L,
MC6890AL

TA

°c

o

to +70
-55 to +125

Storage Temperature Range
Junction Temperature

Tst9

-65 to +150

TJ

+150

°c
°c

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = -12 V, Pin 18 loadedonlyby Pin 19through 1000. Reset high, TA=Tlowto
Thigh(1) unless other w ise noted)
Symbol

Min

Digital Input Logic Levels
High Level, Logic 1
Low Level. Logic 0

VIH
VIL

2.0

-

-

-

-

0.8

Digital Input Current
Data (VIH = 3.0 V)
(VIL = 0.4 V)
Enable (VIH = 3.0 V)
(VIL = 0.4 V)
Reset (VIH = VCe!
(VIL = 0.4 V)

IIH
IlL
IIH
IlL
IIH
IlL

-

0.001
0.5
0.001
-6.5
0.001
-1.0

1.0
-10
1.0
-100
1.0
-15

!J.A
!J.A
!J.A
!J.A
!J.A
!J.A

-1.992

-2.50

mA

0.010

0.20

Characteristic

I

Full Scale Output Current -

Typ

Max

Unit
Vdc

Unipolar

10

-

Unipolar Zero Output - All Bits Off (TA = 25°C)
Output Voltage Temperature Coefficient

-

-

-1.50
-

-

Unipolar Zero
Bipolar Zero
Full Scale Range

!J.A
ppm of
FSR/oC

TCVO

-

±1.0
±5.0
±20

±2.0
±15
±50

9.961
19.922
4.980

10.061
20.122
5.030

0
0
0

±20
±40
±10

Output Voltage, Full Scale Range (See Figure 3) (TA = 25°C)
(10 V Span)
(20 V Span)
(5.0 V Span)

Vo

Output Voltage, Bipolar Zero (MSB on) (See Figure 4) (TA = 25°C)
(10VSpan)
(20 V Span)
(5.0 V Span)

Vo

DAC Output Resistance - Exclusive of Span Resistors
(TA = 25°C) (See Figure 5)

RO

1.0

5.0

Resolution

-

8.0

8.0

8.0

Bits

Nonlinearity - Relative Accuracy
(See Terminology)

NL

-

-

±0.19
(±112 LSB)

%

Vdc
9.861
19.722
4.930

mV

-

-

Differential Nonlinearity

-

Mn

Monotonicity Guaranteed

-

Differential Nonlinearity (TA = 25°C)
(See Terminology)

-

-

±0.29
(±3/4 LSB)

~o

Reference Input Resistor

RREF

3800

4900

6800

n

Reference Output Voltage (T A = 25°C)

2.470

2.500

2.530

Vdc

Reference Output Impedance (TA = 25°C) Iload = 0-3.0 mA

VREF
-

-

0.3

1.0

n

Reference Short Circuit Current (T A = 25°C)

IREF

15

30

50

mA

Reference Output Voltage Temperature Coefficient

TCVO(REF)

Power Supply Range

VCC
VEE

Power Supply Current - All Bits Low
(VCC = 5.0 V)
(VEE = -5.0 V)
(VEE = -15 V)

-

4.5
-16.5

±20

-

5.0
-12

5.5
-4.5

10
-10
-10

20
-15
-15

-

0.010
0.10

±1/10
±1/2

-

90
220

158
358

ppm 1°C
Vdc
mA

ICC
lEE
lEE
PSR

Power Supply Rejection (TA = 25°C)
To VCC (VCC = 4.5 to 5.5 V)
To VEE (VEE = -4.5 V to -16.5 V)

-

-

-

Power Dissipation - All Bits Low
For VCC = 4.5 V, VEE = -4.5 V
For VCC =5.5 V, VEE =-16.5 V

LSB

mW

Po

NOTE 1 Tlow = -55°C for MC6890A. 0° for MC6890
Thigh = +125°C for MC6890A. +70 oC for MC6890

3-612

MC6890
AC SPECIFICATIONS (VCC

=50 V

=-12 V

VEE

TA

=25°C unless otherwise noted)
Symbol

Min

Typ

Max

Unit

ts

-

200

300'

ns

Data Setup Time

tsu(D)

70

40

-

Data Hold Time

tl}(Dl

10

0

-

Characteristic
Current Settling Time
(Enable Positive Edge to ±112 LSB Output)

Pulse Widths
Enable
Reset
Propagation Delays
Enable, Low to High
Reset, High to Low
(10< 1.0J.lA)

tW(E)
tWIRl

70
100'

20

tPLH(E"j
tPHL(Fi)

-

100
250

-

-

-

ns
ns
ns

-

-

ns

"Not 100% tested, guaranteed by design

FIGURE 1 - TIMING DIAGRAM

D"'~

t~IDI

I

l-tsU(DI-

Enable

1.4 V

tW(EI--+---- "

lout

FS

-1

-------~---.... ~~~-. ;,72~;---

...\

os - - - - - - - -

FIGURE 2 -

BLOCK DIAGRAM
B7654321
~

19
REFOUT

I

~

~

4.900 kll

~

~

CD

0

8

~

Source

Double Buffered

~

Latches

12
-"

A.Gnd

n
-=

(

en
~
.....

IReferenceJ

2.5 V

(

cD

A. Gnd

9
13
-"

Current Sources,
Switches

2.450
kll

611
-5 V

14
-""

5.0 k

15

VEE

-"

5.0 k

VEE

Bipolar Offset

620
VCC

5V

617

610

Analog

Digital

Ground

Ground

to -15 V

3-613

16
20V Span

10VSpan

MC6890
TEST FIGURES
UNIPOLAR CONFIGURATIONS

BIPOLAR CONFIGURATIONS

FIGURE 3A

FIGURE 4A
R2son

19
Rl
loon

19

15
Rl
loon

MC6890
18

MC6890
18

+10 V Configuration
Latched Input Code: 11111111

-=-

±S.O V Configuration
Latched Input Code: 10000000

FIGURE 3B

I

-=-

FIGURE 4B
R2 SO n

19
Rl
lOOn

19
Rl
loon

MC6890

18

MC6890
18

+20 V Configuration
Latched Input Code: 11111111

-=-

±10 V Configuration
Latched Input Code: 10000000

FIGURE 3C

FIGURE 4C
R250n

19
Rl
lOOn

19
Rl
loon

MC6890
18

MC6890
18

+5.0 V Configuration
Latched Input Code: 11111111

FIGURE S

±2.5 V Configuration
Latched Input Code: 10000000

TEST CONFIGURATION FOR DAC OUTPUT IMPEDANCE
19

Rl

MC6890

lOOn
18

Latched Input Code: 11111111
12 V
Rout =~Iout

3-614

-=-

MC6890

TERMINOLOGY
Gain error is laser trimmed to less than ±1.0% with R 1 =
100 n (Figure 3) and can be usertrimmed to zero error with
R1 = 200 n pot.

Nonlinearity (Relative Accuracy) - Maximum output
deviation from ideal straight line connecting zero and fullscale readings, expressed as a fraction of LSB or percent
of full scale.

Bipolar Zero - Using the configuration shown in
Figure 6 with R1 = lOOn, R2 = 50 n, with the MSB on and
all other bits off, the output voltage reading compared to
analog ground is expressed as a percentage of the fullscale range. Offset voltage of the output op amp must be
nulled. Bipolar Zero error is laser trimmed to less than
0.20% andcan be usertrimmedto zero with R2= 1
pot.

Differential Nonlinearity - Maximum deviation in the
readings of any two adjacent input bit codes from the ideal
LSB step, expressed in fractions of LSB or percentage of
full scale. A differential nonlinearity value greater than
1 LSB may lead to non-monotonic operation.

oon

Monotonicity - For every increase in the input digital
word, the output current either remains the same or
increases. The MC6890 is guaranteed to be monotonic
over temperature.

Temperature Coefficients - (Unipolar zero, Bipolar
zero, Gain and Reference Output). The maximum deviation
ofthe particular parameter over the specified temperature
range, divided by the temperature range, expressed in
parts per million of Full Scale Range per degree C.

Settling Time - The elapsed time from the Enable
positive transition until the output has settled within an
error band about its final value.
The worst case switching condition occurs when all bits
are latched "on," which corresponds to a low-to-high
transition for all bits. This time is typically 200 ns for the
current output to settle to within ±1 12 LSB for 8 bit
accuracy. These times apply when the output swing is
limited to a small «0.5 V) swing and the external output
capacitance is under 10 pF.

Power Supply Rejection - The change in full scale
current caused by the specified change in VEE or VCC is
expressed in LSB's.
Reset Function - The MC6890 has a Reset pin (9) that
will force the DAC's registers, and therefore the DAC
output current, to zero. This input is active low and should
not occur Simultaneously with an active Enable signal
although no harm would result to the converter. The
power dissipation increases slightly during Reset low.
Reset should not be allowed to become more negative
than ground.

Gain Error - The difference between the actual full
scale range and the ideal full scale range. Based on a 0 to
10 V output configuration, the ideal FSR is 255 x 10 V =
9.961 V.
256

FIGURE 6 -

MC6890 IN TYPICAL BIPOLAR ±2.5 V OPERATION

16
18

4.900kn

R1
0-200 n

lout

19

VO±2.5 V

~

MC34001B

13

R2
0-100 n

07

06

1

1

1
1
0
0
0

1
0
1
0
0

04

03

02

01

DO

1

1

1

1
0
1
0
0

1
0
1
0
0

1

1
1
0

1
1
0
1
0
0

1
0
0
1
1
0

05

0
1

1

0
0

0
0

3·615

Vo (Volts)

R2 =60 n
+ 2.490
+ 2.470
+0.010
-0.010
-2.470
-2.490

R2 = 50 n
+ 2.480
+ 2.460
+ 0.000
- 0.020
- 2.480
- 2.500

I

MC6890

TYPICAL PERFORMANCE CURVES

FIGURE 7 - REFERENCE VOLTAGE versus
EXTERNAL LOAD CURRENT·

~

.....

f.!)

~

-

2.500

>

TA
~

r-- r---

~

~ 2.490

I

1

25 0 c

--r'I

~ 2.480

'"

i

2.470

2.460

\
o

5.0

10

15

25

20

30

35

IREF. REFERENCE OUTPUT CURRENT (rnA)
·External load current is in addition to Reference Input
Current (Pin 18) of 01 A converter.

FIGURE 8 - DIGITAL INPUT CHARACTERISTICS
1.0

Vcc

«

~

-- --r

-1.0 _

~

z

a::
a::

=5.0 V

-2.0

-

Data Inputs

~ f..--"

TA

Reset

=25

0

::l

u

~

-3.0

::l

'"
~
~

i3
is

-4.0

./

-5.0

VEnable

-60
-7.0

-0.2

1/
-0.1

1.0

2.0

3.0

4.0

DIGITAL INPUT LOGIC LEVELS (VOLTS)

3·616

5.0

3C

n
en
CD

FIGURE 9 - TYPICAL APPLICATION OF THE MC6890 IN A MC6800 SERIES MPU SYSTEM

Analog Power
Supplies

Digital
Power Supply
Gnd

U)
Q

+5.0 V

Gnd +5.0 V -5 Vto-15 V

Optional VCC Kelvin Connection
in Absence of +5.0 V Analog Supply

~---------------Digital
System
Ground

0.1 ",F

Kelvin Ground Connection

0.1 ",F
0.1 ",F
10

......J...-

VSS

111

Digital
Gnd

VCC

..

(.,)

0>
-.&.

.......

20

*Note: Bypass
capacitor leads should
be short

MC6800
MC68AOO
MC68BOO
MC6802
etc.

Reset

150n

n

">--+--0

lOOn
SN74LS133
Mem~
<1>2

18 1REFIN
12

VMA

.I. 1.0",F
Address Bus

Data Bus

III

Vout
±5.0V

®

MC68120
MC68121

MOTOROLA

Advance Information
HMOS
INTELLIGENT PERIPHERAL CONTROLLER

I

The MC68120/MC68121 Intelligent Peripheral Controller (IPC) is a
general purpose, mask programmable peripheral controller. The IPC
provides the interface between an M68000 or M6800 Family
microprocessor and the final peripheral devices through a system bus
and control lines. System bus data is transferred to and from the IPC via
dual-port RAM while the software utilizes the semaphore registers to
control RAM tasking or any other shared resource. Multiple operating
modes range from a single chip mode with 21 1/0 lines and 2 control
lines to an expanded mode supporting an address space of 64K bytes.
The MC68120 has 2K bytes of on-chip ROM to make full use of all
operating modes. The MC68121 utilizes only the expanded address
modes, due to the absence of on-chip ROM.
A serial communications interface, 16-bit timer, dual-ported RAM
and semaphore registers are available for use by the IPC in all operating
modes.
• System Bus Compatible with the Asynchronous M68000 Family
• System Bus Compatible with the MC6809 and Other M6800 Family
Processorsl Peripherals
• Local Bus Allows Interface with all M6800 Peripherals
• MC6801 Source and Object Code Compatible
• Upward Compatible with MC6800 Source and Object Code
• 2048 Bytes of ROM (MC68120 Only)
• 128 Bytes of Dual-Ported RAM
• Multiple Operation Modes Ranging from Single Chip to Expanded,
with 64K Byte Address Space
• Six Shared Semaphore Registers
• 21 Parallel 1/0 Lines and 2 Handshake Lines (5110 Lines on
MC68121)
•
•
•
•
•
•
•

Serial Communications Interface (SCI)
16-Bit Three-Function Timer
8-Bit CPU and Internal Bus
Haiti Bus Available Capability Control
8 x 8 Multiply Instruction
TTL Compatible Inputs and Outputs
External and Internal Interrupts

GENERIC INFORMATION
(T A =O°C to 70°C)
Package Type
Ceramic
L Suffix

Frequency (MHz)
1.0
1.0
1.25
1.25

Generic Number
MC68120L 1 (Unicorn ROM)
MC68121L
MC68120L 1-1 (Unicorn ROM)
MC68121L-l

This document contains information on a new product Specifications and information herein
are subject to change without notice

(HIGH-DENSITY N-CHANNEL
SI LICON-GATE)

INTELLIGENT PERIPHERAL
CONTROLLER

~

L SUFFIX

CERAMIC PACKAGE
CASE 740

PIN ASSIGNMENT
VSS
IRQl
HALTI
BAINMI
E

RESET
P24
P23
P22

SR/W

P2i

OTACK

P20

CS

SC2

SA7

SCi

SA6

P30

SA5

P31

SA4

P32

VCC

P33

SA3

P34

SA2

P35

SAl

P36

SAO

P37

SOO

P40

SOl

P41

S02

P42

S03

P43

S04

P44

S05

P45

S06

P46

S07

P47

MC68120· MC68121

MC68120/MC68121 INTELLIGENT PERIPHERAL CONTROLLER -

o

N

~NC')<:t

CLCLCLCLCL

SR/W

I-~--4I~-------I HALT iBA/f\JMI

signals. Figure 22 shows the appropriate timing diagram for
Halt/BA with the recommended circuit. The pUliup resistor
shown in the circuit maintains a high logic level when HALT
is not active. During a positive half-cycle of E, pin 3 is an input sampled to determine if the Halt State is requested (active low). During the negative half cycle of E, the BA signal is
output through pin 3. After the request for Halt State signal
is detected and the processor completes its current instruction, the CPU is halted and the active low BA signal is output
through pin 3 during the negative half cycle of E. The local
bus is then available for other devices to utilize until the Halt
State signal has returned to a high level, thus allowing the

IPC back on the local bus. During the Halt State, the R/Wis
high, and the address bus displays the address of the next instruction.
When single instruction operation is desired, in program
debug for instance, it is advantageous to single step through
instructions. After SA goes low, HALT must be brought
high for one E-cycle and returned low again to single step
through instructions. Figure 22 illustrates the timing involved
while single stepping through a single byte, two bus cycle instruction, such as CLRA.
BA is not output in response to the Wait instruction. If interrupts are to be utilized in removing the processor from a

FIGURE 22 - HALT/SA TIMING DIAGRAM

VIL

InlOut

I

liAl

L.._ _ _ _ _ _ _...J

R/W~
Add/Data

Note'

3-632

~

_ _-----,I

MC68120 • MC68121

Wait State while in the Halt/BA mode then, IRQ1 and IRQ2
are the only interrupts which may do so; therefore, their
masks must be cleared before entering the Wait State.

Expanded Non-Multiplexed Mode - In this mode, both
SC1 and SC2 are configured as outputs. SCl functions as
Input/Output Select (lOS) and is asserted (active-low) only
when addresses $0100 through $01FF are accessed. SC2 is
configured as Rilfii and is used to control the direction of
local data bus transfers. An MPU read is enabled when R/W
and E are high.

MASKABLE INTERRUPT REQUEST 1 -

IRQl
This level-sensitive input can be used to request an interrupt sequence. The IPC will complete the current instruction
before it responds to the request. If the interrupt mask bit
(I-bit) in the Condition Code Register is clear, the IPC will
begin an interrupt sequence: a vector is fetched from $FFF8
and $FFF9, transferred to the Program Counter, and instruction execution is continued at the new location. This is explained in greater detail in the Interrupt Section.
IRQ1 typically requires an external resistor (3K to 10K
depending on external devices drive capability) to V CC for
wire-OR applications. IRQ1 has no internal pullup resistor.

Expanded Multiplexed Modes - In these modes, SC1 is
configured as an input and SC2 is configured as an output.
In the expanded multiplexed modes, the IPC has the ability
to access a 64K byte address space. SC1 functions as an input. Address Strobe, which controls demultiplexing and
enabling of the eight least significant addresses and the data
buses.
By using a transparent latch such as an SN74LS373 or
MC6882, Address Strobe (AS) can also be used to demultiplex the two buses external to the IPC. (See Figure 23.)
SC2 provides the local Data Bus control Signal called
Read/Write (R/Wl. SC2 is configured as RlWand is used to
control the direction of local data bus transfers. An MPU
read is enabled when R/W and E are high.

STROBE CONTROL 1 AND 2 -

SCl and SC2
The functions of SC1 and SC2 depend on the operating
mode. SC1 is configured as an input in all modes except
the Expanded Non-Multiplexed Mode, whereas SC2 is always an output. SC1 and SC2 can drive one Schottky load
and90pF.

SYSTEM BUS INTERFACE

Single Chip Modes - In these modes, SC1 and SC2 are
configured as an input and output, respectively, and both
function as Port 3 control lines. SC1 functions as an input
strobe (lS3) and can be used to indicate that Port 3 input
data is ready or output data has been accepted. Three options associated with IS3 are controlled by the Control and
Status Register for Port 3 and are discussed in the Port 3
description.
SC2 is configured as an output strobe (OS3) and can be
used to strobe output data or acknowledge input data for
Port 3. It is controlled by Output Strobe Select (OSS) in the
Port 3 Control and Status Register. The strobe is generated
by a read (OSS = Q) or write (OSS = 1) to the Port 3 Data
Register. OS3 timing is shown in Figure 6.

Port 1 is a mode-independent 8-bit data port which permits the external system bus to access the dual-ported RAM
and semaphore registers either asynchronously or synchronously with respect to the E clock. In addition to the
eight data lines (SOO-S07), eight address (SAO-SA7) and
three control lines (SR/W, CS, OTACK) are used to access
the dual-ported RAM and semaphore registers.
Port 1 Data Lines (SOO-S07) - These data lines are bidirectional data lines which allow data transfer between the
dual-ported RAM or the semaphore registers, and the
system bus. The data bus output drivers are three-state
devices which remain in the high-impedance state except

FIGURE 23 - TYPICAL LATCH ARRANGEMENT
GNO

AS

J

EN/G
01

I

OC

01

SN74S373

Port 3
Address/ Data

ITypical)

Addres~:

AO-A7

...
08

08

,
Data: 00-07

3-633

I

MC68120· MC68121

during a read of the IPC dual-ported RAM or semaphore
registers by the system processor.
System Address Lines (SAO-SA7) - The address lines
together with the Chip Select Signal allow any of the 128
bytes of RAM or six semaphore registers to be uniquely
selected from the system bus. The address lines must be
valid before the CS signal goes low for the asynchronous interface and valid before the E signal goes high for the synchronous interface. The system interface must be deselected
between reads or between writes for the asynchronous
operation.

I

System ReadlWrite (SR/W) - This signal is generated by
the system bus to control the direction of data trans~r on
the data bus. With the IPC selected, a low on the SRIW line
enables the input buffers, and data is transferred from the
system processor to the IPC. When SRIW is high and the
chip is selected, the data output buffers are turned on and
data is transferred from the IPC to the system bus.
Chip Select (CS) - This Signal is a TTL compatible input
signal, used to activate the system bus interface and allows
transfer of data between the IPC and the system processor
during synchronous or asynchronous accesses. CS provides
the synchronizing Signal for the Semaphore registers during
access by the system bus.

Inputs on P20, P21 and P22 determine the operating mode
which is latched into the Program Control Register on the
positive edge of RES ET. The mode may be read from the
Port 2 Data Register (PC2 is latched from pin 45).
Port 2 also provides an interface for the Serial Communications Interface and Timer. Bit 1, if configured as an
output, is dedicated to the Timer Output Compare function
and cannot be used to provide output from the Port 2 Data
Register.
PORT 3 -

Single Chip Modes - In these modes, Port 3 is an 8-bit
I/O port where each line is configured by the Port 3 Data
Direction Register. Associated with Port 3 are two lines, IS3
and OS3, which can be used to control Port 3 data transfers.
Three Port 3 options, controlled by the Port 3 Control and
Status Register and available only in the Single Chip Modes
are: 1) Port 3 input data can be latched using TS3 as a control
signal, 2) OS3 can be generated by either an IPC read or
write to the Port 3 Data Register, and 3) an iR01 interrupt
can be enabled by an IS3 negative edge. Port 3 latch timing
is shown in Figure 7.
PORT 3 CONTROL AND STATUS REGISTER

Data Transfer Acknowledge (DTACK) - This bidirectional
control line is used to determine synchronous or asynchronous system bus accesses and to provide the data
acknowledge Signal for asynchronous data transfers.
As an input, it is sampled on the falling edge of CS by the
IPC to determine if the system bus is being accessed synchronously or asynchronously with respect to the E clock.
If DTACK is low when sampled, the system bus is synchronous and data will be transferred during E high as shown
in Figure 13.
If DT ACK is high when sampled, the system bus is asynchronous. In this mode DT ACK becomes an output that is
asserted low when data is on the bus during a system read or
when a data transfer is completed during a system write.
Refer to Figures 9 through 12.
DT ACK requires an external pullup resistor when the
system bus is run asynchronously since it is then a bidirectional handshake line for information transfer on the system
data bus.
PORT 2 -

6

PC2

4

I PCl IPCO I P241

3

P23

2

1

I P22 I P2l I P20

$03

2

0

Bits 0-2 Not used.
LATCH ENABLE. This bit controls the input latch
Bit 3
for Port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a read
of the Port 3 Data Register. LATCH ENABLE is
cleared by Reset.
Bit 4

OSS (Output Strobe Select). This bit determines
whether OS3 will be generated by a read or write of
the Port 3 Data Register. When clear, the strobe is
generated by a read; when set, it is generated by a
write. OSS is cleared by Reset.

Bit 5
Bit 6

Not used.
1S3-IRQ1 ENABLE. When set, an TRQj interrupt
will be enabled whenever IS3 FLAG is set; when
clear, the interrupt is inhibited. This bit is cleared by
Reset.
TS3 FLAG. This read-only status bit is set by an IS3
negative edge. It is cleared by a read of the Port 3
Control and Status Register (with IS3 FLAG set)
followed by a read or write to the Port 3 Data
Register or by Reset.

P20-P24

PORT 2 DATA REGISTER

3

$OF

Port 2 is a mode independent 5-bit 1/0 port where each
line is configured by its Data Direction Register. During
reset, all lines are configured as inputs. The TTL compatible
three-state output buffers can drive one Schottky TTL load
and 30 pF, or CMOS devices using external pull up resistors.
P20, P21 and P22 must always be connected to provide the
operating mode.

6

P30-P37

Port 3 can be configured as an 1/0 port, a bi-directional
8-bit data bus, or a multiplexed addressl data bus depending
upon the operating mode. The TTL compatible three-state
output buffers can drive one Schottky TTL load and 90 pF.

Bit 7

Expanded Non-Multiplexed Mode - In this mode, Port 3
is configured as a bi-directional data bus (DO-D7l. The direction of data transfers is controlled by R/W (SC2). Data
transfers are clocked by E (Enable).

3-634

MC68120 • MC68121

pullup resistors to r(lore than 5 volts, however, cannot be
used.

Expanded Multiplexed Modes - In these modes, Port 3 is
configured as a time-multiplexed address (AO-A]) and data
bus (DO-D7l. Address Strobe (AS) must be input on SC1,
and can be used externally to de-multiplex the two buses.
Port 3 is held in a high-impedance state between valid address and data to prevent potential bus conflicts.

Expanded Non-Multiplexed Mode - In this mode, Port 4
is configured from reset as an 8-bit input port, where the
Data Direction Register can be written, to provide any or all
of address lines AO-A7. Internal pullup resistors are intended
to pull the lines high until the Data Direction Register is configured.

PORT 4 - P40-P47
Port 4 is configured as 8-bit liD port, as address outputs,
or as data inputs depending on the operating mode. Port 4
can drive one Schottky TTL load and 90 pF and is the only
port with internal pullup resistors.

Expanded Multiplexed Mode - In all these modes except
Mode 6, Port 4 functions as half of the address bus and provides A8 to A 15. In Mode 6, the port is configured from reset
as an 8-bit parallel input port; the Port 4 Data-Direction
Register must be written to provide any or all of address
lines, A8 to A 15. Internal pullup resistors are intended to pull
the lines high until the Data Direction Register is configured
(bit 0 controls AS, etc.).

Single Chip Modes - In these modes, Port 4 functions as
an 8-bit liD port where each line is configured by the Port 4
Data Direction Register. Internal pullup resistors allow the
port to directly interface with CMOS at 5 volt levels. External

OPERATING MODES
The IPC provides eight different operating modes which
are selectable by hardware programming and referred to as
Modes 0 through 7. The operating mode controls the
memory map, configuration of Port 3, Port 4, SC1 and SC2
and the address location of the interrupt vectors.

Single Chip Modes (4, 7) - In Single Chip Mode, three of
the four IPC ports are configured as parallel inputloutput
data ports, as shown in Figure 25. The IPC functions as a
complete microcomputer in these two modes without external address or data buses. A maximum of 21 liD lines and
two Port 3 control lines are provided.
In Single Chip Test Mode (4), the RAM responds to addresses $XX80 (X = don't care) through $XXFF and the ROM
is removed from the internal address map. A test program
must first be loaded into the RAM using Modes 0, 1, 2, or 6.
If the IPC is reset and then programmed into Mode 4, execution will begin at $XXFE:XXFF. Mode 5 can be irreversibly
entered from Mode 4 without going through reset by setting
bit 5 of the Port 2 Data Register. This mode is used primarily
to test Port 3 and 4 in the Single Chip and Non-Multiplexed
Modes.

FUNDAMENTAL MODES
The eight modes of the IPC can be grouped into three fundamental modes which refer to the type of bus it supports:
Single Chip, Expanded Non-Multiplexed, and Expanded
Multiplexed. Single Chip includes Modes 4 and 7, Expanded
Non-Multiplexed is Mode 5 and the remaining five are Expanded Multiplexed modes. A system utilizing three
MC68120's, one in each of the fundamental operating
modes, is shown in Figure 24. Table 6 summarizes the
characteristics of the operating modes.

TABLE 6 -

SUMMARY OF IPC OPERATING MODES

Common to all Modes:
System Bus Interface
Reserved Register Area
6 Semaphore Registers
I/O Port 2
Programmable Timer
Serial Communications Interface
128 bytes of Dual Ported RAM
Single Chip Mode*
2048 Bytes of ROM (Internal)
Port 3 is a Parallel I/O Port with Two Control Lines
Port 4 is a Parallel I/O Port
SCl is Input Strobe 3 (lS31
SC2 is Output Strobe 3 (OS31
Expanded Non-Multiplexed Mode*
2048 Bytes of ROM (Internall
256 Bytes of External Memory Space
Port 3 is an 8-Bit Data Bus
Port 4 is an Address Bus
SCl is Input/Output Select (IOSI
SC2 is Read/Write (R/WI

Expanded Multiplexed Modes
Four Memory Space Options (64K Address Spacel:
(11 MOOS Compatible
(21 No ROM
(31 External Vector Space
(41 ROM with Partial Address Bus*
External Memory Space Accessed Through:
Port 3 as a Multiplexed Address/Data Bus
Port 4 as an Address Bus (Highl
SCl is Address Strobe Bus (AS) Input
SC2 is Read/Write (R/WI
Test Modes
Expanded Multiplexed Test Mode
May be Used to Test RAM and ROM*
Single Chip and Non-Multiplexed Test Mode*
May be Used to Test Ports 3 and 4 as I/O Ports

* MC68120 only

3-635

I

MC68120· MC68121

FIGURE 24 - IPC FUNDAMENTAL OPERATING MODES

68000
6809
6801
6802

6808
6803
6800

RAM

Single Chip Mode

ROM

II

SSDA
ADLC
CRTC

Expanded
Non-Multiplexed
Mode

System Bus

Expanded
Multiplexed
Mode

ROM

Local
Bus
RAM

PIA
ACIA
GPIA
PTM

SSDA
ADLC
CRTC

Expanded-Multiplexed Modes (0, 1,2,3,6) - In the Expanded Multiplexed Modes, the IPC has the ability to access
a 64K-byte memory space. Port 3 functions as a timemultiplexed address/data bus with address valid on the
negative edge of Address Strobe (AS) and the data bus valid
while E is high .In Modes 0 to 3, Port 4 provides address lines
AS-A 15. However, in Mode 6, Port 4 can provide any subset
of AS to A 15 while retaining the remainder as input lines.
Writing 1's to the desired bits in the Data Direction Register
(DDR) will output the corresponding address lines while the
remaining bits will remain inputs (as configured from reset or
from O's written to the DDRl. Internal pull up resistors are
provided to pull Port 4 lines high until software configures
the port. Initialization of Port 4 in Mode six must be done to
obtain any upper address lines externally.

Expanded Non-Multiplexed Mode (5) - A modest amount
of external memory space is provided in the Expanded NonMultiplexed Mode while retaining significant on-chip
resources. Port 3 functions as an S-bit bi-directional data bus
and Port 4 is configured as an input data port. Any combination of AO to A7 may be provided while retaining the remainder as input data lines. Any combination of the eight
least-significant address lines may be obtained by writing to
the Port 4 Data Direction Register. Internal pullup resistors
are provided to pull Port 4 lines high until it is configured.
Figure 26 illustrates the external resources available in the
Expanded Non-Multiplexed Mode. The IPC interfaces directly with M6800 Family parts and can access 256 bytes of external address space at $100 through $1 FF. lOS provides an
address decode of external memory ($100-$1 FF) and may be
used as an address or chip select line.

3-636

MC68120· MC68121

FIGURE 25 -

SINGLE CHIP MODE

VCC

MC68120

RESET

HALT/SA/NMI
IR01

Port 3
8 I/O Lines

8 System
Address Lines
Port 1
8 System
Data Lines

System
Bus

SR/W

CS
Port 4
8110 Lines

II

DTACK
Port 2
5 I/O Lines
Serial 110,
16-Bit Timer

-

VSS

FIGURE 26 -

EXPANDED NON-MULTIPLEXED MODE
VCC

RESET

MC68120

HALT/SA/NMI
IR01

Port 3
8 Data Lines

8 System
Address Lines
Port 1
8 System
Data Lines

R/W

lOS

SR/W
CS

Port 4
8 Address Lines

DTACK
Port 2
5 I/O Lines
Serial 110,
16-Bit Timer

VSS

3-637

System
Bus

MC68120· MC68121

after the positive edge of RESET. In addition, the internal
and external data buses are connected together so there
must be no memory map overlap (to avoid potential bus conflicts). Mode 0 is used primarily to verify the ROM pattern
and monitor the internal data bus with automated test equipment.

Figure 27 depicts the external resources available in the
Expanded-Multiplexed Modes. Address Strobe can be used
to control a transparent D-type latch to capture addresses
AO-A7, as shown in Figure 23. This allows Port 3 to function
as a Data Bus when E is high.
In Mode 0, the reset vector is external at $BFFE and $BFFF
FIGURE 27 -

EXPANDED MULTIPLEXED MODE
VCC

RESET

HALT/BA/NMI

MC68120/
MC68121

IRQ1

Port 3
8 Lines Multiplexed
Addressl Data

I

8 System
Address Lines
Port 1
8 System
Data Lines

Rlw

AS

System
Bus

SR/W
CS

Port 4
8 Address Lines

DTACK
Port 2
5 I/O Lines
Serial I/O,
16-Bit Timer

VSS

MODE PROGRAMMING
The operating mode is programmed by the levels asserted
on P22, P2l, and P20 during the positive edge of RESET.
These are latched into PC2, PC1, and PCO of the program
control register. The operating mode may be read from the
Port 2 Data Register and programming levels and timing
must be met as shown in Figure 28 and Table 7. Any mode
may be entered from either Mode a or Mode 4 without going
through reset by writing the appropriate bits to the port 2
data register. A brief outline of the operating. modes is
shown in Table 8.
.
Circuitry to provide the programming levels is primarily
dependent on the normal system use of the three pins. If

FIGURE 28 -

configured as outputs, the circuit shown in Figure 29 may be
used; otherwise, the three-state buffers can be used to provide isolation while programming the mode.

MEMORY MAPS
The IPC provides up to 64K bytes of address space
depending upon the operating mode. A memory map for
each operating mode is shown in Figure 30. In Modes 1Rand
6R, the "R" means the ROM has been relocated by a mask
option. The first 32 locations of each map are reserved for
the IPC internal register area, as shown in Table 9, with exceptions as indicated.

MODE PROGRAMMING TIMING
See Figure 29
for Diode
VMPDD

(P20, P21, P22)
Mode Inputs
(P20. P21. P22)

RESET

3-638

VMPL
Mode Latch Level

MC68120 • MC68121

TABLE 7 -

MODE PROGRAMMING SPECIFICATIONS (See Figure 30)
Unit

Symbol

Min

Typ

Max

Mode Programming Input Voltage Low

VMPL

-

-

1.8

V

Mode Programming Input Voltage High

VMPH

4.0

-

-

V

Mode Programming Diode Differential (if Diodes are Used)

VMPDD

0.6

PWRSTL

3.0

-

-

RESET Low Pulse Width

-

E-Cycles

Mode Programming Setup Time

tMPS

2.0

-

-

E-Cycles

Mode Programming Hold Time
RESET Rise Time;;: 1 P.s
RESET Rise Time< 1 P.s

tMPH

0
100

-

-

ns

Characteristic

TABLE 8 -

Mode

Pin 45
P22
PC2

Pin 44
P21
PC1

Pin 43
P20
PCO

ROM

-

V

MODE SELECTION SUMMARY

RAM

Interrupt
Vectors

Bus
Mode

Operating
Mode

7

H

Y

H

I

I

I

6

H

H

L

I

I

I

I
MUX(5,6)

Single Chip
Multiplexed/ Partial Decode(5)

5

H

L

H

L

L

I
1(1)

NMUX(5,6)

H

I
1(2)

I

4

I

3

L

H

H

E

1(7)

E

I
MUX(4)

2

L

H

L

E

I

E

MUX(4)

Multiplexed/RAM(4)

1

L

L

H

I

I

MUX(4)

Multiplexed/RAM and ROM(4)

0

L

L

L

I

I

E
E(3)

MUX(4)

Multiplexed Test(4)

Legend:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"

Non-Multiplexed/ Partial Decode(5)
Single Chip Test
Multiplexed/ RAM(4)

Notes:
(1) Internal RAM is addressed at $XX80
(2) Internal ROM is disabled
(3) Interrupt vectors externally located at $BFFO-$BFFF
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1,2, and 3
(5) Addresses associated with Port 3 are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register
(7) Internal RAM and registers located at $COXX (for use with MDOS)

FIGURE 29 - TYPICAL MODE PROGRAMMING CIRCUIT
V C

R2

RESET

Rl

Rl

Rl

MC68120/
MC68121

r--'

~!-_....L........_-+-_+-_+-___---,,48:.t RESET

P20

43 P20 (PCo)

P21

44 P21 (PC1)

P22

I

L __

I

45 P22 (PC2)

J

Optional
Three-State
Buffers
MC14066B

Notes:
1. Mode 7 as shown
2. R2·C = Reset time constant
3. Rl = 10 k (typical)
4. D= lN914, lN4001 (typical)

3-639

I

MC68120 • MC68121

FIGURE 30- IPC MEMORY MAPS

MC68120
Mode
Multiplexed Test Mode

o

Internal Registers
$001 F
External Memory Space
$0080
Internal RAM
$OOFF

I

External Memory Space

$BFFO

External Interrupt Vectors(2)

$BFFF

Notes:
1i Excludes the following addresses which may be
used externally: $04, $05, $06, $07 and $OF.
2) The interrupt vectors are externally located at
$BFFO-$BFFF.
3) There must be no overlapping of internal and external memory spaces to avoid driving the data
bus with more than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal ROM
using an external RESET vector
5) MC68120 only.

External Memory Space

$F800
Internal ROM(5)

MC68120
Mode

1

Multiplexed/RAM and ROM

$0000""'''''''''''''''''''1'10

Internal Registers( 1)
External Memory Space
Notes:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07 and $OF.
2) Internal ROM addresses $FFFO to $FFFF are not
usable.

Internal RAM

External Memory Space

InternaL ROM

$FFFF'--_ _ _~

External Interrupt Vectors(2)

3-640

MC68120· MC68121

FIGURE 30 - IPC MEMORY MAPS (CONTINUEOI
MC68120/
MC68121
Mode

2

MC68120/
MC68121
Mode

3

Multiplexed/RAM, MDOS Compatible (1)
Multiplexed/ RAM

$0000----...
Internal Registers (1 )
External Memory Space

External Memory Space
Internal RAM

Internal Registers (2 )
External Memory Space
External Memory Space
Internal RAM
External Memory Space
$FFFO~---~<

$FFFO .....----t<
$FFFF "-_ _ _-'J

$FFFF L-_ _ _..I.J

External Interrupt Vectors

Notes:
1) Relocating the internal registers and the internal
RAM to high memory allows processor to run
MDOS.
2) Excludes the following addresses which may be
used externally: $COO4, $C005, $COO6, $COO7,
and $COOF.

Notes:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

MC68120
Mode

External Interrupt Vectors

MC68120
Mode

4

5

Non-Multiplexed/Partial Decode (2) (3)

Single Chip Test (2 )

$000011

)Ir""'>""""""""'"

$=~} Internal Registers (5 )

~lF

I .....
$01 FF"--..--..1
Unusablel1 )14)

$XX80

(3

$F~~)lnternal

$FFFF~

)_,.....,t..,-.,-,.... } Internal RAM(4)

$XXFF

Internal Interrupt Vectors

ROM

'''''"'''"''''"P' V,,,o,"

Notes·
1) Excludes the following addresses which may not
be used externally: $04, $06, and $OF Ino lOS).
2) This mode may be entered without going
through Reset by using Mode 4 and subsequently writing a "1" into bit 5 (peo) of Port 2 Data Register.
3) Address lines AO to A7 will not contain addresses
until the Data Direction Register for Port 4 has
been written with ''1's'' in the appropriate bits.
These address lines will assert "1 's" until made
outputs by writing the Data Direction Register.

Notes:
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a "1" into bit 5 (peo)
of Port 2 Data Register.
3) Addresses A8 to A15 are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
5) MPU Read of Port 3 Data Direction Register will
access Port 3 Data Register instead.

3-641

I

MC68120 • MC68121

FIGURE 30 -

MC68120
Mode

IPC MEMORY MAPS (CONCLUDED)

6

Multiplexed/ Partial Decode

$0000 ~_"'7""""'''''''''

Internal Registers(1)(2)

$OOlF ..............""""-""'-'11<:
External Memory Space
$OOSO ...,,.....,...,....,......1<

Notes:
1) Excludes the following addresses which may be
used externally: $04, $06, $OF.
2) Address lines AS-A 15 will not contain addresses
until the Data Direction Register for Port 4 has
been written with ''1's'' in the appropriate bits
These address lines will assert "l's" until made
outputs by writing the Data Direction Register

Internal RAM
$OOFF .....................~I<

I

External Memory Space

$FSOO

.,....,,......,....,....,,....,...K
Internal ROM

$FFFF ......~........~_J

Internal Interrupt Vectors

MC68120
Mode

7

Single Chip

$OOOO~} Internal

::~}Internal

$OOFFT

Registers( 1)

RAM
Notes:
1) MPU reads of Port 3's Data Direction Register
will access Port 3's Data Register instead.

Unusable

Internal ROM
}

Internal Interrupt Vectors

,."",.~~'-"~

3-642

MC68120· MC68121

TABLE 9 Register

Reserved
Port 2 Data Direction Register* * *
Reserved
Port 2 Data Register
Port
Port
Port
Port

3
4
3
4

Data
Data
Data
Data

INTERNAL REGISTER AREA

Address * * * *
( Hexadecimal)

00

SCI Rate and Mode Control Register
Transmit/ Receive Control and Status Register
SCI Receive Data Register
SCI Transmit Data Register

01
02
03
04*
05* *
06*
07* *

Direction Register* * *
Direction Register* * *
Register
Register

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)

08
09
OA
OB

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register

OC
00
OE
OF*

Register

Function Control Register
Counter Alternate Address (High Byte)
Counter Alternate Address (Low Byte)
Semaphore 1
Semaphore 2
Semaphore 3
Semaphore 4
Semaphore 5
Semaphore 6
Reserved

Address * * * *
( Hexadecimal)

10
11
12
13
14
15
16
17
18
19
lA
lB
lC
lD-1F

***l=Output,O=lnput
* * * *These addresses relocated at $eOOO-$COl F in Mode 3.

* These external addresses in Modes 0, 1, 2, 3, 5, 6 cannot be accessed in Mode 5 .(no lOS),
* * These are external addresses in Modes 0, 1, 2, 3

INTERRUPTS
The IPC supports two types of interrupt requests:
Maskable and Non-Maskable. A Non-Maskable Interrupt
(NMI) is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are controlled by the Condition Code Register I-bit and by individual
enable bits. The I-bit controls all maskable interrupts. Of the
maskable interrupts, there are two types: TROT and IRQ2.
The Programmable Timer and Serial Communications Interface use an internal I RQ2 interrupt line, as -shown in the
block diagram of the IPC. External devices (and IS3) use
!RN. An IRQl interrupt is serviced before an IRQ2 interrupt
if both are pending.
All IRQ2 interrupts use hardware prioritized vectors. The

TABLE 10 -

single SCI interrupt and three timer interrupts are serviced in
a prioritized order where each is vectored to a separate location. All IPC vector locations are shown in Table 10, from
highest (top) to lowest (bottom) priority.
The interrupt flowchart is depicted in Figure 31. The Program Counter, Index Register, Accumulator A, Accumulator
B, and Condition Code Register are pushed to the stack. The
I-bit is set to inhibit maskable interrupts and a vector is
fetched corresponding to the current highest priority interrupt. The vector is transferred to the Program Counter and
instruction execution is resumed. The general interrupt timing sequence is shown in Figure 32. The Interrupt HALT / BA
timing is illustrated in Figure 21 and 22.

MCU VECTOR LOCATIONS *

MSB

LSB

$FFFE

FFFF

RESET* *

Interrupt

NMI

FFFC

FFFD

FFFA

FFFB

Software Interrupt (SWI)

FFF8

FFF9

IRQl (or IS3)

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFFl

SCI (RDRF+ORFE+TDRE)

*These locations are relocated at $BFFO-$BFFF In Mode 0
* * Highest priority

3-643

II

•
FIGURE 31 -

s:

INTERRUPT FLOWCHART

(")
Q)
Q)
~

N

o

i:
(")
Q)
Q)
~

N

~

U)

c:»
~
~

SCI

= TIE-TDRE + RIE-(RORF + ORFEI

Vector ---- PC
Modes 1-7

Mode 0
NMI

BFFC-BFFO

FFFC-FFFD Non-Maskable Interrupt

SWI

BFFA-BFFB

FFFA-FFFB Software Interrupt

IRQ1

BFF8-BFF9

FFF8-FFF9 Maskable Interrupt Request 1

ICF

BFF6-BFF7

FFF6-FFF7 Input Capture Interrupt

OCF

BFF4-BFF5

FFF4-FFF5 Output Compare Interrupt

TOF

BFF2-BFF3

FFF2-FFF3 Timer Overflow Interrupt

SCI

BFFO-BFF1

FFFO-FFF1
A

SCI Interrupt (TORE + RORF + ORFEI

MC68120· MC68121

FIGURE 32 - INTERRUPT SEQUENCE

I

Last Instructlon~

NMI or IR02

Cycle
#1

#3

#2

#4

#5

#6

#7

#8

#10

#9

#11

I

#12

I

\~~-----------------------------------------------------------------.j
~tPcs
Filst Inst. of

Interrupt Routine
Internal -----,.,....-"""",....-"""",,....-"""",,....-""""'--"""",,....-"'"'\.,--"""",,....-"""'\.r--"""''''~-"""""~--_V--_V--_V--,
DataBus-_ _
_
_ _n_ _ _
_
_
__
__
__
__
Op Code
PC 0·7
PC 8·15
X 0·7
X 8· 15·
ACCB
-r~_~~_~~

Internal R/W

_

_r~

_n~_~~

-r~_-J~

_J~

_r~

~

~

~

\~--------------------------~I
PROGRAMMABLE TIMER

when clear, the interrupt is inhibited. It is
cleared by reset.

The Programmable Timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several
microseconds to many seconds. A block diagram of the
Timer is shown in Figure 33.

Bit 3 EOCI Enable Output Compare Interrupt. When set, an
IR02 interrupt is enabled for an output compare; when clear, the interrupt is inhibited. It is
cleared by reset.
Bit 4 EICI Enable Input Capture Interrupt. When set, an
IR02 interrupt is enabled for an input capture;
when clear, the interrupt is inhibited. It is
cleared by reset.

TIMER CONTROL AND STATUS REGISTER ($08)
The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0-4 can be
written. The three most significant bits provide the timer
status and they indicate:

Bit 5 TOF

Timer Overflow Flag. TOF is set when the
counter contains all 1'so It is cleared by reading
the TCSR (with TOF set) followed by reading
the highest byte of the counter ($09), or by
reset. Reading the counter at $15 will not clear
TOF.

Bit 6 OCF

Output Compare Flag. OCF is set when the Output Compare Register matches the free-running
counter. It is cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or SOC), or by reset.
Input Capture Flag. ICF is set to indicate a proper level transition. It is cleared by reading the
TCSR (with ICF set) and then reading the Input
Capture Register High Byte ($OD), or by reset.

• a proper level transition has been detected, or
• a match has been found between the free-running
counter and the output compare register, or
• the free-running counter has overflowed.
Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.
TIMER CONTROL AND STATUS REGISTER
(TSCR)

6543210
ICF IOCF , TOF' EICI' EOCI' ETOI'IEDG' OLVL

I $08

Bit 7 ICF

Bit 0 OLVL Output level. OLVL is clocked to the output level
register by a successful output compare and will
appear at P21 if Bit 1 of the Port 2 Data Direction
Register is set. It is cleared by reset.
Bit 1 IEDG Input Edge. IEDG is cleared by reset and controls which level transition will trigger a counter
transfer to the Input Capture Register:
IEDG = 0 Transfer on a negative edge
IEDG = 1 Transfer on a positive edge
Bit 2ETOI Enable Timer Overflow Interrupt. When set, an
IR02 interrupt is enabled for a timer overflow;

COUNTER ($09:0A)

The key timer element is a 16-bit free-running counter
which is incremented by E (Enable). It is cleared during reset
and is a read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all 1's. The counter may also be read at
location $15 and $16 to avoid the clearing of the TOF.

3-645

~

I

MC68120 • MC68121

FIGUijE 33 -

PROGRAMMABLE TIMER -

BLOCK DIAGRAM

MC68120/MC68121 Internal Bus

I

Timer
Control 'r--'1-~---J~....L.""T""-'-"""'-"""~
and
Status
Register
~08

Bit 1
Port 2

DDR

Output Compare Pulse

___ _ I

Output Input
Level
Edge
Bit 1
Bit 0
Port 2 Port 2

INPUT CAPTURE REGISTER ($OD:OE)
The Input Capture Register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always
senses P20, even when configured as an output. An input
capture can occur independently of ICF: the input capture
register always contains the most current value regardless of
whether ICF was previously set or not. Counter transfer is inhibited, however, between accesses of a double byte IPC
read. The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.

OUTPUT COMPARE REGISTER ($OB:OC)
The Output Compare Register is a 16-bit Read/Write
register used to control an output waveform or provide an arbitrary timeout flag. It is compared with the free-running
counter on each E-cycle. When a match is found, OCF is set
and OLVL is clocked to an output level register. If Port 2, bit
1 is configured as an output, OL VL will appear at P21. The
Output Compare Register and OLVL can then be changed
for the next compare. The compare function is inhibited for
one cycle after a write to the high byte of the counter (SOB)
to ensure a valid compare. The Output Compare Register is
set to SFFFF by reset.

SERIAL COMMUNICATIONS INTERFACE (SCII
A full-duplex asynchronous Serial Communications Interface (SCI) is provided with two data formats and a choice of
Baud rates. The SCI transmitter and receiver are functionally
independent, but use the same data format and bit rate.
Serial data formats include standard mark/space (NRZl and
Bi-phase. Both formats provide one start bit, eight data bits,
and one stop bit. "Baud" and "bit rate" are used
synonymously in the following description.

beginning of the message. In order to allow uninterested
MPUs to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until the data line goes
idle. An SCI receiver is re-enabled by an idle string of ten
Consecutive l's or by reset. Software must provide the required idle string between consecutive messages and prevent it within messages.

WAKE-UP FEATURE
In a typical serial loop mUlti-processor configuration, the
software protocol will usually identify the addressee(s) at the

PROGRAMMABLE OPTIONS
The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase

3-646

MC68120· MC68121

R.A.TE AND MODE CONTROL REGISTER (RMCR)

• clock: external or internal clock source
• Baud rate: one of four per E-clock frequency, or oneeighth of the external clock input to P22
• wake-up features: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver
• clock output: internal bit rate clock enabled or disabled
to P22
SERIAL COMMUNICATIONS REGISTERS
The Serial Communications Interface includes four addressable registers as depicted in Figure 34. It is controlled
by the Rate and Mode Control Register and the
Transmit/Receive Control and Status Register. Data is
transmitted and received utilizing a write-only Transmit
Register and read-only Receive Register. The shift registers
are not accessible by software.
Rate and Mode Control Register ($10) - The Rate and
Mode Control Register (RMCR) controls the SCI Baud rate,
format, clock source, and under certain conditions, the configuration of P22. The register consists of four write-only bits
which are cleared by reset. The two least significant bits control the Baud rate of the internal clock and the remaining two
bits control the format and clock source.

76543210

x

I

x

I

x

I

x

I CCl I CCO I SS1 I SSO I $10

Bitl: BitO SSl:SS0 Speed Select. These two bits select
the Baud rate when using the internal clock.
Four rates may be selected which are a function
of the IPC input frequency (E). Table 11 lists bit
times and rates for three selected IPC frequencies.
Bit 3: Bit 2 CC1:CCO Clock Control and Format Select.
These two bits control the format and select the
serial clock source. If CCl is set, the Data Direction Register (DDR) value for P22 is forced to
the complement of CCO and cannot be altered
until CCl is cleared. If CCl is cleared after having been set, its DDR value is unchanged. Table
12 defines the format, clock source, and use of
P22.
If both CCl and CCO are set, an external TTL compatible
clock rnust be connected to P22 at eight tirnes (8X) the
desired Baud rate, but not greater than E, with a duty cycle
of 50% (± 10% l. If CCl :CCO= 10, the internal Baud rate
clock is provided at P22 regardless of the values for TE or RE.
NOTE: The source of SCI internal baud rate clock is the
free-running counter of the tirner. An IPC write to the
counter can disturb serial operations.

FIGURE 34 - SCI REGISTERS
Bit 7

Rate and Mode Control Register

Bit

a

I Icca I Issa I
CCl

SS1

$10

T ransmit/ Receive Control and Status Register

I I
R6RF

ORFE ITDREI RlE

I I
RE

TIE

TE

I

WU

I

$11

Receive Data Register

$12

Port ::

(Not Addressable)
Receive Shift Register

45

Transmit Shift Register

47

$13
Transmit Data Register

3-647

I

MC68120· MC68121

TABLE 11 -

TABLE 12 -

I

SCI BIT TIMES AND RATES

SSl:SS0

E

614.4 kHz

1.0 MHz

1.2288 MHz

0 0

+16

26 ,",s/38,400 Baud

16 ,",s/62,500 Baud

13.0 ,",sI76,800 Baud

0 1

+128

208 ,",s/4,800 Baud

128 ,",sI7812.5 Baud

104.2 ,",s/9,600 Baud

1 0

+1024

1.67 ms/600 Baud

1.024 ms/976.6 Baud

833.3 ,",s/ 1,200 Baud

1 1

+4096

6.67ms/ 150 Baud

4.096 ms/244.1 Baud

3.33 ms/300 Baud

SCI FORMAT AND CLOCK SOURCE CONTROL

CC1:CCO

Format

Clock
Source

Port 2
Bit 2

0 0

Bi-Phase

Internal

Not Used

0 1

NRZ

Internal

Not Used

1 0

NRZ

Internal

Output

1 1

NRZ

External

Input

Bit 6 ORFE

Transmit/Receive Control and Status Register ($11) The Transmit/Receive Control and Status Register (TRCSR)
controls the transmitter, receiver, wake-up features, and two
individual interrupts and monitors the status of serial operations. All eight bits are readable while only bits 0 to 4 are
writable. The register is initialized to $20 by reset.
TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER
(TRCSRl
7

6

Bit 0 WU

Bit 1 TE

Bit 2 TIE

Bit 3 RE

Bit 4 RIE

Bit 5 TDRE

Bit 7 RDRF

543

IRDRFIORFEITDREI RIE I

RE I TIE

TE

WU

$11

"Wake-up" on Idle Line. When set, WU
enables the wake-up function; it is cleared by
ten consecutive 1's or by reset. WU will (lot set
if the line is idle.
Transmit Enable. When set, the P24 DDR bit is
set, cannot be changed, and will remain set if
TE is subsequently cleared. When TE is
changed from clear to set, the transmitter is
connected to P24 and a preamble of nine consecutive l's is transmitted. TE is cleared by
reset.
Transmit Interrupt Enable. When set, an IR02
interrupt is enabled when TDRE is set; when
clear, the interrupt is inhibited. TIE is cleared
by reset.
Receive Enable. When set, the P23 DDR bit is
cleared, cannot be changed, and will remain
clear if RE is subsequently cleared. While RE is
set, the SCI receiver is enabled. RE is cleared
by reset.
Receiver Interrupt Enable. When set, an IR02
interrupt is enabled when RDRF and/or ORFE
is set; when clear, the interrupt is inhibited.
RIE is cleared by reset.
Transmit Data Register Empty. TDRE is set
when the contents of the Transmit Data
Register is transferred to the output se(ial shift
register or by reset. It is cleared by reading the
TRCSR (with TDRE set) and then writing to
the Transmit Data Register. Additional data

will be transmitted only if TDRE has been
cleared.
Overrun Framing Error. If set, ORFE indicates
either an overrun or framing error. An overrun
occurs when a new byte is ready to transfer to
the Receiver Data Register with RDRF still set.
A receiver framing error has occurred when
the byte boundaries of the bit stream are not
synchronized to the bit counter. An overrun
can be distinguished from a framing error by
the value of RDRF: if RDRF is set, then an
overrun has occurred; otherwise, a framing error has been detected. Data is not transferred
to the Receive Data Register in an overrun
condition. ORFE is cleared by reading the
TRCSR (with ORFE set) then reading the
Receive Data Register, or by reset.
Receive Data Register Full. RDRF is set when
the contents of the input serial shift register is
transferred to the Receive Data Register. It is
cleared by reading the TRCSR (with RDRF
set), and then reading the Receive Data
Register, or by reset.

SERIAL OPERATIONS
The SCI is initialized by writing the control bytes first to
the Rate and Mode Control Register and then to the
Transmit/Receive Control and Status Register. When TE is
set, the output of the Transmit Shift Register is connected to
P24 and serial output is initiated by the transmission of a
9-bit preamble of 1's.
At this point one of two situations exist: 1) if the Transmit
Data Register is empty (TDRE= 1), a continuous string of l's
will be sent indicating an idle line, or 2) if a byte has been
written to the Transmit Data Register (TDRE=O), the byte
will be transferred to the Transmit Shift Register (synchronized with the bit rate clock), TDRE will be set, and
transmission will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit (1), will be transmitted. If TDR E is still set when the
next byte transfer should occur, l's will be sent until more
data is provided. Receive operation is controlled by RE which
configures P23 as an input and enables the receiver. In Biphase format, the output toggles at the start of each bit and
at half time when a "1" is sent. SCI data formats are illustrated in Figure 35. In receiving Bi-phase, a "1" is input
when two transitions occur in less than 3/4 bit-time, and a
"0" is input when more than 3/4 bit-time passes after a transition on P23.

3-648

MC68120· MC68121

FIGURE 35 -

SCI DATA FORMATS

Output
Clock

NRZ
Format

Bi-Phase

Format
Idle Start

Bit

Bit

0

4

7

Stop

Data: 01001101 ($401

INSTRUCTION SET
The MC68120/MC68121 is upward source and object code
compatible with the MC6800 processor and directly compatible with the M6801 Family processors.

E-cycles. Instruction execution times are summarized in
Table 17. With an input frequency (E) of 1 MHz, E-cycles are
equivalent to microseconds. A cycle-by-cycle description of
bus activity for each instruction is provided in Table 18 and a
description of selected instructions is shown in Figure 38.

PROGRAMMING MODEL
A programming model for the MC68120/MC68121 is
shown in Figure 14. Accumulator A can be concatenated
with accumulator B and jointly referred to as accumulator D
where A is the most significant byte. Any operation which
modifies the double accumulator will also modify accumulator A and/ or B. Other registers are defined as
follows:
Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The Stack Pointer is a 16-bit register
which contains the address of the next available location in a
pushdown/pullup (LIFO) queue. The stack resides in random access memory at a location specified by the software.
Index Register - The Index Register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.

Immediate Addressing - The operand is contained in the
following byte(s) of the instruction where the number of
bytes matches the size of the register. These are two or three
byte instructions.
Direct Addressing - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assumed to be $00.
Direct addressing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access (refer to Table 1).
In most applications, this 256-byte area is reserved for frequently referenced data. Note that no direct addressing of
internal control registers is possible in Mode 3.
Extended Addressing - The second and third bytes of the
instruction contain the absolute address of the operand.
These are three byte instructions.

Accumulators - The IPC contains two 8-bit accumulators, A and B, which are used to store operands and
results from the arithmetic logic unit (ALU). They can also be
concatenated and referred to as the D (double) accumulator.
Condition Code Register - The Condition Code Register
indicates the results of an instruction and includes the
following five condition bits: Negative (N), Zero (Z),
Overflow (V), Carry/Borrow from MSB (C), and half carry
from bit 3 (H). These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask (I-bit) and inhibits all maskable interrupts when set. The two unused bits
b6 and b7, are read as ones.

Indexed Addressing - The unsigned offset contained in
the second byte of the instructions is added with carry to the
Index Register and used to reference memory without
changing the Index Register. These are two byte ·instructions.
Inherent Addressing - The operand(s) are registers and
no memory reference is required. These are single byte instructions.
Relative Addressing - Relative addressing is used only for
branch instructions. If the branch condition is true, the Program Counter is overwritten with the sum of a signed single
byte displacement in the second byte of the instruction and
the current Program Counter. This provides a branch range
of -126 to 129 bytes from the first byte of the instruction.
These are two byte instructions.

ADDRESSING MODES
The MC68120/ MC68121 provides six addressing modes
which can be used to reference memory. A summary of addressing modes for all instructions is presented in Tables 13,
14, 15 and 16 where execution times are provided in

3-649

I

MC68120· MC68121

TABLE 13 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes

Pointer Operations

I

Immed Direct
Index
Extend Inherent
Mnemonic Op- # OP- # OP - # OP- # OP- #
CPX

Decrement Index Reg

DEX

09 3

1 X-1

Decrement Stack Pntr

DES

34 3

1 SP - 1 -SP

Increment Index Reg

INX

08 3

1 X + 1-X

Increment Stack Pntr

INS

31 3

1 1 SP + 1 -SP

Load Index Reg

LDX

CE 3

3 DE 4

2 EE 5 2 FE 5

3

M -XH, (M + 1) -XL

Load Stack Pntr

LOS

8E 3

3 9E 4

2 AE 5 2 BE 5

3

M -SPH, (M + 1) -SPL

3 9C 5

2 AC 6 2 BC 6

3

·

Booleanl
Arithmetic Operation
P<-M:M+1

Compare Index Reg

8C 4

5 4 3 2 1 0
H I N Z V C

• :t t t
••• ••
••••••
• • ·I~ • •
••••••
••
•
••
•
••
•
••
•
••••••
•• •• •• •• •• •
• • • • • ••
••••••

-x

Store Index Reg

STX

DF 4

2 EF 5 2 FF 5

3

XH -M, XL -(M + 1)

Store Stack Pntr

STS

9F 4

2 AF 5 2 BF 5

3

SPH -M, SPL -(M + 1)

Index Reg - Stack Pntr

TXS

35 3

1 X - 1 -SP

Stack Pntr - Index Reg
Add
Push Data

TSX
ABX
PSHX

30 3
3A 3
3C 4

Pull Data

PULX

38 5

1 SP + 1 -X
1 B + X-X
1 XL -MSp, SP - 1 -SP
XH -MSR SP - 1 --SP
1 SP + 1 -SP, MSp -XH
SP + 1 -SP, MSp -XL

R

R

R

R

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Accumulator and
Memory Operations
Add Acmltrs
Add B to X
Add with Carry
Add
Add Double
And
Shift Left,
Arithmetic
Shift Left Dbl
Shift Right,
Arithmetic
Bit Test
Compare Acmltrs
Clear

Compare
1 's Complement

Decimal Adj. A
Decrement

Exclusive OR

MNE
ABA
ABX
ADCA
ADCB
ADDA
ADDB
ADDD
ANDA
ANDB
ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
BITA
BITB
CBA
CLR
CLRA
CLRB
CMPA
CMPB
COM
COMA
COMB
DAA
DEC
DECA
DECB
EORA
EORB

Immed
Extend
Direct
Index
Inher
# Op - # Op - # Op - # Op
Op #
1B 2 1
3A 3 1
89 2 2 99 3 2 A9 4 2 B9 4 3
C9 2 2 D9 3 2 E9 4 2 F9 4 3
8B 2 2 9B 3 2 AB 4 2 BB 4 3
CB 2 2 DB 3 2 EB 4 2 FB 4 3
C3 4 3 D3 5 2 E3 6 2 F3 6 3
84 2 2 94 3 2 A4 4 2 B4 4 3
C4 2 2 D4 3 2 E4 4 2 F4 4 3
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
57 2 1
85 2 2 95 3 2 A5 4 2 B5 4 3
C5 2 2 D5 3 2 E5 4 2 F5 4 3
11 2 1
6F 6 2 7F 6 3
4F 2 1
5F 2 1
81 2 2 91 3 2 A1 4 2 B1 4 3
C1 2 2 D1 3 2 E1 4 2 F1 4 3
63 6 2 73 6 3
43 2 1
53 2 1
19 2 1
6A 6 2 7A 6 3
4A 2 1
5A 2 1
88 2 2 98 3 2 A8 4 2 B8 4 3
C8 2 2 D8 3 2 E8 4 2 F8 4 3

-

3-650

Boolean
Expression
A + B-A
OO:B + X -X
A+M+C-A
B+M+C-B
A + M-A
B + M-A
D + M:M + 1 -D
A'M-A
B . M --B

Condition Codes
H
N Z V C

I

•

t

I

,

I

R
R

•
•

••••

I
A·M
B· M
A·B
OO-M
OO-A
00 -B
A·M
B -M
M-M
A --A
B -B
Adj binary sum to BCD
M·1-M
A·1 -A
B·1 -B
A 0 M--A
B 0 M-B

R
R

R
R
R

•

•

I I

I
S
S

S

R
R
R

I

R
R
R

:

I \
R
R
R

S
S

S

R
R

•••

•

I

•

MC68120· MC68121

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Accumulator and
Memory Operations
Increment

Load Acmltrs
Load Double
Logical Shift,
Left

Shift Right,
Logical

Muliiply
2's Complement
(Negate)
No Operation
Inclusive OR
Push Data
Pull Data
Rotate Left

Rotate Right

Subtract Acmltr
Subtract with
Carry
Store Acmltrs

Subtract
Subtract Double
Transfer Acmltr
Test, Zero or
Minus

MNE
INC
INCA
INCB
LOAA
LOAB
LDD
LSL
LSLA
LSLB
LSLD
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
SBA
SBCA
SBCB
STAA
STAB
STD
SUBA
SWBB
SUBO
TAB
TBA
TST
TSTA
TSTB

Extend
Immed
Direct
Index
Inher
# Op - # Op
# Op - # Op
Op #
6C 6 2 Ie ti 3
4C 2 1
5C 2 1
86 2 2 96 3 2 A6 4 2 B6 4 3
C6 2 2 06 3 2 E6 4 2 F6 4 3
CC 3 3 DC 4 2 EC 5 2 FC 5 3
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
30 10 1
60 6 2 70 6 3
40 2 1
50 2 1
01 2 1
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
36 3 1
37 3 1
32 4 1
33 4 1
69 6 2 79 6 3
49 2 1
59 2 1
66 6 2 76 6 3
46 2 1
56 2 1
10 2 1
82 2 2 92 3 2 A2 4 2 B2 4 3
C2 2 2 02 3 2 E2 4 2 F2 4 3
97 3 2 A7 4 2 B7 4 3
07 3 2 E7 4 2 F7 4 3
DD 4 2 ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
co 2 2 00 3 2 EO 4 2 FO 4 3
83 4 3 93 5 2 A3 6 2 B3 6 3
16 2 1
17 2 1
6D 6 2 7D 6 3
40 2 1
50 2 1

-

The Condition Code Register notes are listed after table 16.

3·651

-

Boolean
Expression
M+ 1-M
A + 1-A
B + 1 --B
M -+'A
M --B
M:M + 1 --0

Condition Codes
H I N Z V C

•
••• II 1I ••
••
•••
•
..
••
•••
••• • •
•
; I I
••• II II II
•• •I •I • ••
•• •I •I • ••
•• ••• ••• ••• •••
1 I j
\

I

I

R
R
R

R
R
R
R

AXB-D
00 - M-M
00 - A-A
00 - B --8
PC + 1 -PC
A + M--A
B + M--B
A --Stack
B -Stack
Stack --A
Stack -- B

R
R

I

I I

I

\
I

I

I

I
A - B--A
A - M - C-A
B - M - C--B
A -M
B --M
D--M:M+1
A - M--A
B - M -B
D - M:M + 1 --0
A --B
B --A
M -00
A - 00
B - 00

R
R
R

I

•
••
1
~

]

I I t

I

R
R
R
R
R

•..
R
R
R

I

MC68120· MC68121

TABLE 15 - JUMP AND BRANCH INSTRUCTIONS

Direct
Operations

I

Mnemonic

Branch Always

BRA

Branch Never
Branch If Carry Clear

Relative

OP -# OP -

Index

Extnd

Condo Code Reg.
5 4 3 2 1 0

Inheren

# OP- # OP- # OP

-Ill

Branch Test

20 3

2

BRN

21 3

2

None

BCC

24 3

2

C=O

Branch If Carry Set

BCS

25 3

2

C= 1

Branch If = Zero

BEQ

27 3

2

Z=1

Branch If

~

Zero

BGE

2C 3

2

N(t)V=O

Branch If

> Zero

BGT

2E 3

2

Z+(N(t)V)=O

2

C+Z=O

Branch If Higher

BHI

22 3

Branch If Higher or Same

BHS
BlE

24 3 2
2F 3 2

BlO
BlS

25 3 2
23 3 2

Branch If < Zero
Branch If Carry Set
Branch If Lower Or Same

< Zero

BlT

2D 3

2

N(t)V = 1

BMI

2B 3

2

N- 1

Branch If Not Equal Zero

BNE

26 3

2

Z-O

Branch If Overflow Clear

BVC

28 3

2

V=O

Branch If Overflow Set

BVS

29 3

2

V=1

Branch If Plus

BPL

2A 3

2

N=O

Branch To Subroutine

BSR

8D 6

2

Jump

JMP

Jump To Subroutine

JSR

No Operation

NOP

AD 6 2 BD 6 3
01 2

1

Return From Interrupt

RTI

3B

Return From Subroutine

RTS

39 5

~ } s" S"oI,'

0

Software Interrupt

SWI

3F

Wait For Interrupt

WAI

3E 9

TABLE 16 -

2

1
1

S

CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Condo Code Reg.
5 4 3 2 1 0
#

Boolean Operation

Clear Carry

CLC

OC 2

1

o -C

Clear Interrupt Mask

CLI

OE 2

1

0-1

Clear Overflow

CLV

OA 2

1

o -V

Set Carry

SEC

OD 2

1

1 -C

Set Interrupt Mask

SEI

OF 2

1

1 -I

Set Overflow

SEV

OB 2

1

1 -V

Accumulator A -CCR

TAP

06 2

1

A -CCR

TPA

07 2

1

CCR -A

Operations

Mnemonic OP -

CCR -Accumulator A
LEGEND
OPOperation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
Number of Program Bytes
Arithmetic Plus
Arithmetic Minus
Boolean AND
Arithmetic Multiply
Boolean Inclusive OR
Boolean Exclusive OR
iiii Complement of M
- Transfer Into
OBit = Zero
00 Byte = Zero

,,

OperationsFigure 36

Inherent

#
+
•
X
+
(t)

&

} See Special
Operations Figure 36

6E 3 2 7E 3 3
9D 5 2

N Z V C

I

•

C =0
Z+(N(t)V)-1
C= 1
C+Z- 1

Branch If Minus

Branch If

H

••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
•••• •
••••••
•• •• •• •• •• •
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
• • • • •, 1•
t II
••••••
• ••••
• •••••

None

CONDITION CODE SYMBOLS
H
I
N
Z
V
C
R
S

I

•

3-652

Half-carry from bit 3
Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry/Borrow from MSB
Reset Always
Set Always
Affected
Not Affected

H

I

N

Z

V

C

•••••
• ••••
•••• •
•••••
• ••••
•I •I •I •I •I
I
••••••
R

R

R

S

S

S

MC68120· MC68121

TABLE 17 - INSTRUCTION EXECUTION TIMES IN E CYCLES
ADDRESSING MODE

ADDRESSING MODE
~

ABA
ABX
ADC
ADD
ADDD
AND
ASl
ASlD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BlE
BlO
BlS
BlT
BMI
BNE
BPl
BRA
BRN
BSR
BVC
BVS
CBA
ClC
CLI
ClR
ClV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

'tl

.

Q)

><

a;

'tl

~

'tl

III

'5
Q)

Q)

t)

'tl

c

Q)

E
§

i5

><
w

••

••3

•• ••

4
2

3
5
3

2
2

•
•••
••
•
•
••
2
•

2

•
••
••2
•
•
4

f

•
••
•
•••
•••
3
•
•••
••
••
••
•••
•••
•3
•5
••
•
•3
••

:l

4
4
6
4
6

•
••
•
•••
6

•4

6

•4
6
6

•
••
6

4
6

•

.E

4
4
6
4
6

C

Q)

.E
2

3

••
••
2

• 32
•• ••
••• ••
•• ••
••
••
••
•
•
••
••• 2
2
•• 22
• •2
2
•
• 22
3
•• •3
• •3
6

4

:lIII

Q)

>

'5
Q)

Qj

E
§

';:;
III

a:

••
••
••
•••
3

INX
JMP
JSR
lOA
lDD
lOS
lOX
lSl
lSlD
lSR
lSRD
MUl
NEG
NOP
ORA
PSH
PSHX
PUl
PUlX
ROl
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6
3
3

6

4
6
6

6

4
6

3-653

•
••2
3
3
3

••
••
•
••2
••
••
•••
••
2
••
•••
••
2
4

••
••
•

•••
•

'tl
QI

t)

f

'tl

cQI

'tl
QI

><
QI

.. .
a;
cQI

i5

;c

w

."

••
5

•

• •
•

3
4
4
4

••
••

••
•
3

••
•••
•••
•3
••
•3
4
4
4
3
5

•••
•••
•••

3
6
4
5
5
5
6

.=

~

.=

3
6
4
5
5
5
6

••
•
••
•
••

••
•
••6
•
••

•••
4
••
4
5
5
5
4
6

6

a:

•
•••
2

•

6

>

III

3

•
••
•
•• •
••
•••
•• •
•

•6
••
6
•4
••
••6

QI

'

Qj

6

6

3
2
3
10
2
2

4

6
6

•

3
4
4
5
2
2
10
5
2

4

2
2
2

4
5
5
5
4
6

•
•••
•
•
12
2
2
2
2
2
3
3
9

•

I

MC68120 • MC68121

FIGURE 36 - SPECIAL OPERATIONS
JSR, Jump to Subroutine
PC
Direct

{

1-:-:---:-:--:---1
RTN '--,:--=---'-""7"":"-'---'

PC
INDXD
{

1-:---:--:--,---:---1
RTN

'--"'-'-~

____=--'

PC
EX TN D

f-=,---=---:----:----:-.....,

1---7-"----'c.:.:,---"-

{

RTN'-------

I

BSR, Branch to Subroutine
SP

Stack

~SP-2HH
SP- 1
RTNH
SP~~

RTN '--_ _ _ _- '

RTS, Return from Subroutine

~:rnStack

Subroutine

PC~I--$3-9-=-R-TS--1 ~

SP+ 1

RTNH

~

SP+2

RTNL

SP

Stack

~

SP-7

SWI, Software Interrupt
Main Program

--1\

R:~If-_-.:;$3,,-F_-..=S-,-,W-,-1

~

WAI, Wait for Interrupt
Main Program

R~:

r__

$3_E_=_"'_'A_I---1!

~

SP-6

Condition Code

SP-5

Acmltr B

SP-4

Acmltr A

SP-3

Index Register (XHI

SP-2

Index Register (XLI

SP- 1

RTNH

SP

RTNL

RTI, Return from Interrupt
Interrupt Program

PC

I

$3B-RTI

!

SP

~

Stack

SP
SP+ 1
SP+ 2

Condition Code
Acmltr B

SP+3

Acmltr A

SP+4

Index Register (XH)

SP+5

Index Register (XL

SP+6

RTNH

~SP+7

RTNL

JMP, Jump
Main Program
PCC;m:a
K= Offset

{
Next Instruction

Legend
RTN = Address of next Instruction In Main Program to be executed upon return from subroutme

. . = Stack

pOinter after execution

K:::: 8-bit unsigned value

RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address

3-654

MC68120 • MC68121

CYCLE-BY-CYCLE OPERATION SUMMARY
Note that during MPU reads of internal locations, the
resultant value will not appear on the external Data Bus except in Mode O. "High order" byte refers to the most significant byte of a 16-bit value.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing, are shown in
Table 19. There are 220 valid machine codes, 34 unassigned
codes and 2 reserved for test purposes.

Table 18 provides a detailed description of the information
present on the Address Bus, Data Bus, and the R/W line
during cycle of each instructions.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles
per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.

TABLE 18 -

Address Mode &
Instructions

CYCLE BY CYCLE OPERATION (Sheet 1 of 5)

Address Bus

R/W
Line

Data Bus

IMMEDIATE
ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB

2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

LOS
LOX
LDD

3

1
2

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus FFFF

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

Op Code Address
Op Code Address + 1
Destination Address

1
1

0

Op Code
Destination Address
Data from Accumulator

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address.,. 1
Address of Operand
Address of Operand + 1

1
1

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

3
1
2

3
4

DIRECT
ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB

3

STA

3

1
2

3

1
2

3
LOS
LOX
LDD

4

STS
STX
STD

4

1
2

3
4
1
2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

5
JSR

5

1
2

3
4

5

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

0
0
1
1
1

1
1
1
1
1

0
0

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

-

3-655

Continued -

I

MC68120· MC68121

TABLE 18 -

CYCLE BY CYCLE OPERATION (Sheet 2 of 5)

Address Mode &
Instructions

Address Bus

R/W
Line

Data Bus

EXTENDED
JMP

3

ADC EOR
ADD LDA
AND ORA

4

1
2

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

4

Address of Operand

1

Op Code
Address of Operand
Address of Operand
(Low Order Byte)
Operand Data

1
2

Op Code Address
Op Code Address + 1

1
1

3

BIT SBC
CMP SUB
STA

I

4

1
2

3

Op Code Address + 2

1

4

Operand Destination Address

0

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op Code Address + 2

1

4
5

Address of Operand
Address of Operand + 1

1
1

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op Code Address + 2

1

4
5

Address of Operand
Address of Operand + 1

0
0

1
2

Op Code Address
Op Code Address + 1

1
1

CLR ROL

3

Op Code Address + 2

1

COM ROR
DEC TST
INC

4
5
6

Address of Operand
Address Bus FFFF
Address of Operand

1
1

0

1
2

Op Code Address
Op Code Address + 1

1
1

3

Op code Address + 2

1

4
5
6

Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1

1

2

Op Code Address
Op Code Address + 1

1
1

3

Op Code Address + 2

1

4
5

Subroutine Starting Address
Stack Pointer

0

6

Stack Pointer - 1

0

LDS
LDX

5

LDD

STS
STX

5

STD

ASL LSR
ASR NEG

CPX
SUBD

6

6

ADDD

JSR

6

1

Op Code
Destination Address
(High Order Byte)
Destination Address
(Low Order Byte)
Data from Accumulator
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code
Operand Address
(High Order Byte)
Operand Address
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
Op Code of Next Instruction
Return Address
(Low Order Byte)
Return Address
[tHigh Order Byte)

-

3-656

Continued -

MC68120 • MC68121

TABLE 18 Address Mode &
Instructions

CYCLE BY CYCLE OPERATION (Sheet 3 of 5)

Address Bus

R/W
Line

Data Bus

INDEXED
JMP

3

1

2
3
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB

4

STA

4

1

2
3
4
1

2
3
4
LDS
LDX
LDD

STS
STX
STD

5

1

2
3
4
5
5

1

2
3
4
5

ASL LSR
ASR NEG
CLR ROL
COM ROR
DEC TST (1)
INC

6

CPX
SUBD
ADDD

6

JSR

6

1

2
3
4
5
6
1

2
3
4
5
6
1

2
3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

0
1
1
1

1
1
1
1
1

0
0
1
1
1
1
1

0

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Offset
Low Byte of Restart Vector
'Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus FFFF

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

-

3-657

Continued -

I

MC68120 • MC68121

TABLE 18 -

CYCLE BY CYCLE OPERATION (Sheet 4 of 5)

Address Mode &
Instructions

Address Bus

R/W
Line

Data Bus

INHERENT
ABA DAA SEC
ASL DEC SEI
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA

2

ABX

3

1

Op Code Address
Op Code Address +1

1
1

Op Code
Op Code of Next Instruction

3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Irrelevent Data
Low Byte of Restart Vector

2

1

2

II

ASLD
LSRD

3

1
2
3

Op Code Address
Op Code Address +1
Address Bus FFFF

1
1
1

Op Code
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Op Code Address
Op Code Address +1
Previous Register Contents

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Op Code Address
Op Code Address +1
Stack Pointer

1
1

0

Op Code
Op Code of Next Instruction
Accumulator Data

TSX

3

1
2
3

Op Code Address
Op Code Address + 1
Stack Pointer

1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data

TXS

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Op Code Address
OpCode Address +1
Stack Pointer
Stack Pointer +1

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1

1

0
0

Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

1
2
3
4
1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1

1
1
1
1
1
1
1
1
1

5

Stack Pointer +2

1

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1

1
1

0
0

5

Stack
Stack
Stack
Stack
Sta ck

Pointer
Pointer
Pointer
Pointer
Pointer

0
0
0
0
0

PULX

5

RTS

5

5

WAI

9

6

J
8

9

-2
-3
-4
-5
-6

1

Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
-

3-658

Continued -

MC68120· MC68121

TABLE 18 Address Mode &
Instructions

CYCLE BY CYCLE OPERATION (Sheet 5 of 5)

Address Bus

R/W
Line

Data Bus

INHERENT
10

MUL

10

Op Code Address
Op Code Address +1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Op Code
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

1
2
3
4

Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer +1

1
1
1
1

5

Stack Pointer +2

1

6

Stack Pointer +3

1

Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)

1
2
3
4
5
6
7

8
9
10

RTI

12

SWI

7

Stack Pointer +4

1

8

Stack Pointer +5

1

9

Stack Pointer +6

1

10

Stack Pointer +7

1

1
2
3
4

Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer -·1

1
1
0
0

5
6
7

10
11

Stack Pointer -2
Stack Pointer -3
Stack Pointer -4
Stack Pointer -5
Stack Pointer -6
Stack Pointer -7
Vector Address FFFA (Hex)

0
0
0
0
0
1
1

12

Vector Address FFFB (Hex)

1

8
9

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR

BHT BNE BLO
BLE BPL BHS
BLS BRA BRN
BLT BVC
BMT BVS

3

1
2
3

Op Code Address
Op Code Address +1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4
5
6

Op Code Address
Op Code Address +1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer -1

1
1
1
1
0
0

Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address(High Order Byte)

3-659

I

MC68120· MC68121

OP
00

MNEM

01
02
03

NOP

04
05

LSRD
ASLD
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
CLl
SEI
SBA
C8A

06
07
DB
09
OA
DB
DC
00

II

~E
OF
10
11
12
13
14
15
16
17
lB
19
lA
lB
lC
10
IE
IF
20
21

22
23
24
25
26
27
28
29
, 2A
2B
2C
20
2E
2F
30
31
32
33

MOOE
INHER

#

2

1

35
36
37

3
3
2
2
3
3
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1

38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67

2
2
2
2
2
2
2

TA8
TBA

TABLE 19 -

-

L
2

1
1

oAA

INHER

2

1

ABA

INHER

2

1

BAA
BAN
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BVS
8PL
BMI
BGE

REL

I'

Elf
BGT
BLE
TSX
INS
PULA
PULB

REL
INHER

~

INHER

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1

OP
34

MNEM

MODE

DES
TXS
PSHA
PSHB
PULX
RTS
ABX
RT!
PSHX
MUL
WAI
SWI
NEGA

INHfR

3
3
3
3
5
5
3
10
4
10
9
12
2

COMA
LSRA

2

RORA
ASRA
AS LA
ROLA
DECA

)

)

2
2
2
2

INCA
TSTA
T
CLRA
NEGB

CoM8
LSRB

INCB
TSTB
T
CLR8
NEG

COM
LSA
ROR
ASR

1
1
1
1
1

2
2

1
1

2
2
2
2
2
2
2

!

1
1

1
1

)

INHER
INQXD

1
1
1
1
1
1
1
1
1
1
1
1
1

2
2

2

AOAB
ASRB
ASLB
ROLB
oECB

#

2

6

6
6

6
INOXO 6

1
1
1
1
1
1
1
1
1
1
2

2
2
2
2

MNEM

MODE -

68
69
6A
6B
6C
60
6E
6F
70
71
72

ASL
ROL
DEC

INDXD

73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
B2
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93

.

CPU INSTRUCTION MAP

OP

1

6
6
6

2
2
2

6
6
3
6
6

2
2
2
2
3

COM
LSA

6
6

3

ROR
ASR
ASL
ROL
DEC

6
6
6
6
6

3
3
3
3
3

INC
TST
JMP
CLR
NEG

INDXO
EXTND

6

INC

TST
JMP

6

CLR

EXT NO

SUBA
CMPA
SBCA
SU8D
ANDA

IMMED

3
6
2
)

2
4
)

BllA

)

LDAA

)

EO"A
ADCA
DRAA
ADDA
CPX
BSR
LDS
SU8A
CMPA
SBCA
SUBo

~4

ANOA

95
96
97
9B
99
9A
9B

BIIA
LDAA
STAA
EORA
ADCA
DRAA
ADDA

1

IMMEC
REl

IMMED

DIR

)
)

2
)

4
6
3

3
3

I
3

5

DIR

NOTES.
1. Addressing Modes
INHER", Inherent INDXD", Indexed
IMMEDe Immediate
REL", Relative
EXTND ... Extended
DIR", Direct
2. Unassigned opcodes are indicated by"'" and should not be executed.
3. Codes marked by ''1'' force the PC to function as a 16-bit counter.

3-660

3

3
3
3
3
2
2
2
3
2
2
2
2
2
2
2
3
2
3
2
2
2
2

3

2

3
3

2
2

3

2

3
3
3
3

2
2
2
2

OP

MNEM

MODE

9C
90
9E
9F
40
Al
A2
A3
A4
A5
A6
A7
AB
A9
AA
AB
AC
AD
AE
AF
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
B8
BC
BD
BE
SF
CO
Cl

CPX
JSR
LOS
STS
SU8A
CMPA
SBCA
SUBD
AND'A
BITA
LOAA
STAA

DIR

C2
C3
C4
C5
C6

+

DIR
INDXD

fORA

ADCA
DRAA
ADDA
CPX
JSR
LOS
STS
SUBA
CMPA
SBCA
SUBD

INOXO

FXTND

ANDA

BIlA
LDAA

STAA
fORA
ADCA
DRAA
ADoA
CPX

JSR

LOS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BITB

EXTND
IMMED

-

5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
0

6
5
5
4
4
4
6
4
4
4
4
4
4
4
4
6
6

5
5
)

2
)

4
)
)

7

LDAB

#

OP

2
2
2
2
2
2
2
2
2
2
2
2

DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
OF
EO
El
E)

2
2
2
2
2
2
)

2
.l
3
3
3
3
3
3
3
3
3
3

3
3
3
3
3
2
2
2
3
2
2
2

C7
CB
C9
CA
CB
CC
CD

EORB
AoCB
DRAB
AD DB
LOD

CE

LOX

CF

IMMfD

E3
E4
E5
E6
E7
E8
E9
fA
fB
EC
ED
Ef
fF
FO
Fl
f2
'3
F4
F5
F6
F7
FB
F9
FA
fB
Fe

1

2

2
2

2

FD

2

Ff

2
3

2
3

Ff

3

3

MNEM
SUBB
CMPB
S8CB
AD DO
ANDB
BITB
LDA8
STAB
EORB
ADCB
DRAB
ADDB
LDD
STD
LOX
STX
SUBB
CMPB
SBCB
AOOO
ANDB
BITB

MODE -

#

DIR

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

~
OIR
INDXD

6
4
4
4
4
4
4
4
4
5
5

LOA8

STAB
EOAB
AOCS

OAAB
ADDB
LDD
STD
lOX
STX
SUBB
CMPB
SBCB
ADDD

5
INOXO

EXTND

ANDB
BITB
LOA8

STAB
EORB
ADCB
DRAB
ADDB
Loo
STo
lOX
STX

3
3
3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4

EXTNO

• UN DE f INf D (lP CODf

5
4
4
4
6
4
4
4
4
4
4
4
4

5
5
5
5

2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3

3
3

3
J
:1
3
3
3
3
3
3
3

MC68120 • MC68121

APPENDIX A
MC68120 CUSTOM ORDERING INFORMATION
MC2708s must be clearly marked to indicate which PROM
corresponds to which address space ($F800-$FBFF; $FCOO$FFFF). See Figure A-2 for recommended marking procedure.

A.O
Address $FFEF is Reserved for the Checksum value for the
ROM, to be generated at the factory.
A.1 CUSTOM MC68120 ORDERING INFORMATION
The custom MC68120 specifications may be transmitted to
Motorola in any of the following media:
A) EPROM(s)

FIGURE A-2

~
~

B) MOOS diskette
The specification should be formatted and packaged, as
indicated in the appropriate paragraph below, and mailed
prepaid and insured with a cover letter (see Figure A-1) to:
Motorola Inc.
MPU Marketing
3501 Ed Bluestein Blvd.
Austin, Texas 78721

~
~

xxx = Customer ID

A copy of the cover letter should also be mailed separately.
A.2 EPROMs
MCM2708 and MCM2716 type EPROMs, programmed
with the custom program (positive logic notation for address
and data), may be submitted for pattern generation. The

After the EPROM(s) are marked, they Should be placed in
conductive IC carriers and securely packed. Do not use
styrofoam.
A.3 MOOS DISKETTE
The file name and startl end location should be written on
the label.

FIGURE A-1
cUSTOMERNAME _______________________________________________________
ADDRESS ____________________________________________________________
ST A TE _________________________ CITY __________________ ZIP _ _ _ __
PHONE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EXTENSION _ _ _ _ _ _ _ _ _ _ __
CONTACT MS/MR ___________________________________________

CUSTOMERPART# ____________________________________________________

PATTERN MEDIA
02708 EPROM
02716 EPROM
o Diskette IMDOSI

TEMPERATURE RANGE
00° to 70°C

MARKING
o Standard
o Special

PACKAGE TYPE
Ceramic

o

I Note 11 __________________________________________________________
NOTE: 111 Other Media Require Prior Factory Approval
SIGNATURE ___________________________________________________
TITLE ___________________________________________________

I

®

ItIIOTOROLA

MCl4680SE2

Advance Information

CMOS
(HIGH PERFORMANCE SILICON GATE)

8-BIT MICROPROCESSOR UNIT
The MC146805E2 Microprocessor Unit (MPU) belongs to the M6805
Family of Microcomputers. This 8-bit fully static and expandable
microprocessor contains a CPU, on-chip RAM, 1/0, and TIMER. It is a
low-power, low-cost processor designed for low-end to mid-range applications in the consumer, automotive, industrial, and communications
markets where very low power consumption constitutes an important
factor. The following are the major features of the MC146805E2 MPU:

I

HARDWARE FEATURES

•
•
•
•
•
•

Typical Full Speed Operating Power of 35 mW @ 5 V
Typical WAIT Mode Power of 5 mW
Typical STOP Mode Power of 25 p.W
112 Bytes of On-Chip RAM
16 Bidirectional 1/0 Lines
Internal 8-Bit Timer with Software Programmable 7-Bit Prescaler

•
•
•
•
•
•
•
•
•

External Timer Input
Full External and Timer Interrupts
Multiplexed AddresslData Bus
Master Reset and Power-On Reset
Capable of Addressing Up to 8K Bytes of External Memory
Single 3- to 6-Volt Supply
On-Chip Oscillator
4O-Pin Dual-In-Line Package
Chip Carrier Also Available

SOFTWARE FEATURES

•
•
•
•
•
•
•
•

Similar to the MC6800
Efficient Use of Program Space
Versatile Interrupt Handling
True Bit Manipulation
Addressing Modes with Indexed Addressing for Tables
Efficient Instruction Set
Memory Mapped 1/0
Two Power Saving Standby Modes

8-BIT
MICROPROCESSOR

~
~

WN'
I

LSUFFIX
CERAMIC PACKAGE
CASE 715

SSUFFIX
CERDIP PACKAGE
CASE 734

I

~ e,,""

PSUFFIX

~VVVW'

~

<:>

CASEeAC

AS-A12

80-87

80-87
MPURead~

* VHigh = 2.0 V, VLow= 0.5 V for VOO = 3 V for outputs only.
VHigh=VOO-2.0 V, VLow=O.S V for VOO=5 V± 10% for outputs only.

3:

o

....I.

FIGURE

"c:.

5 - POWER-ON RESET AND RESET TIMING

--1
/ / /lIflfih!l 1J17II7IIII07IZ/!l/IllIOIlZ/lIZmJ/////
OSC1~~~
-==~
~1fIIZ//!1Z2/117I77O!1!7!1!/71//11177!Z1171!77177/
="':::::t
V DD

Ii

RESET

10XOV

1920',,,------1

I

AS _ _~_--,
DS _ _ _ _ _---'
Unmux
A8-A12
Address Bus

~~~,

,~~

Mux BO-B7
Address/ Data ........'-"-'--'-'-'-'--':..Jf ....-J'LJ.J.-'--'--J.J/'~·'LL.i....L.<:zv'--J'---=--,'--..J\..._l-.J¥--J\_ _-./\.--"'--_-P'--"'--_---'''---'''--_ _''--ALLLL.Li.''=-.J .....,-,-"-J....LU'-J '--_ _J
Bus
FE

R!V:j

Zmmo71

\

'--J ...._ _ J'---J\---.,j'---J,---"'--

~

(,.)

m
<0

Oscillator Waveform

Crystal Oscillator Connections

10 MO

38~39

OSC2~O~OSCl
ICOSC2

I

Crystal Parameters Representative Frequencies

RS max
CO
Cl
Q

COSCl
COSC2

5.0 MHz

4.0 MHz

500

750
7 pF
0.012 pF
40 k
15-30 pF
15-25 pF

8 pF
0.02 pF
50 k
15-30 pF
15-25 pF

1.0 MHz
4000
5 pF
0.008 pF
30 k
15-40 pF
15-30 pF

COSCl
Crystal Circuit

~~~39

O~~l
O~C2

..

101

O~9Cl

en
CO
o
U1

m

I\)

•

~

o

...I.

~

en
Q)
o
UI
m

FIGURE 6 - IRQ AND TCR7 INTERRUPT TIMING

I-- n ------t-- n + 1--1--- n + 2 -+-- n + 3 --+--n +4---1----n + 5--t--n + 6-----1-- n + 7 -+- n +8-+-- n+9--1
AS

N

OS
Unmux

Ad~~~~l~us - J '

1.,_ . ~_

/~~_ ~~____

'~'

A

"

IRO or TCR7

Mux BO-B7
Address/Data===X:J<=====X=)(==__J(~l1~~~)l~~~-Y~~-YL-X-~
Bus

R/W

IlU

__~-A~~~~~~~~~~__A-~~DC~~r---~'-~-RTi~-J·~---J·~

\

/

\

'L

*tDSLIH - The Interrupting deVice must release the TliClline within this time to prevent subsequent recognition of the same Interrupt.
~

a,
......

o

FIGURE 7 - TIMER INTERRUPT AFTER WAIT INSTRUCTION: TIMING
Timer

f----.I- tTL

lIE",,",

interna.
Clock

,Counter = $OO~tTL TL

--I

fe---t-tTH
TCRb7

t---t IV AS H ~ n------+--=-n + 1--+--=r1 + 2 -+--=-~n + 3 ----+--=-n + 4 ~ + 5----+---=.n + 6---+--=..n + 7--l

AS
OS
ljnmux

A~~~~1Ls - f i
Mux BO-B7
Address/Data Bus

R/W

A _;'

A ,

•

L

_.....

- - - - - - - - - - . - - d-- ---~
Walt Op Co e
t-,

7//T//l//I///

'

"
--- -

--- -

-- -

--- -

New PCrl

" '-:I'

"---

New PCl 1st Op Code lnt

ROlltlne

\

/

s:

o

...I.

~
Q)

CO

o

(J1

m
N

FIGURE 8 - INTERRUPT RECOVERY FROM STOP INSTRUCTION: TIMING

OSC2 *

11ll/J/71Z717Z7III7!I1 . . .

IRO

\

---

?

7 72

1Z/I7!JITITIllvt:p;fl7Iflflfl/Tfl!I//flIITllflIITRI/I/IJT/lflT!I/II1/Ifl////11l!!ullJZ/l11i
19_20_t_ey_t*_----.J~r__----------------_ _ _ _ _ _ __

t_tIL_A_SH_-t-__

AS
DS

U)

m
"""'-I
--\.

Unmux

A8-A12

ttl

Address Bus - f i
A
\J\""'~'\
Mux BO-B7
Addressl Data
Bus
Stop Op Code
R/W '§'

~-~~----~

*:

Represents the internal gating of the OSCl input pin.
teye is one instruction eycle (for fosc = 5 MHz, teye = 1 I's)

'"

\L--

,~-----------------------------

A

"-+I----

1st Op Code
Int Routine

MC146805E2

FUNCTIONAL PIN DESCRIPTION
VDD AND VSS
VDD and VSS provide power to the chip. VDD provides
power and VSS is ground.

TIm

(MASKABLE INTERRUPT REQUEST)
IRQ is both a level-sensitive and edge-sensitive input
which can be used to request an interrupt sequence. The
M PU completes the current instruction before it responds to
the request. If TAO is low and the interrupt mask bit (I bit) in
the condition code register is clear, the MPU begins an interrupt sequence at the end of the current instruction. The interrupt circuit recognizes both a "wire ORed" level as well as
pulses on the TRO line (see Interrupt section for more
details). TAO requires an external resistor to VDD for "wire
OR" operation.

I

RESET

The RESET input is not required for start-up but can be
used to reset the MPU internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
TIMER

The TIMER input is used for clocking the on-chip timer.
Refer to Timer section for a detailed description.
AS (ADDRESS STROBE)

Address strobe (AS) is an output strobe used to indicate
the presence of an address on the 8-bit multiplexed bus. The
AS line is used to demultiplex the eight least significant address bits from the data bus. A latch controlled by address
strobe should capture addresses on the negative edge. This
output is capable of driving one standard TTL load and 130
pF and is available at f osc + 5 when the M PU is not in the
WAIT or STOP states.
OS (DATA STROBE)

This output is used to transfer data to or from a peripheral
or memory. DS occurs anytime the MPU does a data read or
write. DS also occurs when the MPU does a data transfer to
or from the MPU internal memory. Refer to Table 2 and
Figure 4 for timing characteristics. This output is capable of
driving one standard TTL load and 130 pF. DS is a continuous signal at fosc + 5 when the MPUis not in the WAIT
or STOP state. Some bus cycles are redundant reads of
opcode bytes.

R/W (READ/WRITE)
The R/W output is used to indicate the direction of data
transfer for both internal memory and I/O registers, and external peripheral devices and memories. This output is used
to indicate to a selected peripheral whether the MPU is going
to read or write data on the next data strobe (R/W
low = processor write; R/W high = processor read) .. The
R/W output is capable of driving one standard TTL' load and
130 pF. The normal standby state is read (high),
A8-A12 (HIGH ORDER ADDRESS LINES)

The A8-A 12 output lines constitute the higher order nonmultiplexed addresses. Each output line is capable of driving
one standard TTL load and 130 pF.

BO-B7 (ADDRESS/DATA BUS)

The BO-B7 bidirectional lines constitute the lower order
addresses and data. These lines are mUltiplexed, with address present at address strobe time and data present at data
strobe time. When in the data mode, these lines are bidirectional, transferring data to and from memory and peripheral
devices as indicated by the R/W pin. As outputs in either the
data or address modes, these lines are capable of driving one
standard TTL load and 130 pF.
OSC1,OSC2
The MCl46805E2 provides for two types of oscillator inputs - crystal circuit or external clock. The two oscillator
pins are used to interface to a crystal circuit, as shown in
Figure 5. If an external clock is used, it must be connected to
OSC1. The input at these pins is divided by five to form the
cycle rate seen on the AS and DS pins. The frequency range
is specified by fos c . The OSCl to bus transitions relationships are provided in Figure 9 for system designs using
oscillators slower than 5 MHz.
CRYSTAL - The circuit shown in Figure 5 is recommended when using a crystal. The internal oscillator is deSigned to
interface with an AT-cut parallel resonant quartz crystal
resonator in the frequency range specified for fosc in the
electrical characteristics table. An external CMOS oscillator
is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time.
EXTERNAL CLOCK - An external clock should be applied to the OSCl input with the OSC2 input not connected,
as shown in Figure 10.

LI (LOAD INSTRUCTION)

This output is used to indicate that a fetch of the next opcode is in progress. LI remains low during an external or
timer interrupt. The LI output is used only for certain debugging and test systems. For normal operations this pin is not
connected. The LI output is capable of driving two standard
LSTTL loads and 50 pF. This signal overlaps data strobe.

PAO-PA7
These eight pins constitute input/ output port A. Each line
is individually programmed to be either an input or output
under software control via its data direction register as
shown in Figure 11 (b). An I/O pin is programmed as an output when the corresponding DDR bit is set to a "1", and as
an input when it is set to a "0". In the output mode the bits
are latched and appear on the corresponding output pins. An
MPU read of the port bits programmed as outputs reflects
the last value written to that location. When programmed as
an input, the input data bit(s) are not latched. An MPU read
of the port bits programmed as inputs reflects the current
status of the corresponding input pins. The I/O port timing is
shown in Figure 3. See typical I/O port circuitry in Figure 11.
During a power-on reset or external reset, all lines are configured as inputs (zero in data direction register). The output
port register is not initialized by reset. The TTL compatible
three-state output buffers are capable of driving one standard TTL load and 50 pF. The DDR is a read/write register.

3-672

MC146805E2

FIGURE 9 -

OSC1 TO BUS TRANSITIONS

OSC1

AS

OS

I

R/Vii

A8-A12

BO-B7
MPU Read

BO-B7
MPU Write

----I

*Read data "latched" on OS fall

FIGURE 10 -

EXTERNAL CLOCK CONNECTION

The internal memory space is located within the first 128
bytes of memory (first half of page zero) and is comprised of
the i/O port locations, timer locations, and 112 bytes of
RAM. The MPU can read from or write to any of these locations. A program write to on-chip locations is repeated on
the external bus to permit off-chip memory to duplicate the
content of on-chip memory. Program reads to on-chip locations also appear on the external bus, but the MPU accepts
data only from the addressed on-chip location. Any read
data appearing on the input bus is ignored.
The stack pointer is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to
$OO7F and it is decremented as data is pushed onto the
stack. When data is removed from the stack, the stack
pointer is incremented. A maximum of 64 bytes of RAM is
available for stack usage. Since most programs use only a
small part of the allotted stack locations for interrupts and/ or
subroutine stacking purposes, the unused bytes are usable
for program data storage.
All memory locations above location $OO7F are part of the
external memory map. In addition, ten locations in the I/O
portion of the lower 128 bytes of memory space, as shown in

0$C1 39
OSC2
No
Connection
(NC)

38
MC146805E2

PBO-PB7
These eight pins interface with input/output port B. Refer
to PAO-PA7 description for details of operation.

MEMORY ADDRESSING
The MC146805E2 is capable of addressing 8192 bytes of
memory and I/O registers. The address space is divided into
internal memory space and external memory space, as
shown in Figure 12.

3-673

MC146805E2

FIGURE 11 -

TYPICAL PORT I/O CIRCUITRY
(a)

To
And
From

CPU

I

(b)

Data Direction
Register

$0004

Port A
Register

$0000

Pin

PA7

PA6

PA5

PA4

PA3

PAl

PAl

PAO

Data Direction
Register

$0005

Port B
Register

$0001

Pin

PB7

PB6

PB5

PB4

PB3

PB2

PBl

TABLE 3 - I/O PIN FUNCTIONS

R/W

DDR

0

0

0

1

1

0

1

1

I/O Pin Functions
The I/O pin is in input mode Data IS written
into the output data latch
Data is written into the output data latch and
output to the I/O pin
The state of the I/O pin is read
The I/O pin is in an output mode The output
data latch is read

3-674

PBO

MC146805E2

Figure 12. are part of the external memory map. All of the external memory space is user definable except the highest 10
locations. Locations $1 FF6 to $1 FFF of the external address
space are reserved for interrupt and reset vectors (see
Figure 121.

INDEX REGISTER (X)

The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index
register is also used for data manipulations with the readmodify-write type of instructions and as a temporary storage
register when not performing addressing operations.

REGISTERS
The MC146805E2 contains five registers as shown in the
programming model in Figure 13. The interrupt stacking
order is shown in Figure 14.
ACCUMULATOR (AI

PROGRAM COUNTER (PC)

This accumulator is an 8-bit general purpose register used
to hold operands and results of arithmetic calculations and
data manipulations.

The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the
processor.

FIGURE 12 -

A"~'{

Via
Page 0
Direct
Addressing

MPU ADDRESS MAP
$0000

I/O Ports
Timer
RAM

127
128

Port A Data Register

$0000

Port B Data Register

$0001

External Memory Space

$0002

External Memory Space

$0003

Port A Data Direction Register

$0004

1
$007F
$0080

255
256 ~-

\

--------

4

$OOFF
$0100

Port B Data Direction Register

$0005

External Memory Space

$0006

External Memory Space

$0007

6

External
Memory
Space
18064 Bytes)

9

Timer Data Register

$0008

Timer Control Register

$0009

10

SoooA
External Memory
Space
$oooF

15
16

$0010

RAM
1112 Bytes)

63
64 I-

$003F

/ 7 $0040
;-

81821- -

-

-

-

-

w..::t

~I~ I~er~t.:r0~

-

-

~at:...?n! $lFF6-$lF~7

Timer Interrupt
Interrupt
Vectors
{

Ext;;;ailrn;ru; - SWI _ _ _ _
-__

F~B

-

$1 FFA-$l

-- -

-

\
$lFFC-$lFFD
I

__

/'

$1 FF8-$1 FF9

!- -

8191L-_ _ _ _ _ _ _ _ _ _ _---01$1 FFE-$l FF~27 ~

3-675

/'

/'

/'

/

/

/ , / Stack 164 Bytes Max)

/'
/

f

$007F

I

MC146805E2

FIGURE 13 -

PROGRAMMING MODEL

0
1 Accumulator
0

7
A

1
7

I

12

I

X

Index Register

0

8 7
PCl

PCH

12
6
101010101010111

Program Counter

0

I

SP

Stack Pointer

CC

l§
1

I

FIGURE 14 -

N

Z

C

Condition Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry

STACKING ORDER
Stack

1T1I 1I
Increasing Memory
Addresses

1:

N

Condition Code Register
Accumulator
Index Register

01 0I 0I

PCH
PCL

11

Decreasing Memory
Addresses

T

Unstack
NOTE: Since the stack pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is in
the reverse order.

STACK POINTER (SP)
The stack pointer is a 13-bit register containing the address of the next free location on the stack. When accessing
memory, the seven most significant bits are permanently set
to 0000001. They are appended to the six least significant
register bits to produce an address within the range of $OO7F
to $0040. The stack area of RAM is used to store the return
address on subroutine calls and the machine state during interrupts. During external or power-on reset, and during a
"reset stack pointer" instruction, the stack pointer is set to
its upper limit ($OO7Fl. Nested interrupts and/or subroutines
may use up to 64 (decimal) locations, beyond which the
stack pointer "wraps around" and points to its upper limit,
thereby losing the previously stored information. A
subroutine call occupies two RAM bytes on the stack, while
an interrupt uses five bytes.

carry occurs between bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in binary coded
decimal addition subroutines.
INTERRUPT MASK BIT (I) - When the I bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I bit is set, the interrupt is latched and will
be processed when the I bit is next cleared.
NEGATIVE BIT (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipulation was
negative (bit 7 in the result is a logical one).
ZERO BIT (Z) - When set, this bit indicates that the result
of the last arithmetic, logical, or data manipulation was zero.
CARRY BIT (C) .- The C bit is set when a carry or a borrow out of the ALU occurs during an arithmetic instruction.
The C bit is also modified during bit test, shift, rotate, and
branch types of instruction.

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate the results of the instruction just executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each of the
five bits is explained below.

RESETS
The MC146805E2 has two reset modes: an active low external reset pin (RESET) and a power-on reset function; refer
to Figure 5.

HALF CARRY BIT (H) - The H bit is set to a one when a

3-676

MC146805E2

RESET (PIN #1)

TIMER INTERRUPT

The RESET input pin is used to reset the MPU and provide
an orderly software start-up procedure. When using the
external reset mode, the RESET pin must stay low for a minimum of one tRL. The RESET pin is provided with a Schmitt
trigger to improve its noise immunity capability.

If the timer mask bit (TCR6) is cleared, then each time the
timer decrements to zero (transitions from $01 to $(0) an interrupt request is generated. The actual processor interrupt
is generated only if the interrupt mask bit of the condition
code register is also cleared. When the interrupt is recognized, the current state of the machine is pushed onto the
stack and the I bit in the condition code register is set. This
masks further interrupts until the present one is serviced.
The processor now vectors to the timer interrupt service
routine. The address for this service routine is specified by
the contents of $1 FF8 and $1 FF9 unless the processor is in a
WAIT mode, in which case users of mask versions BP4XXXX and AW9XXXX should refer to the appendix for additional information regarding exceptions to this function. The
contents of $1 FF6 and $1 FF7 specify the service routine.
Also, software must be used to clear the timer interrupt request bit (TCR7). At the end of the timer interrupt service
routine, the software normally executes an RTI instruction
which restores the machine state and starts executing the interrupted program.

POWER-ON RESET

The power-on reset occurs when a positive transition is
detected on VOO. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external reset pin is low at the end of the 1920
tcyc time out, the processor remains in the reset condition.
Either of the two types of reset conditions causes the
following to occur:
- Timer control register interrupt request bit (bit 7) is
cleared to a "0".
- Timer control register interrupt mask bit (bit 6) is set to
a "1".
- All data direction register bits are cleared to a "0" (inputs).
-

Stack pointer is set to $007F.
The address bus is forced to the reset vector ($1 FFE,
$1FFF)'

Condition code register interrupt mask bit (I) is set to a
"1".
STOP and WAIT latches are reset.
External interrupt latch is reset.
All other functions, such as other registers (including output ports), the timer, etc., are not cleared by the reset conditions.

INTERRUPTS
The MCl46805E2 may be interrupted by one of three different methods: either one of two maskable hardware interrupts (external input or timer) or a non-maskable software interrupt (SWI). Systems often require that normal processing
be interrupted so that some external event may be serviced.
Interrupts cause the processor registers to be saved on the
stack and the interrupt mask set to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and a return to normal processing.
The stacking order is shown in Figure 14.
Unlike RESET, hardware interrupts do not cause the current instruction excution to be halted, but are considered
pending until the current instruction execution is complete.
When the current instruction is complete, the processor
checks all pending hardware interrupts and if. unmasked,
proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. Refer to Figure 15 for the interrupt and instruction
processing sequence.

3-677

EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register is
cleared and the external interrupt pin IRQ is "low," then the
external interrupt occurs. The action of the external interrupt
is identical to the timer interrupt with the exception that the
service routine address is specified by the contents of $1 FFA
and $lFFB. The interrupt logic recognizes both a "wire
ORed" level and pulses on the external interrupt line. Figure
16 shows both a functional diagram and timing for the interrupt line. The timing diagram shows two different treatments
of the interrupt line (iRQ) to the processor. The first configuration shows many interrupt lines "wire ORed" to form
the interrupts at the processor. Thus, if after servicing an interrupt the IRQ remains low, then the next interrupt is
recognized. The second method is single pulses on the interrupt line spaced far enough apart to be serviced. Users of
mask versions BP4XXXX and AW9XXXX should refer to the
appendix regarding exceptions to this function. The
minimum time between pulses is a function of the length of
the interrupt service routine. Once a pulse ocurs, the next
pulse should not occur until the MPU software has exited the
routine (an RTI occurs). This time (tILiU is obtained by adding 20 instruction cycles (one cycle tcyc = 5/fosc) to the
total number of cycles it takes to complete the service
routine including the RTI instruction; refer to Figure 6.
SOFTWARE INTERRUPT (SWI)

The software interrupt is an executable instruction. The
action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. The service
routine address is specified by the contents of memory locations $1FFC and $1FFO. See Figure 15 for interrupt arid instruction processing flowchart.
STOP
The STOP instruction places the MC146805E2 in a low
power consumption mode. In the STOP function the internal
oscillator is turned off, causing all internal processing and
the timer to be halted; refer to Figure 17. The OS and AS
lines go to a low state and the R/W line goes to a high state.

I

MC146805E2

FIGURE 15 -

I

RESET AND INTERRUPT PROCESSING FLOWCHART

Stack
PC, X, A, CC

O-DDRs
CLR iRCi Logic
FF-Timer
7F-Prescaler
7F--:-TCR

Timer
Put 1FFE on
Address Bus

Load PC From:
SWI: 1FFC/l FFD
iRCi: lFFA/lFFB
TIMER: lFF8/1FF9
Timer Wait: 1FF6/1 FF7

Fetch
Instruction

SWI

Load PC
from
lFFE/lFFF

Execute All
Instruction
Cycles

3-678

MC146805E2

FIGURE 16 - EXTERNAL INTERRUPT
(a) Interrupt Functional Diagram

Voo
o

External
Interrupt
Request

01------1

>-......I - - - - - Q C

Interrupt Pin

I Bit (CCR)

Power-On Reset

I

External Reset
External Interrupt
Being Serviced

(b) Interrupt Mode Diagram
(1)

}

----

IRO (MPU)IL_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

(2)

~

~

U

IRO~tILIH

Wire ORed Condition
If after servicing an interrupt the IRO remains low, then the next Interrupt IS
recognized.

·~1

t I L l L - - - -...

3-679

Pulse Condition
The minimum pulse width (tILlH) is one
tcyc· The period tlLlL should not be less
than the number of teyc cycles it takes to
execute the interrupt service routine plus
20 tcyc cycles.

MC146805E2

The multiplexed address/data bus goes to the data input
state (as shown in Figure 8). The high order address lines remain at the address of the next instruction. The MPU remains in the STOP mode until an external interrupt or reset
occurs.
During the STOP mode, timer control register (TCR) bits 6
and 7 are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. External
interrupts are enabled in the condition code register. All
other registers and memory remain unaltered. All I/O lines
remain unchanged.
FIGURE 17 -

STOP FUNCTION FLOWCHART

which is allowed to count in a normal sequence. The R/W
line goes to a high state, the multiplexed address/ data bus
goes to the data input state, and the DS and AS lines go to
the low state (as shown in Figure 7). The high order address
lines remain at the address of the next instruction. The MPU
remains in this state until an external interrupt, timer interrupt. or a reset occurs.
During the WAIT mode, the I bit in the condition code
register is cleared to enable interrupts. All other registers,
memory, and I/O lines remain in their last state. The timer
may be enabled to allow a periodic exit from the WAIT
mode. If an external and a timer interrupt occur at the same
time, the external interrupt is serviced first; then, if the timer
interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer WAIT interrupt) is serviced since the MPU is no longer in the WAIT
mode.

TIMER

II

Stop Oscillator
And All Clocks
TCR Bit 7-0
TCR Bit 6-1
Clear I Bit

Yes

WAIT
The WAIT instruction places the MC146805E2 in a low
power consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode; refer to Table
1. In the WAIT function, the internal clock is disabled from
all internal circuitry except the timer circuit; refer to Figure
18. Thus, all internal processing is halted except the timer

The MPU timer contains a single 8-bit software programmable counter (timer data register) with 7-bit software
selectable prescaler. Figure 19 shows a block diagram of the
timer. The counter may be preset under program control and
decrements towards zero. When the counter decrements to
zero, the timer interrupt request bit, i.e., bit 7 of the timer
control register (TCR), is set. Then if the timer interrupt is
not masked, i.e., bit 6 of the TCR and the I bit in the condition code register are both cleared, the processor receives an
interrupt. After completion of the current instruction, the
processor proceeds to store the appropriate registers on the
stack, and then fetches the timer interrupt vector from locations $1 FF8 and $1 FF9 in order to begin servicing the interrupt. If the MPU is interrupted by the timer while in the
WAIT mode, the interrupt vector fetch would be from locations $1 FF6 and $1 FF7.
The counter continues to count after it reaches zero,
allowing the software to determine the number of internal or
external input clocks since the timer interrupt request bit was
set. The counter may be read at any time by the processor
without disturbing the count. The content of the counter
becomes stable prior to the read portion of a cycle and does
not change during the read. The timer interrupt request bit
remains set until cleared by the software. If a read occurs
before the timer interrupt is serviced, the interrupt is lost.
TCR7 may also be used as a scanned status bit in a noninterrupt mode of operation (TCR6= 1).
The prescaler is a 7-bit divider which is used to extend the
maximum length of the timer. Bit 0, bit 1, and bit 2 of the
TCR are programmed to choose the appropriate prescaler
output which is used as the counter input. The processor
cannot write into or read from the prescaler; however, its
contents are cleared to all "Os" by the write operation into
TCR when bit 3 of the written data equals 1, which allows for
truncation-free counting.
The timer input can be configured for three different
operating modes, plus a disable mode, depending' on the
value written to the TCR4, TCR5 control bits. Refer to the
Timer Control Register section.
TIMER INPUT MODE 1
If TCR4 and TCR5 are both programmed to a "0", the input to the timer is from an internal clock and the external
TIMER input is disabled. The internal clock mode can be

3-680

MC146805E2

FIGURE 18 -

WAIT I'UNCTION FLOWCHART

Oscillator Active
Clear I Bit
Timer Clock Active
All Other Clocks
Stop

I

used for periodic interrupt generation, as well as a reference
in frequency and event measurement. The internal clock is
the instruction cycle clock and is coincident with address
strobe (AS) except during a WAIT instruction. During a
WAIT instruction the AS pin goes to a low state but the internal clock to the timer continues to run at its normal rate.

count in this mode is ± 1 clock and therefore accuracy improves with longer input pulse widths.

TIMER INPUT MODE 2
With TCR4= 1 and TCR5= 0, the internal clock and the
TIMER input pin are ANDed to form the timer input signal.
This mode can be used to measure external pulse widths.
The external timer input pulse simply turns on the internal
clock for the duration of the pulse. The resolution of the

3-681

TIMER INPUT MODE 3
If TCR4= and TCR5= 1, then all inputs to the timer are
disabled.

°

TIMER INPUT MODE 4
If TCR4= 1 and TCR5= 1, the internal clock input to the
timer is disabled and the TIMER input pin becomes the input
to the timer. The external TIMER pin can, in this mode, be
used to count external events as well as external frequencies
for generating periodic interrupts.
Figure 19 shows a block diagram of the timer subsystem.

MC146805E2

FIGURE 19 - TIMER BLOCK DIAGRAM

External
Input

Cleared by
TCR3
'~

I

Write

Read

Interrupt

____________~\/~____________--J/

Software Functions
NOTES:
1. Prescaler and timer data register are clocked on the falling edge of the internal clock (AS) or external input.
2. Timer data register is written to during data strobe (oS) and counts down continuously.

TIMER CONTROL REGISTER (TCR)

TCR5 TCR4
0
o
1

76543210

Internal clock (AS) to timer
AND of internal clock (AS) and TIMER
pin to timer
Inputs to timer disabled
TIMER pin to timer

ITCR7lTCR61TCR51TCR41TCR31TCR21TCR11TCROI
All bits in this register except bit 3 are read/write bits.

TCR7 - Timer interrupt request bit: bit used to indicate
the timer interrupt when it is logic "1".
1 - Set whenever the counter decrements to zero, or under program control.
o - Cleared on external reset, power-on reset, STOP instruction, or program control.

1
0
; ;
1
1

TCR3 - Timer Prescaler Reset bit: writing a "1" to this bit
resets the prescaler to zero. A read of this location always
indicates a "0" (unaffected by RESET).
TCR2, TCRl, TCRO - Prescaler address bits: decoded to
select one of eight outputs of the prescaler (unaffected by
RESET).

TCR6 - Timer interrupt mask bit: when this bit is a logic
"1" it inhibits the timer interrupt to the processor.

TCR2

0

1 - Set on external reset, power-on reset, STOP instruction, or program control.
Cleared under program control.

0
0
0
1
1
1
1

o-

TCR5 - External or internal bit: selects the input clock
source to be either the external TIMER pin or the internal
clock (unaffected by RESET).
1 - Select external clock source.
Select internal clock source (AS),

o-

TCR4 - External enable bit: control bit used to enable the
external TIMER pin (unaffected by RESET).
1 - Enable external TIMER pin.
Disable external TIMER pin.

o-

Prescaler
TCRl
TCRO
0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1

Result
...1
... 2
... 4
... 8
... 16
... 32
... 64
...128

INSTRUCTION SET
The MPU has a set of 61 basic instructions. They can be
divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the instructions within a given type are presented in individual
tables.

3-682

MC146805E2

REGISTER/MEMORY INSTRUCTIONS

Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to
subroutine (JSR) instructions have no register operand.
Refer to Table 4.
READ-MODIFY -WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero (TST) instruction is an exception to the read-modifywrite sequence since it does not modify the value. Refer to
Table 5.
BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is
met, otherwise no operation is performed. Branch instructions are two byte instructions. Refer to Table 6.
BIT MANIPULATION INSTRUCTIONS

The MPU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where all
port registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 25610cations. The bit set, bit clear and bit test, and branch functions
are all implemented with a single instruction. For the test and
branch instructions, the value of the bit tested is also placed
in the carry bit of the condition code register. Refer to Table

7.

CONTROL INSTRUCTIONS

These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 8.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 9.
OPCODE MAP SUMMARY
Table 10 is an opcode map for the instructions used on the
MCU.

ADDRESSING MODES
The MPU uses ten different addressing modes to provide
the programmer with an opportunity to optimize the code to
all situations. The various indexed addressing modes make it
possible to locate data tables, code conversion tables, and
scaling tables anywhere in the memory space. Short indexed
accesses are single byte instructions, while the longest instructions (three bytes) permit accessing tables throughout
memory. Short and long absolute addressing is also included. Two byte direct addressing instructions access all data
bytes in most applications. Extended addressing permits
jump instructions to reach all memory. Table 9 shows the
addressing modes for each instruction, with the effects each
instruction has on the condition code register. An opcode
map is shown in Table 10.
The term "effective address" or EA is used in describing
the various addressing modes, and is defined as the address
to or from which the argument for an instruction is fetched

or stored. The ten addressing modes of the processor are
described below. Parentheses are used to indicate "contents
of," an arrow indicates "is replaced by," and a colon indicates concatenation of two bytes.
INHERENT·
In inherent instructions all the information necessary to execute the instruction is contained in the opcode. Operations
specifying only the index register or accumulator, and no
other arguments, are included in this mode.
IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediatley following the opcode. Immediate addressing is used to access constants which do not change during
program execution (e.g., a constant used to initialize a loop
counter).

EA= PC+ 1; PC-PC+2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a Single two byte instruction. This includes all on-chip RAM and I/O registers
and up to 128 bytes of off-chip ROM. Direct addressing is efficient in both memory and speed.
EA= (PC + 1); PC-PC + 2
Address Bus High-O; Address Bus Low-(PC+ 1)
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are
capable of referencing arguments anywhere in memory with
a single three byte instruction. When using the Motorola
assembler, the user need not specify whether an instruction
uses direct or extended addressing. The assembler
automatically selects the most efficient addressing mode.
EA= (PC+ 1):(PC+2); PC-PC+3
Address Bus High-(PC + 1); Address Bus Low-(PC + 2)
INDEXED, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is used to move a pointer through a table or
to address a frequently referenced RAM or I/O location.
EA=X; PC-PC+1
Address Bus High-O, Address Bus Low-X
INDEXED, 8-BIT OFFSET

Here the EA is obtained by adding the contents of the byte
following the opcode to that of the index register; therefore,
the operand is located anywhere within the lowest 511
memory locations. For example, this mode of addressing is
useful for selecting the m-th element in an n element table.
All instructions are two bytes. The contents of the index
register (X) is not changed. The contents of (PC + 1) is an
unsigned 8-bit integer. One byte offset indexing permits
look-up tables to be easily accessed in either RAM or ROM.
EA= X+ (PC+ 1); PC-PC + 2
Address Bus High -K; Address Bus Low-X + (PC + 1)
where: K = The carry from the addition of X + (PC + 1)

3-683

I

MC146805E2

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode the effective
address is the sum of the contents of the unsiged 8-bit index
register and the two unsigned bytes following the opcode.
This addressing mode can be used in a manner similar to indexed 8-bit offset, except that this three byte instruction
allows tables to be anywhere in memory (e.g., jump tables in
ROM). As with direct and extended, the M6805 assembler
determines the most efficient form of indexed offset - 8 or
16 bit. The content of the index register is not changed.
EA= X+ [(PC+ 1):(PC+2)); PC ..... PC+3
Address. Bus High-(PC + 1) + K
Address Bus Low-K + (PC+2)
where: K = The carry from the addition of X + (PC + 2)

opcode. The bit set and clear instructions occupy two bytes,
one for the opcode (including the bit number) and the second to. address the byte which contains the bit of interest.
EA= (PC+ 1); PC-PC+2
Address Bus High~O; Address Bus Low-(PC+ 1)
BIT TEST AND BRANCH

Bit test and branch is a combination of direct addressing,
bit addressing, and relative addressing. The bit address and
condition (set or clear) to be tested are part of the opcode.
The address of the byte to be tested is in the single byte immediately following the opcode byte (EA 1), The signed
relative 8-bit offset is in the third byte (EA2) and is added to
the PC if the specified bit is set or clear in the specified
memory location. This single three byte instruction allows
the program to branch based on the condition of any bit in
the first 256 locations of memory.
EA1 = (PC+ 1)
Address Bus High-O; Address Bus Low-(PC+ 1)
EA2 = PC + 3 + (PC + 2); PC -EA2 if branch taken;
otherwise, PC ..... PC + 3

RELATIVE

I

Relative addressing is used only in branch instructions. In
relative addressing the content of the 8-bit signed byte
f6~Wing the opcode (the offset) is added to the PC if and
onl if the branch condition is true. Otherwise, control proce ds to the next instruction. The span of relative addressing
is limited to the range of -126 to + 129 bytes from the
branch instruction opcode location. The Motorola assembler
calculates the proper offset and checks to see if it is within
the span of the branch.
EA= PC+2+ (PC+ 1); PC ..... EA if branch is taken;
otherwise, PC ..... PC + 2

SYSTEM CONFIGURATION
Figures 20 through 25 show in general terms how the
MC146805E2 bus structure may be utilized. Specified interface details vary with the various peripheral and memory
devices employed.
.
Table 11 provides a detailed description of the information
present on the bus, read/write (R/W) pin and the load instruction (LI) pin during each cycle for each instruction.
This information is useful in comparing actual with expected results during debug of both software and hardware
as the control program is executed. The information is
categorized in groups according to addressing mode and
number of cycles per instruction.

BIT SET/CLEAR

Direct addressing and bit addressing are combined in instructions which set and clear individual memory and I/O
bits. In the bit set and clear instructions, the byte is specified
as a direct address in the location following the opcode. The
first 256 addressable locations are thus accessed. The bit to
be modified within that byte is specified with three bits of the

3·684

TABLE
4 -

3:

REGISTER/MEMORY INSTRUCTIONS
Addressing Modes

Direct

Immediate

#

Cycles

Bytes

3

C6

3

2

3

CE

2

4

C7

BF

2

4

CF

3

BB

2

3

CB

3

Cycles

Bytes

2

B6

2

2

2

BE

-

-

B7

2

Mnemonic

Bytes

LOA

A6

2

Load X from Memory

LOX

AE

Store A in Memory

STA

-

-

2

Function

#

#

#

Load A from Memory

Op
Code

#

#

#

Bytes

4

F6

1

3

4

FE

3

5

F7

5
4
4

#

#

Bytes

Cycles

3

5

DE

3

5

07

3

6

5

OF

3

6

4

DB

3

5

4

09

3

5

Cycles

Bytes

3

E6

2

4

06

1

3

EE

2

4

1

4

E7

2

5

FF

1

4

EF

2

FB

1

3

EB

2

F9

1

3

E9

2

.Op
Cycles Code

STX

-

ADD

AB

AOC

A9

2

2

B9

2

3

C9

3

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

3

EO

2

4

DO

3

5

3

4

F2

1

3

E2

2

4

02

3

5

SBC

A2

2

2

B2

2

3

C2

B4

2

3

C4

3

4

F4

1

3

E4

2

4

04

3

5

AND Memory to A

AND

A4

2

2

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

3

EA

2

4

OA

3

5

Exclusive OR Memory
with A

2

2

B8

2

3

C8

3

4

F8

1

3

E8

2

4

08

3

5

2

3

C1

3

4

F1

1

3

E1

2

4

01

3

5

2

3

C3

3

4

F3

1

3

E3

2

4

03

3

5

EOR

A8

CMP

A1

2

2

B1

w

Arithmetic Compare X
with Memorv

CPX

A3

2

2

B3

ex>

Bit Test Memory with
A (Logical Compare)

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

3

E5

2

4

05

3

5

~ Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSR

-

-

BO

5

CD

3

6

FO

1

5

ED

2

6

DO

3

7

1-

2
TABLE 5 -

READ-MODIFY-WRITE INSTRUCTIONS
Addressing Modes

Inherent (A)

Inherent (X)

Indexed
(No Offset)

Direct

Indexed
(8-Bit Offset)

Op
Code

#

#

#

#

#

#

#

Bytes

Cycles

Bytes

Cycles

Bytes

Cycles

Op
Code

#

Cycles

Op
Code

#

Bytes

Op
Code

#

Mnemonic

Op
Code

Bytes

Cycles

Increment

INC

4C

1

3

5C

1

3

3C

2

5

7C

1

5

6C

2

6

Decrement

DEC

4A

1

3

5A

1

3

3A

2

5

7A

1

5

6A

2

6

Clear

CLR

4F

1

3

5F

1

3

3F

2

5

7F

1

5

6F

2

6

Complement

COM

43

1

3

53

1

3

33

2

5

73

1

5

63

2

6

Negate
(2's Complement)

NEG

40

1

3

50

1

3

30

2

5

70

1

5

60

2

6

Rotate Left Thru Carry

ROL

49

1

3

59

1

3

39

2

5

79

1

5

69

2

6

Rotate Right Thru
Carry

ROR

46

1

3

56

1

3

36

2

5

76

1

5

66

2

6

Logical Shift Left

LSL

48

1

3

58

1

3

38

2

5

78

1

5

2

6

Logical Shift Right

LSR

44

1

3

54

1

3

34

2

5

74

1

5

68
64

2

6

Arithmetic Shift Right

ASR

47

1

3

57

1

3

37

2

5

17

1

5

67

2

6

T est for Negative
or Zero

TST

40

1

3

50

1

3

3D

2

4

70

1

4

60

2

5

Function

..

I

o....
~

#

#

Op
Code

Store X in Memory

Arithmetic Compare A
with Memory

(J1

#

Cycles

Op
Code

Indexed
(l6-Bit Offset)

Add Memory to A
Add Memory and
Carry to A

Subtract Memory from
A with Borrow

a,

Indexed
(8-Bit Offset)

Indexed
(No Offset)

Extended

Op
Code

Op
Code

I

en
CO

o

UI

m

N

MC146805E2

TABLE 6 -

BRANCH INSTRUCTIONS
Relative Addressing Mode
Mnemonic

Op
Code

#

#

Bytes

Cycles

Branch Always

BRA

20

2

3

Branch Never

BRN

21

2

3

Branch IFF Higher

BHI

22

2

3

Branch IFF Lower or Same

BLS

23

2

3

Branch IFF Carry Clear

BCC

24

2

3

!BHSI

24

2

3

BCS

25

2

3

(BLOI

25

2

3

Branch IFF Not Equal

BNE

26

2

3

Branch I FF Equal

BEQ

27

2

3

Branch IFF Half Carry Clear

BHCC

28

2

3

Branch IFF Half Carry Set

BHCS

29

2

3

Branch I FF Plus

BPL

2A

2

3

Branch IFF Minus

BMI

2B

2

3

Function

(Branch IFF Higher or Same I
Branch IFF Carry Set
(Branch IFF Lower!

I

Branch IFF Interrupt Mask Bit is Clear

BMC

2C

2

3

Branch IFF Interrupt Mask Bit is Set

BMS

20

2

3

Branch IFF Interrupt Line is Low

BIL

2E

2

3

Branch IFF Interrupt Line is High

BIH

2F

2

3

Branch to Subroutine

BSR

AO

2

6

TABLE 7 -

BIT MANIPULATION INSTRUCTIONS
Addressing Modes
Bit Set/Clear

Mnemonic

Function

Op
Code

Bit Test and Branch

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles
5

Branch IFF Bit n is Set

BRSET n (n=O

71

-

-

-

2-n

3

Branch IFF Bit n is Clear

BRCLR n (n=O .. 71

-

-

-

01 + 2-n

3

5

Set Bit n

BSET n (n=O . .71

10 + 2-n

2

5

-

-

-

Clear Bit n

BCLR n (n=O .. 71

11 + 2-n

2

5

-

-

-

TABLE 8 -

CONTROL INSTRUCTIONS
Inherent
.---.-~
Mnemonic

Function

Op
Code

#

#

Bytes

Cycles
2~

Transter A to X

TAX

Transfer X to A

TXA

97
9F

1
1

Set Carry Bit

SEC

99

1

2
2

Clear Carry Bit

CLC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

10

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

RSP

9C

1

2

1

2

Stop

NOP
90
STOP-+- 8E

1

2

Walt

WAIT

8F

1

2

Reset Stack Pointer
No-Operation

-

.

3-686

I

MC146805E2

TABLE 9 - INSTRUCTION SET
Condition Codes

Addressing Modes
Mnemonic

Inherent

ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT

Immediate

Direct

Extended

X
X
X

X

x

X
X
X

X
X

.

X
X
X

Relative

Indexed
(No Offset)

Indexed
(8 Bits)

Indexed
(16 Bits)

X
X
X
X
X

X
X
X
X
X

X
X
X

Bit
Set!
Clear

Bit
Test &
Branch

H

I

A

A A A

A

11.111.111.

•

A A
A A A
A A A

••
•
•••
•
•••
A

X
X
X
X
X
X
X
X
X
X
X

X

X

X

X

N Z C

X

••
••
•••
••
•A

I

X
X
X
X
X
X
X
X
X
X
X

A

A

X
X
X
X
X

0
X

X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X

X

1

A
A 1
A A
A
A
A

••
• • •••
•A •A •
A A •

X
X
X
X
X

A A A
0 A A
A AlA

X
X
X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X

X

X

•A •A ••
A
A A A
•••
•A •A •A
••
•
•0 •A• •A •••
•A A •
A~

?

X

?

?

?

?

1

X
X

1

X
X
X
X
X
X
X

X

Condition Code Symbols
H

0
A
A
A
A
A
A

X

•
•0
•
•A

Half Carry (From Bit 3)
Interrupt Mask
N Negative (Sign Bit)
Z Zero
C Carry/Borrow

A
•
?

Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
Cleared
Set

3·687

•1

A A A

•
••
• A
•0 •
•

••
••
A •
••
••

iii
3:

(')

TABLE 10 - MC146805 CMOS INSTRUCTION SET OPCODE MAP

Bit ManiPulation

~

Read-Modlfy~Write

Branch

o

,

RFl

0000

0001

0010

InB~

2

DIR

INH

0011

0100

INH

IX

6

0101

Reaister {Memory

Control
IXl

5

4

3

""""

7

0110

INH

INH

8

9

1000

0111

IMM
A
1010

1001

5 I

EXT

DIR

1100

lOll

IXXll

2

3

0011

3

51
BCLRl 51
BLS 31
COM 51 COMA 31
COM X 3
COM
COM
2
BSC 2
AEL 2
DIR 1
INH 1
INH 12
IXI I 1
IX

BRSET3
3
BTB

~

"I

7

8

1000

9
1001
A
1010

B
1011

BRCLR3,5,'
3

__BJ8

I,

F
1111

2

~~

I B~~T4 I

I

LS~-,

INH

I?

j

LS~;-3

I

~

12

BCL~~e

12

BRSET751 BSET7 51
3
BTB 2
Bse 2

BM~EL
BIL

3

TSTD~ TST~NH

11

TST~NH

12

TST

IXI I 1

I,

CLRA

j

INH

I

CLRX 3
1

INH

I

CLR
2

IXI I

CLR

DIR

EXT
REL
BSC
BTB
IX
IXl
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed INo Offset!
Indexed, 1 Byte IB-Bitl Offset
Indexed, 2 Byte 116-Bitl Offset

,

T

TXA

11

I

51
1

INH

"3

51

WAIT L

IX I

3

12 STADIA 13 STAEXT I 3 STA IX2 I 2 STA IXI I 1 STA IX

11

EOR
I

51

1
1
1

ADO

1

0001

2

0010

3

0011

4

0100

5

0101

6

0110

7
0111

B

1000

IX

1001

--:r
IX
-3
IX

9

A
1010

B
lOll

'2
C

JMP

1100

"0
1
1

STX
STX
STX
STX
DIA I 3
EXT I 3
IX2 I 2
IXI I I

INH

ADC
ORA

...lXm..

IX

"3

-

..

Abbreviations for Address Modes
INH
A
X
IMM

41

STOP
INH

TST

AEL

BRCLRl ~R;~I
BIH-}
CLR
3
BTB 1 2 O\"L BSC 2
AEL I 2
DIR

I

3r--

~

3

12

II(

~

51

INCA
INCX
INC
INC
INH I 1
IXI I 1
INH I 2

5

CM~XT

CLC 21
EOR
EOR
EOR
EOR
INH 2
IMM I 2
DIA 13
EXT I 3
IX2 I 2
21
SEC
12 ADC
ADC ,X2 1 2 ADC ,X1 I
ADC
1
3
AD~XT
I
3
IMM 12
DIR
'NH
31
4
Cli
ORA
ORA
ORA
INH 12
IMM 12 ORADIH 1 j OR~XT I 3
IX2 2
IXI I
'2
<~
-4
SEI
ADD
ADD
ADD
ADD
ADD
INH 12
IMM 12
DIA 3
EXT I 3
IX2 2
IXI I
21-4-~3
RSP
JMP
JMP
JMP
JMP
INH
IX2 2
IXI I
DIA I 3
EXT I 3
'6
NOP
BSR
JSR
JSR
JSR
JSR
INH 12
AEL I 2
DIA I 3
EXT I 3
IX2 I 2
IXI I
3
"0
LOX
LOX
LOX
LOX
LOX
IMM 12
DIA I 3
EXT I 3
IX2 I 2
IXI I

51 DECA 3 '
DECX 3
DEC
DIA 1
INH 1 1
INH I 2 DEC ,X1 I 1

5

2 CMPDIR 13

BIT 21
BIT J
BIT
BIT
BIT
BIT
IMM 2
DIA 3
EXT 3
IX2 2
IXI I 1
21
4 1 - 51
--4
LOA
LOA
LOA
LOA
LOA
LOA
IMM 12
DIA I 3
EXT I 3
IX2 I 2
IXI I 1
IX

TAX,NH I

~

31
REL 2

SUB

4

~
o

CPX
CPX
CPX
CPX
3
EXT I 3
IX2 2
IXI I 1
IX
5 I
AND
2 AN?MM 1 2 ANDDIf< 1 3 AN~XT 1 3 AND ,x2 1 2 AND,X1 I 1
IX

RORA 3
RORX 31
ROR
ROR
1
INH 1
INH 2
IXI I 1
3
,,5 [ ASRA- 1 ASRX 31
ASR
ASR
DIA 1
INH 1
INH 2
IX 1 I 1

31
AS~
RaJ
2

BTB 1 2 o'''-llSC 2
5
BRCLR5
BCLR551
BMI
BTB 2
BSC 2
AEL

3

I ,BRCL~T6B

1110

....B.S..C.

F

E

CPX
CPX 3
DIR
IMM 12

I

o

E

2

BRSET55r-;;ET5,,51--~

BRSET6
3
BTB

1101

r~LR3 51

j

IX
1111

I
,,-----

10

5
5
BHCC 3
51
I
I
BRSET4
LSLX
LSL
LSL
IXI I 1
3
BTB 2
BSC 2
AEL 2
DIR 1
INH I 1
INH I 2
51
51
31
- 51
--3
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
BTB 2
sse 2
REL 2
DIR 1
INH 1
INH I 2
IXI I 1

C

1100

-- 3<[
BSET3 51
BNE
ROR 5
2
JiSC 2
REL 2
DlB

SWI
1

IX'
1110

0

CMP
I 3 CMP,X2 12 CMP,X1 I I
IX
I
4
3
SBC
SBC 31
SBC
SBC
SBC
SBC
IX2 2
IXI I 1
IX
IMM I 2
DIA 3
EXT I 3

CMP
IMM

AEL

6
0110
0111

Q)
Q)

BHI

2

0101

5

en

'r--

BSETl
BSC

5,----

BRCLRl
3
BTB

2

RTS
INH

LSR
LSR
BRSET251 BSET2 51
BCC 31
LSR 51
LSRA 31
LSRX 31
IXI I 1
3
BTB 2
Bse 2
REL 2
DTA 1
INH 1
INH I 2
5G-3
BRCLR2
BCLR,2
BCS
3
BTB 2
SSC 2
REL

4
0100

(..)

~

BRSETl
BTB

3

1X2
1101

SUB ,X1 I 1

2

0010

I

C

B

I? SU~MM

RTI

1

~
Q)
Q)

JSR
LOX

o

1101

E

1110

F

STX

1111

LEGEND
~.~+---------------~

Mnemonic
Bytes

~.
1

# of Cycles ------~

~

1

~X_

"

0000

~

Opcode in Hexadecimal

Opcode in Binary

..-=-:

Address Mode

o
m

UI

N

MC146805E2

FIGURE 20 -

CONNECTION TO CMOS PERIPHERALS

Chip
Enable

TYPical CMOS
Penpheral
(MC146818 etc)

MC146805E2
CMOS
Microprocessor

ADO-AD7

BO-B7

AS~__~A~d~d~re~s~s~S~tr~o~b~e__~IMAS
OS

Data Strobe

OS

R/W

Read/Write

R/W

IRQ
OSC1

Interrupt

IRQ

.! 19~H3..

CKOUT (MC146818)

RESET

FIGURE 21 -

RESET

CONNECTION TO CMOS MULTIPLEXED MEMORIES

MC146805E2
A8A 10

CMOS
Multiplexed
Memory
(MCM65516)

ADQO-AD07
Address Strobe

AS~--~~~~~~--~M

OS

Data Strobe

G

R/W

Read/Write

Vi

3-689

I

MC146805E2

FIGURE 22 -

CONNECTION TO M6800 PERIPHERALS

M6800
Peripherals

MC146805E2

AS

I

DS~____~D~a~ta~S~tr~o~be~__~

R/W ~____--,R..:.;e::.::a:.::d:.../W,-,,-,ri,,-,te~__~R/W
IRQ

Interrupt

RESET

IRQ
RESET

NOTE: In some cases, pullup resistors or other level
shifting techniques may be required on signals
going from NMOS to CMOS parts.

FIGURE 23 -

CONNECTION TO LATCHED NON-MULTIPLEXED CMOS ROM AND EPROM

BO-B7

Address/Data 8us

Data

QO-07
CMOS
Non-Muxed
AO-A7 Memory

MC146805E2

A8-A12

A8

t--------..,

R/W~----...

Output
Enable

DSr-------~~______~

Chip
Enable

AS~--------------------------------~

3-690

S

MC146805E2

FIGURE 24 -

CONNECTION TO STATIC CMOS RAMS

CMOS
Static
RAMs

MC146805E2
CMOS
Microprocessor
DO-D7

AO-A7

A8
A9

A8-A12

II

I---~E

DS~a-----------~

R/W

FIGURE 25 -

CONNECTION TO LATCHED NON-MULTIPLEXED CMOS RAM

Addressl Data Bus

Data

00-07

AO-A7

MC146805E2

CMOS
Non-Muxed
RAM

A8A12

A8

S

DS

R/W

Chip
Enable

AS

3-691

E

MC146805E2

TABLE 11 Address Mode
Instructions
Inherent

R/W
Pin

LI
Pin

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

1
0
0

Op Code
Op Code Next Instruction
Op Code Next Instruction

1
2

Op Code Address
Op Code Address + 1

1
1

1
0

Op Code
Op Code Next Instruction

1
2
3

Op Code Address
Op Code Address + 1
Stack Pointer
: Stack Pointer + 1
i Stack Pointer + 2
New Op Code Address

1
0
0
0
0
0

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Vector Address 1FFC (Hex)
Vector Address 1FFD (Hex)
Interrupt Routine Starting Address

1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1

1
0
0
0
0
0
0
0
0
0

Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code
Op Code
Op Code Next Instruction
Return Address (LO Byte)
Return Address (HI Byte)
Contents of Index Register
Contents of Accumulator
Contents of CC Register
Address of Int. Routine (HI Byte)
Address of Int. Routine (LO Byte)
Interrupt Routine First Opcode

8
9

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer +4
Stack Pointer + 5
New Op Code Address

1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0

Cycles

Cycle #

LSR LSL
ASR NEG
CLR ROL
COM ROR
DEC INC TST

3

1
2
3

TAX CLC SEC
STOP CLI SEI
RSP WAIT NOP TXA

2

RTS

6

4

5

I

6
1
2
3
4

SWI

10

5

6
7

8
9
10

RTI

9

SUMMARY OF CYCLE-BY-CYCLE OPERATION

1
2
3
4
5
6

7

Address Bus

1

Immediate
ADC EOR CPX
ADD LDA LOX
AND ORA BIT
SBC CMP SUB
Bit Setl Clear

2

1
2

Op Code Address
Op Code Address + 1

1
1

BSET n
BelR n

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand

1
1
1
1

0

0
0
0
0

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2
Op Code Address + 2 .

1
1
1
1
1

0
0
0
0

1

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

0
0
0
0

1

1

Data Bus

Op Code
Op Code Next Instruction
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
New Op Code

Op Code
Operand Data

Op Code
Address of Operand
Operand Data
Operand Data
Manipulated Data

Bit Test and Branch
BRSET n
BRCLR n

5

1

Op Code
Address of Operand
Operand Data
Branch Offset
Branch Offset

Relative
BeC BHI BNE BEQ
BeS BPL BHCC BLS
BIL BMC BRN BHCS
BIH BMI BMS BRA

BSR

3

6

2
3
1
2
3
4
5

6

3-692

1

0
1

0

Op Code
Branch Offset
Branch Offset
Op Code
Branch Offset
Branch Offset
First Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

MC146805E2

TABLE 11 - SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED)
Address Mode
Instructions

Cycles

Cycle #

JMP

2

1
2

ADC EOR CPX
ADD LDA LDX
AND ORA BIT
SBC CMP SUB

3

1
2

TST

4

STA
STX

4

LI

R/W
Pin

Pin

Op Code Address
Op Code Address + 1

1
1

0

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

0
0

Op Code Address
Op Code Address + 1
Address of Operand
Op Code Address + 2

1
1
1
1

0
0
0

Op Code Address
Op Code Adrress + 1
Op Code Address + 1
Address of Operand

1
1
1

Address Bus

Data Bus

Direct

LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

3
1
2

3
4
1
2

3
4
·1
2

5

3
4
5
1
2

5

JSR

3
4
5

Op Code Address
Op Code Address + 1
Operand Address
Operand Address
Operand Address

0
1
1
1
1

0
1
1
1

1

1

1

1

0
0
0
1

0
0
0
0
1

Op Code Address
Op Code Address + 1
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

0
0

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Jump Address
Op Code
Address of Operand
Operand Data
Op Code
Address of Operand
Operand Data
Op Code Next Instruction
Op Code
Address of Operand
Address of Operand
Operand Data
Op Code
Address of Operand
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Subroutine Address (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

Extended

3

JMP

1
2

3
ADC BIT ORA
ADD CMP LDX
AND EOR SBC
CPX LDA SUB

4

1
2

3
4
1
2

STA
STX

5

3
4
5
1
2

6

JSR

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
2
1
2

0
1
1
1
1

1

1

1

0
0
0
0
1

Op Code
Jump Address (HI Byte)
Jump Address (LO Byte)
Op Code
Address Operand (HI Byte)
Address Operand (LO Byte)
Operand Data
Op Code
Address of Operand (HI Byte)
Address of Operand (LO Byte)
Address of Operand (LO Byte)
Operand Data

0
0

0
0
0
0
0

Op Code
Address of Subroutine (HI Byte)
Address of Subroutine (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

Op Code Address
Op Code Address + 1

1
1

1
0

Op Code
Op Code Next Instruction

Op Code Address
Op Code Address + 1
Index Register

1
1
1

1

0
0

Op Code
Op Code Next Instruction
Operand Data

Op Code Address
Op Code Address + 1
Index Register
Op Code Address + 1

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register

1
1
1

0
0

0

0

Op Code Address
Op Code Address + 1
Index Register
I ndex Register
Index Register

1
1
1
1
0

1
0

Op Code Address
Op Code Address + 1
Index Register
Stack POinter
Stack POinter - 1

1
1
1
0

1
0
0

Indexed, No-Offset
JMP
ADC
ADD
AND
SBC

2
EOR CPX
LDA LDX
ORA BIT
CMP SUB

3

3

TST

4

STA
STX

4

1
2

3
4
1
2

3
4
1
2

LSL LSR DEC
ASR NEG INC
CLR ROL
COM ROR

5

JSR

5

3
4

5
1
2

3
4

5

3-693

0

1

1

0
0
0

0
0

Op Code
Op Code Next Instruction
Operand Data
Op Code Next Instruction
Op Code
Op Code Next Instruction
Op Code Next Instruction
Operand Data
Op Code
Op Code Next Instruction
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Op Code Next Instruction
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HI Byte)

I

MC146805E2

TABLE 11 -

Address Mode
Instructions

Cycles

SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED)

R/W
Pin

LI
Pin

Op Code Address
Op Code Address + 1
Op Code Address + 1

1
1
1

0
0

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset

1
1

Op Code Address
Op Code Address + 1
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Op Code Address + 2

1
1
1
1

Cycle #

Address Bus

Data Bus

Indexed 8-Bit Offset

3

JMP

1
2

3
ADC
ADD
AND
SUB

EOR CPX
LOA LOX
ORA CMP
BIT SBC

STA
STX

I

4

1
2

3
4
1
2

5

3
4

5
1
2
TST

LSL LSR
ASR NEG
CLR ROL
COM ROR
DEC INC

5

3
4
5
1
2

6

3
4
5
6
1
2

JSR

6

3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Index Register + Offset
Index Register + Offset

1

1

1

1

0
0
0
1

0

0
0
0
0

1
1
1
1
1

0
0
0
0

1
1
1
1

1

0
1
1
1
1

1

1

0
0
0
0
0
1

Op Code Address
Op Code Address + 1
Op Code Address + 1
Index Register + Offset
Stack Pointer
Stack Pointer - 1

0
0

0
0
0
0
0

Op
Op
Op
Op

1
1
1
1

0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset

1
1
1
1
1

0
0
0
0

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Op Code Address + 2
Index Register + Offset

1
1
1

Op Code
Offset
Offset
Op Code
Offset
Offset
Operand Data
Op Code
Offset
Offset
Offset
Operand Data
Op Code
Offset
Offset
Operand Data
Op Code Next Instruction
Op Code
Offset
Offset
Current Operand Data
Current Operand Data
New Operand Data
Op Code
Offset
Offset
1st Subroutine Op Code
Return Address LO Byte
Return Address HI Byte

Indexed, 16-Bit Offset

JMP

ADC CMP SUB
ADD EOR SBC
AND ORA
CPX LOA
BIT LOX

4

1
2

3
4
1
2

5

3
4

5
1
2

STA
STX

6

3
4

5
6
1
2
JSR

7

3
4
5
6
7

Code
Code
Code
Code

Address
Address + 1
Address + 2
Address + 2

Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address + 2
Index Register + Offset
Stack Pointer
Stack Pointer - 1

3·694

1

1

0
1
1
1
1
1

0
0

1

1

1

0
0
0
0
0
1

0
0
0
0
0
0

Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
Offset (LO Byte)
Operand Data
Op Code
Offset (HI Byte)
Offset (LO Byte)
Offset (LO Byte)
1st Subroutine Op Code
Return Address (LO Byte)
Return Address (HO Byte)

MC146805E2

TABLE 11 - SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED)

Instructions

Cycles

Address Bus

Cycle #

RESET
Pin

R/W
Pin

0

1
1

LI
Pin

Data Bus

Other Functions
$1 FFE
$1 FFE

--

Hardware RESET

5

1

$1 FFE

2
3
4

$lFFE
$1 FFE

5

Reset Vector
$1 FFE

$1 FFF

1

Power on Reset

Instruction

1922

Cycles

0
1

·• ···
·

1919
1920
1921

$1 FFE

1922

Reset Vector
Address Bus
Lase Cycle of Previous
Instruction

1
2
3

-

IRQ Interrupt
(Timer Vector $1 FF8, $1 FF9)

10

4

5
6
7
8
9
10

Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Vector High

1

1
1
1

1
1
1

0
0
0

1

0

Vector Low
Op Code

1

1
1

0

Irrelevant Data

1

1

0

Irrelevant Data

1

1

Vector High

1
1

1
1

0
0

Vector Low

0

Op Code

IRQ
Pin

R/W
Pin

LI
Pin

0

X

0

X

0
X
X

1
1

0
0
0

Irrelevant Data
Return Address (LO Byte)

0
0
0

Return Address (HI Byte)
Contents Index Reg
Contents Accumulator

0
0

Contents CC Register
Vector High

0
0

Vector Low
Int Routine First

·• ·· ·· ·••
· · ·

$1 FFE
$1 FFF

Cycles #

0
0
0

Next Op Code Address
Next Op Code Address
SP
SP-1
SP-2
SP-3

X
X

SP-4
$lFFA

X

X
X

$1 FFB

X

IRQ Vector

X

0

0
0
0
0
1
1
1

Data Bus

Irrelevant Data

APPENDIX
MCl46805E2 INTERRUPT CLARIFICATION
Under certain circumstances, the MC146805E2 (BP4XXXX
and AW9XXXX) 8-bit Microprocessor Unit IRQ interrupt
does not conform to the operation described in this
Advanced Information Sheet.

these require no action and the third has a recommended solution.
a. Those not using the'WAIT mode need not take any
action.

1. The level sensitive IRQ mode, which is by far the most
frequently used, is FULLY OPERATIONAL: thus, most
MC146805E2 applications are unaffected. However,
the edge-triggeredlRO interrupt mode MIGHT NOT BE
SERVICED under certain programming circumstances;
therefore, it is recommended that the edge-triggered
mode not be used.

b. If the WAIT mode is used without external interrupt
(IRQ pin held high), no precautions are required.
c. When IRQ can be active (low) during the WAIT
mode, the vector in locations $lFF6 and $lFF7 (the
WAIT mode timer interrupt vector) should be
duplicated in $1 FF2 and $1 FF3. In this way the circumstances that caused selection of the second
vector do not disturb normal program execution.

2. An interrupt-vector address CAN BE improperly
generated in some circumstances. There is a possibility
that when an external interrupt (fRQ) and timer interrupt occur during the WAIT mode (following wait
instruction), address locations $lFF2 and $lFF3 are
selected instead of vector locations $1 FF6 and $1 FF7.
There are three specific examples listed below; two of

On future MC146805E2 parts, no special actions will be
necessary. If you have questions, contact your Motorola
distributor or Motorola sales office, or contact Motorola
Microprocessor Applications Engineering in Austin, Texas.

3·695

II

®

MC146805E3

MOTOROLA
Product Preview

CMOS
(HIGH PERFORMANCE SILICON GATE)

a-BIT MICROPROCESSOR UNIT

I

The MC146805E3 Microprocessor Unit (MPU) belongs to the M6805
Family of microcomputers. This 8-bit fully static and expandable
microprocessor contains a CPU, on-chip RAM, I/O, and TIMER. Operation is identical to the MC146805E2 except that this device includes a
64K memory addressing capability.
The MC146805E3 is a low-power, low-cost processor designed for
low-end to mid-range applications in the consumer, automotive, industrial and communications markets where very low power consumption constitutes an important factor.

HARWARE FEATURES
• Typical Full Speed Operating Power of 35 mW @ 5 V
• Typical WAIT Mode Power of 5 mW
• Typical STOP Mode Power of 25 ,...W
• 112 Bytes of On-Chip RAM
• 16 Bidirectional I/O Lines
• Internal 8-Bit Timer with Software Programming 7-Bit Prescaler
• External Timer Input
• Full External and Timer Interrupts
• Multiplexed Address/Data Bus
• Master Reset and Power-On Reset
• Capable of Addressing Up to 64K Bytes of External Memory
• Single 3- to 6-Volt Supply
• On-Chip Oscillator

a-BIT
MICROPROCESSOR

ri1\11\11111\~1

S SUFFIX

'
9M
~l'llill ~i\ 'CA:T~U::;~AGE
CERDIP PACKAGE
CASE 734

LSUFFIX

tf·~

r

CERAMIC PACKAGE

~W\1'\~
l"ill~

CASE 715

CASE711

r

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT

SOFTWARE FEATURES
• Similar to the MC6800
• Efficient Use of Program Space
• Versatile Interrupt Handling
• True Bit Manipulation
• Addressing Modes with Indexed Addressing for Tables
• Efficient Instruction Set
• Memory Mapped I/O
• Two Power Saving Standby Modes

GENERAL DESCRIPTION
The MC146805E3 MPU, an expanded version of the MC146805E2 MPU,
includes a 64K memory addressing capability. The following paragraph
explains the modifications made to the MC146805E2 and reference
should be made to the MC146805E2 Advance Information Data Sheet
(ADI-850-R2) for detailed information.
Port A bits 5, 6, and 7 have been replaced by high-byte address bits 13, 14, and 15. The new address pins will behave
identically to the current high address pins (A8-A 121. Port
A bits 5 through 7 will be seen as "read only" bits and will
be read as zeros facilitating "all zero" or "anyone" testing.
Port A data direction bits 5 through 7 will be seen as "read
only" bits and will be read as ones, indicating that they are
outputs.
This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice

3-696

RESET

VOO

IRQ

OSCl

LI

OSC2

OS

TIMER

R/W

PBO

AS

PBl

A15

PB2

A14

PB3

A13

PB4

PA4

PB5

PA3

PB6

PA2

PB7

PAl

BO

PAO

Bl

A12

B2

All

B3

Al0

B4

A9

B5

A8

B6

VSS

B7

®

MCl46818
Addendum

MOTOROLA

Advance Information

REAL-TIME CLOCK PLUS RAM (RYC)
Advance Information Data Sheet
ADI-856-Rl

The following information is an addition to POWER-DOWN CONSIDERATIONS
found on page 11 of the MC146818 Advance Information Data Sheet (ADI-856-Rl).

MC146818s with the date code of 3N46XXXX and GC6XXXX require a synchronization of the CE pin with address strobe. The following circuit will satisfy that condition, and also show a typical application of power-down circuitry.
If EE is grounded at all times (no power down required) the following circuit need
not be used.

3-697

I

MC146818

MCl46818

+5V
ADO
MBD701
(Schottky)

4

ADl
AD2

BBV*

AD4

3.9V

6

9
AD6
AD7
AS

10
11
14
17

I

OSC2

STATEK
CXIVor
Equivalent

AD2
AD3

8

AD5

l

ADO

32.768 kHz

ADl

AD3
lN4148
(Si)

470 k

AD4

OSCl

~10PF

AD5

BBV

AD6
AD7
AS

100 k

DS
PS

R/W

15
13

R/W

RESET

~50PF

EE

BBV

+5V

1M >Of---f

MC74HC373 (See Note 1)

1M
+12V(>BBV)~-J~rv--

®

39 k

__~~~~

®

20k

(See Note 2)
* BBV = Battery Backup Voltage
NOTES:
1. All unused inputs of the MC74HC373 must be grounded.
2. If point
equals 12 V point
should be equal to 4.06 V. If point
for 3.18 V.

®

®

3-698

®

equals 10 V point

®

should be equal to 3.38 V with

©

set

®

MC146818

MOTOROLA

Advance Information

CMOS
I HIGH-PERFORMANCE
SILICON-GATE COMPLEMENTARY MOS)

REAL-TIME CLOCK PLUS RAM (RTC)
The MC146818 Real-Time Clock plus RAM is a peripheral device
which includes the unique MOTEL concept for use with various
microprocessors, microcomputers, and larger computers. This part
combines three unique features: a complete time-of-day clock with
alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static
RAM. The MC146818 uses high-speed CMOS technology to interface
with 1 MHz processor buses, while consuming very little power.
The Real-Time Clock plus RAM has two distinct uses. First. it is
designed as a battery powered CMOS part lin an otherwise NMOS/TTL
system) including all the common battery backed-up functions such as
RAM, time, and calendar. Secondly, the MC146818 may be used with a
CMOS microprocessor to relieve the software of the timekeeping
workload and to extend the available RAM of an MPU such as the
MC146805E2.
•

Low-Power, High-Speed, High-Density CMOS

•
•

Internal Time Base and Oscillator
Counts Seconds, Minutes, and Hours of the Day

REAL-TIME CLOCK
PLUS RAM

L SUFFIX
CERAMIC PACKAGE
CASE 716

P SUFFIX
PLASTIC PACKAGE
CASE 709

S SUFFIX

•

Counts Days of the Week, Date, Month, and Year

•

3 V to 6 V Operation

•

Time Base Input Options: 4.194304 MHz, 1.048576 ivlHz, or
32.768 kHz

•

Time Base Oscillator for Parallel Resonant Crystals

•
•

40 to 200 J.LW Typical Operating Power at Low Frequency Time Base
4.0 to 20 mW Typical Operating Power at High Frequency Time
Base

•
•

Binary or BCD Representation of Time, Calendar, and Alarm
12- or 24-Hour Clock with AM and PM in 12-Hour Mode

CERDIP PACKAGE
CASE 623

Z SUFFIX
CHIP CARRIER
CASE 761

..,. •
~

<:>

•

Daylight Savings Time Option

•
•

Automatic End of Month Recognition
Automatic Leap Year Compensation

•
•
•

Microprocessor Bus Compatible
MOTEL Circuit for Bus Universality
Multiplexed Bus for Pin Efficiency

•

Interfaced with Software as 64 RAM Locations

•

14 Bytes of Clock and Control Registers

ADO

•
•

50 Bytes of General Purpose RAM
Status Bit Indicates Data Integrity

AD1

CKFS
IRO

•
•

Bus Compatible Interrupt Signals IIRQ)
Three Interrupts are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day

AD2
AD3

RESET

AD4

DS

PIN ASSIGNMENT
NC
OSC1
OSC2

Periodic Rates from 30.5 J.LS to 500 ms
End-of-Clock Update Cycle

•

Programmable Square-Wave Output Signal
Clock Output May Be Used as Microprocessor Clock Input
At Time Base Frequency + 1 or +4
24-Pin Dual-In-Line Package

•

Chip Carrier Also Available

•
•

VDD
SOW
PS
CKOUT

AD5

NC

AD6

R/W

AD?

AS

VSS

IT

Pin numbers in parentheses represent equivalent Z
suffix chip carrier pins. Pins that have not been
designated for the chip carrier are not connected.

This document contains information on a new product. Specifications and information herein
are subiect to change without notice.

3-699

.MC146818

FIGURE 1 -

BLOCK DIAGRAM
CKOUT
CKFS

OSCl
OSC2

I

sow
VDD - - - .

Vss-----'

Registers A, B, C, D
(4 Bytes)

Bus
Interface
Clock I
Calendar
Update

RESET
PS

Clock, Alarm,
Calendar RAM
(10 Bytes)

BCDI
Binary
Increment
User RAM
(50 Bytes)

MAXIMUM RATINGS (Voltages referenced to VSS)
Ratings
Supply Voltage
All Input Voltages Except OSCl
Current Drain per Pin Excluding
VDO and VSS
Operating Temperature Range
MC146818
MC146818C (VDD = 3.0 to 5.5 V
operation)
Storage Temperature Range

Symbol

Value

Unit

VDD

-0.3 to +8.0

V

Vin

VSS-0.5 to VDD+0.5

V

I

10

mA

TA

TL to TH
o to 70
-40 to 85

DC

Tstg

-55 to + 150

DC

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Cerdip
Ceramic

Symbol

Value

Unit

()JA

120
65
50

DC/W

3-700

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS~(Vin or Vout)
~ VDD. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VDD)·

MC146818

DC ELECTRICAL CHARACTERISTICS (VOO= 3 Vdc, VSS = 0 Vdc T A =

h

to TH unless otherwise noted)
Symbol

Min

Max

Unit

Frequency of Operation

lose

32.768

32.768

kHz

Output Voltage

VOL

-

0.1

ILoad< 10 p.A

VOH

VOO-Ol

-

Characteristics

100 - Bus Idle
CKOUT = fosc, CL = 15 pF; SQW Disabled, CE= VOO- 0.2; CL (OSC2) = 10 pF
fos c =32.768 kHz
100 - Quiescent
fosc= DC; OSCl = DC;
All Other Inputs=VOO-0.2 V;
No Clock
Output High Voltage
(LLoad = - 0.25 mA, All Outputs)
Output Low Voltage
(ILoad=0.25 mA, All Outputs)
Input High Voltage

AOO-A07, OS, AS, R/W, CE,
RESET, CKFS, PS, OSCl

Input Low Voltage (All Inputs)
Input Curren!

All Inputs

Three-State Leakage

IRQ, AOO-A07

V

1003

-

50

I'A

1004

-

50

p.A

VOH

2.7

-

V

VOL

-

0.3

V

VIH

2.1
2.5

V

VIL

VSS

VOO
VOO
0.5

lin

-

±1

I'A

ITSL

-

±10

I'A

V

DC ELECTRICAL CHARACTERISTICS (VOO = 5 Vdc +
- 10%, VSS = 0 Vdc, T A = TL to T H unless otherwise noted)
Symbol

Min

Max

Unit

Frequency of Operation

fosc

32.768

4194.304

kHz

Output Voltage

VOL

-

0.1

ILoad< 10 p.A

VOH

VOO-Ol

-

1001
1002
1003

-

mA

-

3
800
50

1004

-

50

I'A

Output High Voltage
(ILoad= -1.6 mA, AOO-A07, CKOUT)
(ILoad= -1.0 mA, SQW)

VOH

4.1

-

V

Output Low Voltage
(ILoad= 1.6 mA, AOO-A07, CKOUT)
(lLoad= 1.0 mA, IRQ and SQW)

VOL

-

0.4

V

CKFS, AOO-A07, OS, AS, R/W, CE, PS
RESET
OSCl

VIH

VOO-2.0
VOO-0.8
VOO-l.0

AOO-A07, OS, AS, R/W, CE
CKFS, PS, RESET
OSCl

VIL

VSS
VSS
VSS

VOO
VOO
VOO
0.8
0.8
0.8

lin

-

±1

p.A

ITSL

-

±10

I'A

Characteristics

100 - Bus Idle (External Clock)
CKOUT = fosc, CL = 15 pF; SQW Disabled, CE = VOO - 0.2; CL (OSC2) = 10 pF
fos c =4.194304 MHz
fosc= 1.048516 MHz
fos c =32.768 kHz
100 - Quiescent
fosc= DC; OSCl = DC;
All Other Inputs=VOO-0.2 V;
No Clock

Input High Voltage

Input Low Voltage

Input Current

All Inputs

Three-State Leakage

IRQ, AOO-A07

3-701

-

V

I'A
I'A

V

V

I

MC146818

BUS TIMING

VOO=3.0 V
50 pF Load

Ident.
Number

I

VOO=5.0 V
±10%
2 TTL and
130 pF Load

Symbol

Min

Min

Max

Unit

tcyc

5000

-

953

dc

ns

Pulse Width, DS/E Low or RD/WR High

PWEL

1000

-

300

-

ns

3

Pulse Width, DS/E High or RD/WR Low

PWEH

1500

-

325

-

ns

4

Input Rise and Fall Time

-

30

ns

8

R/W Hold Time

tRWH

13

R/W Setup Time Before DS/E

14

Chip Enable Setup Time Before ASI ALE Fall

15

Chip Enable Hold Time

18

Characteristics

1

Cycle Time

2

t r, tf

-

Max

100

10

-

10

-

ns

tRWS

200

-

80

-

ns

tcs

200

*

55

*

ns

tCH

10

-

0

-

ns

Read Data Hold Time

tDHR

10

1000

10

100

ns

21

Write Data Hold Time

tDHW

100

-

0

-

ns

24

Muxed Address Valid Time to ASI ALE Fall

tASL

200

-

50

-

ns

25

Muxed Address Hold Time

tAHL

100

-

20

-

ns

26

Delay TimeDS/E to AS/ALE Rise

tASD

500

-

50

-

ns

27

Pulse Width, ASI ALE High

PWAS H

600

-

135

-

ns

28

Delay Time, ASI ALE to DSI E Rise

tASED

500

-

60

-

ns

30

Peripheral Output Data Delay Time from DS/E or RD

tDDR

1300

-

20

240

ns

31

Peripheral Data Setup Time

tDSW

1500

-

200

-

ns

NOTE: DeSignations E, ALE, RD, and WR refer to signals from alternative microprocessor signals.
* Refer to IMPORTANT NOTICES appearing on page 20 of this data sheet.

FIGURE 2 -

MCl46818 BUS TIMING

AS

DS

R/W

ADOAD7
WRITE

ADOAD7
READ
NOTE VHIGH=VDD-20 V, VLOW=08 V, for VDD=50 V ± 10%

3-702

MC146818

FIGURE 3 -

BUS READ TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin)

RD (Read Output Enable)
(OS Pin)

WR (Write Enable)
(R/W Pin)

CE

11

(Chip Enable)

ADO-AD7
(Address/ Data Bus)

----------------------~

FIGURE 4 -

BUS WRITE TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin)

R1S

(Read Output Enable)
(OS Pin)

WR (Write Enable)
(R/W Pin)

CE(ChiPE_n_a_bl_e_)____

~~~~~~~~~~~--_r~----------------------------~_r~~~~~~

ADO-AD7
(Address/ Data;:..:;;B.:;:.us~)______________________< I

NOTE VHIGH=VOD-20 V, VLOW=08 V, for VDD=50 V

Write Data
Valid

± 10%

3-703

MC146818

TABLE 1 -

SWITCHING CHARACTERISTICS (V OO =5.0 Vdc ± 10%, VSS=O Vdc, T A =

TL

to THI

Symbol

Min

Max

Unit

-

100

ms

5

-

p's

tRLH

5

-

p's

Power Sense Pulse Width

tpWL

5

-

p's

Power Sense Delay Time

tPLH

5

-

p's

IRQ Release from OS

tlROS

-

2

p's

tlRR

-

2

p's

tVRTD

-

2

p's

Description
Oscillator Startup

tRC

Reset Pulse Width

tRWL

Reset Oelay Time

IRQ Release from RESET
VRT Bit Delay

FIGURE 5 -

IRQ RELEASE DELAY

~r- VLOW

OS

RESET

\r-

..

A.

)

IRO

VHIGH

}'tlRR

tlROS
NOTE: VHIGH=VOD-20 V, VLOW=0.8 V, for VOO=50 V ± 10%

FIGURE 6 - TIL EQUIVALENT TEST LOAD

VOO

(IRa Only)

2k
Test
Point

Test Point
Vi
130 pF
MMD7000
or Equivalent

All Outputs Except OSC2 (See Figure 101

3-704

.0-----.

402 k

MC146818

FIGURE 7 -

OV _ _
VDD Pin

POWER-UP

---

---J/T-----~s~s

RESET Pin

CKOUT Pin

FIGURE 8 -

CONDITIONS THAT CLEAR VRT BIT

VDD Pin

OV

PS Pin

VRT Bit

G)

The VRT bit is set to a "1" by reading Register d. The VRT bit can only be cleared by pufling the PS pin low (see REGISTER

3-705

t> ($00)).

MC146818

MOTEL

bus structure is now available. The MOTEL concept IS
shown logically in Figure 9.
MOTEL selects one of two interpretations of two pins. In
the Motorola case, OS and R/W are gated together to produce the internal read enable. The internal write enable is a
similar gating of the inverse of Riw. With competitor buses,
the inversion of RO and WR create functionally identical internal read and write enable signals.
The MC146818 automatically selects the processor type by
using ASI ALE to latch the state of the OS/RD pin. Since OS
is always low and R15 is always high during AS and ALE, the
latch automatically indicates which processor type is connected.

The MOTEL circuit is a new concept that permits the
MC146818 to be directly interfaced with many types of
microprocessors. No external logic is needed to adapt to the
differences in bus control signals from common multiplexed
bus microprocessors.
Practically all microprocessors interface with one of two
synchronous bus structures. One bus was originated by the
Motorola MC6800 and the other by the Intel 8080 and its
companion part, the 8228.
The MOTEL circuit (for MOTorola and IntEl. bus compatibility) is built into peripheral and memory ICs to permit
direct connection to either type of bus. An industry standard
FIGURE 9 -

I

Motorola Type
MPU Signals

Competitor Type
MPU Signals
. ALE

AS

OS, E, or <1>2

R/W

WR

FUNCTIONAL DIAGRAM OF MOTEL CIRCUIT

MC146818
Pin Signals
AS

o

Competitive Bus

Internal
Signals

Q

t---+----I C

Motorola
Bus

OS

Read Enable

R/W

Write Enable

SIGNAL DESCRIPTIONS

AT cut crystal at 4.194304 MHz or 1.048576 MHz frequencies. The crystal connections are shown in Figure 11 and the
crystal characteristics in Figure 12.

The block diagram in Figure 1, shows the pin connection
with the major internal functions of the M C146818 Real-Time
Clock plus RAM. The following paragraphs describe the
function of each pin.

CKOUT -

CLOCK OUT, OUTPUT

Voo,VSS
OC power is provided to the part on these two pins, VOO
being the more positive voltage. The minimum and maximum voltages are listed in the Electrical Characteristics
tables.

The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. A major use for CKOUT is as the input
clock to the microprocessor; thereby saving the cost of a second crystal. The frequency of CKOUT depends upon the
time-base frequency and the state of the CKFS pin as shown
in Table 2.

OSC1, OSC2 -

CKFS -

TIME BASE, INPUTS

The time base for the time functions may be an external
signal or the crystal oscillator. External square waves at
4.194304 MHz, 1.048576 MHz, or 32.768 kHz may be connected to OSC1 as shown in Figure 10. The internal timebase frequency to be used is chosen in Register A.
The on-chip oscillator is designed for a parallel resonant

CLOCK OUT FREOUENCY SELECT, INPUT

When the CKFS pin is tied to VOO it causes CKOUT to be
the same frequency as the time base at the OSC1 pin. When
CKFS is tied to VSS, CKOUT is the OSC1 time-base frequency divided by four. Table 2 summarizes the effect of
CKFS.
.

3-706

MC146818

FIGURE 10 -

EXTERNAL TIME-BASE CONNECTION
VOO

J

Optional

(VOO-1.0 V)

4.194304 MHz
or
1048576 MHz
or
32.768 kHz

I
I

OSC1

(Open)

OSC2

MC146818

FIGURE 11 -

I

CRYSTAL OSCILLATOR CONNECTION

~--------------e-------~--~ OSC1
4.194304 MHz,
1.048576 MHz,

Rf

or
32.768 kHz

....'VV'v-....---i OSC2
C
outT

*32.768 kHz Only -

MC146818

Consult Crystal Manufacturer's Specification

FIGURE 12 -

CRYSTAL PARAMETERS

Crystal Equivalent Circuit

--

------tID~1
4.194304 MHz

1.048576 MHz

RS (Maximum)

75 {}

700 {}

50 k

CO (Maximum)

7 pF

5 pF

1.7 pF

C1

0.012 pF

0.008 pF

0.003 pF

Q

50 k

35 k

30 k

15-30 pF

15-40 pF

10-22 pF

-

-

300-470 k

10 M

10M

22 M

fosc

Cin/Cout
R
Rf

3-707

32.768 kHz

MC146818

TABLE 2 Time Base
(OSC1)
Frequency

Clock Frequency
Select Pin
(CKFS)

Clock Frequency
Output Pin
(CKOUT)

High

4.194304 MHz

4.194304 MHz

Low

1.048576 MHz

1.048576 MHz

High

1.048576 MHz

1.048576 MHz

Low

262.144 kHz

32.768 kHz

High

32.768 kHz

32.768 kHz

Low

8.192 kHz

4.194304 MHz

SQW -

I

the DS pin must remain high during the time AS/ ALE is
high.

CLOCK OUTPUT FREQUENCIES

R/W - READ/WRITE, INPUT
The MOTEL circuit treats the R/W pin in one of two ways.
When a Motorola type processor is connected, R/W is a
level which indicates whether the current cycle is a read or
write. A read cycle is indicated with a high level on R/W
while DS is high, whereas a write cycle is a low on R/W during DS
The second interpretation of R/W is as a negative write
pulse, WR, MEMW, and IIOW from competitor type processors. The MOTEL circuit in !l:!!s mode gives R/W pin the
same meaning as the write (W) pulse on many generic
RAMs.

SQUARE WAVE, OUTPUT

The SQW pin can output a signal from one of the 15 taps
provided by the 22 internal-divider stages. The frequency of
the SQW may be altered by programming Register A, as
shown in Table 5. The SQW signal may be turned on and off
using the SQWE bit in Register B.

ADO-AD7 MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time of the
MC146818 since the bus reversal from address to data is occurring during the internal RAM access time.
The address must be valid just prior to the fall of AS/ ALE
at which time the MC146818 latches the address from ADO
to AD5. Valid write data must be presented and held stable
during the latter portion of the DS or WR pulses. In a read
cycle, the MC146818 outputs eight bits of data during the
latter portion of the DS or RD pulses, then ceases driving the
bus (returns the output drivers to the high-impedance state)
when DS falls in the Motorola case of MOTEL or RD rises in
the other case.
AS - MULTIPLEXED ADDRESS STROBE, INPUT
A positive going multiplexed address strobe pulse serves
to demultiplex the bus. The falling edge of AS or ALE causes
the address to be latched within the MC146818. The
automatic MOTEL circuit in the MC146818 also latches the
state of the DS pin with the falling edge of AS or ALE.

DS - DATA STROBE OR READ, INPUT
The DS pin has two interpretations via the MOTEL circuit.
When emanating from a Motorola type processor, DS is a
positive pulse during the latter portion of the bus cycle, and
is variously called DS (data strobe), E (enable), and 4>2 (4)2
clock). During read cycles, DS signifies the time that the
RTC is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the Real-Time Clock plus RAM to
latch the written data.
The second MOTEL interpretation of DS is that of RD,
MEMR, or I/OR emanating from the competitor type processor. In this case, DS identifies the time period when the
real-time clock plus RAM drives the bus with read data. This
interpretation of DS is also the same as an output-enable
Signal on a typical memory.
The MOTEL circuit, within the MC146818, latches the
state of the DS pin on the falling edge of AS/ ALE. When the
Motorola mode of MOTEL is desired DS must below during
AS/ ALE, which is the case with the Motorola multiplexed
bus processors. To ensure the competitor mode of MOTEL,

CE -

CHIP ENABLE, INPUT
The chip-enable (EE) signal must be asserted (low) for a
bus cycle in which the MC146818 is to be accessed. EE is not
latched and must be stable during DS and AS (Motorola
case of MOTEU and during RD and WR (in the other
MOTEL case). Bus cycles which take place without asserting
CE cause no actions to take place within the MC146818.
When CE is high, the multiplexed bus output is in a highimpedance state.
When IT is high, all address, data, DS, and R/W inputs
from the processor are disconnected within the MC146818.
This permits the MC146818 to be isolated from a powereddown processor. When CE is held high, an unpowered
device cannot receive power through the input pins from the
real-time clock power source. Battery power consumption
can thus be reduced by using a pullup resistor or active
clamp on CE when the main power is off. When CE is not used, it should be grounded.
IRQ - INTERRUPT REQUEST, OUTPUT
The IRQ pin is an active low output of the MC146818 that
may be used as an interrupt input to a processor. The IRQ
output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit
is set. To clear the IRQ pin, the processor program normally
reads Register C. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is
in the high-impedance state. Multiple interrupting devices
may thus be connected to an IRQ bus with one pull up at the
processor.
RESET -

RESET, INPUT

The RESET pin does not a.ffect the clock, calendar, or
RAM functions. On powerup, the RESET pin must be held
low for the specified time, tRLH, in order to allow the power
supply to stabilize. Figure 13 shows a typical representation
of the RESET pin circuit.
When RESET is low the following occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared to zero,
b) Alarm Interrupt Enable (AlE) bit is cleared to zero,
el Update ended Interrupt Enable (UIE) bit is cleared to
zero,
d) Update ended Interrupt Flag (UF) bit is cleared to zero,
e) Interrupt Request status Flag (lRQF) bit is cleared to
zero,
f) Periodic Interrupt Flag (PF) bit is cleared to zero,
g) The part is not accessible.

3·708

MC146818

g) Alarm Interrupt Flag (AF) bit is cleared to zero,
h) IRO pin is in high-impedance state, and
Square Wave output Enable (SOWE) bit is cleared to
zero.

FIGURE 13 - TYPICAL POWERUP DELAY
CIRCUIT FOR RESET

01

PS - POWER SENSE, INPUT
The power-sense pin is used in the control of the valid
RAM and time (VRT) bit in Register D. When the PS pin is
low the VRT bit is cleared to zero.
When using the VRT feature during powerup, the PS pin
must be externally held low for the specified tpLH time. As
power is applied, the VRT bit remains low indicating that the
contents of the RAM, time registers, and calendar are not
guaranteed. PS must go high after powerup to allow the
VRT bit to be set by a read of register D.

02

-+._

System _ _.....,...._-1..._ _..._ _
VOO

Battery
Backup

Voo
10 k

03

MC146818

POWER-DOWN CONSIDERATIONS

I

0.005 I'F

In most systems, the MC146818 must continue to keep
time when system power is removed. In such systems, a
conversion from system power to an alternate power supply,
usually a battery, must be made. During the transition from
system to battery power, the designer of a battery backed-up
RTC system must protect data integrity, minimize power
consumption, and ensure hardware reliability.
The chip enable (eE) pin controls all bus inputs (R/W, DS,
AS, ADO-AD7). eE, when negated, disallows any unintended modification of the RTC data by the bus. eE also reduces
power consumption by reducing the number of transitions
seen internally.
Power consumption may be further reduced by removing
resistive and capacitive loads from the clock out (CKOUT)
pin and the squarewave (SOW) pin.
During and after the power source conversion, the VIN
maximum specification must never be exceeded. Failure to
meet the VIN maximum specification can cause a virtual
SCR to appear which may result in excessive current drain
and destruction of the part.

VSS

01 = MB0701 (Schottky) or Equivalent
02 = 03 = 1N4148 or Equivalent
Note: If the RTC is isolated from the MPU or MCU power by a
diode drop, care must be taken to meet Vin requirements.

FIGURE 14 -

TYPICAL POWERUP DELAY CIRCUIT
FOR POWER SENSE

01

02

...._____ . . . _........._ Battery

System _ ...*"""_~
VOO

~

Backup

PS
MC146818

VSS

I

0.0051'F

ADDRESS MAP
Figure 15 shows the address map of the MC146818. The
memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
data, and four control and status bytes. All 64 bytes are
directly readable and writable by the processor program except for the following: 1) Registers C and D are read only, 2)
bit 7 of Register A is read only, and 3) the high-order bit of
the seconds byte is read only. The contents of four control
and status registers (A, B, C, and D) are described in
REGISTERS.

TIME, CALENDAR, AND ALARM LOCATIONS

01 = MB0701 (Schottky) or Equivalent
02= 1N4148 or Equivalent

The processor program obtains time and calendar information by reading the appropriate locations. The program
may initialize the time, calendar, and alarm by writing to
these RAM locations. The contents of the 10 time, calendar,
and alarm bytes may be either binary or binary-coded decimal (BCD).

3-709

I

MC146818

0-to-23. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected
the high-order bit of the hours byte represents PM when it is
a "1".
The time, calendar, and alarm bytes are not always accessable by the processor program. Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248 /Ls at the 4.194304 MHz and
1.048567 MHz time bases and 1948 P.s for the 32.768 kHz
time base. The Update Cycle section shows how to accommodate the update cycle in the processor program.

Before initializing the internal registers, the SET bit in
Register B should be set to a "1" to prevent time/calendar
updates from occurring. The program initializes the 10 locations in the selected format (binary or BCD), then indicates
the format in the data mode (OM) bit of Register B. All 10
time, calendar, and alarm bytes must use the same data
mode, either binary or BCD. The SET bit may now be cleared
to allow updates. Once initialized the real-time clock makes
all updates in the selected data mode. The data mode cannot
be changed without reinitializing the 10 data bytes.
Table 3 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24112 bit in Register B
establishes whether the hour locations represent 1-to-12 or
FIGURE 15 -

ADDRESS MAP

00

I

14
Bytes
14

Seconds Alarm

2

Minutes

OE

3

Minutes Alarm

3F

TABLE 3 Address
Location

Seconds

1
OD

50
Bytes
User
RAM

63

0

Function

00 "
01
02
03

4

Hours

04

5

Hours Alarm

05

6

Day of Week

06

7

Date of Month

07

8

Month

08

9

Year

09

10

Register A

OA

11

Register B

OB

12

Register C

OC

13

Register D

OD

Binary
or BCD
Contents

TIME, CALENDAR, AND ALARM DATA MODES

Decimal
Range

Range
Binary Data Mode
BCD Data Mode

Example*
Binary
BCD
Data Mode Data Mode

0

Seconds

0-59

$00-$3B

$00-$59

15

21

1

Seconds Alarm

0-59

$00-$3B

$00-$59

15

21

2

Minutes

0-59

$00-$3B

$00-$59

3A

58

3

Minutes Alarm

0-59

$00-$3B

$00-$59

3A

58

Hours
(12 Hour Mode)

1-12

$Ol-$OC (AM) and
$81-$8C (PM)

$01-$12 (AM) and
$81-$92 (PM)

05

05

Hours
(24 Hour Mode)

0-23

$00-$17

$00-$23

05

05

Hours Alarm
(12 Hour Mode)

1-12

$Ol-$OC (AM) and
$81-$8C (PM)

$01-$12 (AM) and
$81-$92 (PM)

05

05

Hours Alarm
(24 Hour Mode)

0-23

$00-$17

$00-23

05

05

05

05

4

5

6

Day of the Week
Sunday= 1

1-7

$01-$ 07

$01-$07

7

Date of the Month

1-31

$01-$1 F

$01-$31

OF

15

8

Month

1-12

$Ol-$OC

$01-$12

02

02

9

Year

0-99

$00-$63

$00-$99

4F

79

'Example: 5:58:21 Thursday 15 February 1979 (time is AM)

3-710

MC146818

When an interrupt event occurs a flag bit is set to a "1" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The "interrupt" flag bit becomes a
status bit, which the software interrogates, when it wishes.
When the software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the
bit was last read.

The three alarm bytes may be used in two ways. First,
when the program inserts an alarm time in the appropriate
hours, minutes, and seconds alarm locations, the alarm
interrrupt is initiated at the specified time each day if the
alarm enable bit is high. The second usage is to insert a
"don't care" state in one or more of three alarm bytes. The
"don't care" code is any hexadecimal byte from CO to FF.
That is, the two most-significant bits of each byte, when set
to "1", create a "don't care" situation. An alarm interrupt
each hour is created with a "don't care" code in the hours
alarm location. Similarly, an alarm is generated every minute
with "don't care" codes in the hours and minutes alarm
bytes. The" don't care" codes in all three alarm bytes create
an interrupt every second.

However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
all utilized flag bits every time Register C is read to insure
that no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable bit is also set, the I RQ pin is
asserted low. IRQ is asserted as long as at least one of the
three interrupt sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the IRQ pin is
being driven low.
The processor program can determine that the RTC
initiated the interrupt by reading Register C. A "1" in bit 7
(IRQF bit) indicates that one or more interrupts have been
initiated by the part. The act of reading Register C clears all
the then-active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual
flag bits in the same byte which have the corresponding
interrupt-mask bits set and service each interrupt which is
set. Again, more than one interrupt-flag bit may be set.

STATIC CMOS RAM
The 50 general purpose RAM bytes are not dedicated
within the MC146818. They can be used by the processor
program, and are fully available during the update cycle.
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed. The 50 user
RAM bytes serve the need for low-power CMOS batterybacked storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional
MC146818s may be included in the system. The time/calendar functions may be disabled by holding the DVO-DV2
dividers, in Register A, in the reset state by setting the SET
bit in Register B or by removing the oscillator. Holding the
dividers in reset prevents interrupts or SQW output from
operating while setting the SET bit allows these functions to
occur. With the dividers clear, the available user RAM is extended to 59 bytes. The high-order bit of the seconds byte,
bit 7 of Register A, and all bits of Registers C and 0 cannot
effectively be used as general purpose RAM.

INTERRUPTS
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for
rates from half-a-second to 30.517 JLs. The update-ended
interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt
conditions are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register B enable the three
interrupts. Writing a "1" to a interrupt-enable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the interrupt-enable bit prohibits the IRQ pin from being
asserted due to the interrupt cause
If an interrupt flag is already set when the interrupt
becomes enabled, the IRQ pin is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before first
enabling new interrupts.

DIVIDER STAGES
The MCl46818 has 22 binary-divider stages following the
time base as shown in Figure 1. The output of the dividers is
a 1 Hz signal to the update-cycle logic. The dividers are controller by three divider bus (oV2, DV1, and DVO) in Register
A.

DIVIDER CONTROL
The divider-control bits have three uses, as shown in Table
4. Three usable operating time bases may be selected
(4.194304 MHz, 1.048576 MHz, or 32.768 kHz). The divider
chain may be held reset, which allows precision setting of
the time. When the divider is changed from reset to an
operating time base, the first update cycle is one-half second
later. The divider-control bits are also used to facilitate
testing the MC146818.

3-711

I

MC146818

TABLE 4 - DIVIDER CONFIGURATIONS
Divider Bits
Register A

Operation
Mode

Divider
Reset

Bypass First
N-Divider Bits

0

Yes

-

N=O

0

1

Yes

-

N=2

0

1

0

Yes

-

N=7

Any

1

1

0

No

Yes

-

Any

1

1

1

No

Yes

-

Time-Base
Frequency

DV2

DV1

DVO

4.194304 MHz

0

0

1.048576 MHz

0

32.768 kHz

Note: Other combinations of divider bits are used for test purposes only.

I

PERIODIC INTERRUPT SELECTION
The periodic interrupt allows the IRO pin to be triggered
from once every 500 ms to once every 30.517 p,s. The
periodic interrupt is separate from the alarm interrupt which
may be output from once-per-second to once-per-day.
Table 5 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function may be separately enabled so that a program could
switch between the two features or use both. The SOW pin
is enabled by the SOWE bit in Register B. Similarly the
periodic interrupt is enabled by the PIE bit in Register B.
Periodic interrupt is usable by practically all real-time
systems. It can be used to scan for all forms of inputs from
contact closures to serial receive bits or bytes. It can be used
in multiplexing displays or with software counters to measure inputs, create output intervals, or await the next needed
software function.

SQUARE-WAVE OUTPUT SELECTION
Fifteen of the 22 divider taps are made available to a
1-of-15 selector as shown in Figure 1. The first purpose of
selecting a divider tap is to generate a square-wave output
signal at the SOW pin. The RSO-RS3 bits in Register A
establish the square-wave frequency as listed in Table 5. The
SOW frequency selection shares the 1-of-15 selector with
periodic interrupts.
Once the frequency is selected, the output of the SOW pin
may be turned on and off under program control with the
square-wave enable (SOWE) bit in Register B. Altering the
divider, square-wave output selection bits, or the SOWE
output-enable bit may generate an asymmetrical waveform
at the time of execution. The square-wave output pin has a
number of potential uses. For example, it can serve as a frequency standard for external use, a frequency synthesizer, or
could be used to generate one or more audio tones under
program control.

TABLE 5 - PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY

RS3
0
0
0
0

Select Bits
Register A
RS2 RS1
0
0

0

0
0
1

0

1

0
0

1
1

1
1

0
0

1
1
1
1

0
0
1
1

1
1

1
1

0
0
1
1
0

32.768 kHz
4.194304 or 1.048576 MHz
Time Base
Time Base
Periodic
Periodic
Interrupt Rate SQW Output Interrupt Rate SQW Output
RSO
tPI
tpi
Frequency
Frequency
None
None
None
None
0
3.90625 ms
1
30.517 P.s
32.768 kHz
256 Hz
0
1

61.035 P.s
122.070 ILS

16.384 kHz
8.192 kHz

0
1

244.141 P.s

4.096 kHz

488.281

7.8125 ms

128 Hz

122.070 uS
244.141 P.s

8.192 kHz
4.096 kHz

0
1
1

2.048 kHz

976.562 p's
1.953125 ms

2.048 kHz
1.024 kHz
512 Hz

488.281 P.s

0
1

976.562 P.s
1.953125 ms

1.024 kHz
512 Hz

0

0

3.90625 ms

256 Hz

3.90625 ms

0
1
1

1

7.8125 ms

7.8125 ms

256 Hz
128 Hz

0
1

15.625 ms
31.25 ms

128 Hz
64 Hz

15.625 ms
31.25 ms

64 Hz
32 Hz

0
1

62.5 ms
125 ms

62.5 ms
125 ms

0
1

250 ms
500 ms

16 Hz
8 Hz
4 Hz
2 Hz

0
0
1
1

p's

32 Hz
16 Hz
8 Hz
4 Hz
2 Hz

3-712

250 ms
500 ms

MC146818

UPDATE CYCLE

time needed to read valid time/ calendar data to exceed
244 p.s.
The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A is set
high between the setting of the PF bit in Register C (see
Figure 16). Periodic interrupts that occur at a rate of greater
than tBUC + tuc allow valid time and date information to be
read at each occurrence of the periodic interrupt. The reads
should be completed within (T PI -+- 2) + tBUC to ensure that
data is not read during the update cycle.
To properly setup the internal counters for daylight savings time operation, the user must set the time at least two
seconds before the rollover will occur. Likewise, the time
must be set at least two seconds before the end of the 29th
or 30th day of the month.

The MC146818 executes an update cycle once-persecond, assuming one of the proper time bases is in place,
the DVO-DV2 divider is not clear, and the SET bit in Register
B is clear. The SET bit in the "1" state permits the program
to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment
the seconds byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
the century byte. The update cycle also compares each
alarm byte with the corresponding time byte and issues an
alarm if a match or if a "don't care" code (11XXXXXX) is
present in all three positions.
With a 4.194304 MHz or 1.048576 MHz time base·the update cycle takes 248 p.s while a 32.768 kHz time base update
cycle takes 1984 p.s. During the update cycle, the time, calendar, and alarm bytes are not accessable by the processor
program. The MC146818 protects the program from reading
transitional data. This protection is provided by switching
the time, calendar, and alarm portion of the RAM off the
microprocessor bus during the entire update cycle. If the
processor reads these RAM locations before the update is
complete the output will be undefined. The update in progress (UIP) status bit is set during the interval.
A program which randomly accesses the time and date information finds data unavailable statistically once every 4032
attempts. Three methods of accommodating nonavailability
during update are usable by the program. In discussing the
three methods it is assumed that at random points user programs are able to call a subroutine to obtain the time of day.
The first method of avoiding the update cycle uses the
update-ended interrupt. If enabled, an interrupt occurs after
every update cycle which indicates that over 999 ms are
available to read valid time and date information. During this
time a display could be updated or the information could be
transfered to continuously available RAM. Before leaving the
interrupt service routine, the IRQF bit in Register C should be
cleared.
The second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in progress
or not. The UIP bit will pulse once-per-second. Statistically,
the UIP bit will indicate that time and date information is
unavailable once every 2032 attempts. After the UIP bit goes
high, the update cycle begins 244 p's later. Therefore, if a low
is read on the UIP bit, the user has at least 244 p's before the
time/calendar data will be changed. If a "1" is read in the
UIP bit, the time/calendar data may not be valid. The user
should avoid interrupt service routines that would cause the

FIGURE 16 -

REGISTERS
The MC146818 has four registers which are accessible to
the processor program. The four registers are also fully accessible during the update cycle.
REGISTER A ($OA)
Read/Write
Register
except UIP

UIP - The update in progress (UIP) bit is a status flag that
may be monitored by the program. When UIP is a "1" the
update cycle is in progress or will soon begin. When UIP is a
"0" the update cycle is not in progress and will not be for at
least 244 P.s (for all time bases). This is detailed in Table 6.
The time, calendar, and alarm information in RAM is fully
available to the program when ihe UIP bit is zero - it is not
in transition. The UIP bit is a read-only bit, and is not affected by Reset. Writing the SET bit in Register B to a "1"
inhibit any update cycle and then clear the UIP status bit.
TABLE 6 -

UPDATE CYCLE TIMES
Minimum Time
Update Cycle Time
Before Update
(tUC)
Cycle (tBUC)

UIP Bit

Time Base
(OSC1)

1

4.194304 MHz

248 p.s

-

1

1.048576 MHz

248 p's

-

1

32.768 kHz

1984 p's

0
0
0

4.194304 MHz

-

244 P.s

1.048576 MHz

-

244 P.s

32.768 kHz

-

244 P.s

UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIPS

UIP bit in _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-:~I--------Register
tU c

A _ \ . -_

UFb" m

'BUe

Register C

P~ bit In
Register C

r

~

__

tpi

------'-~r·

flmITI

tPI+2

l

~

L-_ _ _ _ _ _ _ _ _---'

tpi = Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62.5 ms, etc. per Table 5)
tUC= Update Cycle Time (248 P.s or 1984 p.s)
tBUC = Delay Time Before Update Cycle (244 P.5)

3-713

~.

ww...._ _ _ _ _ _ __

. _

tPI+2

I

MC146818

DV2, DV1, DVO - Three bits are used to permit the program to select various conditions of the 22-stage divider
chain. The divider selection bits identify which of the three
time-base frequencies is in use. Table 4 shows that time
bases of 4. 194304 MHz, 1.048576 MHz, and 32.768 kHz may
be used. The divider selection bits are also used to reset the
divider chain. When the time/ calendar is first initialized, the
program may start the divider at the precise time stored in
the RAM. When the divider reset is removed the first update
cycle begins one-half second later. These three read/write
bits are not affected by R"E'SIT.

II

quency specified in the rate selection bits (RS3 to RSOl appears on the SOW pin. When the SOWE bit is set to a zero
the SOW pin is held low. The state of SOWE is cleared by
the RESET pin. SOWE is a read/write bit.
DM - The data mode (OM) bit indicates whether time
and calendar updates are to use binary or BCD formats. The
DM bit is written by the processor program and may be read
by the program, but is not modified by any internal functions
or RESET. A "1" in DM signifies binary data, while a "0" in
DM specifies binary-coded-decimal (BCD) data.

RS3, RS2, RS1, RSO - The four rate selection bits select
one of 15 taps on the 22-stage divider, or disable the divider
output. The tap selected may be used to generate an output
square wave (SOW pin) and/ or a periodic interrupt. The program may do one of the following: 1) enable the interrupt
with the PIE bit, 2) enable the SOW output pin with the
SQWE bit, 3) enable both at the same time at the same rate,
or 4) enable neither. Table 5 lists the periodic interrupt rates
and the square-wave frequencies that may be chosen with
the RS bits. These four bits are read/write bits which are not
affected by RESET.

24/12 - The 24/12 control bit establishes the format of
the hours bytes as either the 24-hour mode (a "1") or the
12-hour mode (a "0"). This is a read/write bit, which is affected only by software.
DSE - The daylight savings enable (oSE) bit is a
read/write bit which allows the program to enable two
special updates (when DSE is a "1"). On the last Sunday in
April the time increments from 1:59:59 AM to 3:00:00 AM.
On the last Sunday in October when the time first reaches
1:59:59 AM it changes to 1:00:00 AM. These special updates
do not occur when the DSE bit is a "0". DSE is not changed
by any internal operations or reset.

REGISTER B ($OB)
Read/Write
Register

REGISTER C ($OC)
...M_s_B-.-_-.-_--..._--,.---_..--_~--r--L-S__,B Read-Only
Register

SET - When the SET bit is a "0", the update cycle functions normally by advancing the counts once-per-second.
When the SET bit is written to a "1", any update cycle in
progress is aborted and the program may initialize the time
and calendar bytes without an update occurring in the midst
of initializing. SET is a read/write bit which is not modified
by RESET or internal functions of the MC146818.

IRQF - The interrupt request flag !lROF) is set to a "1"
when one or more of the following are true:
PF=PIE="l"
AF= AIE= "1"
UF= UIE= "1"

PIE - The periodic interrupt enable (PIE) bit is a
read/write bit which allows the periodic-interrupt flag (PF)
bit in Register C to cause the IRO pin to be driven low. A program writes a "1" to the PIE bit in order to receive periodic
interrupts at the rate specified by the RS3, RS2, RS1, and
RSO bits in Register A. A zero in PIE blocks IRO from being
initiated by a periodic interrupt, but the periodic flag (PF) bit
is still set at the periodic rate. PI E is not modified by any internal MC146818 functions, but is cleared to "0" by a
RESET.

i.e., IRQF= PF·PIE+ AF·AIE+ UF·UIE
Any time the IROF bit is a "1", the IRO pin is driven low.
All flag bits are cleared after Register C is read by the program or when the RESET pin is low.
PF - The periodic interrupt flag (PF) is a read-only bit
which is set to a "1" when a particular edge is detected on
the selected tap of the divider chain. The RS3 to RSO bits
establish the periodic rate. PF is set to a "1" independent of
the state of the PIE bit. PF being a "1" initiates an IRO Signal
and sets the IROF bit when PIE is also a "1". The PF bit is
cleared by a RESET or a software read of Register C.

AlE - The alarm interrupt enable (AlE) bit is a read/write
bit which when set to a "1" permits the alarm flag (AF) bit in
Register C to assert IRO. An alarm interrupt occurs for each
second that the three time bytes equal the three alarm bytes
(including a "don't care" alarm code of binary llXXXXXX).
When the AlE bit is a "0", the AF bit does not initiate an IRO
signal. The RESET pin clears AlE to "0". The internal functions do not affect the AlE bit.

AF - A "1" in the AF (alarm interrupt flag) bit indicates
that the current time has matched the alarm time. A "1" in
the AF causes the IRQ pin to go low, and a "1" to appear in
the IRQF bit, when the AlE bit also is a "1." A RESET or a
read of Register C clears AF.

UIE - The UIE (update-ended interrupt enable) bit is a
read/write bit which enables the update-end flag (UF) bit in
Register C to assert IRO. The RESET pin going low or the
SET bit going high clears the UIE bit.

UF - The update-ended interrupt flag (UF) bit is set after
each update cycle. When the UIE bit is a "1", the "1" in UF
causes the IRQF bit to be a "1", asserting IRO. UF is cleared
by a Register C read or a RESET.

SQWE - When the square-wave enable (SOWE) bit is set
to a "1" by the program, a square-wave Signal at the fre-

b3 TO bO - The unused bits of Status Register" are read
as "0' s". They can not be written.

3·714

MC146818

REGISTER D ($OD)
MSB

processors. These interfaces assume that the address
decoding can be done quickly. However, if standard metalgate CMOS gates are used the TI setup time may be
violated. Figure 19 illustrates an alternative method of chip
selection which will accommodate such slower decoding.
The MC146818 can be interfaced to single-chip microcomputers (MCU) by using eleven port lines as shown in Figure
20. Non-multiplexed bus microprocessors can be interfaced
with additional support.
There is one method of uSing the multiplexed bus
MC146818 with non-multiplexed bus processors. The interface uses available bus control signals to multiplex the
address and data bus together.
An example using either the Motorola MC6800, MC6802,
MC6808, or MC6809 microprocessor is shown in Figure 21.
Figure 22 illustrates the subroutines which may be used for
data transfers in a non-multiplexed system. The subroutines
should be entered with the registers containing the following
data:
Accumulator A: The address of the RTC to be accessed.
Accumulator B: Write: The data to be written.
Read: The data read from the RTC.
The RTC is mapped to two consecutive memory locations RTC and RTC + 1 as shown in Figure 21.

LSB

I I I I I I I I I :::~st~~IY
Vb:T

b06

:5

:4

b:

:2

bl

:0

VRT - The valid RAM and time (VRT) bit indicates the
condition of the contents of the RAM, provided the power
sense (PS) pin is satisfactorily connected. A "0" appears in
the VRT bit when the power-sense pin is low. The processor
program can set the VRT bit when the time and calendar are
initialized to indicate that the RAM and time are valid. The
VRT is a read only bit which is not modified by the RESET
pin. The VRT bit can only be set by reading Register D.
b6 TO bO - The remaining bits of Register D are unused.
They cannot be written, but are always read as "O's."
TYPICAL INTERFACING
The MC146818 is best suited for use with microprocessors
which generate an address-then-data multiplexed bus.
Figures 17 and 18 show typical interfaces to bus-compatible

FIGURE 17 - MC146818 INTERFACED WITH
MOTOROLA COMPATIBLE MULTIPLEXED BUS MICROPROCESSORS

~8
....,

Addressl Data Multiplexed

8
y

Address Strobe
Data Strobe (E)

--"-

MC6801
MC146805E2

--

Read/Write (R/W)
Interrupt Request (IRO)

8/5

--.....

Address

8/5

V

V

t
I

Other
Peripherals
and
Memory

Address
Decode'

~
CE

I

'.tV
IRO R/W OS AS ADO-AD7

r=L

RESET
MC146818

RESET
CKOUT

------------

__ J

'High-Speed SiliconGate CMOS or TTL
Address Decoding

3-715

CKFS

I

SOW

cr

1

4.1 94304
MHZ (Typ)

I

MC146818

FIGURE 18 - MC146818 INTERFACED WITH
COMPETITOR COMPATIBLE MULTIPLEXED BUS MICROPROCESSORS

~8
~

"

Address/ Data

8

Address Latch Enable (ALE)

8085

~

Read (R)
~

8048

Write(W)

8049

Interrupt Request

..

-

l
8/4

Address

U

8085
Ocly

Address
Decode

I

1'1.
8/V

6+
-[1

~

V7

CE

IRQ R/W

DS

AS ADO-AD?

r=L

RESET

I

Other
Peripherals
and Memory

MC146818

RESET
SQW

lT

4.1 94304
MHZ (Typ)

1
FIGURE 19 - MC146818 INTERFACE WITH MC146805E2
CMOS MULTIPLEXED MICROPROCESSOR WITH SLOW ADDRESSING DECODING

-

Interrupt Request IIRQ)

.

Read/Write IR/WI
Address Strobe IASI
Data Strobe IDSI _

...

1

MC146805E2

5-? Non-multiplexed address

5 Non-Multiplexed Address

K
A

OSC1

I

I
I
I
I

I

I
I
I
I
I
I
~

~

I I

.~

I

8 Multiplexed Address/Data

U

...

IDS
A12

Address
Decode

~
DS

V
CE

~

AS R/W IRQ ADO-AD?

MC146818

RESET
CKOUT CKFS

~11
---- ------------

This illustrates the use of CMOS gating for address decoding.

3-716

i

VDD

SQW

1

Il

LT

4.194304 MHz
(Typl

MC146818

FIGURE 20 - MCl46818 INTERFACED WITH THE PORTS OF A
TYPICAL SINGLE CHIP MICROCOMPUTER

MC146818

MC3870
MC6805
MC146805
S2000
8021

Address! Data

ADO-AD7

Address Strobe
~----------------------~ AS
Read

SOW

CKFS

I

~----------------------~DS

Write

~----------------------~R/W

CKOUT

VSS

I
I

~~~~

I

L________ _

FIGURE 21 -

__...J

MCl46818 INTERFACED WITH MOTOROLA PROCESSORS

Active High Chip Select -----------------------,

OS
AO
MC146818
MC6800,
MC6802,
MC6808,
or
MC6809

R/W

AS

R/W

00-07

ADO-AD7

VSS

3-717

CE

MC146818

FIGURE 22 - SUBROUTINE FOR READING AND WRITING
THE MCl46818 WITH A NON-MULTIPLEXED BUS

I

READ

STA
LDAB
RTS

RTC
RTC+ 1

Generate AS and Latch Data from ACCA
Generate OS and Get Data

WRITE

STA
STAB
RTS

RTC
RTC+ 1

Generate AS and Latch Data from ACCA
Generate OS and Store Data

IMPORTANT NOTICES

Those devices made with date code 3N4GXXXX have the
fol/owing exceptions when used in the Motorola mode of
MOTEL.
1. VOO=3 to 5.25 V for operation
2. OS VIL =0.6 V Max.
The falling edge of chip select should occur during the active high pulse of address strobe, only on those units with
date code GC6XXXX.

3-718

®

MC146823

MOTOROI.A

Advance Information

CMOS
(HIGH-DENSITY HIGH-PERFORMANCE
SILICON-GATE)

PARALLEL INTERFACE
CMOS PARALLEL INTERFACE
The MC146823 CMOS parallel interface (CPI) provides a universal
means of interfacing external signals with the MC146805E2 CMOS
microprocessor and other multiplexed bus microprocessors. The unique
MOTEL circuit on-chip allows direct interfacing to most industry CMOS
microprocessors, as well as many NMOS MPUs.
The MC146823 CPI includes three bidirectional 8-bit ports or 241/0
pins. Each 1/0 line may be separately established as an input or an output under program control via data direction registers associated with
each port. Using the bit change and test instructions of the
MC146805E2, each individual 1/0 pin can be separately accessed. All
port registers are readlwrite bytes to accommodate read-modify-write
instructions. Features include:
•
•

24 Individually Programmed 1/0 Pins
MOTEL Circuit for Bus Compatibility with Many Microprocessors

•

Multiplexed Bus Compatibility with: MCl46805E2, MC6801, MC6803,
and Competitive Microprocessors

•
•

Data Direction Registers for Ports A, B, and C
Four Port CliO Pins May Be Used as Control Lines for:
Four Interrupt Inputs
Input Byte Latch
Output Pulse
Handshake Activity

•
•

15 Registers Addressed as Memory Locations
Handshake Control Logic for Input and Output Peripheral Operation

•
•

Interrupt Output Pin
Reset Input to Clear Interrupts and Initialize Internal Registers

•

3.0 Volt to 5.5 Volt Operating VDD

~

~

.,.
~

~~

P SUFFIX

~ SSUFFIX

CEROIP PACKAGE
CASE 734

Z SUFFIX
CHIP CARRIER
CASE 761

PIN ASSIGNMENT
PC2

VDD

PCl

PC3
PC4/CAl

PCO
PAO

4

PC5/CA2

PAl

PC6/CBl

PA2

PC7/CB2

PA4

PBO

PA6

PBl

8

PA5
10

32

PB2

31

PB3
PB4

11

ORDERING INFORMATION

12

29

PB5

(TA=O°C to +70°C)

13

28

PB6

14

27

PB7

15

26

IRO

25

Package Type
P Suffix

Ceramic (Side Brazed) Cerdip -

CASE 715

PLAS~~CS:~~1KAGE

PA3

Plastic -

L SUFFIX

CERAMIC PACKAGE

S Suffix

Chip Carrier - Z Suffix

Order Number
MCl46823P

L Suffix

MC146823L
MC146823S

AD4

16

MC146823Z

AD5

17

RESET
DS

18

R/W

AD7

19

AS

VSS

20

21

CE

Pin assignments are the same for both the dual-inline and chip carrier package.
This document contains information on a new product Specifications and information herein
are sublect to change without notice

3-719

I

MC146823

BLOCK DIAGRAM

PAO
PAl
PA2
PA3
PA4
PA5
ADO

PA6

ADl

PA7

AD2

I

AD3
AD4
AD5

PBO

AD6

PBl

AD7

PB2
PB3
PB4
PB5

Bus
Input
Register

PB6
PB7

rna
AS
DS

R/W

FfESTI

Control
Inputs

CE

VDD
VSS

;..

..

PCO
PCl
PC2
PC3
PC4/CAl
PC5/CA2
PC6/CBl

4

3-720

PC7/CB2

MC146823

MAXIMUM RATINGS IVoltages reference to VSSI
Ratings

Symbol

Value

Unit

VDD

-0.3 to +8.0

V

All Input Voltages

Yin

VSS - 0.5 to VDD + 0.5

V

Current Drain per Pin Excluding
VDD and VSS
Operating Temperature Range

10

rnA

TA

Supply Voltage

I

Storage Temperature Range

o to

+ 70

-55 to + 150

Tstg

°C
°C

THERMAL CHARACTERISTICS
Characteristics

Symbol

Value

Unit

8JA

50
100
60
TSD

°C/W

Thermal Resistance
Ceramic
Plastic
Cerdip
Chip Carrier

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Yin and V out be constrained to the range VSS ~IVin or Vout) ~VDD·
Leakage currents are reduced and reliability of
operation is enhanced if unused inputs are tied to
an appropriate logic voltage level le.g., either
VSS or VDDI.

DC ELECTRICAL CHARACTERISTICS IVDD = 5 Vdc ± 10%, VSS = 0 Vdc, T A = O°C to 70°C, unless otherwise noted)
Parameter

Symbol

Max

Unit

VOL
VOH

-

0.1

VDD-O.l

-

V
V

Output High Voltage
IILoad= -1.6 mAl ADO-AD7
IILoad= -0.2 mAl PAQ-PA7, PCO-PC7
IILoad= -0.36 mAl PSO-PS7

VOH
VOH
VOH

4.1
4.1
4.1

VDD
VDD
VDD

V

Output Low Voltage
IILoad= 1.6 rnA) ADO-AD7, PSO-PS7
IILoad=0.8 rnA) PAO-PA7, PCO-PC7
IILoad= 1.0 mAl IRQ

VOL
VOL
VOL

0.4
0.4
0.4

V

VIH
VIH

VSS
VSS
VSS
VDD-2.0
VDD-0.8

Output Voltage IILoad:S 10 p.A)

Input High Voltage, ADO-AD7, AS, OS, R/W, CE, PAO-PA7, PSO-PB7, PCO-PC7
RESET
Input Low Voltage IAII Inputs)

Min

V

VIL

VSS

VDD
VDD
0.8

Quiescent Current - No dc Loads
IAII Ports Programmed as Inputs, All Inputs= VDD - 0.2 V)

IDD

-

160

p.A

Total Supply Current
IAII Ports Programmed as Inputs, CE = VI L, tcyc = 1 p.s)

IDD

-

3.0

rnA

lin

-

±10

p.A

ITSL

-

± 10.0

p.A

Input Current, CE, AS, R/W, DS, FrrS'ET
Hi-Z State Leakage, ADO-AD7, PAO-PAl, PSO-PS7, PCO-PC7

V

EQUIVALENT TEST LOADS

VDD

TTL Equivalent

CMOS Equivalent
MMD6150
or Equiv

Test o-----4I..-----it--~--...
Point

C

MMD7000
or Equiv.

Pin
ADO-AD7

Rl
2.55k

R2

C

2.0k

130 pF

PAO-PA7, PCO-PC7

20.0k

4.32k

50 pF

PSO-PS7

11.5k

2.1k

50 pF

TestPoint~

For all outputs except IRQ

1

C = 50 pF; All Ports
= 130 pF; ADO-AD7
forVDD=5V ±10%

-=

I

C

4.02 k

90 pF

3-721

I

MC146823

BUS TIMING (VDD=5 Vdc ± 10%, VSS=O Vdc, TA=Oo to 70°C, unless otherwise noted)
Ident.
Number

I

Characteristics

Symbol

Min

Max

Unit

tcyc

1000

dc

ns

Pulse Width, DS/E Low or RD/WR High

PWEL

300

-

ns

PWEH

325

-

ns

4

Pulse Width, DS/E High or RD/WR Low
Input Rise and Fall Time

-

30

ns

8

R/W Hold Time

tRWH

10

tRWS

25

1

Cycle Time

2
3

CE

tr,tf

-

·ns

-

ns

ns

13

R/W and

15

Chip Enable Hold Time

tCH

0

18

Read Data Hold Time

tDHR

10

100

ns

21

Write Data Hold Time

tDHW

0

ns

24

Muxed Address Valid Time to ASI ALE Fall

tASL

25

25

Muxed Address Hold Time

tAHL

20

-

26

Delay Time DS/E to AS/ALE Rise

tASD

60

-

ns

27

Pulse Width, ASI ALE High

PWASH

170

-

ns

28

Delay Time, ASI ALE to DSI E Rise

tASED

60

-

ns

30

Peripheral Output Data Delay Time from DS/E or RD

tDDR

20

240

ns

31

Peripheral Data Setup Time

tDSW

220

-

ns

Setup Time Before DS/E

NOTE: DeSignations E, ALE, RD, and WR refer to signals from alternative microprocessor signals.

BUS TIMING DIAGRAM

AS

DS

R/W

ADOAD7
WRITE

ADOAD7
READ
NOTE: VHIGH = VDD - 2.0 V, VLOW = 0.8 V, for VDD = 5.0 V ± 10%

3-722

ns
ns

MC146823

BUS READ TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin)

RD (Read Output Enable)
(oS Pin)

WR (Write Enable)
(R/WPin)

IT (Chip

I

Enable)

ADO-AD7
(Address/Data B_us_)_ _ _ _ _ _ _ _ _ _ _

--<

BUS WRITE TIMING COMPETITOR MULTIPLEXED BUS

ALE (Address Latch Enable)
(AS Pin)

AD

(Read Output Enable)
(oS Pin)

WR

(Write Enable)
(A/Vii Pin)

CE(ChiPE_n_a_bl_e)_ _ _~~~~~~~~~~~~~~~~~_ _ _ _ _ _ _ _ _ _~~~~~~~~_

ADO-AD7
(Address/Dat';;,a.:;;B.:;;u;;:;s):.-_ _ _ _ _ _ _ _ _ _

-<

NOTE: VHIGH = VDD - 2.0 V, V LOW = 0.8 V, for VDD = 5.0 V

± 10%

3-723

MC146823

CONTROL TIMING (VDD=50Vdc ±10% VSS=OVdc TA=OOCt0700C)
Unit

Symbol

Min

Max

tlRQR

TBD

-

,..s

Delay, CAl (CB1) Active Transition to CA2 (CB2) High (Output Mode 0)

tC2

TBD

-

,..s

Delay, CA2 Transition from Positive Edge of AS (Output Modes 0 and 1)

tA2

TBD

-

,..5

Delay, CB2 Transition from Negative Edge of AS (Output Modes 0 and 1)

tB2

TBD

-

,..s

CA2/CB2 Pulse Width (Output Mode 1)

tpw

TBD

TBD

ns

tRLH

TBD

-

,..s

tRW

TBD

-

ns

Parameter
Interrupt Response (Input Modes 1 and 3)

Delay, VDD Rise to

RESIT High

Pulse Width, RESET
TBD=To be determined.

CONTROL TIMING DIAGRAMS

II

CA2/CB2 DELAY (OUTPUT MODE 1)

IRQ RESPONSE (INPUT MODES 1 AND 3)

r

CAl
CA2
AS

CA2/CB2
CA2/CB2 DELAY (OUTPUT MODE 0)

CA1/CBl

~_ _ _ _ _ _ _ _ _ _ _ __

----'--.r

tC2

CA2/CB2

AS

3-724

Read Pl DA/Write Pl DB Cycle

MC146823

GENERAL DESCRIPTION
The MC146823, CMOS parallel interface (CPI), contains 24
individual bidirectional 1/0 lines configured in three 8-bit
ports. The 15 internal registers, which control the mode of
operation and contain the status of the port pins, are accessed via an 8-bit multiplexed address/data bus. The lower four
address bits (ADO-AD3) of the multiplexed address bus
determine which register is to be accessed (see Figure 1).
The four address bits (AD4, AD5, AD6, and AD?) must be
separately decoded to position this memory map within each
256 byte address space available via the 8-bit multiplexed
address bus. For more detailed information refer to
REGISTER DESCRIPTION.
FIGURE 1 -

o

4

REGISTER ADDRESS MAP

Port A Data, Clear CA 1 Interrupt

P1DA

Port A Data, Clear CA2 Interrupt

P2DA

Port A Data

PDA

Port B Data

PDB

Port C Data

PDC

Not Used

~

Data Direction Register for Port A

DDRA

Data Direction Register for Port B

DDRB

Data Direction Register for Port C

DDRC

Control Register for Port A

CRA

A

Control Register for Port B

CRB

B

Pin Function Select Register for Port C

FSR

C

Port B Data, Clear CBl Interrupt

P1DB

D

Port B Data, Clear CB2 Interrupt

P2DB

Handshake/ Interrupt Status Register

HSR

Handshake Over-Run Warning Register

HWR

MOTEL
The MOTEL circuit is a concept that permits the
MC146823 to be directly interfaced with different types of
multiplexed bus microprocessors without any. additional
external logic. For a more detailed description of the multiplexed bus, see MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS (ADO-AD7i. Most multiplexed microprocessors use one of two synchronous buses to interface
peripherals. One bus was originated by Motorola in the
MC6803 and the other by Intel in the 8085.
The MOTEL circuit (for MOTorola and intEL bus) is built
into peripheral and memory ICs to permit direct connection
to either type of bus. A functional diagram of the MOTEL circuit is shown in Figure 2.

The CPI is implemented with the MOTEL circuit which
allows direct interface with either of the two major multiplexed microprocessor bus types. A detailed description of
the MOTEL circuit is provided in the MOTEL section.
FIGURE 2 Motorola Type
MPU Signals

Competitor Type
MPU Signals

Three data direction registers (DORsi, one for each port,
determine which pins are outputs and which are inputs. A
logic zero on a DDR bit configures its associated pin as an input; and a logic one configures the pin as an output. Upon
reset, the DDRs are cleared to logic zero to configure all port
pins as inputs.
Actual port data may be read or written via the port data
registers (PDA, PDB, and PDC). Ports A and B each have
two additional data registers (P1DA and P2DA - P1DB and
P2DBI which are used to clear the associated handshakel
interrupt status register bits (HSA1 and HSA2 - HSB1 and
HSB2), respectively. Port A may also be configured as an
8-bit latch when used with CAl. Reset has no effect on the
contents of the port data registers. Users are advised to
initialize the port data registers before changing any port pin
to an output.
Four pins on port C (PC4/CA1, PC5/CA2, PC6/CB1, and
PC7 I CB2) may additionally be programmed as handshake
lines for ports A and B via the port C function select register
(FSR). Both ports A and B have one input-only line and one
bidirectional handshake line each associated with them. The
handshake lines may be programmed to perform a variety of
tasks such as interrupt requests, setting flags, latching data,
and data transfer requests and/or acknowledgements. The
handshake functions are programmed via control registers A
and B (CRA and CRB). Additional information may be found
in PIN DESCRIPTIONS, REGISTER DESCRIPTION, or
HANDSHAKE OPERATION.

FUNCTIONAL DIAGRAM OF MOTEL CIRCUIT

MC146823
Pin Signals

Competitive Bus
D

AS

ALE

AS

C

Q

DS,E,orcf>2

R/W

Ri5

Internal
Signals

Q

Motorola
Bus

DS

Read Enable

R/W

Write Enable

3-725

I

MC146823

READ/WRITE (R/W)

The microprocessor type is automatically selected by the
MOTEL circuit through latching the state of the DS/RD pin
with AS/ ALE. Since DS is always low during AS and RD is
always high during ALE, the latch automatically indicates
with which type microprocessor bus it is interfaced.

The MOTEL circuit treats the R/W input pin in one of two
ways. First, when a Motorola microprocessor is connected,
R/W is a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on
R/W while DS is high, whereas a write cycle is a low on
R/W while DS is high.
The second interpretation of R/W is as a negative write
pulse, WR, MEMW, and !/OW from competitor's microprocessors. The MOTEL circuit in this mode gives the R/W pin
the same meaning as the write (W) pulse on many generic
RAMs.

PIN DESCRIPTIONS
The following paragraphs contain a brief description of the
input and output pins. References (if applicabl.e) are given to
other paragraphs that contain more detail about the function
being performed.

CHIP ENABLE (CE)

MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS
(ADO-AD7)

I

The IT input signal must be asserted (low) for the bus
cycle in which the MC146823 is to be accessed. EE is not
latched and must be stable prior to and during DS (in the
Motorola case of MOTEl) and prior to and during RD and
WR (in the other MOTEL case). Bus cycles which take place
without asserting EE cause no actions to take place within
the MC146823. When EE is high, the multiplexed bus output
is in a high-impedance state.
When EE is high, all data, DS, and R/W inputs'trom the
microprocessor are disconnected within the MC146823. This
permits the MC146823 to be isolated from a powered-down
microprocessor.

Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion of the bus cycle for
data. Address-then-data multiplexing does not slow the
access time of the MC146823 since the bus reversal from
address to data is occurring during the internal register
access time.
The address must be valid tAS L prior to the fall of
AS/ ALE at which time the MC146823 latches the address
present on the ADO-AD3 pins. Valid write data must be
presented and held stable during the latter portion of the DS
or WR pulses. In a read cycle, the MC146823 outputs eight
bits of data during the latter portion of the DS or RD pulses,
then ceases driving the bus (returns the output drivers to
high impedance) tDHR hold time after DS falls in the
Motorola case of MOTEL or RD rises in the other case.

RESET (RESET)
The RESET input pin is an active-low line that is used to
restore all register bits, except the port data register bits, to
logical zeros. After reset, all port lines are configured as inputs and no interrupt or handshake lines are enabled.

ADDRESS STROBE (AS)

INTERRUPT REQUEST (iRTI)

The address strobe input pulse serves to demultiplex the
bus. The falling edge of AS or ALE causes the addresses
ADO-AD3 to be latched within the MC146823. The automatic
MOTEL circuit in the MC146823 also latches the state of the
DS pin with the falling edge of AS or ALE.

The IRQ output line is an open-drain active-low signal that
may be used to interrupt the microprocessor with a service
request. The "open-drain" output allows this and other
interrupt request lines to be wire ORed with a pullup resistor.
The IRQ line is low when bit 7 of the status register is high.
Bit 7 (lRQF) of the handshake/interrupt status register
(HSR) is set if any enabled handshake transition occurs; and
its associated control register bit is set to allow interrupts.
Refer to INTERRUPT DESCRIPTION or HANDSHAKE
OPERATION for additional information.

DATA STROBE OR READ (OS)

The DS input pin has two interpretations via the MOTEL
circuit. When generated by a Motorola microprocessor, DS
is a positive pulse during the latter portion of the bus cycle,
and is variously called DS (data strobe), E (enable), or phase
2 (phase 2 clock). During read cycles, DS or RD signifies the
time that the CPI is to drive the bidirectional bus. In write
cycles, the trailing edge of DS or rising edge of WR causes
the parallel interface to latch the written data present on the
bidirectional bus.
The second MOTEL interpretation of DS is that of RD,
MEMR, or I/OR originating from the competitor's microprocessor. In this case, DS identifies the time period when the
parallel interface drives the bus with read data. This interpretation of DS is also the same as an output-enable signal
on a typical memory.
The MOTEL circuit, within the MC146823, latches the
state of the DS pin on the falling edge of AS/ ALE. When the
Motorola mode of MOTEL is desired DS must be low during
AS/ ALE, which is the case with the Motorola multiplexed
bus microprocessors. To insure the competitor mode of
MOTEL, the DS pin must remain high during the time AS/
ALE is high.

PORT A, BIDIRECTIONAL I/O LINES (PAO-PA7)

Each line of port A, PAO-PA7, is individually programmable as either an input or output via its data direction
register (DDRA). An 1/0 pin is an input when its corresponding DDR bit is a logic zero and an output when the DDR bit is
a logic one. See Figure 3 for typical 110 circuitry and Table 1
for I/O operation.
There are three data registers associated with port A:
PDA, Pl DA, and P2DA. Pl DA and P2DA are accessed when
certain handshake activity is desired. See HANDSHAKE
OPERATION for more information.
Data written to the port A data register, PDA, is latched
into the port A output latch regardless of the state of the
DDRA. Data written to Pl DA or P2DA is ignored and has no
affect upon the output data latch or the I/O lines. An MPU
read of port bits programmed as outputs reflect the last value
written to the PDA register. Port A pins programmed as inputs may be latched via the handshake line PC4/CA 1 (see

3·726

MC146823

FIGURE 3 - TYPICAL PORT 1/0 CIRCUITRY

To
And
From

CPU

TABLE 1 - PORT DATA REGISTER ACCESSES (ALL PORTS)
DDR
R/W Bit
Results
0 The 1/0 pin is in input mode. Data is written into the
0
output data latch
0
1 Data is written into the output data latch and output to the 1/0 pin
1
0 The state of the 1/0 pin is read.
1 The 1/0 pin is in an output mode. The output
1
data latch is read.

HANDSHAKE OPERATION) and latched input data may be
read via any of the three port A data registers. If the port A
input latch feature is not enabled, an MPU read of any port A
data register reflects the current status of the port A input
pins if the corresponding DDRA bits equal zero. Reset has
no effect upon the contents of the port A data register;
however, all pins will be placed in the input mode (all DDRA
bits forced to equal zero) and all handshake lines will be
disabled.
PORT B BIDIRECTIONAL 1/0 LINES (PBO-PB7)
Each line of port B, PBO-PB7, is individually programmable
as either an input or an output via its data direction register
(DDRB). An 1/0 pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one.
There are three data registers associated with port B:
PDB, P1DB, and P2DB. PDB is used for simple port B data
reads and writes. Pl DB and P2DB are accessed when certain
handshake activity is desired. See HANDSHAKE OPERATION for more information.
Data written to PDB or Pl DB data register is latched into
the port B output latch regardless of the state of the DDRB.
An MPU read of port bits programmed as outputs reflect the
last value written to a port B data register. An MPU read of
any port B register reflects the current status of the input
pins whose DDRB bits equal zero. Reset has no effect upon
the contents of the port B data register; however, all pins will
be placed in the input mode (all DDRB bits forced to equal
zero) and all handshake lines will be disabled.

PORT C, BIDIRECTIONAL 1/0 LINES (PCO-PC3J
Each line of port C, PCO-PC3, is individually programmable
as either an input or an output via its data direction register
(DDRC). An 1/0 pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one. Port C data register (PDC) is used for simple port C data
reads and writes.
Data written into PDC is latched into the port C data latch
regardless of the state of the DDRC. An MPU read of port C
bits programmed as outputs reflect the last value written to
the PDC register. An MPU read of the port C register reflects
the current status of the corresponding input pins whose
DDRC bits equal zero. Reset has no effect upon the contents
of the port C data register; however, all pins will be placed in
the input mode (all DDRC bits forced to equal zero) and all
handshake lines will be disabled.
PORT C BIDIRECTIONAL 1/0 LINE OR PORT A INPUT
HANDSHAKE LINE (PC4/CA1)
This line may be programmed as either a simple port CliO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port CliO pin,
PC41 CA 1 performs as described in the PCO-PC3 pin description. If programmed as a port A handshake line, PC4/CAl
performs as described in HANDSHAKE OPERATION.
PORT C BIDIRECTIONAL 1/0 LINE OR PORT A
BIDIRECTIONAL HANDSHAKE LINE (PC5/CA2)
This line may be programmed as either a simple port CliO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port CliO pin,
PC5!CA2 performs as described in the PCO-PC3 pin description. If programmed as a port A handshake line, PC5!CA2
performs as described in HANDSHAKE OPERATION.
PORT C BIDIRECTIONAL 1/0 LINE OR PORT B INPUT
HANDSHAKE LINE (PC6/CB1)
This line may be programmed as either a simple port CliO
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port CliO pin,
PC6!CBl performs as described in the PCO-PC3 pin description. If programmed as a port B handshake line, PC61 CB 1
performs as described in HANDSHAKE OPERATION.

•

MC146823

PORT C BIDIRECTIONAL 1/0 LINE OR PORT B
BIDIRECTIONAL HANDSHAKE LINE (PC7/CB2)
This line may be programmed as either a simple port C I/O
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port C I/O line,
PC7/CB2 performs as described in the PCO-PC3 pin description. If programmed as a port B handshake line, PC7!CB2
performs as described in HANDSHAKE OPERATION.

A summary of the handshake modes is given in the input
and output sections that follow. All handshake activity is
disabled by reset.
INPUT
Handshake lines programmed as inputs operate in any of
four different modes as defined by the control registers (see
Table 2). A bit in the handshake/interrupt status register
(HSR) is set to a logic one on an active transition of any
handshake line programmed as an input. Modes 0 and 1
define a negative transition as active; modes 2 and 3 define a
positive transition as active. If modes 1 or 3 are selected on
any input handshake line then the active transition of that
line results in the IRQF bit of the HSR being set to a logic one
and causes the interrupt line (IRQ) to go low. IRQ is released
by clearing the HSR bits that are input handshake lines
which have interrupts enabled.
If an active transition occurs while the associated HSR bit
is set to a logic one, the corresponding bit in the handshake
warning register (HWR) is set to a logic one indicating that
service of at least one active transition was missed. An HWR
bit is cleared to a logic zero by first accessing the appropriate
port data register, to clear the appropriate HSR status bit.
followed by a read of the HWR.

HANDSHAKE OPERATION

I

Up to four port C pins can be configured as handshake
lines for ports A and B (one input-only and one bidirectional
line for each port) via the port C function select register
IFSR). The direction of data flow for the two bidirectional
handshake lines (CA2 and CB2) is determined by bits 5 and
7, respectively, of the port C data direction register (DDRC).
Actual handshake operation is defined by the appropriate
port control register (CRA or CRB).
The control registers allow each handshake line to be programmed to operate in one of four modes. CA2 and CB2
each have four input and four output modes. For detailed information, see Tables 2 and 3.

TABLE 2 Control
Mode Register Bits*

INPUT HANDSHAKE MODES

Active
Edge

Status Bit
In HSR

IRQ Pin

0

00

- Edge

Set high on
active edge.

Disabled

1

01

- Edge

Set high on
active edge.

Goes low when corresponding
status flag in HSR goes high.

2

10

+ Edge

Set high on
active edge.

Disabled

3

11

+ Edge

Set high on
active edge

Goes low when corresponding
status flag in HSR goes high.

* Cleared

to logiC zero on reset.

TABLE 3 -

Mode

Control
Register
CRAIB)
Bits
3 and 4*

0

00

OUTPUT HANDSHAKE LINES (CA2 AND CB2 ONLY)

Handshake Line Set High
Handshake set high on active
transition of CA 1 input.

Handshake Line Cleared Low
Read of Pl DA or a read of P2DA
while HSAl is cleared.

Handshake set high on active
transition of CBl input.

Write of port B Pl DB or write
of P2DB while HSBl is cleared.

Default
Level
High

1

01

High on the first positive
(negative) transition of AS
while CA2 (CB2) is low.

Low on the first positive
(negative) transition on AS following a read (write) of port
A(B) data registers PlDA(B) or
P2DA(Bl.

High

2

10
11

Never
Always

Always
Never

Low
High

3

* Cleared

to logiC zero on reset.

3-728

MC146823

rna

(CRA and CRB), causes
to go low when IROF (interrupt
is released when
flag) in the HS R is set to a logic one.
IROF is cleared. See Handshake/Interrupt Status Register
under REGISTER DESCRIPTION for additional information.

INPUT LATCH

Port A input-only handshake line (PC4/ CA 1) can be programmed to function as a latch enable for port A input data
via CA 1 LE (bit 2 of CRA). If CA 1 LE is programmed to a
logic one, an active transition of PC4/ CA 1 will latch the current status of the port A input pins into all three port A data
registers (PDA, P1 DA, and P2DA). When CA 1 LE is enabled,
port A and PC4/ CA 1 function as an 8-bit transparent latch;
that is, if the HSA1 bit in the HSR is a logic zero then a read
of any port A register reflects the current state of the port A
input pins and corresponding bits of the output data latch for
portA output pins. If HSA1 is a logic one, a read of any port
A data register reflects the state of the port A input pins
when HSA 1 was set and the corresponding bits of the port A
output data latch for port A output pins.
Further transitions of PC4/ CA 1 result only in setting the
HWA 1 bit in the HWR and do not relatch data into the port A
registers. Latched data is released only by clearing HSA 1 in
the HSR to a logic zero (HSA1 is cleared by reading P1DA).

rna

REGISTER DESCRIPTION
The MC146823 has 15 registers (see Figure 1) which define
the mode of operation and status of the port pins. The
following paragraphs describe these registers.

I

Register Names:

Control Register A (CRA)
Control Register B (CRB)

OUTPUT

Register Addresses:

Each bidirectional handshake line programmed as an output by the DDRC operates in one of four modes as described
in Table 3. Modes 2 and 3 force the output handshake line to
reflect the state of bit 4 in the appropriate control register.
In modes 0 and 1, PC5/CA2 is forced low during the cycle
following a read of P1DA or a read of P2DA while HSA1 is
cleared. PC7/ CB2 is forced low during the cycle following a
write to P1DB or a write to P2DB while HSB1 is cleared.
Because of these differences, port A is the preferred input
port and port B is the preferred output port.
In mode U, PC5/CA2 (PC7/CB2) is set high by an active
transition of PC4/CA1 (PC6/CB1). In mode 1, PC5/CA2
(PC7/ CB2) is set high in the cycle following the cycle in
which PC5/ CA2 (PC7 / CB2) goes low. Mode 1 forces a lowgoing pulse on PC5/CA2 (PC7/CB2) following a read (write)
of P1DA (P1DB) or P2DA (P2DB) that is approximately one
cycle time wide.
When entering an output handshake mode for the first
time after a reset, the handshake line outputs the default
level as listed in Table 3.

$9 (CRA)
$A (CRB)
Register Bits:

o

4
$9

x

X

X

$A

X

X

X

CA2
Mode

CB2
Mode

CAl
LE
X

CAl
Mode

CBl
Mode

Purpose:

These two registers control the handshake and interrupt
activity for those pins defined as handshake lines by the
port C function select register (FSR)'

Description:

CA2 and CB2 are programmed as inputs or outputs via the
associated DDRC bits. Each handshake line is controlled
by two mode bits. Bit 2 of CRA enables the Port A latch
for an active CA 1 transition. Table 2 describes the input
handshake modes (CA1, CB1, CA2, CB2) and Table 3
describes the output handshake modes for CA2 and CB2.

INTERRUPT DESCRIPTION
The MC146823 allows an MPU interrupt request (IRO low)
via the input handshake lines. The input handshake line,
operating in modes 1 or 3 as defined by the control registers

3-729

MC146823

Register Names:
Port A Data Registers (PDA, PlDA, P2DA)

Register Names:
Port B Data Registers (PDB, PlDB, P2DB)

Register Addresses:
$2 (PDA), $0 (PlDA), $1 (P2DA)

Register Addresses:
$3 (PDB), $C(PlDB), $D (P2DB)

Register Bits:
Register Bits:

I

I

7
Bit 7

I Bit 6

Bit 5

4
Bit 4

Bit 3

Bit 2

Bit 1

I Bit 0 I

4

Bit 7

Purpose:
These three registers serve different purposes. PDA is
used to read input data and latch data written to the port A
output pins. P1 DA and P2DA are used to read input data
and to affect handshake and status activity for PC41 CA 1
and PC5/CA2. If enabled, port A input data may be latched into the three port A data registers on an active
PC41 CA 1 transition as described in HANDSHAKE
OPERATION.

Bit 6

Bit 5

I Bit 4 I Bit 3

I Bit 0 I

Description:
Data written into PDB and Pl DB port B registers is latched
into the port B output latch (see Figure 3) regardless of the
state of DDRB. Output pins, as defined by DDRB, assume
the logic levels of the corresponding bits in the port B output latch. Reads of any port B data registers reflect the
contents of the output data latch for output pins and the
current state of the input pins (as determined by DDRB).
Users are recommended to initialize the port B output
latch before changing any pin to an output via the DDRB.
MPU accesses of PlDB or P2DB are primarily used to affect handshake and status activity. A summary of the effects on status and warning register bits of port B data
register accesses is given in Table 5. For more information,
see HANDSHAKE OPERATION or Control Register B
(CRB) under REGISTER DESCRIPTION. Reset has no effect upon the contents of any port B data register.

MPU accesses of PlDA or P2DA are primarily used to affect handshake and status activity. A summary of the effects on the status and warning bits of port A data register
accesses is given in Table 4. For more information, see
HANDSHAKE OPERATION and Control Register A (CRA)
under REGISTER DESCRIPTION. Reset has no. effect
upon the contents of any port A data register.

TABLE 4 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT A DATA REGISTER ACCESSES
Output Latch
HSR Bit

Bit 1

Purpose:
These three registers serve different purposes. The Port B
data registers are used to read input data and to latch data
written to the port B output pins. Writes to PDB and P1 DB
affect the contents of the output data latch while writes to
P2DB do not affect the output data latch. P1 DB and P2DB
accesses additionally affect handshake and status activity
for PC6/CB1 and PC7ICB2.

Description:
Data written into PDA is latched into the port A output
latch (see Figure 3) regardless of the state of DDRA. Output pins, as defined by DDRA, assume the logic levels of
the corresponding bits in the PDA output latch. The PDA
output latch allows the user to read the state of the port A
output data. If the input latch is not enabled, a read of any
port A data register reflects the current state of the port A
input pins as defined by DDRA and the contents of the
output latch for output pins. Writes into P1 DA or P2DA
have no effect upon the output pins or the output data
latch. Users are recommended to initialize the port A output latch before changing any pin to an output via the
DDRA.

Register
Accessed

Bit 2

HWR Bit

Handshake Reaction

Read

Write

PDA

None

None

None

Yes

Yes

P1DA

HSAl cleared
to a logic
zero.

HWAl loaded
into buffer
latch.

CA2 goes low if output modes
o or 1 are selected in the CRA.

Yes

No

P2DA

HSA2 cleared
to a logic
zero.

HWA2 loaded
into buffer
latch.

CA2 goes low if output modes

Yes

No

o or 1 are selected in the CRA.

3-730

MC146823

TABLE 5 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS, WARNING BITS,
AND OUTPUT LATCH BY PORT B DATA REGISTER ACCESSES
Register
Accessed

Output Latch
HSR Bit

None

None

Yes

Yes

P1DB

HSB1 cleared
to a logic
zero.

HWB1 loaded
into buffer
latch.

CB2 goes low if output modes
o or 1 are selected in the CRB.

Yes

Yes

P20B

HSB2 cleared
to a logic
zero.

HWA2 loaded
into buffer
latch.

CB2 goes low if output modes
in CRB.

Yes

No

Register Bits:

I Bit 7 I Bit 6

4
Bit 5

Write

None

Register Address:
$4

6

Read

POB

Register Name:
Port C Data Register (PDC)

7

Handshake Reaction

HWR Bit

Bit 4

Bit 3

Bit 2

Bit 1

I Bit 0 I

Purpose:
The port C data register (PDC) is used to read input data
and to latch data written to the output pins.
Description:
Data is written into the port C output latch (see Figure 3)
regardless of the state of DDRC. Any port C pin defined as
a handshake line by the port C function select register
(FS R) is not affected by PDC. Output pins, as defined by
DDRC, assume logic levels of the corresponding bits in the
port C output latch. A read of PDC reflects the contents of
the output latch for output pins and the current state of
the input pins (as reflected in the DDRC). Reset has no effect upon the contents of PDC. Users are recommended
to initialize the port C output data latch before changing
any pin to an output via the DDRC.
Register Name:
Data Direction Register for Port A (8) (C)

o or 1 are selected

Description:
A logiC zero in a DDR bit places the corresponding port pin
in the input mode. A logic one in a DDR bit places the corresponding pin in the output mode. Any port C pins defined as bidirectional handshake lines also use the port C
DDR (DDRC). Input-only handshake lines are not affected
by DDRC. Reset clears all DDR bits to logic zero configuring all port pins as inputs. The DDRs have no write-inhibit
control over the port data output latches. Data may be
written to the port data registers even though the pins are
. configured as inputs.
Register Name:
Port C Pin Function Select Register (FSR)
Register Address:
$B
Register Bits:
7

6

I CFB21

CFB1

5

4

I CFA21 CFA1 I XX

XX

XX

XX

Purpose:
The port C pin function select register defines whether the
multifunction port C pins are to operate as "normal" port
C lines or as handShake lines.
Description:

Register Address:
$6 ($7) ($8)

Register Bits:

7

I Bit 7 I

4
Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

I Bit 0 I

Purpose:
Each of the three data direction registers (DDRA, DDRB,
and DDRC) define the direction of data flow of the port
pins for ports A, B, and C.

A logic zero in any FS R bit defines the corresponding port
C pin as a "normal" I/O pin. A logic one in any valid FSR
bit defines the corresponding port C pin as a handshake
line. Pins defined as handshake lines function according to
the contents of control register A (CRA) or control register
B (CRB). The port C data direction register (DDRC) is valid
regardless of FSR contents for all pins except PC4/CAl
and PC6/CB1. Transitions on port C pins not defined as
handshake pins do not effect the handshake/interrupt
status register. Reset clears all FS R bits to a logic zero.
Users are recommended to initialize the data direction and
control registers before modifying the FSR.

•

MC146823

I

Register Name:
Handshake/Interrupt Status Register (HSR)

Register Name:
Handshake Warning Register (HWR)

Register Address:
$E

Register Address:
$F

Register Bits:

Register Bits:

7

6

IIRQF I

XX

3
XX

2

1

0

4

XX I HSB21 HSA21 HSBl I HS A1 1

XX

XX

3

2

1

0

XX

Purpose:
The handshake interrupt status register is a read-only flag
register that may be used during a polling routine to determine if any enabled input handshake transition, as defined
by the control register (CRA and CRB), has occurred.

Purpose:
The warning register is a read-only flag register that may
be used to determine if a second attempt to set a handshake/interrupt status register bit has been made before
the original had been serviced.

Description:
If an enabled input handshake transition occurs then the
appropriate HSR bit (HSB2, HSA2, HSB1, or HSA1) is
set. The IRO flag bit (bit 7, IROF) is set when one or more
of the HSR bits 0-3 and their corresponding control
register bits are set to a logic one as shown in the following equation:

Description:
Each bit in the handshake/interrupt status register, except
IROF, has a corresponding bit in the handshake warning
register. If an attempt is made to set a bit in the handshake/interrupt status register that is already set, then the
corresponding bit in the handshake warning register is also
set. An attempt is the occurrence of any enabled input
handshake transition as defined by the control registers.

Bit 7= IROF= [HSB2-CRB2(3)] + [HSA2-CRA2(3)]
+ [HSB1-CRB1(Q)] + [HSA1-CRA1(Q)]

A handshake warning register bit is cleared by first reading
the appropriate data register then reading the handshake
warning register. Reading the data register (either P1 DA,
P2DA, P1 DB, or P2DB) loads a buffer latch with the proper bit in the handshake warning register (HWA 1, HWA2,
HWB 1, and HWB2, respectively). The next read of the
handshake warning register clears the appropriate bit
without affecting the other three handshake warning
register bits. The upper four bits, HWR4-HWR7, always
read as logic zeros. If a port data register is not read before
reading the handshake warning register, then the handshake warning register bits will remain unaffected. Reset
clears all HWR bits to a logic zero.

The numbers in ( ) indicate which bit in the control
register enables the interrupt.
Handshake/interrupt status register bits are cleared by
accessing the appropriate port data register. The following
table lists the HSR bit and the port data register that must
be accessed to clear the bit.
To Clear
HSR Bit
HSB2.
HSA2.
HSB1.
HSA1.

Access
Register
. ..... P2DB
. ..... P2DA
. ..... P1DB
...... P1DA

Recommended status register handling sequence:
1. Read status
register

Reset clears all handshake/interrupt status register bits to
a logic zero.

2. Read/write port
data indicated by
status register
3. Read warning
register

3-732

(User determines which if any
enabled handshake transition
occurred)
(Clears associated status bit and
latches appropriate warning
register bit in the buffer latch)
(Latched warning bit is cleared
and the remaining bits are unaffected)

MC146823

uses the MC146805E2 CMOS MPU. Other multiplexed
microprocessors can be used as easily.
A single-chip microcomputer (MCU) may be interfaced
with 11 port lines as shown in Figure 5. This interface also requires some software overhead to gain up to 13 additional
I/O lines and the MC146823 handshake lines.

TYPICAL INTERFACING
The MC146823 is best suited for use with microprocessors
which generate an address-then-data-multiplexed bus.
Figure 4 shows the MC146823 in a typical CMOS system that

FIGURE 4 -

A TYPICAL CMOS MICROPROCESSOR SYSTEM

MC146818
Real-Time Clock
Plus RAM

lMCM6551~

IMCM655161
16K ROM

16K ROM

Bus Control

0
w if)
:g~

3
8

ffd~
"-_ _ _ _---l

Al ....:2:..-+-_ _ _ _---1
7 Y

2

D2
Data
Inputs

Inputs

3

D4 15

Data- { : : :
Word a
4
Inputs
D2a

D5 14

D3. 3

D3

a

D6 13
Output ...:.1_ _ _-'
Enable a

D7 12

Address{ Al
Inputs
A2-------'

DO

DataWord b
12
Inputs { D2b
D3b 13

Vee~Pln
GND~

10

01: 11

Output Enable _7_ _ _ _---'
16
Pin 8

E~:~ .;.:15=---_ _-'

Vcc= Pin 16
GND=Pin8

HC251

HC157
HC158

MC54174HC157 - Nonlnvertlng Outputs
MC54!74HCl58-lnvertlng Outputs
DO
AO 2
Data Word
A Inputs

Dl

Al 5
A2 11
{

D2
Data
Inputs

A3 14

7 YO}
4

80 3
Data Word
8 Inputs

9

81 6
82 10

12

{

D3
D4 15
D5 14

Yl

Data

Y2

Outputs

D6 13
D7 12

Y3

83 13
Address {
Inputs

:~ ~~

9
A2"':::""--7
Output Enable ~---Vee~Pin 16
GND~

Pin 8

HC257

HC253
AO 14
Address
2
Inputs { Al

AO 2

-=+-+-------4
Data-Word
A Inputs

DOa 6
DataWord a
Inputs {

D1a 5
4

Al 5
A2 11
{

D2a

A3 14

D3 a 3

4 YO}
7
Yl Nontnverting
9
Data
12 Y2
Outputs

80 3

E~~~~~ ...:.1_ _ _ _ _ _ _---'

Data-Word
8 Inputs

81 6
82 10
{

Y3

83 13

DOb 10
DataWord b
Inputs

{

Dlb II
12
D2b
D3b 13

Vee~
GND~

Pin 16
Pin 8

Vee ~ Pin 16
GND~ Pm 8

E~~~~~ -'-15~_ _ _ _ _ ____'

7-25

I

DIGITAL DATA SELECTORS/MULTIPLEXERS

HC298

AD
Data-Word
A Inputs

A1
A2

1

{
Quad
2-lnput
Data
Selector/
Multiplexer

A3

80
Data-Word
B Inputs

81
82

Output
Latch

4

;:

~~}

~ Y2
12

Noninverting
Data
Outputs

Y3

{

83
Select _1_0_ _---J
11
Latch
Clock - - -_ _ _ _ _-----J

VCC= Pin 16
GND= Pin 8

DECODERS/
DEMULTIPLEXERS/
DISPLAY DRIVERS

Device
Number
MC54/MC74

Functional
Equivalent
LSTIL
Device
54174

Function

HC42
HC137
HCl38
HCTl38
HC139

1-of-10 Decoder
1-of-8 Decoder/Demultiplexer with Address Latch
1-of-8 Decoder/ Demultiplexer
1-of-8 Decoder/Demultiplexer with LSTTL-Compatible Inputs
Dual 1-of-4 Decoder/Demultiplexer

HC147
HCl54

Decimal-to-BCD Priority Encoder
1-of-16 Decoder/ Demultiplexer

HC237
HC259
HC4511

1-of-8 Decoder/Demultiplexer with Address Latch
8-Bit Addressable Latch/ 1-of-8 Decoder
BCD-to-Seven-Segment Latch/ Decoder/ Display Driver

HC4514

1-of-16 Decoder/Demultiplexer with Address Latch

* LSl54,

HC4543

BCD-to-Seven-Segment Latch/ Decoder/ Display Driver for
Liquid-Crystal Displays

* LS159
* LS47,
* LS48,
* LS49

LS42
LS137
LSl38
LSl38
LS139
LS147
LSl54,
* LS159
* LS137
LS259
* LS47,
* LS48,
* LS49

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
orCDXXXX Compatibility
Pins
*4028
*4028
*4028
*4028
4556

LS
LS
LS
LS
LS/CMOS

16
16
16
16
16

*4515

LS
LSl54

16
24

*4028
*4099
4511

LS
LS
CMOS

16
16
16

4514,
*4515
4543

LS/CMOS

24

CMOS

16

* Suggested alternative

I

7-27

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS

Device
#Pins
Input Description

Output Description
Single Device
Dual Device

HC42

HC137

HCl38

HCTl38

16

16

16

HCl39
16

HC147

16
BCD Address

3-Bit Binary
Address

3-Bit Binary
Address

3-Bit Binary
Address

2-Bit Binary
Address

Any
Combination
of 9 Inputs

One of 10

One of 8

One of 8

One of 8

One of 4

·

·
··
·
··

·

·

BCD Address of
Highest Input

·

·

·
..

·
..
·

·
·

··

Address Input Latch
Active-High Latch Enable
Active-Low Latch Enable
Active-Low Inputs
Active-Low Outputs
Active-High Outputs

·

Active-Low Output Enable
Active-High Output Enable
Active-Low Reset

·

16

Active-Low Blanking Input
Active-Low Lamp-Test Input
Phase Input (for LCD's)

·

LSTTL-Compatible Inputs

Device

HCl54

HC237

HC259

HC4511

HC4514

# Pins

24

16

16

16

24

16

4-Bit Binary
Address

3-Bit Binary
Address

3-Bit Binary
Address

BCD Data

4-Bit Binary
Address

BCD Data

One of 16

One of 8

One of 8

One of 16

·

·
··

·

7-Segment
Display

7-Segment
Display

·

··

··

Input Description
Output Description
Single Device
Dual Device
Address Input Latch
Active-High Latch Enable
Active-Low Latch Enable
Active-Low Inputs
Active-Low Outputs
Active-High Outputs
Active-Low Output Enable
Active-High Output Enable
Active-Low Reset

I

..

·

·

Active-Low Blanking Input
Active-Low Lamp-Test Input
Phase Input (for LCD's)
LSTTL-Compatible Inputs

7·28

·

HC4543

·

·
··

·
·

·
·

·

··

·

··

·
·

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS

HC42

HC137
YO

15
AD
ILSBI

Y1
Address
Inputs

Y2

parent

Yl

Latch
Y2

A2

14

Y3

Al

Y4

BCD
Address

Y5

Inputs

r

YO
Trans-

Al

Y3

Latch Enable

Inverting
Outputs

Y4
Y5

13
A2

Y6

Y6

Y7

Y7
Y8

12
A3
IMSBI

Chip- {CSl
Select
Inputs
CS2

Y9

VCC ~ Pin 16
Pin 8

GND~

HC138
HCT138
Address
Inputs

HC139

r

15

YO

' ' "{ '"'[Jf"}
Inputs

Al

Yl

A2

Y2

Ala

5

3

6

7

Y3
Y4

Inverting
Outputs

CSa

Yl a
Y2
a
Y3 a

Inverting
Outputs

1

Y5
Y6
Address {
Inputs

Y7

AOb
Alb

14
Yl b } Inverting
">

13

Y2b

Outputs

Y3b
Chlp- {
Select

CSl
CS2

Inputs

CS3

CSb
Pin 16~VCC
Pin 8~ GND

15
VCC~
GND~

HC147

Pin 16
Pin 8

HC154
YO~ABC5
Yl~ABC5
Y2~A BCD

Dl
D2
D3
DeCimal

D4

Data Inputs
(Active-Low)

D5

A1
A2

'"J
A3

D7

r

Y5~ABCD

23

9

D6

Y3~A BCD
Y4~AB CD

BCD

Binary

Address

Address
Inputs

Outputs
(Active-Low)

A1

A2

A3

D8
D9

Y6~A BCD

22

Y7~ABCD

Inverting

21

Y8~ABCD

Outputs

20

Vcc~Pin16
GND~Pin8

7-29

Chip {
Select

CSl

Inputs

CS2

18
VCC~

Pin 24
GND ~ Pin 12

I

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS

HC237

HC259

15

AO
Address
Inputs

Transparent
Latch

Al
{

14
13

A2

12
l-of8
Latch
Enable - - ' - - - - '

11

Decoder

10

YO
Address
Inputs

Yl
Y2

00

AO
Al
{

Ot

02

A2

03

Y3

04
Y4

Data In

13

Y5
Y6

10

05

11

06

12

07

Y7
Reset

Chip- {
Select
Inputs

CSI

16= VCC
Pin 8=GND

CS2--"------------'

HC4514

HC4511

AILSBI 7
1
B

BCD
Inputs

~

C

{

Enable ..;..;....----'
VCC = Pin 16
GND= Pin 8

11
9
10
8

13
12
4-Blt
and

D IMSBI

11

SevenSegment

10

OisplayDriver
Outputs

AO
Binary
Address
Inputs

15
14

Al 3
21

{

A3

4-Blt
Storage

4-to-16
L"lne
Decoder

Latch

22

Latch 1 '----...------'
LE
BI

Control
Inputs

{

Chip
Select

HC4543

I

SevenSegment

8CD
Inputs

DisplayDriver
Outputs

DIMSBI

Control
Inputs

4

{LB~-;::~_ _ _ _ _ _ _~
Ph..;.6_ _ _ _ _ _ _ _ _ _--'

7-30

Y6

4
Y7
18
Y8
17
Y9
20 Y10
19
Yll
14

~~;

Enable

13
16
Y14
15 Y15

LT

VCC=PI016
GND= Pin 8

Y2
Y3
Y4
Y5

2

A2

YO
Yl

23
VCC = Pin 24
GND=Pin 12

Nonlnvertlng
Outputs

ANALOG SWITCHES/
MULTIPLEXERS/
DEMULTIPLEXERS

Functional
Equivalent
LSTTL
Device

Device
Number
MC54/ MC74

HC4016
HC4051
HC4052
HC4053
HC4066

* HC4316
* HC4351
* HC4352
* HC4353

54174

Function

Quad Analog Switch/Multiplexer/Demultiplexer
8-Channel Analog Multiplexer/Demultiplexer
Dual 4-Channel Analog Multiplexer/Demultiplexer
Triple 2-Channel Analog Multiplexer/Demultiplexer
Quad Analog Switch/Multiplexer/Demultiplexer with Enhanced
On-Resistance Linearity
Quad Analog Switch/Multiplexer/Demultiplexer with Separate
Analog and Digital Power Supplies
8-Channel Analog Multiplexer/Demultiplexer with Address Latch
Dual4-Channel Analog Multiplexer/Demultiplexer with Address Latch
Triple 2-Channel Analog Multiplexer/Demultiplexer with Address Latch

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
or CDXXXX Compatibility
Pins

4016,4066
4051
4052
4053
4066,4016

CMOS
CMOS
CMOS
CMOS
CMOS

14
16
16
16
14

*4016

16

*4051
*4052
*4053

18
18
18

* Suggested alternative

* High-Speed CMOS design only

I

7-31

ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS

Device
#Pins
Description

Single Device
Dual Device
Triple Device
Quad Device
1-t0-1
2-to-1
4-to-1
8-to-1

Multiplexing
Multiplexing
Multiplexing
Multiplexing

Active-High ON/OFF Control
Common Address Inputs
2-Bit Binary Address
3-Bit Binary Address
Address Latch with Active-Low
Latch Enable

HC4016

HC4051

HC4052

HC4053

14

16

16

16

14

4 Independently
Controlled
Switches

A 3-Bit Address
Selects
One of 8
Switches

A 2-Bit Address
Selects
One of 4
Switches

A 3-Bit Address
Selects Varying
Combinations of
the 6 Switches

4 Independently
Controlled
Switches

·

·

··
·

··
··
·

·
··

Common Switch Enable
Active-Low Enable
Active-High Enable

·

Separate Analog and Control
Reference Power Supplies

·
·
·
·
··
·

·

·

HC4066

··
·

·

Switched tubs (for RON and
Prop. Delay Improvement)

Device
#Pins
Description

Single Device
Dual Device
Triple Device
Quad Device
1-t0-1
2-to-1
4-to-1
8-to-1

I

Multiplexing
Multiplexing
Multiplexing
Multiplexing

Active-High ON/OFF Control
Common Address Inputs
2-Bit Binary Address
3-Bit Binary Address
Address Latch with Active-Low
Latch Enable
Common Switch Enable
Active-Low Enable
Active-High Enable
Separate Analog and Control
Reference Power Supplies

HC4316

HC4351

HC4352

16

18

18

18

4 Independently
Controlled
Switches.
(Has a separate
Analog Lower
Power Supply)

A 3-Bit Address
Selects
One of 8
Switches.
(Has an Address
Latch)

A 2-Bit Address
Selects
One of 4
Switches.
(Has an Address
Latch)

A 3-Bit Address
Selects Varying
Combinations of
the 6 Switches.
(Has an Address
Latch)

··
·

·

·
··
..
··
·

··

·

Switched tubs (for RON and
Prop. Delay Improvement)

7-32

HC4353

·

·

·
··
·
..
··
·

·

·
··
..
··
·

ANALOG SWITCHES/MULTIPLEXERS/OEMULTIPLEXERS

HC4016

HC4051

XA~2YA
13
A On/ Off Control

XB~Y8

Analog
Inputs/Outputs

Bon/OffControl~

X5

Analog
Outputs/Inputs
X7

"¥"

C On/Off Control

11
Binary {A ILSBI 10
Channel-Select
B--'-'------'
Inputs C IMSBI-9_ _ _ _----'

6

XD~l
10

Enable ....;6'--_ _ _ _---'

YD

Vee=- Pin 16= Positive analog and digital power supply
VEE ~ Pin 7 ~ Negative analog power supply
GND~ Pin 8~ Negative digital power supply

12
D On/Off Control
NOTE

XA. XB. XC. XD~ Analog Inputs/Outputs
Vcc~Pin

Common
Outputllnput

X4

Control inputs are referenced to GNO. Analog inputs/outputs are
referenced to VEE. VEE must be ~GND

14

GND~Pin7

HC4053

HC4052

-~-)

Analog
Inputs/Outputs

Analog
I nputs/ Outputs

Common
Outputllnput

Binary
{
Channel-Select

Binary
{ A ILSBJ 10
Channel-Select
9
Inputs
B IMS8J~------'

Inputs

Common

Outputs/ Inputs

~~

A ILSBJ
B-=------'
CIMSBI-=-9-------'

6_ _ _ _ _----'
Enable-

Enable,.:.6_ _ _ _ _---'

Vee= Pin 16= Positive analog and digital power supply

Vee= Pin 16= Positive analog and digital power supply

VEE= Pin 7= Negative analog power supply
GND= Pm 8= Negative digital power supply
NOTE

VEE = Pin 7 = Negative analog power supply
GNO= Pin 8= Negative digital power supply

Controlmputs are referenced to GND Analog Inputs/outputs are
referenced to VEE VEE must be s GND

NOTE Control inputs are referenced to GNO. Analog inputs/outputs are
referenced to VEE. VEE must be ::5:GNO

HC4066

HC4316

XA~2YA

XA-----~

I

13
A Onl Off Control
A On/Off Control

XB~Y8
B On/Off Control

~

XB -I-----~

YB

Analog
Outputs/Inputs

Analog
Outputs/Inputs

B On/Off Control

XC~YC
~

YC

C On/Off Control

XD

1

~

C On/ Off Control

10

YD
XD

12

D On/ Off Control

YD

Vcc~Pin16
GND~

Pin 8

VEE~Pin9

D On/Off Control
VEE"GND
Enable -~~_ _---'
XA. XB. XC. XD ~ Analog Inputs/Outputs

XA. XS. Xc. XO= Analog Inputs/Outputs
Vee = Pin 14
GND~Pln

~I----""

7

7·33

ANALOG SWITCHES/MULTIPLEXERS/OEMULTIPLEXERS

HC4351

Analog
Inputs/Outputs

Multiplexer/
Demultiplexer

B

12

{

x}

Common
Outputllnput

Vee= Pm 18= Postive analog and digital power supply
VEE ~ Pin 8~ Negative analog power supply
GND~ Pin 9~ Negative digital power supply

AILSBI 13

Binary
Channel-Select
Inputs

3

Channel
Address
Latch

C IMSSI 11
Latch Enable 10
{Enablel
6
.
Switch
7
Enables
Enable 2 - ' - - - - - - - - - - - - - - '

HC4352
15

X

Analog
Inputs/Outputs

•

Common
Outputs/Inputs

3 Y

A ILSBI

Binary
Channel-Select
Inputs

VCC~

12

VEE~

Pin IS~ Postive analog and digital power supply
Pin S~ Negative analog power supply

GND = Pin 9 = Negative digital power supply

B IMSBI 11
{

Enable 1 6
7
Enable2 " ' - - - - - - - - - - - - - - - '

Switch
Enables
{

HC4353
X Switch

Analog

I

Y Switch

Inputs/Outputs

Z Switch

Vee = Pm

18 = Postive analog and digital power supply
VEE ~ Pin 8 ~ Negative analog power supply
GND~ Pin 9~ Negative digital power supply

AILSBI 13
Binary
Channel-Select
Inputs

B

12

{

Channel
Address
Latch

CIMSSI 11
.

Latch Enable 10
Enable 1

SWitch
Enables

6

Enable 2 -'-_ _ _ _ _ _ _------'
{

NOTE: Control Inputs are referenced to GND. Analog Inputs/outputs are referenced to

7-34

Vee Vee

must be ::sGND

SHIFT REGISTERS

Device
Number
MC54/MC74

Functional
Equivalent
LSTTL
Device
54/74

Function

HCl64
HC165
HC166
HCl94
HC195

8-Bit
8-Bit
8-Bit
4-Bit
4-Bit

HC299

8-Bit Bidirectional Universal Shift Register with 3-State Parallel Outputs
8-Bit Serial- or Parallel-Input/ Serial-Output Shift Register with
3-State Output
8-Bit Serial-Input/ Serial- or Parallel-Output Shift Register with
Latched 3-State Outputs
8-Bit Serial- or Parallel-Input/ Serial-Output Shift Register with
Input Latch
Dual 4-Bit Serial-Input/Parallel-Output Shift Register

* HC589

HC595
HC597
HC4015

Serial-Input/Parallel-Output Shift Register
Serial- or Parallel-lnput/Serial-Output Shift Register
Serial- or Parallel-Input/Serial-Output Shift Register with Reset
Bidirectional Universal Shift Register
Universal Shift Register

LSl64
LS165
LS166
LS194A
LS195A

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
orCDXXXX Compatibility
Pins
*4034
*4021
*4021
4194
*4035

LS
LS
LS
LS/CMOS
LS

14
16
16
16
16

LS

20
16

*4034

LS

16

LS

16

4015

CMOS

16

LS299
* LS597
LS595
LS597

* Suggested alternative

* High-Speed CMOS design only
Device
#Pins

HCl64

HC165

. HCl66

HC194

HC195

HC299

HC589

HC595

HC597

HC4015

14

16

16

16

16

20

16

16

16

16

4-Bit Register
8-Bit Register
Serial Data Input
Parallel Data Inputs
Serial Output Only
Parallel Outputs
Inverting Output
Noninverting Output
Serial Shift/ Parallel Load Control
Shifts One Direction Only
Shifts Both Directions
Positive-Transition Clocking
Active-High Clock Enable
Input Data Enable
Data Latch with Active-High
Latch Clock

I

Output Latch with Active-High
Latch Clock
3-State Outputs
Active-Low Output Enable
Active-High Reset
Active-Low Reset

7-35

SHIFT REGISTERS

HC165

HC164
Serial {Al
Data
Inputs
A2

A

1

Data

°A
08

13

°c
00
10
11
12
Clock

8

13

11
12

°E

Parallel
Data
Inputs

Parallel
Data
Outputs

9 °H

14

QH

l

Serial
Data
Outputs

OF
°G

Serial
Data
Input

°H

Reset -:;.9_ _ _---'
VCC= Pin 16
GND= Pin 8

VCC= Pin 14
GND= Pin 7

HC166

HC194

13

0H

}

Parallel

Senal
Data
Output

2

A

3

10

Data

Inputs

11

Parallel
8
Data
Inputs { C

12
14
Serial
Data
Input

Serial {SA
Data
Inputs So

15
14

OAl Parallel

08

°c
12 00

Data
Outputs

o

{

SA

Clock

Serial Shift/Parallel Load

Mode {S1 10
Select
SO ~

15

Reset - - - - -....
Clock 1
VCC= Pin 16
GND= Pin 8

Reset 9 Clock 2

HC195

HC299

Serial Data

I

Inputs

{J

2

15

K

14
13

Parallel { :
Data
Inputs
C

12

o
11
Clock

°A
3-State

Os
°c

Serial

Data
Inputs {

Parallel
Data
Outputs

AH

118

Parallel Data Ports

(Inputs/ Outputs)

1

00

GO

Clock

12
Serial Data

Outputs
Serial Shift/
Reset

Parallel Load

Reset

Mode {S1
Select
S2 --'-------'
Vcc=Pin 16
GND= Pin 8

Output {OEl
Enables
OE2

7-36

-=-------'

VCC= Pin 20
GND= Pin 10

SHIFT REGISTERS

HC589

HC595

Serial {
Data SA

.!:14~_ _ _ _~

Input
A

Serial {
Data
A
Input

15

14

15

OA
OB
Oc

VCC~

Parallel
Data
Inputs

GND~

Input
Latch

Pin 16
Pin 8

Latch

Shift
Register

Shift
Register

°D

Parallel
Data

OE

Outputs

OF
OG

9

°H

OH

} Serial

Data
Output

Latch Clock 12

9

L-+--4--':::'

Reset

{
SOH

Serial
Data
Output

Shift Clock ..:.11'---_ _ _ _-.J

~::!~I~~t~~~

~~~~~: -1"'3----V-C-C-~-Pi-n-16-...J

.!:13:::..-_ _ _ _ _ _ _ _......I

GND~

Output Enable .!:1O:::..-_ _ _ _ _ _ _ _ _ _ _----'

HC597

HC4015

Serial Data {..:.14'--_ _ _ _----.
Input
SA

4

OBI

3

B 1

OCI

9

Clock 1

C 2

Parallel
Data
Outputs

10

ODI

D 3
E 4

0)
°Al

7

Serial Input Data Al
A 15

Parallel
Data
Inputs

Pin 8

Data
Latch

Shift
Register

Reset 1

F 5

6

G 6
H 7

13

9

}
OH

Serial
Data
Output

Serial Input Data A2

15

12

Latch Clock 12

OM)
°B2
Parallel

11
OC2

Data
Outputs

Clock 2
Shift Clock ..:.11'--_ _ _ _-----'

~::~~I~~t~~~

.::13::..-_ _ _ _ _ _ _.-J

Reset ..:.10::...-._ _ _ _ _ _ _ _-'

OD2
Reset 2

Vcc~Pin
GND~

16
Pin 8

14
VCC= Pin 16
GND~ Pin 8

I

7-37

COUNTERS

Device
Number
MC54/MC74

Function

Functional
Equivalent
LSTIL
Device
54/74

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
orCDXXXX Compatibility
Pins
14
14
14
16
16

HC90
HC92
HC93
HC160
HC161

4-Stage Binary Ripple Counter with -:- 2 and -:- 5 Sections
4-Stage Binary Ripple Counter with -:- 2 and -:- 6 Sections
4-Stage Binary Ripple Counter with -:- 2 and -:- 8 Sections
Presettable BCD Counter with Asynchronous Reset
Presettable 4-Bit Binary Counter with Asynchronous Reset

LS90
LS92
LS93
LS160A
LS161A

4160
4161

LS
LS
LS
LS/CMOS
LS/CMOS

HC162
HC163
HCl90
HC191
HC192

Presettable
Presettable
Presettable
Presettable
Presettable

LS162A
LS163A
LS190
LS191
LS192

4162
4163
*4510
*4516
*4510

LS/CMOS
LS/CMOS
LS
LS
LS

16
16
16
16
16

HC193
HC390
HC393
HC4017
HC4020

Presettable 4-Bit Binary Up/Down Counter with Reset
Dual 4-Stage Binary Ripple Counter with, -:- 2 and -:- 5 Sections
Dual 4-Stage Binary Ripple Counter
Decade Counter/Divider
14-Stage Binary Ripple Counter

LS193
LS390
LS393

*4516
*4520
4017
4020

LS
LS
LS
CMOS
CMOS

16
16
14
16
16

HC4024
HC4040
HC4060
HC4518
HC4520

7-Stage Binary Ripple Counter
12-Stage Binary Ripple Counter
14-Stage Binary Ripple Counter with Oscillator
Dual BCD Counter
Dual 4-Bit Binary Counter

4024
4040
4060
4518
4520

CMOS
CMOS
CMOS
CMOS
CMOS

14
16
16
16
16

BCD
4-Bit
BCD
4-Bit
BCD

Counter with Synchronous Reset
Binary Counter with Synchronous Reset
Up/Down Counter
Binary Up/Down Counter
Up/Down Counter with Reset

* Suggested alternative

I

7-38

COUNTERS

He

He

He

He

He

He

He

He

He

He

Device

90

93

162

163

190

16

16

16

16

191
16

192

14

160
16

161

#Pins

92
14

Single Device
Dual Device
Ripple Counter
Number of Ripple Counter
Internal Stages
Number of Stages with
Available Outputs
Count Up
Count Down
4-Bit Binary Counter
BCD Counter
Decimal Counter
Separate
Separate
Separate
Separate

-+ 2
-+ 5
-+ 6
-+ 8

Section
Section
Section
Section

On-Chip Oscillator Capability
Separate Count-Up and
Count-Down Clocks
Count Up/Count Down
Control Input
Positive- Transition Clocking
Negative-Transition Clocking
Active-High Clock Enable
Active-Low Clock Enable
Active-High Count Enable
Active-Low Count Enable
Active-High Set
Active-High Reset
4-Bit Binary Preset Data Inputs
BCD Preset Data Inputs
Active-Low Load Preset
Carry Output
Borrow Output
Ripple Clock Output

14

16

4

· · · · · · · · ·
· ·
4

4

4

4

4

·
·

· · · · · · ·· ·· ··
· · · · · · · ·
· ·
· ·
·
· ·
· · · · · · · · · ·
.. .. .. ..
·· · · · · · · · · ·
·
·
·
··· ·· ··· ·· ··· ·· ···
· · ·
·
·
··

I

7-39

COUNTERS

He
193

He

He

393

He
4020

He
4024

He

390

He
4017

He

Device

4040

4060

He
4518

He
4520

#Pins

16

16

14

16

16

14

16

16

16

16

Single Device
Dual Device
Ripple Counter
Number of Ripple Counter
Internal Stages
Number of Stages with
Available Outputs
Count Up
Count Down
4-Bit Binary Counter
BCD Counter
Decimal Counter
Separate
Separate
Separate
Separate

+
+
+
+

2
5
6
8

Section
Section
Section
Section

On-Chip Oscillator Capability
Separate Count-Up and
Count-Down Clocks
Count Up/Count Down
Control Input
Positive-Transition Clocking
Negative- Transition Clocking
Active-High Clock Enable
Active-Low Clock Enable
Active-High Count Enable
Active-Low Count Enable
Active-High Set
Active-High Reset
4-Bit Binary Preset Data Inputs
BCD Preset Data Inputs
Active-Low Load Preset
Carry Output
Borrow Output
Ripple Clock Output

· · · · · · · · · ·
· ·
· · · ·
4

4

14

7

12

14

4

4

12

7

12

10

·· · ·
· · ·
··
·
· · ·

· · · · · · ·
·
·
·
·

··· · · · ·
·
·· · · · · · · ·
··
·

I

7-40

···
·

···
·

·

·

COUNTERS

HC92

HC90

Clock A

14

+2
Counter

12

Clock A

OA

14

+2
Counter

12

OA

I
11
08
Clock 8

Set 1

Oc

+5
Counter

~6

11

Clock 8

00

Counter

08
Oc
00

I

Set2

Reset 1

Reset 1

Reset 2

Reset 2

VC'C= Pin 5
GNO= Pin 10
No Connection= Pins 2.3,4, 13

VCC~

Pin 5
GNO= Pin 10
No Connection = Pins 4, 13

HC93

Clock A ---'-'4-'--_ _ _ _ _ _-Ch

Clock 8

-------+--01":>

~2

12

Counter

+8
Counter

11

I
Reset 1
Reset 2

\ 3

VCC= Pin 5
GNO=Pin '0
No Connection = Pins 4,6,7,13

7-41

COUNTERS

HC160 HC162
HC161 HC163

HC190

14

PO
Preset
Data
Inputs

13

P1

12
{

P2

01

001
02

BCD or
Binary
Outputs

BCD
Preset
Inputs

11

P3

:~
{

03

15
Clock

15

P2

3

OO}
01
BCD
02
Outputs

P3

03

10

12

Ripple
Carry
Out

Clock

Carry Out

14

Ripple Clock

Count Enable

CountUp/Down -"--------'
Reset

Load
VCC= Pin 16
GND= Pin 8

Load---~

Enable P 7
Caunt
Enables { Enable T _1_0_ _ _ _ _..J

Vcc=Pin 16
GND= Pin 8

HC191

HC192

r

15

4-Bit
Binary

Preset
Inputs

P1

P2

PO 15

32

1

OO}
01

10

02

P3

Clock

BCD
Preset
Inputs {

4-Bil
Binary
Outputs

Clock-Up

Carry Out

Outputs

Carry Output

Load

Count Enable
Count Up/Down

Resel---------'

Load

Vcc=Pin16
GND= Ptn 8

VCC=Ptn16
GND= Ptn 8

HC390

HC193

I

BCD

02

13 Borrow Output

Clock-Down

Ripple Clock

01

03
12

13

14

~

P3

03
12

32 00 }

P1 1
10
P2 9

4-Bit

PO 15
1

Binary

Pl

~ ~~}
6 02

Preset
P2 10
Inputs { P3 9

Clock A

1,15

4-Bit Binary
Outputs

703
12

Clock-Up

5,11 0B
Carry Output

Clock B

13 Borrow Output

Clock-Down

Reset

4,12

+5
Counter

2,14
VCC=Pln16
GND=Prn8

VCC= Pin 16
GND= Pin 8

7-42

6,10 Oc
7,9

°D

COUNTERS

HC393

HC4017
QO
Ql
Q2
3,11
4,10
Clock

1,13

Binary
Counter

5,9
6,8

Reset

Q3

10

Ql
Q2

Q4
Q5

Q3

Decade
Outputs

5 Q6

Q4

6

Q7

Q8

2,12
11
Vcc=Pin 14
GND=Pin 7

12

Q9

Carry Out

Reset .:.1::..5_ _---!
Vcc = Pin 16
GND= Pin 8

HC4020

HC4024
Ql
Q4

Clock

Q5

12

Q6

11

10
Q7

Ql
Q2
Q3

13
Q8

Clock

12

Q4

Q9

Q5

14
Ql0

Q6

15
Ql1

Q7

Q12
Q13

Reset-=-------l

Q14
Vcc= Pin 14
GND= Pin 7

11

No Connection = Pins 8, 10 and 13

Reset
VCC= Pin 16
GND= Pin 8

HC4060

HC4040

Out 1 Out2
Ql
Q2

Clock

Q3

Q4

Q4

05

10
Clock

Q5

06

Q6

07
14

Q7

13

13

Q8
12

15

Q8
09

Q9

010

QlO

012

Qll

013

14
15

014

012
11

Reset

Reset

12
VCC= Pin 16
GND= Pin 8

Vcc=Pin 16
GND= Pin 8

7-43

I

COUNTERS

HC4518

HC4520

Clock a

,
Enablea

O~ I
01a

BCD
Output
Word

02a

A

OOa
Clock a
01a
Enablea

02a

03a

A

03a

Reset a

Reset a

Clockb
12
" 00,
01b
Clock
Enable b

13
14

Aesetb

4- Bit Binary
Output
Word

02b

11

I

Clock b

BCD
Output
Word
B

12
13
14

03b

15
Aeset b 15

Vcc=Pin 16
GND= Pin 8

VCC = Pin 16
GND= Pin 8

I

7-44

00,
01b
02b
03b

I

Binary
Output
Word
B

4~Bit

MONOSTABLE
MULTIVIBRATORS

Functional
Equivalent

LSTIL

Device
Number
MC54/MC74

Device
54/74

Function

HC123

Dual Retriggerable Monostable Multivibrator

HC221

Dual Monostable Multivibrator

LS221

HC423

Dual Retriggerable Monostable Multivibrator

LS423

HC4538

Dual Precision Monostable Multivibrator (Retriggerable, Resettable)

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
or CDXXXX Compatibility
Pins

LS123

*4538,
*4528
*4538,
*4528
*4538
*4528
4538,
4528

* LS423

LS

16

LS

16

LS

16

CMOS

16

* Suggested alternative

Device

#Pins

HC123

HC221

HC423

HC4538

16

16

16

16

Dual Device
Precision Pulse Width
Retriggerable
Positive- Transition Trigger
Negative-Transition Trigger
Active-Low Trigger Enable
Active-High Trigger Enable
Active-Low Reset
Triggerable by Reset Pin
Inverting Output
Noninverting Output

I

7-45

MONOSTABLE MULTIVIBRATORS

HC123

HC221
Vee

ex

Vee

Rx

ex
15,7

15,7
13,5

Trigger/ {
Enable
Inputs

13,5

A
8

2, 10

Rx

4,12

Trigger/ {
Enable
Inputs

IT

Reset _3-'-.,_"_ _-,

A

8

2, 10

4,12

IT

Reset -,3"-.,_"_ _--'

Vee=Pin 16
GND= Pin 8

Vee= Pin 16
GND= Pin 8

HC423

HC4538
Vee

ex

Rx

Trigger {AI
Inputs

15,7

81

13,5
Trigger/
Enable

Vee

Inputs

4,12

IT
Trigger {A2 12
Inputs
82 11

Reset _3-'..,'_'_ _--'

Vee=Pin 16
GND=Pin I, Pin 8, Pin 15

Vee= Pin 16
GND= Pin 8

RX and

I

7-46

eX

are external components

13,--_ _ _--,
Reset 2.:.:

ARITHMETIC CIRCUITS

Device
Number
MC54/MC74

Functional
Equivalent
LSTTL
Device
54/74

Function

HC85
HC181
HC182
HC280
HC283

4-Bit Magnitude Comparator
4-Bit Arithmetic Logic Unit
Carry Lookahead Generator
9-Bit Odd/Even Parity Generator/Checker
4-Bit Binary Full Adder with Fast Carry

LS85
LS181
LS182
LS280
LS283,
LS83

HC688
HCT688

8-Bit Equality Comparator
8-Bit Equality Comparator with LSTTL-Compatible Inputs

LS688
LS688

Functional
Equivalent
CMOS
Device
MC1XXXX
Direct Pin
Number of
or CDXXXX Compatibility
Pins
*4585
4581
4582
*4531
4008

LS
LS/CMOS
LS/CMOS
LS
LS283

16
24
16
14
16

LS
LS

20
20

* Suggested alternative

I

7-47

ARITHMETIC CIRCUITS

HC85

HC181
AO 10
Al12
13

A2

15

A3

Data
Word
Inputs

5 A> Bout}
BO 9

6 A= Bout

Comparison

B111

7 A < Bout

Outputs

B214
B3 1

Cin

Cascading {
Inputs

Operation

::::.: ..;::'--_ _--'

Select

-

{:~:
4

Inputs

A