1983_Fairchild_Microprocessor_Products 1983 Fairchild Microprocessor Products
User Manual: 1983_Fairchild_Microprocessor_Products
Open the PDF directly: View PDF .
Page Count: 796
Download | ![]() |
Open PDF In Browser | View PDF |
January 1983 © 1983 Fairchild Camera and Instrument Corp. Microprocessor Division 3420 Central Expressway Santa Clara, CA 95051 I=AIRCHIL.D A Schlumberger Company The Advance Product Information designation on a Fairchild publication indicates that the product described is not characterized. The specifications presented are based on design goals or preliminary part evaluation and, as they are subject to change, are not guaranteed. Fairchild Microprocessor Division should be contacted for current information on these products. The information furnished in this publication is believed to be accurate and reliable. However, Fairchild cannot assume responsibility for its use, or for use of any circuitry described, other than circuitry entirely embodied in a Fairchild product. No license is granted or implied under any Fairchild patents or trademarks. Fairchild reserves the right to make changes in the circuitry or specifications presented in this publication at any time and without notice. iii iv Table of Contents Section 1 Introduction General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 1·3 Product Line................................................................................. 1·3 Data Book................................................................................ ... 1·3 Section 2 Ordering and Package Information General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2·3 Temperature Range ............................................................................ 2·3 Package Types and Outlines................................................................... 2·3 Section 3 F8 Microcomputer Family General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 3·3 Memory Interface Devices..................................................................... 3·3 Input/Output Devices......................................................................... 3-3 Bus Structure................................................................................ 3-3 Instruction Set. .............................................................................. 3·3 F3850 Central Processing Unit. ................................................................ 3·7 F3851 Program Storage Unit. ................................................................. 3·31 F3861 Peripheral Input/Output. ............................................................... 3·55 F3871 Peripheral Input/Output. ............................................................... 3-67 Section 4 Controller Family F387X Family................................................................................ 4·3 Part Numbers............................................................................ , ... 4·3 Descriptions .............................................................................•... 4·3 F3870 Single·Chip Microcomputer.............................................................. 4·5 F3870AlF3870B High·SpeedSingle·Chip Microcomputer........................................ 4·27 F38C70 Single-Chip Microcomputer........................................................... 4·29 F38E70 Single·Chip Microcomputer.........................................................•. 4·47 F38E70·21 Single·Chip Microcomputer......................................................... 4-67 F38721F38L72 Single·Chip Microcomputer..................................................... 4·71 v Table of Contents Section 5 F6800 Microprocessor Family General ...................................................................................... 5-3 Instruction Set. .............................................................................. 5-5 F6800/F68AOO/F68BOO 8-Bit Microprocessing Unit. ............................................. 5-11 F6801/F6803 Single-Chip Microcomputer...................................................... 5-51 F6802/F6808/F6882 Microprocessor With Clock and RAM ........................................ 5-57 F6809/F68A09/F68B09 Central Processing Unit. ................................................ 5-81 F6809E/F68A09E/F68B09E Central Processing Unit. ............................................ 5-83 F6810/F68A10/F68B10 128 x 8-Bit Static RAM ................................................. 5-87 F6820 Peripheral Interface Adapter............................................................ 5-93 F6821/F68A21/F68B21 Peripheral Interface Adapter............................................ 5-107 F6840/F68A40/F68B40 Programmable Timer.................................................. 5-119 F6844 Direct Memory Access Controller...................................................... 5-135 F6845/F6845A CRT Controller................................................................ 5-155 F6846 ROM-I/O-Timer....................................................................... 5-179 F6847 Video Display Generator.............................................................. 5-199 F6850/F68A50/F68B50 Asynchronous Communications Interface Adapter........................ 5-211 F6852/F68A52/F68B52 Synchronous Serial Data Adapter....................................... 5-223 F6854/F68A54/F68B54 Advanced Data Link Controller.......................................... 5-243 F6856 Synchronous Protocol Communications Controller...................................... 5-267 F38456/F68456 Multiple Protocol Communications Controller................................... 5-297 F68488 General Purpose Interface Adapter.................................................... 5-301 Section 6 16-Bit 13 l Bipolar Microprocessor Family GeneraL ..................................................................................... 6-3 Instruction Set. .............................................................................. 6-3 F9414 4-Chip Data Encryption Set. ............................................................ 6-13 F9423 FIFO Buffer Memory................................................................... 6-27 F9443 Floating Point Processor............................................................... 6-47 F9444 Memory Management and Protection Unit. .............................................. 6-49 F9445 16-Bit Bipolar Microprocessor........................•................................. 6-51 F9446 Dynamic Memory Controller............................................................ 6-79 F9447 1/0 Bus Controller..................................................................... 6-81 F9448 Programmable Multiport Interface....................................................... 6-89 F9449 Multiple Data Channel Controller........................................................ 6-95 F9450 Single-Chip Microprocessor........................................................... 6-109 F9451 Memory Management Unit. ........................................................... 6-111 F9452 Block Protect RAM ................................................................... 6-113 F9470 Console Controller................................................................... 6-115 vi Table of Contents Section 7 F16000 Microprocessor Family General. ..................................................................................... 7-3 Addressing .................................................................................. 7-3 Virtual Memory................................................................................ 7-3 Symmetry.................................................................................... 7-3 High-Level Language Support.................................................................. 7-4 Modularity ................................................................................... 7-4 Slave Processors............................................................................. 7-4 System Protection ............................................................................ 7-4 Future Expansion ............................................................................. 7-4 F16032 High Performance Central Processing Unit. .............................................. 7-7 F16081 Floating Point Unit. .................................................................. 7-13 F16082 Memory Management Unit. ........................................................... 7-15 F16105 Very Intelligent Peripheral Controller. .................................................. 7-17 F16201 Timing Control Unit. ............................................... " ................. 7-19 F16202 Interrupt Control Unit. ................................................................ 7-21 F16203 Channel Controller................................................................... 7-23 F16204 Bus Arbiter.......................................................................... 7-25 F16413 CRT Controller....................................................................... 7-27 F16425 Packet Switching Frame Level Controller............................................... 7·31 F16456 Multiple Protocol Communications Controller........................................... 7-35 F16488 GPIB Controller...................................................................... 7·39 F16802 Local Area Network Controller......................................................... 7-41 Section 8 ROM Products F3532/F68332/F3533 32K ROM ................................................................. 8-5 F3564 64K ROM ............................................................................. 8-11 F3565 64K ROM ............................................................................. 8-13 F3566 64K ROM ............................................................................. 8-15 F3568 64K ROM ............................................................................. 8-17 F3569 64K ROM ............................................................................. 8-19 F3570 64K ROM ............................................................................. 8·21 F35316/F68316 16K ROM ..................................................................... 8-23 Section 9 Development Systems and Software EMUTRAC ................................................................................... 9-5 F38E70 Programming Board ................................................................... 9-9 Formulator................................................................................... 9·11 FS·I. . . . . . . . . . . . . . . . . . . . . . . . . .. . ........................................................... 9-13 PEp·38 ................ , .................................................................... 9·19 PEP-45 ..................................................................................... 9-21 PEP-68 ..................................................................................... 9-23 Software .................................................................................... 9-31 vii Table of Contents Section 10 Applications Matrix Printer..................................•............................................ 10-5 PLL System.......... '.' .................................................................... 10-19 Solar Controller............................................................................ 10-31 F9414 Data Encryption ........... , ...........................................................10·33 CCO 3000 Camera...•...................................................................... 10-45 Section 11 'Resource and Training Centers Section 12 Sales Offices vIIi INTRODUCTION r-;;-\2 IORDERING AND PACKAGE ~ INFORMATION IrulF8 101 MICROCOMPUTER FAMILY CONTROLLER FAMILY 1~IF6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY [!] I 1 ROM PRODUCTS I[!QJ APPLICAnONS 1 I[I!] I [!!J I RESOURCE AND TRAINING CENTERSI 1 SALES OFFICES A Schlumberger Company Section 1 Introduction General capabilities by interconnection with external devices. A microprocessor is essentially an integrated circuit logic replacement device that performs the functions of the central processing unit (CPU) of a computer system. The overall task of the microprocessor is to receive digital data and store it for later processing, to perform arithmetic and logic operations on the data in accordance with instructions contained in a stored program, and to present the results of these operations to the user through some form of output mechanism. The Fairchild Microprocessor Division product line encompasses microprocessors and their support devices, singleand multi-chip microcomputers, and systems to emulate and develop hardware and software. FAIRCHILD Product Line The Microprocessor Division product line includes a wide range of devices to meet the specific needs of four broad application areas: The program is a definable and non-varying specification for any given application. It normally resides in a read only memory (ROM) or program storage unit (PSU). Variable data that is to be operated upon by the microprocessor is normally stored in a random access memory (RAM) or other transient data storage element. Although architectural details vary depending upon manufacturer and technology, a typical microprocessor comprises the following functional areas: 1. Instruction decoding to interpret program instructions. 2. An arithmetic and logic unit (ALU) to perform binary addition, subtraction, etc., and Boolean logic operations. 3. Registers to temporarily store frequently manipulated data. 4. Address buffers to provide the next program instruction address. 5. InpuUoutput (I/O) buffers to read information into or write information out of the microprocessor. 1. 8-bit microprocessors 2. 8-bit single-chip microcomputers 3. 16-bit microprocessors 4. Development aids Within these areas, the Division offers a blend of innovative, state-of-the-art devices and proven, wellestablished devices. For example, the members of the F6800 family, and of the F8 family, can be configured to create a variety of 8-bit computer systems that have a wide range of capabilities. Similarly, the F9445 family components can create extremely fast 16-bit computer systems that are exceptionally resistant to harsh environments, and the F16000 family members can be used in configurations that are ideally suited to communications applications. (The F16000 has a 16-bit I/O structure and a 32-bit internal architecture.) To the user, the Microprocessor Division line represents a single source of cost-effective solutions to the full spectrum of application problems. Data Book Microprocessors are generally used in conjunction with support devices that perform timing, program and transient data memory, I/O signal interface, and other functions. A wide range of configurations is possible with a microprocessor and its related devices; each configuration represents a full microcomputer system. This data book presents a complete technical description of the Fairchild Microprocessor Division product line. Where devices have been characterized, specific information is presented in the form of data sheets. Information on partially characterized devices, and on devices currently under development, is in the form of advance product information sheets. More complete data can be obtained from the Product Marketing Department. A single-chip microcomputer incorporates CPU, memory, I/O, control, and other functions into one integrated circuit. Typically, such devices have facilities for enhancement of 1-3 II Introduction 1-4 [!J 1 1INTRODUCTION 101F8 MICROCOMPUTER FAMILY ICTIICONTROLLER FAMILY 1 0 1 F6800 MICROPROCESSOR FAMILY J 101F16000 MICROPROCESSOR FAMILY ~ IROM PRODUCTS 1 InIg I DEVELOPMENT SYSTEMS AND L!J SOFTWARE I[!QJ I APPLICAnONS I[!TIIRESOURCE AND TRAINING CENTERSI I@] I SALES OFFICES Section 2 Ordering and Packaging Information F=AIRCHIL.D r.. Schlumberger Company General Package Types and Outlines Specific ordering codes, as well as the temperature ranges and package types available, are included in each data sheet of sections 3 through 8. The basic package type of a device, such as dual-in-line • plastic or dual-in-line ceramic, is indicated by the ordering code for that device. To accommodate various die sizes and pin numbers, different package forms exist within each package type. Temperature Range The package forms indicated by device ordering codes are illustrated in the following detailed outline drawings. The basic temperature ranges typically available are: C L M Commercial (O°C to 7S0C) Automotive (- 40°C to 8S°C) Military (- SsoC to 12S0C) Selected products are optionally available in 44- and 68·pin lead less chip carriers. Contact your local sales office for more information. 24-Pin Ceramic Dual·ln-Line r----112 1.290132.7661----1 11\1\1\/1.235131.3691 \1\1\1\ 1 .570 (14.478) .515IL4"~~~~~~~.,g..J ---1 L .100 12.5401 .040 (1.016) .190 14.8261 .lt6~1;:;;;;;:;;::;:;;;;:;;;;;:;:;::;:;J II .03710.9401 .02010.5081 .027 10.686dl--.016 10.4061 STANDOFF WIDTH NOTES: All dimensions are in inches bold and millimeters (parentheses). Pin material is nickel gold·plated kovar. Cap is kovar. Base is ceramic. Package weight is 6.5 grams. 2·3 Ordering and Packaging Information 24-Pin Plastic DIP r--1'2 1.260 (32.004) ----1 I 1\1\1\1 , .240 (31.496) ,1\1\1\ I .055 R (1.40) .050 (1.27) .560 (14.224) .540 (13.716) Ll¥ii=ii~=rr=n=;;=ir'ii=i~ L .085 (2.16) .070 (1.78) .050 NOM (1.27) - .165(4.19) + .150 (3.81 r) II - ;;:;:;;:;:;;;:;:;;:~g.020 (.508) 1= MIN --L SEATING ~ ----'--PLANE .037(.940) .027 (.686) STANDOFF WIDTH II .020 (.508) -II- .016(.406) NOTES: All dimensions are in inches bold and millimeters (parentheses). Pins are tin·plated kovar. Package material is plastic. 28·Pin Ceramic Dual·ln·Line __ . 110 1 .090 (2.79) (2.271 __ .037(0.94) .027 (0.68> STANDOFF WIDTH _II__ ~ .016 !O.41) NOTES: All dimensions are in inches bold and millimeters (parentheses). Pin material is nickel gold·plated kovar. Cap is kovar. Base is ceramic. Package weight is 6.5 grams. 2·4 Ordering and Packaging Information 28·Pln Plastic Dual·ln·Llne ~----.'4.5137.2'1 MAX-~ • =E[::::::::::r-"""=-"~ r. r. 1 Iw ---1 .050TVP ~ 1--- 11.271 y I -, !--.07511.91ITVP 066 !1 40) E -~::,~'" '60(~'06)MAX 0011 •.24Ij NOM :045 (1:141-'1 ~-SEATING -PLANe .100 12.541.--' TVP -I 1'_ 3.301 - - - -;~82",1 .011 (0.28) III h :g:::l Ih ---"i :g~~ ..........- .009 (O.23) +,30 .115(2.92) NOM I ---------1 .018 (0.46) NOM NOTES: All dimensions are In inches bold and millimeters (parentheses). Pins are tin.plated kovar. Package material Is plastic. 40·Pin Ceramic Dual·ln·Line .02' R .580 MAX 1.6354' (14.73) I .060 ~ 1.524) .025 10.635) ~H=H=~~~~~~~~~~~~~~~~~=d~SEATING iPLANE (19.0501 I I~ .750MAX -j .200 (5.080) .125 (2.540) NOTES: All dimensions are in inches bold and millimeters (parentheses). Pin material is nickel gold'plated kovar. Cap is kovar. Base is ceramic. Package weight is 6.5 grams. 2·5 Ordering and Packaging Information 4O-Pin Plastic Dual-In-Line 1 • . 2.0SO (52.070) 'I ~ "f]:::::::::::::::::::r ~: J 1- .060 (1.524) I-- .040 (1.016) .155 (3.94) .070 (1.778) iWNUWllWUWUWHM., .140(3.56) .125(3.18) J I~ " L·ll0(2.794)TYP , .090 (2.286) . j .018 _ (0.457) 1.590 (14.99lj Ir· 610 (15.49) 1 4°.010 :::1.lln9 Plane ~ (0.S08) M.~~5 (0.254~) .680 MAX (17.27) REF. (1.905) TYP. NOTES: All dimensions are In inches bold and millimeters (parentheses). Pins are tin·plated kovar. Package material Is plastic. 4O-Pin Ceramic Dual-In-Line (EPROM) 025(06351 .110 (14 9861 R ."'.(143511 1152~} 410 I .. ge~:: ~~::-l r- 021921 .010(15241 .04011 0161 1'0(4064) ,,0127941 __ _ _ r':~::::::~' " - .----:::::!-L ::.!4~. .'7Si-4·"~ J ~ ,1"(3,751 ! 110c27941 1.010122861 .J' (127001 .. 80 - (121921 0",0"" I~ ::0:::1 ::(~:2,9~51 -II 041(1 1431 --04r:~'016J 02010508,1- - MAX 011104(6) TVP NOTES: All dimensions are In inches bold and millimeters (parentheses). Pin material Is nickel gold-plated kovar. Cap Is kovar. Base is ceramic. Package weight Is 6.5 grams. 2:6 Ordering and Packaging Information 48 Lead Sidebrazed Package .610 ± .010 (15.49 ± 0.25) .030(0.76)R TYP 25 0.50R (1.27) MAX. NOTCH .550 ± I.003 (13.97 ±l sa I • 1 008:;~90~~~~05) j 24 1+·---------(~04~~~~~~)----------1 .165(4.19)MAX .125(3.12)MIN _.040(1.02)TYP I NOTES: 1. Lead Material Is Nickel Gold Plated Kovar or Alloy 42 2. Cap Is Kovar or Alloy 42 3. Base Is Ceramic 4. Cavity Size Is .400 x 0400 5. Package Weight Is 7.7 Grams 54· Pin Ceramic Dual·ln·Line 1 .588 (14.935) .582 (14.783) I 1------.510(12.954)~ .025 (.635) R (REF) 1---------------1.63~R~~402)--------------~-I1 I------------------~:::~::~~:~:-----------------I CAP (REF) AI,O, WINDOW FRAME A1203BASE .600 (15.240) -BENDLlNE- .011 (.279) .009(.229) 11_. -'1 018 (.457) TYP __ .050 (1.270) TYP NOTES: All dimensions are in inches bold and millimeters (parentheses). Pin material is nickel gold-plated kovar. Cap is kovar. Base is ceramic. Package weight is 6.5 grams. 2-7 ~.655 (16.637)----1 I~- -.615(15.621) -I Ordering and Packaging Information 68 Lead Ceramic Leaded Chip Carrier 1 - - - - - - - - - - - 2.000 REf'----------~ 1-----.98 REF·-----J .148 .145 LEAD NO.1 .098 TYP L i .120 .100 , c LID(REF) r ---; --,-' ! i .050 REF NOTES: 1. Lead Material Is Alloy 42 or Kovar Solder Coated 2. Lid Is Kovar or Alloy 42 3. Base & Top Are Ceramic 4. Cavity Size Is .400" x .400" 5. Package Weight Is 7.5 Grams 6. Lead Forming Is Optional 2-8 [!] 1 I INTRODUCTION r;;l2 IORDERING AND ~ INFORMATION PACKAGE F8 MICROCOMPUTER FAMILY CTI 1 I CONTROLLER FAMILY 1~IF6800 MICROPROCESSOR FAMILY 101 F16000 MICROPROCESSOR FAMILY ~I ROM PRODUCTS 1 ~9 I DEVELOPMENT SYSTEMS AND L!.J SOFTWARE [!QJ 1 1 I[!IJ APPLICATIONS I RESOURCE AND TRAINING CENTERS I ~ I SALES OFFICES 1 Section 3 Fa Microcomputer Family FAIRCHILD A Schlumberger Company General Input/Output Devices The distribution of logic among the various elements of a microcomputer system is one of the most variable features of such systems. The traditional division of logic corresponds to the requirements of a computer; e.g., one device serving as CPU, one as memory, and one as I/O. In the F8 microcomputer family, logic is implemented in devices in terms of application complexity rather than in terms of computer function. Thus, for example, two F8 devices implement all of the basic functions of a small microcomputer. Applications that require additional I/O and interrupt capabilities but do not require the PSU storage capacity can make use of the F3861 Peripheral Input/Output (PIO) device. The PIO, which also contains interrupt logic and a programmable timer, interprets CPU control signals to drive • two 8-bit I/O ports. Bus Structure The F8 microcomputer components are interconnected by means of a system bus structure that is composed of the following elements: To accomplish this, the deSign of the F8 family includes a number of non-traditional function assignment features: 1. A small amount of RAM is implemented within the CPU as a scratchpad memory. 2. Memory addressing logic is implemented in the memory devices rather than in the CPU. 3. The I/O ports are implemented in the CPU and memory devices rather than in discrete I/O devices. 1. Eight data bus lines (DBo - DB7) 2. Five control lines (ROMCo - ROMC 4) 3. Two clock lines (, WRITE) 4. Three interrupt lines (PRI IN, PRI OUT, INT REO) Instruction Set Every F8 configuration must contain an F3850 CPU, at least one F3851 Program Storage Unit (PSU) or memory interface device, and standard ROM or PROM (see figure 3-1). The memory-oriented devices may be used Singly or together in the same system; when necessary, multiple units of the same type may be used. For example, an F3850 and two F3851s may comprise a system requiring 2K words of ROM, 64 bytes of RAM, and six I/O ports. The instruction set of a microprocessor or microcomputer is the software tool used to shape the device or system for a particular application. The F8 instruction set is divided into four functional groups. 1. Input/Output 2. Arithmetic/Logical Memory Interface Devices 3. Address Register Control When required by the application, the F3851 PSU may be replaced by an F3853 Static Memory Interface (SMI). Both of these devices interpret control signals output by the F3850 and generate the standard address and control signals required by off-the-shelf dynamic and static memory devices. 4. Indirect Scratchpad Address Register (ISAR) and Status Control The F8 instruction set is presented in table 3-1. 3-3 Fa Microcomputer Family Table 3-1 Fa Instruction Set Instruction Description ADC AI AM AMD AS ASD Instruction Description Add Accumulator to Data Counter Add Immediate to Accumulator Add (Binary) Memory to Accumulator Add (Decimal) Memory to Accumulator Add (Binary) Scratchpad Memory to Accumulator Add (Decimal) Scratchpad Memory to Accumulator JMP Branch Immediate LI LIS LlSL LlSU LM LNK LR Load Immediate Load Immediate Short Load Lower Octal Digit oflSAR Load Upper Octal Digit of ISAR Load Accumulator from Memory Link Carry to Accumulator Load Register BC BF BM BNC BNO BNZ BP BR BR7 BT BZ Branch on Carry Branch on false Branch on Negative Branch if No Carry Branch if No Overflow Branch if Not Zero Branch if Positive Unconditional Branch Branch on ISAR Branch on True Branch on Zero NI NM NOP NS AND Immediate Logical AND from Memory No Operation Logical AND from Scratchpad Memory 01 OM OUT OUTS OR Immediate Logical OR from Memory Output Long Address Output Short Address CI CLR Compare Immediate Clear Accumulator PI PK COM Complement POP Call to Subroutine Immediate Call to Subroutine Direct and Return from Subroutine Direct Return from Subroutine DCI DI DS Load Data Counter Immediate Disable Interrupt Dessement Scratch pad Memory Content SL SR ST Shift Left Shift Right Store to Memory EI Enable Interrupt IN INC INS Input Long Address Increment Accumulator Input Short Address XDC XI XM XS Exchange Data Counters Ekxclusive-OR Immediate Exclusive-OR from Memory Exclusive-OR from Scratch pad Memory 3-4 F8 Microcomputer Family Descriptions Following is data that describes the members of the FB microcomputer system family. F8 FAMILY ORGANIZATION II F3850 CENTRAL PROCESSING UNIT F3851 PROGRAM STORAGE UNIT F3871 PERIPHERAL INPUT/OUTPUT F3853 STATIC MEMORY INTERFACE F3856 PROGRAM STORAGE UNIT F3861 PERIPHERAL INPUT/OUTPUT 3·5 Fa Microcomputer Family 3·6 F3850 I=AIRCHILO Central Processing Unit (CPU) A Schlumberger Company Microprocessor Product Description The Fairchild F3850 is the Central Processing Unit (CPU) for the F8 8-Bit Microprocessor family. The F3850 contains more than 70 instructions in its instruction set and operates on 8-bit units of information. • • • • • 8-Blt Arithmetic and Logic Unit, Supporting Both Binary and Decimal Arithmetic • Interrupt Control Logic • Power-on Reset Logic • Clock Generation Logic Within the CPU Chip. With Crystal and External Clock Generation • More Than 70 Instructions • +5 V and +12 V Power Supplies • Low Power Dissipation (l\'pically Less Than 330 mW) N-channellsoplanar MOS Technology 2 IJ.s Cycle Time 64-Byte Scratchpad on the CPU Chip "TINo Bidirectional, 8-Bit 1/0 Ports, with Output Latches Connection Diagram Signal Functions CLOCK LINES 1/0 PORT LINES -- -------------------- ¢ WRITE XTLX INTREQ ICB ROMCo XTLY ROMe, XTLZ ROMe2 ROMe3 1/000 1/001 EXTREs 1/002 1/003 1/0 04 liDos 1/006 DBo DB, DB, DB, 1/007 DB, 1/010 DBs 1/0 11 1/012 DB, DB, 1/0 13 1/0 14 1/°15 1/°16 1/017 Vss Voo VGG =)-~ --+- --- ----- XTLZ ¢ - - - } INTERRUPT --+-LINES LINES WRITE 39 XTLZ Voo 38 XTLY VGG 37 EXTREs 1/0 03 36 1/004 DB, 3S DB, 1/0 13 34 1/014 32 DB, 31 1/0.. 1/012 RESET 1/0 15 DB, --------- )~'" DATA BUS LINES ...- 1/002 1. 1/001 11 liD" DB, 12 DB, 1/011 13 1/0 10 l' DBo 15 28 26 DB, 16 25 11007 17 2' Vss 1/000 ROMeo ROMe, 18 INTREQ ROMe2 19 ICB ROMe3 2. ROMC 4 (Top View) 3-7 1/0 16 i7017 • F3850 Device Organization The contents of the instruction register are decoded by control unit logic, which generates signals to enable specific sequences of logic operations within the CPU chip. In response to the contents of the instruction register, the control unit also generates five signals, ROMCothrough ROMC4 , that control operations throughout the microprocessor system. The logical organization and pins for the F3850 CPU are illustrated in Figure 1. Arithmetic and Logic Un.lt The arithmetic and logic unit (ALU) provides all data manipulating logic for the F3850. It contains logic that operates on a single 8-bit source data word or combines two 8-bit words of source data to generate a single 8-bit result. Additional information is reported in status flags, where appropriate. Accumulator The accumulator is a general-purpose 8-bit data register, which is the most common data source and results destination fortheALU. Operations performed on two units of source data include addition, compare, and the Boolean operations (AND, OR, Exclusive-OR). The two sources are input to the ALU through the left and right multiplexer buses; the result is placed on the result bus. Scratchpad and ISAR The scratchpad provides 64 8-bit registers that may be used as general-purpose RAM memory (see Figure 2). Operations performed on a single 8-bit unit of source data include complement, increment, decrement, shift right, shift left, and clear. The source is input to the ALU through either the left or right multiplexer bus; the result is placed on the result bus. Figure 2 F8 Programming Model . - - BITNO. __ __ ______~I ~ ~~~~ ~ Instruction Register The CPU contains registers for storing various types of data. The instruction register holds an 8-bit code, which defines the operations to be performed by the CPU. HI NOT INCREMENTED OR DECREMENTED ISAR LO L • .-J INCREMENTED AND DECREMENTED Figure 1 F3850 CPU Logical Organization RESULTS BUS 1 ~ ~I ACCUMULATOR ~ J-- ~ r- ALU I- ... :J ~ STATUS(W) r- 64 x 8-BIT SCRATCHPAD REGISTERS a: w t--ffi ..... )( w ~ ~ ::> :; ~ I :t INSTRUCTION I----- "a: - i 1-..... ISAR i~ I 111 INTERNAL OAT A BUS ~ I r~~'! I 'j'''-j t t t t I - 1/°07 1/008 1- ::> :; -I .... I - DBo l- f---- ..... I CONTROL UNIT LOGIC ~ ROMC O DB, 3-8 ~ ROMC. INTERRUPT LOGIC i ! INT REO ICB POWER ON DETECT Exl ES CLOCK CIRCUITS J X LZ 11v LL XTLX F3850 The indirect scratchpad address register (ISAR) is a 6-bit register used to address the 64 scratchpad registers, i,e" the ISAR is assumed to hold the address of the scratchpad byte that is to be referenced, The first 16 scratchpad bytes can be identified either by instructions without using the ISAR or referenced through the ISAR. The remaining scratchpad bytes are referenced through the ISAR; The ISAR may be visualized as holding two octal digits, HI and LO, as illustrated in Figure 3, This division of the ISAR is important, since a number of instructions increment or decrement the con- Figure 3 II ISAR Register ACCUMULATOR LR r, A 0 ~--~~~--~~ CPU GENERAL REGISTERS ISAR 11~2 REGISTER ADDRESS POINTER LRJ,W J LRW,J 10 A H B H 11 C K 12 D K 13 PK,PI ZERO----' CARRY _ _ _ _ _...J SIGN _ _ _ _ _ _..J 15 0 ,. 0 15 10 16 3F 63 DATA COUNTER LRDC,H LRH,DC LRDC,Q LRQ,DC MEMORY ADDRESS POINTER 3-9 POP 15 LRP,K LRK,P STACK POINTER F3850 tents of the ISAR, when referencing scratchpad bytes through the ISAR. This makes it easy to reference a buffer consisting of contiguous scratchpad bytes. However, only the low-order octal digit (LO) is incremented or decremented; thus ISAR is incremented from 0'27'* to 0'20', not to 0'30'. Similarly, ISAR is decremented from 0'20' to 0'27', not to 0'17'. This feature of the ISAR is very useful in that it greatly simplifies many program sequences. and program memory address registers that are maintained on the F3851, F3852, and F3853 chips. Figure 4 identifies the data transfers that can be implemented by executing a single F8 instruction. For example, the illustration: W register of F3850 CPU - J means that a single instruction can move the contents of the W (or status) register to scratch pad register 9 (J register). Another single instruction can move data in the opposite direction. Selected scratchpad registers are reserved for direct communication with other registers within the F8 system, as illustrated in Figure 4. Status Registers The status (W) register holds five status flags. Table 1 summarizes the way each flag is used. Note that status flags are selectively modified following execution of different instructions. See the "Instruction Execution" section for a discussion of the way individual F8 instructions modify status flags. Scratchpad register 9 (0'11 ') is used as temporary storage for the CPU status register (W register). Scratchpad registers 10 through 15 (0'12' through 0'17') communicate directly with data *The notation O'nn' represents an octal number. Figure 4 F3850 CPU Scratchpad Registers SCRATCHP4D BYTE ADDRESS SCRATCHPAD DECIMAL OCTAL § W REGISTER OF F3850 CPU _ DC REGISTER OFF3851 PSU. !-! F3852 OMI AND F3853 SMI ~ PCOORPC1 (STACK) REGISTER OFF3851 1. PSU F3852 DMI AND F3853 SMI \ DC OR PCO REGISTER OF F3851 PSU F3852 DMI AND F3853 SMI H ( HU HL ~l l - 11 J KU (KL (QU QL j 3-10 10 12 11 13 12 14 ' 13 15 14 16 15 17 16 20 58 72 59 73 60 74 61 75 62 76 63 77 F3850 Overflow (0 Blt)-When the results of an ALU operation are being interpreted as a signed binary number, since the high-order bit (bit 7) represents the sign of the number, some method must be provided for indicating a carry out of the highest numeric bit (bit 6). This is done using the 0 bit. After arithmetic operations, the 0 bit is set to the Exclusive-OR of a carry out of bits 6 and 7. The simplification of signed binary arithmetic is described in the F8 and F3870 Guide to Programming; examples are presented below: ~BITNO. I C B o z I I I C STATUS REGISTER (W) LSIGN ~ L CARRY ZERO OVERFLOW Accumulator contents: value added: Sum: INTERRUPT MASTER ENABLE 76543210 10110011 01110001 11100100 Bit Number Sign (S Blt)-When the results of an ALU operation are being interpreted as a signed binary number, the high-order bit (bit 7) represents the sign of the number. At the conclusion of instructions that may modify the accumulator bit 7, the S bit is set to the complement of the accumulator bit 7. There is a carry out of bit 6 and a carry out of bit 7, so the 0 bit is reset to 0 (1 EEl 1 = 0). The C bit is set to 1. Table 1 Summary of Status Bits There is a carry out of bit 6, but no carry out of bit 7; the 0 bit is set to 1 (1 EEl 0 = 1). The C bitis reset to O. Accumulator contents: value added: Sum: OVERFLOW = CARRY7 + CARRY6 ZERO = ALU 7 ALU6 ALU5 ALU4 ALU3 ALU2 ALU 1 ALUo CARRY = CARRY7 SIGN = ALU 7 Control Unit The control unit decodes the contents of the instruction register and generates two sets of control signals. These signals are transparent to the user. Five control signals (ROMCothrough ROMC4 ) are output by the control unit to identify operations that other chips of the Fa family must perform. These signals are described in the "ROMC Signals" section. Bit Number 01100101 Accumulator contents: value added: 01110110 Sum: 0 1 1 0 1 1 0 1 1 There is no carry, so C is reset to O. C 7 6 5 4 3 2 10 Accumulator contents: 1 00 1 1 1 0 1 value added: 11010001 Sum: 1 0 1 1 0 1 1 1 0 Bit Number Interrupts (ICB Blt)-Externallogic can alter program execution sequence within the CPU by interrupting ongoing operations. However, interrupts are allowed only when the ICB is set to 1; interrupts are disallowed when the ICB is reset to O. Carry (C Blt)-The C bit may be visualized as an extension of an 8-bit data unit; i.e., the ninth of a 9-bit data unit. When two bytes are added, and the sum is greater than 255, then the carry out of the high-order bit appears in the C bit; e.g.: C 7 P 5432 1 0 - 765432 10 01100111 00100100 10001011 Interrupt Logic This logic handles the interrupt requests. For a complete description refer to the "Interrupt" discussion within the "Instruction Execution" section. Bit Number Power on Detect When the External Reset (EXT RES) signal is pulled low and then returned high, or when power is turned on, the power on detect logic sets the PC registers to 0, causing a program originating at memory location 0 to be executed. Also, the interrupt control status bit is set low, inhibiting interrupt acknowledgement. The system is locked in an idle state while EXT RES is held low. fhere is a carry, so C is set to 1. Zero (Z bit)-The Z bit is set whenever an arithmetic or logical operation generates a zero result. The Z bit is reset to 0 when an arithmetic or logical operation could have generated a zero result but did not. 3-11 II F3850 Signal Descriptions The F3850 input and output signals are described in Table 2. "nIble 2 F3850 Signal Descriptions Mnemonic Description Name Pin No. Clock tf> 1 2 Clock Write These output signals drive all other devices in the F8 family. WRITE XTLX 39 Crystal Clock The XTLX output Signal is used when generating the system clock in the crystal mode (with the XTLY and XTLZ signals). XTLY 38 External Clock The XTLY input signal is used with the XTLX signal when generating the system clock in the crystal mode, and is also used for operating in the external clock mode. XTLZ 40 Crystal Clock This input signal must be grounded for crystal clock or external clock. These bidirectional signals are ports through which the CPU communicates with logic external to the microprocessor system. VOPort 1/000-1/0 07 16,11,10,5,36,31,30,25 1/0 Port Zero 1/010-1/0 17 14, 13, 8, 7,34,33,28,27 I/O Port One Intern.lpt ICB 22 Interrupt Control Bit The ICB output signal indicates whether or not the CPU is currently ignoring the INT REO line. If the ICB signal is low, the CPU responds to interrupt requests; if the ICB signal is high, the CPU ignores interrupt requests. INTREO 23 Interrupt Request This input line is used to signal the CPU that an interrupt is being requested.The F3851 PSU, F3861 and F3871 PIOs, and F3853 SMI devices contain logic to initiate interrupt requests by pulling the INT REO signal low. The CPU acknowledges interrupt requests by outputting the appropriate ROMC signals. Control The ROMC output signals control logic operations for other devices in the F8 family. These signals assume a state early in each machine cycle and hold that state for the duration of the cycle. Refer to the "Instruction Execution" section for further discussion and a summary table of the ROMC interpretation by CPU logic. Control ROMCoROMC4 17-21 3-12 F3850 Table 2 F3850 Signal Descriptions (Continued) Mnemonic Pin No. Name Description :r7 External Reset This input signal can be used to externaliy reset the system. When the line is pulled low, a program originating at memory address 0 is executed. Data Bus These eight bidirectional signals are data bus lines that link the F3850 CPU with all other F8 devices in the system. They are multiplexed lines used to transfer data and addresses. Power Supply Power Supply Ground Nominal +5Vdc Nominal +12 Vdc Common power and signal return Reset EXT RES Data Bus DBo-DB7 15, 12, 9, 6, 35, 32, 29, 26 Power VDD VGG Vss 3 4 24 used in this mode of clock generation are summarized as: Clock Circuits A unique feature of the F8 microprocessor is that clock logic forms an integral part of the F3850 CPU chip. The F3850 CPU offers two methods of generating a system clock: crystal mode and external mode. Frequency: 1 to 2 MHz, typical AT cut Mode of Oscillation: Fundamental Operating Temp. Range: O°C to +70°C Drive Level: 10 mW Frequency Tolerance: fa = 1 or 2 MHz±1000 ppm @ CL =20pF Crystal Mode Figure 5 shows the pin configuration for clock generation using the crystal mode. A crystal in the 1- to 2-MHz range is placed across the XTLX and XTLY pins, along with two capacitors (C1 and C2), to provide a highly precise clock frequency. The external crystal (and capacitors) together with internal circuitry combine to form a parallel resonant crystal oscillator. Capacitors C1 and C2 should be approximately 15 pF. The characteristics of the crystal External Mode For F8 applications where synchronization with an external system clock is desired, the external clock mode may be used as shown in Figure 6. For example, a slave F3850 CPU may receive its timing from a master F3850 CPU by having the master c/> output drive the slave XTLY input. Figure 5 Crystal Mode Clock Generation Figure 6 External Mode Clock Generation Vss Vss XTLZ C, XTLY XTLY T 1 T F3850 CPU F3850 CPU XTLX XTLX C, EXTERNAL CLOCK Vss 3·13 • F3850 ROMC Signals Figure 7 illustrates the timing characteristics of the clock signal needed for external mode clock generation and the timing characteristics of the cf> and WRITE signals generated by the CPU. The CPU logic uses the five ROMC signals to identify operations that devices must perform during any instruction cycle. The 32 possible ROMC states are described in the "ROMC Signal Functions" section. The state of the ROMC signals and the operation they identify last through one instruction cycle. Timing Signal Outputs In response to the three clock mode inputs, the F385a CPU outputs two timing signals: clock signal cf> and instruction cycle control signal WRITE. As shown in Figure 7, cf> is the signal used to synchronize the entire microprocessor system. The WRITE signal defines the duration of each machine cycle. Refer to the "Instruction Execution" section. Parameters and specifications for the timing signals are detailed in the "Timing Characteristics" section. The general distribution of logic among devices of the F8 family and general data movements associated with instruction execution are given in the F8 and F3870 Guide to Programming. Memory addressing logic is located on the F3851 Program Storage Unit (PSU), the F3852 Dynamic Memory Interface (DMI), and the F3853 Static Memory Interface (SMI) devices. Each of these devices contains registers to address programs (PCa and PC1) or data (DCa or DC1). The F3851 PSU does not have a DC1 register. Instruction Execution The F385a CPU logic controls instruction execution through the cf> and WRITE timing signals, plus the five ROMC control lines. Devices external to the F385a CPU must respond directly to these signals. Unlike other microprocessors, the F385a CPU does not output addresses at the start of memory access sequences; a simple command to access the memory location addressed by pca or DCa is suffiCient, since the device receiving the memory access command contains pca and DCa registers. (The PC1 and DC1 are buffer registers for pca and DCa.) Instruction Cycle All instructions are executed in cycles that are timed by the trailing edge of WRITE. Moving memory addressing logic from the CPU to memory (and memory interface) devices simplifies CPU logic; however, it creates the potential for devices to compete when responding to memory access commands. There are two types of instruction cycle: the short cycle, which is four cf> periods long, and the long cycle, which is six cf> periods long. The long cycle is sometimes referred to as 1.5 cycles. Figure 7 illustrates the short cycle (PWs ) and the long cycle (PWd. Note that WRITE high appears only at the end of an instruction cycle. There will be as many PCO and DCa registers in a microcomputer system as there are PSU, DMI, and SMI devices; the ambiguity of which unit will respond to a memory read or write command is resolved by ensuring that all pca and DCa registers contain the same information at all times. Every PSU, DMI, and SMI device The simplest instructions of the F8 instruction set execute in one short cycle. The most complex instruction (PI) requires two short cycles plus three long cycles. Figure 7 Clock Generation Timing Signals I- -P'-I 1"- PWk ---.. XTLY td, WRITE ~ _II-- P~ I- ' ~~~~----PWs ---------<~~I td .... --.Ak- j N1\.'""I.~--------. -_ _ _----IL __ ]-----..11 ~l\--_ P w L - - + - l - - - - - - - -__1 pW, 3-14 F3850 has a unique address space, i.e., a unique block of memory addresses within which it responds to memory access commands. As referenced in the "ROMC Signal Functions" section, each ROMC state is identified by individual signal line states (1 for high, 0 for low), and by a two-digit hexadecimal code. The hexadecimal code is used to identify ROMC states throughout this data sheet. Also given in the "ROMC Signal Functions" section is the instruction cycle length (short or long) implied by each code, plus the way in which codes must be interpreted by the other F8devices. For example, an F3851 PSU may have an address space of H'OOOO' through H03FF'; an F3852 DMI may have an address space of H'0400' through H'07FF'. If a microcomputer system has these two memory devices and no others, then the F3851 PSU will respond to memory access commands when the PCO or DCO registers (whichever are identified as the address source) contain a value between H'OOOO' and H03FF'; the F3852 DMI will respond to addresses in the range H'0400' through H07FF'. No device will respond to addresses beyond H'07FF', even though such addresses may exist in PCO and/or DCO. Instruction Execution Sequence Every instruction execution sequence ends with an instruction code being fetched from memory to identify the next instruction cycle. The instruction code is loaded into the CPU instruction register, out of which it is decoded by the CPU control unit logic. An instruction fetch is executed during the last instruction cycle of the previous instruction, as illustrated in Figure 9. Each device compares its address space with the contents of PCO and DCO, whichever is identified as the address source, and only responds to a memory access command if the contents of PCO or DCO is within the device's address space. There is a group of F8 instructions that cause operations to occur entirely within the F3850 CPU. These instructions do not use the data bus, therefore can execute in one cycle. Since one-cycle instructions do not use the data bus, no ROMC state needs to be generated for the one-cycle instruction being executed; therefore, as illustrated in Figure 9, ROMC state 0 is specified, causing the instruction fetch of the next instruction. If all memory address registers (PCO, PC1, DCO, and DC1) are to contain the same information, then ROMC states that require any of these registers' contents to be modified must be acted upon by all devices containing any of these four registers. If devices are not to compete when an ROMC state specifies that a memory access must be performed, then only a device whose address space includes the identified memory address must respond to the ROMC state. Multi-cycle instructions must end with a cycle that does not use the data bus; ROMC state 0 is specified at the beginning of this last instruction cycle, causing the next instruction to be fetched. Following an instruction fetch, CPU logic decodes the fetched instruction code and executes the specified instruction. There are Five types of instruction cycles that can follow. As illustrated in Figure 8, the five ROMC signals that define the ROMC state are output early in the instruction cycle and are maintained stable for the duration olthe instruction cycle; i.e., only one ROMC state can be specified per instruction cycle. Therefore, devices can only be called upon to perform one instruction execution related operation per one instruction cycle. 1. Operations may all be internal to the CPU. This will be the last or the only cycle for an instruction, and will specify ROMC state 0, as illustrated in Figure 9. Figure 8 ROMC Timing Signals Output by F3850 CPU 1_ td, WRITE _____\~ \ _____________~L ___ ~___~/r---, l~td3_.1 ROMe LONG CYCLE _______________________--J){r--------------S-T-AB-L-E----------------3-15 • F3850 Figure 9A Short Cycle Instruction Fetch XTLY r -r- P~--=:1 __~AI_ PW2-111N_____________________ I __ " Id, WRITE td, ~~--- ----PWL----~rl I ______________________I______ ROMC II -'){~~___________________T_R_U_E_RO_M_C_S_TA_~__O__________________~I~I------___ J.:- Id. -I II I--~I I ----------------------I--------------------------------------------~XOPCODEFORNEXTI • •• INSTRUCTION ONE CYCLE OF THE SINGLE. LONG CYCLE DS INSTRUCTION (DECREMENT SCRATCHPAD) Figure 98 Long Cycle Instruction Fetch (During DS Only) XTLY b,-J r--1 Id'~i~ WRITE ____t ~~~~----------------PWs------------------~·1 ---,I N_~ _ _ _ _ _ _ _ I-PW2--l1 II I ROMC II --------------------~I-------X.....________---------------------------------III TRUEROMCSTA~O • .• I--Id,-I I DATA BUS NL.____ II 1-- Id.,. ---J I ----------------------------------------------------------~X ONE CYCLE OF A SINGLE CYCLE INSTRUCTION, OR LAST CYCLE OF A MULnCYCLE INSTRUCTION 3·16 OP CODE FOR NEXT INSTRUCTION NEXT INSTRUCTION F3850 2. Data may be transferred between the F38S0 CPU and memory devices. See the "Referencing Memory" section. 3. Data may be transferred from one memory device to all memory devices. The CPU is not the transmitter or the receiver of data in this transfer. See the "Memory-to-Memory Data Transfers" section. 4. Data may be transferred to or from an 1/0 port, as described in the "lnpuVOutput Interfacing" section. 5. An interrupt may be acknowledged, as described in the "Interrupts" section. Refer to the "Instruction Cycle Execution and Timing" section for a list of the instruction cycles and their associated ROMC state. Referencing Memory Memory may be referenced during an instruction cycle either to transfer the data from the CPU to a memory word or to transfer data from a memory word to the CPU. A memory reference occurs as shown in Figure 10. • If data is being output by the CPU, then the delay before data output is stable will be tdb 1 when data comes from the accumulator; the instruction cycle will be long. The delay before data output is stable will be tdb 2 when data comes from the scratchpad; the instruction cycle in this case will also be long. Every F8 instruction is executed as one, or a sequence of, standard instruction cycles. Timing for the standard instruction cycles is illustrated in Figures 9, 10, 11 and 12. Figure 10 Memory Reference Timing PWL -I L. :-------PWs--------J 11. . (WRITE) N .../r----'li~\,-----------------....1II ~I·~----------------I~,--~------------~ -I DATA BUS (1) __ 1 I I X I 1~.---Idb·-- I 1 1 (HIGH IMPEDANCE) I X DATA BUS (1) 1~.~--------------------ldb2----------------------~~ ·1 I STABLE X DATA BUS I' I· X DATA BUS -I -I DATA STABLE I' X DATA BUS Idb, Id". Id", DATA STABLE I -I 1 (2) There are four possible cases when inputting data to the CPU. via the data bus lines which depend on the data path and the destination in the CPU. as follows: (1) liming for CPU outpulling data onto the data bus. Delay tdb, is the delay when data is coming from the accumulator. tdb,.: Destination -IR (instruction Fetch) tdb.,: Destination - Accumulator (with ALU operation - AM) tdbs: Destination - Scratchpad (LR K.P etc.) tdbo;: Destination - Accumulator (no ALU operation - LM) Delay tdb 2 is the delay when data is coming from the scratchpad (or from a memory device). Delay tdb o is the delay for the CPU to stop driving the data bus. In each case a stable data hold time of 50 ns from the WRITE reference point is required. 3-17 F3850 Figure 11 Timing for Data Input or Output at 1/0 Port Pins '_4- - P W S - - - I - ' ~~ (WRITE)J ________ ____ ~ ___________ ~/~--~N ~11_lh ••- - - - I," ----~~II ----------~------------------~ DATA MAY CHANGE 1/0(1) STABLE I ,----------------OATA MAY CHANGE 1 1...... . - - - - - - - 10 ----~---I X',,~~~~~~~~N~E-W_-_D~A-T_A~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= 110 (2)---------I-----DA-T-A-F-R-0-M-0-L-O.-0-UT-S---...... (2) This represents the timing for data· being output by the CPU at the liD pin. (1) This represents the timing for data at the I/O pin during the execution of the INS instruction, Le., the CPU is inputting. Figure 12 Interrupt Signals Timing r PWs 14 WRITEJ'l- PW 2 ---.. / I_ PWL -I N I ROMC :~ld3~ / '--I TRUE rld'--I ICB(1) 1 I X I_·d'::j INTREQ(2) I ~ I I' INTREQ(2) -I Id, 1 !" 14 EXT RES I I I I I I I I I -I I '\ (1) The ICB signal will go from a 1 .to a 0 following the execution of the E1 instruction and will go from a 0 to a 1 following either the execution of the 01 instruction or the CPU's acknowledqement of an interrupt. (2) This is an input to the CPU chip and is generated by a PSU or F3853 M1 chip. The open drain outputs of these chips are all w~re-ANDed together on this line with the pull-up being located on the CPU chip. For a 0 to 1 transition the delay is measured to 2.0 V. 3-18 F3850 If data is being input to the CPU, then the delay before incoming data must be stable depends on the destination of the data, as illustrated in Figure 10. I/O port pin is a ''wire-AND'' structure between an internal latch and an external signal, if any. The latch is always loaded directly from the accumulator. The type of data transfer is identified by the ROMC state that is output at the beginning of the instruction cycle. Each F8 I/O pin can be set high or low under program control. If a 1 (high) is presented at the latch, then gate (b) turns on and gate (a) turns off, so that P is at Vss (low). If a 0 (low) is presented at the latch, then gate (a) turns on and gate (b) turns off, so that P is at Voo (high). The instruction fetch may also be viewed as a memory reference operation where the destination is the instruction register. Timing for this case is illustrated in Figure 9. When outputting data through an I/O port, the pin can be connected directly to a TTL gate input ("TTL Device Input" in Figure 13). Data is input to the pin from a "TTL Device Output" in Figure 13. Memory-to-Memory Data 1fansfers In response to appropriate ROMC states, data can be transferred from one memory device to all memory devices during one instruction cycle. For example, data can be transferred . from a memory byte within (or controlled by) one memory device, to one byte of an address register (PCO or DCO) within all memory devices. Three ROMC states (C, E, and 11) specify operations of this type, and Figure 10 illustrates timing for the data transfer. In Figure 10, tdb2 is the delay until data from memory or a memory address register is stable on the data bus. In normal operation, high or low levels at P drive the external TTL device input transistor (d). If a low level is set at P, transistor (d) conducts current through the path J, 1, P, and FET(b). This is transferred as a low level to the rest of the circuits in the TTL device and results in a high or low level at the output of the device, depending on its characteristics. If the level at P is set high, transistor (d) does not conduct current, and a high level is transferred by (d). Input/Output Interfacing Programmed I/O in the F8 microcomputer system is influenced by the design of the I/O port pins. As illustrated in Figure 13, each When data is input to the I/O pin, high or low levels at 0 drive the hysteresis circuit in the port and result in logic ones or zeros being transferred to the accumulator. Figure 13 F8 I/O Port Bit r----------------1 I Voo I , , , Voo II IL.. _ _ _ _ _ _ TTL DEVICE INPUT LATCH [0------ v•• L -_ _, _ - - - , I I I L _____ _ HYSTERESIS CIRCUIT TTL DEVICE OUTPUT (OPEN-COLLECTOR) 3-19 ~ IiII F3850 Since the I/O pin and the TTL device output at 0 are wire-ANDed, it is possible for the state of one to affect the transfer of data out from the I/O pin or in from the TTL device output. For example, if the latch in the I/O port is set so that the pin is clamped low by (b), then the level at 0 cannot pull P high. Conversely, if P is clamped to a low level by (c), setting the latch for a high level has no effect. nothing happens until the next interruptable instruction comes to the end of execution. In the case of the EXT RES signal, execution of the interrupt routine begins in the machine cycle immediately following that in which the signal goes low, prcr vided that the setup time specified in Figure 12 has been met. The EXT RES signal response logic ignores the ICB signal. In response to the INT REO signal being low, when the CPU acknowledges the interrupt, it forces the ICB signal high and initiates instruction cycles with ROMC states 1C, OF, 13, and 00, in that order. This causes program execution to branch to the interrupting device's address vector. All I/O port bits should be set for a high level, before data input, to prevent incoming logic zeros from being "masked" by logic ones present at the port from previous outputs. In some instances, the ability to mask bits of a port to logic 1 is useful. (Note that logic 1 becomes a 0 V electrical level at the I/O pin; logic 0 corresponds to a high electrical level.) In response to the EXT RES signal being low, when the CPU acknowledges the interrupt, it forces the ICB signal high, then initiates instruction cycles with ROMC states 1C, 08, and 00, in that order. This causes program execution to branch to memory 10cationO. The F8 CPU can execute two types of programmed I/O operation: 1) I/O via the two CPU ports (0 and 1) 2) I/O via ports on the other devices The ICB signal is pulled low by the E1 instruction and is returned high by the D1 instruction. InpuVOutput operations that use the two CPU I/O ports execute in two instruction cycles. During the first cycle, the fetched instruction is decoded; the data bus is unused. In this cycle data is either sent from the accumulator to the 110 latch or enabled from the I/O pin to the accumulator, depending on whether the instruction is an output or an input. At the falling edge of the WRITE Signal (marking the end of the first cycle and beginning of the second cycle), the data is strobed into either the latch (OUTS) or the accumulator (INS), respectively. The second cycle is then used by the CPU for its next instruction fetch. Figure 11 illustrates I/O timing. Instruction Set Summary The F3850 CPU instruction set is summarized in Table 3. This section does not attempt to give complete directions for programming the F8 microcomputer system; it explains signals and timing associated with the execution of every instruction. Refer to F8 and F3870 Guide to Programming for programming details~ The columns used in Table 3 are describe9 below. Op Code-The Op Code is the instruction mnemonic that appears in the mnemonic field of an assembly language instruction and identifies the instruction. Note that for the data input (INS) the setup and hold times specified are with respect to the WRITE pulse occurring at the end of the first cycle in the two-cycle instruction. For output data (OUTS) the delay is specified with respect to the falling edge of the WRITE signal marking the beginning of the second cycle in the two-cycle instruction. Operand (s)-If the instruction contains any information in the operand field of the assembly language source code, the information is shown inthis column. Arrows identify the portion of object code that represents the operand field. Any portion of object code that does not represent the operand field must represent the mnemonic field. Table 4 explains symbology used in the operand field. InpuVOutput instructions that address I/O ports with an I/O port address greater than H'OF' occupy two bytes; the first byte specifies an IN or OUT instruction, while the second byte provides the 110 port address. Required timing at I/O port pins is given in the section of this data sheet that describes the device containing the addressed I/O port. Object Code-This is the hexadecimal representation of the Interrupts There are three CPU signals with interrupt processing; timing for all signals is illustrated in Figure 12 instruction's object code. The first byte of object code, or in some cases'the first hexadecimal digit of object code, represents the Op Code. The operand is represented by the second and third bytes of object code, if present, or in some cases by the second hexadecimal digit of the first object code byte. Refer to Table 4 for symbology used in the object code field. An interrupt sequence is initiated by pulling either the INT REO signal or the EXT RES signal low. In the case of the INT REO signal nothing happens unless the ICB signal is low. Also, Cycle-This column identifies each instruction cycle for every instruction. Every cycle is listed on a separate horizontal line and is identified by the letter S for a short (four clock period) cycle or 3-20 F3850 Cycle the letter L for a long (six clock period) cycle. Thus, the entry o S 1 2 3S 3L 4 5 6 represents an instruction that executes in one short cycle. The entry S L S Represents Figure 8 tdb 1 in Figure 10 tdb2 in Figure 10 tdb3 in Figure 9A tdb3 in Figure 98 tdb4 in Figure 10 tdb 5 in Figure 10 tdbs in Figure 10 II Status Flags-Status flags are identified as follows: represents an instruction that executes in three cycles: the first is a short cycle; the second is a long cycle; the third (and last) is a short cycle. O-Overflow Z-Zero C-Carry S-Sign ROMC State-This is the state, as identified in the "ROMC Signal Functions" section, that is output by the F3850 CPU in the early stages of the instruction cycle. Within each column, symbology is used as follows: o Timing-Timing for all instructions, except INS and OUTS accessing I/O ports 0 and 1, can be created out of Figures 9 and 10. For the exceptions, Figure 11 is required. I/O Status not affected Status set to 0 Status set to either 1 or O,depending on the results of the instruction'S execution Interrupt-An "x" in this column identifies an instruction that disallows interrupts at the end of the instruction's execution. A "y" identifies cycles in which the ICB is reset to 0 (cleared). The ROMC lines are always set after a delay of td3, as shown in Figure 9. The only timing variations for each instruction cycle are data bus timing variations. Therefore, data bus timing is defined using the delays tdb 1 through tdb& With the exception of tdb3, these time delays are unambiguous in that they are keyed to either the leading edge or the trailing edge of the WRITE signal high, for a long or short instruction cycle, as illustrated in Figure 10. There are two cases for tdb:J, however, as illustrated in Figure 9. These are identified in Table 4 as 3S for Figure 9A and 3L for Figure 98; tdb 1 through tdbs are otherwise identified by the numbers 1 through 6. Function-The effect of each instruction cycle is described in this column using symbology given in Table 4. Instruction Cycle Execution and Timing Table 3 lists the instruction cycles, plus the ROMC state associated with each cycle, for every F8 instruction. Note that instructions are described in the table by order of ascending instruction (first byte) object code. Table 4 lists the symbology used in Table 3. Cycles that do not use the data bus are identified by 0 in the timing column; Figure 8 illustrates timing in this case. Table 3 Instruction Cycle Execution and Timing Op Code Operand(s) Object Code Cycle LR LR LR LR LR LR LR LR A,KU A,KL A,QU A,QL KU,A KL,A QU,A QL,A 00 01 02 03 04 05 06 07 S S S S S S S S ROMC State 0 0 0 0 0 0 0 0 Status Flags Timing 0 Z 3S 3S 3S 3S 3S 3S 3S 3S - - - 3·21 - C S - - - - - - - - - - - Interrupt Function AAAA r12 r13 r14 r15 (r12) (r13) (r14) (r15) - (A) - (A) - (A) - (A) F3850 Table 3 Instruction Cycle Execution and Timing (Continued) Op Code Operand(s) Object Code ROMC State Timing 0 Z C S 7 B 0 15 18 0 0 0 12 14 0 17 14 0 6 9 0 16 19 0 16 19 0 6 9 0 0 5 5 3S 2 2 3S 3S 3S 2 2 3S 2 2 3S 3 5 3S 2 2 3S 2 2 3S 5 5 3S 3S - - - - - - SR 1 12 l l S l l S S S l l S l l S l l S l l S l l S l l S S Sl 1 13 S 0 3S 0 110 0 1/0 SR 4 14 S 0 3S 0 110 0 1 Sl 4 15 S 0 3S 0 1/0 0 110 16 l S l S S 2 0 5 0 0 6 3S 1 3S 3S - - - - - - - 0 110 0 110 S S S S S S S 0 1C 0 1C 0 4 0 3S 0 3S 0 3S 0 3S 1/0 110 1/0 110 - - - lR lR K,P P,K lR LR PK A,IS IS,A lR PO,Q lR lR lR lR lM ST Q,DC DC,Q DC,H H,DC 08 Status Flags Cycle 09 OA OB OC OD OE OF 10 11 17 COM 18 lNK DI 19 1A EI 1B POP 1C - - - - - - - - - - - - - - - - - DCOU - (r14) DCOl - (r15) - DCOU - (r10) DCOl - (r11) - r10 - (DCOU) r11 - (DCOl) - - - - - - - - - 0 1/0 0 1 3·22 PCOl - (r15) PCOU - (r14) r14 - (DCOU) r15 - (DCOl) - - - x - - - A- (ISAR) ISAR- (A) PC1- (PCO); PCOl - (r13) PCOU - (r12) - - - PC1U - (r12) PC1l - (r13) - - - Function r12 - (PC1U) r13 - (PC1l) - - - Interrupt Shift (A) right one bit position (zero fill) Shift (A) left one bit position (zero fill) Shift (A) right four bit positions (zero fill) Shift (A) left four bit positions (zero fill) A - «DCO)) - (DC)- (A) - y - x - x - A - (A) E9 H'FF' Complement accumulator A- (A) + (C) ClearlCB Set ICB PCO- (PC1) F3850 Table 3 Inltnlctlon Cycle Execution and TIming (Continued) Op Code Operand(s) Object Code LR W,J 10 LR INC LI J,W 1E 1F 20 aa 21 aa 22 aa 23 aa 24 aa 25 aa NI 01 XI AI CI IN OUT PI aa I ar ala aa I ala ala PP PP ii jj L DCI 27 PP 28 ii jj iijj I JMP 26 PP 29 ii jj 2A ii jj !ijj I NOP XDC 2B 2C Status Flags Cycle ROMC State TIming 0 Z C S 8 8 8 8 L 8 L 8 L 8 L 8 L 8 L 8 1C 0 0 0 3 0 3 0 3 0 3 0 3 0 3 0 0 38 38 38 6 38 4 38 4 38 4 38 4 38 4 38 110 110 110 110 - - - - 110 110 1/0 110 L L 8 L L 8 L 8 L L 8 L L L 8 L 8 L 8 8 8 8 8 L 3 1B 0 3 1A 0 3 - - - 0 0 2 6 38 2 1 38 6 0 2 1 38 6 2 1 38 2 0 2 0 38 0 0 0 3L - - - 1/0 1/0 110 110 0 C 14 0 3 C 14 0 11 3 E 3 0 0 10 Interrupt Function W- (r9) x - - - - r9- (W) A-(A)+1 A- H'aa' - - - - 0 110 0 110 - - - A - (A) v H'aa' 0 110 A - (A) v H'aa' - - 0 1/0 - - 0 1/0 0 1/0 - - - - 1/0 110 1/0 1/0 - - - - - 1/0 1/0 1/0 1/0 0 - 110 0 - 1/0 - - - - - - - - - - - - - - - - - - - - A - (A) Ell H'aa' A - (A) + H'aa' - Perform H'aa' + (A) + 1. Do not save result, but modify status flags to reflect result. OB- PP A - (I/O Port PP) - - - OB- PP 110 Port PP - (A) x A-H'ii' PC1 - (PCO) + 1 PCOL- H'jj' PCOU- (A) - - - x - A-H'ii' PCOL- H'jj' PCOU- (A) - - x DCOU - ii (increment PCO) OCOL- jj (increment PCO) DCO ~ DC1 - t 8 0 38 - - - - r - (r) + H'FF' Decrement scratchpad byte A- (r) r,A 5f 8 0 38 - - - r - (A) ~ sr 8 0 38 - - - - 18ARU - O'e' D8 ~ LR A, LR Ll8U 3r f 3·23 II F3850 ~Ie 3 Op Code InstNCtlon Cycle Execution and nmlng (Continued) Operand(a) Object ROMC Code Cycle Stele nmlng LlSL ~ 6S+f S 0 3S LIS ~ 7f S 0 3S a$ S 1C 0 Ii S 3 0 S S L 0 1C 1 3S S L 0 3S 4 BT e'li AM SS AMD S9 NM SA OM SB XM SC CM SO ADC BR7 BF IN8 IN8 OUTS OUTS SE i/ tII. 00r1 SF ii gj ii AO,A1 4 thru 15 00r1 A4 thru AF 8O,B1 4 thru 15 B4 thru BF S L 2 0 2 0 2 3S 4 S L 8 L 8 L 8 L S 0 2 3S 4 0 3S L 8 S 8 L S 8 L 8 S 8 8 8 8 L L 8 8 8 L L 8 A 1 0 3S 2 0 2 0 2 0 4 3S 4 3S 4 3S 3 0 0 1C 1 3S 2 3S 0 2 0 38 1C 3 0 0 3S 0 3S 0 1 0 0 1C 0 1C 1B 6 0 3S 1C 0 0 3S 0 1C 1A 0 1 3S Stalus Flegs 0 Z C S - - - - - - - - 1/0 1/0 1/0 1/0 - - - - 1/0 1/0 1/0 1/0 1/0 - 0 - 1/0 0 0 0 1/0 0 0 3·24 1/0 110 1/0 - 1/0 1/0 - Function ISARL- O'e' A-H'Oe' Test e " W register Res = OsoPCO = (pco) + 2 Test e " W register Res ~ 0 so PCO (PCO) + H'ii'+ 1 = A - (A) + ((DCO» Binary, DCO - (DC)+ 1 A - (A) + «DCO» Decimal, DCO - (DCO) + 1 A - (A) " «DCO»; DCO - (DCO) + 1 A - (A)" «OCO»; DCO - (DCO) + 1 A - (A) E9 «DCO»; DCO - (DCO) + 1 Set status flags on basis of «DC» + (A) + 1; DCO - (DCO) + 1 DC - (DC) + (A) - 0 1/0 0 1/0 1/0 1/0 0 0 - Internlpt - - 1/0 - PCO - (PCO) + 2 because (ISARL) 7 PCO - (PCO) + H'ii' + 1 because (ISARL) ~ 7 Test t " W. register Res 0 so PCO (PCO) +H'jj'+ 1 Test t" W. register Res ~ 0 so PCO (PCO) + 2 = = = A - (I/O PortOor1) 110 - - = .DB - Port address (4 thru 15) A - (Port 4 thru 15) I/O Port 0 or 1 - (A) DB - Port address (4 thru 15) x Port (4 thru. 15) (A) F3850 Table 3 Instruction Cycle Execution and Timing (Continued) Op Code Operand(s) Object Code Cycle ROMC State Status Flags Timing 0 Interrupt Z C S AS r Cr S 0 3S 1/0 110 1/0 110 A - (A) + (r) Binary ASD r Dr lC 0 0 0 3S 110 1/0 1/0 1/0 A - (A) - - - + (r) Decimal - 3S 0 1/0 0 110 A - (A) EB (r) 0 1/0 0 110 A - (A) v (r) - - - - - - y IDLE PCOL - In!. address (lower byte); PCl - PCO PCOU - In!. address (upper byte) - - - x XS r Er S S S NS r Fr S 0 3S xx L L lC OF 0 2 L 13 2 S S L S 0 lC a 0 3S 0 1 3S INTRPT RESET xx - - - - - - - y x Function IDLE PCO - 0, PCl - PCO Table 4 Instruction Execution and Timing Symbology Symbol A (A) a aa bb Binary C DB DCO DCOL DCOU DCl Decimal e H Interpretation The accumulator The complement of accumulator contents A single hexadecimal digit being interpreted as data Two hexadecimal digits being interpreted as a single byte of data or as the high order byte of 16 bits of data Two hexadecimal digits being interpreted as the low order byte of 16 bits of data Binary arithmetic specified The carry status flag Fa system data bus The primary data counter register The low order byte of the primary data counter register The high order byte of the primary data counter register The secondary data counter register Decimal arithmetic specified A single octal digit being interpreted as data Scratchpad bytes 10 and 11 Two hexadecimal digits being interpreted as the high order byte of a 16-bit address or as a simple byte address displacement Symbol Interpretation ISAR ISARL ISARU The 6-bit scratchpad address register The low order three bits of ISAR The high order three bits of ISAR Scratchpad byte 9 Two hexadecimal digits being interpreted as the low order byte of a 16-bit address Scratchpad bytes 12 and 13 Scratch pad byte 13 Scratchpad byte 12 The overflow status flag A single hexadecimal digit being interpreted as an I/O port address (0-15) Two hexadecimal digits being interpreted as an I/O port address (0-255) The program counter register The low order byte of the program counter register The high order byte of the program counter register The stack register The low order byte of the stack register The high order byte of the stack register Scratchpad bytes 14 and 15 Scratchpad byte 15 Scratch pad byte 14 J jj K KL KU o p pp PCO PCOL PCOU PCl PC1L PC1U a aL au 3·25 • F3850 'nIble 4 instruction Execution and nmlng Symbology (Continued) Symbol S W Symbol Interpretation Single hexadecimal digit interpreted as scratchpad address: 4 = 0 through B for locations 0 through B in scratchpad r = C for ISAR as address source with no change after access r = 0 for ISAR as address source with ISARL = ISARL + 1 after access r = E for ISAR as address source with ISARL = ISARL-1 after access . r = F is not allowed The sign status flag A single hexadecimal digit identifying a status condition that is tested by a Branch on Condition instruction The status register Z II v E9 0 «()) + Interpretation The zero status flag The logical OR of 8-bit quantities on each side of this symbol is specified The logical AND of 8-bit quantities on each side of this symbol is specified The logical Exclusive-OR of 8-bit quantities on each side of this symbol is specified The value to the right of this symbol is to be loaded into the location specified on the left of this symbol The contents of the location within the brackets is specified The contents of the memory word addressed by the contents of the location within the double brackets is specified The binary address of 8-bit quantities on each side of this symbol is specified ROMC SIgnal Functions Table 5 describes the ROMC signals and their functions. 'nIble 5 ROMC Signal FuncUons ROMC Cycle 4321 0 HEX Length 00000 00 S,L o0 001 01 L 00010 02 L o0 0 1 1 03 L,S 00 o0 o0 o0 01 1 00 1 0 1 1 1 0 1 1 1 000 04 05 06 07 08 S L L L L o1 001 09 L o 1 010 o 1 011 OA OB L L Function Instruction Fetch. The device whose address space includes the contents of the PCO register must place on the data bus the op code addressed by PCO; then all devices increment the contents of PCO. The device whose address space includes the contents of the PCO register must place oli the data bus the contents of the memory location addressed by PCO; then all devices add the 8-bit value on the data bus, as a Signed binary number, to PCO. The device whose DCO addresses a memory word within the address space of that device must place on the data bus the contents of the memory location addressed by DCO; then all devices increment DCO. Similar to 00, except that it is used for Immediate Operand fetches (using PCO) instead of instruction fetches. Colt! the contents of PC1 into PCO. Store the data bus contents into the memory location pOinted to by DCO; increment DCO. Place the high order byte of DCO on the data bus. Place the high order byte of PC1 on the data bus. All pevices copy the contents of PCO into PC1. The CPU outputs zero on the data bus in this ROMC state. Load the data bus into both halves of PCO, thus clearing the register. The device whose address space includes the contents of the DCO register must place the low order byte of DCO onto the data bus. All devices add the 8-bit value on the data bus, treated as a signed binary number, to the data counter. The device whose address space includes the value in PC1 must place the low order byte of PC1 on the data bus. 3·26 F3850 Table 5 ROMC Signal Functions (Continued) ROMC 4 3 2 1 0 Cycle HEX Length a 1 1 a a ac L a 1 1 a 1 a 1 1 1 a aD aE S L a 1 1 1 1 aF L 1 a a a a 1 a a a 1 1a 11 L L 1 a a 1 a 12 L 1 a a 1 1 13 L a 1 a 1 a 1 a 14 15 16 17 18 19 1A L L L L L L L 1 1 a 1 1 18 L 1 1 1 a a 1 1 1 a 1 1C 10 LorS S 1 1 1 1 a 1E L 1 1 1 1 1 1F L 1 1 1 1 1 1 1 a1 a 1 a 1 a 1 1 a 1 a 1 a a a 1 1 a a 1 Function The device whose address space includes the contents of the pca register must place the contents of the memory word addressed by pca onto the data bus; then all devices move the value that has just been placed on the data bus into the low order byte of pca. All devices store in PC1 the current contents of pca, incremented by 1; pca is unaltered. The device whose address space includes the contents of PCO must place the contents of the word addressed by pca onto the data bus. The value on the data bus is then moved to the low order byte of DCa by all devices. The interrupting device with highest priority must place the low order byte of the interrupt vector on the data bus. All devices must copy the contents of pca into PC1. All devices must move the contents of the data bus into the low order byte of pca. Inhibit any modification to the interrupt priority logic. The device whose memory space includes the contents of pca must place the contents of the addressed memory word on the data bus. All devices must then move the contents of the data bus to the upper byte of DCa. All devices copy the contents of pca into PC1. All devices then move the contents of the data bus into the low order byte of pca. The interrupting device with highest priority must move the high order half of the interrupt vector onto the data bus. All devices must move the contents of the data bus into the high order byte of pca. The interrupting device resets its interrupt circuitry (so that it is no longer requesting CPU servicing and can respond to another interrupt). All devices move the contents of the data bus into the high order byte of pca. All devices move the contents of the data bus into the high order byte of PC1. All devices move the contents of the data bus into the high order byte of DCO. All devices move the contents of the data bus into the low order byte of pca. All devices move the contents of the data bus into the low order byte of PC1. All devices move the contents of the data bus into the low order byte of DCa. During the prior cycle, an I/O port timer or interrupt control register was addressed; the device containing the addressed port must move the current contents of the data bus into the addressed port. During the prior cycle, the data bus specified the address of an I/O port. The device containing the addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of timer and interrupt control registers cannot be read back onto the data bus.) None. Devices with DCa and DC1 registers must switch registers. Devices without a DC1 register perform no operation. The device whose address space includes the contents of pca must place the low order byte of pca onto the data bus. The device whose address space includes the contents of pca must place the high order byte of PCO onto the data bus. 3·27 • F3850 Timing Characteristics The timing characteristics of the F3850 are described in Table 6. Table 6 F3asO CPU SIgnal TImIng Characteristics ~ Max Units 0.5 1.0 1'5 200 Px -200 ns t r, tf..;30 ns Ext. to q, - to - Delay Extended Temp. Range 250 500 ns ns C L=100pF tx2 Ext. to q, + to + Delay Extended Temp. Ran~e 250 500 ns ns C L =100pF Pq, q, Period q, Pulse Width~ q, to WRITE + Delay 0.5 1.0 1'5 180 Pq,-180 ns t~ 150 250 400 ns ns C L=100pF 150 250 400 ns ns C L=100pF Pq, ns t~ 550 ns C L=100pF Symbol Characteristic Min P/ Extemallnput Period PWx" External Pulse Width txj PW, td, Extended Temp. Range td2 q, to WRITE - Delay Extended Temp. Range tf= 50 ns; C L = 100 pF PW2 WRITE Pulse Width PWs WRITE Period; Short PWL WRITE Period; Long td 3 WRITE to ROMC Delay. td/ WRITE to ICB Delay 350 ns CL=50pF td 5 WRITE to INT REO Delay 430 ns CL -100pF t sx" EXT RES Setup Time 1.0 1'5 C L -20pF tsu" 1/0 Setup Time 300 ns thO 1/0 Hold Time 50 ns to" 1/0 Output Delay tdbj WRITE to Data Bus Stable tdb2 WRITE to Data Bus Stable Pq, -100 Test Conditions 4Pq, 6Pq, 80 300 0.6 2Pq, 2.5 1'5 C L=50pF 1.3 1'5 C L=100pF 2Pq,+ 1;0 1'5 CL =100pF tdb3" Data Bus Setup 200 ns tdb/ Data Bus Setup 500 ns tdb5 Data Bus Setup 500 ns tdb6" Data Bus Setup 500 ns 1. tf 50 nstyp; CL = 100 pF Symbols marked with an asterisk (") refer to parameters that are most frequently of importance when interfacing to an Fa system. They encompass I/O timing. external timing generation, and possible external RAM timing. The remaining parameters are typically those that are only relevant between Fa devices, and not normally of concern to the user. 2. Input and output capacitance is 3 to 5 pF typical on all pins except VDO. VGG. andVss· 3. If M" REO is being supplied asynchronously. it can be pulled down at any time except during a fetch cycle that has been preceded by a non-privileged instruction. In that case INT REO must go down according to the requirements oftds· 3-28 F3850 DC Characteristics The DC characteristics of the F38S0 are provided in Table Z Voo=+SV±S%, VGG=+12V±S%, Vss=OV, TA=0·Cto+70·C Table 7 F38S0 CPU Signal DC Characteristics Signal Symbol Characteristic Min Max Unit Test Conditions ""WRITE VOH Output High Voltage 4.4 Voo V IOH=-SO/LA VOL Output Low Voltage Vss 0.4 V IOL =1.6mA VOH Output High Voltage 2.9 V IOH = -100 /LA V IH Input High Voltage 4.S VGG VIL Input Low Voltage Vss 0.8 V IIH Input High Current S SO /LA VIN=VOO IlL Input Low Current -10 -120 /LA VIN=VSS VOH Output High Voltage 3.9 Voo V IOH=-100/LA VOL Output Low Voltage Vss 0.4 V IOL =1.6mA V IH Input High Voltage 2.9 Voo V VIL Input Low Voltage Vss 0.8 V VOH Output High Voltage 3.9 Voo V VOL Output Low Voltage Vss 0.4 V IOL =1.6mA IIH Input High Current 3 /LA V IN = 7 V 3-State mode IlL Input Low Current -3 /LA V IN = Vss 3-State mode VOH Output High Voltage 3.9 Voo V IOH=-30/LA VOH Output High Voltage 2.9 Voo V IOH = -1S0 /LA VOL Output Low Voltage Vss 0.4 V IOL =1.6mA Internal pu II-u p to VDO XTLY ROMCQ-4 DB(}'7 IIO(}'17 EXT RES INT REQ ICB V IOH=-100/LA VIH Input High Voltage(1) 2.9 Voo V V IL Input Low Voltage Vss 0.8 V IlL V IH Input Low Current -1.6(4) rnA V IN =O.4V(2l Input High Voltage 3.S Voo V Internal pull-up to Voo VIL Input Low Voltage Vss 0.8 V -1.0 mA VIN=VSS Voo V Internal pull-up to Voo V IlL Input Low Current -0.1 V IH Input High Voltage 3.S V IL Input Low Voltage Vss 0.8 IlL Input Low Current -0.1 -1.0 mA VIN=VSS VOH Output High Voltage 3.9 Voo V IOH=-10/LA VOH Output High Voltage 2.9 Voo V IOH=-100/LA VOL Output Low Voltage Vss 0.4 V IOL = 100/LA 4. -1.8 V max. for extended temperature range. 5. Positive current is defined as conventional current flowing into the pin referenced. 1. Hysteresis input circuit provides additional 0.3 V noise immunity while internal pull-up provides TTL compatibility. 2. Measured while Fa port is outputting a high level. 3. Guaranteed but not tested. 3-29 F3850 Absolute Maximum Ratings Supply Currents Symbol Parameter 100 IGG Min Test Conditions VGG Voo rnA f=2MHz, Outputs Unloaded rnA f=2MHz, Outputs Unloaded XTLX, XTLY, and XTLZ All other inputs Storage temperature Operating temperature Typ Max Unit VooCurrent 45 75 VGGCurrent 12 30 -0.3 V,+15V -0.3 V,+7V -0.3 V,+15V -0.3 V,+7V -55°C, +150°C 0°C,+70°C These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Recommended Operating Ranges The recommended operating ranges of the F3850 are shown below. Supply Voltage (VGG) Supply Voltage (Voo) Part Number Min Typ Max Min Typ Max Vss F3850 +4.75 V +5 V +5.25 V +11.4V +12V +12.6V OV Ordertng Information Order Code Package Temperature Range F3850DC F3850DM F3850PC Ceramic Ceramic Plastic O°Cto +70°C -55°Cto+125°C 0°Cto+70°C 3-30 F3851/F3856 Program Storage Unit FAIRCHIL.D A Schlumberger Company Microprocessor Product Description The Fairchild F3851 and F3856 are the principal program storage devices for the F8 microcomputer system. The F3851 provides 1024 bytes of ROM; the F3856 provides 2048 bytes. The program storage unit (PSU) is customized with programs and permanent data tables, which are specified as ROM masks. The PSU devices have two 8-bit, bidirectional 1/0 ports, interrupt logic, a programmable timer, and a pulse width measurement circuit. They also contain memory addressing logic with data counters and program counters. The interrupt logic responds to requests from an external device and internally from the timer. The pulse width measurement circuit (F3856) is a combination of these two capabilities. • 1024/2048 Bytes of Program Storage • Intemal Memory Addressing Logic • 16 Bidirectional, Individually Controlled 110 Lines, Organized as Two 8-Blt Ports • Programmable Timer (F3856)- Preset, Start, Stop, and Read·Back Ability; Four Selectable Timer Count Rates, and Pulse Width Measurement • Full Interrupt Level- Dalsy·Chain Expandable, Independent Interrupt Address Vectors for Timer and Extemal Interrupt .2 MHz Operation • TTL and LSTTL Compatible • Low Power DisSipation, Typically Less Than 275 mW • +5 V and +12 V Power Supplies The PSU devices are manufactured using N-channel, isoplanar MOS technology; therefore, power dissipation is very low, typically less than 275 mW. Connection Diagram I/O ii7 110 A? Signal Functions DB7 DB, VGG 110 B, Voo Uo"A6 miNT 110 As PRIM I/O 85 WRITE " DBs DB, INT REO iiOii4 PRIIN i/o A:; DBDR 110 STROBE/NC' ROMC4 A; IIOB, DB3 ROMC3 DB, ROMC2 I/O B2 A2 ROMel 110 ROMeo I/O A, Vss I/O i1 AD DB1 II0Bo DBa 110 ONe for F3851 only. F3851 Device Organization Sys~em Clock Timing The PSU Is more than a read-only memory unit: every memo ory device within the F8 system contains its OWn memory addressing logic along with associated address registers. Refer to figure 1 for a simplified block diagram of the PSU. A single 8-bit data bus provides ali necessary communica· tion between a PSU (or any other memory device) and an F3850CPU. Ali timing within the F3851/F3856 PSU Is controlled by the +and WRITE Signals, which are generated from the F3850 CPU. Refer to the F3850 data sheet for a description of these clock Signals, The WRITE clock refreshes and up· dates PSU address registers, which are dynamic. The clock drives sequencing logic to precharge the ROM matrix; it also drives the programmable timer. + The PSU has an elementary arithmetic unit that can incre· ment and add 16-bit data units; for memory addressing logic, these two operations are sufficient. The PSU is func· tlonally illustrated in figure 2. These devices also contain a control unit that decodes the five read-only memory control (ROM C) lines, generated by the CPU, as though they were a &bit instruction code. Similar to the CPU, the PSU gener· ates internal signals to control data flow and arithmetic logic within itself. One control output, data bus drive (DBDR), is generated to coincide with data being output by the PSU. 1/0 Ports The unit contains four preassigned 1/0 port addresses: the two lowest are assigned to 1/0 ports A and B and are used to transfer data to and from external devices. The other two 1/0 addresses are assigned to the-programmable timer and the Interrupt control register and are treated as 1/0 ports. Associated with the 1/0 ports Is an 1/0 port address select register (ASR). This is a 6-blt register for the F3851 and a 5·blt register for the F3856. The contents are a mask option, which must be specified at the time the PSU is created. The ports are addressed as follows: XXXXXXOO XXXXXX01 XXXXXX10 XXXXXX11 1/0 port A 110 port B Interrupt control register Programmable timer Figure 1 PSU Simplified Block Diagram F3856 OUTPUT STROBE 1/0 PORT A 1/0 PORT B DATA BUS PROGRAM COUNTERS DATA COUNTERS ROM DBDR . - PROGRAMMABLE TIMER • ROM CONTROL LINES EXTERNAL INTERRUPT PRIORITY IN PRIORITY OUT INTERRUPT LOGIC VGG Voo GND t " t WRITE 3-32 INTERRUPT REQUEST F3851 ROM Addressing For example, If the six binary digits are 000010, the four I/O port addresses are H'08~ H'09~ H'OA', and H'OB~ The F3851 BK PSU has 1024 bytes of read-only memory; the F3856 16K PSU has 2048 bytes. This ROM array may contain object program code andlor tables of nonvarying data. Every PSU is implemented using a custom mask that specifies the state of every ROM bit and certain address mask options that are external to the ROM array. When a logic 1 is output to I/O port A or B, It places a 0 V level on the output pin. This same inverted logic applies to Input. The F3851 I/O ports, timer, and interrupt control register are not initialized during the power-on reset cycle. The F3856 1/0 ports and interrupt control register are Initialized during both the power-on or external reset cycle; the timer register Is not initialized during power-on or external reset cycles. Figure 2 PSU Functional Diagram r------------------.....:..------------------, F3856 P.W. PRE LOGIC· ~] UPPER BYTE I LOWER BYTE ..'" ~ ... .. I III t + INCREMENTER ADDER LOGIC I I a: I !::C I ; I I I I I I I - t DATA • COUNTER DC, ~ Q Q . -I 1- 1-1 DATA COUNTER DCa LOWER BYTE I ORDER ADDRESS BITS ... ~ ..:ll'" CONTROL UNIT LOGIC I I ; • 1024 x 8-BIT ROM STORAGE ~ Q !:: ~ • • 110 PORTA 5/18 HIGH ORDER ADDRESS BITS _I PAGE SELECT J I 110 PORT ADDRESS SELECT II I t PROGRAM COUNTER PCa DATA BUFFER ~ Q Q ~ J '"c • 10/11 LOW a: STACK REGISTER PCl INTERRUPT ADDRESS VECTOR ~ ... c -I -I TIMER INTERRUPT LOGIC UPPER BYTE r-- a: ~ a: I ADDRESS DEMULTIPLEXER ~ L ________________ _ 3-33 Vss VGG Voo +18 =+! :-- PRIOUT--+- 6 . - ------r---- I I '-_ ---- PAliN --+- 10 INT REO--+- 9 EXTINT-I- 5 - I ~ ~~~~a =+= ----------------------- EJH 17 =g=~; =+~: ROMC, - , 1 4 ROMe. -+-13 DBa DB, DB, DB, DB• DB, DB, DB, I =+= =+=: 22 -,27 - + - 28 -,39 -t- 40 I -,19 - + - 24 -,25 - + - 30 =+~ =+:7 STROBE:...j... 8ii ~ ~ ~ 17 -.. ....-. WRITE ---------------- --+- =+:: =+=~: =+=~: ,1 ::f8 7 F3851 The ROM addressing logic consists of 16-blt registers: program counter PCo, stack register PC1, and data counter DCa. Data counter DC1 Is provided on the F3856 as an additional buffer for DCa. If the hlgh-order bits of the address coincide exactly with the page select mask, an enable signal Is generated, causIng the PSU logic to respond to a memory access request. If the hlgh-order bits of the address do not coincide exactly with the page select, no enabling Signal is generated and the PSU does not respond to memory access requests. A 6-bit page seleCt register and 1O-bit address select register provide decode logic for the F3851. The F3856 uses a 5-bit page select register and an 11-blt address select register. The page select register identifies the memory addressing space of the individual PSU device. Each of the 32 (or 64) page select options allowed by the 5-blt (or 6-bit) page select register identifies a single address space consisting of 2048 (or 1024) continguous memory addresses. Program Counter, Data Counter, and Stack Registers Program counter pca always addresses the memory location out of which the next program instruction byte Is read. If the instruction requires data (I.e., an operand) to be accessed, data counter DCa must address memory for this purpose; pca cannot be used to address data, since It Is saving the address of the next Instruction code. By using the exchange DC Instruction in the F3856 program, the two data counter contents of DCa and DC1 can be exchanged. Incrementer Adder logic There are only two arithmetic operations that memory devices need to perform on the contents of memory address registers: 1. Increment by 1 the 16-bit value stored in address pca or DCa· The provision of two address registers, PCo and DCa, is a convenience to the F3850 CPU and is not a necessary part of the memory addressing logic sequence within a PSU. Address decoding is identical, whether originating In pca or 2. Add an 6-blt value, treated as a Signed binary number (subject to twos complement arithmetic) to the 16-bit value stored in an address register. If the 6-blt value Is being treated as a signed binary number, the hlgh-order bit of the 6-bit value is the sign bit; the sign bit must be propagated through the missing hlgh-order eight bits. DCa· The Pca, PC1, and DCa are loaded from two consecutive Single-byte inputs on the data bus; PC1 and DCa are transmitted as two single-byte outputs on the data bus. The contents of DCa and DC1 of F3856 can be exchanged in one Instruction. The PSU control unit Implements the incrementer adder logic through control signals internal to PSU device logic. Addressing Consistency In Multiple Memory Devices When an ROMC state specifies a memory access, only one memory device responds to the memory access operation Itself. However, every memory device responds to ROMC states that call for modifying the contents of a program counter or data counter register. Providing every memory device that is connected to the 6-bit data bus of an F3850 CPU Is also connected to the ROMC control lines of the same CPU, address contentions cannot arise. Every memory device simultaneously receives the same ROMC state signals from the CPU; every memory device responds to ROMC states by Identically modifying the contents of memory address registers, if such modifications are specified. Therefore, every pca register on every memory device always contains identical information; the same Is true for DCa and PC1 registers. Stack register PC1 is a buffer for program counter PCo; the contents of PC1 are never used directly to address memory. When an Interrupt is acknowledged, the contents of pca are saved In PC1. Page Select and Address Select Registers All memory addresses are 16 bits wide, whether originating in the program counter or in the data counter. Address decode logic within the PSU separates the 16-blt address Into two portions: the low order addresses the ROM storage bytes; the high order addresses the page. High-Order Byte Address Low-Qrder Page Address F3851 1024 Byte Select 6 Bits 64 Page Options 10 Bits F3856 2048 Byte Select 5 Bits 32 Page Options 11 Bits Only one memory device (the one whose address space includes the specified memory address) actually responds to any memory access request. To avoid addressing con· fllcts, it Is only necessary to ensure that the following conditions exist: 3·34 F3851 Signal Descriptions The PSU Input and output signals are described in table 1. Tabla 1 PSU Signal Descriptions Mnamonlc Clock Pin No. Nama Description + WRITE 8 7 Clock The two clock Input signals that originate at the F3850CPU. 110 Ao-iiOA7 19,24,25, 30,31,36, 37,2 110 Ports A Bidirectional ports through which the PIO communicates with logic external to the microprocessor system. 11080-110 B7 20,23,26, . 29,31,35, 38,1 110 Ports B 17,16,15, 14,13 Read-Only Memory Control Input signals that originate at the F3850 CPU control internal functions of the PSU. 21,22,27, 28,33,34, 39,40 11 Data Bus Bidirectional 3-state lines that link the PSU to ali other devices within the microprocessor system. Data Bus Drive A low output, open-drain signal that indicates the data bus currently contains data flowing from the PSU. 12 Strobe This output signal provides a positive pulse whenllO port A is being read by an input instruction or is being updated by an output instruction (F3856). 5 External Interrupt A high-to-Iow transition on this input signal is interpreted as an interrupt request from an external device. This output signal is the iNT REO input to the F3850 CPU; it must be out~ I~ to interrupt the CPU, which occurs only if PR IN is low and PSU interrupt control logic is requesting an interrupt. Unless this ~t signal is low, the PSU does not signal low in response to an set the Ifii'i' R interrupt. This output signal becomes the PRi iN signal to the next device in the Interrupt-prir; daisy TfiI signal is chain; it is output high unless the entering the PSU low and the PSU is not requesting an interrupt /0 Ports _1- Control ROMCo-ROMC4 Data Bus DBo-DB7 OBOR Strobe STROBE Inta~~ EX"I' I INT REO 9 Interrupt Request PRI iN 10 Priority In 6 Priority Out PRi OUT Powar VDO V,GG v,ss 4 Power Supply 3 18 Power Supply +5V ±5% +12 V ±5% System ground -0 V; VDD and VGG are referenced to Vss. Ground 3-35 • F3851 ROMe States 1. All memory devices must receive the same ROMC state signals from one CPU and must contain identical information. Table 2 lists the data bus contents as a function of ROMC states. 2. Page select masks must not be duplicated - more than one memory device cannot have the same memory space. Instruction Execution The PSU responds to signals that are output by the F3850 CPU in the course of implementing instruction cycles. Refer to table 2 for a summary of the data bus response to the ROMC states generated by the CPU. 3. The memory address contained in the specified register (PCo or DCo) must be within the memory space of at least one memory device. Data Output by the PSU Figure 3 provides timing when the PSU outputs data on the Figure 3 Data Bus Timing - -- - td, WRITE td, ....-.PW2--' _ t d3 / _1 ,---, --- ROMC -'I.. / LONG CYCLE STABLE . td, ~ X DATA BUS OUTPUT DBDR (START OF DATA OUT) STABLE "\.. -tda-I DBDR (END OF DATA OUT .I ~I,_------------- td,_ _ _ _ _ _ _ ~ ~ IN SUBSEQUENT CYCLE) _ _ _ _ _ _ _ _ _ _ ________ >k DATA BUS INPUT --------------------------------~ 3·36 STABLE F3851 worst case, in time for the setup required by any F3850 CPU destination (refer to the F3850 CPU data sheet). data bus. This timing applies whenever a PSU is the data source. The PSU places data on the data bus, even in the Table 2 Data Bus Contents as a Function of the ROMC State ROMC State (Hex) 00 01 02 03 If F3851/F3856 PSU is the Source· Description of Data Instruction Offset for branch Operand Operand Address·· If F3850 CPU is the Source Description of Data PCa PCa DCa PCa 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C Byte to be stored Upper byte, DCa Upper byte,· PC1 =00 for Offset for DCa Lower byte, PC1 Byte for PCa, lower PCa Byte for DCa, lower Lower byte of interrupt vector if it is source of the interrupt PCa Byte for DCa, upper PCa Byte for PCa, lower Upper byte of interrupt vector if it is source of the interrupt Byte Byte Byte Byte Byte Byte Byte for for for for for for for Byte from 1/0 register, if selected (Note 1) 10 1E 1F pca Lower byte, DCa Lower byte, PCa Upper byte, PCa ·Only drives the data bus within the segment of address space that belongs to the PSU . •• An entry In this column specifies the register from which a memory address was obtained. Note 1 Ourlng INS or OUTS instruction for port a or 1: 110 byte During INS or OUTS instruction for port 4-F: 110 address During all other Instructions, F385a does not drive. 3·37 PCa, upper PC1 , upper DCa, upper Pca, lower PC1, lower DCa, lower selected 1/0 port • F3851 Each 1/0 port pin is a wire-AND structure between an internallatch and an external Signal, if any. The latch is always loaded directly from the accumulator. Each 1/0 pin is set high or low under program control. If a 1 (high) is presented at the latch, gate (b) turns on and gate (a) turns off, so that P is at Vss (low). If a 0 (low) is presented at the latch, gate (a) turns on and gate (b) turns off, so that P is at Vee (high). The data bus drive signal (DBDR) is low, while data output by the PSU is stable on the data bus. Thus, a DBDR low signal indicates that the data bus currently contains data flowing from a PSU. For systems with more than one PSU, the DBDR outputs can be wire-ORed and the result used as a bus data flow direction indicator. The BBi5'R signal remains low until timing delay tda into the instruction cycle following the one in which DBDR was set low. When data is output through an 1/0 port, the pin is connected directly to a standard TTL gate input. Data is input to the pin from a TTL output. In normal operation, high or low levels at P drive the external TTL device input transistor (d). If a low level is set at P, transistor (d) conducts current through the path J, I, P, and FET (b). This is transferred as a low level to the rest of the circuits in the TTL device and results in a high or low level at the output of the device, depending on its characteristics. If the level at P is set high, transistor (d) cuts off and a high level is transferred by (d). When data is input to the 1/0 pin, a high or low signal at the pin transfers a logic 1 or 0 to the accumulator. Data Input to the PSU When the PSU receives data off the data bus, in the worst case, the data must be added to a 16-bit number within the PSU adder/incrementer. This worst case corresponds to data coming from the accumulator of the CPU for an ADC instruction or from a memory device for a BR instruction. For this worst case, arriving data must allow sufficient time for 16-bit adder logic (time delay td 4 in figure 3 identifies this worst-case timing). PSU Input/Output Interfacing The 1/0 ports with addresses XXXXXXOO and XXXXXX01 (XXXXXX is the 6-bit 1/0 port address select) are used to transmit data between the PSU and external devices. The IN and INS instructions cause data at the 1/0 ports to be transmitted to the CPU; the OUT and OUTS instructions cause data in the CPU accumulator to be loaded into an 1/0 port. Each 1/0 pin has an output latch that holds the pin DC data. Since the 110 pin and the TTL device output at 0 are wireANDed, it is possible for the state of one to affect the transfer of data out from the 1/0 pin or in from the TTL device output. For example, if the latch in the 1/0 port is set so that the pin is clamped low by (b), the level at 0 cannot pull P high. Conversely, if P is clamped to a low level by (c), setting the latch for a high level has no effect. Input and output operations using the two PSU 1/0 ports execute in three instruction cycles. During the first cycle, the port address is transmitted to the data bus. During the second cycle, data is either sent from the accumulator to the 1/0 latch or enabled from the 1/0 pin to the accumulator, depending on whether the instruction is an output or an input. At the falling edge of the WRITE signal (marking the end of the second cycle and beginning of the third cycle), the data is strobed into e.ither the latch (OUTS) or the accumulator (INS), respectively. The third cycle is then used by the CPU for its next instruction fetch. Open-Drain Configuration (Figure 5)- When the 1/0 port is configured as shown in figure 5, the drain connection of FET (a) is open, i.e., not connected to Vee through a pull-up transistor. This option is most useful in applications where several signals (pOSSibly several 110 port lines) are to be wire-QRed together. A common external pull-up, RL, is used to establish the logic 1 levels. Another advantage of this option is that the output (point y) can be tied through a pullup resistor to a voltage higher than Vee (clear up to VGG) for interfacing to external circuits requiring a higher logic 1 level than Veo provides. I/O Port Options Data bus timing associated with the execution of 1/0 instructions does not differ from data bus timing associated with any other data transfer to or from the PSU. However, timing at the 1/0 port itself depends on which port option is being used. Figures 4, 5, and 6 illustrate the three port options; figure 7 illustrates timing for the three cases. If a high level is present at point X (coming from the port latch), FET (a) will conduct and pull point Y to a low level by current flow through RL. This low level at Y causes transistor (b) to turn on and present a low level to the input TTL circuit. If a low level is present at X, FET (a) turns off and point Y is pulled toward Voo by RL. This causes transistor (b) to turn off and present a high level to the internal TTL circuits. Standard Pull-Up Configuration (Figure 4)-AIlI/0 port bits should be set for a high level, before data input, to prevent incoming logic Os from being masked by logic 1s preset at the port from previous outputs. In some instances, the ability to mask bits of a port to logic 1 is useful. (Note that logic 1 becomes a 0 V electrical level at the 1/0 pin; logic 0 corresponds to a high electrical level.) When data is input, a high level at the base of transistor (c) causes (c) to conduct and pull pOint Y low, with current flow through TL• This transfers a high level to the internal 1/0 port logic through inverting action by the hysteresis circuit. If a 3-38 F3851 Figure 4 Standard Pull-Up Configuration ,I -Voo- - - - - - - - - ----------------1 I I I I I OUTPUT STROBE I • I I I I I I I I HYSTERESIS CIRCUIT TTL ~EVICE OUTPUT _________ _ IL..:.(OPEN-COLLECTOR) I ----------------~ Figure 5 Open-Drain Configuration - - - - - - - - - - - - - - - 1 ,I -VOO- - - - - - - - - - VOO I 1/0 PORT I I I I I I x RL I I I L __________ _ .----------- I I I I -------------~-~ Figure 6 Driver Pull-Up Configuration I TTL OUTPUT L __________ _ low level is present at the base of (c), conduction stops and point Y is pulled toward Vee by RL• This is then transferred as a low level to internal I/O port logic through the hysteresis circuit. Voo LED (b) Driver Pull-Up Configuration (Figure 6)- Figure 6 shows the I/O port driver pull-up option used to drive an LED indicator. This application is typical of a front·panel address or data display, where a row of LED indicators shows the logic state at each pin of an I/O port. I I I -= I A high level at X turns FET (b) on and (a) off, providing a path for current through resistor R from the base of transis· tor (c). This stops (c) from conducting and the LED does not light. If a low level is present at X, (b) turns off and (a) turns -----------~ 3-39 F3851 on, providing a path for current from Voo through (a) to R. This current through R turns on (c), which causes the LED to conduct and be lighted. During input instrucions, the trailing edge of the STROBE signal is used to indicate to the external device that the current data on the 1/0 port is read and new data can be changed. For example, if a shift register is connected to the 1/0 port, the trailing edge of the STROBE signal is used to advance the shift register. The three options for 1/0 port output configurations descrIbed above are provided to aid the designer in optimizing (minimizing) the system hardware for a particular application. The choice in configuration is specified as a mask option by the designer. During output instruction, the trailing edge of this STROBE signal indicates that the new data on the 1/0 port latches is being changed. The output on the latches becomes true after typically 500 ns of the trailing edge of this signal. Figure 7 PSU 1/0 Port Timing Refer to the "liming Characteristics" section for all signal characteristics. WRITE \. , I-I,"---T (11 INPUT )( DATA MAY CHANGE DATA STABLE 1- h-1 l ) ( DATA MAY CHANGE "--Isp~ OUTPUT 121 (STANDARD PULLUP) Y ~.9V STABLE ~tod---' y OUTPUT (2) (OPEN DRAIN) STABLE 2.9 V --.~l ~tdp-----' OUTPUT 121 _ _ _ _ _ _ _ _ _ _ (DRIVER PULLUP) X STABLE 2.9V F3851 Programmable Timer F3856 1/0 Strobe An additional output strobe signal is provided on the F3856 to indicate the execution of an input or output instruction for the low address 1/0 port on the PSU circuit. (This is port 4 of the PSU circuit with the 4-7 address.) A pulse of the duration of the WRITE clock on the STROBE pin is provided at the end of the second cycle of the 1/0 instruction for this port. Figure 8 shows the timing relationship of this output with respect to the execution being performed. The F3851 PSU has an 8-bit shift register, addressable as 1/0 port XXXXXX11, that can be used as a programmable timer (XXXXXX is the 6-bit 1/0 port address select, a PSU mask option). Figure 9 illustrates the shift register logiC and the exclusive-OR feedback path. Based·on the logic illustrated in figure 9, binary values in the range 0 through 254, when loaded into the timer, are converted into "timer counts." As shown in table 3, "timer contents" is the actual binary value loaded into a timer, and "timer counts" is the corresponding number of time intervals the timer takes to time out. Data cannot be read out of the programmable timer 1/0 port. Although this pulse appears for both input and output instructions for this port, two different signals for input only are derived from the external gating of the STROBE and ROMCo signals, as shown below. As described in the Guide to Programming the F8 Microcomputer, an assembly-language program specifies timer counts, and the assembler converts timer counts into the binary value that must be loaded Into the programmable timer. This is the value given under "Contents" in table 3. To 3·40 F3851 Figure 8 1/0 Instruction Fetch and Strobe Timing 1.4 . ; - - - - - - - - - - - - - 1 / 0 I N S T R U C T I O N - - - - - - - - - - - - _ .... 1 ~~ I __________ ~n~ I __________ ~n_: n __ ~n~ I FETCH ___ INST. _ _ .....o--_ _--'::PO':':R:..:T:7A=::D;c-DR:::E=::S~S---...........o--_ _C'-'P-=U_--CD:.:B:...:(c=0..:.UT.:cP...:U.c.T'-)_---;:.....:_ _ NEXT_ FETCH ON DATA BUS PSU - DB (INPUT) INST I I S T R O B E - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _~. • • ---------Figure 9 F3851 Timer Block Diagram PRESET TO GIVE TIMER ClK AFTER TWO ADDITIONAL", PERIODS WHENEVER TIMER IS lOADED JAM 8 BITS PARAllEL IF lOADED DECODE TIMER STATE 'FE' AS TIME·OUT T2 T3 D Q D Q T4 D Q T5 D Q T& > D Q T7 C MSB T3 L-~~---Clr==---(].~e----~ T4 T5 ~--------(]~------------~ T7 use a programmable timer, bypassing assembly·language programming, load the programmable timer with the value given under "Contents" in table 3 to time out after the num· ber of intervals given under "Counts." All timers run continuously, unless they have been stopped by loading H'FF' into the timer. Upon timing out, the timer transmits an interrupt request to the interrupt logic. If proper interrupt logic conditions exist, the timer interrupt request is passed on to the CPU through the iNi' REO signal. It is also possible to write small subroutines that calculate time values one count faster or slower than a given value. Such subroutines would be used if programmed delays are required, After a programmable timer has timed out, it again times out after 255 timer counts; therefore, if the programmable timer is left running, it times out every 7905 clock periods, or every 3.953 ms for a 500 ns clock. + The OUT or OUTS instruction is used to load timer counts into the programmable timer. The contents of the program· mabie timer cannot be read using an IN or INS instruction, The timer times out after a time interval given by the prod· uct (period of clock x (timer counts) x 31). For example, a value of 200 (11001000, or H'C8110aded into the program· mabie timer becomes 215 timer counts. The timer, therefore, times out in 3.33 ms, if the period of clock signal is 500 ns. If the timer is actually loaded with a zero value, it times out in 24 counts, whereas, once it has timed out, it next times out in 255 counts; i.e., a time-out is not the same thing as counting down to zero. + + When the timer and timer interrupt are being set to time a new interval, the timer is always loaded before enabling the timer interrupt. Loading the timer clears any pending timer interrupts. When the timer Interrupt is enabled, any pending A value of 255 (H'FF110aded into a programmable timer stops the timer. 3·41 F3851 timer interrupt is acknowledged and forwarded to the CPU. Since the timer runs continuously, unless stopped under program control, enabling the timer before loading a time count can cause errors. Prior time-outs of the timer are latched in the interrupt logic of the PSU, even while timer interrupts are disabled. When the timer is enabled, an immediate interrupt acknowledge occurs if, by chance, the continuous-running timer happens to time out while timer interrupts are disabled. F3851 Interrupt Control Register The interrupt control register. (ICR) has the 110 port address XXXXXX10 (where XXXXXX is the 6-bit 110 port address select). Data is loaded into this register (110 port) using an OUT or OUTS instruction. Data cannot be read out of this register. The contents of the ICR are interpreted as follows: Contents of I/O Port If the timer Is loaded just before enabling timer interrupts, loading the timer clears pending timer interrupts. Now a spurious interrupt request does not exist when the timer interrupt is enabled. Disable all interrupts B'XXXXXXOO' B'XXXXXX01 ' Enable external interrupt, disable timer interrupt B'XXXXXX10' B'XXXXXX11' Figure 10 illustrates a possible signal sequence for a timer that is initially loaded with 200, then allowed to run continuously. Interpretation Disable all interrupts Disable external interrupt, enable timer interrupt Figure 10 Time·Out and Interrupt Request Timing _3.3 ms-~_-3.953 ms--t_-3.953 m s _ A - 200 LOADED INTO TIMER B - FIRST TIME OUT C - SECOND AND SUBSEQUENT TlME·OUTS D - INTERRUPT SERVICE ROUTINES BEING ENTERED BY CPU I" I,. I, -INTERVALS BETWEEN TlME·OUT INTERRUPT REQUEST.REACHING INTERRUPT LOGIC AND SERVICE ROUTINES BEING ENTERED BY CPU Table 3 F3851 Timer Counts Contents of Counter Counts to Interrupt Contents of Counter Counts to Interrupt Contents of Counter Counts to Interrupt Contents of Counter Counts to Interrupt FE FO FB F7 EE 254 40 9A 189 188 187 188 185 184 183 182 181 180 02 A5 4B 124 123 122 121 1. 20 119 118 117 116 115 9F 3D 7C F8 F1 59 58 57 DC B8 71 E3 C7 253 252 251 250 249 248 247 246 245 34 69 03 A7 4F 9E 3C 78 96 20 5B B7 6E DO BA 3·42 E2 C5 SA 15 2A 56 55 54 53 52 51 50 F3851 Table 3 F3851 Timer Counts 8E 10 3B 76 EO OA B4 68 01 A3 47 8F 1F 3F 7E FC F9 F3 E6 CO 9B 36 60 OB B6 6C D9 B2 64 C8 91 23 48 80 1B 37 6F OF BE 70 FA F5 EA 04 A9 52 A4 49 92 25 4A 94 29 53 A6 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 FO EO C1 82 04 06 12 24 48 90 21 42 84 'A 14 28 51 A2 45 8B 17 2E 50 BB 77 EF OE BC 79 F2 E4 C9 93 27 4E 9C 38 70 E1 C3 86 OC 18 31 63 C6 8C 19 33 67 CE 90 3A 74 E9 179 178 177 176 175 174 173 172 171 170 169 168 167 168 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 138 135 134 133 132 131 130 129 128 127 126 125 75 EB 06 AO 5A 85 6A 05 AB 56 AC 58 B1 62 C4 68 11 22 44 89 13 26 4C 98 30 61 C2 84 96 95 94 93 92 91 90 89 68 87 03 10 20 40 81 02 82 81 86 85 84 83 05 80 OB 16 2C 79 78 59 76 75 74 73 B3 66 CC 99 32 65 CA 95 2B 57 AE 5C B9 73 E7 CF 3-43 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 77 72 71 70 69 68 67 66 65 64 63 62 61 80 55 AA 54 A8 50 AO 41 83 06 00 1A 35 6B 07 AF 5E BO 7B F6 EC 08 BO 60 CO 80 00 01 03 07 OF 1E 30 7A F4 E8 DO A1 43 87 OE 1C 39 72 E5 CB 97 2F 5F BF 7F FE 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 254 • F3851 In these 1/0 port contents definitions, X represents "don't care" bi nary digits. The flip-flop is not cleared by a loading of ICA. While counting, the timer jumps from all-zero value to all-one value and, depending on prescaler values, provides an interrupt period of every 512, 2048, 8192, or 32768 clocks. + F3856 Timer and Interrupt Control Registers The F3856 logic responds to an interrupt request that can originate internally from the timer logic or from input by an external device, or from the pulse width measurement circuits. Interrupt functions present in the F3856 include the ability to program the active transition of the external Inter· rupt, the ability to have both the timer and the external interrupts active at the same time, and the ability to mea· sure pulse width of an external signal. If the timer is in the run mode and the ICR is set for a prescaler value of 2 at the time a value of 2 or 1 is loaded into the TR, the next transition from a one-count to a zerocount is not detected. F3856 Interrupt Control Register Configuration The ICR is a 7-bit register used to define various modes of interrupt, the value of the prescaler, and external pulse width measurement. This register is loaded by output instructions; no provision Is made to read the contents of this register. The ICR, along with the 110 ports on the F3856, is reset to zero during the reset sequence. The timer is an 8-bit binary count-down register that is used in conjunction with interrupt logic to generate real-time intervals, to measure elapsed time between two events, or to measure a pulse width appearing on the EXT INT signal. The timer is selected to run in one of four values provided by the prescaler and can be made to start counting or stop counting under program control. Also, the timer contents can be read back under program control. The configuration of this register Is shown in figure 11. Figure 11 F3856 ICR Configuration A zero-detect circuit in the timer detects transitions from a one-count to a zero-count and provides a signal to the interrupt circuits. If all other conditions are satisfied, interrupt circuits, after receiving this signal, request an interrupt service from the CPU. III An external interrupt can be selected under program control to detect the falling or riSing edge of the signal. The active edge is determined by the contents in a bit In the interrupt control register. ~~AL INTERRUPT CONTROL BITS L PRESCALER CONTROL BITS START/STOP BIT EDGE DETECT BIT EXTERNAL PULSE WIDTH MODE Loeallnterrupt Control (Bits 0-1)- These modes define the interrupt state of the timer and external interrupts (see table 4). Both interrupts can be enabled at the same time. When both interrupts are enabled, they are serviced on a firstcome, first-served basis. For example, if the timer interrupt arrives later than the unserviced external interrupt, the external interrupt is serviced first, and the timer interrupt remains stored until it is serviced or cleared. If both interrupts arrive at the same cycle, the timer interrupt is handled first. Table 4 F3856 Timer and External Interrupt Modes Bit 1 Bit 0 o o o The internal timer register (TR) and interrupt control register (ICR) are associated with the two high address ports. The TR, depending on various functions, is in one of two modes: stationary or run. In the stationary mode, the contents of the TR remain unaffected. In the run mode, the TR is a binary count-down register, which decrements every 2, 8, 32, or 128 clock time, depending on the value of the two prescaler bits on the ICA. A circuit detects the one-count-to-zero-count transition of the register and stores it in a flip-flop for interrupt purposes. This flip-flop is cleared any time a new value is loaded into TA. 1 o + Function No Interrupt Enable External Interrupt Only Enable Both External and Timer Interrupts Enable Timer Interrupt Only Presealer Control (Bits 2-3)- These bits define one of the four different prescalers for the timer (refer to table 5). 3-44 F3851 Table 5 F3856 Timer Presealer Modes Bit 3 Bit 2 Presealer Value 1 1 0 0 1 0 0 1 2 8 32 128 2. Load TR with an Initial value. Timer Resolution at 2 MHz Timer Period at 2 MHz 1 jls 4jlS 16 jls 64jlS 256jls 1.024 ms 4.095 ms 16.384 ms 3. As soon as the pulse arrives, the timer starts counting and provides the timer interrupts at zero crossing. 4. At the end of the pulse, the timer stops counting and provides an external interrupt, indicating the end of the pulse. The timer contents can now be read under program control for calculating the pulse width. In this procedure, both interrupts are enabled. It is possible to disable one or both interrupts. If the external interrupt is not enabled, the timer stops at the end of the pulse. However, some means of indication are necessary to detect the end of tlie pulse to the main program. If the timer interrupt is not enabled, the timer zero crossing is not detected. If the pulse duration is always short, such that the timer is stopped before reaching zero, it is not necessary to enable the timer interrupt. Start-5top Timer (Bit 4)- This bit controls the TR. When at 0, the TR is in the run mode; when at 1, the TR is in the stationary mode. Edge Detect Con!!E!. (Bit 5)- This bit defines the active edge of the EXT INT input signal as the source during external interrupts. When this bit is at 0, the falling edge is active; when It Is at 1, the rising edge is active. External Pulse Width Mode (Bit 6)-When this bit is at 0, no special function is performed and the interrupts and timer circuits are controlled by bits 0 through 5 of the ICR. However, when this bit is at 1, the special function of pulse width measurement Is performed. When the timer is loaded with a zero count, the timer interrupt does not occur immediately, although the timer is a zero-count. The timer interrupt occurs only after the one-tozero transition during the countdown. Hence, when the timer Is loaded with a zero count, the timer interrupt occurs after 256 timer counts. Pulse Width Measurement The following procedure is used to measure pulse width for the F3856 PSU (refer to fig ure 12). This feature of being able to load a zero count in the timer without getting interrupted allows the programmer to have complete control over the timer count and is also useful during the pulse width measurement mode. 1. Before the pulse arrives, set the ICR as follows: During reset procedures, the ICR is loaded with zero, which disables the local interrupt controls and establishes the trailing edge of the 00 REa input signal as the active edge for the external interrupt. The active edge of the external signal can be changed by bit 5 of the ICR. However, when this bit is changed, and the level appearing on the external signals is of the same level as the one obtained after the new active edge, an external interrupt ,is generated. For example, when changing the active edge of the external signal from trailing edge to riSing edge under program control, if the external signal is already at a high level, an interrupt Is generated. a. Set the external pulse width mode bit to 1. b. Set the edge detect bit to 1 for a negative pulse or to 0 for a positive pulse. c. Set the startlstop bit to 1 (stop mode). d. Set the prescaler bits to the value of prescaler desired. e. Set the interrupt bits to turn on both interrupts. Figure 12 F3856 Pulse Width Measurement ~ SETUP REGISTERS BIT ~ 1 __- +____EDGE DETECT __________ ~~ TIMER STARTS EXTERNAL INTERRUPT ~,4~ > TIMER STOPS EDGE DETECT BIT =0 ~---------~------r----~ EUINT---+--------------------~ 3-45 • F3851 If such interrupts are undesirable, an additional step is necessary to disable the local external interrupt control during the change of ICR bit 5. For example, when loading the ICR for the change of direction, the external interrupt control can be disabled with the same instruction, and the next instruction can then enable it. The service request flip-flop cannot become set if another interrupt request is being acknowledged anywhere in the system. Rather, if an interrupt request has been latched into the timer interrupt flip-flop or the external interrupt flip-flop, the PSU logic waits until after the process of acknowledging the other interrupt has been completed before setting the service request. This precaution is necessary to ensure that the priority chain is not altered during acknowledgement; an error would occur if one half of the interrupt vector came from one device and the second half from some other device. Note that the feature of generating an interrupt by changing bit 5 of the ICR can be used for software (program-generated) interrupts. PSU Intenupt Handling The service request flip-flop is cleared after an interrupt from the PSU has been acknowledged. It is also cleared whenever the interrupt control register for the PSU is accessed by an output instruction. A typical F8 system interrupt interconnection is shown in figure 13. Each PSU and Pia has a PRi iN and a PRI OUT line so that they can be daisy-chained together in any order to form a priority level of interrupts. Depending on the contents of the ICR, the interrupt control logic can be accepting timer interrupts or external interrupts, or neither, but never both. The conditions for setting the timer interrupt flip-flop and the external interrupt flip-flop differ slightly. External interrupts must be enabled before the external interrupt flip-flop can be set by a negative-going transition of the EXT iN'i' signal. However, the timer interrupt flip-flop is set by a timer time-out independent of the timer interrupt enable bit. This means that the PSU can detect a time-out interrupt that is reo quested while the PSU was checking for external interrupts. Figure 14 is a diagram of the PSU interrupt logic. Between the EXT iNT input signal or the time-out input and the iNf REO output Signal, there are three flip-flops. The EXT INT Signal and the time-out interrupt input each have a synchronizing flip-flop and edge detect logic. The timer interrupt flip-flop is cleared whenever the PSU device timer is loaded or when its timer interrupt has been acknowledged. The external interrupt flip-flop is cleared whenever the device interrupt control register is accessed by an output instruction or when its external interrupt has been acknowledged. Each edge detect clock is followed by its own interrupt flipflop that latches the true condition. The outputs of the timer interrupt flip-flop and the external interrupt flip-flop are ORed to set the service request flipflop, providing that an interrupt from some other PSU is not being acknowledged. Interrupt Acknowledge Sequence Upon receiving an interrupt request, whether from an external source through the 00 INT signal or from the internal timer, the PSU and CPU go through an interrupt sequence that ultimately results in the execution of an interrupt service routine located at the memory address indicated by the interrupt address vector. Figures 15 and 16 illustrate the interrupt sequences for the two cases. Events occurring in these sequences are labeled A through H. The INT REO signal is the NAND of priority input and serVice request. This is an open-drain Signal. The iNf REO signal of several PSUs can be tied together so that anyone can force the line to 0 V if it is requesting interrupt service; a pull-up to Voo is provided by the F3850 CPU to the iNf REO input pin. The PRI iN signal is part of the interrupt priority chain. The ch!!i! ~gins by a strap to V~ ~ device in the chain has a PRIIN input signal and a PRI OUT output Signal. The PRI OUT signal of the PSU is active (0 V) only if the PRI iN Signal is active (0 V) and service request is inactive This means that the PRI Q(j"f and iN'i' REO signals are alwl!ls at opposite levels. The PRI OUT Signal becomes the PRI IN signal for the next device in the interrupt priority daisy chain, if there is one. The function of the priority daisy chain is to ensure that just one device at a time is requesting interrupt service. Event A - The initial interrupt request arrives. The falling edge of the EXT INT pin identifies an external interrupt. The rising edge of the interval timer output indicates a time-out. Event 8- The synchronizing flip-flop in the PSU control logic changes state. Event C- The timer or external interrupt flip-flop goes true, indicating the local interrupt logic acknowledgement of the interrupt. The timer interrupt flip-flop always responds and saves the time-out occurrence, whereas the external inter- 3-46 F3851 Figure 13 F8 System Interrupt Interconnection r-__________~C~O~N~T,ROLrL~IN~E~S~----------_, CPU PSUIPIO 1 ICB P$UlPIQ PIO 2 (n) SMI " - - - - - - - - - - - E X T E R N A L INTERRUPT L I N E S - - - - - - - - - - ' Figure 14 Conceptual Illustration of F3851 PSU Interrupt Laalc Note: All FFs are clocked by the WRITE signal. INTERRUPT CONTROL REGISTER IF I, SET BIT 7 OF INTERRUPT ADDRESS VECTOR ~ TO O. IF 0, SET IT TO 1. H'I'J' .,..---........-' TIME·OUT D Q SYNC FF FROZEN PRiiN--D>o---.....t---., '''OPEN COLLECTOR" GATE 3·47 o DURING EVENT G (INTERRUPT SERVICE), 1 OTHERWISE • F3851 rupt flip-flop is set at this time only if the external interrupt mode is enabled within the local control logic. 3. The current instruction fetch is not protected. Event 0- The INT REO line is pulled low by the PSU, Event F- The CPU generates the Interrupt acknowledge sequence of ROMC states. paSSing the request for servicing on to the CPU. The following conditions must be present for this to occur: Event G-At this pOint, the CPU begins fetching the first instruction of the interrupt service routine. In the PSU interrupt logic, the service request flip-flop and the appropriate interrupt request flip-flop have been cleared. 1. The PRIIN pin must be low. 2. The proper enable state must exist in the local control logic for the type of interrupt (timer or external). Event H- The CPU begins executing the first instruction of the interrupt service routine. 3. The system is not already into Event F because of servicing some other interrupt. Interrupt Address Vector During the interrupt acknowledge, the interrupting PSU provides a 16-bit interrupt address vector (refer to figure 17). The CPU causes this vector to be loaded into PCo so that program execution can branch to the routine that handles this particular interrupt. Fifteen bits of the interrupt vector are specified as a mask option. Bit 7 cannot be masked; it is set by the interrupt control logiC to 0 if the timer interrupt is enabled or to 1 if the external interrupt is enabled. Event E- The CPU now begins its response to the INT REO line by transmitting the unique ROMC state H'10'. This occurs only when the following conditions are satisfied: 1. The CPU is executing the last cycle of an instruction (beginning an instruction fetch). 2. The ICB is enabled (ICB = 0). Figure 15 Timer Interrupt Sequence EVENTS WRITE CLOCK TIME-OUT~ SYNC FF _ _ _ _.....I ~----~~~----------~ TIMER INT FF INT REO (TO CPU) ROMC STATE (FROM CPU) ~J~------------~ 10 (US) --.... LONG OR SHORT CYCLE (L) _ LONG CYCLE (S) _ SHORT CYCLE 3-48 1C OF 13 00 F3851 Figure 16 External Interrupt Sequence EVENTS WRITE CLOCK TIME·OUT • ~",,'--_ _ __ SYNC FF ~------~$Sr---------------------' TIMER INT FF ~jr------------~ INT REO (TO CPU) ROMC STATE (FROM CPU) 10 1C OF 13 00 (US) _____ LONG OR SHORT CYCLE (L) ----- LONG CYCLE (S) _ _ SHORT CYCLE Figure 17 Interrupt Address Vector • •.--------------------INTERRUPTADDRESSVECTOR------------------~~~ 15 • t I··· MASK PROGRAMMABLE L 3·49 MASK PROGRAMMABLE 0 FOR TIMER INTERRUPT 1 FOR EXTERNAL INTERRUPT ~ F3851 Interrupt Signal Timing Timing for signals associated with the PSU interrupt logic is shown in figure 18. All signal characteristics are given in the timing characteristics section of this data sheet. Note: Timing measurements are made at valid logic level to valid logic level of the signals referenced unless otherwise noted. Figure 18 PSU Interrupt Timing WRITE ROMC "_ld3_! r---, \ \ / LONG CYCLE X STABLE -1"1 .. Ir, .. I 2V ~tPd3~1. _IPd'-z!. ;; --- - ~tpr2~ tpr1 ~lpd1~ .....-t 1,,_ .1_ Pd2-.! /' 2V """.. .. tSB1 STROBE • 1562 3·50 . F3851 Timing Characteristics The timing characteristics of the PSU devices are described in table 6. The ac characteristics are Vss = 0 V, Voo = +5.0 V ±5%, VGG = +12 V±5%, TA=O·C to +70·C, unless other· wise specified. Table 6 PSU Signal Timing Characteristics Symbol Parameter pt PW1 td1, td2 td4 PW2 PWs PWl td3 td7 td s tr1 tr2 tpr1 tpd 1, tpd2 tpd3, tpd 4 tsp tad tdP tsu th lex tsB1 tsB2 Min. + Period + Pulse Width + to Write + Delay WRITE to DB Input Delay WRITE Pulse Width WRITE Period; Short WRITE Period; Long WRITE to ROMC Delay WRITE to DB Output Delay WRITE to DBDR - Delay WRITE to ~R + Oelay WRITE to ~ REQ - Delay WRITE to INT REQ + Delay PAliN to INT REQ - Delay PRj iN to PAl OUT Delay Typ. Max. 0.5 180 10 PH80 250 2P++1.0 pt pt-100 ~H~Time ~s ns ns t r, tf = 50 ns typo Cl=100 pF ~s t r, tf = 50 ns typo ns ns ns 2P++100-td2 CI =100 pF 800 ns ns ns ns ns Open drain Cl = 100 pF(1) CI =100 pF(3) Cl=100 pF(2) Cl=50pF 600 ns Cl=50pF ~ Cl = 50 pF, standard pull·up(3) Cl = 50 pF, Rl = 12.5 kQ, open drain(5) C l = 50 pF, driver pull·up 2pt+200 550 2pt +850-td2 200 430 430 200 1.0 2.5 400 200 ~ ns 1.3 0 400 ~ WRITE to STROBE + Delay WRITE to STROBE - Delay 5P++300 6P++410 ns ns ns ns Cl=50pF Cl=50pF Not•• 1. 2. 3. 4. Assume priority In was enabled (PRI iN =0) In the previous F8 cycle, before the Interrupt Is detected In the PSU. The PSU has an Int~p.!..e!nding before priority In Is enabled. Assume pin tied to INT REO Input of the F3850 CPU. Input and output capacitance Is 3 to 5 pF, typical, on all pins except vpp, VGG, and vss. DC Characteristics The dc characteristics of the PSU devices are provided in tables 7 and 8. Supply Currents Vss = 0 V, Voo Symbol Parameter Voo Current VGG Current • ns WRITE to Output Stable WRITE to Output Stable EXT INT Set·up Time Test Conditions 4P+ WRITE to PRI OUT Delay WRITE to Output Stable I/O Set·up Time Units =+5 V ±5%, VGG = + 12 V ±5%, TA =O·C, + 7O·C Min. Typ. Max. Units 28 10 60 30 rnA rnA 3-51 Test Conditions f = 2 MHz, outputs unloaded f = 2 MHz, outputs unloaded F3851 Table 7 F3851 PSU DC Characteristics Symbol VIH VIL VOH VOL IIH IOL VIH VIL IL VIH VIL IL VOH VOL VOH VOL IL VOH VOL IL VIH VIL VIC IIH IlL IlL VOH VOH VOL VIH VIL IL IlL VOH VOL VIH VIL IlL VOH VOL Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input High Voltage Input Low Voltage Leakage Current Input High Voltage Input Low Voltage Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Leakage Current Output High Voltage Output Low Voltage Leakage Current Input High Voltage Input Low Voltage Input Clamp Voltage Input High Current Input Low Current Input Low Current Output High Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Leakage Current Input Low Current Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Leakage Current Output High Voltage Output Low Voltage Signal Data Bus (DBa -DB7) Min. 2.9 Vss 3.9 Vss Max. Voo 0.8 Voo 0.4 1.0 -1.0 Units V V V V lolA lolA Clock Lines (+. WRITE) 4.0 Vss Voo 0.8 3.0 Prlority...!!l '!!:!.d Control Lines (PRI IN. ROMCo ROMC,.) Priority out (PRI OU1) 3.5 Vss Voo 0.8 3.0 3.9 Vss Voo 0.4 Vss· 0.4 3.0 lolA 0.4 3.0 lolA 1!2!!rr:!!.E!.Request (INT REO) ~!!!!..Interrupt 3.5 (EXT IN1) 110 Port Option A (Standard Pull·up) -150 3.9(5) 2.9 Vss 2.9(3) Vss 110 Port Option B (Open Drain) 110 Port Option C (Driver Pull-up) 0.8 15 10 -225 -500 Voo Voo 0.4 Voo 0.8 1.0 -1.6 IOH = -100 lolA IOL=1.6 mA VIN = Voo • 3-state mode VIN = Vss. 3-state mode V V lolA VIN=VOO V V lolA V V V V Data Bus Drive (DBDR) Vss Test Conditions V V V V lolA lolA lolA V V V V V lolA mA Vss 2.9(3) Vss 0.4 Voo 0.8 2.0 lolA 3.75 Vss Voo 0.4 V V V V V VIN =Voo IOH = -100 lolA 10L = 100 lolA Open-drain output(1) 10L =1 mA VIN =Voo External pull·up IOL=2 mA VIN=VOO IIH = 185 lolA VIN=VOO VIN =2V VIN=VSS 10H = - 30 lolA IOH = -150 lolA IOL=1.6 mA Internal pull·up to Voo(3) VIN=VOO VIN=0.4 V(4) External pull-up IOL=2 mA (3) VIN = +12V 10H= -1 mA IOL=1.6 mA Note. 1. 2. 3. 4. 5. Pull·up resistor to Voo on CPU. Positive current Is defined as conventional current flowing Into the pin referenced. Hysteresis Input circuit provides additional 0.3 V noise immunity while Internal/external pull-up provides TTL compatibility. Measured while I/O port is outputting a high level. Guaranteed but not tested. 3-52 F3851/F3856 Table 8 F3856 PSU DC Characteristics Symbol VIH VIL VOH VOL IIH IOL VIH VIL IL VIH VIL IL VOH VOL VOH VOL IL VOH VOL IL VOH VOL VIH VIL IlL VOH VOH VOL VIH VIL IlL VOH VOL VIH VIL VOH VOL Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input High Voltage Input Low Voltage Leakage Current Input High Voltage Input Low Voltage Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Leakage Current Output High Voltage Output Low Voltage Leakage Current Input High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Low Current Output High Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Low Current Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Signal Min. 2.9 Vss 3.9 Vss Data Bus (DBa -DB7) Clock Lines (+, WRITE) 4.0 Vss Priority In and Control Lines (PRI IN, ROMCo ROMC4) Priority out (PRI OUn Max. Voo 0.8 Voo 0.4 3.0 -3.0 Voo 0.8 3.0 3.5 Vss Voo O.S 3.0 3.9 Vss Voo 0.4 Vss 0.4 3.0 Vss 0.4 3.0 3.9 Vss 2.9 Vss Voo 0.4 1~~Request (INTREQ) Units V V V V jAA lolA V V lolA V V lolA V V V V lolA Data Bus Drive (DBDR) Strobe External Interrupt (EXT INn 1/0 Port Option A (Standard Pull-up) 3.9 2.9 Vss 2.9 Vss 1/0 Port Option B (Open Drain) Vss 2.9 Vss 4.0 Vss 1/0 Port Option C (Driver Pull-up) Voo 0.8 -1.6 Voo Voo 0.4 Voo O.S -1.6 0.4 Voo 0.8 Voo 0.4 V lolA V V V V mA V V V V V mA V V V V V Test Conditions IOH = -100 lolA IOL=1.6mA VIN = Voo, 3-state mode VIN = Vss, 3·state mode VIN=VOO VIN =Voo 10H = -100 lolA IOL=l00lolA Openand WRITE signals, which are input from the F3850 CPU. Refer to the F3850 data sheet for a description of these clock signals. The WRITE clock refreshes and updates PIO registers, which are dynamic. The 4> clock also drives the programmable timer. The interrupt logic responds to an interrupt request signal originating from internal timer logic or an external device. Based on priority considerations, the interrupt request is passed on to the F3850 CPU. The programmable timer uses a polynomial shift register in conjunction with interrupt logic to generate real·time intervals. 110 Ports Signal Descriptions The F3861 input and output signals are described in table 1. The PIO has two bidirectional 8·bit 1/0 ports used to transmit data between itself and external devices. in binary notation, the address for port A is XXXXXXoo and for port B is XXXXXX01, where the X binary digits are the unique 1/0 port select code for the PIO (see table 2). For example, if the port select code is 000001, port A may be called port 4 and port B may be called port 5. (The PIO port select code is never designated as all Os, since ports 0 and 1 are reserv· ed for the F3850 CPU.) In addition, the interrupt control Port (ICP) is addressed as port XXXXXX10 and the binary timer is addressed as port XXXXXX11, which become ports 6 and 7, respectively, for the port select code example given above. Figure 1 F3861 Block Diagram Table 2 F3861 Port Addresses The 8·bit data bus in the PIO is the main path for transfer of information between the F3850 CPU and other devices in the F8 microprocessor system. The device contains four preassigned 1/0 port addresses: the two lowest are assign· ed to the two 1/0 ports (A and B) and are used to tranfer data to and from external devices. The other two 1/0 ad· dresses are assigned to two internal registers of the PIO that control interrupt logic and are treated as 1/0 ports. 110 PORT A 110 PORT A OUTPUT STROBE 110 PORT B DATA BUS 110 PORT B ADDRESS ASSIGNED TO XXXX XXXX XXXX XXXX 1/0 Port A 1/0 Port B Interrupt Control Register Programmable Timer XXOO XX01 XX10 XX11 DBDR INTERRUPT VECTOR ADDRESS PROGRAMMABLE TIMER ROM The port and interrupt address vector assignments are given in table 3. CONTROL LINES . . - - EXTERNAL INTERRUPT INTERRUPT CONTROL INTERRUPT LOGIC ~ Table 3 F3861 Port and Address Assignments (HEX) PRIORITY IN PRIORITY OUT Version INTERRUPT REQUEST F3861A F3861B F3861C F3861D F3861E 3·56 Port Addresses 4·7 8·B 20·23 24·27 4·7 Interrupt Address Vector Timer 0600 0340 0320 0360 0020 External 068C 03CO 03AO 03EO ooAO F3861 Table 1 F3861 Signal Descriptions Mnemonic Pin No. Name Description Clock 4> WRITE 8 7 Clock The two clock input signals originate at the F3850 CPU. 19,24, 25, 30 31,36 37, 2 I/O Ports A Bidirectional ports through which the Pia communicates with logic external to the microprocessor system. 20,23, 226,29, 31,35, 38, 1 I/O Ports B 17,16, 15,14, 13 Read Only Memory Control Input signals that originate at the F3850 CPU and control internal functions of the Pia. 21,22, 27,28, 33,34, 39, 40 Data Bus Bidirectional three·state lines that link the Pia to all other devices within the microprocessor system. 11 Data Bus Drive A low output, open drain signal that indicates the data bus currently contains data flowing from the Pia. EXTINT 5 External Interrupt A high·to·low transition on this input signal is interpreted as an interrupt request from an external device. --INT REO 9 Interrupt Request This output signal is the INT REO input to the F3850 CPU; it must be output low to interrupt the CPU, which occurs only if PRI IN is low and Pia interrupt control logic is requesting an interrupt. PRiiN 10 Priority In Unless this input Signal is low, the Pia does not set the INT REO signal low in response to an interrupt. PRIM 6 Priority Out This output signal becomes the PRI IN signal to the next device in the interrupt'priority daisy chain; it is output high unless the PRI IN signal is entering the Pia low and the Pia is not requesting an interrupt. Power Voo 4 Power Supply 5V(± 5%) VGG 3 Power Supply +12V(± 5%) Vss 18 Ground System ground-O V; Voo and VGG are referenced to Vss. 1/0 Ports I/0AqI/O A7 -- I/O So I/O B7 Control ROMCo ROMC4 Data Bus DSo DB7 DBDR II !.!!!!r~t 3·57 3 F3861 Port Pin Description An output instruction (OUT or OUTS) causes the contents of the CPU accumulator (ACC) to be latched into the addressed port. An Input instruction (IN or INS) transfers the contents of the port to the ACC (port 6 is an exception that is described later). The I/O pins on the PIO are logically inverted; the schematic of an 1/0 pin and available output drive options are shown in figure 2. Each output pin has an output latch that holds the data last output to that pin_ The 1/0 ports of the PIO are configured in the standard pull-up option. When outputting data through an I/O port, the pin can be connected directly to a TTL gate input; data is input to the pin from a TTL device output. Since the I/O pin and the TTL device output are wire-ANDed, It is possible for the state of one to affect the transfer of data out from the 1/0 pin or In from the TTL device output. In most cases, therefore, 1/0 port bits should be set for a high level (logic 0) before data input to prevent incoming logic zeros from being masked by logic ones present at the port from previous outputs. However, the ability to mask bits of a port to logic 1 is useful during some Input functions. Programmable Timer Figure 2 1/0 Pin Diagram with Output Buffer Options The 8-bit shift register, addressable as an I/O port, functions as a polynomial timer. This timer is loaded with a value of delay; it counts down this value of delay and, after the programmed interval, generates an interrupt through the interrupt logic of the PIO. z 0 ;:: TIL '" l- I- 0 0 C Q PORT PIN .. .. clock periods) in ail cases except where B is the decrement scratchpad instruction, in which case. the freeze cycle is a long cycle (six clock periods). Figure 5 details the interrupt sequence that occurs, whether the interrupt request is from an external source through the EXT INT pin or from the PIO device internal timer. Events are labeled A through G. Event A An interrupt request must satisfy a set-up time requirement. If not satisfied, the INT REO signal delays going low until the next negative edge of the WRITE clock. The INT REO signal goes low on the next negative edge of the WRITE signal if both the PRi iN signal is low and the appropriate interrupt enable bit of the ICP is set. Event B Event B represents the instruction being executed when the interrupt occurs. The last cycle of B is normally the instruction fetch for the next cycle. However, if B is not a privileged instruction and the CPU interrupt control bit Is set, the last cycle becomes a freeze cycle raher than a fetch. At the end of the freeze cycle the interrupt request latches are inhibited from altering the interrupt daisy chain so that sufficient time is allowed for the daisy chain to settle. Event C This is a no-operation (NO-OP) long cycle, allowing time for the PRI IN/PRI OUT chain to settle. At a 2-Mhz clock rate, a total of seven PIO, PSU, or MI devices can be daisychained without the need for look-ahead lOgic. Event D In PSU circuits, the program counter (PO) is pushed to the stack register (P) to save the return address. The Interrupting PIO places the lower eight bits of the interrupt vector address onto the data bus. This is always a long cycle. If B is a privileged instruction, the instruction fetch is not replaced by a freeze cycle; Instead, the fetch is performed and the next instruction is executed. Although unlikely to be encountered, a series of privileged instructions would be executed sequentially. One more instruction (a protected instruction) is executed after the last privileged instruction. The last cycle of the protected instruction then performs the freeze. Figure 5 Event E In this long cycle, the PIO places the upper eight bits of the interrupt vector address onto the data bus. Interrupt Sequence FREEZE CYCLE WRITE -1 ~III 1 --';'1-I - - 1--f-lI A EXT INT OR TIMER INTERRUPT 4--- i rl' PRI oUT -I 1 ------~! ~ __ J PRI OUT OF NEXT PIO _ _ ~ .;.I__Ir"_ -I-J ___ 3-61 F3861 Table 4 PIO Functions Versus ROMC States Event F In this short cycle, the PIO interrupting interrupt request latch Is cleared. Also, the CPU interrupt control bit is cleared, thus disabling interrupts until an EI instruction is performed. Additionally, during Event F, the PRI tN/PRI OUT daisy-chain freeze is removed, since the interrupt vector address has been passed to the CPU. Another action is the fetch of the instruction from the interrupt address. ROMC State Hex Binary Event G This event starts executing the first instruction of the interrupt service routine. Summary of Interrupt Sequence For the PIO, the interrupt response time is defined as the time elapsed between the occurrence of the 00 jjij'j'signal going active (or the timer transition to H'N') and the beginning of execution of the first instruction of the interrupt service routine. The interrupt response time is a variable dependent on what the microprocessor is doing when the interrupt request occurs. PIO Functions 01111 OF If this circuit is interrupting and is highest in the priority chain, move lower half of interrupt vector into the data bus. 10000 10 Place interrupt circuitry in an inhibit state that prevents altering the interrupt priority chain. 10011 13 If the contents of the data bus in the prior cycle was an address of 1/0 ports on this device, move the current contents of the data bus into the appropriate port (1/0 A, 110 B, timer or control). 11011 1B If the contents of the data bus in the prior cycle was an address of 110 ports on this device, move the contents of the appropriate 1/0 port onto the data bus (110 A or 110 B). As shown in figure 5, the minimum interrupt response time is three long cycles plus two short cycles plus one write clock pulse width plus a set-up time of an EXT INT signal prior to the leading edge of the write pulse, a total of 27 clock periods plus the set-up time. At 2 MHz, this is 14.25 jAs. Although the maximum could theoretically be infinite, a practical maximum is 35 JAS (based on the interrupt request occurring near the beginning of a PI and LR K, P sequence). + Timing Characteristics ROMC States Timing signals are illustrated in figures 3, 6, and 7; the signal timing characteristics are presented in table 5. Table 4 shows the function performed by the PIO device for each ROMC command. Each function is performed entirely within one machine cycle (one cycle of the WRITE clock). All other ROMC states are decoded as NO-OP. Figure 6 F3861 InputlOutput Timing WRITE --.I \~--~JrJ--------~j j---tsu--l INPUT (1) ----------~------------DATA MAY CHANGE DATA STABLE tSP---j OUTPUT (2) ------------~ (STANDARD \ PULL.UP) ~ .....+-" STABLE 2.9 V 3-62 \---------f--th--j i.---------DATA MAY CHANGE F3861 Figure 7 F3861 Interrupt Logic Timing ~--------'/ ROMC I \, I « LONG CYCLE STABLE 1------tr2-----.j ~------------------------~----t-~--4~ tpr~ r-- EXT INT ------------------------------~\ tex ~---------------------Note: Timing measurements are made at valid logic level to valid logic level of the signals references, unless otherwise noted. 3-63 F3881 Table 5 F3861 Timing Characteristics The ac characteristics are VSS = OV, VCC = + 5V( ± 5%), TA = 0 C to + 70· C. Symbol Parameter Min PII> PW1 td 1 td 2 td4 PW2 PWs PW L td 3 II> Period II> Pulse Width II> to WRITE + Delay II> to WRITE - Delay WRITE to DB Input Delay WRITE Pulse Width WRITE Period; Short WRITE Period; Long WRITE to ROMC Delay WRITE to ~utput Delay WRITE to DBDR - Delay WRITE to DBDR + Delay WRITE to INT REO - Delay WRITE to INT REO + Delay PRI IN to INT REO - Delay PRIIN to INT REO + Delay PRI IN to PRI OUT - Delay PRI IN to PRI OUT + Delay WRITE to PRI OUT + Delay WRITE to PRi OUT - Delay WRITE to Output Stable 0.5 180 60 60 I/O Setup Time I/O Hold Time EXT INT Setup Time 1.3 0 400 td7 tds tr1 tr2 tpr1 tpr2 tpd 1 tpd2 tpd3 tpd4 "tsp "tsu *th '*tex Typ PII>-100 Max Units Test Conditions 10 PII>-180 250 225 2PII>+ 1.0 Pell 5IAs ns ns ns lAs ns 550 ns 2PeIl+850-t~ 430 430 240 240 ns ns ns ns ns ns CL = 100 pF Open Drain CL = 100 pF(1) CL = 100 pF (3) CL = 100 pF (2) CL = 100 pF 365 700 640 2.5 ns ns ns lAS CL =50 pF CL =50 pF CL =50 pF CL = 50 pF Standard Pull-up t~ t f = ns typo CL = 100 pF Ct.. = 100 pF t~ t f = 50 ns typo 4PeIl 6PeIl 2P<1> + 100 - td 2 2P<1> + 200 200 lAs ns ns Notes: 1. Assume Priority In was enabled (PRI iN = 0) in the previous FS cycle before the interrupt is detected In the PIO. 2. The PSU has an interrupt pending before priority in is enabled. 3. Assume the pin is tied to the iN'f REO input of the F3850 CPU. 4. The starred * parameters In the table represent those most frequently of importance when interfacing to an FS system. Other parameters are typically those that are relevant between FS chips and are not normally of concern to the user. 5. Input and output capacitance is 3 to 5 pF typical on all pins except VOO ' VGG , and VSS. 3-64 F3861 DC Characteristics The dc characteristics of the F3861 PIO are supplied in table 6. Table 6 F3861 PIO DC Characteristics Symbol Parameter Signal Min Max Units VIH VIL VOH VOL IIH 10L Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Data Bus (OBO-OB7) 3.5 Vss 3.9 Vss Voo 0.8 Voo 0.4 1 -1 V V V V ,..A ,..A 10H -1oo,..A 10l = 1.6 mA VIN = 6V, 3-State mode VIN = Vss ,3-State mode VIH VIL IL Input High Voltage Input Low Voltage Leakage Current Clock Lines (eII,WRITE) 4.0 Vss Voo 0.8 1 V V ,..A VIN = 6V VIH Vil Il Input High Voltage Input Low Voltage Leakage Current Priority In and Control Lines (PRI IN, ROMCOROMC4) 3.5 Vss Voo 0.8 1 V V ,..A VIN = 6V VOH VOL Output High Voltage Output Low Voltage Priority Out (PRI OUT) 3.9 Vss Voo 0.4 V V 10H = -1oo,..A 10L 1oo,..A VOH VOL Il Output High Voltage Output Low Voltage Leakage Current I~rupt Request (INT REQ) Vss 0.4 1 V V ,..A Open Drain Output (1) IOL=1mA VIN = 6V VOH VOL IL Output High Voltage Output Low Voltage Leakage Current Data Bus Drive (DBDR) Vss 0.4 1 V ,..A External Pull-up IOl=2mA VIN 6V VIH VIL VIC IIH IlL III Input Input Input Input Input Input ~n~lnterrupt 3.5 VOH VOH VOL VIH VIL IlL Output High Voltage Output High Voltage Output Low Voltage III IL High Voltage Low Voltage Clamp Voltage High Current Low Voltage Low Current (EXT INT) -150 I/O Port (Standard Pull-Up) 3.9 2.9 Vss 2.9 Vss Input High Voltage Input Low Voltage Leakage Current, DC/PC Leakage Current, OC/PUOM Input Low Current 1.2 15 10 -225 -500 V V V ,.. ,..A ,..A V V Test Conditions = = = IIH = VIN = VIN = VIN = = 10H -30,..A 10H = -100,..A Voo Voo 0.4 Voo 0.8 -1.6 V V V mA VIN = 0.4 V -2.0 mA VIN = 0.4 V -1.6 mA VIN Vss (4) (7) 10l = 2mA Internal Pull-up to Voo (3) Notes: 1. Pull-up resistor to Voo on CPU. 2. Positive current is defined as conventional current flowing into the pin referenced. 3. Hysteresis input circuit provides additional 0.3 V noise immunity while internal/external pull-up provides TTL compatibility. 4. Measured an K a high-level I/O port OUT port. 5. Vss = ·V. Voo = ±5V ± 5%, VGG = + 12V ±5'10, TA = O'C to 70'C 6. Output device off. 7. - 2.0 rnA for extended temperature range. 3-65 185,..A Voo 2V Vss F3861 The supply currents are given in table 7. Table 7 Supply Currents Symbol Parameter IDD IGG VDD Current VGG Current Min Typ Max Units 30 10 70 18 mA mA Test Conditions F f = 2 MHz, Outputs Unloaded = 2 MHZ, Outputs Unloaded Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device leliability, and exposure to stresses greater than those listed may cause permanent damage to the device. VGG VDD External Interrupt Input All Other Inputs and Outputs Storage Temperature Operating Temperature +15V, -0.3V +17V, -0.3V - 600 !-lA, + 225 !-lA + 7 V, -0.3 V -55·C, + 150· C O·C, + 70·C Note All voltages are' with respect to vss' Recommended Operating Ranges Supply Voltage CI DD) Part Number F3861 Min Typ + 4.75 V +5V Max + 5.25 V Min Typ + 12 V +11.4V Max + 12.6 V Vss OV Ordering Information Part Number Package Temperature Range F3861 F3861 DM *F3861 PC Ceramic Ceramic Plastic C M = C Commericial Temperature Range O· to + 70·C L = Limited Temperature Range - 40·C to + 85·C M Military Temperature Range - 55·C to + 125·C * Version A, B, C, D, and E are stocked items. = C 3·66 F3871 Peripheral Input/Output FAIRCHILD A Schlumberger Company Microprocessor Product Connection Diagram Description The Fairchild F3871 Peripheral Input/Output (PIO) device provides two 8-bit 1/0 ports, external interrupt, and a programmable timer. An 8-bit-wide bidirectional data bus transfers 1/0 data bytes between the F3870 Central Processing Unit (CPU) and the PIO. 17087 DB, 1/0 A, The PIO is used in systems that require the 1/0 capability and interrupt functions of the F3851 PSU, but do not need the read-only memory (ROM) storage of the PSU. The PIO is pin-compatible with the PSU. Oils VGG 1/086 Voo iIO.A;i 110 EXTiiiii' PRi OUT DB, WRITE The F3871 has the same improved timer and ready strobe output as the F3870 CPU; therefore, for software compatibility with the F3870, the F3871 PIO should be used in the F8 multichip configurations. DB. '" INT REO The F3871 is manufactured using isoplanar N-channel silicon-gate technology; therefore, power dissipation is very low (less than 200 mW). • 16 Bidirectional, Individually Controlled 1/0 Lines Organized as Two B-Bit Ports .110 Strobe • Programmable TImer- Preset, Start, Stop, and ReadBack Ability: Selectable Timer Count Rates • Full Interrupt Level- Daisy-Chain Expandable, Independent Interrupt Address Vectors for Timer and External Interrupt • Pulse Width Measurement Capability • +5 V and +12 V Power Supplies .2 MHz Operation • TTL and LSTTL Compatible • Low Power Dissipation, Typically Less Than 200 mW 3·67 AS 1/086 110 a. A.; PRim 10 110 DBDR 11 110 A; STROBE 12 110 ROMC, 13 ROMC, 14 ROMC2 15 ROMC, 16 ROMCo 17 Yss 18 I/OAO 19 II0Bo 20 a, DBo F3871 Signal Functions DATA BUS ROMC, ROMC. ROMC. ROMC. Figure 1 F3871 Block Diagram 1/0 PORTA 1/0 PORT B OUTPUT STROBE 1/0 PORTA 110 PORT B DATA BUS DBDR INTERRUPT VECTOR ADDRESS PROGRAMMABLE TIMER ROM CONTROL LINES EXTERNAL INTERRUPT INTERRUPT CONTROL INTERRUPT LOGIC PRIORITY IN PRIORITY OUT INTERRUPT REQUEST Voo VOO GND • WRITE 3·68 F3871 Table 1 F3871 Signal Descriptions Pin No. Name Description 8 7 Clock The two clock input signals that originate at the F3850 CPU. 19,24,25, 30,31,36, 37,2 20,23,26, 29,31,35, 38,1 110 Ports A Bidirectional ports through which the PIO communicates with logic external to the microprocessor system. 17,16,15, 14, 13 Read-Only Memory Control Input signals that originate at the F3850 CPU control internal functions of the PIO. 21,22,27, 28,33,34, 39,40 Data Bus Bidirectional 3-state lines that link the PIO to all other devices within the microprocessor system. DBDR 11 Data Bus Drive A low output, open drain signal that indicates the data bus currently contains data flowing from the PIO. Strobe STROBE 12 Strobe Provides a sin~ow~tput pulse after valid data is present on 110 Ao-1I0 A7 during an output instruction. Interrupt EXTINT 5 External Interrupt A high-to-Iow transition on this input signal is interpreted as an interrupt request from an external device. INTREO 9 Interrupt Request This output signal is the INT REO input to the F3850 CPU; it must be outp.ut low to interrupt the CPU, which occurs only if PRIIN is low and PIO interrupt control logic is requesting an interrupt. PRIIN 10 Priority In Unless this input signal is low, the PIO will not set the INT REO signal low in response to an interrupt. PRIOur 6 Priority Out This output signal becomes the PFiTTN signal to the next device in the interrupt-priority daisy chain; it is output high unless the PRI IN signal is entering the PIO low and the PIO is not requesting an interrupt. Vee 4 Power Supply +5 V (±5%) VGG 3 Power Supply +12 V (±5%) Vss 18 Ground System ground-O V; Vee and VGG are referenced to Vss. Mnemonic Clock + WRiTE 110 Ports 110 Ao-I/O A7 11080-110B7 Control ROMCo-ROMC4 Data Bus D80-DB7 I/O Ports B Power 3-69 F3871 Device Organization Table 2 The peripheral input/output device Includes 110 logic, timer logic, interrupt logic, data bus logic, and control logic, as illustrated in figure 1. The interrupt logic responds to an interrupt request signal originating from Internal timer logic or an external device. Based on priority conSiderations, the interrupt request is passed on to the F3850 CPU. Address Assigned To XXXXXXOO XXXXXXOl XXXXXX10 XXXXXXll 110 Port A 110 Port B Interrupt Control Register Programmable Timer The port and interrupt address vector aSSignments for the F3871 are given in table 3. The programmable timer uses a polynomial shift register in conjunction with interrupt logic to generate real·time Intervals. Table 3 The Soblt data bus In the PIO is the main path for transfer of information between the F3850 CPU and other devices in the Fa microprocessor system. The device has four preassigned I/O port addresses: the lowest two are assigned to the two 110 ports, A and B, and are used to transfer data to and from external devices. The other two 110 addresses are assigned to two internal registers of the· PIO that control Interrupt logic and are treated as 110 ports. F3871 Port and Address Assignments (HEX) Port Port Interrupt Add..... Vector Version Addresses Output Type Timer 3871E 3871F 3871G 3871H 4-7 4-7 4":7 8-B Standard Direct Drive Open Drain Standard 0020 0020 0020 4420 External OOAO OOAO OOAO 44AO Port Pin Description An output instruction (OUT or OUTS) causes the contents of Signal Descriptions the CPU accumulator (ACC) to be latched into the address· ed port. An Input instruction (IN or INS) transfers the con· tents of the port to the ACC (port 6 is an exception that is described in the "Timer and Interrupt Control Port" section). The 110 pins on the PIO are logically inverted; the schematic of an 110 pin and available output drive options are shown in figure 2. Each output pin has an output latch that holds the data last output to that pin. The 110 ports of the PIO are configured in the standard pull-up option. The F3871 input and output signals are described In table 1. System Clock TIming + All timing within the PIO is controlled by the and WRITE signals input from the F3850 CPU. (Refer to the F3850 data sheet for a description of these clock signals.) The WRITE clock refreshes and updates'PIO registers, which are dynamic. The clock drives sequencing logic to precharge interrupt logic. The clock also drives the programmable timer. + F3871 PIO Port Addresses The STROBE output is always configured in a manner simi· lar to a standard output, except that it is capable of driving three TTL loads. + 1/0 Ports Each 110 port pin is a wire-AND structure between an internal output data latch and the external signal. The latch is loaded from the data bus. The output latches are not initial· ized by the system reset sequence. The PIO has two bidirectional Sobit 110 ports used to transmit data between it and external devices. In binary notation, the address for port A is XXXXXXOO and for port B is XXXX· XX01, where the X binary digits are the unique 110 port select code for the PIO (see table 2). For example, if the port select code is 000001, port A can be called port 4 and port B can be called port 5. (The PIO port select code is never deSignated as all "O"s, since ports 0 and 1 are reserved for the F3850 CPU.) In addition, the interrupt control port (ICP) is addressed as port XXXXXX10 and the binary timer is addressed as port XXXXXXll, which become ports 6 and 7, respectively, for the port select code example just given. When transmitting data through an 110 port, the pin can be connected directiy to a TTL gate input; data is input to the pin from a TTL device output. Since the 110 pin and the TTL device output are wlre-ANDed, it is possible for the state of one to affect the transfer of data out from the 110 pin or in from the TTL device output. In most cases, 110 port bits should, therefore, be set for a high level (logiC 0), before data input, to prevent incoming logic "O"s from being masked by logic "l"s present at the port from previous outputs. However, the ability to mask bits of a port to logic 1 is useful during some input functions. 3·70 F3871 Agure 2 F3871 1/0 Pin Diagram with Output Buffer Options z0 ;: "'" TTL I/O OJ "ii:z 0 0 a: ~ ~ :! PORT PIN .... ....a: . .. a: 0 0 0 0 "a:w g" I; OPEN DRAIN OUTPUT STANDARD OUTPUT DIRECT DAIVE OUTPUT Figure 3 F3871 Timer and Interrupt Control Port Block Diagram PRESCALER ;-2, 5, 10, 20, 40, 100, or 200 INTERaUPT CONTROL PORT (PORT XXXXXX10) EVENT COUNTER MODE _ _ ., 2 PRESCALE __ ., 5 PRESCALE __ ., 10 PRE SCALE __ -;- 20 PRE SCALE ~ o 40 PRE SCALE __ ., 100 PRESCALE __ ., 200 PRESCALE __ 4IJ~~2~~i L L~X:~TR::~ INTERRUPT ENABLE TIMER INTERRUPT ENABLE EXT INT ACTIVE LEVEL START/STOP TIMER - - - - - . PULSE WIDTH/INTERVAL TIMER 3·71 F3871 3. On the trailing edge transition of the EXT INT pin, when in the pulse width measurement mode. Strobe An output ready strobe is associated with port A. This flag is used to signal a peripheral device that the F3871 has just completed an output of new data to port A. Since the strobe provides a single low pulse shortly after the output operation is completed, either edge can be used to signal the peripheral. The STROBE signal is also used as an input strobe by performing a dummy output of H'oo' to port A after completing the input operation. An OUT or OUTS instruction to the timer loads the contents of the accumulator (the interval value) to both the timer and the 8-bit modulo-N register, resets the prescaler, and clears any previously stored timer interrupt request. The timer is clocked by the prescaler in the interval timer mode and in the pulse width modulator mode; the prescaler is not used in the event counter mode. The modulo-N register is a buffer that saves the value most recently output to port XXXXXX11 and is used in all three timer modes. Timer and Interrupt Control Port The timer is software-programmable to operate in one of three modes: the interval timer mode, the pulse width measurement mode, and the event counter mode. As shown in figure 3, an 8-bit register (interrupt control port), a programmable prescaler, and an 8-bit modulo-N register are associated with the timer. Interval Timer Mode When ICP bit 4 is cleared (logic 0) and at least one prescale bit is set, the timer operates in the interval timer mode. When bit 3 of the ICP is set, the timer starts counting down from the modulo-N value. After counting down to H'01', the timer returns to the modulo-N value at the next count. On the transition from H'01' to H'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch is set by the transition of H'N' in the timer, thus allowing a full 256 counts if the modulo-N register is preset to HOO: The desired timer mode, prescale value, timer start and stop, active level of the external interrupt pin, and local interrupt enable or disable are selected by the proper bit configuration output from the accumulator to the interrupt control port (port XXXXXX10), with an OUT or OUTS instruction. If bit 1 of the ICP is set and the P'RiIN signal is low, the interrupt request is passed to the F3850 CPU. However, if bit 1 of the ICP is a logic 0, the interrupt request is not passed on to the CPU. If bit 1 is subsequently set, the interrupt request is then passed to the CPU. Only two events reset the timer interrupt request latch: 1. Acknowledgement by the CPU of the timer interrupt request. Interrupt Control Port A special situation exists when reading the ICP with an IN or INS instruction. The accumulator is not loaded with the contents of the ICP; instead, accumulator bits 0 through 6 are loaded with "O"s, while bit 7 is loaded with the logic level being applied tothe EXT INT pin, thus determining the status of the EXT INT signal without servicing an external interrupt request. This capability is useful in two ways: establishing a high-speed polled handshake procedure and using the EXT INT pin as an extra input pin if external interrupts are not required and if the timer is used only in the interval timer mode. However, if it is desirable to read the contents of the ICP, one of the 64 scratch pad registers is used to save a copy of material written to the ICP. 2. Performance of a new load operation of the modulo-N register. (The interrupt priority sequence is discussed in the "Interrupt Sequence" section.) For example, if the modulo-N register is loaded with H'64' (decimal 100), the timer interrupt request latch is set at the 100th count following the timer start, and the timer interrupt request latch is repeatedly set on precise 10o.count intervals. If the prescaler is set at + 40, the timer interrupt request latch is set every 4000 clock periods. For a 2 MHz 4 clock, this setting produces 2 ms intervals. The timer clock rate in the interval timer mode is determined by the frequency of the clock and by the division value selected for the prescaler. If ICP bit 5 is set and bits 6 and 7 are cleared, the prescaler divides by two. If bit 6 or 7 is individually set, the prescaler divides by five or twenty, respectively. Combinations of bits 5, 6, and 7 can also be selected. For example, if bits 5 and 7 are set while 6 is cleared, the prescaler divides by 40. Thus, possible prescaler values are +2, +5, +10, +20, +40, +100, and +200. + + + + + The range of possible intervals is from 2 to 51,200 clock periods (1 ,..s to 25.6 ms for a 2 MHz clock). However, approximately 50 clock periods is a practical minimum, because the time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine is at least 29 clock periods (the response time is dependent on how many privileged instructions are encountered when the request occurs). To establish time + + Any of three conditions causes the prescaler to reset: 1. When the timer is stopped by clearing ICP bit 3. + 2. When an output instruction to the timer (port XXXXXX11) is executed. 3·72 F3871 + As in the interval timer mode, the timer can be read at any time and can be stopped at any time by clearing ICP bit 3, the prescaler, and ICP bit 1 functions as previously described. The timer still functions as an 8-bit binary down counter with the timer interrupt request latch set on the timer's transition from H2'01'to H'N'. Note that the EXT INT pin is not involved with loading the timer; its action is that of automatically starting and stopping the timer and of generating external interrupts. Pulse widths longer than the prescale value times the modulo·N value are easily measured by using the timer interrupt service routine to store the number of timer interrupts in one or more scatchpad registers. intervals greater than 51,200 clock periods, use the timer interrupt service routine to count the number of interrupts, saving the result in one or more of the scratch pad registers until the desired interval is achieved. With this technique, virtually any time interval, or several time intervals, can be generated. The F3871 timer can be read at any time and in any mode, using an input instruction (IN or INS), and can take place "on-the·fly" without interfering with normal timer operation. The timer can be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and resumes counting when bit 3 is set again. The prescaler is reset whenever the timer is stopped; thus, a series of starting and stopping results in a cumulative truncation error. The actual pulse duration is typically slightly longer than the measured value, because the status of the prescaler is not readable and is reset when the timer is stopped. Thus, for maximum accuracy, using a small division setting for the prescaler is advisable. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests can be in error by plus or minus six clock periods, although the cumulative error over many intervals is zero. The prescaler and timer generate precise intervals for setting the timer interrupt request latch, but the time-out can occur at any time within a machine cycle. (There are two types of machine cycles: short cycles that consist of four clock periods and long cycles that consist of six clock periods.) The write clock corresponds to a machine cycle. Interrupt requests are synchronized with the write clock, thus creating the possible plus or minus six error. Additional errors can arise if the interrupt request occurs while a privileged instruction or multicycle instruction is being executed. However, for most applications, all of the above errors are negligible, especially if the desired time interval is greater than one ms. Other timer errors are summarized in the "Timing Characteristics" section. + + Event Counter Mode When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer operates in the event counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer decrements on each transition from the inactive level to the active level of the EXT INT pin. The prescaler is not used in this mode. As in the other two timer modes, the timer can be read at any time and can be stopped at any time by clearing ICP bit 3. ICP bit 1 functions as previously described, and the timer interrupt request latch is set on the timer's transition from H'01' to H'N'. + + Normally, ICP bit 0 is kept cleared in the event counter mode; otherwise, external interrupts are generated on the transition from the inactive level to the active level of the EXT INTpin. Pulse Width Measurement Mode When ICP bit 4 is set (logic 1) and at least one prescale bit is set, the timer operates in the pulse width measurement mode. This mode is used to accurately measure a pulse duration applied to the EXT INT pin. The timer is stopped and the prescaler is reset whenever the EXT INT pin is at its inactive level. The active level of the EXT INT pin is defined by ICP bit 2: if cleared, the EXT INT pin is active low; if set, the EXT INT pin is active high. If ICP bit 3 is set, the pre· scaler and timer start counting when the EXT INT signal goes through a transition to the active level. For the event counter mode, the minimum pulse width required on EXT INT is two clock periods, and the minimum inactive time is two clock periods; the maximum repetition rate is SOO Hz. + + External Interrupts When the timer is in the interval timer mode, the EXT INT pin is available for non-timer-related interrupts. If ICP bit 0 is set, an external interrupt requel!t latch is set when there is a transition from the inactive level to the active level of the EXT INT pin. (The EXT INT pin is an edge-triggered input.) The interrupt request is latched either until acknowledged by the CPU or until ICP bit 0 is cleared (unlike timer interrupt requests that remain latched even when ICP bit 1 is cleared). When the EXT INT pin returns to the inactive level, the timer stops, the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external interrupts are not latched if the ICP interrupt enable is not set.) 3·73 F3871 input cycle. Only the two 1/0 ports (lowest two addresses) respond to input instructions. Output instructions that select a port transfer the contents of the data bus to that port. Outputs of the latches change at the end of the 1/0 transfer cycle. External interrupts are handled in the same manner when the timer is in the pulse width measurement mode or in the event counter mode, except that in the pulse width mea· surement mode only, the external interrupt request latch is set on the trailing edge of the EXT INT signal (i.e., on the transition from the active level to the inactive level). Interrupt Handling Instruction Execution A typical F8 system interrupt interconnection is shown in figure 4. Each PSU and PIO has a PRI IN and a PRI OUT line so that they can be daisy-chained together in any order to form a priority level of interrupts. When a PIO receives an interrupt (either timer or external), it pulls its PRI OUT output signal high, signaling all lower priority peripherals that it has a higher priority interrupt request pending on the CPU. When the PIO device's PRI IN input signal is pulled high by a higher priority peripheral, signaling the PIO that there is a still higher priority interrupt request pending, it passes that signal along by pulling its PRI OUT signal high. When the CPU processes an interrupt request, it commands the interrupting device to place its interrupt vector address on the data bus. Only the device with a PRI IN signal low and an interrupt request pending responds. Should there be another lower priority device with a pending request, it does not respond at that time because its PRI IN input signal is high. The PIO responds to signals that are output by the F3850 CPU in the course of implementing instruction cycles. The PIO places data on the data bus, even in the worse case, in time for the setup required by any F3850 CPU destination. The PIO receives a byte input from the data bus when commanded by an output instruction to load one of its two 1/0 ports or internal registers. The data bus drive signal (DBDR) is low while data output by the PIO is stable on the data bus. Thus, a DBDR low signal indicates that the data bus currently contains data flowing from a PIO. For systems with more than one program storage unit (PSU) or PIO, the DBDR output signal can be wire-ORed and the result used as a bus data flow direction indicator. The DBDR signal can remain low until timing interval tda of the next instruction cycle following the one in which Di3DR" was set low. If there is both a timer interrupt request and an external interrupt request when the CPU starts to process the requests, the timer interrupt is handled first. The PIO device executes the OUT instruction in the same manner as it does the OUTS instruction; the same is true for the IN and INS instructions. The difference between the long- and short-form instructions is found only in the source of the 1/0 address. Within each local interrupt control circuit is a 16-bit interrUpt address vector. This vector is the address to which the program counter is set after an interrupt is acknowledged and is, therefore, the address of the first executable instruction of the interrupt routine. The F8 inputloutput instructions place the 1/0 port address on the data bus during one instruction cycle and then use the data bus in the following instruction cycle to do the actual 1/0 data movement. The Read-Only Memory Control (ROMC) lines coming from the F3850 CPU signal the PIO that an 1/0 data movement is occurring during the current instruction cycle. Therefore, the PIO needs to recognize whether the contents of the data bus during the instruction cycles just prior matches any of its four assigned 1/0 addresses wherever the ROMC lines indicate an 1/0 transfer. The address select logic constantly monitors the data bus for a match to any of the four addresses and holds the information of a match through the following cycle. The interrupt address is unique to the version of the PIO dev.ice selected by the user. Fifteen bits are fixed: bits 0 through 6 and bits 8 through 15. Bit 7 (27) is dependent on the type of interrupt. This bit is a 0 for internal timergenerated interrupts and a 1 for external interrupts. When the interrupt logic sends an interrupt request signal and the CPU is enabled to service it, the normal state sequence of the CPU is interrupted at the end of an instruction. The CPU signals the interrupt circuits through the five ROMC lines. The requesting local interrupt circuit sends a 16-bit interrupt address vector (from the interrupt address generator) onto the data bus in two consecutive bytes. Input instructions that select a port cause the contents of the selected port to be placed on the data bus during the 3-74 F3871 The CPU allows interrupts after all Fa instructions except the following: The address is made available to the program counter through the address demultiplexer circuits. It is simultane· ously made available to all other devices connected to the data bus. It is the address of the next instruction to be exe· cuted. The program counter of each memory device is set with this new address while the stack register is loaded with the previous contents of the program counter. The information in the program counter is lost. Thus, the next instruction to be executed is determined by the value of the interrupt address vector. (PK) (PI) (POP) (JMP) (OUTS) (OUT) (EI) (LRW,J) The interrupt control bit (lCB) of the CPU (loaded in the W register) allows interrupts to be recognized. Clearing the ICB prevents acknowledgement of interrupts. The ICB is cleared during power-on and external reset, and after an interrupt is acknowledged. The interrupt status of the PSU, PIO, or memory interface (MI) devices is not affected by execution of the disable interrupt (01) instruction. At the conclusion of most instructions, the fetch logic checks the state of the interrupt request line. If there is an interrupt, the next instruction fetch cycle is suspended and the system is forced into an interrupt sequence. PUSH K PUSH IMMEDIATE POP JUMP OUTPUT SHORT (Excluding OUTS 00 and 01) OUTPUT SET ICB LOAD THE STATUS REGISTER FROM SCRATCH PAD POWER ON As a result, it is possible to perform one more instruction after each of the above CPU instructions without being interrupted. Figure 4 Fa System Interrupt Interconnection r------------- CONTROL LINES CPU ICB r-----------~ PSUIPIO PSu/PIO 1 2 SMI PIO PRIORITY (n) PRIORITY L - - - - - - - - - E X T E R N A L INTERRUPT l I N E S - - - - - - - - - 3·75 F3871 Interrupt Sequence Figure 5 details the interrupt sequence that occurs whether the interrupt request is from an external source through the EXT INT pin or from the PIO device's internal timer. The events in the sequence are labeled A through G. encountered, a series of priviledged instructions would be executed sequentially. One more instruction (a protected instruction) is executed after the last priviledged instruction. The last cycle of the protected instruction then performs the freeze. Event A An interrupt request must satisfy a set-up time requirement. If not satisfied, the INT REO signal delays going low until the next negative edge of the write clock. The dashed lines on the EXT INT timing in figure 5, illustrate the last opportunity for the EXT INT signal to cause the last cycle of a non protected instruction to become a freeze cycle. The freeze cycle is a short cycle (four clock periods) in all cases except where B is the decrement scratchpad instruction, in which case the freeze cycle is a long cycle (six clock periods). + Event B Event B represents the instruction being executed when the interrupt occurs. The last cycle of B is normally the instruction fetch for the next cycle. However, if B is not a privileged instruction and the CPU interrupt control bit is set, the last cycle becomes a freeze cycle rather than a fetch. At the end of the freeze cycle, the interrupt request latches are inhibited from altering the interrupt daisy chain so that sufficient time is allowed for the daisy chain to settle. + The INT REO signal goes low on the next negative edge of WRITE if both the PRIIN signal is low and the appropriate interrupt enable bit of the ICP is set. Event C This is a no-operation (NO-OP) long cycle, allowing time for the PRIIN/PRI OUT chain to settle. At a 2MHz clock rate, a total of seven PIO, PSU, or MI devices can be daisy-chained without the need for look-ahead logic. + If B is a privileged instruction, the instruction fetch is not replaced by a freeze cycle; instead, the fetch is performed and the next instruction is executed. Although unlikely to be Figure 5 F3871 Interrupt Sequence FREEZE CYCLE WRITE EXT INT OR TIMER INTERRUPT 1 , 1-1 NI --';'1- - - I--II--l 1 -- A 4--- i ~ PRI OUT OF NEXTPIO _~ ____II. J rll I _~ ___ I I IL I ...;I---Ir/l-_-_-I_-..J~I---'----~------~I""'Y 3-76 F3871 Summary of Intenupt Sequence For the PIO, the interrupt response time is defined as the time elapsed between the occurrence of the EXT INT signal going active (or the timer transition to H'N1 and the beginning of execution of the first instruction of the interrupt service routine. The interrupt response time is a variable dependent on what the microprocessor is doing when the interrupt request occurs. Event 0 In PSU circuits, the program counter (PO) is pushed to the stack register (P) to save the return address. The interrupting PIO places the lower eight bits of the interrupt vector address onto the data bus. This is always a long cycle. Event E In this long cycle, the PIO places the upper eight bits of the interrupt vector address onto the data bus. As shown in figure 5, the minimum interrupt response time is three long cycles plus two short cycles plus one WRITE clock pulse width plus a setup time of an EXT INT signal before the leading edge of the WRITE pulse-a total of 27 clock periods plus the setup time. At 2 MHz, this is 14.25 ,..s. Although the maximum could theoretically be infinite, a practical maximum is 35 ,..s (based on the interrupt request occurring near the beginning of a PI and LR K, P sequence). Event F In this short cycle, the PIO interrupting interrupt request latch is cleared. Also, the CPU interrupt control bit is cleared, thus disabling interrupts until an EXT INT instruction is performed. Additionally, during Event F, the PRI INIPRI OUT daisy-chain freeze is removed, since the interrupt vector address has been passed to the CPU. Another action is the fetch of the instruction from the interrupt address. + ROMCStates Table 4 shows the function performed by the PIO device for each ROMC command. Each function is performed entirely within one machine cycle (one cycle of the write clock). All other ROMC states are decoded as NO-oP. Event G This event starts executing the first instruction of the interrupt service routine. Table 4 PIO Functions Versus ROMC States ROMCState Binary Hex PIO Functions 01000 08 Reset command. Load port A, port B, timer, and interrupt control port with H'OO'. 01111 OF If this circuit is interrupting and is highest in the priority chain, move lower half of interrupt vector into the data bus. 10000 10 Place interrupt circuitry in an inhibit state that prevents altering the interrupt priority chain. 10011 13 If this circuit is interrupting and is highest in the priority chain, move upper half of interrupt vector into the data bus and reset the interrupt circuit. 11010 1A If the contents of the data bus in the prior cycle was an address of 1/0 ports on this d.evice, move the current contents of the data bus into the appropriate port (1/0 A, 110 B, timer, or control). 11011 1B If the contents of the data bus in the prior cycle was an address of 1/0 ports on this device, move the contents of the appropriate 1/0 port onto the data bus (1/0 A or 110 B). 3·77 F3871 Timing Characteristics Load timer to read timer error (Notes 1,2) ....................... -5t,to -(tpsc+18t+l Load timer to interrupt request error (Notes 1,3) .............................. -2t,to -9t+ Timing signals are Illustrated in figures 6 through 10, and the signal characteristics are presented in tables 5 through 9. Definitions for the timing characteristics are as follows: Pulse Width Measurement Mode Measurement accuracy (Note 4). . . . . . .. to - (tpsc + 2t+l Minimum pulse width of EXT INT pin .................. 2t+ +I, Error = Indicated Time Val ue - Actual Time Val ue tpsc = t. x Prescale Value Event Counter Mode Minimum active time ofthe EXT INT pin ............... 2t+ Minimum inactive time of the EXT INT pin ............. 2t+ Interval Timer Mode Single interval error,free running (Note 3) ............ ±6t, Cumulative interval error, free running (Note 3) ........... 0 Error between two timer reads (Note 2) .......... ±(tpsc + t,) Start timer to stop timer error (Notes 1,4) .......................... +t,to -(tpsc +t,) Start timer to read timer error (Notes 1,2) ........................ -5t.to -(t psc +7t,) Start timer to interrupt request error (Notes 1,3) ............................. -2 t, to -8t, Load timerto stop timer error (Note 1) .... +t, to -(t psc +2t+l NOTES 1. All times that entail loading, starting, or stopping the timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction. 2.. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS instruction. All times that entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is set. Additional time elapses if the interrupt request occurs during a privileged or multicycle instruction. 4. Error can be cumulative if operation is repetitively performed. 3. Figure 6 F3871 Clock Timing CLOCK TIMING TIMING ALL TIMING SPECIFIED AT Vss ::: 0 V, Voo ::: + 5 V ± 5%, Voo ::: 3·78 + 12 V ± 5% F3871 Figure 7 F3871 Strobe Timing WRITE 1IW-,/ol_ _----"~,.-I- - I/O PORT OUTPUT _-----.I~\I--:- -,SL STROBE (PORT A ONLY) I , Figure 8 F3871 Input Timing WRITEJ\ -..J tSR2 r- -iIHRlr- X X ROMe DATA BUS -------- I tHD3 r-- r===== =J~----------"""'~ 151102_ PORTS I.- X -------- 1/0 ISD4- 3·79 tHI/02 F3871 Figure 9 F3871 Output Timing OUTPUT TIMING Figure 10 F3871 Interrupt Timing INTERRUPT TIMING WRITE ACTIVE LOW l....-tSEI1----..[ I+XI === tHEI1 EXT INT--A:.;C:.T;.:IV.:;E:.H:.I:.G::.H.....;X'-_ _ _ _...... ~I ~I~"",,--r- lflR2 -I _IdP01~1 ---Jlij II PRIOUT _ _ _ _ _ _ _ _ I PRI OUT OF NEXT PIO IN CHAIN iN TO PRI OUT DELAY) 3-80 I'POl ,- \ ......_ _ ---I I'P~ - - "P021_ (PRI !7 _---lII_---i--J II ,I_ 'L F3871 Table 5 F3871 Clock TIming Characteristics Symbol Parameter P+ Po P1 Clock Period 0.5 Low time 180 High time 180 PW WRITE Clock Period 4P, PWo WRITE Clock Period 6P, PW1 WRITE Pulse Width tdw1 Typ. Min. Max. 10 Units Conditions /As ns ns Short cycle Long cycle P,-100 , - to WRITE + delay P, 250 ns tdwO , - to WRITE - delay 225 ns Table 6 F3871 Strobe TIming Characteristics Symbol Parameter Min. Max. Units tI/O-S Port Output to STROBE delay 3t,-1000 3t, +250 ns tSL STROBE Pulse Width, Low 8t,-250 12t,+250 ns tw -1I0 WRITE to 110 Port Output Valid 1000 ns Comments Note 1 Note 2 NOTES 1. Load is 50 pF plus 3 standard TTL inputs. 2. Load is 50 pF plus 1 standard TTL Input. Table 7 F3871 Input Timing Characteristics Symbol Parameter tSR2 ROMC Valid Measured from Fall of WRITE tHR1 ROMC Required Hold After Fall of WRITE tSD4 Data Bus Setup Time Min. 20 Typ. Max. Units 550 ns ns ns tHD3 Data Input Hold Time 20 ns tSI/02 110 Input Setup Time 1.3 ns tHII02 110 Input Hold Time 20 ns 3·81 Conditions F3871 Table 8 F3871 Output Timing Characteristics Symbol Parameter tfDR1 WRITE to DBDR Floating tdoR1 + to tdOR2 WRITE to Typ. Min. iSBi5'R 1-0 200 D'Bl5R 1-0 tdD3 WRITE to Data Valid tOH02 Guaranteed Data Hold Time After Fall of WRITE 2P+tdwo 2P+400 Conditions Max. Units 400 ns 625 ns CL =100 pF; RL =12.5 kQ 2P++ 625tdwO ns CL = 100 pF; RL = 12.5 kQ ns CL =1oo pF 2P++ 700tdwO ns CL =1oo pF ns 30 Table 9 F3871 Interrupt Timing Characteristics Symbol Parameter Min. tSEI1 EXT INT Setup Time 750 tHEI EXT INT Hold Time 30 tdlR2 WRITE to INT REO Delay 430 ns C L =1oo pF WRITE to PRI OUT Delay 640 ns CL =50pF PRiOOi Delay 350 ns C L =50 pF 640 ns Open Drain Output tP01 tdP02 PRIIN to tflR1 WRITE to INT REO Float by PIO Typ. Max. Units Conditions ns ns DC Characteristics The DC characteristics of the F3871 PIO are supplied in table 10. Table 10 F3871 DC Characteristics Symbol Parameter Signal Min. Max. Units VIH VIL VOH VOH VOL IIH IOL CI Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input Capacitance Data Bus (DBa -DB7) 2.0 Vss 3.9 2.4 Voo 0.8 Voo V V V V V ,.,.A 0.4 1.0 -1.0 10 3-82 jAA pF Test Conditions IOH = -100 jAA IOH =100 ,.,.A, VGG =5 V±5% IOL=1.6mA VIN = 6 V, 3-state mode VIN = Vss, 3-state mode 3-state mode F3871 Table 10 F3871 DC Characteristics Symbol VIH VIL IL CI VIH VIL IL CI VOH VOL VOH VOL IL CI VOH VOL IL CI VIH VIL IIH IlL CI VOH VOL VOH VOL VIH VIL IlL CI VOH VOL VIH VIL IL CI VOH VOL IOH Parameter Input High Voltage Input Low Voltage Leakage Current Input Capacitance Signal Clock Lines Input High Voltage Input Low Voltage Leakage Current Input Capacitance Priority In and Control Lines (PRI IN, ROMCo ROMC4) Output High Voltage Output Low Voltage Priority out (PRI OUn Output High Voltage Output Low Voltage Leakage Current Input Capacitance Interrupt Request (lNT REO) Output High Voltage Output Low Voltage Leakage Current Input Capacitance Data Bus Drive (DBDR) Input Input Input Input Input High Voltage Low Voltage High Current Low Current Capacitance (+, WRITE) Min. Max. 2.0 Vee Voo 0.8 ±1.0 10 3.5 Vcc 10 Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Low Current Input Capacitance 1/0 Port Option A (Standard Pull-up) Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Leakage Current Input Capacitance 1/0 Port Option B (Open Drain) Output High Voltage Output Low Voltage Output High Current 1/0 Port Option C (Driver Pull-Up) Vss 2.0 Vss 1.5 Vss -1.5 NOTES 1. Pull-up resistor to voo on CPU. 2. Measured with a high·level 110 port output. 3. Positive current Is defined as conventional current flowing Into the pin referenced. 4. Vss=O V, Voo= +5 V ±5%, VGG = +12 V ±5%, TA =O'C to +70'C unless otherwise noted. 3·83 V V 10H= -1MIlA 10L = -1.8 rnA V V pF Open Drain Output 1 10L =0.8 rnA VIN = 6 V, Output Device Off Output Device Off V IlA pF External Pull·up IOL=1.8 rnA VIN = 6 V, Output Device Off Output Device Off 0.4 1.0 10 2.4 Vss 2.4 Vss 2.0 Vss V V JlA JlA External Pull-ups Exist Internal VIN =0.4 V VIN =2.4 V pF Voo 0.4 V V Voo 0.4 Voo 0.8 1.0 10 V V V V rnA pF 0.4 6.0 0.8 1.0 10 V V V Voo 0.4 -9.0 VIN =Vssto +6V pF JlA 100 Strobe (STROBE) JlA 0.4 1.0 10 0.8 -1.6 VIN = Vss to +6 V V V Vss 2.0 Test Conditions pF Voo 0.4 (EXT INn Output High Voltage Output Low Voltage JlA 3.9 Vss Vss ~Interrupt Voo 0.8 1.0 10 Units V V 10H = -300 JlA IOL=5.0rnA 10H = -100 JlA IOL=1.8rnA Internal Pull-up to Voo VIN =O.4 V2 External Pull-up IOL=1.8mA JlA VIN = 6 V, Output Device Off V V rnA 10H= -1.5 rnA IOL=1.8rnA VO H =0.7 V to 1.5 V pF F3871 The supply currents are given in table 11. Table 11 Supply Currents Symbol Parameter Typ. Max. Units 100 Voo Current 30 70 rnA f IGG VGG Current 10 18 rnA f Min. These are stress ratings only, and functional operation at these ratings, or under any conditions above those indio cated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Part Number The recommended operating ranges of the PIO devices are shown below. Voo Supply Voltage VGG Vss Typ. +4.75 V +5V +11.4 V +12V F3871 DC Ceramic C Ceramic M Plastic C 'Versions E, F, G, and H are stocked Items. Recommended Operating Ranges Max. +5.25 V +12.6 V OV 3·84 Temperature Range F3871DM 'F3871PC NOTE: All voltages are with respect to Vss. Min. Package C = Commercial Temperature Range O· to +70·C L = Limited Temperature Range -4O·C to +85·C M = Military Temperature Range -55·C to +125·C +15V, -0.3V +7V, -0.3V -600,.,A, +225,.A +7V, -0.3V -55·C, +150·C O·C, +70·C VGG Voo Extemallnterrupt Input All Other Inputs and Outputs Storage Temperature Operating Temperature Parameter =2 MHz, Outputs Unloaded =2 MHz, Outputs Unloaded Ordering Information Absolute Maximum Ratings Symbol Conditions I [!] I INTRODUCTION r;;l2 IORDERING AND ~ INFORMATION PACKAGE IWlF8 MICROCOMPUTER FAMILY CONTROLLER FAMILY 1~IF6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY I~ I ROM PRODUCTS Inlg I DEVELOPMENT SYSTEMS AND L!J SOFTWARE I~ I APPLICATIONS IC!IJ I RESOURCE AND TRAINING CENTERSI I@] I SALES OFFICES Section 4 Controller Family FAIRCHILD A Schlumberger Company F387X Family Part Numbers The Fairchild F387X family of devices represents a line of complete, 8-bit microcomputers on single MOS integrated circuits (see figure 4-1). Fabricated using Fairchild doubleion·implanted, N-channel silicon-gate technology and advanced circuit design techniques, the F387X family offers maximum cost-effectiveness in a variety of logic replacement and control applications. Because of the on-going growth of the F387X family, a new numbering system for these devices has been developed by Fairchild: F38 Technology/Option _ _ _ _ _ _ _ _ _ _ _--'T 7X Omit = NMOS CMOS C E EPROM L = Low-power stand-by option (F3872 only) = = Figure 4-1 F387X Family Organization F3870 SINGLE·CHIP MICROCOMPUTER Speed G r a d e - - - - - - - - - - - - - - . . . J Omit Standard A 1.33 us cycle time B 1 us cycle time = F3870AIF3870B HIGH·SPEED SINGLE·CHIP MICROCOMPUTER F38C70 SINGLE·CHIP MICROCOMPUTER F38E70 SINGLE·CHIP MICROCOMPUTER ROM size - - - - - - - - - - - - - - - - - - - ' 1 1024 bytes 2 2048 bytes = 3072 bytes 3 = 4032 or 4096 bytes 4 F38721F38L72 SINGLE·CHIP MICROCOMPUTER = All F387X family microcomputers execute the F8 instruction set of more than 70 commands. They are available with a wide range of memory types and sizes, allowing the designer to select the best combination of RAM and ROM for a particular application. The F387X devices are also available with special types of I/O. Descriptions Following is data that describes the members of the F387X single-chip microcomputer family. The F387X family devices are all pin-compatible, permitting easy system upgrading by replacement of one device in an application with another family member having greater quantities of RAM or ROM, special I/O functions, or all three. Because of this simple upgrading, an F387X-based microcomputer can be enhanced or expanded in many different ways without affecting system printed circuit board, enclosure, or power supply requirements. The Fairchild F387X single-chip microcomputer family is recognized as an industry standard in logic replacement and control. The devices have been designed into, and successfully used in, a wide range of applications requiring intelligent control. 4-3 • Controller Family 4-4 F3870 F=AIRCHILD Single-Chip Microcomputer A Schlumberger Company Microprocessor Product Description Connection Diagram The Fairchild single-chip microcomputer series offers a variety of circuits to serve the high-volume, cost-sensitive controller market. The F3870 is a complete 8-bit microcomputer on a single MOS integrated circuit. The F3870 can execute the F8 instruction set of more than 70 commands, allowing expansion into multi-chip configurations with software compatibility. The device features 64 bytes of scratch pad RAM, a programmable binary timer, 32 bits of 1/0, a single + 5 V power supply requirement, and a choice of 1K, 2K, 3K, or 4K of ROM. 40·Pin DIP Voo RESET EXT INT • Utilizing Fairchild's double-ion-implanted, N-channel silicon-gate technology and advanced circuit design techniques, the single-chip F3870 offers maximum cost effectiveness in a wide range of control and logic replacement applications. • • • • • • • • • • Single-Chip Microcomputer Software·Compatible with FS Family 1024·, 204S·, 3072·, or 4096·Byte Programmable ROM 64·Byte Scratchpad RAM 32·Blt (4·Port) TTL·Compatible I/O Programmable Binary Timer: Interval Timer Mode Pulse Width Measurement Mode Event Counter Mode External Interrupt Crystal, LC, RC, or External Time Base Low Power (275 mW, Typical) Single +5 V:!: 10"10 Power Supply po, po. Vss (Top View) Signal Functions The functions of the F3870 inputs and outputs are described in Table 1. 4-5 F3870 Signal Functions CLOCK { XTL, ~P4o XTL, P41 P42 P43 EXT INT DEVICE ( CONTROL Device Organization TEST P44 P4s POo P47 RESET This section describes the basic functional elements of the F3870 shown in Figures 1 and 2. 110 PORT 4 P46 P01 P02 I/O PORT 0 PO, P04 Pas PSo P51 Ps2 P53 Pa6 PS, P07 P5s 110 PORT 5 ROM Address Registers There are four 12·bit registers associated with the program ROM of the F3870. (In the F3870·1, ·2, and ·3, the 12·bit registers can address more memory space than is phYSically available on the chip; user caution is advised. Older versions of the F3870·1 and ·2, predating date code 8213, may have 11·bit registers; contact Fairchild if you have any questions.) These are the program counter (PO), the stack register (P), the data counter (DC), and the auxiliary data counter (DC1). The program counter is used to address instructions or immediate operands. The stack register is used to save the contents of PO during an interrupt or subroutine call. Thus, P contains the return address at which processing is to resume upon completion of the subroutine or the interrupt routine. P56 P10 PS, P11 P12 I/O PORT 1 Main Control Logic The instruction register (IR) receives the operation code (op code) of the instruction to be executed from the program ROM via the data bus. During all op code fetches, eight bits are latched into the IR. Some instructions are completely specified by the upper four bits of the op code; in such instructions, the lower four bits are an immediate register address or an immediate 4·bit operand. Once latched into the IR, the main control logic decodes the instruction and provides the necessary control gating signals to all circuit elements. P1, P14 P1s P1. P17 The data counter is used to address data tables. This register is autoincrementing. Of the two data counters, only DC can access the ROM. However, the XDC instruction allows DC and DC1 to be exchanged. Associated with the F3870 address registers is a 12·bit adder/incrementer. This logic element is used to increment PO or DC when required and is also used to add displacements to PO on relative branches or to add the data bus contents to DC in the add data counter (ADC) instruction. Program ROM The microcomputer program and data constants are stored in the program ROM, which may be 1024 x 8 (F3870·1), 2048 x 8 (F3870·2), 3072 x 8 (F3870·3), or 4096 x 8 (F3870·4) bytes. When a ROM access is required, the appropriate address register (PO or DC) is gated onto the ROM address bus and the ROM output is gated onto the main data bus. The first byte in the ROM is location zero. 4·6 F3870 Table 1 Signal Functions Mnemonic Device Control EXTINT Pin No. Name Description 38 External Interrupt Software·programmable input that is also used in conjunction with the timer for pulse width measurement and event counting. RESET 39 External Reset Input that may be used to externally reset the F3870. When pulled low, the F3870 resets; when then allowed to go high, the F3870 begins program execution at program location H '0000'. TEST 21 Test Line An input used only in testing the F3870. For normal circuit operation, TEST is left unconnected or grounded. 7 Ready Strobe Normally high output that provides a single low pulse after valid data is present on the P4 o-P4 7 pins during an output instruction. 1,2 Time Base Inputs to which a crystal (1 MHz to 4 MHz), LC network, RC network, or external single·phase clock may be connected. 3-6,8-19, 22-37 I/O Ports Thirty·two bidirectional lines that can be individually used as either TTL·compatible inputs or latched outputs. Power Voo 40 Power Input +5 V ± 10% power supply Vss 20 Ground Signal and power ground Clock STROBE XTL 1, XTL2 110 Ports POO-P0 7 P10-P17 P4 o- P47 P55-P57 Fig. 1 Scratch pad and ISAR The scratch pad provides 64 8·bit registers that may be used as general·purpose RAM. The indirect scratch pad address register (ISAR) is a 6·bit register used to address the 64 registers. All 64 registers may be accessed using the ISAR. In addition, the lower order 12 registers may also be directly addressed. F3870 Architecture The ISAR can be visualized as holding two octal digits. This division of the ISAR is important, since a number of instructions increment or decrement only the least significant three bits of the ISAR when referencing scratch pad bytes via the ISAR. This makes it easy to reference a buffer conSisting of contiguous scratch pad bytes. For example, when the low·order octal digit is incremented or decremented, the ISAR is incremented from octal 27 to 20 or is decremented from octal 20 to 27. This feature of the ISAR is very useful in many program sequences. All six bits of the ISAR may be loaded at one time, or either half may be loaded independently. ACCUMULATOR TEST 1 PROGRAM COUNTER STACK REGISTER DATA COUNTER 0 DATA COUNTER 1 EXTINT vee GND 4·7 • F3870 Fig. 2 F3870 Block Diagram ......-Vcc-40 .--_ _ _ _- - , - GND-20 _EXTINT-38 ROM ADDRESS PROGRAM REGISTERS ROM .--------,_XTL2-1 ...--XTLl-2 _RESET-39 PO, P,DC, DCl L.-;:====~ .........-.. PO,-4 INDIRECT SCRATCH PAD _TEST-21 ~~-3 t----",I ADDRESS .....-.. P02-5 SCRATCHPAD ~~-6 REGISTERS :=:~=~: _ _ 1'06-17 REGISTER _ _ li07-16 :==~ ~P1o-37 ~1Sf1-36 ~P12-35 _ _ 1'f3-34 ""--"'JS'f4-22 --1'T5-23 ACCUMULATOR & STATUS --1'16-24 ~Pl7-25 :==~ ---.1'40-8 ALU .--.-... Pii-9 _ _ 1'4,-10 _ _ 1143-11 _ _ ffi-12 ~P45-13 ~1'46-14 ~P47-15 ;::=====i-"::--: S'I'RO!E -7 . . . - - . PSo-33 ~ P51-32 ~P52-31 ~~-30 _ _ P54-29 :=:w.=~; L..._ _ _..... - - l'Si-26 Scratch pad registers 9 through 15 (decimal) are given mnemonic names (J, H, K, and Q) because of special linkages between these registers and other registers, such as the stack register. These special linkages facilitate the implementation of multi·level interrupts and subroutine nesting. For example, the instruction LR K, P stores the lower eight bits of the stack register in register 13 (K lower, or KL) and stores the upper four bits of P in register 12 (K upper, or KU). operations (using the data presented on the two input buses) and provides the result on the result bus. The arithmetic operations that can be performed in the ALU are binary add, decimal adjust, add with carry, decrement, and increment. The .Iogic operations that can be performed are AND, OR, exclusive·OR, ones complement, shift right, and shift left. Besides providing the result on the result bus, the ALU also provides four signals presenting the status of the result. These signals, stored in the status register (W), represent the CARRY, OVERFLOW, SIGN, and ZERO conditions of the result of the operation. Arithmetic and Logic Unit (ALU) After receiving commands from the main control logic, the ALU performs the required arithmetic or logic 4·8 F3870 Accumulator The accumulator (ACC) is the principal register for data manipulation within the F3870. The ACC serves as one input to the ALU for arithmetic or logical operation. The results of ALU operations are stored in the ACC. An output ready strobe is associated with port 4. This flag may be used to signal a peripheral device that the F3870 has just completed a single low pulse shortly after the output operation is completely finished, so either edge may be used to signal the peripheral. This STROBE signal may also be used to request new input information from a peripheral simply by doing a dummy output of H'OO' to port 4 after completing the input operation. Status Register The status register (also referred to as the W register) holds five status flags, as follows: Timer and Interrupt Control Port • The timer is an 8-bit binary down counter that is software-programmable to operate in one of three • modes: the interval timer mode, the pulse width measurement mode, or the event counter mode; the timer characteristics are described in Table 2. As shown in Figure 4, associated with the timer is an 8-bit register called the interrupt control port, a programmable prescaler, and an 8-bit modulo-N register; a functional logic diagram is shown in Figure 5. _BIT NO. STATUS REGISTER (W) SIGN CARRY ' - - - - - - ZERO ~------ OVERFLOW ~------- INTERRUPT CONTROL BIT The desired timer mode, prescale value, starting and stopping the timer, active level of the EXT INT pin, and local enabling or disabling of interrupts are selected by outputting the proper bit configuration from the accumulator to the ICP (port 6) with an OUT or OUTS instruction. Bits within the ICP are defined as follows: Summary 01 Status Bit OVERFLOW ZERO CARRY 7 (B CARRY 6 ALU 7 1\ ALUs 1\ ALU s ALU3 1\ ALU 2 1\ ALU, 1\ ALU4 1\ ALUo CARRY SIGN Interrupt Control Port (Port 6) Bit O-Externallnterrupt Enable Bit 1-Timer Interrupt Enable Bit 2-EXT INT Active Level Bit 3-Start/Stop Timer Bit 4-Pulse Width/Interval Timer Bit 5- + 2 Timer Prescale Values Bit 6- + 5 Timer Prescale Values Bit 7 - + 20 Timer Prescale Values The interrupt control bit (ICB) of the status register may be used to allow or disallow interrupts in the F3870. This bit is not the same as the two interrupt enable bits in the interrupt control port (ICP). If the ICB is set and the F3870 interrupt logic communicates an interrupt request to the CPU section, the interrupt is acknowledged and processed upon completion of the first non-privileged instruction. If the ICB is cleared, an interrupt request is not acknowledged or processed until the ICB is set. A special situation exists when reading the ICP with an IN or INS instruction. The accumulator is not loaded with the contents of the ICP; instead, accumulator bits 0 through 6 are loaded with zeros, while bit 7 is loaded with the logic level being applied to the EXT INT pin, thus allowing the status of the EXT INT pin to be determined without the necessity of servicing an external interrupt request. This capability is useful in establishing a high-speed, polled handshake procedure or for using EXT INT as an extra input pin if external interrupts are not required and the timer is used only in the interval timer mode. 1/0 Ports The F3870 provides four complete bidirectional 1/0 ports; these are ports 0, 1, '4, and 5. In addition, the interrupt control register is addressed as port 6 and the binary timer is addressed as port 7. An output instruction (OUT or OUTS) causes the contents of the ACCto be latched into the addressed port. An input instruction (IN or INS) transfers the contents of the port to the ACC (port 6 is an exception that is described later). The 1/0 pins on the F3870 are logically inverted. The schematic of an 1/0 pin and conceptual illustrations of available output drive options are shown in Figure 3. 4-9 F3870 Fig. 3 1/0 Port Diagram Voo PORT I/O PIN OPEN DRAIN OUTPUT STANDARD OUTPUT DIRECT DRIVE OUTPUT Ports 0 and 1 are standard output type only. Ports 4 and 5 may be any of the three output options, each pin individually assignable to any port. The STROBE output is always configured similar to a standard output, except that it is capable of driving three TTL loads. Fig. 4 Timer and Interrupt Control Port Block Diagram EXTERNAL PRESCALER CLOCK TIME BASE -:--2, 5, 10, 20, 40, 100, or 200 INT REO INTERRUPT CONTROL PORT (PORT 6) EVENT COUNTER MODE ___ ... 2 PRESCALE ___ ... 5 PRESCALE ___ ... 10 PRESCALE ___ ... 20 PRESCALE ___ + 40 PRESCALE "4... 100 PRESCALE --... 200 PRESCALE _ 4~3 2~i L~X:~TR::~ L INTERRUPT ENABLE TIMER INTERRUPT ENABLE EXT INT ACTIVE LEVEL START/STOP TIMER PULSE WIDTHIINTERVAL TIMER 4·10 EXT INT Fig. 5 Timer/Interrupt Functional Diagram FROM INTERRUPT CONTROL PORT , 82 I 84 .3 .5 •• .7 80 I 81 TIMER INTERRUPT TIME BASE ·LOADS INTERRUPT VECTOR H '020' UPON COMPLETION OF THE FIRST NON· PRIVILEGED INSTRUCTION i: ACKNOWLEDGE TIMER INTERRUPT 'OUTS r ." 'I' '" PULSE WIDTH MODE ~ ..... o JL EXTERNAL INTERRUPT INPUT JL '1)1' ACKNOWLEDGE EXTERNAL INTERRUPT • F3870 Table 2 Timer Characteristics Characteristic Value Interval Timer Mode Single Interval Error, Free-Running (Note 3) ±6tc!> Cumulative Interval Error, Free-Running (Note 3) Error Between Two Tim~r 0 ±(tpsc+tc!» Reads (Note 2) Start Timer to Stop Timer Error (Notes 1, 4) + tc!> to - (tpsc + tc!» Start Timer to Read Timer Error (Notes 1, 2) - 5tc!> to - (tpsc + 7tc!» Start Timer to Interrupt Request Error (Notes 1, 3) - 2t c!> to - 8tc!> + tc!> to - (tpsc + 2tc!» Load Timer to Stop Timer Error (Note 1) Load Timer to Read Timer Error (Notes 1, 2) - 5tc!> to - (tpsc + 8tc!» Load Timer to Interrupt Request Error (Notes 1,3) - 2tc!> to - 9tc!> Pulse Width Measurement Mode + tc!> to - (tpsc + 2tc!» Measurement Accuracy (Note 4) 2tc!> Minimum Pulse Width of EXT INT Pin Event Counter Mode Minimum Active Time of EXT INT Pin 2tc!> Minimum Inactive Time of EXT INT Pin 2tc!> Dellnltlons Error= indicated time value - actual time value tpsc = t¢ x prescale value Nota. 1. All times that entail loading, starting, or stopping the timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction. 2. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS instruction. 3. All times that entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate Interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multi·cycle instruction. 4. Error may be cumulative If operation Is repetitively performed. The rate at which the timer is clocked in the interval timer mode is determined by the frequency of an internal c!> clock and by the division value selected for the prescaler. (The internal clock operates at one-half the external time base frequency.) If ICP bit 5 is set and bits 6 and 7 are cleared, the prescaler divides c!> by 2. Likewise, if bit 6 or 7 is individually set, the prescaler divides c!> by 5 or 20, respectively. Combinations of bits 5, 6, and 7 may also be selected. For example, if bits 5 and 7 are set while bit 6 is cleared, the prescaler divides by 40. Thus, possible prescaler values are: ... 2, ... 5, ... 10, ... 20, ... 40, ... 100, and ... 200. explained in the following paragraphs. An OUT or OUTS instruction to port 7 loads the contents of the accumulator into both the timer and the 8-bit modulo-N register, resets the prescaler, and clears any previously stored timer interrupt request. As previously noted, the timer is an 8-bit down counter that is clocked by the prescaler in the interval timer mode and in the pulse width measurement mode. The prescaler is not used in the event counter mode. The modulo-N register is a buffer whose function is to save the value that was most recently output to port 7. The modulo-N register is used in all three timer modes. Any of three conditions cause the prescaler to be reset: whenever the timer is stopped by clearing ICP bit 3, on execution of an output instruction to port 7 (the timer is assigned port address 7), or on the trailing edge transition of the EXT INT pin when in the pulse width measurement mode. These last two conditions are Interval Timer Mode - When ICP bit 4 is cleared (logic 0) and at least one prescale bit is set, the timer operates in the interval timer mode. When bit 3 of the ICP is set, the timer starts counting down from the modulo-N value. After counting down to H '01', the timer returns to the 4-12 F3870 error over many intervals is zero. The prescaler and timer generate precise intervals for setting the timer interrupt request latch, but the time-out may occur at any time within a machine cycle. (There are two types of machine cycles: short cycles that consist of four", clock periods, and long cycles that consist of6 '" clock periods.) In the multi-chip F8 family, there is a signal referred to as the write clock, which corresponds to a machine cycle. Interrupt requests are synchronized with the internal write clock, thus giving rise to the possible ± 6 '" error. Additional errors may arise due to the interrupt request occurring while a privileged instruction or multi-cycle instruction is being executed. Nevertheless, for most applications, all of the above errors are negligible, especially if the desired time interval is greater than 1 ms. modulo-N value at the next count. On the transition from H '01' to H 'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch is set by the transition of H 'N' in the timer, thus allowing a full 256 counts if the modulo-N register is preset to H '00'. If bit 1 of the ICP is set, the interrupt request is passed .to the CPU section of the F3870. However, if bit 1 of the ICP is a logic 0, the interrupt request is not passed, but the interrupt request latch remains set. If ICP bit 1 is subsequently set, the interrupt request is then passed to the CPU. Only two events can reset the timer interrupt request latch: when the timer interrupt request is acknowledged by the CPU, or when a new load of the modulo-N register is performed. Consider an example in which the modulo-N register is loaded with H '64' (decimal 100). The timer interrupt request latch is set at the 100th count following the timer start, and the timer interrupt request latch is repeatedly set on precise 100-count intervals. If the prescaler is set at + 40, the timer interrupt request latch is set every 4000 '" clock periods. For a 2 MHz '" clock (4 MHz time base frequency), this produces 2 ms intervals. Pulse Width Measurement Mode - When ICP bit 4 is set (logic 1) and at least one prescale bit is set, the timer operates in the pulse width measurement mode. This mode is used for accurately measuring the duration of a pulse applied to the EXT INT pin. The timer is stopped and the prescaler is reset when the EXT INT pin is at its inactive level. The active level of EXT INT is defined by ICP bit 2: if cleared, EXT INT is active-low; if set, EXT INT is active-high. If ICP bit 3 is set, the prescaler and timer start counting when EXT INT transfers to the active level. When EXT INT returns to the inactive level, the timer stops, the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external interrupts are not latched if the ICP interrupt enable bit is not set.) The range of possible intervals is from 2 to 51,200 '" clock periods (1 ,.s to 25.6 ms for a 2 MHz clock). However, approximately 50 '" periods is a practical minimum because the time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine is at least 29 '" periods (the response time is dependent upon how many privileged instructions are encountered when the request occurs). To establish time intervals greater than 51,200 clock periods is simply a matter of using the timer interrupt service routine to count the number of interrupts, saving the result in one or more of the scratch pad registers until the desired interval is achieved. With this technique, virtually any time interval, or several time intervals, may be generated. As in the interval timer mode, the timer may be read at any time, or may be stopped at any time by clearing ICP bit 3, the prescaler and the ICP bit 1 function as previously described; the timer still functions as an a-bit binary down counter with the timer interrupt request latch being set on the timer's transition from H '01 ' to H' N' (modulo-N value). Note that the EXT INT pin has nothing to do with loading the timer; its action is that of automatically starting and stopping the timer and of generating external interrupts. Pulse widths longer than the prescaler value times the modulo-N value are easily measured by using the timer interrupt service routine to store the number of timer interrupts in one or more scratch pad registers. The timer may be read at any time and in any mode using an input instruction (IN 7 or INS 7); this may take place on-the-fly without interfering with normal timer operation. The timer may also be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and resumes counting when bit 3 is again set. The prescaler, however, is reset whenever the timer is stopped; thus, a series of starts and stops results in a cumulative truncation error. As for accuracy, the actual pulse duration is typically slightly longer than the measured value because the status of the prescaler is not readable and is reset when the timer is stopped. Thus, for maximum accuracy, it is advisable to use a small-division setting for the prescaler. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests may be in error by ± 6", clock periods, although the cumulative 4-13 4 F3870 Event Counter Mode - When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer operates in the event counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer decrements on each transition from the inactive level to the active level of the EXT INT pin. The prescaler is not used in this mode but, as in the other two timer modes, the timer may be read at any time, or may be stopped at any time by clearing ICP bit 3; ICP bit 1 functions are previously described, and the timer interrupt request latch is set on the timer's transition from H /01 / to H' N / (modulo·N value). When an interrupt is allowed, the CPU requests that the interrupting element pass its interrupt vector address to the program counter via the data bus. The vector address for a timer interrupt is H '20'; the vector address for an external interrupt is H 'OAO'. After the vector address is passed to the program counter, the CPU sends an acknowledge signal to the appropriate interrupt request latch, which clears that latch. The execution of the interrupt service routine then commences. The return address of the original program is automatically saved in the stack register, P. Power-On Clear The F3870 contains power-on clear circuitry to automatically reset the internal logic following the application of external power. Since many variations of power supply circuitry exist, Fairchild cannot guarantee that the power·on clear will operate under every power-up condition. Normally, ICP bit 0 should be kept cleared in the event counter mode; otherwise, external interrupts are generated on the transition from the inactive level to the active level of the EXT INT pin. For the event counter mode, the minimum pulse width required on the EXT INT pin is 2 '" clock periods, and the minimum inactive time is 2 '" clock periods; therefore, the maximum repetition rate is 500 Hz. The power-on clear circuitry contains on-chip sensors to monitor various conditions. The following conditions must be satisfied before the power-reset sequence is allowed to start: 1. Supply voltage must be above a certain value, typically +3 V to +4 V. 2. The clocks of the device must be functioning. 3. The substrate bias must reach a certain level. External Interrupts When the timer is in the interval timer mode, the EXT INT pin is available for non-timer-related interrupts. If ICP bit o is set, an external interrupt request latch is set when there is a transition from the inactive level to the active level of the EXT INT pin (EXT INT is an edge-triggered input). The interrupt request is latched until either acknowledged by the CPU or ICP bit 0 is cleared (unlike timer interrupt requests, which remain latched even when ICP bit 1 is cleared). External interrupts are handled in the same fashion when the timer is in the pulse width measurement mode or in the event counter mode, except that in the pulse width measurement mode the external interrupt request latch is set on the trailing edge of the EXT INT input; that is, on the transition from the active level to the inactive level. All three conditions must be met before the power-on clear circuitry initiates a reset cycle. However, these conditions can be satisfied even with a supply voltage of as low as 3 volts. The latest versions of the F3870 have a modified delay circuit that gives a typical delay of 500 liS (with a 4 MHz crystal) after the above conditions are met. This is an improvement over the earlier F3870 versions. Since the F3870 is only guaranteed to operate at a supply voltage of 4.5 V or greater, the user must ensure that the supply voltage is at least 4.5 V when the F3870 initiates the reset cycle. For power supplies having a slow rise time, an external RC network can be converted to the external reset input of the F3870 to hold the device in a reset state long enough to allow the power supply to reach a voltage of 4.5 V. Interrupt Handling When either a timer or an external interrupt request is communicated to the CPU section of the F3870, it is acknowledged and processed at the completion of the first non-privileged instruction if the interrupt control bit of the status register is set. If the interrupt control bit is not set, the interrupt request continues either until the interrupt control bit is set and the CPU acknowledges the interrupt or until the interrupt request is cleared as previously described. +5V ~ R F3870 If there are a timer interrupt request and an external interrupt request when the CPU starts to process the requests, the timer interrupt is handled first. 4-14 EXTERNAL RESET ::2S: F3B70 External Reset When the RESET input is low, the contents of the program counter are pushed to the stack register and the program counter and the 1GB of the status register are cleared. The original stack register contents are lost. As with power-on clear, ports 4, 5, 6, and 7 are loaded with H '00'. The contents of all other reg isters and ports are unchanged. When RESET is high, the first program instruction is fetched from ROM location H '0000'. Fig. 6 F3870 Clock Configurations Crystal Mode External Mode OPEN AT CUT 1 - 4 MHz Test Logic Special test logic is implemented to allow access to the internal main data bus for test purposes. EXTERNAL CLOCK LC Mode RC Mode Vee Ixi'l ~'* In normal operation, the TEST pin is unconnected or is connected to ground. When TEST is placed at a level of from 2.8 V to 3.0 V, port 4 becomes an output of the internal data bus and port 5 becomes a wired-OR input to the internal data bus. The data appearing on the port 4 pins is logically true, whereas input data forced on port 5 must be logically false. When TEST is placed at a high level (8.8 V to 9.0 V), the ports act as described above and, additionally, the program ROM is prevented from driving the data bus. In this mode, operands and instructions may be forced externally through port 5 instead of being accessed from the program ROM. When TEST is in either the TTL state or the high state, STROBE ceases its normal function and becomes a cycle clock (identical to the F8 multi-chip system write clock, except inverted). R CmERNAl (OPTIONAL-CAN ..L BE OMITTED) L_-i~_.J CEXTERNAl (OPTIONAL) Minimum L=O.l mH Minimum Q = 40 C = 20.5 pF ± 2.5 pF + CEXTERNAL Maximum CEXTERNAL = 30 pF 1 fMIN =1.1 RC+65ns C = 10 pF ± 1.3 pF + CEXTERNAL f MAX = 1.0RC+15ns Timing complexities render the capabilities associated with the TEST pin impractical for use in a user application, but these capabilities are sufficient to enable Fairchild to implement a rapid method for thoroughly testing the F3870. Example with CEXTERNAL = 0 Example with CEXTERNAL = 0 R= 15 kO± 5% f '" 2.9 MHz±26% L=0.3mH±10% f'" 3.0 MHz± 10% Instruction Set The F3870 executes the entire instruction set of the multi-chip F8 family (F3850 family), as shown in Table 3. Of course, the STORE instruction is of little use in the F3870 because only read·only memory exists in the addressing range of the data counter (the data counter, however, is incremented if STORE is executed). F3870 Clocks The time bases for the F3870 may originate from one of four external sources; the four external configurations are shown in Figure 6. There is an internal 26.5 pF capacitor between XTL 1 and GND, and also between XTL2 and GND. Thus, external capacitors are not required. In all external clock modes, the external time base frequency is divided by 2 to form the internal 1> clock. A summary of programmable registers and ports is given in Figure 7. AlSO, for convenient reference, a programming model of the F3870 is given in Figure 8. 4-15 • F3870 Table 3 F3870 Instruction Set Accumulator Group Instructions Operation Add Carry Add Immediate AND Immediate Clear Compare Immediate Complement Exclusive OR Immediate Increment Load Immediate Load Immediate Short OR Immediate Shift Left One Shift Left Four Shift Right One Shift Right Four Mnemonic OP Code LNK AI NI CLR CI COM XI INC U US 01 SL SL SR SR Operand ii ii ii ii ii i ji 1 4 1 4 Function ACC-(ACC)+ CRY ACC-(ACC) + H'ii' ACC-(ACC) A H'ii' ACC-H'OO' H'ii' + (ACC) + 1 ACC-(ACC) .. H'FF' ACC-(ACC) .. H'ii' ACC-(ACC)+ 1 ACC-H'ii' ACC-H'Oi' ACC-(ACC) V H'ii' SHIFT LEFT 1 SHIFT LEFT 4 SHIFT RIGHT 1 SHIFT RIGHT 4 Machine Code Bytes Cycles 19 24 ii 21 ii 70 25 ii 18 23 ii IF 20 ii 7i 22 ii 13 15 12 14 1 2 2 1 2 1 2 1 2 1 2 1 1 1 1 1 2.5 2.5 1 2.5 1 2.5 1 2.5 1 2.5 1 1 1 1 Status Bits OVF ZERO CRY SIGN 110 I/O 0 110 I/O 110 I/O I/O 0 110 I/O I/O I/O 0 0 I/O 110 I/O I/O I/O 110 0 0 I/O 110 I/O I/O 110 - - - 0 0 0 0 0 110 I/O I/O 1 1 - 0 0 0 0 0 - I/O I/O I/O I/O 1/0 Branch Instructions (In All Conditional Branches, PO (PO) + 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.) Mnemonic Operation Branch Branch Branch Branch on on on on Carry Positive Zero True OP Code Operand BC BP BZ BT aa aa aa t,aa Function PO-I(PO)+ PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ lJ+ lJ+ lJ+ lJ+ H'aa' H'aa' H'aa' H'aa' if if if if CRY; 1 SIGN; 1 ZERO; 1 any test is true Machine Code Bytes 82 aa al aa 84 aa 8t aa 2 2 2 2 Cycles 3/3.5" 3/3.5"" 3/3.5"" 3/3.5"" Status Bits OVF ZERO CRY SIGN - - - - - - - - - t; TEST CONDITION I 22 1 21 J 2° I IZERO I CRY I SIGN I Branch if Negative Branch Branch Branch Branch if if if if No Carry No Overflow Not Zero False Test BM BNC BNO BNZ BF aa aa aa aa t,aa PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ lJ+ lJ+ lJ+ lJ+ lJ+ H'aa' if SIGN; 0 H'aa' if CARRY ",0 H'aa' if OVF; 0 H'aa' if ZERO;O H'aa' if all false test bits 91 aa 92 aa 98aa 94 aa 9t aa 2 2 2 2 2 3/3.5"" 3/3S" 3/3.5"" 3/3.5"" 3/3.5"" - - - aF aa 2 90aa 29 aaaa 2 3 2.5 2.0 3.5 5.5 - - - - - t; TEST CONDITION I 23 I 22 I 21 I 2° I I OVF IZERO ICRY I SIGN I Branch if ISAR (Lower) 7 BR7 aa Branch Relative Jump" BR JMP aa aaaa PO-[(PO)+ lJ+ H'aa' if ISARL",7 PO-(PO)+ 2 if ISARL; 7 PO-[(PO)+ lJ+ H'aa' PO-H'aaaa' - - - Memory Reference Instructions (In All Memory Reference Instructions, the Data Counter Is Incremented DC-DC.1.) Operation Add Binary Add Decimal AND Compare Exclusive OR Load Logical OR Store Mnemonic OP Code AM AMD NM CM XM LM OM ST Operand Function ACC-(ACC)+ [(DC)J ACC-(ACC)+ [(DC)J ACC-(ACC) A [(Dc)J [(DC)J + (ACC) + 1 ACC-(ACC) .. [(DCIl ACC-[(DCIl ACC-(ACC) V [(DC]) (DC)-(ACC) "Privileged instruction "" 3.5 cycles if branch taken. Note JMP and PI change accumulator contents to the high byte address. 4·16 Machine Code 88 89 aA aD 8C 16 8B 17 Bytes Cycles 1 1 1 1 1 1 1 1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Status Bits OVF ZERO CRY 110 110 0 110 0 110 110 110 110 110 - - 0 110 - - 110 110 0 110 0 0 - SIGN 110 110 110 110 110 110 - F3870 F3870 Instruction Set (Cont.) Table 3 Address Register Group Instructions Operation Mnemonic OP Code Add to Data Counter Call to Subroutine Call to Subroutine Immediate Exchange DC Load Data Counter Load Data Counter Load DC Immediate Load Program Counter Load Stack Register Return From Subroutine Store Data Counter Store Data Counter Store Stack Register ADC PK' PI' XDC LR LR DCI LR LR POP' LR LR LR Operand aaaa DC,Q DC,H aaaa PO,Q P,K Q,DC H,DC K,P Function DC-(DC)+ (ACC) P-(PO); POU-(rI2); PL-(rI3) P-(P); PO- H'aaaa't DC-DCl DCU-(rI4); DCL-(rlS) DCU-(rl0); DCL-(rll) DC-H'aaaa' POU-(rI4); POL-(rlS) PU-(rI2); PL-(rI3) PO-(P) rI4-(DCU); rlS-(DCL) rl0-(DCU); rll-(DCL) rI2-(PU); rI3-(P) Machine Code Bytes Cycles OVF 8E OC 28 aaaa 2C OF 10 2A aaaa 00 09 lC OE 11 08 1 1 3 1 1 1 3 1 1 1 1 1 1 2.S 4 6.S 2 4 4 6 4 4 2 4 4 4 - Machine Code Bytes Cycles OVF Cr Dr 3r 4r 00 01 02 03 Sr 04 OS 06 07 Fr Er 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 I.S 1 1 1 1 1 1 1 1 1 1 1 1 110 110 110 Machine Code Bytes Cycles OVF lA lB 26 aa Aa OB 01101a" 01100a" 10 26 27 aa Ba OA IE 1 1 2 1 1 1 1 1 1 2 1 1 1 2 2 4 4'" 1 1 1 2 1 4 4'" 1 1 - - 0 0 110 110 - - - 110 - - - Status Bits ZERO CRY - - - - - - - SIGN - - - Scratch pad Register Instructions (Refer to Scratchpad Addressing Modes) Operation Mnemonic OP Code Operand AS ASD OS LR LR LR LR LR LR LR LR LR LR NS XS r r r A,r A,KU A,KL A,QU A,QL r,A KU,A KL,A QU.A QL,A r r Mnemonic OP Code Operand Add Binary Add Decimal Decrement Load Load Load Load Load Load Load Load Load Load AND Exclusive OR Function ACC-(ACC)+ (r) ACC-(ACC)+ (r) r-(r)+ H'FF' ACC-(r) ACC-(rI2) ACC-(rI3) ACC-(rI4) ACC-(rlS) r-(ACC) rI2-(ACC) rI3-(ACC) rI4-(ACC) rI5-(ACC) ACC-(ACC) A (r) ACC-(ACC)e(r) Status Bits ZERO CRY 110 110 110 110 110 110 - - - - - - 0 0 110 110 0 0 SIGN 110 110 110 - - 110 110 Mtscellaneous Instructions Operation Disable Interrupt Enable Interrupt' Input Input Short Load ISAR Load ISAR Lower Load ISAR Upper Load Status Register' No-Operation Output Output Short Store ISAR Store Status Register 01 EI IN INS LR LlSL LlSU LR NOP OUT OUTS LR LR aa a IS.A a a W,J aa a A,IS J,W Function RESET ICB SET ICB ACC-(INPUT PORT aa) ACC-(INPUT PORT a) ISAR-(ACC) ISARL-a ISARU-a W-(r9) PO-(PO)+ 1 OUTPUT PORT aa-(ACC) OUTPUT PORT a-(ACC) ACC-(ISAR) r9-(W) "Privileged instruction "3-bit octal digit '''Two machine cycles for CPU ports tContents of ACC destroyed 4-17 Status Bits ZERO CRY - - SIGN - 0 0 110 110 - - 110 110 110 - - - - • F3870 Table 3 F3870 Instruction Set (Cont.) Not•• Each lower case character represents a hexadecimal digit. Each cycle equals four machine clock periods. Lower case denotes variables specified by the programmer. J K Kl KU PO POL POU P Pl PU Q Ql QU r Function Deflnltons is replaced by () the contents of (-) binary ones complement of + arithmetic add (binary or decimal) .. logical OR exclusive A logical AND V logical OR inclusive H'#' hexadecimal digit Register a A DC DCl DCl DCU H i and ji ICB IS ISAR ISARl ISARU Names address variable accumulator data counter (indirect address register) data counter #1 (auxiliary data counter) least significant eight bits of data counter addressed most significant eight bits of data counter addressed scratchpad register #10 and #11 immediate operand interrupt control bit indirect scratchpad address register indirect scratchpad address register least significant three bits of ISAR most significant three bits of ISAR W scratchpad register #9 registers #12 and #13 register #13 register #12 program counter least significant eight bits of program counter most significant eight bits of program counter stack register least significant eight bits of program counter most significant eight bits of active stack register registers #14 and #15 register #15 register #14 scratchpad register (any address through 11) status register Scratchpad Addressing Modes (Machine Code Format) r= C (hexadecimal) register addressed by ISAR (unmodified) r= D (hexadecimal) register addressed by ISAR; ISARl incremented r= E (hexadecimal) register addressed by ISAR; ISARl decremented r= F (no operation performed) r= O-B (hexadecimal) register 0 through 11 addressed directly from the instruction Status Register no change in condition 110 is set to 1 or 0, depending on conditions CRY carry flag Mask Options 3. Input/output ports 0 and 1 can be specified either cleared or unaltered following an external reset. 4. External interrupt and external reset can be specified to have or omit an internal pull-up resistor. 5. The 110 port output option choices are: the standard pull-up (option A), the open drain (option B), and the driver pull-up (option C). The ROM array may contain object program code and/or tables of nonvarying data. Every F3870 is implemented using a custom mask that specifies the state of every ROM bit, as well as certain address mask options that are external to the ROM array. The following mask options are specified: 1. The 1024, 2048, 3072, or 4096 bytes of ROM storage. This reflects programs and permanent data tables stored in the PSU memory. 2. Input/output ports can be any of the following three configurations: a. Standard pull-up b. Open drain c. Direct drive The format for mask options must be submitted to Fairchild Microprocessor Division before device manufacture. The data to be stored in permanent memory may be submitted in the form of an EPROM or HP2644/HP2645 cartridge (Formulator format only). Other options must be specified on the Fairchild ROM Code Entry Form, available from a Fairchild representative. 4-18 F3870 Fig. 7 Programmable Registers and Ports ACCUMULATOR I I A hi oIz Icisl STATUS REGISTER W BYTE ADDRESS SCRATCHPAD DEC I 4 3 INDIRECT SCRATCHPAO ADDRESS REGISTER 0 I I IS HEX OCT A 12 0 2 11 AUX DATA COUNTER I 11 DCl HU 10 H 11 B 12 C ,. KL 13 0 15 11 DATA COUNTER I 0 1 DC 13 HL KU I OU 16 " 15 OL 17 16 10 20 11 STACK REGISTER I I I P § 11 PROGRAM COUNTER I PO BINARY TIMER PORT INTERRUPT CONTROL PORT PORT 6 58 3A 72 59 3B 73 60 3C 7. 61 3D 75 62 3E 76 63 3F 77 1/0 PORT 0 7 I/O PORT 1 I/O PORT 4 I L-__________~~STROBE 110 PORT 5 4·19 • Fig. 8 Programming Model r----------------------------•.-,I I ~~ J----, (PO) STATUS ------.11 rl OUTS 7 ADC INS*7 '-1 OUTS 6 INS" 6 ISAft OUTS P. (P 0.1.4,5) 110 INS·P. (P 0,1.4.5) LISU PORTS (4) 5 V VOLTS LOGIC '0' ON 110 PINS SCRATCHPAD REGISTERS AUX DATA COUNTER 101 1_ ~ 11 ~ H U 12 L 13 a 'U'ii ¥-*I T 1 - - r(lS)=T I. LR Iii ,. I. +1.0) ." os· PROGRAM ROM HEX OCTAL * These instructions set status ; The value of the external interrupt input is loaded to bit 7 of the accumulator (with bits 0 through 6 loaded with zeros) when the instruction 'INS 6' is executed. This instruction also sets status. H '000' --.:=:.:.-____~.I RESET transfers P09 to P and tt PO. P, DC, and DCl are 12·bit registers. then clears PO, leB bit 01 W, EXTERNAL INTERRUPT INPUT (+5 V "" LOGIC 1) and Ports 4, 5, 6, and 7. Not.: The instructions PI and PK are shown in two sequential parts (PH, P12, and PK1, PK2). '''(00 ~ ~ F3870 Supplementary Notes This nomenclature is used to be consistent with the assembly language mnemonics. For total software compatibility when expanding into a multi-chip configuration, the F3871 Peripheral Input/Output circuit should be used. The F3871 has the same improved timer (binary count, readable, and three modes of operation) and ready strobe outputs as the F3870. For the F3870, execution of an INS or OUTS instruction requires two machine cycles for ports 0 and 1, whereas ports 4 and 5 require four machine cycles. When an external reset of the F3870 occurs, PO pushes into P and the old contents of P are lost. It must be noted that an external reset is recognized at the start of • the machine cycle and not necessarily at the end of an instruction. Thus, if the F3870 is executing a multi-cycle • instruction, that instruction is not completed and the contents of P upon reset may not necessarily be the address of the instruction that would have been executed next. It may, for example, point to an immediate operand if the reset occurred during the second cycle of an L1 or C1 instruction. Additionally, several instructions (JMP, P1, PK, LR, PO and Q) as well as the interrupt acknowledge sequence modify PO in parts. That is, they alter PO by loading first one part, then the other, and the entire operation takes more than one cycle. Should reset occur during this modification process, the value pushed into P is part of the old PO (the as-yet unmodified part) and part of the new PO (already-modified part). Thus, care should be taken (perhaps by external gating) to ensure that reset does not occur at an undesirable time if any significance is to be given to the contents of P after a reset occurs. The interrupt control bit of the status register is automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine when the ICB is again to be set (by executing the E1 instruction). This action prevents an interrupt service routine from being interrupted unless the programmer so desires. When reading the interrupt control port (port 6), bit 7 of the accumulator is loaded with the actual logic level being applied to the EXT INT pin, regardless of the status of ICP bit 2 (the EXT INT active level bit); that is, if the EXT INT pin is at + 5 V, bit 7 of the accumulator is set to a logic 1, but if the EXT INT pin is at ground, accumulator bit 7 is reset to logic O. In Tab/e 3, the number of cycles shown is "nominal machine cycles." A nominal machine cycle is defined as 4 CLOCK 110 PORT OUTPUT EXT INT ICPBIT { dI:: L ::I ICP BIT 2=1 Note All measurements are referenced to VIL max, VIH min, VOL max, or VOH min 4·23 tEH F3870 Fig. 10 Port Input/Output Timing Diagrams A. Input on Port 4 or 5 INTERNAL WRITE CLOCK IN OR INS OPCODE FETCHED PORT PINS PORT ADDR. PLACED ON DATA BUS PORT DATA DRIVEN ON TO DATA BUS NEXT OPCODE FETCHED ------' ·Cycle timing shown for 4 MHz external clock B. Output on Port 4 or 5 INTERNAL WRITE CLOCK OUT OR OUTS OPCODE FETCHED PORT AOOR. ON DATA BUS ACCUMULATOR CONTENTS ON DATA BUS PORT PINS NEXT OPCODE FETCHED -------r--'~~----- STROBE (ACTIVE FOR PORT. ONLY) STAYS LOW FOR TWO WRITE CYCLES tll()'S 500 ns' MIN ·Cycle timing shown for 4 MHz external clock c. Input on Port 0 or 1 D. Output on Port 0 or 1 INTERNAL WRITE CLOCK INTERNAL WRITE CLOCK OUTSO.1 FETCHED PORT PINS ·Cycle timing shown for 4 MHz external clock ACCDATA ON BUS ----+-"""' ·Cycle timing shown tor 4 MHz external clock 4·24 NEXT OPCODE FETCHED F3870 DC Characteristics Absolute Maximum Ratings The dc characteristics of the F3870 are described in Table 5. These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Voltage on any Pin with Respect to Ground (Except Open-Drain Pins) Voltage on any Open-Drain Pin Power Dissipation Ambient Temperature Under Bias Storage Temperature Table 5 Symbol DC Characteristics -1.0V,+7V - 1.0 V, + 13.2 V 1.5W O·C, + 70 ·C - 55·C, + 150·C T A = O·C to + 70·C, Vee = + 5 V ± 10%, I/O power dissipation s 100 mW Characteristic Min Conditions Max Unit 100 mA Outputs Open 550 mW Outputs Open Icc Power Supply Current Po VIHEX Power Dissipation VILHEX IHEX External Clock Input LOW Voltage IILEX V IH External Clock Input LOW Current Input HIGH Voltage 2.0 5.8 V V IL Input LOW Voltage -0.3 0.8 V IIH Input HIGH Current (Except Open-Drain and Direct-Drive I/O Ports) 100 p.A V IH = 2.4 V, Internal Pull-Up IlL Input LOW Current (Except Open-Drain and Direct-Drive Ports) -1.6 mA V IL =O.4 V p.A Pull-Down, Device Off, V OH =13.2 V p.A VoH =2.4 V mA VoH =0.7 V to 1.5 V mA p.A VOL =O.4 V VOH =2.4 V mA VOL =0.4 V External Clock Input HIGH Voltage 2.4 -0.3 External Clock Input HIGH Current ILOO Leakage Current (Open-Drain Ports) IOH Output HIGH Current (Except Open-Drain and Direct-Drive Ports) IOHOO Output Drive Current (Direct-Drive Ports) IOL Output LOW Current IOHS Output HIGH Current (STROBE Output) IOLS Output LOW Current (STROBE Output) 5.8 0.6 p.A V IHEX =2.4 V -100 p.A V ILEX =0.6 V -100 1.8 -300 5.0 4-25 V 100 ±10 -1.5 V -8.0 F3870 Ordering Information Order Code F3870DC Package Temperature Range· Ceramic C F3870DL Ceramic L F3870DM Ceramic M F3870PC Plastic C 'C = Commercial Temperature Range O'C to + 70'C L= Limited Temperature Range - 40'C to + 85'C M = Military Temperature Range - 55'C to + 125'C I 4-26 F3870AlF3870B High-Speed Single-Chip Microcomputer FAIRCHILD A Schlumberger Company Microprocessor Product Advance Product Information Description The Fairchild F3870A and F3870B are advancements in the F3870 series of single-chip microcomputers. The F3870A and F3870B offer higher instruction execution speed, thereby improving the throughput of the microcomputer. • Fully Hardware- and Software- Compatible with the F3870 Series of Microcomputers • The F3870A Offers An Instruction Cycle Time of 1.33 I-'sec, and the F3870B Cycle Time is 1 I-'sec. • Mask Option Internal Clock Divider Unit Clock Crystal Frequency Without With Internal + 2 Internal +2 F3870 F3870A F3870B 3 MHz 4 MHz 4 MHz 6 MHz 8 MHz Cycle Time 21-'s 1.331-'s 1 I'S For additional information, see the F3870 data sheet 4-27 F3870A/F3870B 4-28 F38C70 FAIRCHILD Single-Chip Microcomputer A Schlumberger Company Microprocessor Product Connection Diagram 40-Pin DIP Description The Fairchild F38C70 8-bit single-chip microcomputer is a member of the F387X series; it executes all of the F8 instruction set and is software-compatible with the F3870. Additional power-save instructions provide two different power-save modes. • • • EXT INT l'O2 po, STROBE P50 ps, 1'40 P4i P42 P43 P44 More than 70 commands of the F8 instruction set are executed by the single-chip microcomputer, which features 2048 bytes of ROM, 64 bytes of scratch pad RAM, a programmable timer, 32 bits of 1/0, and a- Single + 5 V power supply. • • • • Vee RESET POo Implemented in ion-implanted CMOS doublepoly silicongate technology, the F38C70 offers maximum cost effectiveness in a wide range of applications requiring very low power consumption. • • • • • • XTl, XTL2 PS, PS:i PS. P4,; P5s 1'46 P5s 1'57 P47 Single CMOS Integrated Circuit Software-Compatible with F8 and F3870 2048·Byte Mask Programmable ROM 64-Byte Scratchpad RAM 32·Bit 110 with Four Options 8·Blt Programmable Timer with 16·Bit Programmable Prescaler External Interrupt Crystal, LC, RC, or External Clock Single + 5 V (:t 10%) Power Supply Power·Save (PS) and Power·Save All (PSA) Modes Option for all Short Machine Cycles Direct Replacement for F3870 Low Power (SO mW typ., 5 mW in PS mode, 0.5 mW in PSA mode) Po; P17 P1, P15/Ao PO. P14/A, Vss TEST (Top View) Signal Functions CLOCK {~ _ XTL1 XTL, 110 PORT PORT ADDRESS INTERRUPTI RESET STROBE Vee TEST 4-29 ""'-1 L -_ _ _---J Vss - - POWER F38C70 Figure 1 Block Diagram INTERRUPT ADDRESS VECTOR XT~-1 XTL,-2 RESET-38 TEST-21 P00-3 Piij-4 P02-5 110 PORT 0 POi-6 PD.-19 POS-18 Pii;-17 ~==:::-t--_ P07-16 I/O PORT 1 P40-8 "P4,-9 P4,-'O 110 PORT 4 L..._..,.._.....I:---~ ii4;-11 P4;-12 ii45-13 ii46-14 i"i7-15 L-_ _ _ _ _ STROBE-7 r-------~~~~-" P5;-32 P52-31 PS;-30 110 PORT 5 P5.-29 PsS-28 Ps;-27 P5r-28 4·30 F38C70 Main Control Logic contiguous scratchpad bytes. For example, when the ioworder octal digit is incremented or decremented, the ISAR is incremented from octal 27 (0'27) to 0'20' or is decremented from 0'20' to 0'27'. This feature of the ISAR is very useful in many program sequences. The instruction register (IR) receives the operation code (OP code) of the instruction to be executed from the program ROM through the data bus. Eight bits are latched into the IR during all OP code fetches. Some instructions are completely specified by the upper four bits of the OP code; in these instructions, the lower four bits are an immediate register address or an immediate 4·bit operand. Once latch· ed into the IR, the main control logic decodes the instruction and provides the necessary control gating signals to all circuit elements. All six bits of the ISAR can be loaded at one time, or either half can be loaded independently. The decimal scratch pad registers (9 through 15) are given mnemonic names (J, H, K, and Q) because of special linkages between these and other registers, such as the stack register. These special linkages simplify the performance of multi·level interrupts and subroutine nesting. For example, the instruction LR K,P stores the lower eight bits of the stack register into register 13 (K lower, or KL) and stores the upper three bits of P into register 12 (K upper, or KU). ROM Address Registers Four 12·bit registers are associated with the program ROM: program counter PO, stack register P, data counter DCO, and auxiliary data counter DC1. The program counter is us· ed to address instructions or immediate operands; the stack register is used to save the contents of PO during an interrupt or subroutine call. Thus, P contains the return address at which processing is to resume upon completion of the subroutine or the interrupt routine. Arithmetic and Logic Unit (ALU) After receiving commands from the main control logic, the ALU performs the required arithmetic or logic operations (using the data presented on the two input buses) and pro· vides the result on the result bus. The arithmetic operations performed in the ALU are binary add, decimal adjust, add with carry, decrement, and increment. The logic operations performed are AND, OR, exclusive·OR, ones complement, shift right, and shift left. The ALU also provides four signals presenting the status of the result. These signals, stored in status register W, represent the carry, overflow, sign, and zero condition of the operation. The data counter is used to address data tables. This register is autoincrementing. Of the two data counters, only DCO can access the ROM; however, the XDC instruction allows DCO and DC1 to be exchanged. Associated with the address registers is a 12·bit adderl incrementer. This logic element is used to increment PO or DC when required and to add displacements to PO on relative branches or to add the data bus contents to DCO in the add data counter (ADC) instruction. Accumulator The accumulator (ACC) is the prinicpal register for data manipulation within the F38C70. The ACC serves as one in· put to the ALU for arithmetic or logic operations; the results of ALU operations are stored in the ACC. Program ROM The microcomputer program and data constants are stored in the 2048 X 8 byte program ROM. When a ROM access is required, the appropriate address register (PO or DCO) is gated onto the ROM address bus and the ROM output is gated onto the main data bus. The first byte in the ROM is location zero. Status Register The status (W) register holds five status flags: SUMMARY OF STATUS BITS Scratchpad and ISAR The scratch pad provides 64 8-bit registers that can be used as general purpose RAM memory. The indirect scratchpad address register (lSAR) is a 6-bit register used to address the 64 registers. All 64 registers can be accessed using the ISAR. In addition, the lower order 12 registers can also be directly addressed. OVERFlOW=CARRY7 ZERO CARRY =CARRY7 SIGN =ALU 7 ' - - - - - - - INTERRUPT CONTROL BIT The ISAR can be visualized as holding two octal digits. This division of the ISAR is important, since a number of instructions increment or decrement only the least significant three bits of the ISAR when referencing scratch pad bytes through the ISAR. This simplifies referencing a buffer of 4·31 I!I CAARY s = ALU7 A ALU e A Alli5 A ALU 4 A ALU3 A ALU2 A ALU, A AOJo F38C70 Interrupt Control Bit The interrupt control' bit (ICB) is used to allow or disallow interrupts in the F38C70. (This bit Is not the same as the two Interrupt enable bits in the interrupt control port.) If the ICB is set and the F38C70 interrupt logic communicates an interrupt request to the CPU section, the interrupt is acknowledged and processed upon completion of the first non-privileged instruction. If the ICB is cleared, an Interrupt request is not acknowledged or processed until the ICB is set again. An output ready strobe is associated with port 4. This flag Is used to signal a peripheral device that the F38C70 has just completed an output of new data to port 4. Because the strobe provides a single low pulse shortly after the output operation is complete, either edge can be used to signal the peripheral. The STROBE signal is also used to re quest new input Information from a peripheral by performing a dummy output of H'OO' to port 4 after completing the input operation. Four output drive options are available for the F38C70 1/0 ports. Individual bits of the four I/O ports are configured as 1/0 Ports The F38C70 provides four complete bidirectional put ports: 0, 1, 4, and 5. In addition, the in'terrupt port is addressed as port 6, and the binary timer ed as port 7. Ports 8 and 9 are the 16·bit holding the timer prescaler. input/out· control is address· register for An output instruction (OUT or OUTS) causes the contents of the ACCto be latched into the addressed port. An input instruction (IN or INS) transfers the contents of the port to the ACC (port 6, an exception, is described in the ~'Timer and Interrupt COhtrol Port") section. The 1/0 buffers on the F38C70 are logically inverted. Figure 2. 1. Open drain 2. CMOS 3-state push·pull buffer 3. TIL·compatible 4. CMOS push·pull buffer For the 3-state push·pull buffer, the 1/0 pin goes 3·state when executing an INS instruction to that port and remains in 3·state until an OUTS instruction is executed to that port Timer and Interrupt Control POrt Block Diagram EXTERNAL TIME BASE +2 INTERRUPT CONTROL PORT (PORT 8) ' Llli 3 EVENT COUNTER MODE 0 0 _ 0 0 + 2PRESCALE _ 0 1 + 5 PRESCALE _ 0 1 + 10 PRESCALE 0 _ 1 + 20 PRESCALE _ 1 0 .. 40 PRESCALE _ 1 1 + 100 PRESCALE + 200 PRESCALE 1 1 ~ANDlpORT18 + 200 PRESCALE USE 18-BI1 DATA IN PORT 8 AND PORT 8 1 1 1 2 1 0 1 0 1 0 L.= AN~ PORT~9"'~-0-----· AND PORT 8 OR PORT 9 1---+l1~1~~~ MODULO-N REGISTER 8-BITS INTERRUPT LOGIC *0 LATCH O ___ BIT NO. L 0 1 TIMER l1MER 8-BIT DOWN COUNTER (PORT 7) CLOCK PRESCALER EXTERNAL INTERRUPT ENABLE TIMER INTERRUPT ENABLE EXT INT ACTIVE LEVEL EXTERNAL INTERRUPT REOUEST LATCH STARTISTOP l1MER PULSE WIDTHnNTERVAL TIMER EXT INT AS PRESCALER VALUE 4·32 INT REO F38C70 Timer and Interrupt Control Port The timer is an S·bit binary down counter that is software· programmable to operate in one of three modes: interval timer, pulse width measurement, or event counter. As shown in figure 2, an S·bit register (interrupt control port), a programmable 16·bit prescaler, and an S·bit modulo·N register are associated with the timer. prescaler values are.;. 2, .;. 5, .;. 10, .;. 20,';' 40, .;. 100, and .;. 200. If bits 5, 6, and 7 of the interrupt control port are set, and the contents of either of the two prescaler registers are not zero, the timer uses the value that is held in the two registers as a 16·bit prescaler value. The timer mode, prescale value, timer start and stop, active level of the EXT INT pin, and interrupt local enable/disable are selected by the proper bit configuration output from the accumulator to interrupt control port 6 with an OUT or OUTS instruction. Bits within the interrupt control port are defined as follows: 1. When the timer is stopped by clearing ICP bit 3 2. When an output instruction to port 7 (the timer is assigned Port Address 7) is executed 3. On the trailing edge transition of the EXT INT pin when in the pulse width measurement mode Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 Any of three conditions will cause the prescaler to be reset: = External interrupt enable = Timer interrupt enable = EXT INT active level = Start/stop timer = Pulse width/internal timer = .;. 2 Prescaler control = .;. 5 Prescaler control An OUT or OUTS instruction to port 7 loads the contents of the accumulator to both the timer and the S·bit modulo·N register, resets the prescaler, and clears any previously stored timer interrupt request. The timer is an S·bit down· counter clocked by the prescaler in both the interval timer mode and the pulse width measurement mode. The prescaler is not used in the event counter mode. The modulo·N register is used as a buffer in all three timer modes. Its function is to save the value that was most recently output to port 7. = .;. 20 Prescaler control Timer The F38C70 timer, like the F3S70, is an S·bit programmable down counter. However, the F38C70 has two additional S·bit registers (ports Sand 9) that can be accessed by output in· structions. These registers can be used to generate very long interval timer interrupts or any desired prescaler value. Interval Timer Mode When ICP bit 4 is cleared (logic 0) and at least one prescale bit is set, the timer operates in the interval timer mode. When bit 3 of the ICP is set, the timer starts counting down from the modulo·N value. After counting down to H'01', the timer returns to the modulo·N value at the next count. On the transition from H'01' to H'N', the timer sets a timer in· terrupt request latch. Note that the interrupt request latch is set by the transition of H'N'in the timer, thus allowing a full 256 counts if the modulo-N register is preset to H'OO'. A special situation exists when reading the interrupt control port with an IN or INS instruction). The accumulator is not loaded with the content of the ICP; instead, accumlator bits o through 6 are loaded with zeros, and bit 7 is loaded with the logic level being applied to the EXT INT pin. Thus, the status of EXT INT can be determined without needing to service an external interrupt request. This capability is useful in establishing a high·speed polled handshake pro· cedure or for using EXT INT as an extra input pin if external interrupts are not required and the timer is used only in the interval timer mode. If bit 1 of the ICP is set, the interrupt request is passed on to the CPU section of the F38C70. However, if bit 1 of the ICP is a logiC 0, the interrupt request is not passed on the the CPU section, although the interrupt request latch reo mains set. If ICP bit 1 is subsequently set, the interrupt request is then passed on to the CPU section. (The inter· rupt request is acknowledged by the CPU section only if ICB is set.) Only two events reset the timer interrupt reo quest latch: the timer interrupt request is acknowledged by the CPU section, or a new load of the modulo·N register is performed. The rate at which the timer is clocked in the interval timer mode is determined by the frequency of an internal <1> clock and by the division value selected for the prescaler. (The in· ternal <1> clock operates at one·half the external time base frequency.) Assuming ports Sand 9 have been loaded with zeros, if ICP bit 5 is set and bits 6 and 7 are cleared, the prescaler divides <1> by two. In the same manner, if bit 6 or 7 is individually set, the prescaler divides <1> by 5 or 20, respectively. Combinations of bits 5, 6, and 7 may also be selected. For example, if bits 5 and 7 are set, while 6 is cleared, the prescaler will divide by 40. Thus, possible If the modulo·N register is loaded with H'64' (decimal 100), the timer interrupt request latch is set at the 100th count following the timer start and the latch is repeatedly set on precise 100·count intervals. If the prescaler is set at .;. 40, the timer interrupt request latch is set every 4000 4> clock :4·33 F38C70 periods. For a 2-mHz clock (4-mHz time base frequency), this produces 2 ms intervals. its inactive level. The active level of EXT INT is defined by ICP bit 2: if cleared, EXT INT is active low; if set, EXT INT is active high. If ports a and 9 are loaded with zeros, the range of possible intervals is from 2 to 51,200 clock periods (1 ,..s to 25.6 ms for a 2-mHz clock). However, approximately 50 periods is a practical minimum, because the time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine is at least 29 periods (the response time is dependent on how many privileged instructions are encountered when the request occurs). If ICP bit 3 is set, the prescaler and timer start counting when EXT INT transfers to the active level. When EXT INT returns to the inactive level, the timer stops, the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external interrupts are not latched if the ICP interrupt enable bit is not set.) As in the interval timer mode, the timer can be read at any time and can be stopped at any time by clearing ICP bit 3 (the prescaler and ICP bit 1 function as described in the interval timer mode section). The timer still functions as an a-bit binary down counter with the interrupt request latch set on the timer's transition from H'Ol' to H'N' (modulo-N value). Note that the EXT INT pin has nothing to do with loading the timer; its action is that of automatically starting and stopping the timer and of generating external interrupts. Pulse widths longer than the prescale value times the modulo-N value are easily measured by using the timer interrupt service routine to store the number of timer interrupts in one or more scratch pad registers. To establish time intervals greater than 51,200 clock periods, the 16-bit prescaler or the timer interrupt service routine can be used to count the number of interrupts, saving the result in one or more of the scratch pad registers until the desired interval is achieved. Virtually any time interval, or several time intervals, can be generated using this technique. The timer is read at any time and in any mode, using an input instruction (IN 7 or INS 7), and can take place "on-thefly" without interfering in normal timer operation. Also, the timer can be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and resumes counting when bit 3 is set again. The prescaler is reset whenever the timer is stopped; thus, a series of starting and stopping results in a cumulative truncation error. The actual pulse duration is typically slightly longer than the measured value, because the prescaler status is not readable and is reset when the timer is stopped. Thus, for maximum accuracy, it is advisable to use a small division setting for the prescaler. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests can be in error by ± 6 clock periods, although the cumulative error over many intervals is zero. The prescaler and timer generate precise intervals for setting the timer interrupt request latch, but the time out can occur at any time within a machine cycle. (There are two machine cycle types: short, which consist of 4 clock periods, and long, which consist of 6 clock periods.) The Fairchild multi-chip Fa family has a write clock signal that corresponds to a machine cycle. Interrupt requests are synchronized with the internal write clock, thus providing the possible ± 6 error. Additional errors may arise if the interrupt request occurs while a privileged instruction or multi-cycle instruction is being executed. Nevertheless, for most applications, all the above errors are negligible, especially if the desired time interval is greater than one ms. Event Counter Mode When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer operates in the event counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer will decrement on each transition from the inactive level to the active level of the EXT INT pin. The prescaler is not used in this mode. As in the other two timer modes, the timer can be read at any time and can be stopped at any time by clearing ICP bit 3, ICP bit 1 functions as previously described, and the timer interrupt request latch is set on the timer's transition from H'Ol' to H'N' (modulo-N value). Pulse Width Measurement Mode When ICP bit 4 is set (logic 1) and at least one prescale bit is set, the timer operates in the pulse width measurement mode. This mode is used to accurately measure the duration of a pulse applied to the EXT INT pin. The timer is stopped and the pref'caler is reset whenever EXT INT is at For the event counter mode, the minimum pulse width required on EXT INT is 2 clock periods and the minimum inactive time is 2 clock periods; therefore, the maximum repetition rate is 500 Hz. Normally, ICP bit 0 should be kept cleared in the event counter mode; otherwise, external interrupts are generated on the transition from the inactive level to the active level of the EXT INT pin. 4-34 F38C70 The power-on clear circuitry contains on-chip sensors to monitor various conditions. The following conditions must be satisfied before the power-reset sequence is allowed to start: External Interrupts When the timer is in the interval timer mode, the EXT INT pin is available for non-timer related interrupts. If ICP bit 0 is set,.an external interrupt request latch is set for a transition from the inactive level to the active level of EXT INT. (The EXT INT signal is an edge-triggered input.) The interrupt request is latched either until acknowledged by the CPU section or until ICP bit 0 is cleared (unlike timer interrupt requests that remain latched even when ICP bit 1 is cleared). External interrupts are handled in the same fashion when the timer is in the pulse width measurement mode or in the event counter mode, except that when in the pulse width measurement mode, the external interrupt request latch is set on the trailing edge of EXT INT (that is, on the transition from the active level to the inactive level). 1. Supply voltage must be above a certain value, typically + 3 V to + 4 V. 2. The clocks of the device must be functioning. 3. The substrate bias must reach a certain level. All three conditions must be met before the power-on clear circuitry initiates a reset cycle. However, these conditions can be satisfied even with a supply voltage of as low as 3 volts. The latest versions of the F38C70 have a modified delay circuit that gives a typical delay of 500 ".S (with a 4 mHz crystal) after the above conditions are met. This is an improvement over the earlier F38C70 versions. Interrupt Handling When either a timer or an external interrupt request is communicated to the CPU section of the F38C70, it is acknowledged and processed at the completion of the first non-privileged instruction if the interrupt control bit of the status register is set. If the interrupt control bit is not set, the interrupt request continues either until the interrupt control bit is set and the CPU section acknowledges the interrupt or until the interrupt request is cleared (as previously described). Since the F38C70 is only guaranteed to operate at a supply voltage of 4.5 V or greater, the user must ensure that the supply voltage is at least 4.5 V when the F38C70 initiates the reset cycle. For power supplies having a slow rise time, an external RC network can be converted to the external reset input of the F38C70 to hold the device in a reset state long enough to allow the power supply to reach a voltage of 4.5 V. For example: +5V If a timer interrupt request and an external interrupt request occur simultaneously, when the CPU section starts to pro· cess the requests, the timer interrupt is handled first. F387X When an interrupt is allowed, the CPU section requests that the interrupting element pass its interrupt vector address to the program counter through the data bus. The vector address for a timer interrupt is H'020'. The vector address for external interrupts is H'OAO'. After the vector ad· dress is passed to the program counter, the CPU section sends an acknowledge signal to the appropriate interrupt request latch, which clears that latch. The interrupt service routine executes; the return address of the original program is automatically stored in stack register P. External Reset When the RESET signal is taken low, the contents of the program counter are pushed to the stack register and the program counter and the ICB of the status register are cleared. The original stack register contents are lost. As with power-on clear, ports 4, 5, 6, and 7 are loaded with H'OO'. The contents of all other registers and ports are unchanged. When the RESET signal is taken high, the first program instruction is fetched from ROM location H'OOoo'. Power-On Clear The F38C70 contains power-on clear circuitry to automatically reset the internal logic following the application of external power. Since many variations of power supply circuitry exist, Fairchild cannot guarantee that the power-on clear will operate under every power-up condition. 4-35 F38C70 Figure 3 Clock Configurations OPEN ATCUT1-4MHz EXTERNAL CLOCK Vee IXTLII OPEN r=.J ~ ~ R * c.L CEXTERNAl (OPTIONAL-CAN BE OMITTED) L_-jf-_J CEXTEANAL (OPTIONAL) Minimum R = 4kO Example with CEXTERNAL = 0 C = 20.5 pF ± 2.5 pF +CEXTERNAL R=15kO±5% f '" 2.9 MHz±26% 1 f MIN ", 1.1 RC+65ns Minimum L=O.1 mH Minimum Q=40 1 f MAX '" 1.0RC+15ns C= 10 pF± 1.3 pF+CEXTERNAL 1 f= - - - 2n/CC Example with CEXTERNAL = 0 L=0.3mH±10% Maximum CEXTERNAL = 30 pF f'" 3.0 MHz± 10% Test Logic The TEST pin capabilities are impractical for user applications because of timing complexities; however these capabilities are sufficient to enable Fairchild to implement rapid methods for thoroughly testing the F3aC70. Special test logic is implemented to allow access to the internal main data bus for test purposes. In normal operation, the TEST pin must be connected to ground. When the TEST signal is set to VOO ' port 4 becomes an output of the internal data bus and port 5 becomes a wired-OR input to the internal data bus. The data appearing on the port 4 pins is logically true, whereas input data forced on port 5 must be logically false. When the TEST signal is set to one-half the level of Vcc (l/oc/2), the ports act as above and the 2K X a program ROM is prevented from driving the data bus. In this mode, operands and instructions are forced externally through port 5 instead of being accessed from the program ROM. When the TEST signal is in either the Voo/2 or the high state, the STROBE signal ceases its normal function and becomes a cycle clock (identical to the Fa multi-chip system write clock, except inverted). Clocks The time bases for the F38C70 originate from one of four external sources by mask options. These four configurations are illustrated in figure 3. External capacitors are not required. In all external clock modes, the external time base frequency is divided by two to form the internal 41 clock. The selection of clock configurations is by mask options. 4-36 F38C70 Figure 4 F38C70 Programmable Registers and Ports 0 7 I I I~ I IzIcis I ACCUMULATOR A STATUS REGISTER W 7 INDIRECT SCRATCHPAD ADDRESS REGISTER 4 3 I IS 0 I DCl I 0 I I DC I H! HL 11 B 13 KU 12 C K! 14 KL 13 D 15 Q! au 14 18 aL 15 17 18 0 PO 7 I 0 10 20 PORT 6 I I I PORT 7 58 3A 72 59 38 73 80 3C 74 61 3D 75 62 3E 76 63 3F 77 0 7 0 BINARY TIMER 12 I I P I INTERRUPT CONTROL PORT A 0 10 PROGRAM COUNTER 11 10 HU 10 STACK REGISTER 0 I 0 10 DATA COUNTER BYTE ADDRESS OCT HEX DEC I ! 10 AUX DATA COUNTER 0 I 0 4 SCRATCHPAD 7 110 PORT 0 I 1/0 PORT 1 PRESCALER LSW PORT 8 110 PORT 4 PRESCALER MSW PORT 9 110 PORT 5 4-37 L~ F38C70' Figure 5 PS Instruction PS INSTRUCTION EXTERNAL INTERRUPT ~r" FETCH INSTRUCTION FROM LOCATION ZERO Figure 6 ~ TIMED OUT ~ TIMER INTERRUPT TIMER INTERRUPT EXTERNAL INTERRUPT EXTERNAL INTERRUPT ENArED DISArED ENArED DISTLED SERVICE EXTERNAL INTERRUPT FETCH NEXT INSTRUCTION SERVICE TIMER INTERRUPT FETCH NEXT INSTRUCTION PSA Instruction PSA INSTRUCTION I EXTERNAL INTERRUPT EXTERNAL RESET I FETCH INSTRUCTION FROM LOCATION ZERO ~ EXTERNAL INTERRUPT ENABLED I SERVICE EXTERNAL INTERRUPT 4-38 EXTERNAL INTERRUPT DISABLED I FETCH NEXT INSTRUCTION F38C70 Instruction Set The F38C70 executes the entire instruction set of the F3870 family. In addition, two instructions exclusive to the F38C70 allow the F38C70 to further reduce its power consumption by entering into one of two power-save modes. A summary of programmable registers and ports is shown in Figure 4. Table 1 lists the F38C70 instruction set and F8-compatible instructions. Power-Save All Mode When the power-save all instruction (mnemonic PSA, Op code 2F) is executed, the F38C70 halts all its operations and goes into a power-save mode (refer to Figures 5 and 6). The microcomputer is returned to the previous operating status by an external reset or an external interrupt. Both the timer and prescaler are reset when PSA is executed, except in the event counter mode. In returning from either power-save mode, the microcomputer exercises the interrupt routine or continues with the next instruction, depending on whether the interrupt is enabled. Power-Save Mode When the power-save instruction (mnemonic PS, OP code 20) is executed, the F38C70 halts all its operations except the timer and interrupts. The microcomputer is returned to the operating status by an external reset, an external interrupt, or a timer interrupt (as the timer is timed out). If the return is by an external reset, the microcomputer restarts from the reset mode. Table 1 F38C70 Instruction Set and Fa-Compatible Instructions Accumulator Group Instructions Oparation Add Carry Add knmediate And Immediate Clear Compare Immediate Complement Exclusive or Immediate Increment Load Immediate Load Immediate Short Or Immediate Shift Left One Shift Left Four Shift Right One Shift Right Four Mnemonic OP Code LNK AI NI CLR CI COM XI INC LI LIS 01 SL SL SR SR Machine Code Bytes Cycles ii ACC +- (ACC) + CRY ACC +- (ACC) H 'ii' ACC - (ACC) H 'ii' ACC- H'OO' H'ii' ACC - (ACC) eH'FF' ACC - (ACC) e H ii 19 24ii 21ii 70 25ii 18 23 ii 1 2 2 1 2 1 2 1 2.5 2.5 1 2.5 1 2.5 ii 1 ii 1 4 1 4 ACC - (ACC) + 1 ACC- H'ii' ACC- H'Oi' ACC - (ACC) V H 'ii' Shift Left 1 Shift Left 4 Shift Right 1 Shift Right 4 1F 20 ii 7i 22ii 13 15 12 14 1 2 1 2 1 1 1 1 1 2.5 1 2.5 1 1 1 1 Operand ii ii ii Function 4-39 Status Bits OVF Zero CRY Sign 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1/0 0 1/0 1/0 1/0 1/0 1/0 0 1/0 0 1/0 0 1/0 0 1/0 1/0 1/0 1/0 1/0 - - - - - - - 0 0 0 0 0 110 1/0 1/0 1/0 1/0 0 0 0 0 0 1/0 1/0 1/0 1/0 1/0 F38C70 Table 1 F38C70 Instruction Set and Fa·Compatible Instructions (Continued) Branch Instructions (In all conditional branches, PO (PO) + 2 if the test conditions are not met. Execution is complete in 30 cycles) Operation Mnemonic OP Code Branch on Carry Branch on Positive Branch on Zero Branch on True Operand BC aa BP . BZ aa aa BT t,aa Branch if Negative BM aa Branch if No Carry BNC aa Branch if No Overflow BNO aa Branch if Not Zero BNZ aa BF t.aa Branch if False Test Status Bits Cycles OVF Zero CRY Sign Machine Code Bytes PO'" [(PO) + 1] + H'aa'if CRY 1 PO- [(PO) + 1] + H'aa' if PO -+ [(PO) + 1] + H'aa'if Zero 1 PO'" [(PO) + 1] + H'aa' if any test is true 82 aa 2 3/3.5* * - - - - 81aa 84aa 2 2 3/3.5** 3/3.5* * - - - - - - - - 8t aa 2 3/3.5* * - - - - 1] + H'aa' if 91aa 2 3/3.5* * 1] + H'aa'if 92 aa 2 3/3.5* * 1] + H'aa' if 98 aa 2 3/3.5* * 1] + H'aa'if 94 aa 2 3/3.5** 1] + H'aa' if all 9t aa 2 3/3.5** 8Faa 2 2.5 - - - 2.0 90 aa 29 aaa 2 3 3.5 5.5 Function = = PO'" [(PO) + Sign 0 PO'" [(PO) + Carry 0 PO ... [(PO)i + OVF 0 PO'" [(PO) + Zero 0 PO'" [(PO) + false test bits = * = = = TEST CONDITION Branch If ISAR(Lower)7 BR7 aa Branch Relative Jump* BR JMP aa aaaa PO'" [(PO) + 1]+ H'aa' if ISARL 'i!!7 PO ... (PO) + 2 if ISARL = 7 PO'" [(PO) + 1] + H'aa' PO'" H'aaa' * Privileged instruction •• 3.5 Cycles if branch taken. Note JMP and Pl change accumulator contents to the high byte address. 4·40 - F38C70 Table 1 F38C70 Instruction Set and F8-Compatlble Instructions (Continued) Memory Reference Instructions (In all memory reference instructions, the data counter is incremented DC-DC Operation Add Binary Add Decimal AND COMPARE EXCLUSIVE OR LOAD LOGICAL OR STORE Machine Code Mnemonic OP Code Operand Function ACC+-(ACC) + [(DC)] ACC+-(ACC) + [(DC)] ACC-(ACC)A[(DC)] [(DC)] + (ACC) + 1 ACC-(ACC) e [(DC)] ACC-[(DC)] ACC-(ACC) v[(DC)] (DC)-(ACC) AM AMD NM CM XM LM OM ST Bytes Cycles 89 8A 8D 8C 16 8B 17 1 1 1 1 1 1 1 1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Machine Code Bytes Cycles 88 1.) Status Bits OVF Zero CRY Sign 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1/0 0 1/0 1/0 1/0 1/0 1/0 0 1/0 0 1/0 - - -0 1/0 - - 0 1/0 -- Address Register Group Instructions Operetion Add to Data Counter Call to Subroutine Call to Subroutine Immediate Exchange DC Load Data Counter Load Data Counter Load DC Immediate Load Program Counter Load Stack Register Return From Subroutine Store Data Counter Store Data Counter Store Stack Register Mnemonic OPCode Operand ADC PK Function Status Bits OVF Zero CRY Sign DC-(DC) + (ACC) P+-(PO)cllPOU-(r12) + PL-(r13) P-(p)PO-H'aaaa' 8E DC 1 1 2.5 4 - - - 28aaaa 3 6.5 - - * ---- PI aaaa XDC LR LR DCI LR LR POP DC,a DC,H aaaa pO,a P,K DC*DC1 DCU-(r14), DCL ....(r15) DCU-(r10), DCL ....(r11) DC"" H 'aaaa' POU ....(r14), POL-(r15) PU ....(r12), PL....(r13) PO\P 2C .OF 10 2Aaaaa OD 09 1C 1 1 1 3 1 1 1 2 4 4 6 4 4 2 - LR LR LR a,DC H,DC K,P r14 ....(DCU), r15-(DCL) r10-(DCU), r11-(DCL) r12 ....(PU), r13-P OE 11 1 1 1 4 4 4 - - - - - - - -- - 4-41 08 - --- -- -- --- - F38C70 Table 1 F38C70 Instruction Set and FIJ.Compatible Instructions (Continued) Scratchpad Register Instructions (refer to scratchpad addressing modes.) Operation Add Binary Add Decimal Decrement Load Load Load Load Load Load Load Load Load Load And Exclusive Or Mnemonic OP Code Operand AS ASD DS LR LR LR LR LR LR LR LR LR LR NS XS r r r A,r A,KU A,KL A,aU A,aL r,A KU,A KL,A aU,A aL,A r r Machine Code Function ACC(ACC) + (r) ACC+-(ACC) + (r) r+-(r) + H'FF' ACC+-(r) AC+-(r12) ACC+-(r13) ACC+-(r14) ACC+-(r1S) r+-(ACC) r12+-(ACC) r13+-(ACC) r14 ....(ACC) r1S+-(ACC) ACC ....(ACC)A(r) ACC ....(ACC)$(r) 4-42 Cr Dr 3r 4r 00 01 02 03 Sr 04 OS 06 07 Fr Er Bytes Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1.S 1 1 1 1 1 1 1 1 1 1 1 1 Status Bits OVF Zero CRY Sign 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 - - 0 0 1/0 1/0 -- ------ --0 0 1/0 1/0 F38C70 Table 1 F38C70 Instruction Set and Fa·Compatible Instructions (Continued) Miscellaneous Instructions Operation Disable Interrupt Enable Interrupt * Input Input Short Load ISAR Load ISAR Lower Load ISAR Upper Load statusregister No·Operation OUTPUT OUTPUT Short Store ISAR Store Status Reg Power Save Power Save All Mnemonic OP Code Operand 01 EI IN INS LR LlSL LlSU LR Nop OUT OUTS LR LR PS PSA aa a IS.A a a W.J aa a A.15 J.W Machine Code Function Reset ICB SET ICB ACC +- (Input PORT aa) ACC - (Input PORT a) ISAR - (ACC) ISARL +- a ISARU +- a W +- (r9) PO - (PO) + 1 OUTPUT PORT aa +- (ACC) OUTPUT PORT a +- (ACC) ACC -(lSAR) r9 - (yV) Halt Internal Clock Halt Internal Clock and Timer 1A 1B 26aa Aa OB 01101a* * 01100** 10 2B 27 aa Ba OA 1E 20 2F Status Bits OVF Zero CRY Sign Bytes Cycles 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 2 2 - - - - 4 0 0 1/0 1/0 0 0 1/0 1/0 - - - - 4*** 1 1 1 2 1 4 4*** 1 1 3 3 - - - - - - - - 1/0 1/0 1/0 1/0 - - - - - - - - - - - * Privileged instruction .. :Jobit octal digit •• ·Two machine cycles for CPU ports Notes Each lower case character represents a hexadecimal digit. Each cycle equals four machine clock periods. Lower case denotes variables specified by programmer. J K Kl KU PO POL POU P Function definitions () (.) + Ell H'# is replaced by the contents of binary ones complement of arithmetic add (binary or decimal) logical OR exclusive logical AND logical OR inclusive hexadecimal digit Pl PU a al au r W scratchpad register # registers #12 and #13 register #13 register #12 program counter least significant eight bits of program counter most significant eight bits of program counter stack register least significant eight bits of program counter most significant eight bits of active stack register registers #14 and #15 register #15 register #14 scratchpadlregister (any address through 11) status register Register Names Scratchpad Addressing Modes (Machine Code Format) a r r r r r DC DCI DCl DCU H i and ii ICB IS ISAR ISARl ISARU address variable A accumulator data counter (indirect address registe~ data counter #1 (auxiliary data counte~ least significant eight bits of data counter addressed most significant eight bits of data counter addressed scratch pad register #10 and #11 immediate operand interrupt control bit indirect scratchpad address register indirect scratchpad address register least significant three bits of fSAR most significant three bits of ISAR = C =D = E = F = O·B (hexadecimal) register addressed by ISAR (unmodified) (hesadecimal) register addressed by ISAR, ISARl incremented (hexadecimal) Register addressed by ISAR, ISARl decremented (no operation performed) (hexadecimal) register 0 through 11 addressed directly from the instruction Status Register 1/10 CRY 4·43 no change in condition is set to 1 or 0 depending on conditions carry flag F38C70 Supplementary Notes For the F38C70, execution of an INS or OUTS instruction requires two machine cycles for ports 0 and 1, whereas ports 4 an 5 require four machine cycles. When an external reset of the F38C70 occurs, PO is stored in P and the old contents of P are lost. Note that an external reset is recognized at the start of the machine cycle and not necessarily at the end of an instruction. Thus, if the F38C70 is executing a multi·cycle instruction, that instruction is not completed, and the contents of P, upon reset, may not necessarily be the address of the instruction that would have been executed next. They may, for example, pOint to an immediate operand, if the reset occurred during the se· cond cycle of an LI or CI instruction. Additionally, several instructions (JMP, PI, PK, LR, PO, 0) as well as the inter· rupt acknowledge sequence, modify PO in parts. That is, they alter PO by first loading one part, then the other part, and the entire operation takes more than one cycle. Should reset occur during this modification process, the value stored in P becomes part of the old PO (the not yet modified part), and part of the new PO (already modified part). Thus, care should be taken (perhaps by external gating) to ensure that reset does not occur at an undesirable time, if any significance is to be given to the contents of P after a reset occurs. The interrupt control bit of the status register is automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine when ICB will again be set (by executing an EI instruction). This action prevents an interrupt service routine from being interrupted, unless the programmer so desires. When reading the interrupt control port (port 6), bit 7 of the accumulator 1, loaded with the actual logic level being ap· plied to the EXT INT pin, regardless of the status of ICP bit 2 (the EXT INT active level bit); that is, if EXT INT is at + 5 V, bit 7 of the accumulator is set to a logic 1, but if EXT INT is at Vss, the accumulator bit 7 is reset to logic O. In the instruction set summary (table 1), the number of cycles shown are nominal machine cycles. A nominal cycle is defined as 4 CI> clock periods, thus requiring 2 ,..S for a 2·mHz clock frequency (4·mHz external time base frequen· cy). When desired, the long machine cycles can be altered to short machine cycles by mask option. The following nomenclature for register names is used for consistency with the assembly language mnemonics: F8 PCo PC 1 DCo DC1 F38C70 PO P DC DC1 If desired, the F38C70 can execute all instructions in short cycles via mask options to improve the execution speed of the device. Register program counter stack register data counter auxiliary data counter 4·44 F38C70 Signal Descriptions The F38C70 input and output signals are described in Table 2. Table 2 F38C70 Signal Descriptions Mnemonic Pin No. Name Description Clock XTL1 XTl:! 1 Clock The time base inputs to which a crystal (1 to 4 mHz), LC network, RC network, or an external single-phase clock is connected. 3,4,5, 6, 19, 18 17,16 37,36, 35,34, 22,23, 24,25 8,9,10, 11, 12, 13,14, 15, 33,32, 31,30, 29,28, 27,26 Port Address The 32 ports are individually used as either TTL-compatible inputs or as latched outputs. I/O Ports POo-PO? P1o- PO? P4o-~ P5o - P5? Port Address I/O Port I/O Port Interrupt/Reset EXTINT 38 External Interrupt The active state of the external interrupt signal is software programmable; it is also used in conjunction with the timer for pulse width measurement and event counting. RESET 39 Reset This input signal is used to reset the F38C70 externally. When the signal is allowed to go low, the F38C70 resets. When subsequently allowed to go high, the F38C70 begins program execution at location H'OOOO'. Strobe STROBE 7 Strobe This output pin, which is normally high, provides a single low pulse after valid data is present on the P40 - P4? pins during an output instruction. Test TEST 21 Test An input signal used only in testing the F38C70. For normal circuit function, this pin must be connected to ground. Power Vss Vcc 20 40 Ground Power Supply Common power and signal return Power supply input signal, +5 (± 10%) V 4-45 F38C70 DC Characteristics The characteristics of the F38C70 are provided in table 3. Table 3 F38C70 DC Charateristics TA = O· to 70·C, Vcc = 5V ± 10%, 1/0 Power Dissipation s mW Min Max Unit Test Conditions TBD mA Outputs Open TBD mW Outputs Open Symbol Parameter Icc Power Supply Current Po Power Dissipation VIHEX External Clock Input High Voltage 2.4 5.8 V VILHEX External Clock Input Low Voltage -0.3 0.6 V IHEX External Clock Input High Current 100 ,.A- VIHEX = 2.4 V ILEX External Clock Input Low Current -100 ,.A- VILEX = 0.6 V VIH Input High Voltage 2.0 Vcc + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current (except 3· state option) 100 ,.A- VIH = 2.4 V, internal pull·up IlL Input Low Current (except open drain and direct drive ports) -1.6 mA VIL = 0.4 V ,.A- 0 .. VIN .. Vcc ,.A- VOH mA VOH mA VOL ILOO Leakage Current 10H Output High Current (except open drain and direct drive ports) std. ±10 IOHOO Output Drive Current (push-pull) 10L Output Low Current IOHS Output High Current (STROBE Output) IOLS Output Low Current (STROBE Output) -100 1.8 ,.A- -300 5.0 mA = 0.7 V to 1.5 V = 0.4 V VOH = 2.4 V VOL = 0.4 V Ordering Information Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Temperature (Ambient) Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground (Except Open Drain Pins) Power Dissipation TBD -1.5 = 2.4 V Part Number F38C70DC F38C70DL F38C70DM F38C70PC O·C, + 70·C - 55·C, + 150·C -0.3 V, Vcc +0.3 V Temperature Package C Ceramic Ceramic Ceramic Plastic L M C ·c = Commercial Temperature Range O'C to L = Limited Temperature Range - 4O'C to M Military Temperature Range· 55'C to = 1W 4-46 Range" + 70'C + 85'C + 125'C F38E70 Single-Chip Microcomputer F=AIRCHIL.O A Schlumberger Company Microprocessor Product Description Connection Diagram 40-Pin DIP The Fairchild single-chip microcomputer series offers a variety of circuits for the high-volume, cost-sensitive markets. The F38E70 is a complete 8-bit microcomputer on a single MOS integrated circuit. The F38E70 is functionally identical to the F3870, except the F38E70 has 2K bytes of EPROM in place of 2K bytes of ROM. The F38E70 can execute the F8 instruction set of more than 70 commands. The device features 2048 bytes of EPROM, 64 bytes of scratch pad RAM, a programmable binary timer, 32 bits of I/O, and a single + 5 V power supply requirement. EXT INT PiofA1 P1,IAs P12/A9 STROBE P13/A10 P40 Utilizing Fairchild's double-ion-implant, N-channel technology and advanced circuit design techniques, the single-chip F38E70 offers maximum cost-effectiveness in many low-to-medium volume systems. When production volume requires large quantities, the transition to the mask-programmed F3870 is very straightforward, with no circuit design changes. Pso P41 Ps1 P42 P4, Ps2 Ps3 Ps4 P4, P5s P43 • Single-Chip Microcomputer • Software-Compatible with F8 Family • 2048-Byte EPROM (F38E70-2) 64-Byte Scratchpad RAM • 32-Bit (4-Port) TTL-Compatible I/O • Programmable Binary Timer Interval Timer Mode Pulse Width Measurement Mode Event Counter Mode • External Interrupt • Crystal, LC, RC, External, or Internal Time Base • Low Power (375 mW Typical) • Single + 5 V ± 10% Power Supply • Simple EPROM Programming Pin Names PO O-P0 7 P1 o-P1 7 P4 o-P4 7 P5 0-P5 7 STROBE EXTINT RESET TEST 1/v pp XTL 1, XTL 2 V cc , GND vee XTL, P4. jig. P4, jig, P07 Pl,ITEST2 Aiiioe Pl,IPROG A3fPOs P1s/Ao P14fA1 TEST llVpp GND (Top View) F38E70 Architecture Bidirectional 110 Port a/Address· Bidirectional 110 Port 1/Address· Bidirectional 110 Port 4IData Out· Bidirectional 110 Port 5/Data In· Ready Strobe Output External Interrupt Input External Reset Input Test Line/PROG Voltage Input·· Time Base Input Power Supply Lines ISAR TEST 1 ACCUMULATOR PROGRAM COUNTER STACK REGtSTER DATA COUNTER 0 DATA COUNTER 1 EXTINT ., As shown in the connection diagram, some port 0 and port 1 pins are address inputs for programming the F38E70 EPROM section. Ports 4 and 5, Data Out and In, refer to the programming and test modes, "Caution: applying + 25 V to the Vpp pin without the presence of Vee will damage the device. Vee GND 4-47 F38E70 bits are an immediate register address or an Immediate 4-bit operand. Once latched into the IR, the main control logic decodes the instruction and provides the necessary control gating signals to all circuit elements. Signal Functions { EXTlNT _ _ DEVICE CONTROL STROBE mET TEST! Po" Po, { XTL, CLOCK XTL. POWER { Vee GND Po. Po, Po. Po, Po, P10 Pl, Pl2 Pl, Pl. Pl. P40 P4, P4. P4, P44 P4. P4e EPROM Address Registers L1·"'-' There are four 11-bit registers associated with the 2K x 8 EPROM. These are the program counter (PO), the stack register (P), the data counter (DC), and the auxiliary data counter (DC1). The program counter is used to address instructions or immediate operands. The stack register is used to save the contents of PO during an Interrupt or subroutine cell. Thus, P contains the return address at which processing is to resume upon completion of the subroutine or the interrupt routine. LM The data counter (DC) is used to address data tables. This register is autO-incrementing. Of the two data counters, only DC can access the EPROM. However, the XDC instruction allows DC and DC1 to be exchanged. !{ADDRESS Associated with the address registers is an 11-bit adder/ incrementer. This logic element is used to increment PO or DC when required, and Is also used to add displacements to PO on relative branches or to add the accumulator contents to DC1 with the ADC (add data counter) instruction. ILm.. .~, ~ 2048 P47 Pso Ps, Ps. Ps, Ps. Ps, )C 8 EPROM The microcomputer program and data constants are stored in the program EPROM. When an EPROM access is required, the appropriate address register (PO or DC) is gated onto the EPROM address bus and the EPROM output is gated onto the main data bus. The first byte in the EPROM is location zero. L~ SlDATA IN Scratchpad and ISAR P50 The scratchpad provides 64 8-bit registers that may be used as general-purpose read/write data memory. The indirect scratchpad address register (ISAR) is a 6-bit register used to address the 64 registers. All 64 registers may be accessed using ISAR. In addition, the lower order 12 registers may also be directly addressed. Ps, Device Organization This section describes the basic functional elements of the F38E70 as shown in Figure 1. The ISAR can be visualized as holding two octal digits. This division of ISAR is important, since a number of instructions increment or decrement only the least significant three bits of ISAR when referencing scratchpad bytes via ISAR. This makes it easy to reference a buffer consisting of up to eight contiguous scratchpad bytes. For example, when the low-order octal digit is incremented or decremented, ISAR Is incremented from 278 to 20 8 or is decremented from 20 8 to 27 8, This feature of the ISAR is very useful in many Main Control Logic The instruction register (IR) receives the operation code (OPcode) of the instruction to be executed from the program EPROM via the data bus. During all OP code fetches, eight bits are latched into the IR. Some instructions are completely specified by the upper four bits of the OP code. In those instructions, the lower four 4-48 F38E70 Fig. 1 Block Diagram ~VCC-40 '-OND-2O r------,.-- EXT INT-38 .........-..1Sifo-8 ......--..1'41-9 ............... ~2-10 I/OPOAT4 --- -----------..... ::::~!:g ............. 1546 -13 ..........-.. JS4e-14 ~FJ47-15 ~-7 -----------.,.----EJ!:I a:=~~ 1/0 PORT 5 :::: ~!:: ............. 15'55-28 -1'Se-.7 --!'!i-.S Pin Functions Pin Name Type Description PO O-P0 7 P1 o-P1 7 P4o-P47 P5 0-P5 7 STROBE Input/Output Thirty·two lines that can be individually used as either TTL·compatible inputs or as latched outputs. For EPROM programming, 11 lines of ports 0 and 1 are used as address inputs and one line of port 1 is a program control. Port 5 is EPROM data input, and port 4 is EPROM output for verification. . Output This pin, which is normally HIGH, provides a single LOW pulse after valid data is present on the P4 o-P4 7 pins during an output instruction. RESET Input RESET may be used to externally reset the F3BE70. When pulled LOW, the F3BE70 resets. When then allowed to go HIGH, the F3BE70 begins program execution at the program location H '0000'. RESET is held LOW during EPROM programming. EXTINT Input The external interrupt input. Its active state is software-programmable. This input is also used in conjunction with the timer for pulse width measurement and event counting. XTL 1 , XTL 2 Input The time base inputs to which a crystal (1 to 4 MHz), LC network, RC network, or an external single-phase clock may be connected. If timing is not critical, the F3BE70 operates from its internal oscillator with no external components. TEST 1/v pp Input An input used only in testing and programming the F3BE70. For normal circuit functionality, this pin is left unconnected or may be grounded. For EPROM programming, the test pin is connected to the programming voltage (typically 23 V). P1 7ITEST 2 Input I/O during normal operation; must be HIGH when in verify mode. Vcc Power Vcc is the power supply input (+ 5 V ± 10%). 4-49 F38E70 program sequences. All six bits of ISAR may be loaded at one time, or either half may be loaded independently. Summary of Status Bits OVERFLOW = CARRY 7 ZERO Scratch pad registers 9 through 15 (decimal) are given mnemonic names (J, H, K, and 0) because of special linkages between these registers and other registers, such as a stack register. These special linkages facilitate the implementation of multi-level interrupts and subroutine nesting. For example, the instruction LR K, P stores the lower eight bits of the stack register into register 13 (K lower, or KL) and stores the upper three bits of P into the three least significant bits of register 12 (K upper, or KU). CARRY = CARRY 7 SIGN =ALU 7 1/0 Ports The F38E70 provides four complete bidirectional input/ output ports: these are ports 0, 1, 4, and 5. An output instruction (OUT or OUTS) causes the contents of the ACC to be latched into the addressed port. An input instruction (IN or INS) transfers the contents of the port to the ACC (port 6 is an exception, which is described later). The I/O buffers on the F38E70 are logically inverted. The schematic of an I/O port is shown in Figure 2. Accumulator The accumulator (ACC) is the principal register for data manipulation within the F38E70. The ACC serves as one input to the ALU for arithmetic or logical operations. The results of ALU operations are stored back into the ACC. An output ready strobe is associated with port 4. This flag may be used to signal a peripheral device that the F38E70 has just completed an output of new data to port 4. The strobe provides a single low pulse shortly after the output operation is completed, so either edge may be used to signal the peripheral. The STROBE signal may also be used to request new input information from a peripheral simply by doing a dummy output of H '00' to port 4 after completing the input operation. Status Register The status register (W) holds five status flags, as follows: - CARRY s Interrupt Control Bit- The ICB may be used to allow or disallow interrupts in the F38E70. This bit is not the same as the two interrupt enable bits in the interrupt control port (ICP). If the ICB is set and the F38E70 interrupt logic communicates an interrupt request to the CPU section, the interrupt is acknowledged and processed upon completion of the first non-privileged instruction. If the ICB is cleared, an interrupt request is not acknowledged or processed until the ICB is set again. Arithmetic and Logic Unit (ALU) After receiving commands from the main control logic, the ALU performs the required arithmetic or logic operations (using the data presented on the two input busses) and provides the result on the result bus. The arithmetic operations that can be performed in the ALU are binary add, decimal adjust, add with carry, decrement, and increment. The logic operations that can be performed are AND, OR, exclusive-OR, ones complement, shift right, and shift left. Besides providing the result on the result bus, the ALU also provides four signals representing the status of the result. These signals, stored in the status register (W), represent the CARRY, OVERFLOW, SIGN, and ZERO condition of the result of the operation. r-::-r.....;.,...:..~.:.........::...... ED = ALU 7 A ALU s A ALU 5 A ALU 4 A ALU3 A ALU 2 A ALU 1 A ALU o BIT NO. Timer and Interrupt Control Port The timer is an 8-bit binary down counter that is software-programmable to operate in one of three modes· the interVal timer mode, the pulse width measurement . mode, or the event counter mode (the timer characteristics are described in Tab/e 1). As shown in Figure 3, associated with the timer are an 8-bit register called the interrupt control port, a programmable prescaler, and an 8-bit modulo-N register; Figure 4 illustrates the timer/interrupt function. STATUS REGISTER (W) SIGN '----CARRy 1..-_ _ _ _ ZERO L-------OVERFLOW ' - - - - - - - - - I N T E R R U P T CONTROL BIT 4-50 F38E70 Fig. 2 1/0 Port Diagram Vee z 0 ;:: a: PORT 0( I/O :> co l- I- z 0 0 0 C C w ... PIN a: a: ii: 0 Q. a: 0( 0 ~ :! a: Q. 0( • 0 I; Vee f ~!OTYP. ~t-' STANDARD OUTPUT All ports are standard output type only. The STROBE output is always configured similar to a standard output, except that it is capable of driving three TTL loads. Fig. 3 Timer and Interrupt Control Port Block Diagram PRESCALER EXTERNAL TtME BASE CLOCK TIMER 8·BIT DOWN COUNTER (PORT 7) + 2. 5, 10, 20, 40, 100, or 200 INT REO INTERRUPT CONTROL PORT (PORT 6) 3 EVENT COUNTER MODE ~ 0 __ 0 + 2 PRESCALE __ 0 + 5 PRESCALE + 10 PRESCALE -.- 0 + 20 PRESCALE __ 1 + 40 PRESCALE __ 1 + 100 PRESCALE + 200 PRESCALE 2 1 0 _ BIT NO. II I ~ on",,, '''.ERRUPT ENABLE TIMER INTERRUPT ENABLE EXT INT ACTIVE LEVEL START/STOP TIMER -- 1 -- 1 ' - - - - - - - _ PULSE WIDTH/INTERVAL TIMER See Figure 4 for a more detailed functional diagram. 4-51 EXTINT F38E70 Table 1 Timer Characteristics Interrupt Control Port (Port 6) Bit 0 - External Interrupt Enable Bit 1 - Timer Interrupt Enable Bit 2 - EXT INT Active Level Bit 3 - Start/Stop Timer Bit 4 - Pulse Width/Interval Timer Bit 5 - .,. 2 Timer Prescale Values Bit 6 - .,. 5 Timer Prescale Values Bit 7 - .,. 20 Timer Prescale Values Definitions Error= indicated time value - actual time value tpsc = t> x prescale value Interval Timer Mode Single interval error, free-running (note 3) ± 6t> Cumulative interval error, free-running (note 3) 0 Error between two timer reads (note 2) ± (tpsc + t to - (tpsc + t to - (tpsc + 7t to - Bt> (notes 1, 3) Load timer to stop timer error (note 1) + t> to - (tpsc + 2t to - (tpsc + Bt to - 9t> (notes 1, 3) Pulse Width Measurement Mode Measurement accuracy (note 4) Minimum pulse width of EXT INT pin A special situation exists when reading the interrupt control port (with an IN or INS instruction). The accumulator is not loaded with the content of the ICP; instead, accumulator bits 0 through 6 are loaded with Os, while bit 7 is loaded with the logic level being applied to the EXT INT pin, thus allowing the status of EXT INT to be determined without the necessity of servicing an external interrupt request. This capability is useful in establishing a high-speed polled handshake procedure or for using EXT INT as an extra input pin if external interrupts are not required and the timer is used only in the interval timer mode. The rate at which the timer is clocked in the interval timer mode is determined by the frequency of an internal > clock and by the division value selected for the prescaler. (The internal > clock operates at one-half the external time base frequency.) If ICP bit 5 is set and bits 6 and 7 are cleared, the prescaler divides > by two. Likewise, if bit 6 or 7 is individually set, the prescaler divides > by 5 or 20, respectively. Combinations of bits 5, 6, and 7 may also be selected. For example, if bits 5 and 7 are set while 6 is cleared, the prescaler divides by 40. Thus, possible prescaler values are.,. 2, .,. 5, .,. 10, .,. 20, .,. 40, .,. 100, and .,. 200. + t> to - (tpsc + 2t 2t> 2t> Note. 1. All times that entail loading. starting. or stopping the timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction. 2. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS instruction. 3. All times that entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate Interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multi-cycle Instruction. 4. Error may be cumulative if operation is repetitively performed. Any of three conditions causes the prescaler to be reset: when the timer is stopped by clearing the ICP bit 3, on execution of an output instruction to port 7 (the timer is assigned port address 7), or on the trailing edge transition of the EXT INT pin when in the pulse width measurement mode. These last two conditions are explained in more detail below. The desired timer mode, prescale value, starting and stopping the timer, active level of EXT INT pin, and local enabling or disabling of interrupts are selected by outputting the proper bit configuration from the accumulator to the interrupt control port (port 6) with an OUT or OUTS instruction. Bits within the interrupt control port are defined as follows: An OUT or OUTS instruction to port 7 loads the content of the accumulator to both the timer and the B-bit modulo-N register, resets the prescaler, and clears any previously stored timer interrupt request. As previously noted, the timer is an B-bit down counter that is clocked by the prescaler in the interval timer mode and in the pulse width measurement mode. The prescaler is not used in the event counter mode. The modulo-N register is a buffer whose function is to save the value that was most recently output to port 7. The modulo-N register is used in all three timer modes. 4-52 Fig. 4 Timer/Interrupt Functional Diagram FROM INTERRUPT CONTROL PORT 82 I 84 8, 85 86 80 181 87 TIMER INTERRUPT- -LOADS INTERRUPT VECTOR H '020' UPON COMPLETION OF THE FIRST NON·PRIVILEGED INSTRUCTION ..,. ACKNOWLEDGE c:n TIMER INTERRUPT w 'I' TI =PULSE WIDTH MODE c.:I CD m ...... o ...JL EXTERNAL INTERRUPT INPUT .J""L '01' ACKNOWLEDGE EXTERNAL INTERRUPT • F38E70 Interval Timer Mode-When ICP bit 4 is cleared (logic 0) and at least one prescale bit is set, the timer operates in the interval timer mode. When bit 3 of the ICP is set, the timer starts counting down from the modulo·N value. After counting down to H '01', the timer returns to the modulo-N value at the next count. On the transition from H '01' to H 'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch is set by the transition of H 'N' in the timer, thus allowing a full 256 counts if the modulo-N register is preset to H '00'. If bit 1 of the ICP is set, the interrupt request is passed on to the CPU section of the F38E70. However, if bit 1 of the ICP is a logic 0, the interrupt request is not passed on to the CPU section but the interrupt request latch remains set. If ICP bit 1 is subsequently set, the interrupt request is then passed on to the CPU section. (Recall from the discussion of the status register interrupt control bit that the interrupt request is acknowledged by the CPU section only if ICB is set.) Only two events can reset the timer interrupt request latch: when the timer interrupt request Is acknowledged by the CPU section, or when a new load of the modulo-N register is performed. again set. Recall, however, that the prescaler is reset whenever the timer is stopped; thus, a series of starting and stopping results in a cumulative truncation error. A summary of other timer errors is given in the timing section. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests may be in error by ± 6 cf> clock periods, although the cumulative error over many intervals is zero. The prescaler and timer generate precise intervals for setting the timer interrupt request latch, but the time-out may occur at any time within a machine cycle. (There are two types of machine cycles: short cycles, which consist of 4 cf> clock periods, and long cycles, which consist of 6 cf> clock periods.) In the multi-chip F8 family, there is a signal called the write clock that corresponds to a machine cycle. Interrupt requests are synchronized with the internal write clock, thus giving rise to the possible ± 6 cf> error. Additional errors may arise due to the interrupt request occurring while a privileged instruction or multi-cycle instruction is being executed. Nevertheless, for most applications all of the above errors are negligible, especially if the desired time interval is greater than 1 ms. Consider an example in which the modulo-N register is loaded with H '64' (decimal 100). The timer interrupt request latch is set at the 100th count following the timer start, and the timer interrupt request latch is repeatedly set on precise 100-count intervals. If the prescaler is set at + 40, the timer interrupt request latch is set every 4000 cf> clock periods. For a 2 MHz cf> clock (4 MHz time base frequency), this produces 2 ms intervals. Pulse Width Measurement Mode-When ICP bit 4 is set (logic 1) and at least one prescale bit is set, the timer operates in the pulse width measurement mode. This mode is used for accurately measuring the duration of a pulse applied to the EXT INT pin. The timer is stopped and the prescaler is reset whenever EXT INT is at its inactive level. The active level of EXT INT is defined by ICP bit 2: if cleared, EXT INT is active LOW; if set, EXT INT is active high. If ICP bit 3 is set, the prescaler and timer start counting when EXT INT transitions to the active level. When EXT INT returns to the inactive level, the timer stops, the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external interrupts are not latched if the ICP interrupt enable bit is not set.) The range of possible intervals is from 2 to 51,200 cf> clock periods (1 p,s to 25.6 ms for a 2 MHz cf> clock). However, approximately 50 cf> periods is a practical minimum because the time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine is at least 29 cf> periods (the response time is dependent upon how many privileged instructions are encountered when the request occurs). To establish time intervals greater than 51,200 cf> clock periods is simply a matter of using the timer interrupt service routine to count the number of interrupts, saving the result in one or more of the scratchpad registers until the desired interval is achieved. With this technique, virtually any time interval, or several time intervals, may be generated. As in the interval timer mode, the timer may be read at any time and may be stopped at any time by clearing ICP bit 3; the prescaler and ICP bit 1 function as previously described, and the timer still functions as an 8-bit binary down counter, with the timer interrupt request latch being set on the timer transition from H '01' to H 'N'. Note that the EXT INT pin has nothing to do with loading the timer; its action is that of automatically starting and stopping th.e timer and of generating external interrupts. Pulse widths longer than the prescale value times the modulo-N value are easily measured by using the timer interrupt service routine to store the number of timer interrupts in one or more scratchpad registers. The timer may be read at any time and in any mode using an input instruction (IN 7 or INS 7) and may take place "on-the-fly" without interfering with normal timer operation. Also, the timer may be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and resumes counting when bit 3 is 4-54 F38E70 As for accuracy, the actual pulse duration is typically slightly longer than the measured value because the status of the prescaler is not readable and is reset when the timer is stopped. Thus, for maximum accuracy, it is advisable to use a small division setting for the prescaler. interrupt control bit is set and the CPU section acknowledges the interrupt or the interrupt request is cleared as previously described. If there are both a timer interrupt request and an external interrupt request when the CPU section starts to process the requests, the timer interrupt is handled first. Event Counter Mode-When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer operates in the event counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer decrements on each transition from the inactive level to the active level of the EXT INT pin. The prescaler is not used in this mode, but, as in the other two timer modes, the timer may be read at any time and may be stopped at any time by clearing ICP bit 3; ICP bit 1 functions as previously described, and the timer interrupt request latch is set on the timer transition from H '01' to H 'N'. Normally; ICP bit 0 should be kept cleared in the event counter mode; otherwise, external interrupts are generated on the transition from the inactive level to the active level of the EXT INT pin. When an interrupt is allowed, the CPU section requests that the interrupting element pass its interrupt vector address to the program counter via the data bus. The vector address for a timer interrupt is H '020'. The vector address for external interrupts is H 'DAD'. After the vector address is passed to the program counter, the CPU section sends an acknowledge signal to the appropriate interrupt request latch, which clears that latch. The execution of the interrupt service routine then commences. The return address of the original program is automatically saved in the stack register, P. Power-on Clear When power is applied to the F38E70, the program counter and the ICB bit of the status register are cleared. Ports 4, 5, 6, and 7 are loaded with H '00' (thus, the 110 pins for ports 4 and 5 are at VOH ). The contents of other registers and ports are undefined. The first program instruction is then fetched from EPROM location H '000'. For the event counter mode, the minimum pulse width required on EXT INT is 2 clock periods and the minimum inactive time is 2 clock periods; therefore, the maximum repetition rate is 500 Hz. External Interrupts When the timer is in the interval timer mode, the EXT INT pin is available for non-timer-related interrupts. If ICP bit o is set, an external interrupt request latch is set when there is a transition from the inactive level to the active level of EXT INT. (EXT INT is an edge-triggered input.) The interrupt request is latched either until acknowleged by the CPU section or until ICP bit 0 is cleared (unlike timer interrupt requests, which remain latched even when ICP bit 1 is cleared). External interrupts are handled in the same fashion when the timer is in the pulse width measurement mode or in the event counter mode, except that only in the pulse width measurement mode is the external interrupt request latch set on the trailing edge of EXT INT, that is, on the transition from the active level to the inactive level. Interrupt Handling When either a timer or an external interrupt request is communicated to the CPU section of the F38E70, it is acknowledged and processed at the completion of the first non-privileged instruction if the interrupt control bit of the status register is set. If the interrupt control bit is not set, the interrupt request continues until either the 4-55 External Reset When RESET is taken LOW, the content of the program counter is pushed to the stack register, and the program counter and the ICB bit of the status register are then cleared. The original stack register content is lost. As with power·on clear, ports 4, 5, 6, and 7 are loaded with H '00'. The contents of all other registers and ports are unchanged. When RESET is taken HIGH, the first program instruction is fetched from EPROM location H '000'. Test Logic Special test logic is implemented to allow access to the internal main data bus for test purposes. In normal operation, the TEST pin is unconnected or is connected to GND. When TEST is placed at a TTL level (2.0 V to 2.6 V), port 4 becomes an output of the internal data bus and port 5 becomes a wired-OR input to the internal data bus. The data appearing on the port 4 pins is logically true, whereas input data forced on port 5 must be logically false. When TEST is placed at a HIGH level (6.0 V to 7.0 V), the ports act as above and, additionally, the 2K x 8 program ROM is prevented from driving the data bus. In this mode, operands and 4 F38E70 instructions may be forced externally through port 5 instead of being accessed from the program ROM. When TEST is in either the TIL state or the HIGH state, STROBE ceases its normal function and becomes a cycle clock (identical to the F8 multi-chip system write clock, except inverted). Fig. 5 Clock Configurations Crystal Mode Timing complexities render the capabilities associated with the TEST pin impractical for use in a user's application, but these capabilities are sufficient to enable Fairchild to implement a rapid method for thoroughly testing the F38E70. External Mode OPEN ATCUTI-4MHz RC.Mode EXTERNAL CLOCK LC Mode Vee F38E70 Clocks The time base for the F38E70 may originate in one of four external sources. The four external configurations are shown in Figure 5. There is an internal 20 pF capacitor between XTL 1 and GND, and also between XTL2 and GND. Thus, external capacitors are not required. In all external clock modes, the external time base frequency is divided by two to form the internal '" clock. ~ ~R ~ CEXT~NAl * ~ (OPTIONAL-CAN BE OMITTED) L_-if- _J CEXTERNAL (OPTIONAL) Instruction Set The F38E70 executes the entire instruction set of the multi-chip F8 family (F3850 family), as shown in Table 2. Of course, the STORE instruction is of little use in the F38E70 because only read-only memory exists in the addressing range of the data counter (the data counter, however, is incremented if STORE is executed). Minimum R=4kll Minimum L=O.l mH Minimum Q = 40 C = 20.5 pF ± 2.5 pF + CEXTERNAL MaXimum CEXTEANAL = 30 pF 1 'MIN'" 1.1 RC+65ns C= 10 pF± 1.3 pF + CEXTERNAL ,=-v'i:C 1 'MAX'" 1.0 RC+ 15 ns A summary of programmable registers and ports is given in Figure 6, followed by a summary of the F38E70 (F8-compatible) instruction set. Also, for convenient reference, a programming model of the F38E70 is given in Figure 7. 4-56 - 2 ... Example with CEXTERNAL = 0 Example with CEXTEANAL = 0 R=15kll±5% '''' 2.9 MHz±26% L=0.3mH±10% '''' 3.0 MHz± 10% F38E70 Table 2 F38E70 Instruction Set Accumulator Group Instructions Operation Add Carry Add Immediate AND Immediate Clear Compare Immediate Complement Exclusive OR Immediate Increment Load Immediate Load Immediate Short OR Immediate Shift Left One Shift Left Four Shift Right One Shift Right Four Mnemonic OP Code LNK AI NI CLR CI COM XI INC LI LIS 01 SL SL SR SR Oparand ii ii ii ii ii i ii 1 4 1 4 Function ACC-(ACC)+ CRY ACC-(ACC) A H'ii' ACC-(ACC) H'ii' ACC-H'OO' H'ii'+(ACC)+1 ACC-(ACC) .. H'FF' ACC-(ACC) .. H'ii' ACC-(ACC)+ 1 ACC-H'ii' ACC-H'Oi' ACC-(ACC) V H'ii' SHIFT LEFT 1 SHIFT LEFT 4 SHIFT RIGHT 1 SHIFT RIGHT 4 Machine Code Byte. Cycles 19 24 ii 21 ii 70 25 ii 18 23 ii 1F 20 ii 7i 22 ii 13 15 12 14 1 2 2 1 2 1 2 1 2 1 2 1 1 1 1 1 2,5 2.5 1 2.5 1 2.5 1 2.5 1 2.5 1 1 1 1 Statu. Bits OVF ZERO CRY SIGN 110 110 0 110 110 110 110 110 0 110 110 110 110 0 0 110 110 110 110 110 110 0 0 110 110 110 110 110 - - 0 0 0 0 0 - 110 110 110 110 110 - 0 0 0 0 0 - - 110 110 110 1 1 Branch Instructions (In All Conditional Branches, PO (PO)+ 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.) Operation Branch Branch Branch Branch on on on on Carry Positive Zero True Mnemonic OP Code Oparand BC BP BZ BT aa aa aa t,aa Function PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ 1]+ H'aa' 1]+ H'aa' 1]+ H'aa' 1]+ H'aa' if CRY = 1 if SIGN = 1 if ZERO= 1 if any test is true Machine Code Byte. 82 aa 81 aa 84 aa 8t aa 2 2 2 2 Cycle. 3/3.5" 3/3.5" " 3/3.5"" 313.5"" Status Bits OVF ZERO CRY - - - SI.GN - -- - - - - - - - - - t = TEST CONDITION I 22 I 21 I 2° I IZERO I CRY I SIGN I Branch Branch Branch Branch Branch if if if if if Negative No Carry No Overflow Not Zero False Test BM BNC BNO BNZ BF aa aa aa aa t,aa PO-[(PO)+ 1]+ H'aa' if SIGN=O PO-[(PO)+ 1]+ H'aa' if CARRY*O PO-[(PO)+ 1]+ H'aa' if OVF=O PO-[(PO) + 1]+ H'aa' if ZERO=O PO-[(PO)+ 1]+ H'aa' ifall false test bits - - 91 aa 92 aa 98 aa 94 aa 9t aa 2 2 2 2 2 313.5"" 313.5"" 313.5"" 313.5"" 3/3.5"" - - 8F aa 2 2 3 - - 90 aa 29 aaaa 2.5 2.0 3.5 5.5 - - - t=TEST CONDITION 1 23 1 22 121 1 2° 1 1 OVF 1ZERO 1 CRY 1 SIGN 1 Branch if ISAR (Lower) 7 BR7 aa Branch Relative Jump" BR JMP aaaa aa PO-[(PO)+ 1]+ H'aa' if ISARL*7 PO-(PO) + 2 if ISARL=7 PO-[(PO)+ 1]+ H'aa' PO-H'aaaa' - - - Memory Reference Instructions (In All Memory Reference Instructions, the Data Counter Is Incremented DC-DC.1.) Operation Add Binary Add Decimal AND Compare Exclusive OR Load Logical OR Store .. Mnemonic OP Code AM AMD NM CM XM LM OM ST Oparand Function ACC-(ACC)+ [(DC)] ACC-(ACC)+ [(DC)] ACC-(ACC) A [(DC)] [(DC)] + (ACC) + 1 ACC -(ACC) .. [(DC)] ACC-[(DC)] ACC-(ACC) V [(DCn (DC)-(ACC) "Privileged instruction ,. 3.5 cycles if branch taken. Note JMP and PI change accumulator contents to the high byte address. 4-57 Machine Code Byte. Cycle. 88 89 8A 80 8C 16 8B 17 1 1 1 1 1 1 1 1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Status Bits OVF ZERO CRY SIGN 110 110 0 110 0 110 110 110 110 1/0 110 110 110 110 1/0 0 110 - - 110 110 0 110 0 0 - - 110 - • F38E70 Table 2 F38E70 Instruction Set (Cont.) Address Register Group Instructions Operation Mnemonic OP Code Add to Data Counter Call to Subroutine Call to Subroutine Immediate Exchange DC Load Data Counter Load Data Counter Load DC Immediate Load Program Counter Load Stack Register Return From Subroutine Store Data Counter Store Data Counter Store Stack Register ADC PK' PI' XDC LR LR DCI LR LR POP' LR LR LR Operand aaaa DC,a DC,H aaaa PO,a P,K a,DC H,DC K,P Function DC-(DC) + (ACC) P-(PO); POU-(rI2); PL-(rI3) P-(P); PO-H'aaaa't DC-DCl DCU-(rI4); DCL-(rlS) DCU-(rl0); DCL-(rll) DC-H'aaaa' POU-(rI4); POL-(rlS) PU-(rI2); PL-(rI3) PO-(P) rI4-(DCU); rlS-(DCL) rl0-(DCU); rll-(DCL) rI2-(PU); rI3-(P) Machine Code Byte. Cycles 08 1 1 3 1 1 1 3 1 1 1 1 1 1 2.S 4 6.S 2 4 4 6 4 4 2 4 4 4 Machine Code Bytes Cycles 07 Fr Er I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 I.S 1 1 1 1 1 1 1 1 1 1 1 1 Machine Code Bytes Cycles lA lB 26 aa Aa OB 01101a" 01100a" 10 2B 27 aa Ba OA IE 1 1 2 1 1 1 1 1 1 2 1 1 1 2 2 4 4'" 1 1 1 2 1 4 4'" 1 1 8E OC 28 aaaa 2C OF 10 2A aaaa 00 09 lC OE II Status Bits OVF ZERO CRY SIGN - - - - - - - - - - - - - - - - - - - - - - - - Scratchpad Register Instructions (Refer 10 Scralchpad Addressing Modes.) Operation Mnemonic OP Code Operand AS ASD OS LR LR LR LR LR LR LR LR LR LR NS XS r r r A,r A,KU A,KL A,aU A,aL r,A KU,A KL,A aU,A aL,A r r Mnemonic OP Code Operand Add Binary Add Decimal Decrement Load Load Load Load Load Load Load Load Load Load AND Exclusive OR Function ACC-(ACC)+ (r) ACC-(ACC)+ (r) r-(r)+ H'FF' ACC-(r) ACC-(rI2) ACC-(rI3) ACC-(rI4) ACC-(rlS) r-(ACC) rI2-(ACC) rI3-(ACC) rI4-(ACC) rlS-(ACC) ACC-(ACC) A (r) ACC-(ACC)s(r) Cr Dr 3r 4r 00 01 02 03 Sr 04 OS 08 Status Bits OVF ZERO CRY SIGN 110 110 1/0 110 1/0 110 110 1/0 110 110 1/0 110 - - - - - - - - 0 0 - - 1/0 110 - - - - - - - 0 0 1/0 1/0 - - Miscellaneous Instructions Operation Disable Interrupt Enable Interrupt' Input Input Short Load ISAR Load ISAR Lower Load ISAR Upper Load Status Register' No·Operation Output Output Short Store ISAR Store Status Register 01 EI IN INS LR LISL LlSU LR NOP OUT OUTS LR LR aa a IS,A a a W,J aa a A,IS J,W Function RESET ICB SET ICB ACC-(INPUT PORT aa) ACC-(INPUT PORT a) ISAR-(ACC) ISARL-a ISARU-a W-(r9) PO-(PO)+ 1 OUTPUT PORT aa-(ACC) OUTPUT PORT a-(ACC) ACC-(ISAR) r9-(W) 'Privileged instruction "3·bit octal digit .. 'Two machine cycles for CPU ports tContents of ACC destroyed 4·58 Status Bits OVF ZERO CRY SIGN - - - - 0 0 110 110 0 0 1/0 1/0 - - - - 110 - - - - - 110 - - 110 - - - - - 1/0 - - - F38E70 Notes Each lower case character represents a hexadecimal digit. Each cycle equals four machine clock periods. lower case denotes variables specified by the programmer. J K Kl KU PO POL POU P Pl PU a al au r W Function Dellnllons is replaced by the contents of binary ones complement of + arithmetic add (binary or decimal) .. logical OR exclusive A logical AND V logical OR inclusive H'#' hexadecimal digit () (-) scratchpad register #9 registers #12 and #13 register #13 register #12 program counter least significant eight bits of program counter most significant eight bits of program counter stack register least significant eight bits of program counter most significant eight bits of active stack register registers #14 and #15 register #15 register #14 scratchpad register (any address through 11) status register Register Names a address variable A accumulator DC data counter (indirect address register) DC1 data counter #1 (auxiliary data counter) DCl least significant eight bits of data counter addressed DCU most significant eight bits of data counter addressed H scratch pad register #10 and #11 i and ii immediate operand ICB interrupt control bit IS indirect scratchpad address register ISAR indirect scratchpad address register ISARl least significant three bits of ISAR ISARU most significant three bits of ISAR Status Register no change in condition 1/0 is set to 1 or 0, depending on conditions CRY carry flag EPROM Programming F38E70 Erasing Instructions When Vpp is applied to the TEST 1 pin, the device goes into the program or verify mode and the I/O ports take on the different functions of DATA IN (port 5), DATA OUT (port 4), EPROM address (11 pins of ports 0 and 1), and PROG (port 16). The verify mode exists when PROG is HIGH and TEST 2= Vcc. Port 4 outputs the data content of the EPROM according to the address Ao through A 10 • The logical sense is true, and for an unprogrammed location, the outputs are high. During verify mode, the data on port 5 has no effect on the port 4 output. The program mode exists when PROG is taken low. All addresses and DATA IN must be stable before going into this mode. During this mode, the data appearing on port 5 is "burned in" to the EPROM. Note that the sense of port 5 is logically false. At the same time, port 4 outputs the data on the internal data bus, which is exactly equal to the inversion of the data going in on port 5. Port 4 does not indicate satisfactory completion of the EPROM programming in the program mode. The PROG pin must be high before the Vpp is applied in order to prevent a pro· gramming error. The contents of the F38E70 EPROM can be erased by exposure to high·intensity shortwave ultraviolet (UV) light with a wavelength of 2537 Angstroms (A). This can be accomplished with ultraviolet light EPROM erasure devices that are available from several U.S. manufacturers. These erasure devices contain a UV light source, which is usually placed approximately 1 or 2 inches from the EPROM so that the transparent window on top of the device is illuminated. The minimum required integrated dose (intensity x exposure time) of UV light energy incident on the window of the device in order to reliably ensure complete erasure is 15 watt·sec/cm 2• The UV erasure unit should be periodically calibrated if minimum exposure times are to be used. (Minimum exposure times range from 10 to 45 minutes, depending on the model type and age of UV lamp.) If longer exposure times are possible, variations in the output light intensity of the UV light source are not critical. Scratchpad Addressing Modes (Machine Code Format) r= C (hexadecimal) register addressed by ISAR (unmodified) r= D (hexadecimal) register addressed by ISAR; ISARl incremented r= E (hexadecimal) register addressed by ISAR; ISARl decremented r= F (no operation performed) r= O-B (hexadecimal) register 0 through 11 addressed directly from the instruction CAUTION Applying Vpp to the TEST 1IVpp pin without the presence of Vcc will damage the device. 4-59 • F38E70 Fig. 6 Programmable Registers and Ports 7 ACCUMULATOR 0 I IA ~ STATUS REGISTER W I I I zl cis I 4 7 INDIRECT SCRATCHPAD ADDRESS REGISTER I IS I 0 I H K DC I 10 STACK REGISTER I I 01 10 HU 12 HL 11 B 13 KU 12 C 14 KL 13 D 15 au 14 E 16 15 OL 17 10 20 58 3A 72 59 3B 73 60 3C 74 16 P I 0 I PO I 0 BINARY TIMER I I 61 3D 75 62 3E 76 63 3F 77 0 7 I PORT 7 7 INTERRUPT CONTROL PORT A 0 10 PROGRAM COUNTER 2 11 DC1 10 I I I 0 0 I DATA COUNTER I I ! 10 AUX DATA COUNTER 0 BYTE ADDRESS HEX OCT DEC 0 I 0 4 3 SCRATCHPAD 7 110 PORT 0 I 0 PORT 6 I 110 PORT 1 110 PORT 4 110 PORT 5 4·60 L-smae Fig. 7 Programming Model ourS7 r-------------------------~~I AOC INS·7 ~: STATUS ------:I 1-1 r----......-tl LNK OUT86 INS*6 (PO) tSAR OUTS P (PO, 1,4, 5) INS·P(PO,1,4,5) LlSU AS· NS SCRATCHPAD REGISTERS II I I I 110 '1 PORTS (4) x. AUXDATA ASD, COUNTER 5 VOLTS LOGIC 0 ON 110 PINS r-- I XI 1 LR LR TO 11 .j:>. ~ 4R r---I rI_LR L..____ LI,LlS H tri'2 ITa u K ~ t(IS).3:±':;:f::l-oo---t- os· E Q U1. F EPROM L11 . "~rIS) >--+-__ .... :g 3E 3F HEX MEM (2KxS) '000' ..J TO '7FF' ::1 ---,-. 77 I OCTAL LM EXTERNAL INTERRUPT INPUT (+ 5 V LOGIC 1) = Reset transfers PO to P and then clears PO, ICB bit of W, and ports 4, 5, 6, and 7. Note The instructions PI and PK are shown in two sequential parts (Pit, PI2, and PKt , PK2). -These instructions set status. tThe value of the external interrupt input is loaded to bit 7 of the accumulator (with bits a through 6 loaded with zeros) when the instruction 'INS 6' is executed. This instruction also sets status. ttpo, P, DC, and DCI are II bil regislers. (PO) CI· • , • (DO) I I '"T1 W Q) m ~ 0 F38E70 Supplementary Notes For total software compatibility when expanding into a multi-chip configuration, the F3871 Peripheral Input/Output circuit should be used. The F3871 has the same improved timer (binary count, readable, and three modes of operation) and ready strobe output as the F38E70. When an external reset of the F38E70 occurs, PO is pushed into P and the old contents of P are lost. It must be noted that an external reset is recognized at the start of the machine cycle and not necessarily at the end of an instruction. Thus, if the F38E70 is executing a multicycle instruction, that instruction is not completed and the contents of P upon reset may not necessarily be the address of the instruction that would have been executed next. It may, for example, point to an immediate operand if the reset occurred during the second cycle of an LI or CI instruction. Additionally, several instructions (JMP, PI, PK, LR, PO, Q) as well as the interrupt acknowledge sequence modify PO in parts. That is, they alter PO by loading first one part, then the other, and the entire operation takes more than one cycle. Should reset occur during this modification process, the value pushed into P is part of the old PO (the as-yet unmodified part) and part of the new PO (the already modified part). Thus, care should be taken (perhaps by external gating) to ensure that reset does not occur at an undesirable time if any significance is to be given to the contents of P after a reset occurs. The interrupt control bit of the status register is automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine when ICB is again set (by executing an EI instruction). This action prevents an interrupt service routine from being interrupted unless the programmer so desires. When reading the interrupt control port (port 6), bit 7 of the accumulator is loaded with the actual logic level being applied to the EXT INT pin, regardless of the status of ICP bit 2 (the EXT INT active level bit); that is, if EXT INT is at + 5 V, bit 7 of the accumulator is set to a logic 1, but if EXT INT is at GND, accumulator bit 7 is reset to logic O. Absolute Maximum Ratings The absolute maximum ratings of the F38E70 are as follows: O·C, +70·C Temperature (Ambient Under Bias) Storage Temperature - 55·C, + 150·C Voltage on any Pin with Respect to -1.0 V, Ground (Except Test Pin) +7V -1.0 V, +27 V Test Pin Voltage with Respect to Vss In the "F38E70 (F8-compatible) Instruction Set" summary, the number of cycles shown is "nominal" machine cycles. A nominal machine cycle is defined as 4 ¢ clock periods, thus requiring 2 I-'S for a 2 MHz ¢ clock frequency (4 MHz external time base frequency). Also, the summary uses the following nomenclature for register names: F8 F38E70 Program Counter PC o PO PC 1 = P Stack Register Data Counter DC o DC DC 1 = DC1 Auxiliary Data Counter CAUTION Applying Vpp to the TEST 1IVpp pin without the presence of Vcc will damage the device. = = Power Dissipation This nomenclature is used in order to be consistent with the assembly language mnemonics. 1.0 W These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. For the F38E70, execution of an INS or OUTS instruction requires two machine cycles for ports 0 and 1, while ports 4 and 5 require four machine cycles. 4-62 F38E70 Timing Characteristics Vee= +5V ±10%, TA=O·CtO +70·C Signal XTL 1 XTL 2 Comments (Note 3) Symbol Characteristic Min Max Unit to(XTL) Time Base Period, Crystal Mode 250 5000 ns to(LC) Time Base Period, LC Mode 250 5000 ns 4 MHz-2 MHz to(RC) Time Base Period, RC Mode 250 5000 ns 4 MHz-2 MHz to(EX) Time Base Period, External Mode 250 5000 ns 4 MHz-2 MHz tEx(H) External Clock Pulse Width, High tEx(L) External Clock Pulse Width, Low t
Internal STROBE tI/O-S 90 to(EX).100 ns 90 to(EX)·100 ns 4 MHz-2 MHz 2to typo ns 0.5 J1.s at 4 MHz ext. time base Port Output to STROBE Delay 3t -1000 min 3t + 250 max ns Note 1 tSL STROBE Pulse Width, Low 8t - 250 min 12t+ 250 max ns RESET tRH RESET Hold Time, Low 6t + 750 min ns EXTINT tEH EXT INT Hold Time, Active State 6t + 750 min ns Clock Period Notes 1. Load is 50 pF plus 1 standard TTL Input. 2. Specification is applicable when the timer is in the interval timer mode. See "Timer Characteristics" for EXT INT requirements when in the pulse width measurement mode or the event counter mode. 3. The timing diagrams are given in Figure 8. Fig. 8 Timing Diagrams EXTERNAL CLOCK EXTERNAL, CLOCK 1/0 PORT OUTPUT C-=--=--:.--------.-SL---"""Ij ICP BIT 2=0 ICPBIT2=1 Note All measurements are referenced to V 1L max., V1H min., VOL max., or V OH min. 4·63 Note 2 • F38E70 Program/Verify Timing Symbol Parameter ISET-UP 23 V Applied 10 PROG Address Set-up Time lAS Min Max Unit 5 ",S 1 "'s "'s IAH Address Hold Time 1 los Data Set-up Time 1 "'s tOH Dala Hold Time 1 "'s tAV Address to Data Out in Verify 5 "'s tpv PROG to Data Out in Verify. 2 "'s tpo PROG 10 Data Oul in Programming 5 tpROG Programming Time "'s ms 50 60 Note Timing diagrams are given in Figure 9. Fig_ 9 ProgramlVerify Timing Diagrams TEST ADDRESSES NEXT ADDRESS (Ao-A,.) DATA IN (PORT 5) NEXT DATA DATA OUT (PORT 4) DATA VERIFY 4-64 F38E70 DC Characteristics Vcc= 5 V ± 10%, TA = O·C to Symbol + 70·C Characteristic Icc Power Supply Current Po Power Dissipation VIHEX External Clock Input High Voltage VILHEX I HEX External Clock Input Low Voltage IILEX External Clock Input Low Current VIH Input High Voltage VIL Input Low Voltage IIH Input High Current (Except Open-Drain and Direct-Drive I/O Ports) IlL Input Low Current (Except Open-Drain and Direct-Drive Ports) Min Typ Max mA Outputs Open 375 550 mW Outputs Open 5.8 V 2.4 -0.3 0.6 V 100 -100 p.A p.A 2.0 5.8 V -0.3 0.8 V 100 p.A VIH = 2.4 V, Internal Pull-Up -1.6 rnA VIL = 0.4 V 10 p.A p.A VOH = 2.4 V ILOO Leakage Current (Open-Drain Ports) 10H Output High Current (Except Open-Drain and Direct-Drive Ports) -100 -1.5 10HOO Output Drive Current (Direct-Drive Ports) Output Low Current IOHS Output High Current (STROBE Output) IOLS Output Low Current (STROBE Output) VTEST Test Pin Voltage for ProgramlVerify Mode ITEST Test Pin Current for ProgramlVerify Mode Test Conditions 100 External Clock Input High Current 10L Unit 70 -8 1.8 -300 5.0 23 rnA rnA p.A rnA 23.5 24 V 20 30 rnA VIHEX = 2.4 V VILEX =0.6V Pull-Down, Device Off VOH = 0.7 V to 1.5 V VOL = 0.4 V VOH=2.4 V VOL=0.4 V VPROG=O.4 V, VTEST=24 V Capacitance TA=25·C, f=2 MHz Symbol Characteristic C IN Input Capacitance: 1/0 Ports, RESET, EXT INT CXTL Input Capacitance: XTL 1 , XTL2 Min 18 Typical Thermal Resistance Values Plastic ()JA (Junction to ambient) ()JA (Junction to case) 60·C/W (still air) 42·C/W Ceramic ()JA (Junction to ambient) ()JA (Junction to case) 48·C/W (still air) 33·CIW 4-65 Unit Test Condition 7 pF Unmeasured pins returned to GND 23 pf Max • F38E70 Ordering Information Part Number Package Temperature Range" F38E70DC F38E70DL F38E70DM F38E70PC F38E70PL F38E70PM Ceramic Ceramic Ceramic Plastic Plastic Plastic C L M C L M ·C= CommercIal Temperature RangeO·C to + 70·C L= Limited Temperature Range - 40·C to + 85·C M = Military Temperature Range - 55·C to + 125·C 4·66 F38E70-21 Single-Chip Microcomputer FAIRCHILD A Schlumberger Company Microprocessor Product Description The Fairchild F38E70-21 is virtually identical to the F38E70 single-chip microcomputer. Specification differences between the F38E70 and the F38E70-21 are described in this data sheet (refer to the F38E70 data sheet for a complete device description)_ Page 1 F3BE70 Features F3BE70-21 Features • Crystal, LC, RC, External, or Internal Time Base • Crystal, LC, RC, or External Time Base F3BE70 Pin Functions Pin Name Type Description XTL 1 , XTL 2 Input The time base inputs to which a crystal (1 to 4 MHz), LC network, RC network, or an external single-phase clock may be connected. If timing is not critical, the F38E70 operates from its internal oscillator with no external components. TEST 1IVpp Input An input used only in testing and programming the F38E70. For normal circuit functionality, this pin is left unconnected or may be grounded. For EPROM programming, the test pin is connected to the programming voltage (typically 23 V). F3BE70-21 Pin Functions Pin Names Type XTL 1, XTL 2 Input The time base inputs to which a crystal (2 to 4 MHz), LC network, RC network, or an external single-phase clock may be connected. Description TEST 1IVpp Input An input used only in testing and programming the F38E70- 21. For normal circuit functionality, this pin is left unconnected or may be grounded. For EPROM programming, the test pin is connected to the programming voltage (typically 23.5 V). Pages 9 and 10 F3BE70-21 Test Logic All references to "TEST pin" should be changed to "TEST 1 pin". Page 10 F3BE70 Figure 5 Clock Configurations F3BE70-21 Figure 5 Clock Configurations Crystal Mode Crystal Mode AT CUT 1 - AT CUT2 - 4 MHz 4-67 4 MHz • F38E70-21 Page 13 F38E70 EPROM Programming F38E70·21 EPROM Programming When 23 V is applied to the TEST 1 pin, When 23 V to 24 V is applied to the TEST 1 pin, CAUTION Applying + 25 V to the V pp pin without CAUTION Applying + 23 V to the Vpp pin without Page 16 F38E70 Absolute Maximum Ratings Test Pin Voltage with Respect to Vss F38E70·21 Absolute Maximum Ratings -1.0V, +27V Test Pin Voltage with Respect to Vss CAUTION Applying 1.0 V, + 25 V CAUTION Applying + 23 V to the V pp pin without + 25 V to the Vpp pin without F38E70 Timing Characteristics Signal Symbol Min Max Unit Comments (Note 3) XTL 1 XTL 2 to(XTL) Time Base Period, Crystal Mode 250 1000 ns 4 MHz-1 MHz to(LC) Time Base Period, LC Mode 250 1000 ns 4 MHz-1 MHz to(RC) Time Base Period, RC Mode 250 2000 ns 4 MHz-1 MHz to(EX) Time Base Period, External Mode 250 2500 ns 4 MHz-1 MHz tEx(H) External Clock Pulse Width, High 90 2000 ns tEx(L) External Clock Pulse Width, Low 90 2000 ns Characteristic F38E70·21 Timing Characteristics Signal Symbol Min Max Unit Comments (Note 3) XTL 1 XTL 2 to(XTL) Time Base Period, Crystal Mode Characteristic 250 500 ns 4 MHz-2 MHz to(LC) Time Base Period, LC Mode 250 500 ns 4 MHz-2 MHz to(RC) Time Base Period, RC Mode 250 500 ns 4 MHz-2 MHz to(EX) Time Base Period, External Mode 250 500 ns 4 MHz-2 MHz tEx(H) External Clock Pulse Width, High 90 to(EX) - 100 ns tEx(L) External Clock Pulse Width, Low 90 to(EX) - 100 ns 4·68 F38E70·21 Page 17 F38E70 Figure 8 Timing Diagrams F38E70·21 Figure 8 Timing Diagrams Page 18 F38E70 ProgramlVerify Timing _F_38_E_7_0_.2_1-,p_rO_g_r_a_m_/V_e_r_if_y_T_i_m_in_g-r____- .____- ._____ Symbol Parameter Unit Symbol Parameter Unit t pROG Programming Time ms t pROG Programming Time ms Page 19 F38E70 DC Characteristics Symbol Parameter Icc Power Supply Current Po Power Dissipation VTEST Test Pin Voltage for ProgramlVerify Mode ITEST Test Pin Current for ProgramlVerify Mode Min Typ Max 60 330 . Unit Test Conditions mA Outputs Open mW Outputs Open VPR5G=O.4 V, V TEST =23 V F38E70·21 DC Characteristics Symbol Parameter Icc Power Supply Current Po Power Dissipation VTEST Test Pin Voltage for ProgramlVerify Mode ITEST Test Pin Current for ProgramlVerify Mode Min 4·69 Typ Max Unit 70 375 100 550 mA Outputs Open mW Outputs Open Test Conditions l:1li F38E70·21 4·70 F38721F38L72 Single-Chip Microcomputer F=AIRCHILD A Schlumberger Company Microprocessor Product Description Connection Diagram The Fairchild F3872 is a complete 8-bit microcomputer on a single MOS integrated circuit. It can execute the F8 instruction set of more than 70 commands, allowing expansion into multi-chip configurations with software compatibility. The device features 64 bytes of scratchpad RAM, 64 bytes of power-down executable RAM, a programmable binary timer, 32 bits of 110, a single + 5 V power supply requirement, and a choice of 1K, 2K, 3K, or 4K bytes of ROM. A low-power standby option for the executable RAM is available on the F38L72. 40-Pin DIP The F3872 is an expanded memory version of the F3870 single-chip microcomputer. It is identical to the F3870 in the following areas: instruction set, architecture, ac and dc characteristics, and pinout. The only difference between the F3872 and the F3870 lies in the memory expansion and the appropriate memory address registers. • • • • • • • • • Voo RESETIiiA'MPiff' EXT INT PCoIV •• • Utilizing Fairchild's double-ion-implanted, N-channel silicon-gate technology and advanced circuit design techniques, the single-chip F3870 offers maximum cost effectiveness in a wide range of control and logic replacement applications. • • • • XTL, XTL2 P01/VSS· Pl0 po, po, Pl, Pl, STROBE P13 P40 P41 P42 1'43 P44 P4s P50 PSi P5, 1'53 P5. 1'46 P5s P5s P47 1'57 ~ ffi po, Pl, PO. Pl. vss TEST Pl, Single-chip Microcomputer Same Pinout as F3870 Software-Compatible with F8 Family 1024-, 2048·, 3072·, or 4032·Byte Mask·Programmable ROM 64·Byte Scratchpad RAM 32·Bit (4·Port) TTL·Compatible 1/0 Programmable Binary Timer: Interval Timer Mode Pulse Width Measurement Mode Event Counter Mode External Interrupt Crystal, LC, RC, or External Time Base Low Power (285 mW, Typical) Single +5 V:t 10% Power Supply 64 Additional Bytes of Executable RAM Addressable by Program or Data Counter Standby Option for Executable RAM Low Standby Power (8_2 mW) 3.2 V Minimum Standby Supply Voltage No External Components Required to Trickle Charge Battery (Top View) 'Programmable pin; function determined by device option (standard or standby mode). Signal Functions The functions of the F3872 inputs and outputs are described in Table 1. 4-71 • F3872/F38L72 Signal Functions CLOCK { Device Organization XTL, ~P4o XTL2 ~P41 This section describes the basic functional elements of the F3872 shown in Figures 1 and 2. " ' - ' P42 EXTINT DEVICE [ REm/ CONTROL RAMPRT' TEST I/O PORT 0 P43 Main Control Logic The instruction register (IR) receives the operation code (op code) of the instruction to be executed from the program ROM via the data bus. During all op code fetches, eight bits are latched into the IR. Some instructions are completely specified by the upper four bits of the op code; in such instructions, the lower four bits are an immediate register address or an immediate 4-bit operand. Once latched into the IR, the main control logic decodes the instruction and provides the necessary control gating signals to all circuit elements. I/O PORT 4 PO, P54 110 PORT 5 ROM Address Registers There are four 12-bit registers associated with the program ROM of the F3872. (In the F3872-1, -2, and -3, the 12-bit registers can address more memory space than is physically available on the chip; user caution is advised.) These are the program counter (PO), the stack register (P), the data counter (DC), and the auxiliary data counter (DC1). The program counter is used to address instructions or immediate operands. The stack register is used to save the contents of PO during an interrupt or subroutine call. Thus, P contains the return address at which processing is to resume upon completion of the subroutine or the interrupt routine. Pio I'l, P12 I/O PORT 1 I'l, P14 Vss· P15 I'l, VDD i"h Voo Vss* ", The data counter is used" to address data tables. This register is autoincrementing. Of the two data counters, only DC can access the ROM. However, the XDC instruction allows DC and DC1 to be exchanged. Associated with the F3872 address registers is a 12-bit adderlincrementer. This logic element is used to increment PO or DC when required and is also used to add displacements to PO on relative branches or to add the data bus contents to DC in the add data counter (ADC) instruction. Program ROM The microcomputer program and data constants are stored in the program ROM, which may be 1024x 8 (F3872-1), 2048 x 8 (F3872-2), 3072 x 8 (F3872-3), or 4032 x 8 (F3872-4) bytes. When a ROM access. is required, the appropriate address register (PO or DC) is gated onto the ROM address bus and the ROM output is gated onto the main data bus. The first byte in the ROM is location zero. 4-72 F3872/F38L72 Table 1 Signal Functions Pin No. Mnemonic Device Control EXTINT RESETI RAMPRT Description Name 38 External Interrupt Software·programmable input that is also used in conjunction with the timer for pulse width measurement and event counting. 39 External Reset/RAM Protect Input that, in standard operating mode, may be used to externally reset the F3872. When pulled low, the F3872 resets; when then allowed to go high, the F3872 begins program execution at program location H'OOOO'. When RAM standby mode is selected, may be used as RAM protect control. When pulled low, the RAM is disabled and, therefore, protected from any alterations during loss of Voo. TEST 21 Test Line An input used only in testing the F3872. For normal circuit operation, TEST is left unconnected or grounded. 7 Ready Strobe Normally high output that provides a single low pulse after valid data is present on the P4o-P47 pins during an output instruction. XTL 1, XTL2 1,2 Time Base Inputs to which a crystal (1 MHz to 4 MHz), LC network, RC network, or external single·phase clock may be connected. PO O-P0 7 3-6,8-19, 22-37 I/O Ports Thirty·two bidirectional lines that can be individually used as either TTL·compatible inputs or latched outputs; POo and P0 1 may also serve power outputs in standby mode. Power Vee 3 Substrate Decoupling Substrate decoupling power pin that is used only when the standby option is selected; a 0.01 JLF capacitor is required to provide substrate decoupling; alternative function of POo, which is the standard function. Voo 40 Power Input +5 V ± 10% power supply Vse 4 Standby Power The RAM standby power supply if the standby option (+ 5.5 V to + 3.2 V) is selected; alternative function of P0 1, which is the standard function. Vss 20 Ground Signal and power ground Clock STROBE PTO-P1 7 P4 o- P47 P5 5- P57 4·73 • F3872/F38L72 Fig. 1 F3872 Architecture ALU 64 x 8 ACCUMULATOR SCRATCH PAD STATUS REGISTER VDD vs. ISAR PROGRAM COUNTER TEST TEST SEQUENCER STACK REGISTER RESET POWER·ON RESET DATA COUNTER 0 CLOCK LOGIC DATA COUNTER 1 XTL, XTL2 ROM EXT INT RAMPRT· INTERRUPT LOGIC VSB* VBe" ·Standby Mode Only. 64 X 8 Executable RAM The upper 64 bytes of the total memory of the F3a72 is executable RAM. The first byte is at address 4032 decimal (,FCO' hexadecimal). As with the ROM, the RAM may be accessed by the PO and DC address registers. It may be written to via the store (ST) instruction, and it may be read from via the load (LM) instruction. Additionally, instructions may be executed from the RAM. A mask· programmable standby power option is available in which the 64 x a RAM remains powered and protected so that its contents are saved during a loss of the normal circuit power supply. scratchpad bytes via the ISAR. This makes it easy to reference a buffer consisting of contiguous scratch pad bytes. For example, when the low·order octal digit is incremented or decremented, the ISAR is incremented from octal 27 to 20 or is decremented from octal 20 to 27. This feature of the ISAR is very useful in many program sequences. All six bits of the ISAR may be loaded at one time, or either half may be loaded independently. Scratchpad and ISAR The scratchpad provides 64 a·bit registers that may be used as general·purpose RAM. The indirect scratchpad address register (ISAR) is a 6-bit register used to address the 64 registers. All 64 registers may be accessed using the ISAR. In addition, the lower order 12 registers may also be directly addressed. Scratchpad registers 9 through 15 (decimal) are given mnemonic names (J, H, K, and Q) because of special linkages between these registers and other registers, such as the stack register. These special linkages facilitate the implementation of multi·level interrupts and subroutine nesting. For example, the instruction LR K, P stores the lower eight bits of the stack register in register 13 (K lower, or KL) and stores the upper four bits of P in register 12 (K upper, or KU). The scratch pad is not protected by the standby power option. The ISAR can be visualized as holding two octal digits. This division of the ISAR is important, since a number of instructions increment or decrement only the least significant three bits of the ISAR when referencing Arithmetic and Logic Unit (ALU) After receiving commands from the main control logic, the ALU performs the required arithmetic or logic operations (using the data presented on the two input 4-74 F3872/F38l72 Fig. 2 F3872 Block Diagram -..VSS-3*· ..---VOO-40 """"-VSS-20 . - - - - - ' - - - . . . , _ EXT tNT-3S ROM ADDRESS PROGRAM REGISTERS ROM .-------...,_XTL2-1 ....--XTLl-2 po, P, DC, DCl L SCRATCH PAD ~RESET-39 """'-TE5T-21 ~POO-3 ~po,-4 INDIRECT ' -_ _ _-.J\I -;=====: 1----'\ ADDRESS .....----.-. POz-5 ~P03-6 SCRATCHPAO .........-.... P04-19 REGISTERS ~P05-18 ~P06-17 REGISTER ....--.. P07-16 ~===! .....-....... P1o-37 ~Pf1-36 :=::: ~=~; ~P14-22 .............. J5"f5-23 ACCUMULATOR STATUS ~Pl6-24 ~PT7-25 ~====~~ P4o-8 ............... "P41-9 ALU ~P42-10 . . . - - . f.f43"-11 ............... J544-12 ~P4s-13 . . - - - . P46-14 ~P47-15 :==:::::!:==~~--:-STROBE -7 ....-.... PSo-33 ......-.... P5"1-32 ~P52-31 ~ P53-3a ............... ~-29 Standby Mode Options Only: * Alternate :=::: ~=~~ Function for Pin 4 * * Alternate Function for Pin 3 L..._ _ _ _-I~ P57-26 ... Alternate Function for Pin 39 buses) and provides the result on the result bus. The arithmetic operations that can be performed in the ALU are binary add, decimal adjust, add with carry, decrement, and increment. The logiC operations that can be performed are AND, OR, exclusive·OR, ones complement, shift right, and shift left. Besides providing the result on the result bus, the ALU also provides four signals presenting the status of the result. These Signals, stored in the status register (W), represent the CARRY, OVERFLOW, SIGN, and ZERO conditions of the resu It of the operation. Accumulator The accumulator (ACC) is the principal register for data manipulation within the F3872. The ACC serves as one fnput to the ALU for arithmetic or logical operation. The results of ALU operations are stored in the ACC. 4·75 F38721F38L72 The interrupt control bit (ICB) of the status register may be used to allow or disallow interrupts in the F3872. This bit is not the same as the two interrupt enable bits in the interrupt control port (ICP). If the ICB is set and the F3872 interrupt logic communicates an interrupt request to the CPU section, the interrupt is acknowledged and processed upon completion of the first non-privileged instruction. If the ICB is cleared, an interrupt request is not acknowledged or processed until the ICB is set. Status Register The status register (also referred to as the W register) holds five status flags, as follows: _BIT NO. STATUS REGISTER (W) SIGN L---CARRY 110 Ports ' - - - - - - ZERO The F3872 provides four complete bidirectional 110 ports; these are ports 0, 1, 4, and 5. In addition, the interrupt control register is addressed as port 6 and the binary timer is addressed as port 7. An output instruction (OUT or OUTS) causes the contents of the ACC to be latched into the addressed port. An input instruction (IN or INS) transfers the contents of the port to the ACC (port 6 is an exception that is described later). The 110 pins on the F3872 are logically inverted. The schematic of an I/O pin and conceptual illustrations of available output drive options are shown in Figure 3. ' - - - - - - - - OVERFLOW ' - - - - - - - - - - I N T E R R U P T CONTROL BIT Summary of StatuB Bit OVERFLOW ZERO CARRY 7 (B CARRY s ALU7 1\ ALUs 1\ ALU s ALU 3 1\ ALU2 1\ ALU 1 1\ ALU 4 1\ ALUo CARRY SIGN Fig_ 3 1/0 Port Diagram VDD z0 ;:: c PORT 1/0 PIN a: ::> " ii: l- .. .. a: Z 0 "9a: I- e ! a: 0 0 Q Q a: 9 cw c I; STANDARD OUTPUT OPEN DRAIN OUTPUT DIRECT DRIVE OUTPUT Ports 0 and 1 are standard output type only. Ports 4 and 5 may be any of the three output options, each pin individually assignable to any port. The STROBE output is always configured similar to a standard output, except that it is capable of driving three TIL loads. The RESET and EXT INT pins may have standard 6 kO (typical) pull·up or may have no pull-up. 4-76 F38721F38L72 An output ready strobe is associated with port 4. This flag may be used to signal a peripheral device that the F3872 has just completed a single low pulse shortly after the output operation is completely finished, so either edge may be used to signal the peripheral. This STROBE signal may also be used to request new input information from a peripheral simply by dOing a dummy output of H '00' to port 4 after completing the input operation. The desired timer mode, prescale value, starting and stopping the timer, active level of the EXT INT pin, and local enabling or disabling of interrupts are selected by outputting the proper bit configuration from the accumulator to the ICP (port 6) with an OUT or OUTS instruction. Bits within the ICP are defined as follows: Interrupt Control Port (Port 6) Bit Bit Bit Bit Bit Bit Bit Bit Timer and Interrupt Control Port The timer Is an 8-blt binary down counter that is software·programmable to operate in one of three modes: the interval timer mode, the pulse width measurement mode, or the event counter mode; the timer characteristics are described in Table 2. As shown in Figure 4, associated with the timer is an 8-bit register called the interrupt control port, a programmable prescaler, and.an 8-bit modulo-N register; a functional logic diagram is shown in Figure 5. Table 2 O-Externallnterrupt Enable 1-Timer Interrupt Enable 2-EXT INT Active Level 3-StartlStop Timer 4-Pulse Widthllnterval Timer 5- + 2 Timer Prescale Values 6- + 5 Timer Prescale Values 7 - + 20 Timer Prescale Values A special situation exists when reading the ICP with an IN or INS instruction. The accumulator is not loaded with Timer Characteristics Characteristic Value Interval Timer Mode Single Interval Error, Free-Running (Note 3) ±6tt/> Cumulative Interval Error, Free-Running (Note 3) 0 ±(tpsc+tt/» Error Between Two Timer Reads (Note 2) start Timer to Stop Timer Error (Notes 1,4) + ttl> to - (tpsc + tt/» Start Timer to Read Timer Error (Notes 1,2) - 5tt/> to - (tpsc + 7tt/» Start Timer to Interrupt Request Error (Notes 1,3) Load Timer to Stop Timer Error (Note 1) -2tt/> to - 8tt/> + tt/> to - (tpsc + 2tt/» Load Timer to Read Timer Error (Notes 1, 2) - 5tt/> to - (tpsc + 8tt/» Load Timer to Interrupt Request Error (Notes 1, 3) - 2tt/> to - 9tt/> Pulse Width Measurement Mode Measurement Accuracy (Note 4) + tt/> to - (tpsc + 2tt/» Minimum Pulse Width of EXT INT Pin 2tt/> Event Counter Mode Minimum Active Time of EXT INT Pin 2tt/> Minimum Inactive Time of EXT INT Pin 2tt/> Definitions Error= Indicated time value - actual time value tpsc = t> X prescale value Note. 1. All times that entail loading, starting, or stopping the timer are referenced from the end 01 the last machine cycle of the OUT or OUTS instruction. 2. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS Instruction. 3. All times that entail the generation of an interrupt request are relerenced from the start of the machine cycle In which the appropriate interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multi·cycle Instruction. 4. Error may be cumulative If operation is repetitively performed. 4-77 F3872/F38L72 An OUT or OUTS instruction to port 7 loads the contents of the accumulator into both the timer and the 8-bit modulo-N register, resets the prescaler, and clears any previously stored timer interrupt request. As previously noted, the timer is an 8-bit down counter that is clocked by the prescaler in the interval timer mode and in the pulse width measurement mode. The prescaler is not used in the event counter mode. The modulo-N register is a buffer whose function is to save the value that was most recently output to port 7. The modulo-N register is used in all three timer modes. the contents of the ICP; instead, accumulator bits 0 through 6 are loaded with zeros, while bit 7 is loaded with the logic level being applied to the EXT INT pin, thus allowing the status of the EXT INT pin to be determined without the necessity of servicing an external interrupt request. This capability is useful in establishing a high-speed, polled handshake procedure or for using EXT INT as an extra input pin if external interrupts are not required and the timer is used only in the interval timer mode. The rate at which the timer is clocked in the interval timer mode is determined by the frequency of an internal clock and by the division value selected for the prescaler. (The internal clock operates at one-half the external time base frequency.) If·ICP bit 5 is set and bits 6 and 7 are cleared, the prescaler divides by 2. Likewise, if bit 6 or 7 is individually set, the prescaler divides by 5 or 20, respectively. Combinations of bits 5, 6, and 7 may also be selected. For example, if bits 5 and 7 are set while bit 6 is cleared, the prescaler divides by 40. Thus, possible prescaler values are: .;. 2, .;. 5, .;. 10, .;. 20, .;. 40, .;. 100, and.;. 200. Interval Timer Mode - When ICP bit 4 is cleared (logic 0) and at least one prescale bit is set, the timer operates in the interval timer mode. When bit 3 of the ICP is set, the timer starts counting down from the modulo-N value. After counting down to H '01', the timer returns to the modulo-N value at the next count. On the transition from H '01' to H 'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch is set by the transition of H' N' in the timer, thus allowing a full 256 counts if the modulo-N register is preset to H '00'. If bit 1 of the ICP is set, the interrupt request is passed to the CPU section of the F3872. However, if bit 1 of the ICP is a logic 0, the interrupt request is not passed, but the interrupt request latch remains set. If ICP bit 1 is subsequently set, the interrupt request is then passed to the CPU. Only two events can reset the timer interrupt request latch: when the timer interrupt request is acknowledged by the CPU, or when a new load of the modulo-N register is performed . Any of three conditions cause the prescaler to be reset: whenever the timer is stopped by clearing ICP bit 3, on execution of an output instruction to port 7 (the timer is assigned port address 7), or on the trailing edge transition of the EXT INT pin when in the pulse width measurement mode. These last two conditions are explained in the following paragraphs. . Fig. 4 Timer and Interrupt Control Port Block Diagram PRESCAlER EXTERNAL TIME BASE CLOCK 2. 5, 10. 20, 40, 100, or 200 INT REO INTERRUPT CONTROL PORT (PORT 6) ·EVENT COUNTER MODE ____ ... 2 PRESCAlE ____ ... 5 PRESCAlE ---+ 10 PRESCALE .- ... 20 PRESCAlE ... 40 PRESCAlE ... 100 PRESCAlE ... 2QO PRESCAlE ---------____ lJ 3 2~~i L-:X:~TR::~ L INTERRUPT ENABLE TIMER INTERRUPT ENABLE EXT INT ACTIVE LEVEL START/STOP TIMER '---------;.~ PULSE' WIDTHIINTERVAl TIMER 4·78 EXT INT Fig. 5 Timerllnterrupt Functional Diagram FROM INTERRUPT CONTROL PORT 82 I 84 83 85 B6 87 80 I 81 '1' SELECTS TIMER INTERRUPT TIME BASE • LOADS INTERRUPT VECTOR H '020' UPON COMPLETION OF THE FIRST NON- PRIVILEGED INSTRUCTION ....:.., ACKNOWLEDGE TIMER INTERRUPT clock periods. For a 2 MHz > clock (4 MHz time base frequency), this produces 2 ms intervals. Pulse Width Measurement Mode - When ICP bit 4 is set (logic 1) and at least one prescale bit is set, the timer operates in the pulse width measurement mode. This mode is used for accurately measuring the duration of a pulse applied to the EXT INT pin. The timer is stopped and the prescaler is reset when the EXT INT pin is at its inactive level. The active level of EXT INT is defined by ICP bit 2: if cleared, EXT INT is active-low; if set, EXT INT is active-high. If ICP bit 3 is set, the prescaler and timer start counting when EXT INT transfers to the active level. When EXT INT returns to the inactive level, the timer stops, the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external interrupts are not latched if the ICP interrupt enable bit is not set.) The range of possible intervals is from 2 to 51,200 > clock periods (1 P.s to 25.6 ms for a 2 MHz clock). However, approximately 50 > periods is a practical minimum because the time between setting the interrupt request latch and the execution of the first instruction of the interrupt service routine is at least 29 > periods (the response time is dependent upon how many privileged instructions are encountered when the request occurs). To establish time intervals greater than 51,200 clock periods is simply a matter of using the timer interrupt service routine to count the number of interrupts, saving the result in one or more of the scratch pad registers until the desired interval is achieved. With this technique, virtually any time interval, or several time intervals, may be generated. As in the interval timer mode, the timer may be read at any time, or may be stopped at any time by clearing ICP bit 3, the prescaler and the ICP bit 1 function as previously described; the timer still functions as an B-blt binary down counter with the timer interrupt request latch being set on the timer's transition from H '01' to H' N ' (modulo-N value). Note that the EXT INT pin has nothing to do with loading the timer; Its action Is that of automatically starting and stopping the timer and of generating external Interrupts. Pulse widths longer than the prescaler value times the modulo-N value are easily measured by using the timer Interrupt service routine to store the number of timer interrupts in one or more scratch pad registers. The timer may be read at any time and In any mode using an input instruction (IN 7 or INS 7); this may take place on-the-fly without interfering with normal timer operation. The timer may also be stopped at any time by clearing bit 3 of the ICP. The timer holds its current contents indefinitely and resumes counting when bit 3 is again set. The prescaler, however, is reset whenever the timer is stopped; thus, a series of starts and stops results in a cumulative truncation error. As for accuracy, the actual pulse duration Is typically Slightly longer than the measured value because the status of the prescaler is not readable and Is reset when the timer is stopped. Thus, for maximum accuracy, It is advisable to use a smail-division setting for the prescaler. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests may be in error by ± 6 > clock periods, although the cumulative error over many intervals is zero. The prescaler and timer generate precise intervals for setting the timer interrupt request latch, but the time-out may occur at any time within a machine cycle. (There are two types of machine cycles: short cycles that consist of four > clock periods, and long cycles that consist of 6 > clock periods.) In the multi-chip FB family, there is a signal referred to as the write clock, which corresponds to a machine cycle. Interrupt requests are synchronized with the internal write clock, thus giving rise to the possible ± 6 > error. Additional errors may arise due to the interrupt request occurring while a privileged instruction or multi-cycle instruction is being executed. Nevertheless, for most applications, all of the above errors are negligible, especially if the desired time interval is greater than 1 ms. Event Counter Mode - When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6, and 7) are cleared, the timer operates In the event counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer decrements on each transition from the inactive level to the active level of the EXT INT pin. The prescaler is not used in this mode but, as in the other two timer modes, the timer may be read at any time, or may be stopped at any time by clearing ICP bit 3; ICP bit 1 functions are previously described, and the timer Interrupt request latch Is set on the timer's transition from H '01 ' to H 'N' (modulo-N value). Normally, ICP bit 0 should be kept cleared in the event counter mode; otherwise, external interrupts are generated on the transition from the inactive level to the active level of the EXT INT p.in. 4·80 F3872/F38L72 guarantee that the power·on clear will operate under every power-up condition. For the event counter mode, the minimum pulse width required on the EXT INT pin is 2 '" clock periods, and the minimum inactive time is 2 '" clock periods; therefore, the maximum repetition rate is 500 Hz. The power-on clear circuitry contains on-Chip sensors to monitor various conditions. The following conditions must be satisfied before the power-reset sequence is allowed to start: External Interrupts When the timer is in the interval timer mode, the EXT INT pin is available for non·timer-related interrupts. If ICP bit o is set, an external interrupt request latch is set when there is a transition from the inactive level to the active level of the EXT INT pin (EXT INT is an edge-triggered input). The interrupt request is latched until either acknowledged by the CPU or ICP bit 0 is cleared (unlike timer interrupt requests, which remain latched even when ICP bit 1 is cleared). External interrupts are handled in the same fashion when the timer is in the pulse width measurement mode or in the event counter mode, except that in the pulse width measurement mode the external interrupt request latch is set on the trailing edge of the EXT INT input; that is, on the transition from the active level to the inactive level. 1. Supply voltage must be above a certain value, typically + 3 V to +4 V. 2. The clocks of the device must be functioning. 3. The substrate bias must reach a certain level. All three conditions must be met before the power-on clear circuitry initiates a reset cycle. However, these conditions can be satisfied even with a supply voltage of as low as 3 volts. The latest versions of the F3872 have a modified delay circuit that gives a typical delay of 500 ,.s (with a 4 MHz crystal) after the above conditions are met. This is an improvement over the earlier F3872 versions. Since the F3872 is only guaranteed to operate at a supply voltage of 4.5 V or greater, the user must ensure that the supply voltage is at least 4.5 V when the F3872 initiates the reset cycle. For power supplies having a slow rise time, an external RC network can be converted to the external reset input of the F3872 to hold the device in a reset state long enough to allow the power supply to reach a voltage of 4.5 V. Interrupt Handling When either a timer or an external interrupt request is communicated to the CPU section of the F3872, it is acknowledged and processed at the completion of the first non-privileged instruction if the interrupt control bit of the status register is set. If the interrupt control bit is not set, the interrupt request continues either until the interrupt control bit is set and the CPU acknowledges the interrupt or until the interrupt request is cleared as previously described. +5V R If there are a timer interrupt request and an external interrupt request when the CPU starts to process the requests, the timer interrupt is handled first. F3872 When an interrupt is allowed, the CPU requests that the interrupting element pass its interrupt vector address to the program counter via the data bus. The vector address for a timer interrupt is H '20'; the vector address for an external interrupt is H'OAO'. After the vector address is passed to the program counter, the CPU sends an acknowledge signal to the appropriate interrupt request latch, which clears that latch. The execution of the interrupt service routine then commences. The return address of the original program is automatically saved in the stack register, P. EXTERNAL RESET External Reset When the RESET input is low, the contents of the program counter are pushed to the stack register and the program counter and the ICB of the status register are cleared. The original stack register contents are lost. As with power-on clear, ports 4, 5, 6, and 7 are loaded with H '00'. The contents of all other registers and ports are unchanged. When RESET is high, the first program instruction is fetched from ROM location H '0000'. Power-On Clear The F3872 contains power-on clear circuitry to automatically reset the internal logic following the application of external power. Since many variations of power supply circuitry exist, Fairchild cannot Test Logic Special test logic is implemented to allow access to the internal main data bus for test purposes. 4-81 F38721F38L72 In normal operation, the TEST pin is unconnected or Is connected to ground. When TEST is placed at a level of from 2.8 V to 3.0 V, port 4 becomes an output of the internal data bus and port 5 becomes a wired-OR input to the internal data bus. The data appearing on the port 4 pins is logically true, whereas input data forced on port 5 must be logically false. When TEST is placed at a high level (8.8 V to 9.0 V), the ports act a~ described above and, additionally, the program ROM is prevented from driving the data bus. In this mode, operands and instructions may be forced externally through port 5 instead of being accessed from the program ROM. When TEST is in either the TIL state or the high state, STROBE ceases its normal function and becomes a cycle clock (identical to the F8 multi-chip system write clock, except Inverted). Two modes are recommended for powering down. In the first mode (see Figure 6A), the processor must be interrupted early enough to save all necessary data before the Vee falls below the minimum level. After the' save is done, the RESETIRAMPRT pin can fall. This prevents any further RAM accesses; Voo may then fall. The second mode (see Figure 68) may be used if a special save data routine is not needed. External interrupt need not be used, and the only requirement to save the RAM data is that RAMPRT be low for Voo drops below 4.5 V. For example, if a few key variables are to be stored in power-down RAM and it is desired that these be saved during a loss of power, two copies of each variable are kept with an associated flag in the powerdown RAM; thus, no interrupt and save roiJtine is necessary. The method of updating a variable is as follows: Timing complexities render the capabilities associated with the TEST pin impractical for use in a user application, but these capabilities are sufficient to enable Fairchild to implement a rapid method for thoroughly testing the F3872. Clear Flag Word 1 Update Variable (Copy 1) Set Flag Word 1 Clear Flag Word 2 Update Variable (Copy 2) Set Flag Word 2 Standby Power Option If the standby power option is not selected, bits 0 and 1 of port 0 can be read from and written to. If the standby power-down option is selected, port 0 bit 1 is readable only; bit 0 remains both readable and writeable via software, although it is not connected to a package lead. The standby power source (VsS> is connected to pin 4. (A 0.01 p.F capacitor must be connected to pin 3; the purpose of this capacitor Is to decouple noise coupled to the substrate of the circuit when Voo is switched off and on.) Nickel-cadmium batteries (typical voltage of three series cells is 3.6 V) are recommended for use as the standby power source, since the F3872 can automatically trickle charge three such cells. If more than three cells in series are used, a charging circuit must be provided outside the F3872. When the RESET/RAMPRT pin Is brought low, the standby RAM (64 8-bit words in POIDC address spaces 4032 to 4096 10, or FC0 16 to FFF 16) is disabled from being read from or written to. The RAM itself is also switched from Voo power to the VSB power. Execution may terminate at any time, even during the update of a variable of flag word, causing that byte In scratchpad to be "bad" data. There is always a "good" data byte that contains either the most recent or nextmost recent value of the variable. Any copy of the variable in which the flag word is set is a good data byte While this method significantly encumbers the data storage process, it eliminates the need for a power fail interrupt, which reduces external circuitry and leaves the external interrupt pin completely free for other uses. In either power-down mode, theRESET/RAMPRT signal should be held low until Voo is above the minimum level when power returns. 4-82 F3872/F38L72 Fig. 6 Standby Power Option Modes A. Data Save Routine, VSB ~ 3.2 V VDD SUSTAINED BY CAPACITOR OR BATTERY UNTIL IIAMI'IfT BROUGHT LOW VDD--------------------__~----------~ MAIN POWER SUPPLY FAILURE DETECTED --_/ -_/ 1 EXT INT ----------------"""' RESET/RAMPRT ----------------------I-----------{ DATA SAVE MUST BE DONE HERE B. No Save Routine, V SB ~ ~- - - - - - A·C·-CE-S - T-O- ~BEGINSAGAIN !1 "~n~ I - - - - - - - - RAM INHIBITED 3.2 V VDD-_~,- _ _ _ / MAIN POWER FAILURE DETECTED RAMPRTIR~ET--------------~~~ __________________ 4·83 ~,~--------------------~~ F3872/F38L72 F3872 Clocks Fig. 7 F3872 Clock Configurations External Mode Crystal Mode The time bases for the F3872 may originate from one of four external sources; the four external configurations are shown in Figure 7. There is an internal 26.5 pF capacitor between XTL 1 and GND, and also between XTL2 and GND. Thus, external capacitors are not required. In all external clock modes, the external time base frequency is divided by 2 to form the internal clock. . OPEN ATCUT1 - 4 MHz + Instruction Set EXTERNAL CLOCK LC Mode RC Mode vee The F3872 executes the entire instruction set of the multi·chip F8 family (F3850 family), as shown in Table 3. Of course, the STORE instruction only accesses memory in locations FFO-FFF(the data counter however Is incremented each time STORE is exec~ted). ' r;:]L ~ * ;;:I::; A summary of programmable registers and ports is given in Figure 8. AlsO, for convenient reference, a programming model of the F3872 is given in Figure 9. Mask Options The ROM array may contain object program code andlor tables of nonvarying data. Every F3872 is implemented using a custom mask that specifies the state of every ROM bit; as well as certain address mask options that are external to the ROM array. The following mask options are specified: 1. The 1024,2048,3072, or 4096 bytes of ROM storage. This reflects programs and permanent data tables stored in the PSU memory. 2. Inputloutput ports can be any of the following three configurations: a. Standard pull·up b. Open drain c. Direct drive 3. Input/output ports 0 and 1 can be specified either cleared or unaltered following an external reset. 4. External interrupt and external reset can be specified to have or omit an internal pull·up resistor. 5. The 110 port output option choices are: the standard pull·up (option A), the open drain (option B), and the driver pull·up (option C). CEXTERNAL (OPTIONAL-CAN BE OMITTED) L_-l~_J CEXTE"HAL (OPTIONAL) Minimum R=4kll Minimum L=O.l mH Minimum Q=4O C = 20.5 pF ± 2.5 pF + CEXTERNAL Maximum CEXTERNAL 1 f M1N ", 1.1 RC+65 ns C= 10 pF± 1.3 pF+CeXTERNAL 1 fMAX'" 1.0 RC+ 15n8 1 f .. 2".v'[C Example with CEXTERNAL = 0 Example with CEXTERNAL = 0 R=15k!l±5% f '" 2.9 MHz±26% L=O.3mH±10% f .. 3.0 MHz± 10% =30 pF HP2644/HP2645 cartridge (Formulator format only). Other options must be specified on the Fairchild ROM Code Entry Form, available from a Fairchild representative. Supplementary Notes For total software compatibility when expanding into a multi·chip configuration, the F3871 Peripheral Input/Output Circuit should be used. The F3871 has the same improved timer (binary count, readable, and three modes of operation) and ready strobe outputs as the F3872. The interrupt control bit of the status register is automatically reset when an interrupt request is acknowledged. It is then the programmer's responsibility to determine when the ICB is again to be set (by executing the E1 instruction). This action prevents an interrupt service routine from being interrupted unless the programmer so desires. The format for mask options must be submitted to Fairchild Microprocessor Division before device manufacture. The data to be stored in permanent memory may be submitted in the form of an EPROM or 4-84 F3872/F38L72 Table 3 F3872 Instruction Set Accumulator Group Instructions Operallon Add Carry Add Immediate AND Immediate Clear Compare Immediate Complement Exclusive OR Immediate Increment Load Immediate Load Immediate Short OR Immediate Shift Left One Shift Left Four Shift Right One Shift Right Four Mnemonic OP Code LNK AI NI CLR CI COM XI INC LI LIS 01 SL SL SR SR Operand ii ii ii ii ii i ii 1 4 1 4 Funcllon ACC-(ACC)+ CRY ACC-(ACC)+ H'ii' ACC-(ACC) A H'ii' ACC-H'OO' H'ii'+(ACC)+ 1 ACC-(ACC)e H'FF' ACC-(ACC)e H'ii' ACC-(ACC)+ 1 ACC-H'ii' ACC-H'Oi' ACC-(ACC) V H'ii' SHIFT LEFT 1 SHIFT LEFT 4 SHIFT RIGHT 1 SHIFT RIGHT 4 Machine Code Byle. Cycle. 19 24 ii 21 ii 70 25 ii 18 23 ii 1F 20 ii 7i 22 ii 13 15 12 14 1 2 2 1 2 1 2 1 2 1 2 1 1 1 1 1 2.5 2.5 1 2.5 1 2.5 1 2.5 1 2.5 1 1 1 1 Slalua BII. OVF ZERO CRY SIGN 110 110 0 110 110 110 1/0 1/0 0 110 1/0 1/0 1/0 0 0 110 110 1/0 1/0 110 1/0 0 0 1/0 1/0 110 1/0 1/0 - - - 110 1/0 1/0 1/0 1/0 0 0 0 0 0 110 1/0 1/0 1 1 - 0 0 0 0 0 - Branch Instructions (In All Conditional Branches, PO (PO) + 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.) Operation Branch on Carry Branch on Positive Branch on Zero Branch on True Mnemonic OP Code Operand BC BP BZ BT aa aa aa t,aa Function PO-I(PO)+ PO-I(PO)+ PO-I(PO)+ PO-I(PO)+ 1)+ H'aa' 1)+ H'aa' 1)+ H'aa' 1)+ H'aa' if if if if CRY= 1 SIGN = 1 ZERO= 1 any test is true Machine Code Byle. Cycle. 82 aa 81 aa 84 aa 8t aa 2 2 2 2 3.5 3.5 3.5 3.5 Sialu. BII. OVF ZERO CRY - - - - - SIGN - - t = TEST CONDITION I 22 I 21 I 2° I IZERO I CRY ISIGN I Branch Branch Branch Branch Branch if if if if if Negative No Carry No Overflow Not Zero False Test BM BNC BNO BNZ BF aa aa aa aa t,aa PO-I(PO)+ PO-I(PO)+ PO-[(PO)+ PO-[(PO)+ PO-[(PO)+ 1)+ H'aa' if SIGN=O 1)+ H'aa' if CARRY*O 1)+ H'aa' if OVF=O 1)+ H'aa' if ZERO=O 1)+ H'aa' if all false test bits 91 aa 92 aa 98 aa 94 aa 9t aa 2 2 2 2 8F aa 2 90 aa 29 aaaa 2 3 2 3.5 3.5 3.5 3.5 3.5 - - - - - - - - - - - - t=TEST CONDITION I 23 I 22 I 21 I 2° I I OVF IZERO ICRY I SIGN I Branch if ISAR (Lower) 7 BR7 aa Branch Relative Jump· BR JMP aaaa aa PO-I(PO)+ 1)+ H'aa' if ISARL*7 PO-(PO)+ 2 if ISARL= 7 PO-I(PO)+ 1)+ H'aa' PO-H'aaaa' 2.5 2.0 3.5 5.5 - - - - Memory Reference Instructions (In All Memory Reference Instructions, the Data Counter Is Incremented DC-DC.1.) Operallon Add Binary Add Decimal AND Compare Exclusive OR Load Logical OR Store .. Mnemonic OP Code AM AMD NM CM XM LM OM ST Operand Funcllon ACC-(ACC)+ I(DC)) ACC-(ACC) + I(DC) ACC-(ACC) A [(DC) [(DC)) + (ACC) + 1 ACC-(ACC)e I(DC) ACC-I(DC) ACC-(ACC) V I(DC)) (DC)-(ACC) • PriVileged instruction Nole JMP and PI change accumulator contents to the high byte address. 4-85 Machine Code Byle. Cycles 88 89 8A 80 8C 16 8B 17 1 1 1 1 1 1 1 1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Sialus BII. OVF ZERO CRY 1/0 1/0 0 1/0 0 110 110 1/0 1/0 1/0 - - 0 110 - - SIGN 110 1/0 0 1/0 0 1/0 110 1/0 110 1/0 0 1/0 - - - - F3872/F38L72 Table 3 F3872 Instruction Set (Cont.) Address Register Group Instructions Operation Mnemonic OP Code Add to Data Counter Call to Subroutine Call to Subroutine Immediate Exchange DC Load Data Counter Load Data Counter Load DC Immediate ADC PK' PI' XDC LR LR DCI LR LR POP' LR LR LR Load Program Counter Load Stack Register Return From Subroutine Store Data Counter Store Data Counter Store Stack Register Operand aaaa DC,a DC,H aaaa PO,a P,K a,DC H,DC K,P Function DC-(DC)+ (ACC) P-(PO); POU-(r12); PL-(r13) P-(P); PO-H'aaaa'; DC-DC1 DCU-(r14); DCL-(r15) DCU-(r10); DCL-(r11) DC-H'aaaa' POU-(r14); POL-(r15) PU-(r12); PL-(r13) PO-(P) r14-(DCU); r15-(DCL) r10-(DCU); r11-(DCL) r12-(PU); r13-(P) Machine Code Bytes Cycles Status Bits OVF ZERO CRY 8E OC 28 aaaa 2C OF 10 2A aaaa 00 09 1C OE 11 08 1 1 3 1 1 1 3 1 1 1 1 1 1 2.5 4 6.5 2 4 4 6 - - - - 4 - - - - 4 2 4 4 4 - - - Machine Code Bytes Cycles Cr Dr 3r 4r 00 01 02 03 5r 04 05 06 07 Fr Er 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1.5 1 1 1 1 1 1 1 1 1 1 1 1 Machine Code Bytes Cycles 1 1 2 1 1 1 1 1 2 2 4 4'" 1 1 1 2 1 4 4'" 1 1 - - - - - - - - - - - - - - SIGN - - - - - - Scratch pad Register Instructions (Refer to Scratch pad Addressing Modes) Operation Mnemonic OP Code Operand AS ASD OS LR LR LR LR LR LR LR LR LR LR NS XS r r r A,r A,KU A,KL A,aU A,aL r,A KU,A KL,A aU,A aL,A r r Mnemonic OP Code Operand Add Binary Add Decimal Decrement Load Load Load Load Load Load Load Load Load Load AND Exclusive OR Function ACC-(ACC)+ (r) ACC-(ACC) + (r) r-(r)+ H'FF' ACC-(r) ACC-(r12) ACC-(r13) ACC-(r14) ACC-(r15) r-(ACC) r12-(ACC) r13-(ACC) r14-(ACC) r15-(ACC) ACC-(ACC) A (r) ACC-(ACC)<>(r) Status Bits OVF ZERO CRY 1/0 1/0 1/0 1/0 1/0 1/0 - - - - - - - - 110 1/0 1/0 - - - - - - - 0 0 - - 1/0 1/0 0 0 - - SIGN 110 110 1/0 - 1/0 1/0 Miscellaneous Instructions Operation Disable Interrupt Enable Interrupt' Input Input Short Load I,SAR Load ISAR Lower Load ISAR Upper Load Status Register' No·Operation Output Output Short Store ISAR Store Status Register 01 EI IN INS LR LlSL LlSU LR NOP OUT OUTS LR LR aa a IS,A a a W,J aa a A,IS J,W Function RESET ICB SET ICB ACC-(INPUT PORT aa) ACC-(INPUT PORT a) ISAR-(ACC) ISARL-a ISARU-a W-(r9) PO-(PO)+ 1 OUTPUT PORT aa-(ACC) OUTPUT PORT a - (ACC) ACC-(ISAR) r9-(W) 'Privileged instruction "3·blt octal digit "'Two machine cycles for CPU ports ;Conterits of ACC destroyed 4·86 1A 1B 26 aa Aa OB 01101a" 01100a" 10 2B 27 aa Ba OA 1E 1 2 1 1 1 Status Bits OVF ZERO CRY SIGN - - - - - 0 0 1/0 1/0 1/0 110 - - 0 0 - - - 1/0 1/0 1/0 1/0 - - - - - - - - - - F3872/F38L72 Table 3 F3872 Instruction Set (Cont.) Notes Each lower case character represents a hexadecimal digit. Each cycle equals four machine clock periods. Lower case denotes variables specified by the programmer. J K Kl KU PO pal POU P Pl PU Q Ql QU r W Function Dellnltons is replaced by () the contents of (-) binary ones complement of + arithmetic add (binary or decimal) .. logical OR exclusive logical AN D A V logical OR inclusive H'#' hexadecimal digit Register a A DC DCl DCl DCU H i and ii ICB IS ISAR ISARl ISARU Names address variable accumulator data counter (indirect address register) data counter #1 (auxiliary data counter) least significant eight bits of data counter addressed most significant eight bits of data counter addressed scratchpad register #10 and #11 immediate operand interrupt control bit indirect scratch pad address register indirect scratchpad address register least significant three bits of ISAR most significant three bits of ISAR Scratchpad Addressing Modes (Machine Code Format) r= C (hexadecimal) register addressed by ISAR (unmodified) r= D (hexadecimal) register addressed by ISAR; ISARl incremented r= E (hexadecimal) register addressed by ISAR; ISARL decremented r= F (no operation performed) r = O-B (hexadecimal) register a through 11 addressed directly from the instruction Status Register no change in condition 1/0 is set to 1 or 0, depending on conditions CRY carry flag When reading the interrupt control port (port 6), bit 7 of the accumulator is loaded with the actual logic level being applied to the EXT INT pin, regardless of the status of ICP bit 2 (the EXT INT active level bit); that is, if the EXT INT pin is at + 5 V, bit 7 of the accumulator is set to a logic 1, but if the EXT INT pin is at ground, accumulator bit 7 is reset to logic O. For the F3872, execution of an INS or OUTS instruction requires two machine cycles for ports 0 and 1, whereas ports 4 and 5 require four machine cycles. When an external reset of the F3872 occurs, PO pushes intoP and the old contents of P are lost. It must be noted that an external reset is recognized at the start of the machine cycle and not necessarily at the end of an instruction. Thus, if the F3872 is executing a multi-cycle instruction, that instruction is not completed and the contents of P upon reset may not necessarily be the address of the instruction that would have been executed next. It may, for example, pOint to an immediate operand if the reset occurred during the second cycle of an L 1 or C1 instruction. Additionally, several instructions (JMP, P1, PK, LR, PO and 0) as well as the interrupt acknowledge sequence modify PO in parts. That is, they alter PO by loading first one part, then the other, and the entire operation takes more than one cycle. Should reset occur during this modification process, the value pushed into P is part of the old PO (the as-yet unmodified part) and part of the new PO (already-modified part). Thus, care should be taken (perhaps by external gating) to ensure that reset does not occur at an undesirable time if any significance is to be given to the contents of P after a reset occurs. In Table 3, the number of cycles shown is "nominal machine cycles." A nominal machine cycle is defined as 4 cf> clock periods, thus requiring 2 P.s for a 2 MHz clock frequency (4 MHz external time base frequency). Table 3 also uses the following nomenclature for register names: F8 -F3872 PC o = PO PC , P DC o = DC DC, = DC1 = scratchpad register #9 registers #12 and #13 register #13 register #12 program counter least significant eight bits of program counter most significant eight bits of program counter stack register least significant eight bits of program counter most significant eight bits of active stack register registers #14 and #15 register #15 register #14 scratchpad register (any address through 11) status register Program Counter Stack Register Data Counter Auxiliary Data Counter This nomenclature is used to be consistent with the assembly language mnemonics. 4-87 F38721F38L72 Fig. 8 Programmable Registers and Ports ACCUMULATOR I I A 1~lolzlclsl STATUS REGISTER W BYTE ADDRESS SCRATCH PAD DEC I • 3 INDIRECT SCRATCHPAD ADDRESS 0 HEX OCT A 12 0 IS REGISTER 11 AUX DATA COUNTER I 11 HU DCl H 11 DATA COUNTER I 10 HL 11 8 KU 12 C ,. KL 13 0 15 OU " 0 DC 16 15 OL 13 17 10 20 58 3A 72 59 38 73 60 3C 7' 75 16 11 STACK REGISTER I I P I § 11 PROGRAM COUNTER I BINARY TIMER PO PORT 61 3D 62 3E 76 63 3' 77 110 PORT 0 7 INTERRUPT CONTROL PORT PORT 6 I/O PORT 1 110 PORT 4 I L-____________-J~ STROBE I/O PORT 5 4·88 Fig. 9 Programming Model OUTS 7 AOC INS*7 STATUS EI LNO 01 OUTS 6 INS"" 6 (PO) ISAR OUTS p, (P 0,1,4.5) INS·P. (P 0,1,4.5) lISU 110 PORTS (4) 5VVOlTS LOGIC '0' ON 110 PINS SCRATCHPAO REGISTERS AUX DATA COUNTEA ... m14 00 CD 11 !l U12 .• LR LR I_ I + .. ... +(PO) "TI '["""i'j' ~ a ;;1 F(ls)::f4- (0) os· 011 ..... PROGRAM ROM ~ "TI (0) 011 r- ..... N HEX OCTAL * These instructions set status t H '000' EXTERNAL INTERRUPT INPUT C"'SV" LOGIC 1) RESET lransfers P09 to P and +t The value of the external Interrupt input is loaded to bit 7 of the accumulator (with bits 0 through 6 loaded with zeros) when the InstrucHon 'INS 6' Is executed. This Instruction also sels status. ST(OC) PO, P, DC, and Del are 12·blt registers. than cl ••rs PO, ICS bit of W, and ports 4, 5, 6, and 7. Nata: The instructions PI and PK are shown in two sequential parts (Pll. P12. and PK1. PK2). II F38721F38L72 Timing Characteristics The F3872 timing characteristics are described in Table 4 and illustrated in Figures 10 and 11. Table 4 Timing Characteristics Signal XTL 1 XTL2 '" WRITE 1/0 Symbol Characteristic Min Max Unit 250 1000 ns External Clock Pulse Width, High 90 700 ns External Clock Pulse Width, Low 100 700 ns to(EX) Time Base Period, All External Modes tEx(H) tEx(L) t", Internal", Clock Period 2t", tw Internal WRITE Clock Period 4t", 6t", tdllO Output Delay from Internal WRITE Clock tsllo Input Setup Time to WRITE Clock 1000 tllOS Output Valid to STROBE Delay 3~ tSl STROBE Low Time tRH RESET Hold Time, Low -1 00 STROBE RESET Btt -20 tEH EXT INT Hold Time, Inactive State C IN Input Capacitance: 1/0 Ports, RESET, EXT INT RAMPRT, TEST C XTl Input Capacitance: XTL" XTL 2 1000 50 pF Plus One TTL Load ns 3tt ns 12~ ns +20 +2 0 Note 1 ns 6t", + 750 ns To Trigger Interrupt 2t", ns To Trigger Timer; Note 2 7 pF Unmeasured Pins Returned to Vss; Note 3 29.5 pF Unmeasured Pins Returned to Vss; Note 3 23.5 1/0 load is 50 pF plus one standard TTL Input; STROBE load Is 50 pF plus three standard TTL inputs. Specification is applicable when the timer is in the interval timer mode. TA =25'C, f=2 MHz. TA = O'C to + 70'C, vee = + 5 V %10%, ilO power dissipations mW, unless otherwise noted. 4·90 ns 6t~ Note. ,. 2. 3. 4. 4 MHz-1 MHz Short Cycle Long Cycle + 70 EXT INT Hold Time, Active State EXTINT 0 Notes F38721F38L72 Fig. 10 Timing Diagrams EXTERNAL CLOCK INTERNAL (/I CLOCK :::J(===== C- 110 PORT OUTPUT __ --I__ s I---ISL-[ EXT INT { ICP B I T d = I E H = [ ICP BIT 2=1 Note All meaauremenla are referenced 10 VIL max, VIH min, VOL max, or VOH min Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Voltage on any Pin with Respect to Ground (Except Open·Drain Pins) Voltage on any Open·Drain Pin Power Dissipation Ambient Temperature Under Bias Storage Temperature -1.0V,+7V -1.0V, +13.2V 1.5W O·C, + 70 ·C - 55·C, + 150·C 4·91 F3872/F38L72 Fig. 11 Port Input/Output Timing Diagrams A. Input on Port 4 or 5 INTERNAL WRITE CLOCK IN OR INS OPCODE FETCHED PORT ADDR. PLACED ON DATA BUS PORT PINS PORT DATA DRIVEN ON TO DATA BUS NEXT OPCODE FETCHED ------' ·Cycle timing shown for 4 MHz external clock B. Output on Port 4 or 5 INTERNAL WRITE CLOCK OUT OR OUTS OPCODE FETCHED PORTADDR. ON DATA BUS ACCUMULATOR CONTENTS ON DATA BUS PORT PINS NEXT OPCODE FETCHED ___ -+-J~~--- STROBE (ACTIVE FOR PORT 4 ONLY) STAYS LOW FOR TWO WRITE CYCLES ·Cycle timing shown for 4 MHz external clock c. Input on Port 0 or 1 D. Output on Port 0 or 1 INTERNAL WRITE CLOCK INTERNAL WRITE CLOCK OUTSO,1 FETCHED PORT PINS ·Cycle timing shown for 4 MHz external clock ACCDATA ON BUS ----+-- ·Cycle timing shown for 4 MHz external clock 4-92 NEXT OPCODE FETCHED F3872/F38L72 DC Characteristics The dc characteristics of the F3872 are described in Table 5. Table 5 Symbol Icc DC Characteristics Characteristic Min Max Power Supply Current Unit Conditions 100 mA Outputs Open 500 mW Outputs Open 5.8 V Po Power Dissipation VIHEX External Clock Input High Voltage 2.4 VILHEX External Clock Input Low Voltage -0.3 0.6 V IHEX External Clock Input High Current 100 p.A VIHEX= Voo IILEX External Clock Input Low Current -100 p.A VILEX=VSS V IH Input High Voltage RESET, EXT INT 2.0 5.8 V V IL Input Low Voltage RESET, EXT INT -0.3 0.8 V RESET and EXT INT Have Internal Schmitt Triggers Giving Minimum 0.2 V Hysteresis VIHOO Input High Voltage (Open-Drain Ports) 13.2 V IlL Input Low Current RESET, EXT INT -1.6 mA V IL=O.4V Note 1 ILCO Leakage Current (Open-Drain Ports) 10 -5.0 p.A VIN= 13.2 V VIN=O.O V Note 2 10H Output High Current RESET, EXT INT -100 -30 p.A Vo H =2.4 V VOH=3.9 V - 0.1 mA Vo H =2.4 V 10HOO Output High Current (Direct-Drive Ports) mA Vo H = 1.5 V mA Vo H = 0.7 V 1.8 mA VoL =0.4 V Vo H =2.4 V 2.0 -1.5 -8.5 10L Output Low Current 10HS Output High Current (STROBE Output) -300 p.A 10LS Output Low Current (STROBE Output) 5.0 mA VIHRPR RAMPRT Input High Level 1.9 5.8 -0.3 3.2 VILRPR RAMPRT Input Low Level VSB Standby Voo for RAM ISB Standby Current ICHG Trickle Charge Available on VSB with Voo- 4.5 to 5.5 V POlO Power Dissipated by 110 Pins Vo L =0.4 V V Guaranteed 0.1 V less than V IH for RESET 0.4 V Guaranteed 0.1 V less than V IL for RESET 5.5 V 6.0 3.7 mA mA VSB= 5.5 V VSB= 3.2 V -15 mA mA VSB= 3.8 V VSB = 3.2 V 600 60 mW mW All Pins Any One Pin, Note 3 -0.8 Noles I. RESET or EXT INT programmed with standard pull·up. 2. RESET or EXT INT programmed without standard pull·up. 3. 4. Power dissipation of 1/0 pins is calculated by 1: (V DD - VILl (IIILI) + 1: (Voo - VoH )(lIoHI) + 1: (VOL) (loll· TA=O·Cto +70·C, VDD = +5V ±IO%,1I0 power dissipation "IOOmW. 4-93 F38721F38L72 Ordering Information Order Code Package Temperature Range" F3872DC, F38L72DC Ceramic C F3872DL, F38L72DL Ceramic L F3872DM, F38L72DM Ceramic M F3872PC, Plastic C F38L72PC 'c= Commercial Temperature Range O'C to + 70'C L= limited Temperature Range -40'C to + 85'C M = Military Temperature Range - 55'C to + 125'C 4·94 ! [!J I INTRODUCTION r;;l2 I ORDERING AND PACKAGE ~ INFORMATION !01F8 MICROCOMPUTER FAMILY !0ICONTROLLER FAMILY F6800 MICROPROCESSOR FAMILY !01F16000 MICROPROCESSOR FAMILY I~ I ROM PRODUCTS InIg I DEVELOPMENT SYSTEMS AND ~ SOFTWARE I~ I[!I] ! I APPLICATIONS I RESOURCE AND TRAINING CENTERSI ~ I SALES OFFICES Section 5 F6800 Microprocessor F=AIRCHILD A Schlumberger Company Family General The Fairchild F6800 microprocessor family is a set of 8-bit MOS devices that offers a complete and constantly growing selection of microprocessors having a powerful instruction set. As shown in figure 5-1, the F6800 family now includes seven different CPUs (described in table 5-1), supported by such circuits as synchronous and asynchronous controllers for data communications, timers, a direct memory access controller, CRT controllers, RAMs, ROMs, and EPROMs (described in table 5-2). Table 5-1 F6800 Microprocessor Family CPUS Device No. No_ of Power External Pins Supply Addressing F6800 F6801 F6802 F6803 F6808 F6809 F6882 40 40 40 .40 40 40 40 +5V +5V +5V +5V +5V +5V +5V 64K 64K 64K 64K 64K 64K 64K Data Length (Bits) Clock No. of Basic Instructions 8 8 8 8 8 8 8 No Yes Yes Yes Yes Yes Yes 82 72 82 72 59 72 No. of Bytes (RAM) - - 128 128 128 128 Bytes (ROM) 1/0 Lines - - 2K 31 - - - - 13 - - Other 1/0 Serial Serial Timer 16-Bit 16-Bit - - Table 5·2 F6800 Peripheral Devices Type Number Name Comment General-Purpose F6820· Twenty I/O Lines General-Purpose F6821 General-Purpose General-Purpose F6840 F68488 Peripheral Interface Adapter Peripheral Interface Adapter Programmable Timer Module General-Purpose Interface Adapter Special Function F6844 Three 1/0 Channels Special Function Special Function Special Function F6845 F6846 F6847 Direct Memory Access Controller CRT Controller ROM, I/O, Timer Video Display Generator Data Communications F6850 Data Communications F6852 Data Communications F6854 Data Communications F6856/ F3846 Data Communications Memory F38456 Asynchronous Communications Interface Adapter Synchronous Serial Data Adapter Advanced Data Link Controller Synchronous Communications Protocol Controller Multi·Protocol Communications Controller F681 0 128 x 8-Bit Static RAM F684561 .. Not recommended for new designs. 5-3 Twenty 1/0 Lines Three-to 16-Bit Timers IEEE-488 Bus Controller Available in Interlace or Non-Interlace 2K x 8 ROM, Parallel I/O, Timer Low-Cost Video Controller HDLC/SDLC HDLC/SDLC/BTSYNC HDLC/SDLC/BiSYNC/ASYNC • F6800 Microprocessor Family Figure 5·1 F6800 MICROPROCESSING UNIT F681 0 STATIC RAM F6621 PERIPHERAL INTERFACE ADAPTER F6840 PROGRAMMABLE TIMER F6844 DIRECT MEMORY ACCESS CONTROLLER F6845IF6B45A CRT CONTROLLER F6646 ROM·I/O·TIMER F6847 VIDEO DISPLAY GENERATOR F6650 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTOR F6852 SYNCHRONOUS SERIAL DATA ADAPTOR F6854 ADVANCED DATA LINK CONTROLLER F38461F6856 SYNCHRONOUS PROTOCOL COMMUNICATIONS CONTROLLER F364561F68456 MULTIPLE PROTOCOL COMMUNICATIONS CONTROLLER F68468 GENERAL PURPOSE INTERFACE ADAPTOR 5·4 F6800 Microprocessor Family Instruction Set Figure 5·3 F6801/F6803 Programming Model Because a single instruction set is inadequate for the number and flexibility of devices in the F6800 family, it has been necessary to develop three such sets, each serving a portion of the family. 7 0 0 15 I X 15 The basic instruction set, comprising 72 instructions, is supported by the F6800, F6802, F6808, and F6882; figure 5-2 is the associated programming model. An expanded in· struction set, consisting of the basic set plus several addi· tional instructions, is supported by the F6801 and F6803; figure 5-3 illustrates the associated programming model. The expanded instruction set is upward·compatible with the basic set (that is, programs written using either are inter· changeable, provided that the additional instructions are not involved). Both the basic and expanded instruction sets are described in table 5-3. 07 ...··.....l..·m.m~.m ..miiJ 115-.. ·m·~ I INDEX REGISTER (X) 0 I ~ 15 I I B·BIT ACCUMULATORS A AND B OR 16·BIT DOUBLE ACCUMULATOR D STACK POINTER (SP) 0 I PC o PROGRAM COUNTER (PC) CONDITION CODE REGISTER (CCRi CARRY/BORROW FROM MSB OVERFLOW ZERO '----NEGATiVE '------INTERRUPT ' - - - - - - HALF CARRY (from BII 3) I Figure 5·4 F6809 Programming Model The instruction set supported by the high·performance F6809 is similar in structure to the basic and expanded sets, but is not upward·compatible. It is greatly enhanced to take fullest advantage of the powerful F6809 architecture. Figure 5-4 illustrates the F6809 programming model and table 5-4 describes the instruction set. INDEX REGISTER (X) INDEX REGISTER (V) HARDWARE STACK (S) ::==::;::==~PC~==::;::==::: Figure 5·2 F6800/F6802lF6808/F6882 Programming Model 7 I 7 I ACCA 15 ACCUMULATOR A D 0 ACCB 15 I 15 I ! ! o I IX PROGRAM COUNTER -====A===~===B===~ACCUMULATORS 0 ACCUMULATOR B ! L-_ _..:D;:.P_ _....... DIRECT PAGE REGISTER INDEX REGISTER (X) o J PC PROGRAM COUNTER (PC) 1! o I SP CARRY/BORROW OVERFLOW '------ZERO '-----NEGATIVE '------INTERRUPT MASK STACK POINTER (SP) o 1 H I N Z V C CONDITION CODE REGISTER (CCR) CARRY (from BII 7) ' - - - - - - - H A L F CARRY OVERFLOW ZERO NEGATIVE INTERRUPT MASK HALF CARRY (from Bit 3) ' - - - - - - - F A S T INTERRUPT MASK ' - - - - - - - - - - E N T I R E STATE ON STACK 5-5 F6800 Microprocessor Family Table 5-3 Basic and Expanded Instruction Sets Instruction Description ABA *ABX ADC ADD *ADDD AND ASL *ASLD ASR Add Accumulators Add Accumulator B to Index Register Add With Carry Add Add Double Accumulator to Memory; Leave Sum In Double Accumulator Logical AND Arithmetic Shift Left Double Accumulator Shift Left; Clear LSB; Shift MSB into C-Bit Arithmetic Shift Right BCC BCS BEO BFE BGT BHI *BHS BIT BLE *BLO BLS BLT BMI BNE BPL BRA *BRN BSR BVC BVS Branch if Carry Clear Branch if Carry Set Branch if Equal To Zero Branch if Greater Than or Equal To Zero Branch if Greater Than Branch if Higher Than Branch if Higher Than or Same As Bit Test Branch if Less Than or Equal To Branch if Lower Than Branch if Lower Than or Same As Branch if Less Than Zero Branch if Minus Branch if Not Equal To Zero Branch if Plus Branch Always Branch Never Branch to Subroutine Branch if Overflow Clear Branch if Overflow Set CBA CLC CLi CLR CLV CMP COM CPX *CPX Compare Accumulators Clear CarrY Clear Interrupt Mask Clear Clear Overflow Compare Complement Compare Index Register Compare Index Register; Permits Use With Any Conditional Branch Instruction DAA DEC DES DEX Decimal Adjust Decrement Decrement Stack Pointer Decrement Index Register EOR Exclusive OR *F6801/F6803 Only 5-6 F6800 Microprocessor Family Table 5-3 Basic and Expanded Instruction Sets (Cont.) Instruction INC INS INX I Description Increment Increment Stack POinter Increment Index Register JMP JSR 'JSR Jump Jump to Subroutine Additional Addressing Mode Direct LOA 'LDD LOS LOX 'LSL 'LSLD LSR 'LSRD Load Accumulator Load Double Accumulator from Memory Load Stack Pointer Load Index Register Memory or Accumulator Shift Left; Clear LSB; Shift MSB into C·Bit Double Accumulator Shift Left; Clear LSB; Shift MSB into C·Bit Logical Shift Right Double Accumulator Shift Right; Clear MSB; Shift LSB into C·Bit 'MUL Multiply Accumulators; Leave Product in Double Accumulator NEG NOP Negate No Operation ORA Inclusive OR Accumulator PSH 'PSHX PUL 'PULX Push Data Push Index Register to Stack Pull Data Pull Index Register from Stack RJOL ROR RTI RTS Rotate Rotate Return Return SBA SBC SEC SEI SEV STA Subtract Accumulators Subtract With Carry Set Carry Set Interrupt Mask Set Overflow Store Accumulator Store Double Accumulator Store Stack Register Store Index Register Subtract Subtract Double Accumulator; Leave Difference in Double Accumulator Software Interrupt 'STD STS STX SUB 'SUBD SWI Left Right from Interrupt from Subroutine 'F6801/F6803 Only 5·7 • F6800 Microprocessor Family Table 5·3 Basic and Expanded Instruction Sets (Cont.) Instruction Description TAB TAP TBA TPA TST TSX TXS Transfer Accumulators Transfer Accumulators to Condition Code Register Transfer Accumulators Transfer Condition Code Register to Accumulator Test Transfer Stack Pointer to Index Register Transfer Index Register to Stack Pointer WAI Wait for Interrupt *F6801/F6805 Only Table 5·4 F6809 Instruction Set Instruction Description ABX ADCA,ADCB ADDA,ADDB ADDD ANDA, ANDB ANDCC ASL, ASLA ASLB ASR, ASRA, ASRB Add Accumulator B to Index Register Add Memory to Accumulator With Carry Add Memory to Accumulator Add Memory to Accumulator D AND Memory With Accumulator AND Condition Code Register Arithmetic Shift Left of Accumulator or Memory BCC, LBCC BCS,LBCS BEQ,LBEQ BGE, LBGE BGT, LBGT BHI, LBHI BHS, LBHS BITA, BITB BLE,LBLE BLO,LBLO BLS,LBLS BLT, LBLT BMI, LBMI BNE, LBNE BPL, LBPL BRA,LBRA BRN,LBRN BSR,LBSR BVC,LBVC BVS, LBVS Branch if Carry Clear Branch if Carry Set Branch if Equal To Branch if Greater Than or Equal To Branch if Greater Than Branch if Higher Branch if Higher Than or Same As Bit Test Memory With Accumulator Branch if Less Than or Equal To Branch if Lower Branch if Lower Than or Same As Branch if Less Than Branch if Minus Branch if Not Equal To Branch if Plus Branch Always Branch Never Branch to Subroutine Branch if Overflow Clear Branch if Overflow Set CLR, CLRA, CLRB CMPA CMPB Clear Accumulator or Memory Location Arithmetic Shift Right of Accumulator or Memory Compare Memory from Accumulator 5·8 F6800 Microprocessor Family Table 5·4 F6809 Instruction Set (Cont.) Instruction Description CMPD CMPS, CMPU CMPX, CMPY COM, COMA, COMB CWAI Compare Memory from Accumulator D Compare Memory from Stack Pointer Compare Memory from Index Register Complement Accumulator or Memory Location DAA DEC, DECA, DECB Decimal Adjust Accumulator A Decrement Accumulator or Memory Location EORA, EORB EXG D, R EXG R1, R2 ,Exclusive OR Memory With Accumulator Exchange D With X, Y, S, U, or PC Exchange R1 With R2 (R1, R2 = A,B, CC, DP) AND Condition Code Register, Wait for Interrupt INC, INCA, INCB Increment Accumulator or Memory Location JMP JSR Jump Jump to Subroutine LDA, LDB LDD LDS,LDU LDX,LDY LEAS,LEAU LEAX, LEAY LSL, LSLA, LSLB LSR, LSRA, LSRB Load Accumulator from Memory Load Accumulator D from Memory Load Stack Pointer from Memory Load Index Register from Memory Load Effective Address into Stack Pointer Load Effective Address into Index Register Logical Shift Left Accumulator or Memory Location MUL Unsigned Multiply NEG, NEGA, NEGB NOP Negate Accumulator or Memory ORA,ORB ORCC OR Memory With Accumulator OR Condition Code Register PSHS PSHU PULS PULU Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack Push a, B, CC, DP, D, X, Y, U, or PC onto user stack Pull A, B, CC, DP, D, X, Y, U, or PC fro hardware stack ·pull A, B, CC, DP, D, X, Y, U, or PC from user stack ROL, ROLA, ROLB ROR, RORA, RORB RTI RTS Rotate Accumulator or Memory Left Logical Shift Right Accumulator or Memory Location No Operation Rotate Accumulator or Memory Right Return from Interrupt Return from Subroutine 5·9 • F6800 Microprocessor Family Table 5-4 Instruction Set (Cont.) Instruction Description SBCA,SBCB SEX STA,STB STD STS, STU STX,STY SUBA,SUBB SUBD SWI SWI2, SWI3 SYNC Subtract Memory from Accumulator With Bo~row Sign Extend Accumulator B into Accumulator A Store Accumulator to Memory Store Accumulator D to Memory Store Stack Pointer to Memory Store Index Register to Memory Subtract Memory from Accumulator Subtract Memory from Accumulator D Software Interrupt TFR D, R TFR R, D TFR R1, R2 TST, TSTA, TSTB Transfer D to X, Y, S, U, or PC Transfer X, Y, S, U, or PC to D Transfer R1 to R2 Test Accumulator or Memory Location Synchronize With Interrupt Line Descriptions Following is data that describes the members of the F6800 microprocessor family. 5-10 F6800/F68AOO/F68BOO FAIRCHILD 8-Bit Microprocessing Unit A Schlumberger Company Microprocessor Product Description The F6800 is a monolithic 8-bit microprocessing unit (MPU) forming the central control function for the Fairchild F6800 family. Compatible with TTL, the F6800, as with all F6800 system parts, requires only one +5.0 V power supply and no external TTL devices for bus interface. Logic Symbol 33 32 31 30 29 28 27 26 The F6800 is capable of addressing 65K bytes of memory with its 16-bit address lines. The 8-bit data bus is bidirectional as well as 3-state, making direct memory addressing and multiprocessing applications realizable. • • • • • • • • • • • • • • • 37 AD A, .' .2 F6800 8-Bit Parallel Processing Bidirectional Data Bus 16-Bit Address Bus - 65K Bytes of Addressing 72 Instructions - Variable Length 7 Addressing Modes - Direct, Relative, Immediate, Indexed, Extended, Implied and Accumulator Variable Length Stack Vectored Restart Maskable Interrupt Vec;tor Separate Non-Maskable Interrupt - Internal Registers Saved in Stack 6 Internal Registers - 2 Accumulators, Index Register, Program Counter, Stack Pointer, and Condition Code Register Direct Memory Addressing (DMA) and Multiple Processor Capability Simplified Clocking Characteristics Clock Rates 1 MHz (F6800), 1.5 MHz (F68AOO), and 2 MHz (F68BOO) Simple Bus Interface Without TTL Halt and Single Instruction Execution Capability 36 DBE 39 TSC 40 RESET 34 Vec= Pin 8 Vss= Pins 1, 21 Connection Diagram 40-Pln DIP RESET TSC . N.C• Pin Names 00- 0 7 HALT <1>1, <1>2 IRQ NMI DBE TSC RESET VMA BA Ao-A15 R/W Vee Vss ' Bidirectional Data Bus Halt Input Clock Inputs Interrupt Request Input Non-Maskable Interrupt Input Data Bus Enable Input 3-State Control Input Reset Input Valid Memory Address Output Bus Available Output Address Bus Outputs Read I Write Output +5 V Power Supply Input Ground DBE N.C. RiW BA vee 0" D, D. D. D. 0, AS Aa (Top View) 5-11 10 A. n A3 12 A4 13 A. 14 Ao 15 A7 16 Aa 17 A. 18 A'D Al1 19 A'2 22 20 A'3 23 A'4 A15 24 25 • F6800/F68AOO/F68BOO Block Diagram CLOCK,., CLOCK,., RESET NON-MASKABLE INTERRUPT (iiiMi) HALT INTERRUPT REQUEST (IRQ) 3-STATE CONTROL (TSC) DATA BUS ENABLE (DBE) _ BUS AVAILABLE (BA) VALID MEMORY ADDRESS (VMA) READ/WRITE (R/W) MPU Signal Description Address Bus (Ao-A,S) Sixteen pins are used for the address bus. The outputs are 3-state bus drivers capable of driving one standard TTL load and 90 pF. When the output is turned off, it is essentially an open circuit. This permits the MPU to be used in DMA applications. Putting TSC in its HIGH state forces the address bus to go into the 3-state mode. Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine the state of the processor. Clocks Phase One and Phase Two (> 1,>2) Two pins are used for a 2-phase non-overlapping clock that runs at the Vcc voltage level. Data Bus (00-07) Eight pins are used for the data bus. It is bidirectional, transferring data to and from the memory and peripheral devices. It also has 3-state output buffers capable of driving one standard TTL load and 130 pF. The data bus is placed in the 3-state mode when DBE is LOW. Figure 27 shows the microprocessor clocks, and the Clock Timing table shows the static and dynamic clock specifications. The HIGH level is specified at VIHC and the LOW level is specified at VILC' The allowable clock frequency is specified by f (frequency). The minimum > 1 and >2 HIGH level pulse widths are specified by PW>H (pulse width HIGH time). To guarantee the required access time for the peripherals, the clock up time, t ut , is specified. Clock separation, td, is measured at a maximum voltage of Vov (overlap voltage). This allows for a multitude of clock variations at the system frequency rate. Data Bus Enable (DBE) This input is the 3-state control signal for the MPU data bus and will enable the bus drivers when in the HIGH state. This input is TTL-compatible; however, in normal operation it would be driven by the phase two clock. During an MPU read cycle, the data bus drivers will be disabled internally. When it is desired that another device control the data bus, such as 5-12 F6800/F68AOO/F68BOO Fig. 1 MPU Flow Chart WAI • CONDITION CODE REGISTER v v N v N Noles 1. Reset Is recognized at any position in the flowchart. 2. Instructions which affect the I·Bit act upon a one-bit buffer register, "ITMP". This has the effect of delaying any clearing of the I·Bit one clock time. Setting the I-Bit, however, Is not delayed. 3. Refer to tables 8 through 13 for details of instruction execution. 5·13 F6800/F68AOO/F68BOO in Direct Memory Access (DMA) applications, DBE should be held LOW. cycles are required for the processor to stabilize in preparation for restarting. During these eight cycles, VMA will be in an indeterminate state so any devices that are enabled by VMA which could accept a false write during this time (such as a battery-backed RAM) must be disabled until VMA is forced LOW after eight cycles. RESET can go HIGH asynchronously with the system clock any time after the eighth cycle. If additional data set-up or hold time is required on an MPU write, the DBE down time can be decreased as shown in Figure 29 (DBE "" q,2). The minimum down time for DBE is lOBE as shown and must occur within q, 1 up time. The minimum delay from the trailing edge of DBE to the trailing edge of q, 1 is tDBED' By skewing DBE with respect to E in this manner, data set· up or hold time can be increased. Reset timing is shown in Figure 2 and the Read/Write Timing tabl.e. The maximum rise. and fall transition times are specified by tpcr and tpCt. If RESET is HIGH at tpcs (processor control set·up time) as shown. in Figure 2 in any given cycle, then the restart sequence will begin on the next cycle as shown. The RESET control line may also be used to reinitialize the MPU system at any time during its operation. This is accomplished by pulsing RESET LOW for the duration of a minimum of three complete q,2 cycles. The Reset pulse can be completely asynchronous with the MPU system clock and will be recognized during q,2 if set-up time tpcs is met. Bus Available (BA) The Bus Available signal will normally be in the LOW state; when activated, it will go to the HIGH state, indicating that the microprocessor has stopped and that the address bus is available. This will occur if the HALT line is in the LOW state or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all 3·state output drivers will go to their OFF state and other outputs to their normally inactive level. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit I = "0") or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30 pF. If TSC is in the HIGH state, Bus Available will be LOW. Interrupt Request (IRQ) This level-sensitive input requests that an interrupt sequence be generated within the machine. The processor will wait until it completes the current instruction that is being executed before it recognizes the request. At that time, if the interrupt mask bit in the condition code register is not set, the machine will begin an interrupt sequence. The index register, program counter, accumulators, and condition code register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit HIGH so that further interrupts may occur. At the end of the cycle, a 16·bit address will be loaded that points to a vectoring address which is located in memory locations FFF8 and FFF9. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. Interrupt timing is shown in Figure 3. Read/Write (R/W) This TTL-compatible output signals the peripherals and memory devices whether the MPU is in a Read (HIGH) or Write (LOW) state. The normal standby state of this signal is Read (HIGH). 3-State Control (TSC) going HIGH will turn Read/Write to the OFF (high-impedance) state. Also, when the processor is halted, it will be in the OFF state. This output is capable of driving one standard TTL load and 90 pF. Reset (RESET) The RESET input is used to reset and start the MPU from a power·down condition resulting from a power failure or initial start-up of the processor. This input can also be used to reinitialize the machine at any time after start-up. The HALT line must be in the HIGH state for interrupts to be serviced. Interrupts will be latched internally while HALT is LOW. If a HIGH level is detected in this input, this will signal the MPU to begin the reset sequence. During the reset sequence, the contents of the last two locations (FFFE, FFFF) in memory will be loaded into the program counter to point to the beginning of the reset routine. During the reset routine, the interrupt mask bit is set and must be cleared under program control before the MPU can be interrupted by IRQ. While RESET is LOW (assuming a minimum of eight clock cycles have occurred) the MPU output signals will be in the following states: VMA = LOW, BA = LOW, data bus = high impedance, R/W = HIGH (read state), and the address bus will contain the reset address FFFE. Figure 2 illustrates a power·up sequence using the RESET. control line. After the power supply reaches 4.75 V a minimum of eight clock The IRQ has a high-impedance pullup device internal to the chip; however, a 3 kQ external resistor to Vcc should be used for wire·OR and optimum control of interrupts. Non-Maskable Interrupt (NMI) and Wait for Interrupt (WAI) The F6800 is capable of handling two types of interrupts: maskable (IRQ) as described earlier, and non-maskable (NMI). IRQ is maskable by the interrupt mask in the condition code register while NMI is not maskable. The handling of these interrupts by the MPU is the same except that each has its own vector address. The behavior of the MPU when interrupted is shown in Figure 3 which details the MPU response to an interrupt while the MPU is executing the 5·14 F6800/F68AOO/F68BOO Fig. 2 Reset Timing I CY#~LE I .2 ~~~:::: SUPPLY #2 I #3 I _J;.5_.2_5_V________ -..m4.75 v I #8 I #9 I I +1 n I n +2 I n +3 I n +4 I n +5 I m I m +1 I I I ~ ~:::~~~~~~~~~~~~~::::~~~~~~~:b~~~~~~~~~~~~~~~~~~~~::::~:~~~~~~~~~~~~~~ I --;ri.:.---IP-CS------~ IpcS -------------~s-------------~s-----l---' I--- Ipc, --l I - IpCt " ADDRESS BUS #7 J1.JL....J'4~ 55 55 =x::::x::::x:: &\\\\~\\\\\~\\\~\~~~\\\~~\\~\\\\\%'O FFFE FFFE FFFE J5~-------------------~~ ~O--DATA BUS ~\\\~~\\\\\\\\\~\\~\\\\~~\\~\\\\\~~~'i\~C-.I,"---',"---'.'---J'---J'--..J'I...."I;'Oc:::x::::x= PC 8·15 PC 0-7 ~~ BA ~\\\\\\\%\\\\\~\~~~~~~--------~JSS__--------------------------~Si~5----_____________ ~ Fig. 3 FIRST INSTRUCTION = INDETERMINATE Interrupt Timing I CY~LE I #2 I #3 I #4 I #5 I #6 I #7 I #8 I #9 I #10 I #11 I #12 I #13 I #14 I #15 I .2 .....--V_--_V--..,..Ir'--_V--"""',....--V--'"'"'\,....- ADDRESS ----"T'\,---V--"""\,....--V--""",....--V_--~ BUS SPIn - 1) SPIn - 2) SPIn - 3) SPIn - 4) SPIn - 5) SPIn - 6) SPIn - 7) FFF8 FFF9 NEW PC ADDRESS ADDRESS ADDRESS IRQ DR NMI INTERRUPT MASK INST (x) PC 0-7 PC 8-15 X 0-7 X 8-15 R/W VMA 5·15 ACCA ACCB CCR NEW PC 8-15 NEW PC 0-7 FIRST INST OF ADDRESS ADDRESS INTERRUPT ROUTINE • F6800/F68AOO/F68BOO control program. The interrupt shown could be either IRQ or NMI and can be asynchronous with respect to >2. The interrupt is shown going LOW at time tpcs in cycle # 1 which precedes the first cycle of an instruction (OP code fetch). This instruction is not executed, but instead, the program counter (PC), index register (IX), accumulators (ACCX), and the condition code register (CCR) are pushed onto the stack. will reach the high impedance state at tTSD (3-state delay), with VMA being forced LOW. In this example, the data bus is also in the high impedance state while >2 is being held LOW since DBE = >2. At this time, a DMA transfer could occur on cycles #3 and #4. When TSC is returned LOW, the MPU address and R IW lines return to the bus. Because it is too late in cycle #5 to access memory, this cycle is dead and used for synchronization. Program execution resumes in cycle #6. The Interrupt Mask bit is set to prevent further interrupts. The address of the interrupt service routine is then fetched from FFFC, FFFD for an NMI interrupt and from FFF8, FFF9 for an IRQ interrupt. Upon completion of the interrupt service routine, the execution of RTI will pull the PC, IX, ACCX, and CCR off of the stack; the Interrupt Mask bit is restored to its condition prior to Interrupts. Valid Memory Address (VMA) This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not 3-state. One standard TTL load and 90 pFmay be directly driven by this active HIGH signal. Figure 4 is a similar interrupt sequence, except in this case, a WAIT instruction has been executed in preparation for the interrupt. This technique speeds up the MPU's response to the interrupt because the stacking of the PC, IX, ACCX, and the CCR is already done. While the MPU is waiting for the interrupt, Bus Available will go HIGH indicating the following states of the control lines: VMA is LOW, and the address bus, R I Wand data bus are all in the high impedance state. After the interrupt occurs, it is serviced as previously described. Table 1 HALT When this level sensitive input is in the LOW state, all activity in the machine will be halted. The HALT line provides an input to the MPU to allow control of program execution by an outside source. If HALT is HIGH, the MPU will execute the instructions; if it is LOW, the MPU will go to a halted, or idle, mode. A response signal, Bus Available (BA) provides an indication of the current MPU status. When BA is LOW, the MPU is in the process of executing the control program; if BA is HIGH, the MPU has halted and all internal activity has stopped. Memory Map for Interrupt Vectors Vector MS LS Description FFFE FFFF Restart FFFC FFFD Non-maskable Interrupt FFFA FFFB Software Interrupt FFF8 FFF9 Interrupt Request When BA is HIGH, the address bus, data bus, and R I W line will be in a high impedance state, effectively removing the MPU from the system bus. VMA is forced LOW so that the floating system bus will not activate any device on the bus that is enabled by VMA. Refer to Figure 4 for program flow for Interrupts. While the MPU is halted, all program activity is stopped, and if either an NMI or IRQ interrupt occurs, it will be latched into the MPU and acted on as soon as the MPU is taken out of the halted mode. If a RESET command occurs while the LOW, MPU is halted, the following states occur: VMA BA = LOW, data bus = high impedance, R/W = HIGH (read state), and the address bus will contain address FFFE as long as RESET is LOW. As soon as the HALT line goes HIGH, the MPU will go to locations FFFE and FFFF for the address of the reset routine. 3-State Control (TSC) When the 3-State Control (TSC) line is a logic "1", the address bus and the R I W line are placed in a high impedance state. VMA and BA are forced LOW when TSC " 1" to prevent false reads or writes on any device enabled by VMA. It is necessary to delay program execution while TSC is held HIGH. This is done by insuring that no transitions of > 1 (or >2) occur during this period. (Logic levels of the clocks are irrelevant so long as they do not change.) Since the MPU is a dynamic device, the > 1 clock can be stopped for a maximum time PW>H without destroying data within the MPU. TSC then can be used in a short Direct Memory Access (DMA) application. = = Figure 6 shows the timing relationships involved when halting the MPU. The instruction illustrated is a 1-byte, 2-cycle instruction such as CLRA. When HALT goes LOW, the MPU will halt after completing execution of the current instruction. The transition of HALT must occur tpcs before the trailing edge of > 1 of the last cycle of an instruction (Point A of Figure 5 shows the effect of TSC on the MPU. TSC must have its transitions at tTSE (3-state enable) while holding > 1 HIGH and >2 LOW as shown. The address bus and R/W line 5-16 F6800/F68AOO/F68BOO Fig. 4 Wait Instruction Timing I CY#~LE I #2 I #3 I #4 I #7 I #8 I #9 I #10 I .2 JL.SU'"1...I""41""1-fL-I'"1-J4 I n+1 I n+2 I "+3 I n+4 I n+5 I ~r::J<:==:>c===~.,--~5~.,----~C:==)(====)[==:J<:==: ADDRESS BUS~'" INSTRUCTION SPIn) SPIn - 1) SPIn - 4) SPIn - 5) SPIn - 8) SPIn - 7) FFF8 FFF9 R/iN s VMA • INTERRUPT MASK IRQ OR NMI DATA BUS NEW PC 8·15 NEW PC 0·7 ADDRESS ADDRESS BA - - - - - - - - - ! § i 5 - ''_C_CA_A_CC_B_C_C_J--+t 0_ Note Midrange waveform indicates high·impedance state. 5-17 \'------ F6800/F68AOO/F68BOO Fig. 5 3-State Control Timing ., CYCLE #1 #2 #3 #. #5 #6 #8 #7 #9 SYSTEM MPU., IrsD trSD ADDRESS BUS RIW VMA DATA BUS <1>2 = DBE TSC ----I I--- ITSE Fig. 6 tTSE 1-- Halt and Single Instruction Execution for System Debug .' .2 I BA VMA 5S I- \\:..---_...11 ::x::::xr==\----~S~SI__---_1 FETCH EXECUTE < ADDRESS BUS ADDR M+1 DATA BUS INST INST X Note Midrange waveform indicates high impedance state. 5·18 X ) F6800/F68AOO/F68BOO Figure 6). HALT must not go LOW any time later than the minimum tpcs specified. arithmetic logic unit operation: negative (N), zero (Z), overflow (V), carry from bit 7 (C), and half carry from bit 3 (H). These bits of the condition code register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (I). The unused bits of the condition code register (bit 6 and bit 7) are ones. The fetch of the OP code by the MPU is the first cycle of the instruction. If HALT had not been LOW at Point A, but went LOW during >2 of that cycle, the MPU would have halted after completion of the following instruction. BA will go HIGH by time tSA (bus available delay time) after the last instruction cycle. At this time, VMA is LOW and R/Iii, address bus, and the data bus are in the high-impedance state. MPU Instruction Set The F6800 instructions are described in detail in the F6800 Programming Manual. This section will provide a brief introduction and discuss their use in developing F6800 control programs. The F6800 has a set of 72 different executable source instructions. Included are binary and decimal arithmetic, logical, shift, rotate, load, store, conditional or unconditional branch, interrupt and stack manipulation instructions. To debug programs it is advantageous to step through programs instruction by instruction. To do this, HALT must be brought HIGH for one MPU cycle and then returned LOW as shown at Point B of Figure 6. Again, the transitions of HALT must occur tpcs before the trailing edge of the next > 1, indicating that the Address Bus, Data Bus, VMA and R/Iii lines are back on the bus. A single-byte, 2-cycle instruction such as LSR is used for this example also. During the first cycle, the instruction Y is fetched from address M + 1. BA returns HIGH at tSA on the last cycle of the instruction indicating the MPU is off the bus. If instruction Y had been three cycles, the width of the BA LOW time would have been increased by one cycle. Each of the 72 executable instructions of the source language assembles into one to three bytes of machine code. The number of bytes depends on the particular instruction and on the addressing mode. (The addressing modes which are available for use with the various executive instructions are discussed later.) The coding of the first (or only) byte corresponding to an executable instruction is sufficient to identify the instruction and the addressing mode. The hexadecimal equivalents of the binary codes, which result from the translation of the 72 instructions in all valid modes of addressing, are shown in Table 2. There are 197 valid machine codes, 59 of the 256 possible codes being unassigned. MPU Registers The MPU has three 16-bit registers and three 8-bit registers available for use by the programmer (Figure n. Program Counter The program counter is a 2-byte (16 bits) register that points to the current program address. When an instruction translates into two or three bytes of code, the second byte, or the second and third bytes contain(s) an operand, an address, or information from which an address is obtained during execution. Stack Pointer The stack pointer is a 2-byte register that contains the address of the next available location in an external pushdown/pop-up stack. This stack is normally a random access read /write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be nonvolatile. Microprocessor instructions are often divided into three general classifications: (1) memory reference, so called because they operate on specific memory locations; (2) operating instructions that function without needing a memory reference; (3) I/O instructions for transferring data between the microprocessor and peripheral devices. Index Register The index register is a 2-byte register that is used to store data or a 16-bit memory address for the Indexed mode of memory addressing. In many instances, the F6800 performs the same operation on both its internal accumulators and the external memory locations. In addition, the F6800 interface adapters (PIA and ACIA) allow the MPU to treat peripheral devices exactly like other memory locations, hence, no I/O instructions as such are required. Because of these features, other classifications are more suitable for introducing the F6800's instruction set: (1) accumulator and memory operations; (2) program control operations; (3) condition code register operations. Accumulators The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit (ALU). Condition Code Register The condition code register indicates the results of an 5-19 F6800/F68AOO/F68BOO Fig. 7 Programming Model of The Microprocessing Unit ACCA ACCUMULATOR A Aces ACCUMULATOR B 15 IX INDEX REGISTER 15 PC PROGRAM COUNTER SP STACK POINTER 15 CONDITION CODE REGISTER CARRY (FROM BIT 7) OVERFLOW ZERO L-_ _ _ NEGATIVE ' - - - - - - INTERRUPT MASK ' - - - - - - - HALF CARRY (FROM BIT 3) Table 2 Microprocessor Instruction Set-Alphabetic Sequence ABA ADC ADD AND ASL ASR Add Accumulators Add with Carry Add Logical And Arithmetic Shift Left Arithmetic Shift Right BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS Branch if Carry Clear Branch if Carry Set Branch if Equal to Zero Branch if Greater or Equal Zero Branch if Greater than Zero Branch if Higher Bit Test Branch if Less or Equal Branch if Lower or Same Branch if Less than Zero Branch if Minus Branch if Not Equal to Zero Branch if Plus Branch Always Branch to Subroutine Branch if Overflow Clear Branch if Overflow Set CBA CLC CLI CLR Compare Accumulators Clear Carry Clear Interrupt Mask Clear CLV CMP COM CPX Clear Overflow Compare Complement Compare Index Register DAA DEC DES DEX Decimal Adjust Decrement Decrement Stack Pointer Decrement Index Register ROR RTI RTS Rotate Right Return from Interrupt Return from Subroutine Subtract Accumulators Subtract with Carry Set Carry Set Interrupt Mask Set Overflow Store Accumulator Store Stack Register Store Index Register Subtract Software Interrupt Transfer Accumulators Transfer Accumulators to Condition Code Reg. Transfer Accumulators Transfer Condition Code Reg. to Accumulator Test Transfer Stack Pointer to Index Register Transfer Index Register to Stack Pointer EOR Exclusive OR INC INS INX Increment Increment Stack Pointer Increment Index Register SBA SBC SEC SEI SEV STA STS STX SUB SWI JMP JSR Jump Jump to Subroutine TAB TAP LOA LOS LOX LSR Load Accumulator Load Stack Pointer Load Index Register Logical Shift Right TBA TPA NEG NOP Negate No Operation ORA Inclusive OR Accumulator TXS PSH PUL Push Data Pull Data WAI ROL Rotate Left 5·20 TST TSX Wait for Interrupt F6800/F68AOO/F68BOO Table 3 Hexadecimal Values of Machine Codes 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A Nap TAP TPA INX DEX CLV SEV CLC SEC Cli SEI" SBA CBA TAB TBA DAA ABA BRA REL BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE TSX INS PUL PUL DES TXS PSH PSH REL REL REL REL REL REL REl REL REL REL REL REL REL REL RTS A B A B 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 RTI 76 77 WAI SWI NEG A COM LSR A A ROR ASR ASL ROL DEC A A A A A INC TST A A CLR NEG A B COM LSR B B ROR ASR ASL ROL DEC B B B B B INC TST B B CLR NEG B IND COM LSR INO IND ROR ASR ASL ROL DEC IND IND IND IND IND INC TST JMP CLR NEG IND IND IND IND EXT COM LSR EXT EXT 72 73 74 75 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F AO A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF BO ROR ASR ASL ROL DEC EXT EXT EXT EXT EXT INC TST JMP CLR SUB CMP SBC EXT EXT EXT EXT A IMM A IMM A IMM AND BIT LDA A IMM A IMM A IMM EaR ADC ORA ADD CPX BSR LDS A A A A A SUB CMP SBC A DIR A DIR A DIR AND BIT LDA STA EOR ADC ORA ADD CPX A A A A A A A A LDS STS SUB CMP SBC OIR DIR A IND A IND A IND AND BIT LDA STA EOR ADC ORA ADD CPX JSR LDS STS SUB A A A A A A A A IMM IMM IMM IMM IMM REL IMM DIR DIR DIR DIR DIR DIR DIR DIR DIR IND IND IND IND IND IND IND IND IND IND IND IND A EXT B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF CO C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF DO D1 D2 D3 D4 D5 D6 D7 D8 09 DA DB DC DD DE DF EO E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB CMP SBC A EXT A EXT AND BIT LDA STA EOR ADC ORA ADD CPX JSR LDS STS SUB CMP SBC A A A A A A A A AND BIT LDA B IMM B IMM B IMM EOR ADC ORA ADD B B B B EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT B IMM B IMM B IMM EC ED EE EF FO F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF LDX STX SUB CMP SBC IND IND B EXT B EXT B EXT AND BIT LDA STA ADC ADC ORA ADD B B B B B B B B LDX STX IMM IMM IMM IMM LDX IMM SUB CMP SBC B DIR B DIR B DIR AND BIT LDA STA EOR ADC ORA ADD B B B B B B B B LDX STX SUB CMP SBC DIR DIR B IND B IND. B IND DIR DIR DIR DIR DIR DIR DIR DIR AND B IND BIT B IND LDA B IND STA " B IND EOR B IND ADC B IND ORA B IND ADD B IND Notes 1. Addressing Modes: A B 2. Unassigned code indicated by an asterisk (.) = Accumulator A = Accumulator B IMM DIR 5·21 = Immediate = Direct REL IND = Relative = Indexed EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT III F6800/F68AOO/F68BOO Table 4 Accumulator and Memory Operations The accumulator and memory operations and their effect on the CCR are shown in Table 4. Included are Arithmetic Logic, Data Test and Data Handling instructions. Addressing Modes Operations Add Direct Immed OP - ADDA 8B 2 ADDB CB 2 Index Condo Code Reg•• Boolean/Arithmetic Operation Extnd Implied (All register labels refer to contents 5 4 3 2 1 0 H I N Z V C I I I I I I I I I I I I I I I I I I I I I R I I R I I R I I R R S R R S R R R S R R I I I I I I I I I I I I I I R S I I R S I I R S 2 # OP - 2 9B 3 2 AB 5 2 BB 4 3 A + M-A I 2 DB 3 2 EB 5 2 FB 4 3 B + M-B I A + B-A I # OP - # OP - # OP 1B - 1 ABA Add with Carry ADCA 89 2 2 99 3 2 A9 5 2 B9 4 3 A + M+C-A I ADCB C9 2 2 09 3 2 E9 5 2 F9 4 3 B + M+C-B I ANDA 84 2 2 94 3 2 A4 5 2 B4 4 3 A. M - A AN DB C4 2 2 04 3 2 E4 5 2 F4 4 3 B. M - B Bit Test Clear Compare 2 # Add Acmltrs And I Mnemonic BITA 85 2 2 95 3 2 AS 5 2 B5 4 3 A.M BITB C5 2 2 05 3 2 E5 5 2 F5 4 3 B.M 6F 7 2 7F 6 3 00 - M CLR CLRA 4F 2 1 00 - A CLRB 5F 2 1 00 - B CMPA 81 2 2 91 3 2 AI 5 2 Bl 4 3 A-M CMPB Cl 2 2 01 3 2 El 5 2 Fl 4 3 B-M Compare Acmltrs CBA Complement, 1s COM 11 63 7 2 73 6 2 1 A-B M-M 3 COMA 43 2 1 A-A COMB 53 2 1 B-B 7 2 70 6 OO-M-M NEG NEGA 40 2 1 OO-A-A NEGB 50 2 1 OO-B-B DAA 19 2 1 Decimal Adjust, A 60 3 Complement, 2s (Negate) ,Converts Binary Add. of BCD Characters into BCD Format Decrement 6A DEC 7 2 7A 6 DECB Exclusive OR EORA 88 2 2 98 3 2 EORB C8 2 2 08 3 2 Increment INC A8 B8 5 2 E8 5 2 F8 6C 7 2 7C M -1 - M 3 DECA 4A 2 1 SA 2 1 A-I - A B-1 - B 3 A + M-A 4 3 B + M-B 6 3 M + 1- M 4 INCA 4C 2 1 A + 1- A INCB 5C 2 1 B + 1- B Load Acmltr LDAA 86 2 LDAB C6 2 Or, Inclusive ORAA 8A 2 ORAB CA 2 M-A 96 3 2- A6 5 2 B6 4 3 2 06 3 2 E6 5 2 F6 4 3 M-B 2 9A 3 2 AA 5 2 BA 4 3 A+M-A 2 DA 3 2 EA 5 2 FA 4 3 B+M-B 2 A - Msp, SP - 1 - SP Push Data PSHA 36 4 1 PSHB 37 4 1 B - Msp, SP - 1 - SP Pull Data PULA 32 4 1 SP + 1 - SP, Msp - A PULB 33 4 1 SP + 1 - SP, Msp - B 5·22 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • R I I 1 I I 1 2 I I 1 2 I I I 3 I I 4 I I 4 I I 4 I I R I I R I I 5 I I 5 I I 5 I I R I I R I I R I I R • • • • • • • • • • • • • • • • • • • • • • • • • • • • F6800/F68AOO/F68BOO Table 4 Accumulator and Memory Operations (Cont.) Addressing Modes Operations Mnemonic Immed Index Direct Implied op - # op - # op - # op - # op Rotate Left Rotate Right ROL 69 7 2 79 6 (All register labels - # refer to contents M 3 ROLA 49 2 1 A ROLB 59 2 1 B ROR 66 7 2 76 6 M 3 RORA 46 2 1 A RORB 56 2 1 B M Shift Left, ASL Arithmetic ASLA 48 2 1 A ASLB 58 2 1 B 68 7 2 78 6 3 M }CD-II - I I I I I IIJ b7 bO C }LO-" C - } 0 - 1 1 I I I I I I 1-0 C b7 bO }D, - ASR Arithmetic ASRA 47 2 1 A ASRB 57 2 1 B A }O-I ! I I b7 B 7 2 77 6 3 LSR Logic LSRA 44 2 1 LSRB 54 2 1 Store Acmltr Subtract Subtract Acmltrs Subtr. with Carry 64 7 2 74 6 b7 3 STAA 97 4 2 A7 6 2 B7 5 3 A-M STAB D7 4 2 E7 6 2 F7 5 3 B-M SUBA 60 2 2 90 3 2 AO 5 2 80 4 3 A- M - A SUBB CO 2 2 DO 3 2 EO 5 2 FO 4 3 B- M - B SBA ! ! ! I ! ! 1-0 M Shift Right, 10 2 1 SBCA 82 2 2 92 3 2 A2 5 2 B2 4 3 A-M-C-A C2 2 2 D2 3 2 E2 5 2 F2 4 3 B-M-C-B 16 2 1 A-B 17 2 1 B-A Transfer Acmltrs TAB Test, Zero TST or Minus TSTA 4D 2 1 A - 00 TSTB 5D 2 1 B - 00 6D 7 2 7D 6 M - 00 3 bO C 5 4 3 2 1 0 H I N Z V C • • • • • • • • • • • • • • • • • • • • • - A- B - A SBCB TBA I I I I I IJ bO b7 Shift Right, 67 Condo Code Reg •• Boolean/Arithmetic Operation Extnd ! I ! I !-D bO C • • • • • • • • • • • • • • • • • • • • • • • • • H Note Accumulator addressing mode instructions are included in the column for IMPLIED addressing ·See condition code register notes page 26 Legend; OP Operation Code (Hexadecimal); Number of MPU Cycles; # Number of Program Bytes; + Arithmetic Plus; Arithmetic Minus; Msp Contents of memory location + pOinted to be Stack Pointer; Boolean Inclusive OR; Boolean AND; <±> Boolean Exclusive OR; M Complement of M; Transfer Into; O B i t = Zero; 00 Byte = Zero; Condition Code Symbols; H Half-carry from bit 3; Interrupt mask N Negative (sign bit) Z Zero (byte) Overflow, 2'5 complement V Carry from bit 7 C R Reset Always S Set Always Test and set jf true, cleared otherwise Not Affected 5·23 • • • • • • • • I I I 6 I I I 6 I I I 6 I I 1 6 1 1 1 6 1 I 1 6 1 I 1 6 1 1 1 6 1 1 1 6 1 1 1 6 1 1 1 6 1 1 1 6 1 R 1 6 1 R 1 6 1 R 1 6 1 1 1 R I 1 R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R 1 1 R • • 1 1 R R 1 1 R R 1 1 R R N Z V C • • 1 • F6800/F68AOO/F68BOO register. This causes the next byte to be pulled from the stack to come from the location indicated by the index register. The utility of these two instructions can be clarified by describing the stack concept relative to the F6800 system. Program Control Operations Program Control operation can be subdivided into two categories: (1) index register / stack pointer instructions; (2) jump and branch operations. The stack can be thought of as a sequential list of data stored in the MPU's read/write memory. The stack pOinter contains a l6-bit memory address that is used to access the list from one end on a last-in-first-out (LIFO) basis in contrast to the random access mode used by the MPU's other addressing modes. Index Register/Stack Pointer Operations The instructions for direct operation on the MPU's index register and stack pointer are summarized in Table 5. Decrement (DEX, DES), increment (INX, INS), load (LOX, LOS), and store (STX, STS) instructions are provided for both. The compare instruction, CPX, can be used to compare the index register to a l6-bit value and update the condition code register accordingly. The F6800 instruction set and interrupt structure aHow extensive use of the stack concept for efficient handling of data movement, subroutines and interrupts. The instructions can be used to establish one or more stacks anywhere in read/write memory. Stack length is limited only by the amount of memory that is made available. The TSX instruction causes the index register to be loaded with the address of the last data byte put onto the stack. The TXS instruction loads the stack pointer with a value equal to one less than the current contents of the index Table 5 Index Register and Stack Pointer Instructions Pointer Operations Immed Mnemonic Direct Index Extend Condo Code Reg.· Implied OP - # OP - # OP - # OP - # BC 3 3 9C 4 2 AC 6 2 BC 5 3 OP - Boolean/Arithmetic Operation # XH - M, XL - (M + 1) 5 4 3 2 1 0 H I N Z V C • • CD Compare Index Reg CPX Decrement Index Reg DEX 09 4 1 X-I - X Decrement Stack Pntr DES 34 4 1 SP - 1 - SP Increment Index Reg INX DB 4 1 X + 1- X Increment Stack Pntr INS 31 4 1 SP + 1 - SP Load Index Reg LDX CE 3 3 DE 4 2 EE 6 2 FE 5 3 M - XH, (M + 1) - XL • •® Load Stack Pntr LDS BE 3 3 9E 4 2 AE 6 2 BE 5 3 M - SPH, (M + 1) - SPL Store Index Reg STX DF 5 2 EF 7 2 FF 6 3 XH - M, XL - (M + 1) Store Stack Pntr STS 9F 5 2 AF 7 2 BF 6 3 SPH - M, SPL - (M + 1) Indx Reg Stack Pntr TXS 35 4 1 X - I - SP Stack Pmr Indx Reg TSX 30 4 1 SP + 1 - X • • • • • *See condition code register notes page 26 5-24 • • • • • • t ® • • • • • • • • I • • • • • • • • • • ® ® ® • • I • • • • • R • t R • t R • t • • • • • • t R F6800/F68AOO/F68BOO is pushed onto the stack. For both of these instructions, the return address is the memory location following the bytes of code that correspond to the BSR and JSR instruction. The code required for BSR or JSR may be either two or three bytes, depending on whether the JSR is in the indexed (two bytes) or the extended (three bytes) addressing mode. Before it is stacked, the program counter is automatically incremented the correct number of times to be pointing at the location of the next instruction. The return from subroutine instruction, RlS, causes the return address to be retrieved and loaded into the program counter as shown in Figure 14. Operation of the stack pointer with the push and pull instructions is illustrated in Figures 8 and 9. The push instruction (PSHA) causes the contents of the indicated accumulator (A in this example) to be stored in memory at the location indicated by the stack pointer. The stack pointer is automatically decremented by one following the storage operation and is "pointing" to the next empty stack location. The pull instruction (PULA or PULB) causes the last byte stacked to be loaded into the appropriate accumulator. The stack pointer is automatically incremented by one just prior to the data transfer so that it will point to the last byte stacked rather than the next empty location. Note that the pull instruction does not remove the data from memory; in the example, 1A is still in location (m + 1) following execution of PULA. A subsequent push instruction would overwrite that location with the new pushed data. There are several operations that cause the status of the MPU to be saved on the stack. The software interrupt (SWI) and wait for interrupt (WAI) instructions as well as the maskable (IRQ) and non-maskable (NMI) hardware interrupts • all cause the MPU's internal registers (except for the stack pointer itself) to be stacked as shown in Figure 16. MPU status is restored by the return from interrupt, RTI, as shown in Figure 15. Execution of the branch to subroutine (BSR) and jump to subroutine (JSR) instructions cause a return address to be saved on the stack as shown in Figures 11 through 13. The stack is decremented after each byte of the return address Fig. 8 Stack Operation, Push Instruction MPU MPU ACCA 0 - r-- .... m- 2 m -1 SP m - 2 I e e c NEW DATA m l- m+1 7F +2 DATA m + 3 63 m PREVIOUSLY STACKED r+ m DATA m FD - 0 SP---..m -1 :> ----..m PREVIOUSLY STACKED ACCA F3 7F 1 +2 +3 63 FD 3C 3C_ PSHA PC ___ NEXT INSTR (b) AFTER PSHA (a) BEFORE PSHA 5·25 F6800/F68AOO/F68BOO Fig. g Stack Operation, Pull Instruction MPU ACCA m - 2 MPU B- CEJ ACCA -- m-21-_ _ _-4 m-l m-l m SP~m sp- lA PREvrOUSLvlm + 1 STACKED m + 2 DATA m + 3 1A PREVIOUSLY m + 2 3C STACKED .-_~__~ DATA m + 3 1 - _... 0... 5 __ 3C - I m+1 -4 05 Ec;..,. EC PC PULA PC--.. NEXT INSTR - -(a) BEFORE PULA Fig. 10 (b) AFTER PULA Program Flow for Jump and Branch Instructions ~ MAIN PROGRAM n n INDXD n MAIN PROGRAM I MAIN PROGRAM I 7E-JMP + lIKH=NEXT ADDRESSI + 2 IKL =NEXT ADDRESSI K I i NEXT INSTRUCTION n+ 1 1-_.;...,.;.;....;.;....... I (n + 2) ±K (a) JUMP Fig. 11 Program Flow for BSR m-2~ ~ SP---+- m - 2 m-l SP-+- m m +1 - 7E PC~n n +1 - BSR m (n +2)L n +1 -+K 7E BSR = OFFSET - - n+2 NEXT MAIN INSTR ....- (n +2)H - +K ': OFFSET· - m -1 m+l 7A 1-_ _;.....;.;......... -K = SIGNED 7·BIT VALUE (b) BRANCH .+2 NEXT MAIN INST - oK = SIGNED 7-BIT VALUE PC'" (n + 2) ±K 1ST SUBR INSTR (a) BEFORE EXECUTION (b) AFTER EXECUTION 5·26 F6800/F68AOO/F68BOO Fig. 12 Program Flow for JSR (Extended) m -2 - - m-1 m-3 SP~m-2 SP---.m m -1 m+1 7E m m+2 7A m+1 m +2 PC--"'n --- - - 70_ - (n+ 3)H (n + ')l 7E 7A - 7~ n+1 n +2 n +3 SL +1 +2 n +3 = SUBRAOOR NEXT MAIN INSTR n SH = SUBRADOR n SL (a) BEFORE EXECUTION PC_ S (SFORMEOFROM SHANOSL) = SUBRADOR NEXT MAIN INSTR - - 1ST SUBR INSTR t---:::::::::j _ (b) AFTER EXECUTION Fig. 13 Program Flow for JSR (Indexed) m_2~ SP-:~~ SP~m-2 7E m-1 (n +2)H m (n +2)l +1 7E m 7A 7A ,.--JSR ~ AD n +1 K - OFfSET- n +1 K = OFFSET n +2 NEXT MAIN INSTR n +2 NEXT MAIN INSTR 'K ~ a·BIT UNSIGNED VALUE pc- X· +K 1ST SUBR INSTR (a) BEFORE EXECUTION 'CONTENTS OF INDEX REGISTER (b) AFTER EXECUTION 5·27 F6800/F68AOO/F68BOO Fig. 14 Program Flow for RTS - rSP~m-2 m -1 m - 2 (n +3)H m -1 (n + 3)l SP~m 7E m+1 m +1 - --............ ~ ~ - 7A JSR = BD JSR "" BO +1 SH n+2 SL n n. +3 = SUBR ADDR = SUBR ADDR +1 SH - SUBR ADDR n+2 SL - SUBR ADDR .n NEXT MAIN INSTR PC~n+3 - ..... - 10' I Sn I (a) BEFORE EXECUTION Fig. 15 Program Flow for RTI - J m -7 m - 6 CCR m-6 CCR m - 5 ACCB m-S ACCB m - 4 ACCA m - 4 ACCA m - 3 XH (INDEX REG) m - 3 XH m - 2 XL (INDEX REG) m - 2 XL + l)H m-1 PCH PC(n + l)L SP-..m m -1 m PC(n - - - 7E n+1 Sn PC----.... I RTS (b) AFTER EXECUTION -..... SP--.m-7 -- LAST SUBR INSTR LAST SUBR INSTR RTS NEXT MAIN INSTR PCL 7E _ PC~n+1 - LAST INTER INSTR LAST INTER INSTR RTI Sn (a) BEFORE EXECUTION RTI - - (b) AFTER EXECUTION 5-28 F6800/F68AOO/F68BOO Fig. 16 Program Flow for Interrupts WAIT FOR INTERRUPT MAIN PROGRAM SOFTWARE INTERRUPT MAIN PROGRAM n HARDWARE INTERRUPT OR NON-MASKABLE INTERRUPT (NMI) MAIN PROGRAM + , L..-_ _--I r=> m-6 CONDITION CODe m- 5 ACMLTR B m-4 ACMLTR A m- 3 INDEX REGISTER (XH) m-2 INDEX REGISTER (XLl m-' PC(n + 1)H peen SWI • SP--"m -7 + 1)L HOWR INT WAI NO HDWR INT REO NMI NMI WAIT LOOP FFFA FFFC FFFD FFF8 FFF9 FFFB INTERRUPT MEMORY ASSIGNMENT1 FFF8 CONSTANT, HDWARE MS FFF9 CONSTANT, HDWARE LS FFFA SOFTWARE MS FFFB SOFTWARE LS FFFC NON·MASKABLE tNT MS FFFD NON-MASKAB,LE tNT LS c) FIRST INSTR AOOR FORMeD BY FETCHING 2 BYTES FROM PER MEM ASSIGN INTERRUPT PROGRAM I FFFE RESTART MS FFFF RESTART LS Note MS = Most Significant Address Byte LS = Least Significant Address Byte 5·29 1ST INTERRUPT INSTR FFFE FFFF F6800/F68AOO/F68BOO Jump and Branch Operation The jump and branch instructions are summarized in Table 6. These instructions are used to control the transfer of operation from one point to another in the control program. Execution of the jump instruction, JMP, and branch always, BRA, affects program flow as shown in Figure 10. When the MPU encounters the jump (indexed) instruction, it adds the offset to the value in the index register and uses the result as the address of the next instruction to be executed. In the extended addressing mode, the address of the next instruction to be executed is fetched from the two locations immediately following the JMP instruction. The branch always (BRA) instruction is similar to the JMP (extended) instruction except that the relative addressing mode applies and the branch is limited to the range within -125 or +127 bytes of the branch instruction itself. The opcode for the BRA instruction requires one less byte than JMP (extended) but takes one more cycle to execute. The no operation instruction, NOP, while included here, is a jump operation in a very limited sense. Its only effect is to increment the program counter by one. It is useful during program development as a stand-in for some other instruction that is to be determined during debug. It is also used for equalizing the execution time through alternate paths in a control program. Table 6 Jump and Branch Instructions Relative Operations Mnemonic OP - # Index OP - Extend # OP - Condo Code Reg. Implied # OP - Branch Test # Branch Always BRA 20 4 2 None Branch if Carry Clear BCC 24 4 2 C = 0 Branch if Carry Set BCS 25 4 2 C = 1 Branch if = Zero BEQ 27 4 2 Z = 1 Branch if '" Zero BGE 2C 4 2 Branch if > Zero BGT 2E 4 2 Branch if Higher BHI 22 4 2 N + V = 0 Z + (N + V) = 0 C+Z=O Branch if Z + (N Zero BlE 2F 4 2 Branch if lower or Same BlS 23 4 2 + C+Z=l Branch if < Zero BlT 2D 4 2 N Branch if Minus BMI 2B 4 2 + V = 1 N = 1 Branch if not Equal Zero BNE 26 4 2 Z = 0 Branch if Overflow Clear BVC 28 4 2 V = 0 Branch if Overflow Set BVS 29 4 2 V = 1 Branch if Plus BPl 2A 4 2 N = 0 Branch to Subroutine BSR 8D 8 2 Jump JMP 6E 4 2 7E 3 3 Jump to Subroutine JSR AD 8 2 BD 9 3 No Operation NOP 01 2 1 Return from Interrupt RTI 3B 10 1 :5 } See SpeCial Operations Return from Subroutine RTS 39 5 1 Software Interrupt SWI 3F 12 1 Wait for Interrupt" WAI 3E 1 *WAI puts address bus, R/W, and data bus in the 3-8tate mode while VMA is held LOW. tSee condition code register notes page 26. 5-30 V) =1 9 Advances Prog. Cntr. Only t 5 4 3 2 1 0 H I N Z V C • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1·\· • •r • ·I(·r --@-- } See Special Operations • @ •••• F6800/F68AOO/F68BOO The effect on program flow for the jump to subroutine (JSR) and branch to subroutine (BSR) is shown in Figures 11 through 13. Note that the program counter is properly incremented to be pointing at the correct return address before it is stacked. Operation of the branch to subroutine and jump to subroutine (extended) instruction is similar except for the range. The BSR instruction requires less opcode than JSR (2 bytes versus 3 bytes) and also executes one cycle faster than JSR. The return from subroutine, RTS, is used at the end of a subroutine to return to the main program as indicated in Figure 14. was negative or positive, respectively. 2. Branch on equal (BEQ) and branch on not equal (BNE) are used to test the zero status bit, Z, to determine whether or not the result of the previous operation was equal to zero. These two instructions are useful following a compare (CMP) instruction to test for equality between an accumulator and the operand. They are also used following the bit test (BIT) to determine whether or not the same bit positions are set in an accumulator and the operand. 3. Branch on overflow clear (BVC) and branch on overflow set (BVS) tests the state of the V bit to determine if the previous operation caused an arithmetic overflow. 4. Branch on carry clear (BCC) and branch on carry set (BCS) tests the state of the C bit to determine if the previous operation caused a carry to occur. BCC and BCS are useful for testing relative magnitude when the values being tested are regarded as unsigned binary numbers, that is, the values are in the range 00 (lowest) to FF (highest). BCC following a comparison (CMP) will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the value of the operand. Conversely, BCS will cause a branch if the accumulator value is lower than the operand. The effect of executing the software interrupt, SWI, and the wait for interrupt, WAI, and their relationship to the hardware interrupts is shown in Figure 15. SWI causes the MPU contents to be stacked and then fetches the starting address of the interrupt routine from the memory locations that respond to the addresses FFFA and FFFB. Note that as in the case of the subroutine instructions, the program counter is incremented to point at the correct return address before being stacked. The return from interrupt instruction, RTI, (Figure 15) is used at the end of an interrupt routine to restore control to the main program. The SWI instruction is useful for inserting break points in the control program, that is, it can be used to stop operation and put the MPU registers in memory where they can be examined. The WAI instruction is used to decrease the time required to service a hardware interrupt; it stacks the MPU contents and then waits for the interrupt to occur, effectively removing the stacking time from a hardware interrupt sequence. Fig. 17 The fifth complementary pair, branch on higher (BHI) and branch on lower or same (BLS) are in a sense complements to BCC and BCS. BHI tests for both C and Z = 0; if used following a CMP, it will cause a branch if the value in the accumulator is higher than the operand. Conversely, BLS will cause a branch if the unsigned binary value in the accumulator is lower than.or the same as the operand. Conditional Branch Instructions Z= 1 . BMI: N= 1 ; BPL: N = "'; BEQ: BNE: Z = "'; BVC: BVS: V = "'; V= 1 ; BCC: BCS: C = "'; C=1 ; BHI: C + Z = '" ; BLS: C + Z = 1 ; BLE: Z + BGT: Z + BL T: BGE: (N (±) (N (±) The remaining two pairs are useful in testing results of operations in which the values are regarded as signed two's complement numbers. This differs from the unsigned binary case in the following sense: In unsigned, the orientation is higher or lower; in signed two's complement, the comparison is between larger or smaller where the range of values is between -128 and +127. N (±) V = 1 ; N (±) V = '" ; V) = 1 ; V) = '" ; Branch on less than zero (BL T) and branch on greater than .or equal zero (BGE) test the status bits for N EB V = "1" and N EB V = "0", respectively. BL T will always cause a branch following an operation in which two negative numbers were added. In addition, it will cause a branch following a CMP in which the value in the accumulator was negative and the operand was positive. BL T will never cause a branch following a CMP in which the accumulator value was positive and the operand negative. BGE, the complement to BL T, will cause a branch following operations in which two positive values were added or in which the result was zero. The conditional branch instructions, Figure 17, consist of seven pairs of complementary instructions. They are used to test the results of the preceding operation and either continue with the next instruction in sequence (test fails), or cause a branch to another point in the program (test succeeds). Four of the pairs are used for simple tests of status bits N, Z, V, and C: 1. Branch on minus (BMI) and branch on plus (BPL) tests the sign bit, N, to determine if the previous result The last pair, branch on less than or equal zero (BLE) and 5-31 • F6800/F68AOO/F68BOO branch on greater than zero (BGT) test the status bits for Z 0:1 (N + V) "1" and Z 0:1 (N + V) "0", respectively. The action of BlE is identical to that for Bl T except that a branch will also occur if the result of the previous result was zero. Conversely, BGT is similar to BGE except that no branch will occur following a zero result. = the MPU that is useful in controlling program flow during system operation. The bits are defined in Figure 18. = The instructions shown in Table 7 are available to the user for direct manipulation of the CCR. In addition, the MPU automatically sets or clears the appropriate status bits as many of the other instructions on the condition code register were indicated as they were introduced. Condition Code Register Operations The condition code register (CCR) is a 6-bit register within Table 7 Condition Code Register Instructions Condo Code Reg.· Operations Implied Mnemonic Clear Carry Clear Interrupt Mask Clear Overflow Set Carry Set Interrupt Mask Set Overflow Acmltr A - CCR CCR - Acmltr A ClC CLI ClV SEC SEI SEV TAP TPA Boolean Operation OP - # OC OE OA 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 00 OF OB 06 07 O-C 0-1 O-V 1 - C 1 - I 1 - V A - CCR CCR - A R = Reset 5= Set Not affected 1 (ALL) Set according to the contents of Accumulator A. ·See Condition Code Register notes below 5 4 3 2 1 0 H I N Z V C • •R • • •• R • • • • •• •• •• •• •R •S • S • • •S •• • • •@ • •I• I• I• I•I• .= Condition Code Register Notes: (Bit set if test is true and cleared otherwise) 8 (Bit V) Test: 2s complement overflow from subtraction of 1 (Bit V) Test: Result = 10000000? 2 (Bit C) Test: Result MS bytes? = OOOOOOOO? 9 (Bit N) Test: Result less than "O"? (Bit 15 = 1) 3 (Bit C) Test: Decimal value of most significant BCD character greater than nine? (Not cleared if previously set.) 4 (Bit V) Test: Operand = 10000000 prior to execution? 10 (All) load condition code register from stack. (See Special Operations) 11 (Bit I) Set when interrupt occurs. If previously set, a non-maskable interrupt is required to exit the wait state. 12 (All) Set according to the contents of accumulator A. 5 (Bit V) Test: Operand = 01111111 prior to execution? 6 (Bit V) Test: Set equal to result of N has occurred. <±> C after shift 7 (Bit N) Test: Sign bit of most significant (MS) byte = I? 5-32 F6800/F68AOO/F68BOO Fig. 18 H H = Condition Code Register Bit Definition N Z v Selection of the desired addressing mode is made by the user as the source statements are written. Translation into appropriate opcode then depends on the method used. If manual translation is used, the addressing mode is inherent in the opcode. For example, the immediate, direct, indexed, and extended modes may all be used with the ADD instruction. The proper mode is determined by selecting (hexadecimal notation) 8B, 9B, AB, or BB, respectively. C Half-carry; set whenever a carry from b 3 to b 4 of the result is generated by ADD, ABA, ADC; cleared if no b 3 to b4 carry; not affected by other instructions. The source statement format includes adequate information for the selection if an assembler program is used to gen· erate the opcode. For instance, the immediate mode is selected by the assembler whenever it encounters the "#" symbol in the operand field. Similarly, an "X" in the operand field causes the indexed mode to be selected. Only the relative mode applies to the branch instructions; therefore, the mnemonic instruction itself is enough for the assembler to determine addressing mode. Interrupt Mask; set by hardware or software interrupt or SEI instruction; cleared by CLI instruction. (Normally not used in arithmetic operations.) Restored to a zero as a result of an RTI instruction if 1m stored on the stack is LOW. N Negative; set if high order bit (b 7 ) of result is set; cleared otherwise Z Zero; set if result V Overlow; set if there were arithmetic overflow as a result of the operation; cleared otherwise. C Carry; set if there were a carry from the most significant bit (b 7 ) of the result; cleared otherwise. = 0; cleared otherwise. For the instructions that use both direct and extended modes, the assembler selects the direct mode if the operand value is in the range 0-255 and extended otherwise. There are a number of instructions for which the extended mode is valid but the direct is not. For these instructions, the assembler automatically selects the extended mode even if the operand is in the 0-255 range. The addressing modes are summarized in Figure 19. A CLI-WAI instruction sequence operated properly with early F6800 processors only if the preceding instruction were odd. (Least Significant Bit = "1".) Similarly it was advisable to precede any SEI instruction with an odd opcode-such as NOP. These precautions are not necessary for F6800 processors indicating manufacture in November, 1977 or later. Inherent (Includes "Accumulator Addressing") Mode The successive fields in a statement are normally separated by one or more spaces. An exception to this rule occurs for instructions that use dual addressing in the operand field and for instructions that must distinguish between the two accumulators. In these cases, A and B are "operands" but the space between them and the operator may be omitted. This is commonly done, resulting in apparent four character mnemonics for those instructions. Systems which require an interrupt window to be opened under program control should use a CLI-NOP-SEI sequence rather than CLI-SEI. The addition instruction, ADD, provides an example of dual addressing in the operand field: Addressing Modes The MPU operates on 8-bit binary numbers presented to it via the data bus. A given number (byte) may represent either data or an instruction to be executed, depending on where it is encountered in the control program. The F6800 has 72 unique instructions; however, it recognizes and takes action on 197 of the 256 possibilities that can occur using an 8·bit word length. This larger number of instructions results from the fact that many of the executive instructions have more than one addressing mode. or Operator ADDA Operand MEM12 ADDB MEM12 Comment ADD CONTENTS OF MEM 12 TO ACCA ADD CONTENTS OF MEM 12 TO ACCB The example used earlier for the test instruction, TST, also applies to the accumulators and uses the "accumulator addressing mode" to designate which of the two accumulators is being tested: These addressing modes refer to the manner in which the program causes the MPU to obtain its instructions and data. The programmer must have a method for addressing the MPU's internal registers and all of the external memory locations. or 5·33 Operator TSTB TSTA Comment TEST CONTENTS OF ACCB TEST CONTENTS OF ACCA F6800/F68AOO/F68BOO Direct and Extended Addressing Modes In the direct and extended modes of addressing, the operand field of the source statement is the address of the value that is to be operated on. The direct and extended modes differ only in the range of memory locations to which they can direct the MPU. Direct addressing generates a single 8-bit operand and, hence, can address only memory locations 0 through 255; a two byte operand is generated for extended addressing, enabling the MPU to reach the remaining memory locations, 256 through 65535. An example of direct addressing and its effect on program flow is illustrated in Figure 23. A number of the instructions either alone or together with an accumulator operand contain all of the address information that is required, that is, "inherent" in the instruction itself. For instance, the instruction ABA causes the MPU to add the contents of accumulators A and B together and place the result in accumulator A. The instruction INCB, another example of "accumulator addressing", causes the contents of accumulator B to be increased by one. Similarly, INX, incrementing the index register, causes the contents of the index register to be increased by one. Program flow for instructions of this type is illustrated in Figures 20 and 21. In these figures,the general case is shown on the left and a specific example is shown on the right. Numerical examples are in decimal notation. Instructions of this type require only one byte of opcode. Cycle-by-cycle operation of the inherent mode is shown in Table 8. Fig. 19 The MPU, after encountering the opcode for the instruction LDAA (direct) at memory location 5004 (program counter 5004), looks inthe next location, 5005, for the address of the operand. It then sets the program counter equal to the = Addressing Mode Summary DIRECT: IMMEDIATE: 00 INSTRUCTION EXAMPLE: SUBS Z ADDR. RANGE = 0-255 n+1 &. n Z = OPRND ADDRESS +2 INSTRUCTION EXAMPLE: LDAA #K (K = ONE-BYTE DPRND) NEXT INSTR n+1 K = OPERAND n+2 NEXTINSTR OR (K = TWO-BYTE OPRND) (CPX, LOX. AND LOS) z (K = ONE-BYTE OPRND) ~ (K = TWO-BYTE OPERAND) I INSTRUCTION n+ 1 KH = OPERAND K = OPERAND n+2 KL = OPERAI'jD OR n+3 NEXT INSTR n+1 :t K = BRNCH OFFSET Z \-......;KH:.:...=.,:O_P.,:ER ...A ...N,;;D:.--I Z+1L-__ K~L_=_0_P_ER_A_N_D__~ INSTRUCTION RELATIVE: A IF Z :s i l l IF Z > EXAMPLE: SHE 255, ASSEMBLER SELECT DIRECT MODE K 255, EXTENDED MODE IS SELECTED (K=SIGNED 7~BIT VALUE) n+2 NEXT INSTR & ADDR. RANGE: -125 TO +129 RELATIVE TO n. EXTENDED: EXAMPLE: CMPA Z ADDR. RANGE: 256-65535 &. FO INSTRUCTION (n n + 1 ZH = OPRND ADDRESS n+ 2 n +3 ZL = OPRND ADDRESS + 2) ±K I NEXT INSTR .& IF BRNCH Tat FALSE, .& IF BRNCH Tat TRUE. &: I NEXT INSTR n INSTRUCTION EXAMPLE: ADDA Z, X n +1 Z = OFFSET ADDR. RANGE: 0-255 RELATIVE TO INDEX REGISTER, X n+ 2 NEXT INSTR INDEXED: (K =ONE·BYTE OPRND) zLI___K__=_O_PE_R_A_ND__~ (K = TWD-BYTE OPERAND) Z \-......;K:.;.H_=.,:O... P,;;E... RA.,:N,;;D:'--I OR Z+1L-__ KL:.:...=_0_P_ER_A_N_D__~ 5·34 = a-BIT UNSIGNED VALUE) (Z X +Z I K = OPERAND L.------------~ F6800/F68AOO/F68BOO Table 8 Inherent Mode Cycle·by·Cycle Operation Address Mode and Instructions Address Bus Data Bus Inherent ABA ASL ASR CBA CLC CLI CLR CLV COM DES DEX INS INX DAA DEC INC LSR NEG NOP ROL ROR SBA SEC SEI SEV TAB TAP TBA TPA TST 1 2 1 1 Op Code Address Op Code Address + 1 1 1 Op Code Op Code of Next Instruction 1 2 1 1 0 0 Op Code Address Op Code Address + 1 Previous Register Contents New Register Contents 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 1 1 0 Op Code Address Op Code Address + 1 Stack Pointer Stack Poi nter - 1 1 1 0 1 Op Code Op Code of Next Instruction Accumulator Data Accumulator Data 1 1 0 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data (Note 1) Operand Data from Stack 1 1 0 0 Op Code Address Op Code Address + 1 Stack Pointer New Index Register 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 1 0 0 Op Code Address Op Code Address + 1 I ndex Register New Stack Pointer 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data Irrelevant Data 3 4 1 1 0 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 5 1 Stack Pointer + 2 1 Op Code Irrelevant Data (Note 2) Irrelevant Data (Note 1) Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) 2 4 PSH 4 PUL 4 TSX 4 TXS 4 RTS 3 ,4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 5 5·35 F6800/F68AOO/F68BOO Table 8 Inherent Mode Cycle·by·Cycle Operation (Cont.) Address Mode and Instructions Address Bus Data Bus Inherent (Cont'd) WAI 9 RTI 10 SWI 12 8 9 1 1 1 1 1 1 1 1 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer -1 Stack Pointer - 2 Stack Pointer - 3 Stack Pointer - 4 Stack Pointer - 5 Stack Pointer -6 (Note 3) 1 2 3 4 1 1 0 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer + 1 1 1 1 1 5 6 7 1 1 1 Stack Pointer +2 Stack Pointer + 3 Stack Pointer + 4 1 1 1 8 1 Stack Pointer + 5 1 9 1 Stack Pointer + 6 1 10 1 Stack Pointer + 7 1 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 0 1 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Stack Pointer - 3 Stack Pointer - 4 Stack Pointer - 5 Stack Pointer - 6 Stack Pointer - 7 Vector Address FFFA (Hex) Vector Address FFFB (Hex) 1 1 0 0 0 0 0 0 0 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 1 1 0 0 0 0 0 0 1 Op Code Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Op Code Irrelevant Data (Note 2) Irrelevant Data (Note 1) Contents of Condo Code Register from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) Op Code Irrelevant Data (Note 1) Return Address (LOw Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Irrelevant Data (Note 1) Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Notes 1. If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3-state condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. 2. Data is ignored by the MPU, 3. While the MPU is waiting for the interrupt, Bus Available will go HIGH indicating the following states of the control lines: VMA is LOW; address bus, R IW, and data bus afe all in the high impedance state. 5·36 F6800/F68AOO/F68BOO Fig. 20 Inherent Addressing Fig. 22 Immediate Addressing Mode MPU PC PC PC t-"";;';';"=-I/ PC = 5002 GENERAL FLOW =$000 Fig. 23 EXAMPLE Direct Addressing Mode EXAMPLE GENERAL FLOW Fig. 21 MPU Accumulator Addressing MPU MPU t--------I\ ADDR = 100 t------f\ + 1 t--=~-ll PC = 500' 5005 t---~""-Ill AOOR PC PC AODR ~ 0 ~ 255 GENERAL FLOW pc pc ~ 5001 GENERAL FLOW EXAMPLE 5·37 EXAMPLE F6800/F68AOO/F68BOO Table 9 Immediate Mode Cycle·by·Cycle Operation Address Mode and Instructions Data Bus Address Bus Immediate ADC ADD AND BIT CMP EOR LOA ORA SBC SUB CPX LOS LOX 1 2 1 1 Op Code Address Op Code Address + 1 1 1 Op Code Operand Data 1 2 1 1 1 Op Code Address Op Code Address + 1 Op Code address + 2 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte) 2 3 3 Table 10 Direct Mode Cycle·by·Cycle Operation Address Mode and Instructions Address Bus Data Bus Direct ADC ADD AND BIT CMP CPX LOS LOX EOR LOA ORA SBC SUB 1 2 3 4 STA 4 STS STX 5 1 1 1 Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data 3 4 1 1 1 1 Op Code Address Op Code Address + 1 Address of Operand Operarld Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 2 1 1 3 4 0 Op Code Address Op Code Address + 1 Destination Address Destination Address 1 1 1 Op Code Destination Address Irrelevant Data (Note) Data from Accumulator 1 2 1 1 3 4 5 0 3 1 2 1 1 1 Op Code Address Op Code Address + 1 Address of Operand Address of Operand Address of Operand + 1 0 1 1 1 0 0 Op Code Address of Operand Irrelevant Data (Note) Register Data (High Order Byte) Register Data (Low Order Byte) Note If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3·state condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. 5-38 F6800/F68AOO/F68BOO with the" #" symbol. Program flow for this addressing mode is illustrated in Figure 22. value found there (100 in the example) and fetches the operand, in this case a value to be loaded into accumulator A, from that location. For instructions requiring a 2-byte operand such as LOX (load the index register), the operand bytes would be retrieved from locations 100 and 101. Table 10 shows the cycle-by-cycle operations for the direct mode of addressing. The operand format allows either properly defined symbols or numerical values. Except for the instructions CPX, LOX, and LOS, the operand may be any value in the range a to 255. Since compare index register (CPX), load index register (LDX), and load stack pointer (LOS), require 1S-bit values, the immediate mode for these three instructions requires two-byte operands. In the immediate addressing mode, the "address" of the operand is effectively the memory location immediately following the instruction itself. Table 9 shows the cycle-by-cycle operation for the immediate addressing mode. Extended addressing, Figure 24, is similar except that a twobyte address is obtained from locations 5007 and 5008 after the LOAB (extended) opcode shows up in location 500S. Extended addressing can be thought of as the standard addressing mode, that is, it is a method of reaching any place in memory. Direct addressing, since only one address byte is required, provides a faster method of processing data and generates fewer bytes of control code. In most applications, the direct addressing range, memory locations 0-255, are reserved for RAM. They are used for data buffering and temporary storage of system variables, the area in which faster addressing is of most value. Cycle-bycycle operation is shown in Table 11 for extended addressing. Fig,24 Relative Addressing Mode In both the direct and extended modes, the address obtained by the MPU is an absolute numerical address. The relative addressing mode, implemented for the MPU's branch instructions, specifies a memory location relaJive to the program counter's current location. Branch instr"uctions generate two bytes of machine code, one for the instruction opcode and one for the "relative" address. (See Figure 25.) Since it is desirable to be able to branch in either direction, the 8-bit address byte is interpreted as a signed 7 -bit value; the 8th bit of the operand is treated as a sign bit, "0" = plus and" 1" = minus. The remaining seven bits represent the numerical value. This results in a relative addressing range of ± 127 with respect to the location of the branch instruction itself. However, the branch range is computed with respect to the next instruction that would be executed if the branch conditions are not satisfied. Since two bytes are generated, the next instruction is located at PC + 2. If 0 is defined as the address of the branch designation, the range is then: Extended Addressing Mode MPU ADDR .......;;=~-I'\ -=--4" ADDR ~ 300 .... or pc ~ 5006 PC ....~=~-I'\ 5009 ADDR 256 GENERAL FLOW 1--";;;;;';';;--1 + 2) + 127 that is, the destination of the branch instruction must be within -125 to + 129 memory locations of the branch instructions itself. For transferrring control beyond this range, the unconditional jump (JMP), jump to subroutine (JSR), and return from subroutine (RTS) are used. --- .... EXAMPLE In Figure 25, when the MPU encounters the opcode for BEQ (branch if result of last instruction was zero), it tests the zero bit in the condition code register. If that bit is "0", indicating a non-zero result, the MPU continues execution with the next instruction (in location 5010 in Figure 25). If the previous result were zero, the branch condition is satisfied and the MPU adds the offset, 15 in this case, to PC + 2 and branches to location 5025 for the next instruction. Immediate Addressing Mode In the immediate addressing mode, the operand is the value that is to be operated on. For instance, the instruction Operator LOAA (PC + 2) - 127:::; 0 :::; (PC PC - 125:::; 0 :::; PC + 129 Operand #25 Comment LOAD 25 INTO ACCA causes the MPU to "immediately load accumulator A with the value 25"; no further address reference is required. The immediate mode is selected by preceding the operand value 5-39 F6800/F68AOO/F68BOO Table 11 Extended Mode Cycle·by·Cycle Operation Address Mode and Instructions Data Bus Address Bus Extended STS STX 1 2 6 JSR 3 1 1 1 4 0 5 6 1 1 1 2 1 1 1 1 1 1 7 8 9 0 0 1 Op Code Address Op Code Add ress + 1 Op Code Address + 2 Subroutine Starting Address Stack Pointer Stack Pointer -1 Stack Pointer - 2 Op Code Address + 2 Op Code Address + 2 3 1 2 1 1 1 Op Code Address Op Code Address +1 Op Code Address +2 1 1 1 Op Code Jump Address (High Order Byte) Jump Address (Low Order Byte) 1 1 1 1 Op Code Address Op Code Add ress +1 Op Code Address +2 Address of Operand 1 1 1 1 Op Code Address of Operand (H igh Order Byte) Address of Operand (Low Order Byte) Operand Data 1 1 1 1 1 Op Code Add ress Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 1 1 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Operand Data (High Order Byte) Operand Data (Low Order Byte) 3 1 1 1 4 0 Op Code Op Code Op Code Operand Operand 1 1 1 1 Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) I rrelevant Data (Note 1) Data from Accumulator 5 6 3 ADC ADD AND BIT CMP EOR LOA ORA SBC SUB CPX LOS LOX 1 2 4 3 4 1 2 5 3 4 5 STA STA A B 2 5 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 5 1 1 2 1 1 1 1 3 6 0 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) I rrelavant Data (Note 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 1 1 4 JMP 1 1 1 1 Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Address of Subroutine (Low Order Byte) 3 9 Op Code Address Op Code Add ress + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand +1 4 5 6 0 1/0 (Note 2) Address Address + 1 Address + 2 Destination Address Destination Address Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand 1 1 1 1 0 0 0 1 1 1 1 1 0 Op Code Address of Operand (H igh Order Byte) Address of Operand (Low Order Byte) Curent Operand Data Irrelevant Data (Note 1) New Operand Data (Note 2) Notes 1. If device which is addressed during this cycle uses VMA" then the data bus will go to the high impedance 3-state condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. 2. For TST, VMA = "0" and operand data does not change. 5·40 F6800/F68AOO/F68BOO The branch instructions allow the programmer to efficiently direct the MPU to one point or another in the control program depending on the outcome of test results. Since the control program is normally in read-only memory and cannot be changed, the relative address used in execution of branch instructions is a constant numerical value. Cycle-by-cycle operation is shown in Table 12 for relative addressing. The operand field can also contain a numerical value that will be automatically added to X during execution. This format is illustrated in Figure 26. When the MPU encounters the LOAB (Indexed) opcode in location 5006, it looks in the next memory location for the value to be added to X (5 in the example) and calculates the required address by adding 5 to the present index register value of 400. In the operand format, the offset may be represented by a label or a numerical value in the range 0255 as in the example. In the earlier example, STAA X, the operand is equivalent to 0, X, that is, the a may be omitted when the desired address is equal to X. Table 13 shows the cycle-by-cycle operation for the indexed mode of addressing. Indexed Addressing Mode With indexed addressing, the numerical address is variable and depends on the current contents of the index register. A source statement such as Operator STAA Operand Comment Put A in Indexed Location X Fig. 26 causes the MPU to store the contents of a·ccumulator A in the memory location specified by the contents of the index register (recall that the label "X" is reserved to designate the index register). Since there are instructions for manipulating X during program execution (LOX, INX, OEX, etc.), the indexed addressing mode provides a dynamic on· the-fly way to modify program activity. Indexed Addressing Mode MPU MPU ""'I.I AOOR ~ INOX ....~~... OFFSET Fig. 25 Relative Addressing Mode t-----{\ = 405 t------41' PC ~ 5006 t-"';;=---4/ ADOR MPU PC OFFSET:s; 255 GENERAL FLOW PC (PC + 2) 1-';;';';;';';';'_"" 5008 PC 5010 .~=.;..;;;;;,;,~ PC 5025 (PC +2) + (OFFSET) t--"";---4I\ PC t-----4 ~";;';~;';"~I\ 5·41 EXAMPLE F6800/F68AOO/F68BOO Table 12 Relative Mode Cycle·by·Cycle Operation Address Mode and Instructions Address Bus Data Bus Relative BCC BCS BEQ BGE BGT BHI BlE BlS BlT BMI BNE BPl BRA BVC BVS 4 1 2 3 4 1 2 BSR 3 8 4 5 6 7 8 1 1 0 0 Op Code Address Op Code Address + 1 Op Code Address + 2 Branch Address 1 1 1 1 Op Code Branch Offset Irrelevant Data (Note) Irrelevant Data (Note) 1 1 0 1 1 0 0 0 Op Code Address Op Code Address + 1 Return Address of Main Program Stack Poi nter Stack Pointer - 1 Stack Pointer - 2 Return Address of Main Program Subroutine Address 1 1 1 0 0 1 1 1 Op Code Branch Offset Irrelevant Data (Note) Return Address (low Order Byte) Return Address (High Order Byte) Irrelevant Data (Note) Irrelevant Data (Note) Irrelevant Data (Note) Note If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedanc,e 3·5tate condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. Table 13 Indexed Mode Cycle·by·Cycle Operation Address Mode and Instructions Address Bus Data Bus Indexed JMP 4 ADC ADD AND BIT CMP EOR lOA ORA SBC SUB 5 CPX lDS lOX 6 STA 6 1 2 3 4 1 1 0 0 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 2 3 4 1 1 0 0 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 5 1 Op Code Address Op Code Address +1 Index Register Index Register Plus Offset (w/O Carry) Index Register Plus Offset 1 Operand Data Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset + 1 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 1 Operand Data (H igh Order Byte) Operand Data (lOW Order Byte) Op Code Address Op Code Address + 1 I ndex Register Index Register Plus Offset (w/O Carry) Index Register Plus Offset Index Register Plus Offset 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 0 Irrelevant Data (Note 1) Operand Data 1 2 3 4 1 1 0 0 5 6 1 1 1 2 3 4 1 1 0 0 5 0 1 6 5-42 F6800/F68AOO/F68BOO Table 13 Indexed Mode Cycle·by·Cycle Operation (Cont.) Address Mode and Instructions Address Bus Data Bus Indexed (Cont.) ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 1 2 3 4 7 5 6 7 1 2 STS STX 7 JSR 8 1 1 a a 1 a 110 (Note 2) 1 1 3 a 4 0 5 6 7 0 1 2 1 1 1 1 3 a 4 5 6 7 1 1 0 0 8 a Op Code Address Op Code Add ress +1 Index Register I ndex Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset Op Code Address Op Code Address + 1 I ndex Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset + 1 Op Code Address Op Code Address + 1 Index Register Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Index Register Index Register Plus Offset (w/o Carry) 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 1 0 Current Operand Data Irrelevant Data (Note 1) New Operand Data (Note 2) 1 1 1 1 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) 1 0 0 Irrelevant Data (Note 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 1 1 0 0 1 1 1 Op Code Offset Irrelevant Data (Note 1) Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Note 1. If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3-state condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. 2. For TST, VMA = "0" and operand data does not change. 5·43 F6800/F68AOO/F68BOO Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature Range- TL to TH F6800,F68AOO, F68BOO F6800C, F68AOOC, F68BOOC F6800DM, F68AOODM, F68BOODM Storage Temperature Range Thermal Resistance Plastic Package Ceramic Package DC Characteristics Symbol O°C, -40°C, -55°C, -55°C, +70°C +85°C +125°C +150°C 70°C/W 50°C/W Vee = 5.0 V ± 5%, Vss = 0, TA = TL to TH, unless otherwise noted Characteristic VIH VIHe Logic ",1, ",2 VIL VILe Input LOW Voltage Logic ",1, ",2 lIN Input Leakage Current Logic ",1, ",2 ITSI 3-State (OFF State) 00- 0 7 Input Current Ao-AI5, R/W VOH Output HIGH Voltage 00- 0 7 Ao-A I5 , R/W, VMA BA VOL Output LOW Voltage Po Power Dissipation CIN Input Capacitance >1 >2 00- 0 7 Logic Inputs Typ Max Unit Vss + 2.0 Vee - 0.6 Vee Vee + 0.3 V Vss - 0.3 Vss - 0.3 Vss + 0.8 Vss + 0.4 V 1.0 2.5 100 p.A VIN = 0 to 5.25 V, Vee = Max VIN = 0 to 5.25 V, Vee = 0.0 V 2.0 10 100 p.A VIN = 0.4 to 2.4 V, Vee = Max Min Input HIGH Voltage COUT This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields: however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. -0.3 V, +7.0 V -0.3 V, +7.0 V Vss + 2.4 Vss + 2.4 Vss + 2.4 V ILoad = -205 p.A, Vee = Min ILoad = -145 p.A, Vee = Min ILoad = -100 p.A, Vee = Min ILoad = 1.6 mA, Vee Vss + 0.4 V 0.5 1.0 W 25 45 10 6.5 35 70 12.5 10 pF 12 pF Output Capacitance Ao-AI5, R/W, VMA 5·44 Conditions = Min VIN = 0, TA = 25°C, f = 1.0 MHz F6800/F68AOO/F68BOO Clock Timing Symbol Vcc = 5.0 V ± 5%, V ss = 0, TA = TL to TH. unless otherwise noted Characteristic Min Typ Max Unit Conditions Frequency of Operation f F6800 F68AOO F68BOO 0.1 0.1 0.1 1.0 1.5 2.0 MHz F6800 F68AOO F68BOO 1.000 0.666 0.500 10 10 10 !is >1, >2 - F6800 >1, >2 - F68AOO >1. >2 - F68BOO 400 230 180 9500 9500 9500 ns F6800 F68AOO F68BOO 900 600 440 teye Cycle Time (Figure 27) PW.pH Clock Pulse Width tut Total >1 and >2 Up Time t.pr. t.pf Rise and Fall Times td Delay Time or Clock Separation (Figure 27) Read/Write Timing ns 0 0 100 ns Measured Between Vss + 0.4 V and Vcc - 0.6 V 9100 9100 ns Vav = Vss Vav = Vss tAO CharacteristiC Min Typ tf ~ 100 ns tf ~ 35 ns F68AOO Max Min Typ F68BOO Max Min Typ Max Address Delay Unit ns C=90pF C = 30 pF taee + 0.6 V @ tr = + 1.0 V @ tr = (Reference Figures 28 through 32) F6800 Symbol Vcc- 0.6V Peripheral Read Access Time taee = tut - (tAO + tOSR) 270 250 180 165 150 135 530 360 250 ns tOSR Data Set-up Time (Read) 100 60 40 ns tH Input Data Hold Time 10 10 10 ns tH Output Data Hold Time 10 25 10 25 10 25 ns tAH Address Hold Time (Address. R/W. VMA) 30 50 30 50 30 50 ns tEH Enable HIGH Time for DBE Ihput 450 toow Data Delay Time (Write) tpcs tpcr, tpCf tSA trsE trso tOBE tOBEr, tOBEf Processor Controls Processor Control Set-up Time Processor Control Rise and Fall Time Bus Available Delay 3-State Enable 3-State Delay . Data Bus Enable Down Time During > 1 Up Time Data Bus Enable Rise and Fall Times 280 225 220 140 200 100 250 40 270 150 110 100 165 40 270 120 25 545 ns 160 200 ns 100 135 40 220 75 25 ns ns ns ns ns ns 25 ns F6800/F68AOO/F68BOO Fig. 27 Clock Timing Waveform ~------------~------------~ ., ~f Fig. 28 Read Data From Memory or Peripherals \,"---------iilr,-O.BV R/W ADDRESS FRDMMPU'____ ~~~~~~~~~~~------------------------------------!__+~ VMA DATA FROM MEMORY DR PERIPHERALS ~ DATA NOT VALID 5-46 2.0V ---:::::aoo"""'II!!!!===~iOo:: 0.8 v --::::!!Oi'!-=;;;;;;;;;;;;;;__"'l F6800/F68AOO/F68BOO Fig. 29 Write In Memory or Peripherals ADDRESS FROM MPU VMA tDler DATA FROM MPU DATA VALID ~ DATA NOT VALID 5-47 F6800/F68AOO/F68BOO Fig. 30 Typical Data Bus Output Delay vs Capacitive Loading (to ow) 500 Fig. 31 Typical READ/WRITE, VMA, and Address Output Delay vs Capacitive Loading (tAD) 500 ~ ~20J~A~AX~2.JV leiH -IOL ~ 1.6mAMAX@0.4V Vee ~ 5.0 V 400 - T . ~ 25°C ~ 145~~M~x@t4v leiH -IOL ~ 1.6mAMAX@0.4V Vee ~ 5.0V 400 - T . = 25"<: ~ I w 300 >- ::3 w 200 ............ Q 100 w 300 I--' :E ;:: :E L ;:: .. .....- V >- .... W 200 Q ...V 100 V ...... V CL INCLUDES STRAY CAPACITANCE 100 200 400 300 .....- VMt- .....ADDRESS R/W-- CL INCLUDES STRAY CAPACITANCE 100 500 CL - LOAD CAPACITANCE - pF Fig. 32 fo' ....- .....- V I--' 200 300 400 500 CL - LOAD CAPACITANCE - pF Bus Timing Test Loads Test Conditions Vee The dynamic test load for the data bus is 130 pF and one standard TTL load. as shown. The Address. R/iN. and VMA RL = 2.2k outputs are tested under two conditions to allow optimum operation in both buffered and unbuffered systems. The resistor (R) is chosen to insure specified load currents during V OH measurement. TEST POINT -.--<~-KI--+ NOtice that the data bus lines. the address lines, the interrupt IN914 OR eQUIV request line. and the OBE line are all specified and tested to guarantee 0.4 V of dynamic noise immunity at both "1" snd "0" logic levels. C = 130 pF for 0 0 -0,. E = 90 pF for AD-A,s. R/iN. and VMA (except tAD.) = 30 pF for AD-A, •• R/iN. and VMA (tAO. only) = 30 pF for BA. R = 11.7 k!l for 0 0 -0, = 16.5 k!l for Ao-A ... R/iN. and VMA = 24 k!l for BA 5·48 F6800/F68AOO/F68BOO Ordering Information Speed Order Code 1.0 MHz F6800P,S 1.5 MHz 2.0 MHz Temperature Range o to +70°C F6800CP,CS -40 to +85°C F6800DM -55 to +125°C F68AOOP,S o to +70°C F68AOOC,CS -40 to +85°C F68AOODM -55 to +125°C F68BOOP,S o to +70°C F68BOOC,CS -40 to +85°C F68BOODM -55 to +125°C 'P= plastic package, S= CER·DIP package. 5·49 F6800/F68AOO/F68B00 5·50 F6801/F6803 FAIRCHILD Single-Chip Microcomputer A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The Fairchild F6801/F6803 is an 8-bit single-chip microcomputer unit (MCU) which significantly enhances the capabilities of the F6800 family. It includes an upgraded F6800 microprocessor unit (MPU) with upward-source and object-code compatibility. The F6801/F6803 MCU can function as a monolithic microcomputer or can be expanded to a 64K byte address space. Features of the F6801lF6803 MCU include: • • • • • • • • • • • • • • Vss Enhanced F6800 Instruction Set (see table 1) 8 x 8 Multiply Instruction Serial Communications Interface (SCI) 16-bit Three-Function Programmable Timer Bus Compatibility with the F6800 Family 2048 Bytes of ROM (F6801 Only) 128 Bytes of RAM 64 Bytes of RAM, Retainable During Powerdown 29 Parallel 110 and Two Handshake Control Lines Internal Clock Generator With Divide-by-Four Output Interrupt Capability TTL compatible 40·Pin Ceramic or Plastic Package + 5V Power Supply The F6801/F6803 MCU can be configured to function in a wide variety of applications. This flexibility is provided by its ability to be hardware-programmed into eight different operating modes (see table 2). The operating mode controls the configuration of 18 of the 40 MCU pins, available onchip resources, memory map, location of interrupt vectors, and type of external bus. Configuration of the remaining 22 pins is not dependent on the operating mode. E XTAL1 sc, EXTAL2 SC, NM P 30 fROj P31 REm P" Vee P33 P,o P,. P 21 P35 P" P" P" P" P'4 P 40 P'0 P 4l Pll P4' P12 P43 P13 P44 P '4 P 45 P15 P4• P,. P47 PH vee STANDBY The F6803 can be considered an F6801 that operates in Modes 2 and 3 only (either internal RAM with no ROM, or no internal RAM or ROM, respectively). 5-51 • F6801/F6803 Figure 1 Block Diagram nr= r--;::::: I P37 A7 / 1>, 07 PM Ae/D. D. P35 p.. As/D. ",/D. D. D. P33 P33 Pa, p.. SC. SC, A,/D, A,ID, 11010. D, D. D, Ao/I!D. ~ I MODE EXPANDED MULTIPLEXED EXPANDED NON·MULTIPLEXED SINGLE CHIP r----.. ~~~--~4-~~PN /L_L I I PORT 2 p., ~-1r-t---""'+~-1f--:j:-_--""'- p•• ~-1--~f-+----P33 ..... ~~~~~~~~PM ---' R/W R/W AS lOS TIMER SCI P47 p.. p•• p.. p•• p.. p., p.. A,s A,. A,a A,. Al1 A,. Ao Ao p,. A, Ae A. Pl1 p,. PORT 1 '" Aa A. A, P13 p,. p,. p,. P17 Ao 5-52 F6801/F6803 Figure 2 Programming Model 8·BIT ACCUMULATORS A AND B OR 16·BIT DOUBLE ACCUMULATOR D o1 INDEX REGISTER (X) 115 X 115 SP 01 STACK POINTER (SP) 115 PC 01 PROGRAM COUNTER (PC) C CONDITION CODE REGISTER (CCR) ' - - - - - - - - HALF CARRY (From Bit 3) 5-53 • F6801/F6803 Table 1 New Instructions Instructlo ABX ADDD ASLD or LSLD BHS BLO BRN JSR LDD LSL LSRD MUL PSHX PULX STD SUBD CPX Description Unsigned addition of Accumulator B to Index Register Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator Shifts the double accumulator left (towards MSB) one bit, the LSB is cleared and the MSB is shifted into the C-bit Branch if Higher or Same, unsigned conditional branch (same as BCC) Branch if Lower. Unsigned conditional branch (same as BCS) Branch Never Additional addressing mode direct Loads double accumulator from memory Shifts memory or accumulator left(towards MSB) one bit, the LSB is cleared and the MSB ia shifted into the C-bit (same as ASL) Shifts the double accumulator right (towards LjSB) one bit, the MSB is cleared and the LSB is shifted into the C-bi! Unsigned multiply, multiplies the two accumulators and leaves the product in the double accumulator Pushes the Index Register to stack Pulls the Index Register from stack Stores the double accumulator to memory Subtracts memory from the double accumulator and leaves the difference in the double accumulator Internal processing modified to permit its use with any conditional branch instruction 5-54 F6801/F6803 Table 2 Summary of F6801/F6803 Operating Modes Common to all Modes: Reserved Register Area Port 1 Port 2 Programmable Timer Serial Communications Interface Single Chip Mode 7 128 bytes 0 RAMk, 2048 bytes of ROM Port 3 is a parallel I/O port with two control lines Port 4 is a parallel I/O port SC1 is Input Strobe 3 (153) SC2 is Output Strobe 3 (053) Expanded Non-Multiplexed Mode 5 128 bytes of RAM, 2048 bytes of ROM 256 bytes of external memory space Port 3 is an 8-bit data bus Port 4 is an input port/address bus SC1 is InpuUOutput Select (105) SC2 is Read/Write (R/W) Expanded Multiplexed Modes 1, 2, 3 6 Sour memory space options (64K address space) (1) No internal RAM or ROM (Mode 3) (2) Internal RAM, no ROM (Mode 2) (3) Internal RAM and ROM (Mode 1) (4) Internal RAM, ROM with partial address bus (Mode 6) Port 3 is a multiplexed address/data bus Port 4 is an address bus (inputs/address in Mode 6) SC1 is Address Strobe (AS) SC2 is Read/Write (RIW) Test Modes 0 and 4 Expanded Multiplexed Test Mode 0 May be used to test RAM and ROM Single Chip and Non-Multiplexed Test Mode 4 (1) May be changed to Mode 5 without going through reset (2) May be used to test Ports 3 and 4 as 110 ports 5-55 • F6801/F6803 Table 3 . Instruction Execution Times In E·Cycles Addressing Mode i i E .5 ABA ABX ADC ADD AODD AND ASl ASlD ASR BCC BCS BEQ BGE BGT BHI BHS BIT BlE BlO BLS BlT BMI BNE BPl BRA BRN BSA BVC BVS CBA ClC CLI ClR ClV CMP COM CPX DAA DEC DES DEX EOR INC INS • •2 2 4 2 • • •• • • •• •• 2 • •• • •• • •• •• •• ••• •2 •4 •• Addressing Mode i i '1lI w ~ .5 s::. .5 • •3 ••4 ••4 2 3 3 5 3 4 4 6 6 I I) 4 • 6 • • • 6 •• •• • • •• •• ••3 ••4 • •• ••• • • • •• ••• • • • • • • • • • • • • •• •• • •6 •3 4 •5 66 ••• ••6 :.1 '1lI 4 6 •6 •• • •• • •4 ~ I) • • • •2 3 2 • •• •• • ••• •• • • • • • • • •• •• •• •• • • • • • •• 22 •• 2 6 2 •4 •2 6 6 •6 2 •2 2 •• • • •• 33 2 3 •• •• •6 •6 ••3 4 4 iE I.!!! i'1lI '1lI ~ .5 •3 •3 5 3 6 6 4 4 3 3 3 4 4 4 5 5 5 5 5 5 •• • •• •• 2 • •• •• • •• •2 •• • • • •• 3 • • •• • • •• •3 • • • 6 6 I) I) .5 II: • • •• • •• • •3 INX JMP JSR lDA lDD lDS lDX lSl lSlD lSR lSRD MUl NEG NOP ORA PSH PSHX PUl PULX ROl ROR RTI RTS SBA SBC SEC SEI SEV STA STD STS STX SUB SUBD SI TAB TAP TBA TPA TST TSX TXS WAI 3 3 3 3 3 3 •3 3 3 3 3 3 3 3 3 6 3 3 • • •• •• •• • • • • •• • 5·56 •• •2 •• • • • • •2 4 • • • • • •• •• Ii •• 0 c :: I) '1lI •6 ••6 ••6 • • 4 4 • • • • • • •6 •6 •6 6 6 • •• 4 • • • • •• 4 • • • 3 4 4 4 4 4 5 5 5 5 5 5 3 5 4 4 6 6 • •• • • • • •• • •• • •6 •• • • • •• •6 • •• C ! II s::. .5 3 • • • •• • 2 3 2 3 10 2 2 •3 4 4 5 2 2 10 5 2 •2 2 2 • • • • • • 12 2 2 2 2 2 3 3 9 I) ~ ]I CD II: • •• • • •• •• • • •• • • • •• •• • •• • •• •• • • • • • • • •• • • •• •• F6802lF68821F6808 Microprocessor with Clock and RAM FAIRCHILD A Schlumberger Company Microprocessor Product Description Connection Diagram The F6802/F6882 is a monolithic 8·bit microprocessor that contains all the registers and accumulators of the F6800, plus an internal clock oscillator and driver on the same chip. The F6802/F6882 also has 128 bytes of RAM on board, located at hex addresses $0000 to $007F, Vee standby can be utilized on the F6802/F6882 to facilitate memory retention during a power·down situation; the first 8 bytes of RAM at hex addresses $0000 to $0007 can be retained on the F6882, and the first 32 bytes of RAM at hex addresses $0000 to $001 F can be retained on the F6802. The F6808 is identical to the F6802 without on· board RAM. 40·Pln DIP RESET EXTAL MR XTAL IRQ E RE VMA vee NMI STANDBY RIW BA The F6802/F6882 is completely software·compatible with the F6800 microprocessor and the entire F6800 family of parts. (Figure 1 illustrates a typical application using an F6800 family device.) • • • • • • • • • • vss HALT On·Chip Clock Circuit 128 x 8·bit On·Chip RAM (Not Included on F6808) 8 Bytes of RAM are Retalnable on the F6882 32 Bytes of RAM are Retalnable on the F6802 Software·Compatible with the F6800 Standard TTL·Compatible Inputs and Outputs 8·blt Bidirectional Data Bus 16·blt Memory Addressing Interrupt Capability Speed Grades: 1.0 MHz F6802/F6882JF6808 1.5 MHz F68A02/F68A82/F68A08 vee D. A. 0, A, 0, A, 0, A, D. A4 Os As D. A. 07 A7 A15 As A14 As A13 A10 A12 A11 Vss • F6802/F6882/F6808 Signal Functions RAM CONTROL INPUTS RE Ao A, A, A, CLOCK CONTROL j EXTAL A4 XTAL As MR A. A7 RESET CPU CONTROL INPUTS 1 As As NMI A,. IRQ A" ADDRESS BUS HALT BA "" 1 CONTROL OUTPUTS VMA RiW D. 0, '~'1 5·57 0, vee vee vSTBY __ 0, D. Os D. DATA BUS F6802/F6882/F6808 Fig. 1 Typical Microcomputer Block Diagram Vee Vee Vee Vee COUNTER TIMER 110 RESET PARALLEL 110 { = RESET F6846 ROM, I/O, TIMER RES ....-- MR eso I_-'-V"'MA"----l --- 1~ -- I Vee STANDBY HALT VMA CLOCK 2K BYTES ROM 10 I/O LINES 3 LINES TIMER --- 00-07 RE I_..:.:R:..:/W'-----l R/W F68021 NMI --I -..-.-= ~ F6882 ~ BA 00-07 XT AL f-----,--, EXTAL I: Registers Stack Pointer The stack pOinter is a 2·byte register that contains the address of the next available location in an external push·down/pop·up stack. This stack is normally a random access read/write memory that may have any location (address) that is convenient. In those applications that require storage of information in the stack when power is lost, the stack must be non·volatile. A general block diagram of the F6802/F6882 is shown in Figure 2. The number and configuration of the registers are identical to the F6800, as shown, with a 128 x 8-bit RAM' added to the basic microprocessor. The first 8 bytes in the F6882 and the first 32 bytes in the F6802 may be operated in a low·power mode via a Vee standby and can be retained during power·up and power·down conditions via the RE signal. The F6808 is identical to the F6802 except for on·board RAM. Since the F6808 does not have on·board RAM, pin 36 must be tied to ground, allowing the processor to utilize up to 64K bytes of external memory. Index Register The index register is a 2-byte register that is used to store data or a 16·bit memory address for the indexed mode of memory addressing. Accumulators The two 8·bit accumulators are used to hold operands and results from an arithmetic logic unit (ALU). The microprocessing unit (MPU) has three 16-bit registers and three 8-bit registers available for use by the programmer, as shown in Figure 3. Program Counter The program counter is a 2-byte (16·bit) register that points to the current program address. 'If programs are not executed from on·board RAM, TAV1 applies. If pro· grams are to be stored and executed from on·board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs can be executed from on·board RAM when using 1.5 parts. Onboard RAM can be used for data storage with all parts. 5-58 F6802lF6882/F6808 Fig. 2 F6802lF6882 Block Diagram A, At A, At As A, A, Ao 16 15 14 13 12 11 10 9 MEMORY READY 3 ENABLE 37 RESET NON·MASKABLE INTERRUPT 40 6 HALT 2 INTERRUPT REQUEST 4 EXTAL 39 XTAL 39 • BUS AVAILABLE VALID MEMORY ADDRESS READIWRITE 34 26 27 28 29 30 31 32 33 D,Ile D,D,D, 0,0,00 Condition Code Register (Status Word Register) The condition code register Indicates the results of an arlthm!ltic logic unit operation; negative (N), zero (Z), overflow (V), carry from bit 7 (e), and half·carry from bit 3 (H). These bits of the condition code register are used as testable conditions for the conditional branch instructions. Bit 4 is the Interrupt mask bit (I). The unused bits of the condition code register (bit 6 and bit 7) are binary ones (1). Figure 4 shows the order of saving the microprocessor status within the stack. 5·59 F6802lF68821F6808 Fig. 3 Programming Model of the Microprocessing Unit ______ I ° I --,i --,l ..I"______ --'°l F6802lF6882 Signal Descriptions The control and timing signals for the F6802/F6882 are identical to those of the F6800, with the following exceptions: ' - -_ _ A_CC_A_ _.... ACCUMULATOR A ' - -_ _ A_CC_B_ _.... ACCUMULATOR B 1~:5_ _ _ _ _ _'x_ _ _ _ _ ~r 1. TSC, DBE . E When RESET is released, it must go through the low-tohigh threshold without bouncing, oscillating, or otherwise causing an erroneous reset (less than three clock cycles) that may cause improper MPU operation until the next valid reset. -----------------. Fig. 5 RE Power-Up and Reset Timing Vee t \ RESET----------~~ v'll""--------'· RE ________________~V~'L ---.. 4 - - tpCR Note " option 1 is chosen, RESET and RE pins can be tied together. 5-61 OPTION 1 (SEE NOTE BELOW) -----------------OPTION 2 SEE FIGURE 4 FOR POWER DOWN CONDITION F6802lF6882/F6808 Fig. 7 NMI (Non-Maskable Interrupt), Pin 6 A low-going edge on this input requests that a nonmaskable interrupt sequence be generated within the processor. As with the Interrupt request (IRQ) signal, the processor completes the current instruction being executed before it recognizes the iifMT signal. The interrupt mask bit In the condition code register has no effect on NMI. MPU Flow Chart The index register, program counter, accumulators, and condition code register are stored on the stack, as shown in Figure 4. At the end of the cycle, a 16-bit address will be loaded from memory locations $FFFC and $FFFD that pOints to a vectoring address. An address loaded from these locations causes the MPU to branch to a non-maskable interrupt routine in memory. A nominal 3 kO external resistor to Vee should be used for wire-OR and optimum control of interrupts. The NMI signal may be tied directly to Vee if not used. The IRQ and NMI inputs are hardware interrupt lines that are sampled when E is high and start the interrupt routine on a low E following the completion of an instruction. Figure 7 Is a flow chart describing the major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors. Table 1 Memory Map for Interrupt Vectors Vector MS LS $FFFE $FFFF $FFFC $FFFD Non-Maskable Interrupt $FFFA $FFFB Software Interrupt $FFFB $FFF9 Interrupt Request Description Restart so that no further interrupts may occur. At the end of the cycle, a 16-bit address is loaded from memory locations $FFFB and $FFF9 that point to a vectoring address. An address loaded from these locations causes the MPU to branch to an interrupt routine in memory. IRQ (Interrupt Request), Pin 4 This level-sensitive input requests that an interrupt sequence be generated within the machine. The processor waits until it completes the current instruction that is being executed before it recognizes the request. At that time, If the interrupt mask bit in the condition code register is not set, the machine begins an interrupt sequence. The Index register, program counter, accumulators, and condition code register are stored on the stack as shown In Figure 4. The MPU responds to the Interrupt request by setting the interrupt mask bit high The HALT line must be in the high state for interrupts to be serviced. Interrupts are latched Internally while HALT Is low. . The IRQ has a high-Impedance pull-up device Internal to the chip; however, a 3kO external resistor to Vee should be used for the wire-OR and optimum control of interrupts. 5-62 F6802/F6882/F6808 HALT (Halt), Pin 2 When this input is in the low state, all activity in the machine is halted. This input is level-sensitive. In the halt mode, the machine stops at the end of an instruction. Bus Available is in a high state, and Valid Memory Address is in a low state. The address bus displays the address of the next instruction. R/W (Read, Write), Pin 34 This TTL-compatible output signals the periphals and memory devices whether the MPU is in a read (high) or write (low) state. The normal standby state of this signal is read (high). When the processor is halted, it is in the read state. This output is capable of driving one standard TTL load and 90 pF. To ensure single-instruction operation, transition of the HALT line must occur tpcs before the falling edge of E and the HALT line must go high for one clock cycle. Power vcc (Power Supply), Pin 8 Vcc tolerance is ± 5%,. HALT should be tied high if not used; vcc STBY (Power Supply Standby), Pin 35 This pin supplies the dc voltage to the first 8 or 32 bytes of RAM as well as the RAM enable (RE) control logic. • Thus, retention of data in this portion of the RAM on a power-up, power-down, or standby condition is guaranteed. Maximum current drain at maximum V SB is ISBB. RAM Control Port RE (RAM Enable), Pin 36 A TTL-compatible RAM enable input that controls the onchip RAM. When placed in the high state, the on-Chip memory is enabled to respond to the MPU controls. In the low state, the RAM is disabled. This pin may also be utilized to disable reading from and writing to the on-Chip RAM during a power-down situation. The RE signal must be low three cycles before Vcc goes below 4.75 V during power-down as shown in Figure 6. Vss (Ground), Pins 1, 21 System ground; 0 V reference. Clock Control The RE signal should be tied low on the F6808; it should be tied to the correct high or low state if not used. E (Enable), Pin 37 This pin supplies the clock for the MPU and the rest of the system. This is a single-phase, TTL-compatible clock and may be conditioned by a memory ready (MR) signal. The E signal is equivalent to <1>2 on the F6800, and is capable of driving one TTL load and 130 pF. CPU Control Outputs BA (Bus Available), Pin 7 Is normally in the low state; when activated, it goes to the high state, indicating that the microprocessor has stopped and that the address bus is available (but not in a 3-state condition). This occurs if the HALT line is in the low state or the processor is in the wait state as a result of execution of a WAIT instruction. At such time, all 3-state output drivers go to their off state and other outputs to their normally inactive levels. The processor Is removed from the wait state by the occurrence of a maskable (mask bit 1 0) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30 pF. EXTAL (External Crystal Connector), Pin 39 XTAL (Crystal Connector), Pin 38 The F6802lF6882 has an internal oscillator that may be crystal controlled. These connections are for a parallelresonant, AT cut, fundamental crystal. (Figure 8 illustrates the crystal speCifications.) A divide-by-four circuit has been added so that a 4 MHz crystal may be used in place of a 1 MHz crystal for a more cost-effective system. An example of the crystal circuit layout on a printed circuit board is shown in Figure 9. = Pin 39 may be driven externally by a TTL-input signal four times the required clock frequency. Pin 38 is to be grounded in this mode. VMA (Valid Memory Address), Pin 5 This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces, such as the PIA and ACIA. This signal is not 3-state. One standard TTL load and 90 pF may be directly driven by this active-high signal. An RC network is not directly usable as a frequency source on pins 38 and 39. An RC network-type TTL or CMOS oscillator works well as long as the TTL or CMOS output drives the on-chip oscillator. 5-63 F6802lF68821F6808 Fig. 8 Crystal Specification Q VI 3.58 MHz C'N 27pF 4MHz 27pF 27pF 6MHz 20pF 20pF 8MHz 18 pF 18 pF 38~O~3~ COUl T Fig. 9 T elN Suggested PC Board Layout EXAMPLE OF BOARD DESIGN USING THE CRYSTAL OSCILLATOR C OUT 27pF OTHER SIGNALS ARE NOT WIRED IN THIS AREA. Crystal Loading YI ---11011-- - -C~ E SIGNAL IS WIRED APART FROM 38 PIN AND 39 PIN. 39 Co ' - - - - - - - 9 38 3.58 MHz 4.0 MHz 6.0 MHz 8.0 MHz Rs 600 500 30-500 20-400 Co 3.5 pF 6.5 pF 4-6 pF 4-6 pF 0.010.02 pF >20K C, 0.015 pF 0.025 pF 0.010.02 pF Q >40K >30K >20K 37 Nominal Crystal Parameters· 'These are representative AT·cut parallel·response crystal parameters only. Crystals of other types of cuts may also be used. LC networks in place of the crystal are not recommended. Fig.10 If an external clock is used, it may be halted for more than $PWOL. The F6802/F6882/F6808 is a dynamic part except for the internal RAM, and requires the external clock to retain information. Memory Ready Synchronization 4xfo OSCILLATOR EXTAL 39 MR (Memory Ready), Pin 3 A TTL·compatible input control signal that allows stretching of the enable (E) signal. Use of MR requires synchronization with the 4xfo signal, as shown in Figure 10. When MR is high, E will be in normal operation. When MR is low, E may be stretched integral multiples of half periods, allowing interface to slow memories or peripherals. A maximum stretch is tCYC; The MR signal should be tied high if not used. Refer to Figure 11 for MR timing information. ~7 F6802 XTAL MR 5·64 ~ 8 A· M 3 B' M ClRB SF 2 , 00 ..... B 11 2 1 43 2 1 53 2 1 2 2 91 3 2 A1 5 2 81 4 2 2 01 3 2 El 2 Fl 4 5 COM 63 7 2 73 6 Oecimal Adlust, A NEG 60 7 2 70 6 3 3 B --> B 50 2 , 00 - 8 - B 19 2 1 Converts Binary Add. of BCD Characters 4A 2 5A 2 1 M - ' ..... M A-'-A B-1 -~ B OAA 7A 6 2 1 3 OECA OEca ExclUSive OR Increment 2 98 3 2 A8 5 2 B8 4 2 08 3 2 Ea 5 2 Fa 4 B (£) M ..... a 6C 7 2 7C 6 M + , ..... M 2 A6 5 2 B6 4 3 M ..... A 2 E6 5 2 F6 4 3 M .... S A+M ..... A 3 INCA LOAB C6 2 Or,lnclusive ORAA 8A229A32AA5 SA4 ORAB CA 2 FA 4 Pull Data 86 2 2 96 2 06 3 2 3 OA 3 2 EA 5 B+1 ..... B PSH8 37 4 1 32 4 1 33 4 1 AOL 69727963 AOR 49 2 1 59 2 1 66727663 RORA 46 2 1 ~ILO 1 j I! 1 1 1 1 b7 - bO b7 ;J bO 2 1 I 1 1 I 1 1 I I 1- 0 2 1 ;J~ 0 - 58 C b7 2 1 2 1 67 7 2 64 7 2 LSA 77 6 74 6 3 3 LSRA 44 2 1 LSR8 54 2 1 b7 j A7 6 B7 5 3 A 07 4 E7 6 F7 5 3 B-M SUBA 8022903 SUBB C022003 Fa 4 3 SBA 82 2 2 92 3 2 A2 5 EO 5 2 B2 4 3 S8CB C2 2 2 02 3 2 E2 5 F2 4 3 -~ I@ 1 @ t @ I@ 0 C t t t 1 1 1 - 0 M • R • A 1 @ t @ 1 1 B-M ..... S A-S ..... A A-M-C ..... A TAB 16 2 1 A-B A TBA 17 2 1 B-A R • R B-M-C .... S • M - 00 A TSTA 40 2 1 A-DO R A TSTB 50 2 1 B -00 R A v C 60727063 Note Accumulator addressing mode instructions are Included In the column for Implied addressing. 5-67 + o 00 Operation code (hexadecimal) Number of MPU cycles Number 01 program bytes Arithmetic plus Arithmetic minus Boolean AND Contents of memory location point to be stack pOinter Boolean Inclusive-OR Boolean exclusive-OR Complement of M Transfer Into Bit = zero Byte = zero t@ 10 2 1 TST Msp M A-M ..... A A052B043 saCA - bO o-~;!!!!! IbJ 97 4 Subtr. with Carry bO ;f~QITITITI-I STAB STAA Subtract Aemltrs Test, Zero """" jJ C 48 57 or Minus ~1L{] - B ASlA 47 Transfer Acmltrs + ® t ® ® t t® t® t ® ® t@ 1 ASLB ASA Subtract OP C ASRa Store Acmltr Legend B ASRA ® ® • B + M .... B A .... MSp. SP - 1 ..... SP 8 ..... MSp. SP - 1 ..... SP SP+l-SP,M Sp -A SP + 1 ..... SP, MSp ..... B 1 Arithmetic Logic 1 2 68727863 ASL Shtft Right, Shift Right, A ®. 56 AORB ArithmetiC A + 1 ..... A , 1 ROlA Shift Left, 1 5C 2 4 PULA II M ..... A 4C 2 36 AOlB Rotate Right A PSHA PUlB Aotate Left 0 2 INCB Push Data , 88 C8 2 lOAA S BCD Format EORa Load Acmhr A tCD@ tCD@ tCD@ 10 00 - A - A EORA INC A A-A 00 - M·- M NEGB 2 R M - M 40 6A 7 R A A - M NEGA DEC A A- B Into Decrement R • B_ M CSA COMS (Negate) OO~M 00 ..... A COMA Complement,2s '~A B· M - B A·M , 81 C A+8~A 4F 2 Cl v A+M+C'~A 3 6F727F63 CMPB Z B+M - B 1 ClRA CMPA N A +M - A 182 And D--::.C,O_D:-ETR.,.EG-,-:I-:-TC_O:-Nr refer to contents) Op - N Z Condition Code Symbols H I N Z V C R S Half-carry from bit 3 Interrupt mask Negative (sign bit) Zero (byte) Overflow. 2's complement Carry from bit 7 Reset always Set always Test and set If true, cleared otherwise Not affected F6802JF6882JF6808 Table 4 Index Register and Stack Manipulation Instructions COND CODE REG DIRECT IMMED POINTER OPERATIONS MNEMONIC INDEX EXTND IMPLIED OP - # OP - # OP - # OP - # BC 3 3 9C 4 2 AC 6 2 BC 5 3 --~- OP - 5 4 3 2 1 0 BOOLEAN/ARITHMETIC OPERATION # XH ~ CPX Decrement Index Reg Decrement Stack Pntr Increment Index Reg DEX 09 4 1 X- 1- X DES 34 4 1 SP - 1 - SP INX DB 4 1 X+ 1- X Increment Stack Pntr INS 31 4 1 SP Load Index Reg LDX CE 3 3 DE 4 2 EE FE 5 3 M - XH, 1M LDS STX BE 3 3 9E DF 4 2 AE 6 6 2 Load Stack Pntr Store Index Reg 2 5 2 EF 7 2 3 3 M 5 BE FF Store Stack Potr STS 9F 5 2 AF 7 2 BF Indx Reg - Stack Pntr TXS Stack Pntr - Indx Reg TSX Table 5 6 6 + 35 30 +', - Xl ,M+ 1 - SPL I 1 X - 1 - SP 4 1 SP X I R .@ I I R CONDo CODE REG. MNEMONIC OP - OPERATIONS Branch Always Branch If Carry Clear Branch If Carry Set Branch If = Zero Branch If '" Zero Branch If > Zero Branch If Higher Branch If S Zero Branch If Lower Or Same Branch If < Zero Branch If Minus Branch If Not Equal Zero Branch If Overflow Clear Branch If Overflow Set Branch If Plus Branch To Subroutine Jump Jump To Subroutine No Operation Return From Interrupt Return From Subroutine Software Interrupt Wait for Interrupt· 'WAI puts address bus, BRA BCC BCS BEQ BGE BGT BHI BLE BLS BLT BMI BNE BVC BVS BPL BSR JMP JSR NOP RTI RTS SWI WAI 20 24 25 27 2C 2E 22 2F 23 20 2B 26 28 29 2A 80 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 # INDEX OP- EXTND # OP - # IMPLIED OP BRANCH TEST # None 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C =0 C= 1 Z=1 N(±)V = 0 Z + ING1VI =0 C+Z=O Z + ING1V' -1 C+Z=1 NG1V = 1 N= 1 Z=O V=O V=1 N=0 BE 4 AD 8 2 7E 3 2 BO 9 } See Special Operations 3 3 01 3B 39 3F 3E 2 10 5 12 9 1 1 1 1 1 RIW, and data bus In the 3·state mode while VMA is held low. 5·68 Advances Prog. Cntr. Only } See Special Operations R • @ Jump and Branch Instructions RELATIVE @. I 4 +1- I I XH - M, XL - 1M + 1 SPH - M, SPL- 1M + 1 3 N Z V C ··· ·· ·· · ·· ·· ·· ·· ·· · ·· ·· ·· • ® ·· ·· • ® ·· ·· ·· ·· ·· ·· ·· 1 - SP -SP~L I .(j) M, XL -~ ~ 200 Implied Addressing In the implied addressing mode, the instructions give the address (Le., stack pOinter, index register, etc.). These are 1-byte instructions. ./" VI-'"" ....- ~ 100 CL includes stray capacitance 100 Relative Addressing In relative addressing, the address contained in the second byte of the instruction is added to the program counter's lowest 8 bits plus two. The carry or borrow is then added to the higher 8 bits. This allows the user to address data within a range of -125 to + 129 bytes of the present instruction. These are 2-byte instructions. 200 300 400 500 600 CL. LOAD CAPACITANCE (pF) Flg.14 Typical Read/Write, VMA and Address Output Delay vs. Capacitive Loading 600 Summary of Cycle-by-Cycle Operation Tab/e 8 provides a detailed description of the information present on the address bus, data bus, valid memory address (VMA) line, and the read/write (R/W) line during each cycle for each instruction. IOH = -145 /-IA max @ 2.4 V IOL = 1.6 rnA max @ 0.4 V Vee = 5.0 V TA = 25°C 500 400 300 This information is useful in comparing actual with expected results during debug of both software and hardware as the control program is executed. The information is categorized according to addressing mode and number of cycles per instruction. (In general, instructions with the same addressing mode and number of cycles execute in the same manner. Exceptions are indicated In the table.) 200 ...- 100 o - ...... .........- ,..., I A:::::1MA ---- ~w CL includes stray capacitance o 100 200 300 400 500 CL. LOAD CAPACITANCE (pF) 5-71 600 • F6802lF68821F6808 Table 8 Operation Summary Address Mode and Instructions Address Bus R/W Line Data Bus Immediate ADC ADD AND BIT CMP EOR LOA ORA SBC SUB CPX LDS LOX 1 2 1 1 Op Code Add ress Op Code Address +1 1 1 Op Code Operand Data 1 2 1 1 1 Op Code Address Op Code Address + 1 Op Code Add ress + 2 1 1 1 Op Code Operand Data (High Order Byte) Operand Data (Low Order Byte \ Op Code Address Op Code Address + 1 Address of Operand 1 1 1 Op Code Address of Operand Operand Data 2 3 3 -- Direct ADC ADD AND BIT CMP EOR LOA ORA SBC SUB CPX LOS LOX 3 3 1 1 1 4 1 2 3 4 1 1 1 1 Op Code Address Op Code Address + 1 Add ress of Operand Operand Address + 1 1 1 1 1 Op Code Address of Operand Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 2 1 1 0 1 1 1 1 Destination Address 3 Op Code Address' Op Code Address + 1 Destination Addtess Destination Address 1 2 STA 4 4 STS STX 5 1 2 3 4 5 1 1 0 1 1 Op Code Address Op Code Address + 1 Address of Operand Address of Operand Address of Operand + 1 1 1 Op Code Address Op Code Address 0 0 0 1 1 1 Op Code Irrelevant Data (Note 1 I Data from Accumulator 0 Op Code Address of Operand Irrelevant Data INote 1 I Register Data (High Order Byte) Register Data (Low Order Byte) Index Register Plus Offset Iw/o Carry I 1 1 1 1 Op Code Olfset Irrelevant Data (Note 1 ) Irrelevant Data (Note 1 I 0 0 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Olfset 1 1 1 1 1 Op Code Offset Irrelevant Data (Note 1 I I rrelevant Data (Note 1 I Operand Data 1 1 0 0 1 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Olfset (w/o Carry) Index Register Plus Offset Index Register Plus Olfset + 1 1 1 1 1 1 1 Op Code Olfset Irrelevant Data (Note 1) Irrelevant Data (Note 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) 0 Indexed 1 JMP 4 ADC ADD AND BIT CMP CPX LOS LOX EOR LOA ORA SBC SUB 5 2 3 4 1 2 3 4 5 1 6 2 3 4 5 6 1 1 +1 I ndex Register 5-72 F6802/F6882/F6808 Table 8 Operation Summary (Cont.) Address Mode and Instructions Address Bus 1 2 STA 6 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 3 4 5 6 1 2 3 7 4 5 6 7 R/W Line Data Bus 1 1 0 0 0 1 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset 1 1 1 1 1 0 Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Operand Data 1 1 0 0 1 0 Op Code Address Op Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Register Plus Offset 1 1 1 1 1 1 0 Op Code Offset Irrelevant Data (Note 1) I rrelevant Data (Note 1) Current Operand Data Irrelevant Data (Note 1) New Operand Data )Note 31 1 1 0 0 0 1 1 Op Code Address Op Code Address + 1 "ndex Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset 1 1 1 1 1 0 0 Op Code Offset I rrelevant Data (Note 1) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) 1 1 0 1 1 0 0 0 Op Code Address Op Code Address + 1 Index Register Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Index Register Plus Offset (w/o Carry 1 1 1 0 0 1 1 1 Op Code Offset Irrelevant Data (Note 1) Return Address (High Order Byte) Return Address (Low Order Byte) Irrelevant Data (Note 1) Irrelevant Dala(Note 1) Irrelevant Dala (Note 1) 1 1 1 Op Code Address Op Code Address Op Code Address +1 +2 1 1 1 Op Code Jump Address (High Order Byte) Jump Address (LLow Order Byte) 1 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand 1 1 1 1 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Operand Data 1 1 1 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand + 1 1 1 1 1 1 Op Code Address of Operand Address of Operand Operand Data (High Operand Data (High 1 1 1 0 1 Op Code Address Op Code Address + Op Code Address + Operand Destination Operand Destination 1 1 1 1 0 Op Code Destination Address (High Order Byte) Destination Address (Low Order Byte) Irrelevant Data (Note 1) Data from Accumulator 1 1 1 1 0 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand 1 1 1 1 1 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Current Operand Data I rrelevant Data (Note 1) New Operand Data (Note 3) 1/0 (Note 3) 1 2 STS STX 3 7 4 5 6 7 1 2 JSR 3 B 4 5 6 7 B Index Register Plus Offset + 1 Index Register Extended JMP 3 1 2 3 ADC ADD AND BIT CMP EOR LOA ORA SBC SUB 1 2 4 3 4 1 2 CPX LOS LOX 5 3 4 5 1 2 STA A STA B 5 3 4 5 ASL ASR CLR COM DEC INC LSR NEG ROL ROR TST 1 2 3 6 4 5 6 1/0 (Note 3) 5-73 1 2 Address Address (High Order Byte) (Low Order Byte) Order Byte) Order Byte) • F6802lF6882/F6808 Table 8 Operation Summary (Cent.) Address Mode and Instructions Address Bus Extended (Continued) R/W Line Data Bus _. 1 1 1 0 1 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Address of Operand Address of Operand Address of Operand + 1 7 8 9 1 1 1 1 1 1 0 0 1 Op Code Address Op Code Address + 1 Op Code Address + 2 Subroutine Starting Ad,dress Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Op Code Address + 2 Op Code Address + 2 1 1 1 1 0 0 1 1 1 Op Code Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte) 00 Code of Next Instruction Aeturn Address (Low Order Byte) Aeturn Address (High Order Byte) Irrelevant Data I Note 11 I rrelevant Data I Note 11 Address of Subroutine (Low Order Byte) 1 2 1 1 Op Code Address Op Code Address +1 1 1 Op Code Op Code of Next Instruction 1 2 1 1 0 0 Op Code Address Add ress +1 New Aegister Contents 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data INote 11 I rrelevant Data I Note 11 1 1 1 0 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer - 1 1 1 0 1 Op Code Op Code of Next Instruction Accumulator Data Accumulator Data 1 1 0 1 Op Code Address Op Code Address Stack Pointer Stack Pointer + 1 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data (Note 11 Operand Data from Stack 3 4 1 1 0 0 Op Code Address Op Code Address + 1 Stack Pointer New Index Aegister 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data (Note 11 Irrelevant Data (Note 11 1 2 1 1 3 4 0 0 Op Code Address Op Code Address + 1 Index Aegister New Stack Pointer 1 1 1 1 Op Code Op Code of Next Instruction Irrelevant Data Irrelevant Data 1 1 1 1 Op Code Irrelevant Data (Note 21 Irrelevant Data (Note 11 Address of Next Instruction (High Order Byte) Address of Next Instruction (Low Order Byte) 1 2 STS STX 6 3 4 5 6 1 2 JSA 3 i 4 9 5 6 1 1 1 '1 0 0 Op Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) I rrelevant Data I Note 11 Operand Data (High Order Byte) Operand Data (Low Order Byte) Inherent ABA ASL ASA CBA CLC CLI CLA CLV COM DES DEX INS INX DAA DEC INC LSA NEG NOP AOL AOA SBA SEC SEI SEV TAB TAP TBA TPA TST 2 4 PSH 4 PUL 4 TSX 4 TXS 4 ATS 5 3 4 1 2 3 4 1 2 3 4 1 2 o p Code Previous Register Contents 1 2 1 1 3 4 0 1 Op Code Address Op Code Address Stack Pointer Stack Pointer + 1 5 1 Stack Pointer +1 +1 +2 1 5-74 F6802/F6882/F6808 Table 8 Operation Summary (Cont.) Address Mode R/W Address Bus and Instructions WAI 9 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer - 1 Stack Pomter - 2 Stack Pointer - 3 Stack Pointer - 4 Stack Pointer - 5 Stack Pointer ~ 6 t Note 4 I 1 1 0 0 0 0 0 0 1 Op Code Op Code of Next Instruction Return Address (Low Order Byte) Return Address (High Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) 8 9 1 1 1 1 1 1 1 1 1 1 2 3 4 1 1 0 1 Op Code Address Op Code Address + 1 Op Code Stack Pointer + 1 1 1 1 1 5 6 7 1 1 1 Stack Pointer + 2 Stack Pointer + 3 Stack Pointer.+ 4 1 1 1 8 1 Stack Pointer + 5 1 9 1 Stack Poi nter + 6 1 10 1 Stack Pointer + 7 1 1 2 3 4 5 6 8 9 10 11 1 1 1 1 1 1 1 1 1 0 1 Op Code Address Op Code Address + 1 Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Stack Pointer - 3 Stack Pointer - 4 Stack Pointer - 5 Stack Pointer - 6 Stack Pointer - 7 Vector Address FFFA 1Hex! 1 1 0 0 0 0 0 0 0 1 1 12 1 Vector Address FFFB (Hex I 1 Contents of Condo Code Register Irrelevant Data INote 11 Address of Subroutine (High Order Byte! Address of Subroutine (Low Order Byte) 1 2 1 1 0 0 Op Code Address Op Code Add ress + 1 Op Code Address + 2 Branch Address 1 1 1 1 Op Code Branch Offset Irrelevant Data I Note 11 Irrelevant Data 1Note 11 1 1 0 1 1 0 0 0 Op Code Address Op Code Address + 1 Return Address of Main Program Stack Pointer Stack Pointer - 1 Stack Pointer - 2 Return Address of Main Program Subroutine Address 1 1 1 0 0 1 1 1 Op Code Branch Offset Irrelevant Data (Note 11 Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (Note 11 Irrelevant Data (Note 11 1 2 3 4 5 6 7 RTI 10 SWI 12 Data Bus Line 7 Stack Pointer Contents of Accumulator A Contents of Accumulator B Contents of Condo Code Register Irrelevant Data INote 21 Irrelevant Data INote 11 Contents of Condo Code Register from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack (Low Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) Op Code Irrelevant Data (Note 11 Return Address (Low Order Byte) Return Address (l'Iigh Order Byte) Index Register (Low Order Byte) Index Register (High Order Byte) Contents of Accumulator A Contents of Accumu lator B Relative BCC BCS BEQ BGE BGT BSR BHI BLE BLS BLT BMI BNE BPL BRA BVC BVS 4 3 4 I 1 2 I1 I 8 3 4 5 6 7 8 Irrelevant Data (Note 1) Notes: 1. If device that Is addressed during this cycle uses VMA, the data bus goes to the high·lmpedance 3·state condition. Depending on bus capacitance, data from the previous cycle may be retained on the data bus. 2. Data Is Ignored by the MPU. 3. For TST, VMA = 0 and operand data does not change. 4. Most significant byte of address bus = most significant byte of address of BSR Instruction, and least significant byte of address bus = least significant byte of subroutine address. 5·75 • F6802lF6882/F6808 DC Characteristics Absolute Maximum Ratings Table 9 contains the dc characteristics of the F6802lF6882. These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Voltage of any Pin Relative to GND - 0.3 V, -55·C, Storage Temperature Power Dissipation 1.5 W Thermal Resistance, fjJA 1W (Plastic Package) 55·C/W (CER-DIP Package) Table 9 DC Characteristics Symbol VIH VIL liN VOH Vee = 5.0 V ± 5%, Vss= 0, TA= 0 to 70°C unless otherwise noted) Characteristic Max - Vee Vee Input Low Voltage LogiC Extal, Reset Vss - 0.3 - Vss+0.8 - 1.0 2.5 Input Leakage Current Logic Output High Voltage Do-D7 Ao-A I5 , R/W, VMA, E SA ~dc Vss + 2.4 Vss + 2.4 Vs s + 2.4 - ILOAD= - 206 ~dc, Vee= Min ILOAD= -145 /tAdc, Vee= Min I LOAD = -100 /tAdc, Vee= Min - - - 4.0 4.75 - 5.25 5.25 Standby Current F6802 F6882 - - 8.0 3.0 CapaCitance Do-D7 Logic Inputs EXtal A o-A I5 , R/W, VMA - 6 - 12.5 10 12 Vee Standby Power Down Power Up VIN = 0 to 5.25 V, Vee= Max Vdc Vss +O.4 1.2 Vsee Vse Condition Vdc 0.600 Power Dissipation Unit Vdc - Output Low Voltage COUT Typ Vss + 2.0 Vss+4.0 Po' CIN Min Input High Voltage Logic EXtal LogiC Reset VOL Isee + 7.0 V +150°C Vdc lLOAD= 1.0 mAdc, Vee= Min W Vdc mA pF *In power-down mode, maximum power dissipation is less than 42 mW. CapaCitances are periodically sampled rather than 100% tested. 5-76 VIN=O, TA=25°C, f=1.0 MHz F6802/F6882/F6808 Timing Characteristics Tables 10 and 11 contain timing characteristics information. Table 10 Frequency Characteristics F6802 Symbol Characteristic Min Max Min F680A02 Max Unit fa Frequency of Operation 0.1 1.0 0.1 1.5 MHz fXTAL Crystal Frequency 1.0 4.0 1.0 1.5 MHz 4xfo External Osci lIator Frequency 0.4 4.0 0.4 6.0 MHz tCYC Cycle Time 1.0 10 0.666 10 lis tpwEH Clock Pulse Width E High 450 9500 280 9700 E Low 450 5000 280 5000 tpWEL ns t R. tF Fall Time - 25 - 25 ns trc Crystal Oscillator Startup Time 100 - 100 - ms Table 11 Read/Write Timing --,--~--- F6802 Symbol Characteristic Min Max F680A02 Min Max Unit tAO Address Delay - 270 - 220 ns t AV1 t Av2 Address Delay (Internal RAM Read Access Time Useable by Peripheral @ 1 MHz tACC tCYC - tAO + tOSR + tF - 270 605 - 240 310 ns - tOSR Data Setup Time (Read) 100 - 70 - ns tOHR Input Data Hold Time 10 - 10 - ns = .~ tOHW Output Data Hold Time 30 - 20 - ns tAH Address Hold Time (Address, RIW, VMA) 20 - 20 - ns to OW Data Delay Time (Write) - - 170 ns tpcs tpCR, tpCF Processor Controls Processor Control Setup Time Processor Control Rise and Fall Time (Does Not Apply to RESET) (Measured between 0.8 V and 2.0 V) 200 - 225 - 140 - 100 - 100 ns Note If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on~board RAM. this extended delay does not apply~ Programs cannot be executed from One·board RAM can be used for data storage with all parts. 5·77 on~board RAM when using A parts (F68A02. F68A08)~ • F6802/F6882/F6808 Bus Timing Characteristics Symbol F6802NS F6802 F6808 Min Max Parameter F68A02 F68A08 Min Max Unit tCYC CD Cycle Time 1.0 10 0.667 10 I'S PW EL 0pulse Width, E Low 450 5000 280 5000 ns PWEH 0Pulse Width, E' High 450 9500 280 9700 ns tro t f 0CIOCk Rise and Fall Time - 25 - 25 ns tAH ®Address Hold Time 20 - 20 ns tAV1 tAV2 @Non.Muxed Address Valid Time to E 160 - 100 - 270 - tosR @Read Data Setup Time 100 70 tOHR @Read Data Hold Time 10 - 10 - to ow @Write Data Delay Time - 225 - 170 ns tOHW @Wrote Data Hold Time 30 - 20 ns tACC @usable Access Time (See Note 4) 605 - 310 - R/W ADDRESS (NON·MUXED) _ _-+-~ READ DATA NON·MUXED _ _-+-_~ WRITE DATA NON·MUXED ---~ Notes 1. Voltage levels shown are VL ", 0.4 V. VH "2.4 V, unless otherwise specified. 2. Measurement pOints shown are 0.8 V and 2.0 V, unless otherwise noted. 3. All electricals shown for the F6802 apply to the F6802NS and F680S, unless otherwise noted. 4. Usable access time is computed by 12+3+4-17. 22 5-78 ns ns ns ns F6802/F6882/F6808 Fig. 15 Read Data from Memory or Peripherals vIH'd+----E VIL JI--....,.--------~I t, VMA _ _I-_~~ - - - - -.. ~I ...... tDSA ....... DATAFROM __~_ _ _ _ _ _ _ _ _ _ _ _ _-;~~~~:J~~~~~ MEMORY OR PERIPHERALS 0.8 V ~ DATA NOT VALID Note Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. Fig. 16 Write Data In Memory or Peripherals E ADDRESS FROM MPU -t____ DATA ________________________ ~~~ __ ~~~~~~ FROM MPU _ _ DATA NOT VALID Note Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. Fig. 17 Bus Timing Test Load 4.75V C = 130 pF FOR 0 0 -07 , E = 90 pF FOR A,,-A .., R/W, AND VMA = 30 pF FOR BA R = 11.7 kll FOR 0 0 -07 , E = 16.5 kll FOR A,,-A,., R/W, AND VMA = 24 kll FOR BA TEST POINT o-~-1r--I~-1 c MMD8150 OR EQUIV. R MMD7000 OR EQUIV. 5-79 F6802/F6882/F6808 Ordering Information Order Code Speed Temperature Range F6802P, S F6882P,S 1.0 MHz 1.0 MHz O·Cto +70·C O·C to + 70·C - 40·C to + 85·C F6802CP, CS 1.0 MHz F68A02P,S 1.5 MHz O·C to + 70·C F68A02CP, CS 1.5 MHz - 40·C to + 85·C P = Plastic package S = Ceramic package 5·80 F6809/F68A09/F68B09 FAIRCHILD Central Processing Unit A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The Fairchild F6809 8-bit Microprocessor is an advanced, high-performance member of the F6800 family_ It offers greater throughput, improved byte efficiency, and increased adaptability to various software disciplines, including position-independent code, re-entrancy, recursion, block structuring, and high-level language generation. The F6809 is compatible with ali F6800 peripheral devices and is upward source code compatible with F6800-series microprocessors. The device is available in three frequency ranges: 1.0 MHz (F6809), 1.5 MHz (F68A09), and 2.0 MHz (F68B09). Architectural improvements, such as additional 16-bit registers and dual 8-bit data paths, allow for powerful enhancements to the instruction set and addressing capabi Iities. • • • • • • • • • • • • • • • • • • • • Compatible with Entire F6800 Family -Hardware Interfaces with all F6800 Peripherals -Software Has Upward-Compatible Instruction Set and Addressing Modes Two 16-Bit Index Registers Two Indexable 16-Blt Stack Pointers Two 8-Bit Accumulators Can Be Concatenated to Form One 16-Bit Accumulator Direct Page Register Allows Direct Addressing Throughout Memory Map Single + 5 V Supply On-Chip Oscillator MRDY Input Extends Data Access Time for Use with Slow Memory DMA/BREQ Allows Access to Bus for DMA and Memory Refresh Fast Interrupt Request (FIRQ) Stacks Only Program Counter and Condition Code Register Interrupt Acknowledge Output Allows Vectoring by Device Sync Acknowledge Output Allows for Synchronization to External Event 16-Bit Arithmetic (ADD, SUBTRACT, COMPARE, LOAD, STORE) 8 x 8 Unsigned Multiply Transfer/Exchange all Registers Push/Pull all Registers Ten Addressing Modes Expanded Indexed Addressing, Accumulator or up to 16-Bit Offset, Auto-Increment/Decrement by One or Two True Indirect Addressing Load-Effective Address (Top View) 5-81 F6809/F68A09/F68B09 Block Diagram ",--Vcc ""'-Vss DMA/BREQ R/W RA[T BA BS XTAL EXTAL MRDY L-_ _ 5·82 E ~Q A Schlumberger Company F6809E/F68A09E/F68B09E Central Processing Unit Advance Product Information Microprocessor Product Description Connection Diagram P=AIACHILD The Fairchild F6809E 8-bit microprocessor is an advanced, high-performance member of the F6800 family. It offers greater throughput, improved byte efficiency, and Increased adjustability to various software disciplines, including position-independent code, re-entrancy, recursion, block structuring, and high-level language generation. The F6809E Is compatible with all F6800 peripheral devices and Is upward source code compatible with F6800-series microprocessors. It is available in three frequency ranges: 1.0 MHz (F6809E); 1.5 MHz (F68A09E); 2.0 MHz (F68B09E). Vss iiAif NMI TSC IRO LlC FIRO Architectural improvements, such as additional 16-bit registers and dual 8-bit data paths, allow for powerful enhancements to the Instruction set and addressing capabilities. External clock inputs are provided on the F6809E to allow synchronization with peripherals, systems, or other MPUs. AVMA BA 0 Vee E Ao BUSY A, MY A, Do A, D, '" 0, A. • Compatible with Entire F6800 Family - Hardware Interfaces with ~II F6800 Peripherals • Software Has Upward-Compatible Instruction Set and Addressing Modes • Two 16-Bit Index Registers • Two Indexable 16-Blt Stack Registers • Two 6-blt Accumulators Can Be Connected to Form One 16-Bit Accumulator • Direct Page Register Allows Direct Addressing Throughout Memory Map • External E and Q Clock Inputs Allow Synchronization • TSC Input Controls Internal Bus Buffers • LlC Output Indicates Opcode Fetch • AVMA Output Allows Efficient Use of Common Resources In a Multiprocessor System • Fast ",terrupt Request Input Stacks Only Program Counter and Condition Code Register • Interrupt Acknowledge Output Allows Vectoring by Device • Sync Acknowledge Output Allows for Synchronization to External Event • Single Bus-Cycle Reset • Single + 5 V Supply • Early Address Valid Allows Use with Slower Memories • Early Write-Data for Dynamic Memories • 10 Addressing Modes • True Indirect Addressing • Expanded Indexed Addressing • 1484 Instructions with Unique Addressing Modes • Recognizes 6x8 Unsigned Multiply • 16-BIt Arithmetic 5-83 RES BS Do At; D. A, D. At D• At 0, A,. A,. A" A,. A" A13 F6809E1F68A09E1F68B09E Table 1 DC Characteristics F6809E Symbol Characteristic VIH VIHR VI He Input High Voltage VIL VILe liN VOH Input I,.ow Voltage Input Leakage Current Output High Voltage Min Typ Logic, Q 2.2 RES 4.0 - F68A09E Max Min Typ Vce 2.2 Vee 4.0 - F68B09E Max Min Typ Vee 2.2 Vee 4.0 Max Unit - Vee V - Vee V Vee +0.3 V 0.8 V 0.4 V - E Vee -0.75 Logic a, RES -0.2 - 0.8 -0.2 - 0.8 -0.2 E -0.3 - 0.4 -0.3 -0.3 ~ca, - 2.5 -2.5 - 0.4 -2.5 2.5 -2.5 - 2.5 pA -100 Vee Vee +0.3 -0.75 Vee Vee +0.3 -0.75 - RES -100 - 100 -100 pA - - 2.4 - 2.4 - 100 2.4 - 100 0 0.01 - V Ao·A 15, R/W 2.4 - - 2.4 - - 2.4 - - V BA, BS, L1C, AVMA, BUSY 2.4 - - 2.4 - - 2.4 - - V E VOL Output Low Voltage - - 0.5 - - 0.5 - - 0.5 V Po Power Dissipation - - 1.0 1.0 1.0 W 10 15 10 15 - - - - - 10 15 pF CIN 0 0.07 , Logic Input Input, a, Capacitance RES COUT Output Ao·A 15 , R/W, Capacitance BA, BS, L1C, AVMA, BUSY - 30 50 50 - 30 50 pF 15 - 30 10 10 15 - 10 15 pF 0.1 - 1.0 0.1 - 1.5 0.1 - 2.0 MHz 0 0.07 -10 -10 - 10 -10 - 10 pA -100 - 10 Ao·A 15 , R/W 100 -100 - 100 -100 - 100 pA E F ITSI Vee Frequency of Operation (E,a) Three-State (Off State) Input Current = 5.0 V ± 5 %; V55 = 0 V; TA = - 20·C - + 70 ·C, unless otherwise noted. 5·84 Test Conditions , VIN Vee = 0 - 5.25 V; = Max = - 205 pA = Min ILOAD = -145 pA Vee = Min ILOAD = - 100 pA Vee = Min ILOAD = 2 mA; Vee = Min ILOAD Vee = 0 V; = 25·C; = 1 MHz YiN = 0 V; TA = 25"C; F = 1 MHz VIN TA F VIN Vee = 0.4 - 2.4 V = Max F6809E1F68A09E/F68B09E Functional Description Addressing Modes During normal operation, the F6809E fetches an instruction from memory and executes the requested function. This sequence begins following a Reset (REs) input and is repeated indefinitely unless altered by a special instruction or hardware occurence. Software instructions that alter normal operation are: SWI, SWI2, SWI3, CWAI, RTI, and SYNC. An Interrupt or HALT input can modify normal instruction execution. The F6809E has 59 basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes available on the F6809E are: 1. 2. 3. 4. 5. 6. 7. Implied (includes accumulator) Immediate Extended Extended indirect Direct Register Indexed a. Zero-offset b. Constant offset c. Accumulator offset d. Auto increment/decrement 8. Indexed indirect 9. Relative 10. Program counter relative Instruction Set The instruction set of the F6809E is similar to that of the F6800 and is upward-compatible at the source code level. The number of opcodes has been reduced to 59 but, because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) is 1464. Some of the new instructions are: 1. PSH6/PSH5, which are push instructions that have the capability of pushing onto either the user stack (U) or hardware stack (S) any register or set of registers with a single instruction. DC Characteristics Table 1 describes the dc characteristics of the F6809E. Absolute Maximum Ratings 2. PUL6/PUL5, which are pull instructions having the same capabilities as the push instructions, in reverse order. These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this document, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. 3. TFRlEXG, which allow any register to be transferred to or exchanged with another register of like size. 4. LEAXlLEAY/LEAU/LEAS, which calculate the effective address used in an indexed instruction and store that effective value, rather than the data at that address, in a pOinter register. Storage Temperature Range Operating Temperature Range Vce Input Voltage 5. MUL, which multiplies the unsigned binary numbers in the A and B accumulators and places the unsigned result into the 16-bit D accumulator. 5-85 - 55·C, + 150·C - 20·C, + 75·C -0.3V, +7.0V -0.3V, +7.0V F6809E1F68A09E1F68B09E Block Diagram _----VCC -----vss .------iiEs ..-____ NMi" FIRQ .-----~LlC r - - - -.. AVMA . - -......~R/W TSC HALT BA I..-----<~BS 1..-_ _ _ _. . BUSY "t..._ _ _ _ _ E '-------Q 5·86 F681 O/F68A 1O/F68B 10 128 X 8-Bit Static Random Access Memory FAIRCHILD A Schlumberger Company Microprocessor Product Description The F6810 128 x 8-bit static RAM is a byte-organized memory designed for use in bus-organized systems. Fabricated with n-channel, silicon-gate technology, the device is available in three frequency ranges: 1.0 MHz (F681 0), 1.5 MHz (F68A10), 2.0 MHz (F68B10). The device, which operates from asingle power supply, is compatible with TTL and DTL; it needs no clocks or refreshing because of its static operation. Logic Symbol 10 The memory is compatible with the F6800 microcomputer family, providing random storage in byte increments. Memory expansion is provided through multiple chip select inputs. Organized as 128 Bytes of 8 Bits Static Operation Bidirectional 3-State Data Input/Output Six Chip Select Inputs (Four Active LOW, Two Active HIGH) • Single + 5 V Power Supply • TTL-Compatible • Maximum Access Time: 450 ns for F6810 . 360 ns for F68A 10 250 ns for F68B10 23 Ao 22 A, 21 A, 20 Ao 19 A. 18 As 11 Ai 11 12 13 14 F8Bl0 • • • • 2345878 vcc = Pin 24 VSS = Pin 1 Connection Diagram 24·Pin DIP Vee Vss Pin Names 00-07 Ao-A6 CSO-CS5 Rm 15 AO Do Bidirectional Data Bus Address Inputs Chip Select inputs Read/Write Input A, 0, A, Do A3 Os As O. As 07 R/W CSo CSs CS1 CS.· C!12 CS3 '-------', (Top View) 5-87 18 F681 O/F68A1 O/F68B10 Block Diagram Qo • Ai D. MEMORY MATRIX (121_11 Ar ADDRESS DECODE AS 3-STATE BUFFER • • D3 0. Ds Do • D, to.. .... I U- MEMORY CONTIIOL !w to.. .... Signal Function Descriptions Mnemonic Pin No. Bus Handshake 11~23 Ao-A6 00-07 Chip Control CSO-Cs5 RiW 2-9 Description Address Input signal lines con· taining address to Bus which data is to be written or from which data is to be read Data Bus Chip Select Input signal lines that prepare the device for a read or write operation 16 Readl Write Input signal lines that selects a chip rElad or write operation; a HIGH selects memory read, and a LOW selects memory write Supply O·C, + 70·C -40·C, +85·C -55·C, +125·C - 65·C, + l50·C 82.5·CIW These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the abSOlute maximum rating conditions for extended p$rlods of time may affeot device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Recommended Operating Conditions Symbol Gtound Ground for supply and signals 24 -0.3 V, + 7.0 V -0.3 V, + 7.0 V This device conlains circuitry to protect the inputs againsl damage due 10 high static vOllages or electric fields; however, It is advised that normal precautions be taken to avoid application of any vollage higher than maximum rated voltages. Bidirectional inputl output signal lines over which data is read from or written to the device 10-15 Supply Vss Vee Name Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature - TL, TH F68l0, F68Al0, F68Bl0 F68l0C, F68Al0C F6810DM Storage Temperature Range Thermal Resistance - ()JA + 5 V supply voltage 5·88 Characteristic Min Typ Max Unit 4.75 5.0 Vee Supply Voltage 5.25 V VIH Input HIGH Voltage 2.0 5.25 V VIL Input LOW Voltage -0.3 0.8 V F681O/F68A10/F68810 DC Characteristics Vee = 5.0 V ±5%, Vss = 0, TA = TL to TH, unless otherwise noted. Symbol Characteristic liN Input Current (An, R/W, CSn, CSn) VOH Output HIGH Voltage VOL Output LOW Voltage ILO Output Leakage Current, 3·State lee' Supply Current CIN Input Capacitance COUT Output Capacitance Typ Min Max Unit Conditions 2.5 I'A = 0 to 5.25 V = -2051'A IOL = 1.6 rnA CS = 0.8 V or CS = 2.0 V, Va = 0.4 V to 2.4 V Vee = 5.25 V, all other pins grounded, TA = O°C f = 1.0 MHz, TA = 25°C 2.4 VIN V F6810 F68A10, F68B10 10H 0.4 V 10 I'A 80 100 mA 7.5 pF 12.5 pF Bus Timing Characteristics Vee = 5.0 V ±5%, Vss = 0, TA = TL to TH, unless otherwise noted. Symbol Unit Characteristic Read (Figure 1) teye(R) Read Cycle Time taee Access Time tAS Address Set·up Time tAH Address Hold Time tOOR Data Delay Time (Read) tRes Read-to·Select Delay Time tOHA tH 450 360 450 20 0 ns 250 250 360 ns 20 20 ns 0 0 ns 180 220 230 ns 0 0 0 ns Data Hold from Address 10 10 10 ns Output Hold Time 10 10 10 ns tOHR Data Hold from Read 10 tRH Read Hold from Chip Select 80 10 60 10 60 ns 0 0 0 ns 450 360 250 ns 20 20 20 ns 0 0 0 ns 300 250 210 ns Write (Figure 2) teye(W) Write Cycle Time tAS Address Set-up Time tAH Address Hold Time tes Chip Select Pulse Width twes Write·to·Chip Select Delay Time tosw Data Set·up Time (Write) tH Input Hold Time tWH Write Hold from Chip Select 0 0 0 ns 190 80 60 ns 10 10 10 ns 0 0 0 ns 5·89 F681 O/F68A1O/F68B1 0 Fig. 1 Read Cycle Timing I~_ - .- - - - - t a c c tcyc(R) . 2.0 V AODRESS 0.8 v I--IOH- 2.0V cs cs 0.8 V 2.0 V - IRH 1_ 0.8 V 2.0 v RiW 2.4 V DATA DUT--------__---------------( 0.4 V Don'l Care NOle CS and Cs can be enabled for consecutive read cycles, provided RiW' remains at VIH. 5·90 F681 O/F68A1O/F68B1 0 Fig. 2 Write Cycle Timing 1.. · f - - - - - - - - - - - - - t ,..(W)------------~1 ADDRE~~D~~~~D:~ 1-:~1sr.. ~~~------------ t-- ______________________________________________ ,~ IL.------------------- cs--------~~---------~~~~g i cs--------=~"'.,.,_:"1'1"""" _ _1]~~81~D.av-~1-." ~ aLav l I/IIIIIIIIIIA .1 RtW 1...0 - - - - - DATAIN~:.:: losw DATA IN STABLE tH ]...- ~"'"' ............~............~ Not. es and Cs can be enabled lor consecutive write cycles, provided AIW is strobed to VIH belore or coincident with the address change, and remains HIGH lor time tAS. Timing Conditions The conditions under which the timing characteristics have been determined are as follows: Fig. 3 Output Load ........ -...-KIH~Wv-- 5.DV Input Pulse Levels Input Rise and Fall Times Output Load Vee Vss 130pF· TA 0.8 V to 2.0 V 20 ns See Figure 3 5.0 V ±5% o TL to TH, unless otherwise noted 'Includes jig capacitance 5·91 • F681 O/F68A1O/F68B1 0 Ordering Information Speed 1.0 MHz 1.5 MHz 2.0 MHz P Order Code Temperature Ranae F6810P,S O·C to 70·e F6810CP,eS - 40·e to + 85·e F6810DM - 55·e to + 125·e F68A10P,S o·e to + 70·e F68A10epeS - 40·e to + 85·e F68B10DM - 55·e to + 125·e F68B10P S o·e to + 70·e = Plastic package, S = Ceramic package 5·92 F6820 Peripheral Interface Adapter (PIA) F=AIRCHILD A Schlumberger Company Microprocessor Product Logic Symbol Description TheF6820· Peripheral Interface Adapter (PIA) provides the universal means of interfacing peripheral equipment to the F6800 Microprocessing Unit (MPU). This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. 2 3 4 5 6 7 8 9 10 11 • 8-Bit Bidirectional Data Bus for Communication with the MPU • Two Bidirectional 8-Bit Buses for Interface to Peripherals • Two Programmable Control Registers • Two Programmable Data Direction Registers • Four Individually Controlled Interrupt Input Lines, Two Usable as Peripheral Control Outputs • Handshake Control Logic for Input and Output Peripheral Operation • High-Impedance 3-State and Direct Transistor Drive Peripheral Lines • Program-Controlled Interrupt and Interrupt Disable Capability • CMOS Drive Capability on Side A Peripheral Lines 35 RS, 22 CSO 24 (VMA)CS, 23 CS2 25 E 21 RIW 40 CA, 39 CA2 18 CB, 19 CB2 34 RESET F6820 Vec = Pin 20 Vss = Pin 1 33 32 31 30 29 28 27 26 Connection Diagram 40-Pin DIP vss PAn PA, PA2 PA, PA4 Pin Names RiW RESET CA1, CB1 CA2, CB2 15 16 17 36 The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of the interface. Do-Dr PAo-PAr PBo-PBr CSo, CS1, CS2 RSo, RS1 E 12 13 14 PAs Bidirectional Data Bus Bidirectional Peripheral Data Bus A Bidirectional Peripheral Data Bus B Chip Select Inputs Register Select Inputs Enable Input Read/Write Input Reset Input Interrupt Control Inputs Programmable Interrupt Control Input or Peripheral Control Output Interrupt Request Outputs PAs PA, PB. PB, PB2 PB, 13 PB4 14 PBs 15 PB6 16 PB, 17 CB, 18 CB, 19 Vee 20 (Top View) • Not recommended for new designs. 5-93 IROA 38 IROB 37 • F6820 Block Diagram IROA • INTERRUPT STATUS CONTROL A I-CA' _CA:! 00_ 0,- DATA DIRECTION REGISTER A (DORA) 0203- 0.- DATA BUS BUFFERS (DBB) D._ O._PAo 0,- ....-. PA1 -PA:! BUS INPUT REGISTER (BIR) PERIPHERAL INTERFACE A (/) ........ PA3 ....--. PA4 ~PA5 ::> ...::> III .. -PAs ......... PA7 ;!; ...... PBo .......... PB1 .-.... PB2 PERIPHERAL INTERFACE B CSO _ _ CS1~ RS1 -----.. Riw _ _ ......-. P84 ........... PBs CS2 ______ RSo-- .....-.. PS3 CHIP SELECT AND RiW CONTROL . - . . PBe .......... PB7 ENABLE _ _ RESET _ _ DATA 01 RECTION REGISTER B (DDRS) -I IROB • 5·94 INTERRUPT STATUS CONTROL B I-CBl ~CB2 F6820 F6820 PIA Bus Interface ~CA'\ t r- r------....l....-''-, A DATA DATA DIRECTION REG A CA, A I CONTROLS 1~ DtTA J~NTERFACE CONTROL REG A B DATA DATA DIRECTION REG B l~ D:TA J~NTERFACE CONTROL REG B Vcc~ --,--,...J VSS - I -_ _ _ _ _ DATA ADDRESS BUS BUS BUS CONTROL Functional Description t4 -CB'l B CB, CONTROLS PIA Read/Write (RNi), Pin 21 - This signal is generated by the MPU to control the direction of data transfers on the data bus. A LOW on the PIA read/write line enables the input buffers, and data is transferred from the MPU to the PIA on the E signal if the device has been selected. A HIGH on the read/write line sets up the PIA for a transfer of data to the bus. The PIA output buffers are enabled when the proper address and the E pulse are present. PIA Interface Signals for MPU The PIA interfaces to the F6800 MPU with an 8-bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line, and a reset line. These signals, in conjunction with the F6800 VMA output, permit the MPU to have complete control over the PIA. The VMA signal should be utilized in conjunction with an MPU address line into a chip select of the PIA. RESET, Pin 34 - The active·LOW RESET line is used to reset all register bits in the PIA to a logic 0 (LOW). This line can be used as a power-on reset and as a master reset during system operation. PIA Bidirectional Data (00.07), Pins 26·33 - The bidirectional data lines (00.07) allow the transfer of data between the MPU and the PIA. The data bus output drivers are 3·state devices that remain in the highimpedance (OFF) state except when the MPU performs a PIA read operation. The read/write line is in the read (HIGH) state when the PIA is selected for a read operation. PIA Chip Select (CSo, CS1, and CS2), Pins 22·24 - These three input signals are used to select the PIA. eso and eS1 must be HIGH and eS2 must be LOW for selection of the device. Data transfers are then performed under the control of the enable and read/write signals. The chip select lines must be stable for the duration of the E pulse. The device is "deselected" when any of the chip selects are in the inactive state. PIA Enable (E), Pin 25 - The enable (E) pulse is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading and trailing edges of the E pulse. This signal is normally a derivative of the F6800 <1>2 clock. PIA Register Select (RSo and RS1), Pins 35, 36 - The two register select lines are used to select the various registers inside the PIA. These two lines are used in conjunction with internal control registers to select a particular register that is to be written to or read. 5·95 F6820 The data in output register A appears on the data lines that are programmed to be outputs. A logic "1" written into the register causes a HIGH on the corresponding data line, while a "0" results in a LOW. Data in output register A may be read by an MPU read peripheral data A operation when the corresponding lines are programmed as outputs. This data is read properly if the voltage on the peripheral data lines is greater than 2.0 V for a logic "1" output and less than 0.8 V for a logic "0" output. Loading the output lines so that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a read operation to differ from that contained in the respective bit of output register A. The register and chip select lines should be stable for the duration of the E pulse while in the read or write cycle. Interrupt Request (lROA and IROB), Pins 37, 38 - The active-LOW interrupt request lines act to interrupt the MPU either directly or through interrupt priority circuitry. These lines are open drain (no-load· device on the chip). This permits all interrupt request lines to be tied together in a wired-OR configuration. Each interrupt request line has two internal interrupt flag bits that can cause either line to go LOW. Each flag bit is associated with a particular peripheral interrupt line. Also four interrupt enable bits are provided in the PIA that are used to inhibit a particular interrupt from a peripheral device. Section B Peripheral Data (PBo-PB7), Pins 10-17 - The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or outputs in a similar manner to PAo-PA7. However, the output buffers driving these lines differ from those driving lines PAo-PA7. They have 3-state capability, allowing them to enter a high-impedance state when the peripheral data line is used as an input. In addition, data on the peripheral data lines PBo-PB7 is read properly from those lines programmed as outputs even if the voltages are below 2.0 V for a HIGH. As outputs, these lines are compatible with standard TTL and may also be used as a source of up to 1 mA at 1.5 V to drive the base of a transistor switch directly. Servicing an interrupt by the MPU is accomplished by a software routine that, on a priority basis, sequentially reads and tests the two control registers in each PIA for interrupt flag bits that are set. The interrupt flags are cleared (set to 0) as a result of an MPU read peripheral data operation of the corresponding data register. After being cleared, the interrupt flag bit cannot be enabled until the PIA is "deselected"during an E pulse. The E pulse is used to condition the interrupt control lines (CA1, CA2, CB1, CB2). When these lines are used as interrupt inputs, at least one E pulse must occur from the inactive edge to the active edge of the interrupt input signal to condition the edge sense network. If the interrupt flag has been enabled and the edge sense circuit has been properly conditioned, the interrupt flag is set on the next active transition of the interrupt input pin. Interrupt Input (CA1 and CB1), Pins 18,40 - Interrupt input lines CA1 and CB1 are input-only lines that set the interrupt flags of the control registers. The active transition for these signals is also programmed by the two control registers. Peripheral Control (CA2), Pin 39 - The peripheral control line CA2 can be programmed to act as an interrupt.input or as a peripheral control output. As an output, this line is compatible with standard TTL; as an input, the internal pull-up resistor on this line represents one standard TTL load. The function of this signal line is programmed with control register A. PIA/Peripheral Interface Lines The PIA provides two 8-bit bidirectional data buses and four interrupt/control lines for interfacing to peripheral devices_ Section A Peripheral Data (PAo-PA7), Pins 2-9 - Each of the peripheral data lines is programmed to act as an input or output. This is accomplished by setting a "1" in the corresponding data direction register bit for those lines which are to be outputs. A "0" in a bit of the data direction register causes the corresponding peripheral data line to act as an input. During an MPU read peripheral data operation, the data on peripheral data lines programmed to act as inputs appears directly on the corresponding MPU data bus lines. In the input mode, the internal pull-up resistor on these lines represents a maximum of one standard TTL load. Peripheral Control (CB2), Pin 19 - Peripheral control line CB2 may also be programmed to act as an interrupt input or peripheral control output. As an input, this line has high input impedance and is compatible with standard TTL. As an output, it is compatible with standard TTL and may also be used as a source of up to 5-96 F6820 1 mA at 1.5 V to drive the base of a transistor switch directly. This line is programmed by control register B. Control Registers (CRA and CRB) The two control registers (CRA and CRB) allow the MPU to control the operation of the four peripheral control lines CA1, CA2, CB1 and CB2. In addition, they allow the MPU to enable the interrupt lines and monitor the status of the interrupt flags. Bits a through 5 of the two registers are written or read by the MPU when the proper chip select and register select signals are applied. Bits 6 and 7 of the two registers are read only and are modified by external interrupts occurring on control lines CA1, CA2, CB1 or CB2. The format of the control words is shown in Table 2. Note II is recommended Ihat Ihe control lines (CA1. CA2, CBt, CB2) should be held in a logic "1" state when RESET is active to prevent setting of corresponding interrupt flags in the control register when RESET goes to an inactive state. Subsequent to RESET going inactive, a read of the data registers may be used to clear any undesired interrupt flags. Internal Controls There are six locations within the PIA accessible to the MPU data bus: two peripheral registers, two data direction registers, and two control registers. Selection of these locations is controlled by the RSo and RS1 inputs together with bit 2 in the control register, as shown in Table 1. Table 1 Table 2 Bit CRB IROA1 IROB1 5 IROA2 IROB2 CA2 Control CB2 Control Location Selected 5 4 3 DDRA Access DDRB Access CA1 Control CB1 Control Control Register Bit RS1 RSo CRA·2 a a a a a 1 X Peripheral Register A 2 a x Data Direction Register A 1 X Control Register A 1 a a 1 Peripheral Register B ° 1 x x x a Data Direction Register B 1 1 X X Control Register B 1 CRA ? Internal Addressing CRB·2 Control Word Format Data Direction Access Control Bit (CRA·2 and CRB·2) Bit 2 in each control register (CRA and CRB) allows selection of either a peripheral interface register or the data diJection register when the proper register select signals are applied to RSo and RS1. x = Don'l Care Initialization A LOW RESET line has the effect of zeroing all PIA registers. This sets PAo·PA7, PBo·PB7, CA2 and CB2 as inputs, with all interrupts disabled. The PIA must be configured during the restart program which follows the reset. Interrupt Flags (CRA·S, CRA·7, CRB·S, and CRB·?) - The four interrupt flag bits are set by active transitions of signals on the four interrupt and peripheral control lines when those lines are programmed to be inputs. These bits cannot be set directly from the MPU data bus and are reset indirectly by a read peripheral data operation on the appropriate section. Possible configurations of the data direction and control registers are as follows. Control of CA1 and CB1 Interrupt Input Lines (CRA·O, CRB·O, CRA·1, and CRB·1) - The two lowest order bits of the control registers are used to control the interrupt input lines CA1 and CB1. Bits CRA·O and CRB-O are used to enable the MPU interrupt signals IROA and IROB, respectively. Bits CRA-1 and CRB·1 determine the active transition of the interrupt input signals CA1 and CB1 (see Table 3). Data Direction Registers (DDRA and DDRB) The two data direction registers allow the MPU to control the direction of data through each corresponding peripheral data line. A data direction register bit set at "0" configures the corresponding peripheral data line as an input; a "1" results in an output. 5-97 F6820 Control of CA2 and CB2 Peripheral Control Lines (CRA·3, CRA·4, CRA·S, CRB·3, CRB·4 and CRB·S) - Bits 3, 4 and 5 of the two control registers are used to control the CA2 and CB2 peripheral control lines. These bits determine if the control lines will be an interrupt input or an output control signal. If bit CRA·5 (CRB·5) is LOW, CA2 (CB2) is an interrupt input line similar to CAl (CB1) (see Table 4). When CRA·5 (CRB·5) is HIGH, CA2'(CB2) becomes an out· put signal that may be used to control peripheral data transfers. When in the output mode, CA2 and CB2 have slightly different characteristics (see Tables 5 and 6). Table 3 Control of Interrupt Inputs CAl and CBl CRA·1 (CRB·1) CRA·O (CRB·O) Interrupt Input CAl (CB1) Interrupt Flag CRA·7 (CRB·7) MPU Interrupt Request IRaA (IRaB) 0 0 I Active Set HIGH on I of CAl (CB1) Disabled HIGH 0 1 I Active Set HIGH on I of CAl (CB1) Goes LOW when the interrupt flag bit CRA·7 (CRB·7) goes HIGH 1 0 f Active Set HIGH on f of CAl (CB1) Disabled HIGH 1 1 f Active Set HIGH on f of CAl (CB1) Goes LOW when the interrupt flag bit CRA·7 (CRB·7) goes HIGH IROA (IROBI remains IROA (lROB) remains NOle. 1. I indicates positive transition (LOW·to·HIGH) 2. I indicates negative transition (HIGH·to·LOW) 3. The interrupt flag bit CRA-7 is cleared by an MPU read of the A data register, and CRB-7 is cleared by an MPU read of the B data register. 4. If CRA-O (CRB-O) is LOW when an interrupt occurs (interrupt disabled) and is later brought HIGH, iRQA (I ROB) occurs after CRA-O (CRB-O) is written to a "1 ". Table 4 Control of CA2 and CB2 as Interrupt Inputs CRA·S (CRB·S) CRA·4 (CRB·4) CRA·3 (CRB·3) Interrupt Input CA2 (CB2) Interrupt Flag CRA·6 (CRB·6) 0 0 0 I Active Set HIGH on I of CA2 (CB2) Disabled HIGH 0 0 1 I Active Set HIGH on I of CA2 (CB2) Goes LOW when the interrupt flag bit CRA·6 (CRB·6) goes HIGH 0 1 0 f Active Set HIGH on f of CA2 (CB2) Disabled HIGH 0 1 1 ·1 Active Set HIGH on f of CA2 (CB2) Goes LOW when the interrupt flag bit CRA·6 (CRB·6) goes HIGH Noles 1. I indicates positive transition (LOW-ta-HIGH) 2. I indicates negative transition (HIGH·to·LOW) 3. The interrupt flag bit CRA-6 is cleared by an MPU read of the A data register, and CRB-6 is cleared by an MPU read of the B data register. 4. If CRA-3 (CRB-3) is LOW when an Interrupt occurs (Interrupt disabled) and is later brought HIGH, iRQA (I ROB) occurs after CRA·3 (CRB·3) is written to a "1". 5·98 MPU Interrupt Request IRaA (IRaB) IROA (IROB) remains IROA (IROB) remains F6820 Table 5 Control 01 CB2 as an Output CB2 CRB·5 CRB·4 CRB·3 Cleared Set 1 0 0 LOW on the positive transition of the first E pulse following an MPU write "B" data register operation_ HIGH when the interrupt flag bit CRB-? is set by an active transition of the CB1 signal. 1 0 1 LOW on the positive transition of the first E pulse after an MPU write "B" data register operation_ HIGH on the positive edge of the first E pulse following an E pulse that occurred while the part was deselected_ 1 1 0 LOW when CRB-3 goes LOW as a result of an MPU write in control register "B". Always LOW as long as CRB-3 is LOW. Goes HIGH on an MPU write in control register "B" that changes CRB-3 to "1 "_ 1 1 1 Always HIGH as long as CRB-3 is HIGH. Cleared when an MPU write control register "B" results in clearing CRB-3 to "0". HIGH when CRB-3 goes HIGH as a result of an MPU write into control register "B". Table 6 Control 01 CA2 as an Output CA2 CRA·5 CRA·4 CRA·3 1 0 1 Cleared Set 0 LOW on negative transition of E after an MPU read "A" data operation. HIGH when the interrupt flag bit CRA·? is set by an active transition of the CA1 signal. 0 1 LOW on negative transition of E after an MPU read "A" data operation. HIGH on the negative edge of the first E pulse that occurs during a deselect. 1 1 0 LOW when CRA-3 goes LOW as a result of an MPU write to control register "A". Always LOW as long as CRA-3 is LOW. Goes HIGH on an MPU write to control register "A" that changes CRA-3 to "1". 1 1 1 Always HIGH as long as CRA-3 is HIGH. Cleared on an MPU write to control register "A" that clears CRA-3 to a "0". HIGH when CRA-3 goes HIGH as a result of an MPU write to control register "A". Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance -0.3 V, -0.3 V, O·C, -55·C, +?OV +?OV + ?O·C +150·C 82.5·C/W This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this hig impedance circuit. 5-99 F6820 DC Characteristics Vee = 5.0 V ± 5%, Vss = 0, TA = 0 to 70·C unless otherwise noted. Symbol Characteristic VIH Input HIGH Voltage Enable Other Inputs Vss + 2.4 Vss +2.0 Vee Vee Input LOW Voltage Enable Other Inputs Vss -0.3 Vss -0.3 Vss +0.4 Vss +0.8 VIL Min Typ Max Condition Unit V V Input Leakage Current ANV, AESET, ASo, AS1, CSo, CS1, CS2, CA1, CB1, Enable 1.0 2.5 p.A VIN = 0 to 5.25 V ITSI 3-State (OFF State) Input Current Do-D7, PBo-PB7, CB2 2.0 10 p.A VIN = 0.4 to 2.4 V IIH Input HIGH Current PAo-PA7, CA2 p.A VIH = 2.4 V IlL Input LOW Current PAo-PA7, CA2 mA VIL = 0.4 V liN Output HIGH Voltage Do-D7 -100 -250 -1.0 -1.6 V ILoad = - 205 p.A, Enable pulse width <25 p.S Vss + 2.4 VOH Other Outputs VOL IOH Output LOW Voltage Output HIGH Current (Sourcing) Do-D7 Other Outputs PBo-PB7, CB2 IOL Output LOW Current (Sinking) ILOH Output Leakage Current (OFF State) IAOA, IAOB Po Power Dissipation CIN Input Capacitance Enable Do-D7 PAo-PA7, PBo-PB7, CA2, CB2 AfW, AESET, ASo, AS1, CSo, CS1, CS2, CA1, CB1 COUT V Vss + 2.4 Vss +0.4 -205 -100 -1.0 -2.5 -10 1.6 1.0 10 650 V = ILoad -100 p.A, Enable pulse width <25 P.s ILoad = 1.6 mA, Enable pulse width <25 P.s p.A p.A VOH = 2.4 V mA Vo = 1.5 V, the current for driving other than TTL, e.g., Darling base mA VOL = 0.4 V p.A VOH = 2.4 V mW pF 20 12.5 10 VIN = 0, TA = 25·C, f = 1.0 MHz 7.5 Output Capacitance IAOA, IAOB PBo-PB7 pF 5.0 10 5-100 VIN = 0, TA '" 25·C f=1.0MHz F6820 AC Characteristics Vcc = 5.0 V ± 5%, Vss = 0, TA = 0 to lO°C unless otherwise noted. Symbol Characteristic Min tposu Peripheral Data Set-up Time 200 tCA2 Delay Time, Enable Negative Transition to CA2 Negative Transition tRS, Typ Max Unit Condition ns Figure 1 1.0 /ls Figures 2,3 Delay Time, Enable Negative Transition to CA2 Positive Transition 1.0 /ls Figure 2 t r, tf Rise and Fall Times for CAl and CA2 Input Signals 1.0 /ls Figure 3 tRS2 Delay Time from CAl Active Transition to CA2 Positive Transition 2.0 /ls Figure 3 tpow Delay Time, Enable Negative Transition to Peripheral Data Valid 1.0 /ls Figures 4,5 2.0 /lS Vcc - 30% Vcc, Figure 4; Figure 12, Load C 1.0 /ls Figures 6, 1 ns Figure 5 tCMOS Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid PAo-PA7, CA2 tCB2 Delay Time, Enable Positive Transition to CB2 Negative Transition toc Delay Time, Peripheral Data Valid to CB2 Negative Transition tRS' Delay Time, Enable Positive Transition to CB2 Positive Transition 1.0 /lS Figure 6 t r, tf Rise and Fall Time for CB, and CB2 Input Signals 1.0 /lS Figure 7 tRS2 Delay Time, CB, Active Transition to CB2 Positive Transition 2.0 /lS Figure 7 tlR Interrupt Release Time, IROA and IROB /ls Figure 8 tRL RESET LOW Time /ls Figure g, Note 1 * Note'. 20 1.6 2.0 The RESET line must be HIGH a minimum of ,.O.s before addressing the PIA. 5-101 F6820 Bus Timing Characteristics Read Figures 10 and 12 Symbol Characteristic tcycE Enable Cycle Time PWEH Enable Pulse Width, HIGH 0.45 PWEL Enable Pulse Width, LOW 0.43 ",s tAS Set·up Time, Address and RIW Valid to Enable Positive Transition 160 ns tOOR Data Delay Time tH Data Hold Time 10 tAH Address Hold Time 10 tEr, tEt Rise and Fall Time for Enable Input Write Min Typ Max 1.0 Unit ",s 25 320 ",s ns ns ns 25 ns Figures 11 and 12 1.0 tcycE Enable Cycle Time PWEH Enable Pulse Width, HIGH 0.45 PWEL Enable Pulse Width, LOW 0.43 ",s tAS Set·up Time, Address and R/W Valid to Enable Positive Transition 160 ns tosw Data Set·up Time 195 ns tH Data Hold Time 10 ns tAH Address Hold Time 10 tEr, tEt Rise and Fall Time for Enable Input Fig. 1 PAo·PA7 PBO·PB7 Fig. 2 X--------------------------1-- CA2 Delay Time (Read Mode; CRA·5 E~0.4V 2.OV 0.8 V IPDSU _---J/~2.4V-~ ,. / ~,~ ~ ~; ';'.4-. :. .v ",s ns 25 Peripheral Data Set·up Time (Read Mode) ___I ",s 25 ns = CRA·3 = 1, CRA·4 = 0) \ ~~:~~T-V-_-'-RS1. ______ * Assumes part was deselected during any previous E pulse. 5·102 F6820 Fig. 3 CA2 Delay Time (Read Mode; CRA·5 1, CRA·3 CRA·4 0) 0.4 V ~I l.....- tr ,tl C_A_'______~----------~ ~:----~:x:~:~.:~:----- -"",I ~ o.)h ------------------. Fig. 4 Peripheral CMOS Data Delay Times (Write Mode; CRA·5 = CRA·3 = 1, CRA·4 Fig. 5 Peripheral Data and CB2 Delay Times (Write Mode; CRB·5 = CRB·3 = 1, CRB·4 0) 0) E \ 1_ 0.4V ---------"' PAO·PA7 / IPDW il"2-.4""'"V:---------- PSO·PB7 0.4 V -'~~ 2.4 V 0.4 V Fig. 6 CB2 Delay Time (Write Mode; CRB·5 = CRB·3 = 1, CRB·4 E_ CB, ~2.4V \'--- 0) Note ~ 1-~ :; .;,.4. ;,.:C-B'- - -I~- ~_I.Jt". Fig. 7 CB2 goes LOW as a result of the positive transition of the E pulse. CB2 Delay Time (Write Mode; CRB·5 - 1, CRB·3 CRB·4 0) E _I 1_ 1,,1, CB-,------~------~·~:--~:~:V~V:x:~--- • Assumes part was deselected during the previous E pulse. _ICB',I IRs,·~1 2.4j:=- ~~ • Assumes part was deselected during the previous E pulse. 5·103 F6820 Fig. 8 Interrupt Release Time RESET LOW Time Fig. 9 I------IRL-----_I _~~.4V y 'i_O.8V_ _ 1-.~_-_-__IIR~~~--j~~~2.~4V~- 1__ ______ _ IRQA (IRQB) / 'The RESET line must be at VIH for a minimum of 1.0 addressing the PIA. ' Fig. 11 Fig. 10 Bus Read Timing Characteristics (Read Information from PIA) ~s before Bus Write Timing Characteristics (Write Information into PIA) 1·.......- - - - - t c y c E - - - - -......·1 1··o__..,------tcycE-----........ 1 -... tEr I~IAS----'" ......- -----.. tosw ------- ~ ~ tEf 2.0 V RS. CS, Ri'ii 0.8 V RS, CS. RI'ii ~ ~ X X 2.0 V DATA BUS 0.8 V DATA BUS Fig. 12 Bus Timing Test Loads LOAD A LOAD B LOAD C (CMOS LOAD) (iRa ONLY) 00-07, PAo·PA7, PBo·PB7, CA2. CB2) 3k TEST POINT - t -....-KHI-"AI'v--- 5.0 v C IN914 TEST POINT ~ 5.0 V 1100 pF OR EQUIV. C R 130 pF for 00.07 30 pF for PAo·PA7, PBo·PB7, CA2, and CB2 11.7 kO for 00·07 24 kO for PAo·PA7, PBo·PB7, CA2 and CB2 5·104 I_IAH I-IH TESTPOINT~ I 30PF F6820 Ordering Information Speed Order Code Temperature Range 1.0 MHz F6820P,S o·e to + 70·e P = Plastic DIP S = Ceramic DIP • 5·105 F6820 5-106 F6821 IF68A21 IF68821 FAIRCHILD Peripheral Interface Adapter (PIA) A Schlumberger Company Microprocessor Product Description The F6821 Peripheral Interface Adapter (PIA) provides a universal means of interfacing peripheral equipment to the F6800 microprocessing unit (MPU). This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional data buses and four control lines, in three speed ranges: 1.0 MHz (F6821), 1.5 MHz (F68A21), and 2.0 MHz (F68B21). No external logic is required for interfacing to most peripheral devices. Logic Symbol The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of the interface. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 36 • 8-Bit Bidirectional Data Bus for Communication with the MPU • Two Bidirectional 8-Bit Buses for Interface to Peripherals • Two Programmable Control Registers • Two Programmable Data Direction Registers • Four Individually Controlled Interrupt Input Lines, Two Usable as Peripheral Control Outputs • Handshake Control Logic for Input and Output Peripheral Operation • High-Impedance 3-State and Direct Transistor Drive Peripheral Lines • Program-Controlled Interrupt and Interrupt Disable Capability • CMOS Drive Capability on Section A Peripheral Lines • Two-TTL Drive Capability on All A- and B-Section Buffers • TTL-Compatible • Static Operation 35 RS, 22 cSa 24 (VMA)CS, 23 CS, 25 E 21 RNi 40 CA, 39 CA, 18 CB, 19 CB, 34 RESET F6821 33 32 31 Vee ~ Vss = Pin 1 Connection Diagram 40-Pin DIP CA, Plio CA, PA, IRQA PA, PA, RSo PA, RS, PA, REm PAs DO PA7 0, PBo 0, PB, 0, 0, PB, PB, 13 0, PB, 14 0, PB, 15 PB, 16 E PB 7 17 CS, CB, 18 cs, CB, 19 CSo Vee 20 R/W (Top View) 5-107 38 IROB 37 • 30 29 28 27 26 Pin 20 vss IROA F6821/F68A21/F68B21 Block Diagram IRaA~4~--------------------------------------~ ~ 0 _ 0 0,_ 0,_ 03- 0,_ 0,_ t CONTROL REGISTER A (CRA) ~ I L- I DATA BUS BUFFERS (DBB) INTERRUPT STATUS CONTROL A DATA DIRECTION REGISTER A (DORA) r--- OUTPUT BUS Q 0,0,_ ........... PAO OUTPUT REGISTER A (ORA) U BUS INPUT REGISTER (BIR) f---f---- L r ........... PAl I .......... PA 2 PERIPHERAL INTERFACE A V> :::J III ...:::J Q. '!O .......... PA 3 ...--..PA4 ~ ~PA5 r--- ..-......PA6 """-'PA7 OUTPUT I REGISTER B (ORB) [ ............. PB o ~PB1 I v ............. PB 2 PERIPHERAL INTERFACE B CS o-----' ......... PB 3 ........... PB 4 CS1~ RSO~ CHIP SELECT AND AS1~ A/Vi CS2~ R/W-----... r- ........... PBa ........... PB 7 CONTROL lr ENABLE ----... RESET--' ~ IRoe ........ PB s '-- CONTROL RE~~~TB~R B r-J I L DATA DIRECTION REGISTER B (DDRB) -lI= : : ~4~_________________________________·11___:_J_!_~_~~_U~_:__ PIAIMPU Interface Signals Data Bus (Do - 0 7), Pins 26-33 The bidirectional data lines allow the transfer of data between the MPU and the PIA. The data bus output drivers are 3-state devices that remain in the high-impedance (OFF) state, except when the MPU performs a PIA read operation. The read/write (R/W) line is in the read (HIGH) state when the PIA is selected for a read operation. The PIA interfaces to the F6800 MPU with an 8-bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line, and a reset line (see Figure 1). These Signals, in conjunction with the F6800 VMA output, permit the MPU to have complete control over the PIA. The VMA output should be utilized in conjunction with an MPU address line into a chip select of the PIA. 5-108 F6821/F68A21/F68B21 Fig. 1 PIA Bus Interface CA, CA2 I SECTION A CONTROLS CONTROL REG A B DATA ECTIONB DATA ~INTERFACE CONTROL REG B Vee ---. Vss - DATA ADDRESS BUS BUS ......._ _ _ _ _ _........ t 4, BUS CONTROL Enable (E), Pin 25 The enable input pulse is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading and trailing edges of the E pulse. This signal is normally a derivative of the ",2 F6800 clock. • CB,} SECTION B CB 1 CONTROLS Register Select (RS o, RS,), Pins 35, 36 The two register select inputs are used to select the various registers within the PIA. These two lines are used in conjunction with internal control registers to select a particular register that is to be written to or read from. The register select lines should be stable for the duration of the E pulse while in the read or write cycle. Read/Write (R/W), Pin 21 This input signal is generated by the MPU to control the direction of data transfer on the data bus. A LOW on the R/W line enables the input buffers and allows data transfer from the MPU to the PIA on the E signal if the device has been selected. A HIGH on the R/W line sets up the PIA for a transfer of data to the bus; the PIA output buffers are enabled when the proper address and the E pulse are present. Interrupt Request (IROA, IROB), Pins 37, 38 The active-LOW interrupt request inputs act to interrupt the MPU either directly or through interrupt priority circuitry. These lines are open drain (no load device on the chip). This permits all interrupt request lines to be tied together in a wired-OR configuration. Each interrupt request line has two internal interrupt flag bits that can cause either line to go LOW. Each flag bit is associated with a particular peripheral interrupt line. Four interrupt enable bits are also provided in the PIA; these may be used to inhibit a particular interrupt from a peripheral device. Reset (RESET), Pin 34 The active -LOW RESET input is used to reset all register bits in the PIA to a logic 0 (LOW) state. This line can be used as a power-on reset and as a master reset during system operation. Servicing an interrupt by th.e MPU is accomplished by a software routine that, on a priority basis, sequentially reads and tests the two control registers in each PIA for interrupt flag bits that are set. Chip Select (CS o - CS 2), Pins 22-24 These three input signals are used to select the PIA. The CSo and CS1 lines must be HIGH and CS2 must be LOW for selection of the device. Data transfers are then performed under control of the enable and read/write signals. The device is "deselected" when any of the chip select lines is in the inactive state. The interrupt flags are cleared (set to 0) as a result of an MPU read peripheral data operation of the corresponding data register. After being cleared, the interrupt flag bit cannot be enabled until the PIA is "deselected" during an E pulse. The E pulse is used to condition the interrupt control lines (CA 1, CA 2, CB 1, CB 2). When these The chip select lines should be stable for the duration of the E pulse. 5·109 • F6821/F68A21/F68821 lines are used as interrupt inputs, at least one E pulse must occur from the inactive edge to the active edge of the interrupt input signal to condition the edge sense network. If the interrupt flag has been enabled and the edge sense circuit has been conditioned properly, the interrupt flag is set on the next active transition of the interrupt input pin. PIA/Peripheral Interface Signals The PIA provides two 8-bit bidirectional data buses and four interrupt/control lines for interfacing to peripheral devices. transition for these signals is also programmed by the two control registers. Peripheral Control (CA 2, CB 2), Pins 39, 19 Peripheral control line CA2 can be programmed to act as an interrupt input or as a peripheral control output. As an output, this line is compatible with standard TTL; as an input, the internal pull-up resistor on this line represents one standard TTL load. The function of this signal line is programmed by control register A (CRA). Peripheral control line CB2 may also be programmed to act as in interrupt input or peripheral control output. As an input, this line has high input impedance and is compatible with standard TIL. As an output, it is compatible with standard TTL and may also be used as a source of up to 1 mA at 1.5 V to drive the base of a transistor switch directly. This line is programmed by control register B (CRBI. Section A Peripheral Data (PA o - PA 7), Pins 2-9 Each of the peripheral data lines is programmed to act as an input or output. This is accomplished by setting a 1 in the corresponding data direction register (DDR) bit for those lines that are to be outputs. A 0 in a bit of the DDR causes the corresponding peripheral data line to act as an input. During an MPU read peripheral data operation, the data on peripheral lines programmed to act as inputs appears directly on the corresponding MPU data bus lines. In the input mode, the internal pull~up resistor on these lines represents a maximum of one standard TTL load. It is recommended that the control lines (CAl, CB1, CA2, CB2) be held in a logiC 1 state when the RESET line is active to prevent setting of corresponding interrupt flags in the control register when RESET goes to an inactive state. Subsequent to RESET going inactive, a read of the data registers may be used to clear any undesired interrupt flags. The data in output register A (ORAl appears on the data lines that are programmed to be outputs. A logic 1 written into the register causes a HIGH on the corresponding data line, while a 0 results in a LOW. Data in ORA may be read by an MPU read peripheral data A operation when the corresponding lines are programmed as outputs. This data is read properly if the voltage on the peripheral data lines is greater than 2.0 V for a logic 1 output and less than 0.8 V for a logic 0 output. Loading the output lines in such a way that the voltage on these lines does not reach full voltage causes the data transferred into the MPU during a read operation to differ from that contained in the respective bit of output register A. Internal Controls There are six locations within the PIA that are accessible to the MPU data bus: two peripheral registers, two data direction registers, and two control registers. Selection of these locations is controlled by the register select inputs, together with bit 2 in the control register, as shown in Table 1. Table 1 Internal Addressing Control Register Bit Section B Peripheral Data (PB l - PB 7), Pins 10-17 The peripheral data lines in the B section of the PIA can be programmed to act as either inputs or outputs in a manner similar to the A section lines. However, the output buffers driving these lines differ from those driving the A section lines, having a 3-state capability that allows them to enter a high-impedance state when the peripheral data line is used as an input. In addition, data on peripheral data lines PB o through PB, is read properly from those lines programmed as outputs even if the voltages are below 2.0 V for a HIGH. As outputs, these lines are compatible with standard TTL and may also be used as a source of up to 1 mA at 1.5 V to drive the base of a transistor switch directly. CRA-2 CRB-2 Location Selected RSl RSo 0 0 1 X Peripheral Register A 0 0 0 X Data Direction Register A 0 1 X X Control Register A 1 0 X 1 Peripheral Register B 1 0 X 0 Data Direction Register B 1 1 X X Control Register B x= Don't Care Initialization A LOW on the RESET line has the effect of zeroing all PIA registers, This sets PA o - PA" PB o - PB CA 2, and CB 2 " Interrupt Input (CAl' CB 1), Pins 18 and 40 The interrupt input lines are input-only lines that set the interrupt flags of the control registers. The active 5·110 F6821/F68A21/F68B21 as inputs and disables all interrupts. The PIA must be configured during the restart program that follows the reset. CA2, and CB2). In addition, they allow the MPU to enable the interrupt lines and monitor the status of the interrupt flags. Bits 0 through 5 of the two registers may be written to or read from by the MPU when the proper chip select and register select signals are applied. Bits 6 and 7 of the two registers are read"only and are modified by external interrupts occurring on the peripheral control lines. The format of the control words is shown in Table 2. Register Operation Possible configurations of the data direction and control registers are as follows: Data Direction Registers (DORA, DDRB) The two. data direction registers allow the MPU to control the direction of data through each corresponding peripheral data line. A DDR bit set to 0 configures the corresponding peripheral data line as an input; a 1 results in an output. Table 2 Control Word Format o CRA Control Registers (CRA, CRB) The two control registers allow the MPU to control the operation of the four peripheral control lines (CA1, CB1, • CRB ---'-----'---'----~- Table 3 Interrupt Input Line Control Bits MPU Interrupt Request IROA (IROB) CRA-1 (CRB-1) CRA-O (CRB-O) 0 0 j Active Set HIGH on j of CA1 (CB11. Disabled; IRQ remains HIGH. 0 1 j Active Set HIGH on j of CA1 (CB11. Goes LOW when interrupt flag bit CRA-7 (CRB-7) goes HIGH. 1 0 ! Active Set HIGH on ! of CA1 (CB1). Disabled; IRQ remains HIGH. 1 1 ! Active Set HIGH on ! of CA1 (CB1). Goes LOW when interrupt flag bit CRA-7 (CRB-7) goes HIGH. Table 4 Interrupt Input CAl (CB1) Interrupt Flag CRA-7 (CRB-7) Peripheral Control Line Control Bits (CRA-5/CRB-5 LOW) MPU Interrupt Request IROA (IROB) CRA-5 (CRB-5) CRA-4 (CRB-4) CRA-3 (CRB-3) Interrupt Input CA2 ( CB 2) 0 0 0 I Active Set HIGH on (CB2). 0 0 1 I Active Set HIGH on I of CA2 (CB2i. Goes LOW when inte.rrupt flag bit CRA-6 (CRB-6) goes HIGH. 0 1 0 ! Active Set HIGH on I of CA2 (CB2i. Disabled; IRQ remains HIGH. 0 1 1 ! Active Set HIGH on ! CA2 (CB2i. Goes LOW when interrupt flag bit CRA-6 (CRB-6) goes HIGH. Interrupt Flag CRA-6 (CRB-6) j CA2 Disabled; IRQ remains HIGH. Notes 1. I indicates negative transition (HIGH~to-LOW~, 2. , indicates positive transition {LOW-to-HIGH \. 3. The interrupt flag bit,CRA-7, is cleared by an MPU read of the A data register, and CRB-7 is cleared by an MPU read of the B data register. 4. If CRA-O (CRB-O( is LOW when an interrupt occurs linterrupt disabledl and is later brought HIGH, IROA !lROBI occurs after CRA-O (CRB-O( is written to a 1. 5-111 F6821 IF68A21 IF68B21 and CRB-O are used to enable MPU interrupt signals IROA and IROB, respectively. Bits CRA-1 and CRB-1 determine the active transition of the interrupt input signals (see Table 31. Data Direction Access Control Bit (CRA-2, CRB-2) Bit 2 in each control register allows selection of either a peripheral interface register (PIR) or the DDR when the proper register select signals are applied to RSo and RS,. Peripheral Control Line Control Bits (CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, CRB-5) Bits 3, 4, and 5 of the two control registers are used to control the CA 2 and CB 2 peripheral control lines. These bits determine if the control lines act as interrupt inputs or as control outputs. If bit CRA-5 (CRB-51 is LOW, CA2 (CB 2 1is an interrupt input line similar to CAl (CB,I (see Table 41. When CRA-5 (CRB-51 is HIGH, CA 2 (CB 2 1 becomes an output that may be used to control peripheral data transfers. When in the output mode, CA 2 and CB 2 have slightly different characteristics (see Table 5 and Table 6). Interrupt Flag Control Bits (CRA-5, CRA-7, CRB-5, CRB-7) The four interrupt flag bits are set by active transitions of signals on the four interrupt and peripheral control lines when those lines are programmed to be input lines. These bits cannot be set directly from the MPU data bus and are reset indirectly by a read peripheral data operation on the appropriate section. Interrupt Input Line Control Bits (CRA-O, CRA-1, CRB-O, CRB-1) The two lowest-order bits of the control registers are used to control interrupt input lines CAl and CB,. Bits CRA-O Table 5 Control of CA 2 as an Output CA2 Set CRA-5 CRA4 CRA-3 1 0 0 LOW on the negative transition of E after an MPU read data register A operation. HIGH when interrupt flag bit CRA-? is set by an active transition of the CAl signal. 1 0 1 LOW on the negative transition of E after an MPU read data register A operation. HIGH on the negative edge of the first E pulse that occurs while the device is deselected. 1 1 0 LOW when CRA-3 goes LOW as a result of an MPU write control register A oper 2) until one of several predetermined conditions causes it to halt or recycle. The timers are thus programmable, cyclic in nature, controllable by external inputs or the MPU program, and accessible by the MPU at any time. Bus Interlace The programmable timer module (PTM I interfaces to the F6800 bus with an 8-bit bidirectional data bus, two Chip Select lines, a Read/Write line, an Enable (System <1>2) 5-120 F6840/F68A40/F68B40 line, an Interrupt Request line, an external RESET line, and three Register Select lines. These signals, in conjunction with the F6800 VMA output, permit the MPU to control the PTM. VMA should be utilized in conjunction with the MPU address line into a Chip Select of the PTM. Interrupt Request (IRQ) The active LOW Interrupt Request signal is normally tied directly (or through priority interrupt circuitry) to the IRQ input of the MPU. This is an open drain output (no load device on the chip) which permits other similar Interrupt Request lines to be tied together in a wired-OR configuration. Bidirectional Data (00-07) The bidirectional Data Lines (00-07) allow the transfer of data between the MPU and the PTM. The data bus output drivers are 3-state devices which remain in the highimpedance (OFF) state except when the MPU performs a PTM read operation (Read/Write and Enable lines HIGH and PTM Chip Selects activated). The IRQ line is activated if, and only if, the composite interrupt flag (bit 7 of the internal status register) is asserted. The conditions under which the IRQ line is activated are discussed in conjunction with the status register. External RESET A LOW level at this input is clocked into the PTM by the Enable (System <1>2) input. Two Enable pulses are required to synchronize and process the Signal. The PTM then recognizes the active LOW or inactive HIGH on the third Enable pulse. If the RESET signal is asynchronous, an additional Enable period is required if set-up times are not met. The RESET input must be stable HIGH/LOW for the minimum time stated in the AC Characteristics table. Chip Select (CSo, CS1) These two signals are used to activate the data bus interface and allow transfer of data from the PTM. With CSo = '~O" and CS1 = "1", the device is selected and data transfer will occur. Read/Write (R/W) This Signal is generated by the MPU to control the direction of data transfer on the data bus. With the PTM selected, a LOW state on the PTM RiiiJ line enables the input buffers and data is transferred from the MPU to the PTM on the trailing edge of the Enable (System <1>2) signal. Alternately (under the same conditions), RiW = "1" and Enable HIGH allows data in the PTM to be read by the MPU. Recognition of a LOW level at this input by the PTM causes the following action to occur: a. All counter latches are preset to their maximal count values. b. All control register bits are cleared with the exception of CR10 (internal reset bit), which is set. c. All counters are preset to the contents of the latches. d. All counter outputs are reset and all counter clocks are disabled. e. All status register bits (interrupt flags) are cleared. Enable (E, System <1>2) This signal synchronizes data transfer between the MPU and the PTM. It also performs an equivalent synchronization function on the external Clock, RESET. and Gate inputs of the PTM. Table 1 Register Selection Operations Register Select Inputs RS2 RS1 RSo R/W = "0" 0 0 0 CR20 = "0" Write Control Register 3 CR20 = "1" Write Control Register 1 R/W = "1" No Operation 0 0 1 Write Control Register 2 Read Status Register 0 1 0 Write MSB Buffer Register Read Timer 1 Counter Read LSB Buffer Register 0 1 1 Write Timer 1 Latches 1 0 0 Write MSB Buffer Register Read Timer 2 Counter 1 0 1 Write Timer 2 Latches Read LSB Buffer Register 1 1 0 Write MSB Buffer Register Read Timer 3 Counter 1 1 1 Write Timer 3 Latches Read LSB Buffer Register 5-121 5 F6840/F68A40/F68B40 control register bits (except CR1o) are cleared. Therefore, one may write in the sequence CR3, CR2, CR,. Register Select Lines (RSo, RS" RS2) These inputs are used in conjunction with the R/W line to select the internal registers, counters and latches as shown in Table 1. The least significant bit of control register 1 is used as an internal reset bit. When this bit is a logic "0", all timers are allowed to operate in the modes prescribed by the remaining bits of the control registers. Writing a . "1" into CR10 causes all counters to be preset with the contents of the corresponding counter latches, all counter clocks to be disabled, and the timer outputs and interrupt flags I status register) to be reset. Counter latches and control registers are undisturbed by an internal reset and may be written into regardless of the state of CR10. It has been stated previously that the PTM is accessed via MPU load and store operations in much the same manner as a memory device. The instructions available with the F6800 family of MPUs which perform operations directly on memory should not be used when the PTM is accessed. These instructions actually fetch a byte from memory, perform an operation, then restore it to the same address location. Since the PTM uses the R/W line as an additional register select input, the modified data may not be restored to the same register if these instructions are used. The least significant bit of control register 3 is used as a selector for a +8 prescaler, which is available with timer 3 only. The prescaler, if selected, is effectively placed between the clock input circuitry and the input to counter 3. It therefore can be used with either the internal clock (Enable) or an external clock source. Control Register Three write-only registers in the F6840 are used to modify timer operation to suit a variety of applications. Control register 2 has a unique address space (RSo = "1 ", RS, = "0", RS2 = "0") and therefore may be written into any time. The remaining control registers (1 and 3) share the address space selected by a logic "0" on all register select inputs. The least significant bit of control register 2 I CR2o) is used as an additional addressing bit for control registers 1 and 3. Thus, with all Register Selects and R/W inputs at logic "0", control register 3 will be written into if CR2a is a logic "0". Control register 3 can also be written into after a reset LOW condition has occurred, since all The functions depicted in the foregoing discussions are tabulated on the first row in Table 2 for ease of reference. Control register bits CR1o, CR20 and CR30 are unique in that each selects a different function. The remaining bits (1 through 7) of each control register select common functions, with a particular control register affecting only Table 2 Control Register Bits CR10 Internal Reset Bit CR20 Control Register Address Bit o o 1 All timers allowed to operate All timers held in preset state CR3 may be written 1 CR1 may be written CR30 Timer 3 Clock Control o 1 T3 Clock is not prescaled T3 Clock is prescaled by +8 Timer X Clock Source TX uses external clock source on CX input TX uses Enable clock Timer X Counting Mode Control TX configured for normal 116-bit) counting mode TX configured for dual 8-bit counting mode CRX2 o 1 CRX3 CRX4 CRXs CRXs o 1 CRX7 o 1 Timer X Counter Mode and Interrupt Control (See Table 3) Timer X Interrupt Enable Interrupt Flag masked on IRQ Interrupt Flag enabled to IRQ Timer X counter Output Enable TX Output masked on output OX TX Output enabled on output OX * Control Register for timer 1, 2 or 3, Bit 1. 5-122 F6840/F68A40/F68B40 its corresponding timer. For example, bit 1 of control register 1 (CR1,) selects whether an internal or external clock source is to be used with timer 1. Similarly, CR2, selects the clock source for timer 2, and CR3, performs this function for timer 3. The function of each bit of control register "X" can therefore be defined as shown in the remaining section of Table 2. An individual interrupt flag is also cleared by a write timer latches (WI command or a counter initialization (CI) sequence, provided that W or CI affects the timer corresponding to the individual interrupt flag. Counter Latch Initiali~ation Each of the three independent timers consists of a 16-bit addressable counter and 16 bits of addressable latches. The counters are preset to the binary numbers stored in the latches. Counter initialization results in the transfer of the latch contents to the counter. See the notes in Table 5 regarding the binary number N, L or M placed into the latches and their relationship to the output waveforms and counter time outs. Control register bit 2 selects whether the binary information contained in the counter latches (and subsequently loaded into the counter! is to be treated as a single 16-bit word or two 8-bit bytes. In the single 16-bit counter mode (CR2 = "0"), the counter will decrement to zero after N + 1 enabled (G = "0" I clock periods, where N is defined as the 16-bit number in the counter latches. With CRX2 = "1", a similar time-out will occur after (L + 11 . (M + 1) enabled clock periods. where Land M. respectively, refer to the LSB and MSB bytes in the counter latches. Control register bits 3, 4, and 5 are explained in detail in the Timer Operating Modes section. Bit 6 is an interrupt mask bit which will be explained more fully in conjunction with the status register, and bit 7 is used to enable the corresponding timer output. A summary of control register programming modes is shown in Table 3. Since the PTM data bus is 8 bits wide and the counters are 16 bits wide, a temporary register ( MSB buffer register) is provided. This write-only register is for the most significant byte of the desired latch data. Three addresses are provided for the MSB buffer register (as indicated in Table 1), but they all lead to the same buffer. Data from the MSB buffer will be transferred automatically into the most significant byte of timer X when a write timer X latches command is performed. So it can be seen that the F6840 has been designed to allow transfer of two bytes of data into the counter latches provided that the MSB is transferred first. Status Register/Interrupt Flags The F6840 has an internal read-only status register which contains four interrupt flags. (The remaining four bits of the register are not used, and default to "Os" when being read). Bits 0, 1, and 2 are assigned to timers 1, 2, and 3, respectively, as individual flag bits, while bit 7 is a composite interrupt flag. This flag bit will be asserted if any of the individual flag bits is set while bit 6 of the corresponding control register is at a logic "1". The conditions for asserting the composite interrupt flag bit can therefore be expressed as: In the many applications, the source of the data will be an F6800 MPU. It should be noted that the 16-bit store operations of F6800 family microprocessors (STS and STX) transfer data in the order required by the PTM. A store index register instruction, for example, results in the MSB of the X register being transferred to the selected address, then the LSB of the X register being written into the next higher location. Thus, either the index register or stack pointer may be transferred directly into a selected counter latch with a single instruction. INT = I, . CR16 + 12 . CR26 + 13 . CR36 = Composite Interrupt Flag (Bit 71 A logic "0" at the RESET input also initializes the counter latches. In this case, all latches will assume a maximum count of 65,53610. It is important to note that an internal reset (bit zero of control register 1 set) has no effect on the counter latches. where INT h = Timer 1 Interrupt Flag (Bit 0) 12 = Timer 2 I nterrupt Flag (Bit 1) 13 = Timer 3 Interrupt Flag (Bit 21 An interrupt flag is cleared by a timer reset condition; i.e., external RESET = "0" or internal reset bit (CR1o) = "1". It will also be cleared by a read timer counter command, provided that the status register has previously been read while the interrupt flag was set. This condition on the read status register - read timer counter (RS - RT) sequence is designed to prevent miSSing interrupts which might occur after the status register is read, but prior to reading the timer counter. Counter Initialization Counter initialization is defined as the transfer of data from the latches to the counter with subsequent clearing of the individual interrupt flag associated with the counter. Counter initialization always occurs when a reset condition (RESET) = "0" or CR10 = "1" is recognized. It can also occur-depending on timer mode-with a write timer latches command or recognition of a negative transition of the gate input. 5·123 • F6840/F68A40/F68B40 Table 3 Control Register Programming Register 2 Register 3 All timers operate Reg #3 may be written T3 Clk+ 1 All timers preset Reg #1 may be written T3 Clk + 8 Register 1 o o External Clock (CX Input) Internal Clock (Enable) o Normal (16-Bil) Count Mode Dual 8-BitCount Mode Continuous Operating Mode: Gate I or Write to Latches or Reset Causes Counter Initialization Frequency Comparison Mode: Interrupt if Gate L n i S < Counter Time-Out Continuous Operating Mode: Gate I or Reset Causes Counter Initialization Pulse Width Comparison Mode: Interrupt if Gate L---.t is < Counter Time-Out Single Shot Mode: Gate I or Write to Latches or Reset Causes Counter Initialization Frequency Comparison Mode: Interrupt if Gate L n i s > Counter Time-Out Single Shot Mode: Gate I or Reset Causes Counter Initialization Pulse Width Comparison Mode: Interrupt if Gate o Interrupt Flag Masked (iRO) Interrupt Flag Enabled (IRQ) o Timer Output Masked Timer Output Enabled Note Reset is Hardware or Software Reset IRESET) = 0 or CRw = 1 J. 5-124 l-----t is > Counter Time-Out F6840/F68A40/F68B40 Counter recycling or re-initialization occurs when a negative transition of the clock input is recognized after the counter has reached an all-"O" state. In this case, data is transferred from the latches to the counter. cycle, and not recognized the next cycle, or vice versa. E INPUT c3-4--__~~~---'"L ~~J"--Asynchronous Input/Output Lines PTM Each of the three timers within the PTM has external clock and gate inputs as well as a counter output line. The inputs are high impedance, TTL-compatible lines and outputs are capable of driving two standard TTL loads. Clock Inputs (e1, C2 and C3) Input pins C1, C2 and C3 will accept asynchronous TTL vOltage level signals to decrement timers 1, 2 and 3, respectively. The HIGH and LOW levels of the external clocks must each be stable for at least one system clock period plus the sum of the set-up and hold times for the inputs. The asynchronous clock rate can vary from dc to the limit imposed by Enable (System <1>2) set-up and hold time. The external clock inputs are clocked in by Enable (System <1>2) pulses. Three enable periods are used to synchronize and process the external clock. The fourth Enable pulse decrements the internal counter. This does not affect the input frequency, it merely creates a delay between a clock input transition and internal recognition of that transition by the PTM. All references to C inputs in this document relate to internal recognition of the input transition. Note that a clock HIGH or LOW level which does not meet set-up and hold time specifications may require an additional Enable pulse for recognition. When observing recurring events, a lack of synchronization will result in jitter being observed on the output of the PTM when using asynchronous clocks and gate input signals. There are two types of jitter. System jitter is the result of the input signals being out of synchronization with the Enable input (System <1>2), permitting signals with marginal set-up and hold time to be recognized by either the bit time nearest the input transition or the subsequent bit time. E INPUT :iu~G~sEITHER - - ' HERE SYSTEM }-4-BIT TIME I ' - - - OR HERE , JITTER I OUTPUT----------~Sr-L-J Input jitter can be as great as the time between input signal negative going transitions plus the system jitter, if the first transition is recognized during one system RECOGNIZES THIS EDGE I to PTM OR I to PTM External clock input C3 represents a speCial case when timer 3 is programmed to utilize its optional +8 prescaler mode. The maximum input frequency and allowable duty cycles for this case are specified in the AC Characteristics table. The output of the +8 prescaler is treated in the same manner as the previously discussed clock inputs. That is, it is clocked into the counter by Enable pulses, is recognized on the fourth Enable pulse (provided set-up and hold time requirements are met), and must produce an output pulse at least as wide as the sum of an enable period, set-up and hold times. Gate Inputs (G1, G2, (3) Input lines G1, (32 and <33 accept asynchronous TTL-compatible signals which are used as triggers or clock gating functions to timers 1, 2 and 3, respectively. The gating inputs are clocked into the PTM by the Enable (System <1>2) signal in the same manner as the previously discussed Clock inputs. That is, a Gate transition is recognized by the PTM on the fourth Enable pulse (provided set-up and hold time requirements are met), and the HIGH or LOW levels of the Gate input must be stable for at least one system clock period plus the sum of the set-up and hold times. All references to 13 transition in this document relate to internal recognition of the input transition. The Gate inputs of all timers directly affect the internal 16-bit counter. The operation of 133 is therefore independent of the +8 prescaler selection. Timer Outputs (01, 02, 03) Timer outputs 01. 02 and 03 are capable of driving up to two TTL loads and produce a defined output waveform for either continuous or single-shot timer modes. Output waveform definition is accomplished by selecting either single 16-bit or dual 8-bit operating modes. The single 16-bit mode will produce a squarewave output in the continuous timer mode and will produce a single pulse in the single-shot timer mode. The dual 8-bit mode will produce a variable duty cycle pulse in both the continuous and single shot timer modes. One bit of each control register (CRX7) is used to enable the corresponding output. If this bit is cleared, the output will remain LOW (VoLi regardless of the operating mode. 5-125 • F6840/F68A40/F68B40 The continuous and single-shot timer modes are the only ones for which output response is defined. Signals appear at the outputs I unless CRX7 = "0" 1 during frequency and pulse width comparison modes, but the actual waveform is not predictable in typical applications. timers. These modes are outlined in Table 4. Timer Operating Modes Continuous Operating Mode (Table 5) Any of the timers in the PTM may be programmed to operate in a continuous mode by writinq "as" into bits 3 and 5 of the corresponding control register. Assuming that the timer output is enabled ICRX7 = "1"1, either a square wave or a variable duty cycle waveform will be generated at the timer output. OX. The type of output is selected via control register bit 2. In addition to the four timer modes in Table 4, the remaining control register bit is used to modify counter initialization and enabling or interrupt conditions. The F6840 has been designed to operate effectively in a wide variety of applications. This is accomplished by using three bits of each control register ICRX3. CRX4 and CRXsl to define different operating modes of the Table 4 Operating Modes Either a timer reset I CRX10 = "1" or External RESET = "a") condition or internal recognition of a negative transition of the Gate input results in counter initialization. A write timer latches command can be selected as a counter initialization signal by clearing CRX4. Control Register CRX3 CRX4 a . . 1 a 1 1 a CRXs Timer Operating Mode a Continuous 1 Single-Shot . Frequency Comparison . In the dual 8-bit mode (CRX2 = "1") I refer to the example in Figure 1J the MSB decrements once for every full countdown of the LSB + 1. When the Pulse Width Comparison 'Defines additional timer functions Table 5 Continuous Operating Modes, (CRX3 Control Register = "0", CRXs Initialization/Output Waveforms CRX2 CRX4 Counter Initialization a a GI + W +R 'Timer Output (OX) (CRX7 r(N a 1 GI + R 1 a GI + W + R I to r(L GI + R GI I TO TO VOH -VOL I TO VOH -VOL -..I I.- -..I l.- I (L)(T) = Negative transition of Gate input = Write Timer Latches Command = Timer Reset I CR10 = "1" or External RESET = 16-Bit Number in Counter Latch = 8-Bit Number in LSB Counter Latch I- n- n (L)(T) TO TO to W R N L I + 1)(M + 1)(T)T(L + 1)(M + 1)(T) __1 I 1 = "1") + 1 ) ( T ) TN + 1)(TT(N + 1)(T)1 I 1 = "0") = "a") M T to TO ,e) * All time intervals shown above assume the Gate I GI and Clock signals are synchronized to Enable (System 1.>2) with the specified set-up and hold time requirements. 5-126 = = = ,= 8-Bit Number in MSB Counter Latch Clock Input Negative Transitions to Counter Counter Initialization Cycle Counter Time-Out (All "a" Condition) F6840/F68A40/F68B40 Fig. 1 Timer Output Waveforms Example *TIME CONTENTS OF LSB = 04 = L I" M(l ---, , COUNTE RI OUTPUT I I E (SYSTEM 02) 1M + 111L + 11 ~ Period MIL + 1) + 1 ~ LOW portion of period L = Pulse width • Preset LSB and MSB to Respective Latches on the negative transition of the Enable 2.4 V "Preset LSB to LSB Latches and 0.4 v Decrement MSB by one on the negative transition of the Enable OUT EXAMPLE: CONTENTS OF MSB -- 03 = M -I- + .. 1) + 1 ALGEBRAIC EXPRESSION + 1) + 1 " 16 E I 03(04 : I I I I I I I I I I I L_ l{I I I I I I I I I I I I I I I+L~~ITL--~"~I~.'---I+L~ 5E PULSES I I I I I I I I I I I I I I 1-, 5E PULSES 5E PULSES I I I I I (M+1k~ 1 •• 1 I !~! I I I I_I ~ ALGEBRAIC EXPRESSIONOR ) • I (04 + 1)(03 + 1) " 20 E EXTERNAL CLOCK PULSES LSB = "0". the MSB is unchanged; on the next clock pulse the LSB is reset to the count in the LSB latches and the MSB is decremented by 1 (one). The output, if enabled, remains LOW during and after initialization and will remain LOW until the counter MSB is all "Os". The output will go HIGH at the beginning of the next clock pulse. The output remains HIGH until both the LSB and MSB of the counter are all "Os". At the beginning of the next clock pulse the defined time-out (TO) will occur and the output will go LOW. In the normal 16-bit mode the period of the output of the example in Figure 1 would span 1546 clock pulses as opposed to the 20 clock pulses using the dual 8-bit mode. output, if enabled, goes LOW during the counter initialization cycle and reverses state at each time-out. The counter remains cyclical (is re-initialized at each time-out) and the individual interrupt flag is set when time-out occurs. If M = L = "0", the internal counters do not change, but the output toggles at a rate of 1/2 the clock frequency. The discussion of the continous mode has assumed that the application requires an output signal. It should be noted that the timer operates in the same manner with the output disabled (CRX7 = "0"). A read timer counter command is valid regardless of the state of CRX7. The counter is enabled by an absence of a timer reset condition and a logic "0" at the Gate input. The counter will then decrement on the first clock signal recognized during or after the counter initialization cycle. It continues to decrement on each clock signal so long as G remains LOW and no reset condition exists. A counter time-out (the first clock after all counter bits = "0") results in the individual interrupt flag being set and re-initialization of the counter. Single-Shot Timer Mode This mode is identical to the continuous mode with three exceptions. The first of these is obvious from the name - the output returns to a LOW level after the initial time-out and remains LOW until another counter initialization cycle occurs. The waveforms available are shown in Table 6. As indicated in Table 6, the internal counting mechanism remains cyclical in the single-shot mode. Each time-out of the counter results in the setting of an individual interrupt flag and re-initialization of the counter. A special condition exists for the dual 8-bit mode (CRX2 = "1") if L = "0". In this case, the counter will revert to a mode similar to the single 16-bit mode, except time-out occurs after M + 1 clock pulses. The 5·127 F6840/F68A40/F68840 Table 6 Single-Shot Operating Modes, (CRX3 Control Register = "0", CRX7 = "1", CRX5 = "1") Initialization/Output Waveforms CRX2 CRX4 Counter Initialization 0 0 OJ + W +R n'" ""'l r',"., "" '' ' '1 Timer Output (OX) ~ "~=f'" ~ I-(N)(T) 0 1 OJ + R 1 0 OJ + W ~ I TO to +R TO ""'~' i(L)(T) 1 1 OJ + R to n TO TO Symbols are as defined in Tab'e 5 The second major difference between the single-shot and continuous modes is that the internal counter enable is not dependent on the Gate input level remaining in the LOW state for the single-shot mode. Another special condition is introduced in the singleshot mode. If L = M = "0" (Dual 8-bitl or N = "0" (Single 16-bit), the output goes LOW on the first clock received during or after counter initialization. The output remains LOW until the operating mode is changed or non-"O" data is written into the counter latches. Time-outs continue to occur at the end of each clock period. Time Interval Modes The time interval modes are provided for those applications which require more flexibility of interrupt generation and counter initialization. Individual interrupt flags are set in these modes as a function of both counter time-out and transitions of the Gate input. Counter initialization is also affected by interrupt flag status. The output signal is not defined in any of these modes, but the counter does operate in either single 16-bit or dual 8-bit modes as programmed by CRX2. Other features of the time interval modes are outlined in Table 7. The three differences between single-shot and continuous timer modes can be summarized as attributes of the single-shot mode: If CRX5 = "0", as shown in Table 7 and Table 8, an interrupt is generated if the Gate input returns LOW prior to a time-out. If counter time-out occurs first, the counter is recycled and continues to decrement. A bit is set within the timer on the initial time-out which precludes further individual interrupt generation until a new counter initialization cycle has been completed. When this internal bit is set, a negative transition of the Gate input starts a new counter initialization cycle. (The condition of Gj .T· TO is satisfied, since a time-out has occurred and no individual interrupt has been generated.) 1. Output is enabled for only one pulse until it is reinitialized. 2. Counter Enable is independent of Gate. 3. L = M = "0" or N = "0" disables output. Aside from these differences, the two modes are identical. Frequency Comparison or Period Measurement Mode (CRX3 = "1", CRX4 = "0") The frequency comparison mode with CRX5 = "1" is straightforward. If time-out occurs prior to the first negative transition of the Gate input after a counter initialization cycle, an individual interrupt flag is set. The counter is disabled, and a counter initialization cycle cannot begin until the interrupt flag is cleared and a negative transition on G is detected. Any of the timers within the PTM may be programmed to compare the period of a pulse (giving the frequency after calculations) at the Gate input with the time period required for counter time-out. A negative transition of the Gate input enables the counter and starts a counter 5·128 F6840/F68A40/F68B40 Table 7 Timer Interval Modes, CRX3 = "1" CRX4 CRXs Application Condition for Setting Individual Interrupt Flag 0 0 Frequency Comparison Interrupt Generated if Gate Input Period (l/F) is less than Counter Time-Out (TO) 0 1 Frequency Comparison Interrupt Generated if Gate Input Period (l/F) is greater than Counter Time-Out (TO) 1 0 Pulse Width Comparison Interrupt Generated if Gate Input "Down Time" is less than Counter Time-Out (TO) 1 1 Pulse Width Comparison Interrupt Generated if Gate Input "Down Time" is greater than Counter Time-Out (TO) Table 8 Frequency Comparison Mode, CRX3 = "1", CRX4 = "0" Control Register Bit 5 (CRXs) Counter Initialization Counter Enable Flip-Flop Set (CE) Counter Enable Flip-Flop Reset (CE) Interrupt Flag Set (1) 0 GI . I· ICE + TO, CE) + R GI' W' R· I W+ R+ I GI Before TO 1 GI' I + R GI· W' R· I W+R+ I TO Before GI Counter Enable Flip-Flop Reset (CE) Interrupt Flag Set (I) -I represents the interrupt for a given timer. Table 9 Pulse Width Comparison Mode, CRX3 Control Register Bit 5 (CRXs) Counter Initialization = "1", CRX4 = "1" Counter Enable Flip-Flop Set (CE) 0 GI' 1+ R GI' W' R· I W+R+I+G Gt Before TO 1 GI . 1+ R GI· W' R· I W+R+I+G TO Before Gt G = Level sensitive recognition of Gate Input Pulse Width Comparison Mode (CRX3 = "1", CRX4 = "1") This mode is similar to the frequency comparison mode except that a positive, rather than negative, transition of the Gate input terminates the count~ With CRXs = "0", an individual interrupt flag will be generated if the "0" level pulse applied to the Gate input is less than the time period required for counter time-out. With CRXs = "1 ", the interrupt is generated when the reverse condition is true. initialization cycle - provided that other conditions as noted in Table 8 are satisfied. The counter decrements on each clock signal recognized during or after counter initialization until an interrupt is generated, a write timer latches command is issued, or a Timer Reset condition occurs. It can be seen from Table 8 that an interrupt condition will be generated if CRXs = "0" and the period of the pulse (single pulse or separately measured repetitive pulses) at the Gate input is less than the counter time-out period. If CRXs = "1 ", an interrupt is generated if the reverse is true. As can be seen in Table 9, a positive transition of the Gate input disables the counter. With CRXs = "O",-it is therefore possible to obtain directly the width of any pulse causing an interrupt. Similar data for other time interval modes and conditions can be obtained, if two sections of the PTM are dedicated to the purpose. Assume now with CRXs = "1" that a counter initialization has occurred and that the Gate input has returned LOW prior to counter time out. Since there is no individual interrupt flag generated, this automatically starts a new counter initialization cycle. The process will continue with frequency comparison being performed on each Gate input cycle until the mode is changed, or a cycle is determined to be above the predetermined limit. 5-129 F6840/F68A40/F68840 Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature Range - TL to TH F6840P,S/F68A40P,S/F68840P,S F6840CP,CS/F68A40CP,CS F6840DL F6840DM Storage Temperature Range Thermal Resistance Plastic Package Ceramic Package -o.3V,+7.0.V -0.3 V, +7.0 V 0° -40° -55° -55° -55° C, C, C, C, C, +70° C +85° C +85° C +125° C +150° C 115° C/W 60° C/W Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the deVIce at these or any other conditions above those Indicated in the operational sections of this specification is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Symbol Vee = 5.0 V ±5%, Vss = 0, TA = TL Signal Characteristic to TH, unless otherwise noted. Min VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage -0.4 liN Input Leakage Current ITSI 3-State (OFF State) Input Current Do-D7 VOH Output HIGH Voltage Do-D7 Other Outputs VOL Output LOW Voltage Do-D7 01-03, IRQ ILOH Output Leakage Current (OFF State) (IRQI PD Power Dissipation CIN Input Capacitance COUT Output Capacitance Typ Max Test Condition V 0.8 V 1.0 2.5 }lA VIN = 0 to 5.25 2.0 10 }lA VIN = 0.4 to V ILoad ILoad 0.4 0.4 V ILoad ILoad = 3.2 mA 1.0 10 }lA VOH = 2.4 V 470 700 mW 2.4 2.4 Do-D7 All Other Inputs 12.5 7.5 0,,02,03 10 IRQ 5.0 5-130 Unit V 2.4 V = -205 }lA, = 200 }lA = 1.6 mA, VIN = 0, TA = 25°C, f=1.OMHz pF VIN = 0, TA = 25°C, f = 1.0 MHz pF F6840/F68A40/F68B40 Bus Timing Characteristics Read (Figure 2) F6840 F68B40 F68A40 Min Max Min Max Min Max Unit tcycE Enable Cycle Time 1.0 10 0.666 10 0.5 10 /los PWEH Enable Pulse Width, HIGH 0.45 4.5 0.2S0 4.5 0.22 4.5 PWEL Enable Pulse Width, LOW 0.43 0.2S0 0.21 /los tAS Set-up Time, Address and R/W valid to enable positive transition 160 140 70 ns Symbol Characteristic /los ns tOOR Data Delay Time tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 10 ns tEr, tEt Rise and Fall Time for Enable input 320 1S0 220 25 25 25 ns Write (Figure 3) tcycE Enable Cycle Time 1.0 10 0.666 10 0.50 10 /los PWEH Enable Pulse Width, HIGH 0.45 4.5 0.2S0 4.5 0.22 4.5 /los PWEL Enable Pulse Width, LOW 0.43 0.2S0 0.21 tAS Set-up Time, Address and R/W valid to enable positive transition 160 140 70 ns /loS tosw Data Set-up Time 195 SO 60 ns tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 10 ns tEr, tEt Rise and Fall Time for Enable input Fig. 2 25 25 Fig. 3 Bus Read Timing Characteristics (Read Information from PTM) 25 ns Bus Write Timing Characteristics (Write Information into PTM) 1----tcycE---..j E E RS,C:S,RiW DATA BUS 5·131 F6840/F68A40/F68B40 AC Characteristics (Figures 4-8) F6840 Symbol Characteristic Min F68A40 Max Min Max F68B40 Min Max Unit tr, tf Input Rise and Fall Times C,G and RESET PWL Input Pulse Width LOW C,G and RESET tcyc E +lsu +thd tcycE +lsu +thd tcycE +tsu +thd ns PWH Input Pulse Width HIGH C,G tcycE +tsu +thd tcycE +tsu +thd tcycE +tsu +thd ns tsu Input Set-up Time (Synchronous Mode) C,G and RESET C3 (78 Prescaler Mode only) 200 120 75 ns thd Input Hold Time (Synchronous Mode) C,G and RESET C3 (+8 Prescaler Mode onlYI 50 50 50 ns tcmos Output Delay, 01-03 (VOH = 2.4 V, Load B) (VOH = 2.4 V, Load D) (VOH = 0.7 Vee, Load OJ TTL MOS CMOS tlR Interrupt Release Time leo tcm , tr and tf -:s: 1 x Pulse Width or 1.0 fis, whichever Fig.4 IS 1.0' Fig. 7 Input Pulse Width Low 460 450 1.35 340 340 1.0 ns ns !J.s 1.2 0.9 0.7 !J.s Output Delay 2.0 V Input Pulse Width High Fig.8 Fig.6 700 450 2.0 smaller. PWL Fig.5 0.500' !J.s 0.666' IRQ Release Time Input Set-up and Hold Times _ E~_tl")~ ~.4V IRQ 5-132 --------' F6840/F68A40/F68840 Fig. 9 Ordering Information Bus Timing Test Loads Load A (Do-D7) 5.0 V TEST POINT --<,-......--KI'--.... Speed Order Code Temperature Range 1.0 MHz F6840P,S F6840GP,GS F6840DL F684DDM DOG -40° G -55° C -55° C 1.5 MHz F68A4DP,S DOG to +7DoG F68B4DP,S DOC to +7DoC 2.D MHz 130 pF P Load B (0,,0,.0,) VCCOF DEVICE UNDER TEST RL=1.25k TEST POINT --<,-......--KI---. 40 pF Load C (IRQ Only) 5.0 V ~3 k TESTPOINT~ 1DDP'I Load 0 (CMOS Load) TEST POINT 1 1 3DPF 5·133 = Plastic package, S = Ceramic package to +700G to +85° G to +85° C to +125°C F6840/F68A40/F68840 5-134 FAIRCHILD A Schlumberger Company F6844 Direct Memory Access Controller Microprocessor Product Description Connection Diagram 40·Pln DIP The F6844 Direct Memory Access Controller (DMAC) transfers data directly between memory and peripheral device controllers. In bus-organized systems, such as those based on the F6800 microprocessor, the DMAC, rather than the MPU, controls the address and data buses. vss E lID CSiTxAKB RIW DORNT Ao I5IIiTT DJmII T.AKA The DMAC bus interface includes select, read/write, interrupt, transfer request/grant, and bus interface logic to permit data transfer over an 8-bit bidirectional data bus. The F6844 functional configuration is programmed through the data bus. The internal structure provides for control and handling of four individual channels, each of which is separately configured. Programmable control registers provide control for the transfer location and length, individual channel control and transfer mode configuration, priority of servicing, data chaining, and interrupt control. Status and control lines serve the peripheral controllers. TX!ITII ilIQlDENII T.ROo T.RO, TxRQ2 T.RO. Do D, D. D. D. D, The mode of transfer for each channel can be programmed as cycle-stealing or burst transfer. Typical applications include use with the F6856 Synchronous Protocol Communications Controller, the F6854 Advanced Data Link Controller, and the F68488 IEEE-488 Bus Controller. • • • • • • • (Top Vlow) F6844 Signal Functions AO A, Four DMA Channels, Each Having a 16·BII Address Register and a 16·Blt Byte Count Register 2M Byte/Sec Maximum Data Transfer Rate Selection of Fixed or Rotating Priority Service Control Separate Control Bits for Each Channel Data Chain Function Address Increment or Decrement Update Programmable Interrupts and DMA End to Peripheral Controllers CSIT.AKB DORNT DROH A. A. DROT A. IROIDEND As E RES Ao ADDRESS A, RIW Ao T.AKA A. TxRQo A,o TxRQ1 Au A,. A,. TxRQ2 F8844 TxRQ3 fim A,. A" DO D, D. DATA D. D. Ds D. D, 5·135 V,, F6844 (DEN D) signal is directed to the peripheral controller and an interrupt request (IRQ) goes to the MPU. The interrupt control register enables these interrupts; the IRQ/DEND flag bit is read from this register. Functional Description The DMAC has 15 addressable registers, of which eight are 16 bits In length (see Figure 1). Each channel has a separate address register and a byte count register, each of which is 16 bits. There are four channel control registers with three common general control registers (priority, interrupt, and data chain). Chaining of data transfers is controlled by the data chain register. When enabled, the contents of the address and byte count registers for channel 3 are put into the registers of the channel selected for chaining as its byte count register becomes zero. This allows for repetitively reading or writing a block of memory. To prepare a channel for direct memory access (DMA), the address registers must be loaded with the starting memory address and the byte count register loaded with the number of bytes to be transferred. The bits in the channel control register establish the direction of the transfer, the mode, and the address increment or decrement after each cycle. Each channel can be set for one of three transfer modes: three-state control (TSC) steal, halt steal, or halt burst. Two read-only status bits In the channel control register indicate when the channel Is busy transferring data and when the DMA transfer is complete. During the DMA mode, the DMAC controls the address bus and data bus for the system as well as provides the R/W line and a signal to be used as valid memory address (VMA). When a peripheral device controller desires a DMA transfer, it issues a transfer request. Assuming this request is enabled and meets the test of highest priority, the DMAC issues a DMA request. When the DMAC receives the DMA grant (DGRNT) input, it gives a transfer acknowledge (TxAKA or TxAKB) to the peripheral device controller, at which time the data is transferred. When the channel byte count register equals zero, the transfer is complete, a DEND is given to the peripheral device controller, and an IRQ is given to the MPU. The priority control register enables the transfer requests from the peripheral controllers and establishes either a fixed priority or rotating priority scheme of servicing these requests. When the DMA transfer for a channel is complete (the byte count register is zero), a DMA end 5-136 F6844 Fig. 1 Block Diagram RtW Ao A1 A2 A3 A4 As A6 A7 Aa Ag A10 All A12 A13 A14 A15 3 4 5 6 7 8 9 10 11 12 13 14 15 18 17 18 19 iim/llEJilD 33 CSITx AKB 2 ...- - - 4.....-1 Do 28 0,27 0,28 03 25 0424 05 23 0622 Dr 21 32 TxRQO DRQH 36 DRQT 37 DGRNT 38 RES 39 E40 ~------------------~ REQUEST, GRANT, TIMING CONTROL TRANSFER REQUESTI ACKNOW· 29 TxRQ, LEDQE 35 TxAKA VSS=PIN 1 VOO= PIN 20 5·137 F6844 Signal Descriptions The F6844 input and output signals are described in Table 1. Table 1 F6844 Signal Functions Mnemonic Pin No. Description Name Address Ao-A4 4-8 Address In the MPU mode, the signals are hlgh·impedance inputs used to address the DMAC registers. In the DMA mode, these outputs are set to the contents of the address register for the channel being processed. A5-A 15 9-19 Address These output lines are in the high·impedance state during the MPU mode. In the DMA mode, these lines are outputs that are set to the contents of the address register for the channel being processed. 28-21 Bidirectional Data The eight bidirectional lines provide data transfer between the DMAC and the MPU. The data bus output drivers are three-state devices that remain in the high-impedance state except when the MPU performs DMAC read operations. Data Do-D7 Control CSlTxAKB 2 Chip Select/ Transfer Acknowledge B This signal is an output in the four-channel mode during the DMA transfer. At all other times, it is a high-impedance, TTLcompatible input used to address the DMAC. The DMAC is selected when CSlTxAKB is low. Valid memory address (VMA) must be used in generating this input to prevent false selects. Transfers of data to and from the DMAC are then controlled by the E, read/write, and Ao-A4 addres~nes. In the four-channel mode, when TxAKB is needed, the CS gate must have an opencollector output (a pull-up resistor should not be used). In the two-channel mode, CSlTxAKB is always an input. DGRNT 38 DMA Grant A high-impedance input signal to the DMAC, providing control of the system buses. In the three-state control (TSC) steal mode, the signal comes from the system clock drive circuit (DMA grant), indicating that the clock is being stretched. For the halt steal or halt burst mode, this signal is the bus available (BA) from the MPU, indicating that the MPU has halted and transferred control of its buses to the DMAC. For a design involving TSC steal and halt mode transfers, this input must be the logical OR of the clock-driven DMA grant and the MPU BA. DRQH 36 DMA Request Halt Steal This active-low output requests a DMA transfer for a channel programmed for the halt steal or halt burst transfer mode. The signal is connected directly to the MPU HALT input and remains low until the last byte transfer has begun. 5-138 F6844 Table 1 F6844 Signal Functions (Cont.) Mnemonic E R/W Pin No. Name Description 37 DMA Request Three·State Control Steal This active·low output requests a DMA transfer for a channel configured for the TSC steal transfer mode. The signal is connected to the system clock driver, requesting a cp1 clock stretch. It remains in the low state until the transfer has begun. 40 Direct Memory Access The DMAC register I/O transfers, channel request line sampling, and gating of other control signals to the system are done internally in conjunction with the E high·impedance input. This input must be the system memory clock (a nonstretched E clock). 33 Interrupt Request/ DMA End A TTL·compatible, active·low output used to interrupt the MPU and to signal the peripheral controller that the data block transfer has ended. If the interrupt has been enabled, the IRQIDEND line goes low after the last DMA cycle of a transfer. An open'collector gate must be connected to DGRNT and IRQIDEND to prevent false interrupts from the DEND signal when interrupts are not enabled. 39 Reset The RES input resets the DMAC from an external source. In the low state, the R"ES input causes all registers, except address and byte count, to be reset to the logic 0 state. This disables all transfer requests, masks all interrupts, disables the data chain function, and puts each channel control register into the condition of memory write, halt steal transfer mode, and address increment. 3 Read/Write A TTL·compatible signal that is a high·impedance input in the MPU mode and an output in the DMA mode. In the MPU mode, it controls the direction of data flow through the DMAC input/output data bus interface. When read/write is high (MPU read cycle) and the chip is selected, DMAC data output buffers are turned on and a selected register is read. When it is low, the DMAC output drivers are turned off and the MPU writes into a selected register. In the DMA mode, read/write is an output to drive the memory and peripheral controllers. Its state is determined by bit 0 of the channel control register for the channel being serviced. When read/write is high, the memory is written into the peripheral controller. When it is low, the peripheral controller is read and its data stored in the memory. In the DMA mode, the DMAC data buffers are off, so data is not available on the data bus (Do-D7)' 5·139 • F6844 Table 1 F6844 Signal Functions (Cont.) Mnemonic TxAKA TxRQo-TxRQ3 Pin No. 35 32-29 Description Name Transfer Acknowledge A This signal is a TIL-compatible output used in conjunction with the CS/TxAKB line to select the channel to be strobed for transfer, and to give the DMA end signal. In the two-channel mode, only TxAKA is used to select channel 0 or 1, and CS/TxAKB is always an input. Transfer Request Each of the four channels has its own high-impedance input request for transfer line. The peripheral controller requests a transfer by setting its TxRQ line high (a logic 1). The lines are sampled according to the priority and enabling established in the priority control register. In the halt steal mode, and the first byte of the halt burst mode, the TxRQ signals are tested on the positive edge of E and the highest priority channel is strobed. Once strobed, the TxRQs are not tested again until that channel's data transfer is finished. In the succeeding bytes of the halt burst mode transfer, the TxRQ is tested on the negative edge of E, and data is transferred on the next E cycle if the TxRQ signal is high. TxSTB 34 Transfer Strobe This output signal is an acknowledgement to the peripheral controller, and controls transfer of data to or from memory. The transfer strobe is also used as the VMA signal in the DMA mode. In a one·channel system, TxSTB can be inverted and run to the peripheral controller acknowledge input. In a two- or fourchannel system, TxSTB enables the depode of TxAKA and C§/TxAKB to select the device controller to be acknowledged. Power Voo Vss 20 1 Power Supply Nominal +5 Vdc Ground Common power and signal return 5·140 F6844 Bit 3, Address Up/Down-Bit 3 controls the change in the address register for each DMA cycle. If this bit is low, the address register is incremented each time the byte count register decrements. If the bit is high, the address register is decremented. DMAC Register Descriptions The 15 registers in the DMAC are read/write registers, although some of the bits are read·only status bits. Address Registers Each channel has its own individual 16·bit address register. Before a DMA transfer is begun, the starting address for the transfer must be loaded into the address register. Depending on the state of bit 3 of the channel control register, the address register is decremented or incremented after each byte transfer. Bit 6, Busy/Ready Flag- The busy/ready flag is a read· only status bit that indicates a DMA transfer is in process on that channel. This bit goes high at the beginning of the transfer and remains high until the IRQ/DEND has been low for one cycle (DMA end). The bit is then reset and the channel can again be configured for transfer. Byte Count Registers Each channel also has its own byte count register. Before the DMA transfer, this register must be loaded with the number of bytes to be transferred. Since it is 16 bits in length, the transfer can be up to 65,536 bytes of data. The byte count register is decremented at the beginning of each DMA cycle. Bit 7 DMA End (DEND) Flag- The DEND bit indicates that a DMA block transfer has ended. This bit is set at the same time the busy/ready flag is reset. The DEND bit is reset by the MPU reading the channel control register. This bit causes an interrupt if enabled in the interrupt control register. Channel Control Registers The control of each channel's DMA transfer is programmed into its channel control register. Bits 4 and 5 are unused. Priority Control Register The priority control register establishes priority and enables the transfer requests. Bits 4, 5, and 6 are unused. Bit 0, Read/Write (RIW)- The direction of the DMA transfer is controlled by this bit. When it is high, the peripheral controller reads the memory. When it is low, the transfer is in the opposite direction, thus writing into the memory. The system RfW line is in the same state as this R/W bit in the DMA mode. The device controller must change the sense of its R/W input during the DMA mode. Bits 0-3, Request Enable (RE o_3 ) - The four channels are individually enabled by setting the respective RE bit high. A low on any of these bits disables recognition of the transfer request for that channel. The bit number represents the channel number; e.g., bit 2 is channel 2. Bit 7, Rotate Control- The DMAC priority service routine is selected by this rotate control bit. When it is low, the fixed mode is selected. Channel 0 has the highest priority, channel 1 the next highest, etc. When this bit is high, a rotating routine is used: initially, it is the same as in the fixed mode, but once a channel has been serviced, it moves to the lowest priority and those that were below it advance to the next higher priority. Bit 1, Burst/Steal- This bit, along with bit 2, selects the mode of the DMA transfer. With bit 1 high, the burst mode is selected. A low selects the steal mode. B2, TSC/Halt- This bit helps select the mode of DMA transfer. When the bit is high, the TSC mode is selected. When low, the halt mode is selected. A TSC burst mode is illegal for F6800·family processors due to restrictions on <1>1 clock stretching for these products. Interrupt Control Register An interrupt is caused by a channel completing its DMA block transfer. The DEND (channel control register bit 7) flags this condition for each channel. Bits 4, 5, and 6 are unused. The mode selection for bits 1 and 2 is as follows: Blt2 Bit 1 DMA Transfer Mode 0 0 1 0 1 0 Halt Steal Halt Burst TSC Steal (Illegal) Bits 0-3, IRQ/DEND Enable (DIE o_3 ) - Each channel is separately enabled to cause the interrupt. A high enables an interrupt from the channel; a low masks the interrupt. The bit number corresponds to the channel number; e.g., bit 2 is channel 2. 5·141 F6844 Bit 7, IRQ/DEND Flag- This read-only bit indicates an IRQ is requested of the MPU when the signal is high. If the interrupt is enabled (DIE is a 1) when a channel's DEND flag (channel control register bit 7) goes high, the IRQIDEND flag bit also goes high. It is reset by the MPU reading the channel control register that caused the interrupt. CS/TxAKB becomes a chip select in the MPU mode and a transfer acknowledge B in the DMA mode. With bit 3 low, the two-channel mode is selected, and the CS/TxAKB line is always a chip select, both for the MPU and the DMA mode. Initialization During a power-on sequence, the DMAC'is reset through the RES input. All registers, except the address and byte count, are set to a logic 0 state. This disables all requests and the data chain function, while masking all interrupts. The address, byte count, and channel control registers must be programmed before the respective transfer request bit is enabled in the priority control register. Data Chain Register Repetitive reading or writing of a block of memory can be done in the data chain function. A DMA transfer cannot be active on channel 3 during the data chain. Bits 4 through 7 are unused. Bit 0, Data Chain Enable (DCE)- The data chain function is enabled when this bit is high. Transfer Modes Three methods are used for a DMA transfer, determined by the data transfer rate required, the number of channels attached, and the hardware complexity allowable. Refer to Figure 2 (TSC Steal Mode), Figure 3 (Halt Steal Mode), and Figure 4 (Halt Burst Mode) for an illustration of the three DMA transfer methods. Bits 1 and 2, Data Chain Channel Select A, B (DCA, DCB)- The channel updated by data chaining is selected by bits 1 and 2 as follows: DCB Blt2 DCA Blt1 Channel # o o o 1 o 1 2 1 (Illegal) o 1 1 Two of the modes, TSC steal and halt steal, are accomplished by cycle stealing from the MPU. Cycle stealing, in the TSC steal mode, is initiated by the DMAC bringing the DRQT line low. This line goes to the system clock driver, which returns a high on DGRNT on the rising edge of the system ¢1 clock. The DGRNT signal must cause the address control and data lines to go to the high-impedance state, at which time the DMAC supplies the address from the address register of the requesting channel. It also supplies the RIW signal as determined from the channel control register. After one byte is transferred, control is restored to the MPU. This method stretches the ¢1 and ¢2 clocks while the DMAC uses the memory (see Figure 5). The data chain function is performed by transferring the contents of channel 3 address and byte count registers into the respective registers of the channel selected by bits 1 and 2. The transfer occurs during the cycle of E following the byte count register having decremented to zero. Bit 3, TwolFour Channel Select (214)- Bit 3 configures the DMAC to handle two or four channels. When high, this bit selects the four-channel mode, in which the 5·142 F6844 Fig. 2 TSC Steal Mode Timing E MPU TxRQ DGANT ______________________-J TxAKA TxAKB Ao·A15. RM A.·A•• R/W --------------------------------\.-+__________-+.J------------------------------------Y----------Y------------"\----4---------4-----< ~--~----~---~- 5·143 F6844 Fig. 3 Halt Steal Mode Timing E DMA TxRQ / DGRNT / TxAKA \ \ TxAKB X X X X X X / / \ \~--- ./ 5-144 X X X X \\..------------ F6844 Fig. 4 Hall Burst Mode Timing _n. ..! ~ ~~ ~ _I MPU DUMMY DEAD ~ TxRQ DGRNT / Tl(AKA • \ / TxAKB X X X j \ X \ The second mode employing cycle stealing is the halt steal mode. This method actually halts the MPU instead of stretching the c/>1 clock for the transfer period. This mode is initiated by the DMAC bringing the DRQH line low. This line connects to the MPU HALT input. The MPU bus available (BA) line is the DGRNT input to the DMAC. While the MPU is halted, its address bus, data bus, and R/W lines are in the high·impedance state. The DMAC supplies the address and Riw line. After one byte is transferred, the HALT line is returned high and the MPU regains control. In this mode, the MPU stops internal ... _--- activity and is removed from the system while the DMAC uses the memory. The third mode of transfer is the halt burst. This mode is similar to the halt steal mode, except that the transfer does not stop with one byte. The MPU is halted while an entire block of data is transferred. When the channel byte count register equals zero, the transfer is complete and control is returned to the MPU. This mode gives the highest data transfer rate, at the expense of the MPU being inactive during the transfer period. 5·145 F6844 Fig. 5 Flowchart of DMAC Operation WAIT FOR TxRQ INPUT CHECKEDEj'" WAIT FOR TxRQ INPUT ...------1 BURST MODE 5-146 F6844 DMAC Programming Model The following programming model outlines channel preparation for DMA transfer, request enabling, data chain register programming, and register descriptions (see Table 2). Table 2 DMAC Programming Model Address (Hex) Register Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Blt1 Bit 0 Channel Control 1x' DMA End (DEND) Flag Busy/Ready Flag Not Used Not Used Address UpIDown TSCI Halt Burstl Steal Read/Write (R/iN) Priority Control 14 Rotate Control Not Used Not Used Not Used Request Enable #3 (RE 3l Request Enable #2 (RE2l Request Enable #1 (REI) Request Enable #0 (REo) Interrupt Control 15 IRQ/DEND Flag Not Used Not Used Not Used IRQ/DEND Enable #3 (OlEa) IRQ/DEND Enable #2 (DIE2l IRQIDEND Enable #1 (DIE 1) IRQIDEND Enable #0 (OlEo) Data Chain 16 Not Used Not Used Not Used Not Used Two/Four Channel Select (2/4) Data Chain Channel Select B Data Chain Channel Select A Data Chain Enable Register 'The x represents the binary eqUIvalent of the channel desired. Channel Control Register REo_a Bit 7 - Is set at end of DMA block transfer; reset by MPU reading the channel control register. Busy/Ready Bit 6- Status bit set when in transfer; Flag cleared after DMA end. Bits 0-3- High = enable transfer request for the channel; low request disabled. = Interrupt Control Register IRQIDEND Flag Bit 7- This flag is set by DEND in channel control registers when enabled; reset by reading the register that caused it to be set. Bits 0-3- High enable IRQ by DEND for the channel; low = IRQ masked. Address UpIDown Bit 3- High =decrement address register for each byte; low increment. OlEo_a TSC/Halt Bit 2- High = select TSC mode; low = halt modes. Data Chain Register Burst/Steal R/W = = = Bit 0- High =device controller reads Bit 1- High select burst mode; low steal modes. memory; low = write into memory. = Two/Four Channel Bit 3- High =4-channel mode; low =2channel. Data Chain Channel Select Bits 2, 1- Binary equivalent of channel to be updated by chaining. Data Chain Enable Bit 0- High = enable data chain function; low = disabled. Priority Control Register Rotate Control Bit 7 - High = use rotate routine; low = fixed: 0, 1, 2, 3 priority. 5-147 • F6844 The two 8-bit bytes that form the registers in Table 3 are placed in consecutive memory locations, making it very easy to use the MPU index register in programming them. Preparation of a channel for a DMA transfer requires: 1. Load the starting address into the address register. 2. Load the number of bytes into the byte count register. 3. Program the channel control register for the transfer characteristics: direction (bit 0), mode (bits 1 and 2), and the address update (bit 3). Table 3 Address and Byte Count Registers Register Channel Address (Hex) The channel is now configured. To enable the transfer request, set the appropriate enable bit (bits 0-3) of the priority control register, as well as the rotate control bit. Address High Address Low Byte Count High Byte Count Low 0 0 0 0 0 1 2 3 If an interrupt on DEND is desired, the enable bit (bits 0-3) of the interrupt control register must be set. Address High Address Low Byte Count High Byte Count Low 1 1 1 1 4 5 6 7 Address High Address Low Byte Count High Byte Count Low 2 2 2 2 Address High Address Low Byte Count High Byte Count Low 3 3 3 3 If data chaining for the channel is necessary, it is programmed into the data chain register and the appropriate data must be written into the address and byte count registers for channel 3. A comparison of the response times and maximum transfer rates is shown below. The values shown are for a system clock rate of 1 MHz. Mode Response Time I/-ls) Maximum Transfer Rate I/-ls/byte) Halt Burst Halt Steal TSC Steal 3.5-15.53.5-15.52.5-3.5 5-154 ·These values depend upon the cycle in process. 5-148 8 9 A B C D E F F6844 System Description Fig. 6 One·channel Operation IRQ (OPEN COLLECTOR) The DMAC hardware configuration is designed for a one·, two·, or four·channel system. IRQ, DEND, TxAK Generation Derivation of the IRQ, DEND, and TxAK signals for one·, two·, and four·channel DMA is shown in Figures 6, 7, and 8. The IRQ signal, if enabled, is asserted by the DMA to interrupt the MPU whenever a DMA block transfer is completed. The TxAK signal is asserted during each DMA cycle and is used to handshake with a peripheral controller each time a DMA byte transfer occurs. The DEND signal is used to handshake with a peripheral controller each time a DMA block transfer is complete. DENDo --==-..... T,AKo I - - D o - -..... TxAKA NC •• CSIT,AKB Each circuit uses DMA GRANT to demultiplex the IRQIDEND DMAC output to ensure that the system IRQ is asserted at the proper time, only during MPU operation. Whenever DMA GRANT is high, IRQ is negated. Fig. 7 Two·channel System IRQ (OPEN COLLECTOR) The circuits also generate DEND and TxAK for the proper channel, gated by TxSTB. DENDo The one·channel DMA mode requires no channel decoding, so for this mode TxAK is derived from TxSTB directly, and TxSTB is used to demultiplex the IRQIDEND output for DEND generation. DEND, ..... TxAKo r--'\--l-,,~--t--- The two·channel mode circuit is similar to the one· channel circuit but uses TxAKA to identify the active channel and generate the appropriate channel signal. Fig. 8 CS/T,AKB Four·channel System IRQ (OPEN COLLECTOR) DGRNT T,AKAI----~ CS/T,AKB 1--...--+--1 ><~I---+--+---t- T,AKo 10--1.:>0----4--+--+- T,AK, 1O--I.:>O------....- + - T ,AK2 (OPEN COLLECTOR) ......-T,AK3 L~.!.!!Jo--[>O------CS 5·149 F6844 The four-channel circuit is functionally similar to the twochannel circuit but uses a 74LS139 to decode TxAKA and TxAKB for channel identification. Because the DMAC CS/TxAKB pin is bidirectional during four-channel operation, an open-collector gate must be used to drive CS to avoid drive contention. Table 4 Timing Characteristics The bus timing characteristics of the F6844 are described in Table 4 and illustrated in Figure 9. The DMA timing characteristics are presented in Table 5. (Refer to Figures 10 through 15 for the associated timing diagrams.) Figure 16 illustrates the test loads and Figure 17 the CS/TxAKB source current test circuit. Bus Timing Characteristics I Characteristic Min t AS Address Setup Time Ao-A4' R/IN, CS 160 ns tAHI Address Input Hold Time Ao-A4' R/IN, CS 10 ns tOOR Data Delay Time Do-D7 320 ns t ACC Data Access Time Do-D7 480 ns tOHR Data Output Hold Time Do-D7 Symbol Max Unit Read Timing 10 ns 160 ns 10 ns 195 ns 10 ns Write Timing t AS Address Setup Time Ao-A4, R/W, CS tAHI Address Input Hold Time Ao-A4, R/IN, CS tosw Data Setup Time Do-D7 tOHW Data Input Hold Time Do-D7 E Clock Timing teye Cycle Time 1000 ns PWE H Pulse Width - High 450 ns PWE L Pulse Width - Low 430 t~r, t~f Rise and Fall Time ns 25 5-150 ns F6844 Fig. 9 Bus Timing E Ao-Ao (INPUT) R/W (INPUT) eli (INPUT) (WRITE --"""" b.".,.,+----i-!..;.;;;;L - , . - - - - ----' 1"-""'"'"+--:--+1---''''" \ . - - - - ~~~~~~g~-------<1 0.8 v • -------------Table 5 DMA Timing Characteristics Symbol Characteristic Min Max 120 210 20 20 155 10 Unit t TOS1 TxRQ Setup Time, E Rising Edge t TOS2 TxRQ Setup Time, E Falling Edge t TOH1 TxRQ Hold Time, E Rising Edge tTOH2 TxRQ Hold Time, E Falling Edge tOGS DGRNT Setup Time tOGH DGRNT Hold Time tAD Address Output Delay Time A o-A 15, R/W, TxSTB t AHO Address Output Hold Time A o-A 15, R/W, TxSTB tATSO Address Three·State Delay Time A o-A 15, R/W 270 ns tATSR Address Three·State Recovery Time Delay Time, DRQH, DRQT tTK01 TxAK Delay Time, E Rising Edge t TK02 TxAK Delay Time, DGRNT Rising Edge t OE01 IRQIDEND Delay Time, E Falling Edge 270 375 400 190 300 ns tooo t OE02 IRQ/DEND Delay Time, DGRNT Rising Edge 190 ns ns ns ns ns ns ns 270 30 35 5-151 ns ns ns ns ns ns F6844 Fig. 10 TxRQ Inpul Timing Fig. 14 Address Three·slale Timing E (OR DGRNn _ _ _ _J A.·A". RiW-----+---<1 E (OR DGRNn Fig. 11 DGRNT Inpul Timing - 'ATSD~ - - - - - - - . . . . , , [ 2.4 V Ao·A15. R/W _ _ _ _ _ _ _ 0.4V ~ Selup Timing E \0.8V -1± DGRNT~--~i ~ Fig. 15 '1~'" TxAKB, IRQ/DEND OUlpul Timing from DGRNT Inpul 0.8 v DGRNT 2.0 V - - / tTKD2 Hold Timing CSfTxAKB ~~~=:CV \ 0.4 V tOED2 IRQ/DENO 2.4 V E ________ DGRNT 0.8 V Fig. 16 TeslLoads s.ov Fig. 12 DRQH, DRQT, TxAK OUlpul Timing J -- 2.0 V TEST POINT-t----1t-K~~ l- tOOD ) 03 r- trKD1 )j D4 • 2.4 0.4 V Tesl Pin Fig.13 Do·D 7 Address, IRQ/DEND Oulpul Timing E ~,. RIW. T.STB ---1---' 02 c 2.4 V 0.4 V 1'=...;..------~'r 5·152 C=pF R=kO 130 11.7 A o·A 15, RIW 90 16.5 CS/TxAKB 50 24 Others 30 24 F6844 Fig. 17 CS/TxAKB Source Current Test Circuit r----------,I I VDD I, cJU~PpJ:~T "0" "," ON : tcss DC AMPERE METER I I IL E Vss Vss eli INPUT - - " < t - - - - ' __ _ _ _ _ _ _ _ _ .J Absolute Maximum Ratings These are stress ratings only. and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Storage Temperature Operating Temperature Supply Voltage (Voo)' Input Voltage (V IN)' Thermal Resistance -55·C, +150·C O·C, +70·C -0.3 V, + 7.0 V -0.3 V, + 7.0 V 70·C/W 'With respect to Vss. DC Characteristics Symbol Characteristic VIH Input High Voltage VIL Input Low Voltage liN Input Leakage Current TxRO o- TxR0 3 , ~2 OMA, RES, OGRNT ITSI 3-State Leakage Current Ao-A ,5 , R/W, 0 0-0 7 VOH Output High Voltage 0 0-0 7 Ao-A ,5 , R/W All Others Min Typ Max Unit Vss+2.0 Voo V Vss-0.3 Vss+0.8 V 2.5 -10 10 Vss+2.4 Vss +2.4 Vss +2.4 jiA VIN=O to 5.25 V jiA VIN = 0.4 to 2.4 V V IL = -205 jiA IL= -145 jiA IL= -100 jiA V IL= 1.6 mA VOL Output Low Voltage less Source Current CS/TxAKB Po Power Dissipation C IN Input Capacitance E 0 0-0 7, CS/TxAKB, Ao-A4' R/W All Others 20 12.5 10 pF Output Capacitance 12 pF C OUT Vss +O.4 10 16 mA 500 1000 mW Voo= 5.0 V ± 5%, Vss= 0 V, TA = O·C to + 70·C, unless otherwise noted. 5-153 Condition VIN=O V VIN=O V, T A=25·C f= 1.0 MHz • F6844 Ordering Information Order Code F6844P F68A44P F68B44P Temperature Range ooe to ooe to ooe to + 70 + 70 + 70 0 0 0 e e e 5-154 FAIRCHILD A Schlumberger Company F6845/F6845A CRT Controller Microprocessor Product Description Connection Diagram The Fairchild F6845 CRT Controller (CRTC) provides an interface between a microprocessor (MPU) and a raster scan CRT device. The CRTC is used in microprocessor-based controller systems for CRT terminals in stand-alone or multiterminal configurations, including smart, programmable CRT terminals, video games, and Information displays. GND vs iiESlT HS lPSTB RAO MAO RAl MAl RA2 MA2 RA3 MA3 RA4 MA4 DO The F6845 CRTC is designed with an optimum hardware/software balance that achieves integration of all key functions and maintains flexibility. All keyboard functions, read/write operations, cursor movements, and editing are under microprocessor control. The F6845 provides video timing and refresh memory addressing. • • • • • • • • • • • • • • • • • Monochrome or Color CRT Applications Used with "Glass·Teletype", Smart, Programmable, Intelligent CRT Terminals; Video Games; Information Displays Alphanumeric, Semigraphic, and Full Graphic Capability Fully Programmable via Processor Data Bus; Timing can be Generated for Almost Any Alphanumeric Screen Format (e.g., 80 x 24, 72 x 64, and 132 x 20) Single + 5 V Supply F6800·Compatlble Bus Interface TTL·Compatlble Inputs and Outputs Start Address Register Provides Hardware Scroll (By Page, Line, or Characte., Programmable Cursor Register Allows Control of Cursor Format and Blink Rate Light Pen Register Refresh (Screen) Memory Can Be Multiplexed Between the CRTC and the MPU, Thus Removing the Requirements for Line Buffers or External DMA Devices Programmable Interlace or Non·lnterlace Scan Modes 14-Blt Refresh Address Allows up to 16K of Refresh Memory for Use In Character or Semlgraphlc Displays 5-Blt Row Address Allows up to 32 Scan·Llne Character Blocks 512K Address Space Is Available for Graphics System by Using Both the Refresh and Row Addresses Refresh Addresses are Provided During Retrace, Allow· Ing the CRTC to Provide Row Addresses to Refresh Dynamic RAM Programmable Skew for Cursor and Display Enable (DE) MAS 01 MAS 02 MA7 03 MAS D. MA9 05 MAlO 06 MAll 07 MA12 cs MA13 RS • DE CURSOR RNi vcc ClK Signal Functions DISPLAY" MEMORY ADDRESSING CRT { CONTROL 5·155 CURSOR F6845 Figure 1 Non-Interlace Raster Scan System Figure 2 Interlace Raster Scan System VERTICAL SCAN PERIOD VERTICAL RETRACE PERIOD _ _ EVEN NUMBER FIELD (FIRST) HORIZONAL SCAN PERIOD HORIZONTAL RETRACE PERIOD CRTC System Interface The CRTC generates the Signals necessary to interface a digital system to a raster scan CRT display. In this type of display, an electron beam starts in the upper left-hand corner, moves quickly across the screen, and returns. This action is called a horizontal scan. After each horizontal scan, the beam is incrementally moved down in the vertical direction until it has reached the bottom of the screen. At this pOint, one frame has been displayed, as the beam has made many horizontal scans and one vertical scan. Two types of raster scanning are used in CRTs: interlace and non-interlace (illustrated in figures 1 and 2). Noninterlace scanning consists of one field per frame. The scan lines in figure 1 are shown as solid lines, and the retrace patterns are indicated by the dotted lines. Increasing the number of frames per second decreases the flicker. Ordinarily, either a 50 or 60 frame-per-second refresh rate is used to minimize beating between the CRT and the power line frequency. This prevents the displayed data from weaving. Interlace scanning is used in broadcast TV and on data monitors where high-density or high-resolution data must be displayed. Two fields, or vertical scans, are made down the screen for each single picture or frame. The first field (even field) starts in the upper left-hand corner; the second (odd field) in the upper center. Both fields overlap as shown in figure 2, thus interlacing the two fields into a single frame. - - - - - ODD NUMBER FIELD (SECOND) ........... RETRACE in ASCII code and cannot be directly displayed as characters. A character generator ROM is typically used to convert the ASCII codes into the "dot" pattern for every character. The most common method of generating characters is to create a matrix of dots, x dots (columns) wide and y dots (rows) high. Each character is created by selectively filling in the dots. As x and y get larger, a more detailed character can be created. Two common dot matrices are 5 x 7 and 7 x 9. Many variations of these standards allow Chinese, Japanese, or Arabic letters instead of English. Since characters require some space between them, a character block larger than the character is typically used, as shown in figure 3. The figure also shows the corresponding timing and levels for a video Signal that would generate the characters. The CRTC generates the refresh addresses (MAO- MA1:Y, row addresses (RAo - RA4), and the video timing - vertical synchronization (VS), horizontal synchronization (HS), and display enable (DE), as illustrated in figure 4. Other functions include an internal cursor register that generates a cursor output when its contents compare to the current refresh address. A light pen strobe input signal allows capture of the refresh address in an internal light pen register. All timing in the CRTC is derived from the clock (ClK) input. In alphanumeric terminals, this signal is the character rate. The video rate, or dot clock, is externally divided by high-speed logic (TTl) to generate the ClK input. The highspeed logic also generates the timing and control signals necessary for the shift register, latch, and multiplexer control. To display the characters on the CRT screen, the frames must be continually repeated. The data to be displayed is stored in the refresh (screen) memory by the MPU controlling the data processing system. The data is usually written 5-156 F6845 Figure 3 Character Display on the Screen and Video Signal ONE CHARACTER CLOCK ~ 2 4 6 8 } CHARACTER DISPLAY ONE LINE 14 SCAN LINES 10 • 12 14 FIRST SCAN LI NE SECOND SCAN LlNE- Ir-r-~ '-r- r-I r- -1 ~J ~- r-~ lr- r-I ~ ... _I Figure 4 Typical CRT Controller Application ~~-'~~----~---------------------'AB L ___t--t---~-r-------~~~:;;Y-T.:--'DB PRIMARY BUS CURSOR DISPLAY ENABLE ROW ADDRESS HS VS The processor communicates with the CRTC through an 8-bit data bus by reading or writing into the 19 registers. The refresh memory address is multiplexed between the microprocessor and the CRTC. Data appears on a secon- dary bus separate from the processor's primary bus. The secondary data bus concept in no way precludes using the refresh RAM for other purposes. It looks like any other RAM to the processor. 5-157 F6845 scan line counters to the contents of. the programmable register file, AO - AH. For horizontal timing generation, comparisons result in the horizontal sync pulse (HS) of a frequency, position, and width determined by the registers, and the horizontal display signal of a frequency, position, and duration determined by the registers. Refresh Memory Contentions A number of approaches are possible for solving contentions in the refresh memory. 1. The processor always has priority. Generally, "hash" occurs, as the MPU and CATC clocks are not synchronized. 2. The processor has priority access anytime, but can be synchronized by an interrupt to perform accesses only during horizontal and vertical retrace times. 3. The processor is synchronized with the memory wait cycles (states). 4. The processor is synchronized to the character rate as shown in figure 5. The F6800 processor family works very well in this configuration, as constant cycle lengths are present. This method provides no overhead for the processor, as there is never a contention for a memory access. All accesses are transparent. The horizontal counter produces H clock, which drives the scan line counter and vertical control. The contents of the scan line register raster counter are continuously compared to the contents of the scan ·Iine address register. A coincidence resets the raster scan line counter and clocks the vertical counter. Comparisons of vertical counter contents and vertical registers result in a vertical sync (VS) pulse of a frequency, width, and position determined by the registers, and a vertical display of a frequency and position determined by the registers. The width of the VSYNC pulse is fixed at 16 raster lines In the F6845. The vertical control logic has other functions, including the following. The CATC is offered In two pin-compatible versions. This data sheet contains information describing both the F6845 CATC and the F6845A (upgraded) CATC. Complete software compatibility between both versions is maintained by programming all register bits in the F6845A, which are undefined/unused in the F6845, with zeros. The F6845 CATC consists of programmable horizontal and vertical timing generators, programmable linear address register, programmable cursor logic, light pen capture register, and control circuitry for interface to a processor bus. Figure 6 is a functional block diagram of the .CATC. 1. Generates row selects or raster address RAO - RA4 output from the raster count scan line for the corresponding interlace or non-interlace modes. 2. Extends the number of scan lines in the vertical total by the amount programmed in the vertical total adjust register. The linear address generator is driven by ClK and associates the relative positions of characters in memory with their positions on the CRT screen. Fourteen refresh memory address lines, MAO - MA13, are available for addressing up to four pages of 4K characters, eight pages of 2 K characters, etc. Using the start address register, hardware scroliing up to 16K characters is possible. The linear address generator repeats the same sequence of addresses for each scan line of a character row. All CATC timing is derived from the clock (ClK) input, usually the output of an external dot rate counter. Coincidence (CO) circuits continuously compare the contents of the horizontal, horizontal sync width, character row, and The cursor logic determines the cursor location, size, and blink rate on the CRT screen. All are programmable. Figure 5 Transparent Memory Configuration Timing Using F6800 MPU Where m, n are integers and tc is character period. The light pen strobe (lPSTB) going high causes the current contents of the address counter to be latched in the light pen register. The contents of the light pen register are subsequently read by the microprocessor. Internal CRTC registers are programmed by the microprocessor through the data bus, DO - D7' and the control signals RIW, CS, AS, and E. I I I I I......o----lcye = ru m ~ ~ ....~ :30.:; <.> ... o VI:> ;i c3 i= ~ II: W > ... ~ <.>:; W > DISPLAY PERIOD ... 0 o II: II: ., W ., :; :> :; ~ z Q:::E g ... C ~ ::r: z u:::i « B ~ ~ ~ :I: A NUMBER OF HORIZONTAL TOTAL CHAR. (Nht + t ) - - - - - - , NUMBER OF HORIZONTAL DISPLAYED CHAR. (Nhd)-----"l W z L L VERTICAL RETRACE PERIOD TOTAL SCAN LINE ADJUST (Nod)") 5·163 'TI c" c CiI 00 o ~ :J: o ::::!" ~ ::I I" HORIZONTAL TOTAL (RO) = (Nhl+1) x1c k-----------------------thl ~ HORIZONTAL DISPLAY (R1)Nhd x " ----------------------==:1---1 ~~~LSUl CLK I I I I II MAO·MA13· ~~~~~~~--~--~~--~ I 0 I I I I I I I I I I .g" I I III~ ~ / Nhd -1 I I HS I I ~ ::1 3 ·1 Nhd-1 I ~I CHARACTER -/ ~ I HORIZONTAL RETRACE I I I I I Nhd ~ Nhsp -1] ~...l....--I....---J Nhsp Nht I- HS PULSE WIDTH (R3)-I HORIZONTAL SYNC POSITION (R2) FRONT PORCH (SYNC DElAY) I I Nhsw x Ie BACK PORCH (SCAN DELAY) .... (J) "TI I" DISPENI ~ "I ~ Nole Timing is shown for first displayed scan row only. The initial MA is determined by the contents of start address register RI2/R I3. Timing is shown for R12/R 13 = O. 0.....-_ _ _ _ _"'-.. A "'-.. "'-...-_ _ _.....J U1 F6845 Figure 9 CRTC Vertical Timing IF = (N'II +1) x Ire:: + Nadj x lSI FIELD TIME 1 - - - - - - - - - - - - - - - - - - VERTICAL TOTAL (R4) + VERTICAL TOTAL ADJUST ( R 5 ) - - - - - - - - - - - - - - - - - + I ----1O~------------VERTICAL RETRACE CHAR~g~: --J..---I..----l.~~r-----l..----'--..l.r:: -.l---------'-............... 1-1 ...J..-_ _-.J....-_ _ N,sp -1 VERTICAL SYNC DELAY Nvsp I---- '·3"$1 Nvt -+I I I VERTICAL SCAN DELAY I I vs I I I I I I I DISPL~~ ENABLE I I I vs I (Odd Field) I •, (Even Field) I I I I I , I I I ,, , rI ,, ,, ~ h.r~~1 , Noles: 1. 2. ,-1 • "N ht must be an odd number for both interlace modes. ""Initial MA is determined by R12fR13 (start address registe~, which is zero in this timing example. "" "N sl must be an odd number for interlace sync and video mode. 3. , Refer to Figure 2· The odd field is offset V, horizontal scan time. Timing values are described In Table 9. Vertical sync pulse width can be programmed from 1 to 16 scan line times for the MC6845", 1. 5·165 I 1 r-t.~1 I ,, , , Nyt + 1 --J': . • F6845 Horizontal Total Register (RO) - This 8-bit write-only register determines the horizontal sync (HSYNC) frequency by defining the period in character times. It is the total of the displayed characters plus the nondisplayed character times (retrace) minus one. Horizontal Timing Summary -The difference between RO and R1 is the horizontal blanking interval (refer to figure 8). This interval in the horizontal scan period allows the beam to return (retrace) to the left side of the screen. The retrace time is determined by the monitor's horizontal scan components. Retrace time is less than the horizontal blanking . interval. Horizontal Displayed Register (R1) - This 8-bit write-only register determines the number of displayed characters per line. Any 8-bit number can be programmed so long as the contents of RO are greater than the contents of R1. A good rule of thumb is to make the horizontal blanking about 20% of the total horizontal scanning period for a CRT. In inexpensive TV receivers, the beam overscans the display screen so that aging of parts does not result in underscanning. Because of this, the retrace time should be about one-third the horizontal scanning period. The horizontal sync delay, HS pulse width, and horizontal scan delay are typically programmed with a 1:2:2 ratio. Horizontal Sync Position Register (R2) -This 8-bit write-only register controls the horizontal sync position, which defines the horizontal sync delay (Front Porch) and the horizontal scan delay (Back Porch). When the programmed value of this register is increased, the display on the CRT screen is shifted to the lef!. When the programmed value is decreased, the display is shifted to the right. Any 8-bit number can be programmed if the sum of the contents of R1, R2, and R3 is less than the contents of RO. Vertical Total Register (R4) and Vertical Total Adjust Register (RS) - The frequency of the VS pulse is determined by both the R4 and R5 registers. The calculated number of character line times is usually an integer plus a fraction to get exactly a 50 or 60 Hz vertical refresh rate. The integer number of character line times minus one is programmed in the 7-bit write-only vertical total register (R4). The fraction of character line times is programmed in the 5-bit write-only vertical total adjust register (R5) as a number of scan line times. Sync Width Register (R3) - This 8-bit write-only register determines the width of the vertical sync pulse and the horizontal sync pulse for the F6845A CRTC. The vertical sync pulse width is fixed at 16 scan line times for the F6845, and the upper four bits of this register are treated as "don't cares". The F6845A allows control of the VS pulse width for one to sixteen scan line times. Programming the upper four bits for one to fifteen selects pulse widths from one to fifteen scan line times. Programming the upper four bits as zeros selects a VS pulse width of 16 scan line times, allowing compatibility with the F6845. Vertical Displayed Register (RS) - This 7-bit write-only register specifies the number of displayed character rows on the CRT screen and is programmed in character row times. Any number smaller than the contents of the R4 register can be programmed into the R6 register. This horizontal width must be programmed because, were it fixed as an integral of character times, it would vary with the character rate and be out of tolerance for certain monitors. Vertical Sync Position Register (R7) - This 7-bit write-only register controls the position of vertical sync with respect to the reference. It is programmed in character row times. The value programmed in the register is one less than the number of computed character line times. When the programmed value of this register is increased, the display position of the CRT screen is shifted up. When the programmed value is decreased, the display position is shifted down. Any number equal to or less than the vertical total (register R4) can be used. Table 3 Cursor and DE Skew Control Table 4 Interlace Mode Register For both the F6845 and the F6845A, the HS pulse width can be programmed from one to fifteen character clock periods, thus allowing compatibility with the HS pulse width specifications of many different monitors. If zero is written into this register, then no horizontal sync is provided. Value 00 01 10 11 Skew No Character Skew One Character Skew Two Character Skew Not Available Bit 1 0 1 0 1 5-166 Bit 0 0 0 1 1 Mode Normal Sync Mode (Non-Interlace) Normal Sync Mode (Non-Interlace) Interlace Sync Mode I nterlace Sync and Video Mode F6845 Figure 10 Interlace Control SCAN LINE ADDRESS SCAN LINE ADDRESS SCAN LINE ADDRESS 0-------0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 --------0 0 0 --g-----t- 0_-& _ _ _ _ &_1 --&-----&0 0 -&-----9-o 0 0 0 0 4 6 - -& ~ --o--G- 2 3 -& - 4 o 0 --&-----9-- 5 o 0 --9-----.e--6 o 0 -.e------9--7 EVEN FIELD (a) NORMAL SYNC 2 1 ODD FIELD (b) INTERLACE SYNC Interlace Mode and Skew Register (R8) . The F6B45 only allows control of the interlace modes as programmed by the low order two bits of this write·only register. The F6845A controls the interlace modes and allows a program· mabie delay of zero to two character clock times for the display enable (DE) and cursor outputs. Table 3 describes operation of the cursor and DE skew bits. Cursor skew is controlled by bits 6 and 7 of Aegister AB, while DE skew is controlled by bits 4 and 5. Table 4 shows the available in· terlace modes; these modes are selected using the two low order bits of this 6·bit write·only register. In the normal sync mode (non·interlace), only one field is available, as shown in figures 1 and 10 (a). Each scan line is refreshed at the VSYNC frequency (e.g., 50 or 60 Hz). 0 0 -&-----&- 3 _S~-O-~S- 5 0 0 --&----.e-- 7 0------- --------1 --------3 --------5 --------7 EVEN ODD FIELD FIELD (e) INTERFACE SYNC AND VIDEO In addition, the programming of the CATC registers for interlace operation has the following restrictions. F6845 Programming Restrictions 1. The horizontal total register value, AO, must be odd (i.e., an even number of character times). Two interlace modes are available, as shown in figures 2, 10 (b) and 10 (c). The frame time is divided between even and odd alternating fields. The horizontal and vertical timing relationship VSYNC delayed by one·half scan line time) results in the displacement of scan lines in the odd field with respect to the even field. In the interlace sync mode, the same information is painted in both fields, as shown in figure 10 (b). This is a useful mode for filling in a character to enhance readability. 2. For interlace sync and video mode only, the max· imum scan line address, A9, must be odd (i.e., an even number of scan lines). 3. For interlace sync and video mode only, the vertical displayed register, A6, must be even. The program· med number, Nvd, must be one·half the actual number required. The even·numbered scan lines are displayed in the even field and the odd·numbered scan lines are displayed in the odd field. 4. For interlace sync and video mode only, the cursor start register, A10, and cursor end register, A11, must both be even or odd, depending in which field the cursor is to be displayed. F6845A Programming Restrictions 1. The horizontal total register value, AO, must be odd (i.e., an even number of character times). In the interlace sync and video mode, shown in figure 10 (c), alternating lines of the character are displayed in the even field and the odd field. This effectively doubles the given bandwidth of the CAT monitor. 2. To avoid an apparent flicker effect, care must be taken when using either interlace mode. This flicker effect is due to the doubling of the refresh time for all scan lines, since each field is displayed alaernately and can be minimized with proper monitor design (e.g., longer perSistence phosphors). For the interlace sync and video mode only, the ver· tical displayed register, A6, must be even. The pro· grammed number, Nvd, must be one·half the actual number required. Maximum Scan Line Address Register (R9) . This 5·bit write· only register determines the number of scan lines per character row, including the spacing, thus control· ling operation of the row address counter. The programmed value is a maximum address and is one less than the number of scan lines. 5·167 • F6845 Figure 11 Cursor Control I, I, ON ~: Table 5 Cursor Start Register OFF I I ON Bit 6 Bit 5 Cursor Display Mode 0 0 Non-blink 1 0 Cursor Non-display 1 0 Blink, 1/16 Field Rate 1 1 Blink, 1/32 Field Rate Example of Cursor Display Mode :'-BLINK PERIOD= , 1 6 OR 32 TIMES FIELD PERIOD I 111 !- !7 +-1-++-++-1- ~O~ 11~ CURSOR START ADR. =9 CURSOR END ADR. = 9 7 -+-+++++-1- 7 -+++++-1-1- ~o=mg 11m ~omm 11m = CURSOR START ADR. 9 CURSOR END ADA. = 10 = CURSOR START ADR. 1 CURSOR END ADR. = 5 Start Address and Light Pen Registers Cursor Control Registers-Cursor movement is controlled by the following four registers. The following 14-bit registers control the start address and light pen. Cursor Start Register (R10) and Cursor End Register (R11) -These registers allow a cursor of up to 32 scan lines in height to be placed on any scan line of the character block, as shown in figure 11. Register R10 is a l-bit writeonly register used to define the start scan line and the cursor blink rate. Bits 5 and 6 of the cursor start address register control the cursor operation, as shown in table 5. Non-display, display, and two blink modes (16 times or 32 times the field period) are available. Register R11 is a 5-bit write-only register that defines the last scan line of the cursor. Start Address Register (R12-H, R13-L) - This 14-bit writeonly register pair controls the first address by the CRTC after vertical blanking. It consists of an S-bit low order (MAO - MAl) register and a 6-bit high order (MAS - MA13) register. The start address register determines which portion of the refresh RAM is displayed on the CRT screen~ Because the CRTC linear address generator counts from this beginning count, the displayed portion of the screen may be a window on any continuous string of characters within a 16 block of refresh memory. Hardware scrolling by characters, line, or page can be accomplished by centering the R12/R13 pointer in the middle of the available memory space. Bit 5 is the blink timing control; when it is low, the blink frequency is 1/16 of the vertical field rate, and when it is high, the blink frequency is 1/32 of the vertical field rate. Bit 6 is used to enable a blink. The cursor start scan line is set by the lower five bits. Light Pen Register (R16-H, R17-L)- This 14-bit read-only register pair captures the refresh address output by the CRTC on the positive edge of a pulse input to the LPSTB pin. It consists of an S-bit low order (MAo-MA7> register and a 6-bit high order (MAo-MA1J> register. Since the light pen pulse is aynchronous with respect to refresh address timing, an internal synchronizer is deSigned into the CRTC. Due to delays in this circuit, the value of R16 and R1l need to be corrected in software. (See the bus timing diagram in the Timing Characteristics section). Figure 12 shows an interrupt-driven approach, although a polling routine could be used. When an external blink feature on characters is required, it may be necessary to perform cursor blink externally so that both blink rates are synchronized. Note that an invert/non invert cursor is easily implemented by programming the CRTC for a blinking cursor and externally inverting the video signal with an exclusive-OR gate. Cursor Register (R14-H, R1S-L) - This 14-bit read/write register pair is programmed to position the cursor anywhere in the refresh RAM area, thus allowing hardware paging and scrolling through memory without loss of the original cursor position. It consists of an S-bit low order (MAO - MAl) register and a 6-bit high order (MAS - MA13) register. 5-168 F6845 Figure 12 Light Pen Interface MPU CRTC LIGHT PEN CRTC Initialization The bus timing test load is shown in figure 16; figure 17 II- • lustrates the CRTC timing, and figure 18 illustrates the CRTC clock, memory addressing, and light pen timing. All signal timing characteristics are given in the "Timing. Characteristics" section of this data sheet. Registers RO-R15 must be Initialized after the system power is turned on. The processor normally loads the CRTC register file sequentially from a firmware table, after which, in most systems, RO-R11 are not changed. The worksheet of table 6 is useful in computing proper register values for the CRTC. Table 6 shows the worksheet completed for an 80 x 24 configuration using a 7 x 9 character generator, and figure 13 shows an F6800 program that could be used to program the CRT controller. The programmed values allow use of either an F6845 or an F6845A CRTC. Additional CRTC Applications The foremost system function that can be performed by the CRTC is the refreshing of dynamic RAM. This is quite simple, as the refresh addresses run continually. Note that the LPSTB input signal can be used to support additional system function other than a light pen. A digitalto-analog converter (DAC) and comparator could be configured to use the refresh addresses as a reference to a DAC composed of a resistive adder network connected to a comparator. The output of the comparator generates the LPSTB input signal, signifying a match between the refresh address analog level and the unknown voltage. The CRTC registers have an initial value at power up. When using a direct drive monitor (without horizontal oscillator), these initial values can result in out-of-tolerance operation. The CTRC programming should be done immediately after power up, especially in this type of system. CRT Interface Signal Timing Timing charts of CRT interface signals are illustrated with the aid of a programmed example of the CRTC. When values listed in table 7 are programmed into the CRTC control registers, the device provides the outputs as shown in the timing diagrams (figure 8, 9,14, and 15). The screen format of this example is shown in figure 7, which illustrates the relation between refresh memory address (MAQ-MA13l, row address (RAQ-RA4), and the position on the screen. In this example, the start address is assumed to be zero. The light pen strobe input could also be used as a character strobe to allow the CRTC refresh addresses to decode a keyboard matrix. Debouncing would need to be done in software. Both the VS and HS signal outputs can be used as a realtime clock. Once programmed, the CRTC provides a stable reference frequency. 5-169 F6845 Table 6 Worksheet for 80 x 24 Format Display Format Worksheet I. Displayed Characters per Row 2. Displayed Character Rows per Screen 3. Character Matrix a. Columns b,Rows 4. Character Block a. Columns b.Rows 5, Frame Refresh Rate 6. Horizontal Oscillator Frequency 7. Active Scan Lines (Line 2 x Line 4b) 8, Total Scan Lines (Line 6 + Line 5) 9. Total Rows Per Screen (Line 8 + Line 4b) 10. Vertical Sync Delay (Character Rows) 11. Vertical Sync Width (Scan Lines, 16) . 12. Horizontal Sync Delay (Character Times) 13. Horizontal Sync Width (Character Times) 14. Horizontal Scan Delay (Character Times) 15. Total Character Times (Lines 1 + 12 + 13 + 1'4) 16. Character Rate (Line 6 times 15) 17, Dot Clock Rate (Line 4a times 16) 80 24 7 9 9 11 60 16,600 264 310 28 16 6 9 7 102 1.8972 M 17.075 M Char. Rows Columns Rows Columns Rows Hz Hz Lines Lines Rows and 2 Lines Rows Lines Character Times Character Times Character Times Character Times MHz MHz CRTC Registers Declmaf Hex 101 80 86 9 65 50 56 9 24 10 24 24 18 OA 18 18 R9 R10 R11 R12, R13 Horizontal Total (Line 15 minus 1) Horizontal Displayed (Line 1) Horizontal Sync Position (Line 1 + Line 12) Horizontal Sync Width (Line 13) Vertical Total (Line 9 minus 1) Vertical Adjust (Line 9 Lines) Vertical Displayed (Line 2) Vertical Sync Position (Line 2 + Line 10) Interlace (00 Normal, 01 Interlace 03 Interlace, and Vldlo) Max, Scan Line Add (Line 4b minus 1) Cursor Start Cursor End Start Address (Hand L) 11 B R14, R15 Cursor (H and L) 128 RO R1 R2 R3 R4 R5 R6 R7 R8 o O· o 11 128 B 00 80 00 80 5-170 F6845 Figura 13 F6800 Program for CRTC Initialization Page 001 CRTC INIT. SA:O F68451F6845·1 CTRC initialization program 00001 00002 NAM TTL OPT 00003 00004 00005 00006 00007 00008 00009 00010 00011 ooo12A 0000 00013A 0000 5F ooo14A 0001 CE 1020A ooo15A 0004 F7 9000 A ooo16A 0007 A6 00 A ooo17A 0009 B7 9001 A ooo18A OOOC 08 00019A 0000 5C ooo20A OOOE C1 10 A 00021A 0010 26 F20004 ooo22A 0012 3F 00023 00024 00025 00026A 1020 00027A 1020 65 A A 1021 50 A ooo28A 1022 .56 A A 1023 09 A 00029A 1024 18 A A 1025 OA A ooo30A 1026 18 A A 1027 18 A 00 A 00031A 1028 A 1029 OB A 00 A 00032A 102A A 102B OB A 00033A 102C 0080 A 00034A 102E 0080 A 00035 Total Errors 00000-00000 F6845 F6845·1 CRTC initialization program G,S,llE == 85 print FCB's, FOB's & XREF table ****************************************** CRTC addresses * Assign CRTCAO EQU CRTCRG EQU $9000 Address Register CRTCAO + 1 Oata Register ' ****************************************** * Initialization program CRTC1 ORG ClRB lOX STAB lOAA STAA INX INCB CMPB BNE SWI 0 #CRTTAB CRTCAO O,X CRTCRG $10 CRTC1 a place to start clear counter table pOinter load address register get register value from table program register increment counters finished? no: take branch yes: call monitor ****************************************** * CRTC register initialization table CRTTAB ORG FCB $1020 $65,$50 start of table RO, R1 . total & H displayed FCB $56,$09 R2, R3 . pos. & HS width FCB $18,$OA R4, R5 . V total & V total adj. FCB $18,$18 R6, R7 • V displayed & VS pos. FCB $OO,$OB R8, R9· Interlace & Max scan line FCB $OO,$OB R10,R11 . Cursor start & end FOB FOB $0080 R12,R13 • Start Address R14,R15 • Cursor Address $0080 ENO CRTCl 0004 CRTCAO 9000 CRTCRG 9001 CRTTAB 1020 5·171 5 F6845 Table 7 Values Programmed Into CRTC Registers Reg. II AO A1 R2 A3 A4 A5 A6 A7 A8 A9 Al0 All A12 A13 A14 A15 A16 A17 Register Name Value Programmed Value Horizontal Total Horizontal Displayed Horizontal Sync Position Horizontal Sync Width Vertical Total Vertical Scan Line Adjust Vertical Displayed Vertical Sync Position Interlace Mode Max. Scan Line Address Cursor Start Cursor End Start Address (H) Start Address (L) Cursor (H) Cursor (L) Light Pen (H) Light Pen (L) Nht+1 Nht Nhd N hd N hsp N hsp N hsw N hsw N vt + 1 N vt N ad] Nadj Nvd Nvd Nvsp NySp Nsl 1 Nsl 3 0 0 0 2 Figure 14 Cursor Timing Diagram RAO·RM· X I I - - - - - - - -.......X1 I 1 1 MAQ-MA1·· 1'-----------''----------+ I I I ~~~~~~~~~~--~--~--~--~~~~--~--~--~---J,~~~I-N~-+~I CHARACTER ROW' 1 1 ~i~......._-!-_--!-'~ I N.t CURSOR --_..... )i ~ 1 1 I~I-~-~-+--+--+--r--~~-~-_+--+-_+-~-~I~~II 1 CHARACTER' 1 NhI 1 ~ 1 ________ 'TI Ing is shown for non·interlace and interlace sync modes. ample shown has cursor programmed as Cursor Register = Nhd + 2 Cursor Start 1 3 Cursor End "The initial MA Is determinad by the contents of start address register, RI21RI3. Timing is shown for RI2113 = 0 = 5·172 1 1 i ~,........_-,-_-,-_-!-i_--!-i:±J 1121 1 1 1 1 ~r-l = 1 N.t 121 1 1 1 1 r-l~ NhI ____ F6845 Figure 15 Refresh Memory Addressing (MAo - MA1a) Timing Diagram a: ...w h":1:0 w z (J ~I (Ja: HORIZONTAL RETRACE (Non-display) HORIZONTAL DISPLAY CHARACTER ~ Nol 0 1{ > ~ '"is Nol 0 Nhd Nhd+ 1 Nhct Nrni+1 2X1hd 2XNhd + 1 2{ 1 Nvd ..~ (Nvd-1) (Nvd -1) x Nhd (Nyd -1{ Nol !!l (NVd-YX Nhd Nvd{ Q Nhd+ 1 Ie 1) xNhd+ 1 1 N"d+ Nhd 1 Nyd xNhd 0 Nvd)( Nhd Nvd)( Nhd+ 1 (Nvd+1) ~ Nhd- 1 Nvd +~) Nol Nvd; Nhd Nype Nhd + 1 (Nvd+1)i< Nhd- 1 (Nyl Nvt:le Nhd Nvt xNhd+ 1 • • • 1 (Nvd - 1) )( Nhd + Nht (Nvd -1»)11 'Nhd + Nhl Nvd x Nhd + Nht Ie Nhd + 1') x Nhd Nvd x Nhd + Nht x Nhd Nyt x Nhd + Nht Z 0 ~ w (J " Iii a: a: N.t{ Nyt; Nhd 1{ 0 Nadj -1 (Nvt + 1) Ie Nhd-1 (Nyt +? (Nyt + 1) ~ Nhd-1 (Nvt + 1) x Nhd Nvt x Nhd+Nht (Nvt+YXNhd (Nvt+ 1) r Nhd+ 1 (Nvi +2»)( Nhd -1 (N vt+2) x Nhd (N" 1)Nr + Nht (Nv• + 1) x Nhd (Nvt+ 1) ~ Nhd+ 1 (Nvt+2) x Nhd-1 (NYI + i) x Nhd (Nv1)N~d + Nht Note 1: The initial MA is determined by the contents of start register, Rl21R13. Timing is shown for R12/R13=O. Only non·interlace and interlace sync modes are shown. Figure 16 CRTC Bus Timing Test Load 5.0V TesT POINTC>--....--1~~1O- C R lN914 OR EQUIVALENT C= R= 5·173 130 pF for 00·07 30 pF for MAO·MA13, RAO-RA4, DE, HS, VS, and CURSOR 11 kQ for 00·07 24 for All Other Outputs • F6845 Figure 17 CRTC Timing Dlagrem ClK RAO·RA4 DE HS VS CURSOR Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise noted. Figure 18 CRTC Clock, Memory Addressing, and Light Pen Timing Diagram ClK MAg.MA13 lP~B M ______________________ M ~"r-- +2 l - When the CRTC detects the rlslng edge of LDSTB in this perlod, the CRTC sets the refresh memory address 'M + 2' Into the LIGHT PEN REGISTER. tlPD1,tlPD2: Period of uncertelnty for the refresh memory address. Note: Timing measurements are referenced to and ,from a low voltage of 0.8 volts, and a high voltage of 2.0 volts, unless otherwise noted. 5-174 F6845 Timing Characteristics The signal timing for the CRTC bus is shown in figure 19; ac characteristics for the bus timing are given in table 8, and for the CRTC timing in table 9. Figure 19 CRTC Bus Timing Diagram E RS ~~~O======:mxK Rud~ ::~::~~-------------2~!=~~---=~---1~::::::::::tt::~ -=~::~=- Write Data _ ____________ ~M~P~U~W~ri~t.~~~U!-____________~::====::t:~ Not••: 1. 2. Voltage levels shown are VL 2) Input Address Inputs Chip Select Inputs ReadIWrite Input Counter Gate Input External Clock Input Reset Input Peripheral Interrupt Input Bidirectional Peripheral Control Bidirectional Data Lines Bidirectional Peripheral Data Lines Counter Timer Output Interrupt Request Output As A8 CSO RiW Do D, Do D. D4 D. Oe D7 CS, CTG CTC CTO E (Top View) 5·179 F6846 Typical Microcomputer Vee Vee IRQ F6846 ROM-IIO TIMER MR CSo ..,;.-V:.;M"'A"-_ _ _- ; CLOCK 2K BYTES ROM 10110 LINES 3 TIMER LINES PARALLEL 110 Vee Vee RlVi I VMA E RIW F6802 MPU 00-07 XTAL -.-.. CONTROL { ~ ~:~ 0 Ao-A15 AO-A15 XTAL L.:.;.;~"T"""--';';;.;.J -= Block Diagram RIW E RESET R/W AND TIMING CONTROL iiiQ Do 0, 0, Do 04 DATA BUS BUFFERS Ds D. D7 COMPOSITE STATUS REGISTER 'CSO ·CS1 Ao A, A, CHIP SELECT, MODE & ADDRESS INPUTS AND LOGIC cp, cp, p, p, Vss --+Vcc~ Po P4 2048 BYTE ROM Ps P. P7 • Mask Programmable 5-180 F6846 Functional Description The F6846 combination chip may be partitioned into three functional operating sections: programmed storage, timer-counter functions, and a parallel I/O port. Peripheral Control (CP2) may be programmed to act as an interrupt input (set CSR2) or as a Peripheral Control output. Pin Functions Programmed Storage The mask-programmable ROM section is similar to other ROM products of the F6800 family. The ROM is organized in a 2048 by 8-bit array to provide read-only storage for a minimum microcomputer system. Two mask-programmable chip selects are available for user definition. Address inputs Ao-A10 allow any of the 2048 bytes of ROM to be uniquely addressed. Bidirectional data lines (00-07) allow the transfer of data between the MPU and the F6846. Timer-Counter Functions Under software control, this 16-bit binary counter may be programmed to count events, measure frequencies and time intervals, or similar tasks. It may also be used for square wave generation, single pulses of control duration and gated delayed signals. Interrupts may be generated from a number of conditions selectable by software programming. The Timer/Counter Control Register allows control of the interrupt enable, output enable and selection of an internal or external clock source, a divide-by·eight prescaler, and operating mode. The Counter·Timer Clock (CTC) will accept an asynchronous pulse to decrement the internal register for the counter-timer. If the divideby·eight prescaler is used, the maximum clock rate can be four times the master clock frequency with an absolute maximum of 4 HMz. Counter Gate input (CTG) accepts an asynchronous TIL-compatible signal that may be used as a trigger or gating function to the counter-timer. The Counter Timer Output (CTO) is also available and is under software control, being dependent on the timer control register, the gate input, and the clock source. Parallel 110 Port The parallel bidirectional I/O port has functional characteristics similar to the B port on the F6821 PIA. This includes eight bidirectional data lines and two handshake control signals. The control and operation of these lines are completely software programmable. Internal registers associated with the I/O functions may be selected with Ao, A1 and A2. The Peripheral Interrupt input (CP1) will set the interrupt flag (CSR1) of the Composite Status Register. The Bus Interface The F6846 interfaces to the F6800 bus via an 8-bit bidirectional data bus, two chip select lines, a read/write line, and 11 address lines. These Signals, in conjunction with the F6800 VMA Output, permit the MPU to control the F6846. Bidirectional Data Bus (00-07) The bidirectional data lines (00-D7) allow the transfer of data between the MPU and the F6846. The data bus output drivers are 3-state devices that remain in the highimpedance (OFF) state except when the MPU performs an F6846 register or ROM read (Rm HIGH and I/O registers or ROM selected). Chip Select (CSo, CS1) The CSo and CS1 inputs are used to select the ROM or I/O timer of the F6846. They are mask programmed to be . active HIGH or active LOW as specified by the user. Address (Ao-A10) The Address inputs allow any of the 2048 bytes of ROM to be uniquely selected when the circuit is operating in the ROM mode. In the I/O-Timer mode, Address inputs Ao, A1 and A2 select the proper I/O register, while A3 through A10 (together with CSo and CS1) can be used as additional qualifiers in the I/O select circuitry. (See the section on I/O-Timer Select Circuitry for additional details.) Reset (RESEn The active LOW state of the RESET input is used to initialize all register bits in the I/O section of the device to their proper values. (See the section on Initialization for timer and peripheral register reset conditions.) Enable (E) This signal synchronizes data transfer between the MPU and the F6846. It also performs an equivalent synchronization function on the External Clock, RESET and Counter Gate inputs of the F6846 timer se.ction. ReadlWrite (RJW) This signal is generated by the MPU and is used to control the direction of data transfer on the bidirectional data lines. A LOW level on the Rm input enables the F6846 input buffers and data is transferred to the circuit during the >2 pulse when the part has been selected. A 5-181 F6846 Control Register, the Counter Gate input, and the clock source. The output is TTL compatible. HIGH level on the RIW input enables the output buffers and data is transferred to the MPU during 1>2 when the part is selected. External Clock (CTC) CTC will accept asynchronous TTL voltage level signals to be used as a clock to decrement the timer. The HIGH and LOW levels of the external clock must be stable for at least one system clock period plus the sum of the set· up and hold times for the inputs. The asynchronous clock rate can vary from dc to the limit imposed by system <1>2, set-u p and hold times. Interrupt Request (IRQ) The active LOW IRQ output acts to interrupt the MPU through logic included on the F6846. This output utilizes an open drain configuration and permits interrupt request outputs from other circuits to be connected in a wire·OR configuration. Peripheral Data (PO-P7) The Peripheral Data lines can be individually programmed as either inputs or outputs via the Peripheral Data Direction Register. When programmed as outputs, these lines will drive two standard TTL loads (3.2 mAl. They are also capable of sourcing up to 1.0 mA at 1.5 V (logic HIGH output). The External Clock input is clocked in by enable (system 1>2) pulses. Three enable periods are used to synchronize and process the external clock. The fourth enable pulse decrements the internal counter. This does not affect the input frequency; it merely creates a delay between a clock input transition and internal recognition of that transition by the F6846. All references to CTC inputs in this document relate to internal recognition of the input transition. Note that a clock transition that does not meet set·up and hold·time specifications may require an additional enable pulse for recognition. When programmed as inputs, the output drivers associated with these lines enter a 3-state (highimpedance) mode. Since there is no internal pull·up for these lines, they represent a maximum 10 p.A load to the circuitry driving them, regardless of logic state. When observing recurring events, a lack of synchronization will result in either system jitter or input jitter being observed on the output of the F6846 when using an asynchronous clock and gate input signal. System jitter is the result of input signals out of synchronization with the system >2 clock (Enable), permitting signals with marginal set-up and hold time to be recognized within either the bit·time nearest the input transition or subsequent bit·time. A logic LOW at the RESET input forces the Peripheral Data lines to the input configuration by clearing the Peripheral Data Direction Register. This allows the system designer to preclude the possibility of having a peripheral data output connected to an external driver output during power·up sequence. Peripheral Interrupt (CP1) Peripheral Interrupt input CP1 sets the interrupt flags of the Composite Status Register. The active transition for this signal is programmed by the Peripheral Control Register for the parallel port. CPl may also act as a strobe for the Peripheral Data Register when it is used as an input latch. Details for programming CP1 are in the section on the parallel peripheral port. Input jitter can be as great as the time between input signal negative·going transitions plus the system jitter if the first transition is recognized during one system cycle, and not recognized the next cycle or vice·versa. INPUT 02 Peripheral Control (CP2) Peripheral Control CP2 may be programmed to act as an interrupt input or Peripheral Control output. As an input, this line has high impedance and is compatible with standard TTL voltage levels. As an output, it is TTL· compatible and may be used as a source of 1 mA at 1.5 V to directly drive the base of a Darlington transistor switch. CP2 is programmed by the Peripheral Control Register. eTe INPUT ~~~~~ ---'1....-__ .....1 -------...,1--- ~ I EITHERJ ' - OR HERE HERE OUTPUT ,p2~ ~ Counter Timer (CTO) The Counter Timer output is software programmed by selected bits in the Counter/Timer Control Register. The mode of operation is dependent on the CounterlTimer eTe INPUT RECOG~ INPUT 5·182 I--~ BIT TIME SYSTEM JITIER ----1 __ _ J F6846 Counter Gate (CTG) CTG accepts an asynchronous TTL-compatible signal which is used as a trigger or a clock-gating function to the timer. The gating input is clocked into the F6846 by the Enable (system <1>2) signal in the same manner as the previously discussed clock inputs. A CTG transition is recognized on the fourth enable pulse, provided set-up and hold time requirements are met. The HIGH or LOW levels of the CTG input must be stable for at least one system clock period plus the sum of set-up and hold times. All references to CTG transition in this document relate to internal recognition of the input transition. Memory mapping the I/O can be accomplished by using one of the CS inputs to select between ROM and I/O, applying the F6802 VMA output to the other CS (programmed active HIGH) and using the Address lines to decode Address fields. o 1/0(0100) I/O (0200) F6820 F6850 CSo CSo F6802 VMA~--1-~--+-------~ The CTG input of the timer directly affects the internal 16-bit counter. The operation of CTG is therefore independent of the divide-by-eight prescaler selection. RAM 10000.(075) CSo Active HIGH I/O ROM CS1 L H F8820 I/OIOX80) ROM (8000) I/OF~~~) As Active HIGH As Active HIGH Functional Select Circuitry I/O-Timer Select Circuitry CSo and CSt are user programmable. Any of the four binary combinations of CSo and CSt can be used to select the ROM. Likewise, any other combination can be used to select the I/O-Timer. In addition, several Address lines are used as qualifiers for the I/O-Timer. Specifically, A3 = A4 = As = logic L. As can be programmed to anH, L, or don't care (X). A7 = As = As = A10 = don't care or one line only may be programmed to a logic H. The available chip select options are diagramed below. Internal Addrel!sing Seven I/O register locations within the F6846 are accessible to the MPU data bus. Selection of these registers is controlled by Ao, At, and A2 as shown in Tab/e 1, provided the I/O timer is selected. CSo and CSt must be in the I/O state and the proper register address must be applied to access a particular register. The CompOSite Status Register is read only, where all other registers are read/write. Table 1 CS1-r~~----~~o-__________~~ 1/0 SELECT CompOSite Status Register Peripheral Control Register Peripheral Data Direction Register Peripheral Data Register Composite Status Register CounterlTimer Control Register CounterlTimer MSB Register CounterlTimer LSB Register ROM Address CSo __.--t>c>-----G_ A7---O Internal Register Addresses. Register Selected r At. L ~ H X At. A4 Aa 5-183 LOW Voltage Level HIGH Voltage Level Don't Gare A2 A1 Ao L L L H H L L H H L H L H L H L H X X i..: L L H H H H X F6846 conditions causes it to halt or recycle. Thus the timer is programmable, cyclic in nature, controllable by external inputs or MPU program, and accessible to the MPU at any time. Initialization When the RESET input has accepted a LOW signal, all registers are initialized to the reset state. The Peripheral Data Direction and Peripheral Data Registers are cleared. The Peripheral Control Register is cleared except for bit 7 (the reset bit). This forces the parallel port to the input mode with interrupts disabled. To remove the reset condition from the parallel port, an L must be written into the Peripheral Control Register bit 7 (PCR?). Counter Latch Initialization The timer consists of a 16-bit addressable counter and two 8-bit addressable latches. The latches store a binary equivalent of the desired count value minus one. Counter initialization results in the transfer of the latch contents to the counter. It should be noted that data transfer to the counters is always accomplished via the latches. Thus, the counter latches may be accurately described as a 16-bit counter initialization data storage register. During initialization the counter latches are preset to their maximal count, the Counter/Timer Control Register bits are reset to L except for bit 0 (TCRo is set), the counter output is cleared, and the counter clock disabled. This state forces the timer counter to remain in an inactive state. The Composite Status Register is cleared of all interrupt flags. During timer initialization the reset bit (TCRo) must be cleared. In some modes of operation, the initialization of the latches will cause simultaneous counter initialization (I.e., immediate transfer of the new latch data into the counters). It is, therefore, necessary to insure that all 16 bits of the latches are updated simultaneously. Since the F6846 data bus is eight bits wide, a temporary register (MSB buffer register) is provided for the most significant byte of the desired latch data. This is a write-only register selected via Address lines Ao, A1 and A2. Data is transferred directly from the data bus to the MSB buffer when the chip is selected, RiiN is LOW, and the timer MSB register is selected (Ao = L; A1 = A2 = H). ROM Select Circuitry The mask-programmable ROM section is similar in operation to other ROM products of the F6800 microprocessor family. The ROM is organized as 2048 words of 8-bits to provide read-only storage for a minimum microcomputer system. The ROM is active when selected by the unique combination of the chip select inputs. The lower eight bits of the counter latch can also be referred to as a write-only register. Data bus information will be transferred directly to the LSB of a counter latch when the chip is selected, Rm is LOW and the Counterl Timer LSB Register is selected (Ao = A1 == A2 = H). Data from the MSB buffer will be transferred automatically into the most significant byte of the counter latches simultaneously with the transfer of the data bus information to the least significant byte of the counter latch. For brevity, the conditions of this operation will be referred to henceforth as a write-timerlatches command. The active levels of CSo and CS1 for ROM and 1/0 select are a user programmable option. Either CSo and CS1 may be programmed active HIGH or active LOW, but different codes must be used for ROM or 1/0 select. CSo and CS1 are mask programmed simultaneously with the ROM pattern. The ROM select circuitry is shown below. The F6846 has been designed to allow transfer of two bytes of data into the counter latches from any source, provided that the MSB is transferred first. In many applications, the source of the data will be an F6800 MPU. It should therefore be noted that the 16-bit store operations of the F6800 family microprocessors (STS and STX) transfer data in the order required by the F6846. A store index register instruction, for example, results in the MSB of the X register being transferred to the selected address, then the LSB of the X register being written into the next higher location. Thus, either the index register or stack pOinter contents may be transferred directly into either 8-bit latch with a single instruction. Timer Operation The timer may be programmed to operate in modes which fit a wide variety of applications. The device is fully bus compatible with the F6800 system, and is accessed by load and store operations from the MPU. In a typical application, the timer will be loaded by storing two bytes of data into the counter latch. This data is then transferred into the counter during a counter initialization cycle. The counter decrements on each subsequent clock cycle (which may be system <1>2 or an external clock) until one of several predetermined 5-184 F6846 A logic L at the RESET input also initializes the counter latches. All latches will assume maximum count (65,536) values. It is important to note that an internal reset (bit zero of the CounterfTimer Control Register set) has no effect on the counter latches. TCR3, TCR4, and TCRs select the timer operating mode, and are discussed in the next section. CounterfTimer Control Register bit 6 (TCRs) is used to mask or enable the timer interrupt request. When TCRs L, the interrupt flag is masked from the timer. When TCRs = H, the interrupt flag is enabled into bit 7 of the Composite Status Register (composite IRQ bit), which appears on the IRQ output. = Counter Initialization Counter initialization is defined as the transfer of data from the latches to the counter with attendant clearing of the individual interrupt flag associated with the counter. Counter initialization always occurs when a reset condition (external RESET = L or TCRo = H) is recognized. It can also occur depending on the timer mode with a write-timer·latches command or recognition of a negative transition of the CTG input. CounterfTimer Control Register bit 7 (TCR7) has a special function when the timer is in the cascaded single-shot mode. (This function is explained in detail in the section describing the mode.) t"n all other modes, TCR7 merely acts as an output enable bit. If TCR7 = L, the Counter Timer Output (CTO) is forced LOW. Writing a logic L into TCR7 enables CTO. Counter recycling or reinitialization occurs when a clock input is recognized after the counter has reached an all L state. In this case, data is transferred from the latches to the counter, but the interrupt flag is unaffected. Table 2 CounterfTimer Control Register Format Control Register Bit State CounterfTimer Control Register The CounterfTimer Control Register (see Table 2) in the F6846 is used to modify timer operation to suit a variety of applications. The CounterfTimer Control Register has a unique address space (Ao = H, Al = L, A2 = H) and therefore may be written into at any time. The least significant bit of this control register is used as an internal reset bit. When this bit is a logic L, all timers are allowed to operate in the modes prescribed by the remaining bits of the control registers. Bit Definition TCRo L H Internal Reset Timer Enabled Timer in Preset State TCRl L Clock Source Timer uses External Clock (CTC) Timer uses >2 System Clock + 8 Prescaler Enabler Clock is not Prescaled Clock is Prescaled by +8 Counter H TCR2 Writing H into CounterfTimer Control Register bit 0 (TCRo) causes the counter to be preset with the contents of the counter latches, all counter clocks to be disabled, and the timer output and interrupt flag (status register) to be reset. The counter latch and CounteriTimer Control Register are undisturbed by an internal reset and may be written into regardless of the state of TCRo. L H TCR3 TCR4 TCRs X X X Operating Mode Selection See Table 3 TCRs L Timer Interrupt Enable IRQ Masked from Timer IRQ Enabled from Timer Timer Output Enable Counter Output (CTO) Set LOW Counter Output Enabled H CounterfTimer Control Register bit 1 (TCR1) is used to select the clock source. When TCRl L, the external clock input CTC is selected, and when TCRl = H, the timer uses system >2. = TCR7 L H CounterfTimer Control Register bit 2 (TCR2) enables the divide-by-eight prescaler (TCR2 H). In this mode, the clock frequency is divided by eight before being applied to the counter. When TCR2 L the clock is applied directly to the counter. = = 5-185 State Definition F6846 Table 3 CounterlTimer Control Register CSR, I I CSR. CSR, I I CSR4 CSR. I I I I CSR. Interrupt Enabl. L L = Output Disabled (LOW) H = Output Enabled I -----------------For Cascaded Single·shot L = Output Goes Low at Tlme·out H = Output Goes High at Tlme·out TCR. L L Continuous Time, Operating Mode CTGI+W+R T.O. L L H Ca.caded Single Shot CTGI+R T.O. L H L Continuous CTGI+R T.O. L H H No,mal Single Shot CTGI+R T.O. H L L CTG I CTG I Befora T.O. H L H H H L H H H Frequency ComparlsOl'! Pulse Width Comparison L TCRs L Single- . . shot H H I I CTG I Befora T.O. CTGlol+R T.O. Belora CTG I Table 5 Continuous Operating Modes (TCR3 L, TCR7 H, TCRs L) = = Control Register L Continuous H T.O. Befora CTG I CTG'·I'+R Timer Operating Mode L L I 0 (W + T.O.) + R TCR2 TCR4 H H 0 Interrupt Flag Set timer output is enabled (TCR7 = H), a square wave will be generated at the Counter Timer Output CTO (see Table 5). Control Register L Counter Initialization TCR. L Operating Modes . Clock Source L = Exte'nal Clock (CTC) H = Inte,nal Clock (¢2) TCR. The F6846 has been designed to operate effectively in a wide variety of applications. This is accomplished by using three bits of the CounterlTimer Control Register (TCR3, TCR4 and TCRs) to define different operating modes of the timer, outlined in Table 4. TCR4 I = Timer Enabled + 8 Preseale Enable L = Clock Not P'escaled H = Clock Prascaled (+ 8) I Timer Operating Modes TCR3 CSRo H =ResetSlate Timer Output Enable Table 4 I Iintemal Reset L = IRQ Masked H = IRQ Enabled I CSR, L Cascaded Single-shot G w Normal Single-shot R N Frequency Comparison T Pulse Width Comparison to T.O • • Defines Additional Timer Functions L H = Initialization/Output Waveforms Counter Initialization <3+ W + R G + R Timer Output (2X) In + 110)(11 + 1)0)(11 + 11(!') I.. ·1· -I- ·1 ~-VOH I \0 I T.O. Negative transition of CTG input Write-tlmer-Iatches command Timer Reset (TCRo = H or External l6-bit number In Counter Latch Period of Clock input to Counter. . Counter Initialization cycle Counter Time-out (all L condition) I I T.O. FiESEi' -VOL T,O. = L) Nota All time intervals shown above assume that the and eTc signals are synchronized to system <1>2 with the specified set-up and hold time requirements. em Continuous Operating Mode (TCR3 = L, TCRs = L) The timer may be programmed to operate in a continuous counting mode by writing L into bits 3 and 5 of the CounterlTimer Control Register. Assuming that the 5-186 F6846 = = The second difference is the method used to change the output level. CounterlTimer Control Register bit 7 (TCR7) has aspecial function in this mode. The Counter Timer Output (CTO) is equal to TCR7 clocked by time-out. At every time-out the content of TCR7 is clocked to and held at the CTO. Thus, output pulses of length greater than one timer cycle can be generated by cascading timer cycles and counting time-outs with a software program. Either a Timer Reset (TCRo H or External Reset L) condition or internal recognition of a negative transition of the CTG input results in counter initialization. A write· timer-latches command can be selected as a counter initialization signal by clearing TCR4. The discussion of the continuous mode has assumed that the application requires an output signal. It should be noted that the timer operates in the same manner with the output disabled (TCR7 = L). A read-timer· counter command is valid regardless of the state of TCR7. An interrupt is generated at each time-out. To cascade timer cycles, the MPU would need an interrupt routine to: 1) count each time-out and determine when to change TCR7; 2) write into TCR71he state corresponding to the next desired state of the output waveform (only necessary during the last timer cycle before the output is to change state); and 3) clear the interrupt flag by reading the Composite Status Register followed by the read timer MSB. II is also possible, if deSired, to change the length of the timer cycle by reinitializing the timer latches. This allows more flexibility for obtaining desired times. Single-shot Timer Mode (TCRs L, TCR4 H, TCRs H) This mode is identical to the continuous mode with two exceptions. The first of these is obvious from the name-the output returns to a LOW level after the initial time·out and remains LOW until another counter initialization cycle occurs. The internal counting mechanism remains cyclical in the single·shot mode. Each time-out of the counter results in the setting of an individual interrupt flag and reinitialization of the counter. = = = Cascaded Single-shot Mode Output Waveform i t ., I, H = Write an "H" into TCR? L = Write an "L" Into TCR? 10 f--l -I- n==-==!!-_---+-_---i Nota All time intervals shown above assume the CTG and CTC signals are synchronized to system <1>2 with the specified set-up and ,hold time requirements. +ol_o--(n + 1)---+I-(n + 1)--.1 ( n + l ) ' - - -__ H = Write an "H" into TCR? L = Write an "L" into TCR? Time Interval Modes (TCRs Nota All time intervals shown above assume the CTG and CTC signals are synchronized to system q,2 with the specified set·up and hold time requirements. = = H) The time interval modes are provided for applications requiring more flexibility of interrupt generation and counter initialization. The interrupt flag is set in these modes as a function of both counter time-out and CTG input transition. Counter initialization is also affected by interrupt flag status. The output signal is not defined in any of these modes. Other features of the time interval modes are outlined in Table 6. Cascaded Single-shot Mode (TCRs L, TCR4 L, TCRs L) This mode is identical to the single·shot mode with two exceptions. First, the output waveform does not return to LOW level and remain LOW after time·out. Instead, the output level remains at its initialized level until it is reprogrammed and changed by time·out. The output level may be changed at any time·out or may have any number of time-outs between changes. = 1101 tl Normal Single-Shot Mode Output Waveform I_ J I--(n + 1)--.j--(n + 1)-+--(n + 1 ) - + - ( n + 1)--1 The second major difference between the single·shot and continuous modes is that the internal counter enable is not dependent on the CTG input level remaining in the LOW state for the single·shot mode. = 5-187 5 F6846 Table 6 Timer Interval Modes (TCR3 TCR4 TCRs Application = H) condition will be generated if TCR5 = L and the period of the pulse (single pulse or measured separately repetitive pulses) at the CTG input is less than the counter time-out period. If TCR5 = H, an interrupt is generated if the pulse period is greater than the time-out period. Condition for Setting. Individual Interrupt Flag L L Frequency Interrupt generated if CTG Comparison input period (1/F) is less than counter time-out (T.O.) L H Frequency Interrupt generated if CTG Comparison input period (1/F) is greater than counter time-out (T.O.) H L Pulse Width Interrupt generated if CTG Comparison input down time is less than counter time-out (T.O.) H H Pulse Width Interrupt generated if CTG Comparison input down time is greater than counter time-out (T.O.) = Assume now with TCR5 = H that a counter initialization has occurred and that the CTG input has returned LOW prior to counter time-out. Since there is no individual interrupt flag generated, this automatically starts a new counter initialization cycle. The process will continue with frequency comparison being performed on each CTG input cycle until the mode is changed, or a cycle is determined to be above the predetermined limit. = Pulse Width Comparison Mode (TCR3 H, TCR4 = H) This mode is similar to the frequency comparison mode except for the limiting factor being a positive, rather than a negative, transition of the CTG input. With TCR5 = L, an individual interrupt flag will be generated if the L level pulse applied to the CTG input is less than the time period required for counter time-out. With TCRs = H, the interrupt is generated when the reverse condition is true. = Frequency Comparison Mode (TCR3 H, TCR4 L) The timer within the F6846 may be programmed to compare the period of a pulse (giving the frequency after calculations) at the CTG input with the time period required for counter time-out. A negative transition of the CTG input enables the counter and starts a counter initialization cycle-provided that other conditions as noted in Table 7 are satisfied. The counter decrements on each clock signal recognized during or after counter initialization until an interrupt is generated, a write-timerlatches command is issued, or a timer reset condition occurs. It can be seen from Table 7 that an interrupt Table 7 TCR3 As can be seen in Table 8, a positive transition of the CTG input disables the counter. With TCR5 L, it is therefore possible to directly obtain the width of any pulse causing an interrupt. = Frequency Comparison Mode = H, TCR4 = L Control Reg Bit 5 (TCRs) Counter Initialization Counter Enable Flip·Flop Set (CE) Counter Enable Flip-Flop Reset (CE) L G I • I • (CE + TO • CE) + R Glw.R.T W + R +1 G I before TO Glw.R.T W + R + I TO before G I Interrupt Flag Set (I) GI.T+R H i represents the interrupt for a given timer. Table 8 Interrupt Flag Set (I) Pulse Width Comparison Mode TCR3 - H, TCR4 =H Control Reg Bit 5 (TCRs) Counter Initialization Counter Enable Flip-Flop Set (CE) Counter Enable Flip-Flop Reset (CE) L GI.T+R GI.W·R·I W+R+I+G G I before TO H GI.T+R GlfW.R.T W+R+I+G TO before G f 5·188 F6846 Differences Between the F6840 and the F6846 Timers 1. Control Registers 1 and 3 are buried (access through Control Register 2 only) in the F6840 timer. In the F6846 all registers are directly accessible. 1. Timer Reset-Internal Reset bit (TCRo External Reset L = = H) or 2. Any Counter Initialization condition 3. A write-timer-latches command if time interval modes (TCR3 H) are being used. 2. The F6840 has a dual 8-bit continuous mode for generating non-symmetrical waveforms. The F6846 has a cascaded one-shot mode which can accomplish the same function, but also allows the user to generate waveforms longer than one time-out. = 4. A read-timer-counter command, provided this is preceded by a read CompoSite Status Register while CSRo Is set. This latter condition prevents missing an interrupt request generated after reading the status register and prior to reading the counter. 3. Because of the different modes, there is a difference in the control registers between the F6840 and the F6846. (See Table 9). The remaining bits of the Composite Status Register (CSR3-CSRs) are unused. They default to a logic L when read. Composite Status Register The Composite Status Register (CSR) is a read-only register which is shared by ttle timer and the peripheral data port of the F6846. Three individual interrupt flags in the register are set direclly via the appropriate conditions in the timer or peripheral port. The composite interrupt flag, and the IRQ output, respond to these individual interrupts only if corresponding enable bits are set in the appropriate control registers. The sequence of assertion is not detected. Setting TCRs while CSRo is HIGH will cause CSR7 to be set, for example. Composite Status Register and Associated Logic "}-....- [ ) _. . IRQ The composite interrupt flag (CSR7) is clear only if all enabled individual interrupt flags are clear. The conditions for clearing CSR1 and CSR2 are detailed in a later secti.on. The timer interrupt flag (CSRo) is cleared under the following conditions: Table 9 F6840 and F6846 Control Register Comparison Control Register Bit Table 10 F6840 F6846 2 7 16-bit or dual 8-bit mode control Output enable (all modes) + 8 prescale enable Output next state (cascaded one-shot mode only), output enable all other modes o R1 internal reset R2 control register select R3 timer 3 clock control Internal reset Composite Status Register Format CSR7 I CSR.-CSR. Not U.ed Delaull 10 L When Read 1 Comp08110 InlolTUpt Flag L = No Enablod Inlerrupl Flag Sol H • One Dr More Enabled Interrupt Flags Set· I I CSR2 I I CPo InlelTUpl Flag L .: Nolnt Req H = Inl Reque.,ed CSR, I I I CSRo Tlma' Inl...upt Flag L = Nolnl Raq H = Int Requested I J Inve..a of This BII Appea .. allRQ OUlpul I ·Statul of This Bit can be Expre.sed 8S: CSR7 = CSR. - TCRe + CSR, • PCR. + CSR. + PCR. 5-189 Cp, InlalTUpl L = Nolnl Raq H = Int Requested I F6846 110 Operation Parallel Peripheral Port The peripheral port of the F6846 contains eight Peripheral Data lines (PO-P7), two peripheral control lines (CP, and CP2), a Peripheral Data Direction Register, a Peripheral Data Register, and a Peripheral Control Register. The port also directly affects two bits (CSR, and CSR2) of the CompOSite Status Register. The peripheral port is similar to the "B" side of a piA (F6821) with the following exceptions: 1. All registers are directly accessible in the F6846. Data direction and peripheral data in the F6821 are located at the same address, with bit 2 of the control register used for register selection. 2. Peripheral Control Register bit 2 (PCR2) of the F6846 is used to select an optional input latch function. This option Is not available with F6821 PIAs. 3. Interrupt flags are located in the F6846 Composite Status Register rather than bits 6 and 7 of the control register as used in the F6821. 4. Interrupt flags are cleared in the F6821 by reading data from the Peripheral Data Register. F6846 interrupt flags are cleared by either reading or writing to the Peripheral Data Register provided that this sequence is followed: a. flag set, b. read CompOSite Status Register, c. read/write Peripheral Data Register. 5. Bit 6 of the F6846 Peripheral Control Register is not used. Bit 7 (PCR7) is an internal reset bit not available on the F6821. 6. The Peripheral Data lines (and CP2) of the F6846 feature internal current limiting which allows them to directly drive the base of Darlington npn transistors. Peripheral Data Direction Register The MPU can write directly to this 8·bit register to configure the Peripheral Data lines as either inputs or outputs. A particular bit within the register (DDRn) is used to control the corresponding Peripheral Data line (Pn). With DDRn = L, Pn becomes an input; if DDRn = ,H, Pn is an output. For example, writing Hex $OF into the Peripheral Data Direction Register results in Po through P3 becoming outputs and P4 through P7 inputs. Hex $55 in the Peripheral Data Direction Register results in alternate output and inputs at the parallel port. Peripheral Data Register This 8·blt register is used for transferring data between the peripheral data port and the MPU. Any bit corresponding to an output line will be used to drive the output buffer associated with that line. Data in these , output bits are normally provided by an MPU write function. (Input bits, those associated with input lines, are unchanged by a write command.) Any input bit will reflect the state of the associated inpuf line if the input latch function is deselected. If the Peripheral Control Register is programmed to provide input latching, the input bit will retain the state at the time CP, was activated until the Peripheral Data Register is read by the MPU. Peripheral Control Register This 8·bit register is used to control the reset function as well as for selection of optional functions of the two peripheral control lines (CP, and CP2). The Peripheral Control Register functions are outlined in Tab/e 11. Peripheral Port Reset (PCR7) Bit 7 of the Peripheral Control Register (PCR7) may be used to initialize the peripheral section of the F6846. When this bit is set HIGH, the Peripheral Data Register, the Peripheral Data Direction Register, and the interrupt flags associated with the peripheral port (CSR, and CSR2) are all cleared. Other bits in the Peripheral Control Register are not affected by PCR7. PCR7 is set by either a logic L at the external RESET input or under program control by writing an H into the location. In any case, PCR7 may be cleared only by writing an L into the location while RESET is HIGH. The bit must be cleared to activate the port. ' Control of Peripheral Interrupt Line (CP,) CP, may be use,d as an interrupt request to the F6846, as a strobe to allow latching of input data, or both. In any case, the input can be programmed to be activated by either a positive or negative transition of the signal. These options are selected via Peripheral Control Register bits PCRo, PCR, and PCR2. Peripheral Control Register bit 0 (PCRo) is used to enable the interrupt transfer circuitry of the F6846. Regardless of the state of PCRo, an active transition of CP, causes the CompOSite Status Register bit 1 (CSR,) to be set. If PCRo H, this interrupt WII!, be reflected in the composite interrupt flag (CSR7), and thus at the IRQ output. CSR, is cleared bya peripheral port reset condition or by either reading or writing to the Peripheral Data Register after the CompOSite Status Register is = 5·190 F6846 Table 11 Peripheral Control Register Format (Expanded) PCR7 I I PCRt I PCR. I I PCR. PCR. I I I I PCRI PCR, I C... Direction Control L = C... I. Input H • C... I. Output l ~---------------L = Normal Operation I = H Rooet Condition (Cloo .. Perlph Data and Data Dlractlon Reg :t CSR, & CSRol = = I CP, Active Edge Select L Nogatl.e (I) Edge H Posltl.e (I) Edge , = = Cp, Input Latch Control L Input Data Not Latchad Input Data Latchad on Actl.. CP, H = = I I Ic... I. Input (PCR. ="0', I I PCR. I PCR; I I PCR. Cp, InL Enable L = CP1 Int. Ma.ked H =: CP1 Int. Enabled R.let (Sot by Ext. Relet = L or Writing H Into Location; Clearad by Writing L to This Location) CPo Actl.. Edge Solect L Nogatl.. (I) Edge H Posltl.. (I) Edge I I I == I C... Int. Enable L CPolnL Malked H CPo InL Enabled CPo I. Output (PCR. =H PCR< PCR. L L Interrupt Acknowledge L H InpuUOutput Acknowledge, H LorH Programmable Output (CPo Rellacta Data WrlHen Into PCRs) Control of Peripheral Control Line (CP2) CP2 may be used as an input by writing an L into PCR5. In this configuration, CP2 becomes a dual of CP1 in regard to generation of interrupts. An active transition (as selected by PCR4) causes bit 2 of the Composite Status Register to be set. PCR3 is then used to select whether the CP2 transition is to cause CSR7 to be set and, thereby, cause IRQ to go LOW. CP2 has no effect on the input latch function of the F6846. read. The latter alternative is conditional; CSR1 must have a logic H when the CompOSite Status Register was last read. This preculudes inadvertent clearing of interrupt flags generated between the time the CompOSite Status Register is read and the manipulation of peripheral data. Peripheral Control Register bit 1 (PCR1) is used to select the edge which activates CP1. When PCR1 H, CP1 is active on negative transitions (HIGH-to-LOW). LOW-toHIGH transitions are sensed by CP1 when PCR1 = H. = Writing an H into PCR5 causes CP2 to function as an output. PCR4 then determines whether CP2 is to be used in a handshake or programmable output mode. With PCR4 = H, CP2 will merely reflect the data written into PCR3. Since this can readily be changed under program control, this mode allows CP2 to be a programmable output line in much the same manner as those lines selected as outputs by the Peripheral Data Direction Register. In addition to its use as an interrupt input, CP1 can be used as a strobe to capture input data in an internal latch. This option is selected by writing a HIGH into Peripheral Control Register bit 2 (PCR2). In operation, the data at the pins designated by the Peripheral Data Direction Register as inputs will be captured by an active transition of CP1. An MPU read of the Peripheral Data Register will result in the captured data being transferred to the MPU; it also releases the latch to allow capture of new data. Note that successive active transitions with no read-peripheral-data command between does not update the input latch. Also, it should be noted that use of the input latch function (which can be deselected by writing an L into PCR2) has no effect on output data. It also does not affect interrupt function of CP1. The handshaking mode (PCR5 = H, PCR4 = L) allows CP2 to perform one of two functions as selected by PCR3. With PCR3 H, CP2 will go LOW on the first Enable (system >2) positive transition after a read or write to the Peripheral Data Register. This input/output acknowledge signal is released (returns HIGH) on the next positive transition of the enable signal. = ,5-191 F6846 = In the interrupt acknowledge mode (PCR5 H, PCR3 L), CP2 is set when CSR2 is set by an PCR4 active transition of CPl. It is released (goes LOW) on the first positive transition of Enable after CSRl has been cleared via an MPU read or write to the Peripheral Data Register. (Note that the previously described conditions for clearing CSRl still apply.) = = Restart Sequence A typical restart sequence for the F6846 will include initialization of both the Peripheral Control and Peripheral Data Direction Registers of the parallel port. It is necessary to set up the Peripheral Control Register first, since PCR7 L is a condition for writing data into the Peripheral Data Direction Register. (A logic L at the external RESET input automatically sets PCR7). = Absolute Maximum Ratings Supply Voltage, Vee Input Voltage, VIN Operating Temperature, TA Storage Temperature, Tstg Thermal Resistance, B 10 31 iiifi'/EXT 4>A 11 30 GMo i.lS 12 29 GM, DAs 13 28 Y 14 27 GM, DA, DA, 15 DA" 16 25 DA, Vee 17 24 DA, DA" 18 DA10 19 22 DAo DAft 20 21 DA12 DA, (Top VI_I 5·199 40 DO. II F6847 Fig. 1. Block Diagram of Use of the VDG in a TV Game !.IS CLK >B 3.58 MHz c::J Pin Functions Vee +5 V Vss Ground ClK Color burst clock 3.58 MHz (input) DAo - DA12 Address lines to display memory, high impedance during memory select (MS) 000 - 005 Data from display memory RAM or ROM 006, 007 Data from display memory in graphic mode; data also in alpha external mode; color data in alpha semigraphic-4 or -6 mode Chrominance and luminance analog (R-Y, B-Y, t/>A,t/>B,Y Y) output to rf modulator CHB Chroma Bias; reference q,A and q,B levels RP Row Preset; output to provide timing for external character generator Horizontal Sync; output to provide timing for external character generator >A Y RF Modulator INV INT/EXT "A/S MS "A/G FS CSS 5-200 RF to TV Inverts video in all alpha modes Switches to external ROM in alpha mode and between alpha semigraphic-4 and alpha semigraphic-6 in semigraphics mode Alpha/Semigraphics; selects between alpha and semigraphics in alpha mode Memory Select; forces VDG address buffers to high-impedance state Switches between alpha and graphic modes Field Synchronization; goes low at bottom of active display area Color Set Select; selects between two alpha display colors or between two color sets in semigraphics-6 and full graphics mode Graphic Mode Select; selects one of eight graphic modes F6847 VDG Signal Descriptions Address Outputs (DAO - DA12) Thirteen address lines are used by the VDG to scan the display memory. The starting address of the display memory is located at the upper left corner of the display screen. As the television sweeps from left to right and top to bottom, the VDG increments the RAM display address. These lines are TTL-compatible and may be forced into a high-impedance state whenever the MS pin goes lOW. Synchronizing Outputs (FS, HS, RP) Three TTL-compatible outputs provide circuits exterior to the VDG with timing references to the following internal VDG states: Field Sync (FS) - The HIGH-to-lOW transition of the FS output coincides with the end of active display area. During this time interval, an MPU may have total access to the display RAM without causing undesired flicker on the screen. The lOW-to-HIGH transition of FS coincides with the trailing edge of the vertical synchronization pulse. Data Inputs (000 - 007) Eight TTL-compatible data lines are used to input data from the RAM to be processed by the VDG. The data is interpreted and transformed into luminance Y (pin 28) and color outputs A and B (pin 11 and pin 10). Horizontal Sync (HS) - The HIGH-to-lOW transition of the HS output coincides with the leading edge of the horizontal snyc pulse portion of the VDG luminance (Y) output. Power Inputs Vee requires +5 volts. VSS requires zero volts and is normally ground. (The tolerance and current requirements of the VDG are specified in the DC Characteristics table.) Video Outputs (A, ",B, Y, CHB) These four analog outputs are used to transfer luminance and color information to a standard NTSC color television receiver, either via the rf modulator or directly into Y, A, and B television video inputs. luminance (Y) - This six-level analog output contains composite sync, blanking, and four levels of video luminance. A - This three-level analog output is used in combination with the B and Y outputs to specify one of eight colors. B - This four-level analog output is used in combination with the A and Y outputs to specify one of eight colors. Additionally, one analog level is used to specify the time of the color burst reference signal. Chroma Bias (CHB) - This pin is an analog output and provides a dc reference corresponding to the quiescent value of A and B. CHB is used to guarantee good thermal tracking and minimize the variation between the parts. Synchronizing Inputs (MS, ClK) Three-State Control (MS) - This is a TTL-compatible input that, when lOW, forces the VDG address lines into a high-impedance state. This may be done to allow other devices (such as an MPU) to address the display memory RAM. Row Preset (RP) - If desired, an external character generator ROM may be used with the VDG. In this configuration, an external 4-bit counter, used to supply row selection, is clocked by HS and cleared by the RP Signal. Mode Control Inputs (A/G, A/S, INT/EXT, GM o, GM1 , GM2, CSS,INV) Eight TTL-compatible inputs are used to control the operating mode of the VDG. AlS, INT/EXT, CSS and INV may be changed on a character-by-character basis. The CSS pin is used to select between two possible alphanumeric colors when the VDG is in the alphanumeric mode and between two color sets when the VDG is in the semigraphics-6 and full graphic mode. Table 1 illustrates the various modes that can be obtained using the mode contol lines. Display Modes The VDG is capable of generating 12 distinct display modes. The color set selection (CSS) and invert (lNV) pins allow variations on certain modes. The VDG displays two alphanumeric modes with two compatible semigraphic modes or one of eight full graphic modes. A detailed description of the various modes of operation follows. A summary of major modes can be found in Table 2, and a detailed description of VDG modes can be found in Table 3. Alphanumeric Display Modes All alphanumeric modes occupy an 8 x 12 dot character matrix box; there are 32 x 16 character boxes per TV frame. Each horizontal dot (dot-clock) corresponds to one-half the period duration of the 3.58 MHz clock, and each vertical dot is one scan line. One of two colors for the lighted dots may be selected by the color set select pin. Internal Alphanumeric Mode - In the internal alphanumeric mode, an internal ROM will generate 64 ASCII display characters in a standard 5 x 7 box. Six bits of the 8-bit data word are used for the ASCII character generator; the two bits not used can be used to implement inverse video or color switching on a character-by-character basis. A 512-word display memory is required for this class of display. Clock (ClK) - The VDG clock input (ClK) requires a 3.579545 MHz (standard) TV crystal frequency square wave. The duty cycle of this clock must be between 45 and 55 percent since it controls the width of alternate dots on the television screen. 5-201 II F6847 External Alphanumeric Mode - In the external alphanumeric mode, an external character generator may be used to generate custom character sets of up to.256 separate 8 x 1.2 dot characters, each defined by an 8-bit data word. If fewer than eight bits are used for character definition, the remaining bits may be used for inverse video selection or color switching on a character-by-character basis. This display mode also requires a 512-word display memory. Alpha Semlgraphic-4 Mode - The alpha semigraphic-4 mode translates bits O. through 3 into a 4 x 6 dot element in the standard 8 x 12 dot box. Three data bits may be used to select one of eight colors for the entire character box. The extra bit is available to implement mode switching on-the-fly. A 512-word display memory is required. A density of 64 x 32 elements is available in the display area. The element area is four dot-clocks wide by six lines high. Alpha Semigraphic-6 Mode - The alpha semigraphic-6 mode maps six 4 x 4 dot elements into the standard 8 x 12 dot alphanumeric box, providing a screen density of 64 x 48 elements. Six bits are used to generate this map and two data bits may be used to select one of four colors in the display box. The element area is four dot-clocks wide by four lines high. . Full Graphic Mode There are eight full graphic.modes availa1>ie from the VOG. These modes require 1K to 6K bytes of memory. The eight full graphic modes include an outside color border in one of two colors, depending upon the color set select (CSS) pin. Th.e CSS pin selects one of two sets oi four colors in the four color graphic modes. The 64 x 64 Color Graphics Mode (Graphics One C) The 64 x 64 color graphics mode generates a display matrix 64 elements wide by 64 elements high. Each element may be one of four colors. A 1K x 8 display memory is required .. Each pictel equals four dot-clocks by three scan lines. The 128 x 64 Graphics Mode (Graphics One R) - The 128 x 64 graphics mode generates a matrix 128 elements. wide by 64 elements high. Each element may be either On or off. However, the entire display maybe one of two colors, selected by using the color set select pin. A 1K x 8 display memory is required. Each pictel equals two dot-clocks by three scan lines. . The 128 x 64 Color Graphics Mode (Graphics Two C) The 128 x 64 color graphics mode generates a display matrix 128 elements wide by 64 elements high. Each element may be one of four colors. A 2K x 8 display memory is required. Each pictel equals two dot-clocks by three scan lines. The 128 x 96 Graphics Mode (Graphics Two R) - The 128 x 96 graphics mode generates a display matrix 128 elements wide by 96 elements high. Each element.may be ·either On or Off. However, the entire display may be one of two colors, selected by using the color set select pin. A 2K x 8 display memory is required. Each pictel equals two dot-clocks by two scan lines. The 128 x 96 Color Graphics Mode (Graphics Three C) The 128 x 96 color graphics mode generates a display 128 elements wide by 96 elements high. Each element may be one of four colors. A 3K x 8 display memory is required. Each pictel equals two dot-clocks by two scan lines. The 128 x 192 Graphics Mode (Graphics Three R) - The 128 x 192 graphics mode generates a display matrix 128 elements wide by 192 elements high. Each element may be either On or Off, but the On elements may be one of tWo colors, selected with the. color set select pin. A 3K x 8 display memory is required. Each pictel equals two dot-clocks by one scan line. 128 x 192 C.olor Graphics Mode (Graphics Six C) - The 128 x 192 color graphics mode generates Ii display 128 elements wide by 192 element high. Each element may be one of four colors. A 6K x 8 display memory is required. Each pictel equals two dot-clocks by one scan lin~. The 256 x 192 Graphics Mode (Graphics Six R) - The 256 x 192 graphics mode generates a display 256 elements wide by 192 elements high. Each element may be either On or Off, but the On elements may be one of two colors; selected with the color set select pin. A 6K x 8 display memory is required. Each pictel equals one dot-clock by one scan line. F6847 Table 1 Mode Control Inputs AlG AlS 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 2 INT/EXT 0 0 0 0 1 1 X X X X X X X 0 0 1 1 0 1 X X X X X X X X X Alpha/Graphic Mode Selected INV GM2 GM1 GMo 0 1 0 1 X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X 0 0 1 1 0 0 1 1 X X X Internal Alphanumeric Internal Alphanumeric Inverted External Alphanumeric External Alphanumeric Inverted Alpha Semigraphic-4 Alpha Semigraphic-6 64 x 64 Color Graphic 128 x 64 Graphic 128 x 64 Color Graphic 128 x 96 Graphic 128 x 96 Color Graphic 128 x 192 Graphic 128 x 192 Color Graphic 256 x 192 Graphic X X 0 1 0 1 0 1 0 1 Summary of Major Modes Memory Colors Alphanumeric (Internal) 512 x 8 2 Alphanumeric -(External) 512 x 8 2 Alpha Semigraphic-4 512 x 8 8 Box--rn--Element Alpha Semigraphic-6 512 x 8 4 Box------m--Element 64 x 64 Color Graphic 1K x 8 4 128 x 64 Graphic' 1K x 8 2 128 x 64 Color Graphic 2K x 8 4 128 x 96 Graphic' 1.5K x 8 2 128 x 96 Color Graphic 3K x 8 4 128 x 192 Graphic' 3K x 8 2 128 x 192 Color Graphic 6K x 8 4 256 x 192 Graphic' 6K x 8 2 Title 'Graphic mode turns each element on or off. The color may be one of two. 5·203 Display Elements Matrix 64 x 64 Elements Matrix 128 Elements Wide by 64 Elements High Matrix 128 Elements Wide by 96 Elements High Matrix 128 Elements Wide by 192 Elements High Matrix 256 Elements Wide by 192 Elements High • F6847 Table 3 Detailed Description of VDG Modes VOG Pins MS AJG AJS INT/iXT GM2 Color GM, GMO CSS 'NY ! Character Color Background Border I 0 0 1 1 0 0 0 X X I Black I Green Green Black Black ------t----- r----- X 0 1 1 I Black I Orange Orange Black Black I 0 0 1 1 0 0 1 X X X 0 1 1 0 1 0 X X X X X 1 0 1 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 t 1 X X 0 0 0 X 1 1 1 X X 0 0 X 1 t 0 1 1 X X 0 1 X 0 1 0 1 1 X X 0 1 X 1 1 0 1 1 X X 1 0 0 I Ct Co Color X X 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 Black Green Yellow Blue Red Buff Cyan Magenta Orange Ct X 0 0 Co 1 1 X 0 0 0 1 1 1 1 X X X X X X 1 1 1 0 1 1 1 1 1 1 X 0 1 1 X 0 1 0 C, 0 0 Co 0 1 1 0 0 0 0 1 1 0 Black 1 1 1 1 1 Color Black Green Yellow Blue Red Black Buff Cyan Magenta Orange Color Green Yellow Blue Red Buff Cyan Magenta Orange Black Black Green 1----Buff Color 1 Btack Green Green Buff 1 Black Buff 1------------1-----0 Same Color as Graphics One C Same Color as Graphics One A X Same Color as Graphics One C X Same Color as Graphics One R Green f----Buff Green r----Buff Green ----Buff 0 1 1 1 1 1 1 Black Orange C2 X 0 0 0 0 L, 0 0 Black I 0 1 I Orange Black L, 0 0 Black I Green ---- __ L ____ 1 - - - - - L, 0 t 1 I Green Black Green ----- 1 Buff 0 Green 0 X Same Color as Graphics One C ----- 1 Buff 0 Green X 1 1 5-204 Same Color as Graphics One A ----Buff F6847 Table 3 Detailed Description of VDG Modes (Cont.) TV Screen VDG Data Bus Comments Detail Display Mode The internal alphanumeric mode uses an internal 32 Characters in Columns 8 Dots --I t- ---r[g)~ .....!-. ' , I I I I I I I I I ...... I I I I I I I I I 12 Dots 16 Characters in Rows 32 Characters in Columns _ , _5 .. ~ Extra ASCII Code character generator that contains the following five dol by seven dot characters: @ ABCDEF ~ !"#$%&'O·+,-.l0123456789:;<=>? The S·bit ASCII code leaves two bits free; these may be ~rnally connected to the mode pins (NG, AlS, INT/EXT, GM2, GMt, GMo. CSS or INV). GHIJKLMNOPQASTUVWXYZ [ 11 SP The external alphanumeric mode uses an exler- nal character generator as well as a row counter. One Row of Custom Characters Thus, custom character tonts are graphic symbol sets with up to 256 different 8 dot X 12 dot "characters" that may be displayed. I Ic21c, leo IL31 L21 Ld Lol The semigraphic-4 mode uses an internal "coarse graphics" generator in which a rectangle (8 dots by 12 dots) is divided into four equal parts. The luminance of each part is determined by a corresponding bit on the VDG data bus. The color of illuminated parts is determined by three bits. Ls L4 L3 L2 L, Lo 1~1~14141~1~1~ILoI The semigraphic-6 mode is similar to the semigraphic-4 mode with the foUowing differenees. The 8 dot by 12 dot rectangle is divided into six equal parts. Color is determined by the two remaining bits. IE31E21E,I Eoi 1~1~1~1~1~1~1~1~1 The graphics one C mode uses a maximum of 1024 bytes of display RAM in which one pair of bits specifies one picture element. 1~1~14141~1~1~ILoI 1~1~14141~1~1~ILoI The graphics one R mode uses a maximum of 1024 bytes of display RAM in which one bit specifies one picture element. 128 Display Elements in Columns 64 Display Elements in Rows IE31 E21 E,I Eol I~I~I~I~I~I~I~I~I The graphics two C mode uses a maximum of 2048 bytes of display RAM in which one pair of bit specifies one picture element. 128 Display Elements in Columns 96 Display Elements in Rows 1~1~14141~1~1~ILoI 1~1~14141~1~1~ILoI The graphics two R mode uses a maximum of 1536 bytes of display RAM in which one bit specifies gne picture element. 128 Display Elements in Columns 96 Display Elements in Rows IE31 E21 Ed Eol I~I~I~I~I~I~I~I~I The graphics three C mode uses a maximum of 3072 bytes of display RAM in which one pair of bytes specifies one picture element. 128 Display Elements in Columns 192 Display Elements in Rows 1~1~14141~1~1~ILoI 1~1~14141~1~1~ILoI The graphics three R mode uses a maximum of 3072 bytes of display RAM in which one bit specifies on picture element. 128 Display Elements in Columns 192 Display Elements in Rows IE31 E21 Ed Eol I~I~I~I~I~I~I~I~I The graphics six C mode uses a maximum 016144 bytes of display RAM in which one pair of bit specifies one picture element. 256 Display Elements in Columns 192 Display Elements in Rows 1~1~14141~1~1~1~1 1~1~14141~1~1~ILoI The graphics six R mode uses a maximum of 6144 bytes of display RAM in which one bit specifies one picture element. 16 Characters in Rows 64 Display Elements in Columns 32 Display Elements in Rows 64 Display Elements in Columns 48 Display Elements in Rows 64 Display Elements in Columns 64 Display Elements in Rows 128 Display Elements in Columns 64 Display Elements in Rows m One L, Lo Element 5·205 • F6847 Absolute Maximum Ratings Supply Voltage, Vee Input Voltage, any Pin, VIN Operating Temperature Range, TA Storage Temperature Range, TSTG Power Dissipation, Po DC Characteristics Symbol Vee = 5.0 V Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only. and functional operation of the device -0.3 V, + 7.0 V -0.3 V, + 7.0 V O°C, +70°C -65°C, +150°C 945 mW ±5%, VSS = 0.0 V, Characteristic TA under these or any other condHions above those indicated in the operational ~ns of this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. = O°C to Min + 70°C, unless otherwise noted Typ Max Unit VIH Input HIGH Voltage ClK Other Inputs Vss + 2.4 Vss + 2.0 Vee Vee Vdc VIL Input lOW Voltage ClK Other Inputs Vss - 0.3 Vss - 0.3 Vss + 0.4 Vss + 0.8 Vdc lin Input leakage Current ClK, GMo-GM2. INV, INT/EXT. MS. Vss, DDo-DD7, AlS, AlG 2.5 p-Adc ILO Three-State (OFF State) Input Current DAo-DA12 10 p-Adc VOH Outp~HIGH Voltage RP. HS,FS Conditions 2.4 Vdc CLoad = 30 pF ILoad = -100 p-A 2.4 Vdc CLoad = 55 pF ILoad = -100 p-A VOH Output HIGH Voltage DAo-DA12 VOL Output lOW Voltage RP, HS, FS, VSS + 0.4 Vdc CLoad = 30 pF ILoad = 1.6 mA VOL Output lOW Voltage DAo-DA12 VSS + 0.4 Vdc CLoad = 55 pF ILoad = 1.6 mA IOH Output HIGH Current (Sourcing) All Outputs (Except >A, >6, Y, and CH6) IOL Output lOW Current (Sinking) All Outputs (Except >A, >B, Y, and CHB CIN Input Capacitance All Inputs VR Chroma Bias Voltage 0.3 Vee Icc Supply Current 90 -100 p-Adc VOH = 2.4V 1.6 mAdc VOL = 0.4 Vdc 7.5 5-206 pF Vdc 114 mAdc VIN = 0 TA = 25°C f = 1.0 MHz CLoad = 20 pF RLoad = 200 k!l Vee = 4.75 - 5.25 V F6847 DC Characteristics (Cont.) Symbol Vec/JA Vec/JB Vv VWL VWM VWH Characteristic Typ Max Unit Conditions Chroma q,A Voltage VHI Vo VLO VR + 0.1 Vee VR VR - 0.1 Vee Vdc CLoad = 20 pF RLoad = 200 kO See Figure 2 Chroma q,B Voltage Vo VBurst VLO VR + 0.1 Vee VR VR - 0.05 Vee VR - 0.1 Vee Vdc CLoad = 20 pF RLoad = 200 kO See Figure 2 Luminance V Voltage Vs VBLANK VBLAeK 0.2 Vee 0.75 Vs 0.7 Vs Vdc CLoad = 20 pF RLoad = 200 kO See Figure 2 Voltage White Low Voltage White Medium Voltage White High 0.62 0.5 Vs 0.38 Vs Vdc See Figure 2 AC Characteristics Symbol Min Vee = 5.0 V ±5%, TA = O°C to 70°C Characteristic f CLKdc ClK Frequency CLK Duty Cycle tVA tVB Chroma Phase Delay (Measured with Respect to Y Output) q,A q,B try tty Min Typ Max Unit 3.579535 45% 3.579545 50% 3.579555 55% MHz Conditions See Figure 3C 200 200 ns ns Luminance Rise Time Luminance Fall Time 60 50 ns ns trCq,B t,CB Chroma Rise and Fall Times q,A Rise Time q,A Fall Time q,B Rise Time q,B Fall Time 60 60 60 60 ns ns ns ns tWFS Field Sync (FS) Pulse Width 2.03 ms See Figure 3A tWRP tHSRP Row Preset (RP) Pulse Width Delay from HS 0.98 0.98 I'-S I'-S See Figure 38 tWHS Horizontal Sync (HS) 4.9 I'-s See Figure 38 trCq,A t,Cq,A 5-207 See Figure 3D See Figure 3D • F6847 Fig. 2 Video and Chrominance Relationships Output Waveform Left Border Righi Border I I ~ ~:I-----.U. . __ I I Active Video L...-----'.-----tf V_3S.7_S"..... End 01 Horizontal Sync A/G ~G • CSS AlG • CSS + AlG - II ----'1 CSS _~~_ o L-I . ..&....-_ _ >B l(BUrslIB Removed for AlG • CSS • GMol Magenta Orange Red Blue BuH Cyan Fig. 3 Timing Diagrams a. Field Sync FS---"", b. Row Preset Leading Edgs 01 Vert. Blanking tWHS HS---"" 1 - - - - - - IWFS - - - - - - 1 d. Video and Fall Times c. Chroma Phase Delay h iiP-------...... v _ _ _ _ _ _ _ _- J y IYA -+__J >A ________________ >A >B >B------Iy. 5·208 SRP -:.Jl Level #2 :A Level #2 r- ;WRP~ k . Jr. I- ~c. F6847 Ordering Information Order Code F6847P, S P S Temperature Range DOC to +7DoC = Plastic Package = Ceramic Package II 5-209 F6847 5-210 FAIRCHILD A Schlumberger Company F6850/F68A50/F68B50 Asynchronous Communications Interface Adapter (ACIA) Microprocessor Product Description The F6850 Asynchronous Communications Interface Adapter (ACIA) provides the data formatting and control to interface serial asynchronous data communications information to bus-organized systems, such as the F6800 microprocessing unit (MPU). Logie Symbol 22 21 20 19 18 17 16 15 esO The bus interface of the F6850 includes select, enable read/write, interrupt, and bus interface logic to allow data transfer over an 8-bit bidirectional data bus. The parallel data olthe bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of the ACIA is programmed via the data bus during system initialization. A programmable control register provides variable word lengths, clock division ratios, transmit control, receive control, and interrupt control. For peripheral or modem operation, three control lines are provided. These lines allow the ACIA to interface directly with a 0-600 bps modem. 10 eS1 F6850 es. 11 RS 23 24 14 • 13 = Vee Pin 12 Vss = Pin 1 • 8- and 90Bit Transmission • • • • • • • • • Optional Even and Odd Parity Parity, Overrun, and Framing Error Checking Programmable Control Register Optional +1, +16, and +64 Clock Modes Up to 1.0 Mbps Transmission False Start Bit Deletion Peripheral/Modem Control Functions Double Buffered One or Two Stop Bit Operation Connection Diagram 24-Pin DIP Rx DATA Rx DATA Rx ClK Tx ClK CSo, CS1, CS2 RS CTS E Riw RTS Tx DATA IRQ DCD oeD RxCLK Pin Functions 00- 0 7 eTS Vss Bidirectional Data Lines Receive Data Input Receive Clock Input Transmit Clock Input Chip Select Inputs Register Select Input Clear-to-Send Input Enable Input Read/Write Input Request-to-Send Output Transmit Data Output Interrupt Request Output Data Carrier Detect Output Do Tx elK 01 RTS D. Tx DATA 03 IRQ 0, eso Os Cs. Os eS1 Dr RS RiW Vee (Top View) 5·211 F6850/F68A50/F68B50 Block Diagram TRANSMIT CLOCK (Tx CLK) ENABLE (E) READIWRITE (R!W) ====::'--1 + _I CHIP SELECT 0 (CSo) CHIP SELECT 1 (CS1) CHIP SELECT 2 (Cs2) - CHIP SELECT AND READ/WRITE CONTROL LJ~~.t!!.j----~ TRANSMIT DATA (Tx DATA) REGISTER SELECT (RS) _ 1-.---- CLEAR-TO-SEND (eTS) Do0102- 0.0.Da- DATA BUS BUFFERS \ - - - - _ _ _ INTERRUPT REOUEST (IRO) L_~==:;:=~ ____ DATA CARRIER DETECT (DCD) 05- r--L---l---t-l------_ REOUEST-TO-SEND (RTS) Il>- RECEIVE CLOCK (Rx CLK) - - - - - - - - - - - - - _ Functional Description Transmit At the bus interface, the ACIA appears as two addressable memory locations. Internally, there are four registers: two read-only and two write-only. The read-only registers are status and receive data; the write-only registers are control and transmit data. The serial interface consists of serial input and output lines with independent clocks, and three peripheral/modem control lines. A typical transmitting sequence consists of reading the ACIA status register either as a result of an interrupt or in turn in a polling sequence. A character may be written into the transmit data register if the status read operation has indicated that the transmit data register is empty. This character is transferred to a shift register, where it is serialized and transmitted from the transmit data (Tx DATA) output preceded by a start bit and followed by one or two stop bits. Internal parity (odd or even) can be optionally added to the character, and occurs between the last data bit and the first stop bit. After the first character is written in the data register, the status register can be read again to check for a transmit data register empty condition and current peripheral status. If the register is empty, another character can be loaded for transmission even though the first character is in the process of being transmitted (because of double buffering). The second character is transferred automatically into the shift register when the first character transmission is completed. This sequence continues until all the characters have been transmitted. Power On/Master Reset The master reset (CRO, CR1) should be set during system initialization to ensure the reset condition and prepare for programming the ACIA functional configuration when the communications channel is required. Control bits CR5 and CR6 should also be programmed to define the state of the request-to-send (RTS) output whenever master reset is utilized. The ACIA also contains internal power-on reset logic to detect the power line turn-on transition and hold the chip in a reset state to prevent erroneous output transitions prior to initialization. This circuitry depends on clean power turn-on transitions. The power-on reset is released by means of the bus-programmed master reset, which must be applied prior to operating the ACIA. After master resetting the ACIA, the programmable control register can be set for a number of options, such as variable clock divider ratios, variable word length, one or two stop bits, and parity (even, odd, or none). Receive Data is received from a peripheral by means of the receive data (Rx DATA) input. A divide-by-one clock ratio is provided for an externally synchronized clock (to its data) while the divide-by-16 and -64 ratios are provided for internal synchronization. Bit 5-212 F6850/F68A50/F68B50 synchronization in the divide-by-16 and -64 modes is initiated by the detection of 8 or 32 LOW samples, respectively, on the receive data line. False start bit deletion capability ensures that a full half bit of a start bit has been received before the internal clock is synchronized to the bit time. As a character is being received, parity (odd or even) is checked and the error indication made available in the status register along with framing error, overrun error, and receive data register full. In a typical receiving sequence, the status register is read to determine if a character has been received from a peripheral. lithe receive data is full, the character is placed on the 8-bit ACIA bus when a read data command is received from the MPU. When parity has been selected for an 8-bit word (seven bits plus parity), the receiver strips the parity bit (07 = 0) so that data alone is transferred to the MPU. This feature reduces MPU programming. The status register can be read again to determine when another character is available in the receive data register. The receiver is also double buffered so that a character can be read from the data register as another character is being received in the shift register. The above sequence continues until all characters have been received. Chip Select (CSo. CS1. CS2) These three high-impedance, TTL-compatible input lines are used to address the ACIA. The ACIA is selected when CSO and CS1 are HIGH and CS2 is LOW. Transfers of data to and from the ACIA are then performed under the control of the E, R/W, and RS signals. Register Select (RS) The register select line is a high-impedance input that is TTL-compatible. A HIGH level is used to select the transmit/receive data registers and a LOW level the control/status registers. The Riw signal line is used in conjunction with RS to select the read-only or write-only register in each register pair. Interrupt Request (IRQ) Interrupt request is a TTL-compatible, open-drain (no internal pull-up), active-LOW output that is used to interrupt the MPU. The IRQ output remains LOW as long as the cause of the interrupt is present and the appropriate interrupt enable within the ACIA is set. The IRQ status bit, when HIGH, indicates that the IRQ output is in the active state. Input/Output Functions The ACIA interfaces to the F6800 MPU through an 8-bit bidirectional data bus, three chip select lines, a register select line, an interrupt request line, read/write line, and enable line. These signals, in conjunction with F6800 VMA output, permit the MPU to have complete control over the ACIA. Interrupts result from conditions in both the transmitter and receiver sections of the ACIA. The transmitter section causes an interrupt when the transmitter interrupt enabled condition is selected (CRs • CRs), and the transmit data register empty (TORE) status bit is HIGH. The TORE status bit indicates the current status of the transmitter data register except when inhibited by the CTS line being HIGH or the ACIA being maintained in the reset condition. The interrupt is cleared by writing data into the transmit data register. The interrupt is masked by disabling the transmitter interrupt via CRs or CRs, or by the loss of CTS, which inhibits the TORE status bit. The receiver section causes an interrupt when the receiver interrupt enable is set and the receive data register full (RORF) status bit is HIGH, an overrun has occurred, or the data carrier detect (DCO) line has gone HIGH. An interrupt resulting from the RORF status bit can be cleared by reading data or resetting the ACIA. Interrupts caused by overrun or loss of OCO are cleared by reading the status register after the error condition has occurred and then reading the receive data register or resetting the ACIA. The receiver interrupt is masked by resetting the receiver interrupt enable. ACIA Bidirectional Data (DO - 0]) The bidirectional data lines (00-07) allow for data transfer between the ACIA and the MPU. The data bus output drivers are 3-state devices that remain in the high-impedance (OFF) state except when the MPU performs an ACIA read operation. ACIA Enable (E) The enable signal (E) is a high-impedance, TTL-compatible input that enables the bus input/output data buffers and clocks data to. and from the ACIA. This Signal normally is a derivative of the F6800 >2 clock. Read/Write (R/W) The read/write line is a high-impedance input that is TTL -compatible and is used to control the direction of data flow through the ACIA input/output data bus interface. When R/W is HIGH (MPU read cycle), ACIA output drivers are turned on and a selected register is read. When it is LOW, the ACIA output drivers are turned off and the MPU writes into a selected register. Therefore, the Riw signal is used to select read-only or write-only registers within the ACIA. Clock Inputs Separate high-impedance, TTL-compatible inputs are provided for clocking of transmitted and received data. Clock frequencies of 1, 16, or 64 times the data rate may be selected. Transmit Clock (Tx ClK) The transmit clock input is used for the clocking of transmitted data. The transmitter initiates data on the negative transition of the clock. 5-213 5 F6850/F68A50/F68B50 Transmit Data Register (TOR) Data is written into the tranSmit data register during the negative transition of the E (Enable) pulse when the ACIA has been addressed with AS HIGH and Aiw LOW. Writing data into the register causes the TDAE bit in the status register to go lOW. Data can then be transmitted. If the transmitter is idling and no character is being transmitted, the transfer takes place within one bit time of the trailing edge of the write command. If a character is being transmitted, the new data character commences as soon as the previous character is complete. The transfer of data causes the TDAE bit to indicate empty. Receive Clock (Rx ClK) The receive clock input is used for synchronization of received data. (In the 71 mode, the clock and data must be synchronized externally.) The receiver samples the data on the positive transition of the clock. Serial Input/Output lines Receive Data (Rx DATA) The receive data line is a high-impedance, TTL-compatible input through which data is received in a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Receive Data Register (RDR) Data is automatically transferred to the empty receive data register (ADA) from the receiver deserializer (a shift register) upon receiving a complete character. This event causes the receive data register full (ADRF) bit in the status buffer to go HIGH (full). Data may then be read through the bus by addressing the ACIA and selecting the ADA with RS and A/W HIGH when the ACIA is enabled. The non-destructive read cycle causes the ADAF bit to be cleared to empty although the data is retained in the ADA. The status is maintained by the RDRF bit to indicate whether or not the data is current. When the receive data register is full, the automatic transfer of data from the receiver shift register to the data register is inhibited and the ADA contents remain valid, with its current status stored in the status register. Transmit Data (Tx DATA) The transmit data output line transfers serial data to a modem or other peripheral. Peripheral/Modem Control The ACIA includes several functions that permit limited control of a peripheral or modem. The functions included are clear-to-send, request-to-send and data carrier detect. Clear-to-Send (CTS) This high-impedance, TTL-compatible input provides automatic control of the transmitting end of a communications link via the modem clear-to-send active-LOW output by inhibiting the transmit data register empty (TDAE) status bit. Request-to-Send (RTS) The request-td-send output enables the MPU to control a peripheral or modem via the data bus. The ATS output corresponds to the state of control register bits CAs and CA6. When CA6 = 0 or both CAs and CA6 = 1, the ATS output is LOW (the active state.) This output can also be used for data terminal ready(DTA). . Control Register The ACIA control register consists of eight bits of write-only buffer that are selected when AS and A/Ware LOW. This register controls the function of the receiver, transmitter, interrupt enables, and the request-to-send peripheral/modem control output. Data Carrier Detect (DCD) This high-impedance, TTL-compatible input provides automatic control, such as in the receiving end of a communications link, by means of a modem Data Carrier D~tect output.The DCD input inhibits and initializes the receiver section of the ACIA when HIGH. A LOW-to-HIGH transition of DCD initiates an interrupt to the MPU to indicate the occurrence of a loss of carrier when the receive interrupt enable bit is set. The AxCLK must be running for proper DCD operation. Counter Divide Select Bits (CRo and CRt) The counter divide select bits (CAO and CAt) determine the divide ratios utilized in both the transmitter and receiver sections of the ACIA. Additionally, these bits are used to provide a master reset for the ACIA that clears the status register (except for external conditions on CTS and DC D) and initializes both the receiver and transmitter. Master reset does not affect other control register bits. Note that after power-on or a power fail/start, these bits must be set HIGH to resetthe ACIA. After resetting, the clock divide ratio may be selected. ACIA Registers The block diagram for the ACIA indicates the internal registers on the chip that are used for the status, control, receiving, and transmitting of data. The content of each of the registers is summarized in Table 1. 5·214 F6850/F68A50/F68B50 Table 1 Definition of ACIA Register Contents Buffer Address Data Bus Line Number RS'RlW Transmit Data Register RS' R/W Receive Data Register (Write Only) (Read Only) o· -- RS, R/W Control Register RS' R/W Status Register (Write Only) . (Read Only) 0 Data Bit Data Bit 0 Counter Divide Select 1 (CRo) Receive Data Register Full (RDRF) 1 Data Bit 1 Data Bit 1 Counter Divide Select 2 (CR1) Transmit Data Register Empty (TORE) 2 Data Bit 2 Data Bit 2 Word Select 1 (CR2) Data Carrier Detect (DCD) 3 Data Bit 3 Data Bit 3 Word Select 2 (CR3) Clear-Io-Send (CTS) 4 Data Bit 4 Data Bit 4 Word Select 3 (CR4) Framing Error (FE) 5 Data Bit 5 Data Bit 5 Transmit Control 1 (CRs) Receiver Overrun (OVRN) 6 Data Bit 6 Data Bit 6 Transmit Control 2 (CRs) Parity Error (PE) 7 Data Bit 7'" Data Bit 7*' Receive Interrupt Enable (CR7) Interrupt Request (IRQ) = LSB = Bit 0 'Leading bit "Data bit is zero in 7-bit plus parity modes. "'Data bit is "don't care" in 7-bit plus parity modes. request-to-send (RTS) output, and the transmission of a break level (space). The following encoding format is used: These counter select bits provide for the following clock divide ratios: CRl CRO Function CR6 CRS Function 0 0 1 1 0 ~1 o o 0 RTS = LOW, Transmitting Interrupt Disabled RTS = LOW, Transmitting Interrupt Enabled RTS = HIGH, Transmitting Interrupt Disabled RTS = LOW, Transmits a Break Level on the Transmit Data Output. Transmitting Interrupt Disabled. ~16 0 1 ~64 Master Reset Word Select Bits (CR2. CR3 and CR4) The word select bits are used to select word length, parity, and the number of stop bits. The encoding format is as follows: CR4 CR3 CR2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Interrupt Enable Bit (CR7) The following interrupts are enabled by a HIGH level in bit position 7 of the control register (CR7): receive data register full, overrun, or a LOW-to-HIGH transition on the data carrier detect (DCD) signal line. Function 7 7 7 7 8 8 8 8 Bits Bits Bits Bits Bits Bits Bits Bits 1 o + Even Parity + 2 Stop Bits + Odd Parity + 2 Stop Bits + Even Parity + 1 Stop Bit + Odd Parity + 1 Stop Bit + 2 Stop Bits + 1 Stop Bit + Even Parity + 1 Stop Bit + Odd Parity + 1 Stop Bit Status Register Information on the status of the ACIA is available to the MPU by reading the ACIA status register. This read-only register is selected when RS is LOW and R/W is HIGH. Information stored in this register indicates the status of the transmit data register. the receive data register and error logic. and the peripheral/modem status inputs of the ACIA. Receive Data Register Full (RDRF). Bit 0 Receive data register full indicates that received data has been transferred to the receive data register. The RDRF bit is cleared after an MPU read of the receive data register or by a master reset. The cleared or empty state indicates that the Word length, parity select, and stop bit changes are not buffered and therefore become effective immediately. Transmitter Control Bits (CRs and CR6) Two transmitter control bits provide for the control of the interrupt from the transmit data register empty condition, the 5·215 • F6850/F68A50/F68B50 contents of the receive data register are not current. Data carrier detect being HIGH also causes RDRF to indicate empty. Transmit Data Register Empty (TORE). Bit 1 The transmit data register empty bit being set HIGH indicates that the transmit data register contents have been transferred and that new data may be entered. The LOW state indicates that the register is full and that transmission of a new character has not begun since the last write data command. Parity Error (PE). Bit 6 The parity error flag indicates that the number of HIGHs (1 's) in the character does not agree with the preselected odd or even parity. Odd parity is defined to be when the total number of ones is odd. The parity error indication is present as long as the data character is in the RDA. If no parity is selected, both the transmitter parity generator output and the receiver parity check results are inhibited. Interrupt Request (IRQ). Bit 7 Data Carrier Detect (DC D). Bit 2 The data carrier detect bit is HIGH when the DCD input from a modem has gone HIGH to indicate that a carrier is not present. This bit going HIGH causes an interrupt request to be generated when the receive interrupt enable is set. It remains HIGH after the DCD input is returned LOW until cleared by reading first the status register and then the data register, or until a master reset occurs. If the DCD input remains HIGH after read status and read data or master reset has occurred, the interrupt is cleared, and the DCD stat~s bit remains HIGH and will follow the DCD input. The IRQ bit indicates the state of the IRQ output. Any interrupt condition with its applicable enable is indicated in this status bit. Any time the IRQ output is LOW, the IRQ bit is HIGH to indicate the interrupt or service request status. The IRQ bit is cleared by a read operation to the receive data register or a write operation to the transmit data register. Clear-to-Send (CTS). Bit 3 The clear-to-send bit indicates the state of the clear-to-send input from a modem. A LOW CTS indicates that there is a clear-to-send from the modem. In the HIGH state, the transmit data register empty bit is inhibited and the clear-to-send status bit is HIGH. Master reset does not affect the clear-to-send status bit. Framing Error (FE). Bit 4 Framing error indicates that the received character is improperly framed by a start and a stop bit and is detected by the absence of the first stop bit. This error indicates a synchronization error, faulty transmission, or a break condition. The framing error flag is set or reset during the receive data transfer tiine. Therefore, this error indicator is present throughout the time that the associated character is available. Receiver Overrun (OVRN). Bit 5 Overrun is an error flag that indicates that one or more characters in the data stream were lost. That is, a character or a number of characters were received but not read from the receive data register (RDR) prior to subsequent characters being received. The overrun condition begins at the midpoint of the last bit of the second character received in succession without a read of the RDR having occurred. The overrun does not occur in the status register until the valid character prior to overrun has been read. The RDRF bit remains set until the overrun is reset. Character synchronization is maintained during the overrun condition. The overrun indication is reset after the reading of data from the receive data register or by a master reset. 5-216 F6850/F68A50/F68B50 Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static Supply Voltage Input Voltage Operating Temperature - T L. T H F6850. F68A50. F68B50 F6850C. F68A50C F6850Dl F6850DM Storage Temperature Range Thermal Resistance Ceramic Plastic DC Characteristics Symbol Vee = 5.0 -0.3V. -0.3 V. +7.0V +7.0 V O'C. -40'C. -55"C. -55°C. -55'C. + 70°C +85°C +85°C +125°C +150°C voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. 60'C/W 120'C/W V ±5%. VSS Characteristic = O. TA = TL to TH. unless otherwise noted Signal Typ Max Unit VIH Input HIGH Voltage 2.0 Vee V VIL Input lOW Voltage -0.3 0.8 V liN Input leakage Current R/W. CSo. CSt. CS2. RS. Rx DATA. Rx ClK. CTS. DCD 1.0 2.5 ,.,..A VIN = 0 to ITSI 3-State Input Current (OFF State) Do-D7 2.0 10 ,.,..A VIN = 0.4 to VOH Output HIGH Voltage Do-D7 2.4 Tx DATA. RTS 2.4 VOL Output lOW Voltage ILOH Output leakage Current Po Power Dissipation CIN Input Capacitance COUT Output Capacitance Min IRQ V RTS. Tx DATA IRQ 5·217 5.25 V 2.4 V ILoad = -205 ,.,..A. Enable Pulse Width < 25,.,..s ILoad = -100 ,.,..A. Enable Pulse Width < 25,.,..s 0.4 V 10 ,.,..A 300 525 mW 10 7.0 12.5 7.5 pF 10 5.0 pF 1.0 Do-D7 E. Tx ClK. Rx ClK. R/W. RS. Rx DATA. CSo. CS,. CS2. CTS. DCD Condition ILoad = 1.6 mAo Enable Pulse Width < 25,.,..s VOH VIN f = VIN f = = 2.4 V = O. TA = 25~C. 1.0 MHz = O. TA = 25°C. 1.0 MHz • F6850/F68A50/F68B50 AC Characteristics Vcc = 5.0 V ±5%, Vss = 0, TA = TL to TH, unless otherwise noted F68S0 Symbol Characteristic Min F68ASO Max Min PWCL Minimum Clock Pulse Width, LOW +16, +64 Modes 600 450 PWCH Minimum Clock Pulse Width, HIGH +16, +64 Modes 600 450 fc Clock Frequency +1 Mode +16, +64 Modes 600 Clock-to-Data Delay for Transmitter tROS Receive Data Set-up Time +1 Mode 250 tROH Receive Data Hold Time +1 Mode 250 tlR Interrupt Request Release Time tRTS Request-to-Send Delay Time tr, tl Input Transition Times (Except Enable) Unit Condition 280 ns Figure 1 280 ns Figure 2 Min 750 1000 500 800 tTOO F68BSO Max 1000 1500 460 540 100 , Max 30 100 30 kHz ns Figure 3 ns Figure 4 ns Figure 5 1.2 0.9 0.7 /Ls Figure 6 560 480 400 ns Figure 6 1.0 0.5 0.25 /Ls Note Note 1.0"", or 10% of the pulse width. whichever Is smalier Bus Timing Characteristics Read (Figures 7 and 9) F68S0 Symbol Characteristic Min F68ASO Max 1.0 Min Max F68B50 Min Max Unit lcycE Enable Cycle Time PWEH Enable Pulse Width, HIGH 0.45 PWEL Enable Pulse Width, LOW 0.43 0.28 0.21 /Ls tAS Set-up Time, Address, and R/W Valid to Enable Positive Transition 160 140 70 ns 0.500 0.666 25 0.28 25 0.22 /LS 25 /LS tOOR Data Delay Time IH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 10 ns tEn tEl Rise and Fall Time for Enable Input 320 220 25 180 25 25 ns ns Write (Figures Band 9) IcycE Enable Cycle Time PWEH Enable Pulse Width, HIGH PWEL Enable Pulse Width, LOW tAS 1.0 0.666 0.45 .. 25 0.28 0.500 25 0.22 /LS 25 /LS 0.43 0.28 0.21 /Ls Set-up Time, Address, and R/W Valid to Enable Positive Transition 160 140 70 ns tosw Data Set-up Time 100 80 60 ns tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 10 tEr. tEl Rise and Fall Time for Enable Input 25 5-218 10 25 ns 25 ns ; F6850/F68A50/F68850 Fig. 1 Clock Pulse Width, LOW State Fig. 5 Receive Data Hold Time (+1 Mode) PWCL /I - - - ' /2.0V TX eLK OR RXCLK _ _ _ RX elK --- I---'RDH --------2.0-V~X~-------------- Fig.2 RX DATA Clock Pulse Width, HIGH State 0.8 V Fig. 6 TX eLK OR RX elK Request-to-Send Delay and Interrupt Request Release Times PWCH E Fig. 3 Transmit Data Output Delay \f<.'~;;:;'.8":"V _ _ _ _ _ __ X 2.4V ------If-oJ r- '+:;.0.4;..V'--_ _ _ _ __ ..--.-----11R ----' _ TX DATA iRO Fig. 7 Fig.4 Receive Data Set-up Time (+1 Mode) Bus Read Timing Characteristics (Read Information from ACIA) ~2.0V RXDATA~~0~.8~V_ _ _ _ _ _ _ _ _ __ __I ¥,--- 'RDSU RS,C$,RtW RX CLK 0.8 V DATA BUS 5·219 2.4 V . F6850/F68A50/F68B50 Fig. 8 Fig. 9 Bus Write Timing Characteristics (Write Information Into ACIA) Bus llmlng Test Loads Load A (Do-Dr, RTS, Tx DATA) 1+---IcycE------<~ 5.0 V E TEST POINT RS. CS, RtW -J~~--+-~~,-- ___ C = 130 pF FOR~-D-r C = 30 pF FOR RTS AND Tx DATA C R =: !~.:n~~~R~~~D Tx DATA -= DATA BUS Load B (IRQ Only) TEST POINT d:'I 100pF 5·220 F6850/F68A50/F68B50 Ordering Information Speed Order Code 1.0 MHz F6850P,S F6850ep,eS F6850DL F6850DM F68A50P,S F68A50ep,eS F68B50DM F68B50P,S 1.5 MHz 2.0 MHz P Temperature RallRe ooe to lO'e - 40 0 e to + 85°e -55'e to +85'e - 55°e to + 125°e ooe to + lOoe - 40'e to + 85°e - 55°e to + 125°e ooe to + lO'e = Plastic package, S = Ceramic package • 5·221 F6850/F68A50/F68B50 5-222 F68521F68A52/F68B52 FAIRCHILD Synchronous Serial Data Adapter A Schlumberger Company Microprocessor Product Logic Symbol Description The F6852 Synchronous Serial Data Adapter (SSDA) provides a bidirectional serial interface for synchronous data information interchange. It contains interface logic for simultaneously transmitting and receiving standard synchronous communications characters in bus-organized systems, such as the F6800 microprocessor systems. 10 11 14 13 Rx DATA Rx elK The bus interface of the F6852 includes Select, Enable, Read/Write, Interrupt, and bus interface logic to allow data transfer over an 8-bit bidirectional data bus. The parallel data of the bus system is transmitted serially and received by the synchronous data interface with synchronization, fill character insertion/deletion, and error checking. The functional configuration of the SSDA is programmed via the data bus during system initialization. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing, and control lines provide peripheral or modem control. Tx DATA Tx elK IRO RESET TUF 24 CTS 23 DCD SM/Il'fR 22 21 20 19 18 17 16 15 Vss ~ Pin 1 Vee ~ Pin 12 Connection Diagram 24·Pln DIP Typical applications include floppy disk controllers, cassette or cartridge tape controllers, data communications terminals, and numerical control systems. • Programmable Interrupts from Transmitter, Receiver, and Error Detection Logie • Character Synchronization on 1 or 2 SYNC Codes • External Synchronization Available for Parallel-Serial Operation • Available Speeds: 1.0 MHz for the F6852, 1.5 MHz for the F68A52, and 2.0 MHz for the F68B52 • Programmable SYNC Code Register • Up to 600K BPS Transmission • Peripheral/Modem Control Functions • 3 Bytes of FIFO Buffering on Both Transmit and Receive • 7-, 8-, or 9-Bit Transmission • Optional Even and Odd Parity • Parity, Overrun, and Underflow Status (Top View) 5-223 F68521F68A52/F68B52 Pin Names Rx DATA RxCLK TxCLK SM/DTR Tx DATA IRQ TUF RESET CS RS CTS DCD 00-07 E R/iii Vss Vee Receive Data Input Receive Clock Input Transmit Clock Input Sync Match/Data Terminal Ready Output Transmit Data Output Interrupt Request Output Transmitter Underflow Output Reset Input Chip Select Input Register Select Input Clear-to-Send Input Data Carrier Detect Input Bidirectional Data Lines Enable (System <1>2 Clock) Input Read/Write Input Ground Input +5 V Power Supply Input Block Diagram ENABLE 1----------. ~~~:SMIT READ/WAiTe CHIP SELECT ~j:l~~---------- TRANSMITTER REGISTER SELECT r UNDERFLOW 1-....- - - - - - - - - CLEAR-TO-SEND Do 0, 0, 0, D. Os D. r.~~;;;-').++-I--I---_L--- RECEIVE "~~~~::::::::::::~~::~L~~~J''''''1111------ DATA RECEIVE CLOCK SYNC 1------.... ~:~~~ERMINAL READY 5-224 F6852/F68A52/F68B52 (TUFI. The transmitter and receiver each have individual clock inputs, allowing simultaneous operation under separate clock control. Signals to the microprocessor are the data bus and Interrupt Request (IRQ). Device Operation At the bus interface, the SSDA appears as two addressable memory locations. Internally, there are seven registers: two read-only and five write-only registers. The read-only registers are status and receive data; the write-only registers are control 1, control 2, control 3, sync code, and transmit data. The serial interface consists of serial input and output lines with independent clocks, and four peripheral/modem control lines. Data to be transmitted is transferred directly into the 3-byte transmit data first-in, first-out (FIFO) register from the data bus. Availability of the input to the FIFO is indicated by a bit in the status register; once data is entered, it moves through the FIFO to the last empty location. Data at the output of the FIFO is automatically transferred from the FIFO to the transmitter shift register as the shift register becomes available to transmit the next character. If data is not available from the FIFO lunderflow condition I, the transmitter shift register is automatically loaded with either a sync code or an all"1s" character. The transmit section may be programmed to append even, odd, or no parity to the transmitted word. An external Clear-to-Send (CTS) control line is provided to inhibit the transmitter without clearing the FIFO. Serial data is accumulated in the receiver based on the synchronization mode selected. In the external sync mode, used for parallel-serial operation, the receiver is synchronized by the Data Carrier Detect (DCDI input and transfers successive bytes of data to the input of the receiver FIFO. The single-sync-character mode requires that a match occur between the sync code register and one incoming character before data transfer to the FIFO begins. The two-sync-character mode requires that two sync codes be received in sequence to establish synchronization. Subsequent to synchronization in any mode, data is accumulated in the shift register and parity is optionally checked. An indication of parity error is carried through the receiver FI FO with each character to the last empty location. Availability of a word at the FIFO output is indicated by a bit in the status register, as is a parity error. Initialization Du ri ng a power-on seq uence, the SSDA is reset via the RESET input and internally latched in a' reset condition to prevent erroneous output transitions. The sync code register, control register 2, and control register 3 should be programmed prior to the programmed release of the transmitter and/or receiver reset bits; these bits in control register 1 should be cleared after the RESET line has gone HIGH. Transmitter Operation Data is transferred to the transmitter section in parallel form by means of the data bus and transmit data FIFO. The transmit data FIFO is a 3-byte register whose status is indicated by the transmitter data register available (TDRA) status bit and its associated interrupt enable bit. Data is transferred through the FIFO on negative edges of Enable I E I pulses. Two data transfer modes are provided in the SSDA. The 1-byte transfer mode provides for writing data to the transmitter section (and reading from the receiver section lone byte at a time. The 2-byte transfer mode provides for writing two data characters in succession. Data will automatically transfer from the last register location in the transmit data FIFO (when it contains datal to the transmitter shift register during the last half of the last bit of the previous character. A character is transferred into the shift register by the Transmit Clock. Data is transmitted LS8 first, and odd or even parity can be optionally appended. The unused bit positions in short word length characters from the data bus are "don't cares". (Note: The. data bus inputs may be reversed for applications requiring the MSB to be transferred first, e.g., IBM format for floppy disks; however, care must be taken to program the control registers properly - Table 1 will have its bit positions reversed.) When the shift register becomes empty, and data is not available for transfer from the transmit data FIFO, an underflow occurs, and a character is inserted into the transmitter data stream to maintain character synchronization. The character transmitted on underflow will be either a mark (all "1s") or the contents of the sync code register, depending upon the state of the transmit sync code on underflow control bit. The underflow condition is indicated by a pulse (~ Tx ClK HIGH period I on the Transmitter Underflow output (when in Tx Sync on underflow model. The Transmitter Underflow output The SSDA and its internal registers are selected by the address bus, Read/Write (R/iN\ and Enable control lines. To configure the SSDA, control registers are selected and the appropriate bits set. The status register is addressable for reading status. Other I/O lines, in addition to Clear-to-Send I CTSI and Data Carrier Detect (DCDI, include Sync Match/Data Terminal Ready I SM/DTR I and Transmitter Underflow 5·225 F68521F68A521F68B52 occurS coincident with the transfer of the last half of the last bit preceding the underflow character. The underflow status bit is set until cleared by'means of the clear underflow control bit. This output may be used in floppy disk systems to synchronize write operations and for appending CRCC. code detection techniques require custom logic external to the SSDA for character synchronization and use of the parallel-to-serial (external sync) mode. (Note: The receiver shift register is set to "1 s" when resel..} Synchronization The SSDA provides three operating modes with respect to character synchronization: orie-sync-character mode, two-sync-character mode, and external sync mode: The' external sync mode requires synchronization and control of the receiving section through the Data Carrier Detect (i5CD) input Isee Figure 7). This external synchroni-' zation could consist of direct line control from the transmitting end of the serial data link or from external logic designed to detect the start of the message block. The one-sync-character mode searches on a bit-by-bit basis until a match is achieved between the data in the shift register and the sync code register. The match indicates character synchronization is complete and will be retained for message block. In the two-synccharacter mode, the receiver searches for the first sync code match on a bit-by-bit basis and then looks for a second successive sync code character pdor to establishing character synchronization. If the second sync code character is not received, the bit-by-bit search for the first sync code is resumed. Transmission is initiated by clearing the transmitter reset bit in control register 1. When the transmitter reset bit is cleared, the first full positive half-cycie of the Transmit Clock will initiate the transmit cycle, with the transmission of data or underflow characters beginning on the negative edge of the Transmit 'Clock pulse that started the cycle. If the transmit data FIFO was not loaded, an underflow character will be transmitted (see Figure 41. The Clear-to-Send (CTSI input provides for automatic control of the transmitter by means of external system hardware; e.g., the modem CTs output provides the control in a data communications system. The ffi input resets and inhibits the transmitter section when HIGH, but does not reset the transmit data FIFO. The TDRA status bit is inhibited by ffi being HIGH in either the one-sync-character or two-sync-character mode of operation. In the external sync mode, TDRA is unaffected by CTS in order to provide transmit data FIFO status for preloading and operating the transmitter under the control of the Ci'S input. When the transmitter reset bit (Tx Rs) is set, the transmit data FIFO is cleared and the TDRA status bit is cleared. After one E clock has occurred, the transmit data FIFO becomes available for new data with TDRA inhibited. Sync codes received prior to the completion of synchronization (one or two characters) are not transferred to the receive data FIFO. Redundant sync codes during the preamble or sync codes that occur as "fill characters" can be automatically stripped from the data, when the strip sync control bit is set, to minimize system loading. The character synchronization will be retained until cleared by means of the clear sync bit. which also inhibits synchronization search when set. Receiver Operation Data and a presynchronized clock are provided to the SSDA receiver section by means of the Receive Data (Rx DATA) and Receive Clock Iflx CLK} inputs. The data is a continuous stream of binary data bits without means for identifying character boundaries within the stream. It is, therefore, necessary to achieve character synchronization for the data at the beginning of the data block. Once synchronization is achieved, it is assumed to be retained for all successive characters within the block. Receiving Data Once synchronization has been achieved, subsequent characters are automatically transferred into the receive data FIFO and clocked through the FIFO to the last empty location by E pulses (MPU system <1>2). The receiver data available (RDA) status bit indicates when data is available to be read from the last FIFO location INo. 3) when in the 1-byte transfer mode. The 2-by'te transfer mode causes the RDA status ,bit to indicate data is available when the last two FIFO register locations are full. Data being available in the receive data FIFO causes an interrupt request if the receiver interrupt enable (RIE) bit is set. The MPU will then read the SSDA status register, which will indicate that data is available for the MPU read from the receive data FIFO register. The IRQ and RDA status bits are reset by a read from the FIFO. If more than 'one character has been , .."eived and is resident in the receive data FIFO. Data communication systems utilize the detection of sync codes during the initial portion of the preamble to establish character synchronization. This requires the detection of a single code or two successive sync codes. Floppy disk and cartridge' tape units require 16 bits of defined preamble and cassettes require eight bits of preamble to establish the reference for the start of record. All three, are functionally equivalent to the detection of sync codes. Systems that do not utilize 5-226 F6852/F68A52/F68852 subsequent E clocks will cause the FIFO to updat.e, and the ROA and IRQ status bits will be set again. The read data operation for the 2-byte transfer mode requires an intervening E clock between reads to allow the FIFO data to shift. Optional parity is automatically checked as data is received, and the parity status condition is maintained with each character until the data is read from the receive data FIFO. Parity errors will cause an interrupt request if the error interrupt enable (EI E has been set. The parity bit is not transferred to the data bus but must be checked in the status register. Note: In the 2-byte transfer mode, parity should be checked prior to reading the second byte, since a FIFO read clears the error bit. Enable (E) The Enable (E) signal is a high-impedance, TTLcompatible input that enables the bus input/output data buffers, clocks data to and from the SSOA, and moves data through the FIFO registers. This signal is normally the continuous F6800 system q,2 clock, so that incoming data characters are shifted through the FIFO. i Read/write (R/W) The Read/Write line is a high-impedance input that is TTL-compatible and is used to control the direction of data flow through the SSOAs input/output data bus interface. When Read/Write is HIGH (MPU read cycle), SSOA output drivers are turned on if the device is selected and a selected register is read. When it is LOW, the SSOA output drivers are turned off and the MPU writes into a selected register. The Read/Write signal is also used to select read-only or write-only registers within the SSOA. Other status bits that pertain to the receiver section are receiver overrun and data carrier detect (BCD). The overrun status bit is automatically set when a transfer of a character to the receive data FIFO occurs and the first register of the receive data FIFO is full. Overrun causes an interrupt if error interrupt enable (EIE) has been set. The transfer of the overrunning character into the FIFO causes the previous character in the FIFO input register location to be lost. The overrun. status bit is cleared by reading ihe status register (when the overrun condition is present), followed by a receive data FIFO register read. Overrun cannot occur and be cleared without providing an QPportunity to detect the occurrence via the status register. Chip Select (CS) This high-impedance, TTL-compatible input line is used to address the SSOA. The SSOA is selected when CS is LOW. VMA should be used in generating the CS input to insure that false selects will .not occur. Transfers of data to and from the SSOA are then performed under the control of the Enable signal, Read/Write, and Register Select. Register Select (RS) The Register Select Ifne is a high-impedance input that is TTL-compatible. A HIGH level is used to select control registers C2 and C3, the sync code register, and the transmit/receive data registers. A LOW level selects the control 1 and status registers (see Table 1). A positive transition on the 5Ci5 input causes an interrupt if the EIE control bit has been set. The interrupt caused by i5CD is cleared by reading the status register when the OCO status bit is HIGH, followed by a receive data FIFO read. The OCO status bit will subsequently follow the state of the OCO input when it goes LOW. Interrupt Request (IRQ) Interupt Request is a TTL-compatible, open-drain (no internal pull-up), active-LOW output that is used to interrupt the MPU. The Interrupt Request remains LOW until cleared by the MPU. SSOA Interface Signals for MPU The SSDA interfaces to the F6800 MPU with an 8-bit bidirectional data bus, .a Chip Select line, a Register Select line, an Interrupt Request line, a Read/Write line, an Enable line, and a Reset line. These signals, in conjunction with the F6800 VMA output, permit the MPU to have complete control over the SSOA. Reset Input (RESET) The Reset input provides a means of resetting the SSOA from an external source .. In the LOW state, the Reset input causes the following: 1. Receiver reset (Rx Rs) and transmitter reset ITx Rs) bits are set, causing both the receiver and transmitter sections to be held in a reset condition. 2. Peripheral control bits PC1 and PC2 are reset to "0", causing the SM/OTR output to be HIGH. 3. The error interrupt enable (EIE) bit is reset. 4. An internal synchronization mode is selected. 5. The transmitter data register available (TORA) status bit is cleared and inhibited. Bidirectional Data Bus (00-07) The bidirectional data lines (00-07) allow for data transfer between the SSOA and the MPU. The data bus output drivers are 3-state devices that remain in the high-impedance (OFF) state except when the MPU performs an SSOA read operation. 5·227 F6852/F68A52/F68B52 When RESET returns HIGH (the inactive state), the transmitter and receiver sections will remain in the reset state until the receiver reset and transmitter reset bits are cleared via the bus under software control. The control register bit affected by RESET (Rx Rs, Tx Rs, PC1, PC2, EIE, and E/L Sync) cannot be changed when RESET is LOW. Clock Inputs Separate high-impedance, TTL-compatible inputs are provided for clocking of transmitted and received data. Transmit Clock (Tx ClK) The Transmit Clock input is used for the clocking of transmitted data. The transmitter shifts data on the negative transition of the clock. Receive Clock (Rx ClK) The Receive Clock input is used for clocking in received data. The clock and data must be synchronized externally. The receiver samples the data on the positive transition of the clock. Serial Input/Output lines Receive Data (Rx DATA) The Receive Data line is a high-impedance, TTLcompatible input through which data is received in a serial format. Data rates are from a to 600K bps. Transmit Data (Tx DATA) The Transmit Data output line transfers serial data to a modem or other peripheral. Data rates are from a to 600K tips. Peripheral/Modem Control The SSDA includes several functions that permit limited control of a peripheral or modem. The functions included are Clear-to-Send, Sync Match/Data Terminal Ready, Data Carrier Detect, and Transmitter Underflow. Clear-to-Send (CTS) The CTS input provides a real-time inhibit to the transmitter section (the transmit data FIFO is not disturbed). A positive CTS transition resets the transmitter shift register and inhibits the TDRA status bit and its associated interrupt in both the one-synccharacter and two-sync-character modes of operation. TDRA is not affected by the CTS input in the external sync mode. The positive transition of CTs is stored within the SSDA to insure that its occurrence will be acknowledged by the system. The stored CTS information and its associated IRQ lif enabled) are cleared by writing a "1" in the CTS bit in control register 3 or in the transmitter reset bit. The CTS status bit subsequently follows the CTS input when it goes LOW. The CTS input provides character timing for transmitter data when in the external sync mode. Transmission is initiated on the negative transition of the first full positive clock pulse of the Transmit Clock (Tx CLK) after the release of CTS. See Figure 6. Data Carrier Detect (DCD) The DCD input provides a real-time inhibit to the receiver section (the Rx FIFO is not disturbed). A positive DCD transition resets and inhibits the receiver section except for the receive FIFO and the RDRA status bit and its associated IRQ. The positive transition of DCD is stored within the SSDA to insure that its occurrence will be acknowledged by the system. The stored DCD information and its associated IRQ (if enabled) are cleared by reading the status register and then the receive FIFO, or by writing a "1" into the receiver reset bit. The 5C5 status bit subsequently follows the DCD input when it goes LOW. The DCD input provides character synchronization timing for the receiver during the external sync mode of operation. The receiver will be initialized and data will be sampled on the positive transition of the first full Receive Clock cycle after release of DCD. See Figure 7. Sync Match/Data Terminal Ready (SM/DTR) The SM/mR output provides four functions depending on the state of the PC1 and PC2 control bits. When the Sync Match mode is selected (PC1 = "1 ", PC2 = "0"), the output provides a one-bit-wide pulse when a sync code is detected. This pulse occurs for each sync code match even if the receiver has already attained synchronization. The SM output is inhibited when PC2 = "1". The DTR mode (PC1 = "0") provides an output level corresponding to the complement of PC2 (DTR = "0" when PC2 = "1"). See Table 1. Transmitter Underflow (TUF) The Transmitter Underflow output indicates the occurrence of a transfer of a "fill character" to the transmitter shift register when the last location (No.3) in the transmit data FIFO is empty. The Transmitter Underflow output pulse is approximately a Tx CLK HIGH period wide and occurs during the last half of the last bit of the character preceding the underflow. See Figure 4. The Transmitter Underflow output pulse does not occur when the Tx Sync bit is in the reset state. 5-228 F68S2IF68AS2IF68BS2 inhibiting resynchronization. The clear sync bit is set to clear and inhibit receiver synchronization in all modes and is reset to "0" to enable resynchronization. SSDA Registers Seven registers in the SSDA can be accessed by means of the bus. The registers are defined as a read-only or write-only according to the direction of information flow The Register Select input (RS) selects two registers in each state, one being read-only and the other writeonly. The Read/Write input (R/W) defines which of the two selected registers will actually be accessed. Four registers (two read-only and two write-only) can be addressed via the bus at any particular time. These registers and the required addressing are defined in Table 1. Transmitter Interrupt Enable (TIE), C1 Bit 4 TIE enables both the Interrupt Request output (IRQ) and interrupt request status bit to indicate a transmitter service request. When TIE is set and the TDRA status bit is HIGH, the IRQ output will go lOW (the active state) and the IRQ status bit will go HIGH. Receiver Interrupt Enable (RIE), C1 Bit 5 RIE enables both the Interrupt Request output and the interrupt request status bit to indicate service request. When RIE is set and the RDA HIGH, the IRQ output will go lOW (the active and the IRQ status bit will go HIGH. Control Register 1 (C1) Control register 1 is an a-bit, write-only register that can be addressed directly from the data bus. Control register 1 is addressed when RS = "0" and RIW = "0". (IRQ) a receiver status is state) Address Control 1 (AC1) and Address Control 2 (AC2), C1 Bits 6 and 7 AC1 and AC2 select one of the write-only registerscontrol 2, control 3, sync code, or transmit data FIFO - as shown in Table 1, when RS = "1" and R/VV= "0". Receiver Reset (Rx Rs), C1 Bit 0 The receiver reset control bit provides both a reset and inhibit function to the receiver section. When Rx Rs is set, it clears the receiver control logic, sync logic, error logic, Rx Data FIFO control, parity error status bit, and DCD interrupt. The receiver shift register is set to "1s". The Rx Rs bit must be cleared after the occurrence of a lOW level on RESET in order to enable the receiver section of the SSDA. Control Register 2 (C2) Control register 2 is an a-bit, write-only register that can be program.med from the bus when the address control bits in control register 1 (AC1 and AC2) are reset, RS = "1" and R/iiii = "0". Transmitter Reset (Tx Rs), C1 Bit 1 The transmitter reset control bit provides both a reset and inhibit to the transmitter section. When Tx Rs is set, it clears the transmitter control section, transmitter shift register, Tx Data FIFO (which can be reloaded after one E clock pulse), the transmitter underflow status bit, and the CTS interrupt, and inhibits the TDRA status bit (in the one-sync-character and two-sync-character modes). The Tx Rs bit must be cleared after the occurrence of a lOW level on RESET in order to enable the transmitter section of the SSDA. If the Tx FIFO is not preloaded, it must be loaded immediately after the Tx Rs release to prevent a transmitter underflow condition. Peripheral Control 1 (PC1) and Peripheral Control 2 (PC2), C2 Bits 0 and 1 Two control bits, PC1 and PC2, determine the operating characteristics of the Sync Match/DTR output. PC1, when HIGH, selects the Sync Match mode. PC2 provides the inhibit/enable control for the SM/DTR output in the sync match mode. A one-bit-wide pulse is generated at the output when PC2 is "0", and a match occurs between the contents of the sync code register and the incoming data even if sync is inhibited (Clear Sync bit = "1".) The sync match pulse is referenced to the negative edge of Rx ClK pulse causing the match See Figure 3. Strip Synchronization Characters (Strip Sync), C1 Bit 2 If the strip sync bit is set, the SSDA will automatically strip all received characters that match the contents of the sync code register. The characters used for synchronization (one or two characters of sync) are always stripped from the received data stream. The Data Terminal Ready (DTR) mode is selected when PC1 is lOW. When PC2 = "1", the SM/~ output = "0", and vice versa. The operation of PC2 and PC1 is summarized in Table 1. Clear Synchronization (Clear Sync), C1 Bit 3 The clear sync control bit provides the capability of dropping receiver character synchronization and 5-229 F68521F68A521F68B52 1-Byte/2-Byte Transfer (1-Byte/2-Byte), C2 Bit 2 When 1-Byte/2-Byte is set, the TDRA and RDAstatus bits will indicate the availability of their respective data FIFO register for a single -byte data transfer. Alternately, if 1-Byte/2-Byte is reset, the TDRA and RDA status bits 'indicate when two bytes of data can be moved without a second status read. An intervening Enable pulse must occur between data transfers. Word Length Selects (WS1, WS2, WS3), C2 Bits 3, 4, 5 Word length select bits WS1, WS2, and WS3 select word length of seven, eight, or nine bits, including parity, as shown in Table 1. Transmit Sync Code on Underflow (Tx Sync), C2 Bit 6 When Tx Sync is set, the transmitter will automatically send a sync character when data is not available for transmission. If Tx Sync is reset, the transmitter will transmit a mark character (including the parity bit position) on underflow. When the underflow is detected, a pulse approximately a Tx ClK HIGH period wide will occur on the underflow output if the Tx Sync bit is set. Internal parity generation is inhibited during underflow except for sync code fill character transmission in S-bit plus parity word lengths. Error Interrupt Enable (EIE), C2 Bit 7 When EIE is set, the IRQ status bit will go HIGH and the IRQ output will go lOW if: 1. A receiver overrun occurs. The interrupt is cleared by. reading the status register and reading the Rx Data FIFO. 2. DCD input has gone to a "1". The interrupt is cleared by reading the status register and reading the Rx Data FIFO. 3. A parity error exists for the character in the last location (No.3) of the Rx Data FIFO. The interrupt is cleared by readi!!2..the Rx Data FIFO. 4. The CTS input has gone to a "1 ". The interrupt is cleared by writing a "1" in the Clear CTs bit, C3 bit 2, or by Tx Reset. 5. The transmitter has underflowed (in ·the Tic Sync on underflow' mode). The interrupt is cleared by writing a "1" into the clear underflow, C3 bit 3, or Tx Reset. When EIE is a "0", the IRQ status bit and the IRQ output are disabled for the above error conditions. A lOW level on the RESET input resetsEIE to "0". Control Register 3 (C3) Control Register 3 is a 4-bit, write-only register that can be programmmed from the bus when RS = "1" and R/W = "0", and address control bit AC1 = "1" and AC2 = "0". External/Internal Sync Mode Control (Ell Sync), C3BIt 0 When the E/I sync mode bit is HIGH, the SSDA is in the external sync mode and the receiver synchronization logic is disabled. Synchronization can be aChieved by means of the DCD input or by starting Rx ClK at the midpoint of data bit 0 of a character with !5Ci5 lOW. Both the transmitter 'and receiver sections operate as parallel- serial converters in the external sync mode. The clear sync bit in control register 1 acts as a receiver sync inhibit When HIC~H to provide a bus-controllable inhibit. The sync code register can serve as a transmitter fill character register and a receiver match register in this mode. A lOW on the RESET input resets the Ell sync mode bit, placing the SSDA in the internal sync mode. One-Sync-Character/Two-Sync-Character Mode Control (1-Sync/2-Sync), C3 Bit 1 When the 1-Sync/2-Sync bit is set, the SSDA will synchronize on a single match between the received data and the contents of the sync code register. When the 1-Sync/2-Sync bit is reset, two successive sync characters must be received prior to receiver synchronization. If the second sync character is not detected, the bit-by-bit search resumes from the first bit in the second character. See the description of the sync code register for more details. Clear CTS Status (Clear CTS), C3 Bit 2 When a "1" is written into the CTS bit, t!1estored status and interrupt ar.e cleared. Subsequently, the ffi status bit reflects the state of the CT~ut. The Clear CTS control bit does not affect the CTS input nor its inhibit of the transmitter section. The Clear CTS command bit is self-clearing, and writing "0", into this bit is a nonfunctional operation. Clear Transmit Underflow Status (CTUF), C3 Bit 3 When a "1" is written into the CTUF status bit, the CTUF bit and its associated interrupt are reset. The CTUF command bit is se,f-clearing and writing a "0" into this bit is a nonfunctional operation. Sync Code Register The sync code register is an S-bit register for storing the programmable sync code required for received data character synchronization in the one-sync-character and two-sync-character modes. The sync code r~gister also provides for stripping the sync/fill characters from the received data (a programmable option) as well as automatic insertion of fill characters in the transmitted data stream. The sync code register is' not ,!ltilized for receiver character synch ronization in the external sync mode; however, it provides storage of receiver match and transmit fill characters. 5-230 F6852/F68A521F68B52 The sync code register can be loaded when AC2 and AC1 are a "1" and "0", respectively, and R/W = "0" and RS = "1". The sync code register may be changed after the detection of a match with the received data (the first sync code having been detected) to synchronize with a double-word sync pattern. (This sync code change must occur prior to the completion of the second character.) The sync match (SM) output can be used to interrupt the MPU system to indicate that the first eight bits have matched. The service routine would then change the sync match register to the second half of the pattern. Alternately, the one-sync-character mode can be used for sync codes for 16 or more bits by using software to check the second and subsequent bytes after reading them from the FIFO. The detection of the sync code can be programmed to appear on the Sync Match/DTR output by writing a "1" in PC1 (C2 bit 0) and a "0" in PC2 (C2 bit 1). The Sync Match output will go HIGH for one bit time beginning at the character interface between the- sync code and the next character (see Figure 3). Parlly for Sync Characler Transmiller The transmitter does not generate parity for the sync character except in the 9-bit mode. 9-bit (8-bit 8-bit (7-bit 7-bit (6-bit + parity) ... 8-bit sync character + parity + parity) ... 8-bit sync character (no parity) + parity) ... 8-bit sync character (no parity) Receiver AI Synchronlzallon The receiver automatically strips the sync character(s) (two sync characters if 2-sync mode is selected) that is used to establish synchronization. Parity is not checked for these sync characters. Aller Synchronizallcm Is ESlablished When strip-sync bit is selected, the sync characters (fill characters) are stripped and parity is not checked for the stripped sync (fill) characters. When strip-sync bit is not selected (LOW), the sync character is assumed to be normal data and it is transferred into FIFO after parity checking. (When non-parity format is selected parity is not checked.) . ' Sirip Sync (C1 BII 2) WSO-WS2 (Dala Formal) (C2 BII 3-5) 1 X No transfer of sync code. No parity check of sync code. 0 With Parity 'Transfer data and sync codes. Pa'rity check. 0 Without Parity 'Transfer data and sync codes. No parity check. ·Subsequent to synchronization. It is necessary to pay attention to the selected sync character in the following cases: 1. Data format is (6 + parity), (7 + parity). 2. Strip sync is not selected (LOW). 3. After synchronization when sync code is used as a fill character. The transmitter sends the sync character without parity, but the receiver checks the parity as if it is normal data. Therefore, the sync character should be chosen to match the parity check selected for the receiver in this special case. Receive Data First-In First-Out Register (Rx Data FIFO) The receive data FIFO register consists of three 8-bit registers that are used for buffer storage of received data. Each 8-bit register has an internal status bit that monitors its full or empty condition. Data is always transferred from a full register to an adjacent empty register. The transfer from register to register occurs on E pulses. The RDA status bit will be HIGH when data is available in the last location of the Rx Data FIFO. In an overrun condition, the overrunning character will be transferred into the full first stage of the FIFO register and will cause the loss of that ,data character. Successive overruns continue to overwrite the first register of the FIFO. This destruction of data is indicated by means of the overrun status bit. The overrun bit will be set when the overrun occurs and remains set until the status register is read, followed by a read of the Rx Data FIFO. Unused data bits for short word lengths (including the parity bit) will appear as "Os" on the data bus when Rx Data FIFO is read. 5·231 F6852/F68A521F68B52 Transmit Data First-In First-Out Register (Tx Data FIFO) The transmit data FIFO register .consists of three 8-bit registers that are used for buffer storage of data to be transmitted. Each 8-bit register has an internal status bit that monitors its full or empty condition. Data is always transferred from a full register to an adjacent empty reg ister. The transfer is clocked by E pu Ises. The TDRA status bit will be HIGH if the Tx Data FIFO is available for data. Unused data bits for short word lengths will be handled as "don't cares". The parity bit is not transferred over the data bus, since the SSDA generates parity at transmission. When an underflow occurs, the underflow character will be either the contents of the sync code register or an all-"1s" character. The underflow will be stored in the status register until cleared and will appear on the underflow output as a pulse approximately a Tx ClK HIGH period wide. Status Register The status register is an 8-bit, read-only register that provides the real-time status of the SSDA and the associated serial data channel. Reading the status register is a non-destructive process. The method of clearing status bits depends upon the function each bit represents and is discussed for each bit in the register. Receiver Data Available (RDA), S Bit 0 The receiver data available status bit indicates when receiver data can be read from the Rx Data FI FO. The receiver data being present in the last register (No.3) of the FIFO causes RDA to be HIGH for the 1-byte transfer mode. The RDA bit being HIGH indicates that the last two registers (No.2 and No.3) are full when in the 2-byte transfer mode. The second character can be read without a second status read (to determine that the character is available). An E pulse must occur between reads of the Rx Data FIFO to allow the FIFO to shift. Status must be read on a word-by-word basis if receiver data error checking is important. The RDA status bit is reset automatically when data is not available. Transmitter Data Register Available (TDRA).S Bit 1 The TDRA status bit indicates that oata can be loaded into the Tx Data FIFO register. The first register (No.1) of the Tx Data FIFO being empty will be indicated by a HIGH level of the TDRA status bit in the 1-byte transfer mode. The first two registers (No.1 and No.2) must be empty for TDRA to be HIGH when in the 2-byte transfer mode. The Tx Data FIFO can be loaded with two bytes without an intervening status read; however, one E pulse must occur between loads. TDRA is inhibited by the Tx Reset or RESET. When Tx Reset is set, the Tx Data FIFO is cleared and then released on the next E clock pulse. The Tx Data FIFO can then be loaded with up to three characters of data, even though TDRA is inhibited. This feature allows preloading data prior to the release of Tx Reset. A HIGH level on the CTS input inhibits the TDRA status bit in either sync mode of operation (onesync-character or two-sync-characterl. CTS does not affect TDRA in the external sync mode. This enables the SSDA to operate under the control of the CTS input, with TDRA indicating the status of the Tx Data FIFO. The CTS input does not clear the Tx Data FIFO in any operating mode. Data Carrier Detect (DCD). S Bit 2 A positive transition on the DCD input is stored in the SSDA until cleared by reading both status and Rx Data FIFO. A "1" written into Rx Rs also clears the stored DCD status. The DCD status bit, when set, indicates that the DCD input has gone HIGH. The reading of both status and receive data FIFO allows bit 2 of subsequent status reads to indicate the state of the DCD input until the next positive transition. Clear-to-Send (CTS). S Bit 3 A positive transition on the CTS input is stored in the SSDA until cleared by writing a "1" into the Clear ITs control bit or the Tx Rs bit. The CTS status bit, when set, indicates that the CTS input has gone HIGH. The Clear CTS commanO (a "1" into C3 bit 2) allows bit 3 of subsequent status reads to inOicate the state of the CTS input until the next positive transition. Transmitter Underflow (TUF). S Bit 4 When data is not available for the transmitter, an underflow occurs and is so indicated in the status register (in the Tx Sync on underflow mode). The underflow status bit is cleared by writing a "1" into the clear underflow (CTUF) control bit or the Tx Rs bit. TUF indicates that a sync character will be transmitted as the next character. A TUF is indicated on the output only when the contents of the sync code register are to be transferred (transmit sync code on underflow = "1"). Receiver Overrun (Rx Ovrn). S Bit 5 Overrun indicates data has been received when the Rx Data FIFO is full, resulting in Oata loss. The Rx Ovrn status bit is set when overrun occurs. The Rx Ovrn status bit is cleared by reading status followed by reading the Rx Data FIFO or by setting the Rx Rs control bit. 5·232 F68521F68A521F68B52 Receiver Parity Error (PE). S Bit 6 The parity error status bit indicates that parity for the character in the last register of the Rx Data FIFO did not ag ree with selected parity. The parity error is cleared when the character to which it pertains is read from the Rx Data FIFO or when Rx Rs occurs. The OeD input does not clear the parity error or Rx Data FI FO status bits. Table 1 Register Status IS) Interrupt Request (IRQ). S Bit 7 The interrupt request status bit indicates when the IRQ output is in the active state (IRQ output = "0"). The IRQ status bit is subject to the same interrupt enables (RIE, TIE, and EIEI as the IRQ output. The IRQ status bit simplifies status inquiries for polling systems by providing single-bit indication of service requests. SSDA Programming Model Control Inputs Address Control Register Content RS R/W AC2 AC1 Bit 7 Bit 6 Bit 5 Bit 4 0 1 X Interrupt Request IIRQ) Receiver Parity Receiver Overrun IRx Ovrn) Transmitter Clear-toUnderflow Send ITUF) (CTs) Data Carrier Transmitter Detect Data (CGo) Register Available (TDRA) Receiver Data Available (RDA) Strip Sync Characters (Stri p Sync) Transmitter Reset (Tx Rs) Receiver Reset (Rx Rs) X Er~or Bit 3 (PE) Control 1 Cl Bit 2 Bit 1 Bit 0 0 0 X X Address Control 2 IAC2) Address Control 1 IAC1) Receiver Interrupt Enable IRIE) Transmitter Clear Interrupt Sync Enable ITIE) Receive 1 Data FIFO 1 X X D7 Os Os 04 D:3 02 01 Do Control 2 (C2) 1 0 0 0 Error Interrupt Enable IEIE) Transmit Sync Code on Underflow ITx Sync) Word Length Select 3 IWS3) Word Length Select 2 IWS2) Word Length Select 1 IWS1) l-Byte/ 2-Byte Transfer Il-Byte/ 2-Byte) Peripheral Control 2 (PC2) Peripheral Control 1 (PC1) Control 3 (C3) 1 0 0 1 Not Used Not Used Not Used Not Used Clear Clear CTS Transmitter Status Underflow IClear CTS) Status ICTUF) One-SyncCharacter/ Two-SyncCharacter Mode Control Il-Sync/ 2-Sync) External! Internal Sync Mode Control (Ell Sync Sync Code 1 0 1 0 D7 Os Os 04 D:3 02 01 Do 1 Transmit Data FIFO 0 1 1 D7 Os Os 04 D:3 D2 01 Do x = Don't Care 5·233 F68521F68A52/F68B52 Status Register IRQ Bit 7 RDA The IRQ flag is cleared when the source of the IRQ is cleared. The source is determined by the enables in the control registers: TIE, RIE, EIE. Indicate the SSDA status at a point in time, and can be reset as follows: Bit 6 Read Rx Data FIFO, or a "1" into Rx Rs (C1 bit 0). Bit 5 Read status and then Rx Data FIFO, or a "1" into Rx Rs (C1 bit 0). A "1" into CTUF (C3 bit 3) or into Tx Rs (C1 bit 1) Bit 4 (C3 bit 2) or a "1" into Tx Rs (C1 bit 1). A "1" into Bit 3 Read status and then Rx Data FIFO or a "1" into Rx Rs Bit 2 (C1 bit 0). Bit 1 Write into Tx Data FIFO. Bit 0 Read Rx Data FIFO. AC2, AC1 RIE TIE Clear Sync Strip Sync Bits 7, 6 Bit 5 Bit 4 Bit 3 Bit 2 Tx Rs Rx Rs Bit 1 Bit 0 EIE Bit 7 Tx Sync Bit 6 WS3, 2,1 Bits 5-3 Bits 6-0 PE Rx Ovrn TUF CTS DCD TDRA m Control Register 1 Control Register 2 Used to access other registers, as shown above. When "1", enables interrupt on RDA (S bit 0). When "1", enables interrupt on TDRA (S bit 1). When "1", clears receiver character synchronization When "1", strips all sync codes from the received data stream. When "1", resets and inhibits the transmitter section. When "1", resets and inhibits the receiver section. When "1", enables the PE, Rx Ovrn, TUF, ffi, and DCD interrupt flags (S bits 6 through 2). When "1", allows sync code content to be transferred on underflow, and enables the TUF status bit and output. When "0", an all-mark character is transmitted on underflow. Word Length Select 5-234 Bit 5 WS3 Bit 4 WS2 Bit 3 WS1 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 Word Length 6 6 7 8 7 7 8 8 Bits Bits Bits Bits Bits Bits Bits Bits + + Even Parity Odd Parity + + + + Even Parity Odd Parity Even Parity Odd Parity 'F68521F68A52/F68B52 1-Byte/2-Byte Bit 2 PC2, PC1 Bits 1-0 When "1", enables the TDRA and RDA bits to indicate when a 1-byte transfer can occur; when "0", the TDRA and RDA bits indicate when a 2-byte transfer can occur. SM/DTR Output Control Bit 1 PC2 Bit 0 PC1 SM/OTR Output at Pin 5 0 0 0 1 1 Pulse ~ , 1-Bit Wide, on SM 1 1 0 1 0 SM Inhibited, 0 Control Register 3 CTUF Clear CTS 1-Sync/2-Sync Bit 3 Bit 2 Bit 1 Ell Sync Bit 0 When "1", clears TUF (S bit 4)and IRQ, if enabled. When "1", clears CTS (S bit 3)and IRQ, if enabled. When "1", selects the one-sync-character mode; when "0", selects the two-sync-character mode. When "1", selects the external sync mode; when "0", selects the internal sync mode. Notes When the SSDA is used in applications requiring the MSB of data to be received and transmitted first. the data bus inputs to the SSDA may be reversed lDo to 07, etC.l. Caution must be used when this is done, since the bit positions in this table will be reversed, and the parity should not be selected. Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature Range F6852P, S, F68A52P, S, F68B52P,S F6852CP, CS, F68A52CP, CS F6852DLQB F6852DMQB Storage Temperature Range Thermal Resistance Plastic Package Ceramic Package Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -0.3 V, +7.0 V -0.3 V, +7.0 V O°C, -40°C, -55° C, -55°C, -55°C, +70°C +85°C +85° C +125°C +150°C 120°C/W 60°C/W 5-235 • F68521F68A521F68B52 DC Characteristics Vee = 5.0 V ± 5%, VSS = 0, TA =0 to 70·C unless otherwise noted Signal Min Typ Max Unit Test Conditions Symbol Characteristic VIH Input HIGH Voltage VIL Input lOW Voltage 0.8 V liN Input leakage Current Tx ClK, Rx ClK, Rx DATA, Enable, RESET, RS, R/W, CS, OeD, CTS 1.0 2.5 jJA VIN ITSI 3-State (OFF State) Input Current 00-07 2.0 10 jJA VIN = 0.4 to 2.4 V, Vee = 5.25 V VOH Output HIGH Voltage 00-07 2.4 V ILoad = -205 jJA, Enable Pulse Width <25 jJs ILoad = -100 jJA, Enable Pulse Width <25 jJs Tx DATA, DTR, TUF 2.4 0.4 V ILoad = 1.6 mA, Enable Pulse Width <25 jJs 1.0 10 jJA VOH 300 525 mW VOL Output lOW Voltage ILOH Output leakage Current (OFF State) Po Power Dissipation CIN Input Capacitance COUT Output Capacitance 2.0 (IRQ) V pF 00-07 All Other Inputs 12.5 7.5 Tx DATA, SM/DTR, TUF IRQ 10 5-236 = 2.4 V = 0, TA = 25·C, = 1.0 MHz VIN = 0, TA = 25·C, = 1.0 MHz f 5.0 5.25 V VIN f pF = 0 to F68521F68A521F68B52 AC Characteristics Vcc = 5.0 V ± 5%, Vss = 0, TA = O·C to +70·C unless otherwise noted. F6852 F68A52 F68B52 Symbol Characteristic Min PWCL Minimum Clock Pulse Width, LOW (Figure 1) 700 400 280 ns PWCH Minimum Clock Pulse Width, HIGH (Figure 2) 700 400 280 ns fc Clock Frequency tROSU Receive Data Set-up Time (Figures 3, 7) 350 200 160 ns tROH Receive Data Hold Time (Figure 3) 350 200 160 ns tSM Sync Match Delay Time (Figure 3) 1.0 0.666 0.500 p.s troD Clock-te-Data Delay for Transmitter (Figure 4) 1.0 0.666 0.500 p.s truF Transmitter Underflow (Figure 4, 6) 1.0 0.666 0.500 p.s torR DTR Delay Time (Figure 5) 1.0 0.666 0.500 p.s tlR Interrupt Request Release Time (Figure 5) 1.2 0.800 0.600 p.s tRes RESET Minimum Pulse Width tcrs CTS Set-up Time (Figure 6) 200 toco DCD Set-up Time (Figure 7) 500 tr, tf Input Rise and Fall Times (except Enable) Max Min 600 1.0 Max Min 1000 0.666 Max 1500 Unit kHz 0.500 p.s 150 120 ns 350 250 1.0' 1.0' '1.01'8 or 10% of the pulse width. whichever is smaller. 5-237 Test Condition ns 1.0' p.s 0.8 V to 2.0 V F68521F68A521F68B52 Bus Timing Characteristics Read (Figures 8 and 10) F6852 Symbol Characteristic Min F68A52 Max Min 25 0.28 F68B52 Max Min 25 0.22 Max Unit 25 p's tcycE Enable Cycle Time 1.0 PWEH Enable Pulse Width, HIGH 0.45 PWEL Enable Pulse Wi.dth, LOW 0.43 0.28 0.21 p's tAs Set-up Time, Address and R/W valid to Enable positive transition 160 140 70 ns tOOR Data Delay Time 0.666 320 0.5 180 220 tH Data Hold Time 10 10 10 tAH Address Hold Time 10 10 10 tEr, tEl Rise and Fall Time for Enable input 25 25 p's ns ns ns 25 ns Write (Figures 9 and 10) tcycE Enable Cycle Time 1.0 0.666 PWEH Enable Pulse Width, HIGH 0.45 Enab"le Pulse Width, LOW 0.43 0.28 0.21 p's tAS Set-up Time, Address and R/W valid to Enable positive transition 160 140 70 ns tosw Data Set-up Time 195 80 60 ns tH Data Hold Time 10 10 10 ns tAH Address Hold Time 10 tEr, tEl Rise and Fall Time for Enable input Fig. 1 Clock Pulse Width, Low-State -:OWCL- Tx ClK OR Rx ClK 0.8 V 0.22 10 25 10 25 25 Fig. 2 25 p's PWEL 25 0.28 0.5 ns 25 Clock Pulse Width, High-State TXClK~'OV OR Rx ClK -,-PWCH p's ns F6852/F68A52/F68B52 Fig. 3 Receive Data Set-up and Hold Times and Sync Match Delay Time Dn-l DO 0" Rx elK Rx DA'rA SYNCMATCH _ _ ~~~'1 \1 ... _ Rx ClK PERIOO-----j~~ n = Number of bits in character ~ = Don't care Fig. 4 Transmit Data Output Delay and Transmitter Underflow Delay Time Fig. 5 Data Terminal Ready and Interrupt Request Release Times ___2.0Vn ..JJ ~O.8;..V:..-_ _ _ __ Tx ClK _ tTDO--. Tx DATA _ _ _- ' " "...... _+-___0_"_ _ _ _.1 irni - TUF - -_ _ _ _ _ _ _ _ __ = Number )( 2.4 V . .V-------. 4 _ _ _ _~--J ~O.4 IIR 11Uf n -IOTR )~2"".4""V'----- iRQ---------....I of bits in character 5·239 F6852/F68A521F68B52 Fig. 6 Clear-to-Send Set-up Time Fig. 9 Bus Write Timing Characteristics (Write information into SSDA) CTS~ ~l"---------------E TxCLK ---~ RS, C$, RM DATA BUS Tx DATA Fig. 10 Fig. 7 Bus Timing Test Loads Data Carrier Detect Set-up Time Load A (Do-D7, DTii, Tx DATA, TUF) 5.0 V RL=2.Sk TEST POINT -t-~-Kt-.. Rx elK C 1N914 DR EQUIVALENT )(2.0 V Rx DATA Fig. 8 -------J'1G.8V Do C = 130 pF for 00-07 = 30 pF for OTR, Tx DATA, and TUF A = 11.7 kll for 00-07 = 24 kll for i'5'I'R. Tx DATA, and TUF Bus Read Timing Characteristics (Read Information from SSDA) Load B (iRa Only) 5.0 V ~3 Rx, C$, RIW TEST POINT DATA BUS 5·240 --1J k 100 pF F6852/F68A52/F68B52 Ordering Information Speed Order Code Temperature Range 1.0 MHz F6852 P,S F6852 ep,es F6852DLQ8 F6852DMQ8 -40° e to +85° e -55° e to +85° e -55°e to +125°e 1.5 MHz F68A52 P,S F68A52 ep,es ooe to 70 0 e -40° e to +85° e 2.0 MHz F68852 P,S ooe to 70 0 e P :;:: Plastic package; ooe to 70 0 e S = Ceramic package 5-241 F68521F68A521F68B52 5-242 F6854/F68A54/F68B54 Advanced Data Link Controller CADLC) FAIRCHILD A Schlumberger Company Microprocessor Product Description The F6854/F68A54/F68B54 Advanced Data link Controllers (ADlC) perform the complex MPU/data communication link function for the Advanced Data Communication Control Procedure (ADCCP). High-level Data Link Control (HDlC) and Synchronous Data Link Control (SDlC) standards. The ADlC provides key interface requirements with improved software efficiency. The ADlC is designed to provide the data communications interface for both primary and secondary stations in stand-alone. polling and loop configurations. Logic Symbol • F6800 Compatible • Protocol Features • Automatic Flag Detection and Synchronization • Zero Insertion and Deletion • Automatic Address Field Extension (Optional) • Extended Control Field (Optional) • Auto Extendable logic Control Field (Optional) • Variable Word Length Information Field 5-, 6-, 7-, or 8-Bit • Automatic Frame Check Sequence Generation and Check • Abort Detection and Transmission • Idle Detection and Transmission • Modem/Data Channel Control Lines • Loop Mode • Single 5 V Power Supply • Enhanced Speed Options F6854-1.0 MHz F68A54-1.5 MHz F68B54-2.0 MHz VSS~Pin Rx Data F6854 RESET LOC/OTR vCC~ Pin 14 1 Connection Diagram 28-Pin DIP VSS CTS RTS oco LOC/DTR RxData RxC FLAG DET TxC TOSR ROSR TxOats IRQ 00 RESET D-! CS 02 RBo 03 04 RSj 05 06 E Pin Names RxData RxC TxC RESET CS RSo. RS1 R/W E DCD CTS Do - 07 RTS TxData iRQ RDSR TDSR FLAG DET lOC/DTR Vss Vee TOSR ROSR 07 Receiver Serial Data Input Receiver Data Timing Clock Input Transmitter Data Timing Clock Input Chip Master Reset Input Chip Select Input Register Addressing Select Inputs Read/Write Input System Control Clock Input Data Carrier Detect Input Clear-to-Send Input Bidirectional Data 1/0 Lines Request-to-Send Output Transmitter Serial Data Output Interrupt Request Output Receiver Data Service Request Output Transmitter Data Service Request Output Flag Detect Output loop On-line Control/Data Terminal Ready Output Ground +5 V Power Supply (Top View) 5·243 • F6854/F68A54/F68854 Block Diagram es RiVi CONTROL CONTROL REGISTER 3 REGISTER 2 • ". CONTROL REGISTER 4 RSl I- CHIP SELECT 1 • ". RSo i i i i RECEIVER I DATA I FIFO REGISTER 1 (3 BYTES) ~ DATA REGlSTER 1 ('BYTES) I I I- FIFO 2 L • /'- " l STATUS REGISTER 1 TRANSMIT CONTROL J L,. - REGISTER 1 FCS CHECK L !-- Fes GENERATOR =r tt I • iRa FLAG/ABORT GENERATOR t ZERO INSERTION TRANSMITTER CONTROL y ~. I I I . I TxDa11 TxC CTS LOC/DTR RTS TOS" "DSR Operation Transmitter Operation The Transmitter Data FIFO Register (Tx FIFO) cannot be pre-loaded when the transmitter section is in a reset state. After the reset release, the Flag/Mark Idle Select control bit (F/M Idle) selects either the mark idle state (inactive idle) or the flag time fill (active idle) state. This active or inactive mark idle state will continue until data is loaded into the Tx FIFO. Initialization During a power-on sequence, the ADLC is reset via the Reset (RESET) input and internally latched in a reset condition to prevent erroneous output transitions. The four Control Registers must be programmed prior to the release of the reset condition. The release of the reset condition is performed via software by writing a LOW into the Receiver Reset (RxRS) control bit and/or Transmitter Reset (TxRS) control bit. The release of the reset condition will be done after RESET has gone HIGH. The availability of the Tx FIFO is indicated by the Transmitter Data Available/Frame Complete (TDRA/FC) status bit under the control of the 2-Byte/1-Byte Transfer (2/1-Byte) control bit. TDRA status is inhibited by the TxRS control bit or Clear-to-Send (CTS) input being HIGH. When the 1-byte mode is selected, one byte of the Tx FIFO is available for data transfer when TDRA/FC goes At any time during operation, writing a HIGH into the RxRS control bit or TxRS control bit causes the reset condition of the receiver or transmitter section. 5·244 F6854/F68A54/F68B54 HIGH. When the 2-byte mode is selected, two successive bytes can be transferred when TDRA/FC goes HIGH. The frame is termi nated by one of two methods. The most efficient way to terminate the frame from a software standpoint is to write the last data character into the Tx FI FO frame-terminate address (RS" RSo " HH) rather than the Tx FIFO frame-continue address (RS" RSo" HL). An alternate method is to follow the last write of data in the Tx FIFO frame-continue address with the setting of the Transmit Last Data (Tx Last) control bit. Either method causes the last character to be transmitted and the Frame Check Sequence (FCS) field to be appended automatically along with a closing flag. Data for a new frame can be loaded into the Tx FIFO immediately after the old frame data if TDRA/FC is HIGH. The closing flag can serve as the opening flag of the next frame, or separate opening and closing flags may be transmitted. If a new frame is not ready to be transmitted, the ADLC will automatically trans- • mit the active (flag) or inactive (mark) idle condition. The first byte (address field) should be written into the Tx FI FO at the frame-continue address. Then the transmission of a frame automatically starts. If the Transmitter is in a mark idle state, the transfer of an address causes an opening flag within two or three transmitter clock cycles. If the Transmitter has been in a time fill state, the current time fill flag being transmitted is assumed as an opening flag and the address field will follow it. A frame continues as long as data is written into the Tx FI FO at the frame-continue address. The ADLC internally keeps track of the field sequence in the frame. The frame format is described in the Frame Format section. ADLC Transmitter Slale Diagram (Cibi refers to Control Register bit) FLAG IDl.E (C2b2 '-- H) OR 2F INTERFRAME (C4bO' H) C3b1 EXTEND CONTROl. (1 BYTE ONLY) Data Being Transmitted: LC::: F = flag A = address C = (link) control FCS;;: A8T::: I::: logical control (optional) information frame check sequence abort 5-245 F6854/F68A54/F68B54 register (Register 3) for the 1-byte transfer mode. The 2-byte transfer mode causes the RDA status bit to indicate data is available when the last two Rx FIFO register locations (Registers 2 and 3) are full. If the data character present in the Rx FIFO is an address octet, Status Register 1 will exhibit an address present status condition. Data being available in the Rx FIFO causes an interrupt to be initiated (assuming the Receiver Interrupt Enable (RIE) control bit is enabled, RIE="1"). The MPU will read the ADLC status registers as a result of the interrupt or in its turn in a polling sequence. The Receiver Data Available (RDA) or Address Present (AP) status bits will indicate that receiver data is available and the MPU should subsequently read the Rx FIFO. The Interrupt Request (IRQ) and RDA status bits will then be reset automatically. If more than one character is received and is resident in the Rx FIFO, subsequent E clocks will cause the Rx FIFO to update and the RDA and IRQ status bits will again be set. In the 2-byte transfer mode both data bytes may be read on consecutive E cycles. The AP status bit provides for 1-byte transfers only. If the Tx FIFO becomes empty at any time during frame transmission (the Tx FIFO has no data to transfer into the transmitter shift register during transmission of the last half of the next-to-Iast bit of a word), an underrun will occur and the Transmitter automatically terminates the frame by transmitting an abort. The underrun state is indicated by the Transmitter Underrun (TxU.) status bit. Any time the Transmit Abort (ABT) control bit is set, the Transmitter immediately aborts the frame (transmits at least eight consecutive 1s) and clears the Tx FIFO. If the Abort Extend (ABTEX) control bit is set at the time, an idle (at least 16 consecutive 1s) is transmitted, An abort or idle in an out-of-frame condition can be useful to gain eight or 16 bits of delay. (For an example see Programming Considerations.) The CTS input and Request-to-Send (RTS) output are provided for a modem or other hardware interface. The TDRA/FC status bit (when selected to be frame-complete status) can cause an interrupt upon frame completion (i.e., a flag or abort completion). The sequence of each field in the received frame is automatically handled by the ADLC. The frame format is described in the Frame Format section. Details regarding the pin functions, Tx FIFO operation, and control and stat-us registers are described in their respective sections. When a flag is detected, the Receiver establishes frame synchronization to the flag timing. If a series of flags. is received, the Receiver resynchronizes to each flag. When a closing flag is received, the frame is terminated. The 16 bits preceding the closing flag are regarded as the FCS and are not transferred to the MPU. Whatever data is present in the most significant byte portion of the receiver buffer register is right justified and transferred to the Rx FIFO. The frame boundary pointer, explained in the Rx FIFO Register section, is set simultaneously in the Rx FIFO. The frame boundary pointer sets the Frame Valid (FV) status bit (when the frame was completed with no error) or the Frame Check Sequence/Invalid Frame Error (ERR) status bit (when the frame was completed with error) when the last byte of the frame appears at the last location of the Rx FIFO. As long as the FV or ERR status bit is set, the data transfer from the second location of the Rx FIFO to the last location of the Rx FIFO is inhibited. If the frame is terminated before the internal buffer time expires (the frame data is less than 25 bits after an opening flag), the frame is simply ignored. Noise on RxData during time fill can cause this kind of invalid frame. Any time the Rx Frame Discontinue (DISCONTINUE) control bit is set, the ADLC discards the current frame data in the ADLC without dropping flag synchronization. This feature can be used to ignore a frame which is addressed to another station. Once synchronization has been achieved and the internal buffer time (24 bit-times) expires, data will automatically transfer to the Receiver Data FIFO Register (RxFIFO). The Rx FIFO is clocked by System Control Clock (E) input to cause received data to move through the Rx FIFO to the last empty register location. The Receiver Data Available (RDA) status bit indicates when data is present in the last The reception of an abort or idle is explained in the Frame Format section. The details regarding the pin functions, Rx FI FO operation, and control and status registers are described in their respective sections. Receiver Operation Data and a pre-synchronized clock are provided to the ADLC receiver section by means of the Receiver Serial Data (RxData) and Receiver Data Timing Clock (RxC) inputs. The data is a continuous stream of binary bits with the characteristic that a maximum of five 1s can occur in succession unless abort, flag, or idling conditions occur. The Receiver continuously (on a bit-by-bit basis) searches for flags and aborts. 5·246 F6854/F68A54/F68B54 ADLC Receiver State Diagram • 'Out-af-frame Abort (No IRQ) Loop Mode Operation In the loop mode the ADLC not only transmits and receives data frames in the manner previously described, but also has additional features for gaining and relinquishing loop control. In Figure 1, a configuration is shown which depicts loop mode operation. The system configuration shows a primary station and several secondary stations. The loop is always under control of the primary station. When the primary wants to receive data, it transmits a poll sequence and allows frame transmission to secondary stations on the loop. Each secondary is in series and adds one bit of delay to the loop. Secondary A in the figure receives data from the primary via the RxData input, delays the data one bit, and transmits it to secondary B via the Transmitter Serial Data (TxData) output. Secondaries B, C, and 0 operate in a similar manner. Therefore, data passes through each secondary and is received back by the primary controller. Fig. 1 Typical Loop Configuration SECONDARY STATIONS (A,B,C,D) OPERATE IN LOOP MODE 5·247 F6854/F68A54/F68B54 on RxData. The ADLC can recognize the necessary sequences in the data stream to automatically go on/off the loop and to insert its own station data. This procedure is summarized in Table 1. Certain protocol rules must be followed that establish the manner by which the secondary station places itself on-loop (connects TxData to the loop). goes active on the loop (starts transmitting data on the loop). and goes off the loop (disconnects TxData). Otherwise, loop data to other stations down-loop would be interrupted. The data stream always flows the same way; the order in which secondary terminals are serviced is determined by the hardware configuration. The primary controller times the delay through the loop. Should it exceed n + 1 bit-times, where n is the number of secondary terminals on the loop, it will indicate a loop failure. Control is transferred to a secondary by transmitting a go-ahead signal following the closing flag of a polling frame (request for a response from the secondary) from the primary station. The go-ahead from the primary is a 0 and seven 1s followed by mark idling. The primary can abort its response request by interrupting its idle with flags. The secondary should immediately stop transmission and return control to the primary. When the secondary completes its frame, a closing flag is transmitted followed by all 1s. The primary detects the final 01111111 (go-ahead to the primary) and resumes control. Note that if a down-loop secondary (e.g., station D) needs to insert information following an up-loop station (e.g., station A), the go-ahead to station D is the last 0 of the closing flag from station A followed by 1s. 1. Go On-loop - When the ADLC powers up, the terminal station will be off line. The first task is to become an active terminal on the loop. The ADLC must be connected to a loop link via an external switch as shown in Figure 2. After a hardware reset, the ADLC Loop On-line Control/Data Terminal Ready (LOC/DTR) output will be in the HIGH state and the up-loop receive data repeated through gate A to the down-loop stations. Any up-loop transmission will be received by the ADLC. The Loop/Non-Loop Mode (LOOP) control bit must be set to place the ADLC in the loop mode. The ADLC now monitors its RxData input for a string of seven consecutive 1s which will allow a station to go on line. The loop operation may be monitored by use of the Loop Status (LOOP) status bit. After power-up and reset, this bit is a LOW. When seven consecutive 1s are received by the ADLC, the LOC/DTR output will go to a LOW level, disabling gate A (refer to Figure 2), enabling gate B and connecting the ADLC TxData output to the down-loop stations. The up-loop data is now repeated to the down-loop stations via the ADLC. A 1-bit delay is inserted in the data (in NRZI mode, there will be a 2-bit delay) as it circulates through the ADLC. The ADLC is now on-line and the LOOP status bit will be at a HIGH. The ADLC in the primary station should operate in a non-loop, full-duplex mode. The ADLC in the secondaries should operate in a loop mode, monitoring up-loop data Table 1 Summary of Loop Mode Operation Receiver (Rx) Section Transmitter (Tx) Section LOOP Status Bit Off-loop Rx section receives data from loop and searches for seven 1s (when the LOC/DTR control bit set) to go on-loop. Inactive 1. NRZ Mode TxData output is maintained HIGH (mark). 2. NRZI Mode TxData output reflects the RxData input state delayed by one bit-time. (Not normally connected to loop.) The NRZI data is internally decoded to provide error-free transitions to on-loop mode. L On-loop 1. When GAP/TST control bit is set, Rx section searches for 01111111 pattern (the EOP or go-ahead) to become the active terminal on the loop. 2. When the LOC/DTR control bit is reset, Rx section searches for eight 1s to go off-loop. Inactive 1. NRZ Mode TxData output reflects RxData input state delayed one bit-time. 2. NRZI Mode TxData output reflects RxData input state delayed two bit-times. H Active Rx section searches for flag (an interrupt from the loop controller) at RxData input. Received flag causes FLAG DET output to go LOW. IRQ is generated if the RIE and FDSE control bits are set. TxData originates within ADLC until GAP/TST control bit is reset and a flag or abort is completed, then returns to on-loop state. L State 5·248 F6854/F68A54/F68B54 Fig. 2 External Loop Logic ADLC 1-------"1 I RxData TxDala ~i;===~~)--+-j7'l I---''-!---.-Ir-, - ;: 9 'a .. II Status Register 1 RS1, RSo = LH Status Register 2 RS1, RSo Receive Data Available (RDA) 1· Status Register 2 Frame Valid (FV) Read Request (S2RO) Bit 1 Bit 2 Address Present (AP) RS1, RSo = HH Unused BitO 2 Loop Status (LOOP) Inactive Idle Received (Rxldle) 3 Flag Detected (FD) Abort Received (Rx ABT) Bit3 4 Clear-to-Send (CTS) Frame Check Sequence/Invalid Frame Error (ERR) Bit4 5 Transmitter Underrun (TxU) Data Carrier Detect (DCD) Bit 5 6 Transmitter Data Register Available/ Frame Complete (TDRAlFC) Receiver Overrun (OVRN) Bit 6 7 Interrupt Request (IRO) Received Data Available (RDA) Bit 7 II: = HL Receiver Data FIFO Register 0 .! II: = LL Same as RS,. RSo = HL Transmitter Data FIFO Register Control Register 1 Bit No. Control Register 2 (C1bO = L) Control Register 3 (C1bO = H) Frame Continue Frame Terminllte (C1bO = L) Controt Register 4 (C1bO = H) 0 Address Control (AC) Prioritized Status Enable (PSE) Logic Control Field Select (LCF) BitO BitO Double Flag/Single Flag Interframe Control (UFF"/"F") 1 Receiver Interrupt Enable (RIE) 2-Byte/1-Byte' Transfer (2/1-Byte) Extended Control Field Select (CEX) Bit 1 Bit 1 Transmitter 1 Word Length Select (TxWLS1) t'! 2 Flag/Mark Idle Select (F/M Idle) Auto/Address Extend Mode (AEX) Bit 2 Bit2 .. Transmitter Interrupt Enable (TIE) Transmitter 2 Word Length Select (TxWLS2) 3 Receiver Data Service Request Mode (RDSR Mode) Frame Complete/ TDRA Select (FC/TDRA Select) 01/11 Idle (01/11 Idle) Bit 3 Bit3 Receiver 1 Word Length Select (RxWLS,) 4 Transmitter Data Service Request Mode (TDSR Mode) Transmit Last Data (Tx Last) Flag Detect Status Enable (FDSE) Bit4 Bit 4 Receiver 2 Word Length Select (RxWLS2) 5 Rx Frame Discontinue ( DISCONTINUE) Clear Receiver Status (CLR RxST) Loop/Non-Loop Mode (LOOP) Bit5 Bit 5 Transmit Abort (ABT) 6 Receiver Reset (RxRS) Clear Transmitter Status ICLR TxST) Go Active on Poll/Test (GAP/TST) Bit6 Bit6 Abort Extend (ABTEX) 7 Transmitter Reset (TxRS) Request-to-Send Control (RTS) Loop On-Line Control/DTR Control (LOC/DTR) Bit 7 Bit 7 NRZI (Zero Complement)/NRZ Select (NRZI/NRZ) .! .!! 1:11 II: ~ c 0 ~ 5·252 F6854/F68A54/F68B54 Control Register 1 (CR1) RS, L RSo L R/W L AC X 7 6 TxRS RxRS 4 5 DISCONTINUE TDSR Mode bO Address Control (AC) - AC provides another register select signal internally. The AC bit is used in conjunction with the RSo, RS, and Riw inputs to select particular registers, as shown in Table 2. b1 Receiver Interrupt Enable (RIE) - RIE enables/ disables the interrupt request caused by the receiver section (HIGH = enable, LOW = disable). Transmitter Interrupt Enable (TIE) - TIE enables/disables the interrupt request caused by the Transmitter (HIGH = enable, LOW = disable). b3 Receiver Data Service Request Mode (RDSR Mode) RDSR Mode provides the capability of operation with a bus system in the DMA mode when used in conjunction with the prioritized status mode. When RDSR Mode is set, an interrupt request caused by the RDA status bit is inhibited, and the ADLC does not request data transfer via the IRQ output. b4 Transmitter Data Service Request Mode (TDSR Mode) - TDSR Mode provides the capability of operation with a bus system in the DMA mode when used in conjunction with the prioritized status mode. When TDSR Mode is set, an interrupt request caused by the TDRA/FC status bit is inhibited, and the ADLC does not request a data transfer via the IRQ output. b5 Rx Frame Discontinue (DISCONTINUE) - When DISCONTINUE is set, the currently received frame is ignored and the ADLC discards the data of the current frame. DISCONTINUE is automatically reset when the last byte of the frame is discarded or when the ignored frame is aborted by receiving an abort or DCD failure. b6 Receiver Reset (RxRS) - When RxRS is HIGH, the receiver section stays in the reset condition. All receiver sections, including the Rx FIFO and the receiver status bits in both status registers, are reset. (During reset, the stored DCD status is reset but the DCD status bit follows the DCD input.) RxRS is set by forCing a LOW level on the RESET input or by writing 2 1 0 TIE RIE AC a HIGH into RxRS from the data bus. RxRS will be reset by writing a LOW from the data bus after RESET has gone HIGH. b7 b2 3 RDSR Mode Transmitter Reset (TxRS) - When TxRS is HIGH, the transmitter section stays in the reset condition and transmits marks (1s). All transmitter sections, including the Tx FIFO and the transmitter status bits, are reset (Tx FIFO cannot be loaded). During reset, the stored CTS status is reset but the CTS status bit follows the CTS input. TxRS is set by forcing a LOW level on the RESET input or by writing a HIGH from the data bus. It will be reset by writing a LOW after RESET has gone HIGH. • F6854/F68A54/F68854 Control Register 2 (CR2) RS1 L RSo Riw H L (C1bO = L) AC L 7 6 5 4 3 2 1 0 RTS CLR TxST CLR RxST Tx Last FCITDRA Select F/M Idle 2/1 Byte PSE bO Prioritized Status Enable (PSE) - When PSE is set. the status bits in both status registers are prioritized as defined in the Status Register section. When PSE is LOW. the status bits indicate current status without bit suppression by other status bits. The exception to this rule is the CTS status bit which always suppresses the TDRA/FC status bit. b6 Clear Transmitter Status (CLR TxST) - When a HIGH is written into CLR TxST. a reset signal is generated for the transmitter status bits in Status Register 1 (except TDRA/FC). The reset signal is enabled for the bits which have been present during the last read status operation. CLR TxST automatically returns to the LOW state. b1 2-Byte/1-Byte Transfer (2/1-Byte) - When 2/1-Byte is reset. the TDRAlFC and RDA status bits then will indicate the availability of their respective data FIFO registers for a single-byte data transfer. Similarly. if 2/1-Byte is set. the TDRA/FC and RDA status bits indicate when two bytes of data can be moved without a second status read. b7 b2 Flag/Mark Idle Select (F/M Idle) - F/M Idle Select selects flag characters or bit-by-bit mark idle for the time fill or the idle state of the Transmitter. When mark idle is selected. go-ahead code can be generated for loop operation in conjunction with the 01/11 Idle control bit (HIGH =flag time fill. LOW = mark idle). Request-to-Send Control (RTS) - RTS. when HIGH. causes the Ri'S output to be LOW (the active state). When the RTS bit returns LOW and data is being transmitted. the RTS output remains LOW until the last character of the frame (the closing flag or abort) has been completed and the Tx FIFO is empty. If the Transmitter is idling when the RTS bit returns LOW. the RTS ouput will go HIGH (the inactive state) within two bit-times. b3 Frame CompletelTDRA Select (FC/TDRA Select)FCITDRA Select selects TDRA status or FC status for the TDRA/FC status bit indication (HIGH = FC status. LOW = TDRA status). b4 Transmit Last Data (Tx Last) - Tx Last provides another method to terminate a frame. When the Tx Last is set just after loading a data byte. the ADLC assumes the byte is the last byte and terminates the frame by appending Cyclic Redundancy Check Character (CRCC) and a closing flag. This control bit is useful for DMA operation. Tx Last automatically returns to the LOW state. b5 Clear Receiver Status (CLR RxST) - When a HIGH is written into CLR RxST. a reset signal is generated for the receiver status bits in Status Registers 1 and 2 (except AP and RDA bits). The reset signal is enabled only for the bits which have been present during the last read status operation. CLR 'RxST automatically returns to the LOW state. F6854/F68A54/F68B54 Control Register 3 (CR3) RS1 RSo R/W AC 7 6 5 4 3 2 1 a L H L H LOC/DTR GAP/TST LOOP FDSE 01/11 AEX CEX LCF (C1bO = H) bO control bit, LOC/DTR control bit and LOC/DTR output are selected to perform the loop control functions. When LOOP is reset, the ADLC operates in the pointto-point data communications mode. Logic Control Field Select (LCF) - LCF causes the first byte(s) of data belonging to the information field to remain 8-bit characters until the logic control field is complete. The logic control field (when selected) is an automatically extendable field which is extended when bit 7 of a logic control character is HIGH. When LCF is reset, the ADLC assumes no logic control field is present for either the transmitted or received data channels. When the logic control field is terminated, the word length of the information data is then defined by Rx or Tx WLS1 and WLS2. b1 Extended Control Field Select (CEX) - When the CEX bit is HIGH, the control field is extended and assumed to be 16 bits. When CEx is LOW, the control field is assumed to be eight bits. b2 Auto/address Extend Mode (AEX) - AEX, when LOW, allows a full eight bits of the address octet to be utilized for addressing, because address extension is inhibited. When AEX is HIGH, bit a of address octet equal to a causes the address field to be extended by one octet. The exception to this automatic address field extension is when the first address octet is all as (the null address). b3 Idle b6 In the non-loop mode GAP/TST is used for self-test purposes. If GAP/TST is set, the TxData output is connected to the RxData input internally, and provides a loop-back feature. For normal operation, the GAP/TST bit should be reset. b7 01/11 Idle (01/11 Idle) - The 01111 Idle control bit determines whether the inactive (mark) idle condition begins with a a or not. If 01/11 Idle is set, the closing flag (or abort) will be fOllowed by a 011111 ... pattern. This is required of the controller for the go-ahead character in the loop mode. When 01/11 Idle is reset, the idling condition will be all1s. b4 Flag Detect Status Enable (FDSE) - FDSE enables the Flag Detected (FD) status bit in Status Register 1 to indicate the occurrence of a received flag character. The status indication will be accompanied by an interrupt if the RIE control bit is set. Flag detection will cause the FLAG DET output to go LOW for one bit-time regardless of the state of FDSE. b5 Loop/Non-Loop Mode (LOOP) - When LOOP is set, loop mode operation is selected and the GAP/TST Go Active on Poll/Test (GAP/TST) - In the loop mode GAP/TST is used to respond to the poll sequence and to begin transmission. When GAP/TST is set, the Receiver searches for the go-ahead (or endof-poll, EOP). The Receiver go-ahead is converted to an opening flag and the ADLC starts its own transmission. When GAP/TST is reset during the transmission, the end of the frame (the completion of flag or abort) causes the termination of the goactive-on-poll operation and the RxData to TxData link is reestablished. The ADLC then returns to the loop-on-line state. Loop On-line ControllDTR Control (LOC/DTR)In the loop mode LOC/DTR is used to go on-line or to go off-line. When LOC/DTR is set, the ADLC goes to the on-line state after seven consecutive 1s occur at the RxData input. When LOC/DTR is reset, the ADLC goes to the off-line state after eight consecutive 1s occur at the RxData input. In the non-loop mode the LOC/DTR bit directly controls the LOC/DTR output state (HIGH = DTR output goes to LOW level, LOW= DTR output goes to HIGH level). 5·255 • F6854/F68A54/F68854 Control Register 4 (CR4) RS, RSo HH AC 7 6 5 4 L H NRZIINRZ ABTEX ABT RxWLS2 (C1bO=H) bO Double Flag/Single Flag Interframe Control ("FF"/ "F") - "FF"/"F" determines whether the Transmitter will transmit separate closing and opening flags when frames are transmitted successively. When the "FF"/"F" control bit is LOW, the closing flag of the first frame will serve as the opening flag of the second frame; when HIGH, independent opening and closing flags will be transmitted. Table 3 b3, Receiver Word Length Select (RxWLS" RxWSL21b4 RxWLS, and RxWLS2 are used to select the word length of the Receiver information field. The encoding format is shown in Table 3. b6 b7 3 2 I 1 0 TxWLS2 TxWLS, "FF"/"F" RxWLS, I-Field Character Length Select WLS1 WLS2 I·Field Character Length L L 5 bits H L L H 6 bits 7 bits H H 8 bits Status Registers Status Register 1 is the main status register. The IRQ bit indicates whether the ADLC requests service or not. The S2RQ bit indicates whether any bits in Status Register 2 request service. TDRA/FC and RDA, because they are most often used, are located in bit positions that are more convenient to test. RDA reflects the state of the RDA bit in Status Register 2. b1, Transmitter Word Length Select (TxWLS" TxWLS2)b2 TxWLS, and TxWLS2 are used to select the word length of the Transmitter information field. The encoding format is shown in Table 3. b5 I R/W Status Register 2 provides the detailed status information contained in the S2RQ bit, and these bits reflect receiver status. Transmit Abort (ABT)-ABT causes an abort (at least eight bits of 1 in succession) to be transmitted. The abort is initiated and the Tx FIFO is cleared when ABT goes HIGH. Once abort begins, the ABT bit assumes the LOW state. The prioritized status mode provides maximum efficiency in searching the status bits and indicates only the most important action required to service the ADLC. The priority trees of both status registers are provided in Figure 3. Abort Extended (ABTEX)-if ABTEX is set, the abort code initiated by ABT is extended at least 16 bits of consecutive 1s, the mark idle state. Reading the status register is a non-destructive process. The method of clearing status depends upon the bit function and is discussed for each bit in the register. NRZI (Zero Complement)/NRZ Select (NRZllNRZ) NRZI/NRZ selects the transmit/receive data format to be NRZI or NRZ in both loop mode or non-loop mODe operation. When the NRZI mode is selected, a 1-bit delay is added to the transmitted data (TxData) to allow for NRZI encoding (HIGH = NRZI, LOW = NRZ). Fig. 3' Status Register Priority Tree (PSE = 1) (Tx) Decreasing Priority I Note NRZI coding - The serial data remains in the same state to send a binary 1 and switches to the opposite state to send a binary O. / / I I I \ .... - CTS SR2 (Rx) FD ERR, FV, DCD, OVRN, RxABT S2RQ Rx IDLE RDA AP t + TXU \" SR1 (Rx) + TDRAlFC RDA t t + + RDA * Prioritized even when PSE =,0 Note Status bit above will inhibit one below it. 5·256 F6854/F68A54/F68B54 Status Register 1 (SR1) RS1 L RSo L R/W H AC X 7 6 5 4 3 2 1 0 IRQ TDRA/FC TXU CTS FD LOOP S2RQ RDA bO Receiver Data Available (RDA) - The RDA status bit reflects the state of the RDA status bit in status Register 2. It provides the means of achieving data transfers of received data in the full-duplex mode without having to read both status registers. b1 Status Register 2 Read Request (S2RQ) - All the status bits (stored conditions) of Status Register 2 (except RDA) are logically ORed and indicated by the S2RQ status bit. Therefore S2RQ indicates when Status Register 2 needs to be read. When S2RQ is LOW, it is not necessary to read Status Register 2. The bit is cleared when the appropriate bits in Status Register 2 are cleared or when RxRS is used. b2 b6 When the frame-complete mode of operation is selected, the TDRA/FC status bit goes HIGH when an abort is transmitted or when a flag is transmitted with no data in the Tx FIFO. The bit remains HIGH until cleared by resetting the FC/TDRA Select or setting the TxRS control bit. Loop Status (LOOP) - The LOOP status bit is used to monitor the loop operation of the ADLC. This bit does not cause an IRQ. When non-loop mode is selected, LOOP stays LOW; when loop mode is selected, the LOOP goes to HIGH during on-loop condition. When ADLC is in an off-loop condition or go-active-on-poll condition, the LOOP status bit is LOW. b3 Flag Detected (FD) - The FD status bit indicates that a flag has been received if the Flag Detect Status Enable control bit has been set. FD goes HIGH at the last bit of the flag character received (when the FLAG DET output goes LOW) and is stored until cleared by clear RxST or RxRs. b4 Clear-To-Send (CTS) - The CTS input positive transition is stored in Status Register 1 and causes an IRQ (if enabled). The stored CTS condition and its IRQ are cleared by CLR TxST or TxRS control bit. After the stored status is reset, the CTS status bit reflects the state of the CTS input. b5 Transmitter Underrun (TxU) - When the transmitter runs out of data during a frame transmission, an underrun occurs and the frame is automatically terminated by transmitting an abort. The underrun condition is indicated by the TxU status bit. TxU can be cleared by means of the CLK TxST control bit or by TxRS. Transmitter Data Register Available/Frame Complete (TDRA/FC) - The TDRA/FC status bit serves two purposes, depending upon the state of the FCITDRA Select control bit. When TDRA/FC serves as a TDRA status bit, it indicates that data (to be transmitted) can be loaded into the Tx FIFO. The first register (Register 1) of the Tx FIFO being empty (TDRA = HIGH) will be indicated by the TDRA/FC status bit in the 1-byte transfer mode. The first two registers (Registers 1 and 2) must be empty for TDRA to be HIGH when in the 2-byte transfer mode. TDRAlFC is inhibited by TxRS or CTS being HIGH. b7 5·257 Interrupt Request (IRQ) - The Interrupt Request status bit indicates when the IRQ output is in the active state (IRQ output = LOW). The IRQ status bit is subject to the same interrupt enables (RIE, TIE) as the IRQ output. The IRQ status bit simplifies status inquiries for polling systems by providing single-bit indication of service requests. 5 F6854/F68A54/F68854 Status Register 2 (SR2) RS, RSo R/W AC L H L X bO b1 b2 7 6 5 4 3 2 1 0 RDA OVRN DCD ERR RxABT Rx Idle FV AP Address Present (AP) - The AP status bit provides the frame boundary and indicates an address octet is available in the Rx FIFO. In the extended addressing mode. the AP bit continues to indicate addresses until the address field is complete. The AP status bit is cleared by reading data or by RxRS. status bit. Other functions. frame boundary indication and control function. are exactly the same as for the Frame Valid status bit. Refer to the FV status bit. Frame Valid (FV) .:..- The FV status bit provides the frame boundary indication to the MPU and also indicates that a frame is complete with no error. The FV status bit is set when the last data byte of a frame is transferred into the last location of the Rx FIFO (available to be read by MPU). Once FV status is set. the ADLC stops further data transfer into the last location of the Rx FIFO (in order to prevent' the mixing' of two frames) until the status bit is cleared by theCLR RxST or RxRS control bit. Inactive Idle Received (Rx Idle) - The Rx Idle status bit indicates that a minimum of 15 consecutive 1s have been received. The event is stored within the status register and can cause an interrupt. The interrupt and stored condition are cleared by the CLR RxST control bit. Rx Idle is the logical OR of the receiver idling detector (which continues to reflect idling until a LOW is received) and the stored inactive idle condition. b3 Abort Received (RxABT) - The RxABT status bit indicates that seven or more consecutive 1s have been received. Abort has no meaning under out-of-frame conditions; therefore. no interrupt or storing of the status will occur unless a flag has been detected prior to the abort. An abort received when in-frame is stored in the status register and causes an IRQ. The RxABT is the logical OR of the stored conditions and the receiver abort detect logic. which is cleared after 15 consecutive 1s have occurred. The stored abort condition is cleared by the CLR RxST or RxRS control bit. b4 Frame Check Sequence/Invalid Frame Error (ERR) When a frame is complete with a cyclic redundancy check (CR C) error or a short frame error (the frame does not have complete address and control fields). the ERR status bit is set instead of the Frame Valid 5-258 b5 Data Carrier Detect (DCD) - A positive transition on the DCD input is stored in the status register and causes an IRQ (if enabled). The stored DCD condition and its IRQ are cleared by the CLR RxST control bit or RxRS. After stored status is reset. the DCD status bit follows the state of the DCD input. Both the stored DCD condition and the DCD input cause the reset of the receiver section when they are HIGH. b6 Receiver Overrun (OVRN) - The OVRN status bit indicates that receiver data has been transferred into the Rx FIFO when it is full. resulting in data loss. The OVRN status bit is cleared by the CLR RxST or RxRS control bit. Continued overrunning only destroys data in the first FIFO register. b7 Receiver Data Available (RDA) - The Receiver Data Available status bit indicates when receiver data can be read from the Rx FIFO. When the prioritized status mode is used. the RDA bit indicates that non-address and non-last data are available in the Rx FIFO. The receiver data being present in the last register of the FIFO causes RDA to be HIGH for the 1-byte'transfer mode. The RDA bit being HIGH indicates that the last two registers are full when in the 2-byte transfer mode. The RDA status bit is reset automatically when data is not available. F6854/F68A54/F68B54 Frame Format ~I·~--------------------------------AFRAME--------------------------------~ 01111110 (OPENING) FLAG 'EXTENDABLE (OPTIONAL) 01111110 ADDRESS· FIELD CONTROL' FIELD LOGICAL CONTROL SUB-FIELD (OPTION) ~INFORMATION The ADLC transmits and receives data (information or control) in a format called a frame. All frames start with an opening flag (F) and end with a closing flag (F). Between the opening flag and closing flag, a frame contains an address field, control field, information field, and frame check sequence field. FRAME CHECK SEQUENCE FIELD (CLOSING) FLAG FIELD--1 octet becomes the CEX control bit. When the bit is LOW, the ADLC assumes another address octet will follow; when the bit is HIGH, the address extension is terminated. A "null" address (all LOW) does not extend. In the Receiver, the AP status bit distinguishes the address field from other fields. When an address byte is available to be read in the Rx FIFO, the AP status bit is set and causes an interrupt (if enabled). The AP status bit is set for every addresss octet when the address extend mode is used. Flag (F) The flag is the unique binary pattern 01111110. It provides the frame boundary and a reference for the position of each field of the frame. Control (C) Field The eight bits following the address field are the control (link control) field. When the CEX control bit in Control Register 3 is selected, the C-field is extended to 16 bits. The ADLC Transmitter generates a flag pattern internally and the opening flag and closing flags are appended to a frame automatically. Two successive frames can share one flag for a closing flag of the first frame and for the opening flag of the next frame, if the "FF/F" control bit in Control Register 4 is reset. Information (I) Field The I-field follows the C-field and precedes the FCS field. The I-field contains data to be transferred but is not always necessarily contained in every frame. The word length of the I-field can be selected from five to eight bits per byte by control bits in Control Register 4. The I-field will continue until it is terminated by the FCS and closing flag. The Receiver has the capability to handle a partial last byte. The last information byte can be any word length between one and eight bits. If the last byte in the I-field is less than the selected word length, the Receiver will right justify the received bits, fill the remaining bits of the receiver shift register with zeros, and transfer a full byte to the Rx FIFO. Regardless of selected byte length, the ADLC will transfer eight bits of data to the data bus. Unused bits for word lengths of five, six, and seven will be zeroed. The Receiver searches for a flag on a bit-by-bit basis and recognizes a flag at any time. The Receiver establishes the frame synchronization with every flag. The flags mark the frame boundary and reference for each field but they are not transferred to the Rx FIFO. The detection of a flag is indicated by the FLAG DET output and by the FD Status bit. Order of Bit Transmission Address, control and information field bytes are transferred between the MPU and the ADLC in parallel by means of the data bus. The bit on Do (data bus bit 0, pin 22) is serially transmitted first, and the first serially received bit is transferred to the MPU on Do. The FCS field is transmitted and received MSB first. LogiC Control (LC) Field When the LCF control bit in Control Register 3 is selected, the ADLC separates the I-field into two sub-fields. The first sub-field is the logic control field and the following subfield is the data portion of the I-field. The logic control field is eight bits and follows the C-field, which is extendable by Address (A) Field The eight bits following the opening flag are the address (A) field. The A-field can be extendable if the auto-address extend mode is selected in Control Register 3. In the address extend mode, the first bit (bit 0) in every address 5-259 5 F6854/F68A54/F68B54 Abort The function of prematurely terminating a data link is called abort. The Transmitter aborts a frame by sending at least eight consecutive 1s immediately after the ABT control bit in Control Register 4 is set to HIGH. (Tx FIFO is also cleared by the ABT control bit at the same time.) The abort can be extended to at least 16 consecutive 1s, if the ABTEX control bit in the Control Register 4 is set when an abort is sent. This feature is useful to force mark idle transmission. Reception of seven or more consecutive 1s is interpreted as an abort by the Receiver. The Receiver responds to a received abort as follows: 1. An abort in an out-of-frame condition-An abort during the idle or time fill has no meaning. The abort reception is indicated in the Status Register as long as the abort condition continues, but neither an interrupt nor a stored condition occurs. The abort indication disappears after 15 or more consecutive 1s are received (Rx Idle status bit is set). 2. An abort in frame, when less than 26 bits have been received after an opening flag, has not transferred any field to the MPU. The ADLC clears the aborted frame data in the Rx FIFO and clears flag synchronization. Neither an interrupt nor a stored status occurs. The status indication is the same as (1) above. 3. An abort in-frame, when 26 bits or more have been received after an opening flag, might have transferred some fields of the aborted frame onto the data bus. The abort status is stored in Status Register 2 and the data of the aborted frame in the ADLC is cleared. The synchronization is also cleared. octets, if it is selected. The last bit (bit 7) is the CEX bit, and if it is HIGH, the LC-field is extended one octet. Note Hereafter, the term information field, or I-field, is used as the data portion of the information field and excludes the logic control field. This is done in order to keep the consistency of the meaning of information field as specified in SOLC, HOLC, and AOCCP standards. Frame Check Sequence (FCS) Field The 16 bits preceding the closing flag are the FCS field. The FCS is the cyclic redundancy check character (CRCC). The polynomial x16 + x12 + x5 + 1 is used both for the Transmitter and Receiver. Both the transmitter and receiver polynomial registers are initialized to all 1s prior to calculation of the FCS. The Transmitter calculates the FCS on all bits of the address, control, logic control (if selected), and information fields, and transmits the complement of the resulting remainder as FCS. The Receiver performs a similar computation on all bits of the address, control, logic control (if selected), information, and received FCS fields and compares the result to FOB8 (hexadecimal). When the result matches FOB8, the FV status bit is set in Status Register 2. If the result does not match, the ERR status bit is set. The FCS generation, transmission, and checking are performed automatically by the ADLC Transmitter and Receiver. The FCS field is not transferred to the Rx FIFO. Invalid Frame Any valid frames should have at least the A-field, C-field and FCS field between the opening flag and the closing flag. When invalid frames are received, the ADLC handles them as follows: 1. A short frame which has less than 25 between flags- The ADLC ignores the short frame and its reception is not reported to the MPU. 2. A frame less than 32 bits between the flags, or a frame 32 bits or more with an extended A-field or C-field that is not completed is transferred into the Rx FIFO. The ERR status bit indicates the reception of the invalid frame at the end of the frame. 3. Aborted frame- The frame which is aborted by receiving an abort or DCD failure is also an invalid frame. Refer to ABT and DCD status bits. Idle and Time Fill When the Transmitter is in an out-of-frame condition (the Transmitter is not transmitting a frame), it is in an idle state. Either a series of contiguous flags (time fill) or a mark idle (consecutive 1s on a bit-by-bit basis) is selected for the transmission in an idle state by the F/M Idle control bit. When the Receiver receives 15 or more consecutive 1s, the Rx Idle status bit is set and causes an interrupt. The flags and mark idle are not transferred to the Rx FIFO. Programming Considerations 1. Status Priority ~ When the prioritized status mode is used, it is best to test for the lowest priority conditions first. The lowest priority conditions typically occur more frequently and are the most likely conditions to exist when the processor is interrupted. Zero Insertion and Zero Deletion The zero insertion and deletion that allows the content of the frame to be transparent is performed by the ADLC automatically. A binary 0 is inserted by the Transmitter after any succession of five 1s within a frame (A, C, LC, I, and FCS field). The Receiver deletes a binary 0 that follows five successive 1s with ina frame. 2. Stored vs. Present Status - Certain status bits (DCD. CTS, RxABT, and Rx Idle) indicate a status which is the logic OR of a stored and a present condition. It is the stored status that causes an interrupt and which is 5·260 F6854/F68A54/F68B54 status (Control Register 2). Test RDA to indicate whether a 1-byte read should be performed. Then clear the frame end status. cleared by the CLR RxST or CLR TxST control bit. After being cleared, the status register will reflect the present condition of an input or a receiver input sequence. 6. Frame Complete Status and RTS Release - In m~ cases, a modem will require a delay for releasing RTS. An 8-bit or 16-bit delay can be added to the ADLC RTS output by using an abort. At the end of a transmission, frame-complete status will indicate the frame completion. After the TDRA/FC status bit goes HIGH, write 1 into the ABT control bit (and ABTEX bit if a 16-bit delay is required). After the ABT control bit is set, write 0 into the RTS control bit. The Transmitter will transmit eight or 16 1s and the RTS output will then go HIGH (inactive). 3. Clearing Status Registers - In order to clear an interrupt with the two status clear control bits, a particular status condition must be read before it can be cleared. In the prioritized mode, clearing a higher priority condition might result in another IRQ caused by a lower priority condition whose status was suppressed when a status register was first read. This guarantees that a status condition is never inadvertently cleared. 4. Clearing the Rx FIFO - An RxRS will effectively clear the contents of all three Rx FIFO bytes. However, the Rx FIFO may contain data from two different frames when abort or DCD failure occurs. When this happens, the data from a previously closed frame (a frame whose closing flag has been received) will not be destroyed. 7. Note to users not using the F6800 - (a) Care should • be taken when performing a write followed by a read on successive E pulses at a high frequency rate. Time must be allowed for status changes to occur. If this is done, the time that E is LOW between successive write/read E pulses should be at least 500 ns. (b) The ADLC is a completely static part. However, the E frequency should be high enough to move data through the FIFO registers and to service the peripheral requirements. Also, the period between successive E pulses should be less than the period of RxC or TxC in order to maintain synchronization between the data bus and the peripherals. 5. Servicing the Rx FIFO in a 2-Byte Mode - The procedure for reading the last bytes of data is the same, regardless of whether the frame contains an even or an odd number of bytes. Continue to read two bytes until an interrupt occurs that is caused by an end-of-frame status (FV or ERR). When this occurs, indicating that the last byte either has been read or is ready to be read, switch temporarily to the 1-byte mode with no prioritized 5·261 F6854/F68A54/F68B54 Absolute Maximum Ratings Supply Voltage, Vee Input Voltage, VIN Operating Temperature, TA . F6854P/S, F68A54P/S, F68B54P/S F6854CP/CS, F68A54CP/CS F6854DL F6854OM Storage Temperature, TstG DC Characteristics Symbol VIH VIL VOH VOL liN ITSI ILOH Po CIN COUT -O.3V, +7.0V -0.3V, +7.0V O°C, "':40° C, -55° C, -55°C, -65°C, Thermal Resistance, (JJA Plastic Ceramic +70°C +85° C +85° C +125°C +150°C 115°C/W 60° CIW These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however. it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. Vee = 5.0 V + - 5%, Vss = 0, TA = over operating temperature range, unless otherwise noted Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage 00-07 All Others Output LOW Voltage Input Leakage Current All Inputs Except 00-07 Three-State (Off State) InputCurrent 00-07 Output Leakage Current(Off State) IRQ Power Dissipation Input Capacitance 00-07 All Other Inputs Qillput Capacitance IRQ All Others Min VSS Typ Max + 2.0 Vss Vss Vss + 0.8 V Vss + 0.4 2.5 Condition V .V + 2.4 + 2.4 1.0 test Unit V Jl.A ILoad = -205 Jl.A ILoad = -100 JJA ILoad = 1.6 mA VIN = 0 to 5.25 V 2.0 10 Jl.A VIN = 0.4 to 2.4 V Vee = 5.25 V 1.0 10 850 Jl.A mW VOH = 2.4 V Vee = 5.25 V 12.5 7.5 pF 5.0 10 pF VIN = 0, TA = 25°C, f = 1.0 MHz AC Characteristics Symbol PWeL PWeH f max tROSU tROH tRTS tTOO tFO tOTR tLOe tROSR tTDSR tlR tRES tr, tf Characteristic Minimum Clock Pulse Width, LOW Minimum Clock Pulse Width, HIGH Clock Frequency Receive Data Set-up Time Receive Data Hold Time Request-to-Send Delay Time . Clock-to-Data Delay for Transmitter Flag Detect Delay Time DTR Delay Time Loop On-line Control Delay Time RDSR Delay Time TDSR Delay Time Interrupt Request Release Time RESET Minimum Pulse Width Input Rise and Fall Times (Except Enable) 0.8 V to 2.0 V F6854 Min Max F68A54 Min Max F68B54 Min Max 700 700 450 450 280 280 0.66 250 120 1.0 460 320 460 460 460 400 400 0.9 680 460 680 680 680 540 540 1.2 1.0 0.65 1.0· ·1.01-'5 or 10% of the pulse width. whichever is smaUer. 5·262 1.5 120 60 200 100 340 250 340 340 340 340 340 0.7 0.40 to· to· Unit ns ns MHz ns ns ns ns ns ns ns ns ns Jl.s Jl.S Jl.S F6854/F68A54/F68B54 Vee = 5.0 V Bus Timing Characteristics Symbol Read PWEH PWEL teyeE tAS tosw tH tAH tEr, tEl F68A54 Min Max F68B54 Min Max Enable Pulse Width, HIGH Enable Pulse Width, LOW Enable Cycle Time Set-up Time, Address and R/W Valid to Enable Positive Transition Data Delay Time Data Hold Time Address Hold Time Rise and Fall Time for Enable Input 0.45 0.43 1.0 160 0.28 0.28 0.666 140 0.22 0.21 0.50 70 Enable Pulse Width, HIGH Enable Pulse Width, LOW Enable Cycle Time Set Time, Address and R/W Valid to Enable Positive Transition Data Set-up Time Data Hold Time Address Hold Time Rise and Fall Time for Enable Input 0.45 0.43 1.0 160 0.28 0.28 0.666 140 0.22 0.21 0.50 70 195 10 10 80 10 10 60 10 10 320 25 RL -.--_-I - Vee Vss RSOF RDA RSDR RECEIVER STATUS/DATA REGISTER AO"'A2 BYTE MCSA I RCTS 11 t ' TCDR~C TRANSMITTER CONTROWDATA REGISTER it ~> RECEIVER LOGIC AND CONTROL TRANSMITTER LOGIC AND CONTROL I tt IRQ TBMT 5-271 I RTS TCLK TSO RCLK RSI F6856 Fig. 2 Receiver Data Path TEST LOOP RIB (16) CCR(16) ROA RSOF RCVR CONTROL IRQ Ci RCLK Fig. 3 FROM RCR TCLK TO DATA BUS (0,·015) TO DATA BUS (00·0,) Transmitter Data Path FROM DATA BUS (00·0,) TCLK CTS Ci FROM TCR TO DATA BUS (00·0,)· FROM RCVR LOOP REPEATER IRSI TSO CGR(16) 5·272 F6856 Fig. 4 BOP Receive Flow Chart Character assembly and CRC accumulation are stopped when a closing FLAG, ABORT or GA is detected. REOM, ABGA (if the closing character was an ABORT or GA), RDLo-RDL2 (indicating length of last character) and RERR (if the accumulated CRC is incorrect) status bits are set. The last character is transferred to ROB, the RDA output is set HIGH and the IRQ output is set LOW. FOR EOM = ABORT OR GO·AHEAD FOR EOM FLAG RSOF = 1 The CRC accumulation includes all characters following the opening FLAG through the frame check sequence (FCS). The contents of the CRC check register (CCR) are checked at the close of a frame if CRC is selected. If an error is detected, RERR status bit is set. Neither the FCS nor the closing FLAG are assembled and passed on to the CPU. = The receiver may be turned off after the status and last characters are read by the CPU by resetting the RE bit of RCR, or it can be left active to receive additional frames. The closing FLAG of one frame may be used as the opening FLAG of the next frame. Character assembly of the next frame starts with the first non·FLAG character. If the frame was closed with an ABORT or GA, an opening FLAG must be detected before character assembly of the next frame is started. RDA = 1 All receiver status bits except RDA are reset after the re.ceiver status register (RSR) is read by the CPU. The RDA output and status bit are reset when ROB is read by the CPU, ·EOM = FLAG, ABORT OR GO·AHEAD If secondary address is selected, the first non·FLAG character of a frame is compared to the contents of the SYNC/Address Register (SAR). Data for the frame is not passed on to the CPU if no address match occurs. When GLOBAL address is selected, an all '1s' address also results in address match, IRQ = 0 Loop Repeater Operation - Loop repeater mode is a special case of BOP. Receiver operation is the same as for BOP, except that the NRZI decode logic is disabled, frames may be terminated by a GO·AHEAD or FLAG, and received data and GA are routed to the transmitter. The RCLK and TCLK lines should be tied together in this mode. Fig. 5 BISYNC Operation - A flow chart of BISYNC receiver operation is shown in Figure 6, and the BISYNC message format is illustrated in Figure 7. Characters in BISYNC mode may be either EBCDIC or ASCII, as programmed in the MCR. Character length defaults to eight bits. The eighth bit, when ASCII is programmed, may be used for odd parity by the CPU. It is ignored in the recognition of the ASCII characters, BOP Message Format INFORMATION FIELD (IF ANY) o to m BITS INCLUDED IN CRC ACCUM. 5·273 F6856 Character assembly starts after receipt of two continuous SYNC characters and continues until the receiver is turned off by resetting the RE bit of RCA. Assembled characters are shifted through the RIB to the RSPR and transferred to the RDB. The RDA output and status bits are set HIGH each time a character is transferred to the RDB. All characters that match the SYNC character in non·transparent mode and DLE SYNC pairs (if not immediately preceded by an odd number of DLEs) in transparent mode are excluded from the RDB. However, the RSOF output goes HIGH for one RCLK clock period each time a SYNC character is detected. Fig. 6a Data must be read by the CPU each time the RDA output goes HIGH before the next character is assembled to prevent an overrun, resulting in loss of data. The IRQ output goes LOW and the ROVR status bit is set if an overrun occurs. The receiver always starts operation in the nontransparent mode. It switches to transparent mode if a DLE STX character pair is received. The receiver will then remain in transparent mode until a DLE ITB, DLE ETB or DLE ETX (if not immediately preceded by an odd number of DLEs) character pair is received. CRC accumulation begins after the first non·SYNC character if the first character is an SOH or STX. It begins after the second non·SYNC character and enters transparent mode if the first two non-SYNC characters are DLE STX. SYNC characters in non·transparent mode or DLE SYNC pairs in transparent mode are excluded from the CRC accumulation. The first DLE of a DLE DLE sequence and the DLE of DLE ITB, DLE ETB or DLE ETX sequences are not included in the accumulation. The CRC is checked for 0000 remainder after receipt of an ITB, ETB or ETX in non-transparent mode or DLE ITB, DLE ETB or DLE ETX in transparent mode. The REaM and RERR (a non-zero remainder is detected) status bits are set when the closing character is transferred to the RDB, RDA is set HIGH and IRQ is set LOW. The block check character (BCC) following the closing character is passed to the CPU as the next two characters. If the closing character was an ETB or ETX, the receiver should be reset by dropping the RE bit of RCA. If the closing character was an ITB, CRC accumulation and character assembly will start again on the first character following the BCC. All receiver status bits except RDA are reset each time RSR is read by the CPU. The RDA output and status bit are reset each time RDB is read by the CPU. 5-274 BISYNC Receive F6856 Fig. 6b Fig. 6c BISYNC Receive BISYNC Receive iRa = RDA 0 =1 RDA = 1 5·275 F6856 Fig. 6d BISYNC Receive TRANSPARENT MODE RDA = 1 ENTER TRANSPARENT MODE EXCLUDE FROM CRC EXCLUDE FROM CRC NO RSOF= 1 RIR _ROB 5·276 RDA = 1 F6856 Fig. 7 BISYNC Message Format NO CRC SHADED AREA INCLUDED IN CRC ACCUMULATION Shaded area included In CRC accumulation. CRC accumulation begins with the first non·SYNC character and includes all subsequent characters If SYNC strip is not programmed. The CRC accumulation will include only non·SYNC characters if SYNC strip is programmed. The CRC accumulation is checked each character time and the RERR status bit is set if the remainder does not equal "0" or reset if the remainder equals "0". Since there is no defined end·of·message (EOM) character, the REOM status bit is not set. The CPU must determine when the end of message occurs and check the RERR status at that time. If an error·free message has been received, RERR will be "0" for one character time. RE may be dropped, thereby resetting the receiver, after the last character has been read. If RE is not reset, CRC accumulation and character assembly will begin again on the first character following the BCC. The two characters of the BCC are output as normal data characters. BCP Operation - The flow diagram for BCP mode other than BISYNC is shown in Figure 8, and the BCP message format is illustrated in Figure 9. The SYNC character is programmed in the SAA. All characters, including the SYNC character are the length specified in , the receiver control register (RCR). Character assembly starts after receipt of two contiguous SYNC characters and continues until the receiver is turned off by resetting the RE bit of RCA. Assembled characters are shifted through the RIB to the RSPR and transferred to the ROB. The RDA output and status bit are set HIGH each time an assembled character is transferred to the ROB. All characters that match the SYNC character are excluded from the ROB, if SYNC strip has been programmed. Only leading SYNC characters are excluded from the ROB if SYNC stripping has not been programmed. However, the RSOF output goes HIGH for one RCLK clock period each time a SYNC character is detected. Data must be read by the CPU each time the RDA output goes HIGH before the next character is assembled. If !l2!, an overrun will occur resulting in loss of data. The IRQ output goes LOW and the ROVR status bit is set if an overrun occurs. 5-277 F6856 Fig. 8a BCP Receive Fig. 8b BCP Receive RDA I' Fig. 9 BCP Message Format 2X CIjARACTER LENGTH IF , CRC SELECTED 5·278 =1 F6856 (programmed in MCR) are the control field. The character length switches to the programmed length in TCR after the last character of the control field, unless that character was the end of message. Transmitter The mode control SYNC/address (MCSA) register must be programmed prior to starting transmitter operation. The CRC bit of the receiver control register must be set if ORC error checking is desired. The RTS bit of the transmitter control register (TCR) must be set to turn on the transmitter. The SOM bit of TCR may also be set at this time and the transmitter data buffer (TDB) loaded with the first character of the message. When RTS has been loaded into TCR, the RTS output goes LOW. The TSO output is held HIGH (marks) until the CTs input goes LOW. Two SYNC or FLAG characters are then output on TSO, if SOM has been set. Otherwise, TSO will continue to output marks until SOM is set and the first character is loaded into TDB. Transmitter operation after the two SYNC or FLAG characters have been output depends on the mode of operation. Note that TRS and transmitter character length must be reloaded each time TCR is updated until after the EOM bit has been set. The CPU must set the EOM bit of TCR when loading the last character of the message. Character length may be changed at this time to allow transmission of a residual last character. The character in TDB is followed by the FCS (if CRC is selected) and a closing FLAG when EOM is set. The transmitter may be turned off by resetting RTS after TBMT goes HIGH or it may remain active. The cloSing FLAG of one frame may be used as the opening FLAG of the next frame by setting SOM and loading TDB after TBMT goes HIGH. If the transmitter is left active and SOM has not been set, FLAG characters are transmitted between frames if the GATD bit of TCR equals "0" or marks if GATD equals "1". Fig. 10a BOP Transmit BOP Operation - Character length in BOP mode always starts at eight bits per character each frame. It remains eight bits until the address and control fields have been transmitted. It then switches tothe programmed length at the start of the information field, if any, until the last character has been transmitted. Character length switches back to eight bits for the transmission of the frame check sequence (FCS) and the closing FLAG. TURN ON TRANSMITTER RTS 1 = A flow diagram for BOP transmitter operation is shown in Figure 10. The secondary address is transmitted after the initial two FLAGs. The secondary address comes from the SYNC/address register (SAR) if the device is programmed as a secondary station or from the TDB if the device is programmed as a primary. If the secondary address came from SAR, it is followed in the transmission by the character from TDB. Characters are transferred in parallel from SAR or TDB to the transmitter shift register (TXR) and serially shifted, LSB first, out the TSO output. The TBMT output and status bit are set HIGH each time data is transferred from TDB. The CPU must update TCR, if required, and load TDB with the next character. An underrun occurs if this is not done within one character time. If an underrun occurs, the TUR status bit is set and an ABORT (11111111) is transmitted. The output is held at a mark until SOM is set for a new message. A transmitter overrun occurs if TDB is updated before TBMT goes HIGH. An overrun can result in the misinterpretation or loss of the character in TDB. The TOR status bit is set when an overrun occurs. CTS = 0 TBMT =1 SOM =1 The least significant bit (LSB) of each character, starting with the secondary address is examined. The first character with an LSB = "1" denotes the last character of the address field. The next one or two characters 5·279 F68S6 TUR and TOR status bits are reset whenever the transmitter status register (TSR) is read. The TBMT output and status bit are reset when TDB is loaded. A message may be terminated at any time with an ABORT by setting the TACG bit of TCR. This causes the TSO output to go immediately to mark condition until SOM is set. CRC accumulation begins with the first non-FLAG character and includes all subsequent characters up to and including the last data character. The accumulated CRC is then transmitted as the FCS following the last data character, if CRC is selected. Data transmitted on the TSO output is monitored continuously for five consecutive "15." A "0" is inserted in the data stream each time this condition occurs. This insures that a data character will not be interpreted as a FLAG, ABORT or GA at the received end. Fig.10c Fig. 10b BOP Transmit TACO = 1 TO ABORT iiffi =0 NO 5·280 BOP Transmit F68S6 as a DLE STX command and the transmitter begins transparent mode operation. The transmitter will remain in transparent mode until the end of the message. Loop Repeater Operation - Loop repeater mode is a special case of BOP. The primary station in the loop should be programmed for normal BOP primary operation. The GATD bit of TCR is used to initiate a polling sequence. When this bit is set, marks are transmitted after the closing FLAG of a frame. The last "0" of the closing FLAG and the next seven "1s" are interpreted down·loop as a GO·AHEAD. The end of the polling sequence is detected when the ABGA (received GA) bit of the RSR is set. The TBMT output and status bit are set HIGH each time data is transferred from TDB. The CPU should update TCR, if required, and load TDB with the next character. An underrun occurs if this is not done within one character time, and the TUR status bit is set and SYNC characters (or DLE SYNC pairs in transparent mode) are transmitted until TDB is updated. A transmitter overrun occurs if TDB is updated before TBMT goes HIGH. An overrun can result in the misinterpretation or loss of the character in TDB. The TOR status bit is set when an overrun occurs. Down·loop stations should be programmed as BOP secondary, loop repeater (LRSS = "1" in MCR). In this mode, data received at the RSI input is delayed one bit time and output on TSO. When data is to be transmitted in this mode, the CPU should set RTS and SOM and load the first character into TDB. The CTS input is ignored in this mode. The transmitter waits for a received GA. When a received GA is detected, the seventh "1" is changed to a "0," creating a FLAG. This prevents the down-loop station from receiving a GA, reserving the line for the transmitting station. The TBMT output and status bit are set and transmitter operation proceeds in normal BOP operation, except that the NRZI encode logic is disabled. The EOM bit of TCR, GATD (if in transparent mode) and TACG (if the accumulated CRC is to be transmitted as the block check character) should be set when the last character is loaded into TDB. The last character must be an ITB, ETB or ETX if CRC is used. A 16-bit BCC, if selected, is transmitted following the last character. The last character is followed by marks for a minimum of one character time if no BCC is transmitted. A second block of data may be transmitted immediately following the BCC by setting SOM and loading TDB after TBMT goes HIGH. The transmitter may be turned off at this time by resetting RTS. The transmitter transmits marks following the BCC for a minimum of one character time if SOM is not set. When the last character and FCS have been transmitted, the message is terminated with a GA. The TSO output switches back to RSI delayed one bit time. Down-loop stations may then capture the line by detecting the GA. The RCLK and TCLK lines should be tied together in this mode. CRC accumulation begins after the first non-SYNC character for non-transparent mode, or after the second non-SYNC character if the message starts in transparent mode. The CRC continues up to and including the last character. SYNC characters or DLE SYNC pairs caused by a transmitter underrun are not included. Forced DLE characters in transparent mode are not included. The forced DLE of a DLE STX pair which occurs after the start of the message is included. (See Figure 7.) BISYNC Operation - A flow diagram for BISYNC transmitter operation is shown in Figure 11. Character length for BISYNC mode defaults to eight bits per character. The transmitter always assumes nontransparent mode unless forced to transparent mode by the CPU. The message format following the initial SYNC pair depends on the action of the CPU. If the transmitter data buffer (TDB) has not been loaded with the first character of the message, SYNC characters are output on TSO until a TDB load. This can occur only with an 8-bit data bus, since TCR and TDB are loaded simultaneously for a 16-bit data bus. The character from TDB, when available, is transferred to the transmitter shift register, (TSR) and serially shifted out the TSO output. The character in TDB is preceded by a contiguous DLE when GATD (transmit DLE) is set. The GATD bit is cancelled after it has been internally processed. The first occurrence is interpreted TUR and TOR status bits are reset whenever the transmitter status register (TSR) is read. The TBMT output and status bit are reset when TDB is loaded. 5-281 F6856 Fig.11a BISYNC Transmit Fig. 11 b BISYNC Transmit G) 5·282 Not included in CRC accumulation F6856 Fig.11C BISYNC Transmit TRANSPARENT fr L- Vss RDA I I TBMT 5-298 t ~~. TRANSMITIER CONTROUDAT A REGISTER TRANSMITTER LOGIC AND CONTROL I' IRQ TCDR .~1 01 RECEIVER LOGIC AND CONTROL Vee RSOF RSDR RCTS RfS TCLK TSO RCLK RSI F38456/F68456 The F38456/F68456 signal functions are described in the following table. Mnemonic Pin No. Name Description TSO 1 Transmitter Serial Output This output signal is the transmitted serial data. Data changes on the positive going edge of TCLK. RSI 38 Received Serial Input This input signal is the received serial data. Data changes on the negative going edge of RCLK. TCLK 2 Transmitter Clock Timing of the transmitter logic is provided by this input signa I. Frequency is the same as the transmitted baud rate. RCLK 39 Receiver Clock Timing for the receiver logic is provided by this input. Frequency is the same as the received baud rate. CD 27 Carrier Detect This input is general·purpose in nature. It can be tested by reading the transmitter status register. RTS 3 Request to Send This output is used with clear to send to enable the transmitter. It may be set low by programming the appropriat e bit of the transmitter control register. CTS 26 Clear to Send This input signal is used with request to send to enable the transmitter. It can be tested by reading the transmitter status register. DTR 23 Data Terminal Ready This is a general-purpose output. It can be set low by programming the appropriate bit of the receiver control register. DSR 36 Data Set Ready This is a general-purpose input. It can be tested by the CPU by reading the transmitter status register. -- 22 Miscellaneous This is a general-purpose input/output. It can be set low by programming the appropriate bit of the register; it can be tested by the CPU by reading the receiver control register. RDA 14 Receiver Data Available A high level on this output signal indicates an assembled character is in the receiver buffer. RDA is reset on the trailing edge of enable when the receiver buffer is read by the CPU. TBMT 25 Transmitter Buffer Empty A high level indicates the device is ready to receive new data and/or control information from the CPU. This output signal is reset on the leading edge of the first transmitter clock; it follows the trailing edge of enable when the transmitter buffe is loaded. Transmit/Receive Modem Status/Control MISC Transmitter/ Receiver Status/Control 5-299 F38456/F68456 Mnemonic Pin No. Name Description 37 Received Sync or Flag RSOF is high for one receiver clock period when a received sync or flag character is detected on this output signal. 0 0 .015 6·13 28·35 Data Bus These are 16 bidirectional input/output data lines which control information to and from the CPU. Do . 0 7 can be wired to 0 8 • 0 15 for use as an 8·bit data bus. Ao· A2 15·17 Register Address These input signals select internal data, status, and control registers. They may be selected as 8· or 16·bit registers. E 19 Enable (F6456) A strobe on this input causes information transfer between the data bus and the addressed register when the chip enable input is low. RD 19 Read Pulse (F38456) A negative pulse on this input with address causes chip enable to transfer the data bus information to the addressed register. R/W 5 Read/Write (F68456) A high level on this input allows data from the addressed register to be output to the data bus. A low level allows data from the bus to be loaded into the addressed register. WR 5 Write Pulse (F38456) A negative pulse on this input with address causes chip enable to transfer the data bus information to the addressed register. CE 21 Chip Enable A low level on this input signal enables a data bus transfer with enable. BYTE 18 Byte A high level on this input signal indicates an 8·bit data bus. A low level indicates a 16·bit bus. IRQ 24 Interrupt Request This output goes low to indicate a change in the internal .;tatus of the device. The status bits linked to this output are receiver overrun (ROVR), received end·of·message (REOM) and transmitter underrun (TUR). IRQ is reset on the trailing edge 0 enable when the associated status register is read. Ci 4 Chip Initialize A low level initializes the internal control registers and timing on this input signal. Voo 40 Power Supply Power supply input: Vss 20 Ground Ground: 0 V reference Transmitter/ Receiver Status/Control RSOF CPU Interface and Control - Power 5·300 +5 V ± 5% F68488 I=AIRCHILO General-Purpose Interface Adapter A Schlumberger Company Microprocessor Product Description The F68488 General-Purpose Interface Adapter (GPIA) provides the means to interface between an IEEE-488 standard instrument bus and the F6800. The 488 instrument bus provides a means for controlling and moving data from complex systems of multiple instruments. Logic Symbol EOI RFD DAV DAe IBo IB, IB2 183 184 IBs IBs IB7 CS R/W The F68488 will automatically handle all handshake protocol needed on the instrument bus. • • • • • • • • • • • Single or Dual Primary Address Recognition Secondary Address Capability Complete Source and Acceptor Handshakes Programmable Interrupts RFD Hold-Off to Prevent Data Overrun Operates with DMA Controller Serial and Parallel Polling Capability Talk-Only or Listen-Only Capability Selectable Automatic Features to Minimize Software Synchronization Trigger Output F6800 Bus Compatible Pin Names DBa-DB? CS R/W RSo, RS1, RS2 IRQ RESET DMA GRANT DMA REQUEST ASE IBo-IB7 DAC RFD DAV ATN IFC SRQ REN EOI TRIG T/R1' T/R2 E Vss Vee 37 RSo IRQ 38 RS, ASE 39 RS2 19 RESET DMA REQUEST 15 SRQ 23 F68488 DMA GRANT TRIG 24 26 ATN TJA1 28 21 IFC T/R2 27 22 REN 9 10 11 12 13 14 Vee = Pin 20 Vss = Pin 1 Bidirectional Data Lines Chip Select Input Read/Write Input Register Select Inputs Interrupt Request Output Chip Reset Input DMA Transfer in Progress Input DMA Transfer Ready Output Address Switch Enable Output Bidirectional ASCII Bus Bidirectional Data Accepted Line Bidirectional Ready for Data Line Bidirectional Data Valid Line Attention Input Interface Clear Input Service Request Output Remote Enable Input Bidirectional End or Identify Line Group Execute Trigger Output Transmit/Receive Control Outputs Enable Clock Input Ground +5 V Power Supply Connection Diagram 40-Pin DIP Vss IRQ OMA GRANT RS 2 cs RS, ASE RS o R/W IBo IB, DBO IB2 DB, IB3 DB2 IB, DB3 IBs DB, IBS DB, IB7 DBs T/R, DB7 T/R2 DMA REQUEST ATN DAV EOI DAC TRIG RFD SRQ RESET REN iFC Vee (Top View) 5-301 40 II F68488 Functional Description in the sequence can be initiated until the previous step is completed. Information transfer can proceed as fast as the devices can respond, but no faster than the slowest device presently addressed as active. This permits several devices of different speeds to receive the same data concurrently. The IEEE-488 instrument bus standard is a bit-parallel, byte-serial bus structure designed for communication to and from intelligent instruments. Using this standard, many instruments may be interconnected and remotely and automatically controlled or programmed. Data may be taken from, sent to or transferred between instruments. A bus controller dictates the role of each device by making the attention (ATN) line true and sending talk or listen addresses on the instrument bus data lines; those devices that have matching addresses are activated. Device addresses are set into each GPIA from switches or jumpers on a pc board by a microproce$sor as a part of the initialization sequence. The GPIA is designed to work with standard 488-bus driver ICs to meet the complete electrical specifications of the IEEE-488 bus. Additionally, a powered-off instrument may be powered-on without disturbing the 488 bus. With some additional logic, the GPIA could be used with other microprocessors. The F68488 GPIA has been designed to interface the F6800 microprocessor with the complex protocol of the IEE.E-488 instrument bus. Many instrument bus protocol functions are handled automatically by the GPIA and require no additional MPU action. Other functions require minimum MPU response due to a large number of internal registers conveying information on the state of the GPIA and the instrument bus. When the controller makes the ATN line true, instrument bus commands may also be sent to single or multiple GPIAs. Information is transmitted on the instrument bus data lines under sequential control of the three handshake lines. No step Fig. 1. Functional Diagram DATA BYTe TRANSFER CONTROL DATA BUS (8 LINES) ---------------- ......- I + <..- GENERAL INTERFACE MANAGEMENT ...t DAV J / ( RFD / DAC iFC \ /' ATN I SRO / II DEVICE A ABLE TO TALK, LISTEN, AND CONTROL, e.g. CALCULATOR REN J/ J II I-I DEVICE B ABLE TO TALK AND LISTEN e.g. DIGITAL ro II DEVICE C ONLY ABLE TO LISTEN e.g. SIGNAL GENERATOR MULTI METER "" "" "" F684B8 "" r DEV ICE 0 ABL E TO,TALK AN o LISTEN ~ F6802 5·302 F68488 Fig. 2. F68488 GPIA Interface Vee 1 GPIB ~ • EDI SRO REN BUS MGMT. ~ ~ ~ DBs ~ ~ ~ REN IFC ATN r- NRFD OAV r-oe;- SRO 'F3tt8 -- ATN DAC -- OAV F68488 GPIA 01°1 ISo 010, IB, 01°3 010 4 IB3 01°5 is,; 01°6 IBs ~ ~ ~ ~ ~ 010, F3448 DATA I/O EOUEST E IB7 4 TIR, J F6800 } CONTROL BUS ~RANT ~ ASE IB6 010. F6800 } ADDRESS BUS E -rfiw IB, F3448 F6800 DATA BUS ~ RFO F3448 ~ DBo ~ EDI IFC NDAC 1 TIR, BUS HANDSHAKE I n Vss when used in conjunction with the Register Select lines, RSo, RS1, RS2. A HIGH state on the GPIA Read/Write line enables the selection of one of eight read-only registers when used in conjunction with the Register Select lines. GPIA/MPUlnterface Signals The F68488 interfaces to the F6800 MPU with an 8-bit bidirectional Data Bus, a Chip Select, Read/Write line, RESET line, three Register Select lines, an Interrupt Request line, two DMA Control lines, and an Address Switch Enable line. GPIA Register Select (RSO. RS1. RS2) - The three register select lines are used to select the various registers inside the GPIA. These three lines are used in conjunction with the Read/Write line to select a particular register that is to be written to or read from. Table 1 shows the register select coding. GPIA Bidirectional Data (OBO-OB7) - The bidirectional data lines allow the transler of data between the MPU and the GPIA. The data bus output drivers are 3-state devices that remain in the high-impedance (OFF) state except when the MPU performs a GPIA read operation. The Read/Write line is in the read state when the GPIA is selected for a read operation. Interrupt Request (IRQ) - The IRQ output goes to the common interrupt bus for the MPU. This is an open drain output which is wire-ORed to the IRQ bus. The IRQ is set false (LOW) when an enabled interrupt occurs and stays false until the MPU reads from the interrupt status register. GPIA Chip Sc..lect (CS) - This input signal is used to select the <,PIA. The CS signal must be LOW for selection of the device. Chip select decoding will have to be accomplished with logic external to the chip. GPIA Read/Write Line (R/W) - This signal is generated by the MPU to control register access and direction of data transfer on the data bus. A LOW state on the GPIA Read/Write line allows for the selection of one of seven write-only registers RESET - The active-LOW RESET input is used to initialize the device during power-on start-up. The RESET line will be driven by an external power-on reset circuit. 5-303 II F68488 DMA Control Lines (DMA Grant, DMA Request) - The DMA Request line is used to signal waiting data when Byte In (BI) Byte Out (BO) is set HIGH for a DMA controller. The DMA Request line is set HIGH if either the BI or BO interrupt flag is set in the interrupt status register (ROW) and the corresponding bits in the interrupt mask register (ROR) are set true. The DMA Request line is cleared when the DMA Grant is made true. The DMA Grant line is used to signal the GPIA that the DMA controller has control of the MPU data and address lines. The DMA Grant line must be grounded when not in use. Table 1 Register Access RS2 RS1 0 0 0 0 0 0 0 0 0 0 0 Trigger (TRIG) - The TRI6 pin provides an output corresponding to the GET and fget commands. A hardware or software reset places this output at a LOW level. The trigger output can be programmed HIGH by either of two methods: 0 Enable Input (E) MPU ",2 clock. The E input is normally a derivative of the F68488-GPIA/488 Interface Bus Signals The GPIA provides a set of 18 interface signal lines between the F6800 and the IEEE-488 Standard bus. Signal Lines (IBo-lih) - These bidirectional lines allow for the flow of 7-bit ASCII inierface messages and devicedependent messages. Data appears on these lines in a bit-parallel, byte-serial form. These lines are buffered by the transceivers and applied to the 488 bus (0101-0108). Byte Transfer Lines (DAC, RFD, DAV) - These lines allow for proper transfer of each data byte on the bus between sources and acceptors. The RFD line goes passively true to indicate that all acceptors are ready for data. A source will indicate the data is valid by pulling DAV LOW. Upon the reception of valid data by all acceptors, DAC will go passively true to indicate that the data has been accepted . by all acceptors. Bus Management Lines (ATN, IFC, SRQ, REN, EOI) These lines are used to manage an orderly flow of information across. the interface lines. . Attention (ATN) - The ATN signal is sent true over the interface to disable current talkers and listeners, freeing the 5-304 ROW Command Status R1R Address Status R2R 0 Address Mode R2W 0 0 0 0 0 0 0 0 0 from the controller. It is reset when the GPIA moves out of the device trigger active state (DTAS); i.e., when GET, LADS, or ACDS occur. ROR Interrupt Mask 0 0 2. The trigger output is set upon reception of a GET command Interrupt Status Unused 0 0 1. Setting fget (bit 0 of R3W) by the MPU causes the trigger output to be set. It remains set until the fget bit is programmed LOW or until a reset occurs. Address Switch Enable (ASE) - The ASE output is used to enable the device address switch 3-state buffers to allow the instrument address switches to be read on the MPU bus. 0 Register Symbol Register Title RSO R/W 0 0 0 0 0 Auxiliary Command R3R Auxiliary Command R3W Address Switch' R4R Address R4W Serial Poll R5R Serial Poll R5W Command Pass-Through R6R Parallel Poll R6W Data-In R7R Data-Out R7W 'External to F68488 Fig. 3. Source and Acceptor Handshake X ::J( DAV SOURCE SOURCE VALID I I ALL ROY RFD NONE ROYSOME DAC I I ALL ROY nrr=PT~R I if·-rrm DATA TRANSFER BEGIN SOME ROY I I DATA TRANSFER END ACCEPTOR F68488 signal lines (lBo-lB7). During the ATN active state, devices monitor the 0101 - 0108 lines for addressing or an interface command. Data flows on the 0101- 0108 when ATN is inactive (HIGH). command is sent allowing the device to release hold-off. This will delay a talker until the available information has been processed. Data-In Register (Read-Only) Interface Clear (IFC) - The IFC signal is used to put the interface system into a known quiescent state. L Service Request (SRQ) - The SRQ signal is used to indicate a need for attention in addition to requesting an interruption in the current sequence of events. This indicates to the controller that a device on the bus is in need of service. DlO-017 - correspond to 0101-0108 of the 488-1975 standard and 180-187 of the F68488 Remote Enable (REN) - The REN signal is used to select one of two alternate sources of devices programming data, local, or remote control. END or Identify (EOI) - The EOI signal is used to signal the end of a multiple byte transfer sequence and, in conjunction with ATN, executes a parallel polling sequence. Transmit/Receive Control Signals (T/R1, TjR2) - These two signals are used to control the bus transceivers that drive the interface bus. It is assumed that transceivers equivalent to the F3447 or F3448 will be used, where each transceiver has a separate Transmit/Receive control pin. These pins can support one TTL load each. The outputs can then be grouped as shown in Figure 1 with SRQ hardwired HIGH to transmit. The REN, IFC, and ATN lines are hardwired LOW to receive. The EOI line is controlled by TiR1 through the bus transceiver, allowing it to transmit or receive. The TiR1 line operates exactly as T/R2, except during the parallel polling sequence. During parallel poll, EOI will be made an input by T/R1 while the DAV and lBo-lB7lines are outputs. GPIA Internal Controls & Registers There are 15 locations accessible to the MPU data bus that are used for transferring data to control the various functions of the device and provide current device status. Seven of these registers are write-only and eight are read-only. The various registers are accessed according to the three least significant bits of the MPU address bus and the status of the Read/Write line. One of the 15 registers is external to the device, but an address switch register is provided for reading the address switches. Table 2 shows actual bit contents of each of the registers. Data-In Register R7R - The data-in register is an actual 8-bit storage register used to move data from the interface bus when the device is a listener. Reading the register does not destroy information in the data-out register. The DAC (data accepted) line will remain LOW until the MPU removes the byte from the data-in register. The device will automatically finish the handshake by allowing DAC to go HIGH. In RFD (ready for data) hold-off mode, a new handshake is not initiated until a 01 7 I 01 6 I 015 I 01 4 I 013 I 01 2 I 01 1 01 0 I Data-Out Register R7W - The data-out register is an actual 8-bit storage register used to move data out of the device onto the interface bus. Reading from the data-in register has no effect on the information in the data-out register. Writing to the data-out register has no effect on the information in the data-in register. Data-Out Register (Write-Only) I 007 I 006 I 005 I 004 I 003 I 002 I 001 I 000 000-007 - correspond to 0101-D108 of the 488-1975 standard and lBo-lB7 of the F68488 Interrupt Mask Register ROW - The interrupt mask register is a 7-bit storage register used to select the particular events that will cause an interrupt to be sent to the MPU. The seven control bits may be set independently of each other. If dsel (bit 7 of the address mode register) is set HIGH, CMO (bit 2) will interrupt SPAS or RLC. If dsel is set LOW, CMO will interrupt on UACG, UUCG, and OCAS in addition to RLC and SPAS. The command status register R 1R may then be used to determine which command caused the interrupt. Setting GET (bit 5) allows an interrupt to occur on the Group Execute Trigger Command. The ENO bit (bit 1) allows an interrupt to occur if EOI is true (LOW) and ATN is false (HIGH). The APT bit (bit 3) allows an interrupt to occur indicating that a secondary address is available to be examined by the MPU if apte (bit 0 of the address mode register) is enabled, listener or talker primary address is received, and a Secondary Command Group is received. A typical response for a valid secondary address would be to set msa (bit 3 of the auxiliary command register) and dacr (bit 4 of the auxiliary command register), releasing the OAC handshake. The BI bit (bit 0) indicates that a data byte is waiting in the data-in register. BI is set HIGH when the data-in register is full. The BO bit (bit 6) indicates that the data-out register is empty. BO is set when the data-out register is empty. The IRQ bit (bit 7) allows any interrupt to be passed to the MPU. Interrupt Mask Register (Write-Only) I IRQ IRQ 5·305 I BO I GET I X I APT - Mask bit for IRQ Output CMD END I BI I • F68488 Table 2 Internal Register Contents Bit Mnemonic 7 6 5 3 2 1 0 Intllrrupt Mask Register ROW IRQ BO GET APT CMD END BI Interrupt Status Register ROR INT BO GET APT CMD END BI Command Status Register R1R UACG REM LOK RLC SPAS DCAS UUCG TACS LACS LPAS TPAS hide hlda Register Name 4 Unused R1W Address Status Register R2R ma to 10 Address Mode Register R2W dsel to 10 R3R Chip DAC DAV RFD msa rtl ulpa Iget R3W RESET rfdr leoi dacr msa rtl dacd Iget Address Switch Register R4R UD3 UD2 UD1 ADS AD4 AD3 AD2 AD1 Address Register R4W Isbe dal dat ADs AD4 AD3 AD2 AD1 R5R S8 SRQS S6 Ss S4 S3 S2 S1 R5W S8 rsv S6 S5 S4 S3 S2 S1 Auxiliary Command Register Serial Poll Register ATN apte Command Pass-through Register R6R B7 B6 BS B4 B3 B2 B1 Bo Parallel Poll Register R6W PPR 8 PPR7 PPRs PPRs PPR4 PPR3 PPR2 PPR1 Data-In Register R7R 01 7 01 6 015 01 4 01 3 01 2 01 1 01 0 Data-Out Register R7W 007 006 005 004 003 002 001 000 BO - Interrupt on Byte Output BO GET - Interrupt on Group Execute Trigger GET - A Group Execute Trigger has occurred. APT - Interrupt on Secondary Address Pass-Through APT CMD - Interrupt on SPAS UUCG + UACG) - A byte of data has been output. - An Address Pass-Through has occurred. CMD - SPAS + RLC has occurred. + RLC + dsel (DCAS + + dsel (DCAS + UUCG + UACG) END - Interrupt on EOI and ATN END - An EOI has occurred with ATN = HIGH. BI - Interrupt on Byte Input BI Serial Poll Register R5R/W - The serial poll register is an B-bit storage register that can be both written into and read from by the MPU. It is used for establishing the status byte that the device sends out when it is serial poll enabled. Status may be placed in bits 0 through 5 and bit 7. Bit 6 rsv (request for service) is used to drive the logic that controls the SRO line on the bus telling the controller that service is needed. This same logic generates the service request state (SROS) signal that is substituted in the bit 6 position when the status byte is read by the MPU IBo-IB7. In order to initiate a_n rsv (request for service), the MPU sets bit 6 true (generating an rsv signal) and this in turn causes the device to pull down the SRO line. The SROS signal is the same as rsv when SPAS is false. Bit 6, as read by the MPU, will be the SROS. Interrupt Status Register ROR - The interrupt status register is a 7 -bit storage register that corresponds to the interrupt mode register with an additional bit, INT (bit 7). Except lor the INT bit, the other bits in the status register are set regardless of the state of the interrupt mode register when the corresponding event occurs. The IRO (MPU Interrupt) is cleared when the MPU reads from the register. The INT bit is the logical OR of the other six bits ANDed with the 'respective bit of ROW. Interrupt Status Register (Read-Only) liNT INT I BO I GET I X I APT I CMD I END - A byte has been input. BI - Logical OR of all other bits in this register ANDed with the respective bits in the interrupt mask register 5-306 F68488 5erial Poll Register (Read) I 50· I 5RQ5 I 56 I Address Mode Register (Write-Only) I 55 I 54 I hdle I hdla I X I - 10 - Set to listen-only mode hdle - Hold-off RFD on end Status bits hdla - Hold-off RFD on all data Generate a service request apte - Enable the address pass-through feature 5erial Poll Register (Write) rsv X to Bus is in service request status state I I 10 I - Configure for automatic completion of handshake sequence on occurrence of GET, UACG, UUCG, SDC, or DCl commands Status bits SRQS - 50 to dsel SI-Sa [ I dsel rsv I 56 55 I 54 I 53 I 52 I 51 I Parallel Poll Register R6W - This register will be loaded by the MPU, and the complement of the bits in this register will be delivered to the instrument bus (IBo-IB7) during PPAS (Parallel Poll Active State). This register powers up in the PPO (Parallel Poll No Capability) state. The reset bit (auxiliary command register bit 7) will clear this register to the PPO state. The parallel poll interface function is executed by this device using the PP2 subset (Omit Controller Configuration Capability). The controller cannot directly configure the parallel poll output of this device. This must be done by the MPU. The controller will be able to configure the parallel poll indirectly by issuing an addressed command that has been defined in the MPU software. apte I Set to talk-only mode Address 5tatus Register R2R - The address status register • is not a storage register, but is simply an 8-bit port used to couple internal signal modes to the MPU bus. The status flags represented here are stored internally in the logic of the device. These status bits indicate the addressed state of the talker/listener as well as flags that specify whether the device is in the talk-only or listen-only mode. The ma signal is true when the device is in: TACS - Talker Active State TADS - Talker Addressed State lACS - Listener Active State lADS' - Listener Addressed State SPAS - Serial Poll Active State Parallel Poll Register (Write-Only) I PPo I PP7 I PP6 I PP5 I PP4 I PP3 I PP2 ATN - Bit 4 contains the condition of the attention line PPI Address 5tatus Register (Read-Only) Bits delivered to bus during Parallel Poll Active State (PPAS) I ma I to I 10 I ATN I TAC5 I lAC5 I LPA5 I TPA5 I Register powers-up in the PPO state. Parallel Poll is executed using the PP2 subset. Address Mode Register R2W - The address mode register is a storage register with six bits for control: to, 10, hide, hlda, dsel, and apte. The to bit (bit 6) selects the talker/listener and addresses the device to talk only. The 10 bit (bit 5) selects the talker/listener and sets the device to listen only. The apte bit (bit O) is used to enable the extended addressing mode. If apte is set lOW, the device goes from the TPAS (Talker Primary Address State) directly to the TADS (Talker Addressed State). If apte is set HIGH and the secondary address is valid, set msa true. The hlda bit (bit 2) holds off RFD (Ready for Data) on all data until rfdr is set true. The hide bit (bit 3) holds off RFD on EOI enabled (lOW) and ATN not enabled (HIGH). This allows the last byte in a block of data to be continually read as needed. Writing rfdr true (HIGH) will release the handshake. ma - My address has occurred. to - The talk-only mode is enabled. 10 - The listen-only mode is enabled. ATN - The Attention command is asserted. TACS - GPIA is in the Talker Active State. lACS - GPIA is in the Listener Active State. lPAS - GPIA is in the Listener Primary Address~d State. TPAS - GPIA is in the Talker Primary Addressed State. Address 5witch Register R4R - The address switch register is external to the device. There is an enable line (ASE) to be used to enable 3-state drivers connected between the address switches and the MPU. When the MPU addresses the address switch register, the enable line directs the switch information to F68488 be sent to the MPU. The five least significant bits of this 8-bit register are used to specify the bus address of the device, and the remaining three bits may be used at the discretion of the user. The most probable use of one or two of the bits is for controlling the listen-only or talk-only functions. Address Switch Register (Read-Only) Auxiliary Command Register R3R/W - Bit 7, reset, initializes the device to the following states (reset is set true by external RESET input pin and by writing into the register from the MPU): SIDS - AIDS - Acceptor Idle State TIDS - Talker Idle State LIDS - Device Address LACS - User Definable Bits PPIS - PUCS When this register is addressed, the ASE pin is set to allow external address switch information to be read from a bus device. Address Register R4W - The address register is an 8-bit storage register. The purpose of this register is to carry the primary address of the device. The primary address is placed in the five least significant bits of the register. If external switches are used for device addressing, these are normally read from the address switch register and then placed in the address register by the MPU. The AD1-AD5 bits (0 ~ 5) are for the device address. The Isbe bit (bit 7) is set to enable the dual primary addressing mode. During this mode, the device will respond to two consecutive addresses; one address with AD1 equal to 0 and the other address with AD1 equal to 1. For example, if the device address is $OF, the dual primary addressing mode would allow the device to be addressed at both $OF and $OE. The dal bit (bit 6) is set to disable the listener and the dat bit (bit 5) is set to disable the talker. This register is cleared by the RESET input only (not by the reset bit of the auxiliary command register, bit 7). When ATN is enabled and the primary address is received on the IBo-iih lines, the F68488 will set bit 7 of the address status register (MA). This places the F68488 in the TPAS or LPAS. When ATN is disabled, the GPIA may go to one of three states: TACS, LACS or SPAS. I dal I dat I ADs I AD4 AD3 AD2 Isbe - Enable dual primary addressing mode dal - Disable the listener dat - Disable the talker AD1-AD5 - Listener Idle State Listener Active State Parallel Poll Idle State Parallel Poll Unaddressed to Configure State - Parallel Poll No Capability The rfdr (release RFD handshake) bit (bit 6) allows for completion of the handshake that was stopped by RFD (Ready For Data) hold-off commands hlda and hide. The fget (force group execute trigger) bit (bit 0) has the same effect as the GET (Group Execute Trigger) command from the controller. (IEEE STD 488 p. 39.) The rtl (return to local) bit (bit 2) allows the device to respond to local controls and the associated device functions are operative. The dacr (release DAC handshake) bit (bit 4) is set HIGH to allow DAC to go passively true. This bit is set to indicate that the MPU has examined a secondary address or an undefined command. The ulpa (upper/lower primary address) bit (bit 1) will indicate the state of bit 0 on the D101-D108 bus lines at the time the last primary address was received. This bit can be read but not written by the MPU. The msa (valid secondary address) bit (bit 3) is set true (HIGH) when TPAS (Talker Primary Addressed State) or LPAS (Listener Primary Addressed State) is true. The device will become addressed to listen or talk. The primary address must have been previously received. Address Register (Write-Only) I Isbe PPO Source Idle State Primary device address, usually read from address switch register The RFD, DAV, and DAC (Ready for Data, Data Valid, and Data Accepted) bits assume the same state as the corresponding signal on the F68488 package pins. The MPU may only read these bits. These signals are not synchronized with the MPU clock. The dacd (data accept disable) bit (bit 1) set HIGH by the MPU will prevent automatic handshake on addresses or commands. The dacr bit is used to release the handshake. Register is cleared by RESET input pin only. '5-308 F68488 The feoi (forced end or identify) bit (bit 5) tells the device to send EOI LOW with the next data byte transmitted. The EOI line is then returned HIGH after the next byte is transmitted. NOTE: The following signals are not stored but revert to a false (LOW) level one clock cycle (MPU <1>2) after they are set true (HIGH): These are five major address commands. REM shows the remote/local state of the talker/listener. The RLC bit (bit 3) is set whenever a change of state of the remote/local flip-flop occurs and reset when the command status register is read. 1. rfdr 2. feoi 3. dacr The DCAS bit (bit 1) indicates that either the device clear or selected device clear has been received, activating the device clear function. These signals can be written but not read by the MPU. Auxiliary Command Register The SPAS bit (bit 2) indicates that the SPE command has been received, activating the device serial poll function. The UACG bit (bit 7) indicates that an undefined address command has been received and, depending on programming, the MPU decides whether to execute or ignore it. reset - Initialize the chip to the following status: The UUCG bit (bit 0) indicates that an undefined universal command has been received. 1. All interrupts cleared 2. Following bus states are in effect: SIDS, AIDS, TIDS, LIDS, LOCS, PPIS, PUCS, and PPO Command Status Register (Read) I UACG I REM I LOK I X I RlC I SPAS I DCAS IUUCG I 3. Bit is set by RESET input pin. UACG - Undefined Address Command DAC - Corresponds to Data Accepted signal on F68488 package pins DAV - Corresponds to Data Valid signal on F68488 package pins RFD - Corresponds to Ready For Data signal on F68488 package pins REM - Remote Enabled LOK - Local Lockout Enabled RLC - Remote Local State Changed SPAS - Serial Poll Active State is in effect. DC AS - Device Clear Active State is in effect. msa - If GPIA is in LPAS or TDAS, setting msa will force GPIA to LADS or TAOS. UUCG - Undefined Universal Command rtl - Return to local if local lockout is disabled ulpa - State of LSB of the address received on the 0101-8 bus lines fget - Force Group Execute Trigger Command from controller has occurred. rfdr - Complete handshake stopped by RFD hold-off Command Pass-Through Register R6R - The command pass-through register is an 8-bit port with no storage. When this port is addressed by MPU, it connects the instrument data bus (TBO-TB7) to the MPU data bus DBo-DB7. This port can be used to pass commands and secondary addresses, that are not automatically interpreted, through to the MPU for inspection. feoi - Set EOI true, clears after next byte transmitted Command Pass-Through Register (Read Only) dacr - MPU has examined an undefined command or secondary address. dacd - Prevents automatic handshake on addresses or commands Command Status Register R1 R - The command status register flags commands or states as they occur. These flags or states are simply coupled onto the MPU bus from internal storage nodes. BO An 8-bit port used to pass commands and secondary addresses to the MPU that are not automatically interpreted by the GPIA. 5-309 I F68488 Absolute Maximum Ratings Voltage 01 any pin relative to ground Operating Temperature (Ambient) Storage Temperature (Ambient) Power Dissipation DC Characteristics Vee = 5.0 V Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating cond"ions for extended periods may affect device rellablity. -0.3 V, +7.0 V O'C, +70°C -55°C, +150°C 1W ±5%, VSS = 0, TA = 0 to + 70°C. unless otherwise noted Characteristic Min VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage Symbol Typ Max Unit Condition V 0.8 V liN Input Leakage Current 1.0 2.5 /LA VIN = 0 to 5.25 ITSI 3-State (OFF State) Input Current Do-D7 2.0 10 /LA VIN = 0.4 to V ILoad ILoad = = 0.4 0.4 V ILoad ILoad = 1.6 mA = 3.2 mA 10 /LA VOH = 2.4 V VOH VOL Output HIGH Voltage DO-D7 Other Outputs 2.4 2.4 Output LOW Voltage Do-D7 IRQ V 2.4 V -205 /LA -200/LA ILOH Output Leakage Current (OFF State) IRQ 1.0 Po Power Dissipation 600 CIN Input Capacitance Do-D7 All Other Inputs 12.5 7.5 pF VIN = 0, TA 1 = 1.0 MHz = 25°C, Output CapaCitance IRQ 5.0 pF VIN = 0, TA f = 1.0 MHz = 25°C. COUT 5·310 mW F68488 Bus Timing Characteristics Read (Figure 4) Characteristic Symbol Min Typ Max Unit 25 p..s teyeE Enable Cycle Time 1.0 PWEH Enable Pulse Width, HIGH 0.45 p..s p..s PWEL Enable Pulse Width, LOW 0.43 tAS Set-up Time, Address and R/W Valid to Enable Positive Transistion 160 tOOR Data Delay Time ns 320 tH Data Hold Time 10 tAH Address Hold Time 10 tEr, tEl Rise and Fall Time for Enable Input ns ns ns 25 ns Write (Figure 5) 1.0 Enable Cycle Time teyeE p..s PWEH Enable Pulse Width, HIGH 0.45 PWEL Enable Pulse Width, LOW 0.43 p..s tAS Set-up Time, Address and R/W Valid to Enable Positive Transistion 160 ns tosw Data Set-up Time 195 ns tH Data Hold Time 10 ns tAH Address Hold Time 10 tEr, tEl Rise and Fall Time for Enable Input Fig. 4 Bus Read Timing Characteristics Fig. 5 Bus Write Timing Characteristics (Write Information into GPIA) ENABLE cs, ENABLE RS, CS, RM R/W DATA BUS DATA BUS 5-311 p..s ns 25 (Read Information from GPIA) RS, 25 ns F68488 Ordering Information P Speed Order Code Temperature Range 1.0 MHz F68488P,S F68488CP,CS F68488DL F68488DM O"C -40"C -55°C -55°C 1.5 MHz F68A488P,S F68488CP,CS O"C to +70"C -40°C 10 +85°C 2.0 MHz F68B488P,S to to to to +70"C +85°C +85°C +125°C O"Cto +70°C = Plastic package, S = CER-DIP package 5-312 I [!] I INTRODUCTION ~2 IORDERING AND PACKAGE ~ INFORMATION ICIJIF8 MICROCOMPUTER FAMILY 101CONTROLLER FAMILY I ~ IF6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY I [!J I ROM PRODUCTS ISOFTWARE ~9 DEVELOPMENT SYSTEMS AND L!J I[!QJ I APPLICATIONS I [I!J I I ~ I SALES OFFICES RESOURCE AND TRAINING CENTERSI Section 6 III Microprocessor Family F=AIRCHILD A Schlumberger Company General Also produced using 13L technology are the F9414 Data Encryption Set and the F9423 FIFO Buffer Memory. Fairchild has utilized bipolar Isoplanar Integrated Injection Logic (13L) VLSI proven technology to develop very fast 16-bit microprocessors. The F9445 is available now. Typical execution times for the F944520DM (20 MHz clock frequency over a - 55'C to + 125'C operating temperature range) are: Add in 0.3 p,S and a full 16 x 16 bit in 3.5 p,s. The high speed multiply and divide times of the F9445 make this device particularly well suited for real time control and signal processing applications. Instruction Set Each 16-bit F9445 instruction word is divided into smaller sections, or fields, that specify the operation code and related actions, the CPU register conditions and registers, and the I/O device codes, and that derive memory location effective addresses. The instruction set consists of the following types of instructions: Since the F9445 has been implemented in bipolar injection logic, it maintains full high speed performance at high temperature. Thus, it is an excellent processor for use in harsh environments. The F9445 is available in either dual-in-line (DIP) or JEDEC chip carrier packages. The processor is available fully screened per MILSTD-883 Method 5004. 1. Arithmetic and logic instructions 2. Memory reference instructions 3. Stack manipulation instructions 4. I/O instructions The F9445, which is supported by a family of peripheral chips, can address up to 64K words of memory, directly address 62 I/O devices, handle 16 levels of priority interrupt, and perform fast direct memory access. It supplies the signals necessary for operation in multiprocessor environment, and supports minicomputer· like console functions, including internal self-testing. The support devices, like the processor, are implemented in bipolar 13L technology; their operating temperature range is also - 55'C to + 125'C. 5. Control instructions The F9445 instruction set is shown on the following pages. The assembly·language format of each instruction is shown on the left, followed by the name of the instruction and a symbolic description of its action. The corresponding bit pattern for each instruction is shown on the right side of the page. Fairchild provides a full range of design support for the F9445 16·bit processor. The Fairchild System-I (FS-I) Microprocessor Development Station provides a means for developing F9445 software. This system is fully supported by the IMDOS operating system. High level language compilers are currently available in FORTRAN and PASCAL, and in the future DOD Standard JOVIAL J73. The EMUTRAC option to the FS-I provides full in· circuit emulation and tracing of the F9445 system; it also provides simultaneous and interactive hardware and software development and debugging. Assembly·language mnemonics and binary representations for instruction optional parts (within square brackets) and accumulator codes, to be inserted at the indicated places in the instructions, are shown following each group of instructions. The required separator, indicated in the assembly· language formats by a square (0), may be entered as any number or combination of space or tab characters or a comma for the macro·assembler; the separator must be a Single space for the PEPBUG·45 program. A complete F9445 microcomputer is available in the PEP-45. This powerful single board microcomputer is an excellent approach to becoming familiar with the F9445 family. The PEP-45 is useful as development tool, prototyping device, or as a standalone microcomputer. The PEP-45 has two serial I/O ports, onboard EPROM programmers, and meets IEEE bus standards. Fairchild is currently developing the F9450 16·bit microprocessor. This bipolar 13L VLSI device implements the full MIL-STD-1750A Instruction Set Architecture in a single monolithic microprocessor. 6·3 13L Microprocessor Families Descriptions Following is data that describes the members of the F9445 microprocessor family. 16-BIT I'L BIPOLAR MICROPROCESSOR FAMILY ORGANIZATION F9450 SINGLE·CHIP BIPOLAR MICROPROCESSOR F9445 16·BIT BIPOLAR MICROPROCESSOR F9443 FLOATING POINT PROCESSOR F9451 MEMORY MANAGEMENT UNIT F9444 F9452 BLOCK PROTECT RAM MEMORY MANAGEMENT AND PROTECTION UNIT F9446 DYNAMIC MEMORY CONTROLLER F9414 DATA ENCRYPTION SET F9447 I/O BUS CONTROLLER F9423 FIFO BUFFER MEMORY F9446 PROGRAMMABLE MULTIPORT INTERFACE F9449 MULTIPLE DATA CHANNEL CONTROLLER F8470 CONSOLE CONTROLLER 6·4 F9445 Instruction Set Memory Reference Instructions JMPD[@] displacement [,index] 10 9 Jump. Jump to effective address. 10 0 0 0 10 0 0 0 10 0 0 10 0 0 JSRD[@] displacement [,index] 0 1@1 INDEX ISZD[@] displacement [,index] STADAC, [@] displacement [,index] 10 1 @I INDEX DISPLACEMENT 1 @I INDEX DISPLACEMENT AC 1 @I INDEX DISPLACEMENT ACd 0 10 10 10 4 E1 0 LDBDACs, ACd, 9 6 Load Byte. (Byte Pointefl - ACd 8-15, 0- ACd 0-7; LSB of byte pointer in ACs selects high-order byte if 0, low-order byte if 1. 10 STBDACs, ACd o Store Byte. ACd 8-15 - I Byte Pointer!. 0 15 ~ 14 15 11 12 13 14 15 AC s 11 13 12 14 15 11 12 11 13 14 15 12 13 14 15 15 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 o 0 0 0 0 AC s 0 14 DISPLACEMENT 10 AC 0 Store Accumulator. AC - I EA I. 13 INDEX 9 0 12 1 @I 0 0 Load Accumulator. (EAI - AC. 11 1@I 9 LDADAC, [@] displacement [,index] 13 DISPLACEMENT DSZD[@] displacement [,index] Decrement and Skip if Zero. Decrement lEAl; if zero, skip next instruction. 12 INDEX 0 Increment and Skip if Zero. Increment (EAI; if zero, skip next instruction. 10 9 3 Jump to Subroutine. Jump to subroutine at effective address: then return to PC saved in AC3. 11 DISPLACEMENT 15 Effective Address Codes Accumulator Codes Mnemonics Bits @ Index 5 6 7 Effective Address Omitted Omitted Omitted Omitted @ @ @ @ 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 EA EA EA EA EA EA EA EA 1 2 3 0 1 2 3 1 1 1 1 Bits = D; direct page zero = CA + 0; relative to PC = AC2 + D; indexed by AC2 = AC3 + D; indexed by AC3 = (D I; indirect through page zero = 1CA + D I; indirect relative to PC = (AC2 + D I; indirect relative to AC2 = (AC3 + D I; indirect relative to AC3 Mnemonic 8 9 AC 0 0 0 0 1 1 0 ACO AC1 AC2 AC3 1 2 3 1 1 Relative Displacement Notes 0= Displacement; specified as absolute in current radix or relative via mnemonics. CA == Current address or PC-l EA == Effective address. I XX I == Contents allocation XX. e.g. ,EA, == Contents of effective address. @ = Indirect address bit. Byte Pointer 132K,'= 16 bits of ACs. Byte Pointer i64K, = 17 bits of Carry and ACs; upper 32K accessed when Carry = 1, lower 32K when Carry = O. 0= Required separator. 6-5 Mnemonic .+D .-D Meaning Current location plus displacement Current location minus displacement Note o = Displacement in current radix. F9445 Instruction Set Arithmetic and Logic Instructions COM[carry][shift][#]OACs, ACd [,skip] Complement. ACs - ACd. NEG[carry][shlft][#]OACs, ACd [,skip] Negate. -ACs - ACd; affects Carry and Overflow flags. MOV[carry][shift][#]OACs, ACd [,skip] Move. ACs - ACd. INC[carry][shift][#]OACs, ACd [,skip] Increment. ACs + 1 - ACd; affects Carry and Overflow flags. ADC[carry][shift][#]OACs, ACd [,skip] Add Complement. ACs + ACd - ACd; affects Carry and Overflow. SUB[carry][shift][#]OACs, ACd [,skip] Subtract. ACd - ACs - ACd; affects Carry and Overflow. ADD[carry][shift][#]OACs, ACd [,Skip] Add. ACs + ACd - ACd; affects Carry and Overflow. AND[carry][shift][#]OAC s, ACd [,Skip] And. ACs 1\ ACd - ACd. Bits Omitted Z 0 C 10 11 0 0 1 1 ACd 0 0 ACd 0 0 ACs ACd 0 ACs ACd 0 8 8 0 11 1 ACs 0 8 ACd ACs ACd ACs ACd 9 9 8 0 10 11 12 10 11 12 10 11 12 10 11 12 9 10 11 12 8 9 10 11 12 13 8 9 10 11 12 SHIFT 1 CARRY 1 # 15 14 15 SKIP 13 14 15 SKIP 13 14 15 SKIP 13 14 15 SKIP 13 14 15 SKIP 13 14 15 SKIP 0 1 SHIFT 1 CARRY 1 # 1 6 14 SKIP 1 SHIFT 1 CARRY 1 # 1 6 0 11 1 13 SHIFT 1 CARRY 1 # 0 6 4 2 0 11 1 9 8 0 ACd ACs 12 SHIFT 1 CA~RY 1 # 3 0 11 1 9 8 11 1 ACs 11 SHIFT 1 CARRY 1 # 0 0 11 1 10 SHIFT 1 CARRY 1 # 6 0 11 1 9 0 1 SHIFT 1 CARRY 1 # 1 13 14 15 SKIP Shift Operation Base Carry Values Mnemonic 6 0 11 1 ACs 0 1 0 1 Bits Carry Value Used as Base Mnemonic 8 9 Function Omitted L R S 0 0 1 1 0 1 0 1 No shift Left rotate Right rotate Swap bytes Current Carry Zero One Complement of current Carry I Skip Condition Codes Load/No-Load Condition Bits Mnemonic Bit 12 Omitted 0 # 1 Note # = Load/No-Load bit. 0= Required separator. Operation Load result in destination accumulatbr Do not load result Mnemonic Omitted SKP SZC SNC SZR SNR SEZ SBN A No-Load·No Skip instruction is interpreted as a trap if the Trap Enable "flip-flop is set. 6-6 13 14 15 Skip Condition 0 0 0 Do not skip Always skip Skip if zero Carry Skip if non-zero Carry Skip if zero result Skip if non-zero result Skip if either Carry or result zero Skip if both Carry and result non-zero 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I F9445 Instruction Set Arithmetic and Logic Instructions (Continued) 0 ORDACs• ACd Or. ACs V ACd - ACd. 0 + (AC1 x AC21 - ACO, AC1. MULS 2 + (AC1 x AC21 - ACO, AC1. DIV AC2, quotient - AC1, remainder - ACO; Carry and Overflow = 1 if overflow occurs, Carry = 0 if not. DIVS quotient - AC1, remainder - ACO; Carry and Overflow = 1 if overflow occurs, Carry = 0 if not. NORM Normalize. Move the 32 bits in (ACO, AC11 to the left until high-order bit of ACO = 1; number of steps required is subtracted from AC2; affects Overflow flag. SLLD Shift Logically Left. Shift the 32 bits in (ACO, AC11 logically left n times; zeroes shifted to LSB of AC1; n is contents of AC2 (1 :; n :; 311SALD Shift Arithmetically Left. Shift the 32 bits in (ACO, AC11 to the left n times; zeroes shifted to LSB of AC1; set Overflow flag on first sign change; n is contents of AC2 (1 :; n :; 311. SLRD Shift Logically Right. Shift the 32 bits in (ACO, AC11 logically right n times; zeroes shifted to MSB of ACO; n is contents of AC2 (1 :; n :; 311. 5 8 6 1 4 5 3 3 4 6 4 8 6 0 3 4 3 4 10 0 0 0 3 4 10 0 0 0 3 [£ 4 3 4 10 0 0 6·7 0 0 0 6 9 5 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 8 9 10 11 12 13 14 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 0 0 0 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 6 6 0 0 8 0 6 10 0 1 0 0 10 9 ACd 8 6 10 0 Signed Divide. (ACO, AC11/AC2, 3 10 0 Unsigned Divide. (ACO, AC111 4 0 0 Signed Multiply. ACO 3 AC. 10 MUL Unsigned Multiply. ACO 2 6 8 0 15 15 15 15 15 15 15 15 15 F9445 Instruction Set Arithmetic and Logic Instructions (Continued) SARD 3 Shift Arithmetically Right. Shift the 32 bits in (ACO, AC1) arithmetically to the right n times; the MSB (sign I of ACO is extended; n is contents of AC2 (1 s: n s: 31 I. 10 Skip on Not Overflow. Skip next instruction if Overflow = 0; then reset Overflow flag to O. 10 SKNV 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 5 0 0 0 0 0 0 0 15 15 Stack Instructions PSHADAC Push Accumulator. SP + 1 - SP, AC - (SP). POPADAC Pop Accumulator. (SPI - AC, SP-1 - SP. PSHF 0 10 AC 0 AC 0 POPF 10 11 12 13 14 0 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 8 0 10 0 Push Flags. SP + 1 - SP, PSW - (SPI. 0 0 10 6 8 0 0 6 8 9 10 11 12 13 14 Pop Flags. (SPI - PSW, SP-1 - SP. 10 0 0 0 0 0 0 0 0 0 Pop PC and Jump. (SP) - PC, SP-1 - SP. 10 0 0 0 POPJ PSHR 3 0 Push Return Address. SP + 1 - SP, CA +2 -(SPI. 10 TOPRDAC Read Top of Siack. (SPI - AC. TOPWDAC Write Top of Stack. AC - (SPI. MTSPDAC Move to Stack POinter. AC - SP. 4 6 0 0 8 8 3 10 AC 0 AC 0 0 0 4 AC 10 6-8 5· 0 10 11 12 13 14 0 0 0 0 0 9 10 . 11 12 13 14 0 0 0 0 0 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 0 0 0 0 0 9 9 5 10 9 0 0 6 8 0 0 0 15 15 15 15 15 15 15 15 15 F9445 Instruction Set Stack Instructions (Continued) MFSPDAC Move From Stack Pointer. SP - AC. 0 MTFPDAC Move to Frame Pointer. AC - FP. 0 AC 0 0 0 0 3 0 6 3 4 AC Decrement Stack Pointer. SP-1 - SP. 12 13 14 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 9 10 11 12 13 14 0 0 0 0 0 0 11 12 13 14 0 0 0 0 0 6 9 10 11 12 13 14 0 0 0 0 0 0 0 0 0 1 0 0 0 3 4 6 6 0 0 1 11 0 10 0 DSP 0 10 0 9 0 0 FP, then the 5-word return block is popped to (Carry', PC1-151, FP, AC3, AC2, AC1, and ACO, respectively. 0 9 0 3 1 0 6 0 RET Return. SP is loaded with contents of 0 0 Save. Push the 5-word return block (ACO, AC1, AC2, FP [Carry', AC31-15[1 on stack, then load FP and AC3 with contents of SP. 0 0 1 SAY 6 AC 0 1 MFFPDAC Move From Frame Pointer. FP - AC. 4 3 0 1 0 0 9 10 11 12 13 14 0 0 0 0 0 0 9 10 11 12 13 14 15 15 15 15 15 15 Noles SP ~ Stack Pointer FP = Frame Pointer PSW ~ Program Stalus Word CA = Current Address I PC-11 *In 64K-word mode, Carry bit is not involved in SAV and RET and is replaced by AC30 and PCa. respectively. I/O Instructions NIO[ *lDdevice 0 No Data Transfer. 1 SKPIID device DIA[ * ]D AC, device Data In From Register A. A - AC. 0 4 1 0 X 0 0 4 5 6 X X 4 0 AC 0 1 6-9 6 X 0 Skip on Busy/Done Flags. Skip next instruction if Busy/Done meets test condition. 2 8 0 * 9 8 10 • 5 6 0 0 * 11 12 13 14 15 DEVICE CODE 9 8 15 DEVICE CODE 10 11 12 13 14 DEVICE CODE 15 F9445 Instruction Set I/O Instructions (Continued) DOA[ * ]0 AC, device 0 Data Out to Register A. AC - A. DIB[ *]0 AC, device 2 DOB[ * PAC, device DIC[ * ]0 AC, device 3 2 DOC[ *]D AC, device 4 10 c. 5 9 5 10 11 5 9 10 11 8 9 10 8 0 12 12 11 12 9 10 11 * Busy/Done Control Codes 12 * .Busy/Done Test Codes Bits Bits Mnemonic 8 9 Omitted S 0 0 0 1 C 1 0 P 1 1 Operation Does not affect Busy and Done flags START the device by setting Busy = 1 and Done = 0 CLEAR both Busy and Done to 0 and idle the device PULSE the device. Its effect depends on device 8 9 Test Condition BN BZ ON DZ 0 0 1 1 0 1 0 1 Busy is Non-Zero Busy is Zero Done is Non-Zero Done is Zero Device Code Symbols Note. X * Mnemonic = Don't care. = Busy/done control code. • = Busy/done test code. D = Required separator. Mnemonic Octal TTl TTO PTR PTP RTC LPT SMS CPU 10 11 12 13 14 17 61 77 Meaning TTY input TTY output Reader Punch Real-time clock Line printer SMS disk drive Console Refer to "Control Instructions" regarding use of device code 77. 6-10 13 14 13 14 13 14 13 14 OEVICECOOE Note Device code = any number in the current radix (octal only for PEPBUG 451 between 0 and 77 octal except reserved codes 0 and 1. also may be the following standard mnemonics lor other user-defined mnemonics with the macro-assembler I: t' 14 15 15 15 15 OEVICECODE * 6 13 DEVICE COO'E * 6 12 OEVICECODE 8 0 AC 10 11 * 0 4 10 DEVICE CODE 8 0 4 9 * 6 AC 0 Data Out to Register C. AC - 0 0 AC 3 8 6 4 3 10 0 Data In From Register C. C - AC. 5 0 AC 10 0 Data Out to Register B. AC - B. 4 AC 0 Data In From Register B. B - AC. 3 10 15 F9445 Instruction Set Control Instructions INTEN Interrupt Enable. 1 - INTON; allows one more instruction to be executed before 1 - INTON. Alternate assembler format: NIOSDO, CPU INTDS °- INTON. Interrupt Disable. Alternate assembler format: NIOCDO, CPU READSDAC Read Console Switch Register. SW-AC. Alternate assembler format: DIADAC, CPU INTADAC 0 3 4 5 6 10 X X 0 0 0 3 4 5 6 10 X X 0 0 0 3 4 0 Interrupt Acknowledge. The device code of the highest priority device requesting interrupt is loaded to bits 10-15 of AC. Alternate assembler format: DIB DAC, CPU MSKODAC Mask Out. Enables specific devices to request interrupts. Alternate assembler format: DOBDAC,CPU IORST HALT Halt the Processor. Only console operations are recognized. Alternate assembler format: DOC DO, CPU SKP.DCPU Skip on Interrupt-On Flag. Skip next instruction if the INTON flag fulfills the specified test conditions. WAIT Wait for Interrupt. Console, interrupt, and data channel request are recognized. 4 2 0 4 3 AC 10 2 X 10 X X 0 3 4 10 0 0 4 10 6-11 15 8 9 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 0 8 9 0 5 6 8 9 0 0 0 0 9 6 6 10 14 0 6 4 13 6 0 X 12 0 4 3 11 5 X X 10 0 0 0 9 0 0 0 AC 10 0 110 Reset. Clear busyldone and interrupt enable flags of all 1/0 devices. Alternate assembler format: DIC COO, CPU AC 10 8 0 0 9 8 0 0 6 8 9 0 0 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 • 6 0 F9445 Instruction Set Control Instructions (Continued) TRAP 6 Trap. CA - 466, (4761 - PC. 11 1 X X X X X 8 X X X 0 0 X ETRP Enable Trap Instruction. Default state by MR. 10 Disable Trap Instruction. 10 Enable 64K-words mode. [0 0 Disable 64K-words mode. Default state by MR. 10 0 DTRP 6 8 9 0 E64K D64K 0 Interrupt-On (INTON) Control Codes X 10 11 0 0 10 0 12 13 14 15 0 0 0 12 13 14 15 0 0 0 11 12 13 14 0 0 0 0 10 11 12 13 14 0 0 0 0 0 10 11 12 13 14 15 0 0 0 0 0 1J • Interrupt-On (INTON) Test Codes Bits Mnemonic 8 9 Operation Omitted S C P 0 0 1 1 0 1 0 1 No effect Set INTON = 1 Reset INTON = 0 No effect Notes X = Don't care. * 0 11 X 15 15 as shown; however, with READS, INTA, MSKO, 10RST or HALT, the alternate I/O mnemonics, which are shown for each instruction, may be used to control the Interrupt-On flag according to the "Interrupt-On Control Codes" table. Bits • 0 6 3 Most of the Control instructions are a subset of I/O in,structions using device code 77 octal ("aIl1s," mnemonic: CPU); in device code 77 instructions, the Busy/Done control affects the Interrupt-On flag instead of the Busy and Done flags. Use of the Control mnemonics sets the Interrupt-On flag (via bits 8 and g) * 0 10 = Interrupt~On Control ::::: Interrupt-On Test. Required separator. o ::: 6-12 Mnemonic 8 9 Test Condition BN BZ ON DZ 0 0 1 1 0 1 0 1 Skip on INTON Skip on INTON Reserved Reserved =1 =0 F9414 4-Chip Data Encryption Set I=AIRCHILD A Schlumberger Company Microprocessor Product Description The Fairchild F9414 4-Chip Data Encryption Set consists of four similar 40-pin PL@ LSI devices (the 9414-1, 9414-2,9414-3, and 9414-4), and is designed to implement the National Bureau of Standards data encryption standard (DES) algorithm (FIPS-46). The set uses a 56-bit key word to encipher or decipher a 64-bit word that is stored in a bytes; 2 bits of each byte are distributed to each of the four chips. • • • • • • • • • • High Throughput LSTTL Input/Output Single Clock Parity Testing Simultaneous Load and Output Data Cipher Feedback and Block Chaining 3-State Data Buffers Single 5V Power Supply 5 MHz Operation Typical Data Throughput - 4.8 Per 84-Blt Word ,.5 The major elements of each chip include a pair of data registers, four a-bit shift (key) registers, control logic, and two 64-word by 4-bit read-only memories (ROMs). The F9414 encryption set has passed the NBS functional validation test. Signal Functions Connection Diagram Fa CP F7 K. F. K, Fs K, F. K, F, Co F, C, F, C, IINJ P'N ! ! F, INPUT GND 0lN1 DIN1 'N. :: :::"UT ) SELECTION INPUTS Fa F7 Fa DOUT') DATA BIT OUTPUTS D OU70 P, P, Px Py ) e·BIT SELECTION OUTPUT OUTPUT Fx Fy ) E·BIT SELECTION INPUT :: Pa P7 GND Pa C. C, C, P'N D INO S'N SoUT P7 °OU11 Pa °OUTO Ps Px p. Py P, Fy P, Fx P, DATA BIT INPUTS D P, 'OUT Pa I F, F, 'OUT CP Vee GND "NJ -------POWER 6-13 } MODE CONTROL INPUT PARITY BIT INPUT PARITY BIT OUTPUT CLOCK INPUT F9414 Signal Descriptions bytes; bit 8 of each byte is parity. Bits 1 through 4 go to both chip 1 and 2; bits 4 through 7 go to chips 3 and 4. The four chips together also store the 64-bit plaintext or ciphertext word. The chips have separate data inputs and outputs, so the block of data to be processed can be input as the previous block is being output. This overlap permits the processing of a 64·bit block in 24 clock pulses at a 5 MHz typical clock frequency. This results in data throughput of 13.3 MHz (75 ns) per bit, or 200 kHz (4.8 I's) per 64-bit word. The F9414 input and output signals are described in table 1. Functional Description The set operates with a 56·bit key word to encipher or decipher a 64-bit data word that is stored in8 bytes; 2 bits of each byte are distributed to each of the four chips (see figure 1). The key consists of 64 bits in 8 Table 1 F9414 Signal Descriptions Mnemonic Pin No. Name Description F, . Fa 8,7,6,5,4, 3,2,1 Interconnect Lines Input signals; interconnect with p,·p s to implement the permutation function, P, of the algorithm. P, . Pa 21 ·28 Interconnect Lines Output signals; interconnect with F,·Fs to implement the permutation function, P, of the algorithm. K, . K4 36·39 Keyword Input signal for 4 bits of the keyword. DINO' DIN' 12, 11 Data In Data inputs for 2 bits of the data word. SIN 13 Select In Input signal that selects the exclusive·OR function. SOUT 14 Select Out Input signal that selects the output function. DOUTO, DOUT1 16, 15 Data Out Output lines for the data bits. Px , Py 17, 18 E·Bit Select Output signal; E·bit selection for interconnection with Fx, Fy. Fx, Fy 20, 19 E·Bit Select Input Signal; E·bit selection for interconnection with Px, Py. Co' C" C2 35, 34, 33 Control Input Signals used to control the F9414 in one of five modes. PIN 32 Parity In Parity bit input signal POUT 31 Parity Out Parity bit output signal CP 40 Clock Input signal Vce 29 Power +5 V IINJ 9 Power Injection current input GND 10 Ground o V reference. 6·14 ± 5% power supply F9414 Figure 1 4-Chip Encryption Set KEY·IN BYTE DATA·IN BYTE BITS K1,2,3,4 K1, 2,3. 4 BITS I, 2, 3, 4 BITS 7, 6, 5, 4 1,2 3,4 5,6 7,8 MSB LSB eLOeK---1--------~--~_4------~--4_--+_----~~--_+--~------, KEY BIT 8 10 MODE 2----+'---------+--t-----1-'~_t--------++---+___1~--_t Co. 1, ..... SIN SOUT MSB DATA OUT BITS I, 2 3,4 The key register is capable of hold, left shift (encipher), or right shift (decipher) operations, by one or two positions, as required by each of the 16 rounds of the algorithm (see figure 2). Each device also includes logic for the control of these registers during load and cipher operations. The 64-bit word by 4-bit ROMs in each device implement the S-boxes of the algorithm. The major differences among the four devices are the masking of the ROM codes and the key bits that are selected as ROM addresses, according to the E-bit selection table of the algorithm. A set of eight output signals (P,.a) and input signals (F, .a) is interconnected between chips to implement the permutation function, P, of the algorithm. An additional set of outputs (Px and Py) and inputs (Fx and Fy) is used to interconnect the chips as required by columns 1 and 6 of the E bit-selection table. 5,6 PARITY OUT LSB 7,8 Implementation of the Algorithm Initial permutation is accomplished in the F9414 chip set by the manner in which the data is loaded. The DINO input of chip 1 loads bit 1 of each byte, DINI of chip 1 loads bit 2 of each byte, DINO of chip 2 loads bit 3 of each byte, etc. After eight clock cycles, the fOur registers receiving data bits 2, 4, 6, and 8 of each input byte comprise the La block of 32 bits in permuted order within the four devices. The four registers receiving bits 1, 3, 5, and 7 of each byte hold the Ro block. Therefore, each chip slice contains one byte each of the La and Ro blocks. Further shifting of the bits and extracting outputs from the right end of each byte implements the inverse permutation, 1p-l. Each column of the inverse permutation may be found in a register byte, and the first 8 bits (40, 8, 48, etc.) required by row 1 of the Inverse permutation table are at the output ends of the shift registers. 6-15 F9414 Figure 2 F9414 Block Diagram (One Unit) Py Sour S,N D,N 1 ~. I I 8 L.-- D INO ~J) I:L I t 1 ..... r J; 1 I I Fy CP /6 / I.- 6 4''',"~ l[=l \g+ I /6 S·BOX ROM' /4 I / 4 S·BOX ROM' I rr ' ,"' • 1 I T I • I i tI~ tit m,"" °OUTO I 0 I -. IOE MUX RIGHT DATA 6~5 CONTROL DOUT1 OE L.......-- + C, .I 0 8 FX Co C1 I MUX LEFT DATA KE\REG NOTE: THIS CONNEC nON EXISTS ON CHIPS 3 A ND 4 ONLY 'y+, to... ?f'M:KING OPTIONS 6·16 F9414 The 28 key bits in the top half, Co' of the key permutation function are duplicated in the key registers of F9414·1 and F9414·2, while key bits in the bottom half, Do, occupy the registers of both the F9414·3 and F9414·4. In each device, key register 4 holds the .Iast 4 bits of both halves of the key permutation function. Each of the 16 iterations involves a left rotation (encipher) or right rotation (decipher) of the key registers. Table 2 Keyword Distribution Keyword 8 MSB 7 6 5 4 3 2 LSB 1 Parity (Option) During the key shift schedule, chips 1 and 2 bypass the right half of key register 4, and chips 3 and 4 bypass the left. This results in the key alignment returning to its original position after a total of 28 shifts from the 16 alterations. An internal 1·bit right realignment is required by a change from encipher to decipher, after the key has been entered. This, and the reverse (left realignment for decipher to encipher), are performed by the F9414 control logic, which must be stable prior to the loading of the last data byte. When clocked at the same time as a load· key code, the data registers all fill with logic ones. F9414·1 Key Reg. F9414-2 Key Reg. 1 2 3 4 1 2 3 4 F9414-3 Key Reg. F9414·4 Key Reg. 4 3 2 1 4 3 2 1 PIN The keyword is 56 bits long but, if desired, an optional parity bit can be included with each byte of key, making the keyword 64 bits long. Parity does not in any way affect the encryption or decryption, and is taken across the keyword register, not across the K1·K4 inputs. Parity across 1 byte of keyword is taken by passing the parity bit of the keyword through a delay flip·flop to PIN of the F9414·1 or F9414·2, and through POUT of the F9414·1 or F9414·2 into PIN of the F9414·3 or F9414·4. The final parity sum is available on POUT of the F9414·3 or F9414·4. The results of the exclusive·OR of the key bits and data words derived from Ro in the calculation of f(R,K) are taken, 6 bits at a time, to address a set of eight 64 x 4 S ROMs (i.e., S boxes). Two S ROMs per chip, each with four output bits, provide the 32 bits that are then permuted per primitive function P, by chip·to·chip interconnection. The effective result of the interconnect is exclusive·ORed with the ~ block and the entire algorithm is repeated 16 times. The functions of the F9414 (load key, load data, encryption/decryption, and wait) are controlled by the CO·C2 inputs. Data and key are clocked in and/or out on low·to·high clock transitions. Loading a key sets the data registers to all high. The F9414 enables simultaneous input and output of data; i.e., the results of a DES cipher operation can be clocked out on the same low·to.high transition that loads the next word to be processed. Thus, a complete input and output cycle (LOAD/READ DATA) takes just eight clocks. Since the algorithm requires 16 clocks, an entire DES iteration can be accomplished in 24 clocks. At a typical clock frequency of 6 MHz, this translates into a 16 MHz bit rate, a very fast LSI implementation of the DES. This high throughput ensures that the F9414 set is capable of keeping pace with practically every application, and this speed is available over the full military temperature range. The F9414 is structurally designed for high throughput. Since no I/O ports are used for both entering data and reading results, a potential bottleneck is avoided. The 64·bit data word is entered into the F9414 data registers 1 byte at a time at the 0 0 ,0 1 inputs. The MSB of data goes to Do of the F9414·1. The result is output 1 byte at a time on the QO,Q1 pins, MSB output first. Similarly, the keyword is entered 1 byte at a time at its own dedicated inputs (K 1·K4 ). Table 2 shows the distribution of the keyword to the four F9414 devices. 6·17 F9414 Implementation of Cipher Feedback. into the least significant position of the buffer, while all other bytes are shifted and the former MSB discarded. This causes all following encryptions to depend on the present transmission, providing greater security than when each encryption depends only on the present data byte. In cipher feedback (see figure 3), the present 54-bit data input is exclusive-ORed with the output of the encryption unit, and the result of this operation is transmitted and also fed back into the encryption unit to pe~petuate the feedback. At the receiver, the received 54-bit vector is first exclusive-ORed and then deciphered. At the receiver (see figure 5), the transmission is shifted into the least significant position of the buffer and one DES iteration is performed. Since the receiver has used the same data word as the transmitter, this generates the same exclusive-OR mask as was used at the transmitter. Therefore, exclusive-ORing the next received byte with the MSB of the F9414 output recovers the data byte. Figure 4 illustrates the cipher feedback (CFB) transmitter operation. A 54-bit buffer is necessary for storing the input word external to the F9414 and can be provided with two F9423 first-in first-out (FIFO) buffer memories. Bot.h receiver and transmitter operate in the same mode and start with the same (arbitrary) initialization word in the buffer. If the initialization is not done, the first 54 bits of data at the receiver are erroneously deciphered. The transmitter and receiver must be operating in synchronization in cipher feedback. If synchronization is lost or an erroneous bit received, 54 bits of data will be incorrectly deciphered. To encrypt 1 byte of data, one iteration of the DES algorithm is performed on the contents of the buffer. Then the MSB output from the F941,4 is exclusive-ORed with the data byte and the result is transmitted. Additionally, the result of the exclusive-ORing is shifted Figure 3 Cipher Feedback Implementation 6-18 F9414 Figure 4 Cipher Feedback Transmitter ,-----....:..::....--+--IPL PL F9423 F9423 TOP C. SELECT (S'N) (TO Vcel SOUT CP'------' CP C, C. C, C. LSB MSB I TIMING FOR DECIPHER/LOAD DATA CIPHER OUT SET UP FOR FIFO INPUT *(2) ~$s1..- CP I LOW I --------------~I------~I~--------------------~\·~,------~-+t----~~l~---------~--+_:- - - - L O A D DATA---- - - -....0..;1 nil 1"'1 .. ENCIPHER/DECIPHER c, I I 1 ~~~::_I' ENCIPHER/DECIPHER -+1---Il~l--------I SETUP FOR F9414 "C" .'NPUT !-- 1 S~~,~f------------...I1 PE~~~RM I.I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-II'~,______..1__.1,'----""""I(l~---------' NOTES: 1. 8 byte Initialization vector following LD KEY 2. 9 clock pulses required to complete load data operation 6-19 F9414 Figure 5 Cipher Feedback Receiver LSB ,-----.:..:=---+--1PL TOP F9423 PL F9423 Co DO 0, Do 0, CP'----....I C, SOUT SOUT SOUT CP CP Co 9414·2 CP CP Co 9414·4 C, C, C, C, Co CP C, Co C, 9414·1 00 Q, S'N 00 01 S'N S'N SOUT (TO Vee) SOUT C, Do 0, S'N 9414·3 Co 0 0 01 00 C, C, o 0, C, MSB LSB I TIMING FOR DECIPHER/LOAD DATA DATA OUT SET UP FOR FIFO INPUT I CP I 1 ·(2) ~$s1- I Co LOW : : ·~)::::::;..i .....1....---1"....- - - - - 114 LOAD DATA _ _ _ _ .. : ENCIPHER/DECIPHER C, SELECT (S'NI ~r----!------------..j' ~!---"'. I , J 1 I PERFORM I..___________- f 1 • XOR • !.i-'- - -......- I i i ENCIPHER/DECIPHER J1 I SETUP FOR F9414 "C" INPUT ....---111"1- - - - - - NOTES: 1.8 byte initialization vector following LD KEY 2. 9 clock pulses required to complete load data operation 6·20 F9414 Implementation of Cipher Block Chaining receiver needs a 64-bit buffer to store the previous transmission. Both receiver and transmitter must start with the same initialization data or the first 64 bits of transmission will be incorrectly deciphered. Cipher block chaining (see figure 6) is similar to cipher feedback in that successive transmissions are made dependent on previous transmissions, thereby increasing the level of security. The cipher block chaining transmitter takes the present 64-bit input vector and exclusive-ORs it with the output of the encryption unit, then performs an encryption on the result. The result of the encryption is transmitted and also exclusive-ORed with the next 64-bit vector, continuing the chaining process. The receiver runs synchronously with the transmitter, and recovers the data by performing a decryption and then an exclusive-OR on the received 64 bits. Internal exclusive-OR gates on the F9414 make implementation of the cipher block chaining transmitter especially simple. When SIN is high, the exclusive-OR of the D inputs and Q outputs is input to the F9414 register. Since the F9414 can input and output simultaneously, the input data and the F9414 output are exclusive-ORed while the result of the DES iteration is being clocked out at the Q outputs. Therefore, no additional packages are required. Receiver and transmitter must operate in different modes: encrypt and decrypt (see figures 7 and 8). No data buffering is necessary at the transmitter, but the Figure 6 Cipher Block Chaining Mode with Terminal Block Padding P·1 PADDING CHARACTERS PADDING COUNT ENCRYPT ENCRYPT ENCRYPT ENCRYPT DECRYPT DECRYPT DISCARD P CHARACTERS LEGEND: 0, = DATA AT TIME 1 I, = INPUT AT TIME 1 C, = CIPHER AT TIME 1 IV = INITIALIZATION VECTOR 6-21 F9414 Figure 7 Cipher Block Chaining Transmitter DATA IN I CP----------~.-+_--+_~--~~--~~--~~--~_+--_, NOTES: 1. A high on SIN (C, Co = 10 - LD DATA) enables the internal XOR gates to perform the chaining. 2. Hold SIN low while loading initialization vector. Figure 8 I CIPHER OUT Cipher Block Chaining Receiver CIPHER IN PL F9423 TOP Qo Q, Q, Q, PL F9423 TOP Qo Q, Q, Q, LSB I DATA OUT CP Co (LOW) PL & TOP n --_... 6-22 F9414 Timing Characteristics characteristics are provided in table 3. The ac characteristics are: Vee 5V ±5%; TA O·C to 70·C; CL 15 pF; and IINJ 85 to 125 mAo = Signal timing diagrams for the data encryption set are shown in figures 9 through 11, and the timing = = Table 3 Timing Characteristics Limits Symbol Parameter Tp Prop. Delay, CP to P1-8 155 ns Tp Prop. Delay, CP to Px, Py 110 ns 120 ns SOUT Low - ns Min Typ Max Units Comments Tp Prop. Delay, CP to DOUT Tp Prop. Delay, CP to DOUT Tp Prop. Delay, CP to POUT (9414-1, -2) 130 ns SIN' SOUT' High C210 XLH Tp Prop. Delay, CP to POUT (9414-3, -4) 145 ns C210 Tp Prop. Delay, SIN to DOUT - ns SOUT High Tp Prop. Delay, SOUT to DOUT 85 ns 132 75 = = XLH Tp Prop. D.elay, DIN to DOUT - ns Tp Prop. Delay, C210 to DOUT 105 ns Tp Prop. Delay, PIN to POUT Prop. Delay, Fx, Fy to P1-8 60 ns Tp 100 ns Ts Set-up Time, F1-8 to CP 50 ns Ts Set-up Time, DIN to CP 45 ns C210 = XHL Ts Set-up Time, SIN to CP 70 ns C210 = XHL Ts Set-up Time, C210 to CP 110 ns Ts Set-up Time, K1-4 to CP 50 ns C210 = XLH TH Hold Time, CP to F1-8 5 ns TH Hold Time, CP to DIN 0 ns C210 TH Hold Time, CP to SIN 0 ns C210 = XHL = XHL TH Hold Time, CP to C210 0 ns TH Hold Time, CP to K1-4 10 ns C210 = XLH TPWH CP Pulse Width High 50 ns 55 6-23 SIN' SOUT High = F9414 Figure 9 Load Key Timing Diagram CLOCK K INPUT C.:x___________x:::: DOUT Figure 10 :x: x:::: HIGH IMPEDANCE Load/Read Data Timing Diagram LOAD/READ DATA DATA---'\.~ IN Ip+j DATA---";""",J--- OUT _ _ _ _ _ ----, ____ C~ '~, J,~_ ___________________________________ ,-.- ~/_._. C.::::x__________---'x: 6·24 F9414 Figure 11 Cipher Timing Diagram CIPHER II DIN:::J(_ _ _ _ _ ~::i_ DOUT:::><_ _ _ _H_IG_H_I_M_PE_D_AN_C_E_ _ _ _ Co --"'"\ ._.~ . -~ C1._.~ _____________ 13 14 15 16 _____--'X__ .;::!~-----H-IG_H_I_M_PE_D_A_NC_E_ _ __'X'-___ I ,---- .. ~\~!--------------~c------ . l.,-----__ . __ _ _ _ _ _ _ _ _ _ _ _ _ _~j~!_ _ _ _ _ _ _ _ _ _ _ _ _ _ C2:::J( LOW = DECIPHER ::I-_____________'X'--___ HIGH = ENCIPHER DC Characteristics Control Codes The dc characteristics of the data encryption set are provided in table 4. The dc characteristics are specified over operating temperature range, unless otherwise noted: Table 5 provides the control codes for the data encryption set. Table 5 Control Codes Clock Cycles O°C to 70°C; IINJ(min.) = 85 mA; IINJ(max.) = 125 mA; VCC(min.) = 4.75 V; Vee(max.) = 5.25 V. Typical limits are at Vee = 5.0 V, TA = 25°C. 000 1 0 0 X 0 1 X 1 0 X Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Storage Temperature Ambient Temperature under Bias Vee Pin Potential to Ground Pin Input Voltage (DC) Input Current (DC) Output Voltage (Output High) Output Current (DC) (Output Low) Injector Current (IINJ) Injector Voltage (V 1NJ ) _65°, + 150°C - 55°, + 125°C -0.5, +6.0V -0.5, +5.5V -20, +5mA -0.5, +5.5V +20mA + 200 mA -0.5, +1.8V 6-25 DECIPHER ENCIPHER LOAD KEY LOAD DATA/OUTPUT DATA WAIT 16 16 8 8 X F9414 Table 4 DC Characteristics Limits Symbol Parameter Min VIH Input High Voltage 2.0 Vil Input Low Voltage Veo Input Clamp Diode Voltage VOH Output High Voltage VOL Output Low Voltage IIH Typ -0.9 2.4 Guaranteed Input High Voltage V Guaranteed Input Low Voltage -1.5 V rnA = Min, liN = -1B rnA Vee = Min 10H = - 1.0 rnA (D OUT) 10H = - 400 pA (Other Outputs) Vee = Min, 10l = B.O rnA Vee = Max, VIN = 2.7 V Vee = Max, VIN = 2.7 V Vee = Max, VIN = 5.5 V Vee = Max, VIN = 0.4 V V 0.25 0.5 V 1.0 20 I'A Input High Current, CP 1.0 40 I'A 1.0 rnA Input Low Current, All Except CP -0.21 -0.36 Input Low Current, CP -0.42 -0.72 Off State (High Impedance) Output Current, DOUT los Output Short Circuit Current Icc Supply Current VINJ Injector Voltage -15 1.0 Test Conditions IINJ = 100 rnA V Input High Current, All Except CP 10Zl 10ZH Units O.B 3.4 Input High Current, All Inputs III Max Vee = Max, VOUT = 2.4 V = Max, VOUT = 0.5 V Vee = Max, VOUT = 0 Vee = Max IINJ = 100 rnA, Vee = 5.0 V 100 pA Vee -100 I'A Vee -100 rnA 150 220 rnA 1.3 1.5 V Device Interconnection Ordering Information Table 6 gives the interconnection information for the four-chip set. Part Number Package Temperature Range Table 6 F9414 ST DC Ceramic DIP O'C to 70'C Device Interconnection Export Control nF (f) to nP (p)' 1F1 to 2PB 1F2 1P7 1F3 3P4 1F4 3P5 1F5 4P5 1F6 2P4 1F7 4P4 1FB 3P1 2F1 to 1P1 2F2 2P7 3P7 2F3 2F4 4P2 2F5 1P5 3P2 2F6 2F7 4P7 2FB 2P2 3F1 to 1P2 1PB 3F2 3F3 3PB 2P6 3F4 3F5 4PB 4P3 3F6 1P3 3F7 3FB 2P1 4F1 to 3P3 4F2 2P5 4F3 4P6 4F4 1P6 4F5 3P6 4F6 2P3 4F7 1P4 4FB 4P1 1FX 1FY 2FX 2FY 3FX 3FY 4FX 4FY 4PX 2PY 1PX 3PY 2PX 4PY Cryptographic devices and technical data regarding them are subject to Federal Government export controls as specified in Title 22, Code Of Federal Regulations, Parts 121 through 12B. 3PX 1PY • n indicates chip option f and p indicate specific member 6-26 F9423 FI FO Buffer Memory FAIRCHILD A Schlumberger Company Microprocessor Product Description Device Organization The Fairchild F9423 is an expandable fall-through-type high-speed first-in, first-out (FIFO) buffer memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64 words by 4 bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories. As shown in figure 1, the F9423 consists of three sections: 1. An input register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion. 2. A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic. The F9423 has 3-state outputs that provide added versatility, and is fully compatible with all TTL families. 3. An output register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion. • Serial or Parallel Input • Serial or Parallel Output • Expandable Without Additional Logic • 3-State Outputs • Fully Compatible With All TTL Families • Slim 24-Pin Package These three sections operate asynchronously and are virtually independent of one another. Signal Functions The F9423 FIFO signal functions are described in table 1 Connection Diagram Signal Functions PL 0, 00 0, I 24 PARALLEL DATA OUTPUT 23 22 0, ill} CONTROL INPUTS O. SERIAL DATA OUTPUT !iRE REGISTER OUTPUTS 21 20 19 18 PARALLEL { DATA INPUT SERIALI~~~~ 17 16 0, D. 6-27 10 15 11 14 12 13 F9423 Table 1 Signal Functions Mnemonic Pin No. Name Description PL 2 Parallel Load Input signal that, when high, enables Do - 0 3 ; not edge·triggered Ones catching. CPSI 8 Serial Input Clock Edge·triggered input signal that activates on the falling edge. IES 9 Serial Input Enable Input signal that, when low, enables serial and parallel input. TIS 10 Transfer·to·Stack Input signal that, when low, initiates fall·through. MR 11 Master Reset Active·jow input signal. OES 15 Serial Output Enable Input signal that, when low, enables serial and parallel output. TOP 13 Transfer Out Parallel Input signal that, when high, enables a word to be transferred from the stack to the output register; not edge·triggered. (The TOS signal must be low for the transfer to occur.) TOS 14 Transfer Out Serial Input signal that, when low, enables a word to be transferred from the stack to the output register; not edge·triggered. (The TOP signal must be high for the transfer to occur.) CPSO 16 Serial Output Clock Edge·triggered input signal that activates on the falling edge. EO 17 Output Enable Active·low input signal that allows data to be output. 0 0 -03 3-6 Parallel Data Parallel data inputs Os 7 Serial Data Serial data inputs 0 0 -03 18 - 21 Parallel Data Parallel data outputs Os Register Status 22 Serial Data Serial data output IRF 1 Input Register Full Output signal that, when low, indicates that the input register is full. ORE 23 Output Register Empty Output signal that, when high, indicates that the output register contains valid data. Vcc 24 Power Supply Nominal +5 V GND 12 Ground Common power and signal return Control Inputs Data Inputs Data Outputs - Power 6-28 F9423 Figure 1 F9423 Block Diagram DS- - - - - - - - - - - , DES TOP ros CPSO w----------------~~~~~~ '-----1>-- as Functional Description Serial Entry Input Register Data on the serial data (Ds) input is serially entered into the shift register ~2' F1, Fa, FC) on each high-to-Iow transition of the CPSI input when the Serial Input Enable (IES) signal is low. During serial entry, the PL input should be low. The input register can receive data in either bit-serial or 4-bit parallel form. It stores this data until it is sent to the fall-through stack, and also generates the necessary status and control signals. After the fourth clock transition, the four data bits are located in flip-flops Fa - F3· The FC flip·flop is set, ___ forcing the IRF output low and internally inhibiting CPSI pulses from effecting the register. Figure 3 illustrates the final positions in an F9423 resulting from a 256-bit serial bit train (8 0 is the first bit, 8 255 the last). This 5-bit register (see figure 2) is initialized by setting flip-flop F3 and resetting the other flip-flops. The Q-output of the last flip-flop (FC) is output as the Input Register Full (IRF) signal. After initialization, this output is high. Parallel Entry A high on the parallel load (PL) input loads the Do - D3 inputs into the Fa - F3 flip-flops and sets the FC flip-flop. This forces the IRF output low, indicating that the input register is full. During parallel entry, the serial input clock (CPSI) input must be low. 6-29 • F9423 Figure 2 Input Register Conceptual Logic Diagram 10, PL--~~-----------------+~---------4~----------~----------~ INITIALIZE---I------..------....., DS---+--tD a t-r-I---iD S aMr----1D Qt--1---1D at--1---ID Fe Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the F9423, the master reset (MR) input only initializes the stack control section and does not clear the data. Fall-Through Stack The outputs of flip-flops Fo - ~ed the stack. A low level on the transfer-to-stack (TIS) input initiates a fallthrough action; if the top location of the stack is empty, data is loaded into the stack and the input register is reinitialized. (Note that this initialization is delayed until PL is low.) Thus, automatic FIFO action is achieved by connecting the IRF output to the TIS input. Output Register The output register (see figure 4) receives 4-bit data words from the bottom stack location, stores it, and outputs data on a 3-state, 4-bit parallel data bus or on a 3-state serial data bus. The output section generates and receives the necessary status and control signals. An RS-type flip-flop (the initialization flip-flop) in the control section records the f!lct that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TIS may still be low; the initialization flip-flop is not cleared untilPL goes low. Figure 3 Final Bit Positions Resulting from 256-Bit Serial Train F9423 DUTPUT'------REGISTER 6-30 F9423 Figure 4 Output Register Conceptual Logic Diagram . - - - - - - - - - - - O U T P U T FROM STACK _ _ _ _ _ _ _~ I LOAD FROM STACK I S .--- D FX Fo r< MR CP R ° p- .- TOP Lt ro--~~~---r--~-r-----~-4~----~-+----' "'" y ORE ~7 ~7 ~7 IL ..=°"",3_ _ _ _ _ _O,::,''--_OUTPUT DATA........c°:..!'_ _ _ _ _ _O::.!oul Os TOP permits the transfer of the next word (if available) into the output register. During parallel data extraction, the serial output clock (CPSO) line should be low. The transfer out serial (TOS) line should be grounded for single-slice operation or connected to the appropriate ORE line for expanded operation (refer to the "Expansion" section). Parallel Extraction When the FIFO is empty after a low pulse is applied to the MR input, the output register empty (ORE) output is low. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the transfer out parallel (TOP) input is high. As a result of the data transfer, ORE goes high, indicating valid data on the data outputs (provided that the 3-state buffer is enabled). The TOP input can then be used to clock out the next word. The TOP s.igrral is not edge-triggered. Therefore, if TOP goes high before data is available from the stack but data becomes available before TOP again goes low, that data is transferred into the output register. However, internal control circuitry prevents the same data from being transferred twice. If TOP goes high and returns to low before data is available from the stack, ORE remains low, indicating that there is no valid data at the outputs. When TOP goes low, ORE also goes low, indicating that the output data has been extracted; however, the data itself remains on the output bus until a high level on 6-31 F9423 Figure 5 190·Word x 4·Bit Vertical Expansion Scheme MASTER RESET PARALLEL LOAD Serial Extraction When the FIFO is empty after a low is applied to the MR input, the ORE output is low. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the TOS input is low and TOP is high. As a result of the data transfer, ORE goes high, indicating that valid data is in the register. PARALLEL DATA IN I 0, 0, 0, D. I -f -, I II' SERIAL DATA IN L....o SERIAL INPUT CLOCK ~ --- The 3-state serial data output (as) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the high-to-Iow transition of CPSO. To prevent false shifting, CPSO should be low when the new word is being loaded into the output register. The fourth transition empties the shift register, forces ORE low, and disables the serial output, as. For serial operation, the ORE output may be tied to the TOS input, requesting a new word from the stack as soon as the previous one has been shifted out. F942'3 I>- PL Os 0, 0, 0, D. ~: IRF 0-- CPSI OES TOS TOP CPSO EO MR Expansion F9423 Vertical Expansion ORE 0.Q, Q, Q, Q.Qs Jc PL Os 0, 0, 0, D. ---0 EO 0 3 02 MR a, 00 Os 03 O2 MR a, 00 N~ Jc IRF p-~ TOS ORE 4 F9423 P-I- TOP -0 CPSO EO OK TO TTS -0 CPSI OES TOP CPSO PL Os 0 3 O2 0, Do TTS -0 CPSI CPSI - - - < l TOS I MR IRF OES TOP ~ -<: TTS as ~ CPSO EO MR 0 3 O2 a, as 00 Jc Jc (J) w .... I I L...c L.....-o TTS 0 IES L--..<: TOS IRF ORE 5 TOS ORE 6 ~ 03 O2 0, 0 0 as ,-0 TOS ORE 7 F9423 a, 00 II as ,-0 OES ORE 8 F9423 ~~ VALID ~ CPSO ,---0 EO 0 3 02 a, 00 I as MR 03 02 a, 00 I 1 as 1 1 OU ENA OUT CL' SERIAL DATA OUTPUT TRANS OUT PARALLEL 0-+- TOP EO MR IRF IES TOS ~ CPSO 03 O2 N ~ CPS! TOP CPSO EO MR IRF CPSI OES F9423 .j::o PL Os 03 02 D, Do ~ TTS TTS IES ~ TOP CPSO EO MR IRF OES TOP r---- -C '-- INUT REG· STACK (DERIVED FROM TTS) 0 FC ...... ..... F9423 Figure 11 is a conceptual logic diagram of the internal circuitry that determines master/slave operation. When MR and IES are low, the master latch is set. When TTS goes low, the initialization flip·flop is set. If the master latch is high, the input register is immediately initialized and the initialization flip-flop reset. If the master latch is reset, the input register is not initialized until IES goes low. In array operaton, activating TTS initiates a ripple input register initialization from the row master to the last slave. A simila~ration takes place for the output register. Either a TOS or TOP input initiates a load-from·stack operation and sets the ORE request flip-flop. If the master latch is set, the last output register flip-flop is set and the ORE line goes high. If the master latch is reset, the ORE output is low until a serial output enable (OES) input is received. Timing Characteristics Table 2 describes, and figures 12 through 19 illustrate, the F9423 timing characteristics. Table 2 Timing Characteristics Limits Symbol tpHL Characteristic1 Propagation Delay, Negative· Min Typ Max Units 30 40 ns Propagation Delay, Negative· Going TIS to IRF Stack not full, PL low (see figures 12 and 13). Going CP to IRF Output tpLH Comments 68 90 ns tpLH Propagation Delay, Negative· 46 55 ns OES low, TOP high (see figures tpHL Going CPSO to Os Output 30 40 ns 14 and 15). tpLH Propagation Delay, Positive· 80 95 ns EO, CPSO low (see figure 16). tpHL GOing TOP to 0 0 -03 Outputs 68 80 ns Propagation Delay, Negative· 29 50 ns tpHL Going CPSO to ORE tpHL Propagation Delay, Negative· 14 and 15). 39 60 ns Going TOP to ORE tpLH Propagation Delay, Positive· Going TOP to tOFT OES low, TOP high (see figures Parallel output, EO, CPSO low (see figure 16). 79 95 ns 3.6 4.3 !'s ORE Fall-Through Time TIS connected to IRF; TOS connected to ORE; IES, OES, EO, CPSO low, TOP high (see figure 17). tpLH Propagation Delay, Negative· 72 Going TOS to Positive·Going ORE 85 ns Data in stack, TOP high (see figures 14 and 15). 6·37 • F9423 Table 2 Timing Characteristics (Continued) Limits Symbol tpHL Characteristics1 Min Propagation Delay, Positive· Typ Max Units 39 50 ns Going PL to Negative·Going IRF tpLH Propagation Delay, Negative· Comments Stack not full (see figures 18 and 19). 41 55 ns 38 45 ns 32 45 ns 14 18 ns Going PL to Positive·Going IRF tpLH Propagation Delay, Positive· Going OES to ORE tpLH Propagation Delay, Positive· Going IES to Positive·Going tpZL Propagation Delay, OE to tpZH 0 0 -03 Propagation delay out of the high· impedance state. BE to tpHZ Propagation delay, tpLZ 0 0 -03 tpZL Propagation Delay, Negative· tpZH Going OES to Os tpLZ Propagation Delay, Negative· tpHZ Going OES to Os tAP See figure 19. iRF Parallel Appearance Time, ORE 16 20 ns Propagation delay into the high· 14 20 ns Propagation delay out of the high· impedance state. impedance state. 16 22 ns Propagation delay into the high· impedance state. 4 6 ns to 0 0 -03 Time elapsed between ORE going high and valid data appearing at output. Negative number t AS Serial Appearance Time, ORE 5 I vee 18 ns indicates data available before ORE goes high. to Os = 5.0 V ±5%;CL = 15 pF;TA = O'Ctc +75'C 6·38 F9423 Figure 12 Serial Input, Unexpanded or Master Operation CPSI 1.3 V tpHL I \ -f1.3V ',- OF'pLH,-=::::j _ _ __ TTS------------------------------------------------------------------- ~1.3V ~'PWL::1 Conditions: Stack Not Full: IES. PL Low • - - - - - - - - Figure 13 Conditions: Serial Input, Expanded Slave Operation Stack Not Full: iES High When Initiated; PL Low 6·39 F9423 Figure 14 as Serial Output, Unexpanded or Master Operation 1.3V--- Conditions: Figure 15 Data in Stack; TOP High, IES Low When Initiated; 5ES Low Serial Output, Slave Operation OES 1.3 V f lOS Conditions: Data In Stack; TOP High; IES High When Initiated 6-40 1.3V F9423 Figure 16 Parallel Output, 4·Bit Word or Master in Parallel in Expansion i'PWi7f '-.3-V----------------------__________-J___ i t--------------------r roP----------~~ 'PLH '_PH"\L '.3 V '_.3_V_-_-_--J~r--N-EW--O-Ur-p-u-r--- QO.Q3 _____________________________ Conditions: Figure 17 EO, CPSO Low; IES Low When Initiated; Data Available In Stack Fall·Through Time MR \ i 'PW 4 f ' - . 3 - V - - - - - - - - - - r :1 PL ',ec I,: f ------"""''-'_.3_V________________ !:-=,pw---! 'OFT QO.Q3 ____________________________________________ Conditions: TTS Connected to IRF; fOs Connected to ORE; IES, OES, CPSO Low; TOP High 6·41 ~I ~ • F9423 Figure 18 Parallel Load Mode, 4·Bit Word (Unexpanded) or Master in Parallel Expansion I- , ~I Ipw f PL -J STABLE 1.3 IRF NOTES: 1 If stack is full. IRF stays low. 2TTS normally connected to tRF Conditions: Figure 19 Stack Not Full: IES Low When Initialized Parallel Load, Slave Mode _____________________'P_"_L==:1 1.3 V I_I, Conditions: Stack Not Full: Device Initialized With IES High: Initialization Requires That a Master Reset Occur After Power Is Applied 6·42 I. F9423 Timing Set·Up Requirements Table 3 describes the F9423 timing set·up requirements. Table 3 Timing Set·Up Requirements Limits Symbol Characteristics1 tpWH Max Units Min Typ CPSI Pulse Width (High) 18 15 ns tpWL CPSI Pulse Width (Low) 22 15 ns tpWH PL Pulse Width (High) 11 10 ns Comments Stack not full; PL low (see figures 12 and 13). Stack not full (see figures 18 and 19). tPWL TIS Pulse Width (Low) Serial or 40 26 ns Parallel Mode Stack not full; (see figures 12, 13, 18,19). tpWL MR Pulse Width (Low) 35 22 ns See figure 17. tPWH TOP Pulse Width (High) 52 35 ns CPSO low; data available in tPWL TOP Pulse Width (Low) 32 24 ns tPWH CPSO Pulse Width (High) 18 11 ns TOP high; data in stack. tpWL CPSO Pulse Width (Low) ·25 17 ns See figures 14 and 15. 10 6 ns PL low (see figures 12 and 13). stack (see figure 16). ts Set.Up Time, Ds to Negative CPSI th Hold Time, Ds to CPSI 6 4 ns PL low (see figures 12 and 13). ts Set·Up Time, TIS to IRF Serial or 1 -17 ns See figures 12, 13, 18, 19. 0 -26 ns TOP high (see figures 14 and 15). Parallel Mode ts Set·Up Time, Negative·Going ORE to Negative·Going TOS tree Recovery Time, MR to Any Input 30 24 ns See figure 17. ts Set·Up Time, Negative·Going IES 18 15 ns See figure 13. 110 83 ns See figure 13. 0 -12 ns to CPSI ts Set·Up Time, Negative·Going TIS to CPSI ts Set·Up Time, Parallel Inputs to PL Length of time parallel inputs must be applied prior to rising edge of PL. th Hold Time, Parallel Inputs to PL 20 10 ns Length of time parallel inputs remain applied after falling edge of PL. vee = 5.0 V; c L = 15 pF; TA = 25·C 6·43 II F9423 DC Characteristics Table 4 describes the F9423 dc characteristics. Table 4 DC Characteristics Limits2 Units Symbol Characteristic1 Min VIH Input High Voltage 2.0 Vil Input Low Voltage VCD Input Clamp Diode Voltage VOH Output High Voltage, ORE, IRF 2.4 3.4 VOH Output High Voltage, 0 0 -03 , Os 2.4 3.1 VOL Output Low Voltage, ORE, IRF 0.35 0.5 V Val Output Low Voltage, 0 0 -03 , Os 0.35 0.5 V IOZH Output Off High Current, 0 0 -03 , 100 I'A -100 I'A Typ -0.9 Max V Guaranteed input high voltage 0.8 V Guaranteed input low voltage -1.5 V Vcc V V Os 10Zl Output Off Low Current, 0 0 -03 , Os Input High Current 40 JLA Vcc Vcc 1.0 mA Input Low Current, Except OES, MR -0.4 mA III Input Low Current, OES, MR -0.8 mA los4 Output Short Circuit Current Icc Supply Current = Min; liN = -18 mA Vcc = Min; IOH = - 4OO I'A Vcc = Min; 10H = -5.7 mA Vcc = Min; IOl = 8.0 mA Vcc = Min; IOl = 16 mA Vcc = Max; VOUT = 2.4 V; V E = 2.0 V Vcc = Max; VOUT = 0.5 V; V E = 2.0 V 1.0 IIH Test Conditions3 I OR"E,IRF -15 -100 mA rOO-03'OS -30 -130 mA 180 mA 140 = Max; VIN = 2.7 V = Max; VIN = 5.5 V Max; VIN ;; 0.4 V Vcc ;; Vcc = Max; VOUT Vcc = Max; inputs open Notes 1. Typical limits are at vcc ; 5.0 V ± 5%, TA ; O'C to + 75'C, and Max 10adinQ. The temperature ranges are 400 linear feet per minute. Typical thermal resistance values of the package at maximum temperature are: ;; 0 V guaranteed with transverse air flow exceeding BJA (junction·to·ambient) at 400 fpm air flow; 50'C/W, ceramic DIP; 65' C/W, plastic DIP. BJA (junction·to·ambient) in still air; 90'C/W, ceramic DIP; 110'C/W, plastic DIP. BJC (junction·to·case) ; 25'C/W, ceramic DIP; 25'C/W, plastic DIP. 2. The specified limits represent the worst·case values for the characteristic. Since these values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. 3. Conditions for testing not shown in the table are chosen to guarantee operation under worst-case condltions. 4. Duration of short circuit should not exceed 1 second; not more than one output should be shorted at a time. 6-44 F9423 Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this document, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those Iisted may cause permanent damage to the device. -65°C, +150°C -55°C, +125°C -0.5V, +6.0V -0.5V, +5.5V -12 mA, + 5.0 mA -0.5V, +5.5V Storage Temperature Temperature (Ambient) Under Bias Vee Pin Potential to Ground Pin • Input Voltage (DC) 'Input Current (DC) "Voltage Applied to Outputs (Output High) Output Current (Output Low) +20mA • • Either input voltage or input current limit is sufficient to protect the input. • 'Output current limit required. Guaranteed Operating Ranges Supply Voltage (Vee) Part Number F9423XC x '" Min 4.75 V I I Typ 5.0 V I I Max 5.25 V package type (D for ceramic DIP, P for plastic DIP) 6·45 Ambient Temperature (TA) O°C to + 75°C F9423 6-46 A Schlumberger Company F9443 Floating-Point Processor Advance Product Information Microprocessor Product Description • The F9443 Floating·Point Processor is designed to provide enhancement to the numeric capabilities of 16·bit microprocessors by providing a set of floating· point instructions. It can interface with the F9445, F9450 or any other standard 16·bit microprocessor, and it uses the microprocessor memory to directly fetch the required operands. It has eight general·purpose registers on·chip and supports all the basic functions with on·chip microcode. Use of additional off·chip microcode read· only memories (ROMs) provides extended capabilities. Figure 1 is a block diagram of the F9443. • FAIRCHILD • • • • • • • • • Circuit Description Full IEEE SP 0 OX Floating,Point Standard Support (80 Bits) Fast Algorithms for Add, Subtract, Multiply, Square Root, and Divide Functions Support for Full Set of Trigonometric Exponential and Logarithmic Functions Expandable Instruction Set That Can Include Macro Operations (e.g., Vector rotate, Fourier Transform, Array and Matrix Applications) User·Alterable Microcode for User Functions Support of Integer Decimal and Logical Functions Standard 64·Pin Package 13 L@ High Speed Bipolar Logic Low·Power Schottky·Compatible I/O Ve.ry Fast Execution Times Interface to Any 16·Bit Microprocessor The F9443 includes special hardware to provide fast algorithms for the basic functions. This hardware includes full·carry look·ahead for add and subtract (ADD/SUB) functions, recoding logic for multiply and square root functions, and partial·remainder·prediction logic for divide functions. An advanced control scheme provides a 2·level microcode/nanocode control with off· chip microcode expansion. The off·chip microcode can be programmable ROM (PROM) or random·access memory (RAM), with easy expansion for fast implementation of user algorithms. • Operation of the F9443 can proceed in parallel with the host processor to maximize throughput. Multiple F9443s can be connected to the host processor for array processing or other high-speed applications. Figure 1 9443 Block Diagram INSTRUCTION REGISTER MICROCODE ROM NANOCODE ROM I.] u 32·BIT ARITHMETIC AND LOGIC UNIT ~ I'L is a registered trademark of Fairchild Camera and Instrument Corp. 6·47 (OPTIONAL) EXTERNAL MICROCODE ROM (OPTIONAL) EXTERNAL RAM F9443 6-48 F9444 Memory Management and Protection Unit F=AIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The Fairchild F9444 programmable Memory Management and Protection Unit (MMPU) is designed to support complex multi-user and large single-user environments. With four F93422 bipolar static random-access memories (RAMs) serving as map memory, the F9444 expands the physical address space of the F9445 16-bit microprocessor to 2M words by performing logical-to· physical address translation. That is, the six most significant bits (MSBs) of the logical address are translated into 11 physical address bits, leaving the 10 least significant bits (LSBs) of the logical address unchanged. The memory thus consists of 21 bits (10 LSB and 11 MSB), or 4 megabytes. System integrity is maintained by access protection bits associated with each page. Any violation causes non-maskable interrupt to the F9445 central processing unit. Page·written (PW) and page-referenced (PR) bits permit the implementation of demand·paging algorithms. Figure 1 is a functional diagram of the MMPU. 1110 MARo iB2 ili, lB. ili, ili. MAR, iB7 MAR. ilia f1!, 11110 18 11 MAR7 iB12 • • • • • • • • • • • • @ PAg PA, PA, PA, 18 15 GNO PA, PA, PAs PAg PA 10 S'fIIl!A S"TRBO PW SVN WP PR ROVA VP ROVO lMEXT ClK Tm1'fiii llrn'OlJT INJ 6-49 MAR, PAs = MIl - MAR4 GNO 00 W I'L is a registered trademark of Fairchild Camera and Instrument Cm~ MAR, PA, M Standard InputlOutput (I/O) Instruction Format Ability to Implement Demand-Paged Virtual Memory System Ability to Access Up to 2M Words of Memory 2K Pages, With 1K Words for Each Page Memory Expansion Through Mapping and Demand Paging Controls for Memory Mapping Separate RAMs for Storing Maps Access and 1/0 Protection to Maintain System Integrity Special Status Bits for ReadlWrite Protection, Demand Paging, and 1/0 Protection Support for Two User and Two Data Channel Maps Low·Power Schottky·Compatible 1/0 Single + 5 V Power Supply 64 Pin Dual·in·Line Package (DIP) 13 L® Technology MAR, 18 13 1814 0, • • voo iB1 0lM1iP I'IIWE MAPOE i'BOE CS ROVAIN F9444 enabled at a time, but both data channel maps are enabled at the same time. The supervisor determines whether the mapping of program address and data channel address are to be enabled at the same time. If either user mapping or data channel mapping is disabled, the physical address space for that function is equal to the logical address space and only the lowest 64K words can be accessed. Maps The MMPU allows two user maps and two data channel maps to reside in map memory. Each data channel map contains 32 1K-word pages and each user map either 32 or 64 1K-word pages that can be relocated anywhere in memory. The two user maps and two data channel maps function independently. Only one user map can be [ Signal Functions ,,,,, CPU HANDSHAKE Figure 1 F9444 Functional Diagram ClK (lSB) MAR, SYN MARe STRBA MARs RDYAIN MARe RDYA MAR. STRBD MAR, RDYD MAR, cs ill" III,. III,. (MSB) MAR, (lSB) iB'2 iB11 PAg F9444 MEMORY MANAGEMENT AND PROTECTION UNIT - 'PA7 PAg PAs P~ PA. PA2 8 TliO·1B15 4 11 P"" PA10 W SfRBA ",,·A, MARo MAR] 11,00. 0 1 LMID Il!I.lAP i'BWE ii.\APl!'E I'BlJE t - - STJmj RDYA RDYD ~ MIl PW PR WP VP ClK INTPIN iIlTl'll1l't RAM 0 0 .03 MAP DATA °0'°3 r-- SYN I'n; DE 1J J 4 7 ~ RDYAIN os 4 GND INJ 5V GND II II ",,·A, 00.03 MAP RAM DATA °0. 0 3 WE (MSB) PAg DE J t J PW PR WP VP ~·A7 °0. 03 lMEXT 0, lDMAP W i'BWE MAPOE PlIOE INTPIN MAP RAM DATA PA, 0, ABORT RESET (lSB) PA" PAs ill" III. ill. ill, ill. ill. lB. ill. III, iii, ill, (MSB) M INFORMATION BUS MAP RAM ADDRESS -L ---------- MAP RAM PROTECTION ~ INTPOUT GND GND 6-50 ",,·A, 4 °0. 0 3 3 3 MAP RAM DATA °0. 0 3 °0. 0 3 WE Oil ft OE J 1 t J t t- F9445 FAIRCHILD 16-Bit Bipolar Microprocessor A Schlumberger Company Microprocessor Prod ucts Pin Functions Description The F9445 is a 16-bit microprocessor implemented using Fairchild's Isoplanar Integrated Injection Logic (13LBJ ) technology. This bipolar technology and a sophisticated pipeline architecture combine to give the F9445 very fast execution times, The processor has eight programaccessible registers and the capability of directly addressing 128K bytes (64K words) of memory. Up to 4M bytes of physical memory may be accessed using the F9444 memory management unit. The F9445 can address 62 1/0 devices, handle 16 levels of priority interrupt, and perform fast direct memory access. It has control lines to provide operator-console functions and has an on-chip self-test program. The F9445 CPU is supported with a comprehensive family of LSI support circuits to permit cost and performance effective usage in high-performance microcomputer systems. The support circuits include the F9446 Dynamic Memory Controller, F9447 I/O Controller, F9448 Programmable Multiport Interface, F9449 Multiple Data Channel Controller, F9444 Memory Management Unit and F9470 Console Controller. It is also supported with a library of software packages, including editors, debuggers, macro-assembler, relocating loader, real-time executive, interactive mUlti-user disk operating system and utilities, as well as high-level languages: FORTRAN, BASIC and PASCAL. CLK i'B,s F9445 16-BIT iB14 RUN ii, iBl~ iBl1 CARRY iS1 0 MR MICROPROCESSOR STATUS i IB9 INTON MULTIPROCESSOR { SIGNALS iSs BUSREQ is? iS6 BUSLOCK ills INFORMATION BUS iB4 183 ill, ill, ABORT EXTERNAL CQNREQ REQUESTS DCHREQ IBo INTREQ 00. : CONTROL SYN M STRBA 0, STRBD 00 ( TIMING STROBES RDYA Vi ROVO BUSGNT Vee IINJ ( BUS HANDSHAKE SIGNALS GND Absolute Maximum Ratings Beyond these ratings useful life of the device may be impaired. • Advanced Parallel Architecture Leading to Very Fast Execution Times-250 ns Register to Register, 2.9 p,S 16 x 16 Bit Multiply • Directly Addresses up to 128K Bytes of Memory with 11 Addressing Modes • Eight Program-Accessible Registers (ACO, AC1, AC2, AC3,SP, FP, PC,PSW) • Versatile Instruction Set Including Memory Reference, ALU, I/O, Stack, Multiply/Divide, and Floating Point Assist (Scale/Normalize) Instructions with 8·Bit Byte, 16·Bit Word or 32·Bit Double·Word Data • Multi-Processing Capabilities • Flexible Operator·Control Functions and Self·Test • Static Operation with Single Clock up to 24 MHz • LS TTL Input/Output Structure with 13L Internal Circuits • 40·Pin DIP Needing a Single + 5 V Power Supply • Full Military Temperature and Voltage Ranges • Radiation·Tolerant Technology • Comprehensive Family of Support Circuits Storage Temperature Ambient Temperature Under Bias Vee Pin Potential to Ground Pin Input Voltage (dc) Input Current (dc) Output Voltage (Output HIGH) Output Current (dc) (Output LOW) Injector Current (I'NJ) Injector Voltage (V ,NJ ) 6·51 -65 to + 150'C -55 to + 125'C -0.5to+6.0V -0.5 to +5.5 V -20to +5mA -0.5to+5.5V +20mA +450 mA -0.5to+1.5V F9445 Fig. 1 F9445 Functional Diagram MEMORY/BUS CONTROL SIGNALS AND STATUS SIGNALS DATA PATHSC:::::> CONTROL LINES_ Architecture tion register to supply additional control bits during certain instructions. In addition, the control unit has a machine instruction pre-fetch mechanism which overlaps the fetching of the next instruction from memory during execution of short-cycle instructions, such as arithmetic-and-Iogic (ALU) instructions. This pre-fetch capability and the microprogram pipeline give the F9445 very fast and efficient instruction execution. The F9445 microprocessor comprises three main blocks: the data path, the control unit, and the timing generator. Data Path The data path is 16 bits wide and is responsible for all the processing of data and address in the system. In many cases, data and address may be processed simultaneously. Timing Generator The timing generator produces the system timings for the F9445 internal registers, memory, 1/0, and console. The data path includes the following blocks (see Figure 1): Register File (ACO, AC1, AC2, AC3, SP, FP) Program Counter (PC) Program Status Word or Status Register (PSW containing: Carry, Overflow, 32KW, ETRP flags) Interrupt-On Flip-Flop (INTON) Destination Mux Source ~ux 16-Bit ALU 17-Bit Shifter 5-Bit Counter (for multicycle instructions) Bus Register Mux Bus Register Bus Mux and Buffer Incrementer The clock is divided on-chip using a 3-bit twisted ring counter. The divide ratio is 6:1 or 4:1, depending on whether a short or long cycle is required. The long cycle can be extended indefinitely by lowering the inputs BUSGNT, RDYA, or RDYD. These signals hold the processor in state S1 (using BUSGNT or RDYAI or S3 (using RDYDI until the inputs are raised. The twisted ring counter is also used to generate all the strobes by a combinational decode of its outputs and certain bits of the microprogram register. Signal Descriptions Control Unit The operations of the data path components are governed by the pipelined, microprogrammed control unit. This unit comprises three main elements (see Figure 1): the PLA (control store) to contain the microprogram, the pipeline register (microprogram register) to latch the microinstruction executed in the current cycle, and the instruc- All F9445 inputs and outputs are TTL. Information Bus iSothrough is,s, Pins 11 through 26 -16-bit Bus - Active LOW bidirectional; iSo is most significant bit; address valid 6-52 F9445 with STRBA strobe; data valid with STRBD strobe; 3-state during data-channel and non-bus cycles. write or output operation; 3-state during data-channel cycles and short cycles (BUSREQ is HIGH). Timing and Status SYN, Pin 7 - Synchronize Output - Active every cycle; may be used for external synchronization of memory and I/O control. RDYD, Pin 8 - Data Ready - Active HIGH input; used to synchronize external devices with the F9445 during data transfer; a LOW level halts the processor. RDYA, Pin 4 - Address Ready - Active HIGH input; maintains address on bus when LOW. STRBD, Pin 6 - Data Strobe - Active LOW output; active only during memory, I/O, console, or data-channel cycles; used as strobe for data. RUN, Pin 37 - Run Status when in halt state. STRBA, Pin 5 - Strobe Memory Address Register - Active LOW output; active only during normal memory cycles; not active during write portion of read-modify-write cycles (DSl, ISl, STB instructions and auto-increment/decrement addressing modes); used as strobe for external address register; active on I/O cycles when I/O instruction is output onto bus. CARRY, Pin 39 of carry bit. CLK, Pin 40 - Clock Input positive-edge triggered. Memory I/O Instruction Fetch Operand Indirect Address Address Save on interrupt, abort, and trap 1 1 1 1 0 0 0 1 1 0 1 1 Input or Output Data Channel Acknowledge Read Console Code Console Data BUSGNT, Pin 3 - Bus Grant - Active HIGH input; used for multi-microprocessor operation; a LOW level inhibits address output and halts the processor. Service Request The order of priority of requests and interrupts, from highest to lowest, is as follows: MR, ABORT, DCHREQ, Stack Overflow Interrupt, INTREQ, and CONREQ. MR, Pin 33 - Master Reset - Active LOW input; a LOW level causes the processor to enter a wait state after completing the next full cycle; if that cycle is a write, it is inhibited (changed to read); sets the F9445 to 32K mode with trap enabled. M 01 00 State Indicated 0 0 0 1 SO through S4 S5 During machine cycles that do not use the bus, the Single-phase clock; BUSLOCK, Pin 2 - Bus Lock - Active LOW open collector output; set during read portion of read-modify-write cycles (on DSl, ISl, STB, and auto-increment/decrement), reset during write portion of those cycles; used in multimicroprocessor system. If a skip is taken on an arithmetic-and-Iogic (ALU) instruction, the next instruction is fetched but not executed. In such fetches, the iii! and a lines will indicate the following states. o o Active HIGH output; copy Arbitration BUSREQ, Pin 38 - Bus Request - Active LOW output; indicates that a bus cycle is required; useful in multimicroprocessor system. M 0100 Function 0 0 0 1 1 0 1 1 Carry Status - INTON, Pin 27 -Interrupt-On Status - Active HIGH output; copy of Interrupt-On flag; HIGH when interrupts enabled. M, Pin 36 - Memory or I/O Function - Active LOW output. 01, Pin 35 - Memory or 1/0 Function - Active HIGH output. OQ, Pin 34 - Memory or 1/0 Function - Active HIGH output; these pins indicate the type of bus transfer as shown in the following table. 0 0 0 0 Active HIGH output; LOW iii! and DCHREQ, Pin 29 - Data Channel Request - Active LOW input; initiates data-channel cycles while LOW after current instruction. Must occur before TDRH (c). a lines will be "111". BUSREQ and the bus strobes are inactive in these cycles. Vii, Pin 1 - Write Output - Indicates direction of data flow; CONREQ, Pin 28 - Console Request - Active LOW input; initiates a console operation after current instruction. HIGH indicates a read or input operation; LOW indicates a 6·53 F9445 INTREQ, Pin 30 - Interrupt Request - Active LOW input; initiates entry to interrupt procedure, if interrupts are enabled, after the current instruction. Fig. 2 F9445 Register Model 15 ABORT, Pin 32 - Abort - Active LOW input; initiates abort sequence in the current microcycle. PROGRAM COUNTER (PC) PROGRAM STATUS WORD (PSW) ACCUMULATOR 0 (ACO) Power Vee, Pin 31 - Power Supply - Requires +5 V. ACCUMULATOR 1 (AC1) ACCUMULATOR 2 (AC2) GND, Pin 9 - Ground. ACCUMULATOR 3 (AC3) STACK POINTER (SP) liNJ, Pin 10 - Injection Current Input - Operates in 200-400 mA range at approximately 1 V; requires> 350 mA for maximum speed. FRAME POINTER (FP) Register Set The F9445 has eight user-accessible registers (see Figure 2), including seven 16-bit registers and a program status word (PSW) containing the following four flags: carry (bit 0), 32KW (bit 1), trap enable (bit 2), and overflow (bit 15). The carry flag (C) indicates the state of the carry bit during arithmetic and logic operations. The 32KW flag indicates whether the processor is operating in the 32K-word ("1 ") or 64K-word ("0") mode. The trap enable/disable flag (ETRP) indicates whether the trap instruction is enabled ("1") or disabled ("0"). The overflow flag (V) indicates twos-complement overflow in arithmetic operations. liNTON I INTERRUPT-ON FLAG Fig. 3 Data Organization in a Stack (LIFO) INCREASING MEMORY ADDRESSES In addition, there is an interrupt-on (INTON) flag. The CPU responds to interrupt requests from external I/O devices when the flag is set (" 1"). When it is clear ("0"), all interrupt requests are ignored by the CPU. The state of the flag can be altered by the Interrupt-Enable or Interrupt-Disable instruction. SP - FP -.-- TOP OF STACK C I .--~ The seven 16-bit registers comprise a program counter (PC) that sequences the execution of instructions, four general-purpose accumulators (ACO through AC3), the stack pointer (SP) and the frame pointer (FP). The program counter sequences the execution of instructions. It holds the address of the next instruction to be executed and is automatically incremented to fetch instructions from consecutive memory locations. A Skip, Jump, Jump-toSubroutine, or Trap instruction, an interrupt generated by an I/O device or an Abort can alter the sequential execution of instructions. ........ - .. C~ - t TOP OF STACK F_ AC3 AC3 .--1-- OLDFP AC2 AC2 AC1 AC1 ACO ACO AC3 OLDFP AC2 ACO 6-54 SP OLDFP. AC1 The four accumulators serve as source and destination registers for 16-bit arguments in arithmetic-and-Iogic instructions which process the contents cif the source accumulators and a base value for the carry flag and store the 16-bit result in the destination accumulator. The associated carry and overflow flags are set or cleared depending on INCREASING MEMORY ADDRESSES t ! I ........ PREVIOUS RETURN BLOCK - AC3 ~ OLDFP AC2 AC1 ACO I I I I 32K WORD MODE 14K WORD MODE F9445 the result of the ALU operation as the base value of carry. Accumulators AC2 and AC3 also serve as index registers during memory addressing operations. In addition, AC3 functions as a subroutine linkage register, and the pair ACO and AC1 are used as a 32-bit register in the multiply/divide and the normalize and parametric double-shift instructions. two address ranges in which the F9445 can operate are 128K-byte (64K-word) or 64K-byte (32K-word) logical address space. The F9445 master resets to the 64K-byte (32K-word) address range. The 128K-byte (64K word) address range can be enabled or disabled under program control. The other two 16-bit registers serve as temporary storage and as the stack pointer (SP) and frame pointer (FP) in the stack manipulation instructions. The stack pointer contains the add ress of the top of the stack, i.e. the last word "pushed" onto the stack which is also the first word that may be "popped." The frame pointer contains the address of the highest location in a block of five words on the stack, a "frame," containing program status information used to return from a subroutine (see Figure 3). 64K·Byte (32K.Word) Address Range After the master reset is activated or the 064K instruction is executed, the F9445 operates in the 64K-byte (32K-word) address range. In this mode of operation, it uses 15-bit addresses to fetch up to 32K words from the memory and uses either the least-significant sixteenth bit to select high or low byte of the word in the byte instructions or the most-significant sixteenth bit to specify the remaining 15 bits of the word as an indirect address in multi-level indirect addressing instructions. The frame pointer is updated by the Save and Return instructions which are intended to be the first and last instructions, respectively, executed by a subroutine. When a Jump-to-Subroutine instruction is executed, the value PC+ 1 (and the value of the carry bit in 32K-word mode only) is stored in AC3. The Save instruction then pushes five key words onto the stack in the following order: first, the contents of ACO; second, the contents of AC1; third, the contents of AC2; fourth, the value of FP before the Save; and fifth, the contents of AC3. At this point, SP points to the top of the frame (which is the current top of the stack), and that address becomes the new value of FP. This new value of FP is also placed in AC3. When a Return instruction is executed, the five words stored in the frame referenced by FP are used to restore accumulators ACO through AC2 to their values at the time preceding the Save. FP is restored to its previous value (pointing to the last previously saved five-word frame) and PC is loaded with the return address which had been placed in AC3 by the previous Jump-to-Subroutine and pushed onto the stack by the previous Save. The restored value of FP is also placed in AC3 by the Return instruction. In the Load-Byte (LOB) and Store-Byte (STB) instructions, a 16-bit accumulator is specified as the byte pOinter. The most significant 15 bits of the byte pointer are treated as the logical address of the word containing the byte which the least significant bit specifies, selecting the high (if "0") or low (if "1") byte of the word. The remaining memory reference instructions specify effective addresses of 16-bit words via various (11) addressing modes described below. Information may also be moved between SP or FP and any of the four accumulators by the instructions MTFP, MFFP, MTSP, and MFSP without affecting the source register of the move or any of the registers not specified with the instruction. This allows setting up multiple stacks whose pointers are saved in main memory when not in use. Addressing Ranges and Modes Page Zero In this mode the instruction provides an 8-bit absolute address to access the first 256 words (page zero) of memory. PC Relative In this mode the instruction provides an 8-bit twos-complement Signed number which is added to the program counter to access 128 locations below and 127 locations above the address specified in the program counter. Indexed by AC2 (or AC3) In these two modes the instruction provides an 8-bit twos-complement signed number which is added to AC2 (or AC3) to access 128 locations below and 127 locations above the address specified in the accumulator. The memory reference instruction may specify any of the above four memory addressing modes to be either direct or indirect. For direct addressing, the effective address computed using the eight address bits of the instruction is the final address of the target word to be stored or retrieved. The F9445 memory reference instructions support two address ranges and a variety of addressing modes. These modes include direct/indirect addressing which may be absolute, PC-relative, or indexed by AC2 or AC3. Additional addressing modes include auto-increment, autodecrement, and address via stack and frame pOinters. The 6-55 F9445 For indirect addressing, the effective address computed from the eight address bits of the instruction is used to fetch a 16-bit word that supplies the address of the target word. If the most significant bit of this word is "0", the 15 least significant bits provide the address of the target word. However, if the most significant bit of this word is "1", this specifies a further level of indirect address. In that case, the 15 least significant bits refer to the address of another word which could provide the final address of the target, depend ing on whether its most significant bit is "0" or "1". Thus, multiple levels of. indirect addressing continue until a word is fetched with a most significant bit of "0". Such multiple levels of indirect addressing are only allowed in the 32K-word address range operations. provide the displacements for the calculation of effective add resses ot. memory locations. The whole instruction set can be divided into five broad groups: Memory Reference Instructions Arithmetic-and-Logic Instructions Stack Manipulation Instructions 110 Instructions Control Instructions The Memory Reference instructions modify the contents of memory locations, alter program execution sequence, and move operands between the accumulators and memory locations. The contents of accumulators and the carry and overflow flags are processed by the Arithmetic-and-Logic instructions. The Stack instructions manipulate the registers and the memory in stack-associated operations. The 110 instructions effect data transfers between the accumulators and 110 devices. The Control instructions modify or interrogate the state of the CPU and operator console, performing such actions as controlling the status of the interrupt-on flag and reading the status of the console switch register. The next two types of addressing modes are the autoincrement and auto-decrement modes. When locations 20 through 27 (octal) are indirectly addressed, the autoincrement mode is activated: the contents of the specified location are first incremented and stored back and this new value is treated as the effective address (which can, in tum, be either direct or indirect). Locations 30 through 37 (octal) are used as auto-decrement locations in a similar manner. The last type of addressing is stack addressing in which the address of the memory reference is derived from the stack pointer. 128K-Byte (64K-Word) Addressing Range After the E64K instruction is executed, the F9445 starts operating with the 128K-byte (64K-word) addressing range. In this range, the F9445 uses 16-bit addresses to fetch up to 64K words from the memory and supports all the 11 addressing modes described previously. However, only one level of indirect addressing is allowed - the one specified in the instruction - since with 16-bit addresses there are no bits available in the words fetched to indicate further indirect addressing. The byte pointer is also different in the 128K-byte (64K-word) case compared to the 64K-byte (32K-word) case. The 64K-word range byte pointer is 17 bits wide and is composed of the carry flag and the 16-bit accumulator specified in the LDB or STB instruction. The value of the least-significant bit of the 17-bit word selects the high (if "0") or low (if "1") byte of the word to be loaded or stored. Instruction Set The F9445 has fixed-length instructions, each of which is 16 bits long and divided into several fields. The fields are used to specify the operation code and other related actions, to define conditions and specify the CPU registers containing arguments, to define 110 device codes, and to 6-56 F9445 Input/Output Operations The F9445 can transfer the contents of any accumulator to an I/O device by executing a Data-Out instruction. It can load data from an I/O device into any accumulator by executing a Data-In instruction. To test the status of an I/O device, the F9445 can execute a Skip-On-Status instruction.The I/O cycle has the same timing as the memory cycle (see Figures 13 and 14). Features of the I/O cycle are: Input/output devices can transfer data to the F9445-based microcomputer via: Programmed I/O using the I/O instructions of the F9445, Memory-mapped I/O using the load/store instructions of the F9445, or • • • • • • Direct memory access or data-channel transfers. For programmed I/O, the device consists of up to three (minimum one) bidirectional 16-bit device registers, denoted as A, B, and C, and three 1-bit flags: Busy, Done and Interrupt Disable (see Figure 4). The 2-bit status word comprised of Busy and Done represents one of up to four possible states of the device, viz. idle, busy, partially done and completely done (refer to Device Status Flags subsection). The F9445 I/O instructions allow data transfers between any of the accumulators (ACO through AC3) and any of the device registers (A through C), and can test and set the Busy, Done and Interrupt-Disable flags. M I/O Input Execute Instruction Fetch I/O Output Execute Interrupt Save INPUT OUTPUT DEVICE REGISTER A DEVICE REGISTER B DEVICE REGISTER B DEVICE REGISTER C DEVICE REGISTER C Fig. 5 Input/Output Instruction Fields 10 Op Code AC Address Type of Transfer Control 11 0, 0 0 0 0 0 0 0 0 1 W 1 1 0 0 Instruction Decode An I/O instruction in the F9445 system comprises several fields as shown in Figure 5. This format accommodates data transfers between a CPU accumulator and anyone of up to three bidirectional registers in anyone of 621/0 devices. Bits 10 through 15 are coded to represent device codes 00 through 76 (octal). The all "1s" device code, 77 octal, is reserved for CPU control instructions and should not be assigned to any unique I/O device; for similar reasons, device code 1 is also reserved; by convention, device code 0 is not used. DONE DEVICE REGISTER A 1 0 1 0 • The I/O devices can interrupt the normal flow of the program by using the common interrupt request line Fig. 4 1/0 Device Model BUSY 250 ns ( at 24 MHz system clock) minimum cycle time Cycle time can be extended using RDYA, RDYD I/O instruction is output at add ress time STRBA is used to latch the I/O instruction STRBD is used to strobe the data 0 lines indicate the type of cycle as follows: 12 13 14 Device Code 6-57 15 F9445 Bits 3 and 4 specify the address of any accumulator involved in an I/O instruction. When no accumulator is involved, both bits are ignored. The function bits 5,6, and 7 define the I/O operation to be performed. Bits 8 and 9 control or test the status of the device busy and done flags. Device Status Flags Interrupts from a device are disabled when the interruptdisable flag of the device is set to "1". Interrupts are enabled when the flag is clear. Interrupt requests are generated whenever the device sets the done flag. The eight standard I/O instructions were listed previously In the instruction set description of the introduction to this section. The No-Input/Output (NIO) instruction Is a "no data transfer" instruction that can be used to set the busy and done flags as required, by attaching the appropriate flag-setting mnemonic. The F9445 executes a "dummy" data out transfer. The status of a device's busy and done flag.s is tested by executing a Skip (SKP) instruction that causes a specific I/O device to put its busy and done flag states on lines IBo and IB1 of the common information bus. If the flag state satisfies the condition specified by the busy/done flagtesting mnemonic appended to SKP, the CPU skips the next instruction. The remaining six standard I/O instructions first move data between an accumulator and anyone of the device registers A, B, or C. After the transfer is completed, the busy/done flags are set as specified in the I/O instruction. During programmed I/O, the interrupt-disable flag is normally set to disable interrupts, and the busy and done flags define the status of the device for the CPU. The busy and done flag states are coded to represent the indicated device conditions, as follows. Busy Done Device State 0 1 0 1 0 0 1 1 Device idle Device busy Device completely done Device partially done The sequence of I/O transactions is normally dictated by the speed at which the device can communicate with the CPU. If the CPU operates at a higher speed than a device, it enters a wait loop between each I/O transaction with the device. During execution of the loop, the CPU repeatedly monitors the busy or done flag to determine when the device is ready for the next I/O operation. There are three I/O instructions that are common to all I/O devices: Interrupt-Acknowledge, Mask-Out, and Clear-I/ODevices. The device code for these three instructions is 77 (octal). During an output operation, one instruction stores data in the desired device register and places the device in the busy state. The CPU then enters a wait loop which terminates when the device has cleared busy and set done to signal readiness for the next output operation. When the F9445 executes the I/O instruction, the M and 0 lines will indicate an i/O operation (""100~'). The 0 lines are valid on the rising edge of SYN. The device address (bits 10-15) must be decoded by each device on the I/O bus. Transfers of information to and from the F9445 are timed with STRBD in the same way as the memory cycle. To initiate an input transaction, the device sets the done flag. One instruction reads data from the appropriate device register and places the device in the busy state. The CPU then enters a wait loop which terminates when the device has cleared busy and set done to indicate that it has the next data ready. At the address time, the F9445 outputs the I/O instruction on the information bus. This can be used to generate I/O signals on systems without an I/O controller. STRBA is generated and can be used to latch the I/O instruction externally. The interrupt-disable~ busy and done flags organize interrupt-driven program-controlled I/O operations. The CPU controls the interrupt-disable flag. Both the CPU and the device can control the busy and done flags. 6-58 F9445 Interrupts The interrupt request, INTREQ, line is common to all 1/0 devices. When the device completes an 1/0 operation, it should set the done flag. Concurrently, if the device is enabled to interrupt, it should assert the active LOW on the INTREQ line. The processor responds to the interrupt request after completing execution of the current instruction. It then clears the interrupt-on flag so no further interrupts can be started, saves PC (which points to the next instruction) in location 0, and executes a "jump-indirect-to-location·1" instruction to jump to the interrupt service routine. Location 1 should contain the address of the interrupt routine or an indirect address to the routine. The F9445, when interrupted, can check for the source of the interrupt in two ways: It can test the state of the done flags in the various devices, one by one, by executing Skip-on-Done instructions; or It can test the state of the 1/0 devices by executing the Interrupt-Acknowledge instruction, causing the device that had sent an interrupt request to respond by placing its device code on bits 10 through 15 of the information bus. As several devices can request interrupt simultaneously, device priority may be established in a daisy-chain fashion by a physical connection of a serially propagated signal, Interrupt Priority. The first device requesting an interrupt and having its Interrupt-Priority-In line HIGH has priority, and it answers the Interrupt-Acknowledge instruction, at the same time blocking the propagation of the interruptpriority signal by putting its Interrupt-Priority-Out line in a LOW state. The interrupt-priority signal is generated in the device having the highest priority. The F9445 can disable the interrupt system in each I/O device by placing a mask on the information bus while executing the Mask-Out instruction. Each bit in the mask is assigned to a specific device. When that bit is "1", the interrupt system is disabled. A "0" in that bit enables the device. After servicing a device, the routine should restore the preinterrupt states of the accumulators and carry, turn on the interrupt, and jump to the interrupted program. The instruction that enables the interrupt sets interrupt on (INTON), but the flag has no effect until the next instructior begins. Thus, after the instruction that turns the interrupt back on, the processor always executes one more instruction (assumed to be the return to the interrupted program) before another interrupt service can start. If the service routine allows interrupts by higher priority devices, the routine should turn off the interrupt, before dismissing as indicated above, to prevent further interrupts during dismissal. In dismissing, the routine should re-enable lower priority devices. The interrupt request input INTREQ is negative-level sensitive and is synchronized in the processor. Externally, interrupt requests may be latched with the leading edge of SYN. The interrupt request may be reset by the external I/O controller from a decode of the I/O instruction INTA. The F9445 recognizes two other types of interrupts: Abort Interrupt - This is activated by the active LOW of ABORT input. The processor responds by: Aborting the instruction being executed, Storing the address of the aborted instruction in location 46 (octal), and Jumping indirect to location 47 (octal). Stack Overflow interrupt-This is an internal interrupt caused when the stack overflows; I.e., when a stack operation (PSHA, PSHF, PSHR, SAVE, TOPW) writes over a page boundary (mod 256). This interrupt is of higher priority than the external interrupt (INTREQ); the processor responds, at completion of the current instruction by: Clearing the interrupt-on flag (to "0"), Storing the updated program counter in location 0, and Jumping indirect to location 3 (octal). The interrupt-save cycle follows the interrupt. It can be externally detected by the code "011" on the 0 lines and used, for example, to switch an external mapper to nonmapped mode. The order of priority of requests and interrupts, from highest to lowest, is as follows: MR, Ai35Rf, DCHREQ, Stack Overflow Interrupt, INTREQ, and CONREQ. 6·59 F9445 Data Channel 3. The processor sets the code in). The data channel has three methods of operation with the F9445: iiii and 0 lines to "110" (console 4. In response to the iiii and 0 lines being set to "110", the console logic supplies a code on the information bus corresponding to the desired operation, which is selected onto the bus with STRBD. Data-channel cycle with F9445 controlling the memory, Data-channel cycle with external memory control, and Autonomous-bus cycle using bus arbitration scheme. 5. The console logic resets CONREQ. The sequence of events during a data-channel cycle is as follows: 6. The processor executes the console operation. 1. DCHREQ is set. 7. The processor may read or write data from the console switches or console lamps. In this case, the M and 0 lines are set to "111" (console data). In most cases, the processor halts after the console operation by entering a Wait state. The exceptions are Continue and APL. 2. F9445 responds by setting M, 0" and 0 0 to "101" and . BUSREQ to "1". This is recognized externally as DataChannel Acknowledge and can be used to reset DCHREQ if it is the last data-channel cycle required. 3. F9445 3-states the bus and sends STRBA. Console logic can be implemented in three levels of simplicity: 4. The external logic must supply an address at this time. The address time can be extended with RDYA. No Console Code -If a CONREQ is generated and no console code supplied, the default bus value ("0") will cause the processor to execute APL. This sets the PC to -1, then starts normal execution. This is the minimal console operation required. 5. F9445 outputs STRBD. 6. The controller transmits or receives the data-channel data and responds with RDYD, concluding the cycle. Limited Console Operation - A subset of operations can be arranged with a 2-bit console code. These operations are APL, Test, Continue, and Halt. Console Operation Console operation allows examination and modification of the F9445 internal registers without executing programs in main memory. This is very useful for system diagnostics even when the memory or 1/0 part of the microcomputer system is not fully functional. Full Console Operation - A 9-bit code (see Figure 6) defines the full set of console operations. Single-Step is not implemented directly, but can be arranged using Continue first, the Continue operation is specified; after the first instruction is fetched, a new CONREQ is generated and the operation is changed to Halt. Upon request for console operation, th·e processor will execute one of a number of console operations depending on a console code on the information bus (see Figure 6). This facilitates the connection of an external console for monitoring and test purposes. The following sequence is used to execute a console operation: 1. CONREQ is set LOW. 2. The processor finishes the current instruction. 6·60 F9445 Fig. 6 Console Codes o 2 o I I I I 10 , I~ I~GISTER 3 4 5 ~ I I 2 3 4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7 6 [EJ , ,I I IS ACO ACI AC2 AC3 SP FP o o 1 1 8 I Dffi:] I I I 6 I 0 PROGRAM LOAD 1 EXAMINE/DEPOSIT/TEST 0 CONTINUE 1 STOP - I I I 17 • 9 I 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TEST EXAMINE NEXT MEMORY DEPOSIT NEXT MEMORY EXAMINE REGISTER EXAMINE MEMORY DEPOSIT REGISTER DEPOSIT MEMORY is carrying address or data, respectively. The M Signal (M = LOW) indicates that a memory cycle is taking place on the bus, while the WSignal indicates whether the operation is a read or write. The timing of the STRBD is shorter for a write operation, to allow positive hold time for the memories. The signal RDYD may be held LOW to stretch the memory cycles for slow memories. Bus Arbitration The F9445 contains three signals that allow more than one processor to share a common bus: BUSREQ-This is LOW at the beginning of every cycle in which the F9445 requires use of the bus. BUSGNT-When LOW, it is used to halt the processor indicating the bus is unavailable. A typical scheme is shown in Figure 7. This diagram shows'a 4K x 16 static RAM configuration (2114-type 1K x 4). The bus is buffered by a 74240 inverting 3-state buffer. Buffering is optional and depends on fan-out requirements of the memories. The buffer is normally connected for output, but is connected for input when necessary by a simple decode of the M. Wand STRBD lines. BUSLOCK-This indicates that the current bus cycle and the following bus cycle from the processor must not be interrupted by a cycle from another processor. The BUSLOCK signal has two purposes. One purpose is to prevent the external memory address register from being overwritten during those instructions that rely on the address remaining in this register. The other purpose is to provide a method of synchronizing separate software tasks using a standard semaphore system. An external arbiter is required to determine which processor has access to the bus. An address latch (74533) is clocked with STRBA. The memory address is decoded frOm these outputs and forms the chip-select (CS) inputs to the RAM. A shift register (74164) provides a time delay for RDYD for slow memories. An alternative for this would be a one-shot (9602). Fast memories do not require RDYD delayed. Applications Static Memory Interface The F9445 bus structure allows easy connection of static memory. Both address and data are multiplexed onto the 16-bit information bus is(..,.). The mutually exclusive signals STRBA and STRBD indicate that the information bus 6-61 Fig. 7 Static Memory Connection Scheme IBM BUFFER/DRIVER 7....0 2,3 DE, 4.5 MEMORY ARRAY iii 18,17 'BMO iio _ 3 16,15 IBM, IB, 4 0, ~2 702 IB3 8 03 Do IBM4 1~::'A9 Ao-Ag IBMS IBMe IBM7 CS,HWE D7 LE 110,-1104 1/0,-1104 f--,-c>IWE ./0,-1/04 110,-1104 f--ctWE o- IBM,o ~CS IBM11 CSJ HWE ~ 1~::'A9 IBM,2 IBM'3 IBM,4 IBM,S or, ~ ... ~ ~ L504* I *S04 +5V-----f A,B I r--, I 1 0, D;EC.ft?L~~! 02 ~2 Ao 74S138 PLEXER rr -,-----' MAR2 MARJ 03 A, ':' SYN CSo CSt 00 nMAR, I I IMAR, LS04 l ." CO ~ ~ IIICp CLOCK - - - - ' ' - I E,. E31E2 BUFFER LOGIC I ....... 1I0"'/O'~ U1 15 SfRjij~ MAR, I ~ tjWE I/O"'~'~ STRBD L-- MARo ! AO-Ag CS 9,10 I 2',1l,'4 M __ 3 ~ CONNECTION DIAGRAM 1'rm':20 .5V Vi_ STRBA 110,-1104 iii'~'-' iii 1 OE2 1/0,-1/04 1~::A9 Ul...-.JAA9 IBMa IBMg ----.r 110,-1104 I MEMORY CHIP DECODE CS3 74S164 ~MR00 0, 02 03 04 05 06 Q7 lllllllf +5V--o AP ACCESS TIME I 50 ns 200 ns ~ .5V 1k 09 RDYD RDVD DELAY FOR SLOW MEMORY (NOT REQUIRED FOR 93475) 18~VCC A7 As A5 2 17 A4 3 2114 16 A3 4 9~~5 Ao 5 1K X 414 110, Al 6 RAM 13 1/02 CS A'3 7 12EI/O] 8 11 1I0~ GNO 9 10 We 15 As A9 F9445 The schematic (see Figure 8) shows a UART connection. The FPLA decodes the instructions and prod uces outputs from three multiplexers (74138). Spare outputs on these multiplexers can be used to drive other I/O devices. Input/Output The F9445 I/O can utilize a simple scheme similar to the memory connection. To take full advantage of standard F9445 I/O instructions, however, I/O instructions must be externally decoded. An F9445 support circuit (F9448, F9447, F9470) can be used for this purpose. Busy, done, mask and interrupt latches for both input and output are implemented. The baud rate generator (4702) is programmable for baud rates from 110 to 9600 baud. To implement standard F9445 I/O without the support circuits mentioned above requires external logic. This can be implemented with an FPLA (93459). Table 1 illustrates the PLA for 1/0. Table 1 I/O PLA Listing 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P --L-LLLHLHL'--HLL --L-HLLHLHL--LHL --L-LLLLHHL--HLL -HH------L-------L-LLLLHHL--LHL -LH------L-------L-LLLLHHL--LLH --L-LLLLHHL--LHH --L-LLLLLHL--LHL - -- - - -- - -H - --HHH --L-LLLHLHL--HHH --L-HLLHLHL--HHH --L-LLLLHHL--HHH --L-LLLLHHL--HHL --LHLLLHLHLLH----LHHLLHLHLLH----LHLLLLHHLLH----LHLLLLHHLHH----LHLLLHLHLHL----LHHLLHLHLHL----LHLLLLHHLHL----L-HHHHHHH--HLH --L-HHHHHHH--HHL --L-HHHHHHH--LLH --L-HHHHHHH----- 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'A 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F 'F In this scheme, the 1/0 bus is buffered (74240); this is optional. A one-shot (9602) provides a processor cycle delay by holding RDYD low. This allows the use of a slow UART (TR1263B). Converters (1488,1489) are used for RS232level connection, and current loop drivers are switch selected as shown. A one-shot (9602) provides a pulse for a TTY reader delay. LLLLLLLL -----AAA ------AA -----A-A -----A-A -------A -------A -----AA------A-----A-A- - -- - ---AAA-----AA----A-A----A-A---AAAA---A-AA--- Dynamic Memory Control Since dynamic memory is more difficult than static memory t6 connect to any processor, the F9445 requires some additional circuitry to drive dynamic memories (see Figure 9). There are several approaches to dynamic memory control: Using an LSI special-purpose dynamic memory controller (e.g. F9446), which is by far the simplest solution; Using standard SSI or MSI for the controller, requiring considerable board area; Using software-assisted techniques, which reduces hardware requirements but can result in poorer overall performance; or . -AA-A-~ Using a standard MSI dynamic memory controller (e.g. 9642) with additional timing and control logic. -A--A---AAA----A-A----AA------AA-----:-A-----A----A------- The last alternative has the advantage of uSing standard parts with a low part count and no software overhead. This is the scheme shown in Figure 9. The memory address register, data buffer and address decoder are required for any memory, static or dynamic. The 9642 multiplexes the 14-bit address for the dynamiC memories, seven bits at a time. The memories require two strobes: a row address strobe (RAS) and a 'column address strobe (CAS). In the scheme sho~all memory chips receive the same CAS strobe, but the RAS strobe depends on the address. The strobes are sequenced using a combination of F9445 timing signals (STRBA, SYN, STRBD) and other signals generated by a 74164 shift register. Key for Table 1: 'A = Active level of outputs 'P = Product term number 'I = Inputs 'F = Outputs Don't care H = High level L = Low level A = Active 6-63 Fig. 8 F9445 InpuVOutput Connection Scheme (1 of 2} IBI i 74LS138ao ....... MAlI. MAlI, 0, 9 Ao 93LS459 • A, ......, ....... ......" MARl2MARt3 2 42 FPLA A7 • A, ~~- A, 25 A9 MARJ5 24 All UII" 1227 04 15 t----4Ao THRE 'IA, O. "lA, 0, Vee 14 BAUD RATE B8YT, ,. 11 n INTA 9 MSKO TTY IN [ 1v ~ 1.~t 0.47"' ,- EXl' +5V A, . A, ~ ~ rORST 10 110 INSTRUCTION DECODE 0, ~V - t* 7 i74LS13800 CRL '!1""'"""Ta4 13 f' .l220 TROt=~--~~~--' 15 RaYR, 0, r STRBD 1 DR ORR TR 1263Be UART 0, I I Ao ,"VDRIYER +5V 0, 0, .,• t1 o. L DECODER! 07~ At> I t '~"'l 28 "0: en '74LSt3800 I I * 11 CD DEMUX O~ 13 AIO 0, O. 0, E, 06 12 27 . . A, '3 0:> 0, , • A, MAR14 110 ~: 16 17 A;l MAR,O 0, ~:;;;:;~;:;:;;;:~;;;:;;;;:;:;;;:;;:;;~'B' 26 15 CUit 14 CLT, +5V 1/4/o1A1489- -- A~ .,. L: CONNECT FOR 20 rnA CURRENT LOOP ---, R: CONNECT FOR EtA RS232 INTERFACE ~ ~ 13 0, 0, O. 0, "tl STR, 10 iff, H ~.v ! , DECODER! RaYR, 'fiR, DEMUX iSYii, iio BiYi, iio ii, DR iORST i.lIi t 14LS11 t;H )12 MRE! +5Y· BUSY + DONE FLAG LOGIC (FADM RESET SWITCH) ~--~~~~---------i., eLT, 74LS08 74LSoa ........,,0_ F9445 Fig. 8 F9445 Input/Output Connection Scheme (2 of 2) ii IBI 74LS240 i---=-- ..... iie ',' ii, 4,5 ii,o 8,7 I I I I E, • ..1 18 J. I '~' I I 17 I I IL E, ____ JI 18,17 IBla 18,'5 IBlg +IV U,13 1• 181,0 INTERRUPT 8,9 - -,. DE, MSKO 12,11 181" Po 10 ~~O A I ails ji'3 4,5 7..LS1.7 ,. 3 P, 11 SO, D, A, 0, Q3 P3 ,. 1 ',' i81,4 ...... DE, ji'2 p, ,. 00 LATCH 1/1~ STR8~ +5 V +SV PL DE, 1 0, INTRQ (9445) MASK LATCH BUFFER/DRIVER iin r-rJo--I>-_L MR • 74ts7. 11 MK14 0, CP, CD, MK15 iTO • 1. " MAB 1. DE, - 74LS240 SYN(94"5) 18,17 IBI,2 18,15 IBI'3 BUFFEA/DRIVER ii14 6,7 14.13 18114 ii,5 8,9 12,11 181,5 -IB IBI INTA~11,19 IBI OE"OE2 DATA TIME STRETCH ON Ito: +5V_.2- +5V +5V ....!. " .-D--....- 11 181g ,. 181,0 .8'11 9 181,2 ..,,!.! 7 181,3 L-!! 5 111,4 • 181,5 74LS240 ,...!. ADYD 181a , ,...!. 7405 18 . aUFFERJ iTiiiA - ....r-.... I D- t...!.! DRIYER Q CD ii-t-------' " 11 12 13 '4 15 INTA 0 1 0 CODE 01 1 TTl TTO 6-65 IT 0 ....... 17 F9445 Fig. 9 F9445 Dynamic Memory Connection Scheme Dynamic Memory Timing CLOCK ------1 ADDRESS DECODER 7 o-~::::::::::4:;:~rt-tl REF MUX +5. MUX ... ~O;jl3~~~r- REF CP AE RS L-=::::~t.~A13 ROVD 1. t--------.,.A, A6 Refresh Timing ~-----------r~+ .' ....-~"" ADDRESS 00 .~ AOC:~R o 1 Q 0 1 0 REF MEMORY ARRAY I4K.1. MEMORY ARRAY ·5. DATA 748114 ~~~=::;t.3"Ei"E1 DIN' COUT t ,. CP REF-----+ .~KS BUS SHIFT REGISTER CLOCK ADDRESSMUX AND REFRESH COUNTER M STRBD Note. 1. 2. 3. 4. 6-66 D,N connecled· to DOUT connected to Data Bus. All F16K devices have the same address lines and CAS. We line. Each bank of 16 F16K has a separate RAs line (4 banks). Each slice of 4 F16K is connected to a separate data bus line (16slices). F9445 The memory requires "refreshing" every 2 ms. The 9642 contains a 7-bit refresh counter. Every 15.63 ms (2/128), the memory controller enters "refresh" mode. This is synchronized with SYN to avoid any conflict. Another 74164 shift register controls the refresh timing which requires only an RAS strobe. After the refresh cycle, the refresh counter is incremented and the normal memory timing is resumed. The Console Request is set whenever any operation switch is pressed and is reset when the console code is read from the FPLA. The circuit provides for control of two processors sharing the same bus. All the switches are momentary-action type except the data switches and the select-processor switch. A full listing of the FPLA is shown in Table 2. The refresh cycle takes place when needed and may take place during non-memory processor cycles. In these cases, the processor is not halted, and the refresh cycle is overlapped. The console provides all F9445 console functions, including Self-Test, plus the additional function of Single-Step, and is compact enough to be implemented with all switches, lamps, logic and connectors on a double-sided . 17Y2-by-5V2-inch printed-circuit board. Different memory types have different speed requirements. These requirements can be met by changing the "taps" on the 74164 shift registers. . Console Control On an application board, a minimal console is usually required. The APL (automatic program load) function can be easily implemented by pulsing the Console Request line LOW. There are no critical timing requirements since this signal is latched internally. The F9445 will continue to execute APL commands until the Console Request is raised. Since the bus must be HIGH for the APL to execute correctly, bits 5 and 6 of the bus may be tied to +5 V through 3 kf1 resistors as pullups. For debugging and evaluation purposes, a console is a very useful tool. It gives complete control of the processor independent of software and memory operation. Since the console commands are microprogrammed into the F9445, a full console design is fairly simple, the simplest full console uses the F9470 console-controller circuit, which drives an RS232 terminal and contains two serial I/O ports and a timer. The F9447 I/O controller can also be used to provide some console functions. Interfacing to standard switches and lamps requires switch debouncing and encoding operations. The circuit shown in Figure 10 uses R-S latches for switch debouncing and an FPLA (93409) for switch encoding. Table 2 Console PLA Listing *P *P *P 'P 'P *P 'P 'P 'P 'P 'P 'P 'P 'P 'P 'P *P *P 'P -H-HHHHHHHHHL---H-HHHHHHHHL----H-HHHHHHHL-----H-HHHHHHL---H--H-HHHHHHL---L--H-HHHHHL-------H-HHHHL-----H-HL-H---L-----H-HL-H---L-----L-HL-H-----L---L-HL-H-----L---H--H-HHHHL-----L--H-HHHL---------H-HHL----------H-HL-------------L-----------HL-H-----------LL-H-----H------H-HHHHHHHHHH--- 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 *1 *1 *1 *1 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I 'I Key for Table 2: 'A Active level of outputs 'P Product term number 'I Inputs 'F Outputs Don't care H High level L Low level A = Active An address latch is strobed on every STRBA, and a data latch is strobed on every STRBD except "console code read." This results in the correct display on the lamps. The data switches are enabled with "console data read." A Single-Step function is included. This function requires two additional latches, plus some decode logic, and implements a Continue followed by a Halt. 6-67 *A *F *F 'F 'F *F 'F 'F 'F *F 'F 'F *F 'F *F 'F 'F 'F 'F 'F LLLLLLLL -----A---A--A---AA-A-----AA-----AA-A --A-AA----AAA----AAA----AAA-A ----AA-A ----AA----AAA-A --AAAA--------- ------A-----AA------A-----AA-----AA- Fig. 10 F9445 Console Connection Scheme (1 of 3) ,!. 1 ct I t 1 -5V 3k 1 I I A i i f. • 1 " 81,$2 '5V 2,' AS EI 10 10 DEPACO 5 • DEPAC1 1 7 11 I 12 " 13 I, LSI?1 QUAD LATCH ,. Ao I, I 11,12 DEPAC2 1. I DEPAC3 " ENCOD~R , " Sl,S2 2,' A'~ I, 931. 1 A'~ I, Q OEPS, ":' I 1 iDEPFD 1 4 Q £ i 1 SAME AS PLA PIN 1 • • 7 I, GS 1:.8279 QUAD LATCH ,. 1. !, !15 S OE ' - - 100 XI I I, '--- 11.12 'Ob Za~1"i, DEPFLAGS J " 1 13 DPe ,. I, lor. 1 1 1 " 81.$2 2,' Q * , jEXACO 5 ":' I I iEXAC1 I I I I I i i i i i I " 81,82 2,3 Q • ~ EXFD • 12 ,. ,. .--- I" I, - • I, AoD-- I, A'~ I" 9318 ENCODER 1 USD 11 15 EXAC. ~ 7 I" 10 11,12 " 10 LS279 QUAD LATCH , 1 7 2 • • • I, A, I, GS~X. I, 11,12 EXFLAGS " I , • ,. 5 ,. LS2?9 QUAD LATCH EXAC, ~ EX!C Zb~'ih LS2S? MULTIPLEXER DE. DC 1. EXPC " I SWITCH DEIOUNCE DPC ,. h -- SWITCH DECODE 6-68 7':!0. ..... XPC PIN 7 OF PLA 2;C~18, Fig. 10 F9445 Console Connection Scheme (2013) ,. +5V------~r-~--------~----------_r----------_,--------_r------------------------~ CS A, 1k 1405 RESET 01 18 LOGIC DUAL-PROCESSOR LOGIC ., 1 X2 I I X{ ~ : • , iio 10 k 0, 17 I iis X1113 15 4 As 0, 00 '8 0, 3 ,. I., A, M--''''........ . J O. STRSO 2 x, -------+-1; 15 iS7 A, 93459 FPLA 28 PIN ., 27 iis 0, I., A8 M 0, 00 13 05 I FETCH 2. STRBO A, STiiiA~ STABA STRiD~STRBD 23 J (RUN) A A" 22 A" 21 A" J 20 L __________-:::=:::;-;;;;:;;2n~d:;;F;:ET;:C:.;.H'---------1 A" SWITCH OEBOUNCE 6·69 CO&.N-S~O~L~E~C~O~D'~PLA F9445 Fig. 10 F9445 Console Connection Scheme (3 of 3) DATA LAMPS +5 V '\ 18 ADDRESS LAMPS +5V .5 V '\ 270 iio iio IB, ii, iBz IBz iib 183 ii4 ii4 iiis iiis ii6 iS 6 iB7 li7 270 74LS240 " +5 V DRIVERI BUFFER (RUN) • 14 (CARRY) B 12 (ION) • 74" (RUN)A 74.. (CARRY)A (lON)A 15 ,. 00 0, .". STRSA ii 11 +5 V E, W 00 E, 18 270 iiie Do 10 k 74LS240 0, D58* ii W 4 ,. ii g D, 0, fi9 OCTAL LATCH BUFFER 14 M~M 74LS04 " iilO D, iii 10 iill D3 ii'1 74LS04 13 oo~oo mIl 13 D. O. ii12 D5 05 ii13 0, 0, 1814 D7 0, 14 ii13 iil4 iBIS 17 ,. 14 9£-9 DATA SWITCHES 6-70 'iBIS +5V 270 rae 74LS373 DRIVER! 01~O' 00 17 F9445 A Multiprocessor Scheme There are many ways to envision two or more processors working concurrently. The method of interconnecting the processors depends on the application and the performance objectives. Listed here are a few of the options. completely shared resources, does not give as high performance as the Local and Common Memory scheme. However, for certain applications and for two processors only, this scheme can give a considerable performance increase over a single-processor system with very little hardware overhead. This scheme is described in the following paragraphs. Independent Operation For those processors which can be made to run independent tasks, this provides the most efficient scheme. Each processor has independent memory and resources. A general scheme for two tightly coupled F9445 processors is shown in Figure 11. The processors share a common bus and an arbiter selects which processor uses the bus and multiplexes the control lines accordingly. The 1/0 arbitration scheme is very simple: each processor assigns the bus to the other processor when it commences any cycle that does not use the bus, as long as BUS LOCK is not set. Shared 110 Each processor has its own memory but shares an 1/0 bus. This allows high-speed operation while minimizing system resource requirements. Local and Common Memory This gives a good compromise between performance and resource requirements. Each processor normally runs from its own memory at high speed. Accesses to a common memory are rarer and, because of the arbitration problems, slower. The scheme is most efficient when the instruction mix includes many "long" instructions, such as Multiply, Divide, Parametric Shift and Normalize. Since only one processor is using the bus at any time, the synchronization signals RDYA and RDYD can be the same for both processors. However, the interrupt request (INTREQ) and data-channel request (DCHREQ) lines should be separate to avoid any conflicts in 1/0 handling. Tightly Coupled Two or more processors share the same memory and 1/0. This scheme is easiest to implement but, because of the Fig. 11 A Possible General Multiprocessor Scheme RDYD --I----l>--~ RDYA--_----! INFORMATION BUS CONTROL BUS ~IIiIOo. 010 VI] SYN mn !ITImI 6-71 F9445 F9445 Inslruction Execution Times Execution Times Instruction . Clock Cycles 16 MHz 20 MHz 24 MHz COM NEG MOV INC ADC SUB ADD AND OR MUL MULS DIV (Normal) DIV (Overfiowl DIVS (Normal 1 DIVS (Overflow) NORM 6 6 6 6 6 6 6 6 6 70 70 86 14 114 26 10+ 4n 0.375 0.375 0.375 0.375 0.375 0.375 0.375 0.375 0.375 4.375 4.375 5.375 0.875 7.125 1.625 0.625 + 0.25n 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 3.5 3.5 4.3 0.7 5.7 1.3 0.5+ 0.2n 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 2.9 2.9 3.6 0.58 4.7 1.1 0.42 + 0.17n SLLD SALD SARD SLRD SKNV JMP JSR ISZ DSZ LDA STA LDB STB PSHA POPA PSHF POPF POPJ PSHR TOPR TOPW MTSP MTFP MFSP MFFP SAY RET DSP NIO SKP DIA/B/C DOA/B/C ETRP DTRP E64K D64K 10+4n 10 + 4n 10 + 4n 10+ 4n 14 6 6 22 22 12 12 24 26 16 16 16 16 16 16 16 16 6 6 6 6 60 80 6 12 16 12 12 10 10 10 10 0.625 + 0.625 + 0.625 + 0.625 + 0.875 0.375 0.375 1.375 1.375 0.75 0.75 1.5 1.625 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.375 0.375 0.375 0.375 3.75 5.0 0.375 0.625 1.0 1.0 1.0 0.625 0.625 0.625 0.625 0.5 + 0.5 + 0.5 + 0.5 + 0.7 0.3 0.3 1.1 1.1 0.6 0.6 1.2 1.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.3 0.3 0.3 0.3 3.0 4.0 0.3 0.6 0.8 0.6 0.6 0.5 0.5 0.5 0.5 0.42 + 0.42 + 0.42 + 0.42 + 0.58 0.25 0.25 0.92 0.92 0.5 0.5 1.0 1.1 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.25 0.25 0.25 0.25 2.5 3.3 0.25 0.5 0.67 0.5 0.5 0.42 0.42 0.42 0.42 0.25n 0.25n 0.25n 0.25n 0.2n 0.2n 0.2n 0.2n Notes Times for no-skip or unfulfilled skip; for fulfilled skip; add 0.3 (0.25 at 24 MHzl n - number of steps needed for normalization. Time is 0.710.591 if n=O. n - number of shifts; time is 0.710.591 if n=O. 0.17n 0.17n 0.17n 0.17n Times for page-zero addressing; add 0.3 10.251 for indirect; add 0.3 10.251 for auto-increment/decrement; add 0.210.181 for indexed. • Note: Execution times are given for 20 MHz and 24 MHz clock. The clock may be operated from> 0 to 24 MHz within the specified temperature and voltage range. 6·72 F9445 Fig.12 ALU Cycle Timing" SYMBOLANC (PIN II) so S1 S1A S5 so S1 eLK (40) SYN (7) 00 (34), 0, (35) M(36) RUN (37) --1----+----4-_..1 TAlC) ABORT (32) Fig. 13 Minimum Memory Cycle Timing" SYMBOL AND (PIN If) elK (40) 00 (34), 0, (35) M(36),W(1), al1SfiM (38) SVN (7) STABA (5') iB (11-26) READ ii (11-26) WRITE STRBD (6) ·See Timing Parameter Symbol Conventions at end of data sheet. 6·73 S1A F9445 Fig. 14 Extended Memory Cycle Timing" SVMBOlAND (PIN') WAIT FOR RDVA RDVA RECOGNIZED GENER- ....m.. STRBD I RDVD RECOGNIZED S4 ClK (40) 00 (34). O. (35) M(36). W(l). BUSREQ (38) SVN(7) S'fRiiA (5) ROVA (4) iii (11-26) READ iii (11-26) WRITE S'f'iiBo (6) RDVD(8) ·See Timing Parameter Symbol Conventions at end of data sheet. 32 WAIT FOR RDVD 6-74 F9445 Figure 15. Bus and Status Control Timing' SYMBOL AND (PIN .) ClK (40) S1 SO S1G S4 S3 S2 S5 _rLfLiLrLn.rLJiLrL I:: - 1- TC(S) TC(S) SYN(7) TC(SD)- - 1- ffiiiB (6) TC(SA) ::j S'i'RBA(5) TBG(Cl--j BUSGNT(3) 1- iNTiiEa (30) l TRE(t)-I_ I-TC(BG)X - I :::j ; TA(C) - -TC(BR)] iiiJsREci (38) CARRY(39), INTON(27) - TC(CY) ,I; -TC(R)j RUN (37) ~ TC(BL)I- iiiJSlOci( (2) WAIT FOR BUS GNT - I - T C ( REQ)x r-TDRL~ IT - TA(C) j - T C ( SO) --r-~ I DCiiREl'l (29) - r-;: wi fR TC(SD) HTC(SA) CONREa(28) MR(33) DCiiREl'l (29) AiiOiii' (32) so t: BUS GNT RECOGNIZED ·See Timing Parameter Symbol Conventions at end of data sheet. ··If this DCH REQ set-up time Is missed, it is not recognized for another complete cycle. 6-75 • F9445 Guaranteed Operating Ranges Part Number Supply Voltage (Vecl Min Typ Max 4.75V 4.5V F9445DC F9445DM 5.0V 5.0V Case Temperature 5.25V Oto + 75°C 5.5V - 55 to + 125°C DC Characteristics (Over guaranteed operating ranges unless other wise noted.) IINJ(min) 375 mA; IINJ(max) 425 mA = = Symbol Characteristic Min V'H Input HIGH Voltage 2.0 VIL Input lOW Voltage Veo Input Clamp Diode Voltage VOH Output HIGH Voltage; RUN, CARRY, INTON, SYN, STRBD, BUSREQ, STRBA, 0 0 ,0 " M 2.4 VOH Output HIGH Voltage; IBIO• ,51 , W 2.4 VOL Output lOW Voltage "H Typ -0.9 Max Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input lOW Voltage -1.5 V Vee = Min. "N = -18 mA, "NJ = MIN V Vee = Min, IOH = -400/LA, "NJ = MIN 3.4 V Vee = Min, IOH = -1.0 mA, "NJ = MIN 0.25 0.5 V Vee Input HIGH Current; DCHREQ, INTREQ, ClK, MR, RDYA, RDYD, ABORT, CONREQ, BUSGNT 2.0 40 /LA Vee = Max, V'N = 2.7 V, "NJ = MIN "H Input HIGH Current; IBIO' 151 (3-state) 5.0 100 /LA Vee = Max, V'N = 2.7 V, "NJ - "H Input HIGH Current; All inputs 1.0 mA Vee = Max, V'N = 5.5 V, "NJ = MIN III Input lOW Current; All Inputs -0.4 mA Vee = Max, V'N = 0.4 V, "NJ = MIN lozH Output O.£F State (High Impedance) Current IB 0.15' W 100 /LA Vee = Max, Vour = 2.4 V, "NJ = MIN lozL Output O.£F State (High Impedance) Current IB. 0 . '5 -400 /LA Vee = Max, Vour = 0.4 V, "NJ = MIN 10zL Output O£..F State (High Impedance) Current; W -100 /LA Vee = Max, Vour = 0.5 V, "NJ = MIN 10sH Output Short Circuit Current; All Outputs Except BUS lOCK -100 mA Vee = Max, Vour = 0.0 V, "NJ = MIN 1.0 mA Vee = Min, VOH = 5.25 V, "NJ - MIN 350· mA Vee = Max, "NJ = 300 MIN ' LOH Icc V'NJ 3.4 -0.21 -210 -15 Output leakage; BUSlOCK Supply Current 200 Injector Voltage 1.3 'Not more than one output to be shorted at a time. 6·76 V = Min, IOL = 8.0 mA, "NJ = MIN "NJ = 400 mA MIN F9445 AC Characteristics Te = 0 to 75'C; Vee = 4.75 to 5.25 V; IINJ = 375 mA; C L = 15 pF. Input conditioning: Rise Time = 6 ns; Fall time = 6 ns; Amplitude = 0 to 3 V Refer to Symbol Conventions at the end of this data sheet for explanation of the timing parameter symbols. Min Typ Max Unit Symbol Characteristic TC(O) TC(S) Propagation delay, ClK to 0 0 , 0 " M Propagation delay, ClK to SYN 30 ns TC(W) ns 60 ns Propagation delay, ClK to Vii 70 TC(W)z Propagation delay, ClK to Vii going 3-state 70 ns TC(IBA) Propagation delay, ClK to IB,o'15" address 60 ns TC(IBA)z Propagation delay, ClK to IB,o"5(, address, going 3-state (read cycle) 35 ns TC(SA) Propagation delay, ClK to STRBA 30 ns TC(IBD) Propagation delay, ClK to IB,o"5(, data out 75 ns TC(IBD)z Propagation delay, ClK to IB'O-15), data out, going three-state 35 ns TC(SD) Propagation delay, ClK to STRBD 25 ns TRA(C) TC(RA)x Setup time, RDYA to ClK Hold time, ClK to RDYA 3 10 ns ns TRD(C) TC(RD)x Setup time, RDYD to ClK Hold time, ClK to RDYD 2 10 ns ns TIBD(C) Setup time, IBIO. ,5), data in, to ClK (read orfetch cycle) 75 ns TC(IBD)x Hold time, IB,o.'5), data in, after ClK (read or fetch cycle) 25 ns TREQ(C) Setup time, INTREQ, DCHREQ, CONREQ, MR to ClK, all are the same timing relative to S5 15 ns TC(REQ)x Hold time, INTREQ, DCHREQ, CONREQ, MR after ClK, all are the same timing 20 ns TDRh(C) Data channel (DCHREQ) off setup time from ClK (to finish data-channel cycle) 100 ns TA(C) Setup time, ABORT to ClK 30 ns TC(Bl)1 Propagation delay, ClK to BUSlOCK going lOW 35 ns TBG(C) TC(BG)x Setup time, BUSGNT to ClK Hold time, ClK after BUSGNT 10 10 ns ns TC(R) Propagation delay, ClK to RUN 80 ns TC(CY) Propagation delay, ClK to CARRY 50 ns TC(INT) Propagation delay, ClK to INTON 50 ns TC(BR) Propagation delay, ClK to BUSREQ 40 ns 6-77 • 35 F9445 Timing Parameter Symbol Conventions The abbreviated symbols used for ac characteristic timing parameters in this data sheet are defined as follows: The timing symbol convention is: TAb(C)d The timing symbols all begin with the letter "T". The second position, represented by "A", indicates the signal node beginning the interval. The position "b" defines the direction of signal transition at the beginning node "A", if such definition is necessary; the new state of the signal may be: I = Low; h = High; z = 3-state; x = Don't care; v = Valid The position "C", which always appears within parentheses, indicates the signal node ending the interval. The position "d" is the same as "b" but refers to the state of the signal at the node indicated by the mnemonic in position "C". Ordering Informalion ORDER CODE SPEED TEMPERATURE For other temperature ranges, contact Fairchild Sales Office. All packages are 40·pin ceramic DIPs F9445-24 DC F9445-24 DM F9445-24 DMQB 24 MHz 24 MHz 24 MHz O°C to +75°C -55°C to +125°C -55°C to +125°C F9445-20 DC F9445-20 DM F9445-20 DMQB 20 MHz 20 MHz 20 MHz O°C to +75°C -55°C to +125°C -55°C to +125°C F9445-16 DC F9445-16 DM F9445-16 DMQB 16 MHz 16MHz 16 MHz 0°Cto+75°C -55°C to +125°C -55°C to +125°C . Connection Diagram 40-Pln DIP (Top View) W BUSlOCK BUSGNT RDYA CARRY "iiiSiiEQ RUN STRBA ii Si'iiiiii" 0, SYN RDYD GND IINJ ii15 00 iiii AiiOii'i' Yee iIi'i'iiEQ ii14 DCHREQ ii13 CONREQ ii12 INTON jil1 iiio jilO ii, iio ii2 iii, iis m7 ii. 6-78 ClK iii. iis A Schlumberger Company F9446 Dynamic Memory Controller Advance Product Information Microprocessor Product Description Connection Diagram FAIRCHILD The Fairchild F9446 Dynamic Memory Controller (DMC) is designed to support a variety of memory configurations and provide an Interface between 16K and 64K memory chips and the F9445 central processing unit (CPU). It provides a 16-blt memory address register (MAR), an address multiplexer for the row, column, and refresh addresses, a timing generator for the row and column strobe signals and the write enable signal (RAS-CAS-WE), mode arbitration, and page mode logic. It is implemented in 13 ll!> bipolar technology with low-power Schottky-compatible inputs and outputs. vee iiASo m, !IllS:. !Ina ~ WE fS lmlSIiEl:I f.mJRNT RDYD • • • • • • • • • • • • • PAGE 16-blt Memory Address Register Ability to Accommodate a Variety of Memory Speeds 18K or 64K DRAMs Automatic Page Mode Internal Refresh Address Counter Row/Column/Refresh Multiplexer Complete Memory Timing Signals Three-state Outputs for Multlport Memories Internal Refresh Rate Timer low-power Schottky-compatlble 110 13l Bipolar Technology 84-Pln DIP Operetlng Temperature Range of from - S5°C to + 125°C ~ liLYCAS' DlYEND GND RFSH RDYM IlI:Yl:O[ WRITE" ClK STATiC S'I'Imi SPEED 1/256K SPEEDO/RMW MEX TlMODE BANKS TYPE A,s 6-79 • F9446 The F9446 incorporates an address multiplexer and memory timing generator for use with both static and dynamic memories. The multiplexer selects between row and column segments of the internal 16-bit memory address register (MAR) or an internal refresh address counter (RAC). The upper two address bits provide bank information, while the lower seven, eight, or nine address bits are multiplexed to provide row, column, and refresh address. Assertion of the static line supresses row/column multiplexing of the memory address register outputs, which then provides the full 16-bit address. Signal Descriptions CLOCK MEMORY HANDSHAKE MEMORY BUS { CONTROL INFORMATION SUS MEMORY ADDRESS The memory timing sequence is initiated by the memory execute signal; it may be inhibited or aborted by removal of the chip select signal. Once started, the memory timing sequence is automatic. A choice of four speed grades accommodates a variety of memory access times, and external controls may be used to further modify the timing. 18 8 ii, ii. iSs iii4 ii3 182 STRAPS FOR MEMORY TYPE SPEED SElECTION iii1 ilio OPTIONAL { DECODED INPUTS STATIC The four individual RAS lines accommodate from one to four banks of memory chips, with automatic satisfaction of precharge requirements for memory access and refresh, in page mode or not, with distributed refresh or bulk refresh. Refreshes are initiated to satisfy a rate of 128 per 2 ms per RAS bank. For short intervals, they mayautomatically be deferred until non memory CPU cycles; this makes them semi-transparent. RFSH A memory bus request and memory bus grant are provided to govern 3-state control of memory interface signals for multi port or DMA purposes. 6-80 F9447 F=AIRCHILO A Schlumberger Company 110 Bus Controller Advance Product Information Microprocessor Product Description • • The F9447 1/0 Bus Controller (IOC) is used with the F9445 13 L@ 16-Bit Bipolar Microprocessor to demultiplex the 1/0 instruction and data of the information bus (I B)_ It provides all the timing and decode signals required for programmed or data channel (DCH) inputloutput to peripheral device controllers_ In the NOVA@ -compatible mode, the F9447 provides all the timing and Signals required by that 1/0 bus_ For DCH transfers, address generation and handshake can be handled by the F9449 Multiple Data Channel Controller. • • • • • • • • • • Interfaces Directly to the F9445 Controls Standard and High-Speed NOVA-Compatible Data Channels NOVA-Compatible or F9445 1/0 and Data Channel Timing Complete NOVA-Compatible I/O Bus Interface Automatic Program Load Power·Up Reset Delay Console Interface Local Busy/Done/Interrupt Logie Low·Power Schottky.Compatible 1/0 64·Pin DIP or Optional Chip Carrier Package 13L Technology Operating Temperature Range of from - 55°C to +125°C Signal Functions CLOCK cpu HANDSHAKE 1- Connection Diagram CLK - SYN ~~~~A 1_____ STRBD 10PRI DIA jj]Jj RDYD CLK CLEAR AI'rn START (BUSY) CONREQ l'iJLSE (INTPOUT) SKP Cpu CYCLE TYPE l:lm1]j llTC iN'i'A DOA DOB DOC IORST MSKO II START CLEAR PULSE } OUTPUT PROGRAMMED 1/0 STROBES (DONE) CONCD OOA ROENB liOB GLOBAL DOC 0577 iB, M W elllISfP fI!. fI!, fI!. ~ iBs I CONTROL ! (STRBDN) I/O HANDSHAKE FIELD RESET 1/0 SYNCHRONIZATION 189 } DATA BUFFER CONTROL j-II1R 1- CONSOLEIIO SELECT _ MACAi' G':9!!.A.!:. _ _ _ _ _ _ CONEN CON REO CONCD APLEN ~__~__r-~CO_N_L~D~__ GLOBAL = L STAT~~,~~ni 1_ - ~ ! ~,s::~~ BUSY DONE INTPOUT CONLD STRBDN INTPIN ® ® DCHA MSKO DCHO DIA DCHI DfB DlC 10CS I/O PORT STATUS OUTPUT i t II NJ INTA GND DCHMO r......-:----.----..---.1 Vee GND DCHREQ CONSOLE CONTROL OUTPUT GNO I'L is a registered trademark of Fairchild Camera and Instrument Corp. NOVA is a trademark of Data General Corporation_ 6-81 10RST SKP MRCAP OlEN GND Vee msw (STRBSY)~ DATA CHANNEL HANDSHAKE ----+- iBs ~ (INTPIN) II IIO{=: ; : INSTRUCTION ------ 187 Vee CONEN (MSKBIT) f5Ej( STRBD SYN DOEN STRBA DSEN RDVD 10BSY RYDA RDYM DCHEX 00 0, IOENA Wo ME W, INJ W, II F9447 The F9447 1/0 controller is a decoder and timing generator for programmed 1/0 Instructions and data channel transfers. The timing sequence is selected via a three-bit control code, WO-W2• Additional logic is included to implement either the basic console interface or a busy/donelinterrupt function. A hysteresis circuit for deriving a power-on-reset, from an external capacitor to ground, Is also included. Figure 1 is a typical block diagram of the F9447 1/0 controller. Figure 2 shows how the F9447 can be used with the F9445 system. Signal Description Table 1 describes the F9447 signals. Figure 1 F9447 Block Diagram PERIPHERAL CONTROL BUS F9445 ~~~TROL _ _--,/I BUSY/PONEI INTERRUPT OR CONSOLE INPUT BUSY/DONE/ INTERRUPT OR CONSOLE OUTPUT OLOBAL-------------J 6-82 F9447 Figure 2 System Configuration DEV. OOI--__...J CODE ~I---------+--~ D~7~------------~ • CONSOLE CODE CONSOLE DATA ·OPEN COLLECTOR OUTPUTS, REQUIRE PULL·UP RESISTORS. 6-83 F9447 Table 1 F9447 Signal Descriptions Pin No. Name Description 2 Clock A synchronizing input signal primarily for timing non·F9445 mode intervals through a state counter clock on alternate positive edges. SYN 41 Synchronize An input signal from the CPU that maintains system timing. STmiA 40 Strobe Address An active low input signal that indicates an address portion of the CPU cycle (and instruction during I/O execute). RDYA 38 Ready Address An active high open·collector output signal that allows the CPU to continue beyond the address portion of the cycle. S'fRBD 42 Strobe Data An active low input signal that indicates the data portion of the CPU cy~le. RDYD 39 Ready Data An active high open·collector output signal that allows the CPU to continue beyond the data portion of the cycle. RDYM 28 Ready Memory A bidirectional, open collector signal; an active high input during a data channel output cycle indicates that the memory has fetched the data. An active high output during a data channel input cycle indicates to memory that the input data is valid and a write may proceed. ME 31 Memory Enable An active low output that modifies the memory controller to respond for CPU memory accesses or for data channel cycles (ME=M+0 Mnemonic Clock ClK CPU Handshake Memory Handshake 1.°0). CPU Cycle Type M 10 °1 °0 36 37 iN 11 Memory ° Lines Write An active low input from the CPU that indicates a memory type of cycle. A pair of input signals from the CPU to indicate the type of cycle. An active low input signal from the F9445 that indicates a cycle during which data is to be written to a memory or I/O device. 6-84 F9447 Mnemonic Pin No. Name Description 10PRI 1 1/0 Priority An active high input that enables the F9447 to begin an 1/0 or data channel cycle. 10CS 24 1/0 Chip Select An active high input enables strobes for busy and done, as well as 1/0 control decodes. ITS 77 9 Device Select 77 An active low input signal that indicates a decode of iB1O-iB15 all active, a device code 77 (CPU class) 1/0 instruction. 10ENA 30 1/0 Enable An active high input that, when low, inhibits response by the F9447 to any F9445-programmed 1/0 cycle. Used with multiple F9447s to allow disables. DCHREQ 22 Data Channel Request An active low input that indicates there is a data channel request. W2 W1 Wo 110 Instruction Field 33 34 35 Timing Options A three-bit input code; the decodes provide a selection of timing for 1/0 and data channel cycles. iB5-iB9 52-56 Information Bus Active low input signals from the F9445 containing 1/0 instruction bits 5 through 9 during address phase of 1/0 execute cycles. MR 13 Master System Reset An open-collector bidirectional pin that, when pulled low, initializes the F9447 and activates 10RST. Also an output generated by a low level on MRCAP. MRCAP 17 Capacitive Reset An active low input with an internal resistive pullup of 10K ohms to Vee . Cycle Enable Peripheral Timing Mode Select Reset • The F9447 does not modify the F9445 timing for the following control instructions: READS, ION, APL, HALT. 6-85 • F9447 Table 1 F9447 Signal Descriptions (Cont'd.) Pin No. Name Description 8 Global (Local) An input that selects one of two uses of the global and local modes. DIA DIB DIC INTA 46 45 44 49 Active low timing strobe outputs that indicate execution of data input instructions. SKP 50 Data·ln-A Data-In-B Data-In-C Interrupt Acknowledge Skip DOA i50B i50C 59 58 57 Data-Out-A Data-Out-B Data-Out-C Timing strobe outputs (all active low except active high MSKO) that indicate execution of data output instructions. 10RST 51 I/O Reset An active low output that indicates either a decode of the execution of the 10RST instruction or a system reset caused by MR or MRCAP active. MSKO 47 Mask Out START CLEAR PULSE 61 62 60 Start Clear Pulse Active-low control outputs that indicate decode and time of start, clear, and pulse control functions during programmed I/O execution. OS EN 26 Device Select Enable An active low output that enables device select. 10EX 43 I/O Execute An active low output indicating that the F9447 is involved in the execution of a programmed I/O cycle. 10BSY 27 I/O Busy --DCHEX An active low input indicating that another source is using the I/O bus. An active low output is provided when the F9447 is about to or is executing an I/O cycle. 29 Data Channel Execute An active low output indicating that a data channel transfer is in progress. DCHA 18 Data Channel Address An active low timing strobe output that defines address transfer time of a data channel cycle. DCHI 20 Data Channel In An active low timing strobe output that defines data transfer in (write to memory) of a data channel cycle. Mnemonic Console I/O Select GLOBAL Programmed I/O Strobes I/O Handshake Data-Channel Handshake 6-86 F9447 Mnemonic Pin No. Name Description DCHO 19 Data Channel Out An active low timing strobe that is output during data transfer out (write to peripheral) of a data channel. DCHMO 23 Data Channel Mode Out An active high input results in data channel output cycles. 7 Request Enable A timing output that synchronizes interrupt and data·channel priorities. -OlEN 21 Data In Enable An active low output that enables peripheral data onto the F9445 information bus during programmed 1/0 or data·channel input cycles. DOEN 25 Data Out Enable An active low output that enables information bus data onto the peripheral data bus during programmed 1/0 or data· channel output cycles. 110 Synchronization RQENB Data Buffer Control -~-- Console Control Input -- • CONSW --- 15 Console Switch An active low input with internal 2.4K·ohm pullup resistor to Vce and digital delay of approximately 3 ms to eliminate contact bounce. CONSTP 12 Console Step An active low input with characteristics of CONSW that initiates a console request lasting for two console code cycles of the F9445. APLSW 14 Auto Program Load Switch An active low input with characteristics of CONSW and CONSTP that initiates a console request cycle with APL enable active. --CONEN 63 Console Enable An active low output to enable a console to provide information to the IB of the F9445 during a read or write operation. CONREQ 5 Console Request An active low output to the F9445 to request console service. CONCD 6 ConsOle Code An active low output to enable the console code onto the IB of the F9445 in response to a console code cycle of the F9445. --APLEN 4 Auto Program Load Enable An active low output initiated by an APLSW input or the execution of (DOA ac, CPU) instruction and terminated by the execution of a (OOAP ac, CPU) instruction or system reset. CONLD 3 Console Load An active low output to enable the console to latch data from the IB of the F9445. Console Control Output 6-87 F9447 Table 1 F9447 Signal Descriptions, Cont'd. Mnemonic Pin No. Name Description MSKBIT 63 Mask Bit The local logic contains an interrupt disable flag loaded from a select bit of the F9445 information bus during the execution of a mask out instruction. The MSKBIT signal is driven by that selected bit of the IB; a low level at the beginning of MSKO execution sets the interrupt disable flag. STRBSY 15 Strobe Busy A negative·going input edge that strobes the BUSY flag to the clear state. STRBDN 12 Strobe Done A negative·going input edge that strobes the DONE flag to the true state. INTPIN 14 Interrupt Priority In An active high input that determines which peripheral device may interrupt. BUSY 5 Busy Flag An active high output of a flip·flop is set by the execution of an 1/0·Start cycle with 1/0 Chip Select (IOCS) high; and cleared by a similar 1/0·Clear cycle, by a negative transition on STRBSY, by execution of an 10RST Instruction, or by a low level on MR. DONE 6 Done Flag An active high output of a flip·flop is set by a negative transition on STRBDN; cleared by the execution of an 1/0·Start or 1/0·Clear while 1/0 Chip Select (IOCS) is high, by the_ execution of an 10RST instruction, or by a low level on MR. INTPOUT 4 Interrupt Priority Out An active high output that determines which peripheral device may interrupt. CONLD 3 Console Load An active low output that enables the console to latch data from the F9445 information bus. Vcc 64 Power Supply Nominal IINJ 32 Injection Current Constant current (80 mAl obtained by using a dropping resistor from Vcc (nominal V1NJ 1.3 V). Use of bypass capacitor to GND is desirable. GND 16,48 Ground Common power and signal return. 1/0 Port Status Input 1/0 Port Status Output Power + 5 V DC. = 6·88 F9448 Programmable Multiport Interface F=AIRCHILO A Schlumberger Company Advance Product Information Microprocessor Product Description • • The F9448 Programmable Multiport Interface (PMI) is 64 pin bipolar 13L device that facilitates the interface between an F9445 16-bit bipolar microprocessor and many industry-standard input/output (1/0) devices. It decodes 110 instructions and memory addresses from the central processing unit (CPU) to communicate with devices tied to its four external ports. When used with the F9449 Multiple Data Channel Controller, it handles peripheral selection and timing during data channel cycles. Some of the features of the F9448 are: • • • • • • • • • Compatibility with Many Industry-Standard Interfaces Ability to Implement F9445-Programmed I/O Flags Interrupt Arbitration and Response Handling Fabricated in 13 L® Bipolar VI-SI Technology Operating Temperature Range - 55° to + 125°C 64-Pln Package Low-Power Schottky Compatible I/O The F9448 PMI ties the F9445 CPU to many industrystandard microprocessor interfaces. It easily links I/O devices designed for the F6800 or 8080 buses and those directly suitable for the F9445 I/O bus. The system configuration in figure 1 shows how the F9448 can be used to interface F6800, 8086 family I/O devices or the F3870 to the F9445 system. Four Independent I/O Ports Memory-Mapped and Programmed I/O Interface with Serial, Parallel, DMA, and Other Special-Purpose Devices Programmable Peripheral Timing • I'L is a registered trademark of Fairchild Camera and Instrument Corp. Connection Diagram lB. lB. ii, iil0 iis vcc CLOCK I IB, CPU{ HANDSHAKE M:~~~ I SfRiiDiii, ii, ii, iii, ii, iio STRBBZ. Mii ii11 i8 12 iB13 ii14 IB" PS, RDYP STRBDN, RDYM STRBBl, RDYD PS:. o. STRBDN, 0, GND STRBBl, PS, STRBDN, STRBBl, PS, CSC. II Signal Functions CPU CYCLE { TYPE (MSB) PS, ABORT CLK INFORMATION BUS PS, STRBBl, STRBDN, DCHACK, INTPOUT INTPIN DIRN SYN OUT, OUT, STRBD STRBA OUT, iN OUT. DCHACK, OUT, DCHACK, OUT. DCHACK, IINJ iiCiiAcK. PERIPHERAL CONTROL AND ADDRESS BUS STRBBZ. STRBDN. DCHACK, STRBBl, STRBDN, DCHACK, IT BuffiiA } } READY PERIPHERAL M CSC, OUTo DATA } BUFFER/LATCHES CONTROL JiS. GND CSC, IE BUFENA DIRN OUT. OUT, OUT, OUT, OUT, OUT, OUT. PS, STRBBl, STRBDN, iiCHACK, INTERRUPT' PRIORITY CHAIN 1 M:~~~~ { Vee GND 6-89 IINJ PERIPHERAL PORT CONTROL F9448 Figure 1 System Configuration USEADPTlON DCHReQ .ma i ~ DIRN OUT5 OUT, OUTo _0, RDVP ~ 9 RDYA + - ROVD elK -- - - := +-- fiR 2 elK ROVD elK ~ Mli '" . J.r>- ~ rV '--- - t f....:S'f'Rii5Ji3 f....:DCii.A'C'K f....:Pia vcc- - INTPIN - INTPOUT f....:I-DCHACK2 I-Si'RiliZ2 Si'Ai"DN 2 r--- .3453 ..:...- r-- PROM DCHREQ _ME = = = csi--- 1- ~A ..:...- 93471 AAM ADDRESS y DOUT ~ L.J fI REa,. 0, Pin 'YN Ten STRiiA B'M" DCHPIN !""""""+ Mli L .......... -'::::5l La( - USER OPTION _'OJ 1-- PEA 4 PORlS DIRINT iio -iiiS USER OPTION --'- t .A 1 - ) OUTS (STD) OlEN ~ Ne Si ""::"Ne elK t A DCHPOUT ~Ne STRap WE ME 'Ii iTRiD 6-90 0 ~ A ... OIRCON" RDYA - I--:-"'~ 1=:1\ tDEN DCHACK n 0, 110 DEVICE 82XX ~ PSn ~ iffii _M STRBA A 0 MAREN ..... w ~ A MEMORY ADDRESS REGISTER g- I-I-OCHACK. I-S'i'iiiiDR" STRBBZ3 I ~ = .~- STABBZ. STRBP ~ ~ ps. S'fAiiA DCHACK, 0,0, f....:- SYN 1..DECODER. ~ ~ OU13 _M STRSP ~ OUT. _0, ~ DIA I OUTs M- ~ I esc, Ne"":' RDYM 0,- STRBA CONREQ iNfREQ ENA BUFENA DUl a 1=9445 0, MICROPROCESSOR SVN ~ esc, _w w- ~ i:E FIM48 PMI CSC2 _r-_ 180 - IB15 C r- ~ _ _ 'Bo-IB15 ABORT f--- r-- ·OPEN COLLECTOR OUTPUTS REQUIRE PULL·UP RESISTOR 110 DEVICE F9448 Registers 11-bit memory-base address register used in conjuction with memory·mapped 110. Figure 2 shows the F9448 program-accessible registers. Each port has a 16-bit configuration register and busy, done, and interrupt-disable flags. Port 4 also has an Figure 2 F9448 Software Model PORT4 CR(4) I ~ 0 I FORMAT I TIMING 1 I 2 - 3141s I MASK BIT 6 1 7 1 6 1 9" 8 4K PORT3 CR(3) I I FORMAT 32 S12 TIMING I I MASK BIT I DEVICE CODE ~-0~1~1~'~2~3~1~4~'s~6~1~7~'8~'9~;~0~'1~1~'1~2~11~3~'1~4'~1~5- PORT2 TIMING 3 PORT1 CR(1) I o PORH CR(O) I Po I FORMAT I 1 I 2 3 1 4's TIMING I 4'S P2 P, MASK BIT 6 I 11 ' 12 MASK BIT 617 1 a I DEVICE CODE 1 7'6' I 13 ' 14 ' 15 I DEVICE CODE l 11 ! 12 I 13 I 14 ' 15 !J PORT ENABLES P, I p. 1 BLOCK SIZE IMMP I ~·1 PULSE ENABLE r\ I 10 = 4K ; 7 = 31' 1 ~ P, P2 P, P.l--"1..l ~0~-1~~2~~3~~4-L~5~~6-r~7~~a-L~9~~1~0~~11~~1~21-~13~~14~~1~5- 6·91 • F9448 1/0 Ports Transactions between the F9448 and peripheral devices are organized using several select, address, and timing signals. Out 0- 6 signals are shared by all ports, while each set of Peripheral Port Controls is associated with a specific port. The F9448 performs selecting and handshaking with connected peripheral devices. It has five bidirectional ports numbered 0 through 4. Port 0 is used as a bootstrap port by the F9445 to read and write, address and configuration registers inside the F9448; ports 1 through 4 are used to communiate with external peripheral devices. Ports 0 through 3 respond only to programmed 1/0 instructions; port 4 responds to either 1/0 instructions or memory cycles. This latter feature enables a block of up to 4096 memory addresses to be used for memory-mapped 1/0. Table 1 Signal Descriptions Table 1 describes the signals for the F9448. F9448 Signal Descriptions Pin No_ Name Description 45 Clock Input signal from the positive-edge-triggered master clock from which all F9448 timing is generated. SYN 40 Synchronize An input signal from the F9445 for synchronizing the F9445 with external devices. Active during every CPU cycle. Si'RBA 38 Strobe Address An input signal generated by the F9445 during external bus cycles. S'fR"Bi5 39 Strobe Data An input signal generated by the F9445 during data transfer time and used by F9448 to organize transfers. RDYD 52 Data Ready An active high open collector output signal synchronizing F9448 withF9445 during data transfers. A low level stalls the F9445 until the peripheral is ready. 53 Memory Ready Handshake between the memory controller and F9448 during data-channel cycles. Input to F9448 during data-channel read from memory; output from F9448 during data-channel write to memory. 01 00 49 50 51 Memory O-Llne O-Llne Input status lines from the F9445 indicating the type of bus cycle. W 37 Write An input signal indicating the direction of data transfer on the lB. ABORT 46 Abort A low input signal from the Memory Management and Protection Unit that prevents the F9448 from starting another cycle but allows completion of the current cycle. Mnemonic Clock ClK CPU Handshake Ready Memory RDYM CPU Cycle Type M 6-92 F9448 Table 1 F9448 Signal Descriptions (Cont'd.) Mnemonic Pin No. Name Device Code Jumpers CSCO,CSC2 Description 22·24 Chip Select Code Input signals tied to Vee, GND, SYN, or SYN to define a 6·bit device code, DS 10 through DS 15 for port 0 of F9448. 56·63, 1·8 Information Bus A 16·bit, three·state address and data bus for transmitting information between the F9445 and external devices. INTPIN 43 Interrupt Priority Input An input for determining which peripheral device will respond to an INTA instruction. INTPOUT 44 Interrupt Priority Output A priority·slgnal output from the F9448 to lower·priority devices for determining which peripheral device may interrupt. Information Bus iBo·iB15 Interrupt Priority Chain .), Master Reset MR 55 Master Reset An input signal that initializes the F9448 by clearing all F9448 user·accessible registers to 0 and clearing all busy, done, and interrupt·disable flags. LE 47 Latch Enable An output signal that may be used to load the data from the F9445 on the 18 into peripheral data bus latches. B'O'FE"NA 41 Buffer Enable An active low output during memory, I/O, or data channel cycles to enable IB transceivers or latches if data is to be transferred between the IB and a device controlled by the F9448. DIRN 42 Direction An output signal controlling the direction of any bus transceivers on the IB bus between the F9445 and the F9448 or of any data latches/transceivers between the IB bus and a peripheral data bus. 25·31 Outputs A 7-bit peripheral output control bus that is to be shared by all peripheral devices controlled by F9448. 54 Ready Peripheral Open·collector handshake input signal from peripherals to the F9448. Data Bufferl Latches Control Peripheral Control And Address Bus OUTo·OUTe Ready Peripheral RDYP 6-93 • F9448 Table 1 F9448 Signal Descriptions (Cont'd.) Mnemonic Pin No. Name Description ~1·PS4 21, 18, 14, 11 Port Select Outputs for selecting the devices being controlled by ports 1 through 4 of the F9448. STRSBZ1STRBBZ4 20, 17, 13, 10 Strobe Busy A low-to-high transition on the associated port's busy flag. STRBBZ input signal clears the STRBDN 1STRBDN 4 19,15,12,9 Strobe Done A low-to-high transition on the associated port's done flag. STRBi5fii input sets the DCHACK1DcRACK4 33-36 Data Channel Acknowledge Active low select inputs from the F9449 data channel controller. Vee 64 Power Supply Nominal + 5 V DC. GND 16, 48 Ground Ground for both supply and signals. IINJ 32 Injection Current A constant current obtainable by use of a dropping resistor from Vec (V 1NJ .. 13 V) supply. Use of a bypass capacitor to GND Is desirable. Peripheral Port Control Power 6-94 F9449 FAIRCHILD Multiple Data Channel Controller Microprocessor Product Connection Diagram Description The F9449 Multiple Data Channel Controller is a 4-port controller that is used with the Fairchild F9445 16-Bit Bipolar Microprocessor, and either an F9447 1/0 Bus Controller or an F9448 Programmable Multiport Interface, to control direct data transfer to and from memory by peripheral devices_ It contains four pairs of programcontrolled address and word count registers that are multiplexed to control four fully independent data channels (DCHs) through which data transfers can occur. Data channel transfers are similar to direct memory access (DMA) channel transfers, except that the F9445 architecture time-shares its information bus (IB). ii7 iis Vee 18s IB11 iB13 iB15 SYN ROYA STRBO STR • Provides Control of Four Independent Channels • Has Separate Word Count and Memory Address Registers for Each Channel • Supports Byte- or Word· mode Operation on Each Channel • Performs Internal Priority Arbitration • Supports Memory.to·Memory Transfers • Implemented in 13L® Technology. with Low·power Schottky TTL-compatible Input and Output • Available in a 64·Pin Package. • Operating Temperature Range of from - 55°C to +125°C OCHREQ Me ClK MAREN M IOEN 0, II GNO MR GNO OCHMO, DC HMO, OCHMO, OCHACK, OlEN ilcHAcK, 8M, OCHACK, BM, OCHPOUT BM, OCHPIN BM4 STRBA SB TC, OCHMO, TC, TC, OIRINT IB14 ii12 IINJ ® 13L is a registered trademark of Fairchild Camera & InstrumenlCorp. 6-95 F9449 F9449 Signal Functions F9449 CLOCK PERIPHERAL PORT CONTROL INFORMATION BUS BYTE STATUS } REGISTER CONTROL SIGNALS DATA BUFFER CONTROL DCH DIRECTION CONTROL 6·96 F9449 Fig. 1 F9449 Block Diagram Mii---~ • MSB OCHMO, OCHMO, OCHMO. MSB BITO OCHMO. I-----TC, OIRINT---...J \-----TC, \-----TC. ~ ~TC. 6·97 F9449 Register Operation F8449 1/0 Cycle The eight F9449 registers (MA1-4, WC1-4), shown In figure 1, provide four fully independent data channels, numbered 1 to 4, each of which Is capable of transferring up to 32K 8-blt bytes or 16-bit words, depending upon whether It Is strapped for byte-mode or word-mode operation_ Figure 2 illustrates the data formats of these registers_ The F9449 registers are under software control. They are loaded with starting address and word count information through F9445 programmed output Instructions, which are decoded by the F9447 I/O controller or F9448 multiport interface. The F9445 also generates the clock (ClK), synchronize (SYN), address strobe (STRBA), and data strobe (STRBD) bus timing signals. (Figure 5 illustrates the I/O cycle timing; refer to the "Timing Characteristics" section for a description of the cycle characteristics and specifications.) A word count (WC) register associated with each channel contains the number of bytes or words to be transferred by that channel. The WC registers, which are loaded with the twos complement of the number of bytes or words, are automatically incremented after each DCH cycle (i.e., after every byte or word transfer), regardless of operating mode. When a WC register increments from all ones to zero, a terminal count (TC) signal for that port Is set by the F9449. This is normally wired to the F9447 bus controller or F9448 multi port interface to generate an interrupt to the F9445. (Figures 3 and 4 Illustrate system configurations using the F9447 and F9448, respectively.) The TC signal can optionally be used to terminate any further requests from that peripheral channel. . Figure 2 All eight registers are cleared when master reset (MR) goes low to allow hardware implementation of auto load/bootstrap routines (i.e., to fill the memory beginning at address 0). Register Data Formats o IVii I The F9447 or F9448 selects the register to be loaded by generating the appropriate port select (PS) signal, ~ther with input/output enable (IOEN) and strobe (STR) Signals, as shown in table 1. The low-to-high transition of the STR signal during the write time loads the addressed port WC or MA register, selected by the memory address enable (MAR EN) signal, with data from the information bus. The F9445 can read the contents of any register by means of a programmed input instruction, which is decoded by the F9447 or F9448 in the same manner as the output instruction. 15 MSB Word Count (Twos Complement) lSB I F9449 DCH Cycle A peripheral device requests service by asserting Its request (REOn) line to the F9449, which then determines priority and generates a data channel request (DCHREO) Signal to the F9445. After completing its current program instruction, the F9445 responds to the DCHREO or data channel request performing a DCH cycle, which is a long bus cycle similar to an F9445 memory cycle, but with the information bus and the write rN) line not driven. Format for word- or byte-count register load (MAREN = 0). Word count range is from -2 15 to 1 (loaded with twos complement). Iii is an Internal direction bit: 0 Is from peripheral to memory; 1 Is from memory to peripheral. o I MSB 15 Memory Address Format for memory address register load (MAREN Address range is from 0 to 216 _1. lSB I The F9445 sets the bus control lines as follows: M high, 01 low, and 00 high (i.e., M, 01, 00 to 101). It then generates the ClK, SYN, STRBA and STRBD bus timing signals. The high-to-low transition of STRBA latches the priority resolution logic, and starts the internal DCH sequence of the F9449. The F9449 asserts the appropriate data channel acknowledge (DCHACK n) line to signal the requesting peripheral and the F9447 or F9448 that a DCH cycle for it has begun. This may cause the peripheral to remove the REO n signal. (Figure 6 illustrates the DCH cycle timing; refer to the "Timing = 1). A memory address (MA) register associated with each channel contains the address at which the next transfer is to occur; each MA register provides a 16-blt address space (0 to 65535). The MA registers are incremented after each transfer in word mode and after every second transfer In byte mode. 6-98 F9449 Fig. 3 F9449/F9447 Configuration ~~L_.,,_ IBs l8, USER OPTION iwI-- DCHREO ~ ROYA I -~ 100-- SWITCHES { STRDD ROYD ClK CO',EO INTtREO MR ~I I-- II-- I--r--!- ClK 1- IN~EQ APL - ~ CONSOLE C=) om; DS77 IDes STiiiA 1== 11- r 0, 0, J>. DECODER I ~ cs, ~ :::) DATA DISPLAY a '" D 0<1 ~ MEMORY ADDRESS - DOA DOB MRCAP DOC 10RST MSKD CONREQ START CONSW CLEAR CONSTP PULSE APLSW RDENS CONCD OCHEX REGISTER L.....- - r- 93471 RAM ADDRESS D,. DOUT U I t Ph LJ tI rrrr- r-r-f-- ~ r-- I--!.- CONEN DCHA f - - CONi]) 1- AP'CEN DCHI ~ DCHO ~ ~ c-- DCHiiEO ME W II-I--- M REO" ~ I--- 0, OCHACKn MAREN ROYA iM" PCHPIN DCHPOUT OlEN ClK iio -iBiS "::::5 -0( Ne USER OPTION m ~ ME w STRBP 6-99 r-:--~··l t ..... .... 1 J ~NC Sii ~NC PIRINT ,...,.,. DIA OOA DCHMDn ~ iiR L ~ -IDEX TC, SY' SlRBA I--- t :.. PSn 0, STRiO We A 10EN ~ f:!: I I DEY. CODe • • f@3= rr- 1- DATA CHANNEL CONTROLLER miBA cs~ ~A DE f+;-Vcc DiC r-iNTA ROYD ,.... lblPA LE Qn LE oeHMO I-I-- '345' On "? iiR CS, PROM .!tiJ ·t·....· C11 ClK ~ SELD .... Diir-Diir-- ROYA 1 ........ CONSOLE DATA ~ IOBSY v,,--- 1- GLOBAL 1- IB, IB10.15 IOEX sm ..... l' r8 I - DCHREO f-- w I--- M I--- 0, I--- 0, I--- SYN rr- ~r'f- ~ I- 0-0- STEP SKii ~ SiiiiD STRiA I-- z g~=~lE F9447 "0 BUS O,r-SYN r - - IB, W, NC...!.. RDVM O,r-FloW6 MICROPROCESSOR ~ DOENr-- IOENA : : W, W, N C _ ME L -I-- ~ I OiENW IOPRI CONTROLLER 180.18 15 ~ rc= ) .OPEN COLLECTOR OUTPUTS REQUIRE PULL·UP RESISTOR F9449 Fig. 4 F9449/F9448 Configuration iVCC---,----.---'~.. _'r--B,,--=:-LE----1rqv~ . L-... F9448 PMI --~~ USER OPTION ---.. eSC1 ENA - - csc, OIA I BUFENA D'RNf-------' OUTef--------<"'i OUTsl--------<~ Ne....!. RDYM OUT.. I--------<~ OUTaf--------<"'i OUT2f--------<"'i OUT,f--------<"'i IBo",:IB15 , DCHAEa~ wr-Me---- 0, FM46 0, MICROPROCESSOR SYN r--- OUTol--------<~ f--- RDYPf+- r--- i'i'iiiif--ROYA STRBD RDVD CLK CO'ii'AEQ iNTREQ MR I+-- PS.. r=l r-f.-f.-- r--- ' - - - - - - - - - - , --:+ STABDN.. ---------- ~iiA - . . INTPIN - 1 0,0, DECODER I -= INTPDUT -- ~A ... ~ DATA 'OEN CHANNEL ~ - L--- D DCHACK n iiin (1448) (94<1) i-----1f----t--..J CONTROLLER MARENi--t--+---' DCHREQ _iiE ~w STABA a!--- 1 - REGISTER - t-- .... RAM ADDRESS D,. DOUT U I : ~ "'CJ tl I--:- STRBA f+!- ROYA 98411 - " \ It I---- M 1----0, I---- 0, I---- SVN WE t 1 DCHACKn~ REOn Pini-----' iCnl-------_ ~:~~:~~s DCHMOni--------iM"nl----------,- D::~:Sir~:r PlAINT L iiio-ii,s f+-- Ne ) USER OPTION i'fRf+-- _r-1II::::= ~ ..... 1 L-<>( ·OPEN COLLECTOR OUTPUTS REQUIRE PULL·UP RESISTOR 6·100 D iiS,I------r--1 ..... llS,cs, - MEMORY ADDRESS ~ : i5CHACi<1 _ - - tor..~ -,1 ----'''\ _/A ~= DCHACK, - - vcc- II~~ cs c "0 DEVICE uxx I1= -----::§I-:=-------I'I ~~ ~ l~~ =::= _ ~A D~~CE STRBBZJ . . . _ STRBDN, - r = i~ ~ a DCHA: - - eLK i giL..!:..- ~ --=-- T ~ f--------I~_ ' - STRB~- ---;-- STRRD RDVO ~ 110 DEVICE WX F9449 F9449 1/0 Control Table 1 Signal State Operation Performed 10EN W MAR EN PS1 PS2 PS3 PS4 STR 0 X X X X X X X X X X 1 1 1 1 1 No operation No operation 1 1 0 0 0 1 Loads IB data into selected word count register Loads IB data into selected memory address register 1 1 0 1 ·· U U 1 1 ·· ·· X X Loads selected word count register data onto IB Loads selected memory address register data onto IB ·· ·· ·· ·· · · ·One active-low input, selected by programmed 1/0 instruction device code. Note Multiple port selects result in unpredictable results. o Low 1 X U High Don't care Low·to·high transition Fig. 5 • Programmed 1/0 Timing so 51 S2 S3 S3 53 S3 53 S4 S5 S1 so elK elK (56) SYN (59) SYN _+----J STRBD (8) M(55) 01 (53) ~__________________ i. OO(~)~ +-__-+__________________________.J ~ _________________ M, w01. 00 10EN (11) ---t.-------------------,y..----+p--------------------------, ,..-_______________ 10EN A ---1------------------' '----------------- Ps '+-_ _ _~ --jTEN(IBO..) _ 28.31~3~~~ ::.:~ __~'::_========TM:O:O~(I:B:O)========:-C·========~~~~~~~=====j=>------------____ iii --I TSTR(IB) W(5) MAREN (10) MAREN PSH (12-15) (1.4, IB DATA OUT OF F9449 Is READ FOR WRITE ------------------------~~~~~;: 18 WRITE -..I ::::;I~B~D~AT~A~IN~T~0~F~94~4~9=====~)~--------------~TSTR(EN) TEN(STR)--j I II STR (9) ---------------------------....:-..:....""'\\ f STR r-T1B (SlR) ~1.~::::::=7T~(S~TR;)::::::~.~1 6-101 F9449 four F9449 controllers by interconnecting the data channel priority out (DCHPOUT) of a higher priority controller to data channel priority in (DCHPIN) of the next, thereby permitting the system to serve a total of 16 data channel peripherals. Characteristics" section for a description of the cycle characteristics and specifications.) During the address phase of a DCH cycle, the F9449 determines which peripheral is to be served, places the contents of the appropriate MA register onto the information bus and drives the W line to the memory controller so that the memory performs either a read or a write cycle. If internal direction (DIRINT) is high, read/write selection can be programmed from the F9445 as the most significant bit of the WC register contents load. When this bit is at a logic 0 it causes a read of memory. If the DIRINT pin is low, the read/write selection is controlled by the peripheral through a data channel mode (DCHMO n) signal. A high DCHMO n signal indicates a memory read (DCH out operation). If required, the data in enable (DIEN) and second byte (8B) lines are also asserted at this time. Priority resolution occurs during every cycle, at the highto-low transition of the 8YN signal. In a multiple-F9449 system, all pending REOn inputs are latched at that time, and the DCHPINIDCHPOUT signals ripple from device to device. Priorities are reestablished during every cycle, including "short" F9445 cycles. Add itional states are generated by the F9449 address ready (RDYA) signal to allow priority ripple when the F9445 responds to a DCH. request from a "wait" cycle. Signal Descriptions The F9449 RDYA signal causes the microprocessor to generate three additional F9445 address strobe (81 G) states, allowing the address sufficient time to propagate from the F9449 to the memory controller. The F9449 input and output signals are described in table 2. Timing Characteristics The F9449 does not actually perform the data transfer between memory and peripheral. Instead, the end of the 8TRBA signal causes the F9449 to stop driving the address onto the information bus and allows the F9447 or F9448 to provide data control during the data phase of the DCH cycle. It enables a peripheral three·state input buffer, or strobes data out from the IB into the peripheral. The data phase of the DCH cycle can be :extended as required by additional data (83) states 'generated from the F9445 in response to the F9447 or F9448 data ready (RDYD) output being low. The timing characteristics of the F9449 are illustrated in figure 5 (Programmed I/O Timing) and figure 6 (Data Channel Cycle Timing). The abbreviated symbol convention used for timing parameters in this data sheet is TAb(C)d, where: • Timing symbols all begin with the letter "T". • The mnemonic in the position represented by "A" indicates the signal node beginning the interval. • The mnemonic in the position represented by "b" defines the direction of signal transition at the beginning node, if such definition is necessary; the new state of the signal may be low (I), high (h), 3-state (z), don't care (x), or valid (v). • The mnemonic in the position represented by "C", which always appears in parentheses, indicates the signal node ending the interval. • The mnemonic in the position represented by "d" is the same as "b", but refers to the state of the signal at the node indicated by the mnemonic in position "C". Because it must communicate with the peripheral during F9445 programmed I/O cycles, the F9447 or F9448 normally accommodates the data timing peculiarities of the peripheral. The end of·the data strobe (8TRBD) causes the WC and MA registers to increment, a TC signal to be asserted (if the WC register has reached zero), and terminates the W, DCHACK n, RDYA, and 8B signals. Priority Arbitration The F9449 arbitrates DCH requests from multiple peripherals on a fixed·priority basis, with channel 1 having the highest priority and channel 4 the lowest. The priority arbitration scheme allows cascading of up to 6-102 F9449 Figure 6 Data Channel Cycle Timing so S1G S1G 51G 51G S2 S3 S3 S3 S3 S3 S4 so 55 51G ClK elK (56) SYN (5.) SYN ----': STRiiA (41) RDYAm ~I._ _ _ _ _ _ _...J M(~)----~r-----------------------------------------------------------------'r-+-------DATA CHANNEL CYCLE = 101 ii, 01, 00 01 (54) Oo(53)--~''-----------------------------------J''--+----- -.I I ' - TMOO(ME) :-:-_...J-r!=- . TMOO(ME)--I ME (57) ~" _ _: - : -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TSTRBD(W) -+1 W(5)==:) r)I.- TSTRBD(W) ii (1-4, 28·31, 33·36, 60-63) W --I 7 WRITE, I . -______________________ STRBD (8) ME ~_~___"READ --------{===~~~~~==>_------------------------ iii OlEN OlEN (20) TSTRBO(SB) 88(25) I'-_ _ _ _ _ _ _ _ _ ~~~~~~~~~~ --I _ _ _ _ _ _ _ _WRITE _ ~~ TSTRBD(TC) _ _'READ --I 7 TC1.4 (39, 38, 27, 26) _ _ _ _ _:--:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..£:.._-..1 _____ --1_ DCHACK1.4 (6, 46, 45, 44) ~T5TRBA(DCHACK) \_ DCHACK 1.4 -+II'- TDCHPIN(DCHPOUT) DCHPOUT (43) -------------------""* DCHPOUT ---------------""'"'1* DCHPIN ----------------~I.::::::.~I~~TD~C;H;p;INm(D~C;H;POOU~T)n_------------------ DCHPIN (42) ------------------------------.l~ ~~--T-DC-H-P-IN-(S-T-RB-A-)--------------------------------------- \. .____-:-__________________________________...J-r- REQ H (52, 51, 50, 49) DCHREQ (58) I'-TDCHMO(W),-j DCHM01-4(18,19,47,40) TREO(DCHREO) TREO(DCHREO) '3:_____-:-___________________________________ t--- TDIRINT(W)---1 DIRINT(37) \ ....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ 6-103 REO,., F9449 Table 2 F9449 Signal Descriptions Mnemonic Pin No. Name Description Clock elK 56 Clock An input signal from the F9445. The rising edge of the single· phase system clock causes action in the F9449. This line can also be single·stepped for debugging. SYN 59 Synchronize An active-high input signal from the CPU that maintains system timing. The start of SYN indicates the start of a CPU cycle with valid M, 0 1, 0 0 code. S'fRBA 41 Address Strobe An active·low input signal from the F9445. In a DCH cycle, the low-to-high transition is used by the memory controller to strobe the memory address from the IB into the selected MA register. (This can be delayed indefinitely by RDYA.) RDYA 7 Address Ready An active-high open-collector output signal to the F9445. A low level prolongs the STRBA signal to allow time for the F9449 to perform priority resolution and propagate the memory address to the memory controller over the lB. 8 Data Strobe An active-low input signal from the F9445. The low-to-high transition during a DCH cycle causes the selected WC and MA registers to increment and the ViI, DCHACKn, RDYA and SB signals to terminate. 57 Memory Enable An active-low output signal to the memory controller. When low, it informs the memory controller that either the F9445 M is low or a DCH cycle is in progress. M 55 Memory An active-low input signal from the F9445 that serves as a status indicator. When it is low, the F9445 is performing a memory cycle. 01 00 54 53 Memory or I/O Function Active-high "0" line input signals from the F9445, used with the M input to indicate the type of cycle the F9445 is performing. During a DCH cycle, M, 0 1 , 0 0 are set at 101. W 5 Write An active-low input/output signal to and from the components in the system, normally driven by the F9445 to control the read and write·operations. Placed in a high-impedance state by the F9445, during a DCH cycle, when it is driven by the F9449, it is low if the system is writing to memory and high if the system is reading from memory. CPU Handshake Memory ME CPU Cycle Type 6-104 F9449 Table 2 F9449 Signal Descriptions (Cont.) Mnemonic Pin No. Name Description Information Bus Signals iBa·iB15 1-4 28·31 33·36 60·63 Information Bus A set of 16 input/output signals to and from the system. This active·low, bidirectional bus is used to load and examine the contents of the selected WC and MA registers. These signals are driven by the selected MA register during the STRBA state of an F9449 DCH cycle.:...The most significant bit is iBa; the least significant bit is I B15 . DCHPIN 42 Data Channel Priority Input An active·high input signal from a higher·priority F9449 that is used to extend priority resolution logic throughout a multiple· F9449 system. When this signal is iow, it prevents the F9449 from being in a DCH cycle. The highest priority F9449 should have DCHPIN connected high. DCHPOUT 43 Data Channel Priority Output An active·high output signal to a lower·priority F9449 that is used to extend priority resolution logic throughout a multiple· F9449 system. When the signal is high; none of the four channels are requesting a DCH cycle and DCHPIN is high. DCHREO 58 Data Channel Request An active·low open·collector output used by the F9449 to request a DCH from the F9445. Multiple simultaneous requests will be sorted by priority resolution logic during a DCH cycle and will result in additional consecutive DCH cycles. A low level requests a data channel cycle. 20 Data in Enable An active·low output signal that can be used to enable an optional bus transceiver placed between the F9449 and the lB. When low, the F9449 is putting out an address during a DCH cycle or data during an I/O read operation. 17 Master Reset An input signal that is active·low from a power·up, front·panel, or programmed initialization signal. It is used to load the WC and MA registers with zeros, set the internal direction control bit to zero, set the four TC signal lines high and clear the four DCHACK lines. 52 51 50 49 Port Request A set of four active·low input signals from the corresponding requesting peripherals. A low signal on a ~ line indicates that Its associated peripheral wishes a DCH n cycle. Priority resolution logic arbitrates multiple requests and generates a single acknowledge, RE01 having the highest priority and RE04 the lowest. Data Channel Data Buffer Control Reset. Peripheral Port Control 6·105 F9449 Table 2 F9449 Signal Descriptions (Cont.) Mnemonic Pin No. Name Description DCHACK1• DCHACK4 6 46 45 44 Data Channel Acknowledge A set of four active·low output signals to the requesting peripherals and to the F9447 or F9448. When low, it informs the appropriate peripheral that its requested DCH cycle is in progress. The DCHACK signal is used by the peripheral to clear the REQ n line. It is also used by the F9447 or F9448 and by the peripheral to enable data buffers to and from the lB. TC1-TC4 39 38 27 26 Terminal Count A set of four active·high output signals to the associated peripherals, indicating completion of a DCH block. When a WC register is incremented to zero during the last phase of a DCH cycle, the corresponding TC line goes high. When the WC register is loaded with any value from the IB during an I/O write operation to the F9449, the corresponding TC line is cleared to low. Ail four TC signals are set high by a low level on MR. PS4 12 13 14 15 Port Select A set of four active·low input signals from a programmed I/O device. The IB bits are decoded by an F9448, which outputs a port select signal to the F9449. When low, the associated port is selected during an I/O read or write operation. No more than one PS line should be low at a time. BM 1-BM 4 21 22 23 24 Byte Mode A set of four active·low input lines that are used to establish operating modes. When strapped low, the corresponding channel is set for 8-bit byte·mode operation; when strapped high, the associated channel is set for i6-bit word·mode operation. DCHM0 1DCHM04 18 19 47 40 Data Channel Mode Out A set of input signals from the requesting peripherals. When DIRINT is low, a DCHMO n low indicates that the corresponding peripheral is writing to memory during a DCH cycle (IN). When the DCHMO n signal is high, it indicates that the peripheral is reading from memory (OUT). 25 Second Byte An active· low ope~tor output signal to the memory controiler. During STRBD timing, this signal is high during the first byte of a byte·mode DCH cycle and low during the second byte of a byte·mode cycle and during every word in a word·mode DCH cycle. It can be used to strobe either the left or right half of the memory array during a STRBD operation. 11 Input/Output Enable An active·high input signal from the F9447 or F9448. It is used to enable the F9449 when the F9445 wishes to read from or write to a WC or MA register during an I/O cycle. When the signal is high, a programmed I/O operation is in progress. BYTE Status SB Register Control Signals 10EN 6-106 F9449 Table 2 F9449 Signal Descriptions (Cont.) Mnemonic Pin No. Name Description MAR EN 10 Memory Address Register Enable An active-high input signal from the F9447 or F9448. It is used to select the source/destination register for an F9445 programmed I/O operation. A high signal selects an MA register; a low signal selects a WC register. STR 9 Strobe An input signal from the F9447 or F9448. The low-to-high transition causes the F9449 to load the IB data into the selected WC or MA register during an I/O write operation. 37 Internal Direction Input line that is used to establish the control source of the W line. When DIRINT is high during a DCH cycle, the W line is controlled internally by lBo, the most significant bit of t.b..e data word in the WC register. When DIRINT is low, the W line is controlled externally by the DCHMOn input from the corresponding requesting peripheral. DCH Direction Control DIRINT It may be driven low by selected DCHACKn outputs if some channels need internal control and others external control. Power Vcc 64 Power Supply Supply voltage ( + 5 Vdc). IINJ 32 Injection Current A constant 250 mA current supply; may be derived by use of an external resistor to Vcc. (Nominal V1NJ 1.2 V.) GND 16,48 Ground Common power and signal return. = 6-107 F9449 Table 3 DC Characteristics Symbol Characteristic VINJ Injector Voltage. VIH Input High Voltage. VIL Input Low Voltage. Veo Input Clamp Diode Voltage. VOH Output High Voltage. VOL Output Low Voltage. hH Input High Current All Inputs. IlL Input Low Current. 10ZH Output Off (High-Impedance) State High Current 180-1815, W. 10ZL Output Off (High-Impedance) State Low Current 180-1815, W. 10SH Output Short Circuit Current. ILOH OHH Output Leakage Current (Open Collector) RDYA, S8, DCHREQ. Icc Supply Current. Min Typ Max 1.3 2.4 IINJ V Guaranteed Input High Voltage 0.8 V Guaranteed Input Low Voltage -1.5 V = Min, liN = -18 rnA, IINJ = Min Vee = Min, 10H = -400 p.A, IINJ = Min Vee = Min, 10L = 8.0 mA, IINJ = Min Vee = Max, VIN = 5.5 V, IINJ = 300 mA Vee = Max, VIN = 0.4 V, IINJ = Min Vee = Max, VOUT = 2.4 V, IINJ = Min Vee = Max, VOUT = 0.4 V IINJ = Min Vee = Max, VOUT = 0.0 V, IINJ = Min Vee = Min, VOH = 5.25 V, IINJ = Min Vee = Max, IINJ = Min 3.2 0.2 -0.21 -210 -15 = Max V 2.0 -0.9 Test Conditions Unit V 0.5 V 1.0 mA -0.4 mA 100 p.A -500 p.A -100 mA 1.0 125 mA mA Vee *Not more than one output to be 'shorted at a time. Absolute Maximum Ratings Recommended Operating Ranges These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Storage Temperature - 65°C, + 150. o C Ambient Temperature Under 8ias - 55°C, + 125°C - 0.5 V, + 6.0 V Vee Pin Potential to Ground Pin Input Voltage (dc) - 0.5 V, + 5.5 V - 20 mA, + 5 mA Input Current (dc) Output Voltage (Output HIGH) - 0.5 V, + 5.5 V + 20 mA Output Current (dc) (Output LOW) Injector Current (hNJ) + 500 mA Injector Voltage (VINJ) - 0.5 V, + 2.0 V Part Number Supply Voltage (Vee) F9449DC F9449DM Min Typ Max 4.75 V 4.5 V 5.0 V 5.0 V 5.25 V 5.5 V Injector Current (hNJ) Part Number F9449DC F9449DM Min Typ Max 200 mA 200 mA 250 mA 250 mA 300 mA 300 mA Ordering Information 6-108 Order Code Temperature Range F9449DC F9449DM O°C to + 75°C -55°Cto +125°C F9450 (MIL·STD 1750A) FAIRCHILD 16·Bit Bipolar Microprocessor A Schlumberger Company Advance Product Information Microprocessor Product • Single-Chip Microprocessor Fully Implements MIL-STD 17S0A (Notice 1) ISA_ • High Performance Over Military Temperature Range: 700K IPS DAIS Mix with Floating Point; 0_2 /As ADD, 1.85/As MULTIPLY • Real-Time Processing, Two Programmable Timers, 16 Levels of Vectored Interrupt • 32- and 48-Blt Floating Point Arithmetic on Chip • Bipolar VLSI13L, which should be the first key entered after power-up or after issuing the reset baud rate (5) command. Once the baud rates have been set, the F9470 enters the console mode (CM), as indicated by a • prompt. In the CM, the F9470 executes the eight console mode commands described in table 2. In response to the A, C, and E interrogative commands, the F9470 requests .a console operation from the F9445. The F9445 executes that operation under the control of the F9470 and returns a result to the F9470, if appropriate. Leading octal operands are required with C and E commands. (Execution of interrogative commands halts the F9445.) If the baud rate selected for port 1 is 4800, port 2 is disabled and the console mode is entered. If the baud rate of port 1 is 110, the port 2 baud rate is set to 110 and the console mode is entered. If the baud rate of port 1 is between 300 and 2400, the F9470 displays the prompt The J and R commands cause the F9445 to start program execution at a specified memory location. The J command transfers the F9470 from the CM to the I/O service mode (105M), while the R command leaves the F9470 in the CM. The J command causes the F9470 to transfer to the 105M without affecting F9445 status. PEP The T command single-steps the F9445 under control of the F9470, and displ~ys the CPU registers after each instruction. This command halts the F9445. + indicating that the baud rate code for port 2 must be entered by the user. These codes are shown in table 1. While executing the Rand T commands, the F9470 does not respond to 1/0 instructions from the F9445; all I/O read operations (including tests of device flags) return a zero. The baud rate of port 2 must be less than or equal to the baud rate of port 1, and certain combinations are not allowed (as indicated in the table). If the baud rate code entered for port 2 is incorrect, the F9470 again displays the PEP + prompt. Table 1 Baud Rate Selections and Restrictions for Serial 110 Baud Rate Codes for Port 2 Code o 1 2 3 4 5 Baud Rate Selected Disabled 110 300 1200 1800 2400 Baud Rate Options Port 1 Baud Rates 110 300 1200 1800 2400 4800 Valid Baud Rates for Port 2 None 110 300 1200 1800 2400 x x x x x x x x x x x x x x 110 baud automatically sets port 2 to 110 4800 baud automatically disables port 2 6-116 x F9470 Table 2 F9470 Console Mode Commands and Active Keys Command Function Description COMMANDS A Display Accumulators Displays in octal the following registers: PC, ACO, AC1, AC2, AC3, SP, and FP. n,vC Change Accumulator Deposits octal value v into register n, where n is n: 0 Corresponding Register: ACO AC1 2 3 4 5 AC2 AC3 SP FP x:v Deposit Memory Deposits octal value v into memory location x. xE Examine Memory Opens and displays the contents of memory location x, allowing octal numbers to be entered. Memory locations may be closed by: < RETURN> 1\ < ESC> which opens the next memory location (caret) which opens the previous memory location which returns to the monitor xJ Jump Loads F9445 PC with x, starts program execution, and transfers to the 10SM. When x = 0, transfers to the 10SM, and does not affect F9445 status. xR Run Same as Jump, except that F9470 remains in the CM. When x = 0, transfers to the 10SM, and does not affect F9445 status. S Set Baud Rate Resets F9470. The < RETURN> following S initialized the baud rate of port 1. nT Trace Traces n octal steps of F9445 program execution, displaying CPU registers after each instruction, in the form: Instruction Address Instruction ACO AC1 AC2 AC3 SP FP Before tracing a program, set the program counter to the appropriate location, using the xE command. Trace defaults to single-step, if n is omitted. ACTIVE KEYS BACKSPACE BREAK Deletes the previously-typed character. Transfers the F9470 from the 10SM to the CM. Does not affect F9445 program execution except that the F9445 I/O instructions are no longer interpreted by the F9470. 6-117 F9470 1/0 Service Mode Operation In the 1/0 service mode, the F9470 acts as a serial 1/0 controller, interfacing two serial I/O ports to the F9445 using device codes 10 through 13. Executing the J command changes the F9470 from the CM to the 10SM and causes the F9445 to start program execution. In the 10SM, the F9470 communication format is 1 start bit, 8 data bits, and 2 stop bits. Any parity bit should be set to 1. Table 3 lists the F9445 instruction that the F9470 recognizes when in the 10SM. These commands are a subset of the F9445 instructions described in the F9445 data sheet. When in the I/O service mode, the F9470 optionally responds to the device code 77 control instructions (defined in table 4). These device codes (10, 11, 12, 13, and 77) are octal values of the six least significant instruction bits (refer to table 5). Pressing the BREAK key at any time transfers the F9470 from the 10SM to the CM. The BREAK does not affect the F9445 program execution; therefore, execution continues until a console command is executed. The F9470 does not interpret F9445 I/O commands after the BREAK is pressed. Because the execution speeds of the F9445 and the F9470 differ, certain programming considerations must be made when using the F9470. 1. The b~sy flag of the F9470 input ports is not visible to the programmer, hence the SKPBN and SKPBZ instructions should not be used with device codes 10 or 12. 2. After clearing a device·done flag, the F9470 requires time to clear the associated interrupt request. This time, which depends on the baud rate, varies from 10·100 microseconds. When performing interruptdriven I/O, add a delay between the clear interrupt instruction and the next F9445 interrupt enable instruction. This delay ensures that the previously serviced request is cleared before the F9445 interrupt flag is re-enabled. Table 3 F9470 I/O Service Instructions Instruction Description DIAx ACC,DEV DOAx ACC,DEV NIOx DEV Data In from A Data Out from A No I/O; Used to Start or Clear a Device Skip if Busy = 1 Skip if Busy 0 Skip if Done = 1 Skip if Done 0 SKPBN DEV SKPBZ DEV SKPDN DEV SKPDZ DEV = = NOTES If x = S (start), set busy flag, clear done. If x = C (clear), clear busy flag, set done. ACC = Accumulator 0,1,2, or 3. DEV = Device Codes = 10,11,12,13. Note that Busy is not defined for input devices (TTl and PTR); hence, SKPBN and SKPBZ should not be used with these devices. Table 4 F9470 Interrupt Control Commands Instruction Description 10RST Clears all busy and done flags and sets all interrupt disatile flags (disabling interrupts). MSKO ACC Enables or disables device interrupts by clearing or setting the interrupt disable flag in the device. The interrupt disable flag of each device is associated with a specific data line, and is set if its mask bit is 1, cleared if O. INTA ACC Reads device code of highest priority device that is requesting an interrupt. The 6-bit code is loaded into ACC bits 10-15. All 16 bits are set to 0 if no device is interrupting. A simple method of adding the required delay is to insert a no I/O (NIO) instruction between the interrupt clear instruction (e.g., DIAC O,TTI) and the subsequent interrupt enable (INTEN) instruction. Interrupt Disable Bits for 110 Devices 3. The F9470 interrupt mask bits are set by applying power to the board or a1 o-J BUSGNT RDYD 35 oc 22 oc BUSGNT RDYD IB12 iifiii IB11 RDYACK 34 IB13 RDYA CP------~------~ 6-120 F9470 Table 6 Console Controller DC Characteristics Symbol Parameter Icc PD VIH Power Supply Current Min - 100 mA Outputs Open Power Dissipation - 550.0 mW Outputs Open Input High Voltage VIL Input Low Voltage ILOD Leakage Current (open drain ports) 10L Output Low Current 2.0 Unit 5.8 V -0.3 0.8 V -10.0 + 10.0 - 1.8 mA mA Test Conditions Pull-down, device off VOH = 13.2 V VOL = 0.4 V Ordering Information Absolute Maximum Ratings These are stress ratings only, and functional operation at these ratings, or under any conditions above those indicated in this document, is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. .c L M Temperature (ambient) under bias F9470DC O°C, + 70°C F9470DM -55°C, +125°C Storage temperature - 55°C, + 150°C Voltage on all open drain pins -1.0 V, + 13.2 V Voltage on all other pins, with respect to ground - 1.0 V, + 7.0 V Power dissipation Max 1.5W 6-121 Part Number Package Temperature Range" F9470DC F9470DL F9470DM Ceramic Ceramic Ceramic C L M = Commercial Temperature Range O·C to + 70·C = Limited Temperature Range -40·C to +85·C = Military Temperature Range -55·C to + t25·C • F9470 6-122 [!] \ 1 INTRODUCTION r-;;l2 \ORDERING AND ~ INFORMATION ! PACKAGE [!J \ F8 MICROCOMPUTER FAMILY 101 1 CONTROLLER FAMILY ~ F6800 MICROPROCESSOR FAMILY 1 F16000 MICROPROCESSOR FAMILY ! ~ \ ROM PRODUCTS ~9 \DEVELOPMENT SYSTEMS AND L!J I[!QJ SOFTWARE 1APPLICATIONS ![illIRESOURCE AND TRAINING CENTERSI ! ~ \ SALES OFFICES Section 7 F16000 Microprocessor FAIRCHILD A Schlumberger Company Family modes could only be used by some instructions. In addition, addressing has been limited to a small space (about 64K bytes), requiring complex, error-prone schemes for segmenting large programs. The F16000, however, provides 16 megabytes of uniform, unsegmented address space. Any data structure-word, double word, byte, or bit-may be addressed anywhere in the space by any instruction using anyone of the 11 addressing modes. This eliminates overhead, errors associated with memory-segment address calculation, and software compatibility problems for programs written for different address spaces. General The giant strides in semiconductor technology and the startling effect of large-scale integration on the price/performance enhancement of computing and storage elements is a familiar theme in technical, business, and financial literature. Despite these explosive advances, however, computer technology is still in its infancy. The rapidly accelerating pace of technology improvements is expected to continue through the 1980s, when the technology will reach the physical limits governing present materials and manufacturing techniques. New components and systems approaches will then continue the evolution, and the physics-based approach dealing with patterning, processing, and device modeling will be expanded to include information-based aspects of design and architecture. Virtual Memory Along with addressing main memory, management of total system memory hierarchy (fast disk, removable disk, magnetic tape, etc.) has been expensive, as well as a source of error. The F16000 provides facilities for system programs to treat combinations of various storage media as a single large memory space; large programs may be written without concern for size. The programmer need not worry about main or secondary memory management, paging, segmentation, swapping • segments in and out of main memory, or locating the necessary data; the F16000 memory management unit manages the peripheral memory. If the required data for the instruction being executed in the F16000 CPU is not available in the main storage, the CPU can abort the instruction and return to the state existing prior to the execution of that instruction. The CPU then requests the necessary data and is free to perform other tasks until the data is available for re-execution of the aborted instruction. All this is totally transparent to the programmer. Thus, the cost of extensive memory management routines and the potential associated errors are eliminated. As computing costs continue to rapidly decline, the number of applications is exploding. Computers have now permeated most facets of our lives-calculators, automobiles, appliances, telephones, banks, weapons, and even toys-and will continue to play an everincreasing role. The greatest impediment in this trend has been and continues to be the software; software development and maintenance remain manpowerintensive and represent a growing percentage of total system cost. The high software cost and increased software demand have created a major problem for both the information processing and automation industries. Sound engineering and management disciplines have been moderately successful in controlling software cost and quality. However, it has become apparent that new, more powerful hardware architectural features are necessary to more conSistently enhance cost and quality. Symmetry The Fairchild F16000 16-bit microprocessor family, the CPU of which has a 32-bit internal structure, is designed to significantly reduce software costs while improving software quality by incorporating powerful features into its architecture. These architectural features include: Exceptions to the rules, special cases, and arbitrary restrictions on the use of programming facilities contribute heavily to both cost and software errors. This is especially apparent in modern powerful machines, where perhaps a hundred instructions, together with ten addressing modes, several data types, and classes of registers, make it difficult to keep track of which memory or register instruction can or cannot use which addressing mode. The F16000 architecture is totally symmetric in terms of instructions, addressing, registers, and data-type handling. All instructions function in the same way for any of the registers in any addressing mode. Addressing Addressing and memory management have always been problems in software engineering. A great deal of designing and programming time, as well as computer time, is spent on address manipulation. In an attempt to reduce this problem, the number of addressing modes has proliferated; this, in turn, has led to increased programming difficulties, partly because certain addressing 7-3 F16000 Microprocessor Family High-Level Language Support System Protection High-level languages have played a major role in reducing software costs. For example, programmer productivity is about 1.5 to 4.5 instructions per man-day using low-level assembly language for a complex program. Productivity rises to 9 to 16 instructions per man-day for the same program using a high·level language. In addition, high-level languages are less cryptic and can be under· stood and modified more easily. In many cases, highlevel language structures provide less error-prone software, thereby achieving a higher system integrity level. The F16000 architectural features previously discussed, together with the support of arrays, queues, stacks, and records in addition to primitive data types (bits, bytes, etc.) are well suited to the efficient use of high-level language processing and compilation. Devising hardware techniques for detecting software errors and preventing propagation of these errors to sensitive system parts is relatively new in microprocessor design. In the F16000, for example, privileged instructions that can only be executed in the supervisory mode bar the lower-level applications programs from access to certain system resources. Future Expansion Software is a major part of an integrated approach to product and market development in a continuously changing environment involving product lines, services, and customer requirements. End-user software is therefore viewed as an experience base, a trade tool; the software expenditure is an investment to be conserved. This can best be accomplished by protecting the computer architecture from early obsolescence. Modularity Modularity is the design of small, self-contained independent programs, called modules, that may be used in many different combinations to perform specific tasks. It impacts all aspects of software engineering. The extent of system support of modularity affects the development and maintenance of program libraries consisting of many different general-purpose and special modules, which are used to build a complete software system. This is especially important for read-only memory (ROM) software. The F16000 provides for absolute modularity by imposing no restrictions on the individual module codes. Programs written independent of other programs may be loaded anywhere in the address space and mixed with other programs in any order. The F16000 module table is then set up by the linking loader to point to the code, data, and linkage information with the modules. At execution time, the F16000 registers point to appropriate code and data areas, thus eliminating the need for relocation, initialization, or other overhead functions. The open-ended architecture of the F16000 provides for the following expansion: -Increasing direct addressing to four billion bytes of real memory space -Extending the instruction set by adding slave processors -Expanding to 32-bit computers, since the base architecture, including registers and internal data paths, is 32 bits wide -Increasing virtual memory space to the billion or trillion byte range by adding a virtual memory translator and memory management chips Architecturally, slave processors, including virtual memory translators, are considered part of the central processor. The F16000 slave processor instruction sets are intentionally designed as extensions of the CPU instructions so that, as the expected higher levels of semiconductor integration are achieved, F16000 devices can contain various degrees of extended capability on one chip. Slave Processors Specialized functions, such as floating point processing, memory management, fast Fourier transfer, etc., can be incorporated into auxiliary processing elements, such as chips, to replace reams of software that would otherwise reside in the computer memory. In the F16000, the slave processor instructions provide an extension of the main CPU instruction set to augment the expansion of system capabilities In hardware. 7-4 F16000 Microprocessor Family Organization Figure 7-1 illustrates the organization of the F16000 family_ Descriptions Following is data that describes the members of the F16000 microprocessor family_ Figure 7-1 F16000 Microprocessor Family Organization F16032 HIGH PERFORMANCE CENTRAL PROCESSING UNIT F16081 FLOATING POINT UNIT F16082 MEMORY MANAGEMENT UNIT F16105 VERY INTELLIGENT PERIPHERAL CONTROLLER F16201 TIMING CONTROL UNIT F16202 INTERRUPT CONTROL UNIT F16203 CHANNEL CONTROLLER F16204 BUS ARBITER F16413 CRT CONTROLLER F16425 PACKET SWITCHING FRAME LEVEL CONTROLLER F16456 MULTIPLE PROTOCOL COMMUNICATIONS CONTROLLER F16802 LOCAL AREA NETWORK CONTROLLER F16488 GENERAL PURPOSE INTERFACE BUS CONTROLLER 7-5 • F16000 Microprocessor Family 7-6 F16032 High·Performance CPU FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description • • • • • The F16032 central processing unit (CPU) acts as the highest performance CPU for the F16000 microprocessor family. It is designed to provide optimal support to microprocessor users who need a large addressing space for large programs or data structures. The F16000 architecture allows very efficient compilation for large programs generated and maintained in high·level languages, while remaining easy to program at the assembler level for optimizations. Figure 1 is a block diagram of the F16032 CPU. • • • 32-8it Architecture and Implementation 16-Mb Uniform Addressing Space Two-Address Architecture High Degree of Symmetry in Instruction Set Addressing Modes Designed to Support High-Level Language Accesses to Variables High-Speed N-Channel MOS Technology Single + 5 V Power Supply 48-Pin Dual In-Line Package (DIP) Connection Diagram Signal Functions A" A" A21 A,. <>1 NO"'" CLOCK INPUT { __ <1>2 READY - HOLD REQUEST (For ---.Multiprocessing) ROY HOLD -- NON·MASKABLE INTERRUPT REQUEST ,~" ""~"" { A23 A20 INT NMI A1S ILO A" A18 A17 STO A17 A1S ST1 A16 AD1S ST2 AD1. ST3 AD13 PFS AD12 ODIN AD 15 A0 13 INT AD12 AD11 A0 10 NMI ADo9 MULTIPLEXED DATA/ADDRESS BUS ADos RESET/ABORT Voo A21 A19 AD14 kNET~~:~r A22 AD11 ADS A010 u/s RST/ABT ADo7 ADos ATispc ADos AOO4 ADS RSTIABT ADo3 AD7 DS/FLT CONTROL SIGNALS AD9 ADo2 DS/FLT ADo1 AC oo HBE ADS } iiDiN BUS CONTROL SIGNALS ST3 ST, ST, } BUS CYCLE STATUS ST. U/S" USER/SUPERVISOR STATUS LINE PROGRAM FLOW STATUS iUi INTERLOCKED INSTRUCTION STATUS HOLD ACKNOWLEDGE (For Multiprocessing) m Voo AT/SPC BBgND~NDB Hill t 7·7 ADS HBE ADS HLDA AD4 HOLD AD3 BBG AD2 ROY AD1 PH12 ADO GNDL PHll GNDB II F16032 Figure 1 F16032 Block Diagram CONTROLS AND STATUS ADD/DATA BDATA B BUS INTERFACE CONTROLJ....... INSTR UCTIONS t 16 rr MICROCODE ROM AND CONTROL LOGIC 8·BYTE QUEUE INSTRUCTION DECODER l- I-;;;::> III .... DISPLACEMENT AND ~ IMMEDIATE EXTRACTOR REGISTER SET 0 0 0 0 INTBASE SB "z a: w .... ~ .... III II REGISTER CONFIGURATION .... iii ~ WORKING REGISTERS FP SPO 0 PC RO i J SP1 0 \ R1 32·BIT ALU R2 R3 R4 RS R6 R7 I I MOD PSR L _____________ _ • Registers The eight dedicated and eight high-speed general storage registers of the F16032 are illustrated in figure 2. Instruction Set Table 1 is a summary of the instruction set for the F16032, and figure 3 shows the general instruction format. 7-8 / F16032 Figure 2 F16032 Dedicated and General Storage Registers GENERAL DEDICATED . • 32 PC STATIC BASE SB FRAME POINTER FP USER STACK PTR. SPl } INTERRUPT STACK PTR. INTERRUPT BASE Table 1 32 PROGRAM COUNTER PSR MOD STATUS MODULE .. RO~================~ Rl~================~ R2 ~=====::::::: SP spa INTBASE R3~================~ R4~================~ R5~================~ __________________ R6~ R7~ ~ __________________ ~ F16032 Instruction Summary Mnemonic Meaning Mnemonic Meaning ABS ACB ADD ADDC ADDP ADDQ ADDR ADJSP AND ASH Absolute Value Add Compare and Branch Add Add with Carry Add Packed Decimal Add Quick Integer Calculate Address Adjust Stack POinter And Arithmetic Shift ENTER EXIT EXT EXTS Enter New Context Exit Context Extract Field Extract Field Short FFS FLAG Find First Set Bit Flag Trap B BIC BICPSR BISPSR BPT BSR Conditional Branch Bit Clear Bit Clear in PSR Bit Set in PSR Breakpoint Trap Branch to Subroutine IBIT INDEX INS INSS Invert Bit Calculate Index Insert Field Insert Field Short JSR JUMP LMR LPR LSH Jump to Subroutine Jump Load MMU Register Load Processor Register Logical Shift CASE CBIT CHECK CMP CMPM CMPQ CMPS COM CVTP CXP CXPD Case Branch Clear Bit Check Index Compare Compare Multiple Compare Quick Integer Compare String Complement Convert to Bit Pointer Call External Procedure Call External Procedure with Descriptor MEl MOD MOV MOVM MOVQ MOVS MOVSU MOVUS MOVX MOVZ MUL Multiply Extended Integer Modulus of Periodic Function Move Move Multiple Move Quick Integer Move String Mover Supervisor to User Mover User to Supervisor Sign' Extend Zero Extend Multiply DFI DIV Divide Extended Integer Divide 7·9 • F16032 Table 1 F16032 Instruction Summary (Cont'd.) Mnemonic Meaning Mnemonic Meaning NEG NOP NOT Negate No Operation Not OR Or QUO Quotient RDVAL REM RESTORE RET RETI RETT ROT RXP Read Address Validate Remainder Restore General Registers Return from Subroutine Return from Interrupt Return from Trap Rotate Return from External Procedure SBIT SETCFG SKPS SMR SPR SUB SUBC SUBP SVC Set Bit Set Configuration Skip String Store MMU Register Store Processor Reg ister Subtract Subtract with Borrow Subtract Packed Decimal Supervisor Call TBIT Test Bit WAIT WRVAL Wait Write Address Validate XOR Exclusive OR S SAVE Set on Condition Save General Registers Figure 3 F16032 General Instruction Format OPTIONAL EXTENSIONS r~--------------~A'--------------~v~ BASIC INSTRUCTION ~A, ______ ______~ 1) DISP 2 IMPLIED OPERAND(S) DISP 1 2) IMM2 IMMI t INDEX BYTE 2 INDEX BYTE 1 GEN ADDR MODE 1 L-J fI 7-10 GEN ADDR MODE 2 I I OPCODE F16032 DC Characteristics The dc electrical characteristics of the F16032 CPU are presented in table 2. Table 2 DC Electrical Characteristics TA = 0 to 70·C, Voo =5V ±5%,GND =OV Symbol Parameter Min VIH VIL VCH Logical 1 Input Voltage Logical 0 Input Voltage Typ Max Unit 2.0 Voo -0.5 V -0.5 0.8 V Logical 1 Clock Voltage Voo -0.3 V <1>1, <1>2 Pins Only VCL VOH Logical 0 Output Voltage -0.5 Voo + 1.0 0.3 V <1>1,<1>2 Pins Only Logical 1 Output Voltage 2.4 V lOUT = - 400 p.A VOL Logical 0 Output Voltage 0.45 V 10L =2 mA IlLS ATISPC Input Current (low) 1.0 mA VIN =O.4V, ATISPC in Input Mode IlL Input Leakage Current -1.0 1.0 p.A VIN sV oo , All Inputs Except <1>1,<1>2, ATISPC 10L Output Leakage Current -1.0 1.0 p.A Os VIN S Voo 100 Active Supply Current 300 mA lOUT =0, TA =O·C -,-- Absolute Maximum Ratings The absolute maximum ratings for the CPU are presented in table 3. These are stress ratings only, and functional operation at these ratings or under any conditions above those indicated in this data sheet is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Table 3 Absolute Maximum Ratings Temperature Under Bias Storage Temperature All Input or Output Voltages with Respect to GND Power Dissipation O·C, + 70·C -65·C, +150·C -0.5V, +7.0V 1.5W 7·11 Test Conditions • F16032 7·12 F16081 Floating Point Unit FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The F16081 Floating Point Unit (FPU) is a slave processor intended to augment the instruction set of the F16000 microprocessor family. The FPU implements a version the IEEE standard P754 floating point specification. 0" Voo 0, STo 0, ST, SPCIAT 0, • High-Speed Operation • Single (32-Bit) and Double (64-Bit) Precision • Selectable Rounding Modes • Error Detection and Interrupt Generation • NMOS Technology • 24-Pin Dual-In-Line Package (DIP) • + 5 V Power Supply 0" 0" 0, 0, 0, Do elK GNDB GNDl • Signal Functions RESET ~~:TUS SIGNALS RST 1ST, - - STo AD, AD, AD, AD, AD, AD, MULTIPLEXED ADDRESS/DATA BUS AD, ADo SPC/AT Voo t +5V 7-13 GNDl GNDB OV OV SLAVE PROCESSOR CONTROL F16081 Instruction Summary The instructions lor the F16081 are summarized in table 1. Table 1 F16081 Instruction Summary Mnemonic Description ABSI ADDI CMPI DIVI FLOORli LFSR MOVI MOVFL MOVil MOVLF NEGI ROUNDfi SFSR SUBt TRUNCli Absolute Value Floating Point Add Floating POint Compare Floating Point Divide Floating Point Floor Function Load Floating Point Status Register Move Floating Point Move and Convert Move and Convert Move and Convert Negate Floating Point Round Function Store Floating Point Status Register Subtract Floating Point Truncate Function 7·14 F16082 Memory Management Unit FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The F16082 Memory Management Unit (MMU) provides support for virtual memory management and program debugging when used with the F16000 microprocessor family. It is designed to relieve the microprocessor unit of burdensome tasks associated with memory management and provide address translation during program execution. The MMU converts virtual addresses issued by the MPU to physical addresses. Support is included to assist the operating system in implementing memory management policies. Memory protection is implemented by slave instructions that check the validity of a memory reference. The F16082 also permits easy implementation of a virtual machine in a debugging and in-system emulation environment. The MMU slave processor extends the memory management capabilities of the F16000 microprocessor family. Slave processor concepts allow potential software compatibility with future systems because the slave hardware is transparent to the software. • • • • • • • • • • A" A'3 A,. A'3 A19 1NT A18 PAY A" ST. A16 ST, A015 ST, AD14 ST3 A013 PFS AD,2 ODIN A011 ADS AD10 Dynamic Address Translation Using Memory Page Tables On-Chip Cache for the 32 Most Recently Used Memory Page Table Entries Virtual Memory Memory Protection Program Breakpointing Program Flow Tracing Virtual Machine Support High·Speed NMOS Fabrication 48·Pin Dual·ln·Line Package (DIP) Single + 5 V Power Supply UfS ADg SPCfAT AD, ABTfRST AD, FLT AD, HLDAD AD, HLDAI AD, HOLll AD3 RSf /10, ROY AD, ~2 AD. ~1 GNDL 7-15 voo A" GNDB • F16082 Signal Functions CLOCKS READY HOLD CONTROLS I 1- RESET BUS CYCLE! STATUS USER/SUPERVISOR STATUS LINE ADDRESS STROBE SLAVE PROCESSOR CONTROL PROGRAM FLOW STATUS Instruction Summary The instruction commands for the F16082 are summarized in table 1. 11 !, ROY HOLD } HLDAI Table 1 HIGH ORDER ADORES BITS HLDAO RST ST, ST2 ST-j ST, F16082 Instruction Summary Mnemonic Description LMR ROVAL SMR WRVAL Load MMU Register Read Validate Store MMU Register Write Validate U/S MULTIPLEXED ADDRESS AND DATA BUS ADS SPC/AT Absolute Maximum Ratings PFS ABT/RST Voo t +5V GNDL GNDB ov DATA DIRECTION (BUS CONTROL) ABORT/RESET INT INTERRUPT FLT FLOAT (BUS CONTROL) PAV PHYSICAL ADDRESS VALID (Memory These are stress ratings only, and functional operation at these ratings or under any conditions above those indicated in this data sheet is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect device reliability, and exposure to stresses greater than those listed may cause permanent damage to the device. Temperature Under Bias Storage Temperature All Input or Output with Respect to GNO Power Dissipation Control) ov 7-16 O·C, +70·C - 65·C, + 150· -0.5 V, + 7.0 V 1.5 W F16105 Very Intelligent Peripheral Controller I=AIRCHILD A Schlumberger Company Microprocessor Product Advance Product Information Description The F16105 Very Intelligent Peripheral Controller (VIPC) is a general-purpose device to be used either with the F16000 microprocessor family or as a stand-alone system element. The controller is easy to program in both assembly language and high-level language. • • • • • • • • • • • • Upward Software Compatibility with the F16032 Microprocessor Internal10-MHz Clock Speed with Instruction Prefetch 4096·Byte ROM 192·Byte Two·Port RAM 64·Byte Scratchpad RAM 32 Pins Individually Programmable as I/O Asynchronous Communication Interface Port Cascadable 16·Bit Timer and Event Counters Eight Vectored Interrupts Input/Output Processor (lOP) or Slngle·Chip Configurations Remote or Local Bus Configurations External Memory Access of 56K Bytes • 7-17 F16105 7-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .j~a~~~'~ F16201 Timing Control Unit I=AIRCHILO A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The Fairchild F16201 Timing Control Unit (TCU) is a 24-pin Schottky component used with the Fairchild F16000 microprocessor family. It has four basic functions: Von PER CVlAIT 1. 2. 3. 4. Provides two nonoverlapping clock phases for unbuffered use within the F16000 microprocessor family and provides a synchronous TTL output. WArn Provides the basic system read, write, and databuffer-enable control signals_ WAITs WAIT2 'NAl14 1'50 CTTL Generates slow cycles compatible with the requirements of the older peripherals (those for which adding wait states is not sufficient). FCLK XCTl2 XCTL1IECLK Synchronizes the ready and reset inputs for the MPU. Full-V oo Swing Clock Outputs • Two Drive Capability on All Outputs Except Clock • TTL Generator for F16000 Systems •• On-Chip Bus Control Signals for F16000 Systems for Slow 8080 Peripherals • Support Four Wait Inputs (WAin to Force up to 15 Wait Signal Functions • States CRYSTAL INPUT OR EXT SOURCE 1- Wait Input (CWAIT) to Generate an • Continuous Unlimited Number of Wait States CWAIT Timing to Allow a Memory Cycle • Additional Hold and Subsequent Regeneration for System • • •• XCTL1IBCLK ~1 XCTL2 ~2 <:WAlT FCLK WAin CTn WAIT2 ROY WAIT4 Arbitration or Memory Refresh Schmitt Trigger Reset Input, Internally Synchronized to Generate a Reset Output for the F16000 System Fast·Clock TTL Output with Twice the System Clock Frequency Frequency Range of From 0.2 MHz to 10.0 MHz Single + 5 V Power Supply WAlf8 RESET CONTROL SIGNALS I j--- WR RSTT RSro DBE fSO ODIN PER RWEN ADS 7-19 Ri:l Voo GND I I TWO·PHASE CLOCK OUTPUT PERIPHERAL CLOCKS READY l BUS CONTROL PERIPHERAL 3-STATE CONTROL } POWER II F16201 wait count, CWAIT may also be taken to low, overriding the count and forcing a continuous wait to be entered. Functional Description TheF16201 has five major elements (see figure 1): the oscillator and divide·by-2 circuit, the two·phase generator, the reset synchronization circuit, the wait· state generator, and the timing state counter and control signal generator (TSCCSG). The wait-state generator counts the number of wait states to be generated. A start pulse (generated by the TSCCSG circuit) is used to initiate the counting. While the counter is operating or the CWAIT input is low, the wait·state generator holds its wait output to the TSCCSG circuit active. The wait-state generator turns its ready output (RDY) to low when a start pulse is received from the TSCCSG. The RDY output returns to high when the wait signal is released. The oscillator and divide·by-2 circuit is connected to either an external crystal operating at twice the desired clock frequency or an external source by way of the XCTL 1/ECLK pin. This circuit also generates the fast TTL clock (FCLK) with the crystal or ECLK frequency. A one· half·frequency output is created for the two·phase generator. The timing state counter and control signal generator circuit keeps track of the timing state (T-state) within the MPU, generating the control signals accordingly. The arrival of the address strobe (ADS) identifies the first T-state (T1) of a timing cycle. Input signals DDIN and PER are latched, and fast or slow, read or write cycles are generated. The TSCCSG circuit also extends a cycle, as directed by the wait line. The T-state output (TSO) signal identifies the beginning of the second and last T-states ofa timing cycle; it can be used to gate or clock external logic for synchronization. The two·phase generator provides two full·V oo swing, nonoverlapping clock signals. Additionally, it generates a TTL clock (CTTL) and an internal clock to synchronize the other circuits of the chip. The reset synchronization circuit synchronizes the reset· in input (RSTI) to generate reset·out (RSTO) with proper timing. The RSTI has a Schmitt trigger input. Wait timing allows two different modes of operation, providing flexibility in the generation of the wait inputs. When the CWAIT or WAIT inputs are active, wait states are inserted. However, if CWAIT is used to create the wait, the WAIT inputs can be applied and are implemented following CWAIT's release. During a fixed Figure 1 Recommended Operating Conditions The recommended operating ranges of the TCU are shown below. Supply Voltage Vee Temperature TA F16201 Block Diagram ADS CWAIT_ WAIT WAIT, WAIT 2 WAIT, WAIT, WAIT· STATE GENERATOR START TIMING STATE COUNTER AND CONTROL SIGNAL GENERATOR (TSCCSG) ROY _lililN _PER RD WR """-RWEN DSE 'fSO XCTLlI ECLK XCTL2 7-20 4.75 Min., 5.25 Max V 0·C,70·C F16202 Interrupt Control Unit FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The F16202 Interrupt Control Unit (ICU) provides the F16000 microprocessor family with hardware support for prioritized, vectored interrupts and for a real-time clock. • • • • • • • • • • • • • • IR 16 Interrupt Sources, Cascadable to 256 8 Hardware Interrupt Sources In 16-Blt Data Bus Mode Up to 16 Hardware Interrupt Sources In 8-Bit Data Bus Mode Optional 8-Bit InputlOutput (1/0) Port when the 8-Bit Bus Mode is Used Five Optional Clock Outputs In the 8-Bit Bus Mode Two 16-Bit, dc-to-10 MHz Counters that Can Be Combined into a Single 32-Bit Counter Thirty-two 8-Bit Internal Registers Accessible as Pairs in the 16-Bit Bus Mode Software Interrupts Automatic Handling of Return from Interrupts Programmable Polarities and Level/Edge Selection for Each of the Hardware Interrupts Automatic Rotating Priority Mode NMOS Technology 40-Pln Dual In-Line Package (DIP) Single + 5 V Power Supply Signal Functions INTERRUPT (to MPU) CLOCK INPUT 015P, 014P, C13Ps 012P, 011P3 010P2 009P, 008Po RESET BUS CYCLE STATUS LINE (Irom MPU) I BUS CONTROL \ SIGNALS 0, 0, Os 0, 03 O2 0, Do COUT EXTERNAL CLOCK IN/OUT GNO +5 V t 0V 7-21 voo INT IR, ST IR2 O'5P7 IR3 014P6 IR, 013P5 IRs 012P4 IR, 011P3 IR, 010P2 ClK 09Pl WR 08PO AD 07 COUT 06 H!iE 05 lIST 04 A, 03 A3 02 A2 01 A, DO Ao GNO cs • F16202 7-22 F16203 Channel Controller FAIRCHIL.D A Schlumberger Company Advance Product Information Microprocessor Product Description Connection Diagram The F16203 Channel Controller is intended for use with the F16000 microprocessor family. It is a four-channel controller that can operate on a processor local multiplexed bus (via local mode selection) to support low-cost configurations. It can also operate with separate user·defined input/output (I/O) buses (via remote mode selection) when high performance is required. VD D ADo R, AD, AD, AD, • • • Up to Four Independent Channels Interfaces with the F16032 Central Processing Unit Integrated Operation with the F16202 Interrupt Control Unit • Local/Remote (Single-/Multibus) Configurations • Versatile Channel Commands • Command Chaining • Support for Memory-to-Memory and Device-to-Device Transfers • 8- and 16-Bit Devices • NMOS Technology • 48-Pin Dual In-Line Package (DIP) • Single + 5 V Power Supply • Maximum Data Rate of 5M Bytes Per Second • Selectable Cycle Steal/Burst/Semiburst Transfers ADs AD. AD, DSTB AD, AD. AD10 ROY HlDAO HillAi HOLD A19 GND 7-23 elK F16203 Signal Functions Channel Command Summary The basic channel commands for the F16203 are DISABLE VERIFY SEARCH TRANSFER AND SEARCH Various command modifiers are appendable to the basic command and are summarized in table 1. CLOCK INPUT RESET INPUT READY INPUT } MOST SIGNIFICANT ADDRESS 81TS HOLD { CONTROL DMA REQUEST FROM DEVICES 3.0 I - Table 1 R3 112 A1 AO MULTIPLEXED ADDRESS AND DATA BUS Mnemonic Description AS AT BT Word Assembly Auto Transfer Burst Type Directllndirect Mode Destination Location Destination Type Destination Width Lock Priority Match/No Match Match/No Match Interrupt Mask Priority Type Request-While-Disabled Interrupt Mask Stop Enable Source Location Source Type Stop Function Interrupt Mask Source Width Transfer Complete Transfer Complete Interrupt Mask Search Type o MPU BUS CONTROL SIGNALS DATA STROBE TO DEVICES (Remote Mode Only) DMA ACKNOWLEDGE TO DEVICES 3·0 WAIT REQUEST TO F16201 (Remote Mode Only) INTERRUPT REQUEST CHIP SELECT HOLD REQUEST TO MPU I/O SELECT +5V OV 7-24 F16203 Command Modifiers DL DT OW LP MN MNI PT ROI SE SL ST STI SW TC TCI UW F16204 Bus Arbiter FAIRCHILD A Schlumberger Company Microprocessor Product Advance Product Information Description The F16204 Bus Arbiter manages heterogeneous multiprocessor systems that share a common bus. • • • • Multiprocessor Environments Up to 32 Masters Selection of Arbitration Algorithm Encoded Arbitration Scheme • 7·25 16204 7-26 F16413 CRT Controller FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Signal Functions The Fairchild F16413 CRT Controller (CRTC) operates within the F16000 microprocessor family for computer terminal, word processor, and monitor applications. The 64-pin, 5 V controller uses N-channel silicon gate technology. A number of features are programmable for easy adaptation to different display, synchronization, and screen formats. • • • • • • • • • • • • • cs CUR 1 LPICUR, SCAN LINE { COUNTER Programmable Display and Synchronization Formats Memory Addressing: Row/Column, DMA with Row Buffer, or Contiguous Linear Addressing Three Video Modes Three CRT Monitor Interfaces Programmable Window Location Programmable Status Field Location That Can Be Used to Provide a Vertical Split Screen Character Clock Rate to 10 MHz Maskable Interrupts: Line Zero, Vertical Blank, Smooth Scroll Complete, Programmable Row Interrupt, End of Scan Line Two Cursor Flags Double Width, Double Height Attributes Smooth Scrolling Forward or Reverse with Scroll Within Window or Its Inverse (Everything but the Window) Proportional Spacing Single + 5 V Power Supply MEMORY ADDRESS LINES RC, RC, RC, RCo A15 A14 A13 A12 A" AlO A, As A, As A, A4 A, A, A, Ao CCLK LLI LINE LOCK INPUT RD WR IffiT IRQ 0, Os 0, 0, 0, 0, 0, } DATA BUS (1/0) Do PA, PA, PA, PAc PS PBR } REGISTER ADDRESS PROP. SPACING PROCESSOR BUS REO. BLANK VSYNC POWER { The F16413 CRTC features programmable display format for up to 256 characters per row, 128 rows per frame, and 16 rasters per row. It has a programmable format for horizontal and vertical sync pulse delay (front porch), sync pulse width, and scan delay (back porch). Signal Descriptions Table 1 describes the CRTC signals. 7-27 GND VDD HYSNC • F16413 Table 1 CRTC Signal Descriptions Mnemonic Name Description Voo Power + 5 V power supply. GND Ground Commond ground. Ao/ RAo-A5/ RA5 Address Bus and Register Address Lower six bidirectional address bus and register address pins. Ae- A 15 Address Bus Higher 10 address bus output. 0 0 -0 7 Data Bus Bidirectional data bus. CS Chip Select Active low input to enable read/write of the internal registers during peripheral access. RD Read Strobe Input used to read data from the internal peripheral registers. WR Write Strobe Input used to write data to the internal peripheral registers. RST Reset An active low input to initialize the internal control and status registers. IRQ Interrupt Request An active low output that indicates one of the programmable interrupt conditions h.as occurred. CCLK Character Clock Clock input to provide timing for synchronization and screen formatting, 10 MHz maximum. RBl Read Row Buffer Output, read row buffer number 1. WB l Write Row Buffer Output, write row buffer number 1. RB2 Read Row Buffer Output, read row buffer number 2. WB 2 Write Row Buffer Output, write row buffer number 2. HOLD Hold Request Hold request output to the MPU. HOLDAI Hold Acknowledge Hold acknowledge input from the MPU when the CRTC works on the system memory; processor bus request when the CRTC works on dedicated video memory. HOLDAO Hold Acknowledge Hold Acknowledge output to a lower priority peripheral. CURl Cursor 1 Cursor 1 output. CUR2 Cursor 2 Cursor 2 output. 7-28 F16413 Mnemonic Name Description HWS Horizontal Window Start Output indicating the first horizontal position of a window. HWE Horizontal Window End Output indicating the last horizontal position of a window. VWS Vertical Window Start Output indicating the first row of a window. VWE Vertical Window End Output indicating the last row of a window. PS Proportional Space Input causing an update of the RAM address counter; can also be used as a double wide attribute input. DH Double Height Input for double height character attribute. BLANK Blank Active low output signal to turn off the monitor video during horizontal and vertical retrace. HSYNC Horizontal Sync Active low output signal to provide horizontal sync timing. VSYNC Vertical Sync Active low output signal to provide sync timing. RCo-RC 3 Raster Count Address Outputs giving the current raster count value. System Description Mode Control The F16413 CRTC can basically work in two system configurations, Le., on a local bus with dedicated video memory or on the system bus with access to the main memory. In the latter case, external row buffers must be provided, which are being loaded during DMA operation with the characters of the next following row to be displayed. The mode register determines the pin assignment for either system or remote bus operation. It is also used to select contiguous or row/column address, non-interlaced or interlaced video, attribute delay and external synchronization. It contains a reset control bit so the screen format may be reprogrammed anytime after a software reset. There are 33 registers implemented on the F16413 for mode control, screen formatting, and display control. Each of these registers is individually addressable using the lower six address pins when chip select is active. Information can be read out from or written into the register via the S-bit data bus. Windowing and ScrOlling The status field may be used to provide a vertically split screen with the video field. The window feature of the F16413 allows a defined window anywhere in the video field, or splits the screen horizontally into two independent data fields. Using the split screen feature requires programming the number of horizontally displayed characters in each data field into the assigned registers. Screen Format The horizontally displayable dimension of the screen, horizontal front porch, sync pulse width, and back porch are programmable in character clocks. The vertically displayable dimension of the screen is programmable in number of rows. The vertical front porch, sync pulse width, and back porch are programmable in scan lines. The number of scan lines per row is 1 to 16. The soft scroll control register is used to enable soft scroll, to select the area to be scrolled (either video field, window, or status field), and to select scroll rate and direction. 7-29 F16413 CPU/CRTC Memory Contention The CRTC 3-states the address bus during the horizontal and vertical blanking intervals. An interrupt is provided at the beginning of each blanking interval. Remote Bus Configuration During the blanking interval the CPU is free to access the dedicated video memory without disturbing the display during the active video. System Bus Configuration The F16413 is accessing the system memory during DMA cycles to load external row buffers. If the user provides one external row buffer, the DMA operation starts with the first character of the first scan.line of each row and the data is displayed immediately. In this case the RB and WB signals are both active during the first scan line of a row. If two external row buffers are used, then one of them is being loaded with the data of the following row while the other one is sending its data of the present row to the CRT. Loading of the row buffers starts at the beginning of the first scan line of the previous row. 7-30 F16425 Packet Switching Frame Level Controller (FLC) FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Status can be monitored by a series of maskable interrupt conditions or by reading eight directly addressable status registers. The F16425 Packet Switching Frame Level Controller (FLC) is a member of the F16000 microprocessor family that controls the transmission and reception of data (message frames) in a network conforming to the international CCITT HDLC protocol for applications in terminals, network access controllers, and related equipment at level 2 (frame level). It implements X.25 LAPB and portions of X.75, SDLC, and HDLC. It can be used with most MOS microprocessor families. Figure 1 is a block diagram of the F16425 controller. Figure 2 shows how the F16425 interfaces with DTE and DCE. Signal Descriptions Table 1 describes the signals for the F16425 controller. The F16425 controller can be used specificallY in data terminal equipment (DTE), data circuit terminating equipment (DCE), and network nodes (point-to-point, switched, or nonswitched systems). It uses all basic commands and responses-normal response mode (NRM) and asynchronous balanced mode (ABM) with five options. The CPU gives simple one-byte commands to initiate link setup, disconnect and information transfer. • • • • • • • • • • • • • • • • • • • • Signal Functions DDIN D7 D. D. 8-Blt and 16-Blt CPU Compatibility High-Density NMOS SI-Gate Chip 54-Pin DIP with 24 Registers at 8 Bits DC to 2_5 Mb/s One-Mbyte Direct Address Capability On-Board DMA to Transfer Messages to and from Memory Modem Interface Control Signals Programmable Address Field and Global Address Automatic Sequencing, Acknowledging, and Retransmission of Messages Automatic Frame Check Sequence Generation and Test TTL-Compatible Single + 5 V Power Supply Separate Address and Data Bus 8- or 16-Blt Bidirectional Data Bus Automatic Zero Insertion and Deletion for Transparency NRZ or NRZI Serial Data Programmable System Parameters -Primary Timer (11) -Retransmission Counter (N2) -Window Size from 1 to 127 Frames -Buffer length from 16 to 2K Bytes Programmable Basic or Extended Control Field I-Field Residual Last Character X_25 LAPB, X_75 (Excluding Multlllnk), SDLC, HDLC, ADCCP D, Do DATA DIRECTION l~"~ INTERRUPT }~"-'" }.oo.. ,~'"~ ADDRESS BUS CHIP CONTROL HLDAI POWER GND VDD 7-31 F16425 Figure 1 16425 Block Diagram READ/WRITE ENABLE REseT HIBVTE ENABLE DATA DIRECTION IN DMA ENABLE CHIP SELECT WRITE READ~~ GND ~ ____________-i MODEM SIGNALS TRANSMITTER CLOCK TRANSMITTER OUT INTERRUPT REQUEST 110 REGISTERS CENTRAL CONTROLLER DATA BUS ADDRESS BUS <:=========~ A8:A15 <:~~=======~A16.A19 RECEIVER CLOCK ::J~~============~ HOLDS AND . CONTROLLER DMA HOLD ACKNOWLEDGE --"'="-------------1._~_~...J Figure 2 X.25 Interface I SYSTEM & Pt~~r . SOFTWARE PROCEDURES I ----------- PACKET VIRTUAL CALL PROCEDURE LEVEL (SETUP, MAINTAIN, PROCEDURES FLOW CONTROL, CLEAR) I I I F16425 FRAME LEVEL PROCEDURES I I ----------I ~~~~r LINK ACCESS PROCEDURES PROCEDURES. I I I PHYSICAL LEVEL I SYNCHRONOUS CIRCUIT PHYSICAL LEVEL I I DTE(USER) DCE(NODE) 7-32 RS 232C F18425 I Table 2 F18425 Signal Descriptions Mnemonic Name Description Chip Select An active-low Input to enable READ/WRITE of the internal registers during a peripheral access. Data A 16-blt bidirectional data bus. Ao-A4 Address Address bits 0-4 are output during DMA access or Input during periphera access; high-Impedance output at all other times. As-A, 9 Address Address bits 5-19 are output during DMA access; high-Impedance output at all other times. Chip Select CS Data Bus Do-D'5 Register Power GND Ground Voo Power Supply +5 Volts Data Direction In The bidirectional DDIN signal low equals WRITE to FLC: high equals READ from FLC for peripheral access. A DDIN signal low equals WRITE to memory; high equals READ from memory for DMA acoess. Interrupt Request An active-low output Indicating that one of the programmed interrupt conditions has occurred. RCLK Receive Clock Direct clock Input; the RSI signal changes on the failing edge of the RCLK signal. RSI Receive Serial In A receive serial data input signal. TCLK Transmit Clock Direct clock Input, the signal TSO signal changes on the rising edge of the TCLK signal. TSO Transmit Serial Out A transmitted serial output data signal. Data Direction DDIN Interrupt IRQ TransmltterlRecelver 7-33 F16425 Table 1 F16425 Signal Descriptions (Cont'd.) Mnemonic Pin No. Name Description Modem Control CD Carrier Detect An Input signal CTS Clear to Send An input signal DSR Data Set Ready An input signal DTR Data Terminal Ready An output signal RTS Request to Send An output signal DMAE DMA Enable A high output when FLC has control of the system buses, and a low output at all other times; can be used to control external 3-state devices_ HBE High Byte Enable An active-low input/output signal that enables READ/WRITE to the highorder byte of the data bus; input during peripheral access and output during DMA access. This signal is not used in the a-bit mode. HLDAI Hold Acknowledge In An active-low input from the CPU or higher priority DMA granting control of the system buses. HLDAO Hold Acknowledge Out An active-low output to a lower priority DMA. HOLD Hold An active-low output requesting control of the system buses. 11>1 Input Clock One 0.4- to 10-MHz nonoverlapping two-phase clock input. RD Read Strobe An input/output read strobe if the RWEN input is tied to VDD; not used if RWEN is grounded. RST Reset An active-low input to initialize the internal control and status registers. RWEN Read/Write Enable A low input selects DDIN and DS signals for interfacing M6BOO-type microprocessors and a high input selects RD and WR signals for interfacing 16,000, a DB6-type microprocessors. WR/DS Write/Data Strobe A write strobe if the RWEN input is tied to VDD, and a data strobe for READ and WRITE, If the RWEN Input is grounded. WAIT Walt Used to extend the memory cycle during a 16-bit read operation. TEST Test A low invokes an internal test sequence. Chip Control 7-34 F16456 Multiple Protocol Communications Controller FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Signal Functions '"'-'"r The Fairchild F16456 Multiple Protocol Communications Controller (MPCC) is a programmable microprocessor peripheral device that interfaces a computer system to a serial data communication channel with minimum system overhead. It can be used in computer-tocomputer or computer-to-terminal communications, or in control of network trunk lines with the F16000 family and other microprocessors. • • • • • • • • • • • • • • • • • RECEIVE CLOCK RCLK RSI RSOF Do TCLK TSO CD .00'. { F16000 Family, 8080, 8086 Bus Compatible Satisfies Interface Requirements for Asynchronous Mode and for Synchronous Bit·Oriented Protocol (BOP) or Synchronous Byte·Control Protocol (BCP) Generates and Tests Error Detection Codes; Generates and Detects Special Characters Bidirectional Three·State Data Bus Interface (Selectable as 8·Bit or 16·Blt Bus) Full· or Half·Duplex Operation Modem Handshake Signals 5· to 8·Bit Character Lengths Primary or Secondary Station Operation Normal and Transparent Text Modes Directly Addressable Registers Serial Data from dc to 2.0M bps NRZ or NRZI (Complemented on Zero) Serial Data Self·Tested Loop·Back Mode Maintains Data Transparency Through Automatic Manipulation of the Data Stream TTL·Compatible Single + 5 V Power Supply 40·Pin Plastic or Ceramic Dual·ln·Line Package BUFFER { INTERRUPT RESET D. DSR DTR 05 0, RDA D. TBMT D. Ao A, A, vee v,, POWER { D. iifS iliQ REGISTER { ADDRESS 0, 0, 0, CTS RESET INTR. REO. MISC BYTE CPU INPUTS 0'0 0" 0" 013 0,. 0'5 1111 W1\ cs Connection Diagram TSO TCLK RTS RESET WR The F16456 MPCC is functionally divided into a serial data receiver, serial data transmitter, addressable registers, and data bus control logic. The receiver and transmitter operate at independent rates determined by their clocks. The eight registers contained in the MPCC are directly addressable when using an S-bit data bus; they are addressed in pairs when a 16-bit data bus is used. The MPCC is manufactured using high-speed XMOS technology. Figure 1 is a block diagram of the F16456. Signal Descriptions Table 1 lists the input/output signals for the F16456. f>mC irni iRa TBMT Do rn 0, en 0, D. 0, D. D. 0'0 05 0" D. 0" 0, 013 RDA 0,. Ao 0'5 A, DSR A, RSOF BYTE Ill) V,, 7-35 cs RSI RCLK VDD • F16456 Figure 1 F16456 Block Diagram ......--18 B I T S _ _188IT8_ MiIlr MODE CONTROL SYNCIADRESS REGISTER PAIR Do· 0" MCSA tmf 1m RCTS DB eft RESET RSDR Ao·A, BYTE \ViI III! CS DATA BUS CONTROL TCDR RECEIVER STATUS/DATA REGISTER PAIR TRANSMITTER CONTROL/DATA REGISTER PAIR RECEIVER LOGIC AND CONTROL TRANSMITTER LOGIC AND CONTROL 11ft TCLK TSO RCLK RSOF RSI RDA llRI TBMT Table 1 F16456 Signal Descriptions. Mnemonic Pin No. Name Description Vee 40 Power Supply Input + 5 V power supply Vss Misc. 20 Ground o V reference MISC 22 Miscellaneous The DEND bit of the receiver control register (RCR) determines whether the MISC pin is an input or an output. When used as an Input, a low level sets the end·of·message (EOM) bit in the transmitter control register. When used as an output, the· MISC pin is general·purpose In nature and is controlled by bit 14 of the RCA. Power 7-36 F16456 Table 1 F16456 Signal Descriptions (Cont'd.) CPU Inputs BYTE 18 Byte A high·level input that indicates an 8·bit data bus; a low level indicates a 16·bit bus. 0 0-015 6-13,28-35 Data Bus A bidirectional 16-bit data bus. An 8-bit data bus interface is obtained by connection Do through Dz to 0 8 through 0 15 , respectively, and connecting pin 18 (BYTE) to + 5 v. RD 19 Read Pulse A low-level input that transfers the contents of the addressed register to the data bus if CS is low. WR 5 Write Pulse A low-level input that transfers the data bus information to the addressed register is CS is low. RDA 14 Receiver Data Available A high-level output indicating that an assembled character is in the receiver data buffer; reset on the positive edge of RD when reading from the transmitter buffer. TBMT 25 Transmitter Buffer Empty A high-level output indicating that the device is ready to accept another data character from the CPU; reset on the positive edge of WR when written to the transmitter buffer. 4 Reset A low-level Input that disables the transmitter and receiver and initializes the internal control registers and timing. 24 Interrupt Request An output signal that goes low to indicate a change in the_ internal status of the device. The status bits linked to the IRQ output are receiver overrun, received end-of-message and async framing error, received parity error, and transmitte~ underrun. The IRQ signal is reset on the trailing edge of RD when the associated status register is read. 15 16 17 Register Address Input signals that select one of eight 8-bit addressable registers if the BYTE signal is high. If the BYTE signal is low, AO is not used; A1 and A2 select one of four 16-bit register pairs. Reset RESET Interrupt IRQ Register AO A1 A2 7-37 F16456 Table 1 F16456 Signal Descriptions (Cont'd.) .- Mnemonic Tran smit/Recelve Cloc k Pin No. Name Description RCl K 39 Receiver Clock Timing input signal for the receiver logic. RSI 38 Received Serial Input An input signal comprising the received serial data. RSO F 37 Received Sync or Flag An output signal that is high for one receiver clock period each time a flag or sync character is received. TCl K 2 Transmitter Clock An input signal that provides timing for the transmitter logic. TSO 1 Transmitted Serial Output An output signal comprising the transmitted serial data. 27 Carrier Detect A general·purpose input that can be tested by reading the transmitter status register. 26 Clear to Send An input signal used with the RTS signal to enable the transmitter; can be tested by reading the transmitter status register. 36 Data Set Ready A general·purpose input that can be tested by reading the transmitter status register. 23 Data Terminal Ready Modem CTS 3. RTS - Request to Send A general-purpose output that can be set low by programming the DTR bit of the receiver control register to a logic one. An output signal that can be set low by programming the RTS bit of the transmitter control register to a logic one. 7-38 F16488 GPIB Controller FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Signal Functions The Fairchild F16488 General·Purpose Interface Bus (GPIB) controller serves as a generaIIEEE·488 compatible listener/talker and controller within the 16000 microprocessor family for applications in the interconnection of intelligent programmable instruments on the general·purpose interface bus. It is compatible with most MOS microprocessor families. • • • • • • • • • • • • • • ATTENTION Handles All IEEE 488·1975/78 as Well as 1980 Supplement Functions Talker, Listener, and Controller Functions Compliance of All Bus Signals with IEEE 488 and IEC 625 Inputs, Threshold, Termination, and Output Specifications DMA Access Facilities (Compatible with F16203 and Most Other DMA Controllers) Single· Phase 10·MHz Maximum TTL Clock Pass Control Capabilities Stoppage of Transmission of Unwanted Data Possible Through NBAF Auxiliary Command On· Board Drivers Hold·Off on All Data and Hold·Off on Command End-of-Strlng Recognition by EOS Byte or EOI Pin Programmable Counter for T1 4O·Pln Package Single 5 V + 10% Power Supply One·MHz Data Transfer Rate DATA VALID DMA REQUEST DMAGRANT IIAII Ii1II'D DATA ACCEPTED . . . . Iil!lrn READY FOR DATA''''' SERVICE REQUEST m 1m' RESET INTERRUPT es CHIP SELECT l'l) REMOTE ENABLE INTERFACE CLEAR SUBSTRATE Note: Figure 1 is a block diagram of the F16488. 7·39 READ STROBE _ WRITE STROBE GROUP EXECUTIVE TRIGGER TTL CLOCK IN REN , WI! fi!C Ao TRIG CTTL A, VD. +5V A. Vss, o VOLTS VDD VSS2 o VOLTS This is not a pin assignment. F16488 Figure 1 F16488 Block Diagram DAVCllIIIII IEEE 488 DATA BUS (8) (8) IEEE Management a"H"'o::;nd::;O::;h::;Ok::;:O'-_ __ IEEE 488 STATE DIAGRAM AND CONTROL LOGIC TRIGOA DMAE CPU(81 1--'-~-_1Ilf CllI-----l 7-40 F16802 Local Area Network Controller FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description The Fairchild F16802 Local Area Network Controller (LANG) serves as an IEEE-802 token controller within the F16000 microprocessor family. It is intended for application in the interconnection of devices on the token-ring network, and is compatible with most MOS microprocessor families . • 8-bit and 16-bit CPU Compatibility • Handles IEEE-802 LLC and MAC (token-ring). • 7-41 F16802 7-42 I[!] I INTRODUCTION ~2 IORDERING AND PACKAGE ~ INFORMATION I[!] I Fa MICROCOMPUTER FAMILY 1C!JlcONTROLLER FAMILY \WIF68OO MICROPROCESSOR FAMILY \0IF16000 MICROPROCESSOR FAMILY ROM PRODUCTS ~9 I DEVELOPMENT SYSTEMS AND L!.J \[!Q] I[!!] I[1!J SOFTWARE I APPLICATIONS I RESOURCE AND TRAINING CENTERS I I SALES OFFICES Section 8 ROM Products FAIRCHILD A Schlumberger Company This section contains descriptions of the ROM products. These devices are functionally related to the F6800 microprocessor family and offer varying amounts of read only memory. All of the ROM products are custom chips and are mask-programmable. • 8-3 ROM Products 8·4 FAIRCHILD F3532/F68332 F3533 A Schlumberger Company 4096 X 8 ROM Microprocessor Product Logie Symbol Description The F3532/F68332 and F3533 are 4096 x 8-bit maskprogrammable Read Only Memories (ROM), fabricated with n-channel silicon gate technology. They are designed for use in bus-organized systems requiring non-volatile data storage. For ease of use, the F3532/F68332 and F3533 require only a single +5 V power supply, have TTLcompatible inputs and outputs, and, due to their static operation, need no clocking or refreshing. Ao A, A2 10 Aa 11 A_ 13 F3532/F3533 As 14 A. Electrically identical, the F3532/F68332 and F3533 represent both JEDEC standard pinouts, thus providing compatibility with other available 32K ROMs and EPROMs. To facilitate memory expansion, these devices offer two programmable Chip Select inputs whose active levels are user defined. as 16 23 A8 17 22 A. 19 A,o 18 The F3532-30/F3533-30 and F3532/F3533-35 are high speed devices, allowing interface with faster generations of NMOS microprocessors. • • • • • • • • • vcc = GND 'All 00-07 Address Inputs Chip Select Inputs Data Outputs Absolljte Maximum Ratings Voltage on Any Pin Relative· to GND Opersting Temperature Storage Temperature Power Dissipation 21 Pin 2. = Pin 12 = Pin 18 (F3532/F88332). Pin 21 Connection Diagrams 24-Pln DIP Pin Names CS1, CS2 20 (F3533); CS2 = Pin 21 (F3532/F68332), Pin 18 (F3533) Completely Static Operation a-Bit Bus Compatible Organization 3-State Outputs Two Programmable Chip Select Inputs Single +5 V ± 10% Supply Fully TTL Compatible 3 Speed Grades-tAcc = 300, 350, 450 ns Both JEDEC Standard Pinouts Pin Compatible with Other 32K ROMs and EPROMs AD-All 15 A7 -0.3 V, +7 V O·C, +70°C -65·C, +150·C lW A7 Vee A7 vee A. A8 As A8 A. As A. As A_ CS2 .... A_ Al1 Aa cs, ** Aa CS,· A2 A,o A2 A,o A, Al1 A, CS2'" Ao 07 Ao 07 00 O. 00 O. 0, Os 0, Os 02 O. 02 0_ GND Oa GND Oa (Top View) Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (Top View) **Programmable Chip Selects ·(see Custom ROM Programming Information) 8-5 • F3532/F68332 F3533 Block Diagram 00 0, O. 03 O. O. O. 0, An A,o A. A. A, Aa As A. A, CS, A. 32.768-BIT CELL MATRIX A, AD DC Requirements Over operating temperature range Symbol Characteristic Vee Power Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage DC Characteristics Max Unit 5.0 5.5 V -0.3 0.8 V 2.0 5.5 V Max Unit 0.4 V lOUT = 1.6 mA V lOUT = -200/lA 4.5 Note Over operating temperature and voltage range Characteristic Symbol Typ Min VOL Output LOW Voltage Min Typ 2.4 Note VOH Output HIGH Voltage lee Vee Power Supply Current 80 mA 1 liN Input Leakage Current 2.5 /lA 2 lOUT Output Leakage Current 10 /lA 3 Notes on following page. 8-6 F3532/F68332 F3533 AC Characteristics Over operating temperature and voltage range F35XX-30 IEEE SymbolS Symbol Characteristic Min Max 300 Min Max 350 F34XX-45 F68332 Min Max 450 Unit Note TAVAV tCYC TAVQV tACC Address to Output Access Time 300 350 450 ns 4 TSLQV tco Chip Select to Output Delay Time 120 150 150 ns 4 TSHQZ tOF Data Hold After Deselection 150 ns TAXQZ tOHA Data Hold After Address Time 4 4 CIN Input Capacitance COUT Output Capacitance Notes 1. All inputs 5.5 V, TA 2. VIN 3. 4. 5. 6. = 0 V to 5.5 V Cycle Time F35XX-35 10 10 120 10 10 150 10 ns ns 10 7.5 7.5 7.5 pF 5 12.5 12.5 12.5 pF 5 = O°C Device unselected: Your = 0 V to 5.5 V Measured with 1 TTL Load and 130 pF, transition times = .20 ns Capacitance measured with Boonton Meier Timing Parameter Abbreviations All timing abbreviations use upper case characters with no subscripts. The initial character is always T and is followed by four descriptors. These characters specify two signal points arranged in a "from-to" sequence that define a timing interval. The two descriptors for each signal point specify the signal name and the signal transitions. Thus the format is: t___t_----'JX Signal name from which interval is define_d_ _ _T ___ Transition direction for first signal - XI 8ignal name to which interval is defined Transition direction for second signal The signal definitions used in this data sheet are: A = Address 0= Data In Q = Data Out W = Write Enable E = Chip Enable The transition H = transition L = transition V = transition X = transition Z = transition definitions used in this. data sheet are: to HIGH to LOW to valid to invalid or don't care to OFF (high impedance) Timing Diagram ADDRESS ADDRESS X V,H PROGRAMMABLE CHIP SELECTS OUTPUT DATA VOH - - - - _ O P E N _ _ _ _ _-{ VOL • DON'T CARE INPUT CONDITION OR INDETERMINATE OUTPUT STATE 8-7 • F3532/F68332 F3533 Custom ROM Programming Information The customer's unique program code pattern may be submitted to Fairchild in several methods. The most convenient and readily verifiable is in the form of 2708, '2716 or 2732 EPROMs. Program code patterns may also be submitted on Fairchild Formulator MKIII floppy disks or on HP cassette tape in Formulator or MIKBUG* format. Fairchild Use Only SLNo. _______________________________ Bid Control No. _ _ _ _ _ _ _ _ _ _ _ _ __ Field Sales Engineer _ _ _ _ _ _ _ _ _ _ __ Date Sent Customer Company Name _ _ _ _ _ _ _ _ _ _- - Customer Contact Name _ _ _ _ _ _ _ _ _ _ _ _ __ Customer Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ Phone No. _____________________ Fairchild Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ __ Customer Input Media 02708 EPROM 02716 EPROM 02732 EPROM o Floppy Disk o HP Cassette o Formulator Format o MIKBUG Format Request for Return Media o Listing o EPROM (include blank EPROMs) Chip Select Information HIGH CSl 0 CS2 0 LOW 0 Don't Care o o 0 "'MIKBUG is a Motorola trademark. Formulator Format ~O~I~1~1--2~-3~1-4~--5~-6~__7~1~8~1-9~I-l-0~l_l_l~£~(~M-.6~I-M-.5~I-M-.4-I~M-.3~-M.-2.1-M'_l~I_M__ SOR Ll La A3 A2 Al Ao Tl To 001 SOR Start of record defined to be a colon (:) Ll Lo Length field defined to be the number of packed data bytes per record. Each record is (2· L) + 11 characters in length inclusive of start of record. Length 0 implies end of relocatable module. 000 011 D(n-l)lD(n-l)O Dnl DnO CKl CKo Type field. 001 000 ... D(n)l CKl CKo Address field. All characters other than SOR are ASCII hexadecimal (0-9, A-F). 8-8 D(n)O Data field. Checksum field defined to be negative modulo 256 summation of all bytes since start of record. A summation of all characters in a record, including the checksum, will result in zero. F3532/F68332 F3533 Ordering Information' Part No. Order Code F3532·30 F3532·35 F3532·45 F353230P, F353230S F353235P. F353235S F353245P, F353245S F3533·30 F3533·35 F3533·45 F353330P. F353330S F353335P, F353335S F353345P, F353345S F68332 F68332P, F68332S P = Plastic DIP S = Ceramic DIP *For extended temperature or military grade. call factory. • 8·9 F3532/F68332 F3533 8-10 F3564 64K ROM FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Logic Symbol The Fairchild F3564 8192 x 8·bit (64K) mask·program· mabie read·only memory (ROM) is designed for use in bus·organized systems requiring non·volatile memory storage. Because of its high speed, it readily interfaces with all generatins of NMOS microprocessors. Ao • • • • • 0, A, A, A, Fabricated with n·channel silicon·gate technology, the F3564 has industry·standard pinouts and is compatible with other available 24·pin 16K, 32K, and 64K ROMs and EPROMs. • • • • o. A, 10 O2 11 03 13 0, 14 As A, A1 Address Latch Feature Single 5·V Power Supply Automatic Power· Down Access Time (tAA) of 250 ns for F3564·25 and 350 ns for F3564·35 Low Power Dissipation (440 mW Maximum Active, 55 mW Maximum Standby) Fully TTL·Compatible Three·State Outputs Mask·Programmable Enable Function Pin·Compatible with Other Standard 24·Pin 16K, 32K, and 64K ROMs and EPROMs. 23 As 22 Ag 21 19 A" Am 18 A" Os 15 0, 16 17 GND: Pin 12 Vee: Pin 24 LOGIC SYMBOL 20 Connection Diagram The programmable enable (E) input of the F3564 latches the addresses and controls the active and standby modes of operation (see figure 1); no external latches are required. The active level of the E input and the memory contents are user·defined. Vee As Ag A" The F3564 requires only a Single + 5·V power supply, has TTL·compatible inputs and outputs, and, due to its static operation, requires no clocking or refreshing. E Signal Descriptions 01 A,. A" 0, The F3564 Signals are described in table 1. Os 0, 0, 8·11 • F3564 Figure 1 F3564 Block Diagram A'2 A" A,o A9 As A7 As As ADDRESS INPUT BUFFERS A. E 0:: A3 UJ Q 0 A2 65536·BIT CELL MATRIX (.1 UJ Q X A, Ao Table 1 Signal Descriptions Mnemonic Pin No. Name Description Ao·A 12 1·8, 18, 19, 21·23 Address Lines TTL·compatible input lines that identify the memory location to be read. E 20 Enable Programmable input signal that latches the address and controls operating mode. Active level is user·defined. °0·°7 9·11, 13·17 Data Lines TTL·compatible output lines that contain the data read from the addressed location. Vee 24 Supply + S·V power supply GND 12 Ground Supply and signal ground 8·12 F3565 64K ROM FAIRCHIL.D A Schlumberger Company Advance Product Information Microprocessor Product Description Logic Symbol The Fairchild F35658192 x 8-bit (64K) mask-programmable read-only memory (ROM) is designed for use in bus-organized systems requiring non-volatile memory storage. Because of its high speed, it readily interfaces with all generations of NMOS microprocessors. AD A, 00 0, A, A, A, Fabricated with n-channel silicon-gate technology, the F3565 has industry-standard pinouts and is compatible with other available 24-pin 16K, 32K, and 64K ROMs and EPROMs. 10 0, 11 0, 13 0, 1. Os 15 0, 16 0, 17 As A. A, • • • • Completely Static Operation Single 5-V Power Supply Automatic Power-Down Access Time (tAA) of 250 ns for F3565-25 and 350 ns for F3565-35 • Low Power Dissipation (440 mW Maximum Active, 55 mW Maximum Standby) • Fully TTL-Compatible • Three-State Output • Mask-Programmable Enable Function • Pin-Compatible with Other Standard 24-Pin 16K, 32K, and 64K ROMs and EPROMs 23 As 22 A, 21 A12 19 A,o 18 Al1 GND: Pin 12 Vee: Pin 24 20 LOGIC SYMBOL Connection Diagram 24-Pin Dip The programmable enable (E) input of the F3565 controls the output and the active/standby modes of operation (see figure 1). The active level of the E input and the memory contents are user-defined. The F3565 requires only a single + 5-V power supply, has TIL-compatible inputs and outputs, and, due to its static operation, requires no clocking or refreshing. Signal Descriptions The F3565 signals are described in table 1. 8-13 A, Vee As As As A, A. A12 A, E A, A,o A, Al1 Ao 0, 00 0, 0, Os 0, 0, GND 0, II F3565 Figure 1 F3565 Block Diagram 1J - OUTPUT BUFFERS - - Ao POWER· DOWN LOGIC Y DECODER 1·0F·32 BYTES I ADDRESS INPUT BUFFERS t1 t 2 ••• t256 1 2 (/J a::= Wo ca: - •• • 0", UIl) WN cu:. 65536·BIT CELL MATRIX ENABLE INPUT BUFFER f- E xC? .... 256 f Table 1 t t t t t t t11 I - - 1 I I I I I f Signal Descriptions Mnemonic Ao·A12 Pin No. 1·8, 18, 19 21·23 Name Address Lines Description TIL·compatible input lines that identify the memory location to be read. E 20 Enable Programmable input signal that latches the address and controls operating mode. Active level is user·defined. 0 0 .07 9·11,13·17 Data Lines TIL·compatible output lines that contain the data read from the addressed location. Vee 24 Supply + 5·V power supply GND 12 Ground Supply and signal ground 8·14 F3566 64K ROM FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Logic Symbol The F3566 8192 x 8-bit (64K) read-only memory (ROM) is designed for use in bus-organized systems requiring nonvolatile memory storage. Because of its high speed, it readily interfaces with all generations of NMOS microprocessors. An • • • • • 0, A2 A, A, Fabricated with n-channel silicon-gate technology, the F3566 has industry-standard pinouts and is compatible with other available 24-pin 16K, 32K, and 64K ROMs and EPROMs. • • • • 00 A, 10 02 11 0, 13 0, 14 0, 15 o. 16 07 17 A, A. Completely Static Operation Single 5·V Power Supply Hlgh·Speed Data Valid Time of 120 ns Access Time (tAA) of 250 ns for F3566·25 and 350 ns for F3566·35 Low Power Dissipation (440 mW Maximum Active) Fully TTL·Compatible Three·State Output Mask·Programmable Enable Function Pin·Compatlble with Other Standard 24·Pln 16K, 32K, and 64K ROMs and EPROMs 23 A7 A, 22 A. 21 A12 19 A,o 18 Al1 G GND: Pin 12 Vee: Pin 24 LOGIC SYMBOL The output enable (G) input controls the output and provides test data and valid time for high-speed microprocessor applications (see figure 1). The G input and the memory contents are user-defined. 20 Connection Diagram 24·Pin Dip The F3566 required only a single + 5-V power supply, has TTL-compatible inputs and outputs, and, due to its static operation, needs no clocking or refreshing. A7 Vee A. A. A, A. A, A'2 Signal Descriptions A, G The F3566 signals are described in table 1. A2 A,o A, Al1 Ao 07 00 O. 0, 0, 02 0, GND 0, (Top View) 8-15 • F3566 Figure 1 F3566 Block Diagram I I I I I I I I - - OUTPUT BUFFERS ttttttttt Y DECODER 1·0F·32 BYTES ADDRESS INPUT BUFFERS 1 2 - 0", u'" W", - Table 1 t1 t 2 ••• t 256 I/) a::= Wo ea: Ao TS eLi.. xC? ... - ••• 65536·BIT CELL MATRIX ENABLE INPUT ~ G BUFFER 256 Signal Descriptions Mnemonic Ao·A12 Pin No. 1·8, 18, 19, 21·23 Name Address Lines Description TTL·compatible input lines that identify the memory location to be read. G 20 Enable Programmable input signal that latches the address and controls operating mode. Active level is user·defined. °0·°7 9·11,13·17 Data Lines TTL·compatible output lines .that contain the data read from the addressed location. Vce 24 Supply + 5·V power supply GND 12 Ground Supply and signal ground 8·16 F3568 64K ROM FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Logie Symbol The Fairchild F35688192 x 8-bit (64K) mask-programmable, read-only memory (ROM) is designed for use in bus-organized systems requiring non-volatile memory storage. Because of its high speed, it readily interfaces with all generations of NMOS microprocessors. 10 Ao A, Q. 11 Q, 12 Q2 13 Q3 15 Q, 16 Q, 17 Q. 18 Q7 19 A2 A3 Fabricated with n-channel silicon-gate technology, the F3568 has industry standard pinouts and is compatible with other available 28-pin 64K ROMs and EPROMs. A, A, A6 • • • • • • • • • Address Latch Feature Automatic Power-Down Access Time (tAA) of 250 ns for F3568-25 and 350 ns for F3568-35 Low Power Dissipation (440 mW, Maximum, Active; 55 mW, Maximum, Standby) Fully TTL-Compatible Three-State Outputs Mask-Programmable Enable Function Single 5 V Power Supply Pin-Compatible with Other Standard 28-Pin 64K ROMs and EPROMs A7 25 As 24 A9 21 A10 23 A11 27 26 OE CE 22 20 GND: Pin 14 Vee: Pin 28 The chip enable (CE) input of the F3568 latches the addresses and controls the active and standby modes of operation; the output enable (OE) input controls the chip outputs and provides fast data valid time for high-speed microcomputer applications (see figure 1)_ Two chip select (CS) inputs are provided for memory expansion. The active levels of the CE and CS inputs, and the memory contents, are user-defined. II Connection Diagram 28-Pin Dip The F3568 requires only a single + 5 V power supply, has TTL-compatible inputs and outputs, and, due to its static operation, requires no clocking or refreshing. NC Vee A'2 CS, A7 CS2 A. As A, As As A11 A3 OE Signal Descriptions The input/output signal functions of the F3568 are described in table 1. A2 A,. A, CE A. Q7 Q. Q. Q, Qs Q2 Q, GND Q3 (Top View) 8-17 F3568 Figure 1 F3568 Block Diagram A12 All Al0 As CHIP SELECT INPUT BUFFERS AND LATCH Y DECODER 1·0F·32 BYTES As A7 ADDRESS INPUT BUFFERS As As A4 256 A2 • UII) 65536·BIT CELL MATRIX WN Al ~/CS2 AL 2 f/j a:3t wO Qa: OeQ A3 e-s1/CS1 Qu.. ENABLE INPUT BUFFER CE"/CE ><0 256 Ao JJ. Table 1 Signal Functions Mnemonic Pin No. Name Description Ao·A12 2·10,21, 23·25 Address Lines TTL·compatible input lines that identify the memory location to be read CE 20 Chip Enable Programmable input signal that latches the address and controls operating mode; active level is user·defined. CS1 , CS2 26, 27 Chip Select Programmable input Signals that allow memory expansion; active level is user·defined. GND 14 Ground Supply and signal ground OE 22 Output Enable Input signal that controls outputs and provides fast data valid time 0 0.07 11·13, 15·19 Data Lines TTL·compatible output lines that contain the data read from the addressed location Vee 28 Supply + 5 V power supply 8·18 F3569 64K ROM FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Logic Symbol The Fairchild F3569 8192 x 8-bit (64K) mask-programmable, read-only memory (ROM) is designed for use in bus-organized systems requiring non-volatile memory storage. Because of its high speed, it readily interfaces with all generations of NMOS microprocessors. 10 An A, A, Ao • • • • • • 12 Q. 13 Q, 15 Q- 16 Qs 17 Q. 18 Q, 19 As A. A, • 11 Q, A. Fabricated with n-channel silicon-gate technology, the F3569 has industry-standard pinouts and is compatible with other available 28-pin 64K ROMs and EPROMs. • • Q. Automatic Power-Down Access Time (tAA) of 250 ns for F3569-25 and 350 ns for F3569-35 Low Power Dissipation (440 mW, Maximum, Active; 55 mW, Maximum, Standby) Fully TIL-Compatible Three-State Outputs Mask Programmable Enable Function Single 5 V Power Supply Completely Static Operation Pin-Compatible with Other Standard 28-Pln 64K ROMs and PROMs 25 A. 24 As 21 A,. 23 Al1 27 26 ~ CE 22 20 GND: Pin 14 Vee: Pin 28 The chip enable (CE) input of the F3569 controls the active and standby modes of operation; the output enable (OE) input controls the chip output and provides fast data available time for high-speed microcomputer applications (see figure 1). Two chip select (CS) inputs are provided for memory expansion. The active levels of the CE and CS inputs, and the memory contents, are user-defined. Connection Diagram 28-Pin Dip The F3569 requires only a single + 5 V power supply, has TTL-compatible inputs and outputs, and, due to its static operation, requires no clocking or refreshing. NC Vee A,. CS, A, cs, A. As As A, Signal Descriptions The input/output signal functions of the F3569 are described in table 1. 8-19 A_ Al1 A, OE A_ A,. A, CE A. Q, Q. Q. Q, Qs Q- Q- GND Q3 • F3569 Figure 1 F3569 Block Diagram A12 A11 Al0 Ag CHIP SELECT INPUT BUFFERS Y DECODER 1-0F-32 BYTES As A7 As As ADDRESS INPUT BUFFERS A4 256 A3 8:g WN Al Cu. ee/CS2 AL 2 III a:ii= wo Ca: A2 e§1/CS1 • •• 65536-BIT CELL MATRIX ENABLE INPUT BUFFER erlCE xO Ao 256 Table 1 Signal Functions Mnemonic Pin No_ Name Description Ao-A12 2-10,21, 23-25 Address Lines TTL-compatible input lines that Identify the memory location to be read CE 20 Chip Enable Programmable input signal that controls operating mode; active level is user-defined. CS1 , CS2 26, 27 Chip Select Programmable Input signals that allow memory expansion; active level Is user-defined. GND 14 Ground Supply and signal ground OE 22 Output Enable Input signal that controls outputs and provides fast data valid time ° -° 11-13, 15·19 Data Lines TTL·compatlble output lines that contain the data read from the addressed location Vee 28 Supply + 5 V power supply 0 7 8-20 F3570 64K ROM FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Logic Symbol The Fairchild F3570 8192 x 8-bit (64K) mask-programmable, read-only memory (ROM) is designed for use in bus-organized systems requiring non-volatile memory storage. Because of its high speed, it readily interfaces with all generations of NMOS microprocessors. 10 As A, A3 02 13 A4 As Ae A7 • • • • • • • • 12 11 A2 Fabricated with n-channel silicon-gate technology, the F3570 has industry-standard pinouts and is compatible with other available 28-pin 64K ROMs and EPROMs. • a. a, Access Time (tAA) of 250 ns for F3570·25 and 350 ns for F3570·35 High·Speed Data Valid Time of 120 ns Low Power Dissipation (440 mW, Maximum, Active) Fully TTL·Compatible Three·State Outputs Mask·Programmable Chip Select Active Levels Single 5 V Power Supply Completely Static Operation Pin·Compatible with Other Standard 28·Pin 64K ROMs and EPROMs 25 A. 24 As 21 A,. 23 11" 27 28 03 15 a. 18 a, 17 a. 18 07 19 22 GND: Pin 14 Vee: Pin 28 The output enable (OE) input controls the chip output and provides fast data valid time for high-speed microprocessor applications (see figure 1). Two chip select (CS) inputs are provided for memory expansion. The active levels of the CS inputs, and the memory contents, are user-defined. II Connection Diagram 28·Pin Dip The F3570 requires only a single + 5 V power supply, has TTL-compatible inputs and outputs, and, due to its static operation, requires no clocking or refreshing. NC Vee A'2 CS, Signal Descriptions A7 CS2 The input/output signal functions of the F3570 are described in table 1. Ae Ae A, As A. An A3 ijE A2 A,. A, CE As 07 a. a, a. a. ~ a. GND 03 (TopVlow) 8-21 F3570 Figure 1 F3570 Block Diagram A12 All A l0 Ag CHIP SELECT INPUT BUFFERS Y DECODER 1·0F·32 BYTES As A7 A6 A5 ADDRESS INPUT BUFFERS CS1/CS1 CS2/CS2 256 2 A4 A3 • • A2 Al Ao 65536·BIT CELL MATRIX 256 I Table 1 Signal Functions Mnemonic Pin No. Name Description Ao·A12 2·10,21, 23·25 Address Lines TIL·compatible input lines that identify memory location to be read CS 1, CS 2 26, 27 Chip Select Programmable input signals that allow memory expansion; active level is user·defined. GND 14 Ground Supply and signal ground OE 22 Output Enable Input signal that controls outputs and provides fast data valid time °0·°7 11·13, 15·19 Data Lines TIL·compatible output lines that contain the data read from the addressed location Vee 28 Supply + 5 V power supply 8·22 F35316/F68316 FAIRCHILD 2048 X 8 ROM A Schlumberger Company Microprocessor Products Description The F35316/F68316 is a mask-programmable byteorganized MOS Read Only Memory (ROM) designed for use in bus-organized systems requiring non-volatile data storage. It is fabricated with n-channel silicon-gate technology. For ease of use, the F35316/F68316 operates from a single +5 V power supply, inputs and outputs are TTL and DTL compatible, and the device needs no clocks or refreshing because of its static operation. Logic Symbol Ao A, 00 A, 0, 10 0, 11 03 13 A, 14 Os 15 A? Os 16 23 A6 0, 17 22 Ag 19 A" A3 A, F35316/F68316 As As The F35316/F68316 is compatible with the F6800, F8 and other microcomputer families providing read only storage in byte increments. To facilitate memory expansion, the device contains three programmable Chip Select inputs providing any combination of active HIGH or LOW or an optional DON'T CARE state coupled with output wired-OR capability. Chip select code and memory content are user defined and are fixed during the masking process. C51 CS2 CS3 20 18 21 Vee = Pin 24 GND = Pin 12 The F35316/F68316 provides maximum circuit density, reliability and performance yet maintains low power dissipation and yields significant cost advantages over an EPROM approach. • • • • • • • • • Connection Diagram 24-Pin DIP 2048 x 8-BIT BUS-COMPATIBLE ORGANIZATION FULLY STATIC OPERATION 3-STATE DATA OUTPUTS FOR WIRED-OR CAPABILITY MASK-PROGRAMMABLE CHIP SELECTS FOR SIMPLIFIED MEMORY EXPANSION SINGLE +5 V ± 10% POWER SUPPLY TTL AND DTL-COMPATIBLE INPUTS MULTIPLE SPEED GRADES tACC = 250 ns, 300 ns (F35316) tACC = 350 ns, 450 ns, 500 ns (F68316) DIRECTLY COMPATIBLE WITH 2316E PIN COMPATIBLE WITH F2708 AND F2716 EPROMs Pin Names Ao-AlO CS , - CS 3 00-07 • Address Inputs Chip Select Inputs Data Outputs (Top View) Absolute Maximum Ratings Voltage on Any Pin Relative to GND Operating Temperature Storage Temperature Power Dissipation • Programmable Chip Selects -0.3 V to +7 V O°C to +70°C -65°C to + 150°C 1W Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. ThiS is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8-23 F35316/F68316 Block Diagram ",,-Vcc ...-GND AlO A9 As A7 A6 As .. a: ~ ...... .. .. u. :> :> 0. l!; A, a: A3 C C 16,384-BIT CELL MATRIX A, 128 x 128 AI Ao DC Requirements Over operating temperature range Symbol Characteristic Min Typ Max Vee Power Supply Voltage 4.75 5.0 5.25 V VIL Input LOW Voltage -0.5 0.8 V VIH Input HIGH Voltage 2.0 5.5 V DC Characteristics Unit Over operating temperature and voltage range Min Typ Max Unit Notes Symbol Characteristic lee Vee Power Supply Current 110 rnA 1 liN Input Leakage Current 2.5 /lA 2 lOUT Output Leakage Current 10 /lA 3 VOL Output LOW Voltage 0.4 V lOUT = 1.6 rnA VOH Output HIGH Voltage V lOUT = -200 /lA 2.4 Notes on following page. 8·24 F35316/F68316 AC Characteristics (F35316) Over operating temperature and voltage range F35316-25 F35316-30 Symbol 6 Symbol Characteristic Min Min TAVAV tcvc Cycle Time 250 TAVQV tACC Address to Output Delay Time 250 300 ns TSLQV tco Chip Select to Output Delay Time 150 150 ns 4 TSHQZ tOF Data Hold After Deselection 10 150 ns 4 TAXQZ tOHA Data Hold After Address Time 10 ns 4 C'N Input Capacitance 7.5 7.5 pF 5 COUT Output Capacitance 12.5 12.5 pF 5 Max Unit Note IEEE AC Characteristics (F68316) Max Max 300 150 Unit Note ns 10 10 4 Over operating temperature and voltage range F68316-35 F68316-45 Symbol Characteristic Min Min TAVAV tcvc Cycle Time 350 TAVQV tACC Address to Output Delay Time 350 450 ns TSLQV tco Chip Select to Output Delay Time 150 150 ns 4 TSHQZ tOF Data Hold After Deselection 10 150 ns 4 TAXQZ tOHA Data Hold After Address Time 10 ns 4 C'N Input Capacitance 7.5 7.5 pF 5 COUT Output Capacitance 12.5 12.5 pF 5 IEEE SymbolS Max 450 150 10 ns 10 4 Notes = COC Y,N = 0 V to 5.5 V Device unselected: VOUT = 0 V to 5.5 V Measured with 1 TTL load and 130 pF, tranSition tunes Capacitance measured with Boonlon Meter Tlmmg Parameter Abbreviations 1. All inputs 5.5 V. TA 2. 3. 4 5. 6. = 20 ns All timmg abbreviations use upper case characters with no subscripts. The initial character is always T and IS followed by four deSCriptors. These characters specify two signal points arranged in a "from-to" sequence that define a timing interval. The two descriptors for each signal point specify the signal name and the signal transitions. Thus the format is: T x x I 1 Signal name from whiCh mlervat is define_d_ _ _ _ _•_ _ _ _....J TranSItion direction for first signal - - - - - - - - - - ' I X Signal name to which Interval IS defined Transition direction /or second signal _ _ _ _ _ _ _ _ _--'-_ _ _.J The signal definitions used Hl thiS data sheet are: A = Address 0= Data In Q = Dala Oul W :::; Wnte Enable E :::; Chip Enable The tranSItion H = transition L ;:: transition V = transition X = transition Z :::; tranSition definitions used in thiS data sheet are to HIGH to LOW to valid to invalid or dan', care to OFF (high impedance) 8·25 • F35316/F68316 Timing Diagram ADDRESS ADDRESS X PROGRAMMABLE CHIP SELECTS VOH OUTPUT DATA - - - - - - - O P E N - - -_ _ _ _~ Voc • DON'T CARE INPUT CONDITION OR INDETERMINATE OUTPUT STATE Custom ROM Programming Information The customer's unique program code pattern may be submitted to Fairchild in several methods. The most convenient and readily verifiable is in the form of 2708, 2716 or 2732 EPROMs. Program code patterns may also be submitted on Fairchild Formulator MKIII floppy disks or on HP cassette tape in Formulator or MIKBUG* format. Fairchild Use Only SLNo. _________________________________ Bid Control No. ___-'-____________________ Field Sales Engineer _ _ _ _ _ _ _ _ _ _ _ _ __ Date Sent Customer Company Name _ _ _ _ _ _ _ _ _ _ _ _ __ Customer Contact Name _ _ _ _ _ _ _ _ _ _ _ _ _ __ Customer Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Address _________________________________ Phone No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Fairchild Part No. ___________________________ Customer Input Media o 2708 EPROM 2716 EPROM 02732 EPROM Floppy Disk HP Cassette Formulator Format MIKBUG Format Request for Return Media Listing o EPROM (include blank EPROMs) o o o "MIKBUG o o IS o Chip Select Information HIGH CS 1 0 0 CS2 CS3 0 a Motorola trademark. 8·26 LOW 0 Don't Care 0 o o 0 o F35316/F68316 Formulator Format o I' 2 I 3 I' I 5 I 6 7 I 8 I 9 I '0 I 11 " I M·6 I M·5 1 I M.' M·3 I M·2 1 I M .' M -S~0~R~7l-,~7l0~~A'~-A~2~-A~'~-A~O~~T~'~~T~O~~DO-'~~DO-O~D~'-'~Y'~~--~D-(n-_-')'~D~(n-_-'~~D~n'~~Dn-o~~CK~'~C~K~O SOR Start of record defined to be a colon (:) Type field. Length field defined to be the number of packed data bytes per record. Each record is (2' L) + 11 characters in length inclusive of start of record. Length 0 implies end of relocatable module. 001000 ... D(n)1 D(n)O Data field. CK, CKo Checksum field defined to be negative modulo 256 summation of all bytes since start of record. A summation of all characters in a record, including the checksum, will result in zero. Address field. All characters other than SOR are ASCII hexadecimal (O-g, A-F). Ordering Information' Part No, Order Code F35316-25 F35316-30 F68316-35 F68316-45 F3531625P, F3531630P, F3531635P, F3531645P, F3531625S F3531630S F3531635S F3531645S • P = Plastic DIP S = Ceramic DIP • For extended temperature or military range, call factory. 8-27 F35316/F68316 8-28 OJ 1 I INTRODUCTION ~2 I ORDERING AND PACKAGE ~ INFORMATION [!J 1 I F8 MICROCOMPUTER FAMILY 1 0 1 CONTROLLER FAMILY [IJ 1 1F6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY [!] 1 I ROM PRODUCTS DEVELOPMENT SYSTEMS AND SOFTWARE I[!Q] [!!] 1 I APPLICATIONS I RESOURCE AND TRAINING CENTERSI ~ 1SALES OFFICES 1 Section 9 Development Systems and Software I=AIRCHILD A Schlumberger Company General The following is data that describes the design aids available for hardware and software development and emulation in the creation of Fairchild microprocessorbased systems. • 9·3 Development Systems and Software 9-4 EMUTRACTM Emulation and Tracing System FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description • The Breakpoint Comparator Examines the 48-Blt Machine·State Word During Each Bus Cycle, and Can Detect Eight Simultaneous Breakpoint Conditions. • A Programmable Micro-Sequencer Responds During Each Cycle to the Detected Condition by: - Conditional Change in Sequence, with "Jump" or "Step" Functions; - Conditional Update of Two Independent Delay· Counters; - Optional Issue of Four Independent Pulses, to Sync External Tests; - Conditional Recording of One Trace·Frame; - Optional "Pause:' "Interrupt:' etc., Functions. • Each Trace-Frame Word Captures 64 Bits, Composed of the Address Issued During Bus·Cycle and Machine·State Word. • Interactive HardwarelSoftware Debugging is Simplified, with Symbolic LocatlonlVariable-Names, Instruction Mnemonics, and Slgnal·Names. • Simple, English·like Commands Control the Emulation Process. • Command Language Provides REPEAT, File·INCLUDE, and MACRO Capabilities, as Well as Session·Logfile and Selective·Prlntout Generation. The Fairchild EMUTRAC is a powerful, cost·effective, in· circuit emulation and tracing system that supports microcomputer system development. The EMUTRAC system allows simultaneous and interactive hardware and software development, which permits control, interrogation, revision, and debugging of a microcomputer system in its own real· time environment. Software may be developed and debug· ged with or without complete prototype hardware. • Single Controller Fits Within the F5-1 Chassis. • Interchangeable External Modules Individually Support F3870, F6800, F6809, and F9445 Microprocessors. • EMUTRAC Provides Optional Substitution for CPU and 1/0 Peripherals, as Well as Memory, in Prototype Systems. • Address·Steerlng Allows Selective Substitution for Prototype System Memory, in Blocks of 64 Words. • 8K Words (or 16K Bytes) of Mappable Substitution· RAM is Provided, Using 2114 or 2148 Devices. • 4-Blt Tags, Which Aid In Breakpoint·Marking, Can Be Associated with Individual Substitution·Memory Loca· tions, 256-Location Blocks of Prototype Memory, or 1/0 Device Accesses. • A Tag, User·Assignable Probes, Bus Data, and Functions of Key Microprocessor and EMUTRAC·lnternal Signals Comprise the 48-Bit Machine·State Word, Which Is Re· evaluated for Each Bus Cycle. • ™EMUTRAC is a trademark of Fairchild Camera and Instrument Corporation. 9-5 EMUTRAC System Function Operator Interface The EMUTRAC control software, which runs on the FS-I, has simple setup commands that provide explicit control of the memory mapping, tag attachment, breakpoint definition, and sequencer action functions. Additional commands provide the block load/dump functions for RAM definition, as well as the interactive examine/deposit-search operations usually provided in a debugger. Simple commands provide start, stop, and single-cycle control for the emulation; other commands control the operator interface providing log file and print generation, checkpoint creation and retrieval, and REPEAT, INCLUDE, and MACRO commands. The control software provides an easy-to-use, concise command structure, with HELP commands to aid on-line learning, yet aids the accomplished user through command files to perform repetitious tasks. The EMUTRAC system combines the functions of console operations, a symbolic debugger, a logic analyzer, and a substitution CPU and memory. The system consists of an EMUTRAC controller card that plugs into the FS-I development system and an external module that interfaces the controller to the target system (see figure 1). The EMUTRAC system supports all Fairchild microprocessor families, with processor-independent logic on the controller card and logic unique to a specific processor residing in the external module. Different microprocessors can be supported using different EMUTRAC modules with the same EMUTRAC controller card. Figure 1 EMUTRAC System FSI CHASSIS CPU/DISK 1-------I I I I CRT TERMINAL I I I ------------, I EMUTRAC SYSTEM EMUTRAC CONTROL SOFTWARE EMUTRAC CONTROLLER PC BOARD I EMUTRAC MODULE I I I I I I I __ ..J LAB OSCILLOSCOPE OR LOGIC ANALYZER 9-6 EMUTRAC Memory Substitution and Initialization The EMUTRAC system's RAM can selectively substitute for sections of the prototype system's memory. Thus, tablemodifications or code-patches can be made to RAM, and the results verified, without time-consuming PROM·program· ming or ROM-masking. Similarly, the RAM can be used as memory-expansion for the prototype system, permitting extra-large programs (with diagnostic or debugging aids) to be used during development and test. Trace·frame generation is controlled by the programmable sequencer. Detection of a breakpoint can trigger capture of consecutive machine cycles, and counter controls can "center" this capture window as desired. Additionally, the trace log can be considerably filtered to include only those events surrounding the trigger that satisfy additional conditions, thereby making better use of available trace memory. Alternatively, short packets of trace information can be recorded in response to multiple trigger conditions encountered during testing. Block·initialization of EMUTRAC RAM or prototype RAM (or of any control-RAM within the EMUTRAC) can be easily accomplished with the "load from " command. The complementary "dump into " provides a simple way to capture the current contents of any memory. Together, these commands allow "snapshots" to be taken, for later comparison and analysis or for quick state-restoration between test runs. Software Timing The software timing feature, which works under the control of the breakpoint sequencer, allows the user to acquire statistics on the performance of the microprocessor system software modules. The timer allows the user to measure the execution time of a block of code, as well as the number of times that block of code was used during the execution of a given program. This permits the user to estimate the performance of the total system and provides direction for optimization efforts. It can also be used to identify failing sequences that take significantly smaller or larger amounts of time than anticipated. Operator Control The console functions of the EMUTRAC system consist of four groups: run control, memory examine and deposit, 1/0 register examine and deposit, and CPU register examine and deposit. The run control comprises STOP, RESET, START, CONTINUE, and single-instruction STEP commands. The memory, 1/0 register, and CPU register examine and deposit controls allow the user to inspect and modify the state of the microprocessor, 1/0 device, and system memory registers. Locations examined can be displayed in symbolic form, and modifications can be made in terms of userdefined symbols and mnemonic instruction codes. Command· Language Features Commands to the EMUTRAC system are issued as a sequence of simple, English-like sentences; diagnostic messages in response to command errors, and the HELP command assist new users in operating the system. The accomplished user is assisted by language features such as: IF ( ... ) ELSE ( ... ) Program Breakpoints The breakpoint feature provides controlled interruptions or normal program flow when the user-selected pattern of status conditions exists, so that memory, registers, and CPU status can be interrogated and traced. To aid detection of ranges or scattered instances of address- or I/O-access, 4-bit-per-location tags are provided in EMUTRAC memory; thus, improper memory WRITE operations, access to nonexistent memory or 1/0 devices, and references to key variables are all simple to identify. The EMUTRAC breakpointing facility is extremely powerful; up to eight independent breakpoints can be Simultaneously monitored. which allows conditional command-issue, REPEAT ( ... ) which reissues a set of commands several times, INCLUDE which issues a pre-recorded sequence of commands, and MACRO ( ... ) which constructs sequences with replaceable elements. Real·Tlme Trace Control The tracing feature of the EMUTRAC system functions like a dedicated logic analyzer, giving the user a record of up to 255 previous events. The "audit trail" thus created can be used to find the cause of system failure. The EMUTRAC system, however, offers much more than a normal logic analyzer. During the emulation, all commands are recorded in a session·log file as they are issued; this file could, for instance, be printed as documentation of test results. The run can later be duplicated, or extended, by simply issuing the saved log-data as commands with an INCLUDE statement. 9-7 EMUTRAC 9-8 F38E70 FAIRCHILD Programming Board A Schlumberger Company Microprocessor Product DESCRIPTION • The Fairchild F38E70 Programming Board enables the F38E70 single-chip microcomputer to be programmed without special software or hardware on a PROM programmer that can program 2716-type EPROMs. When inserted into the programming board, the F38E70 is recognized by the programming unit as a 2716-type EPROM. • • • • The programming board is linked to the program unit by means of a cable having a 24-pin connector that plugs into the 2716 programming socket. F38E70 Programming Board g-g Enables Programming of F38E70 Single·Chip Microcomputers on PROM Programmer Units Having a 2716·Type EPROM Capability. No Special Software or Hardware Required. On-Board DC-to-DC Converter for Vpp Generation. LED Indicates V pp On. External 5V Power Supply Connector Provides Continuous Vee for Cold Programming Sockets. F38E70 Programming Board DEVICE OPERATION PROGRAMMING PROCEDURE The program or verify mode is entered when Vpp is applied to TEST 1/vpp (pin 21) of the F38E70 microcomputer. The address of the location to be programmed is applied to ports 0 and 1, and the inverse of the data to be programmed is applied to port 5. The PROG pin (pin 24) is then pulled low for. 50 ms and the data written into the designated location. (Operation of the board cannot be guaranteed when used with PROM programmers that do not utilize this method.) The following procedure is used to program the F38E70. 1. Erase the F38E70 under a suitable UV light source. 2. Configure the PROM programmer for 2716·type EPROMs, and load the data to be programmed. 3. Insert the programming board cable connector into the appropriate socket of the programmer; ensure that pin 1 of the connector mates with pin 1 of the socket. 4. Turn on the external + 5 V pow,er supply, if used. The programmer board uses a 74LS240 to invert the data from the EPROM programming unit. A 74LS244 is used to buffer the data output of the F38E70 from the data lines of the programming unit. Figure 1 shows the pin connections for the programming board, the buffer and inverter, and the device socket. 5. Set S1 to extinguish the LED (CR1). 6. Insert the F38E70 into the programming board socket, ensuring that pin 1 of the F38E70 is located near the handle of the zero·insertion·force socket. 7. Set S1 to turn on CR1. An on·board dc·to·dc converter generates Vpp voltage, which must be present during the F38E70 program verification mode. This voltage is adjusted to the required value by varying an on·board potentiometer (R3). A switch (S1) is provided to disconnect the Vpp voltage when inserting or removing the F38E70, and an LED (CR1) is used to indicate the presence of the Vpp voltage on the F38E70. The switch must be off and the LED indicator must not be lit when inserting or removing the F38E70. 8. Perform the 2716·type EPROM programming operation on the PROM programmer. 9. When programming is complete, switch off S1, verify that CR1 is extinguished, and remove the F38E70 from the programming board socket. 10. Cover the window on the F38E70 with suitable material to prevent accidental erasure. DC Characteristics The programming board logic requires constant Vee voltage; therefore, an external power supply must be used with EPROM programming units that remove the Vee voltage from the EPROM socket when not in the program or verify mode. The external power supply is connected to TB1 on the programming board after removing the Vee jumper (W1). Vee +5V±5% Current Consumption < 400 mA Ordering Information Caution Applying Vpp voltage to the TEST 1/vpp pin without the presence of Vee will damage the F38E70. PROGRAMMING VOLTAGE ADJUSTMENT To adjust the Vpp voltage to the required level (specified in the information sheet accompanying each F38E70 unit), apply + 5 V to the programming board and set S1 to turn on the Vpp voltage. Measure the voltage between pin 21 of the programming socket and ground. Adjust the potentiometer to give the correct Vpp voltage. 9·10 Order Code Description 9800224·001 F38E70 Programming Board F8 and F387X Formulator F=AIRCHILC A Schlumberger Company Microprocessor Product Description The top of the line is the Formulator Mark IIiFO. This system is identical to the Mark III, except It interfaces to the iCOM dual-drive floppy disk. The microprocessor system designer can create hardware and software development systems for the F8 and F387X by selecting modular subassemblies from Fairchild's line of F8 and F387X design aids. Development may start with a Formulator Mark I singleboard system, then expand to more sophisticated Mark II or Mark liFO development systems than can handle both software and hardware development (see figure 10-1). Future growth may lead to a complete Formulator Mark III with intelligent control panel, power supply and accessories, or to the top of the line Formulator Mark IIiFO with floppy disk drives. Three growth packages are available for Mark I, Mark II, and Mark III expansion. Growth Package I upgrades the Mark I system to the Mark II level. Growth Package II converts the Mark II to the full Mark III level. Growth Package III upgrades either the Mark II or Mark III to the Mark liFO or the Mark IIiFO floppy disk configurations. Other boards are available as options for all five Formulator configurations to increase the flexibility of the units by adding to their capabilities. These include 4K-byte RAM, 4K-byte PROM, and 16K-byte RAM boards, as well as an I/O light board, a communications board with UART, a byte-parallel board for peripheral Interface, and a PROM programmer. Three growth packages plus a selection of optional modules provide a practical method for upgrading the single-board Mark I to either the Mark II or Mark liFO, or to the maximum system configuration Mark III or Mark IIiFO. Using the growth packages, the designer can begin sophisticated system application programs at very low cost and then upgrade the development tools in relatively inexpensive steps at a later time. The most elementary configuration, called the Formulator Mark I, includes a processor module that contains an F8 CPU, program storage unit that includes a debug program, dynamic and static memory interface circuits, 1024 bytes of random access memory, and the necessary buffers and other components for hardware development. It also includes a 13-slot card cage, an I/O cable kit, and a power cable. The second level, the Formulator Mark II, includes all of the Mark I components plus a memory board with 16 kilobytes of RAM and the complete Formulator operating system, designated FOS. The FOS provides complete software development capability, including an assembler, editor, and debug package, and drivers for a teletype or the TI Silent 733 terminal. The third level, the Formulator Mark liFO, is identical to the Mark II with the addition of interface cards and cables for an iCOM F03712 dual-drive floppy disk system and Fairchild 00S4 Floppy Disk Operating System. The fourth level, the Formulator Mark III, Includes an intelligent control panel, a serial communications module, a quad I/O module, an attractive caeinet, and a power supply. Also included are 16K bytes of RAM, the Formulator processor module, and the Formulator operating system. 9-11 Fa and F387X Formulator 9-12 FS-I Fairchild System-I FA. ReM. L..D A Schlumberger Company Microprocessor Product Advance Product Inlormation Description Multi·User System The Fairchild System· I (FS·I) is a versatile, multi·user development system designed to support software development and hardware prototyping for applications using Fairchild microprocessors, including the F8, F3870, F6800, F6809, F9445, F16000, and such upcoming microprocessors as the F9450. System features include: Three principal versions of the FS-I are available: The FS-I Standard System, the FS·I Multi-User System, and the FS-I Entry-Level System. Numerous software and hardware options are available that operate under Fairchild's Interactive Multi-User Disk Operating System (1M ~OS). The FS·I also supports the in-circuit emulation and tracing (EMUTRAC™) system for the F3870, the F6800, F6809, and the F9445 microprocessors. (For a description of the EMUTRAC system, see EMUTRAC Advance Product /nformation.) • Standard System • • • • • • System features include: • • • • • • • • • • • • • • • • CPU with 128K·Byte RAM and F9445 Instruction Set. A Winchester and a Double·Density Floppy Drive Provide Approximately 10M·Byte 01 Mass Storage. 110 Controller Board Provides Winchester/Floppy Disk Controller Interlace_ Nine Asynchronous Serial RS-232C Ports (Up to 19.2K Baud) Provide Support lor CRT Terminal, Optional Letter-Quality Printer, Modem, and Other Serial Devices. One Synchronous Serial RS·232C Port (Up to 19.2K Baud) and Selectable Protocols, such as BISYNC, DDCMP, SDLC, and HDLC. PROM Programmer Port to Interlace to the Optional Fairchild PROM Programmer Unit. Parallel Printer Port (Centronics·Compatible Interlace). Programmable Real·Time Clock. One CRT Terminal. Single·User Version 01 IMDOS, System Processors, and System Utility Programs (see "System Soltware"). BASIC Language Interpreter with Interface to Custom F9445 Assembly Language Programs. FS·I Diagnostic Programs. Provides Full Support lor the F9445 and for the PEP 45 Microcomputer System. Hardware and Software Upgradable to Multi·User System. EMUTRAC Can Be Added to the Standard System. • • • • • • • • Fully Equipped lor Four Timesharing Users (Expandable to Eight Simultaneous Users with Additional Terminals and Cables). A 16·Bit CPU with 128K·Byte RAM and F9445 Instruction Set. A Winchester and a Double·Density Floppy Drive Provide Approximately 10M·Byte 01 Mass Storage. Memory Management and Protection Unit (MMPU) Board with 384K Bytes 01 RAM (Gives the System 512K Words 01 RAM). 110 Controller Board Provides Winchester/Floppy Disk Controller Interlace. Nine Asynchronous Serial RS-232C Ports (Up to 19.2K Baud) Provide Support lor CRT Terminals, Optional Letter·Quality Printer, Modem, and Other Serial Devices. One Synchronous Serial RS·232C Port (Up to 19.2K Baud) and Selectable Protocols, such as BISYNC, DDCMP, SDLC, and HDLC. PROM Programmer Port to Interlace to the Optional Fairchild PROM Programmer Unit_ Parallel Printer Port (Centronics·Compatible Interlace). Programmable Real·Time Clock. Four CRT Terminals. Multi·User Version 01 1M DOS, System Processors, and System Utility Programs (see "System Soltware". BASIC Language Interpreter with Interlace to Custom F9445 Assembly Language Programs. FS·I Diagnostic Programs. Provides Full Support lor the F9445 and lor the PEP 45 Microcomputer System. EMUTRAC Can Easily Be Added to the Multi·User System. Entry·Level System System features include: A 16·Bit CPU with 128K·Byte RAM and F9445 Instruction Set. • Two Double·Density Floppy Disk Drives Provide Approximately 1M·Byte of Mass Storage. • 110 Controller Board Provides Floppy Disk Controller Interface. • Nine Asynchronous Serial RS·232C Ports (Up to 19.2K Baud) Provide Support for CRT Terminal, Optional Letter·Quality Printer, Modem, and Other Serial Devices. • ™ EMUTRAC is a trademark of Fairchild Camera and Instrument Corp. 9·13 FS·I • • • • • • • • • • • One Synchronous Serial RS·232C Port (Up to 19.2K Baud) and Selectable Protocols, such as BISYNC, DDCMP, SDLC, and HDLC. PROM Programmer Port to Interface to the Optional Fairchild PROM Programmer Unit. Parallel Printer Port (Centronlcs·Compatible Interface). Programmable Real·Time Clock. One CRT Terminal. Slngle·User Version of IMDOS, System Processors, and System Utility Programs (see "System Software"). BASIC Language Interpreter with Interface to Custom F9445 Assembly Language Programs. FS·I Diagnostic Programs. Full Support for the F9445 and for the PEP 45 Microcomputer System. Hardware and Software Factory·Upgradeable to Standard or Multl·User System. EMUTRAC and MMPU Can Be Added to System. • • expansion Slots for Fairchild's Optional I/O Controller Boards, Optional EMUTRAC Controller Board, Memory Expansion Boards, MMPU Board, and Industry·Standard, Nova~ 1/0·Compatlble Interface Boards. Depending Upon System Configuration, the Mainframe Contains a Single 10M·Byte Winchester and a Single 0.5M·Byte Double·Denslty Floppy Disk Drive or Two 0.5M·Byte Double·Denslty Floppy Disk Drives. The MMPU board expands the physical address space of the FS-I to 4M words by performing logical-to-physical address translation. This board is required for multi-user system software. With its 384K bytes of RAM, the MMPU board extends the FS-I memory to 256K words. Hardware Options The FS-I systems support the following Fairchlldsupplied hardware options: System Hardware • The hardware comprising the FS-I development system is housed in a single enclosure that contains the mainframe CPU, I/O board, optional boards, and disk drlves_ The mainframe consists of: • • • Slngle·Board 16·Blt CPU with 128K Bytes of RAM, 4K·Byte PEPBUG45 PROMs for Bootstrapping the l$ystem, Real·Time Clock, an RS·232C·Compatlble Port, and a Centronlcs·Paraliel Compatible Port. • Power Supplies. • I/O Controller Board with the Following: • Eight Asynchronous Serial RS·232C Ports, with Four Ports Having Full Modem Control and All Ports Having Data Rate Selectable Up to 19.2K Baud, that Allow Timesharing by Up to Eight Concurrent Users on Systems Equipped with MMPU Board and Multi·User Operating System Software. • One Synchronous Serial RS·232C Port (Up to 19.2K Baud) and Selectable Protocols, such as BISYNC, DDCMP, SDLC, and HDLC. • A Parallel Data Channel Interface Compatible with Shugart Associates System Interface for Communicating with Disk Units. • 8-Blt Parallel Port to Interface with Optional Fairchild PROM Programmer. • A Total of Nine Asynchronous Serial Ports (R8-232C· Compatible, DB25·Pln Female Connectors). • One Parallel Printer Port (Centronlcs·Compatible Interface, DB25-Pln Connector). • • • • • • Additional I/O Controller Boards that Provide Asynchronous RS·232C Ports (Up to 19.2K Baud) in Sets of Eight, a Synchronou~ RS·232C Port for each I/O Controller Board, Data Channel Interface to Disk Units, and a PROM Programmer Port for each I/O Controller Board. Fairchild's PROM Programmer Unit. MMPU Board that Provides Memory Mapping and Protection Expansion In Increments of 384K Bytes, Optional Multi·User Software Allows the MMPU Board to Support Eight Simultaneous Users. Memory expansion Board that Provides 384K Bytes of Additional RAM (Requires an MMPU Board In the Chassis). EMUTRAC System Controller Board that Provides the Hardware Interface Between the CPU Board In the FS·I and Processor·Speclfic EMUTRAC Modules. EMUTRAC Modules and EMUTRAC Control Software that Support the F3870, the F6800, the F6809, and the F9445 Microprocessors. Additional CRT Terminals. Dot Matrix Printer-Texas Instruments Model 810 Basic RO Terminal (150 CPS), Centronics Parallel Interface, and Cable. Daisywheel Lelter·Quality Prlnter-Qume Model Sprint 9145 with Bidirectional Forms Tractor (45 CPS), Serial Interface, and Cable. .. Nova Is a registered trademark of Data General Corp. 9·14 FS·I System Software PHONE The interactive multi-user disk operating system (IMDOS) is the principal operating system for the FS-I. In addition to being an operating system, the IMDOS includes the following features that are useful for developing F9445-based systems: The PHONE program establishes communication between the FS-I and a modem or telephone line_ Software switches govern communication protocols_ SCRIPT The SCRIPT program processes a text file that contains SCRIPT commands to producean aesthetically pleasing document. TYPESET The TYPESET program processes 11 text file that contains TYPESET commands to produce an aesthetically pleasing document. TESTS A series of programs that test the FS-I hardware_ The diagnostic programs are available on diskette in a version suitable for downloading to an F9445-based system_ BASIC Language interpreter with interface to custom F9445 assembly language programs_ IMDOS Single-User Supervisor-The supervisor manages the FS-I resources and controls the 1/0_ Multi-User Supervisor-The supervisor manages the FS-I resources for up to eight simultaneous users, controls the 1/0, and interfaces transparently to the MMPU board (included only with the multi-user system)_ Executive-The executive provides the command language interface between the user and the supervisor. EDIT The EDIT program provides the ability to create and modify text files_ MACRO The MACRO program is the macroassembler for F9445 macro assembly language_ RELOAD The RELOAD program is used to link relocatable macro assembly language programs to create executable F9445 absolute assembly language programs_ PEPBUG-45 PEPLINK Utility Library This powerful software package, which is included with the standard, multi-user, and entry-level systems, offers advanced capabilities that the user would normally expect from a much larger system, such as: • • The PEPBUG-45 program is a virtual console and debugging tool for F9445 absolute assembly language programs_ The PEPBUG-45 program is also available in PROM_ • • • • • • Provides capability to download programs from the FS-I to PROM or RAM on the PEP 38, PEP 45, and PEP 68 microcomputer systems_ • • Implements the utility functions listed in the FS-I User Guide_ 9-15 Multi-User Timesharing System Executive, Including File Management System with Version Numbers for Automatic Backup Memory Management and Protection by Memory Mapping Password Protection Interactive Command Language and Command Files Multiple Directory Devices Device-Independent 110 Hard Disk, Magnetic Tape, Modem, and Real-Time Clock Support Documentation Aids Concurrent Processing and Spooling FS·I FS·I Command and Utility Summary Software Options F9445 MICRO FORTRAN F9445 PASCAL FS·I/PEP 38 System Software FS·I/PEP 68 System Software F16000 Cross Software F9445 REX F9445 PEPBASIC EMUTRAC Control Software ABTOSV fs1, fs2 Converts an absolute binary file into a save file. An extended subset of FORTRAN66 that interfaces with custom F9445 assembly language subroutines. MICROFORTRAN produces "ROMable" F9445 code and can be operated under the real-time executive (REX). A Jensen and Wirth·compatible PASCAL. The F9445 PASCAL compiler generates F9445 code and interfaces with custom F9445 assembly language subroutines. Includes F8/F3870 cross assembler and program for downloading to the PEP 38 system. Includes F6800 cross assembler, F6809 cross. assembler, F6800·to· F6809 translator program, and program for downloading to the PEP 68 system. Assembler, debugger, and downloader allow the FS·I to generate 16000 code that can be downloaded to an F16000·based system. A real·time executive for F9445·based systems. The REX system allows creation 6f custom REX programs, linkable using RELOAD. A diskette version of PEPBASIC (supplied on PROM with the PEP 45 system). A 2K-word subset of BASIC, which accepts abbreviations, that Is extendable with custom F9445 assembly language subroutines. APpend fs1, fs2 Appends a copy of fS1 to the end of fs2. APR/" ... Special print routine ARITH45 Tests arithmetic instructions. BACKUP Backs up a file or a group of files. BASIC Invokes the F9445 BASIC interpreter. BINCOM/' (fs1, fs2) Compares two or more files. CHI" fs Makes an entry in the change log before editing a file. CLEANSE/" (fs) Removes all but the highest version of all flies. CLear Closes any open files and clears I/O channels. COMPILE Invokes the F9445 Pascal compiler. CONFIGURE Creates a custom version of IMDOS. Copy fs1, fs2 Copies file1 to file2. COPYMINSYS Copies a minimum system from unit 0 to unit 1. CP (fs1, fs2) Copies files and compares original and copy. DElete fs' (I") Deletes files. Ailows wildcards. Directory (n:)(fs") Lists file(s) and chain table. Allows wildcards. Optional EMUTRAC control software packages provide support for each processor-specific EMUTRAC module. (Refer to EMUTRAC Advance Product Information.) In addition, all Fairchild software for the FS·I is independently available without system purChase under an appropriate software license agreement. 9·16 DUmp fs(/") Dump a file in octal or decimal. EDIT Invokes the editor. EDit fs Edits a particular file. EMUTRAC T: Invokes EMULTRAC EXER45 Exercises the FS-I hardware. FS·I F38ASM Invokes the F3870 cross assembler. F68ASM Invokes the F6802/F6808 cross assembler. F69ASM Invokes the F6809 cross assembler. FIND/' «in) (>out) FORMAT MLiMIT Tells the IMDOS the highest location (in lower 32K words of memory) used by a program. MPMACS IN Includes file for creating manual pages. OEDIT fs Examines and allows modification of disk files. Gets information from a keyed source file. ONline m,n,x, ... Places devices on line and specifies order of search. Prepares a disk to become a system or data disk. OUtput fs Directs output of List, Directory, SPace commands to a file. PASSWORDS Creates user names, sets passwords, etc. (2-only). FORTRAN Invokes the MICROFORTRAN compiler. GET n Displays contents of location n (octal). GOodbye Loss user out. PAUSE Halts a program and waits for a (RETURN) to continue. Finds and outputs lines that match the pattern. PEEK Examines status of the 1M DOS, including use of buffers. H ELP/' (topiC)... Shows help information. PEPBUG45 Invokes the PEPBUG45 debugger. INput fs Reads and executes commands from a file. PHONE (10) port Enables communication with a device attached to a port. LlBEDIT/' ... Manipulates libraries of relocatable binary files. PRE/' '" Preprocesses fi le(s). PUT n List (n:) (fs') Lists files on a device. Allows wildcards. Enters octal number into memory location opened by GET. LlSTPASSWORDS Lists user names, passwords, default security (2-only). PRint fs Prints a file on the line printer (L:). QCOPY/' (Is) Prints a Ii Ie on the letter-quality printer. LOad Is Loads a lile into memory. READ.ME LOGin user- Loss in a user; password required. Type this Ii Ie lor information about a release. MAC/' «in) (>out) RELOAD/' Invokes the linker/loader. General macro processor REname IS,new-ls Renames a Ii Ie. RESTORE Returns programs created with BACKUP. RUN Is Loads and executes a lile. Is Executes Is.SV; il no .SV, executes Is.CM. GREP/' pattern ... MACRO/' ... Invokes the F9445 macroassembler. MEM45 Tests the FS-I memory. MINIREPAIR Checks and repairs directory structure on a disk. MISC45 Tests miscellaneous F9445 hardware instructions. 9-17 FS·I SAVE fs,loc: .... ,addr Saves the contents of memory in a file. TAPEWRITE Writes tapes in various formats (EBCDIC etc.). SCRIPT in,out,los Creates a formatted document. TErminal type Identifies terminal type to the IMOOS. TIMER45 Runs instruction set timer. TRANS09 Translates an F6802/F6808 source to F6809. TYpe fs Writes contents of a file on the screen. TYPESET Creates a formatted document. WRITESYS Creates/updates the IMOOS on a system disk. SEcurity fs/code Changes the security protection on a file. SORT/" ... Sorts a file (about 500·line limitation). SPace Shows space useage on disk. STart addr Starts a program in memory at an address. SVTOAB Converts a save file into an absolute binary file. TApe n(.) Sets record length on a tape; octal or n. = decimal. Dimensions and Power Requirements TAPEREAD The FS·I standard mainframe enclosure measures only 26 inches long by 19 inches wide by 13 inches high. It requires a 115 V, 60 Hz ac power source. A 50 Hz system is also available. Reads various tape formats. 9·18 PEP 38 Prototyping, Evaluation and Programming Board FAIRCHILD A Schlumberger Company Microprocessor Product Advance Product Information Description A single-board microcomputer for program development timing, debugging, and emulating the F387X family of single-chip microcomputers, the PEP 38 system includes and F38E70 EPROM microcomputer programmer, an onboard keypad, address and data displays. A 40-pin emultation cable is also provided. Features • • • • • • • • • • • • • • Full In·Circuit Emulation of the F3870 and F3872 Microcomputers On·Card Keypad for Command and Data Entry On·Card 7·Segment Address and Data Displays Programming Sockets for F38E70s and 2716s 2K Bytes of 2114 Static RAM Plus Space for an Additional 2K Bytes Space for 6K Bytes of 2716 EPROM 2K·Byte Firmware Monitor Flexible Memory·Map Strapping Options Crystal·Controlied System Clocks Four General·Purpose Programmable Timers Four General·Purpose Interrupt Controls Current·Loop and EIA RS232C Serial 110 Spare 8·Bit 1/0 Port Requires Only + 5 and + 12V Supplies 9-19 PEP 38 9·20 PEp·45 Prototyping, Evaluation and Programming Board FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description Software Support The Fairchild PEP-45 is a single-board microcomputer for Prototyping, Evaluation, and Programming of microprocessor-based system applications using the F9445 microprocessor. When used with the Fairchild System-I (FS-I) development system, the PEP-45 board provides capability for executing and debugging software directly on the F9445 microprocessor. In addition to serving as an efficient stand-alone evaluation module, the PEP-45 is designed to operate as a key module of the FS-I development system. A PEPLINK utility transparently couples the F5-1 video terminal to the PEP-45 board. A powerful PROM-based PEPBUG debugging monitor provides commands for trouble-shooting assembly language programs and for developing and testing peripheral circuits and custom Interfaces. A PROM-based PEPBASIC language aliows programming In a high-level language. • Stand-alone Prototyplng, Evaluation, and Programming Board. • Provides a Po_rful Development Tool to Support F9445 Microprocessor-based System Development. • Utilizes All the Advantages of the F9445 Microprocessor, with Its Powerful Instruction Set and High Throughput_ • Memory Options for Bipolar and NMOS Memories_ • Interfaces with IEEE 796 Standard Bus. • Buffered F9445 bus. • On-board EPROM Programmer_ • Adapts to 16K or 32K Byte EPROMs or 64K Byte Masked ROMs_ • Standard- and High-Speed RAM Options_ • Console Commands_ • Two Serial I/O Ports. • 16-Blt Parallel Input/Output. • Four Interrupt Sources_ • Five Status Lines_ • On-board +12 V and +25 V Voltage Convertef_ • Requires Single +5 V Power Supply_ Hardware Specifications Microprocessor CPU F9445 Data word size 16 bits Instruction word size 16 bits Address capability 128K bytes Console controller F9470 Memory RAM The PEP-45 board Is primarily Intended for use In hardware prototyping and software development applications. It may also be tied to a host computer, such as the F5-I, for large program editing, assembling/compiling, and general file storage and handling. Cross-assembler software packages are available for creating machine-executable programs in formatted form. These programs may be down-loaded from the host computer system into the PEP-45 board via one of the two serial I/O channels. Since the PEP-45 board can operate In a transparent fashion, it may be placed in-line between the user's in-house terminal and the host computer, giving the PEP-45 the power of the host. ROM Eight sockets for 16K bytes of F2716 EPROMs (8K words), or up to 32K bytes using F2732 EPROMs (16K words), or masked 64K byte ROMs using F3564 Expansion External memory in any combination of RAM or ROM up to 64K bytes maximum (in 16-bit-wlde only) Input/Output Parallel 110 Also useful for incoming inspector of F9445 parts and as a microcomputer training tool, the PEP-45 interacts with the user at the control terminal, with prompts that assist programming. The control terminal may be a video terminal, printer terminal, or from amlcrocomputer control console. 9-21 8K bytes (4K words) static RAM (or optional high-speed RAM) Two TTL-compatible, 16-bit 110 ports (one Input, one output) Serial 110 Two programmable, asynchronous channels, with R5-232 interfaces. Each channel is software-selectable to a baud rate of 110, 300, 1200, 1800, 2400, or 4800 baud Real·Tlme Clock Continuously selectable real-time clock interrupts from approximately 200 j$ to 200 ms PEp·45 System Buses Dual backplane buses Power Supply Requirements l PI- An 86-pin asynchronous sys· tem bus compatible with standard Multibus 16-bit slave boards and multi·master option Environmental Requirements P2-A 6O·pin buffered F9445 bus that allows complete expansion of processor capabilities and faster operating speeds I/O buses Temperature ODC to +50 DC Humidity 0% to 90% (noncondensing) Physical Envelope Dimensions2 J1-A 9-pin RS·232C serial I/O interface for control terminal J2-A 9·pin RS·232C second serial I/O interface for a serial printer or a host computer P3-A 40·pin applications con· nector with two parallel I/O ports (one input and one output), and with status and control bits. May be used for connection to the microcomputer control console or to a high·speed parallel printer (Centronics·type) Connectors +5 V ±5% at 3.5 A (typ) 10.0 (254) 12.0 (305) Height Length Thickness 0.75 (19.05) Weight 17 oz. (approximately) Noles I. Power may be applied to the board either through the card·edge backplane connector or by connection of discrete wires to the board. 2. All dimensions are in inches and millimeters (in parentheses). Fairchild cannot assume responsibility for use of any cir· cuitry described other than circuitry embodied in a Fairchild product. P1 - An B6-contact, double·sided edge connector on 0.156" centers Fairchild reserves the right to make changes in the Circuitry or specifications at any time without notice. P2 - A 60·contact, double·sided edge connector on 0.100" centers J1, J2-9·pin, D·type subminia· ture right·angle connectors P3-A 40·pin, double·sided edge connector on 0.100" centers. Ordering Data Part Number Product Code PEP 9445SFX A F944516PEP Description PEP-45 Board with BK byte PROM sockets populated with PEPBASIC and PEPBUG firmware. Firmware carries copywriter notice. Minimum of four PROM sockets will not be populated. PEP-45 Users Guide, PEPBASIC, and PEPBUG Users Guide supplied. PEP 9445SXX A F944516PEP PEP-45 Board with BK byte static MOS and eight PROM sockets not populated. PEp-45 Users Guide supplied. No firmware included. PEP 9445HXX A F944520PEP PEP 9445 Board with BK byte high speed RAM and PROM sockets not populated.' PEP-45 Users Manual supplied. No firmware or users guides included. 9-22 PEP 68 System Single-Board Microcomputer Development System FAIRCHILD A Schlumberger Company Advance Product Information Microprocessor Product Description • Single· Board, Stand·Alone System • Processor Options-6802, 6808, or 6809 • Asynchronous Multibus· Compatible • Auxiliary Synchronous 680X Bus • Programming Socket for 2716 or 2732 EPROMs • 8K·Byte System Monitor in ROM • 9K Bytes of Static RAM-8K User, 1K System (Write· Protectable Segments) • Six Sockets for User·Supplied ROM/EPROM (2K, 4K, or 8K Types) • Sixteen Possible Memory Map Configurations (Switch·Selectable) • Two High·Speed Audio Cassette Tape Interfaces • Two Independent Serial 1/0 Channels-RS·232·C • Independent Baud Rate Selection-50 Through 19.2K bps • Connector for Parallel Printer (Centronics Type) • Six 8·Bit Parallel 110 Ports Plus Controls • Three Programmable 16·Bit Binary Timers • + 5 Volt-Only Operation The PEP 68 System is a single-board microcomputer specifically designed to aid microprocessor hardware/software designers in designing, prototyping, and debugging their 6802-, 6808-, or 6809-based system. A powerful, ROM-based debugging monitor provides commands for trouble-shooting machine-language programs. Other monitor commands provide for easy development and testing of peripheral circuits and custom Interfaces. The monitor includes a full complement of utility routines to make the hardware/software/firmware design cycles as easy as possible. The PEP 68 System is useful as a microcomputer training tool. Its friendly interaction with the user at the control terminal, through its liberal use of prompting, makes procedures easy to learn for the beginner. The system can be operated using only a serial display terminal and a power supply. Since the system possesses two separate bus connectors, expansion with external memory or peripheral boards is simply a matter of providing a backplane connection. Thus, the PEP 68 System can act as a bus master in a multicard system. • 'Multibus is a trademark of Intel Corporation. 9-23 PEP 88 Block Diagram Multibul Edge Connector - AuXIII.ry Synoh"'....... BUI Edge • norll 1/0 P... llttl ....nler Comoctar (Also lor G.n... ~ PurpuoollO) Hardware Description . The PEP 68 System Is a single-board, stand-alone microcomputer utilizing either a 6802, 6808, or 6809 microprocessor as its central processing element. The system may be connected to a Illrger, host computer system to utilize that system's til~ storage; editing; and assembling capabilitieS. Thus, source language programs can be created, edited, and assembled on the host computer system using PEP-UP cross-assembler software packages. Theresultln·g machine-language programs Can then be downloaded Into the PEP 68 System on·board RAM, executed, and debugged. on the other hand, allows for system expansion with peripheral boards that use the Industry-standard Multlbus Interface. The asynchronous aspect Is accomplished by stretching the CPU's system clock. :Both bus Interfaces on the PEP 68 System can simultaneously connect to external peripheral boards. However, the PEP 68 System can be the only master central processor board In the system. Memory The PEP 68 System contains 8K bytes of on-card static RAM storage for user application programs. Each 4K-byte segment can be separately write-protected by means of either an on-card switch or by signals at the bus edge connectOr. There are an additional 1K bytes of RAM for use by.the board's ROM monitor. A total of six ROM or EPROM sockets Is provided on-board. Each can be jumpered for either 2K, 4K, or 8K-byte devices, i.e., many of the various 24-pln ROMs or EPROMs. Normally, one or two of these sockets contain the FAIR8UGl68 monitor ROM, but If desired, they can be used for user code Instead. Dual Bus Interfaces The PEP 68 System can also serve as the central processor in a multlboard system with connections to peripheral boards accomplished via a bus Interface and the cardcage backplane. It has two separate bus Interfaces: one synchronous and one asynchronous. The synchronous bus Interface Includes the system CPU signals and allows for expansion using synchronous 680X peripheral boards. The asynchronous bus Interface, 9-24 PEP 68 All on-board memory and I/O address decoding is done through the use of a bipolar PROM. This PROM and the four DIP switches tied to it allow the user to select one of 16 different memory map configurations depending on system requirements. This feature is especially useful during the program development phase of a project since the user's code can be resident in either RAM or EPROM and can be relocated with a switch change. interfaces are driven by code contained within the monitor, thus minimizing the required hardware circuitry. The recording format is a self-clocking method that allows synchronous data transfers rates of up to 2000 bits per second. Connections between the recorder and the board are made with subminiature. phone jacks. Serial 1/0 Channels The PEP 68 System provides a zero-insertion-force socket for electrically programming 2716 and 2732 type EPROMs; therefore, the user's application programs residing in RAM can be preserved by "burning" the code into an EPROM. Subsequent execution can be from either RAM or EPROM. The programming socket is driven by signals from three of the six on-board 1/0 ports. The monitor provides commands to perform the following: blank check tests, copy EPROM contents to memory, verify EPROM contents against memory, program any portion of EPROM, and masking non-blank EPROMs against code in memory. EPROM Programming Socket The board contains two serial 1/0 channels. Both channels are general-purpose and may be used with any serial RS-232-C device. One channel is normally used for communication with the user's control terminal; while the second channel would normally be used for the interface to the host computer system. However, this second channel could be used for any serial I/O use, such as a printer or modem. The RS-232-C interfaces generate their own + 12 and -12 volt levels. Thus no additional supplies, other than the +5 Vdc supply, are required. Software Description Each channel has a separate baud-rate clock circuit in which the baud-rate is hardware switch-selectable. This allows very fast communication with a local command ~erminal on channel 1 and communication with a slower speed device such as printer, modem, or phone link on channel 2. Allowed baud rates on each channel are 50, 110, 150,300, 1200, 1800, 2400, 4800, 9600, or 19,200 bps. • • • • • • Parallel 1/0 Ports and Programmable Timers • • The PEP 68 System has six 1/0 ports and associated control signals that can be used for general-purpose input/output. Four ports are available at the top card edge connector, while the remaining 2 are accessible via a speCial plug-in connector. The latter two ports can be used optionally for driving a high speed parallel printer with a special cable that attaches to the board through the plug-in connector. • • • • • • • The signals and controls associated with the three binary timers are accessed via the card edge conneCtor. Each of these three software programmable timers is 16 bits long and can be operated in several different modes, including continuous, single-shot, frequency comparison or pulse-width comparison modes. . • • Audio Cassette Tape Interfaces • There are provisions on the PEP 68 System for connecting two audio cassette tape recorders for storing and retrieving user's applications programs. The • • 9-25 Display or Alter any CPU Register Display or Alter any Memory Location Display a Range of Memory Display the Previous (or next) Location in Memory Rapidly Input Consecutive Data Strings to Memory Find (search for) the Address of the Next Occurrence of a Specified Data String Fill a Range of Memory with a Given Data String Move (Copy) a Block of Memory from One Address Range to Another Address Range Go to an Address and Begin Executing a User Program Load a Formatted File from Either Serial Channel with an Optional Address Bias (Multiple Formats Allowed) PunchlDump a Formatted File to Either Serial Channel with an Optional Address Bias (Multiple Formats) Compare Two Memory Ranges for Differences Calculate Checksums Over a Range of Memory Insert a Program "Patch" Disassemble Machine Code into Assembly mnemonics Set, Clear, and Display up to 8 Address Breakpoints Remove all Breakpoints Temporarily and Then Be Able to Restore Them Intact Continue or Resume Execution After a Break Occurs or After Stopping or Tracing Calculate Relative Branch Offsets and Perform Double, Precision Hexadecimal Arithmetic Program 2716 or 2732 Type EPROMs PEP 68 • Transparent Mode Operation for Conversing with a Host Computer from the Same Command Terminal • Echo Incoming Data from Either of the Serial 110 Channels to the Parallel Printer Port • Echo Monitor Output to Parallel Printer Port for Hardcopy of Monitor Output • Enter ASCII Strings to Memory • Print ASCII Strings from Memory • Keyboard Test Mode • 32 User·Definable Functions • ExaminelAlter 1/0 Port Bits • Slngle·Step Program Execution Through NN Instructions of a Program • Step Through Instructions Conditionally Until Specified Condition is Met • Trace Through NN Instructions Displaying the CPU Registers After Each Instruction • Trace Through Instructions Displaying CPU Registers After Each Occurence Until Specified Condition is Met Applications Low·Cost Development System HIGH SPEED PARALLEL PRINTER MODEMI ACOUSTIC COUPLER OR ANY RS-232-C SERIAL DEVICE FBB PEP SYSTEM TERMINAL More Powerful Development System HIGH SPEED PARALLEL PRINTER HOST COMPUTER SYSTEM FB8 PEP SYSTEM USER'S COMMANO TERMINAL AUXILIARY TO BUS SYNCHRONOUS BACKPLANE TO ASYNCHRONOUS BUS BACKPLANE I I 9-26 PEP 68 Dedicated Use 2 SERIAL 1/0 1...,...-_-_-_-_-_-..,--- CHANNELS - - - , I ___ ~r 6 PARALLEL 110 PORTS PLUS 3 TIMERS F68 PEP SYSTEM TO ASYNCHRONOUS BUS BACKPLANE (OPTIONAL) TO SYNCHRONOUS BUS BACKPLANE (OPTIONAL) I I Multl·Bus Card Cage Use • 9·27 PEP 68 Hardware Specifications Timers Hardware Specifications 3 Binary Timers Three separate 16-bit binary counters Microprocessor CPU 6802, 6808, 6809 Data word size 8 bits (1 byte) Instruction word size 6809: 1-4 bytes 6802/6808: 1-3 bytes Cycle time 1.0 p,s System clock 4,000 MHz Address capability 65,536 bytes Each independently software controlable and readable Each with external clock and gate controls for frequency and pulsewidth measurements Each with a counter output pin Interrupts Hardware Memory One non-maskable interrupt line available at both system bus edge connectors (wired-OR to the Restart pushbutton switch for initiating manual interrupts) RAM 9K bytes, static 2114 RAM on-board One maskable interrupt line for fast interrupt response (6809 only) ROM Six sockets for 24-pin ROMs or EPROMs. Accepts device types: 2516,2716,2532,2732,68316,68332, 68364, or 68764 (Le., anywhere from 2K to 48K bytes of ROM) One maskable I/O interrupt line Expansion Software External memory iri.any combination of RAM or ROM up to 64K bytes maximum Input/Output Parallel I/O Six TTL-compatible, bidirectional 8-bit I/O ports with two port controls each Serial I/O Two programmable, asynchronous channels with full RS-232-C interfaces· Each channel is double-buffered and has independent switch-selectable baud rates of 50, 110, 150, 300, 1200, 1800,2400,4800,9600, or 19,200 bps 9-28 Software interrupts available: 1 for 6802/6808 3 for 6809 PEP 68 System Busses Power Supplies Dual Backplane Busses Requirements P1-an B6·pin· asynchronous system bus compatible with standard Multibus slave boards (multi·master options not supported) + 25 Vdc @ 30 mA (typ) (used for EPROM programming only) Environmental P2-a 60·pin synchronous MPU bus that allows complete expansion capabilities and faster operating speeds 110 Busses +5 Vdc ±5% @ 2.5 A (typ) Temperature o to Humidity o to 90% (noncondensing) +50·C Physical Oimenslons2 P3-a 60·pin applications bus with four parallel 1/0 ports with controls, plus three sets of counter controls for the three on·board binary timers P4-a 25-pin applications connector with two parallel 1/0 ports with controls; can be used for connection with a high-speed parallel printer (Centronics type) Height 8.0 (203.2) Length 12.6 (305) Thickness 0.672 (17.1) Weight 17 oz. (approximate) P5-a 9-pin RS-232-C serial 1/0 interface 1. P6-a 9-pin RS-232-C serial 1/0 interface Power can be applied to the board either through the card-edge backplane connector, or by connection of discrete wlres to the on· board screw-down terminal strip. 2. All dimensions in inches bold and millimeters (parentheses) Nole. Connectors P1-86-contact, double-sided edge connector on 0.156" centers P2-60-contact, double-sided edge connector on 0.100" centers P3-60-contact, double-sided edge connector on 0.100" centers P4-25-pln, subminiature Ootype right angle connector P5, PS-9-pin, subminiature Ootype right angle connector 9-29 PEP 68 Ordering Information Order Number PEP680XCSD 10:: Relocatable Macro Cross-Assembler Software Packages for F6800, F6801, F6802, F6803 Using Intel MDS-800 Series Development Systems Description The PEP 68 System is available with cross-assembler software packages that allow users of Intel development systems to do software development for F6800, F6801, F6802, and F6803 CPUs on their own systems. The crossassembler software· package is compatible with both the Motorola and Fairchild language syntax. Useful features similar to those of the 8080/8085 Assembler are included to provide systems compatibility. PEP 68 Single Board Development S ,",m NN = without cross-assembler 1--_ _ _ The assembler accepts the user's source program as input and translates it into machine-executable code. Relocatable object modules are linked together into load modules and then into execution modules under the ISIS-II operating system. Application programs can then be downloaded in a formatted form through a serial port to the PEP 68 System's on-card memory. Now the program can be exercised and debugged using the FAIRBUG/68 debug monitor. specifies CPU type 8 = 6802/6808 CPU or 9=6809 CPU for Intel MDS systems (single density floppy disk) for Intel MDS systems (double density floppy disk) • • • • • • • 9·30 680X Cross-Assembler Software Package Intellec 800 and 888 Series II Compatible Full Macro Capability Expanded Relocation Capability Expanded Assembler Directives Comprehensive Conditional Assembly Includes Logical, Comparative, and Expression Truncation Operators I=AIRCHILD Software Packages A Schlumberger Company Microprocessor Product convenient and powerful programming debug facility to aid in the development of F8 or F387X programs. The debugging program provides the user with an interactive system via a teletype terminal or via a 4 x 6 keypad. This is the standard debugging aid provided with the PEP 387X development board. Several software packages are offered by the Microprocessor Division for the system developer. A brief description of each one follows. F8 Formulator Disk Operating System Version 4.0 (0054) The Formulator Disk Operating System version 4.0 (DOS4) provides the F8 or F387X system developer with a complete set of tools for software development including source program editor, relocatable assembler, linking loader and interactive debugger. Also included are many utilities for efficient use of the floppy disk subsystem and support for a number of other standard peripherals. The DOS4 is an improved and streamlined version of the F8-D03 with added capability and greater ease of use. Minicomputer F8/F387X Cross Assembler The Fairchild F8/F387X Cross Assembler is designed for use on any 16-bit word length minicomputer with an ANSI FORTRAN IV Compiler. The Cross Assembler is independent of machine character representation and numerical representation. Minor alterations may be required to satisfy various Computer/Operating System/Peripheral Device combinations. FAST Softw,re Debugger Installation and modification of this program should be performed by a programmer who is quite familiar with FORTRAN IV and with the hardware and software configuration of the target computer. Under such circumstances, installation can probably be completed in one or two days. The FAST software debugger (FSD) is a fast software debugging monitor for F8/F387X microcomputer systems programs. Its speed and ease of use meet or exceed any other method of debugging F8/F387X programs. The FSD is designed for use with the Fairchild F387X programming, evaluation, and prototyping (PEP) board. It replaces the PEPBUB monitor chip provided with the board and allows all operations to be performed through a CRT terminal rather than through the PEGBUG keypad. It does not support parallel paper tape 110. F9445 BASIC Language Package The Fairchild BASIC language interpreter for F9445-based systems is specifically tailored to high-performance microcomputing, providing a powerful, interactive programming language that can be used to solve a wide range of application problems. It incorporates extensions of and modifications to the BASIC language originally developed at Dartmouth College. The Fairchild enhanced BASIC increases the capability and flexibility of the language with a complete set of data types, additional statements and functions, comprehensive data management facilities, file management an I/O control and multi-dimensional array capabilities. Interface to custom F9445 assembly language programs is also provided. The BASIC language is fully supported by the F9445 Interactive Multi-User Disk Operating System (IMDOS), which allows full use of the extensive operating features of IMDOS, such as independent 110 and the ability to dynamically create, access, and delete files. FAIRBUG A special Debug ROM 3851A PSU provides the F8 user with a convenient and powerful programming debug facility that is used in the development of F8 programs. This debugging program (FAIR-BUG) provides the user with an interactive system via a teletype terminal. The following capabilities are provided: Display or Alter Memory locations Display or Alter Scratchpad Registers Display of Alter Accumulator, ISAR, Status rN Register) Display or Alter PCO, DCO, DC1 Load Formatted Paper Tape Punch Formatted Paper Tape Punch Paper Tape in PROM Format Entry from Keyboard or by Program Instruction 110 Subroutines available to user F9445 PEP BASIC Language Package The Fairchild PEPBASIC, designed to reside in a 2K PROM, retains the essential simplicity and computational power of BASIC. PEPBASIC provides a unique capability to extend and customize programs, either through enhancements written by the user in F9445 absolute assembly language. Versatile applications like real-time process control, data acquisition, or math packages can be created, based on the general-purpose facilities available within PEPBASIC. F8IF3870 PEP BUG A special F38T56 PSU with a debug monitor (PEPBUG 38) has been developed by Fairchild to provide the user with a 9-31 Software Packages To time an instruction, a short loop containing the instruction is executed and its time lapse compared to a null (no instruction) loop, during the transmission of one character, The 1/0 terminal displays the resulting times. The user specifies the Baud rate of the 1/0 device at program execution time in reponse to a program prompt. F9445 PEPBUG Package The Fairchild F9445 PEPBUG package is the interactive entry and debugging software for use with the F9445 family of microprocessor products. The PEPBUG 45 software package creates a versatile and efficient control environment, enabling the user to enter and test F9445 absolute assembly language programs interactively. It is unique among the programs offered with the F9445 family in that it gives the user control of the microprcessor through a video terminal, provides many different capabilities in a single stand-alone mini-executive program, and occupies a relatively small amount (2 thousand bytes) of memory space. F9445 MICRO FORTRAN Language Package The Fairchild MICROFORTRAN package is a ligh-Ievel language compatible with the F9445 microprocessor based family of products, providing a powerful too,1 for structured program development. Subroutines and functions are independently compiled, and translated into relocatable object modules that can be linked in any combination, according to commands given at load time. Interface to custom F9445 assembly language subroutines is provided. F9445 PASCAL Language Package The Fairchild F9445 PASCAL package is a high-level language suited to the development of microcomputer software because of its strong and logical control structures and its versatility in handling data. Fairchild PASCAL is designed to solve complex problems using such modern language concepts as variable data types, including records, sets, scalars, and others. Interface to custom F9445 assembly language subroutines is provided. F9445 Tests Package The basic diagnostic package for the Fairchild F9445 family of microprocessor products contains seven programs: a memory address test, a memory test, a system exerciser, a memory diagostic, and three F9445 instruction set tests. These disk-based programs enable the user to identify and isolate faults in the CPU, memory, and certain 1/0 subsystems of F9445-based systems. Versions of several of the tests also test the Fairchild System-I (FS-I). PASCAL offers highly structured techniques for organizing and coding programs so that they are easily understood and modified, which allows cost-effective software development. F9445 Instruction Timer F9445 Interactive Multi-User Disk Operating System (1M ~OS) The Fairchild F9445 Instruction Timer (TIMER45) software operates in the F9445-based systems, reporting the time needed to execute each class of CPU instruction. It uses the 1/0 terminal device as the standard to measure the times and report the results. The timer is most useful for detecting the execution speeds in mircroseconds for over 60 representative instructions, to optimize the design of F9445-based systems. It also serves as a diagnostic tool in detecting clock drift. The Fairchild F9445 Interactive Multi-User Disk Operating System (1M ~OS), customized for high-performance microcomputer systems, offers extended file management, timesharing, device-independent inputloutput, system processors such as MACRO assembler and a utility library. F9445 PASCAL, F9445 BASIC, and MICRO FORTRAN compilers are also fully supported. IMOOS is also the principal operating system for the Fairchild System-I (FS-I). 9-32 [!J 1 IINTRODUCTION r;;l2 IORDERING AND PACKAGE ~ INFORMATION 1C!JIF8 MICROCOMPUTER FAMILY 1 0 1 CONTROLLER FAMILY 1~IF6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY ~ I ROM PRODUCTS 1 IITDIRESOURCE AND TRAINING CENTERSI I~ I SALES OFFICES Section 10 Applications I=AIRCHILD A Schlumberger Company II 10·3 Applications 10-4 A Matrix Printer Controller Using The F8 and F3870 Circuits FAIRCHILD A Schlumberger Company The multi-chip F8'" microprocessor and single-chip F3870 MicroMachine'"2 microcomputer have become popular circuits for control applications. Inexpensive and easy to use, their instruction sets and architecture combine to give the modern system designer NMOS LSI power and flexibility. memory size increases. The F8 microprocessor can address up to 64K bytes of program and data storage. Each peripheral controller can easily be implemented as a subroutine within the PSU and, depending upon the desired configuration, the required PSU can be plugged in to provide a modular, flexible system. The architecture of the F8 microprocessor is designed to implement I/O-intensive applications. The memory addressing registers, the 16-bit program counter, and the data counters are located in the Program Storage Unit(PSU). The PSU, as well as the other F8-system peripheral circuits, is driven by the Central Processing Unit (CPU) with micro-instructions communicated over the five control lines (ROMCo-ROMC4) and is synchronized by a Write signal. The unusual partitioning of the CPU and PSU chips frees many pins normally needed for address bussing for use as I/O lines and provides room for a 64-byte scratch pad memory on the CPU chip. No matter how much memory is contained in the system, the number of I/O lines remains fixed at 16; therefore, the number of pins available for useful functions does not diminish as 3851 1K The F3870 MicoMachine2 is a complete 8-bit microcomputer on a single MOS integrated circuit. It features 2048 bytes of ROM, 64 bytes of scratch pad RAM, a programmable binary timer, 32 bits of 110, and has a single +5 V power supply requirement. The F3870 can execute the F8 instruction set and can easily be interfaced with any microprocessor system through the 110 ports by properly defining command, status, and data lines, making it a universal controller. MATRIX PRINTER CONTROLLER A matrix printer controller can be constructed using either the F8 microprocessor (Figure 1) or the F3870 microcom4.7k x 8 PSU· "5 V HOME OATA~ 2N4401 .A-----i BUS~ ~ l ~ ROMC4 REV ~ 201-'""-------1 ROMCO-~ TRIAC CIRCUITS FwD 231-'-''''-------1 L-_---I WRITE TO/FROM CPU +5 V DBDR 4.7k 11 TIP30 :: 24 ~l:: ~ ::~ DUTA} { DUTO ~ OUT B IN B 9667 DARLINGTON DRIVER OUT C 31 IN E OUT E 36 IN F DUTF 37 IN G OUTG 1 '--_---:;;;.....1 'Other PSU. available are the 3856 (2K x 8 with 1/0) and the 3857 (2K x 8 with addre.s bus). Fig. 1 Matrix Printer Controller Using the Fa Microprocessor 10·5 MATRIX PRINTER Il F3870 MICROCOMPUTER I ~' 3 R:::: _--'-::"':-..-1 354' 3 READ STATUS - LiNEffii) TRIAC CIRCUITS 23 FWD ---,P-,,'''"''~123 +5V LOADBYTE---,P-""'""~I ~ DATABUS (1I0PORTO)~ B~T +::S:c~~:::;;C'M",A:::ND"---i 3 4 5 6 7 -I 20 .."R'E'-'-V_ _ _ _ _ _ .. ~'" 24j~ PRINT 2N4401 :: ~ CLEAR BUFFER _ _..:.P.:.:h.....~125 4.7k +5V~ HOME MATRIX PRINTER 2 ..c----~IN~E~F~EE~D~_ _ _ _ __V4,7~k~-----k 1 Ii: J L INAINS{ ~~~~:} ---;r::- {'-= INe- 9667 ~OUTC INO- DA~~I~~~ON I - OUT 0 7 INE- I-OUTE INF- I-OUTF - ING- I-0UTG ,- READ STATUS LOAD BYTE LINE FEED PRINT CLEAR BUFFER ----~ Fig. 2 - - ------~ Matrix Printer Controller Using the F3870 Microcomputer puter (Figure 2). In the F3870-based controller, the following commands are used to perform the control functions: used to hold the gate current off and provide a low-impedance path to ground. This provides good noise immunity to prevent turn-on of either triac by noise. CLEAR BUFFER - stores zeroes in the 40-character print buffer contained within the scratch pad RAM. SOFTWARE DESIGN The matrix printer controller software can easily fit within a 3851 PSU with 1K x 8 bits of ROM and 16 I/O lines. PRINT - causes the contents of the print buffer to be printed. Error status if the head motion is not correct. The timing can be done by software loops without using the timer. This is the easiest technique, but suffers from the drawback that the whole system is tied up during the printing of an entire line. A more sophisticated technique, employed in many real-time control systems, is to make each timing control event a discrete event entered into a table controlled by the real-time monitor. LINE FEED - advances the paper to the next line. LOAD BYTE - takes a byte from the data bus and places it next in the print buffer. Error status if the buffer is full. STATUS - READ places the status on the data bus and clears the status byte. The status is held on the bus until the command is taken away, at which time the port is cleared for reading again. The software has three entry points: The initialization entry point (address H'00B1 '), which fires the reverse triac, turns off the paper-feed solenoid, and returns the print head to the home position. In all command sequences, the F3870 microcomputer presents BUSY until the command has been performed or until status is stable on the data bus. The line-feed entry point (address H'OOCF'), which energizes the paper-feed solenoid for 30 ms and then turns off the solenoid. The current requirements of the matrix printer solenoids are met by a suitable driver, such as the 9667 Darlington driver circuit with seven drivers and built-in back-emf suppression diodes. The 9667 interfaces directly with the F8 microprocessor and F3870 microcomputer ports. The print entry point (address H'0065') , which fires the forward triac, prints the line of characters, fires the reverse triac, and then does a paper feed. The line-feed drive solenoid is implemented as a pnp power transistor (TIP 30), the base drive of which is supplied directly from the I/O port. The HOME phototransistor in the matrix printer supplies base current to a simple 2N4401 npn transistor, which saturates, providing the Home signal to the controller. The forward and reverse triac drives are provided across 100 n resistors from +5 V (Figure 3). A TTL gate is Access to this software is accomplished by loading the registers with the required parameters and executing a "call to subroutine immediate" (PI) instruction to the appropriate entry point. The subroutines to control the matrix printer head motion 10·6, 100 J! 75451 FWD~o-_-", (FROM CONTROLLER) MAC 92-2 Fig. 3 Forward Triac Interface Circuit the status register. A test for minus then detects when Home becomes false: and printing functions are listed in the appendix. These would be used alone in a 3851 PSU with other F8 system circuits or as part of an F3870 universal controller. The control program for the F3870 microcomputer and its subroutines are listed in the appendix. '-1 INPUT & SET STATUS LOOP UNTIL "HOME" IS FALSE However, it must be determined if the forward motion fails for some reason. Therefore, the system does not loop indefinitely but, rather, sets up two counters and waits only 1.5 second, see program segment A. FORWARD MOTION CONTROL The forward triac is fired by setting bit 1 in output port 5: LIS OUTS 5 INS BP 2 5 PRINT SOLENOID CONTROL Once the Home indications goes false, the system fires the print solenoids, waits 650 fJ.s. turns off the solenoids, and waits 700 fJ.s for each of the five columns forming thecharacter, see program segment B. All other bits in port 5 should be cleared so that it is not necessary to OR bit 1 to the port. The Home signal is connected to port 5 bit 7 and active High (+5 = Home). This makes use of the fact that the F8 system input instructions also set Segment A PRDR20 CLR LR LR INS BM O,A 1,A ~RoR30 } 24"" = 256 } 5.9 ms OS BNZ OS BNZ CLR OUTS LIS LR BR 0 PRDR20 1 PRDR20 5 2 1.5 s TURN OFF FWD TRIAC SET ERROR FLAG ERR,A EXIT Segment B PRDR30 LM OUTS LI INC BNZ CLR OUTS LI INC BNZ DS BNZ LOAD FIRING PATTERN 4 186 '-1 9 fJ.S x 70 = 630 fJ.s 4 180 '-1 EOC PRDR30 9 fJ.S x 76 = 684 fJ.S 10·7 } 645 fJ.s "ON TIME" } 698 " "OFF TIME' REVERSE MOTION CONTROL The forward triac is turned off and a 1O-ms delay initiated to allow sufficient time for the triac to stop conduction (one-half cycle is 8.3 ms>. The reverse triac is then fired and the program loops until Home becomes true. Again, there is some error control in the event that something prevents the print head from returning to the home position, see program segment C. is loaded from the table, the address is incremented by one, pointing to the next value in the table. The table is organized so that the first bit pattern is addressed by pointing to the beginning of the table and adding the ASCII character to the data counter five times: DCI ADC ADC ADC ADC ADC LINE FEEO CONTROL The line-feed solenoid can be turned on for only 30 ms; beyond that time, damage may be done to it. Setting bit 7 turns on the solenoid: LI OUTS LIS LR OS BNZ OS BNZ CLR OUTS H'80' 4 10 1,A 0 *-1 *-4 } TABLE ADDRESS POINTS TO THE Nth ENTRY IN A FIVE-BYTEWIDE TABLE Since the first 32 ASCII characters are not used inthis matrix printer, the actual program sllbtracts 32 from the ASCII character before adding it to the data counter five times. TURN ON SOLENOID } 4 BIT PAT 30 ms DELAY CONCLUSION The F8 instruction set has been shown to be ideal for control applications, such as the matrix printer controller described. Of particular note are the input/output instructions that set status, and the table look-up instructions that allow fast access to tables of any length and do not place any constraints on the location of tables in memory. TURN OFF SOLENOID CHARACTER SET TABLE Accessing tables of data with the F8 microprocessor and F3870 MicroMachine 2 microcomputer is easy and efficient. The data counter is loaded using the "load dc immediate" mCIl instruction. The "add accumulator to data counter" (ADC) instruction allows a signed 8-bitvalue contained in the accumulator to be added to the data counter. When the data The F3870 microcomputer has been shown to be ideal for use with any microprocessor system as a universal peripheral controller. This is accomplished by interfacing through the .. input/output ports, which gives the system designer great flexibility in his system configuration. . Segment C PRH010 PRH020 CLR OUTS LIS LR OS BNZ OS BNZ LIS OUTS CLR LR LR INS BP OS BNZ OS BNZ LIS LR LIS LR OS BNZ OS BNZ CLR OUTS TURN OFF FWD TRIAC 5 3 1,A o *-1 1 *-4 1 5 } 10 rns DELAY TURN ON REVERSE TRIAC CLEAR COUNTERS FOR TIMEOUT DELAY O,A 1,A 5 PRH020 ~RD010 ) PRH010 1 ERR,A 3 1,A o *-1 1.5 sTIMEOUT SET ERROR STATUS ) 10 ms DELAY *-4 TURN OFF REVERSE TRIAC 5 10·8 APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OBJECT ADDR LINE 0001 • MATRIX PRINTER CONTROLLER 0002 000:3 • D. R. HOLLINBECK 0004 • FAIRCHILD MOS MICROCOMPUTER 0005 0006 • THE Uti I VERSAL CONTROLLER CONTROL 0007 • PROGRAM IS GIVEN FIRST WITH THE 000:3 • SUBROUTINES AND ,IT PATTERN TABLES 0009 • FOLLOWING 0010 EQU 5 STATUS B'r'TE 0005 0011 :STATUS EQU 4 NUMBER OF BYTES TO PRINT 0004 0012 B'''''TES EGIU .3 000:3 0013 EOC COUNTER FOR END-OF-CHARACTE • • • 001:3 0014 0004 0015 OOFB 0016 0017 001:3 0000 70 0001 EO 0019 0020 0002 Bl 000:3 2:300El OOBl 0021 ODDS 55 0022 0007 54 0023 0024 00,::5 0026 0027 0008 Al 000:3 0028 000'3 :34FE 0048 002'3 OOOE '313C ·., 0030 OOOD 1." o05C (10:31 OOOE '314D 00:32 0010 13 . 002A 00:33 0011 911:3 0034 0013 1 :3 00:3:3 0035 0014 911E 0036 0037 003'3 0(1:3', 0016 45 0040 0017 BO 0041 0018 Al 0042 0019 2204 0043 001B Bl 0044 001C Al 0045 001D 2108 001C 0046 001F '34FC 0047 0021 70 004:3 0022 BO 0049 002:3 55 0050 0051 0052 005:3 0024 Al 0054 0025 2IFB 0055 0027 BI 0008 0056 0028 90DF 0057 0058 0059 0060 002A Al 0061 002B 2204 BUFFER BUS'y' NEUSY • EQU EQU EQU 0'100'-40 START OF BUFFER B'00000100' 'BUSY' BIT £'11111011' NOT 'BUSY' BIT CLR OUTS CLEAR ACCUMULATOR ALLOW READING OF PORTS 1 o AND 1. PRHOME INSURE HEAD IS HOME STATUS-, A CLEAR STATU:S: B'''''TES. A AND BYTE COUNTER DUE PI LR. LR 0 • • READ COMMAND STROBES • INS 1 RDCMD BZ RDCMD BM CLRBUF SL 1 BM PRHH SL 1 BM LINEFD •• • •• 1 Bt1 LDB'''''TE TEST BIT 6 TEST BIT 5 TEST BIT 4 READ STATUS COMMAND LR OUTS INS 01 OUTS INS NI BNZ CLR OUTS LR A,STATUS GET STATUS FROM SCRATCHPAD 0 1 SET 'BUSY' BUS''''' 1 1 B'00001000' WAIT FOR COMMAND .-:3 TO GO AWAY CLEAR STATUS AND PORT 0 STATUS, A CLEAR BUSY STATUS •CLRBSY •• 5:L WAIT FOR COMMAND TEST BIT 7 INS NI .OUTS BR 1 NBUSY ~ RDCMD RESET 'BUSY' WAIT FOR ANOTHER COMMAND LINE FEED COMMAND •LINEFD INS OI 10-9 SET 'BUSY' BUSY II APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) R::;: SOURCE STATEMENT LOC OBJECT ADDR LINE 0062 002n Bl 002E 2:300CF OOCF 006:3 0031 '30F2 0024 0064 0065 0066 0067 0068 OOB 201 :3 0069 0035 C4 0070 0036 2540 003:3 9407 0040 0071 0072 007:3 0074 0075 45 0076 228:3 0077 007:3 0079 0080 00'31 00:32 0083 0084 00:015 0086 00S7 0088 0089 00'90 0091 00'32 00'33 0094 0095 0096 00'37 0ln8 009'3 0100 0101 0102 010:3 0104 0105 0106 0107 0109 0109 011 0 0111 0112 011:3 003A 00:3B 00:3D 003E 55 '30E5 0040 0041 0042 0043 0044 0045 0046 OB AO 5C 44 lF 54 90lID 004:3 0049 004B 004C 004E 004F 0051 0052 005:3 0054 0055 0056 0057 0058 005A OOSC 005D 005F 0060 0063 0024 0024 Al 2204 Bl 2028 54 2018 OB 70 5C OA lF OB 34 94F9 90C9 0052 0024 Al 2204 il '::80065 0065 '30CO 00'::4 • • OUTs: PI BR LFOO CLRBSY -3D DO LINE FEED CLEAR 'BUS')" AND !'JAIT TRANSFER BYTE INTO PRINT BUFFER • LDBYTE LI AS • • • • 1 eI BNZ BUFFER BYTES 0"100" LDBY10 POINT TO NE:':T EMPTY B'iTE IN BUFFER CHECK IF BUFFER FULL ERROR - SET BUFFER FULL STATUS (BIT 3) AND ERROR FLAG (BIT 7). LR 01 •LDBY10 LR BR LR INS LR LR A,STATUS GET HATUS BYTE B"l 0001 000" SET ERROR FLAI3S STATUS,A -:LRBSY IS,A 0 ':;,A A,BYTES LOAD ISAR GET DATA STORE INTO SCRATCHPAD HKREMENT COUNTER I~K • • LR BR -:LEAR PRINT BUFF'ER COMMAt'W • CLRBUF INS OJ OUTS LI CLRB10 • BYTES, A -:::LRBSY • PRINT •PRINT LR LI LR CLR LR LR INC LR D'''''-' BtiZ BR B!.J:SY 1 40 BYTES,A BUFFER I.'>,A ,S,A A,n IS, A BYTES CLRB10 CLRBW BUFFER COMMAtW INS 01 OUTs: PI BR 10·10 1 BU:S..,.. 1 PRDROO CLRBS'r' SET "BUSY' 40 BYTES TO CLEAR '3ET HARTING ADDRES:S AND PUT INTO ISAR CLEAR ACCUMULATOR STORE VIA lSAR INCREMENT lSAR APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OBJECT ADDR LINE 0114 0115 0116 0117 011:3 0119 0120 0121 0122 0123 0124 0065 0:3 0125 0066 11 0126 0067 72 006:3 B5 0127 012:3 0069 10 0129 006A 16 0130 006B 24EO 0131 006!1 11 006E 2AOOEO OOEO 01,32 0133 0071 :3E 0134 0072 aE 0135 0073 8E 0136 0074 :3E 0137 0075 :3E 01303 0076 70 0139 0077 50 0140 oon 51 0141 007'3 75 0142 0071"1 53 0143 DOn 1"15 007C 007E 007F 00:31 00:32 00:34 00:35 00:36 00037 00:3'3 00031"1 OO:3C OO:3D OO:3E 0090 00'31 00'3.3 0094 0035 0097 00'3:3 0091"1 oon 00'3D OO';lF 001"10 001"12 001"13 001"15 001"16 001"17 910F 30 '34FB 31 '34F:3 70 B5 45 22.32 55 9027 16 B4 20BA lF 94FE 70 B4 20B4 lF 94FE 33 94FO 2074 lF '34FE 34 '34C5 70 B5 73 00:3':' 0144 0145 007B 0146 0147 oon 014:3 0149 0150 0151 0152 0153 00B2 0154 0155 0156 0157 015:3 0090 015';.0 0160 0161 0162 016,3 00';.07 0164 0165 OO:3C 0166 0167 0168 00'3F 0169 0170 006"3 0171 0172 017:3 0174 EJECT • •• • • • • • MATRIX PRINTER DRIVER D. R. HOLLINBECK FAIRCHILD MOS MICROCOMPUTER MAIN PRINT ENTRY POINT + PRDROO PRDR10 LR LR ~,P H, DC LIS 2 OUTS LR LM AI LR DCI ADC 5 DC,H -32 H,DC BITPAT SAVE RETURN ADDRESS SAVE DCO FIRE FORWARD TRIAC RESTORE LIST POINTER i~ET NE:X:T CHARACTER TO PRINT SAVE D'::O POINTER TO PRINT TABLE DCO = DCO + '5 • (ACC) ~!lC PRDR20 FlDC FlDC ADC CLR LR LR LIS LR INS (1,1"1 1,A 5 EOC,A S BI'1 !IS: P~DR30 BHZ ?RDR20 D~ 1 PRDR20 ,::LR OUTS LR :5 LR BR LM OUTS Ll IrK BtiZ CLR OUTS +-1 RESET NEEDLE DRIVERS 4 lao BNZ DS BNZ .-1 EOC PRDR30 116 INC BNZ DS BNZ CLR OUTS 5 LE 3 10·11 LOOk AT 'HOME' LED INDICATO A, S:TATIJS B"l 000001 0' STATUS,A PRH005 TURNOFF TRIAC'S AND EXIT GET NEEDLE DRIVER BITS 4 FIRE DRIVERS 1:36 WAIT 650 MICROSECONDS Ll HIC Ll IHITIALIZE DELAY COUNTER INITIALIZE ERROR CODE LOAD NEEDLE FIRING COUNTER o BliZ or PRDR30 THI S: '~ETS THE PROPER ENTRY IH A FIVE BYTE WIDE TABLE. DELAY 700 MICROSECS TEST END-OF-CHARACTER GET NEXT BIT PATTERN DELAY 1350 MICROSECS +-1 BYTES PRDR10 TEST FOR END-OF-LINE GET NEXT BYTE TO PRINT TURN OFF FORI,JARD TRIAC DELAY 10 MILLISECS APPENDIX FORMULATOR FDoS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LoC OBJECT AD DR LINE 00A8 51 00A9 30 OOAA ':l4FE OOAC 31 OOAD 94FB OOAF '3002 OOBl 0:3 00A'3 0177 017:;:: OOA':; 017'3 00B2 01:;:: 0 01 '3 1 01:32 01 :33 01:34 01a5 01:36 01:37 (I 1 ~3:3 00B2 00B3 00B4 00B5 00B6 OOB? OOB',,: OOBA OOI:B OOBD OOBE OOCO OOCl 00C3 00C4 OOC5 71 :E:5 70 01'32 0193 0194 A5 al0B ·30 94FB .31 94F::: 45 22:31 55 7.3 51 00C6 30 00C7 94FE 00(:9 .:::1 OOCA ':l4FB ooce 70 OOCD B5 OOCE OC OOCF OODO OODl 00D2 00D4 00D5 00D6 OOD? OOD::: OODA OODB OODD OODE OODF 01::3'3 0190 01 ':; 1 5'0 51 0:3 70 B5 2080 B4 7A 51 30 94FE 31 94FB 70 1::4 OC lR DS 0175 0176 01 '35 B~C • • • • • • ,.,• DS BtiZ BR PRHDt'lE PRH005 PRH010 LIS: OUTS CLR LF.: LR HE BP DS; Bi''C DS: BNZ IF.: OI PRH020 020 15 020t::. 00C6 0207 02 O~3 00C6 020'3 LF.: LIS: LR DS B~C D.S: Bt·C eLR OUTS 0210 0211 0213 0214 0215 0216 LI': •,., PK Li': eLI': OUTS 021 '9 LI 0220 0221 0222 0223 OUTS: !_IS: LR DS BtiZ D:S: Bt·C CLR OUTS 0225 00D7 022':. 0227 022:3 022'3 SAVE F<:ETURN ADDRESS FIRE RE',/ERSE TRIAC 5 O!'H 1, A 5 '.. IAI T FOR "HOME'- r'RH020 0 i"'RH010 1 F'RH010 rl~ S:TATUS B,"10000001'" HEAD DID t'jOT PETUR~j HOME S:TATUS, A ::: DelAY 1 I) 1"1 I LL I SECS 1, A 0 .-1 1 .-4 TURt'j OFF f':E',/ TRIAC 5 PETUF.:N LltiE FEED ENTRY POINT •LFOO 0217 0218 00D7 0224 f<, F' EtHER HERE TO RETURN PRItH HEAD Hm1E 0202 0212 (I .-1 1 .-4 PRH005 ItH TI ALI ZAT ION E~lTR'r' PO ItiT. ENTER HERE AT THE START OF THE MAIN PRO'3RAM JUST TO Et'jSURE THAT THE PRINT HEAD IS HOt1E. 00(:4 01'36 01n (lOB7 01':;:,,: 019:;0 OOB? 0200 0201 0203 0204 1, A F'K 10-12 f;::,P TUF<:~j OFF TRIAC"S FIRE LI~jE e,.J H"':30 ,.' 4 10 1, A 0 .-1 1 .-4 4 DELA'", .30 FEED MILLISECS TURN OFF LINE FEEI' RETURN FRO~l 8UBfWUTINE APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OBJECT ADDR LINE OOEO OOEl 00E2 00E3 00E4 00 00 00 00 00 00E5 OOE6 00E7 00E8 00E9 00 00 7D 00 00 OOEA OOEB OOEC OOED OOEE 00 60 00 60 00 OOEF OOFO OOFl 00F2 00F3 14 7F 14 7F 14 00F4 00F5 00F6 00F7 00F8 12 2A 7F 2A 24 00F9 OOFA OOFB OOFC OOFD 62 64 08 13 23 OOFE OOFF 0100 0101 0102 36 49 :35 02 05 0103 0104 0105 0106 0107 00 '68 70 00 00 0108 0109 010A 010B 010C 00 It 24 42 00 010D 00 010E 42 010F 24 0230 0231 0232 02:33 0234 0235 0236 0237 0238 0239 0240 0241 0242 0243 0244 0245 0246 0247 0248 0249 0250 0251 0252 0253 0254 0255 0256 0257 0258 0259 0260 0261 0262 0263 0264 0265 0266 0267 0268 02':., 0270 0271 0272 0273 0274 0275 0276 0277 0278 027', 0280 02'31 0282 0283 0284 0285 0286 0287 0288 028', 0290 • • TABLE • In TPAT • • • • • • • • • EJECT OF BIT PATTERNS FOR CHARACTER SET. DC DC DC DC DC H'OO' H'OO' H'09' H'OO' H'OO' DC DC DC DC DC H' 00' H' 00' H'7D' H' 00' H'OO' DC Dr:: DC DC DC 1'1' 00" DC DC DC DC DC H'14' H'7F' H'14' H'7F' H'14' DC DC DC DC DC H'12' DC DC DC DC DC H"'62.-' DC DC DC DC DC H'60' H'OO' H'60' H'OO' H"'2A,o' H'7F' H'2A' H'24' H'64" H'08' H'13" H'23' H' .36' H'49' H':35' W02" H'05' ( ) ••••• • •• (") •• •• ••••••• •• ••••••• •• • • ••• ••••••• ••• • • ($) • •• •• • • • •• • •• (%) •• •• •••• • •• • •• DC DC DC DC DC H' 00" H'68' H'70' H'OO' H'OO' DC DC DC DC DC H'OO' H'lC' H'24' H'42' H'OO' • • • • DC DC DC H'OO' H'42' H'24'- •• •• 10·13 (D •• • ••• ••• (&) (') (0 0) II APPENDIX FORMULATOR FDOS ASSEMBLER (REV R~ 2.0) SOURCE STATEMENT LOC OBJECT ADDR LINE 011 0 lC 0111 00 02'32 02'3:3 0112 0113 0114 0115 0116 08 2A 1C 2A 08 08 OS 7F 0::: 0::: 00 OD OE 00 00 (112:3 0::: 0124 0::: 0125 OB 0126 00 0127 0.3 012:3 (1.3 012'3 00 012A 00 012B 012C 01211 012E 012F 02 04 0:3 10 20 wo:::~' W2A" 0296 02'37 02'3::: DC DC W2A" DC' W' 08'" DC DC DC W'OB~' H'" 0:3'" DC W' DC DC 3E 45 4'::' 51 .3E 0135 00 01:36 21 0137 7F 013:3 01 0139 00 0302 0.30.3 0:304 WO:::'~ H"'7F~' OB~' • 0306 0.307 0.30:=: DC H'" 00'" W' OD'" W' OE'" 0.30'3 DC H'" DC H'" 00'" 0.312 DC 0.313 0314 0:315 0.316 0317 0.31 ::: 031 '31 DC DC H'" 0:::'" W'O:::'" H'" 0:3'" H" oa , ' DC H'" 0:::'" DC DC H'" 00'" H 0.3 ,,' DC W'O:=:-- DC DC H'" 00'" H'" 00'" DC DC W02" H'" 04'" DC H'" 0:3'" H'" 1 0'" 0.310 0320 0.321 0322 0.323 DC • • 0.325 0326 0.327 DC DC O.~:2;:: W20'" • DC DC DC DC DC 0:3.3 I) 03:::1 03.32 0.3.3.3 0:3.34 0.3 35 0:3.36 0.3.37 OO~' • 0324 H~'3E ... H' 45' H'4'3'" H' 51'" W3E" • DC H'" DC 0.3.3:3 DC 0.3.3'31 0:34 (I 0341 DC DC DC DC DC DC DC W45" H'49'" W49'" W31" DC DC DC DC W41' H.-'49'" W49'" 0:342 0343 0.344 0:345 0:34E, 0:347 01:3F 22 0:34::: 0140 41 0141 4'3 0142 49 0349 0'::50 0.351 • H'- 23"- • 10·14 ••• • ••• ••• ••• • • • ••••••• • • (+) •• • ••• (, :> • · • • • (-) ..•• • • • • • ••••• • •• • • • ••••• '.. . (.::. (/) (0) OO~' W21'" H"'7F'" H" 01 ", H'" 00'" 2:3 45 49 49 31 01:3A 01'3B 013C 01:3D Ot:3E W'lC~' • 0:300 0301 0.32'3 0130 0131 0132 0133 0134 Oo~' DC DC 0.311 0121 0:3 0122 0:3 W' DC 0.305 011C 011D 011 E 011F 0120 W'lC' • 02'34 02'35 02'~'3 0117 0118 01 Ll 011 A 011 B DC DC 02'31 H"22'" • • ••••••• (1) • • •• • •• • • • • • • •• • • • •• • •• • • • (2) (.3) APPENDIX F[)RMULATOR FDm: AS.SEMELER (REV 2.0) RS S[)URCE STATEMENT L[)C [)BJECT AD DR LINE 0143 36 0144 0145 0146 0147 0148 OC 14 7F 04 014'3 014A 014B 014C 014D 72 51 51 51 4E 24 0352 0.35:3 0:354 0355 0356 0357 0358 035'3 0360 0361 0362 0363 0364 0.365 014E 014F 0150 0151 0152 1E 0366 2';- 03';:,7 49 4'3 46 036:3 0153 0154 0155 0156 0157 40 47 48 50 60 0158 015'3 015A 015E 015C 36 49 4'3 4'3 0370 0371 0.372 0.3'(·3 0374 0375 0376 037'7 037:3 0379 .36 03'32 .30 03:::4 49 4';' 4A .3C 0.3:35 00 36 03;3:3 0.3'3 (I 00 03;"4 0.3'35 00 6I1 6E 00 00 016C 016D 016E 016F 0170 0:3 14 22 41 00 0171 14 0172 14 017:3 14 0174 14 0175 14 • • 0.336 00 0167 016;3 0169 016A 016E • 0:::.::7 03'31 0.3'32 0393 36 • 0380 0331 03:3'''' 0162 0163 0164 0165 0166 • 03';':;' 03.33 015D 015E 015F 0160 0161 • 03'36 0.3'37 • • 0.3'3:3 • • W.36'· DC DC DC DC W' OC' H'14' H' 24" DC W04" DC , " H'"7" TIC W51" W51' W51" DC DC DC DC DC DC DC DC &..f~·7F'" ~ W4E' W1E' H"'2'3~' W49'" W49" H"'46" DC H"'40'" DC W4?' W48" DC: D,:: DC DC Ie DC DC DC D,:: DC D:: DC DC DC D,:: 0399 0400 0401 0402 0403 0404 0405 0406 0407 040:3 040'3 0410 0411 0412 DC D,::; DC DC DC DC DC DC DC H"'SO'" H···.;:,O··· ri'" 36" W4'3'" j-i" 4 3'- "1"4,"" ri" 3':," H'" 30'" H·'4;" H' 4;';-1' 4W 1"'1", 3C ,,' W 00'" W3';' H" 36'" 0(1" H" 00'" j-i'" H'" 00'" W6D" W6E" W' 00" ••••••• (4) • ••• • •• • •.. • • • • • ••• •••• • .. •• •• • • • • •• • •.. ••• • •• •• •• •• • ..• • • • • • • •• •• (5) (6) (7) (:3) ... • • • • • • • •• •••• ..••• •••• ('3) (:) •• •• • •• ••• (;) W'OO" DC DC DC DC DC ri'" 0,3" W14" H'- 22'" W41" DC DC DC DC DC W14" W14" W14" W14' W14' 10-15 •• •• •• •• • • woo·" • •• • • • • •• •• •• ..• •• (0 (=) II APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OBJECT AD DR LINE 0176 0177 0178 017'3 017A 00 41 22 14 08 017B 017C 017D 017E 017F :30 40 45 48 30 0180 0181 0182 0183 0184 .3E 41 5D 55 3C 0185 0186 0187 0188 0189 3F 48 48 48 3F 0413 0414 0415 0416 0417 041:3 041'3 0420 0421 7F 49 49 4'3 36 018F 0190 0191 01'32 0193 :3E 41 41 41 22 0194 01'35 01% 01'37 0198 41 7F 41 41 019'3 01'3A 01'3B 01'3C 01'3D 7F 4'3 49 49 41 019E 019F 01AO 01Al 01A2 7F 48 48 48 40 3E 0423 0424 0425 0426 0427 0428 042'3 0430 04.31 04.32 0433 0434 0435 0436 043;3 043'3 0440 0441 0442 0443 0444 0445 0446 0447 0448 0449 0450 0451 0452 0453 0454 0455 0456 0457 0458 0459 0460 0461 0462 0463 0464 0465 0466 0467 01A3 01A4 01A5 01A6 01A7 3E 41 41 45 47 • 0422 04:37 018A 018B 018C 018D 018E • 0468 0469 0470 0471 0472 0473 • • • • • • • • • DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC H' 00" H'41' H'22" W14" W30" W40" W45" W48" W.30' H'·.3E'· W41" W5D" W55" H"'3C'" W3F" H"48'" W'48" H''4:3'' H ....3F ... W7F" W4Y W49" H''49 . ' H"'36" W3E'" W41" W41" W41" H'"22'" DC DC DC DC DC W41" H"'7F''W'41 ' W41" H ....-:.t:' ..· -'~ DC DC DC DC DC DC DC DC DC DC 10·16 •• • H'08' DC DC DC DC DC DC DC DC DC DC •• •• W7F" W4'3" H''49 ' H'4'3" H"41 " W7F" H"4:3" W48" H'48" W40' W.3E' W41" W41" W45' W'47' 0) •• • • •• • • •• ••••• • • • ••• • •••• •••• •••••• • • • • • • (?) (.jJ) (A) •••••• ••••••• • • • • • • • • • (B) •• •• ••••• • • • • • • • ••••••• • • • • • • • (C) (D) ••••• ••••••• • • • • • • • • • • • (E) ••••••• • • • • • • (F) • ••••• • • • • • •• • ••• (6) APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OBJECT AD DR LINE 01A8 7F 01A9 08 01AA 08 01AB 08 01AC 7F 01AD 01AE OlAF 01BO 01Bl 00 41 7F 41 00 01B2 01B3 01B4 01B5 01B6 02 01 01 01 7E 01B7 01B8 01B9 01BA 01BB 7F 0:3 14 22 4i OlBC 01BD 01BE 01BF 01CO 7F 01 01 01 01 01el 01C2 01C3 01C4 01C5 7F 20 01C6 01C7 01e:3 01C'3 OleA 7F 10 0:3 04 7F Hl 20 7F 01CB :3E 01ce 01CD 01CE 01CF 41 41 41 ,3E 01DO 01D1 01D2 01D3 01D4 7F 4:3 4:3 4:3 :30 01D5 01DO 01D7 01D8 01D9 3E 41 45 42 3D 01DA 7F 0474 0475 0476 0477 0478 047'3 0480 0481 04:32 0483 0484 04:35 04:36 DC • • 0487 0488 04:39 04'30 0491 04'32 • 04'3) 0494 049~, 0496 0497 04'3:3 049'3 0500 0501 0502 0503 0504 0505 0506 0507 050:3 0509 0510 0511 0512 051.3 0514 0515 0516 0517 051:3 0519 0520 0521 0522 0523 0524 0525 0526 0527 052:3 052'3 0530 0531 0532 0533 05:34 • • • • • • • DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC 10·17 W'7F' H" 08' H' 08" H'08' W'7F' H'OO' H:::41 ' H"'7F'" H'41' WOO" ..._.. • • • (H) ••••••••• • • (I) ••••••• • W02" W01" H'Ol' H' 01' W7E" W7F' WO:3'" W'14' W22" W41" W7F" H'Ol' H'Ol' • •• (J) •• • • • • (0 •••••• ••••••• • '••. ••••••• W01" • H" 01' W7F' W20'" H'l:3'" W20" W7F'" H"7F' WI0' W' 0::;' W04" W7F" W'3E' H'41' W'41 ' W41" W:3E" W7F" W4:3' W'4:3' W'4:3' W'30' H" 3E' ••••••• • •• • ••••••• ••••••• • • • • • • • ...- • (0) ••••••• •• •• (P) • • •• ••••• H'7F' ••••••• W'42' II ••••••• ••••• H'3D' H'45' (M) (N) • • • • •• • • •••• • W41" (U (G!.> APPENDIX FORMULATOR FDOS ASSEMBLER (REV 2.0) RS SOURCE STATEMENT LOC OiJJECT AD DR LINE 01DE; 48 01DC 4C 01DD 4A O.lDE .31 01DF OlEO 01El 011::2 01E3 32 4'3 4'3 4'3 01E4 01E5 01E6 01E7 oiE8 40 40 7F 40 40 OlE.':;' OlEA 01EB 01Ee 01ED 7E 01 01 01 7E 01EE 01EF 01FO 01Fl 01F2 70 2~ oe 03 OC 70 01F3 01i=4 01F5 01F6 01F7 7F 02 oe 02 71=' 01F8 01F9 01FA OlFB 01FC 63 14 08 14 63 01FD 01FE 01FF 0200 0201 60 10 OF 10 60 0202 0203 0204 02'05 0206 43 45 4'3 51 61 053'5 0536 05:37 05.3:01 053':;' 0540 0541 0542 0543 0544 0545 0546 0547 0548 054':;' 0550 0551 0552 05'53 05'54 0555 0556 0'557 0558 0559 0560 0561 0'562 0563 0564 0565 0566 0567 056:01 056'3 0570 0'571 0572 0573 0574 0575 0576 0'571 0'57:3 05'7'3 05:010 0581 0582 0'5:013 0584 0585 0586 0587 058:3 • • • • • • • • &c DC DC DC H'48' H'4C' H'4A' H'31' DC DC DC DC DC H"'32'" DC DC DC DC DC H'40' H'40" H'7F' H'40" H'40' DC DC DC DC DC H'7E' W'Ol' W01' H' 01' r!'7E' DC DC D':; DC DC DC DC DC DC DC H'4'!l' H"4'3 " . H~·26'" H"70' oe' H'03" H'" oe·' H'70" i-l' H'7F' H..'02'" W' oe' H"'02'" H"7F" H'63" H'14' W' 08' H'14" • •• •• • •• • • • • • • • • • • • •• • • ••••••• • •••••• •••••• ••• •• DC DC DC DC DC H'60' W10" W' OF~ W'10' H'60' •• DC DC H'43' W 45' H' 4'3' H"51 ' END ERRS 10·18 W61 " • • • •• •• •• ••• •••••••• • •• • ••••••• •• •• W63' DC DC (R) (S) (T) • DC DC DC DC DC !Ie • H'4~iI" •• ••• •• • •• (U) ('.') (0.1) (..0 •• • •••• • ('0 • •• • •• • • • •• • •• • (2) •• Microprocessor-Controlled Phase-Locked Loop Tuning System , I=AIRCHILD A Schlumberger Company The TV channel changer, the volume control adjustment and other controls with knob and dial-type readouts are taken for granted today, and simplified so that even a child can operate them. The present forms are the result of many years of evolution, from "tweeking of the Cat's Whisker" in the early days of crystal radio, to the two-handed operation required for separate tuning of radio frequency and detector stages in rf receivers, or tuning with sliding inductor coils. These all have evolved into the systems used today and have undergone considerable "human engineering." With the event of fully electronic controlled systems with calculator-type key boards, touch panels, remote control, etc., a similar evolution is taking pla:ce in tuning and display systems. tuning and time readout. Processing and controlling these various functions separately, using hardware, is inefficient, inflexible and costly. The obvious solution is to incorporate a central p'rocessing unit within the receiver to process the human interface controls, determine the function to be performed, and establish the manner in which the function isaccomplished (Figure 3), Since different manufacturers have different receiver requirements, the central processing unit will differ from manufacturer to manufacturer, or even model to model. The F3870 low-cost one-Chip microprocessor with 2K bytes of on-board ROM, a 54-bit scratchpad RAM, and 32 bits (four 8-bit bytes) of TTL-compatible input/output is an ideal candidate for a central processor. The F3870 requires no peripheral devices except a crystal and power supplies. Using this processor, the type of control operation is programmed into the ROM at the factory. With efficient software programming, two or three programs could be stored in the ROM so that the receiver manufacturer may offer the same chassis with differentfeatures and operations. The various controls and displays for TV or AM/FM receiver tuning, volume, brightness, etc., require either director indirect human interface (Figures 1 and 2), They can take many forms, from the old familiar knob system with dial readout that is controlled by a switch, potentiometer or variable capacitor, to a remote control keyboard system or touch-control panel. The latter requires electronic control of the major functions such as INPUTS INPUTS ON/OFF TUNING BAND/AM/FM VOLUME BALANCE BASS TREBLE PHONO TAPE FUNCTIONS PROGRAMMING/TIME FREQ' TIME SET TIME SET ALARM/ALARM DISPLAY FUNCTION ON/OFF VOLUME CHANNEL COLOR TINT CONTRAST BRIGHTNESS SET TIME PROGRAM TIME AND CHANNEL GAMESITELETEXT, ETC. READOUTS FOR CHANNELS/TIME, ETC. Fig. 1 Television INPUTS ON/OFF VOLUME TUNING ETC - DODD DODD DODD DODD ·.--t- ITII]I.. o0 0 0 Fig. 2 Auto Radlo/HI-FI ~ ______________ Fig. 3 Receiver wllh Central Processor 10-19 ~ ____________--J ETC DISPLAY FUNCTION FREQUENCY /TIME AM/FM TAPE FUNCTIONS the line, may be built with almost every imaginable feature by simply adding the appropriate modular circuit onto the bus (Figures 5 and 6). Other circuits will be available shortly-an Schannel 6-bit D/A converter, a time clock, and an on-screen character generator. Each modular chip will have built-in identity code, which is something like a chip select but operates on data on the data bus. The identity code word is four bits; therefore, there are 16 possible combinations, but only 15 are available for use since one is reserved for when no chip is addressed. The microprocessor may also perform additional functions such as DJA conversion for actually controlling the circuits, tuning, volume, brightness, color, etc. It could be used asa time clock capable of being programmed to switch on the receiver at a given time and channel. The microprocessor may also act as a receiver section of a remote control system, ultrasonic or IR, to decode the signals for a particular function. However, specialized chips are now available that perform the dedicated functions - PLL timing, DJA conversion, etc. - more efficiently than microprocessors, and work well under microprocessor command. To address a particular chip on the data bus, the correct IDENT code is placed on the data bus and an IDENT clock on the control bus. The chip selected is initialized and reset, ready to accept data from the data bus. The OAT A clock on the control bus clocks the information into the selected chip. The number STANDARDIZED BUS SYSTEMS Fairchild adopted a standardized bus system (Figure 4) for microprocessor-controlled AM/FM and TV receivers. Using this system, AM/FM and TV models, from low end to the top of MICROPROCESSOR ACKNOWLEOGE Fig. 4 Standardized Bus System KEYBOARD DODD DDDD 0000 DDDD ON SCREEN READOUT OF TIME AND CHANNEL DATA BUS CONTROL BUS FCM 1020 TIME CLDCK CHIP Fig. 5 Mlcroprocas.or-Cont,olled TV with PLL Tuning 10·20 3870 DEDICATED MICAOCONTROLLER 0000 0000 0000 0000 FCM 6020 TIME CLOCK CHIP 7-SEGMENT DECODER DRIVER KEYBOARD Fig. 6 Microprocessor-Controlled AM/FM Radio with PLL Tuning The output frequency of the vce (a varactor local oscillator) is divided down by the divide-by-n counter and fed into the frequency/phase detector where the frequency and phase are compared to a reference frequency. The frequency/phase detector output circuit has three modes~open circuit, or supplying a series of pump-up or pump-down pulse charges to the integrator/amplifier. The output of the integrator/amplifier supplies dc feedback control voltage to the VCO. When~ the loop is locked and operating at the desired frequency, the two frequencies fed into the frequency/phase detector are the same and of essentially the same phase. of words required to read a chip depends upon the particular chip function, and a DATA clock must be generated for each word. To disable the chip from the bus, the procedure is reversed. The wrong IDENT code is put in the data bus with an IDENT clock on the control bus. PLL TUNING It has long been realized that the ultimate tuning system is the phase-locked loop. However, it has not successfully penetrated the consumer market, until recently, due to its stringent requirements-large complex logic, ability to perform at high frequencies, system partitioning, and specific system.configuration. Simple PLL TV tuning systems accurately tuned to the FCC channel assignments; however, local problems such as antenna mismatch, IF misalignment, cable TV problems, etc:, were often present and required fine tuning or, more accurately, detuning of the PLL system. Therefore, it was imperative to add the fine-tuning capability, inherent in the old turret tuners, to the PLL TV tuning system. This complicated the system and also required some kind of non-volatile memory for storing the fine-tuning information for each channel. Under these conditions, the frequency/phase comparator supplies only sufficient charge to maintain loop lock. When the loop is not locked. the two frequencies at the input to the frequency/phase comparator differ. The frequency/phase d e - I I I tector supplies a charge of sufficient amplitude an. d direction to I the integrator/amplifier to generate a voltage for driving the vce to a frequency that will cause the loop to lock. Therefore, the output frequency of the PLL can be ~written as ioilows: Another problem in PLL TV tuning was how to control the TV receiver. especially in the method of entry from the calculatorboard -whether one or two keys should be used, or an entry button, and whether the channel display should indicate which key has been depressed or indicate the channel on the screen. fveo = n x fREF where n is always a whole integer. Changing the value of the divide-by-n counter changes the frequency. For example. a tuning system for tuning in 25 kHz increments requires a reference frequency of 25 kHz. Now, with the addition of the microprocessor as a central control unit, the problems of the PLL TV tuning can be simplified and the exact application can be determined by the TV or AM/FM manufacturer rather than by the semiconductor manufacturer. Unfortunately, to build a programmable divide-by-n counter for a PLL system that operates at the local oscillator frequencies of FM and TV receivers is impractical. Therefore, an ECL highspeed prescaler is inserted between the vce and the programmable divide-by-n counter to reduce the counterfrequency. A simple fixed prescaler (Figure 8) places too many compromises on the PLL designer-long loop lock-up times or BASIC PLL SYSTEMS A better, more descriptive name for the PLL would be "frequency, phase-locked loop" (Figure 7) because. for the loop to lock, the frequency must be adjusted first. then the phase. 10-21 10 Fig. 7 Basic PLL CHANNEL SELECTION to ~ircuil CHANNEL SELECTION Fig. 8 High-Frequency Loop Using Fixed Prescaler '"'I-o----LENGTH: 101 INCHES,----...,.~I G::J G::J ft NINE 10·INCH BRICKS ,.. ~ T ONE ,,·INCH BRICK LENGTH:'10S INCHES CJ eiP CJ CJ eft!-=:J "I CJ ~----~~------# ~'--------------~ FIVE 10·INCH BRICKS FIVE "·INCH BRICKS Fig. 9 Brick Analogy The operation of the system for a total divide-by-n cycle is as follows. When the program counter reaches terminal count, it parallel loads both itself and the swallow counter with the desired divide ratios. The Terminal-Count output of the swallow, counter, which is also the prescaler Mode-Control input, then goes HIGH and both counters begin to count. Since the swallow counter is smaller, it reaches terminal count first and stops, causing the Mode-Control input to the prescaler to go LOW, changing the prescaler modulus. The program counter continues until reaching terminal count and the divide-by-n sequence is repeated. Therefore the program counter performs the coarse, or rough, tuning while the swallow counter handles the fine tuning. restrictions on the timing increments-that generally result in too many loop or receiver problems. A superior approach is to use a dual-modulus prescaler, i.e., an ECL divider with two different divide ratios usually closely related, in a technique called "pulse swallowing." Pulse Swallowing Pulse swallowing is a technique that combines the talent of a very fast, but dumb, ECL prescaler with that of a low speed, but very smart, counter. The best way to explain it is to divert, forthe moment, from the field of electronics and enter the world of masonry. Suppose a universal brick were required for building walls of any length, within one inch, without breaking the brick. One way to do this would be to make one brick 10 inches long and another 11 inches. Using combinations of these two sizes of bricks, walls of any length (over 100") may be builHFigure 9). THE FAIRCHILD MICROPROCESSOR CONTROLLED PLL TUNING SYSTEM The Fairchild FEX2500 PLL circuit is made using CMOS metalgate technology and is packaged in a 28-pin DIP, either plastic or ceramic. The primary features are: Back to electronics-the dual-modulus prescaler(Figure 10) is similar to the two different brick lengths. By controlling the dual-modulus prescaler appropriately, the incoming clock frequency pulses can be counted in two different "block lengths" (Figure 11l. For high-frequency applications, pulse swallowing combines the advantages of-both the straightforward method (Figure 7) and the fixed modulus prescaler (Figure 8). It allows the highest possible reference frequency fREF and vastly reduces the speed requirement of a programmable divide-by-n counter. The dual-modulus prescaler, when operating, appears to swallow pulses when changing between the two divide ratios of the prescaler-thus the name, "pulse swallowing." • Microprocessor addressable • Data-holding registers independent of input data, once addressed • Operates to 4 MHz • Operates to 1 GHz with appropriate prescaler • Fine tuning capability-1 kHz AM band, 25 kHz FMband, 62.5 kHz TV • Complete digital portion of PLL tuning system • On-board oscillator circuit for reference frequency • 4 MHz, 2 MHz and 1 MHz outputs that may be used for clock input to microprocessor or other circuits • Unique data-bus chip select system • Choice of 1 kHz, 5 kHz, 7.8125 kHz or 25 kHz reference frequency • Phase comparator incorporates patented anti-backlash circuit to reduce random FM modulation of the Veo • Out-of-Iock output indicates out-of-Iock condition of loop • Dual ratio program and swallow counters for extended loop frequency range To keep track of how many times the prescaler operates in one of its two modes (usually the higher), an extra counter, called a swallow counter, is added to the system. The swallow counter has only a small total divide ratio compared to that of the program counter. It differs from the program counter in that its Terminal-Count output is connected back to a Stop input and operates like a one-shot. This is called a dead-ended counter because it stops after reaching terminal count. 10-22 r--------------- TOTAL DIVIDE·BV·N COUNTER -----------------l r ____ ~I?A~II~~~~:-------:~U~~~II~:~"~~-, r-0 t{Z PE PE tosc~ DUAL MODULUS PRESCALER +UIL I I t-~-:--+lCP ~~~~';.~~ TC ,.- - CP ~~~~~~: .;-..L.'--:R~F. FRED.) TCJ-..... STOP t ! MODULUS I I I I L ________________________ !~~~!~~ CONTROL (1) lose = N x Iref pc "PROGRAM COUNTER RATIO (2) N = Sw (U-L) + LPc (3) or N = USw + L(Pc-Sw) SW "SWALLOW COUNTER RATIO U "UPPER PRESCALER DIVIDE RATIO L "LOWER PRESCALER DIVIDE RATIO N = TOTAL DIVIDE RATIO LIMITS PC >SW Fig. 10 Frequency Dlvlde-by-N Counter Using a Dual Modulus Prescaler r---- REFERENCE FREQ PERIOD ~ ~ ONE COMPLETE DIVIOE·BV·N CYCLE ~ DIVIDE·BV·N COUNTER OUTPUT WAVEFORM ...., 1 ~ I I I I I ______~I U PARALLEL LOAD i-I- - - - I f ~ Ur----PRESCALER OPERATES IN LOWER DIVIDE RATIO r_---,.---""";,_~ PRESCALER MODE CONTROL WAVEFORM ~ F---I. - - - - ,1________________________......1 (SWALLOW COUNTER OUTPUT) ~ I-- ---------- L. PRESCALER OPERATES IN HIGHER DIVIDE RATIO--' Fig. 11 Dillerent "Block Lengths" The FEX2500 contains all the essential digital components of an advanced Pll tuning system, requiring only an external tuner, integrator and a crystal to complete the entire loop. Programs and Swallow Counters Clock Inputs The Clock input for the program and swallow counters can be selected for either a differential input or a single-ended input by using an Input Select pin (IS)' For TV or FM radio applications, the differential input mode is generally used. The Pll differential inputs are connected directly to the differential outputs of an ECl prescaler. This considerably reduces the amount of radiated digital-interference noise. Single-ended mode is intendedfor AM radio applications without the use of a prescaler. In AM/FM radio, the local oscillator is connected to the singleended input while the differential inputs are connected to the ECl prescaler that derives input from the FM local oscillator. loop change from AM to FM is accomplished with the IS control. The maximum frequency on both inputs is 4 MHz. The Pll loop operates from 100 kHz to 4 MHz directly, and to 1 GHz with the addition of an ECl prescaler. The system has fine tuning increments of 1 kHz for the AM band, 25 kHz for the FM band, and 62.5 kHz for TV and can be set lower with loop compromises. The user has a choice of 1 kHz,5 kHz, 7.8125 kHz or 25 kHz reference frequencies when used with a 4 MHz reference crystal. Once addressed to the desired tuning frequency, the Pll circuit can be operated independently of the microprocessor, since the Pll contains the necessary holding registers for data. To accommodate the 4 MHz input operating frequency and low propagation delays, it uses two power supplies, +12 V and 5 V. The +5 V supply is required to make the input and output circuits compatible with other +5 V logic circuits. Figure 12 shows the complete block diagram containing both the program counter and swallow counter as well as a phase comparator, crystal oscillator, reference frequency divider, four 4-bit registers to store tuning information, plus additional circuits. Counter Configurations The counter has a total bit length of 16 bits, is sub-divided into two sections-a program counter and a swallow counter, and has two selectable configurations: 13 bits program/3 bits swallow or 11 bits program/5 bits swallow. Counter-configuration control determines which bit lengths are selected according to 10·23 III • ID/ENABLE IDE NT CLOCK DATA CLOCK DATA BUS IN 4 BITS DIFF IN + DIFf IN- a N SINGLE ENDED INPUT ... J 1. INPUT SELECT COUNTER CONFIGURATION COMPARATOR OUTPUT DISABLE FREQ/PHASE COMPARATOR REF SELECT 0 OUTPUT ~ ro.,~ "'~, 1 OSC IN MC MODE CONTROL .. CO OL OUT-OF-LOCK -- OSC OUT Fl 1 MHz 2 MHz 4 MHz Fig. 12 FEX2500 PLL Block Diagram F2 F4 an output disable circuit. The actual frequency/phase comparator is the ,standard digital type that locks onto the negative edges of the two waveforms, one from the program counter and the other from the reference-frequency divider (Figure 14), It can only lock onto the correct frequency with no output of the comparator at multiples of either of the two frequencies. different divide ratios required in various applications. The maximum possible divide ratios are: MODE PROGRAM SWALLOW = 8192 13/3 213 11/5 211 = 2048 23 =8 25 = 32 Anti-Backlash Circuit The anti-backlash circuit eliminates the dead-zone problems due to propagation delays in other digital frequency/phase comparators. A narrow pulse (~ 200 nsl is injected into the pump-down circuit to cause a loop error. The loop responds by making' another pulse of equal and opposite magnitude to cancel out the error (Figure 15), Both pulses are arranged to be closely related in time so they can be easily filtered out by small filter capacitors. Therefore the net charge fed to the integrator by these pulses is zero. However, the injection of these pulses causes a slight phase error that operates the frequency-phase comparator outside the dead zone. The addition of this circuit considerably enhances the spectral output of the veo, eliminating random low-frequency modulation caused by phasecomparator "hunting" in standard comparators. Both counters are down types; therefore, the divide ratio is the same as that of the binary load value. The load values for frequency or channel allocation are obtained from the microprocessor. Binary counters, rather than decimal counters, simplify chip design and minimize software programming problems on the microprocessor. For low-frequency operation below 4 MHz, the swallow counter is not used and it is immaterial what data values are loaded into it. Figure 13 shows the data loading format. Frequency/Phase Comparator The frequency/phase comparator has a number of unique features, an anti-backlash circuit, an out-of-Iock detector and r~-- HEXADECIMAL INPUT DATA REGISTERS WXVZ __________ ..;A ____________ SWALLOW + PROGRAM PROGRAM PROGRAM ~ PROGRAM ~~~~ SWALLOW COUNTER PROGRAM COUNTER COUNTER CONFIGURATION 3 BITS SWALLOW 13 BITS PROGRAM I CC = PIN 20 "HIGH" ~ I r~-------------------~'-------------------, ++R:W MSB I I ++ER> I I ++R> I I ++ER> I LSB lSB Mse ++++ ++++ ++++ ++++ HEXADECIMAL INPUT DATA REGISTERS WXYZ r~--------------------~'------------------~, SWALLOW SWALLOW + PROGRAM PROGRAM PROGRAM ~~~~ SWALLOW COUNTER 5 BITS SWALLOW 11 BITS PROGRAM I CC = PIN 20 "LOW" PROGRAM COUNTER ~ COUNTER CONFIGURATION I ++ER:W II MSB ++ER:X I RfGI+ER:V ++++ ++++ ++++ Fig, 13 Bit Coordination Between Input Registers and Loop Counters 10-25 RiGI~TER:Z LSB LSB MSe ++++ ON FREQUENCY AND IN PHASE LOW IN FREQUENCY HIGH IN FREQUENCY DIVIDE-BY-N COUNTER OUTPUT REFERENCE FREQUENCY PUMP UP PUMP DOWN + ~ +--....::.---......---;.-~-; HIGH IMPEDANCE (OPEN CIRCUIT) Fig. 14 I_ REF FREQ PERIOD. Output Waveforms from Frequency/Phase Comparator -I VARIABLE ~ ~INJECTED~ OL TIMING PULSE ERROR PULSE Fig.15 DIGITAL 800 n9 SAMPLER REFERENCE Output of Frequency/Phase Detector with Anti-Backlash Circuit Fig. 16 Out-of-lock Circuit Out-o'-Lock Detector (Figure 16) This circuit is used to detect an out-of-Iock condition, due to either a malfunction or a channel change. The indicator is also useful during initial loop set-up and test. It can also be used to mute the audio during channel changes, or it can be connected to an LED display for indication of loop malfunction. Reference Frequency Divider and Oscillator Circuits The oscillator circuit consists of two high-gain CMOS inverter circuits in series plus the external components-crystal, trimmer capacitor, resistor-connected between the input and output of the inverters. In operation, a window signal is decoded off the referencefrequency divider chain (Figure 17>. When the loop is locked, the negative edge of the output waveform from the divide-by-n counter rests in the middle of the window. If it strays outside the window for two period reference cycles, a latch is set and an out-of-Iock condition is indicated. The reference frequency divider circuit is a straightforward counter with various outputs-4 MHz, 2 MHz and 1 MHz -which may be used for the microprocessor clock. The reference frequencies of 1 kHz, 5 kHz, 7.8125 kHz and 25 kHz are tapped off the divider chain through a 4-input multiplexer, that selects the reference frequency. Output Circuit The output circuit is designed to provide three output modes (Figure 18) -current sourcing (pump-up), current sinking (pump-down) or high impedance (open circuit). Chip-Identity Circuit When the IDENT code (PLL Chip 0110) is present on the Data Bus input and an IDENT clock is generated, the scan counter is initialized. Data can now be entered into the first register W via the DATA clock. which then clocks the scan counter so the second register X is ready to accept data. This is repeated until the remainder of the registers are loaded. Data can be repeatedly loaded into the registers using the DATA clock, but care must be exercised to keep track of which register is receiving data. To disable the Data Bus input to the PLL chip, a wrong IDENT code is put into the data bus and an IDENTclock generated. The IDENT code circuit may be disabled by leaving the 10 Enable input HIGH. When the loop is locked, the output circuit is in the highimpedance state, except during the positive and negative antibacklash pulse injection mentioned previously. Output Disable This control can be used to hold the loop on frequency while new frequency information is being loaded into the PLL registers. When the output is disabled, the output from the frequency phase comparator is in the high impedance state. When a frequency change is initiated, new data is fed, relatively slowly, into the four registers, WXYZ. During the loading of each register, the lool? responds to the new data causing erroneous loop responses, unless the comparator output is disabled. Data Input Terminal Figure 13 shows the input data format for registers W X Y Z in both configurations of the counters. The generation of the input data for operating a PLL at given frequencies is worked out from the equation in Figure 10. The following example shows the procedure for establishing the When this output is disabled, the integrator tends to remember the last charge level, thus keeping the loop on or about frequency. 10-26 -OUT-OF-LOCK-r---IN-LOCK----r--0UT-OF-LOCK- DECODED FROM REFERENCE OIVIDER OUT-OF-LOCK WINDOW :":'~~:-:':"~~~_ _ _....., DIVIDE-BY-N COUNTER Fig. 17 Out-ol-Lock Timing Diagram +5V FROM +N COUNTER FREQ/ PHASE COM OUTPUT DISABLE REF FREQUENCY OIVIDER Flg.18 INPUT Frequency/Pha.. Comparator Output .:----1 + 31/32 : OUTPUT '-----_-c MODE CONTROL llcn 200 MHz ECL PRESCALER INPUT .:----IL.__ H +_._....... + 31/32 ...._ _ ~:. OUTPUT ' - - - - - -..... MODE CONTROL Fig. 19 Pre_lers The integer part of the number is the PC load divide ratio values and will help clarify the operation of the pulse swallowing system. :. PC = 127 Receiver -FM 88.1 to 107.9 MHz IF 10.7 MHz b. Find SW divide ratio (Fine Tuning) Take the integer number from above and multiply by prescaler lower ratio: PLL Setup for 4 MHz Crystal Reference 25 kHz Reference Frequency 1. LOW Frequency = Receiver + IF = 88.1 + 10.7 =98.8 MHz 127 x 31 = 3939 Subtract this number from Divide-by-n: 3952 - 3937 = 15 2. Total Divide-by-n = LOW Frequency + Reference = 98.8 + 25 kHz = 3952 :. SW = 15 This is the number of times the prescaler operates in the divide-by-32 mode. It is not necessary to work out subsequent frequencies in the range, but merely increment the values by the required amount. These numbers then have to be translated first into binary, then into hexadecimal data to fit the data loading format shown in Figure 13. 3. To find PLL loading data: Program Counter = PC Swallow Counter';' SW a. Find PC divide ratio (Coarse Tuni.ng) PRESCALERS (Figure 19) Two prescalers have been specially designed to operate with the FEX2500 PLL chip: 11 C79 divide-by 31/32 (200 MHz) and "Divide-by-n" divided by prescaler lower ratio 3952 + 31 = 127.48387 10-27 • NOTE: FDA TV USE A HEADER AND PLACE 11ee2 RESCALEA AT THE TUNER. 2481256 ~ +SV I OPTIONAL JUMPERS tOO!! '.. - at - BAHQ$WITCH 17, Qa- ~ 33DO \17 OPTIONAL BANDSWITCH .,. ~ PROCESSOR ~D' POWER ON RESET 'N'''' AM/FM "'''RACTOR f"·1k ", ~ 1III I FEX2730 NON-VOLATILE MEMORY TUNER ' -,. If- ~ ,>1 r ~ } d PRESCALEA 1te79 -31/32 , , " AM/FM III".NOSWITCH "" " ,,,,-" .,. d2V J ,f" " ~ '~CPD " "ii ,." , ,, CPI D, S D, • D, Do ,." MICROPROCESSORI FEX2500 EMULATOR PC< E ...." ,,-" ~ o '" Ao Al A~ A3 EL BCD TO 1 SEGMENT DECODER/DRIVER Ao A1 A2 A3 El BCD TO 7 SEGMENT DECOOER/DRIVER :I"17,l , , R '-"---- r-,,- 1 1 , , LINES ! ! I L__ '~~~R!:"O~ __ J I L ______ .J LINES ,-----.. I I ,I : ] I, ,------- ,,,.,------,.-,------,,- (Xl f"" " .,} ~ 11 ." -- ------------- - - --- ------ ------ -------..., SPARE 40·PIN SOCKET (ALL PINS I-I I-I I-I I-I I-I I I I I I I IN PARALLEL WITH MICROPROCESSOR) f. :=IN':- D~ L_________________B~N~~!.:~~I~~~ Fig. 20 Advanced AM/FM Radio Application -,. _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...J 11 C82 divide-by 248/25 (1 GHz)' Other prescalers are available with a decrease in digital noise performance: 11 C90 divide-by 10/11 (600 MHz) and 11C91 divide-by 5/6 (600 MHz)' One exciting area for a PLL tuning system is a home AM/FM radio with short-wave bands. Low-cost short-wave receivers to date are generally difficult to tune but with the precise tuning of a PLL tuning circuit, this would change. The maximum operating frequency of PLL system is limited by the 4 MHz maximum frequency of PLL FEX2500. If the radio had memory storage for a number of short-wave stations, people living in different lands could program in. a station from their own country. Most foreign countries radiate the same program material on a number of frequencies. Due to periodic sunspot activity, some frequencies are better than others; thus it is necessary to store a number of short-wave frequencies. Also, because of the ease of tuning, the short-wave broadcast bands could become acceptable for normal broadcast frequencies. Example using 11C90 divide-by 10/11: = 4 MHz x 10 = 40 MHz AM/FM APPLICATIONS Figure 20 shows an advanced AM/FM radio with a single chip F3870 microprocessor and keyboard with an LED display readout. It has manual or automatic search tuning and storage for a number of stations. It can tune on AM to 1 kHz increments and FM to 25 kHz. HISTORICAL NOTE ON PULSE SWALLOWING The pulse swallowing technique makes the whole PLL tuning system commercially feasible and acceptable in performance. It was the idea, or invention, of John Nichols in about 1968-69 time period when he worked for Fairchild. The work was dorie initially for 360-channel aircraft radio/transmitters. It was not until many years later that his brilliant idea became widely known. With the integrator circuit, the undesirable reference frequency modulation of the VCO frequency is: FM = better than 50 dB at 25 kHz AM = better than 45 dB at 1 kHz 10-29 A Schlumberger Company Microprocessor-Based Solar Controller Mlcroprocessor·Based Solar Controller Controller Operation Energy is being consumed today in greater quantities than ever; at the same time, yesterday's seemingly unlimited resources are now seen to be quite finite. As a result, energy conservation has assumed a new importance, and the search for alternative energy sources has begun in earnest. One of the more promising possibilities is harnes· sing the sun as a direct source of heat. The microprocessor is programmed to solve a set of logicl arithmetic equations. These equations are contained in the EPROM program storage, with the associated constants being held in the 1K RAM. The keyboard can be used to change a number of the equation constants, permitting system changes to be made without hardware modification. FAIRCHILD The solar heating systems now being installed in homes, apartment complexes, and businesses contain heat collecting and storing devices from which resources are drawn during non· and low·sunlight periods. Although there are many types of such systems, the most common circulate water or some other liquid through solar heating panels, or collectors, during the day and store the heated fluid in tanks. When required, this fluid is pumped through radiators or radiant coils to provide area heating. To maintain comfort and make the best use of the available energy, the user must continuously monitor the temperature of every area to be heated, as well as the temperatures of the collectors and the storage tanks. Valves must then be opened or closed and pumps turned on or off to maintain the desired relation· ship among the system components. A computerized energy management system, or solar controller, can perform all of the monitor and control functions with optimum efficiency. A microprocessor-based solar controller designed by Fairchild for Rho Sigma, Inc., a major manufacturer of solar controls, is specifically intended to accept the low voltages produced by thermistor temperature sensors, process and display the data, and provide outputs for relay and switch opening and closing. The solar controller contains a singleboard F8™ microprocessor, two input and two output cards, an AID converter control card, a display control card, two 4K EPROM program storage cards, and a 1K RAM and memory address card (figure 1). Also included in the unit are an AID converter, a 5-c1igit LED display, and a 16-key keyboard. The display automatically sequences through all input channels, displaying the number and temperature of each channel for one second before cycling to the next. The keyboard can be used to halt this sequencing and either make the display continuously monitor only one channel or convert it to a clock-only display that shows time of day. In normal operation, the AID converter receives analog temperature information from as many as 16 thermistors and presents the converted data to the microprocessor. Digital data, such as that produced by switch closures and teletype Signals, can be presented directly to the microprocessor through the 16 digital inputs of the input cards. These data are used to solve the system functional equations and produce two types of microprocessor outputs. In the channel-monitor modes, temperature information is output to the display in degrees Fahrenheit or Celsius, depending upon resident program. In the time-display mode, a timekeeping routine program assumes control of the display Circuitry and the temperature information is not provided. The other microprocessor output consists of control signals that are suitable for opening and closing relays and activating solid state switches. These signals perform such functions as turning on pumps and opening valves to let water run into the storage tank or circulate through radiators. Since program storage is in ROM, power failure does not cause catastrophic loss of memory. When power is restored, a resetting sequence begins, with the controller ensuring that all valves and controls are turned off so that stored energy is not lost. The controller then cycles through all of the inputs, decides what the system operating conditions should be, and generates the necessary output signals. This analysis takes approximately five seconds. To indicate to the user that power has been off, the display flashes until manually reset. Originally designed for use in solar heating applications, the intelligent microprocessor-based controller is applicable to any system in which the ability to deal with multiple sensor inputs and generate control outputs is required. 10-31 II I Fig. 1 Solar Controller Functional Block Diagram } 10-32 CONTROL OUTPUTS HIGH·SPEED DATA ENCRYPTION USING THE F9414 F=AIRCHILD A Schlumberger Company with the exception of the internal ROM table. This approach results in a relatively small die size. INTRODUCTION Until recently, the requirement of secrecy in data communications has been largely limited to military and diplomatic activities. Proprietary business, finanCial, and personal information was seldom transported through hostile environments; when necessary, suitable safeguards were provided by locks and, occasionally, guards. With the advent of solid·state electronics, the extensive use of standard radio links, microwave, commercial, and satellite radio channels, nearly anyone may listen in on masses of sensitive information without being detected. Data throughput of 13.3 MHz (75 ns) per bit can be achieved with a typical power consumption of 500 mW for Vcc and 150 mW at the injector pin, for a total of 650 mW per chip. The F9414 chip set consists of four similar 40-pin devices. A typical connection is shown in figure 1. Figure 2 illustrates the major logic elements of one of the chips, including a pair of data registers, four 8-bit shift (key) registers, control logic, and two 64-bit word by 4-bit read-only memories (ROMs). The F9414 encryption set has passed the NBS functional validation test. Distributed computer systems with interactive terminals have increased effective communication between authorized users, but have also increased the problems of protecting the great quantities of confidential data from access by outsiders. The solution is to make the data somehow incomprehensible to unauthorized access through encryption. The set operates with a 56-bit key word to encipher or decipher a 64-bit data word that is stored in 8 bytes; 2 bits of each byte are distributed to each of the four chips. The key consists of 64 bits in 8 bytes; bit 8 of each byte is parity. Bits 1 through 4 go to both chip 1 and 2; bits 4 through 7 go to chips 3 and 4. The four chips together store the 64-bit plaintext or ciphertext word. In 1977, the National Bureau of Standards adopted the Data Encryption Standard, an encryption algorithm developed by researchers at IBM. The algorithm uses a 56-bit key to map one 64-bit data word into another, and is well-suited to LSI implementation. Accordingly, over the next few years, several semiconductor manufacturers announced LSI devices that perform the data encryption and decryption steps. The chips have separate data inputs and outputs so the block of data to be processed can be input as the previous block is being output. This overlap permits the processing of a 64-bit block in 24 clock pulses, which, at a 5 MHz maximum clock frequency, makes the F9414 substantially the fastest of the present commercially available DES chip implementations. Data throughput of 13.3 MHz (75 ns) per bit or 200 kHz (4.8 I's) per 64-bit word can be achieved. SIGNIFICANT CONCEPTS AND FEATURES OF THE F9414 Fairchild's F9414, a very fast encryption device, is suitable for extremely high bit-rate data communication and data storage applications. As this 4-chip device is aimed primarily at the performance-driven market, it is implemented with bipolar technology, blending lowpower Isoplanar Integrated Injection Logic (I'L ® ) and high-speed TTL, made possible through Fairchild's proprietary isoplanar process. The speed-critical parts of the F9414, including the ROM lookup tables required by the DES algorithm, are TTL for minimum delay, while the control functions are I'L for low power consumption. The TTL outputs ensure high speed and good drive capability. Added advantages of bipolar technology are high radiation resistance and full commercial and military operating temperature range. The key register is capable of hold, left shift (encipher), or right shift (decipher) operations, by one or two pOSitions, as required by each of the 16 rounds of the algorithm. Each device also includes logic for the control of these registers during load and Cipher operations. The 64-bit word by 4-bit ROMs in each device implement the S-boxes of the algorithm. The major differences among the four devices are the masking of the ROM codes and the key bits that are selected as ROM addresses, according to the E-bit selection table of the algorithm. As shown in figure 1, a set of eight output signals (P1.a) and input signals (F 1.a) is interconnected between chips to implement the permutation function, P, of the algorithm. An additional set of outputs, Px and Py, and inputs, Fx and Fy, is used to interconnect the chips as required by columns 1 and 6 of the E-bit selection table. From a manufacturing standpOint, a single-chip approach for the DES results in a chip size undesirably large for economical production of a high-volume device. However, the DES algorithm can be partitioned into a bitslice implementation, yielding devices that are identical, 10-33 F9414 Application Note Figure 1 F9414 4·Chip Encryption Set KEY·IN BYTE DATA·IN BYTE BITS K1, 2, 3, 4 K1, 2, 3, 4 BITS 1, 2, 3, 4 BITS 7, 6, 5, 4 1,2 7,8 5,6 3,4 LSB MSB CLOCK--~--------~--~-4------~--4---+------4r----+---t------, KEY BIT 8 10 ~~?~----~~----~--4---+-----~~-+--------i-i-~--t-~r----t~ SIN SOUT MSB DATA OUT BITS 1,2 5,6 3,4 IMPLEMENTATION OF THE DES ALGORITHM PARITY OUT LSB 7,8 The 28 key bits in the top half, Co' of the key permutation function are duplicated in the key registers of F9414·1 and F9414·2, while key bits in the bottom half, Do, occupy the registers of both the F9414·3 and F9414·4 (see figure 4). In each device, key register 4 holds the last 4 bits of both halves of the key permutation function. Each of the 16 iterations involves a left rotation (encipher) or right rotation (decipher) of the key registers. Initial permutation is accomplished in the F9414 chip set by the manner in which the data is loaded. The DINO input of chip 1 loads bit 1 of each byte, DIN1 of chip 1 loads bit 2 of each byte, DINO of chip 2 loads bit 3 of each byte, etc. After eight clock cycles, the four registers receiving data bits 2, 4, 6, and 8 of each input byte comprise the La block of 32 bits in permuted order within the four devices (see figure 3). The four registers receiving bits 1, 3, 5, and 7 of each byte hold the Ro block. Therefore, each chip slice contains one byte each of the La and Ro blocks. During the key shift schedule, chips 1 and 2 bypass the right half of key register 4, and chips 3 and 4 bypass the left. This results in the key alignment returning to its original position after a total of 28 shifts from the 16 alterations. Further shifting of the bits and extracting outputs from the right end of each byte implements the inverse permutation 1P·1. Each column of the inverse permutation may be found in a register byte and the first 8 bits (40, 8, 48, etc.) required by row 1 of the inverse permutation table are at the output ends of the shift registers. 10·34 F9414 Application Note Figure 2 F9414 Block Diagram Py SOUT S,N D,N , ~n.- Px t I I MUX - 1 I - LEFT DATA D.oUT1 ---, OE 0 SOUT Co Co Co Co CP C, C, C, C, 9414·1 9414·2 9414·3 9414·4 Co C, C2 LSB MSB i TIMING FOR DECIPHER/LOAD DATA CIPHER OUT SET UP FOR FIFO INPUT '(21 ~$s'L- CP LOW I i I I \' NOTES: 1,8 byte initialization vector following LD KEY 2, 9 clock pulses required to complete load data operation 10·40 I F9414 Application Note Figure 8 Cipher Feedback Receiver LSB ...-------'----1-4 PL PL F9423 F9423 TOP Co CP C, SOUT SOUT SoUT SOUT CP CP Co 9414·2 CP CP Co 9414·4 (TO Vee) SOUT Co CP C, Co C, C, 9414·1 Co 9414·3 C, C, Q o Q, 0 0 Q1 C, MSB LSB I TIMING FOR DECIPHER/LOAD DATA DATA OUT SET UP FOR FIFO INPUT I '(2) ~~ , CP Co LOW c, I I ENCIPHERIDECIPHER ,I I (,~!---~~:---~r l. .... - - - - + - - - - - L O A D DATA -------~~i r~----+-----------....jJ ~J---",' I . ;----. I I ENCIPHER/DECIPHER t II I• PERFORM I-----------..jL~!---..1-.... I --"", ,..----XOR I SETUP FOR F9414 "C" INPUT SELECT (S'N) L. NOTES: 1. 8 byte initialization vector following LD KEY 2. 9 clock pulses required to complete load data operation 10-41 F9414 Application Note Cipher Block Chaining with the same initialization data or the first 64 bits of transmission will be incorrectly deciphered. Cipher block chaining (see figure 9) is similar to cipher feedback in that successive transmissions are made dependent on previ.ou~ transmissions, thereby increasing the level of security. The CBC transmitter takes the present 64-bit input vector and exclusive-ORs it with the output of the encryption unit, then performs an encryption and the result. The result of the encryption is transmitted and also exclusive-ORed with the next 64-bit vector, continuing the chaining process. The receiver runs synchronously with the transmitter and recovers the data by performing a< decryption and then an exclusiveOR on the received 64 bits. Internal exclusive-OR gates on the F9414 make implementation of the CBC transmitter especially simple. When SIN is high (figure 10), the exclusive-OR of the D inputs and Q outputs is input to the F9414 register. Since the F9414 can input and output simultaneously, the input data and the F9414 output are exclusive-ORed while the result of the DES iteration is being clocked out at the Q outputs. Therefore, no additional packages are required. SUMMARY The receiver and transmitter must operate in different modes: encrypt and decrypt (see figures 10 and 11). No data buffering is necessary at the transmitter, but the receiver needs a f;l4-bit buffer to store , ~, I- I-- , r.:I ~I i Bi b SF AMPUFlER ~- I r'-' ~ ~ lIIii I III r;;- ~ I , i~ r L ~ - .! <1>. The CCD222 is organized as a matrix array of 488 horizontal lines by 380 vertical columns of charge·coupled photo· elements. The dimensions of these 185,440 photoelements are 12 I'm horizontally by 18 I'm vertically. The photo elements are precisely positioned on 30 I'm horizontal centers and 18 I'm vertical centers. The CCD222 has an active optical area of 8.8 by 11.4 mm, with a diagonal of 14.4 mm. Figure 2 Structural Detail The photosite dimensions of a CCD222 sensor are revealed in this structural detail. Note that photosite separator bar· riers are transparent, and photosltes are optically contigu· ous along the vertical axis. VERTICAL SCAN AXIS HORIZONTAL SCAN AXIS 10'45 II CCO Imaging offers several advantages over "pastgeneration" vacuum tube sensing, including size, 'weight, power, sensitivity and reliability. Equipping an automated process with vision requires interfacing a CCO camera to a computer providing instant, low cost, effective control and intelligence. As usual, there are certain obstacles to be overcome. Some are addressed here utilizing standard components and systems with minor modification. Charge Coupled Devices Fairchild CCD cameras are ideal in many scientific and industrial imaging applications that require a high degree of optical accuracy. Fairchild cameras have been successfully employed in these environments for several years. In part, this is possible because of the precise geometriC pixel alignment and high quality linear video response inherent in each camera through careful circuit and enclosure design techniques. Small, light-weight, and rugged, CCD cameras are well suited for imaging in hostile environments normally too hazardous for traditional vidicon cameras. Charge-Coupled Devices (CCDs) are a family of silicon semiconductor components that operate on a principal called "charge-coupling." Charge-coupling is the collective transfer of mobile electric charge stored within a storage element, to a similar adjacent element by the external manipulation of applied voltages. CCDs are employed as memories, analog signal processors and imagers. CCD image sensors sense a photon-generated charge in an array of depletion regions or potential wells formed by MOS-type capacitors. Then they serially transfer the charge from each element to an output charge detector amplifier, Sensors are classified as Linear Imaging Devices (liDs) or Area Imaging Devices (AIDs), Applications for CCD cameras (some are shown at the end of this, article) include non-contact measurement, product inspection, color sorting, robot guidance, reconnaissance and surveillance. As systems develop and improve, CCDlmaging,applications broaden to include many div,erse areas. The, advantages of CCD cameras for celestial mapping and tracking are widely known and accepted in astronomy. Video data from . scanned x-ray charts are commonly used for computer analysis in medicine. CCD cameras are used as navigational aids for pilots and provide visual information to both ground and airborne flight recording systems. Geological mapping of the earth's resources via satellite is an ongoing space application. Basically, an LID is composed of a row of image,sensing elements (photosites), two analog transport registers, and an output amplifier. Light energy falls on the photosites and generates charge packets proportional to the light intensity. These packets are then transferred in parallel to the analog transport registers and shifted by 2-phase clocks. The charge packets are delivered to an on-chip amplifier and converted to a proportional voltage level. The output, a series of amplitude modulated pulses representing optical information, is called video. Recent software development in the area of artifiCial intelligence has led to "smart" vision systems capable of learned image and pattern recognition. Incorporated as the eyes for robots or automated processes, these systems are playing an ever-increasing role in mechanical assembly, quality control, welding and batch sorting tasks. AIDs are similar to LIDs except that the photosites are arranged in an x-y matrix (Figure 1) with opaque transport registers located between photosite columns (Figure 2). The charge packets are transferred to the output amplifier in two separate fields, line by line. This technique is called interline transfer. Most vision system implementations require at least one field of video data be stored in digital memory in real time for subsequent computer analysis. When imaging at standard TV video rates, fast memory and control circuitry are needed. Additionally, processing algorithms need to acquire stored video data as contiguous sequential video data lines, a difficult job to perform on interlaced video using hardware-based memory storage techniques. The ability to generate, move about and detect discrete packets of electrons fulfills a number of image proceSSing requirements. Characteristically. SOlid-state imaging exhibits features such as unity Gamma, zero lag and no geometric distortion. Conversely, the signal linearity produced by vidicons depends on uncertain analog sweep circuits which are a source of distortion and requires periodic calibration adjustments. Compared to other solid state photosensing arrays. CCDs possess a higher dynamic range (typically 1000:1) and charge transfer efficiency (.9999 typical eTE). 10-A6 Figure 3 Typical Automated Vision Configuration Intelligent Automat/on Fairchild's CCD Imaging Group has demonstrated a Multlbus* binary frame grabber that features the CCD3000 Video Communication Camera for image sensing, a PEP-45 Single-Board Computer as the system controller, and a 32 K byte static RAM multibus memory board for frame storage. A hardware interface, or "data organizer", connects the camera to the PEP-45 parallel input/output port. This system (Figure 3) can perform intelligent image and pattern recognition of high-resolution CCD images. As described, the system performs interlaced binary video frame grabbing with non-interlaced bit-mapped storage. Imaging Fairchild's CCD3000 and CCD4000 cameras are rugged, selfcontained units that take advantage of the geometric accuracy, wide. dynamic range, and reliability of a buriedchannel charge coupled device image sensor. The CCD3000 Video Communications Camera provides a 380 element-perline Interlaced two-flelds-per-frame NTSC composite video signal. The CCD4000 Automation Camera provides video in a non-Interlaced 256-by-256 element square pixel pitch format required for certain automatic inspection, recognition, and robot guidance systems. Camera design makes them ideally suited for intelligent image processing sys· tems typically found in robotic and automated applications. Either camera can be installed as a relatively small Single unit, or separated into a sense head connected to the camera control electronics via cable, Figure 4. Control Several computer interface schemes exist for video cameras. Differences vary depending on th~ particular imago ing application. Binary video is a 1-bit (2-levei) digital representation of analog video relative to some dc threshold voltage. Digitized video usually refers to a two or more bit (multilevel) digital interpretation with respect to a voltage range. In either case, analog·to-digital conversion is required for frame storage. Direct Memory Access (DMA) techniques are often employed to allow video data acquisition in real time. Typically, this means custom-designed hardware for most off-the-shelf computer boards. Commercially available frame grabbers work well for vidicon cameras, but are not always readily adaptable to solid state cameras due to differences in image resolution and pixel data rates. 'Trademarkof Intel Corpclration 10-47 A PEP-45 single-board computer (Figure 5) from Fairchild's Microprocessor Division is used in this system. The PEP-45 uses a 20 MHz F9445 16-bit microprocessor. This board offers high throughput, multi bus capability, and requires only a single + 5 V power supply. System strategy is to first convert the analog signal to binary. Then, by using camera output timing signals, each video line is translated into a series of 24 data words, (See Figure 6). Each data word, consisting of 16 consecutive binary pixels, is fed to the memory mapped input port on the PEP-45 board. Upon reading the word serial-bit parallel video information under program control, the PEP-45 transfers the data over the multibus to memory. RS 170 composite video from the CCD3000 camera consists of 525 horizontal lines in two fields, Figure 7. One field contains every other line of video data (the odd field) and the other field contains the intervening lines of video data (the even field). Generally, image processing routines performed on a stored picture frame are on a line-by-line basis. To facilitate such processing, the video image is stored non-interlaced. Thus, without additional processing, the image can be reconstructed by sequencing through memory. Figure 4 Sense Head Can Be Remote from Control Unit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X X X X X X X X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X X X X X X X X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 6 Non-Interlaced Video Map Figure 5 PEP-45 Single-Board Computer I 525 Ho,lzontal Video Lines . I Ul1lllllllllllmmlmllllllllmlllm~llHmlm11IUlllllllllllllmmIfllllllllllllllllll1TInlllllllllml1lU Odd Field I 1V~ Even Field 380 Picture Elements J"\ ~ ~ An.,og:':.:J~ ~~~ ~... Figure 7 Video Timing 10-48 . -I ~./l ~LCTh'.ShOld Analog Video Shill Register DC Threshold C~~:nok~~: ___ --l Latch Do Through 0" s~~~:Gate Field Index t - - - - - - - - - - Data Ready 1-_________ ~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -------v Data Request Interrupt Request Figure 8 Data Organizer Block Diagram Data Organizer Operation The Data Organizer is used as an interface between the camera and the computer, Figure 8. Composite video from the camera is fed to an operational amplifier in the organizer and compared to a dc threshold voltage from a potentiometer setting to produce Binary Video (BV). The camera's 14.32 MHz master clock is divided in half to derive the video pixel data rate. Composite Blanking, a TIL signal used to indicate valid video, gates the pixel data clock, al· lowing it to function as a shift clock. With the occurrence of each shift clock pulse, binary pixel data is loaded into a serial-in/parallel·out shift register. Pixel data loaded on previous clock pulses is shifted over one bit, and a modul0-16 counter is incremented. A bit·line output from the register is connected to an oscilloscope or to a 75 0 terminated video monitor. This signal provides real-time observation of Binary Video, allowing optimum setting of the comparator threshold. Since the CCD3000 line resolution (380 pixels) is not an even multiple of 16, the last data word in each line must be shifted four places in order to maintain data consistency. The word counter output is compared to a DIP switch set· ting indicating the number of words in each video line. The comparator output resets all counters and logic gates in preparation for the next video line. A buffered Field Index input indicates the start of a new frame (two fields). A reverse video switch connected to the shift register Select input sets the background/object polarity to facilitate image processing in either front-lighted or back-lighted situations. The Word Clock output of the modulo-16 counter latches the shift register outputs, forming the bit·mapped data word every 2.236 ,.s during valid line times. Data Ready is activated by the Word Clock signal when the Data Request signal is present. Data Request is removed after the PEP-45 has successfully read the data word, returning Data Ready to the inactive state, completing a 2-wire handshake cycle. 10-49 • PEP-45 P3 Connector lS08 ........-f<>-PIO Figure 9 Speed Control Modification The PEP-45 Board Because the PEP-45 must acquire and store a video data word in 2.2 ns, instruction times for the image acquisition routine are critical. A minor board modification (Figure 9) was made to insure the fastest possible program execution. The 20 MHz F9445 microprocessor can execute an LOA (Load Accumulator) and a PSHA (Push Accumulator) instruction in 1.4 I'S, leaving 800 ns to cover PEP-45 board and multibus overhead. Replacing the PEP-45 boards 16K words of 2114 NMOS RAM with fast 2148 RAMs for running the camera service routine el iminates the need for extended memory cycles. Polling the status port to determine if the camera data is ready would require an additional instruction. By allowing the Data Ready signal from the data organizer to control the processor's ROYO line when the camera is accessed, video data acquisition time is minimized. Using available gates on the PEP-45 board, the ROYO delay circuit is reconfigured as shown in Figure 9. Signals STo and CM 1 are rem.oved from the P3 connector and replaced by ROYO and Pia respectively. See Table 1. A 32 K byte, 220 ns cycle time static memory card is placed on the IEEE 796 bus and the remaining hardware configured. Once the program is loaded, the system is ready to operate. PEP-45 Board Operation When the processor is interrupted, the image acquisition routine is called. The Stack Pointer, line, and field count registers are initialized. A total of 24 sets of LOA and PSHA instructions are then executed, retaining the first line of bi· nary video in the odd field. During the horizontal blanking period (the time in between valid video lines), the line count is updated. The Stack Pointer is adjusted, leaving enough CCD Data Organizer J5 Connector Signal Pin Signal INO IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 13 14 11 12 9 10 7 8 21 22 19 20 17 18 15 16 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 DO ROYO 5 DATA READY XINT 1 INTERRUPT REQUEST PIO 4 DATA REQUEST Table 1. Data Organizer/PEP-45 Connections memory between the previous and present stack addresses for storage of the first video line from the alternate (even) field. Then, the program returns to acquire the next line of data in the field being acquired and stored (odd field). After the odd field has been collected, the cycle is repeated for the even field with the data acquired interlaced with data already stored from the odd field. Once the total picture frame is stored in memory, the PEP-45 (or any other proces· sor sharing the multi bus) can access the image data, non· interlaced, for further processing. Summary The CC03000/PEP-45 combination demonstrates key capabilities for two diverse Fairchild products - a high· resolution CCO image containing over 180,000 picture ele· ments being captured at NTSC video rates by a fast 16-bit microprocessor board. Superficially, the F9445 microproces· sor performs a mundane role usually aSSigned to hardware logic. However, adept use of the board's powerful instruction set can convert the system function from that of a frame·grabbi ng camera interface to an extremely capable image processor. Additionally, interactive console operation, FS-1 linkage, PEP·BUG and PEp·BASIC readily support more sophisticated application development. Multibus·configured distributed processing schemes with other IEEE-796 masters are feasible. 10-50 I [!] I INTRODUCTION !,;l2 IORDERING AND PACKAGE ~ INFORMATION IC!JIFB MICROCOMPUTER FAMILY 101 \ CONTROLLER FAMILY ~ F6BOO MICROPROCESSOR FAMILY 1 \01F16000 MICROPROCESSOR FAMILY \[!] 1 ROM PRODUCTS [!Q] 1 11 I I APPLICATIONS RESOURCE AND TRAINING CENTE ~ 1SALES OFFICES FAIRCHILD Section 11 Microprocessor Resource and Training Centers A Schlumberger Company Microprocessor Resource Center Karl Kulp 4570 W. 77th Street, Suite 356 Edina, MI 55435 (612) 835·3322 TWX: MINN The Microprocessor Resource Center (MRC) organization was created to serve as yet another, technically oriented, Fairchild customer link to a world-wide support structure that is concerned with all phases of the customer's requirements. Rich Morse 5 Speen Street Framingham, MA (219) 483-6453 TWX: FHAM Every MRC is available to assist the customer in microprocessor hardware and software development and application engineering, product definition, and long-term product strategies. Backed by Fairchild's expertise and extensive resources, the MRC is a tool for solving current problems and planning for future needs. 01701 Gene Price 1570 Brookhollow, Suite 206 Santa Ana, CA 92705 (714) 557·7350 TWX: SANA At each Center is a microprocessor expert who is equally familiar with standard devices and those Fairchild state-ofthe-art products that are on the leading edge of technology. Because they understand the microprocessor market and development trends, these experts provide technical support and planning assistance that can benefit the customer through timely and cost·effective system design and implementation. Microprocessor Education Center As an added convenience, all Microprocessor Division development systems can be demonstrated at the MRCs. This affords the customer an opportunity to assess the perform· ance and applicability of products in an operational-type environment. Education plays a key role in the technical support of a microprocessor user. It is essential to a full understanding of the complexities, capabilities, and applications of modern processor products, and is therefore treated as an important component of the Fairchild Microprocessor Division customer support structure. Training on Fairchild's microprocessor products is available at either the customer or MRC location. This training, which is coordinated by the MRC manager, is performed in con· junction with the Microprocessor Division Education Center. The most recent advances in microprocessor technology are included in the Fairchild Microprocessor Eduction Center courses, which feature a maximum amount of hands-on experience. Indeed, the major thrust of the training courses is to focus on the general techniques of microprocessor usage. This emphasis, it is felt, best prepares the student to apply the available design and development tools to specific applications in an efficient manner. MRC Addresses Jim Gunn 1702 Collins Blvd., Suite 101 Richardson, TX 75081 (214) 234·3391 TWX: DALL The following Education Center course offerings are included . • F8 and F3870 Microprocessor Systems Intended to introduce the student to the Fairchild F8 and F3870 microprocessor systems, this course provides basic knowledge of Fa and F3870 hardware, software, applications, and development aids. Included are laboratory sessions in which the student applies that knowl· Ralph Hayhurst 500 Park Blvd., Suite 575 Itasca, IL 60143 (312) 773-3300 TWX: ROLL 11·3 III Microprocessor Resource and Training Centers edge in practical situations. Among the areas covered are device features and architecture, use of the various registers, machine and assembly language syntax, program writing and debugging, and hands-on use of the PEP 38 and Formulator systems. • F6800 Microprocessor Family This course provides the student basic knowledge of Fairchild F6800 a-bit microprocessor family hardware, software, applications, and development aids. Included are laboratory sessions in which the student applies that knowledge in practical situations. Among the areas covered are device features and architecture, register organization and use, system configurations, program writing and debugging, and hands-on use of the various training and development aids. • F9445 Family Introduction This course is an overview of the Fairchild F9445 16-bit microprocessor and its supporting circuits. Consisting of both lecture and laboratory sessions, with emphasis on hands-on experience, the course covers such areas as F9445 CPU and system timing, software, device features and architecture, and use of the FS-I and EMUTRAC development aids. • F5-1 Development System This course introduces the student to the Fairchild System-I (FS-I) development system, emphasizing handson experience. Included is coverage of operating system usage, utility software usage, high-level languages and their associated compilers and interpreters, and the EMUTRAC emulation and tracking system. • Microprocessor Control and Interface This course is intended to introduce the student to the principles and techniques of microprocessor control and interfaCing. Opportunity is provided for hands-on experimentation with a mini-development system. Included in the course are a review of microprocessor fundamentals, transducer types and applicability, conversion techniques, and parallel and serial formats. • Pascal for Microprocessors An introduction to the high-level Pascal language, this course teaches the student the skills required to produce software in Pascal for many practical applications, in· cluding real-time computing, scientific and engineeringtype problem solving, and data processing. • F16000 Family Introduction Introducing the student to the Fairchild F16000 16-bit microprocessor family, this course Is an overview that consists of both lecture and laboratory sessions. Emphasizing hands-on experience in the laboratory, the course covers such areas as device features and architecture, CPU and system timing, principles of memory management and virtual memory, floating point arithmetiC, and familiarization with design aids. 11·4 [!] 1 1INTRODUCTION ~2 IORDERING AND PACKAGE ~ INFORMATION ru 1 1F8 MICROCOMPUTER FAMILY 1 0 1 CONTROLLER FAMILY 1~IF6800 MICROPROCESSOR FAMILY 101F16000 MICROPROCESSOR FAMILY [!J I 1 ROM PRODUCTS Inlg I DEVELOPMENT SYSTEMS AND L!J SOFTWARE I[!QJ [II] 1 I APPLICATIONS I RESOURCE AND TRAINING CENTERSI A Schlumberger Company Sales Offices United States and Canada Alabama Huntsville Office 500 Wynn Drive, Suite 511 Huntsville, Alabama 35805 Tel: 205-837-8960 Georgia Atlanta Sales Office 3220 Pointe Pkwy, Suite 1200 Norcross, GA 30092 Tel: 404-441-2740 New Jersey New Jersey Office Vreeland Plaza 41 Vreeland Avenue Totowa, New Jersey 07511 Tel: 201-256-9006 Arizona Phoenix Office 2255 West Northern Road, Suite B112 Phoen ix, Arizona 85021 Tel: 602-864-1000 TWX: 910-951-1544 Illinois Itasca Office 500 Park Blvd., Suite 575 Itasca, Illinois 60143 Tel: 312-773-3300 California Los Angeles Office' Crocker Bank Bldg. 15760 Ventura Blvd., Suite 1027 Encino, California 91436 Tel: 213-990-9800 TWX: 910-495-1776 Indiana Indianapolis Office 7202 N. Shadeland, Room 205 Castle Point Indianapolis, Indiana 46250 Tel: 317-849-5412 TWX: 810-260-1793 San Diego Office' 4355 Ruffin Road, Suite 100 San Diego, California 92123 Tel: 714-560-1332 TWX: 910-335-1512 Iowa Cedar Rapids Office 373 Collins Road, NE, Suite 200 Cedar Rapids, Iowa 52402 Tel: 319-395-0090 FAIRCHIL.D Santa Ana Office' 1570 Brookhollow Drive, Suite 206 Santa Ana, California 92705 Tel: 714-557-7350 TWX: 910-595-1109 Santa Clara Office' 3333 Bowers Avenue, Suite 299 Santa Clara, California 95051 Tel: 408-987-9530 TWX: 910-338-0241 Colorado Denver Office 1200 E. Girard Ave., Suite 222, Bldg. B Denver, Colorado 80231 Tel: 303-695-4927 Connecticut Meriden Office 250 Pomeroy Avenue, Suite 202 Meriden, Ct. 06450 Tel: 203-634-8722 Florida Ft. Lauderdale Office 5237 NW. 33rd Ave. Suite 2D Ft. Lauderdale, Florida 33309 Tel: 305-485-7970 TWX: 510-955-4098 Orlando Office' Crane's Roost Office Park 399 Whooping Loop Altamonte Springs, Florida 32701 Tel: 305-834-7000 TWX: 810-850-0152 Kansas Kansas City Office 8600 West 110th Street, Suite 209 Overland Park, Kansas 66210 Tel: 913-649-3974 Maryland Columbia Office 1000 Century Plaza, Suite 225 Columbia, Maryland 21044 Tel: 301-730-1510 TWX: 710-826-9654 Massachusetts Framingham Office 5 Speen Street Framingham, Massachusetts 01701 Tel: 617-872-4900 TWX: 710-380-0599 Michigan Detroit Office' 21999 Farmington Road Farmington Hills, Michigan 48024 Tel: 313-478-7400 TWX: 810-242-2973 Minnesota Minneapolis Office' 4570 West 77th Street, Room 356 Minneapolis, Minnesota 55435 Tel: 612-835-3322 TWX: 910-576-2944 12-3 New Mexico Albuquerque Office North Building 2900 Louisiana N.E. South G2 Albuquerque, New Mexico 87110 Tel: 505-884-5601 TWX: 910-379-6435 New York Fairport Office 815 Ayrault Road Fairport, New York 14450 Tel: 716-223-7700 Hauppauge Office 300 Wheeler Road, Suite 201 Hauppauge, New York 11788 Tel: 516-348-0900 Poughkeepsie Office 19 Davis Avenue Poughkeepsie, New York 12603 Tel: 914-473-5730 TWX: 510-248-0030 North Carolina Raleigh Office 1100 Navaho Drive, Suite 112 Raleigh, North Carolina 27609 Tel: 919-876-9643 Ohio Dayton Office 5045 North Main Street, Suite 105 Dayton, Ohio 45414 Tel: 513-278-8278 TWX: 810-459-1803 Cleveland Office 6133 Rockside Rd., Suite 407 Cleveland, Ohio 44131 Tel: 216-447-9700 Oklahoma Tulsa Office 9810 East 42nd Street, Suite 127 Tulsa, Oklahoma 74145 Tel: 918-627-1591 Oregon Portland Office 8196 SW. Hall Blvd., Suite 328 Beaverton, Oregon 97005 Tel: 503-641-7871 TWX: 910-467-7842 FAIRCHIL..D A Schlumberger Company Sales Offices United States and Canada Pennsylvania Philadelphia Office" 2500 Office Center 2500 Maryland Road Willow Grove, Pennsylvania 19090 Tel: 215-657-2711 Tennessee Knoxville Office Executive Square II 9051 Executive Park Drive, Suite 502 Knoxville, Tennessee 37923 Tel: 615-691-4011 Texas Austin Office 8240 Mopac Expressway, Suite 270 Austin, Texas 78759 Tel: 512-346-3990 Dallas Office 1702 North Collins Street, Suite 101 Richardson, Texas 75081 Tel: 214-234-3391 TWX: 910-867-4757 Houston Office 9896 Bissonnet-2, Suite 470 Houston, Texas 77036 Tel: 713-771-3547 TWX: 910-881-8278 Canada Toronto Regional Office 2375 Steeles Avenue West, Suite 203 Downsview, Ontario, M3J 3A8, Canada Tel: 416-665-5903 TWX: 610-491-1283 12-4 FAIRCHIL.D A Schlumberger Company Fairchild European Design Center SHIRE HALL Shinfield Park Reading, England Tel: 0734752175 Australia Fairchild Austr. Pty. Ltd. Suite 1, First Floor 366 White Horse Road Nunawading, Victoria 3131 Tel: 61-3-8775444 Telex 36496 Austria Fairchild Electronics GmSH Meidlinger Hauplstr. 46 Tel: (0222) 858682/83 Telex 075096 Benelux Fairchild Semiconductor Ruysdaelbaan 35 5613 Ox Eindhoven The Netherlands Tel: 00-31-40-446909 Telex: 00-1451024 Brazil Fairchild Semiconductores Ltda. Caixa Postal 30407 Rua Alagoas, 663 01242 Sao Paulo, Brazil Tel: 66-9092 Telex: 011-23831 Cable: FAIRLEC France FairChild Camera & Instrument S.A. 121, Avenue d'italie 75013 Paris, France Tel: 331-584-5566 Telex: 0042 200614 or 260937 Germany Fairchild Camera and Instrument GmBH Daimlerstrasse 15 8046 Garching Hochbruch Munich, Germany Tel: (089) 320031 Telex: 52 4831 fair d Fairchild Camera and Instrument GmBH Oeltzenstrasse 15 3000 Han nover W. Germany Tel: 0511 17844 Telex: 09 22922 Fairchild Camera and Instrument GmBH Poststrasse 37 7251 Leonberg W. Germany Tel: 07152 41026 Telex: 07 245711 Sales Offices International Hong Kong Fairchild Semiconductor HK Ltd. 135 Hoi Bun Road Kwun Tong Kowloon, Hong Kong Tel: 3-440233 and 3-890271 Telex: HKG-531 Taiwan Fairchild Semiconductor Ltd. Hsietsu Bldg., Room 502 47 Chung Shan North Road Sec. 3 Taipei, Taiwan Tel: 573205 thru 573207 Italy Fairchild Semiconducttori, S.P.A. Via Flamenia Vecchia 653 00191 Roma, Italy Tel: 06 327 4006 Telex: 63046 (FAIR ROM) Fairchild Semiconducttori S.P.A. Viale Corsica 7 20133 Milano, Italy Tel: 296001-5 Telex: 843-330522 Japan Fairchild Japan Corporation Pola Bldg. 1-15-21, Shibuva Shibuya-Ku, Tokyo, 150, Japan Tel: 03 400 8351 Telex: 242173 United Kingdom Fairchild Camera and Instrument Ltd. Semiconductor Division 230 High Street Potters Bar Hertfordshire EN6 5BU England Tel: 0707 51111 Telex: 262835 Fairchild Semiconductor Ltd. 17 Victoria Street Craigshili Livingston West Lothian, Scotland-EH54 5BG Tel: Livingston 0506 32891 Telex: 72629 Fairchild Japan Corporation Yotsubashi Chuo Bldg. 1-4-26, Shinmachi Nishi-Ku, Osaka 550, Japan Tel: 06-541-6138/9 Korea Fairchild Semikor Ltd. K2 219-6 Gari Bong Dong Young Dung Po-Ku Seoul 150-06, Korea Tel: 85-0067 Telex: FAIRKOR 22705 (mailing address) Central P.O. Box 2806 Scandinavia Fairchild Semiconductor AB Svartengsgatan 6 S-11620 Stockholm Sweden Tel: 8-449255 Telex: 17759 Singapore Fairchild Semiconductor Pty. Ltd. No. 11, Lorong 3 Toa Payoh Singapore 12 Tel: 531-066 Telex: FAIRSIN-RS 21376 12-5 • FAIRCHIL.D A Schlumberger Company International Sales Offices 12-6 FA A Sctifumberger Company Fairchild reserves the right to make changes in tha circuitry or specifications at any time without notice. Manufactured under one of the following U.S. patents 29!I1Sn, 3015048, 3064167, 3108359, 3117260: other patents pending. Fairchild cannot assume responsibility for use of any circuitry described other than circuitry embodied in a Fairchild product. No other circuit patent licenses are implied.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:07 14:52-08:00 Modify Date : 2013:08:08 06:31:54-07:00 Metadata Date : 2013:08:08 06:31:54-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:6fcc0165-9ad9-174d-b3d7-cc14f9dd8754 Instance ID : uuid:2c1af90b-fe77-9049-8cee-d880d6e38a7b Page Layout : SinglePage Page Mode : UseNone Page Count : 796EXIF Metadata provided by EXIF.tools